From bfd044a2cb89acd258c63f9d20af132838caa68c Mon Sep 17 00:00:00 2001
From: nzasch <>
Date: Sun, 2 Jul 2023 17:09:41 +0200
Subject: [PATCH] primo commit

---
 README.md                                     |     1 +
 cat.png                                       |   Bin 0 -> 12929 bytes
 cat.svg                                       |    61 +
 squeow_hw/bom/ibom.html                       |  4345 +++
 squeow_hw/fp-info-cache                       |  1947 +
 squeow_hw/jlcpcb.zip                          |   Bin 0 -> 35247 bytes
 squeow_hw/jlcpcb/squeow-B_Cu.gbl              |   285 +
 squeow_hw/jlcpcb/squeow-B_Mask.gbs            |    15 +
 squeow_hw/jlcpcb/squeow-B_Paste.gbp           |    15 +
 squeow_hw/jlcpcb/squeow-B_Silkscreen.gbo      |    16 +
 squeow_hw/jlcpcb/squeow-Edge_Cuts.gm1         |    39 +
 squeow_hw/jlcpcb/squeow-F_Cu.gtl              |  3374 ++
 squeow_hw/jlcpcb/squeow-F_Mask.gts            |   226 +
 squeow_hw/jlcpcb/squeow-F_Paste.gtp           |   218 +
 squeow_hw/jlcpcb/squeow-F_Silkscreen.gto      |  1194 +
 squeow_hw/jlcpcb/squeow-NPTH-drl_map.gbr      |   110 +
 squeow_hw/jlcpcb/squeow-NPTH.drl              |    13 +
 squeow_hw/jlcpcb/squeow-PTH-drl_map.gbr       |   481 +
 squeow_hw/jlcpcb/squeow-PTH.drl               |    32 +
 .../squeow-2022-10-04_134218.zip              |   Bin 0 -> 150971 bytes
 .../squeow-2022-10-04_141706.zip              |   Bin 0 -> 151699 bytes
 .../squeow-2022-10-05_104657.zip              |   Bin 0 -> 77310 bytes
 .../squeow-2022-10-05_140432.zip              |   Bin 0 -> 130374 bytes
 .../squeow-2022-10-05_145900.zip              |   Bin 0 -> 77289 bytes
 .../squeow-2022-10-07_223214.zip              |   Bin 0 -> 77289 bytes
 .../squeow-2022-10-10_123446.zip              |   Bin 0 -> 77365 bytes
 .../squeow-2022-10-10_124608.zip              |   Bin 0 -> 77271 bytes
 .../squeow-2022-10-28_154142.zip              |   Bin 0 -> 77271 bytes
 .../squeow-2022-10-28_192108.zip              |   Bin 0 -> 77271 bytes
 .../squeow-2022-11-11_211649.zip              |   Bin 0 -> 130350 bytes
 .../squeow-2022-11-11_212452.zip              |   Bin 0 -> 77256 bytes
 .../squeow-2022-11-11_214509.zip              |   Bin 0 -> 77256 bytes
 .../squeow-2022-11-13_012818.zip              |   Bin 0 -> 77256 bytes
 .../squeow-2022-11-15_134144.zip              |   Bin 0 -> 77256 bytes
 .../squeow-2022-11-15_134823.zip              |   Bin 0 -> 77256 bytes
 .../squeow-2022-11-18_190348.zip              |   Bin 0 -> 75346 bytes
 .../squeow-2022-11-18_202540.zip              |   Bin 0 -> 97212 bytes
 .../squeow-2023-01-01_011521.zip              |   Bin 0 -> 75731 bytes
 .../squeow-2023-03-15_221901.zip              |   Bin 0 -> 75731 bytes
 .../squeow-2023-06-30_110458.zip              |   Bin 0 -> 75731 bytes
 .../squeow-2023-06-30_111541.zip              |   Bin 0 -> 76188 bytes
 .../squeow-2023-06-30_185236.zip              |   Bin 0 -> 76310 bytes
 .../squeow-2023-06-30_185854.zip              |   Bin 0 -> 76310 bytes
 .../squeow-2023-06-30_201736.zip              |   Bin 0 -> 75092 bytes
 .../squeow-2023-07-01_181420.zip              |   Bin 0 -> 75092 bytes
 squeow_hw/squeow.kicad_pcb                    |  3901 ++
 squeow_hw/squeow.kicad_prl                    |    77 +
 squeow_hw/squeow.kicad_pro                    |   507 +
 squeow_hw/squeow.kicad_sch                    |  3923 ++
 squeow_mod/_autosave-squeow_mod.kicad_pcb     |  2067 +
 squeow_mod/fp-info-cache                      |   435 +
 squeow_mod/squeow_mod-B_Cu.gbr                |   129 +
 squeow_mod/squeow_mod-B_Mask.gbr              |    92 +
 squeow_mod/squeow_mod-B_Paste.gbr             |    15 +
 squeow_mod/squeow_mod-B_Silkscreen.gbr        |    15 +
 squeow_mod/squeow_mod-Edge_Cuts.gbr           |    23 +
 squeow_mod/squeow_mod-F_Cu.gbr                |   719 +
 squeow_mod/squeow_mod-F_Mask.gbr              |   234 +
 squeow_mod/squeow_mod-F_Paste.gbr             |   136 +
 squeow_mod/squeow_mod-F_Silkscreen.gbr        |  1579 +
 squeow_mod/squeow_mod-NPTH.drl                |    23 +
 squeow_mod/squeow_mod-PTH.drl                 |    45 +
 .../squeow_mod-2022-09-13_162503.zip          |   Bin 0 -> 943 bytes
 .../squeow_mod-2022-11-11_220552.zip          |   Bin 0 -> 67058 bytes
 .../squeow_mod-2022-11-11_221817.zip          |   Bin 0 -> 69588 bytes
 .../squeow_mod-2022-11-11_223404.zip          |   Bin 0 -> 74602 bytes
 .../squeow_mod-2022-11-11_224225.zip          |   Bin 0 -> 74715 bytes
 .../squeow_mod-2022-11-11_225139.zip          |   Bin 0 -> 49843 bytes
 .../squeow_mod-2022-11-13_011331.zip          |   Bin 0 -> 78013 bytes
 .../squeow_mod-2022-11-13_012331.zip          |   Bin 0 -> 78414 bytes
 .../squeow_mod-2022-11-13_013833.zip          |   Bin 0 -> 72488 bytes
 .../squeow_mod-2022-11-13_014437.zip          |   Bin 0 -> 72713 bytes
 .../squeow_mod-2022-11-13_015035.zip          |   Bin 0 -> 44173 bytes
 .../squeow_mod-2022-11-15_134056.zip          |   Bin 0 -> 44184 bytes
 .../squeow_mod-2023-03-15_222431.zip          |   Bin 0 -> 44185 bytes
 .../squeow_mod-2023-06-30_111052.zip          |   Bin 0 -> 44185 bytes
 .../squeow_mod-2023-06-30_120439.zip          |   Bin 0 -> 74847 bytes
 .../squeow_mod-2023-06-30_121643.zip          |   Bin 0 -> 74298 bytes
 .../squeow_mod-2023-06-30_151038.zip          |   Bin 0 -> 74038 bytes
 squeow_mod/squeow_mod-job.gbrjob              |   125 +
 squeow_mod/squeow_mod.kicad_pcb               |  1656 +
 squeow_mod/squeow_mod.kicad_prl               |    77 +
 squeow_mod/squeow_mod.kicad_pro               |   454 +
 squeow_mod/squeow_mod.kicad_sch               |  2270 ++
 squeow_sw/.mxproject                          |    14 +
 .../Device/ST/STM32G4xx/Include/stm32g431xx.h | 13139 +++++++
 .../Device/ST/STM32G4xx/Include/stm32g4xx.h   |   259 +
 .../ST/STM32G4xx/Include/system_stm32g4xx.h   |   104 +
 .../CMSIS/Device/ST/STM32G4xx/LICENSE.txt     |     6 +
 squeow_sw/Drivers/CMSIS/Include/cmsis_armcc.h |   894 +
 .../Drivers/CMSIS/Include/cmsis_armclang.h    |  1444 +
 .../CMSIS/Include/cmsis_armclang_ltm.h        |  1891 +
 .../Drivers/CMSIS/Include/cmsis_compiler.h    |   283 +
 squeow_sw/Drivers/CMSIS/Include/cmsis_gcc.h   |  2168 ++
 .../Drivers/CMSIS/Include/cmsis_iccarm.h      |   964 +
 .../Drivers/CMSIS/Include/cmsis_version.h     |    39 +
 .../Drivers/CMSIS/Include/core_armv81mml.h    |  2968 ++
 .../Drivers/CMSIS/Include/core_armv8mbl.h     |  1921 +
 .../Drivers/CMSIS/Include/core_armv8mml.h     |  2835 ++
 squeow_sw/Drivers/CMSIS/Include/core_cm0.h    |   952 +
 .../Drivers/CMSIS/Include/core_cm0plus.h      |  1085 +
 squeow_sw/Drivers/CMSIS/Include/core_cm1.h    |   979 +
 squeow_sw/Drivers/CMSIS/Include/core_cm23.h   |  1996 +
 squeow_sw/Drivers/CMSIS/Include/core_cm3.h    |  1937 +
 squeow_sw/Drivers/CMSIS/Include/core_cm33.h   |  2910 ++
 squeow_sw/Drivers/CMSIS/Include/core_cm35p.h  |  2910 ++
 squeow_sw/Drivers/CMSIS/Include/core_cm4.h    |  2124 ++
 squeow_sw/Drivers/CMSIS/Include/core_cm7.h    |  2725 ++
 squeow_sw/Drivers/CMSIS/Include/core_sc000.h  |  1025 +
 squeow_sw/Drivers/CMSIS/Include/core_sc300.h  |  1912 +
 squeow_sw/Drivers/CMSIS/Include/mpu_armv7.h   |   272 +
 squeow_sw/Drivers/CMSIS/Include/mpu_armv8.h   |   346 +
 squeow_sw/Drivers/CMSIS/Include/tz_context.h  |    70 +
 squeow_sw/Drivers/CMSIS/LICENSE.txt           |   201 +
 .../Inc/Legacy/stm32_hal_legacy.h             |  3912 ++
 .../STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h  |   624 +
 .../Inc/stm32g4xx_hal_adc.h                   |  2034 +
 .../Inc/stm32g4xx_hal_adc_ex.h                |  1393 +
 .../Inc/stm32g4xx_hal_cortex.h                |   419 +
 .../Inc/stm32g4xx_hal_def.h                   |   209 +
 .../Inc/stm32g4xx_hal_dma.h                   |   852 +
 .../Inc/stm32g4xx_hal_dma_ex.h                |   264 +
 .../Inc/stm32g4xx_hal_exti.h                  |   315 +
 .../Inc/stm32g4xx_hal_flash.h                 |  1017 +
 .../Inc/stm32g4xx_hal_flash_ex.h              |    89 +
 .../Inc/stm32g4xx_hal_flash_ramfunc.h         |    74 +
 .../Inc/stm32g4xx_hal_gpio.h                  |   326 +
 .../Inc/stm32g4xx_hal_gpio_ex.h               |   340 +
 .../Inc/stm32g4xx_hal_i2c.h                   |   835 +
 .../Inc/stm32g4xx_hal_i2c_ex.h                |   175 +
 .../Inc/stm32g4xx_hal_pcd.h                   |  1003 +
 .../Inc/stm32g4xx_hal_pcd_ex.h                |    88 +
 .../Inc/stm32g4xx_hal_pwr.h                   |   411 +
 .../Inc/stm32g4xx_hal_pwr_ex.h                |   817 +
 .../Inc/stm32g4xx_hal_rcc.h                   |  3406 ++
 .../Inc/stm32g4xx_hal_rcc_ex.h                |  1606 +
 .../Inc/stm32g4xx_hal_tim.h                   |  2631 ++
 .../Inc/stm32g4xx_hal_tim_ex.h                |  2138 ++
 .../Inc/stm32g4xx_hal_uart.h                  |  1723 +
 .../Inc/stm32g4xx_hal_uart_ex.h               |   651 +
 .../Inc/stm32g4xx_ll_adc.h                    |  8183 ++++
 .../Inc/stm32g4xx_ll_bus.h                    |  1680 +
 .../Inc/stm32g4xx_ll_cortex.h                 |   637 +
 .../Inc/stm32g4xx_ll_crs.h                    |   781 +
 .../Inc/stm32g4xx_ll_dma.h                    |  2578 ++
 .../Inc/stm32g4xx_ll_dmamux.h                 |  2006 +
 .../Inc/stm32g4xx_ll_exti.h                   |  1422 +
 .../Inc/stm32g4xx_ll_gpio.h                   |   994 +
 .../Inc/stm32g4xx_ll_i2c.h                    |  2272 ++
 .../Inc/stm32g4xx_ll_lpuart.h                 |  2650 ++
 .../Inc/stm32g4xx_ll_pwr.h                    |  1602 +
 .../Inc/stm32g4xx_ll_rcc.h                    |  2998 ++
 .../Inc/stm32g4xx_ll_system.h                 |  1516 +
 .../Inc/stm32g4xx_ll_tim.h                    |  6716 ++++
 .../Inc/stm32g4xx_ll_usart.h                  |  4401 +++
 .../Inc/stm32g4xx_ll_usb.h                    |   239 +
 .../Inc/stm32g4xx_ll_utils.h                  |   317 +
 .../Drivers/STM32G4xx_HAL_Driver/LICENSE.txt  |     6 +
 .../STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c  |   772 +
 .../Src/stm32g4xx_hal_adc.c                   |  3682 ++
 .../Src/stm32g4xx_hal_adc_ex.c                |  2373 ++
 .../Src/stm32g4xx_hal_cortex.c                |   517 +
 .../Src/stm32g4xx_hal_dma.c                   |  1110 +
 .../Src/stm32g4xx_hal_dma_ex.c                |   298 +
 .../Src/stm32g4xx_hal_exti.c                  |   639 +
 .../Src/stm32g4xx_hal_flash.c                 |   768 +
 .../Src/stm32g4xx_hal_flash_ex.c              |  1414 +
 .../Src/stm32g4xx_hal_flash_ramfunc.c         |   253 +
 .../Src/stm32g4xx_hal_gpio.c                  |   532 +
 .../Src/stm32g4xx_hal_i2c.c                   |  6884 ++++
 .../Src/stm32g4xx_hal_i2c_ex.c                |   368 +
 .../Src/stm32g4xx_hal_pcd.c                   |  2222 ++
 .../Src/stm32g4xx_hal_pcd_ex.c                |   335 +
 .../Src/stm32g4xx_hal_pwr.c                   |   652 +
 .../Src/stm32g4xx_hal_pwr_ex.c                |  1182 +
 .../Src/stm32g4xx_hal_rcc.c                   |  1401 +
 .../Src/stm32g4xx_hal_rcc_ex.c                |  1825 +
 .../Src/stm32g4xx_hal_tim.c                   |  8108 ++++
 .../Src/stm32g4xx_hal_tim_ex.c                |  3701 ++
 .../Src/stm32g4xx_hal_uart.c                  |  4613 +++
 .../Src/stm32g4xx_hal_uart_ex.c               |  1018 +
 .../Src/stm32g4xx_ll_adc.c                    |  1425 +
 .../Src/stm32g4xx_ll_usb.c                    |   822 +
 squeow_sw/Inc/main.h                          |    87 +
 squeow_sw/Inc/si5351.h                        |    36 +
 squeow_sw/Inc/squeow.h                        |    23 +
 squeow_sw/Inc/stm32g4xx_hal_conf.h            |   380 +
 squeow_sw/Inc/stm32g4xx_it.h                  |    68 +
 squeow_sw/Inc/usb_device.h                    |   103 +
 squeow_sw/Inc/usbd_audio_if.h                 |   137 +
 squeow_sw/Inc/usbd_conf.h                     |   177 +
 squeow_sw/Inc/usbd_desc.h                     |   143 +
 squeow_sw/Makefile                            |   210 +
 .../Class/AUDIO/Inc/usbd_audio.h              |   218 +
 .../Class/AUDIO/Src/usbd_audio.c              |   873 +
 .../Core/Inc/usbd_core.h                      |   158 +
 .../Core/Inc/usbd_ctlreq.h                    |   103 +
 .../Core/Inc/usbd_def.h                       |   420 +
 .../Core/Inc/usbd_ioreq.h                     |   114 +
 .../Core/Src/usbd_core.c                      |   694 +
 .../Core/Src/usbd_ctlreq.c                    |   948 +
 .../Core/Src/usbd_ioreq.c                     |   226 +
 squeow_sw/STM32G431KBTx_FLASH.ld              |   189 +
 squeow_sw/Src/main.c                          |   628 +
 squeow_sw/Src/si5351.c                        |   182 +
 squeow_sw/Src/squeow.c                        |    83 +
 squeow_sw/Src/stm32g4xx_hal_msp.c             |   489 +
 squeow_sw/Src/stm32g4xx_it.c                  |   232 +
 squeow_sw/Src/system_stm32g4xx.c              |   285 +
 squeow_sw/Src/usb_device.c                    |    97 +
 squeow_sw/Src/usbd_audio_if.c                 |   285 +
 squeow_sw/Src/usbd_conf.c                     |   795 +
 squeow_sw/Src/usbd_desc.c                     |   396 +
 squeow_sw/build/main.d                        |    81 +
 squeow_sw/build/main.lst                      |  2832 ++
 squeow_sw/build/main.o                        |   Bin 0 -> 33552 bytes
 squeow_sw/build/si5351.d                      |    75 +
 squeow_sw/build/si5351.lst                    |  1331 +
 squeow_sw/build/si5351.o                      |   Bin 0 -> 19896 bytes
 squeow_sw/build/squeow.d                      |    75 +
 squeow_sw/build/squeow.lst                    |   623 +
 squeow_sw/build/squeow.o                      |   Bin 0 -> 9896 bytes
 squeow_sw/build/squeow_codice.bin             |   Bin 0 -> 33232 bytes
 squeow_sw/build/squeow_codice.elf             |   Bin 0 -> 671888 bytes
 squeow_sw/build/squeow_codice.hex             |  2083 ++
 squeow_sw/build/squeow_codice.map             |  4659 +++
 squeow_sw/build/startup_stm32g431xx.d         |     1 +
 squeow_sw/build/startup_stm32g431xx.o         |   Bin 0 -> 6716 bytes
 squeow_sw/build/stm32g4xx_hal.d               |    73 +
 squeow_sw/build/stm32g4xx_hal.lst             |  2204 ++
 squeow_sw/build/stm32g4xx_hal.o               |   Bin 0 -> 24220 bytes
 squeow_sw/build/stm32g4xx_hal_adc.d           |    74 +
 squeow_sw/build/stm32g4xx_hal_adc.lst         | 22275 +++++++++++
 squeow_sw/build/stm32g4xx_hal_adc.o           |   Bin 0 -> 78924 bytes
 squeow_sw/build/stm32g4xx_hal_adc_ex.d        |    74 +
 squeow_sw/build/stm32g4xx_hal_adc_ex.lst      | 17638 +++++++++
 squeow_sw/build/stm32g4xx_hal_adc_ex.o        |   Bin 0 -> 71060 bytes
 squeow_sw/build/stm32g4xx_hal_cortex.d        |    74 +
 squeow_sw/build/stm32g4xx_hal_cortex.lst      |  5185 +++
 squeow_sw/build/stm32g4xx_hal_cortex.o        |   Bin 0 -> 25756 bytes
 squeow_sw/build/stm32g4xx_hal_dma.d           |    74 +
 squeow_sw/build/stm32g4xx_hal_dma.lst         |  3886 ++
 squeow_sw/build/stm32g4xx_hal_dma.o           |   Bin 0 -> 22552 bytes
 squeow_sw/build/stm32g4xx_hal_dma_ex.d        |    74 +
 squeow_sw/build/stm32g4xx_hal_dma_ex.lst      |  1981 +
 squeow_sw/build/stm32g4xx_hal_dma_ex.o        |   Bin 0 -> 10736 bytes
 squeow_sw/build/stm32g4xx_hal_exti.d          |    74 +
 squeow_sw/build/stm32g4xx_hal_exti.lst        |  1855 +
 squeow_sw/build/stm32g4xx_hal_exti.o          |   Bin 0 -> 16980 bytes
 squeow_sw/build/stm32g4xx_hal_flash.d         |    74 +
 squeow_sw/build/stm32g4xx_hal_flash.lst       |  3454 ++
 squeow_sw/build/stm32g4xx_hal_flash.o         |   Bin 0 -> 18448 bytes
 squeow_sw/build/stm32g4xx_hal_flash_ex.d      |    74 +
 squeow_sw/build/stm32g4xx_hal_flash_ex.lst    |  4194 +++
 squeow_sw/build/stm32g4xx_hal_flash_ex.o      |   Bin 0 -> 25116 bytes
 squeow_sw/build/stm32g4xx_hal_flash_ramfunc.d |    74 +
 .../build/stm32g4xx_hal_flash_ramfunc.lst     |   236 +
 squeow_sw/build/stm32g4xx_hal_flash_ramfunc.o |   Bin 0 -> 3964 bytes
 squeow_sw/build/stm32g4xx_hal_gpio.d          |    74 +
 squeow_sw/build/stm32g4xx_hal_gpio.lst        |  1691 +
 squeow_sw/build/stm32g4xx_hal_gpio.o          |   Bin 0 -> 13744 bytes
 squeow_sw/build/stm32g4xx_hal_i2c.d           |    74 +
 squeow_sw/build/stm32g4xx_hal_i2c.lst         | 25797 +++++++++++++
 squeow_sw/build/stm32g4xx_hal_i2c.o           |   Bin 0 -> 135312 bytes
 squeow_sw/build/stm32g4xx_hal_i2c_ex.d        |    74 +
 squeow_sw/build/stm32g4xx_hal_i2c_ex.lst      |   925 +
 squeow_sw/build/stm32g4xx_hal_i2c_ex.o        |   Bin 0 -> 13644 bytes
 squeow_sw/build/stm32g4xx_hal_msp.d           |    74 +
 squeow_sw/build/stm32g4xx_hal_msp.lst         |  1953 +
 squeow_sw/build/stm32g4xx_hal_msp.o           |   Bin 0 -> 30676 bytes
 squeow_sw/build/stm32g4xx_hal_pcd.d           |    74 +
 squeow_sw/build/stm32g4xx_hal_pcd.lst         |  7846 ++++
 squeow_sw/build/stm32g4xx_hal_pcd.o           |   Bin 0 -> 51184 bytes
 squeow_sw/build/stm32g4xx_hal_pcd_ex.d        |    74 +
 squeow_sw/build/stm32g4xx_hal_pcd_ex.lst      |   970 +
 squeow_sw/build/stm32g4xx_hal_pcd_ex.o        |   Bin 0 -> 13200 bytes
 squeow_sw/build/stm32g4xx_hal_pwr.d           |    74 +
 squeow_sw/build/stm32g4xx_hal_pwr.lst         |  1406 +
 squeow_sw/build/stm32g4xx_hal_pwr.o           |   Bin 0 -> 14356 bytes
 squeow_sw/build/stm32g4xx_hal_pwr_ex.d        |    74 +
 squeow_sw/build/stm32g4xx_hal_pwr_ex.lst      |  3933 ++
 squeow_sw/build/stm32g4xx_hal_pwr_ex.o        |   Bin 0 -> 27596 bytes
 squeow_sw/build/stm32g4xx_hal_rcc.d           |    74 +
 squeow_sw/build/stm32g4xx_hal_rcc.lst         |  5028 +++
 squeow_sw/build/stm32g4xx_hal_rcc.o           |   Bin 0 -> 27248 bytes
 squeow_sw/build/stm32g4xx_hal_rcc_ex.d        |    74 +
 squeow_sw/build/stm32g4xx_hal_rcc_ex.lst      |  5781 +++
 squeow_sw/build/stm32g4xx_hal_rcc_ex.o        |   Bin 0 -> 35292 bytes
 squeow_sw/build/stm32g4xx_hal_tim.d           |    74 +
 squeow_sw/build/stm32g4xx_hal_tim.lst         | 31027 ++++++++++++++++
 squeow_sw/build/stm32g4xx_hal_tim.o           |   Bin 0 -> 165112 bytes
 squeow_sw/build/stm32g4xx_hal_tim_ex.d        |    74 +
 squeow_sw/build/stm32g4xx_hal_tim_ex.lst      | 14004 +++++++
 squeow_sw/build/stm32g4xx_hal_tim_ex.o        |   Bin 0 -> 87236 bytes
 squeow_sw/build/stm32g4xx_hal_uart.d          |    74 +
 squeow_sw/build/stm32g4xx_hal_uart.lst        | 24070 ++++++++++++
 squeow_sw/build/stm32g4xx_hal_uart.o          |   Bin 0 -> 158440 bytes
 squeow_sw/build/stm32g4xx_hal_uart_ex.d       |    74 +
 squeow_sw/build/stm32g4xx_hal_uart_ex.lst     |  4750 +++
 squeow_sw/build/stm32g4xx_hal_uart_ex.o       |   Bin 0 -> 30860 bytes
 squeow_sw/build/stm32g4xx_it.d                |    76 +
 squeow_sw/build/stm32g4xx_it.lst              |   563 +
 squeow_sw/build/stm32g4xx_it.o                |   Bin 0 -> 14592 bytes
 squeow_sw/build/stm32g4xx_ll_adc.d            |     2 +
 squeow_sw/build/stm32g4xx_ll_adc.lst          |    30 +
 squeow_sw/build/stm32g4xx_ll_adc.o            |   Bin 0 -> 1116 bytes
 squeow_sw/build/stm32g4xx_ll_usb.d            |    74 +
 squeow_sw/build/stm32g4xx_ll_usb.lst          |  5711 +++
 squeow_sw/build/stm32g4xx_ll_usb.o            |   Bin 0 -> 44576 bytes
 squeow_sw/build/system_stm32g4xx.d            |    73 +
 squeow_sw/build/system_stm32g4xx.lst          |   570 +
 squeow_sw/build/system_stm32g4xx.o            |   Bin 0 -> 6984 bytes
 squeow_sw/build/usb_device.d                  |    96 +
 squeow_sw/build/usb_device.lst                |   245 +
 squeow_sw/build/usb_device.o                  |   Bin 0 -> 8068 bytes
 squeow_sw/build/usbd_audio.d                  |    89 +
 squeow_sw/build/usbd_audio.lst                |  2657 ++
 squeow_sw/build/usbd_audio.o                  |   Bin 0 -> 26716 bytes
 squeow_sw/build/usbd_audio_if.d               |    87 +
 squeow_sw/build/usbd_audio_if.lst             |   588 +
 squeow_sw/build/usbd_audio_if.o               |   Bin 0 -> 11388 bytes
 squeow_sw/build/usbd_conf.d                   |    91 +
 squeow_sw/build/usbd_conf.lst                 |  2810 ++
 squeow_sw/build/usbd_conf.o                   |   Bin 0 -> 45340 bytes
 squeow_sw/build/usbd_core.d                   |    85 +
 squeow_sw/build/usbd_core.lst                 |  2360 ++
 squeow_sw/build/usbd_core.o                   |   Bin 0 -> 26720 bytes
 squeow_sw/build/usbd_ctlreq.d                 |    87 +
 squeow_sw/build/usbd_ctlreq.lst               |  4356 +++
 squeow_sw/build/usbd_ctlreq.o                 |   Bin 0 -> 35728 bytes
 squeow_sw/build/usbd_desc.d                   |    88 +
 squeow_sw/build/usbd_desc.lst                 |  1131 +
 squeow_sw/build/usbd_desc.o                   |   Bin 0 -> 13676 bytes
 squeow_sw/build/usbd_ioreq.d                  |    85 +
 squeow_sw/build/usbd_ioreq.lst                |   549 +
 squeow_sw/build/usbd_ioreq.o                  |   Bin 0 -> 12060 bytes
 squeow_sw/squeow_codice.ioc                   |   288 +
 squeow_sw/startup_stm32g431xx.s               |   497 +
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 create mode 100644 README.md
 create mode 100644 cat.png
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 create mode 100644 squeow_hw/jlcpcb/squeow-B_Silkscreen.gbo
 create mode 100644 squeow_hw/jlcpcb/squeow-Edge_Cuts.gm1
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 create mode 100644 squeow_hw/squeow-backups/squeow-2022-10-04_134218.zip
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 create mode 100644 squeow_mod/squeow_mod-backups/squeow_mod-2022-09-13_162503.zip
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 create mode 100644 squeow_mod/squeow_mod-job.gbrjob
 create mode 100644 squeow_mod/squeow_mod.kicad_pcb
 create mode 100644 squeow_mod/squeow_mod.kicad_prl
 create mode 100644 squeow_mod/squeow_mod.kicad_pro
 create mode 100644 squeow_mod/squeow_mod.kicad_sch
 create mode 100644 squeow_sw/.mxproject
 create mode 100644 squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h
 create mode 100644 squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h
 create mode 100644 squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h
 create mode 100644 squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/LICENSE.txt
 create mode 100644 squeow_sw/Drivers/CMSIS/Include/cmsis_armcc.h
 create mode 100644 squeow_sw/Drivers/CMSIS/Include/cmsis_armclang.h
 create mode 100644 squeow_sw/Drivers/CMSIS/Include/cmsis_armclang_ltm.h
 create mode 100644 squeow_sw/Drivers/CMSIS/Include/cmsis_compiler.h
 create mode 100644 squeow_sw/Drivers/CMSIS/Include/cmsis_gcc.h
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 create mode 100644 squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h
 create mode 100644 squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h
 create mode 100644 squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h
 create mode 100644 squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h
 create mode 100644 squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h
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diff --git a/README.md b/README.md
new file mode 100644
index 0000000..7e843e0
--- /dev/null
+++ b/README.md
@@ -0,0 +1 @@
+Trasmettitore in modulazione di ampiezza
\ No newline at end of file
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+		c-0.266,4.467,3.148,8.295,7.612,8.559c0.158,0.005,0.319,0.011,0.475,0.011c4.261,0,7.831-3.328,8.079-7.631l0.654-11.254h5.982
+		c4.472,0,8.1-3.622,8.1-8.1S198.606,218.562,194.134,218.562z"/>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+<g>
+</g>
+</svg>
diff --git a/squeow_hw/bom/ibom.html b/squeow_hw/bom/ibom.html
new file mode 100644
index 0000000..6836d76
--- /dev/null
+++ b/squeow_hw/bom/ibom.html
@@ -0,0 +1,4345 @@
+<!DOCTYPE html>
+<html lang="en">
+
+<head>
+  <meta charset="UTF-8">
+  <meta name="viewport" content="width=device-width, initial-scale=1.0">
+  <title>Interactive BOM for KiCAD</title>
+  <style type="text/css">
+:root {
+  --pcb-edge-color: black;
+  --pad-color: #878787;
+  --pad-hole-color: #CCCCCC;
+  --pad-color-highlight: #D04040;
+  --pad-color-highlight-both: #D0D040;
+  --pad-color-highlight-marked: #44a344;
+  --pin1-outline-color: #ffb629;
+  --pin1-outline-color-highlight: #ffb629;
+  --pin1-outline-color-highlight-both: #fcbb39;
+  --pin1-outline-color-highlight-marked: #fdbe41;
+  --silkscreen-edge-color: #aa4;
+  --silkscreen-polygon-color: #4aa;
+  --silkscreen-text-color: #4aa;
+  --fabrication-edge-color: #907651;
+  --fabrication-polygon-color: #907651;
+  --fabrication-text-color: #a27c24;
+  --track-color: #def5f1;
+  --track-color-highlight: #D04040;
+  --zone-color: #def5f1;
+  --zone-color-highlight: #d0404080;
+}
+
+html,
+body {
+  margin: 0px;
+  height: 100%;
+  font-family: Verdana, sans-serif;
+}
+
+.dark.topmostdiv {
+  --pcb-edge-color: #eee;
+  --pad-color: #808080;
+  --pin1-outline-color: #ffa800;
+  --pin1-outline-color-highlight: #ccff00;
+  --track-color: #42524f;
+  --zone-color: #42524f;
+  background-color: #252c30;
+  color: #eee;
+}
+
+button {
+  background-color: #eee;
+  border: 1px solid #888;
+  color: black;
+  height: 44px;
+  width: 44px;
+  text-align: center;
+  text-decoration: none;
+  display: inline-block;
+  font-size: 14px;
+  font-weight: bolder;
+}
+
+.dark button {
+  /* This will be inverted */
+  background-color: #c3b7b5;
+}
+
+button.depressed {
+  background-color: #0a0;
+  color: white;
+}
+
+.dark button.depressed {
+  /* This will be inverted */
+  background-color: #b3b;
+}
+
+button:focus {
+  outline: 0;
+}
+
+button#tb-btn {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' viewBox='0 0 8.47 8.47'%3E%3Crect transform='translate(0 -288.53)' ry='1.17' y='288.8' x='.27' height='7.94' width='7.94' fill='%23f9f9f9'/%3E%3Cg transform='translate(0 -288.53)'%3E%3Crect width='7.94' height='7.94' x='.27' y='288.8' ry='1.17' fill='none' stroke='%23000' stroke-width='.4' stroke-linejoin='round'/%3E%3Cpath d='M1.32 290.12h5.82M1.32 291.45h5.82' fill='none' stroke='%23000' stroke-width='.4'/%3E%3Cpath d='M4.37 292.5v4.23M.26 292.63H8.2' fill='none' stroke='%23000' stroke-width='.3'/%3E%3Ctext font-weight='700' font-size='3.17' font-family='sans-serif'%3E%3Ctspan x='1.35' y='295.73'%3EF%3C/tspan%3E%3Ctspan x='5.03' y='295.68'%3EB%3C/tspan%3E%3C/text%3E%3C/g%3E%3C/svg%3E%0A");
+}
+
+button#lr-btn {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' viewBox='0 0 8.47 8.47'%3E%3Crect transform='translate(0 -288.53)' ry='1.17' y='288.8' x='.27' height='7.94' width='7.94' fill='%23f9f9f9'/%3E%3Cg transform='translate(0 -288.53)'%3E%3Crect width='7.94' height='7.94' x='.27' y='288.8' ry='1.17' fill='none' stroke='%23000' stroke-width='.4' stroke-linejoin='round'/%3E%3Cpath d='M1.06 290.12H3.7m-2.64 1.33H3.7m-2.64 1.32H3.7m-2.64 1.3H3.7m-2.64 1.33H3.7' fill='none' stroke='%23000' stroke-width='.4'/%3E%3Cpath d='M4.37 288.8v7.94m0-4.11h3.96' fill='none' stroke='%23000' stroke-width='.3'/%3E%3Ctext font-weight='700' font-size='3.17' font-family='sans-serif'%3E%3Ctspan x='5.11' y='291.96'%3EF%3C/tspan%3E%3Ctspan x='5.03' y='295.68'%3EB%3C/tspan%3E%3C/text%3E%3C/g%3E%3C/svg%3E%0A");
+}
+
+button#bom-btn {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' viewBox='0 0 8.47 8.47'%3E%3Crect transform='translate(0 -288.53)' ry='1.17' y='288.8' x='.27' height='7.94' width='7.94' fill='%23f9f9f9'/%3E%3Cg transform='translate(0 -288.53)' fill='none' stroke='%23000' stroke-width='.4'%3E%3Crect width='7.94' height='7.94' x='.27' y='288.8' ry='1.17' stroke-linejoin='round'/%3E%3Cpath d='M1.59 290.12h5.29M1.59 291.45h5.33M1.59 292.75h5.33M1.59 294.09h5.33M1.59 295.41h5.33'/%3E%3C/g%3E%3C/svg%3E");
+}
+
+button#bom-grouped-btn {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='32' height='32'%3E%3Cg stroke='%23000' stroke-linejoin='round' class='layer'%3E%3Crect width='29' height='29' x='1.5' y='1.5' stroke-width='2' fill='%23fff' rx='5' ry='5'/%3E%3Cpath stroke-linecap='square' stroke-width='2' d='M6 10h4m4 0h5m4 0h3M6.1 22h3m3.9 0h5m4 0h4m-16-8h4m4 0h4'/%3E%3Cpath stroke-linecap='null' d='M5 17.5h22M5 26.6h22M5 5.5h22'/%3E%3C/g%3E%3C/svg%3E");
+}
+
+button#bom-ungrouped-btn {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='32' height='32'%3E%3Cg stroke='%23000' stroke-linejoin='round' class='layer'%3E%3Crect width='29' height='29' x='1.5' y='1.5' stroke-width='2' fill='%23fff' rx='5' ry='5'/%3E%3Cpath stroke-linecap='square' stroke-width='2' d='M6 10h4m-4 8h3m-3 8h4'/%3E%3Cpath stroke-linecap='null' d='M5 13.5h22m-22 8h22M5 5.5h22'/%3E%3C/g%3E%3C/svg%3E");
+}
+
+button#bom-netlist-btn {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='32' height='32'%3E%3Cg fill='none' stroke='%23000' class='layer'%3E%3Crect width='29' height='29' x='1.5' y='1.5' stroke-width='2' fill='%23fff' rx='5' ry='5'/%3E%3Cpath stroke-width='2' d='M6 26l6-6v-8m13.8-6.3l-6 6v8'/%3E%3Ccircle cx='11.8' cy='9.5' r='2.8' stroke-width='2'/%3E%3Ccircle cx='19.8' cy='22.8' r='2.8' stroke-width='2'/%3E%3C/g%3E%3C/svg%3E");
+}
+
+button#copy {
+  background-image: url("data:image/svg+xml,%3Csvg height='48' viewBox='0 0 48 48' width='48' xmlns='http://www.w3.org/2000/svg'%3E%3Cpath d='M0 0h48v48h-48z' fill='none'/%3E%3Cpath d='M32 2h-24c-2.21 0-4 1.79-4 4v28h4v-28h24v-4zm6 8h-22c-2.21 0-4 1.79-4 4v28c0 2.21 1.79 4 4 4h22c2.21 0 4-1.79 4-4v-28c0-2.21-1.79-4-4-4zm0 32h-22v-28h22v28z'/%3E%3C/svg%3E");
+  background-position: 6px 6px;
+  background-repeat: no-repeat;
+  background-size: 26px 26px;
+  border-radius: 6px;
+  height: 40px;
+  width: 40px;
+  margin: 10px 5px;
+}
+
+button#copy:active {
+  box-shadow: inset 0px 0px 5px #6c6c6c;
+}
+
+textarea.clipboard-temp {
+  position: fixed;
+  top: 0;
+  left: 0;
+  width: 2em;
+  height: 2em;
+  padding: 0;
+  border: None;
+  outline: None;
+  box-shadow: None;
+  background: transparent;
+}
+
+.left-most-button {
+  border-right: 0;
+  border-top-left-radius: 6px;
+  border-bottom-left-radius: 6px;
+}
+
+.middle-button {
+  border-right: 0;
+}
+
+.right-most-button {
+  border-top-right-radius: 6px;
+  border-bottom-right-radius: 6px;
+}
+
+.button-container {
+  font-size: 0;
+  margin: 10px 10px 10px 0px;
+}
+
+.dark .button-container {
+  filter: invert(1);
+}
+
+.button-container button {
+  background-size: 32px 32px;
+  background-position: 5px 5px;
+  background-repeat: no-repeat;
+}
+
+@media print {
+  .hideonprint {
+    display: none;
+  }
+}
+
+canvas {
+  cursor: crosshair;
+}
+
+canvas:active {
+  cursor: grabbing;
+}
+
+.fileinfo {
+  width: 100%;
+  max-width: 1000px;
+  border: none;
+  padding: 5px;
+}
+
+.fileinfo .title {
+  font-size: 20pt;
+  font-weight: bold;
+}
+
+.fileinfo td {
+  overflow: hidden;
+  white-space: nowrap;
+  max-width: 1px;
+  width: 50%;
+  text-overflow: ellipsis;
+}
+
+.bom {
+  border-collapse: collapse;
+  font-family: Consolas, "DejaVu Sans Mono", Monaco, monospace;
+  font-size: 10pt;
+  table-layout: fixed;
+  width: 100%;
+  margin-top: 1px;
+  position: relative;
+}
+
+.bom th,
+.bom td {
+  border: 1px solid black;
+  padding: 5px;
+  word-wrap: break-word;
+  text-align: center;
+  position: relative;
+}
+
+.dark .bom th,
+.dark .bom td {
+  border: 1px solid #777;
+}
+
+.bom th {
+  background-color: #CCCCCC;
+  background-clip: padding-box;
+}
+
+.dark .bom th {
+  background-color: #3b4749;
+}
+
+.bom tr.highlighted:nth-child(n) {
+  background-color: #cfc;
+}
+
+.dark .bom tr.highlighted:nth-child(n) {
+  background-color: #226022;
+}
+
+.bom tr:nth-child(even) {
+  background-color: #f2f2f2;
+}
+
+.dark .bom tr:nth-child(even) {
+  background-color: #313b40;
+}
+
+.bom tr.checked {
+  color: #1cb53d;
+}
+
+.dark .bom tr.checked {
+  color: #2cce54;
+}
+
+.bom tr {
+  transition: background-color 0.2s;
+}
+
+.bom .numCol {
+  width: 30px;
+}
+
+.bom .value {
+  width: 15%;
+}
+
+.bom .quantity {
+  width: 65px;
+}
+
+.bom th .sortmark {
+  position: absolute;
+  right: 1px;
+  top: 1px;
+  margin-top: -5px;
+  border-width: 5px;
+  border-style: solid;
+  border-color: transparent transparent #221 transparent;
+  transform-origin: 50% 85%;
+  transition: opacity 0.2s, transform 0.4s;
+}
+
+.dark .bom th .sortmark {
+  filter: invert(1);
+}
+
+.bom th .sortmark.none {
+  opacity: 0;
+}
+
+.bom th .sortmark.desc {
+  transform: rotate(180deg);
+}
+
+.bom th:hover .sortmark.none {
+  opacity: 0.5;
+}
+
+.bom .bom-checkbox {
+  width: 30px;
+  position: relative;
+  user-select: none;
+  -moz-user-select: none;
+}
+
+.bom .bom-checkbox:before {
+  content: "";
+  position: absolute;
+  border-width: 15px;
+  border-style: solid;
+  border-color: #51829f transparent transparent transparent;
+  visibility: hidden;
+  top: -15px;
+}
+
+.bom .bom-checkbox:after {
+  content: "Double click to set/unset all";
+  position: absolute;
+  color: white;
+  top: -35px;
+  left: -26px;
+  background: #51829f;
+  padding: 5px 15px;
+  border-radius: 8px;
+  white-space: nowrap;
+  visibility: hidden;
+}
+
+.bom .bom-checkbox:hover:before,
+.bom .bom-checkbox:hover:after {
+  visibility: visible;
+  transition: visibility 0.2s linear 1s;
+}
+
+.split {
+  -webkit-box-sizing: border-box;
+  -moz-box-sizing: border-box;
+  box-sizing: border-box;
+  overflow-y: auto;
+  overflow-x: hidden;
+  background-color: inherit;
+}
+
+.split.split-horizontal,
+.gutter.gutter-horizontal {
+  height: 100%;
+  float: left;
+}
+
+.gutter {
+  background-color: #ddd;
+  background-repeat: no-repeat;
+  background-position: 50%;
+  transition: background-color 0.3s;
+}
+
+.dark .gutter {
+  background-color: #777;
+}
+
+.gutter.gutter-horizontal {
+  background-image: url('data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAUAAAAeCAYAAADkftS9AAAAIklEQVQoU2M4c+bMfxAGAgYYmwGrIIiDjrELjpo5aiZeMwF+yNnOs5KSvgAAAABJRU5ErkJggg==');
+  cursor: ew-resize;
+  width: 5px;
+}
+
+.gutter.gutter-vertical {
+  background-image: url('data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAB4AAAAFAQMAAABo7865AAAABlBMVEVHcEzMzMzyAv2sAAAAAXRSTlMAQObYZgAAABBJREFUeF5jOAMEEAIEEFwAn3kMwcB6I2AAAAAASUVORK5CYII=');
+  cursor: ns-resize;
+  height: 5px;
+}
+
+.searchbox {
+  float: left;
+  height: 40px;
+  margin: 10px 5px;
+  padding: 12px 32px;
+  font-family: Consolas, "DejaVu Sans Mono", Monaco, monospace;
+  font-size: 18px;
+  box-sizing: border-box;
+  border: 1px solid #888;
+  border-radius: 6px;
+  outline: none;
+  background-color: #eee;
+  transition: background-color 0.2s, border 0.2s;
+  background-image: url('data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAABNklEQVQ4T8XSMUvDQBQH8P/LElFa/AIZHcTBQSz0I/gFstTBRR2KUC4ldDxw7h0Bl3RRUATxi4iiODgoiLNrbQYp5J6cpJJqomkX33Z37/14d/dIa33MzDuYI4johOI4XhyNRteO46zNYjDzAxE1yBZprVeZ+QbAUhXEGJMA2Ox2u4+fQIa0mPmsCgCgJYQ4t7lfgF0opQYAdv9ABkKI/UnOFCClXKjX61cA1osQY8x9kiRNKeV7IWA3oyhaSdP0FkAtjxhj3hzH2RBCPOf3pzqYHCilfAAX+URm9oMguPzeWSGQvUcMYC8rOBJCHBRdqxTo9/vbRHRqi8bj8XKv1xvODbiuW2u32/bvf0SlDv4XYOY7z/Mavu+nM1+BmQ+NMc0wDF/LprP0DbTWW0T00ul0nn4b7Q87+X4Qmfiq2wAAAABJRU5ErkJggg==');
+  background-position: 10px 10px;
+  background-repeat: no-repeat;
+}
+
+.dark .searchbox {
+  background-color: #111;
+  color: #eee;
+}
+
+.searchbox::placeholder {
+  color: #ccc;
+}
+
+.dark .searchbox::placeholder {
+  color: #666;
+}
+
+.filter {
+  width: calc(60% - 64px);
+}
+
+.reflookup {
+  width: calc(40% - 10px);
+}
+
+input[type=text]:focus {
+  background-color: white;
+  border: 1px solid #333;
+}
+
+.dark input[type=text]:focus {
+  background-color: #333;
+  border: 1px solid #ccc;
+}
+
+mark.highlight {
+  background-color: #5050ff;
+  color: #fff;
+  padding: 2px;
+  border-radius: 6px;
+}
+
+.dark mark.highlight {
+  background-color: #76a6da;
+  color: #111;
+}
+
+.menubtn {
+  background-color: white;
+  border: none;
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='36' height='36' viewBox='0 0 20 20'%3E%3Cpath fill='none' d='M0 0h20v20H0V0z'/%3E%3Cpath d='M15.95 10.78c.03-.25.05-.51.05-.78s-.02-.53-.06-.78l1.69-1.32c.15-.12.19-.34.1-.51l-1.6-2.77c-.1-.18-.31-.24-.49-.18l-1.99.8c-.42-.32-.86-.58-1.35-.78L12 2.34c-.03-.2-.2-.34-.4-.34H8.4c-.2 0-.36.14-.39.34l-.3 2.12c-.49.2-.94.47-1.35.78l-1.99-.8c-.18-.07-.39 0-.49.18l-1.6 2.77c-.1.18-.06.39.1.51l1.69 1.32c-.04.25-.07.52-.07.78s.02.53.06.78L2.37 12.1c-.15.12-.19.34-.1.51l1.6 2.77c.1.18.31.24.49.18l1.99-.8c.42.32.86.58 1.35.78l.3 2.12c.04.2.2.34.4.34h3.2c.2 0 .37-.14.39-.34l.3-2.12c.49-.2.94-.47 1.35-.78l1.99.8c.18.07.39 0 .49-.18l1.6-2.77c.1-.18.06-.39-.1-.51l-1.67-1.32zM10 13c-1.65 0-3-1.35-3-3s1.35-3 3-3 3 1.35 3 3-1.35 3-3 3z'/%3E%3C/svg%3E%0A");
+  background-position: center;
+  background-repeat: no-repeat;
+}
+
+.statsbtn {
+  background-color: white;
+  border: none;
+  background-image: url("data:image/svg+xml,%3Csvg width='36' height='36' xmlns='http://www.w3.org/2000/svg'%3E%3Cpath d='M4 6h28v24H4V6zm0 8h28v8H4m9-16v24h10V5.8' fill='none' stroke='%23000' stroke-width='2'/%3E%3C/svg%3E");
+  background-position: center;
+  background-repeat: no-repeat;
+}
+
+.iobtn {
+  background-color: white;
+  border: none;
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='36' height='36'%3E%3Cpath fill='none' stroke='%23000' stroke-width='2' d='M3 33v-7l6.8-7h16.5l6.7 7v7H3zM3.2 26H33M21 9l5-5.9 5 6h-2.5V15h-5V9H21zm-4.9 0l-5 6-5-6h2.5V3h5v6h2.5z'/%3E%3Cpath fill='none' stroke='%23000' d='M6.1 29.5H10'/%3E%3C/svg%3E");
+  background-position: center;
+  background-repeat: no-repeat;
+}
+
+.visbtn {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24'%3E%3Cpath fill='none' stroke='%23333' d='M2.5 4.5h5v15h-5zM9.5 4.5h5v15h-5zM16.5 4.5h5v15h-5z'/%3E%3C/svg%3E");
+  background-position: center;
+  background-repeat: no-repeat;
+  padding: 15px;
+}
+
+#vismenu-content {
+  left: 0px;
+  font-family: Verdana, sans-serif;
+}
+
+.dark .statsbtn,
+.dark .savebtn,
+.dark .menubtn,
+.dark .iobtn,
+.dark .visbtn {
+  filter: invert(1);
+}
+
+.flexbox {
+  display: flex;
+  align-items: center;
+  justify-content: space-between;
+  width: 100%;
+}
+
+.savebtn {
+  background-color: #d6d6d6;
+  width: auto;
+  height: 30px;
+  flex-grow: 1;
+  margin: 5px;
+  border-radius: 4px;
+}
+
+.savebtn:active {
+  background-color: #0a0;
+  color: white;
+}
+
+.dark .savebtn:active {
+  /* This will be inverted */
+  background-color: #b3b;
+}
+
+.stats {
+  border-collapse: collapse;
+  font-size: 12pt;
+  table-layout: fixed;
+  width: 100%;
+  min-width: 450px;
+}
+
+.dark .stats td {
+  border: 1px solid #bbb;
+}
+
+.stats td {
+  border: 1px solid black;
+  padding: 5px;
+  word-wrap: break-word;
+  text-align: center;
+  position: relative;
+}
+
+#checkbox-stats div {
+  position: absolute;
+  left: 0;
+  top: 0;
+  height: 100%;
+  width: 100%;
+  display: flex;
+  align-items: center;
+  justify-content: center;
+}
+
+#checkbox-stats .bar {
+  background-color: rgba(28, 251, 0, 0.6);
+}
+
+.menu {
+  position: relative;
+  display: inline-block;
+  margin: 10px 10px 10px 0px;
+}
+
+.menu-content {
+  font-size: 12pt !important;
+  text-align: left !important;
+  font-weight: normal !important;
+  display: none;
+  position: absolute;
+  background-color: white;
+  right: 0;
+  min-width: 300px;
+  box-shadow: 0px 8px 16px 0px rgba(0, 0, 0, 0.2);
+  z-index: 100;
+  padding: 8px;
+}
+
+.dark .menu-content {
+  background-color: #111;
+}
+
+.menu:hover .menu-content {
+  display: block;
+}
+
+.menu:hover .menubtn,
+.menu:hover .iobtn,
+.menu:hover .statsbtn {
+  background-color: #eee;
+}
+
+.menu-label {
+  display: inline-block;
+  padding: 8px;
+  border: 1px solid #ccc;
+  border-top: 0;
+  width: calc(100% - 18px);
+}
+
+.menu-label-top {
+  border-top: 1px solid #ccc;
+}
+
+.menu-textbox {
+  float: left;
+  height: 24px;
+  margin: 10px 5px;
+  padding: 5px 5px;
+  font-family: Consolas, "DejaVu Sans Mono", Monaco, monospace;
+  font-size: 14px;
+  box-sizing: border-box;
+  border: 1px solid #888;
+  border-radius: 4px;
+  outline: none;
+  background-color: #eee;
+  transition: background-color 0.2s, border 0.2s;
+  width: calc(100% - 10px);
+}
+
+.menu-textbox.invalid,
+.dark .menu-textbox.invalid {
+  color: red;
+}
+
+.dark .menu-textbox {
+  background-color: #222;
+  color: #eee;
+}
+
+.radio-container {
+  margin: 4px;
+}
+
+.topmostdiv {
+  width: 100%;
+  height: 100%;
+  background-color: white;
+  transition: background-color 0.3s;
+}
+
+#top {
+  height: 78px;
+  border-bottom: 2px solid black;
+}
+
+.dark #top {
+  border-bottom: 2px solid #ccc;
+}
+
+#dbg {
+  display: block;
+}
+
+::-webkit-scrollbar {
+  width: 8px;
+}
+
+::-webkit-scrollbar-track {
+  background: #aaa;
+}
+
+::-webkit-scrollbar-thumb {
+  background: #666;
+  border-radius: 3px;
+}
+
+::-webkit-scrollbar-thumb:hover {
+  background: #555;
+}
+
+.slider {
+  -webkit-appearance: none;
+  width: 100%;
+  margin: 3px 0;
+  padding: 0;
+  outline: none;
+  opacity: 0.7;
+  -webkit-transition: .2s;
+  transition: opacity .2s;
+  border-radius: 3px;
+}
+
+.slider:hover {
+  opacity: 1;
+}
+
+.slider:focus {
+  outline: none;
+}
+
+.slider::-webkit-slider-runnable-track {
+  -webkit-appearance: none;
+  width: 100%;
+  height: 8px;
+  background: #d3d3d3;
+  border-radius: 3px;
+  border: none;
+}
+
+.slider::-webkit-slider-thumb {
+  -webkit-appearance: none;
+  width: 15px;
+  height: 15px;
+  border-radius: 50%;
+  background: #0a0;
+  cursor: pointer;
+  margin-top: -4px;
+}
+
+.dark .slider::-webkit-slider-thumb {
+  background: #3d3;
+}
+
+.slider::-moz-range-thumb {
+  width: 15px;
+  height: 15px;
+  border-radius: 50%;
+  background: #0a0;
+  cursor: pointer;
+}
+
+.slider::-moz-range-track {
+  height: 8px;
+  background: #d3d3d3;
+  border-radius: 3px;
+}
+
+.dark .slider::-moz-range-thumb {
+  background: #3d3;
+}
+
+.slider::-ms-track {
+  width: 100%;
+  height: 8px;
+  border-width: 3px 0;
+  background: transparent;
+  border-color: transparent;
+  color: transparent;
+  transition: opacity .2s;
+}
+
+.slider::-ms-fill-lower {
+  background: #d3d3d3;
+  border: none;
+  border-radius: 3px;
+}
+
+.slider::-ms-fill-upper {
+  background: #d3d3d3;
+  border: none;
+  border-radius: 3px;
+}
+
+.slider::-ms-thumb {
+  width: 15px;
+  height: 15px;
+  border-radius: 50%;
+  background: #0a0;
+  cursor: pointer;
+  margin: 0;
+}
+
+.shameless-plug {
+  font-size: 0.8em;
+  text-align: center;
+  display: block;
+}
+
+a {
+  color: #0278a4;
+}
+
+.dark a {
+  color: #00b9fd;
+}
+
+#frontcanvas,
+#backcanvas {
+  touch-action: none;
+}
+
+.placeholder {
+  border: 1px dashed #9f9fda !important;
+  background-color: #edf2f7 !important;
+}
+
+.dragging {
+  z-index: 999;
+}
+
+.dark .dragging>table>tbody>tr {
+  background-color: #252c30;
+}
+
+.dark .placeholder {
+  filter: invert(1);
+}
+
+.column-spacer {
+  top: 0;
+  left: 0;
+  width: calc(100% - 4px);
+  position: absolute;
+  cursor: pointer;
+  user-select: none;
+  height: 100%;
+}
+
+.column-width-handle {
+  top: 0;
+  right: 0;
+  width: 4px;
+  position: absolute;
+  cursor: col-resize;
+  user-select: none;
+  height: 100%;
+}
+
+.column-width-handle:hover {
+  background-color: #4f99bd;
+}
+
+
+  </style>
+  <script type="text/javascript" >
+///////////////////////////////////////////////
+/*
+  Split.js - v1.3.5
+  MIT License
+  https://github.com/nathancahill/Split.js
+*/
+!function(e,t){"object"==typeof exports&&"undefined"!=typeof module?module.exports=t():"function"==typeof define&&define.amd?define(t):e.Split=t()}(this,function(){"use strict";var e=window,t=e.document,n="addEventListener",i="removeEventListener",r="getBoundingClientRect",s=function(){return!1},o=e.attachEvent&&!e[n],a=["","-webkit-","-moz-","-o-"].filter(function(e){var n=t.createElement("div");return n.style.cssText="width:"+e+"calc(9px)",!!n.style.length}).shift()+"calc",l=function(e){return"string"==typeof e||e instanceof String?t.querySelector(e):e};return function(u,c){function z(e,t,n){var i=A(y,t,n);Object.keys(i).forEach(function(t){return e.style[t]=i[t]})}function h(e,t){var n=B(y,t);Object.keys(n).forEach(function(t){return e.style[t]=n[t]})}function f(e){var t=E[this.a],n=E[this.b],i=t.size+n.size;t.size=e/this.size*i,n.size=i-e/this.size*i,z(t.element,t.size,this.aGutterSize),z(n.element,n.size,this.bGutterSize)}function m(e){var t;this.dragging&&((t="touches"in e?e.touches[0][b]-this.start:e[b]-this.start)<=E[this.a].minSize+M+this.aGutterSize?t=E[this.a].minSize+this.aGutterSize:t>=this.size-(E[this.b].minSize+M+this.bGutterSize)&&(t=this.size-(E[this.b].minSize+this.bGutterSize)),f.call(this,t),c.onDrag&&c.onDrag())}function g(){var e=E[this.a].element,t=E[this.b].element;this.size=e[r]()[y]+t[r]()[y]+this.aGutterSize+this.bGutterSize,this.start=e[r]()[G]}function d(){var t=this,n=E[t.a].element,r=E[t.b].element;t.dragging&&c.onDragEnd&&c.onDragEnd(),t.dragging=!1,e[i]("mouseup",t.stop),e[i]("touchend",t.stop),e[i]("touchcancel",t.stop),t.parent[i]("mousemove",t.move),t.parent[i]("touchmove",t.move),delete t.stop,delete t.move,n[i]("selectstart",s),n[i]("dragstart",s),r[i]("selectstart",s),r[i]("dragstart",s),n.style.userSelect="",n.style.webkitUserSelect="",n.style.MozUserSelect="",n.style.pointerEvents="",r.style.userSelect="",r.style.webkitUserSelect="",r.style.MozUserSelect="",r.style.pointerEvents="",t.gutter.style.cursor="",t.parent.style.cursor=""}function S(t){var i=this,r=E[i.a].element,o=E[i.b].element;!i.dragging&&c.onDragStart&&c.onDragStart(),t.preventDefault(),i.dragging=!0,i.move=m.bind(i),i.stop=d.bind(i),e[n]("mouseup",i.stop),e[n]("touchend",i.stop),e[n]("touchcancel",i.stop),i.parent[n]("mousemove",i.move),i.parent[n]("touchmove",i.move),r[n]("selectstart",s),r[n]("dragstart",s),o[n]("selectstart",s),o[n]("dragstart",s),r.style.userSelect="none",r.style.webkitUserSelect="none",r.style.MozUserSelect="none",r.style.pointerEvents="none",o.style.userSelect="none",o.style.webkitUserSelect="none",o.style.MozUserSelect="none",o.style.pointerEvents="none",i.gutter.style.cursor=j,i.parent.style.cursor=j,g.call(i)}function v(e){e.forEach(function(t,n){if(n>0){var i=F[n-1],r=E[i.a],s=E[i.b];r.size=e[n-1],s.size=t,z(r.element,r.size,i.aGutterSize),z(s.element,s.size,i.bGutterSize)}})}function p(){F.forEach(function(e){e.parent.removeChild(e.gutter),E[e.a].element.style[y]="",E[e.b].element.style[y]=""})}void 0===c&&(c={});var y,b,G,E,w=l(u[0]).parentNode,D=e.getComputedStyle(w).flexDirection,U=c.sizes||u.map(function(){return 100/u.length}),k=void 0!==c.minSize?c.minSize:100,x=Array.isArray(k)?k:u.map(function(){return k}),L=void 0!==c.gutterSize?c.gutterSize:10,M=void 0!==c.snapOffset?c.snapOffset:30,O=c.direction||"horizontal",j=c.cursor||("horizontal"===O?"ew-resize":"ns-resize"),C=c.gutter||function(e,n){var i=t.createElement("div");return i.className="gutter gutter-"+n,i},A=c.elementStyle||function(e,t,n){var i={};return"string"==typeof t||t instanceof String?i[e]=t:i[e]=o?t+"%":a+"("+t+"% - "+n+"px)",i},B=c.gutterStyle||function(e,t){return n={},n[e]=t+"px",n;var n};"horizontal"===O?(y="width","clientWidth",b="clientX",G="left","paddingLeft"):"vertical"===O&&(y="height","clientHeight",b="clientY",G="top","paddingTop");var F=[];return E=u.map(function(e,t){var i,s={element:l(e),size:U[t],minSize:x[t]};if(t>0&&(i={a:t-1,b:t,dragging:!1,isFirst:1===t,isLast:t===u.length-1,direction:O,parent:w},i.aGutterSize=L,i.bGutterSize=L,i.isFirst&&(i.aGutterSize=L/2),i.isLast&&(i.bGutterSize=L/2),"row-reverse"===D||"column-reverse"===D)){var a=i.a;i.a=i.b,i.b=a}if(!o&&t>0){var c=C(t,O);h(c,L),c[n]("mousedown",S.bind(i)),c[n]("touchstart",S.bind(i)),w.insertBefore(c,s.element),i.gutter=c}0===t||t===u.length-1?z(s.element,s.size,L/2):z(s.element,s.size,L);var f=s.element[r]()[y];return f<s.minSize&&(s.minSize=f),t>0&&F.push(i),s}),o?{setSizes:v,destroy:p}:{setSizes:v,getSizes:function(){return E.map(function(e){return e.size})},collapse:function(e){if(e===F.length){var t=F[e-1];g.call(t),o||f.call(t,t.size-t.bGutterSize)}else{var n=F[e];g.call(n),o||f.call(n,n.aGutterSize)}},destroy:p}}});
+
+///////////////////////////////////////////////
+
+///////////////////////////////////////////////
+// Copyright (c) 2013 Pieroxy <pieroxy@pieroxy.net>
+// This work is free. You can redistribute it and/or modify it
+// under the terms of the WTFPL, Version 2
+// For more information see LICENSE.txt or http://www.wtfpl.net/
+//
+// For more information, the home page:
+// http://pieroxy.net/blog/pages/lz-string/testing.html
+//
+// LZ-based compression algorithm, version 1.4.4
+var LZString=function(){var o=String.fromCharCode,i={};var n={decompressFromBase64:function(o){return null==o?"":""==o?null:n._decompress(o.length,32,function(n){return function(o,n){if(!i[o]){i[o]={};for(var t=0;t<o.length;t++)i[o][o.charAt(t)]=t}return i[o][n]}("ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/=",o.charAt(n))})},_decompress:function(i,n,t){var r,e,a,s,p,u,l,f=[],c=4,d=4,h=3,v="",g=[],m={val:t(0),position:n,index:1};for(r=0;r<3;r+=1)f[r]=r;for(a=0,p=Math.pow(2,2),u=1;u!=p;)s=m.val&m.position,m.position>>=1,0==m.position&&(m.position=n,m.val=t(m.index++)),a|=(s>0?1:0)*u,u<<=1;switch(a){case 0:for(a=0,p=Math.pow(2,8),u=1;u!=p;)s=m.val&m.position,m.position>>=1,0==m.position&&(m.position=n,m.val=t(m.index++)),a|=(s>0?1:0)*u,u<<=1;l=o(a);break;case 1:for(a=0,p=Math.pow(2,16),u=1;u!=p;)s=m.val&m.position,m.position>>=1,0==m.position&&(m.position=n,m.val=t(m.index++)),a|=(s>0?1:0)*u,u<<=1;l=o(a);break;case 2:return""}for(f[3]=l,e=l,g.push(l);;){if(m.index>i)return"";for(a=0,p=Math.pow(2,h),u=1;u!=p;)s=m.val&m.position,m.position>>=1,0==m.position&&(m.position=n,m.val=t(m.index++)),a|=(s>0?1:0)*u,u<<=1;switch(l=a){case 0:for(a=0,p=Math.pow(2,8),u=1;u!=p;)s=m.val&m.position,m.position>>=1,0==m.position&&(m.position=n,m.val=t(m.index++)),a|=(s>0?1:0)*u,u<<=1;f[d++]=o(a),l=d-1,c--;break;case 1:for(a=0,p=Math.pow(2,16),u=1;u!=p;)s=m.val&m.position,m.position>>=1,0==m.position&&(m.position=n,m.val=t(m.index++)),a|=(s>0?1:0)*u,u<<=1;f[d++]=o(a),l=d-1,c--;break;case 2:return g.join("")}if(0==c&&(c=Math.pow(2,h),h++),f[l])v=f[l];else{if(l!==d)return null;v=e+e.charAt(0)}g.push(v),f[d++]=e+v.charAt(0),e=v,0==--c&&(c=Math.pow(2,h),h++)}}};return n}();"function"==typeof define&&define.amd?define(function(){return LZString}):"undefined"!=typeof module&&null!=module?module.exports=LZString:"undefined"!=typeof angular&&null!=angular&&angular.module("LZString",[]).factory("LZString",function(){return LZString});
+///////////////////////////////////////////////
+
+///////////////////////////////////////////////
+/*!
+ * PEP v0.4.3 | https://github.com/jquery/PEP
+ * Copyright jQuery Foundation and other contributors | http://jquery.org/license
+ */
+!function(a,b){"object"==typeof exports&&"undefined"!=typeof module?module.exports=b():"function"==typeof define&&define.amd?define(b):a.PointerEventsPolyfill=b()}(this,function(){"use strict";function a(a,b){b=b||Object.create(null);var c=document.createEvent("Event");c.initEvent(a,b.bubbles||!1,b.cancelable||!1);
+for(var d,e=2;e<m.length;e++)d=m[e],c[d]=b[d]||n[e];c.buttons=b.buttons||0;
+var f=0;return f=b.pressure&&c.buttons?b.pressure:c.buttons?.5:0,c.x=c.clientX,c.y=c.clientY,c.pointerId=b.pointerId||0,c.width=b.width||0,c.height=b.height||0,c.pressure=f,c.tiltX=b.tiltX||0,c.tiltY=b.tiltY||0,c.twist=b.twist||0,c.tangentialPressure=b.tangentialPressure||0,c.pointerType=b.pointerType||"",c.hwTimestamp=b.hwTimestamp||0,c.isPrimary=b.isPrimary||!1,c}function b(){this.array=[],this.size=0}function c(a,b,c,d){this.addCallback=a.bind(d),this.removeCallback=b.bind(d),this.changedCallback=c.bind(d),A&&(this.observer=new A(this.mutationWatcher.bind(this)))}function d(a){return"body /shadow-deep/ "+e(a)}function e(a){return'[touch-action="'+a+'"]'}function f(a){return"{ -ms-touch-action: "+a+"; touch-action: "+a+"; }"}function g(){if(F){D.forEach(function(a){String(a)===a?(E+=e(a)+f(a)+"\n",G&&(E+=d(a)+f(a)+"\n")):(E+=a.selectors.map(e)+f(a.rule)+"\n",G&&(E+=a.selectors.map(d)+f(a.rule)+"\n"))});var a=document.createElement("style");a.textContent=E,document.head.appendChild(a)}}function h(){if(!window.PointerEvent){if(window.PointerEvent=a,window.navigator.msPointerEnabled){var b=window.navigator.msMaxTouchPoints;Object.defineProperty(window.navigator,"maxTouchPoints",{value:b,enumerable:!0}),u.registerSource("ms",_)}else Object.defineProperty(window.navigator,"maxTouchPoints",{value:0,enumerable:!0}),u.registerSource("mouse",N),void 0!==window.ontouchstart&&u.registerSource("touch",V);u.register(document)}}function i(a){if(!u.pointermap.has(a)){var b=new Error("InvalidPointerId");throw b.name="InvalidPointerId",b}}function j(a){for(var b=a.parentNode;b&&b!==a.ownerDocument;)b=b.parentNode;if(!b){var c=new Error("InvalidStateError");throw c.name="InvalidStateError",c}}function k(a){var b=u.pointermap.get(a);return 0!==b.buttons}function l(){window.Element&&!Element.prototype.setPointerCapture&&Object.defineProperties(Element.prototype,{setPointerCapture:{value:W},releasePointerCapture:{value:X},hasPointerCapture:{value:Y}})}
+var m=["bubbles","cancelable","view","detail","screenX","screenY","clientX","clientY","ctrlKey","altKey","shiftKey","metaKey","button","relatedTarget","pageX","pageY"],n=[!1,!1,null,null,0,0,0,0,!1,!1,!1,!1,0,null,0,0],o=window.Map&&window.Map.prototype.forEach,p=o?Map:b;b.prototype={set:function(a,b){return void 0===b?this["delete"](a):(this.has(a)||this.size++,void(this.array[a]=b))},has:function(a){return void 0!==this.array[a]},"delete":function(a){this.has(a)&&(delete this.array[a],this.size--)},get:function(a){return this.array[a]},clear:function(){this.array.length=0,this.size=0},forEach:function(a,b){return this.array.forEach(function(c,d){a.call(b,c,d,this)},this)}};var q=["bubbles","cancelable","view","detail","screenX","screenY","clientX","clientY","ctrlKey","altKey","shiftKey","metaKey","button","relatedTarget","buttons","pointerId","width","height","pressure","tiltX","tiltY","pointerType","hwTimestamp","isPrimary","type","target","currentTarget","which","pageX","pageY","timeStamp"],r=[!1,!1,null,null,0,0,0,0,!1,!1,!1,!1,0,null,0,0,0,0,0,0,0,"",0,!1,"",null,null,0,0,0,0],s={pointerover:1,pointerout:1,pointerenter:1,pointerleave:1},t="undefined"!=typeof SVGElementInstance,u={pointermap:new p,eventMap:Object.create(null),captureInfo:Object.create(null),eventSources:Object.create(null),eventSourceList:[],registerSource:function(a,b){var c=b,d=c.events;d&&(d.forEach(function(a){c[a]&&(this.eventMap[a]=c[a].bind(c))},this),this.eventSources[a]=c,this.eventSourceList.push(c))},register:function(a){for(var b,c=this.eventSourceList.length,d=0;d<c&&(b=this.eventSourceList[d]);d++)
+b.register.call(b,a)},unregister:function(a){for(var b,c=this.eventSourceList.length,d=0;d<c&&(b=this.eventSourceList[d]);d++)
+b.unregister.call(b,a)},contains:function(a,b){try{return a.contains(b)}catch(c){return!1}},down:function(a){a.bubbles=!0,this.fireEvent("pointerdown",a)},move:function(a){a.bubbles=!0,this.fireEvent("pointermove",a)},up:function(a){a.bubbles=!0,this.fireEvent("pointerup",a)},enter:function(a){a.bubbles=!1,this.fireEvent("pointerenter",a)},leave:function(a){a.bubbles=!1,this.fireEvent("pointerleave",a)},over:function(a){a.bubbles=!0,this.fireEvent("pointerover",a)},out:function(a){a.bubbles=!0,this.fireEvent("pointerout",a)},cancel:function(a){a.bubbles=!0,this.fireEvent("pointercancel",a)},leaveOut:function(a){this.out(a),this.propagate(a,this.leave,!1)},enterOver:function(a){this.over(a),this.propagate(a,this.enter,!0)},eventHandler:function(a){if(!a._handledByPE){var b=a.type,c=this.eventMap&&this.eventMap[b];c&&c(a),a._handledByPE=!0}},listen:function(a,b){b.forEach(function(b){this.addEvent(a,b)},this)},unlisten:function(a,b){b.forEach(function(b){this.removeEvent(a,b)},this)},addEvent:function(a,b){a.addEventListener(b,this.boundHandler)},removeEvent:function(a,b){a.removeEventListener(b,this.boundHandler)},makeEvent:function(b,c){this.captureInfo[c.pointerId]&&(c.relatedTarget=null);var d=new a(b,c);return c.preventDefault&&(d.preventDefault=c.preventDefault),d._target=d._target||c.target,d},fireEvent:function(a,b){var c=this.makeEvent(a,b);return this.dispatchEvent(c)},cloneEvent:function(a){for(var b,c=Object.create(null),d=0;d<q.length;d++)b=q[d],c[b]=a[b]||r[d],!t||"target"!==b&&"relatedTarget"!==b||c[b]instanceof SVGElementInstance&&(c[b]=c[b].correspondingUseElement);return a.preventDefault&&(c.preventDefault=function(){a.preventDefault()}),c},getTarget:function(a){var b=this.captureInfo[a.pointerId];return b?a._target!==b&&a.type in s?void 0:b:a._target},propagate:function(a,b,c){for(var d=a.target,e=[];d!==document&&!d.contains(a.relatedTarget);) if(e.push(d),d=d.parentNode,!d)return;c&&e.reverse(),e.forEach(function(c){a.target=c,b.call(this,a)},this)},setCapture:function(b,c,d){this.captureInfo[b]&&this.releaseCapture(b,d),this.captureInfo[b]=c,this.implicitRelease=this.releaseCapture.bind(this,b,d),document.addEventListener("pointerup",this.implicitRelease),document.addEventListener("pointercancel",this.implicitRelease);var e=new a("gotpointercapture");e.pointerId=b,e._target=c,d||this.asyncDispatchEvent(e)},releaseCapture:function(b,c){var d=this.captureInfo[b];if(d){this.captureInfo[b]=void 0,document.removeEventListener("pointerup",this.implicitRelease),document.removeEventListener("pointercancel",this.implicitRelease);var e=new a("lostpointercapture");e.pointerId=b,e._target=d,c||this.asyncDispatchEvent(e)}},dispatchEvent:/*scope.external.dispatchEvent || */function(a){var b=this.getTarget(a);if(b)return b.dispatchEvent(a)},asyncDispatchEvent:function(a){requestAnimationFrame(this.dispatchEvent.bind(this,a))}};u.boundHandler=u.eventHandler.bind(u);var v={shadow:function(a){if(a)return a.shadowRoot||a.webkitShadowRoot},canTarget:function(a){return a&&Boolean(a.elementFromPoint)},targetingShadow:function(a){var b=this.shadow(a);if(this.canTarget(b))return b},olderShadow:function(a){var b=a.olderShadowRoot;if(!b){var c=a.querySelector("shadow");c&&(b=c.olderShadowRoot)}return b},allShadows:function(a){for(var b=[],c=this.shadow(a);c;)b.push(c),c=this.olderShadow(c);return b},searchRoot:function(a,b,c){if(a){var d,e,f=a.elementFromPoint(b,c);for(e=this.targetingShadow(f);e;){if(d=e.elementFromPoint(b,c)){var g=this.targetingShadow(d);return this.searchRoot(g,b,c)||d} e=this.olderShadow(e)} return f}},owner:function(a){
+for(var b=a;b.parentNode;)b=b.parentNode;
+return b.nodeType!==Node.DOCUMENT_NODE&&b.nodeType!==Node.DOCUMENT_FRAGMENT_NODE&&(b=document),b},findTarget:function(a){var b=a.clientX,c=a.clientY,d=this.owner(a.target);
+return d.elementFromPoint(b,c)||(d=document),this.searchRoot(d,b,c)}},w=Array.prototype.forEach.call.bind(Array.prototype.forEach),x=Array.prototype.map.call.bind(Array.prototype.map),y=Array.prototype.slice.call.bind(Array.prototype.slice),z=Array.prototype.filter.call.bind(Array.prototype.filter),A=window.MutationObserver||window.WebKitMutationObserver,B="[touch-action]",C={subtree:!0,childList:!0,attributes:!0,attributeOldValue:!0,attributeFilter:["touch-action"]};c.prototype={watchSubtree:function(a){
+//
+this.observer&&v.canTarget(a)&&this.observer.observe(a,C)},enableOnSubtree:function(a){this.watchSubtree(a),a===document&&"complete"!==document.readyState?this.installOnLoad():this.installNewSubtree(a)},installNewSubtree:function(a){w(this.findElements(a),this.addElement,this)},findElements:function(a){return a.querySelectorAll?a.querySelectorAll(B):[]},removeElement:function(a){this.removeCallback(a)},addElement:function(a){this.addCallback(a)},elementChanged:function(a,b){this.changedCallback(a,b)},concatLists:function(a,b){return a.concat(y(b))},
+installOnLoad:function(){document.addEventListener("readystatechange",function(){"complete"===document.readyState&&this.installNewSubtree(document)}.bind(this))},isElement:function(a){return a.nodeType===Node.ELEMENT_NODE},flattenMutationTree:function(a){
+var b=x(a,this.findElements,this);
+return b.push(z(a,this.isElement)),b.reduce(this.concatLists,[])},mutationWatcher:function(a){a.forEach(this.mutationHandler,this)},mutationHandler:function(a){if("childList"===a.type){var b=this.flattenMutationTree(a.addedNodes);b.forEach(this.addElement,this);var c=this.flattenMutationTree(a.removedNodes);c.forEach(this.removeElement,this)}else"attributes"===a.type&&this.elementChanged(a.target,a.oldValue)}};var D=["none","auto","pan-x","pan-y",{rule:"pan-x pan-y",selectors:["pan-x pan-y","pan-y pan-x"]}],E="",F=window.PointerEvent||window.MSPointerEvent,G=!window.ShadowDOMPolyfill&&document.head.createShadowRoot,H=u.pointermap,I=25,J=[1,4,2,8,16],K=!1;try{K=1===new MouseEvent("test",{buttons:1}).buttons}catch(L){}
+var M,N={POINTER_ID:1,POINTER_TYPE:"mouse",events:["mousedown","mousemove","mouseup","mouseover","mouseout"],register:function(a){u.listen(a,this.events)},unregister:function(a){u.unlisten(a,this.events)},lastTouches:[],
+isEventSimulatedFromTouch:function(a){for(var b,c=this.lastTouches,d=a.clientX,e=a.clientY,f=0,g=c.length;f<g&&(b=c[f]);f++){
+var h=Math.abs(d-b.x),i=Math.abs(e-b.y);if(h<=I&&i<=I)return!0}},prepareEvent:function(a){var b=u.cloneEvent(a),c=b.preventDefault;return b.preventDefault=function(){a.preventDefault(),c()},b.pointerId=this.POINTER_ID,b.isPrimary=!0,b.pointerType=this.POINTER_TYPE,b},prepareButtonsForMove:function(a,b){var c=H.get(this.POINTER_ID);
+0!==b.which&&c?a.buttons=c.buttons:a.buttons=0,b.buttons=a.buttons},mousedown:function(a){if(!this.isEventSimulatedFromTouch(a)){var b=H.get(this.POINTER_ID),c=this.prepareEvent(a);K||(c.buttons=J[c.button],b&&(c.buttons|=b.buttons),a.buttons=c.buttons),H.set(this.POINTER_ID,a),b&&0!==b.buttons?u.move(c):u.down(c)}},mousemove:function(a){if(!this.isEventSimulatedFromTouch(a)){var b=this.prepareEvent(a);K||this.prepareButtonsForMove(b,a),b.button=-1,H.set(this.POINTER_ID,a),u.move(b)}},mouseup:function(a){if(!this.isEventSimulatedFromTouch(a)){var b=H.get(this.POINTER_ID),c=this.prepareEvent(a);if(!K){var d=J[c.button];
+c.buttons=b?b.buttons&~d:0,a.buttons=c.buttons}H.set(this.POINTER_ID,a),
+c.buttons&=~J[c.button],0===c.buttons?u.up(c):u.move(c)}},mouseover:function(a){if(!this.isEventSimulatedFromTouch(a)){var b=this.prepareEvent(a);K||this.prepareButtonsForMove(b,a),b.button=-1,H.set(this.POINTER_ID,a),u.enterOver(b)}},mouseout:function(a){if(!this.isEventSimulatedFromTouch(a)){var b=this.prepareEvent(a);K||this.prepareButtonsForMove(b,a),b.button=-1,u.leaveOut(b)}},cancel:function(a){var b=this.prepareEvent(a);u.cancel(b),this.deactivateMouse()},deactivateMouse:function(){H["delete"](this.POINTER_ID)}},O=u.captureInfo,P=v.findTarget.bind(v),Q=v.allShadows.bind(v),R=u.pointermap,S=2500,T=200,U="touch-action",V={events:["touchstart","touchmove","touchend","touchcancel"],register:function(a){M.enableOnSubtree(a)},unregister:function(){},elementAdded:function(a){var b=a.getAttribute(U),c=this.touchActionToScrollType(b);c&&(a._scrollType=c,u.listen(a,this.events),
+Q(a).forEach(function(a){a._scrollType=c,u.listen(a,this.events)},this))},elementRemoved:function(a){a._scrollType=void 0,u.unlisten(a,this.events),
+Q(a).forEach(function(a){a._scrollType=void 0,u.unlisten(a,this.events)},this)},elementChanged:function(a,b){var c=a.getAttribute(U),d=this.touchActionToScrollType(c),e=this.touchActionToScrollType(b);
+d&&e?(a._scrollType=d,Q(a).forEach(function(a){a._scrollType=d},this)):e?this.elementRemoved(a):d&&this.elementAdded(a)},scrollTypes:{EMITTER:"none",XSCROLLER:"pan-x",YSCROLLER:"pan-y",SCROLLER:/^(?:pan-x pan-y)|(?:pan-y pan-x)|auto$/},touchActionToScrollType:function(a){var b=a,c=this.scrollTypes;return"none"===b?"none":b===c.XSCROLLER?"X":b===c.YSCROLLER?"Y":c.SCROLLER.exec(b)?"XY":void 0},POINTER_TYPE:"touch",firstTouch:null,isPrimaryTouch:function(a){return this.firstTouch===a.identifier},setPrimaryTouch:function(a){
+(0===R.size||1===R.size&&R.has(1))&&(this.firstTouch=a.identifier,this.firstXY={X:a.clientX,Y:a.clientY},this.scrolling=!1,this.cancelResetClickCount())},removePrimaryPointer:function(a){a.isPrimary&&(this.firstTouch=null,this.firstXY=null,this.resetClickCount())},clickCount:0,resetId:null,resetClickCount:function(){var a=function(){this.clickCount=0,this.resetId=null}.bind(this);this.resetId=setTimeout(a,T)},cancelResetClickCount:function(){this.resetId&&clearTimeout(this.resetId)},typeToButtons:function(a){var b=0;return"touchstart"!==a&&"touchmove"!==a||(b=1),b},touchToPointer:function(a){var b=this.currentTouchEvent,c=u.cloneEvent(a),d=c.pointerId=a.identifier+2;c.target=O[d]||P(c),c.bubbles=!0,c.cancelable=!0,c.detail=this.clickCount,c.button=0,c.buttons=this.typeToButtons(b.type),c.width=2*(a.radiusX||a.webkitRadiusX||0),c.height=2*(a.radiusY||a.webkitRadiusY||0),c.pressure=a.force||a.webkitForce||.5,c.isPrimary=this.isPrimaryTouch(a),c.pointerType=this.POINTER_TYPE,
+c.altKey=b.altKey,c.ctrlKey=b.ctrlKey,c.metaKey=b.metaKey,c.shiftKey=b.shiftKey;
+var e=this;return c.preventDefault=function(){e.scrolling=!1,e.firstXY=null,b.preventDefault()},c},processTouches:function(a,b){var c=a.changedTouches;this.currentTouchEvent=a;for(var d,e=0;e<c.length;e++)d=c[e],b.call(this,this.touchToPointer(d))},
+shouldScroll:function(a){if(this.firstXY){var b,c=a.currentTarget._scrollType;if("none"===c)
+b=!1;else if("XY"===c)
+b=!0;else{var d=a.changedTouches[0],e=c,f="Y"===c?"X":"Y",g=Math.abs(d["client"+e]-this.firstXY[e]),h=Math.abs(d["client"+f]-this.firstXY[f]);
+b=g>=h}return this.firstXY=null,b}},findTouch:function(a,b){for(var c,d=0,e=a.length;d<e&&(c=a[d]);d++)if(c.identifier===b)return!0},
+vacuumTouches:function(a){var b=a.touches;
+if(R.size>=b.length){var c=[];R.forEach(function(a,d){
+if(1!==d&&!this.findTouch(b,d-2)){var e=a.out;c.push(e)}},this),c.forEach(this.cancelOut,this)}},touchstart:function(a){this.vacuumTouches(a),this.setPrimaryTouch(a.changedTouches[0]),this.dedupSynthMouse(a),this.scrolling||(this.clickCount++,this.processTouches(a,this.overDown))},overDown:function(a){R.set(a.pointerId,{target:a.target,out:a,outTarget:a.target}),u.enterOver(a),u.down(a)},touchmove:function(a){this.scrolling||(this.shouldScroll(a)?(this.scrolling=!0,this.touchcancel(a)):(a.preventDefault(),this.processTouches(a,this.moveOverOut)))},moveOverOut:function(a){var b=a,c=R.get(b.pointerId);
+if(c){var d=c.out,e=c.outTarget;u.move(b),d&&e!==b.target&&(d.relatedTarget=b.target,b.relatedTarget=e,
+d.target=e,b.target?(u.leaveOut(d),u.enterOver(b)):(
+b.target=e,b.relatedTarget=null,this.cancelOut(b))),c.out=b,c.outTarget=b.target}},touchend:function(a){this.dedupSynthMouse(a),this.processTouches(a,this.upOut)},upOut:function(a){this.scrolling||(u.up(a),u.leaveOut(a)),this.cleanUpPointer(a)},touchcancel:function(a){this.processTouches(a,this.cancelOut)},cancelOut:function(a){u.cancel(a),u.leaveOut(a),this.cleanUpPointer(a)},cleanUpPointer:function(a){R["delete"](a.pointerId),this.removePrimaryPointer(a)},
+dedupSynthMouse:function(a){var b=N.lastTouches,c=a.changedTouches[0];
+if(this.isPrimaryTouch(c)){
+var d={x:c.clientX,y:c.clientY};b.push(d);var e=function(a,b){var c=a.indexOf(b);c>-1&&a.splice(c,1)}.bind(null,b,d);setTimeout(e,S)}}};M=new c(V.elementAdded,V.elementRemoved,V.elementChanged,V);var W,X,Y,Z=u.pointermap,$=window.MSPointerEvent&&"number"==typeof window.MSPointerEvent.MSPOINTER_TYPE_MOUSE,_={events:["MSPointerDown","MSPointerMove","MSPointerUp","MSPointerOut","MSPointerOver","MSPointerCancel","MSGotPointerCapture","MSLostPointerCapture"],register:function(a){u.listen(a,this.events)},unregister:function(a){u.unlisten(a,this.events)},POINTER_TYPES:["","unavailable","touch","pen","mouse"],prepareEvent:function(a){var b=a;return $&&(b=u.cloneEvent(a),b.pointerType=this.POINTER_TYPES[a.pointerType]),b},cleanup:function(a){Z["delete"](a)},MSPointerDown:function(a){Z.set(a.pointerId,a);var b=this.prepareEvent(a);u.down(b)},MSPointerMove:function(a){var b=this.prepareEvent(a);u.move(b)},MSPointerUp:function(a){var b=this.prepareEvent(a);u.up(b),this.cleanup(a.pointerId)},MSPointerOut:function(a){var b=this.prepareEvent(a);u.leaveOut(b)},MSPointerOver:function(a){var b=this.prepareEvent(a);u.enterOver(b)},MSPointerCancel:function(a){var b=this.prepareEvent(a);u.cancel(b),this.cleanup(a.pointerId)},MSLostPointerCapture:function(a){var b=u.makeEvent("lostpointercapture",a);u.dispatchEvent(b)},MSGotPointerCapture:function(a){var b=u.makeEvent("gotpointercapture",a);u.dispatchEvent(b)}},aa=window.navigator;aa.msPointerEnabled?(W=function(a){i(a),j(this),k(a)&&(u.setCapture(a,this,!0),this.msSetPointerCapture(a))},X=function(a){i(a),u.releaseCapture(a,!0),this.msReleasePointerCapture(a)}):(W=function(a){i(a),j(this),k(a)&&u.setCapture(a,this)},X=function(a){i(a),u.releaseCapture(a)}),Y=function(a){return!!u.captureInfo[a]},g(),h(),l();var ba={dispatcher:u,Installer:c,PointerEvent:a,PointerMap:p,targetFinding:v};return ba});
+
+///////////////////////////////////////////////
+
+///////////////////////////////////////////////
+var config = {"dark_mode": false, "show_pads": true, "show_fabrication": false, "show_silkscreen": true, "highlight_pin1": false, "redraw_on_drag": true, "board_rotation": 0, "checkboxes": "Sourced,Placed", "bom_view": "left-right", "layer_view": "FB", "fields": ["Value", "Footprint"]}
+///////////////////////////////////////////////
+
+///////////////////////////////////////////////
+var pcbdata = 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jw2/KgH4LsNfDsJQPVQG44MAuBWIEK0c5s6vTVCG4Go5MGkY96yG4QOJNEWGjPH/NyxG3wDGjuZlVGvy2hZPJFZGkmnGqfPGhGjwZPJkYG6G0m+cicwm5mmyVmzY7fDcg7cK64jyeA2dOOIG/mHsKKS+UqHOc6BIFYIKVkCaGgVOUmTYOBUuNuJW7aPdDUBIZaOuO4UQbFPW7aS+E4FKeGE2oUGnYw0uWWnA02x+IEN6OmK2wkf+JaI27hN2p2hhY2paR28uC2xOHsPKLeOOM0WsMmBIMqPskqrqF2xBGO00CqX6oynYzwjwT8BMRhIiGIcxAIuBECWSNUSosIrfItWmsc/GjwE9RBYQUqVOAIuuxhKGNJMunmyu81eG+Y9hKaXO62MuhSBRfukugupyy/Fyum3uke9EVu4LBEQu0e4QLk6eGm7u4yzO0OOe2SbaIerNJW083e2UdeyvDO/fbe4u4QT8JkfelWS+1uk9FYie3mqunukyjwIu3O8zNYJene4QZPCaDu8I1+je8+/Ilu+IUYZ+smiRSB4QOBX+l+rus+/6iBwmge2Qu+hY+B6yGsYBiu9PN+zei+r+sA1e7B2heBtu3FGmzcgW7coW24+Ye0lYbJVcE6+lLM2UKuVcZkDEE5N0wMW63IIKfzIR0KOKlIuze0nhsMVcE8inIke0rhJuBRpUOkn+guTmVcWELBDFYLP4dlXRhMDJR0OkbFExtYH5MrY4MmXR4EfJN43YOmdR6ZSFX4nyqRnidDfkt+SR1cQMS9Tx4RjYVcMRmOTxoUbx/hvuEU5qegDhuUM6ExFM0JwqNvUEOJtJyR6SP0UxiaVJ69XJ6KhjEJkpziQRoIFx5Axm3x5R2x6wxmjRhFckX4RwzKgpoQNOqe6u+mvdAFZ4B/GIBC0QAIsQP7YQfY7cKYkBlB9wmIlNNsoZvJh2D8MZtG5ZsA6Z5ROh/myddyAOYWs7T8TQv7FYHYL7U5hEMUi5wLHmT8e4YEW+O5hdMKG+09U+V57jT8O2mEu52jB5+dQnTkXIZLNuD7aULHOsC5hzf9T8cxcXCa5PLDMDBFuqHR5PWTa0bw5LVKxmpIJDbwuUFXTGaJJRo4X5tEGEslsXSlnx6KU+Mlj8H5qNZ5ha5PFlnKa5guQa5POlj7M57q/l4+Y6MQNUTpc6Zlt5o4CZm5vl+dbjMQTcQkMJzKneY0MQfwUBW69V4rDiU0c3OIMl7F2aMQXAh7E1lDVaOV3l7KlFhuaLW1250YQBXTc1pmCGC5ikL7c1/aaO0RwFmGLV5QSpb5nKMQD8EFzYURmVjiRF3UgFzzcVikFkGNy5oWR3EhVrXp9+zOg1gufssA2PP8EYyFlYDs4t5Wzo+Zuo+mgtxFlRAfEKNbbwitpbZt/wPZsKg547Zhvc87Nh9xXBAnVkc7ORlJB1WULxb7eESR/VUxWIYzWd9J/VSQVCl7LgaePeX520W7fEZRCOUo00SMTdvd9BfVJkaQPXXIcg9lS9uUNxTdzHbFB9rwZpSNCkOxuIS99vG9sja+UJY9tQRTJq6J/VUQRMTdudoDgXDdyNGDyxBF1UQs6D8DqdlHTdkHQjfVaNZkNEBYJq1dnAvda4aD4j3wUdyFFd+d51Pd/SrNnlQy3Nkh61dgrYHhUojsfstbS5IZ7uR6DZ4c5yuG1jgNb7LYfjrj0BOtNm9ifHekVRPIQTl2ZBoh+h3tyKkWrk3YXYJOFMt1pxV9TCBeAz1A8zDWdxFMrLEarMqGGE2RlkEqrM3TyxCzwsvOFz3T/Tnx5guzrwPeQx6x9+CzoKKz52/Rk5Yz2sUzoEQlpQnT7z7U+LpQf+ckNUMUtEnucBLzvTrL4L/+Lk+zvefjR1ow4LM0IXTxwzkLvac0AqX4nw3qHp0T8BgNBBAUd/JhdL4Ajr8xLr4eGT0+hZvI9ro1KZHhHrgI8bgbsF00YbutmejwSNgbSb/O3rlbgbvpebtTyfMBtB9rzb0VKbkYgZ6SWbgUGt9T/Z2Aph3cxgExVBTcHzD3WOoEp7nuZUiZkFPZVBWuT4/PcR51C+J42PZJZxFQIiaGJOCmmJCHv0aUVW5hN75RjhcxC9sHndGcmeBeQHyJlQR4Q9pOb757SOQn5mV7mJExbwoGqBMQFH5xbOtUCn+nuH/VHqHaYnxiqkfVOkWLWHD3f8nn059Hyef/LFRJU5nH7ZZVxlRnmgZnxk5VtlQkpnonj3RGGxKXzGXH3CyJkX7RoeTHh6x5xHgX2H4J35kHiOC3oEttz7o3mgcHtd2nn9vH+sxjnN1rg79tRmjjq2YptbLcH4J2QP3bv6xZ33nif33KVbNGx5kPgP/xhb1y+mjtf35hKaoPnx/jrF2ycP9On3vov33PpYfP2B7NFuUvrPgv0K3RTTu74xS9rBQaOJWUO3kZgqIisZci3Djnu8rdjv6NThBi2gS3oEaSDaTDdv5R0o6QRwk9QMeXiDeGfkQg0C5vn4ekYQ1OaSzf1vgXYL5f6+Vfk4MXN5OflYK7M/ukIM35yfj8sxQw+X4foQp/+U5Vk/97Nv4J+nigKin/u7Q9y0YjyY/IEuK1lAXkwByjcVoTFIJ9I4Q1VZvP4CJwNhpAdJP/l4Aly/hIuLXXGn0yW7s90QjsLWAT18pycQCa4OEJbGJzkDO6RDfbpHz6KlFiBdlLWAnT9xUDzK7A52t23r63cjm/bB7h11VBQx8Cf5QUCyFjgSDaQbBSCrEEw4dd9o+hHTKhyUGgh9C/oBuNIIMKkEXkawS9B113jMw1+ZUU9n106QADKOcGKLr6Rzoag1+IEJ9kujfiChuEjg6+M0gvTWET0Kwd4LHEMxqhkCJ6MwUoWCxLFMMBgy+IY2tooUAwuwAIYkFiE2F0Qag8IV33kGgJbOPECaIRm0LRQCOr6XIafEWDQpnB6Qi8tGhsGJDlBz0FMmaGdA1CNBdQ44sMhqERD8ysWD9EUNLglDgssIOXIkO3RT9NcWQqLlmSqFXZRhigtJm4JFBK4BhRnSCs0IvITQNWOg2oYVGmHLA8BxDNrg0RwLmJQ+FOHjqd0OEnEfGXgITuXV2x7dUGTAqhr4DWDHCngpwivofWeETETyVw1TsJ0no9AbuEVRvncUeYyh3MjoClrzzBGpZfSTnDxjfUFCCkOuSpNuOzyvKnw+u7jQ0lbwC4iZXgkI7wvJSbhGClGJic1tCKIz4ikBg+IXCSKehkif4uIykcympEdwmRIGSEZGyJEvpRc76cAVHEhCNZVAcuBFP7kq6w5f0MKKQCYk5bcjfMWCaqvy2K4iYIRio1QEFCFHSBnE0VdEeekdDnIwQHadkE5lFwCNEQHaRERRkZDahXSjNS0QVBcEHJlGjNY0RsGRGGENkOoqGBiKNTBdzS0VDUcyJPCAxDSSo9kVSKBKyiTyxIiMc6IFG6lMRIY7UVXzTZ9c/RyYoArSIUIei9kgDB4BSF8wfFHkeYwUAWNfQ2iMx4oh0aaPyjJjYsvwc6CBgNF1jSQmowRlGJVwcinouwxgaN3bSoJAxHAbOtcOHqV9CkAQJQdcPoF3CRu45diHEUHGBEsM1accX1mHG/CbhaeGcYtw/qRo6QXXScRuNHF7jFx64lPtPQ/rZxFxkFEcVmhPEHibxG46cRcX4FAjBB93EOL8yFB7pAQWoKkAM3up21fxRoGapG3lpNxLgVoT4AMztTKB5Qf5EEEYX/zfioQkFWENghgkoTUQ6IRsP/FKIEV6AeICMHXFKL/lww77YzIEUxi/BfQyTLGFRKwlchUKyMRomRIVDigXQjRAiZaGvbKhAi0pbCoaGKyBESSaFISf+KZ60hvajoXidBOQk0TRQpjS+PJJ/F4g/xkgHsfcL7F9Ec0XEEuqWwr7MJp4eksCHJFr7e8Hh8nEZiZLzqmQy2Z/JFJgzsl/DQGWkucZQJTq50VIZbR0D3C8k2Qru241Pkt1KrwgbJxEU7hTTInKQAp54ggbuIcnhSzJFffkHCBsneSXJtbYKZeOBxYInJBkigakiKT5TApEfbSW2G6zpTYp9kz3FVN4jmT8BebC+lFKSnOSKBpVf4K1IKnPjC+lkhmj9jqnl9CpqmKSkeGqmZSGBbkmuv8lASDTgCC7PKWNPqkTSgpF4regSy6m9cNpudGmNGj4EwE3xhiY5nuQGbRRXGojLwPkiXH+QwmF08ajghHjnSxo78bOkDBRYghKJ9Paas9CxbXsjOYo3ihky2iaZY4XIiqPMMyrUDFa/+RKg4MhnnASqWrR6BLkyouMRq5rdECYN+lVZQZSwZ+GwXel1k5Jj0kRs9NxlnTSZvwcav/Fjw3TCo5rNGVF1pmmFOWIHQpqdLpl5M1gL0kmT9LJkDNo0X0IGX8Ecx5wAZTTZKCllxmghcYeTa9vVE0mzia6/E3wuE27KncEReeSYnOR6ksd9hCxa6ACCmYSB1Z7whxNsxNk6y5mk0pWf001nGz0BrRQmBbMdkNS9hRfWhObJLzXo5yo4uOMGjVlWzCGk+DTgIKOlCCQ4lhSVqllVGXwo5qY2ERpVjjXQEwWYqdDNBmr4R3SGoRMXXDHymJuEdIqWn6BhBiki5NtHAqXIiwI9wZyc5dEa18zSl/xcCCaEiMZDOgvBkPNEJUl/QiiSqXcnVm6JrHSVt6rcq0RhCphGE4ERccESbLrl1Qy5scvOAT0Bh6iWRl8XBKqAxDyiouDqGHNWInmgVAiRWVMcPJgrHzCQp84UbxQem8h95jcjuTzPhAOwyx1ogKHXNcHohfMiJWeGgSrnVZzMkXaCdPIblbp1ckoUeey18xsldCA8nuSmSdF1y+YPc7MQlHfgtyoFaY+qMAvrlplc5K1SuXa2ZEKi4516f0OeljG3yt5ZYo1FiNvmpyJRvo7BQ9JPmNjUF9Eu3JfMbEIKiYecPebSKzJM5Aiz87eWAt6gQKV55C7+UAsVk7it6SM9yIePGbpFFFZ4t2b2PclK1zEqioTM3QFCKLHxcUpqfkQUUTi1F7whsHKDMW6L1FU0/ppYoMXCijxB9UxVticX7StyU6LTvMH6zRRKZl0/gm3yKzeMqZV0oJaTO5nlxBCQM78THDjgIJVQtTAFDjLjhqhP5QM1CkQS6ighsUeTdCRQRpLzI4ZfoKGfHRLmDwMljM8uLWEbiBRsZ9E/CMCFIKEy4lWc4JauEiW+L2ld0iqP/HCV8y4QLpWOP0vpnAysl86L+MLPw66FGoBcQaGDwrL1wcl7giZuKG6EJ1xooy8UA0tODgxRlmSkartLvmZQGZIMxAm+nmHfcUljS3eACA4iUhNabS5AgsrzlcBglqzAMKIRuXNKTZG6d+DTA7A8F+WBIDSZ71cIWTypEiUXA7C1kHUAi0K7gIHKMVicGihtRFaI1NntST020F2Zit1kQrNFaK3Fb7IPpErvZVhZFfrNoS+kcVDszFX7IRXEqPFDDLxcCLOzm0LsP6f6GXF1CcrqscSQBKRiFAvoBVPK2qD1AozS1D4/UElhDHiUvzvymcOjP4lMRIZ/EaIRdNkrNJJYNVzGGkuLmiz+I90yqkpSDJlUO8iMNMZ5h+iQoSqHR+EQkJZiDQvpuVpGIBPBldU05rssqrTKKu/Luqf0fqpijc2AwJ0DSo0ANdVi1XqYloZuC0P7J1bGgwYgHN0Y1ETU6h8YyWdzNGtBjKcLVdCcNUlCVWbp9V4ZPkDmlTglr8mOM71fmoBVEzsY/kTjA6orKKUU1lq5WmKvyaEx41nqiNXyo7XW0H0P0ENVpnrWZsUw2bcFY1JRWVhVMinUOFsBJURp51QzUqkuspUez2Iq6vrAGOXWVhTmC6vdZur6mCsF1kPVcilJ3UcAL1Qc24S+IOmC13xUVYUYKFSpwI1km1M5KlR+ifrY4qM41r+tCj/qFen0Baj9D2DOImqpiHzGvhJLVUmq8RQajTFlwIpRgGg7qtdDegdV4cwq54M2w6SElENJ1bKn90N5QauBFVZ1I8E1oostQhVSHrihWoAa4qH64Deuu/WkaeIn6q6pxHmgTUlocyLpPuE41xUINrpW9sCHYZAagSuQXYHTLXz/FZNTvfGWJp4iQb3qMGiqoJoSaQkxoJGtTVNT36A0kN2VfCOTgxSA0tNE1LDdJESTSNC4xrNjfyWsZ1VnNDuSdUxzKmaK/emsMlms3Bo2U/NbeYKrYttmEDAa50YQFq0kCBbzgYBELXQOtmrT4pmdd6lFoHzt84tGWm+rFrC1yKAaQWqGk73IF+yKabAzLXSGZUN9n1ItU5h2FCRmd6J5rfTNsia3/TvgRMnztNCIJysCsjnCghMwa1ud8mHnXGXNUa2+df5fWquEaWy5eCJmEmcLhfCuktbYqyXdxg9Im0jaoY7jPCflVCQY43oV0+rbnCTjyYbOTMiZRKHO2drmt2s19hdoEa4zzELVYEh3AwnismMEcYPswUjamJHtiQI/mdwLg3aiSx2/gv/iyEagiSKXXGfcHW0Y44dAzW0F1vB2Rdxt1mFJPjnm3vwhtZ234ieT+0HbLERXEUZjv61PbetnWv5PJhq6yLspaWhyV2HuLM89UzOnhHN1Km9TIV/U9cGtzZ2RSdgLOrnSet52lV+d3XdbgETbygRBuO3Fad5umkc6pdguwySrtSRSTqtYcmdCw1UynRuF68hpnkAN0wiw4Sct4jxUYXpzURQQIShQqjhJjgSagbFOXL01aC6MsYopjpk4yULWGTMEUG7rdLpQgxdChUvbqDHpiFSVuh0b6Q86CMFCpu6BRYgjIm6+YMcoEGaOcR2CAYB8j0hv19KUUh5c84PftHlGQjzMzFABUbsrI+7Z5Woi0jfDz3NijSj0E0ZntrGt7Elxen+YknzLQYD5MCw0YZnSVLpHSfVSvQnGr1FiqU9QsvY6N4XZ7rBHMZPYSFT3QpVaY+pnP8jWH8wt0MisFY2T1lbqbU5tc8stncVo0z93AJcVOOS1K60+1+tcTYsMlzcb95izceuXdl9T+i5iG/YYqv3pF/9l+xXTzvcm/7z9t+5xS/jf1uKiIT4+/VAUBFPrw5H43jYKE6QRRkOG/KgItmQLYH5Sc3LQsewzkUaMDJQgg4aKIPIECeWAmECYlwN6Nno10M0BkkYNaFoa2ChgwKA4P3xF9EB3g8cH4NjE5lzBifhbv3BXCLcF6tBRRuUDopKonBidVYCnVH6CV00rkmqHIaTE9UXULQyvR0P5bGdt+PQ02yhw9pRxLifQ2vwIb3qwDGhsvuURPSUMCa+pbQxsUQN19H1jDWrfMEWpzVZaelIkP4dBoXBaodtSFItVVCq0ewzIfsocEmpPVdajULwGnCGqCFvaaatil9Waoh0sj7tYmpoRX1510QUbQ+IUYOoFiewX5GnMTW1YdQ86VMtI2fz3Su1So5ibBGvh+CG9Ng7Rp5qsAZ1rT98im/3pcBzqSocq0TbsPoIQPByH9S3SY0M2JoyyJjKZKYwo0JBi73Jix+IDMdWNcAhmFzDA1sZrojGVmGOG2CMTOOccg0sxuw8fr6k7GmEseHqPsa8YhomIJx+mtcYQYI9oDUQH6P70qrrAvjCxwE/xyhybGrj4J5/SSVBMf0fj1kTpP8fcA/HogASeE5nSeOhwMTVxtY2uog13Gtx8xhEzCemP4gUThkMk5BKhOgGHjvOp42v1pMUDGTKREE0YaGPWofjccGsJSZXD4m+shJzE8MYFMcAPWfJ7E0KY5OpbhjZJtuv4AlNkmOI0KYU1ydFN5MKAEp9U/qqJNf6NFpxsk7aj3QTHDTWZV49KeMUBonj/yXfm8amP9EaJqpq09SdeDMnRxCIZTocddO6mROM6qlVSej4rNIe7Jivj8dKHGmLTs61E6Kf80hmWTMZpaBGcV3/gAAQvoBCBZgQAqYXgIgEsB9AZgBAFAG0CqAgAug7gAET2x13HSHuc0DLskdkIodqOXUGSD2E0KFw50JOFFAkFpC0AAKsQfUDCz8i4EAKagIKEnXxjDmFgT3WML0cSCSAP205oiHGAnO9n9ynZ+UDSQQS/BpV5mwHPKGuhRsbV+EWEGoDVp5AoWPMLDU4KhArmQI2MBXAVTPM9m7zSUNXI5ifMXmYYi5i0DHSjqqgFgCLB8gaG7PDn6W/ZrBIOeU6rmPs4F4C5YSeBAs/gKwe2lBZfME8TzhE281dDSQiplz55hC1+YBQI5OQ10P87NAdrejILIEJUE4iSjrBKLs59AoKGxh7BiLs5k8ssFzWpxcLs5+Q8KuxiyhAwhEzc/OelV24zgstES9ubAtAXILfFyQABYR4BgvWWF+lvuPuy8WtzhTD7Opa9ZDnez9LXk9hlnOl1qOpvZSzIFiP9lCKjzdEZBdMtqWwuel1C+8yUsaWrLBOcihxGkAzmQLBl+NrJY/MEXZWFMWIJzF/MIhl2/uCS2EeVo0XpV0V5C7FaYt8hxWAXcKz9GgrWhxWgVnsPJZ1BgTfLUlj9shMPB5WtLCV4CGOahCFLeQmrHiPZxeaZXOLZrdTbsGjpLRujqVtq8ZdDpoVaLWrRqwVAiuPQQro5s7d2c/MhXMYZV1S95fFF4XnzXqrFpaMWugW8m3F4ULOaWtzA1Zvl1S3taXPbXQLq4dc0+ZOvCowRG5ly/OHGC8BagXvPmpWcOm66B2N9GK+6Cg4fY0QSVwEO+2uTfXaQy8X8QGAhalE6zhE14CByBYfgeLlwQZdy2F11lAQCNr1fT3kpfNRcX1rVh9a5DY2BcbFvEKhXej/4MLooYm/VbUJAZwwskkK/8AGHDWXOHcum7jd7IwoWbv1y4Ph3dY5CGbgIKmaumVZz0qjUN5NjLiEso38bpHXq/xSVYPFqr/N6G8Gx+zfDIbEgCiZ4BAAkn82seUQBuC3AFTjxutwiGMSu7a398SUf8iZCGnHiuoS8XY5dxDzm22Odt7iAVQmP7hCQ+t9TWbfsP1sdRJtuLsATyY9Q3b3U62c7atOe3CIDYG23eJ1wx3pdanSOzLGNsbhTba2AO+naDtO2/bS3S21xA3DNng7m8wiMXdzv0n3JH2eEGXcz0l2fsidtXZ/oEQp2gIoUb2+7auPR3rbvtyuzXQLuN247EaBO0XbrsV31D9bV2xuHG7B2p7S08O4QwfWeLDmqB4xERQD2BRyQ/3aVXFA3tbDqwoUOdEFF4WFR5M3MGGH0nAr72Xa2CE0N3uvtm9Vg+5cOJvYPvfkX7p9t+16qNXiL97tJSJENGfkS4UyxUCikA8qhb3K1O5g8oNEZCCgUmH0W5RFHkyswkoReyqCg+A06UJKID0KLdfuuPWnIz16CCZN8MDt/ECMzSmKB2ijQB+SQB3h2fGrzDZk2tXaEtVyWkUaH/UImZxUvJcO/IVWDISPBqhkY8KmGIKGBgocaUoBtYAZFlEodHlBZ0lfqJpi759JXe9mQR0eVSP/o/IPD7R89z1xxImHBjhh1VBdIQU+HhFCDWI84fWPEgeQ5w6EbZjCYIoTjgG0BtMLqPv2EarR8IVF5iYbHU/bbjr2gfQlgnIzOzWpX8AZQ1HfBxLC9GfSMENR35HqJPKPKEh+HP8EMRk9YcBY/lzD48lg9mVwVZku2uUFrbzsJSRmofVCrxxqdaxIKzJ+ga3bbA1wFYTTvk0Wu4Amhdg49v0yfu6e1O+nNUmFQHzqfJ2qn+bBsD086drZ2njT9UT6fIhL2WVK9168ILP5rxCoRHM9MMvVEXKYeXAd+ObWqiWIHWZcLWpAh/YXOza8cF+CiwlKi1w4Ozn7Hs9Fou73BowCR+fNKifP5hYLRHvwVKgvPI06zX+Wf3niZQ7slzv5wHtedvwYE9cKF68/hDvON4tSo57QH+UVxblWLiElfCb34vYXI8bdEPEec4uOwU+1F3KSnlhxJlkaBBPNTrl4Jt+gL+6f1ir2vPwXfExqO+QRcEvDZDLmF+7W3pnPiXpC4+Dh1ufLyy+A+rF0844TXOaX7z2g2S9edMuR5BPLl2C9tIzVtX1LyNMoCXOyvoo6rvcViiM5Kv0lkaZYA2oAREvbXGZeeYXBKEivZX8CZAu66QXH38Ccm516HAbgmC5NSZOuR9qEJxFLX6CjCBUqNf+ALCMbqioGyGWBuUXjLn54iEDfbOEOtLn14c+YTYu65nr859eiRfeF+Xn7MBF4PLexv3X+2tBBLljbaqqJab5NxJIOc8E394CBERFC7fVvTSphNtzcECKeCp+KRZnpxJF7yvzsD8fBw9enVEPXxiqbxSdOuhJ7BeVb6N6DjB3KsCSRhAFRUo9yVcdlnSdV0e6jdHwI9R7vd0HVdfFx/8ubiOts49wai6C+qoB1z2ZAQXM377lfa9wDc0ln3w4kl0yBPjFwpehMfd1Gj2W88nnNMAmMqUeYXvECh7pDykuuhwxJ2+TLd+u8PXUy0C4rynuGoI/BLz3VWGQlSS7iPMb3ocefn+/FbMlZXtYdPZ+8Y+VO+79i1QOfuYQdx91jwmENwDJ4dx+n3+8XY8248ry+PXhMkoJ6VF3q08rT6T9PFk/ZO9FAnnhHJ5E/6nOP6npTnCo1kyeZEPskT6HJevVmfISuTcPzG+yyPaKFXJzp/YkccwFgWZD8MgSe3KOuSbn56MHxQE6hXPlSb7CEmOhefAvENK/mJlC9evjytYABwF/c+E0Iv/OSuNF6c8UgXPAKNpPyzegA34vz0JqvPyVAZeUvJbmeIjhK9HOyvYUOnUoyOe2fCKQQLKlAnekgQYK0ufyI4QK8Rfiv3nrntHH/R5ejnvceqD17aQes+oUXyxON+ZzK1avGvQnjlEa/uMuetcJDKpieAvcKaX/IQKN9g6R1dMg32vC3wUvS4Kv+qer3yEm9JxrmvQy77N7pj6ppoyjpb8Ale6FexM63yLlzwQRb9xAtOTL7B2Z4JOrvkcfb7RcO8E9U40hU7718G7BAbVjof4CMgdWten7MPnMspzmEzezvE5rHzZ9h+xqJvl5IeJ1dkEwwLt0mEBFD2XZBBzEWcTK35/5wEwX4DPiFuSBifcJBu1P2aL5I7l3x7gZP/nMfeR/5MNcx5HkgJzmEZfTof7oc3j9FzKA/3LRk8giAy/xR+Y/yVb4pns8a/lhdB3b7El8DbfsfsPsFNRLCiHe/yfwUmAb9RTDeP2IPmldoulUg+7Ot37H5PB/qC/TctoB74yHh/+fAKr3iriP35whRX2hjOg/zn/L3tI/A34CAIx85g/pVjIfxoyX9+M/pcUUWbV74fSHe3fdngH5Yid8jf8fbSfjLKH5zq/zovxMBPziAQU8ydhf7PyVyDSo/kvsP6ps7479tJVMynj4HO8IemeUDGznyOd5+/KlsQHcDvp0i+9FTdk8vQBMFyqQzx9eFJ/BHcG44/F6ejKKpLI/5GggRRe/6fzAJ2CJ/Uk8Dh6pGx+4r/MYkTSNsx8ZLm0F/L7x/xHCn8MEZRZ/i9h/8jEPEYUOKCf7JiSKHz42mjwM4gvGNKJr7ncXSBMwnkL8NioQoEAUsAT+vSAKAJI5pBMyoBVSClA2IcAcv4X+d/q8Sx4hKE8Sb+rBKGJPCoAd6BABzCIf5I8NAQwR1im8JPDkBD1Jyw3+hAXgT+iYoHyI4BL/pyxv+VSLtp9UHAVsgcosWEGSy65/pYoYBGYm/AMB63DzwU0u/qMgngPPCQHkooyCSiJI+AQgGTE0aC6Aa82AakgiBvIOx4T2hAqggngPCDQEWGWaNnA2BTCK8CqgWnnYpWBkxAOgRIa2HJpOB/yN4GTOHHoQK4saaLF4rifgXYFuB4WruK+BoQa4Hx8nga6hhBgQZYExBZfF4HxBKUrEFJBmQc3YrOSBsQ4+Gq9rOineKGMSLOorGA174gXWoG4MYQVGdq0edmIsDJYnGE9zcYrwOFjVYOuGJivA32kRgVBiuH+QA6hcpDzcgbXkMFmk/QQ1YY6n5H0FoE5WMl6taRGG2ztBSOJMEFEVGFiC9g8GAMG0UJIKZi1BPQUJi3obQaRh7o81FMHOgpGD6xxY3QVKCdBUwe+i0UsyHMGjB6uIxgtU29I4xGOkxH8pTBKOOpiqEz1BsHcYLwZ8ErB7tLlDDalwU0GlQBQhiKnBAFOcEHodwexiHUgbpUF8g/iN5hyqbwco5hYfwQR76sBIXRjoWY2jFhxY4ls9hohnGIBZfYfkORgOiNPJ5hwhZ6MsEmyoIVwANBEIW+RLagesyFOqT6Khh0hq6JVjwYVIbpj1YwIWSFyOUoZBg4EuWMGDbBP6HiFte3oGUEvouwYRQEoNQaiFt8DQYiH7kgGPKFTQR/JFANY7IVcHf2JctKFbQJuLtKxURIX9DVBkmEXRmha7l0GmhiFJYSiy/wYqGNqjIVMHXACTvYQXBIIQxyMAd1vO5qGT1ku4jgK7jWYtGCMkRjWwZoS8EGkKYaBpgYlyMCFY01IZITjUmYaDSShNlGWpFhUWHyAvI8IeejqhgwW6gHBdwFoIAOLyISxli5tDBoTImGK2FuicUPeg8wLyBqGZhVoVejcEhGFoogku0H4BlhWinUEFhcWPcj5hUcLmHs4i4SYQ3aM4WJhJhe+g2DfB0onNDQhStCyAlhB1JmFHhtFt6DQ6NYS3CbhZfISE7hMwfVgNhHIaRhWKK+krRX8Tqq+FthKAXyLRgg4VrRdM0YNWHlh7NjaCXhRYTpi0W7RpB4QR1IXCENBxjqBGZY6IamGIUQ5hmFa0awkebKcGEe2Hk6/UG5ipYcUGMF9Q8EU5i9hLIWuAwRStAnAA2F4dOE38TnEBFsh74X2EX25SqhjER7wSaDdhmYUzREIinu+BpMXYFfAb4FAt5S8YF+j5ZRBBWmxz4wkkUYJiRx4vJEiRY+L3apB+bMJFuK0kWWwqR2kWJEtOUzhbZ6RY2OvjB2WkaZGcWJnsgZFBo/iYi7Sg8nFQTMQbFEgXYlrBMwys3cNhiJMHkcEzBQ18NvLRAAUQ9QDi98tEDgo+PPOjRyTkepqk8qCOsBps0QGoBMRV4mFHISY2snABRBYtEC/YfVPYRSKOURJiGiWckQrRAayEGT4QkHvYyRsNguaRj4UCuiYasrpA5GVI0QOEhOMLUbdT08YwuaL1RgpB6bxIG/JVENyA0SeCuRrOHFRS8fkSnj6Mk0e3TvcUUYlFM80opHAaqenB6a4oHfO3izRG0W8yPc16JdgTUvkQtFuRFVFNFACLAoAgWgQUZ5GXRhZHNGbRs/NUFpkSUQUJBI4rGsgagu0b/wzRX0cdF7UWrH8A0s50XGLbRX0SDHIBZuC9HisTUcAG/Y3VDDHFYdAWlIooZUbVEZi3kTFHlRRgY/hbAf0T/Ds2zCGDE+RsUTYiAMmMeFGeCrxIAwoxAIEFEuRyPPDH4a/0cgEnsPJDdE/Ra0WEzORWPIDGgedMQzIHIX/uQTAxTvNvqM0ucGEzLRyYmzFMsEMQW4TR30TlBgcBciKCjRYmKMC0xc0YNGEUrrAVHdR3EXrFfybURDoaxJuqDgCxzKDBi8INYPdEcxysWRj6x80V6rA4WserEze8IKIDdUEMedhVRxrD7GRujLIkzSxkaFzExRZUBSyhxQMfIz+4cOnG5XRasTVEm4+4LbHXRD7qBG3s0cZbHYa/6LeySxMUbLgQsgcezE8xD6MKh+xMUY9GbsY/GKT2x1XubHWMlcS5HfYxqsbGCxeOI7FtxBMWBivYpUenGegGXp7F/Y6Jrjr84Q8QjHOx/3raCORG0c3H44qcYnHCi+EWVhOxRECKLS+suKlQ+xdgqrEPRcbLZhBxMUQEjvQKZBXGNR+rGsZ9xVsYCE/YXsczEmyzNqULc43CDlFlcV6IQQ840QLbG6YkZHfEFxVMTz5bstcaXE8wp8SNEsx0uCLExxzsVX424TcZ5ii4m8dlTtx/5mvxMxlcXGwSC0LBgkWIWwbLEkxVceBiHxSsWFDbAYcdEARxGGJBQLxMURQCba2hNgkmxkXHOgG4qVBAk38jCSDH7k48ffGEJ5tFnFYxtUdwnoJJCSqBIJMUblG8g+5NPGtRYEo/GNKh0RIlFRo0DXGDU/cdFgehw8cqwfanYZokTx38VBFAJaidUiroCie5G3hw6uvgNRECT4iMJNiTLicJMCR9BTht1D7HDRL0SHFmJZ0WLG0UJUcAmlh+IUYnIJ7ODMFeJR0UuHOhUMdVHXx6FDIldRD8Qk62JhuGVHWsZAFOaH8QuKInE4Z8VwlJQUCZbGEJLcvzF7xuCeDhuxECe9aqsR8bjqKWIOI3EjxZoZUnrR/0YP4Luw/rZHmehHAdGWsLOPuynRE1BMLUhvcbXGnxX2IDQiJaTOjgNxqMZfGI40OJkmzJ9cWLi6kOVJjBA4DickmjJHccrhqMgyaTjRI0bG3TQC/3v0lxUXOIri9JIyT9gfeDxLvFHJM/EL6C4sOPcki4SOEixnJ1ydH7iJaVOvxVBOyfhorxz3gcmks5IHsAKUiCYwnQqJuPJhnxiybAmHJiyRYEDOp6kapH4c7JwJjIZ+NckyRxhu7hpWaKXHyGS+KavhEc6kcim86RMXQkf46KWWyopSeNikpB5KVXZ0p1KYSniRLKb8Y0pE0oJHACVKcbJcphUpkyB4UUmSmLu3hqypkOD3CKQUBQMgnBdIXOFoScsX7HaQKpSSnfLVUQQCQRsEseJZpcA3AaMquCfjIISJQQ2ljxckXENZ6mpD1PxgJKBYj7iY4yjFCQ9QDgjqmCMW4HuglCFNEoj8kMIIYF3KsukfxokaSu4KcsJ7BSQy4knHUpI4zNo1wOEV2CKzP8vxOuBT8CaV0jA4c1J6nRpQZK7EQyTBG8iA0chKsx7sPyAWmKpP2Nvo5pWymPz/ARTLyBaEpNomkY4r2u9gNp8pKWnPKBhGmkm6lyokCEx6aYCoRQraYaKVpHEIkrZpDxPWmdpw6WRgDpoynKm987ac9ClEpHISSLpcOEzB6avqTdrKmKHF2ntkuStnS6pS5IND1aZqRGknp9cvShk4GAXDjmEVKAiR+pt6SunTpP1uygfY86XpoJgGBHDgfpUTPqkfYm4ITGapMqQBm0Es+hOn4Gl6UEiqpS6bIRY8wGaQSHpbqXqk8E6NtJjcGdaZBkII7we9SFpkPM+l6ax6dvwcIBOK8Q4kkaeTDbocTNem5KGCm9QPp26QPKPITqW+n4ZfafiDfpaDgRl/pPBExngZ8ICBl0ZEyJbq8GVGQsgwZj2AYwq2iGQ8SQiLOP+mcK6uBhmFpP0CDjCZa6bDDepjqVx6Pp12B+DGa0SDemaZcmeenb8WcshlEZgUEtBqEGyDRnuCP0OQRBIDGWDiqZ5OoToKmDgoUoZRMKZxleZzGShn4ErmW9QIZbBA5kpREmeaGk8EWeZmVkAmaQQpyJmbQD/plhEpkiZwQjkJuZ0WWRh7aaWYwTbQZ6Zhl5Z1aYaS4GJhOlkbpjXFYQW4cISZlr6jhAyE5Z5qYEhUO7UE4xNZ1nqoRbItaYWk0YSMRplVhVTBBm8OthARy1+tqbw7rQPPDakRILQnel7UzmXcr8YNmZyQ5CmBp/Zvo9GcujOpyDqcDeZfoJ1Kw4EnNxk+ZQhDjrsZSWTwTzxGUSFmLZGWcFlDZn9mJmDZhWfvbqpLmoWlc4JmS9nfYpoKTwjpUJClH9peQu6luZuBjUofkV2f5l1ZV2JDn3ppmYFAg5m2funuCAOVek6Z26Utl/Z6OWDifZ9ImNkzZn9m9naZcoATm6u2oNwZ/ISqX1kPZPHu3hGBa6TbF7ZlOVGjPaSaWVkluAMKiKQmEKHV6kZ5pHZkrIWLMVl6ar6TDpC5Z6csDzI5LuvjiM8mDFSMkWLHOyokN2ZV6EE4mTTnRUYGcbovZPHjoTD60mXvBU5U2QFmC5OwIGksZYuWblsGW2feyppC6TTmupemjrn/4dOWkm5ZXPE9lO5chB7hPZrSTGFipy9n2xoGAzCTkr6qUnzkgaOSjwRn8EeRLrKAVgmOmcSsuqICP8GEFFycs42Rk76Z58hnmk5sdszYS64OXE4sgdBG3jx52AuebvBpVFHn4E6js9oh5mecIRq50oqVTVQYeZBTN5IGm3l2pJIELGt5jeWQnFpeOgMSk5g+cDoes/6WCjZ5mbhMzl5ylNWrjaRefhR85SKaJ6aKpEk4Zj2BnkdYTE92CHg1EGkRfTaJ5ROXbb5FoAHx75anAflMp00iJrlEpovNJ35zRJfkTS1+WvnKyG+UMRb5r+sKL353+XkFdERkbES/5z+UqDKKO+SdBgFV+as41axQSwz7gDJIFC7OG/LewNUpuYW79EVinlwyuFGqmTNepbi5pRkCritm8gTciq44GJunagAu55sy6/EE0FQWvO4qG1kPEZBWC7ekchsGKJQ3rnQW8eXzgQXzZBqIbg5uezvSQkKxBSLnQkhufwWfpN1ACQ4FbxPGTS5GBZqlFi5BfKksFf2Om60FUpJoXsuTjCoVikbBdqpEkuJJVDcFOhWy78FRTFgUluiLiWQoBoJMXDyFp8f8QNcFLpWR4FQMMgVdIcZCiIauGbkvrvEhhUO6ukkZKoVxuJroEWKFrzjGA2I9QvnqvOdrpEwuFgpE64Vk9pKCRuu0hfcQ2FArnmQ2QVpNQXbQ6Rf0JiFtrqG5GknBdC4lyOMtqSmFrzsa6PIiCdWTcuerpWTGk1RZq4wUremUXeF+uZaT3RCsXsjmYSQNgVWF/yDqSNuAoH8pL6kxWYXjFEgi0VGFbyPILqkrRUMozSaBYwWbuS+v6AyolbjMU2maTql5tFmvrIVd847uGpnFrhXkURhIAFGFD+NkZeAJhY/vOrFUbvDLiHF5yY3HXuZap+n1FZHjYgwpfhYCW2ZW0D/J9eN7mNmOFXPGyIUFOrEiSRs8bnDkPI28rynfuIuccBol9PM66E6iBdd7ZFNqTCXneAvtOnrAEJbB4rZZuP6RoeQJU7wtFvPBe6W691Fh6CgwxeebvFBJXsDUyrDAkWMltRRClIktJRsii4WJQWJHe2hQ4mIl//g9QL0qha9wnkXDAjztUXPH4AIylZJ0ih2qpbiVmmfJf7gBFsjCyWfuP3sJncMRpYLwokrpLqVpkG7l8UoBWpb8UT6ypV/Kgl7JURDylyrEyWClSvObBOlwIKKRTenxQrI8p2IP8QaeqnmjR5xwaDx7CejKe/lp8oZdGWSeeqImWiomnnGXaehAlGWioyZWjSplRnvp7cpQBSmjZl4Zbx5HEGqjmXGecZe0kSpcBQOy72Gcty4IUH7I2UmCkWqeRH2Fyvl70uTqh/Z7iHRp2GG0g7n6CDlaPm1BwUHZe/ZX2CHK+T7kTencq3sbJQA40k4DoTlzlgDhzDzFA8GhEwOlhVIgIONMEg6our5NjDoOJ5dpTiUq/FOUea9xQQ5tJTxaQ71lNZlI7WeouGRS0OmUOSDyURXrlAmO+uB+V/l4Mp/aYQ9jqCRh5dOlDBYh6cqrTS4jkvZiqOr2TRKGqLcNI5wVy5X2YKO7XlJRteDIWI6qYmEIpgCOsTvvYZcujvDgn20uKYgnkPwew7uC35TRV7hfLtgpIVOtNBXRGuSnboAUT1BjnK0UFS47pOPvvxWJOQsnBUCUL0H45BAyFdBXhOH5I15vwK5epr4Vl4P0a+OJFe16EVTZvOhwU75cJVBOclV+BQVq+ZmXVOYzqd57A9TmZVbgeWkWVBBu4gs7fYb0KVrx2DTuZVJai9sWUywDlUzaWVPTj5UZl7gaZU9O1lc5XD2rlSFXWRhQXWV2RjRClTZUVvEEwQKN9Gk7yMX4vwwPSFsK4nqiPFEYRIe8VdxrswmbnlVzR6SBwpRoZ2rtHbm0EslUFYo0ctRJVpwKZgDRu1CwpTUqMa9KJUrVRmGZaLVbFWxUPVZ1X8S4FWrG4IfwA9IKmvDADjH2uVeVVZVoxSPIJ8FVQiyUeu8tHy1VhInhrjVw1XNHncv8sun9VCVYljHybVXTGHVcoDTLnmkwR6aSF0MjkJda11WySFC9PANT5VuVLjJueqtANXKSs1VLEbUF1XNQbQX1XlRPU6CEDX/w5Md1UdVGVKI43aYNRAZlhQNSBqo6hGIjWrUREHNG8FSeZ1oo15bpjLQSQuRcEemWJTzzfOV1RtUk1g6DBFE17VPZoCgCNWdWGkgbCa5zRvVERqeBK+h6alVGyHNz01aSFVUUaG3nLEK89VRRoJKljFDV5UANYVQS1SNcVRC1S1HXDqs+VY6REwFOSdU7VcAiWkw17VX9X7UvHvYwE891D8TXUS1QVWbZ0oMzXXVdHk/aE6KVadXC11qdjXy1LVW8QvV2sS7XzqZNQ7U/EZWJDV81yRZTVC1XNeyWC1wcUpVKlrRrDX4SyMpWRi1L8XPw5VsWW7UemIZNOm1gvoSnV2o9OSXL5Vu1eGmZVv1cTV2kW4HbVzRnBbqkTVqVVOhga7ujdS/VN1BQVrUHpsVR6a6da4zaunVc4wtUiNazrHUYdcVRFMygE1Ud19hcjXO1ndWsaFhHpuXUJ62tfbVvVExQWRSsI9beUPFD5VFU3QLxbxp4xTLEeWFVFGvqC71ySm9QFeVNYmYeMTVOjWKaWdYzV5ActYkw0kNNeaSaxGdTSR0gkTGCz61gGsKKbVDpnFVqa7pRTXei0mlx781j1KXVr4agHjVyGddWpqfKQZJ7Zn1AxBfXqiSDeKA2+/RKCCE1bUCLX9EO9Q/WXg9VbxpIoFVa5iJ1Dpv8RqMDiDXUUNTVaVDUSGkjykjgVNArQy6NkFTSBIOKZyYllTvCw3Y0kZZeB8N3NBHaeVfRMKiwgxWnzBsNTNJI38NtlYfn5EjNKYhgEF4azRla7DbI3CNHlXZVpa4jUI1HEglpo2RVcYdFWdJIGPWK3SfDtEIGBSSrsDW0iQsHTZUt7D8AUEBnP0ZAydjdY21wn1XJqO0/8GQlqlFVL432N6gtBQLUcmqkQrUf5InSWNbJXEpW+cEoky3s1FksJB2KNWMS/ARhNE1QsljeyC/yywmE0xM6BMO4BNjFTEyl0Xgmb6qU5Td34dcsjkyxzcv3joLa0xjBdJY+HXNNAc1GTboQvIB8NlHJNofnU3RQrTdh7xNSwGyJJN4zYL4dcftC/HBNl8KU2wa8zTbTkBsNcs37O8DtulYsfjUrSbNqMRE3TNdwJgjdU6ze+F+ShVKc0tGiTd4xXkBtDF7eMcTZRI0YR9OoyDNzzaTJQwmTfs4SOISj2Z8SVzek0CgTTWc2FNfDBU0nOUaFub4aYLOC0bNA2Ps1At+wB7SQtn1DC21NpPqi1WNNtP4iFs8jGi3gIOLf1x0xcRBrTrKNjZY23NK1NkrXNq4J41O0kdMAi0tgdDyZbAdVAc2vKAvpi2PNngBR7nN4TUU5HVcCKy2DU3TXS6ctJzc7RcQLEjgRe0asfuDyGEyGgSyt3jHPT0SOBMc3QtozZRJCtZRjc2RNEintBR0xrKc24+zMEy0hNprUTjbNFrUDoppWLUW6BNlUO9KZuOravwostYEfLqtULd4wPAWrii0StUkldKutIrYi3DuiDGU3hMfzTgrPcgNaIz+AgrZj5mtcbawZpJ/Eo601N3bj4wRtyzftqUwSbfnS1NduNPD5tsIIz6BEzPOwzstK1LiwvNpzVSw5NNzcy2lES8PYxVtDVYqVLNWrTy0CyMtMa1TNdcP7gOw21Kc3/atbfa0wSSQIC2UtEClDoNtDjGW2ztT0qq0dau2oC0Pkg2uS3eMNFJ9qJtajPK0q+M+Ub4SsE1PuCF2kSD20RG3jJ826Ez1Ze3hM8bZxL08+pDoyNN/4v7jFte7QW3gIo7aTIZc37Wk0NNobeIB+5zHBWYmN6zmY3egFjQXH1iw7jSS9tMHcC2JE8RgXGgIv8l6REtlcfAhQe3mLqxPCB7dUrQdZLAHi4ShLi82giSHWXwvNEAmT7ItuHdzH4dGElB3UdjHYq1Y0c7XPjjKw/Iy3+4A2GS09wEbTR1UwxlYFVb0uWrnRgoMDO1IfqEnftm2GCnqI190Z2uSZ/ALhlnTcasnap1cNMpvkTidVbM1StEynV/FN0AVdEFb0MnSXRlQS9CAG70H4Np2WmqKv/62danYfRX0RyXZ2mdske1x6d0WupoudFnb534M9nVGaz09dBQkmd7wj53hd8nW5CCRYrq3QXa/nRp2WdszNo0KNY3E50xSpdNNyZdFzLfTBd/prXSZd7nUl1GdiXQV0n6/EmF0BNpXdV0+MMXS3aKdEiDnrFaQDDl3QoYBDSSL0nnbintcJ6G53yRLnS12/GbXT13cNDRMN2QN3XRYrFdXXQ135BOjRfQ+dlwFp0GeynZcD+g83aMBxdw3Xl3j0M3R13dgqBVt15AcXVF1xkLned31dFXX1IfwifHnSVweiod0PdHnfI035/TAF1FUSDJF3JdwgBd03d4uv13+S2Xady7duBvt0AFp3QUHgdQeQgRciATMDgdhh7ccAI9U0Htpnc6TG3SdwJEvfCo92PdW1fg7am3R+CD0jvCMtwfBSxVdFqvKYtMqXAUSY9p7atUo9HzWxEPSA8L82/hLbgkwxMkETzIoYsbRTD15oIk5WatnDIrSvSHcP015qG7YSzDtgvdTongPanK3JQqBBALbsxLerac98PSz07oGPQEyM9L2hOwqt9TC9pDsyvc/AjyYoqE4qttPQ9JUuXTSUoY6IkrEBctu4aT3SAAvZjKiEVvNz0KMJEWz3RMCjCb309+vZUz1u6TCHaYhbPRH38sdmAUTRMcskZjVVP8Nz1yyWETNSX8drYXBlVx8INCZMQvfHBh5+fdTqy9iUG3i89pvUr1Ay25prRq9PyhEyfSuPUkpBM31cz18yG2EfJ19BMg1ZV5MMVX15MXvUoRW9QhJDJO9EvUX3dqmbbn3b8nTMDqZ9H5KP0naKfXkLNMm2vH1RpFvefKEiFTB30xQKslA77KgEXr0dpb6iN4iSFjCsqT9/btP2BQ5rG7379q/INZV5CIgf0cQJPc70i9c6az0juieGDhIl/mMf3PQ//coZr1/ubWVeAW9Y9TklIbUVgU1VniM2yCjyPK3W9fDIBF4N7palRxtpPJIZIwkzaICJpKRNQKAdrBspphcDve8CNUoVj43caMaWBzq9KrbVgQKDrKH0UDShFizogxA3H2dMmrfgO6EStXL0K09EvwOYD1kuAjcD3jIgPntv0tT3fO5OegPW9csk2HKMyAyP2DMEoNvUYDmUHUzp5OdaoNE6SNRwMRQjNBOEga/jEkoCYpg7OQW4v0h3IidZnYVrT+WsnCDzSGOMCDaGROgD3gGrg0sa/ayikgTuDe0mN06dh3NegrM/+IEOGS3g04MRDkPaB3vdIUrrY+DvnH4NuD3ss4PGN4qRB0Ry6SVGyks3oKKzlqcXAnFxUUHWJj4ZVScTTpIOUJXIjRjYdxgcI8rNlSlDLFlhjdU+Q4rgrydyVjTcRnQ5/FqwMwYoh/xa+JIHqY1gYwlek9Q9eh3JEw5CG4sjCe0O0UxLIcnND76dSzyMdQ4jZPM/URsOuWFrBVQrDPLLXELDNlg2bDx3Q8o71aQw/0MKUhw8hrXh6mOizvJcGnGyXDw8TMNo2c5utE7DdNp8yJM3wwazwg2w+kEhWhrC9HHD3VnsMTU5w217Osdw6MUk24zaVF8u5IRPmWsgHtSF+sI0TY6C2bLP1E2kYtjRXsx7w2NZFYYTMSOjp5wddH4jD6JGwksVDUpU4jULMknojPNgmw6MyI3I5faTwwI76s/2vMPVg3EbSPLDaSIrj/4lI2rErDu7hUM7DCwG3gYsAmvDhmhco9yNkkpScqMrJFDibhKp4w9XXvQ/LOKNqaFAEqOnAYwGvhGjiFL5qtRPI3qO4jhVP4ipJRwJlSAjdo6qN3FoA3EMB5azioiSpFnkzzRRA0aPGCsCYPUnriaLGSRPD2dDVyGWnrBNSRj1IfhJ4xYdaizRYpRL8N7xiuL8x0j+Go8xUuADvfwvyv1Z8q32+Y4FHg2nmJmOHJxLKyxX87MTTzP8AGU+jgx63NGOKJHpucG6Y4nhGNkY8Y7IQWxZdWNEfYGIEtHJQzCRxCH+w8XbhRjHEEUghj3YzzaJKySV+JMRb/bvBh1d/gDaAxFQ2WM0j0fCNEsCgo6aGzjRY52FaswYzrWzkELCGx7jI8GaGbj60aGNOs6ogVFxjPNvoy1jd2gNaDoBY9rFvxY460PZjN48GVNd74BLFH4H4MHagTq+B5GipJlfmzOo/wFBNpIwdvBNgTCurEOCRA/QhNVsqcMhPO0/eNBOeD/dihNYp4E5nb1yJE2hOGRXhoHlb1d9tz1HuJ7IpgcqEcMqxfsaoQ1bzs/+PObahHE6Ei8dFbEqGlG2pdOw3h+SiMhfS+HNRy5IdqqqVzsQ5UGgWqr3HJOkRY0FE6qlVHBGqrsWrH+yBOvE4GWU00yHOhiT4HjZC8SXwEJPs8jE1JN6TBJZBychoNoD4ocy7MxMElQDIMJ0TOHBhwzs0k1nAjskk18DfiL3H5NSCSFGpO4cY/DOwjq87AiIUSmk9FOUckk3OgOTliM6jcTu0MlPNw67AkK8qEcMFBOTFWCUr0T+MDRY2qPkwCSDd7k+0af9BCBFO6TS7H+4pyIk6NCBg1vd3CRWhiVBR/IxUwJNswRvcnD5TcU6EgDi8HFFNDTE/IhK9T9A6D5sTKk51PuIwZtDbNTmg83BXs/gkVCS9KUyopPstZtVNwIj7K2XJKWcNDRmTHk2CRcei0zlPNwHwBxLmTFHMCCISHZtAMakW0x+yjTliIkQUS3CRf0rIH09tNVT+CD9A6TAU09N3w1040K5QIM/vCcWtDi70yk1km0L9Qv/Skj+IA0y9CrsKM0uya2sgO6MwFbsLRMKEkM6NVGgV6Phz3sI7DhKkJjulR55q207QqtTyHOhLSqRqEYww63hOQSVh5sZ5MT88HHHobTtk1ZP84Z0kjzLpgyjDAWcU0yLPWM9fquyZjF0+EKc8EHPpkW+mekezi+6INH7LTC7O1Mp+IlPTM0zH7KaKqz0aBTNV+7TIh5hwRoNL6azlcv5P641sxTDEzzQfbNwS6IHYNedMsFuCpDgvFZFlsns/xzYhBkSI2LdbHH7OuojYMHYIC/s9hAwTonRbaRzPCDDJKRd4qHPPGX4IHNpd8Q9U6tyYcz7MpS8c6nMp5oqeAOw9ItMYNJc9ahu1GW707IROcF1VXOgzo8R1Kucx/uvEDM9c6kiyOGEmXN5cm5gVxNzSXGfymxuMu3ODzTvVqzNzagVdr7iaAb3BxK33NTiooIEKr0K8gOD+y9N9eYAxA2nPtiBvRJVOX264OKLvMgagYIKKLzl2iBpEQ0Yu/4fj78IzTKiVSLPOUS3c4b7M8IGiPMRcvSv3N5c2Tato9Wxfh/P8Ez8z5za0lcxPPcMtc23MTzdOsvPtzffoYLmsgYqzoFD8OrqI+ciPOHSx4FIhtqiEm8yeYrIouEPOlUM1hiQELTvdFSWc+C0HY4LDVkyL3ETXDnl/zPnOjxHyQC84wADd87QvQLQg1VaDFVOiNT8sJnNshckR8xLpAWxcMItMR1eWcAoonjOfPV5W8yshcLRnBTRz0TxF35xKKiyBBqL6ASwvw4eC2gs9RkedIspIouMjr7zs0dqSmxdc1As6LN7Ywt0FMrCHmILgNAAkoL3ouIsc0tfThaCk+1FGOhSqixHDSoG88yililiEEtEEAizFzbIwqH4vkLYXIoueL3QhwsOcLi+wv2LwOI4usLjBkIrJLrfvQuZucS7wtULbA5npRLt2itqALIS2iU46wOpot/Y+XP+2bWAJEdpjzW0O4vlLyOggvv4jXIYuQLSXNkt/wX82EsALOg+3NzcOSzQsOcowJks8L7iCOC69sfafP9UnPeYs5y7rcvNNLDousv3a9FhL4FeWvUpZDwnVAAPjzSXNMvwL9i3G299hy0nApEhCwzLtLeDY3MeRIqA1zytwkrgs846Ax8uhWLpZIa1LyUAfOPUhC5yz5iwy/ktd5YK7cuY+0NbBbFwxyxou/L8K4kszUny4XLbL8IODWML66rDF9LenDivCSpy/iuAMji10taYW3icttLPJKFIo93Qi8tIiJbKgSw8uONViMr3Czdg84NKysvs4yICJgUriKw+bnoJK4YKZMMoERjRUTUViv1zAzJHRvt2K56XagIHbjNme2Q6kq9m2ixuh2E8tmmxukyTIrShhQ8AgpRcwUPOY1+WZOsDNy0xfUvmYI1MFAYG2iweCWr7UDqvBYDGKHDnBhqyJTCSKcg2I/spi5Iv+I6qxHD+rKTDyYhQt2iNh1yf+vUuUkyLeoE6rS2cJJyovq7dqjhitMmsJrYoFIBuzvXQ0QMeW3Mpy9c95NqjbcMc/YP5ErwIAiioouqdz5r1a47ZBDDnQsR1rnOg2vvCLa0wilrhE/0yVrA3Eag5dhIBdyIs3ayFLFroqF2ug9YoH2sxAGQzRNsqe5Bf4kNJQiavBMRzan2uYwTNLRqT7YFZ5BIaaj0bsYm68eQHrK60AKxqMk1VDSgQ0eM3fsF0Asgtqq/BusLRsgm+lPrqPOgGwVAc/DyZN1no1BXrXSKgigIVFHoY4ZgGwes0kG3hiioIWDedAvQHPnVGmqphKevvrPhFRTIb1PPnR8zQ0PcAZICLKqp2p6G2TyCqZmTOkhRiG8gSVRbmWzPgb+IOvEvuMG0DDyR4jF9r88XfPYS8xl4JzxFq3nsgFb8tGYOjj82tI4TsbJvNWpT8Kcr+G88ogKYRZyrOQnzrr3wITHybeQg5nWxjzNJsUbEaXSQ5jF641C++M/tFD1Z2ELxuSAuSm+vIBXgFxvmbwAgXCfrxm/RuhGm0JIDoZHuEOrvY1m+VrbrHm5xslCX63QH+gr6wLjixmG2Hkgbe/HKOsbm0P8BIxEW3ZuS5xYiFsEbKtmTHKcuAwLCqgkTIAwOwy66Rs/Enm/xuvC/Im5vy4PGxrz+l0hrluGkHrBetMb9/uRtiGAmXgFRoCm/FtUoLWgpvRbGgfVubQqoDhnVbU/H+vb6crLeteYgjPniv9b68LEccl68Fv3ACm3EydMumwJsOxfG/ZnLbYUPMu+bxm4y4BbnmUFu0UMLVhthbbXoduhbDlApTTLaW3BvWx2gzQbrbm7FORh56G6HHTbY+OSFI6Cg29vOe+uDMyU492+17ZbEUEtBI+XlhIvCb/22DtXY5m1RW2bh2dDuI+NG/H5iCQhINuF+pcETwnQdPm14ELGO2/Vmhpi59tbZ6mAjvAbI+Qk7kgsO13zA79Y5DuLQ+2YYTFehmwzj/b4C0ZuFblM49t2pcqMuOQUMIKQTQ7vO/QPcbpSXXTbryG/himba2+zvmT0aHdvS7uoLLvfQ620qvQ9mQyXMsMJAZ/02ed8a6Sa7sDjQv0oLxq/a38kMbQBvlW0ClFepr9kBjKB0xebs27dpKGnG70ch4z6jjm1n4N62XlruMgv8EEhe7g0EVxyDv0u7uB770IQNa7oe8aDoa7u+lzLjYLFA2wbsewDYYqr9mFZh7GEDHvq2ZsR3De73PFHs/wuewGBx7Ge+bsm7YLtNs2rxeyeCZ7Du7aJO8Ne8ql17uwLnsJR9KMHul70gDmvjdfREjKdk70sHbB8pfHHhvd8ZcEFRoKzMKhkAnAlkLhlw++hPATvPInw2gT+IVIJ8E+yPAjru4oPuz7K+8eLb7AfOKCb7+bPvvL780mvuh8h+zWVPFWQ2gYLscAtqmd8C0cdrzKj+3tS0GB7aMq0YJ0db6HZCLA8kzksWG+k+91VIcIptt6egIIoH6r963pYKUV7negBw4J/74/AUKwVSB/yISYVFNv28b/fJlDluQ23fV+eP6bvzdFVvTwQv9XW4SxkHI8BlHICJgsgJNbr/CaktwzG2HB0Gn+2sk/E2dD/td8avTP4IHg6a/vy8oOtunisHB9iLpEcwp/tlQa/s/vb89Bxsj4Szvuul/AjyIoer85B3aS5a0B++nEH5ogiKSHkLE9hdIoImAeQsS/PAdStWBq/sMiK/C2mCHR7tt5w4X+wDESHB6dQePIseDl6wbvBy4cNa1nlocZIn/EofKmFAGdAq71EyypPldkbzxMusG86g98y/Idn2EzCRBx/67gvEeJpvzGkfzC5mpkerZZ2x8TGHy6B/vtg5hzfTFFH5E/BKbI+dZ6GyGUdR4K0jG0b44Z5R6j4CwEB/CLFHsFQvhyb+R0lt7oGOqkcGHyR70q14FR2xtI4eRxlC8Zkxx/w/YExxluwB8x5tCFHhooenJCWctvrZ0HlGwRruBIrRszHVpAJEL7XBMERo81aGAjNEMIEfu3443grDnHaNKcf3HZfDcfu4TxzwLXHaNHccfHJ3R6OwTtx6L5XHanT7mQCpAi8dX7UVTfsIECLMUJA7TwoCwsKEQnEgNCW/bhrpZS/s/zHyKwrqDqg3QuJZxOrGIoIwnt3keRnIUggUTQoqeVJrTID0s4ML8E/PFyk9ZyO4I38b0dLLYnfztUIDMhhOlnUnqvuW2wnijn4L8E+J4o6hCJVHbjYn+go4uSnyQmQmpClEqKdmEiwjzJuIeQpkJEnzKG0f5C5J78yTC8+WSfi9r6hw7RIYwuyfJCQPc4Kxxcp58UsgubdidZk3wroSynyBJPoJCx8h0LLouYw9JqnfQjZBdCGfVqcjCXHjomk9IAdvzbCq1RYhh5kZ3b0UgQhP0KhnAsqYg8EnQhTi4yrmmwQj6agtaeun+2doLcnDp3jLKJAsvERZnbqNawZnKZ+ILwn5gn6NCEhelyem8sXrw5lC/bisDaHOes4LMhU/I2f+CApySelC4p4idd8c+o0JYnyQo6dFR+2u+ir8XOFTHmneZ22c7erEgYfzn3Z3xr67VQv2e/MtyO9hy5lZ1RJ7nmUFyReAq1R2cB7rQgT3vAvFaoKN9PJz55enhZOEdgdmQ96PPlIcICbBHf5IGBkcPJvYIRQf5HsAYgR8PGfPkwEAuf5wYFwxSgISZz9AAXKFM3tQeb6Oqd4yBZ/B0tnUAsOf+yS/odkvIUMFLOpKZZ3cr4X82uXAPnWFwiei0UmoBdoX7p90OIXbrPs4YgDZ+kRJniEaxcHgzggxeKwwF+e2lQ+p8BS/nClqLSCXiwBNBkXStNxyrC2FxxfgXZUGadSX0F/vaIw+jMxeen/oCWcCXEXvvYFwAZ1EqWCwDupo2c5FzCDWEb8iBdEXZPrpe4nmcqOUj8qwpILpr9lwmfGXGIF3vBDBwrzah8Z0kWt6LPl2eevHfXf5dJ8gV6dx9IBxDalDSVE+l1eX9NvZSPsvXC3LBEcSGFcj7/x+gw3YCV2lfSd3l1rBRXRc9fvq7C6yQFH02pGsBvU2dCAE7aFV8JmAxl7W8R0guG/iBlXpXGxSub1V7droSF0S1eHaqk81fBjoSL405N8vFhjQrG7K9yuIQ11NBEtyAe1AvwkmpuDEBpwO439EoNnVt1QFPMk2zXGvLch7wcRAkIdXZV8NfUig16Tr9XPyLPmYddBTWBvIfrCh1JpRe4aJC2q11DiamhJB9G6tjXO9fPXP2A22PX/FY97SIN16pSjXnV+9RNXhTLtfXXYLE9eQx4NyOBQt8N0fSzU3JfyKNwt6KjKn+X6JJjwy/ItujwYzTDtf1Xe+kTdX+SQm+F43p/gnDsoq1Idcu5UFeKuXkI1y+5TIMi4hplGyAetCvs0DKDfACs/k8RgsSFkYH+4S/sqSw3gNziWFNv+nDePeSoDhxC32FOIdjXmDbdeS8vV8MsEgA151ezU0gBvzriTNzhJUwDIsYIoop0nlIkH86ErdM3S7HMdnXNt7LdVXKN+X2A3Tt05inKJt2zciY4Q6pWs31t6WdlGDIvbdLiFt+aKlX7t57i+3bt26I+3lVxrfshQoGE0YbwdzfSBga/incXXO3kddOYbbApVPRGd9ezOeQN26I5oSt2Dco30G2xXl3TmBUERGo19IiLqsoKiLo2DbZfTE355ka3/BcIPyLc3IwcDLIBNNznIO0p/tSwmh3V6f6bX5QTNfk3GNzhiQ8Td6iTh3Jd7rOG78d40F53yAbPciYpd0GSLaS14Hr4wat5gEGEtN4fd83Daafe/KRd0vcdq499XepqhU0Vs63fkEff33HakYwzQQdzrccqO19Hd8RjwKJvB3MeXXfF3Q4T9e8bU1z2EUwZd0d6d3h4a/cvu8Z4XKX2SNxu5sVp4V+52kONse2nhCD/decR0D7vcy5t6LMjgP2d1A8tTq90A/T3/wC+exhau5APC9eChCLtXTD+5iwiIDz25IiChD0iok+Eu0uYiv94yIwkJIqw/3wV88QrVXDIsfB4K+Iu1dii9XJI+dlgvPfOiP/ImyIiPLDz3dyiS6NP7UiivQmLBYXtqKI0iEosFhi3K0R2LEiWj3GIaPNmMyjtXAYu/ggYogMmJLw1K/qKJNyYvAjwKmemE3eP9oo3IC3de2h1tyI8BvdGiC88iK8gKW+48+i14ZlsHOWmLQo7XYYiI9yPf/jnCdiGT6DGtioeqk8pibCgk/Uxpj7Hp31tAJ6J31oS4WKH+VKCWKiK1oqg+AMVYr5g684W4U8Z6dmhvxl5p8y49xiWT9Y8OP+lMqsj+nSeJh6SPYDpj/o6oQpIS0oNqVPr4sz5VGchwYzebWCGGPqFH03Zi1NEVDxKkYXAxU6Ek7AUknhYwau5aII0VZ5mc+vTOQjhVPmid3riJmPwBBLyR9CQ6FwSZ5lUIYYY+Es/4g3GD8+qS8HvSG9gHz5M8Uzuk3VAKV7FpJNaVFz/WYroHjmsGXPrZhrbSJWwKpJ3A8zyI7roUbJsCYvv4WiFbmeLygHAvHqyHQEo/z92NLXs5veiBJyWES89gGgr0rOJolMS9aCELAC9Qg6oZRFPogLw8TcR7z2GCMvDzxC89wULCZaizYTkkDQUEr2aGbmhFdtYivzU3pdVGcIQK8y4GXFy/r4lEXC+ES+L0GDP2Va+S8MnYFUa8wsvgqSI2g6L1q/qSIjiSzivtkiBLsUgskK87hcr4s8YvaemqoevWr18+QhDIf4Ah0JIJRFkvMLBIIwoc6Ly+oSyDaFgDEzz5yBgoIsoYlfooL/KfPaH0Na+AgZl7facvKNsxJeWub0TZJv0Dji9dmIxXBGDonzZyCT6HL1S8h0ZpiG9mvgIH699mQhvSArdOz6lwsvoL+W+xvUb+RLAv/b5cAtvzr6y8dvbz3G8OvChEq8vQ0r+FbTvRz/tBR0f1p2/Kvmr828CT3FSq++glgqYlIvutL2+YrVUGsxdmMKZS+rjhEvxhYvzU9RW60NqRW9LvsOHgzgvEarfTAWUJOm/WZy5ZsD3vfby6/ygV7wS+FvXJErbsUmb2pKSvJmKpLflaYT68/vfz0KqOS8H7u/OTQmIzfWQ7L9hGAjgkhh/Fv9mKqxesv74Yn0v7b4B+1vqbEWxImGtgFgnvAHwh8AUpbw6AxAkr5G/gfuBpB9wbg5fB/XP0DpC8/mwODO+CvdH2sLevQ74DSbvYH7M8huPL/+/psmH3a8CeP5tMyxv1LE8zpsUz95NwfeXeC/SJsn96wcfhb3QOBJ/b1awyfrL2SzyfD0Ip9qxmVHh+cfan2Swafuk6GxASjny+8nQ273FS2fFb7q9ef+Z7W8Xvfn8RI8wBIbi8XMI715gnP6bCJ+7PJH6Cx5Agnx3diS+n+6/YfLzJ/WwfWGOh+jAM7wSgTPmsfQkzPqkpfWRxRX2qwkvooS1flfTn3Q+ejsBdEeoIUPrLRY200Y6pASK3TC/frk/E+9Go17/1M/litljz4wcAt7Sy2C0SQ3Uv8NomD7RkrFs+ur2+kq4aijNiJSCMBPKHZesLXx3xYNtAJ9bj8L8hKzugZoPLymby73iAVs+t2KCltFwMFgiTeh5d/tfqfoMfeE3X8t/bKiSDgSdgXzGN9PRbX7LTffHl02ttgQtzZKn5WQevgg//+TFeZz+bG1Q2SGdmWyw//kp3bpXsc2xxlOrUkPZiN1gk5LRXQc7FeVgIbhD8v54kYT84/Za+7MLEeYjZIz2bDT3B1SC9rthMN2P2PSP5zP92Cg/8+8HM8NVQjtL/5lhsk1E/UBSj/lrKaAiJw/Odl8fq24v7tpBX7aDd/S/SQCmWU1udPD/C/FP3sSmhvP8T/8/mvyz+y/Pe1L8q/Ev0SmG/89uT+5rfRF6SC/80lb9k/+vzXiZYGPzb8clWv0L+c/+PzXjy/SP4bYOBXv1AzG/7v9D8mGLv/EAc/lhrb+h/kP3j9B/bHLZgK/wdoj/+/Mv42shd/UnT/e/Ec/fD0/5v93s14Yvxn96o+f0n+K/Kf4V01Uo0qZJN26jen8O2w66X+DO6PwX81SWOHb/1/p6nH9N/V6iXLx/9v/OIUwTvz4H9/rvzn+eXfRHmg9/eZcr9m/s62s7FXmzmKC/2aVKEqBK4hkyyqYOEnc5exxjOt7vOcUG+rPJjXhC28s21If/7Op7uww7/R8heE5OaVCLLh0qV64zs+UslJcKaPu5EUdNr/xxN0ELYY//q2HLi8jGsckBGMc+QhCdJy3/Df55wdRx4UW/7TKIwh9IHKoDJS8C7/SJyfUdf6iyb5qdwF+JAA5lxK0VViw1XyQcuFhyL/N/7OeJWigefmA09DEpkAxzTGsXAzAAp+wv/Vxj8YKpQf/JgG6zCFy8yOKiI9M9D+NTgGnWD6TQSH/6UyNmQrnB/6kyUGzf/PgGLXUgFCA9vpsMLJpSAtcCXOIgFrNfmTo/SxjQaZQEoAmfoKTOJQzOOCjNMKgHqAkNLAQP4q4AsDT+pPaCQefZxb/YpQVsI6p3Afhhl9TiDEeb0AkaXNKdTOAFoXH5QgcMeCMApJSlGJjqcAvJixKJ5reAvFpKAu5zn/a6KIaUQHMfCSiDWd/5iAoAZf/dLx1NfGR3KVZTPofZwCeWCpZbZAG5Aw7Ky8A0h9KcIGZA9nDoA/wEpAhS53OCmSwZA5RRca/4yZQIFsdFAIsVb6wtTc9qOAtBS3padgsSdsJoVLjhmAuKBVVWDISAroFfgNfRWHFoGZuM/jTVOHANA75oWA9dLklFajGAntKdKfQEv7f6y6EeAGyyaKyVAqAFT8A4H3/J4SCVQdrvOAAGjKTpSyAlYGLKW4E6WUpQ6CDsC9AstS8AuoFOHT5RKEZIFw4GoGQAhL6yyWRApKH4F5JToF5wB4E64F0i1fWsqb1edbCCeSLAVDazyAuuQg4XJSsyawE4mN6QmyDEEDiSiqhpaNyw2PIGTHT1qe4MRzZeSoHxHNCqa5Z/6Ug6zwuidDykgu1rv1OJTxRdSqZUVYEGtUSx2pPPiXOYKBYgiECwKc2Jog8H579Anj8aLvhYsZEGjydoGSgyDwyEawYigsVpYg+fiCgx9jN9WAFFuDIGypCAFFudwGypRO4/UM7o5CC2QOwKTweAbJQmgt+C9/c0FxcS0FmgpZSwqWMpq/C360IG+hGyVAb2gt0Ef4cspt/MTzGg4Zg+gn7oUAR0HyeWLrATLE4hggIgWg72SFlQP51fKszZDe/jAhNvDRoGODluZMJx5Wa4MzWm6grNih24EbBm3XMGpQXBD3oTdBl5Wa60GdELNPeIwHAJVxhhFRbHtWsEoBX0Io6OUBjwDhBZMCO7aMWeB1gg9DKsYx6QoSsGcYB9wjXEsGEhLkREgfMEYRGqJ5g5j7ThGcHFgjCAZgicEHAJMGQYFbiJNOYA7+QkJFgycEjwKsFRwLMF4yesHFPT4CnMTsFuiPMQVPQ+DnglsHORfiqnMNEB9gly7KgLg7ohceZI3bcF0YGLSc3MUTTgmgYjQUQ7zg9TSfgkZjM1EPJIPT4Bcib9xEYe8EtQaCGb6K8FYwCATgQlMH73A4BAQnMGHgtOB/g9cK7gjCFPCHcFDPGnDmsZJgYiH8GAQskgsRXcFbgqiFjhckSg3LAJ3gkCFUgWmTvggCHNICmhHoZjAUQziFTof8E1gJG4pg6iKkQsu7CQjEQ0Qu0QNBXiGHwKSFOYSSHpEaSEvgz4CZUJ4BJZWCEsQm4BYsC8EaQpyojQFFiWkOVQyQ2OCX1T4Ifg/8SjAd4iFyUSFHVSyHrBGiE9we+AwQ1vLy3XQjA4KyGB6TliuQ8iicASTioYBcF5wY8AFYM7jVXWOD8YNSE7fDHqBQuiHkQtPJHyU87MQtp7nyLkhPgijDmQ4dwpQsMK0yDe64YHSHV5GJ5GcfjBkQoVangsKGjlaSCRQ8sF1wIKGY3YiFlQvyHEifCGcABgiQYKqErUKHAJgUm6lQzgDHAZyFIQwqFgQt8LZQugi4GDRhlidKEzUKHCOMCUTISfx49QzqGNiDcHxQifjAhFcG+Qt4DEiAKFpcZsHZYJqHflacIOQox4HBPaHqiA4IBQxIQtQ4DAjg8OiOgaaEOifsFGtRIQ1IWm6f8Riq8ApIAYRJqFkJPYox3DiErnHh4CQ9diVNRSHyQ4iGlA56E5yc6G4Au6EaQvJCb/QkDrg++D/AlPLwYJaG7A06H+Qvx4jyOKAgkeNQTQnIG4wwPTDQiYENQl9D9QiFoown9BoQvQErQ1qHYQtYFOQxCF1QrRTcgNZbMwvpAFgvlb0wiBTqOeyHdQ3wSfBcmH7OdFDfg8J50EEITjgzSEzUAWGLoWaHYwu+rrBNGFeAj6HrhNaE7hYCFww7FoYwxqHsw6sCFhVvJSPVJSswkqGaw8uAQw89BQwgRz/gvR7FyQwKywpZyiELGj6w16GfzG0gVQk2HeQsNwRgKmFxQvfojsMyFkkMu5oECKEWwwOHqDYOHuwpm6mwiOHqQkKFsUctqKkUOGaw/bQdgfWFtQhqqBIA9BNQhEQNBbOEVwGoLpw93rHQqdA1gxogbQl9A2Qydz5wyTD4wlWRKQvSH9uTOFpQv6F29QyFaYWuFfgzdCVwmdqEQ0WGVqPwFz8M6ECjG3wwSBGHAYJqFcTVaF/Qi6qXQ9uHKQ3GSUw1lZSw3GQ9QGoLGQiCGRwtuZAw4fKYGbLAdw48HPg7dhHVOAIng5OEo6VKH3QsOGPtfcHDg5eGhSUsFLwhuG3zfiGqwluES6Y2G6Q4J4gaBJBDQq+FMDQaFliGiG/6ROFRw0KHAIkSF/w0Wqcwz+GoPUyH2wp+EGDLKFvw9kEsRCaG8aWLDURQuGYNDyGgI+OHsDU+GhQ1ajFQm257Xf+FzKWOHVg2jTlQihE2URsFEI1BHDwxVr4I58E7QJAYKw13TEw5QYtwCBH9wqRL9EXeGgw02GYFEOEkIna5LlXOElw1ETiIiO7JwtEiEw0RGO1ReG4I/kg/wwBF1QpNIgIzMGO1FWGFgyRGokYHDQIkPJe3PTQYI2KGCQ43KqI36EIIokjewx+HbwzdLyIyBaoPGqE4YbuEi5CkC3oDyJV3OgqGIzw79GaEFFXLerurLhSdPQhHxyIp49qLVZ3yNOQrQR5RcARMb5PV5SNwTlY5PI+D/yJR6iuQhSLyeeHb0GeQZ6cxFhtDLJhPBBGLqbuTt6duxKEOBTt6JKEutIpHjyLp6CgsDz16Vx5/yIhQcieOGSKL+TtIjeTlpBp5Iw+hT3yJsRePC+TRRXR450VE6sKDPQVIiU6yZARRvwzeTfjcsRI3UOCfyNeTdgviRZI6uTrInBRNIjPRHwziQYKMJ6lIQUHIKdvSsI89pVIt0QKEAqHRuN9DcPbqEgKWR7cw+eTpItR6muVeQZIvhS9ImhTPI4RQMKMp6SBOJScKUZHXI68EsKEJE1PHKH8KMx5l8firCKahQ96YxErIj5FboSCGr5YuZBIo7SbKJf4BKKLg46MvTgAyoHzxPZQwA95wl1XPQfJTpTmpY5SUo2EBlQjNLXRS/5uQ0Ia8MNAHh0FnDtKJ/6iEDlG3UEgHntV7Cco1IF5wAVG8ov/5XSCGiJMbAEjyFxZgeD5J3/S+DppeVyko5aGvaWDRMoowhQ4OZTdUNlEKouLjwuNKikzZKHO0bFEEA8VHGo/AFCowrhRoFjyUAjCT8YY2ZSsOgHzUK1HcEW6jMAs5QiosJgY4d0p8SHlFeopAGDLT1HeMUIHQSINFqyP5QuovxSWNcYHCot5TiAsEH/wINGR9DEFhozQG6okgiqAqlF6ojQGRA6KFlZHQEhosqH5ojfoGgzNxI6eFwh2PoEao81Fg4CVYYg4lFvpUpjEealGqDewGcSYRaHOZNHMopAg+AqtFlQ11F8yGYH9oqNExKAQH9oppQRAv4H0owFQxA56RWoqrJ2HGNHDo95SJA0gF3YPFz3KNZSTQtapEgnYHVojzJFAlwHhwunAbok4G6ogdHXAl3rRQi9E6WFgEno5oGlo6dGdo1O7v/FtHY4UwF+A+1EseADJ9ozgAHZO1IvokaG7KIA5TQKgH4oigxjKEahYo7dLZ0DkFlQqCq5Kenh0onqFao2/oBo5lGqoq7Bno6KEepY4EVA9lFG+WVFjjDUGcAaJTKmZDFJo2DGLKSjGFTCggSo14EDxRyE3owCzP/P1G/Aq9FlQzDGKGZJT0SNjGgg9/5JoyEH7AAJEb1U0BBI5mYVo2UE9NQXrCglUEKA0zbV9KUFW+D9yKDd+B/kZ1KHZflgkYoC7TuckHh0DvLfo6kGiEAzF0ggqr0SHTFMgsdEiCDTESgskj3AuLgqYnkELNAXBGDRUE6CfhjCggUE+Q76EMudEHSYkCC6Y7EHSYzUqZpKkgUEUihEY6KhPAjpoRIJJSK+YzFuoClEh2FgEvIZEwL9MzGpNALFMgn1GCAxLFEg33xHVXpr32DawcYupqBITNJeYnQR6MH5SVYjripCIFRl8S5w+YvPrfAA0gA/VP6HhWlT2pe0HvlHpy62UMGNdLn6OdW652g+FRfgdFQjMAbELdD35wMdTQTY00F6KEbEBgp0FxgjK7tcXrGjY07gbYmMErYqH6j7D+hkArrHplGbp7oPrHVlEfYYouEEWeaFSKTaVCtqcIRhTGJY8qCYSRbXxbPYrBgXsO7F5+H2Rdwf1wNqIKjq8OIiXYcHxlULa7NbXLw/YheDONSIqneeJCTweVp/FU7wRxAXj/LKoJI+MHR3LQtSGMaqZjEbVQ/bA/oUNIZT64CzRHLD9Z64G7EvcS7ZApJ6gLXI3x7OJXDhIQW4c0evx0JXRFLzRbzjNRzajUQVTKzMahg4oGhbBDLaU4ztQ5QIYL5qdZai4nOp/ua6jqlNfhMaLmHs4wTDNUWbRPYyEJt8QHHq2GYpQhDXGK4oyZrxNRFDqHmBxQRnGBLQMw5vc8zzsW9h4xVXyRQQjQlQxXHOvSLbc4rtR70T7HM40o6tTTqj04zY5g4l9ZtePY5/IK5bvQAPFzLXzhyOH3GMkIHE1qRpSe4muZ7vV3Hw424yWJX3xI8VXEAUC2D3sNPERqVnEpIL7EhfRqo83OPHLsTcw446tSxvGnGfEaHHh452gE4oPHGgEvH4IKnG4VAvGc+L3G+JO6oY493GdWNLbO4yEJCtTni947CxZUSm4i47Czp1DXz7LFoY9GGqiSsMSiQ46JapbZRwE8GjSR449bB40HGr4onRyOSTy/YsvG0WRRDT4v7GroBoaObfaiOqS8xS48UpZ4vJLJRZFYO4tBzYaVvFJ4i/FWeRvFF48iw142nFuCXTAZHYXFb4gBy/48W5r4pNSf4yvGL4/3EOON/FcQenFdyR7Hu4/vESQ0fGKWNzyveNvEnDIXFAEoGj0sV/HMYCXG7DfXGXg0fH0scfE1+SfFBjQ/F04xYbz46FZ+4vqDDiWPHo8G4YfYxPHI7HFieBLODX4+gm74xXEiYmHq0TDlTW9frA848yYDqKS7CEtaAiqIgm2qA9BSqezA+qd+4KqPszGqKtSPbWL66qF1RxcPHHqqT/oR0A1TQVYtRRqRDaRTPNRxYK1TZA6QmSqZ/HsRYVSDqcQkCEj1RIE2tTzhKQnwXQQlBqTSY9GAtSJJKaCCEnNRqUN9SSYfdbr4+aDZYIIkgEptTZqTQmjDEwlyqMNQhhB2YmqVgxgYCtQmqb/H74mIljqd/GNqLNSpYB9YX4kIlOYPtSRQONSB6IomuEhwmG46mA99SDDjqesgYTVzxrqDgJmg5UxHqAXBTY7brATGHxrqBULNEhom7qNonWg9sBCGRhA9tCtjzOXCgiRZ6pjE30FV2Z6rdEhHi9EwZh9YHomDEh1RQwEYkPLUIi22INDrE5/TJYR1AzE/uwlIPW59YKYlWdBH6Xkc4KnExLznE50G5/diBzE/omSAZomPEm9QLEwYnHE5QDXE1uC3E9lI7En8RimNpYeGDOb7Y6ZxbQE4lDiSt4HEvObgkr4mAk8UBeAD4mwkzWCjE34nbEoUC7EyEn7E1LqM/VXZzrH0b7aaZAHQWFg548aqmMIV5+wGhwiSJ0BQgMFh24jKqAIdNgKiDCS2WC4CEDUJwZVGknpsKkhAor0IUkiuDq9UnpLICCS3sP9QDnG7R5dMUnEnWGr0gnpFEk/FgFVHpEBgKqp+faUhkk+qp+fREhHyZs54dIzSonCxB4dD4hL9IpBVwcL4m48apSaJT42UKJxMnff7RfUknikrszoaaGAXVI8Le0URiYwSuaWkuMAek0IwXVVzQh0UUnsacIaFVVUlikhBaJUdT48aU6T0aDliKkzajoYTFjxkrFZuICUlBk2FZrCVGKykvaiiMDfSJMbMlI1QpBMsAsl03NkkUVI6o2DQjDhfR/H41LMLpfc3QU1N0k+khsl2kWG78MdNg3UHDT6MdlAkk6GAUaZ0DFGOkm4DfslmXKozskmxC5knKrckgAivENslfMfcDy40Wo6Yd0nxk0waxkqMnsaSsnzkgUmK1LaBlknkn/mJNKZkumIGQqBwmI48kbkoATiNVTRksNJwPUBcSRku5jI480RQ4Ucm0klkQYNLcDkk+UALkwUnAkIsmESdMna5UzSXk43RNk7kmLk1nQXki5gHk5MjJQdskXMXjxxFeCnbkrEpKlVMlOkx3RNFFcLG0IclOlAMkwsSkldpeTSu0Z0njpN/Adkmsnu6LklmkkXoi5b8l+fI0kV1BikmsAJDdFfjBckiz5CaMkqMkxz4aaHTgKaAsn3EHk7CsVcms6FdD5k4y6D1YUn4aISkNEqslAUwIrWaRikk4pfQYUn8liU9TGOaMMl4ObGb3lMAaPlMTFXY7eoSUmKIVsE+q0IpljFAiyn2wKyligCTSEYrGKkkzBoAUo+JUUzBqWCeJIwaD+qdcHjrQPCmp2MbahpWOimPUb0lHxGcnP1Px68MHKw2kvBqcUyNjOUlOLtksqIaaJKl2U8ymq+bBFTkihJsU80SdUY1g7+VjYH1UykDRAgnFU5KmHqYDQz4/2Lgle8nlPYxiPMdyl+wZGQlVCKkC1KoTPJdTZK9AWoe6Gql7FHDTx5OynvEelBpUsOroSIWA8pQGh+AMAi4IGyqFSP2B+aWanuVXElDY1sj4dBLSDoUKqU/aPjBaTanWgzBpwk5upzU9RrasGamnQ60EdSQ6mDw6RqHUx/DLUhTqrU9mgkNM6lb8OLTTUgBh7UiE58E4ymDcaEIBkI+ZFSP6kVzUbIcqAnS9zDJDwXAnSMBDBqg00JDQ04TKQ0p0hA6Eby/UqGkjLQZB/U0eZOMWGkvzMaKEBbZCIBSJi5IX0Ka+KMaLIQiJnzVnJtQSYJgBFKLqqMsK00+lCu2H/xt+OJj6qUzCk00ngjqfrSE014iI03GmCMfmnCBKxao0hpDo0wGkE6H+YYoIWkDaIJA404Ba7zOpBTQAnRKLfFDK0ybSUwIEiG0NrS2LQ0Sb+NkJ0LAM7KMOJAU07BYIoamkR+cWmrldbSkLDqKXCP5CmLTbSDcLHQGLHDIy0inbb6d2lHtSJjc02bSq0qJBOndxB8LQWmVMLuASLJmnJQBmnh0vdY4RMHTB0qJBXCQHRLzGxC1QN7TqLPmljQNOm60hOnDBShYQrMJCg6GRaO0ukj002PwjLJWmpCPq7MLLpDy0hxarrEpRCLb2mvEfWk4cJGioib0CBhN7Ep0zOlv4nrT3rLPbS41mn904U5Q4m+YB0vkK3aIGioiX2mt+R+YIbSunnXTWnKMGWkDLLpAz07HTHrPfiZWNHRI6J2nW0sOlW0genilGpYQ0nulPEE+k/IDukXBdHTY0/JgG03el0kbWm3afOm101em98GWl3LQY4f07OnO0/rTnLIEjb0wPGcbB6jM0xPFT01Eil0tmHJ0jZBX0rOFj0i/zARZZbt0hunQrOekY0gnT/042nq08FaGLfGnQrCpaCMFukjIf5YZIWBkAkd5Y88C2lP42VZ2kFVQwRJ5aBpSBnIrAhkFIXiKE4relH04ZZL0qJAKCTPFN0hDbqgYhkorHOl8w6BlZ3IWkErHnjy0yRl2kaRnCrLWkoM0KSuLBBnUQ4RkdzQMKnSMmntGSWFiMkRmu6crSSbdCJ4Q/hk8M2LCIE7hnDwQRklQmhl/eUWm/QmxnoMiO42M3gkMPH6lQ4EFTBrJ3jhZO+rJhXVbeMw/zdaPGkwfDXzmrJGKgpLOmYcVnRdUTxmOrFVLMfXxmurQbIBM7UiwxYSkkNM1ZxcQHIhLfBAhrUbLuMt7Q4kanJq4fBB04ZDJSIVNYA08KEFM4pgi5aeI1+ED5ZMpGAa+d1LU5QtglMg1Du6CRomFanKAIaplSaCOrpMn9gY4X1YeMAiqN07kA88YJn1MjplRM6pmdbOJkeI9pl2udCmlKVNbmHMZkVMpzjtYsv4zOEXRtrQqS7M2wKFrfamHMztbHMgRp2II5la6Q4lp8ONqCeCdbvCLyEs6ftY3MkKRPMrtAzrIXQHwVtZ1/O4mj/cmgckH5loTSwynMiAyFXSE5z/V4os5P5AXAsxglyGVK14UoxxMgGB8TP/7qFFFmBlQZTYU37KzaT0r8aWvQITH0qg2W3S7ZDHigYgOrgTe9h39XBptMG9I+5QZQ+1ctKveU8ZgNOnCiGLnjEs/REy5PrwVsbEjfAcQgWlGOrAkQEaBlAWxp1TnwHA43L5ZHDiwsqG4TCAVnNtfFk5FUNg7sDiYks7dB/IG+jfiV4iMgBzALwLqmylSYhrZKTY0sr8avsLVlgNMrAUZS9jdQZXKV5F+CKs7Jj2sz4h6nIVlWs/BDeEd9j65cVDmsyWRBkJrAjIGE7QNC0h6s7ZBBst5A/0fVILsUGxGBWzAIsz1npVFRgKsyO7YUjFkElKCi4SYSkssT4jD3Ueois5uDE2Pai0s19i5ssClPoJ4gytU1nYZF+Dq0aaix1bNnRkFwER1ctm5TFNngZcqBg6J7jkNeVljTa9gDxLNl4oPUiIwdFn5sgMjDs3vjFsznw0wcdmx1Ftl6kIKD1swdlTwBlmZkZ1nPTEDjIU6DAAzJtnQZM3Jg6O2z71JNlI07qAYNbhizpSxkiyPvRwZHDgx5QqrcGNNntIJdgIoc1ICs3po3SVurbzAFAeMYRbnslSh+MLDAAkM3xVsudkzSbVlwUhcbilMhJgc2vShs1FDoSQ1kas9xB/s43Q4sveBYUDUqjst9kapfllw0pQGaMeFmzaFB5wsxDmHICoGTMnITfpUZCXs8DnJYcUoNgGNmrsrdlkBP1nZ1bFxZwBsDUc1upm7EZD3IX+ogfUjnvsa3IPsk9BPs1LhHskbTwcxlkPs14BesopjScvDnPsnDn/zBS50kNlkPeBQhxGGxhMsqBDMzYNmfZF7gyc/hhyc0dktfbCnVsz4g6caapFMczk60rFngZB9mWcv+DCsgVlvXRNkvsqumcc53QJLQTla1aVkjIEzSYAz9IAchrhWafGSzs61niNGhrQqAnL7UVCjdFXVmUc0Ln4ckjmT09CRSZVDkb0nznslBznQPCNlKc5+lesysgZc8pbcycDIpcokhQUU0oUcg+nnfXdkQc864Zs9XJMcn7RWA6jLHOLOD44BS5OZa9n+clb6bZRuAlcoVnuc865is4zkCszQH4ch9mWQff5jc6a5is1uqjsu6RdpVwQPeFIilc7XKiCKBCntRzSxZYMZAEjdmYrWRizpXW6jMnrklQ7mSjHUFKPpGVZdc07kdss24k8Wbm/QxGALc8Qgo6BdnOcmREHgPhFxs29BDA5Clps/iTQc8TnshSkAb8X7k4YKjF78QzAfQiuEKcu7lfoB7nw88LmLoKHnxctdmg8mdkDsujAWsgOrNc9kIHckOqI8kTCOs9XKUsnOSk8wbIJwTfSs8fGRPc9kJZcxdk48pAEo0ydn8hFnlac/HnCKNLlJMhtlTBadjQ8jHkAID7nus5jCVsw1n3c7e7ksnVn5cy+hVVIpiS8qYKlGPHlzsr4J1s7HmboSHi8s3nmDs2oJus7LKLoaDaJsq7nrhPkGJVDDlvcs3nqDEHn+yb7nes4nkdqPtmEkUXkaEuzlgUvnkR0W7lM8qtTK8mXlc8gOiXUZVkypW3nds2XkHs+7KA8+C6Wsgjk4YAPn2FE+CoYI8qncvmA1Er9mVkankSiOPnG6erkdqX3k0cgnL1wSrnmicxjbZR3l28+nm7NFdlFclVkiYXJCnchPnEiDunTVV7nkRZm5OciHl4iJ3hRc2XnOGQLk28+jnm8oPkkPX5ROlBvmSEt3mVkRXk0Rdbko85jCzIO3ne8/lQscxjke83vn6FA3nMYYlDd8qflYc+wrk8h3TfibDkZ8h0QOSZGQuM/EkfnazlJ6bpFgU6/kcPJUob6a3SxIu1mJknOQpPR2oRgV3SpI2vxcuN5He6ZVxvIjUr/OT5EeFEPSCPB6hxkPZRpidCHR6ClEdce2BxMRPQseMfRtg1PS76Q3Q1IwIox6eUSewhUhF6eUSuPUvQYiGx5Fc3/kkCi0gAC26HG6FdAHoTx7g8kM7ZYU0T+PLvSMC+eGN6eVxb6QG4j6TjDmrbxGT6ILBiw8DJLIYgWCC5RiNnN8K8Cvqg56TfSCKQG5ICvfTmYNFEjPDpLZDbHjiEIyCWHVb5pIdQUmaDOQzfJgwPNa2iEkFDTqCoHFTA+HhwCJ6R2NN6hU4HnKnWFs5aC63ywaXQUGvYeDtUQFqpGH2kK8ZXoPAaenaCpJSYQNmn+CvmSltNeneCoGRnAN5BPwWdID9X7yukLDQp5WzGVcDJCH3BQxAyZIU/IVBBmCEwEPkHngcIAwVJMJ3T5CstIZCrO44ESQT4ELLbMKAA4gZCmhzCeIXBCqZTVCtHi1C5ThFCmTwNYzwWvEYoVJKLoU8tNwX1YgQ5z0CqLhC6cYReBDZQ+DtKlCqJCTClIHsga9aE8T/ZBCZenVgGIXvtdoVWkPDF9C+HhOCrDEqVSKIKiRDFtCsjazC/ZTu+NQUdpPoX7RQ4XuCZtq3QeHjDYC9KRC974twQdnfWVHyGkWwXWEdTYb8BIVT8H4VhC9wUQY4YVGBczTzCZKq1yAMgGCgDIptPZAmCyDIaiaqhgipw69RVYV5CPDYgHGyiJCuHBA2Mjb/8b4XHCn4jBQAwTvYDEULRR4Xb8dFjfrbIXgiopyYim4W0i6YXZwPwRg4CEVvIP7hrZd4XiKeHjUSMPIAiw0RwIYC7vo0IUCijoX4ELVncimoXNA8YXw8U4Uwi+4UXC2DKIihaJskGTLmIeHjKeKg4ZcJ/ZCi3A6Eiz4UqzPkX6i79YBYqw7ailDYsiu5RUi7OA0iuHDKit/Ysifja5Cu0iJkCjJ5JD4UPCkkVs4EUU7CqQxNHRER5RLEXibfJjmCgYUxCmVoLCrQzuiyUXwisQzOi5qKNCy2x0GVEWLC18xk+YqJoinLbqighDxCD8jBQZYW+innJFqAsXIkN4V2rB4UNCYjLq2SeTUiozLOoZMW1ip0VxC79aWi8mAgig0WT8HLY+i21AYkpLYBiwkiCizjJcEUMXlC5LIlKX4WNY+LL90IMg9CuMXNixUXkwezh78FoVTi+YUAbMUXzCcsWrRXUX0wEsXUaUnL5i+kWmi+mDmiJ7i6ZaDY1im0V1iuLj5QfQVaEaWiyGKEX3iwmiPixjTNZI8jtimYXQi+8hfQWUXfiukVACWcX4UEfioiuUWcODBpni7dLgS4TKQSsHAycyeR3i/QhrijMVgS6sVOc4kVvC6zgW6DCVznG8XLixMVYS+lBAS/XDJi8/mz/SAaQUY8UwWc4W98yDLUVeUi+kaEUkGVESUSzkWUGQIrQi2gy3i9pCcSyjgKi2iVxi53z9CgSWq4MQRUoRiWCGMSViCimDssy2yNHDxiGc6wgyGWMjHkNIV5JISXbMk/RvEawx1CnsifYUPjTdVbGo/FNCx2cohyjXQwFtLWQQ9PbFrYuX6WSgPgQ9cP76ShyW/HHlLtGTfKOShwIqqTfKGSmyXGSuyVlQHyXAndLgeS1yUL7dyUf4TyUv4EKWRSsKWPUzVDeS6lLAnCKXDMayXR/UEm34GKWpS4KXOSrmRxSmbE2oRKUX5ZKX2SvKUz/er5jPLkat8kHARscZo94hASdlN/qdSWInmxWqVwSZwk1S5azzobnqHhbu5hQTXL5qBqU5QXzSLoSQj9SkuTQ8ccIjXPJTcEK8KY4C0b5MAfEhgVSp5KGKhm3H/gQsEaV6qW5IPoAaWmE1qXjSj8A9SvyB9Sx0aXcQok7SnmDkxKvpSXBe46gQBgW1RvnfAFaUPSong0RSG7Sqa6WSYHAQYYZUbVS7KahpHqVDS2oyusG6VwhWa7hMYkQnS7IwpxOtQHSg4AKMIerbSwghpGa6hqTai7oQ3RhrS2vkHRLGBYyyaXqhOu66MDIyB6erAb3RGU6Eu4DgPIyDNS31TLofirhMC2AYifhJl3PhimgVvnKAUG5gtegbvhTB4JGUGXfSpHCMVBGUCy+NSzIUO4iy/Og8ytARePNmWSMTrHBGWNhAy+GVB9A/q9SmGUTS9cJjS3awQ0TwnAyhGXB8NWXAynWWTEDQmdSg2Wmy08J9Sk2VFGb8JSEa5BL/JmVXhe2UEcNui4EDETQy1KC3/R6WSE82VpUDWgyEg6W7WcIRwy9vCgUeKjivVJR63GKA9UWmVWy7IzUJQaW4ypxA5GNWX0NTGVkJJGUaElGVRgIajYy9+6nSqIxO4z2XBGOuieE8GXNGI3y+E65IxwZYw+yosKYwPGV9IeuXqygow0EOGU5yyUCVDEmUFy7IxWYYuUqy6Wjlyy6VdyxujVyudi1yzLBvSqzBgos0YtywmUOyseXwYMmUDILowmEYDBUyqu7E0BSqb6c2hw3Sob5ysgHC3LuXP+SmWnALmXm0XIxL8gnBUgYmjtSuVRn8fsxAoO+Vxy3AESyuoxXyzMJhylqB1GLOWnhBIQHygmUqygVRc4/WVzy6eUAcXawAqPmZHy1mUHmPWX0yn+WkWNwkDELeXwWAh57sTozoKp6UXYPGXIKhwkTy4zAD4boyp8zuUIyxpQDyv2WFKOGVUKk0YdSwuXQKt8JgK/6CgKgDgIy+BWQYGWXhy/BWBqQ/jSUYhXp1XhUocfJDEK9eV0ym+U3AEGgBGIiLny2eBr4W2VQPcgiJYSBqvylmXqDAfCRy1zCyy3BCCKwwnfy8ijXVT+Wty4IwfMI2VWJB2UsCJOVj8NuAp1BUyWEshVE1KGUqyvDY8ykuW7WYcRO4sBVSjTjDGy9EyvaWPkqylNjSyoOXhRWaWZhF2WRGP6VQPCJW7WFrToykuUIy8rQIKv2WAyscJuK71j+KnGWkcA4CwseeUqy91qsKlJV1S2m5jSxJWay9aU7AEa4WfHuW4A+iwrwRz5/y98Kv3BpVnynQhjwapXoyglCNgiz6HyjaUfoE1hJGc9AVy3OUFKvfQJK8L66K3uWpQDJWuKkeU5KrnQXSwhWfAb1jsyqB5tK5GATKlBXrK6gBkSiqXZDIairKzaAIIJG7E0I2i/rc8wnK05y47ZTgXy0cpC7HFoMyxsK5MbJSqVSoaHK2WDHtXazqOV/qx2VmVPK9LJqgJW67WMFCZK0k6vQVkCnK6IyHZI5oQyyFyRbOXFlGTSWPGZgH8cZE4SmFFVHMx0yvMhEyLfBWBEzE0xVWPFUWza0FFUf3j5wW8QqwSBpTGclXLODonxSlcAYqjgArWdFXgk/olPQElWP1NdTPfCUy4qyEmSAWlVQ9elVUqw4zcMHlV4yEVWyEAVV/HfyVRAXlULCMVWCqeyjW0DlWEq7sCiqiYzm0VIaXAGpQqq0cw3GGawTGXlUQcS4x/MwH6GQRlV3Mc0yhmRlUWfJMxGSkX5vgYVWCmU1QEqvVVqqyVUkqo1UkZRUyqqmchWq+1Xq/QyCF6JYw5fFlUWrC2QrGbFVYmXlVESE1UsmGNXkgf1V+Sh1VRARlUS6N0xZoUlWNEwdBSqwSID4RVX5XW4yuqqYym4ZpzpS2yVRAYNUO2HVVXGKtWmRBhAkqm1WhqiYyMqyPq5q4CZuyvYCYqu1XumOtWrIO1XJqwNUMq1lVawArxhqrtVMILyHtqoVWtqm/gSmOtWpSOMyDql0EBmN1Xyqw1Xiqr/Li4T1Wbq91W4mUMycq+ICJq6dUFSrNWddAUDjqpYw4tE9Ux/Z0yqq76z+q90xyqmqo7qgtUPqhVVvQIlWEwG9UZSrkw2q05zzqyjhLGADUkqhdV6OS9XNETUwkqzVVemcZqAa2XbVqu/QgkitWomXlVpUCxAbqgtU/JONXLq+4nDq8NUN0C9UtqkdV1GMtXIamVWoa3dXYan1Vuq6jWvqz9XX0G5XFqpYxFtH9Uoa1dXrGc8EfqljUoBNjUUawyBGq0xbcanhBFQvjUpqyjUFq2vxxmd0yHqphCia+jXzEuejMa5Yn90UDVAao5lKgCDVnMzTWNqkjW2feDVAmfTUKas6nImTDUMatsZLq8tX8a/DUTqttUTGBdUSrMTVDq/NUMa41XCapTgOkNTUIa0dUYMYjUEahDhkalamnqutWzUaTWZqtNXMq3TUEa5hCT8ezXqaydWfGKNWymX1VCaszX8cVLVJarkx1qy1VaanLXGavlUZqylW8qh+i6q9YyAKdzXoawLUPU09Wtq8DV+a2zVzqp2ypmdMzqATMypgFAAoAQwAmAPMyPgYYAGAFQw8oEAAAAKWA6sgGQA6AHaAIABMAKAD61g4ysgc+n/A1gFqA02r61AAFoJBAEB1tYBR/wDUAAAF7UQPQBrfBgAL4f8C8AcoC1AaiAJgXwCZmaYAQAPrWgAWoC8AFgBgASwB9a0swgAf8AraysCHCROz/AHbUEAfbV9ERIB9YXwCna87XUQVbVXanwCOATIC8AcWDWAOwDzgN+h4ASICyAFACpgVMAFgN8BNUBgBNUT7XEAMgCPWR7XPa17X6Ad7WfambWVgcvrcQcgR7ag7WGMEHU+AMHVQAC7XsASHU4658Cw6+HW2AZCDI61HWMAdHWY6sADY63wC460HUFAWQDFAUoDEACoDpmWQDE6l7UWALoCwQJ3CMAAABKo2sYA42sEAoAC+1jEDMq9yHIES2r11y4FW1q9E214jT7AdOsrAJchB1bvzO1LOuogOtGu1sgFu192pAACutJ17gHJ1rusp1bTlcqhuv+1gOtoQMQBB1c5Ad1rOpwAZuttAous51cOooQlgBQAAAFcIgAjrkICUAIAAQAk9ZOgnAo1IUdfOBBdVjr9ABzq8da7qCdUTqntS9q3tV0AKdbNqZnKHxwkEHqDtbgYw9czrI9dgBo9RzrpwFzqE9cnrU9TzrhYLwBM9dnr1ILnq+dQXqMdUXr3ACXrxdf+ApdWUBZde4B/wJ7qldUilVdSAAAAMLdMMbWoAHXVTav3Uj0HswJzBL5zkY3UH6vQCraxJkMAM3XjSacAA6g7UguBWBRwNvXUQJqg3aofXu6z3XV6j7W+6vrWwK0VC8dOcjW6kPUW1HhB+gF/Vs6rvWwAHvUWARPUp64oAD6x3BD6rPU56/2Dj6tHWT64XXF62PWl6xgAmAcvXTqL/Vk6mvW/6hYjqbbVCAGpvULERIJMIcA2yACPUQ6qA0wGqcBwG/vWI6pA3D61A2yAdA0C6zA0i66HUkODMxz6koAL6vrXL6yvWWAVfUq61QwgAAACqSgHnA2usm1JusoEPSCOZm8EW1YAGW15+sv1502v1apCoN7gAEc8QEo4EBpwAUOvf1d2u6AHuokN3+tr1zAkAoRniXMhhokQEgDF11ADMNHeqh1MOvj1sBsQNjAB4NIAEL1WBun1OBtB1ZeqIAhOsINthuINP+rwN5+oYmVZRamVuvv11BqXI7hs8N7Otj13et8NU4BsA2esMAKADwA84Gm1tQBYAUACLMfWr0A74DxkTgTk0P1kKAegAXERlPqNXbAYATRoR4LRpEojRtW1zRoCA0jB6NfRuv1AxvaNQxo71IxuXAYxt6Nx4KbANRsAQTgWmNgSFCAIQH/AgRuCN/BrF1TOtggRBu91JBviNs2sQ0VZWcNjgFSNIBoyN9BvB1bOu8Nceu517BoCN3dHz1GBqF1GxsENEuqKAIhpl1Yhvl1EhqkNmkHX1G+oUNO+om1JZhUNRFAUil8r7AZ+rW1V+o71GUjv1weuXAj+q1gz+ouNjuvUgPgEsNn+piNuxriN++tm1BnEUUEJpcNHgBoN5mEyNTBtyNKYD71CBruNVgGQNI+ovAY+oeN/OqCNfBuwNAhtwNU2oINMYR2Ny4B91+xu+1BBwnERJpONCJpJNoBtoNZdAYNkBuyN0BspNVgGpNaesH1nBtH1aBuZNE+ueN7Js2NQhsl1HxvKAXxsYAK+qnAyur+NMhtkNWMy11u+uUN5+p+yfKTSoxuE0N2hrW1mo2v1mo2JNjkKhgfWDGInhrf1ruo/11ht5NegH5NeJocNWwC64eSjZSwBtcN/RtUA5JtlNzBqpN8BqVNHBpQNbsDVNzaEeNvBs1NoRo5N4RrwN3JriGgZuDNKhqMkdpsOExJv3AIOr7A0pqj1FJvh1ipv8NdJpVNXqHTNKqEzNrJuzNkxrCNWxs0gRZr2NIZqB+iQCPwBcArNqgCrNcZoENORvrNSZsbNGetTNLZu4N6pqeNU+q7NuZp7N2YD7NuJtBNb12HNPaCjNHRonEsZtRN7eumNk5rlN05rYN6evpNBzCZNGZpZN6xq1Nrxt7N2Jr5N/ZtBNqmDLNo5VHNh5urNlxtrN8ZvlNrBppNV5ubNiqFbN+YHbND5pzN2pu2NL5qDNb5ptNKZE/NI5tFNB2srNHACPNjABrN4xoAtF5uAtypvnNYFsXNd5o1NK5o6Na5ozMz5pJ1dhtINFUlQVWKRQtz4FONXZp/NE5p8NeFuTNKYGvNaZuItbZvvNbJugtT5o3NcFuLNNpuNxu5u/N45uPNjBtwtvepnNtJrnNDJqIt9xpIty5pCNq5pgtVFqr1sRvsNjEGb2q+HPgKRrFN+ODF1v5rRN/5rPNCZoVN8lpAthFpHA4FrvAkFoEtGlqEtD2pEtCFtm107K64d8sjNzFpJNMZrMtJ5rrNclsvNBFqUt9lt4tEFv4tnZvItmluEt1Fp0ttFtMo+lrAIZviMtzerHN0EECtMlsstgFobNClu4tC5pUtfFtIt6ltitrlpsNCVpxNuls1Qc/G8tImnSt1BoCtbFpuNIVvwtKZvCtl4Actz4CctMVpn165rctVVtfNW5ptNXltXwOTHdNmVv3ALVqnNbVs4tTZrstXVsitjluitZFv6tlFvit2luqtSVoPwKVuEA+ukatIeuat0lplNuVo4ts5sKtylrz1q1rKt61tgtQ1vgtI1s8tl5G8tU0MOt0ZtMtM1vPNc1outoFoitxVqitpVpeNeOvutW1uGtNVt2tVawtkDptQtTVs+tJ1ost7Fp+tBVr+tS1oBtK1qBtj5pBtWlq914Np2tH0ChtwzBPMk1uOtWFr/NOFrOtyNtstnVrPOy1p6tN1uBt4upxtNFoFNbYHEt9eFe68JrQtmVvxwX1qstQFvmtilpvN3VunAvVrWt3Zo2tg1rBtj1ohtAGD5S3ljLo+5vQtvNoRtFNqRtsBvyt1NuFtdNtFtDNqxtTNs2tuNplt+NqQtgeFpGklowt2VtOt6tpYNmtrCt2tvRt9NsxtgluxthtpZtA5u3U5ZK1knNqVtPNswtIAGwtp5pttiZtCtHVodt11udtLltdtUtqNtoltm1O5o5titr8tytv9tgduCtGtpst9tp4tjtt1tkdvKt0dsqt0trjtoZsHEbdBR6JNvhtZNvMtattatGdtDtXFtRttNpztsADFtt1oltoNtjtHloJ+Q5sTtFtpVtVdqCtslrrt7Vobti1qbtEdrUtjNoGthds7tT1uL49Fu9tSdrFNKdqttiNtrtttsztYduztE9qzN4tootHdvdtJZtpkZtvnQfdtTt5NqDt69pDtI9oWtNNtvNJVsnt+tuntm5oht7PFLtB1ortWVr5teVs3to9rvtItpbtetpdtBtpjth9oSNdVvGtYfCYtxlqmt59urtl9tmtw9sFtl1v+tO9o7Ne9ritoDsStrNtqtST1StJSnet/lsrtAdovt6do3t9dtvt4drWNzlvztIDpntYDr61b9u8txEUIdJlq/tqtoQd31qQdv1rHt99sBtj9uAdz9vctc9rz+eDsI15dthtR1uIdadqHt5DpvtQtu3t1Dr6t7duZt2Do9tlAkZYDFr3Nydr9tq9prtiDrkdyDsbtfDoxtAjqjts+t1N0uv1NcusNNPxuNNa+rNNhOqBNe+pUNoUnPy0/EhNWhpUNW2qkk1+vN1xJqe4T+rQm2FosNfpqsN5ZnodajtcdaGWeOoIFYdQIDF15AkDt1xoMdk6lpNSjowdghoiNURp5NwjohtAsncdFfnidXYFEYmRpSdXDpYNjZoydbdv3tqju2tODuW4IBTBOcTsmtJTokAZTrIdaTt51S5t3tNTswdkTvqd6jrcd7RAS+xTsSdHTtkdXTqR1PTvQdfToqtL9p2tHGhGdLTskdrhradSTovt5Tv5tVTpmdUFvMdQjoetxdo1+z8lidbv33NGOHGdHDq2dgFp2dqlt6dU9sltAzrxtDTpqohTurUrTsudA9oh11ztuN3TrudszoedB9qid5+qWdCVzOdfloud0EA2d8Dp+dCetudD9vudT9sedCzoadwzrBdYzqhdEzsptfhvSduzpodd1rqdzzqGdx+XRdHzsxdVzs6dKhlxd/zr2dtDq2Nwhqsdi+uXA4hpJ1vxuzA/xuzWzjutNjDvZ80ZUoNWbCdN+gF0Nfgj8dt+v3NSJtoUPppd1eBv9NETpRd6jswKzslTmh/kmtEprJNHDspdAtp4dnVpMdTtrMddLvx1kRor1hzq7tNeGxAsQGP1KrtWd4pr8CdBq+d1tqvt1loodCjsZNADtbtgLoZdohpsdM9rZdoAHX1auotNIACUNIJtGtrlWPVjpu8d5uuGNTvEIdqhDt1ejud1GJrCdWJpNdIjvYg3lSXCk1pUQGOEyNibuDtTrvkdKDqjgOtsAdedvWt2TuNdRdtNd7EHr1ExH3VXNuoN2bqBAubpj12LsMd2rq4NzdvddSLreNIAHn1nxu9dRpsYAJpvZdMhoAAItvrLTcCbswCWbcycDQE6KzQoTUK7woZtrzDLG6RKGAa2jfa6LwEm6ZXeE7lwFg7Bna47QVhw0/gKObAwGLqpTRfaOjJM6qXX86EXQC6kXRW7ojam78nSe7Wume7rXdIxL3Zkab3W26pnSW7u3YI7kXXk6drY1wDQIRq7aOe6YzVe74HX+783fNbqnR67LHV66l9d8bWXfY7pDYNqhtU46p3S46QXWmpW6A/4y6Eu73AD46FjehZCHYmQ3FPbrybYm7MTQGbQPai6iZg7YSCJNab9HmaSHfA683Y67EPXi7lHRRbn3bk7X3Ys7E3kb8AHux7GdS27NXfC7+HYi7gPUC6j3SC6WPb51HVJJ6MLUzqOHTx7UnXe7pnTS78XSo63bcC6/9WJ7z1VHR1PYDRpPbe6+Pfp6BPf075Xa46VPRHLvug26Q9Rx7NPdu7YTa26EPbJ7THfJ79nTqb3jYy6DTT67MPaabBtRvrcPUG6rTSG7GHTl8Q1U8JPHYK6yPTCab9ctJXPYiaw4E/qhpMk7fTXu6U3VW603aMQEvmEMf4ENJznaSa7XVx6TzfB7ePXbat7a67APUA6AvUJ7CzUx6FXfF7tDKGx4nWq6qvYHbavTp6tXSjbFrbq7c7fq67rZ66B3Wh7bHRh7h3Q46IvZrrovdO7ddTabuov3gb6ENJSPabrUvXCbxXVl7kTTl66Pa26GPXK72vaCalGsDQNvT17bXbB6Tzdp6KndfajHSN63Xc16DXa17FPUS7QTdRpEVFd7VXTd6rPf+6C3U96dXS96y3e3bJvdY7pvaF65vVh6LABvqBjFy7YvXOpZCPxwOELnMVDMl7tvZUxRXel69vUq7JXarbQnfl7GPSJ6GnbDj+OOnE/vaKg+vZs7NXfV6/7Z260HbS7y3fmajXS+7CvbLbuGFHMoWFT6wDbd7vnXT7f7ZQ7VTU16wffvaIfUy69ACy7FdWF7R3YNrZDZO6lvfh6/9UnzjuEnZJ1Jj6L9SCrNtYoLCHbucTDWykQnXl6ptbK6D3U87jbai632eOsqvRV6IYNBBWaLl7rPfT7hfW+IkPU+7WfTk62vaT6hnRQ4S1jb6IXW6gxdQ77afU76hfS66n1G76FPYS6LfUM7nUFYojmUvaMrXb7b2Fi6EPc77w/T4ZI/QF6PvTH7HPSUo/fYn7qDcn6eIKn66vWH6i3Ycws/Qa6c/Uc6lPLtp+iWhNbfTGbg/TC7Bfc66K/aD7xvYZ7D3Z96QXXH7FFOqx2Pc37S/YN70/R37RfV37anUZ6lPSr6W4AP6S5EP6g/SP6HvUD6O3QIIq/QS7p/b36TPQpMJxIP7rXXLkl/RS7Q/e37G7Z37/PdX6JfSF6h3e9rYfVOBZDYt7g3TO6EjSXwv8oSAkvd47tffobRynr6N3d2BujarbjfW7qSfRz6wPaxqFYCkQNxE36j/Z57OHfzax/Wf6J/Rf6WfVya2fcJ7QAy87wA4WrG/QH7i/S37B7YD6hvVrb1/fx7MnQXaHPeA6blR041wIv77fd/bzrcN6abef7H3VH6t/bn7KA6PBQ+A7BaAyn6NXSf7C3YgGu3a97N/T372A/ibLwIwh2CB4aD/YH66A3wHCAwgGx7cwHmfd37zfbX6hIhIHqA78ToA3IHYA236BA0oGkAywHs/dH71AwDtJA0tkeAyX75A2n7y/YIGmfQZ6p/aIGzA+t5JA5AGrA/gGcrbYHT/YYGhA2L6YLVf7B3XY6YfeF6LAGrqovU/6VvYw6cxmcdRnRG6dDVG6cLU3diTXG6MLbR7q7UAHTff1qKA4w73jtdhwXTA6m3eHrSHfwHgfYz6N/RLb3vaYHq3R5JQTvkH4nUUH6A1Tas7Y16/A5P6Agyh6pvcy70PTL6Qg3L64fYG7Igz77j1tQGqZB/6dDTt6xXX5aJXSibPPUT6Tffu7sg2d6CPSMGD9jgGYHb17+fVcb9A2UGRfW0HkA5UGPfZW7Z7fk791gldrvdT6tg1HrYXdw7GA+UHSA3M6QbYEGofTf6R3X66ZDTh6fAIoaYvc/7GHf2CDxJ7QNxFt6L9WqRv/SNhiTX84TDTENsLZkHFg84Gag0e5FxICHiTSegwCJx6ZHYQHfPXq6Dg4J6jg2Qhng90GZvb0Hb/aEGpwENrBgz8GogzpJRyjZIFtQK7P/RGlr9e+0qPbIHGgp4b5g8AHTvd77Z3d1LMGH9rrXQzqNPcv7tndS6H3SoHcQ6gHPfTX6EQ0haqpLTq/LYKHLPcf7MQ6KG5PcYHq/dUGivS4gK/iUYp9gKHgdUKHlQz57VQ3571QyIG1AwiHD0nKHiTYqH0QyH6VQ/e61Q+KH7PcsGDjag0+Q3qHoHfTqDQ0qHYAzcHKnSaHsQ2aHVAzkGusGNBrQ/qHNwFJ6jQ7x6sQ2N6cQx0Ggvah7CQ9D6SQ/0GpwGO6Ig5SHY/QaGB+qYh4g2tqV3aK6LaikG//YyA9HVkbd3QsGCvScHFneJYtZEzRoPT+6tPd57Yw4GH4w8GGJQ/ga0A176MA8MHGSd7JGw1+6//XEQAfcaHHQ6aHnQ/M7XQwbIDQwox8w8OGL3dBArg156ZPe2HS3e0HXjQSGpfT0HJDbL73g9h7bykMHXHf36JxMiH6QxMGDUGCHyvdMHKOFCG9HbCGawww7ZwwnAzwy6rrXaiHhAHaH4HWuGJw0GGpw5ybuw1KHtw9L69w30GDwxYAx3Y/7sw647IKEdj2GgWHl3T/7iwzeGxTepjN3RWGOQ1kH4Q0V6tFNJAGwwuGvQ9galw6OGWw7+G9PWKHHA9qaqg2wH1Ay4J8I4OHCIxl6OjSRGafdx7Ww4N64wxuGEw9OHuQyC64IxNihw0RHQjaxGVw53rrPVxGgPdn6QI7uHfXQNrII5y68Pdy6zYPdNviZeoMfQyGxcDj7UIwdqSMtl6Hw9K7qwyAHaw2T7fSAupb2p/b1XXoGJI+uGpI2968Q+gGTI+o6z1GuoLIzIHLg00GcXX+GOwwBGLHUmGugzuGiQ2BG0wxBGMwxSHlvR16BcH5p9SkbqvHQkHkI7CbPAqWGlw+WGpXVWHOQ2b7QwwCzCkGdSvYk2Hlw7+77gDZHvI9xHOw9RGHI72GnI8e6oo1WwLVvlHSI7AGBvSv6bPZRG7PbxG+wyWbITNFHzzPKHl7SOG2IzV6iow6GKI06GqI1uHOg5D6Uw68H5vRYBZDYpGlfcpH2aLI4BdJt64o2tqv/R3rdfcSb9ff/7DfeTasI3CGLQ7hGWvAn6PA8KGf7T4GmA0YHfIx57JQ8cHnw+zRyqKdGZA3gHzowwHiA676Hg4C7NQ6/bEEvcz/fTA7XozGHR/XYHfAw4G2o+QGZw2a6SlP9HC/W57h/cDHmo4oGro/sGyo+1GqowkazfDfp9/cJHXDUDG/QzsG1/Z9HbPWQG6HVlHNUH9GG/fE78Y9V6BfaUGiYxH6voz26fo2B7cDBqAmVQv6XowjGCY/TG7gyQGSY48GyY1DGJECdGOY+sGk/dzHaY9sHeYx9HGYwLHkPf5HJo4FHUw28H5I2SGdlYj7fgwuRPis6qG1ReHoTVeHNowagIQ3eH//dCHybY+HjIw9GKYzrH61dcJ9zZ+GT0J5GAwyVG7IygGgI6LAZI0FG5I+vqAAJpZhiKMlmshLWGcoWIRsj3thVd0K8Qh1l5J/UFSI32GRjKNLBviOMO4ONmS0+3WuyChgG4oOt+4qMjRycNjRwCMFm6UNah1OMN6uGPsQTK2i4N6Nwu2yPCB8H0TRyX2gRn2MfBxX3Hh8/XE0cV7jOONXAhrbXpG2E1KNFkN2+1ZgJu473Juq2PGegExd8o9VceKAMKhn0Pfhu70cR5qOSRuuNdhouMsxhp1pUJ8HhlNsE2h+eO3RwO33ekUOux1eMuh5OOTx6dg3GUeB7xqMOGh2ANHxm521x/wPox62P8mZdCdkEDWRho2S+hqWNR6h+O/OvOP/hguNCx8+OomY8ydkec43x7+MLxiHX/xmuMnx5+OQx0BOGQQzAjExzVQJ6MP3xpePHxwBM+R4BMHOjqPtx8BPP6b9UYJu+O/x1cO5x66P4JkD3IJt+Pbxo7q+ar+OYJihPiR4aPUJiGMgJwhN9akGgogRjUGq5hPkJw+PYJx+MIJzcNIJ7hNRAVBMqNRLFkJn+PCJ8iMcJ0mMEJjGM8J4hP7WooZyJmBNs6uBNeR3BOlRm6O0JyRPRmd+Mf4W0yCJ+RMX23RMux/RNuxkMPCxlcDqJyFjMmfc22hg+NWJkRMAJpROCxlROvxreM1gWpxxq1xP7xscNthsRM8RiROqJi+N8Jqir+q4JO3xyxPsRxROoxwxO9u/t1KxpuOYe/8DFgZwAQAGYC8ASbWGAAgCGAdvXTgAACOSerAAKABSAxCHGABABqARZgsA84BsARRumArACaTkupmAFCC6EngDN1PgF6NUgA4AQgEwAagEwASKHY8QbqKNk2tQAUEGqNQZo31FptpAjRs31musRJ7Rs31k7ozQ8ycUjlRHmTgJuEAyyfh9yYAQQKxvaN8ydw9FAFOTy4CDNAbuTAvwhuTqyauT1RpAA4QeOTYNEaNQZszDyYFiwyybHdFpsIjnyc11aoF+Tk7o8NHyZAAY7sUjTwCeTQZoV9xyaHIsKahTyxrOTchtw97yZRT5puTAyKeuTchtWT2KeeT8huTAVlHBT/se+TSRHBTQ2o80zIGWTQ2o1jqiBhTw2ouTTOopTiybBTKKZG1yYGZT7Kc2TLsApTPcGOTvKZ219QAIAJgDMAKsH/AqYAIAWhv3doAC+D3uoAAgknrM9SgBsAAABJAABy84AAACsQAAABJgAIfUva+ABkANABlQeABapheh4APADwAAABqL2qKTNgHus8AAAAynMAx3eamCdQcASEPYB/wDk6gzUIB6gAj71dfAApWlIB4AGYyeWsLq8zDYBzU0Pq2Y2gAMcD4ArU/ABdU2dqIAM6mUALUAIAIrr/wJrZvdeqA2gLIAN9canycPABpQCeA5gFGm+gLGmIAJCY0AD/Rk06mmIgBmms0zmnZAMB0FUwAAtUEirANXWra+VNjuobXzgZ1MAAeQAAKqtrtoOtrcTd0x807FhC04wBi0++wfAGWnmeJWnDANGma03WmG09amm0+mnM09mnJDf+Bs1t7rnU2OmXPAABxKTQAAaRTMY6YwAsgAOAAAEUOgFqn1tZ4B4AKsA0AKsBk01qm5NFancTQobT0wQAUMGQB5U6tqUzKtqL02On5wHMBR02+me4GWm0AOIBf0/uAAM/+ABjHOmfAAunN9SWnEM+WnpRFWmY01qm40wLh601GhG02mmW04encTUmBvdQGmg0y8mQ01+hw05/B105umSM7WmW4AmnPcJRnm0wem204wAdld7qUzPKmx00RBnUwAB1YdPjp99PiAF1Mb61bX3AXE38p73VzAFAAQAJPUpmEfWyAHVNEADNP9AYXXGp01Nhpi1PCiZNN2p1wD5mWoAupt1MepyI1ep1MA+p2QAUAMnV0/HDNLp0tMEZ9jPVpzjPbpijO7pqjMCZo9MuZvNN8mgtPzgTzP4ZtdNEZrdNkZndMppoLOtpkLOMABBBk6iLNFpvDMrp7zOxZvzPxZgLOJZ/jPJZlTOzpvk2qpgAAaY7vVTNFS1TqqZkzqqcUzIgDLTNADQAcSF/TjBnQzLmZPTfJrqQG+rKgq2rV1cwE1TsgFHTDWcnTzWeoArWZoA7WYFAnWdSzQGb5NPcHqA84DV1zGejQrGa8APmeIzpGdiwPGbhAfGf3TxWd9TmGfCz86cizWWdXTFadyzpGckA5GfuAB2eozgmZAAe6DJ1cwBHTzqY6AAAFEx0xen1U2O75wGOm4AIYAtUygBiAIYAa0/AAT0FNmk08UbfU8Jm+TRemZgM4AUzLIbnU9qm9UwanD08Zm/AOanLU9anLMw6mnU66n3U3pnJQN6ncTbFgydaJnxM0IApMzJmJ01CwFM0pmvg7mm/U5vqizEQAQ0yanCYPAAOgGAA+AKzrZAIDmnACDmwcxDmocyeg5syAA1QFTmxMxJnpMyNnZM4znnU4pnlM7mmO03ybXU2lJA3e6m5gJ9mDgP2bTELLmac3TnFcwzmngEzm1c7IATwGTqKs1Vmas3VnFc2Nmmsy8gps9QAZs+Ygpc7EAydRvqOc1znTU2QBec/zn7rOYAhc0DnRc4+Bxc74Boc17mTs0Gb4sLsBsAHMBdU7trIs5YAWAC+AbM8Tn4AOBJL9Xpmc89HmjUA9ngszLqKc3Rm+TWOn3s2On5U/ABUcymZ4AENrq8xen0c0QB9U4anLAMZmkgLjnzM/jn7U9ZnbMyTnPU+TmNre9r3AM8mFk8cndkysnjk1smNk98nDkzsnDk/smEU5vqg0ycnwU5F7jk1PtwU7cmGAPcmXk48md8xcn0Uzimvk5zpfk/8mV81BHvk7PmJ3cmA2U6fmoU8SmMU5O6JoMsm5o98n8U7Cm0UwynMU/EBf83inf8/snn8zinSU5xwGU5Snvk56GgzbSnvkyfnnkzh7jk1ymcU+SHjkw/mEC5rrkCwgWeUxAX+U6cSVjc1ql9W1qizODm8k84B2gJmYCAKgBrU+MAq9YWZizJGFRcHkAtbEAAA=="))
+///////////////////////////////////////////////
+
+///////////////////////////////////////////////
+/* Utility functions */
+
+var storagePrefix = 'KiCad_HTML_BOM__' + pcbdata.metadata.title + '__' +
+  pcbdata.metadata.revision + '__#';
+var storage;
+
+function initStorage(key) {
+  try {
+    window.localStorage.getItem("blank");
+    storage = window.localStorage;
+  } catch (e) {
+    // localStorage not available
+  }
+  if (!storage) {
+    try {
+      window.sessionStorage.getItem("blank");
+      storage = window.sessionStorage;
+    } catch (e) {
+      // sessionStorage also not available
+    }
+  }
+}
+
+function readStorage(key) {
+  if (storage) {
+    return storage.getItem(storagePrefix + key);
+  } else {
+    return null;
+  }
+}
+
+function writeStorage(key, value) {
+  if (storage) {
+    storage.setItem(storagePrefix + key, value);
+  }
+}
+
+function fancyDblClickHandler(el, onsingle, ondouble) {
+  return function() {
+    if (el.getAttribute("data-dblclick") == null) {
+      el.setAttribute("data-dblclick", 1);
+      setTimeout(function() {
+        if (el.getAttribute("data-dblclick") == 1) {
+          onsingle();
+        }
+        el.removeAttribute("data-dblclick");
+      }, 200);
+    } else {
+      el.removeAttribute("data-dblclick");
+      ondouble();
+    }
+  }
+}
+
+function smoothScrollToRow(rowid) {
+  document.getElementById(rowid).scrollIntoView({
+    behavior: "smooth",
+    block: "center",
+    inline: "nearest"
+  });
+}
+
+function focusInputField(input) {
+  input.scrollIntoView(false);
+  input.focus();
+  input.select();
+}
+
+function copyToClipboard() {
+  var text = '';
+  for (var node of bomhead.childNodes[0].childNodes) {
+    if (node.firstChild) {
+      text = text + node.firstChild.nodeValue;
+    }
+    if (node != bomhead.childNodes[0].lastChild) {
+      text += '\t';
+    }
+  }
+  text += '\n';
+  for (var row of bombody.childNodes) {
+    for (var cell of row.childNodes) {
+      for (var node of cell.childNodes) {
+        if (node.nodeName == "INPUT") {
+          if (node.checked) {
+            text = text + '✓';
+          }
+        } else if (node.nodeName == "MARK") {
+          text = text + node.firstChild.nodeValue;
+        } else {
+          text = text + node.nodeValue;
+        }
+      }
+      if (cell != row.lastChild) {
+        text += '\t';
+      }
+    }
+    text += '\n';
+  }
+  var textArea = document.createElement("textarea");
+  textArea.classList.add('clipboard-temp');
+  textArea.value = text;
+
+  document.body.appendChild(textArea);
+  textArea.focus();
+  textArea.select();
+
+  try {
+    if (document.execCommand('copy')) {
+      console.log('Bom copied to clipboard.');
+    }
+  } catch (err) {
+    console.log('Can not copy to clipboard.');
+  }
+
+  document.body.removeChild(textArea);
+}
+
+function removeGutterNode(node) {
+  for (var i = 0; i < node.childNodes.length; i++) {
+    if (node.childNodes[i].classList &&
+      node.childNodes[i].classList.contains("gutter")) {
+      node.removeChild(node.childNodes[i]);
+      break;
+    }
+  }
+}
+
+function cleanGutters() {
+  removeGutterNode(document.getElementById("bot"));
+  removeGutterNode(document.getElementById("canvasdiv"));
+}
+
+var units = {
+  prefixes: {
+    giga: ["G", "g", "giga", "Giga", "GIGA"],
+    mega: ["M", "mega", "Mega", "MEGA"],
+    kilo: ["K", "k", "kilo", "Kilo", "KILO"],
+    milli: ["m", "milli", "Milli", "MILLI"],
+    micro: ["U", "u", "micro", "Micro", "MICRO", "μ", "µ"], // different utf8 μ
+    nano: ["N", "n", "nano", "Nano", "NANO"],
+    pico: ["P", "p", "pico", "Pico", "PICO"],
+  },
+  unitsShort: ["R", "r", "Ω", "F", "f", "H", "h"],
+  unitsLong: [
+    "OHM", "Ohm", "ohm", "ohms",
+    "FARAD", "Farad", "farad",
+    "HENRY", "Henry", "henry"
+  ],
+  getMultiplier: function(s) {
+    if (this.prefixes.giga.includes(s)) return 1e9;
+    if (this.prefixes.mega.includes(s)) return 1e6;
+    if (this.prefixes.kilo.includes(s)) return 1e3;
+    if (this.prefixes.milli.includes(s)) return 1e-3;
+    if (this.prefixes.micro.includes(s)) return 1e-6;
+    if (this.prefixes.nano.includes(s)) return 1e-9;
+    if (this.prefixes.pico.includes(s)) return 1e-12;
+    return 1;
+  },
+  valueRegex: null,
+}
+
+function initUtils() {
+  var allPrefixes = units.prefixes.giga
+    .concat(units.prefixes.mega)
+    .concat(units.prefixes.kilo)
+    .concat(units.prefixes.milli)
+    .concat(units.prefixes.micro)
+    .concat(units.prefixes.nano)
+    .concat(units.prefixes.pico);
+  var allUnits = units.unitsShort.concat(units.unitsLong);
+  units.valueRegex = new RegExp("^([0-9\.]+)" +
+    "\\s*(" + allPrefixes.join("|") + ")?" +
+    "(" + allUnits.join("|") + ")?" +
+    "(\\b.*)?$", "");
+  units.valueAltRegex = new RegExp("^([0-9]*)" +
+    "(" + units.unitsShort.join("|") + ")?" +
+    "([GgMmKkUuNnPp])?" +
+    "([0-9]*)" +
+    "(\\b.*)?$", "");
+  if (config.fields.includes("Value")) {
+    var index = config.fields.indexOf("Value");
+    pcbdata.bom["parsedValues"] = {};
+    for (var id in pcbdata.bom.fields) {
+      pcbdata.bom.parsedValues[id] = parseValue(pcbdata.bom.fields[id][index])
+    }
+  }
+}
+
+function parseValue(val, ref) {
+  var inferUnit = (unit, ref) => {
+    if (unit) {
+      unit = unit.toLowerCase();
+      if (unit == 'Ω' || unit == "ohm" || unit == "ohms") {
+        unit = 'r';
+      }
+      unit = unit[0];
+    } else {
+      ref = /^([a-z]+)\d+$/i.exec(ref);
+      if (ref) {
+        ref = ref[1].toLowerCase();
+        if (ref == "c") unit = 'f';
+        else if (ref == "l") unit = 'h';
+        else if (ref == "r" || ref == "rv") unit = 'r';
+        else unit = null;
+      }
+    }
+    return unit;
+  };
+  val = val.replace(/,/g, "");
+  var match = units.valueRegex.exec(val);
+  var unit;
+  if (match) {
+    val = parseFloat(match[1]);
+    if (match[2]) {
+      val = val * units.getMultiplier(match[2]);
+    }
+    unit = inferUnit(match[3], ref);
+    if (!unit) return null;
+    else return {
+      val: val,
+      unit: unit,
+      extra: match[4],
+    }
+  }
+  match = units.valueAltRegex.exec(val);
+  if (match && (match[1] || match[4])) {
+    val = parseFloat(match[1] + "." + match[4]);
+    if (match[3]) {
+      val = val * units.getMultiplier(match[3]);
+    }
+    unit = inferUnit(match[2], ref);
+    if (!unit) return null;
+    else return {
+      val: val,
+      unit: unit,
+      extra: match[5],
+    }
+  }
+  return null;
+}
+
+function valueCompare(a, b, stra, strb) {
+  if (a === null && b === null) {
+    // Failed to parse both values, compare them as strings.
+    if (stra != strb) return stra > strb ? 1 : -1;
+    else return 0;
+  } else if (a === null) {
+    return 1;
+  } else if (b === null) {
+    return -1;
+  } else {
+    if (a.unit != b.unit) return a.unit > b.unit ? 1 : -1;
+    else if (a.val != b.val) return a.val > b.val ? 1 : -1;
+    else if (a.extra != b.extra) return a.extra > b.extra ? 1 : -1;
+    else return 0;
+  }
+}
+
+function validateSaveImgDimension(element) {
+  var valid = false;
+  var intValue = 0;
+  if (/^[1-9]\d*$/.test(element.value)) {
+    intValue = parseInt(element.value);
+    if (intValue <= 16000) {
+      valid = true;
+    }
+  }
+  if (valid) {
+    element.classList.remove("invalid");
+  } else {
+    element.classList.add("invalid");
+  }
+  return intValue;
+}
+
+function saveImage(layer) {
+  var width = validateSaveImgDimension(document.getElementById("render-save-width"));
+  var height = validateSaveImgDimension(document.getElementById("render-save-height"));
+  var bgcolor = null;
+  if (!document.getElementById("render-save-transparent").checked) {
+    var style = getComputedStyle(topmostdiv);
+    bgcolor = style.getPropertyValue("background-color");
+  }
+  if (!width || !height) return;
+
+  // Prepare image
+  var canvas = document.createElement("canvas");
+  var layerdict = {
+    transform: {
+      x: 0,
+      y: 0,
+      s: 1,
+      panx: 0,
+      pany: 0,
+      zoom: 1,
+    },
+    bg: canvas,
+    fab: canvas,
+    silk: canvas,
+    highlight: canvas,
+    layer: layer,
+  }
+  // Do the rendering
+  recalcLayerScale(layerdict, width, height);
+  prepareLayer(layerdict);
+  clearCanvas(canvas, bgcolor);
+  drawBackground(layerdict, false);
+  drawHighlightsOnLayer(layerdict, false);
+
+  // Save image
+  var imgdata = canvas.toDataURL("image/png");
+
+  var filename = pcbdata.metadata.title;
+  if (pcbdata.metadata.revision) {
+    filename += `.${pcbdata.metadata.revision}`;
+  }
+  filename += `.${layer}.png`;
+  saveFile(filename, dataURLtoBlob(imgdata));
+}
+
+function saveSettings() {
+  var data = {
+    type: "InteractiveHtmlBom settings",
+    version: 1,
+    pcbmetadata: pcbdata.metadata,
+    settings: settings,
+  }
+  var blob = new Blob([JSON.stringify(data, null, 4)], {
+    type: "application/json"
+  });
+  saveFile(`${pcbdata.metadata.title}.settings.json`, blob);
+}
+
+function loadSettings() {
+  var input = document.createElement("input");
+  input.type = "file";
+  input.accept = ".settings.json";
+  input.onchange = function(e) {
+    var file = e.target.files[0];
+    var reader = new FileReader();
+    reader.onload = readerEvent => {
+      var content = readerEvent.target.result;
+      var newSettings;
+      try {
+        newSettings = JSON.parse(content);
+      } catch (e) {
+        alert("Selected file is not InteractiveHtmlBom settings file.");
+        return;
+      }
+      if (newSettings.type != "InteractiveHtmlBom settings") {
+        alert("Selected file is not InteractiveHtmlBom settings file.");
+        return;
+      }
+      var metadataMatches = newSettings.hasOwnProperty("pcbmetadata");
+      if (metadataMatches) {
+        for (var k in pcbdata.metadata) {
+          if (!newSettings.pcbmetadata.hasOwnProperty(k) || newSettings.pcbmetadata[k] != pcbdata.metadata[k]) {
+            metadataMatches = false;
+          }
+        }
+      }
+      if (!metadataMatches) {
+        var currentMetadata = JSON.stringify(pcbdata.metadata, null, 4);
+        var fileMetadata = JSON.stringify(newSettings.pcbmetadata, null, 4);
+        if (!confirm(
+            `Settins file metadata does not match current metadata.\n\n` +
+            `Page metadata:\n${currentMetadata}\n\n` +
+            `Settings file metadata:\n${fileMetadata}\n\n` +
+            `Press OK if you would like to import settings anyway.`)) {
+          return;
+        }
+      }
+      overwriteSettings(newSettings.settings);
+    }
+    reader.readAsText(file, 'UTF-8');
+  }
+  input.click();
+}
+
+function overwriteSettings(newSettings) {
+  initDone = false;
+  Object.assign(settings, newSettings);
+  writeStorage("bomlayout", settings.bomlayout);
+  writeStorage("bommode", settings.bommode);
+  writeStorage("canvaslayout", settings.canvaslayout);
+  writeStorage("bomCheckboxes", settings.checkboxes.join(","));
+  document.getElementById("bomCheckboxes").value = settings.checkboxes.join(",");
+  for (var checkbox of settings.checkboxes) {
+    writeStorage("checkbox_" + checkbox, settings.checkboxStoredRefs[checkbox]);
+  }
+  writeStorage("markWhenChecked", settings.markWhenChecked);
+  padsVisible(settings.renderPads);
+  document.getElementById("padsCheckbox").checked = settings.renderPads;
+  fabricationVisible(settings.renderFabrication);
+  document.getElementById("fabricationCheckbox").checked = settings.renderFabrication;
+  silkscreenVisible(settings.renderSilkscreen);
+  document.getElementById("silkscreenCheckbox").checked = settings.renderSilkscreen;
+  referencesVisible(settings.renderReferences);
+  document.getElementById("referencesCheckbox").checked = settings.renderReferences;
+  valuesVisible(settings.renderValues);
+  document.getElementById("valuesCheckbox").checked = settings.renderValues;
+  tracksVisible(settings.renderTracks);
+  document.getElementById("tracksCheckbox").checked = settings.renderTracks;
+  zonesVisible(settings.renderZones);
+  document.getElementById("zonesCheckbox").checked = settings.renderZones;
+  dnpOutline(settings.renderDnpOutline);
+  document.getElementById("dnpOutlineCheckbox").checked = settings.renderDnpOutline;
+  setRedrawOnDrag(settings.redrawOnDrag);
+  document.getElementById("dragCheckbox").checked = settings.redrawOnDrag;
+  setDarkMode(settings.darkMode);
+  document.getElementById("darkmodeCheckbox").checked = settings.darkMode;
+  setHighlightPin1(settings.highlightpin1);
+  document.getElementById("highlightpin1Checkbox").checked = settings.highlightpin1;
+  showFootprints(settings.show_footprints);
+  writeStorage("boardRotation", settings.boardRotation);
+  document.getElementById("boardRotation").value = settings.boardRotation / 5;
+  document.getElementById("rotationDegree").textContent = settings.boardRotation;
+  initDone = true;
+  prepCheckboxes();
+  changeBomLayout(settings.bomlayout);
+}
+
+function saveFile(filename, blob) {
+  var link = document.createElement("a");
+  var objurl = URL.createObjectURL(blob);
+  link.download = filename;
+  link.href = objurl;
+  link.click();
+}
+
+function dataURLtoBlob(dataurl) {
+  var arr = dataurl.split(','),
+    mime = arr[0].match(/:(.*?);/)[1],
+    bstr = atob(arr[1]),
+    n = bstr.length,
+    u8arr = new Uint8Array(n);
+  while (n--) {
+    u8arr[n] = bstr.charCodeAt(n);
+  }
+  return new Blob([u8arr], {
+    type: mime
+  });
+}
+
+var settings = {
+  canvaslayout: "default",
+  bomlayout: "default",
+  bommode: "grouped",
+  checkboxes: [],
+  checkboxStoredRefs: {},
+  darkMode: false,
+  highlightpin1: false,
+  redrawOnDrag: true,
+  boardRotation: 0,
+  renderPads: true,
+  renderReferences: true,
+  renderValues: true,
+  renderSilkscreen: true,
+  renderFabrication: true,
+  renderDnpOutline: false,
+  renderTracks: true,
+  renderZones: true,
+  columnOrder: [],
+  hiddenColumns: [],
+}
+
+function initDefaults() {
+  settings.bomlayout = readStorage("bomlayout");
+  if (settings.bomlayout === null) {
+    settings.bomlayout = config.bom_view;
+  }
+  if (!['bom-only', 'left-right', 'top-bottom'].includes(settings.bomlayout)) {
+    settings.bomlayout = config.bom_view;
+  }
+  settings.bommode = readStorage("bommode");
+  if (settings.bommode === null) {
+    settings.bommode = "grouped";
+  }
+  if (!["grouped", "ungrouped", "netlist"].includes(settings.bommode)) {
+    settings.bommode = "grouped";
+  }
+  settings.canvaslayout = readStorage("canvaslayout");
+  if (settings.canvaslayout === null) {
+    settings.canvaslayout = config.layer_view;
+  }
+  var bomCheckboxes = readStorage("bomCheckboxes");
+  if (bomCheckboxes === null) {
+    bomCheckboxes = config.checkboxes;
+  }
+  settings.checkboxes = bomCheckboxes.split(",").filter((e) => e);
+  document.getElementById("bomCheckboxes").value = bomCheckboxes;
+
+  settings.markWhenChecked = readStorage("markWhenChecked") || "";
+  populateMarkWhenCheckedOptions();
+
+  function initBooleanSetting(storageString, def, elementId, func) {
+    var b = readStorage(storageString);
+    if (b === null) {
+      b = def;
+    } else {
+      b = (b == "true");
+    }
+    document.getElementById(elementId).checked = b;
+    func(b);
+  }
+
+  initBooleanSetting("padsVisible", config.show_pads, "padsCheckbox", padsVisible);
+  initBooleanSetting("fabricationVisible", config.show_fabrication, "fabricationCheckbox", fabricationVisible);
+  initBooleanSetting("silkscreenVisible", config.show_silkscreen, "silkscreenCheckbox", silkscreenVisible);
+  initBooleanSetting("referencesVisible", true, "referencesCheckbox", referencesVisible);
+  initBooleanSetting("valuesVisible", true, "valuesCheckbox", valuesVisible);
+  if ("tracks" in pcbdata) {
+    initBooleanSetting("tracksVisible", true, "tracksCheckbox", tracksVisible);
+    initBooleanSetting("zonesVisible", true, "zonesCheckbox", zonesVisible);
+  } else {
+    document.getElementById("tracksAndZonesCheckboxes").style.display = "none";
+    tracksVisible(false);
+    zonesVisible(false);
+  }
+  initBooleanSetting("dnpOutline", false, "dnpOutlineCheckbox", dnpOutline);
+  initBooleanSetting("redrawOnDrag", config.redraw_on_drag, "dragCheckbox", setRedrawOnDrag);
+  initBooleanSetting("darkmode", config.dark_mode, "darkmodeCheckbox", setDarkMode);
+  initBooleanSetting("highlightpin1", config.highlight_pin1, "highlightpin1Checkbox", setHighlightPin1);
+
+  var fields = ["checkboxes", "References"].concat(config.fields).concat(["Quantity"]);
+  var hcols = JSON.parse(readStorage("hiddenColumns"));
+  if (hcols === null) {
+    hcols = [];
+  }
+  settings.hiddenColumns = hcols.filter(e => fields.includes(e));
+
+  var cord = JSON.parse(readStorage("columnOrder"));
+  if (cord === null) {
+    cord = fields;
+  } else {
+    cord = cord.filter(e => fields.includes(e));
+    if (cord.length != fields.length)
+      cord = fields;
+  }
+  settings.columnOrder = cord;
+
+  settings.boardRotation = readStorage("boardRotation");
+  if (settings.boardRotation === null) {
+    settings.boardRotation = config.board_rotation * 5;
+  } else {
+    settings.boardRotation = parseInt(settings.boardRotation);
+  }
+  document.getElementById("boardRotation").value = settings.boardRotation / 5;
+  document.getElementById("rotationDegree").textContent = settings.boardRotation;
+}
+
+// Helper classes for user js callbacks.
+
+const IBOM_EVENT_TYPES = {
+  ALL: "all",
+  HIGHLIGHT_EVENT: "highlightEvent",
+  CHECKBOX_CHANGE_EVENT: "checkboxChangeEvent",
+  BOM_BODY_CHANGE_EVENT: "bomBodyChangeEvent",
+}
+
+const EventHandler = {
+  callbacks: {},
+  init: function() {
+    for (eventType of Object.values(IBOM_EVENT_TYPES))
+      this.callbacks[eventType] = [];
+  },
+  registerCallback: function(eventType, callback) {
+    this.callbacks[eventType].push(callback);
+  },
+  emitEvent: function(eventType, eventArgs) {
+    event = {
+      eventType: eventType,
+      args: eventArgs,
+    }
+    var callback;
+    for (callback of this.callbacks[eventType])
+      callback(event);
+    for (callback of this.callbacks[IBOM_EVENT_TYPES.ALL])
+      callback(event);
+  }
+}
+EventHandler.init();
+
+///////////////////////////////////////////////
+
+///////////////////////////////////////////////
+/* PCB rendering code */
+
+var emptyContext2d = document.createElement("canvas").getContext("2d");
+
+function deg2rad(deg) {
+  return deg * Math.PI / 180;
+}
+
+function calcFontPoint(linepoint, text, offsetx, offsety, tilt) {
+  var point = [
+    linepoint[0] * text.width + offsetx,
+    linepoint[1] * text.height + offsety
+  ];
+  // This approximates pcbnew behavior with how text tilts depending on horizontal justification
+  point[0] -= (linepoint[1] + 0.5 * (1 + text.justify[0])) * text.height * tilt;
+  return point;
+}
+
+function drawText(ctx, text, color) {
+  if ("ref" in text && !settings.renderReferences) return;
+  if ("val" in text && !settings.renderValues) return;
+  ctx.save();
+  ctx.fillStyle = color;
+  ctx.strokeStyle = color;
+  ctx.lineCap = "round";
+  ctx.lineJoin = "round";
+  ctx.lineWidth = text.thickness;
+  if ("svgpath" in text) {
+    ctx.stroke(new Path2D(text.svgpath));
+    ctx.restore();
+    return;
+  }
+  ctx.translate(...text.pos);
+  ctx.translate(text.thickness * 0.5, 0);
+  var angle = -text.angle;
+  if (text.attr.includes("mirrored")) {
+    ctx.scale(-1, 1);
+    angle = -angle;
+  }
+  var tilt = 0;
+  if (text.attr.includes("italic")) {
+    tilt = 0.125;
+  }
+  var interline = text.height * 1.5 + text.thickness;
+  var txt = text.text.split("\n");
+  // KiCad ignores last empty line.
+  if (txt[txt.length - 1] == '') txt.pop();
+  ctx.rotate(deg2rad(angle));
+  var offsety = (1 - text.justify[1]) / 2 * text.height; // One line offset
+  offsety -= (txt.length - 1) * (text.justify[1] + 1) / 2 * interline; // Multiline offset
+  for (var i in txt) {
+    var lineWidth = text.thickness + interline / 2 * tilt;
+    for (var j = 0; j < txt[i].length; j++) {
+      if (txt[i][j] == '\t') {
+        var fourSpaces = 4 * pcbdata.font_data[' '].w * text.width;
+        lineWidth += fourSpaces - lineWidth % fourSpaces;
+      } else {
+        if (txt[i][j] == '~') {
+          j++;
+          if (j == txt[i].length)
+            break;
+        }
+        lineWidth += pcbdata.font_data[txt[i][j]].w * text.width;
+      }
+    }
+    var offsetx = -lineWidth * (text.justify[0] + 1) / 2;
+    var inOverbar = false;
+    for (var j = 0; j < txt[i].length; j++) {
+      if (txt[i][j] == '\t') {
+        var fourSpaces = 4 * pcbdata.font_data[' '].w * text.width;
+        offsetx += fourSpaces - offsetx % fourSpaces;
+        continue;
+      } else if (txt[i][j] == '~') {
+        j++;
+        if (j == txt[i].length)
+          break;
+        if (txt[i][j] != '~') {
+          inOverbar = !inOverbar;
+        }
+      }
+      var glyph = pcbdata.font_data[txt[i][j]];
+      if (inOverbar) {
+        var overbarStart = [offsetx, -text.height * 1.4 + offsety];
+        var overbarEnd = [offsetx + text.width * glyph.w, overbarStart[1]];
+
+        if (!lastHadOverbar) {
+          overbarStart[0] += text.height * 1.4 * tilt;
+          lastHadOverbar = true;
+        }
+        ctx.beginPath();
+        ctx.moveTo(...overbarStart);
+        ctx.lineTo(...overbarEnd);
+        ctx.stroke();
+      } else {
+        lastHadOverbar = false;
+      }
+      for (var line of glyph.l) {
+        ctx.beginPath();
+        ctx.moveTo(...calcFontPoint(line[0], text, offsetx, offsety, tilt));
+        for (var k = 1; k < line.length; k++) {
+          ctx.lineTo(...calcFontPoint(line[k], text, offsetx, offsety, tilt));
+        }
+        ctx.stroke();
+      }
+      offsetx += glyph.w * text.width;
+    }
+    offsety += interline;
+  }
+  ctx.restore();
+}
+
+function drawedge(ctx, scalefactor, edge, color) {
+  ctx.strokeStyle = color;
+  ctx.fillStyle = color;
+  ctx.lineWidth = Math.max(1 / scalefactor, edge.width);
+  ctx.lineCap = "round";
+  ctx.lineJoin = "round";
+  if ("svgpath" in edge) {
+    ctx.stroke(new Path2D(edge.svgpath));
+  } else {
+    ctx.beginPath();
+    if (edge.type == "segment") {
+      ctx.moveTo(...edge.start);
+      ctx.lineTo(...edge.end);
+    }
+    if (edge.type == "rect") {
+      ctx.moveTo(...edge.start);
+      ctx.lineTo(edge.start[0], edge.end[1]);
+      ctx.lineTo(...edge.end);
+      ctx.lineTo(edge.end[0], edge.start[1]);
+      ctx.lineTo(...edge.start);
+    }
+    if (edge.type == "arc") {
+      ctx.arc(
+        ...edge.start,
+        edge.radius,
+        deg2rad(edge.startangle),
+        deg2rad(edge.endangle));
+    }
+    if (edge.type == "circle") {
+      ctx.arc(
+        ...edge.start,
+        edge.radius,
+        0, 2 * Math.PI);
+      ctx.closePath();
+    }
+    if (edge.type == "curve") {
+      ctx.moveTo(...edge.start);
+      ctx.bezierCurveTo(...edge.cpa, ...edge.cpb, ...edge.end);
+    }
+    if("filled" in edge && edge.filled)
+      ctx.fill();
+    else
+      ctx.stroke();
+  }
+}
+
+function getChamferedRectPath(size, radius, chamfpos, chamfratio) {
+  // chamfpos is a bitmask, left = 1, right = 2, bottom left = 4, bottom right = 8
+  var path = new Path2D();
+  var width = size[0];
+  var height = size[1];
+  var x = width * -0.5;
+  var y = height * -0.5;
+  var chamfOffset = Math.min(width, height) * chamfratio;
+  path.moveTo(x, 0);
+  if (chamfpos & 4) {
+    path.lineTo(x, y + height - chamfOffset);
+    path.lineTo(x + chamfOffset, y + height);
+    path.lineTo(0, y + height);
+  } else {
+    path.arcTo(x, y + height, x + width, y + height, radius);
+  }
+  if (chamfpos & 8) {
+    path.lineTo(x + width - chamfOffset, y + height);
+    path.lineTo(x + width, y + height - chamfOffset);
+    path.lineTo(x + width, 0);
+  } else {
+    path.arcTo(x + width, y + height, x + width, y, radius);
+  }
+  if (chamfpos & 2) {
+    path.lineTo(x + width, y + chamfOffset);
+    path.lineTo(x + width - chamfOffset, y);
+    path.lineTo(0, y);
+  } else {
+    path.arcTo(x + width, y, x, y, radius);
+  }
+  if (chamfpos & 1) {
+    path.lineTo(x + chamfOffset, y);
+    path.lineTo(x, y + chamfOffset);
+    path.lineTo(x, 0);
+  } else {
+    path.arcTo(x, y, x, y + height, radius);
+  }
+  path.closePath();
+  return path;
+}
+
+function getOblongPath(size) {
+  return getChamferedRectPath(size, Math.min(size[0], size[1]) / 2, 0, 0);
+}
+
+function getPolygonsPath(shape) {
+  if (shape.path2d) {
+    return shape.path2d;
+  }
+  if ("svgpath" in shape) {
+    shape.path2d = new Path2D(shape.svgpath);
+  } else {
+    var path = new Path2D();
+    for (var polygon of shape.polygons) {
+      path.moveTo(...polygon[0]);
+      for (var i = 1; i < polygon.length; i++) {
+        path.lineTo(...polygon[i]);
+      }
+      path.closePath();
+    }
+    shape.path2d = path;
+  }
+  return shape.path2d;
+}
+
+function drawPolygonShape(ctx, scalefactor, shape, color) {
+  ctx.save();
+  if (!("svgpath" in shape)) {
+    ctx.translate(...shape.pos);
+    ctx.rotate(deg2rad(-shape.angle));
+  }
+  if("filled" in shape && !shape.filled) {
+    ctx.strokeStyle = color;
+    ctx.lineWidth = Math.max(1 / scalefactor, shape.width);
+    ctx.lineCap = "round";
+    ctx.lineJoin = "round";
+    ctx.stroke(getPolygonsPath(shape));
+  } else {
+    ctx.fillStyle = color;
+    ctx.fill(getPolygonsPath(shape));
+  }
+  ctx.restore();
+}
+
+function drawDrawing(ctx, scalefactor, drawing, color) {
+  if (["segment", "arc", "circle", "curve", "rect"].includes(drawing.type)) {
+    drawedge(ctx, scalefactor, drawing, color);
+  } else if (drawing.type == "polygon") {
+    drawPolygonShape(ctx, scalefactor, drawing, color);
+  } else {
+    drawText(ctx, drawing, color);
+  }
+}
+
+function getCirclePath(radius) {
+  var path = new Path2D();
+  path.arc(0, 0, radius, 0, 2 * Math.PI);
+  path.closePath();
+  return path;
+}
+
+function getCachedPadPath(pad) {
+  if (!pad.path2d) {
+    // if path2d is not set, build one and cache it on pad object
+    if (pad.shape == "rect") {
+      pad.path2d = new Path2D();
+      pad.path2d.rect(...pad.size.map(c => -c * 0.5), ...pad.size);
+    } else if (pad.shape == "oval") {
+      pad.path2d = getOblongPath(pad.size);
+    } else if (pad.shape == "circle") {
+      pad.path2d = getCirclePath(pad.size[0] / 2);
+    } else if (pad.shape == "roundrect") {
+      pad.path2d = getChamferedRectPath(pad.size, pad.radius, 0, 0);
+    } else if (pad.shape == "chamfrect") {
+      pad.path2d = getChamferedRectPath(pad.size, pad.radius, pad.chamfpos, pad.chamfratio)
+    } else if (pad.shape == "custom") {
+      pad.path2d = getPolygonsPath(pad);
+    }
+  }
+  return pad.path2d;
+}
+
+function drawPad(ctx, pad, color, outline) {
+  ctx.save();
+  ctx.translate(...pad.pos);
+  ctx.rotate(deg2rad(pad.angle));
+  if (pad.offset) {
+    ctx.translate(...pad.offset);
+  }
+  ctx.fillStyle = color;
+  ctx.strokeStyle = color;
+  var path = getCachedPadPath(pad);
+  if (outline) {
+    ctx.stroke(path);
+  } else {
+    ctx.fill(path);
+  }
+  ctx.restore();
+}
+
+function drawPadHole(ctx, pad, padHoleColor) {
+  if (pad.type != "th") return;
+  ctx.save();
+  ctx.translate(...pad.pos);
+  ctx.rotate(deg2rad(pad.angle));
+  ctx.fillStyle = padHoleColor;
+  if (pad.drillshape == "oblong") {
+    ctx.fill(getOblongPath(pad.drillsize));
+  } else {
+    ctx.fill(getCirclePath(pad.drillsize[0] / 2));
+  }
+  ctx.restore();
+}
+
+function drawFootprint(ctx, layer, scalefactor, footprint, colors, highlight, outline) {
+  if (highlight) {
+    // draw bounding box
+    if (footprint.layer == layer) {
+      ctx.save();
+      ctx.globalAlpha = 0.2;
+      ctx.translate(...footprint.bbox.pos);
+      ctx.rotate(deg2rad(-footprint.bbox.angle));
+      ctx.translate(...footprint.bbox.relpos);
+      ctx.fillStyle = colors.pad;
+      ctx.fillRect(0, 0, ...footprint.bbox.size);
+      ctx.globalAlpha = 1;
+      ctx.strokeStyle = colors.pad;
+      ctx.strokeRect(0, 0, ...footprint.bbox.size);
+      ctx.restore();
+    }
+  }
+  // draw drawings
+  for (var drawing of footprint.drawings) {
+    if (drawing.layer == layer) {
+      drawDrawing(ctx, scalefactor, drawing.drawing, colors.pad);
+    }
+  }
+  // draw pads
+  if (settings.renderPads) {
+    for (var pad of footprint.pads) {
+      if (pad.layers.includes(layer)) {
+        drawPad(ctx, pad, colors.pad, outline);
+        if (pad.pin1 && settings.highlightpin1) {
+          drawPad(ctx, pad, colors.outline, true);
+        }
+      }
+    }
+    for (var pad of footprint.pads) {
+      drawPadHole(ctx, pad, colors.padHole);
+    }
+  }
+}
+
+function drawEdgeCuts(canvas, scalefactor) {
+  var ctx = canvas.getContext("2d");
+  var edgecolor = getComputedStyle(topmostdiv).getPropertyValue('--pcb-edge-color');
+  for (var edge of pcbdata.edges) {
+    drawDrawing(ctx, scalefactor, edge, edgecolor);
+  }
+}
+
+function drawFootprints(canvas, layer, scalefactor, highlight) {
+  var ctx = canvas.getContext("2d");
+  ctx.lineWidth = 3 / scalefactor;
+  var style = getComputedStyle(topmostdiv);
+
+  var colors = {
+    pad: style.getPropertyValue('--pad-color'),
+    padHole: style.getPropertyValue('--pad-hole-color'),
+    outline: style.getPropertyValue('--pin1-outline-color'),
+  }
+
+  for (var i = 0; i < pcbdata.footprints.length; i++) {
+    var mod = pcbdata.footprints[i];
+    var outline = settings.renderDnpOutline && pcbdata.bom.skipped.includes(i);
+    var h = highlightedFootprints.includes(i);
+    var d = markedFootprints.has(i);
+    if (highlight) {
+      if(h && d) {
+        colors.pad = style.getPropertyValue('--pad-color-highlight-both');
+        colors.outline = style.getPropertyValue('--pin1-outline-color-highlight-both');
+      } else if (h) {
+        colors.pad = style.getPropertyValue('--pad-color-highlight');
+        colors.outline = style.getPropertyValue('--pin1-outline-color-highlight');
+      } else if (d) {
+        colors.pad = style.getPropertyValue('--pad-color-highlight-marked');
+        colors.outline = style.getPropertyValue('--pin1-outline-color-highlight-marked');
+      }
+    }
+    if( h || d || !highlight) {
+      drawFootprint(ctx, layer, scalefactor, mod, colors, highlight, outline);
+    }
+  }
+}
+
+function drawBgLayer(layername, canvas, layer, scalefactor, edgeColor, polygonColor, textColor) {
+  var ctx = canvas.getContext("2d");
+  for (var d of pcbdata.drawings[layername][layer]) {
+    if (["segment", "arc", "circle", "curve", "rect"].includes(d.type)) {
+      drawedge(ctx, scalefactor, d, edgeColor);
+    } else if (d.type == "polygon") {
+      drawPolygonShape(ctx, scalefactor, d, polygonColor);
+    } else {
+      drawText(ctx, d, textColor);
+    }
+  }
+}
+
+function drawTracks(canvas, layer, color, highlight) {
+  ctx = canvas.getContext("2d");
+  ctx.strokeStyle = color;
+  ctx.lineCap = "round";
+  for (var track of pcbdata.tracks[layer]) {
+    if (highlight && highlightedNet != track.net) continue;
+    ctx.lineWidth = track.width;
+    ctx.beginPath();
+    if ('radius' in track) {
+      ctx.arc(
+        ...track.center,
+        track.radius,
+        deg2rad(track.startangle),
+        deg2rad(track.endangle));
+    } else {
+      ctx.moveTo(...track.start);
+      ctx.lineTo(...track.end);
+    }
+    ctx.stroke();
+  }
+}
+
+function drawZones(canvas, layer, color, highlight) {
+  ctx = canvas.getContext("2d");
+  ctx.strokeStyle = color;
+  ctx.fillStyle = color;
+  ctx.lineJoin = "round";
+  for (var zone of pcbdata.zones[layer]) {
+    if (!zone.path2d) {
+      zone.path2d = getPolygonsPath(zone);
+    }
+    if (highlight && highlightedNet != zone.net) continue;
+    ctx.fill(zone.path2d);
+    if (zone.width > 0) {
+      ctx.lineWidth = zone.width;
+      ctx.stroke(zone.path2d);
+    }
+  }
+}
+
+function clearCanvas(canvas, color = null) {
+  var ctx = canvas.getContext("2d");
+  ctx.save();
+  ctx.setTransform(1, 0, 0, 1, 0, 0);
+  if (color) {
+    ctx.fillStyle = color;
+    ctx.fillRect(0, 0, canvas.width, canvas.height);
+  } else {
+    if (!window.matchMedia("print").matches)
+      ctx.clearRect(0, 0, canvas.width, canvas.height);
+  }
+  ctx.restore();
+}
+
+function drawNets(canvas, layer, highlight) {
+  var style = getComputedStyle(topmostdiv);
+  if (settings.renderTracks) {
+    var trackColor = style.getPropertyValue(highlight ? '--track-color-highlight' : '--track-color');
+    drawTracks(canvas, layer, trackColor, highlight);
+  }
+  if (settings.renderZones) {
+    var zoneColor = style.getPropertyValue(highlight ? '--zone-color-highlight' : '--zone-color');
+    drawZones(canvas, layer, zoneColor, highlight);
+  }
+  if (highlight && settings.renderPads) {
+    var padColor = style.getPropertyValue('--pad-color-highlight');
+    var padHoleColor = style.getPropertyValue('--pad-hole-color');
+    var ctx = canvas.getContext("2d");
+    for (var footprint of pcbdata.footprints) {
+      // draw pads
+      var padDrawn = false;
+      for (var pad of footprint.pads) {
+        if (highlightedNet != pad.net) continue;
+        if (pad.layers.includes(layer)) {
+          drawPad(ctx, pad, padColor, false);
+          padDrawn = true;
+        }
+      }
+      if (padDrawn) {
+        // redraw all pad holes because some pads may overlap
+        for (var pad of footprint.pads) {
+          drawPadHole(ctx, pad, padHoleColor);
+        }
+      }
+    }
+  }
+}
+
+function drawHighlightsOnLayer(canvasdict, clear = true) {
+  if (clear) {
+    clearCanvas(canvasdict.highlight);
+  }
+  if (markedFootprints.size > 0 || highlightedFootprints.length > 0) {
+    drawFootprints(canvasdict.highlight, canvasdict.layer,
+      canvasdict.transform.s * canvasdict.transform.zoom, true);
+  }
+  if (highlightedNet !== null) {
+    drawNets(canvasdict.highlight, canvasdict.layer, true);
+  }
+}
+
+function drawHighlights() {
+  drawHighlightsOnLayer(allcanvas.front);
+  drawHighlightsOnLayer(allcanvas.back);
+}
+
+function drawBackground(canvasdict, clear = true) {
+  if (clear) {
+    clearCanvas(canvasdict.bg);
+    clearCanvas(canvasdict.fab);
+    clearCanvas(canvasdict.silk);
+  }
+
+  drawNets(canvasdict.bg, canvasdict.layer, false);
+  drawFootprints(canvasdict.bg, canvasdict.layer,
+    canvasdict.transform.s * canvasdict.transform.zoom, false);
+
+  drawEdgeCuts(canvasdict.bg, canvasdict.transform.s * canvasdict.transform.zoom);
+
+  var style = getComputedStyle(topmostdiv);
+  var edgeColor = style.getPropertyValue('--silkscreen-edge-color');
+  var polygonColor = style.getPropertyValue('--silkscreen-polygon-color');
+  var textColor = style.getPropertyValue('--silkscreen-text-color');
+  if (settings.renderSilkscreen) {
+    drawBgLayer(
+      "silkscreen", canvasdict.silk, canvasdict.layer,
+      canvasdict.transform.s * canvasdict.transform.zoom,
+      edgeColor, polygonColor, textColor);
+  }
+  edgeColor = style.getPropertyValue('--fabrication-edge-color');
+  polygonColor = style.getPropertyValue('--fabrication-polygon-color');
+  textColor = style.getPropertyValue('--fabrication-text-color');
+  if (settings.renderFabrication) {
+    drawBgLayer(
+      "fabrication", canvasdict.fab, canvasdict.layer,
+      canvasdict.transform.s * canvasdict.transform.zoom,
+      edgeColor, polygonColor, textColor);
+  }
+}
+
+function prepareCanvas(canvas, flip, transform) {
+  var ctx = canvas.getContext("2d");
+  ctx.setTransform(1, 0, 0, 1, 0, 0);
+  var fontsize = 1.55;
+  ctx.scale(transform.zoom, transform.zoom);
+  ctx.translate(transform.panx, transform.pany);
+  if (flip) {
+    ctx.scale(-1, 1);
+  }
+  ctx.translate(transform.x, transform.y);
+  ctx.rotate(deg2rad(settings.boardRotation));
+  ctx.scale(transform.s, transform.s);
+}
+
+function prepareLayer(canvasdict) {
+  var flip = (canvasdict.layer == "B");
+  for (var c of ["bg", "fab", "silk", "highlight"]) {
+    prepareCanvas(canvasdict[c], flip, canvasdict.transform);
+  }
+}
+
+function rotateVector(v, angle) {
+  angle = deg2rad(angle);
+  return [
+    v[0] * Math.cos(angle) - v[1] * Math.sin(angle),
+    v[0] * Math.sin(angle) + v[1] * Math.cos(angle)
+  ];
+}
+
+function applyRotation(bbox) {
+  var corners = [
+    [bbox.minx, bbox.miny],
+    [bbox.minx, bbox.maxy],
+    [bbox.maxx, bbox.miny],
+    [bbox.maxx, bbox.maxy],
+  ];
+  corners = corners.map((v) => rotateVector(v, settings.boardRotation));
+  return {
+    minx: corners.reduce((a, v) => Math.min(a, v[0]), Infinity),
+    miny: corners.reduce((a, v) => Math.min(a, v[1]), Infinity),
+    maxx: corners.reduce((a, v) => Math.max(a, v[0]), -Infinity),
+    maxy: corners.reduce((a, v) => Math.max(a, v[1]), -Infinity),
+  }
+}
+
+function recalcLayerScale(layerdict, width, height) {
+  var bbox = applyRotation(pcbdata.edges_bbox);
+  var scalefactor = 0.98 * Math.min(
+    width / (bbox.maxx - bbox.minx),
+    height / (bbox.maxy - bbox.miny)
+  );
+  if (scalefactor < 0.1) {
+    scalefactor = 1;
+  }
+  layerdict.transform.s = scalefactor;
+  var flip = (layerdict.layer == "B");
+  if (flip) {
+    layerdict.transform.x = -((bbox.maxx + bbox.minx) * scalefactor + width) * 0.5;
+  } else {
+    layerdict.transform.x = -((bbox.maxx + bbox.minx) * scalefactor - width) * 0.5;
+  }
+  layerdict.transform.y = -((bbox.maxy + bbox.miny) * scalefactor - height) * 0.5;
+  for (var c of ["bg", "fab", "silk", "highlight"]) {
+    canvas = layerdict[c];
+    canvas.width = width;
+    canvas.height = height;
+    canvas.style.width = (width / devicePixelRatio) + "px";
+    canvas.style.height = (height / devicePixelRatio) + "px";
+  }
+}
+
+function redrawCanvas(layerdict) {
+  prepareLayer(layerdict);
+  drawBackground(layerdict);
+  drawHighlightsOnLayer(layerdict);
+}
+
+function resizeCanvas(layerdict) {
+  var canvasdivid = {
+    "F": "frontcanvas",
+    "B": "backcanvas"
+  } [layerdict.layer];
+  var width = document.getElementById(canvasdivid).clientWidth * devicePixelRatio;
+  var height = document.getElementById(canvasdivid).clientHeight * devicePixelRatio;
+  recalcLayerScale(layerdict, width, height);
+  redrawCanvas(layerdict);
+}
+
+function resizeAll() {
+  resizeCanvas(allcanvas.front);
+  resizeCanvas(allcanvas.back);
+}
+
+function pointWithinDistanceToSegment(x, y, x1, y1, x2, y2, d) {
+  var A = x - x1;
+  var B = y - y1;
+  var C = x2 - x1;
+  var D = y2 - y1;
+
+  var dot = A * C + B * D;
+  var len_sq = C * C + D * D;
+  var dx, dy;
+  if (len_sq == 0) {
+    // start and end of the segment coincide
+    dx = x - x1;
+    dy = y - y1;
+  } else {
+    var param = dot / len_sq;
+    var xx, yy;
+    if (param < 0) {
+      xx = x1;
+      yy = y1;
+    } else if (param > 1) {
+      xx = x2;
+      yy = y2;
+    } else {
+      xx = x1 + param * C;
+      yy = y1 + param * D;
+    }
+    dx = x - xx;
+    dy = y - yy;
+  }
+  return dx * dx + dy * dy <= d * d;
+}
+
+function modulo(n, mod) {
+  return ((n % mod) + mod) % mod;
+}
+
+function pointWithinDistanceToArc(x, y, xc, yc, radius, startangle, endangle, d) {
+  var dx = x - xc;
+  var dy = y - yc;
+  var r_sq = dx * dx + dy * dy;
+  var rmin = Math.max(0, radius - d);
+  var rmax = radius + d;
+
+  if (r_sq < rmin * rmin || r_sq > rmax * rmax)
+    return false;
+
+  var angle1 = modulo(deg2rad(startangle), 2 * Math.PI);
+  var dx1 = xc + radius * Math.cos(angle1) - x;
+  var dy1 = yc + radius * Math.sin(angle1) - y;
+  if (dx1 * dx1 + dy1 * dy1 <= d * d)
+    return true;
+
+  var angle2 = modulo(deg2rad(endangle), 2 * Math.PI);
+  var dx2 = xc + radius * Math.cos(angle2) - x;
+  var dy2 = yc + radius * Math.sin(angle2) - y;
+  if (dx2 * dx2 + dy2 * dy2 <= d * d)
+    return true;
+
+  var angle = modulo(Math.atan2(dy, dx), 2 * Math.PI);
+  if (angle1 > angle2)
+    return (angle >= angle2 || angle <= angle1);
+  else
+    return (angle >= angle1 && angle <= angle2);
+}
+
+function pointWithinPad(x, y, pad) {
+  var v = [x - pad.pos[0], y - pad.pos[1]];
+  v = rotateVector(v, -pad.angle);
+  if (pad.offset) {
+    v[0] -= pad.offset[0];
+    v[1] -= pad.offset[1];
+  }
+  return emptyContext2d.isPointInPath(getCachedPadPath(pad), ...v);
+}
+
+function netHitScan(layer, x, y) {
+  // Check track segments
+  if (settings.renderTracks && pcbdata.tracks) {
+    for (var track of pcbdata.tracks[layer]) {
+      if ('radius' in track) {
+        if (pointWithinDistanceToArc(x, y, ...track.center, track.radius, track.startangle, track.endangle, track.width / 2)) {
+          return track.net;
+        }
+      } else {
+        if (pointWithinDistanceToSegment(x, y, ...track.start, ...track.end, track.width / 2)) {
+          return track.net;
+        }
+      }
+    }
+  }
+  // Check pads
+  if (settings.renderPads) {
+    for (var footprint of pcbdata.footprints) {
+      for (var pad of footprint.pads) {
+        if (pad.layers.includes(layer) && pointWithinPad(x, y, pad)) {
+          return pad.net;
+        }
+      }
+    }
+  }
+  return null;
+}
+
+function pointWithinFootprintBbox(x, y, bbox) {
+  var v = [x - bbox.pos[0], y - bbox.pos[1]];
+  v = rotateVector(v, bbox.angle);
+  return bbox.relpos[0] <= v[0] && v[0] <= bbox.relpos[0] + bbox.size[0] &&
+    bbox.relpos[1] <= v[1] && v[1] <= bbox.relpos[1] + bbox.size[1];
+}
+
+function bboxHitScan(layer, x, y) {
+  var result = [];
+  for (var i = 0; i < pcbdata.footprints.length; i++) {
+    var footprint = pcbdata.footprints[i];
+    if (footprint.layer == layer) {
+      if (pointWithinFootprintBbox(x, y, footprint.bbox)) {
+        result.push(i);
+      }
+    }
+  }
+  return result;
+}
+
+function handlePointerDown(e, layerdict) {
+  if (e.button != 0 && e.button != 1) {
+    return;
+  }
+  e.preventDefault();
+  e.stopPropagation();
+
+  if (!e.hasOwnProperty("offsetX")) {
+    // The polyfill doesn't set this properly
+    e.offsetX = e.pageX - e.currentTarget.offsetLeft;
+    e.offsetY = e.pageY - e.currentTarget.offsetTop;
+  }
+
+  layerdict.pointerStates[e.pointerId] = {
+    distanceTravelled: 0,
+    lastX: e.offsetX,
+    lastY: e.offsetY,
+    downTime: Date.now(),
+  };
+}
+
+function handleMouseClick(e, layerdict) {
+  if (!e.hasOwnProperty("offsetX")) {
+    // The polyfill doesn't set this properly
+    e.offsetX = e.pageX - e.currentTarget.offsetLeft;
+    e.offsetY = e.pageY - e.currentTarget.offsetTop;
+  }
+
+  var x = e.offsetX;
+  var y = e.offsetY;
+  var t = layerdict.transform;
+  if (layerdict.layer == "B") {
+    x = (devicePixelRatio * x / t.zoom - t.panx + t.x) / -t.s;
+  } else {
+    x = (devicePixelRatio * x / t.zoom - t.panx - t.x) / t.s;
+  }
+  y = (devicePixelRatio * y / t.zoom - t.y - t.pany) / t.s;
+  var v = rotateVector([x, y], -settings.boardRotation);
+  if ("nets" in pcbdata) {
+    var net = netHitScan(layerdict.layer, ...v);
+    if (net !== highlightedNet) {
+      netClicked(net);
+    }
+  }
+  if (highlightedNet === null) {
+    var footprints = bboxHitScan(layerdict.layer, ...v);
+    if (footprints.length > 0) {
+      footprintsClicked(footprints);
+    }
+  }
+}
+
+function handlePointerLeave(e, layerdict) {
+  e.preventDefault();
+  e.stopPropagation();
+
+  if (!settings.redrawOnDrag) {
+    redrawCanvas(layerdict);
+  }
+
+  delete layerdict.pointerStates[e.pointerId];
+}
+
+function resetTransform(layerdict) {
+  layerdict.transform.panx = 0;
+  layerdict.transform.pany = 0;
+  layerdict.transform.zoom = 1;
+  redrawCanvas(layerdict);
+}
+
+function handlePointerUp(e, layerdict) {
+  if (!e.hasOwnProperty("offsetX")) {
+    // The polyfill doesn't set this properly
+    e.offsetX = e.pageX - e.currentTarget.offsetLeft;
+    e.offsetY = e.pageY - e.currentTarget.offsetTop;
+  }
+
+  e.preventDefault();
+  e.stopPropagation();
+
+  if (e.button == 2) {
+    // Reset pan and zoom on right click.
+    resetTransform(layerdict);
+    layerdict.anotherPointerTapped = false;
+    return;
+  }
+
+  // We haven't necessarily had a pointermove event since the interaction started, so make sure we update this now
+  var ptr = layerdict.pointerStates[e.pointerId];
+  ptr.distanceTravelled += Math.abs(e.offsetX - ptr.lastX) + Math.abs(e.offsetY - ptr.lastY);
+
+  if (e.button == 0 && ptr.distanceTravelled < 10 && Date.now() - ptr.downTime <= 500) {
+    if (Object.keys(layerdict.pointerStates).length == 1) {
+      if (layerdict.anotherPointerTapped) {
+        // This is the second pointer coming off of a two-finger tap
+        resetTransform(layerdict);
+      } else {
+        // This is just a regular tap
+        handleMouseClick(e, layerdict);
+      }
+      layerdict.anotherPointerTapped = false;
+    } else {
+      // This is the first finger coming off of what could become a two-finger tap
+      layerdict.anotherPointerTapped = true;
+    }
+  } else {
+    if (!settings.redrawOnDrag) {
+      redrawCanvas(layerdict);
+    }
+    layerdict.anotherPointerTapped = false;
+  }
+
+  delete layerdict.pointerStates[e.pointerId];
+}
+
+function handlePointerMove(e, layerdict) {
+  if (!layerdict.pointerStates.hasOwnProperty(e.pointerId)) {
+    return;
+  }
+  e.preventDefault();
+  e.stopPropagation();
+
+  if (!e.hasOwnProperty("offsetX")) {
+    // The polyfill doesn't set this properly
+    e.offsetX = e.pageX - e.currentTarget.offsetLeft;
+    e.offsetY = e.pageY - e.currentTarget.offsetTop;
+  }
+
+  var thisPtr = layerdict.pointerStates[e.pointerId];
+
+  var dx = e.offsetX - thisPtr.lastX;
+  var dy = e.offsetY - thisPtr.lastY;
+
+  // If this number is low on pointer up, we count the action as a click
+  thisPtr.distanceTravelled += Math.abs(dx) + Math.abs(dy);
+
+  if (Object.keys(layerdict.pointerStates).length == 1) {
+    // This is a simple drag
+    layerdict.transform.panx += devicePixelRatio * dx / layerdict.transform.zoom;
+    layerdict.transform.pany += devicePixelRatio * dy / layerdict.transform.zoom;
+  } else if (Object.keys(layerdict.pointerStates).length == 2) {
+    var otherPtr = Object.values(layerdict.pointerStates).filter((ptr) => ptr != thisPtr)[0];
+
+    var oldDist = Math.sqrt(Math.pow(thisPtr.lastX - otherPtr.lastX, 2) + Math.pow(thisPtr.lastY - otherPtr.lastY, 2));
+    var newDist = Math.sqrt(Math.pow(e.offsetX - otherPtr.lastX, 2) + Math.pow(e.offsetY - otherPtr.lastY, 2));
+
+    var scaleFactor = newDist / oldDist;
+
+    if (scaleFactor != NaN) {
+      layerdict.transform.zoom *= scaleFactor;
+
+      var zoomd = (1 - scaleFactor) / layerdict.transform.zoom;
+      layerdict.transform.panx += devicePixelRatio * otherPtr.lastX * zoomd;
+      layerdict.transform.pany += devicePixelRatio * otherPtr.lastY * zoomd;
+    }
+  }
+
+  thisPtr.lastX = e.offsetX;
+  thisPtr.lastY = e.offsetY;
+
+  if (settings.redrawOnDrag) {
+    redrawCanvas(layerdict);
+  }
+}
+
+function handleMouseWheel(e, layerdict) {
+  e.preventDefault();
+  e.stopPropagation();
+  var t = layerdict.transform;
+  var wheeldelta = e.deltaY;
+  if (e.deltaMode == 1) {
+    // FF only, scroll by lines
+    wheeldelta *= 30;
+  } else if (e.deltaMode == 2) {
+    wheeldelta *= 300;
+  }
+  var m = Math.pow(1.1, -wheeldelta / 40);
+  // Limit amount of zoom per tick.
+  if (m > 2) {
+    m = 2;
+  } else if (m < 0.5) {
+    m = 0.5;
+  }
+  t.zoom *= m;
+  var zoomd = (1 - m) / t.zoom;
+  t.panx += devicePixelRatio * e.offsetX * zoomd;
+  t.pany += devicePixelRatio * e.offsetY * zoomd;
+  redrawCanvas(layerdict);
+}
+
+function addMouseHandlers(div, layerdict) {
+  div.addEventListener("pointerdown", function(e) {
+    handlePointerDown(e, layerdict);
+  });
+  div.addEventListener("pointermove", function(e) {
+    handlePointerMove(e, layerdict);
+  });
+  div.addEventListener("pointerup", function(e) {
+    handlePointerUp(e, layerdict);
+  });
+  var pointerleave = function(e) {
+    handlePointerLeave(e, layerdict);
+  }
+  div.addEventListener("pointercancel", pointerleave);
+  div.addEventListener("pointerleave", pointerleave);
+  div.addEventListener("pointerout", pointerleave);
+
+  div.onwheel = function(e) {
+    handleMouseWheel(e, layerdict);
+  }
+  for (var element of [div, layerdict.bg, layerdict.fab, layerdict.silk, layerdict.highlight]) {
+    element.addEventListener("contextmenu", function(e) {
+      e.preventDefault();
+    }, false);
+  }
+}
+
+function setRedrawOnDrag(value) {
+  settings.redrawOnDrag = value;
+  writeStorage("redrawOnDrag", value);
+}
+
+function setBoardRotation(value) {
+  settings.boardRotation = value * 5;
+  writeStorage("boardRotation", settings.boardRotation);
+  document.getElementById("rotationDegree").textContent = settings.boardRotation;
+  resizeAll();
+}
+
+function initRender() {
+  allcanvas = {
+    front: {
+      transform: {
+        x: 0,
+        y: 0,
+        s: 1,
+        panx: 0,
+        pany: 0,
+        zoom: 1,
+      },
+      pointerStates: {},
+      anotherPointerTapped: false,
+      bg: document.getElementById("F_bg"),
+      fab: document.getElementById("F_fab"),
+      silk: document.getElementById("F_slk"),
+      highlight: document.getElementById("F_hl"),
+      layer: "F",
+    },
+    back: {
+      transform: {
+        x: 0,
+        y: 0,
+        s: 1,
+        panx: 0,
+        pany: 0,
+        zoom: 1,
+      },
+      pointerStates: {},
+      anotherPointerTapped: false,
+      bg: document.getElementById("B_bg"),
+      fab: document.getElementById("B_fab"),
+      silk: document.getElementById("B_slk"),
+      highlight: document.getElementById("B_hl"),
+      layer: "B",
+    }
+  };
+  addMouseHandlers(document.getElementById("frontcanvas"), allcanvas.front);
+  addMouseHandlers(document.getElementById("backcanvas"), allcanvas.back);
+}
+
+///////////////////////////////////////////////
+
+///////////////////////////////////////////////
+/*
+ * Table reordering via Drag'n'Drop
+ * Inspired by: https://htmldom.dev/drag-and-drop-table-column
+ */
+
+function setBomHandlers() {
+
+  const bom = document.getElementById('bomtable');
+
+  let dragName;
+  let placeHolderElements;
+  let draggingElement;
+  let forcePopulation;
+  let xOffset;
+  let yOffset;
+  let wasDragged;
+
+  const mouseUpHandler = function(e) {
+    // Delete dragging element
+    draggingElement.remove();
+
+    // Make BOM selectable again
+    bom.style.removeProperty("userSelect");
+
+    // Remove listeners
+    document.removeEventListener('mousemove', mouseMoveHandler);
+    document.removeEventListener('mouseup', mouseUpHandler);
+
+    if (wasDragged) {
+      // Redraw whole BOM
+      populateBomTable();
+    }
+  }
+
+  const mouseMoveHandler = function(e) {
+    // Notice the dragging
+    wasDragged = true;
+
+    // Make the dragged element visible
+    draggingElement.style.removeProperty("display");
+
+    // Set elements position to mouse position
+    draggingElement.style.left = `${e.screenX - xOffset}px`;
+    draggingElement.style.top = `${e.screenY - yOffset}px`;
+
+    // Forced redrawing of BOM table
+    if (forcePopulation) {
+      forcePopulation = false;
+      // Copy array
+      phe = Array.from(placeHolderElements);
+      // populate BOM table again
+      populateBomHeader(dragName, phe);
+      populateBomBody(dragName, phe);
+    }
+
+    // Set up array of hidden columns
+    var hiddenColumns = Array.from(settings.hiddenColumns);
+    // In the ungrouped mode, quantity don't exist
+    if (settings.bommode === "ungrouped")
+      hiddenColumns.push("Quantity");
+    // If no checkbox fields can be found, we consider them hidden
+    if (settings.checkboxes.length == 0)
+      hiddenColumns.push("checkboxes");
+
+    // Get table headers and group them into checkboxes, extrafields and normal headers
+    const bh = document.getElementById("bomhead");
+    headers = Array.from(bh.querySelectorAll("th"))
+    headers.shift() // numCol is not part of the columnOrder
+    headerGroups = []
+    lastCompoundClass = null;
+    for (i = 0; i < settings.columnOrder.length; i++) {
+      cElem = settings.columnOrder[i];
+      if (hiddenColumns.includes(cElem)) {
+        // Hidden columns appear as a dummy element
+        headerGroups.push([]);
+        continue;
+      }
+      elem = headers.filter(e => getColumnOrderName(e) === cElem)[0];
+      if (elem.classList.contains("bom-checkbox")) {
+        if (lastCompoundClass === "bom-checkbox") {
+          cbGroup = headerGroups.pop();
+          cbGroup.push(elem);
+          headerGroups.push(cbGroup);
+        } else {
+          lastCompoundClass = "bom-checkbox";
+          headerGroups.push([elem])
+        }
+      } else {
+        headerGroups.push([elem])
+      }
+    }
+
+    // Copy settings.columnOrder
+    var columns = Array.from(settings.columnOrder)
+
+    // Set up array with indices of hidden columns
+    var hiddenIndices = hiddenColumns.map(e => settings.columnOrder.indexOf(e));
+    var dragIndex = columns.indexOf(dragName);
+    var swapIndex = dragIndex;
+    var swapDone = false;
+
+    // Check if the current dragged element is swapable with the left or right element
+    if (dragIndex > 0) {
+      // Get left headers boundingbox
+      swapIndex = dragIndex - 1;
+      while (hiddenIndices.includes(swapIndex) && swapIndex > 0)
+        swapIndex--;
+      if (!hiddenIndices.includes(swapIndex)) {
+        box = getBoundingClientRectFromMultiple(headerGroups[swapIndex]);
+        if (e.clientX < box.left + window.scrollX + (box.width / 2)) {
+          swapElement = columns[dragIndex];
+          columns.splice(dragIndex, 1);
+          columns.splice(swapIndex, 0, swapElement);
+          forcePopulation = true;
+          swapDone = true;
+        }
+      }
+    }
+    if ((!swapDone) && dragIndex < headerGroups.length - 1) {
+      // Get right headers boundingbox
+      swapIndex = dragIndex + 1;
+      while (hiddenIndices.includes(swapIndex))
+        swapIndex++;
+      if (swapIndex < headerGroups.length) {
+        box = getBoundingClientRectFromMultiple(headerGroups[swapIndex]);
+        if (e.clientX > box.left + window.scrollX + (box.width / 2)) {
+          swapElement = columns[dragIndex];
+          columns.splice(dragIndex, 1);
+          columns.splice(swapIndex, 0, swapElement);
+          forcePopulation = true;
+          swapDone = true;
+        }
+      }
+    }
+
+    // Write back change to storage
+    if (swapDone) {
+      settings.columnOrder = columns
+      writeStorage("columnOrder", JSON.stringify(columns));
+    }
+
+  }
+
+  const mouseDownHandler = function(e) {
+    var target = e.target;
+    if (target.tagName.toLowerCase() != "td")
+      target = target.parentElement;
+
+    // Used to check if a dragging has ever happened
+    wasDragged = false;
+
+    // Create new element which will be displayed as the dragged column
+    draggingElement = document.createElement("div")
+    draggingElement.classList.add("dragging");
+    draggingElement.style.display = "none";
+    draggingElement.style.position = "absolute";
+    draggingElement.style.overflow = "hidden";
+
+    // Get bomhead and bombody elements
+    const bh = document.getElementById("bomhead");
+    const bb = document.getElementById("bombody");
+
+    // Get all compound headers for the current column
+    var compoundHeaders;
+    if (target.classList.contains("bom-checkbox")) {
+      compoundHeaders = Array.from(bh.querySelectorAll("th.bom-checkbox"));
+    } else {
+      compoundHeaders = [target];
+    }
+
+    // Create new table which will display the column
+    var newTable = document.createElement("table");
+    newTable.classList.add("bom");
+    newTable.style.background = "white";
+    draggingElement.append(newTable);
+
+    // Create new header element
+    var newHeader = document.createElement("thead");
+    newTable.append(newHeader);
+
+    // Set up array for storing all placeholder elements
+    placeHolderElements = [];
+
+    // Add all compound headers to the new thead element and placeholders
+    compoundHeaders.forEach(function(h) {
+      clone = cloneElementWithDimensions(h);
+      newHeader.append(clone);
+      placeHolderElements.push(clone);
+    });
+
+    // Create new body element
+    var newBody = document.createElement("tbody");
+    newTable.append(newBody);
+
+    // Get indices for compound headers
+    var idxs = compoundHeaders.map(e => getBomTableHeaderIndex(e));
+
+    // For each row in the BOM body...
+    var rows = bb.querySelectorAll("tr");
+    rows.forEach(function(row) {
+      // ..get the cells for the compound column
+      const tds = row.querySelectorAll("td");
+      var copytds = idxs.map(i => tds[i]);
+      // Add them to the new element and the placeholders
+      var newRow = document.createElement("tr");
+      copytds.forEach(function(td) {
+        clone = cloneElementWithDimensions(td);
+        newRow.append(clone);
+        placeHolderElements.push(clone);
+      });
+      newBody.append(newRow);
+    });
+
+    // Compute width for compound header
+    var width = compoundHeaders.reduce((acc, x) => acc + x.clientWidth, 0);
+    draggingElement.style.width = `${width}px`;
+
+    // Insert the new dragging element and disable selection on BOM
+    bom.insertBefore(draggingElement, null);
+    bom.style.userSelect = "none";
+
+    // Determine the mouse position offset
+    xOffset = e.screenX - compoundHeaders.reduce((acc, x) => Math.min(acc, x.offsetLeft), compoundHeaders[0].offsetLeft);
+    yOffset = e.screenY - compoundHeaders[0].offsetTop;
+
+    // Get name for the column in settings.columnOrder
+    dragName = getColumnOrderName(target);
+
+    // Change text and class for placeholder elements
+    placeHolderElements = placeHolderElements.map(function(e) {
+      newElem = cloneElementWithDimensions(e);
+      newElem.textContent = "";
+      newElem.classList.add("placeholder");
+      return newElem;
+    });
+
+    // On next mouse move, the whole BOM needs to be redrawn to show the placeholders
+    forcePopulation = true;
+
+    // Add listeners for move and up on mouse
+    document.addEventListener('mousemove', mouseMoveHandler);
+    document.addEventListener('mouseup', mouseUpHandler);
+  }
+
+  // In netlist mode, there is nothing to reorder
+  if (settings.bommode === "netlist")
+    return;
+
+  // Add mouseDownHandler to every column except the numCol
+  bom.querySelectorAll("th")
+    .forEach(function(head) {
+      if (!head.classList.contains("numCol")) {
+        head.onmousedown = mouseDownHandler;
+      }
+    });
+
+}
+
+function getBoundingClientRectFromMultiple(elements) {
+  var elems = Array.from(elements);
+
+  if (elems.length == 0)
+    return null;
+
+  var box = elems.shift()
+    .getBoundingClientRect();
+
+  elems.forEach(function(elem) {
+    var elembox = elem.getBoundingClientRect();
+    box.left = Math.min(elembox.left, box.left);
+    box.top = Math.min(elembox.top, box.top);
+    box.width += elembox.width;
+    box.height = Math.max(elembox.height, box.height);
+  });
+
+  return box;
+}
+
+function cloneElementWithDimensions(elem) {
+  var newElem = elem.cloneNode(true);
+  newElem.style.height = window.getComputedStyle(elem).height;
+  newElem.style.width = window.getComputedStyle(elem).width;
+  return newElem;
+}
+
+function getBomTableHeaderIndex(elem) {
+  const bh = document.getElementById('bomhead');
+  const ths = Array.from(bh.querySelectorAll("th"));
+  return ths.indexOf(elem);
+}
+
+function getColumnOrderName(elem) {
+  var cname = elem.getAttribute("col_name");
+  if (cname === "bom-checkbox")
+    return "checkboxes";
+  else
+    return cname;
+}
+
+function resizableGrid(tablehead) {
+  var cols = tablehead.firstElementChild.children;
+  var rowWidth = tablehead.offsetWidth;
+
+  for (var i = 1; i < cols.length; i++) {
+    if (cols[i].classList.contains("bom-checkbox"))
+      continue;
+    cols[i].style.width = ((cols[i].clientWidth - paddingDiff(cols[i])) * 100 / rowWidth) + '%';
+  }
+
+  for (var i = 1; i < cols.length - 1; i++) {
+    var div = document.createElement('div');
+    div.className = "column-width-handle";
+    cols[i].appendChild(div);
+    setListeners(div);
+  }
+
+  function setListeners(div) {
+    var startX, curCol, nxtCol, curColWidth, nxtColWidth, rowWidth;
+
+    div.addEventListener('mousedown', function(e) {
+      e.preventDefault();
+      e.stopPropagation();
+
+      curCol = e.target.parentElement;
+      nxtCol = curCol.nextElementSibling;
+      startX = e.pageX;
+
+      var padding = paddingDiff(curCol);
+
+      rowWidth = curCol.parentElement.offsetWidth;
+      curColWidth = curCol.clientWidth - padding;
+      nxtColWidth = nxtCol.clientWidth - padding;
+    });
+
+    document.addEventListener('mousemove', function(e) {
+      if (startX) {
+        var diffX = e.pageX - startX;
+        diffX = -Math.min(-diffX, curColWidth - 20);
+        diffX = Math.min(diffX, nxtColWidth - 20);
+
+        curCol.style.width = ((curColWidth + diffX) * 100 / rowWidth) + '%';
+        nxtCol.style.width = ((nxtColWidth - diffX) * 100 / rowWidth) + '%';
+        console.log(`${curColWidth + nxtColWidth} ${(curColWidth + diffX) * 100 / rowWidth + (nxtColWidth - diffX) * 100 / rowWidth}`);
+      }
+    });
+
+    document.addEventListener('mouseup', function(e) {
+      curCol = undefined;
+      nxtCol = undefined;
+      startX = undefined;
+      nxtColWidth = undefined;
+      curColWidth = undefined
+    });
+  }
+
+  function paddingDiff(col) {
+
+    if (getStyleVal(col, 'box-sizing') == 'border-box') {
+      return 0;
+    }
+
+    var padLeft = getStyleVal(col, 'padding-left');
+    var padRight = getStyleVal(col, 'padding-right');
+    return (parseInt(padLeft) + parseInt(padRight));
+
+  }
+
+  function getStyleVal(elm, css) {
+    return (window.getComputedStyle(elm, null).getPropertyValue(css))
+  }
+}
+
+///////////////////////////////////////////////
+
+///////////////////////////////////////////////
+/* DOM manipulation and misc code */
+
+var bomsplit;
+var canvassplit;
+var initDone = false;
+var bomSortFunction = null;
+var currentSortColumn = null;
+var currentSortOrder = null;
+var currentHighlightedRowId;
+var highlightHandlers = [];
+var footprintIndexToHandler = {};
+var netsToHandler = {};
+var markedFootprints = new Set();
+var highlightedFootprints = [];
+var highlightedNet = null;
+var lastClicked;
+
+function dbg(html) {
+  dbgdiv.innerHTML = html;
+}
+
+function redrawIfInitDone() {
+  if (initDone) {
+    redrawCanvas(allcanvas.front);
+    redrawCanvas(allcanvas.back);
+  }
+}
+
+function padsVisible(value) {
+  writeStorage("padsVisible", value);
+  settings.renderPads = value;
+  redrawIfInitDone();
+}
+
+function referencesVisible(value) {
+  writeStorage("referencesVisible", value);
+  settings.renderReferences = value;
+  redrawIfInitDone();
+}
+
+function valuesVisible(value) {
+  writeStorage("valuesVisible", value);
+  settings.renderValues = value;
+  redrawIfInitDone();
+}
+
+function tracksVisible(value) {
+  writeStorage("tracksVisible", value);
+  settings.renderTracks = value;
+  redrawIfInitDone();
+}
+
+function zonesVisible(value) {
+  writeStorage("zonesVisible", value);
+  settings.renderZones = value;
+  redrawIfInitDone();
+}
+
+function dnpOutline(value) {
+  writeStorage("dnpOutline", value);
+  settings.renderDnpOutline = value;
+  redrawIfInitDone();
+}
+
+function setDarkMode(value) {
+  if (value) {
+    topmostdiv.classList.add("dark");
+  } else {
+    topmostdiv.classList.remove("dark");
+  }
+  writeStorage("darkmode", value);
+  settings.darkMode = value;
+  redrawIfInitDone();
+}
+
+function setShowBOMColumn(field, value) {
+  if (field === "references") {
+    var rl = document.getElementById("reflookup");
+    rl.disabled = !value;
+    if (!value) {
+      rl.value = "";
+      updateRefLookup("");
+    }
+  }
+
+  var n = settings.hiddenColumns.indexOf(field);
+  if (value) {
+    if (n != -1) {
+      settings.hiddenColumns.splice(n, 1);
+    }
+  } else {
+    if (n == -1) {
+      settings.hiddenColumns.push(field);
+    }
+  }
+
+  writeStorage("hiddenColumns", JSON.stringify(settings.hiddenColumns));
+
+  if (initDone) {
+    populateBomTable();
+  }
+
+  redrawIfInitDone();
+}
+
+
+function setFullscreen(value) {
+  if (value) {
+    document.documentElement.requestFullscreen();
+  } else {
+    document.exitFullscreen();
+  }
+}
+
+function fabricationVisible(value) {
+  writeStorage("fabricationVisible", value);
+  settings.renderFabrication = value;
+  redrawIfInitDone();
+}
+
+function silkscreenVisible(value) {
+  writeStorage("silkscreenVisible", value);
+  settings.renderSilkscreen = value;
+  redrawIfInitDone();
+}
+
+function setHighlightPin1(value) {
+  writeStorage("highlightpin1", value);
+  settings.highlightpin1 = value;
+  redrawIfInitDone();
+}
+
+function getStoredCheckboxRefs(checkbox) {
+  function convert(ref) {
+    var intref = parseInt(ref);
+    if (isNaN(intref)) {
+      for (var i = 0; i < pcbdata.footprints.length; i++) {
+        if (pcbdata.footprints[i].ref == ref) {
+          return i;
+        }
+      }
+      return -1;
+    } else {
+      return intref;
+    }
+  }
+  if (!(checkbox in settings.checkboxStoredRefs)) {
+    var val = readStorage("checkbox_" + checkbox);
+    settings.checkboxStoredRefs[checkbox] = val ? val : "";
+  }
+  if (!settings.checkboxStoredRefs[checkbox]) {
+    return new Set();
+  } else {
+    return new Set(settings.checkboxStoredRefs[checkbox].split(",").map(r => convert(r)).filter(a => a >= 0));
+  }
+}
+
+function getCheckboxState(checkbox, references) {
+  var storedRefsSet = getStoredCheckboxRefs(checkbox);
+  var currentRefsSet = new Set(references.map(r => r[1]));
+  // Get difference of current - stored
+  var difference = new Set(currentRefsSet);
+  for (ref of storedRefsSet) {
+    difference.delete(ref);
+  }
+  if (difference.size == 0) {
+    // All the current refs are stored
+    return "checked";
+  } else if (difference.size == currentRefsSet.size) {
+    // None of the current refs are stored
+    return "unchecked";
+  } else {
+    // Some of the refs are stored
+    return "indeterminate";
+  }
+}
+
+function setBomCheckboxState(checkbox, element, references) {
+  var state = getCheckboxState(checkbox, references);
+  element.checked = (state == "checked");
+  element.indeterminate = (state == "indeterminate");
+}
+
+function createCheckboxChangeHandler(checkbox, references, row) {
+  return function () {
+    refsSet = getStoredCheckboxRefs(checkbox);
+    var markWhenChecked = settings.markWhenChecked == checkbox;
+    eventArgs = {
+      checkbox: checkbox,
+      refs: references,
+    }
+    if (this.checked) {
+      // checkbox ticked
+      for (var ref of references) {
+        refsSet.add(ref[1]);
+      }
+      if (markWhenChecked) {
+        row.classList.add("checked");
+        for (var ref of references) {
+          markedFootprints.add(ref[1]);
+        }
+        drawHighlights();
+      }
+      eventArgs.state = 'checked';
+    } else {
+      // checkbox unticked
+      for (var ref of references) {
+        refsSet.delete(ref[1]);
+      }
+      if (markWhenChecked) {
+        row.classList.remove("checked");
+        for (var ref of references) {
+          markedFootprints.delete(ref[1]);
+        }
+        drawHighlights();
+      }
+      eventArgs.state = 'unchecked';
+    }
+    settings.checkboxStoredRefs[checkbox] = [...refsSet].join(",");
+    writeStorage("checkbox_" + checkbox, settings.checkboxStoredRefs[checkbox]);
+    updateCheckboxStats(checkbox);
+    EventHandler.emitEvent(IBOM_EVENT_TYPES.CHECKBOX_CHANGE_EVENT, eventArgs);
+  }
+}
+
+function clearHighlightedFootprints() {
+  if (currentHighlightedRowId) {
+    document.getElementById(currentHighlightedRowId).classList.remove("highlighted");
+    currentHighlightedRowId = null;
+    highlightedFootprints = [];
+    highlightedNet = null;
+  }
+}
+
+function createRowHighlightHandler(rowid, refs, net) {
+  return function () {
+    if (currentHighlightedRowId) {
+      if (currentHighlightedRowId == rowid) {
+        return;
+      }
+      document.getElementById(currentHighlightedRowId).classList.remove("highlighted");
+    }
+    document.getElementById(rowid).classList.add("highlighted");
+    currentHighlightedRowId = rowid;
+    highlightedFootprints = refs ? refs.map(r => r[1]) : [];
+    highlightedNet = net;
+    drawHighlights();
+    EventHandler.emitEvent(
+      IBOM_EVENT_TYPES.HIGHLIGHT_EVENT, {
+      rowid: rowid,
+      refs: refs,
+      net: net
+    });
+  }
+}
+
+function entryMatches(entry) {
+  if (settings.bommode == "netlist") {
+    // entry is just a net name
+    return entry.toLowerCase().indexOf(filter) >= 0;
+  }
+  // check refs
+  if (!settings.hiddenColumns.includes("references")) {
+    for (var ref of entry) {
+      if (ref[0].toLowerCase().indexOf(filter) >= 0) {
+        return true;
+      }
+    }
+  }
+  // check fields
+  for (var i in config.fields) {
+    var f = config.fields[i];
+    if (!settings.hiddenColumns.includes(f)) {
+      for (var ref of entry) {
+        if (pcbdata.bom.fields[ref[1]][i].toLowerCase().indexOf(filter) >= 0) {
+          return true;
+        }
+      }
+    }
+  }
+  return false;
+}
+
+function findRefInEntry(entry) {
+  return entry.filter(r => r[0].toLowerCase() == reflookup);
+}
+
+function highlightFilter(s) {
+  if (!filter) {
+    return s;
+  }
+  var parts = s.toLowerCase().split(filter);
+  if (parts.length == 1) {
+    return s;
+  }
+  var r = "";
+  var pos = 0;
+  for (var i in parts) {
+    if (i > 0) {
+      r += '<mark class="highlight">' +
+        s.substring(pos, pos + filter.length) +
+        '</mark>';
+      pos += filter.length;
+    }
+    r += s.substring(pos, pos + parts[i].length);
+    pos += parts[i].length;
+  }
+  return r;
+}
+
+function checkboxSetUnsetAllHandler(checkboxname) {
+  return function () {
+    var checkboxnum = 0;
+    while (checkboxnum < settings.checkboxes.length &&
+      settings.checkboxes[checkboxnum].toLowerCase() != checkboxname.toLowerCase()) {
+      checkboxnum++;
+    }
+    if (checkboxnum >= settings.checkboxes.length) {
+      return;
+    }
+    var allset = true;
+    var checkbox;
+    var row;
+    for (row of bombody.childNodes) {
+      checkbox = row.childNodes[checkboxnum + 1].childNodes[0];
+      if (!checkbox.checked || checkbox.indeterminate) {
+        allset = false;
+        break;
+      }
+    }
+    for (row of bombody.childNodes) {
+      checkbox = row.childNodes[checkboxnum + 1].childNodes[0];
+      checkbox.checked = !allset;
+      checkbox.indeterminate = false;
+      checkbox.onchange();
+    }
+  }
+}
+
+function createColumnHeader(name, cls, comparator, is_checkbox = false) {
+  var th = document.createElement("TH");
+  th.innerHTML = name;
+  th.classList.add(cls);
+  if (is_checkbox)
+    th.setAttribute("col_name", "bom-checkbox");
+  else
+    th.setAttribute("col_name", name);
+  var span = document.createElement("SPAN");
+  span.classList.add("sortmark");
+  span.classList.add("none");
+  th.appendChild(span);
+  var spacer = document.createElement("div");
+  spacer.className = "column-spacer";
+  th.appendChild(spacer);
+  spacer.onclick = function () {
+    if (currentSortColumn && th !== currentSortColumn) {
+      // Currently sorted by another column
+      currentSortColumn.childNodes[1].classList.remove(currentSortOrder);
+      currentSortColumn.childNodes[1].classList.add("none");
+      currentSortColumn = null;
+      currentSortOrder = null;
+    }
+    if (currentSortColumn && th === currentSortColumn) {
+      // Already sorted by this column
+      if (currentSortOrder == "asc") {
+        // Sort by this column, descending order
+        bomSortFunction = function (a, b) {
+          return -comparator(a, b);
+        }
+        currentSortColumn.childNodes[1].classList.remove("asc");
+        currentSortColumn.childNodes[1].classList.add("desc");
+        currentSortOrder = "desc";
+      } else {
+        // Unsort
+        bomSortFunction = null;
+        currentSortColumn.childNodes[1].classList.remove("desc");
+        currentSortColumn.childNodes[1].classList.add("none");
+        currentSortColumn = null;
+        currentSortOrder = null;
+      }
+    } else {
+      // Sort by this column, ascending order
+      bomSortFunction = comparator;
+      currentSortColumn = th;
+      currentSortColumn.childNodes[1].classList.remove("none");
+      currentSortColumn.childNodes[1].classList.add("asc");
+      currentSortOrder = "asc";
+    }
+    populateBomBody();
+  }
+  if (is_checkbox) {
+    spacer.onclick = fancyDblClickHandler(
+      spacer, spacer.onclick, checkboxSetUnsetAllHandler(name));
+  }
+  return th;
+}
+
+function populateBomHeader(placeHolderColumn = null, placeHolderElements = null) {
+  while (bomhead.firstChild) {
+    bomhead.removeChild(bomhead.firstChild);
+  }
+  var tr = document.createElement("TR");
+  var th = document.createElement("TH");
+  th.classList.add("numCol");
+
+  var vismenu = document.createElement("div");
+  vismenu.id = "vismenu";
+  vismenu.classList.add("menu");
+
+  var visbutton = document.createElement("div");
+  visbutton.classList.add("visbtn");
+  visbutton.classList.add("hideonprint");
+
+  var viscontent = document.createElement("div");
+  viscontent.classList.add("menu-content");
+  viscontent.id = "vismenu-content";
+
+  settings.columnOrder.forEach(column => {
+    if (typeof column !== "string")
+      return;
+
+    // Skip empty columns
+    if (column === "checkboxes" && settings.checkboxes.length == 0)
+      return;
+    else if (column === "Quantity" && settings.bommode == "ungrouped")
+      return;
+
+    var label = document.createElement("label");
+    label.classList.add("menu-label");
+
+    var input = document.createElement("input");
+    input.classList.add("visibility_checkbox");
+    input.type = "checkbox";
+    input.onchange = function (e) {
+      setShowBOMColumn(column, e.target.checked)
+    };
+    input.checked = !(settings.hiddenColumns.includes(column));
+
+    label.appendChild(input);
+    if (column.length > 0)
+      label.append(column[0].toUpperCase() + column.slice(1));
+
+    viscontent.appendChild(label);
+  });
+
+  viscontent.childNodes[0].classList.add("menu-label-top");
+
+  vismenu.appendChild(visbutton);
+  if (settings.bommode != "netlist") {
+    vismenu.appendChild(viscontent);
+    th.appendChild(vismenu);
+  }
+  tr.appendChild(th);
+
+  var checkboxCompareClosure = function (checkbox) {
+    return (a, b) => {
+      var stateA = getCheckboxState(checkbox, a);
+      var stateB = getCheckboxState(checkbox, b);
+      if (stateA > stateB) return -1;
+      if (stateA < stateB) return 1;
+      return 0;
+    }
+  }
+  var stringFieldCompareClosure = function (fieldIndex) {
+    return (a, b) => {
+      var fa = pcbdata.bom.fields[a[0][1]][fieldIndex];
+      var fb = pcbdata.bom.fields[b[0][1]][fieldIndex];
+      if (fa != fb) return fa > fb ? 1 : -1;
+      else return 0;
+    }
+  }
+  var referenceRegex = /(?<prefix>[^0-9]+)(?<number>[0-9]+)/;
+  var compareRefs = (a, b) => {
+    var ra = referenceRegex.exec(a);
+    var rb = referenceRegex.exec(b);
+    if (ra === null || rb === null) {
+      if (a != b) return a > b ? 1 : -1;
+      return 0;
+    } else {
+      if (ra.groups.prefix != rb.groups.prefix) {
+        return ra.groups.prefix > rb.groups.prefix ? 1 : -1;
+      }
+      if (ra.groups.number != rb.groups.number) {
+        return parseInt(ra.groups.number) > parseInt(rb.groups.number) ? 1 : -1;
+      }
+      return 0;
+    }
+  }
+  if (settings.bommode == "netlist") {
+    th = createColumnHeader("Net name", "bom-netname", (a, b) => {
+      if (a > b) return -1;
+      if (a < b) return 1;
+      return 0;
+    });
+    tr.appendChild(th);
+  } else {
+    // Filter hidden columns
+    var columns = settings.columnOrder.filter(e => !settings.hiddenColumns.includes(e));
+    var valueIndex = config.fields.indexOf("Value");
+    var footprintIndex = config.fields.indexOf("Footprint");
+    columns.forEach((column) => {
+      if (column === placeHolderColumn) {
+        var n = 1;
+        if (column === "checkboxes")
+          n = settings.checkboxes.length;
+        for (i = 0; i < n; i++) {
+          td = placeHolderElements.shift();
+          tr.appendChild(td);
+        }
+        return;
+      } else if (column === "checkboxes") {
+        for (var checkbox of settings.checkboxes) {
+          th = createColumnHeader(
+            checkbox, "bom-checkbox", checkboxCompareClosure(checkbox), true);
+          tr.appendChild(th);
+        }
+      } else if (column === "References") {
+        tr.appendChild(createColumnHeader("References", "references", (a, b) => {
+          var i = 0;
+          while (i < a.length && i < b.length) {
+            if (a[i] != b[i]) return compareRefs(a[i][0], b[i][0]);
+            i++;
+          }
+          return a.length - b.length;
+        }));
+      } else if (column === "Value") {
+        tr.appendChild(createColumnHeader("Value", "value", (a, b) => {
+          var ra = a[0][1], rb = b[0][1];
+          return valueCompare(
+            pcbdata.bom.parsedValues[ra], pcbdata.bom.parsedValues[rb],
+            pcbdata.bom.fields[ra][valueIndex], pcbdata.bom.fields[rb][valueIndex]);
+        }));
+        return;
+      } else if (column === "Footprint") {
+        tr.appendChild(createColumnHeader(
+          "Footprint", "footprint", stringFieldCompareClosure(footprintIndex)));
+      } else if (column === "Quantity" && settings.bommode == "grouped") {
+        tr.appendChild(createColumnHeader("Quantity", "quantity", (a, b) => {
+          return a.length - b.length;
+        }));
+      } else {
+        // Other fields
+        var i = config.fields.indexOf(column);
+        if (i < 0)
+          return;
+        tr.appendChild(createColumnHeader(
+          column, `field${i + 1}`, stringFieldCompareClosure(i)));
+      }
+    });
+  }
+  bomhead.appendChild(tr);
+}
+
+function populateBomBody(placeholderColumn = null, placeHolderElements = null) {
+  while (bom.firstChild) {
+    bom.removeChild(bom.firstChild);
+  }
+  highlightHandlers = [];
+  footprintIndexToHandler = {};
+  netsToHandler = {};
+  currentHighlightedRowId = null;
+  var first = true;
+  if (settings.bommode == "netlist") {
+    bomtable = pcbdata.nets.slice();
+  } else {
+    switch (settings.canvaslayout) {
+      case 'F':
+        bomtable = pcbdata.bom.F.slice();
+        break;
+      case 'FB':
+        bomtable = pcbdata.bom.both.slice();
+        break;
+      case 'B':
+        bomtable = pcbdata.bom.B.slice();
+        break;
+    }
+    if (settings.bommode == "ungrouped") {
+      // expand bom table
+      expandedTable = []
+      for (var bomentry of bomtable) {
+        for (var ref of bomentry) {
+          expandedTable.push([ref]);
+        }
+      }
+      bomtable = expandedTable;
+    }
+  }
+  if (bomSortFunction) {
+    bomtable = bomtable.sort(bomSortFunction);
+  }
+  for (var i in bomtable) {
+    var bomentry = bomtable[i];
+    if (filter && !entryMatches(bomentry)) {
+      continue;
+    }
+    var references = null;
+    var netname = null;
+    var tr = document.createElement("TR");
+    var td = document.createElement("TD");
+    var rownum = +i + 1;
+    tr.id = "bomrow" + rownum;
+    td.textContent = rownum;
+    tr.appendChild(td);
+    if (settings.bommode == "netlist") {
+      netname = bomentry;
+      td = document.createElement("TD");
+      td.innerHTML = highlightFilter(netname ? netname : "&lt;no net&gt;");
+      tr.appendChild(td);
+    } else {
+      if (reflookup) {
+        references = findRefInEntry(bomentry);
+        if (references.length == 0) {
+          continue;
+        }
+      } else {
+        references = bomentry;
+      }
+      // Filter hidden columns
+      var columns = settings.columnOrder.filter(e => !settings.hiddenColumns.includes(e));
+      columns.forEach((column) => {
+        if (column === placeholderColumn) {
+          var n = 1;
+          if (column === "checkboxes")
+            n = settings.checkboxes.length;
+          for (i = 0; i < n; i++) {
+            td = placeHolderElements.shift();
+            tr.appendChild(td);
+          }
+          return;
+        } else if (column === "checkboxes") {
+          for (var checkbox of settings.checkboxes) {
+            if (checkbox) {
+              td = document.createElement("TD");
+              var input = document.createElement("input");
+              input.type = "checkbox";
+              input.onchange = createCheckboxChangeHandler(checkbox, references, tr);
+              setBomCheckboxState(checkbox, input, references);
+              if (input.checked && settings.markWhenChecked == checkbox) {
+                tr.classList.add("checked");
+              }
+              td.appendChild(input);
+              tr.appendChild(td);
+            }
+          }
+        } else if (column === "References") {
+          td = document.createElement("TD");
+          td.innerHTML = highlightFilter(references.map(r => r[0]).join(", "));
+          tr.appendChild(td);
+        } else if (column === "Quantity" && settings.bommode == "grouped") {
+          // Quantity
+          td = document.createElement("TD");
+          td.textContent = references.length;
+          tr.appendChild(td);
+        } else {
+          // All the other fields
+          var field_index = config.fields.indexOf(column)
+          if (field_index < 0)
+            return;
+          var valueSet = new Set();
+          references.map(r => r[1]).forEach((id) => valueSet.add(pcbdata.bom.fields[id][field_index]));
+          td = document.createElement("TD");
+          td.innerHTML = highlightFilter(Array.from(valueSet).join(", "));
+          tr.appendChild(td);
+        }
+      });
+    }
+    bom.appendChild(tr);
+    var handler = createRowHighlightHandler(tr.id, references, netname);
+    tr.onmousemove = handler;
+    highlightHandlers.push({
+      id: tr.id,
+      handler: handler,
+    });
+    if (references !== null) {
+      for (var refIndex of references.map(r => r[1])) {
+        footprintIndexToHandler[refIndex] = handler;
+      }
+    }
+    if (netname !== null) {
+      netsToHandler[netname] = handler;
+    }
+    if ((filter || reflookup) && first) {
+      handler();
+      first = false;
+    }
+  }
+  EventHandler.emitEvent(
+    IBOM_EVENT_TYPES.BOM_BODY_CHANGE_EVENT, {
+    filter: filter,
+    reflookup: reflookup,
+    checkboxes: settings.checkboxes,
+    bommode: settings.bommode,
+  });
+}
+
+function highlightPreviousRow() {
+  if (!currentHighlightedRowId) {
+    highlightHandlers[highlightHandlers.length - 1].handler();
+  } else {
+    if (highlightHandlers.length > 1 &&
+      highlightHandlers[0].id == currentHighlightedRowId) {
+      highlightHandlers[highlightHandlers.length - 1].handler();
+    } else {
+      for (var i = 0; i < highlightHandlers.length - 1; i++) {
+        if (highlightHandlers[i + 1].id == currentHighlightedRowId) {
+          highlightHandlers[i].handler();
+          break;
+        }
+      }
+    }
+  }
+  smoothScrollToRow(currentHighlightedRowId);
+}
+
+function highlightNextRow() {
+  if (!currentHighlightedRowId) {
+    highlightHandlers[0].handler();
+  } else {
+    if (highlightHandlers.length > 1 &&
+      highlightHandlers[highlightHandlers.length - 1].id == currentHighlightedRowId) {
+      highlightHandlers[0].handler();
+    } else {
+      for (var i = 1; i < highlightHandlers.length; i++) {
+        if (highlightHandlers[i - 1].id == currentHighlightedRowId) {
+          highlightHandlers[i].handler();
+          break;
+        }
+      }
+    }
+  }
+  smoothScrollToRow(currentHighlightedRowId);
+}
+
+function populateBomTable() {
+  populateBomHeader();
+  populateBomBody();
+  setBomHandlers();
+  resizableGrid(bomhead);
+}
+
+function footprintsClicked(footprintIndexes) {
+  var lastClickedIndex = footprintIndexes.indexOf(lastClicked);
+  for (var i = 1; i <= footprintIndexes.length; i++) {
+    var refIndex = footprintIndexes[(lastClickedIndex + i) % footprintIndexes.length];
+    if (refIndex in footprintIndexToHandler) {
+      lastClicked = refIndex;
+      footprintIndexToHandler[refIndex]();
+      smoothScrollToRow(currentHighlightedRowId);
+      break;
+    }
+  }
+}
+
+function netClicked(net) {
+  if (net in netsToHandler) {
+    netsToHandler[net]();
+    smoothScrollToRow(currentHighlightedRowId);
+  } else {
+    clearHighlightedFootprints();
+    highlightedNet = net;
+    drawHighlights();
+  }
+}
+
+function updateFilter(input) {
+  filter = input.toLowerCase();
+  populateBomTable();
+}
+
+function updateRefLookup(input) {
+  reflookup = input.toLowerCase();
+  populateBomTable();
+}
+
+function changeCanvasLayout(layout) {
+  document.getElementById("fl-btn").classList.remove("depressed");
+  document.getElementById("fb-btn").classList.remove("depressed");
+  document.getElementById("bl-btn").classList.remove("depressed");
+  switch (layout) {
+    case 'F':
+      document.getElementById("fl-btn").classList.add("depressed");
+      if (settings.bomlayout != "bom-only") {
+        canvassplit.collapse(1);
+      }
+      break;
+    case 'B':
+      document.getElementById("bl-btn").classList.add("depressed");
+      if (settings.bomlayout != "bom-only") {
+        canvassplit.collapse(0);
+      }
+      break;
+    default:
+      document.getElementById("fb-btn").classList.add("depressed");
+      if (settings.bomlayout != "bom-only") {
+        canvassplit.setSizes([50, 50]);
+      }
+  }
+  settings.canvaslayout = layout;
+  writeStorage("canvaslayout", layout);
+  resizeAll();
+  changeBomMode(settings.bommode);
+}
+
+function populateMetadata() {
+  document.getElementById("title").innerHTML = pcbdata.metadata.title;
+  document.getElementById("revision").innerHTML = "Rev: " + pcbdata.metadata.revision;
+  document.getElementById("company").innerHTML = pcbdata.metadata.company;
+  document.getElementById("filedate").innerHTML = pcbdata.metadata.date;
+  if (pcbdata.metadata.title != "") {
+    document.title = pcbdata.metadata.title + " BOM";
+  }
+  // Calculate board stats
+  var fp_f = 0,
+    fp_b = 0,
+    pads_f = 0,
+    pads_b = 0,
+    pads_th = 0;
+  for (var i = 0; i < pcbdata.footprints.length; i++) {
+    if (pcbdata.bom.skipped.includes(i)) continue;
+    var mod = pcbdata.footprints[i];
+    if (mod.layer == "F") {
+      fp_f++;
+    } else {
+      fp_b++;
+    }
+    for (var pad of mod.pads) {
+      if (pad.type == "th") {
+        pads_th++;
+      } else {
+        if (pad.layers.includes("F")) {
+          pads_f++;
+        }
+        if (pad.layers.includes("B")) {
+          pads_b++;
+        }
+      }
+    }
+  }
+  document.getElementById("stats-components-front").innerHTML = fp_f;
+  document.getElementById("stats-components-back").innerHTML = fp_b;
+  document.getElementById("stats-components-total").innerHTML = fp_f + fp_b;
+  document.getElementById("stats-groups-front").innerHTML = pcbdata.bom.F.length;
+  document.getElementById("stats-groups-back").innerHTML = pcbdata.bom.B.length;
+  document.getElementById("stats-groups-total").innerHTML = pcbdata.bom.both.length;
+  document.getElementById("stats-smd-pads-front").innerHTML = pads_f;
+  document.getElementById("stats-smd-pads-back").innerHTML = pads_b;
+  document.getElementById("stats-smd-pads-total").innerHTML = pads_f + pads_b;
+  document.getElementById("stats-th-pads").innerHTML = pads_th;
+  // Update version string
+  document.getElementById("github-link").innerHTML = "InteractiveHtmlBom&nbsp;" +
+    /^v\d+\.\d+/.exec(pcbdata.ibom_version)[0];
+}
+
+function changeBomLayout(layout) {
+  document.getElementById("bom-btn").classList.remove("depressed");
+  document.getElementById("lr-btn").classList.remove("depressed");
+  document.getElementById("tb-btn").classList.remove("depressed");
+  switch (layout) {
+    case 'bom-only':
+      document.getElementById("bom-btn").classList.add("depressed");
+      if (bomsplit) {
+        bomsplit.destroy();
+        bomsplit = null;
+        canvassplit.destroy();
+        canvassplit = null;
+      }
+      document.getElementById("frontcanvas").style.display = "none";
+      document.getElementById("backcanvas").style.display = "none";
+      document.getElementById("bot").style.height = "";
+      break;
+    case 'top-bottom':
+      document.getElementById("tb-btn").classList.add("depressed");
+      document.getElementById("frontcanvas").style.display = "";
+      document.getElementById("backcanvas").style.display = "";
+      document.getElementById("bot").style.height = "calc(100% - 80px)";
+      document.getElementById("bomdiv").classList.remove("split-horizontal");
+      document.getElementById("canvasdiv").classList.remove("split-horizontal");
+      document.getElementById("frontcanvas").classList.add("split-horizontal");
+      document.getElementById("backcanvas").classList.add("split-horizontal");
+      if (bomsplit) {
+        bomsplit.destroy();
+        bomsplit = null;
+        canvassplit.destroy();
+        canvassplit = null;
+      }
+      bomsplit = Split(['#bomdiv', '#canvasdiv'], {
+        sizes: [50, 50],
+        onDragEnd: resizeAll,
+        direction: "vertical",
+        gutterSize: 5
+      });
+      canvassplit = Split(['#frontcanvas', '#backcanvas'], {
+        sizes: [50, 50],
+        gutterSize: 5,
+        onDragEnd: resizeAll
+      });
+      break;
+    case 'left-right':
+      document.getElementById("lr-btn").classList.add("depressed");
+      document.getElementById("frontcanvas").style.display = "";
+      document.getElementById("backcanvas").style.display = "";
+      document.getElementById("bot").style.height = "calc(100% - 80px)";
+      document.getElementById("bomdiv").classList.add("split-horizontal");
+      document.getElementById("canvasdiv").classList.add("split-horizontal");
+      document.getElementById("frontcanvas").classList.remove("split-horizontal");
+      document.getElementById("backcanvas").classList.remove("split-horizontal");
+      if (bomsplit) {
+        bomsplit.destroy();
+        bomsplit = null;
+        canvassplit.destroy();
+        canvassplit = null;
+      }
+      bomsplit = Split(['#bomdiv', '#canvasdiv'], {
+        sizes: [50, 50],
+        onDragEnd: resizeAll,
+        gutterSize: 5
+      });
+      canvassplit = Split(['#frontcanvas', '#backcanvas'], {
+        sizes: [50, 50],
+        gutterSize: 5,
+        direction: "vertical",
+        onDragEnd: resizeAll
+      });
+  }
+  settings.bomlayout = layout;
+  writeStorage("bomlayout", layout);
+  changeCanvasLayout(settings.canvaslayout);
+}
+
+function changeBomMode(mode) {
+  document.getElementById("bom-grouped-btn").classList.remove("depressed");
+  document.getElementById("bom-ungrouped-btn").classList.remove("depressed");
+  document.getElementById("bom-netlist-btn").classList.remove("depressed");
+  var chkbxs = document.getElementsByClassName("visibility_checkbox");
+
+  switch (mode) {
+    case 'grouped':
+      document.getElementById("bom-grouped-btn").classList.add("depressed");
+      for (var i = 0; i < chkbxs.length; i++) {
+        chkbxs[i].disabled = false;
+      }
+      break;
+    case 'ungrouped':
+      document.getElementById("bom-ungrouped-btn").classList.add("depressed");
+      for (var i = 0; i < chkbxs.length; i++) {
+        chkbxs[i].disabled = false;
+      }
+      break;
+    case 'netlist':
+      document.getElementById("bom-netlist-btn").classList.add("depressed");
+      for (var i = 0; i < chkbxs.length; i++) {
+        chkbxs[i].disabled = true;
+      }
+  }
+
+  writeStorage("bommode", mode);
+  if (mode != settings.bommode) {
+    settings.bommode = mode;
+    bomSortFunction = null;
+    currentSortColumn = null;
+    currentSortOrder = null;
+    clearHighlightedFootprints();
+  }
+  populateBomTable();
+}
+
+function focusFilterField() {
+  focusInputField(document.getElementById("filter"));
+}
+
+function focusRefLookupField() {
+  focusInputField(document.getElementById("reflookup"));
+}
+
+function toggleBomCheckbox(bomrowid, checkboxnum) {
+  if (!bomrowid || checkboxnum > settings.checkboxes.length) {
+    return;
+  }
+  var bomrow = document.getElementById(bomrowid);
+  var checkbox = bomrow.childNodes[checkboxnum].childNodes[0];
+  checkbox.checked = !checkbox.checked;
+  checkbox.indeterminate = false;
+  checkbox.onchange();
+}
+
+function checkBomCheckbox(bomrowid, checkboxname) {
+  var checkboxnum = 0;
+  while (checkboxnum < settings.checkboxes.length &&
+    settings.checkboxes[checkboxnum].toLowerCase() != checkboxname.toLowerCase()) {
+    checkboxnum++;
+  }
+  if (!bomrowid || checkboxnum >= settings.checkboxes.length) {
+    return;
+  }
+  var bomrow = document.getElementById(bomrowid);
+  var checkbox = bomrow.childNodes[checkboxnum + 1].childNodes[0];
+  checkbox.checked = true;
+  checkbox.indeterminate = false;
+  checkbox.onchange();
+}
+
+function setBomCheckboxes(value) {
+  writeStorage("bomCheckboxes", value);
+  settings.checkboxes = value.split(",").map((e) => e.trim()).filter((e) => e);
+  prepCheckboxes();
+  populateMarkWhenCheckedOptions();
+  setMarkWhenChecked(settings.markWhenChecked);
+}
+
+function setMarkWhenChecked(value) {
+  writeStorage("markWhenChecked", value);
+  settings.markWhenChecked = value;
+  markedFootprints.clear();
+  for (var ref of (value ? getStoredCheckboxRefs(value) : [])) {
+    markedFootprints.add(ref);
+  }
+  populateBomTable();
+  drawHighlights();
+}
+
+function prepCheckboxes() {
+  var table = document.getElementById("checkbox-stats");
+  while (table.childElementCount > 1) {
+    table.removeChild(table.lastChild);
+  }
+  if (settings.checkboxes.length) {
+    table.style.display = "";
+  } else {
+    table.style.display = "none";
+  }
+  for (var checkbox of settings.checkboxes) {
+    var tr = document.createElement("TR");
+    var td = document.createElement("TD");
+    td.innerHTML = checkbox;
+    tr.appendChild(td);
+    td = document.createElement("TD");
+    td.id = "checkbox-stats-" + checkbox;
+    var progressbar = document.createElement("div");
+    progressbar.classList.add("bar");
+    td.appendChild(progressbar);
+    var text = document.createElement("div");
+    text.classList.add("text");
+    td.appendChild(text);
+    tr.appendChild(td);
+    table.appendChild(tr);
+    updateCheckboxStats(checkbox);
+  }
+}
+
+function populateMarkWhenCheckedOptions() {
+  var container = document.getElementById("markWhenCheckedContainer");
+
+  if (settings.checkboxes.length == 0) {
+    container.parentElement.style.display = "none";
+    return;
+  }
+
+  container.innerHTML = '';
+  container.parentElement.style.display = "inline-block";
+
+  function createOption(name, displayName) {
+    var id = "markWhenChecked-" + name;
+
+    var div = document.createElement("div");
+    div.classList.add("radio-container");
+
+    var input = document.createElement("input");
+    input.type = "radio";
+    input.name = "markWhenChecked";
+    input.value = name;
+    input.id = id;
+    input.onchange = () => setMarkWhenChecked(name);
+    div.appendChild(input);
+
+    // Preserve the selected element when the checkboxes change
+    if (name == settings.markWhenChecked) {
+      input.checked = true;
+    }
+
+    var label = document.createElement("label");
+    label.innerHTML = displayName;
+    label.htmlFor = id;
+    div.appendChild(label);
+
+    container.appendChild(div);
+  }
+  createOption("", "None");
+  for (var checkbox of settings.checkboxes) {
+    createOption(checkbox, checkbox);
+  }
+}
+
+function updateCheckboxStats(checkbox) {
+  var checked = getStoredCheckboxRefs(checkbox).size;
+  var total = pcbdata.footprints.length - pcbdata.bom.skipped.length;
+  var percent = checked * 100.0 / total;
+  var td = document.getElementById("checkbox-stats-" + checkbox);
+  td.firstChild.style.width = percent + "%";
+  td.lastChild.innerHTML = checked + "/" + total + " (" + Math.round(percent) + "%)";
+}
+
+document.onkeydown = function (e) {
+  switch (e.key) {
+    case "n":
+      if (document.activeElement.type == "text") {
+        return;
+      }
+      if (currentHighlightedRowId !== null) {
+        checkBomCheckbox(currentHighlightedRowId, "placed");
+        highlightNextRow();
+        e.preventDefault();
+      }
+      break;
+    case "ArrowUp":
+      highlightPreviousRow();
+      e.preventDefault();
+      break;
+    case "ArrowDown":
+      highlightNextRow();
+      e.preventDefault();
+      break;
+    default:
+      break;
+  }
+  if (e.altKey) {
+    switch (e.key) {
+      case "f":
+        focusFilterField();
+        e.preventDefault();
+        break;
+      case "r":
+        focusRefLookupField();
+        e.preventDefault();
+        break;
+      case "z":
+        changeBomLayout("bom-only");
+        e.preventDefault();
+        break;
+      case "x":
+        changeBomLayout("left-right");
+        e.preventDefault();
+        break;
+      case "c":
+        changeBomLayout("top-bottom");
+        e.preventDefault();
+        break;
+      case "v":
+        changeCanvasLayout("F");
+        e.preventDefault();
+        break;
+      case "b":
+        changeCanvasLayout("FB");
+        e.preventDefault();
+        break;
+      case "n":
+        changeCanvasLayout("B");
+        e.preventDefault();
+        break;
+      default:
+        break;
+    }
+    if (e.key >= '1' && e.key <= '9') {
+      toggleBomCheckbox(currentHighlightedRowId, parseInt(e.key));
+      e.preventDefault();
+    }
+  }
+}
+
+function hideNetlistButton() {
+  document.getElementById("bom-ungrouped-btn").classList.remove("middle-button");
+  document.getElementById("bom-ungrouped-btn").classList.add("right-most-button");
+  document.getElementById("bom-netlist-btn").style.display = "none";
+}
+
+window.onload = function (e) {
+  initUtils();
+  initRender();
+  initStorage();
+  initDefaults();
+  cleanGutters();
+  populateMetadata();
+  dbgdiv = document.getElementById("dbg");
+  bom = document.getElementById("bombody");
+  bomhead = document.getElementById("bomhead");
+  filter = "";
+  reflookup = "";
+  if (!("nets" in pcbdata)) {
+    hideNetlistButton();
+  }
+  initDone = true;
+  setBomCheckboxes(document.getElementById("bomCheckboxes").value);
+  // Triggers render
+  changeBomLayout(settings.bomlayout);
+
+  // Users may leave fullscreen without touching the checkbox. Uncheck.
+  document.addEventListener('fullscreenchange', () => {
+    if (!document.fullscreenElement)
+      document.getElementById('fullscreenCheckbox').checked = false;
+  });
+}
+
+window.onresize = resizeAll;
+window.matchMedia("print").addListener(resizeAll);
+
+///////////////////////////////////////////////
+
+///////////////////////////////////////////////
+
+///////////////////////////////////////////////
+  </script>
+</head>
+
+<body>
+
+<div id="topmostdiv" class="topmostdiv">
+  <div id="top">
+    <div style="float: right; height: 100%;">
+      <div class="hideonprint menu" style="float: right; top: 8px;">
+        <button class="menubtn"></button>
+        <div class="menu-content">
+          <label class="menu-label menu-label-top" style="width: calc(50% - 18px)">
+            <input id="darkmodeCheckbox" type="checkbox" onchange="setDarkMode(this.checked)">
+            Dark mode
+          </label><!-- This comment eats space! All of it!
+          --><label class="menu-label menu-label-top" style="width: calc(50% - 17px); border-left: 0;">
+            <input id="fullscreenCheckbox" type="checkbox" onchange="setFullscreen(this.checked)">
+            Full Screen
+          </label>
+          <label class="menu-label" style="width: calc(50% - 18px)">
+            <input id="fabricationCheckbox" type="checkbox" checked onchange="fabricationVisible(this.checked)">
+            Fab layer
+          </label><!-- This comment eats space! All of it!
+          --><label class="menu-label" style="width: calc(50% - 17px); border-left: 0;">
+            <input id="silkscreenCheckbox" type="checkbox" checked onchange="silkscreenVisible(this.checked)">
+            Silkscreen
+          </label>
+          <label class="menu-label" style="width: calc(50% - 18px)">
+            <input id="referencesCheckbox" type="checkbox" checked onchange="referencesVisible(this.checked)">
+            References
+          </label><!-- This comment eats space! All of it!
+          --><label class="menu-label" style="width: calc(50% - 17px); border-left: 0;">
+            <input id="valuesCheckbox" type="checkbox" checked onchange="valuesVisible(this.checked)">
+            Values
+          </label>
+          <div id="tracksAndZonesCheckboxes">
+            <label class="menu-label" style="width: calc(50% - 18px)">
+              <input id="tracksCheckbox" type="checkbox" checked onchange="tracksVisible(this.checked)">
+              Tracks
+            </label><!-- This comment eats space! All of it!
+            --><label class="menu-label" style="width: calc(50% - 17px); border-left: 0;">
+              <input id="zonesCheckbox" type="checkbox" checked onchange="zonesVisible(this.checked)">
+              Zones
+            </label>
+          </div>
+          <label class="menu-label" style="width: calc(50% - 18px)">
+            <input id="padsCheckbox" type="checkbox" checked onchange="padsVisible(this.checked)">
+            Pads
+          </label><!-- This comment eats space! All of it!
+          --><label class="menu-label" style="width: calc(50% - 17px); border-left: 0;">
+            <input id="dnpOutlineCheckbox" type="checkbox" checked onchange="dnpOutline(this.checked)">
+            DNP outlined
+          </label>
+          <label class="menu-label">
+            <input id="highlightpin1Checkbox" type="checkbox" onchange="setHighlightPin1(this.checked)">
+            Highlight first pin
+          </label>
+          <label class="menu-label">
+            <input id="dragCheckbox" type="checkbox" checked onchange="setRedrawOnDrag(this.checked)">
+            Continuous redraw on drag
+          </label>
+          <label class="menu-label">
+            <span>Board rotation</span>
+            <span style="float: right"><span id="rotationDegree">0</span>&#176;</span>
+            <input id="boardRotation" type="range" min="-36" max="36" value="0" class="slider" oninput="setBoardRotation(this.value)">
+          </label>
+          <label class="menu-label">
+            <div style="margin-left: 5px">Bom checkboxes</div>
+            <input id="bomCheckboxes" class="menu-textbox" type=text
+                   oninput="setBomCheckboxes(this.value)">
+          </label>
+          <label class="menu-label">
+            <div style="margin-left: 5px">Mark when checked</div>
+            <div id="markWhenCheckedContainer"></div>
+          </label>
+          <label class="menu-label">
+            <span class="shameless-plug">
+              <span>Created using</span>
+              <a id="github-link" target="blank" href="https://github.com/openscopeproject/InteractiveHtmlBom">InteractiveHtmlBom</a>
+            </span>
+          </label>
+        </div>
+      </div>
+      <div class="button-container hideonprint"
+           style="float: right; position: relative; top: 8px">
+        <button id="fl-btn" class="left-most-button" onclick="changeCanvasLayout('F')"
+                title="Front only">F
+        </button>
+        <button id="fb-btn" class="middle-button" onclick="changeCanvasLayout('FB')"
+                title="Front and Back">FB
+        </button>
+        <button id="bl-btn" class="right-most-button" onclick="changeCanvasLayout('B')"
+                title="Back only">B
+        </button>
+      </div>
+      <div class="button-container hideonprint"
+           style="float: right; position: relative; top: 8px">
+        <button id="bom-btn" class="left-most-button" onclick="changeBomLayout('bom-only')"
+                title="BOM only"></button>
+        <button id="lr-btn" class="middle-button" onclick="changeBomLayout('left-right')"
+                title="BOM left, drawings right"></button>
+        <button id="tb-btn" class="right-most-button" onclick="changeBomLayout('top-bottom')"
+                title="BOM top, drawings bot"></button>
+      </div>
+      <div class="button-container hideonprint"
+           style="float: right; position: relative; top: 8px">
+        <button id="bom-grouped-btn" class="left-most-button" onclick="changeBomMode('grouped')"
+                title="Grouped BOM"></button>
+        <button id="bom-ungrouped-btn" class="middle-button" onclick="changeBomMode('ungrouped')"
+                title="Ungrouped BOM"></button>
+        <button id="bom-netlist-btn" class="right-most-button" onclick="changeBomMode('netlist')"
+                title="Netlist"></button>
+      </div>
+      <div class="hideonprint menu" style="float: right; top: 8px;">
+        <button class="statsbtn"></button>
+        <div class="menu-content">
+          <table class="stats">
+            <tbody>
+              <tr>
+                <td width="40%">Board stats</td>
+                <td>Front</td>
+                <td>Back</td>
+                <td>Total</td>
+              </tr>
+              <tr>
+                <td>Components</td>
+                <td id="stats-components-front">~</td>
+                <td id="stats-components-back">~</td>
+                <td id="stats-components-total">~</td>
+              </tr>
+              <tr>
+                <td>Groups</td>
+                <td id="stats-groups-front">~</td>
+                <td id="stats-groups-back">~</td>
+                <td id="stats-groups-total">~</td>
+              </tr>
+              <tr>
+                <td>SMD pads</td>
+                <td id="stats-smd-pads-front">~</td>
+                <td id="stats-smd-pads-back">~</td>
+                <td id="stats-smd-pads-total">~</td>
+              </tr>
+              <tr>
+                <td>TH pads</td>
+                <td colspan=3 id="stats-th-pads">~</td>
+              </tr>
+            </tbody>
+          </table>
+          <table class="stats">
+            <col width="40%"/><col />
+            <tbody id="checkbox-stats">
+              <tr>
+                <td colspan=2 style="border-top: 0">Checkboxes</td>
+              </tr>
+            </tbody>
+          </table>
+        </div>
+      </div>
+      <div class="hideonprint menu" style="float: right; top: 8px;">
+        <button class="iobtn"></button>
+        <div class="menu-content">
+          <div class="menu-label menu-label-top">
+            <div style="margin-left: 5px;">Save board image</div>
+            <div class="flexbox">
+              <input id="render-save-width" class="menu-textbox" type="text" value="1000" placeholder="Width"
+                  style="flex-grow: 1; width: 50px;" oninput="validateSaveImgDimension(this)">
+              <span>X</span>
+              <input id="render-save-height" class="menu-textbox" type="text" value="1000" placeholder="Height"
+                  style="flex-grow: 1; width: 50px;" oninput="validateSaveImgDimension(this)">
+            </div>
+            <label>
+              <input id="render-save-transparent" type="checkbox">
+              Transparent background
+            </label>
+            <div class="flexbox">
+              <button class="savebtn" onclick="saveImage('F')">Front</button>
+              <button class="savebtn" onclick="saveImage('B')">Back</button>
+            </div>
+          </div>
+          <div class="menu-label">
+            <span style="margin-left: 5px;">Config and checkbox state</span>
+            <div class="flexbox">
+              <button class="savebtn" onclick="saveSettings()">Export</button>
+              <button class="savebtn" onclick="loadSettings()">Import</button>
+            </div>
+          </div>
+        </div>
+      </div>
+    </div>
+    <div id="fileinfodiv" style="overflow: auto;">
+      <table class="fileinfo">
+        <tbody>
+          <tr>
+            <td id="title" class="title" style="width: 70%">
+              Title
+            </td>
+            <td id="revision" class="title" style="width: 30%">
+              Revision
+            </td>
+          </tr>
+          <tr>
+            <td id="company">
+              Company
+            </td>
+            <td id="filedate">
+              Date
+            </td>
+          </tr>
+        </tbody>
+      </table>
+    </div>
+  </div>
+  <div id="bot" class="split" style="height: calc(100% - 80px)">
+    <div id="bomdiv" class="split split-horizontal">
+      <div style="width: 100%">
+        <input id="reflookup" class="textbox searchbox reflookup hideonprint" type="text" placeholder="Ref lookup"
+               oninput="updateRefLookup(this.value)">
+        <input id="filter" class="textbox searchbox filter hideonprint" type="text" placeholder="Filter"
+               oninput="updateFilter(this.value)">
+        <div class="button-container hideonprint" style="float: left; margin: 0;">
+          <button id="copy" title="Copy bom table to clipboard"
+               onclick="copyToClipboard()"></button>
+        </div>
+      </div>
+      <div id="dbg"></div>
+      <table class="bom" id="bomtable">
+        <thead id="bomhead">
+        </thead>
+        <tbody id="bombody">
+        </tbody>
+      </table>
+    </div>
+    <div id="canvasdiv" class="split split-horizontal">
+      <div id="frontcanvas" class="split" touch-action="none" style="overflow: hidden">
+        <div style="position: relative; width: 100%; height: 100%;">
+          <canvas id="F_bg" style="position: absolute; left: 0; top: 0; z-index: 0;"></canvas>
+          <canvas id="F_fab" style="position: absolute; left: 0; top: 0; z-index: 1;"></canvas>
+          <canvas id="F_slk" style="position: absolute; left: 0; top: 0; z-index: 2;"></canvas>
+          <canvas id="F_hl" style="position: absolute; left: 0; top: 0; z-index: 3;"></canvas>
+        </div>
+      </div>
+      <div id="backcanvas" class="split" touch-action="none" style="overflow: hidden">
+        <div style="position: relative; width: 100%; height: 100%;">
+          <canvas id="B_bg" style="position: absolute; left: 0; top: 0; z-index: 0;"></canvas>
+          <canvas id="B_fab" style="position: absolute; left: 0; top: 0; z-index: 1;"></canvas>
+          <canvas id="B_slk" style="position: absolute; left: 0; top: 0; z-index: 2;"></canvas>
+          <canvas id="B_hl" style="position: absolute; left: 0; top: 0; z-index: 3;"></canvas>
+        </div>
+      </div>
+    </div>
+  </div>
+</div>
+
+</body>
+
+</html>
diff --git a/squeow_hw/fp-info-cache b/squeow_hw/fp-info-cache
new file mode 100644
index 0000000..a6cb776
--- /dev/null
+++ b/squeow_hw/fp-info-cache
@@ -0,0 +1,1947 @@
+463412594690780
+Connector_PinSocket_2.54mm
+PinSocket_1x01_P2.54mm_Horizontal
+Through hole angled socket strip, 1x01, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x01 2.54mm single row
+0
+1
+1
+Connector_PinSocket_2.54mm
+PinSocket_1x01_P2.54mm_Vertical
+Through hole straight socket strip, 1x01, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x01 2.54mm single row
+0
+1
+1
+Connector_PinSocket_2.54mm
+PinSocket_1x02_P2.54mm_Horizontal
+Through hole angled socket strip, 1x02, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x02 2.54mm single row
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_1x02_P2.54mm_Vertical
+Through hole straight socket strip, 1x02, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x02 2.54mm single row
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_1x02_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x02, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x02 2.54mm single row style1 pin1 left
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_1x02_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x02, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x02 2.54mm single row style2 pin1 right
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_1x03_P2.54mm_Horizontal
+Through hole angled socket strip, 1x03, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x03 2.54mm single row
+0
+3
+3
+Connector_PinSocket_2.54mm
+PinSocket_1x03_P2.54mm_Vertical
+Through hole straight socket strip, 1x03, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x03 2.54mm single row
+0
+3
+3
+Connector_PinSocket_2.54mm
+PinSocket_1x03_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x03 2.54mm single row style1 pin1 left
+0
+3
+3
+Connector_PinSocket_2.54mm
+PinSocket_1x03_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x03, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x03 2.54mm single row style2 pin1 right
+0
+3
+3
+Connector_PinSocket_2.54mm
+PinSocket_1x04_P2.54mm_Horizontal
+Through hole angled socket strip, 1x04, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x04 2.54mm single row
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_1x04_P2.54mm_Vertical
+Through hole straight socket strip, 1x04, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x04 2.54mm single row
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_1x04_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x04, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x04 2.54mm single row style1 pin1 left
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_1x04_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x04, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x04 2.54mm single row style2 pin1 right
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_1x05_P2.54mm_Horizontal
+Through hole angled socket strip, 1x05, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x05 2.54mm single row
+0
+5
+5
+Connector_PinSocket_2.54mm
+PinSocket_1x05_P2.54mm_Vertical
+Through hole straight socket strip, 1x05, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x05 2.54mm single row
+0
+5
+5
+Connector_PinSocket_2.54mm
+PinSocket_1x05_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x05, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x05 2.54mm single row style1 pin1 left
+0
+5
+5
+Connector_PinSocket_2.54mm
+PinSocket_1x05_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x05, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x05 2.54mm single row style2 pin1 right
+0
+5
+5
+Connector_PinSocket_2.54mm
+PinSocket_1x06_P2.54mm_Horizontal
+Through hole angled socket strip, 1x06, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x06 2.54mm single row
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_1x06_P2.54mm_Vertical
+Through hole straight socket strip, 1x06, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x06 2.54mm single row
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_1x06_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x06, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x06 2.54mm single row style1 pin1 left
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_1x06_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x06, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x06 2.54mm single row style2 pin1 right
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_1x07_P2.54mm_Horizontal
+Through hole angled socket strip, 1x07, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x07 2.54mm single row
+0
+7
+7
+Connector_PinSocket_2.54mm
+PinSocket_1x07_P2.54mm_Vertical
+Through hole straight socket strip, 1x07, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x07 2.54mm single row
+0
+7
+7
+Connector_PinSocket_2.54mm
+PinSocket_1x07_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x07, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x07 2.54mm single row style1 pin1 left
+0
+7
+7
+Connector_PinSocket_2.54mm
+PinSocket_1x07_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x07, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x07 2.54mm single row style2 pin1 right
+0
+7
+7
+Connector_PinSocket_2.54mm
+PinSocket_1x08_P2.54mm_Horizontal
+Through hole angled socket strip, 1x08, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x08 2.54mm single row
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_1x08_P2.54mm_Vertical
+Through hole straight socket strip, 1x08, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x08 2.54mm single row
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_1x08_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x08, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x08 2.54mm single row style1 pin1 left
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_1x08_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x08, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x08 2.54mm single row style2 pin1 right
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_1x09_P2.54mm_Horizontal
+Through hole angled socket strip, 1x09, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x09 2.54mm single row
+0
+9
+9
+Connector_PinSocket_2.54mm
+PinSocket_1x09_P2.54mm_Vertical
+Through hole straight socket strip, 1x09, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x09 2.54mm single row
+0
+9
+9
+Connector_PinSocket_2.54mm
+PinSocket_1x09_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x09, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x09 2.54mm single row style1 pin1 left
+0
+9
+9
+Connector_PinSocket_2.54mm
+PinSocket_1x09_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x09, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x09 2.54mm single row style2 pin1 right
+0
+9
+9
+Connector_PinSocket_2.54mm
+PinSocket_1x10_P2.54mm_Horizontal
+Through hole angled socket strip, 1x10, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x10 2.54mm single row
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_1x10_P2.54mm_Vertical
+Through hole straight socket strip, 1x10, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x10 2.54mm single row
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_1x10_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x10, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x10 2.54mm single row style1 pin1 left
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_1x10_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x10, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x10 2.54mm single row style2 pin1 right
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_1x11_P2.54mm_Horizontal
+Through hole angled socket strip, 1x11, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x11 2.54mm single row
+0
+11
+11
+Connector_PinSocket_2.54mm
+PinSocket_1x11_P2.54mm_Vertical
+Through hole straight socket strip, 1x11, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x11 2.54mm single row
+0
+11
+11
+Connector_PinSocket_2.54mm
+PinSocket_1x11_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x11, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x11 2.54mm single row style1 pin1 left
+0
+11
+11
+Connector_PinSocket_2.54mm
+PinSocket_1x11_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x11, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x11 2.54mm single row style2 pin1 right
+0
+11
+11
+Connector_PinSocket_2.54mm
+PinSocket_1x12_P2.54mm_Horizontal
+Through hole angled socket strip, 1x12, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x12 2.54mm single row
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_1x12_P2.54mm_Vertical
+Through hole straight socket strip, 1x12, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x12 2.54mm single row
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_1x12_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x12, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x12 2.54mm single row style1 pin1 left
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_1x12_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x12, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x12 2.54mm single row style2 pin1 right
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_1x13_P2.54mm_Horizontal
+Through hole angled socket strip, 1x13, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x13 2.54mm single row
+0
+13
+13
+Connector_PinSocket_2.54mm
+PinSocket_1x13_P2.54mm_Vertical
+Through hole straight socket strip, 1x13, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x13 2.54mm single row
+0
+13
+13
+Connector_PinSocket_2.54mm
+PinSocket_1x13_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x13, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x13 2.54mm single row style1 pin1 left
+0
+13
+13
+Connector_PinSocket_2.54mm
+PinSocket_1x13_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x13, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x13 2.54mm single row style2 pin1 right
+0
+13
+13
+Connector_PinSocket_2.54mm
+PinSocket_1x14_P2.54mm_Horizontal
+Through hole angled socket strip, 1x14, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x14 2.54mm single row
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_1x14_P2.54mm_Vertical
+Through hole straight socket strip, 1x14, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x14 2.54mm single row
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_1x14_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x14, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x14 2.54mm single row style1 pin1 left
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_1x14_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x14, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x14 2.54mm single row style2 pin1 right
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_1x15_P2.54mm_Horizontal
+Through hole angled socket strip, 1x15, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x15 2.54mm single row
+0
+15
+15
+Connector_PinSocket_2.54mm
+PinSocket_1x15_P2.54mm_Vertical
+Through hole straight socket strip, 1x15, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x15 2.54mm single row
+0
+15
+15
+Connector_PinSocket_2.54mm
+PinSocket_1x15_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x15, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x15 2.54mm single row style1 pin1 left
+0
+15
+15
+Connector_PinSocket_2.54mm
+PinSocket_1x15_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x15, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x15 2.54mm single row style2 pin1 right
+0
+15
+15
+Connector_PinSocket_2.54mm
+PinSocket_1x16_P2.54mm_Horizontal
+Through hole angled socket strip, 1x16, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x16 2.54mm single row
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_1x16_P2.54mm_Vertical
+Through hole straight socket strip, 1x16, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x16 2.54mm single row
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_1x16_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x16, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x16 2.54mm single row style1 pin1 left
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_1x16_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x16, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x16 2.54mm single row style2 pin1 right
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_1x17_P2.54mm_Horizontal
+Through hole angled socket strip, 1x17, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x17 2.54mm single row
+0
+17
+17
+Connector_PinSocket_2.54mm
+PinSocket_1x17_P2.54mm_Vertical
+Through hole straight socket strip, 1x17, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x17 2.54mm single row
+0
+17
+17
+Connector_PinSocket_2.54mm
+PinSocket_1x17_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x17, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x17 2.54mm single row style1 pin1 left
+0
+17
+17
+Connector_PinSocket_2.54mm
+PinSocket_1x17_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x17, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x17 2.54mm single row style2 pin1 right
+0
+17
+17
+Connector_PinSocket_2.54mm
+PinSocket_1x18_P2.54mm_Horizontal
+Through hole angled socket strip, 1x18, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x18 2.54mm single row
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_1x18_P2.54mm_Vertical
+Through hole straight socket strip, 1x18, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x18 2.54mm single row
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_1x18_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x18, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x18 2.54mm single row style1 pin1 left
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_1x18_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x18, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x18 2.54mm single row style2 pin1 right
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_1x19_P2.54mm_Horizontal
+Through hole angled socket strip, 1x19, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x19 2.54mm single row
+0
+19
+19
+Connector_PinSocket_2.54mm
+PinSocket_1x19_P2.54mm_Vertical
+Through hole straight socket strip, 1x19, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x19 2.54mm single row
+0
+19
+19
+Connector_PinSocket_2.54mm
+PinSocket_1x19_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x19, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x19 2.54mm single row style1 pin1 left
+0
+19
+19
+Connector_PinSocket_2.54mm
+PinSocket_1x19_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x19, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x19 2.54mm single row style2 pin1 right
+0
+19
+19
+Connector_PinSocket_2.54mm
+PinSocket_1x20_P2.54mm_Horizontal
+Through hole angled socket strip, 1x20, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x20 2.54mm single row
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_1x20_P2.54mm_Vertical
+Through hole straight socket strip, 1x20, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x20 2.54mm single row
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_1x20_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x20, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x20 2.54mm single row style1 pin1 left
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_1x20_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x20, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x20 2.54mm single row style2 pin1 right
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_1x21_P2.54mm_Horizontal
+Through hole angled socket strip, 1x21, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x21 2.54mm single row
+0
+21
+21
+Connector_PinSocket_2.54mm
+PinSocket_1x21_P2.54mm_Vertical
+Through hole straight socket strip, 1x21, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x21 2.54mm single row
+0
+21
+21
+Connector_PinSocket_2.54mm
+PinSocket_1x21_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x21, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x21 2.54mm single row style1 pin1 left
+0
+21
+21
+Connector_PinSocket_2.54mm
+PinSocket_1x21_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x21, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x21 2.54mm single row style2 pin1 right
+0
+21
+21
+Connector_PinSocket_2.54mm
+PinSocket_1x22_P2.54mm_Horizontal
+Through hole angled socket strip, 1x22, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x22 2.54mm single row
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_1x22_P2.54mm_Vertical
+Through hole straight socket strip, 1x22, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x22 2.54mm single row
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_1x22_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x22, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x22 2.54mm single row style1 pin1 left
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_1x22_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x22, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x22 2.54mm single row style2 pin1 right
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_1x23_P2.54mm_Horizontal
+Through hole angled socket strip, 1x23, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x23 2.54mm single row
+0
+23
+23
+Connector_PinSocket_2.54mm
+PinSocket_1x23_P2.54mm_Vertical
+Through hole straight socket strip, 1x23, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x23 2.54mm single row
+0
+23
+23
+Connector_PinSocket_2.54mm
+PinSocket_1x23_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x23, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x23 2.54mm single row style1 pin1 left
+0
+23
+23
+Connector_PinSocket_2.54mm
+PinSocket_1x23_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x23, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x23 2.54mm single row style2 pin1 right
+0
+23
+23
+Connector_PinSocket_2.54mm
+PinSocket_1x24_P2.54mm_Horizontal
+Through hole angled socket strip, 1x24, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x24 2.54mm single row
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_1x24_P2.54mm_Vertical
+Through hole straight socket strip, 1x24, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x24 2.54mm single row
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_1x24_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x24, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x24 2.54mm single row style1 pin1 left
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_1x24_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x24, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x24 2.54mm single row style2 pin1 right
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_1x25_P2.54mm_Horizontal
+Through hole angled socket strip, 1x25, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x25 2.54mm single row
+0
+25
+25
+Connector_PinSocket_2.54mm
+PinSocket_1x25_P2.54mm_Vertical
+Through hole straight socket strip, 1x25, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x25 2.54mm single row
+0
+25
+25
+Connector_PinSocket_2.54mm
+PinSocket_1x25_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x25, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x25 2.54mm single row style1 pin1 left
+0
+25
+25
+Connector_PinSocket_2.54mm
+PinSocket_1x25_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x25, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x25 2.54mm single row style2 pin1 right
+0
+25
+25
+Connector_PinSocket_2.54mm
+PinSocket_1x26_P2.54mm_Horizontal
+Through hole angled socket strip, 1x26, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x26 2.54mm single row
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_1x26_P2.54mm_Vertical
+Through hole straight socket strip, 1x26, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x26 2.54mm single row
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_1x26_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x26, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x26 2.54mm single row style1 pin1 left
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_1x26_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x26, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x26 2.54mm single row style2 pin1 right
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_1x27_P2.54mm_Horizontal
+Through hole angled socket strip, 1x27, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x27 2.54mm single row
+0
+27
+27
+Connector_PinSocket_2.54mm
+PinSocket_1x27_P2.54mm_Vertical
+Through hole straight socket strip, 1x27, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x27 2.54mm single row
+0
+27
+27
+Connector_PinSocket_2.54mm
+PinSocket_1x27_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x27, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x27 2.54mm single row style1 pin1 left
+0
+27
+27
+Connector_PinSocket_2.54mm
+PinSocket_1x27_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x27, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x27 2.54mm single row style2 pin1 right
+0
+27
+27
+Connector_PinSocket_2.54mm
+PinSocket_1x28_P2.54mm_Horizontal
+Through hole angled socket strip, 1x28, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x28 2.54mm single row
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_1x28_P2.54mm_Vertical
+Through hole straight socket strip, 1x28, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x28 2.54mm single row
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_1x28_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x28, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x28 2.54mm single row style1 pin1 left
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_1x28_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x28, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x28 2.54mm single row style2 pin1 right
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_1x29_P2.54mm_Horizontal
+Through hole angled socket strip, 1x29, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x29 2.54mm single row
+0
+29
+29
+Connector_PinSocket_2.54mm
+PinSocket_1x29_P2.54mm_Vertical
+Through hole straight socket strip, 1x29, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x29 2.54mm single row
+0
+29
+29
+Connector_PinSocket_2.54mm
+PinSocket_1x29_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x29, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x29 2.54mm single row style1 pin1 left
+0
+29
+29
+Connector_PinSocket_2.54mm
+PinSocket_1x29_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x29, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x29 2.54mm single row style2 pin1 right
+0
+29
+29
+Connector_PinSocket_2.54mm
+PinSocket_1x30_P2.54mm_Horizontal
+Through hole angled socket strip, 1x30, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x30 2.54mm single row
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_1x30_P2.54mm_Vertical
+Through hole straight socket strip, 1x30, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x30 2.54mm single row
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_1x30_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x30, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x30 2.54mm single row style1 pin1 left
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_1x30_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x30, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x30 2.54mm single row style2 pin1 right
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_1x31_P2.54mm_Horizontal
+Through hole angled socket strip, 1x31, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x31 2.54mm single row
+0
+31
+31
+Connector_PinSocket_2.54mm
+PinSocket_1x31_P2.54mm_Vertical
+Through hole straight socket strip, 1x31, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x31 2.54mm single row
+0
+31
+31
+Connector_PinSocket_2.54mm
+PinSocket_1x31_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x31, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x31 2.54mm single row style1 pin1 left
+0
+31
+31
+Connector_PinSocket_2.54mm
+PinSocket_1x31_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x31, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x31 2.54mm single row style2 pin1 right
+0
+31
+31
+Connector_PinSocket_2.54mm
+PinSocket_1x32_P2.54mm_Horizontal
+Through hole angled socket strip, 1x32, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x32 2.54mm single row
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_1x32_P2.54mm_Vertical
+Through hole straight socket strip, 1x32, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x32 2.54mm single row
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_1x32_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x32, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x32 2.54mm single row style1 pin1 left
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_1x32_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x32, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x32 2.54mm single row style2 pin1 right
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_1x33_P2.54mm_Horizontal
+Through hole angled socket strip, 1x33, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x33 2.54mm single row
+0
+33
+33
+Connector_PinSocket_2.54mm
+PinSocket_1x33_P2.54mm_Vertical
+Through hole straight socket strip, 1x33, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x33 2.54mm single row
+0
+33
+33
+Connector_PinSocket_2.54mm
+PinSocket_1x33_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x33, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x33 2.54mm single row style1 pin1 left
+0
+33
+33
+Connector_PinSocket_2.54mm
+PinSocket_1x33_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x33, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x33 2.54mm single row style2 pin1 right
+0
+33
+33
+Connector_PinSocket_2.54mm
+PinSocket_1x34_P2.54mm_Horizontal
+Through hole angled socket strip, 1x34, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x34 2.54mm single row
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_1x34_P2.54mm_Vertical
+Through hole straight socket strip, 1x34, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x34 2.54mm single row
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_1x34_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x34, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x34 2.54mm single row style1 pin1 left
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_1x34_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x34, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x34 2.54mm single row style2 pin1 right
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_1x35_P2.54mm_Horizontal
+Through hole angled socket strip, 1x35, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x35 2.54mm single row
+0
+35
+35
+Connector_PinSocket_2.54mm
+PinSocket_1x35_P2.54mm_Vertical
+Through hole straight socket strip, 1x35, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x35 2.54mm single row
+0
+35
+35
+Connector_PinSocket_2.54mm
+PinSocket_1x35_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x35, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x35 2.54mm single row style1 pin1 left
+0
+35
+35
+Connector_PinSocket_2.54mm
+PinSocket_1x35_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x35, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x35 2.54mm single row style2 pin1 right
+0
+35
+35
+Connector_PinSocket_2.54mm
+PinSocket_1x36_P2.54mm_Horizontal
+Through hole angled socket strip, 1x36, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x36 2.54mm single row
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_1x36_P2.54mm_Vertical
+Through hole straight socket strip, 1x36, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x36 2.54mm single row
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_1x36_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x36, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x36 2.54mm single row style1 pin1 left
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_1x36_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x36, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x36 2.54mm single row style2 pin1 right
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_1x37_P2.54mm_Horizontal
+Through hole angled socket strip, 1x37, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x37 2.54mm single row
+0
+37
+37
+Connector_PinSocket_2.54mm
+PinSocket_1x37_P2.54mm_Vertical
+Through hole straight socket strip, 1x37, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x37 2.54mm single row
+0
+37
+37
+Connector_PinSocket_2.54mm
+PinSocket_1x37_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x37, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x37 2.54mm single row style1 pin1 left
+0
+37
+37
+Connector_PinSocket_2.54mm
+PinSocket_1x37_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x37, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x37 2.54mm single row style2 pin1 right
+0
+37
+37
+Connector_PinSocket_2.54mm
+PinSocket_1x38_P2.54mm_Horizontal
+Through hole angled socket strip, 1x38, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x38 2.54mm single row
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_1x38_P2.54mm_Vertical
+Through hole straight socket strip, 1x38, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x38 2.54mm single row
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_1x38_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x38, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x38 2.54mm single row style1 pin1 left
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_1x38_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x38, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x38 2.54mm single row style2 pin1 right
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_1x39_P2.54mm_Horizontal
+Through hole angled socket strip, 1x39, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x39 2.54mm single row
+0
+39
+39
+Connector_PinSocket_2.54mm
+PinSocket_1x39_P2.54mm_Vertical
+Through hole straight socket strip, 1x39, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x39 2.54mm single row
+0
+39
+39
+Connector_PinSocket_2.54mm
+PinSocket_1x39_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x39, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x39 2.54mm single row style1 pin1 left
+0
+39
+39
+Connector_PinSocket_2.54mm
+PinSocket_1x39_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x39, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x39 2.54mm single row style2 pin1 right
+0
+39
+39
+Connector_PinSocket_2.54mm
+PinSocket_1x40_P2.54mm_Horizontal
+Through hole angled socket strip, 1x40, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x40 2.54mm single row
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_1x40_P2.54mm_Vertical
+Through hole straight socket strip, 1x40, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x40 2.54mm single row
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_1x40_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x40, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x40 2.54mm single row style1 pin1 left
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_1x40_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x40, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x40 2.54mm single row style2 pin1 right
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_2x01_P2.54mm_Horizontal
+Through hole angled socket strip, 2x01, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x01 2.54mm double row
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_2x01_P2.54mm_Vertical
+Through hole straight socket strip, 2x01, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x01 2.54mm double row
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_2x01_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x01, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x01 2.54mm double row
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_2x02_P2.54mm_Horizontal
+Through hole angled socket strip, 2x02, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x02 2.54mm double row
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_2x02_P2.54mm_Vertical
+Through hole straight socket strip, 2x02, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x02 2.54mm double row
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_2x02_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x02, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x02 2.54mm double row
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_2x03_P2.54mm_Horizontal
+Through hole angled socket strip, 2x03, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x03 2.54mm double row
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_2x03_P2.54mm_Vertical
+Through hole straight socket strip, 2x03, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x03 2.54mm double row
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_2x03_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x03, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x03 2.54mm double row
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_2x04_P2.54mm_Horizontal
+Through hole angled socket strip, 2x04, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x04 2.54mm double row
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_2x04_P2.54mm_Vertical
+Through hole straight socket strip, 2x04, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x04 2.54mm double row
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_2x04_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x04, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x04 2.54mm double row
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_2x05_P2.54mm_Horizontal
+Through hole angled socket strip, 2x05, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x05 2.54mm double row
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_2x05_P2.54mm_Vertical
+Through hole straight socket strip, 2x05, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x05 2.54mm double row
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_2x05_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x05, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x05 2.54mm double row
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_2x06_P2.54mm_Horizontal
+Through hole angled socket strip, 2x06, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x06 2.54mm double row
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_2x06_P2.54mm_Vertical
+Through hole straight socket strip, 2x06, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x06 2.54mm double row
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_2x06_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x06, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x06 2.54mm double row
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_2x07_P2.54mm_Horizontal
+Through hole angled socket strip, 2x07, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x07 2.54mm double row
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_2x07_P2.54mm_Vertical
+Through hole straight socket strip, 2x07, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x07 2.54mm double row
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_2x07_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x07, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x07 2.54mm double row
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_2x08_P2.54mm_Horizontal
+Through hole angled socket strip, 2x08, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x08 2.54mm double row
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_2x08_P2.54mm_Vertical
+Through hole straight socket strip, 2x08, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x08 2.54mm double row
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_2x08_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x08, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x08 2.54mm double row
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_2x09_P2.54mm_Horizontal
+Through hole angled socket strip, 2x09, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x09 2.54mm double row
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_2x09_P2.54mm_Vertical
+Through hole straight socket strip, 2x09, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x09 2.54mm double row
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_2x09_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x09, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x09 2.54mm double row
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_2x10_P2.54mm_Horizontal
+Through hole angled socket strip, 2x10, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x10 2.54mm double row
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_2x10_P2.54mm_Vertical
+Through hole straight socket strip, 2x10, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x10 2.54mm double row
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_2x10_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x10, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x10 2.54mm double row
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_2x11_P2.54mm_Horizontal
+Through hole angled socket strip, 2x11, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x11 2.54mm double row
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_2x11_P2.54mm_Vertical
+Through hole straight socket strip, 2x11, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x11 2.54mm double row
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_2x11_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x11, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x11 2.54mm double row
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_2x12_P2.54mm_Horizontal
+Through hole angled socket strip, 2x12, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x12 2.54mm double row
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_2x12_P2.54mm_Vertical
+Through hole straight socket strip, 2x12, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x12 2.54mm double row
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_2x12_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x12, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x12 2.54mm double row
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_2x13_P2.54mm_Horizontal
+Through hole angled socket strip, 2x13, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x13 2.54mm double row
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_2x13_P2.54mm_Vertical
+Through hole straight socket strip, 2x13, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x13 2.54mm double row
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_2x13_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x13, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x13 2.54mm double row
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_2x14_P2.54mm_Horizontal
+Through hole angled socket strip, 2x14, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x14 2.54mm double row
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_2x14_P2.54mm_Vertical
+Through hole straight socket strip, 2x14, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x14 2.54mm double row
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_2x14_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x14, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x14 2.54mm double row
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_2x15_P2.54mm_Horizontal
+Through hole angled socket strip, 2x15, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x15 2.54mm double row
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_2x15_P2.54mm_Vertical
+Through hole straight socket strip, 2x15, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x15 2.54mm double row
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_2x15_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x15, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x15 2.54mm double row
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_2x16_P2.54mm_Horizontal
+Through hole angled socket strip, 2x16, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x16 2.54mm double row
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_2x16_P2.54mm_Vertical
+Through hole straight socket strip, 2x16, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x16 2.54mm double row
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_2x16_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x16, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x16 2.54mm double row
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_2x17_P2.54mm_Horizontal
+Through hole angled socket strip, 2x17, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x17 2.54mm double row
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_2x17_P2.54mm_Vertical
+Through hole straight socket strip, 2x17, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x17 2.54mm double row
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_2x17_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x17, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x17 2.54mm double row
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_2x18_P2.54mm_Horizontal
+Through hole angled socket strip, 2x18, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x18 2.54mm double row
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_2x18_P2.54mm_Vertical
+Through hole straight socket strip, 2x18, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x18 2.54mm double row
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_2x18_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x18, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x18 2.54mm double row
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_2x19_P2.54mm_Horizontal
+Through hole angled socket strip, 2x19, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x19 2.54mm double row
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_2x19_P2.54mm_Vertical
+Through hole straight socket strip, 2x19, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x19 2.54mm double row
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_2x19_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x19, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x19 2.54mm double row
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_2x20_P2.54mm_Horizontal
+Through hole angled socket strip, 2x20, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x20 2.54mm double row
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_2x20_P2.54mm_Vertical
+Through hole straight socket strip, 2x20, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x20 2.54mm double row
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_2x20_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x20, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x20 2.54mm double row
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_2x21_P2.54mm_Horizontal
+Through hole angled socket strip, 2x21, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x21 2.54mm double row
+0
+42
+42
+Connector_PinSocket_2.54mm
+PinSocket_2x21_P2.54mm_Vertical
+Through hole straight socket strip, 2x21, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x21 2.54mm double row
+0
+42
+42
+Connector_PinSocket_2.54mm
+PinSocket_2x21_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x21, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x21 2.54mm double row
+0
+42
+42
+Connector_PinSocket_2.54mm
+PinSocket_2x22_P2.54mm_Horizontal
+Through hole angled socket strip, 2x22, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x22 2.54mm double row
+0
+44
+44
+Connector_PinSocket_2.54mm
+PinSocket_2x22_P2.54mm_Vertical
+Through hole straight socket strip, 2x22, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x22 2.54mm double row
+0
+44
+44
+Connector_PinSocket_2.54mm
+PinSocket_2x22_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x22, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x22 2.54mm double row
+0
+44
+44
+Connector_PinSocket_2.54mm
+PinSocket_2x23_P2.54mm_Horizontal
+Through hole angled socket strip, 2x23, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x23 2.54mm double row
+0
+46
+46
+Connector_PinSocket_2.54mm
+PinSocket_2x23_P2.54mm_Vertical
+Through hole straight socket strip, 2x23, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x23 2.54mm double row
+0
+46
+46
+Connector_PinSocket_2.54mm
+PinSocket_2x23_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x23, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x23 2.54mm double row
+0
+46
+46
+Connector_PinSocket_2.54mm
+PinSocket_2x24_P2.54mm_Horizontal
+Through hole angled socket strip, 2x24, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x24 2.54mm double row
+0
+48
+48
+Connector_PinSocket_2.54mm
+PinSocket_2x24_P2.54mm_Vertical
+Through hole straight socket strip, 2x24, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x24 2.54mm double row
+0
+48
+48
+Connector_PinSocket_2.54mm
+PinSocket_2x24_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x24, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x24 2.54mm double row
+0
+48
+48
+Connector_PinSocket_2.54mm
+PinSocket_2x25_P2.54mm_Horizontal
+Through hole angled socket strip, 2x25, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x25 2.54mm double row
+0
+50
+50
+Connector_PinSocket_2.54mm
+PinSocket_2x25_P2.54mm_Vertical
+Through hole straight socket strip, 2x25, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x25 2.54mm double row
+0
+50
+50
+Connector_PinSocket_2.54mm
+PinSocket_2x25_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x25, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x25 2.54mm double row
+0
+50
+50
+Connector_PinSocket_2.54mm
+PinSocket_2x26_P2.54mm_Horizontal
+Through hole angled socket strip, 2x26, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x26 2.54mm double row
+0
+52
+52
+Connector_PinSocket_2.54mm
+PinSocket_2x26_P2.54mm_Vertical
+Through hole straight socket strip, 2x26, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x26 2.54mm double row
+0
+52
+52
+Connector_PinSocket_2.54mm
+PinSocket_2x26_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x26, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x26 2.54mm double row
+0
+52
+52
+Connector_PinSocket_2.54mm
+PinSocket_2x27_P2.54mm_Horizontal
+Through hole angled socket strip, 2x27, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x27 2.54mm double row
+0
+54
+54
+Connector_PinSocket_2.54mm
+PinSocket_2x27_P2.54mm_Vertical
+Through hole straight socket strip, 2x27, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x27 2.54mm double row
+0
+54
+54
+Connector_PinSocket_2.54mm
+PinSocket_2x27_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x27, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x27 2.54mm double row
+0
+54
+54
+Connector_PinSocket_2.54mm
+PinSocket_2x28_P2.54mm_Horizontal
+Through hole angled socket strip, 2x28, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x28 2.54mm double row
+0
+56
+56
+Connector_PinSocket_2.54mm
+PinSocket_2x28_P2.54mm_Vertical
+Through hole straight socket strip, 2x28, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x28 2.54mm double row
+0
+56
+56
+Connector_PinSocket_2.54mm
+PinSocket_2x28_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x28, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x28 2.54mm double row
+0
+56
+56
+Connector_PinSocket_2.54mm
+PinSocket_2x29_P2.54mm_Horizontal
+Through hole angled socket strip, 2x29, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x29 2.54mm double row
+0
+58
+58
+Connector_PinSocket_2.54mm
+PinSocket_2x29_P2.54mm_Vertical
+Through hole straight socket strip, 2x29, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x29 2.54mm double row
+0
+58
+58
+Connector_PinSocket_2.54mm
+PinSocket_2x29_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x29, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x29 2.54mm double row
+0
+58
+58
+Connector_PinSocket_2.54mm
+PinSocket_2x30_P2.54mm_Horizontal
+Through hole angled socket strip, 2x30, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x30 2.54mm double row
+0
+60
+60
+Connector_PinSocket_2.54mm
+PinSocket_2x30_P2.54mm_Vertical
+Through hole straight socket strip, 2x30, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x30 2.54mm double row
+0
+60
+60
+Connector_PinSocket_2.54mm
+PinSocket_2x30_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x30, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x30 2.54mm double row
+0
+60
+60
+Connector_PinSocket_2.54mm
+PinSocket_2x31_P2.54mm_Horizontal
+Through hole angled socket strip, 2x31, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x31 2.54mm double row
+0
+62
+62
+Connector_PinSocket_2.54mm
+PinSocket_2x31_P2.54mm_Vertical
+Through hole straight socket strip, 2x31, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x31 2.54mm double row
+0
+62
+62
+Connector_PinSocket_2.54mm
+PinSocket_2x31_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x31, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x31 2.54mm double row
+0
+62
+62
+Connector_PinSocket_2.54mm
+PinSocket_2x32_P2.54mm_Horizontal
+Through hole angled socket strip, 2x32, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x32 2.54mm double row
+0
+64
+64
+Connector_PinSocket_2.54mm
+PinSocket_2x32_P2.54mm_Vertical
+Through hole straight socket strip, 2x32, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x32 2.54mm double row
+0
+64
+64
+Connector_PinSocket_2.54mm
+PinSocket_2x32_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x32, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x32 2.54mm double row
+0
+64
+64
+Connector_PinSocket_2.54mm
+PinSocket_2x33_P2.54mm_Horizontal
+Through hole angled socket strip, 2x33, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x33 2.54mm double row
+0
+66
+66
+Connector_PinSocket_2.54mm
+PinSocket_2x33_P2.54mm_Vertical
+Through hole straight socket strip, 2x33, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x33 2.54mm double row
+0
+66
+66
+Connector_PinSocket_2.54mm
+PinSocket_2x33_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x33, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x33 2.54mm double row
+0
+66
+66
+Connector_PinSocket_2.54mm
+PinSocket_2x34_P2.54mm_Horizontal
+Through hole angled socket strip, 2x34, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x34 2.54mm double row
+0
+68
+68
+Connector_PinSocket_2.54mm
+PinSocket_2x34_P2.54mm_Vertical
+Through hole straight socket strip, 2x34, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x34 2.54mm double row
+0
+68
+68
+Connector_PinSocket_2.54mm
+PinSocket_2x34_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x34, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x34 2.54mm double row
+0
+68
+68
+Connector_PinSocket_2.54mm
+PinSocket_2x35_P2.54mm_Horizontal
+Through hole angled socket strip, 2x35, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x35 2.54mm double row
+0
+70
+70
+Connector_PinSocket_2.54mm
+PinSocket_2x35_P2.54mm_Vertical
+Through hole straight socket strip, 2x35, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x35 2.54mm double row
+0
+70
+70
+Connector_PinSocket_2.54mm
+PinSocket_2x35_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x35, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x35 2.54mm double row
+0
+70
+70
+Connector_PinSocket_2.54mm
+PinSocket_2x36_P2.54mm_Horizontal
+Through hole angled socket strip, 2x36, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x36 2.54mm double row
+0
+72
+72
+Connector_PinSocket_2.54mm
+PinSocket_2x36_P2.54mm_Vertical
+Through hole straight socket strip, 2x36, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x36 2.54mm double row
+0
+72
+72
+Connector_PinSocket_2.54mm
+PinSocket_2x36_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x36, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x36 2.54mm double row
+0
+72
+72
+Connector_PinSocket_2.54mm
+PinSocket_2x37_P2.54mm_Horizontal
+Through hole angled socket strip, 2x37, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x37 2.54mm double row
+0
+74
+74
+Connector_PinSocket_2.54mm
+PinSocket_2x37_P2.54mm_Vertical
+Through hole straight socket strip, 2x37, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x37 2.54mm double row
+0
+74
+74
+Connector_PinSocket_2.54mm
+PinSocket_2x37_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x37, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x37 2.54mm double row
+0
+74
+74
+Connector_PinSocket_2.54mm
+PinSocket_2x38_P2.54mm_Horizontal
+Through hole angled socket strip, 2x38, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x38 2.54mm double row
+0
+76
+76
+Connector_PinSocket_2.54mm
+PinSocket_2x38_P2.54mm_Vertical
+Through hole straight socket strip, 2x38, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x38 2.54mm double row
+0
+76
+76
+Connector_PinSocket_2.54mm
+PinSocket_2x38_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x38, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x38 2.54mm double row
+0
+76
+76
+Connector_PinSocket_2.54mm
+PinSocket_2x39_P2.54mm_Horizontal
+Through hole angled socket strip, 2x39, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x39 2.54mm double row
+0
+78
+78
+Connector_PinSocket_2.54mm
+PinSocket_2x39_P2.54mm_Vertical
+Through hole straight socket strip, 2x39, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x39 2.54mm double row
+0
+78
+78
+Connector_PinSocket_2.54mm
+PinSocket_2x39_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x39, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x39 2.54mm double row
+0
+78
+78
+Connector_PinSocket_2.54mm
+PinSocket_2x40_P2.54mm_Horizontal
+Through hole angled socket strip, 2x40, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x40 2.54mm double row
+0
+80
+80
+Connector_PinSocket_2.54mm
+PinSocket_2x40_P2.54mm_Vertical
+Through hole straight socket strip, 2x40, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x40 2.54mm double row
+0
+80
+80
+Connector_PinSocket_2.54mm
+PinSocket_2x40_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x40, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x40 2.54mm double row
+0
+80
+80
diff --git a/squeow_hw/jlcpcb.zip b/squeow_hw/jlcpcb.zip
new file mode 100644
index 0000000000000000000000000000000000000000..6ff0588c0da8170ce482dc358c948819d1c51c96
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new file mode 100644
index 0000000..f94386b
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diff --git a/squeow_hw/jlcpcb/squeow-B_Mask.gbs b/squeow_hw/jlcpcb/squeow-B_Mask.gbs
new file mode 100644
index 0000000..a9a369c
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diff --git a/squeow_hw/jlcpcb/squeow-B_Paste.gbp b/squeow_hw/jlcpcb/squeow-B_Paste.gbp
new file mode 100644
index 0000000..439d538
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diff --git a/squeow_hw/jlcpcb/squeow-B_Silkscreen.gbo b/squeow_hw/jlcpcb/squeow-B_Silkscreen.gbo
new file mode 100644
index 0000000..6f3f4b7
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new file mode 100644
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diff --git a/squeow_hw/jlcpcb/squeow-F_Cu.gtl b/squeow_hw/jlcpcb/squeow-F_Cu.gtl
new file mode 100644
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diff --git a/squeow_hw/jlcpcb/squeow-F_Mask.gts b/squeow_hw/jlcpcb/squeow-F_Mask.gts
new file mode 100644
index 0000000..132b12b
--- /dev/null
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diff --git a/squeow_hw/jlcpcb/squeow-F_Paste.gtp b/squeow_hw/jlcpcb/squeow-F_Paste.gtp
new file mode 100644
index 0000000..3c3034d
--- /dev/null
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diff --git a/squeow_hw/jlcpcb/squeow-F_Silkscreen.gto b/squeow_hw/jlcpcb/squeow-F_Silkscreen.gto
new file mode 100644
index 0000000..1690703
--- /dev/null
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diff --git a/squeow_hw/jlcpcb/squeow-PTH.drl b/squeow_hw/jlcpcb/squeow-PTH.drl
new file mode 100644
index 0000000..6a1ace4
--- /dev/null
+++ b/squeow_hw/jlcpcb/squeow-PTH.drl
@@ -0,0 +1,32 @@
+M48
+; DRILL file {KiCad 6.0.7+dfsg-3} date mer 5 ott 2022, 14:52:04
+; FORMAT={-:-/ absolute / metric / decimal}
+; #@! TF.CreationDate,2022-10-05T14:52:04+02:00
+; #@! TF.GenerationSoftware,Kicad,Pcbnew,6.0.7+dfsg-3
+; #@! TF.FileFunction,Plated,1,2,PTH
+FMAT,2
+METRIC
+; #@! TA.AperFunction,Plated,PTH,ViaDrill
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diff --git a/squeow_hw/squeow-backups/squeow-2022-10-04_134218.zip b/squeow_hw/squeow-backups/squeow-2022-10-04_134218.zip
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literal 0
HcmV?d00001

diff --git a/squeow_hw/squeow.kicad_pcb b/squeow_hw/squeow.kicad_pcb
new file mode 100644
index 0000000..4daabb2
--- /dev/null
+++ b/squeow_hw/squeow.kicad_pcb
@@ -0,0 +1,3901 @@
+(kicad_pcb (version 20221018) (generator pcbnew)
+
+  (general
+    (thickness 1.6)
+  )
+
+  (paper "A4")
+  (layers
+    (0 "F.Cu" signal)
+    (31 "B.Cu" signal)
+    (32 "B.Adhes" user "B.Adhesive")
+    (33 "F.Adhes" user "F.Adhesive")
+    (34 "B.Paste" user)
+    (35 "F.Paste" user)
+    (36 "B.SilkS" user "B.Silkscreen")
+    (37 "F.SilkS" user "F.Silkscreen")
+    (38 "B.Mask" user)
+    (39 "F.Mask" user)
+    (40 "Dwgs.User" user "User.Drawings")
+    (41 "Cmts.User" user "User.Comments")
+    (42 "Eco1.User" user "User.Eco1")
+    (43 "Eco2.User" user "User.Eco2")
+    (44 "Edge.Cuts" user)
+    (45 "Margin" user)
+    (46 "B.CrtYd" user "B.Courtyard")
+    (47 "F.CrtYd" user "F.Courtyard")
+    (48 "B.Fab" user)
+    (49 "F.Fab" user)
+    (50 "User.1" user)
+    (51 "User.2" user)
+    (52 "User.3" user)
+    (53 "User.4" user)
+    (54 "User.5" user)
+    (55 "User.6" user)
+    (56 "User.7" user)
+    (57 "User.8" user)
+    (58 "User.9" user)
+  )
+
+  (setup
+    (stackup
+      (layer "F.SilkS" (type "Top Silk Screen"))
+      (layer "F.Paste" (type "Top Solder Paste"))
+      (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
+      (layer "F.Cu" (type "copper") (thickness 0.035))
+      (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
+      (layer "B.Cu" (type "copper") (thickness 0.035))
+      (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
+      (layer "B.Paste" (type "Bottom Solder Paste"))
+      (layer "B.SilkS" (type "Bottom Silk Screen"))
+      (copper_finish "None")
+      (dielectric_constraints no)
+    )
+    (pad_to_mask_clearance 0)
+    (pcbplotparams
+      (layerselection 0x00010fc_ffffffff)
+      (plot_on_all_layers_selection 0x0000000_00000000)
+      (disableapertmacros false)
+      (usegerberextensions true)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (dashed_line_dash_ratio 12.000000)
+      (dashed_line_gap_ratio 3.000000)
+      (svgprecision 6)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (dxfpolygonmode true)
+      (dxfimperialunits true)
+      (dxfusepcbnewfont true)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue false)
+      (plotinvisibletext false)
+      (sketchpadsonfab false)
+      (subtractmaskfromsilk true)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "jlcpcb/")
+    )
+  )
+
+  (net 0 "")
+  (net 1 "Net-(C1-Pad1)")
+  (net 2 "Net-(C1-Pad2)")
+  (net 3 "VCC")
+  (net 4 "GND")
+  (net 5 "Net-(J1-Pad2)")
+  (net 6 "+3.3V")
+  (net 7 "unconnected-(U1-Pad3)")
+  (net 8 "unconnected-(U1-Pad6)")
+  (net 9 "Net-(U1-Pad9)")
+  (net 10 "Net-(U2-Pad2)")
+  (net 11 "Net-(U2-Pad3)")
+  (net 12 "Net-(J9-Pad1)")
+  (net 13 "Net-(R3-Pad2)")
+  (net 14 "unconnected-(U2-Pad26)")
+  (net 15 "unconnected-(U2-Pad27)")
+  (net 16 "unconnected-(U2-Pad28)")
+  (net 17 "unconnected-(U2-Pad29)")
+  (net 18 "unconnected-(U4-Pad3)")
+  (net 19 "Net-(J1-Pad3)")
+  (net 20 "Net-(J1-Pad4)")
+  (net 21 "Net-(J1-Pad5)")
+  (net 22 "Net-(U1-Pad10)")
+  (net 23 "Net-(R1-Pad2)")
+  (net 24 "unconnected-(U3-Pad3)")
+  (net 25 "unconnected-(U3-Pad1)")
+  (net 26 "unconnected-(U3-Pad2)")
+  (net 27 "Net-(R2-Pad2)")
+  (net 28 "unconnected-(U3-Pad7)")
+  (net 29 "unconnected-(U5-Pad3)")
+  (net 30 "unconnected-(U2-Pad18)")
+  (net 31 "Net-(D1-Pad3)")
+  (net 32 "Net-(D2-Pad3)")
+  (net 33 "Net-(D3-Pad3)")
+  (net 34 "Net-(D4-Pad3)")
+  (net 35 "Net-(D5-Pad2)")
+  (net 36 "Net-(J8-Pad1)")
+  (net 37 "Net-(J4-Pad3)")
+  (net 38 "Net-(J4-Pad4)")
+  (net 39 "Net-(J4-Pad5)")
+  (net 40 "Net-(J4-Pad6)")
+  (net 41 "Net-(J4-Pad8)")
+  (net 42 "Net-(J4-Pad9)")
+  (net 43 "Net-(U2-Pad13)")
+
+  (footprint "Connector_PinSocket_2.54mm:PinSocket_1x08_P2.54mm_Vertical_SMD_Pin1Left" (layer "F.Cu")
+    (tstamp 0477bad4-91d0-48fa-a528-c2785f560c45)
+    (at 29.3624 52.9844 90)
+    (descr "surface-mounted straight socket strip, 1x08, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated")
+    (tags "Surface mounted socket strip SMD 1x08 2.54mm single row style1 pin1 left")
+    (property "Sheetfile" "squeow.kicad_sch")
+    (property "Sheetname" "")
+    (path "/b1eb3852-85b3-447e-97c7-dfd2c1ef979b")
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new file mode 100644
index 0000000..1067b0b
--- /dev/null
+++ b/squeow_hw/squeow.kicad_prl
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diff --git a/squeow_hw/squeow.kicad_pro b/squeow_hw/squeow.kicad_pro
new file mode 100644
index 0000000..49c760d
--- /dev/null
+++ b/squeow_hw/squeow.kicad_pro
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+        "copper_sliver": "warning",
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+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
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+        "npth_inside_courtyard": "ignore",
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+        "pth_inside_courtyard": "ignore",
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+        "silk_over_copper": "warning",
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+    "net_format_name": "",
+    "ngspice": {
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+      "fix_passive_vals": false,
+      "meta": {
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+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_current_sheet_as_root": false,
+    "spice_external_command": "spice \"%I\"",
+    "spice_model_current_sheet_as_root": true,
+    "spice_save_all_currents": false,
+    "spice_save_all_voltages": false,
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+    "subpart_id_separator": 0
+  },
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+  ],
+  "text_variables": {}
+}
diff --git a/squeow_hw/squeow.kicad_sch b/squeow_hw/squeow.kicad_sch
new file mode 100644
index 0000000..4c0a530
--- /dev/null
+++ b/squeow_hw/squeow.kicad_sch
@@ -0,0 +1,3923 @@
+(kicad_sch (version 20230121) (generator eeschema)
+
+  (uuid dd809985-7087-414a-8be4-5f927ae2bdb6)
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+  (paper "A4")
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+    (property "Datasheet" "" (at 66.04 73.66 0)
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+    (pin "1" (uuid f052ec0b-3d34-4928-a647-fcf373e2885e))
+    (instances
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+        )
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+    )
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+
+  (symbol (lib_id "fzzt-rescue:IXDN609PI-ixdn609pi") (at 179.07 69.85 0) (unit 1)
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+    (pin "8" (uuid 6a6d8461-5293-4eed-9632-77b20f506627))
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+    )
+  )
+
+  (symbol (lib_id "power:+3.3V") (at 113.03 152.4 180) (unit 1)
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+    (uuid ce3ed3b9-26b0-4068-9c02-daf7e179d00c)
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+    )
+    (property "Value" "+3.3V" (at 110.49 156.21 0)
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+    (property "Footprint" "" (at 113.03 152.4 0)
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+        )
+      )
+    )
+  )
+
+  (symbol (lib_id "power:GND") (at 116.84 152.4 90) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced)
+    (uuid d10f1deb-3462-41da-972d-b07153d3cdb2)
+    (property "Reference" "#PWR015" (at 123.19 152.4 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (at 120.65 152.3999 90)
+      (effects (font (size 1.27 1.27)) (justify right))
+    )
+    (property "Footprint" "" (at 116.84 152.4 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (at 116.84 152.4 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 36d27768-f05a-4c5f-a81f-a525bdec51c5))
+    (instances
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+        (path "/dd809985-7087-414a-8be4-5f927ae2bdb6"
+          (reference "#PWR015") (unit 1)
+        )
+      )
+    )
+  )
+
+  (symbol (lib_id "power:+3.3V") (at 193.04 97.79 270) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced)
+    (uuid d2416109-3bce-46d8-8d9b-083738ec3147)
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+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "+3.3V" (at 196.85 97.7899 90)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "" (at 193.04 97.79 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (at 193.04 97.79 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 5ae528ec-9ff0-417c-bcca-c75fc3073262))
+    (instances
+      (project "squeow"
+        (path "/dd809985-7087-414a-8be4-5f927ae2bdb6"
+          (reference "#PWR033") (unit 1)
+        )
+      )
+    )
+  )
+
+  (symbol (lib_id "power:VCC") (at 163.83 97.79 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced)
+    (uuid d6ffe743-4a6b-4fab-9bf4-b5d30f2e746a)
+    (property "Reference" "#PWR029" (at 163.83 101.6 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "VCC" (at 163.83 92.71 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 163.83 97.79 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (at 163.83 97.79 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 73bb3655-e7a4-4874-bf29-56f55c9e586c))
+    (instances
+      (project "squeow"
+        (path "/dd809985-7087-414a-8be4-5f927ae2bdb6"
+          (reference "#PWR029") (unit 1)
+        )
+      )
+    )
+  )
+
+  (symbol (lib_id "power:GND") (at 129.54 157.48 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced)
+    (uuid d8997028-a5a2-4d97-8b9b-da732a3f7930)
+    (property "Reference" "#PWR017" (at 129.54 163.83 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (at 132.08 158.7499 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "" (at 129.54 157.48 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (at 129.54 157.48 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 752e8c92-cbcc-4dab-a2c2-2fc0f1d5800b))
+    (instances
+      (project "squeow"
+        (path "/dd809985-7087-414a-8be4-5f927ae2bdb6"
+          (reference "#PWR017") (unit 1)
+        )
+      )
+    )
+  )
+
+  (symbol (lib_id "Diode:BAT54SW") (at 45.72 154.94 0) (mirror y) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced)
+    (uuid dfe6720c-c823-45d0-8b65-257861e7f330)
+    (property "Reference" "D2" (at 45.72 148.59 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "BAT54SW" (at 45.72 151.13 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "Package_TO_SOT_SMD:SOT-323_SC-70" (at 43.815 151.765 0)
+      (effects (font (size 1.27 1.27)) (justify left) hide)
+    )
+    (property "Datasheet" "https://assets.nexperia.com/documents/data-sheet/BAT54W_SER.pdf" (at 48.768 154.94 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 85cf24f8-a40a-45f9-9e9b-c47442e25490))
+    (pin "2" (uuid 10171d11-d24e-40a2-adfc-3889309469e7))
+    (pin "3" (uuid 04eb5cc5-4c93-4d5f-abbd-3844e14af20f))
+    (instances
+      (project "squeow"
+        (path "/dd809985-7087-414a-8be4-5f927ae2bdb6"
+          (reference "D2") (unit 1)
+        )
+      )
+    )
+  )
+
+  (symbol (lib_id "Regulator_Linear:AZ1117R-ADJ") (at 176.53 97.79 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced)
+    (uuid efad2a02-4ebf-46ec-b0f4-c112b41c5bd0)
+    (property "Reference" "U6" (at 176.53 90.17 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "AZ1117R-ADJ" (at 176.53 92.71 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "Package_TO_SOT_SMD:SOT-89-3" (at 176.53 91.44 0)
+      (effects (font (size 1.27 1.27) italic) hide)
+    )
+    (property "Datasheet" "https://www.diodes.com/assets/Datasheets/products_inactive_data/AZ1117.pdf" (at 176.53 97.79 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 8f796c26-2554-455d-ae91-4916c3a31451))
+    (pin "2" (uuid 98bb7b29-be43-4206-aaa8-315012fe2683))
+    (pin "3" (uuid 097577bb-baf6-4a1d-a8d3-6ba3b6470892))
+    (instances
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+        (path "/dd809985-7087-414a-8be4-5f927ae2bdb6"
+          (reference "U6") (unit 1)
+        )
+      )
+    )
+  )
+
+  (symbol (lib_id "power:GND") (at 142.24 105.41 270) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced)
+    (uuid f03bc10e-c6dc-44bf-a012-21260163f64c)
+    (property "Reference" "#PWR023" (at 135.89 105.41 0)
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+    )
+    (property "Value" "GND" (at 138.43 105.4099 90)
+      (effects (font (size 1.27 1.27)) (justify right))
+    )
+    (property "Footprint" "" (at 142.24 105.41 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (at 142.24 105.41 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 52695252-3c5b-407b-9e8e-ce430623b3ae))
+    (instances
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+        (path "/dd809985-7087-414a-8be4-5f927ae2bdb6"
+          (reference "#PWR023") (unit 1)
+        )
+      )
+    )
+  )
+
+  (symbol (lib_id "power:GND") (at 33.02 138.43 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced)
+    (uuid f3a0f934-e94d-4b25-aed7-9a0eac4abc7d)
+    (property "Reference" "#PWR02" (at 33.02 144.78 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (at 35.56 139.6999 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "" (at 33.02 138.43 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (at 33.02 138.43 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 210b856e-7b77-4249-9b3a-42a5f1f18646))
+    (instances
+      (project "squeow"
+        (path "/dd809985-7087-414a-8be4-5f927ae2bdb6"
+          (reference "#PWR02") (unit 1)
+        )
+      )
+    )
+  )
+
+  (symbol (lib_id "Connector:Conn_01x06_Male") (at 67.31 184.15 90) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced)
+    (uuid f4b4a183-d9bc-4713-9132-211ab82e1874)
+    (property "Reference" "J2" (at 68.58 186.69 90)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "GattaBUS" (at 68.58 189.23 90)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical_SMD_Pin1Left" (at 67.31 184.15 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (at 67.31 184.15 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 4c6ebd85-5f57-446c-8f71-3c1bf40f080b))
+    (pin "2" (uuid 2c5a0f81-b0d8-466f-8c7e-c7db92f8dbd5))
+    (pin "3" (uuid b8bb6f46-adea-4402-bb98-8e0fdc2cccd6))
+    (pin "4" (uuid 5ea4ffa9-18ae-42cd-b74d-ad2984248fdd))
+    (pin "5" (uuid 8e765b00-bdd1-4fef-8604-c6a41e3d50bb))
+    (pin "6" (uuid adf94584-a9b3-4483-a871-a43cc0b26764))
+    (instances
+      (project "squeow"
+        (path "/dd809985-7087-414a-8be4-5f927ae2bdb6"
+          (reference "J2") (unit 1)
+        )
+      )
+    )
+  )
+
+  (symbol (lib_id "Device:C") (at 157.48 101.6 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
+    (uuid f65dc182-2ca3-45be-801d-efa69dd19ec3)
+    (property "Reference" "C6" (at 160.401 100.4316 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Value" "220n" (at 160.401 102.743 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "Capacitor_SMD:C_1210_3225Metric_Pad1.33x2.70mm_HandSolder" (at 158.4452 105.41 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (at 157.48 101.6 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid d42644d9-56ba-490d-bd06-83777681a878))
+    (pin "2" (uuid 9b7f9176-2c2f-41fd-9e5f-99e5a723f676))
+    (instances
+      (project "squeow"
+        (path "/dd809985-7087-414a-8be4-5f927ae2bdb6"
+          (reference "C6") (unit 1)
+        )
+      )
+    )
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+)
diff --git a/squeow_mod/_autosave-squeow_mod.kicad_pcb b/squeow_mod/_autosave-squeow_mod.kicad_pcb
new file mode 100644
index 0000000..a72ba19
--- /dev/null
+++ b/squeow_mod/_autosave-squeow_mod.kicad_pcb
@@ -0,0 +1,2067 @@
+(kicad_pcb (version 20221018) (generator pcbnew)
+
+  (general
+    (thickness 1.6)
+  )
+
+  (paper "A4")
+  (layers
+    (0 "F.Cu" signal)
+    (31 "B.Cu" signal)
+    (32 "B.Adhes" user "B.Adhesive")
+    (33 "F.Adhes" user "F.Adhesive")
+    (34 "B.Paste" user)
+    (35 "F.Paste" user)
+    (36 "B.SilkS" user "B.Silkscreen")
+    (37 "F.SilkS" user "F.Silkscreen")
+    (38 "B.Mask" user)
+    (39 "F.Mask" user)
+    (40 "Dwgs.User" user "User.Drawings")
+    (41 "Cmts.User" user "User.Comments")
+    (42 "Eco1.User" user "User.Eco1")
+    (43 "Eco2.User" user "User.Eco2")
+    (44 "Edge.Cuts" user)
+    (45 "Margin" user)
+    (46 "B.CrtYd" user "B.Courtyard")
+    (47 "F.CrtYd" user "F.Courtyard")
+    (48 "B.Fab" user)
+    (49 "F.Fab" user)
+    (50 "User.1" user)
+    (51 "User.2" user)
+    (52 "User.3" user)
+    (53 "User.4" user)
+    (54 "User.5" user)
+    (55 "User.6" user)
+    (56 "User.7" user)
+    (57 "User.8" user)
+    (58 "User.9" user)
+  )
+
+  (setup
+    (stackup
+      (layer "F.SilkS" (type "Top Silk Screen"))
+      (layer "F.Paste" (type "Top Solder Paste"))
+      (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
+      (layer "F.Cu" (type "copper") (thickness 0.035))
+      (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
+      (layer "B.Cu" (type "copper") (thickness 0.035))
+      (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
+      (layer "B.Paste" (type "Bottom Solder Paste"))
+      (layer "B.SilkS" (type "Bottom Silk Screen"))
+      (copper_finish "None")
+      (dielectric_constraints no)
+    )
+    (pad_to_mask_clearance 0)
+    (aux_axis_origin 46.9825 16.51)
+    (pcbplotparams
+      (layerselection 0x00010fc_ffffffff)
+      (plot_on_all_layers_selection 0x0000000_00000000)
+      (disableapertmacros false)
+      (usegerberextensions false)
+      (usegerberattributes true)
+      (usegerberadvancedattributes true)
+      (creategerberjobfile true)
+      (dashed_line_dash_ratio 12.000000)
+      (dashed_line_gap_ratio 3.000000)
+      (svgprecision 6)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin true)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (dxfpolygonmode true)
+      (dxfimperialunits true)
+      (dxfusepcbnewfont true)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (sketchpadsonfab false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "")
+    )
+  )
+
+  (net 0 "")
+  (net 1 "GND")
+  (net 2 "unconnected-(U4-Pad2)")
+  (net 3 "unconnected-(U3-Pad2)")
+  (net 4 "unconnected-(U2-Pad2)")
+  (net 5 "unconnected-(U1-Pad2)")
+  (net 6 "Net-(R4-Pad1)")
+  (net 7 "Net-(R3-Pad1)")
+  (net 8 "Net-(R2-Pad1)")
+  (net 9 "Net-(R1-Pad1)")
+  (net 10 "Net-(Q4-Pad1)")
+  (net 11 "Net-(Q3-Pad1)")
+  (net 12 "Net-(Q2-Pad1)")
+  (net 13 "Net-(Q1-Pad1)")
+  (net 14 "Net-(J6-Pad5)")
+  (net 15 "Net-(J6-Pad4)")
+  (net 16 "Net-(J6-Pad3)")
+  (net 17 "Net-(J6-Pad2)")
+  (net 18 "Net-(J6-Pad1)")
+  (net 19 "Net-(D3-Pad2)")
+  (net 20 "Net-(D2-Pad2)")
+  (net 21 "Net-(D1-Pad2)")
+  (net 22 "Net-(D1-Pad1)")
+  (net 23 "Net-(C4-Pad2)")
+  (net 24 "Net-(C4-Pad1)")
+  (net 25 "Net-(C3-Pad2)")
+  (net 26 "Net-(C3-Pad1)")
+  (net 27 "Net-(C2-Pad2)")
+  (net 28 "Net-(C2-Pad1)")
+  (net 29 "Net-(C1-Pad2)")
+  (net 30 "Net-(C1-Pad1)")
+
+  (footprint "Package_TO_SOT_THT:TO-220F-3_Horizontal_TabDown" (layer "F.Cu")
+    (tstamp 0134792b-1e2a-48a7-a29d-5d883dfcafa1)
+    (at 50.96 78.105 90)
+    (descr "TO-220F-3, Horizontal, RM 2.54mm, see http://www.st.com/resource/en/datasheet/stp20nm60.pdf")
+    (tags "TO-220F-3 Horizontal RM 2.54mm")
+    (property "Sheetfile" "squeow_mod.kicad_sch")
+    (property "Sheetname" "")
+    (path "/34aa2012-1c68-4d57-95ca-133c293530aa")
+    (attr through_hole)
+    (fp_text reference "D1" (at 2.54 -20.22 90) (layer "F.SilkS")
+        (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp e3cbea0c-3e3c-4c91-bd43-134aefdd0b3b)
+    )
+    (fp_text value "D_Schottky_x2_ACom_KAK" (at 2.54 2 90) (layer "F.Fab")
+        (effects (font (size 1 1) (thickness 0.15)))
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+  (segment (start 59.3725 72.0725) (end 55.88 75.565) (width 2) (layer "F.Cu") (net 21) (tstamp 7a0adfcb-e65f-45cd-b15f-1cd0ddbad5ca))
+  (segment (start 52.07 56.515) (end 60.54 64.985) (width 2) (layer "F.Cu") (net 21) (tstamp 7fe58093-583d-41ef-9dc7-a5957b4719e6))
+  (segment (start 56.93 71.755) (end 59.055 71.755) (width 1) (layer "F.Cu") (net 21) (tstamp 8618f475-191d-403f-a4fd-1320937d2b4b))
+  (segment (start 59.055 71.755) (end 59.3725 72.0725) (width 1) (layer "F.Cu") (net 21) (tstamp ada321cb-1977-4a6e-9b00-4dee1ad55ca4))
+  (segment (start 60.54 64.985) (end 60.54 70.905) (width 2) (layer "F.Cu") (net 21) (tstamp bdb89c98-635d-42c5-afac-fc6c3bf04e58))
+  (segment (start 50.96 56.515) (end 52.07 56.515) (width 2) (layer "F.Cu") (net 21) (tstamp bf90ca37-2481-4af3-b6c2-dc7c47681280))
+  (segment (start 50.96 78.105) (end 52.07 78.105) (width 2) (layer "F.Cu") (net 22) (tstamp 176faa20-226e-4809-bfb1-d56d6b11b41d))
+  (segment (start 48.46 86.4475) (end 50.96 86.4475) (width 2) (layer "F.Cu") (net 22) (tstamp 3b3aef3e-d2c7-401a-aa6b-94164a612c90))
+  (segment (start 59.69 93.345) (end 59.69 92.93) (width 1) (layer "F.Cu") (net 22) (tstamp 3cf020a4-8ba0-4c89-bc94-3bc6f70126f8))
+  (segment (start 52.07 78.105) (end 60.54 86.575) (width 2) (layer "F.Cu") (net 22) (tstamp 472131de-a4c1-442e-9005-76726a09c32e))
+  (segment (start 48.46 91.005) (end 48.46 86.4475) (width 2) (layer "F.Cu") (net 22) (tstamp 5efe1963-65ed-42f7-bb05-9861767e9ae5))
+  (segment (start 60.54 92.495) (end 59.69 93.345) (width 2) (layer "F.Cu") (net 22) (tstamp 73a577d1-5784-4bdd-bf31-086f7ca7b4b7))
+  (segment (start 58.5625 94.4725) (end 59.69 93.345) (width 2) (layer "F.Cu") (net 22) (tstamp 9744cd76-653a-405f-b4a6-9ba12f1c940c))
+  (segment (start 51.9275 94.4725) (end 58.5625 94.4725) (width 2) (layer "F.Cu") (net 22) (tstamp a1a2b873-4ece-4f5f-bfe9-b67b85f75558))
+  (segment (start 59.69 92.93) (end 59.47 92.71) (width 1) (layer "F.Cu") (net 22) (tstamp c6b98802-b8ef-470f-b8d6-8c2bfdd1d2fc))
+  (segment (start 50.8 93.345) (end 51.9275 94.4725) (width 2) (layer "F.Cu") (net 22) (tstamp ccbef230-1dc7-477f-a3a1-35fe6c15af5a))
+  (segment (start 60.54 86.575) (end 60.54 92.495) (width 2) (layer "F.Cu") (net 22) (tstamp f6725e05-bf1c-42ff-baef-dc746da76ad7))
+  (segment (start 50.8 93.345) (end 48.46 91.005) (width 2) (layer "F.Cu") (net 22) (tstamp f9a0a125-dc7a-4051-a4e3-01cd11b548e9))
+  (segment (start 54.61 21.9925) (end 54.61 19.44) (width 2) (layer "F.Cu") (net 23) (tstamp 4e34a65c-24f2-44a9-9552-5baa94a4bccc))
+  (segment (start 54.61 21.9925) (end 55.4275 22.81) (width 1) (layer "F.Cu") (net 23) (tstamp 6269ec4c-c4bd-4d99-9ee1-6203d530342a))
+  (segment (start 55.4275 22.81) (end 57.96 22.81) (width 1) (layer "F.Cu") (net 23) (tstamp a0424235-ff99-4902-8269-cfc67fb7b041))
+  (segment (start 50.96 19.05) (end 55 19.05) (width 2) (layer "F.Cu") (net 23) (tstamp d25d37e2-afd4-4cf9-a7eb-8f632a713737))
+  (segment (start 54.83 28.575) (end 54.83 26.4875) (width 1) (layer "F.Cu") (net 24) (tstamp 00424083-3a06-4fab-9227-0f6abbadc52b))
+  (segment (start 54.61 26.2675) (end 55.4275 25.45) (width 1) (layer "F.Cu") (net 24) (tstamp e7d3ba02-c542-4a6e-819c-bac9b5d0f909))
+  (segment (start 55.4275 25.45) (end 57.96 25.45) (width 1) (layer "F.Cu") (net 24) (tstamp f7c587d2-2fe0-4b26-90b1-2c74cd4612ba))
+  (segment (start 48.895 21.59) (end 48.46 22.025) (width 2) (layer "F.Cu") (net 25) (tstamp 19306891-16af-4694-a828-7a789e8136e0))
+  (segment (start 52.705 40.64) (end 54.61 42.545) (width 2) (layer "F.Cu") (net 25) (tstamp 1daf9f6b-b098-447c-88a4-e631efc860de))
+  (segment (start 48.46 38.14) (end 50.96 40.64) (width 2) (layer "F.Cu") (net 25) (tstamp 28042122-8000-4ec2-ae63-450571a4b334))
+  (segment (start 48.46 22.025) (end 48.46 30.28) (width 2) (layer "F.Cu") (net 25) (tstamp 355c503f-de6e-4a00-98ee-2bbd9c0a6ca5))
+  (segment (start 54.61 42.545) (end 54.61 43.5825) (width 2) (layer "F.Cu") (net 25) (tstamp 3cab63ad-0b16-4209-bf66-3a55411dceca))
+  (segment (start 54.61 43.5825) (end 55.4275 44.4) (width 1) (layer "F.Cu") (net 25) (tstamp 5020c4e3-eb92-4ff0-8d74-6a01d58b51cf))
+  (segment (start 50.96 21.59) (end 48.895 21.59) (width 2) (layer "F.Cu") (net 25) (tstamp 5482ab7a-af5c-4ecf-b516-9bdce87f7d4c))
+  (segment (start 55.4275 44.4) (end 57.96 44.4) (width 1) (layer "F.Cu") (net 25) (tstamp 7f89b7b3-24da-4986-85f1-97f0db66de9e))
+  (segment (start 48.46 30.28) (end 48.46 38.14) (width 2) (layer "F.Cu") (net 25) (tstamp b1e443f4-5038-442a-ac34-45564cf16c6f))
+  (segment (start 48.895 29.845) (end 48.46 30.28) (width 2) (layer "F.Cu") (net 25) (tstamp bfafb6d1-a623-4077-bd56-caf9a3536be9))
+  (segment (start 50.96 29.845) (end 48.895 29.845) (width 2) (layer "F.Cu") (net 25) (tstamp e7703231-0a8e-4041-b591-d9ef39e9db9e))
+  (segment (start 50.96 40.64) (end 52.705 40.64) (width 2) (layer "F.Cu") (net 25) (tstamp f71ca8fc-391b-4365-93f9-f6b7c5fb254f))
+  (segment (start 54.61 47.8575) (end 55.4275 47.04) (width 1) (layer "F.Cu") (net 26) (tstamp 1c5019b1-46d4-4984-8a01-362d6a1cce82))
+  (segment (start 55.4275 47.04) (end 57.96 47.04) (width 1) (layer "F.Cu") (net 26) (tstamp ad842466-9e46-4d2c-b2be-b97cbf14f3d6))
+  (segment (start 54.83 50.165) (end 54.83 48.0775) (width 1) (layer "F.Cu") (net 26) (tstamp c8b38c04-ce26-4fd9-a95f-66a124ffb0f0))
+  (segment (start 48.5475 43.18) (end 48.46 43.2675) (width 2) (layer "F.Cu") (net 27) (tstamp 0c39745f-cdb4-42f8-b2a0-8828be85cd21))
+  (segment (start 50.96 62.23) (end 52.07 62.23) (width 2) (layer "F.Cu") (net 27) (tstamp 1b035314-2b9e-48f4-a7c9-c2deb7c9fe8a))
+  (segment (start 50.96 43.18) (end 48.5475 43.18) (width 2) (layer "F.Cu") (net 27) (tstamp 404d0661-4068-479f-85a0-e5549993ad27))
+  (segment (start 48.46 51.635) (end 48.46 59.73) (width 2) (layer "F.Cu") (net 27) (tstamp 4f685399-e74e-44a7-9eb8-d1805a649f0f))
+  (segment (start 54.61 65.1725) (end 55.4275 65.99) (width 1) (layer "F.Cu") (net 27) (tstamp 5b597d12-ecc7-43ae-8199-fb2e04b96d6c))
+  (segment (start 48.66 51.435) (end 48.46 51.635) (width 2) (layer "F.Cu") (net 27) (tstamp 5cadce4d-4a1e-4af7-baaf-5fbf78949932))
+  (segment (start 54.61 64.77) (end 54.61 65.1725) (width 2) (layer "F.Cu") (net 27) (tstamp 8b1b0c40-69f0-46dc-8f62-91b54bcf03a1))
+  (segment (start 55.4275 65.99) (end 57.96 65.99) (width 1) (layer "F.Cu") (net 27) (tstamp 951fb68f-e2bc-4382-8f95-1e5694566506))
+  (segment (start 50.96 51.435) (end 48.66 51.435) (width 2) (layer "F.Cu") (net 27) (tstamp ba88c8e3-eae8-4bca-8bfa-47efcd9f1c3b))
+  (segment (start 48.46 43.2675) (end 48.46 51.635) (width 2) (layer "F.Cu") (net 27) (tstamp d8bcf9cf-28c1-4fd8-9e5c-94ad91992ad7))
+  (segment (start 48.46 59.73) (end 50.96 62.23) (width 2) (layer "F.Cu") (net 27) (tstamp dc977a5f-ff3a-4c79-8b77-bc66c38ff992))
+  (segment (start 52.07 62.23) (end 54.61 64.77) (width 2) (layer "F.Cu") (net 27) (tstamp eaedefd9-a44c-48b8-8e51-4e41ee85108a))
+  (segment (start 55.4275 68.63) (end 57.96 68.63) (width 1) (layer "F.Cu") (net 28) (tstamp 52408008-8c99-4d3a-9cc0-4f301362c612))
+  (segment (start 54.83 71.755) (end 54.83 69.6675) (width 1) (layer "F.Cu") (net 28) (tstamp 638c05ac-8e53-4357-94c2-3a31cf9e8340))
+  (segment (start 54.61 69.4475) (end 55.4275 68.63) (width 1) (layer "F.Cu") (net 28) (tstamp cb61fd3f-f65e-4d94-b40c-8cf45ce3cb72))
+  (segment (start 48.895 73.025) (end 48.46 72.59) (width 2) (layer "F.Cu") (net 29) (tstamp 155c5b6d-851e-45e2-8bc4-624b20dbef77))
+  (segment (start 49.809141 83.82) (end 50.96 83.82) (width 2) (layer "F.Cu") (net 29) (tstamp 412c3144-c50d-4330-91c6-05ed9a29f58a))
+  (segment (start 54.61 86.7625) (end 55.4275 87.58) (width 1) (layer "F.Cu") (net 29) (tstamp 5fde0381-b7e6-4fcf-ac8d-a6e80ec20f14))
+  (segment (start 52.07 83.82) (end 54.61 86.36) (width 2) (layer "F.Cu") (net 29) (tstamp 66cafd64-3853-4dfb-bf4b-0a40d2e59d33))
+  (segment (start 48.46 72.59) (end 48.46 82.470859) (width 2) (layer "F.Cu") (net 29) (tstamp 6f8af218-1481-4864-93ed-a738bd48bf5b))
+  (segment (start 50.96 83.82) (end 52.07 83.82) (width 2) (layer "F.Cu") (net 29) (tstamp 793a4950-89f2-4aaa-bb4d-069c8c2c5011))
+  (segment (start 48.46 64.8575) (end 48.46 72.59) (width 2) (layer "F.Cu") (net 29) (tstamp 80987aca-2b41-4647-b329-ba7a5ca2cdab))
+  (segment (start 55.4275 87.58) (end 57.96 87.58) (width 1) (layer "F.Cu") (net 29) (tstamp 8e0ac09b-ee86-4d70-87d2-5efb9ac08844))
+  (segment (start 54.61 86.36) (end 54.61 86.7625) (width 2) (layer "F.Cu") (net 29) (tstamp 8f15f807-477e-4829-826e-850b1c7598bf))
+  (segment (start 48.46 82.470859) (end 49.809141 83.82) (width 2) (layer "F.Cu") (net 29) (tstamp a78aebb5-23d6-4d94-9a2f-37f032bbafcc))
+  (segment (start 48.5475 64.77) (end 48.46 64.8575) (width 2) (layer "F.Cu") (net 29) (tstamp dddc0e0f-c4d1-4231-aff0-92639633c58b))
+  (segment (start 50.96 64.77) (end 48.5475 64.77) (width 2) (layer "F.Cu") (net 29) (tstamp e9a65852-edb9-4333-b6aa-01a494c660a2))
+  (segment (start 50.96 73.025) (end 48.895 73.025) (width 2) (layer "F.Cu") (net 29) (tstamp f7a9ee9d-8e70-41a3-9db5-92382637ba31))
+  (segment (start 57.3575 92.7225) (end 57.37 92.71) (width 1) (layer "F.Cu") (net 30) (tstamp 27534811-f109-4315-8e5c-3b3dc7002c04))
+  (segment (start 55.4275 90.22) (end 57.96 90.22) (width 1) (layer "F.Cu") (net 30) (tstamp 49245ea2-dee1-4ab8-a8ae-15424dd3f1e1))
+  (segment (start 54.61 91.0375) (end 55.4275 90.22) (width 1) (layer "F.Cu") (net 30) (tstamp 58f4ff1a-69cc-409b-97ce-470d60554d96))
+  (segment (start 56.295 92.7225) (end 57.3575 92.7225) (width 1) (layer "F.Cu") (net 30) (tstamp 5f3be7c3-701f-4965-8e7c-af8244a59f7c))
+  (segment (start 56.295 92.7225) (end 54.61 91.0375) (width 1) (layer "F.Cu") (net 30) (tstamp fa8c1536-6c27-4f8c-8745-bb65b787d840))
+
+)
diff --git a/squeow_mod/fp-info-cache b/squeow_mod/fp-info-cache
new file mode 100644
index 0000000..13c2ebf
--- /dev/null
+++ b/squeow_mod/fp-info-cache
@@ -0,0 +1,435 @@
+103351009360878
+Resistor_SMD
+R_0201_0603Metric
+Resistor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator
+resistor
+0
+4
+2
+Resistor_SMD
+R_0201_0603Metric_Pad0.64x0.40mm_HandSolder
+Resistor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+4
+2
+Resistor_SMD
+R_0402_1005Metric
+Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0402_1005Metric_Pad0.72x0.64mm_HandSolder
+Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_0603_1608Metric
+Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0603_1608Metric_Pad0.98x0.95mm_HandSolder
+Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_0612_1632Metric
+Resistor SMD 0612 (1632 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0612_1632Metric_Pad1.18x3.40mm_HandSolder
+Resistor SMD 0612 (1632 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_0805_2012Metric
+Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0805_2012Metric_Pad1.20x1.40mm_HandSolder
+Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_0815_2038Metric
+Resistor SMD 0815 (2038 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.susumu.co.jp/common/pdf/n_catalog_partition07_en.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0815_2038Metric_Pad1.20x4.05mm_HandSolder
+Resistor SMD 0815 (2038 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.susumu.co.jp/common/pdf/n_catalog_partition07_en.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_01005_0402Metric
+Resistor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator
+resistor
+0
+4
+2
+Resistor_SMD
+R_01005_0402Metric_Pad0.57x0.30mm_HandSolder
+Resistor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+4
+2
+Resistor_SMD
+R_1020_2550Metric
+Resistor SMD 1020 (2550 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1020_2550Metric_Pad1.33x5.20mm_HandSolder
+Resistor SMD 1020 (2550 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1206_3216Metric
+Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1206_3216Metric_Pad1.30x1.75mm_HandSolder
+Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1210_3225Metric
+Resistor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1210_3225Metric_Pad1.30x2.65mm_HandSolder
+Resistor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1218_3246Metric
+Resistor SMD 1218 (3246 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20035/dcrcwe3.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1218_3246Metric_Pad1.22x4.75mm_HandSolder
+Resistor SMD 1218 (3246 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20035/dcrcwe3.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1812_4532Metric
+Resistor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1812_4532Metric_Pad1.30x3.40mm_HandSolder
+Resistor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_2010_5025Metric
+Resistor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_2010_5025Metric_Pad1.40x2.65mm_HandSolder
+Resistor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_2512_6332Metric
+Resistor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_2512_6332Metric_Pad1.40x3.35mm_HandSolder
+Resistor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_2816_7142Metric
+Resistor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_2816_7142Metric_Pad3.20x4.45mm_HandSolder
+Resistor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_4020_10251Metric
+Resistor SMD 4020 (10251 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://datasheet.octopart.com/HVC0603T5004FET-Ohmite-datasheet-26699797.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_4020_10251Metric_Pad1.65x5.30mm_HandSolder
+Resistor SMD 4020 (10251 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://datasheet.octopart.com/HVC0603T5004FET-Ohmite-datasheet-26699797.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_Array_Concave_2x0603
+Thick Film Chip Resistor Array, Wave soldering, Vishay CRA06P (see cra06p.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Concave_4x0402
+Thick Film Chip Resistor Array, Wave soldering, Vishay CRA04P (see cra04p.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Concave_4x0603
+Thick Film Chip Resistor Array, Wave soldering, Vishay CRA06P (see cra06p.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_2x0402
+Chip Resistor Network, ROHM MNR02 (see mnr_g.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Convex_2x0603
+Chip Resistor Network, ROHM MNR12 (see mnr_g.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Convex_2x0606
+Precision Thin Film Chip Resistor Array, VISHAY (see http://www.vishay.com/docs/28770/acasat.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Convex_2x1206
+Chip Resistor Network, ROHM MNR32 (see mnr_g.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Convex_4x0402
+Chip Resistor Network, ROHM MNR04 (see mnr_g.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_4x0603
+Chip Resistor Network, ROHM MNR14 (see mnr_g.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_4x0612
+Precision Thin Film Chip Resistor Array, VISHAY (see http://www.vishay.com/docs/28770/acasat.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_4x1206
+Chip Resistor Network, ROHM MNR34 (see mnr_g.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_5x0603
+Chip Resistor Network, ROHM MNR15 (see mnr_g.pdf)
+resistor array
+0
+10
+10
+Resistor_SMD
+R_Array_Convex_5x1206
+Chip Resistor Network, ROHM MNR35 (see mnr_g.pdf)
+resistor array
+0
+10
+10
+Resistor_SMD
+R_Array_Convex_8x0602
+Chip Resistor Network, ROHM MNR18 (see mnr_g.pdf)
+resistor array
+0
+16
+16
+Resistor_SMD
+R_Cat16-2
+SMT resistor net, Bourns CAT16 series, 2 way
+SMT resistor net Bourns CAT16 series 2 way
+0
+4
+4
+Resistor_SMD
+R_Cat16-4
+SMT resistor net, Bourns CAT16 series, 4 way
+SMT resistor net Bourns CAT16 series 4 way
+0
+8
+8
+Resistor_SMD
+R_Cat16-8
+SMT resistor net, Bourns CAT16 series, 8 way
+SMT resistor net Bourns CAT16 series 8 way
+0
+16
+16
+Resistor_SMD
+R_MELF_MMB-0207
+Resistor, MELF, MMB-0207, http://www.vishay.com/docs/28713/melfprof.pdf
+MELF Resistor
+0
+2
+2
+Resistor_SMD
+R_MicroMELF_MMU-0102
+Resistor, MicroMELF, MMU-0102, http://www.vishay.com/docs/28713/melfprof.pdf
+MicroMELF Resistor
+0
+2
+2
+Resistor_SMD
+R_MiniMELF_MMA-0204
+Resistor, MiniMELF, MMA-0204, http://www.vishay.com/docs/28713/melfprof.pdf
+MiniMELF Resistor
+0
+2
+2
+Resistor_SMD
+R_Shunt_Ohmite_LVK12
+4 contact shunt resistor
+shunt resistor 4 contacts
+0
+4
+4
+Resistor_SMD
+R_Shunt_Ohmite_LVK20
+4 contacts shunt resistor, https://www.ohmite.com/assets/docs/res_lvk.pdf
+4 contacts resistor smd
+0
+4
+4
+Resistor_SMD
+R_Shunt_Ohmite_LVK24
+4 contacts shunt resistor,https://www.ohmite.com/assets/docs/res_lvk.pdf
+4 contacts resistor smd
+0
+4
+4
+Resistor_SMD
+R_Shunt_Ohmite_LVK25
+4 contacts shunt resistor,https://www.ohmite.com/assets/docs/res_lvk.pdf
+4 contacts resistor smd
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSK2512_6332Metric_T1.19mm
+Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 1.19mm, 5 to 200 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf)
+resistor shunt WSK2512
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSK2512_6332Metric_T2.21mm
+Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 2.21mm, 1 to 4.9 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf)
+resistor shunt WSK2512
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSK2512_6332Metric_T2.66mm
+Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 2.66mm, 0.5 to 0.99 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf)
+resistor shunt WSK2512
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSKW0612
+https://www.vishay.com/docs/30332/wskw0612.pdf
+4-Terminal SMD Shunt
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSR2_WSR3
+Power Metal Strip Resistors 0.005 to 0.2, https://www.vishay.com/docs/30101/wsr.pdf
+SMD Shunt Resistor
+0
+2
+2
+Resistor_SMD
+R_Shunt_Vishay_WSR2_WSR3_KelvinConnection
+Power Metal Strip Resistors 0.005 to 0.2, https://www.vishay.com/docs/30101/wsr.pdf
+SMD Shunt Resistor
+0
+4
+2
diff --git a/squeow_mod/squeow_mod-B_Cu.gbr b/squeow_mod/squeow_mod-B_Cu.gbr
new file mode 100644
index 0000000..a6c9fd7
--- /dev/null
+++ b/squeow_mod/squeow_mod-B_Cu.gbr
@@ -0,0 +1,129 @@
+%TF.GenerationSoftware,KiCad,Pcbnew,7.0.5+dfsg-2*%
+%TF.CreationDate,2023-06-30T15:01:52+02:00*%
+%TF.ProjectId,squeow_mod,73717565-6f77-45f6-9d6f-642e6b696361,rev?*%
+%TF.SameCoordinates,PX2cce564PYfbec30*%
+%TF.FileFunction,Copper,L2,Bot*%
+%TF.FilePolarity,Positive*%
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 7.0.5+dfsg-2) date 2023-06-30 15:01:52*
+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+%TA.AperFunction,ComponentPad*%
+%ADD10O,2.000000X1.905000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD11R,2.000000X1.905000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD12O,1.700000X1.700000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD13R,1.700000X1.700000*%
+%TD*%
+G04 APERTURE END LIST*
+D10*
+%TO.P,D1,3,K*%
+%TO.N,Net-(C1-Pad2)*%
+X3977500Y-56515000D03*
+%TO.P,D1,2,A*%
+%TO.N,Net-(D1-Pad2)*%
+X3977500Y-59055000D03*
+D11*
+%TO.P,D1,1,K*%
+%TO.N,Net-(D1-Pad1)*%
+X3977500Y-61595000D03*
+%TD*%
+D10*
+%TO.P,Q3,3,S*%
+%TO.N,Net-(C3-Pad2)*%
+X3977500Y-24130000D03*
+%TO.P,Q3,2,D*%
+%TO.N,Net-(C2-Pad2)*%
+X3977500Y-26670000D03*
+D11*
+%TO.P,Q3,1,G*%
+%TO.N,Net-(Q3-Pad1)*%
+X3977500Y-29210000D03*
+%TD*%
+D10*
+%TO.P,D3,3,K*%
+%TO.N,Net-(C3-Pad2)*%
+X3977500Y-13335000D03*
+%TO.P,D3,2,A*%
+%TO.N,Net-(D3-Pad2)*%
+X3977500Y-15875000D03*
+D11*
+%TO.P,D3,1,K*%
+%TO.N,Net-(D2-Pad2)*%
+X3977500Y-18415000D03*
+%TD*%
+D10*
+%TO.P,D2,3,K*%
+%TO.N,Net-(C2-Pad2)*%
+X3977500Y-34925000D03*
+%TO.P,D2,2,A*%
+%TO.N,Net-(D2-Pad2)*%
+X3977500Y-37465000D03*
+D11*
+%TO.P,D2,1,K*%
+%TO.N,Net-(D1-Pad2)*%
+X3977500Y-40005000D03*
+%TD*%
+D12*
+%TO.P,J6,5,Pin_5*%
+%TO.N,Net-(J6-Pad5)*%
+X24137500Y-33655000D03*
+%TO.P,J6,4,Pin_4*%
+%TO.N,Net-(J6-Pad4)*%
+X24137500Y-36195000D03*
+%TO.P,J6,3,Pin_3*%
+%TO.N,Net-(J6-Pad3)*%
+X24137500Y-38735000D03*
+%TO.P,J6,2,Pin_2*%
+%TO.N,Net-(J6-Pad2)*%
+X24137500Y-41275000D03*
+D13*
+%TO.P,J6,1,Pin_1*%
+%TO.N,Net-(J6-Pad1)*%
+X24137500Y-43815000D03*
+%TD*%
+D10*
+%TO.P,Q1,3,S*%
+%TO.N,Net-(C1-Pad2)*%
+X3977500Y-67310000D03*
+%TO.P,Q1,2,D*%
+%TO.N,Net-(D1-Pad1)*%
+X3977500Y-69850000D03*
+D11*
+%TO.P,Q1,1,G*%
+%TO.N,Net-(Q1-Pad1)*%
+X3977500Y-72390000D03*
+%TD*%
+D10*
+%TO.P,Q2,3,S*%
+%TO.N,Net-(C2-Pad2)*%
+X3977500Y-45720000D03*
+%TO.P,Q2,2,D*%
+%TO.N,Net-(C1-Pad2)*%
+X3977500Y-48260000D03*
+D11*
+%TO.P,Q2,1,G*%
+%TO.N,Net-(Q2-Pad1)*%
+X3977500Y-50800000D03*
+%TD*%
+D10*
+%TO.P,Q4,3,S*%
+%TO.N,Net-(C4-Pad2)*%
+X3977500Y-2540000D03*
+%TO.P,Q4,2,D*%
+%TO.N,Net-(C3-Pad2)*%
+X3977500Y-5080000D03*
+D11*
+%TO.P,Q4,1,G*%
+%TO.N,Net-(Q4-Pad1)*%
+X3977500Y-7620000D03*
+%TD*%
+M02*
diff --git a/squeow_mod/squeow_mod-B_Mask.gbr b/squeow_mod/squeow_mod-B_Mask.gbr
new file mode 100644
index 0000000..2aafd4a
--- /dev/null
+++ b/squeow_mod/squeow_mod-B_Mask.gbr
@@ -0,0 +1,92 @@
+%TF.GenerationSoftware,KiCad,Pcbnew,7.0.5+dfsg-2*%
+%TF.CreationDate,2023-06-30T15:01:54+02:00*%
+%TF.ProjectId,squeow_mod,73717565-6f77-45f6-9d6f-642e6b696361,rev?*%
+%TF.SameCoordinates,PX2cce564PYfbec30*%
+%TF.FileFunction,Soldermask,Bot*%
+%TF.FilePolarity,Negative*%
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 7.0.5+dfsg-2) date 2023-06-30 15:01:54*
+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+%ADD10O,2.000000X1.905000*%
+%ADD11R,2.000000X1.905000*%
+%ADD12O,3.500000X3.500000*%
+%ADD13O,1.700000X1.700000*%
+%ADD14R,1.700000X1.700000*%
+G04 APERTURE END LIST*
+D10*
+%TO.C,D1*%
+X3977500Y-56515000D03*
+X3977500Y-59055000D03*
+D11*
+X3977500Y-61595000D03*
+D12*
+X-11822500Y-59055000D03*
+%TD*%
+D10*
+%TO.C,Q3*%
+X3977500Y-24130000D03*
+X3977500Y-26670000D03*
+D11*
+X3977500Y-29210000D03*
+D12*
+X-11822500Y-26670000D03*
+%TD*%
+D10*
+%TO.C,D3*%
+X3977500Y-13335000D03*
+X3977500Y-15875000D03*
+D11*
+X3977500Y-18415000D03*
+D12*
+X-11822500Y-15875000D03*
+%TD*%
+D10*
+%TO.C,D2*%
+X3977500Y-34925000D03*
+X3977500Y-37465000D03*
+D11*
+X3977500Y-40005000D03*
+D12*
+X-11822500Y-37465000D03*
+%TD*%
+D13*
+%TO.C,J6*%
+X24137500Y-33655000D03*
+X24137500Y-36195000D03*
+X24137500Y-38735000D03*
+X24137500Y-41275000D03*
+D14*
+X24137500Y-43815000D03*
+%TD*%
+D10*
+%TO.C,Q1*%
+X3977500Y-67310000D03*
+X3977500Y-69850000D03*
+D11*
+X3977500Y-72390000D03*
+D12*
+X-11822500Y-69850000D03*
+%TD*%
+D10*
+%TO.C,Q2*%
+X3977500Y-45720000D03*
+X3977500Y-48260000D03*
+D11*
+X3977500Y-50800000D03*
+D12*
+X-11822500Y-48260000D03*
+%TD*%
+D10*
+%TO.C,Q4*%
+X3977500Y-2540000D03*
+X3977500Y-5080000D03*
+D11*
+X3977500Y-7620000D03*
+D12*
+X-11822500Y-5080000D03*
+%TD*%
+M02*
diff --git a/squeow_mod/squeow_mod-B_Paste.gbr b/squeow_mod/squeow_mod-B_Paste.gbr
new file mode 100644
index 0000000..d20ef43
--- /dev/null
+++ b/squeow_mod/squeow_mod-B_Paste.gbr
@@ -0,0 +1,15 @@
+%TF.GenerationSoftware,KiCad,Pcbnew,7.0.5+dfsg-2*%
+%TF.CreationDate,2023-06-30T15:01:53+02:00*%
+%TF.ProjectId,squeow_mod,73717565-6f77-45f6-9d6f-642e6b696361,rev?*%
+%TF.SameCoordinates,PX2cce564PYfbec30*%
+%TF.FileFunction,Paste,Bot*%
+%TF.FilePolarity,Positive*%
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 7.0.5+dfsg-2) date 2023-06-30 15:01:53*
+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+G04 APERTURE END LIST*
+M02*
diff --git a/squeow_mod/squeow_mod-B_Silkscreen.gbr b/squeow_mod/squeow_mod-B_Silkscreen.gbr
new file mode 100644
index 0000000..d8f2894
--- /dev/null
+++ b/squeow_mod/squeow_mod-B_Silkscreen.gbr
@@ -0,0 +1,15 @@
+%TF.GenerationSoftware,KiCad,Pcbnew,7.0.5+dfsg-2*%
+%TF.CreationDate,2023-06-30T15:01:53+02:00*%
+%TF.ProjectId,squeow_mod,73717565-6f77-45f6-9d6f-642e6b696361,rev?*%
+%TF.SameCoordinates,PX2cce564PYfbec30*%
+%TF.FileFunction,Legend,Bot*%
+%TF.FilePolarity,Positive*%
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 7.0.5+dfsg-2) date 2023-06-30 15:01:53*
+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+G04 APERTURE END LIST*
+M02*
diff --git a/squeow_mod/squeow_mod-Edge_Cuts.gbr b/squeow_mod/squeow_mod-Edge_Cuts.gbr
new file mode 100644
index 0000000..274c56a
--- /dev/null
+++ b/squeow_mod/squeow_mod-Edge_Cuts.gbr
@@ -0,0 +1,23 @@
+%TF.GenerationSoftware,KiCad,Pcbnew,7.0.5+dfsg-2*%
+%TF.CreationDate,2023-06-30T15:01:54+02:00*%
+%TF.ProjectId,squeow_mod,73717565-6f77-45f6-9d6f-642e6b696361,rev?*%
+%TF.SameCoordinates,PX2cce564PYfbec30*%
+%TF.FileFunction,Profile,NP*%
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 7.0.5+dfsg-2) date 2023-06-30 15:01:54*
+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+%TA.AperFunction,Profile*%
+%ADD10C,0.100000*%
+%TD*%
+G04 APERTURE END LIST*
+D10*
+X0Y0D02*
+X26035000Y0D01*
+X26035000Y-79375000D01*
+X0Y-79375000D01*
+X0Y0D01*
+M02*
diff --git a/squeow_mod/squeow_mod-F_Cu.gbr b/squeow_mod/squeow_mod-F_Cu.gbr
new file mode 100644
index 0000000..ea3af7e
--- /dev/null
+++ b/squeow_mod/squeow_mod-F_Cu.gbr
@@ -0,0 +1,719 @@
+%TF.GenerationSoftware,KiCad,Pcbnew,7.0.5+dfsg-2*%
+%TF.CreationDate,2023-06-30T15:01:52+02:00*%
+%TF.ProjectId,squeow_mod,73717565-6f77-45f6-9d6f-642e6b696361,rev?*%
+%TF.SameCoordinates,PX2cce564PYfbec30*%
+%TF.FileFunction,Copper,L1,Top*%
+%TF.FilePolarity,Positive*%
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 7.0.5+dfsg-2) date 2023-06-30 15:01:52*
+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+G04 Aperture macros list*
+%AMRoundRect*
+0 Rectangle with rounded corners*
+0 $1 Rounding radius*
+0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
+0 Add a 4 corners polygon primitive as box body*
+4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
+0 Add four circle primitives for the rounded corners*
+1,1,$1+$1,$2,$3*
+1,1,$1+$1,$4,$5*
+1,1,$1+$1,$6,$7*
+1,1,$1+$1,$8,$9*
+0 Add four rect primitives between the rounded corners*
+20,1,$1+$1,$2,$3,$4,$5,0*
+20,1,$1+$1,$4,$5,$6,$7,0*
+20,1,$1+$1,$6,$7,$8,$9,0*
+20,1,$1+$1,$8,$9,$2,$3,0*%
+G04 Aperture macros list end*
+%TA.AperFunction,ComponentPad*%
+%ADD10O,2.000000X1.905000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD11R,2.000000X1.905000*%
+%TD*%
+%TA.AperFunction,SMDPad,CuDef*%
+%ADD12C,4.000000*%
+%TD*%
+%TA.AperFunction,SMDPad,CuDef*%
+%ADD13R,2.160000X0.640000*%
+%TD*%
+%TA.AperFunction,SMDPad,CuDef*%
+%ADD14RoundRect,0.250000X-0.400000X-0.625000X0.400000X-0.625000X0.400000X0.625000X-0.400000X0.625000X0*%
+%TD*%
+%TA.AperFunction,SMDPad,CuDef*%
+%ADD15RoundRect,0.250000X1.450000X-0.537500X1.450000X0.537500X-1.450000X0.537500X-1.450000X-0.537500X0*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD16O,1.700000X1.700000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD17R,1.700000X1.700000*%
+%TD*%
+%TA.AperFunction,SMDPad,CuDef*%
+%ADD18R,0.600000X0.450000*%
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+%ADD19RoundRect,0.250000X-0.400000X-1.450000X0.400000X-1.450000X0.400000X1.450000X-0.400000X1.450000X0*%
+%TD*%
+%TA.AperFunction,Conductor*%
+%ADD20C,1.000000*%
+%TD*%
+%TA.AperFunction,Conductor*%
+%ADD21C,2.000000*%
+%TD*%
+G04 APERTURE END LIST*
+D10*
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diff --git a/squeow_mod/squeow_mod-F_Mask.gbr b/squeow_mod/squeow_mod-F_Mask.gbr
new file mode 100644
index 0000000..e301865
--- /dev/null
+++ b/squeow_mod/squeow_mod-F_Mask.gbr
@@ -0,0 +1,234 @@
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+G04 Aperture macros list*
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+0 $1 Rounding radius*
+0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
+0 Add a 4 corners polygon primitive as box body*
+4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
+0 Add four circle primitives for the rounded corners*
+1,1,$1+$1,$2,$3*
+1,1,$1+$1,$4,$5*
+1,1,$1+$1,$6,$7*
+1,1,$1+$1,$8,$9*
+0 Add four rect primitives between the rounded corners*
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+G04 Aperture macros list end*
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diff --git a/squeow_mod/squeow_mod-F_Paste.gbr b/squeow_mod/squeow_mod-F_Paste.gbr
new file mode 100644
index 0000000..952413d
--- /dev/null
+++ b/squeow_mod/squeow_mod-F_Paste.gbr
@@ -0,0 +1,136 @@
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+%MOMM*%
+%LPD*%
+G01*
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+G04 Aperture macros list*
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+0 $1 Rounding radius*
+0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
+0 Add a 4 corners polygon primitive as box body*
+4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
+0 Add four circle primitives for the rounded corners*
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diff --git a/squeow_mod/squeow_mod-F_Silkscreen.gbr b/squeow_mod/squeow_mod-F_Silkscreen.gbr
new file mode 100644
index 0000000..face792
--- /dev/null
+++ b/squeow_mod/squeow_mod-F_Silkscreen.gbr
@@ -0,0 +1,1579 @@
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diff --git a/squeow_mod/squeow_mod-NPTH.drl b/squeow_mod/squeow_mod-NPTH.drl
new file mode 100644
index 0000000..b77741e
--- /dev/null
+++ b/squeow_mod/squeow_mod-NPTH.drl
@@ -0,0 +1,23 @@
+M48
+; DRILL file {KiCad 7.0.5+dfsg-2} date ven 30 giu 2023, 15:02:06
+; FORMAT={-:-/ absolute / inch / decimal}
+; #@! TF.CreationDate,2023-06-30T15:02:06+02:00
+; #@! TF.GenerationSoftware,Kicad,Pcbnew,7.0.5+dfsg-2
+; #@! TF.FileFunction,NonPlated,1,2,NPTH
+FMAT,2
+INCH
+; #@! TA.AperFunction,NonPlated,NPTH,ComponentDrill
+T1C0.1378
+%
+G90
+G05
+T1
+X-0.4655Y-0.2
+X-0.4655Y-0.625
+X-0.4655Y-1.05
+X-0.4655Y-1.475
+X-0.4655Y-1.9
+X-0.4655Y-2.325
+X-0.4655Y-2.75
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diff --git a/squeow_mod/squeow_mod-PTH.drl b/squeow_mod/squeow_mod-PTH.drl
new file mode 100644
index 0000000..0a88438
--- /dev/null
+++ b/squeow_mod/squeow_mod-PTH.drl
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+; FORMAT={-:-/ absolute / inch / decimal}
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2022-09-13_162503.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2022-09-13_162503.zip
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new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-11_223404.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-11_223404.zip
new file mode 100644
index 0000000000000000000000000000000000000000..3044fbf0cf8c3c3c222f2916182e55bae33ca107
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-11_224225.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-11_224225.zip
new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-11_225139.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-11_225139.zip
new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-13_011331.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-13_011331.zip
new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-13_012331.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-13_012331.zip
new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-13_013833.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-13_013833.zip
new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-13_014437.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-13_014437.zip
new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-13_015035.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-13_015035.zip
new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-15_134056.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2022-11-15_134056.zip
new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2023-03-15_222431.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2023-03-15_222431.zip
new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2023-06-30_111052.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2023-06-30_111052.zip
new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2023-06-30_120439.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2023-06-30_120439.zip
new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2023-06-30_121643.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2023-06-30_121643.zip
new file mode 100644
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diff --git a/squeow_mod/squeow_mod-backups/squeow_mod-2023-06-30_151038.zip b/squeow_mod/squeow_mod-backups/squeow_mod-2023-06-30_151038.zip
new file mode 100644
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HcmV?d00001

diff --git a/squeow_mod/squeow_mod-job.gbrjob b/squeow_mod/squeow_mod-job.gbrjob
new file mode 100644
index 0000000..a147860
--- /dev/null
+++ b/squeow_mod/squeow_mod-job.gbrjob
@@ -0,0 +1,125 @@
+{
+  "Header": {
+    "GenerationSoftware": {
+      "Vendor": "KiCad",
+      "Application": "Pcbnew",
+      "Version": "7.0.5+dfsg-2"
+    },
+    "CreationDate": "2023-06-30T15:01:54+02:00"
+  },
+  "GeneralSpecs": {
+    "ProjectId": {
+      "Name": "squeow_mod",
+      "GUID": "73717565-6f77-45f6-9d6f-642e6b696361",
+      "Revision": "rev?"
+    },
+    "Size": {
+      "X": 26.135,
+      "Y": 79.475
+    },
+    "LayerNumber": 2,
+    "BoardThickness": 1.6,
+    "Finish": "None"
+  },
+  "DesignRules": [
+    {
+      "Layers": "Outer",
+      "PadToPad": 0.25,
+      "PadToTrack": 0.25,
+      "TrackToTrack": 0.25,
+      "MinLineWidth": 1.0
+    }
+  ],
+  "FilesAttributes": [
+    {
+      "Path": "squeow_mod-F_Cu.gbr",
+      "FileFunction": "Copper,L1,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "squeow_mod-B_Cu.gbr",
+      "FileFunction": "Copper,L2,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "squeow_mod-F_Paste.gbr",
+      "FileFunction": "SolderPaste,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "squeow_mod-B_Paste.gbr",
+      "FileFunction": "SolderPaste,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "squeow_mod-F_Silkscreen.gbr",
+      "FileFunction": "Legend,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "squeow_mod-B_Silkscreen.gbr",
+      "FileFunction": "Legend,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "squeow_mod-F_Mask.gbr",
+      "FileFunction": "SolderMask,Top",
+      "FilePolarity": "Negative"
+    },
+    {
+      "Path": "squeow_mod-B_Mask.gbr",
+      "FileFunction": "SolderMask,Bot",
+      "FilePolarity": "Negative"
+    },
+    {
+      "Path": "squeow_mod-Edge_Cuts.gbr",
+      "FileFunction": "Profile",
+      "FilePolarity": "Positive"
+    }
+  ],
+  "MaterialStackup": [
+    {
+      "Type": "Legend",
+      "Name": "Top Silk Screen"
+    },
+    {
+      "Type": "SolderPaste",
+      "Name": "Top Solder Paste"
+    },
+    {
+      "Type": "SolderMask",
+      "Thickness": 0.01,
+      "Name": "Top Solder Mask"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.035,
+      "Name": "F.Cu"
+    },
+    {
+      "Type": "Dielectric",
+      "Thickness": 1.51,
+      "Material": "FR4",
+      "Name": "F.Cu/B.Cu",
+      "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.035,
+      "Name": "B.Cu"
+    },
+    {
+      "Type": "SolderMask",
+      "Thickness": 0.01,
+      "Name": "Bottom Solder Mask"
+    },
+    {
+      "Type": "SolderPaste",
+      "Name": "Bottom Solder Paste"
+    },
+    {
+      "Type": "Legend",
+      "Name": "Bottom Silk Screen"
+    }
+  ]
+}
diff --git a/squeow_mod/squeow_mod.kicad_pcb b/squeow_mod/squeow_mod.kicad_pcb
new file mode 100644
index 0000000..137ba25
--- /dev/null
+++ b/squeow_mod/squeow_mod.kicad_pcb
@@ -0,0 +1,1656 @@
+(kicad_pcb (version 20211014) (generator pcbnew)
+
+  (general
+    (thickness 1.6)
+  )
+
+  (paper "A4")
+  (layers
+    (0 "F.Cu" signal)
+    (31 "B.Cu" signal)
+    (32 "B.Adhes" user "B.Adhesive")
+    (33 "F.Adhes" user "F.Adhesive")
+    (34 "B.Paste" user)
+    (35 "F.Paste" user)
+    (36 "B.SilkS" user "B.Silkscreen")
+    (37 "F.SilkS" user "F.Silkscreen")
+    (38 "B.Mask" user)
+    (39 "F.Mask" user)
+    (40 "Dwgs.User" user "User.Drawings")
+    (41 "Cmts.User" user "User.Comments")
+    (42 "Eco1.User" user "User.Eco1")
+    (43 "Eco2.User" user "User.Eco2")
+    (44 "Edge.Cuts" user)
+    (45 "Margin" user)
+    (46 "B.CrtYd" user "B.Courtyard")
+    (47 "F.CrtYd" user "F.Courtyard")
+    (48 "B.Fab" user)
+    (49 "F.Fab" user)
+    (50 "User.1" user)
+    (51 "User.2" user)
+    (52 "User.3" user)
+    (53 "User.4" user)
+    (54 "User.5" user)
+    (55 "User.6" user)
+    (56 "User.7" user)
+    (57 "User.8" user)
+    (58 "User.9" user)
+  )
+
+  (setup
+    (stackup
+      (layer "F.SilkS" (type "Top Silk Screen"))
+      (layer "F.Paste" (type "Top Solder Paste"))
+      (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
+      (layer "F.Cu" (type "copper") (thickness 0.035))
+      (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
+      (layer "B.Cu" (type "copper") (thickness 0.035))
+      (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
+      (layer "B.Paste" (type "Bottom Solder Paste"))
+      (layer "B.SilkS" (type "Bottom Silk Screen"))
+      (copper_finish "None")
+      (dielectric_constraints no)
+    )
+    (pad_to_mask_clearance 0)
+    (pcbplotparams
+      (layerselection 0x00010fc_ffffffff)
+      (disableapertmacros false)
+      (usegerberextensions false)
+      (usegerberattributes true)
+      (usegerberadvancedattributes true)
+      (creategerberjobfile true)
+      (svguseinch false)
+      (svgprecision 6)
+      (excludeedgelayer true)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (dxfpolygonmode true)
+      (dxfimperialunits true)
+      (dxfusepcbnewfont true)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (sketchpadsonfab false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory "")
+    )
+  )
+
+  (net 0 "")
+  (net 1 "Net-(C1-Pad1)")
+  (net 2 "Net-(C1-Pad2)")
+  (net 3 "Net-(C2-Pad1)")
+  (net 4 "Net-(C2-Pad2)")
+  (net 5 "Net-(C3-Pad1)")
+  (net 6 "Net-(C3-Pad2)")
+  (net 7 "Net-(C4-Pad1)")
+  (net 8 "Net-(C4-Pad2)")
+  (net 9 "Net-(D1-Pad2)")
+  (net 10 "Net-(D2-Pad2)")
+  (net 11 "Net-(D3-Pad2)")
+  (net 12 "Net-(Q1-Pad1)")
+  (net 13 "Net-(Q3-Pad1)")
+  (net 14 "Net-(Q4-Pad1)")
+  (net 15 "unconnected-(U1-Pad2)")
+  (net 16 "GND")
+  (net 17 "unconnected-(U2-Pad2)")
+  (net 18 "unconnected-(U3-Pad2)")
+  (net 19 "unconnected-(U4-Pad2)")
+  (net 20 "Net-(Q2-Pad1)")
+  (net 21 "Net-(J6-Pad2)")
+  (net 22 "Net-(J6-Pad3)")
+  (net 23 "Net-(J6-Pad4)")
+  (net 24 "Net-(R1-Pad1)")
+  (net 25 "Net-(D1-Pad1)")
+  (net 26 "Net-(J6-Pad1)")
+  (net 27 "Net-(R2-Pad1)")
+  (net 28 "Net-(R3-Pad1)")
+  (net 29 "Net-(R4-Pad1)")
+  (net 30 "Net-(J6-Pad5)")
+
+  (footprint "Package_TO_SOT_THT:TO-220F-3_Horizontal_TabDown" (layer "F.Cu")
+    (tedit 5AC8BA0D) (tstamp 0134792b-1e2a-48a7-a29d-5d883dfcafa1)
+    (at 50.96 78.105 90)
+    (descr "TO-220F-3, Horizontal, RM 2.54mm, see http://www.st.com/resource/en/datasheet/stp20nm60.pdf")
+    (tags "TO-220F-3 Horizontal RM 2.54mm")
+    (property "Sheetfile" "squeow_mod.kicad_sch")
+    (property "Sheetname" "")
+    (path "/34aa2012-1c68-4d57-95ca-133c293530aa")
+    (attr through_hole)
+    (fp_text reference "D1" (at 2.54 -20.22 90) (layer "F.SilkS")
+      (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp e3cbea0c-3e3c-4c91-bd43-134aefdd0b3b)
+    )
+    (fp_text value "D_Schottky_x2_ACom_KAK" (at 2.54 2 90) (layer "F.Fab")
+      (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp b07c43bc-2dc9-40f9-b67c-733c12c28e89)
+    )
+    (fp_text user "${REFERENCE}" (at 2.54 -20.22 90) (layer "F.Fab")
+      (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp 5e18aa30-42c6-4779-b0a4-198e1d2e7920)
+    )
+    (fp_line (start -2.71 -19.22) (end -2.71 -3.11) (layer "F.SilkS") (width 0.12) (tstamp 1280474a-d464-4628-ac8a-ba042b748218))
+    (fp_line (start 2.54 -3.11) (end 2.54 -1.15) (layer "F.SilkS") (width 0.12) (tstamp 1e51a8eb-6b78-4968-8de7-1c5c6b641502))
+    (fp_line (start -2.71 -3.11) (end 7.79 -3.11) (layer "F.SilkS") (width 0.12) (tstamp 24384664-1687-4ac0-b427-039bea4352d1))
+    (fp_line (start -2.71 -19.22) (end 7.79 -19.22) (layer "F.SilkS") (width 0.12) (tstamp 2758f51d-88e4-4a26-84e9-468c10e23893))
+    (fp_line (start 5.08 -3.11) (end 5.08 -1.15) (layer "F.SilkS") (width 0.12) (tstamp 46bf5099-aec9-425d-8b68-7b96afaa808e))
+    (fp_line (start 0 -3.11) (end 0 -1.15) (layer "F.SilkS") (width 0.12) (tstamp 56c6d66b-7881-437d-bd78-ddbe778a837b))
+    (fp_line (start 7.79 -19.22) (end 7.79 -3.11) (layer "F.SilkS") (width 0.12) (tstamp f2734a8f-a8d8-4c8c-b519-ec774889b5c1))
+    (fp_line (start 7.92 -19.35) (end -2.84 -19.35) (layer "F.CrtYd") (width 0.05) (tstamp 37707259-b10d-4ea4-bb47-568b4aca40dd))
+    (fp_line (start -2.84 1.25) (end 7.92 1.25) (layer "F.CrtYd") (width 0.05) (tstamp 75a2c46e-9c38-482f-9172-eb3ab9aa58bd))
+    (fp_line (start -2.84 -19.35) (end -2.84 1.25) (layer "F.CrtYd") (width 0.05) (tstamp 9455c583-9e9d-48e5-8402-f710adc30ae9))
+    (fp_line (start 7.92 1.25) (end 7.92 -19.35) (layer "F.CrtYd") (width 0.05) (tstamp edb06c86-1504-4d02-80ea-e81f4b54a65b))
+    (fp_line (start -2.59 -12.42) (end -2.59 -19.1) (layer "F.Fab") (width 0.1) (tstamp 01db896a-4bda-4675-9782-46df674fb533))
+    (fp_line (start 7.67 -12.42) (end 7.67 -3.23) (layer "F.Fab") (width 0.1) (tstamp 0d2e892c-cb1d-436b-864e-0a7d83672a6e))
+    (fp_line (start 2.54 -3.23) (end 2.54 0) (layer "F.Fab") (width 0.1) (tstamp 1854b995-84f6-4b14-8acc-96ea4383d78f))
+    (fp_line (start -2.59 -3.23) (end -2.59 -12.42) (layer "F.Fab") (width 0.1) (tstamp 66d08652-6a53-4787-8021-6373e88d8726))
+    (fp_line (start -2.59 -19.1) (end 7.67 -19.1) (layer "F.Fab") (width 0.1) (tstamp 6d1443db-7dd1-4e9a-a04f-c6b98cb23bd6))
+    (fp_line (start -2.59 -12.42) (end 7.67 -12.42) (layer "F.Fab") (width 0.1) (tstamp 8b3e527d-8d66-4991-8d2b-1a8326be1a0d))
+    (fp_line (start 5.08 -3.23) (end 5.08 0) (layer "F.Fab") (width 0.1) (tstamp a2303ea9-3693-4829-a0a0-a961b59990ae))
+    (fp_line (start 7.67 -19.1) (end 7.67 -12.42) (layer "F.Fab") (width 0.1) (tstamp b1b0ba7c-8cf3-47b5-a767-3d16a01a6b79))
+    (fp_line (start 7.67 -12.42) (end -2.59 -12.42) (layer "F.Fab") (width 0.1) (tstamp bc94777e-87c2-4bf2-afd0-cbbf2a77260d))
+    (fp_line (start 7.67 -3.23) (end -2.59 -3.23) (layer "F.Fab") (width 0.1) (tstamp e2ca9b92-3f8c-489c-a05e-d7f325c8a050))
+    (fp_line (start 0 -3.23) (end 0 0) (layer "F.Fab") (width 0.1) (tstamp ecd04929-5506-4809-8eb1-c0236b3280e6))
+    (fp_circle (center 2.54 -15.8) (end 4.39 -15.8) (layer "F.Fab") (width 0.1) (fill none) (tstamp 6c382f61-70e9-4ffe-9fc0-93b057466a6f))
+    (pad "" np_thru_hole oval (at 2.54 -15.8 90) (size 3.5 3.5) (drill 3.5) (layers *.Cu *.Mask) (tstamp 5ad2c2ff-9091-4864-b93d-fa98dba663cc))
+    (pad "1" thru_hole rect (at 0 0 90) (size 1.905 2) (drill 1.2) (layers *.Cu *.Mask)
+      (net 25 "Net-(D1-Pad1)") (pinfunction "K") (pintype "passive") (tstamp 1fd42927-ed8d-4a5f-8eee-0e4e0bc7ab81))
+    (pad "2" thru_hole oval (at 2.54 0 90) (size 1.905 2) (drill 1.2) (layers *.Cu *.Mask)
+      (net 9 "Net-(D1-Pad2)") (pinfunction "A") (pintype "passive") (tstamp a0ff0e29-8c3d-4fdd-982b-49de8517f75a))
+    (pad "3" thru_hole oval (at 5.08 0 90) (size 1.905 2) (drill 1.2) (layers *.Cu *.Mask)
+      (net 2 "Net-(C1-Pad2)") (pinfunction "K") (pintype "passive") (tstamp 3543b231-1dc8-46db-b9ef-2708e19c1568))
+    (model "${KICAD6_3DMODEL_DIR}/Package_TO_SOT_THT.3dshapes/TO-220F-3_Horizontal_TabDown.wrl"
+      (offset (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (footprint "TestPoint:TestPoint_Pad_D4.0mm" (layer "F.Cu")
+    (tedit 5A0F774F) (tstamp 064ca189-16b6-4691-bae0-eb00c29e37cf)
+    (at 55 53.975)
+    (descr "SMD pad as test Point, diameter 4.0mm")
+    (tags "test point SMD pad")
+    (property "Sheetfile" "squeow_mod.kicad_sch")
+    (property "Sheetname" "")
+    (path "/6d3f0d01-965d-4fe9-a041-9c00fe7ab86b")
+    (attr exclude_from_pos_files)
+    (fp_text reference "J3" (at 0 -2.898) (layer "F.SilkS")
+      (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp 587963ac-a622-4e94-9962-d8b2f25a7a96)
+    )
+    (fp_text value "Vrail" (at 0 3.1) (layer "F.Fab")
+      (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp 2ef93c45-83c8-402b-8110-d5f21bd44c19)
+    )
+    (fp_text user "${REFERENCE}" (at 0 -2.9) (layer "F.Fab")
+      (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp 4528a258-c607-447b-b0b2-68270459cbba)
+    )
+    (fp_circle (center 0 0) (end 0 2.25) (layer "F.SilkS") (width 0.12) (fill none) (tstamp 7f2d40d6-f552-4c88-9613-243ecbbfee1b))
+    (fp_circle (center 0 0) (end 2.5 0) (layer "F.CrtYd") (width 0.05) (fill none) (tstamp 0dda22fd-1168-449d-a3e4-e726665405a8))
+    (pad "1" smd circle (at 0 0) (size 4 4) (layers "F.Cu" "F.Mask")
+      (net 10 "Net-(D2-Pad2)") (pinfunction "Pin_1") (pintype "passive") (tstamp 996b87b5-ad28-48c1-aaa7-866aa525fba3))
+  )
+
+  (footprint "Package_SO:SSO-6_6.8x4.6mm_P1.27mm_Clearance7mm" (layer "F.Cu")
+    (tedit 5A02F2D3) (tstamp 07180bcb-243a-4aa3-98f7-cd5e27d49a9b)
+    (at 62.23 45.72 180)
+    (descr "8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true")
+    (tags "SSO Stretched SO SOIC 1.27")
+    (property "Sheetfile" "squeow_mod.kicad_sch")
+    (property "Sheetname" "")
+    (path "/6b993f44-9809-4ab0-ba6c-69600c51226b")
+    (attr smd)
+    (fp_text reference "U3" (at 0.1 -3.265) (layer "F.SilkS")
+      (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp 0ffdcd23-190c-406f-8796-0231a5dfd359)
+    )
+    (fp_text value "UCC23313" (at 0.05 3.385) (layer "F.Fab")
+      (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp ba6844ba-c309-4d63-ad44-c6142c287819)
+    )
+    (fp_text user "${REFERENCE}" (at 0 -0.065) (layer "F.Fab")
+      (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp a20359b2-3903-4b7d-994d-75e249c0e4fa)
+    )
+    (fp_line (start 3.55 1.785) (end 3.55 2.435) (layer "F.SilkS") (width 0.12) (tstamp 086cf38f-cebe-4608-aa3a-795efa4f09a8))
+    (fp_line (start 3.5 -2.465) (end -3.55 -2.465) (layer "F.SilkS") (width 0.12) (tstamp 73473acb-0463-48a5-a4e3-52cbe6c5f522))
+    (fp_line (start -3.55 -2.465) (end -3.55 -1.815) (layer "F.SilkS") (width 0.12) (tstamp a7b61e43-73ee-4c3e-a9f9-65129227e7eb))
+    (fp_line (start -3.5 2.435) (end 3.55 2.435) (layer "F.SilkS") (width 0.12) (tstamp c42468f2-41db-4dab-8d69-fe2ce169151a))
+    (fp_line (start 3.5 -2.465) (end 3.5 -1.815) (layer "F.SilkS") (width 0.12) (tstamp cf9d9942-246a-43ac-bd78-d6da1eb40d5e))
+    (fp_line (start -3.55 -1.8) (end -5.3 -1.8) (layer "F.SilkS") (width 0.12) (tstamp e206c237-7925-4f31-b8cc-8b8aca5888cd))
+    (fp_line (start -3.5 1.785) (end -3.5 2.435) (layer "F.SilkS") (width 0.12) (tstamp ee427d55-6234-4f42-8cf8-aae144a13e4b))
+    (fp_line (start 5.6 2.54) (end 5.6 -2.56) (layer "F.CrtYd") (width 0.05) (tstamp 17a15af0-f872-40fb-a5f2-e02dfdf41b61))
+    (fp_line (start 5.6 2.54) (end -5.6 2.54) (layer "F.CrtYd") (width 0.05) (tstamp 298c1ff8-81ff-4cb9-bc3f-bc5c2de5fcd0))
+    (fp_line (start -5.6 -2.56) (end 5.6 -2.56) (layer "F.CrtYd") (width 0.05) (tstamp 3ae97d42-7742-47b1-9056-fda311838746))
+    (fp_line (start -5.6 -2.56) (end -5.6 2.54) (layer "F.CrtYd") (width 0.05) (tstamp 69c25bdf-e74c-4391-894e-4bee948851e1))
+    (fp_line (start 3.4 2.285) (end -3.4 2.285) (layer "F.Fab") (width 0.12) (tstamp 001d40bd-c4e0-4b9b-9bb3-d949110308aa))
+    (fp_line (start -3.4 2.285) (end -3.4 -1.265) (layer "F.Fab") (width 0.12) (tstamp 2812461e-5d71-45f0-8e69-c198ce3e4063))
+    (fp_line (start -2.3 -2.315) (end -3.4 -1.215) (layer "F.Fab") (width 0.12) (tstamp 6219c2a2-51a9-41cd-b60d-34f9d404254f))
+    (fp_line (start 3.4 -2.315) (end 3.4 2.285) (layer "F.Fab") (width 0.12) (tstamp 64b35d4c-fbf2-4452-a600-0d7287274968))
+    (fp_line (start 3.4 -2.315) (end -2.3 -2.315) (layer "F.Fab") (width 0.12) (tstamp a809f7eb-9c5e-453b-a414-6230b72e2b1b))
+    (pad "1" smd rect (at -4.27 -1.27 180) (size 2.16 0.64) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 28 "Net-(R3-Pad1)") (pinfunction "A") (pintype "passive") (tstamp 94d1693e-7c7c-4011-93c5-5217d3f06e03))
+    (pad "2" smd rect (at -4.27 0 180) (size 2.16 0.64) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 18 "unconnected-(U3-Pad2)") (pinfunction "NC") (pintype "no_connect") (tstamp af5a3493-bb45-4029-b7da-61c71b4a90f9))
+    (pad "3" smd rect (at -4.27 1.27 180) (size 2.16 0.64) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 16 "GND") (pinfunction "C") (pintype "passive") (tstamp 5dd065ba-351d-4405-b861-edaaf483efc5))
+    (pad "4" smd rect (at 4.27 1.27 180) (size 2.16 0.64) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 6 "Net-(C3-Pad2)") (pinfunction "VEE") (pintype "power_in") (tstamp 6d2ce772-cb84-4cbd-b63c-17a25ad069d0))
+    (pad "5" smd rect (at 4.27 0 180) (size 2.16 0.64) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 13 "Net-(Q3-Pad1)") (pinfunction "VO") (pintype "output") (tstamp 342a5963-ad54-4fd5-aa27-052e7364623d))
+    (pad "6" smd rect (at 4.27 -1.27 180) (size 2.16 0.64) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 5 "Net-(C3-Pad1)") (pinfunction "VCC") (pintype "power_in") (tstamp 0d5c140c-93cd-4671-ad98-e79c2c9e34e1))
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diff --git a/squeow_mod/squeow_mod.kicad_prl b/squeow_mod/squeow_mod.kicad_prl
new file mode 100644
index 0000000..5f44b09
--- /dev/null
+++ b/squeow_mod/squeow_mod.kicad_prl
@@ -0,0 +1,77 @@
+{
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+    "active_layer_preset": "",
+    "auto_track_width": false,
+    "hidden_netclasses": [],
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+    "high_contrast_mode": 0,
+    "net_color_mode": 1,
+    "opacity": {
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+      "tracks": 1.0,
+      "vias": 1.0,
+      "zones": 0.6
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+    "ratsnest_display_mode": 0,
+    "selection_filter": {
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+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": true,
+      "otherItems": true,
+      "pads": true,
+      "text": true,
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+      "vias": true,
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+}
diff --git a/squeow_mod/squeow_mod.kicad_pro b/squeow_mod/squeow_mod.kicad_pro
new file mode 100644
index 0000000..4ce2c49
--- /dev/null
+++ b/squeow_mod/squeow_mod.kicad_pro
@@ -0,0 +1,454 @@
+{
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diff --git a/squeow_mod/squeow_mod.kicad_sch b/squeow_mod/squeow_mod.kicad_sch
new file mode 100644
index 0000000..e1babc2
--- /dev/null
+++ b/squeow_mod/squeow_mod.kicad_sch
@@ -0,0 +1,2270 @@
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diff --git a/squeow_sw/.mxproject b/squeow_sw/.mxproject
new file mode 100644
index 0000000..9368a17
--- /dev/null
+++ b/squeow_sw/.mxproject
@@ -0,0 +1,14 @@
+[PreviousLibFiles]
+LibFiles=Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_i2c.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_i2c.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm7.h;
+
+[PreviousUsedMakefileFiles]
+SourceFiles=Src/main.c;Src/usb_device.c;Src/usbd_conf.c;Src/usbd_desc.c;Src/usbd_audio_if.c;Src/stm32g4xx_it.c;Src/stm32g4xx_hal_msp.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Src/system_stm32g4xx.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Src/system_stm32g4xx.c;;;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c;
+HeaderPath=Drivers/STM32G4xx_HAL_Driver/Inc;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy;Middlewares/ST/STM32_USB_Device_Library/Core/Inc;Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc;Drivers/CMSIS/Device/ST/STM32G4xx/Include;Drivers/CMSIS/Include;Inc;
+CDefines=USE_HAL_DRIVER;STM32G431xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[PreviousGenFiles]
+HeaderPath=../Inc
+HeaderFiles=usb_device.h;usbd_conf.h;usbd_desc.h;usbd_audio_if.h;stm32g4xx_it.h;stm32g4xx_hal_conf.h;main.h;
+SourcePath=../Src
+SourceFiles=usb_device.c;usbd_conf.c;usbd_desc.c;usbd_audio_if.c;stm32g4xx_it.c;stm32g4xx_hal_msp.c;main.c;
+
diff --git a/squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h b/squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h
new file mode 100644
index 0000000..7e3265d
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h
@@ -0,0 +1,13139 @@
+/**
+  ******************************************************************************
+  * @file    stm32g431xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32G431xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32g431xx
+  * @{
+  */
+
+#ifndef __STM32G431xx_H
+#define __STM32G431xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+   */
+#define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1U       /*!< STM32G4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4U       /*!< STM32G4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32G4XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                                 */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                                   */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                                            */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                                    */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                                  */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                                     */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                                               */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                                     */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                                 */
+/******  STM32 specific Interrupt Numbers ***************************************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                                          */
+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts                     */
+  RTC_TAMP_LSECSS_IRQn        = 2,      /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI               */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                                         */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                                             */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                                               */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                                               */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                                               */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                                               */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                                               */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                                               */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                                    */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                                    */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                                    */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                                    */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                                    */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                                    */
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                                                     */
+  USB_HP_IRQn                 = 19,     /*!< USB HP Interrupt                                                                   */
+  USB_LP_IRQn                 = 20,     /*!< USB LP  Interrupt                                                                  */
+  FDCAN1_IT0_IRQn             = 21,     /*!< FDCAN1 IT0 Interrupt                                                               */
+  FDCAN1_IT1_IRQn             = 22,     /*!< FDCAN1 IT1 Interrupt                                                               */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                                      */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt               */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                                   */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                                     */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                                              */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                                              */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                                              */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                                               */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                                               */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                                               */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                                               */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                                              */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                                              */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                                            */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                                            */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                                            */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                                    */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                                    */
+  USBWakeUp_IRQn              = 42,     /*!< USB Wakeup through EXTI line Interrupt                                             */
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break, Transition error and Index error Interrupt                             */
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                                              */
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt                    */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                                     */
+  LPTIM1_IRQn                 = 49,     /*!< LP TIM1 Interrupt                                                                  */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                                              */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                                             */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&3 underrun error  interrupts                                  */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupts                                                             */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                                    */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                                    */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                                    */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                                    */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                                    */
+  UCPD1_IRQn                  = 63,     /*!< UCPD global Interrupt                                                              */
+  COMP1_2_3_IRQn              = 64,     /*!< COMP1, COMP2 and COMP3 Interrupts                                                  */
+  COMP4_IRQn                  = 65,     /*!< COMP4                                                                              */
+  CRS_IRQn                    = 75,     /*!< CRS global interrupt                                                               */
+  SAI1_IRQn                   = 76,     /*!< Serial Audio Interface global interrupt                                            */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                                               */
+  RNG_IRQn                    = 90,     /*!< RNG global interrupt                                                               */
+  LPUART1_IRQn                = 91,     /*!< LP UART 1 Interrupt                                                                */
+  I2C3_EV_IRQn                = 92,     /*!< I2C3 Event Interrupt                                                               */
+  I2C3_ER_IRQn                = 93,     /*!< I2C3 Error interrupt                                                               */
+  DMAMUX_OVR_IRQn             = 94,     /*!< DMAMUX overrun global interrupt                                                    */
+  DMA2_Channel6_IRQn          = 97,     /*!< DMA2 Channel 6 interrupt                                                           */
+  CORDIC_IRQn                 = 100,    /*!< CORDIC global Interrupt                                                            */
+  FMAC_IRQn                   = 101     /*!< FMAC global Interrupt                                                              */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32g4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
+  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
+  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
+  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
+  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
+  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
+       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
+  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
+  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
+  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
+       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
+  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
+  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
+  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
+  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
+  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
+       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
+       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
+  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
+       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
+  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
+  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
+  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
+  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
+       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
+  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
+  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
+  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
+  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
+       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
+  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
+       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
+       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
+  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
+  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
+       uint32_t RESERVED10[2];/*!< Reserved,                                             0x0B8 - 0x0BC */
+  __IO uint32_t GCOMP;        /*!< ADC calibration factors,                       Address offset: 0xC0 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< ADC common status register,            Address offset: 0x300 + 0x00 */
+  uint32_t      RESERVED1;    /*!< Reserved,                              Address offset: 0x300 + 0x04 */
+  __IO uint32_t CCR;          /*!< ADC common configuration register,     Address offset: 0x300 + 0x08 */
+  __IO uint32_t CDR;          /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
+       uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
+       uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
+       uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
+       uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
+  __IO uint32_t RXGFC;        /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x084 */
+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x088 */
+       uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x090 */
+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x094 */
+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x098 */
+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x09C */
+       uint32_t RESERVED6[8]; /*!< Reserved,                                                                0x0A0 - 0x0BC */
+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0C8 */
+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0CC */
+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D0 */
+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D4 */
+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0D8 */
+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0E4 */
+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0E8 */
+} FDCAN_GlobalTypeDef;
+
+/**
+  * @brief FD Controller Area Network Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t CKDIV;        /*!< FDCAN clock divider register,                            Address offset: 0x100 + 0x000 */
+} FDCAN_Config_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED0;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< CRS ccontrol register,              Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< CRS configuration register,         Address offset: 0x04 */
+  __IO uint32_t ISR;         /*!< CRS interrupt and status register,  Address offset: 0x08 */
+  __IO uint32_t ICR;         /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+  __IO uint32_t RESERVED[2];
+  __IO uint32_t STR1;        /*!< DAC Sawtooth register,                                   Address offset: 0x58 */
+  __IO uint32_t STR2;        /*!< DAC Sawtooth register,                                   Address offset: 0x5C */
+  __IO uint32_t STMODR;      /*!< DAC Sawtooth Mode register,                              Address offset: 0x60 */
+} DAC_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
+  __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
+  __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
+  __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
+  __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
+} DBGMCU_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
+  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
+  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
+  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
+  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+  * @brief DMA Multiplexer
+  */
+
+typedef struct
+{
+  __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
+}DMAMUX_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t   CSR;      /*!< DMA Channel Status Register                    Address offset: 0x0080   */
+  __IO uint32_t   CFR;      /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
+}DMAMUX_ChannelStatus_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
+}DMAMUX_RequestGen_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
+  __IO uint32_t   RGCFR;        /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
+}DMAMUX_RequestGenStatus_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
+  __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
+  __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
+  __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
+  __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
+  __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
+  uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
+  __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
+  __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
+  __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
+  __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
+  __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
+  __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
+} EXTI_TypeDef;
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
+  __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
+  __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
+  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
+  __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
+  __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
+  __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
+       uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
+  __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
+  __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
+  __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
+  __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
+  __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
+       uint32_t RESERVED2[15];    /*!< Reserved2,                                Address offset: 0x34 */
+  __IO uint32_t SEC1R;            /*!< FLASH Securable memory register bank1,    Address offset: 0x70 */
+} FLASH_TypeDef;
+
+/**
+  * @brief FMAC
+  */
+typedef struct
+{
+  __IO uint32_t X1BUFCFG;        /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00          */
+  __IO uint32_t X2BUFCFG;        /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04          */
+  __IO uint32_t YBUFCFG;         /*!< FMAC Y Buffer Configuration register,  Address offset: 0x08          */
+  __IO uint32_t PARAM;           /*!< FMAC Parameter register,               Address offset: 0x0C          */
+  __IO uint32_t CR;              /*!< FMAC Control register,                 Address offset: 0x10          */
+  __IO uint32_t SR;              /*!< FMAC Status register,                  Address offset: 0x14          */
+  __IO uint32_t WDATA;           /*!< FMAC Write Data register,              Address offset: 0x18          */
+  __IO uint32_t RDATA;           /*!< FMAC Read Data register,               Address offset: 0x1C          */
+} FMAC_TypeDef;
+
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
+  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
+} GPIO_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief LPTIMER
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;              /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
+  __IO uint32_t ICR;              /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
+  __IO uint32_t IER;              /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
+  __IO uint32_t CFGR;             /*!< LPTIM Configuration register,                       Address offset: 0x0C */
+  __IO uint32_t CR;               /*!< LPTIM Control register,                             Address offset: 0x10 */
+  __IO uint32_t CMP;              /*!< LPTIM Compare register,                             Address offset: 0x14 */
+  __IO uint32_t ARR;              /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
+  __IO uint32_t CNT;              /*!< LPTIM Counter register,                             Address offset: 0x1C */
+  __IO uint32_t OR;               /*!< LPTIM Option register,                              Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;           /*!< OPAMP control/status register,                     Address offset: 0x00 */
+  __IO uint32_t RESERVED[5];   /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
+  __IO uint32_t TCMR;          /*!< OPAMP timer controlled mux mode register,          Address offset: 0x18 */
+} OPAMP_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< PWR power control register 1,        Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< PWR power control register 2,        Address offset: 0x04 */
+  __IO uint32_t CR3;      /*!< PWR power control register 3,        Address offset: 0x08 */
+  __IO uint32_t CR4;      /*!< PWR power control register 4,        Address offset: 0x0C */
+  __IO uint32_t SR1;      /*!< PWR power status register 1,         Address offset: 0x10 */
+  __IO uint32_t SR2;      /*!< PWR power status register 2,         Address offset: 0x14 */
+  __IO uint32_t SCR;      /*!< PWR power status reset register,     Address offset: 0x18 */
+  uint32_t RESERVED;      /*!< Reserved,                            Address offset: 0x1C */
+  __IO uint32_t PUCRA;    /*!< Pull_up control register of portA,   Address offset: 0x20 */
+  __IO uint32_t PDCRA;    /*!< Pull_Down control register of portA, Address offset: 0x24 */
+  __IO uint32_t PUCRB;    /*!< Pull_up control register of portB,   Address offset: 0x28 */
+  __IO uint32_t PDCRB;    /*!< Pull_Down control register of portB, Address offset: 0x2C */
+  __IO uint32_t PUCRC;    /*!< Pull_up control register of portC,   Address offset: 0x30 */
+  __IO uint32_t PDCRC;    /*!< Pull_Down control register of portC, Address offset: 0x34 */
+  __IO uint32_t PUCRD;    /*!< Pull_up control register of portD,   Address offset: 0x38 */
+  __IO uint32_t PDCRD;    /*!< Pull_Down control register of portD, Address offset: 0x3C */
+  __IO uint32_t PUCRE;    /*!< Pull_up control register of portE,   Address offset: 0x40 */
+  __IO uint32_t PDCRE;    /*!< Pull_Down control register of portE, Address offset: 0x44 */
+  __IO uint32_t PUCRF;    /*!< Pull_up control register of portF,   Address offset: 0x48 */
+  __IO uint32_t PDCRF;    /*!< Pull_Down control register of portF, Address offset: 0x4C */
+  __IO uint32_t PUCRG;    /*!< Pull_up control register of portG,   Address offset: 0x50 */
+  __IO uint32_t PDCRG;    /*!< Pull_Down control register of portG, Address offset: 0x54 */
+  uint32_t RESERVED1[10]; /*!< Reserved                             Address offset: 0x58 - 0x7C */
+  __IO uint32_t CR5;      /*!< PWR power control register 5,        Address offset: 0x80 */
+} PWR_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
+  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
+  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
+  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
+  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x10 */
+  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x14 */
+  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
+  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
+  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x24 */
+  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
+  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
+  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
+  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x34 */
+  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
+  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
+  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
+  uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x44 */
+  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
+  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
+  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
+  uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x54 */
+  __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
+  __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
+  __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
+  uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x64 */
+  __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
+  __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
+  __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
+  uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x74 */
+  __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
+  __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
+  __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
+  uint32_t      RESERVED8;   /*!< Reserved,                                                                Address offset: 0x84 */
+  __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
+  uint32_t      RESERVED9;   /*!< Reserved,                                                                Address offset: 0x8C */
+  __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
+  __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
+  __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
+  __IO uint32_t CCIPR2;      /*!< RCC peripherals independent clock configuration register 2,              Address offset: 0x9C */
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMP_INT_6_SUPPORT
+#define RTC_TAMP_INT_NB        4u
+
+#define RTC_TAMP_NB            3u
+#define RTC_BACKUP_NB          16u
+
+
+typedef struct
+{
+  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x08 */
+  __IO uint32_t ICSR;        /*!< RTC initialization control and status register,            Address offset: 0x0C */
+  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x18 */
+       uint32_t RESERVED0;   /*!< Reserved                                                   Address offset: 0x1C */
+       uint32_t RESERVED1;   /*!< Reserved                                                   Address offset: 0x20 */
+  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+       uint32_t RESERVED2;   /*!< Reserved                                                   Address offset: 0x3C */
+  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x48 */
+  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x4C */
+  __IO uint32_t SR;          /*!< RTC Status register,                                       Address offset: 0x50 */
+  __IO uint32_t MISR;        /*!< RTC Masked Interrupt Status register,                      Address offset: 0x54 */
+       uint32_t RESERVED3;   /*!< Reserved                                                   Address offset: 0x58 */
+  __IO uint32_t SCR;         /*!< RTC Status Clear register,                                 Address offset: 0x5C */
+} RTC_TypeDef;
+
+/**
+  * @brief Tamper and backup registers
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;                     /*!< TAMP configuration register 1,          Address offset: 0x00 */
+  __IO uint32_t CR2;                     /*!< TAMP configuration register 2,          Address offset: 0x04 */
+       uint32_t RESERVED0;               /*!< no configuration register 3,            Address offset: 0x08 */
+  __IO uint32_t FLTCR;                   /*!< TAMP filter control register,           Address offset: 0x0C */
+       uint32_t RESERVED1[6];            /*!< Reserved                                Address offset: 0x10 - 0x24 */
+       uint32_t RESERVED2;               /*!< Reserved                                Address offset: 0x28 */
+  __IO uint32_t IER;                     /*!< TAMP Interrupt enable register,         Address offset: 0x2C */
+  __IO uint32_t SR;                      /*!< TAMP Status register,                   Address offset: 0x30 */
+  __IO uint32_t MISR;                    /*!< TAMP Masked Interrupt Status register   Address offset: 0x34 */
+       uint32_t RESERVED3;               /*!< Reserved                                Address offset: 0x38 */
+  __IO uint32_t SCR;                     /*!< TAMP Status clear register,             Address offset: 0x3C */
+       uint32_t RESERVED4[48];           /*!< Reserved                                Address offset: 0x040 - 0xFC */
+  __IO uint32_t BKP0R;                   /*!< TAMP backup register 0,                 Address offset: 0x100 */
+  __IO uint32_t BKP1R;                   /*!< TAMP backup register 1,                 Address offset: 0x104 */
+  __IO uint32_t BKP2R;                   /*!< TAMP backup register 2,                 Address offset: 0x108 */
+  __IO uint32_t BKP3R;                   /*!< TAMP backup register 3,                 Address offset: 0x10C */
+  __IO uint32_t BKP4R;                   /*!< TAMP backup register 4,                 Address offset: 0x110 */
+  __IO uint32_t BKP5R;                   /*!< TAMP backup register 5,                 Address offset: 0x114 */
+  __IO uint32_t BKP6R;                   /*!< TAMP backup register 6,                 Address offset: 0x118 */
+  __IO uint32_t BKP7R;                   /*!< TAMP backup register 7,                 Address offset: 0x11C */
+  __IO uint32_t BKP8R;                   /*!< TAMP backup register 8,                 Address offset: 0x120 */
+  __IO uint32_t BKP9R;                   /*!< TAMP backup register 9,                 Address offset: 0x124 */
+  __IO uint32_t BKP10R;                  /*!< TAMP backup register 10,                Address offset: 0x128 */
+  __IO uint32_t BKP11R;                  /*!< TAMP backup register 11,                Address offset: 0x12C */
+  __IO uint32_t BKP12R;                  /*!< TAMP backup register 12,                Address offset: 0x130 */
+  __IO uint32_t BKP13R;                  /*!< TAMP backup register 13,                Address offset: 0x134 */
+  __IO uint32_t BKP14R;                  /*!< TAMP backup register 14,                Address offset: 0x138 */
+  __IO uint32_t BKP15R;                  /*!< TAMP backup register 15,                Address offset: 0x13C */
+} TAMP_TypeDef;
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;          /*!< SAI global configuration register,        Address offset: 0x00 */
+  uint32_t      RESERVED[16]; /*!< Reserved,                         Address offset: 0x04 to 0x40 */
+  __IO uint32_t PDMCR;        /*!< SAI PDM control register,                 Address offset: 0x44 */
+  __IO uint32_t PDMDLY;       /*!< SAI PDM delay register,                   Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
+  __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
+  __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
+  __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
+  __IO uint32_t I2SCFGR;     /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+  __IO uint32_t I2SPR;       /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                        Address offset: 0x00      */
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers,   Address offset: 0x08-0x14 */
+  __IO uint32_t SCSR;        /*!< SYSCFG CCMSRAM control and status register,          Address offset: 0x18      */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                     Address offset: 0x1C      */
+  __IO uint32_t SWPR;        /*!< SYSCFG CCMSRAM write protection register,            Address offset: 0x20      */
+  __IO uint32_t SKR;         /*!< SYSCFG CCMSRAM Key Register,                         Address offset: 0x24      */
+} SYSCFG_TypeDef;
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register 5,           Address offset: 0x48 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register 6,           Address offset: 0x4C */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x50 */
+  __IO uint32_t DTR2;        /*!< TIM deadtime register 2,                  Address offset: 0x54 */
+  __IO uint32_t ECR;         /*!< TIM encoder control register,             Address offset: 0x58 */
+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x5C */
+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
+  __IO uint32_t OR ;         /*!< TIM option register,                      Address offset: 0x68 */
+       uint32_t RESERVED0[220];/*!< Reserved,                               Address offset: 0x6C */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x3DC */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
+} TIM_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
+  __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
+  __IO uint32_t RTOR;        /*!< USART Receiver Timeout register,          Address offset: 0x14  */
+  __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
+  __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
+  __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
+  __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
+} USART_TypeDef;
+
+/**
+  * @brief Universal Serial Bus Full Speed Device
+  */
+
+typedef struct
+{
+  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */
+  __IO uint16_t RESERVED0;       /*!< Reserved */
+  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
+  __IO uint16_t RESERVED1;       /*!< Reserved */
+  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
+  __IO uint16_t RESERVED2;       /*!< Reserved */
+  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */
+  __IO uint16_t RESERVED3;       /*!< Reserved */
+  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
+  __IO uint16_t RESERVED4;       /*!< Reserved */
+  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
+  __IO uint16_t RESERVED5;       /*!< Reserved */
+  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
+  __IO uint16_t RESERVED6;       /*!< Reserved */
+  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
+  __IO uint16_t RESERVED7[17];   /*!< Reserved */
+  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
+  __IO uint16_t RESERVED8;       /*!< Reserved */
+  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
+  __IO uint16_t RESERVED9;       /*!< Reserved */
+  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
+  __IO uint16_t RESERVEDA;       /*!< Reserved */
+  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
+  __IO uint16_t RESERVEDB;       /*!< Reserved */
+  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
+  __IO uint16_t RESERVEDC;       /*!< Reserved */
+  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
+  __IO uint16_t RESERVEDD;       /*!< Reserved */
+  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
+  __IO uint16_t RESERVEDE;       /*!< Reserved */
+} USB_TypeDef;
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+  * @brief RNG
+  */
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @brief CORDIC
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< CORDIC control and status register,        Address offset: 0x00 */
+  __IO uint32_t WDATA;        /*!< CORDIC argument register,                  Address offset: 0x04 */
+  __IO uint32_t RDATA;        /*!< CORDIC result register,                    Address offset: 0x08 */
+} CORDIC_TypeDef;
+
+/**
+  * @brief UCPD
+  */
+
+typedef struct
+{
+  __IO uint32_t CFG1;          /*!< UCPD configuration register 1,             Address offset: 0x00 */
+  __IO uint32_t CFG2;          /*!< UCPD configuration register 2,             Address offset: 0x04 */
+  __IO uint32_t RESERVED0;     /*!< UCPD reserved register,                    Address offset: 0x08 */
+  __IO uint32_t CR;            /*!< UCPD control register,                     Address offset: 0x0C */
+  __IO uint32_t IMR;           /*!< UCPD interrupt mask register,              Address offset: 0x10 */
+  __IO uint32_t SR;            /*!< UCPD status register,                      Address offset: 0x14 */
+  __IO uint32_t ICR;           /*!< UCPD interrupt flag clear register         Address offset: 0x18 */
+  __IO uint32_t TX_ORDSET;     /*!< UCPD Tx ordered set type register,         Address offset: 0x1C */
+  __IO uint32_t TX_PAYSZ;      /*!< UCPD Tx payload size register,             Address offset: 0x20 */
+  __IO uint32_t TXDR;          /*!< UCPD Tx data register,                     Address offset: 0x24 */
+  __IO uint32_t RX_ORDSET;     /*!< UCPD Rx ordered set type register,         Address offset: 0x28 */
+  __IO uint32_t RX_PAYSZ;      /*!< UCPD Rx payload size register,             Address offset: 0x2C */
+  __IO uint32_t RXDR;          /*!< UCPD Rx data register,                     Address offset: 0x30 */
+  __IO uint32_t RX_ORDEXT1;    /*!< UCPD Rx ordered set extension 1 register,  Address offset: 0x34 */
+  __IO uint32_t RX_ORDEXT2;    /*!< UCPD Rx ordered set extension 2 register,  Address offset: 0x38 */
+} UCPD_TypeDef;
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            (0x08000000UL) /*!< FLASH (up to 128 kB) base address */
+#define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */
+#define SRAM2_BASE            (0x20004000UL) /*!< SRAM2(6 KB) base address */
+#define CCMSRAM_BASE          (0x10000000UL) /*!< CCMSRAM(10 KB) base address */
+#define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */
+
+#define SRAM1_BB_BASE         (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE         (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */
+#define CCMSRAM_BB_BASE       (0x220B0000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE        (0x42000000UL) /*!< Peripheral base address in the bit-band region */
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+#define SRAM1_SIZE_MAX        (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */
+#define SRAM2_SIZE            (0x00001800UL) /*!< SRAM2 size (6 KBytes) */
+#define CCMSRAM_SIZE          (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
+
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
+#define CRS_BASE              (APB1PERIPH_BASE + 0x2000UL)
+#define TAMP_BASE             (APB1PERIPH_BASE + 0x2400UL)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
+#define USB_BASE              (APB1PERIPH_BASE + 0x5C00UL)  /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR           (APB1PERIPH_BASE + 0x6000UL)  /*!< USB_IP Packet Memory Area base address */
+#define FDCAN1_BASE           (APB1PERIPH_BASE + 0x6400UL)
+#define FDCAN_CONFIG_BASE     (APB1PERIPH_BASE + 0x6500UL)  /*!< FDCAN configuration registers base address */
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x7800UL)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
+#define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
+#define UCPD1_BASE            (APB1PERIPH_BASE + 0xA000UL)
+#define SRAMCAN_BASE          (APB1PERIPH_BASE + 0xA400UL)
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
+#define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030UL)
+#define COMP1_BASE            (APB2PERIPH_BASE + 0x0200UL)
+#define COMP2_BASE            (APB2PERIPH_BASE + 0x0204UL)
+#define COMP3_BASE            (APB2PERIPH_BASE + 0x0208UL)
+#define COMP4_BASE            (APB2PERIPH_BASE + 0x020CUL)
+#define OPAMP_BASE            (APB2PERIPH_BASE + 0x0300UL)
+#define OPAMP1_BASE           (APB2PERIPH_BASE + 0x0300UL)
+#define OPAMP2_BASE           (APB2PERIPH_BASE + 0x0304UL)
+#define OPAMP3_BASE           (APB2PERIPH_BASE + 0x0308UL)
+
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400UL)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800UL)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5400UL)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE             (AHB1PERIPH_BASE)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
+#define DMAMUX1_BASE          (AHB1PERIPH_BASE + 0x0800UL)
+#define CORDIC_BASE           (AHB1PERIPH_BASE + 0x0C00UL)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
+#define FMAC_BASE             (AHB1PERIPH_BASE + 0x1400UL)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
+
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
+
+#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
+#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
+#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
+#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
+#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
+#define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
+
+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0020UL)
+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x0024UL)
+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0028UL)
+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x002CUL)
+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0030UL)
+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x0034UL)
+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
+
+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800UL)
+
+#define ADC1_BASE             (AHB2PERIPH_BASE + 0x08000000UL)
+#define ADC2_BASE             (AHB2PERIPH_BASE + 0x08000100UL)
+#define ADC12_COMMON_BASE     (AHB2PERIPH_BASE + 0x08000300UL)
+
+#define DAC_BASE              (AHB2PERIPH_BASE + 0x08000800UL)
+#define DAC1_BASE             (AHB2PERIPH_BASE + 0x08000800UL)
+#define DAC3_BASE             (AHB2PERIPH_BASE + 0x08001000UL)
+
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           (0xE0042000UL)
+
+#define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */
+#define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define USB                 ((USB_TypeDef *) USB_BASE)
+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
+#define FDCAN_CONFIG        ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define UCPD1              ((UCPD_TypeDef *) UCPD1_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP3               ((COMP_TypeDef *) COMP3_BASE)
+#define COMP4               ((COMP_TypeDef *) COMP4_BASE)
+
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP3              ((OPAMP_TypeDef *) OPAMP3_BASE)
+
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMAMUX1             ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
+#define CORDIC              ((CORDIC_TypeDef *) CORDIC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FMAC                ((FMAC_TypeDef *) FMAC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define DAC3                ((DAC_TypeDef *) DAC3_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+
+#define DMAMUX1_Channel0    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
+#define DMAMUX1_Channel1    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
+#define DMAMUX1_Channel2    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
+#define DMAMUX1_Channel3    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
+#define DMAMUX1_Channel4    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
+#define DMAMUX1_Channel5    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
+#define DMAMUX1_Channel6    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
+#define DMAMUX1_Channel7    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
+#define DMAMUX1_Channel8    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
+#define DMAMUX1_Channel9    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
+#define DMAMUX1_Channel10   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
+#define DMAMUX1_Channel11   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
+
+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
+
+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
+
+
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/********************  Bit definition for ADC_ISR register  *******************/
+#define ADC_ISR_ADRDY_Pos              (0U)
+#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos              (1U)
+#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos                (2U)
+#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos                (3U)
+#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos                (4U)
+#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos               (5U)
+#define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos               (6U)
+#define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos               (7U)
+#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos               (8U)
+#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos               (9U)
+#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos              (10U)
+#define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_IER register  *******************/
+#define ADC_IER_ADRDYIE_Pos            (0U)
+#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos            (1U)
+#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos              (2U)
+#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos              (3U)
+#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos              (4U)
+#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos             (5U)
+#define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos             (6U)
+#define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos             (7U)
+#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos             (8U)
+#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos             (9U)
+#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_JQOVFIE_Pos            (10U)
+#define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                (0U)
+#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos               (1U)
+#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos             (2U)
+#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos            (3U)
+#define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos               (4U)
+#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos              (5U)
+#define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
+#define ADC_CR_ADVREGEN_Pos            (28U)
+#define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
+#define ADC_CR_DEEPPWD_Pos             (29U)
+#define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos            (30U)
+#define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos               (31U)
+#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR register  ******************/
+#define ADC_CFGR_DMAEN_Pos             (0U)
+#define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
+#define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
+#define ADC_CFGR_DMACFG_Pos            (1U)
+#define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
+#define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
+
+#define ADC_CFGR_RES_Pos               (3U)
+#define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
+#define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
+#define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
+#define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */
+
+#define ADC_CFGR_EXTSEL_Pos            (5U)
+#define ADC_CFGR_EXTSEL_Msk            (0x1FUL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x000003E0 */
+#define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
+#define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000020 */
+#define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_4              (0x10UL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos             (10U)
+#define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos            (12U)
+#define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
+#define ADC_CFGR_CONT_Pos              (13U)
+#define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
+#define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR_AUTDLY_Pos            (14U)
+#define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
+#define ADC_CFGR_ALIGN_Pos             (15U)
+#define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00008000 */
+#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
+#define ADC_CFGR_DISCEN_Pos            (16U)
+#define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR_DISCNUM_Pos           (17U)
+#define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos           (20U)
+#define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
+#define ADC_CFGR_JQM_Pos               (21U)
+#define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
+#define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
+#define ADC_CFGR_AWD1SGL_Pos           (22U)
+#define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR_AWD1EN_Pos            (23U)
+#define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR_JAWD1EN_Pos           (24U)
+#define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR_JAUTO_Pos             (25U)
+#define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR_AWD1CH_Pos            (26U)
+#define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos             (31U)
+#define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_ROVSE_Pos            (0U)
+#define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos            (1U)
+#define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSR_Pos             (2U)
+#define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos             (5U)
+#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos            (9U)
+#define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos            (10U)
+#define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+#define ADC_CFGR2_GCOMP_Pos            (16U)
+#define ADC_CFGR2_GCOMP_Msk            (0x1UL << ADC_CFGR2_GCOMP_Pos)          /*!< 0x00010000 */
+#define ADC_CFGR2_GCOMP                ADC_CFGR2_GCOMP_Msk                     /*!< ADC Gain Compensation mode */
+
+#define ADC_CFGR2_SWTRIG_Pos           (25U)
+#define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)         /*!< 0x02000000 */
+#define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                    /*!< ADC Software Trigger Bit for Sample time control trigger mode */
+#define ADC_CFGR2_BULB_Pos             (26U)
+#define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)           /*!< 0x04000000 */
+#define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                      /*!< ADC Bulb sampling mode */
+#define ADC_CFGR2_SMPTRIG_Pos          (27U)
+#define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)        /*!< 0x08000000 */
+#define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                   /*!< ADC Sample Time Control Trigger mode */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos             (0U)
+#define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos             (3U)
+#define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos             (6U)
+#define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos             (9U)
+#define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos             (12U)
+#define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos             (15U)
+#define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos             (18U)
+#define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos             (21U)
+#define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos             (24U)
+#define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos             (27U)
+#define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
+
+#define ADC_SMPR1_SMPPLUS_Pos          (31U)
+#define ADC_SMPR1_SMPPLUS_Msk          (0x1UL << ADC_SMPR1_SMPPLUS_Pos)        /*!< 0x80000000 */
+#define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos            (0U)
+#define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos            (3U)
+#define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos            (6U)
+#define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos            (9U)
+#define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos            (12U)
+#define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos            (15U)
+#define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos            (18U)
+#define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos            (21U)
+#define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos            (24U)
+#define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_TR1 register  *******************/
+#define ADC_TR1_LT1_Pos                (0U)
+#define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
+#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
+
+#define ADC_TR1_AWDFILT_Pos            (12U)
+#define ADC_TR1_AWDFILT_Msk            (0x7UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00007000 */
+#define ADC_TR1_AWDFILT                ADC_TR1_AWDFILT_Msk                     /*!< ADC analog watchdog filtering parameter  */
+#define ADC_TR1_AWDFILT_0              (0x1UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00001000 */
+#define ADC_TR1_AWDFILT_1              (0x2UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00002000 */
+#define ADC_TR1_AWDFILT_2              (0x4UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00004000 */
+
+#define ADC_TR1_HT1_Pos                (16U)
+#define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC analog watchdog 1 threshold high */
+
+/********************  Bit definition for ADC_TR2 register  *******************/
+#define ADC_TR2_LT2_Pos                (0U)
+#define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
+#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
+
+#define ADC_TR2_HT2_Pos                (16U)
+#define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
+#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
+
+/********************  Bit definition for ADC_TR3 register  *******************/
+#define ADC_TR3_LT3_Pos                (0U)
+#define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
+#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
+
+#define ADC_TR3_HT3_Pos                (16U)
+#define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
+#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos                 (0U)
+#define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
+#define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
+#define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
+#define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos               (6U)
+#define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos               (12U)
+#define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos               (18U)
+#define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                 (0x10UL<< ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos               (24U)
+#define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos               (0U)
+#define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos               (6U)
+#define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos               (12U)
+#define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos               (18U)
+#define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos               (24U)
+#define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos              (0U)
+#define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos              (6U)
+#define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos              (12U)
+#define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos              (18U)
+#define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos              (24U)
+#define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos              (0U)
+#define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos              (6U)
+#define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos               (0U)
+#define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos                (0U)
+#define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos           (2U)
+#define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos            (7U)
+#define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos              (9U)
+#define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos              (15U)
+#define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
+#define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
+
+#define ADC_JSQR_JSQ3_Pos              (21U)
+#define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos              (27U)
+#define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET1_Pos           (0U)
+#define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
+#define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
+
+#define ADC_OFR1_OFFSETPOS_Pos         (24U)
+#define ADC_OFR1_OFFSETPOS_Msk         (0x1UL << ADC_OFR1_OFFSETPOS_Pos)       /*!< 0x01000000 */
+#define ADC_OFR1_OFFSETPOS             ADC_OFR1_OFFSETPOS_Msk                  /*!< ADC offset number 1 positive */
+#define ADC_OFR1_SATEN_Pos             (25U)
+#define ADC_OFR1_SATEN_Msk             (0x1UL << ADC_OFR1_SATEN_Pos)           /*!< 0x02000000 */
+#define ADC_OFR1_SATEN                 ADC_OFR1_SATEN_Msk                      /*!< ADC offset number 1 saturation enable */
+
+#define ADC_OFR1_OFFSET1_CH_Pos        (26U)
+#define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
+#define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */
+
+#define ADC_OFR1_OFFSET1_EN_Pos        (31U)
+#define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
+#define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET2_Pos           (0U)
+#define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
+#define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
+
+#define ADC_OFR2_OFFSETPOS_Pos         (24U)
+#define ADC_OFR2_OFFSETPOS_Msk         (0x1UL << ADC_OFR2_OFFSETPOS_Pos)       /*!< 0x01000000 */
+#define ADC_OFR2_OFFSETPOS             ADC_OFR2_OFFSETPOS_Msk                  /*!< ADC offset number 2 positive */
+#define ADC_OFR2_SATEN_Pos             (25U)
+#define ADC_OFR2_SATEN_Msk             (0x1UL << ADC_OFR2_SATEN_Pos)           /*!< 0x02000000 */
+#define ADC_OFR2_SATEN                 ADC_OFR2_SATEN_Msk                      /*!< ADC offset number 2 saturation enable */
+
+#define ADC_OFR2_OFFSET2_CH_Pos        (26U)
+#define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
+#define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */
+
+#define ADC_OFR2_OFFSET2_EN_Pos        (31U)
+#define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
+#define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET3_Pos           (0U)
+#define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
+#define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
+
+#define ADC_OFR3_OFFSETPOS_Pos         (24U)
+#define ADC_OFR3_OFFSETPOS_Msk         (0x1UL << ADC_OFR3_OFFSETPOS_Pos)       /*!< 0x01000000 */
+#define ADC_OFR3_OFFSETPOS             ADC_OFR3_OFFSETPOS_Msk                  /*!< ADC offset number 3 positive */
+#define ADC_OFR3_SATEN_Pos             (25U)
+#define ADC_OFR3_SATEN_Msk             (0x1UL << ADC_OFR3_SATEN_Pos)           /*!< 0x02000000 */
+#define ADC_OFR3_SATEN                 ADC_OFR3_SATEN_Msk                      /*!< ADC offset number 3 saturation enable */
+
+#define ADC_OFR3_OFFSET3_CH_Pos        (26U)
+#define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
+#define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */
+
+#define ADC_OFR3_OFFSET3_EN_Pos        (31U)
+#define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
+#define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET4_Pos           (0U)
+#define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
+#define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
+
+#define ADC_OFR4_OFFSETPOS_Pos         (24U)
+#define ADC_OFR4_OFFSETPOS_Msk         (0x1UL << ADC_OFR4_OFFSETPOS_Pos)       /*!< 0x01000000 */
+#define ADC_OFR4_OFFSETPOS             ADC_OFR4_OFFSETPOS_Msk                  /*!< ADC offset number 4 positive */
+#define ADC_OFR4_SATEN_Pos             (25U)
+#define ADC_OFR4_SATEN_Msk             (0x1UL << ADC_OFR4_SATEN_Pos)           /*!< 0x02000000 */
+#define ADC_OFR4_SATEN                 ADC_OFR4_SATEN_Msk                      /*!< ADC offset number 4 saturation enable */
+
+#define ADC_OFR4_OFFSET4_CH_Pos        (26U)
+#define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
+#define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */
+
+#define ADC_OFR4_OFFSET4_EN_Pos        (31U)
+#define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
+#define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos             (0U)
+#define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
+
+/********************  Bit definition for ADC_JDR2 register  ******************/
+#define ADC_JDR2_JDATA_Pos             (0U)
+#define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
+
+/********************  Bit definition for ADC_JDR3 register  ******************/
+#define ADC_JDR3_JDATA_Pos             (0U)
+#define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
+
+/********************  Bit definition for ADC_JDR4 register  ******************/
+#define ADC_JDR4_JDATA_Pos             (0U)
+#define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)
+#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)
+#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)
+#define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
+#define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)
+#define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000030 */
+
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)
+#define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00300000 */
+
+/********************  Bit definition for ADC_GCOMP register  *****************/
+#define ADC_GCOMP_GCOMPCOEFF_Pos       (0U)
+#define ADC_GCOMP_GCOMPCOEFF_Msk       (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00003FFF */
+#define ADC_GCOMP_GCOMPCOEFF           ADC_GCOMP_GCOMPCOEFF_Msk                /*!< ADC Gain Compensation Coefficient */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  *******************/
+#define ADC_CSR_ADRDY_MST_Pos          (0U)
+#define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
+#define ADC_CSR_EOSMP_MST_Pos          (1U)
+#define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
+#define ADC_CSR_EOC_MST_Pos            (2U)
+#define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_MST_Pos            (3U)
+#define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_MST_Pos            (4U)
+#define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_JEOC_MST_Pos           (5U)
+#define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_MST_Pos           (6U)
+#define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_MST_Pos           (7U)
+#define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_AWD2_MST_Pos           (8U)
+#define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
+#define ADC_CSR_AWD3_MST_Pos           (9U)
+#define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_MST_Pos          (10U)
+#define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
+
+#define ADC_CSR_ADRDY_SLV_Pos          (16U)
+#define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
+#define ADC_CSR_EOSMP_SLV_Pos          (17U)
+#define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
+#define ADC_CSR_EOC_SLV_Pos            (18U)
+#define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_SLV_Pos            (19U)
+#define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_SLV_Pos            (20U)
+#define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
+#define ADC_CSR_JEOC_SLV_Pos           (21U)
+#define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_SLV_Pos           (22U)
+#define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_SLV_Pos           (23U)
+#define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
+#define ADC_CSR_AWD2_SLV_Pos           (24U)
+#define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
+#define ADC_CSR_AWD3_SLV_Pos           (25U)
+#define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_SLV_Pos          (26U)
+#define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_DUAL_Pos               (0U)
+#define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
+#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
+#define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos              (8U)
+#define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
+
+#define ADC_CCR_DMACFG_Pos             (13U)
+#define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */
+#define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
+
+#define ADC_CCR_MDMA_Pos               (14U)
+#define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */
+#define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
+#define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */
+#define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos             (16U)
+#define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos              (18U)
+#define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
+#define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos             (22U)
+#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_VSENSESEL_Pos          (23U)
+#define ADC_CCR_VSENSESEL_Msk          (0x1UL << ADC_CCR_VSENSESEL_Pos)        /*!< 0x00800000 */
+#define ADC_CCR_VSENSESEL              ADC_CCR_VSENSESEL_Msk                   /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATSEL_Pos            (24U)
+#define ADC_CCR_VBATSEL_Msk            (0x1UL << ADC_CCR_VBATSEL_Pos)          /*!< 0x01000000 */
+#define ADC_CCR_VBATSEL                ADC_CCR_VBATSEL_Msk                     /*!< ADC internal path to battery voltage enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos          (0U)
+#define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
+
+#define ADC_CDR_RDATA_SLV_Pos          (16U)
+#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/**********************  Bit definition for COMP_CSR register  ****************/
+#define COMP_CSR_EN_Pos            (0U)
+#define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
+#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
+
+#define COMP_CSR_INMSEL_Pos        (4U)
+#define COMP_CSR_INMSEL_Msk        (0xFUL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
+#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
+#define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
+#define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
+#define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
+#define COMP_CSR_INMSEL_3          (0x8UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000080 */
+
+#define COMP_CSR_INPSEL_Pos        (8U)
+#define COMP_CSR_INPSEL_Msk        (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
+#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
+
+#define COMP_CSR_POLARITY_Pos      (15U)
+#define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
+#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
+
+#define COMP_CSR_HYST_Pos          (16U)
+#define COMP_CSR_HYST_Msk          (0x7UL << COMP_CSR_HYST_Pos)                /*!< 0x00070000 */
+#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
+#define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
+#define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
+#define COMP_CSR_HYST_2            (0x4UL << COMP_CSR_HYST_Pos)                /*!< 0x00040000 */
+
+#define COMP_CSR_BLANKING_Pos      (19U)
+#define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00380000 */
+#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
+#define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
+#define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
+#define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00200000 */
+
+#define COMP_CSR_BRGEN_Pos         (22U)
+#define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
+#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator scaler bridge enable */
+
+#define COMP_CSR_SCALEN_Pos        (23U)
+#define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
+#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator voltage scaler enable */
+
+#define COMP_CSR_VALUE_Pos         (30U)
+#define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
+#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
+
+#define COMP_CSR_LOCK_Pos          (31U)
+#define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
+#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CORDIC calculation unit                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CORDIC_CSR register  *****************/
+#define CORDIC_CSR_FUNC_Pos      (0U)
+#define CORDIC_CSR_FUNC_Msk      (0xFUL << CORDIC_CSR_FUNC_Pos)                /*!< 0x0000000F */
+#define CORDIC_CSR_FUNC          CORDIC_CSR_FUNC_Msk                           /*!< Function */
+#define CORDIC_CSR_FUNC_0        (0x1UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000001 */
+#define CORDIC_CSR_FUNC_1        (0x2UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000002 */
+#define CORDIC_CSR_FUNC_2        (0x4UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000004 */
+#define CORDIC_CSR_FUNC_3        (0x8UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000008 */
+#define CORDIC_CSR_PRECISION_Pos (4U)
+#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x000000F0 */
+#define CORDIC_CSR_PRECISION     CORDIC_CSR_PRECISION_Msk                      /*!< Precision */
+#define CORDIC_CSR_PRECISION_0   (0x1UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000010 */
+#define CORDIC_CSR_PRECISION_1   (0x2UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000020 */
+#define CORDIC_CSR_PRECISION_2   (0x4UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000040 */
+#define CORDIC_CSR_PRECISION_3   (0x8UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000080 */
+#define CORDIC_CSR_SCALE_Pos     (8U)
+#define CORDIC_CSR_SCALE_Msk     (0x7UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000700 */
+#define CORDIC_CSR_SCALE         CORDIC_CSR_SCALE_Msk                          /*!< Scaling factor */
+#define CORDIC_CSR_SCALE_0       (0x1UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000100 */
+#define CORDIC_CSR_SCALE_1       (0x2UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000200 */
+#define CORDIC_CSR_SCALE_2       (0x4UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000400 */
+#define CORDIC_CSR_IEN_Pos       (16U)
+#define CORDIC_CSR_IEN_Msk       (0x1UL << CORDIC_CSR_IEN_Pos)                 /*!< 0x00010000 */
+#define CORDIC_CSR_IEN           CORDIC_CSR_IEN_Msk                            /*!< Interrupt Enable */
+#define CORDIC_CSR_DMAREN_Pos    (17U)
+#define CORDIC_CSR_DMAREN_Msk    (0x1UL << CORDIC_CSR_DMAREN_Pos)              /*!< 0x00020000 */
+#define CORDIC_CSR_DMAREN        CORDIC_CSR_DMAREN_Msk                         /*!< DMA Read channel Enable */
+#define CORDIC_CSR_DMAWEN_Pos    (18U)
+#define CORDIC_CSR_DMAWEN_Msk    (0x1UL << CORDIC_CSR_DMAWEN_Pos)              /*!< 0x00040000 */
+#define CORDIC_CSR_DMAWEN        CORDIC_CSR_DMAWEN_Msk                         /*!< DMA Write channel Enable */
+#define CORDIC_CSR_NRES_Pos      (19U)
+#define CORDIC_CSR_NRES_Msk      (0x1UL << CORDIC_CSR_NRES_Pos)                /*!< 0x00080000 */
+#define CORDIC_CSR_NRES          CORDIC_CSR_NRES_Msk                           /*!< Number of results in WDATA register */
+#define CORDIC_CSR_NARGS_Pos     (20U)
+#define CORDIC_CSR_NARGS_Msk     (0x1UL << CORDIC_CSR_NARGS_Pos)               /*!< 0x00100000 */
+#define CORDIC_CSR_NARGS         CORDIC_CSR_NARGS_Msk                          /*!< Number of arguments in RDATA register */
+#define CORDIC_CSR_RESSIZE_Pos   (21U)
+#define CORDIC_CSR_RESSIZE_Msk   (0x1UL << CORDIC_CSR_RESSIZE_Pos)             /*!< 0x00200000 */
+#define CORDIC_CSR_RESSIZE       CORDIC_CSR_RESSIZE_Msk                        /*!< Width of output data */
+#define CORDIC_CSR_ARGSIZE_Pos   (22U)
+#define CORDIC_CSR_ARGSIZE_Msk   (0x1UL << CORDIC_CSR_ARGSIZE_Pos)             /*!< 0x00400000 */
+#define CORDIC_CSR_ARGSIZE       CORDIC_CSR_ARGSIZE_Msk                        /*!< Width of input data */
+#define CORDIC_CSR_RRDY_Pos      (31U)
+#define CORDIC_CSR_RRDY_Msk      (0x1UL << CORDIC_CSR_RRDY_Pos)                /*!< 0x80000000 */
+#define CORDIC_CSR_RRDY          CORDIC_CSR_RRDY_Msk                           /*!< Result Ready Flag */
+
+/*******************  Bit definition for CORDIC_WDATA register  ***************/
+#define CORDIC_WDATA_ARG_Pos     (0U)
+#define CORDIC_WDATA_ARG_Msk     (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)        /*!< 0xFFFFFFFF */
+#define CORDIC_WDATA_ARG         CORDIC_WDATA_ARG_Msk                          /*!< Input Argument */
+
+/*******************  Bit definition for CORDIC_RDATA register  ***************/
+#define CORDIC_RDATA_RES_Pos     (0U)
+#define CORDIC_RDATA_RES_Msk     (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)        /*!< 0xFFFFFFFF */
+#define CORDIC_RDATA_RES         CORDIC_RDATA_RES_Msk                          /*!< Output Result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)
+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)
+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)
+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)
+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)
+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)
+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)
+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define CRS_CR_SYNCOKIE_Pos       (0U)
+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos     (1U)
+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos          (2U)
+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos        (3U)
+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos            (5U)
+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos     (6U)
+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos         (7U)
+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos           (8U)
+#define CRS_CR_TRIM_Msk           (0x7FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00007F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define CRS_CFGR_RELOAD_Pos       (0U)
+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos        (16U)
+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos      (24U)
+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos      (28U)
+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos      (31U)
+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define CRS_ISR_SYNCOKF_Pos       (0U)
+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos     (1U)
+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos          (2U)
+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos        (3U)
+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos       (8U)
+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos      (9U)
+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos       (10U)
+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos         (15U)
+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos         (16U)
+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define CRS_ICR_SYNCOKC_Pos       (0U)
+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos     (1U)
+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos          (2U)
+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos        (3U)
+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
+ */
+#define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)
+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (1U)
+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (2U)
+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000004 */
+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos            (6U)
+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)
+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)
+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)
+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)
+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_HFSEL_Pos            (15U)
+#define DAC_CR_HFSEL_Msk            (0x1UL << DAC_CR_HFSEL_Pos)                /*!< 0x00008000 */
+#define DAC_CR_HFSEL                DAC_CR_HFSEL_Msk                           /*!<DAC channel 1 and 2 high frequency mode enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)
+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (17U)
+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (18U)
+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                /*!< 0x00040000 */
+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                /*!< 0x00080000 */
+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                /*!< 0x00100000 */
+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos            (22U)
+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)
+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)
+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)
+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)
+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+#define DAC_SWTRIGR_SWTRIGB1_Pos    (16U)
+#define DAC_SWTRIGR_SWTRIGB1_Msk    (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)        /*!< 0x00010000 */
+#define DAC_SWTRIGR_SWTRIGB1        DAC_SWTRIGR_SWTRIGB1_Msk                   /*!<DAC channel1 software trigger B */
+#define DAC_SWTRIGR_SWTRIGB2_Pos    (17U)
+#define DAC_SWTRIGR_SWTRIGB2_Msk    (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)        /*!< 0x00020000 */
+#define DAC_SWTRIGR_SWTRIGB2        DAC_SWTRIGR_SWTRIGB2_Msk                   /*!<DAC channel2 software trigger B */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12R1_DACC1DHRB_Pos   (16U)
+#define DAC_DHR12R1_DACC1DHRB_Msk   (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)     /*!< 0x0FFF0000 */
+#define DAC_DHR12R1_DACC1DHRB       DAC_DHR12R1_DACC1DHRB_Msk                  /*!<DAC channel1 12-bit Right-aligned data B */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12L1_DACC1DHRB_Pos   (20U)
+#define DAC_DHR12L1_DACC1DHRB_Msk   (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)     /*!< 0xFFF00000 */
+#define DAC_DHR12L1_DACC1DHRB       DAC_DHR12L1_DACC1DHRB_Msk                  /*!<DAC channel1 12-bit Left aligned data B */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8R1_DACC1DHRB_Pos    (8U)
+#define DAC_DHR8R1_DACC1DHRB_Msk    (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)       /*!< 0x0000FF00 */
+#define DAC_DHR8R1_DACC1DHRB        DAC_DHR8R1_DACC1DHRB_Msk                   /*!<DAC channel1 8-bit Right aligned data B */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+#define DAC_DHR12R2_DACC2DHRB_Pos   (16U)
+#define DAC_DHR12R2_DACC2DHRB_Msk   (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)     /*!< 0x0FFF0000 */
+#define DAC_DHR12R2_DACC2DHRB       DAC_DHR12R2_DACC2DHRB_Msk                  /*!<DAC channel2 12-bit Right-aligned data B */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+#define DAC_DHR12L2_DACC2DHRB_Pos   (20U)
+#define DAC_DHR12L2_DACC2DHRB_Msk   (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)     /*!< 0xFFF00000 */
+#define DAC_DHR12L2_DACC2DHRB       DAC_DHR12L2_DACC2DHRB_Msk                  /*!<DAC channel2 12-bit Left aligned data B */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+#define DAC_DHR8R2_DACC2DHRB_Pos    (8U)
+#define DAC_DHR8R2_DACC2DHRB_Msk    (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)       /*!< 0x0000FF00 */
+#define DAC_DHR8R2_DACC2DHRB        DAC_DHR8R2_DACC2DHRB_Msk                   /*!<DAC channel2 8-bit Right aligned data B */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+#define DAC_DOR1_DACC1DORB_Pos      (16U)
+#define DAC_DOR1_DACC1DORB_Msk      (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)        /*!< 0x0FFF0000 */
+#define DAC_DOR1_DACC1DORB          DAC_DOR1_DACC1DORB_Msk                     /*!<DAC channel1 data output B */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+#define DAC_DOR2_DACC2DORB_Pos      (16U)
+#define DAC_DOR2_DACC2DORB_Msk      (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)        /*!< 0x0FFF0000 */
+#define DAC_DOR2_DACC2DORB          DAC_DOR2_DACC2DORB_Msk                     /*!<DAC channel2 data output B */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DAC1RDY_Pos          (11U)
+#define DAC_SR_DAC1RDY_Msk          (0x1UL << DAC_SR_DAC1RDY_Pos)              /*!< 0x00000800 */
+#define DAC_SR_DAC1RDY              DAC_SR_DAC1RDY_Msk                         /*!<DAC channel 1 ready status bit */
+#define DAC_SR_DORSTAT1_Pos         (12U)
+#define DAC_SR_DORSTAT1_Msk         (0x1UL << DAC_SR_DORSTAT1_Pos)             /*!< 0x00001000 */
+#define DAC_SR_DORSTAT1             DAC_SR_DORSTAT1_Msk                        /*!<DAC channel 1 output register status bit */
+#define DAC_SR_DMAUDR1_Pos          (13U)
+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)
+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)
+#define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DAC2RDY_Pos          (27U)
+#define DAC_SR_DAC2RDY_Msk          (0x1UL << DAC_SR_DAC2RDY_Pos)              /*!< 0x08000000 */
+#define DAC_SR_DAC2RDY              DAC_SR_DAC2RDY_Msk                         /*!<DAC channel 2 ready status bit */
+#define DAC_SR_DORSTAT2_Pos         (28U)
+#define DAC_SR_DORSTAT2_Msk         (0x1UL << DAC_SR_DORSTAT2_Pos)             /*!< 0x10000000 */
+#define DAC_SR_DORSTAT2             DAC_SR_DORSTAT2_Msk                        /*!<DAC channel 2 output register status bit */
+#define DAC_SR_DMAUDR2_Pos          (29U)
+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)
+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)
+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)
+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)
+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)
+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
+
+#define DAC_MCR_DMADOUBLE1_Pos      (8U)
+#define DAC_MCR_DMADOUBLE1_Msk      (0x1UL << DAC_MCR_DMADOUBLE1_Pos)          /*!< 0x00000100 */
+#define DAC_MCR_DMADOUBLE1          DAC_MCR_DMADOUBLE1_Msk                     /*!<DAC Channel 1 DMA double data mode */
+
+#define DAC_MCR_SINFORMAT1_Pos      (9U)
+#define DAC_MCR_SINFORMAT1_Msk      (0x1UL << DAC_MCR_SINFORMAT1_Pos)          /*!< 0x00000200 */
+#define DAC_MCR_SINFORMAT1          DAC_MCR_SINFORMAT1_Msk                     /*!<DAC Channel 1 enable signed format */
+
+#define DAC_MCR_HFSEL_Pos           (14U)
+#define DAC_MCR_HFSEL_Msk           (0x3UL << DAC_MCR_HFSEL_Pos)               /*!< 0x0000C000 */
+#define DAC_MCR_HFSEL               DAC_MCR_HFSEL_Msk                          /*!<HFSEL[1:0] (High Frequency interface mode selection) */
+#define DAC_MCR_HFSEL_0             (0x1UL << DAC_MCR_HFSEL_Pos)               /*!< 0x00004000 */
+#define DAC_MCR_HFSEL_1             (0x2UL << DAC_MCR_HFSEL_Pos)               /*!< 0x00008000 */
+
+#define DAC_MCR_MODE2_Pos           (16U)
+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)               /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)               /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)               /*!< 0x00040000 */
+
+#define DAC_MCR_DMADOUBLE2_Pos      (24U)
+#define DAC_MCR_DMADOUBLE2_Msk      (0x1UL << DAC_MCR_DMADOUBLE2_Pos)          /*!< 0x01000000 */
+#define DAC_MCR_DMADOUBLE2          DAC_MCR_DMADOUBLE2_Msk                     /*!<DAC Channel 2 DMA double data mode */
+
+#define DAC_MCR_SINFORMAT2_Pos      (25U)
+#define DAC_MCR_SINFORMAT2_Msk      (0x1UL << DAC_MCR_SINFORMAT2_Pos)          /*!< 0x02000000 */
+#define DAC_MCR_SINFORMAT2          DAC_MCR_SINFORMAT2_Msk                     /*!<DAC Channel 2 enable signed format */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)
+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)
+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************  Bit definition for DAC_STR1 register  ******************/
+#define DAC_STR1_STRSTDATA1_Pos     (0U)
+#define DAC_STR1_STRSTDATA1_Msk     (0xFFFUL << DAC_STR1_STRSTDATA1_Pos)       /*!< 0x00000FFF */
+#define DAC_STR1_STRSTDATA1         DAC_STR1_STRSTDATA1_Msk                    /*!<DAC Channel 1 Sawtooth starting value */
+#define DAC_STR1_STDIR1_Pos         (12U)
+#define DAC_STR1_STDIR1_Msk         (0x1UL << DAC_STR1_STDIR1_Pos)             /*!< 0x00001000 */
+#define DAC_STR1_STDIR1             DAC_STR1_STDIR1_Msk                        /*!<DAC Channel 1 Sawtooth direction setting */
+
+#define DAC_STR1_STINCDATA1_Pos     (16U)
+#define DAC_STR1_STINCDATA1_Msk     (0xFFFFUL << DAC_STR1_STINCDATA1_Pos)      /*!< 0xFFFF0000 */
+#define DAC_STR1_STINCDATA1         DAC_STR1_STINCDATA1_Msk                    /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
+
+/******************  Bit definition for DAC_STR2 register  ******************/
+#define DAC_STR2_STRSTDATA2_Pos     (0U)
+#define DAC_STR2_STRSTDATA2_Msk     (0xFFFUL << DAC_STR2_STRSTDATA2_Pos)       /*!< 0x00000FFF */
+#define DAC_STR2_STRSTDATA2         DAC_STR2_STRSTDATA2_Msk                    /*!<DAC Channel 2 Sawtooth starting value */
+#define DAC_STR2_STDIR2_Pos         (12U)
+#define DAC_STR2_STDIR2_Msk         (0x1UL << DAC_STR2_STDIR2_Pos)             /*!< 0x00001000 */
+#define DAC_STR2_STDIR2             DAC_STR2_STDIR2_Msk                        /*!<DAC Channel 2 Sawtooth direction setting */
+
+#define DAC_STR2_STINCDATA2_Pos     (16U)
+#define DAC_STR2_STINCDATA2_Msk     (0xFFFFUL << DAC_STR2_STINCDATA2_Pos)      /*!< 0xFFFF0000 */
+#define DAC_STR2_STINCDATA2         DAC_STR2_STINCDATA2_Msk                    /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
+
+/******************  Bit definition for DAC_STMODR register  ****************/
+#define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
+#define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x0000000F */
+#define DAC_STMODR_STRSTTRIGSEL1     DAC_STMODR_STRSTTRIGSEL1_Msk              /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
+#define DAC_STMODR_STRSTTRIGSEL1_0   (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000001 */
+#define DAC_STMODR_STRSTTRIGSEL1_1   (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000002 */
+#define DAC_STMODR_STRSTTRIGSEL1_2   (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000004 */
+#define DAC_STMODR_STRSTTRIGSEL1_3   (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000008 */
+
+#define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
+#define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x0000000F */
+#define DAC_STMODR_STINCTRIGSEL1     DAC_STMODR_STINCTRIGSEL1_Msk              /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
+#define DAC_STMODR_STINCTRIGSEL1_0   (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000001 */
+#define DAC_STMODR_STINCTRIGSEL1_1   (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000002 */
+#define DAC_STMODR_STINCTRIGSEL1_2   (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000004 */
+#define DAC_STMODR_STINCTRIGSEL1_3   (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000008 */
+
+#define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
+#define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x0000000F */
+#define DAC_STMODR_STRSTTRIGSEL2     DAC_STMODR_STRSTTRIGSEL2_Msk              /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
+#define DAC_STMODR_STRSTTRIGSEL2_0   (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000001 */
+#define DAC_STMODR_STRSTTRIGSEL2_1   (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000002 */
+#define DAC_STMODR_STRSTTRIGSEL2_2   (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000004 */
+#define DAC_STMODR_STRSTTRIGSEL2_3   (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000008 */
+
+#define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
+#define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x0000000F */
+#define DAC_STMODR_STINCTRIGSEL2     DAC_STMODR_STINCTRIGSEL2_Msk              /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
+#define DAC_STMODR_STINCTRIGSEL2_0   (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000001 */
+#define DAC_STMODR_STINCTRIGSEL2_1   (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000002 */
+#define DAC_STMODR_STINCTRIGSEL2_2   (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000004 */
+#define DAC_STMODR_STINCTRIGSEL2_3   (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000008 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos               (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos                 (1U)
+#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos               (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos               (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0                 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1                 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
+
+/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (30U)
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
+
+
+/********************  Bit definition for DBGMCU_APB2FZ register  ************/
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define DMA_ISR_GIF1_Pos       (0U)
+#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
+#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos      (1U)
+#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
+#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos      (2U)
+#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
+#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos      (3U)
+#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
+#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos       (4U)
+#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
+#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos      (5U)
+#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
+#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos      (6U)
+#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
+#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos      (7U)
+#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
+#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos       (8U)
+#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
+#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos      (9U)
+#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
+#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos      (10U)
+#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
+#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos      (11U)
+#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
+#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos       (12U)
+#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
+#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos      (13U)
+#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
+#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos      (14U)
+#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
+#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos      (15U)
+#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
+#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos       (16U)
+#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
+#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos      (17U)
+#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
+#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos      (18U)
+#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
+#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos      (19U)
+#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
+#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos       (20U)
+#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
+#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos      (21U)
+#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
+#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos      (22U)
+#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
+#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos      (23U)
+#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
+#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define DMA_IFCR_CGIF1_Pos     (0U)
+#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1_Pos    (1U)
+#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos    (2U)
+#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos    (3U)
+#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos     (4U)
+#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos    (5U)
+#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos    (6U)
+#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos    (7U)
+#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos     (8U)
+#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos    (9U)
+#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos    (10U)
+#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos    (11U)
+#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos     (12U)
+#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos    (13U)
+#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos    (14U)
+#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos    (15U)
+#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos     (16U)
+#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos    (17U)
+#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos    (18U)
+#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos    (19U)
+#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos     (20U)
+#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos    (21U)
+#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos    (22U)
+#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos    (23U)
+#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos         (0U)
+#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
+#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
+#define DMA_CCR_TCIE_Pos       (1U)
+#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
+#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
+#define DMA_CCR_HTIE_Pos       (2U)
+#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
+#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
+#define DMA_CCR_TEIE_Pos       (3U)
+#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
+#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
+#define DMA_CCR_DIR_Pos        (4U)
+#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
+#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
+#define DMA_CCR_CIRC_Pos       (5U)
+#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
+#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
+#define DMA_CCR_PINC_Pos       (6U)
+#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
+#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
+#define DMA_CCR_MINC_Pos       (7U)
+#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
+#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
+
+#define DMA_CCR_PSIZE_Pos      (8U)
+#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
+#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos      (10U)
+#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
+#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos         (12U)
+#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
+#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
+#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos    (14U)
+#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define DMA_CNDTR_NDT_Pos      (0U)
+#define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define DMA_CPAR_PA_Pos        (0U)
+#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define DMA_CMAR_MA_Pos        (0U)
+#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMAMUX Controller                              */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bits definition for DMAMUX_CxCR register  **************/
+#define DMAMUX_CxCR_DMAREQ_ID_Pos                    (0U)
+#define DMAMUX_CxCR_DMAREQ_ID_Msk                    (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
+#define DMAMUX_CxCR_DMAREQ_ID                        DMAMUX_CxCR_DMAREQ_ID_Msk
+#define DMAMUX_CxCR_DMAREQ_ID_0                      (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
+#define DMAMUX_CxCR_DMAREQ_ID_1                      (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
+#define DMAMUX_CxCR_DMAREQ_ID_2                      (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
+#define DMAMUX_CxCR_DMAREQ_ID_3                      (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
+#define DMAMUX_CxCR_DMAREQ_ID_4                      (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
+#define DMAMUX_CxCR_DMAREQ_ID_5                      (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
+#define DMAMUX_CxCR_DMAREQ_ID_6                      (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
+#define DMAMUX_CxCR_DMAREQ_ID_7                      (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
+
+#define DMAMUX_CxCR_SOIE_Pos                         (8U)
+#define DMAMUX_CxCR_SOIE_Msk                         (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
+#define DMAMUX_CxCR_SOIE                             DMAMUX_CxCR_SOIE_Msk
+
+#define DMAMUX_CxCR_EGE_Pos                          (9U)
+#define DMAMUX_CxCR_EGE_Msk                          (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
+#define DMAMUX_CxCR_EGE                              DMAMUX_CxCR_EGE_Msk
+
+#define DMAMUX_CxCR_SE_Pos                           (16U)
+#define DMAMUX_CxCR_SE_Msk                           (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
+#define DMAMUX_CxCR_SE                               DMAMUX_CxCR_SE_Msk
+
+#define DMAMUX_CxCR_SPOL_Pos                         (17U)
+#define DMAMUX_CxCR_SPOL_Msk                         (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
+#define DMAMUX_CxCR_SPOL                             DMAMUX_CxCR_SPOL_Msk
+#define DMAMUX_CxCR_SPOL_0                           (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
+#define DMAMUX_CxCR_SPOL_1                           (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
+
+#define DMAMUX_CxCR_NBREQ_Pos                        (19U)
+#define DMAMUX_CxCR_NBREQ_Msk                        (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
+#define DMAMUX_CxCR_NBREQ                            DMAMUX_CxCR_NBREQ_Msk
+#define DMAMUX_CxCR_NBREQ_0                          (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
+#define DMAMUX_CxCR_NBREQ_1                          (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
+#define DMAMUX_CxCR_NBREQ_2                          (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
+#define DMAMUX_CxCR_NBREQ_3                          (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
+#define DMAMUX_CxCR_NBREQ_4                          (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
+
+#define DMAMUX_CxCR_SYNC_ID_Pos                      (24U)
+#define DMAMUX_CxCR_SYNC_ID_Msk                      (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
+#define DMAMUX_CxCR_SYNC_ID                          DMAMUX_CxCR_SYNC_ID_Msk
+#define DMAMUX_CxCR_SYNC_ID_0                        (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
+#define DMAMUX_CxCR_SYNC_ID_1                        (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
+#define DMAMUX_CxCR_SYNC_ID_2                        (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
+#define DMAMUX_CxCR_SYNC_ID_3                        (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
+#define DMAMUX_CxCR_SYNC_ID_4                        (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
+
+/********************  Bits definition for DMAMUX_CSR register  ****************/
+#define DMAMUX_CSR_SOF0_Pos                          (0U)
+#define DMAMUX_CSR_SOF0_Msk                          (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
+#define DMAMUX_CSR_SOF0                              DMAMUX_CSR_SOF0_Msk
+#define DMAMUX_CSR_SOF1_Pos                          (1U)
+#define DMAMUX_CSR_SOF1_Msk                          (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
+#define DMAMUX_CSR_SOF1                              DMAMUX_CSR_SOF1_Msk
+#define DMAMUX_CSR_SOF2_Pos                          (2U)
+#define DMAMUX_CSR_SOF2_Msk                          (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
+#define DMAMUX_CSR_SOF2                              DMAMUX_CSR_SOF2_Msk
+#define DMAMUX_CSR_SOF3_Pos                          (3U)
+#define DMAMUX_CSR_SOF3_Msk                          (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
+#define DMAMUX_CSR_SOF3                              DMAMUX_CSR_SOF3_Msk
+#define DMAMUX_CSR_SOF4_Pos                          (4U)
+#define DMAMUX_CSR_SOF4_Msk                          (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
+#define DMAMUX_CSR_SOF4                              DMAMUX_CSR_SOF4_Msk
+#define DMAMUX_CSR_SOF5_Pos                          (5U)
+#define DMAMUX_CSR_SOF5_Msk                          (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
+#define DMAMUX_CSR_SOF5                              DMAMUX_CSR_SOF5_Msk
+#define DMAMUX_CSR_SOF6_Pos                          (6U)
+#define DMAMUX_CSR_SOF6_Msk                          (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
+#define DMAMUX_CSR_SOF6                              DMAMUX_CSR_SOF6_Msk
+#define DMAMUX_CSR_SOF7_Pos                          (7U)
+#define DMAMUX_CSR_SOF7_Msk                          (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
+#define DMAMUX_CSR_SOF7                              DMAMUX_CSR_SOF7_Msk
+#define DMAMUX_CSR_SOF8_Pos                          (8U)
+#define DMAMUX_CSR_SOF8_Msk                          (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
+#define DMAMUX_CSR_SOF8                              DMAMUX_CSR_SOF8_Msk
+#define DMAMUX_CSR_SOF9_Pos                          (9U)
+#define DMAMUX_CSR_SOF9_Msk                          (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
+#define DMAMUX_CSR_SOF9                              DMAMUX_CSR_SOF9_Msk
+#define DMAMUX_CSR_SOF10_Pos                         (10U)
+#define DMAMUX_CSR_SOF10_Msk                         (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
+#define DMAMUX_CSR_SOF10                             DMAMUX_CSR_SOF10_Msk
+#define DMAMUX_CSR_SOF11_Pos                         (11U)
+#define DMAMUX_CSR_SOF11_Msk                         (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
+#define DMAMUX_CSR_SOF11                              DMAMUX_CSR_SOF11_Msk
+
+/********************  Bits definition for DMAMUX_CFR register  ****************/
+#define DMAMUX_CFR_CSOF0_Pos                         (0U)
+#define DMAMUX_CFR_CSOF0_Msk                         (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
+#define DMAMUX_CFR_CSOF0                             DMAMUX_CFR_CSOF0_Msk
+#define DMAMUX_CFR_CSOF1_Pos                         (1U)
+#define DMAMUX_CFR_CSOF1_Msk                         (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
+#define DMAMUX_CFR_CSOF1                             DMAMUX_CFR_CSOF1_Msk
+#define DMAMUX_CFR_CSOF2_Pos                         (2U)
+#define DMAMUX_CFR_CSOF2_Msk                         (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
+#define DMAMUX_CFR_CSOF2                             DMAMUX_CFR_CSOF2_Msk
+#define DMAMUX_CFR_CSOF3_Pos                         (3U)
+#define DMAMUX_CFR_CSOF3_Msk                         (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
+#define DMAMUX_CFR_CSOF3                             DMAMUX_CFR_CSOF3_Msk
+#define DMAMUX_CFR_CSOF4_Pos                         (4U)
+#define DMAMUX_CFR_CSOF4_Msk                         (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
+#define DMAMUX_CFR_CSOF4                             DMAMUX_CFR_CSOF4_Msk
+#define DMAMUX_CFR_CSOF5_Pos                         (5U)
+#define DMAMUX_CFR_CSOF5_Msk                         (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
+#define DMAMUX_CFR_CSOF5                             DMAMUX_CFR_CSOF5_Msk
+#define DMAMUX_CFR_CSOF6_Pos                         (6U)
+#define DMAMUX_CFR_CSOF6_Msk                         (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
+#define DMAMUX_CFR_CSOF6                             DMAMUX_CFR_CSOF6_Msk
+#define DMAMUX_CFR_CSOF7_Pos                         (7U)
+#define DMAMUX_CFR_CSOF7_Msk                         (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
+#define DMAMUX_CFR_CSOF7                             DMAMUX_CFR_CSOF7_Msk
+#define DMAMUX_CFR_CSOF8_Pos                         (8U)
+#define DMAMUX_CFR_CSOF8_Msk                         (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
+#define DMAMUX_CFR_CSOF8                             DMAMUX_CFR_CSOF8_Msk
+#define DMAMUX_CFR_CSOF9_Pos                         (9U)
+#define DMAMUX_CFR_CSOF9_Msk                         (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
+#define DMAMUX_CFR_CSOF9                             DMAMUX_CFR_CSOF9_Msk
+#define DMAMUX_CFR_CSOF10_Pos                        (10U)
+#define DMAMUX_CFR_CSOF10_Msk                        (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
+#define DMAMUX_CFR_CSOF10                            DMAMUX_CFR_CSOF10_Msk
+#define DMAMUX_CFR_CSOF11_Pos                        (11U)
+#define DMAMUX_CFR_CSOF11_Msk                        (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
+#define DMAMUX_CFR_CSOF11                            DMAMUX_CFR_CSOF11_Msk
+
+/********************  Bits definition for DMAMUX_RGxCR register  ************/
+#define DMAMUX_RGxCR_SIG_ID_Pos                      (0U)
+#define DMAMUX_RGxCR_SIG_ID_Msk                      (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
+#define DMAMUX_RGxCR_SIG_ID                          DMAMUX_RGxCR_SIG_ID_Msk
+#define DMAMUX_RGxCR_SIG_ID_0                        (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
+#define DMAMUX_RGxCR_SIG_ID_1                        (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
+#define DMAMUX_RGxCR_SIG_ID_2                        (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
+#define DMAMUX_RGxCR_SIG_ID_3                        (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
+#define DMAMUX_RGxCR_SIG_ID_4                        (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
+
+#define DMAMUX_RGxCR_OIE_Pos                         (8U)
+#define DMAMUX_RGxCR_OIE_Msk                         (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
+#define DMAMUX_RGxCR_OIE                             DMAMUX_RGxCR_OIE_Msk
+
+#define DMAMUX_RGxCR_GE_Pos                          (16U)
+#define DMAMUX_RGxCR_GE_Msk                          (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
+#define DMAMUX_RGxCR_GE                              DMAMUX_RGxCR_GE_Msk
+
+#define DMAMUX_RGxCR_GPOL_Pos                        (17U)
+#define DMAMUX_RGxCR_GPOL_Msk                        (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
+#define DMAMUX_RGxCR_GPOL                            DMAMUX_RGxCR_GPOL_Msk
+#define DMAMUX_RGxCR_GPOL_0                          (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
+#define DMAMUX_RGxCR_GPOL_1                          (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
+
+#define DMAMUX_RGxCR_GNBREQ_Pos                      (19U)
+#define DMAMUX_RGxCR_GNBREQ_Msk                      (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
+#define DMAMUX_RGxCR_GNBREQ                          DMAMUX_RGxCR_GNBREQ_Msk
+#define DMAMUX_RGxCR_GNBREQ_0                        (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
+#define DMAMUX_RGxCR_GNBREQ_1                        (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
+#define DMAMUX_RGxCR_GNBREQ_2                        (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
+#define DMAMUX_RGxCR_GNBREQ_3                        (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
+#define DMAMUX_RGxCR_GNBREQ_4                        (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
+
+/********************  Bits definition for DMAMUX_RGSR register  **************/
+#define DMAMUX_RGSR_OF0_Pos                          (0U)
+#define DMAMUX_RGSR_OF0_Msk                          (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
+#define DMAMUX_RGSR_OF0                              DMAMUX_RGSR_OF0_Msk
+#define DMAMUX_RGSR_OF1_Pos                          (1U)
+#define DMAMUX_RGSR_OF1_Msk                          (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
+#define DMAMUX_RGSR_OF1                              DMAMUX_RGSR_OF1_Msk
+#define DMAMUX_RGSR_OF2_Pos                          (2U)
+#define DMAMUX_RGSR_OF2_Msk                          (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
+#define DMAMUX_RGSR_OF2                              DMAMUX_RGSR_OF2_Msk
+#define DMAMUX_RGSR_OF3_Pos                          (3U)
+#define DMAMUX_RGSR_OF3_Msk                          (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
+#define DMAMUX_RGSR_OF3                              DMAMUX_RGSR_OF3_Msk
+
+/********************  Bits definition for DMAMUX_RGCFR register  ************/
+#define DMAMUX_RGCFR_COF0_Pos                        (0U)
+#define DMAMUX_RGCFR_COF0_Msk                        (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
+#define DMAMUX_RGCFR_COF0                            DMAMUX_RGCFR_COF0_Msk
+#define DMAMUX_RGCFR_COF1_Pos                        (1U)
+#define DMAMUX_RGCFR_COF1_Msk                        (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
+#define DMAMUX_RGCFR_COF1                            DMAMUX_RGCFR_COF1_Msk
+#define DMAMUX_RGCFR_COF2_Pos                        (2U)
+#define DMAMUX_RGCFR_COF2_Msk                        (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
+#define DMAMUX_RGCFR_COF2                            DMAMUX_RGCFR_COF2_Msk
+#define DMAMUX_RGCFR_COF3_Pos                        (3U)
+#define DMAMUX_RGCFR_COF3_Msk                        (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
+#define DMAMUX_RGCFR_COF3                            DMAMUX_RGCFR_COF3_Msk
+
+/******************** Bits definition for DMAMUX_IPHW_CFGR2  ******************/
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos       (0U)
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos       (1U)
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos       (2U)
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos       (3U)
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos       (4U)
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos       (5U)
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos       (6U)
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos       (7U)
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
+
+/******************** Bits definition for DMAMUX_IPHW_CFGR1  ******************/
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos       (0U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos       (1U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos       (2U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos       (3U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos       (4U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos       (5U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos       (6U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos       (7U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos    (8U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos    (9U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos    (10U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos    (11U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos    (12U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos    (13U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos    (14U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos    (15U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos          (16U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos          (17U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos          (18U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos          (19U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos          (20U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos          (21U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos          (22U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos          (23U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos        (24U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos        (25U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos        (26U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos        (27U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos        (28U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos        (29U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos        (30U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos        (31U)
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR1 register  ******************/
+#define EXTI_IMR1_IM0_Pos        (0U)
+#define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
+#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos        (1U)
+#define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
+#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos        (2U)
+#define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
+#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos        (3U)
+#define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
+#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos        (4U)
+#define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
+#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos        (5U)
+#define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
+#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos        (6U)
+#define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
+#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos        (7U)
+#define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
+#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos        (8U)
+#define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
+#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos        (9U)
+#define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
+#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos       (10U)
+#define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
+#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos       (11U)
+#define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
+#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos       (12U)
+#define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
+#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos       (13U)
+#define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
+#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos       (14U)
+#define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
+#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos       (15U)
+#define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
+#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos       (16U)
+#define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
+#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos       (17U)
+#define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
+#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos       (18U)
+#define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
+#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos       (19U)
+#define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
+#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos       (20U)
+#define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
+#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos       (21U)
+#define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
+#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos       (22U)
+#define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */
+#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos       (23U)
+#define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
+#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos       (24U)
+#define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
+#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos       (25U)
+#define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
+#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos       (26U)
+#define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
+#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos       (27U)
+#define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
+#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos       (28U)
+#define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
+#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos       (29U)
+#define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
+#define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos       (30U)
+#define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
+#define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM_Pos         (0U)
+#define EXTI_IMR1_IM_Msk         (0x7FFFFFFFUL << EXTI_IMR1_IM_Pos)            /*!< 0x7FFFFFFF */
+#define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR1 register  ******************/
+#define EXTI_EMR1_EM0_Pos        (0U)
+#define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
+#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos        (1U)
+#define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
+#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos        (2U)
+#define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
+#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos        (3U)
+#define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
+#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos        (4U)
+#define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
+#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos        (5U)
+#define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
+#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos        (6U)
+#define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
+#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos        (7U)
+#define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
+#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos        (8U)
+#define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
+#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos        (9U)
+#define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
+#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos       (10U)
+#define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
+#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos       (11U)
+#define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
+#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos       (12U)
+#define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
+#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos       (13U)
+#define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
+#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos       (14U)
+#define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
+#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos       (15U)
+#define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
+#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos       (16U)
+#define EXTI_EMR1_EM16_Msk       (0x1UL << EXTI_EMR1_EM16_Pos)                 /*!< 0x00010000 */
+#define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos       (17U)
+#define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
+#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos       (18U)
+#define EXTI_EMR1_EM18_Msk       (0x1UL << EXTI_EMR1_EM18_Pos)                 /*!< 0x00040000 */
+#define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos       (19U)
+#define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
+#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos       (20U)
+#define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
+#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos       (21U)
+#define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
+#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos       (22U)
+#define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */
+#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos       (23U)
+#define EXTI_EMR1_EM23_Msk       (0x1UL << EXTI_EMR1_EM23_Pos)                 /*!< 0x00800000 */
+#define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos       (24U)
+#define EXTI_EMR1_EM24_Msk       (0x1UL << EXTI_EMR1_EM24_Pos)                 /*!< 0x01000000 */
+#define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos       (25U)
+#define EXTI_EMR1_EM25_Msk       (0x1UL << EXTI_EMR1_EM25_Pos)                 /*!< 0x02000000 */
+#define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos       (26U)
+#define EXTI_EMR1_EM26_Msk       (0x1UL << EXTI_EMR1_EM26_Pos)                 /*!< 0x04000000 */
+#define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos       (27U)
+#define EXTI_EMR1_EM27_Msk       (0x1UL << EXTI_EMR1_EM27_Pos)                 /*!< 0x08000000 */
+#define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos       (28U)
+#define EXTI_EMR1_EM28_Msk       (0x1UL << EXTI_EMR1_EM28_Pos)                 /*!< 0x10000000 */
+#define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos       (29U)
+#define EXTI_EMR1_EM29_Msk       (0x1UL << EXTI_EMR1_EM29_Pos)                 /*!< 0x20000000 */
+#define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos       (30U)
+#define EXTI_EMR1_EM30_Msk       (0x1UL << EXTI_EMR1_EM30_Pos)                 /*!< 0x40000000 */
+#define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */
+
+/******************  Bit definition for EXTI_RTSR1 register  ******************/
+#define EXTI_RTSR1_RT0_Pos       (0U)
+#define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_RT1_Pos       (1U)
+#define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_RT2_Pos       (2U)
+#define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_RT3_Pos       (3U)
+#define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_RT4_Pos       (4U)
+#define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_RT5_Pos       (5U)
+#define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_RT6_Pos       (6U)
+#define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_RT7_Pos       (7U)
+#define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_RT8_Pos       (8U)
+#define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_RT9_Pos       (9U)
+#define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_RT10_Pos      (10U)
+#define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_RT11_Pos      (11U)
+#define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_RT12_Pos      (12U)
+#define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_RT13_Pos      (13U)
+#define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_RT14_Pos      (14U)
+#define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_RT15_Pos      (15U)
+#define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_RT16_Pos      (16U)
+#define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
+#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_RT17_Pos      (17U)
+#define EXTI_RTSR1_RT17_Msk      (0x1UL << EXTI_RTSR1_RT17_Pos)                /*!< 0x00020000 */
+#define EXTI_RTSR1_RT17          EXTI_RTSR1_RT17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR1_RT19_Pos      (19U)
+#define EXTI_RTSR1_RT19_Msk      (0x1UL << EXTI_RTSR1_RT19_Pos)                /*!< 0x00080000 */
+#define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_RT20_Pos      (20U)
+#define EXTI_RTSR1_RT20_Msk      (0x1UL << EXTI_RTSR1_RT20_Pos)                /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_RT21_Pos      (21U)
+#define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR1_RT22_Pos      (22U)
+#define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */
+#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR1_RT29_Pos      (29U)
+#define EXTI_RTSR1_RT29_Msk      (0x1UL << EXTI_RTSR1_RT29_Pos)                /*!< 0x20000000 */
+#define EXTI_RTSR1_RT29          EXTI_RTSR1_RT29_Msk                           /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR1_RT30_Pos      (30U)
+#define EXTI_RTSR1_RT30_Msk      (0x1UL << EXTI_RTSR1_RT30_Pos)                /*!< 0x40000000 */
+#define EXTI_RTSR1_RT30          EXTI_RTSR1_RT30_Msk                           /*!< Rising trigger event configuration bit of line 30 */
+
+/******************  Bit definition for EXTI_FTSR1 register  ******************/
+#define EXTI_FTSR1_FT0_Pos       (0U)
+#define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_FT1_Pos       (1U)
+#define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_FT2_Pos       (2U)
+#define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_FT3_Pos       (3U)
+#define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_FT4_Pos       (4U)
+#define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_FT5_Pos       (5U)
+#define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_FT6_Pos       (6U)
+#define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_FT7_Pos       (7U)
+#define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_FT8_Pos       (8U)
+#define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_FT9_Pos       (9U)
+#define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_FT10_Pos      (10U)
+#define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_FT11_Pos      (11U)
+#define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_FT12_Pos      (12U)
+#define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_FT13_Pos      (13U)
+#define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_FT14_Pos      (14U)
+#define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_FT15_Pos      (15U)
+#define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_FT16_Pos      (16U)
+#define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
+#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_FT17_Pos      (17U)
+#define EXTI_FTSR1_FT17_Msk      (0x1UL << EXTI_FTSR1_FT17_Pos)                /*!< 0x00020000 */
+#define EXTI_FTSR1_FT17          EXTI_FTSR1_FT17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR1_FT19_Pos      (19U)
+#define EXTI_FTSR1_FT19_Msk      (0x1UL << EXTI_FTSR1_FT19_Pos)                /*!< 0x00080000 */
+#define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_FT20_Pos      (20U)
+#define EXTI_FTSR1_FT20_Msk      (0x1UL << EXTI_FTSR1_FT20_Pos)                /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_FT21_Pos      (21U)
+#define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR1_FT22_Pos      (22U)
+#define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */
+#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR1_FT29_Pos      (29U)
+#define EXTI_FTSR1_FT29_Msk      (0x1UL << EXTI_FTSR1_FT29_Pos)                /*!< 0x20000000 */
+#define EXTI_FTSR1_FT29          EXTI_FTSR1_FT29_Msk                           /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR1_FT30_Pos      (30U)
+#define EXTI_FTSR1_FT30_Msk      (0x1UL << EXTI_FTSR1_FT30_Pos)                /*!< 0x40000000 */
+#define EXTI_FTSR1_FT30          EXTI_FTSR1_FT30_Msk                           /*!< Falling trigger event configuration bit of line 30 */
+
+/******************  Bit definition for EXTI_SWIER1 register  *****************/
+#define EXTI_SWIER1_SWI0_Pos     (0U)
+#define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos     (1U)
+#define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos     (2U)
+#define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos     (3U)
+#define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos     (4U)
+#define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos     (5U)
+#define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos     (6U)
+#define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos     (7U)
+#define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos     (8U)
+#define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos     (9U)
+#define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos    (10U)
+#define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos    (11U)
+#define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos    (12U)
+#define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos    (13U)
+#define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos    (14U)
+#define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos    (15U)
+#define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI16_Pos    (16U)
+#define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
+#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWI17_Pos    (17U)
+#define EXTI_SWIER1_SWI17_Msk    (0x1UL << EXTI_SWIER1_SWI17_Pos)              /*!< 0x00020000 */
+#define EXTI_SWIER1_SWI17        EXTI_SWIER1_SWI17_Msk                         /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER1_SWI19_Pos    (19U)
+#define EXTI_SWIER1_SWI19_Msk    (0x1UL << EXTI_SWIER1_SWI19_Pos)              /*!< 0x00080000 */
+#define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWI20_Pos    (20U)
+#define EXTI_SWIER1_SWI20_Msk    (0x1UL << EXTI_SWIER1_SWI20_Pos)              /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos    (21U)
+#define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER1_SWI22_Pos    (22U)
+#define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */
+#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER1_SWI29_Pos    (29U)
+#define EXTI_SWIER1_SWI29_Msk    (0x1UL << EXTI_SWIER1_SWI29_Pos)              /*!< 0x20000000 */
+#define EXTI_SWIER1_SWI29        EXTI_SWIER1_SWI29_Msk                         /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER1_SWI30_Pos    (30U)
+#define EXTI_SWIER1_SWI30_Msk    (0x1UL << EXTI_SWIER1_SWI30_Pos)              /*!< 0x40000000 */
+#define EXTI_SWIER1_SWI30        EXTI_SWIER1_SWI30_Msk                         /*!< Software Interrupt on line 30 */
+
+/*******************  Bit definition for EXTI_PR1 register  *******************/
+#define EXTI_PR1_PIF0_Pos        (0U)
+#define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
+#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
+#define EXTI_PR1_PIF1_Pos        (1U)
+#define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
+#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
+#define EXTI_PR1_PIF2_Pos        (2U)
+#define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
+#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
+#define EXTI_PR1_PIF3_Pos        (3U)
+#define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
+#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
+#define EXTI_PR1_PIF4_Pos        (4U)
+#define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
+#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
+#define EXTI_PR1_PIF5_Pos        (5U)
+#define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
+#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
+#define EXTI_PR1_PIF6_Pos        (6U)
+#define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
+#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
+#define EXTI_PR1_PIF7_Pos        (7U)
+#define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
+#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
+#define EXTI_PR1_PIF8_Pos        (8U)
+#define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
+#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
+#define EXTI_PR1_PIF9_Pos        (9U)
+#define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
+#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
+#define EXTI_PR1_PIF10_Pos       (10U)
+#define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
+#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
+#define EXTI_PR1_PIF11_Pos       (11U)
+#define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
+#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
+#define EXTI_PR1_PIF12_Pos       (12U)
+#define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
+#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
+#define EXTI_PR1_PIF13_Pos       (13U)
+#define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
+#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
+#define EXTI_PR1_PIF14_Pos       (14U)
+#define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
+#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
+#define EXTI_PR1_PIF15_Pos       (15U)
+#define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
+#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
+#define EXTI_PR1_PIF16_Pos       (16U)
+#define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
+#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
+#define EXTI_PR1_PIF17_Pos       (17U)
+#define EXTI_PR1_PIF17_Msk       (0x1UL << EXTI_PR1_PIF17_Pos)                 /*!< 0x00020000 */
+#define EXTI_PR1_PIF17           EXTI_PR1_PIF17_Msk                            /*!< Pending bit for line 17 */
+#define EXTI_PR1_PIF19_Pos       (19U)
+#define EXTI_PR1_PIF19_Msk       (0x1UL << EXTI_PR1_PIF19_Pos)                 /*!< 0x00080000 */
+#define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
+#define EXTI_PR1_PIF20_Pos       (20U)
+#define EXTI_PR1_PIF20_Msk       (0x1UL << EXTI_PR1_PIF20_Pos)                 /*!< 0x00100000 */
+#define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
+#define EXTI_PR1_PIF21_Pos       (21U)
+#define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
+#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
+#define EXTI_PR1_PIF22_Pos       (22U)
+#define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */
+#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
+#define EXTI_PR1_PIF29_Pos       (29U)
+#define EXTI_PR1_PIF29_Msk       (0x1UL << EXTI_PR1_PIF29_Pos)                 /*!< 0x20000000 */
+#define EXTI_PR1_PIF29           EXTI_PR1_PIF29_Msk                            /*!< Pending bit for line 29 */
+#define EXTI_PR1_PIF30_Pos       (30U)
+#define EXTI_PR1_PIF30_Msk       (0x1UL << EXTI_PR1_PIF30_Pos)                 /*!< 0x40000000 */
+#define EXTI_PR1_PIF30           EXTI_PR1_PIF30_Msk                            /*!< Pending bit for line 30 */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_IM34_Pos       (2U)
+#define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */
+#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM36_Pos       (4U)
+#define EXTI_IMR2_IM36_Msk       (0x1UL << EXTI_IMR2_IM36_Pos)                 /*!< 0x00000010 */
+#define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos       (5U)
+#define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */
+#define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos       (6U)
+#define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
+#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos       (7U)
+#define EXTI_IMR2_IM39_Msk       (0x1UL << EXTI_IMR2_IM39_Pos)                 /*!< 0x00000080 */
+#define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos       (8U)
+#define EXTI_IMR2_IM40_Msk       (0x1UL << EXTI_IMR2_IM40_Pos)                 /*!< 0x00000100 */
+#define EXTI_IMR2_IM40           EXTI_IMR2_IM40_Msk                            /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM41_Pos       (9U)
+#define EXTI_IMR2_IM41_Msk       (0x1UL << EXTI_IMR2_IM41_Pos)                 /*!< 0x00000200 */
+#define EXTI_IMR2_IM41           EXTI_IMR2_IM41_Msk                            /*!< Interrupt Mask on line 41 */
+#define EXTI_IMR2_IM_Pos         (0U)
+#define EXTI_IMR2_IM_Msk         (0x3F4UL << EXTI_IMR2_IM_Pos)                 /*!< 0x000003F4 */
+#define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
+
+/*******************  Bit definition for EXTI_EMR2 register  ******************/
+#define EXTI_EMR2_EM34_Pos       (2U)
+#define EXTI_EMR2_EM34_Msk       (0x1UL << EXTI_EMR2_EM34_Pos)                 /*!< 0x00000004 */
+#define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM36_Pos       (4U)
+#define EXTI_EMR2_EM36_Msk       (0x1UL << EXTI_EMR2_EM36_Pos)                 /*!< 0x00000010 */
+#define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos       (5U)
+#define EXTI_EMR2_EM37_Msk       (0x1UL << EXTI_EMR2_EM37_Pos)                 /*!< 0x00000020 */
+#define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos       (6U)
+#define EXTI_EMR2_EM38_Msk       (0x1UL << EXTI_EMR2_EM38_Pos)                 /*!< 0x00000040 */
+#define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM39_Pos       (7U)
+#define EXTI_EMR2_EM39_Msk       (0x1UL << EXTI_EMR2_EM39_Pos)                 /*!< 0x00000080 */
+#define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
+#define EXTI_EMR2_EM40_Pos       (8U)
+#define EXTI_EMR2_EM40_Msk       (0x1UL << EXTI_EMR2_EM40_Pos)                 /*!< 0x00000100 */
+#define EXTI_EMR2_EM40           EXTI_EMR2_EM40_Msk                            /*!< Event Mask on line 40 */
+#define EXTI_EMR2_EM41_Pos       (9U)
+#define EXTI_EMR2_EM41_Msk       (0x1UL << EXTI_EMR2_EM41_Pos)                 /*!< 0x00000200 */
+#define EXTI_EMR2_EM41           EXTI_EMR2_EM41_Msk                            /*!< Event Mask on line 41 */
+#define EXTI_EMR2_EM_Pos         (0U)
+#define EXTI_EMR2_EM_Msk         (0x3F4UL << EXTI_EMR2_EM_Pos)                 /*!< 0x000003F4 */
+#define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */
+
+/******************  Bit definition for EXTI_RTSR2 register  ******************/
+#define EXTI_RTSR2_RT38_Pos      (6U)
+#define EXTI_RTSR2_RT38_Msk      (0x1UL << EXTI_RTSR2_RT38_Pos)                /*!< 0x00000040 */
+#define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
+#define EXTI_RTSR2_RT39_Pos      (7U)
+#define EXTI_RTSR2_RT39_Msk      (0x1UL << EXTI_RTSR2_RT39_Pos)                /*!< 0x00000080 */
+#define EXTI_RTSR2_RT39          EXTI_RTSR2_RT39_Msk                           /*!< Rising trigger event configuration bit of line 39 */
+#define EXTI_RTSR2_RT40_Pos      (8U)
+#define EXTI_RTSR2_RT40_Msk      (0x1UL << EXTI_RTSR2_RT40_Pos)                /*!< 0x00000100 */
+#define EXTI_RTSR2_RT40          EXTI_RTSR2_RT40_Msk                           /*!< Rising trigger event configuration bit of line 40 */
+#define EXTI_RTSR2_RT41_Pos      (9U)
+#define EXTI_RTSR2_RT41_Msk      (0x1UL << EXTI_RTSR2_RT41_Pos)                /*!< 0x00000200 */
+#define EXTI_RTSR2_RT41          EXTI_RTSR2_RT41_Msk                           /*!< Rising trigger event configuration bit of line 41 */
+
+/******************  Bit definition for EXTI_FTSR2 register  ******************/
+#define EXTI_FTSR2_FT38_Pos      (6U)
+#define EXTI_FTSR2_FT38_Msk      (0x1UL << EXTI_FTSR2_FT38_Pos)                /*!< 0x00000040 */
+#define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 37 */
+#define EXTI_FTSR2_FT39_Pos      (7U)
+#define EXTI_FTSR2_FT39_Msk      (0x1UL << EXTI_FTSR2_FT39_Pos)                /*!< 0x00000080 */
+#define EXTI_FTSR2_FT39          EXTI_FTSR2_FT39_Msk                           /*!< Falling trigger event configuration bit of line 39 */
+#define EXTI_FTSR2_FT40_Pos      (8U)
+#define EXTI_FTSR2_FT40_Msk      (0x1UL << EXTI_FTSR2_FT40_Pos)                /*!< 0x00000100 */
+#define EXTI_FTSR2_FT40          EXTI_FTSR2_FT40_Msk                           /*!< Falling trigger event configuration bit of line 40 */
+#define EXTI_FTSR2_FT41_Pos      (9U)
+#define EXTI_FTSR2_FT41_Msk      (0x1UL << EXTI_FTSR2_FT41_Pos)                /*!< 0x00000200 */
+#define EXTI_FTSR2_FT41          EXTI_FTSR2_FT41_Msk                           /*!< Falling trigger event configuration bit of line 41 */
+
+/******************  Bit definition for EXTI_SWIER2 register  *****************/
+#define EXTI_SWIER2_SWI38_Pos    (6U)
+#define EXTI_SWIER2_SWI38_Msk    (0x1UL << EXTI_SWIER2_SWI38_Pos)              /*!< 0x00000040 */
+#define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
+#define EXTI_SWIER2_SWI39_Pos    (7U)
+#define EXTI_SWIER2_SWI39_Msk    (0x1UL << EXTI_SWIER2_SWI39_Pos)              /*!< 0x00000080 */
+#define EXTI_SWIER2_SWI39        EXTI_SWIER2_SWI39_Msk                         /*!< Software Interrupt on line 39 */
+#define EXTI_SWIER2_SWI40_Pos    (8U)
+#define EXTI_SWIER2_SWI40_Msk    (0x1UL << EXTI_SWIER2_SWI40_Pos)              /*!< 0x00000100 */
+#define EXTI_SWIER2_SWI40        EXTI_SWIER2_SWI40_Msk                         /*!< Software Interrupt on line 40 */
+#define EXTI_SWIER2_SWI41_Pos    (9U)
+#define EXTI_SWIER2_SWI41_Msk    (0x1UL << EXTI_SWIER2_SWI41_Pos)              /*!< 0x00000200 */
+#define EXTI_SWIER2_SWI41        EXTI_SWIER2_SWI41_Msk                         /*!< Software Interrupt on line 41 */
+
+/*******************  Bit definition for EXTI_PR2 register  *******************/
+#define EXTI_PR2_PIF38_Pos       (6U)
+#define EXTI_PR2_PIF38_Msk       (0x1UL << EXTI_PR2_PIF38_Pos)                 /*!< 0x00000040 */
+#define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
+#define EXTI_PR2_PIF39_Pos       (7U)
+#define EXTI_PR2_PIF39_Msk       (0x1UL << EXTI_PR2_PIF39_Pos)                 /*!< 0x00000080 */
+#define EXTI_PR2_PIF39           EXTI_PR2_PIF39_Msk                            /*!< Pending bit for line 39 */
+#define EXTI_PR2_PIF40_Pos       (8U)
+#define EXTI_PR2_PIF40_Msk       (0x1UL << EXTI_PR2_PIF40_Pos)                 /*!< 0x00000100 */
+#define EXTI_PR2_PIF40           EXTI_PR2_PIF40_Msk                            /*!< Pending bit for line 40 */
+#define EXTI_PR2_PIF41_Pos       (9U)
+#define EXTI_PR2_PIF41_Msk       (0x1UL << EXTI_PR2_PIF41_Pos)                 /*!< 0x00000200 */
+#define EXTI_PR2_PIF41           EXTI_PR2_PIF41_Msk                            /*!< Pending bit for line 41 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Flexible Datarate Controller Area Network                  */
+/*                                                                            */
+/******************************************************************************/
+/*!<FDCAN control and status registers */
+/*****************  Bit definition for FDCAN_CREL register  *******************/
+#define FDCAN_CREL_DAY_Pos        (0U)
+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
+#define FDCAN_CREL_MON_Pos        (8U)
+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
+#define FDCAN_CREL_YEAR_Pos       (16U)
+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
+#define FDCAN_CREL_SUBSTEP_Pos    (20U)
+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
+#define FDCAN_CREL_STEP_Pos       (24U)
+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
+#define FDCAN_CREL_REL_Pos        (28U)
+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
+
+/*****************  Bit definition for FDCAN_ENDN register  *******************/
+#define FDCAN_ENDN_ETV_Pos        (0U)
+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */
+
+/*****************  Bit definition for FDCAN_DBTP register  *******************/
+#define FDCAN_DBTP_DSJW_Pos       (0U)
+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
+#define FDCAN_DBTP_DTSEG2_Pos     (4U)
+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
+#define FDCAN_DBTP_DTSEG1_Pos     (8U)
+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
+#define FDCAN_DBTP_DBRP_Pos       (16U)
+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
+#define FDCAN_DBTP_TDC_Pos        (23U)
+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
+
+/*****************  Bit definition for FDCAN_TEST register  *******************/
+#define FDCAN_TEST_LBCK_Pos       (4U)
+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
+#define FDCAN_TEST_TX_Pos         (5U)
+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
+#define FDCAN_TEST_RX_Pos         (7U)
+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
+
+/*****************  Bit definition for FDCAN_RWD register  ********************/
+#define FDCAN_RWD_WDC_Pos         (0U)
+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
+#define FDCAN_RWD_WDV_Pos         (8U)
+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
+
+/*****************  Bit definition for FDCAN_CCCR register  ********************/
+#define FDCAN_CCCR_INIT_Pos       (0U)
+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
+#define FDCAN_CCCR_CCE_Pos        (1U)
+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
+#define FDCAN_CCCR_ASM_Pos        (2U)
+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
+#define FDCAN_CCCR_CSA_Pos        (3U)
+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
+#define FDCAN_CCCR_CSR_Pos        (4U)
+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
+#define FDCAN_CCCR_MON_Pos        (5U)
+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
+#define FDCAN_CCCR_DAR_Pos        (6U)
+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
+#define FDCAN_CCCR_TEST_Pos       (7U)
+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
+#define FDCAN_CCCR_FDOE_Pos       (8U)
+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
+#define FDCAN_CCCR_BRSE_Pos       (9U)
+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
+#define FDCAN_CCCR_PXHD_Pos       (12U)
+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
+#define FDCAN_CCCR_EFBI_Pos       (13U)
+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
+#define FDCAN_CCCR_TXP_Pos        (14U)
+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
+#define FDCAN_CCCR_NISO_Pos       (15U)
+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
+
+/*****************  Bit definition for FDCAN_NBTP register  ********************/
+#define FDCAN_NBTP_NTSEG2_Pos     (0U)
+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
+#define FDCAN_NBTP_NTSEG1_Pos     (8U)
+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
+#define FDCAN_NBTP_NBRP_Pos       (16U)
+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
+#define FDCAN_NBTP_NSJW_Pos       (25U)
+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
+
+/*****************  Bit definition for FDCAN_TSCC register  ********************/
+#define FDCAN_TSCC_TSS_Pos        (0U)
+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
+#define FDCAN_TSCC_TCP_Pos        (16U)
+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
+
+/*****************  Bit definition for FDCAN_TSCV register  ********************/
+#define FDCAN_TSCV_TSC_Pos        (0U)
+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
+
+/*****************  Bit definition for FDCAN_TOCC register  ********************/
+#define FDCAN_TOCC_ETOC_Pos       (0U)
+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
+#define FDCAN_TOCC_TOS_Pos        (1U)
+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
+#define FDCAN_TOCC_TOP_Pos        (16U)
+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
+
+/*****************  Bit definition for FDCAN_TOCV register  ********************/
+#define FDCAN_TOCV_TOC_Pos        (0U)
+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
+
+/*****************  Bit definition for FDCAN_ECR register  *********************/
+#define FDCAN_ECR_TEC_Pos         (0U)
+#define FDCAN_ECR_TEC_Msk         (0xFFUL << FDCAN_ECR_TEC_Pos)                /*!< 0x000000FF */
+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
+#define FDCAN_ECR_REC_Pos         (8U)
+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
+#define FDCAN_ECR_RP_Pos          (15U)
+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
+#define FDCAN_ECR_CEL_Pos         (16U)
+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
+
+/*****************  Bit definition for FDCAN_PSR register  *********************/
+#define FDCAN_PSR_LEC_Pos         (0U)
+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
+#define FDCAN_PSR_ACT_Pos         (3U)
+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
+#define FDCAN_PSR_EP_Pos          (5U)
+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
+#define FDCAN_PSR_EW_Pos          (6U)
+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
+#define FDCAN_PSR_BO_Pos          (7U)
+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
+#define FDCAN_PSR_DLEC_Pos        (8U)
+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
+#define FDCAN_PSR_RESI_Pos        (11U)
+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
+#define FDCAN_PSR_RBRS_Pos        (12U)
+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
+#define FDCAN_PSR_REDL_Pos        (13U)
+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
+#define FDCAN_PSR_PXE_Pos         (14U)
+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
+#define FDCAN_PSR_TDCV_Pos        (16U)
+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
+
+/*****************  Bit definition for FDCAN_TDCR register  ********************/
+#define FDCAN_TDCR_TDCF_Pos       (0U)
+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
+#define FDCAN_TDCR_TDCO_Pos       (8U)
+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
+
+/*****************  Bit definition for FDCAN_IR register  **********************/
+#define FDCAN_IR_RF0N_Pos         (0U)
+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
+#define FDCAN_IR_RF0F_Pos         (1U)
+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000002 */
+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
+#define FDCAN_IR_RF0L_Pos         (2U)
+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000004 */
+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
+#define FDCAN_IR_RF1N_Pos         (3U)
+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000008 */
+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
+#define FDCAN_IR_RF1F_Pos         (4U)
+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000010 */
+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
+#define FDCAN_IR_RF1L_Pos         (5U)
+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000020 */
+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
+#define FDCAN_IR_HPM_Pos          (6U)
+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000040 */
+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
+#define FDCAN_IR_TC_Pos           (7U)
+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000080 */
+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
+#define FDCAN_IR_TCF_Pos          (8U)
+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000100 */
+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
+#define FDCAN_IR_TFE_Pos          (9U)
+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000200 */
+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
+#define FDCAN_IR_TEFN_Pos         (10U)
+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00000400 */
+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
+#define FDCAN_IR_TEFF_Pos         (11U)
+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00000800 */
+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
+#define FDCAN_IR_TEFL_Pos         (12U)
+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00001000 */
+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
+#define FDCAN_IR_TSW_Pos          (13U)
+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00002000 */
+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
+#define FDCAN_IR_MRAF_Pos         (14U)
+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00004000 */
+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
+#define FDCAN_IR_TOO_Pos          (15U)
+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00008000 */
+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
+#define FDCAN_IR_ELO_Pos          (16U)
+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00010000 */
+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
+#define FDCAN_IR_EP_Pos           (17U)
+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00020000 */
+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
+#define FDCAN_IR_EW_Pos           (18U)
+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x00040000 */
+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
+#define FDCAN_IR_BO_Pos           (19U)
+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x00080000 */
+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
+#define FDCAN_IR_WDI_Pos          (20U)
+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x00100000 */
+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
+#define FDCAN_IR_PEA_Pos          (21U)
+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x00200000 */
+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
+#define FDCAN_IR_PED_Pos          (22U)
+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x00400000 */
+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
+#define FDCAN_IR_ARA_Pos          (23U)
+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x00800000 */
+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
+
+/*****************  Bit definition for FDCAN_IE register  **********************/
+#define FDCAN_IE_RF0NE_Pos        (0U)
+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable             */
+#define FDCAN_IE_RF0FE_Pos        (1U)
+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000002 */
+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                    */
+#define FDCAN_IE_RF0LE_Pos        (2U)
+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000004 */
+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable            */
+#define FDCAN_IE_RF1NE_Pos        (3U)
+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000008 */
+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable             */
+#define FDCAN_IE_RF1FE_Pos        (4U)
+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000010 */
+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                    */
+#define FDCAN_IE_RF1LE_Pos        (5U)
+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000020 */
+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable            */
+#define FDCAN_IE_HPME_Pos         (6U)
+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000040 */
+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable             */
+#define FDCAN_IE_TCE_Pos          (7U)
+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000080 */
+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable            */
+#define FDCAN_IE_TCFE_Pos         (8U)
+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000100 */
+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable*/
+#define FDCAN_IE_TFEE_Pos         (9U)
+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000200 */
+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                     */
+#define FDCAN_IE_TEFNE_Pos        (10U)
+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00000400 */
+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable           */
+#define FDCAN_IE_TEFFE_Pos        (11U)
+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00000800 */
+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                */
+#define FDCAN_IE_TEFLE_Pos        (12U)
+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00001000 */
+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable        */
+#define FDCAN_IE_TSWE_Pos         (13U)
+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00002000 */
+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable              */
+#define FDCAN_IE_MRAFE_Pos        (14U)
+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00004000 */
+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable        */
+#define FDCAN_IE_TOOE_Pos         (15U)
+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00008000 */
+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                  */
+#define FDCAN_IE_ELOE_Pos         (16U)
+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00010000 */
+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable            */
+#define FDCAN_IE_EPE_Pos          (17U)
+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00020000 */
+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                     */
+#define FDCAN_IE_EWE_Pos          (18U)
+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x00040000 */
+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                    */
+#define FDCAN_IE_BOE_Pos          (19U)
+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x00080000 */
+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                    */
+#define FDCAN_IE_WDIE_Pos         (20U)
+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x00100000 */
+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                */
+#define FDCAN_IE_PEAE_Pos         (21U)
+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x00200000 */
+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable*/
+#define FDCAN_IE_PEDE_Pos         (22U)
+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x00400000 */
+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable      */
+#define FDCAN_IE_ARAE_Pos         (23U)
+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x00800000 */
+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable        */
+
+/*****************  Bit definition for FDCAN_ILS register  **********************/
+#define FDCAN_ILS_RXFIFO0_Pos     (0U)
+#define FDCAN_ILS_RXFIFO0_Msk     (0x1UL << FDCAN_ILS_RXFIFO0_Pos)             /*!< 0x00000001 */
+#define FDCAN_ILS_RXFIFO0         FDCAN_ILS_RXFIFO0_Msk                        /*!<Rx FIFO 0 Message Lost
+                                                                                   Rx FIFO 0 is Full
+                                                                                   Rx FIFO 0 Has New Message                */
+#define FDCAN_ILS_RXFIFO1_Pos     (1U)
+#define FDCAN_ILS_RXFIFO1_Msk     (0x1UL << FDCAN_ILS_RXFIFO1_Pos)             /*!< 0x00000002 */
+#define FDCAN_ILS_RXFIFO1         FDCAN_ILS_RXFIFO1_Msk                        /*!<Rx FIFO 1 Message Lost
+                                                                                   Rx FIFO 1 is Full
+                                                                                   Rx FIFO 1 Has New Message                */
+#define FDCAN_ILS_SMSG_Pos        (2U)
+#define FDCAN_ILS_SMSG_Msk        (0x1UL << FDCAN_ILS_SMSG_Pos)                /*!< 0x00000004 */
+#define FDCAN_ILS_SMSG            FDCAN_ILS_SMSG_Msk                           /*!<Transmission Cancellation Finished
+                                                                                   Transmission Completed
+                                                                                   High Priority Message                    */
+#define FDCAN_ILS_TFERR_Pos       (3U)
+#define FDCAN_ILS_TFERR_Msk       (0x1UL << FDCAN_ILS_TFERR_Pos)               /*!< 0x00000008 */
+#define FDCAN_ILS_TFERR           FDCAN_ILS_TFERR_Msk                          /*!<Tx Event FIFO Element Lost
+                                                                                   Tx Event FIFO Full
+                                                                                   Tx Event FIFO New Entry
+                                                                                   Tx FIFO Empty Interrupt Line             */
+#define FDCAN_ILS_MISC_Pos        (4U)
+#define FDCAN_ILS_MISC_Msk        (0x1UL << FDCAN_ILS_MISC_Pos)                /*!< 0x00000010 */
+#define FDCAN_ILS_MISC            FDCAN_ILS_MISC_Msk                           /*!<Timeout Occurred
+                                                                                    Message RAM Access Failure
+                                                                                    Timestamp Wraparound                    */
+#define FDCAN_ILS_BERR_Pos        (5U)
+#define FDCAN_ILS_BERR_Msk        (0x1UL << FDCAN_ILS_BERR_Pos)                /*!< 0x00000020 */
+#define FDCAN_ILS_BERR            FDCAN_ILS_BERR_Msk                           /*!<Error Passive
+                                                                                   Error Logging Overflow                   */
+#define FDCAN_ILS_PERR_Pos        (6U)
+#define FDCAN_ILS_PERR_Msk        (0x1UL << FDCAN_ILS_PERR_Pos)                /*!< 0x00000040 */
+#define FDCAN_ILS_PERR            FDCAN_ILS_PERR_Msk                           /*!<Access to Reserved Address Line
+                                                                                   Protocol Error in Data Phase Line
+                                                                                   Protocol Error in Arbitration Phase Line
+                                                                                   Watchdog Interrupt Line
+                                                                                   Bus_Off Status
+                                                                                   Warning Status                           */
+
+/*****************  Bit definition for FDCAN_ILE register  **********************/
+#define FDCAN_ILE_EINT0_Pos       (0U)
+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                  */
+#define FDCAN_ILE_EINT1_Pos       (1U)
+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                  */
+
+/*****************  Bit definition for FDCAN_RXGFC register  ********************/
+#define FDCAN_RXGFC_RRFE_Pos      (0U)
+#define FDCAN_RXGFC_RRFE_Msk      (0x1UL << FDCAN_RXGFC_RRFE_Pos)              /*!< 0x00000001 */
+#define FDCAN_RXGFC_RRFE          FDCAN_RXGFC_RRFE_Msk                         /*!<Reject Remote Frames Extended            */
+#define FDCAN_RXGFC_RRFS_Pos      (1U)
+#define FDCAN_RXGFC_RRFS_Msk      (0x1UL << FDCAN_RXGFC_RRFS_Pos)              /*!< 0x00000002 */
+#define FDCAN_RXGFC_RRFS          FDCAN_RXGFC_RRFS_Msk                         /*!<Reject Remote Frames Standard            */
+#define FDCAN_RXGFC_ANFE_Pos      (2U)
+#define FDCAN_RXGFC_ANFE_Msk      (0x3UL << FDCAN_RXGFC_ANFE_Pos)              /*!< 0x0000000C */
+#define FDCAN_RXGFC_ANFE          FDCAN_RXGFC_ANFE_Msk                         /*!<Accept Non-matching Frames Extended      */
+#define FDCAN_RXGFC_ANFS_Pos      (4U)
+#define FDCAN_RXGFC_ANFS_Msk      (0x3UL << FDCAN_RXGFC_ANFS_Pos)              /*!< 0x00000030 */
+#define FDCAN_RXGFC_ANFS          FDCAN_RXGFC_ANFS_Msk                         /*!<Accept Non-matching Frames Standard      */
+#define FDCAN_RXGFC_F1OM_Pos      (8U)
+#define FDCAN_RXGFC_F1OM_Msk      (0x1UL << FDCAN_RXGFC_F1OM_Pos)              /*!< 0x00000100 */
+#define FDCAN_RXGFC_F1OM          FDCAN_RXGFC_F1OM_Msk                         /*!<FIFO 1 operation mode                    */
+#define FDCAN_RXGFC_F0OM_Pos      (9U)
+#define FDCAN_RXGFC_F0OM_Msk      (0x1UL << FDCAN_RXGFC_F0OM_Pos)              /*!< 0x00000200 */
+#define FDCAN_RXGFC_F0OM          FDCAN_RXGFC_F0OM_Msk                         /*!<FIFO 0 operation mode                    */
+#define FDCAN_RXGFC_LSS_Pos       (16U)
+#define FDCAN_RXGFC_LSS_Msk       (0x1FUL << FDCAN_RXGFC_LSS_Pos)              /*!< 0x001F0000 */
+#define FDCAN_RXGFC_LSS           FDCAN_RXGFC_LSS_Msk                          /*!<List Size Standard                       */
+#define FDCAN_RXGFC_LSE_Pos       (24U)
+#define FDCAN_RXGFC_LSE_Msk       (0xFUL << FDCAN_RXGFC_LSE_Pos)               /*!< 0x0F000000 */
+#define FDCAN_RXGFC_LSE           FDCAN_RXGFC_LSE_Msk                          /*!<List Size Extended                       */
+
+/*****************  Bit definition for FDCAN_XIDAM register  ********************/
+#define FDCAN_XIDAM_EIDM_Pos      (0U)
+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                         */
+
+/*****************  Bit definition for FDCAN_HPMS register  *********************/
+#define FDCAN_HPMS_BIDX_Pos       (0U)
+#define FDCAN_HPMS_BIDX_Msk       (0x7UL << FDCAN_HPMS_BIDX_Pos)               /*!< 0x00000007 */
+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                             */
+#define FDCAN_HPMS_MSI_Pos        (6U)
+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                */
+#define FDCAN_HPMS_FIDX_Pos       (8U)
+#define FDCAN_HPMS_FIDX_Msk       (0x1FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00001F00 */
+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                             */
+#define FDCAN_HPMS_FLST_Pos       (15U)
+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                              */
+
+/*****************  Bit definition for FDCAN_RXF0S register  ********************/
+#define FDCAN_RXF0S_F0FL_Pos      (0U)
+#define FDCAN_RXF0S_F0FL_Msk      (0xFUL << FDCAN_RXF0S_F0FL_Pos)              /*!< 0x0000000F */
+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                     */
+#define FDCAN_RXF0S_F0GI_Pos      (8U)
+#define FDCAN_RXF0S_F0GI_Msk      (0x3UL << FDCAN_RXF0S_F0GI_Pos)              /*!< 0x00000300 */
+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                      */
+#define FDCAN_RXF0S_F0PI_Pos      (16U)
+#define FDCAN_RXF0S_F0PI_Msk      (0x3UL << FDCAN_RXF0S_F0PI_Pos)              /*!< 0x00030000 */
+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                      */
+#define FDCAN_RXF0S_F0F_Pos       (24U)
+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                           */
+#define FDCAN_RXF0S_RF0L_Pos      (25U)
+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                   */
+
+/*****************  Bit definition for FDCAN_RXF0A register  ********************/
+#define FDCAN_RXF0A_F0AI_Pos      (0U)
+#define FDCAN_RXF0A_F0AI_Msk      (0x7UL << FDCAN_RXF0A_F0AI_Pos)              /*!< 0x00000007 */
+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_RXF1S register  ********************/
+#define FDCAN_RXF1S_F1FL_Pos      (0U)
+#define FDCAN_RXF1S_F1FL_Msk      (0xFUL << FDCAN_RXF1S_F1FL_Pos)              /*!< 0x0000000F */
+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                     */
+#define FDCAN_RXF1S_F1GI_Pos      (8U)
+#define FDCAN_RXF1S_F1GI_Msk      (0x3UL << FDCAN_RXF1S_F1GI_Pos)              /*!< 0x00000300 */
+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                      */
+#define FDCAN_RXF1S_F1PI_Pos      (16U)
+#define FDCAN_RXF1S_F1PI_Msk      (0x3UL << FDCAN_RXF1S_F1PI_Pos)              /*!< 0x00030000 */
+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                      */
+#define FDCAN_RXF1S_F1F_Pos       (24U)
+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                           */
+#define FDCAN_RXF1S_RF1L_Pos      (25U)
+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                   */
+
+/*****************  Bit definition for FDCAN_RXF1A register  ********************/
+#define FDCAN_RXF1A_F1AI_Pos      (0U)
+#define FDCAN_RXF1A_F1AI_Msk      (0x7UL << FDCAN_RXF1A_F1AI_Pos)              /*!< 0x00000007 */
+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_TXBC register  *********************/
+#define FDCAN_TXBC_TFQM_Pos       (24U)
+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x01000000 */
+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                       */
+
+/*****************  Bit definition for FDCAN_TXFQS register  *********************/
+#define FDCAN_TXFQS_TFFL_Pos      (0U)
+#define FDCAN_TXFQS_TFFL_Msk      (0x7UL << FDCAN_TXFQS_TFFL_Pos)              /*!< 0x00000007 */
+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                       */
+#define FDCAN_TXFQS_TFGI_Pos      (8U)
+#define FDCAN_TXFQS_TFGI_Msk      (0x3UL << FDCAN_TXFQS_TFGI_Pos)              /*!< 0x00000300 */
+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                        */
+#define FDCAN_TXFQS_TFQPI_Pos     (16U)
+#define FDCAN_TXFQS_TFQPI_Msk     (0x3UL << FDCAN_TXFQS_TFQPI_Pos)             /*!< 0x00030000 */
+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                  */
+#define FDCAN_TXFQS_TFQF_Pos      (21U)
+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                       */
+
+/*****************  Bit definition for FDCAN_TXBRP register  *********************/
+#define FDCAN_TXBRP_TRP_Pos       (0U)
+#define FDCAN_TXBRP_TRP_Msk       (0x7UL << FDCAN_TXBRP_TRP_Pos)               /*!< 0x00000007 */
+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending             */
+
+/*****************  Bit definition for FDCAN_TXBAR register  *********************/
+#define FDCAN_TXBAR_AR_Pos        (0U)
+#define FDCAN_TXBAR_AR_Msk        (0x7UL << FDCAN_TXBAR_AR_Pos)                /*!< 0x00000007 */
+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                              */
+
+/*****************  Bit definition for FDCAN_TXBCR register  *********************/
+#define FDCAN_TXBCR_CR_Pos        (0U)
+#define FDCAN_TXBCR_CR_Msk        (0x7UL << FDCAN_TXBCR_CR_Pos)                /*!< 0x00000007 */
+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                     */
+
+/*****************  Bit definition for FDCAN_TXBTO register  *********************/
+#define FDCAN_TXBTO_TO_Pos        (0U)
+#define FDCAN_TXBTO_TO_Msk        (0x7UL << FDCAN_TXBTO_TO_Pos)                /*!< 0x00000007 */
+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                    */
+
+/*****************  Bit definition for FDCAN_TXBCF register  *********************/
+#define FDCAN_TXBCF_CF_Pos        (0U)
+#define FDCAN_TXBCF_CF_Msk        (0x7UL << FDCAN_TXBCF_CF_Pos)                /*!< 0x00000007 */
+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                    */
+
+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/
+#define FDCAN_TXBTIE_TIE_Pos      (0U)
+#define FDCAN_TXBTIE_TIE_Msk      (0x7UL << FDCAN_TXBTIE_TIE_Pos)              /*!< 0x00000007 */
+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable            */
+
+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
+#define FDCAN_TXBCIE_CFIE_Pos     (0U)
+#define FDCAN_TXBCIE_CFIE_Msk     (0x7UL << FDCAN_TXBCIE_CFIE_Pos)             /*!< 0x00000007 */
+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable   */
+
+/*****************  Bit definition for FDCAN_TXEFS register  *********************/
+#define FDCAN_TXEFS_EFFL_Pos      (0U)
+#define FDCAN_TXEFS_EFFL_Msk      (0x7UL << FDCAN_TXEFS_EFFL_Pos)              /*!< 0x00000007 */
+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                    */
+#define FDCAN_TXEFS_EFGI_Pos      (8U)
+#define FDCAN_TXEFS_EFGI_Msk      (0x3UL << FDCAN_TXEFS_EFGI_Pos)              /*!< 0x00000300 */
+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                     */
+#define FDCAN_TXEFS_EFPI_Pos      (16U)
+#define FDCAN_TXEFS_EFPI_Msk      (0x3UL << FDCAN_TXEFS_EFPI_Pos)              /*!< 0x00030000 */
+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                     */
+#define FDCAN_TXEFS_EFF_Pos       (24U)
+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                          */
+#define FDCAN_TXEFS_TEFL_Pos      (25U)
+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost               */
+
+/*****************  Bit definition for FDCAN_TXEFA register  *********************/
+#define FDCAN_TXEFA_EFAI_Pos      (0U)
+#define FDCAN_TXEFA_EFAI_Msk      (0x3UL << FDCAN_TXEFA_EFAI_Pos)              /*!< 0x00000003 */
+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index             */
+
+
+/*!<FDCAN config registers */
+/*****************  Bit definition for FDCAN_CKDIV register  *********************/
+#define FDCAN_CKDIV_PDIV_Pos      (0U)
+#define FDCAN_CKDIV_PDIV_Msk      (0xFUL << FDCAN_CKDIV_PDIV_Pos)              /*!< 0x0000000F */
+#define FDCAN_CKDIV_PDIV          FDCAN_CKDIV_PDIV_Msk                         /*!<Input Clock Divider                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY_Pos             (0U)
+#define FLASH_ACR_LATENCY_Msk             (0xFUL << FLASH_ACR_LATENCY_Pos)     /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS             (0x00000000U)
+#define FLASH_ACR_LATENCY_1WS             (0x00000001U)
+#define FLASH_ACR_LATENCY_2WS             (0x00000002U)
+#define FLASH_ACR_LATENCY_3WS             (0x00000003U)
+#define FLASH_ACR_LATENCY_4WS             (0x00000004U)
+#define FLASH_ACR_LATENCY_5WS             (0x00000005U)
+#define FLASH_ACR_LATENCY_6WS             (0x00000006U)
+#define FLASH_ACR_LATENCY_7WS             (0x00000007U)
+#define FLASH_ACR_LATENCY_8WS             (0x00000008U)
+#define FLASH_ACR_LATENCY_9WS             (0x00000009U)
+#define FLASH_ACR_LATENCY_10WS            (0x0000000AU)
+#define FLASH_ACR_LATENCY_11WS            (0x0000000BU)
+#define FLASH_ACR_LATENCY_12WS            (0x0000000CU)
+#define FLASH_ACR_LATENCY_13WS            (0x0000000DU)
+#define FLASH_ACR_LATENCY_14WS            (0x0000000EU)
+#define FLASH_ACR_LATENCY_15WS            (0x0000000FU)
+#define FLASH_ACR_PRFTEN_Pos              (8U)
+#define FLASH_ACR_PRFTEN_Msk              (0x1UL << FLASH_ACR_PRFTEN_Pos)      /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos                (9U)
+#define FLASH_ACR_ICEN_Msk                (0x1UL << FLASH_ACR_ICEN_Pos)        /*!< 0x00000200 */
+#define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos                (10U)
+#define FLASH_ACR_DCEN_Msk                (0x1UL << FLASH_ACR_DCEN_Pos)        /*!< 0x00000400 */
+#define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos               (11U)
+#define FLASH_ACR_ICRST_Msk               (0x1UL << FLASH_ACR_ICRST_Pos)       /*!< 0x00000800 */
+#define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos               (12U)
+#define FLASH_ACR_DCRST_Msk               (0x1UL << FLASH_ACR_DCRST_Pos)       /*!< 0x00001000 */
+#define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_RUN_PD_Pos              (13U)
+#define FLASH_ACR_RUN_PD_Msk              (0x1UL << FLASH_ACR_RUN_PD_Pos)      /*!< 0x00002000 */
+#define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
+#define FLASH_ACR_SLEEP_PD_Pos            (14U)
+#define FLASH_ACR_SLEEP_PD_Msk            (0x1UL << FLASH_ACR_SLEEP_PD_Pos)    /*!< 0x00004000 */
+#define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
+#define FLASH_ACR_DBG_SWEN_Pos            (18U)
+#define FLASH_ACR_DBG_SWEN_Msk            (0x1UL << FLASH_ACR_DBG_SWEN_Pos)    /*!< 0x00040000 */
+#define FLASH_ACR_DBG_SWEN                FLASH_ACR_DBG_SWEN_Msk               /*!< Software disable for debugger */
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP_Pos                  (0U)
+#define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)          /*!< 0x00000001 */
+#define FLASH_SR_EOP                      FLASH_SR_EOP_Msk
+#define FLASH_SR_OPERR_Pos                (1U)
+#define FLASH_SR_OPERR_Msk                (0x1UL << FLASH_SR_OPERR_Pos)        /*!< 0x00000002 */
+#define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk
+#define FLASH_SR_PROGERR_Pos              (3U)
+#define FLASH_SR_PROGERR_Msk              (0x1UL << FLASH_SR_PROGERR_Pos)      /*!< 0x00000008 */
+#define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk
+#define FLASH_SR_WRPERR_Pos               (4U)
+#define FLASH_SR_WRPERR_Msk               (0x1UL << FLASH_SR_WRPERR_Pos)       /*!< 0x00000010 */
+#define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos               (5U)
+#define FLASH_SR_PGAERR_Msk               (0x1UL << FLASH_SR_PGAERR_Pos)       /*!< 0x00000020 */
+#define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk
+#define FLASH_SR_SIZERR_Pos               (6U)
+#define FLASH_SR_SIZERR_Msk               (0x1UL << FLASH_SR_SIZERR_Pos)       /*!< 0x00000040 */
+#define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk
+#define FLASH_SR_PGSERR_Pos               (7U)
+#define FLASH_SR_PGSERR_Msk               (0x1UL << FLASH_SR_PGSERR_Pos)       /*!< 0x00000080 */
+#define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk
+#define FLASH_SR_MISERR_Pos               (8U)
+#define FLASH_SR_MISERR_Msk               (0x1UL << FLASH_SR_MISERR_Pos)       /*!< 0x00000100 */
+#define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk
+#define FLASH_SR_FASTERR_Pos              (9U)
+#define FLASH_SR_FASTERR_Msk              (0x1UL << FLASH_SR_FASTERR_Pos)      /*!< 0x00000200 */
+#define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk
+#define FLASH_SR_RDERR_Pos                (14U)
+#define FLASH_SR_RDERR_Msk                (0x1UL << FLASH_SR_RDERR_Pos)        /*!< 0x00004000 */
+#define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk
+#define FLASH_SR_OPTVERR_Pos              (15U)
+#define FLASH_SR_OPTVERR_Msk              (0x1UL << FLASH_SR_OPTVERR_Pos)      /*!< 0x00008000 */
+#define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk
+#define FLASH_SR_BSY_Pos                  (16U)
+#define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)          /*!< 0x00010000 */
+#define FLASH_SR_BSY                      FLASH_SR_BSY_Msk
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG_Pos                   (0U)
+#define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)           /*!< 0x00000001 */
+#define FLASH_CR_PG                       FLASH_CR_PG_Msk
+#define FLASH_CR_PER_Pos                  (1U)
+#define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)          /*!< 0x00000002 */
+#define FLASH_CR_PER                      FLASH_CR_PER_Msk
+#define FLASH_CR_MER1_Pos                 (2U)
+#define FLASH_CR_MER1_Msk                 (0x1UL << FLASH_CR_MER1_Pos)         /*!< 0x00000004 */
+#define FLASH_CR_MER1                     FLASH_CR_MER1_Msk
+#define FLASH_CR_PNB_Pos                  (3U)
+#define FLASH_CR_PNB_Msk                  (0x3FUL << FLASH_CR_PNB_Pos)         /*!< 0x000001F8 */
+#define FLASH_CR_PNB                      FLASH_CR_PNB_Msk
+#define FLASH_CR_STRT_Pos                 (16U)
+#define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)         /*!< 0x00010000 */
+#define FLASH_CR_STRT                     FLASH_CR_STRT_Msk
+#define FLASH_CR_OPTSTRT_Pos              (17U)
+#define FLASH_CR_OPTSTRT_Msk              (0x1UL << FLASH_CR_OPTSTRT_Pos)      /*!< 0x00020000 */
+#define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk
+#define FLASH_CR_FSTPG_Pos                (18U)
+#define FLASH_CR_FSTPG_Msk                (0x1UL << FLASH_CR_FSTPG_Pos)        /*!< 0x00040000 */
+#define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk
+#define FLASH_CR_EOPIE_Pos                (24U)
+#define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)        /*!< 0x01000000 */
+#define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk
+#define FLASH_CR_ERRIE_Pos                (25U)
+#define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)        /*!< 0x02000000 */
+#define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk
+#define FLASH_CR_RDERRIE_Pos              (26U)
+#define FLASH_CR_RDERRIE_Msk              (0x1UL << FLASH_CR_RDERRIE_Pos)      /*!< 0x04000000 */
+#define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk
+#define FLASH_CR_OBL_LAUNCH_Pos           (27U)
+#define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)   /*!< 0x08000000 */
+#define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk
+#define FLASH_CR_SEC_PROT1_Pos            (28U)
+#define FLASH_CR_SEC_PROT1_Msk            (0x1UL << FLASH_CR_SEC_PROT1_Pos)    /*!< 0x10000000 */
+#define FLASH_CR_SEC_PROT1                FLASH_CR_SEC_PROT1_Msk
+#define FLASH_CR_OPTLOCK_Pos              (30U)
+#define FLASH_CR_OPTLOCK_Msk              (0x1UL << FLASH_CR_OPTLOCK_Pos)      /*!< 0x40000000 */
+#define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk
+#define FLASH_CR_LOCK_Pos                 (31U)
+#define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)         /*!< 0x80000000 */
+#define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk
+
+/*******************  Bits definition for FLASH_ECCR register  ***************/
+#define FLASH_ECCR_ADDR_ECC_Pos           (0U)
+#define FLASH_ECCR_ADDR_ECC_Msk           (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0003FFFF */
+#define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk
+#define FLASH_ECCR_SYSF_ECC_Pos           (22U)
+#define FLASH_ECCR_SYSF_ECC_Msk           (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)   /*!< 0x00400000 */
+#define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk
+#define FLASH_ECCR_ECCIE_Pos              (24U)
+#define FLASH_ECCR_ECCIE_Msk              (0x1UL << FLASH_ECCR_ECCIE_Pos)      /*!< 0x01000000 */
+#define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk
+#define FLASH_ECCR_ECCC_Pos               (30U)
+#define FLASH_ECCR_ECCC_Msk               (0x1UL << FLASH_ECCR_ECCC_Pos)       /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk
+#define FLASH_ECCR_ECCD_Pos               (31U)
+#define FLASH_ECCR_ECCD_Msk               (0x1UL << FLASH_ECCR_ECCD_Pos)       /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk
+
+/*******************  Bits definition for FLASH_OPTR register  ***************/
+#define FLASH_OPTR_RDP_Pos                (0U)
+#define FLASH_OPTR_RDP_Msk                (0xFFUL << FLASH_OPTR_RDP_Pos)       /*!< 0x000000FF */
+#define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk
+#define FLASH_OPTR_BOR_LEV_Pos            (8U)
+#define FLASH_OPTR_BOR_LEV_Msk            (0x7UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000700 */
+#define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk
+#define FLASH_OPTR_BOR_LEV_0              (0x0UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000000 */
+#define FLASH_OPTR_BOR_LEV_1              (0x1UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000100 */
+#define FLASH_OPTR_BOR_LEV_2              (0x2UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000200 */
+#define FLASH_OPTR_BOR_LEV_3              (0x3UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000300 */
+#define FLASH_OPTR_BOR_LEV_4              (0x4UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000400 */
+#define FLASH_OPTR_nRST_STOP_Pos          (12U)
+#define FLASH_OPTR_nRST_STOP_Msk          (0x1UL << FLASH_OPTR_nRST_STOP_Pos)  /*!< 0x00001000 */
+#define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk
+#define FLASH_OPTR_nRST_STDBY_Pos         (13U)
+#define FLASH_OPTR_nRST_STDBY_Msk         (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk
+#define FLASH_OPTR_nRST_SHDW_Pos          (14U)
+#define FLASH_OPTR_nRST_SHDW_Msk          (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)  /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk
+#define FLASH_OPTR_IWDG_SW_Pos            (16U)
+#define FLASH_OPTR_IWDG_SW_Msk            (0x1UL << FLASH_OPTR_IWDG_SW_Pos)    /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk
+#define FLASH_OPTR_IWDG_STOP_Pos          (17U)
+#define FLASH_OPTR_IWDG_STOP_Msk          (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)  /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk
+#define FLASH_OPTR_IWDG_STDBY_Pos         (18U)
+#define FLASH_OPTR_IWDG_STDBY_Msk         (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk
+#define FLASH_OPTR_WWDG_SW_Pos            (19U)
+#define FLASH_OPTR_WWDG_SW_Msk            (0x1UL << FLASH_OPTR_WWDG_SW_Pos)    /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk
+#define FLASH_OPTR_nBOOT1_Pos             (23U)
+#define FLASH_OPTR_nBOOT1_Msk             (0x1UL << FLASH_OPTR_nBOOT1_Pos)     /*!< 0x00800000 */
+#define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk
+#define FLASH_OPTR_SRAM_PE_Pos            (24U)
+#define FLASH_OPTR_SRAM_PE_Msk            (0x1UL << FLASH_OPTR_SRAM_PE_Pos)    /*!< 0x01000000 */
+#define FLASH_OPTR_SRAM_PE                FLASH_OPTR_SRAM_PE_Msk
+#define FLASH_OPTR_CCMSRAM_RST_Pos        (25U)
+#define FLASH_OPTR_CCMSRAM_RST_Msk        (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
+#define FLASH_OPTR_CCMSRAM_RST            FLASH_OPTR_CCMSRAM_RST_Msk
+#define FLASH_OPTR_nSWBOOT0_Pos           (26U)
+#define FLASH_OPTR_nSWBOOT0_Msk           (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)   /*!< 0x04000000 */
+#define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk
+#define FLASH_OPTR_nBOOT0_Pos             (27U)
+#define FLASH_OPTR_nBOOT0_Msk             (0x1UL << FLASH_OPTR_nBOOT0_Pos)     /*!< 0x08000000 */
+#define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk
+#define FLASH_OPTR_NRST_MODE_Pos          (28U)
+#define FLASH_OPTR_NRST_MODE_Msk          (0x3UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x30000000 */
+#define FLASH_OPTR_NRST_MODE              FLASH_OPTR_NRST_MODE_Msk
+#define FLASH_OPTR_NRST_MODE_0            (0x1UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x10000000 */
+#define FLASH_OPTR_NRST_MODE_1            (0x2UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x20000000 */
+#define FLASH_OPTR_IRHEN_Pos              (30U)
+#define FLASH_OPTR_IRHEN_Msk              (0x1UL << FLASH_OPTR_IRHEN_Pos)      /*!< 0x40000000 */
+#define FLASH_OPTR_IRHEN                  FLASH_OPTR_IRHEN_Msk
+
+/******************  Bits definition for FLASH_PCROP1SR register  **********/
+#define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)
+#define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0x3FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00003FFF */
+#define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk
+
+/******************  Bits definition for FLASH_PCROP1ER register  ***********/
+#define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)
+#define FLASH_PCROP1ER_PCROP1_END_Msk     (0x3FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00003FFF */
+#define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk
+#define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)
+#define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
+#define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk
+
+/******************  Bits definition for FLASH_WRP1AR register  ***************/
+#define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)
+#define FLASH_WRP1AR_WRP1A_STRT_Msk       (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000003F */
+#define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk
+#define FLASH_WRP1AR_WRP1A_END_Pos        (16U)
+#define FLASH_WRP1AR_WRP1A_END_Msk        (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x003F0000 */
+#define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk
+
+/******************  Bits definition for FLASH_WRPB1R register  ***************/
+#define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)
+#define FLASH_WRP1BR_WRP1B_STRT_Msk       (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000003F */
+#define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk
+#define FLASH_WRP1BR_WRP1B_END_Pos        (16U)
+#define FLASH_WRP1BR_WRP1B_END_Msk        (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x003F0000 */
+#define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk
+
+
+/******************  Bits definition for FLASH_SEC1R register  **************/
+#define FLASH_SEC1R_SEC_SIZE1_Pos         (0U)
+#define FLASH_SEC1R_SEC_SIZE1_Msk         (0x7FUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x0000007F */
+#define FLASH_SEC1R_SEC_SIZE1             FLASH_SEC1R_SEC_SIZE1_Msk
+#define FLASH_SEC1R_BOOT_LOCK_Pos         (16U)
+#define FLASH_SEC1R_BOOT_LOCK_Msk         (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
+#define FLASH_SEC1R_BOOT_LOCK             FLASH_SEC1R_BOOT_LOCK_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                Filter Mathematical ACcelerator unit (FMAC)                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for FMAC_X1BUFCFG register  ****************/
+#define FMAC_X1BUFCFG_X1_BASE_Pos     (0U)
+#define FMAC_X1BUFCFG_X1_BASE_Msk     (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)    /*!< 0x000000FF */
+#define FMAC_X1BUFCFG_X1_BASE         FMAC_X1BUFCFG_X1_BASE_Msk                /*!< Base address of X1 buffer */
+#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
+#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
+#define FMAC_X1BUFCFG_X1_BUF_SIZE     FMAC_X1BUFCFG_X1_BUF_SIZE_Msk            /*!< Allocated size of X1 buffer in 16-bit words */
+#define FMAC_X1BUFCFG_FULL_WM_Pos     (24U)
+#define FMAC_X1BUFCFG_FULL_WM_Msk     (0x3UL  << FMAC_X1BUFCFG_FULL_WM_Pos)    /*!< 0x03000000 */
+#define FMAC_X1BUFCFG_FULL_WM         FMAC_X1BUFCFG_FULL_WM_Msk                /*!< Watermark for buffer full flag */
+/*****************  Bit definition for FMAC_X2BUFCFG register  ****************/
+#define FMAC_X2BUFCFG_X2_BASE_Pos     (0U)
+#define FMAC_X2BUFCFG_X2_BASE_Msk     (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)    /*!< 0x000000FF */
+#define FMAC_X2BUFCFG_X2_BASE         FMAC_X2BUFCFG_X2_BASE_Msk                /*!< Base address of X2 buffer */
+#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
+#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
+#define FMAC_X2BUFCFG_X2_BUF_SIZE     FMAC_X2BUFCFG_X2_BUF_SIZE_Msk            /*!< Size of X2 buffer in 16-bit words */
+/*****************  Bit definition for FMAC_YBUFCFG register  *****************/
+#define FMAC_YBUFCFG_Y_BASE_Pos       (0U)
+#define FMAC_YBUFCFG_Y_BASE_Msk       (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)      /*!< 0x000000FF */
+#define FMAC_YBUFCFG_Y_BASE           FMAC_YBUFCFG_Y_BASE_Msk                  /*!< Base address of Y buffer */
+#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos   (8U)
+#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk   (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)  /*!< 0x0000FF00 */
+#define FMAC_YBUFCFG_Y_BUF_SIZE       FMAC_YBUFCFG_Y_BUF_SIZE_Msk              /*!< Size of Y buffer in 16-bit words */
+#define FMAC_YBUFCFG_EMPTY_WM_Pos     (24U)
+#define FMAC_YBUFCFG_EMPTY_WM_Msk     (0x3UL  << FMAC_YBUFCFG_EMPTY_WM_Pos)    /*!< 0x03000000 */
+#define FMAC_YBUFCFG_EMPTY_WM         FMAC_YBUFCFG_EMPTY_WM_Msk                /*!< Watermark for buffer empty flag */
+/******************  Bit definition for FMAC_PARAM register  ******************/
+#define FMAC_PARAM_P_Pos              (0U)
+#define FMAC_PARAM_P_Msk              (0xFFUL << FMAC_PARAM_P_Pos)             /*!< 0x000000FF */
+#define FMAC_PARAM_P                  FMAC_PARAM_P_Msk                         /*!< Input parameter P */
+#define FMAC_PARAM_Q_Pos              (8U)
+#define FMAC_PARAM_Q_Msk              (0xFFUL << FMAC_PARAM_Q_Pos)             /*!< 0x0000FF00 */
+#define FMAC_PARAM_Q                  FMAC_PARAM_Q_Msk                         /*!< Input parameter Q */
+#define FMAC_PARAM_R_Pos              (16U)
+#define FMAC_PARAM_R_Msk              (0xFFUL << FMAC_PARAM_R_Pos)             /*!< 0x00FF0000 */
+#define FMAC_PARAM_R                  FMAC_PARAM_R_Msk                         /*!< Input parameter R */
+#define FMAC_PARAM_FUNC_Pos           (24U)
+#define FMAC_PARAM_FUNC_Msk           (0x7FUL << FMAC_PARAM_FUNC_Pos)          /*!< 0x7F000000 */
+#define FMAC_PARAM_FUNC               FMAC_PARAM_FUNC_Msk                      /*!< Function */
+#define FMAC_PARAM_FUNC_0             (0x1UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x01000000 */
+#define FMAC_PARAM_FUNC_1             (0x2UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x02000000 */
+#define FMAC_PARAM_FUNC_2             (0x4UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x04000000 */
+#define FMAC_PARAM_FUNC_3             (0x8UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x08000000 */
+#define FMAC_PARAM_FUNC_4             (0x10UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x10000000 */
+#define FMAC_PARAM_FUNC_5             (0x20UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x20000000 */
+#define FMAC_PARAM_FUNC_6             (0x40UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x40000000 */
+#define FMAC_PARAM_START_Pos          (31U)
+#define FMAC_PARAM_START_Msk          (0x1UL  << FMAC_PARAM_START_Pos)         /*!< 0x80000000 */
+#define FMAC_PARAM_START              FMAC_PARAM_START_Msk                     /*!< Enable execution */
+/********************  Bit definition for FMAC_CR register  *******************/
+#define FMAC_CR_RIEN_Pos              (0U)
+#define FMAC_CR_RIEN_Msk              (0x1UL  << FMAC_CR_RIEN_Pos)             /*!< 0x00000001 */
+#define FMAC_CR_RIEN                  FMAC_CR_RIEN_Msk                         /*!< Enable read interrupt */
+#define FMAC_CR_WIEN_Pos              (1U)
+#define FMAC_CR_WIEN_Msk              (0x1UL  << FMAC_CR_WIEN_Pos)             /*!< 0x00000002 */
+#define FMAC_CR_WIEN                  FMAC_CR_WIEN_Msk                         /*!< Enable write interrupt */
+#define FMAC_CR_OVFLIEN_Pos           (2U)
+#define FMAC_CR_OVFLIEN_Msk           (0x1UL  << FMAC_CR_OVFLIEN_Pos)          /*!< 0x00000004 */
+#define FMAC_CR_OVFLIEN               FMAC_CR_OVFLIEN_Msk                      /*!< Enable overflow error interrupts */
+#define FMAC_CR_UNFLIEN_Pos           (3U)
+#define FMAC_CR_UNFLIEN_Msk           (0x1UL  << FMAC_CR_UNFLIEN_Pos)          /*!< 0x00000008 */
+#define FMAC_CR_UNFLIEN               FMAC_CR_UNFLIEN_Msk                      /*!< Enable underflow error interrupts */
+#define FMAC_CR_SATIEN_Pos            (4U)
+#define FMAC_CR_SATIEN_Msk            (0x1UL  << FMAC_CR_SATIEN_Pos)           /*!< 0x00000010 */
+#define FMAC_CR_SATIEN                FMAC_CR_SATIEN_Msk                       /*!< Enable saturation error interrupts */
+#define FMAC_CR_DMAREN_Pos            (8U)
+#define FMAC_CR_DMAREN_Msk            (0x1UL  << FMAC_CR_DMAREN_Pos)           /*!< 0x00000100 */
+#define FMAC_CR_DMAREN                FMAC_CR_DMAREN_Msk                       /*!< Enable DMA read channel requests */
+#define FMAC_CR_DMAWEN_Pos            (9U)
+#define FMAC_CR_DMAWEN_Msk            (0x1UL  << FMAC_CR_DMAWEN_Pos)           /*!< 0x00000200 */
+#define FMAC_CR_DMAWEN                FMAC_CR_DMAWEN_Msk                       /*!< Enable DMA write channel requests */
+#define FMAC_CR_CLIPEN_Pos            (15U)
+#define FMAC_CR_CLIPEN_Msk            (0x1UL  << FMAC_CR_CLIPEN_Pos)           /*!< 0x00008000 */
+#define FMAC_CR_CLIPEN                FMAC_CR_CLIPEN_Msk                       /*!< Enable clipping */
+#define FMAC_CR_RESET_Pos             (16U)
+#define FMAC_CR_RESET_Msk             (0x1UL  << FMAC_CR_RESET_Pos)            /*!< 0x00010000 */
+#define FMAC_CR_RESET                 FMAC_CR_RESET_Msk                        /*!< Reset filter mathematical accelerator unit */
+/*******************  Bit definition for FMAC_SR register  ********************/
+#define FMAC_SR_YEMPTY_Pos            (0U)
+#define FMAC_SR_YEMPTY_Msk            (0x1UL  << FMAC_SR_YEMPTY_Pos)           /*!< 0x00000001 */
+#define FMAC_SR_YEMPTY                FMAC_SR_YEMPTY_Msk                       /*!< Y buffer empty flag */
+#define FMAC_SR_X1FULL_Pos            (1U)
+#define FMAC_SR_X1FULL_Msk            (0x1UL  << FMAC_SR_X1FULL_Pos)           /*!< 0x00000002 */
+#define FMAC_SR_X1FULL                FMAC_SR_X1FULL_Msk                       /*!< X1 buffer full flag */
+#define FMAC_SR_OVFL_Pos              (8U)
+#define FMAC_SR_OVFL_Msk              (0x1UL  << FMAC_SR_OVFL_Pos)             /*!< 0x00000100 */
+#define FMAC_SR_OVFL                  FMAC_SR_OVFL_Msk                         /*!< Overflow error flag */
+#define FMAC_SR_UNFL_Pos              (9U)
+#define FMAC_SR_UNFL_Msk              (0x1UL  << FMAC_SR_UNFL_Pos)             /*!< 0x00000200 */
+#define FMAC_SR_UNFL                  FMAC_SR_UNFL_Msk                         /*!< Underflow error flag */
+#define FMAC_SR_SAT_Pos               (10U)
+#define FMAC_SR_SAT_Msk               (0x1UL  << FMAC_SR_SAT_Pos)              /*!< 0x00000400 */
+#define FMAC_SR_SAT                   FMAC_SR_SAT_Msk                          /*!< Saturation error flag */
+/******************  Bit definition for FMAC_WDATA register  ******************/
+#define FMAC_WDATA_WDATA_Pos          (0U)
+#define FMAC_WDATA_WDATA_Msk          (0xFFFFUL << FMAC_WDATA_WDATA_Pos)       /*!< 0x0000FFFF */
+#define FMAC_WDATA_WDATA              FMAC_WDATA_WDATA_Msk                     /*!< Write data */
+/******************  Bit definition for FMACX_RDATA register  *****************/
+#define FMAC_RDATA_RDATA_Pos          (0U)
+#define FMAC_RDATA_RDATA_Msk          (0xFFFFUL << FMAC_RDATA_RDATA_Pos)       /*!< 0x0000FFFF */
+#define FMAC_RDATA_RDATA              FMAC_RDATA_RDATA_Msk                     /*!< Read data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)
+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos           (2U)
+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos           (4U)
+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos           (6U)
+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos           (8U)
+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos           (10U)
+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos           (12U)
+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos           (14U)
+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos           (16U)
+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos           (18U)
+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos          (20U)
+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos          (22U)
+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos          (24U)
+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos          (26U)
+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos          (28U)
+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos          (30U)
+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
+#define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
+#define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
+#define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
+#define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
+#define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
+#define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
+#define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
+#define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
+#define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
+#define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
+#define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
+#define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
+#define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
+#define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
+#define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
+#define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
+#define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
+#define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
+#define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
+#define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
+#define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
+#define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
+#define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
+#define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
+#define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
+#define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
+#define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
+#define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
+#define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
+#define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
+#define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
+#define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
+#define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
+#define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
+#define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
+#define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
+#define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
+#define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
+#define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
+#define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
+#define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
+#define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
+#define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
+#define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
+#define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
+#define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
+#define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)
+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos            (1U)
+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos            (2U)
+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos            (3U)
+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos            (4U)
+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos            (5U)
+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos            (6U)
+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos            (7U)
+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos            (8U)
+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos            (9U)
+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos           (10U)
+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos           (11U)
+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos           (12U)
+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos           (13U)
+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos           (14U)
+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos           (15U)
+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)
+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos           (2U)
+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos           (4U)
+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos           (6U)
+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos           (8U)
+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos           (10U)
+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos           (12U)
+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos           (14U)
+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos           (16U)
+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos           (18U)
+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos          (20U)
+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos          (22U)
+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos          (24U)
+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos          (26U)
+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos          (28U)
+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos          (30U)
+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)
+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos               (1U)
+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos               (2U)
+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos               (3U)
+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos               (4U)
+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos               (5U)
+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos               (6U)
+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos               (7U)
+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos               (8U)
+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos               (9U)
+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos              (10U)
+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos              (11U)
+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos              (12U)
+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos              (13U)
+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos              (14U)
+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos              (15U)
+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
+
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
+#define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
+#define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
+#define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
+#define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
+#define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
+#define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
+#define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
+#define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
+#define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
+#define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
+#define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
+#define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
+#define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
+#define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
+#define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)
+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos               (1U)
+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos               (2U)
+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos               (3U)
+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos               (4U)
+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos               (5U)
+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos               (6U)
+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos               (7U)
+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos               (8U)
+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos               (9U)
+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos              (10U)
+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos              (11U)
+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos              (12U)
+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos              (13U)
+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos              (14U)
+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos              (15U)
+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
+
+/* Legacy defines */
+#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
+
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
+#define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
+#define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
+#define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
+#define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
+#define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
+#define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
+#define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
+#define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
+#define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
+#define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
+#define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
+#define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
+#define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
+#define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
+#define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)
+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos              (1U)
+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos              (2U)
+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos              (3U)
+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos              (4U)
+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos              (5U)
+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos              (6U)
+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos              (7U)
+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos              (8U)
+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos              (9U)
+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos             (10U)
+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos             (11U)
+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos             (12U)
+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos             (13U)
+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos             (14U)
+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos             (15U)
+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos              (16U)
+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos              (17U)
+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos              (18U)
+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos              (19U)
+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos              (20U)
+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos              (21U)
+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos              (22U)
+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos              (23U)
+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos              (24U)
+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos              (25U)
+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos             (26U)
+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos             (27U)
+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos             (28U)
+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos             (29U)
+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos             (30U)
+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos             (31U)
+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)
+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos             (1U)
+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos             (2U)
+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos             (3U)
+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos             (4U)
+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos             (5U)
+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos             (6U)
+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos             (7U)
+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos             (8U)
+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos             (9U)
+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos            (10U)
+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos            (11U)
+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos            (12U)
+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos            (13U)
+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos            (14U)
+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos            (15U)
+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos             (16U)
+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)
+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)
+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)
+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)
+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)
+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)
+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)
+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)
+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)
+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)
+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)
+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)
+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)
+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)
+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)
+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)
+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos               (0U)
+#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
+#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos               (1U)
+#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
+#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos               (2U)
+#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
+#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos               (3U)
+#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
+#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos               (4U)
+#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
+#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos               (5U)
+#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
+#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos               (6U)
+#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
+#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos               (7U)
+#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
+#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos               (8U)
+#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
+#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos               (9U)
+#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
+#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos              (10U)
+#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
+#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos              (11U)
+#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
+#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos              (12U)
+#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
+#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos              (13U)
+#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
+#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos              (14U)
+#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
+#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos              (15U)
+#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
+#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BRR_BR_0                       GPIO_BRR_BR0
+#define GPIO_BRR_BR_1                       GPIO_BRR_BR1
+#define GPIO_BRR_BR_2                       GPIO_BRR_BR2
+#define GPIO_BRR_BR_3                       GPIO_BRR_BR3
+#define GPIO_BRR_BR_4                       GPIO_BRR_BR4
+#define GPIO_BRR_BR_5                       GPIO_BRR_BR5
+#define GPIO_BRR_BR_6                       GPIO_BRR_BR6
+#define GPIO_BRR_BR_7                       GPIO_BRR_BR7
+#define GPIO_BRR_BR_8                       GPIO_BRR_BR8
+#define GPIO_BRR_BR_9                       GPIO_BRR_BR9
+#define GPIO_BRR_BR_10                      GPIO_BRR_BR10
+#define GPIO_BRR_BR_11                      GPIO_BRR_BR11
+#define GPIO_BRR_BR_12                      GPIO_BRR_BR12
+#define GPIO_BRR_BR_13                      GPIO_BRR_BR13
+#define GPIO_BRR_BR_14                      GPIO_BRR_BR14
+#define GPIO_BRR_BR_15                      GPIO_BRR_BR15
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)
+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
+#define I2C_CR1_TXIE_Pos             (1U)
+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
+#define I2C_CR1_RXIE_Pos             (2U)
+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
+#define I2C_CR1_ADDRIE_Pos           (3U)
+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
+#define I2C_CR1_NACKIE_Pos           (4U)
+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
+#define I2C_CR1_STOPIE_Pos           (5U)
+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
+#define I2C_CR1_TCIE_Pos             (6U)
+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
+#define I2C_CR1_ERRIE_Pos            (7U)
+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
+#define I2C_CR1_DNF_Pos              (8U)
+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
+#define I2C_CR1_ANFOFF_Pos           (12U)
+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
+#define I2C_CR1_SWRST_Pos            (13U)
+#define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
+#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
+#define I2C_CR1_TXDMAEN_Pos          (14U)
+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
+#define I2C_CR1_RXDMAEN_Pos          (15U)
+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
+#define I2C_CR1_SBC_Pos              (16U)
+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)
+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
+#define I2C_CR1_WUPEN_Pos            (18U)
+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
+#define I2C_CR1_GCEN_Pos             (19U)
+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
+#define I2C_CR1_SMBHEN_Pos           (20U)
+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
+#define I2C_CR1_SMBDEN_Pos           (21U)
+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)
+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
+#define I2C_CR1_PECEN_Pos            (23U)
+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)
+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
+#define I2C_CR2_RD_WRN_Pos           (10U)
+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
+#define I2C_CR2_ADD10_Pos            (11U)
+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
+#define I2C_CR2_HEAD10R_Pos          (12U)
+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)
+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
+#define I2C_CR2_STOP_Pos             (14U)
+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
+#define I2C_CR2_NACK_Pos             (15U)
+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
+#define I2C_CR2_NBYTES_Pos           (16U)
+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
+#define I2C_CR2_RELOAD_Pos           (24U)
+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
+#define I2C_CR2_AUTOEND_Pos          (25U)
+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
+#define I2C_CR2_PECBYTE_Pos          (26U)
+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)
+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
+#define I2C_OAR1_OA1MODE_Pos         (10U)
+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)
+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)
+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
+#define I2C_OAR2_OA2MSK_Pos          (8U)
+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
+#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)
+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)
+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)
+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)
+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)
+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)
+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)
+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos           (15U)
+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)
+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
+#define I2C_TIMINGR_SCLH_Pos         (8U)
+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)
+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
+#define I2C_TIMINGR_PRESC_Pos        (28U)
+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)
+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
+#define I2C_ISR_TXIS_Pos             (1U)
+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
+#define I2C_ISR_RXNE_Pos             (2U)
+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)
+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
+#define I2C_ISR_NACKF_Pos            (4U)
+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
+#define I2C_ISR_STOPF_Pos            (5U)
+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
+#define I2C_ISR_TC_Pos               (6U)
+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)
+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
+#define I2C_ISR_BERR_Pos             (8U)
+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
+#define I2C_ISR_ARLO_Pos             (9U)
+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
+#define I2C_ISR_OVR_Pos              (10U)
+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
+#define I2C_ISR_PECERR_Pos           (11U)
+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
+#define I2C_ISR_TIMEOUT_Pos          (12U)
+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
+#define I2C_ISR_ALERT_Pos            (13U)
+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
+#define I2C_ISR_BUSY_Pos             (15U)
+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
+#define I2C_ISR_DIR_Pos              (16U)
+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)
+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)
+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
+#define I2C_ICR_NACKCF_Pos           (4U)
+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
+#define I2C_ICR_STOPCF_Pos           (5U)
+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
+#define I2C_ICR_BERRCF_Pos           (8U)
+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
+#define I2C_ICR_ARLOCF_Pos           (9U)
+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)
+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)
+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)
+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
+#define I2C_ICR_ALERTCF_Pos          (13U)
+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)
+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)
+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)
+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)
+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)
+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)
+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)
+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)
+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)
+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)
+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos       (0U)
+#define OPAMP_CSR_OPAMPxEN_Msk       (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)         /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN           OPAMP_CSR_OPAMPxEN_Msk                    /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP_Pos        (1U)
+#define OPAMP_CSR_FORCEVP_Msk        (0x1UL << OPAMP_CSR_FORCEVP_Pos)          /*!< 0x00000002 */
+#define OPAMP_CSR_FORCEVP            OPAMP_CSR_FORCEVP_Msk                     /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP_CSR_VPSEL_Pos          (2U)
+#define OPAMP_CSR_VPSEL_Msk          (0x3UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x0000000C */
+#define OPAMP_CSR_VPSEL              OPAMP_CSR_VPSEL_Msk                       /*!< Non inverting input selection */
+#define OPAMP_CSR_VPSEL_0            (0x1UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x00000004 */
+#define OPAMP_CSR_VPSEL_1            (0x2UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x00000008 */
+#define OPAMP_CSR_USERTRIM_Pos       (4U)
+#define OPAMP_CSR_USERTRIM_Msk       (0x1UL << OPAMP_CSR_USERTRIM_Pos)         /*!< 0x00000010 */
+#define OPAMP_CSR_USERTRIM           OPAMP_CSR_USERTRIM_Msk                    /*!< User trimming enable */
+#define OPAMP_CSR_VMSEL_Pos          (5U)
+#define OPAMP_CSR_VMSEL_Msk          (0x3UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000060 */
+#define OPAMP_CSR_VMSEL              OPAMP_CSR_VMSEL_Msk                       /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0            (0x1UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000020 */
+#define OPAMP_CSR_VMSEL_1            (0x2UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000040 */
+#define OPAMP_CSR_HIGHSPEEDEN_Pos    (7U)
+#define OPAMP_CSR_HIGHSPEEDEN_Msk    (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos)      /*!< 0x00000080 */
+#define OPAMP_CSR_HIGHSPEEDEN        OPAMP_CSR_HIGHSPEEDEN_Msk                 /*!< High speed mode enable */
+#define OPAMP_CSR_OPAMPINTEN_Pos     (8U)
+#define OPAMP_CSR_OPAMPINTEN_Msk     (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos)       /*!< 0x00000100 */
+#define OPAMP_CSR_OPAMPINTEN         OPAMP_CSR_OPAMPINTEN_Msk                  /*!< Internal output enable */
+#define OPAMP_CSR_CALON_Pos          (11U)
+#define OPAMP_CSR_CALON_Msk          (0x1UL << OPAMP_CSR_CALON_Pos)            /*!< 0x00000800 */
+#define OPAMP_CSR_CALON              OPAMP_CSR_CALON_Msk                       /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL_Pos         (12U)
+#define OPAMP_CSR_CALSEL_Msk         (0x3UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00003000 */
+#define OPAMP_CSR_CALSEL             OPAMP_CSR_CALSEL_Msk                      /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0           (0x1UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00001000 */
+#define OPAMP_CSR_CALSEL_1           (0x2UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00002000 */
+#define OPAMP_CSR_PGGAIN_Pos         (14U)
+#define OPAMP_CSR_PGGAIN_Msk         (0x1FUL << OPAMP_CSR_PGGAIN_Pos)          /*!< 0x0007C000 */
+#define OPAMP_CSR_PGGAIN             OPAMP_CSR_PGGAIN_Msk                      /*!< Gain in PGA mode */
+#define OPAMP_CSR_PGGAIN_0           (0x1UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00004000 */
+#define OPAMP_CSR_PGGAIN_1           (0x2UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00008000 */
+#define OPAMP_CSR_PGGAIN_2           (0x4UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00010000 */
+#define OPAMP_CSR_PGGAIN_3           (0x8UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00020000 */
+#define OPAMP_CSR_PGGAIN_4           (0x10UL << OPAMP_CSR_PGGAIN_Pos)          /*!< 0x00040000 */
+#define OPAMP_CSR_TRIMOFFSETP_Pos    (19U)
+#define OPAMP_CSR_TRIMOFFSETP_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)     /*!< 0x00F80000 */
+#define OPAMP_CSR_TRIMOFFSETP        OPAMP_CSR_TRIMOFFSETP_Msk                 /*!< Offset trimming value (PMOS) */
+#define OPAMP_CSR_TRIMOFFSETN_Pos    (24U)
+#define OPAMP_CSR_TRIMOFFSETN_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)     /*!< 0x1F000000 */
+#define OPAMP_CSR_TRIMOFFSETN        OPAMP_CSR_TRIMOFFSETN_Msk                 /*!< Offset trimming value (NMOS) */
+#define OPAMP_CSR_OUTCAL_Pos         (30U)
+#define OPAMP_CSR_OUTCAL_Msk         (0x1UL << OPAMP_CSR_OUTCAL_Pos)           /*!< 0x40000000 */
+#define OPAMP_CSR_OUTCAL             OPAMP_CSR_OUTCAL_Msk                      /*!< OPAMP ouput status flag */
+#define OPAMP_CSR_LOCK_Pos           (31U)
+#define OPAMP_CSR_LOCK_Msk           (0x1UL << OPAMP_CSR_LOCK_Pos)             /*!< 0x80000000 */
+#define OPAMP_CSR_LOCK               OPAMP_CSR_LOCK_Msk                        /*!< OPAMP control/status register lock */
+
+/*********************  Bit definition for OPAMPx_TCMR register  ***************/
+
+#define OPAMP_TCMR_VMSSEL_Pos        (0U)
+#define OPAMP_TCMR_VMSSEL_Msk        (0x1UL << OPAMP_TCMR_VMSSEL_Pos)          /*!< 0x00000001 */
+#define OPAMP_TCMR_VMSSEL            OPAMP_TCMR_VMSSEL_Msk                     /*!< Secondary inverting input selection */
+#define OPAMP_TCMR_VPSSEL_Pos        (1U)
+#define OPAMP_TCMR_VPSSEL_Msk        (0x3UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000006 */
+#define OPAMP_TCMR_VPSSEL            OPAMP_TCMR_VPSSEL_Msk                     /*!< Secondary non inverting input selection */
+#define OPAMP_TCMR_VPSSEL_0          (0x1UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000002 */
+#define OPAMP_TCMR_VPSSEL_1          (0x2UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000004 */
+#define OPAMP_TCMR_T1CMEN_Pos        (3U)
+#define OPAMP_TCMR_T1CMEN_Msk        (0x1UL << OPAMP_TCMR_T1CMEN_Pos)          /*!< 0x00000008 */
+#define OPAMP_TCMR_T1CMEN            OPAMP_TCMR_T1CMEN_Msk                     /*!< Timer 1 controlled mux mode enable */
+#define OPAMP_TCMR_T8CMEN_Pos        (4U)
+#define OPAMP_TCMR_T8CMEN_Msk        (0x1UL << OPAMP_TCMR_T8CMEN_Pos)          /*!< 0x00000010 */
+#define OPAMP_TCMR_T8CMEN            OPAMP_TCMR_T8CMEN_Msk                     /*!< Timer 8 controlled mux mode enable */
+#define OPAMP_TCMR_T20CMEN_Pos       (5U)
+#define OPAMP_TCMR_T20CMEN_Msk       (0x1UL << OPAMP_TCMR_T20CMEN_Pos)         /*!< 0x00000020 */
+#define OPAMP_TCMR_T20CMEN           OPAMP_TCMR_T20CMEN_Msk                    /*!< Timer 20 controlled mux mode enable */
+#define OPAMP_TCMR_LOCK_Pos          (31U)
+#define OPAMP_TCMR_LOCK_Msk          (0x1UL << OPAMP_TCMR_LOCK_Pos)            /*!< 0x80000000 */
+#define OPAMP_TCMR_LOCK              OPAMP_TCMR_LOCK_Msk                       /*!< OPAMP SW control register lock */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR1 register  ********************/
+
+#define PWR_CR1_LPR_Pos              (14U)
+#define PWR_CR1_LPR_Msk              (0x1UL << PWR_CR1_LPR_Pos)                /*!< 0x00004000 */
+#define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
+#define PWR_CR1_VOS_Pos              (9U)
+#define PWR_CR1_VOS_Msk              (0x3UL << PWR_CR1_VOS_Pos)                /*!< 0x00000600 */
+#define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_Pos)                /*!< 0x00000200 */
+#define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_Pos)                /*!< 0x00000400 */
+#define PWR_CR1_DBP_Pos              (8U)
+#define PWR_CR1_DBP_Msk              (0x1UL << PWR_CR1_DBP_Pos)                /*!< 0x00000100 */
+#define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
+#define PWR_CR1_LPMS_Pos             (0U)
+#define PWR_CR1_LPMS_Msk             (0x7UL << PWR_CR1_LPMS_Pos)               /*!< 0x00000007 */
+#define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
+#define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
+#define PWR_CR1_LPMS_STOP1_Pos       (0U)
+#define PWR_CR1_LPMS_STOP1_Msk       (0x1UL << PWR_CR1_LPMS_STOP1_Pos)         /*!< 0x00000001 */
+#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
+#define PWR_CR1_LPMS_STANDBY_Pos     (0U)
+#define PWR_CR1_LPMS_STANDBY_Msk     (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)       /*!< 0x00000003 */
+#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
+#define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)
+#define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)      /*!< 0x00000004 */
+#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
+
+
+/********************  Bit definition for PWR_CR2 register  ********************/
+
+/*!< PVME  Peripheral Voltage Monitor Enable */
+#define PWR_CR2_PVME_Pos             (4U)
+#define PWR_CR2_PVME_Msk             (0xFUL << PWR_CR2_PVME_Pos)               /*!< 0x000000F0 */
+#define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
+#define PWR_CR2_PVME4_Pos            (7U)
+#define PWR_CR2_PVME4_Msk            (0x1UL << PWR_CR2_PVME4_Pos)              /*!< 0x00000080 */
+#define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
+#define PWR_CR2_PVME3_Pos            (6U)
+#define PWR_CR2_PVME3_Msk            (0x1UL << PWR_CR2_PVME3_Pos)              /*!< 0x00000040 */
+#define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
+#define PWR_CR2_PVME2_Pos            (5U)
+#define PWR_CR2_PVME2_Msk            (0x1UL << PWR_CR2_PVME2_Pos)              /*!< 0x00000020 */
+#define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */
+#define PWR_CR2_PVME1_Pos            (4U)
+#define PWR_CR2_PVME1_Msk            (0x1UL << PWR_CR2_PVME1_Pos)              /*!< 0x00000010 */
+#define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
+
+/*!< PVD level configuration */
+#define PWR_CR2_PLS_Pos              (1U)
+#define PWR_CR2_PLS_Msk              (0x7UL << PWR_CR2_PLS_Pos)                /*!< 0x0000000E */
+#define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
+#define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
+#define PWR_CR2_PLS_LEV1_Pos         (1U)
+#define PWR_CR2_PLS_LEV1_Msk         (0x1UL << PWR_CR2_PLS_LEV1_Pos)           /*!< 0x00000002 */
+#define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
+#define PWR_CR2_PLS_LEV2_Pos         (2U)
+#define PWR_CR2_PLS_LEV2_Msk         (0x1UL << PWR_CR2_PLS_LEV2_Pos)           /*!< 0x00000004 */
+#define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
+#define PWR_CR2_PLS_LEV3_Pos         (1U)
+#define PWR_CR2_PLS_LEV3_Msk         (0x3UL << PWR_CR2_PLS_LEV3_Pos)           /*!< 0x00000006 */
+#define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
+#define PWR_CR2_PLS_LEV4_Pos         (3U)
+#define PWR_CR2_PLS_LEV4_Msk         (0x1UL << PWR_CR2_PLS_LEV4_Pos)           /*!< 0x00000008 */
+#define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
+#define PWR_CR2_PLS_LEV5_Pos         (1U)
+#define PWR_CR2_PLS_LEV5_Msk         (0x5UL << PWR_CR2_PLS_LEV5_Pos)           /*!< 0x0000000A */
+#define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
+#define PWR_CR2_PLS_LEV6_Pos         (2U)
+#define PWR_CR2_PLS_LEV6_Msk         (0x3UL << PWR_CR2_PLS_LEV6_Pos)           /*!< 0x0000000C */
+#define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
+#define PWR_CR2_PLS_LEV7_Pos         (1U)
+#define PWR_CR2_PLS_LEV7_Msk         (0x7UL << PWR_CR2_PLS_LEV7_Pos)           /*!< 0x0000000E */
+#define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
+#define PWR_CR2_PVDE_Pos             (0U)
+#define PWR_CR2_PVDE_Msk             (0x1UL << PWR_CR2_PVDE_Pos)               /*!< 0x00000001 */
+#define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
+
+/********************  Bit definition for PWR_CR3 register  ********************/
+#define PWR_CR3_EIWF_Pos             (15U)
+#define PWR_CR3_EIWF_Msk             (0x1UL << PWR_CR3_EIWF_Pos)               /*!< 0x00008000 */
+#define PWR_CR3_EIWF                 PWR_CR3_EIWF_Msk                          /*!< Enable Internal Wake-up line */
+#define PWR_CR3_UCPD_DBDIS_Pos       (14U)
+#define PWR_CR3_UCPD_DBDIS_Msk       (0x1UL << PWR_CR3_UCPD_DBDIS_Pos)         /*!< 0x00004000 */
+#define PWR_CR3_UCPD_DBDIS           PWR_CR3_UCPD_DBDIS_Msk                    /*!< USB Type-C and Power Delivery Dead Battery disable. */
+#define PWR_CR3_UCPD_STDBY_Pos       (13U)
+#define PWR_CR3_UCPD_STDBY_Msk       (0x1UL << PWR_CR3_UCPD_STDBY_Pos)         /*!< 0x00002000 */
+#define PWR_CR3_UCPD_STDBY           PWR_CR3_UCPD_STDBY_Msk                    /*!< USB Type-C and Power Delivery standby mode. */
+#define PWR_CR3_APC_Pos              (10U)
+#define PWR_CR3_APC_Msk              (0x1UL << PWR_CR3_APC_Pos)                /*!< 0x00000400 */
+#define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
+#define PWR_CR3_RRS_Pos              (8U)
+#define PWR_CR3_RRS_Msk              (0x1UL << PWR_CR3_RRS_Pos)                /*!< 0x00000100 */
+#define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
+#define PWR_CR3_EWUP5_Pos            (4U)
+#define PWR_CR3_EWUP5_Msk            (0x1UL << PWR_CR3_EWUP5_Pos)              /*!< 0x00000010 */
+#define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
+#define PWR_CR3_EWUP4_Pos            (3U)
+#define PWR_CR3_EWUP4_Msk            (0x1UL << PWR_CR3_EWUP4_Pos)              /*!< 0x00000008 */
+#define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
+#define PWR_CR3_EWUP3_Pos            (2U)
+#define PWR_CR3_EWUP3_Msk            (0x1UL << PWR_CR3_EWUP3_Pos)              /*!< 0x00000004 */
+#define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
+#define PWR_CR3_EWUP2_Pos            (1U)
+#define PWR_CR3_EWUP2_Msk            (0x1UL << PWR_CR3_EWUP2_Pos)              /*!< 0x00000002 */
+#define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
+#define PWR_CR3_EWUP1_Pos            (0U)
+#define PWR_CR3_EWUP1_Msk            (0x1UL << PWR_CR3_EWUP1_Pos)              /*!< 0x00000001 */
+#define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
+#define PWR_CR3_EWUP_Pos             (0U)
+#define PWR_CR3_EWUP_Msk             (0x1FUL << PWR_CR3_EWUP_Pos)              /*!< 0x0000001F */
+#define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
+
+/********************  Bit definition for PWR_CR4 register  ********************/
+#define PWR_CR4_VBRS_Pos             (9U)
+#define PWR_CR4_VBRS_Msk             (0x1UL << PWR_CR4_VBRS_Pos)               /*!< 0x00000200 */
+#define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
+#define PWR_CR4_VBE_Pos              (8U)
+#define PWR_CR4_VBE_Msk              (0x1UL << PWR_CR4_VBE_Pos)                /*!< 0x00000100 */
+#define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
+#define PWR_CR4_WP5_Pos              (4U)
+#define PWR_CR4_WP5_Msk              (0x1UL << PWR_CR4_WP5_Pos)                /*!< 0x00000010 */
+#define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
+#define PWR_CR4_WP4_Pos              (3U)
+#define PWR_CR4_WP4_Msk              (0x1UL << PWR_CR4_WP4_Pos)                /*!< 0x00000008 */
+#define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
+#define PWR_CR4_WP3_Pos              (2U)
+#define PWR_CR4_WP3_Msk              (0x1UL << PWR_CR4_WP3_Pos)                /*!< 0x00000004 */
+#define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
+#define PWR_CR4_WP2_Pos              (1U)
+#define PWR_CR4_WP2_Msk              (0x1UL << PWR_CR4_WP2_Pos)                /*!< 0x00000002 */
+#define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
+#define PWR_CR4_WP1_Pos              (0U)
+#define PWR_CR4_WP1_Msk              (0x1UL << PWR_CR4_WP1_Pos)                /*!< 0x00000001 */
+#define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
+
+/********************  Bit definition for PWR_SR1 register  ********************/
+#define PWR_SR1_WUFI_Pos             (15U)
+#define PWR_SR1_WUFI_Msk             (0x1UL << PWR_SR1_WUFI_Pos)               /*!< 0x00008000 */
+#define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
+#define PWR_SR1_SBF_Pos              (8U)
+#define PWR_SR1_SBF_Msk              (0x1UL << PWR_SR1_SBF_Pos)                /*!< 0x00000100 */
+#define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
+#define PWR_SR1_WUF_Pos              (0U)
+#define PWR_SR1_WUF_Msk              (0x1FUL << PWR_SR1_WUF_Pos)               /*!< 0x0000001F */
+#define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
+#define PWR_SR1_WUF5_Pos             (4U)
+#define PWR_SR1_WUF5_Msk             (0x1UL << PWR_SR1_WUF5_Pos)               /*!< 0x00000010 */
+#define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
+#define PWR_SR1_WUF4_Pos             (3U)
+#define PWR_SR1_WUF4_Msk             (0x1UL << PWR_SR1_WUF4_Pos)               /*!< 0x00000008 */
+#define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
+#define PWR_SR1_WUF3_Pos             (2U)
+#define PWR_SR1_WUF3_Msk             (0x1UL << PWR_SR1_WUF3_Pos)               /*!< 0x00000004 */
+#define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
+#define PWR_SR1_WUF2_Pos             (1U)
+#define PWR_SR1_WUF2_Msk             (0x1UL << PWR_SR1_WUF2_Pos)               /*!< 0x00000002 */
+#define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
+#define PWR_SR1_WUF1_Pos             (0U)
+#define PWR_SR1_WUF1_Msk             (0x1UL << PWR_SR1_WUF1_Pos)               /*!< 0x00000001 */
+#define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_SR2 register  ********************/
+#define PWR_SR2_PVMO4_Pos            (15U)
+#define PWR_SR2_PVMO4_Msk            (0x1UL << PWR_SR2_PVMO4_Pos)              /*!< 0x00008000 */
+#define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
+#define PWR_SR2_PVMO3_Pos            (14U)
+#define PWR_SR2_PVMO3_Msk            (0x1UL << PWR_SR2_PVMO3_Pos)              /*!< 0x00004000 */
+#define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
+#define PWR_SR2_PVMO2_Pos            (13U)
+#define PWR_SR2_PVMO2_Msk            (0x1UL << PWR_SR2_PVMO2_Pos)              /*!< 0x00002000 */
+#define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */
+#define PWR_SR2_PVMO1_Pos            (12U)
+#define PWR_SR2_PVMO1_Msk            (0x1UL << PWR_SR2_PVMO1_Pos)              /*!< 0x00001000 */
+#define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
+#define PWR_SR2_PVDO_Pos             (11U)
+#define PWR_SR2_PVDO_Msk             (0x1UL << PWR_SR2_PVDO_Pos)               /*!< 0x00000800 */
+#define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
+#define PWR_SR2_VOSF_Pos             (10U)
+#define PWR_SR2_VOSF_Msk             (0x1UL << PWR_SR2_VOSF_Pos)               /*!< 0x00000400 */
+#define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
+#define PWR_SR2_REGLPF_Pos           (9U)
+#define PWR_SR2_REGLPF_Msk           (0x1UL << PWR_SR2_REGLPF_Pos)             /*!< 0x00000200 */
+#define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
+#define PWR_SR2_REGLPS_Pos           (8U)
+#define PWR_SR2_REGLPS_Msk           (0x1UL << PWR_SR2_REGLPS_Pos)             /*!< 0x00000100 */
+#define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
+
+/********************  Bit definition for PWR_SCR register  ********************/
+#define PWR_SCR_CSBF_Pos             (8U)
+#define PWR_SCR_CSBF_Msk             (0x1UL << PWR_SCR_CSBF_Pos)               /*!< 0x00000100 */
+#define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
+#define PWR_SCR_CWUF_Pos             (0U)
+#define PWR_SCR_CWUF_Msk             (0x1FUL << PWR_SCR_CWUF_Pos)              /*!< 0x0000001F */
+#define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
+#define PWR_SCR_CWUF5_Pos            (4U)
+#define PWR_SCR_CWUF5_Msk            (0x1UL << PWR_SCR_CWUF5_Pos)              /*!< 0x00000010 */
+#define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
+#define PWR_SCR_CWUF4_Pos            (3U)
+#define PWR_SCR_CWUF4_Msk            (0x1UL << PWR_SCR_CWUF4_Pos)              /*!< 0x00000008 */
+#define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
+#define PWR_SCR_CWUF3_Pos            (2U)
+#define PWR_SCR_CWUF3_Msk            (0x1UL << PWR_SCR_CWUF3_Pos)              /*!< 0x00000004 */
+#define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
+#define PWR_SCR_CWUF2_Pos            (1U)
+#define PWR_SCR_CWUF2_Msk            (0x1UL << PWR_SCR_CWUF2_Pos)              /*!< 0x00000002 */
+#define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
+#define PWR_SCR_CWUF1_Pos            (0U)
+#define PWR_SCR_CWUF1_Msk            (0x1UL << PWR_SCR_CWUF1_Pos)              /*!< 0x00000001 */
+#define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_PUCRA register  ********************/
+#define PWR_PUCRA_PA15_Pos           (15U)
+#define PWR_PUCRA_PA15_Msk           (0x1UL << PWR_PUCRA_PA15_Pos)             /*!< 0x00008000 */
+#define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
+#define PWR_PUCRA_PA13_Pos           (13U)
+#define PWR_PUCRA_PA13_Msk           (0x1UL << PWR_PUCRA_PA13_Pos)             /*!< 0x00002000 */
+#define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
+#define PWR_PUCRA_PA12_Pos           (12U)
+#define PWR_PUCRA_PA12_Msk           (0x1UL << PWR_PUCRA_PA12_Pos)             /*!< 0x00001000 */
+#define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
+#define PWR_PUCRA_PA11_Pos           (11U)
+#define PWR_PUCRA_PA11_Msk           (0x1UL << PWR_PUCRA_PA11_Pos)             /*!< 0x00000800 */
+#define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
+#define PWR_PUCRA_PA10_Pos           (10U)
+#define PWR_PUCRA_PA10_Msk           (0x1UL << PWR_PUCRA_PA10_Pos)             /*!< 0x00000400 */
+#define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
+#define PWR_PUCRA_PA9_Pos            (9U)
+#define PWR_PUCRA_PA9_Msk            (0x1UL << PWR_PUCRA_PA9_Pos)              /*!< 0x00000200 */
+#define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
+#define PWR_PUCRA_PA8_Pos            (8U)
+#define PWR_PUCRA_PA8_Msk            (0x1UL << PWR_PUCRA_PA8_Pos)              /*!< 0x00000100 */
+#define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
+#define PWR_PUCRA_PA7_Pos            (7U)
+#define PWR_PUCRA_PA7_Msk            (0x1UL << PWR_PUCRA_PA7_Pos)              /*!< 0x00000080 */
+#define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
+#define PWR_PUCRA_PA6_Pos            (6U)
+#define PWR_PUCRA_PA6_Msk            (0x1UL << PWR_PUCRA_PA6_Pos)              /*!< 0x00000040 */
+#define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
+#define PWR_PUCRA_PA5_Pos            (5U)
+#define PWR_PUCRA_PA5_Msk            (0x1UL << PWR_PUCRA_PA5_Pos)              /*!< 0x00000020 */
+#define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
+#define PWR_PUCRA_PA4_Pos            (4U)
+#define PWR_PUCRA_PA4_Msk            (0x1UL << PWR_PUCRA_PA4_Pos)              /*!< 0x00000010 */
+#define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
+#define PWR_PUCRA_PA3_Pos            (3U)
+#define PWR_PUCRA_PA3_Msk            (0x1UL << PWR_PUCRA_PA3_Pos)              /*!< 0x00000008 */
+#define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
+#define PWR_PUCRA_PA2_Pos            (2U)
+#define PWR_PUCRA_PA2_Msk            (0x1UL << PWR_PUCRA_PA2_Pos)              /*!< 0x00000004 */
+#define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
+#define PWR_PUCRA_PA1_Pos            (1U)
+#define PWR_PUCRA_PA1_Msk            (0x1UL << PWR_PUCRA_PA1_Pos)              /*!< 0x00000002 */
+#define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
+#define PWR_PUCRA_PA0_Pos            (0U)
+#define PWR_PUCRA_PA0_Msk            (0x1UL << PWR_PUCRA_PA0_Pos)              /*!< 0x00000001 */
+#define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRA register  ********************/
+#define PWR_PDCRA_PA14_Pos           (14U)
+#define PWR_PDCRA_PA14_Msk           (0x1UL << PWR_PDCRA_PA14_Pos)             /*!< 0x00004000 */
+#define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
+#define PWR_PDCRA_PA12_Pos           (12U)
+#define PWR_PDCRA_PA12_Msk           (0x1UL << PWR_PDCRA_PA12_Pos)             /*!< 0x00001000 */
+#define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
+#define PWR_PDCRA_PA11_Pos           (11U)
+#define PWR_PDCRA_PA11_Msk           (0x1UL << PWR_PDCRA_PA11_Pos)             /*!< 0x00000800 */
+#define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
+#define PWR_PDCRA_PA10_Pos           (10U)
+#define PWR_PDCRA_PA10_Msk           (0x1UL << PWR_PDCRA_PA10_Pos)             /*!< 0x00000400 */
+#define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
+#define PWR_PDCRA_PA9_Pos            (9U)
+#define PWR_PDCRA_PA9_Msk            (0x1UL << PWR_PDCRA_PA9_Pos)              /*!< 0x00000200 */
+#define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
+#define PWR_PDCRA_PA8_Pos            (8U)
+#define PWR_PDCRA_PA8_Msk            (0x1UL << PWR_PDCRA_PA8_Pos)              /*!< 0x00000100 */
+#define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
+#define PWR_PDCRA_PA7_Pos            (7U)
+#define PWR_PDCRA_PA7_Msk            (0x1UL << PWR_PDCRA_PA7_Pos)              /*!< 0x00000080 */
+#define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
+#define PWR_PDCRA_PA6_Pos            (6U)
+#define PWR_PDCRA_PA6_Msk            (0x1UL << PWR_PDCRA_PA6_Pos)              /*!< 0x00000040 */
+#define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
+#define PWR_PDCRA_PA5_Pos            (5U)
+#define PWR_PDCRA_PA5_Msk            (0x1UL << PWR_PDCRA_PA5_Pos)              /*!< 0x00000020 */
+#define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
+#define PWR_PDCRA_PA4_Pos            (4U)
+#define PWR_PDCRA_PA4_Msk            (0x1UL << PWR_PDCRA_PA4_Pos)              /*!< 0x00000010 */
+#define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
+#define PWR_PDCRA_PA3_Pos            (3U)
+#define PWR_PDCRA_PA3_Msk            (0x1UL << PWR_PDCRA_PA3_Pos)              /*!< 0x00000008 */
+#define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
+#define PWR_PDCRA_PA2_Pos            (2U)
+#define PWR_PDCRA_PA2_Msk            (0x1UL << PWR_PDCRA_PA2_Pos)              /*!< 0x00000004 */
+#define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
+#define PWR_PDCRA_PA1_Pos            (1U)
+#define PWR_PDCRA_PA1_Msk            (0x1UL << PWR_PDCRA_PA1_Pos)              /*!< 0x00000002 */
+#define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
+#define PWR_PDCRA_PA0_Pos            (0U)
+#define PWR_PDCRA_PA0_Msk            (0x1UL << PWR_PDCRA_PA0_Pos)              /*!< 0x00000001 */
+#define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRB register  ********************/
+
+#define PWR_PUCRB_PB15_Pos           (15U)
+#define PWR_PUCRB_PB15_Msk           (0x1UL << PWR_PUCRB_PB15_Pos)             /*!< 0x00008000 */
+#define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
+#define PWR_PUCRB_PB14_Pos           (14U)
+#define PWR_PUCRB_PB14_Msk           (0x1UL << PWR_PUCRB_PB14_Pos)             /*!< 0x00004000 */
+#define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
+#define PWR_PUCRB_PB13_Pos           (13U)
+#define PWR_PUCRB_PB13_Msk           (0x1UL << PWR_PUCRB_PB13_Pos)             /*!< 0x00002000 */
+#define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
+#define PWR_PUCRB_PB12_Pos           (12U)
+#define PWR_PUCRB_PB12_Msk           (0x1UL << PWR_PUCRB_PB12_Pos)             /*!< 0x00001000 */
+#define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
+#define PWR_PUCRB_PB11_Pos           (11U)
+#define PWR_PUCRB_PB11_Msk           (0x1UL << PWR_PUCRB_PB11_Pos)             /*!< 0x00000800 */
+#define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
+#define PWR_PUCRB_PB10_Pos           (10U)
+#define PWR_PUCRB_PB10_Msk           (0x1UL << PWR_PUCRB_PB10_Pos)             /*!< 0x00000400 */
+#define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
+#define PWR_PUCRB_PB9_Pos            (9U)
+#define PWR_PUCRB_PB9_Msk            (0x1UL << PWR_PUCRB_PB9_Pos)              /*!< 0x00000200 */
+#define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
+#define PWR_PUCRB_PB8_Pos            (8U)
+#define PWR_PUCRB_PB8_Msk            (0x1UL << PWR_PUCRB_PB8_Pos)              /*!< 0x00000100 */
+#define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
+#define PWR_PUCRB_PB7_Pos            (7U)
+#define PWR_PUCRB_PB7_Msk            (0x1UL << PWR_PUCRB_PB7_Pos)              /*!< 0x00000080 */
+#define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
+#define PWR_PUCRB_PB6_Pos            (6U)
+#define PWR_PUCRB_PB6_Msk            (0x1UL << PWR_PUCRB_PB6_Pos)              /*!< 0x00000040 */
+#define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
+#define PWR_PUCRB_PB5_Pos            (5U)
+#define PWR_PUCRB_PB5_Msk            (0x1UL << PWR_PUCRB_PB5_Pos)              /*!< 0x00000020 */
+#define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
+#define PWR_PUCRB_PB4_Pos            (4U)
+#define PWR_PUCRB_PB4_Msk            (0x1UL << PWR_PUCRB_PB4_Pos)              /*!< 0x00000010 */
+#define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
+#define PWR_PUCRB_PB3_Pos            (3U)
+#define PWR_PUCRB_PB3_Msk            (0x1UL << PWR_PUCRB_PB3_Pos)              /*!< 0x00000008 */
+#define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
+#define PWR_PUCRB_PB2_Pos            (2U)
+#define PWR_PUCRB_PB2_Msk            (0x1UL << PWR_PUCRB_PB2_Pos)              /*!< 0x00000004 */
+#define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
+#define PWR_PUCRB_PB1_Pos            (1U)
+#define PWR_PUCRB_PB1_Msk            (0x1UL << PWR_PUCRB_PB1_Pos)              /*!< 0x00000002 */
+#define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
+#define PWR_PUCRB_PB0_Pos            (0U)
+#define PWR_PUCRB_PB0_Msk            (0x1UL << PWR_PUCRB_PB0_Pos)              /*!< 0x00000001 */
+#define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRB register  ********************/
+#define PWR_PDCRB_PB15_Pos           (15U)
+#define PWR_PDCRB_PB15_Msk           (0x1UL << PWR_PDCRB_PB15_Pos)             /*!< 0x00008000 */
+#define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
+#define PWR_PDCRB_PB14_Pos           (14U)
+#define PWR_PDCRB_PB14_Msk           (0x1UL << PWR_PDCRB_PB14_Pos)             /*!< 0x00004000 */
+#define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
+#define PWR_PDCRB_PB13_Pos           (13U)
+#define PWR_PDCRB_PB13_Msk           (0x1UL << PWR_PDCRB_PB13_Pos)             /*!< 0x00002000 */
+#define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
+#define PWR_PDCRB_PB12_Pos           (12U)
+#define PWR_PDCRB_PB12_Msk           (0x1UL << PWR_PDCRB_PB12_Pos)             /*!< 0x00001000 */
+#define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
+#define PWR_PDCRB_PB11_Pos           (11U)
+#define PWR_PDCRB_PB11_Msk           (0x1UL << PWR_PDCRB_PB11_Pos)             /*!< 0x00000800 */
+#define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
+#define PWR_PDCRB_PB10_Pos           (10U)
+#define PWR_PDCRB_PB10_Msk           (0x1UL << PWR_PDCRB_PB10_Pos)             /*!< 0x00000400 */
+#define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
+#define PWR_PDCRB_PB9_Pos            (9U)
+#define PWR_PDCRB_PB9_Msk            (0x1UL << PWR_PDCRB_PB9_Pos)              /*!< 0x00000200 */
+#define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
+#define PWR_PDCRB_PB8_Pos            (8U)
+#define PWR_PDCRB_PB8_Msk            (0x1UL << PWR_PDCRB_PB8_Pos)              /*!< 0x00000100 */
+#define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
+#define PWR_PDCRB_PB7_Pos            (7U)
+#define PWR_PDCRB_PB7_Msk            (0x1UL << PWR_PDCRB_PB7_Pos)              /*!< 0x00000080 */
+#define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
+#define PWR_PDCRB_PB6_Pos            (6U)
+#define PWR_PDCRB_PB6_Msk            (0x1UL << PWR_PDCRB_PB6_Pos)              /*!< 0x00000040 */
+#define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
+#define PWR_PDCRB_PB5_Pos            (5U)
+#define PWR_PDCRB_PB5_Msk            (0x1UL << PWR_PDCRB_PB5_Pos)              /*!< 0x00000020 */
+#define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
+#define PWR_PDCRB_PB3_Pos            (3U)
+#define PWR_PDCRB_PB3_Msk            (0x1UL << PWR_PDCRB_PB3_Pos)              /*!< 0x00000008 */
+#define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
+#define PWR_PDCRB_PB2_Pos            (2U)
+#define PWR_PDCRB_PB2_Msk            (0x1UL << PWR_PDCRB_PB2_Pos)              /*!< 0x00000004 */
+#define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
+#define PWR_PDCRB_PB1_Pos            (1U)
+#define PWR_PDCRB_PB1_Msk            (0x1UL << PWR_PDCRB_PB1_Pos)              /*!< 0x00000002 */
+#define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
+#define PWR_PDCRB_PB0_Pos            (0U)
+#define PWR_PDCRB_PB0_Msk            (0x1UL << PWR_PDCRB_PB0_Pos)              /*!< 0x00000001 */
+#define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRC register  ********************/
+#define PWR_PUCRC_PC15_Pos           (15U)
+#define PWR_PUCRC_PC15_Msk           (0x1UL << PWR_PUCRC_PC15_Pos)             /*!< 0x00008000 */
+#define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
+#define PWR_PUCRC_PC14_Pos           (14U)
+#define PWR_PUCRC_PC14_Msk           (0x1UL << PWR_PUCRC_PC14_Pos)             /*!< 0x00004000 */
+#define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
+#define PWR_PUCRC_PC13_Pos           (13U)
+#define PWR_PUCRC_PC13_Msk           (0x1UL << PWR_PUCRC_PC13_Pos)             /*!< 0x00002000 */
+#define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
+#define PWR_PUCRC_PC12_Pos           (12U)
+#define PWR_PUCRC_PC12_Msk           (0x1UL << PWR_PUCRC_PC12_Pos)             /*!< 0x00001000 */
+#define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
+#define PWR_PUCRC_PC11_Pos           (11U)
+#define PWR_PUCRC_PC11_Msk           (0x1UL << PWR_PUCRC_PC11_Pos)             /*!< 0x00000800 */
+#define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
+#define PWR_PUCRC_PC10_Pos           (10U)
+#define PWR_PUCRC_PC10_Msk           (0x1UL << PWR_PUCRC_PC10_Pos)             /*!< 0x00000400 */
+#define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
+#define PWR_PUCRC_PC9_Pos            (9U)
+#define PWR_PUCRC_PC9_Msk            (0x1UL << PWR_PUCRC_PC9_Pos)              /*!< 0x00000200 */
+#define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
+#define PWR_PUCRC_PC8_Pos            (8U)
+#define PWR_PUCRC_PC8_Msk            (0x1UL << PWR_PUCRC_PC8_Pos)              /*!< 0x00000100 */
+#define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
+#define PWR_PUCRC_PC7_Pos            (7U)
+#define PWR_PUCRC_PC7_Msk            (0x1UL << PWR_PUCRC_PC7_Pos)              /*!< 0x00000080 */
+#define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
+#define PWR_PUCRC_PC6_Pos            (6U)
+#define PWR_PUCRC_PC6_Msk            (0x1UL << PWR_PUCRC_PC6_Pos)              /*!< 0x00000040 */
+#define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
+#define PWR_PUCRC_PC5_Pos            (5U)
+#define PWR_PUCRC_PC5_Msk            (0x1UL << PWR_PUCRC_PC5_Pos)              /*!< 0x00000020 */
+#define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
+#define PWR_PUCRC_PC4_Pos            (4U)
+#define PWR_PUCRC_PC4_Msk            (0x1UL << PWR_PUCRC_PC4_Pos)              /*!< 0x00000010 */
+#define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
+#define PWR_PUCRC_PC3_Pos            (3U)
+#define PWR_PUCRC_PC3_Msk            (0x1UL << PWR_PUCRC_PC3_Pos)              /*!< 0x00000008 */
+#define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
+#define PWR_PUCRC_PC2_Pos            (2U)
+#define PWR_PUCRC_PC2_Msk            (0x1UL << PWR_PUCRC_PC2_Pos)              /*!< 0x00000004 */
+#define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
+#define PWR_PUCRC_PC1_Pos            (1U)
+#define PWR_PUCRC_PC1_Msk            (0x1UL << PWR_PUCRC_PC1_Pos)              /*!< 0x00000002 */
+#define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
+#define PWR_PUCRC_PC0_Pos            (0U)
+#define PWR_PUCRC_PC0_Msk            (0x1UL << PWR_PUCRC_PC0_Pos)              /*!< 0x00000001 */
+#define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRC register  ********************/
+#define PWR_PDCRC_PC15_Pos           (15U)
+#define PWR_PDCRC_PC15_Msk           (0x1UL << PWR_PDCRC_PC15_Pos)             /*!< 0x00008000 */
+#define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
+#define PWR_PDCRC_PC14_Pos           (14U)
+#define PWR_PDCRC_PC14_Msk           (0x1UL << PWR_PDCRC_PC14_Pos)             /*!< 0x00004000 */
+#define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
+#define PWR_PDCRC_PC13_Pos           (13U)
+#define PWR_PDCRC_PC13_Msk           (0x1UL << PWR_PDCRC_PC13_Pos)             /*!< 0x00002000 */
+#define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
+#define PWR_PDCRC_PC12_Pos           (12U)
+#define PWR_PDCRC_PC12_Msk           (0x1UL << PWR_PDCRC_PC12_Pos)             /*!< 0x00001000 */
+#define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
+#define PWR_PDCRC_PC11_Pos           (11U)
+#define PWR_PDCRC_PC11_Msk           (0x1UL << PWR_PDCRC_PC11_Pos)             /*!< 0x00000800 */
+#define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
+#define PWR_PDCRC_PC10_Pos           (10U)
+#define PWR_PDCRC_PC10_Msk           (0x1UL << PWR_PDCRC_PC10_Pos)             /*!< 0x00000400 */
+#define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
+#define PWR_PDCRC_PC9_Pos            (9U)
+#define PWR_PDCRC_PC9_Msk            (0x1UL << PWR_PDCRC_PC9_Pos)              /*!< 0x00000200 */
+#define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
+#define PWR_PDCRC_PC8_Pos            (8U)
+#define PWR_PDCRC_PC8_Msk            (0x1UL << PWR_PDCRC_PC8_Pos)              /*!< 0x00000100 */
+#define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
+#define PWR_PDCRC_PC7_Pos            (7U)
+#define PWR_PDCRC_PC7_Msk            (0x1UL << PWR_PDCRC_PC7_Pos)              /*!< 0x00000080 */
+#define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
+#define PWR_PDCRC_PC6_Pos            (6U)
+#define PWR_PDCRC_PC6_Msk            (0x1UL << PWR_PDCRC_PC6_Pos)              /*!< 0x00000040 */
+#define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
+#define PWR_PDCRC_PC5_Pos            (5U)
+#define PWR_PDCRC_PC5_Msk            (0x1UL << PWR_PDCRC_PC5_Pos)              /*!< 0x00000020 */
+#define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
+#define PWR_PDCRC_PC4_Pos            (4U)
+#define PWR_PDCRC_PC4_Msk            (0x1UL << PWR_PDCRC_PC4_Pos)              /*!< 0x00000010 */
+#define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
+#define PWR_PDCRC_PC3_Pos            (3U)
+#define PWR_PDCRC_PC3_Msk            (0x1UL << PWR_PDCRC_PC3_Pos)              /*!< 0x00000008 */
+#define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
+#define PWR_PDCRC_PC2_Pos            (2U)
+#define PWR_PDCRC_PC2_Msk            (0x1UL << PWR_PDCRC_PC2_Pos)              /*!< 0x00000004 */
+#define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
+#define PWR_PDCRC_PC1_Pos            (1U)
+#define PWR_PDCRC_PC1_Msk            (0x1UL << PWR_PDCRC_PC1_Pos)              /*!< 0x00000002 */
+#define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
+#define PWR_PDCRC_PC0_Pos            (0U)
+#define PWR_PDCRC_PC0_Msk            (0x1UL << PWR_PDCRC_PC0_Pos)              /*!< 0x00000001 */
+#define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRD register  ********************/
+#define PWR_PUCRD_PD15_Pos           (15U)
+#define PWR_PUCRD_PD15_Msk           (0x1UL << PWR_PUCRD_PD15_Pos)             /*!< 0x00008000 */
+#define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
+#define PWR_PUCRD_PD14_Pos           (14U)
+#define PWR_PUCRD_PD14_Msk           (0x1UL << PWR_PUCRD_PD14_Pos)             /*!< 0x00004000 */
+#define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
+#define PWR_PUCRD_PD13_Pos           (13U)
+#define PWR_PUCRD_PD13_Msk           (0x1UL << PWR_PUCRD_PD13_Pos)             /*!< 0x00002000 */
+#define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
+#define PWR_PUCRD_PD12_Pos           (12U)
+#define PWR_PUCRD_PD12_Msk           (0x1UL << PWR_PUCRD_PD12_Pos)             /*!< 0x00001000 */
+#define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
+#define PWR_PUCRD_PD11_Pos           (11U)
+#define PWR_PUCRD_PD11_Msk           (0x1UL << PWR_PUCRD_PD11_Pos)             /*!< 0x00000800 */
+#define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
+#define PWR_PUCRD_PD10_Pos           (10U)
+#define PWR_PUCRD_PD10_Msk           (0x1UL << PWR_PUCRD_PD10_Pos)             /*!< 0x00000400 */
+#define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
+#define PWR_PUCRD_PD9_Pos            (9U)
+#define PWR_PUCRD_PD9_Msk            (0x1UL << PWR_PUCRD_PD9_Pos)              /*!< 0x00000200 */
+#define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
+#define PWR_PUCRD_PD8_Pos            (8U)
+#define PWR_PUCRD_PD8_Msk            (0x1UL << PWR_PUCRD_PD8_Pos)              /*!< 0x00000100 */
+#define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
+#define PWR_PUCRD_PD7_Pos            (7U)
+#define PWR_PUCRD_PD7_Msk            (0x1UL << PWR_PUCRD_PD7_Pos)              /*!< 0x00000080 */
+#define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
+#define PWR_PUCRD_PD6_Pos            (6U)
+#define PWR_PUCRD_PD6_Msk            (0x1UL << PWR_PUCRD_PD6_Pos)              /*!< 0x00000040 */
+#define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
+#define PWR_PUCRD_PD5_Pos            (5U)
+#define PWR_PUCRD_PD5_Msk            (0x1UL << PWR_PUCRD_PD5_Pos)              /*!< 0x00000020 */
+#define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
+#define PWR_PUCRD_PD4_Pos            (4U)
+#define PWR_PUCRD_PD4_Msk            (0x1UL << PWR_PUCRD_PD4_Pos)              /*!< 0x00000010 */
+#define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
+#define PWR_PUCRD_PD3_Pos            (3U)
+#define PWR_PUCRD_PD3_Msk            (0x1UL << PWR_PUCRD_PD3_Pos)              /*!< 0x00000008 */
+#define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
+#define PWR_PUCRD_PD2_Pos            (2U)
+#define PWR_PUCRD_PD2_Msk            (0x1UL << PWR_PUCRD_PD2_Pos)              /*!< 0x00000004 */
+#define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
+#define PWR_PUCRD_PD1_Pos            (1U)
+#define PWR_PUCRD_PD1_Msk            (0x1UL << PWR_PUCRD_PD1_Pos)              /*!< 0x00000002 */
+#define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
+#define PWR_PUCRD_PD0_Pos            (0U)
+#define PWR_PUCRD_PD0_Msk            (0x1UL << PWR_PUCRD_PD0_Pos)              /*!< 0x00000001 */
+#define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRD register  ********************/
+#define PWR_PDCRD_PD15_Pos           (15U)
+#define PWR_PDCRD_PD15_Msk           (0x1UL << PWR_PDCRD_PD15_Pos)             /*!< 0x00008000 */
+#define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
+#define PWR_PDCRD_PD14_Pos           (14U)
+#define PWR_PDCRD_PD14_Msk           (0x1UL << PWR_PDCRD_PD14_Pos)             /*!< 0x00004000 */
+#define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
+#define PWR_PDCRD_PD13_Pos           (13U)
+#define PWR_PDCRD_PD13_Msk           (0x1UL << PWR_PDCRD_PD13_Pos)             /*!< 0x00002000 */
+#define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
+#define PWR_PDCRD_PD12_Pos           (12U)
+#define PWR_PDCRD_PD12_Msk           (0x1UL << PWR_PDCRD_PD12_Pos)             /*!< 0x00001000 */
+#define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
+#define PWR_PDCRD_PD11_Pos           (11U)
+#define PWR_PDCRD_PD11_Msk           (0x1UL << PWR_PDCRD_PD11_Pos)             /*!< 0x00000800 */
+#define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
+#define PWR_PDCRD_PD10_Pos           (10U)
+#define PWR_PDCRD_PD10_Msk           (0x1UL << PWR_PDCRD_PD10_Pos)             /*!< 0x00000400 */
+#define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
+#define PWR_PDCRD_PD9_Pos            (9U)
+#define PWR_PDCRD_PD9_Msk            (0x1UL << PWR_PDCRD_PD9_Pos)              /*!< 0x00000200 */
+#define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
+#define PWR_PDCRD_PD8_Pos            (8U)
+#define PWR_PDCRD_PD8_Msk            (0x1UL << PWR_PDCRD_PD8_Pos)              /*!< 0x00000100 */
+#define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
+#define PWR_PDCRD_PD7_Pos            (7U)
+#define PWR_PDCRD_PD7_Msk            (0x1UL << PWR_PDCRD_PD7_Pos)              /*!< 0x00000080 */
+#define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
+#define PWR_PDCRD_PD6_Pos            (6U)
+#define PWR_PDCRD_PD6_Msk            (0x1UL << PWR_PDCRD_PD6_Pos)              /*!< 0x00000040 */
+#define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
+#define PWR_PDCRD_PD5_Pos            (5U)
+#define PWR_PDCRD_PD5_Msk            (0x1UL << PWR_PDCRD_PD5_Pos)              /*!< 0x00000020 */
+#define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
+#define PWR_PDCRD_PD4_Pos            (4U)
+#define PWR_PDCRD_PD4_Msk            (0x1UL << PWR_PDCRD_PD4_Pos)              /*!< 0x00000010 */
+#define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
+#define PWR_PDCRD_PD3_Pos            (3U)
+#define PWR_PDCRD_PD3_Msk            (0x1UL << PWR_PDCRD_PD3_Pos)              /*!< 0x00000008 */
+#define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
+#define PWR_PDCRD_PD2_Pos            (2U)
+#define PWR_PDCRD_PD2_Msk            (0x1UL << PWR_PDCRD_PD2_Pos)              /*!< 0x00000004 */
+#define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
+#define PWR_PDCRD_PD1_Pos            (1U)
+#define PWR_PDCRD_PD1_Msk            (0x1UL << PWR_PDCRD_PD1_Pos)              /*!< 0x00000002 */
+#define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
+#define PWR_PDCRD_PD0_Pos            (0U)
+#define PWR_PDCRD_PD0_Msk            (0x1UL << PWR_PDCRD_PD0_Pos)              /*!< 0x00000001 */
+#define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRE register  ********************/
+#define PWR_PUCRE_PE15_Pos           (15U)
+#define PWR_PUCRE_PE15_Msk           (0x1UL << PWR_PUCRE_PE15_Pos)             /*!< 0x00008000 */
+#define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
+#define PWR_PUCRE_PE14_Pos           (14U)
+#define PWR_PUCRE_PE14_Msk           (0x1UL << PWR_PUCRE_PE14_Pos)             /*!< 0x00004000 */
+#define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
+#define PWR_PUCRE_PE13_Pos           (13U)
+#define PWR_PUCRE_PE13_Msk           (0x1UL << PWR_PUCRE_PE13_Pos)             /*!< 0x00002000 */
+#define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
+#define PWR_PUCRE_PE12_Pos           (12U)
+#define PWR_PUCRE_PE12_Msk           (0x1UL << PWR_PUCRE_PE12_Pos)             /*!< 0x00001000 */
+#define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
+#define PWR_PUCRE_PE11_Pos           (11U)
+#define PWR_PUCRE_PE11_Msk           (0x1UL << PWR_PUCRE_PE11_Pos)             /*!< 0x00000800 */
+#define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
+#define PWR_PUCRE_PE10_Pos           (10U)
+#define PWR_PUCRE_PE10_Msk           (0x1UL << PWR_PUCRE_PE10_Pos)             /*!< 0x00000400 */
+#define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
+#define PWR_PUCRE_PE9_Pos            (9U)
+#define PWR_PUCRE_PE9_Msk            (0x1UL << PWR_PUCRE_PE9_Pos)              /*!< 0x00000200 */
+#define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
+#define PWR_PUCRE_PE8_Pos            (8U)
+#define PWR_PUCRE_PE8_Msk            (0x1UL << PWR_PUCRE_PE8_Pos)              /*!< 0x00000100 */
+#define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
+#define PWR_PUCRE_PE7_Pos            (7U)
+#define PWR_PUCRE_PE7_Msk            (0x1UL << PWR_PUCRE_PE7_Pos)              /*!< 0x00000080 */
+#define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
+#define PWR_PUCRE_PE6_Pos            (6U)
+#define PWR_PUCRE_PE6_Msk            (0x1UL << PWR_PUCRE_PE6_Pos)              /*!< 0x00000040 */
+#define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
+#define PWR_PUCRE_PE5_Pos            (5U)
+#define PWR_PUCRE_PE5_Msk            (0x1UL << PWR_PUCRE_PE5_Pos)              /*!< 0x00000020 */
+#define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
+#define PWR_PUCRE_PE4_Pos            (4U)
+#define PWR_PUCRE_PE4_Msk            (0x1UL << PWR_PUCRE_PE4_Pos)              /*!< 0x00000010 */
+#define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
+#define PWR_PUCRE_PE3_Pos            (3U)
+#define PWR_PUCRE_PE3_Msk            (0x1UL << PWR_PUCRE_PE3_Pos)              /*!< 0x00000008 */
+#define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
+#define PWR_PUCRE_PE2_Pos            (2U)
+#define PWR_PUCRE_PE2_Msk            (0x1UL << PWR_PUCRE_PE2_Pos)              /*!< 0x00000004 */
+#define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
+#define PWR_PUCRE_PE1_Pos            (1U)
+#define PWR_PUCRE_PE1_Msk            (0x1UL << PWR_PUCRE_PE1_Pos)              /*!< 0x00000002 */
+#define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
+#define PWR_PUCRE_PE0_Pos            (0U)
+#define PWR_PUCRE_PE0_Msk            (0x1UL << PWR_PUCRE_PE0_Pos)              /*!< 0x00000001 */
+#define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRE register  ********************/
+#define PWR_PDCRE_PE15_Pos           (15U)
+#define PWR_PDCRE_PE15_Msk           (0x1UL << PWR_PDCRE_PE15_Pos)             /*!< 0x00008000 */
+#define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
+#define PWR_PDCRE_PE14_Pos           (14U)
+#define PWR_PDCRE_PE14_Msk           (0x1UL << PWR_PDCRE_PE14_Pos)             /*!< 0x00004000 */
+#define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
+#define PWR_PDCRE_PE13_Pos           (13U)
+#define PWR_PDCRE_PE13_Msk           (0x1UL << PWR_PDCRE_PE13_Pos)             /*!< 0x00002000 */
+#define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
+#define PWR_PDCRE_PE12_Pos           (12U)
+#define PWR_PDCRE_PE12_Msk           (0x1UL << PWR_PDCRE_PE12_Pos)             /*!< 0x00001000 */
+#define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
+#define PWR_PDCRE_PE11_Pos           (11U)
+#define PWR_PDCRE_PE11_Msk           (0x1UL << PWR_PDCRE_PE11_Pos)             /*!< 0x00000800 */
+#define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
+#define PWR_PDCRE_PE10_Pos           (10U)
+#define PWR_PDCRE_PE10_Msk           (0x1UL << PWR_PDCRE_PE10_Pos)             /*!< 0x00000400 */
+#define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
+#define PWR_PDCRE_PE9_Pos            (9U)
+#define PWR_PDCRE_PE9_Msk            (0x1UL << PWR_PDCRE_PE9_Pos)              /*!< 0x00000200 */
+#define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
+#define PWR_PDCRE_PE8_Pos            (8U)
+#define PWR_PDCRE_PE8_Msk            (0x1UL << PWR_PDCRE_PE8_Pos)              /*!< 0x00000100 */
+#define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
+#define PWR_PDCRE_PE7_Pos            (7U)
+#define PWR_PDCRE_PE7_Msk            (0x1UL << PWR_PDCRE_PE7_Pos)              /*!< 0x00000080 */
+#define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
+#define PWR_PDCRE_PE6_Pos            (6U)
+#define PWR_PDCRE_PE6_Msk            (0x1UL << PWR_PDCRE_PE6_Pos)              /*!< 0x00000040 */
+#define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
+#define PWR_PDCRE_PE5_Pos            (5U)
+#define PWR_PDCRE_PE5_Msk            (0x1UL << PWR_PDCRE_PE5_Pos)              /*!< 0x00000020 */
+#define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
+#define PWR_PDCRE_PE4_Pos            (4U)
+#define PWR_PDCRE_PE4_Msk            (0x1UL << PWR_PDCRE_PE4_Pos)              /*!< 0x00000010 */
+#define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
+#define PWR_PDCRE_PE3_Pos            (3U)
+#define PWR_PDCRE_PE3_Msk            (0x1UL << PWR_PDCRE_PE3_Pos)              /*!< 0x00000008 */
+#define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
+#define PWR_PDCRE_PE2_Pos            (2U)
+#define PWR_PDCRE_PE2_Msk            (0x1UL << PWR_PDCRE_PE2_Pos)              /*!< 0x00000004 */
+#define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
+#define PWR_PDCRE_PE1_Pos            (1U)
+#define PWR_PDCRE_PE1_Msk            (0x1UL << PWR_PDCRE_PE1_Pos)              /*!< 0x00000002 */
+#define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
+#define PWR_PDCRE_PE0_Pos            (0U)
+#define PWR_PDCRE_PE0_Msk            (0x1UL << PWR_PDCRE_PE0_Pos)              /*!< 0x00000001 */
+#define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRF register  ********************/
+#define PWR_PUCRF_PF15_Pos           (15U)
+#define PWR_PUCRF_PF15_Msk           (0x1UL << PWR_PUCRF_PF15_Pos)             /*!< 0x00008000 */
+#define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */
+#define PWR_PUCRF_PF14_Pos           (14U)
+#define PWR_PUCRF_PF14_Msk           (0x1UL << PWR_PUCRF_PF14_Pos)             /*!< 0x00004000 */
+#define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */
+#define PWR_PUCRF_PF13_Pos           (13U)
+#define PWR_PUCRF_PF13_Msk           (0x1UL << PWR_PUCRF_PF13_Pos)             /*!< 0x00002000 */
+#define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */
+#define PWR_PUCRF_PF12_Pos           (12U)
+#define PWR_PUCRF_PF12_Msk           (0x1UL << PWR_PUCRF_PF12_Pos)             /*!< 0x00001000 */
+#define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */
+#define PWR_PUCRF_PF11_Pos           (11U)
+#define PWR_PUCRF_PF11_Msk           (0x1UL << PWR_PUCRF_PF11_Pos)             /*!< 0x00000800 */
+#define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */
+#define PWR_PUCRF_PF10_Pos           (10U)
+#define PWR_PUCRF_PF10_Msk           (0x1UL << PWR_PUCRF_PF10_Pos)             /*!< 0x00000400 */
+#define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */
+#define PWR_PUCRF_PF9_Pos            (9U)
+#define PWR_PUCRF_PF9_Msk            (0x1UL << PWR_PUCRF_PF9_Pos)              /*!< 0x00000200 */
+#define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */
+#define PWR_PUCRF_PF8_Pos            (8U)
+#define PWR_PUCRF_PF8_Msk            (0x1UL << PWR_PUCRF_PF8_Pos)              /*!< 0x00000100 */
+#define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */
+#define PWR_PUCRF_PF7_Pos            (7U)
+#define PWR_PUCRF_PF7_Msk            (0x1UL << PWR_PUCRF_PF7_Pos)              /*!< 0x00000080 */
+#define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */
+#define PWR_PUCRF_PF6_Pos            (6U)
+#define PWR_PUCRF_PF6_Msk            (0x1UL << PWR_PUCRF_PF6_Pos)              /*!< 0x00000040 */
+#define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */
+#define PWR_PUCRF_PF5_Pos            (5U)
+#define PWR_PUCRF_PF5_Msk            (0x1UL << PWR_PUCRF_PF5_Pos)              /*!< 0x00000020 */
+#define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */
+#define PWR_PUCRF_PF4_Pos            (4U)
+#define PWR_PUCRF_PF4_Msk            (0x1UL << PWR_PUCRF_PF4_Pos)              /*!< 0x00000010 */
+#define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */
+#define PWR_PUCRF_PF3_Pos            (3U)
+#define PWR_PUCRF_PF3_Msk            (0x1UL << PWR_PUCRF_PF3_Pos)              /*!< 0x00000008 */
+#define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */
+#define PWR_PUCRF_PF2_Pos            (2U)
+#define PWR_PUCRF_PF2_Msk            (0x1UL << PWR_PUCRF_PF2_Pos)              /*!< 0x00000004 */
+#define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */
+#define PWR_PUCRF_PF1_Pos            (1U)
+#define PWR_PUCRF_PF1_Msk            (0x1UL << PWR_PUCRF_PF1_Pos)              /*!< 0x00000002 */
+#define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */
+#define PWR_PUCRF_PF0_Pos            (0U)
+#define PWR_PUCRF_PF0_Msk            (0x1UL << PWR_PUCRF_PF0_Pos)              /*!< 0x00000001 */
+#define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRF register  ********************/
+#define PWR_PDCRF_PF10_Pos           (10U)
+#define PWR_PDCRF_PF10_Msk           (0x1UL << PWR_PDCRF_PF10_Pos)             /*!< 0x00000400 */
+#define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */
+#define PWR_PDCRF_PF9_Pos            (9U)
+#define PWR_PDCRF_PF9_Msk            (0x1UL << PWR_PDCRF_PF9_Pos)              /*!< 0x00000200 */
+#define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */
+#define PWR_PDCRF_PF2_Pos            (2U)
+#define PWR_PDCRF_PF2_Msk            (0x1UL << PWR_PDCRF_PF2_Pos)              /*!< 0x00000004 */
+#define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */
+#define PWR_PDCRF_PF1_Pos            (1U)
+#define PWR_PDCRF_PF1_Msk            (0x1UL << PWR_PDCRF_PF1_Pos)              /*!< 0x00000002 */
+#define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */
+#define PWR_PDCRF_PF0_Pos            (0U)
+#define PWR_PDCRF_PF0_Msk            (0x1UL << PWR_PDCRF_PF0_Pos)              /*!< 0x00000001 */
+#define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRG register  ********************/
+#define PWR_PUCRG_PG10_Pos           (10U)
+#define PWR_PUCRG_PG10_Msk           (0x1UL << PWR_PUCRG_PG10_Pos)             /*!< 0x00000400 */
+#define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */
+
+/********************  Bit definition for PWR_PDCRG register  ********************/
+#define PWR_PDCRG_PG10_Pos           (10U)
+#define PWR_PDCRG_PG10_Msk           (0x1UL << PWR_PDCRG_PG10_Pos)             /*!< 0x00000400 */
+#define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */
+#define PWR_PDCRG_PG9_Pos            (9U)
+#define PWR_PDCRG_PG9_Msk            (0x1UL << PWR_PDCRG_PG9_Pos)              /*!< 0x00000200 */
+#define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */
+#define PWR_PDCRG_PG8_Pos            (8U)
+#define PWR_PDCRG_PG8_Msk            (0x1UL << PWR_PDCRG_PG8_Pos)              /*!< 0x00000100 */
+#define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */
+#define PWR_PDCRG_PG7_Pos            (7U)
+#define PWR_PDCRG_PG7_Msk            (0x1UL << PWR_PDCRG_PG7_Pos)              /*!< 0x00000080 */
+#define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */
+#define PWR_PDCRG_PG6_Pos            (6U)
+#define PWR_PDCRG_PG6_Msk            (0x1UL << PWR_PDCRG_PG6_Pos)              /*!< 0x00000040 */
+#define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */
+#define PWR_PDCRG_PG5_Pos            (5U)
+#define PWR_PDCRG_PG5_Msk            (0x1UL << PWR_PDCRG_PG5_Pos)              /*!< 0x00000020 */
+#define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */
+#define PWR_PDCRG_PG4_Pos            (4U)
+#define PWR_PDCRG_PG4_Msk            (0x1UL << PWR_PDCRG_PG4_Pos)              /*!< 0x00000010 */
+#define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */
+#define PWR_PDCRG_PG3_Pos            (3U)
+#define PWR_PDCRG_PG3_Msk            (0x1UL << PWR_PDCRG_PG3_Pos)              /*!< 0x00000008 */
+#define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */
+#define PWR_PDCRG_PG2_Pos            (2U)
+#define PWR_PDCRG_PG2_Msk            (0x1UL << PWR_PDCRG_PG2_Pos)              /*!< 0x00000004 */
+#define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */
+#define PWR_PDCRG_PG1_Pos            (1U)
+#define PWR_PDCRG_PG1_Msk            (0x1UL << PWR_PDCRG_PG1_Pos)              /*!< 0x00000002 */
+#define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */
+#define PWR_PDCRG_PG0_Pos            (0U)
+#define PWR_PDCRG_PG0_Msk            (0x1UL << PWR_PDCRG_PG0_Pos)              /*!< 0x00000001 */
+#define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */
+
+/********************  Bit definition for PWR_CR5 register  ********************/
+#define PWR_CR5_R1MODE_Pos           (8U)
+#define PWR_CR5_R1MODE_Msk           (0x1U << PWR_CR5_R1MODE_Pos)              /*!< 0x00000100 */
+#define PWR_CR5_R1MODE               PWR_CR5_R1MODE_Msk                        /*!< selection for Main Regulator in Range1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions  (not present on all devices in the STM32G4 serie)
+*/
+
+#define RCC_HSI48_SUPPORT
+#define RCC_PLLP_DIV_2_31_SUPPORT
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                     (8U)
+#define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
+#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
+#define RCC_CR_HSIKERON_Pos                  (9U)
+#define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
+#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                    (10U)
+#define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
+#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
+
+#define RCC_CR_HSEON_Pos                     (16U)
+#define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
+#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
+#define RCC_CR_HSERDY_Pos                    (17U)
+#define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
+#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
+#define RCC_CR_HSEBYP_Pos                    (18U)
+#define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
+#define RCC_CR_CSSON_Pos                     (19U)
+#define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
+#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
+
+#define RCC_CR_PLLON_Pos                     (24U)
+#define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
+#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                    (25U)
+#define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
+
+/********************  Bit definition for RCC_ICSCR register  ***************/
+/*!< HSICAL configuration */
+#define RCC_ICSCR_HSICAL_Pos                 (16U)
+#define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
+#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
+#define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */
+#define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */
+#define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */
+#define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */
+#define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */
+#define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */
+#define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */
+#define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */
+
+/*!< HSITRIM configuration */
+#define RCC_ICSCR_HSITRIM_Pos                (24U)
+#define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
+#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
+#define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_ICSCR_HSITRIM_5                  (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
+#define RCC_ICSCR_HSITRIM_6                  (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                      (0U)
+#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
+#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
+#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
+#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                     (2U)
+#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
+#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                    (4U)
+#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                   (8U)
+#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                   (11U)
+#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
+
+/*!< MCOSEL configuration */
+#define RCC_CFGR_MCOSEL_Pos                  (24U)
+#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
+#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOPRE_Pos                  (28U)
+#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
+
+/* Legacy aliases */
+#define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
+#define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
+#define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
+#define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
+#define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
+#define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define RCC_PLLCFGR_PLLSRC_Pos               (0U)
+#define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_0                 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLSRC_1                 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
+
+#define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)
+#define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
+
+#define RCC_PLLCFGR_PLLM_Pos                 (4U)
+#define RCC_PLLCFGR_PLLM_Msk                 (0xFUL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x000000F0 */
+#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLM_3                   (0x8UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000080 */
+
+#define RCC_PLLCFGR_PLLN_Pos                 (8U)
+#define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00007F00 */
+#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLPEN_Pos               (16U)
+#define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
+#define RCC_PLLCFGR_PLLP_Pos                 (17U)
+#define RCC_PLLCFGR_PLLP_Msk                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)   /*!< 0x00020000 */
+#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLQEN_Pos               (20U)
+#define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
+
+#define RCC_PLLCFGR_PLLQ_Pos                 (21U)
+#define RCC_PLLCFGR_PLLQ_Msk                 (0x3UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00600000 */
+#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00200000 */
+#define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00400000 */
+
+#define RCC_PLLCFGR_PLLREN_Pos               (24U)
+#define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
+#define RCC_PLLCFGR_PLLR_Pos                 (25U)
+#define RCC_PLLCFGR_PLLR_Msk                 (0x3UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x06000000 */
+#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
+#define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x04000000 */
+
+#define RCC_PLLCFGR_PLLPDIV_Pos              (27U)
+#define RCC_PLLCFGR_PLLPDIV_Msk              (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
+#define RCC_PLLCFGR_PLLPDIV                  RCC_PLLCFGR_PLLPDIV_Msk
+#define RCC_PLLCFGR_PLLPDIV_0                (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
+#define RCC_PLLCFGR_PLLPDIV_1                (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
+#define RCC_PLLCFGR_PLLPDIV_2                (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
+#define RCC_PLLCFGR_PLLPDIV_3                (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
+#define RCC_PLLCFGR_PLLPDIV_4                (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
+
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                (0U)
+#define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
+#define RCC_CIER_LSERDYIE_Pos                (1U)
+#define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)  /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
+#define RCC_CIER_HSIRDYIE_Pos                (3U)
+#define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)  /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
+#define RCC_CIER_HSERDYIE_Pos                (4U)
+#define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)  /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
+#define RCC_CIER_PLLRDYIE_Pos                (5U)
+#define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)  /*!< 0x00000020 */
+#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
+#define RCC_CIER_LSECSSIE_Pos                (9U)
+#define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)  /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
+#define RCC_CIER_HSI48RDYIE_Pos              (10U)
+#define RCC_CIER_HSI48RDYIE_Msk              (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
+#define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                 (0U)
+#define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)   /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
+#define RCC_CIFR_LSERDYF_Pos                 (1U)
+#define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
+#define RCC_CIFR_HSIRDYF_Pos                 (3U)
+#define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
+#define RCC_CIFR_HSERDYF_Pos                 (4U)
+#define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
+#define RCC_CIFR_PLLRDYF_Pos                 (5U)
+#define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)   /*!< 0x00000020 */
+#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
+#define RCC_CIFR_CSSF_Pos                    (8U)
+#define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)      /*!< 0x00000100 */
+#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
+#define RCC_CIFR_LSECSSF_Pos                 (9U)
+#define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
+#define RCC_CIFR_HSI48RDYF_Pos               (10U)
+#define RCC_CIFR_HSI48RDYF_Msk               (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
+#define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                 (0U)
+#define RCC_CICR_LSIRDYC_Msk                 (0x1UL << RCC_CICR_LSIRDYC_Pos)   /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk
+#define RCC_CICR_LSERDYC_Pos                 (1U)
+#define RCC_CICR_LSERDYC_Msk                 (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk
+#define RCC_CICR_HSIRDYC_Pos                 (3U)
+#define RCC_CICR_HSIRDYC_Msk                 (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk
+#define RCC_CICR_HSERDYC_Pos                 (4U)
+#define RCC_CICR_HSERDYC_Msk                 (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk
+#define RCC_CICR_PLLRDYC_Pos                 (5U)
+#define RCC_CICR_PLLRDYC_Msk                 (0x1UL << RCC_CICR_PLLRDYC_Pos)   /*!< 0x00000020 */
+#define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk
+#define RCC_CICR_CSSC_Pos                    (8U)
+#define RCC_CICR_CSSC_Msk                    (0x1UL << RCC_CICR_CSSC_Pos)      /*!< 0x00000100 */
+#define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk
+#define RCC_CICR_LSECSSC_Pos                 (9U)
+#define RCC_CICR_LSECSSC_Msk                 (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk
+#define RCC_CICR_HSI48RDYC_Pos               (10U)
+#define RCC_CICR_HSI48RDYC_Msk               (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
+#define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
+#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
+#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_DMAMUX1RST_Pos          (2U)
+#define RCC_AHB1RSTR_DMAMUX1RST_Msk          (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
+#define RCC_AHB1RSTR_DMAMUX1RST              RCC_AHB1RSTR_DMAMUX1RST_Msk
+#define RCC_AHB1RSTR_CORDICRST_Pos           (3U)
+#define RCC_AHB1RSTR_CORDICRST_Msk           (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
+#define RCC_AHB1RSTR_CORDICRST               RCC_AHB1RSTR_CORDICRST_Msk
+#define RCC_AHB1RSTR_FMACRST_Pos             (4U)
+#define RCC_AHB1RSTR_FMACRST_Msk             (0x1UL << RCC_AHB1RSTR_FMACRST_Pos)  /*!< 0x00000010 */
+#define RCC_AHB1RSTR_FMACRST                 RCC_AHB1RSTR_FMACRST_Msk
+#define RCC_AHB1RSTR_FLASHRST_Pos            (8U)
+#define RCC_AHB1RSTR_FLASHRST_Msk            (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
+#define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos              (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define RCC_AHB2RSTR_GPIOARST_Pos            (0U)
+#define RCC_AHB2RSTR_GPIOARST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
+#define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk
+#define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)
+#define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
+#define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk
+#define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)
+#define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
+#define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk
+#define RCC_AHB2RSTR_GPIODRST_Pos            (3U)
+#define RCC_AHB2RSTR_GPIODRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
+#define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk
+#define RCC_AHB2RSTR_GPIOERST_Pos            (4U)
+#define RCC_AHB2RSTR_GPIOERST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
+#define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk
+#define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)
+#define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
+#define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk
+#define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)
+#define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
+#define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk
+#define RCC_AHB2RSTR_ADC12RST_Pos            (13U)
+#define RCC_AHB2RSTR_ADC12RST_Msk            (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
+#define RCC_AHB2RSTR_ADC12RST                RCC_AHB2RSTR_ADC12RST_Msk
+#define RCC_AHB2RSTR_DAC1RST_Pos             (16U)
+#define RCC_AHB2RSTR_DAC1RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
+#define RCC_AHB2RSTR_DAC1RST                 RCC_AHB2RSTR_DAC1RST_Msk
+#define RCC_AHB2RSTR_DAC3RST_Pos             (18U)
+#define RCC_AHB2RSTR_DAC3RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
+#define RCC_AHB2RSTR_DAC3RST                 RCC_AHB2RSTR_DAC3RST_Msk
+#define RCC_AHB2RSTR_RNGRST_Pos              (26U)
+#define RCC_AHB2RSTR_RNGRST_Msk              (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
+#define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+
+/********************  Bit definition for RCC_APB1RSTR1 register  **************/
+#define RCC_APB1RSTR1_TIM2RST_Pos            (0U)
+#define RCC_APB1RSTR1_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk
+#define RCC_APB1RSTR1_TIM3RST_Pos            (1U)
+#define RCC_APB1RSTR1_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
+#define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk
+#define RCC_APB1RSTR1_TIM4RST_Pos            (2U)
+#define RCC_APB1RSTR1_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
+#define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk
+#define RCC_APB1RSTR1_TIM6RST_Pos            (4U)
+#define RCC_APB1RSTR1_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk
+#define RCC_APB1RSTR1_TIM7RST_Pos            (5U)
+#define RCC_APB1RSTR1_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk
+#define RCC_APB1RSTR1_CRSRST_Pos             (8U)
+#define RCC_APB1RSTR1_CRSRST_Msk             (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
+#define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk
+#define RCC_APB1RSTR1_SPI2RST_Pos            (14U)
+#define RCC_APB1RSTR1_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk
+#define RCC_APB1RSTR1_SPI3RST_Pos            (15U)
+#define RCC_APB1RSTR1_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk
+#define RCC_APB1RSTR1_USART2RST_Pos          (17U)
+#define RCC_APB1RSTR1_USART2RST_Msk          (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk
+#define RCC_APB1RSTR1_USART3RST_Pos          (18U)
+#define RCC_APB1RSTR1_USART3RST_Msk          (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk
+#define RCC_APB1RSTR1_UART4RST_Pos           (19U)
+#define RCC_APB1RSTR1_UART4RST_Msk           (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
+#define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk
+#define RCC_APB1RSTR1_I2C1RST_Pos            (21U)
+#define RCC_APB1RSTR1_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk
+#define RCC_APB1RSTR1_I2C2RST_Pos            (22U)
+#define RCC_APB1RSTR1_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk
+#define RCC_APB1RSTR1_USBRST_Pos             (23U)
+#define RCC_APB1RSTR1_USBRST_Msk             (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
+#define RCC_APB1RSTR1_USBRST                 RCC_APB1RSTR1_USBRST_Msk
+#define RCC_APB1RSTR1_FDCANRST_Pos           (25U)
+#define RCC_APB1RSTR1_FDCANRST_Msk           (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
+#define RCC_APB1RSTR1_FDCANRST               RCC_APB1RSTR1_FDCANRST_Msk
+#define RCC_APB1RSTR1_PWRRST_Pos             (28U)
+#define RCC_APB1RSTR1_PWRRST_Msk             (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
+#define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk
+#define RCC_APB1RSTR1_I2C3RST_Pos            (30U)
+#define RCC_APB1RSTR1_I2C3RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
+#define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk
+#define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)
+#define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
+#define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)
+#define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
+#define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk
+#define RCC_APB1RSTR2_UCPD1RST_Pos           (8U)
+#define RCC_APB1RSTR2_UCPD1RST_Msk           (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
+#define RCC_APB1RSTR2_UCPD1RST               RCC_APB1RSTR2_UCPD1RST_Msk
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM1RST_Pos             (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos             (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos             (13U)
+#define RCC_APB2RSTR_TIM8RST_Msk             (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
+#define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos           (14U)
+#define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_TIM15RST_Pos            (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk            (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk
+#define RCC_APB2RSTR_TIM16RST_Pos            (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk            (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk
+#define RCC_APB2RSTR_TIM17RST_Pos            (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk            (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos             (21U)
+#define RCC_APB2RSTR_SAI1RST_Msk             (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos               (0U)
+#define RCC_AHB1ENR_DMA1EN_Msk               (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos               (1U)
+#define RCC_AHB1ENR_DMA2EN_Msk               (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_DMAMUX1EN_Pos            (2U)
+#define RCC_AHB1ENR_DMAMUX1EN_Msk            (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
+#define RCC_AHB1ENR_DMAMUX1EN                RCC_AHB1ENR_DMAMUX1EN_Msk
+#define RCC_AHB1ENR_CORDICEN_Pos             (3U)
+#define RCC_AHB1ENR_CORDICEN_Msk             (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
+#define RCC_AHB1ENR_CORDICEN                 RCC_AHB1ENR_CORDICEN_Msk
+#define RCC_AHB1ENR_FMACEN_Pos               (4U)
+#define RCC_AHB1ENR_FMACEN_Msk               (0x1UL << RCC_AHB1ENR_FMACEN_Pos)  /*!< 0x00000010 */
+#define RCC_AHB1ENR_FMACEN                   RCC_AHB1ENR_FMACEN_Msk
+#define RCC_AHB1ENR_FLASHEN_Pos              (8U)
+#define RCC_AHB1ENR_FLASHEN_Msk              (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
+#define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos                (12U)
+#define RCC_AHB1ENR_CRCEN_Msk                (0x1UL << RCC_AHB1ENR_CRCEN_Pos)  /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_GPIOAEN_Pos              (0U)
+#define RCC_AHB2ENR_GPIOAEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
+#define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk
+#define RCC_AHB2ENR_GPIOBEN_Pos              (1U)
+#define RCC_AHB2ENR_GPIOBEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
+#define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk
+#define RCC_AHB2ENR_GPIOCEN_Pos              (2U)
+#define RCC_AHB2ENR_GPIOCEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
+#define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk
+#define RCC_AHB2ENR_GPIODEN_Pos              (3U)
+#define RCC_AHB2ENR_GPIODEN_Msk              (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
+#define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk
+#define RCC_AHB2ENR_GPIOEEN_Pos              (4U)
+#define RCC_AHB2ENR_GPIOEEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
+#define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk
+#define RCC_AHB2ENR_GPIOFEN_Pos              (5U)
+#define RCC_AHB2ENR_GPIOFEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk
+#define RCC_AHB2ENR_GPIOGEN_Pos              (6U)
+#define RCC_AHB2ENR_GPIOGEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
+#define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk
+#define RCC_AHB2ENR_ADC12EN_Pos              (13U)
+#define RCC_AHB2ENR_ADC12EN_Msk              (0x1UL << RCC_AHB2ENR_ADC12EN_Pos)  /*!< 0x00002000 */
+#define RCC_AHB2ENR_ADC12EN                  RCC_AHB2ENR_ADC12EN_Msk
+#define RCC_AHB2ENR_DAC1EN_Pos               (16U)
+#define RCC_AHB2ENR_DAC1EN_Msk               (0x1UL << RCC_AHB2ENR_DAC1EN_Pos)  /*!< 0x00010000 */
+#define RCC_AHB2ENR_DAC1EN                   RCC_AHB2ENR_DAC1EN_Msk
+#define RCC_AHB2ENR_DAC3EN_Pos               (18U)
+#define RCC_AHB2ENR_DAC3EN_Msk               (0x1UL << RCC_AHB2ENR_DAC3EN_Pos)  /*!< 0x00040000 */
+#define RCC_AHB2ENR_DAC3EN                   RCC_AHB2ENR_DAC3EN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos                (26U)
+#define RCC_AHB2ENR_RNGEN_Msk                (0x1UL << RCC_AHB2ENR_RNGEN_Pos)  /*!< 0x04000000 */
+#define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+
+/********************  Bit definition for RCC_APB1ENR1 register  ***************/
+#define RCC_APB1ENR1_TIM2EN_Pos              (0U)
+#define RCC_APB1ENR1_TIM2EN_Msk              (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk
+#define RCC_APB1ENR1_TIM3EN_Pos              (1U)
+#define RCC_APB1ENR1_TIM3EN_Msk              (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
+#define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk
+#define RCC_APB1ENR1_TIM4EN_Pos              (2U)
+#define RCC_APB1ENR1_TIM4EN_Msk              (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
+#define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk
+#define RCC_APB1ENR1_TIM6EN_Pos              (4U)
+#define RCC_APB1ENR1_TIM6EN_Msk              (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk
+#define RCC_APB1ENR1_TIM7EN_Pos              (5U)
+#define RCC_APB1ENR1_TIM7EN_Msk              (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk
+#define RCC_APB1ENR1_CRSEN_Pos               (8U)
+#define RCC_APB1ENR1_CRSEN_Msk               (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk
+#define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)
+#define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
+#define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk
+#define RCC_APB1ENR1_WWDGEN_Pos              (11U)
+#define RCC_APB1ENR1_WWDGEN_Msk              (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk
+#define RCC_APB1ENR1_SPI2EN_Pos              (14U)
+#define RCC_APB1ENR1_SPI2EN_Msk              (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk
+#define RCC_APB1ENR1_SPI3EN_Pos              (15U)
+#define RCC_APB1ENR1_SPI3EN_Msk              (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk
+#define RCC_APB1ENR1_USART2EN_Pos            (17U)
+#define RCC_APB1ENR1_USART2EN_Msk            (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk
+#define RCC_APB1ENR1_USART3EN_Pos            (18U)
+#define RCC_APB1ENR1_USART3EN_Msk            (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk
+#define RCC_APB1ENR1_UART4EN_Pos             (19U)
+#define RCC_APB1ENR1_UART4EN_Msk             (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
+#define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk
+#define RCC_APB1ENR1_I2C1EN_Pos              (21U)
+#define RCC_APB1ENR1_I2C1EN_Msk              (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk
+#define RCC_APB1ENR1_I2C2EN_Pos              (22U)
+#define RCC_APB1ENR1_I2C2EN_Msk              (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk
+#define RCC_APB1ENR1_USBEN_Pos               (23U)
+#define RCC_APB1ENR1_USBEN_Msk               (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
+#define RCC_APB1ENR1_USBEN                   RCC_APB1ENR1_USBEN_Msk
+#define RCC_APB1ENR1_FDCANEN_Pos             (25U)
+#define RCC_APB1ENR1_FDCANEN_Msk             (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
+#define RCC_APB1ENR1_FDCANEN                 RCC_APB1ENR1_FDCANEN_Msk
+#define RCC_APB1ENR1_PWREN_Pos               (28U)
+#define RCC_APB1ENR1_PWREN_Msk               (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk
+#define RCC_APB1ENR1_I2C3EN_Pos              (30U)
+#define RCC_APB1ENR1_I2C3EN_Msk              (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
+#define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk
+#define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)
+#define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
+#define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1ENR2_LPUART1EN_Pos           (0U)
+#define RCC_APB1ENR2_LPUART1EN_Msk           (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
+#define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk
+#define RCC_APB1ENR2_UCPD1EN_Pos             (8U)
+#define RCC_APB1ENR2_UCPD1EN_Msk             (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
+#define RCC_APB1ENR2_UCPD1EN                 RCC_APB1ENR2_UCPD1EN_Msk
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define RCC_APB2ENR_SYSCFGEN_Pos             (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM1EN_Pos               (11U)
+#define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos               (12U)
+#define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos               (13U)
+#define RCC_APB2ENR_TIM8EN_Msk               (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos             (14U)
+#define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_TIM15EN_Pos              (16U)
+#define RCC_APB2ENR_TIM15EN_Msk              (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk
+#define RCC_APB2ENR_TIM16EN_Pos              (17U)
+#define RCC_APB2ENR_TIM16EN_Msk              (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk
+#define RCC_APB2ENR_TIM17EN_Pos              (18U)
+#define RCC_APB2ENR_TIM17EN_Msk              (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos               (21U)
+#define RCC_APB2ENR_SAI1EN_Msk               (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk
+
+/********************  Bit definition for RCC_AHB1SMENR register  ***************/
+#define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)
+#define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
+#define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk
+#define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)
+#define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
+#define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk
+#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos        (2U)
+#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk        (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
+#define RCC_AHB1SMENR_DMAMUX1SMEN            RCC_AHB1SMENR_DMAMUX1SMEN_Msk
+#define RCC_AHB1SMENR_CORDICSMEN_Pos         (3U)
+#define RCC_AHB1SMENR_CORDICSMEN_Msk         (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
+#define RCC_AHB1SMENR_CORDICSMEN             RCC_AHB1SMENR_CORDICSMEN_Msk
+#define RCC_AHB1SMENR_FMACSMEN_Pos           (4U)
+#define RCC_AHB1SMENR_FMACSMEN_Msk           (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos)  /*!< 0x00000010 */
+#define RCC_AHB1SMENR_FMACSMEN               RCC_AHB1SMENR_FMACSMEN_Msk
+#define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)
+#define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
+#define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk
+#define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)
+#define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
+#define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk
+#define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)
+#define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
+#define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk
+
+/********************  Bit definition for RCC_AHB2SMENR register  *************/
+#define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)
+#define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
+#define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk
+#define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)
+#define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
+#define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk
+#define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)
+#define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
+#define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk
+#define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)
+#define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
+#define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk
+#define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)
+#define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
+#define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk
+#define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)
+#define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk
+#define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)
+#define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
+#define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk
+#define RCC_AHB2SMENR_CCMSRAMSMEN_Pos        (9U)
+#define RCC_AHB2SMENR_CCMSRAMSMEN_Msk        (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos)  /*!< 0x00000200 */
+#define RCC_AHB2SMENR_CCMSRAMSMEN            RCC_AHB2SMENR_CCMSRAMSMEN_Msk
+#define RCC_AHB2SMENR_SRAM2SMEN_Pos          (10U)
+#define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
+#define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk
+#define RCC_AHB2SMENR_ADC12SMEN_Pos          (13U)
+#define RCC_AHB2SMENR_ADC12SMEN_Msk          (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
+#define RCC_AHB2SMENR_ADC12SMEN              RCC_AHB2SMENR_ADC12SMEN_Msk
+#define RCC_AHB2SMENR_DAC1SMEN_Pos           (16U)
+#define RCC_AHB2SMENR_DAC1SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
+#define RCC_AHB2SMENR_DAC1SMEN               RCC_AHB2SMENR_DAC1SMEN_Msk
+#define RCC_AHB2SMENR_DAC3SMEN_Pos           (18U)
+#define RCC_AHB2SMENR_DAC3SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
+#define RCC_AHB2SMENR_DAC3SMEN               RCC_AHB2SMENR_DAC3SMEN_Msk
+#define RCC_AHB2SMENR_RNGSMEN_Pos            (26U)
+#define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
+#define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk
+
+/********************  Bit definition for RCC_AHB3SMENR register  *************/
+
+/********************  Bit definition for RCC_APB1SMENR1 register  *************/
+#define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)
+#define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
+#define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk
+#define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)
+#define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
+#define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk
+#define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)
+#define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
+#define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk
+#define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)
+#define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
+#define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk
+#define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)
+#define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
+#define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk
+#define RCC_APB1SMENR1_CRSSMEN_Pos           (8U)
+#define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
+#define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk
+#define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)
+#define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
+#define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk
+#define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)
+#define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
+#define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk
+#define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)
+#define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
+#define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk
+#define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)
+#define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
+#define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk
+#define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)
+#define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
+#define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk
+#define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)
+#define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
+#define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk
+#define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)
+#define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
+#define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk
+#define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)
+#define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
+#define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk
+#define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)
+#define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
+#define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk
+#define RCC_APB1SMENR1_USBSMEN_Pos           (23U)
+#define RCC_APB1SMENR1_USBSMEN_Msk           (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
+#define RCC_APB1SMENR1_USBSMEN               RCC_APB1SMENR1_USBSMEN_Msk
+#define RCC_APB1SMENR1_FDCANSMEN_Pos         (25U)
+#define RCC_APB1SMENR1_FDCANSMEN_Msk         (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
+#define RCC_APB1SMENR1_FDCANSMEN             RCC_APB1SMENR1_FDCANSMEN_Msk
+#define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)
+#define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
+#define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk
+#define RCC_APB1SMENR1_I2C3SMEN_Pos          (30U)
+#define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
+#define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk
+#define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)
+#define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
+#define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk
+
+/********************  Bit definition for RCC_APB1SMENR2 register  *************/
+#define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)
+#define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
+#define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk
+#define RCC_APB1SMENR2_UCPD1SMEN_Pos         (8U)
+#define RCC_APB1SMENR2_UCPD1SMEN_Msk         (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
+#define RCC_APB1SMENR2_UCPD1SMEN             RCC_APB1SMENR2_UCPD1SMEN_Msk
+
+/********************  Bit definition for RCC_APB2SMENR register  *************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk
+#define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)
+#define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
+#define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk
+#define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk
+#define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)
+#define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
+#define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk
+#define RCC_APB2SMENR_USART1SMEN_Pos         (14U)
+#define RCC_APB2SMENR_USART1SMEN_Msk         (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk
+#define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)
+#define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
+#define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk
+#define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)
+#define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
+#define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk
+#define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)
+#define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
+#define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk
+#define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)
+#define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
+#define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk
+
+/********************  Bit definition for RCC_CCIPR register  ******************/
+#define RCC_CCIPR_USART1SEL_Pos              (0U)
+#define RCC_CCIPR_USART1SEL_Msk              (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk
+#define RCC_CCIPR_USART1SEL_0                (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1                (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
+
+#define RCC_CCIPR_USART2SEL_Pos              (2U)
+#define RCC_CCIPR_USART2SEL_Msk              (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk
+#define RCC_CCIPR_USART2SEL_0                (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1                (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
+
+#define RCC_CCIPR_USART3SEL_Pos              (4U)
+#define RCC_CCIPR_USART3SEL_Msk              (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
+#define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk
+#define RCC_CCIPR_USART3SEL_0                (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
+#define RCC_CCIPR_USART3SEL_1                (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
+
+#define RCC_CCIPR_UART4SEL_Pos               (6U)
+#define RCC_CCIPR_UART4SEL_Msk               (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
+#define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk
+#define RCC_CCIPR_UART4SEL_0                 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
+#define RCC_CCIPR_UART4SEL_1                 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
+
+
+#define RCC_CCIPR_LPUART1SEL_Pos             (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk             (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk
+#define RCC_CCIPR_LPUART1SEL_0               (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
+#define RCC_CCIPR_LPUART1SEL_1               (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
+
+#define RCC_CCIPR_I2C1SEL_Pos                (12U)
+#define RCC_CCIPR_I2C1SEL_Msk                (0x3UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk
+#define RCC_CCIPR_I2C1SEL_0                  (0x1UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1                  (0x2UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00002000 */
+
+#define RCC_CCIPR_I2C2SEL_Pos                (14U)
+#define RCC_CCIPR_I2C2SEL_Msk                (0x3UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x0000C000 */
+#define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk
+#define RCC_CCIPR_I2C2SEL_0                  (0x1UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00004000 */
+#define RCC_CCIPR_I2C2SEL_1                  (0x2UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00008000 */
+
+#define RCC_CCIPR_I2C3SEL_Pos                (16U)
+#define RCC_CCIPR_I2C3SEL_Msk                (0x3UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk
+#define RCC_CCIPR_I2C3SEL_0                  (0x1UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1                  (0x2UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00020000 */
+
+#define RCC_CCIPR_LPTIM1SEL_Pos              (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk
+#define RCC_CCIPR_LPTIM1SEL_0                (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1                (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
+
+#define RCC_CCIPR_SAI1SEL_Pos                (20U)
+#define RCC_CCIPR_SAI1SEL_Msk                (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
+#define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk
+#define RCC_CCIPR_SAI1SEL_0                  (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
+#define RCC_CCIPR_SAI1SEL_1                  (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
+
+#define RCC_CCIPR_I2S23SEL_Pos               (22U)
+#define RCC_CCIPR_I2S23SEL_Msk               (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
+#define RCC_CCIPR_I2S23SEL                   RCC_CCIPR_I2S23SEL_Msk
+#define RCC_CCIPR_I2S23SEL_0                 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
+#define RCC_CCIPR_I2S23SEL_1                 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
+
+#define RCC_CCIPR_FDCANSEL_Pos               (24U)
+#define RCC_CCIPR_FDCANSEL_Msk               (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
+#define RCC_CCIPR_FDCANSEL                   RCC_CCIPR_FDCANSEL_Msk
+#define RCC_CCIPR_FDCANSEL_0                 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
+#define RCC_CCIPR_FDCANSEL_1                 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
+
+#define RCC_CCIPR_CLK48SEL_Pos               (26U)
+#define RCC_CCIPR_CLK48SEL_Msk               (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
+#define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk
+#define RCC_CCIPR_CLK48SEL_0                 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
+#define RCC_CCIPR_CLK48SEL_1                 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CCIPR_ADC12SEL_Pos               (28U)
+#define RCC_CCIPR_ADC12SEL_Msk               (0x3UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x30000000 */
+#define RCC_CCIPR_ADC12SEL                   RCC_CCIPR_ADC12SEL_Msk
+#define RCC_CCIPR_ADC12SEL_0                 (0x1UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x10000000 */
+#define RCC_CCIPR_ADC12SEL_1                 (0x2UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x20000000 */
+
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                   (0U)
+#define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)     /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos                  (1U)
+#define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)    /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos                  (2U)
+#define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)    /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_LSEDRV_Pos                  (3U)
+#define RCC_BDCR_LSEDRV_Msk                  (0x3UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk
+#define RCC_BDCR_LSEDRV_0                    (0x1UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                    (0x2UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                (5U)
+#define RCC_BDCR_LSECSSON_Msk                (0x1UL << RCC_BDCR_LSECSSON_Pos)  /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk
+#define RCC_BDCR_LSECSSD_Pos                 (6U)
+#define RCC_BDCR_LSECSSD_Msk                 (0x1UL << RCC_BDCR_LSECSSD_Pos)   /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos                  (8U)
+#define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                   (15U)
+#define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)     /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos                   (16U)
+#define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)     /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk
+#define RCC_BDCR_LSCOEN_Pos                  (24U)
+#define RCC_BDCR_LSCOEN_Msk                  (0x1UL << RCC_BDCR_LSCOEN_Pos)    /*!< 0x01000000 */
+#define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk
+#define RCC_BDCR_LSCOSEL_Pos                 (25U)
+#define RCC_BDCR_LSCOSEL_Msk                 (0x1UL << RCC_BDCR_LSCOSEL_Pos)   /*!< 0x02000000 */
+#define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                    (0U)
+#define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
+#define RCC_CSR_LSION                        RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos                   (1U)
+#define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk
+
+#define RCC_CSR_RMVF_Pos                     (23U)
+#define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */
+#define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk
+#define RCC_CSR_OBLRSTF_Pos                  (25U)
+#define RCC_CSR_OBLRSTF_Msk                  (0x1UL << RCC_CSR_OBLRSTF_Pos)    /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos                  (26U)
+#define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)    /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_BORRSTF_Pos                  (27U)
+#define RCC_CSR_BORRSTF_Msk                  (0x1UL << RCC_CSR_BORRSTF_Pos)    /*!< 0x08000000 */
+#define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos                  (28U)
+#define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)    /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos                 (29U)
+#define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)   /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos                 (30U)
+#define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)   /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos                 (31U)
+#define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)   /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk
+
+/********************  Bit definition for RCC_CRRCR register  *****************/
+#define RCC_CRRCR_HSI48ON_Pos                (0U)
+#define RCC_CRRCR_HSI48ON_Msk                (0x1UL << RCC_CRRCR_HSI48ON_Pos)  /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk
+#define RCC_CRRCR_HSI48RDY_Pos               (1U)
+#define RCC_CRRCR_HSI48RDY_Msk               (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk
+
+/*!< HSI48CAL configuration */
+#define RCC_CRRCR_HSI48CAL_Pos               (7U)
+#define RCC_CRRCR_HSI48CAL_Msk               (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
+#define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
+#define RCC_CRRCR_HSI48CAL_0                 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
+#define RCC_CRRCR_HSI48CAL_1                 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
+#define RCC_CRRCR_HSI48CAL_2                 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
+#define RCC_CRRCR_HSI48CAL_3                 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
+#define RCC_CRRCR_HSI48CAL_4                 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
+#define RCC_CRRCR_HSI48CAL_5                 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
+#define RCC_CRRCR_HSI48CAL_6                 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
+#define RCC_CRRCR_HSI48CAL_7                 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
+#define RCC_CRRCR_HSI48CAL_8                 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
+
+/********************  Bit definition for RCC_CCIPR2 register  ******************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)
+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos       (3U)
+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos      (5U)
+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000020 */
+#define RNG_CR_CED          RNG_CR_IE_Msk
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)
+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos     (1U)
+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos     (2U)
+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos     (5U)
+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos     (6U)
+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                (22U)
+#define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
+#define RTC_TR_PM                    RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos                (20U)
+#define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
+#define RTC_TR_HT                    RTC_TR_HT_Msk
+#define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
+#define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                (16U)
+#define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
+#define RTC_TR_HU                    RTC_TR_HU_Msk
+#define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
+#define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
+#define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
+#define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos               (12U)
+#define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
+#define RTC_TR_MNT                   RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
+#define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
+#define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos               (8U)
+#define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
+#define RTC_TR_MNU                   RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
+#define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
+#define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
+#define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                (4U)
+#define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
+#define RTC_TR_ST                    RTC_TR_ST_Msk
+#define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
+#define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
+#define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                (0U)
+#define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
+#define RTC_TR_SU                    RTC_TR_SU_Msk
+#define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
+#define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
+#define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
+#define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                (20U)
+#define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
+#define RTC_DR_YT                    RTC_DR_YT_Msk
+#define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
+#define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
+#define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
+#define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                (16U)
+#define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
+#define RTC_DR_YU                    RTC_DR_YU_Msk
+#define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
+#define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
+#define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
+#define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos               (13U)
+#define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
+#define RTC_DR_WDU                   RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
+#define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
+#define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                (12U)
+#define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
+#define RTC_DR_MT                    RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos                (8U)
+#define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
+#define RTC_DR_MU                    RTC_DR_MU_Msk
+#define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
+#define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
+#define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
+#define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                (4U)
+#define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
+#define RTC_DR_DT                    RTC_DR_DT_Msk
+#define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
+#define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                (0U)
+#define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
+#define RTC_DR_DU                    RTC_DR_DU_Msk
+#define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
+#define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
+#define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
+#define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos               (0U)
+#define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
+#define RTC_SSR_SS                   RTC_SSR_SS_Msk
+
+/********************  Bits definition for RTC_ICSR register  ******************/
+#define RTC_ICSR_RECALPF_Pos         (16U)
+#define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
+#define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
+#define RTC_ICSR_INIT_Pos            (7U)
+#define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
+#define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
+#define RTC_ICSR_INITF_Pos           (6U)
+#define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
+#define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
+#define RTC_ICSR_RSF_Pos             (5U)
+#define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
+#define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
+#define RTC_ICSR_INITS_Pos           (4U)
+#define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
+#define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
+#define RTC_ICSR_SHPF_Pos            (3U)
+#define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
+#define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
+#define RTC_ICSR_WUTWF_Pos           (2U)
+#define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
+#define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
+#define RTC_ICSR_ALRBWF_Pos          (1U)
+#define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */
+#define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk
+#define RTC_ICSR_ALRAWF_Pos          (0U)
+#define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */
+#define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos        (16U)
+#define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos        (0U)
+#define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos             (0U)
+#define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_OUT2EN_Pos            (31U)
+#define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
+#define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
+#define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
+#define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
+#define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
+#define RTC_CR_TAMPALRM_PU_Pos       (29U)
+#define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
+#define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
+#define RTC_CR_TAMPOE_Pos            (26U)
+#define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
+#define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
+#define RTC_CR_TAMPTS_Pos            (25U)
+#define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
+#define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
+#define RTC_CR_ITSE_Pos              (24U)
+#define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
+#define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!<Timestamp on internal event enable  */
+#define RTC_CR_COE_Pos               (23U)
+#define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
+#define RTC_CR_COE                   RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos              (21U)
+#define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
+#define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
+#define RTC_CR_POL_Pos               (20U)
+#define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
+#define RTC_CR_POL                   RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos             (19U)
+#define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
+#define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos               (18U)
+#define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                 /*!< 0x00040000 */
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos             (17U)
+#define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
+#define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos             (16U)
+#define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
+#define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos              (15U)
+#define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
+#define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos             (14U)
+#define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
+#define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos            (13U)
+#define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos            (12U)
+#define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos               (11U)
+#define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
+#define RTC_CR_TSE                   RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos              (10U)
+#define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
+#define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos             (9U)
+#define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
+#define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos             (8U)
+#define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
+#define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
+#define RTC_CR_FMT_Pos               (6U)
+#define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
+#define RTC_CR_FMT                   RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos           (5U)
+#define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos           (4U)
+#define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
+#define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos            (3U)
+#define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos           (0U)
+#define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos              (0U)
+#define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
+#define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
+
+/********************  Bits definition for RTC_CALR register  *****************/
+#define RTC_CALR_CALP_Pos            (15U)
+#define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
+#define RTC_CALR_CALP                RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos           (14U)
+#define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
+#define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos          (13U)
+#define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
+#define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos            (0U)
+#define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
+#define RTC_CALR_CALM                RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
+#define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
+#define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
+#define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
+#define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
+#define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
+#define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
+#define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
+#define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos         (0U)
+#define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos         (31U)
+#define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos              (22U)
+#define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TSTR_PM                  RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos              (20U)
+#define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos              (16U)
+#define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos             (12U)
+#define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos             (8U)
+#define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos              (4U)
+#define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos              (0U)
+#define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos             (13U)
+#define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos              (12U)
+#define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos              (8U)
+#define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos              (4U)
+#define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos              (0U)
+#define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos             (0U)
+#define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos          (31U)
+#define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos         (30U)
+#define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos            (28U)
+#define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos            (24U)
+#define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos          (23U)
+#define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos            (22U)
+#define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos            (20U)
+#define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos            (16U)
+#define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos          (15U)
+#define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos           (12U)
+#define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos           (8U)
+#define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos          (7U)
+#define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos            (4U)
+#define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos            (0U)
+#define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos      (24U)
+#define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos          (0U)
+#define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos          (31U)
+#define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos         (30U)
+#define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos            (28U)
+#define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos            (24U)
+#define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos          (23U)
+#define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos            (22U)
+#define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos            (20U)
+#define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos            (16U)
+#define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos          (15U)
+#define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos           (12U)
+#define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos           (8U)
+#define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos          (7U)
+#define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos            (4U)
+#define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos            (0U)
+#define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos      (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk      (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos          (0U)
+#define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
+
+/********************  Bits definition for RTC_SR register  *******************/
+#define RTC_SR_ITSF_Pos              (5U)
+#define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
+#define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
+#define RTC_SR_TSOVF_Pos             (4U)
+#define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
+#define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
+#define RTC_SR_TSF_Pos               (3U)
+#define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
+#define RTC_SR_TSF                   RTC_SR_TSF_Msk
+#define RTC_SR_WUTF_Pos              (2U)
+#define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
+#define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
+#define RTC_SR_ALRBF_Pos             (1U)
+#define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
+#define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
+#define RTC_SR_ALRAF_Pos             (0U)
+#define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
+#define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
+
+/********************  Bits definition for RTC_MISR register  *****************/
+#define RTC_MISR_ITSMF_Pos           (5U)
+#define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
+#define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
+#define RTC_MISR_TSOVMF_Pos          (4U)
+#define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
+#define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
+#define RTC_MISR_TSMF_Pos            (3U)
+#define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
+#define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
+#define RTC_MISR_WUTMF_Pos           (2U)
+#define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
+#define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
+#define RTC_MISR_ALRBMF_Pos          (1U)
+#define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
+#define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
+#define RTC_MISR_ALRAMF_Pos          (0U)
+#define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
+#define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
+
+/********************  Bits definition for RTC_SCR register  ******************/
+#define RTC_SCR_CITSF_Pos            (5U)
+#define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
+#define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
+#define RTC_SCR_CTSOVF_Pos           (4U)
+#define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
+#define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
+#define RTC_SCR_CTSF_Pos             (3U)
+#define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
+#define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
+#define RTC_SCR_CWUTF_Pos            (2U)
+#define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
+#define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
+#define RTC_SCR_CALRBF_Pos           (1U)
+#define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
+#define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
+#define RTC_SCR_CALRAF_Pos           (0U)
+#define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
+#define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Tamper and backup register (TAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for TAMP_CR1 register  *****************/
+#define TAMP_CR1_TAMP1E_Pos          (0U)
+#define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
+#define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
+#define TAMP_CR1_TAMP2E_Pos          (1U)
+#define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
+#define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
+#define TAMP_CR1_TAMP3E_Pos          (2U)
+#define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
+#define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
+#define TAMP_CR1_ITAMP3E_Pos         (18U)
+#define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
+#define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
+#define TAMP_CR1_ITAMP4E_Pos         (19U)
+#define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */
+#define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk
+#define TAMP_CR1_ITAMP5E_Pos         (20U)
+#define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
+#define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
+#define TAMP_CR1_ITAMP6E_Pos         (21U)
+#define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */
+#define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
+
+/********************  Bits definition for TAMP_CR2 register  *****************/
+#define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
+#define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */
+#define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
+#define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
+#define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */
+#define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
+#define TAMP_CR2_TAMP3NOERASE_Pos    (2U)
+#define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */
+#define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk
+#define TAMP_CR2_TAMP1MF_Pos         (16U)
+#define TAMP_CR2_TAMP1MF_Msk         (0x1UL << TAMP_CR2_TAMP1MF_Pos)           /*!< 0x00010000 */
+#define TAMP_CR2_TAMP1MF             TAMP_CR2_TAMP1MF_Msk
+#define TAMP_CR2_TAMP2MF_Pos         (17U)
+#define TAMP_CR2_TAMP2MF_Msk         (0x1UL << TAMP_CR2_TAMP2MF_Pos)           /*!< 0x00020000 */
+#define TAMP_CR2_TAMP2MF             TAMP_CR2_TAMP2MF_Msk
+#define TAMP_CR2_TAMP3MF_Pos         (18U)
+#define TAMP_CR2_TAMP3MF_Msk         (0x1UL << TAMP_CR2_TAMP3MF_Pos)           /*!< 0x00040000 */
+#define TAMP_CR2_TAMP3MF             TAMP_CR2_TAMP3MF_Msk
+#define TAMP_CR2_TAMP1TRG_Pos        (24U)
+#define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
+#define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
+#define TAMP_CR2_TAMP2TRG_Pos        (25U)
+#define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
+#define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
+#define TAMP_CR2_TAMP3TRG_Pos        (26U)
+#define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */
+#define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
+
+/********************  Bits definition for TAMP_FLTCR register  ***************/
+#define TAMP_FLTCR_TAMPFREQ_0        (0x00000001UL)
+#define TAMP_FLTCR_TAMPFREQ_1        (0x00000002UL)
+#define TAMP_FLTCR_TAMPFREQ_2        (0x00000004UL)
+#define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
+#define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000007 */
+#define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
+#define TAMP_FLTCR_TAMPFLT_0         (0x00000008UL)
+#define TAMP_FLTCR_TAMPFLT_1         (0x00000010UL)
+#define TAMP_FLTCR_TAMPFLT_Pos       (3U)
+#define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000018 */
+#define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
+#define TAMP_FLTCR_TAMPPRCH_0        (0x00000020UL)
+#define TAMP_FLTCR_TAMPPRCH_1        (0x00000040UL)
+#define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
+#define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000060 */
+#define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
+#define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
+#define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)       /*!< 0x00000080 */
+#define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
+
+/********************  Bits definition for TAMP_IER register  *****************/
+#define TAMP_IER_TAMP1IE_Pos         (0U)
+#define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
+#define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
+#define TAMP_IER_TAMP2IE_Pos         (1U)
+#define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
+#define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
+#define TAMP_IER_TAMP3IE_Pos         (2U)
+#define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
+#define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
+#define TAMP_IER_ITAMP3IE_Pos        (18U)
+#define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
+#define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
+#define TAMP_IER_ITAMP4IE_Pos        (19U)
+#define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */
+#define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk
+#define TAMP_IER_ITAMP5IE_Pos        (20U)
+#define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
+#define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
+#define TAMP_IER_ITAMP6IE_Pos        (21U)
+#define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */
+#define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
+
+/********************  Bits definition for TAMP_SR register  ******************/
+#define TAMP_SR_TAMP1F_Pos           (0U)
+#define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)       /*!< 0x00000001 */
+#define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
+#define TAMP_SR_TAMP2F_Pos           (1U)
+#define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)       /*!< 0x00000002 */
+#define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
+#define TAMP_SR_TAMP3F_Pos           (2U)
+#define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)       /*!< 0x00000004 */
+#define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
+#define TAMP_SR_ITAMP3F_Pos          (18U)
+#define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)      /*!< 0x00040000 */
+#define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
+#define TAMP_SR_ITAMP4F_Pos          (19U)
+#define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)      /*!< 0x00080000 */
+#define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk
+#define TAMP_SR_ITAMP5F_Pos          (20U)
+#define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)      /*!< 0x00100000 */
+#define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
+#define TAMP_SR_ITAMP6F_Pos          (21U)
+#define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)      /*!< 0x00200000 */
+#define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
+
+/********************  Bits definition for TAMP_MISR register  ****************/
+#define TAMP_MISR_TAMP1MF_Pos        (0U)
+#define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)       /*!< 0x00000001 */
+#define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
+#define TAMP_MISR_TAMP2MF_Pos        (1U)
+#define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)       /*!< 0x00000002 */
+#define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
+#define TAMP_MISR_TAMP3MF_Pos        (2U)
+#define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)       /*!< 0x00000004 */
+#define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
+#define TAMP_MISR_ITAMP3MF_Pos       (18U)
+#define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
+#define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
+#define TAMP_MISR_ITAMP4MF_Pos       (19U)
+#define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)      /*!< 0x00080000 */
+#define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk
+#define TAMP_MISR_ITAMP5MF_Pos       (20U)
+#define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
+#define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
+#define TAMP_MISR_ITAMP6MF_Pos       (21U)
+#define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
+#define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
+
+/********************  Bits definition for TAMP_SCR register  *****************/
+#define TAMP_SCR_CTAMP1F_Pos         (0U)
+#define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)       /*!< 0x00000001 */
+#define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
+#define TAMP_SCR_CTAMP2F_Pos         (1U)
+#define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)       /*!< 0x00000002 */
+#define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
+#define TAMP_SCR_CTAMP3F_Pos         (2U)
+#define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)       /*!< 0x00000004 */
+#define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
+#define TAMP_SCR_CITAMP3F_Pos        (18U)
+#define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)      /*!< 0x00040000 */
+#define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
+#define TAMP_SCR_CITAMP4F_Pos        (19U)
+#define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)      /*!< 0x00080000 */
+#define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk
+#define TAMP_SCR_CITAMP5F_Pos        (20U)
+#define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)      /*!< 0x00100000 */
+#define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
+#define TAMP_SCR_CITAMP6F_Pos        (21U)
+#define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)      /*!< 0x00200000 */
+#define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
+
+/********************  Bits definition for TAMP_BKP0R register  ***************/
+#define TAMP_BKP0R_Pos               (0U)
+#define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)         /*!< 0xFFFFFFFF */
+#define TAMP_BKP0R                   TAMP_BKP0R_Msk
+
+/********************  Bits definition for TAMP_BKP1R register  ***************/
+#define TAMP_BKP1R_Pos               (0U)
+#define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP1R                   TAMP_BKP1R_Msk
+
+/********************  Bits definition for TAMP_BKP2R register  ***************/
+#define TAMP_BKP2R_Pos               (0U)
+#define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP2R                   TAMP_BKP2R_Msk
+
+/********************  Bits definition for TAMP_BKP3R register  ***************/
+#define TAMP_BKP3R_Pos               (0U)
+#define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP3R                   TAMP_BKP3R_Msk
+
+/********************  Bits definition for TAMP_BKP4R register  ***************/
+#define TAMP_BKP4R_Pos               (0U)
+#define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP4R                   TAMP_BKP4R_Msk
+
+/********************  Bits definition for TAMP_BKP5R register  ***************/
+#define TAMP_BKP5R_Pos               (0U)
+#define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP5R                   TAMP_BKP5R_Msk
+
+/********************  Bits definition for TAMP_BKP6R register  ***************/
+#define TAMP_BKP6R_Pos               (0U)
+#define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP6R                   TAMP_BKP6R_Msk
+
+/********************  Bits definition for TAMP_BKP7R register  ***************/
+#define TAMP_BKP7R_Pos               (0U)
+#define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP7R                   TAMP_BKP7R_Msk
+
+/********************  Bits definition for TAMP_BKP8R register  ***************/
+#define TAMP_BKP8R_Pos               (0U)
+#define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP8R                   TAMP_BKP8R_Msk
+
+/********************  Bits definition for TAMP_BKP9R register  ***************/
+#define TAMP_BKP9R_Pos               (0U)
+#define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP9R                   TAMP_BKP9R_Msk
+
+/********************  Bits definition for TAMP_BKP10R register  ***************/
+#define TAMP_BKP10R_Pos               (0U)
+#define TAMP_BKP10R_Msk               (0xFFFFFFFFUL << TAMP_BKP10R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP10R                   TAMP_BKP10R_Msk
+
+/********************  Bits definition for TAMP_BKP11R register  ***************/
+#define TAMP_BKP11R_Pos               (0U)
+#define TAMP_BKP11R_Msk               (0xFFFFFFFFUL << TAMP_BKP11R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP11R                   TAMP_BKP11R_Msk
+
+/********************  Bits definition for TAMP_BKP12R register  ***************/
+#define TAMP_BKP12R_Pos               (0U)
+#define TAMP_BKP12R_Msk               (0xFFFFFFFFUL << TAMP_BKP12R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP12R                   TAMP_BKP12R_Msk
+
+/********************  Bits definition for TAMP_BKP13R register  ***************/
+#define TAMP_BKP13R_Pos               (0U)
+#define TAMP_BKP13R_Msk               (0xFFFFFFFFUL << TAMP_BKP13R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP13R                   TAMP_BKP13R_Msk
+
+/********************  Bits definition for TAMP_BKP14R register  ***************/
+#define TAMP_BKP14R_Pos               (0U)
+#define TAMP_BKP14R_Msk               (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP14R                   TAMP_BKP14R_Msk
+
+/********************  Bits definition for TAMP_BKP15R register  ***************/
+#define TAMP_BKP15R_Pos               (0U)
+#define TAMP_BKP15R_Msk               (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */
+#define TAMP_BKP15R                   TAMP_BKP15R_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)
+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)
+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)
+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)
+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)
+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)
+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)
+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)
+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)
+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)
+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)
+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)
+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)
+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)
+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x00100000U)                               /*!<Bit 0  */
+#define SAI_xCR1_MCKDIV_1          (0x00200000U)                               /*!<Bit 1  */
+#define SAI_xCR1_MCKDIV_2          (0x00400000U)                               /*!<Bit 2  */
+#define SAI_xCR1_MCKDIV_3          (0x00800000U)                               /*!<Bit 3  */
+#define SAI_xCR1_MCKDIV_4          (0x01000000U)                               /*!<Bit 4  */
+#define SAI_xCR1_MCKDIV_5          (0x02000000U)                               /*!<Bit 5  */
+
+#define SAI_xCR1_OSR_Pos           (26U)
+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */
+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<Oversampling ratio for master clock */
+
+#define SAI_xCR1_MCKEN_Pos         (27U)
+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */
+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master clock generation enable */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)
+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)
+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)
+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)
+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)
+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)
+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)
+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */
+#define SAI_xCR2_COMP_Pos          (14U)
+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                /*!< 0x00008000 */
+
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)
+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)
+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)
+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos        (17U)
+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)
+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)
+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)
+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)
+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)
+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)
+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)
+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)
+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)
+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)
+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)
+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)
+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)
+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)
+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos           (0U)
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk
+
+/******************  Bit definition for SAI_PDMCR register  *******************/
+#define SAI_PDMCR_PDMEN_Pos        (0U)
+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM enable */
+
+#define SAI_PDMCR_MICNBR_Pos       (4U)
+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<MICNBR[1:0] (Number of microphones) */
+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000020 */
+
+#define SAI_PDMCR_CKEN1_Pos        (8U)
+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock 1 enable */
+#define SAI_PDMCR_CKEN2_Pos        (9U)
+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock 2 enable */
+#define SAI_PDMCR_CKEN3_Pos        (10U)
+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock 3 enable */
+#define SAI_PDMCR_CKEN4_Pos        (11U)
+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock 4 enable */
+
+/******************  Bit definition for SAI_PDMDLY register  ******************/
+#define SAI_PDMDLY_DLYM1L_Pos      (0U)
+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000004 */
+
+#define SAI_PDMDLY_DLYM1R_Pos      (4U)
+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000040 */
+
+#define SAI_PDMDLY_DLYM2L_Pos      (8U)
+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000400 */
+
+#define SAI_PDMDLY_DLYM2R_Pos      (12U)
+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00004000 */
+
+#define SAI_PDMDLY_DLYM3L_Pos      (16U)
+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00040000 */
+
+#define SAI_PDMDLY_DLYM3R_Pos      (20U)
+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00400000 */
+
+#define SAI_PDMDLY_DLYM4L_Pos      (24U)
+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x04000000 */
+
+#define SAI_PDMDLY_DLYM4R_Pos      (28U)
+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x40000000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
+ */
+#define SPI_I2S_SUPPORT                       /*!< I2S support */
+
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos            (0U)
+#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
+#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
+#define SPI_CR1_CPOL_Pos            (1U)
+#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
+#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
+#define SPI_CR1_MSTR_Pos            (2U)
+#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
+#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos              (3U)
+#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
+#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
+#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
+#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos             (6U)
+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
+#define SPI_CR1_LSBFIRST_Pos        (7U)
+#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
+#define SPI_CR1_SSI_Pos             (8U)
+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
+#define SPI_CR1_SSM_Pos             (9U)
+#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
+#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
+#define SPI_CR1_RXONLY_Pos          (10U)
+#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
+#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
+#define SPI_CR1_CRCL_Pos            (11U)
+#define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
+#define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
+#define SPI_CR1_CRCNEXT_Pos         (12U)
+#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
+#define SPI_CR1_CRCEN_Pos           (13U)
+#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
+#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
+#define SPI_CR1_BIDIOE_Pos          (14U)
+#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos        (15U)
+#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos         (0U)
+#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos         (1U)
+#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos            (2U)
+#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
+#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
+#define SPI_CR2_NSSP_Pos            (3U)
+#define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
+#define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF_Pos             (4U)
+#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
+#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos           (5U)
+#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
+#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos          (6U)
+#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos           (7U)
+#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
+#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS_Pos              (8U)
+#define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
+#define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
+#define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
+#define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
+#define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
+#define SPI_CR2_FRXTH_Pos           (12U)
+#define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
+#define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX_Pos          (13U)
+#define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
+#define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX_Pos          (14U)
+#define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
+#define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos             (0U)
+#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
+#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos              (1U)
+#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
+#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos           (2U)
+#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
+#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
+#define SPI_SR_UDR_Pos              (3U)
+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos           (4U)
+#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
+#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos             (5U)
+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
+#define SPI_SR_OVR_Pos              (6U)
+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
+#define SPI_SR_BSY_Pos              (7U)
+#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
+#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
+#define SPI_SR_FRE_Pos              (8U)
+#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
+#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
+#define SPI_SR_FRLVL_Pos            (9U)
+#define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
+#define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
+#define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
+#define SPI_SR_FTLVL_Pos            (11U)
+#define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
+#define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
+#define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos               (0U)
+#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
+#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos       (0U)
+#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos        (0U)
+#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos        (0U)
+#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_CHLEN_Pos       (0U)
+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_Pos      (1U)
+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */
+#define SPI_I2SCFGR_CKPOL_Pos       (3U)
+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_Pos      (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */
+#define SPI_I2SCFGR_I2SE_Pos        (10U)
+#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos      (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
+#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */
+#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define SPI_I2SPR_I2SDIV_Pos        (0U)
+#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos           (8U)
+#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */
+#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos         (9U)
+#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2        (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000004 */
+
+#define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)
+#define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)   /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< User Flash Bank mode selection */
+
+/******************  Bit definition for SYSCFG_CFGR1 register ******************/
+#define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)
+#define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)    /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
+#define SYSCFG_CFGR1_ANASWVDD_Pos       (9U)
+#define SYSCFG_CFGR1_ANASWVDD_Msk       (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos)    /*!< 0x00000200 */
+#define SYSCFG_CFGR1_ANASWVDD           SYSCFG_CFGR1_ANASWVDD_Msk               /*!< GPIO analog switch control voltage selection */
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
+#define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
+#define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
+#define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)
+#define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)   /*!< 0x00100000 */
+#define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)
+#define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)   /*!< 0x00200000 */
+#define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)
+#define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)   /*!< 0x00400000 */
+#define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */
+
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */
+
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */
+
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x00000007 */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x00000070 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000700 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x00007000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */
+
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */
+
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */
+
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */
+
+/******************  Bit definition for SYSCFG_SCSR register  ****************/
+#define SYSCFG_SCSR_CCMER_Pos         (0U)
+#define SYSCFG_SCSR_CCMER_Msk         (0x1UL << SYSCFG_SCSR_CCMER_Pos)      /*!< 0x00000001 */
+#define SYSCFG_SCSR_CCMER             SYSCFG_SCSR_CCMER_Msk                 /*!< CCMSRAM  Erase Request */
+#define SYSCFG_SCSR_CCMBSY_Pos        (1U)
+#define SYSCFG_SCSR_CCMBSY_Msk        (0x1UL << SYSCFG_SCSR_CCMBSY_Pos)     /*!< 0x00000002 */
+#define SYSCFG_SCSR_CCMBSY            SYSCFG_SCSR_CCMBSY_Msk                /*!< CCMSRAM  Erase Ongoing */
+
+/******************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_CLL_Pos            (0U)
+#define SYSCFG_CFGR2_CLL_Msk            (0x1UL << SYSCFG_CFGR2_CLL_Pos)        /*!< 0x00000001 */
+#define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
+#define SYSCFG_CFGR2_SPL_Pos            (1U)
+#define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)        /*!< 0x00000002 */
+#define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
+#define SYSCFG_CFGR2_PVDL_Pos           (2U)
+#define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)       /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
+#define SYSCFG_CFGR2_ECCL_Pos           (3U)
+#define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)       /*!< 0x00000008 */
+#define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
+#define SYSCFG_CFGR2_SPF_Pos            (8U)
+#define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)        /*!< 0x00000100 */
+#define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
+
+/******************  Bit definition for SYSCFG_SWPR register  ****************/
+#define SYSCFG_SWPR_PAGE0_Pos          (0U)
+#define SYSCFG_SWPR_PAGE0_Msk          (0x1UL << SYSCFG_SWPR_PAGE0_Pos)       /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0              (SYSCFG_SWPR_PAGE0_Msk)                /*!< CCMSRAM  Write protection page 0 */
+#define SYSCFG_SWPR_PAGE1_Pos          (1U)
+#define SYSCFG_SWPR_PAGE1_Msk          (0x1UL << SYSCFG_SWPR_PAGE1_Pos)       /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1              (SYSCFG_SWPR_PAGE1_Msk)                /*!< CCMSRAM  Write protection page 1 */
+#define SYSCFG_SWPR_PAGE2_Pos          (2U)
+#define SYSCFG_SWPR_PAGE2_Msk          (0x1UL << SYSCFG_SWPR_PAGE2_Pos)       /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2              (SYSCFG_SWPR_PAGE2_Msk)                /*!< CCMSRAM  Write protection page 2 */
+#define SYSCFG_SWPR_PAGE3_Pos          (3U)
+#define SYSCFG_SWPR_PAGE3_Msk          (0x1UL << SYSCFG_SWPR_PAGE3_Pos)       /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3              (SYSCFG_SWPR_PAGE3_Msk)                /*!< CCMSRAM  Write protection page 3 */
+#define SYSCFG_SWPR_PAGE4_Pos          (4U)
+#define SYSCFG_SWPR_PAGE4_Msk          (0x1UL << SYSCFG_SWPR_PAGE4_Pos)       /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4              (SYSCFG_SWPR_PAGE4_Msk)                /*!< CCMSRAM  Write protection page 4 */
+#define SYSCFG_SWPR_PAGE5_Pos          (5U)
+#define SYSCFG_SWPR_PAGE5_Msk          (0x1UL << SYSCFG_SWPR_PAGE5_Pos)       /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5              (SYSCFG_SWPR_PAGE5_Msk)                /*!< CCMSRAM  Write protection page 5 */
+#define SYSCFG_SWPR_PAGE6_Pos          (6U)
+#define SYSCFG_SWPR_PAGE6_Msk          (0x1UL << SYSCFG_SWPR_PAGE6_Pos)       /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6              (SYSCFG_SWPR_PAGE6_Msk)                /*!< CCMSRAM  Write protection page 6 */
+#define SYSCFG_SWPR_PAGE7_Pos          (7U)
+#define SYSCFG_SWPR_PAGE7_Msk          (0x1UL << SYSCFG_SWPR_PAGE7_Pos)       /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7              (SYSCFG_SWPR_PAGE7_Msk)                /*!< CCMSRAM  Write protection page 7 */
+#define SYSCFG_SWPR_PAGE8_Pos          (8U)
+#define SYSCFG_SWPR_PAGE8_Msk          (0x1UL << SYSCFG_SWPR_PAGE8_Pos)       /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8              (SYSCFG_SWPR_PAGE8_Msk)                /*!< CCMSRAM  Write protection page 8 */
+#define SYSCFG_SWPR_PAGE9_Pos          (9U)
+#define SYSCFG_SWPR_PAGE9_Msk          (0x1UL << SYSCFG_SWPR_PAGE9_Pos)       /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9              (SYSCFG_SWPR_PAGE9_Msk)                /*!< CCMSRAM  Write protection page 9 */
+
+/******************  Bit definition for SYSCFG_SKR register  ****************/
+#define SYSCFG_SKR_KEY_Pos              (0U)
+#define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)         /*!< 0x000000FF */
+#define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!< CCMSRAM  write protection key for software erase  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)
+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+#define TIM_CR1_DITHEN_Pos      (12U)
+#define TIM_CR1_DITHEN_Msk      (0x1UL << TIM_CR1_DITHEN_Pos)                  /*!< 0x00001000 */
+#define TIM_CR1_DITHEN          TIM_CR1_DITHEN_Msk                             /*!<Dithering enable */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)
+#define TIM_CR2_MMS_Msk           (0x200007UL << TIM_CR2_MMS_Pos)              /*!< 0x02000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[3:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x000001UL << TIM_CR2_MMS_Pos)              /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x000002UL << TIM_CR2_MMS_Pos)              /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x000004UL << TIM_CR2_MMS_Pos)              /*!< 0x00000040 */
+#define TIM_CR2_MMS_3             (0x200000UL << TIM_CR2_MMS_Pos)              /*!< 0x02000000 */
+
+#define TIM_CR2_TI1S_Pos          (7U)
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS4N_Pos         (15U)
+#define TIM_CR2_OIS4N_Msk         (0x1UL << TIM_CR2_OIS4N_Pos)                 /*!< 0x00008000 */
+#define TIM_CR2_OIS4N             TIM_CR2_OIS4N_Msk                            /*!<Output Idle state 4 (OC4N output) */
+#define TIM_CR2_OIS5_Pos          (16U)
+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)
+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)
+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
+
+#define TIM_SMCR_OCCS_Pos         (3U)
+#define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
+#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos           (4U)
+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
+
+#define TIM_SMCR_MSM_Pos          (7U)
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+#define TIM_SMCR_SMSPE_Pos        (24U)
+#define TIM_SMCR_SMSPE_Msk        (0x1UL << TIM_SMCR_SMSPE_Pos)                /*!< 0x02000000 */
+#define TIM_SMCR_SMSPE            TIM_SMCR_SMSPE_Msk                           /*!<SMS preload enable */
+
+#define TIM_SMCR_SMSPS_Pos        (25U)
+#define TIM_SMCR_SMSPS_Msk        (0x1UL << TIM_SMCR_SMSPS_Pos)                /*!< 0x04000000 */
+#define TIM_SMCR_SMSPS            TIM_SMCR_SMSPS_Msk                           /*!<SMS preload source */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+#define TIM_DIER_IDXIE_Pos        (20U)
+#define TIM_DIER_IDXIE_Msk        (0x1UL << TIM_DIER_IDXIE_Pos)                /*!< 0x00100000 */
+#define TIM_DIER_IDXIE            TIM_DIER_IDXIE_Msk                           /*!<Encoder index interrupt enable */
+#define TIM_DIER_DIRIE_Pos        (21U)
+#define TIM_DIER_DIRIE_Msk        (0x1UL << TIM_DIER_DIRIE_Pos)                /*!< 0x00200000 */
+#define TIM_DIER_DIRIE            TIM_DIER_DIRIE_Msk                           /*!<Encoder direction change interrupt enable */
+#define TIM_DIER_IERRIE_Pos       (22U)
+#define TIM_DIER_IERRIE_Msk       (0x1UL << TIM_DIER_IERRIE_Pos)               /*!< 0x00400000 */
+#define TIM_DIER_IERRIE           TIM_DIER_IERRIE_Msk                          /*!<Encoder index error enable */
+#define TIM_DIER_TERRIE_Pos       (23U)
+#define TIM_DIER_TERRIE_Msk       (0x1UL << TIM_DIER_TERRIE_Pos)               /*!< 0x00800000 */
+#define TIM_DIER_TERRIE           TIM_DIER_TERRIE_Msk                          /*!<Encoder transition error enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)
+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos           (13U)
+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos          (16U)
+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)
+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+#define TIM_SR_IDXF_Pos           (20U)
+#define TIM_SR_IDXF_Msk           (0x1UL << TIM_SR_IDXF_Pos)                   /*!< 0x00100000 */
+#define TIM_SR_IDXF               TIM_SR_IDXF_Msk                              /*!<Encoder index interrupt flag */
+#define TIM_SR_DIRF_Pos           (21U)
+#define TIM_SR_DIRF_Msk           (0x1UL << TIM_SR_DIRF_Pos)                   /*!< 0x00200000 */
+#define TIM_SR_DIRF               TIM_SR_DIRF_Msk                              /*!<Encoder direction change interrupt flag */
+#define TIM_SR_IERRF_Pos          (22U)
+#define TIM_SR_IERRF_Msk          (0x1UL << TIM_SR_IERRF_Pos)                  /*!< 0x00400000 */
+#define TIM_SR_IERRF              TIM_SR_IERRF_Msk                             /*!<Encoder index error flag */
+#define TIM_SR_TERRF_Pos          (23U)
+#define TIM_SR_TERRF_Msk          (0x1UL << TIM_SR_TERRF_Pos)                  /*!< 0x00800000 */
+#define TIM_SR_TERRF              TIM_SR_TERRF_Msk                             /*!<Encoder transition error flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)
+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)
+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)
+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos      (2U)
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos      (2U)
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)
+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)
+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)
+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)
+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)
+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)
+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NE_Pos        (14U)
+#define TIM_CCER_CC4NE_Msk        (0x1UL << TIM_CCER_CC4NE_Pos)                /*!< 0x00004000 */
+#define TIM_CCER_CC4NE            TIM_CCER_CC4NE_Msk                           /*!<Capture/Compare 4 Complementary output enable */
+#define TIM_CCER_CC4NP_Pos        (15U)
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)
+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)
+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)
+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)
+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)
+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)
+#define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)
+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)
+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)
+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)
+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)
+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)
+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)
+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)
+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos         (20U)
+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)
+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos         (25U)
+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
+
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
+
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM1_AF1 register  *******************/
+#define TIM1_AF1_BKINE_Pos        (0U)
+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
+#define TIM1_AF1_BKCMP1E_Pos      (1U)
+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
+#define TIM1_AF1_BKCMP2E_Pos      (2U)
+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
+#define TIM1_AF1_BKCMP3E_Pos      (3U)
+#define TIM1_AF1_BKCMP3E_Msk      (0x1UL << TIM1_AF1_BKCMP3E_Pos)              /*!< 0x00000008 */
+#define TIM1_AF1_BKCMP3E          TIM1_AF1_BKCMP3E_Msk                         /*!<BRK COMP3 enable */
+#define TIM1_AF1_BKCMP4E_Pos      (4U)
+#define TIM1_AF1_BKCMP4E_Msk      (0x1UL << TIM1_AF1_BKCMP4E_Pos)              /*!< 0x00000010 */
+#define TIM1_AF1_BKCMP4E          TIM1_AF1_BKCMP4E_Msk                         /*!<BRK COMP4 enable */
+#define TIM1_AF1_BKINP_Pos        (9U)
+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
+#define TIM1_AF1_BKCMP1P_Pos      (10U)
+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
+#define TIM1_AF1_BKCMP2P_Pos      (11U)
+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
+#define TIM1_AF1_BKCMP3P_Pos      (12U)
+#define TIM1_AF1_BKCMP3P_Msk      (0x1UL << TIM1_AF1_BKCMP3P_Pos)              /*!< 0x00001000 */
+#define TIM1_AF1_BKCMP3P          TIM1_AF1_BKCMP3P_Msk                         /*!<BRK COMP3 input polarity */
+#define TIM1_AF1_BKCMP4P_Pos      (13U)
+#define TIM1_AF1_BKCMP4P_Msk      (0x1UL << TIM1_AF1_BKCMP4P_Pos)              /*!< 0x00002000 */
+#define TIM1_AF1_BKCMP4P          TIM1_AF1_BKCMP4P_Msk                         /*!<BRK COMP4 input polarity */
+#define TIM1_AF1_ETRSEL_Pos       (14U)
+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM1_AF2 register  *********************/
+#define TIM1_AF2_BK2INE_Pos        (0U)
+#define TIM1_AF2_BK2INE_Msk        (0x1UL << TIM1_AF2_BK2INE_Pos)                /*!< 0x00000001 */
+#define TIM1_AF2_BK2INE            TIM1_AF2_BK2INE_Msk                           /*!<BRK2 BKIN input enable */
+#define TIM1_AF2_BK2CMP1E_Pos      (1U)
+#define TIM1_AF2_BK2CMP1E_Msk      (0x1UL << TIM1_AF2_BK2CMP1E_Pos)              /*!< 0x00000002 */
+#define TIM1_AF2_BK2CMP1E          TIM1_AF2_BK2CMP1E_Msk                         /*!<BRK2 COMP1 enable */
+#define TIM1_AF2_BK2CMP2E_Pos      (2U)
+#define TIM1_AF2_BK2CMP2E_Msk      (0x1UL << TIM1_AF2_BK2CMP2E_Pos)              /*!< 0x00000004 */
+#define TIM1_AF2_BK2CMP2E          TIM1_AF2_BK2CMP2E_Msk                         /*!<BRK2 COMP2 enable */
+#define TIM1_AF2_BK2CMP3E_Pos      (3U)
+#define TIM1_AF2_BK2CMP3E_Msk      (0x1UL << TIM1_AF2_BK2CMP3E_Pos)              /*!< 0x00000008 */
+#define TIM1_AF2_BK2CMP3E          TIM1_AF2_BK2CMP3E_Msk                         /*!<BRK2 COMP3 enable */
+#define TIM1_AF2_BK2CMP4E_Pos      (4U)
+#define TIM1_AF2_BK2CMP4E_Msk      (0x1UL << TIM1_AF2_BK2CMP4E_Pos)              /*!< 0x00000010 */
+#define TIM1_AF2_BK2CMP4E          TIM1_AF2_BK2CMP4E_Msk                         /*!<BRK2 COMP4 enable */
+#define TIM1_AF2_BK2INP_Pos        (9U)
+#define TIM1_AF2_BK2INP_Msk        (0x1UL << TIM1_AF2_BK2INP_Pos)                /*!< 0x00000200 */
+#define TIM1_AF2_BK2INP            TIM1_AF2_BK2INP_Msk                           /*!<BRK2 BKIN input polarity */
+#define TIM1_AF2_BK2CMP1P_Pos      (10U)
+#define TIM1_AF2_BK2CMP1P_Msk      (0x1UL << TIM1_AF2_BK2CMP1P_Pos)              /*!< 0x00000400 */
+#define TIM1_AF2_BK2CMP1P          TIM1_AF2_BK2CMP1P_Msk                         /*!<BRK2 COMP1 input polarity */
+#define TIM1_AF2_BK2CMP2P_Pos      (11U)
+#define TIM1_AF2_BK2CMP2P_Msk      (0x1UL << TIM1_AF2_BK2CMP2P_Pos)              /*!< 0x00000800 */
+#define TIM1_AF2_BK2CMP2P          TIM1_AF2_BK2CMP2P_Msk                         /*!<BRK2 COMP2 input polarity */
+#define TIM1_AF2_BK2CMP3P_Pos      (12U)
+#define TIM1_AF2_BK2CMP3P_Msk      (0x1UL << TIM1_AF2_BK2CMP3P_Pos)              /*!< 0x00000400 */
+#define TIM1_AF2_BK2CMP3P          TIM1_AF2_BK2CMP3P_Msk                         /*!<BRK2 COMP3 input polarity */
+#define TIM1_AF2_BK2CMP4P_Pos      (13U)
+#define TIM1_AF2_BK2CMP4P_Msk      (0x1UL << TIM1_AF2_BK2CMP4P_Pos)              /*!< 0x00000800 */
+#define TIM1_AF2_BK2CMP4P          TIM1_AF2_BK2CMP4P_Msk                         /*!<BRK2 COMP4 input polarity */
+#define TIM1_AF2_OCRSEL_Pos        (16U)
+#define TIM1_AF2_OCRSEL_Msk        (0x7UL << TIM1_AF2_OCRSEL_Pos)                /*!< 0x00070000 */
+#define TIM1_AF2_OCRSEL            TIM1_AF2_OCRSEL_Msk                           /*!<BRK2 COMP2 input polarity */
+#define TIM1_AF2_OCRSEL_0         (0x1UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM1_AF2_OCRSEL_1         (0x2UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00020000 */
+#define TIM1_AF2_OCRSEL_2         (0x4UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00040000 */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM_OR_HSE32EN_Pos       (0U)
+#define TIM_OR_HSE32EN_Msk       (0x1UL << TIM_OR_HSE32EN_Pos)                  /*!< 0x00000001 */
+#define TIM_OR_HSE32EN           TIM_OR_HSE32EN_Msk                             /*!< HSE/32 clock enable */
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
+
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
+
+#define TIM_TISEL_TI3SEL_Pos      (16U)
+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
+
+#define TIM_TISEL_TI4SEL_Pos      (24U)
+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
+
+/*******************  Bit definition for TIM_DTR2 register  *********************/
+#define TIM_DTR2_DTGF_Pos      (0U)
+#define TIM_DTR2_DTGF_Msk      (0xFFUL << TIM_DTR2_DTGF_Pos)                /*!< 0x0000000F */
+#define TIM_DTR2_DTGF          TIM_DTR2_DTGF_Msk                            /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
+#define TIM_DTR2_DTGF_0        (0x01UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000001 */
+#define TIM_DTR2_DTGF_1        (0x02UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000002 */
+#define TIM_DTR2_DTGF_2        (0x04UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000004 */
+#define TIM_DTR2_DTGF_3        (0x08UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000008 */
+#define TIM_DTR2_DTGF_4        (0x10UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000010 */
+#define TIM_DTR2_DTGF_5        (0x20UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000020 */
+#define TIM_DTR2_DTGF_6        (0x40UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000040 */
+#define TIM_DTR2_DTGF_7        (0x80UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000080 */
+
+#define TIM_DTR2_DTAE_Pos      (16U)
+#define TIM_DTR2_DTAE_Msk      (0x1UL << TIM_DTR2_DTAE_Pos)                 /*!< 0x00004000 */
+#define TIM_DTR2_DTAE          TIM_DTR2_DTAE_Msk                            /*!<Deadtime asymmetric enable */
+#define TIM_DTR2_DTPE_Pos      (17U)
+#define TIM_DTR2_DTPE_Msk      (0x1UL << TIM_DTR2_DTPE_Pos)                 /*!< 0x00008000 */
+#define TIM_DTR2_DTPE          TIM_DTR2_DTPE_Msk                            /*!<Deadtime prelaod enable */
+
+/*******************  Bit definition for TIM_ECR register  *********************/
+#define TIM_ECR_IE_Pos       (0U)
+#define TIM_ECR_IE_Msk       (0x1UL << TIM_ECR_IE_Pos)                   /*!< 0x00000001 */
+#define TIM_ECR_IE           TIM_ECR_IE_Msk                              /*!<Index enable */
+
+#define TIM_ECR_IDIR_Pos      (1U)
+#define TIM_ECR_IDIR_Msk      (0x3UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000006 */
+#define TIM_ECR_IDIR          TIM_ECR_IDIR_Msk                            /*!<IDIR[1:0] bits (Index direction)*/
+#define TIM_ECR_IDIR_0        (0x01UL << TIM_ECR_IDIR_Pos)                /*!< 0x00000001 */
+#define TIM_ECR_IDIR_1        (0x02UL << TIM_ECR_IDIR_Pos)                /*!< 0x00000002 */
+
+#define TIM_ECR_FIDX_Pos      (5U)
+#define TIM_ECR_FIDX_Msk      (0x1UL << TIM_ECR_FIDX_Pos)                 /*!< 0x00000020 */
+#define TIM_ECR_FIDX          TIM_ECR_FIDX_Msk                            /*!<First index enable */
+
+#define TIM_ECR_IPOS_Pos      (6U)
+#define TIM_ECR_IPOS_Msk      (0x3UL << TIM_ECR_IPOS_Pos)                 /*!< 0x0000000C0 */
+#define TIM_ECR_IPOS          TIM_ECR_IPOS_Msk                            /*!<IPOS[1:0] bits (Index positioning)*/
+#define TIM_ECR_IPOS_0        (0x01UL << TIM_ECR_IPOS_Pos)                /*!< 0x00000001 */
+#define TIM_ECR_IPOS_1        (0x02UL << TIM_ECR_IPOS_Pos)                /*!< 0x00000002 */
+
+#define TIM_ECR_PW_Pos        (16U)
+#define TIM_ECR_PW_Msk        (0xFFUL << TIM_ECR_PW_Pos)                  /*!< 0x00FF0000 */
+#define TIM_ECR_PW            TIM_ECR_PW_Msk                              /*!<PW[7:0] bits (Pulse width)*/
+#define TIM_ECR_PW_0          (0x01UL << TIM_ECR_PW_Pos)                  /*!< 0x00010000 */
+#define TIM_ECR_PW_1          (0x02UL << TIM_ECR_PW_Pos)                  /*!< 0x00020000 */
+#define TIM_ECR_PW_2          (0x04UL << TIM_ECR_PW_Pos)                  /*!< 0x00040000 */
+#define TIM_ECR_PW_3          (0x08UL << TIM_ECR_PW_Pos)                  /*!< 0x00080000 */
+#define TIM_ECR_PW_4          (0x10UL << TIM_ECR_PW_Pos)                  /*!< 0x00100000 */
+#define TIM_ECR_PW_5          (0x20UL << TIM_ECR_PW_Pos)                  /*!< 0x00200000 */
+#define TIM_ECR_PW_6          (0x40UL << TIM_ECR_PW_Pos)                  /*!< 0x00400000 */
+#define TIM_ECR_PW_7          (0x80UL << TIM_ECR_PW_Pos)                  /*!< 0x00800000 */
+
+#define TIM_ECR_PWPRSC_Pos    (24U)
+#define TIM_ECR_PWPRSC_Msk    (0x7UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x07000000 */
+#define TIM_ECR_PWPRSC        TIM_ECR_PWPRSC_Msk                          /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
+#define TIM_ECR_PWPRSC_0      (0x01UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x01000000 */
+#define TIM_ECR_PWPRSC_1      (0x02UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x02000000 */
+#define TIM_ECR_PWPRSC_2      (0x04UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x04000000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)
+#define TIM_DMAR_DMAB_Msk         (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0xFFFFFFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                       /*!<DMA register for burst accesses */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)
+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)
+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)
+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)
+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)
+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)
+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)
+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)
+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)
+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)
+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)
+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)
+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)
+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)
+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)
+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)
+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)
+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)
+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)
+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)
+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)
+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x0200E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00008000 */
+#define LPTIM_CFGR_TRIGSEL_3        (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x02000000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)
+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)
+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)
+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)
+#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)
+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+#define LPTIM_CR_COUNTRST_Pos       (3U)
+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
+#define LPTIM_CR_RSTARE_Pos         (4U)
+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)
+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)
+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)
+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_OR register  *******************/
+#define LPTIM_OR_IN1_Pos             (0U)
+#define LPTIM_OR_IN1_Msk             (0xDUL << LPTIM_OR_IN1_Pos)                 /*!< 0x0000000D */
+#define LPTIM_OR_IN1                 LPTIM_OR_IN1_Msk                            /*!< IN1[2:0] bits (Remap selection) */
+#define LPTIM_OR_IN1_0               (0x1UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000001 */
+#define LPTIM_OR_IN1_1               (0x4UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000004 */
+#define LPTIM_OR_IN1_2               (0x8UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000008 */
+
+#define LPTIM_OR_IN2_Pos             (1U)
+#define LPTIM_OR_IN2_Msk             (0x19UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000032 */
+#define LPTIM_OR_IN2                 LPTIM_OR_IN2_Msk                            /*!< IN2[2:0] bits (Remap selection) */
+#define LPTIM_OR_IN2_0               (0x1UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000002 */
+#define LPTIM_OR_IN2_1               (0x8UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000010 */
+#define LPTIM_OR_IN2_2               (0x10UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000020 */
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos             (0U)
+#define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
+#define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
+#define USART_CR1_UESM_Pos           (1U)
+#define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
+#define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos             (2U)
+#define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
+#define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
+#define USART_CR1_TE_Pos             (3U)
+#define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
+#define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos         (4U)
+#define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
+#define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos         (5U)
+#define USART_CR1_RXNEIE_Msk         (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
+#define USART_CR1_RXNEIE             USART_CR1_RXNEIE_Msk                      /*!< RXNE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
+#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk                      /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE     USART_CR1_RXNEIE_Msk                      /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
+#define USART_CR1_TCIE_Pos           (6U)
+#define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos          (7U)
+#define USART_CR1_TXEIE_Msk          (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
+#define USART_CR1_TXEIE              USART_CR1_TXEIE_Msk                       /*!< TXE Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos  USART_CR1_TXEIE_Pos
+#define USART_CR1_TXEIE_TXFNFIE_Msk  USART_CR1_TXEIE_Msk                       /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE      USART_CR1_TXEIE_Msk                       /*!< TXE and TX FIFO Not Full Interrupt Enable */
+#define USART_CR1_PEIE_Pos           (8U)
+#define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
+#define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos             (9U)
+#define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
+#define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
+#define USART_CR1_PCE_Pos            (10U)
+#define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
+#define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos           (11U)
+#define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
+#define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos              (12U)
+#define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
+#define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
+#define USART_CR1_M0_Pos             (12U)
+#define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
+#define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos            (13U)
+#define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
+#define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos           (14U)
+#define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
+#define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos          (15U)
+#define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
+#define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos           (16U)
+#define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
+#define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
+#define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
+#define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
+#define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
+#define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos           (21U)
+#define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
+#define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
+#define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
+#define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
+#define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
+#define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos          (26U)
+#define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
+#define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos          (27U)
+#define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
+#define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos             (28U)
+#define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
+#define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos         (29U)
+#define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */
+#define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos         (30U)
+#define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */
+#define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
+#define USART_CR1_RXFFIE_Pos         (31U)
+#define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */
+#define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_SLVEN_Pos          (0U)
+#define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */
+#define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
+#define USART_CR2_DIS_NSS_Pos        (3U)
+#define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< Slave Select (NSS) pin management */
+#define USART_CR2_ADDM7_Pos          (4U)
+#define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
+#define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos           (5U)
+#define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
+#define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos          (6U)
+#define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
+#define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos           (8U)
+#define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
+#define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos           (9U)
+#define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
+#define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos           (10U)
+#define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
+#define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos          (11U)
+#define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
+#define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
+#define USART_CR2_STOP_Pos           (12U)
+#define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
+#define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
+#define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos          (14U)
+#define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
+#define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos           (15U)
+#define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
+#define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos          (16U)
+#define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
+#define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos          (17U)
+#define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
+#define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos        (18U)
+#define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
+#define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos       (19U)
+#define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos          (20U)
+#define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
+#define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos        (21U)
+#define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
+#define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos          (23U)
+#define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
+#define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos            (24U)
+#define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
+#define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos            (0U)
+#define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
+#define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos           (1U)
+#define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
+#define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos           (2U)
+#define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
+#define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos          (3U)
+#define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
+#define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos           (4U)
+#define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
+#define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos           (5U)
+#define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
+#define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos           (6U)
+#define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
+#define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos           (7U)
+#define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
+#define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos           (8U)
+#define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
+#define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos           (9U)
+#define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
+#define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos          (10U)
+#define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
+#define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos         (11U)
+#define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
+#define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos         (12U)
+#define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
+#define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos           (13U)
+#define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
+#define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos            (14U)
+#define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
+#define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos            (15U)
+#define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
+#define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos        (17U)
+#define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos            (20U)
+#define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
+#define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
+#define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos          (22U)
+#define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
+#define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TXFTIE_Pos         (23U)
+#define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */
+#define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
+#define USART_CR3_TCBGTIE_Pos        (24U)
+#define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
+#define USART_CR3_RXFTCFG_Pos        (25U)
+#define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
+#define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos         (28U)
+#define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */
+#define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
+#define USART_CR3_TXFTCFG_Pos        (29U)
+#define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
+#define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_LPUART_Pos         (0U)
+#define USART_BRR_LPUART_Msk         (0xFFFFFUL << USART_BRR_LPUART_Pos)       /*!< 0x000FFFFF */
+#define USART_BRR_LPUART             USART_BRR_LPUART_Msk                      /*!< LPUART Baud rate register [19:0] */
+#define USART_BRR_BRR_Pos            (0U)
+#define USART_BRR_BRR_Msk            (0xFFFFUL << USART_BRR_BRR_Pos)           /*!< 0x0000FFFF */
+#define USART_BRR_BRR                USART_BRR_BRR_Msk                         /*!< USART Baud rate register [15:0] */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos           (0U)
+#define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
+#define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos            (8U)
+#define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
+#define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos           (0U)
+#define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos          (24U)
+#define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
+#define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos          (0U)
+#define USART_RQR_ABRRQ_Msk          (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
+#define USART_RQR_ABRRQ              USART_RQR_ABRRQ_Msk                       /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos          (1U)
+#define USART_RQR_SBKRQ_Msk          (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
+#define USART_RQR_SBKRQ              USART_RQR_SBKRQ_Msk                       /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos           (2U)
+#define USART_RQR_MMRQ_Msk           (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
+#define USART_RQR_MMRQ               USART_RQR_MMRQ_Msk                        /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos          (3U)
+#define USART_RQR_RXFRQ_Msk          (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
+#define USART_RQR_RXFRQ              USART_RQR_RXFRQ_Msk                       /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos          (4U)
+#define USART_RQR_TXFRQ_Msk          (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
+#define USART_RQR_TXFRQ              USART_RQR_TXFRQ_Msk                       /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos             (0U)
+#define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
+#define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
+#define USART_ISR_FE_Pos             (1U)
+#define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
+#define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
+#define USART_ISR_NE_Pos             (2U)
+#define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
+#define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos            (3U)
+#define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
+#define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos           (4U)
+#define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
+#define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos           (5U)
+#define USART_ISR_RXNE_Msk           (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
+#define USART_ISR_RXNE               USART_ISR_RXNE_Msk                        /*!< Read Data Register Not Empty */
+#define USART_ISR_RXNE_RXFNE_Pos     USART_ISR_RXNE_Pos
+#define USART_ISR_RXNE_RXFNE_Msk     USART_ISR_RXNE_Msk                        /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_Msk                        /*!< Read Data Register or RX FIFO Not Empty */
+#define USART_ISR_TC_Pos             (6U)
+#define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
+#define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos            (7U)
+#define USART_ISR_TXE_Msk            (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
+#define USART_ISR_TXE                USART_ISR_TXE_Msk                         /*!< Transmit Data Register Empty */
+#define USART_ISR_TXE_TXFNF_Pos      USART_ISR_TXE_Pos
+#define USART_ISR_TXE_TXFNF_Msk      USART_ISR_TXE_Msk                       /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF          USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
+#define USART_ISR_LBDF_Pos           (8U)
+#define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
+#define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos          (9U)
+#define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
+#define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos            (10U)
+#define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
+#define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
+#define USART_ISR_RTOF_Pos           (11U)
+#define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
+#define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos           (12U)
+#define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
+#define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos            (13U)
+#define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */
+#define USART_ISR_UDR                USART_ISR_UDR_Msk                         /*!< SPI slave underrun error flag */
+#define USART_ISR_ABRE_Pos           (14U)
+#define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
+#define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos           (15U)
+#define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
+#define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos           (16U)
+#define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
+#define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
+#define USART_ISR_CMF_Pos            (17U)
+#define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
+#define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos           (18U)
+#define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
+#define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos            (19U)
+#define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
+#define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos            (20U)
+#define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
+#define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos          (21U)
+#define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
+#define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos          (22U)
+#define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
+#define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos           (23U)
+#define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */
+#define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty */
+#define USART_ISR_RXFF_Pos           (24U)
+#define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */
+#define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full */
+#define USART_ISR_TCBGT_Pos          (25U)
+#define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
+#define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time completion */
+#define USART_ISR_RXFT_Pos           (26U)
+#define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */
+#define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO threshold flag */
+#define USART_ISR_TXFT_Pos           (27U)
+#define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */
+#define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO threshold flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos           (0U)
+#define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
+#define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos           (1U)
+#define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
+#define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos           (2U)
+#define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
+#define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos          (3U)
+#define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
+#define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos         (4U)
+#define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
+#define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos         (5U)
+#define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */
+#define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO empty Clear flag */
+#define USART_ICR_TCCF_Pos           (6U)
+#define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
+#define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos        (7U)
+#define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF_Pos          (8U)
+#define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
+#define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos          (9U)
+#define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
+#define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos          (11U)
+#define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
+#define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos          (12U)
+#define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
+#define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos          (13U)
+#define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */
+#define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
+#define USART_ICR_CMCF_Pos           (17U)
+#define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
+#define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos           (20U)
+#define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
+#define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos            (0U)
+#define USART_RDR_RDR_Msk            (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
+#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos            (0U)
+#define USART_TDR_TDR_Msk            (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
+#define USART_TDR_TDR                USART_TDR_TDR_Msk                         /*!< TDR[8:0] bits (Transmit Data value) */
+
+/*******************  Bit definition for USART_PRESC register  ****************/
+#define USART_PRESC_PRESCALER_Pos    (0U)
+#define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 VREFBUF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos    (0U)
+#define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos     (1U)
+#define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
+#define VREFBUF_CSR_VRR_Pos     (3U)
+#define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
+#define VREFBUF_CSR_VRS_Pos     (4U)
+#define VREFBUF_CSR_VRS_Msk     (0x3UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000030 */
+#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<VRS[5:0] bits (Voltage reference scale) */
+#define VREFBUF_CSR_VRS_0       (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000010 */
+#define VREFBUF_CSR_VRS_1       (0x2UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000020 */
+
+/*******************  Bit definition for VREFBUF_CCR register  ******************/
+#define VREFBUF_CCR_TRIM_Pos    (0U)
+#define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         USB Device FS Endpoint registers                   */
+/*                                                                            */
+/******************************************************************************/
+#define USB_EP0R                             USB_BASE                    /*!< endpoint 0 register address */
+#define USB_EP1R                             (USB_BASE + 0x0x00000004)   /*!< endpoint 1 register address */
+#define USB_EP2R                             (USB_BASE + 0x0x00000008)   /*!< endpoint 2 register address */
+#define USB_EP3R                             (USB_BASE + 0x0x0000000C)   /*!< endpoint 3 register address */
+#define USB_EP4R                             (USB_BASE + 0x0x00000010)   /*!< endpoint 4 register address */
+#define USB_EP5R                             (USB_BASE + 0x0x00000014)   /*!< endpoint 5 register address */
+#define USB_EP6R                             (USB_BASE + 0x0x00000018)   /*!< endpoint 6 register address */
+#define USB_EP7R                             (USB_BASE + 0x0x0000001C)   /*!< endpoint 7 register address */
+
+/* bit positions */
+#define USB_EP_CTR_RX                            ((uint16_t)0x8000U)           /*!<  EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX                           ((uint16_t)0x4000U)           /*!<  EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT                            ((uint16_t)0x3000U)           /*!<  EndPoint RX STATus bit field */
+#define USB_EP_SETUP                             ((uint16_t)0x0800U)           /*!<  EndPoint SETUP */
+#define USB_EP_T_FIELD                           ((uint16_t)0x0600U)           /*!<  EndPoint TYPE */
+#define USB_EP_KIND                              ((uint16_t)0x0100U)           /*!<  EndPoint KIND */
+#define USB_EP_CTR_TX                            ((uint16_t)0x0080U)           /*!<  EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX                           ((uint16_t)0x0040U)           /*!<  EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT                            ((uint16_t)0x0030U)           /*!<  EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD                         ((uint16_t)0x000FU)           /*!<  EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK                         ((uint16_t)0x0600U)           /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK                              ((uint16_t)0x0000U)           /*!< EndPoint BULK */
+#define USB_EP_CONTROL                           ((uint16_t)0x0200U)           /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS                       ((uint16_t)0x0400U)           /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT                         ((uint16_t)0x0600U)           /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL                          ((uint16_t)0x0010U)           /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK                            ((uint16_t)0x0020U)           /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID                          ((uint16_t)0x0030U)           /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1                           ((uint16_t)0x0010U)           /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2                           ((uint16_t)0x0020U)           /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
+                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL                          ((uint16_t)0x1000U)           /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK                            ((uint16_t)0x2000U)           /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID                          ((uint16_t)0x3000U)           /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1                           ((uint16_t)0x1000U)           /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2                           ((uint16_t)0x2000U)           /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/*                                                                            */
+/*                         USB Device FS General registers                    */
+/*                                                                            */
+/******************************************************************************/
+#define USB_CNTR                             (USB_BASE + 0x00000040U)     /*!< Control register */
+#define USB_ISTR                             (USB_BASE + 0x00000044U)     /*!< Interrupt status register */
+#define USB_FNR                              (USB_BASE + 0x00000048U)     /*!< Frame number register */
+#define USB_DADDR                            (USB_BASE + 0x0000004CU)     /*!< Device address register */
+#define USB_BTABLE                           (USB_BASE + 0x00000050U)     /*!< Buffer Table address register */
+#define USB_LPMCSR                           (USB_BASE + 0x00000054U)     /*!< LPM Control and Status register */
+#define USB_BCDR                             (USB_BASE + 0x00000058U)     /*!< Battery Charging detector register*/
+
+/******************  Bits definition for USB_CNTR register  *******************/
+#define USB_CNTR_CTRM                            ((uint16_t)0x8000U)           /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM                         ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM                            ((uint16_t)0x2000U)           /*!< ERRor Mask */
+#define USB_CNTR_WKUPM                           ((uint16_t)0x1000U)           /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM                           ((uint16_t)0x0800U)           /*!< SUSPend Mask */
+#define USB_CNTR_RESETM                          ((uint16_t)0x0400U)           /*!< RESET Mask   */
+#define USB_CNTR_SOFM                            ((uint16_t)0x0200U)           /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM                           ((uint16_t)0x0100U)           /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM                          ((uint16_t)0x0080U)           /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME                        ((uint16_t)0x0020U)           /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME                          ((uint16_t)0x0010U)           /*!< RESUME request */
+#define USB_CNTR_FSUSP                           ((uint16_t)0x0008U)           /*!< Force SUSPend */
+#define USB_CNTR_LPMODE                          ((uint16_t)0x0004U)           /*!< Low-power MODE */
+#define USB_CNTR_PDWN                            ((uint16_t)0x0002U)           /*!< Power DoWN */
+#define USB_CNTR_FRES                            ((uint16_t)0x0001U)           /*!< Force USB RESet */
+
+/******************  Bits definition for USB_ISTR register  *******************/
+#define USB_ISTR_EP_ID                           ((uint16_t)0x000FU)           /*!< EndPoint IDentifier (read-only bit)  */
+#define USB_ISTR_DIR                             ((uint16_t)0x0010U)           /*!< DIRection of transaction (read-only bit)  */
+#define USB_ISTR_L1REQ                           ((uint16_t)0x0080U)           /*!< LPM L1 state request  */
+#define USB_ISTR_ESOF                            ((uint16_t)0x0100U)           /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_SOF                             ((uint16_t)0x0200U)           /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_RESET                           ((uint16_t)0x0400U)           /*!< RESET (clear-only bit) */
+#define USB_ISTR_SUSP                            ((uint16_t)0x0800U)           /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_WKUP                            ((uint16_t)0x1000U)           /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_ERR                             ((uint16_t)0x2000U)           /*!< ERRor (clear-only bit) */
+#define USB_ISTR_PMAOVR                          ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_CTR                             ((uint16_t)0x8000U)           /*!< Correct TRansfer (clear-only bit) */
+
+#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
+#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
+#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
+#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
+#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
+#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
+#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
+
+/******************  Bits definition for USB_FNR register  ********************/
+#define USB_FNR_FN                               ((uint16_t)0x07FFU)           /*!< Frame Number */
+#define USB_FNR_LSOF                             ((uint16_t)0x1800U)           /*!< Lost SOF */
+#define USB_FNR_LCK                              ((uint16_t)0x2000U)           /*!< LoCKed */
+#define USB_FNR_RXDM                             ((uint16_t)0x4000U)           /*!< status of D- data line */
+#define USB_FNR_RXDP                             ((uint16_t)0x8000U)           /*!< status of D+ data line */
+
+/******************  Bits definition for USB_DADDR register    ****************/
+#define USB_DADDR_ADD                            ((uint8_t)0x7FU)              /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0                           ((uint8_t)0x01U)              /*!< Bit 0 */
+#define USB_DADDR_ADD1                           ((uint8_t)0x02U)              /*!< Bit 1 */
+#define USB_DADDR_ADD2                           ((uint8_t)0x04U)              /*!< Bit 2 */
+#define USB_DADDR_ADD3                           ((uint8_t)0x08U)              /*!< Bit 3 */
+#define USB_DADDR_ADD4                           ((uint8_t)0x10U)              /*!< Bit 4 */
+#define USB_DADDR_ADD5                           ((uint8_t)0x20U)              /*!< Bit 5 */
+#define USB_DADDR_ADD6                           ((uint8_t)0x40U)              /*!< Bit 6 */
+
+#define USB_DADDR_EF                             ((uint8_t)0x80U)              /*!< Enable Function */
+
+/******************  Bit definition for USB_BTABLE register  ******************/
+#define USB_BTABLE_BTABLE                        ((uint16_t)0xFFF8U)           /*!< Buffer Table */
+
+/******************  Bits definition for USB_BCDR register  *******************/
+#define USB_BCDR_BCDEN                           ((uint16_t)0x0001U)           /*!< Battery charging detector (BCD) enable */
+#define USB_BCDR_DCDEN                           ((uint16_t)0x0002U)           /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_PDEN                            ((uint16_t)0x0004U)           /*!< Primary detection (PD) mode enable */
+#define USB_BCDR_SDEN                            ((uint16_t)0x0008U)           /*!< Secondary detection (SD) mode enable */
+#define USB_BCDR_DCDET                           ((uint16_t)0x0010U)           /*!< Data contact detection (DCD) status */
+#define USB_BCDR_PDET                            ((uint16_t)0x0020U)           /*!< Primary detection (PD) status */
+#define USB_BCDR_SDET                            ((uint16_t)0x0040U)           /*!< Secondary detection (SD) status */
+#define USB_BCDR_PS2DET                          ((uint16_t)0x0080U)           /*!< PS2 port or proprietary charger detected */
+#define USB_BCDR_DPPU                            ((uint16_t)0x8000U)           /*!< DP Pull-up Enable */
+
+/*******************  Bit definition for LPMCSR register  *********************/
+#define USB_LPMCSR_LMPEN                         ((uint16_t)0x0001U)           /*!< LPM support enable  */
+#define USB_LPMCSR_LPMACK                        ((uint16_t)0x0002U)           /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_REMWAKE                       ((uint16_t)0x0008U)           /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_BESL                          ((uint16_t)0x00F0U)           /*!< BESL value received with last ACKed LPM Token  */
+
+/*!< Buffer descriptor table */
+/*****************  Bit definition for USB_ADDR0_TX register  *****************/
+#define USB_ADDR0_TX_ADDR0_TX_Pos                (1U)
+#define USB_ADDR0_TX_ADDR0_TX_Msk                (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR0_TX_ADDR0_TX                    USB_ADDR0_TX_ADDR0_TX_Msk     /*!< Transmission Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_TX register  *****************/
+#define USB_ADDR1_TX_ADDR1_TX_Pos                (1U)
+#define USB_ADDR1_TX_ADDR1_TX_Msk                (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR1_TX_ADDR1_TX                    USB_ADDR1_TX_ADDR1_TX_Msk     /*!< Transmission Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_TX register  *****************/
+#define USB_ADDR2_TX_ADDR2_TX_Pos                (1U)
+#define USB_ADDR2_TX_ADDR2_TX_Msk                (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR2_TX_ADDR2_TX                    USB_ADDR2_TX_ADDR2_TX_Msk     /*!< Transmission Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_TX register  *****************/
+#define USB_ADDR3_TX_ADDR3_TX_Pos                (1U)
+#define USB_ADDR3_TX_ADDR3_TX_Msk                (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR3_TX_ADDR3_TX                    USB_ADDR3_TX_ADDR3_TX_Msk     /*!< Transmission Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_TX register  *****************/
+#define USB_ADDR4_TX_ADDR4_TX_Pos                (1U)
+#define USB_ADDR4_TX_ADDR4_TX_Msk                (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR4_TX_ADDR4_TX                    USB_ADDR4_TX_ADDR4_TX_Msk     /*!< Transmission Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_TX register  *****************/
+#define USB_ADDR5_TX_ADDR5_TX_Pos                (1U)
+#define USB_ADDR5_TX_ADDR5_TX_Msk                (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR5_TX_ADDR5_TX                    USB_ADDR5_TX_ADDR5_TX_Msk     /*!< Transmission Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_TX register  *****************/
+#define USB_ADDR6_TX_ADDR6_TX_Pos                (1U)
+#define USB_ADDR6_TX_ADDR6_TX_Msk                (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR6_TX_ADDR6_TX                    USB_ADDR6_TX_ADDR6_TX_Msk     /*!< Transmission Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_TX register  *****************/
+#define USB_ADDR7_TX_ADDR7_TX_Pos                (1U)
+#define USB_ADDR7_TX_ADDR7_TX_Msk                (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR7_TX_ADDR7_TX                    USB_ADDR7_TX_ADDR7_TX_Msk     /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_TX register  ****************/
+#define USB_COUNT0_TX_COUNT0_TX_Pos              (0U)
+#define USB_COUNT0_TX_COUNT0_TX_Msk              (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
+#define USB_COUNT0_TX_COUNT0_TX                  USB_COUNT0_TX_COUNT0_TX_Msk   /*!< Transmission Byte Count 0 */
+
+/*****************  Bit definition for USB_COUNT1_TX register  ****************/
+#define USB_COUNT1_TX_COUNT1_TX_Pos              (0U)
+#define USB_COUNT1_TX_COUNT1_TX_Msk              (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
+#define USB_COUNT1_TX_COUNT1_TX                  USB_COUNT1_TX_COUNT1_TX_Msk   /*!< Transmission Byte Count 1 */
+
+/*****************  Bit definition for USB_COUNT2_TX register  ****************/
+#define USB_COUNT2_TX_COUNT2_TX_Pos              (0U)
+#define USB_COUNT2_TX_COUNT2_TX_Msk              (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
+#define USB_COUNT2_TX_COUNT2_TX                  USB_COUNT2_TX_COUNT2_TX_Msk   /*!< Transmission Byte Count 2 */
+
+/*****************  Bit definition for USB_COUNT3_TX register  ****************/
+#define USB_COUNT3_TX_COUNT3_TX_Pos              (0U)
+#define USB_COUNT3_TX_COUNT3_TX_Msk              (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
+#define USB_COUNT3_TX_COUNT3_TX                  USB_COUNT3_TX_COUNT3_TX_Msk   /*!< Transmission Byte Count 3 */
+
+/*****************  Bit definition for USB_COUNT4_TX register  ****************/
+#define USB_COUNT4_TX_COUNT4_TX_Pos              (0U)
+#define USB_COUNT4_TX_COUNT4_TX_Msk              (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
+#define USB_COUNT4_TX_COUNT4_TX                  USB_COUNT4_TX_COUNT4_TX_Msk   /*!< Transmission Byte Count 4 */
+
+/*****************  Bit definition for USB_COUNT5_TX register  ****************/
+#define USB_COUNT5_TX_COUNT5_TX_Pos              (0U)
+#define USB_COUNT5_TX_COUNT5_TX_Msk              (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
+#define USB_COUNT5_TX_COUNT5_TX                  USB_COUNT5_TX_COUNT5_TX_Msk   /*!< Transmission Byte Count 5 */
+
+/*****************  Bit definition for USB_COUNT6_TX register  ****************/
+#define USB_COUNT6_TX_COUNT6_TX_Pos              (0U)
+#define USB_COUNT6_TX_COUNT6_TX_Msk              (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
+#define USB_COUNT6_TX_COUNT6_TX                  USB_COUNT6_TX_COUNT6_TX_Msk   /*!< Transmission Byte Count 6 */
+
+/*****************  Bit definition for USB_COUNT7_TX register  ****************/
+#define USB_COUNT7_TX_COUNT7_TX_Pos              (0U)
+#define USB_COUNT7_TX_COUNT7_TX_Msk              (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
+#define USB_COUNT7_TX_COUNT7_TX                  USB_COUNT7_TX_COUNT7_TX_Msk   /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 0 (low) */
+
+/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 0 (high) */
+
+/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 1 (low) */
+
+/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 1 (high) */
+
+/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 2 (low) */
+
+/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 2 (high) */
+
+/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 3 (low) */
+
+/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 3 (high) */
+
+/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 4 (low) */
+
+/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 4 (high) */
+
+/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 5 (low) */
+
+/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 5 (high) */
+
+/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 6 (low) */
+
+/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 6 (high) */
+
+/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 7 (low) */
+
+/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_ADDR0_RX register  *****************/
+#define USB_ADDR0_RX_ADDR0_RX_Pos                (1U)
+#define USB_ADDR0_RX_ADDR0_RX_Msk                (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR0_RX_ADDR0_RX                    USB_ADDR0_RX_ADDR0_RX_Msk     /*!< Reception Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_RX register  *****************/
+#define USB_ADDR1_RX_ADDR1_RX_Pos                (1U)
+#define USB_ADDR1_RX_ADDR1_RX_Msk                (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR1_RX_ADDR1_RX                    USB_ADDR1_RX_ADDR1_RX_Msk     /*!< Reception Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_RX register  *****************/
+#define USB_ADDR2_RX_ADDR2_RX_Pos                (1U)
+#define USB_ADDR2_RX_ADDR2_RX_Msk                (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR2_RX_ADDR2_RX                    USB_ADDR2_RX_ADDR2_RX_Msk     /*!< Reception Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_RX register  *****************/
+#define USB_ADDR3_RX_ADDR3_RX_Pos                (1U)
+#define USB_ADDR3_RX_ADDR3_RX_Msk                (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR3_RX_ADDR3_RX                    USB_ADDR3_RX_ADDR3_RX_Msk     /*!< Reception Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_RX register  *****************/
+#define USB_ADDR4_RX_ADDR4_RX_Pos                (1U)
+#define USB_ADDR4_RX_ADDR4_RX_Msk                (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR4_RX_ADDR4_RX                    USB_ADDR4_RX_ADDR4_RX_Msk     /*!< Reception Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_RX register  *****************/
+#define USB_ADDR5_RX_ADDR5_RX_Pos                (1U)
+#define USB_ADDR5_RX_ADDR5_RX_Msk                (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR5_RX_ADDR5_RX                    USB_ADDR5_RX_ADDR5_RX_Msk     /*!< Reception Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_RX register  *****************/
+#define USB_ADDR6_RX_ADDR6_RX_Pos                (1U)
+#define USB_ADDR6_RX_ADDR6_RX_Msk                (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR6_RX_ADDR6_RX                    USB_ADDR6_RX_ADDR6_RX_Msk     /*!< Reception Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_RX register  *****************/
+#define USB_ADDR7_RX_ADDR7_RX_Pos                (1U)
+#define USB_ADDR7_RX_ADDR7_RX_Msk                (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
+#define USB_ADDR7_RX_ADDR7_RX                    USB_ADDR7_RX_ADDR7_RX_Msk     /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_RX register  ****************/
+#define USB_COUNT0_RX_COUNT0_RX_Pos              (0U)
+#define USB_COUNT0_RX_COUNT0_RX_Msk              (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
+#define USB_COUNT0_RX_COUNT0_RX                  USB_COUNT0_RX_COUNT0_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK_Pos              (10U)
+#define USB_COUNT0_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
+#define USB_COUNT0_RX_NUM_BLOCK                  USB_COUNT0_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
+#define USB_COUNT0_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
+#define USB_COUNT0_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
+#define USB_COUNT0_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
+#define USB_COUNT0_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
+
+#define USB_COUNT0_RX_BLSIZE_Pos                 (15U)
+#define USB_COUNT0_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
+#define USB_COUNT0_RX_BLSIZE                     USB_COUNT0_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT1_RX register  ****************/
+#define USB_COUNT1_RX_COUNT1_RX_Pos              (0U)
+#define USB_COUNT1_RX_COUNT1_RX_Msk              (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
+#define USB_COUNT1_RX_COUNT1_RX                  USB_COUNT1_RX_COUNT1_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK_Pos              (10U)
+#define USB_COUNT1_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
+#define USB_COUNT1_RX_NUM_BLOCK                  USB_COUNT1_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
+#define USB_COUNT1_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
+#define USB_COUNT1_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
+#define USB_COUNT1_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
+#define USB_COUNT1_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
+
+#define USB_COUNT1_RX_BLSIZE_Pos                 (15U)
+#define USB_COUNT1_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
+#define USB_COUNT1_RX_BLSIZE                     USB_COUNT1_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT2_RX register  ****************/
+#define USB_COUNT2_RX_COUNT2_RX_Pos              (0U)
+#define USB_COUNT2_RX_COUNT2_RX_Msk              (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
+#define USB_COUNT2_RX_COUNT2_RX                  USB_COUNT2_RX_COUNT2_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK_Pos              (10U)
+#define USB_COUNT2_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
+#define USB_COUNT2_RX_NUM_BLOCK                  USB_COUNT2_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
+#define USB_COUNT2_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
+#define USB_COUNT2_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
+#define USB_COUNT2_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
+#define USB_COUNT2_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
+
+#define USB_COUNT2_RX_BLSIZE_Pos                 (15U)
+#define USB_COUNT2_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
+#define USB_COUNT2_RX_BLSIZE                     USB_COUNT2_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT3_RX register  ****************/
+#define USB_COUNT3_RX_COUNT3_RX_Pos              (0U)
+#define USB_COUNT3_RX_COUNT3_RX_Msk              (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
+#define USB_COUNT3_RX_COUNT3_RX                  USB_COUNT3_RX_COUNT3_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK_Pos              (10U)
+#define USB_COUNT3_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
+#define USB_COUNT3_RX_NUM_BLOCK                  USB_COUNT3_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
+#define USB_COUNT3_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
+#define USB_COUNT3_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
+#define USB_COUNT3_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
+#define USB_COUNT3_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
+
+#define USB_COUNT3_RX_BLSIZE_Pos                 (15U)
+#define USB_COUNT3_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
+#define USB_COUNT3_RX_BLSIZE                     USB_COUNT3_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT4_RX register  ****************/
+#define USB_COUNT4_RX_COUNT4_RX_Pos              (0U)
+#define USB_COUNT4_RX_COUNT4_RX_Msk              (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
+#define USB_COUNT4_RX_COUNT4_RX                  USB_COUNT4_RX_COUNT4_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK_Pos              (10U)
+#define USB_COUNT4_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
+#define USB_COUNT4_RX_NUM_BLOCK                  USB_COUNT4_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
+#define USB_COUNT4_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
+#define USB_COUNT4_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
+#define USB_COUNT4_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
+#define USB_COUNT4_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
+
+#define USB_COUNT4_RX_BLSIZE_Pos                 (15U)
+#define USB_COUNT4_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
+#define USB_COUNT4_RX_BLSIZE                     USB_COUNT4_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT5_RX register  ****************/
+#define USB_COUNT5_RX_COUNT5_RX_Pos              (0U)
+#define USB_COUNT5_RX_COUNT5_RX_Msk              (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
+#define USB_COUNT5_RX_COUNT5_RX                  USB_COUNT5_RX_COUNT5_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK_Pos              (10U)
+#define USB_COUNT5_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
+#define USB_COUNT5_RX_NUM_BLOCK                  USB_COUNT5_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
+#define USB_COUNT5_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
+#define USB_COUNT5_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
+#define USB_COUNT5_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
+#define USB_COUNT5_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
+
+#define USB_COUNT5_RX_BLSIZE_Pos                 (15U)
+#define USB_COUNT5_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
+#define USB_COUNT5_RX_BLSIZE                     USB_COUNT5_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT6_RX register  ****************/
+#define USB_COUNT6_RX_COUNT6_RX_Pos              (0U)
+#define USB_COUNT6_RX_COUNT6_RX_Msk              (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
+#define USB_COUNT6_RX_COUNT6_RX                  USB_COUNT6_RX_COUNT6_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK_Pos              (10U)
+#define USB_COUNT6_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
+#define USB_COUNT6_RX_NUM_BLOCK                  USB_COUNT6_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
+#define USB_COUNT6_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
+#define USB_COUNT6_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
+#define USB_COUNT6_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
+#define USB_COUNT6_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
+
+#define USB_COUNT6_RX_BLSIZE_Pos                 (15U)
+#define USB_COUNT6_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
+#define USB_COUNT6_RX_BLSIZE                     USB_COUNT6_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT7_RX register  ****************/
+#define USB_COUNT7_RX_COUNT7_RX_Pos              (0U)
+#define USB_COUNT7_RX_COUNT7_RX_Msk              (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
+#define USB_COUNT7_RX_COUNT7_RX                  USB_COUNT7_RX_COUNT7_RX_Msk   /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK_Pos              (10U)
+#define USB_COUNT7_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
+#define USB_COUNT7_RX_NUM_BLOCK                  USB_COUNT7_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
+#define USB_COUNT7_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
+#define USB_COUNT7_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
+#define USB_COUNT7_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
+#define USB_COUNT7_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
+
+#define USB_COUNT7_RX_BLSIZE_Pos                 (15U)
+#define USB_COUNT7_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
+#define USB_COUNT7_RX_BLSIZE                     USB_COUNT7_RX_BLSIZE_Msk      /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
+
+/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    UCPD                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for UCPD_CFG1 register  *******************/
+#define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
+#define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
+#define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk             /*!< Number of cycles (minus 1) for a half bit clock */
+#define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
+#define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
+#define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
+#define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
+#define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
+#define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
+#define UCPD_CFG1_IFRGAP_Pos                (6U)
+#define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x000007C0 */
+#define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                 /*!< Clock divider value to generates Interframe gap */
+#define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000040 */
+#define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000080 */
+#define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000100 */
+#define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000200 */
+#define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000400 */
+#define UCPD_CFG1_TRANSWIN_Pos              (11U)
+#define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x0000F800 */
+#define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk               /*!< Number of cycles (minus 1) of the half bit clock */
+#define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00000800 */
+#define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00001000 */
+#define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00002000 */
+#define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00004000 */
+#define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00008000 */
+#define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
+#define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
+#define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk            /*!< Prescaler for UCPDCLK */
+#define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
+#define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
+#define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
+#define UCPD_CFG1_RXORDSETEN_Pos            (20U)
+#define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
+#define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk             /*!< Receiver ordered set detection enable */
+#define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
+#define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
+#define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
+#define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
+#define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
+#define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
+#define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
+#define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
+#define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
+#define UCPD_CFG1_TXDMAEN_Pos               (29U)
+#define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)     /*!< 0x20000000 */
+#define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                /*!< DMA transmission requests enable   */
+#define UCPD_CFG1_RXDMAEN_Pos               (30U)
+#define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)     /*!< 0x40000000 */
+#define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                /*!< DMA reception requests enable   */
+#define UCPD_CFG1_UCPDEN_Pos                (31U)
+#define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)      /*!< 0x80000000 */
+#define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                 /*!< USB Power Delivery Block Enable */
+
+/********************  Bits definition for UCPD_CFG2 register  *******************/
+#define UCPD_CFG2_RXFILTDIS_Pos             (0U)
+#define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)   /*!< 0x00000001 */
+#define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk              /*!< Enables an Rx pre-filter for the BMC decoder */
+#define UCPD_CFG2_RXFILT2N3_Pos             (1U)
+#define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)   /*!< 0x00000002 */
+#define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk              /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
+#define UCPD_CFG2_FORCECLK_Pos              (2U)
+#define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)    /*!< 0x00000004 */
+#define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk               /*!< Controls forcing of the clock request UCPDCLK_REQ */
+#define UCPD_CFG2_WUPEN_Pos                 (3U)
+#define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)       /*!< 0x00000008 */
+#define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                  /*!< Wakeup from STOP enable */
+
+/********************  Bits definition for UCPD_CR register  ********************/
+#define UCPD_CR_TXMODE_Pos                  (0U)
+#define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000003 */
+#define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                   /*!< Type of Tx packet  */
+#define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000001 */
+#define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000002 */
+#define UCPD_CR_TXSEND_Pos                  (2U)
+#define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)        /*!< 0x00000004 */
+#define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                   /*!< Type of Tx packet  */
+#define UCPD_CR_TXHRST_Pos                  (3U)
+#define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)        /*!< 0x00000008 */
+#define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                   /*!< Command to send a Tx Hard Reset  */
+#define UCPD_CR_RXMODE_Pos                  (4U)
+#define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)        /*!< 0x00000010 */
+#define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                   /*!< Receiver mode  */
+#define UCPD_CR_PHYRXEN_Pos                 (5U)
+#define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)       /*!< 0x00000020 */
+#define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                  /*!< Controls enable of USB Power Delivery receiver  */
+#define UCPD_CR_PHYCCSEL_Pos                (6U)
+#define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)      /*!< 0x00000040 */
+#define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                 /*!<  */
+#define UCPD_CR_ANASUBMODE_Pos              (7U)
+#define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000180 */
+#define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk               /*!< Analog PHY sub-mode   */
+#define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000080 */
+#define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000100 */
+#define UCPD_CR_ANAMODE_Pos                 (9U)
+#define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)       /*!< 0x00000200 */
+#define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                  /*!< Analog PHY working mode   */
+#define UCPD_CR_CCENABLE_Pos                (10U)
+#define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000C00 */
+#define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                 /*!<  */
+#define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000400 */
+#define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000800 */
+#define UCPD_CR_FRSRXEN_Pos                 (16U)
+#define UCPD_CR_FRSRXEN_Msk                 (0x1UL << UCPD_CR_FRSRXEN_Pos)       /*!< 0x00010000 */
+#define UCPD_CR_FRSRXEN                     UCPD_CR_FRSRXEN_Msk                  /*!< Enable FRS request detection function */
+#define UCPD_CR_FRSTX_Pos                   (17U)
+#define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)         /*!< 0x00020000 */
+#define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                    /*!< Signal Fast Role Swap request */
+#define UCPD_CR_RDCH_Pos                    (18U)
+#define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)          /*!< 0x00040000 */
+#define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                     /*!<  */
+#define UCPD_CR_CC1TCDIS_Pos                (20U)
+#define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)      /*!< 0x00100000 */
+#define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC0 to be disabled. */
+#define UCPD_CR_CC2TCDIS_Pos                (21U)
+#define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)      /*!< 0x00200000 */
+#define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC2 to be disabled. */
+
+/********************  Bits definition for UCPD_IMR register  *******************/
+#define UCPD_IMR_TXISIE_Pos                 (0U)
+#define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)       /*!< 0x00000001 */
+#define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                  /*!< Enable TXIS interrupt  */
+#define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
+#define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)  /*!< 0x00000002 */
+#define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk             /*!< Enable TXMSGDISC interrupt  */
+#define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
+#define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)  /*!< 0x00000004 */
+#define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk             /*!< Enable TXMSGSENT interrupt  */
+#define UCPD_IMR_TXMSGABTIE_Pos             (3U)
+#define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)   /*!< 0x00000008 */
+#define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk              /*!< Enable TXMSGABT interrupt  */
+#define UCPD_IMR_HRSTDISCIE_Pos             (4U)
+#define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)   /*!< 0x00000010 */
+#define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk              /*!< Enable HRSTDISC interrupt  */
+#define UCPD_IMR_HRSTSENTIE_Pos             (5U)
+#define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)   /*!< 0x00000020 */
+#define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk              /*!< Enable HRSTSENT interrupt  */
+#define UCPD_IMR_TXUNDIE_Pos                (6U)
+#define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)      /*!< 0x00000040 */
+#define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                 /*!< Enable TXUND interrupt  */
+#define UCPD_IMR_RXNEIE_Pos                 (8U)
+#define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)       /*!< 0x00000100 */
+#define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                  /*!< Enable RXNE interrupt  */
+#define UCPD_IMR_RXORDDETIE_Pos             (9U)
+#define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)   /*!< 0x00000200 */
+#define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk              /*!< Enable RXORDDET interrupt  */
+#define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
+#define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)  /*!< 0x00000400 */
+#define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk             /*!< Enable RXHRSTDET interrupt  */
+#define UCPD_IMR_RXOVRIE_Pos                (11U)
+#define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)      /*!< 0x00000800 */
+#define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                 /*!< Enable RXOVR interrupt  */
+#define UCPD_IMR_RXMSGENDIE_Pos             (12U)
+#define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)   /*!< 0x00001000 */
+#define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk              /*!< Enable RXMSGEND interrupt  */
+#define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
+#define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)  /*!< 0x00004000 */
+#define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk             /*!< Enable TYPECEVT1IE interrupt  */
+#define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
+#define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)  /*!< 0x00008000 */
+#define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk             /*!< Enable TYPECEVT2IE interrupt  */
+#define UCPD_IMR_FRSEVTIE_Pos               (20U)
+#define UCPD_IMR_FRSEVTIE_Msk               (0x1UL << UCPD_IMR_FRSEVTIE_Pos)     /*!< 0x00100000 */
+#define UCPD_IMR_FRSEVTIE                   UCPD_IMR_FRSEVTIE_Msk                /*!< Fast Role Swap interrupt  */
+
+/********************  Bits definition for UCPD_SR register  ********************/
+#define UCPD_SR_TXIS_Pos                    (0U)
+#define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)          /*!< 0x00000001 */
+#define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                     /*!< Transmit interrupt status  */
+#define UCPD_SR_TXMSGDISC_Pos               (1U)
+#define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)     /*!< 0x00000002 */
+#define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                /*!< Transmit message discarded interrupt  */
+#define UCPD_SR_TXMSGSENT_Pos               (2U)
+#define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)     /*!< 0x00000004 */
+#define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                /*!< Transmit message sent interrupt  */
+#define UCPD_SR_TXMSGABT_Pos                (3U)
+#define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)      /*!< 0x00000008 */
+#define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                 /*!< Transmit message abort interrupt  */
+#define UCPD_SR_HRSTDISC_Pos                (4U)
+#define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)      /*!< 0x00000010 */
+#define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                 /*!< HRST discarded interrupt  */
+#define UCPD_SR_HRSTSENT_Pos                (5U)
+#define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)      /*!< 0x00000020 */
+#define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                 /*!< HRST sent interrupt  */
+#define UCPD_SR_TXUND_Pos                   (6U)
+#define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)         /*!< 0x00000040 */
+#define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                    /*!< Tx data underrun condition interrupt  */
+#define UCPD_SR_RXNE_Pos                    (8U)
+#define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)          /*!< 0x00000100 */
+#define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                     /*!< Receive data register not empty interrupt  */
+#define UCPD_SR_RXORDDET_Pos                (9U)
+#define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)      /*!< 0x00000200 */
+#define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                 /*!< Rx ordered set (4 K-codes) detected interrupt  */
+#define UCPD_SR_RXHRSTDET_Pos               (10U)
+#define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)     /*!< 0x00000400 */
+#define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                /*!< Rx Hard Reset detect interrupt  */
+#define UCPD_SR_RXOVR_Pos                   (11U)
+#define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)         /*!< 0x00000800 */
+#define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                    /*!< Rx data overflow interrupt  */
+#define UCPD_SR_RXMSGEND_Pos                (12U)
+#define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)      /*!< 0x00001000 */
+#define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                 /*!< Rx message received  */
+#define UCPD_SR_RXERR_Pos                   (13U)
+#define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)         /*!< 0x00002000 */
+#define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                    /*!< RX Error */
+#define UCPD_SR_TYPECEVT1_Pos               (14U)
+#define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)     /*!< 0x00004000 */
+#define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                /*!< Type C voltage level event on CC1  */
+#define UCPD_SR_TYPECEVT2_Pos               (15U)
+#define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)     /*!< 0x00008000 */
+#define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                /*!< Type C voltage level event on CC2  */
+#define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
+#define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
+#define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk           /*!< Status of DC level on CC1 pin  */
+#define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
+#define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
+#define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk           /*!<Status of DC level on CC2 pin  */
+#define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
+#define UCPD_SR_FRSEVT_Pos                  (20U)
+#define UCPD_SR_FRSEVT_Msk                  (0x1UL << UCPD_SR_FRSEVT_Pos)        /*!< 0x00100000 */
+#define UCPD_SR_FRSEVT                      UCPD_SR_FRSEVT_Msk                   /*!< Fast Role Swap detection event  */
+
+/********************  Bits definition for UCPD_ICR register  *******************/
+#define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
+#define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)  /*!< 0x00000002 */
+#define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk             /*!< Tx message discarded flag (TXMSGDISC) clear  */
+#define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
+#define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)  /*!< 0x00000004 */
+#define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk             /*!< Tx message sent flag (TXMSGSENT) clear  */
+#define UCPD_ICR_TXMSGABTCF_Pos             (3U)
+#define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)   /*!< 0x00000008 */
+#define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk              /*!< Tx message abort flag (TXMSGABT) clear  */
+#define UCPD_ICR_HRSTDISCCF_Pos             (4U)
+#define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)   /*!< 0x00000010 */
+#define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk              /*!< Hard reset discarded flag (HRSTDISC) clear  */
+#define UCPD_ICR_HRSTSENTCF_Pos             (5U)
+#define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)   /*!< 0x00000020 */
+#define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk              /*!< Hard reset sent flag (HRSTSENT) clear  */
+#define UCPD_ICR_TXUNDCF_Pos                (6U)
+#define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)      /*!< 0x00000040 */
+#define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                 /*!< Tx underflow flag (TXUND) clear  */
+#define UCPD_ICR_RXORDDETCF_Pos             (9U)
+#define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)   /*!< 0x00000200 */
+#define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk              /*!< Rx ordered set detect flag (RXORDDET) clear  */
+#define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
+#define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)  /*!< 0x00000400 */
+#define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk             /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
+#define UCPD_ICR_RXOVRCF_Pos                (11U)
+#define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)      /*!< 0x00000800 */
+#define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                 /*!< Rx overflow flag (RXOVR) clear  */
+#define UCPD_ICR_RXMSGENDCF_Pos             (12U)
+#define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)   /*!< 0x00001000 */
+#define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk              /*!< Rx message received flag (RXMSGEND) clear  */
+#define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
+#define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)  /*!< 0x00004000 */
+#define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk             /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
+#define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
+#define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)  /*!< 0x00008000 */
+#define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk             /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
+#define UCPD_ICR_FRSEVTCF_Pos               (20U)
+#define UCPD_ICR_FRSEVTCF_Msk               (0x1UL << UCPD_ICR_FRSEVTCF_Pos)     /*!< 0x00100000 */
+#define UCPD_ICR_FRSEVTCF                   UCPD_ICR_FRSEVTCF_Msk                /*!< Fast Role Swap event flag clear  */
+
+/********************  Bits definition for UCPD_TXORDSET register  **************/
+#define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
+#define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
+#define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk               /*!< Tx Ordered Set */
+
+/********************  Bits definition for UCPD_TXPAYSZ register  ****************/
+#define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
+#define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
+#define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk             /*!< Tx payload size in bytes  */
+
+/********************  Bits definition for UCPD_TXDR register  *******************/
+#define UCPD_TXDR_TXDATA_Pos                (0U)
+#define UCPD_TXDR_TXDATA_Msk                 (0xFFUL << UCPD_TXDR_TXDATA_Pos)     /*!< 0x000000FF */
+#define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                  /*!< Tx Data Register */
+
+/********************  Bits definition for UCPD_RXORDSET register  **************/
+#define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
+#define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
+#define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk            /*!< Rx Ordered Set Code detected  */
+#define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
+#define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
+#define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
+#define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
+#define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
+#define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk           /*!< Rx Ordered Set Debug indication */
+#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
+#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
+#define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk           /*!< Rx Ordered Set corrupted K-Codes (Debug) */
+
+/********************  Bits definition for UCPD_RXPAYSZ register  ****************/
+#define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
+#define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
+#define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk             /*!< Rx payload size in bytes  */
+
+/********************  Bits definition for UCPD_RXDR register  *******************/
+#define UCPD_RXDR_RXDATA_Pos                (0U)
+#define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)     /*!< 0x000000FF */
+#define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                 /*!< 8-bit receive data  */
+
+/********************  Bits definition for UCPD_RXORDEXT1 register  **************/
+#define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
+#define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
+#define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk               /*!< RX Ordered Set Extension Register 1 */
+
+/********************  Bits definition for UCPD_RXORDEXT2 register  **************/
+#define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
+#define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
+#define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk               /*!< RX Ordered Set Extension Register 1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)
+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)
+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)
+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
+
+#define WWDG_CFR_WDGTB_Pos      (11U)
+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */
+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */
+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */
+
+#define WWDG_CFR_EWI_Pos        (9U)
+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)
+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
+
+
+/******************************** FDCAN Instances ******************************/
+#define IS_FDCAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1)
+
+#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                        ((INSTANCE) == COMP2) || \
+                                        ((INSTANCE) == COMP3) || \
+                                        ((INSTANCE) == COMP4))
+
+/******************************* CORDIC Instances *****************************/
+#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
+                                       ((INSTANCE) == DAC3))
+
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+                                       ((INSTANCE) == DMA1_Channel2) || \
+                                       ((INSTANCE) == DMA1_Channel3) || \
+                                       ((INSTANCE) == DMA1_Channel4) || \
+                                       ((INSTANCE) == DMA1_Channel5) || \
+                                       ((INSTANCE) == DMA1_Channel6) || \
+                                       ((INSTANCE) == DMA2_Channel1) || \
+                                       ((INSTANCE) == DMA2_Channel2) || \
+                                       ((INSTANCE) == DMA2_Channel3) || \
+                                       ((INSTANCE) == DMA2_Channel4) || \
+                                       ((INSTANCE) == DMA2_Channel5) || \
+                                       ((INSTANCE) == DMA2_Channel6))
+
+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3))
+
+/******************************* FMAC Instances *******************************/
+#define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG))
+
+/******************************* GPIO AF Instances ****************************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2) || \
+                                         ((INSTANCE) == OPAMP3))
+
+/******************************** PCD Instances *******************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+#define IS_TAMP_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == TAMP)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3))
+
+/******************************** SAI Instances *******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI2) || \
+                                            ((__INSTANCE__) == SPI3))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8)    || \
+                                            ((INSTANCE) == TIM15)   || \
+                                            ((INSTANCE) == TIM16)   || \
+                                            ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM8)   || \
+                                               ((INSTANCE) == TIM15)  || \
+                                               ((INSTANCE) == TIM16)  || \
+                                               ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM3) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM4) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM8) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM17) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3) ||           \
+      ((CHANNEL) == TIM_CHANNEL_4)))            \
+    ||                                          \
+    (((INSTANCE) == TIM8) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3) ||           \
+      ((CHANNEL) == TIM_CHANNEL_4)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
+                                                    ((INSTANCE) == TIM2)    || \
+                                                    ((INSTANCE) == TIM3)    || \
+                                                    ((INSTANCE) == TIM4)    || \
+                                                    ((INSTANCE) == TIM8)    || \
+                                                    ((INSTANCE) == TIM15)   || \
+                                                    ((INSTANCE) == TIM16)   || \
+                                                    ((INSTANCE) == TIM17))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM8)   || \
+                                                     ((INSTANCE) == TIM15)  || \
+                                                     ((INSTANCE) == TIM16)  || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                      ((INSTANCE) == TIM2)  || \
+                                                      ((INSTANCE) == TIM3)  || \
+                                                      ((INSTANCE) == TIM4)  || \
+                                                      ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                         ((INSTANCE) == TIM2)   || \
+                                                         ((INSTANCE) == TIM3)   || \
+                                                         ((INSTANCE) == TIM4)   || \
+                                                         ((INSTANCE) == TIM8)   || \
+                                                         ((INSTANCE) == TIM15))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM8))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                             ((INSTANCE) == TIM2)  || \
+                                             ((INSTANCE) == TIM3)  || \
+                                             ((INSTANCE) == TIM4)  || \
+                                             ((INSTANCE) == TIM8))
+
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM6)  || \
+                                            ((INSTANCE) == TIM7)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
+                                                       ((INSTANCE) == TIM2) || \
+                                                       ((INSTANCE) == TIM3) || \
+                                                       ((INSTANCE) == TIM4)  || \
+                                                       ((INSTANCE) == TIM8)  || \
+                                                       ((INSTANCE) == TIM15) || \
+                                                       ((INSTANCE) == TIM16) || \
+                                                       ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
+#define IS_TIM_OCCS_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)  || \
+                                                       ((INSTANCE) == TIM2)  || \
+                                                       ((INSTANCE) == TIM3)  || \
+                                                       ((INSTANCE) == TIM8)  || \
+                                                       ((INSTANCE) == TIM15) || \
+                                                       ((INSTANCE) == TIM16) || \
+                                                       ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                       ((INSTANCE) == TIM8)  || \
+                                                       ((INSTANCE) == TIM15) || \
+                                                       ((INSTANCE) == TIM16) || \
+                                                       ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/******************* TIM Instances : Timer input selection ********************/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                                  ((INSTANCE) == TIM8))
+
+
+/****************** TIM Instances : supporting HSE/32 request instances *******************/
+#define IS_TIM_HSE32_INSTANCE(INSTANCE)         (((INSTANCE) == TIM16)   || \
+                                                 ((INSTANCE) == TIM17))
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4))
+
+/*********************** UART Instances : FIFO mode ***************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == UART4) || \
+                                         ((INSTANCE) == LPUART1))
+
+/*********************** UART Instances : SPI Slave mode **********************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                              ((INSTANCE) == USART2) || \
+                                              ((INSTANCE) == USART3))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3) || \
+                                                            ((INSTANCE) == UART4))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                 ((INSTANCE) == USART2) || \
+                                                 ((INSTANCE) == USART3) || \
+                                                 ((INSTANCE) == UART4)  || \
+                                                 ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == UART4)  || \
+                                           ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                          ((INSTANCE) == USART2) || \
+                                          ((INSTANCE) == USART3) || \
+                                          ((INSTANCE) == UART4))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == LPUART1))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4))
+
+/********************* USART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/****************************** UCPD Instances ********************************/
+#define IS_UCPD_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == UCPD1)
+
+/******************************* USB Instances *******************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/**
+  * @}
+  */
+
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32G4xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */
+/*  product lines within the same STM32G4 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define TIM7_DAC_IRQn     TIM7_IRQn
+#define COMP4_5_6_IRQn    COMP4_IRQn
+
+/* Aliases for __IRQHandler */
+#define TIM7_DAC_IRQHandler     TIM7_IRQHandler
+#define COMP4_5_6_IRQHandler    COMP4_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32G431xx_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h b/squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h
new file mode 100644
index 0000000..5bc4aa9
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h
@@ -0,0 +1,259 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32G4xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32G4xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral’s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32g4xx
+  * @{
+  */
+
+#ifndef __STM32G4xx_H
+#define __STM32G4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32G4)
+#define STM32G4
+#endif /* STM32G4 */
+
+/* Uncomment the line below according to the target STM32G4 device used in your
+   application
+  */
+
+#if !defined (STM32G431xx) && !defined (STM32G441xx) && !defined (STM32G471xx) && \
+    !defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G484xx) && \
+    !defined (STM32GBK1CB) && !defined (STM32G491xx) && !defined (STM32G4A1xx)
+  /* #define STM32G431xx */   /*!< STM32G431xx Devices */
+  /* #define STM32G441xx */   /*!< STM32G441xx Devices */
+  /* #define STM32G471xx */   /*!< STM32G471xx Devices */
+  /* #define STM32G473xx */   /*!< STM32G473xx Devices */
+  /* #define STM32G483xx */   /*!< STM32G483xx Devices */
+  /* #define STM32G474xx */   /*!< STM32G474xx Devices */
+  /* #define STM32G484xx */   /*!< STM32G484xx Devices */
+  /* #define STM32G491xx */   /*!< STM32G491xx Devices */
+  /* #define STM32G4A1xx */   /*!< STM32G4A1xx Devices */
+  /* #define STM32GBK1CB */   /*!< STM32GBK1CB Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.2.2
+  */
+#define __STM32G4_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32G4_CMSIS_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
+#define __STM32G4_CMSIS_VERSION_SUB2   (0x02U) /*!< [15:8]  sub2 version */
+#define __STM32G4_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32G4_CMSIS_VERSION        ((__STM32G4_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32G4_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32G4_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32G4_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32G431xx)
+  #include "stm32g431xx.h"
+#elif defined(STM32G441xx)
+  #include "stm32g441xx.h"
+#elif defined(STM32G471xx)
+  #include "stm32g471xx.h"
+#elif defined(STM32G473xx)
+  #include "stm32g473xx.h"
+#elif defined(STM32G483xx)
+  #include "stm32g483xx.h"
+#elif defined(STM32G474xx)
+  #include "stm32g474xx.h"
+#elif defined(STM32G484xx)
+  #include "stm32g484xx.h"
+#elif defined(STM32G491xx)
+  #include "stm32g491xx.h"
+#elif defined(STM32G4A1xx)
+  #include "stm32g4a1xx.h"
+#elif defined(STM32GBK1CB)
+  #include "stm32gbk1cb.h"
+#else
+  #error "Please select first the target STM32G4xx device used in your application (in stm32g4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT)                             \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
+  do {                                                                     \
+    uint32_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
+  } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT)                            \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
+  do {                                                                     \
+    uint16_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
+  } while(0)
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32g4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32G4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
diff --git a/squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h b/squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h
new file mode 100644
index 0000000..ba8bdae
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h
@@ -0,0 +1,104 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32g4xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32G4xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32g4xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32G4XX_H
+#define __SYSTEM_STM32G4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32G4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32G4xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;            /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32G4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32G4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32G4xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32G4XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/LICENSE.txt b/squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/LICENSE.txt
new file mode 100644
index 0000000..5306686
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Device/ST/STM32G4xx/LICENSE.txt
@@ -0,0 +1,6 @@
+This software component is provided to you as part of a software package and
+applicable license terms are in the  Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the Apache-2.0 license shall apply. 
+You may obtain a copy of the Apache-2.0 at:
+https://opensource.org/licenses/Apache-2.0
diff --git a/squeow_sw/Drivers/CMSIS/Include/cmsis_armcc.h b/squeow_sw/Drivers/CMSIS/Include/cmsis_armcc.h
new file mode 100644
index 0000000..da9d654
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,894 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.1.0
+ * @date     08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __ARM_FEATURE_DSP         1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __memory_changed()
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section("RESET")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/squeow_sw/Drivers/CMSIS/Include/cmsis_armclang.h b/squeow_sw/Drivers/CMSIS/Include/cmsis_armclang.h
new file mode 100644
index 0000000..478f75b
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/cmsis_armclang.h
@@ -0,0 +1,1444 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.2.0
+ * @date     08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section("RESET")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF)
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define     __SADD8                 __builtin_arm_sadd8
+#define     __QADD8                 __builtin_arm_qadd8
+#define     __SHADD8                __builtin_arm_shadd8
+#define     __UADD8                 __builtin_arm_uadd8
+#define     __UQADD8                __builtin_arm_uqadd8
+#define     __UHADD8                __builtin_arm_uhadd8
+#define     __SSUB8                 __builtin_arm_ssub8
+#define     __QSUB8                 __builtin_arm_qsub8
+#define     __SHSUB8                __builtin_arm_shsub8
+#define     __USUB8                 __builtin_arm_usub8
+#define     __UQSUB8                __builtin_arm_uqsub8
+#define     __UHSUB8                __builtin_arm_uhsub8
+#define     __SADD16                __builtin_arm_sadd16
+#define     __QADD16                __builtin_arm_qadd16
+#define     __SHADD16               __builtin_arm_shadd16
+#define     __UADD16                __builtin_arm_uadd16
+#define     __UQADD16               __builtin_arm_uqadd16
+#define     __UHADD16               __builtin_arm_uhadd16
+#define     __SSUB16                __builtin_arm_ssub16
+#define     __QSUB16                __builtin_arm_qsub16
+#define     __SHSUB16               __builtin_arm_shsub16
+#define     __USUB16                __builtin_arm_usub16
+#define     __UQSUB16               __builtin_arm_uqsub16
+#define     __UHSUB16               __builtin_arm_uhsub16
+#define     __SASX                  __builtin_arm_sasx
+#define     __QASX                  __builtin_arm_qasx
+#define     __SHASX                 __builtin_arm_shasx
+#define     __UASX                  __builtin_arm_uasx
+#define     __UQASX                 __builtin_arm_uqasx
+#define     __UHASX                 __builtin_arm_uhasx
+#define     __SSAX                  __builtin_arm_ssax
+#define     __QSAX                  __builtin_arm_qsax
+#define     __SHSAX                 __builtin_arm_shsax
+#define     __USAX                  __builtin_arm_usax
+#define     __UQSAX                 __builtin_arm_uqsax
+#define     __UHSAX                 __builtin_arm_uhsax
+#define     __USAD8                 __builtin_arm_usad8
+#define     __USADA8                __builtin_arm_usada8
+#define     __SSAT16                __builtin_arm_ssat16
+#define     __USAT16                __builtin_arm_usat16
+#define     __UXTB16                __builtin_arm_uxtb16
+#define     __UXTAB16               __builtin_arm_uxtab16
+#define     __SXTB16                __builtin_arm_sxtb16
+#define     __SXTAB16               __builtin_arm_sxtab16
+#define     __SMUAD                 __builtin_arm_smuad
+#define     __SMUADX                __builtin_arm_smuadx
+#define     __SMLAD                 __builtin_arm_smlad
+#define     __SMLADX                __builtin_arm_smladx
+#define     __SMLALD                __builtin_arm_smlald
+#define     __SMLALDX               __builtin_arm_smlaldx
+#define     __SMUSD                 __builtin_arm_smusd
+#define     __SMUSDX                __builtin_arm_smusdx
+#define     __SMLSD                 __builtin_arm_smlsd
+#define     __SMLSDX                __builtin_arm_smlsdx
+#define     __SMLSLD                __builtin_arm_smlsld
+#define     __SMLSLDX               __builtin_arm_smlsldx
+#define     __SEL                   __builtin_arm_sel
+#define     __QADD                  __builtin_arm_qadd
+#define     __QSUB                  __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/squeow_sw/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/squeow_sw/Drivers/CMSIS/Include/cmsis_armclang_ltm.h
new file mode 100644
index 0000000..1b5a965
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/cmsis_armclang_ltm.h
@@ -0,0 +1,1891 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang_ltm.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V1.2.0
+ * @date     08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section("RESET")))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF)
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/squeow_sw/Drivers/CMSIS/Include/cmsis_compiler.h b/squeow_sw/Drivers/CMSIS/Include/cmsis_compiler.h
new file mode 100644
index 0000000..21a2c71
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/squeow_sw/Drivers/CMSIS/Include/cmsis_gcc.h b/squeow_sw/Drivers/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 0000000..1e08e7e
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,2168 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.2.0
+ * @date     08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+  \brief   Initializes data and bss sections
+  \details This default implementations initialized all data and additional bss
+           sections relying on .copy.table and .zero.table specified properly
+           in the used linker script.
+  
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+  extern void _start(void) __NO_RETURN;
+  
+  typedef struct {
+    uint32_t const* src;
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __copy_table_t;
+  
+  typedef struct {
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __zero_table_t;
+  
+  extern const __copy_table_t __copy_table_start__;
+  extern const __copy_table_t __copy_table_end__;
+  extern const __zero_table_t __zero_table_start__;
+  extern const __zero_table_t __zero_table_end__;
+
+  for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = pTable->src[i];
+    }
+  }
+ 
+  for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = 0u;
+    }
+  }
+ 
+  _start();
+}
+  
+#define __PROGRAM_START           __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/squeow_sw/Drivers/CMSIS/Include/cmsis_iccarm.h b/squeow_sw/Drivers/CMSIS/Include/cmsis_iccarm.h
new file mode 100644
index 0000000..7af7562
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/cmsis_iccarm.h
@@ -0,0 +1,964 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.1.0
+ * @date     08. May 2019
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved. 
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/squeow_sw/Drivers/CMSIS/Include/cmsis_version.h b/squeow_sw/Drivers/CMSIS/Include/cmsis_version.h
new file mode 100644
index 0000000..3174cf6
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.3
+ * @date     24. June 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_armv81mml.h b/squeow_sw/Drivers/CMSIS/Include/core_armv81mml.h
new file mode 100644
index 0000000..8cee930
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_armv81mml.h
@@ -0,0 +1,2968 @@
+/**************************************************************************//**
+ * @file     core_armv81mml.h
+ * @brief    CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
+ * @version  V1.0.0
+ * @date     15. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV81MML_H_GENERIC
+#define __CORE_ARMV81MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMV81MML
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+#define __ARM_ARCH_8M_MAIN__    1  // patching for now
+/*  CMSIS ARMV81MML definitions */
+#define __ARMv81MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv81MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv81MML_CMSIS_VERSION       ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv81MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U    
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+  
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U    
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+  
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U    
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+  
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U    
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+  
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV81MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV81MML_H_DEPENDANT
+#define __CORE_ARMV81MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv81MML_REV
+    #define __ARMv81MML_REV               0x0000U
+    #warning "__ARMv81MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv81MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos                    4U                                            /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk                   (0x1UL << MPU_RLAR_PXN_Pos)                    /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  __DSB();
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV81MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_armv8mbl.h b/squeow_sw/Drivers/CMSIS/Include/core_armv8mbl.h
new file mode 100644
index 0000000..266f180
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_armv8mbl.h
@@ -0,0 +1,1921 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  __DSB();
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_armv8mml.h b/squeow_sw/Drivers/CMSIS/Include/core_armv8mml.h
new file mode 100644
index 0000000..ba5d83f
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_armv8mml.h
@@ -0,0 +1,2835 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version  V5.1.0
+ * @date     12. September 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[32U];
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  __DSB();
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)                      );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_cm0.h b/squeow_sw/Drivers/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000..70e4505
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_cm0.h
@@ -0,0 +1,952 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     13. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t vectors = 0x0U;
+  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+  /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t vectors = 0x0U;
+  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_cm0plus.h b/squeow_sw/Drivers/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000..fe7b424
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,1085 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     13. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t vectors = SCB->VTOR;
+#else
+  uint32_t vectors = 0x0U;
+#endif
+  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+  /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t vectors = SCB->VTOR;
+#else
+  uint32_t vectors = 0x0U;
+#endif
+  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_cm1.h b/squeow_sw/Drivers/CMSIS/Include/core_cm1.h
new file mode 100644
index 0000000..44c2a49
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_cm1.h
@@ -0,0 +1,979 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.1
+ * @date     12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_cm23.h b/squeow_sw/Drivers/CMSIS/Include/core_cm23.h
new file mode 100644
index 0000000..49f4a5b
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_cm23.h
@@ -0,0 +1,1996 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+	
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  __DSB();
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_cm3.h b/squeow_sw/Drivers/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000..1f69e8b
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1937 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.1.0
+ * @date     13. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+#endif
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[32U];
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t vectors = (uint32_t )SCB->VTOR;
+  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+  /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t vectors = (uint32_t )SCB->VTOR;
+  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_cm33.h b/squeow_sw/Drivers/CMSIS/Include/core_cm33.h
new file mode 100644
index 0000000..2f1d98e
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_cm33.h
@@ -0,0 +1,2910 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.1.0
+ * @date     12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_FP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[32U];
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  __DSB();
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_cm35p.h b/squeow_sw/Drivers/CMSIS/Include/core_cm35p.h
new file mode 100644
index 0000000..7d34367
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_cm35p.h
@@ -0,0 +1,2910 @@
+/**************************************************************************//**
+ * @file     core_cm35p.h
+ * @brief    CMSIS Cortex-M35P Core Peripheral Access Layer Header File
+ * @version  V1.0.0
+ * @date     12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM35P_H_GENERIC
+#define __CORE_CM35P_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M35P
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM35P definitions */
+#define __CM35P_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM35P_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM35P_CMSIS_VERSION       ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \
+                                      __CM35P_CMSIS_VERSION_SUB           )    /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (35U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_FP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM35P_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM35P_H_DEPENDANT
+#define __CORE_CM35P_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM35P_REV
+    #define __CM35P_REV               0x0000U
+    #warning "__CM35P_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M35P */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[32U];
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  __DSB();
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM35P_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_cm4.h b/squeow_sw/Drivers/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000..90c2a72
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_cm4.h
@@ -0,0 +1,2124 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.1.0
+ * @date     13. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[32U];
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t vectors = (uint32_t )SCB->VTOR;
+  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+  /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t vectors = (uint32_t )SCB->VTOR;
+  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_cm7.h b/squeow_sw/Drivers/CMSIS/Include/core_cm7.h
new file mode 100644
index 0000000..3da3c43
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2725 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.1.1
+ * @date     28. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISDYNADD_Pos         26U                                         /*!< ACTLR: DISDYNADD Position */
+#define SCnSCB_ACTLR_DISDYNADD_Msk         (1UL << SCnSCB_ACTLR_DISDYNADD_Pos)         /*!< ACTLR: DISDYNADD Mask */
+
+#define SCnSCB_ACTLR_DISISSCH1_Pos         21U                                         /*!< ACTLR: DISISSCH1 Position */
+#define SCnSCB_ACTLR_DISISSCH1_Msk         (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos)      /*!< ACTLR: DISISSCH1 Mask */
+
+#define SCnSCB_ACTLR_DISDI_Pos             16U                                         /*!< ACTLR: DISDI Position */
+#define SCnSCB_ACTLR_DISDI_Msk             (0x1FUL << SCnSCB_ACTLR_DISDI_Pos)          /*!< ACTLR: DISDI Mask */
+
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos     15U                                         /*!< ACTLR: DISCRITAXIRUR Position */
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk     (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos)     /*!< ACTLR: DISCRITAXIRUR Mask */
+
+#define SCnSCB_ACTLR_DISBTACALLOC_Pos      14U                                         /*!< ACTLR: DISBTACALLOC Position */
+#define SCnSCB_ACTLR_DISBTACALLOC_Msk      (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos)      /*!< ACTLR: DISBTACALLOC Mask */
+
+#define SCnSCB_ACTLR_DISBTACREAD_Pos       13U                                         /*!< ACTLR: DISBTACREAD Position */
+#define SCnSCB_ACTLR_DISBTACREAD_Msk       (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos)       /*!< ACTLR: DISBTACREAD Mask */
+
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[32U];
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t vectors = (uint32_t )SCB->VTOR;
+  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+  __DSB();
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t vectors = (uint32_t )SCB->VTOR;
+  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+#define __SCB_DCACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#define __SCB_ICACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
+
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   I-Cache Invalidate by address
+  \details Invalidates I-Cache for the given address.
+           I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           I-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   isize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    if ( isize > 0 ) {
+       int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_ICACHE_LINE_SIZE;
+        op_size -= __SCB_ICACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address.
+           D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) { 
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+    
+      __DSB();
+
+      do {
+        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+           D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are cleaned.
+  \param[in]   addr    address
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) { 
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+    
+      __DSB();
+
+      do {
+        SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+           D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) { 
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+    
+      __DSB();
+
+      do {
+        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr +=          __SCB_DCACHE_LINE_SIZE;
+        op_size -=          __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_sc000.h b/squeow_sw/Drivers/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000..f315013
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_sc000.h
@@ -0,0 +1,1025 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/core_sc300.h b/squeow_sw/Drivers/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000..ad031f2
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1912 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     31. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[32U];
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t vectors = (uint32_t )SCB->VTOR;
+  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+  /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t vectors = (uint32_t )SCB->VTOR;
+  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/squeow_sw/Drivers/CMSIS/Include/mpu_armv7.h b/squeow_sw/Drivers/CMSIS/Include/mpu_armv7.h
new file mode 100644
index 0000000..337eb65
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/mpu_armv7.h
@@ -0,0 +1,272 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.1.0
+ * @date     08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/squeow_sw/Drivers/CMSIS/Include/mpu_armv8.h b/squeow_sw/Drivers/CMSIS/Include/mpu_armv8.h
new file mode 100644
index 0000000..2fe28b6
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/mpu_armv8.h
@@ -0,0 +1,346 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.0
+ * @date     08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/squeow_sw/Drivers/CMSIS/Include/tz_context.h b/squeow_sw/Drivers/CMSIS/Include/tz_context.h
new file mode 100644
index 0000000..d4c1474
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/Include/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
diff --git a/squeow_sw/Drivers/CMSIS/LICENSE.txt b/squeow_sw/Drivers/CMSIS/LICENSE.txt
new file mode 100644
index 0000000..c0ee812
--- /dev/null
+++ b/squeow_sw/Drivers/CMSIS/LICENSE.txt
@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
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+      to the Licensor or its representatives, including but not limited to
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+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
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diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
index 0000000..aca5b00
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,3912 @@
+/**
+  ******************************************************************************
+  * @file    stm32_hal_legacy.h
+  * @author  MCD Application Team
+  * @brief   This file contains aliases definition for the STM32Cube HAL constants
+  *          macros and functions maintained for legacy purpose.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
+#if defined(STM32U5)
+#define CRYP_DATATYPE_32B               CRYP_NO_SWAP
+#define CRYP_DATATYPE_16B               CRYP_HALFWORD_SWAP
+#define CRYP_DATATYPE_8B                CRYP_BYTE_SWAP
+#define CRYP_DATATYPE_1B                CRYP_BIT_SWAP
+#define CRYP_CCF_CLEAR                  CRYP_CLEAR_CCF
+#define CRYP_ERR_CLEAR                  CRYP_CLEAR_RWEIF
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP                   ADC_REGULAR_GROUP
+#define INJECTED_GROUP                  ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT                       ADC_AWD_EVENT
+#define AWD1_EVENT                      ADC_AWD1_EVENT
+#define AWD2_EVENT                      ADC_AWD2_EVENT
+#define AWD3_EVENT                      ADC_AWD3_EVENT
+#define OVR_EVENT                       ADC_OVR_EVENT
+#define JQOVF_EVENT                     ADC_JQOVF_EVENT
+#define ALL_CHANNELS                    ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
+/* to the second dedicated IO (only for COMP2).                               */
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define  MPU_DEVICE_nGnRnE          MPU_DEVICE_NGNRNE
+#define  MPU_DEVICE_nGnRE           MPU_DEVICE_NGNRE
+#define  MPU_DEVICE_nGRE            MPU_DEVICE_NGRE
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Aliases CRC API aliases
+  * @{
+  */
+#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
+#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
+#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC_WAVE_NONE                                   0x00000000U
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT  DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT  DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT       DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP                    OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE                      FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW                     OB_IWDG_SW
+#define OB_WDG_HW                     OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
+#if defined(STM32G0)
+#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR     FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR     FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R      FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR     FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR     FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R      FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0              OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0                OB_USER_NBOOT0
+#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
+#define OB_nBOOT0_SET                 OB_NBOOT0_SET
+#endif /* STM32U5 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+  * @{
+  */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
+#define GET_GPIO_INDEX                            GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
+    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
+
+#if defined(STM32L1)
+#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+#define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
+
+#if defined(STM32U5)
+#define GPIO_AF0_RTC_50Hz                         GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI                      GTZC_PERIPH_DCMI_PSSI
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+  */
+#define HRTIM_EVENTSRC_1              (0x00000000U)
+#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+  */
+#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
+#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
+#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_LPTIM_ReadCompare      HAL_LPTIM_ReadCapturedValue
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_LPTIM_Aliased_Defines LL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define LL_LPTIM_SetCompareCH1     LL_LPTIM_OC_SetCompareCH1
+#define LL_LPTIM_SetCompareCH2     LL_LPTIM_OC_SetCompareCH2
+#define LL_LPTIM_GetCompareCH1     LL_LPTIM_OC_GetCompareCH1
+#define LL_LPTIM_GetCompareCH2     LL_LPTIM_OC_GetCompareCH2
+/**
+  * @}
+  */
+
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1        LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2        LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL    0x00000000U
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef             NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE                    NOR_WRITE
+#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+#define I2S_IT_TXE               I2S_IT_TXP
+#define I2S_IT_RXNE              I2S_IT_RXP
+
+#define I2S_FLAG_TXE             I2S_FLAG_TXP
+#define I2S_FLAG_RXNE            I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+#define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA                       ATA_DATA
+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD                  ATA_CARD_HEAD
+#define CF_STATUS_CMD                 ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FORMAT_BIN                  RTC_FORMAT_BIN
+#define FORMAT_BCD                  RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+#define SPI_FLAG_TXE                    SPI_FLAG_TXP
+#define SPI_FLAG_RXNE                   SPI_FLAG_RXP
+
+#define SPI_IT_TXE                      SPI_IT_TXP
+#define SPI_IT_RXNE                     SPI_IT_RXP
+
+#define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
+#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
+#define TIM_DMABase_SR                   TIM_DMABASE_SR
+#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
+#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
+#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
+#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
+#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
+#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
+#define TIM_DMABase_OR                   TIM_DMABASE_OR
+
+#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
+
+#define __DIV_LPUART                    UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED               USART_NACK_ENABLE
+#define USARTNACK_DISABLED              USART_NACK_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CFR_BASE                    WWDG_CFR_BASE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0                CAN_IT_TME
+#define CAN_IT_RQCP1                CAN_IT_TME
+#define CAN_IT_RQCP2                CAN_IT_TME
+#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define VLAN_TAG                ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR              0x00000100U
+#define ETH_MMCRIR             0x00000104U
+#define ETH_MMCTIR             0x00000108U
+#define ETH_MMCRIMR            0x0000010CU
+#define ETH_MMCTIMR            0x00000110U
+#define ETH_MMCTGFSCCR         0x0000014CU
+#define ETH_MMCTGFMSCCR        0x00000150U
+#define ETH_MMCTGFCR           0x00000168U
+#define ETH_MMCRFCECR          0x00000194U
+#define ETH_MMCRFAECR          0x00000198U
+#define ETH_MMCRGUFCR          0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF             DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
+
+/**
+  * @}
+  */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
+#define CM_RGB888               DMA2D_INPUT_RGB888
+#define CM_RGB565               DMA2D_INPUT_RGB565
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
+#define CM_L8                   DMA2D_INPUT_L8
+#define CM_AL44                 DMA2D_INPUT_AL44
+#define CM_AL88                 DMA2D_INPUT_AL88
+#define CM_L4                   DMA2D_INPUT_L4
+#define CM_A8                   DMA2D_INPUT_A8
+#define CM_A4                   DMA2D_INPUT_A4
+/**
+  * @}
+  */
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7) || defined(STM32U5)
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+  * @{
+  */
+#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+                                                                        for compatibility with legacy code */
+/**
+  * @}
+  */
+
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 || STM32U5 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr     HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT  HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
+
+/**
+  * @}
+  */
+
+#if !defined(STM32F2)
+/** @defgroup HASH_alias HASH API alias
+  * @{
+  */
+#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< Redirection for compatibility with legacy code */
+/**
+  *
+  * @}
+  */
+#endif /* STM32F2 */
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
+
+/**
+  * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
+                                                                 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+/**
+  * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
+#define CR_PMODE_BB                                   CR_VOS_BB
+
+#define DBP_BitNumber                                 DBP_BIT_NUMBER
+#define PVDE_BitNumber                                PVDE_BIT_NUMBER
+#define PMODE_BitNumber                               PMODE_BIT_NUMBER
+#define EWUP_BitNumber                                EWUP_BIT_NUMBER
+#define FPDS_BitNumber                                FPDS_BIT_NUMBER
+#define ODEN_BitNumber                                ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
+#define BRE_BitNumber                                 BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
+
+/**
+  * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError                                TIM_DMAError
+#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define AES_IT_CC                      CRYP_IT_CC
+#define AES_IT_ERR                     CRYP_IT_ERR
+#define AES_FLAG_CCF                   CRYP_FLAG_CCF
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
+#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
+#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1                                   ADC_SQR1
+#define __HAL_ADC_SMPR1                                  ADC_SMPR1
+#define __HAL_ADC_SMPR2                                  ADC_SMPR2
+#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR                                   ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32F3)
+#define COMP_START                                       __HAL_COMP_ENABLE
+#define COMP_STOP                                        __HAL_COMP_DISABLE
+#define COMP_LOCK                                        __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro             */
+/*       is COMP_FLAG_LOCK.                                                   */
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
+/*       argument.                                                            */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+  * @}
+  */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+                           ((WAVE) == DAC_WAVE_NOISE)|| \
+                           ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_WRPAREA          IS_OB_WRPAREA
+#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE        IS_FLASH_TYPEERASE
+#define IS_NBSECTORS        IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
+#define __HAL_I2C_SPEED                 I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+#define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+  * @{
+  */
+
+#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
+                                         )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection               SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection                 Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14                RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS
+#define RCC_IT_CSSHSE               RCC_IT_CSS
+
+#define RCC_PLLMUL_3                RCC_PLL_MUL3
+#define RCC_PLLMUL_4                RCC_PLL_MUL4
+#define RCC_PLLMUL_6                RCC_PLL_MUL6
+#define RCC_PLLMUL_8                RCC_PLL_MUL8
+#define RCC_PLLMUL_12               RCC_PLL_MUL12
+#define RCC_PLLMUL_16               RCC_PLL_MUL16
+#define RCC_PLLMUL_24               RCC_PLL_MUL24
+#define RCC_PLLMUL_32               RCC_PLL_MUL32
+#define RCC_PLLMUL_48               RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2                RCC_PLL_DIV2
+#define RCC_PLLDIV_3                RCC_PLL_DIV3
+#define RCC_PLLDIV_4                RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV               RCC_MCODIV_1
+#define RCC_MCO_DIV1                RCC_MCODIV_1
+#define RCC_MCO_DIV2                RCC_MCODIV_2
+#define RCC_MCO_DIV4                RCC_MCODIV_4
+#define RCC_MCO_DIV8                RCC_MCODIV_8
+#define RCC_MCO_DIV16               RCC_MCODIV_16
+#define RCC_MCO_DIV32               RCC_MCODIV_32
+#define RCC_MCO_DIV64               RCC_MCODIV_64
+#define RCC_MCO_DIV128              RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB            RCC_CR_HSION_BB
+#define CR_CSSON_BB            RCC_CR_CSSON_BB
+#define CR_PLLON_BB            RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB            RCC_CR_MSION_BB
+#define CSR_LSION_BB           RCC_CSR_LSION_BB
+#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB            RCC_CR_HSEON_BB
+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection         Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL  RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL  RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE           __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE           __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear      __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear     __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear     __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear      __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear      __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear      __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear      __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection            IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48                   RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48              RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2               RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1               RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK               RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE            __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE          __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET          __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#else
+#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+                                                       (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
+                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif   /* STM32F1 */
+
+#define IS_ALARM                                  IS_RTC_ALARM
+#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
+#define IS_TAMPER                                 IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
+
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
+#define eMMC_HIGH_VOLTAGE_RANGE     EMMC_HIGH_VOLTAGE_RANGE
+#define eMMC_DUAL_VOLTAGE_RANGE     EMMC_DUAL_VOLTAGE_RANGE
+#define eMMC_LOW_VOLTAGE_RANGE      EMMC_LOW_VOLTAGE_RANGE
+
+#define SDMMC_NSpeed_CLK_DIV        SDMMC_NSPEED_CLK_DIV
+#define SDMMC_HSpeed_CLK_DIV        SDMMC_HSPEED_CLK_DIV
+#endif
+
+#if defined(STM32F4) || defined(STM32F2)
+#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define  SDMMC1_IRQn                SDIO_IRQn
+#define  SDMMC1_IRQHandler          SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
+#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
+#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
+#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
+#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
+#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
+#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
+#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
+#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
+#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
+#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
+#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
+#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
+#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
+#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
+#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
+#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
+#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define  SDIO_IRQn                  SDMMC1_IRQn
+#define  SDIO_IRQHandler            SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
+#define __USART_ENABLE                  __HAL_USART_ENABLE
+#define __USART_DISABLE                 __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16               0x00000000U
+#define USART_OVERSAMPLING_8                USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE                     SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32F7)
+#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
+#endif /* STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
+
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h
new file mode 100644
index 0000000..60a335b
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h
@@ -0,0 +1,624 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_H
+#define STM32G4xx_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_conf.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL HAL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+#define HAL_TICK_FREQ_10HZ         100U
+#define HAL_TICK_FREQ_100HZ        10U
+#define HAL_TICK_FREQ_1KHZ         1U
+#define HAL_TICK_FREQ_DEFAULT      HAL_TICK_FREQ_1KHZ
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSCFG_BootMode Boot Mode
+  * @{
+  */
+#define SYSCFG_BOOT_MAINFLASH          0x00000000U
+#define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_MEMMEMRMP_MODE_0
+
+#if defined (FMC_BANK1)
+#define SYSCFG_BOOT_FMC                SYSCFG_MEMMEMRMP_MODE_1
+#endif /* FMC_BANK1 */
+
+#define SYSCFG_BOOT_SRAM               (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0)
+
+#if defined (QUADSPI)
+#define SYSCFG_BOOT_QUADSPI            (SYSCFG_MEMMEMRMP_MODE_2 | SYSCFG_MEMMEMRMP_MODE_1)
+#endif /* QUADSPI */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
+  * @{
+  */
+#define SYSCFG_IT_FPU_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Floating Point Unit Invalid operation Interrupt */
+#define SYSCFG_IT_FPU_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Floating Point Unit Divide-by-zero Interrupt */
+#define SYSCFG_IT_FPU_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Floating Point Unit Underflow Interrupt */
+#define SYSCFG_IT_FPU_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Floating Point Unit Overflow Interrupt */
+#define SYSCFG_IT_FPU_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Floating Point Unit Input denormal Interrupt */
+#define SYSCFG_IT_FPU_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Floating Point Unit Inexact Interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_CCMSRAMWRP CCM Write protection
+  * @{
+  */
+#define SYSCFG_CCMSRAMWRP_PAGE0          SYSCFG_SWPR_PAGE0  /*!< CCMSRAM Write protection page 0 */
+#define SYSCFG_CCMSRAMWRP_PAGE1          SYSCFG_SWPR_PAGE1  /*!< CCMSRAM Write protection page 1 */
+#define SYSCFG_CCMSRAMWRP_PAGE2          SYSCFG_SWPR_PAGE2  /*!< CCMSRAM Write protection page 2 */
+#define SYSCFG_CCMSRAMWRP_PAGE3          SYSCFG_SWPR_PAGE3  /*!< CCMSRAM Write protection page 3 */
+#define SYSCFG_CCMSRAMWRP_PAGE4          SYSCFG_SWPR_PAGE4  /*!< CCMSRAM Write protection page 4 */
+#define SYSCFG_CCMSRAMWRP_PAGE5          SYSCFG_SWPR_PAGE5  /*!< CCMSRAM Write protection page 5 */
+#define SYSCFG_CCMSRAMWRP_PAGE6          SYSCFG_SWPR_PAGE6  /*!< CCMSRAM Write protection page 6 */
+#define SYSCFG_CCMSRAMWRP_PAGE7          SYSCFG_SWPR_PAGE7  /*!< CCMSRAM Write protection page 7 */
+#define SYSCFG_CCMSRAMWRP_PAGE8          SYSCFG_SWPR_PAGE8  /*!< CCMSRAM Write protection page 8 */
+#define SYSCFG_CCMSRAMWRP_PAGE9          SYSCFG_SWPR_PAGE9  /*!< CCMSRAM Write protection page 9 */
+#define SYSCFG_CCMSRAMWRP_PAGE10         SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
+#define SYSCFG_CCMSRAMWRP_PAGE11         SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
+#define SYSCFG_CCMSRAMWRP_PAGE12         SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
+#define SYSCFG_CCMSRAMWRP_PAGE13         SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
+#define SYSCFG_CCMSRAMWRP_PAGE14         SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
+#define SYSCFG_CCMSRAMWRP_PAGE15         SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
+#define SYSCFG_CCMSRAMWRP_PAGE16         SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
+#define SYSCFG_CCMSRAMWRP_PAGE17         SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
+#define SYSCFG_CCMSRAMWRP_PAGE18         SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
+#define SYSCFG_CCMSRAMWRP_PAGE19         SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
+#define SYSCFG_CCMSRAMWRP_PAGE20         SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
+#define SYSCFG_CCMSRAMWRP_PAGE21         SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
+#define SYSCFG_CCMSRAMWRP_PAGE22         SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
+#define SYSCFG_CCMSRAMWRP_PAGE23         SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
+#define SYSCFG_CCMSRAMWRP_PAGE24         SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
+#define SYSCFG_CCMSRAMWRP_PAGE25         SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
+#define SYSCFG_CCMSRAMWRP_PAGE26         SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
+#define SYSCFG_CCMSRAMWRP_PAGE27         SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
+#define SYSCFG_CCMSRAMWRP_PAGE28         SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
+#define SYSCFG_CCMSRAMWRP_PAGE29         SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
+#define SYSCFG_CCMSRAMWRP_PAGE30         SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
+#define SYSCFG_CCMSRAMWRP_PAGE31         SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
+
+/**
+  * @}
+  */
+
+#if defined(VREFBUF)
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+  * @{
+  */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0  0x00000000U /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS_0      /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V)   */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2  VREFBUF_CSR_VRS_1      /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V)   */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+  * @{
+  */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  0x00000000U       /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ       /*!< VREF_plus pin is high impedance */
+
+/**
+  * @}
+  */
+#endif /* VREFBUF */
+
+/** @defgroup SYSCFG_flags_definition Flags
+  * @{
+  */
+
+#define SYSCFG_FLAG_SRAM_PE             SYSCFG_CFGR2_SPF       /*!< SRAM parity error (first 32kB of SRAM1 + CCM SRAM) */
+#define SYSCFG_FLAG_CCMSRAM_BUSY        SYSCFG_SCSR_CCMBSY     /*!< CCMSRAM busy by erase operation */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+  * @{
+  */
+
+/** @brief  Fast-mode Plus driving capability on a specific GPIO
+  */
+#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
+#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
+#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
+#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
+  * @{
+  */
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode
+  */
+#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM5()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_I2C3_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_LPTIM1_STOP */
+
+#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_TIM1_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM8()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_TIM8_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_TIM15_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_TIM16_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_TIM17_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM20_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM20()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM20()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_TIM20_STOP */
+
+#if defined(DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_HRTIM1()         SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HRTIM1()       CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
+#endif /* DBGMCU_APB2FZ_DBG_HRTIM1_STOP */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+  * @{
+  */
+
+/** @brief  Main Flash memory mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH()       CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
+
+/** @brief  System Flash memory mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
+
+/** @brief  Embedded SRAM mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM()        MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
+
+#if defined (FMC_BANK1)
+/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FMC()         MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
+#endif /* FMC_BANK1 */
+
+#if defined (QUADSPI)
+/** @brief  QUADSPI mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()     MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
+#endif /* QUADSPI */
+
+/**
+  * @brief  Return the boot mode as configured by user.
+  * @retval The boot mode as configured by user. The returned value can be one
+  *         of the following values:
+  *           @arg @ref SYSCFG_BOOT_MAINFLASH
+  *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH
+  *           @arg @ref SYSCFG_BOOT_FMC (*)
+  *           @arg @ref SYSCFG_BOOT_QUADSPI (*)
+  *           @arg @ref SYSCFG_BOOT_SRAM
+  * @note   (*) availability depends on devices
+  */
+#define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
+
+/** @brief  CCMSRAM page write protection enable macro
+  * @param __CCMSRAMWRP__: This parameter can be a value of @ref SYSCFG_CCMSRAMWRP
+  * @note   write protection can only be disabled by a system reset
+  * @retval None
+  */
+/* Legacy define */
+#define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE   __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE
+#define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__)    do {assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__)));\
+                                                                     SET_BIT(SYSCFG->SWPR,(__CCMSRAMWRP__));\
+                                                                   }while(0)
+
+/** @brief  CCMSRAM page write protection unlock prior to erase
+  * @note   Writing a wrong key reactivates the write protection
+  */
+#define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK()    do {SYSCFG->SKR = 0xCA;\
+                                                  SYSCFG->SKR = 0x53;\
+                                                }while(0)
+
+/** @brief  CCMSRAM erase
+  * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end of erase
+  */
+#define __HAL_SYSCFG_CCMSRAM_ERASE()         SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER)
+
+/** @brief  Floating Point Unit interrupt enable/disable macros
+  * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
+  */
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+                                                                 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
+                                                               }while(0)
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
+                                                               }while(0)
+
+/** @brief  SYSCFG Break ECC lock.
+  *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_ECC_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
+
+/** @brief  SYSCFG Break Cortex-M4 Lockup lock.
+  *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
+
+/** @brief  SYSCFG Break PVD lock.
+  *         Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
+
+/** @brief  SYSCFG Break SRAM parity lock.
+  *         Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM SRAM) signal connection to TIM1/8/15/16/17 Break input.
+  * @note   The selected configuration is locked and can be unlocked by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
+
+/** @brief  Check SYSCFG flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref SYSCFG_FLAG_SRAM_PE   SRAM Parity Error Flag
+  *            @arg @ref SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
+                                                & (__FLAG__))!= 0U) ? 1U : 0U)
+
+/** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.
+  */
+#define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
+
+/** @brief  Fast-mode Plus driving capability enable/disable macros
+  * @param __FASTMODEPLUS__: This parameter can be a value of :
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
+  */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
+  * @{
+  */
+
+#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
+
+#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC)           || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY)    || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
+
+#if (CCMSRAM_SIZE == 0x00008000UL) || (CCMSRAM_SIZE == 0x00004000UL)
+#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__)  ((__PAGE__) > 0U)
+#elif (CCMSRAM_SIZE == 0x00002800UL)
+#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__)  (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU))
+#endif /* CCMSRAM_SIZE */
+
+#if defined(VREFBUF)
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2))
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+#endif /* VREFBUF */
+
+#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+#elif defined(SYSCFG_FASTMODEPLUS_PB8)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
+#elif defined(SYSCFG_FASTMODEPLUS_PB9)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+#else
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
+#endif /* SYSCFG_FASTMODEPLUS_PB */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and Configuration functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
+uint32_t HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group3
+  * @{
+  */
+
+/* DBGMCU Peripheral Control functions  *****************************************/
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+
+/**
+  * @}
+  */
+
+/* Exported variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern uint32_t uwTickFreq;
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group4
+  * @{
+  */
+
+/* SYSCFG Control functions  ****************************************************/
+void HAL_SYSCFG_CCMSRAMErase(void);
+void HAL_SYSCFG_EnableMemorySwappingBank(void);
+void HAL_SYSCFG_DisableMemorySwappingBank(void);
+
+#if defined(VREFBUF)
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+#endif /* VREFBUF */
+
+void HAL_SYSCFG_EnableIOSwitchBooster(void);
+void HAL_SYSCFG_DisableIOSwitchBooster(void);
+void HAL_SYSCFG_EnableIOSwitchVDD(void);
+void HAL_SYSCFG_DisableIOSwitchVDD(void);
+
+void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h
new file mode 100644
index 0000000..f0114a3
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h
@@ -0,0 +1,2034 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_ADC_H
+#define STM32G4xx_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/* Include low level driver */
+#include "stm32g4xx_ll_adc.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  ADC group regular oversampling structure definition
+  */
+typedef struct
+{
+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+
+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+
+  uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
+
+  uint32_t OversamplingStopReset;         /*!< Selects the regular oversampling mode.
+                                               The oversampling is either temporary stopped or reset upon an injected
+                                               sequence interruption.
+                                               If oversampling is enabled on both regular and injected groups, this parameter
+                                               is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
+                                               (the oversampling buffer is zeroed during injection sequence).
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
+
+} ADC_OversamplingTypeDef;
+
+/**
+  * @brief  Structure definition of ADC instance and ADC group regular.
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
+  *            GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait.
+  *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
+  *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, SamplingMode.
+  * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled
+  *          - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
+  *          - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter
+  *         (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
+                                       This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
+                                       Note: The ADC clock configuration is common to all ADC instances.
+                                       Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
+                                             AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
+                                       Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
+                                             if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
+                                             must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
+                                       Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
+                                       Note: This parameter can be modified only if all ADC instances are disabled. */
+
+  uint32_t Resolution;            /*!< Configure the ADC resolution.
+                                       This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
+
+  uint32_t DataAlign;             /*!< Specify ADC data alignment in conversion data register (right or left).
+                                       Refer to reference manual for alignments formats versus resolutions.
+                                       This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
+
+  uint32_t GainCompensation;      /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion data, based on following formula:
+                                           DATA = DATA(raw) * (gain compensation coef) / 4096
+                                       2.12 bit format, unsigned: 2 bits exponents / 12 bits mantissa
+                                        Gain step is 1/4096 = 0.000244
+                                        Gain range is 0.0000 to 3.999756
+                                       This parameter value can be
+                                        0           Gain compensation will be disabled and coefficient set to 0
+                                        1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified value
+
+                                       Note: Gain compensation when enabled is applied to all channels. */
+
+  uint32_t ScanConvMode;          /*!< Configure the sequencer of ADC groups regular and injected.
+                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+                                       If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
+                                                    Scan direction is upward: from rank 1 to rank 'n'.
+                                       This parameter can be a value of @ref ADC_Scan_mode */
+
+  uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
+                                       This parameter can be a value of @ref ADC_EOCSelection. */
+
+  FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
+                                       conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
+                                       using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
+                                       This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
+                                       for low frequency applications.
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
+                                             Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
+                                             Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
+                                             use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
+                                             (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
+
+  FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
+                                       after the first ADC conversion start trigger occurred (software start or external trigger).
+                                       This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t NbrOfConversion;       /*!< Specify the number of ranks that will be converted within the regular group sequencer.
+                                       To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 16.
+                                       Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
+                                       continuous mode or external trigger that could launch a conversion). */
+
+  FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
+                                       (main sequence subdivided in successive parts).
+                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+                                       This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
+                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+
+  uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion start.
+                                       If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
+                                       This parameter can be a value of @ref ADC_regular_external_trigger_source.
+                                       Caution: external trigger source is common to all ADC instances. */
+
+  uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start.
+                                       If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
+                                       This parameter can be a value of @ref ADC_regular_external_trigger_edge */
+
+  uint32_t SamplingMode;          /*!< Select the sampling mode to be used for ADC group regular conversion.
+                                       This parameter can be a value of @ref ADC_regular_sampling_mode */
+
+  FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
+                                       or in continuous mode (DMA transfer unlimited, whatever number of conversions).
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
+
+  uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
+                                       This parameter applies to ADC group regular only.
+                                       This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
+                                       Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
+                                       end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
+                                       HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
+                                       Note: Error reporting with respect to the conversion mode:
+                                             - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
+                                               overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
+                                             - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
+
+  FunctionalState OversamplingMode;       /*!< Specify whether the oversampling feature is enabled or disabled.
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
+
+  ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.
+                                               Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
+
+} ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of ADC channel for regular group
+  * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
+  *          - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
+  *          - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
+  *         on the fly).
+  */
+typedef struct
+{
+  uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
+                                        This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+                                        Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
+
+  uint32_t Rank;                   /*!< Specify the rank in the regular group sequencer.
+                                        This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
+                                        Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
+                                        the new channel setting (or parameter number of conversions adjusted) */
+
+  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
+                                        Unit: ADC clock cycles
+                                        Conversion time is the addition of sampling time and processing time
+                                        (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+                                        This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
+                                        Caution: This parameter applies to a channel that can be used into regular and/or injected group.
+                                                 It overwrites the last setting.
+                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                              Refer to device datasheet for timings values. */
+
+  uint32_t SingleDiff;             /*!< Select single-ended or differential input.
+                                        In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
+                                                              Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
+                                        This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
+                                        Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
+                                                 It overwrites the last setting.
+                                        Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
+                                        Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
+                                        Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+                                              If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
+                                        of another parameter update on the fly) */
+
+  uint32_t OffsetNumber;           /*!< Select the offset number
+                                        This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
+                                        Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
+
+  uint32_t Offset;                 /*!< Define the offset to be applied on the raw converted data.
+                                        Offset value must be a positive number.
+                                        Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
+                                        0x3FF, 0xFF or 0x3F respectively.
+                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
+                                              without continuous mode or external trigger that could launch a conversion). */
+
+  uint32_t OffsetSign;                /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data.
+                                        This parameter can be a value of @ref ADCEx_OffsetSign.
+                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
+                                              without continuous mode or external trigger that could launch a conversion). */
+  FunctionalState OffsetSaturation;   /*!< Define if the offset should be saturated upon under or over flow.
+                                        This parameter value can be ENABLE or DISABLE.
+                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
+                                              without continuous mode or external trigger that could launch a conversion). */
+
+} ADC_ChannelConfTypeDef;
+
+/**
+  * @brief  Structure definition of ADC analog watchdog
+  * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
+  *          - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and injected groups.
+  */
+typedef struct
+{
+  uint32_t WatchdogNumber;    /*!< Select which ADC analog watchdog is monitoring the selected channel.
+                                   For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+                                   This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
+
+  uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.
+                                   For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
+                                   This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+
+  uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
+                                   For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
+                                   This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
+
+  FunctionalState ITMode;     /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
+                                   This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
+                                   between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
+                                         the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
+                                   Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+                                         impacted: the comparison of analog watchdog thresholds is done on
+                                         oversampling final computation (after ratio and shift application):
+                                         ADC data register bitfield [15:4] (12 most significant bits). */
+
+  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
+                                   between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
+                                         the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
+                                   Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+                                         impacted: the comparison of analog watchdog thresholds is done on
+                                         oversampling final computation (after ratio and shift application):
+                                         ADC data register bitfield [15:4] (12 most significant bits). */
+
+  uint32_t FilteringConfig;   /*!< Specify whether filtering should be use and the number of samples to consider.
+                                   Before setting flag or raising interrupt, analog watchdog can wait to have several
+                                   consecutive out-of-window samples. This parameter allows to configure this number.
+                                   This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE.
+                                   This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */
+} ADC_AnalogWDGConfTypeDef;
+
+/**
+  * @brief  ADC group injected contexts queue configuration
+  * @note   Structure intended to be used only through structure "ADC_HandleTypeDef"
+  */
+typedef struct
+{
+  uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each
+                                              HAL_ADCEx_InjectedConfigChannel() call to finally initialize
+                                              JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
+
+  uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */
+} ADC_InjectionConfigTypeDef;
+
+/** @defgroup ADC_States ADC States
+  * @{
+  */
+
+/**
+  * @brief  HAL ADC state machine: ADC states definition (bitfields)
+  * @note   ADC state machine is managed by bitfields, state must be compared
+  *         with bit by bit.
+  *         For example:
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+  */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET             (0x00000000UL)   /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY             (0x00000001UL)   /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002UL)   /*!< ADC is busy due to an internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT           (0x00000004UL)   /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010UL)   /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020UL)   /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA         (0x00000040UL)   /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY          (0x00000100UL)   /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
+                                                              external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC           (0x00000200UL)   /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR           (0x00000400UL)   /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 series: End Of Sampling flag raised  */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY          (0x00001000UL)   /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
+                                                              external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC           (0x00002000UL)   /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF         (0x00004000UL)   /*!< Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1              (0x00010000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2              (0x00020000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3              (0x00040000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000UL)   /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  ADC handle Structure definition
+  */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+{
+  ADC_TypeDef                   *Instance;              /*!< Register base address */
+  ADC_InitTypeDef               Init;                   /*!< ADC initialization parameters and regular conversions setting */
+  DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
+  HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
+  __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
+  __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
+  ADC_InjectionConfigTypeDef    InjectionConfig ;       /*!< ADC injected channel configuration build-up structure */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
+  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
+  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
+  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
+  void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete callback */
+  void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */
+  void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 2 callback */
+  void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 3 callback */
+  void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc);         /*!< ADC end of sampling callback */
+  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
+  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+} ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL ADC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
+  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
+  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
+  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
+  HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID       = 0x05U,  /*!< ADC group injected context queue overflow callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID   = 0x06U,  /*!< ADC analog watchdog 2 callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID   = 0x07U,  /*!< ADC analog watchdog 3 callback ID */
+  HAL_ADC_END_OF_SAMPLING_CB_ID         = 0x08U,  /*!< ADC end of sampling callback ID */
+  HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID          */
+  HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID        */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL ADC Callback pointer definition
+  */
+typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+  * @{
+  */
+#define HAL_ADC_ERROR_NONE              (0x00U)   /*!< No error                                    */
+#define HAL_ADC_ERROR_INTERNAL          (0x01U)   /*!< ADC peripheral internal error (problem of clocking,
+                                                       enable/disable, erroneous state, ...)       */
+#define HAL_ADC_ERROR_OVR               (0x02U)   /*!< Overrun error                               */
+#define HAL_ADC_ERROR_DMA               (0x04U)   /*!< DMA transfer error                          */
+#define HAL_ADC_ERROR_JQOVF             (0x08U)   /*!< Injected context queue overflow error       */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
+  * @{
+  */
+#define ADC_CLOCK_SYNC_PCLK_DIV1           (LL_ADC_CLOCK_SYNC_PCLK_DIV1)  /*!< ADC synchronous clock derived from AHB clock without prescaler */
+#define ADC_CLOCK_SYNC_PCLK_DIV2           (LL_ADC_CLOCK_SYNC_PCLK_DIV2)  /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4           (LL_ADC_CLOCK_SYNC_PCLK_DIV4)  /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+
+#define ADC_CLOCK_ASYNC_DIV1               (LL_ADC_CLOCK_ASYNC_DIV1)      /*!< ADC asynchronous clock without prescaler */
+#define ADC_CLOCK_ASYNC_DIV2               (LL_ADC_CLOCK_ASYNC_DIV2)      /*!< ADC asynchronous clock with prescaler division by 2   */
+#define ADC_CLOCK_ASYNC_DIV4               (LL_ADC_CLOCK_ASYNC_DIV4)      /*!< ADC asynchronous clock with prescaler division by 4   */
+#define ADC_CLOCK_ASYNC_DIV6               (LL_ADC_CLOCK_ASYNC_DIV6)      /*!< ADC asynchronous clock with prescaler division by 6   */
+#define ADC_CLOCK_ASYNC_DIV8               (LL_ADC_CLOCK_ASYNC_DIV8)      /*!< ADC asynchronous clock with prescaler division by 8   */
+#define ADC_CLOCK_ASYNC_DIV10              (LL_ADC_CLOCK_ASYNC_DIV10)     /*!< ADC asynchronous clock with prescaler division by 10  */
+#define ADC_CLOCK_ASYNC_DIV12              (LL_ADC_CLOCK_ASYNC_DIV12)     /*!< ADC asynchronous clock with prescaler division by 12  */
+#define ADC_CLOCK_ASYNC_DIV16              (LL_ADC_CLOCK_ASYNC_DIV16)     /*!< ADC asynchronous clock with prescaler division by 16  */
+#define ADC_CLOCK_ASYNC_DIV32              (LL_ADC_CLOCK_ASYNC_DIV32)     /*!< ADC asynchronous clock with prescaler division by 32  */
+#define ADC_CLOCK_ASYNC_DIV64              (LL_ADC_CLOCK_ASYNC_DIV64)     /*!< ADC asynchronous clock with prescaler division by 64  */
+#define ADC_CLOCK_ASYNC_DIV128             (LL_ADC_CLOCK_ASYNC_DIV128)    /*!< ADC asynchronous clock with prescaler division by 128 */
+#define ADC_CLOCK_ASYNC_DIV256             (LL_ADC_CLOCK_ASYNC_DIV256)    /*!< ADC asynchronous clock with prescaler division by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_RESOLUTION  ADC instance - Resolution
+  * @{
+  */
+#define ADC_RESOLUTION_12B                 (LL_ADC_RESOLUTION_12B)  /*!< ADC resolution 12 bits */
+#define ADC_RESOLUTION_10B                 (LL_ADC_RESOLUTION_10B)  /*!< ADC resolution 10 bits */
+#define ADC_RESOLUTION_8B                  (LL_ADC_RESOLUTION_8B)   /*!< ADC resolution  8 bits */
+#define ADC_RESOLUTION_6B                  (LL_ADC_RESOLUTION_6B)   /*!< ADC resolution  6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
+  * @{
+  */
+#define ADC_DATAALIGN_RIGHT                (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define ADC_DATAALIGN_LEFT                 (LL_ADC_DATA_ALIGN_LEFT)       /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode
+  * @{
+  */
+#define ADC_SCAN_DISABLE         (0x00000000UL)       /*!< Scan mode disabled */
+#define ADC_SCAN_ENABLE          (0x00000001UL)       /*!< Scan mode enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
+  * @{
+  */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_SOFTWARE_START            (LL_ADC_REG_TRIG_SOFTWARE)                 /*!< ADC group regular conversion trigger internal: SW start. */
+#define ADC_EXTERNALTRIG_T1_TRGO      (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_CC1       (LL_ADC_REG_TRIG_EXT_TIM1_CH1)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_CC2       (LL_ADC_REG_TRIG_EXT_TIM1_CH2)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_CC3       (LL_ADC_REG_TRIG_EXT_TIM1_CH3)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_TRGO      (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_CC1       (LL_ADC_REG_TRIG_EXT_TIM2_CH1)             /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_CC2       (LL_ADC_REG_TRIG_EXT_TIM2_CH2)             /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_CC3       (LL_ADC_REG_TRIG_EXT_TIM2_CH3)             /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T3_TRGO      (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T3_CC1       (LL_ADC_REG_TRIG_EXT_TIM3_CH1)             /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T3_CC4       (LL_ADC_REG_TRIG_EXT_TIM3_CH4)             /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T4_TRGO      (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T4_CC1       (LL_ADC_REG_TRIG_EXT_TIM4_CH1)             /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T4_CC4       (LL_ADC_REG_TRIG_EXT_TIM4_CH4)             /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T6_TRGO      (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T7_TRGO      (LL_ADC_REG_TRIG_EXT_TIM7_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T8_TRGO      (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T8_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)           /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T8_CC1       (LL_ADC_REG_TRIG_EXT_TIM8_CH1)             /*!< ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T15_TRGO     (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)           /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T20_TRGO     (LL_ADC_REG_TRIG_EXT_TIM20_TRGO)           /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T20_TRGO2    (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)          /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T20_CC1      (LL_ADC_REG_TRIG_EXT_TIM20_CH1)            /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T20_CC2      (LL_ADC_REG_TRIG_EXT_TIM20_CH2)            /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T20_CC3      (LL_ADC_REG_TRIG_EXT_TIM20_CH3)            /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_HRTIM_TRG1   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)           /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_HRTIM_TRG2   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2)           /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_HRTIM_TRG3   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)           /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_HRTIM_TRG4   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4)           /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_HRTIM_TRG5   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5)           /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_HRTIM_TRG6   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6)           /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_HRTIM_TRG7   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7)           /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_HRTIM_TRG8   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8)           /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_HRTIM_TRG9   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9)           /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_HRTIM_TRG10  (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10)          /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_EXT_IT2      (LL_ADC_REG_TRIG_EXT_EXTI_LINE2)           /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_EXT_IT11     (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)          /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_LPTIM_OUT    (LL_ADC_REG_TRIG_EXT_LPTIM_OUT)            /*!< ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
+  * @{
+  */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000UL)                      /*!< Regular conversions hardware trigger detection disabled */
+#define ADC_EXTERNALTRIGCONVEDGE_RISING         (LL_ADC_REG_TRIG_EXT_RISING)        /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING        (LL_ADC_REG_TRIG_EXT_FALLING)       /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode
+  * @{
+  */
+#define ADC_SAMPLING_MODE_NORMAL                (0x00000000UL)      /*!< ADC conversions sampling phase duration is defined using  @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */
+#define ADC_SAMPLING_MODE_BULB                  (ADC_CFGR2_BULB)    /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
+                                                                                Note: First conversion is using minimal sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */
+#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED     (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events:
+                                                                                 Trigger rising edge  = start sampling
+                                                                                 Trigger falling edge = stop sampling and start conversion */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
+  * @{
+  */
+#define ADC_EOC_SINGLE_CONV         (ADC_ISR_EOC)                 /*!< End of unitary conversion flag  */
+#define ADC_EOC_SEQ_CONV            (ADC_ISR_EOS)                 /*!< End of sequence conversions flag    */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
+  * @{
+  */
+#define ADC_OVR_DATA_PRESERVED             (LL_ADC_REG_OVR_DATA_PRESERVED)    /*!< ADC group regular behavior in case of overrun: data preserved */
+#define ADC_OVR_DATA_OVERWRITTEN           (LL_ADC_REG_OVR_DATA_OVERWRITTEN)  /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
+  * @{
+  */
+#define ADC_REGULAR_RANK_1                 (LL_ADC_REG_RANK_1)  /*!< ADC group regular sequencer rank 1 */
+#define ADC_REGULAR_RANK_2                 (LL_ADC_REG_RANK_2)  /*!< ADC group regular sequencer rank 2 */
+#define ADC_REGULAR_RANK_3                 (LL_ADC_REG_RANK_3)  /*!< ADC group regular sequencer rank 3 */
+#define ADC_REGULAR_RANK_4                 (LL_ADC_REG_RANK_4)  /*!< ADC group regular sequencer rank 4 */
+#define ADC_REGULAR_RANK_5                 (LL_ADC_REG_RANK_5)  /*!< ADC group regular sequencer rank 5 */
+#define ADC_REGULAR_RANK_6                 (LL_ADC_REG_RANK_6)  /*!< ADC group regular sequencer rank 6 */
+#define ADC_REGULAR_RANK_7                 (LL_ADC_REG_RANK_7)  /*!< ADC group regular sequencer rank 7 */
+#define ADC_REGULAR_RANK_8                 (LL_ADC_REG_RANK_8)  /*!< ADC group regular sequencer rank 8 */
+#define ADC_REGULAR_RANK_9                 (LL_ADC_REG_RANK_9)  /*!< ADC group regular sequencer rank 9 */
+#define ADC_REGULAR_RANK_10                (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
+#define ADC_REGULAR_RANK_11                (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
+#define ADC_REGULAR_RANK_12                (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
+#define ADC_REGULAR_RANK_13                (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
+#define ADC_REGULAR_RANK_14                (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
+#define ADC_REGULAR_RANK_15                (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
+#define ADC_REGULAR_RANK_16                (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+  * @{
+  */
+#define ADC_SAMPLETIME_2CYCLES_5         (LL_ADC_SAMPLINGTIME_2CYCLES_5)    /*!< Sampling time 2.5 ADC clock cycles */
+#define ADC_SAMPLETIME_6CYCLES_5         (LL_ADC_SAMPLINGTIME_6CYCLES_5)    /*!< Sampling time 6.5 ADC clock cycles */
+#define ADC_SAMPLETIME_12CYCLES_5        (LL_ADC_SAMPLINGTIME_12CYCLES_5)   /*!< Sampling time 12.5 ADC clock cycles */
+#define ADC_SAMPLETIME_24CYCLES_5        (LL_ADC_SAMPLINGTIME_24CYCLES_5)   /*!< Sampling time 24.5 ADC clock cycles */
+#define ADC_SAMPLETIME_47CYCLES_5        (LL_ADC_SAMPLINGTIME_47CYCLES_5)   /*!< Sampling time 47.5 ADC clock cycles */
+#define ADC_SAMPLETIME_92CYCLES_5        (LL_ADC_SAMPLINGTIME_92CYCLES_5)   /*!< Sampling time 92.5 ADC clock cycles */
+#define ADC_SAMPLETIME_247CYCLES_5       (LL_ADC_SAMPLINGTIME_247CYCLES_5)  /*!< Sampling time 247.5 ADC clock cycles */
+#define ADC_SAMPLETIME_640CYCLES_5       (LL_ADC_SAMPLINGTIME_640CYCLES_5)  /*!< Sampling time 640.5 ADC clock cycles */
+#define ADC_SAMPLETIME_3CYCLES_5           (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_CHANNEL  ADC instance - Channel number
+  * @{
+  */
+/* Note: VrefInt, TempSensor and Vbat internal channels are not available on  */
+/*        all ADC instances (refer to Reference Manual).                      */
+#define ADC_CHANNEL_0                      (LL_ADC_CHANNEL_0)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
+#define ADC_CHANNEL_1                      (LL_ADC_CHANNEL_1)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
+#define ADC_CHANNEL_2                      (LL_ADC_CHANNEL_2)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
+#define ADC_CHANNEL_3                      (LL_ADC_CHANNEL_3)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
+#define ADC_CHANNEL_4                      (LL_ADC_CHANNEL_4)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
+#define ADC_CHANNEL_5                      (LL_ADC_CHANNEL_5)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
+#define ADC_CHANNEL_6                      (LL_ADC_CHANNEL_6)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
+#define ADC_CHANNEL_7                      (LL_ADC_CHANNEL_7)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
+#define ADC_CHANNEL_8                      (LL_ADC_CHANNEL_8)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
+#define ADC_CHANNEL_9                      (LL_ADC_CHANNEL_9)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
+#define ADC_CHANNEL_10                     (LL_ADC_CHANNEL_10)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define ADC_CHANNEL_11                     (LL_ADC_CHANNEL_11)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define ADC_CHANNEL_12                     (LL_ADC_CHANNEL_12)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define ADC_CHANNEL_13                     (LL_ADC_CHANNEL_13)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define ADC_CHANNEL_14                     (LL_ADC_CHANNEL_14)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define ADC_CHANNEL_15                     (LL_ADC_CHANNEL_15)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define ADC_CHANNEL_16                     (LL_ADC_CHANNEL_16)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define ADC_CHANNEL_17                     (LL_ADC_CHANNEL_17)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define ADC_CHANNEL_18                     (LL_ADC_CHANNEL_18)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define ADC_CHANNEL_VREFINT                (LL_ADC_CHANNEL_VREFINT)         /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */
+#define ADC_CHANNEL_TEMPSENSOR_ADC1        (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */
+#define ADC_CHANNEL_TEMPSENSOR_ADC5        (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */
+#define ADC_CHANNEL_VBAT                   (LL_ADC_CHANNEL_VBAT)            /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */
+#define ADC_CHANNEL_VOPAMP1                (LL_ADC_CHANNEL_VOPAMP1)         /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */
+#define ADC_CHANNEL_VOPAMP2                (LL_ADC_CHANNEL_VOPAMP2)         /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */
+#define ADC_CHANNEL_VOPAMP3_ADC2           (LL_ADC_CHANNEL_VOPAMP3_ADC2)    /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */
+#define ADC_CHANNEL_VOPAMP3_ADC3           (LL_ADC_CHANNEL_VOPAMP3_ADC3)    /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */
+#define ADC_CHANNEL_VOPAMP4                (LL_ADC_CHANNEL_VOPAMP4)         /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */
+#define ADC_CHANNEL_VOPAMP5                (LL_ADC_CHANNEL_VOPAMP5)         /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */
+#define ADC_CHANNEL_VOPAMP6                (LL_ADC_CHANNEL_VOPAMP6)         /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+  * @{
+  */
+#define ADC_ANALOGWATCHDOG_1               (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
+#define ADC_ANALOGWATCHDOG_2               (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
+#define ADC_ANALOGWATCHDOG_3               (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration
+  * @{
+  */
+#define ADC_AWD_FILTERING_NONE          (0x00000000UL)                                                /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_2SAMPLES      ((ADC_TR1_AWDFILT_0))                                         /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_3SAMPLES      ((ADC_TR1_AWDFILT_1))                                         /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_4SAMPLES      ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0))                     /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_5SAMPLES      ((ADC_TR1_AWDFILT_2))                                         /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_6SAMPLES      ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0))                     /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_7SAMPLES      ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1))                     /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_8SAMPLES      ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
+  * @{
+  */
+#define ADC_ANALOGWATCHDOG_NONE                 (0x00000000UL)                                          /*!< No analog watchdog selected                                             */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG           (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)                    /*!< Analog watchdog applied to a regular group single channel               */
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC         (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)                   /*!< Analog watchdog applied to an injected group single channel             */
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */
+#define ADC_ANALOGWATCHDOG_ALL_REG              (ADC_CFGR_AWD1EN)                                       /*!< Analog watchdog applied to regular group all channels                   */
+#define ADC_ANALOGWATCHDOG_ALL_INJEC            (ADC_CFGR_JAWD1EN)                                      /*!< Analog watchdog applied to injected group all channels                  */
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC         (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)                    /*!< Analog watchdog applied to regular and injected groups all channels     */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_RATIO  Oversampling - Ratio
+  * @{
+  */
+#define ADC_OVERSAMPLING_RATIO_2           (LL_ADC_OVS_RATIO_2)   /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_4           (LL_ADC_OVS_RATIO_4)   /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_8           (LL_ADC_OVS_RATIO_8)   /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_16          (LL_ADC_OVS_RATIO_16)  /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_32          (LL_ADC_OVS_RATIO_32)  /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_64          (LL_ADC_OVS_RATIO_64)  /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_128         (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_256         (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_SHIFT  Oversampling - Data shift
+  * @{
+  */
+#define ADC_RIGHTBITSHIFT_NONE             (LL_ADC_OVS_SHIFT_NONE)    /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_1                (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_2                (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_3                (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_4                (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_5                (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_6                (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_7                (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_8                (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
+  * @{
+  */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER   (LL_ADC_OVS_REG_CONT)          /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER    (LL_ADC_OVS_REG_DISCONT)       /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG  Oversampling - Oversampling scope for ADC group regular
+  * @{
+  */
+#define ADC_REGOVERSAMPLING_CONTINUED_MODE    (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */
+#define ADC_REGOVERSAMPLING_RESUMED_MODE      (LL_ADC_OVS_GRP_REGULAR_RESUMED)   /*!< Oversampling buffer zeroed during injection sequence     */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Event_type ADC Event type
+  * @{
+  */
+#define ADC_EOSMP_EVENT          (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
+#define ADC_AWD1_EVENT           (ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
+#define ADC_AWD2_EVENT           (ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
+#define ADC_AWD3_EVENT           (ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
+#define ADC_OVR_EVENT            (ADC_FLAG_OVR)   /*!< ADC overrun event */
+#define ADC_JQOVF_EVENT          (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
+/**
+  * @}
+  */
+#define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+  * @{
+  */
+#define ADC_IT_RDY           ADC_IER_ADRDYIE    /*!< ADC Ready interrupt source */
+#define ADC_IT_EOSMP         ADC_IER_EOSMPIE    /*!< ADC End of sampling interrupt source */
+#define ADC_IT_EOC           ADC_IER_EOCIE      /*!< ADC End of regular conversion interrupt source */
+#define ADC_IT_EOS           ADC_IER_EOSIE      /*!< ADC End of regular sequence of conversions interrupt source */
+#define ADC_IT_OVR           ADC_IER_OVRIE      /*!< ADC overrun interrupt source */
+#define ADC_IT_JEOC          ADC_IER_JEOCIE     /*!< ADC End of injected conversion interrupt source */
+#define ADC_IT_JEOS          ADC_IER_JEOSIE     /*!< ADC End of injected sequence of conversions interrupt source */
+#define ADC_IT_AWD1          ADC_IER_AWD1IE     /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
+#define ADC_IT_AWD2          ADC_IER_AWD2IE     /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
+#define ADC_IT_AWD3          ADC_IER_AWD3IE     /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
+#define ADC_IT_JQOVF         ADC_IER_JQOVFIE    /*!< ADC Injected Context Queue Overflow interrupt source */
+
+#define ADC_IT_AWD           ADC_IT_AWD1        /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+  * @{
+  */
+#define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
+#define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
+#define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */
+#define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
+#define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
+#define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
+#define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+  * @{
+  */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+  * @brief Return resolution bits in CFGR register RES[1:0] field.
+  * @param __HANDLE__ ADC handle
+  * @retval Value of bitfield RES in CFGR register.
+  */
+#define ADC_GET_RESOLUTION(__HANDLE__)                                         \
+  (LL_ADC_GetResolution((__HANDLE__)->Instance))
+
+/**
+  * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+  * @brief Simultaneously clear and set specific bits of the handle State.
+  * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+  *        the first parameter is the ADC handle State, the second parameter is the
+  *        bit field to clear, the third and last parameter is the bit field to set.
+  * @retval None
+  */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+  * @brief Verify that a given value is aligned with the ADC resolution range.
+  * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
+  * @param __ADC_VALUE__ value checked against the resolution.
+  * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
+  */
+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
+  ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
+
+/**
+  * @brief Verify the length of the scheduled regular conversions group.
+  * @param __LENGTH__ number of programmed conversions.
+  * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
+  */
+#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
+
+
+/**
+  * @brief Verify the number of scheduled regular conversions in discontinuous mode.
+  * @param NUMBER number of scheduled regular conversions in discontinuous mode.
+  * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)
+  */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
+
+
+/**
+  * @brief Verify the ADC clock setting.
+  * @param __ADC_CLOCK__ programmed ADC clock.
+  * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
+  */
+#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
+
+/**
+  * @brief Verify the ADC resolution setting.
+  * @param __RESOLUTION__ programmed ADC resolution.
+  * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+  */
+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B)    )
+
+/**
+  * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
+  * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
+  * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+  */
+#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
+                                                    ((__RESOLUTION__) == ADC_RESOLUTION_6B)   )
+
+/**
+  * @brief Verify the ADC converted data alignment.
+  * @param __ALIGN__ programmed ADC converted data alignment.
+  * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
+  */
+#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
+                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT)    )
+
+/**
+  * @brief Verify the ADC gain compensation.
+  * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient.
+  * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid)
+  */
+#define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL)
+
+/**
+  * @brief Verify the ADC scan mode.
+  * @param __SCAN_MODE__ programmed ADC scan mode.
+  * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
+  */
+#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
+                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )
+
+/**
+  * @brief Verify the ADC edge trigger setting for regular group.
+  * @param __EDGE__ programmed ADC edge trigger setting.
+  * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+  */
+#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
+
+/**
+  * @brief Verify the ADC regular conversions external trigger.
+  * @param __HANDLE__ ADC handle
+  * @param __REGTRIG__ programmed ADC regular conversions external trigger.
+  * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2)       || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10)     || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
+                                                 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2)       || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3)       || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)))    || \
+                                                 ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2)    || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4)    || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2)))     || \
+                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2)       || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
+                                                 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2)       || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3)       || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)))    || \
+                                                 ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2)))     || \
+                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )
+#elif defined(STM32G471xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
+                                                 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)))    || \
+                                                 ((((__HANDLE__)->Instance == ADC3)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2)))     || \
+                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)        || \
+                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2)       || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
+                                                 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2)       || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3)       || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)))    || \
+                                                 (((__HANDLE__)->Instance == ADC3) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2)))     || \
+                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )
+#endif
+
+/**
+  * @brief Verify the ADC regular conversions external trigger.
+  * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger.
+  * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid)
+  */
+#define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL)          || \
+                                               ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB)            || \
+                                               ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED)  )
+
+/**
+  * @brief Verify the ADC regular conversions check for converted data availability.
+  * @param __EOC_SELECTION__ converted data availability check.
+  * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
+  */
+#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
+                                                 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)  )
+
+/**
+  * @brief Verify the ADC regular conversions overrun handling.
+  * @param __OVR__ ADC regular conversions overrun handling.
+  * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
+  */
+#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
+                                 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )
+
+/**
+  * @brief Verify the ADC conversions sampling time.
+  * @param __TIME__ ADC conversions sampling time.
+  * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
+  */
+#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
+                                      ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5)   || \
+                                      ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
+                                      ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
+                                      ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )
+
+/**
+  * @brief Verify the ADC regular channel setting.
+  * @param  __CHANNEL__ programmed ADC regular channel.
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )
+
+/**
+  * @}
+  */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Fixed timeout values for ADC conversion (including sampling time)        */
+/* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111        */
+/* Maximum conversion time is 12.5 + Maximum sampling time                  */
+/*                       or 12.5  + 640.5 = 653 ADC clock cycles            */
+/* Minimum ADC Clock frequency is 0.14 MHz                                  */
+/* Maximum conversion time is                                               */
+/*              653 / 0.14 MHz = 4.66 ms                                    */
+#define ADC_STOP_CONVERSION_TIMEOUT     ( 5UL)     /*!< ADC stop time-out value */
+
+/* Delay for temperature sensor stabilization time.                         */
+/* Maximum delay is 120us (refer device datasheet, parameter tSTART).       */
+/* Unit: us                                                                 */
+#define ADC_TEMPSENSOR_DELAY_US         (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+  * @{
+  */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user.                                                                */
+
+/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
+  * @{
+  */
+
+/** @brief  Reset ADC handle state.
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  do{                                                                          \
+    (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
+    (__HANDLE__)->MspInitCallback = NULL;                                      \
+    (__HANDLE__)->MspDeInitCallback = NULL;                                    \
+  } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @brief Enable ADC interrupt.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC Interrupt
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
+  *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
+  (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+  * @brief Disable ADC interrupt.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC Interrupt
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
+  *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
+  (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC interrupt source to check
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
+  *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
+  * @retval State of interruption (SET or RESET)
+  */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
+  (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief Check whether the specified ADC flag is set or not.
+  * @param __HANDLE__ ADC handle
+  * @param __FLAG__ ADC flag
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_FLAG_RDY     ADC Ready flag
+  *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
+  *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
+  *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
+  *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag
+  *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.
+  * @retval State of flag (TRUE or FALSE).
+  */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
+  ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief Clear the specified ADC flag.
+  * @param __HANDLE__ ADC handle
+  * @param __FLAG__ ADC flag
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_FLAG_RDY     ADC Ready flag
+  *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
+  *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
+  *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
+  *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag
+  *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.
+  * @retval None
+  */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
+  (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get ADC channel number in decimal format
+  *         from literals ADC_CHANNEL_x.
+  * @note   Example:
+  *           __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
+  *           will return decimal number "4".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned, either defined with number
+  *         or with bitfield (only one bit must be set).
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1                 (8)
+  *         @arg @ref ADC_CHANNEL_2                 (8)
+  *         @arg @ref ADC_CHANNEL_3                 (8)
+  *         @arg @ref ADC_CHANNEL_4                 (8)
+  *         @arg @ref ADC_CHANNEL_5                 (8)
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @retval Value between Min_Data=0 and Max_Data=18
+  */
+#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                           \
+  __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
+
+/**
+  * @brief  Helper macro to get ADC channel in literal format ADC_CHANNEL_x
+  *         from number in decimal format.
+  * @note   Example:
+  *           __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+  *           will return a data equivalent to "ADC_CHANNEL_4".
+  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1                 (8)
+  *         @arg @ref ADC_CHANNEL_2                 (8)
+  *         @arg @ref ADC_CHANNEL_3                 (8)
+  *         @arg @ref ADC_CHANNEL_4                 (8)
+  *         @arg @ref ADC_CHANNEL_5                 (8)
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                        \
+  __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
+
+/**
+  * @brief  Helper macro to determine whether the selected channel
+  *         corresponds to literal definitions of driver.
+  * @note   The different literal definitions of ADC channels are:
+  *         - ADC internal channel:
+  *           ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
+  *         - ADC external channel (channel connected to a GPIO pin):
+  *           ADC_CHANNEL_1, ADC_CHANNEL_2, ...
+  * @note   The channel parameter must be a value defined from literal
+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+  *         ADC_CHANNEL_TEMPSENSOR, ...),
+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
+  *         must not be a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1                 (8)
+  *         @arg @ref ADC_CHANNEL_2                 (8)
+  *         @arg @ref ADC_CHANNEL_3                 (8)
+  *         @arg @ref ADC_CHANNEL_4                 (8)
+  *         @arg @ref ADC_CHANNEL_5                 (8)
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+  */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                             \
+  __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
+
+/**
+  * @brief  Helper macro to convert a channel defined from parameter
+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+  *         ADC_CHANNEL_TEMPSENSOR, ...),
+  *         to its equivalent parameter definition of a ADC external channel
+  *         (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
+  * @note   The channel parameter can be, additionally to a value
+  *         defined from parameter definition of a ADC internal channel
+  *         (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
+  *         a value defined from parameter definition of
+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is returned
+  *         from ADC registers.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1                 (8)
+  *         @arg @ref ADC_CHANNEL_2                 (8)
+  *         @arg @ref ADC_CHANNEL_3                 (8)
+  *         @arg @ref ADC_CHANNEL_4                 (8)
+  *         @arg @ref ADC_CHANNEL_5                 (8)
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  */
+#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                    \
+  __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
+
+/**
+  * @brief  Helper macro to determine whether the internal channel
+  *         selected is available on the ADC instance selected.
+  * @note   The channel parameter must be a value defined from parameter
+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+  *         ADC_CHANNEL_TEMPSENSOR, ...),
+  *         must not be a value defined from parameter definition of
+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __ADC_INSTANCE__ ADC instance
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+  *         Value "1" if the internal channel selected is available on the ADC instance selected.
+  */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Helper macro to get the ADC multimode conversion data of ADC master
+  *         or ADC slave from raw value with both ADC conversion data concatenated.
+  * @note   This macro is intended to be used when multimode transfer by DMA
+  *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+  *         In this case the transferred data need to processed with this macro
+  *         to separate the conversion data of ADC master and ADC slave.
+  * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_MASTER
+  *         @arg @ref LL_ADC_MULTI_SLAVE
+  * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
+  __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Helper macro to select the ADC common instance
+  *         to which is belonging the selected ADC instance.
+  * @note   ADC common register instance can be used for:
+  *         - Set parameters common to several ADC instances
+  *         - Multimode (for devices with several ADC instances)
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @param  __ADCx__ ADC instance
+  * @retval ADC common register instance
+  */
+#define __HAL_ADC_COMMON_INSTANCE(__ADCx__)                                    \
+  __LL_ADC_COMMON_INSTANCE((__ADCx__))
+
+/**
+  * @brief  Helper macro to check if all ADC instances sharing the same
+  *         ADC common instance are disabled.
+  * @note   This check is required by functions with setting conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @note   On devices with only 1 ADC common instance, parameter of this macro
+  *         is useless and can be ignored (parameter kept for compatibility
+  *         with devices featuring several ADC common instances).
+  * @param  __ADCXY_COMMON__ ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value "0" if all ADC instances sharing the same ADC common instance
+  *         are disabled.
+  *         Value "1" if at least one ADC instance sharing the same ADC common instance
+  *         is enabled.
+  */
+#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
+
+/**
+  * @brief  Helper macro to define the ADC conversion data full-scale digital
+  *         value corresponding to the selected ADC resolution.
+  * @note   ADC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data full-scale digital value
+  */
+#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+  __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to convert the ADC conversion data from
+  *         a resolution to another resolution.
+  * @param  __DATA__ ADC conversion data to be converted
+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data to the requested resolution
+  */
+#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+                                          __ADC_RESOLUTION_CURRENT__,\
+                                          __ADC_RESOLUTION_TARGET__) \
+__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
+                                 (__ADC_RESOLUTION_CURRENT__),\
+                                 (__ADC_RESOLUTION_TARGET__))
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                       __ADC_DATA__,\
+                                       __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+                              (__ADC_DATA__),\
+                              (__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to calculate analog reference voltage (Vref+)
+  *         (unit: mVolt) from ADC conversion data of internal voltage
+  *         reference VrefInt.
+  * @note   Computation is using VrefInt calibration value
+  *         stored in system memory for each device during production.
+  * @note   This voltage depends on user board environment: voltage level
+  *         connected to pin Vref+.
+  *         On devices with small package, the pin Vref+ is not present
+  *         and internally bonded to pin Vdda.
+  * @note   On this STM32 series, calibration data of internal voltage reference
+  *         VrefInt corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         internal voltage reference VrefInt.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *         of internal voltage reference VrefInt (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval Analog reference voltage (unit: mV)
+  */
+#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+                                          __ADC_RESOLUTION__) \
+__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
+                                 (__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor calibration values
+  *         stored in system memory for each device during production.
+  * @note   Calculation formula:
+  *           Temperature = ((TS_ADC_DATA - TS_CAL1)
+  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
+  *                Avg_Slope = (TS_CAL2 - TS_CAL1)
+  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL1 (calibrated in factory)
+  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL2 (calibrated in factory)
+  *         Caution: Calculation relevancy under reserve that calibration
+  *                  parameters are correct (address and data).
+  *                  To calculate temperature using temperature sensor
+  *                  datasheet typical values (generic values less, therefore
+  *                  less accurate than calibrated values),
+  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   On this STM32 series, calibration data of temperature sensor
+  *         corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         temperature sensor.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+  *                                 temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
+  *                                 sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+                                   __TEMPSENSOR_ADC_DATA__,\
+                                   __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
+                          (__TEMPSENSOR_ADC_DATA__),\
+                          (__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor typical values
+  *         (refer to device datasheet).
+  * @note   Calculation formula:
+  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+  *                         / Avg_Slope + CALx_TEMP
+  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
+  *                                   (unit: digital value)
+  *                Avg_Slope        = temperature sensor slope
+  *                                   (unit: uV/Degree Celsius)
+  *                TS_TYP_CALx_VOLT = temperature sensor digital value at
+  *                                   temperature CALx_TEMP (unit: mV)
+  *         Caution: Calculation relevancy under reserve the temperature sensor
+  *                  of the current device has characteristics in line with
+  *                  datasheet typical values.
+  *                  If temperature sensor calibration values are available on
+  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+  *                  temperature calculation will be more accurate using
+  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   ADC measurement data must correspond to a resolution of 12bits
+  *         (full scale digital value 4095). If not the case, the data must be
+  *         preliminarily rescaled to an equivalent resolution of 12 bits.
+  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+  *                                       On STM32G4, refer to device datasheet parameter "Avg_Slope".
+  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
+  *                                       On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
+  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+                                              __TEMPSENSOR_TYP_CALX_V__,\
+                                              __TEMPSENSOR_CALX_TEMP__,\
+                                              __VREFANALOG_VOLTAGE__,\
+                                              __TEMPSENSOR_ADC_DATA__,\
+                                              __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
+                                     (__TEMPSENSOR_TYP_CALX_V__),\
+                                     (__TEMPSENSOR_CALX_TEMP__),\
+                                     (__VREFANALOG_VOLTAGE__),\
+                                     (__TEMPSENSOR_ADC_DATA__),\
+                                     (__ADC_RESOLUTION__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Include ADC HAL Extended module */
+#include "stm32g4xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+  * @brief    Initialization and Configuration functions
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+                                           pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions  *****************************************************/
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
+
+/* ADC sampling control */
+HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
+HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
+
+/**
+  * @}
+  */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+  * @{
+  */
+uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
+uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAError(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32G4xx_HAL_ADC_H */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h
new file mode 100644
index 0000000..d2da2c2
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h
@@ -0,0 +1,1393 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_adc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_ADC_EX_H
+#define STM32G4xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  ADC Injected Conversion Oversampling structure definition
+  */
+typedef struct
+{
+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+
+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+} ADC_InjOversamplingTypeDef;
+
+/**
+  * @brief  Structure definition of ADC group injected and ADC channel affected to ADC group injected
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation
+  *          - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+  *            AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
+  * @note   The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
+  *          - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
+  *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign', 'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
+  *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
+  *            on ADC groups regular and injected.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t InjectedChannel;               /*!< Specifies the channel to configure into ADC group injected.
+                                               This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+                                               Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
+
+  uint32_t InjectedRank;                  /*!< Specifies the rank in the ADC group injected sequencer.
+                                               This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
+                                               Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
+                                               the new channel setting (or parameter number of conversions adjusted) */
+
+  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
+                                               Unit: ADC clock cycles.
+                                               Conversion time is the addition of sampling time and processing time
+                                               (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+                                               This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
+                                               Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
+                                                        It overwrites the last setting.
+                                               Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+                                                     sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                                     Refer to device datasheet for timings values. */
+
+  uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.
+                                               In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
+                                               Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
+                                               This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
+                                               Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
+                                                        It overwrites the last setting.
+                                               Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
+                                               Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
+                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+                                               If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
+                                               of another parameter update on the fly) */
+
+  uint32_t InjectedOffsetNumber;          /*!< Selects the offset number.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
+                                               Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
+
+  uint32_t InjectedOffset;                /*!< Defines the offset to be applied on the raw converted data.
+                                               Offset value must be a positive number.
+                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
+                                               between Min_Data = 0x000 and Max_Data = 0xFFF,  0x3FF, 0xFF or 0x3F respectively.
+                                               Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
+                                               without continuous mode or external trigger that could launch a conversion). */
+
+  uint32_t InjectedOffsetSign;                /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data.
+                                               This parameter can be a value of @ref ADCEx_OffsetSign.
+                                               Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+  FunctionalState InjectedOffsetSaturation;   /*!< Define if the offset should be saturated upon under or over flow.
+                                               This parameter value can be ENABLE or DISABLE.
+                                               Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+
+  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
+                                               To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+
+  FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
+                                               (main sequence subdivided in successive parts).
+                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                               Discontinuous mode can be enabled only if continuous mode is disabled.
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+                                               Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+
+  FunctionalState AutoInjectedConv;       /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+                                               Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
+                                               Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+                                                     To maintain JAUTO always enabled, DMA must be configured in circular mode.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+
+  FunctionalState QueueInjectedContext;   /*!< Specifies whether the context queue feature is enabled.
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
+                                               new injected context is set when queue is full, error is triggered by interruption and through function
+                                               'HAL_ADCEx_InjectedQueueOverflowCallback'.
+                                               Caution: This feature request that the sequence is fully configured before injected conversion start.
+                                                        Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the configuration of other channels previously set.
+                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
+
+  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
+                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
+                                               This parameter can be a value of @ref ADC_injected_external_trigger_source.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+
+  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
+                                               This parameter can be a value of @ref ADC_injected_external_trigger_edge.
+                                               If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
+
+  FunctionalState InjecOversamplingMode;         /*!< Specifies whether the oversampling feature is enabled or disabled.
+                                                      This parameter can be set to ENABLE or DISABLE.
+                                                      Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
+
+  ADC_InjOversamplingTypeDef  InjecOversampling; /*!< Specifies the Oversampling parameters.
+                                                      Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
+                                                      Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
+} ADC_InjectionConfTypeDef;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Structure definition of ADC multimode
+  * @note   The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
+  *         Both Master and Slave ADCs must be disabled.
+  */
+typedef struct
+{
+  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multimode.
+                                   This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
+
+  uint32_t DMAAccessMode;     /*!< Configures the DMA mode for multimode ADC:
+                                   selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
+                                   This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
+
+  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
+                                   This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
+                                   Delay range depends on selected resolution:
+                                    from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
+                                    from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits.     */
+} ADC_MultiModeTypeDef;
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
+  * @{
+  */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_INJECTED_SOFTWARE_START        (LL_ADC_INJ_TRIG_SOFTWARE)            /*!< Software triggers injected group conversion start */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)      /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T1_CC3       (LL_ADC_INJ_TRIG_EXT_TIM1_CH3)        /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T1_CC4       (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)        /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T2_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T2_CC1       (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)        /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T3_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC1       (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)        /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC3       (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)        /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC4       (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)        /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T4_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T4_CC3       (LL_ADC_INJ_TRIG_EXT_TIM4_CH3)        /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T4_CC4       (LL_ADC_INJ_TRIG_EXT_TIM4_CH4)        /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T6_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T7_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)      /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T8_CC2       (LL_ADC_INJ_TRIG_EXT_TIM8_CH2)        /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T8_CC4       (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)        /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T15_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)      /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T16_CC1      (LL_ADC_INJ_TRIG_EXT_TIM16_CH1)       /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T20_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)      /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T20_TRGO2    (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)     /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T20_CC2      (LL_ADC_INJ_TRIG_EXT_TIM20_CH2)       /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T20_CC4      (LL_ADC_INJ_TRIG_EXT_TIM20_CH4)       /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1)      /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)      /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3)      /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)      /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5)      /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6)      /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7)      /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8)      /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9)      /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10  (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10)     /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_EXT_IT3      (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)      /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_EXT_IT15     (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)     /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_LPTIM_OUT    (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)       /*!< ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
+  * @{
+  */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           (0x00000000UL)        /*!< Injected conversions hardware trigger detection disabled                             */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         (ADC_JSQR_JEXTEN_0)   /*!< Injected conversions hardware trigger detection on the rising edge                   */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        (ADC_JSQR_JEXTEN_1)   /*!< Injected conversions hardware trigger detection on the falling edge                  */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  (ADC_JSQR_JEXTEN)     /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
+  * @{
+  */
+#define ADC_SINGLE_ENDED                (LL_ADC_SINGLE_ENDED)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
+#define ADC_DIFFERENTIAL_ENDED          (LL_ADC_DIFFERENTIAL_ENDED)   /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OFFSET_NB  ADC instance - Offset number
+  * @{
+  */
+#define ADC_OFFSET_NONE              (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */
+#define ADC_OFFSET_1                 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define ADC_OFFSET_2                 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define ADC_OFFSET_3                 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define ADC_OFFSET_4                 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
+  * @{
+  */
+#define ADC_OFFSET_SIGN_NEGATIVE      (0x00000000UL)          /*!< Offset sign negative, offset is subtracted */
+#define ADC_OFFSET_SIGN_POSITIVE      (ADC_OFR1_OFFSETPOS)   /*!< Offset sign positive, offset is added  */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
+  * @{
+  */
+#define ADC_INJECTED_RANK_1                (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
+#define ADC_INJECTED_RANK_2                (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
+#define ADC_INJECTED_RANK_3                (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
+#define ADC_INJECTED_RANK_4                (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
+/**
+  * @}
+  */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_HAL_EC_MULTI_MODE  Multimode - Mode
+  * @{
+  */
+#define ADC_MODE_INDEPENDENT               (LL_ADC_MULTI_INDEPENDENT)                                          /*!< ADC dual mode disabled (ADC independent mode) */
+#define ADC_DUALMODE_REGSIMULT             (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */
+#define ADC_DUALMODE_INTERL                (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */
+#define ADC_DUALMODE_INJECSIMULT           (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */
+#define ADC_DUALMODE_ALTERTRIG             (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG   (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
+
+/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION  Multimode - DMA transfer mode depending on ADC resolution
+  * @{
+  */
+#define ADC_DMAACCESSMODE_DISABLED      (0x00000000UL)     /*!< DMA multimode disabled: each ADC uses its own DMA channel */
+#define ADC_DMAACCESSMODE_12_10_BITS    (ADC_CCR_MDMA_1)   /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
+#define ADC_DMAACCESSMODE_8_6_BITS      (ADC_CCR_MDMA)     /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
+  * @{
+  */
+#define ADC_TWOSAMPLINGDELAY_1CYCLE        (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)   /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
+#define ADC_TWOSAMPLINGDELAY_2CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)  /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_3CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)  /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_4CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)  /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_5CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)  /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_6CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)  /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_7CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)  /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_8CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)  /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_9CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)  /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_10CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_11CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_12CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/** @defgroup ADC_HAL_EC_GROUPS  ADC instance - Groups
+  * @{
+  */
+#define ADC_REGULAR_GROUP                  (LL_ADC_GROUP_REGULAR)           /*!< ADC group regular (available on all STM32 devices) */
+#define ADC_INJECTED_GROUP                 (LL_ADC_GROUP_INJECTED)          /*!< ADC group injected (not available on all STM32 devices)*/
+#define ADC_REGULAR_INJECTED_GROUP         (LL_ADC_GROUP_REGULAR_INJECTED)  /*!< ADC both groups regular and injected */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_CFGR_fields ADCx CFGR fields
+  * @{
+  */
+#define ADC_CFGR_FIELDS    (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
+                            ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
+                            ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
+                            ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
+                            ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
+                            ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )
+/**
+  * @}
+  */
+
+/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
+  * @{
+  */
+#if defined(ADC_SMPR1_SMPPLUS)
+#define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
+                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
+                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
+                             ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS)
+#else
+#define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
+                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
+                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
+                             ADC_SMPR1_SMP0)
+#endif /* ADC_SMPR1_SMPPLUS */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
+  * @{
+  */
+/* ADC_CFGR fields of parameters that can be updated when no conversion
+   (neither regular nor injected) is on-going  */
+#define ADC_CFGR_FIELDS_2  ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
+  * @{
+  */
+
+/** @brief  Force ADC instance in multimode mode independent (multimode disable).
+  * @note   This macro must be used only in case of transition from multimode
+  *         to mode independent and in case of unknown previous state,
+  *         to ensure ADC configuration is in mode independent.
+  * @note   Standard way of multimode configuration change is done from
+  *         HAL ADC handle of ADC master using function
+  *         "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
+  *         Usage of this macro is not the Standard way of multimode
+  *         configuration and can lead to have HAL ADC handles status
+  *         misaligned. Usage of this macro must be limited to cases
+  *         mentioned above.
+  * @param __HANDLE__ ADC handle.
+  * @retval None
+  */
+#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__)                                 \
+  LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
+
+/**
+  * @}
+  */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
+  * @{
+  */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+  * @brief Test if conversion trigger of injected group is software start
+  *        or external trigger.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (software start) or RESET (external trigger).
+  */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
+  (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
+
+/**
+  * @brief Check whether or not ADC is independent.
+  * @param __HANDLE__ ADC handle.
+  * @note  When multimode feature is not available, the macro always returns SET.
+  * @retval SET (ADC is independent) or RESET (ADC is not).
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define ADC_IS_INDEPENDENT(__HANDLE__)    \
+  ( ( ( ((__HANDLE__)->Instance) == ADC5) \
+    )?                                    \
+    SET                                   \
+    :                                     \
+    RESET                                 \
+  )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define ADC_IS_INDEPENDENT(__HANDLE__)    \
+  ( ( ( ((__HANDLE__)->Instance) == ADC3) \
+    )?                                    \
+    SET                                   \
+    :                                     \
+    RESET                                 \
+  )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
+
+/**
+  * @brief Set the selected injected Channel rank.
+  * @param __CHANNELNB__ Channel number.
+  * @param __RANKNB__ Rank number.
+  * @retval None
+  */
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\
+                                                  & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
+
+/**
+  * @brief Configure ADC injected context queue
+  * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
+  * @retval None
+  */
+#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
+
+/**
+  * @brief Configure ADC discontinuous conversion mode for injected group
+  * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
+  * @retval None
+  */
+#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) <<  ADC_CFGR_JDISCEN_Pos)
+
+/**
+  * @brief Configure ADC discontinuous conversion mode for regular group
+  * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
+  * @retval None
+  */
+#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
+
+/**
+  * @brief Configure the number of discontinuous conversions for regular group.
+  * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
+  * @retval None
+  */
+#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
+
+/**
+  * @brief Configure the ADC auto delay mode.
+  * @param __AUTOWAIT__ Auto delay bit enable or disable.
+  * @retval None
+  */
+#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
+
+/**
+  * @brief Configure ADC continuous conversion mode.
+  * @param __CONTINUOUS_MODE__ Continuous mode.
+  * @retval None
+  */
+#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
+
+/**
+  * @brief Configure the ADC DMA continuous request.
+  * @param __DMACONTREQ_MODE__ DMA continuous request mode.
+  * @retval None
+  */
+#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) <<  ADC_CFGR_DMACFG_Pos)
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief Configure the ADC DMA continuous request for ADC multimode.
+  * @param __DMACONTREQ_MODE__ DMA continuous request mode.
+  * @retval None
+  */
+#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief Shift the offset with respect to the selected ADC resolution.
+  * @note   Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+  *         If resolution 12 bits, no shift.
+  *         If resolution 10 bits, shift of 2 ranks on the left.
+  *         If resolution 8 bits, shift of 4 ranks on the left.
+  *         If resolution 6 bits, shift of 6 ranks on the left.
+  *         Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
+  * @param __HANDLE__ ADC handle
+  * @param __OFFSET__ Value to be shifted
+  * @retval None
+  */
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
+  ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
+
+/**
+  * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
+  * @note  Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+  *        If resolution 12 bits, no shift.
+  *        If resolution 10 bits, shift of 2 ranks on the left.
+  *        If resolution 8 bits, shift of 4 ranks on the left.
+  *        If resolution 6 bits, shift of 6 ranks on the left.
+  *        Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
+  * @param __HANDLE__ ADC handle
+  * @param __THRESHOLD__ Value to be shifted
+  * @retval None
+  */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+  ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
+
+/**
+  * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
+  * @note  Thresholds have to be left-aligned on bit 7.
+  *        If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
+  *        If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
+  *        If resolution 8 bits, no shift.
+  *        If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
+  * @param __HANDLE__ ADC handle
+  * @param __THRESHOLD__ Value to be shifted
+  * @retval None
+  */
+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                       \
+  ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0))                    ? \
+   ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
+   ((__THRESHOLD__) << 2UL)                                                                                 \
+  )
+
+/**
+  * @brief Clear Common Control Register.
+  * @param __HANDLE__ ADC handle.
+  * @retval None
+  */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
+                                                                ADC_CCR_CKMODE    | \
+                                                                ADC_CCR_PRESC     | \
+                                                                ADC_CCR_VBATSEL   | \
+                                                                ADC_CCR_VSENSESEL | \
+                                                                ADC_CCR_VREFEN    | \
+                                                                ADC_CCR_MDMA      | \
+                                                                ADC_CCR_DMACFG    | \
+                                                                ADC_CCR_DELAY     | \
+                                                                ADC_CCR_DUAL)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+/**
+  * @brief Set handle instance of the ADC slave associated to the ADC master.
+  * @param __HANDLE_MASTER__ ADC master handle.
+  * @param __HANDLE_SLAVE__ ADC slave handle.
+  * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.
+  * @retval None
+  */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
+  ( ((__HANDLE_MASTER__)->Instance == ADC1) ?                            \
+    ((__HANDLE_SLAVE__)->Instance = ADC2)                                \
+    :                                                                    \
+    ((__HANDLE_MASTER__)->Instance == ADC3) ?                            \
+    ((__HANDLE_SLAVE__)->Instance = ADC4)                                \
+    :                                                                    \
+    ((__HANDLE_SLAVE__)->Instance = NULL)                                \
+  )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
+/**
+  * @brief Set handle instance of the ADC slave associated to the ADC master.
+  * @param __HANDLE_MASTER__ ADC master handle.
+  * @param __HANDLE_SLAVE__ ADC slave handle.
+  * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.
+  * @retval None
+  */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
+  ( ((__HANDLE_MASTER__)->Instance == ADC1) ?                            \
+    ((__HANDLE_SLAVE__)->Instance = ADC2)                                \
+    :                                                                    \
+    ((__HANDLE_SLAVE__)->Instance = NULL)                                \
+  )
+#endif
+
+
+/**
+  * @brief Verify the ADC instance connected to the temperature sensor.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5))
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
+
+/**
+  * @brief Verify the ADC instance connected to the battery voltage VBAT.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4))
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) != ADC2)
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
+#endif
+
+/**
+  * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+  */
+#define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) != ADC2)
+
+/**
+  * @brief Verify the length of scheduled injected conversions group.
+  * @param __LENGTH__ number of programmed conversions.
+  * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
+  */
+#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
+
+/**
+  * @brief Calibration factor size verification (7 bits maximum).
+  * @param __CALIBRATION_FACTOR__ Calibration factor value.
+  * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
+  */
+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
+
+
+/**
+  * @brief Verify the ADC channel setting.
+  * @param __HANDLE__ ADC handle.
+  * @param __CHANNEL__ programmed ADC channel.
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (      ( ((__CHANNEL__) == ADC_CHANNEL_1)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))              || \
+                                                        ((((__HANDLE__)->Instance) == ADC1)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_17)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))   || \
+                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3)     || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC4)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC5)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP5)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC5)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP4)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
+#elif defined(STM32G471xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (      ( ((__CHANNEL__) == ADC_CHANNEL_1)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))              || \
+                                                        ((((__HANDLE__)->Instance) == ADC1)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_13)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_17)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))   || \
+                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3)     || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (      ( ((__CHANNEL__) == ADC_CHANNEL_1)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))              || \
+                                                        ((((__HANDLE__)->Instance) == ADC1)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_13)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_17)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))))
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (      ( ((__CHANNEL__) == ADC_CHANNEL_1)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))              || \
+                                                        ((((__HANDLE__)->Instance) == ADC1)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_13)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_17)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))   || \
+                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3)     || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
+
+/**
+  * @brief Verify the ADC channel setting in differential mode.
+  * @param __HANDLE__ ADC handle.
+  * @param __CHANNEL__ programmed ADC channel.
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)  ( ( ((__CHANNEL__) == ADC_CHANNEL_1)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14))         || \
+                                                        ((((__HANDLE__)->Instance) == ADC1)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)))         || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC4)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC5)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))) )
+#elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)  ( ( ((__CHANNEL__) == ADC_CHANNEL_1)           || \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14))         || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))) )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)  ( ( ((__CHANNEL__) == ADC_CHANNEL_1)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14))         || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13))) )
+#endif
+
+/**
+  * @brief Verify the ADC single-ended input or differential mode setting.
+  * @param __SING_DIFF__ programmed channel setting.
+  * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
+  */
+#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
+                                                   ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )
+
+/**
+  * @brief Verify the ADC offset management setting.
+  * @param __OFFSET_NUMBER__ ADC offset management.
+  * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
+  */
+#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )
+
+/**
+  * @brief Verify the ADC offset sign setting.
+  * @param __OFFSET_SIGN__ ADC offset sign.
+  * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)
+  */
+#define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__)     (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \
+                                                 ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE)    )
+
+/**
+  * @brief Verify the ADC injected channel setting.
+  * @param __CHANNEL__ programmed ADC injected channel.
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )
+
+/**
+  * @brief Verify the ADC injected conversions external trigger.
+  * @param __HANDLE__ ADC handle.
+  * @param __INJTRIG__ programmed ADC injected conversions external trigger.
+  * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2)      || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG2)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG4)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG5)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG6)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG7)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG8)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG9)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10)    || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
+                                                       ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)))   || \
+                                                       ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1)   || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3)   || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3)))    || \
+                                                       ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2)      || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
+                                                       ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)))   || \
+                                                       ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3)))    || \
+                                                       ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
+#elif defined(STM32G471xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
+                                                       ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)))   || \
+                                                       ((((__HANDLE__)->Instance == ADC3)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3)))    || \
+                                                       ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
+                                                       ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2)      || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
+                                                       ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)))   || \
+                                                       (((__HANDLE__)->Instance == ADC3) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3)))    || \
+                                                       ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
+#endif
+
+/**
+  * @brief Verify the ADC edge trigger setting for injected group.
+  * @param __EDGE__ programmed ADC edge trigger setting.
+  * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+  */
+#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief Verify the ADC multimode setting.
+  * @param __MODE__ programmed ADC multimode setting.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)               || \
+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
+                                    ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
+                                    ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
+                                    ((__MODE__) == ADC_DUALMODE_INTERL)                || \
+                                    ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )
+
+/**
+  * @brief Verify the ADC multimode DMA access setting.
+  * @param __MODE__ programmed ADC multimode DMA access setting.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED)   || \
+                                               ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
+                                               ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS)     )
+
+/**
+  * @brief Verify the ADC multimode delay setting.
+  * @param __DELAY__ programmed ADC multimode delay setting.
+  * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
+  */
+#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES)   )
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief Verify the ADC analog watchdog setting.
+  * @param __WATCHDOG__ programmed ADC analog watchdog setting.
+  * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
+  */
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
+                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
+                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )
+
+/**
+  * @brief Verify the ADC analog watchdog mode setting.
+  * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
+  * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
+  */
+#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)             || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )
+
+/**
+  * @brief Verify the ADC analog watchdog filtering setting.
+  * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting.
+  * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid)
+  */
+#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__)  (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE)            || \
+                                                                    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES)        || \
+                                                                    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES)        || \
+                                                                    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES)        || \
+                                                                    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES)        || \
+                                                                    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES)        || \
+                                                                    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES)        || \
+                                                                    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES)           )
+
+
+/**
+  * @brief Verify the ADC conversion (regular or injected or both).
+  * @param __CONVERSION__ ADC conversion group.
+  * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
+  */
+#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)         || \
+                                                 ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
+                                                 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )
+
+/**
+  * @brief Verify the ADC event type.
+  * @param __EVENT__ ADC event.
+  * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
+  */
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT)  || \
+                                      ((__EVENT__) == ADC_AWD_EVENT)    || \
+                                      ((__EVENT__) == ADC_AWD2_EVENT)   || \
+                                      ((__EVENT__) == ADC_AWD3_EVENT)   || \
+                                      ((__EVENT__) == ADC_OVR_EVENT)    || \
+                                      ((__EVENT__) == ADC_JQOVF_EVENT)  )
+
+/**
+  * @brief Verify the ADC oversampling ratio.
+  * @param __RATIO__ programmed ADC oversampling ratio.
+  * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
+  */
+#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__)      (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
+
+/**
+  * @brief Verify the ADC oversampling shift.
+  * @param __SHIFT__ programmed ADC oversampling shift.
+  * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
+  */
+#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))
+
+/**
+  * @brief Verify the ADC oversampling triggered mode.
+  * @param __MODE__ programmed ADC oversampling triggered mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
+
+/**
+  * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
+  * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
+                                               ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
+
+/**
+  * @brief Verify the DFSDM mode configuration.
+  * @param __HANDLE__ ADC handle.
+  * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
+  *      this reason, the input parameter is the ADC handle and not the configuration parameter
+  *      directly.
+  * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
+  */
+#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
+
+/**
+  * @brief Return the DFSDM configuration mode.
+  * @param __HANDLE__ ADC handle.
+  * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
+  *       For this reason, the input parameter is the ADC handle and not the configuration parameter
+  *       directly.
+  * @retval DFSDM configuration mode
+  */
+#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+  * @{
+  */
+/* IO operation functions *****************************************************/
+
+/* ADC calibration */
+HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+uint32_t                HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+                                                       uint32_t CalibrationFactor);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* ADC multimode */
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+uint32_t                HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
+
+/* ADC group regular conversions stop */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @addtogroup ADCEx_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
+                                                        ADC_InjectionConfTypeDef *sConfigInjected);
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
+#endif /* ADC_MULTIMODE_SUPPORT */
+HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_ADC_EX_H */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h
new file mode 100644
index 0000000..c55a859
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h
@@ -0,0 +1,419 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_HAL_CORTEX_H
+#define __STM32G4xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @brief CORTEX HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @brief  MPU Region initialization structure 
+  * @{
+  */
+typedef struct
+{
+  uint8_t                Enable;                /*!< Specifies the status of the region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+}MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bit  for pre-emption priority,
+                                                      4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bit  for pre-emption priority,
+                                                      3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority,
+                                                      2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority,
+                                                      1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority,
+                                                      0 bit  for subpriority */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8       0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK            0x00000004U
+
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
+#define  MPU_HARDFAULT_NMI                (MPU_CTRL_HFNMIENA_Msk)
+#define  MPU_PRIVILEGED_DEFAULT           (MPU_CTRL_PRIVDEFENA_Msk)
+#define  MPU_HFNMI_PRIVDEF                (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE           ((uint8_t)0x01)
+#define  MPU_REGION_DISABLE          ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_CACHEABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE       ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_BUFFERABLE   ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
+  * @{
+  */
+#define  MPU_TEX_LEVEL0              ((uint8_t)0x00)
+#define  MPU_TEX_LEVEL1              ((uint8_t)0x01)
+#define  MPU_TEX_LEVEL2              ((uint8_t)0x02)
+#define  MPU_TEX_LEVEL4              ((uint8_t)0x04)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_32B        ((uint8_t)0x04)
+#define   MPU_REGION_SIZE_64B        ((uint8_t)0x05)
+#define   MPU_REGION_SIZE_128B       ((uint8_t)0x06)
+#define   MPU_REGION_SIZE_256B       ((uint8_t)0x07)
+#define   MPU_REGION_SIZE_512B       ((uint8_t)0x08)
+#define   MPU_REGION_SIZE_1KB        ((uint8_t)0x09)
+#define   MPU_REGION_SIZE_2KB        ((uint8_t)0x0A)
+#define   MPU_REGION_SIZE_4KB        ((uint8_t)0x0B)
+#define   MPU_REGION_SIZE_8KB        ((uint8_t)0x0C)
+#define   MPU_REGION_SIZE_16KB       ((uint8_t)0x0D)
+#define   MPU_REGION_SIZE_32KB       ((uint8_t)0x0E)
+#define   MPU_REGION_SIZE_64KB       ((uint8_t)0x0F)
+#define   MPU_REGION_SIZE_128KB      ((uint8_t)0x10)
+#define   MPU_REGION_SIZE_256KB      ((uint8_t)0x11)
+#define   MPU_REGION_SIZE_512KB      ((uint8_t)0x12)
+#define   MPU_REGION_SIZE_1MB        ((uint8_t)0x13)
+#define   MPU_REGION_SIZE_2MB        ((uint8_t)0x14)
+#define   MPU_REGION_SIZE_4MB        ((uint8_t)0x15)
+#define   MPU_REGION_SIZE_8MB        ((uint8_t)0x16)
+#define   MPU_REGION_SIZE_16MB       ((uint8_t)0x17)
+#define   MPU_REGION_SIZE_32MB       ((uint8_t)0x18)
+#define   MPU_REGION_SIZE_64MB       ((uint8_t)0x19)
+#define   MPU_REGION_SIZE_128MB      ((uint8_t)0x1A)
+#define   MPU_REGION_SIZE_256MB      ((uint8_t)0x1B)
+#define   MPU_REGION_SIZE_512MB      ((uint8_t)0x1C)
+#define   MPU_REGION_SIZE_1GB        ((uint8_t)0x1D)
+#define   MPU_REGION_SIZE_2GB        ((uint8_t)0x1E)
+#define   MPU_REGION_SIZE_4GB        ((uint8_t)0x1F)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS        ((uint8_t)0x00)
+#define  MPU_REGION_PRIV_RW          ((uint8_t)0x01)
+#define  MPU_REGION_PRIV_RW_URO      ((uint8_t)0x02)
+#define  MPU_REGION_FULL_ACCESS      ((uint8_t)0x03)
+#define  MPU_REGION_PRIV_RO          ((uint8_t)0x05)
+#define  MPU_REGION_PRIV_RO_URO      ((uint8_t)0x06)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0          ((uint8_t)0x00)
+#define  MPU_REGION_NUMBER1          ((uint8_t)0x01)
+#define  MPU_REGION_NUMBER2          ((uint8_t)0x02)
+#define  MPU_REGION_NUMBER3          ((uint8_t)0x03)
+#define  MPU_REGION_NUMBER4          ((uint8_t)0x04)
+#define  MPU_REGION_NUMBER5          ((uint8_t)0x05)
+#define  MPU_REGION_NUMBER6          ((uint8_t)0x06)
+#define  MPU_REGION_NUMBER7          ((uint8_t)0x07)
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 
+  * @brief    Initialization and Configuration functions
+  * @{
+  */
+/* Initialization and Configuration functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 
+  * @brief   Cortex control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/ 
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) > SysTick_IRQn)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+                                     ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
+                                ((TYPE) == MPU_TEX_LEVEL1)  || \
+                                ((TYPE) == MPU_TEX_LEVEL2)  || \
+                                ((TYPE) == MPU_TEX_LEVEL4))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_HAL_CORTEX_H */
+
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h
new file mode 100644
index 0000000..c16f6c7
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h
@@ -0,0 +1,209 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_HAL_DEF
+#define __STM32G4xx_HAL_DEF
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+#include "Legacy/stm32_hal_legacy.h"  /* Aliases file for old names compatibility */
+#include <stddef.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00U,
+  HAL_ERROR    = 0x01U,
+  HAL_BUSY     = 0x02U,
+  HAL_TIMEOUT  = 0x03U
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00U,
+  HAL_LOCKED   = 0x01U
+} HAL_LockTypeDef;
+
+/* Exported macros -----------------------------------------------------------*/
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
+  do{                                                                \
+    (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__);             \
+    (__DMA_HANDLE__).Parent = (__HANDLE__);                          \
+  } while(0)
+
+#define UNUSED(X) (void)X
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__: specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose:
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1U)
+/* Reserved for future use */
+#error " USE_RTOS should be 0 in the current HAL release "
+#else
+#define __HAL_LOCK(__HANDLE__)             \
+  do{                                      \
+    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+    {                                      \
+      return HAL_BUSY;                     \
+    }                                      \
+    else                                   \
+    {                                      \
+      (__HANDLE__)->Lock = HAL_LOCKED;     \
+    }                                      \
+  }while (0U)
+
+#define __HAL_UNLOCK(__HANDLE__)           \
+  do{                                      \
+    (__HANDLE__)->Lock = HAL_UNLOCKED;     \
+  }while (0U)
+#endif /* USE_RTOS */
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#ifndef __weak
+#define __weak  __attribute__((weak))
+#endif
+#ifndef __packed
+#define __packed  __attribute__((packed))
+#endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#ifndef __weak
+#define __weak   __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif
+#ifndef __ALIGN_END
+#define __ALIGN_END      __attribute__ ((aligned (4)))
+#endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END    __attribute__ ((aligned (4U)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#else
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#if defined   (__CC_ARM)      /* ARM Compiler V5*/
+#define __ALIGN_BEGIN    __align(4U)
+#elif defined (__ICCARM__)    /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif /* __CC_ARM */
+#endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM Compiler V4/V5 and V6
+   --------------------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif /* __CC_ARM */
+
+/**
+  * @brief  __NOINLINE definition
+  */
+#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined   (  __GNUC__  )
+/* ARM V4/V5 and V6 & GNU Compiler
+   -------------------------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif /* __CC_ARM || __GNUC__ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32G4xx_HAL_DEF */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h
new file mode 100644
index 0000000..0e6eecf
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h
@@ -0,0 +1,852 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_HAL_DMA_H
+#define __STM32G4xx_HAL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
+                                           This parameter can be a value of @ref DMA_request */
+
+  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
+                                           from memory to memory or from peripheral to memory.
+                                           This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
+                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
+                                           This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
+                                           This parameter can be a value of @ref DMA_Memory_data_size */
+
+  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
+                                           This parameter can be a value of @ref DMA_mode
+                                           @note The circular buffer mode cannot be used if the memory-to-memory
+                                                 data transfer is configured on the selected Channel */
+
+  uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
+                                           This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
+  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                     */
+} HAL_DMA_StateTypeDef;
+
+/**
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
+} HAL_DMA_LevelCompleteTypeDef;
+
+
+/**
+  * @brief  HAL DMA Callback ID structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */
+
+} HAL_DMA_CallbackIDTypeDef;
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  DMA_Channel_TypeDef    *Instance;                                                  /*!< Register base address                */
+
+  DMA_InitTypeDef       Init;                                                        /*!< DMA communication parameters         */
+
+  HAL_LockTypeDef       Lock;                                                        /*!< DMA locking object                   */
+
+  __IO HAL_DMA_StateTypeDef  State;                                                  /*!< DMA transfer state                   */
+
+  void                  *Parent;                                                     /*!< Parent object state                  */
+
+  void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma);                       /*!< DMA transfer complete callback       */
+
+  void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma);                   /*!< DMA Half transfer complete callback  */
+
+  void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma);                      /*!< DMA transfer error callback          */
+
+  void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma);                      /*!< DMA transfer abort callback          */
+
+  __IO uint32_t          ErrorCode;                                                  /*!< DMA Error code                       */
+
+  DMA_TypeDef            *DmaBaseAddress;                                            /*!< DMA Channel Base Address             */
+
+  uint32_t               ChannelIndex;                                               /*!< DMA Channel Index                    */
+
+  DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                   /*!< Register base address                */
+
+  DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                             /*!< DMAMUX Channels Status Base Address  */
+
+  uint32_t                         DMAmuxChannelStatusMask;                          /*!< DMAMUX Channel Status Mask           */
+
+  DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                /*!< DMAMUX request generator Base Address */
+
+  DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                          /*!< DMAMUX request generator Address     */
+
+  uint32_t                         DMAmuxRequestGenStatusMask;                       /*!< DMAMUX request generator Status mask */
+
+} DMA_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @{
+  */
+#define HAL_DMA_ERROR_NONE             0x00000000U    /*!< No error                              */
+#define HAL_DMA_ERROR_TE               0x00000001U    /*!< Transfer error                        */
+#define HAL_DMA_ERROR_NO_XFER          0x00000004U    /*!< Abort requested with no Xfer ongoing  */
+#define HAL_DMA_ERROR_TIMEOUT          0x00000020U    /*!< Timeout error                         */
+#define HAL_DMA_ERROR_NOT_SUPPORTED    0x00000100U    /*!< Not supported mode                    */
+#define HAL_DMA_ERROR_SYNC             0x00000200U    /*!< DMAMUX sync overrun  error              */
+#define HAL_DMA_ERROR_REQGEN           0x00000400U    /*!< DMAMUX request generator overrun  error */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_request DMA request
+  * @{
+  */
+#define DMA_REQUEST_MEM2MEM            0U  /*!< memory to memory transfer   */
+
+#define DMA_REQUEST_GENERATOR0         1U
+#define DMA_REQUEST_GENERATOR1         2U
+#define DMA_REQUEST_GENERATOR2         3U
+#define DMA_REQUEST_GENERATOR3         4U
+
+#define DMA_REQUEST_ADC1               5U
+
+#define DMA_REQUEST_DAC1_CHANNEL1      6U
+#define DMA_REQUEST_DAC1_CHANNEL2      7U
+
+#define DMA_REQUEST_TIM6_UP            8U
+#define DMA_REQUEST_TIM7_UP            9U
+
+#define DMA_REQUEST_SPI1_RX           10U
+#define DMA_REQUEST_SPI1_TX           11U
+#define DMA_REQUEST_SPI2_RX           12U
+#define DMA_REQUEST_SPI2_TX           13U
+#define DMA_REQUEST_SPI3_RX           14U
+#define DMA_REQUEST_SPI3_TX           15U
+
+#define DMA_REQUEST_I2C1_RX           16U
+#define DMA_REQUEST_I2C1_TX           17U
+#define DMA_REQUEST_I2C2_RX           18U
+#define DMA_REQUEST_I2C2_TX           19U
+#define DMA_REQUEST_I2C3_RX           20U
+#define DMA_REQUEST_I2C3_TX           21U
+#if defined (I2C4)
+#define DMA_REQUEST_I2C4_RX           22U
+#define DMA_REQUEST_I2C4_TX           23U
+#endif /* I2C4 */
+
+#define DMA_REQUEST_USART1_RX         24U
+#define DMA_REQUEST_USART1_TX         25U
+#define DMA_REQUEST_USART2_RX         26U
+#define DMA_REQUEST_USART2_TX         27U
+#define DMA_REQUEST_USART3_RX         28U
+#define DMA_REQUEST_USART3_TX         29U
+
+#define DMA_REQUEST_UART4_RX          30U
+#define DMA_REQUEST_UART4_TX          31U
+#if defined (UART5)
+#define DMA_REQUEST_UART5_RX          32U
+#define DMA_REQUEST_UART5_TX          33U
+#endif /* UART5 */
+
+#define DMA_REQUEST_LPUART1_RX        34U
+#define DMA_REQUEST_LPUART1_TX        35U
+
+#define DMA_REQUEST_ADC2              36U
+#if defined (ADC3)
+#define DMA_REQUEST_ADC3              37U
+#endif /* ADC3 */
+#if defined (ADC4)
+#define DMA_REQUEST_ADC4              38U
+#endif /* ADC4 */
+#if defined (ADC5)
+#define DMA_REQUEST_ADC5              39U
+#endif /* ADC5 */
+
+#if defined (QUADSPI)
+#define DMA_REQUEST_QUADSPI           40U
+#endif /* QUADSPI */
+
+#if defined (DAC2)
+#define DMA_REQUEST_DAC2_CHANNEL1     41U
+#endif /* DAC2 */
+
+#define DMA_REQUEST_TIM1_CH1          42U
+#define DMA_REQUEST_TIM1_CH2          43U
+#define DMA_REQUEST_TIM1_CH3          44U
+#define DMA_REQUEST_TIM1_CH4          45U
+#define DMA_REQUEST_TIM1_UP           46U
+#define DMA_REQUEST_TIM1_TRIG         47U
+#define DMA_REQUEST_TIM1_COM          48U
+
+#define DMA_REQUEST_TIM8_CH1          49U
+#define DMA_REQUEST_TIM8_CH2          50U
+#define DMA_REQUEST_TIM8_CH3          51U
+#define DMA_REQUEST_TIM8_CH4          52U
+#define DMA_REQUEST_TIM8_UP           53U
+#define DMA_REQUEST_TIM8_TRIG         54U
+#define DMA_REQUEST_TIM8_COM          55U
+
+#define DMA_REQUEST_TIM2_CH1          56U
+#define DMA_REQUEST_TIM2_CH2          57U
+#define DMA_REQUEST_TIM2_CH3          58U
+#define DMA_REQUEST_TIM2_CH4          59U
+#define DMA_REQUEST_TIM2_UP           60U
+
+#define DMA_REQUEST_TIM3_CH1          61U
+#define DMA_REQUEST_TIM3_CH2          62U
+#define DMA_REQUEST_TIM3_CH3          63U
+#define DMA_REQUEST_TIM3_CH4          64U
+#define DMA_REQUEST_TIM3_UP           65U
+#define DMA_REQUEST_TIM3_TRIG         66U
+
+#define DMA_REQUEST_TIM4_CH1          67U
+#define DMA_REQUEST_TIM4_CH2          68U
+#define DMA_REQUEST_TIM4_CH3          69U
+#define DMA_REQUEST_TIM4_CH4          70U
+#define DMA_REQUEST_TIM4_UP           71U
+
+#if defined (TIM5)
+#define DMA_REQUEST_TIM5_CH1          72U
+#define DMA_REQUEST_TIM5_CH2          73U
+#define DMA_REQUEST_TIM5_CH3          74U
+#define DMA_REQUEST_TIM5_CH4          75U
+#define DMA_REQUEST_TIM5_UP           76U
+#define DMA_REQUEST_TIM5_TRIG         77U
+#endif /* TIM5 */
+
+#define DMA_REQUEST_TIM15_CH1         78U
+#define DMA_REQUEST_TIM15_UP          79U
+#define DMA_REQUEST_TIM15_TRIG        80U
+#define DMA_REQUEST_TIM15_COM         81U
+
+#define DMA_REQUEST_TIM16_CH1         82U
+#define DMA_REQUEST_TIM16_UP          83U
+#define DMA_REQUEST_TIM17_CH1         84U
+#define DMA_REQUEST_TIM17_UP          85U
+
+#if defined (TIM20)
+#define DMA_REQUEST_TIM20_CH1         86U
+#define DMA_REQUEST_TIM20_CH2         87U
+#define DMA_REQUEST_TIM20_CH3         88U
+#define DMA_REQUEST_TIM20_CH4         89U
+#define DMA_REQUEST_TIM20_UP          90U
+#endif /* TIM20 */
+
+#define DMA_REQUEST_AES_IN            91U
+#define DMA_REQUEST_AES_OUT           92U
+
+#if defined (TIM20)
+#define DMA_REQUEST_TIM20_TRIG        93U
+#define DMA_REQUEST_TIM20_COM         94U
+#endif /* TIM20 */
+
+#if defined (HRTIM1)
+#define DMA_REQUEST_HRTIM1_M          95U
+#define DMA_REQUEST_HRTIM1_A          96U
+#define DMA_REQUEST_HRTIM1_B          97U
+#define DMA_REQUEST_HRTIM1_C          98U
+#define DMA_REQUEST_HRTIM1_D          99U
+#define DMA_REQUEST_HRTIM1_E          100U
+#define DMA_REQUEST_HRTIM1_F          101U
+#endif /* HRTIM1 */
+
+#define DMA_REQUEST_DAC3_CHANNEL1     102U
+#define DMA_REQUEST_DAC3_CHANNEL2     103U
+#if defined (DAC4)
+#define DMA_REQUEST_DAC4_CHANNEL1     104U
+#define DMA_REQUEST_DAC4_CHANNEL2     105U
+#endif /* DAC4 */
+
+#if defined (SPI4)
+#define DMA_REQUEST_SPI4_RX           106U
+#define DMA_REQUEST_SPI4_TX           107U
+#endif /* SPI4 */
+
+#define DMA_REQUEST_SAI1_A            108U
+#define DMA_REQUEST_SAI1_B            109U
+
+#define DMA_REQUEST_FMAC_READ         110U
+#define DMA_REQUEST_FMAC_WRITE        111U
+
+#define DMA_REQUEST_CORDIC_READ       112U
+#define DMA_REQUEST_CORDIC_WRITE      113U
+
+#define DMA_REQUEST_UCPD1_RX         114U
+#define DMA_REQUEST_UCPD1_TX         115U
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @{
+  */
+#define DMA_PERIPH_TO_MEMORY         0x00000000U                   /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         DMA_CCR_DIR                   /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         DMA_CCR_MEM2MEM               /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @{
+  */
+#define DMA_PINC_ENABLE        DMA_CCR_PINC              /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE       0x00000000U               /*!< Peripheral increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @{
+  */
+#define DMA_MINC_ENABLE         DMA_CCR_MINC              /*!< Memory increment mode Enable  */
+#define DMA_MINC_DISABLE        0x00000000U               /*!< Memory increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @{
+  */
+#define DMA_PDATAALIGN_BYTE          0x00000000U                  /*!< Peripheral data alignment : Byte     */
+#define DMA_PDATAALIGN_HALFWORD      DMA_CCR_PSIZE_0              /*!< Peripheral data alignment : HalfWord */
+#define DMA_PDATAALIGN_WORD          DMA_CCR_PSIZE_1              /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @{
+  */
+#define DMA_MDATAALIGN_BYTE          0x00000000U                  /*!< Memory data alignment : Byte     */
+#define DMA_MDATAALIGN_HALFWORD      DMA_CCR_MSIZE_0              /*!< Memory data alignment : HalfWord */
+#define DMA_MDATAALIGN_WORD          DMA_CCR_MSIZE_1              /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @{
+  */
+#define DMA_NORMAL         0x00000000U       /*!< Normal mode                  */
+#define DMA_CIRCULAR       DMA_CCR_CIRC      /*!< Circular mode                */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @{
+  */
+#define DMA_PRIORITY_LOW              0x00000000U              /*!< Priority level : Low       */
+#define DMA_PRIORITY_MEDIUM           DMA_CCR_PL_0             /*!< Priority level : Medium    */
+#define DMA_PRIORITY_HIGH             DMA_CCR_PL_1             /*!< Priority level : High      */
+#define DMA_PRIORITY_VERY_HIGH        DMA_CCR_PL               /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @{
+  */
+#define DMA_IT_TC                     DMA_CCR_TCIE
+#define DMA_IT_HT                     DMA_CCR_HTIE
+#define DMA_IT_TE                     DMA_CCR_TEIE
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @{
+  */
+#define DMA_FLAG_GL1                      0x00000001U
+#define DMA_FLAG_TC1                      0x00000002U
+#define DMA_FLAG_HT1                      0x00000004U
+#define DMA_FLAG_TE1                      0x00000008U
+#define DMA_FLAG_GL2                      0x00000010U
+#define DMA_FLAG_TC2                      0x00000020U
+#define DMA_FLAG_HT2                      0x00000040U
+#define DMA_FLAG_TE2                      0x00000080U
+#define DMA_FLAG_GL3                      0x00000100U
+#define DMA_FLAG_TC3                      0x00000200U
+#define DMA_FLAG_HT3                      0x00000400U
+#define DMA_FLAG_TE3                      0x00000800U
+#define DMA_FLAG_GL4                      0x00001000U
+#define DMA_FLAG_TC4                      0x00002000U
+#define DMA_FLAG_HT4                      0x00004000U
+#define DMA_FLAG_TE4                      0x00008000U
+#define DMA_FLAG_GL5                      0x00010000U
+#define DMA_FLAG_TC5                      0x00020000U
+#define DMA_FLAG_HT5                      0x00040000U
+#define DMA_FLAG_TE5                      0x00080000U
+#define DMA_FLAG_GL6                      0x00100000U
+#define DMA_FLAG_TC6                      0x00200000U
+#define DMA_FLAG_HT6                      0x00400000U
+#define DMA_FLAG_TE6                      0x00800000U
+#if defined (DMA1_Channel7)
+#define DMA_FLAG_GL7                      0x01000000U
+#define DMA_FLAG_TC7                      0x02000000U
+#define DMA_FLAG_HT7                      0x04000000U
+#define DMA_FLAG_TE7                      0x08000000U
+#endif /* DMA1_Channel7 */
+#if defined (DMA1_Channel8)
+#define DMA_FLAG_GL8                      0x10000000U
+#define DMA_FLAG_TC8                      0x20000000U
+#define DMA_FLAG_HT8                      0x40000000U
+#define DMA_FLAG_TE8                      0x80000000U
+#endif /* DMA1_Channel8 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset DMA handle state.
+  * @param  __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Enable the specified DMA Channel.
+  * @param  __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
+
+/**
+  * @brief  Disable the specified DMA Channel.
+  * @param  __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
+
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Channel transfer complete flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+
+#if defined (DMA1_Channel8)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\
+   DMA_FLAG_TC8)
+#elif defined (DMA1_Channel6)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
+   DMA_FLAG_TC6)
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Return the current DMA Channel half transfer complete flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified half transfer complete flag index.
+  */
+#if defined (DMA1_Channel8)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\
+   DMA_FLAG_HT8)
+#elif defined (DMA1_Channel6)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
+   DMA_FLAG_HT6)
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Return the current DMA Channel transfer error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined (DMA1_Channel8)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\
+   DMA_FLAG_TE8)
+#elif defined (DMA1_Channel6)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
+   DMA_FLAG_TE6)
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Return the current DMA Channel Global interrupt flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined (DMA1_Channel8)
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\
+   DMA_ISR_GIF8)
+#elif defined (DMA1_Channel6)
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
+   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
+   DMA_ISR_GIF6)
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Get the DMA Channel pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx  Transfer complete flag
+  *            @arg DMA_FLAG_HTx  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx  Transfer error flag
+  *            @arg DMA_FLAG_GLx  Global interrupt flag
+  *         Where x can be from 1 to 8 to select the DMA Channel x flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#if defined (DMA1_Channel8)
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
+                                                  (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
+#elif defined (DMA1_Channel6)
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
+                                                  (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Clear the DMA Channel pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx  Transfer complete flag
+  *            @arg DMA_FLAG_HTx  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx  Transfer error flag
+  *            @arg DMA_FLAG_GLx  Global interrupt flag
+  *         Where x can be from 1 to 8 to select the DMA Channel x flag.
+  * @retval None
+  */
+#if defined (DMA1_Channel8)
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
+                                                    (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
+#else
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
+                                                    (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Enable the specified DMA Channel interrupts.
+  * @param  __HANDLE__ DMA handle
+  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DMA Channel interrupts.
+  * @param  __HANDLE__ DMA handle
+  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_IT_TC  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE  Transfer error interrupt mask
+  * @retval The state of DMA_IT (SET or RESET).
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Return the number of remaining data units in the current DMA Channel transfer.
+  * @param  __HANDLE__ DMA handle
+  * @retval The number of remaining data units in the current DMA Channel transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
+  * @}
+  */
+
+/* Include DMA HAL Extension module */
+#include "stm32g4xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
+                                   uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
+                                          uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @{
+  */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_ALL_REQUEST(REQUEST)    ((REQUEST) <= DMA_REQUEST_UCPD1_TX)
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_HAL_DMA_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h
new file mode 100644
index 0000000..ac8d562
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h
@@ -0,0 +1,264 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_HAL_DMA_EX_H
+#define __STM32G4xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMAEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL DMA Synchro definition
+  */
+
+
+/**
+  * @brief  HAL DMAMUX Synchronization configuration structure definition
+  */
+typedef struct
+{
+  uint32_t SyncSignalID;  /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
+                              This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
+
+  uint32_t SyncPolarity;  /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
+                              This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
+
+  FunctionalState SyncEnable;  /*!< Specifies if the synchronization shall be enabled or disabled
+                                    This parameter can take the value ENABLE or DISABLE*/
+
+
+  FunctionalState EventEnable;    /*!< Specifies if an event shall be generated once the RequestNumber is reached.
+                                       This parameter can take the value ENABLE or DISABLE */
+
+  uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
+                               This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+
+
+} HAL_DMA_MuxSyncConfigTypeDef;
+
+
+/**
+  * @brief  HAL DMAMUX request generator parameters structure definition
+  */
+typedef struct
+{
+  uint32_t SignalID;      /*!< Specifies the ID of the signal used for DMAMUX request generator
+                              This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
+
+  uint32_t Polarity;       /*!< Specifies the polarity of the signal on which the request is generated.
+                             This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
+
+  uint32_t RequestNumber;  /*!< Specifies the number of DMA request that will be generated after a signal event
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+
+} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
+  * @{
+  */
+
+/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
+  * @{
+  */
+#define HAL_DMAMUX1_SYNC_EXTI0                      0U     /*!<  Synchronization Signal is EXTI0  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI1                      1U     /*!<  Synchronization Signal is EXTI1  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI2                      2U     /*!<  Synchronization Signal is EXTI2  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI3                      3U     /*!<  Synchronization Signal is EXTI3  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI4                      4U     /*!<  Synchronization Signal is EXTI4  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI5                      5U     /*!<  Synchronization Signal is EXTI5  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI6                      6U     /*!<  Synchronization Signal is EXTI6  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI7                      7U     /*!<  Synchronization Signal is EXTI7  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI8                      8U     /*!<  Synchronization Signal is EXTI8  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI9                      9U     /*!<  Synchronization Signal is EXTI9  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI10                    10U     /*!<  Synchronization Signal is EXTI10 IT   */
+#define HAL_DMAMUX1_SYNC_EXTI11                    11U     /*!<  Synchronization Signal is EXTI11 IT   */
+#define HAL_DMAMUX1_SYNC_EXTI12                    12U     /*!<  Synchronization Signal is EXTI12 IT   */
+#define HAL_DMAMUX1_SYNC_EXTI13                    13U     /*!<  Synchronization Signal is EXTI13 IT   */
+#define HAL_DMAMUX1_SYNC_EXTI14                    14U     /*!<  Synchronization Signal is EXTI14 IT   */
+#define HAL_DMAMUX1_SYNC_EXTI15                    15U     /*!<  Synchronization Signal is EXTI15 IT   */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT           16U     /*!<  Synchronization Signal is DMAMUX1 Channel0 Event  */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT           17U     /*!<  Synchronization Signal is DMAMUX1 Channel1 Event  */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT           18U     /*!<  Synchronization Signal is DMAMUX1 Channel2 Event  */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT           19U     /*!<  Synchronization Signal is DMAMUX1 Channel3 Event  */
+#define HAL_DMAMUX1_SYNC_LPTIM1_OUT                20U     /*!<  Synchronization Signal is LPTIM1 OUT */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_SYNC_NO_EVENT                               0U    /*!< block synchronization events        */
+#define HAL_DMAMUX_SYNC_RISING     ((uint32_t)DMAMUX_CxCR_SPOL_0)    /*!< synchronize with rising edge events */
+#define HAL_DMAMUX_SYNC_FALLING    ((uint32_t)DMAMUX_CxCR_SPOL_1)    /*!< synchronize with falling edge events */
+#define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL)  /*!< synchronize with rising and falling edge events */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
+  * @{
+  */
+#define HAL_DMAMUX1_REQ_GEN_EXTI0                0U        /*!< Request generator Signal is EXTI0 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI1                1U        /*!< Request generator Signal is EXTI1 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI2                2U        /*!< Request generator Signal is EXTI2 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI3                3U        /*!< Request generator Signal is EXTI3 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI4                4U        /*!< Request generator Signal is EXTI4 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI5                5U        /*!< Request generator Signal is EXTI5 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI6                6U        /*!< Request generator Signal is EXTI6 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI7                7U        /*!< Request generator Signal is EXTI7 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI8                8U        /*!< Request generator Signal is EXTI8 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI9                9U        /*!< Request generator Signal is EXTI9 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI10              10U        /*!< Request generator Signal is EXTI10 IT   */
+#define HAL_DMAMUX1_REQ_GEN_EXTI11              11U        /*!< Request generator Signal is EXTI11 IT   */
+#define HAL_DMAMUX1_REQ_GEN_EXTI12              12U        /*!< Request generator Signal is EXTI12 IT   */
+#define HAL_DMAMUX1_REQ_GEN_EXTI13              13U        /*!< Request generator Signal is EXTI13 IT   */
+#define HAL_DMAMUX1_REQ_GEN_EXTI14              14U        /*!< Request generator Signal is EXTI14 IT   */
+#define HAL_DMAMUX1_REQ_GEN_EXTI15              15U        /*!< Request generator Signal is EXTI15 IT   */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT     16U        /*!< Request generator Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT     17U        /*!< Request generator Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT     18U        /*!< Request generator Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT     19U        /*!< Request generator Signal is DMAMUX1 Channel3 Event */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT          20U        /*!< Request generator Signal is LPTIM1 OUT  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_REQ_GEN_NO_EVENT         0x00000000U           /*!< block request generator events        */
+#define HAL_DMAMUX_REQ_GEN_RISING           DMAMUX_RGxCR_GPOL_0   /*!< generate request on rising edge events */
+#define HAL_DMAMUX_REQ_GEN_FALLING          DMAMUX_RGxCR_GPOL_1   /*!< generate request on falling edge events */
+#define HAL_DMAMUX_REQ_GEN_RISING_FALLING   DMAMUX_RGxCR_GPOL     /*!< generate request on rising and falling edge events */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMAEx_Exported_Functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup DMAEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* ------------------------- REQUEST -----------------------------------------*/
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
+                                                      HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
+/* -------------------------------------------------------------------------- */
+
+/* ------------------------- SYNCHRO -----------------------------------------*/
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
+/* -------------------------------------------------------------------------- */
+
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
+  * @brief    DMAEx private macros
+  * @{
+  */
+
+#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT)
+
+#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)    || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
+
+#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
+
+#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE)   || \
+                                     ((EVENT) == ENABLE))
+
+#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT)
+
+#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)   || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)  || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_HAL_DMA_EX_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h
new file mode 100644
index 0000000..afde61d
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h
@@ -0,0 +1,315 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_EXTI_H
+#define STM32G4xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup EXTI EXTI
+  * @brief EXTI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+  * @{
+  */
+typedef enum
+{
+  HAL_EXTI_COMMON_CB_ID         = 0x00UL
+} EXTI_CallbackIDTypeDef;
+
+
+/**
+  * @brief  EXTI Handle structure definition
+  */
+typedef struct
+{
+  uint32_t Line;                    /*!<  Exti line number */
+  void (* PendingCallback)(void);   /*!<  Exti pending callback */
+} EXTI_HandleTypeDef;
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Line;      /*!< The Exti line to be configured. This parameter
+                           can be a value of @ref EXTI_Line */
+  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
+                           This parameter can be a combination of @ref EXTI_Mode */
+  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
+                           can be a value of @ref EXTI_Trigger */
+  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
+                           This parameter is only possible for line 0 to 15. It
+                           can be a value of @ref EXTI_GPIOSel */
+} EXTI_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | 0x00u)
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | 0x01u)
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | 0x02u)
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | 0x03u)
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | 0x04u)
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | 0x05u)
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | 0x06u)
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | 0x07u)
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | 0x08u)
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | 0x09u)
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | 0x0Au)
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | 0x0Bu)
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | 0x0Cu)
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | 0x0Du)
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | 0x0Eu)
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | 0x0Fu)
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | 0x10u)
+#define EXTI_LINE_17                        (EXTI_CONFIG   | EXTI_REG1 | 0x11u)
+#define EXTI_LINE_18                        (EXTI_DIRECT   | EXTI_REG1 | 0x12u)
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | 0x13u)
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | 0x14u)
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | 0x15u)
+#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | 0x16u)
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | 0x17u)
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | 0x18u)
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | 0x19u)
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Au)
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Bu)
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Cu)
+#define EXTI_LINE_29                        (EXTI_CONFIG   | EXTI_REG1 | 0x1Du)
+#define EXTI_LINE_30                        (EXTI_CONFIG   | EXTI_REG1 | 0x1Eu)
+#define EXTI_LINE_31                        (EXTI_CONFIG   | EXTI_REG1 | 0x1Fu)
+#define EXTI_LINE_32                        (EXTI_CONFIG   | EXTI_REG2 | 0x00u)
+#define EXTI_LINE_33                        (EXTI_CONFIG   | EXTI_REG2 | 0x01u)
+#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_REG2 | 0x02u)
+#define EXTI_LINE_35                        (EXTI_DIRECT   | EXTI_REG2 | 0x03u)
+#define EXTI_LINE_36                        (EXTI_DIRECT   | EXTI_REG2 | 0x04u)
+#define EXTI_LINE_37                        (EXTI_DIRECT   | EXTI_REG2 | 0x05u)
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | 0x06u)
+#define EXTI_LINE_39                        (EXTI_CONFIG   | EXTI_REG2 | 0x07u)
+#define EXTI_LINE_40                        (EXTI_CONFIG   | EXTI_REG2 | 0x08u)
+#define EXTI_LINE_41                        (EXTI_CONFIG   | EXTI_REG2 | 0x09u)
+#define EXTI_LINE_42                        (EXTI_DIRECT   | EXTI_REG2 | 0x0Au)
+#define EXTI_LINE_43                        (EXTI_DIRECT   | EXTI_REG2 | 0x0Bu)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_NONE                      0x00000000U
+#define EXTI_MODE_INTERRUPT                 0x00000001U
+#define EXTI_MODE_EVENT                     0x00000002U
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+#define EXTI_TRIGGER_NONE                   0x00000000U
+#define EXTI_TRIGGER_RISING                 0x00000001U
+#define EXTI_TRIGGER_FALLING                0x00000002U
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000U
+#define EXTI_GPIOB                          0x00000001U
+#define EXTI_GPIOC                          0x00000002U
+#define EXTI_GPIOD                          0x00000003U
+#define EXTI_GPIOE                          0x00000004U
+#define EXTI_GPIOF                          0x00000005U
+#define EXTI_GPIOG                          0x00000006U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+/**
+  * @brief  EXTI Line property definition
+  */
+#define EXTI_PROPERTY_SHIFT                 24U
+#define EXTI_DIRECT                         (0x01uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
+
+/**
+  * @brief  EXTI Register and bit usage
+  */
+#define EXTI_REG_SHIFT                      16U
+#define EXTI_REG1                           (0x00uL << EXTI_REG_SHIFT)
+#define EXTI_REG2                           (0x01uL << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2)
+#define EXTI_PIN_MASK                       0x0000001FU
+
+/**
+  * @brief  EXTI Mask for interrupt & event mode
+  */
+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+  * @brief  EXTI Mask for trigger possibilities
+  */
+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+  * @brief  EXTI Line number
+  */
+#define EXTI_LINE_NB                        44UL
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_LINE(__EXTI_LINE__)          ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
+                                              ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \
+                                               (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \
+                                               (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \
+                                              (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
+                                               (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
+
+#define IS_EXTI_MODE(__EXTI_LINE__)          ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
+                                              (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))
+
+#define IS_EXTI_TRIGGER(__EXTI_LINE__)       (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
+
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
+
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG))
+
+#define IS_EXTI_GPIO_PIN(__PIN__)        ((__PIN__) < 16u)
+
+#define IS_EXTI_PENDING_EDGE(__EDGE__)   (((__EDGE__) == EXTI_TRIGGER_RISING)   || \
+                                          ((__EDGE__) == EXTI_TRIGGER_FALLING)|| \
+                                          ((__EDGE__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_CB(__CB__)               ((__CB__) == HAL_EXTI_COMMON_CB_ID)
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+  * @brief    EXTI Exported Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+  * @brief    Configuration functions
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_EXTI_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h
new file mode 100644
index 0000000..f13aa0b
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h
@@ -0,0 +1,1017 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_flash.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_FLASH_H
+#define STM32G4xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeErase;   /*!< Mass erase or page erase.
+                             This parameter can be a value of @ref FLASH_Type_Erase */
+  uint32_t Banks;       /*!< Select bank to erase.
+                             This parameter must be a value of @ref FLASH_Banks
+                             (FLASH_BANK_BOTH should be used only for mass erase) */
+  uint32_t Page;        /*!< Initial Flash page to erase when page erase is disabled.
+                             This parameter must be a value between 0 and (max number of pages in the bank - 1)
+                             (eg : 127 for 512KB dual bank) */
+  uint32_t NbPages;     /*!< Number of pages to be erased.
+                             This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
+} FLASH_EraseInitTypeDef;
+
+/**
+  * @brief  FLASH Option Bytes Program structure definition
+  */
+typedef struct
+{
+  uint32_t OptionType;     /*!< Option byte to be configured.
+                                This parameter can be a combination of the values of @ref FLASH_OB_Type */
+  uint32_t WRPArea;        /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
+                                Only one WRP area could be programmed at the same time.
+                                This parameter can be value of @ref FLASH_OB_WRP_Area */
+  uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
+                                This parameter must be a value between 0 and (max number of pages in the bank - 1) */
+  uint32_t WRPEndOffset;   /*!< Write protection end offset (used for OPTIONBYTE_WRP).
+                                This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
+  uint32_t RDPLevel;       /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
+                                This parameter can be a value of @ref FLASH_OB_Read_Protection */
+  uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
+                                This parameter can be a combination of @ref FLASH_OB_USER_Type */
+  uint32_t USERConfig;     /*!< Value of the user option byte (used for OPTIONBYTE_USER).
+                                This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
+                                @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
+                                @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
+                                @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
+                                @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2 (*),
+                                @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE,
+                                @ref FLASH_OB_USER_CCMSRAM_RST
+                                @note (*) availability depends on devices */
+  uint32_t PCROPConfig;    /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
+                                This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
+                                and @ref FLASH_OB_PCROP_RDP */
+  uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between begin and end of bank
+                                => Be careful of the bank swapping for the address */
+  uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between PCROP Start address and end of bank */
+  uint32_t BootEntryPoint; /*!< Set the Boot Lock (used for OPTIONBYTE_BOOT_LOCK).
+                                This parameter can be a value of @ref FLASH_OB_Boot_Lock */
+  uint32_t SecBank;        /*!< Bank of securable memory area to be programmed (used for OPTIONBYTE_SEC).
+                                Only one securable memory area could be programmed at the same time.
+                                This parameter can be one of the following values:
+                                FLASH_BANK_1: Securable memory area to be programmed in bank 1
+                                FLASH_BANK_2: Securable memory area to be programmed in bank 2 (*)
+                                @note (*) availability depends on devices */
+  uint32_t SecSize;        /*!< Size of securable memory area to be programmed (used for OPTIONBYTE_SEC),
+                                in number of pages. Securable memory area is starting from first page of the bank.
+                                Only one securable memory could be programmed at the same time.
+                                This parameter must be a value between 0 and (max number of pages in the bank - 1) */
+} FLASH_OBProgramInitTypeDef;
+
+/**
+  * @brief  FLASH Procedure structure definition
+  */
+typedef enum
+{
+  FLASH_PROC_NONE = 0,
+  FLASH_PROC_PAGE_ERASE,
+  FLASH_PROC_MASS_ERASE,
+  FLASH_PROC_PROGRAM,
+  FLASH_PROC_PROGRAM_LAST
+} FLASH_ProcedureTypeDef;
+
+/**
+  * @brief  FLASH Cache structure definition
+  */
+typedef enum
+{
+  FLASH_CACHE_DISABLED = 0,
+  FLASH_CACHE_ICACHE_ENABLED,
+  FLASH_CACHE_DCACHE_ENABLED,
+  FLASH_CACHE_ICACHE_DCACHE_ENABLED
+} FLASH_CacheTypeDef;
+
+/**
+  * @brief  FLASH handle Structure definition
+  */
+typedef struct
+{
+  HAL_LockTypeDef             Lock;              /* FLASH locking object */
+  __IO uint32_t               ErrorCode;         /* FLASH error code */
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;  /* Internal variable to indicate which procedure is ongoing or not in IT context */
+  __IO uint32_t               Address;           /* Internal variable to save address selected for program in IT context */
+  __IO uint32_t               Bank;              /* Internal variable to save current bank selected during erase in IT context */
+  __IO uint32_t               Page;              /* Internal variable to define the current page which is erasing in IT context */
+  __IO uint32_t               NbPagesToErase;    /* Internal variable to save the remaining pages to erase in IT context */
+  __IO FLASH_CacheTypeDef     CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
+} FLASH_ProcessTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASH_Error FLASH Error
+  * @{
+  */
+#define HAL_FLASH_ERROR_NONE      0x00000000U
+#define HAL_FLASH_ERROR_OP        FLASH_FLAG_OPERR
+#define HAL_FLASH_ERROR_PROG      FLASH_FLAG_PROGERR
+#define HAL_FLASH_ERROR_WRP       FLASH_FLAG_WRPERR
+#define HAL_FLASH_ERROR_PGA       FLASH_FLAG_PGAERR
+#define HAL_FLASH_ERROR_SIZ       FLASH_FLAG_SIZERR
+#define HAL_FLASH_ERROR_PGS       FLASH_FLAG_PGSERR
+#define HAL_FLASH_ERROR_MIS       FLASH_FLAG_MISERR
+#define HAL_FLASH_ERROR_FAST      FLASH_FLAG_FASTERR
+#define HAL_FLASH_ERROR_RD        FLASH_FLAG_RDERR
+#define HAL_FLASH_ERROR_OPTV      FLASH_FLAG_OPTVERR
+#define HAL_FLASH_ERROR_ECCC      FLASH_FLAG_ECCC
+#define HAL_FLASH_ERROR_ECCD      FLASH_FLAG_ECCD
+#if defined (FLASH_OPTR_DBANK)
+#define HAL_FLASH_ERROR_ECCC2     FLASH_FLAG_ECCC2
+#define HAL_FLASH_ERROR_ECCD2     FLASH_FLAG_ECCD2
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Type_Erase FLASH Erase Type
+  * @{
+  */
+#define FLASH_TYPEERASE_PAGES     0x00U                    /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE 0x01U                    /*!<Flash mass erase activation*/
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Banks FLASH Banks
+  * @{
+  */
+#define FLASH_BANK_1              0x00000001U              /*!< Bank 1   */
+#if defined (FLASH_OPTR_DBANK)
+#define FLASH_BANK_2              0x00000002U              /*!< Bank 2   */
+#define FLASH_BANK_BOTH           (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
+#else
+#define FLASH_BANK_BOTH           FLASH_BANK_1             /*!< Bank 1   */
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup FLASH_Type_Program FLASH Program Type
+  * @{
+  */
+#define FLASH_TYPEPROGRAM_DOUBLEWORD    0x00U              /*!< Program a double-word (64-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_FAST          0x01U              /*!< Fast program a 32 row double-word (64-bit) at a specified address.
+                                                                And another 32 row double-word (64-bit) will be programmed */
+#define FLASH_TYPEPROGRAM_FAST_AND_LAST 0x02U              /*!< Fast program a 32 row double-word (64-bit) at a specified address.
+                                                                And this is the last 32 row double-word (64-bit) programmed */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
+  * @{
+  */
+#define OPTIONBYTE_WRP            0x01U                    /*!< WRP option byte configuration */
+#define OPTIONBYTE_RDP            0x02U                    /*!< RDP option byte configuration */
+#define OPTIONBYTE_USER           0x04U                    /*!< USER option byte configuration */
+#define OPTIONBYTE_PCROP          0x08U                    /*!< PCROP option byte configuration */
+#define OPTIONBYTE_BOOT_LOCK      0x10U                    /*!< Boot lock option byte configuration */
+#define OPTIONBYTE_SEC            0x20U                    /*!< Securable memory option byte configuration */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
+  * @{
+  */
+#define OB_WRPAREA_BANK1_AREAA    0x00U                    /*!< Flash Bank 1 Area A */
+#define OB_WRPAREA_BANK1_AREAB    0x01U                    /*!< Flash Bank 1 Area B */
+#if defined (FLASH_OPTR_DBANK)
+#define OB_WRPAREA_BANK2_AREAA    0x02U                    /*!< Flash Bank 2 Area A */
+#define OB_WRPAREA_BANK2_AREAB    0x04U                    /*!< Flash Bank 2 Area B */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_Boot_Lock FLASH Boot Lock
+  * @{
+  */
+#define OB_BOOT_LOCK_DISABLE      0x00000000U              /*!< Boot Lock Disable */
+#define OB_BOOT_LOCK_ENABLE       FLASH_SEC1R_BOOT_LOCK    /*!< Boot Lock Enable */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
+  * @{
+  */
+#define OB_RDP_LEVEL_0            0xAAU
+#define OB_RDP_LEVEL_1            0xBBU
+#define OB_RDP_LEVEL_2            0xCCU                    /*!< Warning: When enabling read protection level 2 
+                                                                it's no more possible to go back to level 1 or 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
+  * @{
+  */
+#define OB_USER_BOR_LEV           0x00000001U              /*!< BOR reset Level */
+#define OB_USER_nRST_STOP         0x00000002U              /*!< Reset generated when entering the stop mode */
+#define OB_USER_nRST_STDBY        0x00000004U              /*!< Reset generated when entering the standby mode */
+#define OB_USER_IWDG_SW           0x00000008U              /*!< Independent watchdog selection */
+#define OB_USER_IWDG_STOP         0x00000010U              /*!< Independent watchdog counter freeze in stop mode */
+#define OB_USER_IWDG_STDBY        0x00000020U              /*!< Independent watchdog counter freeze in standby mode */
+#define OB_USER_WWDG_SW           0x00000040U              /*!< Window watchdog selection */
+#if defined (FLASH_OPTR_DBANK)
+#define OB_USER_BFB2              0x00000080U              /*!< Dual-bank boot */
+#define OB_USER_DBANK             0x00000100U              /*!< Single bank with 128-bits data or two banks with 64-bits data */
+#endif
+#if defined (FLASH_OPTR_PB4_PUPEN)
+#define OB_USER_PB4_PUPEN         0x00000100U              /*!< USB power delivery dead-battery/TDI pull-up */
+#endif
+#define OB_USER_nBOOT1            0x00000200U              /*!< Boot configuration */
+#define OB_USER_SRAM_PE           0x00000400U              /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */
+#define OB_USER_CCMSRAM_RST       0x00000800U              /*!< CCMSRAM Erase when system reset */
+#define OB_USER_nRST_SHDW         0x00001000U              /*!< Reset generated when entering the shutdown mode */
+#define OB_USER_nSWBOOT0          0x00002000U              /*!< Software BOOT0 */
+#define OB_USER_nBOOT0            0x00004000U              /*!< nBOOT0 option bit */
+#define OB_USER_NRST_MODE         0x00008000U              /*!< Reset pin configuration */
+#define OB_USER_IRHEN             0x00010000U              /*!< Internal Reset Holder enable */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
+  * @{
+  */
+#define OB_BOR_LEVEL_0            FLASH_OPTR_BOR_LEV_0     /*!< Reset level threshold is around 1.7V */
+#define OB_BOR_LEVEL_1            FLASH_OPTR_BOR_LEV_1     /*!< Reset level threshold is around 2.0V */
+#define OB_BOR_LEVEL_2            FLASH_OPTR_BOR_LEV_2     /*!< Reset level threshold is around 2.2V */
+#define OB_BOR_LEVEL_3            FLASH_OPTR_BOR_LEV_3     /*!< Reset level threshold is around 2.5V */
+#define OB_BOR_LEVEL_4            FLASH_OPTR_BOR_LEV_4     /*!< Reset level threshold is around 2.8V */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
+  * @{
+  */
+#define OB_STOP_RST               0x00000000U              /*!< Reset generated when entering the stop mode */
+#define OB_STOP_NORST             FLASH_OPTR_nRST_STOP     /*!< No reset generated when entering the stop mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
+  * @{
+  */
+#define OB_STANDBY_RST            0x00000000U              /*!< Reset generated when entering the standby mode */
+#define OB_STANDBY_NORST          FLASH_OPTR_nRST_STDBY    /*!< No reset generated when entering the standby mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
+  * @{
+  */
+#define OB_SHUTDOWN_RST           0x00000000U              /*!< Reset generated when entering the shutdown mode */
+#define OB_SHUTDOWN_NORST         FLASH_OPTR_nRST_SHDW     /*!< No reset generated when entering the shutdown mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
+  * @{
+  */
+#define OB_IWDG_HW                0x00000000U              /*!< Hardware independent watchdog */
+#define OB_IWDG_SW                FLASH_OPTR_IWDG_SW       /*!< Software independent watchdog */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
+  * @{
+  */
+#define OB_IWDG_STOP_FREEZE       0x00000000U              /*!< Independent watchdog counter is frozen in Stop mode */
+#define OB_IWDG_STOP_RUN          FLASH_OPTR_IWDG_STOP     /*!< Independent watchdog counter is running in Stop mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
+  * @{
+  */
+#define OB_IWDG_STDBY_FREEZE      0x00000000U              /*!< Independent watchdog counter is frozen in Standby mode */
+#define OB_IWDG_STDBY_RUN         FLASH_OPTR_IWDG_STDBY    /*!< Independent watchdog counter is running in Standby mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
+  * @{
+  */
+#define OB_WWDG_HW                0x00000000U              /*!< Hardware window watchdog */
+#define OB_WWDG_SW                FLASH_OPTR_WWDG_SW       /*!< Software window watchdog */
+/**
+  * @}
+  */
+
+#if defined (FLASH_OPTR_DBANK)
+/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
+  * @{
+  */
+#define OB_BFB2_DISABLE           0x00000000U              /*!< Dual-bank boot disable */
+#define OB_BFB2_ENABLE            FLASH_OPTR_BFB2          /*!< Dual-bank boot enable */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type
+  * @{
+  */
+#define OB_DBANK_128_BITS         0x00000000U              /*!< Single-bank with 128-bits data */
+#define OB_DBANK_64_BITS          FLASH_OPTR_DBANK         /*!< Dual-bank with 64-bits data */
+/**
+  * @}
+  */
+#endif
+
+#if defined (FLASH_OPTR_PB4_PUPEN)
+/** @defgroup FLASH_OB_USER_PB4_PUPEN FLASH Option Bytes User PB4 PUPEN bit
+  * @{
+  */
+#define OB_PB4_PUPEN_DISABLE      0x00000000U              /*!< USB power delivery dead-battery enabled/ TDI pull-up deactivated */
+#define OB_PB4_PUPEN_ENABLE       FLASH_OPTR_PB4_PUPEN     /*!< USB power delivery dead-battery disabled/ TDI pull-up activated */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
+  * @{
+  */
+#define OB_BOOT1_SRAM             0x00000000U              /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
+#define OB_BOOT1_SYSTEM           FLASH_OPTR_nBOOT1        /*!< System memory is selected as boot space (if BOOT0=1) */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_SRAM_PE FLASH Option Bytes User SRAM Parity Check Type
+  * @{
+  */
+#define OB_SRAM_PARITY_ENABLE     0x00000000U              /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */
+#define OB_SRAM_PARITY_DISABLE    FLASH_OPTR_SRAM_PE       /*!< SRAM parity check disable (first 32kB of SRAM1 + CCM SRAM) */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_CCMSRAM_RST FLASH Option Bytes User CCMSRAM Erase On Reset Type
+  * @{
+  */
+#define OB_CCMSRAM_RST_ERASE      0x00000000U              /*!< CCMSRAM erased when a system reset occurs */
+#define OB_CCMSRAM_RST_NOT_ERASE  FLASH_OPTR_CCMSRAM_RST   /*!< CCMSRAM is not erased when a system reset occurs */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
+  * @{
+  */
+#define OB_BOOT0_FROM_OB          0x00000000U              /*!< BOOT0 taken from the option bit nBOOT0 */
+#define OB_BOOT0_FROM_PIN         FLASH_OPTR_nSWBOOT0      /*!< BOOT0 taken from PB8/BOOT0 pin */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
+  * @{
+  */
+#define OB_nBOOT0_RESET           0x00000000U              /*!< nBOOT0 = 0 */
+#define OB_nBOOT0_SET             FLASH_OPTR_nBOOT0        /*!< nBOOT0 = 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_NRST_MODE FLASH Option Bytes User NRST mode bit
+  * @{
+  */
+#define OB_NRST_MODE_INPUT_ONLY   FLASH_OPTR_NRST_MODE_0   /*!< Reset pin is in Reset input mode only */
+#define OB_NRST_MODE_GPIO         FLASH_OPTR_NRST_MODE_1   /*!< Reset pin is in GPIO mode only */
+#define OB_NRST_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE     /*!< Reset pin is in reset input and output mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_USER_INTERNAL_RESET_HOLDER FLASH Option Bytes User internal reset holder bit
+  * @{
+  */
+#define OB_IRH_DISABLE            0x00000000U              /*!< Internal Reset holder disable */
+#define OB_IRH_ENABLE             FLASH_OPTR_IRHEN         /*!< Internal Reset holder enable */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
+  * @{
+  */
+#define OB_PCROP_RDP_NOT_ERASE    0x00000000U              /*!< PCROP area is not erased when the RDP level 
+                                                                is decreased from Level 1 to Level 0 */
+#define OB_PCROP_RDP_ERASE        FLASH_PCROP1ER_PCROP_RDP /*!< PCROP area is erased when the RDP level is 
+                                                                decreased from Level 1 to Level 0 (full mass erase) */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */
+#define FLASH_LATENCY_0           FLASH_ACR_LATENCY_0WS    /*!< FLASH Zero wait state */
+#define FLASH_LATENCY_1           FLASH_ACR_LATENCY_1WS    /*!< FLASH One wait state */
+#define FLASH_LATENCY_2           FLASH_ACR_LATENCY_2WS    /*!< FLASH Two wait states */
+#define FLASH_LATENCY_3           FLASH_ACR_LATENCY_3WS    /*!< FLASH Three wait states */
+#define FLASH_LATENCY_4           FLASH_ACR_LATENCY_4WS    /*!< FLASH Four wait states */
+#define FLASH_LATENCY_5           FLASH_ACR_LATENCY_5WS    /*!< FLASH Five wait state */
+#define FLASH_LATENCY_6           FLASH_ACR_LATENCY_6WS    /*!< FLASH Six wait state */
+#define FLASH_LATENCY_7           FLASH_ACR_LATENCY_7WS    /*!< FLASH Seven wait states */
+#define FLASH_LATENCY_8           FLASH_ACR_LATENCY_8WS    /*!< FLASH Eight wait states */
+#define FLASH_LATENCY_9           FLASH_ACR_LATENCY_9WS    /*!< FLASH Nine wait states */
+#define FLASH_LATENCY_10          FLASH_ACR_LATENCY_10WS   /*!< FLASH Ten wait state */
+#define FLASH_LATENCY_11          FLASH_ACR_LATENCY_11WS   /*!< FLASH Eleven wait state */
+#define FLASH_LATENCY_12          FLASH_ACR_LATENCY_12WS   /*!< FLASH Twelve wait states */
+#define FLASH_LATENCY_13          FLASH_ACR_LATENCY_13WS   /*!< FLASH Thirteen wait states */
+#define FLASH_LATENCY_14          FLASH_ACR_LATENCY_14WS   /*!< FLASH Fourteen wait states */
+#define FLASH_LATENCY_15          FLASH_ACR_LATENCY_15WS   /*!< FLASH Fifteen wait states */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Keys FLASH Keys
+  * @{
+  */
+#define FLASH_KEY1                0x45670123U              /*!< Flash key1 */
+#define FLASH_KEY2                0xCDEF89ABU              /*!< Flash key2: used with FLASH_KEY1 
+                                                                to unlock the FLASH registers access */
+
+#define FLASH_PDKEY1              0x04152637U              /*!< Flash power down key1 */
+#define FLASH_PDKEY2              0xFAFBFCFDU              /*!< Flash power down key2: used with FLASH_PDKEY1 
+                                                                to unlock the RUN_PD bit in FLASH_ACR */
+
+#define FLASH_OPTKEY1             0x08192A3BU              /*!< Flash option byte key1 */
+#define FLASH_OPTKEY2             0x4C5D6E7FU              /*!< Flash option byte key2: used with FLASH_OPTKEY1 
+                                                                to allow option bytes operations */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flags FLASH Flags Definition
+  * @{
+  */
+#define FLASH_FLAG_EOP            FLASH_SR_EOP             /*!< FLASH End of operation flag */
+#define FLASH_FLAG_OPERR          FLASH_SR_OPERR           /*!< FLASH Operation error flag */
+#define FLASH_FLAG_PROGERR        FLASH_SR_PROGERR         /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR         FLASH_SR_WRPERR          /*!< FLASH Write protection error flag */
+#define FLASH_FLAG_PGAERR         FLASH_SR_PGAERR          /*!< FLASH Programming alignment error flag */
+#define FLASH_FLAG_SIZERR         FLASH_SR_SIZERR          /*!< FLASH Size error flag  */
+#define FLASH_FLAG_PGSERR         FLASH_SR_PGSERR          /*!< FLASH Programming sequence error flag */
+#define FLASH_FLAG_MISERR         FLASH_SR_MISERR          /*!< FLASH Fast programming data miss error flag */
+#define FLASH_FLAG_FASTERR        FLASH_SR_FASTERR         /*!< FLASH Fast programming error flag */
+#define FLASH_FLAG_RDERR          FLASH_SR_RDERR           /*!< FLASH PCROP read error flag */
+#define FLASH_FLAG_OPTVERR        FLASH_SR_OPTVERR         /*!< FLASH Option validity error flag  */
+#define FLASH_FLAG_BSY            FLASH_SR_BSY             /*!< FLASH Busy flag */
+#define FLASH_FLAG_ECCC           FLASH_ECCR_ECCC          /*!< FLASH ECC correction in 64 LSB bits */
+#define FLASH_FLAG_ECCD           FLASH_ECCR_ECCD          /*!< FLASH ECC detection in 64 LSB bits */
+#if defined (FLASH_OPTR_DBANK)
+#define FLASH_FLAG_ECCC2          FLASH_ECCR_ECCC2         /*!< FLASH ECC correction in 64 MSB bits (mode 128 bits only) */
+#define FLASH_FLAG_ECCD2          FLASH_ECCR_ECCD2         /*!< FLASH ECC detection in 64 MSB bits (mode 128 bits only) */
+#endif
+
+#define FLASH_FLAG_SR_ERRORS      (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
+                                   FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \
+                                   FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \
+                                   FLASH_FLAG_OPTVERR)
+#if defined (FLASH_OPTR_DBANK)
+#define FLASH_FLAG_ECCR_ERRORS    (FLASH_FLAG_ECCC    | FLASH_FLAG_ECCD    | FLASH_FLAG_ECCC2  | FLASH_FLAG_ECCD2)
+#else
+#define FLASH_FLAG_ECCR_ERRORS    (FLASH_FLAG_ECCC    | FLASH_FLAG_ECCD)
+#endif
+#define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
+  * @brief FLASH Interrupt definition
+  * @{
+  */
+#define FLASH_IT_EOP              FLASH_CR_EOPIE           /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_OPERR            FLASH_CR_ERRIE           /*!< Error Interrupt source */
+#define FLASH_IT_RDERR            FLASH_CR_RDERRIE         /*!< PCROP Read Error Interrupt source*/
+#define FLASH_IT_ECCC            (FLASH_ECCR_ECCIE >> 24U) /*!< ECC Correction Interrupt source */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+  * @brief macros to control FLASH features
+  * @{
+  */
+
+/**
+  * @brief  Set the FLASH Latency.
+  * @param  __LATENCY__ FLASH Latency.
+  *         This parameter can be one of the following values :
+  *           @arg FLASH_LATENCY_0:  FLASH Zero wait state
+  *           @arg FLASH_LATENCY_1:  FLASH One wait state
+  *           @arg FLASH_LATENCY_2:  FLASH Two wait states
+  *           @arg FLASH_LATENCY_3:  FLASH Three wait states
+  *           @arg FLASH_LATENCY_4:  FLASH Four wait states
+  *           @arg FLASH_LATENCY_5:  FLASH Five wait states
+  *           @arg FLASH_LATENCY_6:  FLASH Six wait states
+  *           @arg FLASH_LATENCY_7:  FLASH Seven wait states
+  *           @arg FLASH_LATENCY_8:  FLASH Eight wait states 
+  *           @arg FLASH_LATENCY_9:  FLASH Nine wait states 
+  *           @arg FLASH_LATENCY_10: FLASH Ten wait state
+  *           @arg FLASH_LATENCY_11: FLASH Eleven wait state
+  *           @arg FLASH_LATENCY_12: FLASH Twelve wait states
+  *           @arg FLASH_LATENCY_13: FLASH Thirteen wait states
+  *           @arg FLASH_LATENCY_14: FLASH Fourteen wait states
+  *           @arg FLASH_LATENCY_15: FLASH Fifteen wait states
+  * @retval None
+  */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__)    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
+
+/**
+  * @brief  Get the FLASH Latency.
+  * @retval FLASH_Latency.
+  *         This parameter can be one of the following values :
+  *           @arg FLASH_LATENCY_0:  FLASH Zero wait state
+  *           @arg FLASH_LATENCY_1:  FLASH One wait state
+  *           @arg FLASH_LATENCY_2:  FLASH Two wait states
+  *           @arg FLASH_LATENCY_3:  FLASH Three wait states
+  *           @arg FLASH_LATENCY_4:  FLASH Four wait states
+  *           @arg FLASH_LATENCY_5:  FLASH Five wait states
+  *           @arg FLASH_LATENCY_6:  FLASH Six wait states
+  *           @arg FLASH_LATENCY_7:  FLASH Seven wait states
+  *           @arg FLASH_LATENCY_8:  FLASH Eight wait states 
+  *           @arg FLASH_LATENCY_9:  FLASH Nine wait states 
+  *           @arg FLASH_LATENCY_10: FLASH Ten wait state
+  *           @arg FLASH_LATENCY_11: FLASH Eleven wait state
+  *           @arg FLASH_LATENCY_12: FLASH Twelve wait states
+  *           @arg FLASH_LATENCY_13: FLASH Thirteen wait states
+  *           @arg FLASH_LATENCY_14: FLASH Fourteen wait states
+  *           @arg FLASH_LATENCY_15: FLASH Fifteen wait states
+  */
+#define __HAL_FLASH_GET_LATENCY()               READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
+
+/**
+  * @brief  Enable the FLASH prefetch buffer.
+  * @retval None
+  */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
+
+/**
+  * @brief  Disable the FLASH prefetch buffer.
+  * @retval None
+  */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
+
+/**
+  * @brief  Enable the FLASH instruction cache.
+  * @retval none
+  */
+#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
+
+/**
+  * @brief  Disable the FLASH instruction cache.
+  * @retval none
+  */
+#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
+
+/**
+  * @brief  Enable the FLASH data cache.
+  * @retval none
+  */
+#define __HAL_FLASH_DATA_CACHE_ENABLE()         SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
+
+/**
+  * @brief  Disable the FLASH data cache.
+  * @retval none
+  */
+#define __HAL_FLASH_DATA_CACHE_DISABLE()        CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
+
+/**
+  * @brief  Reset the FLASH instruction Cache.
+  * @note   This function must be used only when the Instruction Cache is disabled.
+  * @retval None
+  */
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
+                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
+                                                   } while (0)
+
+/**
+  * @brief  Reset the FLASH data Cache.
+  * @note   This function must be used only when the data Cache is disabled.
+  * @retval None
+  */
+#define __HAL_FLASH_DATA_CACHE_RESET()          do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \
+                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
+                                                   } while (0)
+
+/**
+  * @brief  Enable the FLASH power down during Low-power run mode.
+  * @note   Writing this bit to 1, automatically the keys are
+  *         lost and a new unlock sequence is necessary to re-write it to 0.
+  */
+#define __HAL_FLASH_POWER_DOWN_ENABLE()         do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
+                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
+                                                     SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);   \
+                                                   } while (0)
+
+/**
+  * @brief  Disable the FLASH power down during Low-power run mode.
+  * @note   Writing this bit to 0, automatically the keys are
+  *         lost and a new unlock sequence is necessary to re-write it to 1.
+  */
+#define __HAL_FLASH_POWER_DOWN_DISABLE()        do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
+                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
+                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
+                                                   } while (0)
+
+/**
+  * @brief  Enable the FLASH power down during Low-Power sleep mode
+  * @retval none
+  */
+#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
+
+/**
+  * @brief  Disable the FLASH power down during Low-Power sleep mode
+  * @retval none
+  */
+#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
+  *  @brief macros to handle FLASH interrupts
+  * @{
+  */
+
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__ FLASH interrupt
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_OPERR: Error Interrupt
+  *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
+  *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
+  * @retval none
+  */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
+                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
+                                                   } while (0)
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__ FLASH interrupt
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_OPERR: Error Interrupt
+  *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
+  *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
+  * @retval none
+  */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
+                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
+                                                   } while (0)
+
+/**
+  * @brief  Check whether the specified FLASH flag is set or not.
+  * @param  __FLAG__ specifies the FLASH flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+  *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+  *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
+  *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+  *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+  *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+  *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
+  *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
+  *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
+  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+  *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
+  *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits
+  *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits
+  *     @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only)
+  *     @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only)
+  * @note  (*) availability depends on devices
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG(__FLAG__)          ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \
+                                                 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
+                                                 (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))
+
+/**
+  * @brief  Clear the FLASH's pending flags.
+  * @param  __FLAG__ specifies the FLASH flags to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+  *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+  *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
+  *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+  *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+  *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+  *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
+  *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
+  *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
+  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+  *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits
+  *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits
+  *     @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only)
+  *     @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only)
+  *     @arg FLASH_FLAG_SR_ERRORS: FLASH All SR errors flags
+  *     @arg FLASH_FLAG_ECCR_ERRORS: FLASH All ECCR errors flags
+  * @note  (*) availability depends on devices
+  * @retval None
+  */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
+                                                     if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
+                                                   } while (0)
+/**
+  * @}
+  */
+
+/* Include FLASH HAL Extended module */
+#include "stm32g4xx_hal_flash_ex.h"
+#include "stm32g4xx_hal_flash_ramfunc.h"
+
+/* Exported variables --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Variables FLASH Exported Variables
+  * @{
+  */
+extern FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+  * @{
+  */
+
+/* Program operation functions  ***********************************************/
+/** @addtogroup FLASH_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+/* FLASH IRQ handler method */
+void               HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup FLASH_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef  HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef  HAL_FLASH_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef  HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef  HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef  HAL_FLASH_OB_Launch(void);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup FLASH_Exported_Functions_Group3
+  * @{
+  */
+uint32_t HAL_FLASH_GetError(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Private_Functions
+  * @{
+  */
+HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+  * @{
+  */
+#define FLASH_SIZE_DATA_REGISTER        FLASHSIZE_BASE
+
+#if defined (FLASH_OPTR_DBANK)
+#define FLASH_SIZE                      ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200UL << 10U) : \
+                                        (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
+#define FLASH_BANK_SIZE                 (FLASH_SIZE >> 1)
+#define FLASH_PAGE_NB                   128U
+#define FLASH_PAGE_SIZE_128_BITS        0x1000U /* 4 KB */
+#else
+#define FLASH_SIZE                      ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \
+                                        (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
+#define FLASH_BANK_SIZE                 (FLASH_SIZE)
+#define FLASH_PAGE_NB                   ((FLASH_SIZE == 0x00080000U) ? 256U : \
+                                        ((FLASH_SIZE == 0x00040000U) ? 128U : 64U))
+#endif
+
+#define FLASH_PAGE_SIZE                 0x800U  /* 2 KB */
+
+#define FLASH_TIMEOUT_VALUE             1000U   /* 1 s  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+  *  @{
+  */
+
+#define IS_FLASH_TYPEERASE(VALUE)          (((VALUE) == FLASH_TYPEERASE_PAGES) || \
+                                            ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#if defined (FLASH_OPTR_DBANK)
+#define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2)  || \
+                                            ((BANK) == FLASH_BANK_BOTH))
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2))
+#else
+#define IS_FLASH_BANK(BANK)                ((BANK) == FLASH_BANK_1)
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      ((BANK) == FLASH_BANK_1)
+#endif
+
+#define IS_FLASH_TYPEPROGRAM(VALUE)        (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
+                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
+                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
+
+#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE)))
+
+#define IS_FLASH_OTP_ADDRESS(ADDRESS)      (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))
+
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
+
+#define IS_FLASH_PAGE(PAGE)                ((PAGE) < FLASH_PAGE_NB)
+
+#define IS_OPTIONBYTE(VALUE)               (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \
+                                            OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_SEC)))
+
+#if defined (FLASH_OPTR_DBANK)
+#define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
+                                            ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
+#else
+#define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
+#endif
+
+#define IS_OB_BOOT_LOCK(VALUE)             (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE))
+
+#define IS_OB_RDP_LEVEL(LEVEL)             (((LEVEL) == OB_RDP_LEVEL_0) ||\
+                                            ((LEVEL) == OB_RDP_LEVEL_1) ||\
+                                            ((LEVEL) == OB_RDP_LEVEL_2))
+
+#define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U))
+
+#define IS_OB_USER_BOR_LEVEL(LEVEL)        (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
+                                            ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
+                                            ((LEVEL) == OB_BOR_LEVEL_4))
+
+#define IS_OB_USER_STOP(VALUE)             (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
+
+#define IS_OB_USER_STANDBY(VALUE)          (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
+
+#define IS_OB_USER_SHUTDOWN(VALUE)         (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
+
+#define IS_OB_USER_IWDG(VALUE)             (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
+
+#define IS_OB_USER_IWDG_STOP(VALUE)        (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
+
+#define IS_OB_USER_IWDG_STDBY(VALUE)       (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
+
+#define IS_OB_USER_WWDG(VALUE)             (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
+
+#if defined (FLASH_OPTR_DBANK)
+#define IS_OB_USER_BFB2(VALUE)             (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
+
+#define IS_OB_USER_DBANK(VALUE)            (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS))
+#endif
+
+#if defined (FLASH_OPTR_PB4_PUPEN)
+#define IS_OB_USER_PB4_PUPEN(VALUE)        (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE))
+#endif
+
+#define IS_OB_USER_BOOT1(VALUE)            (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
+
+#define IS_OB_USER_SRAM_PARITY(VALUE)      (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE))
+
+#define IS_OB_USER_CCMSRAM_RST(VALUE)      (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE))
+
+#define IS_OB_USER_SWBOOT0(VALUE)          (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
+
+#define IS_OB_USER_BOOT0(VALUE)            (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET))
+
+#define IS_OB_USER_NRST_MODE(VALUE)        (((VALUE) == OB_NRST_MODE_GPIO) || ((VALUE) == OB_NRST_MODE_INPUT_ONLY) || \
+                                            ((VALUE) == OB_NRST_MODE_INPUT_OUTPUT))
+
+#define IS_OB_USER_IRHEN(VALUE)            (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE))
+
+#define IS_OB_PCROP_RDP(VALUE)             (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
+
+#define IS_OB_SECMEM_SIZE(VALUE)           ((VALUE) <= FLASH_PAGE_NB)
+
+#define IS_FLASH_LATENCY(LATENCY)          (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
+                                            ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
+                                            ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
+                                            ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \
+                                            ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \
+                                            ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \
+                                            ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \
+                                            ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_FLASH_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h
new file mode 100644
index 0000000..b785f6f
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h
@@ -0,0 +1,89 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_FLASH_EX_H
+#define STM32G4xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/* Extended Program operation functions  *************************************/
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank);
+void              HAL_FLASHEx_EnableDebugger(void);
+void              HAL_FLASHEx_DisableDebugger(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup FLASHEx_Private_Functions
+  * @{
+  */
+void              FLASH_PageErase(uint32_t Page, uint32_t Banks);
+void              FLASH_FlushCaches(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_FLASH_EX_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h
new file mode 100644
index 0000000..3f0f1bb
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h
@@ -0,0 +1,74 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_flash_ramfunc.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH RAMFUNC driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_FLASH_RAMFUNC_H
+#define STM32G4xx_FLASH_RAMFUNC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH_RAMFUNC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
+#if defined (FLASH_OPTR_DBANK)
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_FLASH_RAMFUNC_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h
new file mode 100644
index 0000000..1b710c1
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h
@@ -0,0 +1,326 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_GPIO_H
+#define STM32G4xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+/**
+  * @brief   GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins */
+
+  uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode */
+
+  uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull */
+
+  uint32_t Speed;      /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
+                            This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+} GPIO_InitTypeDef;
+
+/**
+  * @brief  GPIO Bit SET and Bit RESET enumeration
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0U,
+  GPIO_PIN_SET
+} GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+/** @defgroup GPIO_pins GPIO pins
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              (0x0000FFFFU) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode GPIO mode
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0x00WX00YZ
+  *           - W  : EXTI trigger detection on 3 bits
+  *           - X  : EXTI mode (IT or Event) on 2 bits
+  *           - Y  : Output type (Push Pull or Open Drain) on 1 bit
+  *           - Z  : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
+  * @{
+  */ 
+#define  GPIO_MODE_INPUT                        MODE_INPUT                                                  /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    (MODE_OUTPUT | OUTPUT_PP)                                   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    (MODE_OUTPUT | OUTPUT_OD)                                   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        (MODE_AF | OUTPUT_PP)                                       /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        (MODE_AF | OUTPUT_OD)                                       /*!< Alternate Function Open Drain Mode    */
+
+#define  GPIO_MODE_ANALOG                       MODE_ANALOG                                                 /*!< Analog Mode  */
+    
+#define  GPIO_MODE_IT_RISING                    (MODE_INPUT | EXTI_IT | TRIGGER_RISING)                     /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)                    /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+ 
+#define  GPIO_MODE_EVT_RISING                   (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)                     /*!< External Event Mode with Rising edge trigger detection             */
+#define  GPIO_MODE_EVT_FALLING                  (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)                    /*!< External Event Mode with Falling edge trigger detection            */
+#define  GPIO_MODE_EVT_RISING_FALLING           (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Event Mode with Rising/Falling edge trigger detection     */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed GPIO speed
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define  GPIO_SPEED_FREQ_LOW        (0x00000000U)   /*!< range up to 5 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_MEDIUM     (0x00000001U)   /*!< range  5 MHz to 25 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_HIGH       (0x00000002U)   /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_VERY_HIGH  (0x00000003U)   /*!< range 50 MHz to 120 MHz, please refer to the product datasheet */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_pull GPIO pull
+  * @brief GPIO Pull-Up or Pull-Down Activation
+  * @{
+  */
+#define  GPIO_NOPULL        (0x00000000U)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        (0x00000001U)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      (0x00000002U)   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Check whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clear the EXTI's line pending flags.
+  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     (EXTI->PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Check whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clear the EXTI's line pending bits.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)       (EXTI->PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+#define GPIO_MODE_Pos                           0U
+#define GPIO_MODE                               (0x3UL << GPIO_MODE_Pos)
+#define MODE_INPUT                              (0x0UL << GPIO_MODE_Pos)
+#define MODE_OUTPUT                             (0x1UL << GPIO_MODE_Pos)
+#define MODE_AF                                 (0x2UL << GPIO_MODE_Pos)
+#define MODE_ANALOG                             (0x3UL << GPIO_MODE_Pos)
+#define OUTPUT_TYPE_Pos                         4U
+#define OUTPUT_TYPE                             (0x1UL << OUTPUT_TYPE_Pos)
+#define OUTPUT_PP                               (0x0UL << OUTPUT_TYPE_Pos)
+#define OUTPUT_OD                               (0x1UL << OUTPUT_TYPE_Pos)
+#define EXTI_MODE_Pos                           16U
+#define EXTI_MODE                               (0x3UL << EXTI_MODE_Pos)
+#define EXTI_IT                                 (0x1UL << EXTI_MODE_Pos)
+#define EXTI_EVT                                (0x2UL << EXTI_MODE_Pos)
+#define TRIGGER_MODE_Pos                         20U
+#define TRIGGER_MODE                            (0x7UL << TRIGGER_MODE_Pos)
+#define TRIGGER_RISING                          (0x1UL << TRIGGER_MODE_Pos)
+#define TRIGGER_FALLING                         (0x2UL << TRIGGER_MODE_Pos)
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
+                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+
+#define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
+                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
+                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
+                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\
+                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\
+                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
+                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
+                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                                     ((__MODE__) == GPIO_MODE_ANALOG))
+
+#define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\
+                                     ((__PULL__) == GPIO_PULLUP)   || \
+                                     ((__PULL__) == GPIO_PULLDOWN))
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extended module */
+#include "stm32g4xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+  *  @brief    GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *****************************/
+void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+  *  @brief    IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void              HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_GPIO_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h
new file mode 100644
index 0000000..ec466f9
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h
@@ -0,0 +1,340 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_GPIO_EX_H
+#define STM32G4xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIOEx GPIOEx
+  * @brief GPIO Extended HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
+  * @{
+  */
+
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping   */
+#if defined(TIM5)
+#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping   */
+#endif /* TIM5 */
+#define GPIO_AF1_TIM16         ((uint8_t)0x01)  /* TIM16 Alternate Function mapping  */
+#define GPIO_AF1_TIM17         ((uint8_t)0x01)  /* TIM17 Alternate Function mapping  */
+#define GPIO_AF1_TIM17_COMP1   ((uint8_t)0x01)  /* TIM17/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF1_TIM15         ((uint8_t)0x01)  /* TIM15 Alternate Function mapping  */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping     */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping  */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping  */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping  */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping  */
+#if defined(TIM5)
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping  */
+#endif /* TIM5 */
+#define GPIO_AF2_TIM8          ((uint8_t)0x02)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16         ((uint8_t)0x02)  /* TIM16 Alternate Function mapping */
+#if defined(TIM20)
+#define GPIO_AF2_TIM20         ((uint8_t)0x02)  /* TIM20 Alternate Function mapping */
+#endif /* TIM20 */
+#define GPIO_AF2_TIM1_COMP1    ((uint8_t)0x02)  /* TIM1/COMP1 Break in Alternate Function mapping   */
+#define GPIO_AF2_TIM15_COMP1   ((uint8_t)0x02)  /* TIM15/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF2_TIM16_COMP1   ((uint8_t)0x02)  /* TIM16/COMP1 Break in Alternate Function mapping  */
+#if defined(TIM20)
+#define GPIO_AF2_TIM20_COMP1   ((uint8_t)0x02)  /* TIM20/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF2_TIM20_COMP2   ((uint8_t)0x02)  /* TIM20/COMP2 Break in Alternate Function mapping  */
+#endif /* TIM20 */
+#define GPIO_AF2_I2C3          ((uint8_t)0x02)  /* I2C3 Alternate Function mapping  */
+#define GPIO_AF2_COMP1         ((uint8_t)0x02)  /* COMP1 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM15         ((uint8_t)0x03)  /* TIM15 Alternate Function mapping   */
+#if defined(TIM20)
+#define GPIO_AF3_TIM20         ((uint8_t)0x03)  /* TIM20 Alternate Function mapping   */
+#endif /* TIM20 */
+#define GPIO_AF3_UCPD1         ((uint8_t)0x03)  /* UCPD1 Alternate Function mapping   */
+#define GPIO_AF3_I2C3          ((uint8_t)0x03)  /* I2C3 Alternate Function mapping    */
+#if defined(I2C4)
+#define GPIO_AF3_I2C4          ((uint8_t)0x03)  /* I2C4 Alternate Function mapping    */
+#endif /* I2C4 */
+#if defined(HRTIM1)
+#define GPIO_AF3_HRTIM1        ((uint8_t)0x03)  /* HRTIM1 Alternate Function mapping  */
+#endif /* HRTIM1 */
+#if defined(QUADSPI)
+#define GPIO_AF3_QUADSPI       ((uint8_t)0x03)  /* QUADSPI Alternate Function mapping */
+#endif /* QUADSPI */
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping    */
+#define GPIO_AF3_SAI1          ((uint8_t)0x03)  /* SAI1 Alternate Function mapping  */
+#define GPIO_AF3_COMP3         ((uint8_t)0x03)  /* COMP3 Alternate Function mapping */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_TIM1          ((uint8_t)0x04)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF4_TIM8          ((uint8_t)0x04)  /* TIM8 Alternate Function mapping    */
+#define GPIO_AF4_TIM16         ((uint8_t)0x04)  /* TIM16 Alternate Function mapping   */
+#define GPIO_AF4_TIM17         ((uint8_t)0x04)  /* TIM17 Alternate Function mapping   */
+#define GPIO_AF4_TIM8_COMP1    ((uint8_t)0x04)  /* TIM8/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping    */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping    */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping    */
+#if defined(I2C4)
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping    */
+#endif /* I2C4 */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping       */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping       */
+#if defined(SPI4)
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping       */
+#endif /* SPI4 */
+#define GPIO_AF5_IR            ((uint8_t)0x05)  /* IR Alternate Function mapping         */
+#define GPIO_AF5_TIM8          ((uint8_t)0x05)  /* TIM8 Alternate Function mapping       */
+#define GPIO_AF5_TIM8_COMP1    ((uint8_t)0x05)  /* TIM8/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF5_UART4         ((uint8_t)0x05)  /* UART4 Alternate Function mapping      */
+#if defined(UART5)
+#define GPIO_AF5_UART5         ((uint8_t)0x05)  /* UART5 Alternate Function mapping      */
+#endif /* UART5 */
+#define GPIO_AF5_I2S2ext       ((uint8_t)0x05)  /* I2S2ext_SD Alternate Function mapping */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2 Alternate Function mapping       */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping       */
+#define GPIO_AF6_TIM1          ((uint8_t)0x06)  /* TIM1 Alternate Function mapping       */
+#if defined(TIM5)
+#define GPIO_AF6_TIM5          ((uint8_t)0x06)  /* TIM5 Alternate Function mapping       */
+#endif /* TIM5 */
+#define GPIO_AF6_TIM8          ((uint8_t)0x06)  /* TIM8 Alternate Function mapping       */
+#if defined(TIM20)
+#define GPIO_AF6_TIM20         ((uint8_t)0x06)  /* TIM20 Alternate Function mapping      */
+#endif /* TIM20 */
+#define GPIO_AF6_TIM1_COMP1    ((uint8_t)0x06)  /* TIM1/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF6_TIM1_COMP2    ((uint8_t)0x06)  /* TIM1/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF6_TIM8_COMP2    ((uint8_t)0x06)  /* TIM8/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF6_IR            ((uint8_t)0x06)  /* IR Alternate Function mapping         */
+#define GPIO_AF6_I2S3ext       ((uint8_t)0x06)  /* I2S3ext_SD Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping  */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping  */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping  */
+#if defined(COMP5)
+#define GPIO_AF7_COMP5         ((uint8_t)0x07)  /* COMP5 Alternate Function mapping   */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define GPIO_AF7_COMP6         ((uint8_t)0x07)  /* COMP6 Alternate Function mapping   */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define GPIO_AF7_COMP7         ((uint8_t)0x07)  /* COMP7 Alternate Function mapping   */
+#endif /* COMP7 */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_COMP1         ((uint8_t)0x08)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF8_COMP2         ((uint8_t)0x08)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF8_COMP3         ((uint8_t)0x08)  /* COMP3 Alternate Function mapping   */
+#define GPIO_AF8_COMP4         ((uint8_t)0x08)  /* COMP4 Alternate Function mapping   */
+#if defined(COMP5)
+#define GPIO_AF8_COMP5         ((uint8_t)0x08)  /* COMP5 Alternate Function mapping   */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define GPIO_AF8_COMP6         ((uint8_t)0x08)  /* COMP6 Alternate Function mapping   */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define GPIO_AF8_COMP7         ((uint8_t)0x08)  /* COMP7 Alternate Function mapping   */
+#endif /* COMP7 */
+#define GPIO_AF8_I2C3          ((uint8_t)0x08)  /* I2C3 Alternate Function mapping    */
+#if defined(I2C4)
+#define GPIO_AF8_I2C4          ((uint8_t)0x08)  /* I2C4 Alternate Function mapping    */
+#endif /* I2C4 */
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */
+#if defined(UART5)
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */
+#endif /* UART5 */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_TIM1          ((uint8_t)0x09)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF9_TIM8          ((uint8_t)0x09)  /* TIM8 Alternate Function mapping    */
+#define GPIO_AF9_TIM15         ((uint8_t)0x09)  /* TIM15 Alternate Function mapping   */
+#define GPIO_AF9_TIM1_COMP1    ((uint8_t)0x09)  /* TIM1/COMP1 Break in Alternate Function mapping   */
+#define GPIO_AF9_TIM8_COMP1    ((uint8_t)0x09)  /* TIM8/COMP1 Break in Alternate Function mapping   */
+#define GPIO_AF9_TIM15_COMP1   ((uint8_t)0x09)  /* TIM15/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF9_FDCAN1        ((uint8_t)0x09)  /* FDCAN1 Alternate Function mapping  */
+#if defined(FDCAN2)
+#define GPIO_AF9_FDCAN2        ((uint8_t)0x09)  /* FDCAN2 Alternate Function mapping  */
+#endif /* FDCAN2 */
+
+/**
+  * @brief   AF 10 selection
+  */
+#define GPIO_AF10_TIM2         ((uint8_t)0x0A)  /* TIM2 Alternate Function mapping    */
+#define GPIO_AF10_TIM3         ((uint8_t)0x0A)  /* TIM3 Alternate Function mapping    */
+#define GPIO_AF10_TIM4         ((uint8_t)0x0A)  /* TIM4 Alternate Function mapping    */
+#define GPIO_AF10_TIM8         ((uint8_t)0x0A)  /* TIM8 Alternate Function mapping    */
+#define GPIO_AF10_TIM17        ((uint8_t)0x0A)  /* TIM17 Alternate Function mapping   */
+#define GPIO_AF10_TIM8_COMP2   ((uint8_t)0x0A)  /* TIM8/COMP2 Break in Alternate Function mapping    */
+#define GPIO_AF10_TIM17_COMP1  ((uint8_t)0x0A)  /* TIM17/COMP1 Break in Alternate Function mapping   */
+#if defined(QUADSPI)
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* OctoSPI Manager Port 1 Alternate Function mapping */
+#endif /* QUADSPI */
+
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_FDCAN1       ((uint8_t)0x0B)  /* FDCAN1 Alternate Function mapping  */
+#if defined(FDCAN3)
+#define GPIO_AF11_FDCAN3       ((uint8_t)0x0B)  /* FDCAN3 Alternate Function mapping  */
+#endif /* FDCAN3 */
+#define GPIO_AF11_TIM1         ((uint8_t)0x0B)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF11_TIM8         ((uint8_t)0x0B)  /* TIM8 Alternate Function mapping    */
+#define GPIO_AF11_TIM8_COMP1   ((uint8_t)0x0B)  /* TIM8/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF11_LPTIM1       ((uint8_t)0x0B)  /* LPTIM1 Alternate Function mapping  */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_LPUART1      ((uint8_t)0x0C)  /* LPUART1 Alternate Function mapping */
+#define GPIO_AF12_TIM1         ((uint8_t)0x0C)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF12_TIM1_COMP1   ((uint8_t)0x0C)  /* TIM1/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF12_TIM1_COMP2   ((uint8_t)0x0C)  /* TIM1/COMP2 Break in Alternate Function mapping  */
+#if defined(HRTIM1)
+#define GPIO_AF12_HRTIM1       ((uint8_t)0x0C)  /* HRTIM1 Alternate Function mapping  */
+#endif /* HRTIM1 */
+#if defined(FMC_BANK1)
+#define GPIO_AF12_FMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */
+#endif /* FMC_BANK1 */
+#define GPIO_AF12_SAI1         ((uint8_t)0x0C)  /* SAI1 Alternate Function mapping  */
+
+/**
+  * @brief   AF 13 selection
+  */
+#if defined(HRTIM1)
+#define GPIO_AF13_HRTIM1       ((uint8_t)0x0D)  /* HRTIM1 Alternate Function mapping  */
+#endif /* HRTIM1 */
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping  */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping   */
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping   */
+#define GPIO_AF14_UCPD1        ((uint8_t)0x0E)  /* UCPD1 Alternate Function mapping  */
+#define GPIO_AF14_SAI1         ((uint8_t)0x0E)  /* SAI1 Alternate Function mapping  */
+#define GPIO_AF14_UART4        ((uint8_t)0x0E)  /* UART4 Alternate Function mapping      */
+#if defined(UART5)
+#define GPIO_AF14_UART5        ((uint8_t)0x0E)  /* UART5 Alternate Function mapping      */
+#endif /* UART5 */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
+  * @{
+  */
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0UL :\
+                                      ((__GPIOx__) == (GPIOB))? 1UL :\
+                                      ((__GPIOx__) == (GPIOC))? 2UL :\
+                                      ((__GPIOx__) == (GPIOD))? 3UL :\
+                                      ((__GPIOx__) == (GPIOE))? 4UL :\
+                                      ((__GPIOx__) == (GPIOF))? 5UL : 6UL)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_GPIO_EX_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h
new file mode 100644
index 0000000..a2ae591
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h
@@ -0,0 +1,835 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_I2C_H
+#define STM32G4xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+  * @{
+  */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+  * @brief  I2C Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                     This parameter calculated by referring to I2C initialization section
+                                     in Reference manual */
+
+  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
+                                     This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                     This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+
+  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
+                                     This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+
+  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
+                                     This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing
+                                     mode is selected.
+                                     This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+
+  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
+                                     This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+
+  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
+                                     This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+
+} I2C_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :\n
+  *          b7-b6  Error information\n
+  *             00 : No Error\n
+  *             01 : Abort (Abort user request on going)\n
+  *             10 : Timeout\n
+  *             11 : Error\n
+  *          b5     Peripheral initialization status\n
+  *             0  : Reset (peripheral not initialized)\n
+  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
+  *          b4     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b3\n
+  *             0  : Ready or Busy (No Listen mode ongoing)\n
+  *             1  : Listen (peripheral in Address Listen Mode)\n
+  *          b2     Intrinsic process state\n
+  *             0  : Ready\n
+  *             1  : Busy (peripheral busy with some configuration or internal operations)\n
+  *          b1     Rx state\n
+  *             0  : Ready (no Rx operation ongoing)\n
+  *             1  : Busy (Rx operation ongoing)\n
+  *          b0     Tx state\n
+  *             0  : Ready (no Tx operation ongoing)\n
+  *             1  : Busy (Tx operation ongoing)
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+  * @brief  I2C handle Structure definition
+  * @{
+  */
+typedef struct __I2C_HandleTypeDef
+{
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
+
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
+
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
+
+  uint16_t                   XferSize;       /*!< I2C transfer size                         */
+
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
+
+  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
+                                                  be a value of @ref I2C_XFEROPTIONS */
+
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
+
+  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+  /*!< I2C transfer IRQ handler function pointer */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
+
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
+
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
+
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
+
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
+
+  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Listen Complete callback              */
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Memory Tx Transfer completed callback */
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Memory Rx Transfer completed callback */
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Error callback                        */
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Abort callback                        */
+
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+  /*!< I2C Slave Address Match callback */
+
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Msp DeInit callback                   */
+
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL I2C Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
+
+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2C Callback pointer definition
+  */
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
+/*!< pointer to an I2C callback function */
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
+                                          uint16_t AddrMatchCode);
+/*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
+  * @{
+  */
+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  I2C_OTHER_FRAME                (0x000000AAU)
+#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
+#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
+  * @{
+  */
+#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
+#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
+#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
+#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
+#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
+#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
+#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
+#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)
+#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
+#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
+  * @{
+  */
+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
+#define I2C_DIRECTION_RECEIVE           (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
+  * @{
+  */
+#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
+#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
+#define  I2C_SOFTEND_MODE               (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
+  * @{
+  */
+#define  I2C_NO_STARTSTOP               (0x00000000U)
+#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+  * @{
+  */
+#define I2C_FLAG_TXE                    I2C_ISR_TXE
+#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
+#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
+#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
+#define I2C_FLAG_AF                     I2C_ISR_NACKF
+#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
+#define I2C_FLAG_TC                     I2C_ISR_TC
+#define I2C_FLAG_TCR                    I2C_ISR_TCR
+#define I2C_FLAG_BERR                   I2C_ISR_BERR
+#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
+#define I2C_FLAG_OVR                    I2C_ISR_OVR
+#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
+#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
+#define I2C_FLAG_DIR                    I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                             \
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;  \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;       \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                                  } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/** @brief  Enable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified I2C interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & \
+                                                                   (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified I2C flag is set or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *            @arg @ref I2C_FLAG_BUSY    Bus busy
+  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define I2C_FLAG_MASK  (0x0001FFFFU)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
+                                                    (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
+                                                    ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
+                                                    ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                         (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                        (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+/**
+  * @}
+  */
+
+/* Include I2C HAL Extended module */
+#include "stm32g4xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+                                           pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions  ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                          uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                         uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                         uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                        uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                   uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+                                        uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                             uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                            uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                      uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                 uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                               uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                              uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                             uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                  uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                 uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                 uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                uint32_t XferOptions);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+  * @{
+  */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  * @{
+  */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+  * @{
+  */
+
+#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
+                                         ((MASK) == I2C_OA2_MASK01) || \
+                                         ((MASK) == I2C_OA2_MASK02) || \
+                                         ((MASK) == I2C_OA2_MASK03) || \
+                                         ((MASK) == I2C_OA2_MASK04) || \
+                                         ((MASK) == I2C_OA2_MASK05) || \
+                                         ((MASK) == I2C_OA2_MASK06) || \
+                                         ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
+                                         ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
+                                         ((MODE) == I2C_AUTOEND_MODE) || \
+                                         ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
+                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
+                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+                                         ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
+                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
+                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
+                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
+                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
+                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= \
+                                                   (uint32_t)~((uint32_t)(I2C_CR2_SADD   | I2C_CR2_HEAD10R | \
+                                                                          I2C_CR2_NBYTES | I2C_CR2_RELOAD  | \
+                                                                          I2C_CR2_RD_WRN)))
+
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
+                                                              >> 16U))
+#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
+                                                             >> 16U))
+#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
+                                                                         (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
+                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+                                                                 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
+                                                                (~I2C_CR2_RD_WRN)) : \
+                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+                                                                 (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
+                                                                (~I2C_CR2_RD_WRN)))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
+                                                    ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32g4xx_hal_i2c.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32G4xx_HAL_I2C_H */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h
new file mode 100644
index 0000000..9fda573
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h
@@ -0,0 +1,175 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_I2C_EX_H
+#define STM32G4xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+  * @{
+  */
+#define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
+#if defined(SYSCFG_CFGR1_I2C4_FMP)
+#define I2C_FASTMODEPLUS_I2C4           SYSCFG_CFGR1_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C4           (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported  */
+#endif /* SYSCFG_CFGR1_I2C4_FMP */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+/**
+  * @}
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
+  * @{
+  */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+  * @{
+  */
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+                                         ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
+
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
+                                         ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32g4xx_hal_i2c_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_I2C_EX_H */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h
new file mode 100644
index 0000000..48b51e1
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h
@@ -0,0 +1,1003 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_pcd.h
+  * @author  MCD Application Team
+  * @brief   Header file of PCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_PCD_H
+#define STM32G4xx_HAL_PCD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_ll_usb.h"
+
+#if defined (USB)
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PCD_Exported_Types PCD Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PCD State structure definition
+  */
+typedef enum
+{
+  HAL_PCD_STATE_RESET   = 0x00,
+  HAL_PCD_STATE_READY   = 0x01,
+  HAL_PCD_STATE_ERROR   = 0x02,
+  HAL_PCD_STATE_BUSY    = 0x03,
+  HAL_PCD_STATE_TIMEOUT = 0x04
+} PCD_StateTypeDef;
+
+/* Device LPM suspend state */
+typedef enum
+{
+  LPM_L0 = 0x00, /* on */
+  LPM_L1 = 0x01, /* LPM L1 sleep */
+  LPM_L2 = 0x02, /* suspend */
+  LPM_L3 = 0x03, /* off */
+} PCD_LPM_StateTypeDef;
+
+typedef enum
+{
+  PCD_LPM_L0_ACTIVE = 0x00, /* on */
+  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+} PCD_LPM_MsgTypeDef;
+
+typedef enum
+{
+  PCD_BCD_ERROR                     = 0xFF,
+  PCD_BCD_CONTACT_DETECTION         = 0xFE,
+  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
+  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
+  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
+  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
+
+} PCD_BCD_MsgTypeDef;
+
+
+
+
+
+typedef USB_TypeDef        PCD_TypeDef;
+typedef USB_CfgTypeDef     PCD_InitTypeDef;
+typedef USB_EPTypeDef      PCD_EPTypeDef;
+
+
+/**
+  * @brief  PCD Handle Structure definition
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+typedef struct __PCD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  PCD_TypeDef             *Instance;   /*!< Register base address             */
+  PCD_InitTypeDef         Init;        /*!< PCD required parameters           */
+  __IO uint8_t            USB_Address; /*!< USB Address                       */
+  PCD_EPTypeDef           IN_ep[8];   /*!< IN endpoint parameters             */
+  PCD_EPTypeDef           OUT_ep[8];  /*!< OUT endpoint parameters            */
+  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status             */
+  __IO PCD_StateTypeDef   State;       /*!< PCD communication state           */
+  __IO  uint32_t          ErrorCode;   /*!< PCD Error code                    */
+  uint32_t                Setup[12];   /*!< Setup packet buffer               */
+  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                         */
+  uint32_t                BESL;
+
+
+  uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .
+                                       This parameter can be set to ENABLE or DISABLE        */
+
+  uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.
+                                       This parameter can be set to ENABLE or DISABLE        */
+  void                    *pData;      /*!< Pointer to upper stack Handler */
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */
+  void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */
+  void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */
+  void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */
+  void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */
+  void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */
+  void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */
+
+  void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */
+  void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */
+  void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */
+  void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */
+  void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */
+  void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */
+
+  void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */
+  void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+} PCD_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Include PCD HAL Extended module */
+#include "stm32g4xx_hal_pcd_ex.h"
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+/** @defgroup PCD_Speed PCD Speed
+  * @{
+  */
+#define PCD_SPEED_FULL               USBD_FS_SPEED
+/**
+  * @}
+  */
+
+/** @defgroup PCD_PHY_Module PCD PHY Module
+  * @{
+  */
+#define PCD_PHY_ULPI                 1U
+#define PCD_PHY_EMBEDDED             2U
+#define PCD_PHY_UTMI                 3U
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Error_Code_definition PCD Error Code definition
+  * @brief  PCD Error Code definition
+  * @{
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+#define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+  *  @brief macros to handle interrupts and specific clock configurations
+  * @{
+  */
+
+
+#define __HAL_PCD_ENABLE(__HANDLE__)                              (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__)                             (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)             ((USB_ReadInterrupts((__HANDLE__)->Instance)\
+                                                                    & (__INTERRUPT__)) == (__INTERRUPT__))
+
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)           (((__HANDLE__)->Instance->ISTR)\
+                                                                   &= (uint16_t)(~(__INTERRUPT__)))
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                         EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                        EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
+  * @brief  HAL USB OTG PCD Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */
+  HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */
+  HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */
+  HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */
+  HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */
+  HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */
+  HAL_PCD_DISCONNECT_CB_ID   = 0x07,      /*!< USB PCD Disconnect callback ID   */
+
+  HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */
+  HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */
+
+} HAL_PCD_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
+  * @brief  HAL USB OTG PCD Callback pointer definition
+  * @{
+  */
+
+typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */
+typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */
+typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */
+typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
+typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */
+typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */
+typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */
+
+/**
+  * @}
+  */
+
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+                                           HAL_PCD_CallbackIDTypeDef CallbackID,
+                                           pPCD_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
+                                             HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+                                                       pPCD_DataOutStageCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+                                                      pPCD_DataInStageCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+                                                       pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+                                                      pPCD_IsoInIncpltCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
+                                              pPCD_BcdCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
+                                              pPCD_LpmCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+                                  uint16_t ep_mps, uint8_t ep_type);
+
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+                                     uint8_t *pBuf, uint32_t len);
+
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+                                      uint8_t *pBuf, uint32_t len);
+
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+  * @{
+  */
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
+  * @{
+  */
+
+
+#define USB_WAKEUP_EXTI_LINE                                          (0x1U << 18)  /*!< USB FS EXTI Line WakeUp Interrupt */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_EP0_MPS PCD EP0 MPS
+  * @{
+  */
+#define PCD_EP0MPS_64                                                 EP_MPS_64
+#define PCD_EP0MPS_32                                                 EP_MPS_32
+#define PCD_EP0MPS_16                                                 EP_MPS_16
+#define PCD_EP0MPS_08                                                 EP_MPS_8
+/**
+  * @}
+  */
+
+/** @defgroup PCD_ENDP PCD ENDP
+  * @{
+  */
+#define PCD_ENDP0                                                     0U
+#define PCD_ENDP1                                                     1U
+#define PCD_ENDP2                                                     2U
+#define PCD_ENDP3                                                     3U
+#define PCD_ENDP4                                                     4U
+#define PCD_ENDP5                                                     5U
+#define PCD_ENDP6                                                     6U
+#define PCD_ENDP7                                                     7U
+/**
+  * @}
+  */
+
+/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
+  * @{
+  */
+#define PCD_SNG_BUF                                                   0U
+#define PCD_DBL_BUF                                                   1U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+  * @{
+  */
+
+/********************  Bit definition for USB_COUNTn_RX register  *************/
+#define USB_CNTRX_NBLK_MSK                    (0x1FU << 10)
+#define USB_CNTRX_BLSIZE                      (0x1U << 15)
+
+/* SetENDPOINT */
+#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue)  (*(__IO uint16_t *)\
+                                                    (&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
+
+/* GetENDPOINT */
+#define PCD_GET_ENDPOINT(USBx, bEpNum)             (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
+
+/* ENDPOINT transfer */
+#define USB_EP0StartXfer                           USB_EPStartXfer
+
+/**
+  * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wType Endpoint Type.
+  * @retval None
+  */
+#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum))\
+                                                              & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
+
+
+/**
+  * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval Endpoint Type
+  */
+#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
+
+/**
+  * @brief free buffer used from the application realizing it to the line
+  *         toggles bit SW_BUF in the double buffered endpoint register
+  * @param USBx USB device.
+  * @param   bEpNum, bDir
+  * @retval None
+  */
+#define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
+  do { \
+    if ((bDir) == 0U) \
+    { \
+      /* OUT double buffered endpoint */ \
+      PCD_TX_DTOG((USBx), (bEpNum)); \
+    } \
+    else if ((bDir) == 1U) \
+    { \
+      /* IN double buffered endpoint */ \
+      PCD_RX_DTOG((USBx), (bEpNum)); \
+    } \
+  } while(0)
+
+/**
+  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wState new state
+  * @retval None
+  */
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
+  do { \
+    uint16_t _wRegVal; \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
+    /* toggle first bit ? */ \
+    if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
+    { \
+      _wRegVal ^= USB_EPTX_DTOG1; \
+    } \
+    /* toggle second bit ?  */ \
+    if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
+    { \
+      _wRegVal ^= USB_EPTX_DTOG2; \
+    } \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+  } while(0) /* PCD_SET_EP_TX_STATUS */
+
+/**
+  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wState new state
+  * @retval None
+  */
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
+  do { \
+    uint16_t _wRegVal; \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
+    /* toggle first bit ? */ \
+    if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
+    { \
+      _wRegVal ^= USB_EPRX_DTOG1; \
+    } \
+    /* toggle second bit ? */ \
+    if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
+    { \
+      _wRegVal ^= USB_EPRX_DTOG2; \
+    } \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+  } while(0) /* PCD_SET_EP_RX_STATUS */
+
+/**
+  * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wStaterx new state.
+  * @param  wStatetx new state.
+  * @retval None
+  */
+#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
+  do { \
+    uint16_t _wRegVal; \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
+    /* toggle first bit ? */ \
+    if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
+    { \
+      _wRegVal ^= USB_EPRX_DTOG1; \
+    } \
+    /* toggle second bit ? */ \
+    if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
+    { \
+      _wRegVal ^= USB_EPRX_DTOG2; \
+    } \
+    /* toggle first bit ? */ \
+    if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
+    { \
+      _wRegVal ^= USB_EPTX_DTOG1; \
+    } \
+    /* toggle second bit ?  */ \
+    if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
+    { \
+      _wRegVal ^= USB_EPTX_DTOG2; \
+    } \
+    \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+  } while(0) /* PCD_SET_EP_TXRX_STATUS */
+
+/**
+  * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
+  *         /STAT_RX[1:0])
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval status
+  */
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
+
+/**
+  * @brief  sets directly the VALID tx/rx-status into the endpoint register
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_EP_TX_VALID(USBx, bEpNum)      (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
+#define PCD_SET_EP_RX_VALID(USBx, bEpNum)      (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
+
+/**
+  * @brief  checks stall condition in an endpoint.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval TRUE = endpoint in stall condition.
+  */
+#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
+#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
+
+/**
+  * @brief  set & clear EP_KIND bit.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_EP_KIND(USBx, bEpNum) \
+  do { \
+    uint16_t _wRegVal; \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
+    \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
+  } while(0) /* PCD_SET_EP_KIND */
+
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
+  do { \
+    uint16_t _wRegVal; \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
+    \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+  } while(0) /* PCD_CLEAR_EP_KIND */
+
+/**
+  * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_OUT_STATUS(USBx, bEpNum)       PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)     PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+  * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_BULK_EP_DBUF(USBx, bEpNum)     PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum)   PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval None
+  */
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
+  do { \
+    uint16_t _wRegVal; \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
+    \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
+  } while(0) /* PCD_CLEAR_RX_EP_CTR */
+
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
+  do { \
+    uint16_t _wRegVal; \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
+    \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
+  } while(0) /* PCD_CLEAR_TX_EP_CTR */
+
+/**
+  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval None
+  */
+#define PCD_RX_DTOG(USBx, bEpNum) \
+  do { \
+    uint16_t _wEPVal; \
+    \
+    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
+    \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
+  } while(0) /* PCD_RX_DTOG */
+
+#define PCD_TX_DTOG(USBx, bEpNum) \
+  do { \
+    uint16_t _wEPVal; \
+    \
+    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
+    \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
+  } while(0) /* PCD_TX_DTOG */
+/**
+  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval None
+  */
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
+  do { \
+    uint16_t _wRegVal; \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
+    \
+    if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
+    { \
+      PCD_RX_DTOG((USBx), (bEpNum)); \
+    } \
+  } while(0) /* PCD_CLEAR_RX_DTOG */
+
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
+  do { \
+    uint16_t _wRegVal; \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
+    \
+    if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
+    { \
+      PCD_TX_DTOG((USBx), (bEpNum)); \
+    } \
+  } while(0) /* PCD_CLEAR_TX_DTOG */
+
+/**
+  * @brief  Sets address in an endpoint register.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  bAddr Address.
+  * @retval None
+  */
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
+  do { \
+    uint16_t _wRegVal; \
+    \
+    _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
+    \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+  } while(0) /* PCD_SET_EP_ADDRESS */
+
+/**
+  * @brief  Gets address in an endpoint register.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval None
+  */
+#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
+
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
+                                                    + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
+                                                    + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+
+
+/**
+  * @brief  sets address of the tx/rx buffer.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wAddr address to be set (must be word aligned).
+  * @retval None
+  */
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
+  do { \
+    __IO uint16_t *_wRegVal; \
+    uint32_t _wRegBase = (uint32_t)USBx; \
+    \
+    _wRegBase += (uint32_t)(USBx)->BTABLE; \
+    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
+    *_wRegVal = ((wAddr) >> 1) << 1; \
+  } while(0) /* PCD_SET_EP_TX_ADDRESS */
+
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
+  do { \
+    __IO uint16_t *_wRegVal; \
+    uint32_t _wRegBase = (uint32_t)USBx; \
+    \
+    _wRegBase += (uint32_t)(USBx)->BTABLE; \
+    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
+    *_wRegVal = ((wAddr) >> 1) << 1; \
+  } while(0) /* PCD_SET_EP_RX_ADDRESS */
+
+/**
+  * @brief  Gets address of the tx/rx buffer.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval address of the buffer.
+  */
+#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+  * @brief  Sets counter of rx buffer with no. of blocks.
+  * @param  pdwReg Register pointer
+  * @param  wCount Counter.
+  * @param  wNBlocks no. of Blocks.
+  * @retval None
+  */
+#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
+  do { \
+    (wNBlocks) = (wCount) >> 5; \
+    if (((wCount) & 0x1fU) == 0U) \
+    { \
+      (wNBlocks)--; \
+    } \
+    *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
+  } while(0) /* PCD_CALC_BLK32 */
+
+#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
+  do { \
+    (wNBlocks) = (wCount) >> 1; \
+    if (((wCount) & 0x1U) != 0U) \
+    { \
+      (wNBlocks)++; \
+    } \
+    *(pdwReg) = (uint16_t)((wNBlocks) << 10); \
+  } while(0) /* PCD_CALC_BLK2 */
+
+#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
+  do { \
+    uint32_t wNBlocks; \
+    \
+    if ((wCount) > 62U) \
+    { \
+      PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
+    } \
+    else \
+    { \
+      if ((wCount) == 0U) \
+      { \
+        *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
+        *(pdwReg) |= USB_CNTRX_BLSIZE; \
+      } \
+      else \
+      { \
+        PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
+      } \
+    } \
+  } while(0) /* PCD_SET_EP_CNT_RX_REG */
+
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
+  do { \
+    uint32_t _wRegBase = (uint32_t)(USBx); \
+    __IO uint16_t *pdwReg; \
+    \
+    _wRegBase += (uint32_t)(USBx)->BTABLE; \
+    pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
+    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
+  } while(0)
+
+/**
+  * @brief  sets counter for the tx/rx buffer.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wCount Counter value.
+  * @retval None
+  */
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
+  do { \
+    uint32_t _wRegBase = (uint32_t)(USBx); \
+    __IO uint16_t *_wRegVal; \
+    \
+    _wRegBase += (uint32_t)(USBx)->BTABLE; \
+    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
+    *_wRegVal = (uint16_t)(wCount); \
+  } while(0)
+
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
+  do { \
+    uint32_t _wRegBase = (uint32_t)(USBx); \
+    __IO uint16_t *_wRegVal; \
+    \
+    _wRegBase += (uint32_t)(USBx)->BTABLE; \
+    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
+    PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
+  } while(0)
+
+/**
+  * @brief  gets counter of the tx buffer.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval Counter value
+  */
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
+
+/**
+  * @brief  Sets buffer 0/1 address in a double buffer endpoint.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wBuf0Addr buffer 0 address.
+  * @retval Counter value
+  */
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
+  do { \
+    PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
+  } while(0) /* PCD_SET_EP_DBUF0_ADDR */
+
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
+  do { \
+    PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
+  } while(0) /* PCD_SET_EP_DBUF1_ADDR */
+
+/**
+  * @brief  Sets addresses in a double buffer endpoint.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  wBuf0Addr: buffer 0 address.
+  * @param  wBuf1Addr = buffer 1 address.
+  * @retval None
+  */
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
+  do { \
+    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
+    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
+  } while(0) /* PCD_SET_EP_DBUF_ADDR */
+
+/**
+  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval None
+  */
+#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum)    (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum)    (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @param  bDir endpoint dir  EP_DBUF_OUT = OUT
+  *         EP_DBUF_IN  = IN
+  * @param  wCount: Counter value
+  * @retval None
+  */
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
+  do { \
+    if ((bDir) == 0U) \
+      /* OUT endpoint */ \
+    { \
+      PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
+    } \
+    else \
+    { \
+      if ((bDir) == 1U) \
+      { \
+        /* IN endpoint */ \
+        PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
+      } \
+    } \
+  } while(0) /* SetEPDblBuf0Count*/
+
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
+  do { \
+    uint32_t _wBase = (uint32_t)(USBx); \
+    __IO uint16_t *_wEPRegVal; \
+    \
+    if ((bDir) == 0U) \
+    { \
+      /* OUT endpoint */ \
+      PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
+    } \
+    else \
+    { \
+      if ((bDir) == 1U) \
+      { \
+        /* IN endpoint */ \
+        _wBase += (uint32_t)(USBx)->BTABLE; \
+        _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
+        *_wEPRegVal = (uint16_t)(wCount); \
+      } \
+    } \
+  } while(0) /* SetEPDblBuf1Count */
+
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
+  do { \
+    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+  } while(0) /* PCD_SET_EP_DBUF_CNT */
+
+/**
+  * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpNum Endpoint Number.
+  * @retval None
+  */
+#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum)     (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum)     (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_PCD_H */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h
new file mode 100644
index 0000000..300eab2
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h
@@ -0,0 +1,88 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_pcd_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PCD HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_PCD_EX_H
+#define STM32G4xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+#if defined (USB)
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCDEx
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @{
+  */
+
+
+
+HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
+                                       uint16_t ep_kind, uint32_t pmaadress);
+
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* STM32G4xx_HAL_PCD_EX_H */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h
new file mode 100644
index 0000000..fe23556
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h
@@ -0,0 +1,411 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_PWR_H
+#define STM32G4xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
+                            This parameter can be a value of @ref PWR_PVD_detection_level. */
+
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref PWR_PVD_Mode. */
+}PWR_PVDTypeDef;
+
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+
+/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
+  * @{
+  */
+#define PWR_PVDLEVEL_0                  PWR_CR2_PLS_LEV0  /*!< PVD threshold around 2.0 V */
+#define PWR_PVDLEVEL_1                  PWR_CR2_PLS_LEV1  /*!< PVD threshold around 2.2 V */
+#define PWR_PVDLEVEL_2                  PWR_CR2_PLS_LEV2  /*!< PVD threshold around 2.4 V */
+#define PWR_PVDLEVEL_3                  PWR_CR2_PLS_LEV3  /*!< PVD threshold around 2.5 V */
+#define PWR_PVDLEVEL_4                  PWR_CR2_PLS_LEV4  /*!< PVD threshold around 2.6 V */
+#define PWR_PVDLEVEL_5                  PWR_CR2_PLS_LEV5  /*!< PVD threshold around 2.8 V */
+#define PWR_PVDLEVEL_6                  PWR_CR2_PLS_LEV6  /*!< PVD threshold around 2.9 V */
+#define PWR_PVDLEVEL_7                  PWR_CR2_PLS_LEV7  /*!< External input analog voltage (compared internally to VREFINT) */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_Mode  PWR PVD interrupt and event mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< Basic mode is used */
+#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+  * @}
+  */
+
+
+
+
+/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON            ((uint32_t)0x00000000) /*!< Regulator in main mode      */
+#define PWR_LOWPOWERREGULATOR_ON        PWR_CR1_LPR            /*!< Regulator in low-power mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry  PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)        /*!< Wait For Interruption instruction to enter Sleep mode */
+#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)        /*!< Wait For Event instruction to enter Sleep mode        */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry  PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)       /*!< Wait For Interruption instruction to enter Stop mode */
+#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)       /*!< Wait For Event instruction to enter Stop mode        */
+/**
+  * @}
+  */
+
+
+/** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)   /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_EVENT_LINE  PWR PVD event line
+  * @{
+  */
+#define PWR_EVENT_LINE_PVD  ((uint32_t)0x00010000)  /*!< Event line 16 Connected to the PVD Event Line */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macros  PWR Exported Macros
+  * @{
+  */
+
+/** @brief  Check whether or not a specific PWR flag is set.
+  * @param  __FLAG__: specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
+  *                  was received from the WKUP pin 1.
+  *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
+  *                  was received from the WKUP pin 2.
+  *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
+  *                  was received from the WKUP pin 3.
+  *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
+  *                  was received from the WKUP pin 4.
+  *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
+  *                  was received from the WKUP pin 5.
+  *            @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
+  *                  entered StandBy mode.
+  *            @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
+  *                 the internal wakeup line.
+  *            @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
+  *                 low-power regulator is ready.
+  *            @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
+  *                 regulator is ready in main mode or is in low-power mode.
+  *            @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
+  *                 in the selected voltage range or is still changing to the required voltage level.
+  *            @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
+  *                  below or above the selected PVD threshold.
+@if PWR_CR2_PVME1
+  *            @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
+  *                  is below or above PVM1 threshold (applicable when USB feature is supported).
+@endif
+@if PWR_CR2_PVME2
+  *            @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
+  *                  is below or above PVM2 threshold (applicable when VDDIO2 is present on device).
+@endif
+  *            @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
+  *                  is below or above PVM3 threshold.
+  *            @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
+  *                  is below or above PVM4 threshold.
+  *
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_FLAG(__FLAG__)  ( ((((uint8_t)(__FLAG__)) >> 5U) == 1)  ?\
+                                      (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
+                                      (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
+
+/** @brief  Clear a specific PWR flag.
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
+  *                  was received from the WKUP pin 1.
+  *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
+  *                  was received from the WKUP pin 2.
+  *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
+  *                  was received from the WKUP pin 3.
+  *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
+  *                  was received from the WKUP pin 4.
+  *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
+  *                  was received from the WKUP pin 5.
+  *            @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
+  *            @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
+  *                  entered Standby mode.
+  * @retval None
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__)   ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
+                                         (PWR->SCR  = (__FLAG__)) :\
+                                         (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
+/**
+  * @brief Enable the PVD Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief Disable the PVD Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                   \
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Check whether or not the PVD EXTI interrupt flag is set.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR1 & PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Clear the PVD EXTI interrupt flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @}
+  */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  PWR_Private_Macros   PWR Private Macros
+  * @{
+  */
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+
+#define IS_PWR_PVD_MODE(MODE)  (((MODE) == PWR_PVD_MODE_NORMAL)              ||\
+                                ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\
+                                ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\
+                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   ||\
+                                ((MODE) == PWR_PVD_MODE_EVENT_RISING)        ||\
+                                ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       ||\
+                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
+
+#define IS_PWR_REGULATOR(REGULATOR)      (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+                                          ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
+
+/**
+  * @}
+  */
+
+/* Include PWR HAL Extended module */
+#include "stm32g4xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *******************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+
+/* WakeUp pins configuration functions ****************************************/
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+
+void HAL_PWR_PVDCallback(void);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32G4xx_HAL_PWR_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h
new file mode 100644
index 0000000..923f83c
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h
@@ -0,0 +1,817 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_PWR_EX_H
+#define STM32G4xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWREx
+  * @{
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
+  * @{
+  */
+
+
+/**
+  * @brief  PWR PVM configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold.
+                           This parameter can be a value of @ref PWREx_PVM_Type. */
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref PWREx_PVM_Mode. */
+}PWR_PVMTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
+  * @{
+  */
+#define PWR_WUP_POLARITY_SHIFT                  0x05U   /*!< Internal constant used to retrieve wakeup pin polariry */
+/**
+  * @}
+  */
+
+
+/** @defgroup PWREx_WakeUp_Pins  PWR wake-up pins
+  * @{
+  */
+#define PWR_WAKEUP_PIN1                 PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
+#define PWR_WAKEUP_PIN2                 PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
+#define PWR_WAKEUP_PIN3                 PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
+#define PWR_WAKEUP_PIN4                 PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
+#define PWR_WAKEUP_PIN5                 PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
+#define PWR_WAKEUP_PIN1_HIGH            PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
+#define PWR_WAKEUP_PIN2_HIGH            PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
+#define PWR_WAKEUP_PIN3_HIGH            PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
+#define PWR_WAKEUP_PIN4_HIGH            PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
+#define PWR_WAKEUP_PIN5_HIGH            PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
+#define PWR_WAKEUP_PIN1_LOW             (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
+#define PWR_WAKEUP_PIN2_LOW             (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
+#define PWR_WAKEUP_PIN3_LOW             (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
+#define PWR_WAKEUP_PIN4_LOW             (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
+#define PWR_WAKEUP_PIN5_LOW             (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
+  * @{
+  */
+#if defined(PWR_CR2_PVME1)
+#define PWR_PVM_1                  PWR_CR2_PVME1  /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+#define PWR_PVM_2                  PWR_CR2_PVME2  /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
+#endif /* PWR_CR2_PVME2 */
+#define PWR_PVM_3                  PWR_CR2_PVME3  /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
+#define PWR_PVM_4                  PWR_CR2_PVME4  /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V  */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode
+  * @{
+  */
+#define PWR_PVM_MODE_NORMAL                 0x00000000U   /*!< basic mode is used */
+#define PWR_PVM_MODE_IT_RISING              0x00010001U   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVM_MODE_IT_FALLING             0x00010002U   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVM_MODE_IT_RISING_FALLING      0x00010003U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVM_MODE_EVENT_RISING           0x00020001U   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVM_MODE_EVENT_FALLING          0x00020002U   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVM_MODE_EVENT_RISING_FALLING   0x00020003U   /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale
+  * @{
+  */
+#if defined(PWR_CR5_R1MODE)
+#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST  ((uint32_t)0x00000000)  /*!< Voltage scaling range 1 boost mode  */
+#endif /*PWR_CR5_R1MODE */
+#define PWR_REGULATOR_VOLTAGE_SCALE1        PWR_CR1_VOS_0           /*!< Voltage scaling range 1 normal mode */
+#define PWR_REGULATOR_VOLTAGE_SCALE2        PWR_CR1_VOS_1           /*!< Voltage scaling range 2             */
+/**
+  * @}
+  */
+
+
+/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
+  * @{
+  */
+#define PWR_BATTERY_CHARGING_RESISTOR_5           0x00000000U           /*!< VBAT charging through a 5 kOhms resistor   */
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5         PWR_CR4_VBRS          /*!< VBAT charging through a 1.5 kOhms resistor */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
+  * @{
+  */
+#define PWR_BATTERY_CHARGING_DISABLE        0x00000000U
+#define PWR_BATTERY_CHARGING_ENABLE         PWR_CR4_VBE
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
+  * @{
+  */
+#define PWR_GPIO_BIT_0   PWR_PUCRA_PA0    /*!< GPIO port I/O pin 0  */
+#define PWR_GPIO_BIT_1   PWR_PUCRA_PA1    /*!< GPIO port I/O pin 1  */
+#define PWR_GPIO_BIT_2   PWR_PUCRA_PA2    /*!< GPIO port I/O pin 2  */
+#define PWR_GPIO_BIT_3   PWR_PUCRA_PA3    /*!< GPIO port I/O pin 3  */
+#define PWR_GPIO_BIT_4   PWR_PUCRA_PA4    /*!< GPIO port I/O pin 4  */
+#define PWR_GPIO_BIT_5   PWR_PUCRA_PA5    /*!< GPIO port I/O pin 5  */
+#define PWR_GPIO_BIT_6   PWR_PUCRA_PA6    /*!< GPIO port I/O pin 6  */
+#define PWR_GPIO_BIT_7   PWR_PUCRA_PA7    /*!< GPIO port I/O pin 7  */
+#define PWR_GPIO_BIT_8   PWR_PUCRA_PA8    /*!< GPIO port I/O pin 8  */
+#define PWR_GPIO_BIT_9   PWR_PUCRA_PA9    /*!< GPIO port I/O pin 9  */
+#define PWR_GPIO_BIT_10  PWR_PUCRA_PA10   /*!< GPIO port I/O pin 10 */
+#define PWR_GPIO_BIT_11  PWR_PUCRA_PA11   /*!< GPIO port I/O pin 11 */
+#define PWR_GPIO_BIT_12  PWR_PUCRA_PA12   /*!< GPIO port I/O pin 12 */
+#define PWR_GPIO_BIT_13  PWR_PUCRA_PA13   /*!< GPIO port I/O pin 13 */
+#define PWR_GPIO_BIT_14  PWR_PDCRA_PA14   /*!< GPIO port I/O pin 14 */
+#define PWR_GPIO_BIT_15  PWR_PUCRA_PA15   /*!< GPIO port I/O pin 15 */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_GPIO GPIO port
+  * @{
+  */
+#define PWR_GPIO_A   0x00000000U      /*!< GPIO port A */
+#define PWR_GPIO_B   0x00000001U      /*!< GPIO port B */
+#define PWR_GPIO_C   0x00000002U      /*!< GPIO port C */
+#define PWR_GPIO_D   0x00000003U      /*!< GPIO port D */
+#define PWR_GPIO_E   0x00000004U      /*!< GPIO port E */
+#define PWR_GPIO_F   0x00000005U      /*!< GPIO port F */
+#define PWR_GPIO_G   0x00000006U      /*!< GPIO port G */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
+  * @{
+  */
+#if defined(PWR_CR2_PVME1)
+#define PWR_EXTI_LINE_PVM1  0x00000008U  /*!< External interrupt line 35 Connected to the PVM1 EXTI Line   */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+#define PWR_EXTI_LINE_PVM2  0x00000010U  /*!< External interrupt line 36 Connected to the PVM2 EXTI Line   */
+#endif /* PWR_CR2_PVME2 */
+#define PWR_EXTI_LINE_PVM3  0x00000020U  /*!< External interrupt line 37 Connected to the PVM3 EXTI Line   */
+#define PWR_EXTI_LINE_PVM4  0x00000040U  /*!< External interrupt line 38 Connected to the PVM4 EXTI Line   */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
+  * @{
+  */
+#if defined(PWR_CR2_PVME1)
+#define PWR_EVENT_LINE_PVM1     0x00000008U     /*!< Event line 35 Connected to the PVM1 EXTI Line */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+#define PWR_EVENT_LINE_PVM2     0x00000010U     /*!< Event line 36 Connected to the PVM2 EXTI Line */
+#endif /* PWR_CR2_PVME2 */
+#define PWR_EVENT_LINE_PVM3     0x00000020U     /*!< Event line 37 Connected to the PVM3 EXTI Line */
+#define PWR_EVENT_LINE_PVM4     0x00000040U     /*!< Event line 38 Connected to the PVM4 EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Flag  PWR Status Flags
+  *        Elements values convention: 0000 0000 0XXY YYYYb
+  *           - Y YYYY  : Flag position in the XX register (5 bits)
+  *           - XX  : Status register (2 bits)
+  *                 - 01: SR1 register
+  *                 - 10: SR2 register
+  *        The only exception is PWR_FLAG_WU, encompassing all
+  *        wake-up flags and set to PWR_SR1_WUF.
+  * @{
+  */
+#define PWR_FLAG_WUF1                       0x0020U              /*!< Wakeup event on wakeup pin 1 */
+#define PWR_FLAG_WUF2                       0x0021U              /*!< Wakeup event on wakeup pin 2 */
+#define PWR_FLAG_WUF3                       0x0022U              /*!< Wakeup event on wakeup pin 3 */
+#define PWR_FLAG_WUF4                       0x0023U              /*!< Wakeup event on wakeup pin 4 */
+#define PWR_FLAG_WUF5                       0x0024U              /*!< Wakeup event on wakeup pin 5 */
+#define PWR_FLAG_WU                         PWR_SR1_WUF          /*!< Encompass wakeup event on all wakeup pins */
+#define PWR_FLAG_SB                         0x0028U              /*!< Standby flag */
+#define PWR_FLAG_WUFI                       0x002FU              /*!< Wakeup on internal wakeup line */
+
+#define PWR_FLAG_REGLPS                     0x0048U              /*!< Low-power regulator start flag */
+#define PWR_FLAG_REGLPF                     0x0049U              /*!< Low-power regulator flag */
+#define PWR_FLAG_VOSF                       0x004AU              /*!< Voltage scaling flag */
+#define PWR_FLAG_PVDO                       0x004BU              /*!< Power Voltage Detector output flag */
+#if defined(PWR_CR2_PVME1)
+#define PWR_FLAG_PVMO1                      0x004CU              /*!< Power Voltage Monitoring 1 output flag */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+#define PWR_FLAG_PVMO2                      0x004DU              /*!< Power Voltage Monitoring 2 output flag */
+#endif /* PWR_CR2_PVME2 */
+#define PWR_FLAG_PVMO3                      0x004EU              /*!< Power Voltage Monitoring 3 output flag */
+#define PWR_FLAG_PVMO4                      0x004FU              /*!< Power Voltage Monitoring 4 output flag */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
+ * @{
+ */
+
+#if defined(PWR_CR2_PVME1)
+/**
+  * @brief Enable the PVM1 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Disable the PVM1 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Enable the PVM1 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
+
+/**
+  * @brief Disable the PVM1 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
+
+/**
+  * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
+
+
+/**
+  * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
+
+
+/**
+  * @brief  PVM1 EXTI line configuration: set rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                     \
+    __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
+  * @retval EXTI PVM1 Line Status.
+  */
+#define __HAL_PWR_PVM1_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Clear the PVM1 EXTI flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
+
+#endif /* PWR_CR2_PVME1 */
+
+
+#if defined(PWR_CR2_PVME2)
+/**
+  * @brief Enable the PVM2 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Disable the PVM2 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Enable the PVM2 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
+
+/**
+  * @brief Disable the PVM2 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
+
+/**
+  * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
+
+
+/**
+  * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
+
+
+/**
+  * @brief  PVM2 EXTI line configuration: set rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                     \
+    __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
+  * @retval EXTI PVM2 Line Status.
+  */
+#define __HAL_PWR_PVM2_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Clear the PVM2 EXTI flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
+
+#endif /* PWR_CR2_PVME2 */
+
+
+/**
+  * @brief Enable the PVM3 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Disable the PVM3 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Enable the PVM3 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
+
+/**
+  * @brief Disable the PVM3 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
+
+/**
+  * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
+
+
+/**
+  * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
+
+
+/**
+  * @brief  PVM3 EXTI line configuration: set rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                     \
+    __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
+  * @retval EXTI PVM3 Line Status.
+  */
+#define __HAL_PWR_PVM3_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Clear the PVM3 EXTI flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
+
+
+
+
+/**
+  * @brief Enable the PVM4 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Disable the PVM4 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Enable the PVM4 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
+
+/**
+  * @brief Disable the PVM4 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
+
+/**
+  * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
+
+
+/**
+  * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
+
+
+/**
+  * @brief  PVM4 EXTI line configuration: set rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                     \
+    __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
+  * @retval EXTI PVM4 Line Status.
+  */
+#define __HAL_PWR_PVM4_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Clear the PVM4 EXTI flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
+
+
+/**
+  * @brief Configure the main internal regulator output voltage.
+  * @param  __REGULATOR__: specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST  Regulator voltage output range 1 mode,
+  *                                                typical output voltage at 1.28 V,
+  *                                                system frequency up to 170 MHz.
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1  Regulator voltage output range 1 mode,
+  *                                                typical output voltage at 1.2 V,
+  *                                                system frequency up to 150 MHz.
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2  Regulator voltage output range 2 mode,
+  *                                                typical output voltage at 1.0 V,
+  *                                                system frequency up to 26 MHz.
+  * @note  This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
+  *        whether or not VOSF flag is cleared when moving from range 2 to range 1. User
+  *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
+  * @retval None
+  */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
+                                                            __IO uint32_t tmpreg;                               \
+                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
+                                                            /* Delay after an RCC peripheral clock enabling */  \
+                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
+                                                            UNUSED(tmpreg);                                     \
+                                                          } while(0)
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
+  * @{
+  */
+
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
+                                ((PIN) == PWR_WAKEUP_PIN2) || \
+                                ((PIN) == PWR_WAKEUP_PIN3) || \
+                                ((PIN) == PWR_WAKEUP_PIN4) || \
+                                ((PIN) == PWR_WAKEUP_PIN5) || \
+                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
+                                ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
+                                ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
+                                ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
+                                ((PIN) == PWR_WAKEUP_PIN5_LOW))
+
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
+                               ((TYPE) == PWR_PVM_2) ||\
+                               ((TYPE) == PWR_PVM_3) ||\
+                               ((TYPE) == PWR_PVM_4))
+
+#define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\
+                                ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
+                                ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
+                                ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
+                                ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
+                                ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
+                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
+
+#if defined(PWR_CR5_R1MODE)
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \
+                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1)       || \
+                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
+#else
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
+#endif
+
+
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
+                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
+
+#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
+                                           ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
+
+#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U)
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
+                           ((GPIO) == PWR_GPIO_B) ||\
+                           ((GPIO) == PWR_GPIO_C) ||\
+                           ((GPIO) == PWR_GPIO_D) ||\
+                           ((GPIO) == PWR_GPIO_E) ||\
+                           ((GPIO) == PWR_GPIO_F) ||\
+                           ((GPIO) == PWR_GPIO_G))
+
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
+  * @{
+  */
+
+
+/* Peripheral Control functions  **********************************************/
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
+void HAL_PWREx_DisableBatteryCharging(void);
+void HAL_PWREx_EnableInternalWakeUpLine(void);
+void HAL_PWREx_DisableInternalWakeUpLine(void);
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
+void HAL_PWREx_EnablePullUpPullDownConfig(void);
+void HAL_PWREx_DisablePullUpPullDownConfig(void);
+void HAL_PWREx_EnableSRAM2ContentRetention(void);
+void HAL_PWREx_DisableSRAM2ContentRetention(void);
+#if defined(PWR_CR2_PVME1)
+void HAL_PWREx_EnablePVM1(void);
+void HAL_PWREx_DisablePVM1(void);
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+void HAL_PWREx_EnablePVM2(void);
+void HAL_PWREx_DisablePVM2(void);
+#endif /* PWR_CR2_PVME2 */
+void HAL_PWREx_EnablePVM3(void);
+void HAL_PWREx_DisablePVM3(void);
+void HAL_PWREx_EnablePVM4(void);
+void HAL_PWREx_DisablePVM4(void);
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWREx_EnableLowPowerRunMode(void);
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
+void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSHUTDOWNMode(void);
+
+void HAL_PWREx_PVD_PVM_IRQHandler(void);
+#if defined(PWR_CR2_PVME1)
+void HAL_PWREx_PVM1Callback(void);
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+void HAL_PWREx_PVM2Callback(void);
+#endif /* PWR_CR2_PVME2 */
+void HAL_PWREx_PVM3Callback(void);
+void HAL_PWREx_PVM4Callback(void);
+
+#if defined(PWR_CR3_UCPD_STDBY)
+void HAL_PWREx_EnableUCPDStandbyMode(void);
+void HAL_PWREx_DisableUCPDStandbyMode(void);
+#endif /* PWR_CR3_UCPD_STDBY */
+#if defined(PWR_CR3_UCPD_DBDIS)
+void HAL_PWREx_EnableUCPDDeadBattery(void);
+void HAL_PWREx_DisableUCPDDeadBattery(void);
+#endif /* PWR_CR3_UCPD_DBDIS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32G4xx_HAL_PWR_EX_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h
new file mode 100644
index 0000000..c0969dc
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h
@@ -0,0 +1,3406 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_RCC_H
+#define STM32G4xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC PLL configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PLLState;   /*!< The new state of the PLL.
+                            This parameter can be a value of @ref RCC_PLL_Config                      */
+
+  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
+                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
+
+  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
+                            This parameter must be a value of @ref RCC_PLLM_Clock_Divider             */
+
+  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
+                            This parameter must be a number between Min_Data = 8 and Max_Data = 127    */
+
+  uint32_t PLLP;       /*!< PLLP: Division factor for ADC clock.
+                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
+
+  uint32_t PLLQ;       /*!< PLLQ: Division factor for SAI, I2S, USB, FDCAN and QUADSPI clocks.
+                            This parameter must be a value of @ref RCC_PLLQ_Clock_Divider             */
+
+  uint32_t PLLR;       /*!< PLLR: Division for the main system clock.
+                            User have to set the PLLR parameter correctly to not exceed max frequency 170MHZ.
+                            This parameter must be a value of @ref RCC_PLLR_Clock_Divider             */
+
+}RCC_PLLInitTypeDef;
+
+/**
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+  */
+typedef struct
+{
+  uint32_t OscillatorType;       /*!< The oscillators to be configured.
+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
+
+  uint32_t HSEState;             /*!< The new state of the HSE.
+                                      This parameter can be a value of @ref RCC_HSE_Config                        */
+
+  uint32_t LSEState;             /*!< The new state of the LSE.
+                                      This parameter can be a value of @ref RCC_LSE_Config                        */
+
+  uint32_t HSIState;             /*!< The new state of the HSI.
+                                      This parameter can be a value of @ref RCC_HSI_Config                        */
+
+  uint32_t HSICalibrationValue;  /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+  uint32_t LSIState;             /*!< The new state of the LSI.
+                                      This parameter can be a value of @ref RCC_LSI_Config                        */
+
+  uint32_t HSI48State;             /*!< The new state of the HSI48.
+                                        This parameter can be a value of @ref RCC_HSI48_Config */
+
+  RCC_PLLInitTypeDef PLL;        /*!< Main PLL structure parameters                                               */
+
+}RCC_OscInitTypeDef;
+
+/**
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t ClockType;             /*!< The clock to be configured.
+                                       This parameter can be a value of @ref RCC_System_Clock_Type      */
+
+  uint32_t SYSCLKSource;          /*!< The clock source used as system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_System_Clock_Source    */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+}RCC_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_Timeout_Value Timeout Values
+  * @{
+  */
+#define RCC_DBP_TIMEOUT_VALUE          2U                        /* 2 ms (minimum Tick + 1) */
+#define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+  * @{
+  */
+#define RCC_OSCILLATORTYPE_NONE        0x00000000U               /*!< Oscillator configuration unchanged */
+#define RCC_OSCILLATORTYPE_HSE         0x00000001U               /*!< HSE to configure */
+#define RCC_OSCILLATORTYPE_HSI         0x00000002U               /*!< HSI to configure */
+#define RCC_OSCILLATORTYPE_LSE         0x00000004U               /*!< LSE to configure */
+#define RCC_OSCILLATORTYPE_LSI         0x00000008U               /*!< LSI to configure */
+#define RCC_OSCILLATORTYPE_HSI48       0x00000020U               /*!< HSI48 to configure */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Config HSE Config
+  * @{
+  */
+#define RCC_HSE_OFF                    0x00000000U                                /*!< HSE clock deactivation */
+#define RCC_HSE_ON                     RCC_CR_HSEON                               /*!< HSE clock activation */
+#define RCC_HSE_BYPASS                 (RCC_CR_HSEBYP | RCC_CR_HSEON)             /*!< External clock source for HSE clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Config LSE Config
+  * @{
+  */
+#define RCC_LSE_OFF                    0x00000000U                                    /*!< LSE clock deactivation */
+#define RCC_LSE_ON                     RCC_BDCR_LSEON                                 /*!< LSE clock activation */
+#define RCC_LSE_BYPASS                 (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)             /*!< External clock source for LSE clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Config HSI Config
+  * @{
+  */
+#define RCC_HSI_OFF                    0x00000000U            /*!< HSI clock deactivation */
+#define RCC_HSI_ON                     RCC_CR_HSION           /*!< HSI clock activation */
+#define RCC_HSICALIBRATION_DEFAULT     0x40U                  /* Default HSI calibration trimming value */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Config LSI Config
+  * @{
+  */
+#define RCC_LSI_OFF                    0x00000000U            /*!< LSI clock deactivation */
+#define RCC_LSI_ON                     RCC_CSR_LSION          /*!< LSI clock activation */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI48_Config HSI48 Config
+  * @{
+  */
+#define RCC_HSI48_OFF                  0x00000000U            /*!< HSI48 clock deactivation */
+#define RCC_HSI48_ON                   RCC_CRRCR_HSI48ON      /*!< HSI48 clock activation */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Config PLL Config
+  * @{
+  */
+#define RCC_PLL_NONE                   0x00000000U            /*!< PLL configuration unchanged */
+#define RCC_PLL_OFF                    0x00000001U            /*!< PLL deactivation */
+#define RCC_PLL_ON                     0x00000002U            /*!< PLL activation */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider
+  * @{
+  */
+#define RCC_PLLM_DIV1                  0x00000001U             /*!< PLLM division factor = 1  */
+#define RCC_PLLM_DIV2                  0x00000002U             /*!< PLLM division factor = 2  */
+#define RCC_PLLM_DIV3                  0x00000003U             /*!< PLLM division factor = 3  */
+#define RCC_PLLM_DIV4                  0x00000004U             /*!< PLLM division factor = 4  */
+#define RCC_PLLM_DIV5                  0x00000005U             /*!< PLLM division factor = 5  */
+#define RCC_PLLM_DIV6                  0x00000006U             /*!< PLLM division factor = 6  */
+#define RCC_PLLM_DIV7                  0x00000007U             /*!< PLLM division factor = 7  */
+#define RCC_PLLM_DIV8                  0x00000008U             /*!< PLLM division factor = 8  */
+#define RCC_PLLM_DIV9                  0x00000009U             /*!< PLLM division factor = 9  */
+#define RCC_PLLM_DIV10                 0x0000000AU             /*!< PLLM division factor = 10 */
+#define RCC_PLLM_DIV11                 0x0000000BU             /*!< PLLM division factor = 11 */
+#define RCC_PLLM_DIV12                 0x0000000CU             /*!< PLLM division factor = 12 */
+#define RCC_PLLM_DIV13                 0x0000000DU             /*!< PLLM division factor = 13 */
+#define RCC_PLLM_DIV14                 0x0000000EU             /*!< PLLM division factor = 14 */
+#define RCC_PLLM_DIV15                 0x0000000FU             /*!< PLLM division factor = 15 */
+#define RCC_PLLM_DIV16                 0x00000010U             /*!< PLLM division factor = 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
+  * @{
+  */
+#define RCC_PLLP_DIV2                  0x00000002U             /*!< PLLP division factor = 2  */
+#define RCC_PLLP_DIV3                  0x00000003U             /*!< PLLP division factor = 3  */
+#define RCC_PLLP_DIV4                  0x00000004U             /*!< PLLP division factor = 4  */
+#define RCC_PLLP_DIV5                  0x00000005U             /*!< PLLP division factor = 5  */
+#define RCC_PLLP_DIV6                  0x00000006U             /*!< PLLP division factor = 6  */
+#define RCC_PLLP_DIV7                  0x00000007U             /*!< PLLP division factor = 7  */
+#define RCC_PLLP_DIV8                  0x00000008U             /*!< PLLP division factor = 8  */
+#define RCC_PLLP_DIV9                  0x00000009U             /*!< PLLP division factor = 9  */
+#define RCC_PLLP_DIV10                 0x0000000AU             /*!< PLLP division factor = 10 */
+#define RCC_PLLP_DIV11                 0x0000000BU             /*!< PLLP division factor = 11 */
+#define RCC_PLLP_DIV12                 0x0000000CU             /*!< PLLP division factor = 12 */
+#define RCC_PLLP_DIV13                 0x0000000DU             /*!< PLLP division factor = 13 */
+#define RCC_PLLP_DIV14                 0x0000000EU             /*!< PLLP division factor = 14 */
+#define RCC_PLLP_DIV15                 0x0000000FU             /*!< PLLP division factor = 15 */
+#define RCC_PLLP_DIV16                 0x00000010U             /*!< PLLP division factor = 16 */
+#define RCC_PLLP_DIV17                 0x00000011U             /*!< PLLP division factor = 17 */
+#define RCC_PLLP_DIV18                 0x00000012U             /*!< PLLP division factor = 18 */
+#define RCC_PLLP_DIV19                 0x00000013U             /*!< PLLP division factor = 19 */
+#define RCC_PLLP_DIV20                 0x00000014U             /*!< PLLP division factor = 20 */
+#define RCC_PLLP_DIV21                 0x00000015U             /*!< PLLP division factor = 21 */
+#define RCC_PLLP_DIV22                 0x00000016U             /*!< PLLP division factor = 22 */
+#define RCC_PLLP_DIV23                 0x00000017U             /*!< PLLP division factor = 23 */
+#define RCC_PLLP_DIV24                 0x00000018U             /*!< PLLP division factor = 24 */
+#define RCC_PLLP_DIV25                 0x00000019U             /*!< PLLP division factor = 25 */
+#define RCC_PLLP_DIV26                 0x0000001AU             /*!< PLLP division factor = 26 */
+#define RCC_PLLP_DIV27                 0x0000001BU             /*!< PLLP division factor = 27 */
+#define RCC_PLLP_DIV28                 0x0000001CU             /*!< PLLP division factor = 28 */
+#define RCC_PLLP_DIV29                 0x0000001DU             /*!< PLLP division factor = 29 */
+#define RCC_PLLP_DIV30                 0x0000001EU             /*!< PLLP division factor = 30 */
+#define RCC_PLLP_DIV31                 0x0000001FU             /*!< PLLP division factor = 31 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
+  * @{
+  */
+#define RCC_PLLQ_DIV2                  0x00000002U             /*!< PLLQ division factor = 2 */
+#define RCC_PLLQ_DIV4                  0x00000004U             /*!< PLLQ division factor = 4 */
+#define RCC_PLLQ_DIV6                  0x00000006U             /*!< PLLQ division factor = 6 */
+#define RCC_PLLQ_DIV8                  0x00000008U             /*!< PLLQ division factor = 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
+  * @{
+  */
+#define RCC_PLLR_DIV2                  0x00000002U             /*!< PLLR division factor = 2 */
+#define RCC_PLLR_DIV4                  0x00000004U             /*!< PLLR division factor = 4 */
+#define RCC_PLLR_DIV6                  0x00000006U             /*!< PLLR division factor = 6 */
+#define RCC_PLLR_DIV8                  0x00000008U             /*!< PLLR division factor = 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
+  * @{
+  */
+#define RCC_PLLSOURCE_NONE             0x00000000U              /*!< No clock selected as PLL entry clock source  */
+#define RCC_PLLSOURCE_HSI              RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI clock selected as PLL entry clock source */
+#define RCC_PLLSOURCE_HSE              RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
+  * @{
+  */
+#define RCC_PLL_ADCCLK                 RCC_PLLCFGR_PLLPEN      /*!< PLLADCCLK selection from main PLL */
+#define RCC_PLL_48M1CLK                RCC_PLLCFGR_PLLQEN      /*!< PLL48M1CLK selection from main PLL */
+#define RCC_PLL_SYSCLK                 RCC_PLLCFGR_PLLREN      /*!< PLLCLK selection from main PLL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+  * @{
+  */
+#define RCC_CLOCKTYPE_SYSCLK           0x00000001U              /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK             0x00000002U              /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1            0x00000004U              /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2            0x00000008U              /*!< PCLK2 to configure */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
+#define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
+#define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+  * @{
+  */
+#define RCC_SYSCLK_DIV1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
+#define RCC_SYSCLK_DIV2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
+#define RCC_SYSCLK_DIV4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
+#define RCC_SYSCLK_DIV8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
+#define RCC_SYSCLK_DIV16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
+#define RCC_SYSCLK_DIV64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
+#define RCC_SYSCLK_DIV128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define RCC_SYSCLK_DIV256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define RCC_SYSCLK_DIV512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
+  * @{
+  */
+#define RCC_HCLK_DIV1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
+#define RCC_HCLK_DIV2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
+#define RCC_HCLK_DIV4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
+#define RCC_HCLK_DIV8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
+#define RCC_HCLK_DIV16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+  * @{
+  */
+#define RCC_RTCCLKSOURCE_NONE          0x00000000U             /*!< No clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO_Index MCO Index
+  * @{
+  */
+/* 32     28      20       16      0
+   --------------------------------
+   | MCO   | GPIO  | GPIO  | GPIO  |
+   | Index |  AF   | Port  |  Pin  |
+   -------------------------------*/
+
+#define RCC_MCO_GPIOPORT_POS           16U
+#define RCC_MCO_GPIOPORT_MASK          (0xFUL << RCC_MCO_GPIOPORT_POS)
+#define RCC_MCO_GPIOAF_POS             20U
+#define RCC_MCO_GPIOAF_MASK            (0xFFUL << RCC_MCO_GPIOAF_POS)
+#define RCC_MCO_INDEX_POS              28U
+#define RCC_MCO_INDEX_MASK             (0x1UL << RCC_MCO_INDEX_POS)
+#define RCC_MCO1_INDEX                 (0x0UL << RCC_MCO_INDEX_POS)             /*!< MCO1 index */
+#define RCC_MCO_PA8                    (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8)
+#define RCC_MCO_PG10                   (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10)
+
+/* Legacy Defines*/
+#define RCC_MCO1                       RCC_MCO_PA8
+#define RCC_MCO                        RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
+  * @{
+  */
+#define RCC_MCO1SOURCE_NOCLOCK         0x00000000U                            /*!< MCO1 output disabled, no clock on MCO1 */
+#define RCC_MCO1SOURCE_SYSCLK          RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
+#define RCC_MCO1SOURCE_HSI             (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
+#define RCC_MCO1SOURCE_HSE             RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
+#define RCC_MCO1SOURCE_PLLCLK          (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< PLLCLK selection as MCO1 source */
+#define RCC_MCO1SOURCE_LSI             (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
+#define RCC_MCO1SOURCE_LSE             (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
+#define RCC_MCO1SOURCE_HSI48           RCC_CFGR_MCOSEL_3                      /*!< HSI48 selection as MCO1 source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
+  * @{
+  */
+#define RCC_MCODIV_1                   RCC_CFGR_MCOPRE_DIV1     /*!< MCO not divided  */
+#define RCC_MCODIV_2                   RCC_CFGR_MCOPRE_DIV2     /*!< MCO divided by 2 */
+#define RCC_MCODIV_4                   RCC_CFGR_MCOPRE_DIV4     /*!< MCO divided by 4 */
+#define RCC_MCODIV_8                   RCC_CFGR_MCOPRE_DIV8     /*!< MCO divided by 8 */
+#define RCC_MCODIV_16                  RCC_CFGR_MCOPRE_DIV16    /*!< MCO divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt Interrupts
+  * @{
+  */
+#define RCC_IT_LSIRDY                  RCC_CIFR_LSIRDYF      /*!< LSI Ready Interrupt flag */
+#define RCC_IT_LSERDY                  RCC_CIFR_LSERDYF      /*!< LSE Ready Interrupt flag */
+#define RCC_IT_HSIRDY                  RCC_CIFR_HSIRDYF      /*!< HSI16 Ready Interrupt flag */
+#define RCC_IT_HSERDY                  RCC_CIFR_HSERDYF      /*!< HSE Ready Interrupt flag */
+#define RCC_IT_PLLRDY                  RCC_CIFR_PLLRDYF      /*!< PLL Ready Interrupt flag */
+#define RCC_IT_CSS                     RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */
+#define RCC_IT_LSECSS                  RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */
+#define RCC_IT_HSI48RDY                RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag Flags
+  *        Elements values convention: XXXYYYYYb
+  *           - YYYYY  : Flag position in the register
+  *           - XXX  : Register index
+  *                 - 001: CR register
+  *                 - 010: BDCR register
+  *                 - 011: CSR register
+  *                 - 100: CRRCR register
+  * @{
+  */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY                ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
+#define RCC_FLAG_HSERDY                ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
+#define RCC_FLAG_PLLRDY                ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY                ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)  /*!< LSE Ready flag */
+#define RCC_FLAG_LSECSSD               ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY                ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)    /*!< LSI Ready flag */
+#define RCC_FLAG_OBLRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)   /*!< Option Byte Loader reset flag */
+#define RCC_FLAG_PINRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)   /*!< PIN reset flag */
+#define RCC_FLAG_BORRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)   /*!< BOR reset flag */
+#define RCC_FLAG_SFTRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)   /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)  /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)  /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)  /*!< Low-Power reset flag */
+
+/* Flags in the CRRCR register */
+#define RCC_FLAG_HSI48RDY              ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSEDrive_Config LSE Drive Config
+  * @{
+  */
+#define RCC_LSEDRIVE_LOW                 0x00000000U            /*!< LSE low drive capability */
+#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */
+#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_DMA1_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_DMA2_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_DMAMUX1_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_CORDIC_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_FMAC_CLK_ENABLE()              do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_FLASH_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_CRC_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_DMA1_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
+
+#define __HAL_RCC_DMA2_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
+
+#define __HAL_RCC_DMAMUX1_CLK_DISABLE()        CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
+
+#define __HAL_RCC_CORDIC_CLK_DISABLE()         CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)
+
+#define __HAL_RCC_FMAC_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN)
+
+#define __HAL_RCC_FLASH_CLK_DISABLE()          CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
+
+#define __HAL_RCC_CRC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_GPIOA_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_GPIOB_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_GPIOC_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_GPIOD_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_GPIOE_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_GPIOF_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_ADC12_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
+
+#define __HAL_RCC_GPIOB_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
+
+#define __HAL_RCC_GPIOC_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
+
+#define __HAL_RCC_GPIOD_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
+
+#define __HAL_RCC_GPIOE_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
+
+#define __HAL_RCC_GPIOF_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
+
+#define __HAL_RCC_GPIOG_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
+
+#define __HAL_RCC_ADC12_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_CLK_DISABLE()         CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
+#endif /* AES */
+
+#define __HAL_RCC_RNG_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_DISABLE()           CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
+#endif /* QUADSPI */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_TIM2_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_TIM3_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_TIM4_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_CRS_CLK_ENABLE()             do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_RTCAPB_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_WWDG_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_SPI2_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_USART2_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_USART3_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_I2C2_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_USB_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_I2C3_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_LPUART1_CLK_ENABLE()         do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_TIM2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
+
+#define __HAL_RCC_TIM3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
+
+#define __HAL_RCC_TIM4_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
+
+#define __HAL_RCC_TIM7_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
+
+#define __HAL_RCC_CRS_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
+
+#define __HAL_RCC_RTCAPB_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
+
+#define __HAL_RCC_WWDG_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDG2EN)
+
+#define __HAL_RCC_SPI2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
+
+#define __HAL_RCC_SPI3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
+
+#define __HAL_RCC_USART2_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
+
+#define __HAL_RCC_USART3_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
+
+#define __HAL_RCC_I2C2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
+
+#define __HAL_RCC_USB_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
+
+#define __HAL_RCC_I2C3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
+
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
+
+#define __HAL_RCC_LPUART1_CLK_DISABLE()        CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_SYSCFG_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_TIM1_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_SPI1_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_TIM8_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_USART1_CLK_ENABLE()          do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_TIM16_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#define __HAL_RCC_TIM17_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_CLK_ENABLE()            do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_ENABLE()           do { \
+                                                 __IO uint32_t tmpreg; \
+                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
+                                                 /* Delay after an RCC peripheral clock enabling */ \
+                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
+                                                 UNUSED(tmpreg); \
+                                               } while(0)
+#endif /* HRTIM1 */
+
+#define __HAL_RCC_SYSCFG_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
+
+#define __HAL_RCC_TIM1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
+
+#define __HAL_RCC_SPI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
+
+#define __HAL_RCC_TIM8_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
+
+#define __HAL_RCC_USART1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
+
+#define __HAL_RCC_TIM16_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
+
+#define __HAL_RCC_TIM17_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN)
+#endif /* HRTIM1 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
+  * @brief  Check whether the AHB1 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)
+
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
+
+#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED()     (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)
+
+#define __HAL_RCC_CORDIC_IS_CLK_ENABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U)
+
+#define __HAL_RCC_FMAC_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U)
+
+#define __HAL_RCC_FLASH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
+
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
+
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)
+
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
+
+#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED()    (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)
+
+#define __HAL_RCC_CORDIC_IS_CLK_DISABLED()     (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)
+
+#define __HAL_RCC_FMAC_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U)
+
+#define __HAL_RCC_FLASH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
+
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
+  * @brief  Check whether the AHB2 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
+
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
+
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
+
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
+
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
+
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
+
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
+
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_IS_CLK_ENABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) != 0U)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) != 0U)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) != 0U)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
+
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
+
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
+
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
+
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
+
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
+
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
+
+#define __HAL_RCC_ADC12_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_IS_CLK_DISABLED()     (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) == 0U)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) == 0U)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) == 0U)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
+  * @brief  Check whether the AHB3 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
+#endif /* QUADSPI */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
+  * @brief  Check whether the APB1 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
+
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
+
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
+
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
+
+#define __HAL_RCC_CRS_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
+
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
+
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
+
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
+
+#define __HAL_RCC_USART2_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
+
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
+
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
+
+#define __HAL_RCC_USB_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)
+
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
+
+#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
+
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
+
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
+
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
+
+#define __HAL_RCC_CRS_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
+
+#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)
+
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)
+
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
+
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)
+
+#define __HAL_RCC_USART2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
+
+#define __HAL_RCC_USART3_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
+
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
+
+#if defined(USB)
+#define __HAL_RCC_USB_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U)
+#endif /* USB */
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)
+
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)
+
+#define __HAL_RCC_LPUART1_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
+  * @brief  Check whether the APB2 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
+
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
+
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
+
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
+
+#define __HAL_RCC_USART1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
+
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
+
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) != 0U)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) != 0U)
+#endif /* HRTIM1 */
+
+
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
+
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
+
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
+
+#define __HAL_RCC_USART1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
+
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
+
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) == 0U)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) == 0U)
+#endif /* HRTIM1 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB1_FORCE_RESET()           WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
+
+#define __HAL_RCC_DMA1_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
+
+#define __HAL_RCC_DMA2_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
+
+#define __HAL_RCC_DMAMUX1_FORCE_RESET()        SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
+
+#define __HAL_RCC_CORDIC_FORCE_RESET()         SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
+
+#define __HAL_RCC_FMAC_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
+
+#define __HAL_RCC_FLASH_FORCE_RESET()          SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
+
+#define __HAL_RCC_CRC_FORCE_RESET()            SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
+
+
+#define __HAL_RCC_AHB1_RELEASE_RESET()         WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
+
+#define __HAL_RCC_DMA1_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
+
+#define __HAL_RCC_DMA2_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
+
+#define __HAL_RCC_DMAMUX1_RELEASE_RESET()      CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
+
+#define __HAL_RCC_CORDIC_RELEASE_RESET()       CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
+
+#define __HAL_RCC_FMAC_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
+
+#define __HAL_RCC_FLASH_RELEASE_RESET()        CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
+
+#define __HAL_RCC_CRC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()           WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
+
+#define __HAL_RCC_GPIOA_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
+
+#define __HAL_RCC_GPIOB_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
+
+#define __HAL_RCC_GPIOC_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
+
+#define __HAL_RCC_GPIOD_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
+
+#define __HAL_RCC_GPIOE_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
+
+#define __HAL_RCC_GPIOF_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
+
+#define __HAL_RCC_GPIOG_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
+
+#define __HAL_RCC_ADC12_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_FORCE_RESET()         SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
+
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()         WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
+
+#define __HAL_RCC_GPIOA_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
+
+#define __HAL_RCC_GPIOB_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
+
+#define __HAL_RCC_GPIOC_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
+
+#define __HAL_RCC_GPIOE_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
+
+#define __HAL_RCC_GPIOF_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
+
+#define __HAL_RCC_GPIOG_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
+
+#define __HAL_RCC_ADC12_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_RELEASE_RESET()       CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB3_FORCE_RESET()           WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_FORCE_RESET()            SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_FORCE_RESET()           SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
+#endif /* QUADSPI */
+
+#define __HAL_RCC_AHB3_RELEASE_RESET()         WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_RELEASE_RESET()         CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
+#endif /* QUADSPI */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB1_FORCE_RESET()           WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
+
+#define __HAL_RCC_TIM2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
+
+#define __HAL_RCC_TIM3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
+
+#define __HAL_RCC_TIM4_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
+
+#define __HAL_RCC_TIM7_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
+
+#define __HAL_RCC_CRS_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
+
+#define __HAL_RCC_SPI2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
+
+#define __HAL_RCC_SPI3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
+
+#define __HAL_RCC_USART2_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
+
+#define __HAL_RCC_USART3_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
+
+#define __HAL_RCC_I2C2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
+
+#define __HAL_RCC_USB_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
+
+#define __HAL_RCC_I2C3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
+
+#define __HAL_RCC_LPTIM1_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
+
+#define __HAL_RCC_LPUART1_FORCE_RESET()        SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_FORCE_RESET()           SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_FORCE_RESET()          SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
+
+#define __HAL_RCC_APB1_RELEASE_RESET()         WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
+
+#define __HAL_RCC_TIM2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
+
+#define __HAL_RCC_TIM3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
+
+#define __HAL_RCC_TIM4_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
+
+#define __HAL_RCC_TIM7_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
+
+#define __HAL_RCC_CRS_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
+
+#define __HAL_RCC_SPI2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
+
+#define __HAL_RCC_SPI3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
+
+#define __HAL_RCC_USART2_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
+
+#define __HAL_RCC_USART3_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
+
+#define __HAL_RCC_I2C2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
+
+#define __HAL_RCC_USB_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
+
+#define __HAL_RCC_I2C3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
+
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
+
+#define __HAL_RCC_LPUART1_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB2_FORCE_RESET()           WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
+
+#define __HAL_RCC_SYSCFG_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
+
+#define __HAL_RCC_TIM1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
+
+#define __HAL_RCC_SPI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
+
+#define __HAL_RCC_TIM8_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
+
+#define __HAL_RCC_USART1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
+
+#define __HAL_RCC_TIM16_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
+
+#define __HAL_RCC_TIM17_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
+#endif /* HRTIM1 */
+
+
+#define __HAL_RCC_APB2_RELEASE_RESET()         WRITE_REG(RCC->APB2RSTR, 0x00000000U)
+
+#define __HAL_RCC_SYSCFG_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
+
+#define __HAL_RCC_TIM1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
+
+#define __HAL_RCC_SPI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
+
+#define __HAL_RCC_TIM8_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
+
+#define __HAL_RCC_USART1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
+
+#define __HAL_RCC_TIM16_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
+
+#define __HAL_RCC_TIM17_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
+#endif /* HRTIM1 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
+
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
+
+#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
+
+#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
+
+#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
+
+#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
+
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
+
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
+
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
+
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
+
+#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
+
+#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
+
+#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
+
+#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
+
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
+
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
+
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
+
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
+
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
+
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
+
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
+
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
+
+#define __HAL_RCC_CCM_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
+
+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
+
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
+
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
+
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
+
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
+
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
+
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
+
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
+
+#define __HAL_RCC_CCM_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
+
+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
+#endif /* QUADSPI */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
+
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
+
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
+
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
+
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
+
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
+
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
+
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
+
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
+
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
+
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
+
+#if defined(USB)
+#define __HAL_RCC_USB_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
+#endif /* USB */
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
+
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
+
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
+
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
+
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
+
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
+
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
+
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
+
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
+
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
+
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
+
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
+
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
+
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
+
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
+
+#if defined(USB)
+#define __HAL_RCC_USB_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
+#endif /* USB */
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
+
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
+
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
+
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
+
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
+
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
+
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
+
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
+
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
+#endif /* HRTIM1 */
+
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
+
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
+
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
+
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
+
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
+
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
+#endif /* HRTIM1 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
+  * @brief  Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)
+
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)
+
+#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)
+
+#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U)
+
+#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U)
+
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)
+
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)
+
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)
+
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)
+
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)
+
+#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)
+
+#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U)
+
+#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U)
+
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)
+
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)
+
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
+  * @brief  Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)
+
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)
+
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)
+
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)
+
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)
+
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)
+
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)
+
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)
+
+#define __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U)
+
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) != 0U)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) != 0U)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) != 0U)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)
+
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)
+
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)
+
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)
+
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)
+
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)
+
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)
+
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)
+
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)
+
+#define __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U)
+
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U)
+
+#if defined(ADC345_COMMON)
+#define __HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) == 0U)
+#endif /* ADC345_COMMON */
+
+#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U)
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) == 0U)
+#endif /* DAC2 */
+
+#define __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U)
+
+#if defined(DAC4)
+#define __HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) == 0U)
+#endif /* DAC4 */
+
+#if defined(AES)
+#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)
+#endif /* AES */
+
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
+  * @brief  Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)
+#endif /* QUADSPI */
+
+#if defined(FMC_BANK1)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)
+#endif /* FMC_BANK1 */
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)
+#endif /* QUADSPI */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
+  * @brief  Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)
+
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)
+
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)
+
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)
+
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
+
+#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)
+
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)
+
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)
+
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)
+
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)
+
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)
+
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)
+
+#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)
+
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)
+
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U)
+
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)
+
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)
+
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
+
+#if defined(TIM5)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)
+#endif /* TIM5 */
+
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)
+
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)
+
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
+
+#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)
+
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)
+
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)
+
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)
+
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)
+
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)
+
+#if defined(UART4)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)
+#endif /* UART4 */
+
+#if defined(UART5)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)
+#endif /* UART5 */
+
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)
+
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)
+
+#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U)
+
+#if defined(FDCAN1)
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U)
+#endif /* FDCAN1 */
+
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)
+
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)
+
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)
+
+#if defined(I2C4)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)
+#endif /* I2C4 */
+
+#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
+  * @brief  Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)
+
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
+
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)
+
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) != 0U)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)
+
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)
+
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) != 0U)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) != 0U)
+#endif /* HRTIM1 */
+
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)
+
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)
+
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)
+
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)
+
+#if defined(SPI4)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) == 0U)
+#endif /* SPI4 */
+
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)
+
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)
+
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)
+
+#if defined(TIM20)
+#define __HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) == 0U)
+#endif /* TIM20 */
+
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) == 0U)
+#endif /* HRTIM1 */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
+  * @{
+  */
+
+/** @brief  Macros to force or release the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_CSR register.
+  * @note   The BKPSRAM is not affected by this reset.
+  * @retval None
+  */
+#define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
+  * @{
+  */
+
+/** @brief  Macros to enable or disable the RTC clock.
+  * @note   As the RTC is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the RTC
+  *         (to be done once after reset).
+  * @note   These macros must be used after the RTC clock source was selected.
+  * @retval None
+  */
+#define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+#define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+/**
+  * @}
+  */
+
+/** @brief  Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  *         It is used (enabled by hardware) as system clock source after startup
+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+  *         of the HSE used directly or indirectly as system clock (if the Clock
+  *         Security System CSS is enabled).
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
+  *         you have to select another source of the system clock then stop the HSI.
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  * @retval None
+  */
+#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
+
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
+
+/** @brief  Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  __HSICALIBRATIONVALUE__ specifies the calibration trimming value
+  *         (default is RCC_HSICALIBRATION_DEFAULT).
+  *         This parameter must be a number between 0 and 0x7F.
+  * @retval None
+  */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
+                  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
+
+/**
+  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
+  *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
+  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
+  *           speed because of the HSI startup time.
+  * @note     The enable of this function has not effect on the HSION bit.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
+
+#define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
+
+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles.
+  * @retval None
+  */
+#define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
+
+#define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
+
+/**
+  * @brief  Macro to configure the External High Speed oscillator (HSE).
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this macro. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.
+  * @param  __STATE__ specifies the new state of the HSE.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_HSE_OFF  Turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                                   6 HSE oscillator clock cycles.
+  *            @arg @ref RCC_HSE_ON  Turn ON the HSE oscillator.
+  *            @arg @ref RCC_HSE_BYPASS  HSE oscillator bypassed with external clock.
+  * @retval None
+  */
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                                    \
+                    do {                                                   \
+                      if((__STATE__) == RCC_HSE_ON)                        \
+                      {                                                    \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                    \
+                      }                                                    \
+                      else if((__STATE__) == RCC_HSE_BYPASS)               \
+                      {                                                    \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);                   \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                    \
+                      }                                                    \
+                      else                                                 \
+                      {                                                    \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                  \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                 \
+                      }                                                    \
+                    } while(0)
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE).
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this macro. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @param  __STATE__ specifies the new state of the LSE.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_LSE_OFF  Turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                                   6 LSE oscillator clock cycles.
+  *            @arg @ref RCC_LSE_ON  Turn ON the LSE oscillator.
+  *            @arg @ref RCC_LSE_BYPASS  LSE oscillator bypassed with external clock.
+  * @retval None
+  */
+#define __HAL_RCC_LSE_CONFIG(__STATE__)                                        \
+                    do {                                                       \
+                      if((__STATE__) == RCC_LSE_ON)                            \
+                      {                                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                    \
+                      }                                                        \
+                      else if((__STATE__) == RCC_LSE_BYPASS)                   \
+                      {                                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                   \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                    \
+                      }                                                        \
+                      else                                                     \
+                      {                                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                 \
+                      }                                                        \
+                    } while(0)
+
+/** @brief  Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
+  * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   After enabling the HSI48, the application software should wait on HSI48RDY
+  *         flag to be set indicating that HSI48 clock is stable.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_HSI48_ENABLE()  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
+
+#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
+
+/** @brief  Macros to configure the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using the Power Backup Access macro before to configure
+  *         the RTC clock source (to be done once after reset).
+  * @note   Once the RTC clock is configured it cannot be changed unless the
+  *         Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
+  *         a Power On Reset (POR).
+  *
+  * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_RTCCLKSOURCE_NONE  No clock selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
+  *
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
+  *         RTC clock source).
+  * @retval None
+  */
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__)  \
+                  MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
+
+
+/** @brief  Macro to get the RTC clock source.
+  * @retval The returned value can be one of the following:
+  *            @arg @ref RCC_RTCCLKSOURCE_NONE  No clock selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
+  */
+#define  __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/** @brief  Macros to enable or disable the main PLL.
+  * @note   After enabling the main PLL, the application software should wait on
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The main PLL can not be disabled if it is used as system clock source
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+  * @retval None
+  */
+#define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLLON)
+
+#define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
+
+/** @brief  Macro to configure the PLL clock source.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
+  * @retval None
+  *
+  */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
+
+/** @brief  Macro to configure the PLL source division factor M.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *         This parameter must be a value of @ref RCC_PLLM_Clock_Divider.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency
+  *         of 8 MHz to limit PLL jitter.
+  * @retval None
+  *
+  */
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos)
+
+/**
+  * @brief  Macro to configure the main PLL clock source, multiplication and division factors.
+  * @note   This macro must be used only when the main PLL is disabled.
+  * @note   This macro preserves the PLL's output clocks enable state.
+  *
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
+  *
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock.
+  *          This parameter must be a value of @ref RCC_PLLM_Clock_Divider
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency
+  *         of 8 MHz to limit PLL jitter.
+  *
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock.
+  *          This parameter must be a number between 8 and 127.
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 64 and 344 MHz.
+  *
+  * @param  __PLLP__ specifies the division factor for SAI clock.
+  *          This parameter must be a number in the range (2 to 31).
+  *
+  * @param  __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
+  *          This parameter must be in the range (2, 4, 6 or 8).
+  * @note   If the USB OTG FS is used in your application, you have to set the
+  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+  *         the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
+  *         correctly.
+  * @param  __PLLR__ specifies the division factor for the main system clock.
+  * @note   You have to set the PLLR parameter correctly to not exceed 170MHZ.
+  *          This parameter must be in the range (2, 4, 6 or 8).
+  * @retval None
+  */
+#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
+                  MODIFY_REG(RCC->PLLCFGR, \
+                             (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
+                              RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \
+                             ((__PLLSOURCE__) | \
+                              (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
+                              ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
+                              ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
+                              ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
+                              ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))
+
+/** @brief  Macro to get the oscillator used as PLL clock source.
+  * @retval The oscillator used as PLL clock source. The returned value can be one
+  *         of the following:
+  *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
+
+/**
+  * @brief  Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK)
+  * @note   Enabling/disabling clock outputs RCC_PLL_ADCCLK and RCC_PLL_48M1CLK can be done at anytime
+  *         without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
+  *         be stopped if used as System Clock.
+  * @param  __PLLCLOCKOUT__ specifies the PLL clock to be output.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg @ref RCC_PLL_ADCCLK  This clock is used to generate a clock on ADC.
+  *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB (48 MHz),
+  *                                   FDCAN (<=48 MHz) and QSPI (<=48 MHz).
+  *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 170MHz)
+  * @retval None
+  */
+#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__)   SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
+
+#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
+
+/**
+  * @brief  Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
+  * @param  __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_PLL_ADCCLK  This clock is used to generate a clock on ADC.
+  *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB (48 MHz),
+  *                                   FDCAN (<=48 MHz) and QSPI (<=48 MHz).
+  *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 170MHz)
+  * @retval SET / RESET
+  */
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__)  READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
+
+/**
+  * @brief  Macro to configure the system clock source.
+  * @param  __SYSCLKSOURCE__ specifies the system clock source.
+  *          This parameter can be one of the following values:
+  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+  * @retval None
+  */
+#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
+
+/** @brief  Macro to get the clock source used as system clock.
+  * @retval The clock source used as system clock. The returned value can be one
+  *         of the following:
+  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
+  */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @param  __LSEDRIVE__ specifies the new state of the LSE drive capability.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_LSEDRIVE_LOW  LSE oscillator low drive capability.
+  *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW  LSE oscillator medium low drive capability.
+  *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH  LSE oscillator medium high drive capability.
+  *            @arg @ref RCC_LSEDRIVE_HIGH  LSE oscillator high drive capability.
+  * @retval None
+  */
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+                  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
+
+/** @brief  Macro to configure the MCO clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled
+  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System  clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee
+  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  Main PLL clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
+  *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
+  *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
+  *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
+  *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
+  */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+  * @brief macros to manage the specified RCC Flags and interrupts.
+  * @{
+  */
+
+/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
+  *         the selected interrupts).
+  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
+  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
+  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
+  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
+  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
+  * @retval None
+  */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
+  *        the selected interrupts).
+  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
+  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
+  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
+  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
+  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
+  * @retval None
+  */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
+  *         bits to clear the selected interrupt pending bits.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
+  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
+  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
+  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
+  *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt
+  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
+  *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
+  * @retval None
+  */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
+
+/** @brief  Check whether the RCC interrupt has occurred or not.
+  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
+  *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
+  *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
+  *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
+  *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt
+  *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
+  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags.
+  *        The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
+  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
+  * @retval None
+ */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
+
+/** @brief  Check whether the selected RCC flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_FLAG_HSIRDY  HSI oscillator clock ready
+  *            @arg @ref RCC_FLAG_HSERDY  HSE oscillator clock ready
+  *            @arg @ref RCC_FLAG_PLLRDY  Main PLL clock ready
+  *            @arg @ref RCC_FLAG_HSI48RDY  HSI48 clock ready for devices with HSI48
+  *            @arg @ref RCC_FLAG_LSERDY  LSE oscillator clock ready
+  *            @arg @ref RCC_FLAG_LSECSSD  Clock security system failure on LSE oscillator detection
+  *            @arg @ref RCC_FLAG_LSIRDY  LSI oscillator clock ready
+  *            @arg @ref RCC_FLAG_BORRST  BOR reset
+  *            @arg @ref RCC_FLAG_OBLRST  OBLRST reset
+  *            @arg @ref RCC_FLAG_PINRST  Pin reset
+  *            @arg @ref RCC_FLAG_SFTRST  Software reset
+  *            @arg @ref RCC_FLAG_IWDGRST  Independent Watchdog reset
+  *            @arg @ref RCC_FLAG_WWDGRST  Window Watchdog reset
+  *            @arg @ref RCC_FLAG_LPWRRST  Low Power reset
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                     \
+                                        ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR :                  \
+                                        ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                   \
+                                        ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) &    \
+                                          ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \
+                                            ? 1U : 0U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RCC_Private_Constants
+  * @{
+  */
+/* Defines used for Flags */
+#define CR_REG_INDEX              1U
+#define BDCR_REG_INDEX            2U
+#define CSR_REG_INDEX             3U
+#define CRRCR_REG_INDEX           4U
+
+#define RCC_FLAG_MASK             0x1FU
+
+/* Define used for IS_RCC_CLOCKTYPE() */
+#define RCC_CLOCKTYPE_ALL              (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2)  /*!< All clcoktype to configure */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros
+  * @{
+  */
+
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                               || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE)   == RCC_OSCILLATORTYPE_HSE)   || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI)   == RCC_OSCILLATORTYPE_HSI)   || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI)   == RCC_OSCILLATORTYPE_LSI)   || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE)   == RCC_OSCILLATORTYPE_LSE))
+
+#define IS_RCC_HSE(__HSE__)  (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
+                              ((__HSE__) == RCC_HSE_BYPASS))
+
+#define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+                              ((__LSE__) == RCC_LSE_BYPASS))
+
+#define IS_RCC_HSI(__HSI__)  (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
+
+#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
+
+#define IS_RCC_LSI(__LSI__)  (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+
+#define IS_RCC_HSI48(__HSI48__)  (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
+
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
+                             ((__PLL__) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
+                                      ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \
+                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
+
+#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
+
+#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
+
+#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
+                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
+
+#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
+                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
+
+#define IS_RCC_CLOCKTYPE(__CLK__)  ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
+
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
+                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
+                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \
+                               ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV8)   || \
+                               ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || \
+                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
+                               ((__HCLK__) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
+                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
+                               ((__PCLK__) == RCC_HCLK_DIV16))
+
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE)   || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)    || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)    || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
+
+#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO_PA8) || \
+                              ((__MCOX__) == RCC_MCO_PG10))
+
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
+
+#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
+                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
+                                ((__DIV__) == RCC_MCODIV_16))
+
+#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
+                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
+                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
+                                     ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
+
+/**
+  * @}
+  */
+
+/* Include RCC HAL Extended module */
+#include "stm32g4xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup RCC_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void              HAL_RCC_EnableCSS(void);
+void              HAL_RCC_EnableLSECSS(void);
+void              HAL_RCC_DisableLSECSS(void);
+uint32_t          HAL_RCC_GetSysClockFreq(void);
+uint32_t          HAL_RCC_GetHCLKFreq(void);
+uint32_t          HAL_RCC_GetPCLK1Freq(void);
+uint32_t          HAL_RCC_GetPCLK2Freq(void);
+void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+/* CSS NMI IRQ handler */
+void              HAL_RCC_NMI_IRQHandler(void);
+/* User Callbacks in non blocking mode (IT mode) */
+void              HAL_RCC_CSSCallback(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_RCC_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h
new file mode 100644
index 0000000..3dcc2f8
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h
@@ -0,0 +1,1606 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_rcc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_RCC_EX_H
+#define STM32G4xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
+                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source.
+                                        This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+  uint32_t Usart2ClockSelection;   /*!< Specifies USART2 clock source.
+                                        This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
+
+  uint32_t Usart3ClockSelection;   /*!< Specifies USART3 clock source.
+                                        This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
+
+#if defined(UART4)
+  uint32_t Uart4ClockSelection;    /*!< Specifies UART4 clock source.
+                                        This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+#endif /* UART4 */
+
+#if defined(UART5)
+  uint32_t Uart5ClockSelection;    /*!< Specifies UART5 clock source.
+                                        This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+#endif /* UART5 */
+
+  uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source.
+                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
+
+  uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source.
+                                        This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
+
+  uint32_t I2c2ClockSelection;     /*!< Specifies I2C2 clock source.
+                                        This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+  uint32_t I2c3ClockSelection;     /*!< Specifies I2C3 clock source.
+                                        This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+#if defined(I2C4)
+
+  uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source.
+                                        This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
+#endif /* I2C4 */
+
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source.
+                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
+
+  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source.
+                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
+
+  uint32_t I2sClockSelection;     /*!< Specifies I2S clock source.
+                                        This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+#if defined(FDCAN1)
+
+  uint32_t FdcanClockSelection;     /*!< Specifies FDCAN clock source.
+                                        This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */
+#endif /* FDCAN1 */
+#if defined(USB)
+
+  uint32_t UsbClockSelection;      /*!< Specifies USB clock source (warning: same source for RNG).
+                                        This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+#endif /* USB */
+
+  uint32_t RngClockSelection;      /*!< Specifies RNG clock source (warning: same source for USB).
+                                        This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
+
+  uint32_t Adc12ClockSelection;    /*!< Specifies ADC12 interface clock source.
+                                        This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+#if defined(ADC345_COMMON)
+  uint32_t Adc345ClockSelection;   /*!< Specifies ADC345 interface clock source.
+                                        This parameter can be a value of @ref RCCEx_ADC345_Clock_Source */
+#endif /* ADC345_COMMON */
+
+#if defined(QUADSPI)
+  uint32_t QspiClockSelection;     /*!< Specifies QuadSPI clock source.
+                                        This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */
+#endif
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC clock source.
+                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */
+}RCC_PeriphCLKInitTypeDef;
+
+/**
+  * @brief RCC_CRS Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
+                                       This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
+
+  uint32_t Source;                /*!< Specifies the SYNC signal source.
+                                       This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
+
+  uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
+                                       This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
+
+  uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
+                                       It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
+                                       This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
+
+  uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
+                                       This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
+
+  uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
+                                       This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
+
+}RCC_CRSInitTypeDef;
+
+/**
+  * @brief RCC_CRS Synchronization structure definition
+  */
+typedef struct
+{
+  uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
+                                       This parameter must be a number between 0 and 0xFFFF */
+
+  uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
+                                       This parameter must be a number between 0 and 0x7F */
+
+  uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter
+                                       value latched in the time of the last SYNC event.
+                                       This parameter must be a number between 0 and 0xFFFF */
+
+  uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
+                                       frequency error counter latched in the time of the last SYNC event.
+                                       It shows whether the actual frequency is below or above the target.
+                                       This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
+
+}RCC_CRSSynchroInfoTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
+  * @{
+  */
+#define RCC_LSCOSOURCE_LSI             0x00000000U           /*!< LSI selection for low speed clock output */
+#define RCC_LSCOSOURCE_LSE             RCC_BDCR_LSCOSEL      /*!< LSE selection for low speed clock output */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
+  * @{
+  */
+#define RCC_PERIPHCLK_USART1           0x00000001U
+#define RCC_PERIPHCLK_USART2           0x00000002U
+#define RCC_PERIPHCLK_USART3           0x00000004U
+#if defined(UART4)
+#define RCC_PERIPHCLK_UART4            0x00000008U
+#endif /* UART4 */
+#if defined(UART5)
+#define RCC_PERIPHCLK_UART5            0x00000010U
+#endif /* UART5 */
+#define RCC_PERIPHCLK_LPUART1          0x00000020U
+#define RCC_PERIPHCLK_I2C1             0x00000040U
+#define RCC_PERIPHCLK_I2C2             0x00000080U
+#define RCC_PERIPHCLK_I2C3             0x00000100U
+#define RCC_PERIPHCLK_LPTIM1           0x00000200U
+#define RCC_PERIPHCLK_SAI1             0x00000400U
+#define RCC_PERIPHCLK_I2S              0x00000800U
+#if defined(FDCAN1)
+#define RCC_PERIPHCLK_FDCAN            0x00001000U
+#endif /* FDCAN1 */
+#define RCC_PERIPHCLK_USB              0x00002000U
+#define RCC_PERIPHCLK_RNG              0x00004000U
+#define RCC_PERIPHCLK_ADC12            0x00008000U
+#if defined(ADC345_COMMON)
+#define RCC_PERIPHCLK_ADC345           0x00010000U
+#endif /* ADC345_COMMON */
+#if defined(I2C4)
+#define RCC_PERIPHCLK_I2C4             0x00020000U
+#endif /* I2C4 */
+#if defined(QUADSPI)
+#define RCC_PERIPHCLK_QSPI             0x00040000U
+#endif /* QUADSPI */
+#define RCC_PERIPHCLK_RTC              0x00080000U
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
+  * @{
+  */
+#define RCC_USART1CLKSOURCE_PCLK2      0x00000000U
+#define RCC_USART1CLKSOURCE_SYSCLK     RCC_CCIPR_USART1SEL_0
+#define RCC_USART1CLKSOURCE_HSI        RCC_CCIPR_USART1SEL_1
+#define RCC_USART1CLKSOURCE_LSE        (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
+  * @{
+  */
+#define RCC_USART2CLKSOURCE_PCLK1      0x00000000U
+#define RCC_USART2CLKSOURCE_SYSCLK     RCC_CCIPR_USART2SEL_0
+#define RCC_USART2CLKSOURCE_HSI        RCC_CCIPR_USART2SEL_1
+#define RCC_USART2CLKSOURCE_LSE        (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
+  * @{
+  */
+#define RCC_USART3CLKSOURCE_PCLK1      0x00000000U
+#define RCC_USART3CLKSOURCE_SYSCLK     RCC_CCIPR_USART3SEL_0
+#define RCC_USART3CLKSOURCE_HSI        RCC_CCIPR_USART3SEL_1
+#define RCC_USART3CLKSOURCE_LSE        (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
+/**
+  * @}
+  */
+
+#if defined(UART4)
+/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
+  * @{
+  */
+#define RCC_UART4CLKSOURCE_PCLK1       0x00000000U
+#define RCC_UART4CLKSOURCE_SYSCLK      RCC_CCIPR_UART4SEL_0
+#define RCC_UART4CLKSOURCE_HSI         RCC_CCIPR_UART4SEL_1
+#define RCC_UART4CLKSOURCE_LSE         (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
+/**
+  * @}
+  */
+#endif /* UART4 */
+
+#if defined(UART5)
+/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
+  * @{
+  */
+#define RCC_UART5CLKSOURCE_PCLK1       0x00000000U
+#define RCC_UART5CLKSOURCE_SYSCLK      RCC_CCIPR_UART5SEL_0
+#define RCC_UART5CLKSOURCE_HSI         RCC_CCIPR_UART5SEL_1
+#define RCC_UART5CLKSOURCE_LSE         (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
+/**
+  * @}
+  */
+#endif /* UART5 */
+
+/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
+  * @{
+  */
+#define RCC_LPUART1CLKSOURCE_PCLK1     0x00000000U
+#define RCC_LPUART1CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0
+#define RCC_LPUART1CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1
+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
+  * @{
+  */
+#define RCC_I2C1CLKSOURCE_PCLK1        0x00000000U
+#define RCC_I2C1CLKSOURCE_SYSCLK       RCC_CCIPR_I2C1SEL_0
+#define RCC_I2C1CLKSOURCE_HSI          RCC_CCIPR_I2C1SEL_1
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
+  * @{
+  */
+#define RCC_I2C2CLKSOURCE_PCLK1        0x00000000U
+#define RCC_I2C2CLKSOURCE_SYSCLK       RCC_CCIPR_I2C2SEL_0
+#define RCC_I2C2CLKSOURCE_HSI          RCC_CCIPR_I2C2SEL_1
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
+  * @{
+  */
+#define RCC_I2C3CLKSOURCE_PCLK1        0x00000000U
+#define RCC_I2C3CLKSOURCE_SYSCLK       RCC_CCIPR_I2C3SEL_0
+#define RCC_I2C3CLKSOURCE_HSI          RCC_CCIPR_I2C3SEL_1
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
+  * @{
+  */
+#define RCC_LPTIM1CLKSOURCE_PCLK1      0x00000000U
+#define RCC_LPTIM1CLKSOURCE_LSI        RCC_CCIPR_LPTIM1SEL_0
+#define RCC_LPTIM1CLKSOURCE_HSI        RCC_CCIPR_LPTIM1SEL_1
+#define RCC_LPTIM1CLKSOURCE_LSE        RCC_CCIPR_LPTIM1SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
+  * @{
+  */
+#define RCC_SAI1CLKSOURCE_SYSCLK       0x00000000U
+#define RCC_SAI1CLKSOURCE_PLL          RCC_CCIPR_SAI1SEL_0
+#define RCC_SAI1CLKSOURCE_EXT          RCC_CCIPR_SAI1SEL_1
+#define RCC_SAI1CLKSOURCE_HSI          (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
+  * @{
+  */
+#define RCC_I2SCLKSOURCE_SYSCLK       0x00000000U
+#define RCC_I2SCLKSOURCE_PLL          RCC_CCIPR_I2S23SEL_0
+#define RCC_I2SCLKSOURCE_EXT          RCC_CCIPR_I2S23SEL_1
+#define RCC_I2SCLKSOURCE_HSI          (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0)
+/**
+  * @}
+  */
+#if defined(FDCAN1)
+/** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source
+  * @{
+  */
+#define RCC_FDCANCLKSOURCE_HSE          0x00000000U
+#define RCC_FDCANCLKSOURCE_PLL          RCC_CCIPR_FDCANSEL_0
+#define RCC_FDCANCLKSOURCE_PCLK1        RCC_CCIPR_FDCANSEL_1
+/**
+  * @}
+  */
+#endif /* FDCAN1 */
+
+/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
+  * @{
+  */
+#define RCC_RNGCLKSOURCE_HSI48         0x00000000U
+#define RCC_RNGCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USB_Clock_Source USB Clock Source
+  * @{
+  */
+#define RCC_USBCLKSOURCE_HSI48         0x00000000U
+#define RCC_USBCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_ADC12_Clock_Source ADC12 Clock Source
+  * @{
+  */
+#define RCC_ADC12CLKSOURCE_NONE        0x00000000U
+#define RCC_ADC12CLKSOURCE_PLL         RCC_CCIPR_ADC12SEL_0
+#define RCC_ADC12CLKSOURCE_SYSCLK      RCC_CCIPR_ADC12SEL_1
+/**
+  * @}
+  */
+
+#if defined(ADC345_COMMON)
+/** @defgroup RCCEx_ADC345_Clock_Source ADC345 Clock Source
+  * @{
+  */
+#define RCC_ADC345CLKSOURCE_NONE     0x00000000U
+#define RCC_ADC345CLKSOURCE_PLL      RCC_CCIPR_ADC345SEL_0
+#define RCC_ADC345CLKSOURCE_SYSCLK   RCC_CCIPR_ADC345SEL_1
+/**
+  * @}
+  */
+#endif /* ADC345_COMMON */
+
+#if defined(I2C4)
+/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
+  * @{
+  */
+#define RCC_I2C4CLKSOURCE_PCLK1        0x00000000U
+#define RCC_I2C4CLKSOURCE_SYSCLK       RCC_CCIPR2_I2C4SEL_0
+#define RCC_I2C4CLKSOURCE_HSI          RCC_CCIPR2_I2C4SEL_1
+/**
+  * @}
+  */
+#endif /* I2C4 */
+
+#if defined(QUADSPI)
+/** @defgroup RCCEx_QSPI_Clock_Source QuadSPI Clock Source
+  * @{
+  */
+#define RCC_QSPICLKSOURCE_SYSCLK    0x00000000U
+#define RCC_QSPICLKSOURCE_HSI       RCC_CCIPR2_QSPISEL_0
+#define RCC_QSPICLKSOURCE_PLL       RCC_CCIPR2_QSPISEL_1
+/**
+  * @}
+  */
+#endif /* QUADSPI */
+
+/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
+  * @{
+  */
+#define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM19        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
+  * @{
+  */
+#define RCC_CRS_NONE                   0x00000000U
+#define RCC_CRS_TIMEOUT                0x00000001U
+#define RCC_CRS_SYNCOK                 0x00000002U
+#define RCC_CRS_SYNCWARN               0x00000004U
+#define RCC_CRS_SYNCERR                0x00000008U
+#define RCC_CRS_SYNCMISS               0x00000010U
+#define RCC_CRS_TRIMOVF                0x00000020U
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
+  * @{
+  */
+#define RCC_CRS_SYNC_SOURCE_GPIO       0x00000000U             /*!< Synchro Signal source GPIO */
+#define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
+#define RCC_CRS_SYNC_SOURCE_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
+  * @{
+  */
+#define RCC_CRS_SYNC_DIV1        0x00000000U                               /*!< Synchro Signal not divided (default) */
+#define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
+#define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
+#define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
+  * @{
+  */
+#define RCC_CRS_SYNC_POLARITY_RISING   0x00000000U             /*!< Synchro Active on rising edge (default) */
+#define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
+  * @{
+  */
+#define RCC_CRS_RELOADVALUE_DEFAULT    0x0000BB7FU             /*!< The reset value of the RELOAD field corresponds
+                                                                    to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
+  * @{
+  */
+#define RCC_CRS_ERRORLIMIT_DEFAULT     0x00000022U             /*!< Default Frequency error limit */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
+  * @{
+  */
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U             /*!< The default value is 32, which corresponds to the middle of the trimming interval.
+                                                                      The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
+                                                                      corresponds to a higher output frequency */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
+  * @{
+  */
+#define RCC_CRS_FREQERRORDIR_UP        0x00000000U               /*!< Upcounting direction, the actual frequency is above the target */
+#define RCC_CRS_FREQERRORDIR_DOWN      CRS_ISR_FEDIR             /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
+  * @{
+  */
+#define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */
+#define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */
+#define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */
+#define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */
+#define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */
+#define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */
+#define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE           /*!< Trimming overflow or underflow */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
+  * @{
+  */
+#define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
+#define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
+#define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */
+#define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
+#define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */
+#define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/
+#define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+ * @{
+ */
+
+/** @brief  Macro to configure the USART1 clock (USART1CLK).
+  *
+  * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
+  *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
+  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
+  *            @arg @ref RCC_USART1CLKSOURCE_LSE  LSE selected as USART1 clock
+  * @retval None
+  */
+#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
+
+/** @brief  Macro to get the USART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
+  *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
+  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
+  *            @arg @ref RCC_USART1CLKSOURCE_LSE  LSE selected as USART1 clock
+  */
+#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
+
+/** @brief  Macro to configure the USART2 clock (USART2CLK).
+  *
+  * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
+  *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
+  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
+  *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
+  * @retval None
+  */
+#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
+
+/** @brief  Macro to get the USART2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
+  *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
+  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
+  *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
+  */
+#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
+
+/** @brief  Macro to configure the USART3 clock (USART3CLK).
+  *
+  * @param  __USART3_CLKSOURCE__ specifies the USART3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
+  *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
+  *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
+  *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
+  * @retval None
+  */
+#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
+
+/** @brief  Macro to get the USART3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
+  *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
+  *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
+  *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
+  */
+#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
+
+#if defined(UART4)
+/** @brief  Macro to configure the UART4 clock (UART4CLK).
+  *
+  * @param  __UART4_CLKSOURCE__ specifies the UART4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
+  *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock
+  *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock
+  *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock
+  * @retval None
+  */
+#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
+
+/** @brief  Macro to get the UART4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
+  *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock
+  *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock
+  *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock
+  */
+#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
+#endif /* UART4 */
+
+#if defined(UART5)
+
+/** @brief  Macro to configure the UART5 clock (UART5CLK).
+  *
+  * @param  __UART5_CLKSOURCE__ specifies the UART5 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
+  *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock
+  *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock
+  *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock
+  * @retval None
+  */
+#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
+
+/** @brief  Macro to get the UART5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
+  *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock
+  *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock
+  *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock
+  */
+#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))
+
+#endif /* UART5 */
+
+/** @brief  Macro to configure the LPUART1 clock (LPUART1CLK).
+  *
+  * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
+  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
+  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
+  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
+  * @retval None
+  */
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
+
+/** @brief  Macro to get the LPUART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
+  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
+  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
+  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
+  */
+#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
+
+/** @brief  Macro to configure the I2C1 clock (I2C1CLK).
+  *
+  * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock
+  *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
+  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
+  * @retval None
+  */
+#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock
+  *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
+  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
+  */
+#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
+
+
+/** @brief  Macro to configure the I2C2 clock (I2C2CLK).
+  *
+  * @param  __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock
+  *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
+  *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
+  * @retval None
+  */
+#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock
+  *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
+  *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
+  */
+#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
+
+/** @brief  Macro to configure the I2C3 clock (I2C3CLK).
+  *
+  * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock
+  *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock
+  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
+  * @retval None
+  */
+#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock
+  *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock
+  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
+  */
+#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
+
+#if defined(I2C4)
+
+/** @brief  Macro to configure the I2C4 clock (I2C4CLK).
+  *
+  * @param  __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_I2C4CLKSOURCE_PCLK1  PCLK1 selected as I2C4 clock
+  *            @arg @ref RCC_I2C4CLKSOURCE_HSI  HSI selected as I2C4 clock
+  *            @arg @ref RCC_I2C4CLKSOURCE_SYSCLK  System Clock selected as I2C4 clock
+  * @retval None
+  */
+#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_I2C4CLKSOURCE_PCLK1  PCLK1 selected as I2C4 clock
+  *            @arg @ref RCC_I2C4CLKSOURCE_HSI  HSI selected as I2C4 clock
+  *            @arg @ref RCC_I2C4CLKSOURCE_SYSCLK  System Clock selected as I2C4 clock
+  */
+#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))
+
+#endif /* I2C4 */
+
+/** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
+  *
+  * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 selected as LPTIM1 clock
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPTIM1 clock
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  LSI selected as LPTIM1 clock
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPTIM1 clock
+  * @retval None
+  */
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
+
+/** @brief  Macro to get the LPTIM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPUART1 clock
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  System Clock selected as LPUART1 clock
+  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPUART1 clock
+  */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
+
+/**
+  * @brief  Macro to configure the SAI1 clock source.
+  * @param  __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
+  *         from the HSI, system PLL, System Clock or external clock.
+  *          This parameter can be one of the following values:
+  *             @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLL    SAI1 clock = PLL "Q" clock
+  *             @arg @ref RCC_SAI1CLKSOURCE_EXT    SAI1 clock = EXT
+  *             @arg @ref RCC_SAI1CLKSOURCE_HSI    SAI1 clock = HSI
+  *
+  * @retval None
+  */
+#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
+
+/** @brief  Macro to get the SAI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
+  *             @arg @ref RCC_SAI1CLKSOURCE_PLL    SAI1 clock = PLL "Q" clock
+  *             @arg @ref RCC_SAI1CLKSOURCE_EXT    SAI1 clock = EXT
+  *             @arg @ref RCC_SAI1CLKSOURCE_HSI    SAI1 clock = HSI
+  *
+  */
+#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
+
+/**
+  * @brief  Macro to configure the I2S clock source.
+  * @param  __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived
+  *         from the HSI, system PLL, System Clock or external clock.
+  *          This parameter can be one of the following values:
+  *             @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
+  *             @arg @ref RCC_I2SCLKSOURCE_PLL    I2S clock = PLL "Q" clock
+  *             @arg @ref RCC_I2SCLKSOURCE_EXT    I2S clock = EXT
+  *             @arg @ref RCC_I2SCLKSOURCE_HSI    I2S clock = HSI
+  *
+  * @retval None
+  */
+#define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__)\
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__))
+
+/** @brief  Macro to get the I2S clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
+  *             @arg @ref RCC_I2SCLKSOURCE_PLL    I2S clock = PLL "Q" clock
+  *             @arg @ref RCC_I2SCLKSOURCE_EXT    I2S clock = EXT
+  *             @arg @ref RCC_I2SCLKSOURCE_HSI    I2S clock = HSI
+  *
+  */
+#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL)))
+
+#if defined(FDCAN1)
+/**
+  * @brief  Macro to configure the FDCAN clock source.
+  * @param  __FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is derived
+  *         from the HSE, system PLL or PCLK1.
+  *          This parameter can be one of the following values:
+  *             @arg @ref RCC_FDCANCLKSOURCE_HSE   FDCAN clock = HSE
+  *             @arg @ref RCC_FDCANCLKSOURCE_PLL   FDCAN clock = PLL "Q" clock
+  *             @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
+  *
+  * @retval None
+  */
+#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__)\
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
+
+/** @brief  Macro to get the FDCAN clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg @ref RCC_FDCANCLKSOURCE_HSE   FDCAN clock = HSE
+  *             @arg @ref RCC_FDCANCLKSOURCE_PLL   FDCAN clock = PLL "Q" clock
+  *             @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
+  *
+  */
+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL)))
+#endif /* FDCAN1 */
+
+/** @brief  Macro to configure the RNG clock.
+  *
+  * @note  USB and RNG peripherals share the same 48MHz clock source.
+  *
+  * @param  __RNG_CLKSOURCE__ specifies the RNG clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock for devices with HSI48
+  *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL Clock selected as RNG clock
+  * @retval None
+  */
+#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
+
+/** @brief  Macro to get the RNG clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock for devices with HSI48
+  *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL "Q" clock selected as RNG clock
+  */
+#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
+
+#if defined(USB)
+
+/** @brief  Macro to configure the USB clock (USBCLK).
+  *
+  * @note  USB, RNG peripherals share the same 48MHz clock source.
+  *
+  * @param  __USB_CLKSOURCE__ specifies the USB clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
+  *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock
+  * @retval None
+  */
+#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
+
+/** @brief  Macro to get the USB clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
+  *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock
+  */
+#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
+
+#endif /* USB */
+
+/** @brief  Macro to configure the ADC12 interface clock.
+  * @param  __ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_ADC12CLKSOURCE_NONE    No clock selected as ADC12 clock
+  *            @arg @ref RCC_ADC12CLKSOURCE_PLL     PLL Clock selected as ADC12 clock
+  *            @arg @ref RCC_ADC12CLKSOURCE_SYSCLK  System Clock selected as ADC12 clock
+  * @retval None
+  */
+#define __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__))
+
+/** @brief  Macro to get the ADC12 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_ADC12CLKSOURCE_NONE    No clock selected as ADC12 clock
+  *            @arg @ref RCC_ADC12CLKSOURCE_PLL     PLL Clock selected as ADC12 clock
+  *            @arg @ref RCC_ADC12CLKSOURCE_SYSCLK  System Clock selected as ADC12 clock
+  */
+#define __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL))
+
+#if defined(ADC345_COMMON)
+/** @brief  Macro to configure the ADC345 interface clock.
+  * @param  __ADC345_CLKSOURCE__ specifies the ADC345 digital interface clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_ADC345CLKSOURCE_NONE    No clock selected as ADC345 clock
+  *            @arg @ref RCC_ADC345CLKSOURCE_PLL     PLL Clock selected as ADC345 clock
+  *            @arg @ref RCC_ADC345CLKSOURCE_SYSCLK  System Clock selected as ADC345 clock
+  * @retval None
+  */
+#define __HAL_RCC_ADC345_CONFIG(__ADC345_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC345SEL, __ADC345_CLKSOURCE__)
+
+/** @brief  Macro to get the ADC345 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_ADC345CLKSOURCE_NONE    No clock selected as ADC345 clock
+  *            @arg @ref RCC_ADC345CLKSOURCE_PLL     PLL Clock selected as ADC345 clock
+  *            @arg @ref RCC_ADC345CLKSOURCE_SYSCLK  System Clock selected as ADC345 clock
+  */
+#define __HAL_RCC_GET_ADC345_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC345SEL))
+#endif /* ADC345_COMMON */
+
+#if defined(QUADSPI)
+
+/** @brief  Macro to configure the QuadSPI clock.
+  * @param  __QSPI_CLKSOURCE__ specifies the QuadSPI clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_QSPICLKSOURCE_SYSCLK  System Clock selected as QuadSPI clock
+  *            @arg @ref RCC_QSPICLKSOURCE_HSI     HSI clock selected as QuadSPI clock
+  *            @arg @ref RCC_QSPICLKSOURCE_PLL     PLL Q divider clock selected as QuadSPI clock
+  * @retval None
+  */
+#define __HAL_RCC_QSPI_CONFIG(__QSPI_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, __QSPI_CLKSOURCE__)
+
+/** @brief  Macro to get the QuadSPI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_QSPICLKSOURCE_SYSCLK  System Clock selected as QuadSPI clock
+  *            @arg @ref RCC_QSPICLKSOURCE_HSI     HSI clock selected as QuadSPI clock
+  *            @arg @ref RCC_QSPICLKSOURCE_PLL     PLL Q divider clock selected as QuadSPI clock
+  */
+#define __HAL_RCC_GET_QSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_QSPISEL))
+
+#endif /* QUADSPI */
+
+/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
+  * @brief macros to manage the specified RCC Flags and interrupts.
+  * @{
+  */
+
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                      \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                       \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
+  * @retval EXTI RCC LSE CSS Line Status.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Clear the RCC LSE CSS EXTI flag.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief  Enable the specified CRS interrupts.
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval None
+  */
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified CRS interrupts.
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval None
+  */
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
+
+/** @brief  Check whether the CRS interrupt has occurred or not.
+  * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
+  *         This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
+
+/** @brief  Clear the CRS interrupt pending bits
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
+  */
+/* CRS IT Error Mask */
+#define  RCC_CRS_IT_ERROR_MASK                 (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
+
+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
+                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
+                                                 } \
+                                                 else \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
+                                                 } \
+                                               } while(0)
+
+/**
+  * @brief  Check whether the specified CRS flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
+  * @retval The new state of _FLAG_ (TRUE or FALSE).
+  */
+#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the CRS specified FLAG.
+  * @param __FLAG__ specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
+  * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
+  * @retval None
+  */
+
+/* CRS Flag Error Mask */
+#define RCC_CRS_FLAG_ERROR_MASK                (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
+
+#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
+                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
+                                                 } \
+                                                 else \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \
+                                                 } \
+                                               } while(0)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
+  * @{
+  */
+/**
+  * @brief  Enable the oscillator clock for frequency error counter.
+  * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+  * @brief  Disable the oscillator clock for frequency error counter.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+  * @brief  Enable the automatic hardware adjustment of TRIM bits.
+  * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+  * @brief  Enable or disable the automatic hardware adjustment of TRIM bits.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency
+  *             of the synchronization source after prescaling. It is then decreased by one in order to
+  *             reach the expected synchronization on the zero value. The formula is the following:
+  *             RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval None
+  */
+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group2
+  * @{
+  */
+
+void              HAL_RCCEx_EnableLSECSS(void);
+void              HAL_RCCEx_DisableLSECSS(void);
+void              HAL_RCCEx_EnableLSECSS_IT(void);
+void              HAL_RCCEx_LSECSS_IRQHandler(void);
+void              HAL_RCCEx_LSECSS_Callback(void);
+void              HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
+void              HAL_RCCEx_DisableLSCO(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group3
+  * @{
+  */
+
+void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
+void              HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
+void              HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
+uint32_t          HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
+void              HAL_RCCEx_CRS_IRQHandler(void);
+void              HAL_RCCEx_CRS_SyncOkCallback(void);
+void              HAL_RCCEx_CRS_SyncWarnCallback(void);
+void              HAL_RCCEx_CRS_ExpectedSyncCallback(void);
+void              HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros
+  * @{
+  */
+
+#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
+                                       ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
+
+#if defined(STM32G474xx) || defined(STM32G484xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)       == RCC_PERIPHCLK_FDCAN)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC345)      == RCC_PERIPHCLK_ADC345)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_QSPI)        == RCC_PERIPHCLK_QSPI)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)       == RCC_PERIPHCLK_FDCAN)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC345)      == RCC_PERIPHCLK_ADC345)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_QSPI)        == RCC_PERIPHCLK_QSPI)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)       == RCC_PERIPHCLK_FDCAN)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC345)      == RCC_PERIPHCLK_ADC345)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_QSPI)        == RCC_PERIPHCLK_QSPI)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
+
+#elif defined(STM32G471xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
+
+#elif defined(STM32G431xx) || defined(STM32G441xx)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)       == RCC_PERIPHCLK_FDCAN)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
+
+#elif defined(STM32GBK1CB)
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+               ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
+                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
+                (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)       == RCC_PERIPHCLK_FDCAN)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
+                (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
+                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
+
+#endif /* STM32G474xx || STM32G484xx */
+
+#define IS_RCC_USART1CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
+                ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
+                ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
+                ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
+
+#define IS_RCC_USART2CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
+                ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
+                ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
+                ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
+
+#define IS_RCC_USART3CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \
+                ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
+                ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \
+                ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
+
+#if defined(UART4)
+#define IS_RCC_UART4CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1)  || \
+                ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
+                ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)    || \
+                ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
+#endif /* UART4 */
+
+#if defined(UART5)
+#define IS_RCC_UART5CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1)  || \
+                ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
+                ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)    || \
+                ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
+
+#endif /* UART5 */
+
+#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
+                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
+                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
+                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__)   \
+               (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
+                ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
+                ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C2CLKSOURCE(__SOURCE__)   \
+               (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
+                ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
+                ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
+
+#define IS_RCC_I2C3CLKSOURCE(__SOURCE__)   \
+               (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
+                ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
+                ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
+
+#if defined(I2C4)
+
+#define IS_RCC_I2C4CLKSOURCE(__SOURCE__)   \
+               (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
+                ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
+                ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
+
+#endif /* I2C4 */
+
+#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
+                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)   || \
+                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)   || \
+                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
+
+#define IS_RCC_SAI1CLKSOURCE(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK)  || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT)     || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
+
+#define IS_RCC_I2SCLKSOURCE(__SOURCE__)   \
+               (((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK)  || \
+                ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_I2SCLKSOURCE_EXT)     || \
+                ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI))
+
+#if defined(FDCAN1)
+#define IS_RCC_FDCANCLKSOURCE(__SOURCE__)   \
+               (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
+                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
+                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1))
+
+#endif /* FDCAN1 */
+#define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)   || \
+                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL))
+
+#if defined(USB)
+#define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \
+                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
+
+#endif /* USB */
+
+#define IS_RCC_ADC12CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE)    || \
+                ((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK))
+
+#if defined(ADC345_COMMON)
+#define IS_RCC_ADC345CLKSOURCE(__SOURCE__)  \
+               (((__SOURCE__) == RCC_ADC345CLKSOURCE_NONE)    || \
+                ((__SOURCE__) == RCC_ADC345CLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_ADC345CLKSOURCE_SYSCLK))
+#endif /* ADC345_COMMON */
+
+#if defined(QUADSPI)
+
+#define IS_RCC_QSPICLKSOURCE(__SOURCE__)  \
+                (((__SOURCE__) == RCC_QSPICLKSOURCE_HSI)   || \
+                 ((__SOURCE__) == RCC_QSPICLKSOURCE_SYSCLK)|| \
+                 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL))
+
+#endif /* QUADSPI */
+
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
+
+#define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
+
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
+                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
+
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
+
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
+
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
+
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
+                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_RCC_EX_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h
new file mode 100644
index 0000000..acc47aa
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h
@@ -0,0 +1,2631 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_TIM_H
+#define STM32G4xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Time base Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+                                   Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+                                   (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(),
+                                    __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(),
+                                    __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_ClockDivision */
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                    reaches zero, an update event is generated and counting restarts
+                                    from the RCR value (N).
+                                    This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                     Max_Data = 0xFF.
+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                     Max_Data = 0xFFFF. */
+
+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+                               (or 0xFFEF if dithering is activated)
+                               Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
+                               Pulse value */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
+                               This parameter can be a value of @ref TIM_Output_Fast_State
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+} TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM One Pulse Mode Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+                               (or 0xFFEF if dithering is activated)
+                               Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
+                               Pulse value */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;   /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+  * @brief  TIM Encoder Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Mode */
+
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC1Selection;  /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC2Selection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+  * @brief  Clock Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;     /*!< TIM clock sources
+                                 This parameter can be a value of @ref TIM_Clock_Source */
+  uint32_t ClockPolarity;   /*!< TIM clock polarity
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
+  uint32_t ClockFilter;     /*!< TIM clock filter
+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+  * @brief  TIM Clear Input Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClearInputState;      /*!< TIM clear Input state
+                                      This parameter can be ENABLE or DISABLE */
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source,
+                                      ETR prescaler must be off */
+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+  * @brief  TIM Master configuration Structure definition
+  * @note   Advanced timers provide TRGO2 internal line which is redirected
+  *         to the ADC
+  */
+typedef struct
+{
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
+  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
+                                        @note When the Master/slave mode is enabled, the effect of
+                                        an event on the trigger input (TRGI) is delayed to allow a
+                                        perfect synchronization between the current timer and its
+                                        slaves (through TRGO). It is not mandatory in case of timer
+                                        synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+  * @brief  TIM Slave configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  SlaveMode;         /*!< Slave mode selection
+                                    This parameter can be a value of @ref TIM_Slave_Mode */
+  uint32_t  InputTrigger;      /*!< Input Trigger source
+                                    This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter
+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+  * @brief  TIM Break input(s) and Dead time configuration Structure definition
+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
+  *        filter and polarity.
+  */
+typedef struct
+{
+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint32_t LockLevel;            /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
+
+  uint32_t DeadTime;             /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+  uint32_t BreakState;           /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+  uint32_t BreakPolarity;        /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
+
+  uint32_t BreakFilter;          /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t BreakAFMode;          /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
+
+  uint32_t Break2State;          /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+
+  uint32_t Break2Polarity;       /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
+
+  uint32_t Break2Filter;         /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Break2AFMode;         /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
+
+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
+} HAL_TIM_StateTypeDef;
+
+/**
+  * @brief  TIM Channel States definition
+  */
+typedef enum
+{
+  HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */
+  HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */
+  HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */
+} HAL_TIM_ChannelStateTypeDef;
+
+/**
+  * @brief  DMA Burst States definition
+  */
+typedef enum
+{
+  HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */
+  HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */
+  HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */
+} HAL_TIM_DMABurstStateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
+typedef enum
+{
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
+  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+  * @brief  TIM Time Base Handle Structure definition
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+  TIM_TypeDef                        *Instance;         /*!< Register base address                             */
+  TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */
+  HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */
+  DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array
+                                                             This array is accessed by a @ref DMA_Handle_index */
+  HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */
+  __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */
+  __IO HAL_TIM_ChannelStateTypeDef   ChannelState[6];   /*!< TIM channel operation state                       */
+  __IO HAL_TIM_ChannelStateTypeDef   ChannelNState[4];  /*!< TIM complementary channel operation state         */
+  __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
+  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
+  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
+  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
+  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
+  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
+  void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
+  void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Encoder Index Callback                              */
+  void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Direction Change Callback                           */
+  void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Index Error Callback                                */
+  void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Transition Error Callback                           */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL TIM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                              */
+  , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                            */
+  , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                */
+  , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                              */
+  , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                */
+  , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                              */
+  , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                               */
+  , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                             */
+  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                         */
+  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                       */
+  , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                           */
+  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                         */
+  , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
+  , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
+  , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
+  , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
+
+  , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
+  , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
+  , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
+  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID           */
+  , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
+  , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
+  , HAL_TIM_COMMUTATION_CB_ID             = 0x18U   /*!< TIM Commutation Callback ID                                */
+  , HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U   /*!< TIM Commutation half complete Callback ID                  */
+  , HAL_TIM_BREAK_CB_ID                   = 0x1AU   /*!< TIM Break Callback ID                                      */
+  , HAL_TIM_BREAK2_CB_ID                  = 0x1BU   /*!< TIM Break2 Callback ID                                     */
+  , HAL_TIM_ENCODER_INDEX_CB_ID           = 0x1CU   /*!< TIM Encoder Index Callback ID                              */
+  , HAL_TIM_DIRECTION_CHANGE_CB_ID        = 0x1DU   /*!< TIM Direction Change Callback ID                           */
+  , HAL_TIM_INDEX_ERROR_CB_ID             = 0x1EU   /*!< TIM Index Error Callback ID                                */
+  , HAL_TIM_TRANSITION_ERROR_CB_ID        = 0x1FU   /*!< TIM Transition Error Callback ID                           */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL TIM Callback pointer definition
+  */
+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+  * @{
+  */
+#define TIM_CLEARINPUTSOURCE_NONE     0xFFFFFFFFU                               /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR      0x00000001U                               /*!< OCREF_CLR is connected to ETRF input */
+#define TIM_CLEARINPUTSOURCE_COMP1    0x00000000U                               /*!< OCREF_CLR_INT is connected to COMP1 output */
+#define TIM_CLEARINPUTSOURCE_COMP2    TIM1_AF2_OCRSEL_0                         /*!< OCREF_CLR_INT is connected to COMP2 output */
+#define TIM_CLEARINPUTSOURCE_COMP3    TIM1_AF2_OCRSEL_1                         /*!< OCREF_CLR_INT is connected to COMP3 output */
+#define TIM_CLEARINPUTSOURCE_COMP4    (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0)   /*!< OCREF_CLR_INT is connected to COMP4 output */
+#if defined (COMP5)
+#define TIM_CLEARINPUTSOURCE_COMP5    TIM1_AF2_OCRSEL_2                         /*!< OCREF_CLR_INT is connected to COMP5 output */
+#endif /* COMP5 */
+#if defined (COMP6)
+#define TIM_CLEARINPUTSOURCE_COMP6    (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0)   /*!< OCREF_CLR_INT is connected to COMP6 output */
+#endif /* COMP6 */
+#if defined (COMP7)
+#define TIM_CLEARINPUTSOURCE_COMP7    (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1)   /*!< OCREF_CLR_INT is connected to COMP7 output */
+#endif /* COMP7 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+  * @{
+  */
+#define TIM_DMABASE_CR1                    0x00000000U
+#define TIM_DMABASE_CR2                    0x00000001U
+#define TIM_DMABASE_SMCR                   0x00000002U
+#define TIM_DMABASE_DIER                   0x00000003U
+#define TIM_DMABASE_SR                     0x00000004U
+#define TIM_DMABASE_EGR                    0x00000005U
+#define TIM_DMABASE_CCMR1                  0x00000006U
+#define TIM_DMABASE_CCMR2                  0x00000007U
+#define TIM_DMABASE_CCER                   0x00000008U
+#define TIM_DMABASE_CNT                    0x00000009U
+#define TIM_DMABASE_PSC                    0x0000000AU
+#define TIM_DMABASE_ARR                    0x0000000BU
+#define TIM_DMABASE_RCR                    0x0000000CU
+#define TIM_DMABASE_CCR1                   0x0000000DU
+#define TIM_DMABASE_CCR2                   0x0000000EU
+#define TIM_DMABASE_CCR3                   0x0000000FU
+#define TIM_DMABASE_CCR4                   0x00000010U
+#define TIM_DMABASE_BDTR                   0x00000011U
+#define TIM_DMABASE_CCR5                   0x00000012U
+#define TIM_DMABASE_CCR6                   0x00000013U
+#define TIM_DMABASE_CCMR3                  0x00000014U
+#define TIM_DMABASE_DTR2                   0x00000015U
+#define TIM_DMABASE_ECR                    0x00000016U
+#define TIM_DMABASE_TISEL                  0x00000017U
+#define TIM_DMABASE_AF1                    0x00000018U
+#define TIM_DMABASE_AF2                    0x00000019U
+#define TIM_DMABASE_OR                     0x0000001AU
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+  * @{
+  */
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+  * @{
+  */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+  * @{
+  */
+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+  * @{
+  */
+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+  * @{
+  */
+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+  * @{
+  */
+#define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+  * @{
+  */
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+  * @{
+  */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+  * @{
+  */
+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+  * @{
+  */
+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+  * @{
+  */
+#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+  * @{
+  */
+#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+  * @{
+  */
+#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+  * @{
+  */
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+  * @{
+  */
+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+  * @{
+  */
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+  * @{
+  */
+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+  * @{
+  */
+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
+#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)                                   /*!< Encoder mode: Clock plus direction, x2 mode */
+#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
+#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2      (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)                                   /*!< Encoder mode: Directional Clock, x2 mode */
+#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
+#define TIM_ENCODERMODE_X1_TI1                   (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
+#define TIM_ENCODERMODE_X1_TI2                   (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+  * @{
+  */
+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
+#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
+#define TIM_IT_IDX                         TIM_DIER_IDXIE                       /*!< Index interrupt             */
+#define TIM_IT_DIR                         TIM_DIER_DIRIE                       /*!< Direction change interrupt  */
+#define TIM_IT_IERR                        TIM_DIER_IERRIE                      /*!< Index error interrupt       */
+#define TIM_IT_TERR                        TIM_DIER_TERRIE                      /*!< Transition error interrupt  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source
+  * @{
+  */
+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+  * @{
+  */
+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+  * @{
+  */
+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
+#define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
+#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
+#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
+#define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
+#define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
+#define TIM_FLAG_IDX                       TIM_SR_IDXF                          /*!< Encoder index flag            */
+#define TIM_FLAG_DIR                       TIM_SR_DIRF                          /*!< Direction change flag         */
+#define TIM_FLAG_IERR                      TIM_SR_IERRF                         /*!< Index error flag              */
+#define TIM_FLAG_TERR                      TIM_SR_TERRF                         /*!< Transition error flag         */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Channel TIM Channel
+  * @{
+  */
+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
+#define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
+#define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+  * @{
+  */
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
+#if defined (TIM5)
+#define TIM_CLOCKSOURCE_ITR4        TIM_TS_ITR4          /*!< External clock source mode 1 (ITR4)                   */
+#endif /* TIM5 */
+#define TIM_CLOCKSOURCE_ITR5        TIM_TS_ITR5          /*!< External clock source mode 1 (ITR5)                   */
+#define TIM_CLOCKSOURCE_ITR6        TIM_TS_ITR6          /*!< External clock source mode 1 (ITR6)                   */
+#define TIM_CLOCKSOURCE_ITR7        TIM_TS_ITR7          /*!< External clock source mode 1 (ITR7)                   */
+#define TIM_CLOCKSOURCE_ITR8        TIM_TS_ITR8          /*!< External clock source mode 1 (ITR8)                   */
+#if defined (TIM20)
+#define TIM_CLOCKSOURCE_ITR9        TIM_TS_ITR9          /*!< External clock source mode 1 (ITR9)                   */
+#endif /* TIM20 */
+#define TIM_CLOCKSOURCE_ITR10       TIM_TS_ITR10         /*!< External clock source mode 1 (ITR10)                  */
+#define TIM_CLOCKSOURCE_ITR11       TIM_TS_ITR11         /*!< External clock source mode 1 (ITR11)                  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+  * @{
+  */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+  * @{
+  */
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+  * @{
+  */
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+  * @{
+  */
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+  * @{
+  */
+#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+  * @{
+  */
+#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+/** @defgroup TIM_Lock_level  TIM Lock level
+  * @{
+  */
+#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
+#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+  * @{
+  */
+#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
+#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+  * @{
+  */
+#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
+#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
+  * @{
+  */
+#define TIM_BREAK_AFMODE_INPUT             0x00000000U                          /*!< Break input BRK in input mode */
+#define TIM_BREAK_AFMODE_BIDIRECTIONAL     TIM_BDTR_BKBID                       /*!< Break input BRK in bidirectional mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
+  * @{
+  */
+#define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
+#define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
+  * @{
+  */
+#define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
+#define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
+  * @{
+  */
+#define TIM_BREAK2_AFMODE_INPUT            0x00000000U                          /*!< Break2 input BRK2 in input mode */
+#define TIM_BREAK2_AFMODE_BIDIRECTIONAL    TIM_BDTR_BK2BID                      /*!< Break2 input BRK2 in bidirectional mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+  * @{
+  */
+#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
+  * @{
+  */
+#define TIM_GROUPCH5_NONE                  0x00000000U                          /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /*!< OC1REFC is the logical AND of OC1REFC and OC5REF    */
+#define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /*!< OC2REFC is the logical AND of OC2REFC and OC5REF    */
+#define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /*!< OC3REFC is the logical AND of OC3REFC and OC5REF    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+  * @{
+  */
+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_ENCODER_CLK      TIM_CR2_MMS_3                                    /*!< Encoder clock is used as trigger output(TRGO)                 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
+  * @{
+  */
+#define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
+#define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
+#define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
+#define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+  * @{
+  */
+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+  * @{
+  */
+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
+#define TIM_SLAVEMODE_COMBINED_GATEDRESET    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)                  /*!< Combined gated + reset mode   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+  * @{
+  */
+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
+#define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
+#define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
+#define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
+#define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
+#define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
+#define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
+#define TIM_OCMODE_PULSE_ON_COMPARE        (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)                     /*!< Pulse on compare (CH3&CH4 only)        */
+#define TIM_OCMODE_DIRECTION_OUTPUT        (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0)  /*!< Direction output (CH3&CH4 only)        */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+  * @{
+  */
+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
+#if defined (TIM5)
+#define TIM_TS_ITR4          TIM_SMCR_TS_3                                                     /*!< Internal Trigger 4 (ITR9)              */
+#endif /* TIM5 */
+#define TIM_TS_ITR5          (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 5 (ITR5)              */
+#define TIM_TS_ITR6          (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 6 (ITR6)              */
+#define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */
+#define TIM_TS_ITR8          (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 8 (ITR8)              */
+#if defined (TIM20)
+#define TIM_TS_ITR9          (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 9 (ITR9)              */
+#endif /* TIM20 */
+#define TIM_TS_ITR10         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 10 (ITR10)            */
+#define TIM_TS_ITR11         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)   /*!< Internal Trigger 11 (ITR11)            */
+#define TIM_TS_NONE          0xFFFFFFFFU                                                       /*!< No trigger selected                    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+  * @{
+  */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+  * @{
+  */
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+  * @{
+  */
+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+  * @{
+  */
+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */
+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_19TRANSFERS     0x00001200U                          /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_20TRANSFERS     0x00001300U                          /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_21TRANSFERS     0x00001400U                          /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_22TRANSFERS     0x00001500U                          /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_23TRANSFERS     0x00001600U                          /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_24TRANSFERS     0x00001700U                          /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_25TRANSFERS     0x00001800U                          /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_26TRANSFERS     0x00001900U                          /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+  * @{
+  */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+  * @}
+  */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+  * @{
+  */
+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_System TIM Break System
+  * @{
+  */
+#define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20 */
+#define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */
+#define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @brief  Reset TIM handle state.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;            \
+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;            \
+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;            \
+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \
+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \
+                                                     } while(0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
+                                                     } while(0)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+  * @brief  Enable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+  * @brief  Disable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
+  *       disabled
+  */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled unconditionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief  Enable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  *            @arg TIM_IT_IDX: Index interrupt
+  *            @arg TIM_IT_DIR: Direction change interrupt
+  *            @arg TIM_IT_IERR: Index error interrupt
+  *            @arg TIM_IT_TERR: Transition error interrupt
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  *            @arg TIM_IT_IDX: Index interrupt
+  *            @arg TIM_IT_DIR: Direction change interrupt
+  *            @arg TIM_IT_IERR: Index error interrupt
+  *            @arg TIM_IT_TERR: Transition error interrupt
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief  Check whether the specified TIM interrupt flag is set or not.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  *            @arg TIM_FLAG_IDX: Index interrupt flag
+  *            @arg TIM_FLAG_DIR: Direction change interrupt flag
+  *            @arg TIM_FLAG_IERR: Index error interrupt flag
+  *            @arg TIM_FLAG_TERR: Transition error interrupt flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified TIM interrupt flag.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  *            @arg TIM_FLAG_IDX: Index interrupt flag
+  *            @arg TIM_FLAG_DIR: Direction change interrupt flag
+  *            @arg TIM_FLAG_IERR: Index error interrupt flag
+  *            @arg TIM_FLAG_TERR: Transition error interrupt flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  *            @arg TIM_IT_IDX: Index interrupt
+  *            @arg TIM_IT_DIR: Direction change interrupt
+  *            @arg TIM_IT_IERR: Index error interrupt
+  *            @arg TIM_IT_TERR: Transition error interrupt
+  * @retval The state of TIM_IT (SET or RESET).
+  */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+                                                             == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  *            @arg TIM_IT_IDX: Index interrupt
+  *            @arg TIM_IT_DIR: Direction change interrupt
+  *            @arg TIM_IT_IERR: Index error interrupt
+  *            @arg TIM_IT_TERR: Transition error interrupt
+  * @retval None
+  */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+  *       in an atomic way.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Get update interrupt flag (UIF) copy status.
+  * @param  __COUNTER__ Counter value.
+  * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+  */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
+/**
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
+  * @param  __HANDLE__ TIM handle.
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
+  *       or Encoder mode.
+  */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+  * @brief  Set the TIM Prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __PRESC__ specifies the Prescaler new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+  * @brief  Set the TIM Counter Register value on runtime.
+  * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
+  *      case of 32 bits counter TIM instance.
+  *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __COUNTER__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+  * @brief  Get the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+  */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
+
+/**
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __AUTORELOAD__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+  do{                                                    \
+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Autoreload Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+  */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CKD__ specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  * @retval None
+  */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+  do{                                                   \
+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Clock Division value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval The clock division can be one of the following values:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
+  *         function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  do{                                                    \
+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Input Capture prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+  * @retval The input capture prescaler can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  __COMPARE__ specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+  * @brief  Get the TIM Capture Compare Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
+  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+  */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+   ((__HANDLE__)->Instance->CCR6))
+
+/**
+  * @brief  Set the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Reset the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Enable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is enabled an active edge on the trigger input acts
+  *        like a compare match on CCx output. Delay to sample the trigger
+  *        input and to activate CCx output is reduced to 3 clock cycles.
+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Disable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is disabled CCx output behaves normally depending
+  *        on counter and CCRx values even when the trigger is ON. The minimum
+  *        delay to activate CCx output when an active edge occurs on the
+  *        trigger input is 5 clock cycles.
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
+  *        overflow/underflow generates an update interrupt or DMA request (if
+  *        enabled)
+  * @retval None
+  */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
+  *        following events generate an update interrupt or DMA request (if
+  *        enabled):
+  *           _ Counter overflow underflow
+  *           _ Setting the UG bit
+  *           _ Update generation through the slave mode controller
+  * @retval None
+  */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+  * @brief  Set the TIM Capture x input polarity on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __POLARITY__ Polarity for TIx source
+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+  * @retval None
+  */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
+  do{                                                                     \
+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+  }while(0)
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+  * @{
+  */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE))
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+  * @{
+  */
+#if defined(COMP5) && defined(COMP6) && defined(COMP7)
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1)    || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2)    || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3)    || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4)    || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP5)    || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP6)    || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP7)    || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
+#else /* COMP5 && COMP6 && COMP7 */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1)    || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2)    || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3)    || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4)    || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
+#endif /* COMP5 && COMP6 && COMP7 */
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
+                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
+                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
+                                   ((__BASE__) == TIM_DMABASE_AF1)   || \
+                                   ((__BASE__) == TIM_DMABASE_AF2)   || \
+                                   ((__BASE__) == TIM_DMABASE_TISEL) || \
+                                   ((__BASE__) == TIM_DMABASE_DTR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_ECR)  || \
+                                   ((__BASE__) == TIM_DMABASE_OR))
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
+                                            ((__MODE__) == TIM_UIFREMAP_ENALE))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1)                      || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2)                      || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12)                     || \
+                                            ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2)    || \
+                                            ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1)    || \
+                                            ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2)      || \
+                                            ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_X1_TI1)                   || \
+                                            ((__MODE__) == TIM_ENCODERMODE_X1_TI2))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_4))
+
+#if defined(TIM5) && defined(TIM20)
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
+#elif defined(TIM5)
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
+#elif defined(TIM20)
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
+#else
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
+#endif /* TIM5 && TIM20 */
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
+                                         ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
+
+
+#define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
+                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
+                                          ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
+
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_ENCODER_CLK))
+
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
+                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)               || \
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)                 || \
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)                 || \
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)               || \
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)             || \
+                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \
+                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
+                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \
+                                   ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT)   || \
+                                   ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE))
+
+#if defined (TIM5) && defined(TIM20)
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR4) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR5) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR6) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR7) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR9) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR10)|| \
+                                                               ((__SELECTION__) == TIM_TS_ITR11)|| \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+#elif defined (TIM5)
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR4) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR5) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR6) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR7) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR10)|| \
+                                                               ((__SELECTION__) == TIM_TS_ITR11)|| \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+#elif defined (TIM20)
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR5) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR6) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR7) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR9) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR11)|| \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+#else
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR5) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR6) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR7) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR11)|| \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+#endif /* TIM5 && TIM20 */
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
+                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
+   (__HANDLE__)->ChannelState[5])
+
+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
+   ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
+                                                                       (__HANDLE__)->ChannelState[0]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[1]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[2]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[3]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[4]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[5]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                     } while(0)
+
+#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
+   (__HANDLE__)->ChannelNState[3])
+
+#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
+   ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
+                                                                         (__HANDLE__)->ChannelNState[0] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[1] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[2] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[3] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                       } while(0)
+
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32g4xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief   Time Base functions
+  * @{
+  */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief   TIM Output Compare functions
+  * @{
+  */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief   TIM PWM functions
+  * @{
+  */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief   TIM Input Capture functions
+  * @{
+  */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief   TIM One Pulse functions
+  * @{
+  */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief   TIM Encoder functions
+  * @{
+  */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief   IRQ handler management
+  * @{
+  */
+/* Interrupt Handler functions  ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief   Peripheral Control functions
+  * @{
+  */
+/* Control functions  *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+                                                   uint32_t BurstLength,  uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief   TIM Callbacks functions
+  * @{
+  */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief  Peripheral State functions
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+/* Peripheral Channel state functions  ************************************************/
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_TIM_H */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h
new file mode 100644
index 0000000..b40d85c
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h
@@ -0,0 +1,2138 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_TIM_EX_H
+#define STM32G4xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Hall sensor Configuration Structure definition
+  */
+
+typedef struct
+{
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+
+/**
+  * @brief  TIM Break/Break2 input configuration
+  */
+typedef struct
+{
+  uint32_t Source;         /*!< Specifies the source of the timer break input.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */
+} TIMEx_BreakInputConfigTypeDef;
+
+/**
+  * @brief  TIM Encoder index configuration
+  */
+typedef struct
+{
+  uint32_t Polarity;                  /*!< TIM Encoder index polarity.This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */
+
+  uint32_t Prescaler;                 /*!< TIM Encoder index prescaler.This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */
+
+  uint32_t Filter;                    /*!< TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  FunctionalState  FirstIndexEnable;  /*!< Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE. */
+
+  uint32_t Position;                  /*!< Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Position */
+
+  uint32_t Direction;                 /*!< Specifies in which counter direction the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */
+
+} TIMEx_EncoderIndexConfigTypeDef;
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+  * @{
+  */
+#define TIM_TIM1_ETR_GPIO        0x00000000U                                                 /* !< ETR input is connected to GPIO */
+#define TIM_TIM1_ETR_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< ETR input is connected to COMP1_OUT */
+#define TIM_TIM1_ETR_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< ETR input is connected to COMP2_OUT */
+#define TIM_TIM1_ETR_COMP3       (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to COMP3_OUT */
+#define TIM_TIM1_ETR_COMP4       TIM1_AF1_ETRSEL_2                                           /* !< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM1_ETR_COMP5       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM1_ETR_COMP6       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM1_ETR_COMP7       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM1_ETR_ADC1_AWD1   TIM1_AF1_ETRSEL_3                                           /* !< ADC1 analog watchdog 1 */
+#define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /* !< ADC1 analog watchdog 2 */
+#define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                     /* !< ADC1 analog watchdog 3 */
+#if defined (ADC4)
+#define TIM_TIM1_ETR_ADC4_AWD1   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC4 analog watchdog 1 */
+#define TIM_TIM1_ETR_ADC4_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                     /* !< ADC4 analog watchdog 2 */
+#define TIM_TIM1_ETR_ADC4_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC4 analog watchdog 3 */
+#endif /* ADC4 */
+
+#define TIM_TIM2_ETR_GPIO         0x00000000U                                                /* !< ETR input is connected to GPIO */
+#define TIM_TIM2_ETR_COMP1        TIM1_AF1_ETRSEL_0                                          /* !< ETR input is connected to COMP1_OUT */
+#define TIM_TIM2_ETR_COMP2        TIM1_AF1_ETRSEL_1                                          /* !< ETR input is connected to COMP2_OUT */
+#define TIM_TIM2_ETR_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                    /* !< ETR input is connected to COMP3_OUT */
+#define TIM_TIM2_ETR_COMP4        TIM1_AF1_ETRSEL_2                                          /* !< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM2_ETR_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                    /* !< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM2_ETR_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                    /* !< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM2_ETR_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)/* !< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM2_ETR_TIM3_ETR     TIM1_AF1_ETRSEL_3                                          /* !< ETR input is connected to TIM3 ETR */
+#define TIM_TIM2_ETR_TIM4_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                    /* !< ETR input is connected to TIM4 ETR */
+#if defined (TIM5)
+#define TIM_TIM2_ETR_TIM5_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                    /* !< ETR input is connected to TIM5 ETR */
+#endif /* TIM5 */
+#define TIM_TIM2_ETR_LSE          (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to LSE */
+
+#define TIM_TIM3_ETR_GPIO         0x00000000U                                                 /* !< ETR input is connected to GPIO */
+#define TIM_TIM3_ETR_COMP1        TIM1_AF1_ETRSEL_0                                           /* !< ETR input is connected to COMP1_OUT */
+#define TIM_TIM3_ETR_COMP2        TIM1_AF1_ETRSEL_1                                           /* !< ETR input is connected to COMP2_OUT */
+#define TIM_TIM3_ETR_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to COMP3_OUT */
+#define TIM_TIM3_ETR_COMP4        TIM1_AF1_ETRSEL_2                                           /* !< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM3_ETR_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM3_ETR_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM3_ETR_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM3_ETR_TIM2_ETR     TIM1_AF1_ETRSEL_3                                           /* !< ETR input is connected to TIM2 ETR */
+#define TIM_TIM3_ETR_TIM4_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to TIM4 ETR */
+#define TIM_TIM3_ETR_ADC2_AWD1    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 1 */
+#define TIM_TIM3_ETR_ADC2_AWD2    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                     /* !< ADC2 analog watchdog 2 */
+#define TIM_TIM3_ETR_ADC2_AWD3    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 3 */
+
+#define TIM_TIM4_ETR_GPIO         0x00000000U                                                 /* !< ETR input is connected to GPIO */
+#define TIM_TIM4_ETR_COMP1        TIM1_AF1_ETRSEL_0                                           /* !< ETR input is connected to COMP1_OUT */
+#define TIM_TIM4_ETR_COMP2        TIM1_AF1_ETRSEL_1                                           /* !< ETR input is connected to COMP2_OUT */
+#define TIM_TIM4_ETR_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to COMP3_OUT */
+#define TIM_TIM4_ETR_COMP4        TIM1_AF1_ETRSEL_2                                           /* !< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM4_ETR_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM4_ETR_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM4_ETR_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM4_ETR_TIM3_ETR     TIM1_AF1_ETRSEL_3                                           /* !< ETR input is connected to TIM3 ETR */
+#if defined (TIM5)
+#define TIM_TIM4_ETR_TIM5_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to TIM5 ETR */
+#endif /* TIM5 */
+
+#if defined (TIM5)
+#define TIM_TIM5_ETR_GPIO         0x00000000U                                                 /* !< ETR input is connected to GPIO */
+#define TIM_TIM5_ETR_COMP1        TIM1_AF1_ETRSEL_0                                           /* !< ETR input is connected to COMP1_OUT */
+#define TIM_TIM5_ETR_COMP2        TIM1_AF1_ETRSEL_1                                           /* !< ETR input is connected to COMP2_OUT */
+#define TIM_TIM5_ETR_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to COMP3_OUT */
+#define TIM_TIM5_ETR_COMP4        TIM1_AF1_ETRSEL_2                                           /* !< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM5_ETR_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM5_ETR_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM5_ETR_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM5_ETR_TIM2_ETR     TIM1_AF1_ETRSEL_3                                           /* !< ETR input is connected to TIM2 ETR */
+#define TIM_TIM5_ETR_TIM3_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to TIM3 ETR */
+#endif /* TIM5 */
+
+#define TIM_TIM8_ETR_GPIO        0x00000000U                                                  /* !< ETR input is connected to GPIO */
+#define TIM_TIM8_ETR_COMP1       TIM1_AF1_ETRSEL_0                                            /* !< ETR input is connected to COMP1_OUT */
+#define TIM_TIM8_ETR_COMP2       TIM1_AF1_ETRSEL_1                                            /* !< ETR input is connected to COMP2_OUT */
+#define TIM_TIM8_ETR_COMP3       (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                      /* !< ETR input is connected to COMP3_OUT */
+#define TIM_TIM8_ETR_COMP4       TIM1_AF1_ETRSEL_2                                            /* !< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM8_ETR_COMP5       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                      /* !< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM8_ETR_COMP6       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                      /* !< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM8_ETR_COMP7       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /* !< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM8_ETR_ADC2_AWD1   TIM1_AF1_ETRSEL_3                                            /* !< ADC2 analog watchdog 1 */
+#define TIM_TIM8_ETR_ADC2_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                      /* !< ADC2 analog watchdog 2 */
+#define TIM_TIM8_ETR_ADC2_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                      /* !< ADC2 analog watchdog 3 */
+#if defined (ADC3)
+#define TIM_TIM8_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /* !< ADC3 analog watchdog 1 */
+#define TIM_TIM8_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                      /* !< ADC3 analog watchdog 2 */
+#define TIM_TIM8_ETR_ADC3_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)  /* !< ADC3 analog watchdog 3 */
+#endif /* ADC3 */
+
+#if defined (TIM20)
+#define TIM_TIM20_ETR_GPIO       0x00000000U                                                 /* !< ETR input is connected to GPIO */
+#define TIM_TIM20_ETR_COMP1      TIM1_AF1_ETRSEL_0                                           /* !< ETR input is connected to COMP1_OUT */
+#define TIM_TIM20_ETR_COMP2      TIM1_AF1_ETRSEL_1                                           /* !< ETR input is connected to COMP2_OUT */
+#define TIM_TIM20_ETR_COMP3      (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to COMP3_OUT */
+#define TIM_TIM20_ETR_COMP4      TIM1_AF1_ETRSEL_2                                           /* !< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM20_ETR_COMP5      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM20_ETR_COMP6      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM20_ETR_COMP7      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define TIM_TIM20_ETR_ADC3_AWD1  TIM1_AF1_ETRSEL_3                                           /* !< ADC3 analog watchdog 1 */
+#define TIM_TIM20_ETR_ADC3_AWD2  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /* !< ADC3 analog watchdog 2 */
+#define TIM_TIM20_ETR_ADC3_AWD3  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                     /* !< ADC3 analog watchdog 3 */
+#if defined (ADC5)
+#define TIM_TIM20_ETR_ADC5_AWD1  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 1 */
+#define TIM_TIM20_ETR_ADC5_AWD2  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                     /* !< ADC5 analog watchdog 2 */
+#define TIM_TIM20_ETR_ADC5_AWD3  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 3 */
+#endif /* ADC5 */
+#endif /* TIM20 */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input TIM Extended Break input
+  * @{
+  */
+#define TIM_BREAKINPUT_BRK     0x00000001U                                      /*!< Timer break input  */
+#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /*!< Timer break2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */
+#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP3    0x00000008U                               /* !< The COMP3 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP4    0x00000010U                               /* !< The COMP4 output is connected to the break input */
+#if defined(COMP5)
+#define TIM_BREAKINPUTSOURCE_COMP5    0x00000020U                               /* !< The COMP5 output is connected to the break input */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_BREAKINPUTSOURCE_COMP6    0x00000040U                               /* !< The COMP6 output is connected to the break input */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_BREAKINPUTSOURCE_COMP7    0x00000080U                               /* !< The COMP7 output is connected to the break input */
+#endif /* COMP7 */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /*!< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /*!< Break input source is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /*!< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /*!< Break input source is active_high */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
+  * @{
+  */
+#define TIM_TIM1_TI1_GPIO   0x00000000U                                       /*!< TIM1 input 1 is connected to GPIO */
+#define TIM_TIM1_TI1_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM1 input 1 is connected to COMP1_OUT */
+#define TIM_TIM1_TI1_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM1 input 1 is connected to COMP2_OUT */
+#define TIM_TIM1_TI1_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM1 input 1 is connected to COMP3_OUT */
+#define TIM_TIM1_TI1_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM1 input 1 is connected to COMP4_OUT */
+
+
+#define TIM_TIM2_TI1_GPIO   0x00000000U                                       /*!< TIM2 input 1 is connected to GPIO */
+#define TIM_TIM2_TI1_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM2 input 1 is connected to COMP1_OUT */
+#define TIM_TIM2_TI1_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM2 input 1 is connected to COMP2_OUT */
+#define TIM_TIM2_TI1_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM2 input 1 is connected to COMP3_OUT */
+#define TIM_TIM2_TI1_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM2 input 1 is connected to COMP4_OUT */
+#if defined (COMP5)
+#define TIM_TIM2_TI1_COMP5  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM2 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+
+#define TIM_TIM2_TI2_GPIO   0x00000000U                                       /*!< TIM2 input 2 is connected to GPIO */
+#define TIM_TIM2_TI2_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM2 input 2 is connected to COMP1_OUT */
+#define TIM_TIM2_TI2_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM2 input 2 is connected to COMP2_OUT */
+#define TIM_TIM2_TI2_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM2 input 2 is connected to COMP3_OUT */
+#define TIM_TIM2_TI2_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM2 input 2 is connected to COMP4_OUT */
+#if defined (COMP6)
+#define TIM_TIM2_TI2_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM2 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+
+#define TIM_TIM2_TI3_GPIO   0x00000000U                                       /*!< TIM2 input 3 is connected to GPIO */
+#define TIM_TIM2_TI3_COMP4  TIM_TISEL_TI3SEL_0                                /*!< TIM2 input 3 is connected to COMP4_OUT */
+
+#define TIM_TIM2_TI4_GPIO   0x00000000U                                       /*!< TIM2 input 4 is connected to GPIO */
+#define TIM_TIM2_TI4_COMP1  TIM_TISEL_TI4SEL_0                                /*!< TIM2 input 4 is connected to COMP1_OUT */
+#define TIM_TIM2_TI4_COMP2  TIM_TISEL_TI4SEL_1                                /*!< TIM2 input 4 is connected to COMP2_OUT */
+
+
+#define TIM_TIM3_TI1_GPIO   0x00000000U                                       /*!< TIM3 input 1 is connected to GPIO */
+#define TIM_TIM3_TI1_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM3 input 1 is connected to COMP1_OUT */
+#define TIM_TIM3_TI1_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM3 input 1 is connected to COMP2_OUT */
+#define TIM_TIM3_TI1_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM3 input 1 is connected to COMP3_OUT */
+#define TIM_TIM3_TI1_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM3 input 1 is connected to COMP4_OUT */
+#if defined (COMP5)
+#define TIM_TIM3_TI1_COMP5  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM3 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined (COMP6)
+#define TIM_TIM3_TI1_COMP6  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)         /*!< TIM3 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined (COMP7)
+#define TIM_TIM3_TI1_COMP7  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)   /*!< TIM3 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM3_TI2_GPIO   0x00000000U                                       /*!< TIM3 input 2 is connected to GPIO */
+#define TIM_TIM3_TI2_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM3 input 2 is connected to COMP1_OUT */
+#define TIM_TIM3_TI2_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM3 input 2 is connected to COMP2_OUT */
+#define TIM_TIM3_TI2_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM3 input 2 is connected to COMP3_OUT */
+#define TIM_TIM3_TI2_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM3 input 2 is connected to COMP4_OUT */
+#if defined (COMP5)
+#define TIM_TIM3_TI2_COMP5  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM3 input 2 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined (COMP6)
+#define TIM_TIM3_TI2_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1)         /*!< TIM3 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined (COMP7)
+#define TIM_TIM3_TI2_COMP7  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)   /*!< TIM3 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM3_TI3_GPIO   0x00000000U                                       /*!< TIM3 input 3 is connected to GPIO */
+#define TIM_TIM3_TI3_COMP3  TIM_TISEL_TI3SEL_0                                /*!< TIM3 input 3 is connected to COMP3_OUT */
+
+
+#define TIM_TIM4_TI1_GPIO   0x00000000U                                       /*!< TIM4 input 1 is connected to GPIO */
+#define TIM_TIM4_TI1_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM4 input 1 is connected to COMP1_OUT */
+#define TIM_TIM4_TI1_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM4 input 1 is connected to COMP2_OUT */
+#define TIM_TIM4_TI1_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM4 input 1 is connected to COMP3_OUT */
+#define TIM_TIM4_TI1_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM4 input 1 is connected to COMP4_OUT */
+#if defined (COMP5)
+#define TIM_TIM4_TI1_COMP5  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM4 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined (COMP6)
+#define TIM_TIM4_TI1_COMP6  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)         /*!< TIM4 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined (COMP7)
+#define TIM_TIM4_TI1_COMP7  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)   /*!< TIM4 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM4_TI2_GPIO   0x00000000U                                       /*!< TIM4 input 2 is connected to GPIO */
+#define TIM_TIM4_TI2_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM4 input 2 is connected to COMP1_OUT */
+#define TIM_TIM4_TI2_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM4 input 2 is connected to COMP2_OUT */
+#define TIM_TIM4_TI2_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM4 input 2 is connected to COMP3_OUT */
+#define TIM_TIM4_TI2_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM4 input 2 is connected to COMP4_OUT */
+#if defined (COMP5)
+#define TIM_TIM4_TI2_COMP5  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM4 input 2 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined (COMP6)
+#define TIM_TIM4_TI2_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1)         /*!< TIM4 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined (COMP7)
+#define TIM_TIM4_TI2_COMP7  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)   /*!< TIM4 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM4_TI3_GPIO   0x00000000U                                       /*!< TIM4 input 3 is connected to GPIO */
+#if defined (COMP5)
+#define TIM_TIM4_TI3_COMP5  TIM_TISEL_TI3SEL_0                                /*!< TIM4 input 3 is connected to COMP5_OUT */
+#endif /* COMP5 */
+
+#define TIM_TIM4_TI4_GPIO   0x00000000U                                       /*!< TIM4 input 4 is connected to GPIO */
+#if defined (COMP6)
+#define TIM_TIM4_TI4_COMP6  TIM_TISEL_TI4SEL_0                                /*!< TIM4 input 4 is connected to COMP6_OUT */
+#endif /* COMP6 */
+
+
+#if defined(TIM5)
+#define TIM_TIM5_TI1_GPIO   0x00000000U                                       /*!< TIM5 input 1 is connected to GPIO */
+#define TIM_TIM5_TI1_LSI    TIM_TISEL_TI1SEL_0                                /*!< TIM5 input 1 is connected to LSI */
+#define TIM_TIM5_TI1_LSE    TIM_TISEL_TI1SEL_1                                /*!< TIM5 input 1 is connected to LSE */
+#define TIM_TIM5_TI1_RTC_WK (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM5 input 1 is connected to RTC_WAKEUP */
+#define TIM_TIM5_TI1_COMP1  TIM_TISEL_TI1SEL_2                                /*!< TIM5 input 1 is connected to COMP1_OUT */
+#define TIM_TIM5_TI1_COMP2  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM5 input 1 is connected to COMP2_OUT */
+#define TIM_TIM5_TI1_COMP3  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)         /*!< TIM5 input 1 is connected to COMP3_OUT */
+#define TIM_TIM5_TI1_COMP4  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)   /*!< TIM5 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM5_TI1_COMP5  TIM_TISEL_TI1SEL_3                                /*!< TIM5 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM5_TI1_COMP6  (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0)         /*!< TIM5 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM5_TI1_COMP7  (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1)         /*!< TIM5 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM5_TI2_GPIO   0x00000000U                                       /*!< TIM5 input 2 is connected to GPIO */
+#define TIM_TIM5_TI2_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM5 input 2 is connected to COMP1_OUT */
+#define TIM_TIM5_TI2_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM5 input 2 is connected to COMP2_OUT */
+#define TIM_TIM5_TI2_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM5 input 2 is connected to COMP3_OUT */
+#define TIM_TIM5_TI2_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM5 input 2 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define TIM_TIM5_TI2_COMP5  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM5 input 2 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define TIM_TIM5_TI2_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1)         /*!< TIM5 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM5_TI2_COMP7  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)   /*!< TIM5 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+#endif /* TIM5 */
+
+
+#define TIM_TIM8_TI1_GPIO   0x00000000U                                       /*!< TIM8 input 1 is connected to GPIO */
+#define TIM_TIM8_TI1_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM8 input 1 is connected to COMP1_OUT */
+#define TIM_TIM8_TI1_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM8 input 1 is connected to COMP2_OUT */
+#define TIM_TIM8_TI1_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM8 input 1 is connected to COMP3_OUT */
+#define TIM_TIM8_TI1_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM8 input 1 is connected to COMP4_OUT */
+
+
+#define TIM_TIM15_TI1_GPIO  0x00000000U                                       /*!< TIM15 input 1 is connected to GPIO */
+#define TIM_TIM15_TI1_LSE   TIM_TISEL_TI1SEL_0                                /*!< TIM15 input 1 is connected to LSE */
+#define TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_1                                /*!< TIM15 input 1 is connected to COMP1_OUT */
+#define TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM15 input 1 is connected to COMP2_OUT */
+#if defined (COMP5)
+#define TIM_TIM15_TI1_COMP5 TIM_TISEL_TI1SEL_2                                /*!< TIM15 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP7)
+#define TIM_TIM15_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM15 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+#define TIM_TIM15_TI2_GPIO  0x00000000U                                       /*!< TIM15 input 2 is connected to GPIO */
+#define TIM_TIM15_TI2_COMP2 TIM_TISEL_TI2SEL_0                                /*!< TIM15 input 2 is connected to COMP2_OUT */
+#define TIM_TIM15_TI2_COMP3 TIM_TISEL_TI2SEL_1                                /*!< TIM15 input 2 is connected to COMP3_OUT */
+#if defined (COMP6)
+#define TIM_TIM15_TI2_COMP6 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM15 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define TIM_TIM15_TI2_COMP7 TIM_TISEL_TI2SEL_2                                /*!< TIM15 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+
+
+#define TIM_TIM16_TI1_GPIO    0x00000000U                                     /*!< TIM16 input 1 is connected to GPIO */
+#if defined (COMP6)
+#define TIM_TIM16_TI1_COMP6   TIM_TISEL_TI1SEL_0                              /*!< TIM16 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#define TIM_TIM16_TI1_MCO     TIM_TISEL_TI1SEL_1                              /*!< TIM16 input 1 is connected to MCO */
+#define TIM_TIM16_TI1_HSE_32  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)       /*!< TIM16 input 1 is connected to HSE/32 */
+#define TIM_TIM16_TI1_RTC_WK  TIM_TISEL_TI1SEL_2                              /*!< TIM16 input 1 is connected to RTC_WAKEUP */
+#define TIM_TIM16_TI1_LSE     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)       /*!< TIM16 input 1 is connected to LSE */
+#define TIM_TIM16_TI1_LSI     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)       /*!< TIM16 input 1 is connected to LSI */
+
+
+#define TIM_TIM17_TI1_GPIO    0x00000000U                                     /*!< TIM17 input 1 is connected to GPIO */
+#if defined (COMP5)
+#define TIM_TIM17_TI1_COMP5   TIM_TISEL_TI1SEL_0                              /*!< TIM17 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#define TIM_TIM17_TI1_MCO     TIM_TISEL_TI1SEL_1                              /*!< TIM17 input 1 is connected to MCO */
+#define TIM_TIM17_TI1_HSE_32  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)       /*!< TIM17 input 1 is connected to HSE/32 */
+#define TIM_TIM17_TI1_RTC_WK  TIM_TISEL_TI1SEL_2                              /*!< TIM17 input 1 is connected to RTC_WAKEUP */
+#define TIM_TIM17_TI1_LSE     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)       /*!< TIM17 input 1 is connected to LSE */
+#define TIM_TIM17_TI1_LSI     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)       /*!< TIM17 input 1 is connected to LSI */
+
+
+#if defined (TIM20)
+#define TIM_TIM20_TI1_GPIO  0x00000000U                                      /*!< TIM20 input 1 is connected to GPIO */
+#define TIM_TIM20_TI1_COMP1 TIM_TISEL_TI1SEL_0                               /*!< TIM20 input 1 is connected to COMP1_OUT */
+#define TIM_TIM20_TI1_COMP2 TIM_TISEL_TI1SEL_1                               /*!< TIM20 input 1 is connected to COMP2_OUT */
+#define TIM_TIM20_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)        /*!< TIM20 input 1 is connected to COMP3_OUT */
+#define TIM_TIM20_TI1_COMP4 TIM_TISEL_TI1SEL_2                               /*!< TIM20 input 1 is connected to COMP4_OUT */
+#endif /* TIM20 */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload enabling
+  * @{
+  */
+#define TIM_SMS_PRELOAD_SOURCE_UPDATE     0x00000000U                            /*!< Prelaod of SMS bitfield is disabled */
+#define TIM_SMS_PRELOAD_SOURCE_INDEX      TIM_SMCR_SMSPS                         /*!< Preload of SMS bitfield is enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position
+  * @{
+  */
+#define TIM_ENCODERINDEX_POSITION_00        0x00000000U                           /*!< Encoder index position is AB=00 */
+#define TIM_ENCODERINDEX_POSITION_01        TIM_ECR_IPOS_0                        /*!< Encoder index position is AB=01 */
+#define TIM_ENCODERINDEX_POSITION_10        TIM_ECR_IPOS_1                        /*!< Encoder index position is AB=10 */
+#define TIM_ENCODERINDEX_POSITION_11        (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)     /*!< Encoder index position is AB=11 */
+#define TIM_ENCODERINDEX_POSITION_0         0x00000000U                           /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 0 */
+#define TIM_ENCODERINDEX_POSITION_1         TIM_ECR_IPOS_0                        /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction
+  * @{
+  */
+#define TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U        /*!< Index resets the counter whatever the direction  */
+#define TIM_ENCODERINDEX_DIRECTION_UP      TIM_ECR_IDIR_0     /*!< Index resets the counter when up-counting only   */
+#define TIM_ENCODERINDEX_DIRECTION_DOWN    TIM_ECR_IDIR_1     /*!< Index resets the counter when down-counting only */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity
+  * @{
+  */
+#define TIM_ENCODERINDEX_POLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_ENCODERINDEX_POLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index prescaler
+  * @{
+  */
+#define TIM_ENCODERINDEX_PRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_ENCODERINDEX_PRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_ENCODERINDEX_PRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_ENCODERINDEX_PRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note   ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+  ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note   ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \
+  (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+  *         output signal frequency.
+  * @note   ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000);
+  * @note   This macro should be used only if dithering is already enabled
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65519)
+  */
+#define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
+  (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
+  (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
+  *         active/inactive delay.
+  * @note   ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
+  *         output compare active/inactive delay.
+  * @note   ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10);
+  * @note   This macro should be used only if dithering is already enabled
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65519)
+  */
+#define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+  *        (when the timer operates in one pulse mode).
+  * @note   ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+  *         pulse duration (when the timer operates in one pulse mode).
+  * @note   ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20);
+  * @note   This macro should be used only if dithering is already enabled
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65519)
+  */
+#define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
+
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
+                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#if defined (COMP5) && defined (COMP6) && defined (COMP7)
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP5) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP6) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP7))
+
+
+#else
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4))
+
+#endif /* COMP5 && COMP6 && COMP7 */
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
+                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
+                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+
+#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
+
+#define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \
+  (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5))
+
+#if defined(TIM5) && defined(TIM20)
+#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))            \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)))            \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))            \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))            \
+   ||                                        \
+   (((INSTANCE) == TIM5) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))            \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))            \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))            \
+   ||                                        \
+   (((INSTANCE) == TIM20) &&                 \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))))
+
+#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)))             \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)))             \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)))             \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)))             \
+   ||                                        \
+   (((INSTANCE) == TIM5) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)))             \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)))             \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)))             \
+   ||                                        \
+   (((INSTANCE) == TIM20) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10))))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)||          \
+     ((__SELECTION__) == TIM_TS_ITR11)||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM5) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM20) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)||          \
+     ((__SELECTION__) == TIM_TS_NONE))))
+
+#elif defined(TIM5)
+#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)))            \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
+   ||                                        \
+   (((INSTANCE) == TIM5) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
+
+#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)))             \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)))             \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)))             \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)))             \
+   ||                                        \
+   (((INSTANCE) == TIM5) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)))             \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)))             \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8))))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM5) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR4) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_NONE))))
+#elif defined(TIM20)
+#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)))            \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)))            \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)))            \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)))            \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)))            \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)))            \
+   ||                                        \
+   (((INSTANCE) == TIM20) &&                 \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
+
+#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)))             \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)))             \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)))             \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)))             \
+   ||                                       \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)))             \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)))             \
+   ||                                        \
+   (((INSTANCE) == TIM20) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8))))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR9) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM20) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_NONE))))
+#else
+#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)))            \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
+
+#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR1)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||       \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||       \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||       \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||       \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR8)))          \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||       \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||       \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||       \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||       \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR11)))          \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||       \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||       \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||       \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||       \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR8)))          \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||       \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||       \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||       \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||       \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR8)))          \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||       \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||       \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||       \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||       \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR8)))          \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||       \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||       \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||       \
+     ((__SELECTION__) == TIM_TS_TI2FP2)  ||       \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||       \
+     ((__SELECTION__) == TIM_TS_ITR8))))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR6) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0) ||          \
+     ((__SELECTION__) == TIM_TS_ITR1) ||          \
+     ((__SELECTION__) == TIM_TS_ITR2) ||          \
+     ((__SELECTION__) == TIM_TS_ITR3) ||          \
+     ((__SELECTION__) == TIM_TS_ITR5) ||          \
+     ((__SELECTION__) == TIM_TS_ITR7) ||          \
+     ((__SELECTION__) == TIM_TS_ITR8) ||          \
+     ((__SELECTION__) == TIM_TS_NONE))))
+
+#endif /* TIM5 && TIM20 */
+#define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__)   \
+  (IS_TIM_OC_MODE(__MODE__) \
+   && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \
+       ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1 == 1)))
+
+#define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_3) ||    \
+   ((__CHANNEL__) == TIM_CHANNEL_4))
+
+#define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE)  IS_TIM_CC3_INSTANCE(INSTANCE)
+
+#define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__)    ((__WIDTH__) <= 0xFFU)
+
+#define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__)    ((__PRESCALER__) <= 0x7U)
+
+#define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__)    (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) \
+                                                    || ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX))
+
+#define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__)        (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED)  || \
+                                                           ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED))
+
+#define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \
+                                                           ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \
+                                                           ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \
+                                                           ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8))
+
+#define IS_TIM_ENCODERINDEX_FILTER(__FILTER__)            ((__FILTER__) <= 0xFUL)
+
+#define IS_TIM_ENCODERINDEX_POSITION(__POSITION__)        (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \
+                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \
+                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \
+                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \
+                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0)  || \
+                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1))
+
+#define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__)      (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \
+                                                           ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP)      || \
+                                                           ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN))
+
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  *  @brief    Timer Hall Sensor functions
+  * @{
+  */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  * @{
+  */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  *  @brief    Timer Complementary PWM functions
+  * @{
+  */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  *  @brief    Timer Complementary One Pulse functions
+  * @{
+  */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
+
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler,
+                                                    uint32_t PulseWidth);
+HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source);
+HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime);
+HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime);
+HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
+                                               TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig);
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  * @{
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  * @{
+  */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
+  * @{
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32G4xx_HAL_TIM_EX_H */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h
new file mode 100644
index 0000000..0df466b
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h
@@ -0,0 +1,1723 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_uart.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_UART_H
+#define STM32G4xx_HAL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+  * @{
+  */
+
+/**
+  * @brief UART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                /*!< This member configures the UART communication baud rate.
+                                         The baud rate register is computed using the following formula:
+                                         LPUART:
+                                         =======
+                                         Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
+                                         where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
+                                         UART:
+                                         =====
+                                         - If oversampling is 16 or in LIN mode,
+                                            Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
+                                         - If oversampling is 8,
+                                            Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
+                                            ((huart->Init.BaudRate)))[15:4]
+                                            Baud Rate Register[3] =  0
+                                            Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) /
+                                            ((huart->Init.BaudRate)))[3:0]) >> 1
+                                         where uart_ker_ck_pres is the UART input clock divided by a prescaler */
+
+  uint32_t WordLength;              /*!< Specifies the number of data bits transmitted or received in a frame.
+                                         This parameter can be a value of @ref UARTEx_Word_Length. */
+
+  uint32_t StopBits;                /*!< Specifies the number of stop bits transmitted.
+                                         This parameter can be a value of @ref UART_Stop_Bits. */
+
+  uint32_t Parity;                  /*!< Specifies the parity mode.
+                                         This parameter can be a value of @ref UART_Parity
+                                         @note When parity is enabled, the computed parity is inserted
+                                               at the MSB position of the transmitted data (9th bit when
+                                               the word length is set to 9 data bits; 8th bit when the
+                                               word length is set to 8 data bits). */
+
+  uint32_t Mode;                    /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                         This parameter can be a value of @ref UART_Mode. */
+
+  uint32_t HwFlowCtl;               /*!< Specifies whether the hardware flow control mode is enabled
+                                         or disabled.
+                                         This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+
+  uint32_t OverSampling;            /*!< Specifies whether the Over sampling 8 is enabled or disabled,
+                                         to achieve higher speed (up to f_PCLK/8).
+                                         This parameter can be a value of @ref UART_Over_Sampling. */
+
+  uint32_t OneBitSampling;          /*!< Specifies whether a single sample or three samples' majority vote is selected.
+                                         Selecting the single sample method increases the receiver tolerance to clock
+                                         deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+
+  uint32_t ClockPrescaler;          /*!< Specifies the prescaler value used to divide the UART clock source.
+                                         This parameter can be a value of @ref UART_ClockPrescaler. */
+
+} UART_InitTypeDef;
+
+/**
+  * @brief  UART Advanced Features initialization structure definition
+  */
+typedef struct
+{
+  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
+                                       Advanced Features may be initialized at the same time .
+                                       This parameter can be a value of
+                                       @ref UART_Advanced_Features_Initialization_Type. */
+
+  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Tx_Inv. */
+
+  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Rx_Inv. */
+
+  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
+                                       vs negative/inverted logic).
+                                       This parameter can be a value of @ref UART_Data_Inv. */
+
+  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
+                                       This parameter can be a value of @ref UART_Rx_Tx_Swap. */
+
+  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
+                                       This parameter can be a value of @ref UART_Overrun_Disable. */
+
+  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
+                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
+
+  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
+                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
+
+  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
+                                       detection is carried out.
+                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
+
+  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
+                                       This parameter can be a value of @ref UART_MSB_First. */
+} UART_AdvFeatureInitTypeDef;
+
+/**
+  * @brief HAL UART State definition
+  * @note  HAL UART State value is a combination of 2 different substates:
+  *        gState and RxState (see @ref UART_State_Definition).
+  *        - gState contains UART state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized. HAL UART Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef uint32_t HAL_UART_StateTypeDef;
+
+/**
+  * @brief UART clock sources definition
+  */
+typedef enum
+{
+  UART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */
+  UART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */
+  UART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */
+  UART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */
+  UART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
+  UART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
+} UART_ClockSourceTypeDef;
+
+/**
+  * @brief HAL UART Reception type definition
+  * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.
+  *        It is expected to admit following values :
+  *           HAL_UART_RECEPTION_STANDARD         = 0x00U,
+  *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,
+  *           HAL_UART_RECEPTION_TORTO            = 0x02U,
+  *           HAL_UART_RECEPTION_TOCHARMATCH      = 0x03U,
+  */
+typedef uint32_t HAL_UART_RxTypeTypeDef;
+
+/**
+  * @brief  UART handle Structure definition
+  */
+typedef struct __UART_HandleTypeDef
+{
+  USART_TypeDef            *Instance;                /*!< UART registers base address        */
+
+  UART_InitTypeDef         Init;                     /*!< UART communication parameters      */
+
+  UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */
+
+  const uint8_t            *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
+
+  uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */
+
+  __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */
+
+  uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */
+
+  uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */
+
+  __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */
+
+  uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */
+
+  uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.
+                                                          This parameter can be a value of @ref UARTEx_FIFO_mode. */
+
+  uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */
+
+  uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */
+
+  __IO HAL_UART_RxTypeTypeDef ReceptionType;         /*!< Type of ongoing reception          */
+
+  void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
+
+  void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+
+  DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef           Lock;                    /*!< Locking object                     */
+
+  __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management
+                                                          and also related to Tx operations. This parameter
+                                                          can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations. This
+                                                          parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
+  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
+  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
+  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
+  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
+  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
+  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
+  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
+  void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */
+  void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */
+  void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback     */
+
+  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
+  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
+#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL UART Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
+  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
+  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
+  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
+  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
+  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
+  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
+  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
+  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
+  HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */
+  HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */
+
+  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
+  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL UART Callback pointer definition
+  */
+typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef  void (*pUART_RxEventCallbackTypeDef)
+(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+  * @{
+  */
+
+/** @defgroup UART_State_Definition UART State Code Definition
+  * @{
+  */
+#define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized
+                                                          Value is allowed for gState and RxState */
+#define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use
+                                                          Value is allowed for gState and RxState */
+#define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing
+                                                          Value is allowed for RxState only */
+#define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing
+                                                          Not to be used for neither gState nor RxState.Value is result
+                                                          of combination (Or) between gState and RxState values */
+#define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error
+                                                          Value is allowed for gState only */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Error_Definition   UART Error Definition
+  * @{
+  */
+#define  HAL_UART_ERROR_NONE             (0x00000000U)    /*!< No error                */
+#define  HAL_UART_ERROR_PE               (0x00000001U)    /*!< Parity error            */
+#define  HAL_UART_ERROR_NE               (0x00000002U)    /*!< Noise error             */
+#define  HAL_UART_ERROR_FE               (0x00000004U)    /*!< Frame error             */
+#define  HAL_UART_ERROR_ORE              (0x00000008U)    /*!< Overrun error           */
+#define  HAL_UART_ERROR_DMA              (0x00000010U)    /*!< DMA transfer error      */
+#define  HAL_UART_ERROR_RTO              (0x00000020U)    /*!< Receiver Timeout error  */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define  HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
+  * @{
+  */
+#define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
+#define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */
+#define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Parity  UART Parity
+  * @{
+  */
+#define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */
+#define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */
+#define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+  * @{
+  */
+#define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */
+#define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */
+#define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */
+#define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mode UART Transfer Mode
+  * @{
+  */
+#define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */
+#define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */
+#define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup UART_State  UART State
+  * @{
+  */
+#define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */
+#define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+  * @{
+  */
+#define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+  * @{
+  */
+#define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_ClockPrescaler  UART Clock Prescaler
+  * @{
+  */
+#define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
+#define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
+#define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
+#define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
+#define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
+#define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
+#define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
+#define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
+#define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
+#define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
+#define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
+#define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection
+                                                                              on start bit              */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection
+                                                                              on falling edge           */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection
+                                                                              on 0x7F frame detection   */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection
+                                                                              on 0x55 frame detection   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
+  * @{
+  */
+#define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN    UART Local Interconnection Network mode
+  * @{
+  */
+#define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
+  * @{
+  */
+#define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Tx    UART DMA Tx
+  * @{
+  */
+#define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Rx   UART DMA Rx
+  * @{
+  */
+#define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
+  * @{
+  */
+#define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
+  * @{
+  */
+#define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */
+#define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Request_Parameters UART Request Parameters
+  * @{
+  */
+#define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
+#define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */
+#define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */
+#define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
+#define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
+  * @{
+  */
+#define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */
+#define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */
+#define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */
+#define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */
+#define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */
+#define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+  * @{
+  */
+#define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
+  * @{
+  */
+#define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */
+#define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
+  * @{
+  */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */
+/**
+  * @}
+  */
+
+/** @defgroup UART_MSB_First   UART Advanced Feature MSB First
+  * @{
+  */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received
+                                                                         first disable                      */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received
+                                                                         first enable                       */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
+  * @{
+  */
+#define UART_CR2_ADDRESS_LSB_POS             24U             /*!< UART address-matching LSB position in CR2 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
+  * @{
+  */
+#define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                     */
+#define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                   */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register
+                                                                         not empty or RXFIFO is not empty            */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
+  * @{
+  */
+#define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB
+                                                          position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB
+                                                          position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
+  * @{
+  */
+#define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */
+/**
+  * @}
+  */
+
+/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
+  * @{
+  */
+#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Flags     UART Status Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */
+#define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */
+#define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */
+#define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */
+#define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */
+#define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */
+#define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */
+#define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */
+#define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */
+#define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */
+#define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */
+#define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */
+#define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */
+#define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */
+#define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */
+#define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */
+#define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */
+#define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */
+#define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */
+#define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */
+#define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */
+#define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */
+#define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */
+#define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */
+#define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */
+#define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interrupt_definition   UART Interrupts Definition
+  *        Elements values convention: 000ZZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZZ  : Flag position in the ISR register(5bits)
+  *        Elements values convention: 000000000XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *        Elements values convention: 0000ZZZZ00000000b
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+#define UART_IT_PE                          0x0028U              /*!< UART parity error interruption                 */
+#define UART_IT_TXE                         0x0727U              /*!< UART transmit data register empty interruption */
+#define UART_IT_TXFNF                       0x0727U              /*!< UART TX FIFO not full interruption             */
+#define UART_IT_TC                          0x0626U              /*!< UART transmission complete interruption        */
+#define UART_IT_RXNE                        0x0525U              /*!< UART read data register not empty interruption */
+#define UART_IT_RXFNE                       0x0525U              /*!< UART RXFIFO not empty interruption             */
+#define UART_IT_IDLE                        0x0424U              /*!< UART idle interruption                         */
+#define UART_IT_LBD                         0x0846U              /*!< UART LIN break detection interruption          */
+#define UART_IT_CTS                         0x096AU              /*!< UART CTS interruption                          */
+#define UART_IT_CM                          0x112EU              /*!< UART character match interruption              */
+#define UART_IT_WUF                         0x1476U              /*!< UART wake-up from stop mode interruption       */
+#define UART_IT_RXFF                        0x183FU              /*!< UART RXFIFO full interruption                  */
+#define UART_IT_TXFE                        0x173EU              /*!< UART TXFIFO empty interruption                 */
+#define UART_IT_RXFT                        0x1A7CU              /*!< UART RXFIFO threshold reached interruption     */
+#define UART_IT_TXFT                        0x1B77U              /*!< UART TXFIFO threshold reached interruption     */
+#define UART_IT_RTO                         0x0B3AU              /*!< UART receiver timeout interruption             */
+
+#define UART_IT_ERR                         0x0060U              /*!< UART error interruption                        */
+
+#define UART_IT_ORE                         0x0300U              /*!< UART overrun error interruption                */
+#define UART_IT_NE                          0x0200U              /*!< UART noise error interruption                  */
+#define UART_IT_FE                          0x0100U              /*!< UART frame error interruption                  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
+  * @{
+  */
+#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
+#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
+#define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */
+#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
+#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
+#define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */
+#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
+#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
+#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
+#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
+#define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
+#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_RECEPTION_TYPE_Values  UART Reception type values
+  * @{
+  */
+#define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */
+#define HAL_UART_RECEPTION_TOIDLE            (0x00000001U)             /*!< Reception till completion or IDLE event  */
+#define HAL_UART_RECEPTION_TORTO             (0x00000002U)             /*!< Reception till completion or RTO event   */
+#define HAL_UART_RECEPTION_TOCHARMATCH       (0x00000003U)             /*!< Reception till completion or CM event    */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+  * @{
+  */
+
+/** @brief  Reset UART handle states.
+  * @param  __HANDLE__ UART handle.
+  * @retval None
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                     } while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                     } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief  Flush the UART Data registers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
+  do{                \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+  }  while(0U)
+
+/** @brief  Clear the specified UART pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag
+  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag
+  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the UART PE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief  Clear the UART FE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief  Clear the UART NE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief  Clear the UART ORE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief  Clear the UART IDLE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief  Clear the UART TX FIFO empty clear flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
+
+/** @brief  Check whether the specified UART flag is set or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag
+  *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag
+  *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag
+  *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag
+  *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
+  *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
+  *            @arg @ref UART_FLAG_SBKF  Send Break flag
+  *            @arg @ref UART_FLAG_CMF   Character match flag
+  *            @arg @ref UART_FLAG_BUSY  Busy flag
+  *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
+  *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
+  *            @arg @ref UART_FLAG_CTS   CTS Change flag
+  *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
+  *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
+  *            @arg @ref UART_FLAG_TC    Transmission Complete flag
+  *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
+  *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag
+  *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
+  *            @arg @ref UART_FLAG_ORE   Overrun Error flag
+  *            @arg @ref UART_FLAG_NE    Noise Error flag
+  *            @arg @ref UART_FLAG_FE    Framing Error flag
+  *            @arg @ref UART_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Enable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (\
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
+                                                           ((__HANDLE__)->Instance->CR1 |= (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
+                                                           ((__HANDLE__)->Instance->CR2 |= (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 |= (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief  Disable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (\
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
+                                                           ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
+                                                           ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief  Check whether the specified UART interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
+
+/** @brief  Check whether the specified UART interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
+                                                                (__HANDLE__)->Instance->CR1 : \
+                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
+                                                                 (__HANDLE__)->Instance->CR2 : \
+                                                                 (__HANDLE__)->Instance->CR3)) & (1U <<\
+                                                                     (((uint16_t)(__INTERRUPT__)) &\
+                                                                      UART_IT_MASK)))  != RESET) ? SET : RESET)
+
+/** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
+  *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific UART request flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __REQ__ specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+  *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+  *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+  *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  * @retval None
+  */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the UART one bit sample method.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the UART one bit sample method.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
+
+/** @brief  Enable UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief  Disable UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief  Enable CTS flow control.
+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)               \
+  do{                                                             \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;               \
+  } while(0U)
+
+/** @brief  Disable CTS flow control.
+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)               \
+  do{                                                              \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);             \
+  } while(0U)
+
+/** @brief  Enable RTS flow control.
+  * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)              \
+  do{                                                            \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;              \
+  } while(0U)
+
+/** @brief  Disable RTS flow control.
+  * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)              \
+  do{                                                             \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);            \
+  } while(0U)
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros   UART Private Macros
+  * @{
+  */
+/** @brief  Get UART clok division factor from clock prescaler value.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval UART clock division factor
+  */
+#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
+  (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
+
+/** @brief  BRR division operation to set BRR register with LPUART.
+  * @param  __PCLK__ LPUART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                        \
+  ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \
+               (uint32_t)((__BAUD__)/2U)) / (__BAUD__))                                \
+  )
+
+/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                        \
+  (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                       \
+  ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  Check whether or not UART instance is Low Power UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
+  */
+#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
+
+/** @brief  Check UART Baud rate.
+  * @param  __BAUDRATE__ Baudrate specified by the user.
+  *         The maximum Baud Rate is derived from the maximum clock on G4 (i.e. 150 MHz)
+  *         divided by the smallest oversampling used on the USART (i.e. 8)
+  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+  */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 18750001U)
+
+/** @brief  Check UART assertion time.
+  * @param  __TIME__ 5-bit value assertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
+
+/** @brief  Check UART deassertion time.
+  * @param  __TIME__ 5-bit value deassertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/**
+  * @brief Ensure that UART frame number of stop bits is valid.
+  * @param __STOPBITS__ UART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that LPUART frame number of stop bits is valid.
+  * @param __STOPBITS__ LPUART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
+                                          ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that UART frame parity is valid.
+  * @param __PARITY__ UART frame parity.
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+                                    ((__PARITY__) == UART_PARITY_EVEN) || \
+                                    ((__PARITY__) == UART_PARITY_ODD))
+
+/**
+  * @brief Ensure that UART hardware flow control is valid.
+  * @param __CONTROL__ UART hardware flow control.
+  * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+  */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+  (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+  * @brief Ensure that UART communication mode is valid.
+  * @param __MODE__ UART communication mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+  * @brief Ensure that UART state is valid.
+  * @param __STATE__ UART state.
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+                                  ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+  * @brief Ensure that UART oversampling is valid.
+  * @param __SAMPLING__ UART oversampling.
+  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+  */
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+  * @brief Ensure that UART frame sampling is valid.
+  * @param __ONEBIT__ UART frame sampling.
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate detection mode is valid.
+  * @param __MODE__ UART auto Baud rate detection mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+
+/**
+  * @brief Ensure that UART receiver timeout setting is valid.
+  * @param __TIMEOUT__ UART receiver timeout setting.
+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+  */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/** @brief  Check the receiver timeout value.
+  * @note   The maximum UART receiver timeout value is 0xFFFFFF.
+  * @param  __TIMEOUTVALUE__ receiver timeout value.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/**
+  * @brief Ensure that UART LIN state is valid.
+  * @param __LIN__ UART LIN state.
+  * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+  */
+#define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
+                                     ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+  * @brief Ensure that UART LIN break detection length is valid.
+  * @param __LENGTH__ UART LIN break detection length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+
+/**
+  * @brief Ensure that UART DMA TX state is valid.
+  * @param __DMATX__ UART DMA TX state.
+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+  */
+#define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+                                       ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA RX state is valid.
+  * @param __DMARX__ UART DMA RX state.
+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+  */
+#define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+                                       ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+/**
+  * @brief Ensure that UART half-duplex state is valid.
+  * @param __HDSEL__ UART half-duplex state.
+  * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+  */
+#define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up method is valid.
+  * @param __WAKEUP__ UART wake-up method .
+  * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+  */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+  * @brief Ensure that UART request parameter is valid.
+  * @param __PARAM__ UART request parameter.
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
+                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
+                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
+                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @brief Ensure that UART advanced features initialization is valid.
+  * @param __INIT__ UART advanced features initialization.
+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
+                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
+                                                            UART_ADVFEATURE_SWAP_INIT              | \
+                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
+                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
+                                                            UART_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+  * @brief Ensure that UART frame TX inversion setting is valid.
+  * @param __TXINV__ UART frame TX inversion setting.
+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX inversion setting is valid.
+  * @param __RXINV__ UART frame RX inversion setting.
+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame data inversion setting is valid.
+  * @param __DATAINV__ UART frame data inversion setting.
+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+  * @param __SWAP__ UART frame RX/TX pins swap setting.
+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+  * @brief Ensure that UART frame overrun setting is valid.
+  * @param __OVERRUN__ UART frame overrun setting.
+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+  */
+#define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate state is valid.
+  * @param __AUTOBAUDRATE__ UART auto Baud rate state.
+  * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+                                                           ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+  * @param __DMA__ UART DMA enabling or disabling on error setting.
+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+  * @brief Ensure that UART frame MSB first setting is valid.
+  * @param __MSBFIRST__ UART frame MSB first setting.
+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+  * @brief Ensure that UART stop mode state is valid.
+  * @param __STOPMODE__ UART stop mode state.
+  * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART mute mode state is valid.
+  * @param __MUTE__ UART mute mode state.
+  * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+  */
+#define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up selection is valid.
+  * @param __WAKE__ UART wake-up selection.
+  * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+  */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+
+/**
+  * @brief Ensure that UART driver enable polarity is valid.
+  * @param __POLARITY__ UART driver enable polarity.
+  * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+  */
+#define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))
+
+/**
+  * @brief Ensure that UART Prescaler is valid.
+  * @param __CLOCKPRESCALER__ UART Prescaler value.
+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+  */
+#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
+
+/**
+  * @}
+  */
+
+/* Include UART HAL Extended module */
+#include "stm32g4xx_hal_uart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Errors functions  **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void              UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout);
+void              UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+/**
+  * @}
+  */
+
+/* Private variables -----------------------------------------------------------*/
+/** @defgroup UART_Private_variables UART Private variables
+  * @{
+  */
+/* Prescaler Table used in BRR computation macros.
+   Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
+extern const uint16_t UARTPrescTable[12];
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_UART_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
new file mode 100644
index 0000000..1408711
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
@@ -0,0 +1,651 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_uart_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_UART_EX_H
+#define STM32G4xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  UART wake up from stop mode parameters
+  */
+typedef struct
+{
+  uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
+                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+                                    be filled up. */
+
+  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
+                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
+
+  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+  * @{
+  */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+  * @{
+  */
+#define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
+  * @{
+  */
+#define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
+  * @brief    UART FIFO mode
+  * @{
+  */
+#define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */
+#define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
+  * @brief    UART TXFIFO threshold level
+  * @{
+  */
+#define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TX FIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TX FIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TX FIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TX FIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty            */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
+  * @brief    UART RXFIFO threshold level
+  * @{
+  */
+#define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RX FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RX FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RX FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RX FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+  * @{
+  */
+
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+                                           uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined(UART5)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART5)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \
+      {                                                       \
+        case RCC_UART5CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#elif defined(UART4)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#else
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#endif /* UART5 */
+
+/** @brief  Report the UART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define UART_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+    if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x01FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x003FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else                                                              \
+    {                                                                 \
+      (__HANDLE__)->Mask = 0x0000U;                                   \
+    }                                                                 \
+  } while(0U)
+
+/**
+  * @brief Ensure that UART frame length is valid.
+  * @param __LENGTH__ UART frame length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that UART wake-up address length is valid.
+  * @param __ADDRESS__ UART wake-up address length.
+  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+  */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+  * @brief Ensure that UART TXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART TXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
+
+/**
+  * @brief Ensure that UART RXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART RXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_UART_EX_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h
new file mode 100644
index 0000000..11dc3e6
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h
@@ -0,0 +1,8183 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_ADC_H
+#define STM32G4xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
+
+/** @defgroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Internal mask for ADC group regular sequencer:                             */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
+/* - sequencer register offset                                                */
+/* - sequencer rank bits position into the selected register                  */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET                 (0x00000000UL)
+#define ADC_SQR2_REGOFFSET                 (0x00000100UL)
+#define ADC_SQR3_REGOFFSET                 (0x00000200UL)
+#define ADC_SQR4_REGOFFSET                 (0x00000300UL)
+
+#define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
+                                            | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_SQRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
+#define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted  */
+/* into ADC group regular sequencer ranks literals definition.                */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ1_Pos)
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ2_Pos)
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ3_Pos)
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ4_Pos)
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ5_Pos)
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ6_Pos)
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ7_Pos)
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ8_Pos)
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ9_Pos)
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
+
+
+
+/* Internal mask for ADC group injected sequencer:                            */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
+/* - data register offset                                                     */
+/* - sequencer rank bits position into the selected register                  */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET                 (0x00000000UL)
+#define ADC_JDR2_REGOFFSET                 (0x00000100UL)
+#define ADC_JDR3_REGOFFSET                 (0x00000200UL)
+#define ADC_JDR4_REGOFFSET                 (0x00000300UL)
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
+                                            | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+#define ADC_JDRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
+
+/* Definition of ADC group injected sequencer bits information to be inserted */
+/* into ADC group injected sequencer ranks literals definition.               */
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ1_Pos)
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ2_Pos)
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ3_Pos)
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ4_Pos)
+
+
+
+/* Internal mask for ADC group regular trigger:                               */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
+/* - regular trigger source                                                   */
+/* - regular trigger edge                                                     */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible                  */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
+                                             ((ADC_CFGR_EXTSEL)                            << (4U * 1UL)) | \
+                                             ((ADC_CFGR_EXTSEL)                            << (4U * 2UL)) | \
+                                             ((ADC_CFGR_EXTSEL)                            << (4U * 3UL))  )
+
+/* Mask containing trigger edge masks for each of possible                    */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1UL)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2UL)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3UL))  )
+
+/* Definition of ADC group regular trigger bits information.                  */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (ADC_CFGR_EXTSEL_Pos)
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (ADC_CFGR_EXTEN_Pos)
+
+
+
+/* Internal mask for ADC group injected trigger:                              */
+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
+/* - injected trigger source                                                  */
+/* - injected trigger edge                                                    */
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible                  */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \
+                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \
+                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \
+                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )
+
+/* Mask containing trigger edge masks for each of possible                    */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
+
+/* Definition of ADC group injected trigger bits information.                 */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (ADC_JSQR_JEXTSEL_Pos)
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (ADC_JSQR_JEXTEN_Pos)
+
+
+
+
+
+
+/* Internal mask for ADC channel:                                             */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
+/* - channel identifier defined by number                                     */
+/* - channel identifier defined by bitfield                                   */
+/* - channel differentiation between external channels (connected to          */
+/*   GPIO pins) and internal channels (connected to internal paths)           */
+/* - channel sampling time defined by SMPRx register offset                   */
+/*   and SMPx bits positions into SMPRx register                              */
+#define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)
+#define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
+#define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
+                                            | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_2       (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET                (0x00000000UL)
+#define ADC_SMPR2_REGOFFSET                (0x02000000UL)
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+#define ADC_SMPRX_REGOFFSET_POS            (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000UL)
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
+
+/* Definition of channels ID number information to be inserted into           */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_NUMBER               (0x00000000UL)
+#define ADC_CHANNEL_1_NUMBER               (ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER               (ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_3_NUMBER               (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER               (ADC_CFGR_AWD1CH_2)
+#define ADC_CHANNEL_5_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_7_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER               (ADC_CFGR_AWD1CH_3)
+#define ADC_CHANNEL_9_NUMBER               (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_11_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
+#define ADC_CHANNEL_13_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_15_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
+                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4)
+#define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
+
+/* Definition of channels ID bitfield information to be inserted into         */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)
+#define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)
+#define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)
+#define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)
+#define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)
+#define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)
+#define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)
+#define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)
+#define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)
+#define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)
+#define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)
+#define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)
+#define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)
+#define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)
+#define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)
+#define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)
+#define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
+#define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
+#define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
+
+/* Definition of channels sampling time information to be inserted into       */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
+#define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
+#define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
+#define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
+#define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
+#define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
+#define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
+#define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
+#define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
+#define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
+#define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
+#define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
+#define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
+#define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
+#define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
+#define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
+#define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
+#define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
+#define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
+
+
+/* Internal mask for ADC mode single or differential ended:                   */
+/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
+/* the relevant bits for:                                                     */
+/* (concatenation of multiple bits used in different registers)               */
+/* - ADC calibration: calibration start, calibration factor get or set        */
+/* - ADC channels: set each ADC channel ending mode                           */
+#define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)
+#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
+#define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
+#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000UL)                           /* Selection of 1 bit to discriminate differential mode: mask of bit */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16UL)                                   /* Selection of 1 bit to discriminate differential mode: position of bit */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
+
+/* Internal mask for ADC analog watchdog:                                     */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
+/* (concatenation of multiple bits used in different analog watchdogs,        */
+/* (feature of several watchdogs not available on all STM32 families)).       */
+/* - analog watchdog 1: monitored channel defined by number,                  */
+/*   selection of ADC group (ADC groups regular and-or injected).             */
+/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
+/*   selection on groups.                                                     */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)
+#define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)
+#define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)
+
+/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
+/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
+#define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
+#define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
+#define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+
+#define ADC_AWD_CRX_REGOFFSET_POS          (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
+#define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
+#define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
+#define ADC_AWD_TRX_BIT_HIGH_MASK          (0x00010000UL)                   /* Selection of 1 bit to discriminate threshold high: mask of bit */
+#define ADC_AWD_TRX_BIT_HIGH_POS           (16UL)                           /* Selection of 1 bit to discriminate threshold high: position of bit */
+#define ADC_AWD_TRX_BIT_HIGH_SHIFT4        (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
+
+/* Internal mask for ADC offset:                                              */
+/* Internal register offset for ADC offset number configuration */
+#define ADC_OFR1_REGOFFSET                 (0x00000000UL)
+#define ADC_OFR2_REGOFFSET                 (0x00000001UL)
+#define ADC_OFR3_REGOFFSET                 (0x00000002UL)
+#define ADC_OFR4_REGOFFSET                 (0x00000003UL)
+#define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
+                                            | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+
+
+/* ADC registers bits positions */
+#define ADC_CFGR_RES_BITOFFSET_POS         (ADC_CFGR_RES_Pos)
+#define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (ADC_CFGR_AWD1SGL_Pos)
+#define ADC_CFGR_AWD1EN_BITOFFSET_POS      (ADC_CFGR_AWD1EN_Pos)
+#define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (ADC_CFGR_JAWD1EN_Pos)
+#define ADC_TR1_HT1_BITOFFSET_POS          (ADC_TR1_HT1_Pos)
+
+
+/* ADC registers bits groups */
+#define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
+
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF                   (3000UL)                     /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G4, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP               (130L)                       /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG          (3000UL)                     /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Driver macro reserved for internal use: set a pointer to
+  *         a register from a register basis from which an offset
+  *         is applied.
+  * @param  __REG__ Register basis from which the offset is applied.
+  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+  * @retval Pointer to register address
+  */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
+  ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of ADC common parameters
+  *         and multimode
+  *         (all ADC instances belonging to the same ADC common instance).
+  * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
+  *         is conditioned to ADC instances state (all ADC instances
+  *         sharing the same ADC common instance):
+  *         All ADC instances sharing the same ADC common instance must be
+  *         disabled.
+  */
+typedef struct
+{
+  uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
+                                             This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
+                                             @note On this STM32 series, if ADC group injected is used, some
+                                                   clock ratio constraints between ADC clock and AHB clock
+                                                   must be respected. Refer to reference manual.
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
+
+  uint32_t MultiDMATransfer;            /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
+
+  uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Affects both group regular and group injected (availability
+  *         of ADC group injected depends on STM32 families).
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t Resolution;                  /*!< Set ADC resolution.
+                                             This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
+
+  uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
+                                             This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
+
+  uint32_t LowPowerMode;                /*!< Set ADC low power mode.
+                                             This parameter can be a value of @ref ADC_LL_EC_LP_MODE
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+                                             @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
+                                                   (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
+                                                   In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+
+  uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
+
+  uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+                                             @note This parameter has an effect only if group regular sequencer is enabled
+                                                   (scan length of 2 ranks or more).
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+  uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+                                             Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
+
+  uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
+
+  uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
+                                             data preserved or overwritten.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC group injected.
+  * @note   These parameters have an impact on ADC scope: ADC group injected.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "INJ").
+  * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+                                             @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
+                                                   (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
+                                                   In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
+
+  uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
+
+  uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+                                             @note This parameter has an effect only if group injected sequencer is enabled
+                                                   (scan length of 2 ranks or more).
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+  uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+                                             Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
+
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+  * @brief    Flags defines which can be used with LL_ADC_ReadReg function
+  * @{
+  */
+#define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
+#define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */
+#define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence conversions */
+#define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue overflow */
+#define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
+#define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
+#define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */
+#define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */
+#define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master group regular end of sequence conversions */
+#define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
+#define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master group regular overrun */
+#define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave group regular overrun */
+#define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master group regular end of sampling phase */
+#define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master group injected end of sequence conversions */
+#define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
+#define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master group injected contexts queue overflow */
+#define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
+#define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
+#define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
+#define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
+#define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
+#define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
+#define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+  * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
+  * @{
+  */
+#define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
+#define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */
+#define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */
+#define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */
+#define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary conversion */
+#define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence conversions */
+#define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue overflow */
+#define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */
+#define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */
+#define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
+  * @{
+  */
+/* List of ADC registers intended to be used (most commonly) with             */
+/* DMA transfer.                                                              */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
+#define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
+  * @{
+  */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock without prescaler */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+#define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                                        /*!< ADC asynchronous clock without prescaler */
+#define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2   */
+#define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4   */
+#define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6   */
+#define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8   */
+#define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10  */
+#define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12  */
+#define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16  */
+#define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32  */
+#define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64  */
+#define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128 */
+#define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
+  * @{
+  */
+/* Note: Other measurement paths to internal channels may be available        */
+/*       (connections to other peripherals).                                  */
+/*       If they are not listed below, they do not require any specific       */
+/*       path enable. In this case, Access to measurement path is done        */
+/*       only by selecting the corresponding ADC internal channel.            */
+#define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)         /*!< ADC measurement paths all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_VSENSESEL)    /*!< ADC measurement path to internal channel temperature sensor */
+#define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATSEL)      /*!< ADC measurement path to internal channel Vbat */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
+  * @{
+  */
+#define LL_ADC_RESOLUTION_12B              (0x00000000UL)                      /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution  8 bits */
+#define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution  6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
+  * @{
+  */
+#define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000UL)         /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR_ALIGN)       /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
+  * @{
+  */
+#define LL_ADC_LP_MODE_NONE                (0x00000000UL)                      /*!< No ADC low power mode activated */
+#define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number
+  * @{
+  */
+#define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
+  * @{
+  */
+#define LL_ADC_OFFSET_DISABLE              (0x00000000UL)         /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_ENABLE               (ADC_OFR1_OFFSET1_EN)  /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
+  * @{
+  */
+#define LL_ADC_OFFSET_SIGN_NEGATIVE        (0x00000000UL)       /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_SIGN_POSITIVE        (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
+  * @{
+  */
+#define LL_ADC_OFFSET_SATURATION_DISABLE   (0x00000000UL)          /*!< ADC offset saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_SATURATION_ENABLE    (ADC_OFR1_SATEN)        /*!< ADC offset saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
+/**
+  * @}
+  */
+/** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
+  * @{
+  */
+#define LL_ADC_GROUP_REGULAR               (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED              (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL) /*!< ADC both groups regular and injected */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
+  * @{
+  */
+#define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
+#define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
+#define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
+#define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
+#define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
+#define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
+#define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
+#define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
+#define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
+#define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
+#define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */
+#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1     (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */
+#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5     (LL_ADC_CHANNEL_4  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */
+#define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */
+#define LL_ADC_CHANNEL_VOPAMP1             (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */
+#define LL_ADC_CHANNEL_VOPAMP2             (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */
+#define LL_ADC_CHANNEL_VOPAMP3_ADC2        (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */
+#define LL_ADC_CHANNEL_VOPAMP3_ADC3        (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */
+#define LL_ADC_CHANNEL_VOPAMP4             (LL_ADC_CHANNEL_5  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */
+#define LL_ADC_CHANNEL_VOPAMP5             (LL_ADC_CHANNEL_3  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */
+#define LL_ADC_CHANNEL_VOPAMP6             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
+  * @{
+  */
+#define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000UL)                                                                                                  /*!<
+                                           ADC group regular conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH1       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH1       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_CH1       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO     (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH1      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH2      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH3      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE2     (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!<
+                                           ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
+#define LL_ADC_REG_TRIG_EXT_LPTIM_OUT      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
+  * @{
+  */
+#define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SAMPLING_MODE  ADC group regular - Sampling mode
+  * @{
+  */
+#define LL_ADC_REG_SAMPLING_MODE_NORMAL               (0x00000000UL)       /*!< ADC conversions sampling phase duration is defined using  @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */
+#define LL_ADC_REG_SAMPLING_MODE_BULB                 (ADC_CFGR2_BULB)     /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
+                                                                                Note: First conversion is using minimal sampling time (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */
+#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED    (ADC_CFGR2_SMPTRIG)  /*!< ADC conversions sampling phase is controlled by trigger events:
+                                                                                 Trigger rising edge  = start sampling
+                                                                                 Trigger falling edge = stop sampling and start conversion */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
+  * @{
+  */
+#define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)          /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
+  * @{
+  */
+#define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000UL)                        /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                  ADC_CFGR_DMAEN)    /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)    /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+/**
+  * @}
+  */
+
+#if defined(ADC_SMPR1_SMPPLUS)
+/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
+  * @{
+  */
+#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT      (0x00000000UL)      /*!< ADC sampling time let to default settings. */
+#define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
+  * @{
+  */
+#define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)         /*!< ADC group regular behavior in case of overrun: data preserved */
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
+  * @{
+  */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000UL)                                              /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
+  * @{
+  */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                                                               /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                               ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
+  * @{
+  */
+#define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000UL)                                                                                                      /*!<
+                                           ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                     /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM16_CH1      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO     (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2    (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_CH2      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_CH4      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
+                                           Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10    (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2 instances. */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
+#define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion trigger polarity set to falling edge */
+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000UL)         /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode
+  * @{
+  */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
+#define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
+  * @{
+  */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                  /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
+  * @{
+  */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000UL)         /*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
+  * @{
+  */
+#define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+  * @{
+  */
+#define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000UL)                                              /*!< Sampling time 2.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_6CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_12CYCLES_5     (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 12.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_24CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 47.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 247.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
+  * @{
+  */
+#define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
+#define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
+#define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+  * @{
+  */
+#define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+#define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
+#define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
+  * @{
+  */
+#define LL_ADC_AWD_DISABLE                 (0x00000000UL)                                                                                      /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                                    | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN                                     ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG       ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG       ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
+#define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
+#define LL_ADC_AWD_CH_VOPAMP1_REG          ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP1_INJ          ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP2_REG          ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP2_INJ          ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP4_REG          ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP4_INJ          ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP4_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP5_REG          ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP5_INJ          ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP5_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP6_REG          ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP6_INJ          ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP6_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by either group regular or injected */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
+  * @{
+  */
+#define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1              ) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW           (              ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
+#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG  Analog watchdog - filtering config
+  * @{
+  */
+#define LL_ADC_AWD_FILTERING_NONE          (0x00000000UL)                                              /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_2SAMPLES      (                                        ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_3SAMPLES      (                    ADC_TR1_AWDFILT_1                    ) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_4SAMPLES      (                    ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_5SAMPLES      (ADC_TR1_AWDFILT_2                                        ) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_6SAMPLES      (ADC_TR1_AWDFILT_2 |                     ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_7SAMPLES      (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1                    ) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_8SAMPLES      (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
+  * @{
+  */
+#define LL_ADC_OVS_DISABLE                 (0x00000000UL)                                        /*!< ADC oversampling disabled. */
+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
+#define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
+#define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*!< ADC oversampling on conversions of ADC group injected. */
+#define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
+  * @{
+  */
+#define LL_ADC_OVS_REG_CONT                (0x00000000UL)         /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
+#define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
+  * @{
+  */
+#define LL_ADC_OVS_RATIO_2                 (0x00000000UL)                                           /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_4                 (                                      ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_8                 (                   ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_16                (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2                                      ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2                    | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift
+  * @{
+  */
+#define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                                                              /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+/**
+  * @}
+  */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode
+  * @{
+  */
+#define LL_ADC_MULTI_INDEPENDENT           (0x00000000UL)                                                      /*!< ADC dual mode disabled (ADC independent mode) */
+#define LL_ADC_MULTI_DUAL_REG_SIMULT       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: group regular simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTERL       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                 ADC_CCR_DUAL_2                  | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3                                   | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                   ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                  ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                  ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer
+  * @{
+  */
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC        (0x00000000UL)                                     /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (                 ADC_CCR_MDMA_1                 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B   (                 ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1                 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B   (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
+  * @{
+  */
+#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE   (0x00000000UL)                                                          /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
+#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES  (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES  (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES  (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3                                     | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave
+  * @{
+  */
+#define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
+#define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */
+#define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
+/**
+  * @}
+  */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+
+/** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
+  * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
+/*       not timeout values.                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Indications for estimation of ADC timeout delays, for this           */
+/*       STM32 series:                                                        */
+/*       - ADC calibration time: maximum delay is 112/fADC.                   */
+/*         (refer to device datasheet, parameter "tCAL")                      */
+/*       - ADC enable time: maximum delay is 1 conversion cycle.              */
+/*         (refer to device datasheet, parameter "tSTAB")                     */
+/*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
+/*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
+/*         cycles                                                             */
+/*       - ADC conversion time: duration depending on ADC clock and ADC       */
+/*         configuration.                                                     */
+/*         (refer to device reference manual, section "Timing")               */
+
+/* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "tADCVREG_STUP").                                                */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+
+/* Delay for internal voltage reference stabilization time.                   */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "tstart_vrefint").                                               */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_VREFINT_STAB_US           ( 12UL)  /*!< Delay for internal voltage reference stabilization time */
+
+/* Delay for temperature sensor stabilization time.                           */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US        (120UL)  /*!< Delay for temperature sensor stabilization time */
+
+/* Delay required between ADC end of calibration and ADC enable.              */
+/* Note: On this STM32 series, a minimum number of ADC clock cycles           */
+/*       are required between ADC end of calibration and ADC enable.          */
+/*       Wait time can be computed in user application by waiting for the     */
+/*       equivalent number of CPU cycles, by taking into account              */
+/*       ratio of CPU clock versus ADC clock prescalers.                      */
+/* Unit: ADC clock cycles.                                                    */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES   (  4UL)  /*!< Delay required between ADC end of calibration and ADC enable */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+  * @{
+  */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get ADC channel number in decimal format
+  *         from literals LL_ADC_CHANNEL_x.
+  * @note   Example:
+  *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+  *           will return decimal number "4".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned, either defined with number
+  *         or with bitfield (only one bit must be set).
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @retval Value between Min_Data=0 and Max_Data=18
+  */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
+  ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ?                               \
+   (                                                                                       \
+       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
+   )                                                                                       \
+   :                                                                                       \
+   (                                                                                       \
+       (uint32_t)POSITION_VAL((__CHANNEL__))                                               \
+   )                                                                                       \
+  )
+
+/**
+  * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+  *         from number in decimal format.
+  * @note   Example:
+  *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+  *           will return a data equivalent to "LL_ADC_CHANNEL_4".
+  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                  \
+  (((__DECIMAL_NB__) <= 9UL) ?                                                                          \
+   (                                                                                                    \
+       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |          \
+       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                             |          \
+       (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))           \
+   )                                                                                                    \
+   :                                                                                                    \
+   (                                                                                                    \
+       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                      | \
+       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                      | \
+       (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \
+   )                                                                                                    \
+  )
+
+/**
+  * @brief  Helper macro to determine whether the selected channel
+  *         corresponds to literal definitions of driver.
+  * @note   The different literal definitions of ADC channels are:
+  *         - ADC internal channel:
+  *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+  *         - ADC external channel (channel connected to a GPIO pin):
+  *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+  * @note   The channel parameter must be a value defined from literal
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+  *         must not be a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+  */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
+  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
+
+/**
+  * @brief  Helper macro to convert a channel defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         to its equivalent parameter definition of a ADC external channel
+  *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+  * @note   The channel parameter can be, additionally to a value
+  *         defined from parameter definition of a ADC internal channel
+  *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is returned
+  *         from ADC registers.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
+  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+  * @brief  Helper macro to determine whether the internal channel
+  *         selected is available on the ADC instance selected.
+  * @note   The channel parameter must be a value defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         must not be a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __ADC_INSTANCE__ ADC instance
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+  *         Value "1" if the internal channel selected is available on the ADC instance selected.
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  ((((__ADC_INSTANCE__) == ADC1)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC2)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC3)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC4)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC5)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+  )
+#elif defined(STM32G471xx)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  ((((__ADC_INSTANCE__) == ADC1)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC2)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC3)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+  )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  ((((__ADC_INSTANCE__) == ADC1)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC2)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+      )                                                                        \
+   )                                                                           \
+  )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  ((((__ADC_INSTANCE__) == ADC1)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC2)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC3)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+  )
+#endif
+
+/**
+  * @brief  Helper macro to define ADC analog watchdog parameter:
+  *         define a single channel to monitor with analog watchdog
+  *         from sequencer channel and groups definition.
+  * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+  *         Example:
+  *           LL_ADC_SetAnalogWDMonitChannels(
+  *             ADC1, LL_ADC_AWD1,
+  *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  * @param  __GROUP__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_GROUP_REGULAR
+  *         @arg @ref LL_ADC_GROUP_INJECTED
+  *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG  (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ  (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG  (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ  (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(6)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(6)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (6)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ         (1)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ         (2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ    (2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     (0)(3)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     (0)(3)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ    (3)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ         (5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ         (5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG          (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ          (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ         (4)
+  *
+  *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
+  (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
+   ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                         \
+   :                                                                                                      \
+   ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                                 \
+   ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                        \
+   :                                                                                                      \
+   (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)        \
+  )
+
+/**
+  * @brief  Helper macro to set the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
+  *         or @ref LL_ADC_SetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to set the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           LL_ADC_SetAnalogWDThresholds
+  *            (< ADCx param >,
+  *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+  ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+
+/**
+  * @brief  Helper macro to get the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to get the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+  *            (LL_ADC_RESOLUTION_8B,
+  *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+  ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+
+/**
+  * @brief  Helper macro to get the ADC analog watchdog threshold high
+  *         or low from raw value containing both thresholds concatenated.
+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+  *         Example, to get analog watchdog threshold high from the register raw value:
+  *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
+  * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)       \
+  (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
+
+/**
+  * @brief  Helper macro to set the ADC calibration value with both single ended
+  *         and differential modes calibration factors concatenated.
+  * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().
+  *         Example, to set calibration factors single ended to 0x55
+  *         and differential ended to 0x2A:
+  *           LL_ADC_SetCalibrationFactor(
+  *             ADC1,
+  *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
+  * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
+  * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \
+  (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Helper macro to get the ADC multimode conversion data of ADC master
+  *         or ADC slave from raw value with both ADC conversion data concatenated.
+  * @note   This macro is intended to be used when multimode transfer by DMA
+  *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+  *         In this case the transferred data need to processed with this macro
+  *         to separate the conversion data of ADC master and ADC slave.
+  * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_MASTER
+  *         @arg @ref LL_ADC_MULTI_SLAVE
+  * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
+  (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Helper macro to select, from a ADC instance, to which ADC instance
+  *         it has a dependence in multimode (ADC master of the corresponding
+  *         ADC common instance).
+  * @note   In case of device with multimode available and a mix of
+  *         ADC instances compliant and not compliant with multimode feature,
+  *         ADC instances not compliant with multimode feature are
+  *         considered as master instances (do not depend to
+  *         any other ADC instance).
+  * @param  __ADCx__ ADC instance
+  * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
+  */
+#if defined(ADC5)
+#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+  ( ( ((__ADCx__) == ADC2)                                                     \
+    )?                                                                         \
+    (ADC1)                                                                     \
+    :                                                                          \
+    ( ( ((__ADCx__) == ADC4)                                                   \
+      )?                                                                       \
+      (ADC3)                                                                   \
+      :                                                                        \
+      (__ADCx__)                                                               \
+    )                                                                          \
+  )
+#else
+#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+  ( ( ((__ADCx__) == ADC2)                                                     \
+    )?                                                                         \
+    (ADC1)                                                                     \
+    :                                                                          \
+    (__ADCx__)                                                                 \
+  )
+#endif /* ADC5 */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Helper macro to select the ADC common instance
+  *         to which is belonging the selected ADC instance.
+  * @note   ADC common register instance can be used for:
+  *         - Set parameters common to several ADC instances
+  *         - Multimode (for devices with several ADC instances)
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @param  __ADCx__ ADC instance
+  * @retval ADC common register instance
+  */
+#if defined(ADC345_COMMON)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
+  ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2))                              \
+    ? (                                                                        \
+       (ADC12_COMMON)                                                          \
+      )                                                                        \
+      :                                                                        \
+      (                                                                        \
+       (ADC345_COMMON)                                                         \
+      )                                                                        \
+  )
+#else
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)  (ADC12_COMMON)
+#endif /* ADC345_COMMON */
+/**
+  * @brief  Helper macro to check if all ADC instances sharing the same
+  *         ADC common instance are disabled.
+  * @note   This check is required by functions with setting conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @note   On devices with only 1 ADC common instance, parameter of this macro
+  *         is useless and can be ignored (parameter kept for compatibility
+  *         with devices featuring several ADC common instances).
+  * @param  __ADCXY_COMMON__ ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value "0" if all ADC instances sharing the same ADC common instance
+  *         are disabled.
+  *         Value "1" if at least one ADC instance sharing the same ADC common instance
+  *         is enabled.
+  */
+#if defined(ADC345_COMMON)
+#if defined(ADC4) &&  defined(ADC5)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
+    ? (                                                                        \
+       (LL_ADC_IsEnabled(ADC1) |                                               \
+        LL_ADC_IsEnabled(ADC2)  )                                              \
+      )                                                                        \
+      :                                                                        \
+      (                                                                        \
+       (LL_ADC_IsEnabled(ADC3) |                                               \
+        LL_ADC_IsEnabled(ADC4) |                                               \
+        LL_ADC_IsEnabled(ADC5)  )                                              \
+      )                                                                        \
+  )
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
+    ? (                                                                        \
+       (LL_ADC_IsEnabled(ADC1) |                                               \
+        LL_ADC_IsEnabled(ADC2)  )                                              \
+      )                                                                        \
+      :                                                                        \
+      (LL_ADC_IsEnabled(ADC3))                                                 \
+  )
+#endif /* ADC4 && ADC5 */
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
+#endif
+
+/**
+  * @brief  Helper macro to define the ADC conversion data full-scale digital
+  *         value corresponding to the selected ADC resolution.
+  * @note   ADC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
+  */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+  (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
+
+/**
+  * @brief  Helper macro to convert the ADC conversion data from
+  *         a resolution to another resolution.
+  * @param  __DATA__ ADC conversion data to be converted
+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data to the requested resolution
+  */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+                                         __ADC_RESOLUTION_CURRENT__,\
+                                         __ADC_RESOLUTION_TARGET__)          \
+(((__DATA__)                                                                 \
+  << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \
+)
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                      __ADC_DATA__,\
+                                      __ADC_RESOLUTION__)                    \
+((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
+)
+
+/**
+  * @brief  Helper macro to calculate analog reference voltage (Vref+)
+  *         (unit: mVolt) from ADC conversion data of internal voltage
+  *         reference VrefInt.
+  * @note   Computation is using VrefInt calibration value
+  *         stored in system memory for each device during production.
+  * @note   This voltage depends on user board environment: voltage level
+  *         connected to pin Vref+.
+  *         On devices with small package, the pin Vref+ is not present
+  *         and internally bonded to pin Vdda.
+  * @note   On this STM32 series, calibration data of internal voltage reference
+  *         VrefInt corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         internal voltage reference VrefInt.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *         of internal voltage reference VrefInt (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Analog reference voltage (unit: mV)
+  */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+                                         __ADC_RESOLUTION__)                 \
+(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
+                                    (__ADC_RESOLUTION__),                    \
+                                    LL_ADC_RESOLUTION_12B)                   \
+)
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor calibration values
+  *         stored in system memory for each device during production.
+  * @note   Calculation formula:
+  *           Temperature = ((TS_ADC_DATA - TS_CAL1)
+  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
+  *                Avg_Slope = (TS_CAL2 - TS_CAL1)
+  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL1 (calibrated in factory)
+  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL2 (calibrated in factory)
+  *         Caution: Calculation relevancy under reserve that calibration
+  *                  parameters are correct (address and data).
+  *                  To calculate temperature using temperature sensor
+  *                  datasheet typical values (generic values less, therefore
+  *                  less accurate than calibrated values),
+  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   On this STM32 series, calibration data of temperature sensor
+  *         corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         temperature sensor.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+  *                                 temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
+  *                                 sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+                                  __TEMPSENSOR_ADC_DATA__,\
+                                  __ADC_RESOLUTION__)                            \
+(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
+                                                  (__ADC_RESOLUTION__),          \
+                                                  LL_ADC_RESOLUTION_12B)         \
+                 * (__VREFANALOG_VOLTAGE__))                                     \
+                / TEMPSENSOR_CAL_VREFANALOG)                                     \
+      - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
+   ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
+  ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+ ) + TEMPSENSOR_CAL1_TEMP                                                        \
+)
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor typical values
+  *         (refer to device datasheet).
+  * @note   Calculation formula:
+  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+  *                         / Avg_Slope + CALx_TEMP
+  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
+  *                                   (unit: digital value)
+  *                Avg_Slope        = temperature sensor slope
+  *                                   (unit: uV/Degree Celsius)
+  *                TS_TYP_CALx_VOLT = temperature sensor digital value at
+  *                                   temperature CALx_TEMP (unit: mV)
+  *         Caution: Calculation relevancy under reserve the temperature sensor
+  *                  of the current device has characteristics in line with
+  *                  datasheet typical values.
+  *                  If temperature sensor calibration values are available on
+  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+  *                  temperature calculation will be more accurate using
+  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   ADC measurement data must correspond to a resolution of 12 bits
+  *         (full scale digital value 4095). If not the case, the data must be
+  *         preliminarily rescaled to an equivalent resolution of 12 bits.
+  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+  *                                       On STM32G4, refer to device datasheet parameter "Avg_Slope".
+  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
+  *                                       On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
+  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+                                             __TEMPSENSOR_TYP_CALX_V__,\
+                                             __TEMPSENSOR_CALX_TEMP__,\
+                                             __VREFANALOG_VOLTAGE__,\
+                                             __TEMPSENSOR_ADC_DATA__,\
+                                             __ADC_RESOLUTION__)            \
+(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
+               / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
+              * 1000UL)                                                     \
+    -                                                                       \
+    (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
+              * 1000UL)                                                     \
+   )                                                                        \
+  ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                \
+ ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                    \
+)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+  * @{
+  */
+/* Note: LL ADC functions to set DMA transfer are located into sections of    */
+/*       configuration of ADC instance, groups and multimode (if available):  */
+/*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
+
+/**
+  * @brief  Function to help to configure DMA transfer from ADC: retrieve the
+  *         ADC register address from ADC instance and a list of ADC registers
+  *         intended to be used (most commonly) with DMA transfer.
+  * @note   These ADC registers are data registers:
+  *         when ADC conversion data is available in ADC data registers,
+  *         ADC generates a DMA transfer request.
+  * @note   This macro is intended to be used with LL DMA driver, refer to
+  *         function "LL_DMA_ConfigAddresses()".
+  *         Example:
+  *           LL_DMA_ConfigAddresses(DMA1,
+  *                                  LL_DMA_CHANNEL_1,
+  *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+  *                                  (uint32_t)&< array or variable >,
+  *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+  * @note   For devices with several ADC: in multimode, some devices
+  *         use a different data register outside of ADC instance scope
+  *         (common data register). This macro manages this register difference,
+  *         only ADC instance has to be set as parameter.
+  * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n
+  *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n
+  *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr
+  * @param  ADCx ADC instance
+  * @param  Register This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+  *
+  *         (1) Available on devices with several ADC instances.
+  * @retval ADC register address
+  */
+#if defined(ADC_MULTIMODE_SUPPORT)
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+  uint32_t data_reg_addr;
+
+  if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
+  {
+    /* Retrieve address of register DR */
+    data_reg_addr = (uint32_t) &(ADCx->DR);
+  }
+  else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+  {
+    /* Retrieve address of register CDR */
+    data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+  }
+
+  return data_reg_addr;
+}
+#else
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+  /* Prevent unused argument(s) compilation warning */
+  (void)(Register);
+
+  /* Retrieve address of register DR */
+  return (uint32_t) &(ADCx->DR);
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+  * @{
+  */
+
+/**
+  * @brief  Set parameter common to several ADC: Clock source and prescaler.
+  * @note   On this STM32 series, if ADC group injected is used, some
+  *         clock ratio constraints between ADC clock and AHB clock
+  *         must be respected.
+  *         Refer to reference manual.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n
+  *         CCR      PRESC          LL_ADC_SetCommonClock
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  CommonClock This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: Clock source and prescaler.
+  * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n
+  *         CCR      PRESC          LL_ADC_GetCommonClock
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Configure all paths (overwrite current configuration).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  *         The values not selected are removed from configuration.
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay is required for internal voltage reference and
+  *         temperature sensor stabilization time.
+  *         Refer to device datasheet.
+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+  *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
+  *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalCh\n
+  *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Add paths to the current configuration.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay is required for internal voltage reference and
+  *         temperature sensor stabilization time.
+  *         Refer to device datasheet.
+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+  *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChAdd\n
+  *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalChAdd\n
+  *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalChAdd
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  SET_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Remove paths to the current configuration.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChRem\n
+  *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalChRem\n
+  *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalChRem
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: measurement path to internal
+  *         channels (VrefInt, temperature sensor, ...).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
+  *         CCR      VSENSESEL      LL_ADC_GetCommonPathInternalCh\n
+  *         CCR      VBATSEL        LL_ADC_GetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Set ADC calibration factor in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   This function is intended to set calibration parameters
+  *         without having to perform a new calibration using
+  *         @ref LL_ADC_StartCalibration().
+  * @note   For devices with differential mode available:
+  *         Calibration of offset is specific to each of
+  *         single-ended and differential modes
+  *         (calibration factor must be specified for each of these
+  *         differential modes, if used afterwards and if the application
+  *         requires their calibration).
+  * @note   In case of setting calibration factors of both modes single ended
+  *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
+  *         both calibration factors must be concatenated.
+  *         To perform this processing, use helper macro
+  *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled, without calibration on going, without conversion
+  *         on going on group regular.
+  * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n
+  *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor
+  * @param  ADCx ADC instance
+  * @param  SingleDiff This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
+  * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
+{
+  MODIFY_REG(ADCx->CALFACT,
+             SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
+             CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
+}
+
+/**
+  * @brief  Get ADC calibration factor in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   Calibration factors are set by hardware after performing
+  *         a calibration run using function @ref LL_ADC_StartCalibration().
+  * @note   For devices with differential mode available:
+  *         Calibration of offset is specific to each of
+  *         single-ended and differential modes
+  * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n
+  *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor
+  * @param  ADCx ADC instance
+  * @param  SingleDiff This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval Value between Min_Data=0x00 and Max_Data=0x7F
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+  /* Retrieve bits with position in register depending on parameter           */
+  /* "SingleDiff".                                                            */
+  /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */
+  /* containing other bits reserved for other purpose.                        */
+  return (uint32_t)(READ_BIT(ADCx->CALFACT,
+                             (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
+                                                                                  ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
+}
+
+/**
+  * @brief  Set ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     RES            LL_ADC_SetResolution
+  * @param  ADCx ADC instance
+  * @param  Resolution This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
+}
+
+/**
+  * @brief  Get ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CFGR     RES            LL_ADC_GetResolution
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
+}
+
+/**
+  * @brief  Set ADC conversion data alignment.
+  * @note   Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     ALIGN          LL_ADC_SetDataAlignment
+  * @param  ADCx ADC instance
+  * @param  DataAlignment This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
+}
+
+/**
+  * @brief  Get ADC conversion data alignment.
+  * @note   Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CFGR     ALIGN          LL_ADC_GetDataAlignment
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
+}
+
+/**
+  * @brief  Set ADC low power mode.
+  * @note   Description of ADC low power modes:
+  *         - ADC low power mode "auto wait": Dynamic low power mode,
+  *           ADC conversions occurrences are limited to the minimum necessary
+  *           in order to reduce power consumption.
+  *           New ADC conversion starts only when the previous
+  *           unitary conversion data (for ADC group regular)
+  *           or previous sequence conversions data (for ADC group injected)
+  *           has been retrieved by user software.
+  *           In the meantime, ADC remains idle: does not performs any
+  *           other conversion.
+  *           This mode allows to automatically adapt the ADC conversions
+  *           triggers to the speed of the software that reads the data.
+  *           Moreover, this avoids risk of overrun for low frequency
+  *           applications.
+  *           How to use this low power mode:
+  *           - It is not recommended to use with interruption or DMA
+  *             since these modes have to clear immediately the EOC flag
+  *             (by CPU to free the IRQ pending event or by DMA).
+  *             Auto wait will work but fort a very short time, discarding
+  *             its intended benefit (except specific case of high load of CPU
+  *             or DMA transfers which can justify usage of auto wait).
+  *           - Do use with polling: 1. Start conversion,
+  *             2. Later on, when conversion data is needed: poll for end of
+  *             conversion  to ensure that conversion is completed and
+  *             retrieve ADC conversion data. This will trig another
+  *             ADC conversion start.
+  *         - ADC low power mode "auto power-off" (feature available on
+  *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+  *           the ADC automatically powers-off after a conversion and
+  *           automatically wakes up when a new conversion is triggered
+  *           (with startup time between trigger and start of sampling).
+  *           This feature can be combined with low power mode "auto wait".
+  * @note   With ADC low power mode "auto wait", the ADC conversion data read
+  *         is corresponding to previous ADC conversion start, independently
+  *         of delay during which ADC was idle.
+  *         Therefore, the ADC conversion data may be outdated: does not
+  *         correspond to the current voltage level on the selected
+  *         ADC channel.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode
+  * @param  ADCx ADC instance
+  * @param  LowPowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_LP_MODE_NONE
+  *         @arg @ref LL_ADC_LP_AUTOWAIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
+}
+
+/**
+  * @brief  Get ADC low power mode:
+  * @note   Description of ADC low power modes:
+  *         - ADC low power mode "auto wait": Dynamic low power mode,
+  *           ADC conversions occurrences are limited to the minimum necessary
+  *           in order to reduce power consumption.
+  *           New ADC conversion starts only when the previous
+  *           unitary conversion data (for ADC group regular)
+  *           or previous sequence conversions data (for ADC group injected)
+  *           has been retrieved by user software.
+  *           In the meantime, ADC remains idle: does not performs any
+  *           other conversion.
+  *           This mode allows to automatically adapt the ADC conversions
+  *           triggers to the speed of the software that reads the data.
+  *           Moreover, this avoids risk of overrun for low frequency
+  *           applications.
+  *           How to use this low power mode:
+  *           - It is not recommended to use with interruption or DMA
+  *             since these modes have to clear immediately the EOC flag
+  *             (by CPU to free the IRQ pending event or by DMA).
+  *             Auto wait will work but fort a very short time, discarding
+  *             its intended benefit (except specific case of high load of CPU
+  *             or DMA transfers which can justify usage of auto wait).
+  *           - Do use with polling: 1. Start conversion,
+  *             2. Later on, when conversion data is needed: poll for end of
+  *             conversion  to ensure that conversion is completed and
+  *             retrieve ADC conversion data. This will trig another
+  *             ADC conversion start.
+  *         - ADC low power mode "auto power-off" (feature available on
+  *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+  *           the ADC automatically powers-off after a conversion and
+  *           automatically wakes up when a new conversion is triggered
+  *           (with startup time between trigger and start of sampling).
+  *           This feature can be combined with low power mode "auto wait".
+  * @note   With ADC low power mode "auto wait", the ADC conversion data read
+  *         is corresponding to previous ADC conversion start, independently
+  *         of delay during which ADC was idle.
+  *         Therefore, the ADC conversion data may be outdated: does not
+  *         correspond to the current voltage level on the selected
+  *         ADC channel.
+  * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_LP_MODE_NONE
+  *         @arg @ref LL_ADC_LP_AUTOWAIT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
+}
+
+/**
+  * @brief  Set ADC selected offset number 1, 2, 3 or 4.
+  * @note   This function set the 2 items of offset configuration:
+  *         - ADC channel to which the offset programmed will be applied
+  *           (independently of channel mapped on ADC group regular
+  *           or group injected)
+  *         - Offset level (offset to be subtracted from the raw
+  *           converted data).
+  * @note   Caution: Offset format is dependent to ADC resolution:
+  *         offset has to be left-aligned on bit 11, the LSB (right bits)
+  *         are set to 0.
+  * @note   This function enables the offset, by default. It can be forced
+  *         to disable state using function LL_ADC_SetOffsetState().
+  * @note   If a channel is mapped on several offsets numbers, only the offset
+  *         with the lowest value is considered for the subtraction.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @note   On STM32G4, some fast channels are available: fast analog inputs
+  *         coming from GPIO pads (ADC_IN1..5).
+  * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n
+  *         OFR1     OFFSET1        LL_ADC_SetOffset\n
+  *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n
+  *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n
+  *         OFR2     OFFSET2        LL_ADC_SetOffset\n
+  *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n
+  *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n
+  *         OFR3     OFFSET3        LL_ADC_SetOffset\n
+  *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n
+  *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n
+  *         OFR4     OFFSET4        LL_ADC_SetOffset\n
+  *         OFR4     OFFSET4_EN     LL_ADC_SetOffset
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  MODIFY_REG(*preg,
+             ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+             ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+}
+
+/**
+  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+  *         Channel to which the offset programmed will be applied
+  *         (independently of channel mapped on ADC group regular
+  *         or group injected)
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @note   On STM32G4, some fast channels are available: fast analog inputs
+  *         coming from GPIO pads (ADC_IN1..5).
+  * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n
+  *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n
+  *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n
+  *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
+}
+
+/**
+  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+  *         Offset level (offset to be subtracted from the raw
+  *         converted data).
+  * @note   Caution: Offset format is dependent to ADC resolution:
+  *         offset has to be left-aligned on bit 11, the LSB (right bits)
+  *         are set to 0.
+  * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
+  *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
+  *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
+  *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
+}
+
+/**
+  * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
+  *         force offset state disable or enable
+  *         without modifying offset channel or offset value.
+  * @note   This function should be needed only in case of offset to be
+  *         enabled-disabled dynamically, and should not be needed in other cases:
+  *         function LL_ADC_SetOffset() automatically enables the offset.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll OFR1     OFFSET1_EN     LL_ADC_SetOffsetState\n
+  *         OFR2     OFFSET2_EN     LL_ADC_SetOffsetState\n
+  *         OFR3     OFFSET3_EN     LL_ADC_SetOffsetState\n
+  *         OFR4     OFFSET4_EN     LL_ADC_SetOffsetState
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  OffsetState This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_DISABLE
+  *         @arg @ref LL_ADC_OFFSET_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  MODIFY_REG(*preg,
+             ADC_OFR1_OFFSET1_EN,
+             OffsetState);
+}
+
+/**
+  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+  *         offset state disabled or enabled.
+  * @rmtoll OFR1     OFFSET1_EN     LL_ADC_GetOffsetState\n
+  *         OFR2     OFFSET2_EN     LL_ADC_GetOffsetState\n
+  *         OFR3     OFFSET3_EN     LL_ADC_GetOffsetState\n
+  *         OFR4     OFFSET4_EN     LL_ADC_GetOffsetState
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_DISABLE
+  *         @arg @ref LL_ADC_OFFSET_ENABLE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
+}
+
+/**
+  * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
+  *         choose offset sign.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll OFR1     OFFSETPOS      LL_ADC_SetOffsetSign\n
+  *         OFR2     OFFSETPOS      LL_ADC_SetOffsetSign\n
+  *         OFR3     OFFSETPOS      LL_ADC_SetOffsetSign\n
+  *         OFR4     OFFSETPOS      LL_ADC_SetOffsetSign
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  OffsetSign This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+  *         @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  MODIFY_REG(*preg,
+             ADC_OFR1_OFFSETPOS,
+             OffsetSign);
+}
+
+/**
+  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+  *         offset sign if positive or negative.
+  * @rmtoll OFR1     OFFSETPOS      LL_ADC_GetOffsetSign\n
+  *         OFR2     OFFSETPOS      LL_ADC_GetOffsetSign\n
+  *         OFR3     OFFSETPOS      LL_ADC_GetOffsetSign\n
+  *         OFR4     OFFSETPOS      LL_ADC_GetOffsetSign
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+  *         @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
+}
+
+/**
+  * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
+  *         choose offset saturation mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll OFR1     SATEN          LL_ADC_SetOffsetSaturation\n
+  *         OFR2     SATEN          LL_ADC_SetOffsetSaturation\n
+  *         OFR3     SATEN          LL_ADC_SetOffsetSaturation\n
+  *         OFR4     SATEN          LL_ADC_SetOffsetSaturation
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  OffsetSaturation This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
+  *         @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  MODIFY_REG(*preg,
+             ADC_OFR1_SATEN,
+             OffsetSaturation);
+}
+
+/**
+  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+  *         offset saturation if enabled or disabled.
+  * @rmtoll OFR1     SATEN          LL_ADC_GetOffsetSaturation\n
+  *         OFR2     SATEN          LL_ADC_GetOffsetSaturation\n
+  *         OFR3     SATEN          LL_ADC_GetOffsetSaturation\n
+  *         OFR4     SATEN          LL_ADC_GetOffsetSaturation
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
+  *         @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN);
+}
+
+/**
+  * @brief  Set ADC gain compensation.
+  * @note   This function set the gain compensation coefficient
+  *         that is applied to raw converted data using the formula:
+  *           DATA = DATA(raw) * (gain compensation coef) / 4096
+  * @note   This function enables the gain compensation if given
+  *         coefficient is above 0, otherwise it disables it.
+  * @note   Gain compensation when enabled is applied to all channels.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll GCOMP    GCOMPCOEFF     LL_ADC_SetGainCompensation\n
+  *         CFGR2    GCOMP          LL_ADC_SetGainCompensation
+  * @param  ADCx ADC instance
+  * @param  GainCompensation This parameter can be:
+  *         0           Gain compensation will be disabled and value set to 0
+  *         1 -> 16393  Gain compensation will be enabled with specified value
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
+{
+  MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCOMP_Pos);
+}
+
+/**
+  * @brief  Get the ADC gain compensation value
+  * @rmtoll GCOMP    GCOMPCOEFF     LL_ADC_GetGainCompensation\n
+  *         CFGR2    GCOMP          LL_ADC_GetGainCompensation
+  * @param  ADCx ADC instance
+  * @retval Returned value can be:
+  *         0           Gain compensation is disabled
+  *         1 -> 16393  Gain compensation is enabled with returned value
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
+}
+
+#if defined(ADC_SMPR1_SMPPLUS)
+/**
+  * @brief  Set ADC sampling time common configuration impacting
+  *         settings of sampling time channel wise.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll SMPR1    SMPPLUS        LL_ADC_SetSamplingTimeCommonConfig
+  * @param  ADCx ADC instance
+  * @param  SamplingTimeCommonConfig This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
+{
+  MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
+}
+
+/**
+  * @brief  Get ADC sampling time common configuration impacting
+  *         settings of sampling time channel wise.
+  * @rmtoll SMPR1    SMPPLUS        LL_ADC_GetSamplingTimeCommonConfig
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
+}
+#endif /* ADC_SMPR1_SMPPLUS */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Set ADC group regular conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   On this STM32 series, setting trigger source to external trigger
+  *         also set trigger polarity to rising edge
+  *         (default setting for compatibility with some ADC on other
+  *         STM32 families having this setting set by HW default value).
+  *         In case of need to modify trigger edge, use
+  *         function @ref LL_ADC_REG_SetTriggerEdge().
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n
+  *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2       (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3       (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2      (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4      (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11     (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2      (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
+  *
+  *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+  *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   To determine whether group regular trigger source is
+  *         internal (SW start) or external, without detail
+  *         of which peripheral is selected as external trigger,
+  *         (equivalent to
+  *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+  *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n
+  *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2       (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3       (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2      (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4      (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11     (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2      (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
+  *
+  *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+  *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+  __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
+
+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+  /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */
+  uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+  /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */
+  /* to match with triggers literals definition.                              */
+  return ((TriggerSource
+           & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
+          | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
+         );
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source internal (SW start)
+  *         or external.
+  * @note   In case of group regular trigger source set to external trigger,
+  *         to determine which peripheral is selected as external trigger,
+  *         use function @ref LL_ADC_REG_GetTriggerSource().
+  * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
+  * @param  ADCx ADC instance
+  * @retval Value "0" if trigger source external trigger
+  *         Value "1" if trigger source SW start.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge
+  * @param  ADCx ADC instance
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
+}
+
+/**
+  * @brief  Set ADC sampling mode.
+  * @note   This function set the ADC conversion sampling mode
+  * @note   This mode applies to regular group only.
+  * @note   Set sampling mode is applied to all conversion of regular group.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR2    BULB           LL_ADC_REG_SetSamplingMode\n
+  *         CFGR2    SMPTRIG        LL_ADC_REG_SetSamplingMode
+  * @param  ADCx ADC instance
+  * @param  SamplingMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
+}
+
+/**
+  * @brief  Get the ADC sampling mode
+  * @rmtoll CFGR2    BULB           LL_ADC_REG_GetSamplingMode\n
+  *         CFGR2    SMPTRIG        LL_ADC_REG_GetSamplingMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
+}
+
+/**
+  * @brief  Set ADC group regular sequencer length and scan direction.
+  * @note   Description of ADC group regular sequencer features:
+  *         - For devices with sequencer fully configurable
+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are configurable.
+  *           This function performs configuration of:
+  *           - Sequence length: Number of ranks in the scan sequence.
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from rank 1 to rank n).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerRanks()".
+  *         - For devices with sequencer not fully configurable
+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are defined by channel number.
+  *           This function performs configuration of:
+  *           - Sequence length: Number of ranks in the scan sequence is
+  *             defined by number of channels set in the sequence,
+  *             rank of each channel is fixed by channel HW number.
+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from lowest channel number to
+  *             highest channel number).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerChannels()".
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
+  * @param  ADCx ADC instance
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+  MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer length and scan direction.
+  * @note   Description of ADC group regular sequencer features:
+  *         - For devices with sequencer fully configurable
+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are configurable.
+  *           This function retrieves:
+  *           - Sequence length: Number of ranks in the scan sequence.
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from rank 1 to rank n).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerRanks()".
+  *         - For devices with sequencer not fully configurable
+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are defined by channel number.
+  *           This function retrieves:
+  *           - Sequence length: Number of ranks in the scan sequence is
+  *             defined by number of channels set in the sequence,
+  *             rank of each channel is fixed by channel HW number.
+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from lowest channel number to
+  *             highest channel number).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerChannels()".
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+  * @brief  Set ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @note   It is not possible to enable both ADC group regular
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   It is not possible to enable both ADC auto-injected mode
+  *         and ADC group regular sequencer discontinuous mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n
+  *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @param  SeqDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n
+  *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
+}
+
+/**
+  * @brief  Set ADC group regular sequence: channel on the selected
+  *         scan sequence rank.
+  * @note   This function performs configuration of:
+  *         - Channels ordering into each rank of scan sequence:
+  *           whatever channel can be placed into whatever rank.
+  * @note   On this STM32 series, ADC group regular sequencer is
+  *         fully configurable: sequencer length and each rank
+  *         affectation to a channel are configurable.
+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_RANK_1
+  *         @arg @ref LL_ADC_REG_RANK_2
+  *         @arg @ref LL_ADC_REG_RANK_3
+  *         @arg @ref LL_ADC_REG_RANK_4
+  *         @arg @ref LL_ADC_REG_RANK_5
+  *         @arg @ref LL_ADC_REG_RANK_6
+  *         @arg @ref LL_ADC_REG_RANK_7
+  *         @arg @ref LL_ADC_REG_RANK_8
+  *         @arg @ref LL_ADC_REG_RANK_9
+  *         @arg @ref LL_ADC_REG_RANK_10
+  *         @arg @ref LL_ADC_REG_RANK_11
+  *         @arg @ref LL_ADC_REG_RANK_12
+  *         @arg @ref LL_ADC_REG_RANK_13
+  *         @arg @ref LL_ADC_REG_RANK_14
+  *         @arg @ref LL_ADC_REG_RANK_15
+  *         @arg @ref LL_ADC_REG_RANK_16
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+  /* Set bits with content of parameter "Channel" with bits position          */
+  /* in register and register position depending on parameter "Rank".         */
+  /* Parameters "Rank" and "Channel" are used with masks because containing   */
+  /* other bits reserved for other purpose.                                   */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+
+  MODIFY_REG(*preg,
+             ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+}
+
+/**
+  * @brief  Get ADC group regular sequence: channel on the selected
+  *         scan sequence rank.
+  * @note   On this STM32 series, ADC group regular sequencer is
+  *         fully configurable: sequencer length and each rank
+  *         affectation to a channel are configurable.
+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_RANK_1
+  *         @arg @ref LL_ADC_REG_RANK_2
+  *         @arg @ref LL_ADC_REG_RANK_3
+  *         @arg @ref LL_ADC_REG_RANK_4
+  *         @arg @ref LL_ADC_REG_RANK_5
+  *         @arg @ref LL_ADC_REG_RANK_6
+  *         @arg @ref LL_ADC_REG_RANK_7
+  *         @arg @ref LL_ADC_REG_RANK_8
+  *         @arg @ref LL_ADC_REG_RANK_9
+  *         @arg @ref LL_ADC_REG_RANK_10
+  *         @arg @ref LL_ADC_REG_RANK_11
+  *         @arg @ref LL_ADC_REG_RANK_12
+  *         @arg @ref LL_ADC_REG_RANK_13
+  *         @arg @ref LL_ADC_REG_RANK_14
+  *         @arg @ref LL_ADC_REG_RANK_15
+  *         @arg @ref LL_ADC_REG_RANK_16
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+
+  return (uint32_t)((READ_BIT(*preg,
+                              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+                     >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+                   );
+}
+
+/**
+  * @brief  Set ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @note   It is not possible to enable both ADC group regular
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode
+  * @param  ADCx ADC instance
+  * @param  Continuous This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
+}
+
+/**
+  * @brief  Get ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
+}
+
+/**
+  * @brief  Set ADC group regular conversion data transfer: no transfer or
+  *         transfer by DMA, and DMA requests mode.
+  * @note   If transfer by DMA selected, specifies the DMA requests
+  *         mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *        (overrun flag and interruption if enabled).
+  * @note   For devices with several ADC instances: ADC multimode DMA
+  *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_ADC_DMA_GetRegAddr().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     DMAEN          LL_ADC_REG_SetDMATransfer\n
+  *         CFGR     DMACFG         LL_ADC_REG_SetDMATransfer
+  * @param  ADCx ADC instance
+  * @param  DMATransfer This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data transfer: no transfer or
+  *         transfer by DMA, and DMA requests mode.
+  * @note   If transfer by DMA selected, specifies the DMA requests
+  *         mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   For devices with several ADC instances: ADC multimode DMA
+  *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_ADC_DMA_GetRegAddr().
+  * @rmtoll CFGR     DMAEN          LL_ADC_REG_GetDMATransfer\n
+  *         CFGR     DMACFG         LL_ADC_REG_GetDMATransfer
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
+}
+
+/**
+  * @brief  Set ADC group regular behavior in case of overrun:
+  *         data preserved or overwritten.
+  * @note   Compatibility with devices without feature overrun:
+  *         other devices without this feature have a behavior
+  *         equivalent to data overwritten.
+  *         The default setting of overrun is data preserved.
+  *         Therefore, for compatibility with all devices, parameter
+  *         overrun should be set to data overwritten.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun
+  * @param  ADCx ADC instance
+  * @param  Overrun This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
+}
+
+/**
+  * @brief  Get ADC group regular behavior in case of overrun:
+  *         data preserved or overwritten.
+  * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+  * @{
+  */
+
+/**
+  * @brief  Set ADC group injected conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   On this STM32 series, setting trigger source to external trigger
+  *         also set trigger polarity to rising edge
+  *         (default setting for compatibility with some ADC on other
+  *         STM32 families having this setting set by HW default value).
+  *         In case of need to modify trigger edge, use
+  *         function @ref LL_ADC_INJ_SetTriggerEdge().
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
+  *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+  *
+  *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+  *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   To determine whether group injected trigger source is
+  *         internal (SW start) or external, without detail
+  *         of which peripheral is selected as external trigger,
+  *         (equivalent to
+  *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+  *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
+  *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+  *
+  *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+  *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+  __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+
+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+  /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
+  uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+  /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
+  /* to match with triggers literals definition.                              */
+  return ((TriggerSource
+           & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
+          | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
+         );
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger source internal (SW start)
+            or external
+  * @note   In case of group injected trigger source set to external trigger,
+  *         to determine which peripheral is selected as external trigger,
+  *         use function @ref LL_ADC_INJ_GetTriggerSource.
+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
+  * @param  ADCx ADC instance
+  * @retval Value "0" if trigger source external trigger
+  *         Value "1" if trigger source SW start.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set ADC group injected conversion trigger polarity.
+  *         Applicable only for trigger source set to external trigger.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge
+  * @param  ADCx ADC instance
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger polarity.
+  *         Applicable only for trigger source set to external trigger.
+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
+}
+
+/**
+  * @brief  Set ADC group injected sequencer length and scan direction.
+  * @note   This function performs configuration of:
+  *         - Sequence length: Number of ranks in the scan sequence.
+  *         - Sequence direction: Unless specified in parameters, sequencer
+  *           scan direction is forward (from rank 1 to rank n).
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
+  * @param  ADCx ADC instance
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+  * @brief  Get ADC group injected sequencer length and scan direction.
+  * @note   This function retrieves:
+  *         - Sequence length: Number of ranks in the scan sequence.
+  *         - Sequence direction: Unless specified in parameters, sequencer
+  *           scan direction is forward (from rank 1 to rank n).
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+  * @brief  Set ADC group injected sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @note   It is not possible to enable both ADC group injected
+  *         auto-injected mode and sequencer discontinuous mode.
+  * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @param  SeqDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
+}
+
+/**
+  * @brief  Get ADC group injected sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
+}
+
+/**
+  * @brief  Set ADC group injected sequence: channel on the selected
+  *         sequence rank.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On STM32G4, some fast channels are available: fast analog inputs
+  *         coming from GPIO pads (ADC_IN1..5).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+  /* Set bits with content of parameter "Channel" with bits position          */
+  /* in register depending on parameter "Rank".                               */
+  /* Parameters "Rank" and "Channel" are used with masks because containing   */
+  /* other bits reserved for other purpose.                                   */
+  MODIFY_REG(ADCx->JSQR,
+             (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
+             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
+}
+
+/**
+  * @brief  Get ADC group injected sequence: channel on the selected
+  *         sequence rank.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n
+  *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n
+  *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n
+  *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  return (uint32_t)((READ_BIT(ADCx->JSQR,
+                              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+                     >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+                   );
+}
+
+/**
+  * @brief  Set ADC group injected conversion trigger:
+  *         independent or from ADC group regular.
+  * @note   This mode can be used to extend number of data registers
+  *         updated after one ADC conversion trigger and with data
+  *         permanently kept (not erased by successive conversions of scan of
+  *         ADC sequencer ranks), up to 5 data registers:
+  *         1 data register on ADC group regular, 4 data registers
+  *         on ADC group injected.
+  * @note   If ADC group injected injected trigger source is set to an
+  *         external trigger, this feature must be must be set to
+  *         independent trigger.
+  *         ADC group injected automatic trigger is compliant only with
+  *         group injected trigger source set to SW start, without any
+  *         further action on  ADC group injected conversion start or stop:
+  *         in this case, ADC group injected is controlled only
+  *         from ADC group regular.
+  * @note   It is not possible to enable both ADC group injected
+  *         auto-injected mode and sequencer discontinuous mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto
+  * @param  ADCx ADC instance
+  * @param  TrigAuto This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger:
+  *         independent or from ADC group regular.
+  * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
+}
+
+/**
+  * @brief  Set ADC group injected contexts queue mode.
+  * @note   A context is a setting of group injected sequencer:
+  *         - group injected trigger
+  *         - sequencer length
+  *         - sequencer ranks
+  *         If contexts queue is disabled:
+  *         - only 1 sequence can be configured
+  *           and is active perpetually.
+  *         If contexts queue is enabled:
+  *         - up to 2 contexts can be queued
+  *           and are checked in and out as a FIFO stack (first-in, first-out).
+  *         - If a new context is set when queues is full, error is triggered
+  *           by interruption "Injected Queue Overflow".
+  *         - Two behaviors are possible when all contexts have been processed:
+  *           the contexts queue can maintain the last context active perpetually
+  *           or can be empty and injected group triggers are disabled.
+  *         - Triggers can be only external (not internal SW start)
+  *         - Caution: The sequence must be fully configured in one time
+  *           (one write of register JSQR makes a check-in of a new context
+  *           into the queue).
+  *           Therefore functions to set separately injected trigger and
+  *           sequencer channels cannot be used, register JSQR must be set
+  *           using function @ref LL_ADC_INJ_ConfigQueueContext().
+  * @note   This parameter can be modified only when no conversion is on going
+  *         on either groups regular or injected.
+  * @note   A modification of the context mode (bit JQDIS) causes the contexts
+  *         queue to be flushed and the register JSQR is cleared.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n
+  *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode
+  * @param  ADCx ADC instance
+  * @param  QueueMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
+}
+
+/**
+  * @brief  Get ADC group injected context queue mode.
+  * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n
+  *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
+}
+
+/**
+  * @brief  Set one context on ADC group injected that will be checked in
+  *         contexts queue.
+  * @note   A context is a setting of group injected sequencer:
+  *         - group injected trigger
+  *         - sequencer length
+  *         - sequencer ranks
+  *         This function is intended to be used when contexts queue is enabled,
+  *         because the sequence must be fully configured in one time
+  *         (functions to set separately injected trigger and sequencer channels
+  *         cannot be used):
+  *         Refer to function @ref LL_ADC_INJ_SetQueueMode().
+  * @note   In the contexts queue, only the active context can be read.
+  *         The parameters of this function can be read using functions:
+  *         @arg @ref LL_ADC_INJ_GetTriggerSource()
+  *         @arg @ref LL_ADC_INJ_GetTriggerEdge()
+  *         @arg @ref LL_ADC_INJ_GetSequencerRanks()
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On STM32G4, some fast channels are available: fast analog inputs
+  *         coming from GPIO pads (ADC_IN1..5).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+  *
+  *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+  *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  *
+  *         Note: This parameter is discarded in case of SW start:
+  *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  * @param  Rank1_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @param  Rank2_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @param  Rank3_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @param  Rank4_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
+                                                   uint32_t TriggerSource,
+                                                   uint32_t ExternalTriggerEdge,
+                                                   uint32_t SequencerNbRanks,
+                                                   uint32_t Rank1_Channel,
+                                                   uint32_t Rank2_Channel,
+                                                   uint32_t Rank3_Channel,
+                                                   uint32_t Rank4_Channel)
+{
+  /* Set bits with content of parameter "Rankx_Channel" with bits position    */
+  /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */
+  /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */
+  /* because containing other bits reserved for other purpose.                */
+  /* If parameter "TriggerSource" is set to SW start, then parameter          */
+  /* "ExternalTriggerEdge" is discarded.                                      */
+  uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
+  MODIFY_REG(ADCx->JSQR,
+             ADC_JSQR_JEXTSEL |
+             ADC_JSQR_JEXTEN  |
+             ADC_JSQR_JSQ4    |
+             ADC_JSQR_JSQ3    |
+             ADC_JSQR_JSQ2    |
+             ADC_JSQR_JSQ1    |
+             ADC_JSQR_JL,
+             (TriggerSource & ADC_JSQR_JEXTSEL)          |
+             (ExternalTriggerEdge * (is_trigger_not_sw)) |
+             (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+             (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+             (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+             (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+             SequencerNbRanks
+            );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+  * @{
+  */
+
+/**
+  * @brief  Set sampling time of the selected ADC channel
+  *         Unit: ADC clock cycles.
+  * @note   On this device, sampling time is on channel scope: independently
+  *         of channel mapped on ADC group regular or injected.
+  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
+  *         converted:
+  *         sampling time constraints must be respected (sampling time can be
+  *         adjusted in function of ADC clock frequency and sampling time
+  *         setting).
+  *         Refer to device datasheet for timings values (parameters TS_vrefint,
+  *         TS_temp, ...).
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         On this STM32 series, ADC processing time is:
+  *         - 12.5 ADC clock cycles at ADC resolution 12 bits
+  *         - 10.5 ADC clock cycles at ADC resolution 10 bits
+  *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+  *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+  * @note   In case of ADC conversion of internal channel (VrefInt,
+  *         temperature sensor, ...), a sampling time minimum value
+  *         is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @param  SamplingTime This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)
+  *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
+  *
+  *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles
+  *             can be replaced by 3.5 ADC clock cycles.
+  *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+  /* Set bits with content of parameter "SamplingTime" with bits position     */
+  /* in register and register position depending on parameter "Channel".      */
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+
+  MODIFY_REG(*preg,
+             ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
+             SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
+}
+
+/**
+  * @brief  Get sampling time of the selected ADC channel
+  *         Unit: ADC clock cycles.
+  * @note   On this device, sampling time is on channel scope: independently
+  *         of channel mapped on ADC group regular or injected.
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         On this STM32 series, ADC processing time is:
+  *         - 12.5 ADC clock cycles at ADC resolution 12 bits
+  *         - 10.5 ADC clock cycles at ADC resolution 10 bits
+  *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+  *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+  * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)
+  *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
+  *
+  *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles
+  *             can be replaced by 3.5 ADC clock cycles.
+  *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+
+  return (uint32_t)(READ_BIT(*preg,
+                             ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
+                    >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
+                   );
+}
+
+/**
+  * @brief  Set mode single-ended or differential input of the selected
+  *         ADC channel.
+  * @note   Channel ending is on channel scope: independently of channel mapped
+  *         on ADC group regular or injected.
+  *         In differential mode: Differential measurement is carried out
+  *         between the selected channel 'i' (positive input) and
+  *         channel 'i+1' (negative input). Only channel 'i' has to be
+  *         configured, channel 'i+1' is configured automatically.
+  * @note   Refer to Reference Manual to ensure the selected channel is
+  *         available in differential mode.
+  *         For example, internal channels (VrefInt, TempSensor, ...) are
+  *         not available in differential mode.
+  * @note   When configuring a channel 'i' in differential mode,
+  *         the channel 'i+1' is not usable separately.
+  * @note   On STM32G4, some channels are internally fixed to single-ended inputs
+  *         configuration:
+  *         - ADC1: Channels 12, 15, 16, 17 and 18
+  *         - ADC2: Channels 15, 17 and 18
+  *         - ADC3: Channels 12, 16, 17 and 18            (1)
+  *         - ADC4: Channels 16, 17 and 18                (1)
+  *         - ADC5: Channels 2, 3, 4, 16, 17 and 18       (1)
+  *         (1) ADC3/4/5 are not available on all devices, refer to device datasheet
+  *             for more details.
+  * @note   For ADC channels configured in differential mode, both inputs
+  *         should be biased at (Vref+)/2 +/-200mV.
+  *         (Vref+ is the analog voltage reference)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll DIFSEL   DIFSEL         LL_ADC_SetChannelSingleDiff
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  * @param  SingleDiff This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
+{
+  /* Bits for single or differential mode selection for each channel are set  */
+  /* to 1 only when the differential mode is selected, and to 0 when the      */
+  /* single mode is selected.                                                 */
+  
+  if (SingleDiff == LL_ADC_DIFFERENTIAL_ENDED)
+  {
+    SET_BIT(ADCx->DIFSEL,
+            Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+  }
+  else
+  {
+    CLEAR_BIT(ADCx->DIFSEL,
+            Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+  }
+}
+
+/**
+  * @brief  Get mode single-ended or differential input of the selected
+  *         ADC channel.
+  * @note   When configuring a channel 'i' in differential mode,
+  *         the channel 'i+1' is not usable separately.
+  *         Therefore, to ensure a channel is configured in single-ended mode,
+  *         the configuration of channel itself and the channel 'i-1' must be
+  *         read back (to ensure that the selected channel channel has not been
+  *         configured in differential mode by the previous channel).
+  * @note   Refer to Reference Manual to ensure the selected channel is
+  *         available in differential mode.
+  *         For example, internal channels (VrefInt, TempSensor, ...) are
+  *         not available in differential mode.
+  * @note   When configuring a channel 'i' in differential mode,
+  *         the channel 'i+1' is not usable separately.
+  * @note   On STM32G4, some channels are internally fixed to single-ended inputs
+  *         configuration:
+  *         - ADC1: Channels 12, 15, 16, 17 and 18
+  *         - ADC2: Channels 15, 17 and 18
+  *         - ADC3: Channels 12, 16, 17 and 18            (1)
+  *         - ADC4: Channels 16, 17 and 18                (1)
+  *         - ADC5: Channels 2, 3, 4, 16, 17 and 18       (1)
+  *         (1) ADC3/4/5 are not available on all devices, refer to device datasheet
+  *             for more details.
+  * @note   One or several values can be selected. In this case, the value
+  *         returned is null if all channels are in single ended-mode.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSingleDiff
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  * @retval 0: channel in single-ended mode, else: channel in differential mode
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+  * @{
+  */
+
+/**
+  * @brief  Set ADC analog watchdog monitored channels:
+  *         a single channel, multiple channels or all channels,
+  *         on ADC groups regular and-or injected.
+  * @note   Once monitored channels are selected, analog watchdog
+  *         is enabled.
+  * @note   In case of need to define a single channel to monitor
+  *         with analog watchdog from sequencer channel definition,
+  *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+  * @note   On this STM32 series, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+  *             the 2 LSB are ignored.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n
+  *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
+  *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDChannelGroup This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG  (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ  (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG  (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ  (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(6)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(6)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (6)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ         (1)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ         (2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ    (2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     (0)(3)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     (0)(3)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ    (3)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ         (5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ         (5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG          (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ          (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ         (4)
+  *
+  *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
+{
+  /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
+  /* in register and register position depending on parameter "AWDy".         */
+  /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
+  /* containing other bits reserved for other purpose.                        */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+  MODIFY_REG(*preg,
+             (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+             AWDChannelGroup & AWDy);
+}
+
+/**
+  * @brief  Get ADC analog watchdog monitored channel.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Applicable only when the analog watchdog is set to monitor
+  *           one channel.
+  * @note   On this STM32 series, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+  *             the 2 LSB are ignored.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n
+  *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
+  *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2 (1)
+  *         @arg @ref LL_ADC_AWD3 (1)
+  *
+  *         (1) On this AWD number, monitored channel can be retrieved
+  *             if only 1 channel is programmed (or none or all channels).
+  *             This function cannot retrieve monitored channel if
+  *             multiple channels are programmed simultaneously
+  *             by bitfield.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *
+  *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+                                                   + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+  uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK);
+
+  /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */
+  /* (parameter value LL_ADC_AWD_DISABLE).                                    */
+  /* Else, the selected AWD is enabled and is monitoring a group of channels  */
+  /* or a single channel.                                                     */
+  if (AnalogWDMonitChannels != 0UL)
+  {
+    if (AWDy == LL_ADC_AWD1)
+    {
+      if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
+      {
+        /* AWD monitoring a group of channels */
+        AnalogWDMonitChannels = ((AnalogWDMonitChannels
+                                  | (ADC_AWD_CR23_CHANNEL_MASK)
+                                 )
+                                 & (~(ADC_CFGR_AWD1CH))
+                                );
+      }
+      else
+      {
+        /* AWD monitoring a single channel */
+        AnalogWDMonitChannels = (AnalogWDMonitChannels
+                                 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
+                                );
+      }
+    }
+    else
+    {
+      if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
+      {
+        /* AWD monitoring a group of channels */
+        AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
+                                 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
+                                );
+      }
+      else
+      {
+        /* AWD monitoring a single channel */
+        /* AWD monitoring a group of channels */
+        AnalogWDMonitChannels = (AnalogWDMonitChannels
+                                 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
+                                 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
+                                );
+      }
+    }
+  }
+
+  return AnalogWDMonitChannels;
+}
+
+/**
+  * @brief  Set ADC analog watchdog thresholds value of both thresholds
+  *         high and low.
+  * @note   If value of only one threshold high or low must be set,
+  *         use function @ref LL_ADC_SetAnalogWDThresholds().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @note   On this STM32 series, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+  *             the 2 LSB are ignored.
+  * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
+  *         impacted: the comparison of analog watchdog thresholds is done on
+  *         oversampling final computation (after ratio and shift application):
+  *         ADC data register bitfield [15:4] (12 most significant bits).
+  * @rmtoll TR1      HT1            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR2      HT2            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR3      HT3            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
+                                                     uint32_t AWDThresholdLowValue)
+{
+  /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
+  /* position in register and register position depending on parameter        */
+  /* "AWDy".                                                                  */
+  /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
+  /* containing other bits reserved for other purpose.                        */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+
+  MODIFY_REG(*preg,
+             ADC_TR1_HT1 | ADC_TR1_LT1,
+             (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
+}
+
+/**
+  * @brief  Set ADC analog watchdog threshold value of threshold
+  *         high or low.
+  * @note   If values of both thresholds high or low must be set,
+  *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @note   On this STM32 series, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+  *             the 2 LSB are ignored.
+  * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
+  *         impacted: the comparison of analog watchdog thresholds is done on
+  *         oversampling final computation (after ratio and shift application):
+  *         ADC data register bitfield [15:4] (12 most significant bits).
+  * @note   On this STM32 series, setting of this feature is not conditioned to
+  *         ADC state:
+  *         ADC can be disabled, enabled with or without conversion on going
+  *         on either ADC groups regular or injected.
+  * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n
+  *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n
+  *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n
+  *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n
+  *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n
+  *         TR3      LT3            LL_ADC_SetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
+                                                  uint32_t AWDThresholdValue)
+{
+  /* Set bits with content of parameter "AWDThresholdValue" with bits         */
+  /* position in register and register position depending on parameters       */
+  /* "AWDThresholdsHighLow" and "AWDy".                                       */
+  /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
+  /* containing other bits reserved for other purpose.                        */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+                                             ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+
+  MODIFY_REG(*preg,
+             AWDThresholdsHighLow,
+             AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
+}
+
+/**
+  * @brief  Get ADC analog watchdog threshold value of threshold high,
+  *         threshold low or raw data with ADC thresholds high and low
+  *         concatenated.
+  * @note   If raw data with ADC thresholds high and low is retrieved,
+  *         the data of each threshold high or low can be isolated
+  *         using helper macro:
+  *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+  * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n
+  *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n
+  *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n
+  *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n
+  *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n
+  *         TR3      LT3            LL_ADC_GetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+                                                   ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+
+  return (uint32_t)(READ_BIT(*preg,
+                             (AWDThresholdsHighLow | ADC_TR1_LT1))
+                    >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
+                        & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
+}
+
+/**
+  * @brief  Set ADC analog watchdog filtering configuration
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @note   On this STM32 series, this feature is only available on first
+  *         analog watchdog (AWD1)
+  * @rmtoll TR1      AWDFILT        LL_ADC_SetAWDFilteringConfiguration
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  * @param  FilteringConfig This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_FILTERING_NONE
+  *         @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
+{
+  /* Prevent unused argument(s) compilation warning */
+  (void)(AWDy);
+  MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
+}
+
+/**
+  * @brief  Get ADC analog watchdog filtering configuration
+  * @note   On this STM32 series, this feature is only available on first
+  *         analog watchdog (AWD1)
+  * @rmtoll TR1      AWDFILT        LL_ADC_GetAWDFilteringConfiguration
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  * @retval Returned value can be:
+  *         @arg @ref LL_ADC_AWD_FILTERING_NONE
+  *         @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+  /* Prevent unused argument(s) compilation warning */
+  (void)(AWDy);
+  return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
+  * @{
+  */
+
+/**
+  * @brief  Set ADC oversampling scope: ADC groups regular and-or injected
+  *         (availability of ADC group injected depends on STM32 families).
+  * @note   If both groups regular and injected are selected,
+  *         specify behavior of ADC group injected interrupting
+  *         group regular: when ADC group injected is triggered,
+  *         the oversampling on ADC group regular is either
+  *         temporary stopped and continued, or resumed from start
+  *         (oversampler buffer reset).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n
+  *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n
+  *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope
+  * @param  ADCx ADC instance
+  * @param  OvsScope This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_DISABLE
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+  *         @arg @ref LL_ADC_OVS_GRP_INJECTED
+  *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
+}
+
+/**
+  * @brief  Get ADC oversampling scope: ADC groups regular and-or injected
+  *         (availability of ADC group injected depends on STM32 families).
+  * @note   If both groups regular and injected are selected,
+  *         specify behavior of ADC group injected interrupting
+  *         group regular: when ADC group injected is triggered,
+  *         the oversampling on ADC group regular is either
+  *         temporary stopped and continued, or resumed from start
+  *         (oversampler buffer reset).
+  * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n
+  *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n
+  *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_DISABLE
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+  *         @arg @ref LL_ADC_OVS_GRP_INJECTED
+  *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
+}
+
+/**
+  * @brief  Set ADC oversampling discontinuous mode (triggered mode)
+  *         on the selected ADC group.
+  * @note   Number of oversampled conversions are done either in:
+  *         - continuous mode (all conversions of oversampling ratio
+  *           are done from 1 trigger)
+  *         - discontinuous mode (each conversion of oversampling ratio
+  *           needs a trigger)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @note   On this STM32 series, oversampling discontinuous mode
+  *         (triggered mode) can be used only when oversampling is
+  *         set on group regular only and in resumed mode.
+  * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont
+  * @param  ADCx ADC instance
+  * @param  OverSamplingDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_REG_CONT
+  *         @arg @ref LL_ADC_OVS_REG_DISCONT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
+}
+
+/**
+  * @brief  Get ADC oversampling discontinuous mode (triggered mode)
+  *         on the selected ADC group.
+  * @note   Number of oversampled conversions are done either in:
+  *         - continuous mode (all conversions of oversampling ratio
+  *           are done from 1 trigger)
+  *         - discontinuous mode (each conversion of oversampling ratio
+  *           needs a trigger)
+  * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_REG_CONT
+  *         @arg @ref LL_ADC_OVS_REG_DISCONT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
+}
+
+/**
+  * @brief  Set ADC oversampling
+  *         (impacting both ADC groups regular and injected)
+  * @note   This function set the 2 items of oversampling configuration:
+  *         - ratio
+  *         - shift
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
+  *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
+  * @param  ADCx ADC instance
+  * @param  Ratio This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_RATIO_2
+  *         @arg @ref LL_ADC_OVS_RATIO_4
+  *         @arg @ref LL_ADC_OVS_RATIO_8
+  *         @arg @ref LL_ADC_OVS_RATIO_16
+  *         @arg @ref LL_ADC_OVS_RATIO_32
+  *         @arg @ref LL_ADC_OVS_RATIO_64
+  *         @arg @ref LL_ADC_OVS_RATIO_128
+  *         @arg @ref LL_ADC_OVS_RATIO_256
+  * @param  Shift This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
+{
+  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
+}
+
+/**
+  * @brief  Get ADC oversampling ratio
+  *        (impacting both ADC groups regular and injected)
+  * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
+  * @param  ADCx ADC instance
+  * @retval Ratio This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_RATIO_2
+  *         @arg @ref LL_ADC_OVS_RATIO_4
+  *         @arg @ref LL_ADC_OVS_RATIO_8
+  *         @arg @ref LL_ADC_OVS_RATIO_16
+  *         @arg @ref LL_ADC_OVS_RATIO_32
+  *         @arg @ref LL_ADC_OVS_RATIO_64
+  *         @arg @ref LL_ADC_OVS_RATIO_128
+  *         @arg @ref LL_ADC_OVS_RATIO_256
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
+}
+
+/**
+  * @brief  Get ADC oversampling shift
+  *        (impacting both ADC groups regular and injected)
+  * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
+  * @param  ADCx ADC instance
+  * @retval Shift This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
+  * @{
+  */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Set ADC multimode configuration to operate in independent mode
+  *         or multimode (for devices with several ADC instances).
+  * @note   If multimode configuration: the selected ADC instance is
+  *         either master or slave depending on hardware.
+  *         Refer to reference manual.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      DUAL           LL_ADC_SetMultimode
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  Multimode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
+}
+
+/**
+  * @brief  Get ADC multimode configuration to operate in independent mode
+  *         or multimode (for devices with several ADC instances).
+  * @note   If multimode configuration: the selected ADC instance is
+  *         either master or slave depending on hardware.
+  *         Refer to reference manual.
+  * @rmtoll CCR      DUAL           LL_ADC_GetMultimode
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
+}
+
+/**
+  * @brief  Set ADC multimode conversion data transfer: no transfer
+  *         or transfer by DMA.
+  * @note   If ADC multimode transfer by DMA is not selected:
+  *         each ADC uses its own DMA channel, with its individual
+  *         DMA transfer settings.
+  *         If ADC multimode transfer by DMA is selected:
+  *         One DMA channel is used for both ADC (DMA of ADC master)
+  *         Specifies the DMA requests mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   How to retrieve multimode conversion data:
+  *         Whatever multimode transfer by DMA setting: using function
+  *         @ref LL_ADC_REG_ReadMultiConversionData32().
+  *         If ADC multimode transfer by DMA is selected: conversion data
+  *         is a raw data with ADC master and slave concatenated.
+  *         A macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled
+  *         or enabled without conversion on going on group regular.
+  * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\n
+  *         CCR      DMACFG         LL_ADC_SetMultiDMATransfer
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  MultiDMATransfer This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
+}
+
+/**
+  * @brief  Get ADC multimode conversion data transfer: no transfer
+  *         or transfer by DMA.
+  * @note   If ADC multimode transfer by DMA is not selected:
+  *         each ADC uses its own DMA channel, with its individual
+  *         DMA transfer settings.
+  *         If ADC multimode transfer by DMA is selected:
+  *         One DMA channel is used for both ADC (DMA of ADC master)
+  *         Specifies the DMA requests mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   How to retrieve multimode conversion data:
+  *         Whatever multimode transfer by DMA setting: using function
+  *         @ref LL_ADC_REG_ReadMultiConversionData32().
+  *         If ADC multimode transfer by DMA is selected: conversion data
+  *         is a raw data with ADC master and slave concatenated.
+  *         A macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\n
+  *         CCR      DMACFG         LL_ADC_GetMultiDMATransfer
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
+}
+
+/**
+  * @brief  Set ADC multimode delay between 2 sampling phases.
+  * @note   The sampling delay range depends on ADC resolution:
+  *         - ADC resolution 12 bits can have maximum delay of 12 cycles.
+  *         - ADC resolution 10 bits can have maximum delay of 10 cycles.
+  *         - ADC resolution  8 bits can have maximum delay of  8 cycles.
+  *         - ADC resolution  6 bits can have maximum delay of  6 cycles.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  MultiTwoSamplingDelay This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+  *
+  *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+  *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+  *         (3) Parameter available only if ADC resolution is 12 bits.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
+}
+
+/**
+  * @brief  Get ADC multimode delay between 2 sampling phases.
+  * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+  *
+  *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+  *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+  *         (3) Parameter available only if ADC resolution is 12 bits.
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Put ADC instance in deep power down state.
+  * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
+  *         state, the internal analog calibration is lost. After exiting from
+  *         deep power down, calibration must be relaunched or calibration factor
+  *         (preliminarily saved) must be set back into calibration register.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_DEEPPWD);
+}
+
+/**
+  * @brief  Disable ADC deep power down mode.
+  * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
+  *         state, the internal analog calibration is lost. After exiting from
+  *         deep power down, calibration must be relaunched or calibration factor
+  *         (preliminarily saved) must be set back into calibration register.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+  * @brief  Get the selected ADC instance deep power down state.
+  * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: deep power down is disabled, 1: deep power down is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable ADC instance internal voltage regulator.
+  * @note   On this STM32 series, after ADC internal voltage regulator enable,
+  *         a delay for ADC internal voltage regulator stabilization
+  *         is required before performing a ADC calibration or ADC enable.
+  *         Refer to device datasheet, parameter tADCVREG_STUP.
+  *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADVREGEN);
+}
+
+/**
+  * @brief  Disable ADC internal voltage regulator.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+  * @brief  Get the selected ADC instance internal voltage regulator state.
+  * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the selected ADC instance.
+  * @note   On this STM32 series, after ADC enable, a delay for
+  *         ADC internal analog stabilization is required before performing a
+  *         ADC conversion start.
+  *         Refer to device datasheet, parameter tSTAB.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
+  * @rmtoll CR       ADEN           LL_ADC_Enable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADEN);
+}
+
+/**
+  * @brief  Disable the selected ADC instance.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be not disabled. Must be enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CR       ADDIS          LL_ADC_Disable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADDIS);
+}
+
+/**
+  * @brief  Get the selected ADC instance enable state.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll CR       ADEN           LL_ADC_IsEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: ADC is disabled, 1: ADC is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the selected ADC instance disable state.
+  * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no ADC disable command on going.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Start ADC calibration in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   On this STM32 series, a minimum number of ADC clock cycles
+  *         are required between ADC end of calibration and ADC enable.
+  *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+  * @note   For devices with differential mode available:
+  *         Calibration of offset is specific to each of
+  *         single-ended and differential modes
+  *         (calibration run must be performed for each of these
+  *         differential modes, if used afterwards and if the application
+  *         requires their calibration).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n
+  *         CR       ADCALDIF       LL_ADC_StartCalibration
+  * @param  ADCx ADC instance
+  * @param  SingleDiff This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
+}
+
+/**
+  * @brief  Get ADC calibration state.
+  * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
+  * @param  ADCx ADC instance
+  * @retval 0: calibration complete, 1: calibration in progress.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Start ADC group regular conversion.
+  * @note   On this STM32 series, this function is relevant for both
+  *         internal trigger (SW start) and external trigger:
+  *         - If ADC trigger has been set to software start, ADC conversion
+  *           starts immediately.
+  *         - If ADC trigger has been set to external trigger, ADC conversion
+  *           will start at next trigger event (on the selected trigger edge)
+  *           following the ADC start conversion command.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group regular,
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADSTART);
+}
+
+/**
+  * @brief  Stop ADC group regular conversion.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled with conversion on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADSTP);
+}
+
+/**
+  * @brief  Get ADC group regular conversion state.
+  * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get ADC group regular command of conversion stop state
+  * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no command of conversion stop is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Start ADC sampling phase for sampling time trigger mode
+  * @note   This function is relevant only when
+  *         - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+  *           using @ref LL_ADC_REG_SetSamplingMode
+  *         - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group regular,
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CFGR2    SWTRIG         LL_ADC_REG_StartSamplingPhase
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+}
+
+/**
+  * @brief  Stop ADC sampling phase for sampling time trigger mode and start conversion
+  * @note   This function is relevant only when
+  *         - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+  *           using @ref LL_ADC_REG_SetSamplingMode
+  *         - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+  *         - @ref LL_ADC_REG_StartSamplingPhase has been called to start
+  *           the sampling phase
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group regular,
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CFGR2    SWTRIG         LL_ADC_REG_StopSamplingPhase
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         all ADC configurations: all ADC resolutions and
+  *         all oversampling increased data width (for devices
+  *         with feature oversampling).
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 12 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 10 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 8 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 6 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Get ADC multimode conversion data of ADC master, ADC slave
+  *         or raw data with ADC master and slave concatenated.
+  * @note   If raw data with ADC master and slave concatenated is retrieved,
+  *         a macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  *         (however this macro is mainly intended for multimode
+  *         transfer by DMA, because this function can do the same
+  *         by getting multimode conversion data of ADC master or ADC slave
+  *         separately).
+  * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n
+  *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  ConversionData This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_MASTER
+  *         @arg @ref LL_ADC_MULTI_SLAVE
+  *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
+                             ConversionData)
+                    >> (POSITION_VAL(ConversionData) & 0x1FUL)
+                   );
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+  * @{
+  */
+
+/**
+  * @brief  Start ADC group injected conversion.
+  * @note   On this STM32 series, this function is relevant for both
+  *         internal trigger (SW start) and external trigger:
+  *         - If ADC trigger has been set to software start, ADC conversion
+  *           starts immediately.
+  *         - If ADC trigger has been set to external trigger, ADC conversion
+  *           will start at next trigger event (on the selected trigger edge)
+  *           following the ADC start conversion command.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group injected,
+  *         without conversion stop command on going on group injected,
+  *         without ADC disable command on going.
+  * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_JADSTART);
+}
+
+/**
+  * @brief  Stop ADC group injected conversion.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled with conversion on going on group injected,
+  *         without ADC disable command on going.
+  * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_JADSTP);
+}
+
+/**
+  * @brief  Get ADC group injected conversion state.
+  * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group injected.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get ADC group injected command of conversion stop state
+  * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no command of conversion stop is on going on ADC group injected.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         all ADC configurations: all ADC resolutions and
+  *         all oversampling increased data width (for devices
+  *         with feature oversampling).
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint32_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 12 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint16_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 10 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint16_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 8 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint8_t)(READ_BIT(*preg,
+                            ADC_JDR1_JDATA)
+                  );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 6 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint8_t)(READ_BIT(*preg,
+                            ADC_JDR1_JDATA)
+                  );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+  * @{
+  */
+
+/**
+  * @brief  Get flag ADC ready.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular end of unitary conversion.
+  * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular end of sequence conversions.
+  * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular overrun.
+  * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular end of sampling phase.
+  * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group injected end of unitary conversion.
+  * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group injected end of sequence conversions.
+  * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group injected contexts queue overflow.
+  * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 1 flag
+  * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 2.
+  * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 3.
+  * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear flag ADC ready.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of unitary conversion.
+  * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of sequence conversions.
+  * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
+}
+
+/**
+  * @brief  Clear flag ADC group regular overrun.
+  * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of sampling phase.
+  * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
+}
+
+/**
+  * @brief  Clear flag ADC group injected end of unitary conversion.
+  * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
+}
+
+/**
+  * @brief  Clear flag ADC group injected end of sequence conversions.
+  * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
+}
+
+/**
+  * @brief  Clear flag ADC group injected contexts queue overflow.
+  * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 1.
+  * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 2.
+  * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 3.
+  * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Get flag multimode ADC ready of the ADC master.
+  * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC ready of the ADC slave.
+  * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.
+  * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
+  * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.
+  * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
+  * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular overrun of the ADC master.
+  * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular overrun of the ADC slave.
+  * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.
+  * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.
+  * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.
+  * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
+  * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.
+  * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
+  * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.
+  * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.
+  * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.
+  * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode analog watchdog 1 of the ADC slave.
+  * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.
+  * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.
+  * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.
+  * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.
+  * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of sequence conversions.
+  * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+  * @brief  Enable ADC group regular interruption overrun.
+  * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of sampling.
+  * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+  * @brief  Enable interruption ADC group injected end of unitary conversion.
+  * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+  * @brief  Enable interruption ADC group injected end of sequence conversions.
+  * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+  * @brief  Enable interruption ADC group injected context queue overflow.
+  * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 1.
+  * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 2.
+  * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 3.
+  * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+  * @brief  Disable interruption ADC ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of sequence conversions.
+  * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular overrun.
+  * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of sampling.
+  * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+  * @brief  Disable interruption ADC group injected end of sequence conversions.
+  * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+  * @brief  Disable interruption ADC group injected context queue overflow.
+  * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 1.
+  * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 2.
+  * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 3.
+  * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+  * @brief  Get state of interruption ADC ready
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of unitary conversion
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of sequence conversions
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular overrun
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of sampling
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group injected end of unitary conversion
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group injected end of sequence conversions
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group injected context queue overflow interrupt state
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC analog watchdog 1
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption Get ADC analog watchdog 2
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption Get ADC analog watchdog 3
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 families) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
+void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_ADC_H */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h
new file mode 100644
index 0000000..8641c9f
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h
@@ -0,0 +1,1680 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_bus.h
+  * @author  MCD Application Team
+  * @brief   Header file of BUS LL module.
+
+  @verbatim
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+        (++) AHB & APB peripherals, 1 dummy read is necessary
+
+    [..]
+      Workarounds:
+      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_BUS_H
+#define STM32G4xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  * @{
+  */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN
+#define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN
+#define LL_AHB1_GRP1_PERIPH_DMAMUX1        RCC_AHB1ENR_DMAMUX1EN
+#define LL_AHB1_GRP1_PERIPH_CORDIC         RCC_AHB1ENR_CORDICEN
+#define LL_AHB1_GRP1_PERIPH_FMAC           RCC_AHB1ENR_FMACEN
+#define LL_AHB1_GRP1_PERIPH_FLASH          RCC_AHB1ENR_FLASHEN
+#define LL_AHB1_GRP1_PERIPH_SRAM1          RCC_AHB1SMENR_SRAM1SMEN
+#define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#define LL_AHB2_GRP1_PERIPH_GPIOA          RCC_AHB2ENR_GPIOAEN
+#define LL_AHB2_GRP1_PERIPH_GPIOB          RCC_AHB2ENR_GPIOBEN
+#define LL_AHB2_GRP1_PERIPH_GPIOC          RCC_AHB2ENR_GPIOCEN
+#define LL_AHB2_GRP1_PERIPH_GPIOD          RCC_AHB2ENR_GPIODEN
+#define LL_AHB2_GRP1_PERIPH_GPIOE          RCC_AHB2ENR_GPIOEEN
+#define LL_AHB2_GRP1_PERIPH_GPIOF          RCC_AHB2ENR_GPIOFEN
+#define LL_AHB2_GRP1_PERIPH_GPIOG          RCC_AHB2ENR_GPIOGEN
+#define LL_AHB2_GRP1_PERIPH_CCM            RCC_AHB2SMENR_CCMSMEN
+#define LL_AHB2_GRP1_PERIPH_SRAM2          RCC_AHB2SMENR_SRAM2SMEN
+#define LL_AHB2_GRP1_PERIPH_ADC12          RCC_AHB2ENR_ADC12EN
+#if defined(ADC345_COMMON)
+#define LL_AHB2_GRP1_PERIPH_ADC345         RCC_AHB2ENR_ADC345EN
+#endif /* ADC345_COMMON */
+#define LL_AHB2_GRP1_PERIPH_DAC1           RCC_AHB2ENR_DAC1EN
+#if defined(DAC2)
+#define LL_AHB2_GRP1_PERIPH_DAC2           RCC_AHB2ENR_DAC2EN
+#endif /* DAC2 */
+#define LL_AHB2_GRP1_PERIPH_DAC3           RCC_AHB2ENR_DAC3EN
+#if defined(DAC4)
+#define LL_AHB2_GRP1_PERIPH_DAC4           RCC_AHB2ENR_DAC4EN
+#endif /* DAC4 */
+#if defined(AES)
+#define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
+#endif /* AES */
+#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#if defined(FMC_Bank1_R)
+#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+#endif /* FMC_Bank1_R */
+#if defined(QUADSPI)
+#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+#endif /* QUADSPI */
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR1_TIM2EN
+#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR1_TIM3EN
+#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR1_TIM4EN
+#if defined(TIM5)
+#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR1_TIM5EN
+#endif /* TIM5 */
+#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR1_TIM6EN
+#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR1_TIM7EN
+#define LL_APB1_GRP1_PERIPH_CRS            RCC_APB1ENR1_CRSEN
+#define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR1_RTCAPBEN
+#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR1_WWDGEN
+#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR1_SPI2EN
+#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR1_SPI3EN
+#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR1_USART2EN
+#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR1_USART3EN
+#if defined(UART4)
+#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR1_UART4EN
+#endif /* UART4 */
+#if defined(UART5)
+#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR1_UART5EN
+#endif /* UART5 */
+#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR1_I2C1EN
+#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR1_I2C2EN
+#define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR1_USBEN
+#if defined(FDCAN1)
+#define LL_APB1_GRP1_PERIPH_FDCAN          RCC_APB1ENR1_FDCANEN
+#endif /* FDCAN1 */
+#define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR1_PWREN
+#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR1_I2C3EN
+#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR1_LPTIM1EN
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP2_PERIPH_ALL            0xFFFFFFFFU
+#define LL_APB1_GRP2_PERIPH_LPUART1        RCC_APB1ENR2_LPUART1EN
+#if defined(I2C4)
+#define LL_APB1_GRP2_PERIPH_I2C4           RCC_APB1ENR2_I2C4EN
+#endif /* I2C4 */
+#define LL_APB1_GRP2_PERIPH_UCPD1         RCC_APB1ENR2_UCPD1EN
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APB2ENR_SYSCFGEN
+#define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
+#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
+#define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN
+#define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
+#if defined(SPI4)
+#define LL_APB2_GRP1_PERIPH_SPI4           RCC_APB2ENR_SPI4EN
+#endif /* SPI4 */
+#define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN
+#define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
+#define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
+#if defined(TIM20)
+#define LL_APB2_GRP1_PERIPH_TIM20          RCC_APB2ENR_TIM20EN
+#endif /* TIM20 */
+#define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN
+#if defined(HRTIM1)
+#define LL_APB2_GRP1_PERIPH_HRTIM1         RCC_APB2ENR_HRTIM1EN
+#endif /* HRTIM1 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+  * @{
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMAMMUXEN     LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CORDICEN      LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      FMACEN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMAMUXEN      LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      CORDICEN      LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      FMACEN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  * @retval State of Periphs (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMAMUXEN      LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      CORDICEN      LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      FMACEN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMAMUXRST     LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     CORDICRST     LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     FMACRST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     FLASHRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMAMUXRST     LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     CORDICRST     LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     FMACRST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     FLASHRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB1 peripheral clocks in Sleep and Stop modes
+  * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
+  *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
+  *         AHB1SMENR    DMAMUXSMEN    LL_AHB1_GRP1_EnableClockStopSleep\n
+  *         AHB1SMENR    CORDICSMEN    LL_AHB1_GRP1_EnableClockStopSleep\n
+  *         AHB1SMENR    FMACSMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
+  *         AHB1SMENR    FLASHSMEN     LL_AHB1_GRP1_EnableClockStopSleep\n
+  *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_EnableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1SMENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB1 peripheral clocks in Sleep and Stop modes
+  * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    DMAMUXSMEN    LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    CORDICSMEN    LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    FMACSMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    FLASHSMEN     LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_DisableClockStopSleep\n
+  *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_DisableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1SMENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      ADC12EN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      ADC345EN      LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      DAC1EN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      DAC2EN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      DAC3EN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      DAC4EN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      AESEN         LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      ADC12EN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      ADC345EN      LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      DAC1EN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      DAC2EN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      DAC3EN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      DAC4EN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      AESEN         LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      ADC12EN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      ADC345EN      LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      DAC1EN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      DAC2EN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      DAC3EN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      DAC4EN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      AESEN         LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR      GPIOARST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      GPIOBRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      GPIOCRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      GPIODRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      GPIOERST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      GPIOFRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      GPIOGRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      ADC12RST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      ADC345RST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      DAC1RST        LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      DAC2RST        LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      DAC3RST        LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      DAC4RST        LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      AESRST         LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR      RNGRST         LL_AHB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR      GPIOARST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      GPIOBRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      GPIOCRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      GPIODRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      GPIOERST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      GPIOFRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      GPIOGRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      ADC12RST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      ADC345RST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      DAC1RST        LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      DAC2RST        LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      DAC3RST        LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      DAC4RST        LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      AESRST         LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR      RNGRST         LL_AHB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB2 peripheral clocks in Sleep and Stop modes
+  * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIOFSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    GPIOGSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    SRAM2SMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    CCMSMEN       LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    ADC12SMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    ADC345SMEN    LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    DAC1SMEN      LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    DAC2SMEN      LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    DAC3SMEN      LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    DAC4SMEN      LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    AESSMEN       LL_AHB2_GRP1_EnableClockStopSleep\n
+  *         AHB2SMENR    RNGSMEN       LL_AHB2_GRP1_EnableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CCM
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2SMENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB2 peripheral clocks in Sleep and Stop modes
+  * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIOFSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    GPIOGSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    SRAM2SMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    CCMSMEN       LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    ADC12SMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    ADC345SMEN    LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    DAC1SMEN      LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    DAC2SMEN      LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    DAC3SMEN      LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    DAC4SMEN      LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    AESSMEN       LL_AHB2_GRP1_DisableClockStopSleep\n
+  *         AHB2SMENR    RNGSMEN       LL_AHB2_GRP1_DisableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CCM
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2SMENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB3 peripheral clocks in Sleep and Stop modes
+  * @rmtoll AHB3SMENR    FMCSMEN       LL_AHB3_GRP1_EnableClockStopSleep\n
+  *         AHB3SMENR    QSPISMEN      LL_AHB3_GRP1_EnableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3SMENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB3 peripheral clocks in Sleep and Stop modes
+  * @rmtoll AHB3SMENR    FMCSMEN       LL_AHB3_GRP1_DisableClockStopSleep\n
+  *         AHB3SMENR    QSPISMEN      LL_AHB3_GRP1_DisableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3SMENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     TIM3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     TIM4EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     TIM5EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     TIM6EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     TIM7EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     CRSEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     WWDGEN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     SPI2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     SPI3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     USART2EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     USART3EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     UART4EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     UART5EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     I2C1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     I2C2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     USBEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     FDCANEN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     PWREN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     I2C3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1ENR1, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_EnableClock\n
+  *         APB1ENR2     I2C4EN        LL_APB1_GRP2_EnableClock\n
+  *         APB1ENR2     UCPD1EN       LL_APB1_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1ENR2, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     CRSEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     USBEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     FDCANEN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     PWREN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1ENR2     I2C4EN        LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1ENR2     UCPD1EN       LL_APB1_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     TIM3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     TIM4EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     TIM5EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     TIM6EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     TIM7EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     CRSEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     WWDGEN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     SPI2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     SPI3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     USART2EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     USART3EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     UART4EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     UART5EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     I2C1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     I2C2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     USBEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     FDCANEN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     PWREN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     I2C3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1ENR1, Periphs);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_DisableClock\n
+  *         APB1ENR2     I2C4EN        LL_APB1_GRP2_DisableClock\n
+  *         APB1ENR2     UCPD1EN      LL_APB1_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1ENR2, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1RSTR1     TIM2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     TIM3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     TIM4RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     TIM5RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     TIM6RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     TIM7RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     CRSRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     SPI2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     SPI3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     USART2RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     USART3RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     UART4RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     UART5RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     I2C1RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     I2C2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     USBRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     FDCANRST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     PWRRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     I2C3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR1     LPTIM1RST      LL_APB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1RSTR1, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1RSTR2     LPUART1RST     LL_APB1_GRP2_ForceReset\n
+  *         APB1RSTR2     I2C4RST        LL_APB1_GRP2_ForceReset\n
+  *         APB1RSTR2     UCPD1RST       LL_APB1_GRP2_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1RSTR2, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1RSTR1     TIM2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     TIM3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     TIM4RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     TIM5RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     TIM6RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     TIM7RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     CRSRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     SPI2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     SPI3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     USART2RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     USART3RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     UART4RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     UART5RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     I2C1RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     I2C2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     USBRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     FDCANRST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     PWRRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     I2C3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR1     LPTIM1RST      LL_APB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1RSTR1, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1RSTR2     LPUART1RST     LL_APB1_GRP2_ReleaseReset\n
+  *         APB1RSTR2     I2C4RST        LL_APB1_GRP2_ReleaseReset\n
+  *         APB1RSTR2     UCPD1RST       LL_APB1_GRP2_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1RSTR2, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripheral clocks in Sleep and Stop modes
+  * @rmtoll APB1SMENR1     TIM2SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     TIM3SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     TIM4SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     TIM5SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     TIM6SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     TIM7SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     CRSSMEN         LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     RTCAPBSMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     WWDGSMEN        LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     SPI2SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     SPI3SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     USART2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     USART3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     UART4SMEN       LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     UART5SMEN       LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     I2C1SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     I2C2SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     USBSMEN         LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     FDCANSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     PWRSMEN         LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     I2C3SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
+  *         APB1SMENR1     LPTIM1SMEN      LL_APB1_GRP1_EnableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1SMENR1, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Enable APB1 peripheral clocks in Sleep and Stop modes
+  * @rmtoll APB1SMENR2     LPUART1SMEN     LL_APB1_GRP2_EnableClockStopSleep\n
+  *         APB1SMENR2     I2C4SMEN        LL_APB1_GRP2_EnableClockStopSleep\n
+  *         APB1SMENR2     UCPD1SMEN       LL_APB1_GRP2_EnableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1SMENR2, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB1 peripheral clocks in Sleep and Stop modes
+  * @rmtoll APB1SMENR1     TIM2SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     TIM3SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     TIM4SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     TIM5SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     TIM6SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     TIM7SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     CRSSMEN         LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     RTCAPBSMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     WWDGSMEN        LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     SPI2SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     SPI3SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     USART2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     USART3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     UART4SMEN       LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     UART5SMEN       LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     I2C1SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     I2C2SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     USBSMEN         LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     FDCANSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     PWRSMEN         LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     I2C3SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
+  *         APB1SMENR1     LPTIM1SMEN      LL_APB1_GRP1_DisableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1SMENR1, Periphs);
+}
+
+/**
+  * @brief  Disable APB1 peripheral clocks in Sleep and Stop modes
+  * @rmtoll APB1SMENR2     LPUART1SMEN     LL_APB1_GRP2_DisableClockStopSleep\n
+  *         APB1SMENR2     I2C4SMEN        LL_APB1_GRP2_DisableClockStopSleep\n
+  *         APB1SMENR2     UCPD1SMEN      LL_APB1_GRP2_DisableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1SMENR2, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable APB2 peripherals clock.
+  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM20EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      HRTIM1EN      LL_APB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM20EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      HRTIM1EN      LL_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock.
+  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM20EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      HRTIM1EN      LL_APB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB2 peripherals reset.
+  * @rmtoll APB2RSTR      SYSCFGRST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      TIM1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      SPI1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      TIM8RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      USART1RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      SPI4RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      TIM15RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      TIM16RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      TIM17RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      TIM20RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      SAI1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      HRTIM1RST      LL_APB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB2 peripherals reset.
+  * @rmtoll APB2RSTR      SYSCFGRST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      TIM1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      SPI1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      TIM8RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      USART1RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      SPI4RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      TIM15RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      TIM16RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      TIM17RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      TIM20RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      SAI1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR      HRTIM1RST      LL_APB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB2 peripheral clocks in Sleep and Stop modes
+  * @rmtoll APB2SMENR      SYSCFGSMEN      LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR      TIM1SMEN        LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR      SPI1SMEN        LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR      TIM8SMEN        LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR      USART1SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR      SPI4SMEN        LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR      TIM15SMEN       LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR      TIM16SMEN       LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR      TIM17SMEN       LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR      TIM20SMEN       LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR      SAI1SMEN        LL_APB2_GRP1_EnableClockStopSleep\n
+  *         APB2SMENR      HRTIM1SMEN      LL_APB2_GRP1_EnableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2SMENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB2 peripheral clocks in Sleep and Stop modes
+  * @rmtoll APB2SMENR      SYSCFGSMEN      LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR      TIM1SMEN        LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR      SPI1SMEN        LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR      TIM8SMEN        LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR      USART1SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR      SPI4SMEN        LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR      TIM15SMEN       LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR      TIM16SMEN       LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR      TIM17SMEN       LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR      TIM20SMEN       LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR      SAI1SMEN        LL_APB2_GRP1_DisableClockStopSleep\n
+  *         APB2SMENR      HRTIM1SMEN      LL_APB2_GRP1_DisableClockStopSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2SMENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_BUS_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h
new file mode 100644
index 0000000..a0283f2
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h
@@ -0,0 +1,637 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL CORTEX driver contains a set of generic APIs that can be
+    used by user:
+      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
+          functions
+      (+) Low power mode configuration (SCB register of Cortex-MCU)
+      (+) MPU API to configure and enable regions
+      (+) API to access to MCU info (CPUID register)
+      (+) API to enable fault handler (SHCSR accesses)
+
+  @endverbatim
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_CORTEX_H
+#define __STM32G4xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX_LL CORTEX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+  * @{
+  */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+  * @{
+  */
+#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+  * @{
+  */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+  * @{
+  */
+#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+  * @{
+  */
+#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+  * @{
+  */
+#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+  * @{
+  */
+#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+  * @{
+  */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+  * @{
+  */
+
+/**
+  * @brief  This function checks if the Systick counter flag is active or not.
+  * @note   It can be used in timeout function on application side.
+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+  return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configures the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+  {
+    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+  else
+  {
+    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+}
+
+/**
+  * @brief  Get the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+  * @brief  Enable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Disable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+  return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+  * @{
+  */
+
+/**
+  * @brief  Processor uses sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Processor uses deep sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+  *         empty main application.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Do not sleep when returning to Thread mode.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
+  *         processor.
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+  /* Set SEVEONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+  *         excluded
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+  /* Clear SEVEONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+  * @{
+  */
+
+/**
+  * @brief  Enable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+  /* Enable the system handler fault */
+  SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @brief  Disable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+  /* Disable the system handler fault */
+  CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+  * @{
+  */
+
+/**
+  * @brief  Get Implementer code
+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
+  * @retval Value should be equal to 0x41 for ARM
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
+  * @retval Value between 0 and 255 (0x0: revision 0)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+  * @brief  Get Architecture number 
+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetArchitecture
+  * @retval Value should be equal to 0xF for Cortex-M4 devices
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+  * @brief  Get Part number
+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
+  * @retval Value should be equal to 0xC24 for Cortex-M4
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
+  * @retval Value between 0 and 255 (0x1: patch 1)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+  * @{
+  */
+
+/**
+  * @brief  Enable MPU with input options
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
+  * @param  Options This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+  /* Enable the MPU*/
+  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+  /* Ensure MPU settings take effects */
+  __DSB();
+  /* Sequence instruction fetches using update settings */
+  __ISB();
+}
+
+/**
+  * @brief  Disable MPU
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+  /* Disable MPU*/
+  WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+  * @brief  Check if MPU is enabled or not
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+  return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable a MPU region
+  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Enable the MPU region */
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Configure and enable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
+  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @param  Address Value of region base address
+  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Set base address */
+  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+  /* Configure MPU */
+  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
+}
+
+/**
+  * @brief  Disable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
+  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Disable the MPU region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @}
+  */
+
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_CORTEX_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h
new file mode 100644
index 0000000..054d572
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h
@@ -0,0 +1,781 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_crs.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRS LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_CRS_H
+#define __STM32G4xx_LL_CRS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
+  * @{
+  */
+
+/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_CRS_ReadReg function
+  * @{
+  */
+#define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
+#define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
+#define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
+#define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
+#define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
+#define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
+#define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
+  * @{
+  */
+#define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
+#define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
+#define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
+#define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
+  * @{
+  */
+#define LL_CRS_SYNC_DIV_1                  ((uint32_t)0x00U)                         /*!< Synchro Signal not divided (default) */
+#define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
+#define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
+#define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
+  * @{
+  */
+#define LL_CRS_SYNC_SOURCE_GPIO            ((uint32_t)0x00U)       /*!< Synchro Signal source GPIO */
+#define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
+#define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
+  * @{
+  */
+#define LL_CRS_SYNC_POLARITY_RISING        ((uint32_t)0x00U)     /*!< Synchro Active on rising edge (default) */
+#define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
+  * @{
+  */
+#define LL_CRS_FREQ_ERROR_DIR_UP             ((uint32_t)0x00U)         /*!< Upcounting direction, the actual frequency is above the target */
+#define LL_CRS_FREQ_ERROR_DIR_DOWN           ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
+  * @{
+  */
+/**
+  * @brief Reset value of the RELOAD field
+  * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
+  *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
+  */
+#define LL_CRS_RELOADVALUE_DEFAULT         ((uint32_t)0xBB7FU)
+
+/**
+  * @brief Reset value of Frequency error limit.
+  */
+#define LL_CRS_ERRORLIMIT_DEFAULT          ((uint32_t)0x22U)
+
+/**
+  * @brief Reset value of the HSI48 Calibration field
+  * @note The default value is 64, which corresponds to the middle of the trimming interval.
+  *       The trimming step is specified in the product datasheet.
+  *       A higher TRIM value corresponds to a higher output frequency
+  */
+#define LL_CRS_HSI48CALIBRATION_DEFAULT    ((uint32_t)0x40U)
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
+  * @{
+  */
+
+/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
+  * @{
+  */
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between
+  *         the target frequency and the frequency of the synchronization source after
+  *         prescaling. It is then decreased by one in order to reach the expected
+  *         synchronization on the zero value. The formula is the following:
+  *              RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval Reload value (in Hz)
+  */
+#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
+  * @{
+  */
+
+/** @defgroup CRS_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable Frequency error counter
+  * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
+  * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Disable Frequency error counter
+  * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Check if Frequency error counter is enabled or not
+  * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Disable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Check if Automatic trimming is enabled or not
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set HSI48 oscillator smooth trimming
+  * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
+  * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
+  * @param  Value a number between Min_Data = 0 and Max_Data = 63
+  * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
+}
+
+/**
+  * @brief  Get HSI48 oscillator smooth trimming
+  * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
+  * @retval a number between Min_Data = 0 and Max_Data = 63
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+}
+
+/**
+  * @brief  Set counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
+  * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
+  *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
+}
+
+/**
+  * @brief  Get counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
+  * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+}
+
+/**
+  * @brief  Set frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
+  * @param  Value a number between Min_Data = 0 and Max_Data = 255
+  * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
+}
+
+/**
+  * @brief  Get frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
+  * @retval A number between Min_Data = 0 and Max_Data = 255
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
+}
+
+/**
+  * @brief  Set division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
+  * @param  Divider This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
+}
+
+/**
+  * @brief  Get division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
+}
+
+/**
+  * @brief  Set SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
+}
+
+/**
+  * @brief  Get SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
+}
+
+/**
+  * @brief  Set input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
+}
+
+/**
+  * @brief  Get input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
+}
+
+/**
+  * @brief  Configure CRS for the synchronization
+  * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
+  *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
+  *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
+  * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
+  * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
+  * @param  Settings This parameter can be a combination of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
+  *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
+                                                  uint32_t ReloadValue, uint32_t Settings)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
+  MODIFY_REG(CRS->CFGR,
+             CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
+             ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate software SYNC event
+  * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Get the frequency error direction latched in the time of the last
+  * SYNC event
+  * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+  * @brief  Get the frequency error counter value latched in the time of the last SYNC event
+  * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
+  * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if SYNC event OK signal occurred or not
+  * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if SYNC warning signal occurred or not
+  * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error signal occurred or not
+  * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Expected SYNC signal occurred or not
+  * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if SYNC error signal occurred or not
+  * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if SYNC missed error signal occurred or not
+  * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Trimming overflow or underflow occurred or not
+  * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the SYNC event OK flag
+  * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+}
+
+/**
+  * @brief  Clear the  SYNC warning flag
+  * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+}
+
+/**
+  * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
+  * the ERR flag
+  * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+}
+
+/**
+  * @brief  Clear Expected SYNC flag
+  * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Disable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Check if SYNC event OK interrupt is enabled or not
+  * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Disable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Check if SYNC warning interrupt is enabled or not
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Disable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error interrupt is enabled or not
+  * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Disable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Check if Expected SYNC interrupt is enabled or not
+  * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_CRS_DeInit(void);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRS) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_CRS_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h
new file mode 100644
index 0000000..76dfbf0
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h
@@ -0,0 +1,2578 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_DMA_H
+#define __STM32G4xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+#include "stm32g4xx_ll_dmamux.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  * @{
+  */
+/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
+static const uint8_t CHANNEL_OFFSET_TAB[] =
+{
+  (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE)
+#if defined (DMA1_Channel7)
+  ,
+  (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
+#endif /* DMA1_Channel7 */
+#if defined (DMA1_Channel8)
+  ,
+  (uint8_t)(DMA1_Channel8_BASE - DMA1_BASE)
+#endif /* DMA1_Channel8 */
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Constants DMA Private Constants
+  * @{
+  */
+/* Define used to get CSELR register offset */
+#define DMA_CSELR_OFFSET                  (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
+
+/* Defines used for the bit position in the register and perform offsets */
+#define DMA_POSITION_CSELR_CXS            POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_Private_Macros DMA Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
+                                        or as Source base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
+                                        or as Destination base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
+                                        from memory to memory or from peripheral to memory.
+                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
+                                        This parameter can be a value of @ref DMA_LL_EC_MODE
+                                        @note: The circular buffer mode cannot be used if the memory to memory
+                                               data transfer direction is configured on the selected Channel
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
+                                        The data unit is equal to the source buffer configuration set in PeripheralSize
+                                        or MemorySize parameters depending in the transfer direction.
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
+                                        This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
+
+  uint32_t Priority;               /*!< Specifies the channel priority level.
+                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
+
+} LL_DMA_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+  * @{
+  */
+/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_DMA_WriteReg function
+  * @{
+  */
+#define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
+#define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
+#define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
+#define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
+#define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
+#define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
+#define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
+#define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
+#define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
+#define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
+#define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
+#define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
+#if defined (DMA1_Channel7)
+#define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
+#define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
+#endif /* DMA1_Channel7 */
+#if defined (DMA1_Channel8)
+#define LL_DMA_IFCR_CGIF8                 DMA_IFCR_CGIF8        /*!< Channel 8 global flag            */
+#define LL_DMA_IFCR_CTCIF8                DMA_IFCR_CTCIF8       /*!< Channel 8 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF8                DMA_IFCR_CHTIF8       /*!< Channel 8 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF8                DMA_IFCR_CTEIF8       /*!< Channel 8 transfer error flag    */
+#endif /* DMA1_Channel8 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_DMA_ReadReg function
+  * @{
+  */
+#define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
+#define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
+#define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
+#define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
+#define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
+#define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
+#define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
+#define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
+#define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
+#define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
+#define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
+#define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
+#define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
+#define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
+#define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
+#define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
+#define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
+#define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
+#define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
+#define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
+#define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
+#define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
+#define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
+#define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
+#if defined (DMA1_Channel7)
+#define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
+#define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
+#define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
+#define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
+#endif /* DMA1_Channel7 */
+#if defined (DMA1_Channel8)
+#define LL_DMA_ISR_GIF8                   DMA_ISR_GIF8          /*!< Channel 8 global flag            */
+#define LL_DMA_ISR_TCIF8                  DMA_ISR_TCIF8         /*!< Channel 8 transfer complete flag */
+#define LL_DMA_ISR_HTIF8                  DMA_ISR_HTIF8         /*!< Channel 8 half transfer flag     */
+#define LL_DMA_ISR_TEIF8                  DMA_ISR_TEIF8         /*!< Channel 8 transfer error flag    */
+#endif /* DMA1_Channel8 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
+  * @{
+  */
+#define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
+#define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
+#define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+  * @{
+  */
+#define LL_DMA_CHANNEL_1                  0x00000000U /*!< DMA Channel 1 */
+#define LL_DMA_CHANNEL_2                  0x00000001U /*!< DMA Channel 2 */
+#define LL_DMA_CHANNEL_3                  0x00000002U /*!< DMA Channel 3 */
+#define LL_DMA_CHANNEL_4                  0x00000003U /*!< DMA Channel 4 */
+#define LL_DMA_CHANNEL_5                  0x00000004U /*!< DMA Channel 5 */
+#define LL_DMA_CHANNEL_6                  0x00000005U /*!< DMA Channel 6 */
+#if defined (DMA1_Channel7)
+#define LL_DMA_CHANNEL_7                  0x00000006U /*!< DMA Channel 7 */
+#endif /* DMA1_Channel7 */
+#if defined (DMA1_Channel8)
+#define LL_DMA_CHANNEL_8                  0x00000007U /*!< DMA Channel 8 */
+#endif /* DMA1_Channel8 */
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_DMA_CHANNEL_ALL                0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
+#endif /*USE_FULL_LL_DRIVER*/
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
+  * @{
+  */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MODE Transfer mode
+  * @{
+  */
+#define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */
+#define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
+  * @{
+  */
+#define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
+#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
+  * @{
+  */
+#define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
+#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
+  * @{
+  */
+#define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */
+#define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
+  * @{
+  */
+#define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */
+#define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
+  * @{
+  */
+#define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */
+#define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
+#define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
+#define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
+  * @{
+  */
+/**
+  * @brief  Convert DMAx_Channely into DMAx
+  * @param  __CHANNEL_INSTANCE__ DMAx_Channely
+  * @retval DMAx
+  */
+#if defined (DMA1_Channel8)
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
+  (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel8)) ?  DMA2 : DMA1)
+#else
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
+  (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel6)) ?  DMA2 : DMA1)
+#endif /* DMA1_Channel8 */
+/**
+  * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
+  * @param  __CHANNEL_INSTANCE__ DMAx_Channely
+  * @retval LL_DMA_CHANNEL_y
+  */
+#if defined (DMA1_Channel8)
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
+  (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel7)) ? LL_DMA_CHANNEL_7 : \
+   LL_DMA_CHANNEL_8)
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
+  (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
+   LL_DMA_CHANNEL_6)
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
+  * @param  __DMA_INSTANCE__ DMAx
+  * @param  __CHANNEL__ LL_DMA_CHANNEL_y
+  * @retval DMAx_Channely
+  */
+#if defined (DMA1_Channel8)
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
+  ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA2_Channel7 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) ? DMA1_Channel8 : \
+   DMA2_Channel8)
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
+  ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+   DMA2_Channel6)
+#endif /* DMA1_Channel8 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief  Enable DMA channel.
+  * @rmtoll CCR          EN            LL_DMA_EnableChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN);
+}
+
+/**
+  * @brief  Disable DMA channel.
+  * @rmtoll CCR          EN            LL_DMA_DisableChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN);
+}
+
+/**
+  * @brief  Check if DMA channel is enabled or disabled.
+  * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+                    DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure all parameters link to DMA transfer.
+  * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
+  *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
+  *         CCR          CIRC          LL_DMA_ConfigTransfer\n
+  *         CCR          PINC          LL_DMA_ConfigTransfer\n
+  *         CCR          MINC          LL_DMA_ConfigTransfer\n
+  *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
+  *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
+  *         CCR          PL            LL_DMA_ConfigTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+             DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
+             Configuration);
+}
+
+/**
+  * @brief  Set Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
+  *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+             DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
+}
+
+/**
+  * @brief  Get Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
+  *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+                   DMA_CCR_DIR | DMA_CCR_MEM2MEM));
+}
+
+/**
+  * @brief  Set DMA mode circular or normal.
+  * @note The circular buffer mode cannot be used if the memory-to-memory
+  * data transfer is configured on the selected Channel.
+  * @rmtoll CCR          CIRC          LL_DMA_SetMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_CIRC,
+             Mode);
+}
+
+/**
+  * @brief  Get DMA mode circular or normal.
+  * @rmtoll CCR          CIRC          LL_DMA_GetMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+                   DMA_CCR_CIRC));
+}
+
+/**
+  * @brief  Set Peripheral increment mode.
+  * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PINC,
+             PeriphOrM2MSrcIncMode);
+}
+
+/**
+  * @brief  Get Peripheral increment mode.
+  * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+                   DMA_CCR_PINC));
+}
+
+/**
+  * @brief  Set Memory increment mode.
+  * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MINC,
+             MemoryOrM2MDstIncMode);
+}
+
+/**
+  * @brief  Get Memory increment mode.
+  * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+                   DMA_CCR_MINC));
+}
+
+/**
+  * @brief  Set Peripheral size.
+  * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PSIZE,
+             PeriphOrM2MSrcDataSize);
+}
+
+/**
+  * @brief  Get Peripheral size.
+  * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+                   DMA_CCR_PSIZE));
+}
+
+/**
+  * @brief  Set Memory size.
+  * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MSIZE,
+             MemoryOrM2MDstDataSize);
+}
+
+/**
+  * @brief  Get Memory size.
+  * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+                   DMA_CCR_MSIZE));
+}
+
+/**
+  * @brief  Set Channel priority level.
+  * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  Priority This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PL,
+             Priority);
+}
+
+/**
+  * @brief  Get Channel priority level.
+  * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+                   DMA_CCR_PL));
+}
+
+/**
+  * @brief  Set Number of data to transfer.
+  * @note   This action has no effect if
+  *         channel is enabled.
+  * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR,
+             DMA_CNDTR_NDT, NbData);
+}
+
+/**
+  * @brief  Get Number of data to transfer.
+  * @note   Once the channel is enabled, the return value indicate the
+  *         remaining bytes to be transmitted.
+  * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR,
+                   DMA_CNDTR_NDT));
+}
+
+/**
+  * @brief  Configure the Source and Destination addresses.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @note   Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
+  * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
+  *         CMAR         MA            LL_DMA_ConfigAddresses
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
+                                            uint32_t DstAddress, uint32_t Direction)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  /* Direction Memory to Periph */
+  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+  {
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, SrcAddress);
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, DstAddress);
+  }
+  /* Direction Periph to Memory and Memory to Memory */
+  else
+  {
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, SrcAddress);
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, DstAddress);
+  }
+}
+
+/**
+  * @brief  Set the Memory address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Peripheral address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, PeriphAddress);
+}
+
+/**
+  * @brief  Get Memory address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR));
+}
+
+/**
+  * @brief  Get Peripheral address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR));
+}
+
+/**
+  * @brief  Set the Memory to Memory Source address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Memory to Memory Destination address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, MemoryAddress);
+}
+
+/**
+  * @brief  Get the Memory to Memory Source address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR));
+}
+
+/**
+  * @brief  Get the Memory to Memory Destination address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR));
+}
+
+/**
+  * @brief  Set DMA request for DMA instance on Channel x.
+  * @note   Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
+  * @rmtoll CSELR        C1S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C2S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C3S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C4S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C5S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C6S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C7S           LL_DMA_SetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @param  PeriphRequest This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX_REQ_ADC1
+  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
+  *         @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
+  *         @arg @ref LL_DMAMUX_REQ_I2C4_TX
+  *         @arg @ref LL_DMAMUX_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
+  *         @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
+  *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
+  *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
+  *         @arg @ref LL_DMAMUX_REQ_ADC2
+  *         @arg @ref LL_DMAMUX_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX_REQ_ADC4 (*)
+  *         @arg @ref LL_DMAMUX_REQ_ADC5 (*)
+  *         @arg @ref LL_DMAMUX_REQ_QSPI (*)
+  *         @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
+  *         @arg @ref LL_DMAMUX_REQ_AES_IN
+  *         @arg @ref LL_DMAMUX_REQ_AES_OUT
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
+  *         @arg @ref LL_DMAMUX_REQ_DAC3_CH1
+  *         @arg @ref LL_DMAMUX_REQ_DAC3_CH2
+  *         @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
+  *         @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
+  *         @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
+  *         @arg @ref LL_DMAMUX_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
+  *         @arg @ref LL_DMAMUX_REQ_FMAC_READ
+  *         @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
+  *         @arg @ref LL_DMAMUX_REQ_CORDIC_READ
+  *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
+  *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
+  *         (*) Not on all G4 devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
+{
+  uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
+  MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, PeriphRequest);
+}
+
+/**
+  * @brief  Get DMA request for DMA instance on Channel x.
+  * @rmtoll CSELR        C1S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C2S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C3S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C4S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C5S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C6S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C7S           LL_DMA_GetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX_REQ_ADC1
+  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
+  *         @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
+  *         @arg @ref LL_DMAMUX_REQ_I2C4_TX
+  *         @arg @ref LL_DMAMUX_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
+  *         @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
+  *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
+  *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
+  *         @arg @ref LL_DMAMUX_REQ_ADC2
+  *         @arg @ref LL_DMAMUX_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX_REQ_ADC4 (*)
+  *         @arg @ref LL_DMAMUX_REQ_ADC5 (*)
+  *         @arg @ref LL_DMAMUX_REQ_QSPI (*)
+  *         @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
+  *         @arg @ref LL_DMAMUX_REQ_AES_IN
+  *         @arg @ref LL_DMAMUX_REQ_AES_OUT
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
+  *         @arg @ref LL_DMAMUX_REQ_DAC3_CH1
+  *         @arg @ref LL_DMAMUX_REQ_DAC3_CH2
+  *         @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
+  *         @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
+  *         @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
+  *         @arg @ref LL_DMAMUX_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
+  *         @arg @ref LL_DMAMUX_REQ_FMAC_READ
+  *         @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
+  *         @arg @ref LL_DMAMUX_REQ_CORDIC_READ
+  *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
+  *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
+  *         (*) Not on all G4 devices
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
+  return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Channel 1 global interrupt flag.
+  * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 2 global interrupt flag.
+  * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 3 global interrupt flag.
+  * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 4 global interrupt flag.
+  * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 5 global interrupt flag.
+  * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 6 global interrupt flag.
+  * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
+}
+
+#if defined (DMA1_Channel7)
+/**
+  * @brief  Get Channel 7 global interrupt flag.
+  * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined (DMA1_Channel8)
+/**
+  * @brief  Get Channel 8 global interrupt flag.
+  * @rmtoll ISR          GIF8          LL_DMA_IsActiveFlag_GI8
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Get Channel 1 transfer complete flag.
+  * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 2 transfer complete flag.
+  * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 3 transfer complete flag.
+  * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 4 transfer complete flag.
+  * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 5 transfer complete flag.
+  * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 6 transfer complete flag.
+  * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
+}
+
+#if defined (DMA1_Channel7)
+/**
+  * @brief  Get Channel 7 transfer complete flag.
+  * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined (DMA1_Channel8)
+/**
+  * @brief  Get Channel 8 transfer complete flag.
+  * @rmtoll ISR          TCIF8         LL_DMA_IsActiveFlag_TC8
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Get Channel 1 half transfer flag.
+  * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 2 half transfer flag.
+  * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 3 half transfer flag.
+  * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 4 half transfer flag.
+  * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 5 half transfer flag.
+  * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 6 half transfer flag.
+  * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
+}
+
+#if defined (DMA1_Channel8)
+/**
+  * @brief  Get Channel 7 half transfer flag.
+  * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined (DMA1_Channel8)
+/**
+  * @brief  Get Channel 8 half transfer flag.
+  * @rmtoll ISR          HTIF8         LL_DMA_IsActiveFlag_HT8
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Get Channel 1 transfer error flag.
+  * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 2 transfer error flag.
+  * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 3 transfer error flag.
+  * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 4 transfer error flag.
+  * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 5 transfer error flag.
+  * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Channel 6 transfer error flag.
+  * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
+}
+
+#if defined (DMA1_Channel7)
+/**
+  * @brief  Get Channel 7 transfer error flag.
+  * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined (DMA1_Channel8)
+/**
+  * @brief  Get Channel 8 transfer error flag.
+  * @rmtoll ISR          TEIF8         LL_DMA_IsActiveFlag_TE8
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Clear Channel 1 global interrupt flag.
+  * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
+    LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet.
+  * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
+}
+
+/**
+  * @brief  Clear Channel 2 global interrupt flag.
+  * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
+    LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet.
+  * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
+}
+
+/**
+  * @brief  Clear Channel 3 global interrupt flag.
+  * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
+    LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet.
+  * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
+}
+
+/**
+  * @brief  Clear Channel 4 global interrupt flag.
+  * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
+    LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet.
+  * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
+}
+
+/**
+  * @brief  Clear Channel 5 global interrupt flag.
+  * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
+    LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet.
+  * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
+}
+
+/**
+  * @brief  Clear Channel 6 global interrupt flag.
+  * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
+    LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet.
+  * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
+}
+
+#if defined (DMA1_Channel7)
+/**
+  * @brief  Clear Channel 7 global interrupt flag.
+  * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
+    LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet.
+  * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined (DMA1_Channel8)
+/**
+  * @brief  Clear Channel 8 global interrupt flag.
+  * @note Do not Clear Channel 8 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC8, LL_DMA_ClearFlag_HT8,
+    LL_DMA_ClearFlag_TE8. bug id 2.3.1 in Product Errata Sheet.
+  * @rmtoll IFCR         CGIF8         LL_DMA_ClearFlag_GI8
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Clear Channel 1  transfer complete flag.
+  * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
+}
+
+/**
+  * @brief  Clear Channel 2  transfer complete flag.
+  * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
+}
+
+/**
+  * @brief  Clear Channel 3  transfer complete flag.
+  * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
+}
+
+/**
+  * @brief  Clear Channel 4  transfer complete flag.
+  * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
+}
+
+/**
+  * @brief  Clear Channel 5  transfer complete flag.
+  * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
+}
+
+/**
+  * @brief  Clear Channel 6  transfer complete flag.
+  * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
+}
+
+#if defined (DMA1_Channel7)
+/**
+  * @brief  Clear Channel 7  transfer complete flag.
+  * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined (DMA1_Channel8)
+/**
+  * @brief  Clear Channel 8  transfer complete flag.
+  * @rmtoll IFCR         CTCIF8        LL_DMA_ClearFlag_TC8
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Clear Channel 1  half transfer flag.
+  * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
+}
+
+/**
+  * @brief  Clear Channel 2  half transfer flag.
+  * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
+}
+
+/**
+  * @brief  Clear Channel 3  half transfer flag.
+  * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
+}
+
+/**
+  * @brief  Clear Channel 4  half transfer flag.
+  * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
+}
+
+/**
+  * @brief  Clear Channel 5  half transfer flag.
+  * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
+}
+
+/**
+  * @brief  Clear Channel 6  half transfer flag.
+  * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
+}
+
+#if defined (DMA1_Channel7)
+/**
+  * @brief  Clear Channel 7  half transfer flag.
+  * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined (DMA1_Channel8)
+/**
+  * @brief  Clear Channel 8  half transfer flag.
+  * @rmtoll IFCR         CHTIF8        LL_DMA_ClearFlag_HT8
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+  * @brief  Clear Channel 1 transfer error flag.
+  * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
+}
+
+/**
+  * @brief  Clear Channel 2 transfer error flag.
+  * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
+}
+
+/**
+  * @brief  Clear Channel 3 transfer error flag.
+  * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
+}
+
+/**
+  * @brief  Clear Channel 4 transfer error flag.
+  * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
+}
+
+/**
+  * @brief  Clear Channel 5 transfer error flag.
+  * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
+}
+
+/**
+  * @brief  Clear Channel 6 transfer error flag.
+  * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
+}
+
+#if defined (DMA1_Channel7)
+/**
+  * @brief  Clear Channel 7 transfer error flag.
+  * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
+}
+#endif /* DMA1_Channel7 */
+
+#if defined (DMA1_Channel8)
+/**
+  * @brief  Clear Channel 8 transfer error flag.
+  * @rmtoll IFCR         CTEIF8        LL_DMA_ClearFlag_TE8
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8);
+}
+#endif /* DMA1_Channel8 */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+  * @{
+  */
+/**
+  * @brief  Enable Transfer complete interrupt.
+  * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+  * @brief  Enable Half transfer interrupt.
+  * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+  * @brief  Enable Transfer error interrupt.
+  * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+  * @brief  Disable Transfer complete interrupt.
+  * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+  * @brief  Disable Half transfer interrupt.
+  * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+  * @brief  Disable Transfer error interrupt.
+  * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+  * @brief  Check if Transfer complete Interrupt is enabled.
+  * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+                    DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Half transfer Interrupt is enabled.
+  * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+                    DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Transfer error Interrupt is enabled.
+  * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         (*) Not on all G4 devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
+                    DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_DMA_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h
new file mode 100644
index 0000000..7cd04b4
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h
@@ -0,0 +1,2006 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_dmamux.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMAMUX LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_DMAMUX_H
+#define __STM32G4xx_LL_DMAMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMAMUX1)
+
+/** @defgroup DMAMUX_LL DMAMUX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
+  * @{
+  */
+/* Define used to get DMAMUX CCR register size */
+#define DMAMUX_CCR_SIZE                   0x00000004U
+
+/* Define used to get DMAMUX RGCR register size */
+#define DMAMUX_RGCR_SIZE                  0x00000004U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Private_Macros DMAMUX Private Macros
+  * @{
+  */
+#define UNUSED(X) (void)X
+/**
+  * @}
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
+  * @{
+  */
+/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_DMAMUX_WriteReg function
+  * @{
+  */
+#define LL_DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0       /*!< Synchronization Event Overrun Flag Channel 0  */
+#define LL_DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1       /*!< Synchronization Event Overrun Flag Channel 1  */
+#define LL_DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2       /*!< Synchronization Event Overrun Flag Channel 2  */
+#define LL_DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3       /*!< Synchronization Event Overrun Flag Channel 3  */
+#define LL_DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4       /*!< Synchronization Event Overrun Flag Channel 4  */
+#define LL_DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5       /*!< Synchronization Event Overrun Flag Channel 5  */
+#define LL_DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6       /*!< Synchronization Event Overrun Flag Channel 6  */
+#define LL_DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7       /*!< Synchronization Event Overrun Flag Channel 7  */
+#define LL_DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8       /*!< Synchronization Event Overrun Flag Channel 8  */
+#define LL_DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9       /*!< Synchronization Event Overrun Flag Channel 9  */
+#define LL_DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10      /*!< Synchronization Event Overrun Flag Channel 10 */
+#define LL_DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11      /*!< Synchronization Event Overrun Flag Channel 11 */
+#define LL_DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12      /*!< Synchronization Event Overrun Flag Channel 12 */
+#define LL_DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13      /*!< Synchronization Event Overrun Flag Channel 13 */
+#define LL_DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14      /*!< Synchronization Event Overrun Flag Channel 14 */
+#define LL_DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15      /*!< Synchronization Event Overrun Flag Channel 15 */
+#define LL_DMAMUX_RGCFR_RGCOF0            DMAMUX_RGCFR_COF0      /*!< Request Generator 0 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF1            DMAMUX_RGCFR_COF1      /*!< Request Generator 1 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF2            DMAMUX_RGCFR_COF2      /*!< Request Generator 2 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF3            DMAMUX_RGCFR_COF3      /*!< Request Generator 3 Trigger Event Overrun Flag */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_DMAMUX_ReadReg function
+  * @{
+  */
+#define LL_DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0       /*!< Synchronization Event Overrun Flag Channel 0  */
+#define LL_DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1       /*!< Synchronization Event Overrun Flag Channel 1  */
+#define LL_DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2       /*!< Synchronization Event Overrun Flag Channel 2  */
+#define LL_DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3       /*!< Synchronization Event Overrun Flag Channel 3  */
+#define LL_DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4       /*!< Synchronization Event Overrun Flag Channel 4  */
+#define LL_DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5       /*!< Synchronization Event Overrun Flag Channel 5  */
+#define LL_DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6       /*!< Synchronization Event Overrun Flag Channel 6  */
+#define LL_DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7       /*!< Synchronization Event Overrun Flag Channel 7  */
+#define LL_DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8       /*!< Synchronization Event Overrun Flag Channel 8  */
+#define LL_DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9       /*!< Synchronization Event Overrun Flag Channel 9  */
+#define LL_DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10      /*!< Synchronization Event Overrun Flag Channel 10 */
+#define LL_DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11      /*!< Synchronization Event Overrun Flag Channel 11 */
+#define LL_DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12      /*!< Synchronization Event Overrun Flag Channel 12 */
+#define LL_DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13      /*!< Synchronization Event Overrun Flag Channel 13 */
+#define LL_DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14      /*!< Synchronization Event Overrun Flag Channel 14 */
+#define LL_DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15      /*!< Synchronization Event Overrun Flag Channel 15 */
+#define LL_DMAMUX_RGSR_RGOF0              DMAMUX_RGSR_OF0       /*!< Request Generator 0 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF1              DMAMUX_RGSR_OF1       /*!< Request Generator 1 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF2              DMAMUX_RGSR_OF2       /*!< Request Generator 2 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF3              DMAMUX_RGSR_OF3       /*!< Request Generator 3 Trigger Event Overrun Flag */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMAMUX_WriteReg functions
+  * @{
+  */
+#define LL_DMAMUX_CCR_SOIE                DMAMUX_CxCR_SOIE          /*!< Synchronization Event Overrun Interrupt */
+#define LL_DMAMUX_RGCR_RGOIE              DMAMUX_RGxCR_OIE          /*!< Request Generation Trigger Event Overrun Interrupt    */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
+  * @{
+  */
+#define LL_DMAMUX_REQ_MEM2MEM         0x00000000U  /*!< Memory to memory transfer  */
+#define LL_DMAMUX_REQ_GENERATOR0      0x00000001U  /*!< DMAMUX request generator 0 */
+#define LL_DMAMUX_REQ_GENERATOR1      0x00000002U  /*!< DMAMUX request generator 1 */
+#define LL_DMAMUX_REQ_GENERATOR2      0x00000003U  /*!< DMAMUX request generator 2 */
+#define LL_DMAMUX_REQ_GENERATOR3      0x00000004U  /*!< DMAMUX request generator 3 */
+#define LL_DMAMUX_REQ_ADC1            0x00000005U  /*!< DMAMUX ADC1 request        */
+#define LL_DMAMUX_REQ_DAC1_CH1        0x00000006U  /*!< DMAMUX DAC1 CH1 request    */
+#define LL_DMAMUX_REQ_DAC1_CH2        0x00000007U  /*!< DMAMUX DAC1 CH2 request    */
+#define LL_DMAMUX_REQ_TIM6_UP         0x00000008U  /*!< DMAMUX TIM6 UP request     */
+#define LL_DMAMUX_REQ_TIM7_UP         0x00000009U  /*!< DMAMUX TIM7 UP request     */
+#define LL_DMAMUX_REQ_SPI1_RX         0x0000000AU  /*!< DMAMUX SPI1 RX request     */
+#define LL_DMAMUX_REQ_SPI1_TX         0x0000000BU  /*!< DMAMUX SPI1 TX request     */
+#define LL_DMAMUX_REQ_SPI2_RX         0x0000000CU  /*!< DMAMUX SPI2 RX request     */
+#define LL_DMAMUX_REQ_SPI2_TX         0x0000000DU  /*!< DMAMUX SPI2 TX request     */
+#define LL_DMAMUX_REQ_SPI3_RX         0x0000000EU  /*!< DMAMUX SPI3 RX request     */
+#define LL_DMAMUX_REQ_SPI3_TX         0x0000000FU  /*!< DMAMUX SPI3 TX request     */
+#define LL_DMAMUX_REQ_I2C1_RX         0x00000010U  /*!< DMAMUX I2C1 RX request     */
+#define LL_DMAMUX_REQ_I2C1_TX         0x00000011U  /*!< DMAMUX I2C1 TX request     */
+#define LL_DMAMUX_REQ_I2C2_RX         0x00000012U  /*!< DMAMUX I2C2 RX request     */
+#define LL_DMAMUX_REQ_I2C2_TX         0x00000013U  /*!< DMAMUX I2C2 TX request     */
+#define LL_DMAMUX_REQ_I2C3_RX         0x00000014U  /*!< DMAMUX I2C3 RX request     */
+#define LL_DMAMUX_REQ_I2C3_TX         0x00000015U  /*!< DMAMUX I2C3 TX request     */
+#define LL_DMAMUX_REQ_I2C4_RX         0x00000016U  /*!< DMAMUX I2C4 RX request     */
+#define LL_DMAMUX_REQ_I2C4_TX         0x00000017U  /*!< DMAMUX I2C4 TX request     */
+#define LL_DMAMUX_REQ_USART1_RX       0x00000018U  /*!< DMAMUX USART1 RX request   */
+#define LL_DMAMUX_REQ_USART1_TX       0x00000019U  /*!< DMAMUX USART1 TX request   */
+#define LL_DMAMUX_REQ_USART2_RX       0x0000001AU  /*!< DMAMUX USART2 RX request   */
+#define LL_DMAMUX_REQ_USART2_TX       0x0000001BU  /*!< DMAMUX USART2 TX request   */
+#define LL_DMAMUX_REQ_USART3_RX       0x0000001CU  /*!< DMAMUX USART3 RX request   */
+#define LL_DMAMUX_REQ_USART3_TX       0x0000001DU  /*!< DMAMUX USART3 TX request   */
+#define LL_DMAMUX_REQ_UART4_RX        0x0000001EU  /*!< DMAMUX UART4 RX request    */
+#define LL_DMAMUX_REQ_UART4_TX        0x0000001FU  /*!< DMAMUX UART4 TX request    */
+#define LL_DMAMUX_REQ_UART5_RX        0x00000020U  /*!< DMAMUX UART5 RX request    */
+#define LL_DMAMUX_REQ_UART5_TX        0x00000021U  /*!< DMAMUX UART5 TX request    */
+#define LL_DMAMUX_REQ_LPUART1_RX      0x00000022U  /*!< DMAMUX LPUART1 RX request  */
+#define LL_DMAMUX_REQ_LPUART1_TX      0x00000023U  /*!< DMAMUX LPUART1 TX request  */
+#define LL_DMAMUX_REQ_ADC2            0x00000024U  /*!< DMAMUX ADC2 request        */
+#define LL_DMAMUX_REQ_ADC3            0x00000025U  /*!< DMAMUX ADC3 request        */
+#define LL_DMAMUX_REQ_ADC4            0x00000026U  /*!< DMAMUX ADC4 request        */
+#define LL_DMAMUX_REQ_ADC5            0x00000027U  /*!< DMAMUX ADC5 request        */
+#define LL_DMAMUX_REQ_QSPI            0x00000028U  /*!< DMAMUX QSPI request        */
+#define LL_DMAMUX_REQ_DAC2_CH1        0x00000029U  /*!< DMAMUX DAC2 CH1 request    */
+#define LL_DMAMUX_REQ_TIM1_CH1        0x0000002AU  /*!< DMAMUX TIM1 CH1 request    */
+#define LL_DMAMUX_REQ_TIM1_CH2        0x0000002BU  /*!< DMAMUX TIM1 CH2 request    */
+#define LL_DMAMUX_REQ_TIM1_CH3        0x0000002CU  /*!< DMAMUX TIM1 CH3 request    */
+#define LL_DMAMUX_REQ_TIM1_CH4        0x0000002DU  /*!< DMAMUX TIM1 CH4 request    */
+#define LL_DMAMUX_REQ_TIM1_UP         0x0000002EU  /*!< DMAMUX TIM1 UP request     */
+#define LL_DMAMUX_REQ_TIM1_TRIG       0x0000002FU  /*!< DMAMUX TIM1 TRIG request   */
+#define LL_DMAMUX_REQ_TIM1_COM        0x00000030U  /*!< DMAMUX TIM1 COM request    */
+#define LL_DMAMUX_REQ_TIM8_CH1        0x00000031U  /*!< DMAMUX TIM8 CH1 request    */
+#define LL_DMAMUX_REQ_TIM8_CH2        0x00000032U  /*!< DMAMUX TIM8 CH2 request    */
+#define LL_DMAMUX_REQ_TIM8_CH3        0x00000033U  /*!< DMAMUX TIM8 CH3 request    */
+#define LL_DMAMUX_REQ_TIM8_CH4        0x00000034U  /*!< DMAMUX TIM8 CH4 request    */
+#define LL_DMAMUX_REQ_TIM8_UP         0x00000035U  /*!< DMAMUX TIM8 UP request     */
+#define LL_DMAMUX_REQ_TIM8_TRIG       0x00000036U  /*!< DMAMUX TIM8 TRIG request   */
+#define LL_DMAMUX_REQ_TIM8_COM        0x00000037U  /*!< DMAMUX TIM8 COM request    */
+#define LL_DMAMUX_REQ_TIM2_CH1        0x00000038U  /*!< DMAMUX TIM2 CH1 request    */
+#define LL_DMAMUX_REQ_TIM2_CH2        0x00000039U  /*!< DMAMUX TIM2 CH2 request    */
+#define LL_DMAMUX_REQ_TIM2_CH3        0x0000003AU  /*!< DMAMUX TIM2 CH3 request    */
+#define LL_DMAMUX_REQ_TIM2_CH4        0x0000003BU  /*!< DMAMUX TIM2 CH4 request    */
+#define LL_DMAMUX_REQ_TIM2_UP         0x0000003CU  /*!< DMAMUX TIM2 UP request     */
+#define LL_DMAMUX_REQ_TIM3_CH1        0x0000003DU  /*!< DMAMUX TIM3 CH1 request    */
+#define LL_DMAMUX_REQ_TIM3_CH2        0x0000003EU  /*!< DMAMUX TIM3 CH2 request    */
+#define LL_DMAMUX_REQ_TIM3_CH3        0x0000003FU  /*!< DMAMUX TIM3 CH3 request    */
+#define LL_DMAMUX_REQ_TIM3_CH4        0x00000040U  /*!< DMAMUX TIM3 CH4 request    */
+#define LL_DMAMUX_REQ_TIM3_UP         0x00000041U  /*!< DMAMUX TIM3 UP request     */
+#define LL_DMAMUX_REQ_TIM3_TRIG       0x00000042U  /*!< DMAMUX TIM3 TRIG request   */
+#define LL_DMAMUX_REQ_TIM4_CH1        0x00000043U  /*!< DMAMUX TIM4 CH1 request    */
+#define LL_DMAMUX_REQ_TIM4_CH2        0x00000044U  /*!< DMAMUX TIM4 CH2 request    */
+#define LL_DMAMUX_REQ_TIM4_CH3        0x00000045U  /*!< DMAMUX TIM4 CH3 request    */
+#define LL_DMAMUX_REQ_TIM4_CH4        0x00000046U  /*!< DMAMUX TIM4 CH4 request    */
+#define LL_DMAMUX_REQ_TIM4_UP         0x00000047U  /*!< DMAMUX TIM4 UP request     */
+#define LL_DMAMUX_REQ_TIM5_CH1        0x00000048U  /*!< DMAMUX TIM5 CH1 request    */
+#define LL_DMAMUX_REQ_TIM5_CH2        0x00000049U  /*!< DMAMUX TIM5 CH2 request    */
+#define LL_DMAMUX_REQ_TIM5_CH3        0x0000004AU  /*!< DMAMUX TIM5 CH3 request    */
+#define LL_DMAMUX_REQ_TIM5_CH4        0x0000004BU  /*!< DMAMUX TIM5 CH4 request    */
+#define LL_DMAMUX_REQ_TIM5_UP         0x0000004CU  /*!< DMAMUX TIM5 UP request     */
+#define LL_DMAMUX_REQ_TIM5_TRIG       0x0000004DU  /*!< DMAMUX TIM5 TRIG request   */
+#define LL_DMAMUX_REQ_TIM15_CH1       0x0000004EU  /*!< DMAMUX TIM15 CH1 request   */
+#define LL_DMAMUX_REQ_TIM15_UP        0x0000004FU  /*!< DMAMUX TIM15 UP request    */
+#define LL_DMAMUX_REQ_TIM15_TRIG      0x00000050U  /*!< DMAMUX TIM15 TRIG request  */
+#define LL_DMAMUX_REQ_TIM15_COM       0x00000051U  /*!< DMAMUX TIM15 COM request   */
+#define LL_DMAMUX_REQ_TIM16_CH1       0x00000052U  /*!< DMAMUX TIM16 CH1 request   */
+#define LL_DMAMUX_REQ_TIM16_UP        0x00000053U  /*!< DMAMUX TIM16 UP request    */
+#define LL_DMAMUX_REQ_TIM17_CH1       0x00000054U  /*!< DMAMUX TIM17 CH1 request   */
+#define LL_DMAMUX_REQ_TIM17_UP        0x00000055U  /*!< DMAMUX TIM17 UP request    */
+#define LL_DMAMUX_REQ_TIM20_CH1       0x00000056U  /*!< DMAMUX TIM20 CH1 request   */
+#define LL_DMAMUX_REQ_TIM20_CH2       0x00000057U  /*!< DMAMUX TIM20 CH2 request   */
+#define LL_DMAMUX_REQ_TIM20_CH3       0x00000058U  /*!< DMAMUX TIM20 CH3 request   */
+#define LL_DMAMUX_REQ_TIM20_CH4       0x00000059U  /*!< DMAMUX TIM20 CH4 request   */
+#define LL_DMAMUX_REQ_TIM20_UP        0x0000005AU  /*!< DMAMUX TIM20 UP request    */
+#define LL_DMAMUX_REQ_AES_IN          0x0000005BU  /*!< DMAMUX AES_IN request      */
+#define LL_DMAMUX_REQ_AES_OUT         0x0000005CU  /*!< DMAMUX AES_OUT request     */
+#define LL_DMAMUX_REQ_TIM20_TRIG      0x0000005DU  /*!< DMAMUX TIM20 TRIG request  */
+#define LL_DMAMUX_REQ_TIM20_COM       0x0000005EU  /*!< DMAMUX TIM20 COM request   */
+#define LL_DMAMUX_REQ_HRTIM1_M        0x0000005FU  /*!< DMAMUX HRTIM M request     */
+#define LL_DMAMUX_REQ_HRTIM1_A        0x00000060U  /*!< DMAMUX HRTIM A request     */
+#define LL_DMAMUX_REQ_HRTIM1_B        0x00000061U  /*!< DMAMUX HRTIM B request     */
+#define LL_DMAMUX_REQ_HRTIM1_C        0x00000062U  /*!< DMAMUX HRTIM C request     */
+#define LL_DMAMUX_REQ_HRTIM1_D        0x00000063U  /*!< DMAMUX HRTIM D request     */
+#define LL_DMAMUX_REQ_HRTIM1_E        0x00000064U  /*!< DMAMUX HRTIM E request     */
+#define LL_DMAMUX_REQ_HRTIM1_F        0x00000065U  /*!< DMAMUX HRTIM F request     */
+#define LL_DMAMUX_REQ_DAC3_CH1        0x00000066U  /*!< DMAMUX DAC3 CH1 request    */
+#define LL_DMAMUX_REQ_DAC3_CH2        0x00000067U  /*!< DMAMUX DAC3 CH2 request    */
+#define LL_DMAMUX_REQ_DAC4_CH1        0x00000068U  /*!< DMAMUX DAC4 CH1 request    */
+#define LL_DMAMUX_REQ_DAC4_CH2        0x00000069U  /*!< DMAMUX DAC4 CH2 request    */
+#define LL_DMAMUX_REQ_SPI4_RX         0x0000006AU  /*!< DMAMUX SPI4 RX request     */
+#define LL_DMAMUX_REQ_SPI4_TX         0x0000006BU  /*!< DMAMUX SPI4 TX request     */
+#define LL_DMAMUX_REQ_SAI1_A          0x0000006CU  /*!< DMAMUX SAI1 A request      */
+#define LL_DMAMUX_REQ_SAI1_B          0x0000006DU  /*!< DMAMUX SAI1 B request      */
+#define LL_DMAMUX_REQ_FMAC_READ       0x0000006EU  /*!< DMAMUX FMAC READ request   */
+#define LL_DMAMUX_REQ_FMAC_WRITE      0x0000006FU  /*!< DMAMUX FMAC WRITE request  */
+#define LL_DMAMUX_REQ_CORDIC_READ     0x00000070U  /*!< DMAMUX CORDIC READ request */
+#define LL_DMAMUX_REQ_CORDIC_WRITE    0x00000071U  /*!< DMAMUX CORDIC WRITE request*/
+#define LL_DMAMUX_REQ_UCPD1_RX        0x00000072U  /*!< DMAMUX USBPD1_RX request   */
+#define LL_DMAMUX_REQ_UCPD1_TX        0x00000073U  /*!< DMAMUX USBPD1_TX request   */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
+  * @{
+  */
+#define LL_DMAMUX_CHANNEL_0               0x00000000U               /*!< DMAMUX Channel 0 connected to DMA1 Channel 1  */
+#define LL_DMAMUX_CHANNEL_1               0x00000001U               /*!< DMAMUX Channel 1 connected to DMA1 Channel 2  */
+#define LL_DMAMUX_CHANNEL_2               0x00000002U               /*!< DMAMUX Channel 2 connected to DMA1 Channel 3  */
+#define LL_DMAMUX_CHANNEL_3               0x00000003U               /*!< DMAMUX Channel 3 connected to DMA1 Channel 4  */
+#define LL_DMAMUX_CHANNEL_4               0x00000004U               /*!< DMAMUX Channel 4 connected to DMA1 Channel 5  */
+#define LL_DMAMUX_CHANNEL_5               0x00000005U               /*!< DMAMUX Channel 5 connected to DMA1 Channel 6  */
+#define LL_DMAMUX_CHANNEL_6               0x00000006U               /*!< DMAMUX Channel 6 connected to DMA1 Channel 7  */
+#define LL_DMAMUX_CHANNEL_7               0x00000007U               /*!< DMAMUX Channel 7 connected to DMA1 Channel 8  */
+#define LL_DMAMUX_CHANNEL_8               0x00000008U               /*!< DMAMUX Channel 8 connected to DMA2 Channel 1  */
+#define LL_DMAMUX_CHANNEL_9               0x00000009U               /*!< DMAMUX Channel 9 connected to DMA2 Channel 2  */
+#define LL_DMAMUX_CHANNEL_10              0x0000000AU               /*!< DMAMUX Channel 10 connected to DMA2 Channel 3 */
+#define LL_DMAMUX_CHANNEL_11              0x0000000BU               /*!< DMAMUX Channel 11 connected to DMA2 Channel 4 */
+#define LL_DMAMUX_CHANNEL_12              0x0000000CU               /*!< DMAMUX Channel 12 connected to DMA2 Channel 5 */
+#define LL_DMAMUX_CHANNEL_13              0x0000000DU               /*!< DMAMUX Channel 13 connected to DMA2 Channel 6 */
+#define LL_DMAMUX_CHANNEL_14              0x0000000EU               /*!< DMAMUX Channel 14 connected to DMA2 Channel 7 */
+#define LL_DMAMUX_CHANNEL_15              0x0000000FU               /*!< DMAMUX Channel 15 connected to DMA2 Channel 8 */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
+  * @{
+  */
+#define LL_DMAMUX_SYNC_NO_EVENT            0x00000000U                               /*!< All requests are blocked   */
+#define LL_DMAMUX_SYNC_POL_RISING          DMAMUX_CxCR_SPOL_0                        /*!< Synchronization on event on rising edge */
+#define LL_DMAMUX_SYNC_POL_FALLING         DMAMUX_CxCR_SPOL_1                        /*!< Synchronization on event on falling edge */
+#define LL_DMAMUX_SYNC_POL_RISING_FALLING  (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
+  * @{
+  */
+#define LL_DMAMUX_SYNC_EXTI_LINE0      0x00000000U                                                                                     /*!< Synchronization signal from EXTI Line0  */
+#define LL_DMAMUX_SYNC_EXTI_LINE1      DMAMUX_CxCR_SYNC_ID_0                                                                           /*!< Synchronization signal from EXTI Line1  */
+#define LL_DMAMUX_SYNC_EXTI_LINE2      DMAMUX_CxCR_SYNC_ID_1                                                                           /*!< Synchronization signal from EXTI Line2  */
+#define LL_DMAMUX_SYNC_EXTI_LINE3      (DMAMUX_CxCR_SYNC_ID_1 |DMAMUX_CxCR_SYNC_ID_0)                                                  /*!< Synchronization signal from EXTI Line3  */
+#define LL_DMAMUX_SYNC_EXTI_LINE4      DMAMUX_CxCR_SYNC_ID_2                                                                           /*!< Synchronization signal from EXTI Line4  */
+#define LL_DMAMUX_SYNC_EXTI_LINE5      (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line5  */
+#define LL_DMAMUX_SYNC_EXTI_LINE6      (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from EXTI Line6  */
+#define LL_DMAMUX_SYNC_EXTI_LINE7      (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line7  */
+#define LL_DMAMUX_SYNC_EXTI_LINE8      DMAMUX_CxCR_SYNC_ID_3                                                                           /*!< Synchronization signal from EXTI Line8  */
+#define LL_DMAMUX_SYNC_EXTI_LINE9      (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line9  */
+#define LL_DMAMUX_SYNC_EXTI_LINE10     (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from EXTI Line10 */
+#define LL_DMAMUX_SYNC_EXTI_LINE11     (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line11 */
+#define LL_DMAMUX_SYNC_EXTI_LINE12     (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)                                                 /*!< Synchronization signal from EXTI Line12 */
+#define LL_DMAMUX_SYNC_EXTI_LINE13     (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line13 */
+#define LL_DMAMUX_SYNC_EXTI_LINE14     (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)                         /*!< Synchronization signal from EXTI Line14 */
+#define LL_DMAMUX_SYNC_EXTI_LINE15     (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line15 */
+#define LL_DMAMUX_SYNC_DMAMUX_CH0      DMAMUX_CxCR_SYNC_ID_4                                                                           /*!< Synchronization signal from DMAMUX channel0 Event */
+#define LL_DMAMUX_SYNC_DMAMUX_CH1      (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from DMAMUX channel1 Event */
+#define LL_DMAMUX_SYNC_DMAMUX_CH2      (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from DMAMUX channel2 Event */
+#define LL_DMAMUX_SYNC_DMAMUX_CH3      (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from DMAMUX channel3 Event */
+#define LL_DMAMUX_SYNC_LPTIM1_OUT      (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2)                                                 /*!< Synchronization signal from LPTIM1 Output */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
+  * @{
+  */
+#define LL_DMAMUX_REQ_GEN_0           0x00000000U
+#define LL_DMAMUX_REQ_GEN_1           0x00000001U
+#define LL_DMAMUX_REQ_GEN_2           0x00000002U
+#define LL_DMAMUX_REQ_GEN_3           0x00000003U
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
+  * @{
+  */
+#define LL_DMAMUX_REQ_GEN_NO_EVENT                  0x00000000U                                  /*!< No external DMA request  generation */
+#define LL_DMAMUX_REQ_GEN_POL_RISING                DMAMUX_RGxCR_GPOL_0                          /*!< External DMA request generation on event on rising edge */
+#define LL_DMAMUX_REQ_GEN_POL_FALLING               DMAMUX_RGxCR_GPOL_1                          /*!< External DMA request generation on event on falling edge */
+#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING        (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)  /*!< External DMA request generation on rising and falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
+  * @{
+  */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE0      0x00000000U                                                                                     /*!< Request signal generation from EXTI Line0  */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE1      DMAMUX_RGxCR_SIG_ID_0                                                                           /*!< Request signal generation from EXTI Line1  */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE2      DMAMUX_RGxCR_SIG_ID_1                                                                           /*!< Request signal generation from EXTI Line2  */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE3      (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)                                                  /*!< Request signal generation from EXTI Line3  */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE4      DMAMUX_RGxCR_SIG_ID_2                                                                           /*!< Request signal generation from EXTI Line4  */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE5      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from EXTI Line5  */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE6      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from EXTI Line6  */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE7      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line7  */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE8      DMAMUX_RGxCR_SIG_ID_3                                                                           /*!< Request signal generation from EXTI Line8  */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE9      (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from EXTI Line9  */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE10     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from EXTI Line10 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE11     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line11 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE12     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)                                                 /*!< Request signal generation from EXTI Line12 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE13     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line13 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE14     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)                         /*!< Request signal generation from EXTI Line14 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE15     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
+#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0      DMAMUX_RGxCR_SIG_ID_4                                                                           /*!< Request signal generation from DMAMUX channel0 Event */
+#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from DMAMUX channel1 Event */
+#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from DMAMUX channel2 Event */
+#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from DMAMUX channel3 Event */
+#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2)                                                 /*!< Request signal generation from LPTIM1 Output */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
+  * @{
+  */
+/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMAMUX register
+  * @param  __INSTANCE__ DMAMUX Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMAMUX register
+  * @param  __INSTANCE__ DMAMUX Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
+  * @{
+  */
+
+/** @defgroup DMAMUX_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief  Set DMAMUX request ID for DMAMUX Channel x.
+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
+  *         DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_SetRequestID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX_REQ_ADC1
+  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
+  *         @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
+  *         @arg @ref LL_DMAMUX_REQ_I2C4_TX
+  *         @arg @ref LL_DMAMUX_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
+  *         @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
+  *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
+  *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
+  *         @arg @ref LL_DMAMUX_REQ_ADC2
+  *         @arg @ref LL_DMAMUX_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX_REQ_ADC4 (*)
+  *         @arg @ref LL_DMAMUX_REQ_ADC5 (*)
+  *         @arg @ref LL_DMAMUX_REQ_QSPI (*)
+  *         @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
+  *         @arg @ref LL_DMAMUX_REQ_AES_IN
+  *         @arg @ref LL_DMAMUX_REQ_AES_OUT
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
+  *         @arg @ref LL_DMAMUX_REQ_DAC3_CH1
+  *         @arg @ref LL_DMAMUX_REQ_DAC3_CH2
+  *         @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
+  *         @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
+  *         @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
+  *         @arg @ref LL_DMAMUX_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
+  *         @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
+  *         @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
+  *         @arg @ref LL_DMAMUX_REQ_CORDIC_READ
+  *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
+  *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
+  *         (*) Not on all G4 devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
+{
+  (void)(DMAMUXx);
+  MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
+}
+
+/**
+  * @brief  Get DMAMUX request ID for DMAMUX Channel x.
+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
+  *         DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_GetRequestID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  *         (*) Not on all G4 devices
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX_REQ_ADC1
+  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
+  *         @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
+  *         @arg @ref LL_DMAMUX_REQ_I2C4_TX
+  *         @arg @ref LL_DMAMUX_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
+  *         @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
+  *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
+  *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
+  *         @arg @ref LL_DMAMUX_REQ_ADC2
+  *         @arg @ref LL_DMAMUX_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX_REQ_ADC4 (*)
+  *         @arg @ref LL_DMAMUX_REQ_ADC5 (*)
+  *         @arg @ref LL_DMAMUX_REQ_QSPI (*)
+  *         @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH4
+  *         @arg @ref LL_DMAMUX_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
+  *         @arg @ref LL_DMAMUX_REQ_AES_IN
+  *         @arg @ref LL_DMAMUX_REQ_AES_OUT
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
+  *         @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
+  *         @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
+  *         @arg @ref LL_DMAMUX_REQ_DAC3_CH1
+  *         @arg @ref LL_DMAMUX_REQ_DAC3_CH2
+  *         @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
+  *         @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
+  *         @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
+  *         @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
+  *         @arg @ref LL_DMAMUX_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
+  *         @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
+  *         @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
+  *         @arg @ref LL_DMAMUX_REQ_CORDIC_READ
+  *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
+  *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
+  *         (*) Not on all G4 devices
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID));
+}
+
+/**
+  * @brief  Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
+  * @rmtoll CxCR         NBREQ         LL_DMAMUX_SetSyncRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
+{
+  (void)(DMAMUXx);
+  MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
+}
+
+/**
+  * @brief  Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
+  * @rmtoll CxCR         NBREQ         LL_DMAMUX_GetSyncRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Between Min_Data = 1 and Max_Data = 32
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
+}
+
+/**
+  * @brief  Set the polarity of the signal on which the DMA request is synchronized.
+  * @rmtoll CxCR         SPOL          LL_DMAMUX_SetSyncPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
+{
+  (void)(DMAMUXx);
+  MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
+}
+
+/**
+  * @brief  Get the polarity of the signal on which the DMA request is synchronized.
+  * @rmtoll CxCR         SPOL          LL_DMAMUX_GetSyncPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
+}
+
+/**
+  * @brief  Enable the Event Generation on DMAMUX channel x.
+  * @rmtoll CxCR         EGE           LL_DMAMUX_EnableEventGeneration
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
+}
+
+/**
+  * @brief  Disable the Event Generation on DMAMUX channel x.
+  * @rmtoll CxCR         EGE           LL_DMAMUX_DisableEventGeneration
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
+}
+
+/**
+  * @brief  Check if the Event Generation on DMAMUX channel x is enabled or disabled.
+  * @rmtoll CxCR         EGE           LL_DMAMUX_IsEnabledEventGeneration
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the synchronization mode.
+  * @rmtoll CxCR         SE            LL_DMAMUX_EnableSync
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
+}
+
+/**
+  * @brief  Disable the synchronization mode.
+  * @rmtoll CxCR         SE            LL_DMAMUX_DisableSync
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
+}
+
+/**
+  * @brief  Check if the synchronization mode is enabled or disabled.
+  * @rmtoll CxCR         SE            LL_DMAMUX_IsEnabledSync
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set DMAMUX synchronization ID  on DMAMUX Channel x.
+  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_SetSyncID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  SyncID This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
+  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
+  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
+  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
+  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
+  *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
+{
+  (void)(DMAMUXx);
+  MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
+}
+
+/**
+  * @brief  Get DMAMUX synchronization ID  on DMAMUX Channel x.
+  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_GetSyncID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
+  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
+  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
+  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
+  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
+  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
+  *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID));
+}
+
+/**
+  * @brief  Enable the Request Generator.
+  * @rmtoll RGxCR        GE            LL_DMAMUX_EnableRequestGen
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  (void)(DMAMUXx);
+  SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
+}
+
+/**
+  * @brief  Disable the Request Generator.
+  * @rmtoll RGxCR        GE            LL_DMAMUX_DisableRequestGen
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  (void)(DMAMUXx);
+  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
+}
+
+/**
+  * @brief  Check if the Request Generator is enabled or disabled.
+  * @rmtoll RGxCR        GE            LL_DMAMUX_IsEnabledRequestGen
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  (void)(DMAMUXx);
+  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the polarity of the signal on which the DMA request is generated.
+  * @rmtoll RGxCR        GPOL          LL_DMAMUX_SetRequestGenPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
+                                                     uint32_t Polarity)
+{
+  UNUSED(DMAMUXx);
+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
+                                                       (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
+}
+
+/**
+  * @brief  Get the polarity of the signal on which the DMA request is generated.
+  * @rmtoll RGxCR        GPOL          LL_DMAMUX_GetRequestGenPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  UNUSED(DMAMUXx);
+  return (READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
+                                                             (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL));
+}
+
+/**
+  * @brief  Set the number of DMA request that will be autorized after a generation event.
+  * @note   This field can only be written when Generator is disabled.
+  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_SetGenRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
+                                               uint32_t RequestNb)
+{
+  UNUSED(DMAMUXx);
+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
+                                                       (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
+}
+
+/**
+  * @brief  Get the number of DMA request that will be autorized after a generation event.
+  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_GetGenRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @retval Between Min_Data = 1 and Max_Data = 32
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
+                                                              (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
+}
+
+/**
+  * @brief  Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
+  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_SetRequestSignalID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @param  RequestSignalID This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
+  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
+                                                  uint32_t RequestSignalID)
+{
+  UNUSED(DMAMUXx);
+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
+                                                       (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
+}
+
+/**
+  * @brief  Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
+  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_GetRequestSignalID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
+  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
+  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  UNUSED(DMAMUXx);
+  return (READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
+                                                             (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 0.
+  * @rmtoll CSR          SOF0          LL_DMAMUX_IsActiveFlag_SO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 1.
+  * @rmtoll CSR          SOF1          LL_DMAMUX_IsActiveFlag_SO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 2.
+  * @rmtoll CSR          SOF2          LL_DMAMUX_IsActiveFlag_SO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 3.
+  * @rmtoll CSR          SOF3          LL_DMAMUX_IsActiveFlag_SO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 4.
+  * @rmtoll CSR          SOF4          LL_DMAMUX_IsActiveFlag_SO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 5.
+  * @rmtoll CSR          SOF5          LL_DMAMUX_IsActiveFlag_SO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 6.
+  * @rmtoll CSR          SOF6          LL_DMAMUX_IsActiveFlag_SO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 7.
+  * @rmtoll CSR          SOF7          LL_DMAMUX_IsActiveFlag_SO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 8.
+  * @rmtoll CSR          SOF8          LL_DMAMUX_IsActiveFlag_SO8
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 9.
+  * @rmtoll CSR          SOF9          LL_DMAMUX_IsActiveFlag_SO9
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 10.
+  * @rmtoll CSR          SOF10         LL_DMAMUX_IsActiveFlag_SO10
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 11.
+  * @rmtoll CSR          SOF11         LL_DMAMUX_IsActiveFlag_SO11
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
+}
+
+#if defined (DMAMUX_CSR_SOF12)
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 12.
+  * @rmtoll CSR          SOF12         LL_DMAMUX_IsActiveFlag_SO12
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
+}
+#endif /* DMAMUX_CSR_SOF12 */
+
+#if defined (DMAMUX_CSR_SOF13)
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 13.
+  * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO13
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
+}
+#endif /* DMAMUX_CSR_SOF13 */
+
+#if defined (DMAMUX_CSR_SOF14)
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 14.
+  * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO14
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
+}
+#endif /* DMAMUX_CSR_SOF14 */
+
+#if defined (DMAMUX_CSR_SOF15)
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 15.
+  * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO15
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
+}
+#endif /* DMAMUX_CSR_SOF15 */
+
+/**
+  * @brief  Get Request Generator 0 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF0           LL_DMAMUX_IsActiveFlag_RGO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 1 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF1           LL_DMAMUX_IsActiveFlag_RGO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 2 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF2           LL_DMAMUX_IsActiveFlag_RGO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 3 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF3           LL_DMAMUX_IsActiveFlag_RGO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 0.
+  * @rmtoll CFR          CSOF0         LL_DMAMUX_ClearFlag_SO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 1.
+  * @rmtoll CFR          CSOF1         LL_DMAMUX_ClearFlag_SO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 2.
+  * @rmtoll CFR          CSOF2         LL_DMAMUX_ClearFlag_SO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 3.
+  * @rmtoll CFR          CSOF3         LL_DMAMUX_ClearFlag_SO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 4.
+  * @rmtoll CFR          CSOF4         LL_DMAMUX_ClearFlag_SO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 5.
+  * @rmtoll CFR          CSOF5         LL_DMAMUX_ClearFlag_SO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 6.
+  * @rmtoll CFR          CSOF6         LL_DMAMUX_ClearFlag_SO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 7.
+  * @rmtoll CFR          CSOF7         LL_DMAMUX_ClearFlag_SO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 8.
+  * @rmtoll CFR          CSOF8         LL_DMAMUX_ClearFlag_SO8
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 9.
+  * @rmtoll CFR          CSOF9         LL_DMAMUX_ClearFlag_SO9
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 10.
+  * @rmtoll CFR          CSOF10        LL_DMAMUX_ClearFlag_SO10
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 11.
+  * @rmtoll CFR          CSOF11        LL_DMAMUX_ClearFlag_SO11
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
+}
+
+#if defined (DMAMUX_CFR_CSOF12)
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 12.
+  * @rmtoll CFR          CSOF12        LL_DMAMUX_ClearFlag_SO12
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12);
+}
+#endif /* DMAMUX_CFR_CSOF12 */
+
+#if defined (DMAMUX_CFR_CSOF13)
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 13.
+  * @rmtoll CFR          CSOF13        LL_DMAMUX_ClearFlag_SO13
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13);
+}
+#endif /* DMAMUX_CFR_CSOF13 */
+
+#if defined (DMAMUX_CFR_CSOF14)
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 14.
+  * @rmtoll CFR          CSOF14        LL_DMAMUX_ClearFlag_SO14
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF14);
+}
+#endif /* DMAMUX_CFR_CSOF14 */
+
+#if defined (DMAMUX_CFR_CSOF15)
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 15.
+  * @rmtoll CFR          CSOF15        LL_DMAMUX_ClearFlag_SO15
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF15);
+}
+#endif /* DMAMUX_CFR_CSOF15 */
+
+/**
+  * @brief  Clear Request Generator 0 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF0          LL_DMAMUX_ClearFlag_RGO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
+}
+
+/**
+  * @brief  Clear Request Generator 1 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF1          LL_DMAMUX_ClearFlag_RGO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
+}
+
+/**
+  * @brief  Clear Request Generator 2 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF2          LL_DMAMUX_ClearFlag_RGO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
+}
+
+/**
+  * @brief  Clear Request Generator 3 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF3          LL_DMAMUX_ClearFlag_RGO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll CxCR         SOIE          LL_DMAMUX_EnableIT_SO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
+}
+
+/**
+  * @brief  Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll CxCR         SOIE          LL_DMAMUX_DisableIT_SO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
+}
+
+/**
+  * @brief  Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
+  * @rmtoll CxCR         SOIE          LL_DMAMUX_IsEnabledIT_SO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  (void)(DMAMUXx);
+  return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll RGxCR        OIE           LL_DMAMUX_EnableIT_RGO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  UNUSED(DMAMUXx);
+  SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
+                                                    (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE);
+}
+
+/**
+  * @brief  Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll RGxCR        OIE           LL_DMAMUX_DisableIT_RGO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  UNUSED(DMAMUXx);
+  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
+                                                      (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE);
+}
+
+/**
+  * @brief  Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
+  * @rmtoll RGxCR        OIE           LL_DMAMUX_IsEnabledIT_RGO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  UNUSED(DMAMUXx);
+  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
+                                                              (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMAMUX1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_DMAMUX_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h
new file mode 100644
index 0000000..db1d280
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h
@@ -0,0 +1,1422 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_EXTI_H
+#define __STM32G4xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
+                                     This parameter can be set either to ENABLE or DISABLE */
+
+  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+  * @{
+  */
+#define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
+#define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
+#define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
+#define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
+#define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
+#define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
+#define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
+#define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
+#define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
+#define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
+#define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
+#define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
+#define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
+#define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
+#define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
+#define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
+#if defined(EXTI_IMR1_IM16)
+#define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */
+#endif /* EXTI_IMR1_IM16 */
+#define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
+#if defined(EXTI_IMR1_IM18)
+#define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
+#endif /* EXTI_IMR1_IM18 */
+#define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
+#if defined(EXTI_IMR1_IM20)
+#define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
+#endif /* EXTI_IMR1_IM20 */
+#if defined(EXTI_IMR1_IM21)
+#define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
+#endif /* EXTI_IMR1_IM21 */
+#if defined(EXTI_IMR1_IM22)
+#define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
+#endif /* EXTI_IMR1_IM22 */
+#define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
+#if defined(EXTI_IMR1_IM24)
+#define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
+#endif /* EXTI_IMR1_IM24 */
+#if defined(EXTI_IMR1_IM25)
+#define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
+#endif /* EXTI_IMR1_IM25 */
+#if defined(EXTI_IMR1_IM26)
+#define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */
+#endif /* EXTI_IMR1_IM26 */
+#if defined(EXTI_IMR1_IM27)
+#define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */
+#endif /* EXTI_IMR1_IM27 */
+#if defined(EXTI_IMR1_IM28)
+#define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
+#endif /* EXTI_IMR1_IM28 */
+#if defined(EXTI_IMR1_IM29)
+#define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
+#endif /* EXTI_IMR1_IM29 */
+#if defined(EXTI_IMR1_IM30)
+#define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
+#endif /* EXTI_IMR1_IM30 */
+#if defined(EXTI_IMR1_IM31)
+#define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
+#endif /* EXTI_IMR1_IM31 */
+#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/
+
+#if defined(EXTI_IMR2_IM32)
+#define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
+#endif /* EXTI_IMR2_IM32 */
+#if defined(EXTI_IMR2_IM33)
+#define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
+#endif /* EXTI_IMR2_IM33 */
+#if defined(EXTI_IMR2_IM34)
+#define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
+#endif /* EXTI_IMR2_IM34 */
+#if defined(EXTI_IMR2_IM35)
+#define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
+#endif /* EXTI_IMR2_IM35 */
+#if defined(EXTI_IMR2_IM36)
+#define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
+#endif /* EXTI_IMR2_IM36 */
+#if defined(EXTI_IMR2_IM37)
+#define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */
+#endif /* EXTI_IMR2_IM37 */
+#if defined(EXTI_IMR2_IM38)
+#define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */
+#endif /* EXTI_IMR2_IM38 */
+#if defined(EXTI_IMR2_IM39)
+#define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */
+#endif /* EXTI_IMR2_IM39 */
+#if defined(EXTI_IMR2_IM40)
+#define LL_EXTI_LINE_40                EXTI_IMR2_IM40          /*!< Extended line 40 */
+#endif /* EXTI_IMR2_IM40 */
+#if defined(EXTI_IMR2_IM41)
+#define LL_EXTI_LINE_41                EXTI_IMR2_IM41          /*!< Extended line 41 */
+#endif /* EXTI_IMR2_IM41 */
+#if defined(EXTI_IMR2_IM42)
+#define LL_EXTI_LINE_42                EXTI_IMR2_IM42          /*!< Extended line 42 */
+#endif /* EXTI_IMR2_IM42 */
+#define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE              0x00000000U             /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+  * @{
+  */
+#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+  * @}
+  */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in EXTI register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in EXTI register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+  * @{
+  */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR1, ExtiLine);
+}
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
+  * @note The reset value for the direct lines (lines from 32 to 34, line
+  *       39) is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35 (*)
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @note   (*): Available in some devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
+  * @note The reset value for the direct lines (lines from 32 to 34, line
+  *       39) is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35 (*)
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @note   (*): Available in some devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
+  * @note The reset value for the direct lines (lines from 32 to 34, line
+  *       39) is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35 (*)
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @note   (*): Available in some devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35 (*)
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @note   (*): Available in some devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35 (*)
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @note   (*): Available in some devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35 (*)
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @note   (*): Available in some devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  * @note   (*): Available in some devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  * @note   (*): Available in some devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
+  * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  * @note   (*): Available in some devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  * @note   (*): Available in some devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  * @note   (*): Available in some devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
+  * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  * @note   (*): Available in some devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
+  * @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR1
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER1, ExtiLine);
+}
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
+  * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  * @note   (*): Available in some devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER2, ExtiLine);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_IsActiveFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  * @note   (*): Available in some devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_ReadFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
+}
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  * @note   (*): Available in some devices
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
+}
+
+/**
+  * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_ClearFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31 (*)
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR1, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for  Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32 (*)
+  *         @arg @ref LL_EXTI_LINE_33 (*)
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  * @note   (*): Available in some devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR2, ExtiLine);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* EXTI */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_EXTI_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h
new file mode 100644
index 0000000..faf0e9a
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h
@@ -0,0 +1,994 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_GPIO_H
+#define STM32G4xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
+
+/** @defgroup GPIO_LL GPIO
+  * @{
+  */
+/** MISRA C:2012 deviation rule has been granted for following rules:
+  * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
+  * which may be out of array bounds [..,UNKNOWN] in following APIs:
+  * LL_GPIO_GetAFPin_0_7
+  * LL_GPIO_SetAFPin_0_7
+  * LL_GPIO_SetAFPin_8_15
+  * LL_GPIO_GetAFPin_8_15
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL GPIO Init Structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+  * @{
+  */
+#define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
+                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
+                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
+                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
+                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
+                                           GPIO_BSRR_BS15) /*!< Select all pins */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+  * @{
+  */
+#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+  * @{
+  */
+#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
+#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
+/**
+  * @}
+  */
+#define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
+#define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
+#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
+#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+  * @{
+  */
+#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+  * @{
+  */
+#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+  MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->MODER,
+                             (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @param  OutputType This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+  * @brief  Return gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+}
+
+/**
+  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Speed This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
+{
+  MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),
+             (Speed << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
+                             (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Pull This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+  MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->PUPDR,
+                             (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
+             (Alternate << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+                             (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
+             (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+                             (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
+}
+
+
+/**
+  * @brief  Lock configuration of several pins for a dedicated port.
+  * @note   When the lock sequence has been applied on a port bit, the
+  *         value of this port bit can no longer be modified until the
+  *         next reset.
+  * @note   Each lock bit freezes a specific configuration register
+  *         (control and alternate function registers).
+  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  __IO uint32_t temp;
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  WRITE_REG(GPIOx->LCKR, PinMask);
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  /* Read LCKR register. This read is mandatory to complete key lock sequence */
+  temp = READ_REG(GPIOx->LCKR);
+  (void) temp;
+}
+
+/**
+  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
+  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
+  * @param  GPIOx GPIO Port
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+  return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+  * @{
+  */
+
+/**
+  * @brief  Return full input data register value for a dedicated port.
+  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
+  * @param  GPIOx GPIO Port
+  * @retval Input data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Write output data register for the port.
+  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
+  * @param  GPIOx GPIO Port
+  * @param  PortValue Level value for each pin of the port
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+  WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+  * @brief  Return full output data register value for a dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
+  * @param  GPIOx GPIO Port
+  * @retval Output data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set several pins to high level on dedicated gpio port.
+  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+  * @brief  Set several pins to low level on dedicated gpio port.
+  * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BRR, PinMask);
+}
+
+/**
+  * @brief  Toggle data value for several pin of dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  uint32_t odr = READ_REG(GPIOx->ODR);
+  WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_GPIO_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_i2c.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_i2c.h
new file mode 100644
index 0000000..9350781
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_i2c.h
@@ -0,0 +1,2272 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_I2C_H
+#define STM32G4xx_LL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
+
+/** @defgroup I2C_LL I2C
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Constants I2C Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_Private_Macros I2C Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
+                                     This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetMode(). */
+
+  uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
+                                     This parameter must be set by referring to the STM32CubeMX Tool and
+                                     the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetTiming(). */
+
+  uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
+                                     This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
+
+                                     This feature can be modified afterwards using unitary functions
+                                     @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+
+  uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
+                                     This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetDigitalFilter(). */
+
+  uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
+                                     This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetOwnAddress1(). */
+
+  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
+                                     match code or next received byte.
+                                     This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_AcknowledgeNextData(). */
+
+  uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+                                     This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetOwnAddress1(). */
+} LL_I2C_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_I2C_WriteReg function
+  * @{
+  */
+#define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
+#define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
+#define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
+#define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
+#define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
+#define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
+#define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
+#define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
+#define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_I2C_ReadReg function
+  * @{
+  */
+#define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
+#define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
+#define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
+#define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
+#define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
+#define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
+#define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
+#define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
+#define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
+#define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
+#define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
+#define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
+#define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
+#define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
+#define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
+  * @{
+  */
+#define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
+#define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
+#define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
+#define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
+#define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
+#define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
+#define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+  * @{
+  */
+#define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                 */
+#define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge           */
+#define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode
+                                                                         (Default address not acknowledge)        */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
+  * @{
+  */
+#define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
+#define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
+  * @{
+  */
+#define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
+#define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+  * @{
+  */
+#define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
+#define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
+  * @{
+  */
+#define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                 */
+#define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.   */
+#define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done.
+                                                                         All Address2 are acknowledged.        */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+  * @{
+  */
+#define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
+#define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
+  * @{
+  */
+#define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
+#define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
+  * @{
+  */
+#define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
+#define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_MODE Transfer End Mode
+  * @{
+  */
+#define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD           /*!< Enable I2C Reload mode.     */
+#define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND          /*!< Enable I2C Automatic end mode
+                                                                          with no HW PEC comparison.  */
+#define LL_I2C_MODE_SOFTEND                 0x00000000U              /*!< Enable I2C Software end mode
+                                                                          with no HW PEC comparison.  */
+#define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD       /*!< Enable SMBUS Automatic end mode
+                                                                          with HW PEC comparison.     */
+#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND      /*!< Enable SMBUS Automatic end mode
+                                                                          with HW PEC comparison.     */
+#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND      /*!< Enable SMBUS Software end mode
+                                                                          with HW PEC comparison.     */
+#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
+#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Software end mode with HW PEC comparison.    */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
+  * @{
+  */
+#define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U
+/*!< Don't Generate Stop and Start condition. */
+#define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)
+/*!< Generate Stop condition (Size should be set to 0).      */
+#define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Start for read request. */
+#define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Start for write request. */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Restart for read request, slave 7Bit address.  */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | \
+                                                       I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
+/*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for write request, slave 10Bit address.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
+  * @{
+  */
+#define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master,
+                                                                          slave enters receiver mode.  */
+#define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master,
+                                                                          slave enters transmitter mode.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for
+                                                                          transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for
+                                                                          reception */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
+  * @{
+  */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect
+                                                                          SCL low level timeout.              */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect
+                                                                          both SCL and SDA high level timeout.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
+  * @{
+  */
+#define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                 /*!< TimeoutA enable bit          */
+#define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                   /*!< TimeoutB (extended clock)
+                                                                                       enable bit                   */
+#define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
+                                                       I2C_TIMEOUTR_TEXTEN)       /*!< TimeoutA and TimeoutB
+(extended clock) enable bits */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in I2C register
+  * @param  __INSTANCE__ I2C Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in I2C register
+  * @param  __INSTANCE__ I2C Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
+  * @{
+  */
+/**
+  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
+  * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
+  * @param  __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+                           (tscldel = (SCLDEL+1)xtpresc)
+  * @param  __HOLD_TIME__  This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+                           (tsdadel = SDADELxtpresc)
+  * @param  __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+                            (tsclh = (SCLH+1)xtpresc)
+  * @param  __SCLL_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF.
+                            (tscll = (SCLL+1)xtpresc)
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
+  ((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
+   (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
+   (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
+   (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
+   (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable I2C peripheral (PE = 1).
+  * @rmtoll CR1          PE            LL_I2C_Enable
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Disable I2C peripheral (PE = 0).
+  * @note   When PE = 0, the I2C SCL and SDA lines are released.
+  *         Internal state machines and status bits are put back to their reset value.
+  *         When cleared, PE must be kept low for at least 3 APB clock cycles.
+  * @rmtoll CR1          PE            LL_I2C_Disable
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Check if the I2C peripheral is enabled or disabled.
+  * @rmtoll CR1          PE            LL_I2C_IsEnabled
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure Noise Filters (Analog and Digital).
+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
+  *         The filters can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
+  *         CR1          DNF           LL_I2C_ConfigFilters
+  * @param  I2Cx I2C Instance.
+  * @param  AnalogFilter This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
+  *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
+  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
+}
+
+/**
+  * @brief  Configure Digital Noise Filter.
+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
+  *         This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
+  * @param  I2Cx I2C Instance.
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
+  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
+}
+
+/**
+  * @brief  Get the current Digital Noise Filter configuration.
+  * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
+}
+
+/**
+  * @brief  Enable Analog Noise Filter.
+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+  * @brief  Disable Analog Noise Filter.
+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+  * @brief  Check if Analog Noise Filter is enabled or disabled.
+  * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA transmission requests.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA transmission requests.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA transmission requests are enabled or disabled.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA reception requests.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA reception requests.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA reception requests are enabled or disabled.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
+  *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
+  * @param  I2Cx I2C Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TXDR register */
+    data_reg_addr = (uint32_t) &(I2Cx->TXDR);
+  }
+  else
+  {
+    /* return address of RXDR register */
+    data_reg_addr = (uint32_t) &(I2Cx->RXDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @brief  Enable Clock stretching.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+  * @brief  Disable Clock stretching.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+  * @brief  Check if Clock stretching is enabled or disabled.
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable hardware byte control in slave mode.
+  * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+  * @brief  Disable hardware byte control in slave mode.
+  * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+  * @brief  Check if hardware byte control in slave mode is enabled or disabled.
+  * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Wakeup from STOP.
+  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @note   This bit can only be programmed when Digital Filter is disabled.
+  * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+  * @brief  Disable Wakeup from STOP.
+  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+  * @brief  Check if Wakeup from STOP is enabled or disabled.
+  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable General Call.
+  * @note   When enabled the Address 0x00 is ACKed.
+  * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+  * @brief  Disable General Call.
+  * @note   When disabled the Address 0x00 is NACKed.
+  * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+  * @brief  Check if General Call is enabled or disabled.
+  * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
+  * @note   Changing this bit is not allowed, when the START bit is set.
+  * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
+  * @param  I2Cx I2C Instance.
+  * @param  AddressingMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
+}
+
+/**
+  * @brief  Get the Master addressing mode.
+  * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
+}
+
+/**
+  * @brief  Set the Own Address1.
+  * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
+  *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+  * @param  OwnAddrSize This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
+  *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+  MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+  * @brief  Enable acknowledge on Own Address1 match address.
+  * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+  * @brief  Disable acknowledge on Own Address1 match address.
+  * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
+  * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the 7bits Own Address2.
+  * @note   This action has no effect if own address2 is enabled.
+  * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
+  *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
+  * @param  OwnAddrMask This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
+{
+  MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+}
+
+/**
+  * @brief  Enable acknowledge on Own Address2 match address.
+  * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+  * @brief  Disable  acknowledge on Own Address2 match address.
+  * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
+  * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
+  * @param  I2Cx I2C Instance.
+  * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
+{
+  WRITE_REG(I2Cx->TIMINGR, Timing);
+}
+
+/**
+  * @brief  Get the Timing Prescaler setting.
+  * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
+}
+
+/**
+  * @brief  Get the SCL low period setting.
+  * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
+}
+
+/**
+  * @brief  Get the SCL high period setting.
+  * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
+}
+
+/**
+  * @brief  Get the SDA hold time.
+  * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
+}
+
+/**
+  * @brief  Get the SDA setup time.
+  * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
+}
+
+/**
+  * @brief  Configure peripheral mode.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
+  *         CR1          SMBDEN        LL_I2C_SetMode
+  * @param  I2Cx I2C Instance.
+  * @param  PeripheralMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_I2C
+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
+}
+
+/**
+  * @brief  Get peripheral mode.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
+  *         CR1          SMBDEN        LL_I2C_GetMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_I2C
+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
+}
+
+/**
+  * @brief  Enable SMBus alert (Host or Device mode)
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   SMBus Device mode:
+  *         - SMBus Alert pin is drived low and
+  *           Alert Response Address Header acknowledge is enabled.
+  *         SMBus Host mode:
+  *         - SMBus Alert pin management is supported.
+  * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+  * @brief  Disable SMBus alert (Host or Device mode)
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   SMBus Device mode:
+  *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+  *           Alert Response Address Header acknowledge is disabled.
+  *         SMBus Host mode:
+  *         - SMBus Alert pin management is not supported.
+  * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+  * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SMBus Packet Error Calculation (PEC).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+  * @brief  Disable SMBus Packet Error Calculation (PEC).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+  * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the SMBus Clock Timeout.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
+  *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
+  *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @param  TimeoutAMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  * @param  TimeoutB
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
+                                               uint32_t TimeoutB)
+{
+  MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
+             TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
+}
+
+/**
+  * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   These bits can only be programmed when TimeoutA is disabled.
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
+}
+
+/**
+  * @brief  Get the SMBus Clock TimeoutA setting.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
+}
+
+/**
+  * @brief  Set the SMBus Clock TimeoutA mode.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This bit can only be programmed when TimeoutA is disabled.
+  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutAMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
+}
+
+/**
+  * @brief  Get the SMBus Clock TimeoutA mode.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
+}
+
+/**
+  * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   These bits can only be programmed when TimeoutB is disabled.
+  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+  * @brief  Get the SMBus Extended Cumulative Clock TimeoutB setting.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+  * @brief  Enable the SMBus Clock Timeout.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+  * @brief  Disable the SMBus Clock Timeout.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+  * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
+           (ClockTimeout)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable TXIS interrupt.
+  * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+  * @brief  Disable TXIS interrupt.
+  * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+  * @brief  Check if the TXIS Interrupt is enabled or disabled.
+  * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable RXNE interrupt.
+  * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+  * @brief  Disable RXNE interrupt.
+  * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+  * @brief  Check if the RXNE Interrupt is enabled or disabled.
+  * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Address match interrupt (slave mode only).
+  * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+  * @brief  Disable Address match interrupt (slave mode only).
+  * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+  * @brief  Check if Address match interrupt is enabled or disabled.
+  * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Not acknowledge received interrupt.
+  * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+  * @brief  Disable Not acknowledge received interrupt.
+  * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+  * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
+  * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable STOP detection interrupt.
+  * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+  * @brief  Disable STOP detection interrupt.
+  * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+  * @brief  Check if STOP detection interrupt is enabled or disabled.
+  * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Transfer Complete interrupt.
+  * @note   Any of these events will generate interrupt :
+  *         Transfer Complete (TC)
+  *         Transfer Complete Reload (TCR)
+  * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+  * @brief  Disable Transfer Complete interrupt.
+  * @note   Any of these events will generate interrupt :
+  *         Transfer Complete (TC)
+  *         Transfer Complete Reload (TCR)
+  * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+  * @brief  Check if Transfer Complete interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Error interrupts.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   Any of these errors will generate interrupt :
+  *         Arbitration Loss (ARLO)
+  *         Bus Error detection (BERR)
+  *         Overrun/Underrun (OVR)
+  *         SMBus Timeout detection (TIMEOUT)
+  *         SMBus PEC error detection (PECERR)
+  *         SMBus Alert pin event detection (ALERT)
+  * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+  * @brief  Disable Error interrupts.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   Any of these errors will generate interrupt :
+  *         Arbitration Loss (ARLO)
+  *         Bus Error detection (BERR)
+  *         Overrun/Underrun (OVR)
+  *         SMBus Timeout detection (TIMEOUT)
+  *         SMBus PEC error detection (PECERR)
+  *         SMBus Alert pin event detection (ALERT)
+  * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+  * @brief  Check if Error interrupts are enabled or disabled.
+  * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
+  * @{
+  */
+
+/**
+  * @brief  Indicate the status of Transmit data register empty flag.
+  * @note   RESET: When next data is written in Transmit data register.
+  *         SET: When Transmit data register is empty.
+  * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Transmit interrupt flag.
+  * @note   RESET: When next data is written in Transmit data register.
+  *         SET: When Transmit data register is empty.
+  * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Receive data register not empty flag.
+  * @note   RESET: When Receive data register is read.
+  *         SET: When the received data is copied in Receive data register.
+  * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Address matched flag (slave mode).
+  * @note   RESET: Clear default value.
+  *         SET: When the received slave address matched with one of the enabled slave address.
+  * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Not Acknowledge received flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a NACK is received after a byte transmission.
+  * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Stop detection flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a Stop condition is detected.
+  * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Transfer complete flag (master mode).
+  * @note   RESET: Clear default value.
+  *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
+  * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Transfer complete flag (master mode).
+  * @note   RESET: Clear default value.
+  *         SET: When RELOAD=1 and NBYTES date have been transferred.
+  * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Bus error flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a misplaced Start or Stop condition is detected.
+  * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Arbitration lost flag.
+  * @note   RESET: Clear default value.
+  *         SET: When arbitration lost.
+  * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
+  * @note   RESET: Clear default value.
+  *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+  * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of SMBus PEC error flag in reception.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When the received PEC does not match with the PEC register content.
+  * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of SMBus Timeout detection flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When a timeout or extended clock timeout occurs.
+  * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of SMBus alert flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When SMBus host configuration, SMBus alert enabled and
+  *              a falling edge event occurs on SMBA pin.
+  * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Bus Busy flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a Start condition is detected.
+  * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Address Matched flag.
+  * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
+}
+
+/**
+  * @brief  Clear Not Acknowledge flag.
+  * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
+}
+
+/**
+  * @brief  Clear Stop detection flag.
+  * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
+}
+
+/**
+  * @brief  Clear Transmit data register empty flag (TXE).
+  * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
+  * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
+{
+  WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
+}
+
+/**
+  * @brief  Clear Bus error flag.
+  * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
+}
+
+/**
+  * @brief  Clear Arbitration lost flag.
+  * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
+}
+
+/**
+  * @brief  Clear Overrun/Underrun flag.
+  * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
+}
+
+/**
+  * @brief  Clear SMBus PEC error flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
+}
+
+/**
+  * @brief  Clear SMBus Timeout detection flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
+}
+
+/**
+  * @brief  Clear SMBus Alert flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable automatic STOP condition generation (master mode).
+  * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
+  *         This bit has no effect in slave mode or when RELOAD bit is set.
+  * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+  * @brief  Disable automatic STOP condition generation (master mode).
+  * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
+  * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+  * @brief  Check if automatic STOP condition is enabled or disabled.
+  * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable reload mode (master mode).
+  * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
+  * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+  * @brief  Disable reload mode (master mode).
+  * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
+  * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+  * @brief  Check if reload mode is enabled or disabled.
+  * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the number of bytes for transfer.
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
+  * @param  I2Cx I2C Instance.
+  * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
+}
+
+/**
+  * @brief  Get the number of bytes configured for transfer.
+  * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
+}
+
+/**
+  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
+            or next received byte.
+  * @note   Usage in Slave mode only.
+  * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
+  * @param  I2Cx I2C Instance.
+  * @param  TypeAcknowledge This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ACK
+  *         @arg @ref LL_I2C_NACK
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
+}
+
+/**
+  * @brief  Generate a START or RESTART condition
+  * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
+  *         This action has no effect when RELOAD is set.
+  * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_START);
+}
+
+/**
+  * @brief  Generate a STOP condition after the current byte transfer (master mode).
+  * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
+}
+
+/**
+  * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
+  * @note   The master sends the complete 10bit slave address read sequence :
+  *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
+            in Read direction.
+  * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+  * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
+  * @note   The master only sends the first 7 bits of 10bit address in Read direction.
+  * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+  * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
+  * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the transfer direction (master mode).
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
+  * @param  I2Cx I2C Instance.
+  * @param  TransferRequest This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_REQUEST_WRITE
+  *         @arg @ref LL_I2C_REQUEST_READ
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
+}
+
+/**
+  * @brief  Get the transfer direction requested (master mode).
+  * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_REQUEST_WRITE
+  *         @arg @ref LL_I2C_REQUEST_READ
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
+}
+
+/**
+  * @brief  Configure the slave address for transfer (master mode).
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
+  * @param  I2Cx I2C Instance.
+  * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
+}
+
+/**
+  * @brief  Get the slave address programmed for transfer.
+  * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
+  *         CR2          ADD10         LL_I2C_HandleTransfer\n
+  *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
+  *         CR2          START         LL_I2C_HandleTransfer\n
+  *         CR2          STOP          LL_I2C_HandleTransfer\n
+  *         CR2          RELOAD        LL_I2C_HandleTransfer\n
+  *         CR2          NBYTES        LL_I2C_HandleTransfer\n
+  *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
+  *         CR2          HEAD10R       LL_I2C_HandleTransfer
+  * @param  I2Cx I2C Instance.
+  * @param  SlaveAddr Specifies the slave address to be programmed.
+  * @param  SlaveAddrSize This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
+  *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
+  * @param  TransferSize Specifies the number of bytes to be programmed.
+  *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
+  * @param  EndMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_RELOAD
+  *         @arg @ref LL_I2C_MODE_AUTOEND
+  *         @arg @ref LL_I2C_MODE_SOFTEND
+  *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
+  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
+  *         @arg @ref LL_I2C_GENERATE_STOP
+  *         @arg @ref LL_I2C_GENERATE_START_READ
+  *         @arg @ref LL_I2C_GENERATE_START_WRITE
+  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
+  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
+  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
+  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
+                                           uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
+             (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
+             I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+             I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
+             SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
+}
+
+/**
+  * @brief  Indicate the value of transfer direction (slave mode).
+  * @note   RESET: Write transfer, Slave enters in receiver mode.
+  *         SET: Read transfer, Slave enters in transmitter mode.
+  * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_DIRECTION_WRITE
+  *         @arg @ref LL_I2C_DIRECTION_READ
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
+}
+
+/**
+  * @brief  Return the slave matched address.
+  * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
+}
+
+/**
+  * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
+            or an Address Matched is received.
+  *         This bit has no effect when RELOAD bit is set.
+  *         This bit has no effect in device mode when SBC bit is not set.
+  * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
+}
+
+/**
+  * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the SMBus Packet Error byte calculated.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
+}
+
+/**
+  * @brief  Read Receive Data register.
+  * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+{
+  return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
+}
+
+/**
+  * @brief  Write in Transmit Data Register .
+  * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
+  * @param  I2Cx I2C Instance.
+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+  WRITE_REG(I2Cx->TXDR, Data);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
+ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* I2C1 || I2C2 || I2C3 || I2C4 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_I2C_H */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h
new file mode 100644
index 0000000..ea93064
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h
@@ -0,0 +1,2650 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_lpuart.h
+  * @author  MCD Application Team
+  * @brief   Header file of LPUART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_LPUART_H
+#define STM32G4xx_LL_LPUART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPUART1)
+
+/** @defgroup LPUART_LL LPUART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
+  * @{
+  */
+/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
+static const uint16_t LPUART_PRESCALER_TAB[] =
+{
+  (uint16_t)1,
+  (uint16_t)2,
+  (uint16_t)4,
+  (uint16_t)6,
+  (uint16_t)8,
+  (uint16_t)10,
+  (uint16_t)12,
+  (uint16_t)16,
+  (uint16_t)32,
+  (uint16_t)64,
+  (uint16_t)128,
+  (uint16_t)256
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
+  * @{
+  */
+/* Defines used in Baud Rate related macros and corresponding register setting computation */
+#define LPUART_LPUARTDIV_FREQ_MUL     256U
+#define LPUART_BRR_MASK               0x000FFFFFU
+#define LPUART_BRR_MIN_VALUE          0x00000300U
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL LPUART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
+                                           This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetPrescaler().*/
+
+  uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref LPUART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetHWFlowCtrl().*/
+
+} LL_LPUART_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
+  * @{
+  */
+#define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error clear flag */
+#define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error clear flag */
+#define LL_LPUART_ICR_NCF                  USART_ICR_NECF                /*!< Noise error detected clear flag */
+#define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error clear flag */
+#define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected clear flag */
+#define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete clear flag */
+#define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS clear flag */
+#define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match clear flag */
+#define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
+  * @{
+  */
+#define LL_LPUART_ISR_PE               USART_ISR_PE         /*!< Parity error flag */
+#define LL_LPUART_ISR_FE               USART_ISR_FE         /*!< Framing error flag */
+#define LL_LPUART_ISR_NE               USART_ISR_NE         /*!< Noise detected flag */
+#define LL_LPUART_ISR_ORE              USART_ISR_ORE        /*!< Overrun error flag */
+#define LL_LPUART_ISR_IDLE             USART_ISR_IDLE       /*!< Idle line detected flag */
+#define LL_LPUART_ISR_RXNE_RXFNE       USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#define LL_LPUART_ISR_TC               USART_ISR_TC         /*!< Transmission complete flag */
+#define LL_LPUART_ISR_TXE_TXFNF        USART_ISR_TXE_TXFNF  /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_LPUART_ISR_CTSIF            USART_ISR_CTSIF      /*!< CTS interrupt flag */
+#define LL_LPUART_ISR_CTS              USART_ISR_CTS        /*!< CTS flag */
+#define LL_LPUART_ISR_BUSY             USART_ISR_BUSY       /*!< Busy flag */
+#define LL_LPUART_ISR_CMF              USART_ISR_CMF        /*!< Character match flag */
+#define LL_LPUART_ISR_SBKF             USART_ISR_SBKF       /*!< Send break flag */
+#define LL_LPUART_ISR_RWU              USART_ISR_RWU        /*!< Receiver wakeup from Mute mode flag */
+#define LL_LPUART_ISR_WUF              USART_ISR_WUF        /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ISR_TEACK            USART_ISR_TEACK      /*!< Transmit enable acknowledge flag */
+#define LL_LPUART_ISR_REACK            USART_ISR_REACK      /*!< Receive enable acknowledge flag */
+#define LL_LPUART_ISR_TXFE             USART_ISR_TXFE       /*!< TX FIFO empty flag */
+#define LL_LPUART_ISR_RXFF             USART_ISR_RXFF       /*!< RX FIFO full flag */
+#define LL_LPUART_ISR_RXFT             USART_ISR_RXFT       /*!< RX FIFO threshold flag */
+#define LL_LPUART_ISR_TXFT             USART_ISR_TXFT       /*!< TX FIFO threshold flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
+  * @{
+  */
+#define LL_LPUART_CR1_IDLEIE         USART_CR1_IDLEIE         /*!< IDLE interrupt enable */
+#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
+                                                                   interrupt enable */
+#define LL_LPUART_CR1_TCIE           USART_CR1_TCIE           /*!< Transmission complete interrupt enable */
+#define LL_LPUART_CR1_TXEIE_TXFNFIE  USART_CR1_TXEIE_TXFNFIE  /*!< Transmit data register empty and TX FIFO
+                                                                   not full interrupt enable */
+#define LL_LPUART_CR1_PEIE           USART_CR1_PEIE           /*!< Parity error */
+#define LL_LPUART_CR1_CMIE           USART_CR1_CMIE           /*!< Character match interrupt enable */
+#define LL_LPUART_CR1_TXFEIE         USART_CR1_TXFEIE         /*!< TX FIFO empty interrupt enable */
+#define LL_LPUART_CR1_RXFFIE         USART_CR1_RXFFIE         /*!< RX FIFO full interrupt enable */
+#define LL_LPUART_CR3_EIE            USART_CR3_EIE            /*!< Error interrupt enable */
+#define LL_LPUART_CR3_CTSIE          USART_CR3_CTSIE          /*!< CTS interrupt enable */
+#define LL_LPUART_CR3_WUFIE          USART_CR3_WUFIE          /*!< Wakeup from Stop mode interrupt enable */
+#define LL_LPUART_CR3_TXFTIE         USART_CR3_TXFTIE         /*!< TX FIFO threshold interrupt enable */
+#define LL_LPUART_CR3_RXFTIE         USART_CR3_RXFTIE         /*!< RX FIFO threshold interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+  * @{
+  */
+#define LL_LPUART_FIFOTHRESHOLD_1_8        0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_4        0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_2        0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_3_4        0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_7_8        0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_8_8        0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DIRECTION Direction
+  * @{
+  */
+#define LL_LPUART_DIRECTION_NONE  0x00000000U                  /*!< Transmitter and Receiver are disabled           */
+#define LL_LPUART_DIRECTION_RX    USART_CR1_RE                 /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_LPUART_DIRECTION_TX    USART_CR1_TE                 /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled            */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_LPUART_PARITY_NONE 0x00000000U                    /*!< Parity control disabled                            */
+#define LL_LPUART_PARITY_EVEN USART_CR1_PCE                  /*!< Parity control enabled and Even Parity is selected */
+#define LL_LPUART_PARITY_ODD  (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_LPUART_WAKEUP_IDLELINE    0x00000000U    /*!<  LPUART wake up from Mute mode on Idle Line    */
+#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!<  LPUART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_8B 0x00000000U  /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
+  * @{
+  */
+#define LL_LPUART_PRESCALER_DIV1   0x00000000U                    /*!< Input clock not divided   */
+#define LL_LPUART_PRESCALER_DIV2   (USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 2  */
+#define LL_LPUART_PRESCALER_DIV4   (USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 4  */
+#define LL_LPUART_PRESCALER_DIV6   (USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 6  */
+#define LL_LPUART_PRESCALER_DIV8   (USART_PRESC_PRESCALER_2)      /*!< Input clock divided by 8  */
+#define LL_LPUART_PRESCALER_DIV10  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 10 */
+#define LL_LPUART_PRESCALER_DIV12  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 12 */
+#define LL_LPUART_PRESCALER_DIV16  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 16 */
+#define LL_LPUART_PRESCALER_DIV32  (USART_PRESC_PRESCALER_3)      /*!< Input clock divided by 32 */
+#define LL_LPUART_PRESCALER_DIV64  (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 64 */
+#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 128 */
+#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_LPUART_STOPBITS_1         0x00000000U             /*!< 1 stop bit */
+#define LL_LPUART_STOPBITS_2         USART_CR2_STOP_1        /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_LPUART_TXRX_STANDARD      0x00000000U        /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_LPUART_TXRX_SWAPPED       (USART_CR2_SWAP)   /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_RXPIN_LEVEL_STANDARD   0x00000000U       /*!< RX pin signal works using the standard logic levels */
+#define LL_LPUART_RXPIN_LEVEL_INVERTED   (USART_CR2_RXINV) /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_TXPIN_LEVEL_STANDARD  0x00000000U       /*!< TX pin signal works using the standard logic levels */
+#define LL_LPUART_TXPIN_LEVEL_INVERTED  (USART_CR2_TXINV) /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U       /*!< Logical data from the data register are send/received
+                                                               in positive/direct logic. (1=H, 0=L)                  */
+#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
+                                                               in negative/inverse logic. (1=L, 0=H).
+                                                               The parity bit is also inverted.                      */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U        /*!< data is transmitted/received with data bit 0 first,
+                                                            following the start bit */
+#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
+                                                            following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U     /*!< 4-bit address detection method selected */
+#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_LPUART_HWCONTROL_NONE    0x00000000U                       /*!< CTS and RTS hardware flow control disabled */
+#define LL_LPUART_HWCONTROL_RTS     USART_CR3_RTSE                    /*!< RTS output enabled, data is only requested
+                                                                           when there is space in the receive buffer  */
+#define LL_LPUART_HWCONTROL_CTS     USART_CR3_CTSE                    /*!< CTS mode enabled, data is only transmitted
+                                                                           when the nCTS input is asserted (tied to 0)*/
+#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_LPUART_WAKEUP_ON_ADDRESS   0x00000000U                          /*!< Wake up active on address match */
+#define LL_LPUART_WAKEUP_ON_STARTBIT  USART_CR3_WUS_1                      /*!< Wake up active on Start bit detection */
+#define LL_LPUART_WAKEUP_ON_RXNE      (USART_CR3_WUS_0 | USART_CR3_WUS_1)  /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_LPUART_DE_POLARITY_HIGH         0x00000000U    /*!< DE signal is active high */
+#define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP  /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U    /*!< Get address of data register used for transmission */
+#define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U    /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Compute LPUARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud Rate value to achieve
+  * @retval LPUARTDIV value to be used for BRR register filling
+  */
+#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
+  ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
+      * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  LPUART Enable
+  * @rmtoll CR1          UE            LL_LPUART_Enable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  LPUART Disable
+  * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
+  *         flags, in the LPUARTx_ISR are set to their default values.
+  * @note   In order to go into low-power mode without generating errors on the line,
+  *         the TE bit must be reset before and the software must wait
+  *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
+  *         The DMA requests are also reset when UE = 0 so the DMA channel must
+  *         be disabled before resetting the UE bit.
+  * @rmtoll CR1          UE            LL_LPUART_Disable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled
+  * @rmtoll CR1          UE            LL_LPUART_IsEnabled
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  FIFO Mode Enable
+  * @rmtoll CR1          FIFOEN        LL_LPUART_EnableFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  FIFO Mode Disable
+  * @rmtoll CR1          FIFOEN        LL_LPUART_DisableFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  Indicate if FIFO Mode is enabled
+  * @rmtoll CR1          FIFOEN        LL_LPUART_IsEnabledFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure TX FIFO Threshold
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_SetTXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return TX FIFO Threshold Configuration
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_GetTXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure RX FIFO Threshold
+  * @rmtoll CR3          RXFTCFG       LL_LPUART_SetRXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return RX FIFO Threshold Configuration
+  * @rmtoll CR3          RXFTCFG       LL_LPUART_GetRXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure TX and RX FIFOs Threshold
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_ConfigFIFOsThreshold\n
+  *         CR3          RXFTCFG       LL_LPUART_ConfigFIFOsThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  TXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @param  RXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
+                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+  * @brief  LPUART enabled in STOP Mode
+  * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
+  *         LPUART clock selection is HSI or LSE in RCC.
+  * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  LPUART disabled in STOP Mode
+  * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
+  * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled in STOP Mode
+  *         (able to wake up MCU from Stop mode or not)
+  * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
+  *         CR1          TE            LL_LPUART_SetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
+  *         CR1          TE            LL_LPUART_GetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_LPUART_SetParity\n
+  *         CR1          PCE           LL_LPUART_SetParity
+  * @param  LPUARTx LPUART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_LPUART_GetParity\n
+  *         CR1          PCE           LL_LPUART_GetParity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_SetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_GetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
+  * @rmtoll PRESC        PRESCALER     LL_LPUART_SetPrescaler
+  * @param  LPUARTx LPUART Instance
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
+  * @rmtoll PRESC        PRESCALER     LL_LPUART_GetPrescaler
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
+  *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
+  *         CR1          PCE           LL_LPUART_ConfigCharacter\n
+  *         CR1          M             LL_LPUART_ConfigCharacter\n
+  *         CR2          STOP          LL_LPUART_ConfigCharacter
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
+                                               uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  *
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Set Address of the LPUART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
+  *
+  * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock and expected Baud Rate values
+  * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
+  *         (Baud rate value != 0).
+  * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
+  *         a care should be taken when generating high baud rates using high PeriphClk
+  *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
+  * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                           uint32_t BaudRate)
+{
+  if (BaudRate != 0U)
+  {
+    LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
+{
+  uint32_t lpuartdiv;
+  uint32_t brrresult;
+  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
+
+  lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
+
+  if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
+  {
+    brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
+  }
+  else
+  {
+    brrresult = 0x0UL;
+  }
+
+  return (brrresult);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : c
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the LPUART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE
+
+/**
+  * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
+  * @rmtoll ISR          RXNE_RXFNE    LL_LPUART_IsActiveFlag_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF
+
+/**
+  * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
+  * @rmtoll ISR          TXE_TXFNF     LL_LPUART_IsActiveFlag_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS interrupt Flag is set or not
+  * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS Flag is set or not
+  * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
+  * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Empty Flag is set or not
+  * @rmtoll ISR          TXFE          LL_LPUART_IsActiveFlag_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Full Flag is set or not
+  * @rmtoll ISR          RXFF          LL_LPUART_IsActiveFlag_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Threshold Flag is set or not
+  * @rmtoll ISR          TXFT          LL_LPUART_IsActiveFlag_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Threshold Flag is set or not
+  * @rmtoll ISR          RXFT          LL_LPUART_IsActiveFlag_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise detected Flag
+  * @rmtoll ICR          NECF          LL_LPUART_ClearFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE
+
+/**
+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_EnableIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF
+
+/**
+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_EnableIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Empty Interrupt
+  * @rmtoll CR1          TXFEIE        LL_LPUART_EnableIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_LPUART_EnableIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Threshold Interrupt
+  * @rmtoll CR3          TXFTIE        LL_LPUART_EnableIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Threshold Interrupt
+  * @rmtoll CR3          RXFTIE        LL_LPUART_EnableIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE
+
+/**
+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_DisableIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF
+
+/**
+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_LPUART_DisableIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Empty Interrupt
+  * @rmtoll CR1          TXFEIE        LL_LPUART_DisableIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_LPUART_DisableIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Threshold Interrupt
+  * @rmtoll CR3          TXFTIE        LL_LPUART_DisableIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Threshold Interrupt
+  * @rmtoll CR3          RXFTIE        LL_LPUART_DisableIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
+
+/**
+  * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF
+
+/**
+  * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_IsEnabledIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
+  * @rmtoll CR1          TXFEIE        LL_LPUART_IsEnabledIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
+  * @rmtoll CR1          RXFFIE        LL_LPUART_IsEnabledIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
+  * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
+  * @rmtoll CR3          TXFTIE        LL_LPUART_IsEnabledIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
+  * @rmtoll CR3          RXFTIE        LL_LPUART_IsEnabledIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the LPUART data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
+  * @param  LPUARTx LPUART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
+{
+  return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
+{
+  return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
+{
+  LPUARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
+{
+  LPUARTx->TDR = Value & 0x1FFUL;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put LPUART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data and FIFO flush
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
+void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPUART1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_LPUART_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h
new file mode 100644
index 0000000..a15c7cf
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h
@@ -0,0 +1,1602 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_PWR_H
+#define STM32G4xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+#define LL_PWR_SCR_CSBF                    PWR_SCR_CSBF
+#define LL_PWR_SCR_CWUF                    PWR_SCR_CWUF
+#define LL_PWR_SCR_CWUF5                   PWR_SCR_CWUF5
+#define LL_PWR_SCR_CWUF4                   PWR_SCR_CWUF4
+#define LL_PWR_SCR_CWUF3                   PWR_SCR_CWUF3
+#define LL_PWR_SCR_CWUF2                   PWR_SCR_CWUF2
+#define LL_PWR_SCR_CWUF1                   PWR_SCR_CWUF1
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
+  * @{
+  */
+#define LL_PWR_SR1_WUFI                    PWR_SR1_WUFI
+#define LL_PWR_SR1_SBF                     PWR_SR1_SBF
+#define LL_PWR_SR1_WUF5                    PWR_SR1_WUF5
+#define LL_PWR_SR1_WUF4                    PWR_SR1_WUF4
+#define LL_PWR_SR1_WUF3                    PWR_SR1_WUF3
+#define LL_PWR_SR1_WUF2                    PWR_SR1_WUF2
+#define LL_PWR_SR1_WUF1                    PWR_SR1_WUF1
+#if defined(PWR_SR2_PVMO4)
+#define LL_PWR_SR2_PVMO4                   PWR_SR2_PVMO4
+#endif /* PWR_SR2_PVMO4 */
+#if defined(PWR_SR2_PVMO3)
+#define LL_PWR_SR2_PVMO3                   PWR_SR2_PVMO3
+#endif /* PWR_SR2_PVMO3 */
+#if defined(PWR_SR2_PVMO2)
+#define LL_PWR_SR2_PVMO2                   PWR_SR2_PVMO2
+#endif /* PWR_SR2_PVMO2 */
+#if defined(PWR_SR2_PVMO1)
+#define LL_PWR_SR2_PVMO1                   PWR_SR2_PVMO1
+#endif /* PWR_SR2_PVMO1 */
+#define LL_PWR_SR2_PVDO                    PWR_SR2_PVDO
+#define LL_PWR_SR2_VOSF                    PWR_SR2_VOSF
+#define LL_PWR_SR2_REGLPF                  PWR_SR2_REGLPF
+#define LL_PWR_SR2_REGLPS                  PWR_SR2_REGLPS
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
+  * @{
+  */
+#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR1_VOS_0)
+#define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR1_VOS_1)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
+  * @{
+  */
+#define LL_PWR_MODE_STOP0                  (PWR_CR1_LPMS_STOP0)
+#define LL_PWR_MODE_STOP1                  (PWR_CR1_LPMS_STOP1)
+#define LL_PWR_MODE_STANDBY                (PWR_CR1_LPMS_STANDBY)
+#define LL_PWR_MODE_SHUTDOWN               (PWR_CR1_LPMS_SHUTDOWN)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
+  * @{
+  */
+#if defined(PWR_CR2_PVME1)
+#define LL_PWR_PVM_VDDA_COMP               (PWR_CR2_PVME1)     /* Monitoring VDDA vs. x.xV */
+#endif
+#if defined(PWR_CR2_PVME2)
+#define LL_PWR_PVM_VDDA_FASTDAC            (PWR_CR2_PVME2)     /* Monitoring VDDA vs. x.xV */
+#endif
+#if defined(PWR_CR2_PVME3)
+#define LL_PWR_PVM_VDDA_ADC                (PWR_CR2_PVME3)     /* Monitoring VDDA vs. 1.62V  */
+#endif
+#if defined(PWR_CR2_PVME4)
+#define LL_PWR_PVM_VDDA_OPAMP_DAC          (PWR_CR2_PVME4)     /* Monitoring VDDA vs. 1x.xV   */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
+  * @{
+  */
+#define LL_PWR_PVDLEVEL_0                  (PWR_CR2_PLS_LEV0)  /* VPVD0 around 2.0 V */
+#define LL_PWR_PVDLEVEL_1                  (PWR_CR2_PLS_LEV1)  /* VPVD1 around 2.2 V */
+#define LL_PWR_PVDLEVEL_2                  (PWR_CR2_PLS_LEV2)  /* VPVD2 around 2.4 V */
+#define LL_PWR_PVDLEVEL_3                  (PWR_CR2_PLS_LEV3)  /* VPVD3 around 2.5 V */
+#define LL_PWR_PVDLEVEL_4                  (PWR_CR2_PLS_LEV4)  /* VPVD4 around 2.6 V */
+#define LL_PWR_PVDLEVEL_5                  (PWR_CR2_PLS_LEV5)  /* VPVD5 around 2.8 V */
+#define LL_PWR_PVDLEVEL_6                  (PWR_CR2_PLS_LEV6)  /* VPVD6 around 2.9 V */
+#define LL_PWR_PVDLEVEL_7                  (PWR_CR2_PLS_LEV7)  /* External input analog voltage   (Compare internally to VREFINT) */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_WAKEUP WAKEUP
+  * @{
+  */
+#define LL_PWR_WAKEUP_PIN1                 (PWR_CR3_EWUP1)
+#define LL_PWR_WAKEUP_PIN2                 (PWR_CR3_EWUP2)
+#define LL_PWR_WAKEUP_PIN3                 (PWR_CR3_EWUP3)
+#define LL_PWR_WAKEUP_PIN4                 (PWR_CR3_EWUP4)
+#define LL_PWR_WAKEUP_PIN5                 (PWR_CR3_EWUP5)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
+  * @{
+  */
+#define LL_PWR_BATT_CHARG_RESISTOR_5K      ((uint32_t)0x00000000)
+#define LL_PWR_BATT_CHARGRESISTOR_1_5K     (PWR_CR4_VBRS)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GPIO GPIO
+  * @{
+  */
+#define LL_PWR_GPIO_A                      ((uint32_t)(&(PWR->PUCRA)))
+#define LL_PWR_GPIO_B                      ((uint32_t)(&(PWR->PUCRB)))
+#define LL_PWR_GPIO_C                      ((uint32_t)(&(PWR->PUCRC)))
+#define LL_PWR_GPIO_D                      ((uint32_t)(&(PWR->PUCRD)))
+#define LL_PWR_GPIO_E                      ((uint32_t)(&(PWR->PUCRE)))
+#define LL_PWR_GPIO_F                      ((uint32_t)(&(PWR->PUCRF)))
+#define LL_PWR_GPIO_G                      ((uint32_t)(&(PWR->PUCRG)))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
+  * @{
+  */
+#define LL_PWR_GPIO_BIT_0                  ((uint32_t)0x00000001)
+#define LL_PWR_GPIO_BIT_1                  ((uint32_t)0x00000002)
+#define LL_PWR_GPIO_BIT_2                  ((uint32_t)0x00000004)
+#define LL_PWR_GPIO_BIT_3                  ((uint32_t)0x00000008)
+#define LL_PWR_GPIO_BIT_4                  ((uint32_t)0x00000010)
+#define LL_PWR_GPIO_BIT_5                  ((uint32_t)0x00000020)
+#define LL_PWR_GPIO_BIT_6                  ((uint32_t)0x00000040)
+#define LL_PWR_GPIO_BIT_7                  ((uint32_t)0x00000080)
+#define LL_PWR_GPIO_BIT_8                  ((uint32_t)0x00000100)
+#define LL_PWR_GPIO_BIT_9                  ((uint32_t)0x00000200)
+#define LL_PWR_GPIO_BIT_10                 ((uint32_t)0x00000400)
+#define LL_PWR_GPIO_BIT_11                 ((uint32_t)0x00000800)
+#define LL_PWR_GPIO_BIT_12                 ((uint32_t)0x00001000)
+#define LL_PWR_GPIO_BIT_13                 ((uint32_t)0x00002000)
+#define LL_PWR_GPIO_BIT_14                 ((uint32_t)0x00004000)
+#define LL_PWR_GPIO_BIT_15                 ((uint32_t)0x00008000)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+  * @{
+  */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in PWR register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in PWR register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Switch the regulator from main mode to low-power mode
+  * @rmtoll CR1          LPR           LL_PWR_EnableLowPowerRunMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_LPR);
+}
+
+/**
+  * @brief  Switch the regulator from low-power mode to main mode
+  * @rmtoll CR1          LPR           LL_PWR_DisableLowPowerRunMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
+}
+
+/**
+  * @brief  Check if the regulator is in low-power mode
+  * @rmtoll CR1          LPR           LL_PWR_IsEnabledLowPowerRunMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->CR1, PWR_CR1_LPR);
+
+  return ((temp == (PWR_CR1_LPR))?1U:0U);
+
+}
+
+/**
+  * @brief  Switch from run main mode to run low-power mode.
+  * @rmtoll CR1          LPR           LL_PWR_EnterLowPowerRunMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
+{
+  LL_PWR_EnableLowPowerRunMode();
+}
+
+/**
+  * @brief  Switch from run main mode to low-power mode.
+  * @rmtoll CR1          LPR           LL_PWR_ExitLowPowerRunMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
+{
+  LL_PWR_DisableLowPowerRunMode();
+}
+
+/**
+  * @brief  Set the main internal regulator output voltage
+  * @rmtoll CR1          VOS           LL_PWR_SetRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
+}
+
+/**
+  * @brief  Get the main internal regulator output voltage
+  * @rmtoll CR1          VOS           LL_PWR_GetRegulVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
+}
+
+#if defined(PWR_CR5_R1MODE)
+/**
+  * @brief  Enable main regulator voltage range 1 boost mode
+  * @rmtoll CR5          R1MODE        LL_PWR_EnableRange1BoostMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void)
+{
+  CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
+}
+
+/**
+  * @brief  Disable main regulator voltage range 1 boost mode
+  * @rmtoll CR5          R1MODE        LL_PWR_DisableRange1BoostMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void)
+{
+  SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
+}
+
+/**
+  * @brief  Check if the main regulator voltage range 1 boost mode is enabled
+  * @rmtoll CR5          R1MODE        LL_PWR_IsEnabledRange1BoostMode
+  * @retval Inverted state of bit (0 or 1).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->CR5, PWR_CR5_R1MODE);
+
+  return ((temp == (0U))?1U:0U);
+}
+#endif /* PWR_CR5_R1MODE */
+
+/**
+  * @brief  Enable access to the backup domain
+  * @rmtoll CR1          DBP           LL_PWR_EnableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain
+  * @rmtoll CR1          DBP           LL_PWR_DisableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Check if the backup domain is enabled
+  * @rmtoll CR1          DBP           LL_PWR_IsEnabledBkUpAccess
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->CR1, PWR_CR1_DBP);
+
+  return ((temp == (PWR_CR1_DBP))?1U:0U);
+
+}
+
+/**
+  * @brief  Set Low-Power mode
+  * @rmtoll CR1          LPMS          LL_PWR_SetPowerMode
+  * @param  LowPowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_MODE_STOP0
+  *         @arg @ref LL_PWR_MODE_STOP1
+  *         @arg @ref LL_PWR_MODE_STANDBY
+  *         @arg @ref LL_PWR_MODE_SHUTDOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
+}
+
+/**
+  * @brief  Get Low-Power mode
+  * @rmtoll CR1          LPMS          LL_PWR_GetPowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_MODE_STOP0
+  *         @arg @ref LL_PWR_MODE_STOP1
+  *         @arg @ref LL_PWR_MODE_STANDBY
+  *         @arg @ref LL_PWR_MODE_SHUTDOWN
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
+}
+
+#if defined(PWR_CR3_UCPD_STDBY)
+/**
+  * @brief  Enable the USB Type-C and Power Delivery memorization in Standby mode.
+  * @note   This function must be called just before entering Standby mode.
+  * @rmtoll CR3          UCPD_STDBY    LL_PWR_EnableUCPDStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
+}
+
+/**
+  * @brief  Disable the USB Type-C and Power Delivery memorization in Standby mode.
+  * @note   This function must be called after exiting Standby mode and before any
+  *         UCPD configuration update.
+  * @rmtoll CR3          UCPD_STDBY     LL_PWR_DisableUCPDStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
+}
+
+/**
+  * @brief  Check the USB Type-C and Power Delivery Standby mode memorization state.
+  * @rmtoll CR3          UCPD_STDBY           LL_PWR_IsEnabledUCPDStandbyMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
+{
+
+  return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY)) ? 1UL : 0UL);
+
+}
+#endif /* PWR_CR3_UCPD_STDBY */
+
+#if defined(PWR_CR3_UCPD_DBDIS)
+/**
+  * @brief  Enable the USB Type-C and power delivery dead battery pull-down behavior
+  *         on UCPD CC1 and CC2 pins.
+  * @note   After exiting reset, the USB Type-C dead battery behavior is enabled,
+  *         which may have a pull-down effect on CC1 and CC2 pins. It is recommended
+  *         to disable it in all cases, either to stop this pull-down or to hand over
+  *         control to the UCPD (which should therefore be initialized before doing the disable).
+  * @rmtoll CR3          UCPD_DBDIS           LL_PWR_EnableUCPDDeadBattery
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
+}
+
+/**
+  * @brief  Disable the USB Type-C and power delivery dead battery pull-down behavior
+  *         on UCPD CC1 and CC2 pins.
+  * @note   After exiting reset, the USB Type-C dead battery behavior is enabled,
+  *         which may have a pull-down effect on CC1 and CC2 pins. It is recommended
+  *         to disable it in all cases, either to stop this pull-down or to hand over
+  *         control to the UCPD (which should therefore be initialized before doing the disable).
+  * @rmtoll CR3          UCPD_DBDIS           LL_PWR_DisableUCPDDeadBattery
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
+}
+
+/**
+  * @brief  Check the USB Type-C and power delivery dead battery pull-down behavior
+  *         on UCPD CC1 and CC2 pins.
+  * @note   After exiting reset, the USB Type-C dead battery behavior is enabled,
+  *         which may have a pull-down effect on CC1 and CC2 pins. It is recommended
+  *         to disable it in all cases, either to stop this pull-down or to hand over
+  *         control to the UCPD (which should therefore be initialized before doing the disable).
+  * @rmtoll CR3          UCPD_DBDIS           LL_PWR_IsEnabledUCPDDeadBattery
+  * @retval State of feature (1 : enabled; 0 : disabled).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL);
+}
+#endif /* PWR_CR3_UCPD_DBDIS */
+
+#if defined(PWR_CR2_USV)
+/**
+  * @brief  Enable VDDUSB supply
+  * @rmtoll CR2          USV           LL_PWR_EnableVddUSB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddUSB(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_USV);
+}
+
+/**
+  * @brief  Disable VDDUSB supply
+  * @rmtoll CR2          USV           LL_PWR_DisableVddUSB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddUSB(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
+}
+
+/**
+  * @brief  Check if VDDUSB supply is enabled
+  * @rmtoll CR2          USV           LL_PWR_IsEnabledVddUSB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->CR2, PWR_CR2_USV);
+
+  return ((temp == (PWR_CR2_USV))?1U:0U);
+
+}
+#endif
+
+#if defined(PWR_CR2_IOSV)
+/**
+  * @brief  Enable VDDIO2 supply
+  * @rmtoll CR2          IOSV          LL_PWR_EnableVddIO2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddIO2(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_IOSV);
+}
+
+/**
+  * @brief  Disable VDDIO2 supply
+  * @rmtoll CR2          IOSV          LL_PWR_DisableVddIO2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddIO2(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
+}
+
+/**
+  * @brief  Check if VDDIO2 supply is enabled
+  * @rmtoll CR2          IOSV          LL_PWR_IsEnabledVddIO2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->CR2, PWR_CR2_IOSV);
+
+  return ((temp == (PWR_CR2_IOSV))?1U:0U);
+
+}
+#endif
+
+/**
+  * @brief  Enable the Power Voltage Monitoring on a peripheral
+  * @rmtoll CR2          PVME1         LL_PWR_EnablePVM\n
+  *         CR2          PVME2         LL_PWR_EnablePVM\n
+  *         CR2          PVME3         LL_PWR_EnablePVM\n
+  *         CR2          PVME4         LL_PWR_EnablePVM
+  * @param  PeriphVoltage This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVM_VDDA_COMP     (*)
+  *         @arg @ref LL_PWR_PVM_VDDA_FASTDAC  (*)
+  *         @arg @ref LL_PWR_PVM_VDDA_ADC
+  *         @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
+{
+  SET_BIT(PWR->CR2, PeriphVoltage);
+}
+
+/**
+  * @brief  Disable the Power Voltage Monitoring on a peripheral
+  * @rmtoll CR2          PVME1         LL_PWR_DisablePVM\n
+  *         CR2          PVME2         LL_PWR_DisablePVM\n
+  *         CR2          PVME3         LL_PWR_DisablePVM\n
+  *         CR2          PVME4         LL_PWR_DisablePVM
+  * @param  PeriphVoltage This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVM_VDDA_COMP     (*)
+  *         @arg @ref LL_PWR_PVM_VDDA_FASTDAC  (*)
+  *         @arg @ref LL_PWR_PVM_VDDA_ADC
+  *         @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
+{
+  CLEAR_BIT(PWR->CR2, PeriphVoltage);
+}
+
+/**
+  * @brief  Check if Power Voltage Monitoring is enabled on a peripheral
+  * @rmtoll CR2          PVME1         LL_PWR_IsEnabledPVM\n
+  *         CR2          PVME2         LL_PWR_IsEnabledPVM\n
+  *         CR2          PVME3         LL_PWR_IsEnabledPVM\n
+  *         CR2          PVME4         LL_PWR_IsEnabledPVM
+  * @param  PeriphVoltage This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVM_VDDA_COMP     (*)
+  *         @arg @ref LL_PWR_PVM_VDDA_FASTDAC  (*)
+  *         @arg @ref LL_PWR_PVM_VDDA_ADC
+  *         @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
+  *
+  *         (*) value not defined in all devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->CR2, PeriphVoltage);
+
+  return ((temp == (PeriphVoltage))?1U:0U);
+
+}
+
+/**
+  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
+  * @rmtoll CR2          PLS           LL_PWR_SetPVDLevel
+  * @param  PVDLevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+  MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
+}
+
+/**
+  * @brief  Get the voltage threshold detection
+  * @rmtoll CR2          PLS           LL_PWR_GetPVDLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
+}
+
+/**
+  * @brief  Enable Power Voltage Detector
+  * @rmtoll CR2          PVDE          LL_PWR_EnablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_PVDE);
+}
+
+/**
+  * @brief  Disable Power Voltage Detector
+  * @rmtoll CR2          PVDE          LL_PWR_DisablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
+}
+
+/**
+  * @brief  Check if Power Voltage Detector is enabled
+  * @rmtoll CR2          PVDE          LL_PWR_IsEnabledPVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->CR2, PWR_CR2_PVDE);
+
+  return ((temp == (PWR_CR2_PVDE))?1U:0U);
+}
+
+/**
+  * @brief  Enable Internal Wake-up line
+  * @rmtoll CR3          EIWF          LL_PWR_EnableInternWU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableInternWU(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+/**
+  * @brief  Disable Internal Wake-up line
+  * @rmtoll CR3          EIWF          LL_PWR_DisableInternWU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableInternWU(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+/**
+  * @brief  Check if Internal Wake-up line is enabled
+  * @rmtoll CR3          EIWF          LL_PWR_IsEnabledInternWU
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable pull-up and pull-down configuration
+  * @rmtoll CR3          APC           LL_PWR_EnablePUPDCfg
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+/**
+  * @brief  Disable pull-up and pull-down configuration
+  * @rmtoll CR3          APC           LL_PWR_DisablePUPDCfg
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+/**
+  * @brief  Check if pull-up and pull-down configuration  is enabled
+  * @rmtoll CR3          APC           LL_PWR_IsEnabledPUPDCfg
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->CR3, PWR_CR3_APC);
+
+  return ((temp == (PWR_CR3_APC))?1U:0U);
+}
+
+/**
+  * @brief  Enable SRAM2 content retention in Standby mode
+  * @rmtoll CR3          RRS           LL_PWR_EnableSRAM2Retention
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+
+/**
+  * @brief  Disable SRAM2 content retention in Standby mode
+  * @rmtoll CR3          RRS           LL_PWR_DisableSRAM2Retention
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+
+/**
+  * @brief  Check if SRAM2 content retention in Standby mode  is enabled
+  * @rmtoll CR3          RRS           LL_PWR_IsEnabledSRAM2Retention
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->CR3, PWR_CR3_RRS);
+
+  return ((temp == (PWR_CR3_RRS))?1U:0U);
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality
+  * @rmtoll CR3          EWUP1         LL_PWR_EnableWakeUpPin\n
+  *         CR3          EWUP2         LL_PWR_EnableWakeUpPin\n
+  *         CR3          EWUP3         LL_PWR_EnableWakeUpPin\n
+  *         CR3          EWUP4         LL_PWR_EnableWakeUpPin\n
+  *         CR3          EWUP5         LL_PWR_EnableWakeUpPin\n
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->CR3, WakeUpPin);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality
+  * @rmtoll CR3          EWUP1         LL_PWR_DisableWakeUpPin\n
+  *         CR3          EWUP2         LL_PWR_DisableWakeUpPin\n
+  *         CR3          EWUP3         LL_PWR_DisableWakeUpPin\n
+  *         CR3          EWUP4         LL_PWR_DisableWakeUpPin\n
+  *         CR3          EWUP5         LL_PWR_DisableWakeUpPin\n
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->CR3, WakeUpPin);
+}
+
+/**
+  * @brief  Check if the WakeUp PINx functionality is enabled
+  * @rmtoll CR3          EWUP1         LL_PWR_IsEnabledWakeUpPin\n
+  *         CR3          EWUP2         LL_PWR_IsEnabledWakeUpPin\n
+  *         CR3          EWUP3         LL_PWR_IsEnabledWakeUpPin\n
+  *         CR3          EWUP4         LL_PWR_IsEnabledWakeUpPin\n
+  *         CR3          EWUP5         LL_PWR_IsEnabledWakeUpPin\n
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->CR3, WakeUpPin);
+
+  return ((temp == (WakeUpPin))?1U:0U);
+}
+
+/**
+  * @brief  Set the resistor impedance
+  * @rmtoll CR4          VBRS          LL_PWR_SetBattChargResistor
+  * @param  Resistor This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
+{
+  MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
+}
+
+/**
+  * @brief  Get the resistor impedance
+  * @rmtoll CR4          VBRS          LL_PWR_GetBattChargResistor
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
+}
+
+/**
+  * @brief  Enable battery charging
+  * @rmtoll CR4          VBE           LL_PWR_EnableBatteryCharging
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
+{
+  SET_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+/**
+  * @brief  Disable battery charging
+  * @rmtoll CR4          VBE           LL_PWR_DisableBatteryCharging
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
+{
+  CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+/**
+  * @brief  Check if battery charging is enabled
+  * @rmtoll CR4          VBE           LL_PWR_IsEnabledBatteryCharging
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->CR4, PWR_CR4_VBE);
+
+  return ((temp == (PWR_CR4_VBE))?1U:0U);
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity low for the event detection
+  * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->CR4, WakeUpPin);
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity high for the event detection
+  * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityHigh
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->CR4, WakeUpPin);
+}
+
+/**
+  * @brief  Get the Wake-Up pin polarity for the event detection
+  * @rmtoll CR4          WP1           LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR4          WP2           LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR4          WP3           LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR4          WP4           LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR4          WP5           LL_PWR_IsWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->CR4, WakeUpPin);
+
+  return ((temp == (WakeUpPin))?1U:0U);
+}
+
+/**
+  * @brief  Enable GPIO pull-up state in Standby and Shutdown modes
+  * @rmtoll PUCRA        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRB        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRC        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRD        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRE        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRF        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  *         PUCRG        PU0-15        LL_PWR_EnableGPIOPullUp\n
+  * @param  GPIO This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_A
+  *         @arg @ref LL_PWR_GPIO_B
+  *         @arg @ref LL_PWR_GPIO_C
+  *         @arg @ref LL_PWR_GPIO_D
+  *         @arg @ref LL_PWR_GPIO_E
+  *         @arg @ref LL_PWR_GPIO_F
+  *         @arg @ref LL_PWR_GPIO_G
+  *
+  *         (*) value not defined in all devices
+  * @param  GPIONumber This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_BIT_0
+  *         @arg @ref LL_PWR_GPIO_BIT_1
+  *         @arg @ref LL_PWR_GPIO_BIT_2
+  *         @arg @ref LL_PWR_GPIO_BIT_3
+  *         @arg @ref LL_PWR_GPIO_BIT_4
+  *         @arg @ref LL_PWR_GPIO_BIT_5
+  *         @arg @ref LL_PWR_GPIO_BIT_6
+  *         @arg @ref LL_PWR_GPIO_BIT_7
+  *         @arg @ref LL_PWR_GPIO_BIT_8
+  *         @arg @ref LL_PWR_GPIO_BIT_9
+  *         @arg @ref LL_PWR_GPIO_BIT_10
+  *         @arg @ref LL_PWR_GPIO_BIT_11
+  *         @arg @ref LL_PWR_GPIO_BIT_12
+  *         @arg @ref LL_PWR_GPIO_BIT_13
+  *         @arg @ref LL_PWR_GPIO_BIT_14
+  *         @arg @ref LL_PWR_GPIO_BIT_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+  SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
+}
+
+/**
+  * @brief  Disable GPIO pull-up state in Standby and Shutdown modes
+  * @rmtoll PUCRA        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRB        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRC        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRD        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRE        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRF        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  *         PUCRG        PU0-15        LL_PWR_DisableGPIOPullUp\n
+  * @param  GPIO This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_A
+  *         @arg @ref LL_PWR_GPIO_B
+  *         @arg @ref LL_PWR_GPIO_C
+  *         @arg @ref LL_PWR_GPIO_D
+  *         @arg @ref LL_PWR_GPIO_E
+  *         @arg @ref LL_PWR_GPIO_F
+  *         @arg @ref LL_PWR_GPIO_G
+  *
+  *         (*) value not defined in all devices
+  * @param  GPIONumber This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_BIT_0
+  *         @arg @ref LL_PWR_GPIO_BIT_1
+  *         @arg @ref LL_PWR_GPIO_BIT_2
+  *         @arg @ref LL_PWR_GPIO_BIT_3
+  *         @arg @ref LL_PWR_GPIO_BIT_4
+  *         @arg @ref LL_PWR_GPIO_BIT_5
+  *         @arg @ref LL_PWR_GPIO_BIT_6
+  *         @arg @ref LL_PWR_GPIO_BIT_7
+  *         @arg @ref LL_PWR_GPIO_BIT_8
+  *         @arg @ref LL_PWR_GPIO_BIT_9
+  *         @arg @ref LL_PWR_GPIO_BIT_10
+  *         @arg @ref LL_PWR_GPIO_BIT_11
+  *         @arg @ref LL_PWR_GPIO_BIT_12
+  *         @arg @ref LL_PWR_GPIO_BIT_13
+  *         @arg @ref LL_PWR_GPIO_BIT_14
+  *         @arg @ref LL_PWR_GPIO_BIT_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+  CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
+}
+
+/**
+  * @brief  Check if GPIO pull-up state is enabled
+  * @rmtoll PUCRA        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRB        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRC        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRD        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRE        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRF        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  *         PUCRG        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
+  * @param  GPIO This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_A
+  *         @arg @ref LL_PWR_GPIO_B
+  *         @arg @ref LL_PWR_GPIO_C
+  *         @arg @ref LL_PWR_GPIO_D
+  *         @arg @ref LL_PWR_GPIO_E
+  *         @arg @ref LL_PWR_GPIO_F
+  *         @arg @ref LL_PWR_GPIO_G
+  *
+  *         (*) value not defined in all devices
+  * @param  GPIONumber This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_BIT_0
+  *         @arg @ref LL_PWR_GPIO_BIT_1
+  *         @arg @ref LL_PWR_GPIO_BIT_2
+  *         @arg @ref LL_PWR_GPIO_BIT_3
+  *         @arg @ref LL_PWR_GPIO_BIT_4
+  *         @arg @ref LL_PWR_GPIO_BIT_5
+  *         @arg @ref LL_PWR_GPIO_BIT_6
+  *         @arg @ref LL_PWR_GPIO_BIT_7
+  *         @arg @ref LL_PWR_GPIO_BIT_8
+  *         @arg @ref LL_PWR_GPIO_BIT_9
+  *         @arg @ref LL_PWR_GPIO_BIT_10
+  *         @arg @ref LL_PWR_GPIO_BIT_11
+  *         @arg @ref LL_PWR_GPIO_BIT_12
+  *         @arg @ref LL_PWR_GPIO_BIT_13
+  *         @arg @ref LL_PWR_GPIO_BIT_14
+  *         @arg @ref LL_PWR_GPIO_BIT_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+  return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable GPIO pull-down state in Standby and Shutdown modes
+  * @rmtoll PDCRA        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRB        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRC        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRD        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRE        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRF        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  *         PDCRG        PD0-15        LL_PWR_EnableGPIOPullDown\n
+  * @param  GPIO This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_A
+  *         @arg @ref LL_PWR_GPIO_B
+  *         @arg @ref LL_PWR_GPIO_C
+  *         @arg @ref LL_PWR_GPIO_D
+  *         @arg @ref LL_PWR_GPIO_E
+  *         @arg @ref LL_PWR_GPIO_F
+  *         @arg @ref LL_PWR_GPIO_G
+  *
+  *         (*) value not defined in all devices
+  * @param  GPIONumber This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_BIT_0
+  *         @arg @ref LL_PWR_GPIO_BIT_1
+  *         @arg @ref LL_PWR_GPIO_BIT_2
+  *         @arg @ref LL_PWR_GPIO_BIT_3
+  *         @arg @ref LL_PWR_GPIO_BIT_4
+  *         @arg @ref LL_PWR_GPIO_BIT_5
+  *         @arg @ref LL_PWR_GPIO_BIT_6
+  *         @arg @ref LL_PWR_GPIO_BIT_7
+  *         @arg @ref LL_PWR_GPIO_BIT_8
+  *         @arg @ref LL_PWR_GPIO_BIT_9
+  *         @arg @ref LL_PWR_GPIO_BIT_10
+  *         @arg @ref LL_PWR_GPIO_BIT_11
+  *         @arg @ref LL_PWR_GPIO_BIT_12
+  *         @arg @ref LL_PWR_GPIO_BIT_13
+  *         @arg @ref LL_PWR_GPIO_BIT_14
+  *         @arg @ref LL_PWR_GPIO_BIT_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+  SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
+}
+
+/**
+  * @brief  Disable GPIO pull-down state in Standby and Shutdown modes
+  * @rmtoll PDCRA        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRB        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRC        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRD        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRE        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRF        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  *         PDCRG        PD0-15        LL_PWR_DisableGPIOPullDown\n
+  * @param  GPIO This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_A
+  *         @arg @ref LL_PWR_GPIO_B
+  *         @arg @ref LL_PWR_GPIO_C
+  *         @arg @ref LL_PWR_GPIO_D
+  *         @arg @ref LL_PWR_GPIO_E
+  *         @arg @ref LL_PWR_GPIO_F
+  *         @arg @ref LL_PWR_GPIO_G
+  *
+  *         (*) value not defined in all devices
+  * @param  GPIONumber This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_BIT_0
+  *         @arg @ref LL_PWR_GPIO_BIT_1
+  *         @arg @ref LL_PWR_GPIO_BIT_2
+  *         @arg @ref LL_PWR_GPIO_BIT_3
+  *         @arg @ref LL_PWR_GPIO_BIT_4
+  *         @arg @ref LL_PWR_GPIO_BIT_5
+  *         @arg @ref LL_PWR_GPIO_BIT_6
+  *         @arg @ref LL_PWR_GPIO_BIT_7
+  *         @arg @ref LL_PWR_GPIO_BIT_8
+  *         @arg @ref LL_PWR_GPIO_BIT_9
+  *         @arg @ref LL_PWR_GPIO_BIT_10
+  *         @arg @ref LL_PWR_GPIO_BIT_11
+  *         @arg @ref LL_PWR_GPIO_BIT_12
+  *         @arg @ref LL_PWR_GPIO_BIT_13
+  *         @arg @ref LL_PWR_GPIO_BIT_14
+  *         @arg @ref LL_PWR_GPIO_BIT_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+  CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
+}
+
+/**
+  * @brief  Check if GPIO pull-down state is enabled
+  * @rmtoll PDCRA        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRB        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRC        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRD        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRE        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRF        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  *         PDCRG        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
+  * @param  GPIO This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_A
+  *         @arg @ref LL_PWR_GPIO_B
+  *         @arg @ref LL_PWR_GPIO_C
+  *         @arg @ref LL_PWR_GPIO_D
+  *         @arg @ref LL_PWR_GPIO_E
+  *         @arg @ref LL_PWR_GPIO_F
+  *         @arg @ref LL_PWR_GPIO_G
+  *
+  *         (*) value not defined in all devices
+  * @param  GPIONumber This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_GPIO_BIT_0
+  *         @arg @ref LL_PWR_GPIO_BIT_1
+  *         @arg @ref LL_PWR_GPIO_BIT_2
+  *         @arg @ref LL_PWR_GPIO_BIT_3
+  *         @arg @ref LL_PWR_GPIO_BIT_4
+  *         @arg @ref LL_PWR_GPIO_BIT_5
+  *         @arg @ref LL_PWR_GPIO_BIT_6
+  *         @arg @ref LL_PWR_GPIO_BIT_7
+  *         @arg @ref LL_PWR_GPIO_BIT_8
+  *         @arg @ref LL_PWR_GPIO_BIT_9
+  *         @arg @ref LL_PWR_GPIO_BIT_10
+  *         @arg @ref LL_PWR_GPIO_BIT_11
+  *         @arg @ref LL_PWR_GPIO_BIT_12
+  *         @arg @ref LL_PWR_GPIO_BIT_13
+  *         @arg @ref LL_PWR_GPIO_BIT_14
+  *         @arg @ref LL_PWR_GPIO_BIT_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+  return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Internal Wake-up line Flag
+  * @rmtoll SR1          WUFI          LL_PWR_IsActiveFlag_InternWU
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR1, PWR_SR1_WUFI);
+
+  return ((temp == (PWR_SR1_WUFI))?1U:0U);
+
+}
+
+/**
+  * @brief  Get Stand-By Flag
+  * @rmtoll SR1          SBF           LL_PWR_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR1, PWR_SR1_SBF);
+
+  return ((temp == (PWR_SR1_SBF))?1U:0U);
+
+}
+
+/**
+  * @brief  Get Wake-up Flag 5
+  * @rmtoll SR1          WUF5          LL_PWR_IsActiveFlag_WU5
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR1, PWR_SR1_WUF5);
+
+  return ((temp == (PWR_SR1_WUF5))?1U:0U);
+}
+
+/**
+  * @brief  Get Wake-up Flag 4
+  * @rmtoll SR1          WUF4          LL_PWR_IsActiveFlag_WU4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR1, PWR_SR1_WUF4);
+
+  return ((temp == (PWR_SR1_WUF4))?1U:0U);
+}
+
+/**
+  * @brief  Get Wake-up Flag 3
+  * @rmtoll SR1          WUF3          LL_PWR_IsActiveFlag_WU3
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR1, PWR_SR1_WUF3);
+
+  return ((temp == (PWR_SR1_WUF3))?1U:0U);
+}
+
+/**
+  * @brief  Get Wake-up Flag 2
+  * @rmtoll SR1          WUF2          LL_PWR_IsActiveFlag_WU2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR1, PWR_SR1_WUF2);
+
+  return ((temp == (PWR_SR1_WUF2))?1U:0U);
+}
+
+/**
+  * @brief  Get Wake-up Flag 1
+  * @rmtoll SR1          WUF1          LL_PWR_IsActiveFlag_WU1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR1, PWR_SR1_WUF1);
+
+  return ((temp == (PWR_SR1_WUF1))?1U:0U);
+}
+
+/**
+  * @brief  Clear Stand-By Flag
+  * @rmtoll SCR          CSBF          LL_PWR_ClearFlag_SB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
+}
+
+/**
+  * @brief  Clear Wake-up Flags
+  * @rmtoll SCR          CWUF          LL_PWR_ClearFlag_WU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 5
+  * @rmtoll SCR          CWUF5         LL_PWR_ClearFlag_WU5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 4
+  * @rmtoll SCR          CWUF4         LL_PWR_ClearFlag_WU4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 3
+  * @rmtoll SCR          CWUF3         LL_PWR_ClearFlag_WU3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 2
+  * @rmtoll SCR          CWUF2         LL_PWR_ClearFlag_WU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 1
+  * @rmtoll SCR          CWUF1         LL_PWR_ClearFlag_WU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
+{
+  WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
+}
+
+/**
+  * @brief  Indicate whether VDDA voltage is below or above PVM4 threshold
+  * @rmtoll SR2          PVMO4         LL_PWR_IsActiveFlag_PVMO4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO4);
+
+  return ((temp == (PWR_SR2_PVMO4))?1U:0U);
+
+}
+
+/**
+  * @brief  Indicate whether VDDA voltage is below or above PVM3 threshold
+  * @rmtoll SR2          PVMO3         LL_PWR_IsActiveFlag_PVMO3
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO3);
+
+  return ((temp == (PWR_SR2_PVMO3))?1U:0U);
+
+}
+
+#if defined(PWR_SR2_PVMO2)
+/**
+  * @brief  Indicate whether VDDIO2 voltage is below or above PVM2 threshold
+  * @rmtoll SR2          PVMO2         LL_PWR_IsActiveFlag_PVMO2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO2);
+
+  return ((temp == (PWR_SR2_PVMO2))?1U:0U);
+
+}
+#endif /* PWR_SR2_PVMO2 */
+
+#if defined(PWR_SR2_PVMO1)
+/**
+  * @brief  Indicate whether VDDUSB voltage is below or above PVM1 threshold
+  * @rmtoll SR2          PVMO1         LL_PWR_IsActiveFlag_PVMO1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO1);
+
+  return ((temp == (PWR_SR2_PVMO1))?1U:0U);
+
+}
+#endif /* PWR_SR2_PVMO1 */
+
+/**
+  * @brief  Indicate whether VDD voltage is below or above the selected PVD threshold
+  * @rmtoll SR2          PVDO          LL_PWR_IsActiveFlag_PVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+ uint32_t temp;
+ temp = READ_BIT(PWR->SR2, PWR_SR2_PVDO);
+
+ return ((temp == (PWR_SR2_PVDO))?1U:0U);
+
+}
+
+/**
+  * @brief  Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
+  * @rmtoll SR2          VOSF          LL_PWR_IsActiveFlag_VOS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR2, PWR_SR2_VOSF);
+
+  return ((temp == (PWR_SR2_VOSF))?1U:0U);
+
+}
+
+/**
+  * @brief  Indicate whether the regulator is ready in main mode or is in low-power mode
+  * @note: Take care, return value "0" means the regulator is ready.  Return value "1" means the output voltage range is still changing.
+  * @rmtoll SR2          REGLPF        LL_PWR_IsActiveFlag_REGLPF
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPF);
+
+  return ((temp == (PWR_SR2_REGLPF))?1U:0U);
+
+}
+
+/**
+  * @brief  Indicate whether or not the low-power regulator is ready
+  * @rmtoll SR2          REGLPS        LL_PWR_IsActiveFlag_REGLPS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
+{
+  uint32_t temp;
+  temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPS);
+
+  return ((temp == (PWR_SR2_REGLPS))?1U:0U);
+
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
+  * @{
+  */
+/* Old functions name kept for legacy purpose, to be replaced by the          */
+/* current functions name.                                                    */
+#define LL_PWR_IsActiveFlag_VOSF  LL_PWR_IsActiveFlag_VOS
+#define LL_PWR_EnableUSBDeadBattery            LL_PWR_EnableUCPDDeadBattery
+#define LL_PWR_DisableUSBDeadBattery           LL_PWR_DisableUCPDDeadBattery
+#define LL_PWR_IsEnabledUSBDeadBattery         LL_PWR_IsEnabledUCPDDeadBattery
+#define LL_PWR_EnableDeadBatteryPD             LL_PWR_EnableUCPDDeadBattery
+#define LL_PWR_DisableDeadBatteryPD            LL_PWR_DisableUCPDDeadBattery
+#define LL_PWR_EnableUSBStandByModePD          LL_PWR_EnableUCPDStandbyMode
+#define LL_PWR_EnableStandByModePD             LL_PWR_EnableUCPDStandbyMode
+#define LL_PWR_DisableUSBStandByModePD         LL_PWR_DisableUCPDStandbyMode
+#define LL_PWR_DisableStandByModePD            LL_PWR_DisableUCPDStandbyMode
+#define LL_PWR_IsEnabledUSBStandByModePD       LL_PWR_IsEnabledUCPDStandbyMode
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(PWR) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_PWR_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h
new file mode 100644
index 0000000..4c18025
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h
@@ -0,0 +1,2998 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_RCC_H
+#define STM32G4xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup RCC_LL RCC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Constants RCC Private Constants
+  * @{
+  */
+/* Defines used to perform offsets*/
+/* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
+#define RCC_OFFSET_CCIPR        0U
+#define RCC_OFFSET_CCIPR2       0x14U
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+  * @{
+  */
+
+/**
+  * @brief  RCC Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
+  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
+  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
+  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+  * @brief    Defines used to adapt values of different oscillators
+  * @note     These values could be modified in the user environment according to
+  *           HW set-up.
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    8000000U   /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */
+#endif /* HSI48_VALUE */
+
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    48000U     /*!< Value of the I2S_CKIN, I2S and SAI1 external clock source in Hz */
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_RCC_WriteReg function
+  * @{
+  */
+#define LL_RCC_CICR_LSIRDYC                RCC_CICR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CICR_LSERDYC                RCC_CICR_LSERDYC     /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CICR_HSIRDYC                RCC_CICR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CICR_HSERDYC                RCC_CICR_HSERDYC     /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CICR_PLLRDYC                RCC_CICR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
+#define LL_RCC_CICR_HSI48RDYC              RCC_CICR_HSI48RDYC   /*!< HSI48 Ready Interrupt Clear */
+#define LL_RCC_CICR_LSECSSC                RCC_CICR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */
+#define LL_RCC_CICR_CSSC                   RCC_CICR_CSSC        /*!< Clock Security System Interrupt Clear */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_RCC_ReadReg function
+  * @{
+  */
+#define LL_RCC_CIFR_LSIRDYF                RCC_CIFR_LSIRDYF     /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIFR_LSERDYF                RCC_CIFR_LSERDYF     /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIFR_HSIRDYF                RCC_CIFR_HSIRDYF     /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIFR_HSERDYF                RCC_CIFR_HSERDYF     /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CIFR_PLLRDYF                RCC_CIFR_PLLRDYF     /*!< PLL Ready Interrupt flag */
+#define LL_RCC_CIFR_HSI48RDYF              RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */
+#define LL_RCC_CIFR_LSECSSF                RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */
+#define LL_RCC_CIFR_CSSF                   RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */
+#define LL_RCC_CSR_OBLRSTF                 RCC_CSR_OBLRSTF    /*!< OBL reset flag */
+#define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */
+#define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
+#define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
+  * @{
+  */
+#define LL_RCC_CIER_LSIRDYIE               RCC_CIER_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIER_LSERDYIE               RCC_CIER_LSERDYIE      /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIER_HSIRDYIE               RCC_CIER_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIER_HSERDYIE               RCC_CIER_HSERDYIE      /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIER_PLLRDYIE               RCC_CIER_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
+#define LL_RCC_CIER_HSI48RDYIE             RCC_CIER_HSI48RDYIE    /*!< HSI48 Ready Interrupt Enable */
+#define LL_RCC_CIER_LSECSSIE               RCC_CIER_LSECSSIE      /*!< LSE CSS Interrupt Enable */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
+  * @{
+  */
+#define LL_RCC_LSEDRIVE_LOW                0x00000000U             /*!< Xtal mode lower driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_0       /*!< Xtal mode medium low driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_1       /*!< Xtal mode medium high driving capability */
+#define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV         /*!< Xtal mode higher driving capability */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE  LSCO Selection
+  * @{
+  */
+#define LL_RCC_LSCO_CLKSOURCE_LSI          0x00000000U                 /*!< LSI selection for low speed clock  */
+#define LL_RCC_LSCO_CLKSOURCE_LSE          RCC_BDCR_LSCOSEL            /*!< LSE selection for low speed clock  */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
+  * @{
+  */
+#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
+  * @{
+  */
+#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
+  * @{
+  */
+#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
+  * @{
+  */
+#define LL_RCC_MCO1SOURCE_NOCLOCK          0x00000000U                            /*!< MCO output disabled, no clock on MCO */
+#define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSI              (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_PLLCLK           (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< Main PLL selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSI              (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSE              (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSI48            RCC_CFGR_MCOSEL_3                      /*!< HSI48 selection as MCO1 source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
+  * @{
+  */
+#define LL_RCC_MCO1_DIV_1                  RCC_CFGR_MCOPRE_DIV1       /*!< MCO not divided */
+#define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_DIV2       /*!< MCO divided by 2 */
+#define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_DIV4       /*!< MCO divided by 4 */
+#define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCOPRE_DIV8       /*!< MCO divided by 8 */
+#define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_DIV16      /*!< MCO divided by 16 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+  * @{
+  */
+#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
+#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
+  * @{
+  */
+#define LL_RCC_USART1_CLKSOURCE_PCLK2      (RCC_CCIPR_USART1SEL << 16U)                           /*!< PCLK2 clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_HSI        ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_LSE        ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)   /*!< LSE clock used as USART1 clock source */
+#define LL_RCC_USART2_CLKSOURCE_PCLK1      (RCC_CCIPR_USART2SEL << 16U)                           /*!< PCLK1 clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_HSI        ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_LSE        ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)   /*!< LSE clock used as USART2 clock source */
+#define LL_RCC_USART3_CLKSOURCE_PCLK1      (RCC_CCIPR_USART3SEL << 16U)                           /*!< PCLK1 clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_HSI        ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_LSE        ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)   /*!< LSE clock used as USART3 clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_UARTx_CLKSOURCE  Peripheral UART clock source selection
+  * @{
+  */
+#if defined(RCC_CCIPR_UART4SEL)
+#define LL_RCC_UART4_CLKSOURCE_PCLK1       (RCC_CCIPR_UART4SEL << 16U)                           /*!< PCLK1 clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_SYSCLK      ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0)  /*!< SYSCLK clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_HSI         ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1)  /*!< HSI clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_LSE         ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL)    /*!< LSE clock used as UART4 clock source */
+#endif /* RCC_CCIPR_UART4SEL */
+#if defined(RCC_CCIPR_UART5SEL)
+#define LL_RCC_UART5_CLKSOURCE_PCLK1       (RCC_CCIPR_UART5SEL << 16U)                           /*!< PCLK1 clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_SYSCLK      ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0)  /*!< SYSCLK clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_HSI         ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1)  /*!< HSI clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_LSE         ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL)    /*!< LSE clock used as UART5 clock source */
+#endif /* RCC_CCIPR_UART5SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE  Peripheral LPUART clock source selection
+  * @{
+  */
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK1     0x00000000U                     /*!< PCLK1 clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0          /*!< SYSCLK clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1          /*!< HSI clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_LSE       RCC_CCIPR_LPUART1SEL            /*!< LSE clock used as LPUART1 clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
+  * @{
+  */
+#define LL_RCC_I2C1_CLKSOURCE_PCLK1        ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U))                                                      /*!< PCLK1 clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_SYSCLK       ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos))     /*!< SYSCLK clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_HSI          ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos))     /*!< HSI clock used as I2C1 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_PCLK1        ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U))                                                      /*!< PCLK1 clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_SYSCLK       ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos))     /*!< SYSCLK clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_HSI          ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos))     /*!< HSI clock used as I2C2 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_PCLK1        ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U))                                                      /*!< PCLK1 clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_SYSCLK       ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos))     /*!< SYSCLK clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_HSI          ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos))     /*!< HSI clock used as I2C3 clock source */
+#if defined(RCC_CCIPR2_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE_PCLK1        ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U))                                                    /*!< PCLK1 clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_SYSCLK       ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_HSI          ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
+#endif /* RCC_CCIPR2_I2C4SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1      0x00000000U                                            /*!< PCLK1 clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI        RCC_CCIPR_LPTIM1SEL_0                                  /*!< LSI clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_HSI        RCC_CCIPR_LPTIM1SEL_1                                  /*!< HSI clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE        RCC_CCIPR_LPTIM1SEL                                    /*!< LSE clock used as LPTIM1 clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE  Peripheral SAI clock source selection
+  * @{
+  */
+#define LL_RCC_SAI1_CLKSOURCE_SYSCLK       0x00000000U                                           /*!< System clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLL          RCC_CCIPR_SAI1SEL_0                                   /*!< PLL clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PIN          RCC_CCIPR_SAI1SEL_1                                   /*!< EXT clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_HSI          (RCC_CCIPR_SAI1SEL_0 | RCC_CCIPR_SAI1SEL_1)           /*!< HSI clock used as SAI1 clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2S_CLKSOURCE  Peripheral I2S clock source selection
+  * @{
+  */
+#define LL_RCC_I2S_CLKSOURCE_SYSCLK       0x00000000U                                          /*!< System clock used as I2S clock source */
+#define LL_RCC_I2S_CLKSOURCE_PLL          RCC_CCIPR_I2S23SEL_0                                 /*!< PLL clock used as I2S clock source */
+#define LL_RCC_I2S_CLKSOURCE_PIN          RCC_CCIPR_I2S23SEL_1                                 /*!< EXT clock used as I2S clock source */
+#define LL_RCC_I2S_CLKSOURCE_HSI          (RCC_CCIPR_I2S23SEL_0 | RCC_CCIPR_I2S23SEL_1)        /*!< HSI clock used as I2S clock source */
+/**
+  * @}
+  */
+
+#if defined(FDCAN1)
+/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN clock source selection
+  * @{
+  */
+#define LL_RCC_FDCAN_CLKSOURCE_HSE        0x00000000U             /*!< HSE clock used as FDCAN clock source */
+#define LL_RCC_FDCAN_CLKSOURCE_PLL        RCC_CCIPR_FDCANSEL_0    /*!< PLL clock used as FDCAN clock source */
+#define LL_RCC_FDCAN_CLKSOURCE_PCLK1      RCC_CCIPR_FDCANSEL_1    /*!< PCLK1 clock used as FDCAN clock source */
+/**
+  * @}
+  */
+#endif /* FDCAN1 */
+
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
+  * @{
+  */
+#define LL_RCC_RNG_CLKSOURCE_HSI48        0x00000000U             /*!< HSI48 clock used as RNG clock source */
+#define LL_RCC_RNG_CLKSOURCE_PLL          RCC_CCIPR_CLK48SEL_1    /*!< PLL clock used as RNG clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
+  * @{
+  */
+#define LL_RCC_USB_CLKSOURCE_HSI48        0x00000000U             /*!< HSI48 clock used as USB clock source */
+#define LL_RCC_USB_CLKSOURCE_PLL          RCC_CCIPR_CLK48SEL_1    /*!< PLL clock used as USB clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
+  * @{
+  */
+#define LL_RCC_ADC12_CLKSOURCE_NONE        ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U))                                                       /*!< No clock used as ADC12 clock source */
+#define LL_RCC_ADC12_CLKSOURCE_PLL         ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_0 >> RCC_CCIPR_ADC12SEL_Pos))    /*!< PLL clock used as ADC12 clock source */
+#define LL_RCC_ADC12_CLKSOURCE_SYSCLK      ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_1 >> RCC_CCIPR_ADC12SEL_Pos))    /*!< SYSCLK clock used as ADC12 clock source */
+#if defined(RCC_CCIPR_ADC345SEL)
+#define LL_RCC_ADC345_CLKSOURCE_NONE       ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U))                                                      /*!< No clock used as ADC345 clock source */
+#define LL_RCC_ADC345_CLKSOURCE_PLL        ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_0 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< PLL clock used as ADC345 clock source */
+#define LL_RCC_ADC345_CLKSOURCE_SYSCLK     ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_1 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< SYSCLK clock used as ADC345 clock source */
+#endif /* RCC_CCIPR_ADC345SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_QUADSPI  Peripheral QUADSPI get clock source
+  * @{
+  */
+#define LL_RCC_QUADSPI_CLKSOURCE_SYSCLK    0x00000000U              /*!< SYSCLK used as QuadSPI clock source */
+#define LL_RCC_QUADSPI_CLKSOURCE_HSI       RCC_CCIPR2_QSPISEL_0     /*!< HSI used as QuadSPI clock source */
+#define LL_RCC_QUADSPI_CLKSOURCE_PLL       RCC_CCIPR2_QSPISEL_1     /*!< PLL used as QuadSPI clock source */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
+  * @{
+  */
+#define LL_RCC_USART1_CLKSOURCE            RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
+#define LL_RCC_USART2_CLKSOURCE            RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
+#define LL_RCC_USART3_CLKSOURCE            RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
+  * @{
+  */
+#if defined(RCC_CCIPR_UART4SEL)
+#define LL_RCC_UART4_CLKSOURCE             RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
+#endif /* RCC_CCIPR_UART4SEL */
+#if defined(RCC_CCIPR_UART5SEL)
+#define LL_RCC_UART5_CLKSOURCE             RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
+#endif /* RCC_CCIPR_UART5SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
+  * @{
+  */
+#define LL_RCC_LPUART1_CLKSOURCE           RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
+  * @{
+  */
+#define LL_RCC_I2C1_CLKSOURCE              ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
+#define LL_RCC_I2C2_CLKSOURCE              ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
+#define LL_RCC_I2C3_CLKSOURCE              ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
+#if defined(RCC_CCIPR2_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE              ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
+#endif /* RCC_CCIPR2_I2C4SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE            RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAI1  Peripheral SAI get clock source
+  * @{
+  */
+#define LL_RCC_SAI1_CLKSOURCE              RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2S  Peripheral I2S get clock source
+  * @{
+  */
+#define LL_RCC_I2S_CLKSOURCE              RCC_CCIPR_I2S23SEL /*!< I2S Clock source selection */
+/**
+  * @}
+  */
+
+#if defined(FDCAN1)
+/** @defgroup RCC_LL_EC_FDCAN  Peripheral FDCAN get clock source
+  * @{
+  */
+#define LL_RCC_FDCAN_CLKSOURCE             RCC_CCIPR_FDCANSEL /*!< FDCAN Clock source selection */
+#endif /* FDCAN1 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
+  * @{
+  */
+#define LL_RCC_RNG_CLKSOURCE               RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
+  * @{
+  */
+#define LL_RCC_USB_CLKSOURCE               RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ADC  Peripheral ADC get clock source
+  * @{
+  */
+#define LL_RCC_ADC12_CLKSOURCE             ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL >> RCC_CCIPR_ADC12SEL_Pos))    /*!< ADC12 Clock source selection */
+#if defined(RCC_CCIPR_ADC345SEL_Pos)
+#define LL_RCC_ADC345_CLKSOURCE            ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL >> RCC_CCIPR_ADC345SEL_Pos)) /*!< ADC345 Clock source selection */
+#endif /* RCC_CCIPR_ADC345SEL_Pos */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_QUADSPI  Peripheral QUADSPI get clock source
+  * @{
+  */
+#define LL_RCC_QUADSPI_CLKSOURCE           RCC_CCIPR2_QSPISEL    /*!< QuadSPI Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
+  * @{
+  */
+#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_LL_EC_PLLSOURCE  PLL entry clock source
+  * @{
+  */
+#define LL_RCC_PLLSOURCE_NONE              0x00000000U             /*!< No clock */
+#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLM_DIV  PLL division factor
+  * @{
+  */
+#define LL_RCC_PLLM_DIV_1                  0x00000000U                                                                           /*!< PLL division factor by 1 */
+#define LL_RCC_PLLM_DIV_2                  RCC_PLLCFGR_PLLM_0                                                                    /*!< PLL division factor by 2 */
+#define LL_RCC_PLLM_DIV_3                  RCC_PLLCFGR_PLLM_1                                                                    /*!< PLL division factor by 3 */
+#define LL_RCC_PLLM_DIV_4                  (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)                                             /*!< PLL division factor by 4 */
+#define LL_RCC_PLLM_DIV_5                  RCC_PLLCFGR_PLLM_2                                                                    /*!< PLL division factor by 5 */
+#define LL_RCC_PLLM_DIV_6                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)                                             /*!< PLL division factor by 6 */
+#define LL_RCC_PLLM_DIV_7                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)                                             /*!< PLL division factor by 7 */
+#define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)                        /*!< PLL division factor by 8 */
+#define LL_RCC_PLLM_DIV_9                  RCC_PLLCFGR_PLLM_3                                                                    /*!< PLL division factor by 9 */
+#define LL_RCC_PLLM_DIV_10                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)                                             /*!< PLL division factor by 10 */
+#define LL_RCC_PLLM_DIV_11                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)                                             /*!< PLL division factor by 11 */
+#define LL_RCC_PLLM_DIV_12                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)                        /*!< PLL division factor by 12 */
+#define LL_RCC_PLLM_DIV_13                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)                                             /*!< PLL division factor by 13 */
+#define LL_RCC_PLLM_DIV_14                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)                        /*!< PLL division factor by 14 */
+#define LL_RCC_PLLM_DIV_15                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)                        /*!< PLL division factor by 15 */
+#define LL_RCC_PLLM_DIV_16                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)   /*!< PLL division factor by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
+  * @{
+  */
+#define LL_RCC_PLLR_DIV_2                  0x00000000U            /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
+#define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_0)   /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
+#define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_1)   /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
+#define LL_RCC_PLLR_DIV_8                  (RCC_PLLCFGR_PLLR)     /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
+  * @{
+  */
+#define LL_RCC_PLLP_DIV_2                  (RCC_PLLCFGR_PLLPDIV_1)                                              /*!< Main PLL division factor for PLLP output by 2 */
+#define LL_RCC_PLLP_DIV_3                  (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)                        /*!< Main PLL division factor for PLLP output by 3 */
+#define LL_RCC_PLLP_DIV_4                  (RCC_PLLCFGR_PLLPDIV_2)                                              /*!< Main PLL division factor for PLLP output by 4 */
+#define LL_RCC_PLLP_DIV_5                  (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)                        /*!< Main PLL division factor for PLLP output by 5 */
+#define LL_RCC_PLLP_DIV_6                  (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)                        /*!< Main PLL division factor for PLLP output by 6 */
+#define LL_RCC_PLLP_DIV_7                  (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 7 */
+#define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLPDIV_3)                                              /*!< Main PLL division factor for PLLP output by 8 */
+#define LL_RCC_PLLP_DIV_9                  (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)                        /*!< Main PLL division factor for PLLP output by 9 */
+#define LL_RCC_PLLP_DIV_10                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)                        /*!< Main PLL division factor for PLLP output by 10 */
+#define LL_RCC_PLLP_DIV_11                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 11 */
+#define LL_RCC_PLLP_DIV_12                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)                        /*!< Main PLL division factor for PLLP output by 12 */
+#define LL_RCC_PLLP_DIV_13                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 13 */
+#define LL_RCC_PLLP_DIV_14                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)  /*!< Main PLL division factor for PLLP output by 14 */
+#define LL_RCC_PLLP_DIV_15                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */
+#define LL_RCC_PLLP_DIV_16                 (RCC_PLLCFGR_PLLPDIV_4)                                              /*!< Main PLL division factor for PLLP output by 16 */
+#define LL_RCC_PLLP_DIV_17                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0)                        /*!< Main PLL division factor for PLLP output by 17 */
+#define LL_RCC_PLLP_DIV_18                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1)                        /*!< Main PLL division factor for PLLP output by 18 */
+#define LL_RCC_PLLP_DIV_19                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 19 */
+#define LL_RCC_PLLP_DIV_20                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2)                        /*!< Main PLL division factor for PLLP output by 20 */
+#define LL_RCC_PLLP_DIV_21                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 21 */
+#define LL_RCC_PLLP_DIV_22                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)  /*!< Main PLL division factor for PLLP output by 22 */
+#define LL_RCC_PLLP_DIV_23                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */
+#define LL_RCC_PLLP_DIV_24                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3)                        /*!< Main PLL division factor for PLLP output by 24 */
+#define LL_RCC_PLLP_DIV_25                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 25 */
+#define LL_RCC_PLLP_DIV_26                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)  /*!< Main PLL division factor for PLLP output by 26 */
+#define LL_RCC_PLLP_DIV_27                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */
+#define LL_RCC_PLLP_DIV_28                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)  /*!< Main PLL division factor for PLLP output by 28 */
+#define LL_RCC_PLLP_DIV_29                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */
+#define LL_RCC_PLLP_DIV_30                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */
+#define LL_RCC_PLLP_DIV_31                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
+  * @{
+  */
+#define LL_RCC_PLLQ_DIV_2                  0x00000000U             /*!< Main PLL division factor for PLLQ output by 2 */
+#define LL_RCC_PLLQ_DIV_4                  (RCC_PLLCFGR_PLLQ_0)    /*!< Main PLL division factor for PLLQ output by 4 */
+#define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_1)    /*!< Main PLL division factor for PLLQ output by 6 */
+#define LL_RCC_PLLQ_DIV_8                  (RCC_PLLCFGR_PLLQ)      /*!< Main PLL division factor for PLLQ output by 8 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RCC register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, __VALUE__)
+
+/**
+  * @brief  Read a value in RCC register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency on system domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 127
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_8
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
+                   ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
+
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on ADC domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+
+  * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 127
+  * @param  __PLLP__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_3
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_5
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_7
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  *         @arg @ref LL_RCC_PLLP_DIV_9
+  *         @arg @ref LL_RCC_PLLP_DIV_10
+  *         @arg @ref LL_RCC_PLLP_DIV_11
+  *         @arg @ref LL_RCC_PLLP_DIV_12
+  *         @arg @ref LL_RCC_PLLP_DIV_13
+  *         @arg @ref LL_RCC_PLLP_DIV_14
+  *         @arg @ref LL_RCC_PLLP_DIV_15
+  *         @arg @ref LL_RCC_PLLP_DIV_16
+  *         @arg @ref LL_RCC_PLLP_DIV_17
+  *         @arg @ref LL_RCC_PLLP_DIV_18
+  *         @arg @ref LL_RCC_PLLP_DIV_19
+  *         @arg @ref LL_RCC_PLLP_DIV_20
+  *         @arg @ref LL_RCC_PLLP_DIV_21
+  *         @arg @ref LL_RCC_PLLP_DIV_22
+  *         @arg @ref LL_RCC_PLLP_DIV_23
+  *         @arg @ref LL_RCC_PLLP_DIV_24
+  *         @arg @ref LL_RCC_PLLP_DIV_25
+  *         @arg @ref LL_RCC_PLLP_DIV_26
+  *         @arg @ref LL_RCC_PLLP_DIV_27
+  *         @arg @ref LL_RCC_PLLP_DIV_28
+  *         @arg @ref LL_RCC_PLLP_DIV_29
+  *         @arg @ref LL_RCC_PLLP_DIV_30
+  *         @arg @ref LL_RCC_PLLP_DIV_31
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
+                   ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
+
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 127
+  * @param  __PLLQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
+                   ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
+
+/**
+  * @brief  Helper macro to calculate the HCLK frequency
+  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
+  * @param  __AHBPRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval HCLK clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos] & 0x1FU))
+
+/**
+  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos] & 0x1FU))
+
+/**
+  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos] & 0x1FU))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the Clock Security System.
+  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+  * @brief  Enable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Disable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Enable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Disable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Check if HSE oscillator Ready
+  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI even in stop mode
+  * @note HSI oscillator is forced ON even in Stop mode
+  * @rmtoll CR           HSIKERON      LL_RCC_HSI_EnableInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+  * @brief  Disable HSI in stop mode
+  * @rmtoll CR           HSIKERON      LL_RCC_HSI_DisableInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+  * @brief  Enable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Disable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Check if HSI clock is ready
+  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get HSI Calibration value
+  * @note When HSITRIM is written, HSICAL is updated with the sum of
+  *       HSITRIM and the factory trim value
+  * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
+  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
+}
+
+/**
+  * @brief  Set HSI Calibration trimming
+  * @note user-programmable trimming value that is added to the HSICAL
+  * @note Default value is 16, which, when added to the HSICAL value,
+  *       should trim the HSI to 16 MHz +/- 1 %
+  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
+  * @param  Value Between Min_Data = 0 and Max_Data = 127
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
+}
+
+/**
+  * @brief  Get HSI Calibration trimming
+  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
+  * @retval Between Min_Data = 0 and Max_Data = 127
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI48 HSI48
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI48
+  * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
+{
+  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
+}
+
+/**
+  * @brief  Disable HSI48
+  * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
+{
+  CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
+}
+
+/**
+  * @brief  Check if HSI48 oscillator Ready
+  * @rmtoll CRRCR          HSI48RDY      LL_RCC_HSI48_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
+{
+  return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get HSI48 Calibration value
+  * @rmtoll CRRCR          HSI48CAL      LL_RCC_HSI48_GetCalibration
+  * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+  * @{
+  */
+
+/**
+  * @brief  Enable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Disable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Enable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Disable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Set LSE oscillator drive capability
+  * @note The oscillator is in Xtal mode when it is not in bypass mode.
+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
+  * @param  LSEDrive This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+}
+
+/**
+  * @brief  Get LSE oscillator drive capability
+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+}
+
+/**
+  * @brief  Enable Clock security system on LSE.
+  * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+  * @brief  Disable Clock security system on LSE.
+  * @note Clock security system can be disabled only after a LSE
+  *       failure detection. In that case it MUST be disabled by software.
+  * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_DisableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+  * @brief  Check if LSE oscillator Ready
+  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if CSS on LSE failure Detection
+  * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsCSSDetected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
+{
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Disable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Check if LSI is Ready
+  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSCO LSCO
+  * @{
+  */
+
+/**
+  * @brief  Enable Low speed clock
+  * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+}
+
+/**
+  * @brief  Disable Low speed clock
+  * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+}
+
+/**
+  * @brief  Configure Low speed clock selection
+  * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_SetSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
+}
+
+/**
+  * @brief  Get Low speed clock selection
+  * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_System System
+  * @{
+  */
+
+/**
+  * @brief  Configure the system clock source
+  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+  * @brief  Get the system clock source
+  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Set AHB prescaler
+  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+  * @brief  Set APB1 prescaler
+  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+  * @brief  Set APB2 prescaler
+  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+  * @brief  Get AHB prescaler
+  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+  * @brief  Get APB1 prescaler
+  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+  * @brief  Get APB2 prescaler
+  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+  * @{
+  */
+
+/**
+  * @brief  Configure MCOx
+  * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
+  *         CFGR         MCOPRE        LL_RCC_ConfigMCO
+  * @param  MCOxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
+  *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI48
+  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
+  *
+  *         (*) value not defined in all devices.
+  * @param  MCOxPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1_DIV_1
+  *         @arg @ref LL_RCC_MCO1_DIV_2
+  *         @arg @ref LL_RCC_MCO1_DIV_4
+  *         @arg @ref LL_RCC_MCO1_DIV_8
+  *         @arg @ref LL_RCC_MCO1_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+  * @{
+  */
+
+/**
+  * @brief  Configure USARTx clock source
+  * @rmtoll CCIPR        USARTxSEL     LL_RCC_SetUSARTClockSource
+  * @param  USARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
+{
+  MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
+}
+
+#if defined(UART4)
+/**
+  * @brief  Configure UARTx clock source
+  * @rmtoll CCIPR        UARTxSEL      LL_RCC_SetUARTClockSource
+  * @param  UARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
+{
+  MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
+}
+#endif /* UART4 */
+
+/**
+  * @brief  Configure LPUART1x clock source
+  * @rmtoll CCIPR        LPUART1SEL    LL_RCC_SetLPUARTClockSource
+  * @param  LPUARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
+}
+
+/**
+  * @brief  Configure I2Cx clock source
+  * @rmtoll CCIPR        I2CxSEL       LL_RCC_SetI2CClockSource
+  * @param  I2CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
+{
+  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
+  MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U)));
+}
+
+/**
+  * @brief  Configure LPTIMx clock source
+  * @rmtoll CCIPR        LPTIM1SEL     LL_RCC_SetLPTIMClockSource
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
+}
+
+/**
+  * @brief  Configure SAIx clock source
+  * @rmtoll CCIPR        SAI1SEL       LL_RCC_SetSAIClockSource
+  * @param  SAIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
+}
+
+/**
+  * @brief  Configure I2S clock source
+  * @rmtoll CCIPR        I2S23SEL      LL_RCC_SetI2SClockSource
+  * @param  I2SxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, I2SxSource);
+}
+
+#if defined(FDCAN1)
+/**
+  * @brief  Configure FDCAN clock source
+  * @rmtoll CCIPR        FDCANSEL      LL_RCC_SetFDCANClockSource
+  * @param  FDCANxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, FDCANxSource);
+}
+#endif /* FDCAN1 */
+
+/**
+  * @brief  Configure RNG clock source
+  * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetRNGClockSource
+  * @param  RNGxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
+}
+
+/**
+  * @brief  Configure USB clock source
+  * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetUSBClockSource
+  * @param  USBxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
+}
+
+/**
+  * @brief  Configure ADC clock source
+  * @rmtoll CCIPR        ADC12SEL         LL_RCC_SetADCClockSource\n
+  *         CCIPR        ADC345SEL        LL_RCC_SetADCClockSource
+  * @param  ADCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE   (*)
+  *         @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL    (*)
+  *         @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
+{
+  MODIFY_REG(RCC->CCIPR, 3U << ((ADCxSource & 0x001F0000U) >> 16U), ((ADCxSource & 0x000000FFU) << ((ADCxSource & 0x001F0000U) >> 16U)));
+}
+
+#if defined(QUADSPI)
+/**
+  * @brief  Configure QUADSPI clock source
+  * @rmtoll CCIPR2         QSPISEL     LL_RCC_SetQUADSPIClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetQUADSPIClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, Source);
+}
+#endif /* QUADSPI */
+
+/**
+  * @brief  Get USARTx clock source
+  * @rmtoll CCIPR        USARTxSEL     LL_RCC_GetUSARTClockSource
+  * @param  USARTx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
+}
+
+#if defined(UART4)
+/**
+  * @brief  Get UARTx clock source
+  * @rmtoll CCIPR        UARTxSEL      LL_RCC_GetUARTClockSource
+  * @param  UARTx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
+}
+#endif /* UART4 */
+
+/**
+  * @brief  Get LPUARTx clock source
+  * @rmtoll CCIPR        LPUART1SEL    LL_RCC_GetLPUARTClockSource
+  * @param  LPUARTx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
+}
+
+/**
+  * @brief  Get I2Cx clock source
+  * @rmtoll CCIPR        I2CxSEL       LL_RCC_GetI2CClockSource
+  * @param  I2Cx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+  *
+  *         (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
+{
+  __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
+  return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
+}
+
+/**
+  * @brief  Get LPTIMx clock source
+  * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_GetLPTIMClockSource
+  * @param  LPTIMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx));
+}
+
+/**
+  * @brief  Get SAIx clock source
+  * @rmtoll CCIPR        SAI1SEL       LL_RCC_GetSAIClockSource
+  * @param  SAIx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *
+  *         (*) value not defined in all devices.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx));
+}
+
+/**
+  * @brief  Get I2Sx clock source
+  * @rmtoll CCIPR        I2S23SEL      LL_RCC_GetI2SClockSource
+  * @param  I2Sx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2S_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
+}
+
+#if defined(FDCAN1)
+/**
+  * @brief  Get FDCANx clock source
+  * @rmtoll CCIPR        FDCANSEL      LL_RCC_GetFDCANClockSource
+  * @param  FDCANx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, FDCANx));
+}
+#endif /* FDCAN1 */
+
+/**
+  * @brief  Get RNGx clock source
+  * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetRNGClockSource
+  * @param  RNGx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
+}
+
+/**
+  * @brief  Get USBx clock source
+  * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetUSBClockSource
+  * @param  USBx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
+}
+
+/**
+  * @brief  Get ADCx clock source
+  * @rmtoll CCIPR        ADCSEL        LL_RCC_GetADCClockSource
+  * @param  ADCx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC12_CLKSOURCE
+  *         @arg @ref LL_RCC_ADC345_CLKSOURCE        (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE   (*)
+  *         @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL    (*)
+  *         @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
+{
+  return (uint32_t)((READ_BIT(RCC->CCIPR, 3UL << ((ADCx & 0x001F0000U) >> 16U)) >> ((ADCx & 0x001F0000U) >> 16U)) | (ADCx & 0xFFFF0000U));
+}
+
+#if defined(QUADSPI)
+/**
+  * @brief  Get QUADSPI clock source
+  * @rmtoll CCIPR2         QSPISEL     LL_RCC_GetQUADSPIClockSource
+  * @param  QUADSPIx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetQUADSPIClockSource(uint32_t QUADSPIx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR2, QUADSPIx));
+}
+#endif /* QUADSPI */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+  * @{
+  */
+
+/**
+  * @brief  Set RTC Clock Source
+  * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
+  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+  *       set). The BDRST bit can be used to reset them.
+  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+  * @brief  Get RTC Clock Source
+  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+  * @brief  Enable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Disable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Check if RTC has been enabled or not
+  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Force the Backup domain reset
+  * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @brief  Release the Backup domain reset
+  * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_LL_EF_PLL PLL
+  * @{
+  */
+
+/**
+  * @brief  Enable PLL
+  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+  * @brief  Disable PLL
+  * @note Cannot be disabled if the PLL clock is used as the system clock
+  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+  * @brief  Check if PLL Ready
+  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure PLL used for SYSCLK Domain
+  * @note PLL Source and PLLM Divider can be written only when PLL
+  *       is disabled.
+  * @note PLLN/PLLR can be written only when PLL is disabled.
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  * @param  PLLN Between Min_Data = 8 and Max_Data = 127
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
+}
+
+/**
+  * @brief  Configure PLL used for ADC domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL
+  *       is disabled.
+  * @note PLLN/PLLP can be written only when PLL is disabled.
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_ADC\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_ADC\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_ADC\n
+  *         PLLCFGR      PLLPDIV       LL_RCC_PLL_ConfigDomain_ADC
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  * @param  PLLN Between Min_Data = 8 and Max_Data = 127
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_3
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_5
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_7
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  *         @arg @ref LL_RCC_PLLP_DIV_9
+  *         @arg @ref LL_RCC_PLLP_DIV_10
+  *         @arg @ref LL_RCC_PLLP_DIV_11
+  *         @arg @ref LL_RCC_PLLP_DIV_12
+  *         @arg @ref LL_RCC_PLLP_DIV_13
+  *         @arg @ref LL_RCC_PLLP_DIV_14
+  *         @arg @ref LL_RCC_PLLP_DIV_15
+  *         @arg @ref LL_RCC_PLLP_DIV_16
+  *         @arg @ref LL_RCC_PLLP_DIV_17
+  *         @arg @ref LL_RCC_PLLP_DIV_18
+  *         @arg @ref LL_RCC_PLLP_DIV_19
+  *         @arg @ref LL_RCC_PLLP_DIV_20
+  *         @arg @ref LL_RCC_PLLP_DIV_21
+  *         @arg @ref LL_RCC_PLLP_DIV_22
+  *         @arg @ref LL_RCC_PLLP_DIV_23
+  *         @arg @ref LL_RCC_PLLP_DIV_24
+  *         @arg @ref LL_RCC_PLLP_DIV_25
+  *         @arg @ref LL_RCC_PLLP_DIV_26
+  *         @arg @ref LL_RCC_PLLP_DIV_27
+  *         @arg @ref LL_RCC_PLLP_DIV_28
+  *         @arg @ref LL_RCC_PLLP_DIV_29
+  *         @arg @ref LL_RCC_PLLP_DIV_30
+  *         @arg @ref LL_RCC_PLLP_DIV_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
+             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
+}
+
+/**
+  * @brief  Configure PLL used for 48Mhz domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       is disabled.
+  * @note PLLN/PLLQ can be written only when PLL is disabled.
+  * @note This  can be selected for USB, RNG
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  * @param  PLLN Between Min_Data = 8 and Max_Data = 127
+  * @param  PLLQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
+             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
+}
+
+/**
+  * @brief  Configure PLL clock source
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource
+  * @param PLLSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+}
+
+/**
+  * @brief  Get Main PLL multiplication factor for VCO
+  * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
+  * @retval Between Min_Data = 8 and Max_Data = 127
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
+}
+
+/**
+  * @brief  Get Main PLL division factor for PLLP
+  * @note Used for PLLADCCLK (ADC clock)
+  * @rmtoll PLLCFGR      PLLPDIV       LL_RCC_PLL_GetP\n
+  * @rmtoll PLLCFGR      PLLP          LL_RCC_PLL_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_3
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_5
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_7
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  *         @arg @ref LL_RCC_PLLP_DIV_9
+  *         @arg @ref LL_RCC_PLLP_DIV_10
+  *         @arg @ref LL_RCC_PLLP_DIV_11
+  *         @arg @ref LL_RCC_PLLP_DIV_12
+  *         @arg @ref LL_RCC_PLLP_DIV_13
+  *         @arg @ref LL_RCC_PLLP_DIV_14
+  *         @arg @ref LL_RCC_PLLP_DIV_15
+  *         @arg @ref LL_RCC_PLLP_DIV_16
+  *         @arg @ref LL_RCC_PLLP_DIV_17
+  *         @arg @ref LL_RCC_PLLP_DIV_18
+  *         @arg @ref LL_RCC_PLLP_DIV_19
+  *         @arg @ref LL_RCC_PLLP_DIV_20
+  *         @arg @ref LL_RCC_PLLP_DIV_21
+  *         @arg @ref LL_RCC_PLLP_DIV_22
+  *         @arg @ref LL_RCC_PLLP_DIV_23
+  *         @arg @ref LL_RCC_PLLP_DIV_24
+  *         @arg @ref LL_RCC_PLLP_DIV_25
+  *         @arg @ref LL_RCC_PLLP_DIV_26
+  *         @arg @ref LL_RCC_PLLP_DIV_27
+  *         @arg @ref LL_RCC_PLLP_DIV_28
+  *         @arg @ref LL_RCC_PLLP_DIV_29
+  *         @arg @ref LL_RCC_PLLP_DIV_30
+  *         @arg @ref LL_RCC_PLLP_DIV_31
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
+{
+  return (uint32_t) ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) != 0U) ? READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) : ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) == RCC_PLLCFGR_PLLP) ? LL_RCC_PLLP_DIV_17 : LL_RCC_PLLP_DIV_7) );
+}
+
+/**
+  * @brief  Get Main PLL division factor for PLLQ
+  * @note Used for PLL48M1CLK selected for USB, RNG (48 MHz clock)
+  * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
+}
+
+/**
+  * @brief  Get Main PLL division factor for PLLR
+  * @note Used for PLLCLK (system clock)
+  * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
+}
+
+/**
+  * @brief  Get Division factor for the main PLL and other PLL
+  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_1
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+}
+
+/**
+  * @brief  Enable PLL output mapped on ADC domain clock
+  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_ADC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
+}
+
+/**
+  * @brief  Disable PLL output mapped on ADC domain clock
+  * @note Cannot be disabled if the PLL clock is used as the system
+  *       clock
+  * @note In order to save power, when the PLLCLK  of the PLL is
+  *       not used,  should be 0
+  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_ADC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
+}
+
+/**
+  * @brief  Check if PLL output mapped on ADC domain clock is enabled
+  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_IsEnabledDomain_ADC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL output mapped on 48MHz domain clock
+  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_48M
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
+}
+
+/**
+  * @brief  Disable PLL output mapped on 48MHz domain clock
+  * @note Cannot be disabled if the PLL clock is used as the system
+  *       clock
+  * @note In order to save power, when the PLLCLK  of the PLL is
+  *       not used,  should be 0
+  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_48M
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
+}
+
+/**
+  * @brief  Check if PLL output mapped on 48MHz domain clock is enabled
+  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_IsEnabledDomain_48M
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL output mapped on SYSCLK domain
+  * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_EnableDomain_SYS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
+}
+
+/**
+  * @brief  Disable PLL output mapped on SYSCLK domain
+  * @note Cannot be disabled if the PLL clock is used as the system
+  *       clock
+  * @note In order to save power, when the PLLCLK  of the PLL is
+  *       not used, Main PLL  should be 0
+  * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_DisableDomain_SYS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
+}
+
+/**
+  * @brief  Check if PLL output mapped on SYSCLK domain clock is enabled
+  * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_IsEnabledDomain_SYS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear LSI ready interrupt flag
+  * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
+}
+
+/**
+  * @brief  Clear LSE ready interrupt flag
+  * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
+}
+
+/**
+  * @brief  Clear HSI ready interrupt flag
+  * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
+}
+
+/**
+  * @brief  Clear HSE ready interrupt flag
+  * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
+}
+
+/**
+  * @brief  Clear PLL ready interrupt flag
+  * @rmtoll CICR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
+}
+
+/**
+  * @brief  Clear HSI48 ready interrupt flag
+  * @rmtoll CICR          HSI48RDYC     LL_RCC_ClearFlag_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
+}
+
+/**
+  * @brief  Clear Clock security system interrupt flag
+  * @rmtoll CICR         CSSC          LL_RCC_ClearFlag_HSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_CSSC);
+}
+
+/**
+  * @brief  Clear LSE Clock security system interrupt flag
+  * @rmtoll CICR         LSECSSC       LL_RCC_ClearFlag_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
+}
+
+/**
+  * @brief  Check if LSI ready interrupt occurred or not
+  * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LSE ready interrupt occurred or not
+  * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if HSI ready interrupt occurred or not
+  * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if HSE ready interrupt occurred or not
+  * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if PLL ready interrupt occurred or not
+  * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if HSI48 ready interrupt occurred or not
+  * @rmtoll CIR          HSI48RDYF     LL_RCC_IsActiveFlag_HSI48RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Clock security system interrupt occurred or not
+  * @rmtoll CIFR         CSSF          LL_RCC_IsActiveFlag_HSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LSE Clock security system interrupt occurred or not
+  * @rmtoll CIFR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
+  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+  return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Low Power reset is set or not.
+  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Option byte reset is set or not.
+  * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
+{
+  return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Pin reset is set or not.
+  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+  return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+  return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Window Watchdog reset is set or not.
+  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+  return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag BOR reset is set or not.
+  * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
+{
+  return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set RMVF bit to clear the reset flags.
+  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Enable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Enable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Enable PLL ready interrupt
+  * @rmtoll CIER         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
+}
+
+/**
+  * @brief  Enable HSI48 ready interrupt
+  * @rmtoll CIER          HSI48RDYIE    LL_RCC_EnableIT_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+
+/**
+  * @brief  Enable LSE clock security system interrupt
+  * @rmtoll CIER         LSECSSIE      LL_RCC_EnableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Disable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Disable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Disable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Disable PLL ready interrupt
+  * @rmtoll CIER         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
+}
+
+/**
+  * @brief  Disable HSI48 ready interrupt
+  * @rmtoll CIER          HSI48RDYIE    LL_RCC_DisableIT_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+
+/**
+  * @brief  Disable LSE clock security system interrupt
+  * @rmtoll CIER         LSECSSIE      LL_RCC_DisableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if PLL ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER          HSI48RDYIE    LL_RCC_IsEnabledIT_HSI48RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if LSECSS interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSECSSIE      LL_RCC_IsEnabledIT_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+  * @{
+  */
+void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+#if defined(UART4)
+uint32_t    LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
+#endif /* UART4 */
+uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
+uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+uint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
+#if defined(FDCAN1)
+uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
+#endif /* FDCAN1 */
+uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
+#if defined(QUADSPI)
+uint32_t    LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource);
+#endif /* QUADSPI */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_RCC_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h
new file mode 100644
index 0000000..2a8e877
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h
@@ -0,0 +1,1516 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_system.h
+  * @author  MCD Application Team
+  * @brief   Header file of SYSTEM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL SYSTEM driver contains a set of generic APIs that can be
+    used by user:
+      (+) Some of the FLASH features need to be handled in the SYSTEM file.
+      (+) Access to DBGCMU registers
+      (+) Access to SYSCFG registers
+      (+) Access to VREFBUF registers
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_SYSTEM_H
+#define __STM32G4xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
+
+/** @defgroup SYSTEM_LL SYSTEM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+  * @{
+  */
+
+/* Defines used for position in the register */
+#define DBGMCU_REVID_POSITION         (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
+
+/**
+  * @brief Power-down in Run mode Flash key
+  */
+#define FLASH_PDKEY1                  0x04152637U /*!< Flash power down key1 */
+#define FLASH_PDKEY2                  0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 
+                                                       to unlock the RUN_PD bit in FLASH_ACR */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
+  * @{
+  */
+#define LL_SYSCFG_REMAP_FLASH              0x00000000U                                           /*!< Main Flash memory mapped at 0x00000000              */
+#define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */
+#define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */
+#if defined(FMC_Bank1_R)
+#define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
+#endif /* FMC_Bank1_R */
+#define LL_SYSCFG_REMAP_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000                 */
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_MEMRMP_FB_MODE)
+/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
+  * @{
+  */
+#define LL_SYSCFG_BANKMODE_BANK1           0x00000000U               /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) 
+                                                                      and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00080000) */
+#define LL_SYSCFG_BANKMODE_BANK2           SYSCFG_MEMRMP_FB_MODE     /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) 
+                                                                      and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00080000) */
+/**
+  * @}
+  */
+
+#endif /* SYSCFG_MEMRMP_FB_MODE */
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+  * @{
+  */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6     SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7     SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8     SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
+#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9     SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */
+#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1    SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
+#if defined(I2C2)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2    SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
+#endif /* I2C2 */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3    SYSCFG_CFGR1_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */
+#if defined(I2C4)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4    SYSCFG_CFGR1_I2C4_FMP     /*!< Enable Fast Mode Plus on I2C4 pins */
+#endif /* I2C4 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+  * @{
+  */
+#define LL_SYSCFG_EXTI_PORTA               0U                        /*!< EXTI PORT A                        */
+#define LL_SYSCFG_EXTI_PORTB               1U                        /*!< EXTI PORT B                        */
+#define LL_SYSCFG_EXTI_PORTC               2U                        /*!< EXTI PORT C                        */
+#define LL_SYSCFG_EXTI_PORTD               3U                        /*!< EXTI PORT D                        */
+#define LL_SYSCFG_EXTI_PORTE               4U                        /*!< EXTI PORT E                        */
+#define LL_SYSCFG_EXTI_PORTF               5U                        /*!< EXTI PORT F                        */
+#define LL_SYSCFG_EXTI_PORTG               6U                        /*!< EXTI PORT G                        */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+  * @{
+  */
+#define LL_SYSCFG_EXTI_LINE0               (uint32_t)((0x000FU << 16U) | 0U)  /* !< EXTI_POSITION_0  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1               (uint32_t)((0x00F0U << 16U) | 0U)  /* !< EXTI_POSITION_4  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2               (uint32_t)((0x0F00U << 16U) | 0U)  /* !< EXTI_POSITION_8  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3               (uint32_t)((0xF000U << 16U) | 0U)  /* !< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4               (uint32_t)((0x000FU << 16U) | 1U)  /* !< EXTI_POSITION_0  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5               (uint32_t)((0x00F0U << 16U) | 1U)  /* !< EXTI_POSITION_4  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6               (uint32_t)((0x0F00U << 16U) | 1U)  /* !< EXTI_POSITION_8  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7               (uint32_t)((0xF000U << 16U) | 1U)  /* !< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8               (uint32_t)((0x000FU << 16U) | 2U)  /* !< EXTI_POSITION_0  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9               (uint32_t)((0x00F0U << 16U) | 2U)  /* !< EXTI_POSITION_4  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10              (uint32_t)((0x0F00U << 16U) | 2U)  /* !< EXTI_POSITION_8  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11              (uint32_t)((0xF000U << 16U) | 2U)  /* !< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12              (uint32_t)((0x000FU << 16U) | 3U)  /* !< EXTI_POSITION_0  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13              (uint32_t)((0x00F0U << 16U) | 3U)  /* !< EXTI_POSITION_4  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14              (uint32_t)((0x0F00U << 16U) | 3U)  /* !< EXTI_POSITION_8  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15              (uint32_t)((0xF000U << 16U) | 3U)  /* !< EXTI_POSITION_12 | EXTICR[3] */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+  * @{
+  */
+#define LL_SYSCFG_TIMBREAK_ECC             SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal 
+                                                                   with Break Input of TIM1/8/15/16/17                           */
+#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection 
+                                                                   with TIM1/8/15/16/17 Break Input 
+                                                                   and also the PVDE and PLS bits of the Power Control Interface */
+#define LL_SYSCFG_TIMBREAK_SRAM_PARITY     SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM_PARITY error signal 
+                                                                   with Break Input of TIM1/8/15/16/17                           */
+#define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM4 
+                                                                   with Break Input of TIM1/15/16/17                             */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCMSRAM WRP
+  * @{
+  */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE0         SYSCFG_SWPR_PAGE0  /*!< CCMSRAM Write protection page 0  */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE1         SYSCFG_SWPR_PAGE1  /*!< CCMSRAM Write protection page 1  */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE2         SYSCFG_SWPR_PAGE2  /*!< CCMSRAM Write protection page 2  */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE3         SYSCFG_SWPR_PAGE3  /*!< CCMSRAM Write protection page 3  */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE4         SYSCFG_SWPR_PAGE4  /*!< CCMSRAM Write protection page 4  */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE5         SYSCFG_SWPR_PAGE5  /*!< CCMSRAM Write protection page 5  */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE6         SYSCFG_SWPR_PAGE6  /*!< CCMSRAM Write protection page 6  */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE7         SYSCFG_SWPR_PAGE7  /*!< CCMSRAM Write protection page 7  */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE8         SYSCFG_SWPR_PAGE8  /*!< CCMSRAM Write protection page 8  */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE9         SYSCFG_SWPR_PAGE9  /*!< CCMSRAM Write protection page 9  */
+#if defined(SYSCFG_SWPR_PAGE10)
+#define LL_SYSCFG_CCMSRAMWRP_PAGE10        SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE11        SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE12        SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE13        SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE14        SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE15        SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE16        SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE17        SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE18        SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE19        SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE20        SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE21        SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE22        SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE23        SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE24        SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE25        SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE26        SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE27        SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE28        SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE29        SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE30        SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE31        SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
+#endif /* SYSCFG_SWPR_PAGE10 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+  * @{
+  */
+#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1FZR1_DBG_TIM2_STOP   /*!< The counter clock of TIM2 is stopped when the core is halted*/
+#if defined(TIM3)
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1FZR1_DBG_TIM3_STOP   /*!< The counter clock of TIM3 is stopped when the core is halted*/
+#endif /* TIM3 */
+#if defined(TIM4)
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1FZR1_DBG_TIM4_STOP   /*!< The counter clock of TIM4 is stopped when the core is halted*/
+#endif /* TIM4 */
+#if defined(TIM5)
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1FZR1_DBG_TIM5_STOP   /*!< The counter clock of TIM5 is stopped when the core is halted*/
+#endif /* TIM5 */
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1FZR1_DBG_TIM6_STOP   /*!< The counter clock of TIM6 is stopped when the core is halted*/
+#if defined(TIM7)
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1FZR1_DBG_TIM7_STOP   /*!< The counter clock of TIM7 is stopped when the core is halted*/
+#endif /* TIM7 */
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1FZR1_DBG_RTC_STOP    /*!< The clock of the RTC counter is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1FZR1_DBG_WWDG_STOP   /*!< The window watchdog counter clock is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1FZR1_DBG_IWDG_STOP   /*!< The independent watchdog counter clock is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1FZR1_DBG_I2C1_STOP   /*!< The I2C1 SMBus timeout is frozen*/
+#if defined(I2C2)
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1FZR1_DBG_I2C2_STOP   /*!< The I2C2 SMBus timeout is frozen*/
+#endif /* I2C2 */
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1FZR1_DBG_I2C3_STOP   /*!< The I2C3 SMBus timeout is frozen*/
+#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
+  * @{
+  */
+#if defined(I2C4)
+#define LL_DBGMCU_APB1_GRP2_I2C4_STOP      DBGMCU_APB1FZR2_DBG_I2C4_STOP   /*!< The I2C4 SMBus timeout is frozen*/
+#endif /* I2C4 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ_DBG_TIM1_STOP     /*!< The counter clock of TIM1 is stopped when the core is halted*/
+#if defined(TIM8)
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ_DBG_TIM8_STOP     /*!< The counter clock of TIM8 is stopped when the core is halted*/
+#endif /* TIM8 */
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ_DBG_TIM15_STOP    /*!< The counter clock of TIM15 is stopped when the core is halted*/
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ_DBG_TIM16_STOP    /*!< The counter clock of TIM16 is stopped when the core is halted*/
+#if defined(TIM17)
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ_DBG_TIM17_STOP    /*!< The counter clock of TIM17 is stopped when the core is halted*/
+#endif /* TIM17 */
+#if defined(TIM20)
+#define LL_DBGMCU_APB2_GRP1_TIM20_STOP     DBGMCU_APB2FZ_DBG_TIM20_STOP    /*!< The counter clock of TIM20 is stopped when the core is halted*/
+#endif /* TIM20 */
+#if defined(HRTIM1)
+#define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP     DBGMCU_APB2FZ_DBG_HRTIM1_STOP    /*!< The counter clock of HRTIM1 is stopped when the core is halted*/
+#endif /* HRTIM1 */
+/**
+  * @}
+  */
+
+#if defined(VREFBUF)
+/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
+  * @{
+  */
+#define LL_VREFBUF_VOLTAGE_SCALE0          ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
+#define LL_VREFBUF_VOLTAGE_SCALE1          VREFBUF_CSR_VRS_0      /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V)   */
+#define LL_VREFBUF_VOLTAGE_SCALE2          VREFBUF_CSR_VRS_1      /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V)   */
+/**
+  * @}
+  */
+#endif /* VREFBUF */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+  * @{
+  */
+#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
+#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
+#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
+#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
+#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
+#if defined(FLASH_ACR_LATENCY_5WS)
+#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
+#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
+#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
+#define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH eight wait states */
+#define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */
+#define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS  /*!< FLASH ten wait states */
+#define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS  /*!< FLASH eleven wait states */
+#define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS  /*!< FLASH twelve wait states */
+#define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS  /*!< FLASH thirteen wait states */
+#define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS  /*!< FLASH fourteen wait states */
+#define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS  /*!< FLASH fifteen wait states */
+#endif /* FLASH_ACR_LATENCY_5WS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+  * @{
+  */
+
+/**
+  * @brief  Set memory mapping at address 0x00000000
+  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory
+  * @param  Memory This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_REMAP_FLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SRAM
+  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
+  *         @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
+{
+  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
+}
+
+/**
+  * @brief  Get memory mapping at address 0x00000000
+  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_REMAP_FLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SRAM
+  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
+  *         @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
+  *
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
+}
+
+#if defined(SYSCFG_MEMRMP_FB_MODE)
+/**
+  * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
+  * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_SetFlashBankMode
+  * @param  Bank This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
+{
+  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
+}
+
+/**
+  * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
+  * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_GetFlashBankMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
+}
+#endif /* SYSCFG_MEMRMP_FB_MODE */
+
+/**
+  * @brief  Enable I/O analog switch voltage booster.
+  * @note   When voltage booster is enabled, I/O analog switches are supplied
+  *         by a dedicated voltage booster, from VDD power domain. This is
+  *         the recommended configuration with low VDDA voltage operation.
+  * @note   The I/O analog switch voltage booster is relevant for peripherals
+  *         using I/O in analog input: ADC, COMP, OPAMP.
+  *         However, COMP and OPAMP inputs have a high impedance and
+  *         voltage booster do not impact performance significantly.
+  *         Therefore, the voltage booster is mainly intended for
+  *         usage with ADC.
+  * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_EnableAnalogBooster
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+  * @brief  Disable I/O analog switch voltage booster.
+  * @note   When voltage booster is enabled, I/O analog switches are supplied
+  *         by a dedicated voltage booster, from VDD power domain. This is
+  *         the recommended configuration with low VDDA voltage operation.
+  * @note   The I/O analog switch voltage booster is relevant for peripherals
+  *         using I/O in analog input: ADC, COMP, OPAMP.
+  *         However, COMP and OPAMP inputs have a high impedance and
+  *         voltage booster do not impact performance significantly.
+  *         Therefore, the voltage booster is mainly intended for
+  *         usage with ADC.
+  * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_DisableAnalogBooster
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+  * @brief  Enable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
+  *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Disable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
+  *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Enable Floating Point Unit Invalid operation Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_EnableIT_FPU_IOC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
+}
+
+/**
+  * @brief  Enable Floating Point Unit Divide-by-zero Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_EnableIT_FPU_DZC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
+}
+
+/**
+  * @brief  Enable Floating Point Unit Underflow Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_EnableIT_FPU_UFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
+}
+
+/**
+  * @brief  Enable Floating Point Unit Overflow Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_EnableIT_FPU_OFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
+}
+
+/**
+  * @brief  Enable Floating Point Unit Input denormal Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_EnableIT_FPU_IDC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
+}
+
+/**
+  * @brief  Enable Floating Point Unit Inexact Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_EnableIT_FPU_IXC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
+}
+
+/**
+  * @brief  Disable Floating Point Unit Invalid operation Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_DisableIT_FPU_IOC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
+}
+
+/**
+  * @brief  Disable Floating Point Unit Divide-by-zero Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_DisableIT_FPU_DZC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
+}
+
+/**
+  * @brief  Disable Floating Point Unit Underflow Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_DisableIT_FPU_UFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
+}
+
+/**
+  * @brief  Disable Floating Point Unit Overflow Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_DisableIT_FPU_OFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
+}
+
+/**
+  * @brief  Disable Floating Point Unit Input denormal Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_DisableIT_FPU_IDC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
+}
+
+/**
+  * @brief  Disable Floating Point Unit Inexact Interrupt
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_DisableIT_FPU_IXC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
+}
+
+/**
+  * @brief  Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_IsEnabledIT_FPU_IOC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
+{
+  return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_IsEnabledIT_FPU_DZC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
+{
+  return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_IsEnabledIT_FPU_UFC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
+{
+  return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_IsEnabledIT_FPU_OFC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
+{
+  return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_IsEnabledIT_FPU_IDC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
+{
+  return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
+  * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_IsEnabledIT_FPU_IXC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
+{
+  return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure source input for the EXTI external interrupt.
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
+  * @param  Port This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG
+  *
+  *         (*) value not defined in all devices
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+  MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << (POSITION_VAL((Line >> 16U)) & 0x1FU) );
+}
+
+/**
+  * @brief  Get the configured defined for specific EXTI Line
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG
+  *
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x1FU));
+}
+
+/**
+  * @brief  Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation. This bit is
+  * automatically cleared at the end of the CCMSRAM erase operation.)
+  * @note This bit is write-protected: setting this bit is possible only after the
+  *       correct key sequence is written in the SYSCFG_SKR register as described in
+  *       the Reference Manual.
+  * @rmtoll SYSCFG_SCSR  CCMER       LL_SYSCFG_EnableCCMSRAMErase
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMErase(void)
+{
+  /* Starts a hardware CCMSRAM erase operation*/
+  SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
+}
+
+/**
+  * @brief  Check if CCMSRAM erase operation is on going
+  * @rmtoll SYSCFG_SCSR  CCMBSY      LL_SYSCFG_IsCCMSRAMEraseOngoing
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsCCMSRAMEraseOngoing(void)
+{
+  return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMBSY) == (SYSCFG_SCSR_CCMBSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set connections to TIM1/8/15/16/17 Break inputs
+  * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR2 SPL           LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_SetTIMBreakInputs
+  * @param  Break This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
+  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
+}
+
+/**
+  * @brief  Get connections to TIM1/8/15/16/17 Break inputs
+  * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR2 SPL           LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_GetTIMBreakInputs
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
+  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
+}
+
+/**
+  * @brief  Check if SRAM parity error detected
+  * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_IsActiveFlag_SP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
+{
+  return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear SRAM parity error flag
+  * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_ClearFlag_SP
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
+{
+  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
+}
+
+/**
+  * @brief  Enable CCMSRAM page write protection
+  * @note Write protection is cleared only by a system reset
+  * @rmtoll SYSCFG_SWPR  PAGEx         LL_SYSCFG_EnableCCMSRAMPageWRP
+  * @param  CCMSRAMWRP This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE16 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE17 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE18 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE19 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE20 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE21 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE22 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE23 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE24 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE25 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE26 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE27 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE28 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE29 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE30 (*)
+  *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE31 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMPageWRP(uint32_t CCMSRAMWRP)
+{
+  SET_BIT(SYSCFG->SWPR, CCMSRAMWRP);
+}
+
+/**
+  * @brief  CCMSRAM page write protection lock prior to erase
+  * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_LockCCMSRAMWRP
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_LockCCMSRAMWRP(void)
+{
+  /* Writing a wrong key reactivates the write protection */
+  WRITE_REG(SYSCFG->SKR, 0x00);
+}
+
+/**
+  * @brief  CCMSRAM page write protection unlock prior to erase
+  * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_UnlockCCMSRAMWRP
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_UnlockCCMSRAMWRP(void)
+{
+  /* unlock the write protection of the CCMER bit */
+  WRITE_REG(SYSCFG->SKR, 0xCA);
+  WRITE_REG(SYSCFG->SKR, 0x53);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+  * @{
+  */
+
+/**
+  * @brief  Return the device identifier
+  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
+  * @retval Values between Min_Data=0x00 and Max_Data=0x0FFF (ex: device ID is 0x6415)
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+  * @brief  Return the device revision identifier
+  * @note This field indicates the revision of the device.
+  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> (DBGMCU_REVID_POSITION & 0x1FU));
+}
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Set Trace pin assignment control
+  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
+  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
+  * @param  PinAssignment This parameter can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRACE_NONE
+  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+{
+  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+}
+
+/**
+  * @brief  Get Trace pin assignment control
+  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
+  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRACE_NONE
+  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+  * @brief  Freeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1FZR1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB1 peripherals (group2 peripherals)
+  * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1FZR2, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group2 peripherals)
+  * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
+}
+
+/**
+  * @brief  Freeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+  * @}
+  */
+
+#if defined(VREFBUF)
+/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
+  * @{
+  */
+
+/**
+  * @brief  Enable Internal voltage reference
+  * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_VREFBUF_Enable(void)
+{
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+  * @brief  Disable Internal voltage reference
+  * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_VREFBUF_Disable(void)
+{
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+  * @brief  Enable high impedance (VREF+pin is high impedance)
+  * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_EnableHIZ
+  * @retval None
+  */
+__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
+{
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
+}
+
+/**
+  * @brief  Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
+  * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_DisableHIZ
+  * @retval None
+  */
+__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
+{
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
+}
+
+/**
+  * @brief  Set the Voltage reference scale
+  * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_SetVoltageScaling
+  * @param  Scale This parameter can be one of the following values:
+  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
+  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
+  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
+{
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
+}
+
+/**
+  * @brief  Get the Voltage reference scale
+  * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_GetVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
+  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
+  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
+  */
+__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
+{
+  return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
+}
+
+/**
+  * @brief  Check if Voltage reference buffer is ready
+  * @rmtoll VREFBUF_CSR  VRR           LL_VREFBUF_IsVREFReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
+{
+  return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the trimming code for VREFBUF calibration
+  * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_GetTrimming
+  * @retval Between 0 and 0x3F
+  */
+__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
+{
+  return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
+}
+
+/**
+  * @brief  Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
+  * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_SetTrimming
+  * @param  Value Between 0 and 0x3F
+  * @retval None
+  */
+__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
+{
+  WRITE_REG(VREFBUF->CCR, Value);
+}
+
+/**
+  * @}
+  */
+#endif /* VREFBUF */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+  * @{
+  */
+
+/**
+  * @brief  Set FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
+  * @param  Latency This parameter can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5 (*)
+  *         @arg @ref LL_FLASH_LATENCY_6 (*)
+  *         @arg @ref LL_FLASH_LATENCY_7 (*)
+  *         @arg @ref LL_FLASH_LATENCY_8 (*)
+  *         @arg @ref LL_FLASH_LATENCY_9 (*)
+  *         @arg @ref LL_FLASH_LATENCY_10 (*)
+  *         @arg @ref LL_FLASH_LATENCY_11 (*)
+  *         @arg @ref LL_FLASH_LATENCY_12 (*)
+  *         @arg @ref LL_FLASH_LATENCY_13 (*)
+  *         @arg @ref LL_FLASH_LATENCY_14 (*)
+  *         @arg @ref LL_FLASH_LATENCY_15 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+  * @brief  Get FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5 (*)
+  *         @arg @ref LL_FLASH_LATENCY_6 (*)
+  *         @arg @ref LL_FLASH_LATENCY_7 (*)
+  *         @arg @ref LL_FLASH_LATENCY_8 (*)
+  *         @arg @ref LL_FLASH_LATENCY_9 (*)
+  *         @arg @ref LL_FLASH_LATENCY_10 (*)
+  *         @arg @ref LL_FLASH_LATENCY_11 (*)
+  *         @arg @ref LL_FLASH_LATENCY_12 (*)
+  *         @arg @ref LL_FLASH_LATENCY_13 (*)
+  *         @arg @ref LL_FLASH_LATENCY_14 (*)
+  *         @arg @ref LL_FLASH_LATENCY_15 (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+  * @brief  Enable Prefetch
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+  * @brief  Disable Prefetch
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+  * @brief  Check if Prefetch buffer is enabled
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
+{
+  return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Instruction cache
+  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+  * @brief  Disable Instruction cache
+  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+  * @brief  Enable Data cache
+  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+  * @brief  Disable Data cache
+  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+  * @brief  Enable Instruction cache reset
+  * @note  bit can be written only when the instruction cache is disabled
+  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+  * @brief  Disable Instruction cache reset
+  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+  * @brief  Enable Data cache reset
+  * @note bit can be written only when the data cache is disabled
+  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+/**
+  * @brief  Disable Data cache reset
+  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+/**
+  * @brief  Enable Flash Power-down mode during run mode or Low-power run mode
+  * @note Flash memory can be put in power-down mode only when the code is executed
+  *       from RAM
+  * @note Flash must not be accessed when power down is enabled
+  * @note Flash must not be put in power-down while a program or an erase operation
+  *       is on-going
+  * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\n
+  *         FLASH_PDKEYR PDKEY1        LL_FLASH_EnableRunPowerDown\n
+  *         FLASH_PDKEYR PDKEY2        LL_FLASH_EnableRunPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
+{
+  /* Following values must be written consecutively to unlock the RUN_PD bit in
+     FLASH_ACR */
+  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
+  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
+  SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
+}
+
+/**
+  * @brief  Disable Flash Power-down mode during run mode or Low-power run mode
+  * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_DisableRunPowerDown\n
+  *         FLASH_PDKEYR PDKEY1        LL_FLASH_DisableRunPowerDown\n
+  *         FLASH_PDKEYR PDKEY2        LL_FLASH_DisableRunPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
+{
+  /* Following values must be written consecutively to unlock the RUN_PD bit in
+     FLASH_ACR */
+  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
+  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
+}
+
+/**
+  * @brief  Enable Flash Power-down mode during Sleep or Low-power sleep mode
+  * @note Flash must not be put in power-down while a program or an erase operation
+  *       is on-going
+  * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_EnableSleepPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
+}
+
+/**
+  * @brief  Disable Flash Power-down mode during Sleep or Low-power sleep mode
+  * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_DisableSleepPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_SYSTEM_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h
new file mode 100644
index 0000000..d42f158
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h
@@ -0,0 +1,6716 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_LL_TIM_H
+#define __STM32G4xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20)
+
+/** @defgroup TIM_LL TIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  * @{
+  */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+  0x00U,   /* 0: TIMx_CH1  */
+  0x00U,   /* 1: TIMx_CH1N */
+  0x00U,   /* 2: TIMx_CH2  */
+  0x00U,   /* 3: TIMx_CH2N */
+  0x04U,   /* 4: TIMx_CH3  */
+  0x04U,   /* 5: TIMx_CH3N */
+  0x04U,   /* 6: TIMx_CH4  */
+  0x04U,   /* 7: TIMx_CH4N */
+  0x38U,   /* 8: TIMx_CH5  */
+  0x38U    /* 9: TIMx_CH6  */
+
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+  0U,            /* 0: OC1M, OC1FE, OC1PE */
+  0U,            /* 1: - NA */
+  8U,            /* 2: OC2M, OC2FE, OC2PE */
+  0U,            /* 3: - NA */
+  0U,            /* 4: OC3M, OC3FE, OC3PE */
+  0U,            /* 5: - NA */
+  8U,            /* 6: OC4M, OC4FE, OC4PE */
+  0U,            /* 7: - NA */
+  0U,            /* 8: OC5M, OC5FE, OC5PE */
+  8U             /* 9: OC6M, OC6FE, OC6PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+  0U,            /* 0: CC1S, IC1PSC, IC1F */
+  0U,            /* 1: - NA */
+  8U,            /* 2: CC2S, IC2PSC, IC2F */
+  0U,            /* 3: - NA */
+  0U,            /* 4: CC3S, IC3PSC, IC3F */
+  0U,            /* 5: - NA */
+  8U,            /* 6: CC4S, IC4PSC, IC4F */
+  0U,            /* 7: - NA */
+  0U,            /* 8: - NA */
+  0U             /* 9: - NA */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+  0U,            /* 0: CC1P */
+  2U,            /* 1: CC1NP */
+  4U,            /* 2: CC2P */
+  6U,            /* 3: CC2NP */
+  8U,            /* 4: CC3P */
+  10U,           /* 5: CC3NP */
+  12U,           /* 6: CC4P */
+  14U,           /* 7: CC4NP */
+  16U,           /* 8: CC5P */
+  20U            /* 9: CC6P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+  0U,            /* 0: OIS1 */
+  1U,            /* 1: OIS1N */
+  2U,            /* 2: OIS2 */
+  3U,            /* 3: OIS2N */
+  4U,            /* 4: OIS3 */
+  5U,            /* 5: OIS3N */
+  6U,            /* 6: OIS4 */
+  7U,            /* 7: OIS4N */
+  8U,            /* 8: OIS5 */
+  10U            /* 9: OIS6 */
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+  * @{
+  */
+
+/* Defines used for the bit position in the register and perform offsets */
+#define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) & 0x1FUL)
+
+/* Generic bit definitions for TIMx_AF1 register */
+#define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */
+#define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */
+
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+/**
+@endcond
+  */
+
+#define OCREF_CLEAR_SELECT_Pos (28U)
+#define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos)                /*!< 0x10000000 */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+  * @{
+  */
+/** @brief  Convert channel id into channel index.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval none
+  */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
+
+/** @brief  Calculate the deadtime sampling period(in ps).
+  * @param  __TIMCLK__ timer input clock frequency (in Hz).
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval none
+  */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
+  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
+   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  TIM Time Base configuration structure definition.
+  */
+typedef struct
+{
+  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetPrescaler().*/
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetCounterMode().*/
+
+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+                                   Some timer instances may support 32 bits counters. In that case this parameter must
+                                   be a number between 0x0000 and 0xFFFFFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetAutoReload().*/
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetClockDivision().*/
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                   reaches zero, an update event is generated and counting restarts
+                                   from the RCR value (N).
+                                   This means in PWM mode that (N+1) corresponds to:
+                                      - the number of PWM periods in edge-aligned mode
+                                      - the number of half PWM period in center-aligned mode
+                                   GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                   Max_Data = 0xFF.
+                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                   Max_Data = 0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the output mode.
+                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetMode().*/
+
+  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                               This feature can be modified afterwards using unitary function
+                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture configuration structure definition.
+  */
+
+typedef struct
+{
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t ICActiveInput; /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+  * @brief  TIM Encoder interface configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_SetEncoderMode().*/
+
+  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+  * @brief  TIM Hall sensor interface configuration structure definition.
+  */
+typedef struct
+{
+
+  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
+                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
+                                    Prescaler must be set to get a maximum counter period longer than the
+                                    time interval between 2 consecutive changes on the Hall inputs.
+                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
+                                    This parameter can be a value of
+                                    @ref TIM_LL_EC_IC_FILTER.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+                                    A positive pulse (TRGO event) is generated with a programmable delay every time
+                                    a change occurs on the Hall inputs.
+                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+  * @brief  BDTR (Break and Dead Time) structure definition
+  */
+typedef struct
+{
+  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                       programmed. */
+
+  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                      programmed. */
+
+  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+                                      register has been written, their content is frozen until the next reset.*/
+
+  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_OC_SetDeadTime()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+                                       programmed. */
+
+  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakAFMode;           /*!< Specifies the alternate function mode of the break input.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note Bidirectional break input is only supported by advanced timers instances.
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2AFMode;          /*!< Specifies the alternate function mode of the break2 input.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note Bidirectional break input is only supported by advanced timers instances.
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+  * @{
+  */
+#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
+#define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
+#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
+#define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
+#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
+#define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
+#define LL_TIM_SR_IDXF                         TIM_SR_IDXF          /*!< Index interrupt flag  */
+#define LL_TIM_SR_DIRF                         TIM_SR_DIRF          /*!< Direction Change interrupt flag  */
+#define LL_TIM_SR_IERRF                        TIM_SR_IERRF         /*!< Index Error flag  */
+#define LL_TIM_SR_TERRF                        TIM_SR_TERRF         /*!< Transition Error flag  */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+  * @{
+  */
+#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+  * @{
+  */
+#define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
+#define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+  * @{
+  */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+  * @{
+  */
+#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
+#define LL_TIM_DIER_IDXIE                      TIM_DIER_IDXIE       /*!< Index interrupt enable */
+#define LL_TIM_DIER_DIRIE                      TIM_DIER_DIRIE       /*!< Direction Change interrupt enable */
+#define LL_TIM_DIER_IERRIE                     TIM_DIER_IERRIE      /*!< Index Error interrupt enable */
+#define LL_TIM_DIER_TERRIE                     TIM_DIER_TERRIE      /*!< Transition Error interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+  * @{
+  */
+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+  * @{
+  */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+  * @{
+  */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+  * @{
+  */
+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+  * @{
+  */
+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
+  * @{
+  */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+  * @{
+  */
+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+  * @{
+  */
+#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
+#define LL_TIM_CHANNEL_CH4N                    TIM_CCER_CC4NE     /*!< Timer complementary output channel 4 */
+#define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
+#define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+  * @{
+  */
+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+  * @{
+  */
+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+#define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
+#define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
+#define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
+#define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
+#define LL_TIM_OCMODE_PULSE_ON_COMPARE         (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)                    /*!<Pulse on Compare mode */
+#define LL_TIM_OCMODE_DIRECTION_OUTPUT         (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+  * @{
+  */
+#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+  * @{
+  */
+#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
+  * @{
+  */
+#define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+  * @{
+  */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+  * @{
+  */
+#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+  * @{
+  */
+#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+  * @{
+  */
+#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+  * @{
+  */
+#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+  * @{
+  */
+#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
+#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2     (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)                                   /*!< Encoder mode: Clock plus direction - x2 mode */
+#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1     (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
+#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2       (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)                                   /*!< Encoder mode: Directional Clock, x2 mode */
+#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12  (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
+#define LL_TIM_ENCODERMODE_X1_TI1                    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
+#define LL_TIM_ENCODERMODE_X1_TI2                    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+  * @{
+  */
+#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+#define LL_TIM_TRGO_ENCODERCLK                 TIM_CR2_MMS_3                                   /*!< Encoder clock signal is used as trigger output */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
+  * @{
+  */
+#define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
+#define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
+#define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
+#define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+  * @{
+  */
+#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
+#define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET   (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)   /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
+                                                                                        the counter are controlled. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
+  * @{
+  */
+#define LL_TIM_SMSPS_TIMUPDATE                 0x00000000U                         /*!< The SMS preload transfer is triggered by the Timer's Update event */
+#define LL_TIM_SMSPS_INDEX                     TIM_SMCR_SMSPS                      /*!< The SMS preload transfer is triggered by the Index event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+  * @{
+  */
+#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
+#define LL_TIM_TS_ITR4                         TIM_SMCR_TS_3                                                   /*!< Internal Trigger 4 (ITR4) is used as trigger input */
+#define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_0)                                 /*!< Internal Trigger 5 (ITR5) is used as trigger input */
+#define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 6 (ITR6) is used as trigger input */
+#define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */
+#define LL_TIM_TS_ITR8                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_2)                                 /*!< Internal Trigger 8 (ITR8) is used as trigger input */
+#define LL_TIM_TS_ITR9                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                 /*!< Internal Trigger 9 (ITR9) is used as trigger input */
+#define LL_TIM_TS_ITR10                        (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                 /*!< Internal Trigger 10 (ITR10) is used as trigger input */
+#define LL_TIM_TS_ITR11                        (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+  * @{
+  */
+#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+  * @{
+  */
+#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+  * @{
+  */
+#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
+  * @{
+  */
+#define LL_TIM_TIM1_ETRSOURCE_GPIO        0x00000000U                                                  /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM1_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                            /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM1_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                            /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM1_ETRSOURCE_COMP3       (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM1_ETRSOURCE_COMP4       TIM1_AF1_ETRSEL_2                                            /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM1_ETRSOURCE_COMP5       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM1_ETRSOURCE_COMP6       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                      /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM1_ETRSOURCE_COMP7       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1   TIM1_AF1_ETRSEL_3                                            /*!< ADC1 analog watchdog 1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                      /*!< ADC1 analog watchdog 2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                      /*!< ADC1 analog watchdog 3 */
+#if defined(ADC4)
+#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ADC4 analog watchdog 1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                      /*!< ADC4 analog watchdog 2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)  /*!< ADC4 analog watchdog 3 */
+#endif /* ADC4 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
+  * @{
+  */
+#define LL_TIM_TIM2_ETRSOURCE_GPIO         0x00000000U                                                 /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM2_ETRSOURCE_COMP1        TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM2_ETRSOURCE_COMP2        TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM2_ETRSOURCE_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM2_ETRSOURCE_COMP4        TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM2_ETRSOURCE_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM2_ETRSOURCE_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM2_ETRSOURCE_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR     TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM3 ETR */
+#define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM4 ETR */
+#if defined(TIM5)
+#define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to TIM5 ETR */
+#endif /* TIM5 */
+#define LL_TIM_TIM2_ETRSOURCE_LSE          (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
+  * @{
+  */
+#define LL_TIM_TIM3_ETRSOURCE_GPIO         0x00000000U                                                 /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM3_ETRSOURCE_COMP1        TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM3_ETRSOURCE_COMP2        TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM3_ETRSOURCE_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM3_ETRSOURCE_COMP4        TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM3_ETRSOURCE_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM3_ETRSOURCE_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM3_ETRSOURCE_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR     TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM2 ETR */
+#define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM4 ETR */
+#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */
+#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                     /*!< ADC2 analog watchdog 2 */
+#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
+  * @{
+  */
+#define LL_TIM_TIM4_ETRSOURCE_GPIO         0x00000000U                                                 /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM4_ETRSOURCE_COMP1        TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM4_ETRSOURCE_COMP2        TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM4_ETRSOURCE_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM4_ETRSOURCE_COMP4        TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM4_ETRSOURCE_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM4_ETRSOURCE_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM4_ETRSOURCE_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR     TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM3 ETR */
+#if defined(TIM5)
+#define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM5 ETR */
+#endif /* TIM5 */
+/**
+  * @}
+  */
+
+#if defined(TIM5)
+/** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
+  * @{
+  */
+#define LL_TIM_TIM5_ETRSOURCE_GPIO         0x00000000U                                                 /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM5_ETRSOURCE_COMP1        TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM5_ETRSOURCE_COMP2        TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM5_ETRSOURCE_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM5_ETRSOURCE_COMP4        TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM5_ETRSOURCE_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM5_ETRSOURCE_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM5_ETRSOURCE_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR     TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM2 ETR */
+#define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM3 ETR */
+/**
+  * @}
+  */
+#endif /* TIM5 */
+
+/** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
+  * @{
+  */
+#define LL_TIM_TIM8_ETRSOURCE_GPIO        0x00000000U                                                  /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM8_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                            /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM8_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                            /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM8_ETRSOURCE_COMP3       (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM8_ETRSOURCE_COMP4       TIM1_AF1_ETRSEL_2                                            /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM8_ETRSOURCE_COMP5       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM8_ETRSOURCE_COMP6       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                      /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM8_ETRSOURCE_COMP7       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1   TIM1_AF1_ETRSEL_3                                            /*!< ADC2 analog watchdog 1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                      /*!< ADC2 analog watchdog 2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                      /*!< ADC2 analog watchdog 3 */
+#if defined(ADC3)
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ADC3 analog watchdog 1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                      /*!< ADC3 analog watchdog 2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)  /*!< ADC3 analog watchdog 3 */
+#endif /* ADC3 */
+/**
+  * @}
+  */
+
+#if defined(TIM20)
+/** @defgroup TIM_LL_EC_TIM20_ETRSOURCE External Trigger Source TIM20
+  * @{
+  */
+#define LL_TIM_TIM20_ETRSOURCE_GPIO       0x00000000U                                                  /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM20_ETRSOURCE_COMP1      TIM1_AF1_ETRSEL_0                                            /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM20_ETRSOURCE_COMP2      TIM1_AF1_ETRSEL_1                                            /*!< ETR input is connected to COMP2_OUT */
+#define LL_TIM_TIM20_ETRSOURCE_COMP3      (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP3_OUT */
+#define LL_TIM_TIM20_ETRSOURCE_COMP4      TIM1_AF1_ETRSEL_2                                            /*!< ETR input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM20_ETRSOURCE_COMP5      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM20_ETRSOURCE_COMP6      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                      /*!< ETR input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM20_ETRSOURCE_COMP7      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ETR input is connected to COMP7_OUT */
+#endif /* COMP7 */
+#if defined(ADC3)
+#define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1  TIM1_AF1_ETRSEL_3                                            /*!< ADC3 analog watchdog 1 */
+#define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                      /*!< ADC3 analog watchdog 2 */
+#define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                      /*!< ADC3 analog watchdog 3 */
+#endif /* ADC3 */
+#if defined(ADC5)
+#define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ADC5 analog watchdog 1 */
+#define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                      /*!< ADC5 analog watchdog 2 */
+#define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)  /*!< ADC5 analog watchdog 3 */
+#endif /* ADC5 */
+/**
+  * @}
+  */
+#endif /* TIM20 */
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+  * @{
+  */
+#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
+  * @{
+  */
+#define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
+  * @{
+  */
+#define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
+#define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
+  * @{
+  */
+#define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+  * @{
+  */
+#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+  * @{
+  */
+#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
+  * @{
+  */
+#define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
+#define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
+  * @{
+  */
+#define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */
+#define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */
+#define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */
+#define LL_TIM_BKIN_SOURCE_BKCOMP3             TIM1_AF1_BKCMP3E    /*!< internal signal: COMP3 output */
+#define LL_TIM_BKIN_SOURCE_BKCOMP4             TIM1_AF1_BKCMP4E    /*!< internal signal: COMP4 output */
+#if defined(COMP5)
+#define LL_TIM_BKIN_SOURCE_BKCOMP5             TIM1_AF1_BKCMP5E    /*!< internal signal: COMP5 output */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_BKIN_SOURCE_BKCOMP6             TIM1_AF1_BKCMP6E    /*!< internal signal: COMP6 output */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_BKIN_SOURCE_BKCOMP7             TIM1_AF1_BKCMP7E    /*!< internal signal: COMP7 output */
+#endif /* COMP7 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
+  * @{
+  */
+#define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */
+#define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
+  * @{
+  */
+#define LL_TIM_BREAK_AFMODE_INPUT              0x00000000U              /*!< Break input BRK in input mode */
+#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL      TIM_BDTR_BKBID           /*!< Break input BRK in bidirectional mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
+  * @{
+  */
+#define LL_TIM_BREAK2_AFMODE_INPUT             0x00000000U             /*!< Break2 input BRK2 in input mode */
+#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL     TIM_BDTR_BK2BID         /*!< Break2 input BRK2 in bidirectional mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+  * @{
+  */
+#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DTR2          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ECR           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_ECR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_OR            (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_OR register is the DMA base address for DMA burst */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+  * @{
+  */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_19TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 19 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_20TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 20 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_21TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 21 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_22TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 22 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_23TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 23 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_24TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_25TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_3)                                 /*!< Transfer is done to 25 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_26TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_3 |  TIM_DCR_DBL_0)               /*!< Transfer is done to 26 registers starting from the DMA burst base address */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM1_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM1 input 1 is connected to GPIO */
+#define LL_TIM_TIM1_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM1 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM1_TI1_RMP_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM1 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM1_TI1_RMP_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM1 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM1_TI1_RMP_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM1 input 1 is connected to COMP4_OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_TI1_RMP  TIM2 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM2_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 1 is connected to GPIO */
+#define LL_TIM_TIM2_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM2 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM2_TI1_RMP_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM2 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM2_TI1_RMP_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM2 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM2_TI1_RMP_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM2 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM2_TI1_RMP_COMP5  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM2 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_TI2_RMP  TIM2 Timer Input Ch2 Remap
+  * @{
+  */
+#define LL_TIM_TIM2_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 2 is connected to GPIO */
+#define LL_TIM_TIM2_TI2_RMP_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM2 input 2 is connected to COMP1_OUT */
+#define LL_TIM_TIM2_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM2 input 2 is connected to COMP2_OUT */
+#define LL_TIM_TIM2_TI2_RMP_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM2 input 2 is connected to COMP3_OUT */
+#define LL_TIM_TIM2_TI2_RMP_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM2 input 2 is connected to COMP4_OUT */
+#if defined(COMP6)
+#define LL_TIM_TIM2_TI2_RMP_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM2 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_TI3_RMP  TIM2 Timer Input Ch3 Remap
+  * @{
+  */
+#define LL_TIM_TIM2_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 3 is connected to GPIO */
+#define LL_TIM_TIM2_TI3_RMP_COMP4  TIM_TISEL_TI3SEL_0                                /*!< TIM2 input 3 is connected to COMP4_OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 Timer Input Ch4 Remap
+  * @{
+  */
+#define LL_TIM_TIM2_TI4_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 4 is connected to GPIO */
+#define LL_TIM_TIM2_TI4_RMP_COMP1  TIM_TISEL_TI4SEL_0                                /*!< TIM2 input 4 is connected to COMP1_OUT */
+#define LL_TIM_TIM2_TI4_RMP_COMP2  TIM_TISEL_TI4SEL_1                                /*!< TIM2 input 4 is connected to COMP2_OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM3_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM3 input 1 is connected to GPIO */
+#define LL_TIM_TIM3_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM3 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM3 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM3 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM3 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM3_TI1_RMP_COMP5  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM3 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM3_TI1_RMP_COMP6  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)         /*!< TIM3 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM3_TI1_RMP_COMP7  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)   /*!< TIM3 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM3_TI2_RMP  TIM3 Timer Input Ch2 Remap
+  * @{
+  */
+#define LL_TIM_TIM3_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM3 input 2 is connected to GPIO */
+#define LL_TIM_TIM3_TI2_RMP_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM3 input 2 is connected to COMP1_OUT */
+#define LL_TIM_TIM3_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM3 input 2 is connected to COMP2_OUT */
+#define LL_TIM_TIM3_TI2_RMP_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM3 input 2 is connected to COMP3_OUT */
+#define LL_TIM_TIM3_TI2_RMP_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM3 input 2 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM3_TI2_RMP_COMP5  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM3 input 2 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM3_TI2_RMP_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1)         /*!< TIM3 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM3_TI2_RMP_COMP7  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)   /*!< TIM3 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM3_TI3_RMP  TIM3 Timer Input Ch3 Remap
+  * @{
+  */
+#define LL_TIM_TIM3_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM3 input 3 is connected to GPIO */
+#define LL_TIM_TIM3_TI3_RMP_COMP3  TIM_TISEL_TI3SEL_0                                /*!< TIM3 input 3 is connected to COMP3_OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM4_TI1_RMP  TIM4 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM4_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 1 is connected to GPIO */
+#define LL_TIM_TIM4_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM4 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM4_TI1_RMP_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM4 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM4_TI1_RMP_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM4 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM4_TI1_RMP_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM4 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM4_TI1_RMP_COMP5  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM4 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM4_TI1_RMP_COMP6  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)         /*!< TIM4 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM4_TI1_RMP_COMP7  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)   /*!< TIM4 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM4_TI2_RMP  TIM4 Timer Input Ch2 Remap
+  * @{
+  */
+#define LL_TIM_TIM4_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 2 is connected to GPIO */
+#define LL_TIM_TIM4_TI2_RMP_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM4 input 2 is connected to COMP1_OUT */
+#define LL_TIM_TIM4_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM4 input 2 is connected to COMP2_OUT */
+#define LL_TIM_TIM4_TI2_RMP_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM4 input 2 is connected to COMP3_OUT */
+#define LL_TIM_TIM4_TI2_RMP_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM4 input 2 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM4_TI2_RMP_COMP5  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM4 input 2 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM4_TI2_RMP_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1)         /*!< TIM4 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM4_TI2_RMP_COMP7  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)   /*!< TIM4 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM4_TI3_RMP  TIM4 Timer Input Ch3 Remap
+  * @{
+  */
+#define LL_TIM_TIM4_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 3 is connected to GPIO */
+#if defined(COMP5)
+#define LL_TIM_TIM4_TI3_RMP_COMP5  TIM_TISEL_TI3SEL_0                                /*!< TIM4 input 3 is connected to COMP5_OUT */
+#endif /* COMP5 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM4_TI4_RMP  TIM4 Timer Input Ch4 Remap
+  * @{
+  */
+#define LL_TIM_TIM4_TI4_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 4 is connected to GPIO */
+#if defined(COMP6)
+#define LL_TIM_TIM4_TI4_RMP_COMP6  TIM_TISEL_TI4SEL_0                                /*!< TIM4 input 4 is connected to COMP6_OUT */
+#endif /* COMP6 */
+/**
+  * @}
+  */
+
+#if defined(TIM5)
+/** @defgroup TIM_LL_EC_TIM5_TI1_RMP  TIM5 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM5_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM5 input 1 is connected to GPIO */
+#define LL_TIM_TIM5_TI1_RMP_LSI    TIM_TISEL_TI1SEL_0                                /*!< TIM5 input 1 is connected to LSI */
+#define LL_TIM_TIM5_TI1_RMP_LSE    TIM_TISEL_TI1SEL_1                                /*!< TIM5 input 1 is connected to LSE */
+#define LL_TIM_TIM5_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM5 input 1 is connected to RTC_WAKEUP */
+#define LL_TIM_TIM5_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_2                                /*!< TIM5 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM5_TI1_RMP_COMP2  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM5 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM5_TI1_RMP_COMP3  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)         /*!< TIM5 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM5_TI1_RMP_COMP4  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)   /*!< TIM5 input 1 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM5_TI1_RMP_COMP5  TIM_TISEL_TI1SEL_3                                /*!< TIM5 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM5_TI1_RMP_COMP6  (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0)         /*!< TIM5 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM5_TI1_RMP_COMP7  (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1)         /*!< TIM5 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM5_TI2_RMP  TIM5 Timer Input Ch2 Remap
+  * @{
+  */
+#define LL_TIM_TIM5_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM5 input 2 is connected to GPIO */
+#define LL_TIM_TIM5_TI2_RMP_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM5 input 2 is connected to COMP1_OUT */
+#define LL_TIM_TIM5_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM5 input 2 is connected to COMP2_OUT */
+#define LL_TIM_TIM5_TI2_RMP_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM5 input 2 is connected to COMP3_OUT */
+#define LL_TIM_TIM5_TI2_RMP_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM5 input 2 is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM5_TI2_RMP_COMP5  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM5 input 2 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_TIM5_TI2_RMP_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1)         /*!< TIM5 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM5_TI2_RMP_COMP7  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)   /*!< TIM5 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+  * @}
+  */
+#endif /* TIM5 */
+
+/** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM8_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM8 input 1 is connected to GPIO */
+#define LL_TIM_TIM8_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM8 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM8_TI1_RMP_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM8 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM8_TI1_RMP_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM8 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM8_TI1_RMP_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM8 input 1 is connected to COMP4_OUT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM15_TI1_RMP_GPIO  0x00000000U                                       /*!< TIM15 input 1 is connected to GPIO */
+#define LL_TIM_TIM15_TI1_RMP_LSE   TIM_TISEL_TI1SEL_0                                /*!< TIM15 input 1 is connected to LSE */
+#define LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1                                /*!< TIM15 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM15 input 1 is connected to COMP2_OUT */
+#if defined(COMP5)
+#define LL_TIM_TIM15_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_2                                /*!< TIM15 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP7)
+#define LL_TIM_TIM15_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM15 input 1 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 Timer Input Ch2 Remap
+  * @{
+  */
+#define LL_TIM_TIM15_TI2_RMP_GPIO  0x00000000U                                       /*!< TIM15 input 2 is connected to GPIO */
+#define LL_TIM_TIM15_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0                                /*!< TIM15 input 2 is connected to COMP2_OUT */
+#define LL_TIM_TIM15_TI2_RMP_COMP3 TIM_TISEL_TI2SEL_1                                /*!< TIM15 input 2 is connected to COMP3_OUT */
+#if defined(COMP6)
+#define LL_TIM_TIM15_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM15 input 2 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_TIM15_TI2_RMP_COMP7 TIM_TISEL_TI2SEL_2                                /*!< TIM15 input 2 is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM16_TI1_RMP_GPIO    0x00000000U                                     /*!< TIM16 input 1 is connected to GPIO */
+#if defined(COMP6)
+#define LL_TIM_TIM16_TI1_RMP_COMP6   TIM_TISEL_TI1SEL_0                              /*!< TIM16 input 1 is connected to COMP6_OUT */
+#endif /* COMP6 */
+#define LL_TIM_TIM16_TI1_RMP_MCO     TIM_TISEL_TI1SEL_1                              /*!< TIM16 input 1 is connected to MCO */
+#define LL_TIM_TIM16_TI1_RMP_HSE_32  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)       /*!< TIM16 input 1 is connected to HSE/32 */
+#define LL_TIM_TIM16_TI1_RMP_RTC_WK  TIM_TISEL_TI1SEL_2                              /*!< TIM16 input 1 is connected to RTC_WAKEUP */
+#define LL_TIM_TIM16_TI1_RMP_LSE     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)       /*!< TIM16 input 1 is connected to LSE */
+#define LL_TIM_TIM16_TI1_RMP_LSI     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)       /*!< TIM16 input 1 is connected to LSI */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM17_TI1_RMP_GPIO    0x00000000U                                     /*!< TIM17 input 1 is connected to GPIO */
+#if defined(COMP5)
+#define LL_TIM_TIM17_TI1_RMP_COMP5   TIM_TISEL_TI1SEL_0                              /*!< TIM17 input 1 is connected to COMP5_OUT */
+#endif /* COMP5 */
+#define LL_TIM_TIM17_TI1_RMP_MCO     TIM_TISEL_TI1SEL_1                              /*!< TIM17 input 1 is connected to MCO */
+#define LL_TIM_TIM17_TI1_RMP_HSE_32  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)       /*!< TIM17 input 1 is connected to HSE/32 */
+#define LL_TIM_TIM17_TI1_RMP_RTC_WK  TIM_TISEL_TI1SEL_2                              /*!< TIM17 input 1 is connected to RTC_WAKEUP */
+#define LL_TIM_TIM17_TI1_RMP_LSE     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)       /*!< TIM17 input 1 is connected to LSE */
+#define LL_TIM_TIM17_TI1_RMP_LSI     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)       /*!< TIM17 input 1 is connected to LSI */
+/**
+  * @}
+  */
+
+#if defined(TIM20)
+/** @defgroup TIM_LL_EC_TIM20_TI1_RMP  TIM20 Timer Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM20_TI1_RMP_GPIO  0x00000000U                                      /*!< TIM20 input 1 is connected to GPIO */
+#define LL_TIM_TIM20_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0                               /*!< TIM20 input 1 is connected to COMP1_OUT */
+#define LL_TIM_TIM20_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1                               /*!< TIM20 input 1 is connected to COMP2_OUT */
+#define LL_TIM_TIM20_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)        /*!< TIM20 input 1 is connected to COMP3_OUT */
+#define LL_TIM_TIM20_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2                               /*!< TIM20 input 1 is connected to COMP4_OUT */
+/**
+  * @}
+  */
+#endif /* TIM20 */
+
+/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
+  * @{
+  */
+#define LL_TIM_OCREF_CLR_INT_ETR         OCREF_CLEAR_SELECT_Msk                   /*!< OCREF_CLR_INT is connected to ETRF */
+#define LL_TIM_OCREF_CLR_INT_COMP1       0x00000000U                              /*!< OCREF clear input is connected to COMP1_OUT */
+#define LL_TIM_OCREF_CLR_INT_COMP2       TIM1_AF2_OCRSEL_0                        /*!< OCREF clear input is connected to COMP2_OUT */
+#define LL_TIM_OCREF_CLR_INT_COMP3       TIM1_AF2_OCRSEL_1                        /*!< OCREF clear input is connected to COMP3_OUT */
+#define LL_TIM_OCREF_CLR_INT_COMP4       (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0)  /*!< OCREF clear input is connected to COMP4_OUT */
+#if defined(COMP5)
+#define LL_TIM_OCREF_CLR_INT_COMP5       TIM1_AF2_OCRSEL_2                        /*!< OCREF clear input is connected to COMP5_OUT */
+#endif /* COMP5 */
+#if defined(COMP6)
+#define LL_TIM_OCREF_CLR_INT_COMP6       (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0)  /*!< OCREF clear input is connected to COMP6_OUT */
+#endif /* COMP6 */
+#if defined(COMP7)
+#define LL_TIM_OCREF_CLR_INT_COMP7       (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1)  /*!< OCREF clear input is connected to COMP7_OUT */
+#endif /* COMP7 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
+  * @{
+  */
+#define LL_TIM_INDEX_UP_DOWN     0x00000000U         /*!< Index resets the counter whatever the direction */
+#define LL_TIM_INDEX_UP          TIM_ECR_IDIR_0      /*!< Index resets the counter when up-counting only */
+#define LL_TIM_INDEX_DOWN        TIM_ECR_IDIR_1      /*!< Index resets the counter when down-counting only */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
+  * @{
+  */
+#define LL_TIM_INDEX_POSITION_DOWN_DOWN    0x00000000U                           /*!< Index resets the counter when AB = 00 */
+#define LL_TIM_INDEX_POSITION_DOWN_UP      TIM_ECR_IPOS_0                        /*!< Index resets the counter when AB = 01 */
+#define LL_TIM_INDEX_POSITION_UP_DOWN      TIM_ECR_IPOS_1                        /*!< Index resets the counter when AB = 10 */
+#define LL_TIM_INDEX_POSITION_UP_UP        (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)     /*!< Index resets the counter when AB = 11 */
+#define LL_TIM_INDEX_POSITION_DOWN         0x00000000U                           /*!< Index resets the counter when clock is 0 */
+#define LL_TIM_INDEX_POSITION_UP           TIM_ECR_IPOS_0                        /*!< Index resets the counter when clock is 1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
+  * @{
+  */
+#define LL_TIM_INDEX_ALL           0x00000000U                           /*!< Index is always active */
+#define LL_TIM_INDEX_FIRST_ONLY    TIM_ECR_FIDX                          /*!< The first Index only resets the counter */
+/**
+  * @}
+  */
+/** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
+  * @{
+  */
+#define LL_TIM_PWPRSC_X1     0x00000000U                                              /*!< Pulse on compare pulse width prescaler 1 */
+#define LL_TIM_PWPRSC_X2     TIM_ECR_PWPRSC_0                                         /*!< Pulse on compare pulse width prescaler 2 */
+#define LL_TIM_PWPRSC_X4     TIM_ECR_PWPRSC_1                                         /*!< Pulse on compare pulse width prescaler 4 */
+#define LL_TIM_PWPRSC_X8     (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0)                    /*!< Pulse on compare pulse width prescaler 8 */
+#define LL_TIM_PWPRSC_X16    TIM_ECR_PWPRSC_2                                         /*!< Pulse on compare pulse width prescaler 16 */
+#define LL_TIM_PWPRSC_X32    (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0)                    /*!< Pulse on compare pulse width prescaler 32 */
+#define LL_TIM_PWPRSC_X64    (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1)                    /*!< Pulse on compare pulse width prescaler 64 */
+#define LL_TIM_PWPRSC_X128   (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_HSE_32_REQUEST Clock HSE/32 request
+  * @{
+  */
+#define LL_TIM_HSE_32_NOT_REQUEST     0x00000000U            /*!< Clock HSE/32 not requested */
+#define LL_TIM_HSE_32_REQUEST         TIM_OR_HSE32EN         /*!< Clock HSE/32 requested for TIM16/17 TI1SEL remap */
+/**
+  * @}
+  */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
+/**
+@endcond
+  */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+/**
+  * @brief  Write a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
+  * @{
+  */
+
+/**
+  * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
+  * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+  * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
+  *        to TIMx_CNT register bit 31)
+  * @param  __CNT__ Counter value
+  * @retval UIF status bit
+  */
+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
+  (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+
+/**
+  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @param  __DT__ deadtime duration (in ns)
+  * @retval DTG[0:7]
+  */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
+  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
+    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
+    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
+                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
+    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+    0U)
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+  *         output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
+   (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
+  *         active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
+  *         output compare active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+  *         (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+  *         pulse duration (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+  * @param  __ICPSC__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+  */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+  * @{
+  */
+/**
+  * @brief  Enable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Disable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Indicates whether the timer counter is enabled.
+  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Disable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Indicates whether update event generation is enabled.
+  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval Inverted state of bit (0 or 1).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set update event source
+  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+  *       generate an update interrupt or DMA request if enabled:
+  *        - Counter overflow/underflow
+  *        - Setting the UG bit
+  *        - Update generation through the slave mode controller
+  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+  *       overflow/underflow generates an update interrupt or DMA request if enabled.
+  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+  * @param  TIMx Timer instance
+  * @param  UpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+  * @brief  Get actual event update source
+  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+  * @brief  Set one pulse mode (one shot v.s. repetitive).
+  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+  * @param  TIMx Timer instance
+  * @param  OnePulseMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+  * @brief  Get actual one pulse mode.
+  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+  * @brief  Set the timer counter counting mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *       requires a timer reset to avoid unexpected direction
+  *       due to DIR bit readonly in center aligned mode.
+  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+  *         CR1          CMS           LL_TIM_SetCounterMode
+  * @param  TIMx Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+}
+
+/**
+  * @brief  Get actual counter mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+  *         CR1          CMS           LL_TIM_GetCounterMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+{
+  uint32_t counter_mode;
+
+  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+  if (counter_mode == 0U)
+  {
+    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+  }
+
+  return counter_mode;
+}
+
+/**
+  * @brief  Enable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Disable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
+  *         (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+  * @param  TIMx Timer instance
+  * @param  ClockDivision This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
+  *         generators (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+  * @brief  Set the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note If dithering is activated, pay attention to the Counter value interpretation
+  * @rmtoll CNT          CNT           LL_TIM_SetCounter
+  * @param  TIMx Timer instance
+  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+  WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+  * @brief  Get the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note If dithering is activated, pay attention to the Counter value interpretation
+  * @rmtoll CNT          CNT           LL_TIM_GetCounter
+  * @param  TIMx Timer instance
+  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+  * @brief  Get the current direction of the counter
+  * @rmtoll CR1          DIR           LL_TIM_GetDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+  * @brief  Set the prescaler value.
+  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+  * @note The prescaler can be changed on the fly as this control register is buffered. The new
+  *       prescaler ratio is taken into account at the next update event.
+  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Prescaler between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+  WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+  * @brief  Get the prescaler value.
+  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+  * @param  TIMx Timer instance
+  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+  * @brief  Set the auto-reload value.
+  * @note The counter is blocked while the auto-reload value is null.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+  *       In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
+  *       parameter.
+  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+  * @param  TIMx Timer instance
+  * @param  AutoReload between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+  WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+  * @brief  Get the auto-reload value.
+  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note If dithering is activated, pay attention to the returned value interpretation
+  * @param  TIMx Timer instance
+  * @retval Auto-reload value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+  * @brief  Set the repetition counter value.
+  * @note For advanced timer instances RepetitionCounter can be up to 65535.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+  WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+  * @brief  Get the repetition counter value.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @retval Repetition counter value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+  *       in an atomic way.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) copy is set.
+  * @param  Counter Counter value
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
+{
+  return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable dithering.
+  * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides dithering.
+  * @rmtoll CR1          DITHEN          LL_TIM_EnableDithering
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
+}
+
+/**
+  * @brief  Disable dithering.
+  * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides dithering.
+  * @rmtoll CR1          DITHEN          LL_TIM_DisableDithering
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
+}
+
+/**
+  * @brief  Indicates whether dithering is activated.
+  * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides dithering.
+  * @rmtoll CR1          DITHEN          LL_TIM_IsEnabledDithering
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+  * @{
+  */
+/**
+  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+  *       they are updated only when a commutation event (COM) occurs.
+  * @note Only on channels that have a complementary output.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
+  * @param  TIMx Timer instance
+  * @param  CCUpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+  * @brief  Set the trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @param  DMAReqTrigger This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+  * @brief  Get actual trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+  * @brief  Set the lock level to freeze the
+  *         configuration of several capture/compare parameters.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       the lock mechanism is supported by a timer instance.
+  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
+  * @param  TIMx Timer instance
+  * @param  LockLevel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_LOCKLEVEL_OFF
+  *         @arg @ref LL_TIM_LOCKLEVEL_1
+  *         @arg @ref LL_TIM_LOCKLEVEL_2
+  *         @arg @ref LL_TIM_LOCKLEVEL_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+  * @brief  Enable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_EnableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Disable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_DisableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Indicate whether channel(s) is(are) enabled.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure an output channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS6          LL_TIM_OC_ConfigOutput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Define the behavior of the output reference signal OCxREF from which
+  *         OCx and OCxN (when relevant) are derived.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_SetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+  *         @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE   (for channel 3 or channel 4 only)
+  *         @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT   (for channel 3 or channel 4 only)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Get the output compare mode of an output channel.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_GetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+  *         @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE   (for channel 3 or channel 4 only)
+  *         @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT   (for channel 3 or channel 4 only)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Set the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the IDLE state of an output channel
+  * @note This function is significant only for the timer instances
+  *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+  *       can be used to check whether or not a timer instance provides
+  *       a break input.
+  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS4N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_SetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  IdleState This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Get the IDLE state of an output channel
+  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS4N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_GetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Enable fast mode for the output channel.
+  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Disable fast mode for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Indicates whether fast mode is enabled for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable clearing the output channel on an external event.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
+  * @note This function enables clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+  *         the Ocx and OCxN signals).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       dead-time insertion feature is supported by a timer instance.
+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
+  * @param  TIMx Timer instance
+  * @param  DeadTime between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 5 (TIMx_CCR5).
+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 6 (TIMx_CCR6).
+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR6, CompareValue);
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 3 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR6));
+}
+
+/**
+  * @brief  Select on which reference signal the OC5REF is combined to.
+  * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the combined 3-phase PWM mode.
+  * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
+  * @param  TIMx Timer instance
+  * @param  GroupCH5 This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_GROUPCH5_NONE
+  *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+{
+  MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
+}
+
+/**
+  * @brief  Set the pulse on compare pulse width prescaler.
+  * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+  *       whether or not the pulse on compare feature is supported by the timer
+  *       instance.
+  * @rmtoll ECR          PWPRSC           LL_TIM_OC_SetPulseWidthPrescaler
+  * @param  TIMx Timer instance
+  * @param  PulseWidthPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_PWPRSC_X1
+  *         @arg @ref LL_TIM_PWPRSC_X2
+  *         @arg @ref LL_TIM_PWPRSC_X4
+  *         @arg @ref LL_TIM_PWPRSC_X8
+  *         @arg @ref LL_TIM_PWPRSC_X16
+  *         @arg @ref LL_TIM_PWPRSC_X32
+  *         @arg @ref LL_TIM_PWPRSC_X64
+  *         @arg @ref LL_TIM_PWPRSC_X128
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
+}
+
+/**
+  * @brief  Get the pulse on compare pulse width prescaler.
+  * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+  *       whether or not the pulse on compare feature is supported by the timer
+  *       instance.
+  * @rmtoll ECR          PWPRSC           LL_TIM_OC_GetPulseWidthPrescaler
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_PWPRSC_X1
+  *         @arg @ref LL_TIM_PWPRSC_X2
+  *         @arg @ref LL_TIM_PWPRSC_X4
+  *         @arg @ref LL_TIM_PWPRSC_X8
+  *         @arg @ref LL_TIM_PWPRSC_X16
+  *         @arg @ref LL_TIM_PWPRSC_X32
+  *         @arg @ref LL_TIM_PWPRSC_X64
+  *         @arg @ref LL_TIM_PWPRSC_X128
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
+}
+
+/**
+  * @brief  Set the pulse on compare pulse width duration.
+  * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+  *       whether or not the pulse on compare feature is supported by the timer
+  *       instance.
+  * @rmtoll ECR          PW           LL_TIM_OC_SetPulseWidth
+  * @param  TIMx Timer instance
+  * @param  PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
+}
+
+/**
+  * @brief  Get the pulse on compare pulse width duration.
+  * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+  *       whether or not the pulse on compare feature is supported by the timer
+  *       instance.
+  * @rmtoll ECR          PW           LL_TIM_OC_GetPulseWidth
+  * @param  TIMx Timer instance
+  * @retval Returned value can be between Min_Data=0 and Max_Data=255:
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure input channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC1F          LL_TIM_IC_Config\n
+  *         CCMR1        CC2S          LL_TIM_IC_Config\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC2F          LL_TIM_IC_Config\n
+  *         CCMR2        CC3S          LL_TIM_IC_Config\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC3F          LL_TIM_IC_Config\n
+  *         CCMR2        CC4S          LL_TIM_IC_Config\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC4F          LL_TIM_IC_Config\n
+  *         CCER         CC1P          LL_TIM_IC_Config\n
+  *         CCER         CC1NP         LL_TIM_IC_Config\n
+  *         CCER         CC2P          LL_TIM_IC_Config\n
+  *         CCER         CC2NP         LL_TIM_IC_Config\n
+  *         CCER         CC3P          LL_TIM_IC_Config\n
+  *         CCER         CC3NP         LL_TIM_IC_Config\n
+  *         CCER         CC4P          LL_TIM_IC_Config\n
+  *         CCER         CC4NP         LL_TIM_IC_Config
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
+             << SHIFT_TAB_ICxx[iChannel]);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICActiveInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the prescaler of input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current prescaler value acting on an  input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the current input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+          SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get captured value for input channel 1.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 1 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get captured value for input channel 2.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 2 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get captured value for input channel 3.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 3 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get captured value for input channel 4.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 4 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+  * @{
+  */
+/**
+  * @brief  Enable external clock mode 2.
+  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Disable external clock mode 2.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Indicate whether external clock mode 2 is enabled.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the clock source of the counter clock.
+  * @note when selected clock source is external clock mode 1, the timer input
+  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+  *       function. This timer input must be configured by calling
+  *       the @ref LL_TIM_IC_Config() function.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode1.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+  *         SMCR         ECE           LL_TIM_SetClockSource
+  * @param  TIMx Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+  * @brief  Set the encoder interface mode.
+  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the encoder mode.
+  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+  * @param  TIMx Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+  *         @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
+  *         @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
+  *         @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
+  *         @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
+  *         @arg @ref LL_TIM_ENCODERMODE_X1_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X1_TI2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger output (TRGO) used for timer synchronization .
+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can operate as a master timer.
+  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+  * @param  TIMx Timer instance
+  * @param  TimerSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO_RESET
+  *         @arg @ref LL_TIM_TRGO_ENABLE
+  *         @arg @ref LL_TIM_TRGO_UPDATE
+  *         @arg @ref LL_TIM_TRGO_CC1IF
+  *         @arg @ref LL_TIM_TRGO_OC1REF
+  *         @arg @ref LL_TIM_TRGO_OC2REF
+  *         @arg @ref LL_TIM_TRGO_OC3REF
+  *         @arg @ref LL_TIM_TRGO_OC4REF
+  *         @arg @ref LL_TIM_TRGO_ENCODERCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+  * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
+  * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can be used for ADC synchronization.
+  * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
+  * @param  TIMx Timer Instance
+  * @param  ADCSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO2_RESET
+  *         @arg @ref LL_TIM_TRGO2_ENABLE
+  *         @arg @ref LL_TIM_TRGO2_UPDATE
+  *         @arg @ref LL_TIM_TRGO2_CC1F
+  *         @arg @ref LL_TIM_TRGO2_OC1
+  *         @arg @ref LL_TIM_TRGO2_OC2
+  *         @arg @ref LL_TIM_TRGO2_OC3
+  *         @arg @ref LL_TIM_TRGO2_OC4
+  *         @arg @ref LL_TIM_TRGO2_OC5
+  *         @arg @ref LL_TIM_TRGO2_OC6
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+}
+
+/**
+  * @brief  Set the synchronization mode of a slave timer.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+  * @param  TIMx Timer instance
+  * @param  SlaveMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+  *         @arg @ref LL_TIM_SLAVEMODE_RESET
+  *         @arg @ref LL_TIM_SLAVEMODE_GATED
+  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+  * @brief  Set the selects the trigger input to be used to synchronize the counter.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+  * @param  TIMx Timer instance
+  * @param  TriggerInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TS_ITR0
+  *         @arg @ref LL_TIM_TS_ITR1
+  *         @arg @ref LL_TIM_TS_ITR2
+  *         @arg @ref LL_TIM_TS_ITR3
+  *         @arg @ref LL_TIM_TS_TI1F_ED
+  *         @arg @ref LL_TIM_TS_TI1FP1
+  *         @arg @ref LL_TIM_TS_TI2FP2
+  *         @arg @ref LL_TIM_TS_ETRF
+  *         @arg @ref LL_TIM_TS_ITR4
+  *         @arg @ref LL_TIM_TS_ITR5
+  *         @arg @ref LL_TIM_TS_ITR6
+  *         @arg @ref LL_TIM_TS_ITR7
+  *         @arg @ref LL_TIM_TS_ITR8
+  *         @arg @ref LL_TIM_TS_ITR9
+  *         @arg @ref LL_TIM_TS_ITR10
+  *         @arg @ref LL_TIM_TS_ITR11
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+  * @brief  Enable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief  Disable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief Indicates whether the Master/Slave mode is enabled.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the external trigger (ETR) input.
+  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an external trigger input.
+  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+  *         SMCR         ETPS          LL_TIM_ConfigETR\n
+  *         SMCR         ETF           LL_TIM_ConfigETR
+  * @param  TIMx Timer instance
+  * @param  ETRPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+  * @param  ETRPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+  * @param  ETRFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+                                      uint32_t ETRFilter)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+  * @brief  Select the external trigger (ETR) input source.
+  * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports ETR source selection.
+  * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource
+  * @param  TIMx Timer instance
+  * @param  ETRSource This parameter can be one of the following values:
+  *
+  *         TIM1: any combination of ETR_RMP where
+  *
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP3
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP4
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP5       (*)
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP6       (*)
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP7       (*)
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1   (*)
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2   (*)
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3   (*)
+  *
+  *         TIM2: any combination of ETR_RMP where
+  *
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP3
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP4
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP5       (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP6       (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP7       (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR    (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
+  *
+  *         TIM3: any combination of ETR_RMP where
+  *
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP3
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP4
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP5       (*)
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP6       (*)
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP7       (*)
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3
+  *
+  *         TIM4: any combination of ETR_RMP where
+  *
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP3
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP4
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP5       (*)
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP6       (*)
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP7       (*)
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR    (*)
+  *
+  *         TIM5: any combination of ETR_RMP where       (**)
+  *
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO        (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1       (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2       (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP3       (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP4       (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP5       (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP6       (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP7       (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR    (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR    (*)
+  *
+  *         TIM8: any combination of ETR_RMP where
+  *
+  *            . . ETR_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP3
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP4
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP5       (*)
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP6       (*)
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP7       (*)
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (*)
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (*)
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   (*)
+  *
+  *         TIM20: any combination of ETR_RMP where       (**)
+  *
+  *            . . ETR_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_GPIO       (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP1      (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP2      (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP3      (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP4      (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP5      (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP6      (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP7      (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1  (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2  (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3  (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1  (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2  (*)
+  *            @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3  (*)
+  *
+  *         (*)  Value not defined in all devices. \n
+  *         (**) Register not available in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
+{
+  MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
+}
+
+/**
+  * @brief  Enable SMS preload.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPE           LL_TIM_EnableSMSPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
+}
+
+/**
+  * @brief  Disable SMS preload.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPE           LL_TIM_DisableSMSPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
+}
+
+/**
+  * @brief  Indicate whether  SMS preload is enabled.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPE           LL_TIM_IsEnabledSMSPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the preload source of SMS.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPS        LL_TIM_SetSMSPreloadSource\n
+  * @param  TIMx Timer instance
+  * @param  PreloadSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SMSPS_TIMUPDATE
+  *         @arg @ref LL_TIM_SMSPS_INDEX
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
+}
+
+/**
+  * @brief  Get the preload source of SMS.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPS        LL_TIM_GetSMSPreloadSource\n
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_SMSPS_TIMUPDATE
+  *         @arg @ref LL_TIM_SMSPS_INDEX
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+  * @{
+  */
+/**
+  * @brief  Enable the break function.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+  * @brief  Disable the break function.
+  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
+  * @param  TIMx Timer instance
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+  * @brief  Configure the break input.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @note Bidirectional mode is only supported by advanced timer instances.
+  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance is an advanced-control timer.
+  * @note In bidirectional mode (BKBID bit set), the Break input is configured both
+  *        in input mode and in open drain output mode. Any active Break event will
+  *        assert a low logic level on the Break input to indicate an internal break
+  *        event to external devices.
+  * @note When bidirectional mode isn't supported, BreakAFMode must be set to
+  *       LL_TIM_BREAK_AFMODE_INPUT.
+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+  *         BDTR         BKF           LL_TIM_ConfigBRK\n
+  *         BDTR         BKBID         LL_TIM_ConfigBRK
+  * @param  TIMx Timer instance
+  * @param  BreakPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+  * @param  BreakFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+  * @param  BreakAFMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_AFMODE_INPUT
+  *         @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
+                                      uint32_t BreakAFMode)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
+}
+
+/**
+  * @brief  Disarm the break input (when it operates in bidirectional mode).
+  * @note  The break input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output .
+  * @rmtoll BDTR         BKDSRM        LL_TIM_DisarmBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+/**
+  * @brief  Re-arm the break input (when it operates in bidirectional mode).
+  * @note  The Break input is automatically armed as soon as MOE bit is set.
+  * @rmtoll BDTR         BKDSRM        LL_TIM_ReArmBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+/**
+  * @brief  Enable the break 2 function.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+  * @brief  Disable the break  2 function.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+  * @brief  Configure the break 2 input.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @note Bidirectional mode is only supported by advanced timer instances.
+  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance is an advanced-control timer.
+  * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
+  *        in input mode and in open drain output mode. Any active Break event will
+  *        assert a low logic level on the Break 2 input to indicate an internal break
+  *        event to external devices.
+  * @note When bidirectional mode isn't supported, Break2AFMode must be set to
+  *       LL_TIM_BREAK2_AFMODE_INPUT.
+  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2F          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2BID        LL_TIM_ConfigBRK2
+  * @param  TIMx Timer instance
+  * @param  Break2Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+  * @param  Break2Filter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+  * @param  Break2AFMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
+  *         @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
+                                       uint32_t Break2AFMode)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
+}
+
+/**
+  * @brief  Disarm the break 2 input (when it operates in bidirectional mode).
+  * @note  The break 2 input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output.
+  * @rmtoll BDTR         BK2DSRM       LL_TIM_DisarmBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+/**
+  * @brief  Re-arm the break 2 input (when it operates in bidirectional mode).
+  * @note  The Break 2 input is automatically armed as soon as MOE bit is set.
+  * @rmtoll BDTR         BK2DSRM       LL_TIM_ReArmBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+/**
+  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
+  *         BDTR         OSSR          LL_TIM_SetOffStates
+  * @param  TIMx Timer instance
+  * @param  OffStateIdle This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSI_DISABLE
+  *         @arg @ref LL_TIM_OSSI_ENABLE
+  * @param  OffStateRun This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSR_DISABLE
+  *         @arg @ref LL_TIM_OSSR_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Disable automatic output (MOE can be set only by software).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Indicate whether automatic output is enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Indicates whether outputs are enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the signals connected to the designated timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP3E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP4E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP5E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP6E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP7E       LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2NE         LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP3E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP4E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP5E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP6E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP7E      LL_TIM_EnableBreakInputSource
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
+  *
+  *         (*)  Value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  SET_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Disable the signals connected to the designated timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP3E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP4E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP5E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP6E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP7E       LL_TIM_DisableBreakInputSource\n
+  *         AF2          BKINE         LL_TIM_DisableBreakInputSource\n
+  *         AF2          BKCMP1E       LL_TIM_DisableBreakInputSource\n
+  *         AF2          BKCMP2E       LL_TIM_DisableBreakInputSource\n
+  *         AF2          BKCMP3E       LL_TIM_DisableBreakInputSource\n
+  *         AF2          BKCMP4E       LL_TIM_DisableBreakInputSource\n
+  *         AF2          BKCMP5E       LL_TIM_DisableBreakInputSource\n
+  *         AF2          BKCMP6E       LL_TIM_DisableBreakInputSource\n
+  *         AF2          BKCMP7E       LL_TIM_DisableBreakInputSource
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
+  *
+  *         (*)  Value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  CLEAR_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Set the polarity of the break signal for the timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF1          BKCMP3P       LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF1          BKCMP4P       LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2CMP3P      LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2CMP4P      LL_TIM_SetBreakInputSourcePolarity
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
+  *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
+                                                        uint32_t Polarity)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
+}
+/**
+  * @brief  Enable asymmetrical deadtime.
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides asymmetrical deadtime.
+  * @rmtoll DTR2          DTAE          LL_TIM_EnableAsymmetricalDeadTime
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
+}
+
+/**
+  * @brief  Disable asymmetrical dead-time.
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides asymmetrical deadtime.
+  * @rmtoll DTR2          DTAE          LL_TIM_DisableAsymmetricalDeadTime
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
+}
+
+/**
+  * @brief  Indicates whether asymmetrical deadtime is activated.
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides asymmetrical deadtime.
+  * @rmtoll DTR2          DTAE          LL_TIM_IsEnabledAsymmetricalDeadTime
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
+  *         rising edge of OCxN signals).
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       asymmetrical dead-time insertion feature is supported by a timer instance.
+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+  * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
+  *       (LOCK bits in TIMx_BDTR register).
+  * @rmtoll DTR2         DTGF           LL_TIM_SetFallingDeadTime
+  * @param  TIMx Timer instance
+  * @param  DeadTime between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+  MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
+}
+
+/**
+  * @brief  Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
+  *         the rising edge of OCxN signals).
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       asymmetrical dead-time insertion feature is supported by a timer instance.
+  * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
+  *       (LOCK bits in TIMx_BDTR register).
+  * @rmtoll DTR2          DTGF           LL_TIM_GetFallingDeadTime
+  * @param  TIMx Timer instance
+  * @retval Returned value can be between Min_Data=0 and Max_Data=255:
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
+}
+
+/**
+  * @brief  Enable deadtime preload.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides deadtime preload.
+  * @rmtoll DTR2          DTPE          LL_TIM_EnableDeadTimePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
+}
+
+/**
+  * @brief  Disable dead-time preload.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides deadtime preload.
+  * @rmtoll DTR2          DTPE          LL_TIM_DisableDeadTimePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
+}
+
+/**
+  * @brief  Indicates whether deadtime preload is activated.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides deadtime preload.
+  * @rmtoll DTR2          DTPE          LL_TIM_IsEnabledDeadTimePreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+  * @{
+  */
+/**
+  * @brief  Configures the timer DMA burst feature.
+  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports the DMA burst mode.
+  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+  *         DCR          DBA           LL_TIM_ConfigDMABurst
+  * @param  TIMx Timer instance
+  * @param  DMABurstBaseAddress This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR
+  * @param  DMABurstLength This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Encoder Encoder configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable encoder index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR         IE           LL_TIM_EnableEncoderIndex
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->ECR, TIM_ECR_IE);
+}
+
+/**
+  * @brief  Disable encoder index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR         IE           LL_TIM_DisableEncoderIndex
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
+}
+
+/**
+  * @brief  Indicate whether encoder index is enabled.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR         IE           LL_TIM_IsEnabledEncoderIndex
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Set index direction
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IDIR           LL_TIM_SetIndexDirection
+  * @param  TIMx Timer instance
+  * @param  IndexDirection This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_UP
+  *         @arg @ref LL_TIM_INDEX_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
+}
+
+/**
+  * @brief  Get actual index direction
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IDIR           LL_TIM_GetIndexDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_UP
+  *         @arg @ref LL_TIM_INDEX_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
+}
+
+/**
+  * @brief  Enable first index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          FIDX          LL_TIM_EnableFirstIndex
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
+}
+
+/**
+  * @brief  Disable first index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          FIDX          LL_TIM_DisableFirstIndex
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
+}
+
+/**
+  * @brief  Indicates whether first index is enabled.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          FIDX          LL_TIM_IsEnabledFirstIndex
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set index positioning
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IPOS           LL_TIM_SetIndexPositionning
+  * @param  TIMx Timer instance
+  * @param  IndexPositionning This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP_UP
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
+}
+
+/**
+  * @brief  Get actual index positioning
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IPOS           LL_TIM_GetIndexPositionning
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP_UP
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
+}
+
+/**
+  * @brief  Configure encoder index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IDIR          LL_TIM_ConfigIDX\n
+  *         ECR          FIDX          LL_TIM_ConfigIDX\n
+  *         ECR          IPOS          LL_TIM_ConfigIDX
+  * @param  TIMx Timer instance
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+  * @{
+  */
+/**
+  * @brief  Remap TIM inputs (input channel, internal/external triggers).
+  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+  *       a some timer inputs can be remapped.
+  * @rmtoll TIM1_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM2_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM2_TISEL    TI2SEL      LL_TIM_SetRemap\n
+  *         TIM2_TISEL    TI3SEL      LL_TIM_SetRemap\n
+  *         TIM2_TISEL    TI4SEL      LL_TIM_SetRemap\n
+  *         TIM3_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM3_TISEL    TI2SEL      LL_TIM_SetRemap\n
+  *         TIM3_TISEL    TI3SEL      LL_TIM_SetRemap\n
+  *         TIM4_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM4_TISEL    TI2SEL      LL_TIM_SetRemap\n
+  *         TIM4_TISEL    TI3SEL      LL_TIM_SetRemap\n
+  *         TIM4_TISEL    TI4SEL      LL_TIM_SetRemap\n
+  *         TIM5_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM5_TISEL    TI2SEL      LL_TIM_SetRemap\n
+  *         TIM8_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM15_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM15_TISEL   TI2SEL      LL_TIM_SetRemap\n
+  *         TIM16_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM17_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM20_TISEL   TI1SEL      LL_TIM_SetRemap
+  * @param  TIMx Timer instance
+  * @param  Remap Remap param depends on the TIMx. Description available only
+  *         in CHM version of the User Manual (not in .pdf).
+  *         Otherwise see Reference Manual description of TISEL registers.
+  *
+  *         Below description summarizes "Timer Instance" and "Remap" param combinations:
+  *
+  *         TIM1: one of the following values
+  *
+  *            @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP3
+  *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP4
+  *
+  *         TIM2: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM2_TI1_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM2_TI1_RMP_COMP3
+  *            @arg @ref LL_TIM_TIM2_TI1_RMP_COMP4
+  *            @arg @ref LL_TIM_TIM2_TI1_RMP_COMP5 (*)
+  *
+  *            . . TI2_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM2_TI2_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM2_TI2_RMP_COMP3
+  *            @arg @ref LL_TIM_TIM2_TI2_RMP_COMP4
+  *            @arg @ref LL_TIM_TIM2_TI2_RMP_COMP6 (*)
+  *
+  *            . . TI3_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM2_TI3_RMP_COMP4
+  *
+  *            . . TI4_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
+  *
+  *         TIM3: any combination of TI1_RMP and TI2_RMP where
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP3
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP4
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP5 (*)
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP6 (*)
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP7 (*)
+  *
+  *            . . TI2_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP3
+  *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP4
+  *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP5 (*)
+  *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP6 (*)
+  *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP7 (*)
+  *
+  *            . . TI3_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3
+  *
+  *         TIM4: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP3
+  *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP4
+  *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP5 (*)
+  *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP6 (*)
+  *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP7 (*)
+  *
+  *            . . TI2_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP3
+  *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP4
+  *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP5 (*)
+  *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP6 (*)
+  *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP7 (*)
+  *
+  *            . . TI3_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM4_TI3_RMP_COMP5 (*)
+  *
+  *            . . TI4_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM4_TI4_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM4_TI4_RMP_COMP6 (*)
+  *
+  *         TIM5: any combination of TI1_RMP and TI2_RMP where (**)
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_GPIO   (*)
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_LSI    (*)
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_LSE    (*)
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_RTC_WK (*)
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP1  (*)
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP2  (*)
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP3  (*)
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP4  (*)
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP5  (*)
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP6  (*)
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP7  (*)
+  *
+  *            . . TI2_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM5_TI2_RMP_GPIO  (*)
+  *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP1 (*)
+  *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP2 (*)
+  *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP3 (*)
+  *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP4 (*)
+  *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP5 (*)
+  *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP6 (*)
+  *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP7 (*)
+  *
+  *         TIM8: one of the following values
+  *
+  *            @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM8_TI1_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM8_TI1_RMP_COMP3
+  *            @arg @ref LL_TIM_TIM8_TI1_RMP_COMP4
+  *
+  *         TIM15: any combination of TI1_RMP and TI2_RMP where
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_COMP5 (*)
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_COMP7 (*)
+  *
+  *            . . TI2_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM15_TI2_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM15_TI2_RMP_COMP3
+  *            @arg @ref LL_TIM_TIM15_TI2_RMP_COMP6 (*)
+  *            @arg @ref LL_TIM_TIM15_TI2_RMP_COMP7 (*)
+  *
+  *         TIM16: one of the following values
+  *
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_COMP6 (*)
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
+  *
+  *         TIM17: one of the following values
+  *
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_COMP5 (*)
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_RTC_WK
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_LSE
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_LSI
+  *
+  *         TIM20: one of the following values (**)
+  *
+  *            @arg @ref LL_TIM_TIM20_TI1_RMP_GPIO  (*)
+  *            @arg @ref LL_TIM_TIM20_TI1_RMP_COMP1 (*)
+  *            @arg @ref LL_TIM_TIM20_TI1_RMP_COMP2 (*)
+  *            @arg @ref LL_TIM_TIM20_TI1_RMP_COMP3 (*)
+  *            @arg @ref LL_TIM_TIM20_TI1_RMP_COMP4 (*)
+  *
+  *         (*)  Value not defined in all devices. \n
+  *         (**) Register not available in all devices.
+  *
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+  MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
+}
+
+/**
+  * @brief  Enable request for HSE/32 clock used for TISEL remap.
+  * @note Only TIM16 and TIM17 support HSE/32 remap
+  * @rmtoll OR         HSE32EN           LL_TIM_EnableHSE32
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->OR, TIM_OR_HSE32EN);
+}
+
+/**
+  * @brief  Disable request for HSE/32 clock used for TISEL remap.
+  * @note Only TIM16 and TIM17 support HSE/32 remap
+  * @rmtoll OR         HSE32EN           LL_TIM_DisableHSE32
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->OR, TIM_OR_HSE32EN);
+}
+
+/**
+  * @brief  Indicate whether request for HSE/32 clock is enabled.
+  * @note Only TIM16 and TIM17 support HSE/32 remap
+  * @rmtoll OR         HSE32EN           LL_TIM_IsEnabledHSE32
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
+  * @{
+  */
+/**
+  * @brief  Set the OCREF clear input source
+  * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
+  * @note This function can only be used in Output compare and PWM modes.
+  * @note Macro IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can configure OCREF clear input source.
+  * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
+  * @rmtoll AF2           OCRSEL              LL_TIM_SetOCRefClearInputSource
+  * @param  TIMx Timer instance
+  * @param  OCRefClearInputSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_ETR
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP3
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP4
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP5 (*)
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP6 (*)
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP7 (*)
+  *
+  *         (*)  Value not defined in all devices. \n
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
+             ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos);
+  MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+  * @{
+  */
+/**
+  * @brief  Clear the update interrupt flag (UIF).
+  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
+  * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
+  * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
+  * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
+  * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the commutation interrupt flag (COMIF).
+  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the trigger interrupt flag (TIF).
+  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break interrupt flag (BIF).
+  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break 2 interrupt flag (B2IF).
+  * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+}
+
+/**
+  * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+  * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+  *         (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+  *         (Capture/Compare 2 over-capture interrupt is pending).
+  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+  *         (Capture/Compare 3 over-capture interrupt is pending).
+  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+  *         (Capture/Compare 4 over-capture interrupt is pending).
+  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the system break interrupt flag (SBIF).
+  * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
+}
+
+/**
+  * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
+  * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the transition error interrupt flag (TERRF).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll SR           TERRF           LL_TIM_ClearFlag_TERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
+}
+
+/**
+  * @brief  Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll SR           TERRF           LL_TIM_IsActiveFlag_TERR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the index error interrupt flag (IERRF).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll SR           IERRF           LL_TIM_ClearFlag_IERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
+}
+
+/**
+  * @brief  Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll SR           IERRF           LL_TIM_IsActiveFlag_IERR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the direction change interrupt flag (DIRF).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll SR           DIRF           LL_TIM_ClearFlag_DIR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
+}
+
+/**
+  * @brief  Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll SR           DIRF           LL_TIM_IsActiveFlag_DIR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the index interrupt flag (IDXF).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll SR           IDXF           LL_TIM_ClearFlag_IDX
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
+}
+
+/**
+  * @brief  Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll SR           IDXF           LL_TIM_IsActiveFlag_IDX
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+  * @{
+  */
+/**
+  * @brief  Enable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Disable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Indicates whether the update interrupt (UIE) is enabled.
+  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Disable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
+  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
+  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Disable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Indicates whether the break interrupt (BIE) is enabled.
+  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable transition error interrupt (TERRIE).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         TERRIE           LL_TIM_EnableIT_TERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
+}
+
+/**
+  * @brief  Disable transition error interrupt (TERRIE).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         TERRIE           LL_TIM_DisableIT_TERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
+}
+
+/**
+  * @brief  Indicates whether the transition error interrupt (TERRIE) is enabled.
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         TERRIE           LL_TIM_IsEnabledIT_TERR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable index error interrupt (IERRIE).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         IERRIE           LL_TIM_EnableIT_IERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
+}
+
+/**
+  * @brief  Disable index error interrupt (IERRIE).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         IERRIE           LL_TIM_DisableIT_IERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
+}
+
+/**
+  * @brief  Indicates whether the index error interrupt (IERRIE) is enabled.
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         IERRIE           LL_TIM_IsEnabledIT_IERR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable direction change interrupt (DIRIE).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         DIRIE           LL_TIM_EnableIT_DIR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
+}
+
+/**
+  * @brief  Disable direction change interrupt (DIRIE).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         DIRIE           LL_TIM_DisableIT_DIR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
+}
+
+/**
+  * @brief  Indicates whether the direction change interrupt (DIRIE) is enabled.
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         DIRIE           LL_TIM_IsEnabledIT_DIR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable index interrupt (IDXIE).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         IDXIE           LL_TIM_EnableIT_IDX
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
+}
+
+/**
+  * @brief  Disable index interrupt (IDXIE).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         IDXIE           LL_TIM_DisableIT_IDX
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
+}
+
+/**
+  * @brief  Indicates whether the index interrupt (IDXIE) is enabled.
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         IDXIE           LL_TIM_IsEnabledIT_IDX
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+/**
+  * @brief  Enable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Disable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
+  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Disable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
+  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
+  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+  * @{
+  */
+/**
+  * @brief  Generate an update event.
+  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+  * @brief  Generate Capture/Compare 1 event.
+  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 2 event.
+  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 3 event.
+  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 4 event.
+  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+  * @brief  Generate commutation event.
+  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+  * @brief  Generate trigger event.
+  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+  * @brief  Generate break event.
+  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+  * @brief  Generate break 2 event.
+  * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_B2G);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_LL_TIM_H */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h
new file mode 100644
index 0000000..f15e11e
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h
@@ -0,0 +1,4401 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_USART_H
+#define STM32G4xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @defgroup USART_LL USART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Variables USART Private Variables
+  * @{
+  */
+/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
+static const uint32_t USART_PRESCALER_TAB[] =
+{
+  1UL,
+  2UL,
+  4UL,
+  6UL,
+  8UL,
+  10UL,
+  12UL,
+  16UL,
+  32UL,
+  64UL,
+  128UL,
+  256UL
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
+                                           This parameter can be a value of @ref USART_LL_EC_PRESCALER.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetPrescaler().*/
+
+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetHWFlowCtrl().*/
+
+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+  * @brief LL USART Clock Init Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+                                           USART HW configuration can be modified afterwards using unitary functions
+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetClockPolarity().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetClockPhase().
+                                           For more details, refer to description of this function. */
+
+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetLastClkPulseOutput().
+                                           For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_WriteReg function
+  * @{
+  */
+#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error clear flag */
+#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error clear flag */
+#define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected clear flag */
+#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error clear flag */
+#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected clear flag */
+#define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty clear flag */
+#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete clear flag */
+#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time clear flag */
+#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection clear flag */
+#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag */
+#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout clear flag */
+#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block clear flag */
+#define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun clear flag */
+#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match clear flag */
+#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_ReadReg function
+  * @{
+  */
+#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
+#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
+#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
+#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
+#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
+#define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
+#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
+#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
+#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
+#define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
+#define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
+#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
+#define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
+#define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+  * @{
+  */
+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
+#define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
+#define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
+#define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
+#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
+#define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+  * @{
+  */
+#define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+  * @{
+  */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+  * @{
+  */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+  * @{
+  */
+
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+  * @{
+  */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
+  * @{
+  */
+#define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not divided   */
+#define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock divided by 2  */
+#define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock divided by 4  */
+#define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 6  */
+#define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock divided by 8  */
+#define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 10 */
+#define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 12 */
+#define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock divided by 32 */
+#define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 64 */
+#define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 128 */
+#define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+  * @{
+  */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+  * @{
+  */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+  * @{
+  */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+  */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+  (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+  */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+  ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  USART Enable
+  * @rmtoll CR1          UE            LL_USART_Enable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  USART Disable (all USART prescalers and outputs are disabled)
+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the USART is kept, but all the status
+  *         flags, in the USARTx_ISR are set to their default values.
+  * @rmtoll CR1          UE            LL_USART_Disable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if USART is enabled
+  * @rmtoll CR1          UE            LL_USART_IsEnabled
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  FIFO Mode Enable
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  FIFO Mode Disable
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  Indicate if FIFO Mode is enabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure TX FIFO Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return TX FIFO Threshold Configuration
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure RX FIFO Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return RX FIFO Threshold Configuration
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure TX and RX FIFOs Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
+  *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
+  * @param  USARTx USART Instance
+  * @param  TXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @param  RXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+  * @brief  USART enabled in STOP Mode.
+  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+  *         USART clock selection is HSI or LSE in RCC.
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  USART disabled in STOP Mode.
+  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+  *         CR1          TE            LL_USART_SetTransferDirection
+  * @param  USARTx USART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+  *         CR1          TE            LL_USART_GetTransferDirection
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_USART_SetParity\n
+  *         CR1          PCE           LL_USART_SetParity
+  * @param  USARTx USART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_USART_GetParity\n
+  *         CR1          PCE           LL_USART_GetParity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+  *         CR1          M1            LL_USART_SetDataWidth
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+  *         CR1          M1            LL_USART_GetDataWidth
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Oversampling to 8-bit or 16-bit mode
+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+  * @param  USARTx USART Instance
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+  * @brief  Return Oversampling mode
+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @param  LastBitClockPulse This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+  * @brief  Retrieve Clock pulse of the last data bit output configuration
+  *         (Last bit Clock pulse output to the SCLK pin or not)
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+  * @param  USARTx USART Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+  * @param  USARTx USART Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+  *         CR2          CPOL          LL_USART_ConfigClock\n
+  *         CR2          LBCL          LL_USART_ConfigClock
+  * @param  USARTx USART Instance
+  * @param  Phase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @param  LBCPOutput This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+  * @brief  Enable Clock output on SCLK pin
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Disable Clock output on SCLK pin
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Indicate if Clock output on SCLK pin is enabled
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+  * @param  USARTx USART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+  *         CR1          PCE           LL_USART_ConfigCharacter\n
+  *         CR1          M0            LL_USART_ConfigCharacter\n
+  *         CR1          M1            LL_USART_ConfigCharacter\n
+  *         CR2          STOP          LL_USART_ConfigCharacter
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+                                              uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+  * @param  USARTx USART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Enable Auto Baud-Rate Detection
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Disable Auto Baud-Rate Detection
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Auto Baud-Rate mode bits
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @param  AutoBaudRateMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+  * @brief  Return Auto Baud-Rate mode
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+  * @brief  Enable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Disable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Indicate if Receiver Timeout feature is enabled
+  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Address of the USART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+  * @param  USARTx USART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the USART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+  * @param  USARTx USART Instance
+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Disable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Indicate if One bit sampling method is enabled
+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+  * @param  USARTx USART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+  *         (Baud rate value != 0)
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                          uint32_t OverSampling,
+                                          uint32_t BaudRate)
+{
+  uint32_t usartdiv;
+  uint32_t brrtemp;
+
+  if (PrescalerValue > LL_USART_PRESCALER_DIV256)
+  {
+    /* Do not overstep the size of USART_PRESCALER_TAB */
+  }
+  else if (BaudRate == 0U)
+  {
+    /* Can Not divide per 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+    brrtemp = usartdiv & 0xFFF0U;
+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+    USARTx->BRR = brrtemp;
+  }
+  else
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                              uint32_t OverSampling)
+{
+  uint32_t usartdiv;
+  uint32_t brrresult = 0x0U;
+  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
+
+  usartdiv = USARTx->BRR;
+
+  if (usartdiv == 0U)
+  {
+    /* Do not perform a division by 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+    if (usartdiv != 0U)
+    {
+      brrresult = (periphclkpresc * 2U) / usartdiv;
+    }
+  }
+  else
+  {
+    if ((usartdiv & 0xFFFFU) != 0U)
+    {
+      brrresult = periphclkpresc / usartdiv;
+    }
+  }
+  return (brrresult);
+}
+
+/**
+  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
+  * @param  USARTx USART Instance
+  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+  * @brief  Set Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
+  * @param  USARTx USART Instance
+  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @brief  Get Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+  * @{
+  */
+
+/**
+  * @brief  Enable IrDA mode
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_EnableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Disable IrDA mode
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_DisableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Indicate if IrDA mode is enabled
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure IrDA Power Mode (Normal or Low Power)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_IRDA_POWER_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+  * @brief  Set Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Smartcard NACK transmission
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Disable Smartcard NACK transmission
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Indicate if Smartcard NACK transmission is enabled
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Smartcard mode
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Disable Smartcard mode
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Indicate if Smartcard mode is enabled
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+  *         In transmission mode, it specifies the number of automatic retransmission retries, before
+  *         generating a transmission error (FE bit set).
+  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
+  *         reception error (RXNE and PE bits set)
+  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+}
+
+/**
+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
+  * @{
+  */
+/**
+  * @brief  Enable SPI Synchronous Slave mode
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Disable SPI Synchronous Slave mode
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Indicate if  SPI Synchronous Slave mode is enabled
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SPI Slave Selection using NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave Selection depends on NSS input pin
+  *         (The slave is selected when NSS is low and deselected when NSS is high).
+  * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Disable SPI Slave Selection using NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave will be always selected and NSS input pin will be ignored.
+  * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+  * @{
+  */
+
+/**
+  * @brief  Set LIN Break Detection Length
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @param  LINBDLength This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+  * @brief  Return LIN Break Detection Length
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+  * @brief  Enable LIN mode
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Disable LIN mode
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Indicate if LIN mode is enabled
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+  * @{
+  */
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+  * @note   In UART mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Asynchronous Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+  /* In Asynchronous mode, the following bits must be kept cleared:
+  - LINEN, CLKEN bits in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+  * @note   In Synchronous mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the USART in Synchronous mode.
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  * @note   Other remaining configurations items related to Synchronous Mode
+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+  *         CR3          IREN          LL_USART_ConfigSyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+  /* set the UART/USART in Synchronous mode */
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+  * @note   In LIN mode, the following bits must be kept cleared:
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also set the UART/USART in LIN mode.
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+  * @note   Other remaining configurations items related to LIN Mode
+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+  *         CR2          STOP          LL_USART_ConfigLINMode\n
+  *         CR2          LINEN         LL_USART_ConfigLINMode\n
+  *         CR3          IREN          LL_USART_ConfigLINMode\n
+  *         CR3          SCEN          LL_USART_ConfigLINMode\n
+  *         CR3          HDSEL         LL_USART_ConfigLINMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+  /* In LIN mode, the following bits must be kept cleared:
+  - STOP and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* Set the UART/USART in LIN mode */
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+  * @note   In Half Duplex mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *         This function also sets the UART/USART in Half Duplex mode.
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+  * @note   Other remaining configurations items related to Half Duplex Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+  /* In Half Duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+  /* set the UART/USART in Half Duplex mode */
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+  * @note   In Smartcard mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also configures Stop bits to 1.5 bits and
+  *         sets the USART in Smartcard mode (SCEN bit).
+  *         Clock Output is also enabled (CLKEN).
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+  * @note   Other remaining configurations items related to Smartcard Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+  /* In Smartcard mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+  /* Configure Stop bits to 1.5 bits */
+  /* Synchronous mode is activated by default */
+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+  /* set the UART/USART in Smartcard mode */
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+  * @note   In IRDA mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the UART/USART in IRDA mode (IREN bit).
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+  * @note   Other remaining configurations items related to Irda Mode
+  *         (as Baud Rate, Word length, Power mode, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+  *         CR3          IREN          LL_USART_ConfigIrdaMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* set the UART/USART in IRDA mode */
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+  *         (several USARTs connected in a network, one of the USARTs can be the master,
+  *         its TX output connected to the RX inputs of the other slaves USARTs).
+  * @note   In MultiProcessor mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Multi processor Mode
+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+  /* In Multi Processor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the USART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE
+
+/**
+  * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF
+
+/**
+  * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Flag is set or not
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS interrupt Flag is set or not
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Flag is set or not
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Time Out Flag is set or not
+  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Flag is set or not
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the SPI Slave Underrun error flag is set or not
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Threshold Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Threshold Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise Error detected Flag
+  * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear TX FIFO Empty Flag
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
+  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+
+/**
+  * @brief  Clear LIN Break Detection Flag
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Receiver Time Out Flag
+  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+  * @brief  Clear End Of Block Flag
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+  * @brief  Clear SPI Slave Underrun Flag
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE
+
+/**
+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF
+
+/**
+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Enable End Of Block Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Enable LIN Break Detection Interrupt
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE
+
+/**
+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF
+
+/**
+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Disable End Of Block Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Disable LIN Break Detection Interrupt
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE
+
+/**
+  * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF
+
+/**
+  * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
+  * @param  USARTx USART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(USARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(USARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData8
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+  USARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData9
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request an Automatic Baud Rate measurement on next received data frame
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
+}
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put USART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data and FIFO flush
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @brief  Request a Transmit data and FIFO flush
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_USART_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h
new file mode 100644
index 0000000..1675cc6
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h
@@ -0,0 +1,239 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_usb.h
+  * @author  MCD Application Team
+  * @brief   Header file of USB Low Layer HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_USB_H
+#define STM32G4xx_LL_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+#if defined (USB)
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USB_LL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  USB Mode definition
+  */
+
+
+
+typedef enum
+{
+  USB_DEVICE_MODE  = 0
+} USB_ModeTypeDef;
+
+/**
+  * @brief  USB Initialization Structure definition
+  */
+typedef struct
+{
+  uint32_t dev_endpoints;           /*!< Device Endpoints number.
+                                         This parameter depends on the used USB core.
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+  uint32_t speed;                   /*!< USB Core speed.
+                                         This parameter can be any value of @ref PCD_Speed/HCD_Speed
+                                                                                 (HCD_SPEED_xxx, HCD_SPEED_xxx) */
+
+  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */
+
+  uint32_t phy_itface;              /*!< Select the used PHY interface.
+                                         This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module  */
+
+  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */
+
+  uint32_t low_power_enable;        /*!< Enable or disable Low Power mode                                       */
+
+  uint32_t lpm_enable;              /*!< Enable or disable Battery charging.                                    */
+
+  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */
+} USB_CfgTypeDef;
+
+typedef struct
+{
+  uint8_t   num;             /*!< Endpoint number
+                                  This parameter must be a number between Min_Data = 1 and Max_Data = 15    */
+
+  uint8_t   is_in;           /*!< Endpoint direction
+                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
+
+  uint8_t   is_stall;        /*!< Endpoint stall condition
+                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
+
+  uint8_t   type;            /*!< Endpoint type
+                                  This parameter can be any value of @ref USB_EP_Type                       */
+
+  uint8_t   data_pid_start;  /*!< Initial data PID
+                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
+
+  uint16_t  pmaadress;       /*!< PMA Address
+                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */
+
+  uint16_t  pmaaddr0;        /*!< PMA Address0
+                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */
+
+  uint16_t  pmaaddr1;        /*!< PMA Address1
+                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */
+
+  uint8_t   doublebuffer;    /*!< Double buffer enable
+                                  This parameter can be 0 or 1                                              */
+
+  uint16_t  tx_fifo_num;     /*!< This parameter is not required by USB Device FS peripheral, it is used
+                                  only by USB OTG FS peripheral
+                                  This parameter is added to ensure compatibility across USB peripherals    */
+
+  uint32_t  maxpacket;       /*!< Endpoint Max packet size
+                                  This parameter must be a number between Min_Data = 0 and Max_Data = 64KB  */
+
+  uint8_t   *xfer_buff;      /*!< Pointer to transfer buffer                                                */
+
+  uint32_t  xfer_len;        /*!< Current transfer length                                                   */
+
+  uint32_t  xfer_count;      /*!< Partial transfer length in case of multi packet transfer                  */
+
+  uint32_t  xfer_len_db;      /*!< double buffer transfer length used with bulk double buffer in           */
+
+  uint8_t   xfer_fill_db;     /*!< double buffer Need to Fill new buffer  used with bulk_in                */
+
+} USB_EPTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
+  * @{
+  */
+#define EP_MPS_64                              0U
+#define EP_MPS_32                              1U
+#define EP_MPS_16                              2U
+#define EP_MPS_8                               3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
+  * @{
+  */
+#define EP_TYPE_CTRL                           0U
+#define EP_TYPE_ISOC                           1U
+#define EP_TYPE_BULK                           2U
+#define EP_TYPE_INTR                           3U
+#define EP_TYPE_MSK                            3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL Device Speed
+  * @{
+  */
+#define USBD_FS_SPEED                          2U
+/**
+  * @}
+  */
+
+#define BTABLE_ADDRESS                         0x000U
+#define PMA_ACCESS                             1U
+
+#define EP_ADDR_MSK                            0x7U
+
+#ifndef USE_USB_DOUBLE_BUFFER
+#define USE_USB_DOUBLE_BUFFER                  1U
+#endif /* USE_USB_DOUBLE_BUFFER */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+  * @{
+  */
+
+
+HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
+
+#if defined (HAL_PCD_MODULE_ENABLED)
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+#endif /* defined (HAL_PCD_MODULE_ENABLED) */
+
+HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
+uint32_t          USB_ReadInterrupts(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
+
+void              USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
+                               uint16_t wPMABufAddr, uint16_t wNBytes);
+
+void              USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
+                              uint16_t wPMABufAddr, uint16_t wNBytes);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* STM32G4xx_LL_USB_H */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h
new file mode 100644
index 0000000..6a12eb7
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h
@@ -0,0 +1,317 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_utils.h
+  * @author  MCD Application Team
+  * @brief   Header file of UTILS LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL UTILS driver contains a set of generic APIs that can be
+    used by user:
+      (+) Device electronic signature
+      (+) Timing functions
+      (+) PLL configuration functions
+
+  @endverbatim
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_UTILS_H
+#define STM32G4xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup UTILS_LL UTILS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+  * @{
+  */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY                  0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS              UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+  * @{
+  */
+/**
+  * @brief  UTILS PLL structure definition
+  */
+typedef struct
+{
+  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
+                        This parameter must be a number between Min_Data = 8 and Max_Data = 86
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+  uint32_t PLLR;   /*!< Division for the main system clock.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAHBPrescaler(). */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB1Prescaler(). */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+  * @{
+  */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+  * @{
+  */
+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+  * @{
+  */
+#define LL_UTILS_PACKAGETYPE_LQFP64         0x00000000U /*!< LQFP64 package type                      */
+#define LL_UTILS_PACKAGETYPE_LQFP100        0x00000002U /*!< LQFP100 package type                     */
+#define LL_UTILS_PACKAGETYPE_WLCSP81        0x00000005U /*!< WLCSP81 package type                     */
+#define LL_UTILS_PACKAGETYPE_LQFP128        0x00000007U /*!< LQFP128 package type                     */
+#define LL_UTILS_PACKAGETYPE_UFQFPN32       0x00000008U /*!< UFQFPN32 package type                    */
+#define LL_UTILS_PACKAGETYPE_LQFP32         0x00000009U /*!< LQFP32 package type                      */
+#define LL_UTILS_PACKAGETYPE_UFQFPN48       0x0000000AU /*!< UFQFPN48 package type                    */
+#define LL_UTILS_PACKAGETYPE_LQFP48         0x0000000BU /*!< LQFP48 package type                      */
+#define LL_UTILS_PACKAGETYPE_WLCSP49        0x0000000CU /*!< WLCSP49 package type                     */
+#define LL_UTILS_PACKAGETYPE_UFBGA64        0x0000000DU /*!< UFBGA64 package type                     */
+#define LL_UTILS_PACKAGETYPE_UFBGA100       0x0000000EU /*!< UFBGA100 package type                    */
+#define LL_UTILS_PACKAGETYPE_LQFP48_EBIKE   0x00000010U /*!< LQFP48 EBIKE package type                */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+  * @{
+  */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+  * @{
+  */
+
+/**
+  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+  * @brief  Get Flash memory size
+  * @note   This bitfield indicates the size of the device Flash memory expressed in
+  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+  * @retval FLASH_SIZE[15:0]: Flash memory size
+  */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
+}
+
+/**
+  * @brief  Get Package type
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP64
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP81
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP128
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP32
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP48
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_EBIKE
+  *
+*/
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source of the time base.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  Ticks Number of ticks
+  * @retval None
+  */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+  /* Configure the SysTick to have interrupt in 1ms time base */
+  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
+  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
+}
+
+void        LL_Init1msTick(uint32_t HCLKFrequency);
+void        LL_mDelay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+  * @{
+  */
+
+void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_UTILS_H */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/LICENSE.txt b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/LICENSE.txt
new file mode 100644
index 0000000..b40364c
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/LICENSE.txt
@@ -0,0 +1,6 @@
+This software component is provided to you as part of a software package and
+applicable license terms are in the  Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the BSD-3-Clause license shall apply. 
+You may obtain a copy of the BSD-3-Clause at:
+https://opensource.org/licenses/BSD-3-Clause
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c
new file mode 100644
index 0000000..3d9e92f
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c
@@ -0,0 +1,772 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal.c
+  * @author  MCD Application Team
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL.
+    [..]
+    The HAL contains two APIs' categories:
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL HAL
+  * @brief HAL module driver
+  * @{
+  */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/**
+  * @brief STM32G4xx HAL Driver version number V1.2.2
+  */
+#define __STM32G4xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32G4xx_HAL_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
+#define __STM32G4xx_HAL_VERSION_SUB2   (0x02U) /*!< [15:8]  sub2 version */
+#define __STM32G4xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32G4xx_HAL_VERSION         ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\
+                                         |(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\
+                                         |(__STM32G4xx_HAL_VERSION_SUB2 << 8U )\
+                                         |(__STM32G4xx_HAL_VERSION_RC))
+
+#if defined(VREFBUF)
+#define VREFBUF_TIMEOUT_VALUE     10U   /* 10 ms */
+#endif /* VREFBUF */
+
+/* ------------ SYSCFG registers bit address in the alias region ------------ */
+#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
+/* ---  MEMRMP Register ---*/
+/* Alias word address of FB_MODE bit */
+#define MEMRMP_OFFSET           SYSCFG_OFFSET
+#define FB_MODE_BitNumber       ((uint8_t)0x8)
+#define FB_MODE_BB              (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
+
+/* --- GPC Register ---*/
+/* Alias word address of CCMER bit */
+#define SCSR_OFFSET             (SYSCFG_OFFSET + 0x18)
+#define CCMER_BitNumber         ((uint8_t)0x0)
+#define SCSR_CCMER_BB           (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (CCMER_BitNumber * 4))
+
+/* Private macro -------------------------------------------------------------*/
+/* Exported variables ---------------------------------------------------------*/
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+  * @{
+  */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+  *  @brief    HAL Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the Flash interface the NVIC allocation and initial time base
+          clock configuration.
+      (+) De-Initialize common part of the HAL.
+      (+) Configure the time base source to have 1ms time base with a dedicated
+          Tick interrupt priority.
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose
+             timer for example or other time source), keeping in mind that Time base
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically
+             at the beginning of the program after reset by HAL_Init() or at any time
+             when clock is configured, by HAL_RCC_ClockConfig().
+        (++) Source of time base is configured  to generate interrupts at regular
+             time intervals. Care must be taken if HAL_Delay() is called from a
+             peripheral ISR process, the Tick interrupt line must have higher priority
+            (numerically lower) than the peripheral interrupt. Otherwise the caller
+            ISR process will be blocked.
+       (++) functions affecting time base configurations are declared as __weak
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function is used to configure the Flash prefetch, the Instruction and Data caches,
+  *         the time base source, NVIC and any required global low level hardware
+  *         by calling the HAL_MspInit() callback function to be optionally defined in user file
+  *         stm32g4xx_hal_msp.c.
+  *
+  * @note   HAL_Init() function is called at the beginning of program after reset and before
+  *         the clock configuration.
+  *
+  * @note   In the default implementation the System Timer (Systick) is used as source of time base.
+  *         The Systick configuration is based on HSI clock, as HSI is the clock
+  *         used after a system Reset and the NVIC configuration is set to Priority group 4.
+  *         Once done, time base tick starts incrementing: the tick variable counter is incremented
+  *         each 1ms in the SysTick_Handler() interrupt handler.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+  HAL_StatusTypeDef  status = HAL_OK;
+  /* Configure Flash prefetch, Instruction cache, Data cache */
+  /* Default configuration at reset is:                      */
+  /* - Prefetch disabled                                     */
+  /* - Instruction cache enabled                             */
+  /* - Data cache enabled                                    */
+#if (INSTRUCTION_CACHE_ENABLE == 0U)
+  __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+#endif /* INSTRUCTION_CACHE_ENABLE */
+
+#if (DATA_CACHE_ENABLE == 0U)
+  __HAL_FLASH_DATA_CACHE_DISABLE();
+#endif /* DATA_CACHE_ENABLE */
+
+#if (PREFETCH_ENABLE != 0U)
+  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Init the low level hardware */
+    HAL_MspInit();
+  }
+
+  /* Return function status */
+  return status;
+
+}
+
+/**
+  * @brief  This function de-initializes common part of the HAL and stops the source of time base.
+  * @note   This function is optional.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __HAL_RCC_APB1_FORCE_RESET();
+  __HAL_RCC_APB1_RELEASE_RESET();
+
+  __HAL_RCC_APB2_FORCE_RESET();
+  __HAL_RCC_APB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB1_FORCE_RESET();
+  __HAL_RCC_AHB1_RELEASE_RESET();
+
+  __HAL_RCC_AHB2_FORCE_RESET();
+  __HAL_RCC_AHB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB3_FORCE_RESET();
+  __HAL_RCC_AHB3_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the MSP.
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief This function configures the source of the time base:
+  *        The time source is configured to have 1ms time base with a dedicated
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals.
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+  *       The SysTick interrupt must have higher priority (numerically lower)
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  HAL_StatusTypeDef  status = HAL_OK;
+
+  if (uwTickFreq != 0U)
+  {
+    /* Configure the SysTick to have interrupt in 1ms time basis*/
+    if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
+    {
+      /* Configure the SysTick IRQ priority */
+      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+      {
+        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+        uwTickPrio = TickPriority;
+      }
+      else
+      {
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+  *  @brief    HAL Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in SysTick ISR.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick += uwTickFreq;
+}
+
+/**
+  * @brief Provides a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief This function returns a tick priority.
+  * @retval tick priority
+  */
+uint32_t HAL_GetTickPrio(void)
+{
+  return uwTickPrio;
+}
+
+/**
+  * @brief Set new tick Freq.
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
+{
+  HAL_StatusTypeDef status  = HAL_OK;
+  uint32_t prevTickFreq;
+
+  assert_param(IS_TICKFREQ(Freq));
+
+  if (uwTickFreq != Freq)
+  {
+    /* Back up uwTickFreq frequency */
+    prevTickFreq = uwTickFreq;
+
+    /* Update uwTickFreq global variable used by HAL_InitTick() */
+    uwTickFreq = Freq;
+
+    /* Apply the new tick Freq  */
+    status = HAL_InitTick(uwTickPrio);
+
+    if (status != HAL_OK)
+    {
+      /* Restore previous tick frequency */
+      uwTickFreq = prevTickFreq;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Returns tick frequency.
+  * @retval tick period in Hz
+  */
+uint32_t HAL_GetTickFreq(void)
+{
+  return uwTickFreq;
+}
+
+/**
+  * @brief This function provides minimum delay (in milliseconds) based
+  *        on variable incremented.
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += (uint32_t)(uwTickFreq);
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+  }
+}
+
+/**
+  * @brief Suspends Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the SysTick interrupt will be disabled and so Tick increment
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the SysTick interrupt will be enabled and so Tick increment
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Returns the HAL revision.
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+  return __STM32G4xx_HAL_VERSION;
+}
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+  return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16U);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+  return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
+  *  @brief    HAL Debug functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### HAL Debug functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode.
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode.
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP0/STOP1/STOP2 modes.
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP0/STOP1/STOP2 modes.
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode.
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode.
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
+  *  @brief    HAL SYSCFG configuration functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### HAL SYSCFG configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start a hardware CCMSRAM erase operation
+      (+) Enable/Disable the Internal FLASH Bank Swapping
+      (+) Configure the Voltage reference buffer
+      (+) Enable/Disable the Voltage reference buffer
+      (+) Enable/Disable the I/O analog switch voltage booster
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start a hardware CCMSRAM erase operation.
+  * @note   As long as CCMSRAM is not erased the CCMER bit will be set.
+  *         This bit is automatically reset at the end of the CCMSRAM erase operation.
+  * @retval None
+  */
+void HAL_SYSCFG_CCMSRAMErase(void)
+{
+  /* unlock the write protection of the CCMER bit */
+  SYSCFG->SKR = 0xCA;
+  SYSCFG->SKR = 0x53;
+  /* Starts a hardware CCMSRAM erase operation*/
+  SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
+}
+
+/**
+  * @brief  Enable the Internal FLASH Bank Swapping.
+  *
+  * @note   This function can be used only for STM32G4xx devices.
+  *
+  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
+  *         and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00040000)
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_EnableMemorySwappingBank(void)
+{
+  SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE);
+}
+
+/**
+  * @brief  Disable the Internal FLASH Bank Swapping.
+  *
+  * @note   This function can be used only for STM32G4xx devices.
+  *
+  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
+  *         and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00040000)
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableMemorySwappingBank(void)
+{
+  CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE);
+}
+
+#if defined(VREFBUF)
+/**
+  * @brief Configure the internal voltage reference buffer voltage scale.
+  * @param  VoltageScaling: specifies the output voltage to achieve
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREFBUF_OUT around 2.048 V.
+  *                                                This requires VDDA equal to or higher than 2.4 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREFBUF_OUT around 2.5 V.
+  *                                                This requires VDDA equal to or higher than 2.8 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREFBUF_OUT around 2.9 V.
+  *                                                This requires VDDA equal to or higher than 3.15 V.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+}
+
+/**
+  * @brief Configure the internal voltage reference buffer high impedance mode.
+  * @param  Mode: specifies the high impedance mode
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+}
+
+/**
+  * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
+  * @param TrimmingValue specifies trimming code for VREFBUF calibration
+  *        This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+
+  MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+}
+
+/**
+  * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
+  * @retval HAL_OK/HAL_TIMEOUT
+  */
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
+{
+  uint32_t tickstart;
+
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait for VRR bit  */
+  while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U)
+  {
+    if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVREFBUF(void)
+{
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+#endif /* VREFBUF */
+
+/**
+  * @brief  Enable the I/O analog switch voltage booster
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_EnableIOSwitchBooster(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+  * @brief  Disable the I/O analog switch voltage booster
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableIOSwitchBooster(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+  * @brief  Enable the I/O analog switch voltage by VDD
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_EnableIOSwitchVDD(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
+}
+
+/**
+  * @brief  Disable the I/O analog switch voltage by VDD
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableIOSwitchVDD(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
+}
+
+
+/** @brief  CCMSRAM page write protection enable
+  * @param Page: This parameter is a long 32bit value and can be a value of @ref SYSCFG_CCMSRAMWRP
+  * @note   write protection can only be disabled by a system reset
+  * @retval None
+  */
+void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page)
+{
+  assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE(Page));
+
+  SET_BIT(SYSCFG->SWPR, (uint32_t)(Page));
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c
new file mode 100644
index 0000000..47bfcbc
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c
@@ -0,0 +1,3682 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_adc.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Analog to Digital Converter (ADC)
+  *          peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *          Other functions (extended functions) are available in file
+  *          "stm32g4xx_hal_adc_ex.c".
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### ADC peripheral features #####
+  ==============================================================================
+  [..]
+  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+
+  (+) Interrupt generation at the end of regular conversion and in case of
+      analog watchdog or overrun events.
+
+  (+) Single and continuous conversion modes.
+
+  (+) Scan mode for conversion of several channels sequentially.
+
+  (+) Data alignment with in-built data coherency.
+
+  (+) Programmable sampling time (channel wise)
+
+  (+) External trigger (timer or EXTI) with configurable polarity
+
+  (+) DMA request generation for transfer of conversions data of regular group.
+
+  (+) Configurable delay between conversions in Dual interleaved mode.
+
+  (+) ADC channels selectable single/differential input.
+
+  (+) ADC offset shared on 4 offset instances.
+  (+) ADC gain compensation
+
+  (+) ADC calibration
+
+  (+) ADC conversion of regular group.
+
+  (+) ADC supply requirements: 1.62 V to 3.6 V.
+
+  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+      Vdda or to an external voltage reference).
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+
+     *** Configuration of top level parameters related to ADC ***
+     ============================================================
+     [..]
+
+    (#) Enable the ADC interface
+        (++) As prerequisite, ADC clock must be configured at RCC top level.
+
+        (++) Two clock settings are mandatory:
+             (+++) ADC clock (core clock, also possibly conversion clock).
+
+             (+++) ADC clock (conversions clock).
+                   Two possible clock sources: synchronous clock derived from AHB clock
+                   or asynchronous clock derived from system clock or PLL (output divider P)
+                   running up to 75MHz.
+
+             (+++) Example:
+                   Into HAL_ADC_MspInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)
+
+               RCC_ADCCLKSOURCE_PLL enable:                       (optional: if asynchronous clock selected)
+               (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
+               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLL;
+               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+        (++) ADC clock source and clock prescaler are configured at ADC level with
+             parameter "ClockPrescaler" using function HAL_ADC_Init().
+
+    (#) ADC pins configuration
+         (++) Enable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+         (++) Configure these ADC pins in analog mode
+              using function HAL_GPIO_Init()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Configure the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+              into the function of corresponding ADC interruption vector
+              ADCx_IRQHandler().
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+              using function HAL_DMA_Init().
+         (++) Configure the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+              into the function of corresponding DMA interruption vector
+              DMAx_Channelx_IRQHandler().
+
+     *** Configuration of ADC, group regular, channels parameters ***
+     ================================================================
+     [..]
+
+    (#) Configure the ADC parameters (resolution, data alignment, ...)
+        and regular group parameters (conversion trigger, sequencer, ...)
+        using function HAL_ADC_Init().
+
+    (#) Configure the channels for regular group parameters (channel number,
+        channel rank into sequencer, ..., into regular group)
+        using function HAL_ADC_ConfigChannel().
+
+    (#) Optionally, configure the analog watchdog parameters (channels
+        monitored, thresholds, ...)
+        using function HAL_ADC_AnalogWDGConfig().
+
+     *** Execution of ADC conversions ***
+     ====================================
+     [..]
+
+    (#) Optionally, perform an automatic ADC calibration to improve the
+        conversion accuracy
+        using function HAL_ADCEx_Calibration_Start().
+
+    (#) ADC driver can be used among three modes: polling, interruption,
+        transfer by DMA.
+
+        (++) ADC conversion by polling:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start()
+          (+++) Wait for ADC conversion completion
+                using function HAL_ADC_PollForConversion()
+          (+++) Retrieve conversion results
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral
+                using function HAL_ADC_Stop()
+
+        (++) ADC conversion by interruption:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_IT()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback()
+                (this function must be implemented in user program)
+          (+++) Retrieve conversion results
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral
+                using function HAL_ADC_Stop_IT()
+
+        (++) ADC conversion with transfer by DMA:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_DMA()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+                (these functions must be implemented in user program)
+          (+++) Conversion results are automatically transferred by DMA into
+                destination variable address.
+          (+++) Stop conversion and disable the ADC peripheral
+                using function HAL_ADC_Stop_DMA()
+
+     [..]
+
+    (@) Callback functions must be implemented in user program:
+      (+@) HAL_ADC_ErrorCallback()
+      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+      (+@) HAL_ADC_ConvCpltCallback()
+      (+@) HAL_ADC_ConvHalfCpltCallback
+
+     *** Deinitialization of ADC ***
+     ============================================================
+     [..]
+
+    (#) Disable the ADC interface
+      (++) ADC clock can be hard reset and disabled at RCC top level.
+        (++) Hard reset of ADC peripherals
+             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+        (++) ADC clock disable
+             using the equivalent macro/functions as configuration step.
+             (+++) Example:
+                   Into HAL_ADC_MspDeInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+               (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
+               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+    (#) ADC pins configuration
+         (++) Disable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Disable the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Deinitialize the DMA
+              using function HAL_DMA_Init().
+         (++) Disable the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+    [..]
+
+    *** Callback registration ***
+    =============================================
+    [..]
+
+     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions HAL_ADC_RegisterCallback()
+     to register an interrupt callback.
+    [..]
+
+     Function HAL_ADC_RegisterCallback() allows to register following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
+       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+       (+) EndOfSamplingCallback          : ADC end of sampling callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+
+     Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
+     weak function.
+    [..]
+
+     HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
+       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+       (+) EndOfSamplingCallback          : ADC end of sampling callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     [..]
+
+     By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
+     these callbacks are null (not registered beforehand).
+    [..]
+
+     If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+     [..]
+
+     Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+    [..]
+
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
+     or HAL_ADC_Init() function.
+     [..]
+
+     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADC ADC
+  * @brief ADC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+#define ADC_CFGR_FIELDS_1  ((ADC_CFGR_RES    | ADC_CFGR_ALIGN   |\
+                             ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
+                             ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
+                             ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL))   /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */
+
+/* Timeout values for ADC operations (enable settling time,                   */
+/*   disable settling time, ...).                                             */
+/*   Values defined to be higher than worst cases: low clock frequency,       */
+/*   maximum prescalers.                                                      */
+#define ADC_ENABLE_TIMEOUT              (2UL)    /*!< ADC enable time-out value  */
+#define ADC_DISABLE_TIMEOUT             (2UL)    /*!< ADC disable time-out value */
+
+/* Timeout to wait for current conversion on going to be completed.           */
+/* Timeout fixed to longest ADC conversion possible, for 1 channel:           */
+/*   - maximum sampling time (640.5 adc_clk)                                  */
+/*   - ADC resolution (Tsar 12 bits= 12.5 adc_clk)                            */
+/*   - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio)   */
+/*   - ADC oversampling ratio 256                                             */
+/*   Calculation: 653 * 4096 * 256 CPU clock cycles max                       */
+/* Unit: cycles of CPU clock.                                                 */
+#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL)  /*!< ADC conversion completion time-out value */
+
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    ADC Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the ADC.
+      (+) De-initialize the ADC.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the ADC peripheral and regular group according to
+  *         parameters specified in structure "ADC_InitTypeDef".
+  * @note   As prerequisite, ADC clock must be configured at RCC top level
+  *         (refer to description of RCC configuration for ADC
+  *         in header of this file).
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+  *         coming from ADC state reset. Following calls to this function can
+  *         be used to reconfigure some parameters of ADC_InitTypeDef
+  *         structure on the fly, without modifying MSP configuration. If ADC
+  *         MSP has to be modified again, HAL_ADC_DeInit() must be called
+  *         before HAL_ADC_Init().
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure
+  *         "ADC_InitTypeDef".
+  * @note   This function configures the ADC within 2 scopes: scope of entire
+  *         ADC and scope of regular group. For parameters details, see comments
+  *         of structure "ADC_InitTypeDef".
+  * @note   Parameters related to common ADC registers (ADC clock mode) are set
+  *         only if all ADCs are disabled.
+  *         If this is not the case, these common parameters setting are
+  *         bypassed without error reporting: it can be the intended behaviour in
+  *         case of update of a parameter of ADC_InitTypeDef on the fly,
+  *         without  disabling the other ADCs.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmpCFGR;
+  uint32_t tmp_adc_reg_is_conversion_on_going;
+  __IO uint32_t wait_loop_index = 0UL;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check ADC handle */
+  if (hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+  assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation));
+  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv));
+  assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+  assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+
+  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+  {
+    assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+    assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+    if (hadc->Init.DiscontinuousConvMode == ENABLE)
+    {
+      assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+    }
+  }
+
+  /* DISCEN and CONT bits cannot be set at the same time */
+  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+
+  /* Actions performed only if ADC is coming from state reset:                */
+  /* - Initialization of ADC MSP                                              */
+  if (hadc->State == HAL_ADC_STATE_RESET)
+  {
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    /* Init the ADC Callback settings */
+    hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
+    hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
+    hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
+    hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
+    hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak callback */
+    hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;  /* Legacy weak callback */
+    hadc->LevelOutOfWindow2Callback     = HAL_ADCEx_LevelOutOfWindow2Callback;      /* Legacy weak callback */
+    hadc->LevelOutOfWindow3Callback     = HAL_ADCEx_LevelOutOfWindow3Callback;      /* Legacy weak callback */
+    hadc->EndOfSamplingCallback         = HAL_ADCEx_EndOfSamplingCallback;          /* Legacy weak callback */
+
+    if (hadc->MspInitCallback == NULL)
+    {
+      hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hadc->MspInitCallback(hadc);
+#else
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+
+    /* Initialize Lock */
+    hadc->Lock = HAL_UNLOCKED;
+  }
+
+  /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
+  if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
+  {
+    /* Disable ADC deep power down mode */
+    LL_ADC_DisableDeepPowerDown(hadc->Instance);
+
+    /* System was in deep power down mode, calibration must
+     be relaunched or a previously saved calibration factor
+     re-applied once the ADC voltage regulator is enabled */
+  }
+
+  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+  {
+    /* Enable ADC internal voltage regulator */
+    LL_ADC_EnableInternalRegulator(hadc->Instance);
+
+    /* Note: Variable divided by 2 to compensate partially              */
+    /*       CPU processing cycles, scaling in us split to not          */
+    /*       exceed 32 bits register capacity and handle low frequency. */
+    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+    while (wait_loop_index != 0UL)
+    {
+      wait_loop_index--;
+    }
+  }
+
+  /* Verification that ADC voltage regulator is correctly enabled, whether    */
+  /* or not ADC is coming from state reset (if any potential problem of       */
+  /* clocking, voltage regulator would not be enabled).                       */
+  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    /* Set ADC error code to ADC peripheral internal error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Configuration of ADC parameters if previous preliminary actions are      */
+  /* correctly completed and if there is no conversion on going on regular    */
+  /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
+  /* called to update a parameter on the fly).                                */
+  tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+
+  if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+      && (tmp_adc_reg_is_conversion_on_going == 0UL)
+     )
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+
+    /* Configuration of common ADC parameters                                 */
+
+    /* Parameters update conditioned to ADC state:                            */
+    /* Parameters that can be updated only when ADC is disabled:              */
+    /*  - clock configuration                                                 */
+    if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+    {
+      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+      {
+        /* Reset configuration of ADC common register CCR:                      */
+        /*                                                                      */
+        /*   - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set  */
+        /*     according to adc->Init.ClockPrescaler. It selects the clock      */
+        /*    source and sets the clock division factor.                        */
+        /*                                                                      */
+        /* Some parameters of this register are not reset, since they are set   */
+        /* by other functions and must be kept in case of usage of this         */
+        /* function on the fly (update of a parameter of ADC_InitTypeDef        */
+        /* without needing to reconfigure all other ADC groups/channels         */
+        /* parameters):                                                         */
+        /*   - when multimode feature is available, multimode-related           */
+        /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
+        /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
+        /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
+        /*     (set into HAL_ADC_ConfigChannel() or                             */
+        /*     HAL_ADCEx_InjectedConfigChannel() )                              */
+        LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
+      }
+    }
+
+    /* Configuration of ADC:                                                  */
+    /*  - resolution                               Init.Resolution            */
+    /*  - data alignment                           Init.DataAlign             */
+    /*  - external trigger to start conversion     Init.ExternalTrigConv      */
+    /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
+    /*  - continuous conversion mode               Init.ContinuousConvMode    */
+    /*  - overrun                                  Init.Overrun               */
+    /*  - discontinuous mode                       Init.DiscontinuousConvMode */
+    /*  - discontinuous mode channel count         Init.NbrOfDiscConversion   */
+    tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)           |
+                hadc->Init.Overrun                                                     |
+                hadc->Init.DataAlign                                                   |
+                hadc->Init.Resolution                                                  |
+                ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+
+    if (hadc->Init.DiscontinuousConvMode == ENABLE)
+    {
+      tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
+    }
+
+    /* Enable external trigger if trigger selection is different of software  */
+    /* start.                                                                 */
+    /* Note: This configuration keeps the hardware feature of parameter       */
+    /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+    /*       software start.                                                  */
+    if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+    {
+      tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
+                  | hadc->Init.ExternalTrigConvEdge
+                 );
+    }
+
+    /* Update Configuration Register CFGR */
+    MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
+
+    /* Configuration of sampling mode */
+    MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
+
+    /* Parameters update conditioned to ADC state:                            */
+    /* Parameters that can be updated when ADC is disabled or enabled without */
+    /* conversion on going on regular and injected groups:                    */
+    /*  - Gain Compensation               Init.GainCompensation               */
+    /*  - DMA continuous request          Init.DMAContinuousRequests          */
+    /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
+    /*  - Oversampling parameters         Init.Oversampling                   */
+    tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+    tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+    if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+        && (tmp_adc_is_conversion_on_going_injected == 0UL)
+       )
+    {
+      tmpCFGR = (ADC_CFGR_DFSDM(hadc)                                            |
+                 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
+                 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+
+      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
+
+      if (hadc->Init.GainCompensation != 0UL)
+      {
+        SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
+        MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
+      }
+      else
+      {
+        CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
+        MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
+      }
+
+      if (hadc->Init.OversamplingMode == ENABLE)
+      {
+        assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
+        assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
+        assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
+        assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
+
+        /* Configuration of Oversampler:                                      */
+        /*  - Oversampling Ratio                                              */
+        /*  - Right bit shift                                                 */
+        /*  - Triggered mode                                                  */
+        /*  - Oversampling mode (continued/resumed)                           */
+        MODIFY_REG(hadc->Instance->CFGR2,
+                   ADC_CFGR2_OVSR  |
+                   ADC_CFGR2_OVSS  |
+                   ADC_CFGR2_TROVS |
+                   ADC_CFGR2_ROVSM,
+                   ADC_CFGR2_ROVSE                       |
+                   hadc->Init.Oversampling.Ratio         |
+                   hadc->Init.Oversampling.RightBitShift |
+                   hadc->Init.Oversampling.TriggeredMode |
+                   hadc->Init.Oversampling.OversamplingStopReset
+                  );
+      }
+      else
+      {
+        /* Disable ADC oversampling scope on ADC group regular */
+        CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
+      }
+
+    }
+
+    /* Configuration of regular group sequencer:                              */
+    /* - if scan mode is disabled, regular channels sequence length is set to */
+    /*   0x00: 1 channel converted (channel on regular rank 1)                */
+    /*   Parameter "NbrOfConversion" is discarded.                            */
+    /*   Note: Scan mode is not present by hardware on this device, but       */
+    /*   emulated by software for alignment over all STM32 devices.           */
+    /* - if scan mode is enabled, regular channels sequence length is set to  */
+    /*   parameter "NbrOfConversion".                                         */
+
+    if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+    {
+      /* Set number of ranks in regular group sequencer */
+      MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
+    }
+    else
+    {
+      CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
+    }
+
+    /* Initialize the ADC state */
+    /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
+    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Deinitialize the ADC peripheral registers to their default reset
+  *         values, with deinitialization of the ADC MSP.
+  * @note   For devices with several ADCs: reset of ADC common registers is done
+  *         only if all ADCs sharing the same common group are disabled.
+  *         (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
+  *         all ADC instances use the same core clock at RCC level, disabling
+  *         the core clock reset all ADC instances).
+  *         If this is not the case, reset of these common parameters reset is
+  *         bypassed without error reporting: it can be the intended behavior in
+  *         case of reset of a single ADC while the other ADCs sharing the same
+  *         common group is still running.
+  * @note   By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
+  *         this saves more power by reducing leakage currents
+  *         and is particularly interesting before entering MCU low-power modes.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check ADC handle */
+  if (hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+  /* Stop potential conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped            */
+  /* Flush register JSQR: reset the queue sequencer when injected             */
+  /* queue sequencer is enabled and ADC disabled.                             */
+  /* The software and hardware triggers of the injected sequence are both     */
+  /* internally disabled just after the completion of the last valid          */
+  /* injected sequence.                                                       */
+  SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Change ADC state */
+      hadc->State = HAL_ADC_STATE_READY;
+    }
+  }
+
+  /* Note: HAL ADC deInit is done independently of ADC conversion stop        */
+  /*       and disable return status. In case of status fail, attempt to      */
+  /*       perform deinitialization anyway and it is up user code in          */
+  /*       in HAL_ADC_MspDeInit() to reset the ADC peripheral using           */
+  /*       system RCC hard reset.                                             */
+
+  /* ========== Reset ADC registers ========== */
+  /* Reset register IER */
+  __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
+                              ADC_IT_JQOVF | ADC_IT_OVR  |
+                              ADC_IT_JEOS  | ADC_IT_JEOC |
+                              ADC_IT_EOS   | ADC_IT_EOC  |
+                              ADC_IT_EOSMP | ADC_IT_RDY));
+
+  /* Reset register ISR */
+  __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+                              ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
+                              ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
+                              ADC_FLAG_EOS   | ADC_FLAG_EOC  |
+                              ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+
+  /* Reset register CR */
+  /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
+     ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
+     no direct reset applicable.
+     Update CR register to reset value where doable by software */
+  CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
+  SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+
+  /* Reset register CFGR */
+  CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
+  SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+  /* Reset register CFGR2 */
+  CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS   | ADC_CFGR2_OVSS |
+            ADC_CFGR2_OVSR  | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
+
+  /* Reset register SMPR1 */
+  CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
+
+  /* Reset register SMPR2 */
+  CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
+            ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+            ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
+
+  /* Reset register TR1 */
+  CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
+
+  /* Reset register TR2 */
+  CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
+
+  /* Reset register TR3 */
+  CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
+
+  /* Reset register SQR1 */
+  CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
+            ADC_SQR1_SQ1 | ADC_SQR1_L);
+
+  /* Reset register SQR2 */
+  CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
+            ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
+
+  /* Reset register SQR3 */
+  CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
+            ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
+
+  /* Reset register SQR4 */
+  CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+  /* Register JSQR was reset when the ADC was disabled */
+
+  /* Reset register DR */
+  /* bits in access mode read only, no direct reset applicable*/
+
+  /* Reset register OFR1 */
+  CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
+  /* Reset register OFR2 */
+  CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
+  /* Reset register OFR3 */
+  CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
+  /* Reset register OFR4 */
+  CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+
+  /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+  /* bits in access mode read only, no direct reset applicable*/
+
+  /* Reset register AWD2CR */
+  CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+  /* Reset register AWD3CR */
+  CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+  /* Reset register DIFSEL */
+  CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+  /* Reset register CALFACT */
+  CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+
+
+  /* ========== Reset common ADC registers ========== */
+
+  /* Software is allowed to change common parameters only when all the other
+     ADCs are disabled.   */
+  if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+  {
+    /* Reset configuration of ADC common register CCR:
+      - clock mode: CKMODE, PRESCEN
+      - multimode related parameters (when this feature is available): MDMA,
+        DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
+      - internal measurement paths: Vbat, temperature sensor, Vref (set into
+        HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
+    */
+    ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
+
+    /* ========== Hard reset ADC peripheral ========== */
+    /* Performs a global reset of the entire ADC peripherals instances        */
+    /* sharing the same common ADC instance: ADC state is forced to           */
+    /* a similar state as after device power-on.                              */
+    /* Note: A possible implementation is to add RCC bus reset of ADC         */
+    /* (for example, using macro                                              */
+    /*  __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
+    /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)":         */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    if (hadc->MspDeInitCallback == NULL)
+    {
+      hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
+    }
+
+    /* DeInit the low level hardware */
+    hadc->MspDeInitCallback(hadc);
+#else
+    /* DeInit the low level hardware */
+    HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  }
+
+  /* Set ADC error code to none */
+  ADC_CLEAR_ERRORCODE(hadc);
+
+  /* Reset injected channel configuration parameters */
+  hadc->InjectionConfig.ContextQueue = 0;
+  hadc->InjectionConfig.ChannelCount = 0;
+
+  /* Set ADC state */
+  hadc->State = HAL_ADC_STATE_RESET;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Initialize the ADC MSP.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspInit must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitialize the ADC MSP.
+  * @param hadc ADC handle
+  * @note   All ADC instances use the same core clock at RCC level, disabling
+  *         the core clock reset all ADC instances).
+  * @retval None
+  */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspDeInit must be implemented in the user file.
+   */
+}
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User ADC Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
+  *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
+  *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+                                           pADC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = pCallback;
+        break;
+
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = pCallback;
+        break;
+
+      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+        hadc->InjectedConvCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
+        hadc->InjectedQueueOverflowCallback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+        hadc->LevelOutOfWindow2Callback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+        hadc->LevelOutOfWindow3Callback = pCallback;
+        break;
+
+      case HAL_ADC_END_OF_SAMPLING_CB_ID :
+        hadc->EndOfSamplingCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a ADC Callback
+  *         ADC callback is redirected to the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
+  *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
+  *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+        break;
+
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+        break;
+
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+        break;
+
+      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+        hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+        break;
+
+      case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
+        hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+        hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+        hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
+        break;
+
+      case HAL_ADC_END_OF_SAMPLING_CB_ID :
+        hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
+        break;
+
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
+  * @brief    ADC IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of regular group.
+      (+) Stop conversion of regular group.
+      (+) Poll for conversion complete on regular group.
+      (+) Poll for conversion event.
+      (+) Get result of regular channel conversion.
+      (+) Start conversion of regular group and enable interruptions.
+      (+) Stop conversion of regular group and disable interruptions.
+      (+) Handle ADC interrupt request
+      (+) Start conversion of regular group and enable DMA transfer.
+      (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC, start conversion of regular group.
+  * @note   Interruptions enabled in this function: None.
+  * @note   Case of multimode enabled (when multimode feature is available):
+  *           if ADC is Slave, ADC is enabled but conversion is not started,
+  *           if ADC is master, ADC is enabled and multimode conversion is started.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - if ADC instance is master or if multimode feature is not available
+        - if multimode setting is disabled (ADC instance slave in independent mode) */
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+         )
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#endif
+
+      /* Set ADC error code */
+      /* Check if a conversion is on going on ADC group injected */
+      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+      {
+        /* Reset ADC error code fields related to regular conversions only */
+        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+      }
+      else
+      {
+        /* Reset all ADC error code fields */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+
+      /* Clear ADC group regular conversion flag and overrun flag               */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      /* Case of multimode enabled (when multimode feature is available):     */
+      /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
+      /*    enabled only (conversion is not started),                         */
+      /*  - if ADC is master, ADC is enabled and conversion is started.       */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+         )
+      {
+        /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+        {
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+        }
+
+        /* Start ADC group regular conversion */
+        LL_ADC_REG_StartConversion(hadc->Instance);
+      }
+      else
+      {
+        /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        /* if Master ADC JAUTO bit is set, update Slave State in setting
+           HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
+        tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+        if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
+        {
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+        }
+
+      }
+#else
+      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+      {
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+      }
+
+      /* Start ADC group regular conversion */
+      LL_ADC_REG_StartConversion(hadc->Instance);
+#endif
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected channels in
+  *         case of auto_injection mode), disable ADC peripheral.
+  * @note:  ADC peripheral disable is forcing stop of potential
+  *         conversion on injected group. If injected group is under use, it
+  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Wait for regular group conversion to be completed.
+  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
+  *         conversion) are cleared by this function, with an exception:
+  *         if low power feature "LowPowerAutoWait" is enabled, flags are
+  *         not cleared to not interfere with this feature until data register
+  *         is read using function HAL_ADC_GetValue().
+  * @note   This function cannot be used in a particular setup: ADC configured
+  *         in DMA mode and polling for end of each conversion (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+  *         In this case, DMA resets the flag EOC and polling cannot be
+  *         performed on each conversion. Nevertheless, polling can still
+  *         be performed on the complete sequence (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+  * @param hadc ADC handle
+  * @param Timeout Timeout value in millisecond.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t tmp_Flag_End;
+  uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* If end of conversion selected to end of sequence conversions */
+  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+  {
+    tmp_Flag_End = ADC_FLAG_EOS;
+  }
+  /* If end of conversion selected to end of unitary conversion */
+  else /* ADC_EOC_SINGLE_CONV */
+  {
+    /* Verification that ADC configuration is compliant with polling for      */
+    /* each conversion:                                                       */
+    /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
+    /* several ranks and polling for end of each conversion.                  */
+    /* For code simplicity sake, this particular case is generalized to       */
+    /* ADC configured in DMA mode and and polling for end of each conversion. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+    if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+       )
+    {
+      /* Check ADC DMA mode in independent mode on ADC group regular */
+      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        return HAL_ERROR;
+      }
+      else
+      {
+        tmp_Flag_End = (ADC_FLAG_EOC);
+      }
+    }
+    else
+    {
+      /* Check ADC DMA mode in multimode on ADC group regular */
+      if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        return HAL_ERROR;
+      }
+      else
+      {
+        tmp_Flag_End = (ADC_FLAG_EOC);
+      }
+    }
+#else
+    /* Check ADC DMA mode */
+    if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      return HAL_ERROR;
+    }
+    else
+    {
+      tmp_Flag_End = (ADC_FLAG_EOC);
+    }
+#endif
+  }
+
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+
+  /* Wait until End of unitary conversion or sequence conversions flag is raised */
+  while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+  /* Determine whether any further conversion upcoming on group regular       */
+  /* by external trigger, continuous mode or scan sequence on going.          */
+  if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+      && (hadc->Init.ContinuousConvMode == DISABLE)
+     )
+  {
+    /* Check whether end of sequence is reached */
+    if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+    {
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+      if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+      }
+    }
+  }
+
+  /* Get relevant register CFGR in ADC instance of ADC master or slave        */
+  /* in function of multimode state (for devices with multimode               */
+  /* available).                                                              */
+#if defined(ADC_MULTIMODE_SUPPORT)
+  if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+      || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+      || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+      || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+     )
+  {
+    /* Retrieve handle ADC CFGR register */
+    tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+  }
+  else
+  {
+    /* Retrieve Master ADC CFGR register */
+    tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+    tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+  }
+#else
+  /* Retrieve handle ADC CFGR register */
+  tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif
+
+  /* Clear polled flag */
+  if (tmp_Flag_End == ADC_FLAG_EOS)
+  {
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
+  }
+  else
+  {
+    /* Clear end of conversion EOC flag of regular group if low power feature */
+    /* "LowPowerAutoWait " is disabled, to not interfere with this feature    */
+    /* until data register is read using function HAL_ADC_GetValue().         */
+    if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
+    {
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll for ADC event.
+  * @param hadc ADC handle
+  * @param EventType the ADC event type.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event
+  *            @arg @ref ADC_AWD1_EVENT   ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
+  *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
+  *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
+  *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
+  *            @arg @ref ADC_JQOVF_EVENT  ADC Injected context queue overflow event
+  * @param Timeout Timeout value in millisecond.
+  * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
+  *         Indeed, the latter is reset only if hadc->Init.Overrun field is set
+  *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
+  *         by a new converted data as soon as OVR is cleared.
+  *         To reset OVR flag once the preserved data is retrieved, the user can resort
+  *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+
+  /* Check selected event flag */
+  while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  switch (EventType)
+  {
+    /* End Of Sampling event */
+    case ADC_EOSMP_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+
+      /* Clear the End Of Sampling flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+
+      break;
+
+    /* Analog watchdog (level out of window) event */
+    /* Note: In case of several analog watchdog enabled, if needed to know      */
+    /* which one triggered and on which ADCx, test ADC state of analog watchdog */
+    /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()".        */
+    /* For example:                                                             */
+    /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "          */
+    /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) "          */
+    /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) "          */
+
+    /* Check analog watchdog 1 flag */
+    case ADC_AWD_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+      /* Clear ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+
+      break;
+
+    /* Check analog watchdog 2 flag */
+    case ADC_AWD2_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+      /* Clear ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+
+      break;
+
+    /* Check analog watchdog 3 flag */
+    case ADC_AWD3_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+      /* Clear ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+
+      break;
+
+    /* Injected context queue overflow event */
+    case ADC_JQOVF_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+      /* Set ADC error code to Injected context queue overflow */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+      /* Clear ADC Injected context queue overflow flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+      break;
+
+    /* Overrun event */
+    default: /* Case ADC_OVR_EVENT */
+      /* If overrun is set to overwrite previous data, overrun event is not     */
+      /* considered as an error.                                                */
+      /* (cf ref manual "Managing conversions without using the DMA and without */
+      /* overrun ")                                                             */
+      if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+      {
+        /* Set ADC state */
+        SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+        /* Set ADC error code to overrun */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+      }
+      else
+      {
+        /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
+           otherwise, data register is potentially overwritten by new converted data as soon
+           as OVR is cleared. */
+        __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+      }
+      break;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of regular group with interruption.
+  * @note   Interruptions enabled in this function according to initialization
+  *         setting : EOC (end of conversion), EOS (end of sequence),
+  *         OVR overrun.
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   Case of multimode enabled (when multimode feature is available):
+  *         HAL_ADC_Start_IT() must be called for ADC Slave first, then for
+  *         ADC Master.
+  *         For ADC Slave, ADC is enabled only (conversion is not started).
+  *         For ADC Master, ADC is enabled and multimode conversion is started.
+  * @note   To guarantee a proper reset of all interruptions once all the needed
+  *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
+  *         a correct stop of the IT-based conversions.
+  * @note   By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
+  *         interruption. If required (e.g. in case of oversampling with trigger
+  *         mode), the user must:
+  *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
+  *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
+  *          before calling HAL_ADC_Start_IT().
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - if ADC instance is master or if multimode feature is not available
+        - if multimode setting is disabled (ADC instance slave in independent mode) */
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+         )
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#endif
+
+      /* Set ADC error code */
+      /* Check if a conversion is on going on ADC group injected */
+      if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+      {
+        /* Reset ADC error code fields related to regular conversions only */
+        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+      }
+      else
+      {
+        /* Reset all ADC error code fields */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+
+      /* Clear ADC group regular conversion flag and overrun flag               */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Disable all interruptions before enabling the desired ones */
+      __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+      /* Enable ADC end of conversion interrupt */
+      switch (hadc->Init.EOCSelection)
+      {
+        case ADC_EOC_SEQ_CONV:
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
+          break;
+        /* case ADC_EOC_SINGLE_CONV */
+        default:
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+          break;
+      }
+
+      /* Enable ADC overrun interrupt */
+      /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
+         ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
+         behavior and no CPU time is lost for a non-processed interruption */
+      if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+      {
+        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+      }
+
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      /* Case of multimode enabled (when multimode feature is available):     */
+      /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
+      /*    enabled only (conversion is not started),                         */
+      /*  - if ADC is master, ADC is enabled and conversion is started.       */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+         )
+      {
+        /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+        {
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+
+          /* Enable as well injected interruptions in case
+           HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+           allows to start regular and injected conversions when JAUTO is
+           set with a single call to HAL_ADC_Start_IT() */
+          switch (hadc->Init.EOCSelection)
+          {
+            case ADC_EOC_SEQ_CONV:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+              break;
+            /* case ADC_EOC_SINGLE_CONV */
+            default:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+              break;
+          }
+        }
+
+        /* Start ADC group regular conversion */
+        LL_ADC_REG_StartConversion(hadc->Instance);
+      }
+      else
+      {
+        /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        /* if Master ADC JAUTO bit is set, Slave injected interruptions
+           are enabled nevertheless (for same reason as above) */
+        tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+        if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
+        {
+          /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
+             and in resetting HAL_ADC_STATE_INJ_EOC bit */
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+          /* Next, set Slave injected interruptions */
+          switch (hadc->Init.EOCSelection)
+          {
+            case ADC_EOC_SEQ_CONV:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+              break;
+            /* case ADC_EOC_SINGLE_CONV */
+            default:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+              break;
+          }
+        }
+      }
+#else
+      /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+      {
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+
+        /* Enable as well injected interruptions in case
+         HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+         allows to start regular and injected conversions when JAUTO is
+         set with a single call to HAL_ADC_Start_IT() */
+        switch (hadc->Init.EOCSelection)
+        {
+          case ADC_EOC_SEQ_CONV:
+            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+            __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+            break;
+          /* case ADC_EOC_SINGLE_CONV */
+          default:
+            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+            __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+            break;
+        }
+      }
+
+      /* Start ADC group regular conversion */
+      LL_ADC_REG_StartConversion(hadc->Instance);
+#endif
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable interrution of
+  *         end-of-conversion, disable ADC peripheral.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC end of conversion interrupt for regular group */
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
+  * @note   Interruptions enabled in this function:
+  *         overrun (if applicable), DMA half transfer, DMA transfer complete.
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
+  *         is designed for single-ADC mode only. For multimode, the dedicated
+  *         HAL_ADCEx_MultiModeStart_DMA() function must be used.
+  * @param hadc ADC handle
+  * @param pData Destination Buffer address.
+  * @param Length Number of data to be transferred from ADC peripheral to memory
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+    /* Ensure that multimode regular conversions are not enabled.   */
+    /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
+    if ((ADC_IS_INDEPENDENT(hadc) != RESET)
+        || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+       )
+#endif /* ADC_MULTIMODE_SUPPORT */
+    {
+      /* Enable the ADC peripheral */
+      tmp_hal_status = ADC_Enable(hadc);
+
+      /* Start conversion if ADC is effectively enabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state                                                        */
+        /* - Clear state bitfield related to regular group conversion results   */
+        /* - Set state bitfield related to regular operation                    */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                          HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+        /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+          - if ADC instance is master or if multimode feature is not available
+          - if multimode setting is disabled (ADC instance slave in independent mode) */
+        if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+            || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+           )
+        {
+          CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        }
+#endif
+
+        /* Check if a conversion is on going on ADC group injected */
+        if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+        {
+          /* Reset ADC error code fields related to regular conversions only */
+          CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+        }
+        else
+        {
+          /* Reset all ADC error code fields */
+          ADC_CLEAR_ERRORCODE(hadc);
+        }
+
+        /* Set the DMA transfer complete callback */
+        hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+        /* Set the DMA half transfer complete callback */
+        hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+        /* Set the DMA error callback */
+        hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+        /* Manage ADC and DMA start: ADC overrun interruption, DMA start,     */
+        /* ADC start (in case of SW start):                                   */
+
+        /* Clear regular group conversion flag and overrun flag               */
+        /* (To ensure of no unknown state from potential previous ADC         */
+        /* operations)                                                        */
+        __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+        /* Process unlocked */
+        /* Unlock before starting ADC conversions: in case of potential         */
+        /* interruption, to let the process to ADC IRQ Handler.                 */
+        __HAL_UNLOCK(hadc);
+
+        /* With DMA, overrun event is always considered as an error even if
+           hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
+           ADC_IT_OVR is enabled. */
+        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+        /* Enable ADC DMA mode */
+        SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+        /* Start the DMA channel */
+        tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+        /* Enable conversion of regular group.                                  */
+        /* If software start has been selected, conversion starts immediately.  */
+        /* If external trigger has been selected, conversion will start at next */
+        /* trigger event.                                                       */
+        /* Start ADC group regular conversion */
+        LL_ADC_REG_StartConversion(hadc->Instance);
+      }
+      else
+      {
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+      }
+
+    }
+#if defined(ADC_MULTIMODE_SUPPORT)
+    else
+    {
+      tmp_hal_status = HAL_ERROR;
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+#endif
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable ADC DMA transfer, disable
+  *         ADC peripheral.
+  * @note:  ADC peripheral disable is forcing stop of potential
+  *         conversion on ADC group injected. If ADC group injected is under use, it
+  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+  * @note   Case of multimode enabled (when multimode feature is available):
+  *         HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
+  *         For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential ADC group regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
+    CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+    {
+      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+      /* Check if DMA channel effectively disabled */
+      if (tmp_hal_status != HAL_OK)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+      }
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripheral */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
+    /* to keep in memory a potential failing status.                          */
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmp_hal_status = ADC_Disable(hadc);
+    }
+    else
+    {
+      (void)ADC_Disable(hadc);
+    }
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get ADC regular group conversion result.
+  * @note   Reading register DR automatically clears ADC flag EOC
+  *         (ADC group regular end of unitary conversion).
+  * @note   This function does not clear ADC flag EOS
+  *         (ADC group regular end of sequence conversion).
+  *         Occurrence of flag EOS rising:
+  *          - If sequencer is composed of 1 rank, flag EOS is equivalent
+  *            to flag EOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag EOC only is raised, at the end of the scan sequence
+  *            both flags EOC and EOS are raised.
+  *         To clear this flag, either use function:
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADC_PollForConversion()
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+  * @param hadc ADC handle
+  * @retval ADC group regular conversion data
+  */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Note: EOC flag is not cleared here by software because automatically     */
+  /*       cleared by hardware when reading register DR.                      */
+
+  /* Return ADC converted value */
+  return hadc->Instance->DR;
+}
+
+/**
+  * @brief  Start ADC conversion sampling phase of regular group
+  * @note:  This function should only be called to start sampling when
+  *         - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
+  *         mode has been selected
+  *         - @ref ADC_SOFTWARE_START has been selected as trigger source
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Start sampling */
+  SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop ADC conversion sampling phase of regular group and start conversion
+  * @note:  This function should only be called to stop sampling when
+  *         - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
+  *         mode has been selected
+  *         - @ref ADC_SOFTWARE_START has been selected as trigger source
+  *         - after sampling has been started using @ref HAL_ADC_StartSampling.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Start sampling */
+  CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle ADC interrupt request.
+  * @param hadc ADC handle
+  * @retval None
+  */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
+{
+  uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
+  uint32_t tmp_isr = hadc->Instance->ISR;
+  uint32_t tmp_ier = hadc->Instance->IER;
+  uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+  uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+  uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+
+  /* ========== Check End of Sampling flag for ADC group regular ========== */
+  if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
+  {
+    /* Update state machine on end of sampling status if not in error state */
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+    }
+
+    /* End Of Sampling callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->EndOfSamplingCallback(hadc);
+#else
+    HAL_ADCEx_EndOfSamplingCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear regular group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+  }
+
+  /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
+  if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
+      (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+  {
+    /* Update state machine on conversion status if not in error state */
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+    }
+
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going         */
+    /* to disable interruption.                                               */
+    if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+    {
+      /* Get relevant register CFGR in ADC instance of ADC master or slave    */
+      /* in function of multimode state (for devices with multimode           */
+      /* available).                                                          */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+         )
+      {
+        /* check CONT bit directly in handle ADC CFGR register */
+        tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+      }
+      else
+      {
+        /* else need to check Master ADC CONT bit */
+        tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+        tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+      }
+#else
+      tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif
+
+      /* Carry on if continuous mode is disabled */
+      if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
+      {
+        /* If End of Sequence is reached, disable interrupts */
+        if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+        {
+          /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit         */
+          /* ADSTART==0 (no conversion on going)                              */
+          if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+          {
+            /* Disable ADC end of sequence conversion interrupt */
+            /* Note: Overrun interrupt was enabled with EOC interrupt in      */
+            /* HAL_Start_IT(), but is not disabled here because can be used   */
+            /* by overrun IRQ process below.                                  */
+            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+            /* Set ADC state */
+            CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+            if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+            {
+              SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+            }
+          }
+          else
+          {
+            /* Change ADC state to error state */
+            SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+            /* Set ADC error code to ADC peripheral internal error */
+            SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+          }
+        }
+      }
+    }
+
+    /* Conversion complete callback */
+    /* Note: Into callback function "HAL_ADC_ConvCpltCallback()",             */
+    /*       to determine if conversion has been triggered from EOC or EOS,   */
+    /*       possibility to use:                                              */
+    /*        " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "               */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear regular group conversion flag */
+    /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
+    /*       conversion flags clear induces the release of the preserved data.*/
+    /*       Therefore, if the preserved data value is needed, it must be     */
+    /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+  }
+
+  /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
+  if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
+      (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
+  {
+    /* Update state machine on conversion status if not in error state */
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+    }
+
+    /* Retrieve ADC configuration */
+    tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+    tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+    /* Get relevant register CFGR in ADC instance of ADC master or slave  */
+    /* in function of multimode state (for devices with multimode         */
+    /* available).                                                        */
+#if defined(ADC_MULTIMODE_SUPPORT)
+    if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+        || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+       )
+    {
+      tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+    }
+    else
+    {
+      tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+      tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+    }
+#else
+    tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif
+
+    /* Disable interruption if no further conversion upcoming by injected     */
+    /* external trigger or by automatic injected conversion with regular      */
+    /* group having no further conversion upcoming (same conditions as        */
+    /* regular group interruption disabling above),                           */
+    /* and if injected scan sequence is completed.                            */
+    if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
+    {
+      if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
+          ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+           (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
+      {
+        /* If End of Sequence is reached, disable interrupts */
+        if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+        {
+          /* Particular case if injected contexts queue is enabled:             */
+          /* when the last context has been fully processed, JSQR is reset      */
+          /* by the hardware. Even if no injected conversion is planned to come */
+          /* (queue empty, triggers are ignored), it can start again            */
+          /* immediately after setting a new context (JADSTART is still set).   */
+          /* Therefore, state of HAL ADC injected group is kept to busy.        */
+          if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+          {
+            /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit       */
+            /* JADSTART==0 (no conversion on going)                             */
+            if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+            {
+              /* Disable ADC end of sequence conversion interrupt  */
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+
+              /* Set ADC state */
+              CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+              if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+              {
+                SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+              }
+            }
+            else
+            {
+              /* Update ADC state machine to error */
+              SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+              /* Set ADC error code to ADC peripheral internal error */
+              SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+            }
+          }
+        }
+      }
+    }
+
+    /* Injected Conversion complete callback */
+    /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to
+              if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+              if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+              interruption has been triggered by end of conversion or end of
+              sequence.    */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->InjectedConvCpltCallback(hadc);
+#else
+    HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear injected group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+  }
+
+  /* ========== Check Analog watchdog 1 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+    /* Level out of window 1 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->LevelOutOfWindowCallback(hadc);
+#else
+    HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+  }
+
+  /* ========== Check analog watchdog 2 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+    /* Level out of window 2 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->LevelOutOfWindow2Callback(hadc);
+#else
+    HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+  }
+
+  /* ========== Check analog watchdog 3 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+    /* Level out of window 3 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->LevelOutOfWindow3Callback(hadc);
+#else
+    HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+  }
+
+  /* ========== Check Overrun flag ========== */
+  if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
+  {
+    /* If overrun is set to overwrite previous data (default setting),        */
+    /* overrun event is not considered as an error.                           */
+    /* (cf ref manual "Managing conversions without using the DMA and without */
+    /* overrun ")                                                             */
+    /* Exception for usage with DMA overrun event always considered as an     */
+    /* error.                                                                 */
+    if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+    {
+      overrun_error = 1UL;
+    }
+    else
+    {
+      /* Check DMA configuration */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
+      {
+        /* Multimode (when feature is available) is enabled,
+           Common Control Register MDMA bits must be checked. */
+        if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
+        {
+          overrun_error = 1UL;
+        }
+      }
+      else
+#endif
+      {
+        /* Multimode not set or feature not available or ADC independent */
+        if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL)
+        {
+          overrun_error = 1UL;
+        }
+      }
+    }
+
+    if (overrun_error == 1UL)
+    {
+      /* Change ADC state to error state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+      /* Set ADC error code to overrun */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+      /* Error callback */
+      /* Note: In case of overrun, ADC conversion data is preserved until     */
+      /*       flag OVR is reset.                                             */
+      /*       Therefore, old ADC conversion data can be retrieved in         */
+      /*       function "HAL_ADC_ErrorCallback()".                            */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    }
+
+    /* Clear ADC overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  }
+
+  /* ========== Check Injected context queue overflow flag ========== */
+  if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
+  {
+    /* Change ADC state to overrun state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+    /* Set ADC error code to Injected context queue overflow */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+    /* Clear the Injected context queue overflow flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+    /* Injected context queue overflow callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->InjectedQueueOverflowCallback(hadc);
+#else
+    HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  }
+
+}
+
+/**
+  * @brief  Conversion complete callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Conversion DMA half-transfer callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 1 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  ADC error callback in non-blocking mode
+  *         (ADC conversion with interruption or transfer by DMA).
+  * @note   In case of error due to overrun when using ADC with DMA transfer
+  *         (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+  *         - If needed, restart a new ADC conversion using function
+  *           "HAL_ADC_Start_DMA()"
+  *           (this function is also clearing overrun flag)
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ErrorCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure channels on regular group
+      (+) Configure the analog watchdog
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure a channel to be assigned to ADC group regular.
+  * @note   In case of usage of internal measurement channels:
+  *         Vbat/VrefInt/TempSensor.
+  *         These internal paths can be disabled using function
+  *         HAL_ADC_DeInit().
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes channel into ADC group regular,
+  *         following calls to this function can be used to reconfigure
+  *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
+  *         without resetting the ADC.
+  *         The setting of these parameters is conditioned to ADC state:
+  *         Refer to comments of structure "ADC_ChannelConfTypeDef".
+  * @param hadc ADC handle
+  * @param sConfig Structure of ADC channel assigned to ADC group regular.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmpOffsetShifted;
+  uint32_t tmp_config_internal_channel;
+  __IO uint32_t wait_loop_index = 0UL;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
+  assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
+
+  /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+     ignored (considered as reset) */
+  assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
+
+  /* Verification of channel number */
+  if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+  {
+    assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
+  }
+  else
+  {
+    assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Channel number                                                        */
+  /*  - Channel rank                                                          */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Set ADC group regular sequence: channel on the selected scan sequence rank */
+    LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
+
+    /* Parameters update conditioned to ADC state:                              */
+    /* Parameters that can be updated when ADC is disabled or enabled without   */
+    /* conversion on going on regular group:                                    */
+    /*  - Channel sampling time                                                 */
+    /*  - Channel offset                                                        */
+    tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+    tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+    if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+        && (tmp_adc_is_conversion_on_going_injected == 0UL)
+       )
+    {
+      /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
+      if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
+      {
+        /* Set sampling time of the selected ADC channel */
+        LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
+
+        /* Set ADC sampling time common configuration */
+        LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
+      }
+      else
+      {
+        /* Set sampling time of the selected ADC channel */
+        LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
+
+        /* Set ADC sampling time common configuration */
+        LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
+      }
+
+      /* Configure the offset: offset enable/disable, channel, offset value */
+
+      /* Shift the offset with respect to the selected ADC resolution. */
+      /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+      tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
+
+      if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
+      {
+        /* Set ADC selected offset number */
+        LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
+
+        assert_param(IS_ADC_OFFSET_SIGN(sConfig->OffsetSign));
+        assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSaturation));
+        /* Set ADC selected offset sign & saturation */
+        LL_ADC_SetOffsetSign(hadc->Instance, sConfig->OffsetNumber, sConfig->OffsetSign);
+        LL_ADC_SetOffsetSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
+      }
+      else
+      {
+        /* Scan each offset register to check if the selected channel is targeted. */
+        /* If this is the case, the corresponding offset number is disabled.       */
+        if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+            == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+        {
+          LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
+        }
+        if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+            == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+        {
+          LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
+        }
+        if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+            == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+        {
+          LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
+        }
+        if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+            == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+        {
+          LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
+        }
+      }
+    }
+
+    /* Parameters update conditioned to ADC state:                              */
+    /* Parameters that can be updated only when ADC is disabled:                */
+    /*  - Single or differential mode                                           */
+    if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+    {
+      /* Set mode single-ended or differential input of the selected ADC channel */
+      LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
+
+      /* Configuration of differential mode */
+      if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
+      {
+        /* Set sampling time of the selected ADC channel */
+        /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
+        LL_ADC_SetChannelSamplingTime(hadc->Instance,
+                                      (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
+                                      sConfig->SamplingTime);
+      }
+
+    }
+
+    /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
+    /* If internal channel selected, enable dedicated internal buffers and    */
+    /* paths.                                                                 */
+    /* Note: these internal measurement paths can be disabled using           */
+    /* HAL_ADC_DeInit().                                                      */
+
+    if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+    {
+      tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+      /* If the requested internal measurement path has already been enabled, */
+      /* bypass the configuration processing.                                 */
+      if (((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5))
+          && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+      {
+        if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                         LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+          /* Delay for temperature sensor stabilization time */
+          /* Wait loop initialization and execution */
+          /* Note: Variable divided by 2 to compensate partially              */
+          /*       CPU processing cycles, scaling in us split to not          */
+          /*       exceed 32 bits register capacity and handle low frequency. */
+          wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+          while (wait_loop_index != 0UL)
+          {
+            wait_loop_index--;
+          }
+        }
+      }
+      else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+      {
+        if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                         LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+        }
+      }
+      else if ((sConfig->Channel == ADC_CHANNEL_VREFINT)
+               && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+      {
+        if (ADC_VREFINT_INSTANCE(hadc))
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                         LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+        }
+      }
+      else
+      {
+        /* nothing to do */
+      }
+    }
+  }
+
+  /* If a conversion is on going on regular group, no update on regular       */
+  /* channel could be done on neither of the channel configuration structure  */
+  /* parameters.                                                              */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Configure the analog watchdog.
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the selected analog watchdog, successive
+  *         calls to this function can be used to reconfigure some parameters
+  *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
+  *         the ADC.
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure
+  *         "ADC_AnalogWDGConfTypeDef".
+  * @note   On this STM32 series, analog watchdog thresholds can be modified
+  *         while ADC conversion is on going.
+  *         In this case, some constraints must be taken into account:
+  *         the programmed threshold values are effective from the next
+  *         ADC EOC (end of unitary conversion).
+  *         Considering that registers write delay may happen due to
+  *         bus activity, this might cause an uncertainty on the
+  *         effective timing of the new programmed threshold values.
+  * @param hadc ADC handle
+  * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmpAWDHighThresholdShifted;
+  uint32_t tmpAWDLowThresholdShifted;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(AnalogWDGConfig->FilteringConfig));
+  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+
+  if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
+      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
+      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
+  {
+    assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
+  }
+
+  /* Verify thresholds range */
+  if (hadc->Init.OversamplingMode == ENABLE)
+  {
+    /* Case of oversampling enabled: depending on ratio and shift configuration,
+       analog watchdog thresholds can be higher than ADC resolution.
+       Verify if thresholds are within maximum thresholds range. */
+    assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
+    assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
+  }
+  else
+  {
+    /* Verify if thresholds are within the selected ADC resolution */
+    assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+    assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on ADC groups regular and injected:                  */
+  /*  - Analog watchdog channels                                              */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+  if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    /* Analog watchdog configuration */
+    if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+    {
+      /* Configuration of analog watchdog:                                    */
+      /*  - Set the analog watchdog enable mode: one or overall group of      */
+      /*    channels, on groups regular and-or injected.                      */
+      switch (AnalogWDGConfig->WatchdogMode)
+      {
+        case ADC_ANALOGWATCHDOG_SINGLE_REG:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
+                                          LL_ADC_GROUP_REGULAR));
+          break;
+
+        case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
+                                          LL_ADC_GROUP_INJECTED));
+          break;
+
+        case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
+                                          LL_ADC_GROUP_REGULAR_INJECTED));
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_REG:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_INJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+          break;
+
+        default: /* ADC_ANALOGWATCHDOG_NONE */
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
+          break;
+      }
+
+      /* Set the filtering configuration */
+      MODIFY_REG(hadc->Instance->TR1,
+                 ADC_TR1_AWDFILT,
+                 AnalogWDGConfig->FilteringConfig);
+
+      /* Update state, clear previous result related to AWD1 */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+      /* Clear flag ADC analog watchdog */
+      /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+      /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+      /* (in case left enabled by previous ADC operations).                 */
+      LL_ADC_ClearFlag_AWD1(hadc->Instance);
+
+      /* Configure ADC analog watchdog interrupt */
+      if (AnalogWDGConfig->ITMode == ENABLE)
+      {
+        LL_ADC_EnableIT_AWD1(hadc->Instance);
+      }
+      else
+      {
+        LL_ADC_DisableIT_AWD1(hadc->Instance);
+      }
+    }
+    /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
+    else
+    {
+      switch (AnalogWDGConfig->WatchdogMode)
+      {
+        case ADC_ANALOGWATCHDOG_SINGLE_REG:
+        case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+        case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+          /* Update AWD by bitfield to keep the possibility to monitor        */
+          /* several channels by successive calls of this function.           */
+          if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+          {
+            SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
+          }
+          else
+          {
+            SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
+          }
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_REG:
+        case ADC_ANALOGWATCHDOG_ALL_INJEC:
+        case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+          break;
+
+        default: /* ADC_ANALOGWATCHDOG_NONE */
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
+          break;
+      }
+
+      if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+      {
+        /* Update state, clear previous result related to AWD2 */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+        /* Clear flag ADC analog watchdog */
+        /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+        /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+        /* (in case left enabled by previous ADC operations).                 */
+        LL_ADC_ClearFlag_AWD2(hadc->Instance);
+
+        /* Configure ADC analog watchdog interrupt */
+        if (AnalogWDGConfig->ITMode == ENABLE)
+        {
+          LL_ADC_EnableIT_AWD2(hadc->Instance);
+        }
+        else
+        {
+          LL_ADC_DisableIT_AWD2(hadc->Instance);
+        }
+      }
+      /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+      else
+      {
+        /* Update state, clear previous result related to AWD3 */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+        /* Clear flag ADC analog watchdog */
+        /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+        /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+        /* (in case left enabled by previous ADC operations).                 */
+        LL_ADC_ClearFlag_AWD3(hadc->Instance);
+
+        /* Configure ADC analog watchdog interrupt */
+        if (AnalogWDGConfig->ITMode == ENABLE)
+        {
+          LL_ADC_EnableIT_AWD3(hadc->Instance);
+        }
+        else
+        {
+          LL_ADC_DisableIT_AWD3(hadc->Instance);
+        }
+      }
+    }
+
+  }
+
+  /* Analog watchdog thresholds configuration */
+  if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+  {
+    /* Shift the offset with respect to the selected ADC resolution:        */
+    /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
+    /* are set to 0.                                                        */
+    tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+    tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+  }
+  /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
+  else
+  {
+    /* Shift the offset with respect to the selected ADC resolution:        */
+    /* Thresholds have to be left-aligned on bit 7, the LSB (right bits)    */
+    /* are set to 0.                                                        */
+    tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+    tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+  }
+
+  /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+  LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
+                                  tmpAWDLowThresholdShifted);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+  *  @brief    ADC Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral state and errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions to get in run-time the status of the
+    peripheral.
+      (+) Check the ADC state
+      (+) Check the ADC error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the ADC handle state.
+  * @note   ADC state machine is managed by bitfields, ADC status must be
+  *         compared with states bits.
+  *         For example:
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+  * @param hadc ADC handle
+  * @retval ADC handle state (bitfield on 32 bits)
+  */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Return ADC handle state */
+  return hadc->State;
+}
+
+/**
+  * @brief  Return the ADC error code.
+  * @param hadc ADC handle
+  * @retval ADC error code (bitfield on 32 bits)
+  */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  return hadc->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Stop ADC conversion.
+  * @param hadc ADC handle
+  * @param ConversionGroup ADC group regular and/or injected.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_REGULAR_GROUP           ADC regular conversion type.
+  *            @arg @ref ADC_INJECTED_GROUP          ADC injected conversion type.
+  *            @arg @ref ADC_REGULAR_INJECTED_GROUP  ADC regular and injected conversion type.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
+{
+  uint32_t tickstart;
+  uint32_t Conversion_Timeout_CPU_cycles = 0UL;
+  uint32_t conversion_group_reassigned = ConversionGroup;
+  uint32_t tmp_ADC_CR_ADSTART_JADSTART;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
+
+  /* Verification if ADC is not already stopped (on regular and injected      */
+  /* groups) to bypass this function if not needed.                           */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+  if ((tmp_adc_is_conversion_on_going_regular != 0UL)
+      || (tmp_adc_is_conversion_on_going_injected != 0UL)
+     )
+  {
+    /* Particular case of continuous auto-injection mode combined with        */
+    /* auto-delay mode.                                                       */
+    /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
+    /* injected group stop ADC_CR_JADSTP).                                    */
+    /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1   */
+    /* (see reference manual).                                                */
+    if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
+        && (hadc->Init.ContinuousConvMode == ENABLE)
+        && (hadc->Init.LowPowerAutoWait == ENABLE)
+       )
+    {
+      /* Use stop of regular group */
+      conversion_group_reassigned = ADC_REGULAR_GROUP;
+
+      /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
+      while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
+      {
+        if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+        Conversion_Timeout_CPU_cycles ++;
+      }
+
+      /* Clear JEOS */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
+    }
+
+    /* Stop potential conversion on going on ADC group regular */
+    if (conversion_group_reassigned != ADC_INJECTED_GROUP)
+    {
+      /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+      if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+      {
+        if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+        {
+          /* Stop ADC group regular conversion */
+          LL_ADC_REG_StopConversion(hadc->Instance);
+        }
+      }
+    }
+
+    /* Stop potential conversion on going on ADC group injected */
+    if (conversion_group_reassigned != ADC_REGULAR_GROUP)
+    {
+      /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
+      if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+      {
+        if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+        {
+          /* Stop ADC group injected conversion */
+          LL_ADC_INJ_StopConversion(hadc->Instance);
+        }
+      }
+    }
+
+    /* Selection of start and stop bits with respect to the regular or injected group */
+    switch (conversion_group_reassigned)
+    {
+      case ADC_REGULAR_INJECTED_GROUP:
+        tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
+        break;
+      case ADC_INJECTED_GROUP:
+        tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
+        break;
+      /* Case ADC_REGULAR_GROUP only*/
+      default:
+        tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
+        break;
+    }
+
+    /* Wait for conversion effectively stopped */
+    tickstart = HAL_GetTick();
+
+    while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+  }
+
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC must be disabled
+  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
+{
+  uint32_t tickstart;
+
+  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
+  /* enabling phase not yet completed: flag ADC ready not yet set).           */
+  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
+  /* causes: ADC clock not running, ...).                                     */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    /* Check if conditions to enable the ADC are fulfilled */
+    if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+                               | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+      /* Set ADC error code to ADC peripheral internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+      return HAL_ERROR;
+    }
+
+    /* Enable the ADC peripheral */
+    LL_ADC_Enable(hadc->Instance);
+
+    /* Wait for ADC effectively enabled */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+    {
+      /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
+          has been cleared (after a calibration), ADEN bit is reset by the
+          calibration logic.
+          The workaround is to continue setting ADEN until ADRDY is becomes 1.
+          Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+          4 ADC clock cycle duration */
+      /* Note: Test of ADC enabled required due to hardware constraint to     */
+      /*       not enable ADC if already enabled.                             */
+      if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+      {
+        LL_ADC_Enable(hadc->Instance);
+      }
+
+      if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC conversions must be
+  *         stopped.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
+{
+  uint32_t tickstart;
+  const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
+
+  /* Verification if ADC is not already disabled:                             */
+  /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
+  /*       disabled.                                                          */
+  if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+      && (tmp_adc_is_disable_on_going == 0UL)
+     )
+  {
+    /* Check if conditions to disable the ADC are fulfilled */
+    if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+    {
+      /* Disable the ADC peripheral */
+      LL_ADC_Disable(hadc->Instance);
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+    }
+    else
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+      /* Set ADC error code to ADC peripheral internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+      return HAL_ERROR;
+    }
+
+    /* Wait for ADC effectively disabled */
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+
+    while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DMA transfer complete callback.
+  * @param hdma pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Update state machine on conversion status if not in error state */
+  if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going         */
+    /* to disable interruption.                                               */
+    /* Is it the end of the regular sequence ? */
+    if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
+    {
+      /* Are conversions software-triggered ? */
+      if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+      {
+        /* Is CONT bit set ? */
+        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
+        {
+          /* CONT bit is not set, no more conversions expected */
+          CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+          if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+          {
+            SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* DMA End of Transfer interrupt was triggered but conversions sequence
+         is not over. If DMACFG is set to 0, conversions are stopped. */
+      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL)
+      {
+        /* DMACFG bit is not set, conversions are stopped. */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+        if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+        {
+          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+        }
+      }
+    }
+
+    /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  }
+  else /* DMA and-or internal error occurred */
+  {
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+    {
+      /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Call ADC DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback(hdma);
+    }
+  }
+}
+
+/**
+  * @brief  DMA half transfer complete callback.
+  * @param hdma pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ConvHalfCpltCallback(hadc);
+#else
+  HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA error callback.
+  * @param hdma pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+  /* Set ADC error code to DMA error */
+  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+  /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ErrorCallback(hadc);
+#else
+  HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c
new file mode 100644
index 0000000..c45adc4
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c
@@ -0,0 +1,2373 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_adc_ex.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Analog to Digital Converter (ADC)
+  *          peripheral:
+  *           + Peripheral Control functions
+  *          Other functions (generic functions) are available in file
+  *          "stm32g4xx_hal_adc.c".
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  [..]
+  (@) Sections "ADC peripheral features" and "How to use this driver" are
+      available in file of generic functions "stm32g4xx_hal_adc.c".
+  [..]
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADCEx ADCEx
+  * @brief ADC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+  * @{
+  */
+
+#define ADC_JSQR_FIELDS  ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
+                           ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
+                           ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))  /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */
+
+/* Fixed timeout value for ADC calibration.                                   */
+/* Values defined to be higher than worst cases: low clock frequency,         */
+/* maximum prescalers.                                                        */
+/* Ex of profile low frequency : f_ADC at f_CPU/3968 (minimum value           */
+/* considering both possible ADC clocking scheme:                             */
+/*        - ADC clock from synchronous clock with AHB prescaler 512,          */
+/*          ADC prescaler 4.                                                  */
+/*           Ratio max = 512 *4 = 2048                                        */
+/*        - ADC clock from asynchronous clock (PLLP) with prescaler 256.      */
+/*          Highest CPU clock PLL (PLLR).                                     */
+/*           Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256    */
+/*                     = 3968 )                                               */
+/* Calibration_time MAX = 81 / f_ADC                                          */
+/*                      = 81 / (f_CPU/3938) = 318978 CPU cycles               */
+#define ADC_CALIBRATION_TIMEOUT         (318978UL)   /*!< ADC calibration time-out value (unit: CPU cycles) */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
+  * @brief    Extended IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+      (+) Perform the ADC self-calibration for single or differential ending.
+      (+) Get calibration factors for single or differential ending.
+      (+) Set calibration factors for single or differential ending.
+
+      (+) Start conversion of ADC group injected.
+      (+) Stop conversion of ADC group injected.
+      (+) Poll for conversion complete on ADC group injected.
+      (+) Get result of ADC group injected channel conversion.
+      (+) Start conversion of ADC group injected and enable interruptions.
+      (+) Stop conversion of ADC group injected and disable interruptions.
+
+      (+) When multimode feature is available, start multimode and enable DMA transfer.
+      (+) Stop multimode and disable ADC DMA transfer.
+      (+) Get result of multimode conversion.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Perform an ADC automatic self-calibration
+  *         Calibration prerequisite: ADC must be disabled (execute this
+  *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+  * @param  hadc       ADC handle
+  * @param  SingleDiff Selection of single-ended or differential input
+  *         This parameter can be one of the following values:
+  *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
+  *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  __IO uint32_t wait_loop_index = 0UL;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Calibration prerequisite: ADC must be disabled. */
+
+  /* Disable the ADC (if not already disabled) */
+  tmp_hal_status = ADC_Disable(hadc);
+
+  /* Check if ADC is effectively disabled */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+
+    /* Start ADC calibration in mode single-ended or differential */
+    LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
+
+    /* Wait for calibration completion */
+    while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
+    {
+      wait_loop_index++;
+      if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_BUSY_INTERNAL,
+                          HAL_ADC_STATE_ERROR_INTERNAL);
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_BUSY_INTERNAL,
+                      HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    /* Note: No need to update variable "tmp_hal_status" here: already set    */
+    /*       to state "HAL_ERROR" by function disabling the ADC.              */
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get the calibration factor.
+  * @param hadc ADC handle.
+  * @param SingleDiff This parameter can be only:
+  *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
+  *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+  * @retval Calibration value.
+  */
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+  /* Return the selected ADC calibration value */
+  return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
+}
+
+/**
+  * @brief  Set the calibration factor to overwrite automatic conversion result.
+  *         ADC must be enabled and no conversion is ongoing.
+  * @param hadc ADC handle
+  * @param SingleDiff This parameter can be only:
+  *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
+  *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+  * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+  * @retval HAL state
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+                                                 uint32_t CalibrationFactor)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+  assert_param(IS_ADC_CALFACT(CalibrationFactor));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Verification of hardware constraints before modifying the calibration    */
+  /* factors register: ADC must be enabled, no conversion on going.           */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+  if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+      && (tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    /* Set the selected ADC calibration value */
+    LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
+  }
+  else
+  {
+    /* Update ADC state machine */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    /* Update ADC error code */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+    /* Update ADC state machine to error */
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of injected group.
+  * @note   Interruptions enabled in this function: None.
+  * @note   Case of multimode enabled when multimode feature is available:
+  *         HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
+  *         then for ADC master.
+  *         For ADC slave, ADC is enabled only (conversion is not started).
+  *         For ADC master, ADC is enabled and multimode conversion is started.
+  * @param hadc ADC handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tmp_config_injected_queue;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+  {
+    return HAL_BUSY;
+  }
+  else
+  {
+    /* In case of software trigger detection enabled, JQDIS must be set
+      (which can be done only if ADSTART and JADSTART are both cleared).
+       If JQDIS is not set at that point, returns an error
+       - since software trigger detection is disabled. User needs to
+       resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+       - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+         the queue is empty */
+    tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+    if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
+        && (tmp_config_injected_queue == 0UL)
+       )
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      return HAL_ERROR;
+    }
+
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Check if a regular conversion is ongoing */
+      if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
+      {
+        /* Reset ADC error code field related to injected conversions only */
+        CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+      }
+      else
+      {
+        /* Set ADC error code to none */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to injected group conversion results  */
+      /* - Set state bitfield related to injected operation                   */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+                        HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - if ADC instance is master or if multimode feature is not available
+        - if multimode setting is disabled (ADC instance slave in independent mode) */
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+         )
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#endif
+
+      /* Clear ADC group injected group conversion flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable conversion of injected group, if automatic injected conversion  */
+      /* is disabled.                                                           */
+      /* If software start has been selected, conversion starts immediately.    */
+      /* If external trigger has been selected, conversion will start at next   */
+      /* trigger event.                                                         */
+      /* Case of multimode enabled (when multimode feature is available):       */
+      /* if ADC is slave,                                                       */
+      /*    - ADC is enabled only (conversion is not started),                  */
+      /*    - if multimode only concerns regular conversion, ADC is enabled     */
+      /*     and conversion is started.                                         */
+      /* If ADC is master or independent,                                       */
+      /*    - ADC is enabled and conversion is started.                         */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+         )
+      {
+        /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+        if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+        {
+          LL_ADC_INJ_StartConversion(hadc->Instance);
+        }
+      }
+      else
+      {
+        /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#else
+      if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+      {
+        /* Start ADC group injected conversion */
+        LL_ADC_INJ_StartConversion(hadc->Instance);
+      }
+#endif
+
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+
+    /* Return function status */
+    return tmp_hal_status;
+  }
+}
+
+/**
+  * @brief  Stop conversion of injected channels. Disable ADC peripheral if
+  *         no regular conversion is on going.
+  * @note   If ADC must be disabled and if conversion is on going on
+  *         regular group, function HAL_ADC_Stop must be used to stop both
+  *         injected and regular groups, and disable the ADC.
+  * @note   If injected group mode auto-injection is enabled,
+  *         function HAL_ADC_Stop must be used.
+  * @note   In case of multimode enabled (when multimode feature is available),
+  *         HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
+  *         For ADC master, conversion is stopped and ADC is disabled.
+  *         For ADC slave, ADC is disabled only (conversion stop of ADC master
+  *         has already stopped conversion of ADC slave).
+  * @param hadc ADC handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going on injected group only. */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if injected conversions are effectively stopped   */
+  /* and if no conversion on regular group is on-going                       */
+  if (tmp_hal_status == HAL_OK)
+  {
+    if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      /* 2. Disable the ADC peripheral */
+      tmp_hal_status = ADC_Disable(hadc);
+
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    /* Conversion on injected group is stopped, but ADC not disabled since    */
+    /* conversion on regular group is still running.                          */
+    else
+    {
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Wait for injected group conversion to be completed.
+  * @param hadc ADC handle
+  * @param Timeout Timeout value in millisecond.
+  * @note   Depending on hadc->Init.EOCSelection, JEOS or JEOC is
+  *         checked and cleared depending on AUTDLY bit status.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t tmp_Flag_End;
+  uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+  uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+  uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* If end of sequence selected */
+  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+  {
+    tmp_Flag_End = ADC_FLAG_JEOS;
+  }
+  else /* end of conversion selected */
+  {
+    tmp_Flag_End = ADC_FLAG_JEOC;
+  }
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  /* Wait until End of Conversion or Sequence flag is raised */
+  while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Retrieve ADC configuration */
+  tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+  tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+  /* Get relevant register CFGR in ADC instance of ADC master or slave  */
+  /* in function of multimode state (for devices with multimode         */
+  /* available).                                                        */
+#if defined(ADC_MULTIMODE_SUPPORT)
+  if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+      || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+      || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+      || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+     )
+  {
+    tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+  }
+  else
+  {
+    tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+    tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+  }
+#else
+  tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif
+
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+  /* Determine whether any further conversion upcoming on group injected      */
+  /* by external trigger or by automatic injected conversion                  */
+  /* from group regular.                                                      */
+  if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL)            ||
+      ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL)      &&
+       ((tmp_adc_reg_is_trigger_source_sw_start != 0UL)  &&
+        (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+  {
+    /* Check whether end of sequence is reached */
+    if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+    {
+      /* Particular case if injected contexts queue is enabled:             */
+      /* when the last context has been fully processed, JSQR is reset      */
+      /* by the hardware. Even if no injected conversion is planned to come */
+      /* (queue empty, triggers are ignored), it can start again            */
+      /* immediately after setting a new context (JADSTART is still set).   */
+      /* Therefore, state of HAL ADC injected group is kept to busy.        */
+      if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+      {
+        /* Set ADC state */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+        if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+        {
+          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+        }
+      }
+    }
+  }
+
+  /* Clear polled flag */
+  if (tmp_Flag_End == ADC_FLAG_JEOS)
+  {
+    /* Clear end of sequence JEOS flag of injected group if low power feature */
+    /* "LowPowerAutoWait " is disabled, to not interfere with this feature.   */
+    /* For injected groups, no new conversion will start before JEOS is       */
+    /* cleared.                                                               */
+    if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
+    {
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+    }
+  }
+  else
+  {
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+  }
+
+  /* Return API HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of injected group with interruption.
+  * @note   Interruptions enabled in this function according to initialization
+  *         setting : JEOC (end of conversion) or JEOS (end of sequence)
+  * @note   Case of multimode enabled (when multimode feature is enabled):
+  *         HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
+  *         then for ADC master.
+  *         For ADC slave, ADC is enabled only (conversion is not started).
+  *         For ADC master, ADC is enabled and multimode conversion is started.
+  * @param hadc ADC handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tmp_config_injected_queue;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+  {
+    return HAL_BUSY;
+  }
+  else
+  {
+    /* In case of software trigger detection enabled, JQDIS must be set
+      (which can be done only if ADSTART and JADSTART are both cleared).
+       If JQDIS is not set at that point, returns an error
+       - since software trigger detection is disabled. User needs to
+       resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+       - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+         the queue is empty */
+    tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+    if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
+        && (tmp_config_injected_queue == 0UL)
+       )
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      return HAL_ERROR;
+    }
+
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Check if a regular conversion is ongoing */
+      if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
+      {
+        /* Reset ADC error code field related to injected conversions only */
+        CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+      }
+      else
+      {
+        /* Set ADC error code to none */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to injected group conversion results  */
+      /* - Set state bitfield related to injected operation                   */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+                        HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - if ADC instance is master or if multimode feature is not available
+        - if multimode setting is disabled (ADC instance slave in independent mode) */
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+         )
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#endif
+
+      /* Clear ADC group injected group conversion flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable ADC Injected context queue overflow interrupt if this feature   */
+      /* is enabled.                                                            */
+      if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
+      {
+        __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
+      }
+
+      /* Enable ADC end of conversion interrupt */
+      switch (hadc->Init.EOCSelection)
+      {
+        case ADC_EOC_SEQ_CONV:
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+          break;
+        /* case ADC_EOC_SINGLE_CONV */
+        default:
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+          break;
+      }
+
+      /* Enable conversion of injected group, if automatic injected conversion  */
+      /* is disabled.                                                           */
+      /* If software start has been selected, conversion starts immediately.    */
+      /* If external trigger has been selected, conversion will start at next   */
+      /* trigger event.                                                         */
+      /* Case of multimode enabled (when multimode feature is available):       */
+      /* if ADC is slave,                                                       */
+      /*    - ADC is enabled only (conversion is not started),                  */
+      /*    - if multimode only concerns regular conversion, ADC is enabled     */
+      /*     and conversion is started.                                         */
+      /* If ADC is master or independent,                                       */
+      /*    - ADC is enabled and conversion is started.                         */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+         )
+      {
+        /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+        if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+        {
+          LL_ADC_INJ_StartConversion(hadc->Instance);
+        }
+      }
+      else
+      {
+        /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#else
+      if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+      {
+        /* Start ADC group injected conversion */
+        LL_ADC_INJ_StartConversion(hadc->Instance);
+      }
+#endif
+
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+
+    /* Return function status */
+    return tmp_hal_status;
+  }
+}
+
+/**
+  * @brief  Stop conversion of injected channels, disable interruption of
+  *         end-of-conversion. Disable ADC peripheral if no regular conversion
+  *         is on going.
+  * @note   If ADC must be disabled and if conversion is on going on
+  *         regular group, function HAL_ADC_Stop must be used to stop both
+  *         injected and regular groups, and disable the ADC.
+  * @note   If injected group mode auto-injection is enabled,
+  *         function HAL_ADC_Stop must be used.
+  * @note   Case of multimode enabled (when multimode feature is available):
+  *         HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
+  *         then for ADC slave.
+  *         For ADC master, conversion is stopped and ADC is disabled.
+  *         For ADC slave, ADC is disabled only (conversion stop of ADC master
+  *         has already stopped conversion of ADC slave).
+  * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going on injected group only. */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if injected conversions are effectively stopped   */
+  /* and if no conversion on the other group (regular group) is intended to   */
+  /* continue.                                                                */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC end of conversion interrupt for injected channels */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
+
+    if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      /* 2. Disable the ADC peripheral */
+      tmp_hal_status = ADC_Disable(hadc);
+
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    /* Conversion on injected group is stopped, but ADC not disabled since    */
+    /* conversion on regular group is still running.                          */
+    else
+    {
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Enable ADC, start MultiMode conversion and transfer regular results through DMA.
+  * @note   Multimode must have been previously configured using
+  *         HAL_ADCEx_MultiModeConfigChannel() function.
+  *         Interruptions enabled in this function:
+  *          overrun, DMA half transfer, DMA transfer complete.
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   State field of Slave ADC handle is not updated in this configuration:
+  *          user should not rely on it for information related to Slave regular
+  *         conversions.
+  * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+  * @param pData Destination Buffer address.
+  * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  ADC_HandleTypeDef tmphadcSlave;
+  ADC_Common_TypeDef *tmpADC_Common;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+  {
+    return HAL_BUSY;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Temporary handle minimum initialization */
+    __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+    ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
+    /* Set a temporary handle of the ADC slave associated to the ADC master   */
+    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+    if (tmphadcSlave.Instance == NULL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+
+      return HAL_ERROR;
+    }
+
+    /* Enable the ADC peripherals: master and slave (in case if not already   */
+    /* enabled previously)                                                    */
+    tmp_hal_status = ADC_Enable(hadc);
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmp_hal_status = ADC_Enable(&tmphadcSlave);
+    }
+
+    /* Start multimode conversion of ADCs pair */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
+                        HAL_ADC_STATE_REG_BUSY);
+
+      /* Set ADC error code to none */
+      ADC_CLEAR_ERRORCODE(hadc);
+
+      /* Set the DMA transfer complete callback */
+      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+      /* Set the DMA half transfer complete callback */
+      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+      /* Set the DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
+
+      /* Pointer to the common control register  */
+      tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+      /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
+      /* start (in case of SW start):                                           */
+
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable ADC overrun interrupt */
+      __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+      /* Start the DMA channel */
+      tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
+
+      /* Enable conversion of regular group.                                    */
+      /* If software start has been selected, conversion starts immediately.    */
+      /* If external trigger has been selected, conversion will start at next   */
+      /* trigger event.                                                         */
+      /* Start ADC group regular conversion */
+      LL_ADC_REG_StartConversion(hadc->Instance);
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+
+    /* Return function status */
+    return tmp_hal_status;
+  }
+}
+
+/**
+  * @brief  Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
+  * @note   Multimode is kept enabled after this function. MultiMode DMA bits
+  *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+  *         Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+  *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+  *         resort to HAL_ADCEx_DisableMultiMode() API.
+  * @note   In case of DMA configured in circular mode, function
+  *         HAL_ADC_Stop_DMA() must be called after this function with handle of
+  *         ADC slave, to properly disable the DMA channel.
+  * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tickstart;
+  ADC_HandleTypeDef tmphadcSlave;
+  uint32_t tmphadcSlave_conversion_on_going;
+  HAL_StatusTypeDef tmphadcSlave_disable_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+
+  /* 1. Stop potential multimode conversion on going, on regular and injected groups */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Temporary handle minimum initialization */
+    __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+    ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
+    /* Set a temporary handle of the ADC slave associated to the ADC master   */
+    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+    if (tmphadcSlave.Instance == NULL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+
+      return HAL_ERROR;
+    }
+
+    /* Procedure to disable the ADC peripheral: wait for conversions          */
+    /* effectively stopped (ADC master and ADC slave), then disable ADC       */
+
+    /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+    tickstart = HAL_GetTick();
+
+    tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+    while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+           || (tmphadcSlave_conversion_on_going == 1UL)
+          )
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+        if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+            || (tmphadcSlave_conversion_on_going == 1UL)
+           )
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_ERROR;
+        }
+      }
+
+      tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+    }
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    /* Note: DMA channel of ADC slave should be stopped after this function   */
+    /*       with HAL_ADC_Stop_DMA() API.                                     */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status == HAL_ERROR)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripherals: master and slave */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+    /* memory a potential failing status.                                     */
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
+      if ((ADC_Disable(hadc) == HAL_OK)           &&
+          (tmphadcSlave_disable_status == HAL_OK))
+      {
+        tmp_hal_status = HAL_OK;
+      }
+    }
+    else
+    {
+      /* In case of error, attempt to disable ADC master and slave without status assert */
+      (void) ADC_Disable(hadc);
+      (void) ADC_Disable(&tmphadcSlave);
+    }
+
+    /* Set ADC state (ADC master) */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_READY);
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Return the last ADC Master and Slave regular conversions results when in multimode configuration.
+  * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
+  * @retval The converted data values.
+  */
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
+{
+  const ADC_Common_TypeDef *tmpADC_Common;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below               */
+  UNUSED(hadc);
+
+  /* Pointer to the common control register  */
+  tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+  /* Return the multi mode conversion value */
+  return tmpADC_Common->CDR;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Get ADC injected group conversion result.
+  * @note   Reading register JDRx automatically clears ADC flag JEOC
+  *         (ADC group injected end of unitary conversion).
+  * @note   This function does not clear ADC flag JEOS
+  *         (ADC group injected end of sequence conversion)
+  *         Occurrence of flag JEOS rising:
+  *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
+  *            to flag JEOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag JEOC only is raised, at the end of the scan sequence
+  *            both flags JEOC and EOS are raised.
+  *         Flag JEOS must not be cleared by this function because
+  *         it would not be compliant with low power features
+  *         (feature low power auto-wait, not available on all STM32 families).
+  *         To clear this flag, either use function:
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+  * @param hadc ADC handle
+  * @param InjectedRank the converted ADC injected rank.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
+  *            @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
+  *            @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
+  *            @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
+  * @retval ADC group injected conversion data
+  */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
+{
+  uint32_t tmp_jdr;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+  /* Get ADC converted value */
+  switch (InjectedRank)
+  {
+    case ADC_INJECTED_RANK_4:
+      tmp_jdr = hadc->Instance->JDR4;
+      break;
+    case ADC_INJECTED_RANK_3:
+      tmp_jdr = hadc->Instance->JDR3;
+      break;
+    case ADC_INJECTED_RANK_2:
+      tmp_jdr = hadc->Instance->JDR2;
+      break;
+    case ADC_INJECTED_RANK_1:
+    default:
+      tmp_jdr = hadc->Instance->JDR1;
+      break;
+  }
+
+  /* Return ADC converted value */
+  return tmp_jdr;
+}
+
+/**
+  * @brief  Injected conversion complete callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Injected context queue overflow callback.
+  * @note   This callback is called if injected context queue is enabled
+            (parameter "QueueInjectedContext" in injected channel configuration)
+            and if a new injected context is set when queue is full (maximum 2
+            contexts).
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 2 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 3 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
+  */
+}
+
+
+/**
+  * @brief  End Of Sampling callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected channels in
+  *         case of auto_injection mode), disable ADC peripheral if no
+  *         conversion is on going on injected group.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+  /* Disable ADC peripheral if regular conversions are effectively stopped
+     and if no injected conversions are on-going */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+    if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      /* 2. Disable the ADC peripheral */
+      tmp_hal_status = ADC_Disable(hadc);
+
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    /* Conversion on injected group is stopped, but ADC not disabled since    */
+    /* conversion on regular group is still running.                          */
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+/**
+  * @brief  Stop ADC conversion of ADC groups regular and injected,
+  *         disable interrution of end-of-conversion,
+  *         disable ADC peripheral if no conversion is on going
+  *         on injected group.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped
+    and if no injected conversion is on-going */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+    /* Disable all regular-related interrupts */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+    /* 2. Disable ADC peripheral if no injected conversions are on-going */
+    if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      tmp_hal_status = ADC_Disable(hadc);
+      /* if no issue reported */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable ADC DMA transfer, disable
+  *         ADC peripheral if no conversion is on going
+  *         on injected group.
+  * @note   HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
+  *         For multimode (when multimode feature is available),
+  *         HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped
+     and if no injected conversion is on-going */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+    /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+    CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+    /* while DMA transfer is on going)                                        */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status != HAL_OK)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripheral */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
+    /* to keep in memory a potential failing status.                          */
+    if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      if (tmp_hal_status == HAL_OK)
+      {
+        tmp_hal_status = ADC_Disable(hadc);
+      }
+      else
+      {
+        (void)ADC_Disable(hadc);
+      }
+
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
+  * @note   Multimode is kept enabled after this function. Multimode DMA bits
+  *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+  *         multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+  *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+  *         resort to HAL_ADCEx_DisableMultiMode() API.
+  * @note   In case of DMA configured in circular mode, function
+  *         HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
+  *         ADC slave, to properly disable the DMA channel.
+  * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tickstart;
+  ADC_HandleTypeDef tmphadcSlave;
+  uint32_t tmphadcSlave_conversion_on_going;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+
+  /* 1. Stop potential multimode conversion on going, on regular groups */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+    /* Temporary handle minimum initialization */
+    __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+    ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
+    /* Set a temporary handle of the ADC slave associated to the ADC master   */
+    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+    if (tmphadcSlave.Instance == NULL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+
+      return HAL_ERROR;
+    }
+
+    /* Procedure to disable the ADC peripheral: wait for conversions          */
+    /* effectively stopped (ADC master and ADC slave), then disable ADC       */
+
+    /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+    tickstart = HAL_GetTick();
+
+    tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+    while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+           || (tmphadcSlave_conversion_on_going == 1UL)
+          )
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+        if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+            || (tmphadcSlave_conversion_on_going == 1UL)
+           )
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_ERROR;
+        }
+      }
+
+      tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+    }
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    /* Note: DMA channel of ADC slave should be stopped after this function   */
+    /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status != HAL_OK)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripherals: master and slave if no injected        */
+    /*   conversion is on-going.                                              */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+    /* memory a potential failing status.                                     */
+    if (tmp_hal_status == HAL_OK)
+    {
+      if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+      {
+        tmp_hal_status =  ADC_Disable(hadc);
+        if (tmp_hal_status == HAL_OK)
+        {
+          if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL)
+          {
+            tmp_hal_status =  ADC_Disable(&tmphadcSlave);
+          }
+        }
+      }
+
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Both Master and Slave ADC's could be disabled. Update Master State */
+        /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+      }
+      else
+      {
+        /* injected (Master or Slave) conversions are still on-going,
+           no Master State change */
+      }
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
+  * @brief    ADC Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure channels on injected group
+      (+) Configure multimode when multimode feature is available
+      (+) Enable or Disable Injected Queue
+      (+) Disable ADC voltage regulator
+      (+) Enter ADC deep-power-down mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure a channel to be assigned to ADC group injected.
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes injected group, following calls to this
+  *         function can be used to reconfigure some parameters of structure
+  *         "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
+  *         The setting of these parameters is conditioned to ADC state:
+  *         Refer to comments of structure "ADC_InjectionConfTypeDef".
+  * @note   In case of usage of internal measurement channels:
+  *         Vbat/VrefInt/TempSensor.
+  *         These internal paths can be disabled using function
+  *         HAL_ADC_DeInit().
+  * @note   Caution: For Injected Context Queue use, a context must be fully
+  *         defined before start of injected conversion. All channels are configured
+  *         consecutively for the same ADC instance. Therefore, the number of calls to
+  *         HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
+  *         InjectedNbrOfConversion for each context.
+  *  - Example 1: If 1 context is intended to be used (or if there is no use of the
+  *    Injected Queue Context feature) and if the context contains 3 injected ranks
+  *    (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
+  *    called once for each channel (i.e. 3 times) before starting a conversion.
+  *    This function must not be called to configure a 4th injected channel:
+  *    it would start a new context into context queue.
+  *  - Example 2: If 2 contexts are intended to be used and each of them contains
+  *    3 injected ranks (InjectedNbrOfConversion = 3),
+  *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
+  *    for each context (3 channels x 2 contexts = 6 calls). Conversion can
+  *    start once the 1st context is set, that is after the first three
+  *    HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
+  * @param hadc ADC handle
+  * @param sConfigInjected Structure of ADC injected group and ADC channel for
+  *         injected group.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmpOffsetShifted;
+  uint32_t tmp_config_internal_channel;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+  __IO uint32_t wait_loop_index = 0;
+
+  uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
+  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
+  assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+  assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv));
+  assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
+  assert_param(IS_ADC_OFFSET_SIGN(sConfigInjected->InjectedOffsetSign));
+  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedOffsetSaturation));
+  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
+
+  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+  {
+    assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+    assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
+    assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+  }
+
+
+  /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+     ignored (considered as reset) */
+  assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE)));
+
+  /* JDISCEN and JAUTO bits can't be set at the same time  */
+  assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
+
+  /*  DISCEN and JAUTO bits can't be set at the same time */
+  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
+
+  /* Verification of channel number */
+  if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
+  {
+    assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
+  }
+  else
+  {
+    assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Configuration of injected group sequencer:                               */
+  /* Hardware constraint: Must fully define injected context register JSQR    */
+  /* before make it entering into injected sequencer queue.                   */
+  /*                                                                          */
+  /* - if scan mode is disabled:                                              */
+  /*    * Injected channels sequence length is set to 0x00: 1 channel         */
+  /*      converted (channel on injected rank 1)                              */
+  /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
+  /*    * Injected context register JSQR setting is simple: register is fully */
+  /*      defined on one call of this function (for injected rank 1) and can  */
+  /*      be entered into queue directly.                                     */
+  /* - if scan mode is enabled:                                               */
+  /*    * Injected channels sequence length is set to parameter               */
+  /*      "InjectedNbrOfConversion".                                          */
+  /*    * Injected context register JSQR setting more complex: register is    */
+  /*      fully defined over successive calls of this function, for each      */
+  /*      injected channel rank. It is entered into queue only when all       */
+  /*      injected ranks have been set.                                       */
+  /*   Note: Scan mode is not present by hardware on this device, but used    */
+  /*   by software for alignment over all STM32 devices.                      */
+
+  if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
+      (sConfigInjected->InjectedNbrOfConversion == 1U))
+  {
+    /* Configuration of context register JSQR:                                */
+    /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
+    /*    (scan mode disabled, only rank 1 used)                              */
+    /*  - external trigger to start conversion                                */
+    /*  - external trigger polarity                                           */
+    /*  - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
+
+    if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+    {
+      /* Enable external trigger if trigger selection is different of         */
+      /* software start.                                                      */
+      /* Note: This configuration keeps the hardware feature of parameter     */
+      /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
+      /*       software start.                                                */
+      if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+      {
+        tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
+                                           | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
+                                           | sConfigInjected->ExternalTrigInjecConvEdge
+                                          );
+      }
+      else
+      {
+        tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
+      }
+
+      MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
+      /* For debug and informative reasons, hadc handle saves JSQR setting */
+      hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
+
+    }
+  }
+  else
+  {
+    /* Case of scan mode enabled, several channels to set into injected group */
+    /* sequencer.                                                             */
+    /*                                                                        */
+    /* Procedure to define injected context register JSQR over successive     */
+    /* calls of this function, for each injected channel rank:                */
+    /* 1. Start new context and set parameters related to all injected        */
+    /*    channels: injected sequence length and trigger.                     */
+
+    /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
+    /*   call of the context under setting                                    */
+    if (hadc->InjectionConfig.ChannelCount == 0U)
+    {
+      /* Initialize number of channels that will be configured on the context */
+      /*  being built                                                         */
+      hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
+      /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
+         call, this context will be written in JSQR register at the last call.
+         At this point, the context is merely reset  */
+      hadc->InjectionConfig.ContextQueue = 0x00000000U;
+
+      /* Configuration of context register JSQR:                              */
+      /*  - number of ranks in injected group sequencer                       */
+      /*  - external trigger to start conversion                              */
+      /*  - external trigger polarity                                         */
+
+      /* Enable external trigger if trigger selection is different of         */
+      /* software start.                                                      */
+      /* Note: This configuration keeps the hardware feature of parameter     */
+      /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
+      /*       software start.                                                */
+      if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+      {
+        tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)
+                                           | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
+                                           | sConfigInjected->ExternalTrigInjecConvEdge
+                                          );
+      }
+      else
+      {
+        tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U));
+      }
+
+    }
+
+    /* 2. Continue setting of context under definition with parameter       */
+    /*    related to each channel: channel rank sequence                    */
+    /* Clear the old JSQx bits for the selected rank */
+    tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
+
+    /* Set the JSQx bits for the selected rank */
+    tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
+
+    /* Decrease channel count  */
+    hadc->InjectionConfig.ChannelCount--;
+
+    /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
+          call, aggregate the setting to those already built during the previous
+          HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course)  */
+    hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
+
+    /* 4. End of context setting: if this is the last channel set, then write context
+        into register JSQR and make it enter into queue                   */
+    if (hadc->InjectionConfig.ChannelCount == 0U)
+    {
+      MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
+    }
+  }
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on injected group:                                   */
+  /*  - Injected context queue: Queue disable (active context is kept) or     */
+  /*    enable (context decremented, up to 2 contexts queued)                 */
+  /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
+  /*    mode is disabled.                                                     */
+  if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* If auto-injected mode is disabled: no constraint                       */
+    if (sConfigInjected->AutoInjectedConv == DISABLE)
+    {
+      MODIFY_REG(hadc->Instance->CFGR,
+                 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
+                 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext)           |
+                 ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode));
+    }
+    /* If auto-injected mode is enabled: Injected discontinuous setting is    */
+    /* discarded.                                                             */
+    else
+    {
+      MODIFY_REG(hadc->Instance->CFGR,
+                 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
+                 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext));
+    }
+
+  }
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular and injected groups:                      */
+  /*  - Automatic injected conversion: can be enabled if injected group       */
+  /*    external triggers are disabled.                                       */
+  /*  - Channel sampling time                                                 */
+  /*  - Channel offset                                                        */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+  if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    /* If injected group external triggers are disabled (set to injected      */
+    /* software start): no constraint                                         */
+    if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+        || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
+    {
+      if (sConfigInjected->AutoInjectedConv == ENABLE)
+      {
+        SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+      }
+      else
+      {
+        CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+      }
+    }
+    /* If Automatic injected conversion was intended to be set and could not  */
+    /* due to injected group external triggers enabled, error is reported.    */
+    else
+    {
+      if (sConfigInjected->AutoInjectedConv == ENABLE)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+        tmp_hal_status = HAL_ERROR;
+      }
+      else
+      {
+        CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+      }
+    }
+
+    if (sConfigInjected->InjecOversamplingMode == ENABLE)
+    {
+      assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
+      assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
+
+      /*  JOVSE must be reset in case of triggered regular mode  */
+      assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
+
+      /* Configuration of Injected Oversampler:                                 */
+      /*  - Oversampling Ratio                                                  */
+      /*  - Right bit shift                                                     */
+
+      /* Enable OverSampling mode */
+      MODIFY_REG(hadc->Instance->CFGR2,
+                 ADC_CFGR2_JOVSE |
+                 ADC_CFGR2_OVSR  |
+                 ADC_CFGR2_OVSS,
+                 ADC_CFGR2_JOVSE                                  |
+                 sConfigInjected->InjecOversampling.Ratio         |
+                 sConfigInjected->InjecOversampling.RightBitShift
+                );
+    }
+    else
+    {
+      /* Disable Regular OverSampling */
+      CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
+    }
+
+    /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
+    if (sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
+    {
+      /* Set sampling time of the selected ADC channel */
+      LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
+
+      /* Set ADC sampling time common configuration */
+      LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
+    }
+    else
+    {
+      /* Set sampling time of the selected ADC channel */
+      LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
+
+      /* Set ADC sampling time common configuration */
+      LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
+    }
+
+    /* Configure the offset: offset enable/disable, channel, offset value */
+
+    /* Shift the offset with respect to the selected ADC resolution. */
+    /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+    tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
+
+    if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
+    {
+      /* Set ADC selected offset number */
+      LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel,
+                       tmpOffsetShifted);
+
+      /* Set ADC selected offset sign & saturation */
+      LL_ADC_SetOffsetSign(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedOffsetSign);
+      LL_ADC_SetOffsetSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber,
+                                 (sConfigInjected->InjectedOffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
+    }
+    else
+    {
+      /* Scan each offset register to check if the selected channel is targeted. */
+      /* If this is the case, the corresponding offset number is disabled.       */
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+          == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+      {
+        LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
+      }
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+          == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+      {
+        LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
+      }
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+          == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+      {
+        LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
+      }
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+          == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+      {
+        LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
+      }
+    }
+
+  }
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated only when ADC is disabled:                */
+  /*  - Single or differential mode                                           */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    /* Set mode single-ended or differential input of the selected ADC channel */
+    LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff);
+
+    /* Configuration of differential mode */
+    /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
+    if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
+    {
+      /* Set sampling time of the selected ADC channel */
+      LL_ADC_SetChannelSamplingTime(hadc->Instance,
+                                    (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel)
+                                                                               + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
+    }
+
+  }
+
+  /* Management of internal measurement channels: Vbat/VrefInt/TempSensor   */
+  /* internal measurement paths enable: If internal channel selected,       */
+  /* enable dedicated internal buffers and path.                            */
+  /* Note: these internal measurement paths can be disabled using           */
+  /* HAL_ADC_DeInit().                                                      */
+
+  if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
+  {
+    tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+    /* If the requested internal measurement path has already been enabled,   */
+    /* bypass the configuration processing.                                   */
+    if (((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC1)
+         || (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC5))
+        && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+    {
+      if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+      {
+        LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                       LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+        /* Delay for temperature sensor stabilization time */
+        /* Wait loop initialization and execution */
+        /* Note: Variable divided by 2 to compensate partially              */
+        /*       CPU processing cycles, scaling in us split to not          */
+        /*       exceed 32 bits register capacity and handle low frequency. */
+        wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
+        while (wait_loop_index != 0UL)
+        {
+          wait_loop_index--;
+        }
+      }
+    }
+    else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
+             && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+    {
+      if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+      {
+        LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                       LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+      }
+    }
+    else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
+             && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+    {
+      if (ADC_VREFINT_INSTANCE(hadc))
+      {
+        LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                       LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+      }
+    }
+    else
+    {
+      /* nothing to do */
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Enable ADC multimode and configure multimode parameters
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes multimode parameters, following
+  *         calls to this function can be used to reconfigure some parameters
+  *         of structure "ADC_MultiModeTypeDef" on the fly, without resetting
+  *         the ADCs.
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure
+  *         "ADC_MultiModeTypeDef".
+  * @note   To move back configuration from multimode to single mode, ADC must
+  *         be reset (using function HAL_ADC_Init() ).
+  * @param hadc Master ADC handle
+  * @param multimode Structure of ADC multimode configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  ADC_Common_TypeDef *tmpADC_Common;
+  ADC_HandleTypeDef tmphadcSlave;
+  uint32_t tmphadcSlave_conversion_on_going;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_MULTIMODE(multimode->Mode));
+  if (multimode->Mode != ADC_MODE_INDEPENDENT)
+  {
+    assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
+    assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Temporary handle minimum initialization */
+  __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+  ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
+  ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+  if (tmphadcSlave.Instance == NULL)
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hadc);
+
+    return HAL_ERROR;
+  }
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Multimode DMA configuration                                           */
+  /*  - Multimode DMA mode                                                    */
+  tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+  if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+      && (tmphadcSlave_conversion_on_going == 0UL))
+  {
+    /* Pointer to the common control register */
+    tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+    /* If multimode is selected, configure all multimode parameters.          */
+    /* Otherwise, reset multimode parameters (can be used in case of          */
+    /* transition from multimode to independent mode).                        */
+    if (multimode->Mode != ADC_MODE_INDEPENDENT)
+    {
+      MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
+                 multimode->DMAAccessMode |
+                 ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+
+      /* Parameters that can be updated only when ADC is disabled:                */
+      /*  - Multimode mode selection                                              */
+      /*  - Multimode delay                                                       */
+      /*    Note: Delay range depends on selected resolution:                     */
+      /*      from 1 to 12 clock cycles for 12 bits                               */
+      /*      from 1 to 10 clock cycles for 10 bits,                              */
+      /*      from 1 to 8 clock cycles for 8 bits                                 */
+      /*      from 1 to 6 clock cycles for 6 bits                                 */
+      /*    If a higher delay is selected, it will be clipped to maximum delay    */
+      /*    range                                                                 */
+      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+      {
+        MODIFY_REG(tmpADC_Common->CCR,
+                   ADC_CCR_DUAL |
+                   ADC_CCR_DELAY,
+                   multimode->Mode |
+                   multimode->TwoSamplingDelay
+                  );
+      }
+    }
+    else /* ADC_MODE_INDEPENDENT */
+    {
+      CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
+
+      /* Parameters that can be updated only when ADC is disabled:                */
+      /*  - Multimode mode selection                                              */
+      /*  - Multimode delay                                                       */
+      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+      {
+        CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
+      }
+    }
+  }
+  /* If one of the ADC sharing the same common group is enabled, no update    */
+  /* could be done on neither of the multimode structure parameters.          */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Enable Injected Queue
+  * @note   This function resets CFGR register JQDIS bit in order to enable the
+  *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+  *         are both equal to 0 to ensure that no regular nor injected
+  *         conversion is ongoing.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+  /* Parameter can be set only if no conversion is on-going */
+  if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+    /* Update state, clear previous result related to injected queue overflow */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+    tmp_hal_status = HAL_OK;
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Disable Injected Queue
+  * @note   This function sets CFGR register JQDIS bit in order to disable the
+  *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+  *         are both equal to 0 to ensure that no regular nor injected
+  *         conversion is ongoing.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+  /* Parameter can be set only if no conversion is on-going */
+  if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
+    tmp_hal_status = HAL_OK;
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Disable ADC voltage regulator.
+  * @note   Disabling voltage regulator allows to save power. This operation can
+  *         be carried out only when ADC is disabled.
+  * @note   To enable again the voltage regulator, the user is expected to
+  *         resort to HAL_ADC_Init() API.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    LL_ADC_DisableInternalRegulator(hadc->Instance);
+    tmp_hal_status = HAL_OK;
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enter ADC deep-power-down mode
+  * @note   This mode is achieved in setting DEEPPWD bit and allows to save power
+  *         in reducing leakage currents. It is particularly interesting before
+  *         entering stop modes.
+  * @note   Setting DEEPPWD automatically clears ADVREGEN bit and disables the
+  *         ADC voltage regulator. This means that this API encompasses
+  *         HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
+  *         calibration is lost.
+  * @note   To exit the ADC deep-power-down mode, the user is expected to
+  *         resort to HAL_ADC_Init() API as well as to relaunch a calibration
+  *         with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
+  *         saved calibration factor.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    LL_ADC_EnableDeepPowerDown(hadc->Instance);
+    tmp_hal_status = HAL_OK;
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c
new file mode 100644
index 0000000..d53ee2c
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c
@@ -0,0 +1,517 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the CORTEX:
+  *           + Initialization and Configuration functions
+  *           + Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M4 exceptions are managed by CMSIS functions.
+
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+         The pending IRQ priority will be managed only by the sub priority.
+
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest pre-emption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+
+    [..]
+    *** How to configure SysTick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+       inside the stm32g4xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+
+  @endverbatim
+  ******************************************************************************
+
+  The table below gives the allowed values of the pre-emption priority and subpriority according
+  to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
+  
+    ==========================================================================================================================
+      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
+    ==========================================================================================================================
+     NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bit for pre-emption priority
+                           |                                   |                             | 4 bits for subpriority
+    --------------------------------------------------------------------------------------------------------------------------
+     NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bit for pre-emption priority
+                           |                                   |                             | 3 bits for subpriority
+    --------------------------------------------------------------------------------------------------------------------------    
+     NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
+                           |                                   |                             | 2 bits for subpriority
+    --------------------------------------------------------------------------------------------------------------------------    
+     NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
+                           |                                   |                             | 1 bit for subpriority
+    --------------------------------------------------------------------------------------------------------------------------    
+     NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
+                           |                                   |                             | 0 bit for subpriority                       
+    ==========================================================================================================================
+
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      SysTick functionalities
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Set the priority grouping field (pre-emption priority and subpriority)
+  *         using the required unlock sequence.
+  * @param  PriorityGroup: The priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bit  for pre-emption priority,
+  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bit  for pre-emption priority,
+  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+  *                                    1 bit  for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
+  *                                    0 bit  for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+  *         The pending IRQ priority will be managed only by the subpriority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+  * @brief  Set the priority of an interrupt.
+  * @param  IRQn: External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
+  * @param  PreemptPriority: The pre-emption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority
+  * @param  SubPriority: the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t prioritygroup;
+
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+  prioritygroup = NVIC_GetPriorityGrouping();
+
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+  * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiate a system reset request to reset the MCU.
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): 
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+   return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ *  @brief   Cortex control functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the priority grouping field from the NVIC Interrupt Controller.
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+  * @brief  Get the priority of an interrupt.
+  * @param  IRQn: External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
+  * @param   PriorityGroup: the priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
+  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
+  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+  *                                      1 bit for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
+  *                                      0 bit for subpriority
+  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
+  * @retval None
+  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+  * @brief  Set Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Get Pending Interrupt (read the pending register in the NVIC
+  *         and return the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *          This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clear the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief Get active interrupt (read the active register in NVIC and return the active bit).
+  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+  * @brief  Configure the SysTick clock source.
+  * @param  CLKSource: specifies the SysTick clock source.
+  *          This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+  * @brief  Handle SYSTICK interrupt request.
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+#if (__MPU_PRESENT == 1)
+/**
+  * @brief  Enable the MPU.
+  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
+  *          NMI, FAULTMASK and privileged accessto the default memory 
+  *          This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+
+
+/**
+  * @brief  Disable the MPU.
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL  = 0;
+}
+
+
+/**
+  * @brief  Initialize and configure the Region and the memory to be protected.
+  * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+
+  if ((MPU_Init->Enable) != 0U)
+  {
+    /* Check the parameters */
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+    MPU->RBAR = MPU_Init->BaseAddress;
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec        << MPU_RASR_XN_Pos)   |
+                ((uint32_t)MPU_Init->AccessPermission   << MPU_RASR_AP_Pos)   |
+                ((uint32_t)MPU_Init->TypeExtField       << MPU_RASR_TEX_Pos)  |
+                ((uint32_t)MPU_Init->IsShareable        << MPU_RASR_S_Pos)    |
+                ((uint32_t)MPU_Init->IsCacheable        << MPU_RASR_C_Pos)    |
+                ((uint32_t)MPU_Init->IsBufferable       << MPU_RASR_B_Pos)    |
+                ((uint32_t)MPU_Init->SubRegionDisable   << MPU_RASR_SRD_Pos)  |
+                ((uint32_t)MPU_Init->Size               << MPU_RASR_SIZE_Pos) |
+                ((uint32_t)MPU_Init->Enable             << MPU_RASR_ENABLE_Pos);
+  }
+  else
+  {
+    MPU->RBAR = 0x00;
+    MPU->RASR = 0x00;
+  }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c
new file mode 100644
index 0000000..a96558e
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c
@@ -0,0 +1,1110 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA HAL module driver.
+  *         This file provides firmware functions to manage the following
+  *         functionalities of the Direct Memory Access (DMA) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the DMA Channel
+       (except for internal SRAM / FLASH memories: no initialization is
+       necessary). Please refer to the Reference manual for connection between peripherals
+       and DMA requests.
+
+   (#) For a given Channel, program the required configuration through the following parameters:
+       Channel request, Transfer Direction, Source and Destination data formats,
+       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
+       using HAL_DMA_Init() function.
+
+       Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
+       thanks to:
+      (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or  __HAL_RCC_DMA2_CLK_ENABLE() ;
+      (##) DMAMUX1:      __HAL_RCC_DMAMUX1_CLK_ENABLE();
+
+   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+       detection.
+
+   (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+              address and destination address and the Length of data to be transferred
+          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+              case a fixed Timeout can be configured by User depending from his application.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+              Source address and destination address and the Length of data to be transferred.
+              In this case the DMA interrupt is configured
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+              add his own function to register callbacks with HAL_DMA_RegisterCallback().
+
+     *** DMA HAL driver macros list ***
+     =============================================
+      [..]
+       Below the list of macros in DMA HAL driver.
+
+       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
+       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
+       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
+       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
+       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
+       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
+       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
+
+     [..]
+      (@) You can refer to the DMA HAL driver header file for more useful macros
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA DMA
+  * @brief DMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @{
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief   Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to initialize the DMA Channel source
+    and destination addresses, incrementation and data sizes, transfer direction,
+    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
+    [..]
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DMA according to the specified
+  *         parameters in the DMA_InitTypeDef and initialize the associated handle.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmp;
+
+  /* Check the DMA handle allocation */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+  assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
+
+  /* Compute the channel index */
+  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
+  {
+    /* DMA1 */
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA1;
+  }
+  else
+  {
+    /* DMA2 */
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA2;
+  }
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+  /* Get the CR register value */
+  tmp = hdma->Instance->CCR;
+
+  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
+  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  |
+                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |
+                      DMA_CCR_DIR   | DMA_CCR_MEM2MEM));
+
+  /* Prepare the DMA Channel configuration */
+  tmp |=  hdma->Init.Direction        |
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+          hdma->Init.Mode                | hdma->Init.Priority;
+
+  /* Write to DMA Channel CR register */
+  hdma->Instance->CCR = tmp;
+
+  /* Initialize parameters for DMAMUX channel :
+     DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
+  */
+  DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    /* if memory to memory force the request to 0*/
+    hdma->Init.Request = DMA_REQUEST_MEM2MEM;
+  }
+
+  /* Set peripheral request  to DMAMUX channel */
+  hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
+
+  /* Clear the DMAMUX synchro overrun flag */
+  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+  if (((hdma->Init.Request >  0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
+  {
+    /* Initialize parameters for DMAMUX request generator :
+       DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
+    */
+    DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+    /* Reset the DMAMUX request generator register*/
+    hdma->DMAmuxRequestGen->RGCR = 0U;
+
+    /* Clear the DMAMUX request generator overrun flag */
+    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+  }
+  else
+  {
+    hdma->DMAmuxRequestGen = 0U;
+    hdma->DMAmuxRequestGenStatus = 0U;
+    hdma->DMAmuxRequestGenStatusMask = 0U;
+  }
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state*/
+  hdma->State  = HAL_DMA_STATE_READY;
+
+  /* Allocate lock resource and initialize it */
+  hdma->Lock = HAL_UNLOCKED;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the DMA peripheral.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+
+  /* Check the DMA handle allocation */
+  if (NULL == hdma)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* Disable the selected DMA Channelx */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Compute the channel index */
+  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
+  {
+    /* DMA1 */
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA1;
+  }
+  else
+  {
+    /* DMA2 */
+    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA2;
+  }
+
+  /* Reset DMA Channel control register */
+  hdma->Instance->CCR  = 0;
+
+  /* Clear all flags */
+  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+
+  /* Initialize parameters for DMAMUX channel :
+     DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
+
+  DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+  /* Reset the DMAMUX channel that corresponds to the DMA channel */
+  hdma->DMAmuxChannel->CCR = 0;
+
+  /* Clear the DMAMUX synchro overrun flag */
+  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+  /* Reset Request generator parameters if any */
+  if (((hdma->Init.Request >  0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
+  {
+    /* Initialize parameters for DMAMUX request generator :
+       DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
+    */
+    DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+    /* Reset the DMAMUX request generator register*/
+    hdma->DMAmuxRequestGen->RGCR = 0U;
+
+    /* Clear the DMAMUX request generator overrun flag */
+    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+  }
+
+  hdma->DMAmuxRequestGen = 0U;
+  hdma->DMAmuxRequestGenStatus = 0U;
+  hdma->DMAmuxRequestGenStatusMask = 0U;
+
+  /* Clean callbacks */
+  hdma->XferCpltCallback = NULL;
+  hdma->XferHalfCpltCallback = NULL;
+  hdma->XferErrorCallback = NULL;
+  hdma->XferAbortCallback = NULL;
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief   Input and Output operation functions
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start DMA transfer
+      (+) Configure the source, destination address and data length and
+          Start DMA transfer with interrupt
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the DMA Transfer.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination (up to 256Kbytes-1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if (HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length & clear flags*/
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+    status = HAL_BUSY;
+  }
+  return status;
+}
+
+/**
+  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination (up to 256Kbytes-1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
+                                   uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if (HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length & clear flags*/
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the transfer complete interrupt */
+    /* Enable the transfer Error interrupt */
+    if (NULL != hdma->XferHalfCpltCallback)
+    {
+      /* Enable the Half transfer complete interrupt as well */
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+    }
+    else
+    {
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
+    }
+
+    /* Check if DMAMUX Synchronization is enabled*/
+    if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+    {
+      /* Enable DMAMUX sync overrun IT*/
+      hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+    }
+
+    if (hdma->DMAmuxRequestGen != 0U)
+    {
+      /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+      /* enable the request gen overrun IT*/
+      hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+    }
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Remain BUSY */
+    status = HAL_BUSY;
+  }
+  return status;
+}
+
+/**
+  * @brief  Abort the DMA Transfer.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+    * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    /* no transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    status = HAL_ERROR;
+  }
+  else
+  {
+     /* Disable DMA IT */
+     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+     
+     /* disable the DMAMUX sync overrun IT*/
+     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+     
+     /* Disable the channel */
+     __HAL_DMA_DISABLE(hdma);
+     
+     /* Clear all flags */
+     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+     
+     /* Clear the DMAMUX synchro overrun flag */
+     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+     
+     if (hdma->DMAmuxRequestGen != 0U)
+     {
+       /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
+       /* disable the request gen overrun IT*/
+       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+     
+       /* Clear the DMAMUX request generator overrun flag */
+       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+     }
+  }  
+  /* Change the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer in Interrupt mode.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* no transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Disable DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+    /* Disable the channel */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* disable the DMAMUX sync overrun IT*/
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+    /* Clear all flags */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    if (hdma->DMAmuxRequestGen != 0U)
+    {
+      /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
+      /* disable the request gen overrun IT*/
+      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Call User Abort callback */
+    if (hdma->XferAbortCallback != NULL)
+    {
+      hdma->XferAbortCallback(hdma);
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Channel.
+  * @param  CompleteLevel Specifies the DMA level complete.
+  * @param  Timeout       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
+                                          uint32_t Timeout)
+{
+  uint32_t temp;
+  uint32_t tickstart;
+
+  if (HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* no transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    __HAL_UNLOCK(hdma);
+    return HAL_ERROR;
+  }
+
+  /* Polling mode not supported in circular mode */
+  if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC))
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+
+  /* Get the level transfer complete flag */
+  if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
+  {
+    /* Transfer Complete flag */
+
+    temp = (uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU);
+  }
+  else
+  {
+    /* Half Transfer Complete flag */
+    temp = (uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU);
+  }
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while (0U == (hdma->DmaBaseAddress->ISR & temp))
+  {
+    if ((0U != (hdma->DmaBaseAddress->ISR & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU)))))
+    {
+      /* When a DMA transfer error occurs */
+      /* A hardware clear of its EN bits is performed */
+      /* Clear all flags */
+      hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      return HAL_ERROR;
+    }
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /*Check for DMAMUX Request generator (if used) overrun status */
+  if (hdma->DMAmuxRequestGen != 0U)
+  {
+    /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
+    if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+    {
+      /* Disable the request gen overrun interrupt */
+      hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+    }
+  }
+
+  /* Check for DMAMUX Synchronization overrun */
+  if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+  {
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    /* Update error code */
+    hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+  }
+
+  if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
+  {
+    /* Clear the transfer complete flag */
+    hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU));
+
+    /* The selected Channelx EN bit is cleared (DMA is disabled and
+    all transfers are complete) */
+    hdma->State = HAL_DMA_STATE_READY;
+  }
+  else
+  {
+    /* Clear the half transfer complete flag */
+    hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU));
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle DMA interrupt request.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+  uint32_t source_it = hdma->Instance->CCR;
+
+  /* Half Transfer Complete Interrupt management ******************************/
+  if ((0U != (flag_it & ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_HT)))
+  {
+    /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+    if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+    {
+      /* Disable the half transfer interrupt */
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+    }
+    /* Clear the half transfer complete flag */
+    hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1FU));
+
+    /* DMA peripheral state is not updated in Half Transfer */
+    /* but in Transfer Complete case */
+
+    if (hdma->XferHalfCpltCallback != NULL)
+    {
+      /* Half transfer callback */
+      hdma->XferHalfCpltCallback(hdma);
+    }
+  }
+  /* Transfer Complete Interrupt management ***********************************/
+  else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU))))
+           && (0U != (source_it & DMA_IT_TC)))
+  {
+    if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+    {
+      /* Disable the transfer complete and error interrupt */
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+    }
+    /* Clear the transfer complete flag */
+    hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1FU));
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    if (hdma->XferCpltCallback != NULL)
+    {
+      /* Transfer complete callback */
+      hdma->XferCpltCallback(hdma);
+    }
+  }
+  /* Transfer Error Interrupt management **************************************/
+  else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU))))
+           && (0U != (source_it & DMA_IT_TE)))
+  {
+    /* When a DMA transfer error occurs */
+    /* A hardware clear of its EN bits is performed */
+    /* Disable ALL DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+    /* Clear all flags */
+    hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+
+    /* Update error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    if (hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+  return;
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Channel.
+  * @param  CallbackID           User Callback identifier
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @param  pCallback            pointer to private callbacsk function which has pointer to
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if (HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+      case  HAL_DMA_XFER_CPLT_CB_ID:
+        hdma->XferCpltCallback = pCallback;
+        break;
+
+      case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+        hdma->XferHalfCpltCallback = pCallback;
+        break;
+
+      case  HAL_DMA_XFER_ERROR_CB_ID:
+        hdma->XferErrorCallback = pCallback;
+        break;
+
+      case  HAL_DMA_XFER_ABORT_CB_ID:
+        hdma->XferAbortCallback = pCallback;
+        break;
+
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Channel.
+  * @param  CallbackID           User Callback identifier
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if (HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+      case  HAL_DMA_XFER_CPLT_CB_ID:
+        hdma->XferCpltCallback = NULL;
+        break;
+
+      case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+        hdma->XferHalfCpltCallback = NULL;
+        break;
+
+      case  HAL_DMA_XFER_ERROR_CB_ID:
+        hdma->XferErrorCallback = NULL;
+        break;
+
+      case  HAL_DMA_XFER_ABORT_CB_ID:
+        hdma->XferAbortCallback = NULL;
+        break;
+
+      case   HAL_DMA_XFER_ALL_CB_ID:
+        hdma->XferCpltCallback = NULL;
+        hdma->XferHalfCpltCallback = NULL;
+        hdma->XferErrorCallback = NULL;
+        hdma->XferAbortCallback = NULL;
+        break;
+
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
+  *  @brief    Peripheral State and Errors functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the DMA hande state.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval HAL state
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+  /* Return DMA handle state */
+  return hdma->State;
+}
+
+/**
+  * @brief  Return the DMA error code.
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Channel.
+  * @retval DMA Error Code
+  */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+  return hdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the DMA Transfer parameter.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Channel.
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* Clear the DMAMUX synchro overrun flag */
+  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+  if (hdma->DMAmuxRequestGen != 0U)
+  {
+    /* Clear the DMAMUX request generator overrun flag */
+    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+  }
+
+  /* Clear all flags */
+  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+
+  /* Configure DMA Channel data length */
+  hdma->Instance->CNDTR = DataLength;
+
+  /* Memory to Peripheral */
+  if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {
+    /* Configure DMA Channel destination address */
+    hdma->Instance->CPAR = DstAddress;
+
+    /* Configure DMA Channel source address */
+    hdma->Instance->CMAR = SrcAddress;
+  }
+  /* Peripheral to Memory */
+  else
+  {
+    /* Configure DMA Channel source address */
+    hdma->Instance->CPAR = SrcAddress;
+
+    /* Configure DMA Channel destination address */
+    hdma->Instance->CMAR = DstAddress;
+  }
+}
+
+/**
+  * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on stream number
+  * @param  hdma        pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval None
+  */
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+  uint32_t dmamux_base_addr;
+  uint32_t channel_number;
+  DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase;
+
+  /* check if instance is not outside the DMA channel range */
+  if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
+  {
+    /* DMA1 */
+    DMAMUX1_ChannelBase = DMAMUX1_Channel0;
+  }
+  else
+  {
+    /* DMA2 */
+#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx)
+    DMAMUX1_ChannelBase = DMAMUX1_Channel8;
+#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB)
+    DMAMUX1_ChannelBase = DMAMUX1_Channel6;
+#else
+    DMAMUX1_ChannelBase = DMAMUX1_Channel7;
+#endif /* STM32G4x1xx) */
+  }
+  dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase;
+  channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
+  hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
+  hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+  hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
+}
+
+/**
+  * @brief  Updates the DMA handle with the DMAMUX  request generator params
+  * @param  hdma        pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Channel.
+  * @retval None
+  */
+
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+  uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
+
+  /* DMA Channels are connected to DMAMUX1 request generator blocks*/
+  hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
+
+  hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
+
+  hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c
new file mode 100644
index 0000000..cb44db8
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c
@@ -0,0 +1,298 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_dma_ex.c
+  * @author  MCD Application Team
+  * @brief   DMA Extension HAL module driver
+  *         This file provides firmware functions to manage the following
+  *         functionalities of the DMA Extension peripheral:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  The DMA Extension HAL driver can be used as follows:
+
+   (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+   (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+       to respectively enable/disable the request generator.
+
+   (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
+       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
+       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
+       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
+      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMAEx DMAEx
+  * @brief DMA Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+  * @{
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
+  *  @brief   Extended features functions
+  *
+@verbatim
+ ===============================================================================
+                #####  Extended features functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+    (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+    (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+       to respectively enable/disable the request generator.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA channel.
+  * @param  pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+
+  assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
+  assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
+  assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
+  assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
+
+  /*Check if the DMA state is ready */
+  if (hdma->State == HAL_DMA_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
+    MODIFY_REG(hdma->DMAmuxChannel->CCR, \
+               (~DMAMUX_CxCR_DMAREQ_ID), \
+               ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
+               pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
+               ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
+
+    /* Process UnLocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /*DMA State not Ready*/
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMAMUX request generator block used by the given DMA channel (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA channel.
+  * @param  pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
+  *         contains the request generator parameters.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
+                                                      HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+
+  assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
+  assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block
+  */
+  if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    /* Set the request generator new parameters */
+    hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
+                                   ((pRequestGeneratorConfig->RequestNumber - 1U) << (POSITION_VAL(DMAMUX_RGxCR_GNBREQ) & 0x1FU)) | \
+                                   pRequestGeneratorConfig->Polarity;
+    /* Process UnLocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the DMAMUX request generator block used by the given DMA channel (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block
+  */
+  if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
+  {
+
+    /* Enable the request generator*/
+    hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the DMAMUX request generator block used by the given DMA channel (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block
+  */
+  if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
+  {
+
+    /* Disable the request generator*/
+    hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handles DMAMUX interrupt request.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA channel.
+  * @retval None
+  */
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  /* Check for DMAMUX Synchronization overrun */
+  if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+  {
+    /* Disable the synchro overrun interrupt */
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    /* Update error code */
+    hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+
+    if (hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+
+  if (hdma->DMAmuxRequestGen != 0)
+  {
+    /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
+    if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+    {
+      /* Disable the request gen overrun interrupt */
+      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+
+      if (hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c
new file mode 100644
index 0000000..94af4cc
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c
@@ -0,0 +1,639 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
+  *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### EXTI Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each Exti line can be configured within this driver.
+
+    (+) Exti line can be configured in 3 different modes
+        (++) Interrupt
+        (++) Event
+        (++) Both of them
+
+    (+) Configurable Exti lines can be configured with 3 different triggers
+        (++) Rising
+        (++) Falling
+        (++) Both of them
+
+    (+) When set in interrupt mode, configurable Exti lines have two different
+        interrupt pending registers which allow to distinguish which transition
+        occurs:
+        (++) Rising edge pending interrupt
+        (++) Falling
+
+    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+        be selected through multiplexer.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+        (++) Choose the interrupt line number by setting "Line" member from
+             EXTI_ConfigTypeDef structure.
+        (++) Configure the interrupt and/or event mode using "Mode" member from
+             EXTI_ConfigTypeDef structure.
+        (++) For configurable lines, configure rising and/or falling trigger
+             "Trigger" member from EXTI_ConfigTypeDef structure.
+        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+             member from GPIO_InitTypeDef structure.
+
+    (#) Get current Exti configuration of a dedicated line using
+        HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+
+    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+        (++) Provide exiting handle as first parameter.
+        (++) Provide which callback will be registered using one value from
+             EXTI_CallbackIDTypeDef.
+        (++) Provide callback function pointer.
+
+    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
+
+    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+/** MISRA C:2012 deviation rule has been granted for following rule:
+  * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+  * of bounds [0,3] in following API :
+  * HAL_EXTI_SetConfigLine
+  * HAL_EXTI_GetConfigLine
+  * HAL_EXTI_ClearConfigLine
+  */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+#define EXTI_MODE_OFFSET                    0x08U   /* 0x20: offset between MCU IMR/EMR registers */
+#define EXTI_CONFIG_OFFSET                  0x08U   /* 0x20: offset between MCU Rising/Falling configuration registers */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+  *  @brief    Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on EXTI configuration to be set.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+  /* Assign line number to handle */
+  hexti->Line = pExtiConfig->Line;
+
+  /* Compute line register offset */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  /* Compute line position */
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  /* Compute line mask */
+  maskline = (1uL << linepos);
+
+  /* Configure triggers for configurable lines */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+  {
+    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+    /* Configure rising trigger */
+    regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store rising trigger mode */
+    *regaddr = regval;
+
+    /* Configure falling trigger */
+    regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store falling trigger mode */
+    *regaddr = regval;
+
+    /* Configure gpio port selection in case of gpio exti line */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[linepos >> 2u];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      SYSCFG->EXTICR[linepos >> 2u] = regval;
+    }
+  }
+
+  /* Configure interrupt mode : read current mode */
+  regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store interrupt mode */
+  *regaddr = regval;
+
+  /* Configure event mode : read current mode */
+  regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store event mode */
+  *regaddr = regval;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Get configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on structure to store Exti configuration.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* Store handle line number to configuration structure */
+  pExtiConfig->Line = hexti->Line;
+
+  /* Compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  /* Compute line position */
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  /* Compute mask */
+  maskline = (1uL << linepos);
+
+  /* 1] Get core mode : interrupt */
+  regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00u)
+  {
+    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+  }
+  else
+  {
+    pExtiConfig->Mode = EXTI_MODE_NONE;
+  }
+
+  /* Get event mode */
+  regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00u)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_EVENT;
+  }
+
+  /* Get default Trigger and GPIOSel configuration */
+  pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+  pExtiConfig->GPIOSel = 0x00u;
+
+  /* 2] Get trigger for configurable lines : rising */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+  {
+    regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0x00u)
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+    }
+
+    /* Get falling configuration */
+    regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0x00u)
+    {
+      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+    }
+
+    /* Get Gpio port selection for gpio lines */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[linepos >> 2u];
+      pExtiConfig->GPIOSel = ((regval >> (SYSCFG_EXTICR1_EXTI1_Pos * ((linepos & 0x03u)))));
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Clear whole configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  /* compute line position */
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  /* compute line mask */
+  maskline = (1uL << linepos);
+
+  /* 1] Clear interrupt mode */
+  regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 2] Clear event mode */
+  regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 3] Clear triggers in case of configurable lines */
+  if ((hexti->Line & EXTI_CONFIG) != 0x00u)
+  {
+    regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    /* Get Gpio port selection for gpio lines */
+    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[linepos >> 2u];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      SYSCFG->EXTICR[linepos >> 2u] = regval;
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Register callback for a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  CallbackID User callback identifier.
+  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+  * @param  pPendingCbfn function pointer to be stored as callback.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_CB(CallbackID));
+
+  switch (CallbackID)
+  {
+    /* set common callback */
+    case  HAL_EXTI_COMMON_CB_ID:
+      hexti->PendingCallback = pPendingCbfn;
+      break;
+
+    default:
+      hexti->PendingCallback = NULL;
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Store line number as handle private field.
+  * @param  hexti Exti handle.
+  * @param  ExtiLine Exti line number.
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Store line number as handle private field */
+    hexti->Line = ExtiLine;
+
+    return HAL_OK;
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+  *  @brief EXTI IO functions.
+  *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  hexti Exti handle.
+  * @retval none.
+  */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Compute line register offset */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  /* compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Get pending bit  */
+  regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
+  regval = (*regaddr & maskline);
+
+  if (regval != 0x00u)
+  {
+    /* Clear pending bit */
+    *regaddr = maskline;
+
+    /* Call pending callback */
+    if (hexti->PendingCallback != NULL)
+    {
+      hexti->PendingCallback();
+    }
+  }
+}
+
+/**
+  * @brief  Get interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge unused
+  * @retval 1 if interrupt is pending else 0.
+  */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  UNUSED(Edge);
+
+  /* Compute line register offset */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  /* Compute line position */
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  /* Compute line mask */
+  maskline = (1uL << linepos);
+
+  /* Get pending bit */
+  regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
+
+  /* return 1 if bit is set else 0 */
+  regval = ((*regaddr & maskline) >> linepos);
+  return regval;
+}
+
+
+/**
+  * @brief  Clear interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge unused
+  * @retval None.
+  */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  UNUSED(Edge);
+
+  /* Compute line register offset */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Get pending register address */
+  regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
+
+  /* Clear Pending bit */
+  *regaddr =  maskline;
+}
+
+
+/**
+  * @brief  Generate a software interrupt for a dedicated line.
+  * @param  hexti Exti handle.
+  * @retval None.
+  */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+  /* compute line register offset */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  /* compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
+  *regaddr = maskline;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c
new file mode 100644
index 0000000..9139817
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c
@@ -0,0 +1,768 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_flash.c
+  * @author  MCD Application Team
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions
+  *           + Peripheral Errors functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+
+  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+       to the Flash memory. It implements the erase and program Flash memory operations
+       and the read and write protection mechanisms.
+
+  [..] The Flash memory interface accelerates code execution with a system of instruction
+       prefetch and cache lines.
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Option bytes programming
+      (+) Prefetch on I-Code
+      (+) 32 cache lines of 4*64 or 2*128 bits on I-Code
+      (+) 8 cache lines of 4*64 or 2*128 bits on D-Code
+      (+) Error code correction (ECC) : Data in flash are 72-bits word
+          (8 bits added per double word)
+
+
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      This driver provides functions and macros to configure and program the FLASH
+      memory of all STM32G4xx devices.
+
+      (#) Flash Memory IO Programming functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Program functions: double word and fast program (full row programming)
+           (++) There are two modes of programming :
+            (+++) Polling mode using HAL_FLASH_Program() function
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+
+      (#) Interrupts and flags management functions:
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+           (++) Callback functions are called when the flash operations are finished :
+                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
+                HAL_FLASH_OperationErrorCallback()
+           (++) Get error flag status by calling HAL_GetError()
+
+      (#) Option bytes management functions:
+           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
+                HAL_FLASH_OB_Lock() functions
+           (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
+                In this case, a reset is generated
+
+    [..]
+      In addition to these functions, this driver includes a set of macros allowing
+      to handle the following operations:
+       (+) Set the latency
+       (+) Enable/Disable the prefetch buffer
+       (+) Enable/Disable the Instruction cache and the Data cache
+       (+) Reset the Instruction cache and the Data cache
+       (+) Enable/Disable the Flash power-down during low-power run and sleep modes
+       (+) Enable/Disable the Flash interrupts
+       (+) Monitor the Flash flags status
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH FLASH
+  * @brief FLASH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+  * @{
+  */
+#define FLASH_NB_DOUBLE_WORDS_IN_ROW  32
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+  * @{
+  */
+
+/**
+  * @brief  Variable used for Program/Erase sectors under interruption
+  */
+FLASH_ProcessTypeDef pFlash  = {.Lock = HAL_UNLOCKED,
+                                .ErrorCode = HAL_FLASH_ERROR_NONE,
+                                .ProcedureOnGoing = FLASH_PROC_NONE,
+                                .Address = 0U,
+                                .Bank = FLASH_BANK_1,
+                                .Page = 0U,
+                                .NbPagesToErase = 0U,
+                                .CacheToReactivate = FLASH_CACHE_DISABLED};
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+  * @{
+  */
+static void          FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+static void          FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+  *  @brief   Programming operation functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the FLASH
+    program operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Program double word or fast program of a row at a specified address.
+  * @param  TypeProgram Indicate the way to program at a specified address.
+  *         This parameter can be a value of @ref FLASH_Type_Program.
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  *         This parameter is the data for the double word program and the address where
+  *         are stored the data for the row fast program.
+  *
+  * @retval HAL_Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status;
+  uint32_t prog_bit = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+    if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
+    {
+      /* Program double-word (64-bit) at a specified address */
+      FLASH_Program_DoubleWord(Address, Data);
+      prog_bit = FLASH_CR_PG;
+    }
+    else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
+    {
+      /* Fast program a 32 row double-word (64-bit) at a specified address */
+      FLASH_Program_Fast(Address, (uint32_t)Data);
+
+      /* If it is the last row, the bit will be cleared at the end of the operation */
+      if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
+      {
+        prog_bit = FLASH_CR_FSTPG;
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+    /* If the program operation is completed, disable the PG or FSTPG Bit */
+    if (prog_bit != 0U)
+    {
+      CLEAR_BIT(FLASH->CR, prog_bit);
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  /* return status */
+  return status;
+}
+
+/**
+  * @brief  Program double word or fast program of a row at a specified address with interrupt enabled.
+  * @param  TypeProgram Indicate the way to program at a specified address.
+  *         This parameter can be a value of @ref FLASH_Type_Program.
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  *         This parameter is the data for the double word program and the address where
+  *         are stored the data for the row fast program.
+  *
+  * @retval HAL_Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+  if (status != HAL_OK)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+  else
+  {
+    /* Set internal variables used by the IRQ handler */
+    if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
+    {
+      pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
+    }
+    else
+    {
+      pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+    }
+    pFlash.Address = Address;
+
+    /* Enable End of Operation and Error interrupts */
+    __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+    if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
+    {
+      /* Program double-word (64-bit) at a specified address */
+      FLASH_Program_DoubleWord(Address, Data);
+    }
+    else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
+    {
+      /* Fast program a 32 row double-word (64-bit) at a specified address */
+      FLASH_Program_Fast(Address, (uint32_t)Data);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Handle FLASH interrupt request.
+  * @retval None
+  */
+void HAL_FLASH_IRQHandler(void)
+{
+  uint32_t tmp_page;
+  uint32_t error;
+  FLASH_ProcedureTypeDef procedure;
+
+  /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */
+  CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
+#if defined (FLASH_OPTR_DBANK)
+  CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
+#endif
+
+  /* Disable the FSTPG Bit only if it is the last row programmed */
+  if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)
+  {
+    CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
+  }
+
+  /* Check FLASH operation error flags */
+  error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
+
+  if (error != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= error;
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG(error);
+
+    /* Flush the caches to be sure of the data consistency */
+    FLASH_FlushCaches() ;
+
+    /* FLASH error interrupt user callback */
+    procedure = pFlash.ProcedureOnGoing;
+    if (procedure == FLASH_PROC_PAGE_ERASE)
+    {
+      HAL_FLASH_OperationErrorCallback(pFlash.Page);
+    }
+    else if (procedure == FLASH_PROC_MASS_ERASE)
+    {
+      HAL_FLASH_OperationErrorCallback(pFlash.Bank);
+    }
+    else if ((procedure == FLASH_PROC_PROGRAM) ||
+             (procedure == FLASH_PROC_PROGRAM_LAST))
+    {
+      HAL_FLASH_OperationErrorCallback(pFlash.Address);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /*Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
+    if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
+    {
+      /* Nb of pages to erased can be decreased */
+      pFlash.NbPagesToErase--;
+
+      /* Check if there are still pages to erase*/
+      if (pFlash.NbPagesToErase != 0U)
+      {
+        /* Indicate user which page has been erased*/
+        HAL_FLASH_EndOfOperationCallback(pFlash.Page);
+
+        /* Increment page number */
+        pFlash.Page++;
+        tmp_page = pFlash.Page;
+        FLASH_PageErase(tmp_page, pFlash.Bank);
+      }
+      else
+      {
+        /* No more pages to Erase */
+        /* Reset Address and stop Erase pages procedure */
+        pFlash.Page = 0xFFFFFFFFU;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+        /* Flush the caches to be sure of the data consistency */
+        FLASH_FlushCaches() ;
+
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Page);
+      }
+    }
+    else
+    {
+      /* Flush the caches to be sure of the data consistency */
+      FLASH_FlushCaches() ;
+
+      procedure = pFlash.ProcedureOnGoing;
+      if (procedure == FLASH_PROC_MASS_ERASE)
+      {
+        /* MassErase ended. Return the selected bank */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
+      }
+      else if ((procedure == FLASH_PROC_PROGRAM) ||
+               (procedure == FLASH_PROC_PROGRAM_LAST))
+      {
+        /* Program ended. Return the selected address */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      /*Clear the procedure ongoing*/
+      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+    }
+  }
+
+  if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+  {
+    /* Disable End of Operation and Error interrupts */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+}
+
+/**
+  * @brief  FLASH end of operation interrupt callback.
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure:
+  *           @arg Mass Erase: Bank number which has been requested to erase
+  *           @arg Page Erase: Page which has been erased
+  *                            (if 0xFFFFFFFF, it means that all the selected pages have been erased)
+  *           @arg Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  FLASH operation error interrupt callback.
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure:
+  *           @arg Mass Erase: Bank number which has been requested to erase
+  *           @arg Page Erase: Page number which returned an error
+  *           @arg Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+  * @brief   Management functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the FLASH control register access.
+  * @retval HAL_Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Registers access */
+    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+    /* verify Flash is unlocked */
+    if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Lock the FLASH control register access.
+  * @retval HAL_Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
+  /* verify Flash is locked */
+  if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
+  {
+    status = HAL_OK;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unlock the FLASH Option Bytes Registers access.
+  * @retval HAL_Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
+  {
+    /* Authorizes the Option Byte register programming */
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+
+    /* verify option bytes are unlocked */
+    if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Lock the FLASH Option Bytes Registers access.
+  * @retval HAL_Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
+
+  /* Verify option bytes are locked */
+  if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
+  {
+    status = HAL_OK;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @retval HAL_Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+  /* Set the bit to force the option byte reloading */
+  SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+
+  /* Wait for last operation to be completed */
+  return (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
+  * @brief   Peripheral Errors functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Peripheral Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the specific FLASH error flag.
+  * @retval FLASH_ErrorCode. The returned value can be:
+  *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
+  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
+  *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
+  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
+  *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
+  *            @arg HAL_FLASH_ERROR_NONE: No error set
+  *            @arg HAL_FLASH_ERROR_OP: FLASH Operation error
+  *            @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
+  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
+  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
+  *            @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
+  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
+  *            @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
+  *            @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
+  *            @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
+  *            @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
+  */
+uint32_t HAL_FLASH_GetError(void)
+{
+  return pFlash.ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout maximum flash operation timeout.
+  * @retval HAL_Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error
+     flag will be set */
+
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t error;
+
+  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
+  {
+    if ((HAL_GetTick() - tickstart) > Timeout)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Check FLASH operation error flags */
+  error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
+  if (error != 0u)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= error;
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG(error);
+
+    return HAL_ERROR;
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+  }
+
+  /* If there is an error flag set */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Program double-word (64-bit) at a specified address.
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+  /* Set PG bit */
+  SET_BIT(FLASH->CR, FLASH_CR_PG);
+
+  /* Program first word */
+  *(uint32_t *)Address = (uint32_t)Data;
+
+  /* Barrier to ensure programming is performed in 2 steps, in right order
+    (independently of compiler optimization behavior) */
+  __ISB();
+
+  /* Program second word */
+  *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
+}
+
+/**
+  * @brief  Fast program a row double-word (64-bit) at a specified address.
+  * @param  Address specifies the address to be programmed.
+  * @param  DataAddress specifies the address where the data are stored.
+  * @retval None
+  */
+static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
+{
+  uint8_t row_index = (2 * FLASH_NB_DOUBLE_WORDS_IN_ROW);
+  uint32_t *dest_addr = (uint32_t *)Address;
+  uint32_t *src_addr = (uint32_t *)DataAddress;
+  uint32_t primask_bit;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
+
+  /* Set FSTPG bit */
+  SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
+
+  /* Enter critical section: Disable interrupts to avoid any interruption during the loop */
+  primask_bit = __get_PRIMASK();
+  __disable_irq();
+
+  /* Program the double words of the row */
+  do
+  {
+    *dest_addr = *src_addr;
+    dest_addr++;
+    src_addr++;
+    row_index--;
+  }
+  while (row_index != 0U);
+
+  /* Exit critical section: restore previous priority mask */
+  __set_PRIMASK(primask_bit);
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c
new file mode 100644
index 0000000..fd64b10
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c
@@ -0,0 +1,1414 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_flash_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the FLASH extended peripheral:
+  *           + Extended programming operations functions
+  *
+  @verbatim
+  ==============================================================================
+                   ##### Flash Extended features #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the FLASH interface for STM32G4xx
+       devices contains the following additional features
+
+       (+) Capacity up to 512 Kbytes with dual bank architecture supporting read-while-write
+           capability (RWW)
+       (+) Dual bank 64-bits memory organization with possibility of single bank 128-bits
+       (+) Protected areas including WRP, PCROP and Securable memory
+
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure and program the FLASH memory
+       of all STM32G4xx devices. It includes
+      (#) Flash Memory Erase functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Erase function: Erase pages, or mass erase banks
+           (++) There are two modes of erase :
+             (+++) Polling Mode using HAL_FLASHEx_Erase()
+             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+
+      (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to:
+        (++) Configure the write protection areas (WRP)
+        (++) Set the Read protection Level (RDP)
+        (++) Program the user Option Bytes
+        (++) Configure the Proprietary Code ReadOut protection areas (PCROP)
+        (++) Configure the Securable memory areas
+        (++) Configure the Boot Lock
+
+      (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to:
+        (++) Get the configuration of write protection areas (WRP)
+        (++) Get the level of read protection (RDP)
+        (++) Get the value of the user Option Bytes
+        (++) Get the configuration of Proprietary Code ReadOut Protection areas (PCROP)
+        (++) Get the configuration of Securable memory areas
+        (++) Get the status of Boot Lock
+
+      (#) Activation of Securable memory area: Use HAL_FLASHEx_EnableSecMemProtection()
+        (++) Deny the access to securable memory area
+
+      (#) Enable or disable debugger: Use HAL_FLASHEx_EnableDebugger() or
+          HAL_FLASHEx_DisableDebugger()
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASHEx FLASHEx
+  * @brief FLASH Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+  * @{
+  */
+static void              FLASH_MassErase(uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);
+static void              FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset);
+static uint32_t          FLASH_OB_GetRDP(void);
+static uint32_t          FLASH_OB_GetUser(void);
+static void              FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr);
+static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecMemBank, uint32_t SecMemSize);
+static void              FLASH_OB_GetSecMem(uint32_t SecMemBank, uint32_t *SecMemSize);
+static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig);
+static uint32_t          FLASH_OB_GetBootLock(void);
+
+/**
+  * @}
+  */
+
+/* Exported functions -------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+  * @brief   Extended IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Extended programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the Extended FLASH
+    programming operations Operations.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory pages.
+  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  * @param[out]  PageError pointer to variable that contains the configuration
+  *         information on faulty page in case of error (0xFFFFFFFF means that all
+  *         the pages have been correctly erased).
+  * @retval HAL_Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+{
+  HAL_StatusTypeDef status;
+  uint32_t page_index;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+    /* Deactivate the cache if they are activated to avoid data misbehavior */
+    if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
+    {
+      if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
+      {
+        /* Disable data cache  */
+        __HAL_FLASH_DATA_CACHE_DISABLE();
+        pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
+      }
+      else
+      {
+        pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
+      }
+    }
+    else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
+    {
+      /* Disable data cache  */
+      __HAL_FLASH_DATA_CACHE_DISABLE();
+      pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+    }
+    else
+    {
+      pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+    }
+
+    if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /* Mass erase to be done */
+      FLASH_MassErase(pEraseInit->Banks);
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+#if defined (FLASH_OPTR_DBANK)
+      /* If the erase operation is completed, disable the MER1 and MER2 Bits */
+      CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
+#else
+      /* If the erase operation is completed, disable the MER1 Bit */
+      CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
+#endif
+    }
+    else
+    {
+      /*Initialization of PageError variable*/
+      *PageError = 0xFFFFFFFFU;
+
+      for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
+      {
+        FLASH_PageErase(page_index, pEraseInit->Banks);
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+        /* If the erase operation is completed, disable the PER Bit */
+        CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
+
+        if (status != HAL_OK)
+        {
+          /* In case of error, stop erase procedure and return the faulty page */
+          *PageError = page_index;
+          break;
+        }
+      }
+    }
+
+    /* Flush the caches to be sure of the data consistency */
+    FLASH_FlushCaches();
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
+  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  * @retval HAL_Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Deactivate the cache if they are activated to avoid data misbehavior */
+  if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
+  {
+    if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
+    {
+      /* Disable data cache  */
+      __HAL_FLASH_DATA_CACHE_DISABLE();
+      pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
+    }
+    else
+    {
+      pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
+    }
+  }
+  else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
+  {
+    /* Disable data cache  */
+    __HAL_FLASH_DATA_CACHE_DISABLE();
+    pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+  }
+  else
+  {
+    pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+  }
+
+  /* Enable End of Operation and Error interrupts */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+  pFlash.Bank = pEraseInit->Banks;
+
+  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+  {
+    /* Mass erase to be done */
+    pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
+    FLASH_MassErase(pEraseInit->Banks);
+  }
+  else
+  {
+    /* Erase by page to be done */
+    pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
+    pFlash.NbPagesToErase = pEraseInit->NbPages;
+    pFlash.Page = pEraseInit->Page;
+
+    /*Erase 1st page and wait for IT */
+    FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Program Option bytes.
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+  *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+  * @note   New option bytes configuration will be taken into account in two cases:
+  *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+  *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+  * @retval HAL_Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Write protection configuration */
+  if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
+  {
+    /* Configure of Write protection on the selected area */
+    if (FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Read protection configuration */
+  if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
+  {
+    /* Configure the Read protection level */
+    if (FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* User Configuration */
+  if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
+  {
+    /* Configure the user option bytes */
+    if (FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* PCROP Configuration */
+  if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
+  {
+    if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr)
+    {
+      /* Configure the Proprietary code readout protection */
+      if (FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK)
+      {
+        status = HAL_ERROR;
+      }
+    }
+  }
+
+  /* Securable memory Configuration */
+  if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0U)
+  {
+    /* Configure the securable memory area */
+    if (FLASH_OB_SecMemConfig(pOBInit->SecBank, pOBInit->SecSize) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Boot Entry Point Configuration */
+  if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U)
+  {
+    /* Configure the boot unique entry point option */
+    if (FLASH_OB_BootLockConfig(pOBInit->BootEntryPoint) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Get the Option bytes configuration.
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that contains the
+  *         configuration information.
+  * @note   The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate
+  *         which area is requested for the WRP and PCROP, else no information will be returned.
+  * @retval None
+  */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
+
+#if defined (FLASH_OPTR_DBANK)
+  if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
+      (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
+#else
+  if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
+#endif
+  {
+    pOBInit->OptionType |= OPTIONBYTE_WRP;
+    /* Get write protection on the selected area */
+    FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
+  }
+
+  /* Get Read protection level */
+  pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+  /* Get the user option bytes */
+  pOBInit->USERConfig = FLASH_OB_GetUser();
+
+#if defined (FLASH_OPTR_DBANK)
+  if ((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2))
+#else
+  if (pOBInit->PCROPConfig == FLASH_BANK_1)
+#endif
+  {
+    pOBInit->OptionType |= OPTIONBYTE_PCROP;
+    /* Get the Proprietary code readout protection */
+    FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
+  }
+
+  pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK;
+
+  /* Get the boot entry point */
+  pOBInit->BootEntryPoint = FLASH_OB_GetBootLock();
+
+  /* Get the securable memory area configuration */
+#if defined (FLASH_OPTR_DBANK)
+  if ((pOBInit->SecBank == FLASH_BANK_1) || (pOBInit->SecBank == FLASH_BANK_2))
+#else
+  if (pOBInit->SecBank == FLASH_BANK_1)
+#endif
+  {
+    pOBInit->OptionType |= OPTIONBYTE_SEC;
+    FLASH_OB_GetSecMem(pOBInit->SecBank, &(pOBInit->SecSize));
+  }
+}
+
+/**
+  * @brief  Enable the FLASH Securable Memory protection.
+  * @param  Bank: Bank to be protected
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be protected
+  *            @arg FLASH_BANK_2: Bank2 to be protected (*)
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected (*)
+  * @note   (*) availability depends on devices
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank)
+{
+#if defined (FLASH_OPTR_DBANK)
+  if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)
+  {
+    /* Check the parameters */
+    assert_param(IS_FLASH_BANK(Bank));
+
+    /* Enable the Securable Memory Protection Bit for the bank 1 if requested */
+    if ((Bank & FLASH_BANK_1) != 0U)
+    {
+      SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1);
+    }
+
+    /* Enable the Securable Memory Protection Bit for the bank 2 if requested */
+    if ((Bank & FLASH_BANK_2) != 0U)
+    {
+      SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT2);
+    }
+  }
+  else
+#endif
+  {
+    SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable Debugger.
+  * @note   After calling this API, flash interface allow debugger intrusion.
+  * @retval None
+  */
+void HAL_FLASHEx_EnableDebugger(void)
+{
+  FLASH->ACR |= FLASH_ACR_DBG_SWEN;
+}
+
+
+/**
+  * @brief  Disable Debugger.
+  * @note   After calling this API, Debugger is disabled: it's no more possible to
+  *         break, see CPU register, etc...
+  * @retval None
+  */
+void HAL_FLASHEx_DisableDebugger(void)
+{
+  FLASH->ACR &= ~FLASH_ACR_DBG_SWEN;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASHEx_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Mass erase of FLASH memory.
+  * @param  Banks Banks to be erased.
+  *         This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased (*)
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased (*)
+  * @note   (*) availability depends on devices
+  * @retval None
+  */
+static void FLASH_MassErase(uint32_t Banks)
+{
+#if defined (FLASH_OPTR_DBANK)
+  if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)
+#endif
+  {
+    /* Check the parameters */
+    assert_param(IS_FLASH_BANK(Banks));
+
+    /* Set the Mass Erase Bit for the bank 1 if requested */
+    if ((Banks & FLASH_BANK_1) != 0U)
+    {
+      SET_BIT(FLASH->CR, FLASH_CR_MER1);
+    }
+
+#if defined (FLASH_OPTR_DBANK)
+    /* Set the Mass Erase Bit for the bank 2 if requested */
+    if ((Banks & FLASH_BANK_2) != 0U)
+    {
+      SET_BIT(FLASH->CR, FLASH_CR_MER2);
+    }
+#endif
+  }
+#if defined (FLASH_OPTR_DBANK)
+  else
+  {
+    SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
+  }
+#endif
+
+  /* Proceed to erase all sectors */
+  SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+  * @brief  Erase the specified FLASH memory page.
+  * @param  Page FLASH page to erase.
+  *         This parameter must be a value between 0 and (max number of pages in the bank - 1).
+  * @param  Banks Bank where the page will be erased.
+  *         This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Page in bank 1 to be erased
+  *            @arg FLASH_BANK_2: Page in bank 2 to be erased (*)
+  * @note   (*) availability depends on devices
+  * @retval None
+  */
+void FLASH_PageErase(uint32_t Page, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_PAGE(Page));
+
+#if defined (FLASH_OPTR_DBANK)
+  if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
+  {
+    CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
+  }
+  else
+  {
+    assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
+
+    if ((Banks & FLASH_BANK_1) != 0U)
+    {
+      CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
+    }
+    else
+    {
+      SET_BIT(FLASH->CR, FLASH_CR_BKER);
+    }
+  }
+#endif
+
+  /* Proceed to erase the page */
+  MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos));
+  SET_BIT(FLASH->CR, FLASH_CR_PER);
+  SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+  * @brief  Flush the instruction and data caches.
+  * @retval None
+  */
+void FLASH_FlushCaches(void)
+{
+  FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
+
+  /* Flush instruction cache  */
+  if ((cache == FLASH_CACHE_ICACHE_ENABLED) ||
+      (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+  {
+    /* Disable instruction cache */
+    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+    /* Reset instruction cache */
+    __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+    /* Enable instruction cache */
+    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+  }
+
+  /* Flush data cache */
+  if ((cache == FLASH_CACHE_DCACHE_ENABLED) ||
+      (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+  {
+    /* Reset data cache */
+    __HAL_FLASH_DATA_CACHE_RESET();
+    /* Enable data cache */
+    __HAL_FLASH_DATA_CACHE_ENABLE();
+  }
+
+  /* Reset internal variable */
+  pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+}
+
+/**
+  * @brief  Configure the write protection area into Option Bytes.
+  * @note   When the memory read protection level is selected (RDP level = 1),
+  *         it is not possible to program or erase Flash memory if the CPU debug
+  *         features are connected (JTAG or single wire) or boot code is being
+  *         executed from RAM or System flash, even if WRP is not activated.
+  * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+  *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+  * @note   New option bytes configuration will be taken into account in two cases:
+  *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+  *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+  * @param  WRPArea specifies the area to be configured.
+  *         This parameter can be one of the following values:
+  *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
+  *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
+  *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (*)
+  *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (*)
+  * @note   (*) availability depends on devices
+  * @param  WRPStartOffset specifies the start page of the write protected area.
+  *         This parameter can be page number between 0 and (max number of pages in the bank - 1).
+  * @param  WRDPEndOffset specifies the end page of the write protected area.
+  *         This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1).
+  * @retval HAL_Status
+  */
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRPAREA(WRPArea));
+  assert_param(IS_FLASH_PAGE(WRPStartOffset));
+  assert_param(IS_FLASH_PAGE(WRDPEndOffset));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    /* Configure the write protected area */
+    if (WRPArea == OB_WRPAREA_BANK1_AREAA)
+    {
+      FLASH->WRP1AR = ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset);
+    }
+    else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
+    {
+      FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset);
+    }
+#if defined (FLASH_OPTR_DBANK)
+    else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
+    {
+      FLASH->WRP2AR = ((WRDPEndOffset << FLASH_WRP2AR_WRP2A_END_Pos) | WRPStartOffset);
+    }
+    else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
+    {
+      FLASH->WRP2BR = ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset);
+    }
+#endif
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set the read protection level into Option Bytes.
+  * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+  *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+  * @note   New option bytes configuration will be taken into account in two cases:
+  *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+  *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+  * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible
+  *         to go back to level 1 or 0 !!!
+  * @param  RDPLevel specifies the read protection level.
+  *         This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Memory Read protection
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  *
+  * @retval HAL_Status
+  */
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_OB_RDP_LEVEL(RDPLevel));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    /* Configure the RDP level in the option bytes register */
+    MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
+
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Program the FLASH User Option Bytes.
+  * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+  *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+  * @note   New option bytes configuration will be taken into account in two cases:
+  *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+  *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+  * @param  UserType The FLASH User Option Bytes to be modified.
+  *         This parameter can be a combination of @ref FLASH_OB_USER_Type.
+  * @param  UserConfig The selected User Option Bytes values:
+  *         This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
+  *         @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY ,
+  *         @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
+  *         @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
+  *         @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW,
+  *         @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_nBOOT1,
+  *         @ref FLASH_OB_USER_SRAM_PE, @ref FLASH_OB_USER_CCMSRAM_RST,
+  *         @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
+  *         @ref FLASH_OB_USER_NRST_MODE, @ref FLASH_OB_USER_INTERNAL_RESET_HOLDER
+  * @note   (*) availability depends on devices
+  * @retval HAL_Status
+  */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
+{
+  uint32_t optr_reg_val = 0;
+  uint32_t optr_reg_mask = 0;
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_OB_USER_TYPE(UserType));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if ((UserType & OB_USER_BOR_LEV) != 0U)
+    {
+      /* BOR level option byte should be modified */
+      assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
+
+      /* Set value and mask for BOR level option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
+      optr_reg_mask |= FLASH_OPTR_BOR_LEV;
+    }
+
+    if ((UserType & OB_USER_nRST_STOP) != 0U)
+    {
+      /* nRST_STOP option byte should be modified */
+      assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
+
+      /* Set value and mask for nRST_STOP option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
+      optr_reg_mask |= FLASH_OPTR_nRST_STOP;
+    }
+
+    if ((UserType & OB_USER_nRST_STDBY) != 0U)
+    {
+      /* nRST_STDBY option byte should be modified */
+      assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
+
+      /* Set value and mask for nRST_STDBY option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
+      optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
+    }
+
+    if ((UserType & OB_USER_nRST_SHDW) != 0U)
+    {
+      /* nRST_SHDW option byte should be modified */
+      assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
+
+      /* Set value and mask for nRST_SHDW option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
+      optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
+    }
+
+    if ((UserType & OB_USER_IWDG_SW) != 0U)
+    {
+      /* IWDG_SW option byte should be modified */
+      assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
+
+      /* Set value and mask for IWDG_SW option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
+      optr_reg_mask |= FLASH_OPTR_IWDG_SW;
+    }
+
+    if ((UserType & OB_USER_IWDG_STOP) != 0U)
+    {
+      /* IWDG_STOP option byte should be modified */
+      assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
+
+      /* Set value and mask for IWDG_STOP option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
+      optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
+    }
+
+    if ((UserType & OB_USER_IWDG_STDBY) != 0U)
+    {
+      /* IWDG_STDBY option byte should be modified */
+      assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
+
+      /* Set value and mask for IWDG_STDBY option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
+      optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
+    }
+
+    if ((UserType & OB_USER_WWDG_SW) != 0U)
+    {
+      /* WWDG_SW option byte should be modified */
+      assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
+
+      /* Set value and mask for WWDG_SW option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
+      optr_reg_mask |= FLASH_OPTR_WWDG_SW;
+    }
+
+#if defined (FLASH_OPTR_BFB2)
+    if ((UserType & OB_USER_BFB2) != 0U)
+    {
+      /* BFB2 option byte should be modified */
+      assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
+
+      /* Set value and mask for BFB2 option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
+      optr_reg_mask |= FLASH_OPTR_BFB2;
+    }
+#endif
+
+    if ((UserType & OB_USER_nBOOT1) != 0U)
+    {
+      /* nBOOT1 option byte should be modified */
+      assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
+
+      /* Set value and mask for nBOOT1 option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
+      optr_reg_mask |= FLASH_OPTR_nBOOT1;
+    }
+
+    if ((UserType & OB_USER_SRAM_PE) != 0U)
+    {
+      /* SRAM_PE option byte should be modified */
+      assert_param(IS_OB_USER_SRAM_PARITY(UserConfig & FLASH_OPTR_SRAM_PE));
+
+      /* Set value and mask for SRAM_PE option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_PE);
+      optr_reg_mask |= FLASH_OPTR_SRAM_PE;
+    }
+
+    if ((UserType & OB_USER_CCMSRAM_RST) != 0U)
+    {
+      /* CCMSRAM_RST option byte should be modified */
+      assert_param(IS_OB_USER_CCMSRAM_RST(UserConfig & FLASH_OPTR_CCMSRAM_RST));
+
+      /* Set value and mask for CCMSRAM_RST option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_CCMSRAM_RST);
+      optr_reg_mask |= FLASH_OPTR_CCMSRAM_RST;
+    }
+
+    if ((UserType & OB_USER_nSWBOOT0) != 0U)
+    {
+      /* nSWBOOT0 option byte should be modified */
+      assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
+
+      /* Set value and mask for nSWBOOT0 option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
+      optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
+    }
+
+    if ((UserType & OB_USER_nBOOT0) != 0U)
+    {
+      /* nBOOT0 option byte should be modified */
+      assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
+
+      /* Set value and mask for nBOOT0 option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
+      optr_reg_mask |= FLASH_OPTR_nBOOT0;
+    }
+
+    if ((UserType & OB_USER_NRST_MODE) != 0U)
+    {
+      /* Reset Configuration option byte should be modified */
+      assert_param(IS_OB_USER_NRST_MODE(UserConfig & FLASH_OPTR_NRST_MODE));
+
+      /* Set value and mask for Reset Configuration option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_NRST_MODE);
+      optr_reg_mask |= FLASH_OPTR_NRST_MODE;
+    }
+
+    if ((UserType & OB_USER_IRHEN) != 0U)
+    {
+      /* IRH option byte should be modified */
+      assert_param(IS_OB_USER_IRHEN(UserConfig & FLASH_OPTR_IRHEN));
+
+      /* Set value and mask for IRH option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IRHEN);
+      optr_reg_mask |= FLASH_OPTR_IRHEN;
+    }
+
+    /* Configure the option bytes register */
+    MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
+
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the Proprietary code readout protection area into Option Bytes.
+  * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+  *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+  * @note   New option bytes configuration will be taken into account in two cases:
+  *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+  *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+  * @param  PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP option).
+  *         This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 (*)
+  *         with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE.
+  * @note   (*) availability depends on devices
+  * @param  PCROPStartAddr specifies the start address of the Proprietary code readout protection.
+  *         This parameter can be an address between begin and end of the bank.
+  * @param  PCROPEndAddr specifies the end address of the Proprietary code readout protection.
+  *         This parameter can be an address between PCROPStartAddr and end of the bank.
+  * @retval HAL_Status
+  */
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
+{
+  HAL_StatusTypeDef status;
+  uint32_t reg_value;
+  uint32_t bank1_addr;
+#if defined (FLASH_OPTR_DBANK)
+  uint32_t bank2_addr;
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
+  assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
+  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
+  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+#if defined (FLASH_OPTR_DBANK)
+    /* Get the information about the bank swapping */
+    if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)
+    {
+      bank1_addr = FLASH_BASE;
+      bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
+    }
+    else
+    {
+      bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
+      bank2_addr = FLASH_BASE;
+    }
+#else
+    bank1_addr = FLASH_BASE;
+#endif
+
+#if defined (FLASH_OPTR_DBANK)
+    if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
+    {
+      /* Configure the Proprietary code readout protection */
+      if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
+      {
+        reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
+        MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
+
+        reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
+        MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
+      }
+      else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
+      {
+        reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
+        MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
+
+        reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
+        MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+    else
+#endif
+    {
+      /* Configure the Proprietary code readout protection */
+      if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
+      {
+        reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
+        MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
+
+        reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
+        MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
+      }
+#if defined (FLASH_OPTR_DBANK)
+      else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
+      {
+        reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
+        MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
+
+        reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
+        MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
+      }
+#endif
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+
+    MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
+
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the Securable memory area into Option Bytes.
+  * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+  *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+  * @note   New option bytes configuration will be taken into account in two cases:
+  *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+  *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+  * @param  SecBank specifies bank of securable memory area to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Securable memory in Bank1 to be configured
+  *            @arg FLASH_BANK_2: Securable memory in Bank2 to be configured (*)
+  * @note   (*) availability depends on devices
+  * @param  SecSize specifies the number of pages of the Securable memory area,
+  *         starting from first page of the bank.
+  *         This parameter can be page number between 0 and (max number of pages in the bank - 1)
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecBank, uint32_t SecSize)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(SecBank));
+  assert_param(IS_OB_SECMEM_SIZE(SecSize));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    /* Configure the write protected area */
+    if (SecBank == FLASH_BANK_1)
+    {
+      MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1, SecSize);
+    }
+#if defined (FLASH_OPTR_DBANK)
+    else if (SecBank == FLASH_BANK_2)
+    {
+      MODIFY_REG(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2, SecSize);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+#endif
+
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the Boot Lock into Option Bytes.
+  * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+  *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+  * @note   New option bytes configuration will be taken into account in two cases:
+  *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+  *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+  * @param  BootLockConfig specifies the boot lock configuration.
+  *          This parameter can be one of the following values:
+  *            @arg OB_BOOT_LOCK_ENABLE: Enable Boot Lock
+  *            @arg OB_BOOT_LOCK_DISABLE: Disable Boot Lock
+  *
+  * @retval HAL_Status
+  */
+static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT_LOCK(BootLockConfig));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_BOOT_LOCK, BootLockConfig);
+
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Return the Securable memory area configuration into Option Bytes.
+  * @param[in]  SecBank specifies the bank where securable memory area is located.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Securable memory in Bank1
+  *            @arg FLASH_BANK_2: Securable memory in Bank2 (*)
+  * @note   (*) availability depends on devices
+  * @param[out]  SecSize specifies the number of pages used in the securable
+                 memory area of the bank.
+  * @retval None
+  */
+static void FLASH_OB_GetSecMem(uint32_t SecBank, uint32_t *SecSize)
+{
+  /* Get the configuration of the securable memory area */
+  if (SecBank == FLASH_BANK_1)
+  {
+    *SecSize = READ_BIT(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1);
+  }
+#if defined (FLASH_OPTR_DBANK)
+  else if (SecBank == FLASH_BANK_2)
+  {
+    *SecSize = READ_BIT(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+#endif
+}
+
+/**
+  * @brief  Return the Boot Lock configuration into Option Byte.
+  * @retval BootLockConfig.
+  *         This return value can be one of the following values:
+  *            @arg OB_BOOT_LOCK_ENABLE: Boot lock enabled
+  *            @arg OB_BOOT_LOCK_DISABLE: Boot lock disabled
+  */
+static uint32_t FLASH_OB_GetBootLock(void)
+{
+  return (READ_REG(FLASH->SEC1R) & FLASH_SEC1R_BOOT_LOCK);
+}
+
+/**
+  * @brief  Return the Write Protection configuration into Option Bytes.
+  * @param[in]  WRPArea specifies the area to be returned.
+  *          This parameter can be one of the following values:
+  *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
+  *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
+  *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32G43x/STM32G44x devices)
+  *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32G43x/STM32G44x devices)
+  * @param[out]  WRPStartOffset specifies the address where to copied the start page
+  *              of the write protected area.
+  * @param[out]  WRDPEndOffset specifies the address where to copied the end page of
+  *              the write protected area.
+  * @retval None
+  */
+static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
+{
+  /* Get the configuration of the write protected area */
+  if (WRPArea == OB_WRPAREA_BANK1_AREAA)
+  {
+    *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos);
+  }
+  else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
+  {
+    *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos);
+  }
+#if defined (FLASH_OPTR_DBANK)
+  else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
+  {
+    *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos);
+  }
+  else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
+  {
+    *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos);
+  }
+#endif
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  Return the FLASH Read Protection level into Option Bytes.
+  * @retval RDP_Level
+  *         This return value can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  */
+static uint32_t FLASH_OB_GetRDP(void)
+{
+  uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
+
+  if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
+  {
+    return (OB_RDP_LEVEL_1);
+  }
+  else
+  {
+    return rdp_level;
+  }
+}
+
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval OB_user_config
+  *         This return value is a combination of @ref FLASH_OB_USER_BOR_LEVEL,
+  *         @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
+  *         @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
+  *         @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
+  *         @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW,
+  *         @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_DBANK (*),
+  *         @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE,
+  *         @ref FLASH_OB_USER_CCMSRAM_RST, @ref OB_USER_nSWBOOT0,@ref FLASH_OB_USER_nBOOT0,
+  *         @ref FLASH_OB_USER_NRST_MODE, @ref FLASH_OB_USER_INTERNAL_RESET_HOLDER
+  * @note  (*) availability depends on devices
+  */
+static uint32_t FLASH_OB_GetUser(void)
+{
+  uint32_t user_config = READ_REG(FLASH->OPTR);
+  CLEAR_BIT(user_config, FLASH_OPTR_RDP);
+
+  return user_config;
+}
+
+/**
+  * @brief  Return the FLASH PCROP configuration into Option Bytes.
+  * @param[in,out] PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP option).
+  *        This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
+  *        with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE.
+  * @param[out] PCROPStartAddr specifies the address where to copied the start address
+  *        of the Proprietary code readout protection.
+  * @param[out] PCROPEndAddr specifies the address where to copied the end address of
+  *        the Proprietary code readout protection.
+  * @retval None
+  */
+static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr)
+{
+  uint32_t reg_value;
+  uint32_t bank1_addr;
+#if defined (FLASH_OPTR_DBANK)
+  uint32_t bank2_addr;
+
+  /* Get the information about the bank swapping */
+  if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)
+  {
+    bank1_addr = FLASH_BASE;
+    bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
+  }
+  else
+  {
+    bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
+    bank2_addr = FLASH_BASE;
+  }
+#else
+  bank1_addr = FLASH_BASE;
+#endif
+
+#if defined (FLASH_OPTR_DBANK)
+  if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
+  {
+    if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
+    {
+      reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
+      *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
+
+      reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
+      *PCROPEndAddr = (reg_value << 4) + FLASH_BASE;
+    }
+    else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
+    {
+      reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
+      *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
+
+      reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
+      *PCROPEndAddr = (reg_value << 4) + FLASH_BASE;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+  else
+#endif
+  {
+    if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
+    {
+      reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
+      *PCROPStartAddr = (reg_value << 3) + bank1_addr;
+
+      reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
+      *PCROPEndAddr = (reg_value << 3) + bank1_addr;
+    }
+#if defined (FLASH_OPTR_DBANK)
+    else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
+    {
+      reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
+      *PCROPStartAddr = (reg_value << 3) + bank2_addr;
+
+      reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
+      *PCROPEndAddr = (reg_value << 3) + bank2_addr;
+    }
+#endif
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c
new file mode 100644
index 0000000..f12a1a8
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c
@@ -0,0 +1,253 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_flash_ramfunc.c
+  * @author  MCD Application Team
+  * @brief   FLASH RAMFUNC driver.
+  *          This file provides a Flash firmware functions which should be
+  *          executed from internal SRAM
+  *            + FLASH Power Down in Run mode
+  *            + FLASH DBANK User Option Byte
+  *
+  *
+  @verbatim
+  ==============================================================================
+                   ##### Flash RAM functions #####
+  ==============================================================================
+
+    *** ARM Compiler ***
+    --------------------
+    [..] RAM functions are defined using the toolchain options.
+         Functions that are executed in RAM should reside in a separate
+         source module. Using the 'Options for File' dialog you can simply change
+         the 'Code / Const' area of a module to a memory space in physical RAM.
+         Available memory areas are declared in the 'Target' tab of the
+         Options for Target' dialog.
+
+    *** ICCARM Compiler ***
+    -----------------------
+    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
+
+    *** GNU Compiler ***
+    --------------------
+    [..] RAM functions are defined using a specific toolchain attribute
+         "__attribute__((section(".RamFunc")))".
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
+  * @brief FLASH functions executed from RAM
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions -------------------------------------------------------*/
+
+/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH_RAMFUNC Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### ramfunc functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions that should be executed from RAM.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the Power down in Run Mode
+  * @note   This function should be called and executed from SRAM memory.
+  * @retval None
+  */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
+{
+  /* Enable the Power Down in Run mode*/
+  __HAL_FLASH_POWER_DOWN_ENABLE();
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Disable the Power down in Run Mode
+  * @note   This function should be called and executed from SRAM memory.
+  * @retval None
+  */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
+{
+  /* Disable the Power Down in Run mode*/
+  __HAL_FLASH_POWER_DOWN_DISABLE();
+
+  return HAL_OK;
+}
+
+#if defined (FLASH_OPTR_DBANK)
+/**
+  * @brief  Program the FLASH DBANK User Option Byte.
+  *
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To modify the DBANK option byte, no PCROP region should be defined.
+  *         To deactivate PCROP, user should perform RDP changing.
+  *
+  * @param  DBankConfig The FLASH DBANK User Option Byte value.
+  *         This parameter  can be one of the following values:
+  *            @arg OB_DBANK_128_BITS: Single-bank with 128-bits data
+  *            @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data
+  *
+  * @retval HAL_Status
+  */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig)
+{
+  uint32_t count, reg;
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check if the PCROP is disabled */
+  reg = FLASH->PCROP1SR;
+  if (reg > FLASH->PCROP1ER)
+  {
+    reg = FLASH->PCROP2SR;
+    if (reg > FLASH->PCROP2ER)
+    {
+      /* Disable Flash prefetch */
+      __HAL_FLASH_PREFETCH_BUFFER_DISABLE();
+
+      if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
+      {
+        /* Disable Flash instruction cache */
+        __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+
+        /* Flush Flash instruction cache */
+        __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+      }
+
+      if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
+      {
+        /* Disable Flash data cache */
+        __HAL_FLASH_DATA_CACHE_DISABLE();
+
+        /* Flush Flash data cache */
+        __HAL_FLASH_DATA_CACHE_RESET();
+      }
+
+      /* Disable WRP zone A of 1st bank if needed */
+      reg = FLASH->WRP1AR;
+      if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <=
+          ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos))
+      {
+        MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT);
+      }
+
+      /* Disable WRP zone B of 1st bank if needed */
+      reg = FLASH->WRP1BR;
+      if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <=
+          ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos))
+      {
+        MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT);
+      }
+
+      /* Disable WRP zone A of 2nd bank if needed */
+      reg = FLASH->WRP2AR;
+      if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <=
+          ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos))
+      {
+        MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT);
+      }
+
+      /* Disable WRP zone B of 2nd bank if needed */
+      reg = FLASH->WRP2BR;
+      if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <=
+          ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos))
+      {
+        MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT);
+      }
+
+      /* Modify the DBANK user option byte */
+      MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig);
+
+      /* Set OPTSTRT Bit */
+      SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+      /* Wait for last operation to be completed */
+      /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */
+      count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U);
+      do
+      {
+        if (count == 0U)
+        {
+          break;
+        }
+        count--;
+      }
+      while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET);
+
+      /* If the option byte program operation is completed, disable the OPTSTRT Bit */
+      CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+      /* Set the bit to force the option byte reloading */
+      SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c
new file mode 100644
index 0000000..b735929
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c
@@ -0,0 +1,532 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+        configured by software in several modes:
+        (++) Input mode
+        (++) Analog mode
+        (++) Output mode
+        (++) Alternate function mode
+        (++) External interrupt/event lines
+
+    (+) During and just after reset, the alternate functions and external interrupt
+        lines are not active and the I/O ports are configured in input floating mode.
+
+    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+        activated or not.
+
+    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+        type and the IO speed can be selected depending on the VDD value.
+
+    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+        multiplexer that allows only one peripheral alternate function (AF) connected
+       to an IO pin at a time. In this way, there can be no conflict between peripherals
+       sharing the same IO pin.
+
+    (+) All ports have external interrupt/event capability. To use external interrupt
+        lines, the port must be configured in input mode. All available GPIO pins are
+        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+    (+) The external interrupt/event controller consists of up to 44 edge detectors
+        (16 lines are connected to GPIO) for generating event/interrupt requests (each
+        input line can be independently configured to select the type (interrupt or event)
+        and the corresponding trigger event (rising or falling or both). Each line can
+        also be masked independently.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from
+             GPIO_InitTypeDef structure select the type (interrupt or event) and
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+    (#) To set/reset the level of a pin configured in output mode use
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+    (#) During and just after reset, the alternate functions are not
+        active and the GPIO pins are configured in input floating mode (except JTAG
+        pins).
+
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+        priority over the GPIO function.
+
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+        general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
+        The HSE has priority over the GPIO function.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+/** MISRA C:2012 deviation rule has been granted for following rules:
+  * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
+  * range of the shift operator in following API :
+  * HAL_GPIO_Init
+  * HAL_GPIO_DeInit
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+#define GPIO_NUMBER           (16U)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup GPIO_Exported_Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
+  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position = 0x00U;
+  uint32_t iocurrent;
+  uint32_t temp;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0U)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1UL << position);
+
+    if (iocurrent != 0x00u)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
+         ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+        temp |= (GPIO_Init->Speed << (position * 2U));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;
+        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+        GPIOx->OTYPER = temp;
+      }
+
+      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+      {
+        /* Check the Pull parameter */
+        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+        /* Activate the Pull-up or Pull down resistor for the current IO */
+        temp = GPIOx->PUPDR;
+        temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+        temp |= ((GPIO_Init->Pull) << (position * 2U));
+        GPIOx->PUPDR = temp;
+      }
+
+      /* In case of Alternate function mode selection */
+      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+      {
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3U];
+        temp &= ~(0xFU << ((position & 0x07U) * 4U));
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
+        GPIOx->AFR[position >> 3U] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+      GPIOx->MODER = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+        temp = SYSCFG->EXTICR[position >> 2U];
+        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+        SYSCFG->EXTICR[position >> 2U] = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR1 = temp;
+
+        temp = EXTI->FTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR1 = temp;
+
+        temp = EXTI->EMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->EMR1 = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI->IMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->IMR1 = temp;
+      }
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position = 0x00U;
+  uint32_t iocurrent;
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Configure the port pins */
+  while ((GPIO_Pin >> position) != 0U)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Pin) & (1UL << position);
+
+    if (iocurrent != 0x00u)
+    {
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      /* Clear the External Interrupt or Event for the current IO */
+
+      tmp = SYSCFG->EXTICR[position >> 2U];
+      tmp &= (0x0FUL << (4U * (position & 0x03U)));
+      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+      {
+        /* Clear EXTI line configuration */
+        EXTI->IMR1 &= ~(iocurrent);
+        EXTI->EMR1 &= ~(iocurrent);
+
+        /* Clear Rising Falling edge configuration */
+        EXTI->FTSR1 &= ~(iocurrent);
+        EXTI->RTSR1 &= ~(iocurrent);
+
+        tmp = 0x0FUL << (4U * (position & 0x03U));
+        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
+      }
+
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO in Analog Mode */
+      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u));
+
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position);
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+  *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+  *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read the specified input port pin.
+  * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
+  * @param  GPIO_Pin specifies the port bit to read.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Set or clear the selected data port bit.
+  *
+  * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  *
+  * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @param  PinState specifies the value to be written to the selected bit.
+  *         This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRR = (uint32_t)GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Toggle the specified GPIO pin.
+  * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
+  * @param  GPIO_Pin specifies the pin to be toggled.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  uint32_t odr;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* get current Output Data Register value */
+  odr = GPIOx->ODR;
+
+  /* Set selected pins that were at low level, and reset ones that were high */
+  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+}
+
+/**
+  * @brief  Lock GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
+  * @param  GPIO_Pin specifies the port bits to be locked.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK register. This read is mandatory to complete key lock sequence */
+  tmp = GPIOx->LCKR;
+
+  /* read again in order to confirm lock is active */
+  if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+  /* EXTI line interrupt detected */
+  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+}
+
+/**
+  * @brief  EXTI line detection callback.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c
new file mode 100644
index 0000000..54c8246
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c
@@ -0,0 +1,6884 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_i2c.c
+  * @author  MCD Application Team
+  * @brief   I2C HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The I2C HAL driver can be used as follows:
+
+    (#) Declare a I2C_HandleTypeDef handle structure, for example:
+        I2C_HandleTypeDef  hi2c;
+
+    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+        (##) Enable the I2Cx interface clock
+        (##) I2C pins configuration
+            (+++) Enable the clock for the I2C GPIOs
+            (+++) Configure I2C pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the I2Cx interrupt priority
+            (+++) Enable the NVIC I2C IRQ Channel
+        (##) DMA Configuration if you need to use DMA process
+            (+++) Declare a DMA_HandleTypeDef handle structure for
+                  the transmit or receive channel
+            (+++) Enable the DMAx interface clock using
+            (+++) Configure the DMA handle parameters
+            (+++) Configure the DMA Tx or Rx channel
+            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+                  the DMA Tx or Rx channel
+
+    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+
+    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+
+    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+
+    *** Polling mode IO MEM operation ***
+    =====================================
+    [..]
+      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+
+    *** Interrupt mode or DMA mode IO sequential operation ***
+    ==========================================================
+    [..]
+      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+          when a direction change during transfer
+    [..]
+      (+) A specific option field manage the different steps of a sequential transfer
+      (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
+      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
+           no sequential mode
+      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition
+      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
+                            start condition, address and data to transfer without a final stop condition,
+                            an then permit a call the same master sequential interface several times
+                            (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
+                            or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
+      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to
+                            transfer
+                            if no direction change and without a final stop condition in both cases
+      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to
+                            transfer
+                            if no direction change and with a final stop condition in both cases
+      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
+                            after several call of the same master sequential interface several times
+                            (link with option I2C_FIRST_AND_NEXT_FRAME).
+                            Usage can, transfer several bytes one by one using
+                              HAL_I2C_Master_Seq_Transmit_IT
+                              or HAL_I2C_Master_Seq_Receive_IT
+                              or HAL_I2C_Master_Seq_Transmit_DMA
+                              or HAL_I2C_Master_Seq_Receive_DMA
+                              with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
+                             Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
+                              Receive sequence permit to call the opposite interface Receive or Transmit
+                              without stopping the communication and so generate a restart condition.
+      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
+                            each call of the same master sequential
+                            interface.
+                            Usage can, transfer several bytes one by one with a restart with slave address between
+                            each bytes using
+                              HAL_I2C_Master_Seq_Transmit_IT
+                              or HAL_I2C_Master_Seq_Receive_IT
+                              or HAL_I2C_Master_Seq_Transmit_DMA
+                              or HAL_I2C_Master_Seq_Receive_DMA
+                              with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
+                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
+                            generation of STOP condition.
+
+      (+) Different sequential I2C interfaces are listed below:
+      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
+            users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
+            HAL_I2C_DisableListen_IT()
+      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
+           add their own code to check the Address Match Code and the transmission direction request by master
+           (Write/Read).
+      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
+          add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
+            users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** Interrupt mode IO MEM operation ***
+    =======================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+          HAL_I2C_Mem_Write_IT()
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+          HAL_I2C_Mem_Read_IT()
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+    *** DMA mode IO operation ***
+    ==============================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Master_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Master_Receive_DMA()
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Slave_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Slave_Receive_DMA()
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** DMA mode IO MEM operation ***
+    =================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+          HAL_I2C_Mem_Write_DMA()
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+          HAL_I2C_Mem_Read_DMA()
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+
+     *** I2C HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in I2C HAL driver.
+
+      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+     *** Callback registration ***
+     =============================================
+    [..]
+     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
+     to register an interrupt callback.
+    [..]
+     Function HAL_I2C_RegisterCallback() allows to register following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+     For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
+    [..]
+     Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
+     weak function.
+     HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+    [..]
+     For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
+    [..]
+     By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
+     these callbacks are null (not registered beforehand).
+     If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+    [..]
+     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
+     or HAL_I2C_Init() function.
+    [..]
+     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+     [..]
+       (@) You can refer to the I2C HAL driver header file for more useful macros
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2C I2C
+  * @brief I2C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+  * @{
+  */
+#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
+#define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE      255U
+#define SLAVE_ADDR_SHIFT     7U
+#define SLAVE_ADDR_MSK       0x06U
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
+                                                         (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
+                                              (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
+/*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))
+/*!< Default Value */
+#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /*!< Bit field can be combinated with
+                                                         @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /*!< Bit field can be combinated with
+                                                         @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
+                                                         and @ref I2C_XFER_RX_IT */
+
+#define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /*!< Bit definition to manage addition of global Error
+                                                         and NACK treatment */
+#define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /*!< Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /*!< Bit definition to manage only Reload of NBYTE */
+
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Macro to get remaining data to transfer on DMA side */
+#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__)     __HAL_DMA_GET_COUNTER(__HANDLE__)
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions to handle DMA transfer */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+/* Private functions to handle IT transfer */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                                uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                               uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                               uint32_t Tickstart);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                          uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                            uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+                                                    uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                             uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/* Private function to flush TXDR register */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+
+/* Private function to handle  start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+                               uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the I2Cx peripheral:
+
+      (+) User must Implement HAL_I2C_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_I2C_Init() to configure the selected device with
+          the selected configuration:
+        (++) Clock Timing
+        (++) Own Address 1
+        (++) Addressing mode (Master, Slave)
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) Own Address 2 Mask
+        (++) General call mode
+        (++) Nostretch mode
+
+      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+          of the selected I2Cx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the I2C according to the specified parameters
+  *         in the I2C_InitTypeDef and initialize the associated handle.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+  if (hi2c->State == HAL_I2C_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hi2c->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    /* Init the I2C Callback settings */
+    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
+    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
+    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
+    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
+    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
+    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
+
+    if (hi2c->MspInitCallback == NULL)
+    {
+      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    hi2c->MspInitCallback(hi2c);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+  /* Configure I2Cx: Frequency range */
+  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Disable Own Address1 before set the Own Address1 configuration */
+  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+  /* Configure I2Cx: Own Address1 and ack own address1 mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+  }
+  else /* I2C_ADDRESSINGMODE_10BIT */
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+  }
+
+  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+  /* Configure I2Cx: Addressing Master mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+  {
+    hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+  }
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+  /* Disable Own Address2 before set the Own Address2 configuration */
+  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
+  /* Configure I2Cx: Dual mode and Own Address2 */
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
+                          (hi2c->Init.OwnAddress2Masks << 8));
+
+  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+  /* Configure I2Cx: Generalcall and NoStretch mode */
+  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+  /* Enable the selected I2C peripheral */
+  __HAL_I2C_ENABLE(hi2c);
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the I2C peripheral.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the I2C Peripheral Clock */
+  __HAL_I2C_DISABLE(hi2c);
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  if (hi2c->MspDeInitCallback == NULL)
+  {
+    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  hi2c->MspDeInitCallback(hi2c);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_RESET;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User I2C Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+                                           pI2C_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = pCallback;
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Unregister an I2C Callback
+  *         I2C callback is redirected to the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Register the Slave Address Match I2C Callback
+  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pCallback pointer to the Address Match Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Slave Address Match I2C Callback
+  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2C data
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2C_Master_Transmit()
+        (++) HAL_I2C_Master_Receive()
+        (++) HAL_I2C_Slave_Transmit()
+        (++) HAL_I2C_Slave_Receive()
+        (++) HAL_I2C_Mem_Write()
+        (++) HAL_I2C_Mem_Read()
+        (++) HAL_I2C_IsDeviceReady()
+
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2C_Master_Transmit_IT()
+        (++) HAL_I2C_Master_Receive_IT()
+        (++) HAL_I2C_Slave_Transmit_IT()
+        (++) HAL_I2C_Slave_Receive_IT()
+        (++) HAL_I2C_Mem_Write_IT()
+        (++) HAL_I2C_Mem_Read_IT()
+        (++) HAL_I2C_Master_Seq_Transmit_IT()
+        (++) HAL_I2C_Master_Seq_Receive_IT()
+        (++) HAL_I2C_Slave_Seq_Transmit_IT()
+        (++) HAL_I2C_Slave_Seq_Receive_IT()
+        (++) HAL_I2C_EnableListen_IT()
+        (++) HAL_I2C_DisableListen_IT()
+        (++) HAL_I2C_Master_Abort_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2C_Master_Transmit_DMA()
+        (++) HAL_I2C_Master_Receive_DMA()
+        (++) HAL_I2C_Slave_Transmit_DMA()
+        (++) HAL_I2C_Slave_Receive_DMA()
+        (++) HAL_I2C_Mem_Write_DMA()
+        (++) HAL_I2C_Mem_Read_DMA()
+        (++) HAL_I2C_Master_Seq_Transmit_DMA()
+        (++) HAL_I2C_Master_Seq_Receive_DMA()
+        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+        (++) HAL_I2C_Slave_Seq_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2C_MasterTxCpltCallback()
+        (++) HAL_I2C_MasterRxCpltCallback()
+        (++) HAL_I2C_SlaveTxCpltCallback()
+        (++) HAL_I2C_SlaveRxCpltCallback()
+        (++) HAL_I2C_MemTxCpltCallback()
+        (++) HAL_I2C_MemRxCpltCallback()
+        (++) HAL_I2C_AddrCallback()
+        (++) HAL_I2C_ListenCpltCallback()
+        (++) HAL_I2C_ErrorCallback()
+        (++) HAL_I2C_AbortCpltCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                          uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                         I2C_GENERATE_START_WRITE);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_WRITE);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                         uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                         I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmits in slave mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                         uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* If 10bit addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      /* Wait until ADDR flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Wait until DIR flag is set Transmitter mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until AF flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+
+    /* Clear AF flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in blocking mode
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                        uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferSize = hi2c->XferCount;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Wait until DIR flag is reset Receiver mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        /* Store Last receive data if any */
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+        {
+          /* Read data from RXDR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          hi2c->XferCount--;
+          hi2c->XferSize--;
+        }
+
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                             uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                            uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                              uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA channel */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                         hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                             uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA channel */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                         hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                       hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                       hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in blocking mode to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+    }
+
+    do
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+      }
+
+    } while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in blocking mode from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                   uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                         I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
+    }
+
+    do
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+      }
+    } while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
+        != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                      uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
+        != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                       hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Send Slave Address */
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                       hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Checks if target device is ready for communication.
+  * @note   This function is used with Memory devices
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+                                        uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  __IO uint32_t I2C_Trials = 0UL;
+
+  FlagStatus tmp1;
+  FlagStatus tmp2;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    do
+    {
+      /* Generate Start */
+      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
+
+      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+      /* Wait until STOPF flag is set or a NACK flag is set*/
+      tickstart = HAL_GetTick();
+
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+
+      while ((tmp1 == RESET) && (tmp2 == RESET))
+      {
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Update I2C state */
+            hi2c->State = HAL_I2C_STATE_READY;
+
+            /* Update I2C error code */
+            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+
+            return HAL_ERROR;
+          }
+        }
+
+        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+      }
+
+      /* Check if the NACKF flag has not been set */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Device is ready */
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_OK;
+      }
+      else
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Clear STOP Flag, auto generated with autoend*/
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+      /* Check if the maximum allowed number of trials has been reached */
+      if (I2C_Trials == Trials)
+      {
+        /* Generate Stop */
+        hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+      /* Increment Trials */
+      I2C_Trials++;
+    } while (I2C_Trials < Trials);
+
+    /* Update I2C state */
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Update I2C error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                 uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to write */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                  uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA channel */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                         hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to write */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to read */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                 uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA channel */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                         hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to read */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      /* Abort DMA Xfer if any */
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                 uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                       hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* Enable ERR, STOP, NACK, ADDR interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                               uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
+                                       (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    hi2c->State = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR = I2C_Slave_ISR_IT;
+
+    /* Enable the Address Match interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp;
+
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if (hi2c->State == HAL_I2C_STATE_LISTEN)
+  {
+    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+    hi2c->XferISR = NULL;
+
+    /* Disable the Address Match interrupt */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+  if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts and Store Previous state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    }
+    else
+    {
+      /* Do nothing */
+    }
+
+    /* Set State at HAL_I2C_STATE_ABORT */
+    hi2c->State = HAL_I2C_STATE_ABORT;
+
+    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Wrong usage of abort function */
+    /* This function should be used only in case of abort monitored by master device */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+  * @{
+  */
+
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  /* Get current IT Flags and IT sources value */
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+  /* I2C events treatment -------------------------------------*/
+  if (hi2c->XferISR != NULL)
+  {
+    hi2c->XferISR(hi2c, itflags, itsources);
+  }
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmperror;
+
+  /* I2C Bus error interrupt occurred ------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+  }
+
+  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+  }
+
+  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+  }
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the Error Callback in case of Error detected */
+  if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
+  {
+    I2C_ITError(hi2c, tmperror);
+  }
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+  * @param  AddrMatchCode Address Match Code
+  * @retval None
+  */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C error callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C abort callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  *  @brief   Peripheral State, Mode and Error functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2C handle state.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL state
+  */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+  /* Return I2C handle state */
+  return hi2c->State;
+}
+
+/**
+  * @brief  Returns the I2C Master, Slave, Memory or no mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL mode
+  */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->Mode;
+}
+
+/**
+  * @brief  Return the I2C error code.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *              the configuration information for the specified I2C.
+  * @retval I2C Error Code
+  */
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    /* Error callback will be send during stop flag treatment */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR */
+    hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+    {
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+                             hi2c->XferOptions, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+                             I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, tmpITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                          uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, tmpITFlags);
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hi2c->XferCount == 0U)
+    {
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+        /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+           Warning[Pa134]: left and right operands are identical */
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, tmpITFlags);
+      }
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      }
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, hi2c->ErrorCode);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    if (hi2c->XferCount > 0U)
+    {
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+
+    if ((hi2c->XferCount == 0U) && \
+        (tmpoptions != I2C_NO_OPTION_FRAME))
+    {
+      /* Call I2C Slave Sequential complete process */
+      I2C_ITSlaveSeqCplt(hi2c);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, tmpITFlags);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR only if XferCount not reach "0" */
+    /* A TXIS flag can be set, during STOP treatment      */
+    /* Check if all Data have already been sent */
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+    if (hi2c->XferCount > 0U)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+    else
+    {
+      if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+      {
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                            uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t xfermode;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* No need to generate STOP, it is automatically done */
+    /* But enable STOP interrupt, to treat it */
+    /* Error callback will be send during stop flag treatment */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable TC interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+
+    if (hi2c->XferCount != 0U)
+    {
+      /* Recover Slave address */
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      /* Prepare the new XferSize to transfer */
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        xfermode = I2C_RELOAD_MODE;
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          xfermode = hi2c->XferOptions;
+        }
+        else
+        {
+          xfermode = I2C_AUTOEND_MODE;
+        }
+      }
+
+      /* Set the new XferSize in Nbytes register */
+      I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Enable DMA Request */
+      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t treatdmanack = 0U;
+  HAL_I2C_StateTypeDef tmpstate;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, ITFlags);
+  }
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0 */
+    /* So clear Flag NACKF only */
+    if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+        (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+    {
+      /* Split check of hdmarx, for MISRA compliance */
+      if (hi2c->hdmarx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+        {
+          if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      /* Split check of hdmatx, for MISRA compliance  */
+      if (hi2c->hdmatx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+        {
+          if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      if (treatdmanack == 1U)
+      {
+        if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+          /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+             Warning[Pa134]: left and right operands are identical */
+        {
+          /* Call I2C Listen complete process */
+          I2C_ITListenCplt(hi2c, ITFlags);
+        }
+        else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+          /* Flush TX register */
+          I2C_Flush_TXDR(hi2c);
+
+          /* Last Byte is Transmitted */
+          /* Call I2C Slave Sequential complete process */
+          I2C_ITSlaveSeqCplt(hi2c);
+        }
+        else
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+        }
+      }
+      else
+      {
+        /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Set ErrorCode corresponding to a Non-Acknowledge */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+        /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+        tmpstate = hi2c->State;
+
+        if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+        {
+          if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+          }
+          else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+          }
+          else
+          {
+            /* Do nothing */
+          }
+
+          /* Call the corresponding callback to inform upper layer of End of Transfer */
+          I2C_ITError(hi2c, hi2c->ErrorCode);
+        }
+      }
+    }
+    else
+    {
+      /* Only Clear NACK Flag, no DMA treatment is pending */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for write request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                                uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TCR flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for read request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                               uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                               uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TC flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  I2C Address complete process callback.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint8_t transferdirection;
+  uint16_t slaveaddrcode;
+  uint16_t ownadd1code;
+  uint16_t ownadd2code;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ITFlags);
+
+  /* In case of Listen state, need to inform upper layer of address match code event */
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    transferdirection = I2C_GET_DIR(hi2c);
+    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+
+    /* If 10bits addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
+      {
+        slaveaddrcode = ownadd1code;
+        hi2c->AddrEventCount++;
+        if (hi2c->AddrEventCount == 2U)
+        {
+          /* Reset Address Event counter */
+          hi2c->AddrEventCount = 0U;
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        slaveaddrcode = ownadd2code;
+
+        /* Disable ADDR Interrupts */
+        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+    /* else 7 bits addressing mode is selected */
+    else
+    {
+      /* Disable ADDR Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* Else clear address flag only */
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Master sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* No Generate Stop, to permit restart mode */
+  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterTxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterRxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Slave sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Master complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmperror;
+  uint32_t tmpITFlags = ITFlags;
+  __IO uint32_t tmpreg;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+  }
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Reset handle parameters */
+  hi2c->XferISR       = NULL;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set acknowledge error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  /* Fetch Last receive data if any */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+  {
+    /* Read data from RXDR */
+    tmpreg = (uint8_t)hi2c->Instance->RXDR;
+    UNUSED(tmpreg);
+  }
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Slave complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmpITFlags = ITFlags;
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+  }
+  else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Disable Address Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
+    }
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
+    }
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if ((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+  }
+
+  /* All data are not transferred, so set error code accordingly */
+  if (hi2c->XferCount != 0U)
+  {
+    /* Set ErrorCode corresponding to a Non-Acknowledge */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    if (hi2c->State == HAL_I2C_STATE_LISTEN)
+    {
+      /* Call I2C Listen complete process */
+      I2C_ITListenCplt(hi2c, tmpITFlags);
+    }
+  }
+  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+  {
+    /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
+    I2C_ITSlaveSeqCplt(hi2c);
+
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ListenCpltCallback(hi2c);
+#else
+    HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Listen complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  /* Reset handle parameters */
+  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if ((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+  }
+
+  /* Disable all Interrupts*/
+  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+  /* Clear NACK Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  hi2c->ListenCpltCallback(hi2c);
+#else
+  HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  I2C interrupts error process.
+  * @param  hi2c I2C handle.
+  * @param  ErrorCode Error code to handle.
+  * @retval None
+  */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+  uint32_t tmppreviousstate;
+
+  /* Reset handle parameters */
+  hi2c->Mode          = HAL_I2C_MODE_NONE;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+  hi2c->XferCount     = 0U;
+
+  /* Set new error code */
+  hi2c->ErrorCode |= ErrorCode;
+
+  /* Disable Interrupts */
+  if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
+      (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+      (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    /* Disable all interrupts, except interrupts related to LISTEN state */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* keep HAL_I2C_STATE_LISTEN if set */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR       = I2C_Slave_ISR_IT;
+  }
+  else
+  {
+    /* Disable all interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* If state is an abort treatment on going, don't change state */
+    /* This change will be do later */
+    if (hi2c->State != HAL_I2C_STATE_ABORT)
+    {
+      /* Set HAL_I2C_STATE_READY */
+      hi2c->State         = HAL_I2C_STATE_READY;
+    }
+    hi2c->XferISR       = NULL;
+  }
+
+  /* Abort DMA TX transfer if any */
+  tmppreviousstate = hi2c->PreviousState;
+  if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
+                                 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+      {
+        /* Call Directly XferAbortCallback function in case of error */
+        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  /* Abort DMA RX transfer if any */
+  else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
+                                      (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  else
+  {
+    I2C_TreatErrorCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Error callback treatment.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AbortCpltCallback(hi2c);
+#else
+    HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Tx data register flush process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+  /* If a pending TXIS flag is set */
+  /* Write a dummy data in TXDR to clear it */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+  {
+    hi2c->Instance->TXDR = 0x00U;
+  }
+
+  /* Flush TX register if not empty */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  {
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+  }
+}
+
+/**
+  * @brief  DMA I2C master transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA channel */
+    if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+                         hi2c->XferSize) != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+/**
+  * @brief  DMA I2C slave transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    /* Last Byte is Transmitted */
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+/**
+  * @brief DMA I2C master receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA channel */
+    if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
+                         hi2c->XferSize) != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+/**
+  * @brief  DMA I2C slave receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
+      (tmpoptions != I2C_NO_OPTION_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+/**
+  * @brief  DMA I2C communication error callback.
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Disable Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+}
+
+/**
+  * @brief DMA I2C communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Reset AbortCpltCallback */
+  if (hi2c->hdmatx != NULL)
+  {
+    hi2c->hdmatx->XferAbortCallback = NULL;
+  }
+  if (hi2c->hdmarx != NULL)
+  {
+    hi2c->hdmarx->XferAbortCallback = NULL;
+  }
+
+  I2C_TreatErrorCallback(hi2c);
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout. It waits
+  *                until a flag is no longer in the specified status.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Flag Specifies the I2C flag to check.
+  * @param  Status The actual Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+                                                    uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+  {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+  {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State = HAL_I2C_STATE_READY;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+  {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check if a STOPF is detected */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+    {
+      /* Check if an RXNE is pending */
+      /* Store Last receive data if any */
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+      {
+        /* Return HAL_OK */
+        /* The Reading of data from RXDR will be done in caller function */
+        return HAL_OK;
+      }
+      else
+      {
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+        {
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+          hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+        }
+        else
+        {
+          hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Clear Configuration Register 2 */
+        I2C_RESET_CR2(hi2c);
+
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles errors detection during an I2C Communication.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t itflag   = hi2c->Instance->ISR;
+  uint32_t error_code = 0;
+  uint32_t tickstart = Tickstart;
+  uint32_t tmp1;
+  HAL_I2C_ModeTypeDef tmp2;
+
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
+  {
+    /* Clear NACKF Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Wait until STOP Flag is set or timeout occurred */
+    /* AutoEnd should be initiate after AF */
+    while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
+          tmp2 = hi2c->Mode;
+
+          /* In case of I2C still busy, try to regenerate a STOP manually */
+          if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
+              (tmp1 != I2C_CR2_STOP) && \
+              (tmp2 != HAL_I2C_MODE_SLAVE))
+          {
+            /* Generate Stop */
+            hi2c->Instance->CR2 |= I2C_CR2_STOP;
+            
+            /* Update Tick with new reference */
+            tickstart = HAL_GetTick();
+          }
+          
+          while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+          {
+            /* Check for the Timeout */
+            if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
+            {
+              hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+              hi2c->State = HAL_I2C_STATE_READY;
+              hi2c->Mode = HAL_I2C_MODE_NONE;
+              
+              /* Process Unlocked */
+              __HAL_UNLOCK(hi2c);
+              
+              status = HAL_ERROR;
+            }
+          }
+        }
+      }
+    }
+
+    /* In case STOP Flag is detected, clear it */
+    if (status == HAL_OK)
+    {
+      /* Clear STOP Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+    }
+
+    error_code |= HAL_I2C_ERROR_AF;
+
+    status = HAL_ERROR;
+  }
+
+  /* Refresh Content of Status register */
+  itflag = hi2c->Instance->ISR;
+
+  /* Then verify if an additional errors occurs */
+  /* Check if a Bus error occurred */
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
+  {
+    error_code |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+
+    status = HAL_ERROR;
+  }
+
+  /* Check if an Over-Run/Under-Run error occurred */
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
+  {
+    error_code |= HAL_I2C_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+
+    status = HAL_ERROR;
+  }
+
+  /* Check if an Arbitration Loss error occurred */
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
+  {
+    error_code |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+
+    status = HAL_ERROR;
+  }
+
+  if (status != HAL_OK)
+  {
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->ErrorCode |= error_code;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  hi2c I2C handle.
+  * @param  DevAddress Specifies the slave address to be programmed.
+  * @param  Size Specifies the number of bytes to be programmed.
+  *   This parameter must be a value between 0 and 255.
+  * @param  Mode New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+  * @param  Request New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+  * @retval None
+  */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+                               uint32_t Request)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_TRANSFER_MODE(Mode));
+  assert_param(IS_TRANSFER_REQUEST(Request));
+
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+                            (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+                              (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+
+  /* update CR2 register */
+  MODIFY_REG(hi2c->Instance->CR2, \
+             ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+               (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
+                I2C_CR2_START | I2C_CR2_STOP)), tmp);
+}
+
+/**
+  * @brief  Manage the enabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+      (hi2c->XferISR == I2C_Slave_ISR_DMA))
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if (InterruptRequest == I2C_XFER_ERROR_IT)
+    {
+      /* Enable ERR and NACK interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+    }
+
+    if (InterruptRequest == I2C_XFER_RELOAD_IT)
+    {
+      /* Enable TC interrupts */
+      tmpisr |= I2C_IT_TCI;
+    }
+  }
+  else
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK, and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= I2C_IT_STOPI;
+    }
+  }
+
+  /* Enable interrupts only at the end */
+  /* to avoid the risk of I2C interrupt handle execution before */
+  /* all interrupts requested done */
+  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Manage the disabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+  {
+    /* Disable TC and TXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+  {
+    /* Disable TC and RXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+  {
+    /* Disable ADDR, NACK and STOP interrupts */
+    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+  }
+
+  if (InterruptRequest == I2C_XFER_ERROR_IT)
+  {
+    /* Enable ERR and NACK interrupts */
+    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+  }
+
+  if (InterruptRequest == I2C_XFER_CPLT_IT)
+  {
+    /* Enable STOP interrupts */
+    tmpisr |= I2C_IT_STOPI;
+  }
+
+  if (InterruptRequest == I2C_XFER_RELOAD_IT)
+  {
+    /* Enable TC interrupts */
+    tmpisr |= I2C_IT_TCI;
+  }
+
+  /* Disable interrupts only at the end */
+  /* to avoid a breaking situation like at "t" time */
+  /* all disable interrupts request are not done */
+  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+  /* if user set XferOptions to I2C_OTHER_FRAME            */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to I2C_FIRST_FRAME                    */
+  if (hi2c->XferOptions == I2C_OTHER_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+  /* it request implicitly to generate a restart condition    */
+  /* then generate a stop condition at the end of transfer    */
+  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
+  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c
new file mode 100644
index 0000000..b2e51cf
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c
@@ -0,0 +1,368 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_i2c_ex.c
+  * @author  MCD Application Team
+  * @brief   I2C Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of I2C Extended peripheral:
+  *           + Filter Mode Functions
+  *           + WakeUp Mode Functions
+  *           + FastModePlus Functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### I2C peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the I2C interface for STM32G4xx
+       devices contains the following additional features
+
+       (+) Possibility to disable or enable Analog Noise Filter
+       (+) Use of a configured Digital Noise Filter
+       (+) Disable or enable wakeup from Stop mode(s)
+       (+) Disable or enable Fast Mode Plus
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+          (++) HAL_I2CEx_EnableWakeUp()
+          (++) HAL_I2CEx_DisableWakeUp()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_I2CEx_EnableFastModePlus()
+          (++) HAL_I2CEx_DisableFastModePlus()
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2CEx I2CEx
+  * @brief I2C Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
+  * @brief    Filter Mode Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Filter Mode Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Noise Filters
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure I2C Analog noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter New state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Reset I2Cx ANOFF bit */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hi2c->Instance->CR1 |= AnalogFilter;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure I2C Digital noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Get the old register value */
+    tmpreg = hi2c->Instance->CR1;
+
+    /* Reset I2Cx DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << 8U;
+
+    /* Store the new register value */
+    hi2c->Instance->CR1 = tmpreg;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
+  * @brief    WakeUp Mode Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### WakeUp Mode Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Wake Up Feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
+  * @brief    Fast Mode Plus Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Fast Mode Plus Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Fast Mode Plus
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Enable fast mode plus driving capability for selected pin */
+  SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @brief Disable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Disable fast mode plus driving capability for selected pin */
+  CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c
new file mode 100644
index 0000000..4bc9bef
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c
@@ -0,0 +1,2222 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_pcd.c
+  * @author  MCD Application Team
+  * @brief   PCD HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The PCD HAL driver can be used as follows:
+
+     (#) Declare a PCD_HandleTypeDef handle structure, for example:
+         PCD_HandleTypeDef  hpcd;
+
+     (#) Fill parameters of Init structure in HCD handle
+
+     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
+
+     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+         (##) Enable the PCD/USB Low Level interface clock using
+              (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral
+
+         (##) Initialize the related GPIO clocks
+         (##) Configure PCD pin-out
+         (##) Configure PCD NVIC interrupt
+
+     (#)Associate the Upper USB device stack to the HAL PCD Driver:
+         (##) hpcd.pData = pdev;
+
+     (#)Enable PCD transmission and reception:
+         (##) HAL_PCD_Start();
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCD PCD
+  * @brief PCD HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined (USB)
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+  * @{
+  */
+#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
+#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+  * @{
+  */
+
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
+static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+  * @{
+  */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the PCD according to the specified
+  *         parameters in the PCD_InitTypeDef and initialize the associated handle.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{
+  uint8_t i;
+
+  /* Check the PCD handle allocation */
+  if (hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+
+  if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hpcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->SOFCallback = HAL_PCD_SOFCallback;
+    hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+    hpcd->ResetCallback = HAL_PCD_ResetCallback;
+    hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+    hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+    hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+    hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
+    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
+    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
+    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
+    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
+    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
+
+    if (hpcd->MspInitCallback == NULL)
+    {
+      hpcd->MspInitCallback = HAL_PCD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hpcd->MspInitCallback(hpcd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_PCD_MspInit(hpcd);
+#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
+  }
+
+  hpcd->State = HAL_PCD_STATE_BUSY;
+
+  /* Disable the Interrupts */
+  __HAL_PCD_DISABLE(hpcd);
+
+  /* Init endpoints structures */
+  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+  {
+    /* Init ep structure */
+    hpcd->IN_ep[i].is_in = 1U;
+    hpcd->IN_ep[i].num = i;
+    hpcd->IN_ep[i].tx_fifo_num = i;
+    /* Control until ep is activated */
+    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
+    hpcd->IN_ep[i].maxpacket = 0U;
+    hpcd->IN_ep[i].xfer_buff = 0U;
+    hpcd->IN_ep[i].xfer_len = 0U;
+  }
+
+  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+  {
+    hpcd->OUT_ep[i].is_in = 0U;
+    hpcd->OUT_ep[i].num = i;
+    /* Control until ep is activated */
+    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
+    hpcd->OUT_ep[i].maxpacket = 0U;
+    hpcd->OUT_ep[i].xfer_buff = 0U;
+    hpcd->OUT_ep[i].xfer_len = 0U;
+  }
+
+  /* Init Device */
+  (void)USB_DevInit(hpcd->Instance, hpcd->Init);
+
+  hpcd->USB_Address = 0U;
+  hpcd->State = HAL_PCD_STATE_READY;
+
+  /* Activate LPM */
+  if (hpcd->Init.lpm_enable == 1U)
+  {
+    (void)HAL_PCDEx_ActivateLPM(hpcd);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the PCD peripheral.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Check the PCD handle allocation */
+  if (hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hpcd->State = HAL_PCD_STATE_BUSY;
+
+  /* Stop Device */
+  if (USB_StopDevice(hpcd->Instance) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  if (hpcd->MspDeInitCallback == NULL)
+  {
+    hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hpcd->MspDeInitCallback(hpcd);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_PCD_MspDeInit(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+  hpcd->State = HAL_PCD_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the PCD MSP.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes PCD MSP.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User USB PCD Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hpcd USB PCD handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+                                           HAL_PCD_CallbackIDTypeDef CallbackID,
+                                           pPCD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_SOF_CB_ID :
+        hpcd->SOFCallback = pCallback;
+        break;
+
+      case HAL_PCD_SETUPSTAGE_CB_ID :
+        hpcd->SetupStageCallback = pCallback;
+        break;
+
+      case HAL_PCD_RESET_CB_ID :
+        hpcd->ResetCallback = pCallback;
+        break;
+
+      case HAL_PCD_SUSPEND_CB_ID :
+        hpcd->SuspendCallback = pCallback;
+        break;
+
+      case HAL_PCD_RESUME_CB_ID :
+        hpcd->ResumeCallback = pCallback;
+        break;
+
+      case HAL_PCD_CONNECT_CB_ID :
+        hpcd->ConnectCallback = pCallback;
+        break;
+
+      case HAL_PCD_DISCONNECT_CB_ID :
+        hpcd->DisconnectCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+  return status;
+}
+
+/**
+  * @brief  Unregister an USB PCD Callback
+  *         USB PCD callabck is redirected to the weak predefined callback
+  * @param  hpcd USB PCD handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  /* Setup Legacy weak Callbacks  */
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_SOF_CB_ID :
+        hpcd->SOFCallback = HAL_PCD_SOFCallback;
+        break;
+
+      case HAL_PCD_SETUPSTAGE_CB_ID :
+        hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+        break;
+
+      case HAL_PCD_RESET_CB_ID :
+        hpcd->ResetCallback = HAL_PCD_ResetCallback;
+        break;
+
+      case HAL_PCD_SUSPEND_CB_ID :
+        hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+        break;
+
+      case HAL_PCD_RESUME_CB_ID :
+        hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+        break;
+
+      case HAL_PCD_CONNECT_CB_ID :
+        hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+        break;
+
+      case HAL_PCD_DISCONNECT_CB_ID :
+        hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+        break;
+
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = HAL_PCD_MspInit;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = HAL_PCD_MspInit;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Data OUT Stage Callback
+  *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+                                                       pPCD_DataOutStageCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataOutStageCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB PCD Data OUT Stage Callback
+  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Data IN Stage Callback
+  *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Data IN Stage Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+                                                      pPCD_DataInStageCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataInStageCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB PCD Data IN Stage Callback
+  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Iso OUT incomplete Callback
+  *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+                                                       pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOOUTIncompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB PCD Iso OUT incomplete Callback
+  *         USB PCD Iso OUT incomplete Callback is redirected
+  *         to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Iso IN incomplete Callback
+  *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+                                                      pPCD_IsoInIncpltCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOINIncompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB PCD Iso IN incomplete Callback
+  *         USB PCD Iso IN incomplete Callback is redirected
+  *         to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD BCD Callback
+  *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD BCD Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->BCDCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB PCD BCD Callback
+  *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD LPM Callback
+  *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD LPM Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->LPMCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB PCD LPM Callback
+  *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the PCD data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the USB device
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  __HAL_PCD_ENABLE(hpcd);
+  (void)USB_DevConnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the USB device.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  __HAL_PCD_DISABLE(hpcd);
+  (void)USB_DevDisconnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  This function handles PCD interrupt request.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+  uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
+
+  if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
+  {
+    /* servicing of the endpoint correct transfer interrupt */
+    /* clear of the CTR flag into the sub */
+    (void)PCD_EP_ISR_Handler(hpcd);
+
+    return;
+  }
+
+  if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->ResetCallback(hpcd);
+#else
+    HAL_PCD_ResetCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+    (void)HAL_PCD_SetAddress(hpcd, 0U);
+
+    return;
+  }
+
+  if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
+
+    return;
+  }
+
+  if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
+
+    return;
+  }
+
+  if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
+  {
+    hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
+    hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
+
+    if (hpcd->LPM_State == LPM_L1)
+    {
+      hpcd->LPM_State = LPM_L0;
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
+#else
+      HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->ResumeCallback(hpcd);
+#else
+    HAL_PCD_ResumeCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
+
+    return;
+  }
+
+  if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
+  {
+    /* Force low-power mode in the macrocell */
+    hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
+
+    /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
+
+    hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->SuspendCallback(hpcd);
+#else
+    HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+    return;
+  }
+
+  /* Handle LPM Interrupt */
+  if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ)
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
+    if (hpcd->LPM_State == LPM_L0)
+    {
+      /* Force suspend and low-power mode before going to L1 state*/
+      hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
+      hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
+
+      hpcd->LPM_State = LPM_L1;
+      hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
+#else
+      HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+    else
+    {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->SuspendCallback(hpcd);
+#else
+      HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+
+    return;
+  }
+
+  if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->SOFCallback(hpcd);
+#else
+    HAL_PCD_SOFCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+    return;
+  }
+
+  if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
+  {
+    /* clear ESOF flag in ISTR */
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
+
+    return;
+  }
+}
+
+
+/**
+  * @brief  Data OUT stage callback.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Data IN stage callback
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DataInStageCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Setup stage callback
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SetupStageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  USB Start Of Frame callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SOFCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  USB Reset callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ResetCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Suspend event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SuspendCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Resume event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ResumeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Incomplete ISO OUT callback.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Incomplete ISO IN callback.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Connection event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ConnectCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Disconnection event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DisconnectCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   management functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the PCD data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Connect the USB device
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  (void)USB_DevConnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disconnect the USB device.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  (void)USB_DevDisconnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the USB Device address.
+  * @param  hpcd PCD handle
+  * @param  address new device address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+  __HAL_LOCK(hpcd);
+  hpcd->USB_Address = address;
+  (void)USB_SetDevAddress(hpcd->Instance, address);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Open and configure an endpoint.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  ep_mps endpoint max packet size
+  * @param  ep_type endpoint type
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+                                  uint16_t ep_mps, uint8_t ep_type)
+{
+  HAL_StatusTypeDef  ret = HAL_OK;
+  PCD_EPTypeDef *ep;
+
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
+  }
+
+  ep->num = ep_addr & EP_ADDR_MSK;
+  ep->maxpacket = ep_mps;
+  ep->type = ep_type;
+
+  if (ep->is_in != 0U)
+  {
+    /* Assign a Tx FIFO */
+    ep->tx_fifo_num = ep->num;
+  }
+  /* Set initial data PID. */
+  if (ep_type == EP_TYPE_BULK)
+  {
+    ep->data_pid_start = 0U;
+  }
+
+  __HAL_LOCK(hpcd);
+  (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+
+  return ret;
+}
+
+/**
+  * @brief  Deactivate an endpoint.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
+  }
+  ep->num   = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+  (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Receive an amount of data.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  pBuf pointer to the reception buffer
+  * @param  len amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  PCD_EPTypeDef *ep;
+
+  ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;
+  ep->xfer_len = len;
+  ep->xfer_count = 0U;
+  ep->is_in = 0U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  if ((ep_addr & EP_ADDR_MSK) == 0U)
+  {
+    (void)USB_EP0StartXfer(hpcd->Instance, ep);
+  }
+  else
+  {
+    (void)USB_EPStartXfer(hpcd->Instance, ep);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get Received Data Size
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval Data Size
+  */
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
+}
+/**
+  * @brief  Send an amount of data
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  pBuf pointer to the transmission buffer
+  * @param  len amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  PCD_EPTypeDef *ep;
+
+  ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;
+  ep->xfer_len = len;
+  ep->xfer_fill_db = 1U;
+  ep->xfer_len_db = len;
+  ep->xfer_count = 0U;
+  ep->is_in = 1U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  if ((ep_addr & EP_ADDR_MSK) == 0U)
+  {
+    (void)USB_EP0StartXfer(hpcd->Instance, ep);
+  }
+  else
+  {
+    (void)USB_EPStartXfer(hpcd->Instance, ep);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set a STALL condition over an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+
+  if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+    ep->is_in = 0U;
+  }
+
+  ep->is_stall = 1U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+
+  (void)USB_EPSetStall(hpcd->Instance, ep);
+
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Clear a STALL condition over in an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+
+  if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
+  }
+
+  ep->is_stall = 0U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+  (void)USB_EPClearStall(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Flush an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(ep_addr);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate remote wakeup signalling
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  return (USB_ActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+  * @brief  De-activate remote wakeup signalling.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  return (USB_DeActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the PCD handle state.
+  * @param  hpcd PCD handle
+  * @retval HAL state
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+  return hpcd->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup PCD_Private_Functions
+  * @{
+  */
+
+
+/**
+  * @brief  This function handles PCD Endpoint interrupt request.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
+{
+  PCD_EPTypeDef *ep;
+  uint16_t count;
+  uint16_t wIstr;
+  uint16_t wEPVal;
+  uint16_t TxPctSize;
+  uint8_t epindex;
+
+  /* stay in loop while pending interrupts */
+  while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
+  {
+    wIstr = hpcd->Instance->ISTR;
+
+    /* extract highest priority endpoint number */
+    epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
+
+    if (epindex == 0U)
+    {
+      /* Decode and service control endpoint interrupt */
+
+      /* DIR bit = origin of the interrupt */
+      if ((wIstr & USB_ISTR_DIR) == 0U)
+      {
+        /* DIR = 0 */
+
+        /* DIR = 0 => IN  int */
+        /* DIR = 0 implies that (EP_CTR_TX = 1) always */
+        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+        ep = &hpcd->IN_ep[0];
+
+        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+        ep->xfer_buff += ep->xfer_count;
+
+        /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DataInStageCallback(hpcd, 0U);
+#else
+        HAL_PCD_DataInStageCallback(hpcd, 0U);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+        if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
+        {
+          hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
+          hpcd->USB_Address = 0U;
+        }
+      }
+      else
+      {
+        /* DIR = 1 */
+
+        /* DIR = 1 & CTR_RX => SETUP or OUT int */
+        /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+        ep = &hpcd->OUT_ep[0];
+        wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+
+        if ((wEPVal & USB_EP_SETUP) != 0U)
+        {
+          /* Get SETUP Packet */
+          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+
+          USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
+                      ep->pmaadress, (uint16_t)ep->xfer_count);
+
+          /* SETUP bit kept frozen while CTR_RX = 1 */
+          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+
+          /* Process SETUP Packet*/
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+          hpcd->SetupStageCallback(hpcd);
+#else
+          HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+        }
+        else if ((wEPVal & USB_EP_CTR_RX) != 0U)
+        {
+          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+
+          /* Get Control Data OUT Packet */
+          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+
+          if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
+          {
+            USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
+                        ep->pmaadress, (uint16_t)ep->xfer_count);
+
+            ep->xfer_buff += ep->xfer_count;
+
+            /* Process Control Data OUT Packet */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+            hpcd->DataOutStageCallback(hpcd, 0U);
+#else
+            HAL_PCD_DataOutStageCallback(hpcd, 0U);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+          }
+
+          if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U)
+          {
+            PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
+            PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Decode and service non control endpoints interrupt */
+      /* process related endpoint register */
+      wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
+
+      if ((wEPVal & USB_EP_CTR_RX) != 0U)
+      {
+        /* clear int flag */
+        PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
+        ep = &hpcd->OUT_ep[epindex];
+
+        /* OUT Single Buffering */
+        if (ep->doublebuffer == 0U)
+        {
+          count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+
+          if (count != 0U)
+          {
+            USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
+          }
+        }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+        else
+        {
+          /* manage double buffer bulk out */
+          if (ep->type == EP_TYPE_BULK)
+          {
+            count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
+          }
+          else /* manage double buffer iso out */
+          {
+            /* free EP OUT Buffer */
+            PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
+
+            if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
+            {
+              /* read from endpoint BUF0Addr buffer */
+              count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+
+              if (count != 0U)
+              {
+                USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+              }
+            }
+            else
+            {
+              /* read from endpoint BUF1Addr buffer */
+              count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+
+              if (count != 0U)
+              {
+                USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+              }
+            }
+          }
+        }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+        /* multi-packet on the NON control OUT endpoint */
+        ep->xfer_count += count;
+        ep->xfer_buff += count;
+
+        if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
+        {
+          /* RX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+          hpcd->DataOutStageCallback(hpcd, ep->num);
+#else
+          HAL_PCD_DataOutStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+        }
+        else
+        {
+          (void) USB_EPStartXfer(hpcd->Instance, ep);
+        }
+      }
+
+      if ((wEPVal & USB_EP_CTR_TX) != 0U)
+      {
+        ep = &hpcd->IN_ep[epindex];
+
+        /* clear int flag */
+        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
+
+        if (ep->type != EP_TYPE_BULK)
+        {
+          ep->xfer_len = 0U;
+
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+          if (ep->doublebuffer != 0U)
+          {
+            if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+            {
+              PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+            }
+            else
+            {
+              PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+            }
+          }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+          /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+          hpcd->DataInStageCallback(hpcd, ep->num);
+#else
+          HAL_PCD_DataInStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+        }
+        else
+        {
+          /* Manage Bulk Single Buffer Transaction */
+          if ((wEPVal & USB_EP_KIND) == 0U)
+          {
+            /* multi-packet on the NON control IN endpoint */
+            TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+
+            if (ep->xfer_len > TxPctSize)
+            {
+              ep->xfer_len -= TxPctSize;
+            }
+            else
+            {
+              ep->xfer_len = 0U;
+            }
+
+            /* Zero Length Packet? */
+            if (ep->xfer_len == 0U)
+            {
+              /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+              hpcd->DataInStageCallback(hpcd, ep->num);
+#else
+              HAL_PCD_DataInStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+            }
+            else
+            {
+              /* Transfer is not yet Done */
+              ep->xfer_buff += TxPctSize;
+              ep->xfer_count += TxPctSize;
+              (void)USB_EPStartXfer(hpcd->Instance, ep);
+            }
+          }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+          /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
+          else
+          {
+            (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
+          }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+        }
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+/**
+  * @brief  Manage double buffer bulk out transaction from ISR
+  * @param  hpcd PCD handle
+  * @param  ep current endpoint handle
+  * @param  wEPVal Last snapshot of EPRx register value taken in ISR
+  * @retval HAL status
+  */
+static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
+                                      PCD_EPTypeDef *ep, uint16_t wEPVal)
+{
+  uint16_t count;
+
+  /* Manage Buffer0 OUT */
+  if ((wEPVal & USB_EP_DTOG_RX) != 0U)
+  {
+    /* Get count of received Data on buffer0 */
+    count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+
+    if (ep->xfer_len >= count)
+    {
+      ep->xfer_len -= count;
+    }
+    else
+    {
+      ep->xfer_len = 0U;
+    }
+
+    if (ep->xfer_len == 0U)
+    {
+      /* set NAK to OUT endpoint since double buffer is enabled */
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
+    }
+
+    /* Check if Buffer1 is in blocked state which requires to toggle */
+    if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+    {
+      PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
+    }
+
+    if (count != 0U)
+    {
+      USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+    }
+  }
+  /* Manage Buffer 1 DTOG_RX=0 */
+  else
+  {
+    /* Get count of received data */
+    count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+
+    if (ep->xfer_len >= count)
+    {
+      ep->xfer_len -= count;
+    }
+    else
+    {
+      ep->xfer_len = 0U;
+    }
+
+    if (ep->xfer_len == 0U)
+    {
+      /* set NAK on the current endpoint */
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
+    }
+
+    /*Need to FreeUser Buffer*/
+    if ((wEPVal & USB_EP_DTOG_TX) == 0U)
+    {
+      PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
+    }
+
+    if (count != 0U)
+    {
+      USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+    }
+  }
+
+  return count;
+}
+
+
+/**
+  * @brief  Manage double buffer bulk IN transaction from ISR
+  * @param  hpcd PCD handle
+  * @param  ep current endpoint handle
+  * @param  wEPVal Last snapshot of EPRx register value taken in ISR
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
+                                                PCD_EPTypeDef *ep, uint16_t wEPVal)
+{
+  uint32_t len;
+  uint16_t TxPctSize;
+
+  /* Data Buffer0 ACK received */
+  if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+  {
+    /* multi-packet on the NON control IN endpoint */
+    TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+
+    if (ep->xfer_len > TxPctSize)
+    {
+      ep->xfer_len -= TxPctSize;
+    }
+    else
+    {
+      ep->xfer_len = 0U;
+    }
+
+    /* Transfer is completed */
+    if (ep->xfer_len == 0U)
+    {
+      PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+      PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+
+      /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->DataInStageCallback(hpcd, ep->num);
+#else
+      HAL_PCD_DataInStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      if ((wEPVal & USB_EP_DTOG_RX) != 0U)
+      {
+        PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
+      }
+    }
+    else /* Transfer is not yet Done */
+    {
+      /* need to Free USB Buff */
+      if ((wEPVal & USB_EP_DTOG_RX) != 0U)
+      {
+        PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
+      }
+
+      /* Still there is data to Fill in the next Buffer */
+      if (ep->xfer_fill_db == 1U)
+      {
+        ep->xfer_buff += TxPctSize;
+        ep->xfer_count += TxPctSize;
+
+        /* Calculate the len of the new buffer to fill */
+        if (ep->xfer_len_db >= ep->maxpacket)
+        {
+          len = ep->maxpacket;
+          ep->xfer_len_db -= len;
+        }
+        else if (ep->xfer_len_db == 0U)
+        {
+          len = TxPctSize;
+          ep->xfer_fill_db = 0U;
+        }
+        else
+        {
+          ep->xfer_fill_db = 0U;
+          len = ep->xfer_len_db;
+          ep->xfer_len_db = 0U;
+        }
+
+        /* Write remaining Data to Buffer */
+        /* Set the Double buffer counter for pma buffer1 */
+        PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+
+        /* Copy user buffer to USB PMA */
+        USB_WritePMA(hpcd->Instance, ep->xfer_buff,  ep->pmaaddr0, (uint16_t)len);
+      }
+    }
+  }
+  else /* Data Buffer1 ACK received */
+  {
+    /* multi-packet on the NON control IN endpoint */
+    TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+
+    if (ep->xfer_len >= TxPctSize)
+    {
+      ep->xfer_len -= TxPctSize;
+    }
+    else
+    {
+      ep->xfer_len = 0U;
+    }
+
+    /* Transfer is completed */
+    if (ep->xfer_len == 0U)
+    {
+      PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+      PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+
+      /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->DataInStageCallback(hpcd, ep->num);
+#else
+      HAL_PCD_DataInStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      /* need to Free USB Buff */
+      if ((wEPVal & USB_EP_DTOG_RX) == 0U)
+      {
+        PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
+      }
+    }
+    else /* Transfer is not yet Done */
+    {
+      /* need to Free USB Buff */
+      if ((wEPVal & USB_EP_DTOG_RX) == 0U)
+      {
+        PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
+      }
+
+      /* Still there is data to Fill in the next Buffer */
+      if (ep->xfer_fill_db == 1U)
+      {
+        ep->xfer_buff += TxPctSize;
+        ep->xfer_count += TxPctSize;
+
+        /* Calculate the len of the new buffer to fill */
+        if (ep->xfer_len_db >= ep->maxpacket)
+        {
+          len = ep->maxpacket;
+          ep->xfer_len_db -= len;
+        }
+        else if (ep->xfer_len_db == 0U)
+        {
+          len = TxPctSize;
+          ep->xfer_fill_db = 0U;
+        }
+        else
+        {
+          len = ep->xfer_len_db;
+          ep->xfer_len_db = 0U;
+          ep->xfer_fill_db = 0;
+        }
+
+        /* Set the Double buffer counter for pmabuffer1 */
+        PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+
+        /* Copy the user buffer to USB PMA */
+        USB_WritePMA(hpcd->Instance, ep->xfer_buff,  ep->pmaaddr1, (uint16_t)len);
+      }
+    }
+  }
+
+  /*enable endpoint IN*/
+  PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+
+  return HAL_OK;
+}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+
+
+/**
+  * @}
+  */
+#endif /* defined (USB) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c
new file mode 100644
index 0000000..60d761e
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c
@@ -0,0 +1,335 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_pcd_ex.c
+  * @author  MCD Application Team
+  * @brief   PCD Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCDEx PCDEx
+  * @brief PCD Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined (USB)
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @brief    PCDEx control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Update FIFO configuration
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure PMA for EP
+  * @param  hpcd  Device instance
+  * @param  ep_addr endpoint address
+  * @param  ep_kind endpoint Kind
+  *                  USB_SNG_BUF: Single Buffer used
+  *                  USB_DBL_BUF: Double Buffer used
+  * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
+  *                   this parameter is 16-bit value providing the address
+  *                   in PMA allocated to endpoint.
+  *                   In case of double buffer endpoint this parameter
+  *                   is a 32-bit value providing the endpoint buffer 0 address
+  *                   in the LSB part of 32-bit value and endpoint buffer 1 address
+  *                   in the MSB part of 32-bit value.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
+                                       uint16_t ep_kind, uint32_t pmaadress)
+{
+  PCD_EPTypeDef *ep;
+
+  /* initialize ep structure*/
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+  }
+
+  /* Here we check if the endpoint is single or double Buffer*/
+  if (ep_kind == PCD_SNG_BUF)
+  {
+    /* Single Buffer */
+    ep->doublebuffer = 0U;
+    /* Configure the PMA */
+    ep->pmaadress = (uint16_t)pmaadress;
+  }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+  else /* USB_DBL_BUF */
+  {
+    /* Double Buffer Endpoint */
+    ep->doublebuffer = 1U;
+    /* Configure the PMA */
+    ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
+    ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
+  }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate BatteryCharging feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_TypeDef *USBx = hpcd->Instance;
+  hpcd->battery_charging_active = 1U;
+
+  /* Enable BCD feature */
+  USBx->BCDR |= USB_BCDR_BCDEN;
+
+  /* Enable DCD : Data Contact Detect */
+  USBx->BCDR &= ~(USB_BCDR_PDEN);
+  USBx->BCDR &= ~(USB_BCDR_SDEN);
+  USBx->BCDR |= USB_BCDR_DCDEN;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate BatteryCharging feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_TypeDef *USBx = hpcd->Instance;
+  hpcd->battery_charging_active = 0U;
+
+  /* Disable BCD feature */
+  USBx->BCDR &= ~(USB_BCDR_BCDEN);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle BatteryCharging Process.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+  USB_TypeDef *USBx = hpcd->Instance;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Wait Detect flag or a timeout is happen */
+  while ((USBx->BCDR & USB_BCDR_DCDET) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > 1000U)
+    {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      return;
+    }
+  }
+
+  HAL_Delay(200U);
+
+  /* Data Pin Contact ? Check Detect flag */
+  if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
+  {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+  /* Primary detection: checks if connected to Standard Downstream Port
+  (without charging capability) */
+  USBx->BCDR &= ~(USB_BCDR_DCDEN);
+  HAL_Delay(50U);
+  USBx->BCDR |= (USB_BCDR_PDEN);
+  HAL_Delay(50U);
+
+  /* If Charger detect ? */
+  if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)
+  {
+    /* Start secondary detection to check connection to Charging Downstream
+    Port or Dedicated Charging Port */
+    USBx->BCDR &= ~(USB_BCDR_PDEN);
+    HAL_Delay(50U);
+    USBx->BCDR |= (USB_BCDR_SDEN);
+    HAL_Delay(50U);
+
+    /* If CDP ? */
+    if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)
+    {
+      /* Dedicated Downstream Port DCP */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Charging Downstream Port CDP */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+  }
+  else /* NO */
+  {
+    /* Standard Downstream Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+
+  /* Battery Charging capability discovery finished Start Enumeration */
+  (void)HAL_PCDEx_DeActivateBCD(hpcd);
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#else
+  HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  Activate LPM feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+
+  USB_TypeDef *USBx = hpcd->Instance;
+  hpcd->lpm_active = 1U;
+  hpcd->LPM_State = LPM_L0;
+
+  USBx->LPMCSR |= USB_LPMCSR_LMPEN;
+  USBx->LPMCSR |= USB_LPMCSR_LPMACK;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate LPM feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_TypeDef *USBx = hpcd->Instance;
+
+  hpcd->lpm_active = 0U;
+
+  USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
+  USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
+
+  return HAL_OK;
+}
+
+
+
+/**
+  * @brief  Send LPM message to user layer callback.
+  * @param  hpcd PCD handle
+  * @param  msg LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_LPM_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Send BatteryCharging message to user layer callback.
+  * @param  hpcd PCD handle
+  * @param  msg LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_BCD_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c
new file mode 100644
index 0000000..7127cb4
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c
@@ -0,0 +1,652 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR PWR
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Defines PWR Private Defines
+  * @{
+  */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  * @{
+  */
+#define PVD_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVD threshold crossing */
+#define PVD_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVD threshold crossing        */
+#define PVD_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVD trigger                 */
+#define PVD_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVD trigger                */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
+  * @retval None
+  */
+void HAL_PWR_DeInit(void)
+{
+  __HAL_RCC_PWR_FORCE_RESET();
+  __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+  * @brief Enable access to the backup domain
+  *        (RTC registers, RTC backup data registers).
+  * @note  After reset, the backup domain is protected against
+  *        possible unwanted write accesses.
+  * @note  RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
+  *        In order to set or modify the RTC clock, the backup domain access must be
+  *        disabled.
+  * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the
+  *        back-up domain.
+  * @retval None
+  */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief Disable access to the backup domain
+  *        (RTC registers, RTC backup data registers).
+  * @retval None
+  */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+
+
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
+  *  @brief Low Power modes configuration functions
+  *
+@verbatim
+
+ ===============================================================================
+                 ##### Peripheral Control functions #####
+ ===============================================================================
+
+     [..]
+     *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a
+          threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
+
+      (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
+          than the PVD threshold. This event is internally connected to the EXTI
+          line16 and can generate an interrupt if enabled. This is done through
+          __HAL_PVD_EXTI_ENABLE_IT() macro.
+      (+) The PVD is stopped in Standby mode.
+
+
+    *** WakeUp pin configuration ***
+    ================================
+    [..]
+      (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
+          The polarity of these pins can be set to configure event detection on high
+          level (rising edge) or low level (falling edge).
+
+
+
+    *** Low Power modes configuration ***
+    =====================================
+    [..]
+      The devices feature 8 low-power modes:
+      (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
+      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
+      (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
+      (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
+      (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
+      (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
+      (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
+      (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
+
+
+   *** Low-power run mode ***
+   ==========================
+    [..]
+      (+) Entry: (from main run mode)
+        (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
+
+      (+) Exit:
+        (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
+             then can the system clock frequency be increased above 2 MHz.
+
+
+   *** Sleep mode / Low-power sleep mode ***
+   =========================================
+    [..]
+      (+) Entry:
+          The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
+          in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
+          (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
+          (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
+          In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+
+      (+) WFI Exit:
+        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
+             controller (NVIC) or any wake-up event.
+
+      (+) WFE Exit:
+        (++) Any wake-up event such as an EXTI line configured in event mode.
+
+         [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
+             the MCU is in Low-power Run mode.
+
+   *** Stop 0, Stop 1 modes ***
+   ===============================
+    [..]
+      (+) Entry:
+          The Stop 0, Stop 1 modes are entered through the following API's:
+          (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
+      (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
+          (++) PWR_MAINREGULATOR_ON
+          (++) PWR_LOWPOWERREGULATOR_ON
+      (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
+          (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
+          (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
+
+      (+) WFI Exit:
+          (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
+          (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
+               when programmed in wakeup mode.
+      (+) WFE Exit:
+          (++) Any EXTI Line (Internal or External) configured in Event mode.
+
+       [..]
+          When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
+          depending on the LPR bit setting.
+
+   *** Standby mode ***
+   ====================
+     [..]
+      The Standby mode offers two options:
+      (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
+        SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
+        and Standby circuitry.
+      (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
+        SRAM and register contents are lost except for the RTC registers, RTC backup registers
+        and Standby circuitry.
+
+      (++) Entry:
+          (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
+                SRAM1 and register contents are lost except for registers in the Backup domain and
+                Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
+                To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
+                to set RRS bit.
+
+      (++) Exit:
+          (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
+                external reset in NRST pin, IWDG reset.
+
+      [..]    After waking up from Standby mode, program execution restarts in the same way as after a Reset.
+
+
+    *** Shutdown mode ***
+   ======================
+     [..]
+      In Shutdown mode,
+        voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
+        SRAM and registers contents are lost except for backup domain registers.
+
+      (+) Entry:
+          The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
+
+      (+) Exit:
+          (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
+               external reset in NRST pin.
+
+         [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
+
+
+   *** Auto-wakeup (AWU) from low-power mode ***
+   =============================================
+    [..]
+      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
+      Wakeup event, a tamper event or a time-stamp event, without depending on
+      an external interrupt (Auto-wakeup mode).
+
+      (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
+
+
+        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
+             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
+             is necessary to configure the RTC to detect the tamper or time stamp event using the
+             HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
+
+        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
+              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+  * @{
+  */
+
+
+
+/**
+  * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
+  * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
+  *        configuration information.
+  * @note Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage thresholds corresponding to each
+  *         detection level.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+
+  /* Set PLS bits according to PVDLevel value */
+  MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
+
+  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+  __HAL_PWR_PVD_EXTI_DISABLE_IT();
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+
+  /* Configure interrupt mode */
+  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_IT();
+  }
+
+  /* Configure event mode */
+  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+  }
+
+  /* Configure the edge */
+  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+  }
+
+  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief Enable the Power Voltage Detector (PVD).
+  * @retval None
+  */
+void HAL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_PVDE);
+}
+
+/**
+  * @brief Disable the Power Voltage Detector (PVD).
+  * @retval None
+  */
+void HAL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
+}
+
+
+
+
+/**
+  * @brief Enable the WakeUp PINx functionality.
+  * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
+  *         This parameter can be one of the following legacy values which set the default polarity
+  *         i.e. detection on high level (rising edge):
+  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
+  *
+  *         or one of the following value where the user can explicitly specify the enabled pin and
+  *         the chosen polarity:
+  *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
+  *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
+  *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
+  *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
+  *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
+  * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
+  * @retval None
+  */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
+{
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
+
+  /* Specifies the Wake-Up pin polarity for the event detection
+    (rising or falling edge) */
+  MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
+
+  /* Enable wake-up pin */
+  SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
+
+
+}
+
+/**
+  * @brief Disable the WakeUp PINx functionality.
+  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+  *         This parameter can be one of the following values:
+  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
+  * @retval None
+  */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+
+  CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
+}
+
+
+/**
+  * @brief Enter Sleep or Low-power Sleep mode.
+  * @note  In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
+  * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
+  *            @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
+  * @note  Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
+  *        in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
+  *        to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
+  *        Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
+  *        Additionally, the clock frequency must be reduced below 2 MHz.
+  *        Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
+  *        be done before calling HAL_PWR_EnterSLEEPMode() API.
+  * @note  When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
+  *        Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
+  * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
+  *           This parameter can be one of the following values:
+  *            @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
+  *            @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
+  * @note  When WFI entry is used, tick interrupt have to be disabled if not desired as
+  *        the interrupt wake up source.
+  * @retval None
+  */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+  /* Set Regulator parameter */
+  if (Regulator == PWR_MAINREGULATOR_ON)
+  {
+    /* If in low-power run mode at this point, exit it */
+    if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
+    {
+      (void)HAL_PWREx_DisableLowPowerRunMode();
+    }
+    /* Regulator now in main mode. */
+  }
+  else
+  {
+    /* If in run mode, first move to low-power run mode.
+       The system clock frequency must be below 2 MHz at this point. */
+    if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == 0U)
+    {
+      HAL_PWREx_EnableLowPowerRunMode();
+    }
+  }
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+
+}
+
+
+/**
+  * @brief Enter Stop mode
+  * @note  This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
+  *        on devices where only "Stop mode" is mentioned with main or low power regulator ON.
+  * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note  All clocks in the VCORE domain are stopped; the PLL,
+  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
+  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
+  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
+  *        only to the peripheral requesting it.
+  *        SRAM1, SRAM2 and register contents are preserved.
+  *        The BOR is available.
+  *        The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
+  * @note  When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock.
+  * @note  When the voltage regulator operates in low power mode (Stop 1), an additional
+  *         startup delay is incurred when waking up.
+  *         By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
+  *         is higher although the startup time is reduced.
+  * @param Regulator: Specifies the regulator state in Stop mode.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
+  *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power regulator ON)
+  * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI instruction.
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE instruction.
+  * @retval None
+  */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+
+  if(Regulator == PWR_LOWPOWERREGULATOR_ON)
+  {
+    HAL_PWREx_EnterSTOP1Mode(STOPEntry);
+  }
+  else
+  {
+    HAL_PWREx_EnterSTOP0Mode(STOPEntry);
+  }
+}
+
+/**
+  * @brief Enter Standby mode.
+  * @note  In Standby mode, the PLL, the HSI and the HSE oscillators are switched
+  *        off. The voltage regulator is disabled, except when SRAM2 content is preserved
+  *        in which case the regulator is in low-power mode.
+  *        SRAM1 and register contents are lost except for registers in the Backup domain and
+  *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
+  *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
+  *        to set RRS bit.
+  *        The BOR is available.
+  * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
+  *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
+  *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
+  *        same.
+  *        These states are effective in Standby mode only if APC bit is set through
+  *        HAL_PWREx_EnablePullUpPullDownConfig() API.
+  * @retval None
+  */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+  /* Set Stand-by mode */
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+
+
+/**
+  * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
+  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+  *       re-enters SLEEP mode when an interruption handling is over.
+  *       Setting this bit is useful when the processor is expected to run only on
+  *       interruptions handling.
+  * @retval None
+  */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+  * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+  * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+  *       re-enters SLEEP mode when an interruption handling is over.
+  * @retval None
+  */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+
+/**
+  * @brief Enable CORTEX M4 SEVONPEND bit.
+  * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
+  *       WFE to wake up when an interrupt moves from inactive to pended.
+  * @retval None
+  */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+  /* Set SEVONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+/**
+  * @brief Disable CORTEX M4 SEVONPEND bit.
+  * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
+  *       WFE to wake up when an interrupt moves from inactive to pended.
+  * @retval None
+  */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+  /* Clear SEVONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+
+
+
+/**
+  * @brief PWR PVD interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWR_PVDCallback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_PWR_PVDCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c
new file mode 100644
index 0000000..05577aa
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c
@@ -0,0 +1,1182 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_pwr_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Extended Initialization and de-initialization functions
+  *           + Extended Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWREx PWREx
+  * @brief PWR Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+
+#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx)
+#define PWR_PORTF_AVAILABLE_PINS   0x0000FFFFU /* PF0..PF15 */
+#define PWR_PORTG_AVAILABLE_PINS   0x000007FFU /* PG0..PG10 */
+#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) || defined (STM32G491xx) || defined (STM32G4A1xx)
+#define PWR_PORTF_AVAILABLE_PINS   0x00000607U /* PF0..PF2 and PF9 and PF10 */
+#define PWR_PORTG_AVAILABLE_PINS   0x00000400U /* PG10 */
+#endif
+
+/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
+  * @{
+  */
+
+/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
+  * @{
+  */
+#define PVM_MODE_IT               0x00010000U    /*!< Mask for interruption yielded by PVM threshold crossing */
+#define PVM_MODE_EVT              0x00020000U    /*!< Mask for event yielded by PVM threshold crossing        */
+#define PVM_RISING_EDGE           0x00000001U    /*!< Mask for rising edge set as PVM trigger                 */
+#define PVM_FALLING_EDGE          0x00000002U    /*!< Mask for falling edge set as PVM trigger                */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
+  * @{
+  */
+#define PWR_FLAG_SETTING_DELAY_US                      50UL   /*!< Time out value for REGLPF and VOSF flags setting */
+/**
+  * @}
+  */
+
+
+
+/**
+  * @}
+  */
+
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
+  *  @brief   Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Extended Peripheral Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief Return Voltage Scaling Range.
+  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
+  *         or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
+  */
+uint32_t HAL_PWREx_GetVoltageRange(void)
+{
+  if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
+  {
+    return PWR_REGULATOR_VOLTAGE_SCALE2;
+  }
+  else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE)
+  {
+    /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */
+    return PWR_REGULATOR_VOLTAGE_SCALE1;
+  }
+  else
+  {
+    return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
+  }
+}
+
+
+
+/**
+  * @brief Configure the main internal regulator output voltage.
+  * @param  VoltageScaling: specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode,
+  *                                                typical output voltage at 1.28 V,
+  *                                                system frequency up to 170 MHz.
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
+  *                                                typical output voltage at 1.2 V,
+  *                                                system frequency up to 150 MHz.
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
+  *                                                typical output voltage at 1.0 V,
+  *                                                system frequency up to 26 MHz.
+  * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
+  *        a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
+  *        When moving from Range 2 to Range 1, the system frequency can be increased to
+  *        a value up to 150 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
+  *        When moving from Range 1 to Boost Mode Range 1, the system frequency can be increased to
+  *        a value up to 170 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
+  * @note  When moving from Range 2 to Range 1, the API waits for VOSF flag to be
+  *        cleared before returning the status. If the flag is not cleared within
+  *        50 microseconds, HAL_TIMEOUT status is reported.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+  uint32_t wait_loop_index;
+
+  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+
+  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
+  {
+    /* If current range is range 2 */
+    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
+    {
+      /* Make sure Range 1 Boost is enabled */
+      CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
+
+      /* Set Range 1 */
+      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
+
+      /* Wait until VOSF is cleared */
+      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
+      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
+      {
+        wait_loop_index--;
+      }
+      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* If current range is range 1 normal or boost mode */
+    else
+    {
+      /* Enable Range 1 Boost (no issue if bit already reset) */
+      CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
+    }
+  }
+  else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
+  {
+    /* If current range is range 2 */
+    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
+    {
+      /* Make sure Range 1 Boost is disabled */
+      SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
+
+      /* Set Range 1 */
+      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
+
+      /* Wait until VOSF is cleared */
+      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
+      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
+      {
+        wait_loop_index--;
+      }
+      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+     /* If current range is range 1 normal or boost mode */
+    else
+    {
+      /* Disable Range 1 Boost (no issue if bit already set) */
+      SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
+    }
+  }
+  else
+  {
+    /* Set Range 2 */
+    MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
+    /* No need to wait for VOSF to be cleared for this transition */
+    /* PWR_CR5_R1MODE bit setting has no effect in Range 2        */
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief Enable battery charging.
+  *        When VDD is present, charge the external battery on VBAT through an internal resistor.
+  * @param  ResistorSelection: specifies the resistor impedance.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5     5 kOhms resistor
+  *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
+  * @retval None
+  */
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
+{
+  assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
+
+  /* Specify resistor selection */
+  MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
+
+  /* Enable battery charging */
+  SET_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+
+/**
+  * @brief Disable battery charging.
+  * @retval None
+  */
+void HAL_PWREx_DisableBatteryCharging(void)
+{
+  CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+
+/**
+  * @brief Enable Internal Wake-up Line.
+  * @retval None
+  */
+void HAL_PWREx_EnableInternalWakeUpLine(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+
+/**
+  * @brief Disable Internal Wake-up Line.
+  * @retval None
+  */
+void HAL_PWREx_DisableInternalWakeUpLine(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+
+
+/**
+  * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
+  * @note  Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
+  *        pull-up state in Standby and Shutdown modes.
+  * @note  This state is effective in Standby and Shutdown modes only if APC bit
+  *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+  * @note  The configuration is lost when exiting the Shutdown mode due to the
+  *        power-on reset, maintained when exiting the Standby mode.
+  * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
+  *        PDy bit of PWR_PDCRx register is cleared unless it is reserved.
+  * @note  Even if a PUy bit to set is reserved, the other PUy bits entered as input
+  *        parameter at the same time are set.
+  * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G
+  *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
+  * @param  GPIONumber: Specify the I/O pins numbers.
+  *         This parameter can be one of the following values:
+  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
+  *         I/O pins are available) or the logical OR of several of them to set
+  *         several bits for a given port in a single API call.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  assert_param(IS_PWR_GPIO(GPIO));
+  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+  switch (GPIO)
+  {
+    case PWR_GPIO_A:
+       SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
+       CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
+       break;
+    case PWR_GPIO_B:
+       SET_BIT(PWR->PUCRB, GPIONumber);
+       CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
+       break;
+    case PWR_GPIO_C:
+       SET_BIT(PWR->PUCRC, GPIONumber);
+       CLEAR_BIT(PWR->PDCRC, GPIONumber);
+       break;
+    case PWR_GPIO_D:
+       SET_BIT(PWR->PUCRD, GPIONumber);
+       CLEAR_BIT(PWR->PDCRD, GPIONumber);
+       break;
+    case PWR_GPIO_E:
+       SET_BIT(PWR->PUCRE, GPIONumber);
+       CLEAR_BIT(PWR->PDCRE, GPIONumber);
+       break;
+    case PWR_GPIO_F:
+       SET_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+       CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+       break;
+    case PWR_GPIO_G:
+       SET_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
+       CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
+       break;
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
+  * @note  Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
+  *        in pull-up state in Standby and Shutdown modes.
+  * @note  Even if a PUy bit to reset is reserved, the other PUy bits entered as input
+  *        parameter at the same time are reset.
+  * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G
+  *          (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
+  * @param  GPIONumber: Specify the I/O pins numbers.
+  *         This parameter can be one of the following values:
+  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
+  *         I/O pins are available) or the logical OR of several of them to reset
+  *         several bits for a given port in a single API call.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  assert_param(IS_PWR_GPIO(GPIO));
+  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+  switch (GPIO)
+  {
+    case PWR_GPIO_A:
+       CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
+       break;
+    case PWR_GPIO_B:
+       CLEAR_BIT(PWR->PUCRB, GPIONumber);
+       break;
+    case PWR_GPIO_C:
+       CLEAR_BIT(PWR->PUCRC, GPIONumber);
+       break;
+    case PWR_GPIO_D:
+       CLEAR_BIT(PWR->PUCRD, GPIONumber);
+       break;
+    case PWR_GPIO_E:
+       CLEAR_BIT(PWR->PUCRE, GPIONumber);
+       break;
+    case PWR_GPIO_F:
+       CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+       break;
+    case PWR_GPIO_G:
+       CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
+       break;
+    default:
+       status = HAL_ERROR;
+       break;
+  }
+
+  return status;
+}
+
+
+
+/**
+  * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
+  * @note  Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
+  *        pull-down state in Standby and Shutdown modes.
+  * @note  This state is effective in Standby and Shutdown modes only if APC bit
+  *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+  * @note  The configuration is lost when exiting the Shutdown mode due to the
+  *        power-on reset, maintained when exiting the Standby mode.
+  * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
+  *        PUy bit of PWR_PUCRx register is cleared unless it is reserved.
+  * @note  Even if a PDy bit to set is reserved, the other PDy bits entered as input
+  *        parameter at the same time are set.
+  * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G
+  *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
+  * @param  GPIONumber: Specify the I/O pins numbers.
+  *         This parameter can be one of the following values:
+  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
+  *         I/O pins are available) or the logical OR of several of them to set
+  *         several bits for a given port in a single API call.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  assert_param(IS_PWR_GPIO(GPIO));
+  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+  switch (GPIO)
+  {
+    case PWR_GPIO_A:
+       SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
+       CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
+       break;
+    case PWR_GPIO_B:
+       SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
+       CLEAR_BIT(PWR->PUCRB, GPIONumber);
+       break;
+    case PWR_GPIO_C:
+       SET_BIT(PWR->PDCRC, GPIONumber);
+       CLEAR_BIT(PWR->PUCRC, GPIONumber);
+       break;
+    case PWR_GPIO_D:
+       SET_BIT(PWR->PDCRD, GPIONumber);
+       CLEAR_BIT(PWR->PUCRD, GPIONumber);
+       break;
+    case PWR_GPIO_E:
+       SET_BIT(PWR->PDCRE, GPIONumber);
+       CLEAR_BIT(PWR->PUCRE, GPIONumber);
+       break;
+    case PWR_GPIO_F:
+       SET_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+       CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+       break;
+    case PWR_GPIO_G:
+       SET_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
+       CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
+       break;
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
+  * @note  Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
+  *        in pull-down state in Standby and Shutdown modes.
+  * @note  Even if a PDy bit to reset is reserved, the other PDy bits entered as input
+  *        parameter at the same time are reset.
+  * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G
+  *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
+  * @param  GPIONumber: Specify the I/O pins numbers.
+  *         This parameter can be one of the following values:
+  *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
+  *         I/O pins are available) or the logical OR of several of them to reset
+  *         several bits for a given port in a single API call.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  assert_param(IS_PWR_GPIO(GPIO));
+  assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+  switch (GPIO)
+  {
+    case PWR_GPIO_A:
+       CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
+       break;
+    case PWR_GPIO_B:
+       CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
+       break;
+    case PWR_GPIO_C:
+       CLEAR_BIT(PWR->PDCRC, GPIONumber);
+       break;
+    case PWR_GPIO_D:
+       CLEAR_BIT(PWR->PDCRD, GPIONumber);
+       break;
+    case PWR_GPIO_E:
+       CLEAR_BIT(PWR->PDCRE, GPIONumber);
+       break;
+    case PWR_GPIO_F:
+       CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+       break;
+    case PWR_GPIO_G:
+       CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
+       break;
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+
+
+/**
+  * @brief Enable pull-up and pull-down configuration.
+  * @note  When APC bit is set, the I/O pull-up and pull-down configurations defined in
+  *        PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
+  * @note  Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
+  *        PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
+  *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
+  *        is no conflict when setting PUy or PDy bit.
+  * @retval None
+  */
+void HAL_PWREx_EnablePullUpPullDownConfig(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+
+/**
+  * @brief Disable pull-up and pull-down configuration.
+  * @note  When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
+  *        PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
+  * @retval None
+  */
+void HAL_PWREx_DisablePullUpPullDownConfig(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+
+
+/**
+  * @brief Enable SRAM2 content retention in Standby mode.
+  * @note  When RRS bit is set, SRAM2 is powered by the low-power regulator in
+  *         Standby mode and its content is kept.
+  * @retval None
+  */
+void HAL_PWREx_EnableSRAM2ContentRetention(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+
+
+/**
+  * @brief Disable SRAM2 content retention in Standby mode.
+  * @note  When RRS bit is reset, SRAM2 is powered off in Standby mode
+  *        and its content is lost.
+  * @retval None
+  */
+void HAL_PWREx_DisableSRAM2ContentRetention(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+
+
+
+
+#if defined(PWR_CR2_PVME1)
+/**
+  * @brief Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
+  * @retval None
+  */
+void HAL_PWREx_EnablePVM1(void)
+{
+  SET_BIT(PWR->CR2, PWR_PVM_1);
+}
+
+/**
+  * @brief Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
+  * @retval None
+  */
+void HAL_PWREx_DisablePVM1(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_PVM_1);
+}
+#endif /* PWR_CR2_PVME1 */
+
+
+#if defined(PWR_CR2_PVME2)
+/**
+  * @brief Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
+  * @retval None
+  */
+void HAL_PWREx_EnablePVM2(void)
+{
+  SET_BIT(PWR->CR2, PWR_PVM_2);
+}
+
+/**
+  * @brief Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
+  * @retval None
+  */
+void HAL_PWREx_DisablePVM2(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_PVM_2);
+}
+#endif /* PWR_CR2_PVME2 */
+
+
+/**
+  * @brief Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
+  * @retval None
+  */
+void HAL_PWREx_EnablePVM3(void)
+{
+  SET_BIT(PWR->CR2, PWR_PVM_3);
+}
+
+/**
+  * @brief Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
+  * @retval None
+  */
+void HAL_PWREx_DisablePVM3(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_PVM_3);
+}
+
+
+/**
+  * @brief Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
+  * @retval None
+  */
+void HAL_PWREx_EnablePVM4(void)
+{
+  SET_BIT(PWR->CR2, PWR_PVM_4);
+}
+
+/**
+  * @brief Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
+  * @retval None
+  */
+void HAL_PWREx_DisablePVM4(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_PVM_4);
+}
+
+
+
+
+/**
+  * @brief Configure the Peripheral Voltage Monitoring (PVM).
+  * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
+  *        PVM configuration information.
+  * @note The API configures a single PVM according to the information contained
+  *       in the input structure. To configure several PVMs, the API must be singly
+  *       called for each PVM used.
+  * @note Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage thresholds corresponding to each
+  *         detection level and to each monitored supply.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
+  assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
+
+
+  /* Configure EXTI 35 to 38 interrupts if so required:
+     scan through PVMType to detect which PVMx is set and
+     configure the corresponding EXTI line accordingly. */
+  switch (sConfigPVM->PVMType)
+  {
+#if defined(PWR_CR2_PVME1)
+    case PWR_PVM_1:
+      /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+      __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
+      __HAL_PWR_PVM1_EXTI_DISABLE_IT();
+      __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
+      __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
+
+      /* Configure interrupt mode */
+      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_PVM1_EXTI_ENABLE_IT();
+      }
+
+      /* Configure event mode */
+      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
+      }
+
+      /* Configure the edge */
+      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
+      }
+
+      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;
+#endif /* PWR_CR2_PVME1 */
+
+#if defined(PWR_CR2_PVME2)
+    case PWR_PVM_2:
+      /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+      __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
+      __HAL_PWR_PVM2_EXTI_DISABLE_IT();
+      __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
+      __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
+
+      /* Configure interrupt mode */
+      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_PVM2_EXTI_ENABLE_IT();
+      }
+
+      /* Configure event mode */
+      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
+      }
+
+      /* Configure the edge */
+      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
+      }
+
+      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;
+#endif /* PWR_CR2_PVME2 */
+
+    case PWR_PVM_3:
+      /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+      __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
+      __HAL_PWR_PVM3_EXTI_DISABLE_IT();
+      __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
+      __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
+
+      /* Configure interrupt mode */
+      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_PVM3_EXTI_ENABLE_IT();
+      }
+
+      /* Configure event mode */
+      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
+      }
+
+      /* Configure the edge */
+      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
+      }
+
+      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;
+
+    case PWR_PVM_4:
+      /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+      __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
+      __HAL_PWR_PVM4_EXTI_DISABLE_IT();
+      __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
+      __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
+
+      /* Configure interrupt mode */
+      if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_PVM4_EXTI_ENABLE_IT();
+      }
+
+      /* Configure event mode */
+      if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
+      }
+
+      /* Configure the edge */
+      if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
+      }
+
+      if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief Enter Low-power Run mode
+  * @note  In Low-power Run mode, all I/O pins keep the same state as in Run mode.
+  * @note  When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
+  *        Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
+  *        Additionally, the clock frequency must be reduced below 2 MHz.
+  *        Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
+  *        be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
+  * @retval None
+  */
+void HAL_PWREx_EnableLowPowerRunMode(void)
+{
+  /* Set Regulator parameter */
+  SET_BIT(PWR->CR1, PWR_CR1_LPR);
+}
+
+
+/**
+  * @brief Exit Low-power Run mode.
+  * @note  Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
+  *        REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
+  *        returns HAL_TIMEOUT status). The system clock frequency can then be
+  *        increased above 2 MHz.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
+{
+  uint32_t wait_loop_index;
+
+  /* Clear LPR bit */
+  CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
+
+  /* Wait until REGLPF is reset */
+  wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U));
+  while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
+  {
+    wait_loop_index--;
+  }
+  if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
+  {
+    return HAL_TIMEOUT;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief Enter Stop 0 mode.
+  * @note  In Stop 0 mode, main and low voltage regulators are ON.
+  * @note  In Stop 0 mode, all I/O pins keep the same state as in Run mode.
+  * @note  All clocks in the VCORE domain are stopped; the PLL, the HSI
+  *        and the HSE oscillators are disabled. Some peripherals with the wakeup capability
+  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
+  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
+  *        only to the peripheral requesting it.
+  *        SRAM1, SRAM2 and register contents are preserved.
+  *        The BOR is available.
+  * @note  When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
+  *         is set; the HSI oscillator is selected if STOPWUCK is cleared.
+  * @note  By keeping the internal regulator ON during Stop 0 mode, the consumption
+  *         is higher although the startup time is reduced.
+  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+  /* Stop 0 mode with Main Regulator */
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Select Stop mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+
+/**
+  * @brief Enter Stop 1 mode.
+  * @note  In Stop 1 mode, only low power voltage regulator is ON.
+  * @note  In Stop 1 mode, all I/O pins keep the same state as in Run mode.
+  * @note  All clocks in the VCORE domain are stopped; the PLL, the HSI
+  *        and the HSE oscillators are disabled. Some peripherals with the wakeup capability
+  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
+  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
+  *        only to the peripheral requesting it.
+  *        SRAM1, SRAM2 and register contents are preserved.
+  *        The BOR is available.
+  * @note  When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
+  *         is set.
+  * @note  Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
+  * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+  /* Stop 1 mode with Low-Power Regulator */
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Select Stop mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+
+
+
+/**
+  * @brief Enter Shutdown mode.
+  * @note  In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched
+  *        off. The voltage regulator is disabled and Vcore domain is powered off.
+  *        SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
+  *        The BOR is not available.
+  * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
+  * @retval None
+  */
+void HAL_PWREx_EnterSHUTDOWNMode(void)
+{
+
+  /* Set Shutdown mode */
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+
+
+
+/**
+  * @brief This function handles the PWR PVD/PVMx interrupt request.
+  * @note This API should be called under the PVD_PVM_IRQHandler().
+  * @retval None
+  */
+void HAL_PWREx_PVD_PVM_IRQHandler(void)
+{
+  /* Check PWR exti flag */
+  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0U)
+  {
+    /* PWR PVD interrupt user callback */
+    HAL_PWR_PVDCallback();
+
+    /* Clear PVD exti pending bit */
+    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+  }
+  /* Next, successively check PVMx exti flags */
+#if defined(PWR_CR2_PVME1)
+  if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U)
+  {
+    /* PWR PVM1 interrupt user callback */
+    HAL_PWREx_PVM1Callback();
+
+    /* Clear PVM1 exti pending bit */
+    __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
+  }
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
+  if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0U)
+  {
+    /* PWR PVM2 interrupt user callback */
+    HAL_PWREx_PVM2Callback();
+
+    /* Clear PVM2 exti pending bit */
+    __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
+  }
+#endif /* PWR_CR2_PVME2 */
+  if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U)
+  {
+    /* PWR PVM3 interrupt user callback */
+    HAL_PWREx_PVM3Callback();
+
+    /* Clear PVM3 exti pending bit */
+    __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
+  }
+  if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0U)
+  {
+    /* PWR PVM4 interrupt user callback */
+    HAL_PWREx_PVM4Callback();
+
+    /* Clear PVM4 exti pending bit */
+    __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
+  }
+}
+
+
+#if defined(PWR_CR2_PVME1)
+/**
+  * @brief PWR PVM1 interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWREx_PVM1Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_PVM1Callback() API can be implemented in the user file
+   */
+}
+#endif /* PWR_CR2_PVME1 */
+
+#if defined(PWR_CR2_PVME2)
+/**
+  * @brief PWR PVM2 interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWREx_PVM2Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_PVM2Callback() API can be implemented in the user file
+   */
+}
+#endif /* PWR_CR2_PVME2 */
+
+/**
+  * @brief PWR PVM3 interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWREx_PVM3Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_PVM3Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief PWR PVM4 interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWREx_PVM4Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_PVM4Callback() API can be implemented in the user file
+   */
+}
+
+#if defined(PWR_CR3_UCPD_STDBY)
+/**
+  * @brief Enable UCPD configuration memorization in Standby.
+  * @retval None
+  */
+void HAL_PWREx_EnableUCPDStandbyMode(void)
+{
+  /* Memorize UCPD configuration when entering standby mode */
+  SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
+}
+
+/**
+  * @brief Disable UCPD configuration memorization in Standby.
+  * @note  This function must be called on exiting the Standby mode and before any UCPD
+  *        configuration update.
+  * @retval None
+  */
+void HAL_PWREx_DisableUCPDStandbyMode(void)
+{
+  /* Write 0 immediately after Standby exit when using UCPD,
+     and before writing any UCPD registers */
+  CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
+}
+#endif /* PWR_CR3_UCPD_STDBY */
+
+#if defined(PWR_CR3_UCPD_DBDIS)
+/**
+  * @brief Enable the USB Type-C dead battery pull-down behavior
+  *        on UCPDx_CC1 and UCPDx_CC2 pins
+  * @retval None
+  */
+void HAL_PWREx_EnableUCPDDeadBattery(void)
+{
+  /* Write 0 to enable the USB Type-C dead battery pull-down behavior */
+  CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
+}
+
+/**
+  * @brief Disable the USB Type-C dead battery pull-down behavior
+  *        on UCPDx_CC1 and UCPDx_CC2 pins
+  * @note After exiting reset, the USB Type-C dead battery behavior will be enabled,
+  *       which may have a pull-down effect on CC1 and CC2 pins.
+  *       It is recommended to disable it in all cases, either to stop this pull-down
+  *       or to hand over control to the UCPD (which should therefore be
+  *       initialized before doing the disable).
+  * @retval None
+  */
+void HAL_PWREx_DisableUCPDDeadBattery(void)
+{
+  /* Write 1 to disable the USB Type-C dead battery pull-down behavior */
+  SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
+}
+#endif /* PWR_CR3_UCPD_DBDIS */
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c
new file mode 100644
index 0000000..8c6fe27
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c
@@ -0,0 +1,1401 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Reset and Clock Control (RCC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                      ##### RCC specific features #####
+  ==============================================================================
+    [..]
+      After reset the device is running from High Speed Internal oscillator
+      (16 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
+      and I-Cache are disabled, and all peripherals are off except internal
+      SRAM, Flash and JTAG.
+
+      (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses:
+          all peripherals mapped on these buses are running at HSI speed.
+      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+      (+) All GPIOs are in analog mode, except the JTAG pins which
+          are assigned to be used for debug purpose.
+
+    [..]
+      Once the device started from reset, the user application has to:
+      (+) Configure the clock source to be used to drive the System clock
+          (if the application needs higher frequency/performance)
+      (+) Configure the System clock frequency and Flash settings
+      (+) Configure the AHB and APB buses prescalers
+      (+) Enable the clock for the peripheral(s) to be used
+      (+) Configure the clock source(s) for peripherals which clocks are not
+          derived from the System clock (USB, RNG, USART, LPUART, FDCAN, some TIMERs,
+          UCPD, I2S, I2C, LPTIM, ADC, QSPI)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCC RCC
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE          2U                /* 2 ms (minimum Tick + 1) */
+#define LSI_TIMEOUT_VALUE          2U                /* 2 ms (minimum Tick + 1) */
+#define HSI48_TIMEOUT_VALUE        2U                /* 2 ms (minimum Tick + 1) */
+#define PLL_TIMEOUT_VALUE          2U                /* 2 ms (minimum Tick + 1) */
+#define CLOCKSWITCH_TIMEOUT_VALUE  5000U             /* 5 s    */
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__)   ((__RCC_MCOx__) & GPIO_PIN_MASK)
+
+#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__)    (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS)
+
+#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS)
+
+#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__)  (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__)))
+
+#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
+            (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_Private_Functions RCC Private Functions
+  * @{
+  */
+static uint32_t          RCC_GetSysClockFreqFromPLLSource(void);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+  @verbatim
+ ===============================================================================
+           ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to configure the internal and external oscillators
+      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
+       and APB2).
+
+    [..] Internal/external clock and PLL configuration
+         (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
+             the PLL as System clock source.
+
+         (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
+             clock source.
+
+         (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
+             through the PLL as System clock source. Can be used also optionally as RTC clock source.
+
+         (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
+
+         (+) PLL (clocked by HSI, HSE) providing up to three independent output clocks:
+           (++) The first output is used to generate the high speed system clock (up to 170 MHz).
+           (++) The second output is used to generate the clock for the USB (48 MHz),
+                the QSPI (<= 48 MHz), the FDCAN, the SAI and the I2S.
+           (++) The third output is used to generate a clock for ADC
+
+         (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
+            (HSE used directly or through PLL as System clock source), the System clock
+             is automatically switched to HSI and an interrupt is generated if enabled.
+             The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
+             exception vector.
+
+         (+) MCO (microcontroller clock output): used to output LSI, HSI, LSE, HSE,
+             main PLL clock, system clock or RC48 clock (through a configurable prescaler) on PA8 pin.
+
+    [..] System, AHB and APB buses clocks configuration
+         (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+             HSE and main PLL.
+             The AHB clock (HCLK) is derived from System clock through configurable
+             prescaler and used to clock the CPU, memory and peripherals mapped
+             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+             from AHB clock through configurable prescalers and used to clock
+             the peripherals mapped on these buses. You can use
+             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+
+           (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
+                divided by 2 to 31.
+                You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
+                to configure this clock.
+           (+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz
+                to work correctly, while the RNG peripheral requires a frequency
+                equal or lower than to 48 MHz. This clock is derived of the main PLL
+                through PLLQ divider. You have to enable the peripheral clock and use
+                HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
+           (+@) IWDG clock which is always the LSI clock.
+
+
+         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 170 MHz.
+             The clock source frequency should be adapted depending on the device voltage range
+             as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
+
+  @endverbatim
+
+           Table 1. HCLK clock frequency for STM32G4xx devices
+           +----------------------------------------------------------------------------+
+           | Latency         |            HCLK clock frequency (MHz)                    |
+           |                 |----------------------------------------------------------|
+           |                 |  voltage range 1  |  voltage range 1  | voltage range 2  |
+           |                 | boost mode 1.28 V | normal mode 1.2 V |     1.0 V        |
+           |-----------------|-------------------|-------------------|------------------|
+           |0WS(1 CPU cycles)|    HCLK <= 34     |    HCLK <= 30     |    HCLK <= 13    |
+           |-----------------|-------------------|-------------------|------------------|
+           |1WS(2 CPU cycles)|    HCLK <= 68     |    HCLK <= 60     |    HCLK <= 26    |
+           |-----------------|-------------------|-------------------|------------------|
+           |2WS(3 CPU cycles)|    HCLK <= 102    |    HCLK <= 90     |        -         |
+           |-----------------|-------------------|-------------------|------------------|
+           |3WS(4 CPU cycles)|    HCLK <= 136    |    HCLK <= 120    |        -         |
+           |-----------------|-------------------|-------------------|------------------|
+           |4WS(5 CPU cycles)|    HCLK <= 170    |    HCLK <= 150    |        -         |
+           +----------------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief  Reset the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL OFF
+  *            - AHB, APB1 and APB2 prescaler set to 1.
+  *            - CSS, MCO1 OFF
+  *            - All interrupts disabled
+  *            - All interrupt and reset flags cleared
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+  uint32_t tickstart;
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Set HSION bit to the reset value */
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+
+  /* Wait till HSI is ready */
+  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+ /* Set HSITRIM[6:0] bits to the reset value */
+  SET_BIT(RCC->ICSCR, RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos);
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Reset CFGR register (HSI is selected as system clock source) */
+  RCC->CFGR = 0x00000001u;
+
+  /* Wait till HSI is ready */
+  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+  {
+    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HSI_VALUE;
+
+  /* Adapt Systick interrupt period */
+  if (HAL_InitTick(uwTickPrio) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */
+  RCC->CR = RCC_CR_HSION;
+
+  /* Then again to HSEBYP in case bypass was enabled */
+  RCC->CR = RCC_CR_HSION;
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait till PLL is OFF */
+  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* once PLL is OFF, reset PLLCFGR register to default value */
+  RCC->PLLCFGR = RCC_PLLCFGR_PLLN_4;
+
+  /* Disable all interrupts */
+  CLEAR_REG(RCC->CIER);
+
+  /* Clear all interrupt flags */
+  WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
+
+  /* Clear all reset flags */
+  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this macro. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this macro. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  uint32_t tickstart;
+  uint32_t temp_sysclksrc;
+  uint32_t temp_pllckcfg;
+
+  /* Check Null pointer */
+  if (RCC_OscInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+  /*------------------------------- HSE Configuration ------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
+
+    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+    if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE))
+    {
+      if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+      /* Check the HSE State */
+      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is ready */
+        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is disabled */
+        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
+    if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI))
+    {
+      /* When HSI is used as system clock it will not be disabled */
+      if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+
+        /* Adapt Systick interrupt period */
+        if (HAL_InitTick(uwTickPrio) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+      }
+    }
+    else
+    {
+      /* Check the HSI State */
+      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is disabled */
+        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
+      {
+        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is disabled */
+      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    FlagStatus       pwrclkchanged = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Update LSE configuration in Backup Domain control register    */
+    /* Requires to enable write access to Backup Domain if necessary */
+    if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
+    {
+      __HAL_RCC_PWR_CLK_ENABLE();
+      pwrclkchanged = SET;
+    }
+
+    if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+    {
+      /* Enable write access to Backup domain */
+      SET_BIT(PWR->CR1, PWR_CR1_DBP);
+
+      /* Wait for Backup domain Write protection disable */
+      tickstart = HAL_GetTick();
+
+      while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+
+    /* Check the LSE State */
+    if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is disabled */
+      while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Restore clock configuration if changed */
+    if (pwrclkchanged == SET)
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+    }
+  }
+
+  /*------------------------------ HSI48 Configuration -----------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
+
+    /* Check the HSI48 State */
+    if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till HSI48 is ready */
+      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_DISABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till HSI48 is disabled */
+      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+
+  if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
+  {
+    /* Check if the PLL is used as system clock or not */
+    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+    {
+      if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+                             RCC_OscInitStruct->PLL.PLLM,
+                             RCC_OscInitStruct->PLL.PLLN,
+                             RCC_OscInitStruct->PLL.PLLP,
+                             RCC_OscInitStruct->PLL.PLLQ,
+                             RCC_OscInitStruct->PLL.PLLR);
+
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+
+        /* Enable PLL System Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Disable all PLL outputs to save power if no PLLs on */
+          MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
+        __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is disabled */
+        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Check if there is a request to disable the PLL used as System clock source */
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+      /* Do not return HAL_ERROR if request repeats the current configuration */
+      temp_pllckcfg = RCC->PLLCFGR;
+      if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
+         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
+         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
+         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
+         (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the CPU, AHB and APB buses clocks according to the specified
+  *         parameters in the RCC_ClkInitStruct.
+  * @param  RCC_ClkInitStruct  pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC peripheral.
+  * @param  FLatency  FLASH Latency
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_LATENCY_0   FLASH 0 Latency cycle
+  *            @arg FLASH_LATENCY_1   FLASH 1 Latency cycle
+  *            @arg FLASH_LATENCY_2   FLASH 2 Latency cycles
+  *            @arg FLASH_LATENCY_3   FLASH 3 Latency cycles
+  *            @arg FLASH_LATENCY_4   FLASH 4 Latency cycles
+  *            @arg FLASH_LATENCY_5   FLASH 5 Latency cycles
+  *            @arg FLASH_LATENCY_6   FLASH 6 Latency cycles
+  *            @arg FLASH_LATENCY_7   FLASH 7 Latency cycles
+  *            @arg FLASH_LATENCY_8   FLASH 8 Latency cycles
+  *            @arg FLASH_LATENCY_9   FLASH 9 Latency cycles
+  *            @arg FLASH_LATENCY_10  FLASH 10 Latency cycles
+  *            @arg FLASH_LATENCY_11  FLASH 11 Latency cycles
+  *            @arg FLASH_LATENCY_12  FLASH 12 Latency cycles
+  *            @arg FLASH_LATENCY_13  FLASH 13 Latency cycles
+  *            @arg FLASH_LATENCY_14  FLASH 14 Latency cycles
+  *            @arg FLASH_LATENCY_15  FLASH 15 Latency cycles
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
+  *
+  * @note   The HSI is used by default as system clock source after
+  *         startup from Reset, wake-up from STANDBY mode. After restart from Reset,
+  *         the HSI frequency is set to its default value 16 MHz.
+  *
+  * @note   The HSI can be selected as system clock source after
+  *         from STOP modes or in case of failure of the HSE used directly or indirectly
+  *         as system clock (if the Clock Security System CSS is enabled).
+  *
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after startup delay or PLL locked).
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source is ready.
+  *
+  * @note   You can use HAL_RCC_GetClockConfig() function to know which clock is
+  *         currently used as system clock source.
+  *
+  * @note   Depending on the device voltage range, the software has to set correctly
+  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+  uint32_t tickstart;
+  uint32_t pllfreq;
+  uint32_t hpre = RCC_SYSCLK_DIV1;
+
+  /* Check Null pointer */
+  if (RCC_ClkInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+  assert_param(IS_FLASH_LATENCY(FLatency));
+
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+    must be correctly programmed according to the frequency of the CPU clock
+    (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if (FLatency > __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if (__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /*------------------------- SYSCLK Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+  {
+    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+    /* PLL is selected as System Clock Source */
+    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+    {
+      /* Check the PLL ready flag */
+      if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
+      {
+        return HAL_ERROR;
+      }
+      /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */
+      /* Compute target PLL output frequency */
+      pllfreq = RCC_GetSysClockFreqFromPLLSource();
+
+      /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
+      if(pllfreq > 80000000U)
+      {
+        if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
+            (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
+              (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
+        {
+          MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
+          hpre = RCC_SYSCLK_DIV2;
+        }
+      }
+    }
+    else
+    {
+      /* HSE is selected as System Clock Source */
+      if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+      {
+        /* Check the HSE ready flag */
+        if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* HSI is selected as System Clock Source */
+      else
+      {
+        /* Check the HSI ready flag */
+        if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */
+      pllfreq = HAL_RCC_GetSysClockFreq();
+
+      /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
+      if(pllfreq > 80000000U)
+      {
+        MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
+        hpre = RCC_SYSCLK_DIV2;
+      }
+
+    }
+
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+    {
+      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+    /* Set the highest APB divider in order to ensure that we do not go through
+       a non-spec phase whatever we decrease or increase HCLK. */
+    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+    {
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+    }
+    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+    {
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
+    }
+
+    /* Set the new HCLK clock divider */
+    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+  }
+  else
+  {
+    /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
+    if(hpre == RCC_SYSCLK_DIV2)
+    {
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
+    }
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if (FLatency < __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by polling the FLASH_ACR register */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+  }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
+  }
+
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
+
+  /* Configure the source of time base considering new system clocks settings*/
+  return HAL_InitTick(uwTickPrio);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to:
+
+    (+) Output clock to MCO pin.
+    (+) Retrieve current clock frequencies.
+    (+) Enable the Clock Security System.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Select the clock source to output on MCO pin(PA8/PG10).
+  * @note   PA8/PG10 should be configured in alternate function mode.
+  * @note   The default configuration of the GPIOG pin 10 (PG10) is set to reset mode (NRST pin)
+  *         and user shall set the NRST_MODE Bit in the FLASH OPTR register to be able to use it 
+  *         as an MCO pin.
+  *         The @ref HAL_FLASHEx_OBProgram() API can be used to configure the NRST_MODE Bit value.
+  * @param  RCC_MCOx  specifies the output direction for the clock source.
+  *          For STM32G4xx family this parameter can have only one value:
+  *            @arg @ref RCC_MCO_PA8  Clock source to output on MCO1 pin(PA8).
+  *            @arg @ref RCC_MCO_PG10  Clock source to output on MCO1 pin(PG10).
+  * @param  RCC_MCOSource  specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled, no clock on MCO
+  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  system  clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee
+  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  main PLL clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
+  *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48
+  * @param  RCC_MCODiv  specifies the MCO prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_MCODIV_1  no division applied to MCO clock
+  *            @arg @ref RCC_MCODIV_2  division by 2 applied to MCO clock
+  *            @arg @ref RCC_MCODIV_4  division by 4 applied to MCO clock
+  *            @arg @ref RCC_MCODIV_8  division by 8 applied to MCO clock
+  *            @arg @ref RCC_MCODIV_16  division by 16 applied to MCO clock
+  * @retval None
+  */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+  GPIO_InitTypeDef gpio_initstruct;
+  uint32_t mcoindex;
+  uint32_t mco_gpio_index;
+  GPIO_TypeDef * mco_gpio_port;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO(RCC_MCOx));
+
+  /* Common GPIO init parameters */
+  gpio_initstruct.Mode      = GPIO_MODE_AF_PP;
+  gpio_initstruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_initstruct.Pull      = GPIO_NOPULL;
+
+  /* Get MCOx selection */
+  mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK;
+
+  /* Get MCOx GPIO Port */
+  mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx);
+
+  /* MCOx Clock Enable */
+  mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx);
+  SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index ));
+
+  /* Configure the MCOx pin in alternate function mode */
+  gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx);
+  gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx);
+  HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct);
+
+   if (mcoindex == RCC_MCO1_INDEX)
+  {
+    assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+    /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv));
+  }
+}
+
+/**
+  * @brief  Return the SYSCLK frequency.
+  *
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
+  *           HSI_VALUE(*) Value multiplied/divided by the PLL factors.
+  * @note     (*) HSI_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value
+  *               16 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSE_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value
+  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baudrate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time SYSCLK changes, this function must be called to update the
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t pllvco, pllsource, pllr, pllm;
+  uint32_t sysclockfreq;
+
+  if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
+  {
+    /* HSI used as system clock source */
+    sysclockfreq = HSI_VALUE;
+  }
+  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
+  {
+    /* HSE used as system clock source */
+    sysclockfreq = HSE_VALUE;
+  }
+  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
+  {
+    /* PLL used as system clock  source */
+
+    /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+    pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
+
+    switch (pllsource)
+    {
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      break;
+
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+    default:
+      pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+      break;
+    }
+    pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
+    sysclockfreq = pllvco/pllr;
+  }
+  else
+  {
+    sysclockfreq = 0U;
+  }
+
+  return sysclockfreq;
+}
+
+/**
+  * @brief  Return the HCLK frequency.
+  * @note   Each time HCLK changes, this function must be called to update the
+  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
+  * @retval HCLK frequency in Hz
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+  return SystemCoreClock;
+}
+
+/**
+  * @brief  Return the PCLK1 frequency.
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency in Hz
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
+}
+
+/**
+  * @brief  Return the PCLK2 frequency.
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK2 frequency in Hz
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
+}
+
+/**
+  * @brief  Configure the RCC_OscInitStruct according to the internal
+  *         RCC configuration registers.
+  * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
+  *         will be configured.
+  * @retval None
+  */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  /* Check the parameters */
+  assert_param(RCC_OscInitStruct != (void *)NULL);
+
+  /* Set all possible values for the Oscillator type parameter ---------------*/
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \
+                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
+
+  /* Get the HSE configuration -----------------------------------------------*/
+  if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+
+  /* Get the HSI configuration -----------------------------------------------*/
+  if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION)
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+
+  RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos;
+
+  /* Get the LSE configuration -----------------------------------------------*/
+  if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+
+  /* Get the LSI configuration -----------------------------------------------*/
+  if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION)
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+
+  /* Get the HSI48 configuration ---------------------------------------------*/
+  if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
+  {
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
+  }
+
+  /* Get the PLL configuration -----------------------------------------------*/
+  if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON)
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+  }
+  RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+  RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
+  RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+  RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
+  RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U);
+  RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
+}
+
+/**
+  * @brief  Configure the RCC_ClkInitStruct according to the internal
+  *         RCC configuration registers.
+  * @param  RCC_ClkInitStruct  pointer to an RCC_ClkInitTypeDef structure that
+  *         will be configured.
+  * @param  pFLatency  Pointer on the Flash Latency.
+  * @retval None
+  */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+  /* Check the parameters */
+  assert_param(RCC_ClkInitStruct != (void  *)NULL);
+  assert_param(pFLatency != (void *)NULL);
+
+  /* Set all possible values for the Clock type parameter --------------------*/
+  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+  /* Get the SYSCLK configuration --------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);
+
+  /* Get the HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);
+
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/
+  *pFLatency = __HAL_FLASH_GET_LATENCY();
+}
+
+/**
+  * @brief  Enable the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+  * @note   The Clock Security System can only be cleared by reset.
+  * @retval None
+  */
+void HAL_RCC_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSON) ;
+}
+
+/**
+  * @brief  Enable the LSE Clock Security System.
+  * @note   If a failure is detected on the external 32 kHz oscillator,
+  *         the LSE clock is no longer supplied to the RTC but no hardware action
+  *         is made to the registers. If enabled, an interrupt will be generated
+  *         and handle through @ref RCCEx_EXTI_LINE_LSECSS
+  * @note   The Clock Security System can only be cleared by reset or after a LSE failure detection.
+  * @retval None
+  */
+void HAL_RCC_EnableLSECSS(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+}
+
+/**
+  * @brief  Disable the LSE Clock Security System.
+  * @note   After LSE failure detection, the software must disable LSECSSON
+  * @note   The Clock Security System can only be cleared by reset otherwise.
+  * @retval None
+  */
+void HAL_RCC_DisableLSECSS(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+}
+
+/**
+  * @brief Handle the RCC Clock Security System interrupt request.
+  * @note This API should be called under the NMI_Handler().
+  * @retval None
+  */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+  /* Check RCC CSSF interrupt flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+  {
+    /* RCC Clock Security System interrupt user callback */
+    HAL_RCC_CSSCallback();
+
+    /* Clear RCC CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+  }
+}
+
+/**
+  * @brief  RCC Clock Security System interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCC_CSSCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RCC_CSSCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup RCC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Compute SYSCLK frequency based on PLL SYSCLK source.
+  * @retval SYSCLK frequency
+  */
+static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
+{
+  uint32_t pllvco, pllsource, pllr, pllm;
+  uint32_t sysclockfreq;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
+     SYSCLK = PLL_VCO / PLLR
+   */
+  pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+  pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
+
+  switch (pllsource)
+  {
+  case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+    pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+    break;
+
+  case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+  default:
+    pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+    break;
+  }
+
+  pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
+  sysclockfreq = pllvco/pllr;
+
+  return sysclockfreq;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c
new file mode 100644
index 0000000..acd2664
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c
@@ -0,0 +1,1825 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_rcc_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities RCC extended peripheral:
+  *           + Extended Peripheral Control functions
+  *           + Extended Clock management functions
+  *           + Extended Clock Recovery System Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCCEx RCCEx
+  * @brief RCC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+ * @{
+ */
+#define PLL_TIMEOUT_VALUE        2U                /* 2 ms (minimum Tick + 1) */
+
+#define DIVIDER_P_UPDATE          0U
+#define DIVIDER_Q_UPDATE          1U
+#define DIVIDER_R_UPDATE          2U
+
+#define __LSCO_CLK_ENABLE()       __HAL_RCC_GPIOA_CLK_ENABLE()
+#define LSCO_GPIO_PORT            GPIOA
+#define LSCO_PIN                  GPIO_PIN_2
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
+ * @{
+ */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+  * @{
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ *  @brief  Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Peripheral Control functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+    [..]
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+        select the RTC clock source; in this case the Backup domain will be reset in
+        order to modify the RTC Clock source, as consequence RTC registers (including
+        the backup registers) are set to their reset values.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initialize the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains a field PeriphClockSelection which can be a combination of the following values:
+  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)
+  *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)
+  *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)
+  *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S  I2S peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_FDCAN  FDCAN peripheral clock (only for devices with FDCAN)
+  *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)
+  *            @arg @ref RCC_PERIPHCLK_ADC12  ADC1 and ADC2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_ADC345  ADC3, ADC4 and ADC5 peripheral clock (only for devices with ADC3, ADC4, ADC5)
+  *            @arg @ref RCC_PERIPHCLK_QSPI  QuadSPI peripheral clock (only for devices with QuadSPI)
+  *
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source: in this case the access to Backup domain is enabled.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tmpregister;
+  uint32_t tickstart;
+  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
+  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*-------------------------- RTC clock source configuration ----------------------*/
+  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+  {
+    FlagStatus       pwrclkchanged = RESET;
+    
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock */
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+    {
+      __HAL_RCC_PWR_CLK_ENABLE();
+      pwrclkchanged = SET;
+    }
+      
+    /* Enable write access to Backup domain */
+    SET_BIT(PWR->CR1, PWR_CR1_DBP);
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
+    {
+      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        ret = HAL_TIMEOUT;
+        break;
+      }
+    }
+
+    if(ret == HAL_OK)
+    { 
+      /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
+      tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
+      
+      if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
+      {
+        /* Store the content of BDCR register before the reset of Backup Domain */
+        tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
+        /* RTC Clock selection can be changed only if the Backup Domain is reset */
+        __HAL_RCC_BACKUPRESET_FORCE();
+        __HAL_RCC_BACKUPRESET_RELEASE();
+        /* Restore the Content of BDCR register */
+        RCC->BDCR = tmpregister;
+      }
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            ret = HAL_TIMEOUT;
+            break;
+          }
+        }
+      }
+      
+      if(ret == HAL_OK)
+      {
+        /* Apply new RTC clock source selection */
+        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+      }
+      else
+      {
+        /* set overall return value */
+        status = ret;
+      }
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+
+    /* Restore clock configuration if changed */
+    if(pwrclkchanged == SET)
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+    }
+  }
+
+  /*-------------------------- USART1 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+
+    /* Configure the USART1 clock source */
+    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+  }
+
+  /*-------------------------- USART2 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+
+    /* Configure the USART2 clock source */
+    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+  }
+
+  /*-------------------------- USART3 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+
+    /* Configure the USART3 clock source */
+    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+  }
+
+#if defined(UART4)
+  /*-------------------------- UART4 clock source configuration --------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
+
+    /* Configure the UART4 clock source */
+    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
+  }
+#endif /* UART4 */
+
+#if defined(UART5)
+
+  /*-------------------------- UART5 clock source configuration --------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
+
+    /* Configure the UART5 clock source */
+    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
+  }
+
+#endif /* UART5 */
+
+  /*-------------------------- LPUART1 clock source configuration ------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
+
+    /* Configure the LPUAR1 clock source */
+    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+  }
+
+  /*-------------------------- I2C1 clock source configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+
+    /* Configure the I2C1 clock source */
+    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+  }
+
+  /*-------------------------- I2C2 clock source configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
+
+    /* Configure the I2C2 clock source */
+    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
+  }
+
+  /*-------------------------- I2C3 clock source configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
+
+    /* Configure the I2C3 clock source */
+    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
+  }
+
+#if defined(I2C4)  
+
+  /*-------------------------- I2C4 clock source configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+    /* Configure the I2C4 clock source */
+    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+  }
+
+#endif /* I2C4 */
+
+  /*-------------------------- LPTIM1 clock source configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
+
+    /* Configure the LPTIM1 clock source */
+    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+  }
+
+  /*-------------------------- SAI1 clock source configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+
+    /* Configure the SAI1 interface clock source */
+    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+    
+    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
+    {
+      /* Enable PLL48M1CLK output */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+    }
+  }
+
+  /*-------------------------- I2S clock source configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
+
+    /* Configure the I2S interface clock source */
+    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
+    
+    if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
+    {
+      /* Enable PLL48M1CLK output */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+    }
+  }
+
+#if defined(FDCAN1)
+  /*-------------------------- FDCAN clock source configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
+
+    /* Configure the FDCAN interface clock source */
+    __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
+    
+    if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
+    {
+      /* Enable PLL48M1CLK output */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+    }
+  }
+#endif /* FDCAN1 */
+
+#if defined(USB)
+
+  /*-------------------------- USB clock source configuration ----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
+  {
+    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
+    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+
+    if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
+    {
+      /* Enable PLL48M1CLK output */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+    }
+  }
+
+#endif /* USB */
+
+  /*-------------------------- RNG clock source configuration ----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
+  {
+    assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
+    __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
+
+    if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
+    {
+      /* Enable PLL48M1CLK output */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+    }
+  }
+
+  /*-------------------------- ADC12 clock source configuration ----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
+
+    /* Configure the ADC12 interface clock source */
+    __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
+    
+    if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
+    {
+      /* Enable PLLADCCLK output */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
+    }
+  }
+  
+#if defined(ADC345_COMMON)
+  /*-------------------------- ADC345 clock source configuration ----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_ADC345CLKSOURCE(PeriphClkInit->Adc345ClockSelection));
+
+    /* Configure the ADC345 interface clock source */
+    __HAL_RCC_ADC345_CONFIG(PeriphClkInit->Adc345ClockSelection);
+    
+    if(PeriphClkInit->Adc345ClockSelection == RCC_ADC345CLKSOURCE_PLL)
+    {
+      /* Enable PLLADCCLK output */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
+    }
+  }
+#endif /* ADC345_COMMON */
+
+#if defined(QUADSPI)
+
+  /*-------------------------- QuadSPIx clock source configuration ----------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection));
+
+    /* Configure the QuadSPI clock source */
+    __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
+
+    if(PeriphClkInit->QspiClockSelection == RCC_QSPICLKSOURCE_PLL)
+    {
+      /* Enable PLL48M1CLK output */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+    }
+  }
+
+#endif /* QUADSPI */
+
+  return status;
+}
+
+/**
+  * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
+  * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         returns the configuration information for the Extended Peripherals
+  *         clocks(USART1, USART2, USART3, UART4, UART5, LPUART1, I2C1, I2C2, I2C3, I2C4,
+  *         LPTIM1, SAI1, I2Sx, FDCANx, USB, RNG, ADCx, RTC, QSPI).
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  /* Set all possible values for the extended clock type parameter------------*/
+
+#if defined(STM32G474xx) || defined(STM32G484xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | \
+                                        RCC_PERIPHCLK_UART5   | \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | \
+                                        RCC_PERIPHCLK_I2C4    | \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_I2S    | RCC_PERIPHCLK_FDCAN  | \
+                                        RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_ADC12  | RCC_PERIPHCLK_ADC345 | \
+                                        RCC_PERIPHCLK_QSPI    | \
+                                        RCC_PERIPHCLK_RTC;
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | \
+                                        RCC_PERIPHCLK_UART5   | \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_I2S    | RCC_PERIPHCLK_FDCAN  | \
+                                        RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_ADC12  | RCC_PERIPHCLK_ADC345 | \
+                                        RCC_PERIPHCLK_QSPI    | \
+                                        RCC_PERIPHCLK_RTC;
+
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | \
+                                        RCC_PERIPHCLK_UART5   | \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | \
+                                        RCC_PERIPHCLK_I2C4    | \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_I2S    | \
+                                        RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_ADC12  | RCC_PERIPHCLK_ADC345 | \
+                                        RCC_PERIPHCLK_QSPI    | \
+                                        RCC_PERIPHCLK_RTC;
+
+#elif defined(STM32G471xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | \
+                                        RCC_PERIPHCLK_UART5   | \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | \
+                                        RCC_PERIPHCLK_I2C4    | \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_I2S    | \
+                                        RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_ADC12  | \
+                                        RCC_PERIPHCLK_RTC;
+#elif defined(STM32G431xx) || defined(STM32G441xx)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_I2S    | RCC_PERIPHCLK_FDCAN    | \
+                                        RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_ADC12  | \
+                                        RCC_PERIPHCLK_RTC;
+#elif defined(STM32GBK1CB)
+
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+                                        RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | \
+                                        RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_I2S    | RCC_PERIPHCLK_FDCAN    | \
+                                        RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_ADC12  | \
+                                        RCC_PERIPHCLK_RTC;
+
+#endif /* STM32G431xx */
+
+
+  /* Get the USART1 clock source ---------------------------------------------*/
+  PeriphClkInit->Usart1ClockSelection  = __HAL_RCC_GET_USART1_SOURCE();
+  /* Get the USART2 clock source ---------------------------------------------*/
+  PeriphClkInit->Usart2ClockSelection  = __HAL_RCC_GET_USART2_SOURCE();
+  /* Get the USART3 clock source ---------------------------------------------*/
+  PeriphClkInit->Usart3ClockSelection  = __HAL_RCC_GET_USART3_SOURCE();
+
+#if defined(UART4)
+  /* Get the UART4 clock source ----------------------------------------------*/
+  PeriphClkInit->Uart4ClockSelection   = __HAL_RCC_GET_UART4_SOURCE();
+#endif /* UART4 */
+
+#if defined(UART5)
+  /* Get the UART5 clock source ----------------------------------------------*/
+  PeriphClkInit->Uart5ClockSelection   = __HAL_RCC_GET_UART5_SOURCE();
+#endif /* UART5 */
+  
+  /* Get the LPUART1 clock source --------------------------------------------*/
+  PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
+
+  /* Get the I2C1 clock source -----------------------------------------------*/
+  PeriphClkInit->I2c1ClockSelection    = __HAL_RCC_GET_I2C1_SOURCE();
+
+  /* Get the I2C2 clock source ----------------------------------------------*/
+  PeriphClkInit->I2c2ClockSelection    = __HAL_RCC_GET_I2C2_SOURCE();
+
+  /* Get the I2C3 clock source -----------------------------------------------*/
+  PeriphClkInit->I2c3ClockSelection    = __HAL_RCC_GET_I2C3_SOURCE();
+
+#if defined(I2C4)
+  /* Get the I2C4 clock source -----------------------------------------------*/
+  PeriphClkInit->I2c4ClockSelection    = __HAL_RCC_GET_I2C4_SOURCE();
+#endif /* I2C4 */
+
+  /* Get the LPTIM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim1ClockSelection  = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+  /* Get the SAI1 clock source -----------------------------------------------*/
+  PeriphClkInit->Sai1ClockSelection    = __HAL_RCC_GET_SAI1_SOURCE();
+
+  /* Get the I2S clock source -----------------------------------------------*/
+  PeriphClkInit->I2sClockSelection    = __HAL_RCC_GET_I2S_SOURCE();
+
+#if defined(FDCAN1)
+  /* Get the FDCAN clock source -----------------------------------------------*/
+  PeriphClkInit->FdcanClockSelection    = __HAL_RCC_GET_FDCAN_SOURCE();
+#endif /* FDCAN1 */
+
+#if defined(USB)
+  /* Get the USB clock source ------------------------------------------------*/
+  PeriphClkInit->UsbClockSelection   = __HAL_RCC_GET_USB_SOURCE();
+#endif /* USB */
+
+  /* Get the RNG clock source ------------------------------------------------*/
+  PeriphClkInit->RngClockSelection   = __HAL_RCC_GET_RNG_SOURCE();
+
+  /* Get the ADC12 clock source -----------------------------------------------*/
+  PeriphClkInit->Adc12ClockSelection     = __HAL_RCC_GET_ADC12_SOURCE();
+
+#if defined(ADC345_COMMON)
+  /* Get the ADC345 clock source ----------------------------------------------*/
+  PeriphClkInit->Adc345ClockSelection     = __HAL_RCC_GET_ADC345_SOURCE();
+#endif /* ADC345_COMMON */
+
+#if defined(QUADSPI)
+  /* Get the QuadSPIclock source --------------------------------------------*/
+  PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
+#endif /* QUADSPI */
+
+  /* Get the RTC clock source ------------------------------------------------*/
+  PeriphClkInit->RTCClockSelection     = __HAL_RCC_GET_RTC_SOURCE();
+
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for peripherals with clock source from PLL
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk  Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)
+  *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)
+  *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)
+  *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S  SPI peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_FDCAN  FDCAN peripheral clock (only for devices with FDCAN)
+  *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)
+  *            @arg @ref RCC_PERIPHCLK_ADC12  ADC1 and ADC2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_ADC345  ADC3, ADC4 and ADC5 peripheral clock (only for devices with ADC3, ADC4, ADC5)
+  *            @arg @ref RCC_PERIPHCLK_QSPI  QSPI peripheral clock (only for devices with QSPI)
+  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
+  * @retval Frequency in Hz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  uint32_t frequency = 0U;
+  uint32_t srcclk;
+  uint32_t pllvco, plln, pllp;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+  if(PeriphClk == RCC_PERIPHCLK_RTC)
+  {
+    /* Get the current RTC source */
+    srcclk = __HAL_RCC_GET_RTC_SOURCE();
+
+    /* Check if LSE is ready and if RTC clock selection is LSE */
+    if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
+    {
+      frequency = LSE_VALUE;
+    }
+    /* Check if LSI is ready and if RTC clock selection is LSI */
+    else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
+    {
+      frequency = LSI_VALUE;
+    }
+    /* Check if HSE is ready  and if RTC clock selection is HSI_DIV32*/
+    else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32))
+    {
+      frequency = HSE_VALUE / 32U;
+    }
+    /* Clock not enabled for RTC*/
+    else
+    {
+      /* nothing to do: frequency already initialized to 0 */
+    }
+  }
+  else
+  {
+    /* Other external peripheral clock source than RTC */
+
+    /* Compute PLL clock input */
+    if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)   /* HSI ? */
+    {
+      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+      {
+        pllvco = HSI_VALUE;
+      }
+      else
+      {
+        pllvco = 0U;
+      }
+    }
+    else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)   /* HSE ? */
+    {
+      if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+      {
+        pllvco = HSE_VALUE;
+      }
+      else
+      {
+        pllvco = 0U;
+      }
+    }
+    else /* No source */
+    {
+      pllvco = 0U;
+    }
+
+    /* f(PLL Source) / PLLM */
+    pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
+
+    switch(PeriphClk)
+    {
+
+    case RCC_PERIPHCLK_USART1:
+      /* Get the current USART1 source */
+      srcclk = __HAL_RCC_GET_USART1_SOURCE();
+
+      if(srcclk == RCC_USART1CLKSOURCE_PCLK2)
+      {
+        frequency = HAL_RCC_GetPCLK2Freq();
+      }
+      else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI) )
+      {
+        frequency = HSI_VALUE;
+      }
+      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for USART1 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+    case RCC_PERIPHCLK_USART2:
+      /* Get the current USART2 source */
+      srcclk = __HAL_RCC_GET_USART2_SOURCE();
+
+      if(srcclk == RCC_USART2CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))  && (srcclk == RCC_USART2CLKSOURCE_LSE))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for USART2 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+    case RCC_PERIPHCLK_USART3:
+      /* Get the current USART3 source */
+      srcclk = __HAL_RCC_GET_USART3_SOURCE();
+
+      if(srcclk == RCC_USART3CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for USART3 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+#if defined(UART4)
+    case RCC_PERIPHCLK_UART4:
+      /* Get the current UART4 source */
+      srcclk = __HAL_RCC_GET_UART4_SOURCE();
+
+      if(srcclk == RCC_UART4CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for UART4 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+#endif /* UART4 */
+
+#if defined(UART5)
+    case RCC_PERIPHCLK_UART5:
+      /* Get the current UART5 source */
+      srcclk = __HAL_RCC_GET_UART5_SOURCE();
+
+      if(srcclk == RCC_UART5CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for UART5 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+#endif /* UART5 */
+
+    case RCC_PERIPHCLK_LPUART1:
+      /* Get the current LPUART1 source */
+      srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
+
+      if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for LPUART1 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+    case RCC_PERIPHCLK_I2C1:
+      /* Get the current I2C1 source */
+      srcclk = __HAL_RCC_GET_I2C1_SOURCE();
+
+      if(srcclk == RCC_I2C1CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
+      {
+        frequency = HSI_VALUE;
+      }
+      /* Clock not enabled for I2C1 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+    case RCC_PERIPHCLK_I2C2:
+      /* Get the current I2C2 source */
+      srcclk = __HAL_RCC_GET_I2C2_SOURCE();
+
+      if(srcclk == RCC_I2C2CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
+      {
+        frequency = HSI_VALUE;
+      }
+      /* Clock not enabled for I2C2 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+    case RCC_PERIPHCLK_I2C3:
+      /* Get the current I2C3 source */
+      srcclk = __HAL_RCC_GET_I2C3_SOURCE();
+
+      if(srcclk == RCC_I2C3CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_HSI))
+      {
+        frequency = HSI_VALUE;
+      }
+      /* Clock not enabled for I2C3 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+#if defined(I2C4)
+
+    case RCC_PERIPHCLK_I2C4:
+      /* Get the current I2C4 source */
+      srcclk = __HAL_RCC_GET_I2C4_SOURCE();
+
+      if(srcclk == RCC_I2C4CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
+      {
+        frequency = HSI_VALUE;
+      }
+      /* Clock not enabled for I2C4 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+#endif /* I2C4 */
+
+    case RCC_PERIPHCLK_LPTIM1:
+      /* Get the current LPTIM1 source */
+      srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+      if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI))
+      {
+        frequency = LSI_VALUE;
+      }
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI))
+      {
+        frequency = HSI_VALUE;
+      }
+      else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE))
+      {
+        frequency = LSE_VALUE;
+      }
+      /* Clock not enabled for LPTIM1 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+    case RCC_PERIPHCLK_SAI1:
+      /* Get the current SAI1 source */
+      srcclk = __HAL_RCC_GET_SAI1_SOURCE();
+
+      if(srcclk == RCC_SAI1CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if(srcclk == RCC_SAI1CLKSOURCE_PLL)
+      {
+        if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U)
+        {
+          /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+          plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+          frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
+        }
+      }
+      else if(srcclk == RCC_SAI1CLKSOURCE_EXT)
+      {
+        /* External clock used.*/
+        frequency = EXTERNAL_CLOCK_VALUE;
+      }
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SAI1CLKSOURCE_HSI))
+      {
+        frequency = HSI_VALUE;
+      }
+      /* Clock not enabled for SAI1 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+    case RCC_PERIPHCLK_I2S:
+      /* Get the current I2Sx source */
+      srcclk = __HAL_RCC_GET_I2S_SOURCE();
+
+      if(srcclk == RCC_I2SCLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else if(srcclk == RCC_I2SCLKSOURCE_PLL)
+      {
+        if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U)
+        {
+          /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+          plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+          frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
+        }
+      }
+      else if(srcclk == RCC_I2SCLKSOURCE_EXT)
+      {
+        /* External clock used.*/
+        frequency = EXTERNAL_CLOCK_VALUE;
+      }      
+      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2SCLKSOURCE_HSI))
+      {
+        frequency = HSI_VALUE;
+      }
+      /* Clock not enabled for I2S */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+#if defined(FDCAN1)
+    case RCC_PERIPHCLK_FDCAN:
+      /* Get the current FDCANx source */
+      srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
+
+      if(srcclk == RCC_FDCANCLKSOURCE_PCLK1)
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+      }
+      else if(srcclk == RCC_FDCANCLKSOURCE_HSE)
+      {
+        frequency = HSE_VALUE;
+      }
+      else if(srcclk == RCC_FDCANCLKSOURCE_PLL)
+      {
+        if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U)
+        {
+          /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+          plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+          frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
+        }
+      }
+      /* Clock not enabled for FDCAN */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+#endif /* FDCAN1 */
+    
+#if defined(USB)
+    
+    case RCC_PERIPHCLK_USB:
+      /* Get the current USB source */
+      srcclk = __HAL_RCC_GET_USB_SOURCE();
+      
+      if(srcclk == RCC_USBCLKSOURCE_PLL)  /* PLL ? */
+      {
+        /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+        plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+        frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
+      }
+      else if((HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48)) /* HSI48 ? */
+      {
+        frequency = HSI48_VALUE;
+      }
+      else /* No clock source */
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+      
+#endif /* USB */
+
+    case RCC_PERIPHCLK_RNG:
+      /* Get the current RNG source */
+      srcclk = __HAL_RCC_GET_RNG_SOURCE();
+
+      if(srcclk == RCC_RNGCLKSOURCE_PLL)  /* PLL ? */
+      {
+        /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+        plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+        frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
+      }
+      else if( (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48)) /* HSI48 ? */
+      {
+        frequency = HSI48_VALUE;
+      }
+      else /* No clock source */
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+    case RCC_PERIPHCLK_ADC12:
+      /* Get the current ADC12 source */
+      srcclk = __HAL_RCC_GET_ADC12_SOURCE();
+      
+      if(srcclk == RCC_ADC12CLKSOURCE_PLL)
+      {
+        if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U)
+        {
+          /* f(PLLP) = f(VCO input) * PLLN / PLLP */
+          plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+          pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
+          if(pllp == 0U)
+          {
+            if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
+            {
+              pllp = 17U;
+            }
+            else
+            {
+              pllp = 7U;
+            }
+          }
+          frequency = (pllvco * plln) / pllp;
+        }
+      }
+      else if(srcclk == RCC_ADC12CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      /* Clock not enabled for ADC12 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+#if defined(ADC345_COMMON)
+    case RCC_PERIPHCLK_ADC345:
+      /* Get the current ADC345 source */
+      srcclk = __HAL_RCC_GET_ADC345_SOURCE();
+      
+      if(srcclk == RCC_ADC345CLKSOURCE_PLL)
+      {
+        if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U)
+        {
+          /* f(PLLP) = f(VCO input) * PLLN / PLLP */
+          plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+          pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
+          if(pllp == 0U)
+          {
+            if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
+            {
+              pllp = 17U;
+            }
+            else
+            {
+              pllp = 7U;
+            }
+          }
+          frequency = (pllvco * plln) / pllp;
+        }
+      }
+      else if(srcclk == RCC_ADC345CLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      /* Clock not enabled for ADC345 */
+      else
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+#endif /* ADC345_COMMON */
+
+#if defined(QUADSPI)
+
+    case RCC_PERIPHCLK_QSPI:
+      /* Get the current QSPI source */
+      srcclk = __HAL_RCC_GET_QSPI_SOURCE();
+      
+      if(srcclk == RCC_QSPICLKSOURCE_PLL)  /* PLL ? */
+      {
+        /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+        plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+        frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
+      }
+      else if(srcclk == RCC_QSPICLKSOURCE_HSI)
+      {
+        frequency = HSI_VALUE;
+      }      
+      else if(srcclk == RCC_QSPICLKSOURCE_SYSCLK)
+      {
+        frequency = HAL_RCC_GetSysClockFreq();
+      }
+      else /* No clock source */
+      {
+        /* nothing to do: frequency already initialized to 0 */
+      }
+      break;
+
+#endif /* QUADSPI */
+
+    default:
+      break;
+    }
+  }
+
+  return(frequency);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
+ *  @brief  Extended Clock management functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended clock management functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the
+    activation or deactivation of LSE CSS,
+    Low speed clock output and clock after wake-up from STOP mode.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the LSE Clock Security System.
+  * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
+  *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
+  *         clock with HAL_RCCEx_PeriphCLKConfig().
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+}
+
+/**
+  * @brief  Disable the LSE Clock Security System.
+  * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
+  * @retval None
+  */
+void HAL_RCCEx_DisableLSECSS(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+
+  /* Disable LSE CSS IT if any */
+  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
+}
+
+/**
+  * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
+  * @note   LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS_IT(void)
+{
+  /* Enable LSE CSS */
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+
+  /* Enable LSE CSS IT */
+  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
+
+  /* Enable IT on EXTI Line 19 */
+  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
+  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
+}
+
+/**
+  * @brief Handle the RCC LSE Clock Security System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_LSECSS_IRQHandler(void)
+{
+  /* Check RCC LSE CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
+  {
+    /* RCC LSE Clock Security System interrupt user callback */
+    HAL_RCCEx_LSECSS_Callback();
+
+    /* Clear RCC LSE CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
+  }
+}
+
+/**
+  * @brief  RCCEx LSE Clock Security System interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_LSECSS_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Select the Low Speed clock source to output on LSCO pin (PA2).
+  * @param  LSCOSource  specifies the Low Speed clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_LSCOSOURCE_LSI  LSI clock selected as LSCO source
+  *            @arg @ref RCC_LSCOSOURCE_LSE  LSE clock selected as LSCO source
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+  FlagStatus       pwrclkchanged = RESET;
+  FlagStatus       backupchanged = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
+
+  /* LSCO Pin Clock Enable */
+  __LSCO_CLK_ENABLE();
+
+  /* Configure the LSCO pin in analog mode */
+  GPIO_InitStruct.Pin = LSCO_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
+
+  /* Update LSCOSEL clock source in Backup Domain control register */
+  if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+  {
+    __HAL_RCC_PWR_CLK_ENABLE();
+    pwrclkchanged = SET;
+  }
+  if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+  {
+    HAL_PWR_EnableBkUpAccess();
+    backupchanged = SET;
+  }
+
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
+
+  if(backupchanged == SET)
+  {
+    HAL_PWR_DisableBkUpAccess();
+  }
+  if(pwrclkchanged == SET)
+  {
+    __HAL_RCC_PWR_CLK_DISABLE();
+  }
+}
+
+/**
+  * @brief  Disable the Low Speed clock output.
+  * @retval None
+  */
+void HAL_RCCEx_DisableLSCO(void)
+{
+  FlagStatus       pwrclkchanged = RESET;
+  FlagStatus       backupchanged = RESET;
+
+  /* Update LSCOEN bit in Backup Domain control register */
+  if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+  {
+    __HAL_RCC_PWR_CLK_ENABLE();
+    pwrclkchanged = SET;
+  }
+  if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+  {
+    /* Enable access to the backup domain */
+    HAL_PWR_EnableBkUpAccess();
+    backupchanged = SET;
+  }
+
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+
+  /* Restore previous configuration */
+  if(backupchanged == SET)
+  {
+    /* Disable access to the backup domain */
+    HAL_PWR_DisableBkUpAccess();
+  }
+  if(pwrclkchanged == SET)
+  {
+    __HAL_RCC_PWR_CLK_DISABLE();
+  }
+}
+
+
+/**
+  * @}
+  */
+
+#if defined(CRS)
+
+/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
+ *  @brief  Extended Clock Recovery System Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Clock Recovery System Control functions  #####
+ ===============================================================================
+    [..]
+      For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
+
+      (#) In System clock config, HSI48 needs to be enabled
+
+      (#) Enable CRS clock in IP MSP init which will use CRS functions
+
+      (#) Call CRS functions as follows:
+          (##) Prepare synchronization configuration necessary for HSI48 calibration
+              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
+                        and also HSI48 oscillator smooth trimming.
+              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
+                        directly reload value with target and sychronization frequencies values
+          (##) Call function HAL_RCCEx_CRSConfig which
+              (+++) Resets CRS registers to their default values.
+              (+++) Configures CRS registers with synchronization configuration
+              (+++) Enables automatic calibration and frequency error counter feature
+           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
+           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
+           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
+           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
+           should be used as SYNC signal.
+
+          (##) A polling function is provided to wait for complete synchronization
+              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
+              (+++) According to CRS status, user can decide to adjust again the calibration or continue
+                        application if synchronization is OK
+
+      (#) User can retrieve information related to synchronization in calling function
+            HAL_RCCEx_CRSGetSynchronizationInfo()
+
+      (#) Regarding synchronization status and synchronization information, user can try a new calibration
+           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
+           Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
+           it means that the actual frequency is lower than the target (and so, that the TRIM value should be
+           incremented), while when it is detected during the upcounting phase it means that the actual frequency
+           is higher (and that the TRIM value should be decremented).
+
+      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
+          through CRS Handler (CRS_IRQn/CRS_IRQHandler)
+              (++) Call function HAL_RCCEx_CRSConfig()
+              (++) Enable CRS_IRQn (thanks to NVIC functions)
+              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
+              (++) Implement CRS status management in the following user callbacks called from
+                   HAL_RCCEx_CRS_IRQHandler():
+                   (+++) HAL_RCCEx_CRS_SyncOkCallback()
+                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()
+                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
+                   (+++) HAL_RCCEx_CRS_ErrorCallback()
+
+      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
+          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
+
+@endverbatim
+ * @{
+ */
+
+/**
+  * @brief  Start automatic synchronization for polling mode
+  * @param  pInit Pointer on RCC_CRSInitTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
+{
+  uint32_t value;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
+  assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
+  assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
+  assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
+  assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
+  assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
+
+  /* CONFIGURATION */
+
+  /* Before configuration, reset CRS registers to their default values*/
+  __HAL_RCC_CRS_FORCE_RESET();
+  __HAL_RCC_CRS_RELEASE_RESET();
+
+  /* Set the SYNCDIV[2:0] bits according to Prescaler value */
+  /* Set the SYNCSRC[1:0] bits according to Source value */
+  /* Set the SYNCSPOL bit according to Polarity value */
+  value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
+  /* Set the RELOAD[15:0] bits according to ReloadValue value */
+  value |= pInit->ReloadValue;
+  /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
+  value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
+  WRITE_REG(CRS->CFGR, value);
+
+  /* Adjust HSI48 oscillator smooth trimming */
+  /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
+
+  /* START AUTOMATIC SYNCHRONIZATION*/
+
+  /* Enable Automatic trimming & Frequency error counter */
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
+}
+
+/**
+  * @brief  Generate the software synchronization event
+  * @retval None
+  */
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Return synchronization info
+  * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
+{
+  /* Check the parameter */
+  assert_param(pSynchroInfo != (void *)NULL);
+
+  /* Get the reload value */
+  pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+
+  /* Get HSI48 oscillator smooth trimming */
+  pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+
+  /* Get Frequency error capture */
+  pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+
+  /* Get Frequency error direction */
+  pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+* @brief Wait for CRS Synchronization status.
+* @param Timeout  Duration of the timeout
+* @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
+*        frequency.
+* @note    If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
+* @retval Combination of Synchronization status
+*          This parameter can be a combination of the following values:
+*            @arg @ref RCC_CRS_TIMEOUT
+*            @arg @ref RCC_CRS_SYNCOK
+*            @arg @ref RCC_CRS_SYNCWARN
+*            @arg @ref RCC_CRS_SYNCERR
+*            @arg @ref RCC_CRS_SYNCMISS
+*            @arg @ref RCC_CRS_TRIMOVF
+*/
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
+{
+  uint32_t crsstatus = RCC_CRS_NONE;
+  uint32_t tickstart;
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  /* Wait for CRS flag or timeout detection */
+  do
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        crsstatus = RCC_CRS_TIMEOUT;
+      }
+    }
+    /* Check CRS SYNCOK flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
+    {
+      /* CRS SYNC event OK */
+      crsstatus |= RCC_CRS_SYNCOK;
+
+      /* Clear CRS SYNC event OK bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
+    }
+
+    /* Check CRS SYNCWARN flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
+    {
+      /* CRS SYNC warning */
+      crsstatus |= RCC_CRS_SYNCWARN;
+
+      /* Clear CRS SYNCWARN bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
+    }
+
+    /* Check CRS TRIM overflow flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_TRIMOVF;
+
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
+    }
+
+    /* Check CRS Error flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_SYNCERR;
+
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
+    }
+
+    /* Check CRS SYNC Missed flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
+    {
+      /* CRS SYNC Missed */
+      crsstatus |= RCC_CRS_SYNCMISS;
+
+      /* Clear CRS SYNC Missed bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
+    }
+
+    /* Check CRS Expected SYNC flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
+    {
+      /* frequency error counter reached a zero value */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
+    }
+  } while(RCC_CRS_NONE == crsstatus);
+
+  return crsstatus;
+}
+
+/**
+  * @brief Handle the Clock Recovery System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_CRS_IRQHandler(void)
+{
+  uint32_t crserror = RCC_CRS_NONE;
+  /* Get current IT flags and IT sources values */
+  uint32_t itflags = READ_REG(CRS->ISR);
+  uint32_t itsources = READ_REG(CRS->CR);
+
+  /* Check CRS SYNCOK flag  */
+  if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
+  {
+    /* Clear CRS SYNC event OK flag */
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_SyncOkCallback();
+  }
+  /* Check CRS SYNCWARN flag  */
+  else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
+  {
+    /* Clear CRS SYNCWARN flag */
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_SyncWarnCallback();
+  }
+  /* Check CRS Expected SYNC flag  */
+  else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
+  {
+    /* frequency error counter reached a zero value */
+    WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_ExpectedSyncCallback();
+  }
+  /* Check CRS Error flags  */
+  else
+  {
+    if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
+    {
+      if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
+      {
+        crserror |= RCC_CRS_SYNCERR;
+      }
+      if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
+      {
+        crserror |= RCC_CRS_SYNCMISS;
+      }
+      if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
+      {
+        crserror |= RCC_CRS_TRIMOVF;
+      }
+
+      /* Clear CRS Error flags */
+      WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+
+      /* user error callback */
+      HAL_RCCEx_CRS_ErrorCallback(crserror);
+    }
+  }
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System Error interrupt callback.
+  * @param  Error Combination of Error status.
+  *         This parameter can be a combination of the following values:
+  *           @arg @ref RCC_CRS_SYNCERR
+  *           @arg @ref RCC_CRS_SYNCMISS
+  *           @arg @ref RCC_CRS_TRIMOVF
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Error);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+#endif /* CRS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCCEx_Private_Functions
+ * @{
+ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c
new file mode 100644
index 0000000..02cbdb4
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c
@@ -0,0 +1,8108 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer (TIM) peripheral:
+  *           + TIM Time Base Initialization
+  *           + TIM Time Base Start
+  *           + TIM Time Base Start Interruption
+  *           + TIM Time Base Start DMA
+  *           + TIM Output Compare/PWM Initialization
+  *           + TIM Output Compare/PWM Channel Configuration
+  *           + TIM Output Compare/PWM  Start
+  *           + TIM Output Compare/PWM  Start Interruption
+  *           + TIM Output Compare/PWM Start DMA
+  *           + TIM Input Capture Initialization
+  *           + TIM Input Capture Channel Configuration
+  *           + TIM Input Capture Start
+  *           + TIM Input Capture Start Interruption
+  *           + TIM Input Capture Start DMA
+  *           + TIM One Pulse Initialization
+  *           + TIM One Pulse Channel Configuration
+  *           + TIM One Pulse Start
+  *           + TIM Encoder Interface Initialization
+  *           + TIM Encoder Interface Start
+  *           + TIM Encoder Interface Start Interruption
+  *           + TIM Encoder Interface Start DMA
+  *           + Commutation Event configuration with Interruption and DMA
+  *           + TIM OCRef clear configuration
+  *           + TIM External Clock configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Generic features #####
+  ==============================================================================
+  [..] The Timer features include:
+       (#) 16-bit up, down, up/down auto-reload counter.
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+           counter clock frequency either by any factor between 1 and 65536.
+       (#) Up to 4 independent channels for:
+           (++) Input Capture
+           (++) Output Compare
+           (++) PWM generation (Edge and Center-aligned Mode)
+           (++) One-pulse mode output
+       (#) Synchronization circuit to control the timer with external signals and to interconnect
+            several timers together.
+       (#) Supports incremental encoder for positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Time Base : HAL_TIM_Base_MspInit()
+           (++) Input Capture : HAL_TIM_IC_MspInit()
+           (++) Output Compare : HAL_TIM_OC_MspInit()
+           (++) PWM generation : HAL_TIM_PWM_MspInit()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+             __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+       Initialization function of this driver:
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+       (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare:
+            to use the Timer to generate an Output Compare signal.
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+            PWM signal.
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+            external signal.
+       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+            in One Pulse Mode.
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+     (#) The DMA Burst is managed with the two following functions:
+         HAL_TIM_DMABurst_WriteStart()
+         HAL_TIM_DMABurst_ReadStart()
+
+    *** Callback registration ***
+  =============================================
+
+  [..]
+  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+
+  [..]
+  Use Function HAL_TIM_RegisterCallback() to register a callback.
+  HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  the Callback ID and a pointer to the user callback function.
+
+  [..]
+  Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+
+  [..]
+  These functions allow to register/unregister following callbacks:
+    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
+    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
+    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+    (+) TriggerCallback                   : TIM Trigger Callback.
+    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+    (+) IC_CaptureCallback                : TIM Input Capture Callback.
+    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+    (+) ErrorCallback                     : TIM Error Callback.
+    (+) CommutationCallback               : TIM Commutation Callback.
+    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
+    (+) BreakCallback                     : TIM Break Callback.
+    (+) Break2Callback                    : TIM Break2 Callback.
+    (+) EncoderIndexCallback              : TIM Encoder Index Callback.
+    (+) DirectionChangeCallback           : TIM Direction Change Callback
+    (+) IndexErrorCallback                : TIM Index Error Callback.
+    (+) TransitionErrorCallback           : TIM Transition Error Callback
+
+  [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+  examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
+
+  [..]
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+  functionalities in the Init / DeInit only when these callbacks are null
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+  [..]
+    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+    Exception done MspInit / MspDeInit that can be registered / unregistered
+    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+  [..]
+      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registration feature is not available and all callbacks
+      are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIM TIM
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup TIM_Private_Constants
+  * @{
+  */
+#define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL
+
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+  * @{
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief    Time Base functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Time Base functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM base.
+    (+) De-initialize the TIM base.
+    (+) Start the Time Base.
+    (+) Stop the Time Base.
+    (+) Start the Time Base and enable interrupt.
+    (+) Stop the Time Base and disable interrupt.
+    (+) Start the Time Base and enable DMA transfer.
+    (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Time base Unit according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Base_MspInitCallback == NULL)
+    {
+      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Base peripheral
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Base_MspDeInitCallback == NULL)
+  {
+    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Base_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Starts the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the DMA Period elapsed callbacks */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA channel */
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
+                       Length) != HAL_OK)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+
+  /* Enable the TIM Update DMA request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief    TIM Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### TIM Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Output Compare.
+    (+) De-initialize the TIM Output Compare.
+    (+) Start the TIM Output Compare.
+    (+) Stop the TIM Output Compare.
+    (+) Start the TIM Output Compare and enable interrupt.
+    (+) Stop the TIM Output Compare and disable interrupt.
+    (+) Start the TIM Output Compare and enable DMA transfer.
+    (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Output Compare according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OC_MspInitCallback == NULL)
+    {
+      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the Output Compare */
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OC_MspDeInitCallback == NULL)
+  {
+    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief    TIM PWM functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM PWM.
+    (+) De-initialize the TIM PWM.
+    (+) Start the TIM PWM.
+    (+) Stop the TIM PWM.
+    (+) Start the TIM PWM and enable interrupt.
+    (+) Stop the TIM PWM and disable interrupt.
+    (+) Start the TIM PWM and enable DMA transfer.
+    (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM PWM Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->PWM_MspInitCallback == NULL)
+    {
+      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->PWM_MspDeInitCallback == NULL)
+  {
+    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->PWM_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the PWM signal generation.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Capture/Compare 3 request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief    TIM Input Capture functions
+  *
+@verbatim
+  ==============================================================================
+              ##### TIM Input Capture functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+   (+) Initialize and configure the TIM Input Capture.
+   (+) De-initialize the TIM Input Capture.
+   (+) Start the TIM Input Capture.
+   (+) Stop the TIM Input Capture.
+   (+) Start the TIM Input Capture and enable interrupt.
+   (+) Stop the TIM Input Capture and disable interrupt.
+   (+) Start the TIM Input Capture and enable DMA transfer.
+   (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Input Capture Time base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->IC_MspInitCallback == NULL)
+    {
+      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->IC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the input capture */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->IC_MspDeInitCallback == NULL)
+  {
+    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->IC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture MSP.
+  * @param  htim TIM Input Capture handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Input Capture MSP.
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel state */
+  if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+      || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+  {
+    return HAL_BUSY;
+  }
+  else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
+           && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief    TIM One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM One Pulse.
+    (+) De-initialize the TIM One Pulse.
+    (+) Start the TIM One Pulse.
+    (+) Stop the TIM One Pulse.
+    (+) Start the TIM One Pulse and enable interrupt.
+    (+) Stop the TIM One Pulse and disable interrupt.
+    (+) Start the TIM One Pulse and enable DMA transfer.
+    (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+  * @note   When the timer instance is initialized in One Pulse mode, timer
+  *         channels 1 and channel 2 are reserved and cannot be used for other
+  *         purpose.
+  * @param  htim TIM One Pulse handle
+  * @param  OnePulseMode Select the One pulse mode.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OnePulse_MspInitCallback == NULL)
+    {
+      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OnePulse_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the One Pulse Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Reset the OPM Bit */
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  htim->Instance->CR1 |= OnePulseMode;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM One Pulse
+  * @param  htim TIM One Pulse handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OnePulse_MspDeInitCallback == NULL)
+  {
+    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OnePulse_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief    TIM Encoder functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM Encoder functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Encoder.
+    (+) De-initialize the TIM Encoder.
+    (+) Start the TIM Encoder.
+    (+) Stop the TIM Encoder.
+    (+) Start the TIM Encoder and enable interrupt.
+    (+) Stop the TIM Encoder and disable interrupt.
+    (+) Start the TIM Encoder and enable DMA transfer.
+    (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
+  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+  * @note   When the timer instance is initialized in Encoder mode, timer
+  *         channels 1 and channel 2 are reserved and cannot be used for other
+  *         purpose.
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Encoder_MspInitCallback == NULL)
+    {
+      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Encoder_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Reset the SMS and ECE bits */
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitializes the TIM Encoder interface
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Encoder_MspDeInitCallback == NULL)
+  {
+    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Encoder_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+
+  /* Enable the encoder interface channels */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+  }
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+
+  /* Enable the encoder interface channels */
+  /* Enable the capture compare Interrupts 1 and/or 2 */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 and 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @param  pData1 The destination Buffer address for IC1.
+  * @param  pData2 The destination Buffer address for IC2.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((pData1 == NULL) && (Length > 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((pData2 == NULL) && (Length > 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+
+    default:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 and 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief    TIM IRQ handler management
+  *
+@verbatim
+  ==============================================================================
+                        ##### IRQ handler management #####
+  ==============================================================================
+  [..]
+    This section provides Timer IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+  /* Capture compare 1 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+    {
+      {
+        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        /* Output compare event */
+        else
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 3 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 4 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* TIM Update event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->BreakCallback(htim);
+#else
+      HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break2 input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->Break2Callback(htim);
+#else
+      HAL_TIMEx_Break2Callback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM commutation event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->CommutationCallback(htim);
+#else
+      HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Encoder index event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IDX) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IDX) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->EncoderIndexCallback(htim);
+#else
+      HAL_TIMEx_EncoderIndexCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Direction change event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_DIR) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_DIR) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->DirectionChangeCallback(htim);
+#else
+      HAL_TIMEx_DirectionChangeCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Index error event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IERR) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IERR) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->IndexErrorCallback(htim);
+#else
+      HAL_TIMEx_IndexErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Transition error event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TERR) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TERR) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TransitionErrorCallback(htim);
+#else
+      HAL_TIMEx_TransitionErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief    TIM Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                   ##### Peripheral Control functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+      (+) Configure External Clock source.
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master and the Slave synchronization.
+      (+) Configure the DMA Burst Mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM Output Compare Channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM Output Compare handle
+  * @param  sConfig TIM Output Compare configuration structure
+  * @param  Channel TIM Channels to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+                                           TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 1 in Output Compare */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 2 in Output Compare */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 3 in Output Compare */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 4 in Output Compare */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 5 in Output Compare */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 6 in Output Compare */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture Channels according to the specified
+  *         parameters in the TIM_IC_InitTypeDef.
+  * @param  htim TIM IC handle
+  * @param  sConfig TIM Input Capture configuration structure
+  * @param  Channel TIM Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  if (Channel == TIM_CHANNEL_1)
+  {
+    /* TI1 Configuration */
+    TIM_TI1_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Set the IC1PSC value */
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    /* TI2 Configuration */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+    TIM_TI2_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC2PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+    /* Set the IC2PSC value */
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+  }
+  else if (Channel == TIM_CHANNEL_3)
+  {
+    /* TI3 Configuration */
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+    TIM_TI3_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC3PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+    /* Set the IC3PSC value */
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_4)
+  {
+    /* TI4 Configuration */
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+    TIM_TI4_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC4PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+    /* Set the IC4PSC value */
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM PWM  channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM PWM handle
+  * @param  sConfig TIM PWM configuration structure
+  * @param  Channel TIM Channels to be configured
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 5 in PWM mode */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel5*/
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 6 in PWM mode */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel6 */
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse Channels according to the specified
+  *         parameters in the TIM_OnePulse_InitTypeDef.
+  * @param  htim TIM One Pulse handle
+  * @param  sConfig TIM One Pulse configuration structure
+  * @param  OutputChannel TIM output channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  InputChannel TIM input Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @note  To output a waveform with a minimum delay user can enable the fast
+  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+  *        output is forced in response to the edge detection on TIx input,
+  *        without taking in account the comparison.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  TIM_OC_InitTypeDef temp1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+  if (OutputChannel != InputChannel)
+  {
+    /* Process Locked */
+    __HAL_LOCK(htim);
+
+    htim->State = HAL_TIM_STATE_BUSY;
+
+    /* Extract the Output compare configuration from sConfig structure */
+    temp1.OCMode = sConfig->OCMode;
+    temp1.Pulse = sConfig->Pulse;
+    temp1.OCPolarity = sConfig->OCPolarity;
+    temp1.OCNPolarity = sConfig->OCNPolarity;
+    temp1.OCIdleState = sConfig->OCIdleState;
+    temp1.OCNIdleState = sConfig->OCNIdleState;
+
+    switch (OutputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_OC1_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_OC2_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+
+    if (status == HAL_OK)
+    {
+      switch (InputChannel)
+      {
+        case TIM_CHANNEL_1:
+        {
+          assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+          TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC1PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        case TIM_CHANNEL_2:
+        {
+          assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+          TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC2PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        default:
+          status = HAL_ERROR;
+          break;
+      }
+    }
+
+    htim->State = HAL_TIM_STATE_READY;
+
+    __HAL_UNLOCK(htim);
+
+    return status;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_DTR2
+  *            @arg TIM_DMABASE_ECR
+  *            @arg TIM_DMABASE_TISEL
+  *            @arg TIM_DMABASE_AF1
+  *            @arg TIM_DMABASE_AF2
+  *            @arg TIM_DMABASE_OR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
+{
+  HAL_StatusTypeDef status;
+
+  status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                            ((BurstLength) >> 8U) + 1U);
+
+
+
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_DTR2
+  *            @arg TIM_DMABASE_ECR
+  *            @arg TIM_DMABASE_TISEL
+  *            @arg TIM_DMABASE_AF1
+  *            @arg TIM_DMABASE_AF2
+  *            @arg TIM_DMABASE_OR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+                                                   uint32_t  BurstLength,  uint32_t  DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM DMA Burst mode
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA channel) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_DTR2
+  *            @arg TIM_DMABASE_ECR
+  *            @arg TIM_DMABASE_TISEL
+  *            @arg TIM_DMABASE_AF1
+  *            @arg TIM_DMABASE_AF2
+  *            @arg TIM_DMABASE_OR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+  HAL_StatusTypeDef status;
+
+  status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                           ((BurstLength) >> 8U) + 1U);
+
+
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_DTR2
+  *            @arg TIM_DMABASE_ECR
+  *            @arg TIM_DMABASE_TISEL
+  *            @arg TIM_DMABASE_AF1
+  *            @arg TIM_DMABASE_AF2
+  *            @arg TIM_DMABASE_OR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stop the DMA burst reading
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA channel) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Generate a software event
+  * @param  htim TIM handle
+  * @param  EventSource specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
+  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+  * @note   Basic timers can only generate an update event.
+  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+  * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+  *         only for timer instances supporting break input(s).
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the event sources */
+  htim->Instance->EGR = EventSource;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the OCRef clear feature
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (sClearInputConfig->ClearInputSource)
+  {
+    case TIM_CLEARINPUTSOURCE_NONE:
+    {
+      /* Clear the OCREF clear selection bit and the the ETR Bits */
+      if (IS_TIM_OCCS_INSTANCE(htim->Instance))
+      {
+        CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+
+        /* Clear TIMx_AF2_OCRSEL (reset value) */
+        CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
+      }
+      else
+      {
+        CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+      }
+      break;
+    }
+
+    case TIM_CLEARINPUTSOURCE_COMP1:
+    case TIM_CLEARINPUTSOURCE_COMP2:
+    case TIM_CLEARINPUTSOURCE_COMP3:
+    case TIM_CLEARINPUTSOURCE_COMP4:
+#if defined (COMP5)
+    case TIM_CLEARINPUTSOURCE_COMP5:
+#endif /* COMP5 */
+#if defined (COMP6)
+    case TIM_CLEARINPUTSOURCE_COMP6:
+#endif /* COMP6 */
+#if defined (COMP7)
+    case TIM_CLEARINPUTSOURCE_COMP7:
+#endif /* COMP7 */
+    {
+      if (IS_TIM_OCCS_INSTANCE(htim->Instance))
+      {
+        /* Clear the OCREF clear selection bit */
+        CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+
+        /* Clear TIM1_AF2_OCRSEL (reset value) */
+        MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource);
+      }
+      break;
+    }
+
+    case TIM_CLEARINPUTSOURCE_ETR:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+      {
+        htim->State = HAL_TIM_STATE_READY;
+        __HAL_UNLOCK(htim);
+        return HAL_ERROR;
+      }
+
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClearInputConfig->ClearInputPrescaler,
+                        sClearInputConfig->ClearInputPolarity,
+                        sClearInputConfig->ClearInputFilter);
+
+      if (IS_TIM_OCCS_INSTANCE(htim->Instance))
+      {
+        /* Set the OCREF clear selection bit */
+        SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+
+        /* Clear TIMx_AF2_OCRSEL (reset value) */
+        CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
+      }
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    switch (Channel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 1 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 1 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 2 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 2 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_3:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 3 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 3 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_4:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 4 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 4 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_5:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 5 */
+          SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 5 */
+          CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_6:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 6 */
+          SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 6 */
+          CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+        }
+        break;
+      }
+      default:
+        break;
+    }
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief   Configures the clock source to be used
+  * @param  htim TIM handle
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+  htim->Instance->SMCR = tmpsmcr;
+
+  switch (sClockSourceConfig->ClockSource)
+  {
+    case TIM_CLOCKSOURCE_INTERNAL:
+    {
+      assert_param(IS_TIM_INSTANCE(htim->Instance));
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE1:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE2:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI2:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1ED:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ITR0:
+    case TIM_CLOCKSOURCE_ITR1:
+    case TIM_CLOCKSOURCE_ITR2:
+    case TIM_CLOCKSOURCE_ITR3:
+#if defined (TIM5)
+    case TIM_CLOCKSOURCE_ITR4:
+#endif /* TIM5 */
+    case TIM_CLOCKSOURCE_ITR5:
+    case TIM_CLOCKSOURCE_ITR6:
+    case TIM_CLOCKSOURCE_ITR7:
+    case TIM_CLOCKSOURCE_ITR8:
+#if defined (TIM20)
+    case TIM_CLOCKSOURCE_ITR9:
+#endif /* TIM20 */
+#if defined (HRTIM1)
+    case TIM_CLOCKSOURCE_ITR10:
+#endif /* HRTIM1 */
+    case TIM_CLOCKSOURCE_ITR11:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input
+  * @param  htim TIM handle.
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
+  *         output of a XOR gate.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+  *            pins are connected to the TI1 input (XOR combination)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Reset the TI1 selection */
+  tmpcr2 &= ~TIM_CR2_TI1S;
+
+  /* Set the TI1 selection */
+  tmpcr2 |= TI1_Selection;
+
+  /* Write to TIMxCR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Disable Trigger Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode in interrupt mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+                                                TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Enable Trigger Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read the captured value from Capture Compare unit
+  * @param  htim TIM handle.
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval Captured value
+  */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpreg = 0U;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Return the capture 1 value */
+      tmpreg =  htim->Instance->CCR1;
+
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Return the capture 2 value */
+      tmpreg =   htim->Instance->CCR2;
+
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Return the capture 3 value */
+      tmpreg =   htim->Instance->CCR3;
+
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Return the capture 4 value */
+      tmpreg =   htim->Instance->CCR4;
+
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief    TIM Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM Callbacks functions #####
+  ==============================================================================
+ [..]
+   This section provides TIM callback functions:
+   (+) TIM Period elapsed callback
+   (+) TIM Output Compare callback
+   (+) TIM Input capture callback
+   (+) TIM Trigger callback
+   (+) TIM Error callback
+   (+) TIM Index callback
+   (+) TIM Direction change callback
+   (+) TIM Index error callback
+   (+) TIM Transition error callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Period elapsed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture half complete callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timer error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
+  *          @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
+  *          @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
+  *          @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
+  *          @param pCallback pointer to the callback function
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback               = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback                = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback             = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback              = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback            = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback                = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback        = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                      = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback              = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback              = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback            = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback          = pCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        htim->Break2Callback                       = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_INDEX_CB_ID :
+        htim->EncoderIndexCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_DIRECTION_CHANGE_CB_ID :
+        htim->DirectionChangeCallback              = pCallback;
+        break;
+
+      case HAL_TIM_INDEX_ERROR_CB_ID :
+        htim->IndexErrorCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_TRANSITION_ERROR_CB_ID :
+        htim->TransitionErrorCallback              = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a TIM callback
+  *         TIM callback is redirected to the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
+  *          @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
+  *          @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
+  *          @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp Init Callback */
+        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp DeInit Callback */
+        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        /* Legacy weak Period Elapsed Callback */
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        /* Legacy weak Period Elapsed half complete Callback */
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        /* Legacy weak Trigger Callback */
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        /* Legacy weak Trigger half complete Callback */
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        /* Legacy weak IC Capture Callback */
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        /* Legacy weak IC Capture half complete Callback */
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        /* Legacy weak OC Delay Elapsed Callback */
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        /* Legacy weak PWM Pulse Finished Callback */
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        /* Legacy weak PWM Pulse Finished half complete Callback */
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        /* Legacy weak Error Callback */
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        /* Legacy weak Commutation Callback */
+        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        /* Legacy weak Commutation half complete Callback */
+        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        /* Legacy weak Break Callback */
+        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        /* Legacy weak Break2 Callback */
+        htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
+        break;
+
+      case HAL_TIM_ENCODER_INDEX_CB_ID :
+        /* Legacy weak Encoder Index Callback */
+        htim->EncoderIndexCallback              = HAL_TIMEx_EncoderIndexCallback;
+        break;
+
+      case HAL_TIM_DIRECTION_CHANGE_CB_ID :
+        /* Legacy weak Direction Change Callback */
+        htim->DirectionChangeCallback           = HAL_TIMEx_DirectionChangeCallback;
+        break;
+
+      case HAL_TIM_INDEX_ERROR_CB_ID :
+        /* Legacy weak Index Error Callback */
+        htim->IndexErrorCallback                = HAL_TIMEx_IndexErrorCallback;
+        break;
+
+      case HAL_TIM_TRANSITION_ERROR_CB_ID :
+        /* Legacy weak Transition Error Callback */
+        htim->TransitionErrorCallback           = HAL_TIMEx_TransitionErrorCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp Init Callback */
+        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp DeInit Callback */
+        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief   TIM Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base handle state.
+  * @param  htim TIM Base handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC handle state.
+  * @param  htim TIM Output Compare handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM handle state.
+  * @param  htim TIM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Input Capture handle state.
+  * @param  htim TIM IC handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM One Pulse Mode handle state.
+  * @param  htim TIM OPM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM handle
+  * @retval Active channel
+  */
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
+{
+  return htim->Channel;
+}
+
+/**
+  * @brief  Return actual state of the TIM channel.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval TIM Channel state
+  */
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_state;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+  return channel_state;
+}
+
+/**
+  * @brief  Return actual state of a DMA burst operation.
+  * @param  htim TIM handle
+  * @retval DMA burst state
+  */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+  return htim->DMABurstState;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA error callback
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureCallback(htim);
+#else
+  HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureHalfCpltCallback(htim);
+#else
+  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Period Elapse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Period Elapse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerCallback(htim);
+#else
+  HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerHalfCpltCallback(htim);
+#else
+  HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+  * @brief  Timer Output Compare 1 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= OC_Config->OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC1NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS1;
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= OC_Config->OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= OC_Config->OCNIdleState;
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 3 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 8U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC3NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS3;
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 4U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 4 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC4NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 12U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC4NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4;
+    /* Reset the Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4N;
+
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 6U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 6U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 5 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC5E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC5M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC5P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 16U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS5;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 8U);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR5 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 6 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC6E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC6M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 20U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS6;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 10U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR6 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Slave Timer configuration function
+  * @param  htim TIM handle
+  * @param  sSlaveConfig Slave timer configuration
+  * @retval None
+  */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the Trigger Selection Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source */
+  tmpsmcr |= sSlaveConfig->InputTrigger;
+
+  /* Reset the slave mode Bits */
+  tmpsmcr &= ~TIM_SMCR_SMS;
+  /* Set the slave mode */
+  tmpsmcr |= sSlaveConfig->SlaveMode;
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Configure the trigger prescaler, filter, and polarity */
+  switch (sSlaveConfig->InputTrigger)
+  {
+    case TIM_TS_ETRF:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      /* Configure the ETR Trigger source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sSlaveConfig->TriggerPrescaler,
+                        sSlaveConfig->TriggerPolarity,
+                        sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI1F_ED:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \
+          (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
+      {
+        return HAL_ERROR;
+      }
+
+      /* Disable the Channel 1: Reset the CC1E Bit */
+      tmpccer = htim->Instance->CCER;
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;
+      tmpccmr1 = htim->Instance->CCMR1;
+
+      /* Set the filter */
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+      /* Write to TIMx CCMR1 and CCER registers */
+      htim->Instance->CCMR1 = tmpccmr1;
+      htim->Instance->CCER = tmpccer;
+      break;
+    }
+
+    case TIM_TS_TI1FP1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI1 Filter and Polarity */
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI2FP2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI2 Filter and Polarity */
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_ITR0:
+    case TIM_TS_ITR1:
+    case TIM_TS_ITR2:
+    case TIM_TS_ITR3:
+#if defined (TIM5)
+    case TIM_TS_ITR4:
+#endif /* TIM5 */
+    case TIM_TS_ITR5:
+    case TIM_TS_ITR6:
+    case TIM_TS_ITR7:
+    case TIM_TS_ITR8:
+#if defined (TIM20)
+    case TIM_TS_ITR9:
+#endif /* TIM20 */
+#if defined (HRTIM1)
+    case TIM_TS_ITR10:
+#endif /* HRTIM1 */
+    case TIM_TS_ITR11:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger));
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  }
+  else
+  {
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI1.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;
+  tmpccmr1 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI2.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4U);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;
+  tmpccmr2 |= TIM_ICSelection;
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;
+  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  * @retval None
+  */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;
+  tmpccmr2 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;
+  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx to select the TIM peripheral
+  * @param  InputTriggerSource The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  *            @arg TIM_TS_ITR4: Internal Trigger 4  (*)
+  *            @arg TIM_TS_ITR5: Internal Trigger 5
+  *            @arg TIM_TS_ITR6: Internal Trigger 6
+  *            @arg TIM_TS_ITR7: Internal Trigger 7
+  *            @arg TIM_TS_ITR8: Internal Trigger 8
+  *            @arg TIM_TS_ITR9: Internal Trigger 9   (*)
+  *            @arg TIM_TS_ITR10: Internal Trigger 10
+  *            @arg TIM_TS_ITR11: Internal Trigger 11
+  *
+  *       (*)  Value not defined in all devices.
+  *
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+  * @param  ExtTRGFilter External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
+  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+  /* Reset the TIM callback to the legacy weak callbacks */
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+  htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
+  htim->EncoderIndexCallback              = HAL_TIMEx_EncoderIndexCallback;
+  htim->DirectionChangeCallback           = HAL_TIMEx_DirectionChangeCallback;
+  htim->IndexErrorCallback                = HAL_TIMEx_IndexErrorCallback;
+  htim->TransitionErrorCallback           = HAL_TIMEx_TransitionErrorCallback;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c
new file mode 100644
index 0000000..0ffa8d1
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c
@@ -0,0 +1,3701 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_tim_ex.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer Extended peripheral:
+  *           + Time Hall Sensor Interface Initialization
+  *           + Time Hall Sensor Interface Start
+  *           + Time Complementary signal break and dead time configuration
+  *           + Time Master and Slave synchronization configuration
+  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+  *           + Time OCRef clear configuration
+  *           + Timer remapping capabilities configuration
+  *           + Timer encoder index configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Extended features #####
+  ==============================================================================
+  [..]
+    The Timer Extended features include:
+    (#) Complementary outputs with programmable dead-time for :
+        (++) Output Compare
+        (++) PWM generation (Edge and Center-aligned Mode)
+        (++) One-pulse mode output
+    (#) Synchronization circuit to control the timer with external signals and to
+        interconnect several timers together.
+    (#) Break input to put the timer output signals in reset state or in a known state.
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+        positioning purposes
+    (#) In case of Pulse on compare, configure pulse length and delay
+    (#) Encoder index configuration
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+              __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+         initialization function of this driver:
+          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+               Timer Hall Sensor Interface and the commutation event with the corresponding
+               Interrupt and DMA request if needed (Note that One Timer is used to interface
+               with the Hall sensor Interface and another Timer should be used to use
+               the commutation event).
+     (#) In case of Pulse On Compare:
+           (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler
+
+
+     (#) Activate the TIM peripheral using one of the start functions:
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+                HAL_TIMEx_OCN_Start_IT()
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+                HAL_TIMEx_PWMN_Start_IT()
+           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
+                HAL_TIMEx_HallSensor_Start_IT().
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIMEx TIMEx
+  * @brief TIM Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
+  * @{
+  */
+/* Timeout for break input rearm */
+#define TIM_BREAKINPUT_REARM_TIMEOUT    5UL /* 5 milliseconds */
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  * @brief    Timer Hall Sensor functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Timer Hall Sensor functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure TIM HAL Sensor.
+    (+) De-initialize TIM HAL Sensor.
+    (+) Start the Hall Sensor Interface.
+    (+) Stop the Hall Sensor Interface.
+    (+) Start the Hall Sensor Interface and enable interrupts.
+    (+) Stop the Hall Sensor Interface and disable interrupts.
+    (+) Start the Hall Sensor Interface and enable DMA transfers.
+    (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+  * @note   When the timer instance is initialized in Hall Sensor Interface mode,
+  *         timer channels 1 and channel 2 are reserved and cannot be used for
+  *         other purpose.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  sConfig TIM Hall Sensor configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
+{
+  TIM_OC_InitTypeDef OC_Config;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy week callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->HallSensor_MspInitCallback == NULL)
+    {
+      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->HallSensor_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
+  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+  /* Reset the IC1PSC Bits */
+  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+  /* Set the IC1PSC value */
+  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+  /* Enable the Hall sensor interface (XOR function of the three inputs) */
+  htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+  htim->Instance->SMCR &= ~TIM_SMCR_TS;
+  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+  OC_Config.OCMode = TIM_OCMODE_PWM2;
+  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+  OC_Config.Pulse = sConfig->Commutation_Delay;
+
+  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+    register to 101 */
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Hall Sensor interface
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->HallSensor_MspDeInitCallback == NULL)
+  {
+    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->HallSensor_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1, 2 and 3
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the capture compare Interrupts 1 event */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the capture compare Interrupts event */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel state */
+  if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+      || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+  {
+    return HAL_BUSY;
+  }
+  else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+           && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Set the DMA Input Capture 1 Callbacks */
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA channel for Capture 1*/
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  /* Enable the capture compare 1 Interrupt */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+  /* Disable the capture compare Interrupts 1 event */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Timer Complementary Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary Output Compare/PWM.
+    (+) Stop the Complementary Output Compare/PWM.
+    (+) Start the Complementary Output Compare/PWM and enable interrupts.
+    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM OC handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the TIM Break interrupt */
+    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+    /* Enable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the TIM Break interrupt (only if no more channel is active) */
+    tmpccer = htim->Instance->CCER;
+    if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE  | TIM_CCER_CC4NE)) == (uint32_t)RESET)
+    {
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    }
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  * @brief    Timer Complementary PWM functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Timer Complementary PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary PWM.
+    (+) Stop the Complementary PWM.
+    (+) Start the Complementary PWM and enable interrupts.
+    (+) Stop the Complementary PWM and disable interrupts.
+    (+) Start the Complementary PWM and enable DMA transfers.
+    (+) Stop the Complementary PWM and disable DMA transfers.
+    (+) Start the Complementary Input Capture measurement.
+    (+) Stop the Complementary Input Capture.
+    (+) Start the Complementary Input Capture and enable interrupts.
+    (+) Stop the Complementary Input Capture and disable interrupts.
+    (+) Start the Complementary Input Capture and enable DMA transfers.
+    (+) Stop the Complementary Input Capture and disable DMA transfers.
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the TIM Break interrupt */
+    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+    /* Enable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the TIM Break interrupt (only if no more channel is active) */
+    tmpccer = htim->Instance->CCER;
+    if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE  | TIM_CCER_CC4NE)) == (uint32_t)RESET)
+    {
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    }
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the
+  *         complementary output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+  *         output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the complementary PWM output */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  * @brief    Timer Complementary One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Timer Complementary One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to enable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM  channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to enable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  /* Enable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM  channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+      (+) Configure the commutation event in case of use of the Hall sensor interface.
+      (+) Configure Output channels for OC and PWM mode.
+
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master synchronization.
+      (+) Configure timer remapping capabilities.
+      (+) Select timer input source.
+      (+) Enable or disable channel grouping.
+      (+) Configure Pulse on compare.
+      (+) Configure Encoder index.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the TIM commutation event sequence.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR4: Internal trigger 4 selected   (*)
+  *            @arg TIM_TS_ITR5: Internal trigger 5 selected
+  *            @arg TIM_TS_ITR6: Internal trigger 6 selected
+  *            @arg TIM_TS_ITR7: Internal trigger 7 selected
+  *            @arg TIM_TS_ITR8: Internal trigger 8 selected
+  *            @arg TIM_TS_ITR9: Internal trigger 9 selected   (*)
+  *            @arg TIM_TS_ITR10: Internal trigger 10 selected
+  *            @arg TIM_TS_ITR11: Internal trigger 11 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  *
+  *         (*)  Value not defined in all devices.
+  *
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+
+  __HAL_LOCK(htim);
+
+#if defined(TIM5) && defined(TIM20)
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
+      (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
+      (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR9) ||
+      (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
+#elif defined(TIM5)
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
+      (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
+      (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR11))
+#elif defined(TIM20)
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
+      (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
+      (InputTrigger == TIM_TS_ITR9)  || (InputTrigger == TIM_TS_ITR11))
+#else
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
+      (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
+      (InputTrigger == TIM_TS_ITR11))
+#endif /* TIM5 && TIM20 */
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with interrupt.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR4: Internal trigger 4 selected   (*)
+  *            @arg TIM_TS_ITR5: Internal trigger 5 selected
+  *            @arg TIM_TS_ITR6: Internal trigger 6 selected
+  *            @arg TIM_TS_ITR7: Internal trigger 7 selected
+  *            @arg TIM_TS_ITR8: Internal trigger 8 selected
+  *            @arg TIM_TS_ITR9: Internal trigger 9 selected   (*)
+  *            @arg TIM_TS_ITR10: Internal trigger 10 selected
+  *            @arg TIM_TS_ITR11: Internal trigger 11 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  *
+  *         (*)  Value not defined in all devices.
+  *
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+
+  __HAL_LOCK(htim);
+
+#if defined(TIM5) && defined(TIM20)
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
+      (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
+      (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR9) ||
+      (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
+#elif defined(TIM5)
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
+      (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
+      (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR11))
+#elif defined(TIM20)
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
+      (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
+      (InputTrigger == TIM_TS_ITR9)  || (InputTrigger == TIM_TS_ITR11))
+#else
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
+      (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
+      (InputTrigger == TIM_TS_ITR11))
+#endif /* TIM5 && TIM20 */
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  /* Enable the Commutation Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with DMA.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR4: Internal trigger 4 selected   (*)
+  *            @arg TIM_TS_ITR5: Internal trigger 5 selected
+  *            @arg TIM_TS_ITR6: Internal trigger 6 selected
+  *            @arg TIM_TS_ITR7: Internal trigger 7 selected
+  *            @arg TIM_TS_ITR8: Internal trigger 8 selected
+  *            @arg TIM_TS_ITR9: Internal trigger 9 selected   (*)
+  *            @arg TIM_TS_ITR10: Internal trigger 10 selected
+  *            @arg TIM_TS_ITR11: Internal trigger 11 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  *
+  *         (*)  Value not defined in all devices.
+  *
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+
+  __HAL_LOCK(htim);
+
+#if defined(TIM5) && defined(TIM20)
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
+      (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
+      (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR9) ||
+      (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
+#elif defined(TIM5)
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
+      (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
+      (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR11))
+#elif defined(TIM20)
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
+      (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
+      (InputTrigger == TIM_TS_ITR9)  || (InputTrigger == TIM_TS_ITR11))
+#else
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
+      (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
+      (InputTrigger == TIM_TS_ITR11))
+#endif /* TIM5 && TIM20 */
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Enable the Commutation DMA Request */
+  /* Set the DMA Commutation Callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Enable the Commutation DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in master mode.
+  * @param  htim TIM handle.
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+    /* Clear the MMS2 bits */
+    tmpcr2 &= ~TIM_CR2_MMS2;
+    /* Select the TRGO2 source*/
+    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+  }
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  htim TIM handle
+  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @note   Interrupts can be generated when an active level is detected on the
+  *         break input, the break 2 input or the system break input. Break
+  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+  uint32_t tmpbdtr = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+
+  if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
+
+    /* Set BREAK AF mode */
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
+  }
+
+  if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+    assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+    assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+
+    /* Set the BREAK2 input related BDTR bits */
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+
+    if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
+
+      /* Set BREAK2 AF mode */
+      MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
+    }
+  }
+
+  /* Set TIMx_BDTR */
+  htim->Instance->BDTR = tmpbdtr;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the break input source.
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @param  sBreakInputConfig Break input source configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+                                             uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmporx;
+  uint32_t bkin_enable_mask;
+  uint32_t bkin_polarity_mask;
+  uint32_t bkin_enable_bitpos;
+  uint32_t bkin_polarity_bitpos;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+  assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  switch (sBreakInputConfig->Source)
+  {
+    case TIM_BREAKINPUTSOURCE_BKIN:
+    {
+      bkin_enable_mask = TIM1_AF1_BKINE;
+      bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKINP;
+      bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_COMP1:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP1E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKCMP1P;
+      bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_COMP2:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP2E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKCMP2P;
+      bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_COMP3:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP3E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKCMP3P;
+      bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_COMP4:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP4E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP4E_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKCMP4P;
+      bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos;
+      break;
+    }
+#if defined (COMP5)
+    case TIM_BREAKINPUTSOURCE_COMP5:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP5E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP5E_Pos;
+      /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
+      bkin_polarity_mask = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+#endif /* COMP5 */
+#if defined (COMP6)
+    case TIM_BREAKINPUTSOURCE_COMP6:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP6E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP6E_Pos;
+      /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
+      bkin_polarity_mask = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+#endif /* COMP7 */
+#if defined (COMP7)
+    case TIM_BREAKINPUTSOURCE_COMP7:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP7E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP7E_Pos;
+      /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
+      bkin_polarity_mask = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+#endif /* COMP7 */
+
+    default:
+    {
+      bkin_enable_mask = 0U;
+      bkin_polarity_mask = 0U;
+      bkin_enable_bitpos = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+  }
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Get the TIMx_AF1 register value */
+      tmporx = htim->Instance->AF1;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+      tmporx &= ~bkin_polarity_mask;
+      tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+
+      /* Set TIMx_AF1 */
+      htim->Instance->AF1 = tmporx;
+      break;
+    }
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Get the TIMx_AF2 register value */
+      tmporx = htim->Instance->AF2;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+      tmporx &= ~bkin_polarity_mask;
+      tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+
+      /* Set TIMx_AF2 */
+      htim->Instance->AF2 = tmporx;
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Configures the TIMx Remapping input capabilities.
+  * @param  htim TIM handle.
+  * @param  Remap specifies the TIM remapping source.
+  *         For TIM1, the parameter can take one of the following values:
+  *            @arg TIM_TIM1_ETR_GPIO           TIM1 ETR is connected to GPIO
+  *            @arg TIM_TIM1_ETR_COMP1          TIM1 ETR is connected to COMP1 output
+  *            @arg TIM_TIM1_ETR_COMP2          TIM1 ETR is connected to COMP2 output
+  *            @arg TIM_TIM1_ETR_COMP3          TIM1 ETR is connected to COMP3 output
+  *            @arg TIM_TIM1_ETR_COMP4          TIM1 ETR is connected to COMP4 output
+  *            @arg TIM_TIM1_ETR_COMP5          TIM1 ETR is connected to COMP5 output    (*)
+  *            @arg TIM_TIM1_ETR_COMP6          TIM1 ETR is connected to COMP6 output    (*)
+  *            @arg TIM_TIM1_ETR_COMP7          TIM1 ETR is connected to COMP7 output    (*)
+  *            @arg TIM_TIM1_ETR_ADC1_AWD1      TIM1 ETR is connected to ADC1 AWD1
+  *            @arg TIM_TIM1_ETR_ADC1_AWD2      TIM1 ETR is connected to ADC1 AWD2
+  *            @arg TIM_TIM1_ETR_ADC1_AWD3      TIM1 ETR is connected to ADC1 AWD3
+  *            @arg TIM_TIM1_ETR_ADC4_AWD1      TIM1 ETR is connected to ADC4 AWD1       (*)
+  *            @arg TIM_TIM1_ETR_ADC4_AWD2      TIM1 ETR is connected to ADC4 AWD2       (*)
+  *            @arg TIM_TIM1_ETR_ADC4_AWD3      TIM1 ETR is connected to ADC4 AWD3       (*)
+  *
+  *         For TIM2, the parameter can take one of the following values:
+  *            @arg TIM_TIM2_ETR_GPIO           TIM2 ETR is connected to GPIO
+  *            @arg TIM_TIM2_ETR_COMP1          TIM2 ETR is connected to COMP1 output
+  *            @arg TIM_TIM2_ETR_COMP2          TIM2 ETR is connected to COMP2 output
+  *            @arg TIM_TIM2_ETR_COMP3          TIM2 ETR is connected to COMP3 output
+  *            @arg TIM_TIM2_ETR_COMP4          TIM2 ETR is connected to COMP4 output
+  *            @arg TIM_TIM2_ETR_COMP5          TIM2 ETR is connected to COMP5 output    (*)
+  *            @arg TIM_TIM2_ETR_COMP6          TIM2 ETR is connected to COMP6 output    (*)
+  *            @arg TIM_TIM2_ETR_COMP7          TIM2 ETR is connected to COMP7 output    (*)
+  *            @arg TIM_TIM2_ETR_TIM3_ETR       TIM2 ETR is connected to TIM3 ETR pin
+  *            @arg TIM_TIM2_ETR_TIM4_ETR       TIM2 ETR is connected to TIM4 ETR pin
+  *            @arg TIM_TIM2_ETR_TIM5_ETR       TIM2 ETR is connected to TIM5 ETR pin    (*)
+  *            @arg TIM_TIM2_ETR_LSE
+  *
+  *         For TIM3, the parameter can take one of the following values:
+  *            @arg TIM_TIM3_ETR_GPIO           TIM3 ETR is connected to GPIO
+  *            @arg TIM_TIM3_ETR_COMP1          TIM3 ETR is connected to COMP1 output
+  *            @arg TIM_TIM3_ETR_COMP2          TIM3 ETR is connected to COMP2 output
+  *            @arg TIM_TIM3_ETR_COMP3          TIM3 ETR is connected to COMP3 output
+  *            @arg TIM_TIM3_ETR_COMP4          TIM3 ETR is connected to COMP4 output
+  *            @arg TIM_TIM3_ETR_COMP5          TIM3 ETR is connected to COMP5 output    (*)
+  *            @arg TIM_TIM3_ETR_COMP6          TIM3 ETR is connected to COMP6 output    (*)
+  *            @arg TIM_TIM3_ETR_COMP7          TIM3 ETR is connected to COMP7 output    (*)
+  *            @arg TIM_TIM3_ETR_TIM2_ETR       TIM3 ETR is connected to TIM2 ETR pin
+  *            @arg TIM_TIM3_ETR_TIM4_ETR       TIM3 ETR is connected to TIM4 ETR pin
+  *            @arg TIM_TIM3_ETR_ADC2_AWD1      TIM3 ETR is connected to ADC2 AWD1
+  *            @arg TIM_TIM3_ETR_ADC2_AWD2      TIM3 ETR is connected to ADC2 AWD2
+  *            @arg TIM_TIM3_ETR_ADC2_AWD3      TIM3 ETR is connected to ADC2 AWD3
+  *
+  *         For TIM4, the parameter can take one of the following values:
+  *            @arg TIM_TIM4_ETR_GPIO           TIM4 ETR is connected to GPIO
+  *            @arg TIM_TIM4_ETR_COMP1          TIM4 ETR is connected to COMP1 output
+  *            @arg TIM_TIM4_ETR_COMP2          TIM4 ETR is connected to COMP2 output
+  *            @arg TIM_TIM4_ETR_COMP3          TIM4 ETR is connected to COMP3 output
+  *            @arg TIM_TIM4_ETR_COMP4          TIM4 ETR is connected to COMP4 output
+  *            @arg TIM_TIM4_ETR_COMP5          TIM4 ETR is connected to COMP5 output    (*)
+  *            @arg TIM_TIM4_ETR_COMP6          TIM4 ETR is connected to COMP6 output    (*)
+  *            @arg TIM_TIM4_ETR_COMP7          TIM4 ETR is connected to COMP7 output    (*)
+  *            @arg TIM_TIM4_ETR_TIM3_ETR       TIM4 ETR is connected to TIM3 ETR pin
+  *            @arg TIM_TIM4_ETR_TIM5_ETR       TIM4 ETR is connected to TIM5 ETR pin    (*)
+  *
+  *         For TIM5, the parameter can take one of the following values:       (**)
+  *            @arg TIM_TIM5_ETR_GPIO           TIM5 ETR is connected to GPIO            (*)
+  *            @arg TIM_TIM5_ETR_COMP1          TIM5 ETR is connected to COMP1 output    (*)
+  *            @arg TIM_TIM5_ETR_COMP2          TIM5 ETR is connected to COMP2 output    (*)
+  *            @arg TIM_TIM5_ETR_COMP3          TIM5 ETR is connected to COMP3 output    (*)
+  *            @arg TIM_TIM5_ETR_COMP4          TIM5 ETR is connected to COMP4 output    (*)
+  *            @arg TIM_TIM5_ETR_COMP5          TIM5 ETR is connected to COMP5 output    (*)
+  *            @arg TIM_TIM5_ETR_COMP6          TIM5 ETR is connected to COMP6 output    (*)
+  *            @arg TIM_TIM5_ETR_COMP7          TIM5 ETR is connected to COMP7 output    (*)
+  *            @arg TIM_TIM5_ETR_TIM2_ETR       TIM5 ETR is connected to TIM2 ETR pin    (*)
+  *            @arg TIM_TIM5_ETR_TIM3_ETR       TIM5 ETR is connected to TIM3 ETR pin    (*)
+  *
+  *         For TIM8, the parameter can take one of the following values:
+  *            @arg TIM_TIM8_ETR_GPIO            TIM8 ETR is connected to GPIO
+  *            @arg TIM_TIM8_ETR_COMP1           TIM8 ETR is connected to COMP1 output
+  *            @arg TIM_TIM8_ETR_COMP2           TIM8 ETR is connected to COMP2 output
+  *            @arg TIM_TIM8_ETR_COMP3           TIM8 ETR is connected to COMP3 output
+  *            @arg TIM_TIM8_ETR_COMP4           TIM8 ETR is connected to COMP4 output
+  *            @arg TIM_TIM8_ETR_COMP5           TIM8 ETR is connected to COMP5 output    (*)
+  *            @arg TIM_TIM8_ETR_COMP6           TIM8 ETR is connected to COMP6 output    (*)
+  *            @arg TIM_TIM8_ETR_COMP7           TIM8 ETR is connected to COMP7 output    (*)
+  *            @arg TIM_TIM8_ETR_ADC2_AWD1       TIM8 ETR is connected to ADC2 AWD1
+  *            @arg TIM_TIM8_ETR_ADC2_AWD2       TIM8 ETR is connected to ADC2 AWD2
+  *            @arg TIM_TIM8_ETR_ADC2_AWD3       TIM8 ETR is connected to ADC2 AWD3
+  *            @arg TIM_TIM8_ETR_ADC3_AWD1       TIM8 ETR is connected to ADC3 AWD1       (*)
+  *            @arg TIM_TIM8_ETR_ADC3_AWD2       TIM8 ETR is connected to ADC3 AWD2       (*)
+  *            @arg TIM_TIM8_ETR_ADC3_AWD3       TIM8 ETR is connected to ADC3 AWD3       (*)
+  *
+  *         For TIM20, the parameter can take one of the following values:       (**)
+  *            @arg TIM_TIM20_ETR_GPIO            TIM20 ETR is connected to GPIO
+  *            @arg TIM_TIM20_ETR_COMP1           TIM20 ETR is connected to COMP1 output  (*)
+  *            @arg TIM_TIM20_ETR_COMP2           TIM20 ETR is connected to COMP2 output  (*)
+  *            @arg TIM_TIM20_ETR_COMP3           TIM20 ETR is connected to COMP3 output  (*)
+  *            @arg TIM_TIM20_ETR_COMP4           TIM20 ETR is connected to COMP4 output  (*)
+  *            @arg TIM_TIM20_ETR_COMP5           TIM20 ETR is connected to COMP5 output  (*)
+  *            @arg TIM_TIM20_ETR_COMP6           TIM20 ETR is connected to COMP6 output  (*)
+  *            @arg TIM_TIM20_ETR_COMP7           TIM20 ETR is connected to COMP7 output  (*)
+  *            @arg TIM_TIM20_ETR_ADC3_AWD1       TIM20 ETR is connected to ADC3 AWD1     (*)
+  *            @arg TIM_TIM20_ETR_ADC3_AWD2       TIM20 ETR is connected to ADC3 AWD2     (*)
+  *            @arg TIM_TIM20_ETR_ADC3_AWD3       TIM20 ETR is connected to ADC3 AWD3     (*)
+  *            @arg TIM_TIM20_ETR_ADC5_AWD1       TIM20 ETR is connected to ADC5 AWD1     (*)
+  *            @arg TIM_TIM20_ETR_ADC5_AWD2       TIM20 ETR is connected to ADC5 AWD2     (*)
+  *            @arg TIM_TIM20_ETR_ADC5_AWD3       TIM20 ETR is connected to ADC5 AWD3     (*)
+  *
+  *         (*)  Value not defined in all devices. \n
+  *         (**) Register not available in all devices.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_REMAP(Remap));
+
+  __HAL_LOCK(htim);
+
+  MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Select the timer input source
+  * @param  htim TIM handle.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TI1 input channel
+  *            @arg TIM_CHANNEL_2: TI2 input channel
+  *            @arg TIM_CHANNEL_3: TI3 input channel
+  *            @arg TIM_CHANNEL_4: TI4 input channel
+  * @param  TISelection specifies the timer input source
+  *         For TIM1 this parameter can be one of the following values:
+  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
+  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
+  *            @arg TIM_TIM1_TI1_COMP2:               TIM1 TI1 is connected to COMP2 output
+  *            @arg TIM_TIM1_TI1_COMP3:               TIM1 TI1 is connected to COMP3 output
+  *            @arg TIM_TIM1_TI1_COMP4:               TIM1 TI1 is connected to COMP4 output
+  *
+  *         For TIM2 this parameter can be one of the following values:
+  *            @arg TIM_TIM2_TI1_GPIO:                TIM2 TI1 is connected to GPIO
+  *            @arg TIM_TIM2_TI1_COMP1:               TIM2 TI1 is connected to COMP1 output
+  *            @arg TIM_TIM2_TI1_COMP2:               TIM2 TI1 is connected to COMP2 output
+  *            @arg TIM_TIM2_TI1_COMP3:               TIM2 TI1 is connected to COMP3 output
+  *            @arg TIM_TIM2_TI1_COMP4:               TIM2 TI1 is connected to COMP4 output
+  *            @arg TIM_TIM2_TI1_COMP5:               TIM2 TI1 is connected to COMP5 output     (*)
+  *
+  *            @arg TIM_TIM2_TI2_GPIO:                TIM1 TI2 is connected to GPIO
+  *            @arg TIM_TIM2_TI2_COMP1:               TIM2 TI2 is connected to COMP1 output
+  *            @arg TIM_TIM2_TI2_COMP2:               TIM2 TI2 is connected to COMP2 output
+  *            @arg TIM_TIM2_TI2_COMP3:               TIM2 TI2 is connected to COMP3 output
+  *            @arg TIM_TIM2_TI2_COMP4:               TIM2 TI2 is connected to COMP4 output
+  *            @arg TIM_TIM2_TI2_COMP6:               TIM2 TI2 is connected to COMP6 output     (*)
+  *
+  *            @arg TIM_TIM2_TI3_GPIO:                TIM2 TI3 is connected to GPIO
+  *            @arg TIM_TIM2_TI3_COMP4:               TIM2 TI3 is connected to COMP4 output
+  *
+  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
+  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
+  *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
+  *
+  *         For TIM3 this parameter can be one of the following values:
+  *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
+  *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
+  *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
+  *            @arg TIM_TIM3_TI1_COMP3:               TIM3 TI1 is connected to COMP3 output
+  *            @arg TIM_TIM3_TI1_COMP4:               TIM3 TI1 is connected to COMP4 output
+  *            @arg TIM_TIM3_TI1_COMP5:               TIM3 TI1 is connected to COMP5 output     (*)
+  *            @arg TIM_TIM3_TI1_COMP6:               TIM3 TI1 is connected to COMP6 output     (*)
+  *            @arg TIM_TIM3_TI1_COMP7:               TIM3 TI1 is connected to COMP7 output     (*)
+  *
+  *            @arg TIM_TIM3_TI2_GPIO:                TIM3 TI2 is connected to GPIO
+  *            @arg TIM_TIM3_TI2_COMP1:               TIM3 TI2 is connected to COMP1 output
+  *            @arg TIM_TIM3_TI2_COMP2:               TIM3 TI2 is connected to COMP2 output
+  *            @arg TIM_TIM3_TI2_COMP3:               TIM3 TI2 is connected to COMP3 output
+  *            @arg TIM_TIM3_TI2_COMP4:               TIM3 TI2 is connected to COMP4 output
+  *            @arg TIM_TIM3_TI2_COMP5:               TIM3 TI2 is connected to COMP5 output     (*)
+  *            @arg TIM_TIM3_TI2_COMP6:               TIM3 TI2 is connected to COMP6 output     (*)
+  *            @arg TIM_TIM3_TI2_COMP7:               TIM3 TI2 is connected to COMP7 output     (*)
+  *
+  *            @arg TIM_TIM3_TI3_GPIO:                TIM3 TI3 is connected to GPIO
+  *            @arg TIM_TIM3_TI3_COMP3:               TIM3 TI3 is connected to COMP3 output
+
+  *         For TIM4 this parameter can be one of the following values:
+  *            @arg TIM_TIM4_TI1_GPIO:                TIM4 TI1 is connected to GPIO
+  *            @arg TIM_TIM4_TI1_COMP1:               TIM4 TI1 is connected to COMP1 output
+  *            @arg TIM_TIM4_TI1_COMP2:               TIM4 TI1 is connected to COMP2 output
+  *            @arg TIM_TIM4_TI1_COMP3:               TIM4 TI1 is connected to COMP3 output
+  *            @arg TIM_TIM4_TI1_COMP4:               TIM4 TI1 is connected to COMP4 output
+  *            @arg TIM_TIM4_TI1_COMP5:               TIM4 TI1 is connected to COMP5 output     (*)
+  *            @arg TIM_TIM4_TI1_COMP6:               TIM4 TI1 is connected to COMP6 output     (*)
+  *            @arg TIM_TIM4_TI1_COMP7:               TIM4 TI1 is connected to COMP7 output     (*)
+  *
+  *            @arg TIM_TIM4_TI2_GPIO:                TIM4 TI2 is connected to GPIO
+  *            @arg TIM_TIM4_TI2_COMP1:               TIM4 TI2 is connected to COMP1 output
+  *            @arg TIM_TIM4_TI2_COMP2:               TIM4 TI2 is connected to COMP2 output
+  *            @arg TIM_TIM4_TI2_COMP3:               TIM4 TI2 is connected to COMP3 output
+  *            @arg TIM_TIM4_TI2_COMP4:               TIM4 TI2 is connected to COMP4 output
+  *            @arg TIM_TIM4_TI2_COMP5:               TIM4 TI2 is connected to COMP5 output     (*)
+  *            @arg TIM_TIM4_TI2_COMP6:               TIM4 TI2 is connected to COMP6 output     (*)
+  *            @arg TIM_TIM4_TI2_COMP7:               TIM4 TI2 is connected to COMP7 output     (*)
+  *
+  *            @arg TIM_TIM4_TI3_GPIO:                TIM4 TI3 is connected to GPIO
+  *            @arg TIM_TIM4_TI3_COMP5:               TIM4 TI3 is connected to COMP5 output     (*)
+  *
+  *            @arg TIM_TIM4_TI4_GPIO:                TIM4 TI4 is connected to GPIO
+  *            @arg TIM_TIM4_TI4_COMP6:               TIM4 TI4 is connected to COMP6 output     (*)
+  *
+  *         For TIM5 this parameter can be one of the following values:    (**)
+  *            @arg TIM_TIM5_TI1_GPIO:                TIM5 TI1 is connected to GPIO
+  *            @arg TIM_TIM5_TI1_LSI:                 TIM5 TI1 is connected to LSI clock        (*)
+  *            @arg TIM_TIM5_TI1_LSE:                 TIM5 TI1 is connected to LSE clock        (*)
+  *            @arg TIM_TIM5_TI1_RTC_WK:              TIM5 TI1 is connected to RTC Wakeup       (*)
+  *            @arg TIM_TIM5_TI1_COMP1:               TIM5 TI1 is connected to COMP1 output     (*)
+  *            @arg TIM_TIM5_TI1_COMP2:               TIM5 TI1 is connected to COMP2 output     (*)
+  *            @arg TIM_TIM5_TI1_COMP3:               TIM5 TI1 is connected to COMP3 output     (*)
+  *            @arg TIM_TIM5_TI1_COMP4:               TIM5 TI1 is connected to COMP4 output     (*)
+  *            @arg TIM_TIM5_TI1_COMP5:               TIM5 TI1 is connected to COMP5 output     (*)
+  *            @arg TIM_TIM5_TI1_COMP6:               TIM5 TI1 is connected to COMP6 output     (*)
+  *            @arg TIM_TIM5_TI1_COMP7:               TIM5 TI1 is connected to COMP7 output     (*)
+  *
+  *            @arg TIM_TIM5_TI2_GPIO:                TIM5 TI2 is connected to GPIO
+  *            @arg TIM_TIM5_TI2_COMP1:               TIM5 TI2 is connected to COMP1 output
+  *            @arg TIM_TIM5_TI2_COMP2:               TIM5 TI2 is connected to COMP2 output
+  *            @arg TIM_TIM5_TI2_COMP3:               TIM5 TI2 is connected to COMP3 output
+  *            @arg TIM_TIM5_TI2_COMP4:               TIM5 TI2 is connected to COMP4 output
+  *            @arg TIM_TIM5_TI2_COMP5:               TIM5 TI2 is connected to COMP5 output     (*)
+  *            @arg TIM_TIM5_TI2_COMP6:               TIM5 TI2 is connected to COMP6 output     (*)
+  *            @arg TIM_TIM5_TI2_COMP7:               TIM5 TI2 is connected to COMP7 output     (*)
+  *
+  *         For TIM8 this parameter can be one of the following values:
+  *            @arg TIM_TIM8_TI1_GPIO:                TIM8 TI1 is connected to GPIO
+  *            @arg TIM_TIM8_TI1_COMP1:               TIM8 TI1 is connected to COMP1 output
+  *            @arg TIM_TIM8_TI1_COMP2:               TIM8 TI1 is connected to COMP2 output
+  *            @arg TIM_TIM8_TI1_COMP3:               TIM8 TI1 is connected to COMP3 output
+  *            @arg TIM_TIM8_TI1_COMP4:               TIM8 TI1 is connected to COMP4 output
+  *
+  *         For TIM15 this parameter can be one of the following values:
+  *            @arg TIM_TIM15_TI1_GPIO:                TIM15 TI1 is connected to GPIO
+  *            @arg TIM_TIM15_TI1_LSE:                 TIM15 TI1 is connected to LSE clock
+  *            @arg TIM_TIM15_TI1_COMP1:               TIM15 TI1 is connected to COMP1 output
+  *            @arg TIM_TIM15_TI1_COMP2:               TIM15 TI1 is connected to COMP2 output
+  *            @arg TIM_TIM15_TI1_COMP5:               TIM15 TI1 is connected to COMP5 output     (*)
+  *            @arg TIM_TIM15_TI1_COMP7:               TIM15 TI1 is connected to COMP7 output     (*)
+  *
+  *            @arg TIM_TIM15_TI2_GPIO:                TIM15 TI2 is connected to GPIO
+  *            @arg TIM_TIM15_TI2_COMP2:               TIM15 TI2 is connected to COMP2 output
+  *            @arg TIM_TIM15_TI2_COMP3:               TIM15 TI2 is connected to COMP3 output
+  *            @arg TIM_TIM15_TI2_COMP6:               TIM15 TI2 is connected to COMP6 output     (*)
+  *            @arg TIM_TIM15_TI2_COMP7:               TIM15 TI2 is connected to COMP7 output     (*)
+  *
+  *         For TIM16 this parameter can be one of the following values:
+  *            @arg TIM_TIM16_TI1_GPIO:                TIM16 TI1 is connected to GPIO
+  *            @arg TIM_TIM16_TI1_COMP6:               TIM16 TI1 is connected to COMP6 output     (*)
+  *            @arg TIM_TIM16_TI1_MCO:                 TIM15 TI1 is connected to MCO output
+  *            @arg TIM_TIM16_TI1_HSE_32:              TIM15 TI1 is connected to HSE div 32
+  *            @arg TIM_TIM16_TI1_RTC_WK:              TIM15 TI1 is connected to RTC wakeup
+  *            @arg TIM_TIM16_TI1_LSE:                 TIM15 TI1 is connected to LSE clock
+  *            @arg TIM_TIM16_TI1_LSI:                 TIM15 TI1 is connected to LSI clock
+  *
+  *         For TIM17 this parameter can be one of the following values:
+  *            @arg TIM_TIM17_TI1_GPIO:                TIM17 TI1 is connected to GPIO
+  *            @arg TIM_TIM17_TI1_COMP5:               TIM17 TI1 is connected to COMP5 output     (*)
+  *            @arg TIM_TIM17_TI1_MCO:                 TIM17 TI1 is connected to MCO output
+  *            @arg TIM_TIM17_TI1_HSE_32:              TIM17 TI1 is connected to HSE div 32
+  *            @arg TIM_TIM17_TI1_RTC_WK:              TIM17 TI1 is connected to RTC wakeup
+  *            @arg TIM_TIM17_TI1_LSE:                 TIM17 TI1 is connected to LSE clock
+  *            @arg TIM_TIM17_TI1_LSI:                 TIM17 TI1 is connected to LSI clock
+
+  *         For TIM20 this parameter can be one of the following values:    (**)
+  *            @arg TIM_TIM20_TI1_GPIO:                TIM20 TI1 is connected to GPIO
+  *            @arg TIM_TIM20_TI1_COMP1:               TIM20 TI1 is connected to COMP1 output     (*)
+  *            @arg TIM_TIM20_TI1_COMP2:               TIM20 TI1 is connected to COMP2 output     (*)
+  *            @arg TIM_TIM20_TI1_COMP3:               TIM20 TI1 is connected to COMP3 output     (*)
+  *            @arg TIM_TIM20_TI1_COMP4:               TIM20 TI1 is connected to COMP4 output     (*)
+  *
+  *         (*)  Value not defined in all devices. \n
+  *         (**) Register not available in all devices.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_TIM_TISEL_TIX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_TISEL(TISelection));
+
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
+
+      /* If required, set OR bit to request HSE/32 clock */
+      if (IS_TIM_HSE32_INSTANCE(htim->Instance))
+      {
+        SET_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
+      }
+      else
+      {
+        CLEAR_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
+      }
+      break;
+    case TIM_CHANNEL_2:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
+      break;
+    case TIM_CHANNEL_3:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
+      break;
+    case TIM_CHANNEL_4:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
+      break;
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Group channel 5 and channel 1, 2 or 3
+  * @param  htim TIM handle.
+  * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
+  *         This parameter can be any combination of the following values:
+  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_GROUPCH5(Channels));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Clear GC5Cx bit fields */
+  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+
+  /* Set GC5Cx bit fields */
+  htim->Instance->CCR5 |= Channels;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disarm the designated break input (when it operates in bidirectional mode).
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to disarm
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @note  The break input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output .
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpbdtr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Check initial conditions */
+      tmpbdtr = READ_REG(htim->Instance->BDTR);
+      if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
+          (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+      {
+        /* Break input BRK is disarmed */
+        SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
+      }
+      break;
+    }
+
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Check initial conditions */
+      tmpbdtr = READ_REG(htim->Instance->BDTR);
+      if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
+          (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+      {
+        /* Break input BRK is disarmed */
+        SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Arm the designated break input (when it operates in bidirectional mode).
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to arm
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @note  Arming is possible at anytime, even if fault is present.
+  * @note  Break input is automatically armed as soon as MOE bit is set.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Check initial conditions */
+      if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
+      {
+        /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+        /* Init tickstart for timeout management */
+        tickstart = HAL_GetTick();
+        while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+        {
+          if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+          {
+            /* New check to avoid false timeout detection in case of preemption */
+            if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+            {
+              return HAL_TIMEOUT;
+            }
+          }
+        }
+      }
+      break;
+    }
+
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Check initial conditions */
+      if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
+      {
+        /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+        /* Init tickstart for timeout management */
+        tickstart = HAL_GetTick();
+        while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+        {
+          if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+          {
+            /* New check to avoid false timeout detection in case of preemption */
+            if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+            {
+              return HAL_TIMEOUT;
+            }
+          }
+        }
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Enable dithering
+  * @param  htim TIM handle
+  * @note   Main usage is PWM mode
+  * @note   This function must be called when timer is stopped or disabled (CEN =0)
+  * @note   If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
+  *           - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
+  *           - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
+  *           - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
+  *           - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers
+  *             (corresponds to 4094 for the integer part and 15 for the dithered part).
+  * @note   Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER()  __HAL_TIM_CALC_PULSE_DITHER()
+  *         can be used to calculate period (ARR) and delay (CCRx) value.
+  * @note   Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
+  * @note   Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
+  *         So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
+  *         __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable dithering
+  * @param  htim TIM handle
+  * @note   This function must be called when timer is stopped or disabled (CEN =0)
+  * @note   If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
+  *           - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
+  *           - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
+  *           - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
+  *           - ARR and CCRx values are limited to 0xFFEF in dithering mode
+  *             (corresponds to 4094 for the integer part and 15 for the dithered part).
+  * @note   Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
+  *         So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
+  *         __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the pulse on compare pulse width and pulse prescaler
+  * @param  htim TIM Output Compare handle
+  * @param  PulseWidthPrescaler  Pulse width prescaler
+  *         This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7
+  * @param  PulseWidth  Pulse width
+  *         This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim,
+                                                    uint32_t PulseWidthPrescaler,
+                                                    uint32_t PulseWidth)
+{
+  uint32_t tmpecr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
+  assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx ECR register value */
+  tmpecr = htim->Instance->ECR;
+  /* Reset the Pulse width prescaler and the Pulse width */
+  tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
+  /* Set the Pulse width prescaler and Pulse width*/
+  tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
+  tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
+  /* Write to TIMx ECR */
+  htim->Instance->ECR = tmpecr;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
+  * @param  htim TIM handle
+  * @param  Source Source of slave mode selection preload
+  *         This parameter can be one of the following values:
+  *            @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload
+  *            @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
+
+  MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable deadtime preload
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable deadtime preload
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure deadtime
+  * @param  htim TIM handle
+  * @param  Deadtime Deadtime value
+  * @note   This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DEADTIME(Deadtime));
+
+  MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure asymmetrical deadtime
+  * @param  htim TIM handle
+  * @param  FallingDeadtime Falling edge deadtime value
+  * @note   This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DEADTIME(FallingDeadtime));
+
+  MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable asymmetrical deadtime
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable asymmetrical deadtime
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the encoder index.
+  * @note   warning in case of encoder mode clock plus direction
+  *                    @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
+  *         Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN
+  * @param  htim TIM handle.
+  * @param  sEncoderIndexConfig Encoder index configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
+                                               TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
+  assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
+  assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
+  assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
+  assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
+  assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Configures the TIMx External Trigger (ETR) which is used as Index input */
+  TIM_ETR_SetConfig(htim->Instance,
+                    sEncoderIndexConfig->Prescaler,
+                    sEncoderIndexConfig->Polarity,
+                    sEncoderIndexConfig->Filter);
+
+  /* Configures the encoder index */
+  MODIFY_REG(htim->Instance->ECR,
+             TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
+             (sEncoderIndexConfig->Direction |
+              ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
+              sEncoderIndexConfig->Position |
+              TIM_ECR_IE));
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable encoder index
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable encoder index
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable encoder first index
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable encoder first index
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Extended Callbacks functions #####
+  ==============================================================================
+  [..]
+    This section provides Extended TIM callback functions:
+    (+) Timer Commutation callback
+    (+) Timer Break callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Hall commutation changed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Hall commutation changed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break2 detection callback in non blocking mode
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_Break2Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Encoder index callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Direction change callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Index error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transition error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Extended Peripheral State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Hall Sensor interface handle state.
+  * @param  htim TIM Hall Sensor handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return actual state of the TIM complementary channel.
+  * @param  htim TIM handle
+  * @param  ChannelN TIM Complementary channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @retval TIM Complementary channel state
+  */
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN)
+{
+  HAL_TIM_ChannelStateTypeDef channel_state;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+
+  channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+
+  return channel_state;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA Commutation callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationCallback(htim);
+#else
+  HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Commutation half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationHalfCpltCallback(htim);
+#else
+  HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback (complementary channel).
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA error callback (complementary channel)
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+  * @retval None
+  */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+  uint32_t tmp;
+
+  tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &=  ~tmp;
+
+  /* Set or reset the CCxNE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c
new file mode 100644
index 0000000..3a2509f
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c
@@ -0,0 +1,4613 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_uart.c
+  * @author  MCD Application Team
+  * @brief   UART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+    The UART HAL driver can be used as follows:
+
+    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+        (++) Enable the USARTx interface clock.
+        (++) UART pins configuration:
+            (+++) Enable the clock for the UART GPIOs.
+            (+++) Configure these UART pins as alternate function pull-up.
+        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+             and HAL_UART_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (++) UART interrupts handling:
+              -@@-  The specific UART interrupts (Transmission complete interrupt,
+                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
+                inside the transmit and receive processes.
+        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+             and HAL_UART_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                  interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
+        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+        in the huart handle AdvancedInit structure.
+
+    (#) For the UART asynchronous mode, initialize the UART registers by calling
+        the HAL_UART_Init() API.
+
+    (#) For the UART Half duplex mode, initialize the UART registers by calling
+        the HAL_HalfDuplex_Init() API.
+
+    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+        by calling the HAL_LIN_Init() API.
+
+    (#) For the UART Multiprocessor mode, initialize the UART registers
+        by calling the HAL_MultiProcessor_Init() API.
+
+    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    [..]
+    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
+        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+        calling the customized HAL_UART_MspInit() API.
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function HAL_UART_RegisterCallback() to register a user callback.
+    Function HAL_UART_RegisterCallback() allows to register following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) WakeupCallback            : Wakeup Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) WakeupCallback            : Wakeup Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+
+    [..]
+    For specific callback RxEventCallback, use dedicated registration/reset functions:
+    respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
+
+    [..]
+    By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+    all callbacks are set to the corresponding weak (surcharged) functions:
+    examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
+    and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
+    or HAL_UART_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak (surcharged) callbacks are used.
+
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UART UART
+  * @brief HAL UART module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+  * @{
+  */
+#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
+                                      USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+
+#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
+                                      USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+
+#define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */
+#define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */
+
+#define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */
+#define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+  * @{
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup UART_Private_variables
+  * @{
+  */
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+/**
+  * @}
+  */
+
+/* Exported Constants --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+    and UART multiprocessor mode configuration procedures (details for the procedures
+    are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible UART formats are listed in the
+  following table.
+
+  Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+  {
+    /* Check the parameters */
+    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In asynchronous mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Initialize the half-duplex mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check UART instance */
+  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In half-duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the LIN mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart             UART handle.
+  * @param BreakDetectLength Specifies the LIN break detection length.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the LIN UART instance */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+  /* Check the Break detection length parameter */
+  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+  /* LIN mode limited to 16-bit oversampling only */
+  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    return HAL_ERROR;
+  }
+  /* LIN mode limited to 8-bit data length */
+  if (huart->Init.WordLength != UART_WORDLENGTH_8B)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In LIN mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+  /* Set the USART LIN Break detection length. */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the multiprocessor mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart        UART handle.
+  * @param Address      UART node address (4-, 6-, 7- or 8-bit long).
+  * @param WakeUpMethod Specifies the UART wakeup method.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+  * @note  If the user resorts to idle line detection wake up, the Address parameter
+  *        is useless and ignored by the initialization function.
+  * @note  If the user resorts to address mark wake up, the address length detection
+  *        is configured by default to 4 bits only. For the UART to be able to
+  *        manage 6-, 7- or 8-bit long addresses detection, the API
+  *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
+  *        HAL_MultiProcessor_Init().
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the wake up method parameter */
+  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In multiprocessor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+  {
+    /* If address mark wake up method is chosen, set the USART address node */
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+  }
+
+  /* Set the wake up method by setting the WAKE bit in the CR1 register */
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief DeInitialize the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  huart->Instance->CR1 = 0x0U;
+  huart->Instance->CR2 = 0x0U;
+  huart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  if (huart->MspDeInitCallback == NULL)
+  {
+    huart->MspDeInitCallback = HAL_UART_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  huart->MspDeInitCallback(huart);
+#else
+  /* DeInit the low level hardware */
+  HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_RESET;
+  huart->RxState = HAL_UART_STATE_RESET;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the UART MSP.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the UART MSP.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User UART Callback
+  *         To be used instead of the weak predefined callback
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_WAKEUP_CB_ID :
+        huart->WakeupCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_FIFO_FULL_CB_ID :
+        huart->RxFifoFullCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+        huart->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an UART Callback
+  *         UART callaback is redirected to the weak predefined callback
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  __HAL_LOCK(huart);
+
+  if (HAL_UART_STATE_READY == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback    */
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback         */
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback     */
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback         */
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback          */
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback      */
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
+                                                                                  AbortTransmitCpltCallback          */
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak
+                                                                                  AbortReceiveCpltCallback           */
+        break;
+
+      case HAL_UART_WAKEUP_CB_ID :
+        huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback         */
+        break;
+
+      case HAL_UART_RX_FIFO_FULL_CB_ID :
+        huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback     */
+        break;
+
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+        huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback    */
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback        */
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback      */
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_UART_STATE_RESET == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  Register a User UART Rx Event Callback
+  *         To be used instead of the weak predefined callback
+  * @param  huart     Uart handle
+  * @param  pCallback Pointer to the Rx Event Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    huart->RxEventCallback = pCallback;
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the UART Rx Event Callback
+  *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
+  * @param  huart     Uart handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+  return status;
+}
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+  * @brief UART Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the UART asynchronous
+    and Half duplex data transfers.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The communication is performed in polling mode.
+           The HAL status of all data processing is returned by the same function
+           after finishing transfer.
+       (+) Non-Blocking mode: The communication is performed using Interrupts
+           or DMA, These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) Blocking mode API's are :
+        (+) HAL_UART_Transmit()
+        (+) HAL_UART_Receive()
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (+) HAL_UART_Transmit_IT()
+        (+) HAL_UART_Receive_IT()
+        (+) HAL_UART_IRQHandler()
+
+    (#) Non-Blocking mode API's with DMA are :
+        (+) HAL_UART_Transmit_DMA()
+        (+) HAL_UART_Receive_DMA()
+        (+) HAL_UART_DMAPause()
+        (+) HAL_UART_DMAResume()
+        (+) HAL_UART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (+) HAL_UART_TxHalfCpltCallback()
+        (+) HAL_UART_TxCpltCallback()
+        (+) HAL_UART_RxHalfCpltCallback()
+        (+) HAL_UART_RxCpltCallback()
+        (+) HAL_UART_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_UART_Abort()
+        (+) HAL_UART_AbortTransmit()
+        (+) HAL_UART_AbortReceive()
+        (+) HAL_UART_Abort_IT()
+        (+) HAL_UART_AbortTransmit_IT()
+        (+) HAL_UART_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_UART_AbortCpltCallback()
+        (+) HAL_UART_AbortTransmitCpltCallback()
+        (+) HAL_UART_AbortReceiveCpltCallback()
+
+    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
+        reception services:
+        (+) HAL_UARTEx_RxEventCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+           in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+           to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+           Transfer is kept ongoing on UART side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
+           user callback is executed.
+
+    -@- In the Half duplex communication, it is forbidden to run the transmit
+        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Send an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+  *       data to the TXFIFO. Write operations to the TDR register are performed
+  *       when TXFNF flag is set. From hardware perspective, TXFNF flag and
+  *       TXE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (u8 or u16 data elements).
+  * @param Size    Amount of data elements (u8 or u16) to be sent.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  const uint8_t  *pdata8bits;
+  const uint16_t *pdata16bits;
+  uint32_t tickstart;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (const uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    __HAL_UNLOCK(huart);
+
+    while (huart->TxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+        pdata16bits++;
+      }
+      else
+      {
+        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+        pdata8bits++;
+      }
+      huart->TxXferCount--;
+    }
+
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+  *       is not empty. Read operations from the RDR register are performed when
+  *       RXFNE flag is set. From hardware perspective, RXFNE flag and
+  *       RXNE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (u8 or u16 data elements).
+  * @param Size    Amount of data elements (u8 or u16) to be received.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint16_t uhMask;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+    uhMask = huart->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    __HAL_UNLOCK(huart);
+
+    /* as long as data have to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+        pdata16bits++;
+      }
+      else
+      {
+        *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+        pdata8bits++;
+      }
+      huart->RxXferCount--;
+    }
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in interrupt mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->pTxBuffPtr  = pData;
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+    huart->TxISR       = NULL;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Configure Tx interrupt processing */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->TxISR = UART_TxISR_16BIT_FIFOEN;
+      }
+      else
+      {
+        huart->TxISR = UART_TxISR_8BIT_FIFOEN;
+      }
+
+      __HAL_UNLOCK(huart);
+
+      /* Enable the TX FIFO threshold interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+    }
+    else
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->TxISR = UART_TxISR_16BIT;
+      }
+      else
+      {
+        huart->TxISR = UART_TxISR_8BIT;
+      }
+
+      __HAL_UNLOCK(huart);
+
+      /* Enable the Transmit Data Register Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    if (!(IS_LPUART_INSTANCE(huart->Instance)))
+    {
+      /* Check that USART RTOEN bit is set */
+      if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+      {
+        /* Enable the UART Receiver Timeout Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+      }
+    }
+
+    return (UART_Start_Receive_IT(huart, pData, Size));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->pTxBuffPtr  = pData;
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA transfer complete callback */
+      huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+      /* Set the UART DMA Half transfer complete callback */
+      huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+      /* Set the DMA error callback */
+      huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+      /* Set the DMA abort callback */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the UART transmit DMA channel */
+      if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+        __HAL_UNLOCK(huart);
+
+        /* Restore huart->gState to ready */
+        huart->gState = HAL_UART_STATE_READY;
+
+        return HAL_ERROR;
+      }
+    }
+    /* Clear the TC flag in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+    __HAL_UNLOCK(huart);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the UART CR3 register */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode.
+  * @note   When the UART parity is enabled (PCE = 1), the received data contain
+  *         the parity bit (MSB position).
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    if (!(IS_LPUART_INSTANCE(huart->Instance)))
+    {
+      /* Check that USART RTOEN bit is set */
+      if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+      {
+        /* Enable the UART Receiver Timeout Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+      }
+    }
+
+    return (UART_Start_Receive_DMA(huart, pData, Size));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pause the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  __HAL_LOCK(huart);
+
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    /* Disable the UART DMA Tx request */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the UART DMA Rx request */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    /* Enable the UART DMA Tx request */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {    
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the UART DMA Rx request */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+     the stream and the corresponding call back is executed. */
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel */
+    if (huart->hdmatx != NULL)
+    {
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel */
+    if (huart->hdmarx != NULL)
+    {
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    UART_EndRxTransfer(huart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+  /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+                                          USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+  /* Disable TCIE, TXEIE and TXFTIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  huart->TxXferCount = 0U;
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+  /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+  uint32_t abortcplt = 1U;
+
+  /* Disable interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
+                                          USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (huart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+    {
+      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+    }
+    else
+    {
+      huart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (huart->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+    }
+    else
+    {
+      huart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* UART Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        huart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* UART Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        huart->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1U;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    huart->TxXferCount = 0U;
+    huart->RxXferCount = 0U;
+
+    /* Clear ISR function pointers */
+    huart->RxISR = NULL;
+    huart->TxISR = NULL;
+
+    /* Reset errorCode */
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Discard the received data */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+    /* Restore huart->gState and huart->RxState to Ready */
+    huart->gState  = HAL_UART_STATE_READY;
+    huart->RxState = HAL_UART_STATE_READY;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    huart->AbortCpltCallback(huart);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+        huart->hdmatx->XferAbortCallback(huart->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      huart->TxXferCount = 0U;
+
+      /* Clear TxISR function pointers */
+      huart->TxISR = NULL;
+
+      /* Restore huart->gState to Ready */
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      huart->AbortTransmitCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    huart->TxXferCount = 0U;
+
+    /* Clear TxISR function pointers */
+    huart->TxISR = NULL;
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    huart->AbortTransmitCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+        huart->hdmarx->XferAbortCallback(huart->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      huart->RxXferCount = 0U;
+
+      /* Clear RxISR function pointer */
+      huart->pRxBuffPtr = NULL;
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+      /* Discard the received data */
+      __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+      /* Restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      huart->AbortReceiveCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    huart->RxXferCount = 0U;
+
+    /* Clear RxISR function pointer */
+    huart->pRxBuffPtr = NULL;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    huart->AbortReceiveCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle UART interrupt request.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+
+  uint32_t errorflags;
+  uint32_t errorcode;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+  if (errorflags == 0U)
+  {
+    /* UART in mode Receiver ---------------------------------------------------*/
+    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+    {
+      if (huart->RxISR != NULL)
+      {
+        huart->RxISR(huart);
+      }
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != 0U)
+      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+  {
+    /* UART parity error interrupt occurred -------------------------------------*/
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+    }
+
+    /* UART frame error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+    }
+
+    /* UART noise error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+    }
+
+    /* UART Over-Run interrupt occurred -----------------------------------------*/
+    if (((isrflags & USART_ISR_ORE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+    }
+
+    /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_RTO;
+    }
+
+    /* Call UART Error Call back function if need be ----------------------------*/
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+    {
+      /* UART in mode Receiver --------------------------------------------------*/
+      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+      {
+        if (huart->RxISR != NULL)
+        {
+          huart->RxISR(huart);
+        }
+      }
+
+      /* If Error is to be considered as blocking :
+          - Receiver Timeout error in Reception
+          - Overrun error in Reception
+          - any error occurs in DMA mode reception
+      */
+      errorcode = huart->ErrorCode;
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+      {
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+
+        /* Abort the UART DMA Rx channel if enabled */
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+        {
+          /* Disable the UART DMA Rx request if enabled */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the UART DMA Rx channel */
+          if (huart->hdmarx != NULL)
+          {
+            /* Set the UART DMA Abort callback :
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered error callback*/
+            huart->ErrorCallback(huart);
+#else
+            /*Call legacy weak error callback*/
+            HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered error callback*/
+        huart->ErrorCallback(huart);
+#else
+        /*Call legacy weak error callback*/
+        HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : */
+  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      && ((isrflags & USART_ISR_IDLE) != 0U)
+      && ((cr1its & USART_ISR_IDLE) != 0U))
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+    /* Check if DMA mode is enabled in UART */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      /* DMA mode enabled */
+      /* Check received length : If all expected data are received, do nothing,
+         (DMA cplt callback will be called).
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+      if ((nb_remaining_rx_data > 0U)
+          && (nb_remaining_rx_data < huart->RxXferSize))
+      {
+        /* Reception is not complete */
+        huart->RxXferCount = nb_remaining_rx_data;
+
+        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+        if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
+        {
+          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+             in the UART CR3 register */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* At end of Rx process, restore huart->RxState to Ready */
+          huart->RxState = HAL_UART_STATE_READY;
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          /* Last bytes received, so no need as the abort is immediate */
+          (void)HAL_DMA_Abort(huart->hdmarx);
+        }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      return;
+    }
+    else
+    {
+      /* DMA mode not enabled */
+      /* Check received length : If all expected data are received, do nothing.
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+      if ((huart->RxXferCount > 0U)
+          && (nb_rx_data > 0U))
+      {
+        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+        /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxEventCallback(huart, nb_rx_data);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      return;
+    }
+  }
+
+  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+
+    /* UART Rx state is not reset as a reception process might be ongoing.
+       If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Wakeup Callback */
+    huart->WakeupCallback(huart);
+#else
+    /* Call legacy weak Wakeup Callback */
+    HAL_UARTEx_WakeupCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* UART in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+  {
+    if (huart->TxISR != NULL)
+    {
+      huart->TxISR(huart);
+    }
+    return;
+  }
+
+  /* UART in mode Transmitter (transmission end) -----------------------------*/
+  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+  {
+    UART_EndTransmit_IT(huart);
+    return;
+  }
+
+  /* UART TX Fifo Empty occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx Fifo Empty Callback */
+    huart->TxFifoEmptyCallback(huart);
+#else
+    /* Call legacy weak Tx Fifo Empty Callback */
+    HAL_UARTEx_TxFifoEmptyCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* UART RX Fifo Full occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Rx Fifo Full Callback */
+    huart->RxFifoFullCallback(huart);
+#else
+    /* Call legacy weak Rx Fifo Full Callback */
+    HAL_UARTEx_RxFifoFullCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART error callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Receive Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Reception Event Callback (Rx event notification called after use of advanced reception service).
+  * @param  huart UART handle
+  * @param  Size  Number of data available in application reception buffer (indicates a position in
+  *               reception buffer until which, data are available)
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  UNUSED(Size);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   UART control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the UART.
+     (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
+     (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
+     (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
+     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+     (+) UART_SetConfig() API configures the UART peripheral
+     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+     (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Update on the fly the receiver timeout value in RTOR register.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @param  TimeoutValue receiver timeout value in number of baud blocks. The timeout
+  *                     value must be less or equal to 0x0FFFFFFFF.
+  * @retval None
+  */
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+    MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+  }
+}
+
+/**
+  * @brief  Enable the UART receiver timeout feature.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    if (huart->gState == HAL_UART_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(huart);
+
+      huart->gState = HAL_UART_STATE_BUSY;
+
+      /* Set the USART RTOEN bit */
+      SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(huart);
+
+      return HAL_OK;
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the UART receiver timeout feature.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    if (huart->gState == HAL_UART_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(huart);
+
+      huart->gState = HAL_UART_STATE_BUSY;
+
+      /* Clear the USART RTOEN bit */
+      CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(huart);
+
+      return HAL_OK;
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable UART in mute mode (does not mean UART enters mute mode;
+  *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Enable USART mute mode by setting the MME bit in the CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
+  *         as it may not have been in mute mode at this very moment).
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Enter UART mute mode (means UART actually enters mute mode).
+  * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+  * @brief  Enable the UART transmitter and disable the UART receiver.
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the UART receiver and disable the UART transmitter.
+  * @param  huart UART handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Transmit break characters.
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Send break characters */
+  __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  *  @brief   UART Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) Return the UART handle state.
+      (+) Return the UART handle error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Return the UART handle state.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval HAL state
+  */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+  uint32_t temp1;
+  uint32_t temp2;
+  temp1 = huart->gState;
+  temp2 = huart->RxState;
+
+  return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the UART handle error code.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval UART Error Code
+  */
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+  return huart->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  huart UART handle.
+  * @retval none
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+  /* Init the UART Callback settings */
+  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
+  huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */
+  huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
+  huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
+  huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCallback           */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @brief Configure the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg;
+  uint16_t brrtemp;
+  UART_ClockSourceTypeDef clocksource;
+  uint32_t usartdiv;
+  HAL_StatusTypeDef ret               = HAL_OK;
+  uint32_t lpuart_ker_ck_pres;
+  uint32_t pclk;
+
+  /* Check the parameters */
+  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  if (UART_INSTANCE_LOWPOWER(huart))
+  {
+    assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
+  }
+  else
+  {
+    assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+    assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+  }
+
+  assert_param(IS_UART_PARITY(huart->Init.Parity));
+  assert_param(IS_UART_MODE(huart->Init.Mode));
+  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+  assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+  *  the UART Word Length, Parity, Mode and oversampling:
+  *  set the M bits according to huart->Init.WordLength value
+  *  set PCE and PS bits according to huart->Init.Parity value
+  *  set TE and RE bits according to huart->Init.Mode value
+  *  set OVER8 bit according to huart->Init.OverSampling value */
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+  * to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure
+  * - UART HardWare Flow Control: set CTSE and RTSE bits according
+  *   to huart->Init.HwFlowCtl value
+  * - one-bit sampling method versus three samples' majority rule according
+  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
+  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+
+  if (!(UART_INSTANCE_LOWPOWER(huart)))
+  {
+    tmpreg |= huart->Init.OneBitSampling;
+  }
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+  /*-------------------------- USART PRESC Configuration -----------------------*/
+  /* Configure
+  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
+  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  UART_GETCLOCKSOURCE(huart, clocksource);
+
+  /* Check LPUART instance */
+  if (UART_INSTANCE_LOWPOWER(huart))
+  {
+    /* Retrieve frequency clock */
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        pclk = (uint32_t) HSI_VALUE;
+        break;
+      case UART_CLOCKSOURCE_SYSCLK:
+        pclk = HAL_RCC_GetSysClockFreq();
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+        break;
+      default:
+        pclk = 0U;
+        ret = HAL_ERROR;
+        break;
+    }
+
+    /* If proper clock source reported */
+    if (pclk != 0U)
+    {
+      /* Compute clock after Prescaler */
+      lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
+
+      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+          (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+      {
+        ret = HAL_ERROR;
+      }
+      else
+      {
+        /* Check computed UsartDiv value is in allocated range
+           (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
+        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+        {
+          huart->Instance->BRR = usartdiv;
+        }
+        else
+        {
+          ret = HAL_ERROR;
+        }
+      } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
+                (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+    } /* if (pclk != 0) */
+  }
+  /* Check UART Over Sampling to set Baud Rate Register */
+  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+        break;
+      case UART_CLOCKSOURCE_PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        pclk = (uint32_t) HSI_VALUE;
+        break;
+      case UART_CLOCKSOURCE_SYSCLK:
+        pclk = HAL_RCC_GetSysClockFreq();
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+        break;
+      default:
+        pclk = 0U;
+        ret = HAL_ERROR;
+        break;
+    }
+
+    /* USARTDIV must be greater than or equal to 0d16 */
+    if (pclk != 0U)
+    {
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+      {
+        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+        huart->Instance->BRR = brrtemp;
+      }
+      else
+      {
+        ret = HAL_ERROR;
+      }
+    }
+  }
+  else
+  {
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+        break;
+      case UART_CLOCKSOURCE_PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        pclk = (uint32_t) HSI_VALUE;
+        break;
+      case UART_CLOCKSOURCE_SYSCLK:
+        pclk = HAL_RCC_GetSysClockFreq();
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+        break;
+      default:
+        pclk = 0U;
+        ret = HAL_ERROR;
+        break;
+    }
+
+    if (pclk != 0U)
+    {
+      /* USARTDIV must be greater than or equal to 0d16 */
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+      {
+        huart->Instance->BRR = (uint16_t)usartdiv;
+      }
+      else
+      {
+        ret = HAL_ERROR;
+      }
+    }
+  }
+
+  /* Initialize the number of data to process during RX/TX ISR execution */
+  huart->NbTxDataToProcess = 1;
+  huart->NbRxDataToProcess = 1;
+
+  /* Clear ISR function pointers */
+  huart->RxISR = NULL;
+  huart->TxISR = NULL;
+
+  return ret;
+}
+
+/**
+  * @brief Configure the UART peripheral advanced features.
+  * @param huart UART handle.
+  * @retval None
+  */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+  }
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+  {
+    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+  }
+
+  /* if required, configure auto Baud rate detection scheme */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+  {
+    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+    /* set auto Baudrate detection parameters if detection is enabled */
+    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+    {
+      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+    }
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+  }
+}
+
+/**
+  * @brief Check the UART Idle State.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+  uint32_t tickstart;
+
+  /* Initialize the UART ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Check if the Receiver is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the UART State */
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles UART Communication Timeout. It waits
+  *                  until a flag is no longer in the specified status.
+  * @param huart     UART handle.
+  * @param Flag      Specifies the UART flag to check
+  * @param Status    The actual Flag status (SET or RESET)
+  * @param Tickstart Tick start value
+  * @param Timeout   Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+           interrupts for the interrupt process */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+                                                USART_CR1_TXEIE_TXFNFIE));
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+        huart->gState = HAL_UART_STATE_READY;
+        huart->RxState = HAL_UART_STATE_READY;
+
+        __HAL_UNLOCK(huart);
+
+        return HAL_TIMEOUT;
+      }
+
+      if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+      {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+        {
+          /* Clear Receiver Timeout flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+             interrupts for the interrupt process */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+                                                  USART_CR1_TXEIE_TXFNFIE));
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+          huart->gState = HAL_UART_STATE_READY;
+          huart->RxState = HAL_UART_STATE_READY;
+          huart->ErrorCode = HAL_UART_ERROR_RTO;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start Receive operation in interrupt mode.
+  * @note   This function could be called by all HAL UART API providing reception in Interrupt mode.
+  * @note   When calling this function, parameters validity is considered as already checked,
+  *         i.e. Rx State, buffer address, ...
+  *         UART Handle is assumed as Locked.
+  * @param  huart UART handle.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  huart->pRxBuffPtr  = pData;
+  huart->RxXferSize  = Size;
+  huart->RxXferCount = Size;
+  huart->RxISR       = NULL;
+
+  /* Computation of UART mask to apply to RDR register */
+  UART_MASK_COMPUTATION(huart);
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Configure Rx interrupt processing */
+  if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+  {
+    /* Set the Rx ISR function pointer according to the data word length */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+    }
+    else
+    {
+      huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+    }
+
+    __HAL_UNLOCK(huart);
+
+    /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+  }
+  else
+  {
+    /* Set the Rx ISR function pointer according to the data word length */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      huart->RxISR = UART_RxISR_16BIT;
+    }
+    else
+    {
+      huart->RxISR = UART_RxISR_8BIT;
+    }
+
+    __HAL_UNLOCK(huart);
+
+    /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+    }
+    else
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }  
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start Receive operation in DMA mode.
+  * @note   This function could be called by all HAL UART API providing reception in DMA mode.
+  * @note   When calling this function, parameters validity is considered as already checked,
+  *         i.e. Rx State, buffer address, ...
+  *         UART Handle is assumed as Locked.
+  * @param  huart UART handle.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  huart->pRxBuffPtr = pData;
+  huart->RxXferSize = Size;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+  if (huart->hdmarx != NULL)
+  {
+    /* Set the UART DMA transfer complete callback */
+    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+    /* Set the UART DMA Half transfer complete callback */
+    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+    /* Set the DMA error callback */
+    huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+    /* Set the DMA abort callback */
+    huart->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+    {
+      /* Set error code to DMA */
+      huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+      __HAL_UNLOCK(huart);
+
+      /* Restore huart->RxState to ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      return HAL_ERROR;
+    }
+  }
+  __HAL_UNLOCK(huart);
+
+  /* Enable the UART Parity Error Interrupt */
+  if (huart->Init.Parity != UART_PARITY_NONE)
+  {
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+  }
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+  in the UART CR3 register */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE, TCIE, TXFT interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+
+  /* At end of Tx process, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+  }
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Reset RxIsr function pointer */
+  huart->RxISR = NULL;
+}
+
+
+/**
+  * @brief DMA UART transmit process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+  {
+    huart->TxXferCount = 0U;
+
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Enable the UART Transmit Complete Interrupt */
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+  }
+  /* DMA Circular mode */
+  else
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Tx complete callback*/
+    huart->TxCpltCallback(huart);
+#else
+    /*Call legacy weak Tx complete callback*/
+    HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART transmit process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx Half complete callback*/
+  huart->TxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Tx Half complete callback*/
+  HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA UART receive process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+  {
+    huart->RxXferCount = 0U;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+    {
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+    }
+  }
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : use Rx Event callback */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Event callback*/
+    huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+    /*Call legacy weak Rx Event callback*/
+    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* In other cases : use Rx Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx complete callback*/
+    huart->RxCpltCallback(huart);
+#else
+    /*Call legacy weak Rx complete callback*/
+    HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART receive process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : use Rx Event callback */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Event callback*/
+    huart->RxEventCallback(huart, huart->RxXferSize / 2U);
+#else
+    /*Call legacy weak Rx Event callback*/
+    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* In other cases : use Rx Half Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Half complete callback*/
+    huart->RxHalfCpltCallback(huart);
+#else
+    /*Call legacy weak Rx Half complete callback*/
+    HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART communication error callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    huart->TxXferCount = 0U;
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    huart->RxXferCount = 0U;
+    UART_EndRxTransfer(huart);
+  }
+
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+  huart->RxXferCount = 0U;
+  huart->TxXferCount = 0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmarx != NULL)
+  {
+    if (huart->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmatx != NULL)
+  {
+    if (huart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->TxXferCount = 0U;
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  huart->AbortTransmitCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  huart->AbortReceiveCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief TX interrupt handler for 7 or 8 bits data word length .
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
+{
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if (huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+      huart->pTxBuffPtr++;
+      huart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief TX interrupt handler for 9 bits data word length.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
+{
+  const uint16_t *tmp;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if (huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      tmp = (const uint16_t *) huart->pTxBuffPtr;
+      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+      huart->pTxBuffPtr += 2U;
+      huart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (huart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+        /* Enable the UART Transmit Complete Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+        break; /* force exit loop */
+      }
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+        huart->pTxBuffPtr++;
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  const uint16_t *tmp;
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (huart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+        /* Enable the UART Transmit Complete Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+        break; /* force exit loop */
+      }
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        tmp = (const uint16_t *) huart->pTxBuffPtr;
+        huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+        huart->pTxBuffPtr += 2U;
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  huart pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable the UART Transmit Complete Interrupt */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Cleat TxISR function pointer */
+  huart->TxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief RX interrupt handler for 7 or 8 bits data word length .
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+    huart->pRxBuffPtr++;
+    huart->RxXferCount--;
+
+    if (huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+
+      /* Check current reception Mode :
+         If Reception till IDLE event has been selected : */
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Disable IDLE interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+        {
+          /* Clear IDLE Flag */
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      else
+      {
+        /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrupt handler for 9 bits data word length .
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    tmp = (uint16_t *) huart->pRxBuffPtr ;
+    *tmp = (uint16_t)(uhdata & uhMask);
+    huart->pRxBuffPtr += 2U;
+    huart->RxXferCount--;
+
+    if (huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+
+      /* Check current reception Mode :
+         If Reception till IDLE event has been selected : */
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Disable IDLE interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+        {
+          /* Clear IDLE Flag */
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      else
+      {
+        /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+  uint16_t  nb_rx_data;
+  uint16_t  rxdatacount;
+  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
+  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
+  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    nb_rx_data = huart->NbRxDataToProcess;
+    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+      *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+      huart->pRxBuffPtr++;
+      huart->RxXferCount--;
+      isrflags = READ_REG(huart->Instance->ISR);
+
+      /* If some non blocking errors occurred */
+      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+      {
+        /* UART parity error interrupt occurred -------------------------------------*/
+        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_PE;
+        }
+
+        /* UART frame error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_FE;
+        }
+
+        /* UART noise error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_NE;
+        }
+
+        /* Call UART Error Call back function if need be ----------------------------*/
+        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+        {
+          /* Non Blocking error : transfer could go on.
+          Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          huart->ErrorCode = HAL_UART_ERROR_NONE;
+        }
+      }
+
+      if (huart->RxXferCount == 0U)
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+           and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+        /* Check current reception Mode :
+           If Reception till IDLE event has been selected : */
+        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+        {
+          /* Set reception type to Standard */
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          /* Disable IDLE interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+          {
+            /* Clear IDLE Flag */
+            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+          }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx Event callback*/
+          huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+          /*Call legacy weak Rx Event callback*/
+          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+        }
+        else
+        {
+          /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx complete callback*/
+          huart->RxCpltCallback(huart);
+#else
+          /*Call legacy weak Rx complete callback*/
+          HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_8BIT;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+  uint16_t  nb_rx_data;
+  uint16_t  rxdatacount;
+  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
+  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
+  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    nb_rx_data = huart->NbRxDataToProcess;
+    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+      tmp = (uint16_t *) huart->pRxBuffPtr ;
+      *tmp = (uint16_t)(uhdata & uhMask);
+      huart->pRxBuffPtr += 2U;
+      huart->RxXferCount--;
+      isrflags = READ_REG(huart->Instance->ISR);
+
+      /* If some non blocking errors occurred */
+      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+      {
+        /* UART parity error interrupt occurred -------------------------------------*/
+        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_PE;
+        }
+
+        /* UART frame error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_FE;
+        }
+
+        /* UART noise error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_NE;
+        }
+
+        /* Call UART Error Call back function if need be ----------------------------*/
+        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+        {
+          /* Non Blocking error : transfer could go on.
+          Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          huart->ErrorCode = HAL_UART_ERROR_NONE;
+        }
+      }
+
+      if (huart->RxXferCount == 0U)
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+           and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+        /* Check current reception Mode :
+           If Reception till IDLE event has been selected : */
+        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+        {
+          /* Set reception type to Standard */
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          /* Disable IDLE interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+          {
+            /* Clear IDLE Flag */
+            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+          }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx Event callback*/
+          huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+          /*Call legacy weak Rx Event callback*/
+          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+        }
+        else
+        {
+          /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx complete callback*/
+          huart->RxCpltCallback(huart);
+#else
+          /*Call legacy weak Rx complete callback*/
+          HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_16BIT;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c
new file mode 100644
index 0000000..c980cee
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c
@@ -0,0 +1,1018 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_uart_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended UART HAL module driver.
+  *          This file provides firmware functions to manage the following extended
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### UART peripheral extended features  #####
+  ==============================================================================
+
+    (#) Declare a UART_HandleTypeDef handle structure.
+
+    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+        -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
+            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+            configured prior starting RX/TX transfers.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UARTEx UARTEx
+  * @brief UART Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
+  * @{
+  */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+  * @{
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
+  * @{
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Extended Initialization and Configuration Functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+     procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible UART formats are listed in the
+  following table.
+
+    Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the RS485 Driver enable feature according to the specified
+  *         parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart            UART handle.
+  * @param Polarity         Select the driver enable polarity.
+  *          This parameter can be one of the following values:
+  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
+  * @param AssertionTime    Driver Enable assertion time:
+  *       5-bit value defining the time between the activation of the DE (Driver Enable)
+  *       signal and the beginning of the start bit. It is expressed in sample time
+  *       units (1/8 or 1/16 bit time, depending on the oversampling rate)
+  * @param DeassertionTime  Driver Enable deassertion time:
+  *       5-bit value defining the time between the end of the last stop bit, in a
+  *       transmitted message, and the de-activation of the DE (Driver Enable) signal.
+  *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+  *       oversampling rate).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime)
+{
+  uint32_t temp;
+
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check the Driver Enable UART instance */
+  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+  /* Check the Driver Enable polarity */
+  assert_param(IS_UART_DE_POLARITY(Polarity));
+
+  /* Check the Driver Enable assertion time */
+  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+  /* Check the Driver Enable deassertion time */
+  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+  /* Set the Driver Enable polarity */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+  /* Set the Driver Enable assertion and deassertion times */
+  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+  *  @brief Extended functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of Wakeup and FIFO mode related callback functions.
+
+    (#) Wakeup from Stop mode Callback:
+        (+) HAL_UARTEx_WakeupCallback()
+
+    (#) TX/RX Fifos Callbacks:
+        (+) HAL_UARTEx_RxFifoFullCallback()
+        (+) HAL_UARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief UART wakeup from Stop mode callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART RX Fifo full callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART TX Fifo empty callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+  * @brief    Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..] This section provides the following functions:
+     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+         detection length to more than 4 bits for multiprocessor address mark wake up.
+     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+         trigger: address match, Start Bit detection or RXNE bit status.
+     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+     (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
+     (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
+     (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+     (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+    [..] This subsection also provides a set of additional functions providing enhanced reception
+    services to user. (For example, these functions allow application to handle use cases
+    where number of data to be received is unknown).
+
+    (#) Compared to standard reception services which only consider number of received
+        data elements as reception completion criteria, these functions also consider additional events
+        as triggers for updating reception status to caller :
+       (+) Detection of inactivity period (RX line has not been active for a given period).
+          (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
+               for 1 frame time, after last received byte.
+          (++) RX inactivity detected by RTO, i.e. line has been in idle state
+               for a programmable time, after last received byte.
+       (+) Detection that a specific character has been received.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
+           or till IDLE event occurs. Reception is handled only during function execution.
+           When function exits, no data reception could occur. HAL status and number of actually received data elements,
+           are returned by function after finishing transfer.
+       (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
+           These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
+           The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
+
+    (#) Blocking mode API:
+        (+) HAL_UARTEx_ReceiveToIdle()
+
+    (#) Non-Blocking mode API with Interrupt:
+        (+) HAL_UARTEx_ReceiveToIdle_IT()
+
+    (#) Non-Blocking mode API with DMA:
+        (+) HAL_UARTEx_ReceiveToIdle_DMA()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief By default in multiprocessor mode, when the wake up method is set
+  *        to address mark, the UART handles only 4-bit long addresses detection;
+  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
+  *        long).
+  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+  * @param huart         UART handle.
+  * @param AddressLength This parameter can be one of the following values:
+  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address length parameter */
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Set Wakeup from Stop mode interrupt flag selection.
+  * @note It is the application responsibility to enable the interrupt used as
+  *       usart_wkup interrupt source before entering low-power mode.
+  * @param huart           UART handle.
+  * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
+  *          This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUP_ON_ADDRESS
+  *          @arg @ref UART_WAKEUP_ON_STARTBIT
+  *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* check the wake-up from stop mode UART instance */
+  assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+  /* check the wake-up selection parameter */
+  assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the wake-up selection scheme */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+  if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+  {
+    UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+
+  /* Wait until REACK flag is set */
+  if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+  {
+    status = HAL_TIMEOUT;
+  }
+  else
+  {
+    /* Initialize the UART State */
+    huart->gState = HAL_UART_STATE_READY;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief Enable UART Stop Mode.
+  * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  /* Set UESM bit */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable UART Stop Mode.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  /* Clear UESM bit */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Enable FIFO mode */
+  SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+  huart->FifoMode = UART_FIFOMODE_ENABLE;
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Enable FIFO mode */
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+  huart->FifoMode = UART_FIFOMODE_DISABLE;
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the TXFIFO threshold.
+  * @param huart      UART handle.
+  * @param Threshold  TX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_4
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_2
+  *            @arg @ref UART_TXFIFO_THRESHOLD_3_4
+  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Update TX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the RXFIFO threshold.
+  * @param huart      UART handle.
+  * @param Threshold  RX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_4
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_2
+  *            @arg @ref UART_RXFIFO_THRESHOLD_3_4
+  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check the parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Update RX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode till either the expected number of data
+  *        is received or an IDLE event occurs.
+  * @note  HAL_OK is returned if reception is completed (expected number of data has been received)
+  *        or if reception is stopped after IDLE event (less than the expected number of data has been received)
+  *        In this case, RxLen output parameter indicates number of data available in reception buffer.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *        of uint16_t available through pData.
+  * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+  *       is not empty. Read operations from the RDR register are performed when
+  *       RXFNE flag is set. From hardware perspective, RXFNE flag and
+  *       RXNE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.
+  * @param RxLen   Number of data elements finally received
+  *                (could be lower than Size, in case reception ends on IDLE event)
+  * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+                                           uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint16_t uhMask;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+    uhMask = huart->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    __HAL_UNLOCK(huart);
+
+    /* Initialize output number of received elements */
+    *RxLen = 0U;
+
+    /* as long as data have to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      /* Check if IDLE flag is set */
+      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+      {
+        /* Clear IDLE flag in ISR */
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+        /* If Set, but no data ever received, clear flag without exiting loop */
+        /* If Set, and data has already been received, this means Idle Event is valid : End reception */
+        if (*RxLen > 0U)
+        {
+          huart->RxState = HAL_UART_STATE_READY;
+
+          return HAL_OK;
+        }
+      }
+
+      /* Check if RXNE flag is set */
+      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
+      {
+        if (pdata8bits == NULL)
+        {
+          *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+          pdata16bits++;
+        }
+        else
+        {
+          *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+          pdata8bits++;
+        }
+        /* Increment number of received elements */
+        *RxLen += 1U;
+        huart->RxXferCount--;
+      }
+
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          huart->RxState = HAL_UART_STATE_READY;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set number of received elements in output parameter : RxLen */
+    *RxLen = huart->RxXferSize - huart->RxXferCount;
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode till either the expected number of data
+  *        is received or an IDLE event occurs.
+  * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
+  *        to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
+  *        number of received data elements.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *        of uint16_t available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    /* Set Reception type to reception till IDLE Event*/
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+    status =  UART_Start_Receive_IT(huart, pData, Size);
+
+    /* Check Rx process has been successfully started */
+    if (status == HAL_OK)
+    {
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+      }
+      else
+      {
+        /* In case of errors already pending when reception is started,
+           Interrupts may have already been raised and lead to reception abortion.
+           (Overrun error for instance).
+           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+        status = HAL_ERROR;
+      }
+    }
+
+    return status;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode till either the expected number
+  *        of data is received or an IDLE event occurs.
+  * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
+  *        to DMA services, transferring automatically received data elements in user reception buffer and
+  *        calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
+  *        reception phase as ended. In all cases, callback execution will indicate number of received data elements.
+  * @note  When the UART parity is enabled (PCE = 1), the received data contain
+  *        the parity bit (MSB position).
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *        of uint16_t available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    /* Set Reception type to reception till IDLE Event*/
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+    status =  UART_Start_Receive_DMA(huart, pData, Size);
+
+    /* Check Rx process has been successfully started */
+    if (status == HAL_OK)
+    {
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+      }
+      else
+      {
+        /* In case of errors already pending when reception is started,
+           Interrupts may have already been raised and lead to reception abortion.
+           (Overrun error for instance).
+           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+        status = HAL_ERROR;
+      }
+    }
+
+    return status;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+  * @param huart           UART handle.
+  * @param WakeUpSelection UART wake up from stop mode parameters.
+  * @retval None
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+  /* Set the USART address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+  /* Set the USART address node */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+  * @brief Calculate the number of data to process in RX/TX ISR.
+  * @note The RX FIFO depth and the TX FIFO depth is extracted from
+  *       the UART configuration registers.
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
+{
+  uint8_t rx_fifo_depth;
+  uint8_t tx_fifo_depth;
+  uint8_t rx_fifo_threshold;
+  uint8_t tx_fifo_threshold;
+  static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+  {
+    huart->NbTxDataToProcess = 1U;
+    huart->NbRxDataToProcess = 1U;
+  }
+  else
+  {
+    rx_fifo_depth = RX_FIFO_DEPTH;
+    tx_fifo_depth = TX_FIFO_DEPTH;
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+                               (uint16_t)denominator[tx_fifo_threshold];
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+                               (uint16_t)denominator[rx_fifo_threshold];
+  }
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c
new file mode 100644
index 0000000..b40c47c
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c
@@ -0,0 +1,1425 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_adc.c
+  * @author  MCD Application Team
+  * @brief   ADC LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_ll_adc.h"
+#include "stm32g4xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
+
+/** @addtogroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Constants
+  * @{
+  */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
+/*       not timeout values:                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
+/*       values definition.                                                   */
+/* Note: ADC timeout values are defined here in CPU cycles to be independent  */
+/*       of device clock setting.                                             */
+/*       In user application, ADC timeout values should be defined with       */
+/*       temporal values, in function of device clock settings.               */
+/*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
+/*        - ADC clock from synchronous clock with AHB prescaler 512,          */
+/*          ADC prescaler 4.                                                  */
+/*           Ratio max = 512 *4 = 2048                                        */
+/*        - ADC clock from asynchronous clock (PLLP) with prescaler 256.      */
+/*          Highest CPU clock PLL (PLLR).                                     */
+/*           Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256    */
+/*                     = 3968                                                 */
+/* Unit: CPU cycles.                                                          */
+#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          (3968UL)
+#define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* common to several ADC instances.                                           */
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
+  (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
+   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC instance.                                                              */
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
+  (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                                 \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
+  )
+
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
+  (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                               \
+   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
+  )
+
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
+  (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                    \
+   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC group regular                                                          */
+#if defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)               \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG5)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG6)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG7)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG8)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG9)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG10)               \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2)           \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3)           \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         \
+          )                                                                    \
+      )                                                                        \
+   || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2)          \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG2)          \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG4)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)               \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2)           \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3)           \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         \
+          )                                                                    \
+      )                                                                        \
+   || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#elif defined(STM32G471xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         \
+          )                                                                    \
+      )                                                                        \
+   || (((__ADC_INSTANCE__) == ADC3) \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
+  )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)               \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2)           \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3)           \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         \
+          )                                                                    \
+      )                                                                        \
+   || (((__ADC_INSTANCE__) == ADC3)                                            \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#endif
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
+  (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                       \
+   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
+  )
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
+  (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                    \
+   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
+   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
+  )
+
+#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
+  (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)              \
+   || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
+  )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
+  (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)                  \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
+  )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
+  (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)              \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC group injected                                                         */
+#if defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
+  (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)               \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10)               \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)         \
+          )                                                                    \
+      )                                                                        \
+   || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1)          \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3)          \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
+  (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)               \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)         \
+          )                                                                    \
+      )                                                                        \
+   || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#elif defined(STM32G471xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
+  (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)         \
+          )                                                                    \
+      )                                                                        \
+   || ((((__ADC_INSTANCE__) == ADC3)) \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
+  (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
+  )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
+  (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)               \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)         \
+          )                                                                    \
+      )                                                                        \
+   || ((((__ADC_INSTANCE__) == ADC3))                                          \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#endif
+
+#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \
+  (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                     \
+   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
+   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
+  )
+
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
+  (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                        \
+   || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
+  )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
+  (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)                  \
+   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
+   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
+   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
+  )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
+  (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)              \
+   || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
+  )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* multimode.                                                                 */
+#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)                                   \
+  (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                              \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \
+  )
+
+#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)                   \
+  (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)                 \
+   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B)       \
+   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B)         \
+   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B)       \
+   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B)         \
+  )
+
+#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)                   \
+  (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)              \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)         \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)         \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)         \
+  )
+
+#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)                   \
+  (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                           \
+   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
+   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
+  )
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of all ADC instances belonging to
+  *         the same ADC common instance to their default reset values.
+  * @note   This function is performing a hard reset, using high level
+  *         clock source RCC ADC reset.
+  *         Caution: On this STM32 series, if several ADC instances are available
+  *         on the selected device, RCC ADC reset will reset
+  *         all ADC instances belonging to the common ADC instance.
+  *         To de-initialize only 1 ADC instance, use
+  *         function @ref LL_ADC_DeInit().
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC common registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+  if (ADCxy_COMMON == ADC12_COMMON)
+  {
+    /* Force reset of ADC clock (core clock) */
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12);
+
+    /* Release reset of ADC clock (core clock) */
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12);
+  }
+#if defined(ADC345_COMMON)
+  else
+  {
+    /* Force reset of ADC clock (core clock) */
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC345);
+
+    /* Release reset of ADC clock (core clock) */
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC345);
+  }
+#endif
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize some features of ADC common parameters
+  *         (all ADC instances belonging to the same ADC common instance)
+  *         and multimode (for devices with several ADC instances available).
+  * @note   The setting of ADC common parameters is conditioned to
+  *         ADC instances state:
+  *         All ADC instances belonging to the same ADC common instance
+  *         must be disabled.
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC common registers are initialized
+  *          - ERROR: ADC common registers are not initialized
+  */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+  assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+  assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
+  if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+  {
+    assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
+    assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
+  }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Note: Hardware constraint (refer to description of functions             */
+  /*       "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"):               */
+  /*       On this STM32 series, setting of these features is conditioned to  */
+  /*       ADC state:                                                         */
+  /*       All ADC instances of the ADC common group must be disabled.        */
+  if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - common to several ADC                                               */
+    /*    (all ADC instances belonging to the same ADC common instance)       */
+    /*    - Set ADC clock (conversion clock)                                  */
+    /*  - multimode (if several ADC instances available on the                */
+    /*    selected device)                                                    */
+    /*    - Set ADC multimode configuration                                   */
+    /*    - Set ADC multimode DMA transfer                                    */
+    /*    - Set ADC multimode: delay between 2 sampling phases                */
+#if defined(ADC_MULTIMODE_SUPPORT)
+    if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+    {
+      MODIFY_REG(ADCxy_COMMON->CCR,
+                 ADC_CCR_CKMODE
+                 | ADC_CCR_PRESC
+                 | ADC_CCR_DUAL
+                 | ADC_CCR_MDMA
+                 | ADC_CCR_DELAY
+                 ,
+                 ADC_CommonInitStruct->CommonClock
+                 | ADC_CommonInitStruct->Multimode
+                 | ADC_CommonInitStruct->MultiDMATransfer
+                 | ADC_CommonInitStruct->MultiTwoSamplingDelay
+                );
+    }
+    else
+    {
+      MODIFY_REG(ADCxy_COMMON->CCR,
+                 ADC_CCR_CKMODE
+                 | ADC_CCR_PRESC
+                 | ADC_CCR_DUAL
+                 | ADC_CCR_MDMA
+                 | ADC_CCR_DELAY
+                 ,
+                 ADC_CommonInitStruct->CommonClock
+                 | LL_ADC_MULTI_INDEPENDENT
+                );
+    }
+#else
+    LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
+#endif
+  }
+  else
+  {
+    /* Initialization error: One or several ADC instances belonging to        */
+    /* the same ADC common instance are not disabled.                         */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+  * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+  *                              whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+  /* Set ADC_CommonInitStruct fields to default values */
+  /* Set fields of ADC common */
+  /* (all ADC instances belonging to the same ADC common instance) */
+  ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+  /* Set fields of ADC multimode */
+  ADC_CommonInitStruct->Multimode             = LL_ADC_MULTI_INDEPENDENT;
+  ADC_CommonInitStruct->MultiDMATransfer      = LL_ADC_MULTI_REG_DMA_EACH_ADC;
+  ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
+#endif /* ADC_MULTIMODE_SUPPORT */
+}
+
+/**
+  * @brief  De-initialize registers of the selected ADC instance
+  *         to their default reset values.
+  * @note   To reset all ADC instances quickly (perform a hard reset),
+  *         use function @ref LL_ADC_CommonDeInit().
+  * @note   If this functions returns error status, it means that ADC instance
+  *         is in an unknown state.
+  *         In this case, perform a hard reset using high level
+  *         clock source RCC ADC reset.
+  *         Caution: On this STM32 series, if several ADC instances are available
+  *         on the selected device, RCC ADC reset will reset
+  *         all ADC instances belonging to the common ADC instance.
+  *         Refer to function @ref LL_ADC_CommonDeInit().
+  * @param  ADCx ADC instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are de-initialized
+  *          - ERROR: ADC registers are not de-initialized
+  */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+  ErrorStatus status = SUCCESS;
+
+  __IO uint32_t timeout_cpu_cycles = 0UL;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+  /* Disable ADC instance if not already disabled.                            */
+  if (LL_ADC_IsEnabled(ADCx) == 1UL)
+  {
+    /* Set ADC group regular trigger source to SW start to ensure to not      */
+    /* have an external trigger event occurring during the conversion stop    */
+    /* ADC disable process.                                                   */
+    LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
+
+    /* Stop potential ADC conversion on going on ADC group regular.           */
+    if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
+    {
+      if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
+      {
+        LL_ADC_REG_StopConversion(ADCx);
+      }
+    }
+
+    /* Set ADC group injected trigger source to SW start to ensure to not     */
+    /* have an external trigger event occurring during the conversion stop    */
+    /* ADC disable process.                                                   */
+    LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
+
+    /* Stop potential ADC conversion on going on ADC group injected.          */
+    if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
+    {
+      if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
+      {
+        LL_ADC_INJ_StopConversion(ADCx);
+      }
+    }
+
+    /* Wait for ADC conversions are effectively stopped                       */
+    timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+    while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
+            | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
+    {
+      timeout_cpu_cycles--;
+      if (timeout_cpu_cycles == 0UL)
+      {
+        /* Time-out error */
+        status = ERROR;
+        break;
+      }
+    }
+
+    /* Flush group injected contexts queue (register JSQR):                   */
+    /* Note: Bit JQM must be set to empty the contexts queue (otherwise       */
+    /*       contexts queue is maintained with the last active context).      */
+    LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
+
+    /* Disable the ADC instance */
+    LL_ADC_Disable(ADCx);
+
+    /* Wait for ADC instance is effectively disabled */
+    timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
+    while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
+    {
+      timeout_cpu_cycles--;
+      if (timeout_cpu_cycles == 0UL)
+      {
+        /* Time-out error */
+        status = ERROR;
+        break;
+      }
+    }
+  }
+
+  /* Check whether ADC state is compliant with expected state */
+  if (READ_BIT(ADCx->CR,
+               (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+                | ADC_CR_ADDIS | ADC_CR_ADEN)
+              )
+      == 0UL)
+  {
+    /* ========== Reset ADC registers ========== */
+    /* Reset register IER */
+    CLEAR_BIT(ADCx->IER,
+              (LL_ADC_IT_ADRDY
+               | LL_ADC_IT_EOC
+               | LL_ADC_IT_EOS
+               | LL_ADC_IT_OVR
+               | LL_ADC_IT_EOSMP
+               | LL_ADC_IT_JEOC
+               | LL_ADC_IT_JEOS
+               | LL_ADC_IT_JQOVF
+               | LL_ADC_IT_AWD1
+               | LL_ADC_IT_AWD2
+               | LL_ADC_IT_AWD3
+              )
+             );
+
+    /* Reset register ISR */
+    SET_BIT(ADCx->ISR,
+            (LL_ADC_FLAG_ADRDY
+             | LL_ADC_FLAG_EOC
+             | LL_ADC_FLAG_EOS
+             | LL_ADC_FLAG_OVR
+             | LL_ADC_FLAG_EOSMP
+             | LL_ADC_FLAG_JEOC
+             | LL_ADC_FLAG_JEOS
+             | LL_ADC_FLAG_JQOVF
+             | LL_ADC_FLAG_AWD1
+             | LL_ADC_FLAG_AWD2
+             | LL_ADC_FLAG_AWD3
+            )
+           );
+
+    /* Reset register CR */
+    /*  - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,  */
+    /*    ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in                      */
+    /*    access mode "read-set": no direct reset applicable.                 */
+    /*  - Reset Calibration mode to default setting (single ended).           */
+    /*  - Disable ADC internal voltage regulator.                             */
+    /*  - Enable ADC deep power down.                                         */
+    /*    Note: ADC internal voltage regulator disable and ADC deep power     */
+    /*          down enable are conditioned to ADC state disabled:            */
+    /*          already done above.                                           */
+    CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
+    SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
+
+    /* Reset register CFGR */
+    MODIFY_REG(ADCx->CFGR,
+               (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN
+                | ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
+                | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
+                | ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD
+                | ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN
+                | ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN),
+               ADC_CFGR_JQDIS
+              );
+
+    /* Reset register CFGR2 */
+    CLEAR_BIT(ADCx->CFGR2,
+              (ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
+               | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG
+               | ADC_CFGR2_GCOMP
+               | ADC_CFGR2_OVSR   | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
+             );
+
+    /* Reset register SMPR1 */
+    CLEAR_BIT(ADCx->SMPR1,
+              (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
+               | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
+               | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
+             );
+
+    /* Reset register SMPR2 */
+    CLEAR_BIT(ADCx->SMPR2,
+              (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
+               | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
+               | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
+             );
+
+    /* Reset register TR1 */
+    MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
+
+    /* Reset register TR2 */
+    MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
+
+    /* Reset register TR3 */
+    MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
+
+    /* Reset register SQR1 */
+    CLEAR_BIT(ADCx->SQR1,
+              (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
+               | ADC_SQR1_SQ1 | ADC_SQR1_L)
+             );
+
+    /* Reset register SQR2 */
+    CLEAR_BIT(ADCx->SQR2,
+              (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
+               | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
+             );
+
+    /* Reset register SQR3 */
+    CLEAR_BIT(ADCx->SQR3,
+              (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
+               | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
+             );
+
+    /* Reset register SQR4 */
+    CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+    /* Reset register JSQR */
+    CLEAR_BIT(ADCx->JSQR,
+              (ADC_JSQR_JL
+               | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
+               | ADC_JSQR_JSQ4    | ADC_JSQR_JSQ3
+               | ADC_JSQR_JSQ2    | ADC_JSQR_JSQ1)
+             );
+
+    /* Reset register DR */
+    /* Note: bits in access mode read only, no direct reset applicable */
+
+    /* Reset register OFR1 */
+    CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS);
+    /* Reset register OFR2 */
+    CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS);
+    /* Reset register OFR3 */
+    CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS);
+    /* Reset register OFR4 */
+    CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS);
+
+    /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+    /* Note: bits in access mode read only, no direct reset applicable */
+
+    /* Reset register AWD2CR */
+    CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+    /* Reset register AWD3CR */
+    CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+    /* Reset register DIFSEL */
+    CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+    /* Reset register CALFACT */
+    CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+
+    /* Reset register GCOMP */
+    CLEAR_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF);
+  }
+  else
+  {
+    /* ADC instance is in an unknown state */
+    /* Need to performing a hard reset of ADC instance, using high level      */
+    /* clock source RCC ADC reset.                                            */
+    /* Caution: On this STM32 series, if several ADC instances are available  */
+    /*          on the selected device, RCC ADC reset will reset              */
+    /*          all ADC instances belonging to the common ADC instance.       */
+    /* Caution: On this STM32 series, if several ADC instances are available  */
+    /*          on the selected device, RCC ADC reset will reset              */
+    /*          all ADC instances belonging to the common ADC instance.       */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Affects both group regular and group injected (availability
+  *         of ADC group injected depends on STM32 families).
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, some other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group regular or group injected sequencer:
+  *            map channel on the selected sequencer rank.
+  *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+  assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
+  assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
+  assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
+
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if (LL_ADC_IsEnabled(ADCx) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC instance                                                        */
+    /*    - Set ADC data resolution                                           */
+    /*    - Set ADC conversion data alignment                                 */
+    /*    - Set ADC low power mode                                            */
+    MODIFY_REG(ADCx->CFGR,
+               ADC_CFGR_RES
+               | ADC_CFGR_ALIGN
+               | ADC_CFGR_AUTDLY
+               ,
+               ADC_InitStruct->Resolution
+               | ADC_InitStruct->DataAlignment
+               | ADC_InitStruct->LowPowerMode
+              );
+
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
+  * @param  ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+  *                        whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+  /* Set ADC_InitStruct fields to default values */
+  /* Set fields of ADC instance */
+  ADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
+  ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+  ADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
+
+}
+
+/**
+  * @brief  Initialize some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group regular or group injected sequencer:
+  *            map channel on the selected sequencer rank.
+  *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
+  assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
+  if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+  {
+    assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+
+    /* ADC group regular continuous mode and discontinuous mode                 */
+    /* can not be enabled simultenaeously                                       */
+    assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+                 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
+  }
+  assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
+  assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
+  assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
+
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if (LL_ADC_IsEnabled(ADCx) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC group regular                                                   */
+    /*    - Set ADC group regular trigger source                              */
+    /*    - Set ADC group regular sequencer length                            */
+    /*    - Set ADC group regular sequencer discontinuous mode                */
+    /*    - Set ADC group regular continuous mode                             */
+    /*    - Set ADC group regular conversion data transfer: no transfer or    */
+    /*      transfer by DMA, and DMA requests mode                            */
+    /*    - Set ADC group regular overrun behavior                            */
+    /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by    */
+    /*       setting of trigger source to SW start.                           */
+    if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+    {
+      MODIFY_REG(ADCx->CFGR,
+                 ADC_CFGR_EXTSEL
+                 | ADC_CFGR_EXTEN
+                 | ADC_CFGR_DISCEN
+                 | ADC_CFGR_DISCNUM
+                 | ADC_CFGR_CONT
+                 | ADC_CFGR_DMAEN
+                 | ADC_CFGR_DMACFG
+                 | ADC_CFGR_OVRMOD
+                 ,
+                 ADC_REG_InitStruct->TriggerSource
+                 | ADC_REG_InitStruct->SequencerDiscont
+                 | ADC_REG_InitStruct->ContinuousMode
+                 | ADC_REG_InitStruct->DMATransfer
+                 | ADC_REG_InitStruct->Overrun
+                );
+    }
+    else
+    {
+      MODIFY_REG(ADCx->CFGR,
+                 ADC_CFGR_EXTSEL
+                 | ADC_CFGR_EXTEN
+                 | ADC_CFGR_DISCEN
+                 | ADC_CFGR_DISCNUM
+                 | ADC_CFGR_CONT
+                 | ADC_CFGR_DMAEN
+                 | ADC_CFGR_DMACFG
+                 | ADC_CFGR_OVRMOD
+                 ,
+                 ADC_REG_InitStruct->TriggerSource
+                 | LL_ADC_REG_SEQ_DISCONT_DISABLE
+                 | ADC_REG_InitStruct->ContinuousMode
+                 | ADC_REG_InitStruct->DMATransfer
+                 | ADC_REG_InitStruct->Overrun
+                );
+    }
+
+    /* Set ADC group regular sequencer length and scan direction */
+    LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+  * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  *                            whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+  /* Set ADC_REG_InitStruct fields to default values */
+  /* Set fields of ADC group regular */
+  /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by      */
+  /*       setting of trigger source to SW start.                             */
+  ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
+  ADC_REG_InitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
+  ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+  ADC_REG_InitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
+  ADC_REG_InitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
+  ADC_REG_InitStruct->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+}
+
+/**
+  * @brief  Initialize some features of ADC group injected.
+  * @note   These parameters have an impact on ADC scope: ADC group injected.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "INJ").
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group injected sequencer:
+  *            map channel on the selected sequencer rank.
+  *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @note   Caution if feature ADC group injected contexts queue is enabled
+  *         (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
+  *         using successively several times this function will appear as
+  *         having no effect.
+  *         To set several features of ADC group injected, use
+  *         function @ref LL_ADC_INJ_ConfigQueueContext().
+  * @param  ADCx ADC instance
+  * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
+  assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
+  if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+  {
+    assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
+  }
+  assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
+
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if (LL_ADC_IsEnabled(ADCx) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC group injected                                                  */
+    /*    - Set ADC group injected trigger source                             */
+    /*    - Set ADC group injected sequencer length                           */
+    /*    - Set ADC group injected sequencer discontinuous mode               */
+    /*    - Set ADC group injected conversion trigger: independent or         */
+    /*      from ADC group regular                                            */
+    /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by    */
+    /*       setting of trigger source to SW start.                           */
+    if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+    {
+      MODIFY_REG(ADCx->CFGR,
+                 ADC_CFGR_JDISCEN
+                 | ADC_CFGR_JAUTO
+                 ,
+                 ADC_INJ_InitStruct->SequencerDiscont
+                 | ADC_INJ_InitStruct->TrigAuto
+                );
+    }
+    else
+    {
+      MODIFY_REG(ADCx->CFGR,
+                 ADC_CFGR_JDISCEN
+                 | ADC_CFGR_JAUTO
+                 ,
+                 LL_ADC_REG_SEQ_DISCONT_DISABLE
+                 | ADC_INJ_InitStruct->TrigAuto
+                );
+    }
+
+    MODIFY_REG(ADCx->JSQR,
+               ADC_JSQR_JEXTSEL
+               | ADC_JSQR_JEXTEN
+               | ADC_JSQR_JL
+               ,
+               ADC_INJ_InitStruct->TriggerSource
+               | ADC_INJ_InitStruct->SequencerLength
+              );
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+  * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+  *                            whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+  /* Set ADC_INJ_InitStruct fields to default values */
+  /* Set fields of ADC group injected */
+  ADC_INJ_InitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
+  ADC_INJ_InitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+  ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+  ADC_INJ_InitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c
new file mode 100644
index 0000000..c8f9fda
--- /dev/null
+++ b/squeow_sw/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c
@@ -0,0 +1,822 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_usb.c
+  * @author  MCD Application Team
+  * @brief   USB Low Layer HAL module driver.
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
+
+      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+
+  @endverbatim
+
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_LL_USB_DRIVER
+  * @{
+  */
+
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
+#if defined (USB)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Initializes the USB Core
+  * @param  USBx USB Instance
+  * @param  cfg pointer to a USB_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(cfg);
+
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EnableGlobalInt
+  *         Enables the controller's Global Int in the AHB Config reg
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
+{
+  uint32_t winterruptmask;
+
+  /* Clear pending interrupts */
+  USBx->ISTR = 0U;
+
+  /* Set winterruptmask variable */
+  winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM |
+                   USB_CNTR_SUSPM | USB_CNTR_ERRM |
+                   USB_CNTR_SOFM | USB_CNTR_ESOFM |
+                   USB_CNTR_RESETM | USB_CNTR_L1REQM;
+
+  /* Set interrupt mask */
+  USBx->CNTR = (uint16_t)winterruptmask;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DisableGlobalInt
+  *         Disable the controller's Global Int in the AHB Config reg
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
+{
+  uint32_t winterruptmask;
+
+  /* Set winterruptmask variable */
+  winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM |
+                   USB_CNTR_SUSPM | USB_CNTR_ERRM |
+                   USB_CNTR_SOFM | USB_CNTR_ESOFM |
+                   USB_CNTR_RESETM | USB_CNTR_L1REQM;
+
+  /* Clear interrupt mask */
+  USBx->CNTR &= (uint16_t)(~winterruptmask);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetCurrentMode Set functional mode
+  * @param  USBx Selected device
+  * @param  mode current core mode
+  *          This parameter can be one of the these values:
+  *            @arg USB_DEVICE_MODE Peripheral mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(USBx);
+  UNUSED(mode);
+
+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+              only by USB OTG FS peripheral.
+            - This function is added to ensure compatibility across platforms.
+   */
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevInit Initializes the USB controller registers
+  *         for device mode
+  * @param  USBx Selected device
+  * @param  cfg  pointer to a USB_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(cfg);
+
+  /* Init Device */
+  /* CNTR_FRES = 1 */
+  USBx->CNTR = (uint16_t)USB_CNTR_FRES;
+
+  /* CNTR_FRES = 0 */
+  USBx->CNTR = 0U;
+
+  /* Clear pending interrupts */
+  USBx->ISTR = 0U;
+
+  /*Set Btable Address*/
+  USBx->BTABLE = BTABLE_ADDRESS;
+
+  return HAL_OK;
+}
+
+#if defined (HAL_PCD_MODULE_ENABLED)
+/**
+  * @brief  Activate and configure an endpoint
+  * @param  USBx Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint16_t wEpRegVal;
+
+  wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
+
+  /* initialize Endpoint */
+  switch (ep->type)
+  {
+    case EP_TYPE_CTRL:
+      wEpRegVal |= USB_EP_CONTROL;
+      break;
+
+    case EP_TYPE_BULK:
+      wEpRegVal |= USB_EP_BULK;
+      break;
+
+    case EP_TYPE_INTR:
+      wEpRegVal |= USB_EP_INTERRUPT;
+      break;
+
+    case EP_TYPE_ISOC:
+      wEpRegVal |= USB_EP_ISOCHRONOUS;
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+  }
+
+  PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
+
+  PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
+
+  if (ep->doublebuffer == 0U)
+  {
+    if (ep->is_in != 0U)
+    {
+      /*Set the endpoint Transmit buffer address */
+      PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+      if (ep->type != EP_TYPE_ISOC)
+      {
+        /* Configure NAK status for the Endpoint */
+        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+      }
+      else
+      {
+        /* Configure TX Endpoint to disabled state */
+        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+      }
+    }
+    else
+    {
+      /* Set the endpoint Receive buffer address */
+      PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
+
+      /* Set the endpoint Receive buffer counter */
+      PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
+      /* Configure VALID status for the Endpoint */
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+    }
+  }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+  /* Double Buffer */
+  else
+  {
+    if (ep->type == EP_TYPE_BULK)
+    {
+      /* Set bulk endpoint as double buffered */
+      PCD_SET_BULK_EP_DBUF(USBx, ep->num);
+    }
+    else
+    {
+      /* Set the ISOC endpoint in double buffer mode */
+      PCD_CLEAR_EP_KIND(USBx, ep->num);
+    }
+
+    /* Set buffer address for double buffered mode */
+    PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
+
+    if (ep->is_in == 0U)
+    {
+      /* Clear the data toggle bits for the endpoint IN/OUT */
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+    }
+    else
+    {
+      /* Clear the data toggle bits for the endpoint IN/OUT */
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+      if (ep->type != EP_TYPE_ISOC)
+      {
+        /* Configure NAK status for the Endpoint */
+        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+      }
+      else
+      {
+        /* Configure TX Endpoint to disabled state */
+        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+      }
+
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+    }
+  }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+  return ret;
+}
+
+/**
+  * @brief  De-activate and de-initialize an endpoint
+  * @param  USBx Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+  if (ep->doublebuffer == 0U)
+  {
+    if (ep->is_in != 0U)
+    {
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+      /* Configure DISABLE status for the Endpoint */
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+    }
+
+    else
+    {
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
+      /* Configure DISABLE status for the Endpoint */
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+    }
+  }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+  /* Double Buffer */
+  else
+  {
+    if (ep->is_in == 0U)
+    {
+      /* Clear the data toggle bits for the endpoint IN/OUT*/
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+      /* Reset value of the data toggle bits for the endpoint out*/
+      PCD_TX_DTOG(USBx, ep->num);
+
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+    }
+    else
+    {
+      /* Clear the data toggle bits for the endpoint IN/OUT*/
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+      PCD_RX_DTOG(USBx, ep->num);
+
+      /* Configure DISABLE status for the Endpoint*/
+      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+    }
+  }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPStartXfer setup and starts a transfer over an EP
+  * @param  USBx Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+  uint32_t len;
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+  uint16_t pmabuffer;
+  uint16_t wEPVal;
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+  /* IN endpoint */
+  if (ep->is_in == 1U)
+  {
+    /*Multi packet transfer*/
+    if (ep->xfer_len > ep->maxpacket)
+    {
+      len = ep->maxpacket;
+    }
+    else
+    {
+      len = ep->xfer_len;
+    }
+
+    /* configure and validate Tx endpoint */
+    if (ep->doublebuffer == 0U)
+    {
+      USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
+      PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+    }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+    else
+    {
+      /* double buffer bulk management */
+      if (ep->type == EP_TYPE_BULK)
+      {
+        if (ep->xfer_len_db > ep->maxpacket)
+        {
+          /* enable double buffer */
+          PCD_SET_BULK_EP_DBUF(USBx, ep->num);
+
+          /* each Time to write in PMA xfer_len_db will */
+          ep->xfer_len_db -= len;
+
+          /* Fill the two first buffer in the Buffer0 & Buffer1 */
+          if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
+          {
+            /* Set the Double buffer counter for pmabuffer1 */
+            PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+            pmabuffer = ep->pmaaddr1;
+
+            /* Write the user buffer to USB PMA */
+            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+            ep->xfer_buff += len;
+
+            if (ep->xfer_len_db > ep->maxpacket)
+            {
+              ep->xfer_len_db -= len;
+            }
+            else
+            {
+              len = ep->xfer_len_db;
+              ep->xfer_len_db = 0U;
+            }
+
+            /* Set the Double buffer counter for pmabuffer0 */
+            PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+            pmabuffer = ep->pmaaddr0;
+
+            /* Write the user buffer to USB PMA */
+            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+          }
+          else
+          {
+            /* Set the Double buffer counter for pmabuffer0 */
+            PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+            pmabuffer = ep->pmaaddr0;
+
+            /* Write the user buffer to USB PMA */
+            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+            ep->xfer_buff += len;
+
+            if (ep->xfer_len_db > ep->maxpacket)
+            {
+              ep->xfer_len_db -= len;
+            }
+            else
+            {
+              len = ep->xfer_len_db;
+              ep->xfer_len_db = 0U;
+            }
+
+            /* Set the Double buffer counter for pmabuffer1 */
+            PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+            pmabuffer = ep->pmaaddr1;
+
+            /* Write the user buffer to USB PMA */
+            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+          }
+        }
+        /* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
+        else
+        {
+          len = ep->xfer_len_db;
+
+          /* disable double buffer mode for Bulk endpoint */
+          PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
+
+          /* Set Tx count with nbre of byte to be transmitted */
+          PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+          pmabuffer = ep->pmaaddr0;
+
+          /* Write the user buffer to USB PMA */
+          USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+        }
+      }
+      else /* manage isochronous double buffer IN mode */
+      {
+        /* each Time to write in PMA xfer_len_db will */
+        ep->xfer_len_db -= len;
+
+        /* Fill the data buffer */
+        if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
+        {
+          /* Set the Double buffer counter for pmabuffer1 */
+          PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+          pmabuffer = ep->pmaaddr1;
+
+          /* Write the user buffer to USB PMA */
+          USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+        }
+        else
+        {
+          /* Set the Double buffer counter for pmabuffer0 */
+          PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+          pmabuffer = ep->pmaaddr0;
+
+          /* Write the user buffer to USB PMA */
+          USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+        }
+      }
+    }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+    PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
+  }
+  else /* OUT endpoint */
+  {
+    if (ep->doublebuffer == 0U)
+    {
+      /* Multi packet transfer */
+      if (ep->xfer_len > ep->maxpacket)
+      {
+        len = ep->maxpacket;
+        ep->xfer_len -= len;
+      }
+      else
+      {
+        len = ep->xfer_len;
+        ep->xfer_len = 0U;
+      }
+      /* configure and validate Rx endpoint */
+      PCD_SET_EP_RX_CNT(USBx, ep->num, len);
+    }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+    else
+    {
+      /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
+      /* Set the Double buffer counter */
+      if (ep->type == EP_TYPE_BULK)
+      {
+        PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
+
+        /* Coming from ISR */
+        if (ep->xfer_count != 0U)
+        {
+          /* update last value to check if there is blocking state */
+          wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
+
+          /*Blocking State */
+          if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
+              (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
+          {
+            PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
+          }
+        }
+      }
+      /* iso out double */
+      else if (ep->type == EP_TYPE_ISOC)
+      {
+        /* Multi packet transfer */
+        if (ep->xfer_len > ep->maxpacket)
+        {
+          len = ep->maxpacket;
+          ep->xfer_len -= len;
+        }
+        else
+        {
+          len = ep->xfer_len;
+          ep->xfer_len = 0U;
+        }
+        PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
+      }
+      else
+      {
+        return HAL_ERROR;
+      }
+    }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+    PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  USB_EPSetStall set a stall condition over an EP
+  * @param  USBx Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+  if (ep->is_in != 0U)
+  {
+    PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
+  }
+  else
+  {
+    PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPClearStall Clear a stall condition over an EP
+  * @param  USBx Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+  if (ep->doublebuffer == 0U)
+  {
+    if (ep->is_in != 0U)
+    {
+      PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+      if (ep->type != EP_TYPE_ISOC)
+      {
+        /* Configure NAK status for the Endpoint */
+        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+      }
+    }
+    else
+    {
+      PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
+      /* Configure VALID status for the Endpoint */
+      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+    }
+  }
+
+  return HAL_OK;
+}
+#endif /* defined (HAL_PCD_MODULE_ENABLED) */
+
+/**
+  * @brief  USB_StopDevice Stop the usb device mode
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
+{
+  /* disable all interrupts and force USB reset */
+  USBx->CNTR = (uint16_t)USB_CNTR_FRES;
+
+  /* clear interrupt status register */
+  USBx->ISTR = 0U;
+
+  /* switch-off device */
+  USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetDevAddress Stop the usb device mode
+  * @param  USBx Selected device
+  * @param  address new device address to be assigned
+  *          This parameter can be a value from 0 to 255
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
+{
+  if (address == 0U)
+  {
+    /* set device address and enable function */
+    USBx->DADDR = (uint16_t)USB_DADDR_EF;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevConnect(USB_TypeDef *USBx)
+{
+  /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
+  USBx->BCDR |= (uint16_t)USB_BCDR_DPPU;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevDisconnect(USB_TypeDef *USBx)
+{
+  /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */
+  USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadInterrupts return the global USB interrupt status
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+uint32_t  USB_ReadInterrupts(USB_TypeDef *USBx)
+{
+  uint32_t tmpreg;
+
+  tmpreg = USBx->ISTR;
+  return tmpreg;
+}
+
+/**
+  * @brief  USB_ActivateRemoteWakeup : active remote wakeup signalling
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
+{
+  USBx->CNTR |= (uint16_t)USB_CNTR_RESUME;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
+{
+  USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Copy a buffer from user memory area to packet memory area (PMA)
+  * @param   USBx USB peripheral instance register address.
+  * @param   pbUsrBuf pointer to user memory area.
+  * @param   wPMABufAddr address into PMA.
+  * @param   wNBytes no. of bytes to be copied.
+  * @retval None
+  */
+void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+  uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
+  uint32_t BaseAddr = (uint32_t)USBx;
+  uint32_t i;
+  uint32_t temp1;
+  uint32_t temp2;
+  __IO uint16_t *pdwVal;
+  uint8_t *pBuf = pbUsrBuf;
+
+  pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
+
+  for (i = n; i != 0U; i--)
+  {
+    temp1 = *pBuf;
+    pBuf++;
+    temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8));
+    *pdwVal = (uint16_t)temp2;
+    pdwVal++;
+
+#if PMA_ACCESS > 1U
+    pdwVal++;
+#endif /* PMA_ACCESS */
+
+    pBuf++;
+  }
+}
+
+/**
+  * @brief Copy data from packet memory area (PMA) to user memory buffer
+  * @param   USBx USB peripheral instance register address.
+  * @param   pbUsrBuf pointer to user memory area.
+  * @param   wPMABufAddr address into PMA.
+  * @param   wNBytes no. of bytes to be copied.
+  * @retval None
+  */
+void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+  uint32_t n = (uint32_t)wNBytes >> 1;
+  uint32_t BaseAddr = (uint32_t)USBx;
+  uint32_t i;
+  uint32_t temp;
+  __IO uint16_t *pdwVal;
+  uint8_t *pBuf = pbUsrBuf;
+
+  pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
+
+  for (i = n; i != 0U; i--)
+  {
+    temp = *(__IO uint16_t *)pdwVal;
+    pdwVal++;
+    *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
+    pBuf++;
+    *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
+    pBuf++;
+
+#if PMA_ACCESS > 1U
+    pdwVal++;
+#endif /* PMA_ACCESS */
+  }
+
+  if ((wNBytes % 2U) != 0U)
+  {
+    temp = *pdwVal;
+    *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB) */
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
+
+/**
+  * @}
+  */
diff --git a/squeow_sw/Inc/main.h b/squeow_sw/Inc/main.h
new file mode 100644
index 0000000..a7d0bf4
--- /dev/null
+++ b/squeow_sw/Inc/main.h
@@ -0,0 +1,87 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define TEMPERATURA_Pin GPIO_PIN_4
+#define TEMPERATURA_GPIO_Port GPIOA
+#define CORRENTE_Pin GPIO_PIN_5
+#define CORRENTE_GPIO_Port GPIOA
+#define DIRETTA_Pin GPIO_PIN_6
+#define DIRETTA_GPIO_Port GPIOA
+#define RIFLESSA_Pin GPIO_PIN_7
+#define RIFLESSA_GPIO_Port GPIOA
+#define AUDIO_IN_Pin GPIO_PIN_0
+#define AUDIO_IN_GPIO_Port GPIOB
+#define T_SWDIO_Pin GPIO_PIN_13
+#define T_SWDIO_GPIO_Port GPIOA
+#define T_SWCLK_Pin GPIO_PIN_14
+#define T_SWCLK_GPIO_Port GPIOA
+#define T_SWO_Pin GPIO_PIN_3
+#define T_SWO_GPIO_Port GPIOB
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
diff --git a/squeow_sw/Inc/si5351.h b/squeow_sw/Inc/si5351.h
new file mode 100644
index 0000000..9b39b0f
--- /dev/null
+++ b/squeow_sw/Inc/si5351.h
@@ -0,0 +1,36 @@
+#define SI5351_ADDRESS		(0x60)
+
+#define SI5351_CRYSTAL_FREQ	24000000
+
+#define SI5351_MIN_FREQ		3000
+#define SI5351_MAX_FREQ		200000000
+
+// #### registri ####
+
+#define SI5351_OUT_ENABLE	3
+#define SI5351_OUT_DIS_STATE	24
+
+#define SI5351_INPUT_SOURCE	15
+
+#define	SI5351_CLK0_CONTROL	16
+#define	SI5351_CLK1_CONTROL	17
+#define	SI5351_CLK2_CONTROL	18
+
+#define SI5351_PLLA		26
+#define SI5351_PLLB		34
+
+#define SI5351_MULTISYNTH0	42
+#define SI5351_MULTISYNTH1	50
+#define SI5351_MULTISYNTH2	58
+
+#define SI5351_RESET		177
+#define SI5351_CRYSTAL_LOAD	183
+
+extern I2C_HandleTypeDef hi2c1;
+
+void si5351_initialize(void);
+void si5351_set_frequency(uint32_t freq, uint8_t pll);
+void si5351_off_clk(uint8_t clk);
+void si5351_on_clk(uint8_t clk);
+
+extern uint8_t oeb;
diff --git a/squeow_sw/Inc/squeow.h b/squeow_sw/Inc/squeow.h
new file mode 100644
index 0000000..fbdfc85
--- /dev/null
+++ b/squeow_sw/Inc/squeow.h
@@ -0,0 +1,23 @@
+#define STATO_AUDIO_DISCONNESSO		0
+#define STATO_AUDIO_CONNESSO		1
+#define STATO_AUDIO_RIPRODUZIONE	2
+#define STATO_AUDIO_TONO		3
+#define STATO_AUDIO_ADC			4
+
+#define SAMPLES_BUFFER_SIZE                (1024) ///< deve essere ^2
+#define SAMPLES_BUFFER_SIZE_MASK           (SAMPLES_BUFFER_SIZE - 1)
+#define SINE_INCREMENT                  0.314
+#define VU_DELAY                        0x3FF
+
+extern uint8_t stato_audio;
+extern char display_buffer[16];
+extern uint16_t pwm_value, sample_value;
+extern uint8_t rails_number;
+extern uint16_t samples_ringbuf[SAMPLES_BUFFER_SIZE]; ///< buffer ad anello dei dati RX
+extern uint16_t samples_ringbuf_input_index, samples_ringbuf_output_index;
+
+uint32_t sat_sub(uint16_t x, uint16_t y);
+uint16_t u16_sine(void);
+uint16_t u12_sine(void);
+void store_sample(uint16_t sample);
+void store_samples(uint16_t *data, uint16_t size);
diff --git a/squeow_sw/Inc/stm32g4xx_hal_conf.h b/squeow_sw/Inc/stm32g4xx_hal_conf.h
new file mode 100644
index 0000000..acf68d0
--- /dev/null
+++ b/squeow_sw/Inc/stm32g4xx_hal_conf.h
@@ -0,0 +1,380 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file
+  ******************************************************************************
+ * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_CONF_H
+#define STM32G4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+
+#define HAL_MODULE_ENABLED
+
+  #define HAL_ADC_MODULE_ENABLED
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CORDIC_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_DAC_MODULE_ENABLED   */
+/*#define HAL_FDCAN_MODULE_ENABLED   */
+/*#define HAL_FMAC_MODULE_ENABLED   */
+/*#define HAL_HRTIM_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+#define HAL_I2C_MODULE_ENABLED
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_NAND_MODULE_ENABLED   */
+/*#define HAL_NOR_MODULE_ENABLED   */
+/*#define HAL_OPAMP_MODULE_ENABLED   */
+#define HAL_PCD_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_SRAM_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+  * @brief This is the list of modules where register callback can be used
+  */
+#define USE_HAL_ADC_REGISTER_CALLBACKS        0U
+#define USE_HAL_COMP_REGISTER_CALLBACKS       0U
+#define USE_HAL_CORDIC_REGISTER_CALLBACKS     0U
+#define USE_HAL_CRYP_REGISTER_CALLBACKS       0U
+#define USE_HAL_DAC_REGISTER_CALLBACKS        0U
+#define USE_HAL_EXTI_REGISTER_CALLBACKS       0U
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS      0U
+#define USE_HAL_FMAC_REGISTER_CALLBACKS       0U
+#define USE_HAL_HRTIM_REGISTER_CALLBACKS      0U
+#define USE_HAL_I2C_REGISTER_CALLBACKS        0U
+#define USE_HAL_I2S_REGISTER_CALLBACKS        0U
+#define USE_HAL_IRDA_REGISTER_CALLBACKS       0U
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS      0U
+#define USE_HAL_NAND_REGISTER_CALLBACKS       0U
+#define USE_HAL_NOR_REGISTER_CALLBACKS        0U
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS      0U
+#define USE_HAL_PCD_REGISTER_CALLBACKS        0U
+#define USE_HAL_QSPI_REGISTER_CALLBACKS       0U
+#define USE_HAL_RNG_REGISTER_CALLBACKS        0U
+#define USE_HAL_RTC_REGISTER_CALLBACKS        0U
+#define USE_HAL_SAI_REGISTER_CALLBACKS        0U
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS      0U
+#define USE_HAL_SPI_REGISTER_CALLBACKS        0U
+#define USE_HAL_SRAM_REGISTER_CALLBACKS       0U
+#define USE_HAL_TIM_REGISTER_CALLBACKS        0U
+#define USE_HAL_UART_REGISTER_CALLBACKS       0U
+#define USE_HAL_USART_REGISTER_CALLBACKS      0U
+#define USE_HAL_WWDG_REGISTER_CALLBACKS       0U
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (12288000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE)
+  #define HSI48_VALUE   (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz.
+                                               The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+/*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations in voltage and temperature.*/
+#define LSI_VALUE  (32000UL)     /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  (32768UL)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    (5000UL)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S and SAI peripherals
+  *        This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    (12288000UL) /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+
+#define  VDD_VALUE                   (3300UL) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY           (0UL)    /*!< tick interrupt priority (lowest by default)  */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              0U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32g4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32g4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32g4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32g4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32g4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32g4xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+#include "stm32g4xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32g4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32g4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32g4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32g4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32g4xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32g4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+#include "stm32g4xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+#include "stm32g4xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32g4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32g4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32g4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32g4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32g4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32g4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#include "stm32g4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32g4xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32g4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32g4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+#include "stm32g4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32g4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32g4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32g4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32g4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32g4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32g4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+#include "stm32g4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32g4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32g4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32g4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32g4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_CONF_H */
diff --git a/squeow_sw/Inc/stm32g4xx_it.h b/squeow_sw/Inc/stm32g4xx_it.h
new file mode 100644
index 0000000..2501db4
--- /dev/null
+++ b/squeow_sw/Inc/stm32g4xx_it.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_IT_H
+#define __STM32G4xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USB_LP_IRQHandler(void);
+void TIM3_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_IT_H */
diff --git a/squeow_sw/Inc/usb_device.h b/squeow_sw/Inc/usb_device.h
new file mode 100644
index 0000000..c2b7fee
--- /dev/null
+++ b/squeow_sw/Inc/usb_device.h
@@ -0,0 +1,103 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usb_device.h
+  * @version        : v3.0_Cube
+  * @brief          : Header for usb_device.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_DEVICE__H__
+#define __USB_DEVICE__H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+#include "stm32g4xx_hal.h"
+#include "usbd_def.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup USBD_OTG_DRIVER
+  * @{
+  */
+
+/** @defgroup USBD_DEVICE USBD_DEVICE
+  * @brief Device file for Usb otg low level driver.
+  * @{
+  */
+
+/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/*
+ * -- Insert your variables declaration here --
+ */
+/* USER CODE BEGIN VARIABLES */
+
+/* USER CODE END VARIABLES */
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype
+  * @brief Declaration of public functions for Usb device.
+  * @{
+  */
+
+/** USB Device initialization function. */
+void MX_USB_Device_Init(void);
+
+/*
+ * -- Insert functions declaration here --
+ */
+/* USER CODE BEGIN FD */
+
+/* USER CODE END FD */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_DEVICE__H__ */
+
diff --git a/squeow_sw/Inc/usbd_audio_if.h b/squeow_sw/Inc/usbd_audio_if.h
new file mode 100644
index 0000000..16fa0f3
--- /dev/null
+++ b/squeow_sw/Inc/usbd_audio_if.h
@@ -0,0 +1,137 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_audio_if.h
+  * @version        : v3.0_Cube
+  * @brief          : Header for usbd_audio_if.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_AUDIO_IF_H__
+#define __USBD_AUDIO_IF_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_audio.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @brief For Usb device.
+  * @{
+  */
+
+/** @defgroup USBD_AUDIO_IF USBD_AUDIO_IF
+  * @brief Usb audio interface device module.
+  * @{
+  */
+
+/** @defgroup USBD_AUDIO_IF_Exported_Defines USBD_AUDIO_IF_Exported_Defines
+  * @brief Defines.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_DEFINES */
+
+/* USER CODE END EXPORTED_DEFINES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_AUDIO_IF_Exported_Types USBD_AUDIO_IF_Exported_Types
+  * @brief Types.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_TYPES */
+
+/* USER CODE END EXPORTED_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_AUDIO_IF_Exported_Macros USBD_AUDIO_IF_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_MACRO */
+
+/* USER CODE END EXPORTED_MACRO */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_AUDIO_IF_Exported_Variables USBD_AUDIO_IF_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/** AUDIO_IF Interface callback. */
+extern USBD_AUDIO_ItfTypeDef USBD_AUDIO_fops_FS;
+
+/* USER CODE BEGIN EXPORTED_VARIABLES */
+
+/* USER CODE END EXPORTED_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_AUDIO_IF_Exported_FunctionsPrototype USBD_AUDIO_IF_Exported_FunctionsPrototype
+  * @brief Public functions declaration.
+  * @{
+  */
+
+/**
+  * @brief  Manages the DMA full transfer complete event.
+  * @retval None
+  */
+void TransferComplete_CallBack_FS(void);
+
+/**
+  * @brief  Manages the DMA half transfer complete event.
+  * @retval None
+  */
+void HalfTransfer_CallBack_FS(void);
+
+/* USER CODE BEGIN EXPORTED_FUNCTIONS */
+
+/* USER CODE END EXPORTED_FUNCTIONS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_AUDIO_IF_H__ */
diff --git a/squeow_sw/Inc/usbd_conf.h b/squeow_sw/Inc/usbd_conf.h
new file mode 100644
index 0000000..c27cc22
--- /dev/null
+++ b/squeow_sw/Inc/usbd_conf.h
@@ -0,0 +1,177 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_conf.h
+  * @version        : v3.0_Cube
+  * @brief          : Header for usbd_conf.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_CONF__H__
+#define __USBD_CONF__H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "stm32g4xx.h"
+#include "stm32g4xx_hal.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup USBD_OTG_DRIVER
+  * @brief Driver for Usb device.
+  * @{
+  */
+
+/** @defgroup USBD_CONF USBD_CONF
+  * @brief Configuration file for Usb otg low level driver.
+  * @{
+  */
+
+/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+/* USER CODE END PV */
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines
+  * @brief Defines for configuration of the Usb device.
+  * @{
+  */
+
+/*---------- -----------*/
+#define USBD_MAX_NUM_INTERFACES     1U
+/*---------- -----------*/
+#define USBD_MAX_NUM_CONFIGURATION     1U
+/*---------- -----------*/
+#define USBD_MAX_STR_DESC_SIZ     512U
+/*---------- -----------*/
+#define USBD_DEBUG_LEVEL     0U
+/*---------- -----------*/
+#define USBD_LPM_ENABLED     1U
+/*---------- -----------*/
+#define USBD_SELF_POWERED     1U
+/*---------- -----------*/
+#define USBD_AUDIO_FREQ     22100U
+
+/****************************************/
+/* #define for FS and HS identification */
+#define DEVICE_FS 		0
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* Memory management macros */
+
+/** Alias for memory allocation. */
+#define USBD_malloc         (void *)USBD_static_malloc
+
+/** Alias for memory release. */
+#define USBD_free           USBD_static_free
+
+/** Alias for memory set. */
+#define USBD_memset         memset
+
+/** Alias for memory copy. */
+#define USBD_memcpy         memcpy
+
+/** Alias for delay. */
+#define USBD_Delay          HAL_Delay
+
+/* DEBUG macros */
+
+#if (USBD_DEBUG_LEVEL > 0)
+#define USBD_UsrLog(...)    printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_UsrLog(...)
+#endif
+
+#if (USBD_DEBUG_LEVEL > 1)
+
+#define USBD_ErrLog(...)    printf("ERROR: ") ;\
+                            printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_ErrLog(...)
+#endif
+
+#if (USBD_DEBUG_LEVEL > 2)
+#define USBD_DbgLog(...)    printf("DEBUG : ") ;\
+                            printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_DbgLog(...)
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types
+  * @brief Types.
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype
+  * @brief Declaration of public functions for Usb device.
+  * @{
+  */
+
+/* Exported functions -------------------------------------------------------*/
+void *USBD_static_malloc(uint32_t size);
+void USBD_static_free(void *p);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_CONF__H__ */
+
diff --git a/squeow_sw/Inc/usbd_desc.h b/squeow_sw/Inc/usbd_desc.h
new file mode 100644
index 0000000..e09caf5
--- /dev/null
+++ b/squeow_sw/Inc/usbd_desc.h
@@ -0,0 +1,143 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_desc.c
+  * @version        : v3.0_Cube
+  * @brief          : Header for usbd_conf.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_DESC__C__
+#define __USBD_DESC__C__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_def.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_DESC USBD_DESC
+  * @brief Usb device descriptors module.
+  * @{
+  */
+
+/** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants
+  * @brief Constants.
+  * @{
+  */
+#define         DEVICE_ID1          (UID_BASE)
+#define         DEVICE_ID2          (UID_BASE + 0x4)
+#define         DEVICE_ID3          (UID_BASE + 0x8)
+
+#define         USB_SIZ_STRING_SERIAL       0x1A
+
+/* USER CODE BEGIN EXPORTED_CONSTANTS */
+
+/* USER CODE END EXPORTED_CONSTANTS */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Defines USBD_DESC_Exported_Defines
+  * @brief Defines.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_DEFINES */
+
+/* USER CODE END EXPORTED_DEFINES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_TypesDefinitions USBD_DESC_Exported_TypesDefinitions
+  * @brief Types.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_TYPES */
+
+/* USER CODE END EXPORTED_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Macros USBD_DESC_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_MACRO */
+
+/* USER CODE END EXPORTED_MACRO */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Variables USBD_DESC_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+extern USBD_DescriptorsTypeDef     AUDIO_Desc;
+
+/* USER CODE BEGIN EXPORTED_VARIABLES */
+
+/* USER CODE END EXPORTED_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_FunctionsPrototype USBD_DESC_Exported_FunctionsPrototype
+  * @brief Public functions declaration.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_FUNCTIONS */
+
+/* USER CODE END EXPORTED_FUNCTIONS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_DESC__C__ */
+
diff --git a/squeow_sw/Makefile b/squeow_sw/Makefile
new file mode 100644
index 0000000..f9f61bd
--- /dev/null
+++ b/squeow_sw/Makefile
@@ -0,0 +1,210 @@
+##########################################################################################################################
+# File automatically-generated by tool: [projectgenerator] version: [3.19.2] date: [Fri Jun 30 20:08:39 CEST 2023] 
+##########################################################################################################################
+
+# ------------------------------------------------
+# Generic Makefile (based on gcc)
+#
+# ChangeLog :
+#	2017-02-10 - Several enhancements + project update mode
+#   2015-07-22 - first version
+# ------------------------------------------------
+
+######################################
+# target
+######################################
+TARGET = squeow_codice
+
+
+######################################
+# building variables
+######################################
+# debug build?
+DEBUG = 1
+# optimization
+OPT = -Og
+
+
+#######################################
+# paths
+#######################################
+# Build path
+BUILD_DIR = build
+
+######################################
+# source
+######################################
+# C sources
+C_SOURCES =  \
+Src/main.c \
+Src/squeow.c \
+Src/si5351.c \
+Src/stm32g4xx_it.c \
+Src/stm32g4xx_hal_msp.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c \
+Src/system_stm32g4xx.c \
+Src/usb_device.c \
+Src/usbd_conf.c \
+Src/usbd_desc.c \
+Src/usbd_audio_if.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c \
+Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c \
+Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \
+Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \
+Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \
+Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c
+
+# ASM sources
+ASM_SOURCES =  \
+startup_stm32g431xx.s
+
+
+#######################################
+# binaries
+#######################################
+PREFIX = arm-none-eabi-
+# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx)
+# either it can be added to the PATH environment variable.
+ifdef GCC_PATH
+CC = $(GCC_PATH)/$(PREFIX)gcc
+AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp
+CP = $(GCC_PATH)/$(PREFIX)objcopy
+SZ = $(GCC_PATH)/$(PREFIX)size
+else
+CC = $(PREFIX)gcc
+AS = $(PREFIX)gcc -x assembler-with-cpp
+CP = $(PREFIX)objcopy
+SZ = $(PREFIX)size
+endif
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary -S
+ 
+#######################################
+# CFLAGS
+#######################################
+# cpu
+CPU = -mcpu=cortex-m4
+
+# fpu
+FPU = -mfpu=fpv4-sp-d16
+
+# float-abi
+FLOAT-ABI = -mfloat-abi=hard
+
+# mcu
+MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
+
+# macros for gcc
+# AS defines
+AS_DEFS = 
+
+# C defines
+C_DEFS =  \
+-DUSE_HAL_DRIVER \
+-DSTM32G431xx
+
+
+# AS includes
+AS_INCLUDES = 
+
+# C includes
+C_INCLUDES =  \
+-IInc \
+-IDrivers/STM32G4xx_HAL_Driver/Inc \
+-IDrivers/STM32G4xx_HAL_Driver/Inc/Legacy \
+-IDrivers/CMSIS/Device/ST/STM32G4xx/Include \
+-IDrivers/CMSIS/Include \
+-IMiddlewares/ST/STM32_USB_Device_Library/Core/Inc \
+-IMiddlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc
+
+
+# compile gcc flags
+ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
+
+CFLAGS += $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
+
+ifeq ($(DEBUG), 1)
+CFLAGS += -g -gdwarf-2
+endif
+
+
+# Generate dependency information
+CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
+
+
+#######################################
+# LDFLAGS
+#######################################
+# link script
+LDSCRIPT = STM32G431KBTx_FLASH.ld
+
+# libraries
+LIBS = -lc -lm -lnosys 
+LIBDIR = 
+LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
+
+# default action: build all
+all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
+
+
+#######################################
+# build the application
+#######################################
+# list of objects
+OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
+vpath %.c $(sort $(dir $(C_SOURCES)))
+# list of ASM program objects
+OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
+vpath %.s $(sort $(dir $(ASM_SOURCES)))
+
+$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) 
+	$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
+
+$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
+	$(AS) -c $(CFLAGS) $< -o $@
+
+$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
+	$(CC) $(OBJECTS) $(LDFLAGS) -o $@
+	$(SZ) $@
+
+$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
+	$(HEX) $< $@
+	
+$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
+	$(BIN) $< $@	
+	
+$(BUILD_DIR):
+	mkdir $@		
+
+#######################################
+# clean up
+#######################################
+clean:
+	-rm -fR $(BUILD_DIR)
+  
+#######################################
+# dependencies
+#######################################
+-include $(wildcard $(BUILD_DIR)/*.d)
diff --git a/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h
new file mode 100644
index 0000000..648adda
--- /dev/null
+++ b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h
@@ -0,0 +1,218 @@
+/**
+  ******************************************************************************
+  * @file    usbd_audio.h
+  * @author  MCD Application Team
+  * @brief   header file for the usbd_audio.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_AUDIO_H
+#define __USB_AUDIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include  "usbd_ioreq.h"
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_AUDIO
+  * @brief This file is the Header file for usbd_audio.c
+  * @{
+  */
+
+
+/** @defgroup USBD_AUDIO_Exported_Defines
+  * @{
+  */
+#ifndef USBD_AUDIO_FREQ
+/* AUDIO Class Config */
+#define USBD_AUDIO_FREQ                               48000U
+#endif /* USBD_AUDIO_FREQ */
+
+#ifndef USBD_MAX_NUM_INTERFACES
+#define USBD_MAX_NUM_INTERFACES                       1U
+#endif /* USBD_AUDIO_FREQ */
+
+#ifndef AUDIO_HS_BINTERVAL
+#define AUDIO_HS_BINTERVAL                            0x01U
+#endif /* AUDIO_HS_BINTERVAL */
+
+#ifndef AUDIO_FS_BINTERVAL
+#define AUDIO_FS_BINTERVAL                            0x01U
+#endif /* AUDIO_FS_BINTERVAL */
+
+#define AUDIO_OUT_EP                                  0x01U
+#define USB_AUDIO_CONFIG_DESC_SIZ                     0x6DU
+#define AUDIO_INTERFACE_DESC_SIZE                     0x09U
+#define USB_AUDIO_DESC_SIZ                            0x09U
+#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE             0x09U
+#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE            0x07U
+
+#define AUDIO_DESCRIPTOR_TYPE                         0x21U
+#define USB_DEVICE_CLASS_AUDIO                        0x01U
+#define AUDIO_SUBCLASS_AUDIOCONTROL                   0x01U
+#define AUDIO_SUBCLASS_AUDIOSTREAMING                 0x02U
+#define AUDIO_PROTOCOL_UNDEFINED                      0x00U
+#define AUDIO_STREAMING_GENERAL                       0x01U
+#define AUDIO_STREAMING_FORMAT_TYPE                   0x02U
+
+/* Audio Descriptor Types */
+#define AUDIO_INTERFACE_DESCRIPTOR_TYPE               0x24U
+#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE                0x25U
+
+/* Audio Control Interface Descriptor Subtypes */
+#define AUDIO_CONTROL_HEADER                          0x01U
+#define AUDIO_CONTROL_INPUT_TERMINAL                  0x02U
+#define AUDIO_CONTROL_OUTPUT_TERMINAL                 0x03U
+#define AUDIO_CONTROL_FEATURE_UNIT                    0x06U
+
+#define AUDIO_INPUT_TERMINAL_DESC_SIZE                0x0CU
+#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE               0x09U
+#define AUDIO_STREAMING_INTERFACE_DESC_SIZE           0x07U
+
+#define AUDIO_CONTROL_MUTE                            0x0001U
+
+#define AUDIO_FORMAT_TYPE_I                           0x01U
+#define AUDIO_FORMAT_TYPE_III                         0x03U
+
+#define AUDIO_ENDPOINT_GENERAL                        0x01U
+
+#define AUDIO_REQ_GET_CUR                             0x81U
+#define AUDIO_REQ_SET_CUR                             0x01U
+
+#define AUDIO_OUT_STREAMING_CTRL                      0x02U
+
+#define AUDIO_OUT_TC                                  0x01U
+#define AUDIO_IN_TC                                   0x02U
+
+
+#define AUDIO_OUT_PACKET                              (uint16_t)(((USBD_AUDIO_FREQ * 2U * 2U) / 1000U))
+#define AUDIO_DEFAULT_VOLUME                          70U
+
+/* Number of sub-packets in the audio transfer buffer. You can modify this value but always make sure
+  that it is an even number and higher than 3 */
+#define AUDIO_OUT_PACKET_NUM                          80U
+/* Total size of the audio transfer buffer */
+#define AUDIO_TOTAL_BUF_SIZE                          ((uint16_t)(AUDIO_OUT_PACKET * AUDIO_OUT_PACKET_NUM))
+
+/* Audio Commands enumeration */
+typedef enum
+{
+  AUDIO_CMD_START = 1,
+  AUDIO_CMD_PLAY,
+  AUDIO_CMD_STOP,
+} AUDIO_CMD_TypeDef;
+
+
+typedef enum
+{
+  AUDIO_OFFSET_NONE = 0,
+  AUDIO_OFFSET_HALF,
+  AUDIO_OFFSET_FULL,
+  AUDIO_OFFSET_UNKNOWN,
+} AUDIO_OffsetTypeDef;
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_CORE_Exported_TypesDefinitions
+  * @{
+  */
+typedef struct
+{
+  uint8_t cmd;
+  uint8_t data[USB_MAX_EP0_SIZE];
+  uint8_t len;
+  uint8_t unit;
+} USBD_AUDIO_ControlTypeDef;
+
+
+typedef struct
+{
+  uint32_t alt_setting;
+  uint8_t buffer[AUDIO_TOTAL_BUF_SIZE];
+  AUDIO_OffsetTypeDef offset;
+  uint8_t rd_enable;
+  uint16_t rd_ptr;
+  uint16_t wr_ptr;
+  USBD_AUDIO_ControlTypeDef control;
+} USBD_AUDIO_HandleTypeDef;
+
+
+typedef struct
+{
+  int8_t (*Init)(uint32_t AudioFreq, uint32_t Volume, uint32_t options);
+  int8_t (*DeInit)(uint32_t options);
+  int8_t (*AudioCmd)(uint8_t *pbuf, uint32_t size, uint8_t cmd);
+  int8_t (*VolumeCtl)(uint8_t vol);
+  int8_t (*MuteCtl)(uint8_t cmd);
+  int8_t (*PeriodicTC)(uint8_t *pbuf, uint32_t size, uint8_t cmd);
+  int8_t (*GetState)(void);
+} USBD_AUDIO_ItfTypeDef;
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_CORE_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CORE_Exported_Variables
+  * @{
+  */
+
+extern USBD_ClassTypeDef USBD_AUDIO;
+#define USBD_AUDIO_CLASS &USBD_AUDIO
+/**
+  * @}
+  */
+
+/** @defgroup USB_CORE_Exported_Functions
+  * @{
+  */
+uint8_t USBD_AUDIO_RegisterInterface(USBD_HandleTypeDef *pdev,
+                                     USBD_AUDIO_ItfTypeDef *fops);
+
+void USBD_AUDIO_Sync(USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __USB_AUDIO_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c
new file mode 100644
index 0000000..6f1b085
--- /dev/null
+++ b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c
@@ -0,0 +1,873 @@
+/**
+  ******************************************************************************
+  * @file    usbd_audio.c
+  * @author  MCD Application Team
+  * @brief   This file provides the Audio core functions.
+  *
+  * @verbatim
+  *
+  *          ===================================================================
+  *                                AUDIO Class  Description
+  *          ===================================================================
+  *           This driver manages the Audio Class 1.0 following the "USB Device Class Definition for
+  *           Audio Devices V1.0 Mar 18, 98".
+  *           This driver implements the following aspects of the specification:
+  *             - Device descriptor management
+  *             - Configuration descriptor management
+  *             - Standard AC Interface Descriptor management
+  *             - 1 Audio Streaming Interface (with single channel, PCM, Stereo mode)
+  *             - 1 Audio Streaming Endpoint
+  *             - 1 Audio Terminal Input (1 channel)
+  *             - Audio Class-Specific AC Interfaces
+  *             - Audio Class-Specific AS Interfaces
+  *             - AudioControl Requests: only SET_CUR and GET_CUR requests are supported (for Mute)
+  *             - Audio Feature Unit (limited to Mute control)
+  *             - Audio Synchronization type: Asynchronous
+  *             - Single fixed audio sampling rate (configurable in usbd_conf.h file)
+  *          The current audio class version supports the following audio features:
+  *             - Pulse Coded Modulation (PCM) format
+  *             - sampling rate: 48KHz.
+  *             - Bit resolution: 16
+  *             - Number of channels: 2
+  *             - No volume control
+  *             - Mute/Unmute capability
+  *             - Asynchronous Endpoints
+  *
+  * @note     In HS mode and when the DMA is used, all variables and data structures
+  *           dealing with the DMA during the transaction process should be 32-bit aligned.
+  *
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* BSPDependencies
+- "stm32xxxxx_{eval}{discovery}.c"
+- "stm32xxxxx_{eval}{discovery}_io.c"
+- "stm32xxxxx_{eval}{discovery}_audio.c"
+EndBSPDependencies */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_audio.h"
+#include "usbd_ctlreq.h"
+
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+
+/** @defgroup USBD_AUDIO
+  * @brief usbd core module
+  * @{
+  */
+
+/** @defgroup USBD_AUDIO_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_AUDIO_Private_Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_AUDIO_Private_Macros
+  * @{
+  */
+#define AUDIO_SAMPLE_FREQ(frq)         (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16))
+
+#define AUDIO_PACKET_SZE(frq)          (uint8_t)(((frq * 2U * 2U)/1000U) & 0xFFU), \
+                                       (uint8_t)((((frq * 2U * 2U)/1000U) >> 8) & 0xFFU)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_AUDIO_Private_FunctionPrototypes
+  * @{
+  */
+static uint8_t USBD_AUDIO_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+static uint8_t USBD_AUDIO_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+
+static uint8_t USBD_AUDIO_Setup(USBD_HandleTypeDef *pdev,
+                                USBD_SetupReqTypedef *req);
+
+static uint8_t *USBD_AUDIO_GetCfgDesc(uint16_t *length);
+static uint8_t *USBD_AUDIO_GetDeviceQualifierDesc(uint16_t *length);
+static uint8_t USBD_AUDIO_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum);
+static uint8_t USBD_AUDIO_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum);
+static uint8_t USBD_AUDIO_EP0_RxReady(USBD_HandleTypeDef *pdev);
+static uint8_t USBD_AUDIO_EP0_TxReady(USBD_HandleTypeDef *pdev);
+static uint8_t USBD_AUDIO_SOF(USBD_HandleTypeDef *pdev);
+
+static uint8_t USBD_AUDIO_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
+static uint8_t USBD_AUDIO_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
+static void AUDIO_REQ_GetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+static void AUDIO_REQ_SetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_AUDIO_Private_Variables
+  * @{
+  */
+
+USBD_ClassTypeDef USBD_AUDIO =
+{
+  USBD_AUDIO_Init,
+  USBD_AUDIO_DeInit,
+  USBD_AUDIO_Setup,
+  USBD_AUDIO_EP0_TxReady,
+  USBD_AUDIO_EP0_RxReady,
+  USBD_AUDIO_DataIn,
+  USBD_AUDIO_DataOut,
+  USBD_AUDIO_SOF,
+  USBD_AUDIO_IsoINIncomplete,
+  USBD_AUDIO_IsoOutIncomplete,
+  USBD_AUDIO_GetCfgDesc,
+  USBD_AUDIO_GetCfgDesc,
+  USBD_AUDIO_GetCfgDesc,
+  USBD_AUDIO_GetDeviceQualifierDesc,
+};
+
+/* USB AUDIO device Configuration Descriptor */
+__ALIGN_BEGIN static uint8_t USBD_AUDIO_CfgDesc[USB_AUDIO_CONFIG_DESC_SIZ] __ALIGN_END =
+{
+  /* Configuration 1 */
+  0x09,                                 /* bLength */
+  USB_DESC_TYPE_CONFIGURATION,          /* bDescriptorType */
+  LOBYTE(USB_AUDIO_CONFIG_DESC_SIZ),    /* wTotalLength  109 bytes*/
+  HIBYTE(USB_AUDIO_CONFIG_DESC_SIZ),
+  0x02,                                 /* bNumInterfaces */
+  0x01,                                 /* bConfigurationValue */
+  0x00,                                 /* iConfiguration */
+#if (USBD_SELF_POWERED == 1U)
+  0xC0,                                 /* bmAttributes: Bus Powered according to user configuration */
+#else
+  0x80,                                 /* bmAttributes: Bus Powered according to user configuration */
+#endif
+  USBD_MAX_POWER,                       /* bMaxPower = 100 mA */
+  /* 09 byte*/
+
+  /* USB Speaker Standard interface descriptor */
+  AUDIO_INTERFACE_DESC_SIZE,            /* bLength */
+  USB_DESC_TYPE_INTERFACE,              /* bDescriptorType */
+  0x00,                                 /* bInterfaceNumber */
+  0x00,                                 /* bAlternateSetting */
+  0x00,                                 /* bNumEndpoints */
+  USB_DEVICE_CLASS_AUDIO,               /* bInterfaceClass */
+  AUDIO_SUBCLASS_AUDIOCONTROL,          /* bInterfaceSubClass */
+  AUDIO_PROTOCOL_UNDEFINED,             /* bInterfaceProtocol */
+  0x00,                                 /* iInterface */
+  /* 09 byte*/
+
+  /* USB Speaker Class-specific AC Interface Descriptor */
+  AUDIO_INTERFACE_DESC_SIZE,            /* bLength */
+  AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+  AUDIO_CONTROL_HEADER,                 /* bDescriptorSubtype */
+  0x00,          /* 1.00 */             /* bcdADC */
+  0x01,
+  0x27,                                 /* wTotalLength = 39*/
+  0x00,
+  0x01,                                 /* bInCollection */
+  0x01,                                 /* baInterfaceNr */
+  /* 09 byte*/
+
+  /* USB Speaker Input Terminal Descriptor */
+  AUDIO_INPUT_TERMINAL_DESC_SIZE,       /* bLength */
+  AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+  AUDIO_CONTROL_INPUT_TERMINAL,         /* bDescriptorSubtype */
+  0x01,                                 /* bTerminalID */
+  0x01,                                 /* wTerminalType AUDIO_TERMINAL_USB_STREAMING   0x0101 */
+  0x01,
+  0x00,                                 /* bAssocTerminal */
+  0x01,                                 /* bNrChannels */
+  0x00,                                 /* wChannelConfig 0x0000  Mono */
+  0x00,
+  0x00,                                 /* iChannelNames */
+  0x00,                                 /* iTerminal */
+  /* 12 byte*/
+
+  /* USB Speaker Audio Feature Unit Descriptor */
+  0x09,                                 /* bLength */
+  AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+  AUDIO_CONTROL_FEATURE_UNIT,           /* bDescriptorSubtype */
+  AUDIO_OUT_STREAMING_CTRL,             /* bUnitID */
+  0x01,                                 /* bSourceID */
+  0x01,                                 /* bControlSize */
+  AUDIO_CONTROL_MUTE,                   /* bmaControls(0) */
+  0,                                    /* bmaControls(1) */
+  0x00,                                 /* iTerminal */
+  /* 09 byte*/
+
+  /*USB Speaker Output Terminal Descriptor */
+  0x09,      /* bLength */
+  AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+  AUDIO_CONTROL_OUTPUT_TERMINAL,        /* bDescriptorSubtype */
+  0x03,                                 /* bTerminalID */
+  0x01,                                 /* wTerminalType  0x0301*/
+  0x03,
+  0x00,                                 /* bAssocTerminal */
+  0x02,                                 /* bSourceID */
+  0x00,                                 /* iTerminal */
+  /* 09 byte*/
+
+  /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Zero Bandwidth */
+  /* Interface 1, Alternate Setting 0                                             */
+  AUDIO_INTERFACE_DESC_SIZE,            /* bLength */
+  USB_DESC_TYPE_INTERFACE,              /* bDescriptorType */
+  0x01,                                 /* bInterfaceNumber */
+  0x00,                                 /* bAlternateSetting */
+  0x00,                                 /* bNumEndpoints */
+  USB_DEVICE_CLASS_AUDIO,               /* bInterfaceClass */
+  AUDIO_SUBCLASS_AUDIOSTREAMING,        /* bInterfaceSubClass */
+  AUDIO_PROTOCOL_UNDEFINED,             /* bInterfaceProtocol */
+  0x00,                                 /* iInterface */
+  /* 09 byte*/
+
+  /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Operational */
+  /* Interface 1, Alternate Setting 1                                           */
+  AUDIO_INTERFACE_DESC_SIZE,            /* bLength */
+  USB_DESC_TYPE_INTERFACE,              /* bDescriptorType */
+  0x01,                                 /* bInterfaceNumber */
+  0x01,                                 /* bAlternateSetting */
+  0x01,                                 /* bNumEndpoints */
+  USB_DEVICE_CLASS_AUDIO,               /* bInterfaceClass */
+  AUDIO_SUBCLASS_AUDIOSTREAMING,        /* bInterfaceSubClass */
+  AUDIO_PROTOCOL_UNDEFINED,             /* bInterfaceProtocol */
+  0x00,                                 /* iInterface */
+  /* 09 byte*/
+
+  /* USB Speaker Audio Streaming Interface Descriptor */
+  AUDIO_STREAMING_INTERFACE_DESC_SIZE,  /* bLength */
+  AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+  AUDIO_STREAMING_GENERAL,              /* bDescriptorSubtype */
+  0x01,                                 /* bTerminalLink */
+  0x01,                                 /* bDelay */
+  0x01,                                 /* wFormatTag AUDIO_FORMAT_PCM  0x0001 */
+  0x00,
+  /* 07 byte*/
+
+  /* USB Speaker Audio Type III Format Interface Descriptor */
+  0x0B,                                 /* bLength */
+  AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+  AUDIO_STREAMING_FORMAT_TYPE,          /* bDescriptorSubtype */
+  AUDIO_FORMAT_TYPE_I,                  /* bFormatType */
+  0x02,                                 /* bNrChannels */
+  0x02,                                 /* bSubFrameSize :  2 Bytes per frame (16bits) */
+  16,                                   /* bBitResolution (16-bits per sample) */
+  0x01,                                 /* bSamFreqType only one frequency supported */
+  AUDIO_SAMPLE_FREQ(USBD_AUDIO_FREQ),   /* Audio sampling frequency coded on 3 bytes */
+  /* 11 byte*/
+
+  /* Endpoint 1 - Standard Descriptor */
+  AUDIO_STANDARD_ENDPOINT_DESC_SIZE,    /* bLength */
+  USB_DESC_TYPE_ENDPOINT,               /* bDescriptorType */
+  AUDIO_OUT_EP,                         /* bEndpointAddress 1 out endpoint */
+  USBD_EP_TYPE_ISOC,                    /* bmAttributes */
+  AUDIO_PACKET_SZE(USBD_AUDIO_FREQ),    /* wMaxPacketSize in Bytes (Freq(Samples)*2(Stereo)*2(HalfWord)) */
+  AUDIO_FS_BINTERVAL,                   /* bInterval */
+  0x00,                                 /* bRefresh */
+  0x00,                                 /* bSynchAddress */
+  /* 09 byte*/
+
+  /* Endpoint - Audio Streaming Descriptor*/
+  AUDIO_STREAMING_ENDPOINT_DESC_SIZE,   /* bLength */
+  AUDIO_ENDPOINT_DESCRIPTOR_TYPE,       /* bDescriptorType */
+  AUDIO_ENDPOINT_GENERAL,               /* bDescriptor */
+  0x00,                                 /* bmAttributes */
+  0x00,                                 /* bLockDelayUnits */
+  0x00,                                 /* wLockDelay */
+  0x00,
+  /* 07 byte*/
+} ;
+
+/* USB Standard Device Descriptor */
+__ALIGN_BEGIN static uint8_t USBD_AUDIO_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
+{
+  USB_LEN_DEV_QUALIFIER_DESC,
+  USB_DESC_TYPE_DEVICE_QUALIFIER,
+  0x00,
+  0x02,
+  0x00,
+  0x00,
+  0x00,
+  0x40,
+  0x01,
+  0x00,
+};
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_AUDIO_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  USBD_AUDIO_Init
+  *         Initialize the AUDIO interface
+  * @param  pdev: device instance
+  * @param  cfgidx: Configuration index
+  * @retval status
+  */
+static uint8_t USBD_AUDIO_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
+{
+  UNUSED(cfgidx);
+  USBD_AUDIO_HandleTypeDef *haudio;
+
+  /* Allocate Audio structure */
+  haudio = USBD_malloc(sizeof(USBD_AUDIO_HandleTypeDef));
+
+  if (haudio == NULL)
+  {
+    pdev->pClassData = NULL;
+    return (uint8_t)USBD_EMEM;
+  }
+
+  pdev->pClassData = (void *)haudio;
+
+  if (pdev->dev_speed == USBD_SPEED_HIGH)
+  {
+    pdev->ep_out[AUDIO_OUT_EP & 0xFU].bInterval = AUDIO_HS_BINTERVAL;
+  }
+  else   /* LOW and FULL-speed endpoints */
+  {
+    pdev->ep_out[AUDIO_OUT_EP & 0xFU].bInterval = AUDIO_FS_BINTERVAL;
+  }
+
+  /* Open EP OUT */
+  (void)USBD_LL_OpenEP(pdev, AUDIO_OUT_EP, USBD_EP_TYPE_ISOC, AUDIO_OUT_PACKET);
+  pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 1U;
+
+  haudio->alt_setting = 0U;
+  haudio->offset = AUDIO_OFFSET_UNKNOWN;
+  haudio->wr_ptr = 0U;
+  haudio->rd_ptr = 0U;
+  haudio->rd_enable = 0U;
+
+  /* Initialize the Audio output Hardware layer */
+  if (((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->Init(USBD_AUDIO_FREQ,
+                                                       AUDIO_DEFAULT_VOLUME,
+                                                       0U) != 0U)
+  {
+    return (uint8_t)USBD_FAIL;
+  }
+
+  /* Prepare Out endpoint to receive 1st packet */
+  (void)USBD_LL_PrepareReceive(pdev, AUDIO_OUT_EP, haudio->buffer,
+                               AUDIO_OUT_PACKET);
+
+  return (uint8_t)USBD_OK;
+}
+
+/**
+  * @brief  USBD_AUDIO_Init
+  *         DeInitialize the AUDIO layer
+  * @param  pdev: device instance
+  * @param  cfgidx: Configuration index
+  * @retval status
+  */
+static uint8_t USBD_AUDIO_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
+{
+  UNUSED(cfgidx);
+
+  /* Open EP OUT */
+  (void)USBD_LL_CloseEP(pdev, AUDIO_OUT_EP);
+  pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 0U;
+  pdev->ep_out[AUDIO_OUT_EP & 0xFU].bInterval = 0U;
+
+  /* DeInit  physical Interface components */
+  if (pdev->pClassData != NULL)
+  {
+    ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->DeInit(0U);
+    (void)USBD_free(pdev->pClassData);
+    pdev->pClassData = NULL;
+  }
+
+  return (uint8_t)USBD_OK;
+}
+
+/**
+  * @brief  USBD_AUDIO_Setup
+  *         Handle the AUDIO specific requests
+  * @param  pdev: instance
+  * @param  req: usb requests
+  * @retval status
+  */
+static uint8_t USBD_AUDIO_Setup(USBD_HandleTypeDef *pdev,
+                                USBD_SetupReqTypedef *req)
+{
+  USBD_AUDIO_HandleTypeDef *haudio;
+  uint16_t len;
+  uint8_t *pbuf;
+  uint16_t status_info = 0U;
+  USBD_StatusTypeDef ret = USBD_OK;
+
+  haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+
+  if (haudio == NULL)
+  {
+    return (uint8_t)USBD_FAIL;
+  }
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
+  {
+    case USB_REQ_TYPE_CLASS:
+      switch (req->bRequest)
+      {
+        case AUDIO_REQ_GET_CUR:
+          AUDIO_REQ_GetCurrent(pdev, req);
+          break;
+
+        case AUDIO_REQ_SET_CUR:
+          AUDIO_REQ_SetCurrent(pdev, req);
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          ret = USBD_FAIL;
+          break;
+      }
+      break;
+
+    case USB_REQ_TYPE_STANDARD:
+      switch (req->bRequest)
+      {
+        case USB_REQ_GET_STATUS:
+          if (pdev->dev_state == USBD_STATE_CONFIGURED)
+          {
+            (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            ret = USBD_FAIL;
+          }
+          break;
+
+        case USB_REQ_GET_DESCRIPTOR:
+          if ((req->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE)
+          {
+            pbuf = USBD_AUDIO_CfgDesc + 18;
+            len = MIN(USB_AUDIO_DESC_SIZ, req->wLength);
+
+            (void)USBD_CtlSendData(pdev, pbuf, len);
+          }
+          break;
+
+        case USB_REQ_GET_INTERFACE:
+          if (pdev->dev_state == USBD_STATE_CONFIGURED)
+          {
+            (void)USBD_CtlSendData(pdev, (uint8_t *)&haudio->alt_setting, 1U);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            ret = USBD_FAIL;
+          }
+          break;
+
+        case USB_REQ_SET_INTERFACE:
+          if (pdev->dev_state == USBD_STATE_CONFIGURED)
+          {
+            if ((uint8_t)(req->wValue) <= USBD_MAX_NUM_INTERFACES)
+            {
+              haudio->alt_setting = (uint8_t)(req->wValue);
+            }
+            else
+            {
+              /* Call the error management function (command will be NAKed */
+              USBD_CtlError(pdev, req);
+              ret = USBD_FAIL;
+            }
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            ret = USBD_FAIL;
+          }
+          break;
+
+        case USB_REQ_CLEAR_FEATURE:
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          ret = USBD_FAIL;
+          break;
+      }
+      break;
+    default:
+      USBD_CtlError(pdev, req);
+      ret = USBD_FAIL;
+      break;
+  }
+
+  return (uint8_t)ret;
+}
+
+
+/**
+  * @brief  USBD_AUDIO_GetCfgDesc
+  *         return configuration descriptor
+  * @param  speed : current device speed
+  * @param  length : pointer data length
+  * @retval pointer to descriptor buffer
+  */
+static uint8_t *USBD_AUDIO_GetCfgDesc(uint16_t *length)
+{
+  *length = (uint16_t)sizeof(USBD_AUDIO_CfgDesc);
+
+  return USBD_AUDIO_CfgDesc;
+}
+
+/**
+  * @brief  USBD_AUDIO_DataIn
+  *         handle data IN Stage
+  * @param  pdev: device instance
+  * @param  epnum: endpoint index
+  * @retval status
+  */
+static uint8_t USBD_AUDIO_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
+{
+  UNUSED(pdev);
+  UNUSED(epnum);
+
+  /* Only OUT data are processed */
+  return (uint8_t)USBD_OK;
+}
+
+/**
+  * @brief  USBD_AUDIO_EP0_RxReady
+  *         handle EP0 Rx Ready event
+  * @param  pdev: device instance
+  * @retval status
+  */
+static uint8_t USBD_AUDIO_EP0_RxReady(USBD_HandleTypeDef *pdev)
+{
+  USBD_AUDIO_HandleTypeDef *haudio;
+  haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+
+  if (haudio == NULL)
+  {
+    return (uint8_t)USBD_FAIL;
+  }
+
+  if (haudio->control.cmd == AUDIO_REQ_SET_CUR)
+  {
+    /* In this driver, to simplify code, only SET_CUR request is managed */
+
+    if (haudio->control.unit == AUDIO_OUT_STREAMING_CTRL)
+    {
+      ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->MuteCtl(haudio->control.data[0]);
+      haudio->control.cmd = 0U;
+      haudio->control.len = 0U;
+    }
+  }
+
+  return (uint8_t)USBD_OK;
+}
+/**
+  * @brief  USBD_AUDIO_EP0_TxReady
+  *         handle EP0 TRx Ready event
+  * @param  pdev: device instance
+  * @retval status
+  */
+static uint8_t USBD_AUDIO_EP0_TxReady(USBD_HandleTypeDef *pdev)
+{
+  UNUSED(pdev);
+
+  /* Only OUT control data are processed */
+  return (uint8_t)USBD_OK;
+}
+/**
+  * @brief  USBD_AUDIO_SOF
+  *         handle SOF event
+  * @param  pdev: device instance
+  * @retval status
+  */
+static uint8_t USBD_AUDIO_SOF(USBD_HandleTypeDef *pdev)
+{
+  UNUSED(pdev);
+
+  return (uint8_t)USBD_OK;
+}
+
+/**
+  * @brief  USBD_AUDIO_SOF
+  *         handle SOF event
+  * @param  pdev: device instance
+  * @retval status
+  */
+void USBD_AUDIO_Sync(USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset)
+{
+  USBD_AUDIO_HandleTypeDef *haudio;
+  uint32_t BufferSize = AUDIO_TOTAL_BUF_SIZE / 2U;
+
+  if (pdev->pClassData == NULL)
+  {
+    return;
+  }
+
+  haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+
+  haudio->offset = offset;
+
+  if (haudio->rd_enable == 1U)
+  {
+    haudio->rd_ptr += (uint16_t)BufferSize;
+
+    if (haudio->rd_ptr == AUDIO_TOTAL_BUF_SIZE)
+    {
+      /* roll back */
+      haudio->rd_ptr = 0U;
+    }
+  }
+
+  if (haudio->rd_ptr > haudio->wr_ptr)
+  {
+    if ((haudio->rd_ptr - haudio->wr_ptr) < AUDIO_OUT_PACKET)
+    {
+      BufferSize += 4U;
+    }
+    else
+    {
+      if ((haudio->rd_ptr - haudio->wr_ptr) > (AUDIO_TOTAL_BUF_SIZE - AUDIO_OUT_PACKET))
+      {
+        BufferSize -= 4U;
+      }
+    }
+  }
+  else
+  {
+    if ((haudio->wr_ptr - haudio->rd_ptr) < AUDIO_OUT_PACKET)
+    {
+      BufferSize -= 4U;
+    }
+    else
+    {
+      if ((haudio->wr_ptr - haudio->rd_ptr) > (AUDIO_TOTAL_BUF_SIZE - AUDIO_OUT_PACKET))
+      {
+        BufferSize += 4U;
+      }
+    }
+  }
+
+  if (haudio->offset == AUDIO_OFFSET_FULL)
+  {
+    ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->AudioCmd(&haudio->buffer[0],
+                                                         BufferSize, AUDIO_CMD_PLAY);
+    haudio->offset = AUDIO_OFFSET_NONE;
+  }
+}
+
+/**
+  * @brief  USBD_AUDIO_IsoINIncomplete
+  *         handle data ISO IN Incomplete event
+  * @param  pdev: device instance
+  * @param  epnum: endpoint index
+  * @retval status
+  */
+static uint8_t USBD_AUDIO_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum)
+{
+  UNUSED(pdev);
+  UNUSED(epnum);
+
+  return (uint8_t)USBD_OK;
+}
+/**
+  * @brief  USBD_AUDIO_IsoOutIncomplete
+  *         handle data ISO OUT Incomplete event
+  * @param  pdev: device instance
+  * @param  epnum: endpoint index
+  * @retval status
+  */
+static uint8_t USBD_AUDIO_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum)
+{
+  UNUSED(pdev);
+  UNUSED(epnum);
+
+  return (uint8_t)USBD_OK;
+}
+/**
+  * @brief  USBD_AUDIO_DataOut
+  *         handle data OUT Stage
+  * @param  pdev: device instance
+  * @param  epnum: endpoint index
+  * @retval status
+  */
+static uint8_t USBD_AUDIO_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
+{
+  uint16_t PacketSize;
+  USBD_AUDIO_HandleTypeDef *haudio;
+
+  haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+
+  if (haudio == NULL)
+  {
+    return (uint8_t)USBD_FAIL;
+  }
+
+  if (epnum == AUDIO_OUT_EP)
+  {
+    /* Get received data packet length */
+    PacketSize = (uint16_t)USBD_LL_GetRxDataSize(pdev, epnum);
+
+    /* Packet received Callback */
+    ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->PeriodicTC(&haudio->buffer[haudio->wr_ptr],
+                                                           PacketSize, AUDIO_OUT_TC);
+
+    /* Increment the Buffer pointer or roll it back when all buffers are full */
+    haudio->wr_ptr += PacketSize;
+
+    if (haudio->wr_ptr == AUDIO_TOTAL_BUF_SIZE)
+    {
+      /* All buffers are full: roll back */
+      haudio->wr_ptr = 0U;
+
+      if (haudio->offset == AUDIO_OFFSET_UNKNOWN)
+      {
+        ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->AudioCmd(&haudio->buffer[0],
+                                                             AUDIO_TOTAL_BUF_SIZE / 2U,
+                                                             AUDIO_CMD_START);
+        haudio->offset = AUDIO_OFFSET_NONE;
+      }
+    }
+
+    if (haudio->rd_enable == 0U)
+    {
+      if (haudio->wr_ptr == (AUDIO_TOTAL_BUF_SIZE / 2U))
+      {
+        haudio->rd_enable = 1U;
+      }
+    }
+
+    /* Prepare Out endpoint to receive next audio packet */
+    (void)USBD_LL_PrepareReceive(pdev, AUDIO_OUT_EP,
+                                 &haudio->buffer[haudio->wr_ptr],
+                                 AUDIO_OUT_PACKET);
+  }
+
+  return (uint8_t)USBD_OK;
+}
+
+/**
+  * @brief  AUDIO_Req_GetCurrent
+  *         Handles the GET_CUR Audio control request.
+  * @param  pdev: instance
+  * @param  req: setup class request
+  * @retval status
+  */
+static void AUDIO_REQ_GetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  USBD_AUDIO_HandleTypeDef *haudio;
+  haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+
+  if (haudio == NULL)
+  {
+    return;
+  }
+
+  (void)USBD_memset(haudio->control.data, 0, 64U);
+
+  /* Send the current mute state */
+  (void)USBD_CtlSendData(pdev, haudio->control.data, req->wLength);
+}
+
+/**
+  * @brief  AUDIO_Req_SetCurrent
+  *         Handles the SET_CUR Audio control request.
+  * @param  pdev: instance
+  * @param  req: setup class request
+  * @retval status
+  */
+static void AUDIO_REQ_SetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  USBD_AUDIO_HandleTypeDef *haudio;
+  haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+
+  if (haudio == NULL)
+  {
+    return;
+  }
+
+  if (req->wLength != 0U)
+  {
+    /* Prepare the reception of the buffer over EP0 */
+    (void)USBD_CtlPrepareRx(pdev, haudio->control.data, req->wLength);
+
+    haudio->control.cmd = AUDIO_REQ_SET_CUR;     /* Set the request value */
+    haudio->control.len = (uint8_t)req->wLength; /* Set the request data length */
+    haudio->control.unit = HIBYTE(req->wIndex);  /* Set the request target unit */
+  }
+}
+
+
+/**
+  * @brief  DeviceQualifierDescriptor
+  *         return Device Qualifier descriptor
+  * @param  length : pointer data length
+  * @retval pointer to descriptor buffer
+  */
+static uint8_t *USBD_AUDIO_GetDeviceQualifierDesc(uint16_t *length)
+{
+  *length = (uint16_t)sizeof(USBD_AUDIO_DeviceQualifierDesc);
+
+  return USBD_AUDIO_DeviceQualifierDesc;
+}
+
+/**
+  * @brief  USBD_AUDIO_RegisterInterface
+  * @param  fops: Audio interface callback
+  * @retval status
+  */
+uint8_t USBD_AUDIO_RegisterInterface(USBD_HandleTypeDef *pdev,
+                                     USBD_AUDIO_ItfTypeDef *fops)
+{
+  if (fops == NULL)
+  {
+    return (uint8_t)USBD_FAIL;
+  }
+
+  pdev->pUserData = fops;
+
+  return (uint8_t)USBD_OK;
+}
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h
new file mode 100644
index 0000000..3f9dedb
--- /dev/null
+++ b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h
@@ -0,0 +1,158 @@
+/**
+  ******************************************************************************
+  * @file    usbd_core.h
+  * @author  MCD Application Team
+  * @brief   Header file for usbd_core.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_CORE_H
+#define __USBD_CORE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_conf.h"
+#include "usbd_def.h"
+#include "usbd_ioreq.h"
+#include "usbd_ctlreq.h"
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_CORE
+  * @brief This file is the Header file for usbd_core.c file
+  * @{
+  */
+
+
+/** @defgroup USBD_CORE_Exported_Defines
+  * @{
+  */
+#ifndef USBD_DEBUG_LEVEL
+#define USBD_DEBUG_LEVEL           0U
+#endif /* USBD_DEBUG_LEVEL */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_CORE_Exported_TypesDefinitions
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_CORE_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CORE_Exported_Variables
+  * @{
+  */
+#define USBD_SOF          USBD_LL_SOF
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CORE_Exported_FunctionsPrototype
+  * @{
+  */
+USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id);
+USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass);
+
+USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+
+USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup);
+USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
+USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
+
+USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed);
+USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev);
+
+USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
+USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
+
+USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev);
+
+/* USBD Low Level Driver */
+USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev);
+
+USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
+                                  uint8_t ep_type, uint16_t ep_mps);
+
+USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr);
+
+USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
+                                    uint8_t *pbuf, uint32_t size);
+
+USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
+                                          uint8_t *pbuf, uint32_t size);
+
+uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t  ep_addr);
+
+void  USBD_LL_Delay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_CORE_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
diff --git a/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
new file mode 100644
index 0000000..4239126
--- /dev/null
+++ b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
@@ -0,0 +1,103 @@
+/**
+  ******************************************************************************
+  * @file    usbd_req.h
+  * @author  MCD Application Team
+  * @brief   Header file for the usbd_req.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_REQUEST_H
+#define __USB_REQUEST_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include  "usbd_def.h"
+
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_REQ
+  * @brief header file for the usbd_req.c file
+  * @{
+  */
+
+/** @defgroup USBD_REQ_Exported_Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Exported_Types
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_REQ_Exported_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBD_REQ_Exported_Variables
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBD_REQ_Exported_FunctionsPrototype
+  * @{
+  */
+
+USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+
+void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata);
+void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_REQUEST_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h
new file mode 100644
index 0000000..e88f995
--- /dev/null
+++ b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h
@@ -0,0 +1,420 @@
+/**
+  ******************************************************************************
+  * @file    usbd_def.h
+  * @author  MCD Application Team
+  * @brief   General defines for the usb device library
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_DEF_H
+#define __USBD_DEF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_conf.h"
+
+/** @addtogroup STM32_USBD_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USB_DEF
+  * @brief general defines for the usb device library file
+  * @{
+  */
+
+/** @defgroup USB_DEF_Exported_Defines
+  * @{
+  */
+
+#ifndef NULL
+#define NULL                                            0U
+#endif /* NULL */
+
+#ifndef USBD_MAX_NUM_INTERFACES
+#define USBD_MAX_NUM_INTERFACES                         1U
+#endif /* USBD_MAX_NUM_CONFIGURATION */
+
+#ifndef USBD_MAX_NUM_CONFIGURATION
+#define USBD_MAX_NUM_CONFIGURATION                      1U
+#endif /* USBD_MAX_NUM_CONFIGURATION */
+
+#ifndef USBD_LPM_ENABLED
+#define USBD_LPM_ENABLED                                0U
+#endif /* USBD_LPM_ENABLED */
+
+#ifndef USBD_SELF_POWERED
+#define USBD_SELF_POWERED                               1U
+#endif /*USBD_SELF_POWERED */
+
+#ifndef USBD_MAX_POWER
+#define USBD_MAX_POWER                                  0x32U /* 100 mA */
+#endif /* USBD_MAX_POWER */
+
+#ifndef USBD_SUPPORT_USER_STRING_DESC
+#define USBD_SUPPORT_USER_STRING_DESC                   0U
+#endif /* USBD_SUPPORT_USER_STRING_DESC */
+
+#ifndef USBD_CLASS_USER_STRING_DESC
+#define USBD_CLASS_USER_STRING_DESC                     0U
+#endif /* USBD_CLASS_USER_STRING_DESC */
+
+#define  USB_LEN_DEV_QUALIFIER_DESC                     0x0AU
+#define  USB_LEN_DEV_DESC                               0x12U
+#define  USB_LEN_CFG_DESC                               0x09U
+#define  USB_LEN_IF_DESC                                0x09U
+#define  USB_LEN_EP_DESC                                0x07U
+#define  USB_LEN_OTG_DESC                               0x03U
+#define  USB_LEN_LANGID_STR_DESC                        0x04U
+#define  USB_LEN_OTHER_SPEED_DESC_SIZ                   0x09U
+
+#define  USBD_IDX_LANGID_STR                            0x00U
+#define  USBD_IDX_MFC_STR                               0x01U
+#define  USBD_IDX_PRODUCT_STR                           0x02U
+#define  USBD_IDX_SERIAL_STR                            0x03U
+#define  USBD_IDX_CONFIG_STR                            0x04U
+#define  USBD_IDX_INTERFACE_STR                         0x05U
+
+#define  USB_REQ_TYPE_STANDARD                          0x00U
+#define  USB_REQ_TYPE_CLASS                             0x20U
+#define  USB_REQ_TYPE_VENDOR                            0x40U
+#define  USB_REQ_TYPE_MASK                              0x60U
+
+#define  USB_REQ_RECIPIENT_DEVICE                       0x00U
+#define  USB_REQ_RECIPIENT_INTERFACE                    0x01U
+#define  USB_REQ_RECIPIENT_ENDPOINT                     0x02U
+#define  USB_REQ_RECIPIENT_MASK                         0x03U
+
+#define  USB_REQ_GET_STATUS                             0x00U
+#define  USB_REQ_CLEAR_FEATURE                          0x01U
+#define  USB_REQ_SET_FEATURE                            0x03U
+#define  USB_REQ_SET_ADDRESS                            0x05U
+#define  USB_REQ_GET_DESCRIPTOR                         0x06U
+#define  USB_REQ_SET_DESCRIPTOR                         0x07U
+#define  USB_REQ_GET_CONFIGURATION                      0x08U
+#define  USB_REQ_SET_CONFIGURATION                      0x09U
+#define  USB_REQ_GET_INTERFACE                          0x0AU
+#define  USB_REQ_SET_INTERFACE                          0x0BU
+#define  USB_REQ_SYNCH_FRAME                            0x0CU
+
+#define  USB_DESC_TYPE_DEVICE                           0x01U
+#define  USB_DESC_TYPE_CONFIGURATION                    0x02U
+#define  USB_DESC_TYPE_STRING                           0x03U
+#define  USB_DESC_TYPE_INTERFACE                        0x04U
+#define  USB_DESC_TYPE_ENDPOINT                         0x05U
+#define  USB_DESC_TYPE_DEVICE_QUALIFIER                 0x06U
+#define  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION        0x07U
+#define  USB_DESC_TYPE_IAD                              0x0BU
+#define  USB_DESC_TYPE_BOS                              0x0FU
+
+#define USB_CONFIG_REMOTE_WAKEUP                        0x02U
+#define USB_CONFIG_SELF_POWERED                         0x01U
+
+#define USB_FEATURE_EP_HALT                             0x00U
+#define USB_FEATURE_REMOTE_WAKEUP                       0x01U
+#define USB_FEATURE_TEST_MODE                           0x02U
+
+#define USB_DEVICE_CAPABITY_TYPE                        0x10U
+
+#define USB_CONF_DESC_SIZE                              0x09U
+#define USB_IF_DESC_SIZE                                0x09U
+#define USB_EP_DESC_SIZE                                0x07U
+#define USB_IAD_DESC_SIZE                               0x08U
+
+#define USB_HS_MAX_PACKET_SIZE                          512U
+#define USB_FS_MAX_PACKET_SIZE                          64U
+#define USB_MAX_EP0_SIZE                                64U
+
+/*  Device Status */
+#define USBD_STATE_DEFAULT                              0x01U
+#define USBD_STATE_ADDRESSED                            0x02U
+#define USBD_STATE_CONFIGURED                           0x03U
+#define USBD_STATE_SUSPENDED                            0x04U
+
+
+/*  EP0 State */
+#define USBD_EP0_IDLE                                   0x00U
+#define USBD_EP0_SETUP                                  0x01U
+#define USBD_EP0_DATA_IN                                0x02U
+#define USBD_EP0_DATA_OUT                               0x03U
+#define USBD_EP0_STATUS_IN                              0x04U
+#define USBD_EP0_STATUS_OUT                             0x05U
+#define USBD_EP0_STALL                                  0x06U
+
+#define USBD_EP_TYPE_CTRL                               0x00U
+#define USBD_EP_TYPE_ISOC                               0x01U
+#define USBD_EP_TYPE_BULK                               0x02U
+#define USBD_EP_TYPE_INTR                               0x03U
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_DEF_Exported_TypesDefinitions
+  * @{
+  */
+
+typedef  struct  usb_setup_req
+{
+  uint8_t   bmRequest;
+  uint8_t   bRequest;
+  uint16_t  wValue;
+  uint16_t  wIndex;
+  uint16_t  wLength;
+} USBD_SetupReqTypedef;
+
+typedef struct
+{
+  uint8_t   bLength;
+  uint8_t   bDescriptorType;
+  uint16_t  wTotalLength;
+  uint8_t   bNumInterfaces;
+  uint8_t   bConfigurationValue;
+  uint8_t   iConfiguration;
+  uint8_t   bmAttributes;
+  uint8_t   bMaxPower;
+} USBD_ConfigDescTypedef;
+
+typedef struct
+{
+  uint8_t   bLength;
+  uint8_t   bDescriptorType;
+  uint16_t  wTotalLength;
+  uint8_t   bNumDeviceCaps;
+} USBD_BosDescTypedef;
+
+typedef struct
+{
+  uint8_t   bLength;
+  uint8_t   bDescriptorType;
+  uint8_t   bEndpointAddress;
+  uint8_t   bmAttributes;
+  uint16_t  wMaxPacketSize;
+  uint8_t   bInterval;
+} USBD_EpDescTypedef;
+
+struct _USBD_HandleTypeDef;
+
+typedef struct _Device_cb
+{
+  uint8_t (*Init)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+  uint8_t (*DeInit)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+  /* Control Endpoints*/
+  uint8_t (*Setup)(struct _USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef  *req);
+  uint8_t (*EP0_TxSent)(struct _USBD_HandleTypeDef *pdev);
+  uint8_t (*EP0_RxReady)(struct _USBD_HandleTypeDef *pdev);
+  /* Class Specific Endpoints*/
+  uint8_t (*DataIn)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+  uint8_t (*DataOut)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+  uint8_t (*SOF)(struct _USBD_HandleTypeDef *pdev);
+  uint8_t (*IsoINIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+  uint8_t (*IsoOUTIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+
+  uint8_t  *(*GetHSConfigDescriptor)(uint16_t *length);
+  uint8_t  *(*GetFSConfigDescriptor)(uint16_t *length);
+  uint8_t  *(*GetOtherSpeedConfigDescriptor)(uint16_t *length);
+  uint8_t  *(*GetDeviceQualifierDescriptor)(uint16_t *length);
+#if (USBD_SUPPORT_USER_STRING_DESC == 1U)
+  uint8_t  *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint8_t index,  uint16_t *length);
+#endif
+
+} USBD_ClassTypeDef;
+
+/* Following USB Device Speed */
+typedef enum
+{
+  USBD_SPEED_HIGH  = 0U,
+  USBD_SPEED_FULL  = 1U,
+  USBD_SPEED_LOW   = 2U,
+} USBD_SpeedTypeDef;
+
+/* Following USB Device status */
+typedef enum
+{
+  USBD_OK = 0U,
+  USBD_BUSY,
+  USBD_EMEM,
+  USBD_FAIL,
+} USBD_StatusTypeDef;
+
+/* USB Device descriptors structure */
+typedef struct
+{
+  uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+#if (USBD_CLASS_USER_STRING_DESC == 1)
+  uint8_t *(*GetUserStrDescriptor)(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length);
+#endif
+#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1))
+  uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+#endif
+} USBD_DescriptorsTypeDef;
+
+/* USB Device handle structure */
+typedef struct
+{
+  uint32_t status;
+  uint32_t total_length;
+  uint32_t rem_length;
+  uint32_t maxpacket;
+  uint16_t is_used;
+  uint16_t bInterval;
+} USBD_EndpointTypeDef;
+
+/* USB Device handle structure */
+typedef struct _USBD_HandleTypeDef
+{
+  uint8_t                 id;
+  uint32_t                dev_config;
+  uint32_t                dev_default_config;
+  uint32_t                dev_config_status;
+  USBD_SpeedTypeDef       dev_speed;
+  USBD_EndpointTypeDef    ep_in[16];
+  USBD_EndpointTypeDef    ep_out[16];
+  __IO uint32_t           ep0_state;
+  uint32_t                ep0_data_len;
+  __IO uint8_t            dev_state;
+  __IO uint8_t            dev_old_state;
+  uint8_t                 dev_address;
+  uint8_t                 dev_connection_status;
+  uint8_t                 dev_test_mode;
+  uint32_t                dev_remote_wakeup;
+  uint8_t                 ConfIdx;
+
+  USBD_SetupReqTypedef    request;
+  USBD_DescriptorsTypeDef *pDesc;
+  USBD_ClassTypeDef       *pClass;
+  void                    *pClassData;
+  void                    *pUserData;
+  void                    *pData;
+  void                    *pBosDesc;
+  void                    *pConfDesc;
+} USBD_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_DEF_Exported_Macros
+  * @{
+  */
+__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
+{
+  uint16_t _SwapVal, _Byte1, _Byte2;
+  uint8_t *_pbuff = addr;
+
+  _Byte1 = *(uint8_t *)_pbuff;
+  _pbuff++;
+  _Byte2 = *(uint8_t *)_pbuff;
+
+  _SwapVal = (_Byte2 << 8) | _Byte1;
+
+  return _SwapVal;
+}
+
+#ifndef LOBYTE
+#define LOBYTE(x)  ((uint8_t)((x) & 0x00FFU))
+#endif
+
+#ifndef HIBYTE
+#define HIBYTE(x)  ((uint8_t)(((x) & 0xFF00U) >> 8U))
+#endif
+
+#ifndef MIN
+#define MIN(a, b)  (((a) < (b)) ? (a) : (b))
+#endif
+
+#ifndef MAX
+#define MAX(a, b)  (((a) > (b)) ? (a) : (b))
+#endif
+
+#if  defined ( __GNUC__ )
+#ifndef __weak
+#define __weak   __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* In HS mode and when the DMA is used, all variables and data structures dealing
+   with the DMA during the transaction process should be 4-bytes aligned */
+
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END    __attribute__ ((aligned (4U)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#else
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#if defined   (__CC_ARM)      /* ARM Compiler */
+#define __ALIGN_BEGIN    __align(4U)
+#elif defined (__ICCARM__)    /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif /* __CC_ARM */
+#endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DEF_Exported_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DEF_Exported_FunctionsPrototype
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_DEF_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
new file mode 100644
index 0000000..3ba14b0
--- /dev/null
+++ b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
@@ -0,0 +1,114 @@
+/**
+  ******************************************************************************
+  * @file    usbd_ioreq.h
+  * @author  MCD Application Team
+  * @brief   Header file for the usbd_ioreq.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_IOREQ_H
+#define __USBD_IOREQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include  "usbd_def.h"
+#include  "usbd_core.h"
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_IOREQ
+  * @brief header file for the usbd_ioreq.c file
+  * @{
+  */
+
+/** @defgroup USBD_IOREQ_Exported_Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Exported_Types
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_IOREQ_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_IOREQ_Exported_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype
+  * @{
+  */
+
+USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
+                                    uint8_t *pbuf, uint32_t len);
+
+USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
+                                            uint8_t *pbuf, uint32_t len);
+
+USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
+                                     uint8_t *pbuf, uint32_t len);
+
+USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
+                                      uint8_t *pbuf, uint32_t len);
+
+USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev);
+
+uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_IOREQ_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
new file mode 100644
index 0000000..e1e0de6
--- /dev/null
+++ b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
@@ -0,0 +1,694 @@
+/**
+  ******************************************************************************
+  * @file    usbd_core.c
+  * @author  MCD Application Team
+  * @brief   This file provides all the USBD core functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_core.h"
+
+/** @addtogroup STM32_USBD_DEVICE_LIBRARY
+  * @{
+  */
+
+
+/** @defgroup USBD_CORE
+  * @brief usbd core module
+  * @{
+  */
+
+/** @defgroup USBD_CORE_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_CORE_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_CORE_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_CORE_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CORE_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_CORE_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  USBD_Init
+  *         Initializes the device stack and load the class driver
+  * @param  pdev: device instance
+  * @param  pdesc: Descriptor structure address
+  * @param  id: Low level core index
+  * @retval None
+  */
+USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
+                             USBD_DescriptorsTypeDef *pdesc, uint8_t id)
+{
+  USBD_StatusTypeDef ret;
+
+  /* Check whether the USB Host handle is valid */
+  if (pdev == NULL)
+  {
+#if (USBD_DEBUG_LEVEL > 1U)
+    USBD_ErrLog("Invalid Device handle");
+#endif
+    return USBD_FAIL;
+  }
+
+  /* Unlink previous class resources */
+  pdev->pClass = NULL;
+  pdev->pUserData = NULL;
+  pdev->pConfDesc = NULL;
+
+  /* Assign USBD Descriptors */
+  if (pdesc != NULL)
+  {
+    pdev->pDesc = pdesc;
+  }
+
+  /* Set Device initial State */
+  pdev->dev_state = USBD_STATE_DEFAULT;
+  pdev->id = id;
+
+  /* Initialize low level driver */
+  ret = USBD_LL_Init(pdev);
+
+  return ret;
+}
+
+/**
+  * @brief  USBD_DeInit
+  *         Re-Initialize the device library
+  * @param  pdev: device instance
+  * @retval status: status
+  */
+USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
+{
+  USBD_StatusTypeDef ret;
+
+  /* Disconnect the USB Device */
+  (void)USBD_LL_Stop(pdev);
+
+  /* Set Default State */
+  pdev->dev_state = USBD_STATE_DEFAULT;
+
+  /* Free Class Resources */
+  if (pdev->pClass != NULL)
+  {
+    pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+    pdev->pClass = NULL;
+    pdev->pUserData = NULL;
+  }
+
+  /* Free Device descriptors resources */
+  pdev->pDesc = NULL;
+  pdev->pConfDesc = NULL;
+
+  /* DeInitialize low level driver */
+  ret = USBD_LL_DeInit(pdev);
+
+  return ret;
+}
+
+/**
+  * @brief  USBD_RegisterClass
+  *         Link class driver to Device Core.
+  * @param  pDevice : Device Handle
+  * @param  pclass: Class handle
+  * @retval USBD Status
+  */
+USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
+{
+  uint16_t len = 0U;
+
+  if (pclass == NULL)
+  {
+#if (USBD_DEBUG_LEVEL > 1U)
+    USBD_ErrLog("Invalid Class handle");
+#endif
+    return USBD_FAIL;
+  }
+
+  /* link the class to the USB Device handle */
+  pdev->pClass = pclass;
+
+  /* Get Device Configuration Descriptor */
+#ifdef USE_USB_HS
+  if (pdev->pClass->GetHSConfigDescriptor != NULL)
+  {
+    pdev->pConfDesc = (void *)pdev->pClass->GetHSConfigDescriptor(&len);
+  }
+#else /* Default USE_USB_FS */
+  if (pdev->pClass->GetFSConfigDescriptor != NULL)
+  {
+    pdev->pConfDesc = (void *)pdev->pClass->GetFSConfigDescriptor(&len);
+  }
+#endif /* USE_USB_FS */
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_Start
+  *         Start the USB Device Core.
+  * @param  pdev: Device Handle
+  * @retval USBD Status
+  */
+USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
+{
+  /* Start the low level driver  */
+  return USBD_LL_Start(pdev);
+}
+
+/**
+  * @brief  USBD_Stop
+  *         Stop the USB Device Core.
+  * @param  pdev: Device Handle
+  * @retval USBD Status
+  */
+USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev)
+{
+  /* Disconnect USB Device */
+  (void)USBD_LL_Stop(pdev);
+
+  /* Free Class Resources */
+  if (pdev->pClass != NULL)
+  {
+    (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+  }
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_RunTestMode
+  *         Launch test mode process
+  * @param  pdev: device instance
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef  *pdev)
+{
+  /* Prevent unused argument compilation warning */
+  UNUSED(pdev);
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_SetClassConfig
+  *        Configure device and start the interface
+  * @param  pdev: device instance
+  * @param  cfgidx: configuration index
+  * @retval status
+  */
+
+USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
+{
+  USBD_StatusTypeDef ret = USBD_FAIL;
+
+  if (pdev->pClass != NULL)
+  {
+    /* Set configuration and Start the Class */
+    ret = (USBD_StatusTypeDef)pdev->pClass->Init(pdev, cfgidx);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USBD_ClrClassConfig
+  *         Clear current configuration
+  * @param  pdev: device instance
+  * @param  cfgidx: configuration index
+  * @retval status: USBD_StatusTypeDef
+  */
+USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
+{
+  /* Clear configuration and De-initialize the Class process */
+  if (pdev->pClass != NULL)
+  {
+    pdev->pClass->DeInit(pdev, cfgidx);
+  }
+
+  return USBD_OK;
+}
+
+
+/**
+  * @brief  USBD_LL_SetupStage
+  *         Handle the setup stage
+  * @param  pdev: device instance
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
+{
+  USBD_StatusTypeDef ret;
+
+  USBD_ParseSetupRequest(&pdev->request, psetup);
+
+  pdev->ep0_state = USBD_EP0_SETUP;
+
+  pdev->ep0_data_len = pdev->request.wLength;
+
+  switch (pdev->request.bmRequest & 0x1FU)
+  {
+    case USB_REQ_RECIPIENT_DEVICE:
+      ret = USBD_StdDevReq(pdev, &pdev->request);
+      break;
+
+    case USB_REQ_RECIPIENT_INTERFACE:
+      ret = USBD_StdItfReq(pdev, &pdev->request);
+      break;
+
+    case USB_REQ_RECIPIENT_ENDPOINT:
+      ret = USBD_StdEPReq(pdev, &pdev->request);
+      break;
+
+    default:
+      ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USBD_LL_DataOutStage
+  *         Handle data OUT stage
+  * @param  pdev: device instance
+  * @param  epnum: endpoint index
+  * @param  pdata: data pointer
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
+                                        uint8_t epnum, uint8_t *pdata)
+{
+  USBD_EndpointTypeDef *pep;
+  USBD_StatusTypeDef ret;
+
+  if (epnum == 0U)
+  {
+    pep = &pdev->ep_out[0];
+
+    if (pdev->ep0_state == USBD_EP0_DATA_OUT)
+    {
+      if (pep->rem_length > pep->maxpacket)
+      {
+        pep->rem_length -= pep->maxpacket;
+
+        (void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket));
+      }
+      else
+      {
+        if (pdev->dev_state == USBD_STATE_CONFIGURED)
+        {
+          if (pdev->pClass->EP0_RxReady != NULL)
+          {
+            pdev->pClass->EP0_RxReady(pdev);
+          }
+        }
+
+        (void)USBD_CtlSendStatus(pdev);
+      }
+    }
+    else
+    {
+#if 0
+      if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
+      {
+        /*
+          * STATUS PHASE completed, update ep0_state to idle
+          */
+        pdev->ep0_state = USBD_EP0_IDLE;
+        (void)USBD_LL_StallEP(pdev, 0U);
+      }
+#endif
+    }
+  }
+  else
+  {
+    if (pdev->dev_state == USBD_STATE_CONFIGURED)
+    {
+      if (pdev->pClass->DataOut != NULL)
+      {
+        ret = (USBD_StatusTypeDef)pdev->pClass->DataOut(pdev, epnum);
+
+        if (ret != USBD_OK)
+        {
+          return ret;
+        }
+      }
+    }
+  }
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_LL_DataInStage
+  *         Handle data in stage
+  * @param  pdev: device instance
+  * @param  epnum: endpoint index
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
+                                       uint8_t epnum, uint8_t *pdata)
+{
+  USBD_EndpointTypeDef *pep;
+  USBD_StatusTypeDef ret;
+
+  if (epnum == 0U)
+  {
+    pep = &pdev->ep_in[0];
+
+    if (pdev->ep0_state == USBD_EP0_DATA_IN)
+    {
+      if (pep->rem_length > pep->maxpacket)
+      {
+        pep->rem_length -= pep->maxpacket;
+
+        (void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length);
+
+        /* Prepare endpoint for premature end of transfer */
+        (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
+      }
+      else
+      {
+        /* last packet is MPS multiple, so send ZLP packet */
+        if ((pep->maxpacket == pep->rem_length) &&
+            (pep->total_length >= pep->maxpacket) &&
+            (pep->total_length < pdev->ep0_data_len))
+        {
+          (void)USBD_CtlContinueSendData(pdev, NULL, 0U);
+          pdev->ep0_data_len = 0U;
+
+          /* Prepare endpoint for premature end of transfer */
+          (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
+        }
+        else
+        {
+          if (pdev->dev_state == USBD_STATE_CONFIGURED)
+          {
+            if (pdev->pClass->EP0_TxSent != NULL)
+            {
+              pdev->pClass->EP0_TxSent(pdev);
+            }
+          }
+          (void)USBD_LL_StallEP(pdev, 0x80U);
+          (void)USBD_CtlReceiveStatus(pdev);
+        }
+      }
+    }
+    else
+    {
+#if 0
+      if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
+          (pdev->ep0_state == USBD_EP0_IDLE))
+      {
+        (void)USBD_LL_StallEP(pdev, 0x80U);
+      }
+#endif
+    }
+
+    if (pdev->dev_test_mode == 1U)
+    {
+      (void)USBD_RunTestMode(pdev);
+      pdev->dev_test_mode = 0U;
+    }
+  }
+  else
+  {
+    if (pdev->dev_state == USBD_STATE_CONFIGURED)
+    {
+      if (pdev->pClass->DataIn != NULL)
+      {
+        ret = (USBD_StatusTypeDef)pdev->pClass->DataIn(pdev, epnum);
+
+        if (ret != USBD_OK)
+        {
+          return ret;
+        }
+      }
+    }
+  }
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_LL_Reset
+  *         Handle Reset event
+  * @param  pdev: device instance
+  * @retval status
+  */
+
+USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
+{
+  /* Upon Reset call user call back */
+  pdev->dev_state = USBD_STATE_DEFAULT;
+  pdev->ep0_state = USBD_EP0_IDLE;
+  pdev->dev_config = 0U;
+  pdev->dev_remote_wakeup = 0U;
+
+  if (pdev->pClass == NULL)
+  {
+    return USBD_FAIL;
+  }
+
+  if (pdev->pClassData != NULL)
+  {
+    if (pdev->pClass->DeInit != NULL)
+    {
+      (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+    }
+  }
+
+  /* Open EP0 OUT */
+  (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
+  pdev->ep_out[0x00U & 0xFU].is_used = 1U;
+
+  pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
+
+  /* Open EP0 IN */
+  (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
+  pdev->ep_in[0x80U & 0xFU].is_used = 1U;
+
+  pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_LL_SetSpeed
+  *         Handle Reset event
+  * @param  pdev: device instance
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
+                                    USBD_SpeedTypeDef speed)
+{
+  pdev->dev_speed = speed;
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_LL_Suspend
+  *         Handle Suspend event
+  * @param  pdev: device instance
+  * @retval status
+  */
+
+USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
+{
+  pdev->dev_old_state = pdev->dev_state;
+  pdev->dev_state = USBD_STATE_SUSPENDED;
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_LL_Resume
+  *         Handle Resume event
+  * @param  pdev: device instance
+  * @retval status
+  */
+
+USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
+{
+  if (pdev->dev_state == USBD_STATE_SUSPENDED)
+  {
+    pdev->dev_state = pdev->dev_old_state;
+  }
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_LL_SOF
+  *         Handle SOF event
+  * @param  pdev: device instance
+  * @retval status
+  */
+
+USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
+{
+  if (pdev->pClass == NULL)
+  {
+    return USBD_FAIL;
+  }
+
+  if (pdev->dev_state == USBD_STATE_CONFIGURED)
+  {
+    if (pdev->pClass->SOF != NULL)
+    {
+      (void)pdev->pClass->SOF(pdev);
+    }
+  }
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_LL_IsoINIncomplete
+  *         Handle iso in incomplete event
+  * @param  pdev: device instance
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
+                                           uint8_t epnum)
+{
+  if (pdev->pClass == NULL)
+  {
+    return USBD_FAIL;
+  }
+
+  if (pdev->dev_state == USBD_STATE_CONFIGURED)
+  {
+    if (pdev->pClass->IsoINIncomplete != NULL)
+    {
+      (void)pdev->pClass->IsoINIncomplete(pdev, epnum);
+    }
+  }
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_LL_IsoOUTIncomplete
+  *         Handle iso out incomplete event
+  * @param  pdev: device instance
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
+                                            uint8_t epnum)
+{
+  if (pdev->pClass == NULL)
+  {
+    return USBD_FAIL;
+  }
+
+  if (pdev->dev_state == USBD_STATE_CONFIGURED)
+  {
+    if (pdev->pClass->IsoOUTIncomplete != NULL)
+    {
+      (void)pdev->pClass->IsoOUTIncomplete(pdev, epnum);
+    }
+  }
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_LL_DevConnected
+  *         Handle device connection event
+  * @param  pdev: device instance
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
+{
+  /* Prevent unused argument compilation warning */
+  UNUSED(pdev);
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_LL_DevDisconnected
+  *         Handle device disconnection event
+  * @param  pdev: device instance
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
+{
+  /* Free Class Resources */
+  pdev->dev_state = USBD_STATE_DEFAULT;
+
+  if (pdev->pClass != NULL)
+  {
+    (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+  }
+
+  return USBD_OK;
+}
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
new file mode 100644
index 0000000..8679de4
--- /dev/null
+++ b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
@@ -0,0 +1,948 @@
+/**
+  ******************************************************************************
+  * @file    usbd_req.c
+  * @author  MCD Application Team
+  * @brief   This file provides the standard USB requests following chapter 9.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_ctlreq.h"
+#include "usbd_ioreq.h"
+
+
+/** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY
+  * @{
+  */
+
+
+/** @defgroup USBD_REQ
+  * @brief USB standard requests module
+  * @{
+  */
+
+/** @defgroup USBD_REQ_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_FunctionPrototypes
+  * @{
+  */
+static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+static uint8_t USBD_GetLen(uint8_t *buf);
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_Functions
+  * @{
+  */
+
+
+/**
+  * @brief  USBD_StdDevReq
+  *         Handle standard usb device requests
+  * @param  pdev: device instance
+  * @param  req: usb request
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  USBD_StatusTypeDef ret = USBD_OK;
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
+  {
+    case USB_REQ_TYPE_CLASS:
+    case USB_REQ_TYPE_VENDOR:
+      ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+      break;
+
+    case USB_REQ_TYPE_STANDARD:
+      switch (req->bRequest)
+      {
+        case USB_REQ_GET_DESCRIPTOR:
+          USBD_GetDescriptor(pdev, req);
+          break;
+
+        case USB_REQ_SET_ADDRESS:
+          USBD_SetAddress(pdev, req);
+          break;
+
+        case USB_REQ_SET_CONFIGURATION:
+          ret = USBD_SetConfig(pdev, req);
+          break;
+
+        case USB_REQ_GET_CONFIGURATION:
+          USBD_GetConfig(pdev, req);
+          break;
+
+        case USB_REQ_GET_STATUS:
+          USBD_GetStatus(pdev, req);
+          break;
+
+        case USB_REQ_SET_FEATURE:
+          USBD_SetFeature(pdev, req);
+          break;
+
+        case USB_REQ_CLEAR_FEATURE:
+          USBD_ClrFeature(pdev, req);
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          break;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USBD_StdItfReq
+  *         Handle standard usb interface requests
+  * @param  pdev: device instance
+  * @param  req: usb request
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  USBD_StatusTypeDef ret = USBD_OK;
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
+  {
+    case USB_REQ_TYPE_CLASS:
+    case USB_REQ_TYPE_VENDOR:
+    case USB_REQ_TYPE_STANDARD:
+      switch (pdev->dev_state)
+      {
+        case USBD_STATE_DEFAULT:
+        case USBD_STATE_ADDRESSED:
+        case USBD_STATE_CONFIGURED:
+
+          if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
+          {
+            ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+
+            if ((req->wLength == 0U) && (ret == USBD_OK))
+            {
+              (void)USBD_CtlSendStatus(pdev);
+            }
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+          }
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          break;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USBD_StdEPReq
+  *         Handle standard usb endpoint requests
+  * @param  pdev: device instance
+  * @param  req: usb request
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  USBD_EndpointTypeDef *pep;
+  uint8_t ep_addr;
+  USBD_StatusTypeDef ret = USBD_OK;
+  ep_addr = LOBYTE(req->wIndex);
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
+  {
+    case USB_REQ_TYPE_CLASS:
+    case USB_REQ_TYPE_VENDOR:
+      ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+      break;
+
+    case USB_REQ_TYPE_STANDARD:
+      switch (req->bRequest)
+      {
+        case USB_REQ_SET_FEATURE:
+          switch (pdev->dev_state)
+          {
+            case USBD_STATE_ADDRESSED:
+              if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+              {
+                (void)USBD_LL_StallEP(pdev, ep_addr);
+                (void)USBD_LL_StallEP(pdev, 0x80U);
+              }
+              else
+              {
+                USBD_CtlError(pdev, req);
+              }
+              break;
+
+            case USBD_STATE_CONFIGURED:
+              if (req->wValue == USB_FEATURE_EP_HALT)
+              {
+                if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U))
+                {
+                  (void)USBD_LL_StallEP(pdev, ep_addr);
+                }
+              }
+              (void)USBD_CtlSendStatus(pdev);
+
+              break;
+
+            default:
+              USBD_CtlError(pdev, req);
+              break;
+          }
+          break;
+
+        case USB_REQ_CLEAR_FEATURE:
+
+          switch (pdev->dev_state)
+          {
+            case USBD_STATE_ADDRESSED:
+              if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+              {
+                (void)USBD_LL_StallEP(pdev, ep_addr);
+                (void)USBD_LL_StallEP(pdev, 0x80U);
+              }
+              else
+              {
+                USBD_CtlError(pdev, req);
+              }
+              break;
+
+            case USBD_STATE_CONFIGURED:
+              if (req->wValue == USB_FEATURE_EP_HALT)
+              {
+                if ((ep_addr & 0x7FU) != 0x00U)
+                {
+                  (void)USBD_LL_ClearStallEP(pdev, ep_addr);
+                }
+                (void)USBD_CtlSendStatus(pdev);
+                ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+              }
+              break;
+
+            default:
+              USBD_CtlError(pdev, req);
+              break;
+          }
+          break;
+
+        case USB_REQ_GET_STATUS:
+          switch (pdev->dev_state)
+          {
+            case USBD_STATE_ADDRESSED:
+              if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+              {
+                USBD_CtlError(pdev, req);
+                break;
+              }
+              pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
+                    &pdev->ep_out[ep_addr & 0x7FU];
+
+              pep->status = 0x0000U;
+
+              (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
+              break;
+
+            case USBD_STATE_CONFIGURED:
+              if ((ep_addr & 0x80U) == 0x80U)
+              {
+                if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
+                {
+                  USBD_CtlError(pdev, req);
+                  break;
+                }
+              }
+              else
+              {
+                if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
+                {
+                  USBD_CtlError(pdev, req);
+                  break;
+                }
+              }
+
+              pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
+                    &pdev->ep_out[ep_addr & 0x7FU];
+
+              if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
+              {
+                pep->status = 0x0000U;
+              }
+              else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U)
+              {
+                pep->status = 0x0001U;
+              }
+              else
+              {
+                pep->status = 0x0000U;
+              }
+
+              (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
+              break;
+
+            default:
+              USBD_CtlError(pdev, req);
+              break;
+          }
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          break;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+
+  return ret;
+}
+
+
+/**
+  * @brief  USBD_GetDescriptor
+  *         Handle Get Descriptor requests
+  * @param  pdev: device instance
+  * @param  req: usb request
+  * @retval status
+  */
+static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  uint16_t len = 0U;
+  uint8_t *pbuf = NULL;
+  uint8_t err = 0U;
+
+  switch (req->wValue >> 8)
+  {
+#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U))
+    case USB_DESC_TYPE_BOS:
+      if (pdev->pDesc->GetBOSDescriptor != NULL)
+      {
+        pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
+      }
+      else
+      {
+        USBD_CtlError(pdev, req);
+        err++;
+      }
+      break;
+#endif
+    case USB_DESC_TYPE_DEVICE:
+      pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
+      break;
+
+    case USB_DESC_TYPE_CONFIGURATION:
+      if (pdev->dev_speed == USBD_SPEED_HIGH)
+      {
+        pbuf = pdev->pClass->GetHSConfigDescriptor(&len);
+        pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+      }
+      else
+      {
+        pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
+        pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+      }
+      break;
+
+    case USB_DESC_TYPE_STRING:
+      switch ((uint8_t)(req->wValue))
+      {
+        case USBD_IDX_LANGID_STR:
+          if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_MFC_STR:
+          if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_PRODUCT_STR:
+          if (pdev->pDesc->GetProductStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_SERIAL_STR:
+          if (pdev->pDesc->GetSerialStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_CONFIG_STR:
+          if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_INTERFACE_STR:
+          if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        default:
+#if (USBD_SUPPORT_USER_STRING_DESC == 1U)
+          if (pdev->pClass->GetUsrStrDescriptor != NULL)
+          {
+            pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue), &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+#endif
+
+#if (USBD_CLASS_USER_STRING_DESC == 1U)
+          if (pdev->pDesc->GetUserStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetUserStrDescriptor(pdev->dev_speed, (req->wValue), &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+#endif
+
+#if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U))
+          USBD_CtlError(pdev, req);
+          err++;
+#endif
+          break;
+      }
+      break;
+
+    case USB_DESC_TYPE_DEVICE_QUALIFIER:
+      if (pdev->dev_speed == USBD_SPEED_HIGH)
+      {
+        pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len);
+      }
+      else
+      {
+        USBD_CtlError(pdev, req);
+        err++;
+      }
+      break;
+
+    case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
+      if (pdev->dev_speed == USBD_SPEED_HIGH)
+      {
+        pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
+        pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
+      }
+      else
+      {
+        USBD_CtlError(pdev, req);
+        err++;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      err++;
+      break;
+  }
+
+  if (err != 0U)
+  {
+    return;
+  }
+
+  if (req->wLength != 0U)
+  {
+    if (len != 0U)
+    {
+      len = MIN(len, req->wLength);
+      (void)USBD_CtlSendData(pdev, pbuf, len);
+    }
+    else
+    {
+      USBD_CtlError(pdev, req);
+    }
+  }
+  else
+  {
+    (void)USBD_CtlSendStatus(pdev);
+  }
+}
+
+
+/**
+  * @brief  USBD_SetAddress
+  *         Set device address
+  * @param  pdev: device instance
+  * @param  req: usb request
+  * @retval status
+  */
+static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  uint8_t  dev_addr;
+
+  if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
+  {
+    dev_addr = (uint8_t)(req->wValue) & 0x7FU;
+
+    if (pdev->dev_state == USBD_STATE_CONFIGURED)
+    {
+      USBD_CtlError(pdev, req);
+    }
+    else
+    {
+      pdev->dev_address = dev_addr;
+      (void)USBD_LL_SetUSBAddress(pdev, dev_addr);
+      (void)USBD_CtlSendStatus(pdev);
+
+      if (dev_addr != 0U)
+      {
+        pdev->dev_state = USBD_STATE_ADDRESSED;
+      }
+      else
+      {
+        pdev->dev_state = USBD_STATE_DEFAULT;
+      }
+    }
+  }
+  else
+  {
+    USBD_CtlError(pdev, req);
+  }
+}
+
+/**
+  * @brief  USBD_SetConfig
+  *         Handle Set device configuration request
+  * @param  pdev: device instance
+  * @param  req: usb request
+  * @retval status
+  */
+static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  USBD_StatusTypeDef ret = USBD_OK;
+  static uint8_t cfgidx;
+
+  cfgidx = (uint8_t)(req->wValue);
+
+  if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
+  {
+    USBD_CtlError(pdev, req);
+    return USBD_FAIL;
+  }
+
+  switch (pdev->dev_state)
+  {
+    case USBD_STATE_ADDRESSED:
+      if (cfgidx != 0U)
+      {
+        pdev->dev_config = cfgidx;
+
+        ret = USBD_SetClassConfig(pdev, cfgidx);
+
+        if (ret != USBD_OK)
+        {
+          USBD_CtlError(pdev, req);
+        }
+        else
+        {
+          (void)USBD_CtlSendStatus(pdev);
+          pdev->dev_state = USBD_STATE_CONFIGURED;
+        }
+      }
+      else
+      {
+        (void)USBD_CtlSendStatus(pdev);
+      }
+      break;
+
+    case USBD_STATE_CONFIGURED:
+      if (cfgidx == 0U)
+      {
+        pdev->dev_state = USBD_STATE_ADDRESSED;
+        pdev->dev_config = cfgidx;
+        (void)USBD_ClrClassConfig(pdev, cfgidx);
+        (void)USBD_CtlSendStatus(pdev);
+      }
+      else if (cfgidx != pdev->dev_config)
+      {
+        /* Clear old configuration */
+        (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
+
+        /* set new configuration */
+        pdev->dev_config = cfgidx;
+
+        ret = USBD_SetClassConfig(pdev, cfgidx);
+
+        if (ret != USBD_OK)
+        {
+          USBD_CtlError(pdev, req);
+          (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
+          pdev->dev_state = USBD_STATE_ADDRESSED;
+        }
+        else
+        {
+          (void)USBD_CtlSendStatus(pdev);
+        }
+      }
+      else
+      {
+        (void)USBD_CtlSendStatus(pdev);
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      (void)USBD_ClrClassConfig(pdev, cfgidx);
+      ret = USBD_FAIL;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USBD_GetConfig
+  *         Handle Get device configuration request
+  * @param  pdev: device instance
+  * @param  req: usb request
+  * @retval status
+  */
+static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  if (req->wLength != 1U)
+  {
+    USBD_CtlError(pdev, req);
+  }
+  else
+  {
+    switch (pdev->dev_state)
+    {
+      case USBD_STATE_DEFAULT:
+      case USBD_STATE_ADDRESSED:
+        pdev->dev_default_config = 0U;
+        (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
+        break;
+
+      case USBD_STATE_CONFIGURED:
+        (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U);
+        break;
+
+      default:
+        USBD_CtlError(pdev, req);
+        break;
+    }
+  }
+}
+
+/**
+  * @brief  USBD_GetStatus
+  *         Handle Get Status request
+  * @param  pdev: device instance
+  * @param  req: usb request
+  * @retval status
+  */
+static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  switch (pdev->dev_state)
+  {
+    case USBD_STATE_DEFAULT:
+    case USBD_STATE_ADDRESSED:
+    case USBD_STATE_CONFIGURED:
+      if (req->wLength != 0x2U)
+      {
+        USBD_CtlError(pdev, req);
+        break;
+      }
+
+#if (USBD_SELF_POWERED == 1U)
+      pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
+#else
+      pdev->dev_config_status = 0U;
+#endif
+
+      if (pdev->dev_remote_wakeup != 0U)
+      {
+        pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
+      }
+
+      (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U);
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+}
+
+
+/**
+  * @brief  USBD_SetFeature
+  *         Handle Set device feature request
+  * @param  pdev: device instance
+  * @param  req: usb request
+  * @retval status
+  */
+static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
+  {
+    pdev->dev_remote_wakeup = 1U;
+    (void)USBD_CtlSendStatus(pdev);
+  }
+}
+
+
+/**
+  * @brief  USBD_ClrFeature
+  *         Handle clear device feature request
+  * @param  pdev: device instance
+  * @param  req: usb request
+  * @retval status
+  */
+static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  switch (pdev->dev_state)
+  {
+    case USBD_STATE_DEFAULT:
+    case USBD_STATE_ADDRESSED:
+    case USBD_STATE_CONFIGURED:
+      if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
+      {
+        pdev->dev_remote_wakeup = 0U;
+        (void)USBD_CtlSendStatus(pdev);
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+}
+
+
+/**
+  * @brief  USBD_ParseSetupRequest
+  *         Copy buffer into setup structure
+  * @param  pdev: device instance
+  * @param  req: usb request
+  * @retval None
+  */
+void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
+{
+  uint8_t *pbuff = pdata;
+
+  req->bmRequest = *(uint8_t *)(pbuff);
+
+  pbuff++;
+  req->bRequest = *(uint8_t *)(pbuff);
+
+  pbuff++;
+  req->wValue = SWAPBYTE(pbuff);
+
+  pbuff++;
+  pbuff++;
+  req->wIndex = SWAPBYTE(pbuff);
+
+  pbuff++;
+  pbuff++;
+  req->wLength = SWAPBYTE(pbuff);
+}
+
+
+/**
+  * @brief  USBD_CtlError
+  *         Handle USB low level Error
+  * @param  pdev: device instance
+  * @param  req: usb request
+  * @retval None
+  */
+void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  UNUSED(req);
+
+  (void)USBD_LL_StallEP(pdev, 0x80U);
+  (void)USBD_LL_StallEP(pdev, 0U);
+}
+
+
+/**
+  * @brief  USBD_GetString
+  *         Convert Ascii string into unicode one
+  * @param  desc : descriptor buffer
+  * @param  unicode : Formatted string buffer (unicode)
+  * @param  len : descriptor length
+  * @retval None
+  */
+void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
+{
+  uint8_t idx = 0U;
+  uint8_t *pdesc;
+
+  if (desc == NULL)
+  {
+    return;
+  }
+
+  pdesc = desc;
+  *len = ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U;
+
+  unicode[idx] = *(uint8_t *)len;
+  idx++;
+  unicode[idx] = USB_DESC_TYPE_STRING;
+  idx++;
+
+  while (*pdesc != (uint8_t)'\0')
+  {
+    unicode[idx] = *pdesc;
+    pdesc++;
+    idx++;
+
+    unicode[idx] = 0U;
+    idx++;
+  }
+}
+
+
+/**
+  * @brief  USBD_GetLen
+  *         return the string length
+   * @param  buf : pointer to the ascii string buffer
+  * @retval string length
+  */
+static uint8_t USBD_GetLen(uint8_t *buf)
+{
+  uint8_t  len = 0U;
+  uint8_t *pbuff = buf;
+
+  while (*pbuff != (uint8_t)'\0')
+  {
+    len++;
+    pbuff++;
+  }
+
+  return len;
+}
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
new file mode 100644
index 0000000..99b5945
--- /dev/null
+++ b/squeow_sw/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
@@ -0,0 +1,226 @@
+/**
+  ******************************************************************************
+  * @file    usbd_ioreq.c
+  * @author  MCD Application Team
+  * @brief   This file provides the IO requests APIs for control endpoints.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_ioreq.h"
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+
+/** @defgroup USBD_IOREQ
+  * @brief control I/O requests module
+  * @{
+  */
+
+/** @defgroup USBD_IOREQ_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_FunctionPrototypes
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  USBD_CtlSendData
+  *         send data on the ctl pipe
+  * @param  pdev: device instance
+  * @param  buff: pointer to data buffer
+  * @param  len: length of data to be sent
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
+                                    uint8_t *pbuf, uint32_t len)
+{
+  /* Set EP0 State */
+  pdev->ep0_state = USBD_EP0_DATA_IN;
+  pdev->ep_in[0].total_length = len;
+
+#ifdef USBD_AVOID_PACKET_SPLIT_MPS
+  pdev->ep_in[0].rem_length = 0U;
+#else
+  pdev->ep_in[0].rem_length = len;
+#endif
+
+  /* Start the transfer */
+  (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_CtlContinueSendData
+  *         continue sending data on the ctl pipe
+  * @param  pdev: device instance
+  * @param  buff: pointer to data buffer
+  * @param  len: length of data to be sent
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
+                                            uint8_t *pbuf, uint32_t len)
+{
+  /* Start the next transfer */
+  (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_CtlPrepareRx
+  *         receive data on the ctl pipe
+  * @param  pdev: device instance
+  * @param  buff: pointer to data buffer
+  * @param  len: length of data to be received
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
+                                     uint8_t *pbuf, uint32_t len)
+{
+  /* Set EP0 State */
+  pdev->ep0_state = USBD_EP0_DATA_OUT;
+  pdev->ep_out[0].total_length = len;
+
+#ifdef USBD_AVOID_PACKET_SPLIT_MPS
+  pdev->ep_out[0].rem_length = 0U;
+#else
+  pdev->ep_out[0].rem_length = len;
+#endif
+
+  /* Start the transfer */
+  (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_CtlContinueRx
+  *         continue receive data on the ctl pipe
+  * @param  pdev: device instance
+  * @param  buff: pointer to data buffer
+  * @param  len: length of data to be received
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
+                                      uint8_t *pbuf, uint32_t len)
+{
+  (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_CtlSendStatus
+  *         send zero lzngth packet on the ctl pipe
+  * @param  pdev: device instance
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
+{
+  /* Set EP0 State */
+  pdev->ep0_state = USBD_EP0_STATUS_IN;
+
+  /* Start the transfer */
+  (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_CtlReceiveStatus
+  *         receive zero lzngth packet on the ctl pipe
+  * @param  pdev: device instance
+  * @retval status
+  */
+USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
+{
+  /* Set EP0 State */
+  pdev->ep0_state = USBD_EP0_STATUS_OUT;
+
+  /* Start the transfer */
+  (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_GetRxCount
+  *         returns the received data length
+  * @param  pdev: device instance
+  * @param  ep_addr: endpoint address
+  * @retval Rx Data blength
+  */
+uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  return USBD_LL_GetRxDataSize(pdev, ep_addr);
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/squeow_sw/STM32G431KBTx_FLASH.ld b/squeow_sw/STM32G431KBTx_FLASH.ld
new file mode 100644
index 0000000..22d7347
--- /dev/null
+++ b/squeow_sw/STM32G431KBTx_FLASH.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Author		: STM32CubeMX
+**
+**  Abstract    : Linker script for STM32G431KBTx series
+**                128Kbytes FLASH and 32Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed “as is,� without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 32K
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 128K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/squeow_sw/Src/main.c b/squeow_sw/Src/main.c
new file mode 100644
index 0000000..e6f9145
--- /dev/null
+++ b/squeow_sw/Src/main.c
@@ -0,0 +1,628 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "usb_device.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "si5351.h"
+ 
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+ADC_HandleTypeDef hadc2;
+
+I2C_HandleTypeDef hi2c1;
+
+TIM_HandleTypeDef htim2;
+TIM_HandleTypeDef htim3;
+
+UART_HandleTypeDef huart1;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_TIM2_Init(void);
+static void MX_I2C1_Init(void);
+static void MX_TIM3_Init(void);
+static void MX_ADC1_Init(void);
+static void MX_ADC2_Init(void);
+static void MX_USART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_TIM2_Init();
+  MX_I2C1_Init();
+  MX_TIM3_Init();
+  MX_ADC1_Init();
+  MX_ADC2_Init();
+  MX_USART1_UART_Init();
+  MX_USB_Device_Init();
+  /* USER CODE BEGIN 2 */
+
+   HAL_TIM_Base_Start_IT(&htim2);
+   HAL_TIM_Base_Start_IT(&htim3);
+
+	HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
+        HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_2);
+        HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_3);
+        HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4);
+
+	HAL_Delay(10);
+	si5351_initialize();
+        HAL_Delay(10);
+        si5351_on_clk(0);
+        si5351_on_clk(1);
+        si5351_set_frequency(1000000,0);
+        si5351_set_frequency(1000000,1);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+//	HAL_GPIO_TogglePin(LED_GPIO_Port, LED_Pin);
+
+//                TIM2->CCR1 = pwm_value > 1024 ? 1024 : pwm_value;
+//                TIM2->CCR2 = pwm_value > 2048 ? 1024 : sat_sub(pwm_value,1024) & 1023;
+//                TIM2->CCR3 = pwm_value > 3072 ? 1024 : sat_sub(pwm_value,2048) & 1023;
+//                TIM2->CCR4 = pwm_value > 4096 ? 1024 : sat_sub(pwm_value,3072) & 1023;
+        HAL_Delay(10);
+        si5351_set_frequency(1000000,0);
+        si5351_set_frequency(1000000,1);
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
+  RCC_OscInitStruct.PLL.PLLN = 32;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  HAL_RCC_MCOConfig(RCC_MCO_PG10, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1);
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  ADC_MultiModeTypeDef multimode = {0};
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+
+  /* USER CODE END ADC1_Init 1 */
+
+  /** Common config
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
+  hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.GainCompensation = 0;
+  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  hadc1.Init.LowPowerAutoWait = DISABLE;
+  hadc1.Init.ContinuousConvMode = DISABLE;
+  hadc1.Init.NbrOfConversion = 1;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+  hadc1.Init.DMAContinuousRequests = DISABLE;
+  hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+  hadc1.Init.OversamplingMode = DISABLE;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure the ADC multi-mode
+  */
+  multimode.Mode = ADC_MODE_INDEPENDENT;
+  if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_15;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
+  sConfig.SingleDiff = ADC_SINGLE_ENDED;
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;
+  sConfig.Offset = 0;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief ADC2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC2_Init(void)
+{
+
+  /* USER CODE BEGIN ADC2_Init 0 */
+
+  /* USER CODE END ADC2_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC2_Init 1 */
+
+  /* USER CODE END ADC2_Init 1 */
+
+  /** Common config
+  */
+  hadc2.Instance = ADC2;
+  hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
+  hadc2.Init.Resolution = ADC_RESOLUTION_12B;
+  hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc2.Init.GainCompensation = 0;
+  hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
+  hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
+  hadc2.Init.LowPowerAutoWait = DISABLE;
+  hadc2.Init.ContinuousConvMode = DISABLE;
+  hadc2.Init.NbrOfConversion = 4;
+  hadc2.Init.DiscontinuousConvMode = DISABLE;
+  hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+  hadc2.Init.DMAContinuousRequests = DISABLE;
+  hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+  hadc2.Init.OversamplingMode = DISABLE;
+  if (HAL_ADC_Init(&hadc2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_3;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
+  sConfig.SingleDiff = ADC_SINGLE_ENDED;
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;
+  sConfig.Offset = 0;
+  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_2;
+  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_3;
+  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_4;
+  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC2_Init 2 */
+
+  /* USER CODE END ADC2_Init 2 */
+
+}
+
+/**
+  * @brief I2C1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_I2C1_Init(void)
+{
+
+  /* USER CODE BEGIN I2C1_Init 0 */
+
+  /* USER CODE END I2C1_Init 0 */
+
+  /* USER CODE BEGIN I2C1_Init 1 */
+
+  /* USER CODE END I2C1_Init 1 */
+  hi2c1.Instance = I2C1;
+  hi2c1.Init.Timing = 0x208080C1;
+  hi2c1.Init.OwnAddress1 = 0;
+  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c1.Init.OwnAddress2 = 0;
+  hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Analogue filter
+  */
+  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Digital filter
+  */
+  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN I2C1_Init 2 */
+
+  /* USER CODE END I2C1_Init 2 */
+
+}
+
+/**
+  * @brief TIM2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+  TIM_OC_InitTypeDef sConfigOC = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = 0;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = 2047;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.OCMode = TIM_OCMODE_PWM1;
+  sConfigOC.Pulse = 500;
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.Pulse = 1000;
+  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.Pulse = 1500;
+  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.Pulse = 2000;
+  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+  HAL_TIM_MspPostInit(&htim2);
+
+}
+
+/**
+  * @brief TIM3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM3_Init(void)
+{
+
+  /* USER CODE BEGIN TIM3_Init 0 */
+
+  /* USER CODE END TIM3_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM3_Init 1 */
+
+  /* USER CODE END TIM3_Init 1 */
+  htim3.Instance = TIM3;
+  htim3.Init.Prescaler = 49152;
+  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim3.Init.Period = 199;
+  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM3_Init 2 */
+
+  /* USER CODE END TIM3_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+/* USER CODE BEGIN MX_GPIO_Init_1 */
+/* USER CODE END MX_GPIO_Init_1 */
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+  /*Configure GPIO pin : PG10 */
+  GPIO_InitStruct.Pin = GPIO_PIN_10;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+/* USER CODE BEGIN MX_GPIO_Init_2 */
+/* USER CODE END MX_GPIO_Init_2 */
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  __disable_irq();
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/squeow_sw/Src/si5351.c b/squeow_sw/Src/si5351.c
new file mode 100644
index 0000000..73d0b9d
--- /dev/null
+++ b/squeow_sw/Src/si5351.c
@@ -0,0 +1,182 @@
+#include "main.h"
+#include "stm32g4xx_hal.h"
+#include <math.h>
+#include "si5351.h"
+
+uint8_t oeb;
+
+void si5351_write8 (uint8_t reg, uint8_t value){
+	while (HAL_I2C_IsDeviceReady(&hi2c1, (uint16_t)(SI5351_ADDRESS<<1), 3, 100) != HAL_OK) { }
+	HAL_I2C_Mem_Write(&hi2c1, (uint8_t)(SI5351_ADDRESS<<1), (uint8_t)reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)(&value), 1, 100);
+}
+
+uint8_t si5351_read8(uint8_t reg, uint8_t *value){
+	HAL_StatusTypeDef status = HAL_OK;
+	while (HAL_I2C_IsDeviceReady(&hi2c1, (uint16_t)(SI5351_ADDRESS<<1), 3, 100) != HAL_OK) { }
+	status = HAL_I2C_Mem_Read(&hi2c1,							// i2c handle
+    						  (uint8_t)(SI5351_ADDRESS<<1),		// i2c address, left aligned
+							  (uint8_t)reg,						// register address
+							  I2C_MEMADD_SIZE_8BIT,				// si5351 uses 8bit register addresses
+							  (uint8_t*)(&value),				// write returned data to this variable
+							  1,								// how many bytes to expect returned
+							  100);								// timeout
+
+  return status;
+}
+
+
+void CalcRegisters(uint32_t fout, uint8_t *regs){
+//    uint32_t fref = SI5351_CRYSTAL_FREQ;                        // The reference frequency
+ 
+    // Calc Output Multisynth Divider and R with e = 0 and f = 1 => msx_p2 = 0 and msx_p3 = 1
+    uint32_t d = 4;
+    uint32_t msx_p1 = 0;                         // If fout > 150 MHz then MSx_P1 = 0 and MSx_DIVBY4 = 0xC0, see datasheet 4.1.3
+    int msx_divby4 = 0;
+    int rx_div = 0;
+    int r = 1;
+ 
+    if (fout > 150e6)
+        msx_divby4 = 0x0C;                       // MSx_DIVBY4[1:0] = 0b11, see datasheet 4.1.3
+    else if (fout < 292969UL)                    // If fout < 500 kHz then use R divider, see datasheet 4.2.2. In reality this means > 292 968,75 Hz when d = 2048
+    {
+        int rd = 0;
+        while ((r < 128) && (r * fout < 292969UL))
+        {
+            r <<= 1;
+            rd++;
+        }
+        rx_div = rd << 4;
+
+        d = 600e6 / (r * fout);                  // Use lowest VCO frequency but handle d minimum
+        if (d % 2)                               // Make d even to reduce spurious and phase noise/jitter, see datasheet 4.1.2.1.
+            d++;
+
+        if (d * r * fout < 600e6)                // VCO frequency to low check and maintain an even d value
+            d += 2;
+    }
+    else                                         // 292968 Hz <= fout <= 150 MHz
+    {
+        d = 600e6 / fout;                        // Use lowest VCO frequency but handle d minimum
+        if (d < 6)
+            d = 6;
+        else if (d % 2)                          // Make d even to reduce phase noise/jitter, see datasheet 4.1.2.1.
+           d++;
+
+        if (d * fout < 600e6)                    // VCO frequency to low check and maintain an even d value
+            d += 2;
+    }
+    msx_p1 = 128 * d - 512;
+
+    uint32_t fvco = (uint32_t) d * r * fout;
+
+    // Calc Feedback Multisynth Divider
+    double fmd = (double)fvco / SI5351_CRYSTAL_FREQ;            // The FMD value has been found
+    int a = fmd;                                 // a is the integer part of the FMD value
+ 
+    double b_c = (double)fmd - a;                // Get b/c
+    uint32_t c = 1048575UL;
+    uint32_t b = (double)b_c * c;
+    if (b > 0)
+    {
+        c = (double)b / b_c + 0.5;               // Improves frequency precision in some cases
+        if (c > 1048575UL)
+            c = 1048575UL;
+    }
+
+    uint32_t msnx_p1 = 128 * a + 128 * b / c - 512;   // See datasheet 3.2
+    uint32_t msnx_p2 = 128 * b - c * (128 * b / c);
+    uint32_t msnx_p3 = c;
+ 
+    // Feedback Multisynth Divider registers
+    regs[0] = (msnx_p3 >> 8) & 0xFF;
+    regs[1] = msnx_p3 & 0xFF;
+    regs[2] = (msnx_p1 >> 16) & 0x03;
+    regs[3] = (msnx_p1 >> 8) & 0xFF;
+    regs[4] = msnx_p1 & 0xFF;
+    regs[5] = ((msnx_p3 >> 12) & 0xF0) + ((msnx_p2 >> 16) & 0x0F);
+    regs[6] = (msnx_p2 >> 8) & 0xFF;
+    regs[7] = msnx_p2 & 0xFF;
+ 
+    // Output Multisynth Divider registers 
+    regs[8] = 0;                                  // (msx_p3 >> 8) & 0xFF
+    regs[9] = 1;                                  // msx_p3 & 0xFF
+    regs[10] = rx_div + msx_divby4 + ((msx_p1 >> 16) & 0x03);
+    regs[11] = (msx_p1 >> 8) & 0xFF;
+    regs[12] = msx_p1 & 0xFF;
+    regs[13] = 0;                                 // ((msx_p3 >> 12) & 0xF0) + (msx_p2 >> 16) & 0x0F
+    regs[14] = 0;                                 // (msx_p2 >> 8) & 0xFF
+    regs[15] = 0;                                 // msx_p2 & 0xFF
+
+//	HAL_I2C_Master_Transmit(&hi2c2, Si5351_ConfigStruct->HW_I2C_Address, reg_data, sizeof(reg_data), HAL_MAX_DELAY); 
+    return;
+}
+
+void si5351_initialize(){
+	uint8_t dummy;
+	// Initialize Si5351A
+	while (si5351_read8(0,dummy) & 0x80);    // Wait for Si5351A to initialize
+	oeb = 0xFF;
+
+    si5351_write8(SI5351_OUT_ENABLE, oeb);            // Output Enable Control, disable all
+
+    si5351_write8(SI5351_INPUT_SOURCE, 0x00);           // PLL Input Source, select the XTAL input as the reference clock for PLLA and PLLB
+    si5351_write8(SI5351_OUT_DIS_STATE, 0x00);		// stato bassa Z giu se disabilitati
+
+    // Output MultisynthN, e = 0, f = 1, MS0_P2 and MSO_P3
+    si5351_write8(SI5351_MULTISYNTH0, 0x00);
+    si5351_write8(SI5351_MULTISYNTH0+1, 0x01);
+    si5351_write8(SI5351_MULTISYNTH0+5, 0x00);
+    si5351_write8(SI5351_MULTISYNTH0+6, 0x00);
+    si5351_write8(SI5351_MULTISYNTH0+7, 0x00);
+
+    si5351_write8(SI5351_MULTISYNTH1, 0x00);
+    si5351_write8(SI5351_MULTISYNTH1+1, 0x01);
+    si5351_write8(SI5351_MULTISYNTH1+5, 0x00);
+    si5351_write8(SI5351_MULTISYNTH1+6, 0x00);
+    si5351_write8(SI5351_MULTISYNTH1+7, 0x00);
+
+    si5351_write8(SI5351_MULTISYNTH2, 0x00);
+    si5351_write8(SI5351_MULTISYNTH2+1, 0x01);
+    si5351_write8(SI5351_MULTISYNTH2+5, 0x00);
+    si5351_write8(SI5351_MULTISYNTH2+6, 0x00);
+    si5351_write8(SI5351_MULTISYNTH2+7, 0x00);
+
+    si5351_write8(SI5351_CLK0_CONTROL, 0x4F);   // Power up CLK0, PLLA, MS0 operates in integer mode, Output Clock 0 is not inverted, Select MultiSynth 0 as the source for CLK0 and 8 mA
+    si5351_write8(SI5351_CLK1_CONTROL, 0x5F);   // Power up CLK1, PLLA, MS0 operates in integer mode, Output Clock 1 is inverted, Select MultiSynth 1 as the source for CLK1 and 8 mA
+    si5351_write8(SI5351_CLK2_CONTROL, 0x6F);   // Power up CLK2, PLLB, int, non inv, multisynth 2, 8 ma
+
+    // Reference load configuration
+    si5351_write8(SI5351_CRYSTAL_LOAD, 0x12);          // Set reference load C: 6 pF = 0x12, 8 pF = 0x92, 10 pF = 0xD2
+}
+
+void si5351_set_frequency(uint32_t freq, uint8_t pll){
+	uint8_t regs[16];
+	CalcRegisters(freq, regs);
+
+    // Load Output Multisynth0 with d (e and f already set during init. and never changed)
+	if(pll == 0){
+		for (int i = 0; i < 8; i++)
+			si5351_write8(SI5351_PLLA + i, regs[i]);
+		for (int i = 10; i < 13; i++)
+	        	si5351_write8(34 + i, regs[i]);
+	} else if(pll == 1){
+		for (int i = 0; i < 8; i++)
+			si5351_write8(SI5351_PLLB + i, regs[i]);
+		for (int i = 10; i < 13; i++)
+        		si5351_write8(42 + i, regs[i]);
+	}
+
+    // Reset PLLA
+    // delayMicroseconds(500);            // Allow registers to settle before resetting the PLL
+    si5351_write8(SI5351_RESET, 0x20);
+}
+
+void si5351_off_clk(uint8_t clk){
+	oeb |= 1U << clk;
+	si5351_write8(SI5351_OUT_ENABLE, oeb);
+}
+
+void si5351_on_clk(uint8_t clk){
+	oeb &= ~(1U << clk);
+	si5351_write8(SI5351_OUT_ENABLE, oeb);
+}
diff --git a/squeow_sw/Src/squeow.c b/squeow_sw/Src/squeow.c
new file mode 100644
index 0000000..d6f2853
--- /dev/null
+++ b/squeow_sw/Src/squeow.c
@@ -0,0 +1,83 @@
+#include <main.h>
+#include <stdio.h>
+#include <stm32g4xx_hal_conf.h>
+#include <math.h>
+
+#include "squeow.h"
+
+/* SQUEOW
+
+TIM3 eventi 98304000/(49152×200) 10hz
+TIM2 PWM 98304000/2048 48khz
+
+risoluzione PWM 4*2048 -> 8192 (13bit)
+
+*/
+
+uint8_t stato_audio;
+uint16_t pwm_value, sample_value;
+char display_buffer[16];
+uint8_t rails_number;
+uint16_t samples_ringbuf[SAMPLES_BUFFER_SIZE]; ///< buffer ad anello dei dati RX
+uint16_t samples_ringbuf_input_index, samples_ringbuf_output_index;
+
+
+void audio_play(uint16_t pbuf, uint8_t size){
+/*
+	char display_buffer[16];
+        uint16_t static indice;
+        indice++;
+        snprintf(display_buffer, 10, "n %d", indice);
+        ssd1306_SetCursor(0, 1);
+        ssd1306_WriteString(display_buffer, Font_11x18, White);
+//        ssd1306_UpdateScreen(&hi2c1);
+*/
+	for (uint8_t i=0; i<size; i++) {
+		
+	}
+
+}
+
+uint32_t sat_sub(uint16_t x, uint16_t y){
+    uint16_t res = x - y;
+    res &= -(res <= x);
+    return res;
+}
+
+uint16_t u16_sine(void){
+        static double angle;
+        angle += SINE_INCREMENT;
+         if(angle >= 6.28) angle = 0;
+        return (uint16_t)((sin(angle)*0x7fff)+0x7fff);
+}
+
+uint16_t u12_sine(void){
+        static double angle;
+        angle += SINE_INCREMENT;
+         if(angle >= 6.28) angle = 0;
+        return (uint16_t)((sin(angle)*0x7ff)+0x7ff);
+}
+
+uint16_t sample(void){
+/*
+                        stato_audio == STATO_AUDIO_ADC;
+                        HAL_ADC_Start(&hadc1);
+                        if (HAL_ADC_PollForConversion(&hadc1, 10) == HAL_OK){
+//                              store_sample(HAL_ADC_GetValue(&hadc1) << 4);
+                                sample_value = HAL_ADC_GetValue(&hadc1);
+                        }
+                        HAL_ADC_Stop(&hadc1);
+                        */
+}
+
+void store_samples(uint16_t *data, uint16_t size){
+        for(uint16_t i = 0; i < size; ++i) {
+              samples_ringbuf[samples_ringbuf_input_index] = data[i];
+                store_sample(data[i]);
+        }
+}
+
+void store_sample(uint16_t sample){
+                samples_ringbuf[samples_ringbuf_input_index] = sample;
+                ringbuf_increment(&samples_ringbuf_input_index, SAMPLES_BUFFER_SIZE_MASK);
+}
diff --git a/squeow_sw/Src/stm32g4xx_hal_msp.c b/squeow_sw/Src/stm32g4xx_hal_msp.c
new file mode 100644
index 0000000..f8e0ea6
--- /dev/null
+++ b/squeow_sw/Src/stm32g4xx_hal_msp.c
@@ -0,0 +1,489 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file         stm32g4xx_hal_msp.c
+  * @brief        This file provides code for the MSP Initialization
+  *               and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+                    /**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
+  */
+  HAL_PWREx_DisableUCPDDeadBattery();
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0;
+
+/**
+* @brief ADC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspInit 0 */
+
+  /* USER CODE END ADC1_MspInit 0 */
+
+  /** Initializes the peripherals clocks
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
+    PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    HAL_RCC_ADC12_CLK_ENABLED++;
+    if(HAL_RCC_ADC12_CLK_ENABLED==1){
+      __HAL_RCC_ADC12_CLK_ENABLE();
+    }
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**ADC1 GPIO Configuration
+    PB0     ------> ADC1_IN15
+    */
+    GPIO_InitStruct.Pin = AUDIO_IN_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(AUDIO_IN_GPIO_Port, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN ADC1_MspInit 1 */
+
+  /* USER CODE END ADC1_MspInit 1 */
+  }
+  else if(hadc->Instance==ADC2)
+  {
+  /* USER CODE BEGIN ADC2_MspInit 0 */
+
+  /* USER CODE END ADC2_MspInit 0 */
+
+  /** Initializes the peripherals clocks
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
+    PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    HAL_RCC_ADC12_CLK_ENABLED++;
+    if(HAL_RCC_ADC12_CLK_ENABLED==1){
+      __HAL_RCC_ADC12_CLK_ENABLE();
+    }
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**ADC2 GPIO Configuration
+    PA4     ------> ADC2_IN17
+    PA5     ------> ADC2_IN13
+    PA6     ------> ADC2_IN3
+    PA7     ------> ADC2_IN4
+    */
+    GPIO_InitStruct.Pin = TEMPERATURA_Pin|CORRENTE_Pin|DIRETTA_Pin|RIFLESSA_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN ADC2_MspInit 1 */
+
+  /* USER CODE END ADC2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief ADC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+  /* USER CODE END ADC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    HAL_RCC_ADC12_CLK_ENABLED--;
+    if(HAL_RCC_ADC12_CLK_ENABLED==0){
+      __HAL_RCC_ADC12_CLK_DISABLE();
+    }
+
+    /**ADC1 GPIO Configuration
+    PB0     ------> ADC1_IN15
+    */
+    HAL_GPIO_DeInit(AUDIO_IN_GPIO_Port, AUDIO_IN_Pin);
+
+  /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+  /* USER CODE END ADC1_MspDeInit 1 */
+  }
+  else if(hadc->Instance==ADC2)
+  {
+  /* USER CODE BEGIN ADC2_MspDeInit 0 */
+
+  /* USER CODE END ADC2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    HAL_RCC_ADC12_CLK_ENABLED--;
+    if(HAL_RCC_ADC12_CLK_ENABLED==0){
+      __HAL_RCC_ADC12_CLK_DISABLE();
+    }
+
+    /**ADC2 GPIO Configuration
+    PA4     ------> ADC2_IN17
+    PA5     ------> ADC2_IN13
+    PA6     ------> ADC2_IN3
+    PA7     ------> ADC2_IN4
+    */
+    HAL_GPIO_DeInit(GPIOA, TEMPERATURA_Pin|CORRENTE_Pin|DIRETTA_Pin|RIFLESSA_Pin);
+
+  /* USER CODE BEGIN ADC2_MspDeInit 1 */
+
+  /* USER CODE END ADC2_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief I2C MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(hi2c->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspInit 0 */
+
+  /* USER CODE END I2C1_MspInit 0 */
+
+  /** Initializes the peripherals clocks
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
+    PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**I2C1 GPIO Configuration
+    PA15     ------> I2C1_SCL
+    PB7     ------> I2C1_SDA
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_15;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_I2C1_CLK_ENABLE();
+  /* USER CODE BEGIN I2C1_MspInit 1 */
+
+  /* USER CODE END I2C1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief I2C MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
+{
+  if(hi2c->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspDeInit 0 */
+
+  /* USER CODE END I2C1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_I2C1_CLK_DISABLE();
+
+    /**I2C1 GPIO Configuration
+    PA15     ------> I2C1_SCL
+    PB7     ------> I2C1_SDA
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_15);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7);
+
+  /* USER CODE BEGIN I2C1_MspDeInit 1 */
+
+  /* USER CODE END I2C1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Base MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+  else if(htim_base->Instance==TIM3)
+  {
+  /* USER CODE BEGIN TIM3_MspInit 0 */
+
+  /* USER CODE END TIM3_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM3_CLK_ENABLE();
+    /* TIM3 interrupt Init */
+    HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(TIM3_IRQn);
+  /* USER CODE BEGIN TIM3_MspInit 1 */
+
+  /* USER CODE END TIM3_MspInit 1 */
+  }
+
+}
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(htim->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspPostInit 0 */
+
+  /* USER CODE END TIM2_MspPostInit 0 */
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**TIM2 GPIO Configuration
+    PA0     ------> TIM2_CH1
+    PA1     ------> TIM2_CH2
+    PA2     ------> TIM2_CH3
+    PA3     ------> TIM2_CH4
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN TIM2_MspPostInit 1 */
+
+  /* USER CODE END TIM2_MspPostInit 1 */
+  }
+
+}
+/**
+* @brief TIM_Base MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }
+  else if(htim_base->Instance==TIM3)
+  {
+  /* USER CODE BEGIN TIM3_MspDeInit 0 */
+
+  /* USER CODE END TIM3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM3_CLK_DISABLE();
+
+    /* TIM3 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(TIM3_IRQn);
+  /* USER CODE BEGIN TIM3_MspDeInit 1 */
+
+  /* USER CODE END TIM3_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+
+  /** Initializes the peripherals clocks
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+    PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USART1 GPIO Configuration
+    PA9     ------> USART1_TX
+    PA10     ------> USART1_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+
+    /**USART1 GPIO Configuration
+    PA9     ------> USART1_TX
+    PA10     ------> USART1_RX
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
+
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/squeow_sw/Src/stm32g4xx_it.c b/squeow_sw/Src/stm32g4xx_it.c
new file mode 100644
index 0000000..9b6ffb5
--- /dev/null
+++ b/squeow_sw/Src/stm32g4xx_it.c
@@ -0,0 +1,232 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32g4xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern PCD_HandleTypeDef hpcd_USB_FS;
+extern TIM_HandleTypeDef htim3;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M4 Processor Interruption and Exception Handlers          */
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+  while (1)
+  {
+  }
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32G4xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32g4xx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles USB low priority interrupt remap.
+  */
+void USB_LP_IRQHandler(void)
+{
+  /* USER CODE BEGIN USB_LP_IRQn 0 */
+
+  /* USER CODE END USB_LP_IRQn 0 */
+  HAL_PCD_IRQHandler(&hpcd_USB_FS);
+  /* USER CODE BEGIN USB_LP_IRQn 1 */
+
+  /* USER CODE END USB_LP_IRQn 1 */
+}
+
+/**
+  * @brief This function handles TIM3 global interrupt.
+  */
+void TIM3_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM3_IRQn 0 */
+
+  /* USER CODE END TIM3_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim3);
+  /* USER CODE BEGIN TIM3_IRQn 1 */
+
+  /* USER CODE END TIM3_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/squeow_sw/Src/system_stm32g4xx.c b/squeow_sw/Src/system_stm32g4xx.c
new file mode 100644
index 0000000..d20700b
--- /dev/null
+++ b/squeow_sw/Src/system_stm32g4xx.c
@@ -0,0 +1,285 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32g4xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32g4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the HSI (16 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | HSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 16000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 16000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 16
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for RNG                  | Disabled
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32g4xx_system
+  * @{
+  */
+
+/** @addtogroup STM32G4xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32g4xx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE     24000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32G4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32G4xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in Flash or Sram, else the vector table is kept at the automatic
+     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32G4xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32G4xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = HSI_VALUE;
+
+  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32G4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value
+  *              24 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, pllvco, pllr, pllsource, pllm;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x04:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C:  /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
+      if (pllsource == 0x02UL) /* HSI used as PLL clock source */
+      {
+        pllvco = (HSI_VALUE / pllm);
+      }
+      else                   /* HSE used as PLL clock source */
+      {
+        pllvco = (HSE_VALUE / pllm);
+      }
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
diff --git a/squeow_sw/Src/usb_device.c b/squeow_sw/Src/usb_device.c
new file mode 100644
index 0000000..52f2aec
--- /dev/null
+++ b/squeow_sw/Src/usb_device.c
@@ -0,0 +1,97 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usb_device.c
+  * @version        : v3.0_Cube
+  * @brief          : This file implements the USB Device
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "usb_device.h"
+#include "usbd_core.h"
+#include "usbd_desc.h"
+#include "usbd_audio.h"
+#include "usbd_audio_if.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+
+/* USER CODE END PFP */
+
+extern void Error_Handler(void);
+/* USB Device Core handle declaration. */
+USBD_HandleTypeDef hUsbDeviceFS;
+extern USBD_DescriptorsTypeDef AUDIO_Desc;
+
+/*
+ * -- Insert your variables declaration here --
+ */
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*
+ * -- Insert your external function declaration here --
+ */
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/**
+  * Init USB device Library, add supported class and start the library
+  * @retval None
+  */
+void MX_USB_Device_Init(void)
+{
+  /* USER CODE BEGIN USB_Device_Init_PreTreatment */
+
+  /* USER CODE END USB_Device_Init_PreTreatment */
+
+  /* Init Device Library, add supported class and start the library. */
+  if (USBD_Init(&hUsbDeviceFS, &AUDIO_Desc, DEVICE_FS) != USBD_OK) {
+    Error_Handler();
+  }
+  if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_AUDIO) != USBD_OK) {
+    Error_Handler();
+  }
+  if (USBD_AUDIO_RegisterInterface(&hUsbDeviceFS, &USBD_AUDIO_fops_FS) != USBD_OK) {
+    Error_Handler();
+  }
+  if (USBD_Start(&hUsbDeviceFS) != USBD_OK) {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USB_Device_Init_PostTreatment */
+
+  /* USER CODE END USB_Device_Init_PostTreatment */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/Src/usbd_audio_if.c b/squeow_sw/Src/usbd_audio_if.c
new file mode 100644
index 0000000..a1c32c7
--- /dev/null
+++ b/squeow_sw/Src/usbd_audio_if.c
@@ -0,0 +1,285 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_audio_if.c
+  * @version        : v3.0_Cube
+  * @brief          : Generic media access layer.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+ /* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_audio_if.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @brief Usb device library.
+  * @{
+  */
+
+/** @addtogroup USBD_AUDIO_IF
+  * @{
+  */
+
+/** @defgroup USBD_AUDIO_IF_Private_TypesDefinitions USBD_AUDIO_IF_Private_TypesDefinitions
+  * @brief Private types.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_TYPES */
+
+/* USER CODE END PRIVATE_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_AUDIO_IF_Private_Defines USBD_AUDIO_IF_Private_Defines
+  * @brief Private defines.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_DEFINES */
+
+/* USER CODE END PRIVATE_DEFINES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_AUDIO_IF_Private_Macros USBD_AUDIO_IF_Private_Macros
+  * @brief Private macros.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_MACRO */
+
+/* USER CODE END PRIVATE_MACRO */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_AUDIO_IF_Private_Variables USBD_AUDIO_IF_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_VARIABLES */
+
+/* USER CODE END PRIVATE_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_AUDIO_IF_Exported_Variables USBD_AUDIO_IF_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+extern USBD_HandleTypeDef hUsbDeviceFS;
+
+/* USER CODE BEGIN EXPORTED_VARIABLES */
+
+/* USER CODE END EXPORTED_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_AUDIO_IF_Private_FunctionPrototypes USBD_AUDIO_IF_Private_FunctionPrototypes
+  * @brief Private functions declaration.
+  * @{
+  */
+
+static int8_t AUDIO_Init_FS(uint32_t AudioFreq, uint32_t Volume, uint32_t options);
+static int8_t AUDIO_DeInit_FS(uint32_t options);
+static int8_t AUDIO_AudioCmd_FS(uint8_t* pbuf, uint32_t size, uint8_t cmd);
+static int8_t AUDIO_VolumeCtl_FS(uint8_t vol);
+static int8_t AUDIO_MuteCtl_FS(uint8_t cmd);
+static int8_t AUDIO_PeriodicTC_FS(uint8_t *pbuf, uint32_t size, uint8_t cmd);
+static int8_t AUDIO_GetState_FS(void);
+
+/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */
+
+/* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */
+
+/**
+  * @}
+  */
+
+USBD_AUDIO_ItfTypeDef USBD_AUDIO_fops_FS =
+{
+  AUDIO_Init_FS,
+  AUDIO_DeInit_FS,
+  AUDIO_AudioCmd_FS,
+  AUDIO_VolumeCtl_FS,
+  AUDIO_MuteCtl_FS,
+  AUDIO_PeriodicTC_FS,
+  AUDIO_GetState_FS,
+};
+
+/* Private functions ---------------------------------------------------------*/
+/**
+  * @brief  Initializes the AUDIO media low layer over USB FS IP
+  * @param  AudioFreq: Audio frequency used to play the audio stream.
+  * @param  Volume: Initial volume level (from 0 (Mute) to 100 (Max))
+  * @param  options: Reserved for future use
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+static int8_t AUDIO_Init_FS(uint32_t AudioFreq, uint32_t Volume, uint32_t options)
+{
+  /* USER CODE BEGIN 0 */
+  UNUSED(AudioFreq);
+  UNUSED(Volume);
+  UNUSED(options);
+  return (USBD_OK);
+  /* USER CODE END 0 */
+}
+
+/**
+  * @brief  De-Initializes the AUDIO media low layer
+  * @param  options: Reserved for future use
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+static int8_t AUDIO_DeInit_FS(uint32_t options)
+{
+  /* USER CODE BEGIN 1 */
+  UNUSED(options);
+  return (USBD_OK);
+  /* USER CODE END 1 */
+}
+
+/**
+  * @brief  Handles AUDIO command.
+  * @param  pbuf: Pointer to buffer of data to be sent
+  * @param  size: Number of data to be sent (in bytes)
+  * @param  cmd: Command opcode
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+static int8_t AUDIO_AudioCmd_FS(uint8_t* pbuf, uint32_t size, uint8_t cmd)
+{
+  /* USER CODE BEGIN 2 */
+  switch(cmd)
+  {
+    case AUDIO_CMD_START:
+    break;
+
+    case AUDIO_CMD_PLAY:
+    break;
+  }
+  UNUSED(pbuf);
+  UNUSED(size);
+  UNUSED(cmd);
+  return (USBD_OK);
+  /* USER CODE END 2 */
+}
+
+/**
+  * @brief  Controls AUDIO Volume.
+  * @param  vol: volume level (0..100)
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+static int8_t AUDIO_VolumeCtl_FS(uint8_t vol)
+{
+  /* USER CODE BEGIN 3 */
+  UNUSED(vol);
+  return (USBD_OK);
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief  Controls AUDIO Mute.
+  * @param  cmd: command opcode
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+static int8_t AUDIO_MuteCtl_FS(uint8_t cmd)
+{
+  /* USER CODE BEGIN 4 */
+  UNUSED(cmd);
+  return (USBD_OK);
+  /* USER CODE END 4 */
+}
+
+/**
+  * @brief  AUDIO_PeriodicT_FS
+  * @param  cmd: Command opcode
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+static int8_t AUDIO_PeriodicTC_FS(uint8_t *pbuf, uint32_t size, uint8_t cmd)
+{
+  /* USER CODE BEGIN 5 */
+  UNUSED(pbuf);
+  UNUSED(size);
+  UNUSED(cmd);
+  return (USBD_OK);
+  /* USER CODE END 5 */
+}
+
+/**
+  * @brief  Gets AUDIO State.
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+static int8_t AUDIO_GetState_FS(void)
+{
+  /* USER CODE BEGIN 6 */
+  return (USBD_OK);
+  /* USER CODE END 6 */
+}
+
+/**
+  * @brief  Manages the DMA full transfer complete event.
+  * @retval None
+  */
+void TransferComplete_CallBack_FS(void)
+{
+  /* USER CODE BEGIN 7 */
+  USBD_AUDIO_Sync(&hUsbDeviceFS, AUDIO_OFFSET_FULL);
+  /* USER CODE END 7 */
+}
+
+/**
+  * @brief  Manages the DMA Half transfer complete event.
+  * @retval None
+  */
+void HalfTransfer_CallBack_FS(void)
+{
+  /* USER CODE BEGIN 8 */
+  USBD_AUDIO_Sync(&hUsbDeviceFS, AUDIO_OFFSET_HALF);
+  /* USER CODE END 8 */
+}
+
+/* USER CODE BEGIN PRIVATE_FUNCTIONS_IMPLEMENTATION */
+
+/* USER CODE END PRIVATE_FUNCTIONS_IMPLEMENTATION */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/squeow_sw/Src/usbd_conf.c b/squeow_sw/Src/usbd_conf.c
new file mode 100644
index 0000000..1ffa62a
--- /dev/null
+++ b/squeow_sw/Src/usbd_conf.c
@@ -0,0 +1,795 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_conf.c
+  * @version        : v3.0_Cube
+  * @brief          : This file implements the board support package for the USB device library
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+#include "stm32g4xx_hal.h"
+#include "usbd_def.h"
+#include "usbd_core.h"
+
+#include "usbd_audio.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+PCD_HandleTypeDef hpcd_USB_FS;
+void Error_Handler(void);
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* Exported function prototypes ----------------------------------------------*/
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+
+/* USER CODE END PFP */
+
+/* Private functions ---------------------------------------------------------*/
+static USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status);
+/* USER CODE BEGIN 1 */
+static void SystemClockConfig_Resume(void);
+
+/* USER CODE END 1 */
+extern void SystemClock_Config(void);
+
+/*******************************************************************************
+                       LL Driver Callbacks (PCD -> USB Device Library)
+*******************************************************************************/
+/* MSP Init */
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
+#else
+void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(pcdHandle->Instance==USB)
+  {
+  /* USER CODE BEGIN USB_MspInit 0 */
+
+  /* USER CODE END USB_MspInit 0 */
+
+  /** Initializes the peripherals clocks
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_USB_CLK_ENABLE();
+
+    /* Peripheral interrupt init */
+    HAL_NVIC_SetPriority(USB_LP_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USB_LP_IRQn);
+  /* USER CODE BEGIN USB_MspInit 1 */
+
+  /* USER CODE END USB_MspInit 1 */
+  }
+}
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
+#else
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  if(pcdHandle->Instance==USB)
+  {
+  /* USER CODE BEGIN USB_MspDeInit 0 */
+
+  /* USER CODE END USB_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USB_CLK_DISABLE();
+
+    /* Peripheral interrupt Deinit*/
+    HAL_NVIC_DisableIRQ(USB_LP_IRQn);
+
+  /* USER CODE BEGIN USB_MspDeInit 1 */
+
+  /* USER CODE END USB_MspDeInit 1 */
+  }
+}
+
+/**
+  * @brief  Setup stage callback
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PreTreatment */
+
+  /* USER CODE END  HAL_PCD_SetupStageCallback_PreTreatment */
+  USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
+  /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PostTreatment */
+
+  /* USER CODE END  HAL_PCD_SetupStageCallback_PostTreatment */
+}
+
+/**
+  * @brief  Data Out stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_DataOutStageCallback_PreTreatment */
+  USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
+  /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_DataOutStageCallback_PostTreatment */
+}
+
+/**
+  * @brief  Data In stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_DataInStageCallback_PreTreatment */
+  USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
+  /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PostTreatment  */
+
+  /* USER CODE END HAL_PCD_DataInStageCallback_PostTreatment */
+}
+
+/**
+  * @brief  SOF callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_SOFCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_SOFCallback_PreTreatment */
+  USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_SOFCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_SOFCallback_PostTreatment */
+}
+
+/**
+  * @brief  Reset callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ResetCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_ResetCallback_PreTreatment */
+  USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
+
+  if ( hpcd->Init.speed != PCD_SPEED_FULL)
+  {
+    Error_Handler();
+  }
+    /* Set Speed. */
+  USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
+
+  /* Reset Device. */
+  USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_ResetCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_ResetCallback_PostTreatment */
+}
+
+/**
+  * @brief  Suspend callback.
+  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_SuspendCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_SuspendCallback_PreTreatment */
+  /* Inform USB library that core enters in suspend Mode. */
+  USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
+  /* Enter in STOP mode. */
+  /* USER CODE BEGIN 2 */
+  if (hpcd->Init.low_power_enable)
+  {
+    /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
+    SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+  }
+  /* USER CODE END 2 */
+  /* USER CODE BEGIN HAL_PCD_SuspendCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_SuspendCallback_PostTreatment */
+}
+
+/**
+  * @brief  Resume callback.
+  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ResumeCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_ResumeCallback_PreTreatment */
+
+  /* USER CODE BEGIN 3 */
+  if (hpcd->Init.low_power_enable)
+  {
+    /* Reset SLEEPDEEP bit of Cortex System Control Register. */
+    SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+    SystemClockConfig_Resume();
+  }
+  /* USER CODE END 3 */
+
+  USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_ResumeCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_ResumeCallback_PostTreatment */
+}
+
+/**
+  * @brief  ISOOUTIncomplete callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ISOOUTIncompleteCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_ISOOUTIncompleteCallback_PreTreatment */
+  USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+  /* USER CODE BEGIN HAL_PCD_ISOOUTIncompleteCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_ISOOUTIncompleteCallback_PostTreatment */
+}
+
+/**
+  * @brief  ISOINIncomplete callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ISOINIncompleteCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_ISOINIncompleteCallback_PreTreatment */
+  USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+  /* USER CODE BEGIN HAL_PCD_ISOINIncompleteCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_ISOINIncompleteCallback_PostTreatment */
+}
+
+/**
+  * @brief  Connect callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_ConnectCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_ConnectCallback_PreTreatment */
+  USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_ConnectCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_ConnectCallback_PostTreatment */
+}
+
+/**
+  * @brief  Disconnect callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN HAL_PCD_DisconnectCallback_PreTreatment */
+
+  /* USER CODE END HAL_PCD_DisconnectCallback_PreTreatment */
+  USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
+  /* USER CODE BEGIN HAL_PCD_DisconnectCallback_PostTreatment */
+
+  /* USER CODE END HAL_PCD_DisconnectCallback_PostTreatment */
+}
+
+  /* USER CODE BEGIN LowLevelInterface */
+
+  /* USER CODE END LowLevelInterface */
+
+/*******************************************************************************
+                       LL Driver Interface (USB Device Library --> PCD)
+*******************************************************************************/
+
+/**
+  * @brief  Initializes the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
+{
+  /* Init USB Ip. */
+  hpcd_USB_FS.pData = pdev;
+  /* Link the driver to the stack. */
+  pdev->pData = &hpcd_USB_FS;
+
+  hpcd_USB_FS.Instance = USB;
+  hpcd_USB_FS.Init.dev_endpoints = 8;
+  hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
+  hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
+  hpcd_USB_FS.Init.Sof_enable = DISABLE;
+  hpcd_USB_FS.Init.low_power_enable = DISABLE;
+  hpcd_USB_FS.Init.lpm_enable = DISABLE;
+  hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
+
+  #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  /* register Msp Callbacks (before the Init) */
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPINIT_CB_ID, PCD_MspInit);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPDEINIT_CB_ID, PCD_MspDeInit);
+  #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+  if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
+  {
+    Error_Handler( );
+  }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  /* Register USB PCD CallBacks */
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback);
+  /* USER CODE BEGIN RegisterCallBackFirstPart */
+
+  /* USER CODE END RegisterCallBackFirstPart */
+  HAL_PCD_RegisterLpmCallback(&hpcd_USB_FS, PCDEx_LPM_Callback);
+  HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_FS, PCD_DataOutStageCallback);
+  HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback);
+  HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback);
+  HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback);
+  /* USER CODE BEGIN RegisterCallBackSecondPart */
+
+  /* USER CODE END RegisterCallBackSecondPart */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  /* USER CODE BEGIN EndPoint_Configuration */
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, 0x00, PCD_SNG_BUF, 0x10);
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, 0x80, PCD_SNG_BUF, 0x50);
+  /* USER CODE END EndPoint_Configuration */
+  /* USER CODE BEGIN EndPoint_Configuration_AUDIO */
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, AUDIO_OUT_EP, PCD_DBL_BUF, 0x01500090);
+  /* USER CODE END EndPoint_Configuration_AUDIO */
+  return USBD_OK;
+}
+
+/**
+  * @brief  De-Initializes the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_DeInit(pdev->pData);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Starts the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_Start(pdev->pData);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Stops the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_Stop(pdev->pData);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Opens an endpoint of the low level driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  ep_type: Endpoint type
+  * @param  ep_mps: Endpoint max packet size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Closes an endpoint of the low level driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Flushes an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Sets a Stall condition on an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Clears a Stall condition on an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Returns Stall condition.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval Stall (1: Yes, 0: No)
+  */
+uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
+
+  if((ep_addr & 0x80) == 0x80)
+  {
+    return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
+  }
+  else
+  {
+    return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
+  }
+}
+
+/**
+  * @brief  Assigns a USB address to the device.
+  * @param  pdev: Device handle
+  * @param  dev_addr: Device address
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Transmits data over an endpoint.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  pbuf: Pointer to data to be sent
+  * @param  size: Data size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Prepares an endpoint for reception.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  pbuf: Pointer to data to be received
+  * @param  size: Data size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Returns the last transferred packet size.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval Received Data Size
+  */
+uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
+}
+
+/**
+  * @brief  Send LPM message to user layer
+  * @param  hpcd: PCD handle
+  * @param  msg: LPM message
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+#else
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN LPM_Callback */
+  switch (msg)
+  {
+  case PCD_LPM_L0_ACTIVE:
+    if (hpcd->Init.low_power_enable)
+    {
+      SystemClockConfig_Resume();
+
+      /* Reset SLEEPDEEP bit of Cortex System Control Register. */
+      SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+    }
+    USBD_LL_Resume(hpcd->pData);
+    break;
+
+  case PCD_LPM_L1_ACTIVE:
+    USBD_LL_Suspend(hpcd->pData);
+
+    /* Enter in STOP mode. */
+    if (hpcd->Init.low_power_enable)
+    {
+      /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
+      SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+    }
+    break;
+  }
+  /* USER CODE END LPM_Callback */
+}
+
+/**
+  * @brief  Delays routine for the USB Device Library.
+  * @param  Delay: Delay in ms
+  * @retval None
+  */
+void USBD_LL_Delay(uint32_t Delay)
+{
+  HAL_Delay(Delay);
+}
+
+/**
+  * @brief  Static single allocation.
+  * @param  size: Size of allocated memory
+  * @retval None
+  */
+void *USBD_static_malloc(uint32_t size)
+{
+  static uint32_t mem[(sizeof(USBD_AUDIO_HandleTypeDef)/4)+1];/* On 32-bit boundary */
+  return mem;
+}
+
+/**
+  * @brief  Dummy memory free
+  * @param  p: Pointer to allocated  memory address
+  * @retval None
+  */
+void USBD_static_free(void *p)
+{
+
+}
+
+/* USER CODE BEGIN 5 */
+/**
+  * @brief  Configures system clock after wake-up from USB resume callBack:
+  *         enable HSI, PLL and select PLL as system clock source.
+  * @retval None
+  */
+static void SystemClockConfig_Resume(void)
+{
+  SystemClock_Config();
+}
+/* USER CODE END 5 */
+
+/**
+  * @brief  Returns the USB status depending on the HAL status:
+  * @param  hal_status: HAL status
+  * @retval USB status
+  */
+USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
+{
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  switch (hal_status)
+  {
+    case HAL_OK :
+      usb_status = USBD_OK;
+    break;
+    case HAL_ERROR :
+      usb_status = USBD_FAIL;
+    break;
+    case HAL_BUSY :
+      usb_status = USBD_BUSY;
+    break;
+    case HAL_TIMEOUT :
+      usb_status = USBD_FAIL;
+    break;
+    default :
+      usb_status = USBD_FAIL;
+    break;
+  }
+  return usb_status;
+}
diff --git a/squeow_sw/Src/usbd_desc.c b/squeow_sw/Src/usbd_desc.c
new file mode 100644
index 0000000..7de84e4
--- /dev/null
+++ b/squeow_sw/Src/usbd_desc.c
@@ -0,0 +1,396 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_desc.c
+  * @version        : v3.0_Cube
+  * @brief          : This file implements the USB device descriptors.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_core.h"
+#include "usbd_desc.h"
+#include "usbd_conf.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @addtogroup USBD_DESC
+  * @{
+  */
+
+/** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions
+  * @brief Private types.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_TYPES */
+
+/* USER CODE END PRIVATE_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines
+  * @brief Private defines.
+  * @{
+  */
+
+#define USBD_VID     1155
+#define USBD_LANGID_STRING     1033
+#define USBD_MANUFACTURER_STRING     "STMicroelectronics"
+#define USBD_PID     22336
+#define USBD_PRODUCT_STRING     "STM32 Audio Class"
+#define USBD_CONFIGURATION_STRING     "AUDIO Config"
+#define USBD_INTERFACE_STRING     "AUDIO Interface"
+
+/* USER CODE BEGIN PRIVATE_DEFINES */
+
+/* USER CODE END PRIVATE_DEFINES */
+
+/**
+  * @}
+  */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros
+  * @brief Private macros.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_MACRO */
+
+/* USER CODE END PRIVATE_MACRO */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  * @brief Private functions declaration.
+  * @{
+  */
+
+static void Get_SerialNum(void);
+static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len);
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  * @brief Private functions declaration.
+  * @{
+  */
+
+uint8_t * USBD_AUDIO_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_AUDIO_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_AUDIO_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_AUDIO_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_AUDIO_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_AUDIO_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_AUDIO_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+USBD_DescriptorsTypeDef AUDIO_Desc =
+{
+  USBD_AUDIO_DeviceDescriptor,
+  USBD_AUDIO_LangIDStrDescriptor,
+  USBD_AUDIO_ManufacturerStrDescriptor,
+  USBD_AUDIO_ProductStrDescriptor,
+  USBD_AUDIO_SerialStrDescriptor,
+  USBD_AUDIO_ConfigStrDescriptor,
+  USBD_AUDIO_InterfaceStrDescriptor
+};
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+/** USB standard device descriptor. */
+__ALIGN_BEGIN uint8_t USBD_AUDIO_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END =
+{
+  0x12,                       /*bLength */
+  USB_DESC_TYPE_DEVICE,       /*bDescriptorType*/
+  0x00,                       /*bcdUSB */
+  0x02,
+  0x00,                       /*bDeviceClass*/
+  0x00,                       /*bDeviceSubClass*/
+  0x00,                       /*bDeviceProtocol*/
+  USB_MAX_EP0_SIZE,           /*bMaxPacketSize*/
+  LOBYTE(USBD_VID),           /*idVendor*/
+  HIBYTE(USBD_VID),           /*idVendor*/
+  LOBYTE(USBD_PID),           /*idProduct*/
+  HIBYTE(USBD_PID),           /*idProduct*/
+  0x00,                       /*bcdDevice rel. 2.00*/
+  0x02,
+  USBD_IDX_MFC_STR,           /*Index of manufacturer  string*/
+  USBD_IDX_PRODUCT_STR,       /*Index of product string*/
+  USBD_IDX_SERIAL_STR,        /*Index of serial number string*/
+  USBD_MAX_NUM_CONFIGURATION  /*bNumConfigurations*/
+};
+
+/* USB_DeviceDescriptor */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+
+/** USB lang identifier descriptor. */
+__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =
+{
+     USB_LEN_LANGID_STR_DESC,
+     USB_DESC_TYPE_STRING,
+     LOBYTE(USBD_LANGID_STRING),
+     HIBYTE(USBD_LANGID_STRING)
+};
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+/* Internal string descriptor. */
+__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
+
+#if defined ( __ICCARM__ ) /*!< IAR Compiler */
+  #pragma data_alignment=4
+#endif
+__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = {
+  USB_SIZ_STRING_SERIAL,
+  USB_DESC_TYPE_STRING,
+};
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions
+  * @brief Private functions.
+  * @{
+  */
+
+/**
+  * @brief  Return the device descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_AUDIO_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = sizeof(USBD_AUDIO_DeviceDesc);
+  return USBD_AUDIO_DeviceDesc;
+}
+
+/**
+  * @brief  Return the LangID string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_AUDIO_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = sizeof(USBD_LangIDDesc);
+  return USBD_LangIDDesc;
+}
+
+/**
+  * @brief  Return the product string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_AUDIO_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the manufacturer string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_AUDIO_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the serial number string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_AUDIO_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = USB_SIZ_STRING_SERIAL;
+
+  /* Update the serial number string descriptor with the data from the unique
+   * ID */
+  Get_SerialNum();
+
+  /* USER CODE BEGIN USBD_AUDIO_SerialStrDescriptor */
+
+  /* USER CODE END USBD_AUDIO_SerialStrDescriptor */
+
+  return (uint8_t *) USBD_StringSerial;
+}
+
+/**
+  * @brief  Return the configuration string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_AUDIO_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == USBD_SPEED_HIGH)
+  {
+    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the interface string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_AUDIO_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Create the serial number string descriptor
+  * @param  None
+  * @retval None
+  */
+static void Get_SerialNum(void)
+{
+  uint32_t deviceserial0;
+  uint32_t deviceserial1;
+  uint32_t deviceserial2;
+
+  deviceserial0 = *(uint32_t *) DEVICE_ID1;
+  deviceserial1 = *(uint32_t *) DEVICE_ID2;
+  deviceserial2 = *(uint32_t *) DEVICE_ID3;
+
+  deviceserial0 += deviceserial2;
+
+  if (deviceserial0 != 0)
+  {
+    IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
+    IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
+  }
+}
+
+/**
+  * @brief  Convert Hex 32Bits value into char
+  * @param  value: value to convert
+  * @param  pbuf: pointer to the buffer
+  * @param  len: buffer length
+  * @retval None
+  */
+static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
+{
+  uint8_t idx = 0;
+
+  for (idx = 0; idx < len; idx++)
+  {
+    if (((value >> 28)) < 0xA)
+    {
+      pbuf[2 * idx] = (value >> 28) + '0';
+    }
+    else
+    {
+      pbuf[2 * idx] = (value >> 28) + 'A' - 10;
+    }
+
+    value = value << 4;
+
+    pbuf[2 * idx + 1] = 0;
+  }
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/squeow_sw/build/main.d b/squeow_sw/build/main.d
new file mode 100644
index 0000000..01064b9
--- /dev/null
+++ b/squeow_sw/build/main.d
@@ -0,0 +1,81 @@
+build/main.o: Src/main.c Inc/main.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h \
+ Inc/usb_device.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \
+ Inc/usbd_conf.h Inc/si5351.h
+Inc/main.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
+Inc/usb_device.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
+Inc/usbd_conf.h:
+Inc/si5351.h:
diff --git a/squeow_sw/build/main.lst b/squeow_sw/build/main.lst
new file mode 100644
index 0000000..b77797f
--- /dev/null
+++ b/squeow_sw/build/main.lst
@@ -0,0 +1,2832 @@
+ARM GAS  /tmp/cc8GRwsk.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"main.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Src/main.c"
+  20              		.section	.text.MX_GPIO_Init,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	MX_GPIO_Init:
+  27              	.LFB341:
+   1:Src/main.c    **** /* USER CODE BEGIN Header */
+   2:Src/main.c    **** /**
+   3:Src/main.c    ****   ******************************************************************************
+   4:Src/main.c    ****   * @file           : main.c
+   5:Src/main.c    ****   * @brief          : Main program body
+   6:Src/main.c    ****   ******************************************************************************
+   7:Src/main.c    ****   * @attention
+   8:Src/main.c    ****   *
+   9:Src/main.c    ****   * Copyright (c) 2022 STMicroelectronics.
+  10:Src/main.c    ****   * All rights reserved.
+  11:Src/main.c    ****   *
+  12:Src/main.c    ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Src/main.c    ****   * in the root directory of this software component.
+  14:Src/main.c    ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Src/main.c    ****   *
+  16:Src/main.c    ****   ******************************************************************************
+  17:Src/main.c    ****   */
+  18:Src/main.c    **** /* USER CODE END Header */
+  19:Src/main.c    **** /* Includes ------------------------------------------------------------------*/
+  20:Src/main.c    **** #include "main.h"
+  21:Src/main.c    **** #include "usb_device.h"
+  22:Src/main.c    **** 
+  23:Src/main.c    **** /* Private includes ----------------------------------------------------------*/
+  24:Src/main.c    **** /* USER CODE BEGIN Includes */
+  25:Src/main.c    **** #include "si5351.h"
+  26:Src/main.c    ****  
+  27:Src/main.c    **** /* USER CODE END Includes */
+  28:Src/main.c    **** 
+  29:Src/main.c    **** /* Private typedef -----------------------------------------------------------*/
+  30:Src/main.c    **** /* USER CODE BEGIN PTD */
+  31:Src/main.c    **** 
+ARM GAS  /tmp/cc8GRwsk.s 			page 2
+
+
+  32:Src/main.c    **** /* USER CODE END PTD */
+  33:Src/main.c    **** 
+  34:Src/main.c    **** /* Private define ------------------------------------------------------------*/
+  35:Src/main.c    **** /* USER CODE BEGIN PD */
+  36:Src/main.c    **** /* USER CODE END PD */
+  37:Src/main.c    **** 
+  38:Src/main.c    **** /* Private macro -------------------------------------------------------------*/
+  39:Src/main.c    **** /* USER CODE BEGIN PM */
+  40:Src/main.c    **** 
+  41:Src/main.c    **** /* USER CODE END PM */
+  42:Src/main.c    **** 
+  43:Src/main.c    **** /* Private variables ---------------------------------------------------------*/
+  44:Src/main.c    **** ADC_HandleTypeDef hadc1;
+  45:Src/main.c    **** ADC_HandleTypeDef hadc2;
+  46:Src/main.c    **** 
+  47:Src/main.c    **** I2C_HandleTypeDef hi2c1;
+  48:Src/main.c    **** 
+  49:Src/main.c    **** TIM_HandleTypeDef htim2;
+  50:Src/main.c    **** TIM_HandleTypeDef htim3;
+  51:Src/main.c    **** 
+  52:Src/main.c    **** UART_HandleTypeDef huart1;
+  53:Src/main.c    **** 
+  54:Src/main.c    **** /* USER CODE BEGIN PV */
+  55:Src/main.c    **** 
+  56:Src/main.c    **** /* USER CODE END PV */
+  57:Src/main.c    **** 
+  58:Src/main.c    **** /* Private function prototypes -----------------------------------------------*/
+  59:Src/main.c    **** void SystemClock_Config(void);
+  60:Src/main.c    **** static void MX_GPIO_Init(void);
+  61:Src/main.c    **** static void MX_TIM2_Init(void);
+  62:Src/main.c    **** static void MX_I2C1_Init(void);
+  63:Src/main.c    **** static void MX_TIM3_Init(void);
+  64:Src/main.c    **** static void MX_ADC1_Init(void);
+  65:Src/main.c    **** static void MX_ADC2_Init(void);
+  66:Src/main.c    **** static void MX_USART1_UART_Init(void);
+  67:Src/main.c    **** /* USER CODE BEGIN PFP */
+  68:Src/main.c    **** 
+  69:Src/main.c    **** /* USER CODE END PFP */
+  70:Src/main.c    **** 
+  71:Src/main.c    **** /* Private user code ---------------------------------------------------------*/
+  72:Src/main.c    **** /* USER CODE BEGIN 0 */
+  73:Src/main.c    **** 
+  74:Src/main.c    **** /* USER CODE END 0 */
+  75:Src/main.c    **** 
+  76:Src/main.c    **** /**
+  77:Src/main.c    ****   * @brief  The application entry point.
+  78:Src/main.c    ****   * @retval int
+  79:Src/main.c    ****   */
+  80:Src/main.c    **** int main(void)
+  81:Src/main.c    **** {
+  82:Src/main.c    ****   /* USER CODE BEGIN 1 */
+  83:Src/main.c    **** 
+  84:Src/main.c    ****   /* USER CODE END 1 */
+  85:Src/main.c    **** 
+  86:Src/main.c    ****   /* MCU Configuration--------------------------------------------------------*/
+  87:Src/main.c    **** 
+  88:Src/main.c    ****   /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ARM GAS  /tmp/cc8GRwsk.s 			page 3
+
+
+  89:Src/main.c    ****   HAL_Init();
+  90:Src/main.c    **** 
+  91:Src/main.c    ****   /* USER CODE BEGIN Init */
+  92:Src/main.c    **** 
+  93:Src/main.c    ****   /* USER CODE END Init */
+  94:Src/main.c    **** 
+  95:Src/main.c    ****   /* Configure the system clock */
+  96:Src/main.c    ****   SystemClock_Config();
+  97:Src/main.c    **** 
+  98:Src/main.c    ****   /* USER CODE BEGIN SysInit */
+  99:Src/main.c    **** 
+ 100:Src/main.c    ****   /* USER CODE END SysInit */
+ 101:Src/main.c    **** 
+ 102:Src/main.c    ****   /* Initialize all configured peripherals */
+ 103:Src/main.c    ****   MX_GPIO_Init();
+ 104:Src/main.c    ****   MX_TIM2_Init();
+ 105:Src/main.c    ****   MX_I2C1_Init();
+ 106:Src/main.c    ****   MX_TIM3_Init();
+ 107:Src/main.c    ****   MX_ADC1_Init();
+ 108:Src/main.c    ****   MX_ADC2_Init();
+ 109:Src/main.c    ****   MX_USART1_UART_Init();
+ 110:Src/main.c    ****   MX_USB_Device_Init();
+ 111:Src/main.c    ****   /* USER CODE BEGIN 2 */
+ 112:Src/main.c    **** 
+ 113:Src/main.c    ****    HAL_TIM_Base_Start_IT(&htim2);
+ 114:Src/main.c    ****    HAL_TIM_Base_Start_IT(&htim3);
+ 115:Src/main.c    **** 
+ 116:Src/main.c    **** 	HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
+ 117:Src/main.c    ****         HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_2);
+ 118:Src/main.c    ****         HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_3);
+ 119:Src/main.c    ****         HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4);
+ 120:Src/main.c    **** 
+ 121:Src/main.c    **** 	HAL_Delay(10);
+ 122:Src/main.c    **** 	si5351_initialize();
+ 123:Src/main.c    ****         HAL_Delay(10);
+ 124:Src/main.c    ****         si5351_on_clk(0);
+ 125:Src/main.c    ****         si5351_on_clk(1);
+ 126:Src/main.c    ****         si5351_set_frequency(1000000,0);
+ 127:Src/main.c    ****         si5351_set_frequency(1000000,1);
+ 128:Src/main.c    **** 
+ 129:Src/main.c    ****   /* USER CODE END 2 */
+ 130:Src/main.c    **** 
+ 131:Src/main.c    ****   /* Infinite loop */
+ 132:Src/main.c    ****   /* USER CODE BEGIN WHILE */
+ 133:Src/main.c    ****   while (1)
+ 134:Src/main.c    ****   {
+ 135:Src/main.c    ****     /* USER CODE END WHILE */
+ 136:Src/main.c    **** 
+ 137:Src/main.c    ****     /* USER CODE BEGIN 3 */
+ 138:Src/main.c    **** //	HAL_GPIO_TogglePin(LED_GPIO_Port, LED_Pin);
+ 139:Src/main.c    **** 
+ 140:Src/main.c    **** //                TIM2->CCR1 = pwm_value > 1024 ? 1024 : pwm_value;
+ 141:Src/main.c    **** //                TIM2->CCR2 = pwm_value > 2048 ? 1024 : sat_sub(pwm_value,1024) & 1023;
+ 142:Src/main.c    **** //                TIM2->CCR3 = pwm_value > 3072 ? 1024 : sat_sub(pwm_value,2048) & 1023;
+ 143:Src/main.c    **** //                TIM2->CCR4 = pwm_value > 4096 ? 1024 : sat_sub(pwm_value,3072) & 1023;
+ 144:Src/main.c    ****         HAL_Delay(10);
+ 145:Src/main.c    ****         si5351_set_frequency(1000000,0);
+ARM GAS  /tmp/cc8GRwsk.s 			page 4
+
+
+ 146:Src/main.c    ****         si5351_set_frequency(1000000,1);
+ 147:Src/main.c    **** 
+ 148:Src/main.c    ****   }
+ 149:Src/main.c    ****   /* USER CODE END 3 */
+ 150:Src/main.c    **** }
+ 151:Src/main.c    **** 
+ 152:Src/main.c    **** /**
+ 153:Src/main.c    ****   * @brief System Clock Configuration
+ 154:Src/main.c    ****   * @retval None
+ 155:Src/main.c    ****   */
+ 156:Src/main.c    **** void SystemClock_Config(void)
+ 157:Src/main.c    **** {
+ 158:Src/main.c    ****   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 159:Src/main.c    ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 160:Src/main.c    **** 
+ 161:Src/main.c    ****   /** Configure the main internal regulator output voltage
+ 162:Src/main.c    ****   */
+ 163:Src/main.c    ****   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+ 164:Src/main.c    **** 
+ 165:Src/main.c    ****   /** Initializes the RCC Oscillators according to the specified parameters
+ 166:Src/main.c    ****   * in the RCC_OscInitTypeDef structure.
+ 167:Src/main.c    ****   */
+ 168:Src/main.c    ****   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
+ 169:Src/main.c    ****   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ 170:Src/main.c    ****   RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ 171:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ 172:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ 173:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
+ 174:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLN = 32;
+ 175:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ 176:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
+ 177:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+ 178:Src/main.c    ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 179:Src/main.c    ****   {
+ 180:Src/main.c    ****     Error_Handler();
+ 181:Src/main.c    ****   }
+ 182:Src/main.c    **** 
+ 183:Src/main.c    ****   /** Initializes the CPU, AHB and APB buses clocks
+ 184:Src/main.c    ****   */
+ 185:Src/main.c    ****   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ 186:Src/main.c    ****                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ 187:Src/main.c    ****   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ 188:Src/main.c    ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 189:Src/main.c    ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ 190:Src/main.c    ****   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ 191:Src/main.c    **** 
+ 192:Src/main.c    ****   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+ 193:Src/main.c    ****   {
+ 194:Src/main.c    ****     Error_Handler();
+ 195:Src/main.c    ****   }
+ 196:Src/main.c    ****   HAL_RCC_MCOConfig(RCC_MCO_PG10, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1);
+ 197:Src/main.c    **** }
+ 198:Src/main.c    **** 
+ 199:Src/main.c    **** /**
+ 200:Src/main.c    ****   * @brief ADC1 Initialization Function
+ 201:Src/main.c    ****   * @param None
+ 202:Src/main.c    ****   * @retval None
+ARM GAS  /tmp/cc8GRwsk.s 			page 5
+
+
+ 203:Src/main.c    ****   */
+ 204:Src/main.c    **** static void MX_ADC1_Init(void)
+ 205:Src/main.c    **** {
+ 206:Src/main.c    **** 
+ 207:Src/main.c    ****   /* USER CODE BEGIN ADC1_Init 0 */
+ 208:Src/main.c    **** 
+ 209:Src/main.c    ****   /* USER CODE END ADC1_Init 0 */
+ 210:Src/main.c    **** 
+ 211:Src/main.c    ****   ADC_MultiModeTypeDef multimode = {0};
+ 212:Src/main.c    ****   ADC_ChannelConfTypeDef sConfig = {0};
+ 213:Src/main.c    **** 
+ 214:Src/main.c    ****   /* USER CODE BEGIN ADC1_Init 1 */
+ 215:Src/main.c    **** 
+ 216:Src/main.c    ****   /* USER CODE END ADC1_Init 1 */
+ 217:Src/main.c    **** 
+ 218:Src/main.c    ****   /** Common config
+ 219:Src/main.c    ****   */
+ 220:Src/main.c    ****   hadc1.Instance = ADC1;
+ 221:Src/main.c    ****   hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
+ 222:Src/main.c    ****   hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+ 223:Src/main.c    ****   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 224:Src/main.c    ****   hadc1.Init.GainCompensation = 0;
+ 225:Src/main.c    ****   hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+ 226:Src/main.c    ****   hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 227:Src/main.c    ****   hadc1.Init.LowPowerAutoWait = DISABLE;
+ 228:Src/main.c    ****   hadc1.Init.ContinuousConvMode = DISABLE;
+ 229:Src/main.c    ****   hadc1.Init.NbrOfConversion = 1;
+ 230:Src/main.c    ****   hadc1.Init.DiscontinuousConvMode = DISABLE;
+ 231:Src/main.c    ****   hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 232:Src/main.c    ****   hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 233:Src/main.c    ****   hadc1.Init.DMAContinuousRequests = DISABLE;
+ 234:Src/main.c    ****   hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+ 235:Src/main.c    ****   hadc1.Init.OversamplingMode = DISABLE;
+ 236:Src/main.c    ****   if (HAL_ADC_Init(&hadc1) != HAL_OK)
+ 237:Src/main.c    ****   {
+ 238:Src/main.c    ****     Error_Handler();
+ 239:Src/main.c    ****   }
+ 240:Src/main.c    **** 
+ 241:Src/main.c    ****   /** Configure the ADC multi-mode
+ 242:Src/main.c    ****   */
+ 243:Src/main.c    ****   multimode.Mode = ADC_MODE_INDEPENDENT;
+ 244:Src/main.c    ****   if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
+ 245:Src/main.c    ****   {
+ 246:Src/main.c    ****     Error_Handler();
+ 247:Src/main.c    ****   }
+ 248:Src/main.c    **** 
+ 249:Src/main.c    ****   /** Configure Regular Channel
+ 250:Src/main.c    ****   */
+ 251:Src/main.c    ****   sConfig.Channel = ADC_CHANNEL_15;
+ 252:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_1;
+ 253:Src/main.c    ****   sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
+ 254:Src/main.c    ****   sConfig.SingleDiff = ADC_SINGLE_ENDED;
+ 255:Src/main.c    ****   sConfig.OffsetNumber = ADC_OFFSET_NONE;
+ 256:Src/main.c    ****   sConfig.Offset = 0;
+ 257:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 258:Src/main.c    ****   {
+ 259:Src/main.c    ****     Error_Handler();
+ARM GAS  /tmp/cc8GRwsk.s 			page 6
+
+
+ 260:Src/main.c    ****   }
+ 261:Src/main.c    ****   /* USER CODE BEGIN ADC1_Init 2 */
+ 262:Src/main.c    **** 
+ 263:Src/main.c    ****   /* USER CODE END ADC1_Init 2 */
+ 264:Src/main.c    **** 
+ 265:Src/main.c    **** }
+ 266:Src/main.c    **** 
+ 267:Src/main.c    **** /**
+ 268:Src/main.c    ****   * @brief ADC2 Initialization Function
+ 269:Src/main.c    ****   * @param None
+ 270:Src/main.c    ****   * @retval None
+ 271:Src/main.c    ****   */
+ 272:Src/main.c    **** static void MX_ADC2_Init(void)
+ 273:Src/main.c    **** {
+ 274:Src/main.c    **** 
+ 275:Src/main.c    ****   /* USER CODE BEGIN ADC2_Init 0 */
+ 276:Src/main.c    **** 
+ 277:Src/main.c    ****   /* USER CODE END ADC2_Init 0 */
+ 278:Src/main.c    **** 
+ 279:Src/main.c    ****   ADC_ChannelConfTypeDef sConfig = {0};
+ 280:Src/main.c    **** 
+ 281:Src/main.c    ****   /* USER CODE BEGIN ADC2_Init 1 */
+ 282:Src/main.c    **** 
+ 283:Src/main.c    ****   /* USER CODE END ADC2_Init 1 */
+ 284:Src/main.c    **** 
+ 285:Src/main.c    ****   /** Common config
+ 286:Src/main.c    ****   */
+ 287:Src/main.c    ****   hadc2.Instance = ADC2;
+ 288:Src/main.c    ****   hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
+ 289:Src/main.c    ****   hadc2.Init.Resolution = ADC_RESOLUTION_12B;
+ 290:Src/main.c    ****   hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 291:Src/main.c    ****   hadc2.Init.GainCompensation = 0;
+ 292:Src/main.c    ****   hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
+ 293:Src/main.c    ****   hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
+ 294:Src/main.c    ****   hadc2.Init.LowPowerAutoWait = DISABLE;
+ 295:Src/main.c    ****   hadc2.Init.ContinuousConvMode = DISABLE;
+ 296:Src/main.c    ****   hadc2.Init.NbrOfConversion = 4;
+ 297:Src/main.c    ****   hadc2.Init.DiscontinuousConvMode = DISABLE;
+ 298:Src/main.c    ****   hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 299:Src/main.c    ****   hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 300:Src/main.c    ****   hadc2.Init.DMAContinuousRequests = DISABLE;
+ 301:Src/main.c    ****   hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+ 302:Src/main.c    ****   hadc2.Init.OversamplingMode = DISABLE;
+ 303:Src/main.c    ****   if (HAL_ADC_Init(&hadc2) != HAL_OK)
+ 304:Src/main.c    ****   {
+ 305:Src/main.c    ****     Error_Handler();
+ 306:Src/main.c    ****   }
+ 307:Src/main.c    **** 
+ 308:Src/main.c    ****   /** Configure Regular Channel
+ 309:Src/main.c    ****   */
+ 310:Src/main.c    ****   sConfig.Channel = ADC_CHANNEL_3;
+ 311:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_1;
+ 312:Src/main.c    ****   sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
+ 313:Src/main.c    ****   sConfig.SingleDiff = ADC_SINGLE_ENDED;
+ 314:Src/main.c    ****   sConfig.OffsetNumber = ADC_OFFSET_NONE;
+ 315:Src/main.c    ****   sConfig.Offset = 0;
+ 316:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ARM GAS  /tmp/cc8GRwsk.s 			page 7
+
+
+ 317:Src/main.c    ****   {
+ 318:Src/main.c    ****     Error_Handler();
+ 319:Src/main.c    ****   }
+ 320:Src/main.c    **** 
+ 321:Src/main.c    ****   /** Configure Regular Channel
+ 322:Src/main.c    ****   */
+ 323:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_2;
+ 324:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ 325:Src/main.c    ****   {
+ 326:Src/main.c    ****     Error_Handler();
+ 327:Src/main.c    ****   }
+ 328:Src/main.c    **** 
+ 329:Src/main.c    ****   /** Configure Regular Channel
+ 330:Src/main.c    ****   */
+ 331:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_3;
+ 332:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ 333:Src/main.c    ****   {
+ 334:Src/main.c    ****     Error_Handler();
+ 335:Src/main.c    ****   }
+ 336:Src/main.c    **** 
+ 337:Src/main.c    ****   /** Configure Regular Channel
+ 338:Src/main.c    ****   */
+ 339:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_4;
+ 340:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ 341:Src/main.c    ****   {
+ 342:Src/main.c    ****     Error_Handler();
+ 343:Src/main.c    ****   }
+ 344:Src/main.c    ****   /* USER CODE BEGIN ADC2_Init 2 */
+ 345:Src/main.c    **** 
+ 346:Src/main.c    ****   /* USER CODE END ADC2_Init 2 */
+ 347:Src/main.c    **** 
+ 348:Src/main.c    **** }
+ 349:Src/main.c    **** 
+ 350:Src/main.c    **** /**
+ 351:Src/main.c    ****   * @brief I2C1 Initialization Function
+ 352:Src/main.c    ****   * @param None
+ 353:Src/main.c    ****   * @retval None
+ 354:Src/main.c    ****   */
+ 355:Src/main.c    **** static void MX_I2C1_Init(void)
+ 356:Src/main.c    **** {
+ 357:Src/main.c    **** 
+ 358:Src/main.c    ****   /* USER CODE BEGIN I2C1_Init 0 */
+ 359:Src/main.c    **** 
+ 360:Src/main.c    ****   /* USER CODE END I2C1_Init 0 */
+ 361:Src/main.c    **** 
+ 362:Src/main.c    ****   /* USER CODE BEGIN I2C1_Init 1 */
+ 363:Src/main.c    **** 
+ 364:Src/main.c    ****   /* USER CODE END I2C1_Init 1 */
+ 365:Src/main.c    ****   hi2c1.Instance = I2C1;
+ 366:Src/main.c    ****   hi2c1.Init.Timing = 0x208080C1;
+ 367:Src/main.c    ****   hi2c1.Init.OwnAddress1 = 0;
+ 368:Src/main.c    ****   hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+ 369:Src/main.c    ****   hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+ 370:Src/main.c    ****   hi2c1.Init.OwnAddress2 = 0;
+ 371:Src/main.c    ****   hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+ 372:Src/main.c    ****   hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+ 373:Src/main.c    ****   hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+ARM GAS  /tmp/cc8GRwsk.s 			page 8
+
+
+ 374:Src/main.c    ****   if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+ 375:Src/main.c    ****   {
+ 376:Src/main.c    ****     Error_Handler();
+ 377:Src/main.c    ****   }
+ 378:Src/main.c    **** 
+ 379:Src/main.c    ****   /** Configure Analogue filter
+ 380:Src/main.c    ****   */
+ 381:Src/main.c    ****   if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+ 382:Src/main.c    ****   {
+ 383:Src/main.c    ****     Error_Handler();
+ 384:Src/main.c    ****   }
+ 385:Src/main.c    **** 
+ 386:Src/main.c    ****   /** Configure Digital filter
+ 387:Src/main.c    ****   */
+ 388:Src/main.c    ****   if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
+ 389:Src/main.c    ****   {
+ 390:Src/main.c    ****     Error_Handler();
+ 391:Src/main.c    ****   }
+ 392:Src/main.c    ****   /* USER CODE BEGIN I2C1_Init 2 */
+ 393:Src/main.c    **** 
+ 394:Src/main.c    ****   /* USER CODE END I2C1_Init 2 */
+ 395:Src/main.c    **** 
+ 396:Src/main.c    **** }
+ 397:Src/main.c    **** 
+ 398:Src/main.c    **** /**
+ 399:Src/main.c    ****   * @brief TIM2 Initialization Function
+ 400:Src/main.c    ****   * @param None
+ 401:Src/main.c    ****   * @retval None
+ 402:Src/main.c    ****   */
+ 403:Src/main.c    **** static void MX_TIM2_Init(void)
+ 404:Src/main.c    **** {
+ 405:Src/main.c    **** 
+ 406:Src/main.c    ****   /* USER CODE BEGIN TIM2_Init 0 */
+ 407:Src/main.c    **** 
+ 408:Src/main.c    ****   /* USER CODE END TIM2_Init 0 */
+ 409:Src/main.c    **** 
+ 410:Src/main.c    ****   TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+ 411:Src/main.c    ****   TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 412:Src/main.c    ****   TIM_OC_InitTypeDef sConfigOC = {0};
+ 413:Src/main.c    **** 
+ 414:Src/main.c    ****   /* USER CODE BEGIN TIM2_Init 1 */
+ 415:Src/main.c    **** 
+ 416:Src/main.c    ****   /* USER CODE END TIM2_Init 1 */
+ 417:Src/main.c    ****   htim2.Instance = TIM2;
+ 418:Src/main.c    ****   htim2.Init.Prescaler = 0;
+ 419:Src/main.c    ****   htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 420:Src/main.c    ****   htim2.Init.Period = 2047;
+ 421:Src/main.c    ****   htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 422:Src/main.c    ****   htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 423:Src/main.c    ****   if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+ 424:Src/main.c    ****   {
+ 425:Src/main.c    ****     Error_Handler();
+ 426:Src/main.c    ****   }
+ 427:Src/main.c    ****   sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ 428:Src/main.c    ****   if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+ 429:Src/main.c    ****   {
+ 430:Src/main.c    ****     Error_Handler();
+ARM GAS  /tmp/cc8GRwsk.s 			page 9
+
+
+ 431:Src/main.c    ****   }
+ 432:Src/main.c    ****   if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
+ 433:Src/main.c    ****   {
+ 434:Src/main.c    ****     Error_Handler();
+ 435:Src/main.c    ****   }
+ 436:Src/main.c    ****   sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 437:Src/main.c    ****   sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 438:Src/main.c    ****   if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+ 439:Src/main.c    ****   {
+ 440:Src/main.c    ****     Error_Handler();
+ 441:Src/main.c    ****   }
+ 442:Src/main.c    ****   sConfigOC.OCMode = TIM_OCMODE_PWM1;
+ 443:Src/main.c    ****   sConfigOC.Pulse = 500;
+ 444:Src/main.c    ****   sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 445:Src/main.c    ****   sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+ 446:Src/main.c    ****   if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+ 447:Src/main.c    ****   {
+ 448:Src/main.c    ****     Error_Handler();
+ 449:Src/main.c    ****   }
+ 450:Src/main.c    ****   sConfigOC.Pulse = 1000;
+ 451:Src/main.c    ****   if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
+ 452:Src/main.c    ****   {
+ 453:Src/main.c    ****     Error_Handler();
+ 454:Src/main.c    ****   }
+ 455:Src/main.c    ****   sConfigOC.Pulse = 1500;
+ 456:Src/main.c    ****   if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+ 457:Src/main.c    ****   {
+ 458:Src/main.c    ****     Error_Handler();
+ 459:Src/main.c    ****   }
+ 460:Src/main.c    ****   sConfigOC.Pulse = 2000;
+ 461:Src/main.c    ****   if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
+ 462:Src/main.c    ****   {
+ 463:Src/main.c    ****     Error_Handler();
+ 464:Src/main.c    ****   }
+ 465:Src/main.c    ****   /* USER CODE BEGIN TIM2_Init 2 */
+ 466:Src/main.c    **** 
+ 467:Src/main.c    ****   /* USER CODE END TIM2_Init 2 */
+ 468:Src/main.c    ****   HAL_TIM_MspPostInit(&htim2);
+ 469:Src/main.c    **** 
+ 470:Src/main.c    **** }
+ 471:Src/main.c    **** 
+ 472:Src/main.c    **** /**
+ 473:Src/main.c    ****   * @brief TIM3 Initialization Function
+ 474:Src/main.c    ****   * @param None
+ 475:Src/main.c    ****   * @retval None
+ 476:Src/main.c    ****   */
+ 477:Src/main.c    **** static void MX_TIM3_Init(void)
+ 478:Src/main.c    **** {
+ 479:Src/main.c    **** 
+ 480:Src/main.c    ****   /* USER CODE BEGIN TIM3_Init 0 */
+ 481:Src/main.c    **** 
+ 482:Src/main.c    ****   /* USER CODE END TIM3_Init 0 */
+ 483:Src/main.c    **** 
+ 484:Src/main.c    ****   TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+ 485:Src/main.c    ****   TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 486:Src/main.c    **** 
+ 487:Src/main.c    ****   /* USER CODE BEGIN TIM3_Init 1 */
+ARM GAS  /tmp/cc8GRwsk.s 			page 10
+
+
+ 488:Src/main.c    **** 
+ 489:Src/main.c    ****   /* USER CODE END TIM3_Init 1 */
+ 490:Src/main.c    ****   htim3.Instance = TIM3;
+ 491:Src/main.c    ****   htim3.Init.Prescaler = 49152;
+ 492:Src/main.c    ****   htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 493:Src/main.c    ****   htim3.Init.Period = 199;
+ 494:Src/main.c    ****   htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 495:Src/main.c    ****   htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 496:Src/main.c    ****   if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
+ 497:Src/main.c    ****   {
+ 498:Src/main.c    ****     Error_Handler();
+ 499:Src/main.c    ****   }
+ 500:Src/main.c    ****   sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ 501:Src/main.c    ****   if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
+ 502:Src/main.c    ****   {
+ 503:Src/main.c    ****     Error_Handler();
+ 504:Src/main.c    ****   }
+ 505:Src/main.c    ****   sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 506:Src/main.c    ****   sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 507:Src/main.c    ****   if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+ 508:Src/main.c    ****   {
+ 509:Src/main.c    ****     Error_Handler();
+ 510:Src/main.c    ****   }
+ 511:Src/main.c    ****   /* USER CODE BEGIN TIM3_Init 2 */
+ 512:Src/main.c    **** 
+ 513:Src/main.c    ****   /* USER CODE END TIM3_Init 2 */
+ 514:Src/main.c    **** 
+ 515:Src/main.c    **** }
+ 516:Src/main.c    **** 
+ 517:Src/main.c    **** /**
+ 518:Src/main.c    ****   * @brief USART1 Initialization Function
+ 519:Src/main.c    ****   * @param None
+ 520:Src/main.c    ****   * @retval None
+ 521:Src/main.c    ****   */
+ 522:Src/main.c    **** static void MX_USART1_UART_Init(void)
+ 523:Src/main.c    **** {
+ 524:Src/main.c    **** 
+ 525:Src/main.c    ****   /* USER CODE BEGIN USART1_Init 0 */
+ 526:Src/main.c    **** 
+ 527:Src/main.c    ****   /* USER CODE END USART1_Init 0 */
+ 528:Src/main.c    **** 
+ 529:Src/main.c    ****   /* USER CODE BEGIN USART1_Init 1 */
+ 530:Src/main.c    **** 
+ 531:Src/main.c    ****   /* USER CODE END USART1_Init 1 */
+ 532:Src/main.c    ****   huart1.Instance = USART1;
+ 533:Src/main.c    ****   huart1.Init.BaudRate = 115200;
+ 534:Src/main.c    ****   huart1.Init.WordLength = UART_WORDLENGTH_8B;
+ 535:Src/main.c    ****   huart1.Init.StopBits = UART_STOPBITS_1;
+ 536:Src/main.c    ****   huart1.Init.Parity = UART_PARITY_NONE;
+ 537:Src/main.c    ****   huart1.Init.Mode = UART_MODE_TX_RX;
+ 538:Src/main.c    ****   huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 539:Src/main.c    ****   huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+ 540:Src/main.c    ****   huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 541:Src/main.c    ****   huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 542:Src/main.c    ****   huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ 543:Src/main.c    ****   if (HAL_UART_Init(&huart1) != HAL_OK)
+ 544:Src/main.c    ****   {
+ARM GAS  /tmp/cc8GRwsk.s 			page 11
+
+
+ 545:Src/main.c    ****     Error_Handler();
+ 546:Src/main.c    ****   }
+ 547:Src/main.c    ****   if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 548:Src/main.c    ****   {
+ 549:Src/main.c    ****     Error_Handler();
+ 550:Src/main.c    ****   }
+ 551:Src/main.c    ****   if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 552:Src/main.c    ****   {
+ 553:Src/main.c    ****     Error_Handler();
+ 554:Src/main.c    ****   }
+ 555:Src/main.c    ****   if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+ 556:Src/main.c    ****   {
+ 557:Src/main.c    ****     Error_Handler();
+ 558:Src/main.c    ****   }
+ 559:Src/main.c    ****   /* USER CODE BEGIN USART1_Init 2 */
+ 560:Src/main.c    **** 
+ 561:Src/main.c    ****   /* USER CODE END USART1_Init 2 */
+ 562:Src/main.c    **** 
+ 563:Src/main.c    **** }
+ 564:Src/main.c    **** 
+ 565:Src/main.c    **** /**
+ 566:Src/main.c    ****   * @brief GPIO Initialization Function
+ 567:Src/main.c    ****   * @param None
+ 568:Src/main.c    ****   * @retval None
+ 569:Src/main.c    ****   */
+ 570:Src/main.c    **** static void MX_GPIO_Init(void)
+ 571:Src/main.c    **** {
+  28              		.loc 1 571 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 40
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32 0000 00B5     		push	{lr}
+  33              	.LCFI0:
+  34              		.cfi_def_cfa_offset 4
+  35              		.cfi_offset 14, -4
+  36 0002 8BB0     		sub	sp, sp, #44
+  37              	.LCFI1:
+  38              		.cfi_def_cfa_offset 48
+ 572:Src/main.c    ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
+  39              		.loc 1 572 3 view .LVU1
+  40              		.loc 1 572 20 is_stmt 0 view .LVU2
+  41 0004 0023     		movs	r3, #0
+  42 0006 0593     		str	r3, [sp, #20]
+  43 0008 0693     		str	r3, [sp, #24]
+  44 000a 0793     		str	r3, [sp, #28]
+  45 000c 0893     		str	r3, [sp, #32]
+  46 000e 0993     		str	r3, [sp, #36]
+ 573:Src/main.c    **** /* USER CODE BEGIN MX_GPIO_Init_1 */
+ 574:Src/main.c    **** /* USER CODE END MX_GPIO_Init_1 */
+ 575:Src/main.c    **** 
+ 576:Src/main.c    ****   /* GPIO Ports Clock Enable */
+ 577:Src/main.c    ****   __HAL_RCC_GPIOF_CLK_ENABLE();
+  47              		.loc 1 577 3 is_stmt 1 view .LVU3
+  48              	.LBB4:
+  49              		.loc 1 577 3 view .LVU4
+  50              		.loc 1 577 3 view .LVU5
+  51 0010 03F18043 		add	r3, r3, #1073741824
+ARM GAS  /tmp/cc8GRwsk.s 			page 12
+
+
+  52 0014 03F50433 		add	r3, r3, #135168
+  53 0018 DA6C     		ldr	r2, [r3, #76]
+  54 001a 42F02002 		orr	r2, r2, #32
+  55 001e DA64     		str	r2, [r3, #76]
+  56              		.loc 1 577 3 view .LVU6
+  57 0020 DA6C     		ldr	r2, [r3, #76]
+  58 0022 02F02002 		and	r2, r2, #32
+  59 0026 0192     		str	r2, [sp, #4]
+  60              		.loc 1 577 3 view .LVU7
+  61 0028 019A     		ldr	r2, [sp, #4]
+  62              	.LBE4:
+  63              		.loc 1 577 3 view .LVU8
+ 578:Src/main.c    ****   __HAL_RCC_GPIOG_CLK_ENABLE();
+  64              		.loc 1 578 3 view .LVU9
+  65              	.LBB5:
+  66              		.loc 1 578 3 view .LVU10
+  67              		.loc 1 578 3 view .LVU11
+  68 002a DA6C     		ldr	r2, [r3, #76]
+  69 002c 42F04002 		orr	r2, r2, #64
+  70 0030 DA64     		str	r2, [r3, #76]
+  71              		.loc 1 578 3 view .LVU12
+  72 0032 DA6C     		ldr	r2, [r3, #76]
+  73 0034 02F04002 		and	r2, r2, #64
+  74 0038 0292     		str	r2, [sp, #8]
+  75              		.loc 1 578 3 view .LVU13
+  76 003a 029A     		ldr	r2, [sp, #8]
+  77              	.LBE5:
+  78              		.loc 1 578 3 view .LVU14
+ 579:Src/main.c    ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+  79              		.loc 1 579 3 view .LVU15
+  80              	.LBB6:
+  81              		.loc 1 579 3 view .LVU16
+  82              		.loc 1 579 3 view .LVU17
+  83 003c DA6C     		ldr	r2, [r3, #76]
+  84 003e 42F00102 		orr	r2, r2, #1
+  85 0042 DA64     		str	r2, [r3, #76]
+  86              		.loc 1 579 3 view .LVU18
+  87 0044 DA6C     		ldr	r2, [r3, #76]
+  88 0046 02F00102 		and	r2, r2, #1
+  89 004a 0392     		str	r2, [sp, #12]
+  90              		.loc 1 579 3 view .LVU19
+  91 004c 039A     		ldr	r2, [sp, #12]
+  92              	.LBE6:
+  93              		.loc 1 579 3 view .LVU20
+ 580:Src/main.c    ****   __HAL_RCC_GPIOB_CLK_ENABLE();
+  94              		.loc 1 580 3 view .LVU21
+  95              	.LBB7:
+  96              		.loc 1 580 3 view .LVU22
+  97              		.loc 1 580 3 view .LVU23
+  98 004e DA6C     		ldr	r2, [r3, #76]
+  99 0050 42F00202 		orr	r2, r2, #2
+ 100 0054 DA64     		str	r2, [r3, #76]
+ 101              		.loc 1 580 3 view .LVU24
+ 102 0056 DB6C     		ldr	r3, [r3, #76]
+ 103 0058 03F00203 		and	r3, r3, #2
+ 104 005c 0493     		str	r3, [sp, #16]
+ 105              		.loc 1 580 3 view .LVU25
+ARM GAS  /tmp/cc8GRwsk.s 			page 13
+
+
+ 106 005e 049B     		ldr	r3, [sp, #16]
+ 107              	.LBE7:
+ 108              		.loc 1 580 3 view .LVU26
+ 581:Src/main.c    **** 
+ 582:Src/main.c    ****   /*Configure GPIO pin : PG10 */
+ 583:Src/main.c    ****   GPIO_InitStruct.Pin = GPIO_PIN_10;
+ 109              		.loc 1 583 3 view .LVU27
+ 110              		.loc 1 583 23 is_stmt 0 view .LVU28
+ 111 0060 4FF48063 		mov	r3, #1024
+ 112 0064 0593     		str	r3, [sp, #20]
+ 584:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 113              		.loc 1 584 3 is_stmt 1 view .LVU29
+ 114              		.loc 1 584 24 is_stmt 0 view .LVU30
+ 115 0066 0223     		movs	r3, #2
+ 116 0068 0693     		str	r3, [sp, #24]
+ 585:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 117              		.loc 1 585 3 is_stmt 1 view .LVU31
+ 586:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 118              		.loc 1 586 3 view .LVU32
+ 587:Src/main.c    ****   GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+ 119              		.loc 1 587 3 view .LVU33
+ 588:Src/main.c    ****   HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+ 120              		.loc 1 588 3 view .LVU34
+ 121 006a 05A9     		add	r1, sp, #20
+ 122 006c 0248     		ldr	r0, .L3
+ 123 006e FFF7FEFF 		bl	HAL_GPIO_Init
+ 124              	.LVL0:
+ 589:Src/main.c    **** 
+ 590:Src/main.c    **** /* USER CODE BEGIN MX_GPIO_Init_2 */
+ 591:Src/main.c    **** /* USER CODE END MX_GPIO_Init_2 */
+ 592:Src/main.c    **** }
+ 125              		.loc 1 592 1 is_stmt 0 view .LVU35
+ 126 0072 0BB0     		add	sp, sp, #44
+ 127              	.LCFI2:
+ 128              		.cfi_def_cfa_offset 4
+ 129              		@ sp needed
+ 130 0074 5DF804FB 		ldr	pc, [sp], #4
+ 131              	.L4:
+ 132              		.align	2
+ 133              	.L3:
+ 134 0078 00180048 		.word	1207965696
+ 135              		.cfi_endproc
+ 136              	.LFE341:
+ 138              		.section	.text.Error_Handler,"ax",%progbits
+ 139              		.align	1
+ 140              		.global	Error_Handler
+ 141              		.syntax unified
+ 142              		.thumb
+ 143              		.thumb_func
+ 145              	Error_Handler:
+ 146              	.LFB342:
+ 593:Src/main.c    **** 
+ 594:Src/main.c    **** /* USER CODE BEGIN 4 */
+ 595:Src/main.c    **** 
+ 596:Src/main.c    **** /* USER CODE END 4 */
+ 597:Src/main.c    **** 
+ 598:Src/main.c    **** /**
+ARM GAS  /tmp/cc8GRwsk.s 			page 14
+
+
+ 599:Src/main.c    ****   * @brief  This function is executed in case of error occurrence.
+ 600:Src/main.c    ****   * @retval None
+ 601:Src/main.c    ****   */
+ 602:Src/main.c    **** void Error_Handler(void)
+ 603:Src/main.c    **** {
+ 147              		.loc 1 603 1 is_stmt 1 view -0
+ 148              		.cfi_startproc
+ 149              		@ Volatile: function does not return.
+ 150              		@ args = 0, pretend = 0, frame = 0
+ 151              		@ frame_needed = 0, uses_anonymous_args = 0
+ 152              		@ link register save eliminated.
+ 604:Src/main.c    ****   /* USER CODE BEGIN Error_Handler_Debug */
+ 605:Src/main.c    ****   /* User can add his own implementation to report the HAL error return state */
+ 606:Src/main.c    ****   __disable_irq();
+ 153              		.loc 1 606 3 view .LVU37
+ 154              	.LBB8:
+ 155              	.LBI8:
+ 156              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.2.0
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     08. May 2019
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+ARM GAS  /tmp/cc8GRwsk.s 			page 15
+
+
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ARM GAS  /tmp/cc8GRwsk.s 			page 16
+
+
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
+ARM GAS  /tmp/cc8GRwsk.s 			page 17
+
+
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 157              		.loc 2 207 27 view .LVU38
+ 158              	.LBB9:
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/cc8GRwsk.s 			page 18
+
+
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 159              		.loc 2 209 3 view .LVU39
+ 160              		.syntax unified
+ 161              	@ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 162 0000 72B6     		cpsid i
+ 163              	@ 0 "" 2
+ 164              		.thumb
+ 165              		.syntax unified
+ 166              	.L6:
+ 167              	.LBE9:
+ 168              	.LBE8:
+ 607:Src/main.c    ****   while (1)
+ 169              		.loc 1 607 3 discriminator 1 view .LVU40
+ 608:Src/main.c    ****   {
+ 609:Src/main.c    ****   }
+ 170              		.loc 1 609 3 discriminator 1 view .LVU41
+ 607:Src/main.c    ****   while (1)
+ 171              		.loc 1 607 9 discriminator 1 view .LVU42
+ 172 0002 FEE7     		b	.L6
+ 173              		.cfi_endproc
+ 174              	.LFE342:
+ 176              		.section	.text.MX_TIM2_Init,"ax",%progbits
+ 177              		.align	1
+ 178              		.syntax unified
+ 179              		.thumb
+ 180              		.thumb_func
+ 182              	MX_TIM2_Init:
+ 183              	.LFB338:
+ 404:Src/main.c    **** 
+ 184              		.loc 1 404 1 view -0
+ 185              		.cfi_startproc
+ 186              		@ args = 0, pretend = 0, frame = 56
+ 187              		@ frame_needed = 0, uses_anonymous_args = 0
+ 188 0000 00B5     		push	{lr}
+ 189              	.LCFI3:
+ 190              		.cfi_def_cfa_offset 4
+ 191              		.cfi_offset 14, -4
+ 192 0002 8FB0     		sub	sp, sp, #60
+ 193              	.LCFI4:
+ 194              		.cfi_def_cfa_offset 64
+ 410:Src/main.c    ****   TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 195              		.loc 1 410 3 view .LVU44
+ 410:Src/main.c    ****   TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 196              		.loc 1 410 26 is_stmt 0 view .LVU45
+ 197 0004 0023     		movs	r3, #0
+ 198 0006 0A93     		str	r3, [sp, #40]
+ 199 0008 0B93     		str	r3, [sp, #44]
+ 200 000a 0C93     		str	r3, [sp, #48]
+ 201 000c 0D93     		str	r3, [sp, #52]
+ 411:Src/main.c    ****   TIM_OC_InitTypeDef sConfigOC = {0};
+ 202              		.loc 1 411 3 is_stmt 1 view .LVU46
+ 411:Src/main.c    ****   TIM_OC_InitTypeDef sConfigOC = {0};
+ 203              		.loc 1 411 27 is_stmt 0 view .LVU47
+ 204 000e 0793     		str	r3, [sp, #28]
+ 205 0010 0893     		str	r3, [sp, #32]
+ 206 0012 0993     		str	r3, [sp, #36]
+ 412:Src/main.c    **** 
+ARM GAS  /tmp/cc8GRwsk.s 			page 19
+
+
+ 207              		.loc 1 412 3 is_stmt 1 view .LVU48
+ 412:Src/main.c    **** 
+ 208              		.loc 1 412 22 is_stmt 0 view .LVU49
+ 209 0014 0093     		str	r3, [sp]
+ 210 0016 0193     		str	r3, [sp, #4]
+ 211 0018 0293     		str	r3, [sp, #8]
+ 212 001a 0393     		str	r3, [sp, #12]
+ 213 001c 0493     		str	r3, [sp, #16]
+ 214 001e 0593     		str	r3, [sp, #20]
+ 215 0020 0693     		str	r3, [sp, #24]
+ 417:Src/main.c    ****   htim2.Init.Prescaler = 0;
+ 216              		.loc 1 417 3 is_stmt 1 view .LVU50
+ 417:Src/main.c    ****   htim2.Init.Prescaler = 0;
+ 217              		.loc 1 417 18 is_stmt 0 view .LVU51
+ 218 0022 3248     		ldr	r0, .L25
+ 219 0024 4FF08042 		mov	r2, #1073741824
+ 220 0028 0260     		str	r2, [r0]
+ 418:Src/main.c    ****   htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 221              		.loc 1 418 3 is_stmt 1 view .LVU52
+ 418:Src/main.c    ****   htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 222              		.loc 1 418 24 is_stmt 0 view .LVU53
+ 223 002a 4360     		str	r3, [r0, #4]
+ 419:Src/main.c    ****   htim2.Init.Period = 2047;
+ 224              		.loc 1 419 3 is_stmt 1 view .LVU54
+ 419:Src/main.c    ****   htim2.Init.Period = 2047;
+ 225              		.loc 1 419 26 is_stmt 0 view .LVU55
+ 226 002c 8360     		str	r3, [r0, #8]
+ 420:Src/main.c    ****   htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 227              		.loc 1 420 3 is_stmt 1 view .LVU56
+ 420:Src/main.c    ****   htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 228              		.loc 1 420 21 is_stmt 0 view .LVU57
+ 229 002e 40F2FF72 		movw	r2, #2047
+ 230 0032 C260     		str	r2, [r0, #12]
+ 421:Src/main.c    ****   htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 231              		.loc 1 421 3 is_stmt 1 view .LVU58
+ 421:Src/main.c    ****   htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 232              		.loc 1 421 28 is_stmt 0 view .LVU59
+ 233 0034 0361     		str	r3, [r0, #16]
+ 422:Src/main.c    ****   if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+ 234              		.loc 1 422 3 is_stmt 1 view .LVU60
+ 422:Src/main.c    ****   if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+ 235              		.loc 1 422 32 is_stmt 0 view .LVU61
+ 236 0036 8361     		str	r3, [r0, #24]
+ 423:Src/main.c    ****   {
+ 237              		.loc 1 423 3 is_stmt 1 view .LVU62
+ 423:Src/main.c    ****   {
+ 238              		.loc 1 423 7 is_stmt 0 view .LVU63
+ 239 0038 FFF7FEFF 		bl	HAL_TIM_Base_Init
+ 240              	.LVL1:
+ 423:Src/main.c    ****   {
+ 241              		.loc 1 423 6 view .LVU64
+ 242 003c 0028     		cmp	r0, #0
+ 243 003e 44D1     		bne	.L17
+ 427:Src/main.c    ****   if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+ 244              		.loc 1 427 3 is_stmt 1 view .LVU65
+ 427:Src/main.c    ****   if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+ 245              		.loc 1 427 34 is_stmt 0 view .LVU66
+ARM GAS  /tmp/cc8GRwsk.s 			page 20
+
+
+ 246 0040 4FF48053 		mov	r3, #4096
+ 247 0044 0A93     		str	r3, [sp, #40]
+ 428:Src/main.c    ****   {
+ 248              		.loc 1 428 3 is_stmt 1 view .LVU67
+ 428:Src/main.c    ****   {
+ 249              		.loc 1 428 7 is_stmt 0 view .LVU68
+ 250 0046 0AA9     		add	r1, sp, #40
+ 251 0048 2848     		ldr	r0, .L25
+ 252 004a FFF7FEFF 		bl	HAL_TIM_ConfigClockSource
+ 253              	.LVL2:
+ 428:Src/main.c    ****   {
+ 254              		.loc 1 428 6 view .LVU69
+ 255 004e 0028     		cmp	r0, #0
+ 256 0050 3DD1     		bne	.L18
+ 432:Src/main.c    ****   {
+ 257              		.loc 1 432 3 is_stmt 1 view .LVU70
+ 432:Src/main.c    ****   {
+ 258              		.loc 1 432 7 is_stmt 0 view .LVU71
+ 259 0052 2648     		ldr	r0, .L25
+ 260 0054 FFF7FEFF 		bl	HAL_TIM_PWM_Init
+ 261              	.LVL3:
+ 432:Src/main.c    ****   {
+ 262              		.loc 1 432 6 view .LVU72
+ 263 0058 0028     		cmp	r0, #0
+ 264 005a 3AD1     		bne	.L19
+ 436:Src/main.c    ****   sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 265              		.loc 1 436 3 is_stmt 1 view .LVU73
+ 436:Src/main.c    ****   sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 266              		.loc 1 436 37 is_stmt 0 view .LVU74
+ 267 005c 0023     		movs	r3, #0
+ 268 005e 0793     		str	r3, [sp, #28]
+ 437:Src/main.c    ****   if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+ 269              		.loc 1 437 3 is_stmt 1 view .LVU75
+ 437:Src/main.c    ****   if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+ 270              		.loc 1 437 33 is_stmt 0 view .LVU76
+ 271 0060 0993     		str	r3, [sp, #36]
+ 438:Src/main.c    ****   {
+ 272              		.loc 1 438 3 is_stmt 1 view .LVU77
+ 438:Src/main.c    ****   {
+ 273              		.loc 1 438 7 is_stmt 0 view .LVU78
+ 274 0062 07A9     		add	r1, sp, #28
+ 275 0064 2148     		ldr	r0, .L25
+ 276 0066 FFF7FEFF 		bl	HAL_TIMEx_MasterConfigSynchronization
+ 277              	.LVL4:
+ 438:Src/main.c    ****   {
+ 278              		.loc 1 438 6 view .LVU79
+ 279 006a 0028     		cmp	r0, #0
+ 280 006c 33D1     		bne	.L20
+ 442:Src/main.c    ****   sConfigOC.Pulse = 500;
+ 281              		.loc 1 442 3 is_stmt 1 view .LVU80
+ 442:Src/main.c    ****   sConfigOC.Pulse = 500;
+ 282              		.loc 1 442 20 is_stmt 0 view .LVU81
+ 283 006e 6023     		movs	r3, #96
+ 284 0070 0093     		str	r3, [sp]
+ 443:Src/main.c    ****   sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 285              		.loc 1 443 3 is_stmt 1 view .LVU82
+ 443:Src/main.c    ****   sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+ARM GAS  /tmp/cc8GRwsk.s 			page 21
+
+
+ 286              		.loc 1 443 19 is_stmt 0 view .LVU83
+ 287 0072 4FF4FA73 		mov	r3, #500
+ 288 0076 0193     		str	r3, [sp, #4]
+ 444:Src/main.c    ****   sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+ 289              		.loc 1 444 3 is_stmt 1 view .LVU84
+ 444:Src/main.c    ****   sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+ 290              		.loc 1 444 24 is_stmt 0 view .LVU85
+ 291 0078 0022     		movs	r2, #0
+ 292 007a 0292     		str	r2, [sp, #8]
+ 445:Src/main.c    ****   if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+ 293              		.loc 1 445 3 is_stmt 1 view .LVU86
+ 445:Src/main.c    ****   if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+ 294              		.loc 1 445 24 is_stmt 0 view .LVU87
+ 295 007c 0492     		str	r2, [sp, #16]
+ 446:Src/main.c    ****   {
+ 296              		.loc 1 446 3 is_stmt 1 view .LVU88
+ 446:Src/main.c    ****   {
+ 297              		.loc 1 446 7 is_stmt 0 view .LVU89
+ 298 007e 6946     		mov	r1, sp
+ 299 0080 1A48     		ldr	r0, .L25
+ 300 0082 FFF7FEFF 		bl	HAL_TIM_PWM_ConfigChannel
+ 301              	.LVL5:
+ 446:Src/main.c    ****   {
+ 302              		.loc 1 446 6 view .LVU90
+ 303 0086 40BB     		cbnz	r0, .L21
+ 450:Src/main.c    ****   if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
+ 304              		.loc 1 450 3 is_stmt 1 view .LVU91
+ 450:Src/main.c    ****   if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
+ 305              		.loc 1 450 19 is_stmt 0 view .LVU92
+ 306 0088 4FF47A73 		mov	r3, #1000
+ 307 008c 0193     		str	r3, [sp, #4]
+ 451:Src/main.c    ****   {
+ 308              		.loc 1 451 3 is_stmt 1 view .LVU93
+ 451:Src/main.c    ****   {
+ 309              		.loc 1 451 7 is_stmt 0 view .LVU94
+ 310 008e 0422     		movs	r2, #4
+ 311 0090 6946     		mov	r1, sp
+ 312 0092 1648     		ldr	r0, .L25
+ 313 0094 FFF7FEFF 		bl	HAL_TIM_PWM_ConfigChannel
+ 314              	.LVL6:
+ 451:Src/main.c    ****   {
+ 315              		.loc 1 451 6 view .LVU95
+ 316 0098 08BB     		cbnz	r0, .L22
+ 455:Src/main.c    ****   if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+ 317              		.loc 1 455 3 is_stmt 1 view .LVU96
+ 455:Src/main.c    ****   if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+ 318              		.loc 1 455 19 is_stmt 0 view .LVU97
+ 319 009a 40F2DC53 		movw	r3, #1500
+ 320 009e 0193     		str	r3, [sp, #4]
+ 456:Src/main.c    ****   {
+ 321              		.loc 1 456 3 is_stmt 1 view .LVU98
+ 456:Src/main.c    ****   {
+ 322              		.loc 1 456 7 is_stmt 0 view .LVU99
+ 323 00a0 0822     		movs	r2, #8
+ 324 00a2 6946     		mov	r1, sp
+ 325 00a4 1148     		ldr	r0, .L25
+ 326 00a6 FFF7FEFF 		bl	HAL_TIM_PWM_ConfigChannel
+ARM GAS  /tmp/cc8GRwsk.s 			page 22
+
+
+ 327              	.LVL7:
+ 456:Src/main.c    ****   {
+ 328              		.loc 1 456 6 view .LVU100
+ 329 00aa D0B9     		cbnz	r0, .L23
+ 460:Src/main.c    ****   if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
+ 330              		.loc 1 460 3 is_stmt 1 view .LVU101
+ 460:Src/main.c    ****   if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
+ 331              		.loc 1 460 19 is_stmt 0 view .LVU102
+ 332 00ac 4FF4FA63 		mov	r3, #2000
+ 333 00b0 0193     		str	r3, [sp, #4]
+ 461:Src/main.c    ****   {
+ 334              		.loc 1 461 3 is_stmt 1 view .LVU103
+ 461:Src/main.c    ****   {
+ 335              		.loc 1 461 7 is_stmt 0 view .LVU104
+ 336 00b2 0C22     		movs	r2, #12
+ 337 00b4 6946     		mov	r1, sp
+ 338 00b6 0D48     		ldr	r0, .L25
+ 339 00b8 FFF7FEFF 		bl	HAL_TIM_PWM_ConfigChannel
+ 340              	.LVL8:
+ 461:Src/main.c    ****   {
+ 341              		.loc 1 461 6 view .LVU105
+ 342 00bc 98B9     		cbnz	r0, .L24
+ 468:Src/main.c    **** 
+ 343              		.loc 1 468 3 is_stmt 1 view .LVU106
+ 344 00be 0B48     		ldr	r0, .L25
+ 345 00c0 FFF7FEFF 		bl	HAL_TIM_MspPostInit
+ 346              	.LVL9:
+ 470:Src/main.c    **** 
+ 347              		.loc 1 470 1 is_stmt 0 view .LVU107
+ 348 00c4 0FB0     		add	sp, sp, #60
+ 349              	.LCFI5:
+ 350              		.cfi_remember_state
+ 351              		.cfi_def_cfa_offset 4
+ 352              		@ sp needed
+ 353 00c6 5DF804FB 		ldr	pc, [sp], #4
+ 354              	.L17:
+ 355              	.LCFI6:
+ 356              		.cfi_restore_state
+ 425:Src/main.c    ****   }
+ 357              		.loc 1 425 5 is_stmt 1 view .LVU108
+ 358 00ca FFF7FEFF 		bl	Error_Handler
+ 359              	.LVL10:
+ 360              	.L18:
+ 430:Src/main.c    ****   }
+ 361              		.loc 1 430 5 view .LVU109
+ 362 00ce FFF7FEFF 		bl	Error_Handler
+ 363              	.LVL11:
+ 364              	.L19:
+ 434:Src/main.c    ****   }
+ 365              		.loc 1 434 5 view .LVU110
+ 366 00d2 FFF7FEFF 		bl	Error_Handler
+ 367              	.LVL12:
+ 368              	.L20:
+ 440:Src/main.c    ****   }
+ 369              		.loc 1 440 5 view .LVU111
+ 370 00d6 FFF7FEFF 		bl	Error_Handler
+ 371              	.LVL13:
+ARM GAS  /tmp/cc8GRwsk.s 			page 23
+
+
+ 372              	.L21:
+ 448:Src/main.c    ****   }
+ 373              		.loc 1 448 5 view .LVU112
+ 374 00da FFF7FEFF 		bl	Error_Handler
+ 375              	.LVL14:
+ 376              	.L22:
+ 453:Src/main.c    ****   }
+ 377              		.loc 1 453 5 view .LVU113
+ 378 00de FFF7FEFF 		bl	Error_Handler
+ 379              	.LVL15:
+ 380              	.L23:
+ 458:Src/main.c    ****   }
+ 381              		.loc 1 458 5 view .LVU114
+ 382 00e2 FFF7FEFF 		bl	Error_Handler
+ 383              	.LVL16:
+ 384              	.L24:
+ 463:Src/main.c    ****   }
+ 385              		.loc 1 463 5 view .LVU115
+ 386 00e6 FFF7FEFF 		bl	Error_Handler
+ 387              	.LVL17:
+ 388              	.L26:
+ 389 00ea 00BF     		.align	2
+ 390              	.L25:
+ 391 00ec 00000000 		.word	htim2
+ 392              		.cfi_endproc
+ 393              	.LFE338:
+ 395              		.section	.text.MX_I2C1_Init,"ax",%progbits
+ 396              		.align	1
+ 397              		.syntax unified
+ 398              		.thumb
+ 399              		.thumb_func
+ 401              	MX_I2C1_Init:
+ 402              	.LFB337:
+ 356:Src/main.c    **** 
+ 403              		.loc 1 356 1 view -0
+ 404              		.cfi_startproc
+ 405              		@ args = 0, pretend = 0, frame = 0
+ 406              		@ frame_needed = 0, uses_anonymous_args = 0
+ 407 0000 08B5     		push	{r3, lr}
+ 408              	.LCFI7:
+ 409              		.cfi_def_cfa_offset 8
+ 410              		.cfi_offset 3, -8
+ 411              		.cfi_offset 14, -4
+ 365:Src/main.c    ****   hi2c1.Init.Timing = 0x208080C1;
+ 412              		.loc 1 365 3 view .LVU117
+ 365:Src/main.c    ****   hi2c1.Init.Timing = 0x208080C1;
+ 413              		.loc 1 365 18 is_stmt 0 view .LVU118
+ 414 0002 1148     		ldr	r0, .L35
+ 415 0004 114B     		ldr	r3, .L35+4
+ 416 0006 0360     		str	r3, [r0]
+ 366:Src/main.c    ****   hi2c1.Init.OwnAddress1 = 0;
+ 417              		.loc 1 366 3 is_stmt 1 view .LVU119
+ 366:Src/main.c    ****   hi2c1.Init.OwnAddress1 = 0;
+ 418              		.loc 1 366 21 is_stmt 0 view .LVU120
+ 419 0008 114B     		ldr	r3, .L35+8
+ 420 000a 4360     		str	r3, [r0, #4]
+ 367:Src/main.c    ****   hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+ARM GAS  /tmp/cc8GRwsk.s 			page 24
+
+
+ 421              		.loc 1 367 3 is_stmt 1 view .LVU121
+ 367:Src/main.c    ****   hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+ 422              		.loc 1 367 26 is_stmt 0 view .LVU122
+ 423 000c 0023     		movs	r3, #0
+ 424 000e 8360     		str	r3, [r0, #8]
+ 368:Src/main.c    ****   hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+ 425              		.loc 1 368 3 is_stmt 1 view .LVU123
+ 368:Src/main.c    ****   hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+ 426              		.loc 1 368 29 is_stmt 0 view .LVU124
+ 427 0010 0122     		movs	r2, #1
+ 428 0012 C260     		str	r2, [r0, #12]
+ 369:Src/main.c    ****   hi2c1.Init.OwnAddress2 = 0;
+ 429              		.loc 1 369 3 is_stmt 1 view .LVU125
+ 369:Src/main.c    ****   hi2c1.Init.OwnAddress2 = 0;
+ 430              		.loc 1 369 30 is_stmt 0 view .LVU126
+ 431 0014 0361     		str	r3, [r0, #16]
+ 370:Src/main.c    ****   hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+ 432              		.loc 1 370 3 is_stmt 1 view .LVU127
+ 370:Src/main.c    ****   hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+ 433              		.loc 1 370 26 is_stmt 0 view .LVU128
+ 434 0016 4361     		str	r3, [r0, #20]
+ 371:Src/main.c    ****   hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+ 435              		.loc 1 371 3 is_stmt 1 view .LVU129
+ 371:Src/main.c    ****   hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+ 436              		.loc 1 371 31 is_stmt 0 view .LVU130
+ 437 0018 8361     		str	r3, [r0, #24]
+ 372:Src/main.c    ****   hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+ 438              		.loc 1 372 3 is_stmt 1 view .LVU131
+ 372:Src/main.c    ****   hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+ 439              		.loc 1 372 30 is_stmt 0 view .LVU132
+ 440 001a C361     		str	r3, [r0, #28]
+ 373:Src/main.c    ****   if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+ 441              		.loc 1 373 3 is_stmt 1 view .LVU133
+ 373:Src/main.c    ****   if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+ 442              		.loc 1 373 28 is_stmt 0 view .LVU134
+ 443 001c 0362     		str	r3, [r0, #32]
+ 374:Src/main.c    ****   {
+ 444              		.loc 1 374 3 is_stmt 1 view .LVU135
+ 374:Src/main.c    ****   {
+ 445              		.loc 1 374 7 is_stmt 0 view .LVU136
+ 446 001e FFF7FEFF 		bl	HAL_I2C_Init
+ 447              	.LVL18:
+ 374:Src/main.c    ****   {
+ 448              		.loc 1 374 6 view .LVU137
+ 449 0022 50B9     		cbnz	r0, .L32
+ 381:Src/main.c    ****   {
+ 450              		.loc 1 381 3 is_stmt 1 view .LVU138
+ 381:Src/main.c    ****   {
+ 451              		.loc 1 381 7 is_stmt 0 view .LVU139
+ 452 0024 0021     		movs	r1, #0
+ 453 0026 0848     		ldr	r0, .L35
+ 454 0028 FFF7FEFF 		bl	HAL_I2CEx_ConfigAnalogFilter
+ 455              	.LVL19:
+ 381:Src/main.c    ****   {
+ 456              		.loc 1 381 6 view .LVU140
+ 457 002c 38B9     		cbnz	r0, .L33
+ 388:Src/main.c    ****   {
+ARM GAS  /tmp/cc8GRwsk.s 			page 25
+
+
+ 458              		.loc 1 388 3 is_stmt 1 view .LVU141
+ 388:Src/main.c    ****   {
+ 459              		.loc 1 388 7 is_stmt 0 view .LVU142
+ 460 002e 0021     		movs	r1, #0
+ 461 0030 0548     		ldr	r0, .L35
+ 462 0032 FFF7FEFF 		bl	HAL_I2CEx_ConfigDigitalFilter
+ 463              	.LVL20:
+ 388:Src/main.c    ****   {
+ 464              		.loc 1 388 6 view .LVU143
+ 465 0036 20B9     		cbnz	r0, .L34
+ 396:Src/main.c    **** 
+ 466              		.loc 1 396 1 view .LVU144
+ 467 0038 08BD     		pop	{r3, pc}
+ 468              	.L32:
+ 376:Src/main.c    ****   }
+ 469              		.loc 1 376 5 is_stmt 1 view .LVU145
+ 470 003a FFF7FEFF 		bl	Error_Handler
+ 471              	.LVL21:
+ 472              	.L33:
+ 383:Src/main.c    ****   }
+ 473              		.loc 1 383 5 view .LVU146
+ 474 003e FFF7FEFF 		bl	Error_Handler
+ 475              	.LVL22:
+ 476              	.L34:
+ 390:Src/main.c    ****   }
+ 477              		.loc 1 390 5 view .LVU147
+ 478 0042 FFF7FEFF 		bl	Error_Handler
+ 479              	.LVL23:
+ 480              	.L36:
+ 481 0046 00BF     		.align	2
+ 482              	.L35:
+ 483 0048 00000000 		.word	hi2c1
+ 484 004c 00540040 		.word	1073763328
+ 485 0050 C1808020 		.word	545292481
+ 486              		.cfi_endproc
+ 487              	.LFE337:
+ 489              		.section	.text.MX_TIM3_Init,"ax",%progbits
+ 490              		.align	1
+ 491              		.syntax unified
+ 492              		.thumb
+ 493              		.thumb_func
+ 495              	MX_TIM3_Init:
+ 496              	.LFB339:
+ 478:Src/main.c    **** 
+ 497              		.loc 1 478 1 view -0
+ 498              		.cfi_startproc
+ 499              		@ args = 0, pretend = 0, frame = 32
+ 500              		@ frame_needed = 0, uses_anonymous_args = 0
+ 501 0000 00B5     		push	{lr}
+ 502              	.LCFI8:
+ 503              		.cfi_def_cfa_offset 4
+ 504              		.cfi_offset 14, -4
+ 505 0002 89B0     		sub	sp, sp, #36
+ 506              	.LCFI9:
+ 507              		.cfi_def_cfa_offset 40
+ 484:Src/main.c    ****   TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 508              		.loc 1 484 3 view .LVU149
+ARM GAS  /tmp/cc8GRwsk.s 			page 26
+
+
+ 484:Src/main.c    ****   TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 509              		.loc 1 484 26 is_stmt 0 view .LVU150
+ 510 0004 0023     		movs	r3, #0
+ 511 0006 0493     		str	r3, [sp, #16]
+ 512 0008 0593     		str	r3, [sp, #20]
+ 513 000a 0693     		str	r3, [sp, #24]
+ 514 000c 0793     		str	r3, [sp, #28]
+ 485:Src/main.c    **** 
+ 515              		.loc 1 485 3 is_stmt 1 view .LVU151
+ 485:Src/main.c    **** 
+ 516              		.loc 1 485 27 is_stmt 0 view .LVU152
+ 517 000e 0193     		str	r3, [sp, #4]
+ 518 0010 0293     		str	r3, [sp, #8]
+ 519 0012 0393     		str	r3, [sp, #12]
+ 490:Src/main.c    ****   htim3.Init.Prescaler = 49152;
+ 520              		.loc 1 490 3 is_stmt 1 view .LVU153
+ 490:Src/main.c    ****   htim3.Init.Prescaler = 49152;
+ 521              		.loc 1 490 18 is_stmt 0 view .LVU154
+ 522 0014 1348     		ldr	r0, .L45
+ 523 0016 144A     		ldr	r2, .L45+4
+ 524 0018 0260     		str	r2, [r0]
+ 491:Src/main.c    ****   htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 525              		.loc 1 491 3 is_stmt 1 view .LVU155
+ 491:Src/main.c    ****   htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 526              		.loc 1 491 24 is_stmt 0 view .LVU156
+ 527 001a 4FF44042 		mov	r2, #49152
+ 528 001e 4260     		str	r2, [r0, #4]
+ 492:Src/main.c    ****   htim3.Init.Period = 199;
+ 529              		.loc 1 492 3 is_stmt 1 view .LVU157
+ 492:Src/main.c    ****   htim3.Init.Period = 199;
+ 530              		.loc 1 492 26 is_stmt 0 view .LVU158
+ 531 0020 8360     		str	r3, [r0, #8]
+ 493:Src/main.c    ****   htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 532              		.loc 1 493 3 is_stmt 1 view .LVU159
+ 493:Src/main.c    ****   htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 533              		.loc 1 493 21 is_stmt 0 view .LVU160
+ 534 0022 C722     		movs	r2, #199
+ 535 0024 C260     		str	r2, [r0, #12]
+ 494:Src/main.c    ****   htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 536              		.loc 1 494 3 is_stmt 1 view .LVU161
+ 494:Src/main.c    ****   htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 537              		.loc 1 494 28 is_stmt 0 view .LVU162
+ 538 0026 0361     		str	r3, [r0, #16]
+ 495:Src/main.c    ****   if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
+ 539              		.loc 1 495 3 is_stmt 1 view .LVU163
+ 495:Src/main.c    ****   if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
+ 540              		.loc 1 495 32 is_stmt 0 view .LVU164
+ 541 0028 8361     		str	r3, [r0, #24]
+ 496:Src/main.c    ****   {
+ 542              		.loc 1 496 3 is_stmt 1 view .LVU165
+ 496:Src/main.c    ****   {
+ 543              		.loc 1 496 7 is_stmt 0 view .LVU166
+ 544 002a FFF7FEFF 		bl	HAL_TIM_Base_Init
+ 545              	.LVL24:
+ 496:Src/main.c    ****   {
+ 546              		.loc 1 496 6 view .LVU167
+ 547 002e 90B9     		cbnz	r0, .L42
+ARM GAS  /tmp/cc8GRwsk.s 			page 27
+
+
+ 500:Src/main.c    ****   if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
+ 548              		.loc 1 500 3 is_stmt 1 view .LVU168
+ 500:Src/main.c    ****   if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
+ 549              		.loc 1 500 34 is_stmt 0 view .LVU169
+ 550 0030 4FF48053 		mov	r3, #4096
+ 551 0034 0493     		str	r3, [sp, #16]
+ 501:Src/main.c    ****   {
+ 552              		.loc 1 501 3 is_stmt 1 view .LVU170
+ 501:Src/main.c    ****   {
+ 553              		.loc 1 501 7 is_stmt 0 view .LVU171
+ 554 0036 04A9     		add	r1, sp, #16
+ 555 0038 0A48     		ldr	r0, .L45
+ 556 003a FFF7FEFF 		bl	HAL_TIM_ConfigClockSource
+ 557              	.LVL25:
+ 501:Src/main.c    ****   {
+ 558              		.loc 1 501 6 view .LVU172
+ 559 003e 60B9     		cbnz	r0, .L43
+ 505:Src/main.c    ****   sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 560              		.loc 1 505 3 is_stmt 1 view .LVU173
+ 505:Src/main.c    ****   sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 561              		.loc 1 505 37 is_stmt 0 view .LVU174
+ 562 0040 0023     		movs	r3, #0
+ 563 0042 0193     		str	r3, [sp, #4]
+ 506:Src/main.c    ****   if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+ 564              		.loc 1 506 3 is_stmt 1 view .LVU175
+ 506:Src/main.c    ****   if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+ 565              		.loc 1 506 33 is_stmt 0 view .LVU176
+ 566 0044 0393     		str	r3, [sp, #12]
+ 507:Src/main.c    ****   {
+ 567              		.loc 1 507 3 is_stmt 1 view .LVU177
+ 507:Src/main.c    ****   {
+ 568              		.loc 1 507 7 is_stmt 0 view .LVU178
+ 569 0046 01A9     		add	r1, sp, #4
+ 570 0048 0648     		ldr	r0, .L45
+ 571 004a FFF7FEFF 		bl	HAL_TIMEx_MasterConfigSynchronization
+ 572              	.LVL26:
+ 507:Src/main.c    ****   {
+ 573              		.loc 1 507 6 view .LVU179
+ 574 004e 30B9     		cbnz	r0, .L44
+ 515:Src/main.c    **** 
+ 575              		.loc 1 515 1 view .LVU180
+ 576 0050 09B0     		add	sp, sp, #36
+ 577              	.LCFI10:
+ 578              		.cfi_remember_state
+ 579              		.cfi_def_cfa_offset 4
+ 580              		@ sp needed
+ 581 0052 5DF804FB 		ldr	pc, [sp], #4
+ 582              	.L42:
+ 583              	.LCFI11:
+ 584              		.cfi_restore_state
+ 498:Src/main.c    ****   }
+ 585              		.loc 1 498 5 is_stmt 1 view .LVU181
+ 586 0056 FFF7FEFF 		bl	Error_Handler
+ 587              	.LVL27:
+ 588              	.L43:
+ 503:Src/main.c    ****   }
+ 589              		.loc 1 503 5 view .LVU182
+ARM GAS  /tmp/cc8GRwsk.s 			page 28
+
+
+ 590 005a FFF7FEFF 		bl	Error_Handler
+ 591              	.LVL28:
+ 592              	.L44:
+ 509:Src/main.c    ****   }
+ 593              		.loc 1 509 5 view .LVU183
+ 594 005e FFF7FEFF 		bl	Error_Handler
+ 595              	.LVL29:
+ 596              	.L46:
+ 597 0062 00BF     		.align	2
+ 598              	.L45:
+ 599 0064 00000000 		.word	htim3
+ 600 0068 00040040 		.word	1073742848
+ 601              		.cfi_endproc
+ 602              	.LFE339:
+ 604              		.section	.text.MX_ADC1_Init,"ax",%progbits
+ 605              		.align	1
+ 606              		.syntax unified
+ 607              		.thumb
+ 608              		.thumb_func
+ 610              	MX_ADC1_Init:
+ 611              	.LFB335:
+ 205:Src/main.c    **** 
+ 612              		.loc 1 205 1 view -0
+ 613              		.cfi_startproc
+ 614              		@ args = 0, pretend = 0, frame = 48
+ 615              		@ frame_needed = 0, uses_anonymous_args = 0
+ 616 0000 10B5     		push	{r4, lr}
+ 617              	.LCFI12:
+ 618              		.cfi_def_cfa_offset 8
+ 619              		.cfi_offset 4, -8
+ 620              		.cfi_offset 14, -4
+ 621 0002 8CB0     		sub	sp, sp, #48
+ 622              	.LCFI13:
+ 623              		.cfi_def_cfa_offset 56
+ 211:Src/main.c    ****   ADC_ChannelConfTypeDef sConfig = {0};
+ 624              		.loc 1 211 3 view .LVU185
+ 211:Src/main.c    ****   ADC_ChannelConfTypeDef sConfig = {0};
+ 625              		.loc 1 211 24 is_stmt 0 view .LVU186
+ 626 0004 0024     		movs	r4, #0
+ 627 0006 0994     		str	r4, [sp, #36]
+ 628 0008 0A94     		str	r4, [sp, #40]
+ 629 000a 0B94     		str	r4, [sp, #44]
+ 212:Src/main.c    **** 
+ 630              		.loc 1 212 3 is_stmt 1 view .LVU187
+ 212:Src/main.c    **** 
+ 631              		.loc 1 212 26 is_stmt 0 view .LVU188
+ 632 000c 2022     		movs	r2, #32
+ 633 000e 2146     		mov	r1, r4
+ 634 0010 01A8     		add	r0, sp, #4
+ 635 0012 FFF7FEFF 		bl	memset
+ 636              	.LVL30:
+ 220:Src/main.c    ****   hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
+ 637              		.loc 1 220 3 is_stmt 1 view .LVU189
+ 220:Src/main.c    ****   hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
+ 638              		.loc 1 220 18 is_stmt 0 view .LVU190
+ 639 0016 1E48     		ldr	r0, .L55
+ 640 0018 4FF0A043 		mov	r3, #1342177280
+ARM GAS  /tmp/cc8GRwsk.s 			page 29
+
+
+ 641 001c 0360     		str	r3, [r0]
+ 221:Src/main.c    ****   hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+ 642              		.loc 1 221 3 is_stmt 1 view .LVU191
+ 221:Src/main.c    ****   hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+ 643              		.loc 1 221 29 is_stmt 0 view .LVU192
+ 644 001e 4FF40033 		mov	r3, #131072
+ 645 0022 4360     		str	r3, [r0, #4]
+ 222:Src/main.c    ****   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 646              		.loc 1 222 3 is_stmt 1 view .LVU193
+ 222:Src/main.c    ****   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 647              		.loc 1 222 25 is_stmt 0 view .LVU194
+ 648 0024 8460     		str	r4, [r0, #8]
+ 223:Src/main.c    ****   hadc1.Init.GainCompensation = 0;
+ 649              		.loc 1 223 3 is_stmt 1 view .LVU195
+ 223:Src/main.c    ****   hadc1.Init.GainCompensation = 0;
+ 650              		.loc 1 223 24 is_stmt 0 view .LVU196
+ 651 0026 C460     		str	r4, [r0, #12]
+ 224:Src/main.c    ****   hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+ 652              		.loc 1 224 3 is_stmt 1 view .LVU197
+ 224:Src/main.c    ****   hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+ 653              		.loc 1 224 31 is_stmt 0 view .LVU198
+ 654 0028 0461     		str	r4, [r0, #16]
+ 225:Src/main.c    ****   hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 655              		.loc 1 225 3 is_stmt 1 view .LVU199
+ 225:Src/main.c    ****   hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 656              		.loc 1 225 27 is_stmt 0 view .LVU200
+ 657 002a 4461     		str	r4, [r0, #20]
+ 226:Src/main.c    ****   hadc1.Init.LowPowerAutoWait = DISABLE;
+ 658              		.loc 1 226 3 is_stmt 1 view .LVU201
+ 226:Src/main.c    ****   hadc1.Init.LowPowerAutoWait = DISABLE;
+ 659              		.loc 1 226 27 is_stmt 0 view .LVU202
+ 660 002c 0423     		movs	r3, #4
+ 661 002e 8361     		str	r3, [r0, #24]
+ 227:Src/main.c    ****   hadc1.Init.ContinuousConvMode = DISABLE;
+ 662              		.loc 1 227 3 is_stmt 1 view .LVU203
+ 227:Src/main.c    ****   hadc1.Init.ContinuousConvMode = DISABLE;
+ 663              		.loc 1 227 31 is_stmt 0 view .LVU204
+ 664 0030 0477     		strb	r4, [r0, #28]
+ 228:Src/main.c    ****   hadc1.Init.NbrOfConversion = 1;
+ 665              		.loc 1 228 3 is_stmt 1 view .LVU205
+ 228:Src/main.c    ****   hadc1.Init.NbrOfConversion = 1;
+ 666              		.loc 1 228 33 is_stmt 0 view .LVU206
+ 667 0032 4477     		strb	r4, [r0, #29]
+ 229:Src/main.c    ****   hadc1.Init.DiscontinuousConvMode = DISABLE;
+ 668              		.loc 1 229 3 is_stmt 1 view .LVU207
+ 229:Src/main.c    ****   hadc1.Init.DiscontinuousConvMode = DISABLE;
+ 669              		.loc 1 229 30 is_stmt 0 view .LVU208
+ 670 0034 0123     		movs	r3, #1
+ 671 0036 0362     		str	r3, [r0, #32]
+ 230:Src/main.c    ****   hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 672              		.loc 1 230 3 is_stmt 1 view .LVU209
+ 230:Src/main.c    ****   hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 673              		.loc 1 230 36 is_stmt 0 view .LVU210
+ 674 0038 80F82440 		strb	r4, [r0, #36]
+ 231:Src/main.c    ****   hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 675              		.loc 1 231 3 is_stmt 1 view .LVU211
+ 231:Src/main.c    ****   hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ARM GAS  /tmp/cc8GRwsk.s 			page 30
+
+
+ 676              		.loc 1 231 31 is_stmt 0 view .LVU212
+ 677 003c C462     		str	r4, [r0, #44]
+ 232:Src/main.c    ****   hadc1.Init.DMAContinuousRequests = DISABLE;
+ 678              		.loc 1 232 3 is_stmt 1 view .LVU213
+ 232:Src/main.c    ****   hadc1.Init.DMAContinuousRequests = DISABLE;
+ 679              		.loc 1 232 35 is_stmt 0 view .LVU214
+ 680 003e 0463     		str	r4, [r0, #48]
+ 233:Src/main.c    ****   hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+ 681              		.loc 1 233 3 is_stmt 1 view .LVU215
+ 233:Src/main.c    ****   hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+ 682              		.loc 1 233 36 is_stmt 0 view .LVU216
+ 683 0040 80F83840 		strb	r4, [r0, #56]
+ 234:Src/main.c    ****   hadc1.Init.OversamplingMode = DISABLE;
+ 684              		.loc 1 234 3 is_stmt 1 view .LVU217
+ 234:Src/main.c    ****   hadc1.Init.OversamplingMode = DISABLE;
+ 685              		.loc 1 234 22 is_stmt 0 view .LVU218
+ 686 0044 C463     		str	r4, [r0, #60]
+ 235:Src/main.c    ****   if (HAL_ADC_Init(&hadc1) != HAL_OK)
+ 687              		.loc 1 235 3 is_stmt 1 view .LVU219
+ 235:Src/main.c    ****   if (HAL_ADC_Init(&hadc1) != HAL_OK)
+ 688              		.loc 1 235 31 is_stmt 0 view .LVU220
+ 689 0046 80F84040 		strb	r4, [r0, #64]
+ 236:Src/main.c    ****   {
+ 690              		.loc 1 236 3 is_stmt 1 view .LVU221
+ 236:Src/main.c    ****   {
+ 691              		.loc 1 236 7 is_stmt 0 view .LVU222
+ 692 004a FFF7FEFF 		bl	HAL_ADC_Init
+ 693              	.LVL31:
+ 236:Src/main.c    ****   {
+ 694              		.loc 1 236 6 view .LVU223
+ 695 004e C8B9     		cbnz	r0, .L52
+ 243:Src/main.c    ****   if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
+ 696              		.loc 1 243 3 is_stmt 1 view .LVU224
+ 243:Src/main.c    ****   if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
+ 697              		.loc 1 243 18 is_stmt 0 view .LVU225
+ 698 0050 0023     		movs	r3, #0
+ 699 0052 0993     		str	r3, [sp, #36]
+ 244:Src/main.c    ****   {
+ 700              		.loc 1 244 3 is_stmt 1 view .LVU226
+ 244:Src/main.c    ****   {
+ 701              		.loc 1 244 7 is_stmt 0 view .LVU227
+ 702 0054 09A9     		add	r1, sp, #36
+ 703 0056 0E48     		ldr	r0, .L55
+ 704 0058 FFF7FEFF 		bl	HAL_ADCEx_MultiModeConfigChannel
+ 705              	.LVL32:
+ 244:Src/main.c    ****   {
+ 706              		.loc 1 244 6 view .LVU228
+ 707 005c A0B9     		cbnz	r0, .L53
+ 251:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_1;
+ 708              		.loc 1 251 3 is_stmt 1 view .LVU229
+ 251:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_1;
+ 709              		.loc 1 251 19 is_stmt 0 view .LVU230
+ 710 005e 0D4B     		ldr	r3, .L55+4
+ 711 0060 0193     		str	r3, [sp, #4]
+ 252:Src/main.c    ****   sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
+ 712              		.loc 1 252 3 is_stmt 1 view .LVU231
+ 252:Src/main.c    ****   sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
+ARM GAS  /tmp/cc8GRwsk.s 			page 31
+
+
+ 713              		.loc 1 252 16 is_stmt 0 view .LVU232
+ 714 0062 0623     		movs	r3, #6
+ 715 0064 0293     		str	r3, [sp, #8]
+ 253:Src/main.c    ****   sConfig.SingleDiff = ADC_SINGLE_ENDED;
+ 716              		.loc 1 253 3 is_stmt 1 view .LVU233
+ 253:Src/main.c    ****   sConfig.SingleDiff = ADC_SINGLE_ENDED;
+ 717              		.loc 1 253 24 is_stmt 0 view .LVU234
+ 718 0066 0023     		movs	r3, #0
+ 719 0068 0393     		str	r3, [sp, #12]
+ 254:Src/main.c    ****   sConfig.OffsetNumber = ADC_OFFSET_NONE;
+ 720              		.loc 1 254 3 is_stmt 1 view .LVU235
+ 254:Src/main.c    ****   sConfig.OffsetNumber = ADC_OFFSET_NONE;
+ 721              		.loc 1 254 22 is_stmt 0 view .LVU236
+ 722 006a 7F22     		movs	r2, #127
+ 723 006c 0492     		str	r2, [sp, #16]
+ 255:Src/main.c    ****   sConfig.Offset = 0;
+ 724              		.loc 1 255 3 is_stmt 1 view .LVU237
+ 255:Src/main.c    ****   sConfig.Offset = 0;
+ 725              		.loc 1 255 24 is_stmt 0 view .LVU238
+ 726 006e 0422     		movs	r2, #4
+ 727 0070 0592     		str	r2, [sp, #20]
+ 256:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 728              		.loc 1 256 3 is_stmt 1 view .LVU239
+ 256:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 729              		.loc 1 256 18 is_stmt 0 view .LVU240
+ 730 0072 0693     		str	r3, [sp, #24]
+ 257:Src/main.c    ****   {
+ 731              		.loc 1 257 3 is_stmt 1 view .LVU241
+ 257:Src/main.c    ****   {
+ 732              		.loc 1 257 7 is_stmt 0 view .LVU242
+ 733 0074 0DEB0201 		add	r1, sp, r2
+ 734 0078 0548     		ldr	r0, .L55
+ 735 007a FFF7FEFF 		bl	HAL_ADC_ConfigChannel
+ 736              	.LVL33:
+ 257:Src/main.c    ****   {
+ 737              		.loc 1 257 6 view .LVU243
+ 738 007e 28B9     		cbnz	r0, .L54
+ 265:Src/main.c    **** 
+ 739              		.loc 1 265 1 view .LVU244
+ 740 0080 0CB0     		add	sp, sp, #48
+ 741              	.LCFI14:
+ 742              		.cfi_remember_state
+ 743              		.cfi_def_cfa_offset 8
+ 744              		@ sp needed
+ 745 0082 10BD     		pop	{r4, pc}
+ 746              	.L52:
+ 747              	.LCFI15:
+ 748              		.cfi_restore_state
+ 238:Src/main.c    ****   }
+ 749              		.loc 1 238 5 is_stmt 1 view .LVU245
+ 750 0084 FFF7FEFF 		bl	Error_Handler
+ 751              	.LVL34:
+ 752              	.L53:
+ 246:Src/main.c    ****   }
+ 753              		.loc 1 246 5 view .LVU246
+ 754 0088 FFF7FEFF 		bl	Error_Handler
+ 755              	.LVL35:
+ARM GAS  /tmp/cc8GRwsk.s 			page 32
+
+
+ 756              	.L54:
+ 259:Src/main.c    ****   }
+ 757              		.loc 1 259 5 view .LVU247
+ 758 008c FFF7FEFF 		bl	Error_Handler
+ 759              	.LVL36:
+ 760              	.L56:
+ 761              		.align	2
+ 762              	.L55:
+ 763 0090 00000000 		.word	hadc1
+ 764 0094 0080F03E 		.word	1055948800
+ 765              		.cfi_endproc
+ 766              	.LFE335:
+ 768              		.section	.text.MX_ADC2_Init,"ax",%progbits
+ 769              		.align	1
+ 770              		.syntax unified
+ 771              		.thumb
+ 772              		.thumb_func
+ 774              	MX_ADC2_Init:
+ 775              	.LFB336:
+ 273:Src/main.c    **** 
+ 776              		.loc 1 273 1 view -0
+ 777              		.cfi_startproc
+ 778              		@ args = 0, pretend = 0, frame = 32
+ 779              		@ frame_needed = 0, uses_anonymous_args = 0
+ 780 0000 00B5     		push	{lr}
+ 781              	.LCFI16:
+ 782              		.cfi_def_cfa_offset 4
+ 783              		.cfi_offset 14, -4
+ 784 0002 89B0     		sub	sp, sp, #36
+ 785              	.LCFI17:
+ 786              		.cfi_def_cfa_offset 40
+ 279:Src/main.c    **** 
+ 787              		.loc 1 279 3 view .LVU249
+ 279:Src/main.c    **** 
+ 788              		.loc 1 279 26 is_stmt 0 view .LVU250
+ 789 0004 2022     		movs	r2, #32
+ 790 0006 0021     		movs	r1, #0
+ 791 0008 6846     		mov	r0, sp
+ 792 000a FFF7FEFF 		bl	memset
+ 793              	.LVL37:
+ 287:Src/main.c    ****   hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
+ 794              		.loc 1 287 3 is_stmt 1 view .LVU251
+ 287:Src/main.c    ****   hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
+ 795              		.loc 1 287 18 is_stmt 0 view .LVU252
+ 796 000e 2848     		ldr	r0, .L69
+ 797 0010 284B     		ldr	r3, .L69+4
+ 798 0012 0360     		str	r3, [r0]
+ 288:Src/main.c    ****   hadc2.Init.Resolution = ADC_RESOLUTION_12B;
+ 799              		.loc 1 288 3 is_stmt 1 view .LVU253
+ 288:Src/main.c    ****   hadc2.Init.Resolution = ADC_RESOLUTION_12B;
+ 800              		.loc 1 288 29 is_stmt 0 view .LVU254
+ 801 0014 4FF40033 		mov	r3, #131072
+ 802 0018 4360     		str	r3, [r0, #4]
+ 289:Src/main.c    ****   hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 803              		.loc 1 289 3 is_stmt 1 view .LVU255
+ 289:Src/main.c    ****   hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 804              		.loc 1 289 25 is_stmt 0 view .LVU256
+ARM GAS  /tmp/cc8GRwsk.s 			page 33
+
+
+ 805 001a 0023     		movs	r3, #0
+ 806 001c 8360     		str	r3, [r0, #8]
+ 290:Src/main.c    ****   hadc2.Init.GainCompensation = 0;
+ 807              		.loc 1 290 3 is_stmt 1 view .LVU257
+ 290:Src/main.c    ****   hadc2.Init.GainCompensation = 0;
+ 808              		.loc 1 290 24 is_stmt 0 view .LVU258
+ 809 001e C360     		str	r3, [r0, #12]
+ 291:Src/main.c    ****   hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
+ 810              		.loc 1 291 3 is_stmt 1 view .LVU259
+ 291:Src/main.c    ****   hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
+ 811              		.loc 1 291 31 is_stmt 0 view .LVU260
+ 812 0020 0361     		str	r3, [r0, #16]
+ 292:Src/main.c    ****   hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
+ 813              		.loc 1 292 3 is_stmt 1 view .LVU261
+ 292:Src/main.c    ****   hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
+ 814              		.loc 1 292 27 is_stmt 0 view .LVU262
+ 815 0022 0122     		movs	r2, #1
+ 816 0024 4261     		str	r2, [r0, #20]
+ 293:Src/main.c    ****   hadc2.Init.LowPowerAutoWait = DISABLE;
+ 817              		.loc 1 293 3 is_stmt 1 view .LVU263
+ 293:Src/main.c    ****   hadc2.Init.LowPowerAutoWait = DISABLE;
+ 818              		.loc 1 293 27 is_stmt 0 view .LVU264
+ 819 0026 0822     		movs	r2, #8
+ 820 0028 8261     		str	r2, [r0, #24]
+ 294:Src/main.c    ****   hadc2.Init.ContinuousConvMode = DISABLE;
+ 821              		.loc 1 294 3 is_stmt 1 view .LVU265
+ 294:Src/main.c    ****   hadc2.Init.ContinuousConvMode = DISABLE;
+ 822              		.loc 1 294 31 is_stmt 0 view .LVU266
+ 823 002a 0377     		strb	r3, [r0, #28]
+ 295:Src/main.c    ****   hadc2.Init.NbrOfConversion = 4;
+ 824              		.loc 1 295 3 is_stmt 1 view .LVU267
+ 295:Src/main.c    ****   hadc2.Init.NbrOfConversion = 4;
+ 825              		.loc 1 295 33 is_stmt 0 view .LVU268
+ 826 002c 4377     		strb	r3, [r0, #29]
+ 296:Src/main.c    ****   hadc2.Init.DiscontinuousConvMode = DISABLE;
+ 827              		.loc 1 296 3 is_stmt 1 view .LVU269
+ 296:Src/main.c    ****   hadc2.Init.DiscontinuousConvMode = DISABLE;
+ 828              		.loc 1 296 30 is_stmt 0 view .LVU270
+ 829 002e 0422     		movs	r2, #4
+ 830 0030 0262     		str	r2, [r0, #32]
+ 297:Src/main.c    ****   hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 831              		.loc 1 297 3 is_stmt 1 view .LVU271
+ 297:Src/main.c    ****   hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 832              		.loc 1 297 36 is_stmt 0 view .LVU272
+ 833 0032 80F82430 		strb	r3, [r0, #36]
+ 298:Src/main.c    ****   hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 834              		.loc 1 298 3 is_stmt 1 view .LVU273
+ 298:Src/main.c    ****   hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 835              		.loc 1 298 31 is_stmt 0 view .LVU274
+ 836 0036 C362     		str	r3, [r0, #44]
+ 299:Src/main.c    ****   hadc2.Init.DMAContinuousRequests = DISABLE;
+ 837              		.loc 1 299 3 is_stmt 1 view .LVU275
+ 299:Src/main.c    ****   hadc2.Init.DMAContinuousRequests = DISABLE;
+ 838              		.loc 1 299 35 is_stmt 0 view .LVU276
+ 839 0038 0363     		str	r3, [r0, #48]
+ 300:Src/main.c    ****   hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+ 840              		.loc 1 300 3 is_stmt 1 view .LVU277
+ARM GAS  /tmp/cc8GRwsk.s 			page 34
+
+
+ 300:Src/main.c    ****   hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+ 841              		.loc 1 300 36 is_stmt 0 view .LVU278
+ 842 003a 80F83830 		strb	r3, [r0, #56]
+ 301:Src/main.c    ****   hadc2.Init.OversamplingMode = DISABLE;
+ 843              		.loc 1 301 3 is_stmt 1 view .LVU279
+ 301:Src/main.c    ****   hadc2.Init.OversamplingMode = DISABLE;
+ 844              		.loc 1 301 22 is_stmt 0 view .LVU280
+ 845 003e C363     		str	r3, [r0, #60]
+ 302:Src/main.c    ****   if (HAL_ADC_Init(&hadc2) != HAL_OK)
+ 846              		.loc 1 302 3 is_stmt 1 view .LVU281
+ 302:Src/main.c    ****   if (HAL_ADC_Init(&hadc2) != HAL_OK)
+ 847              		.loc 1 302 31 is_stmt 0 view .LVU282
+ 848 0040 80F84030 		strb	r3, [r0, #64]
+ 303:Src/main.c    ****   {
+ 849              		.loc 1 303 3 is_stmt 1 view .LVU283
+ 303:Src/main.c    ****   {
+ 850              		.loc 1 303 7 is_stmt 0 view .LVU284
+ 851 0044 FFF7FEFF 		bl	HAL_ADC_Init
+ 852              	.LVL38:
+ 303:Src/main.c    ****   {
+ 853              		.loc 1 303 6 view .LVU285
+ 854 0048 38BB     		cbnz	r0, .L64
+ 310:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_1;
+ 855              		.loc 1 310 3 is_stmt 1 view .LVU286
+ 310:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_1;
+ 856              		.loc 1 310 19 is_stmt 0 view .LVU287
+ 857 004a 1B4B     		ldr	r3, .L69+8
+ 858 004c 0093     		str	r3, [sp]
+ 311:Src/main.c    ****   sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
+ 859              		.loc 1 311 3 is_stmt 1 view .LVU288
+ 311:Src/main.c    ****   sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
+ 860              		.loc 1 311 16 is_stmt 0 view .LVU289
+ 861 004e 0623     		movs	r3, #6
+ 862 0050 0193     		str	r3, [sp, #4]
+ 312:Src/main.c    ****   sConfig.SingleDiff = ADC_SINGLE_ENDED;
+ 863              		.loc 1 312 3 is_stmt 1 view .LVU290
+ 312:Src/main.c    ****   sConfig.SingleDiff = ADC_SINGLE_ENDED;
+ 864              		.loc 1 312 24 is_stmt 0 view .LVU291
+ 865 0052 0023     		movs	r3, #0
+ 866 0054 0293     		str	r3, [sp, #8]
+ 313:Src/main.c    ****   sConfig.OffsetNumber = ADC_OFFSET_NONE;
+ 867              		.loc 1 313 3 is_stmt 1 view .LVU292
+ 313:Src/main.c    ****   sConfig.OffsetNumber = ADC_OFFSET_NONE;
+ 868              		.loc 1 313 22 is_stmt 0 view .LVU293
+ 869 0056 7F22     		movs	r2, #127
+ 870 0058 0392     		str	r2, [sp, #12]
+ 314:Src/main.c    ****   sConfig.Offset = 0;
+ 871              		.loc 1 314 3 is_stmt 1 view .LVU294
+ 314:Src/main.c    ****   sConfig.Offset = 0;
+ 872              		.loc 1 314 24 is_stmt 0 view .LVU295
+ 873 005a 0422     		movs	r2, #4
+ 874 005c 0492     		str	r2, [sp, #16]
+ 315:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ 875              		.loc 1 315 3 is_stmt 1 view .LVU296
+ 315:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ 876              		.loc 1 315 18 is_stmt 0 view .LVU297
+ 877 005e 0593     		str	r3, [sp, #20]
+ARM GAS  /tmp/cc8GRwsk.s 			page 35
+
+
+ 316:Src/main.c    ****   {
+ 878              		.loc 1 316 3 is_stmt 1 view .LVU298
+ 316:Src/main.c    ****   {
+ 879              		.loc 1 316 7 is_stmt 0 view .LVU299
+ 880 0060 6946     		mov	r1, sp
+ 881 0062 1348     		ldr	r0, .L69
+ 882 0064 FFF7FEFF 		bl	HAL_ADC_ConfigChannel
+ 883              	.LVL39:
+ 316:Src/main.c    ****   {
+ 884              		.loc 1 316 6 view .LVU300
+ 885 0068 C8B9     		cbnz	r0, .L65
+ 323:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ 886              		.loc 1 323 3 is_stmt 1 view .LVU301
+ 323:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ 887              		.loc 1 323 16 is_stmt 0 view .LVU302
+ 888 006a 0C23     		movs	r3, #12
+ 889 006c 0193     		str	r3, [sp, #4]
+ 324:Src/main.c    ****   {
+ 890              		.loc 1 324 3 is_stmt 1 view .LVU303
+ 324:Src/main.c    ****   {
+ 891              		.loc 1 324 7 is_stmt 0 view .LVU304
+ 892 006e 6946     		mov	r1, sp
+ 893 0070 0F48     		ldr	r0, .L69
+ 894 0072 FFF7FEFF 		bl	HAL_ADC_ConfigChannel
+ 895              	.LVL40:
+ 324:Src/main.c    ****   {
+ 896              		.loc 1 324 6 view .LVU305
+ 897 0076 A0B9     		cbnz	r0, .L66
+ 331:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ 898              		.loc 1 331 3 is_stmt 1 view .LVU306
+ 331:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ 899              		.loc 1 331 16 is_stmt 0 view .LVU307
+ 900 0078 1223     		movs	r3, #18
+ 901 007a 0193     		str	r3, [sp, #4]
+ 332:Src/main.c    ****   {
+ 902              		.loc 1 332 3 is_stmt 1 view .LVU308
+ 332:Src/main.c    ****   {
+ 903              		.loc 1 332 7 is_stmt 0 view .LVU309
+ 904 007c 6946     		mov	r1, sp
+ 905 007e 0C48     		ldr	r0, .L69
+ 906 0080 FFF7FEFF 		bl	HAL_ADC_ConfigChannel
+ 907              	.LVL41:
+ 332:Src/main.c    ****   {
+ 908              		.loc 1 332 6 view .LVU310
+ 909 0084 78B9     		cbnz	r0, .L67
+ 339:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ 910              		.loc 1 339 3 is_stmt 1 view .LVU311
+ 339:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ 911              		.loc 1 339 16 is_stmt 0 view .LVU312
+ 912 0086 1823     		movs	r3, #24
+ 913 0088 0193     		str	r3, [sp, #4]
+ 340:Src/main.c    ****   {
+ 914              		.loc 1 340 3 is_stmt 1 view .LVU313
+ 340:Src/main.c    ****   {
+ 915              		.loc 1 340 7 is_stmt 0 view .LVU314
+ 916 008a 6946     		mov	r1, sp
+ 917 008c 0848     		ldr	r0, .L69
+ARM GAS  /tmp/cc8GRwsk.s 			page 36
+
+
+ 918 008e FFF7FEFF 		bl	HAL_ADC_ConfigChannel
+ 919              	.LVL42:
+ 340:Src/main.c    ****   {
+ 920              		.loc 1 340 6 view .LVU315
+ 921 0092 50B9     		cbnz	r0, .L68
+ 348:Src/main.c    **** 
+ 922              		.loc 1 348 1 view .LVU316
+ 923 0094 09B0     		add	sp, sp, #36
+ 924              	.LCFI18:
+ 925              		.cfi_remember_state
+ 926              		.cfi_def_cfa_offset 4
+ 927              		@ sp needed
+ 928 0096 5DF804FB 		ldr	pc, [sp], #4
+ 929              	.L64:
+ 930              	.LCFI19:
+ 931              		.cfi_restore_state
+ 305:Src/main.c    ****   }
+ 932              		.loc 1 305 5 is_stmt 1 view .LVU317
+ 933 009a FFF7FEFF 		bl	Error_Handler
+ 934              	.LVL43:
+ 935              	.L65:
+ 318:Src/main.c    ****   }
+ 936              		.loc 1 318 5 view .LVU318
+ 937 009e FFF7FEFF 		bl	Error_Handler
+ 938              	.LVL44:
+ 939              	.L66:
+ 326:Src/main.c    ****   }
+ 940              		.loc 1 326 5 view .LVU319
+ 941 00a2 FFF7FEFF 		bl	Error_Handler
+ 942              	.LVL45:
+ 943              	.L67:
+ 334:Src/main.c    ****   }
+ 944              		.loc 1 334 5 view .LVU320
+ 945 00a6 FFF7FEFF 		bl	Error_Handler
+ 946              	.LVL46:
+ 947              	.L68:
+ 342:Src/main.c    ****   }
+ 948              		.loc 1 342 5 view .LVU321
+ 949 00aa FFF7FEFF 		bl	Error_Handler
+ 950              	.LVL47:
+ 951              	.L70:
+ 952 00ae 00BF     		.align	2
+ 953              	.L69:
+ 954 00b0 00000000 		.word	hadc2
+ 955 00b4 00010050 		.word	1342177536
+ 956 00b8 0800900C 		.word	210763784
+ 957              		.cfi_endproc
+ 958              	.LFE336:
+ 960              		.section	.text.MX_USART1_UART_Init,"ax",%progbits
+ 961              		.align	1
+ 962              		.syntax unified
+ 963              		.thumb
+ 964              		.thumb_func
+ 966              	MX_USART1_UART_Init:
+ 967              	.LFB340:
+ 523:Src/main.c    **** 
+ 968              		.loc 1 523 1 view -0
+ARM GAS  /tmp/cc8GRwsk.s 			page 37
+
+
+ 969              		.cfi_startproc
+ 970              		@ args = 0, pretend = 0, frame = 0
+ 971              		@ frame_needed = 0, uses_anonymous_args = 0
+ 972 0000 08B5     		push	{r3, lr}
+ 973              	.LCFI20:
+ 974              		.cfi_def_cfa_offset 8
+ 975              		.cfi_offset 3, -8
+ 976              		.cfi_offset 14, -4
+ 532:Src/main.c    ****   huart1.Init.BaudRate = 115200;
+ 977              		.loc 1 532 3 view .LVU323
+ 532:Src/main.c    ****   huart1.Init.BaudRate = 115200;
+ 978              		.loc 1 532 19 is_stmt 0 view .LVU324
+ 979 0002 1548     		ldr	r0, .L81
+ 980 0004 154B     		ldr	r3, .L81+4
+ 981 0006 0360     		str	r3, [r0]
+ 533:Src/main.c    ****   huart1.Init.WordLength = UART_WORDLENGTH_8B;
+ 982              		.loc 1 533 3 is_stmt 1 view .LVU325
+ 533:Src/main.c    ****   huart1.Init.WordLength = UART_WORDLENGTH_8B;
+ 983              		.loc 1 533 24 is_stmt 0 view .LVU326
+ 984 0008 4FF4E133 		mov	r3, #115200
+ 985 000c 4360     		str	r3, [r0, #4]
+ 534:Src/main.c    ****   huart1.Init.StopBits = UART_STOPBITS_1;
+ 986              		.loc 1 534 3 is_stmt 1 view .LVU327
+ 534:Src/main.c    ****   huart1.Init.StopBits = UART_STOPBITS_1;
+ 987              		.loc 1 534 26 is_stmt 0 view .LVU328
+ 988 000e 0023     		movs	r3, #0
+ 989 0010 8360     		str	r3, [r0, #8]
+ 535:Src/main.c    ****   huart1.Init.Parity = UART_PARITY_NONE;
+ 990              		.loc 1 535 3 is_stmt 1 view .LVU329
+ 535:Src/main.c    ****   huart1.Init.Parity = UART_PARITY_NONE;
+ 991              		.loc 1 535 24 is_stmt 0 view .LVU330
+ 992 0012 C360     		str	r3, [r0, #12]
+ 536:Src/main.c    ****   huart1.Init.Mode = UART_MODE_TX_RX;
+ 993              		.loc 1 536 3 is_stmt 1 view .LVU331
+ 536:Src/main.c    ****   huart1.Init.Mode = UART_MODE_TX_RX;
+ 994              		.loc 1 536 22 is_stmt 0 view .LVU332
+ 995 0014 0361     		str	r3, [r0, #16]
+ 537:Src/main.c    ****   huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 996              		.loc 1 537 3 is_stmt 1 view .LVU333
+ 537:Src/main.c    ****   huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 997              		.loc 1 537 20 is_stmt 0 view .LVU334
+ 998 0016 0C22     		movs	r2, #12
+ 999 0018 4261     		str	r2, [r0, #20]
+ 538:Src/main.c    ****   huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+ 1000              		.loc 1 538 3 is_stmt 1 view .LVU335
+ 538:Src/main.c    ****   huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+ 1001              		.loc 1 538 25 is_stmt 0 view .LVU336
+ 1002 001a 8361     		str	r3, [r0, #24]
+ 539:Src/main.c    ****   huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 1003              		.loc 1 539 3 is_stmt 1 view .LVU337
+ 539:Src/main.c    ****   huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 1004              		.loc 1 539 28 is_stmt 0 view .LVU338
+ 1005 001c C361     		str	r3, [r0, #28]
+ 540:Src/main.c    ****   huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 1006              		.loc 1 540 3 is_stmt 1 view .LVU339
+ 540:Src/main.c    ****   huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 1007              		.loc 1 540 30 is_stmt 0 view .LVU340
+ARM GAS  /tmp/cc8GRwsk.s 			page 38
+
+
+ 1008 001e 0362     		str	r3, [r0, #32]
+ 541:Src/main.c    ****   huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ 1009              		.loc 1 541 3 is_stmt 1 view .LVU341
+ 541:Src/main.c    ****   huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ 1010              		.loc 1 541 30 is_stmt 0 view .LVU342
+ 1011 0020 4362     		str	r3, [r0, #36]
+ 542:Src/main.c    ****   if (HAL_UART_Init(&huart1) != HAL_OK)
+ 1012              		.loc 1 542 3 is_stmt 1 view .LVU343
+ 542:Src/main.c    ****   if (HAL_UART_Init(&huart1) != HAL_OK)
+ 1013              		.loc 1 542 38 is_stmt 0 view .LVU344
+ 1014 0022 8362     		str	r3, [r0, #40]
+ 543:Src/main.c    ****   {
+ 1015              		.loc 1 543 3 is_stmt 1 view .LVU345
+ 543:Src/main.c    ****   {
+ 1016              		.loc 1 543 7 is_stmt 0 view .LVU346
+ 1017 0024 FFF7FEFF 		bl	HAL_UART_Init
+ 1018              	.LVL48:
+ 543:Src/main.c    ****   {
+ 1019              		.loc 1 543 6 view .LVU347
+ 1020 0028 70B9     		cbnz	r0, .L77
+ 547:Src/main.c    ****   {
+ 1021              		.loc 1 547 3 is_stmt 1 view .LVU348
+ 547:Src/main.c    ****   {
+ 1022              		.loc 1 547 7 is_stmt 0 view .LVU349
+ 1023 002a 0021     		movs	r1, #0
+ 1024 002c 0A48     		ldr	r0, .L81
+ 1025 002e FFF7FEFF 		bl	HAL_UARTEx_SetTxFifoThreshold
+ 1026              	.LVL49:
+ 547:Src/main.c    ****   {
+ 1027              		.loc 1 547 6 view .LVU350
+ 1028 0032 58B9     		cbnz	r0, .L78
+ 551:Src/main.c    ****   {
+ 1029              		.loc 1 551 3 is_stmt 1 view .LVU351
+ 551:Src/main.c    ****   {
+ 1030              		.loc 1 551 7 is_stmt 0 view .LVU352
+ 1031 0034 0021     		movs	r1, #0
+ 1032 0036 0848     		ldr	r0, .L81
+ 1033 0038 FFF7FEFF 		bl	HAL_UARTEx_SetRxFifoThreshold
+ 1034              	.LVL50:
+ 551:Src/main.c    ****   {
+ 1035              		.loc 1 551 6 view .LVU353
+ 1036 003c 40B9     		cbnz	r0, .L79
+ 555:Src/main.c    ****   {
+ 1037              		.loc 1 555 3 is_stmt 1 view .LVU354
+ 555:Src/main.c    ****   {
+ 1038              		.loc 1 555 7 is_stmt 0 view .LVU355
+ 1039 003e 0648     		ldr	r0, .L81
+ 1040 0040 FFF7FEFF 		bl	HAL_UARTEx_DisableFifoMode
+ 1041              	.LVL51:
+ 555:Src/main.c    ****   {
+ 1042              		.loc 1 555 6 view .LVU356
+ 1043 0044 30B9     		cbnz	r0, .L80
+ 563:Src/main.c    **** 
+ 1044              		.loc 1 563 1 view .LVU357
+ 1045 0046 08BD     		pop	{r3, pc}
+ 1046              	.L77:
+ 545:Src/main.c    ****   }
+ARM GAS  /tmp/cc8GRwsk.s 			page 39
+
+
+ 1047              		.loc 1 545 5 is_stmt 1 view .LVU358
+ 1048 0048 FFF7FEFF 		bl	Error_Handler
+ 1049              	.LVL52:
+ 1050              	.L78:
+ 549:Src/main.c    ****   }
+ 1051              		.loc 1 549 5 view .LVU359
+ 1052 004c FFF7FEFF 		bl	Error_Handler
+ 1053              	.LVL53:
+ 1054              	.L79:
+ 553:Src/main.c    ****   }
+ 1055              		.loc 1 553 5 view .LVU360
+ 1056 0050 FFF7FEFF 		bl	Error_Handler
+ 1057              	.LVL54:
+ 1058              	.L80:
+ 557:Src/main.c    ****   }
+ 1059              		.loc 1 557 5 view .LVU361
+ 1060 0054 FFF7FEFF 		bl	Error_Handler
+ 1061              	.LVL55:
+ 1062              	.L82:
+ 1063              		.align	2
+ 1064              	.L81:
+ 1065 0058 00000000 		.word	huart1
+ 1066 005c 00380140 		.word	1073821696
+ 1067              		.cfi_endproc
+ 1068              	.LFE340:
+ 1070              		.section	.text.SystemClock_Config,"ax",%progbits
+ 1071              		.align	1
+ 1072              		.global	SystemClock_Config
+ 1073              		.syntax unified
+ 1074              		.thumb
+ 1075              		.thumb_func
+ 1077              	SystemClock_Config:
+ 1078              	.LFB334:
+ 157:Src/main.c    ****   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 1079              		.loc 1 157 1 view -0
+ 1080              		.cfi_startproc
+ 1081              		@ args = 0, pretend = 0, frame = 80
+ 1082              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1083 0000 00B5     		push	{lr}
+ 1084              	.LCFI21:
+ 1085              		.cfi_def_cfa_offset 4
+ 1086              		.cfi_offset 14, -4
+ 1087 0002 95B0     		sub	sp, sp, #84
+ 1088              	.LCFI22:
+ 1089              		.cfi_def_cfa_offset 88
+ 158:Src/main.c    ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 1090              		.loc 1 158 3 view .LVU363
+ 158:Src/main.c    ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 1091              		.loc 1 158 22 is_stmt 0 view .LVU364
+ 1092 0004 3822     		movs	r2, #56
+ 1093 0006 0021     		movs	r1, #0
+ 1094 0008 06A8     		add	r0, sp, #24
+ 1095 000a FFF7FEFF 		bl	memset
+ 1096              	.LVL56:
+ 159:Src/main.c    **** 
+ 1097              		.loc 1 159 3 is_stmt 1 view .LVU365
+ 159:Src/main.c    **** 
+ARM GAS  /tmp/cc8GRwsk.s 			page 40
+
+
+ 1098              		.loc 1 159 22 is_stmt 0 view .LVU366
+ 1099 000e 0023     		movs	r3, #0
+ 1100 0010 0193     		str	r3, [sp, #4]
+ 1101 0012 0293     		str	r3, [sp, #8]
+ 1102 0014 0393     		str	r3, [sp, #12]
+ 1103 0016 0493     		str	r3, [sp, #16]
+ 1104 0018 0593     		str	r3, [sp, #20]
+ 163:Src/main.c    **** 
+ 1105              		.loc 1 163 3 is_stmt 1 view .LVU367
+ 1106 001a 4FF40070 		mov	r0, #512
+ 1107 001e FFF7FEFF 		bl	HAL_PWREx_ControlVoltageScaling
+ 1108              	.LVL57:
+ 168:Src/main.c    ****   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ 1109              		.loc 1 168 3 view .LVU368
+ 168:Src/main.c    ****   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ 1110              		.loc 1 168 36 is_stmt 0 view .LVU369
+ 1111 0022 2123     		movs	r3, #33
+ 1112 0024 0693     		str	r3, [sp, #24]
+ 169:Src/main.c    ****   RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ 1113              		.loc 1 169 3 is_stmt 1 view .LVU370
+ 169:Src/main.c    ****   RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ 1114              		.loc 1 169 30 is_stmt 0 view .LVU371
+ 1115 0026 4FF48033 		mov	r3, #65536
+ 1116 002a 0793     		str	r3, [sp, #28]
+ 170:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ 1117              		.loc 1 170 3 is_stmt 1 view .LVU372
+ 170:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ 1118              		.loc 1 170 32 is_stmt 0 view .LVU373
+ 1119 002c 0123     		movs	r3, #1
+ 1120 002e 0C93     		str	r3, [sp, #48]
+ 171:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ 1121              		.loc 1 171 3 is_stmt 1 view .LVU374
+ 171:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ 1122              		.loc 1 171 34 is_stmt 0 view .LVU375
+ 1123 0030 0223     		movs	r3, #2
+ 1124 0032 0D93     		str	r3, [sp, #52]
+ 172:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
+ 1125              		.loc 1 172 3 is_stmt 1 view .LVU376
+ 172:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
+ 1126              		.loc 1 172 35 is_stmt 0 view .LVU377
+ 1127 0034 0322     		movs	r2, #3
+ 1128 0036 0E92     		str	r2, [sp, #56]
+ 173:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLN = 32;
+ 1129              		.loc 1 173 3 is_stmt 1 view .LVU378
+ 173:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLN = 32;
+ 1130              		.loc 1 173 30 is_stmt 0 view .LVU379
+ 1131 0038 0F93     		str	r3, [sp, #60]
+ 174:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ 1132              		.loc 1 174 3 is_stmt 1 view .LVU380
+ 174:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ 1133              		.loc 1 174 30 is_stmt 0 view .LVU381
+ 1134 003a 2022     		movs	r2, #32
+ 1135 003c 1092     		str	r2, [sp, #64]
+ 175:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
+ 1136              		.loc 1 175 3 is_stmt 1 view .LVU382
+ 175:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
+ 1137              		.loc 1 175 30 is_stmt 0 view .LVU383
+ARM GAS  /tmp/cc8GRwsk.s 			page 41
+
+
+ 1138 003e 1193     		str	r3, [sp, #68]
+ 176:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+ 1139              		.loc 1 176 3 is_stmt 1 view .LVU384
+ 176:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+ 1140              		.loc 1 176 30 is_stmt 0 view .LVU385
+ 1141 0040 0422     		movs	r2, #4
+ 1142 0042 1292     		str	r2, [sp, #72]
+ 177:Src/main.c    ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 1143              		.loc 1 177 3 is_stmt 1 view .LVU386
+ 177:Src/main.c    ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 1144              		.loc 1 177 30 is_stmt 0 view .LVU387
+ 1145 0044 1393     		str	r3, [sp, #76]
+ 178:Src/main.c    ****   {
+ 1146              		.loc 1 178 3 is_stmt 1 view .LVU388
+ 178:Src/main.c    ****   {
+ 1147              		.loc 1 178 7 is_stmt 0 view .LVU389
+ 1148 0046 06A8     		add	r0, sp, #24
+ 1149 0048 FFF7FEFF 		bl	HAL_RCC_OscConfig
+ 1150              	.LVL58:
+ 178:Src/main.c    ****   {
+ 1151              		.loc 1 178 6 view .LVU390
+ 1152 004c A0B9     		cbnz	r0, .L87
+ 185:Src/main.c    ****                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ 1153              		.loc 1 185 3 is_stmt 1 view .LVU391
+ 185:Src/main.c    ****                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ 1154              		.loc 1 185 31 is_stmt 0 view .LVU392
+ 1155 004e 0F23     		movs	r3, #15
+ 1156 0050 0193     		str	r3, [sp, #4]
+ 187:Src/main.c    ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 1157              		.loc 1 187 3 is_stmt 1 view .LVU393
+ 187:Src/main.c    ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 1158              		.loc 1 187 34 is_stmt 0 view .LVU394
+ 1159 0052 0321     		movs	r1, #3
+ 1160 0054 0291     		str	r1, [sp, #8]
+ 188:Src/main.c    ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ 1161              		.loc 1 188 3 is_stmt 1 view .LVU395
+ 188:Src/main.c    ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ 1162              		.loc 1 188 35 is_stmt 0 view .LVU396
+ 1163 0056 0023     		movs	r3, #0
+ 1164 0058 0393     		str	r3, [sp, #12]
+ 189:Src/main.c    ****   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ 1165              		.loc 1 189 3 is_stmt 1 view .LVU397
+ 189:Src/main.c    ****   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ 1166              		.loc 1 189 36 is_stmt 0 view .LVU398
+ 1167 005a 0493     		str	r3, [sp, #16]
+ 190:Src/main.c    **** 
+ 1168              		.loc 1 190 3 is_stmt 1 view .LVU399
+ 190:Src/main.c    **** 
+ 1169              		.loc 1 190 36 is_stmt 0 view .LVU400
+ 1170 005c 0593     		str	r3, [sp, #20]
+ 192:Src/main.c    ****   {
+ 1171              		.loc 1 192 3 is_stmt 1 view .LVU401
+ 192:Src/main.c    ****   {
+ 1172              		.loc 1 192 7 is_stmt 0 view .LVU402
+ 1173 005e 01A8     		add	r0, sp, #4
+ 1174 0060 FFF7FEFF 		bl	HAL_RCC_ClockConfig
+ 1175              	.LVL59:
+ARM GAS  /tmp/cc8GRwsk.s 			page 42
+
+
+ 192:Src/main.c    ****   {
+ 1176              		.loc 1 192 6 view .LVU403
+ 1177 0064 50B9     		cbnz	r0, .L88
+ 196:Src/main.c    **** }
+ 1178              		.loc 1 196 3 is_stmt 1 view .LVU404
+ 1179 0066 0022     		movs	r2, #0
+ 1180 0068 4FF08061 		mov	r1, #67108864
+ 1181 006c 0448     		ldr	r0, .L89
+ 1182 006e FFF7FEFF 		bl	HAL_RCC_MCOConfig
+ 1183              	.LVL60:
+ 197:Src/main.c    **** 
+ 1184              		.loc 1 197 1 is_stmt 0 view .LVU405
+ 1185 0072 15B0     		add	sp, sp, #84
+ 1186              	.LCFI23:
+ 1187              		.cfi_remember_state
+ 1188              		.cfi_def_cfa_offset 4
+ 1189              		@ sp needed
+ 1190 0074 5DF804FB 		ldr	pc, [sp], #4
+ 1191              	.L87:
+ 1192              	.LCFI24:
+ 1193              		.cfi_restore_state
+ 180:Src/main.c    ****   }
+ 1194              		.loc 1 180 5 is_stmt 1 view .LVU406
+ 1195 0078 FFF7FEFF 		bl	Error_Handler
+ 1196              	.LVL61:
+ 1197              	.L88:
+ 194:Src/main.c    ****   }
+ 1198              		.loc 1 194 5 view .LVU407
+ 1199 007c FFF7FEFF 		bl	Error_Handler
+ 1200              	.LVL62:
+ 1201              	.L90:
+ 1202              		.align	2
+ 1203              	.L89:
+ 1204 0080 00040600 		.word	394240
+ 1205              		.cfi_endproc
+ 1206              	.LFE334:
+ 1208              		.section	.text.main,"ax",%progbits
+ 1209              		.align	1
+ 1210              		.global	main
+ 1211              		.syntax unified
+ 1212              		.thumb
+ 1213              		.thumb_func
+ 1215              	main:
+ 1216              	.LFB333:
+  81:Src/main.c    ****   /* USER CODE BEGIN 1 */
+ 1217              		.loc 1 81 1 view -0
+ 1218              		.cfi_startproc
+ 1219              		@ Volatile: function does not return.
+ 1220              		@ args = 0, pretend = 0, frame = 0
+ 1221              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1222 0000 08B5     		push	{r3, lr}
+ 1223              	.LCFI25:
+ 1224              		.cfi_def_cfa_offset 8
+ 1225              		.cfi_offset 3, -8
+ 1226              		.cfi_offset 14, -4
+  89:Src/main.c    **** 
+ 1227              		.loc 1 89 3 view .LVU409
+ARM GAS  /tmp/cc8GRwsk.s 			page 43
+
+
+ 1228 0002 FFF7FEFF 		bl	HAL_Init
+ 1229              	.LVL63:
+  96:Src/main.c    **** 
+ 1230              		.loc 1 96 3 view .LVU410
+ 1231 0006 FFF7FEFF 		bl	SystemClock_Config
+ 1232              	.LVL64:
+ 103:Src/main.c    ****   MX_TIM2_Init();
+ 1233              		.loc 1 103 3 view .LVU411
+ 1234 000a FFF7FEFF 		bl	MX_GPIO_Init
+ 1235              	.LVL65:
+ 104:Src/main.c    ****   MX_I2C1_Init();
+ 1236              		.loc 1 104 3 view .LVU412
+ 1237 000e FFF7FEFF 		bl	MX_TIM2_Init
+ 1238              	.LVL66:
+ 105:Src/main.c    ****   MX_TIM3_Init();
+ 1239              		.loc 1 105 3 view .LVU413
+ 1240 0012 FFF7FEFF 		bl	MX_I2C1_Init
+ 1241              	.LVL67:
+ 106:Src/main.c    ****   MX_ADC1_Init();
+ 1242              		.loc 1 106 3 view .LVU414
+ 1243 0016 FFF7FEFF 		bl	MX_TIM3_Init
+ 1244              	.LVL68:
+ 107:Src/main.c    ****   MX_ADC2_Init();
+ 1245              		.loc 1 107 3 view .LVU415
+ 1246 001a FFF7FEFF 		bl	MX_ADC1_Init
+ 1247              	.LVL69:
+ 108:Src/main.c    ****   MX_USART1_UART_Init();
+ 1248              		.loc 1 108 3 view .LVU416
+ 1249 001e FFF7FEFF 		bl	MX_ADC2_Init
+ 1250              	.LVL70:
+ 109:Src/main.c    ****   MX_USB_Device_Init();
+ 1251              		.loc 1 109 3 view .LVU417
+ 1252 0022 FFF7FEFF 		bl	MX_USART1_UART_Init
+ 1253              	.LVL71:
+ 110:Src/main.c    ****   /* USER CODE BEGIN 2 */
+ 1254              		.loc 1 110 3 view .LVU418
+ 1255 0026 FFF7FEFF 		bl	MX_USB_Device_Init
+ 1256              	.LVL72:
+ 113:Src/main.c    ****    HAL_TIM_Base_Start_IT(&htim3);
+ 1257              		.loc 1 113 4 view .LVU419
+ 1258 002a 1D4C     		ldr	r4, .L94
+ 1259 002c 2046     		mov	r0, r4
+ 1260 002e FFF7FEFF 		bl	HAL_TIM_Base_Start_IT
+ 1261              	.LVL73:
+ 114:Src/main.c    **** 
+ 1262              		.loc 1 114 4 view .LVU420
+ 1263 0032 1C48     		ldr	r0, .L94+4
+ 1264 0034 FFF7FEFF 		bl	HAL_TIM_Base_Start_IT
+ 1265              	.LVL74:
+ 116:Src/main.c    ****         HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_2);
+ 1266              		.loc 1 116 2 view .LVU421
+ 1267 0038 0021     		movs	r1, #0
+ 1268 003a 2046     		mov	r0, r4
+ 1269 003c FFF7FEFF 		bl	HAL_TIM_PWM_Start
+ 1270              	.LVL75:
+ 117:Src/main.c    ****         HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_3);
+ 1271              		.loc 1 117 9 view .LVU422
+ARM GAS  /tmp/cc8GRwsk.s 			page 44
+
+
+ 1272 0040 0421     		movs	r1, #4
+ 1273 0042 2046     		mov	r0, r4
+ 1274 0044 FFF7FEFF 		bl	HAL_TIM_PWM_Start
+ 1275              	.LVL76:
+ 118:Src/main.c    ****         HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4);
+ 1276              		.loc 1 118 9 view .LVU423
+ 1277 0048 0821     		movs	r1, #8
+ 1278 004a 2046     		mov	r0, r4
+ 1279 004c FFF7FEFF 		bl	HAL_TIM_PWM_Start
+ 1280              	.LVL77:
+ 119:Src/main.c    **** 
+ 1281              		.loc 1 119 9 view .LVU424
+ 1282 0050 0C21     		movs	r1, #12
+ 1283 0052 2046     		mov	r0, r4
+ 1284 0054 FFF7FEFF 		bl	HAL_TIM_PWM_Start
+ 1285              	.LVL78:
+ 121:Src/main.c    **** 	si5351_initialize();
+ 1286              		.loc 1 121 2 view .LVU425
+ 1287 0058 0A20     		movs	r0, #10
+ 1288 005a FFF7FEFF 		bl	HAL_Delay
+ 1289              	.LVL79:
+ 122:Src/main.c    ****         HAL_Delay(10);
+ 1290              		.loc 1 122 2 view .LVU426
+ 1291 005e FFF7FEFF 		bl	si5351_initialize
+ 1292              	.LVL80:
+ 123:Src/main.c    ****         si5351_on_clk(0);
+ 1293              		.loc 1 123 9 view .LVU427
+ 1294 0062 0A20     		movs	r0, #10
+ 1295 0064 FFF7FEFF 		bl	HAL_Delay
+ 1296              	.LVL81:
+ 124:Src/main.c    ****         si5351_on_clk(1);
+ 1297              		.loc 1 124 9 view .LVU428
+ 1298 0068 0020     		movs	r0, #0
+ 1299 006a FFF7FEFF 		bl	si5351_on_clk
+ 1300              	.LVL82:
+ 125:Src/main.c    ****         si5351_set_frequency(1000000,0);
+ 1301              		.loc 1 125 9 view .LVU429
+ 1302 006e 0120     		movs	r0, #1
+ 1303 0070 FFF7FEFF 		bl	si5351_on_clk
+ 1304              	.LVL83:
+ 126:Src/main.c    ****         si5351_set_frequency(1000000,1);
+ 1305              		.loc 1 126 9 view .LVU430
+ 1306 0074 0C4C     		ldr	r4, .L94+8
+ 1307 0076 0021     		movs	r1, #0
+ 1308 0078 2046     		mov	r0, r4
+ 1309 007a FFF7FEFF 		bl	si5351_set_frequency
+ 1310              	.LVL84:
+ 127:Src/main.c    **** 
+ 1311              		.loc 1 127 9 view .LVU431
+ 1312 007e 0121     		movs	r1, #1
+ 1313 0080 2046     		mov	r0, r4
+ 1314 0082 FFF7FEFF 		bl	si5351_set_frequency
+ 1315              	.LVL85:
+ 1316              	.L92:
+ 133:Src/main.c    ****   {
+ 1317              		.loc 1 133 3 discriminator 1 view .LVU432
+ 144:Src/main.c    ****         si5351_set_frequency(1000000,0);
+ARM GAS  /tmp/cc8GRwsk.s 			page 45
+
+
+ 1318              		.loc 1 144 9 discriminator 1 view .LVU433
+ 1319 0086 0A20     		movs	r0, #10
+ 1320 0088 FFF7FEFF 		bl	HAL_Delay
+ 1321              	.LVL86:
+ 145:Src/main.c    ****         si5351_set_frequency(1000000,1);
+ 1322              		.loc 1 145 9 discriminator 1 view .LVU434
+ 1323 008c 064C     		ldr	r4, .L94+8
+ 1324 008e 0021     		movs	r1, #0
+ 1325 0090 2046     		mov	r0, r4
+ 1326 0092 FFF7FEFF 		bl	si5351_set_frequency
+ 1327              	.LVL87:
+ 146:Src/main.c    **** 
+ 1328              		.loc 1 146 9 discriminator 1 view .LVU435
+ 1329 0096 0121     		movs	r1, #1
+ 1330 0098 2046     		mov	r0, r4
+ 1331 009a FFF7FEFF 		bl	si5351_set_frequency
+ 1332              	.LVL88:
+ 133:Src/main.c    ****   {
+ 1333              		.loc 1 133 9 discriminator 1 view .LVU436
+ 1334 009e F2E7     		b	.L92
+ 1335              	.L95:
+ 1336              		.align	2
+ 1337              	.L94:
+ 1338 00a0 00000000 		.word	htim2
+ 1339 00a4 00000000 		.word	htim3
+ 1340 00a8 40420F00 		.word	1000000
+ 1341              		.cfi_endproc
+ 1342              	.LFE333:
+ 1344              		.global	huart1
+ 1345              		.section	.bss.huart1,"aw",%nobits
+ 1346              		.align	2
+ 1349              	huart1:
+ 1350 0000 00000000 		.space	144
+ 1350      00000000 
+ 1350      00000000 
+ 1350      00000000 
+ 1350      00000000 
+ 1351              		.global	htim3
+ 1352              		.section	.bss.htim3,"aw",%nobits
+ 1353              		.align	2
+ 1356              	htim3:
+ 1357 0000 00000000 		.space	76
+ 1357      00000000 
+ 1357      00000000 
+ 1357      00000000 
+ 1357      00000000 
+ 1358              		.global	htim2
+ 1359              		.section	.bss.htim2,"aw",%nobits
+ 1360              		.align	2
+ 1363              	htim2:
+ 1364 0000 00000000 		.space	76
+ 1364      00000000 
+ 1364      00000000 
+ 1364      00000000 
+ 1364      00000000 
+ 1365              		.global	hi2c1
+ 1366              		.section	.bss.hi2c1,"aw",%nobits
+ARM GAS  /tmp/cc8GRwsk.s 			page 46
+
+
+ 1367              		.align	2
+ 1370              	hi2c1:
+ 1371 0000 00000000 		.space	76
+ 1371      00000000 
+ 1371      00000000 
+ 1371      00000000 
+ 1371      00000000 
+ 1372              		.global	hadc2
+ 1373              		.section	.bss.hadc2,"aw",%nobits
+ 1374              		.align	2
+ 1377              	hadc2:
+ 1378 0000 00000000 		.space	108
+ 1378      00000000 
+ 1378      00000000 
+ 1378      00000000 
+ 1378      00000000 
+ 1379              		.global	hadc1
+ 1380              		.section	.bss.hadc1,"aw",%nobits
+ 1381              		.align	2
+ 1384              	hadc1:
+ 1385 0000 00000000 		.space	108
+ 1385      00000000 
+ 1385      00000000 
+ 1385      00000000 
+ 1385      00000000 
+ 1386              		.text
+ 1387              	.Letext0:
+ 1388              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 1389              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 1390              		.file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 1391              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 1392              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"
+ 1393              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"
+ 1394              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 1395              		.file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h"
+ 1396              		.file 11 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h"
+ 1397              		.file 12 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h"
+ 1398              		.file 13 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"
+ 1399              		.file 14 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h"
+ 1400              		.file 15 "Inc/si5351.h"
+ 1401              		.file 16 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"
+ 1402              		.file 17 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h"
+ 1403              		.file 18 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h"
+ 1404              		.file 19 "Inc/main.h"
+ 1405              		.file 20 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"
+ 1406              		.file 21 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ 1407              		.file 22 "Inc/usb_device.h"
+ 1408              		.file 23 "<built-in>"
+ARM GAS  /tmp/cc8GRwsk.s 			page 47
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 main.c
+     /tmp/cc8GRwsk.s:21     .text.MX_GPIO_Init:00000000 $t
+     /tmp/cc8GRwsk.s:26     .text.MX_GPIO_Init:00000000 MX_GPIO_Init
+     /tmp/cc8GRwsk.s:134    .text.MX_GPIO_Init:00000078 $d
+     /tmp/cc8GRwsk.s:139    .text.Error_Handler:00000000 $t
+     /tmp/cc8GRwsk.s:145    .text.Error_Handler:00000000 Error_Handler
+     /tmp/cc8GRwsk.s:177    .text.MX_TIM2_Init:00000000 $t
+     /tmp/cc8GRwsk.s:182    .text.MX_TIM2_Init:00000000 MX_TIM2_Init
+     /tmp/cc8GRwsk.s:391    .text.MX_TIM2_Init:000000ec $d
+     /tmp/cc8GRwsk.s:1363   .bss.htim2:00000000 htim2
+     /tmp/cc8GRwsk.s:396    .text.MX_I2C1_Init:00000000 $t
+     /tmp/cc8GRwsk.s:401    .text.MX_I2C1_Init:00000000 MX_I2C1_Init
+     /tmp/cc8GRwsk.s:483    .text.MX_I2C1_Init:00000048 $d
+     /tmp/cc8GRwsk.s:1370   .bss.hi2c1:00000000 hi2c1
+     /tmp/cc8GRwsk.s:490    .text.MX_TIM3_Init:00000000 $t
+     /tmp/cc8GRwsk.s:495    .text.MX_TIM3_Init:00000000 MX_TIM3_Init
+     /tmp/cc8GRwsk.s:599    .text.MX_TIM3_Init:00000064 $d
+     /tmp/cc8GRwsk.s:1356   .bss.htim3:00000000 htim3
+     /tmp/cc8GRwsk.s:605    .text.MX_ADC1_Init:00000000 $t
+     /tmp/cc8GRwsk.s:610    .text.MX_ADC1_Init:00000000 MX_ADC1_Init
+     /tmp/cc8GRwsk.s:763    .text.MX_ADC1_Init:00000090 $d
+     /tmp/cc8GRwsk.s:1384   .bss.hadc1:00000000 hadc1
+     /tmp/cc8GRwsk.s:769    .text.MX_ADC2_Init:00000000 $t
+     /tmp/cc8GRwsk.s:774    .text.MX_ADC2_Init:00000000 MX_ADC2_Init
+     /tmp/cc8GRwsk.s:954    .text.MX_ADC2_Init:000000b0 $d
+     /tmp/cc8GRwsk.s:1377   .bss.hadc2:00000000 hadc2
+     /tmp/cc8GRwsk.s:961    .text.MX_USART1_UART_Init:00000000 $t
+     /tmp/cc8GRwsk.s:966    .text.MX_USART1_UART_Init:00000000 MX_USART1_UART_Init
+     /tmp/cc8GRwsk.s:1065   .text.MX_USART1_UART_Init:00000058 $d
+     /tmp/cc8GRwsk.s:1349   .bss.huart1:00000000 huart1
+     /tmp/cc8GRwsk.s:1071   .text.SystemClock_Config:00000000 $t
+     /tmp/cc8GRwsk.s:1077   .text.SystemClock_Config:00000000 SystemClock_Config
+     /tmp/cc8GRwsk.s:1204   .text.SystemClock_Config:00000080 $d
+     /tmp/cc8GRwsk.s:1209   .text.main:00000000 $t
+     /tmp/cc8GRwsk.s:1215   .text.main:00000000 main
+     /tmp/cc8GRwsk.s:1338   .text.main:000000a0 $d
+     /tmp/cc8GRwsk.s:1346   .bss.huart1:00000000 $d
+     /tmp/cc8GRwsk.s:1353   .bss.htim3:00000000 $d
+     /tmp/cc8GRwsk.s:1360   .bss.htim2:00000000 $d
+     /tmp/cc8GRwsk.s:1367   .bss.hi2c1:00000000 $d
+     /tmp/cc8GRwsk.s:1374   .bss.hadc2:00000000 $d
+     /tmp/cc8GRwsk.s:1381   .bss.hadc1:00000000 $d
+
+UNDEFINED SYMBOLS
+HAL_GPIO_Init
+HAL_TIM_Base_Init
+HAL_TIM_ConfigClockSource
+HAL_TIM_PWM_Init
+HAL_TIMEx_MasterConfigSynchronization
+HAL_TIM_PWM_ConfigChannel
+HAL_TIM_MspPostInit
+HAL_I2C_Init
+HAL_I2CEx_ConfigAnalogFilter
+HAL_I2CEx_ConfigDigitalFilter
+memset
+HAL_ADC_Init
+ARM GAS  /tmp/cc8GRwsk.s 			page 48
+
+
+HAL_ADCEx_MultiModeConfigChannel
+HAL_ADC_ConfigChannel
+HAL_UART_Init
+HAL_UARTEx_SetTxFifoThreshold
+HAL_UARTEx_SetRxFifoThreshold
+HAL_UARTEx_DisableFifoMode
+HAL_PWREx_ControlVoltageScaling
+HAL_RCC_OscConfig
+HAL_RCC_ClockConfig
+HAL_RCC_MCOConfig
+HAL_Init
+MX_USB_Device_Init
+HAL_TIM_Base_Start_IT
+HAL_TIM_PWM_Start
+HAL_Delay
+si5351_initialize
+si5351_on_clk
+si5351_set_frequency
diff --git a/squeow_sw/build/main.o b/squeow_sw/build/main.o
new file mode 100644
index 0000000000000000000000000000000000000000..851dc6266d6aa87d68d0d34eaabdc9f95a248466
GIT binary patch
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diff --git a/squeow_sw/build/si5351.d b/squeow_sw/build/si5351.d
new file mode 100644
index 0000000..abb34b3
--- /dev/null
+++ b/squeow_sw/build/si5351.d
@@ -0,0 +1,75 @@
+build/si5351.o: Src/si5351.c Inc/main.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h Inc/si5351.h
+Inc/main.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
+Inc/si5351.h:
diff --git a/squeow_sw/build/si5351.lst b/squeow_sw/build/si5351.lst
new file mode 100644
index 0000000..2ae25a2
--- /dev/null
+++ b/squeow_sw/build/si5351.lst
@@ -0,0 +1,1331 @@
+ARM GAS  /tmp/ccx0f9ME.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"si5351.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Src/si5351.c"
+  20              		.section	.text.si5351_write8,"ax",%progbits
+  21              		.align	1
+  22              		.global	si5351_write8
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	si5351_write8:
+  28              	.LVL0:
+  29              	.LFB329:
+   1:Src/si5351.c  **** #include "main.h"
+   2:Src/si5351.c  **** #include "stm32g4xx_hal.h"
+   3:Src/si5351.c  **** #include <math.h>
+   4:Src/si5351.c  **** #include "si5351.h"
+   5:Src/si5351.c  **** 
+   6:Src/si5351.c  **** uint8_t oeb;
+   7:Src/si5351.c  **** 
+   8:Src/si5351.c  **** void si5351_write8 (uint8_t reg, uint8_t value){
+  30              		.loc 1 8 48 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 8
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		.loc 1 8 48 is_stmt 0 view .LVU1
+  35 0000 10B5     		push	{r4, lr}
+  36              	.LCFI0:
+  37              		.cfi_def_cfa_offset 8
+  38              		.cfi_offset 4, -8
+  39              		.cfi_offset 14, -4
+  40 0002 86B0     		sub	sp, sp, #24
+  41              	.LCFI1:
+  42              		.cfi_def_cfa_offset 32
+  43 0004 0446     		mov	r4, r0
+  44 0006 8DF81710 		strb	r1, [sp, #23]
+   9:Src/si5351.c  **** 	while (HAL_I2C_IsDeviceReady(&hi2c1, (uint16_t)(SI5351_ADDRESS<<1), 3, 100) != HAL_OK) { }
+  45              		.loc 1 9 2 is_stmt 1 view .LVU2
+  46              	.LVL1:
+  47              	.L2:
+  48              		.loc 1 9 91 discriminator 1 view .LVU3
+  49              		.loc 1 9 78 discriminator 1 view .LVU4
+ARM GAS  /tmp/ccx0f9ME.s 			page 2
+
+
+  50              		.loc 1 9 9 is_stmt 0 discriminator 1 view .LVU5
+  51 000a 6423     		movs	r3, #100
+  52 000c 0322     		movs	r2, #3
+  53 000e C021     		movs	r1, #192
+  54 0010 0948     		ldr	r0, .L4
+  55 0012 FFF7FEFF 		bl	HAL_I2C_IsDeviceReady
+  56              	.LVL2:
+  57              		.loc 1 9 78 discriminator 1 view .LVU6
+  58 0016 0028     		cmp	r0, #0
+  59 0018 F7D1     		bne	.L2
+  10:Src/si5351.c  **** 	HAL_I2C_Mem_Write(&hi2c1, (uint8_t)(SI5351_ADDRESS<<1), (uint8_t)reg, I2C_MEMADD_SIZE_8BIT, (uint8
+  60              		.loc 1 10 2 is_stmt 1 view .LVU7
+  61 001a 6423     		movs	r3, #100
+  62 001c 0293     		str	r3, [sp, #8]
+  63 001e 0123     		movs	r3, #1
+  64 0020 0193     		str	r3, [sp, #4]
+  65 0022 0DF11702 		add	r2, sp, #23
+  66 0026 0092     		str	r2, [sp]
+  67 0028 2246     		mov	r2, r4
+  68 002a C021     		movs	r1, #192
+  69 002c 0248     		ldr	r0, .L4
+  70 002e FFF7FEFF 		bl	HAL_I2C_Mem_Write
+  71              	.LVL3:
+  11:Src/si5351.c  **** }
+  72              		.loc 1 11 1 is_stmt 0 view .LVU8
+  73 0032 06B0     		add	sp, sp, #24
+  74              	.LCFI2:
+  75              		.cfi_def_cfa_offset 8
+  76              		@ sp needed
+  77 0034 10BD     		pop	{r4, pc}
+  78              	.L5:
+  79 0036 00BF     		.align	2
+  80              	.L4:
+  81 0038 00000000 		.word	hi2c1
+  82              		.cfi_endproc
+  83              	.LFE329:
+  85              		.section	.text.si5351_read8,"ax",%progbits
+  86              		.align	1
+  87              		.global	si5351_read8
+  88              		.syntax unified
+  89              		.thumb
+  90              		.thumb_func
+  92              	si5351_read8:
+  93              	.LVL4:
+  94              	.LFB330:
+  12:Src/si5351.c  **** 
+  13:Src/si5351.c  **** uint8_t si5351_read8(uint8_t reg, uint8_t *value){
+  95              		.loc 1 13 50 is_stmt 1 view -0
+  96              		.cfi_startproc
+  97              		@ args = 0, pretend = 0, frame = 8
+  98              		@ frame_needed = 0, uses_anonymous_args = 0
+  99              		.loc 1 13 50 is_stmt 0 view .LVU10
+ 100 0000 10B5     		push	{r4, lr}
+ 101              	.LCFI3:
+ 102              		.cfi_def_cfa_offset 8
+ 103              		.cfi_offset 4, -8
+ 104              		.cfi_offset 14, -4
+ARM GAS  /tmp/ccx0f9ME.s 			page 3
+
+
+ 105 0002 86B0     		sub	sp, sp, #24
+ 106              	.LCFI4:
+ 107              		.cfi_def_cfa_offset 32
+ 108 0004 0446     		mov	r4, r0
+ 109 0006 0591     		str	r1, [sp, #20]
+  14:Src/si5351.c  **** 	HAL_StatusTypeDef status = HAL_OK;
+ 110              		.loc 1 14 2 is_stmt 1 view .LVU11
+ 111              	.LVL5:
+  15:Src/si5351.c  **** 	while (HAL_I2C_IsDeviceReady(&hi2c1, (uint16_t)(SI5351_ADDRESS<<1), 3, 100) != HAL_OK) { }
+ 112              		.loc 1 15 2 view .LVU12
+ 113              	.L7:
+ 114              		.loc 1 15 91 discriminator 1 view .LVU13
+ 115              		.loc 1 15 78 discriminator 1 view .LVU14
+ 116              		.loc 1 15 9 is_stmt 0 discriminator 1 view .LVU15
+ 117 0008 6423     		movs	r3, #100
+ 118 000a 0322     		movs	r2, #3
+ 119 000c C021     		movs	r1, #192
+ 120 000e 0948     		ldr	r0, .L9
+ 121 0010 FFF7FEFF 		bl	HAL_I2C_IsDeviceReady
+ 122              	.LVL6:
+ 123              		.loc 1 15 78 discriminator 1 view .LVU16
+ 124 0014 0028     		cmp	r0, #0
+ 125 0016 F7D1     		bne	.L7
+  16:Src/si5351.c  **** 	status = HAL_I2C_Mem_Read(&hi2c1,							// i2c handle
+ 126              		.loc 1 16 2 is_stmt 1 view .LVU17
+ 127              		.loc 1 16 11 is_stmt 0 view .LVU18
+ 128 0018 6423     		movs	r3, #100
+ 129 001a 0293     		str	r3, [sp, #8]
+ 130 001c 0123     		movs	r3, #1
+ 131 001e 0193     		str	r3, [sp, #4]
+ 132 0020 05AA     		add	r2, sp, #20
+ 133 0022 0092     		str	r2, [sp]
+ 134 0024 2246     		mov	r2, r4
+ 135 0026 C021     		movs	r1, #192
+ 136 0028 0248     		ldr	r0, .L9
+ 137 002a FFF7FEFF 		bl	HAL_I2C_Mem_Read
+ 138              	.LVL7:
+  17:Src/si5351.c  ****     						  (uint8_t)(SI5351_ADDRESS<<1),		// i2c address, left aligned
+  18:Src/si5351.c  **** 							  (uint8_t)reg,						// register address
+  19:Src/si5351.c  **** 							  I2C_MEMADD_SIZE_8BIT,				// si5351 uses 8bit register addresses
+  20:Src/si5351.c  **** 							  (uint8_t*)(&value),				// write returned data to this variable
+  21:Src/si5351.c  **** 							  1,								// how many bytes to expect returned
+  22:Src/si5351.c  **** 							  100);								// timeout
+  23:Src/si5351.c  **** 
+  24:Src/si5351.c  ****   return status;
+ 139              		.loc 1 24 3 is_stmt 1 view .LVU19
+  25:Src/si5351.c  **** }
+ 140              		.loc 1 25 1 is_stmt 0 view .LVU20
+ 141 002e 06B0     		add	sp, sp, #24
+ 142              	.LCFI5:
+ 143              		.cfi_def_cfa_offset 8
+ 144              		@ sp needed
+ 145 0030 10BD     		pop	{r4, pc}
+ 146              	.L10:
+ 147 0032 00BF     		.align	2
+ 148              	.L9:
+ 149 0034 00000000 		.word	hi2c1
+ARM GAS  /tmp/ccx0f9ME.s 			page 4
+
+
+ 150              		.cfi_endproc
+ 151              	.LFE330:
+ 153              		.global	__aeabi_ui2d
+ 154              		.global	__aeabi_ddiv
+ 155              		.global	__aeabi_d2uiz
+ 156              		.global	__aeabi_d2iz
+ 157              		.global	__aeabi_i2d
+ 158              		.global	__aeabi_dsub
+ 159              		.global	__aeabi_dmul
+ 160              		.global	__aeabi_dadd
+ 161              		.section	.text.CalcRegisters,"ax",%progbits
+ 162              		.align	1
+ 163              		.global	CalcRegisters
+ 164              		.syntax unified
+ 165              		.thumb
+ 166              		.thumb_func
+ 168              	CalcRegisters:
+ 169              	.LVL8:
+ 170              	.LFB331:
+  26:Src/si5351.c  **** 
+  27:Src/si5351.c  **** 
+  28:Src/si5351.c  **** void CalcRegisters(uint32_t fout, uint8_t *regs){
+ 171              		.loc 1 28 49 is_stmt 1 view -0
+ 172              		.cfi_startproc
+ 173              		@ args = 0, pretend = 0, frame = 0
+ 174              		@ frame_needed = 0, uses_anonymous_args = 0
+ 175              		.loc 1 28 49 is_stmt 0 view .LVU22
+ 176 0000 2DE9F84F 		push	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 177              	.LCFI6:
+ 178              		.cfi_def_cfa_offset 40
+ 179              		.cfi_offset 3, -40
+ 180              		.cfi_offset 4, -36
+ 181              		.cfi_offset 5, -32
+ 182              		.cfi_offset 6, -28
+ 183              		.cfi_offset 7, -24
+ 184              		.cfi_offset 8, -20
+ 185              		.cfi_offset 9, -16
+ 186              		.cfi_offset 10, -12
+ 187              		.cfi_offset 11, -8
+ 188              		.cfi_offset 14, -4
+ 189 0004 8046     		mov	r8, r0
+ 190 0006 0C46     		mov	r4, r1
+  29:Src/si5351.c  **** //    uint32_t fref = SI5351_CRYSTAL_FREQ;                        // The reference frequency
+  30:Src/si5351.c  ****  
+  31:Src/si5351.c  ****     // Calc Output Multisynth Divider and R with e = 0 and f = 1 => msx_p2 = 0 and msx_p3 = 1
+  32:Src/si5351.c  ****     uint32_t d = 4;
+ 191              		.loc 1 32 5 is_stmt 1 view .LVU23
+ 192              	.LVL9:
+  33:Src/si5351.c  ****     uint32_t msx_p1 = 0;                         // If fout > 150 MHz then MSx_P1 = 0 and MSx_DIVBY
+ 193              		.loc 1 33 5 view .LVU24
+  34:Src/si5351.c  ****     int msx_divby4 = 0;
+ 194              		.loc 1 34 5 view .LVU25
+  35:Src/si5351.c  ****     int rx_div = 0;
+ 195              		.loc 1 35 5 view .LVU26
+  36:Src/si5351.c  ****     int r = 1;
+ 196              		.loc 1 36 5 view .LVU27
+  37:Src/si5351.c  ****  
+ARM GAS  /tmp/ccx0f9ME.s 			page 5
+
+
+  38:Src/si5351.c  ****     if (fout > 150e6)
+ 197              		.loc 1 38 5 view .LVU28
+ 198              		.loc 1 38 8 is_stmt 0 view .LVU29
+ 199 0008 674B     		ldr	r3, .L29+24
+ 200 000a 9842     		cmp	r0, r3
+ 201 000c 49D8     		bhi	.L20
+  39:Src/si5351.c  ****         msx_divby4 = 0x0C;                       // MSx_DIVBY4[1:0] = 0b11, see datasheet 4.1.3
+  40:Src/si5351.c  ****     else if (fout < 292969UL)                    // If fout < 500 kHz then use R divider, see datas
+ 202              		.loc 1 40 10 is_stmt 1 view .LVU30
+ 203              		.loc 1 40 13 is_stmt 0 view .LVU31
+ 204 000e 674B     		ldr	r3, .L29+28
+ 205 0010 9842     		cmp	r0, r3
+ 206 0012 38D9     		bls	.L21
+  41:Src/si5351.c  ****     {
+  42:Src/si5351.c  ****         int rd = 0;
+  43:Src/si5351.c  ****         while ((r < 128) && (r * fout < 292969UL))
+  44:Src/si5351.c  ****         {
+  45:Src/si5351.c  ****             r <<= 1;
+  46:Src/si5351.c  ****             rd++;
+  47:Src/si5351.c  ****         }
+  48:Src/si5351.c  ****         rx_div = rd << 4;
+  49:Src/si5351.c  **** 
+  50:Src/si5351.c  ****         d = 600e6 / (r * fout);                  // Use lowest VCO frequency but handle d minimum
+  51:Src/si5351.c  ****         if (d % 2)                               // Make d even to reduce spurious and phase noise/
+  52:Src/si5351.c  ****             d++;
+  53:Src/si5351.c  **** 
+  54:Src/si5351.c  ****         if (d * r * fout < 600e6)                // VCO frequency to low check and maintain an even
+  55:Src/si5351.c  ****             d += 2;
+  56:Src/si5351.c  ****     }
+  57:Src/si5351.c  ****     else                                         // 292968 Hz <= fout <= 150 MHz
+  58:Src/si5351.c  ****     {
+  59:Src/si5351.c  ****         d = 600e6 / fout;                        // Use lowest VCO frequency but handle d minimum
+ 207              		.loc 1 59 9 is_stmt 1 view .LVU32
+ 208              		.loc 1 59 19 is_stmt 0 view .LVU33
+ 209 0014 FFF7FEFF 		bl	__aeabi_ui2d
+ 210              	.LVL10:
+ 211              		.loc 1 59 19 view .LVU34
+ 212 0018 0246     		mov	r2, r0
+ 213 001a 0B46     		mov	r3, r1
+ 214 001c 5CA1     		adr	r1, .L29
+ 215 001e D1E90001 		ldrd	r0, [r1]
+ 216 0022 FFF7FEFF 		bl	__aeabi_ddiv
+ 217              	.LVL11:
+ 218              		.loc 1 59 11 view .LVU35
+ 219 0026 FFF7FEFF 		bl	__aeabi_d2uiz
+ 220              	.LVL12:
+  60:Src/si5351.c  ****         if (d < 6)
+ 221              		.loc 1 60 9 is_stmt 1 view .LVU36
+ 222              		.loc 1 60 12 is_stmt 0 view .LVU37
+ 223 002a 0528     		cmp	r0, #5
+ 224 002c 2ED9     		bls	.L23
+  61:Src/si5351.c  ****             d = 6;
+  62:Src/si5351.c  ****         else if (d % 2)                          // Make d even to reduce phase noise/jitter, see d
+ 225              		.loc 1 62 14 is_stmt 1 view .LVU38
+ 226              		.loc 1 62 17 is_stmt 0 view .LVU39
+ 227 002e 10F0010F 		tst	r0, #1
+ 228 0032 2CD0     		beq	.L18
+ARM GAS  /tmp/ccx0f9ME.s 			page 6
+
+
+  63:Src/si5351.c  ****            d++;
+ 229              		.loc 1 63 12 is_stmt 1 view .LVU40
+ 230              		.loc 1 63 13 is_stmt 0 view .LVU41
+ 231 0034 0130     		adds	r0, r0, #1
+ 232              	.LVL13:
+ 233              		.loc 1 63 13 view .LVU42
+ 234 0036 2AE0     		b	.L18
+ 235              	.LVL14:
+ 236              	.L16:
+ 237              	.LBB2:
+  45:Src/si5351.c  ****             rd++;
+ 238              		.loc 1 45 13 is_stmt 1 view .LVU43
+  45:Src/si5351.c  ****             rd++;
+ 239              		.loc 1 45 15 is_stmt 0 view .LVU44
+ 240 0038 7600     		lsls	r6, r6, #1
+ 241              	.LVL15:
+  46:Src/si5351.c  ****         }
+ 242              		.loc 1 46 13 is_stmt 1 view .LVU45
+  46:Src/si5351.c  ****         }
+ 243              		.loc 1 46 15 is_stmt 0 view .LVU46
+ 244 003a 0135     		adds	r5, r5, #1
+ 245              	.LVL16:
+ 246              	.L13:
+  43:Src/si5351.c  ****         {
+ 247              		.loc 1 43 26 is_stmt 1 view .LVU47
+ 248 003c 7F2E     		cmp	r6, #127
+ 249 003e 04DC     		bgt	.L15
+  43:Src/si5351.c  ****         {
+ 250              		.loc 1 43 32 is_stmt 0 discriminator 1 view .LVU48
+ 251 0040 08FB06F2 		mul	r2, r8, r6
+  43:Src/si5351.c  ****         {
+ 252              		.loc 1 43 26 discriminator 1 view .LVU49
+ 253 0044 594B     		ldr	r3, .L29+28
+ 254 0046 9A42     		cmp	r2, r3
+ 255 0048 F6D9     		bls	.L16
+ 256              	.L15:
+  48:Src/si5351.c  **** 
+ 257              		.loc 1 48 9 is_stmt 1 view .LVU50
+  48:Src/si5351.c  **** 
+ 258              		.loc 1 48 16 is_stmt 0 view .LVU51
+ 259 004a 2D01     		lsls	r5, r5, #4
+ 260              	.LVL17:
+  50:Src/si5351.c  ****         if (d % 2)                               // Make d even to reduce spurious and phase noise/
+ 261              		.loc 1 50 9 is_stmt 1 view .LVU52
+  50:Src/si5351.c  ****         if (d % 2)                               // Make d even to reduce spurious and phase noise/
+ 262              		.loc 1 50 24 is_stmt 0 view .LVU53
+ 263 004c 3746     		mov	r7, r6
+  50:Src/si5351.c  ****         if (d % 2)                               // Make d even to reduce spurious and phase noise/
+ 264              		.loc 1 50 19 view .LVU54
+ 265 004e 08FB06F0 		mul	r0, r8, r6
+ 266              	.LVL18:
+  50:Src/si5351.c  ****         if (d % 2)                               // Make d even to reduce spurious and phase noise/
+ 267              		.loc 1 50 19 view .LVU55
+ 268 0052 FFF7FEFF 		bl	__aeabi_ui2d
+ 269              	.LVL19:
+  50:Src/si5351.c  ****         if (d % 2)                               // Make d even to reduce spurious and phase noise/
+ 270              		.loc 1 50 19 view .LVU56
+ARM GAS  /tmp/ccx0f9ME.s 			page 7
+
+
+ 271 0056 0246     		mov	r2, r0
+ 272 0058 0B46     		mov	r3, r1
+ 273 005a 4DA1     		adr	r1, .L29
+ 274 005c D1E90001 		ldrd	r0, [r1]
+ 275 0060 FFF7FEFF 		bl	__aeabi_ddiv
+ 276              	.LVL20:
+  50:Src/si5351.c  ****         if (d % 2)                               // Make d even to reduce spurious and phase noise/
+ 277              		.loc 1 50 11 view .LVU57
+ 278 0064 FFF7FEFF 		bl	__aeabi_d2uiz
+ 279              	.LVL21:
+  51:Src/si5351.c  ****             d++;
+ 280              		.loc 1 51 9 is_stmt 1 view .LVU58
+  51:Src/si5351.c  ****             d++;
+ 281              		.loc 1 51 12 is_stmt 0 view .LVU59
+ 282 0068 10F0010F 		tst	r0, #1
+ 283 006c 00D0     		beq	.L17
+  52:Src/si5351.c  **** 
+ 284              		.loc 1 52 13 is_stmt 1 view .LVU60
+  52:Src/si5351.c  **** 
+ 285              		.loc 1 52 14 is_stmt 0 view .LVU61
+ 286 006e 0130     		adds	r0, r0, #1
+ 287              	.LVL22:
+ 288              	.L17:
+  54:Src/si5351.c  ****             d += 2;
+ 289              		.loc 1 54 9 is_stmt 1 view .LVU62
+  54:Src/si5351.c  ****             d += 2;
+ 290              		.loc 1 54 15 is_stmt 0 view .LVU63
+ 291 0070 00FB07F7 		mul	r7, r0, r7
+  54:Src/si5351.c  ****             d += 2;
+ 292              		.loc 1 54 19 view .LVU64
+ 293 0074 08FB07F7 		mul	r7, r8, r7
+  54:Src/si5351.c  ****             d += 2;
+ 294              		.loc 1 54 12 view .LVU65
+ 295 0078 4D4B     		ldr	r3, .L29+32
+ 296 007a 9F42     		cmp	r7, r3
+ 297 007c 4ED8     		bhi	.L22
+  55:Src/si5351.c  ****     }
+ 298              		.loc 1 55 13 is_stmt 1 view .LVU66
+  55:Src/si5351.c  ****     }
+ 299              		.loc 1 55 15 is_stmt 0 view .LVU67
+ 300 007e 0230     		adds	r0, r0, #2
+ 301              	.LVL23:
+  55:Src/si5351.c  ****     }
+ 302              		.loc 1 55 15 view .LVU68
+ 303              	.LBE2:
+  34:Src/si5351.c  ****     int rx_div = 0;
+ 304              		.loc 1 34 9 view .LVU69
+ 305 0080 4FF0000A 		mov	r10, #0
+ 306 0084 12E0     		b	.L12
+ 307              	.LVL24:
+ 308              	.L21:
+ 309              	.LBB3:
+  42:Src/si5351.c  ****         while ((r < 128) && (r * fout < 292969UL))
+ 310              		.loc 1 42 13 view .LVU70
+ 311 0086 0025     		movs	r5, #0
+ 312              	.LBE3:
+  36:Src/si5351.c  ****  
+ARM GAS  /tmp/ccx0f9ME.s 			page 8
+
+
+ 313              		.loc 1 36 9 view .LVU71
+ 314 0088 0126     		movs	r6, #1
+ 315 008a D7E7     		b	.L13
+ 316              	.LVL25:
+ 317              	.L23:
+  61:Src/si5351.c  ****         else if (d % 2)                          // Make d even to reduce phase noise/jitter, see d
+ 318              		.loc 1 61 15 view .LVU72
+ 319 008c 0620     		movs	r0, #6
+ 320              	.LVL26:
+ 321              	.L18:
+  64:Src/si5351.c  **** 
+  65:Src/si5351.c  ****         if (d * fout < 600e6)                    // VCO frequency to low check and maintain an even
+ 322              		.loc 1 65 9 is_stmt 1 view .LVU73
+ 323              		.loc 1 65 15 is_stmt 0 view .LVU74
+ 324 008e 08FB00F2 		mul	r2, r8, r0
+ 325              		.loc 1 65 12 view .LVU75
+ 326 0092 474B     		ldr	r3, .L29+32
+ 327 0094 9A42     		cmp	r2, r3
+ 328 0096 44D8     		bhi	.L24
+  66:Src/si5351.c  ****             d += 2;
+ 329              		.loc 1 66 13 is_stmt 1 view .LVU76
+ 330              		.loc 1 66 15 is_stmt 0 view .LVU77
+ 331 0098 0230     		adds	r0, r0, #2
+ 332              	.LVL27:
+  36:Src/si5351.c  ****  
+ 333              		.loc 1 36 9 view .LVU78
+ 334 009a 0126     		movs	r6, #1
+  35:Src/si5351.c  ****     int r = 1;
+ 335              		.loc 1 35 9 view .LVU79
+ 336 009c 0025     		movs	r5, #0
+  34:Src/si5351.c  ****     int rx_div = 0;
+ 337              		.loc 1 34 9 view .LVU80
+ 338 009e AA46     		mov	r10, r5
+ 339 00a0 04E0     		b	.L12
+ 340              	.LVL28:
+ 341              	.L20:
+  36:Src/si5351.c  ****  
+ 342              		.loc 1 36 9 view .LVU81
+ 343 00a2 0126     		movs	r6, #1
+  35:Src/si5351.c  ****     int r = 1;
+ 344              		.loc 1 35 9 view .LVU82
+ 345 00a4 0025     		movs	r5, #0
+  39:Src/si5351.c  ****     else if (fout < 292969UL)                    // If fout < 500 kHz then use R divider, see datas
+ 346              		.loc 1 39 20 view .LVU83
+ 347 00a6 4FF00C0A 		mov	r10, #12
+  32:Src/si5351.c  ****     uint32_t msx_p1 = 0;                         // If fout > 150 MHz then MSx_P1 = 0 and MSx_DIVBY
+ 348              		.loc 1 32 14 view .LVU84
+ 349 00aa 0420     		movs	r0, #4
+ 350              	.LVL29:
+ 351              	.L12:
+  67:Src/si5351.c  ****     }
+  68:Src/si5351.c  ****     msx_p1 = 128 * d - 512;
+ 352              		.loc 1 68 5 is_stmt 1 view .LVU85
+ 353              		.loc 1 68 22 is_stmt 0 view .LVU86
+ 354 00ac 00F10077 		add	r7, r0, #33554432
+ 355 00b0 043F     		subs	r7, r7, #4
+ 356              		.loc 1 68 12 view .LVU87
+ARM GAS  /tmp/ccx0f9ME.s 			page 9
+
+
+ 357 00b2 FF01     		lsls	r7, r7, #7
+ 358              	.LVL30:
+  69:Src/si5351.c  **** 
+  70:Src/si5351.c  ****     uint32_t fvco = (uint32_t) d * r * fout;
+ 359              		.loc 1 70 5 is_stmt 1 view .LVU88
+ 360              		.loc 1 70 34 is_stmt 0 view .LVU89
+ 361 00b4 06FB00F0 		mul	r0, r6, r0
+ 362              	.LVL31:
+  71:Src/si5351.c  **** 
+  72:Src/si5351.c  ****     // Calc Feedback Multisynth Divider
+  73:Src/si5351.c  ****     double fmd = (double)fvco / SI5351_CRYSTAL_FREQ;            // The FMD value has been found
+ 363              		.loc 1 73 5 is_stmt 1 view .LVU90
+ 364              		.loc 1 73 18 is_stmt 0 view .LVU91
+ 365 00b8 08FB00F0 		mul	r0, r8, r0
+ 366              	.LVL32:
+ 367              		.loc 1 73 18 view .LVU92
+ 368 00bc FFF7FEFF 		bl	__aeabi_ui2d
+ 369              	.LVL33:
+ 370              		.loc 1 73 12 view .LVU93
+ 371 00c0 35A3     		adr	r3, .L29+8
+ 372 00c2 D3E90023 		ldrd	r2, [r3]
+ 373 00c6 FFF7FEFF 		bl	__aeabi_ddiv
+ 374              	.LVL34:
+ 375 00ca 8046     		mov	r8, r0
+ 376              	.LVL35:
+ 377              		.loc 1 73 12 view .LVU94
+ 378 00cc 8946     		mov	r9, r1
+ 379              	.LVL36:
+  74:Src/si5351.c  ****     int a = fmd;                                 // a is the integer part of the FMD value
+ 380              		.loc 1 74 5 is_stmt 1 view .LVU95
+ 381              		.loc 1 74 9 is_stmt 0 view .LVU96
+ 382 00ce FFF7FEFF 		bl	__aeabi_d2iz
+ 383              	.LVL37:
+ 384 00d2 0646     		mov	r6, r0
+ 385              	.LVL38:
+  75:Src/si5351.c  ****  
+  76:Src/si5351.c  ****     double b_c = (double)fmd - a;                // Get b/c
+ 386              		.loc 1 76 5 is_stmt 1 view .LVU97
+ 387              		.loc 1 76 30 is_stmt 0 view .LVU98
+ 388 00d4 FFF7FEFF 		bl	__aeabi_i2d
+ 389              	.LVL39:
+ 390              		.loc 1 76 30 view .LVU99
+ 391 00d8 0246     		mov	r2, r0
+ 392 00da 0B46     		mov	r3, r1
+ 393              		.loc 1 76 12 view .LVU100
+ 394 00dc 4046     		mov	r0, r8
+ 395 00de 4946     		mov	r1, r9
+ 396 00e0 FFF7FEFF 		bl	__aeabi_dsub
+ 397              	.LVL40:
+ 398 00e4 8046     		mov	r8, r0
+ 399              	.LVL41:
+ 400              		.loc 1 76 12 view .LVU101
+ 401 00e6 8946     		mov	r9, r1
+ 402              	.LVL42:
+  77:Src/si5351.c  ****     uint32_t c = 1048575UL;
+ 403              		.loc 1 77 5 is_stmt 1 view .LVU102
+  78:Src/si5351.c  ****     uint32_t b = (double)b_c * c;
+ARM GAS  /tmp/ccx0f9ME.s 			page 10
+
+
+ 404              		.loc 1 78 5 view .LVU103
+ 405              		.loc 1 78 30 is_stmt 0 view .LVU104
+ 406 00e8 2DA3     		adr	r3, .L29+16
+ 407 00ea D3E90023 		ldrd	r2, [r3]
+ 408 00ee FFF7FEFF 		bl	__aeabi_dmul
+ 409              	.LVL43:
+ 410              		.loc 1 78 14 view .LVU105
+ 411 00f2 FFF7FEFF 		bl	__aeabi_d2uiz
+ 412              	.LVL44:
+  79:Src/si5351.c  ****     if (b > 0)
+ 413              		.loc 1 79 5 is_stmt 1 view .LVU106
+ 414              		.loc 1 79 8 is_stmt 0 view .LVU107
+ 415 00f6 8346     		mov	fp, r0
+ 416 00f8 B8B1     		cbz	r0, .L25
+  80:Src/si5351.c  ****     {
+  81:Src/si5351.c  ****         c = (double)b / b_c + 0.5;               // Improves frequency precision in some cases
+ 417              		.loc 1 81 9 is_stmt 1 view .LVU108
+ 418              		.loc 1 81 13 is_stmt 0 view .LVU109
+ 419 00fa FFF7FEFF 		bl	__aeabi_ui2d
+ 420              	.LVL45:
+ 421              		.loc 1 81 23 view .LVU110
+ 422 00fe 4246     		mov	r2, r8
+ 423 0100 4B46     		mov	r3, r9
+ 424 0102 FFF7FEFF 		bl	__aeabi_ddiv
+ 425              	.LVL46:
+ 426              		.loc 1 81 29 view .LVU111
+ 427 0106 0022     		movs	r2, #0
+ 428 0108 2A4B     		ldr	r3, .L29+36
+ 429 010a FFF7FEFF 		bl	__aeabi_dadd
+ 430              	.LVL47:
+ 431              		.loc 1 81 11 view .LVU112
+ 432 010e FFF7FEFF 		bl	__aeabi_d2uiz
+ 433              	.LVL48:
+  82:Src/si5351.c  ****         if (c > 1048575UL)
+ 434              		.loc 1 82 9 is_stmt 1 view .LVU113
+ 435              		.loc 1 82 12 is_stmt 0 view .LVU114
+ 436 0112 B0F5801F 		cmp	r0, #1048576
+ 437 0116 09D3     		bcc	.L19
+  83:Src/si5351.c  ****             c = 1048575UL;
+ 438              		.loc 1 83 15 view .LVU115
+ 439 0118 2748     		ldr	r0, .L29+40
+ 440              	.LVL49:
+ 441              		.loc 1 83 15 view .LVU116
+ 442 011a 07E0     		b	.L19
+ 443              	.LVL50:
+ 444              	.L22:
+  34:Src/si5351.c  ****     int rx_div = 0;
+ 445              		.loc 1 34 9 view .LVU117
+ 446 011c 4FF0000A 		mov	r10, #0
+ 447 0120 C4E7     		b	.L12
+ 448              	.LVL51:
+ 449              	.L24:
+  36:Src/si5351.c  ****  
+ 450              		.loc 1 36 9 view .LVU118
+ 451 0122 0126     		movs	r6, #1
+  35:Src/si5351.c  ****     int r = 1;
+ 452              		.loc 1 35 9 view .LVU119
+ARM GAS  /tmp/ccx0f9ME.s 			page 11
+
+
+ 453 0124 0025     		movs	r5, #0
+  34:Src/si5351.c  ****     int rx_div = 0;
+ 454              		.loc 1 34 9 view .LVU120
+ 455 0126 AA46     		mov	r10, r5
+ 456 0128 C0E7     		b	.L12
+ 457              	.LVL52:
+ 458              	.L25:
+  77:Src/si5351.c  ****     uint32_t b = (double)b_c * c;
+ 459              		.loc 1 77 14 view .LVU121
+ 460 012a 2348     		ldr	r0, .L29+40
+ 461              	.LVL53:
+ 462              	.L19:
+  84:Src/si5351.c  ****     }
+  85:Src/si5351.c  **** 
+  86:Src/si5351.c  ****     uint32_t msnx_p1 = 128 * a + 128 * b / c - 512;   // See datasheet 3.2
+ 463              		.loc 1 86 5 is_stmt 1 view .LVU122
+ 464              		.loc 1 86 38 is_stmt 0 view .LVU123
+ 465 012c 4FEACB1B 		lsl	fp, fp, #7
+ 466              	.LVL54:
+ 467              		.loc 1 86 42 view .LVU124
+ 468 0130 BBFBF0F3 		udiv	r3, fp, r0
+ 469              		.loc 1 86 32 view .LVU125
+ 470 0134 03EBC616 		add	r6, r3, r6, lsl #7
+ 471              	.LVL55:
+ 472              		.loc 1 86 14 view .LVU126
+ 473 0138 A6F50076 		sub	r6, r6, #512
+ 474              	.LVL56:
+  87:Src/si5351.c  ****     uint32_t msnx_p2 = 128 * b - c * (128 * b / c);
+ 475              		.loc 1 87 5 is_stmt 1 view .LVU127
+ 476              		.loc 1 87 14 is_stmt 0 view .LVU128
+ 477 013c 00FB13BB 		mls	fp, r0, r3, fp
+ 478              	.LVL57:
+  88:Src/si5351.c  ****     uint32_t msnx_p3 = c;
+ 479              		.loc 1 88 5 is_stmt 1 view .LVU129
+  89:Src/si5351.c  ****  
+  90:Src/si5351.c  ****     // Feedback Multisynth Divider registers
+  91:Src/si5351.c  ****     regs[0] = (msnx_p3 >> 8) & 0xFF;
+ 480              		.loc 1 91 5 view .LVU130
+ 481              		.loc 1 91 24 is_stmt 0 view .LVU131
+ 482 0140 030A     		lsrs	r3, r0, #8
+ 483              		.loc 1 91 13 view .LVU132
+ 484 0142 2370     		strb	r3, [r4]
+  92:Src/si5351.c  ****     regs[1] = msnx_p3 & 0xFF;
+ 485              		.loc 1 92 5 is_stmt 1 view .LVU133
+ 486              		.loc 1 92 13 is_stmt 0 view .LVU134
+ 487 0144 6070     		strb	r0, [r4, #1]
+  93:Src/si5351.c  ****     regs[2] = (msnx_p1 >> 16) & 0x03;
+ 488              		.loc 1 93 5 is_stmt 1 view .LVU135
+ 489              		.loc 1 93 31 is_stmt 0 view .LVU136
+ 490 0146 C6F30143 		ubfx	r3, r6, #16, #2
+ 491              		.loc 1 93 13 view .LVU137
+ 492 014a A370     		strb	r3, [r4, #2]
+  94:Src/si5351.c  ****     regs[3] = (msnx_p1 >> 8) & 0xFF;
+ 493              		.loc 1 94 5 is_stmt 1 view .LVU138
+ 494              		.loc 1 94 24 is_stmt 0 view .LVU139
+ 495 014c 330A     		lsrs	r3, r6, #8
+ 496              		.loc 1 94 13 view .LVU140
+ARM GAS  /tmp/ccx0f9ME.s 			page 12
+
+
+ 497 014e E370     		strb	r3, [r4, #3]
+  95:Src/si5351.c  ****     regs[4] = msnx_p1 & 0xFF;
+ 498              		.loc 1 95 5 is_stmt 1 view .LVU141
+ 499              		.loc 1 95 13 is_stmt 0 view .LVU142
+ 500 0150 2671     		strb	r6, [r4, #4]
+  96:Src/si5351.c  ****     regs[5] = ((msnx_p3 >> 12) & 0xF0) + ((msnx_p2 >> 16) & 0x0F);
+ 501              		.loc 1 96 5 is_stmt 1 view .LVU143
+ 502              		.loc 1 96 25 is_stmt 0 view .LVU144
+ 503 0152 000B     		lsrs	r0, r0, #12
+ 504              	.LVL58:
+ 505              		.loc 1 96 32 view .LVU145
+ 506 0154 00F0F000 		and	r0, r0, #240
+ 507              		.loc 1 96 59 view .LVU146
+ 508 0158 CBF30343 		ubfx	r3, fp, #16, #4
+ 509              		.loc 1 96 40 view .LVU147
+ 510 015c 1843     		orrs	r0, r0, r3
+ 511              		.loc 1 96 13 view .LVU148
+ 512 015e 6071     		strb	r0, [r4, #5]
+  97:Src/si5351.c  ****     regs[6] = (msnx_p2 >> 8) & 0xFF;
+ 513              		.loc 1 97 5 is_stmt 1 view .LVU149
+ 514              		.loc 1 97 24 is_stmt 0 view .LVU150
+ 515 0160 4FEA1B23 		lsr	r3, fp, #8
+ 516              		.loc 1 97 13 view .LVU151
+ 517 0164 A371     		strb	r3, [r4, #6]
+  98:Src/si5351.c  ****     regs[7] = msnx_p2 & 0xFF;
+ 518              		.loc 1 98 5 is_stmt 1 view .LVU152
+ 519              		.loc 1 98 13 is_stmt 0 view .LVU153
+ 520 0166 84F807B0 		strb	fp, [r4, #7]
+  99:Src/si5351.c  ****  
+ 100:Src/si5351.c  ****     // Output Multisynth Divider registers 
+ 101:Src/si5351.c  ****     regs[8] = 0;                                  // (msx_p3 >> 8) & 0xFF
+ 521              		.loc 1 101 5 is_stmt 1 view .LVU154
+ 522              		.loc 1 101 13 is_stmt 0 view .LVU155
+ 523 016a 0023     		movs	r3, #0
+ 524 016c 2372     		strb	r3, [r4, #8]
+ 102:Src/si5351.c  ****     regs[9] = 1;                                  // msx_p3 & 0xFF
+ 525              		.loc 1 102 5 is_stmt 1 view .LVU156
+ 526              		.loc 1 102 13 is_stmt 0 view .LVU157
+ 527 016e 0122     		movs	r2, #1
+ 528 0170 6272     		strb	r2, [r4, #9]
+ 103:Src/si5351.c  ****     regs[10] = rx_div + msx_divby4 + ((msx_p1 >> 16) & 0x03);
+ 529              		.loc 1 103 5 is_stmt 1 view .LVU158
+ 530              		.loc 1 103 23 is_stmt 0 view .LVU159
+ 531 0172 5544     		add	r5, r5, r10
+ 532              	.LVL59:
+ 533              		.loc 1 103 23 view .LVU160
+ 534 0174 EDB2     		uxtb	r5, r5
+ 535              		.loc 1 103 54 view .LVU161
+ 536 0176 C7F30142 		ubfx	r2, r7, #16, #2
+ 537              		.loc 1 103 36 view .LVU162
+ 538 017a 1544     		add	r5, r5, r2
+ 539              		.loc 1 103 14 view .LVU163
+ 540 017c A572     		strb	r5, [r4, #10]
+ 104:Src/si5351.c  ****     regs[11] = (msx_p1 >> 8) & 0xFF;
+ 541              		.loc 1 104 5 is_stmt 1 view .LVU164
+ 542              		.loc 1 104 24 is_stmt 0 view .LVU165
+ 543 017e 3A0A     		lsrs	r2, r7, #8
+ARM GAS  /tmp/ccx0f9ME.s 			page 13
+
+
+ 544              		.loc 1 104 14 view .LVU166
+ 545 0180 E272     		strb	r2, [r4, #11]
+ 105:Src/si5351.c  ****     regs[12] = msx_p1 & 0xFF;
+ 546              		.loc 1 105 5 is_stmt 1 view .LVU167
+ 547              		.loc 1 105 14 is_stmt 0 view .LVU168
+ 548 0182 2773     		strb	r7, [r4, #12]
+ 106:Src/si5351.c  ****     regs[13] = 0;                                 // ((msx_p3 >> 12) & 0xF0) + (msx_p2 >> 16) & 0x0
+ 549              		.loc 1 106 5 is_stmt 1 view .LVU169
+ 550              		.loc 1 106 14 is_stmt 0 view .LVU170
+ 551 0184 6373     		strb	r3, [r4, #13]
+ 107:Src/si5351.c  ****     regs[14] = 0;                                 // (msx_p2 >> 8) & 0xFF
+ 552              		.loc 1 107 5 is_stmt 1 view .LVU171
+ 553              		.loc 1 107 14 is_stmt 0 view .LVU172
+ 554 0186 A373     		strb	r3, [r4, #14]
+ 108:Src/si5351.c  ****     regs[15] = 0;                                 // msx_p2 & 0xFF
+ 555              		.loc 1 108 5 is_stmt 1 view .LVU173
+ 556              		.loc 1 108 14 is_stmt 0 view .LVU174
+ 557 0188 E373     		strb	r3, [r4, #15]
+ 109:Src/si5351.c  **** 
+ 110:Src/si5351.c  **** //	HAL_I2C_Master_Transmit(&hi2c2, Si5351_ConfigStruct->HW_I2C_Address, reg_data, sizeof(reg_data),
+ 111:Src/si5351.c  ****     return;
+ 558              		.loc 1 111 5 is_stmt 1 view .LVU175
+ 112:Src/si5351.c  **** }
+ 559              		.loc 1 112 1 is_stmt 0 view .LVU176
+ 560 018a BDE8F88F 		pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 561              	.LVL60:
+ 562              	.L30:
+ 563              		.loc 1 112 1 view .LVU177
+ 564 018e 00BF     		.align	3
+ 565              	.L29:
+ 566 0190 00000000 		.word	0
+ 567 0194 A3E1C141 		.word	1103225251
+ 568 0198 00000000 		.word	0
+ 569 019c 60E37641 		.word	1098310496
+ 570 01a0 00000000 		.word	0
+ 571 01a4 FEFF2F41 		.word	1093664766
+ 572 01a8 80D1F008 		.word	150000000
+ 573 01ac 68780400 		.word	292968
+ 574 01b0 FF45C323 		.word	599999999
+ 575 01b4 0000E03F 		.word	1071644672
+ 576 01b8 FFFF0F00 		.word	1048575
+ 577              		.cfi_endproc
+ 578              	.LFE331:
+ 580              		.section	.text.si5351_initialize,"ax",%progbits
+ 581              		.align	1
+ 582              		.global	si5351_initialize
+ 583              		.syntax unified
+ 584              		.thumb
+ 585              		.thumb_func
+ 587              	si5351_initialize:
+ 588              	.LFB332:
+ 113:Src/si5351.c  **** 
+ 114:Src/si5351.c  **** void si5351_initialize(){
+ 589              		.loc 1 114 25 is_stmt 1 view -0
+ 590              		.cfi_startproc
+ 591              		@ args = 0, pretend = 0, frame = 0
+ 592              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccx0f9ME.s 			page 14
+
+
+ 593 0000 10B5     		push	{r4, lr}
+ 594              	.LCFI7:
+ 595              		.cfi_def_cfa_offset 8
+ 596              		.cfi_offset 4, -8
+ 597              		.cfi_offset 14, -4
+ 598 0002 0024     		movs	r4, #0
+ 115:Src/si5351.c  **** 	uint8_t dummy;
+ 599              		.loc 1 115 2 view .LVU179
+ 116:Src/si5351.c  **** 	// Initialize Si5351A
+ 117:Src/si5351.c  **** 	while (si5351_read8(0,dummy) & 0x80);    // Wait for Si5351A to initialize
+ 600              		.loc 1 117 2 view .LVU180
+ 601              	.L32:
+ 602              		.loc 1 117 9 discriminator 1 view .LVU181
+ 603 0004 2146     		mov	r1, r4
+ 604 0006 0020     		movs	r0, #0
+ 605 0008 FFF7FEFF 		bl	si5351_read8
+ 606              	.LVL61:
+ 607 000c 10F0800F 		tst	r0, #128
+ 608 0010 F8D1     		bne	.L32
+ 118:Src/si5351.c  **** 	oeb = 0xFF;
+ 609              		.loc 1 118 2 view .LVU182
+ 610              		.loc 1 118 6 is_stmt 0 view .LVU183
+ 611 0012 FF21     		movs	r1, #255
+ 612 0014 2C4B     		ldr	r3, .L34
+ 613 0016 1970     		strb	r1, [r3]
+ 119:Src/si5351.c  **** 
+ 120:Src/si5351.c  ****     si5351_write8(SI5351_OUT_ENABLE, oeb);            // Output Enable Control, disable all
+ 614              		.loc 1 120 5 is_stmt 1 view .LVU184
+ 615 0018 0320     		movs	r0, #3
+ 616 001a FFF7FEFF 		bl	si5351_write8
+ 617              	.LVL62:
+ 121:Src/si5351.c  **** 
+ 122:Src/si5351.c  ****     si5351_write8(SI5351_INPUT_SOURCE, 0x00);           // PLL Input Source, select the XTAL input 
+ 618              		.loc 1 122 5 view .LVU185
+ 619 001e 0021     		movs	r1, #0
+ 620 0020 0F20     		movs	r0, #15
+ 621 0022 FFF7FEFF 		bl	si5351_write8
+ 622              	.LVL63:
+ 123:Src/si5351.c  ****     si5351_write8(SI5351_OUT_DIS_STATE, 0x00);		// stato bassa Z giu se disabilitati
+ 623              		.loc 1 123 5 view .LVU186
+ 624 0026 0021     		movs	r1, #0
+ 625 0028 1820     		movs	r0, #24
+ 626 002a FFF7FEFF 		bl	si5351_write8
+ 627              	.LVL64:
+ 124:Src/si5351.c  **** 
+ 125:Src/si5351.c  ****     // Output MultisynthN, e = 0, f = 1, MS0_P2 and MSO_P3
+ 126:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH0, 0x00);
+ 628              		.loc 1 126 5 view .LVU187
+ 629 002e 0021     		movs	r1, #0
+ 630 0030 2A20     		movs	r0, #42
+ 631 0032 FFF7FEFF 		bl	si5351_write8
+ 632              	.LVL65:
+ 127:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH0+1, 0x01);
+ 633              		.loc 1 127 5 view .LVU188
+ 634 0036 0121     		movs	r1, #1
+ 635 0038 2B20     		movs	r0, #43
+ 636 003a FFF7FEFF 		bl	si5351_write8
+ARM GAS  /tmp/ccx0f9ME.s 			page 15
+
+
+ 637              	.LVL66:
+ 128:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH0+5, 0x00);
+ 638              		.loc 1 128 5 view .LVU189
+ 639 003e 0021     		movs	r1, #0
+ 640 0040 2F20     		movs	r0, #47
+ 641 0042 FFF7FEFF 		bl	si5351_write8
+ 642              	.LVL67:
+ 129:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH0+6, 0x00);
+ 643              		.loc 1 129 5 view .LVU190
+ 644 0046 0021     		movs	r1, #0
+ 645 0048 3020     		movs	r0, #48
+ 646 004a FFF7FEFF 		bl	si5351_write8
+ 647              	.LVL68:
+ 130:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH0+7, 0x00);
+ 648              		.loc 1 130 5 view .LVU191
+ 649 004e 0021     		movs	r1, #0
+ 650 0050 3120     		movs	r0, #49
+ 651 0052 FFF7FEFF 		bl	si5351_write8
+ 652              	.LVL69:
+ 131:Src/si5351.c  **** 
+ 132:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH1, 0x00);
+ 653              		.loc 1 132 5 view .LVU192
+ 654 0056 0021     		movs	r1, #0
+ 655 0058 3220     		movs	r0, #50
+ 656 005a FFF7FEFF 		bl	si5351_write8
+ 657              	.LVL70:
+ 133:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH1+1, 0x01);
+ 658              		.loc 1 133 5 view .LVU193
+ 659 005e 0121     		movs	r1, #1
+ 660 0060 3320     		movs	r0, #51
+ 661 0062 FFF7FEFF 		bl	si5351_write8
+ 662              	.LVL71:
+ 134:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH1+5, 0x00);
+ 663              		.loc 1 134 5 view .LVU194
+ 664 0066 0021     		movs	r1, #0
+ 665 0068 3720     		movs	r0, #55
+ 666 006a FFF7FEFF 		bl	si5351_write8
+ 667              	.LVL72:
+ 135:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH1+6, 0x00);
+ 668              		.loc 1 135 5 view .LVU195
+ 669 006e 0021     		movs	r1, #0
+ 670 0070 3820     		movs	r0, #56
+ 671 0072 FFF7FEFF 		bl	si5351_write8
+ 672              	.LVL73:
+ 136:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH1+7, 0x00);
+ 673              		.loc 1 136 5 view .LVU196
+ 674 0076 0021     		movs	r1, #0
+ 675 0078 3920     		movs	r0, #57
+ 676 007a FFF7FEFF 		bl	si5351_write8
+ 677              	.LVL74:
+ 137:Src/si5351.c  **** 
+ 138:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH2, 0x00);
+ 678              		.loc 1 138 5 view .LVU197
+ 679 007e 0021     		movs	r1, #0
+ 680 0080 3A20     		movs	r0, #58
+ 681 0082 FFF7FEFF 		bl	si5351_write8
+ 682              	.LVL75:
+ARM GAS  /tmp/ccx0f9ME.s 			page 16
+
+
+ 139:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH2+1, 0x01);
+ 683              		.loc 1 139 5 view .LVU198
+ 684 0086 0121     		movs	r1, #1
+ 685 0088 3B20     		movs	r0, #59
+ 686 008a FFF7FEFF 		bl	si5351_write8
+ 687              	.LVL76:
+ 140:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH2+5, 0x00);
+ 688              		.loc 1 140 5 view .LVU199
+ 689 008e 0021     		movs	r1, #0
+ 690 0090 3F20     		movs	r0, #63
+ 691 0092 FFF7FEFF 		bl	si5351_write8
+ 692              	.LVL77:
+ 141:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH2+6, 0x00);
+ 693              		.loc 1 141 5 view .LVU200
+ 694 0096 0021     		movs	r1, #0
+ 695 0098 4020     		movs	r0, #64
+ 696 009a FFF7FEFF 		bl	si5351_write8
+ 697              	.LVL78:
+ 142:Src/si5351.c  ****     si5351_write8(SI5351_MULTISYNTH2+7, 0x00);
+ 698              		.loc 1 142 5 view .LVU201
+ 699 009e 0021     		movs	r1, #0
+ 700 00a0 4120     		movs	r0, #65
+ 701 00a2 FFF7FEFF 		bl	si5351_write8
+ 702              	.LVL79:
+ 143:Src/si5351.c  **** 
+ 144:Src/si5351.c  ****     si5351_write8(SI5351_CLK0_CONTROL, 0x4F);   // Power up CLK0, PLLA, MS0 operates in integer mod
+ 703              		.loc 1 144 5 view .LVU202
+ 704 00a6 4F21     		movs	r1, #79
+ 705 00a8 1020     		movs	r0, #16
+ 706 00aa FFF7FEFF 		bl	si5351_write8
+ 707              	.LVL80:
+ 145:Src/si5351.c  ****     si5351_write8(SI5351_CLK1_CONTROL, 0x5F);   // Power up CLK1, PLLA, MS0 operates in integer mod
+ 708              		.loc 1 145 5 view .LVU203
+ 709 00ae 5F21     		movs	r1, #95
+ 710 00b0 1120     		movs	r0, #17
+ 711 00b2 FFF7FEFF 		bl	si5351_write8
+ 712              	.LVL81:
+ 146:Src/si5351.c  ****     si5351_write8(SI5351_CLK2_CONTROL, 0x6F);   // Power up CLK2, PLLB, int, non inv, multisynth 2,
+ 713              		.loc 1 146 5 view .LVU204
+ 714 00b6 6F21     		movs	r1, #111
+ 715 00b8 1220     		movs	r0, #18
+ 716 00ba FFF7FEFF 		bl	si5351_write8
+ 717              	.LVL82:
+ 147:Src/si5351.c  **** 
+ 148:Src/si5351.c  ****     // Reference load configuration
+ 149:Src/si5351.c  ****     si5351_write8(SI5351_CRYSTAL_LOAD, 0x12);          // Set reference load C: 6 pF = 0x12, 8 pF =
+ 718              		.loc 1 149 5 view .LVU205
+ 719 00be 1221     		movs	r1, #18
+ 720 00c0 B720     		movs	r0, #183
+ 721 00c2 FFF7FEFF 		bl	si5351_write8
+ 722              	.LVL83:
+ 150:Src/si5351.c  **** }
+ 723              		.loc 1 150 1 is_stmt 0 view .LVU206
+ 724 00c6 10BD     		pop	{r4, pc}
+ 725              	.L35:
+ 726              		.align	2
+ 727              	.L34:
+ARM GAS  /tmp/ccx0f9ME.s 			page 17
+
+
+ 728 00c8 00000000 		.word	oeb
+ 729              		.cfi_endproc
+ 730              	.LFE332:
+ 732              		.section	.text.si5351_set_frequency,"ax",%progbits
+ 733              		.align	1
+ 734              		.global	si5351_set_frequency
+ 735              		.syntax unified
+ 736              		.thumb
+ 737              		.thumb_func
+ 739              	si5351_set_frequency:
+ 740              	.LVL84:
+ 741              	.LFB333:
+ 151:Src/si5351.c  **** 
+ 152:Src/si5351.c  **** void si5351_set_frequency(uint32_t freq, uint8_t pll){
+ 742              		.loc 1 152 54 is_stmt 1 view -0
+ 743              		.cfi_startproc
+ 744              		@ args = 0, pretend = 0, frame = 16
+ 745              		@ frame_needed = 0, uses_anonymous_args = 0
+ 746              		.loc 1 152 54 is_stmt 0 view .LVU208
+ 747 0000 10B5     		push	{r4, lr}
+ 748              	.LCFI8:
+ 749              		.cfi_def_cfa_offset 8
+ 750              		.cfi_offset 4, -8
+ 751              		.cfi_offset 14, -4
+ 752 0002 84B0     		sub	sp, sp, #16
+ 753              	.LCFI9:
+ 754              		.cfi_def_cfa_offset 24
+ 755 0004 0C46     		mov	r4, r1
+ 153:Src/si5351.c  **** 	uint8_t regs[16];
+ 756              		.loc 1 153 2 is_stmt 1 view .LVU209
+ 154:Src/si5351.c  **** 	CalcRegisters(freq, regs);
+ 757              		.loc 1 154 2 view .LVU210
+ 758 0006 6946     		mov	r1, sp
+ 759              	.LVL85:
+ 760              		.loc 1 154 2 is_stmt 0 view .LVU211
+ 761 0008 FFF7FEFF 		bl	CalcRegisters
+ 762              	.LVL86:
+ 155:Src/si5351.c  **** 
+ 156:Src/si5351.c  ****     // Load Output Multisynth0 with d (e and f already set during init. and never changed)
+ 157:Src/si5351.c  **** 	if(pll == 0){
+ 763              		.loc 1 157 2 is_stmt 1 view .LVU212
+ 764              		.loc 1 157 4 is_stmt 0 view .LVU213
+ 765 000c 94B1     		cbz	r4, .L47
+ 158:Src/si5351.c  **** 		for (int i = 0; i < 8; i++)
+ 159:Src/si5351.c  **** 			si5351_write8(SI5351_PLLA + i, regs[i]);
+ 160:Src/si5351.c  **** 		for (int i = 10; i < 13; i++)
+ 161:Src/si5351.c  **** 	        	si5351_write8(34 + i, regs[i]);
+ 162:Src/si5351.c  **** 	} else if(pll == 1){
+ 766              		.loc 1 162 9 is_stmt 1 view .LVU214
+ 767              		.loc 1 162 11 is_stmt 0 view .LVU215
+ 768 000e 012C     		cmp	r4, #1
+ 769 0010 1FD1     		bne	.L42
+ 770              	.LBB4:
+ 163:Src/si5351.c  **** 		for (int i = 0; i < 8; i++)
+ 771              		.loc 1 163 12 view .LVU216
+ 772 0012 0024     		movs	r4, #0
+ 773 0014 2EE0     		b	.L43
+ARM GAS  /tmp/ccx0f9ME.s 			page 18
+
+
+ 774              	.LVL87:
+ 775              	.L39:
+ 776              		.loc 1 163 12 view .LVU217
+ 777              	.LBE4:
+ 778              	.LBB5:
+ 159:Src/si5351.c  **** 		for (int i = 10; i < 13; i++)
+ 779              		.loc 1 159 4 is_stmt 1 discriminator 3 view .LVU218
+ 780 0016 04F11003 		add	r3, r4, #16
+ 781 001a 6B44     		add	r3, sp, r3
+ 782 001c 04F11A00 		add	r0, r4, #26
+ 783 0020 13F8101C 		ldrb	r1, [r3, #-16]	@ zero_extendqisi2
+ 784 0024 C0B2     		uxtb	r0, r0
+ 785 0026 FFF7FEFF 		bl	si5351_write8
+ 786              	.LVL88:
+ 158:Src/si5351.c  **** 		for (int i = 0; i < 8; i++)
+ 787              		.loc 1 158 27 discriminator 3 view .LVU219
+ 788 002a 0134     		adds	r4, r4, #1
+ 789              	.LVL89:
+ 790              	.L37:
+ 158:Src/si5351.c  **** 		for (int i = 0; i < 8; i++)
+ 791              		.loc 1 158 21 discriminator 1 view .LVU220
+ 792 002c 072C     		cmp	r4, #7
+ 793 002e F2DD     		ble	.L39
+ 794              	.LBE5:
+ 795              	.LBB6:
+ 160:Src/si5351.c  **** 	        	si5351_write8(34 + i, regs[i]);
+ 796              		.loc 1 160 12 is_stmt 0 view .LVU221
+ 797 0030 0A24     		movs	r4, #10
+ 798              	.LVL90:
+ 160:Src/si5351.c  **** 	        	si5351_write8(34 + i, regs[i]);
+ 799              		.loc 1 160 12 view .LVU222
+ 800 0032 0CE0     		b	.L40
+ 801              	.LVL91:
+ 802              	.L47:
+ 160:Src/si5351.c  **** 	        	si5351_write8(34 + i, regs[i]);
+ 803              		.loc 1 160 12 view .LVU223
+ 804              	.LBE6:
+ 805              	.LBB7:
+ 158:Src/si5351.c  **** 			si5351_write8(SI5351_PLLA + i, regs[i]);
+ 806              		.loc 1 158 12 view .LVU224
+ 807 0034 0024     		movs	r4, #0
+ 808 0036 F9E7     		b	.L37
+ 809              	.LVL92:
+ 810              	.L41:
+ 158:Src/si5351.c  **** 			si5351_write8(SI5351_PLLA + i, regs[i]);
+ 811              		.loc 1 158 12 view .LVU225
+ 812              	.LBE7:
+ 813              	.LBB8:
+ 161:Src/si5351.c  **** 	} else if(pll == 1){
+ 814              		.loc 1 161 11 is_stmt 1 discriminator 3 view .LVU226
+ 815 0038 04F11003 		add	r3, r4, #16
+ 816 003c 6B44     		add	r3, sp, r3
+ 817 003e 04F12200 		add	r0, r4, #34
+ 818 0042 13F8101C 		ldrb	r1, [r3, #-16]	@ zero_extendqisi2
+ 819 0046 C0B2     		uxtb	r0, r0
+ 820 0048 FFF7FEFF 		bl	si5351_write8
+ 821              	.LVL93:
+ARM GAS  /tmp/ccx0f9ME.s 			page 19
+
+
+ 160:Src/si5351.c  **** 	        	si5351_write8(34 + i, regs[i]);
+ 822              		.loc 1 160 29 discriminator 3 view .LVU227
+ 823 004c 0134     		adds	r4, r4, #1
+ 824              	.LVL94:
+ 825              	.L40:
+ 160:Src/si5351.c  **** 	        	si5351_write8(34 + i, regs[i]);
+ 826              		.loc 1 160 22 discriminator 1 view .LVU228
+ 827 004e 0C2C     		cmp	r4, #12
+ 828 0050 F2DD     		ble	.L41
+ 829              	.LVL95:
+ 830              	.L42:
+ 160:Src/si5351.c  **** 	        	si5351_write8(34 + i, regs[i]);
+ 831              		.loc 1 160 22 is_stmt 0 discriminator 1 view .LVU229
+ 832              	.LBE8:
+ 164:Src/si5351.c  **** 			si5351_write8(SI5351_PLLB + i, regs[i]);
+ 165:Src/si5351.c  **** 		for (int i = 10; i < 13; i++)
+ 166:Src/si5351.c  ****         		si5351_write8(42 + i, regs[i]);
+ 167:Src/si5351.c  **** 	}
+ 168:Src/si5351.c  **** 
+ 169:Src/si5351.c  ****     // Reset PLLA
+ 170:Src/si5351.c  ****     // delayMicroseconds(500);            // Allow registers to settle before resetting the PLL
+ 171:Src/si5351.c  ****     si5351_write8(SI5351_RESET, 0x20);
+ 833              		.loc 1 171 5 is_stmt 1 view .LVU230
+ 834 0052 2021     		movs	r1, #32
+ 835 0054 B120     		movs	r0, #177
+ 836 0056 FFF7FEFF 		bl	si5351_write8
+ 837              	.LVL96:
+ 172:Src/si5351.c  **** }
+ 838              		.loc 1 172 1 is_stmt 0 view .LVU231
+ 839 005a 04B0     		add	sp, sp, #16
+ 840              	.LCFI10:
+ 841              		.cfi_remember_state
+ 842              		.cfi_def_cfa_offset 8
+ 843              		@ sp needed
+ 844 005c 10BD     		pop	{r4, pc}
+ 845              	.LVL97:
+ 846              	.L44:
+ 847              	.LCFI11:
+ 848              		.cfi_restore_state
+ 849              	.LBB9:
+ 164:Src/si5351.c  **** 			si5351_write8(SI5351_PLLB + i, regs[i]);
+ 850              		.loc 1 164 4 is_stmt 1 discriminator 3 view .LVU232
+ 851 005e 04F11003 		add	r3, r4, #16
+ 852 0062 6B44     		add	r3, sp, r3
+ 853 0064 04F12200 		add	r0, r4, #34
+ 854 0068 13F8101C 		ldrb	r1, [r3, #-16]	@ zero_extendqisi2
+ 855 006c C0B2     		uxtb	r0, r0
+ 856 006e FFF7FEFF 		bl	si5351_write8
+ 857              	.LVL98:
+ 163:Src/si5351.c  **** 			si5351_write8(SI5351_PLLB + i, regs[i]);
+ 858              		.loc 1 163 27 discriminator 3 view .LVU233
+ 859 0072 0134     		adds	r4, r4, #1
+ 860              	.LVL99:
+ 861              	.L43:
+ 163:Src/si5351.c  **** 			si5351_write8(SI5351_PLLB + i, regs[i]);
+ 862              		.loc 1 163 21 discriminator 1 view .LVU234
+ 863 0074 072C     		cmp	r4, #7
+ARM GAS  /tmp/ccx0f9ME.s 			page 20
+
+
+ 864 0076 F2DD     		ble	.L44
+ 865              	.LBE9:
+ 866              	.LBB10:
+ 165:Src/si5351.c  ****         		si5351_write8(42 + i, regs[i]);
+ 867              		.loc 1 165 12 is_stmt 0 view .LVU235
+ 868 0078 0A24     		movs	r4, #10
+ 869              	.LVL100:
+ 165:Src/si5351.c  ****         		si5351_write8(42 + i, regs[i]);
+ 870              		.loc 1 165 12 view .LVU236
+ 871 007a 0AE0     		b	.L45
+ 872              	.LVL101:
+ 873              	.L46:
+ 166:Src/si5351.c  **** 	}
+ 874              		.loc 1 166 11 is_stmt 1 discriminator 3 view .LVU237
+ 875 007c 04F11003 		add	r3, r4, #16
+ 876 0080 6B44     		add	r3, sp, r3
+ 877 0082 04F12A00 		add	r0, r4, #42
+ 878 0086 13F8101C 		ldrb	r1, [r3, #-16]	@ zero_extendqisi2
+ 879 008a C0B2     		uxtb	r0, r0
+ 880 008c FFF7FEFF 		bl	si5351_write8
+ 881              	.LVL102:
+ 165:Src/si5351.c  ****         		si5351_write8(42 + i, regs[i]);
+ 882              		.loc 1 165 29 discriminator 3 view .LVU238
+ 883 0090 0134     		adds	r4, r4, #1
+ 884              	.LVL103:
+ 885              	.L45:
+ 165:Src/si5351.c  ****         		si5351_write8(42 + i, regs[i]);
+ 886              		.loc 1 165 22 discriminator 1 view .LVU239
+ 887 0092 0C2C     		cmp	r4, #12
+ 888 0094 F2DD     		ble	.L46
+ 889 0096 DCE7     		b	.L42
+ 890              	.LBE10:
+ 891              		.cfi_endproc
+ 892              	.LFE333:
+ 894              		.section	.text.si5351_off_clk,"ax",%progbits
+ 895              		.align	1
+ 896              		.global	si5351_off_clk
+ 897              		.syntax unified
+ 898              		.thumb
+ 899              		.thumb_func
+ 901              	si5351_off_clk:
+ 902              	.LVL104:
+ 903              	.LFB334:
+ 173:Src/si5351.c  **** 
+ 174:Src/si5351.c  **** void si5351_off_clk(uint8_t clk){
+ 904              		.loc 1 174 33 view -0
+ 905              		.cfi_startproc
+ 906              		@ args = 0, pretend = 0, frame = 0
+ 907              		@ frame_needed = 0, uses_anonymous_args = 0
+ 908              		.loc 1 174 33 is_stmt 0 view .LVU241
+ 909 0000 08B5     		push	{r3, lr}
+ 910              	.LCFI12:
+ 911              		.cfi_def_cfa_offset 8
+ 912              		.cfi_offset 3, -8
+ 913              		.cfi_offset 14, -4
+ 175:Src/si5351.c  **** 	oeb |= 1U << clk;
+ 914              		.loc 1 175 2 is_stmt 1 view .LVU242
+ARM GAS  /tmp/ccx0f9ME.s 			page 21
+
+
+ 915              		.loc 1 175 12 is_stmt 0 view .LVU243
+ 916 0002 0123     		movs	r3, #1
+ 917 0004 8340     		lsls	r3, r3, r0
+ 918              		.loc 1 175 6 view .LVU244
+ 919 0006 044A     		ldr	r2, .L53
+ 920 0008 1178     		ldrb	r1, [r2]	@ zero_extendqisi2
+ 921 000a 1943     		orrs	r1, r1, r3
+ 922 000c C9B2     		uxtb	r1, r1
+ 923 000e 1170     		strb	r1, [r2]
+ 176:Src/si5351.c  **** 	si5351_write8(SI5351_OUT_ENABLE, oeb);
+ 924              		.loc 1 176 2 is_stmt 1 view .LVU245
+ 925 0010 0320     		movs	r0, #3
+ 926              	.LVL105:
+ 927              		.loc 1 176 2 is_stmt 0 view .LVU246
+ 928 0012 FFF7FEFF 		bl	si5351_write8
+ 929              	.LVL106:
+ 177:Src/si5351.c  **** }
+ 930              		.loc 1 177 1 view .LVU247
+ 931 0016 08BD     		pop	{r3, pc}
+ 932              	.L54:
+ 933              		.align	2
+ 934              	.L53:
+ 935 0018 00000000 		.word	oeb
+ 936              		.cfi_endproc
+ 937              	.LFE334:
+ 939              		.section	.text.si5351_on_clk,"ax",%progbits
+ 940              		.align	1
+ 941              		.global	si5351_on_clk
+ 942              		.syntax unified
+ 943              		.thumb
+ 944              		.thumb_func
+ 946              	si5351_on_clk:
+ 947              	.LVL107:
+ 948              	.LFB335:
+ 178:Src/si5351.c  **** 
+ 179:Src/si5351.c  **** void si5351_on_clk(uint8_t clk){
+ 949              		.loc 1 179 32 is_stmt 1 view -0
+ 950              		.cfi_startproc
+ 951              		@ args = 0, pretend = 0, frame = 0
+ 952              		@ frame_needed = 0, uses_anonymous_args = 0
+ 953              		.loc 1 179 32 is_stmt 0 view .LVU249
+ 954 0000 08B5     		push	{r3, lr}
+ 955              	.LCFI13:
+ 956              		.cfi_def_cfa_offset 8
+ 957              		.cfi_offset 3, -8
+ 958              		.cfi_offset 14, -4
+ 180:Src/si5351.c  **** 	oeb &= ~(1U << clk);
+ 959              		.loc 1 180 2 is_stmt 1 view .LVU250
+ 960              		.loc 1 180 14 is_stmt 0 view .LVU251
+ 961 0002 0123     		movs	r3, #1
+ 962 0004 8340     		lsls	r3, r3, r0
+ 963              		.loc 1 180 6 view .LVU252
+ 964 0006 044A     		ldr	r2, .L57
+ 965 0008 1178     		ldrb	r1, [r2]	@ zero_extendqisi2
+ 966 000a 21EA0301 		bic	r1, r1, r3
+ 967 000e 1170     		strb	r1, [r2]
+ 181:Src/si5351.c  **** 	si5351_write8(SI5351_OUT_ENABLE, oeb);
+ARM GAS  /tmp/ccx0f9ME.s 			page 22
+
+
+ 968              		.loc 1 181 2 is_stmt 1 view .LVU253
+ 969 0010 0320     		movs	r0, #3
+ 970              	.LVL108:
+ 971              		.loc 1 181 2 is_stmt 0 view .LVU254
+ 972 0012 FFF7FEFF 		bl	si5351_write8
+ 973              	.LVL109:
+ 182:Src/si5351.c  **** }
+ 974              		.loc 1 182 1 view .LVU255
+ 975 0016 08BD     		pop	{r3, pc}
+ 976              	.L58:
+ 977              		.align	2
+ 978              	.L57:
+ 979 0018 00000000 		.word	oeb
+ 980              		.cfi_endproc
+ 981              	.LFE335:
+ 983              		.global	oeb
+ 984              		.section	.bss.oeb,"aw",%nobits
+ 987              	oeb:
+ 988 0000 00       		.space	1
+ 989              		.text
+ 990              	.Letext0:
+ 991              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 992              		.file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 993              		.file 4 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 994              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 995              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h"
+ 996              		.file 7 "Inc/si5351.h"
+ARM GAS  /tmp/ccx0f9ME.s 			page 23
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 si5351.c
+     /tmp/ccx0f9ME.s:21     .text.si5351_write8:00000000 $t
+     /tmp/ccx0f9ME.s:27     .text.si5351_write8:00000000 si5351_write8
+     /tmp/ccx0f9ME.s:81     .text.si5351_write8:00000038 $d
+     /tmp/ccx0f9ME.s:86     .text.si5351_read8:00000000 $t
+     /tmp/ccx0f9ME.s:92     .text.si5351_read8:00000000 si5351_read8
+     /tmp/ccx0f9ME.s:149    .text.si5351_read8:00000034 $d
+     /tmp/ccx0f9ME.s:162    .text.CalcRegisters:00000000 $t
+     /tmp/ccx0f9ME.s:168    .text.CalcRegisters:00000000 CalcRegisters
+     /tmp/ccx0f9ME.s:566    .text.CalcRegisters:00000190 $d
+     /tmp/ccx0f9ME.s:581    .text.si5351_initialize:00000000 $t
+     /tmp/ccx0f9ME.s:587    .text.si5351_initialize:00000000 si5351_initialize
+     /tmp/ccx0f9ME.s:728    .text.si5351_initialize:000000c8 $d
+     /tmp/ccx0f9ME.s:987    .bss.oeb:00000000 oeb
+     /tmp/ccx0f9ME.s:733    .text.si5351_set_frequency:00000000 $t
+     /tmp/ccx0f9ME.s:739    .text.si5351_set_frequency:00000000 si5351_set_frequency
+     /tmp/ccx0f9ME.s:895    .text.si5351_off_clk:00000000 $t
+     /tmp/ccx0f9ME.s:901    .text.si5351_off_clk:00000000 si5351_off_clk
+     /tmp/ccx0f9ME.s:935    .text.si5351_off_clk:00000018 $d
+     /tmp/ccx0f9ME.s:940    .text.si5351_on_clk:00000000 $t
+     /tmp/ccx0f9ME.s:946    .text.si5351_on_clk:00000000 si5351_on_clk
+     /tmp/ccx0f9ME.s:979    .text.si5351_on_clk:00000018 $d
+     /tmp/ccx0f9ME.s:988    .bss.oeb:00000000 $d
+
+UNDEFINED SYMBOLS
+HAL_I2C_IsDeviceReady
+HAL_I2C_Mem_Write
+hi2c1
+HAL_I2C_Mem_Read
+__aeabi_ui2d
+__aeabi_ddiv
+__aeabi_d2uiz
+__aeabi_d2iz
+__aeabi_i2d
+__aeabi_dsub
+__aeabi_dmul
+__aeabi_dadd
diff --git a/squeow_sw/build/si5351.o b/squeow_sw/build/si5351.o
new file mode 100644
index 0000000000000000000000000000000000000000..0c14612ffc24e82e235f5ae49a96cf8ade7833f2
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literal 0
HcmV?d00001

diff --git a/squeow_sw/build/squeow.d b/squeow_sw/build/squeow.d
new file mode 100644
index 0000000..5827dee
--- /dev/null
+++ b/squeow_sw/build/squeow.d
@@ -0,0 +1,75 @@
+build/squeow.o: Src/squeow.c Inc/main.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h Inc/squeow.h
+Inc/main.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
+Inc/squeow.h:
diff --git a/squeow_sw/build/squeow.lst b/squeow_sw/build/squeow.lst
new file mode 100644
index 0000000..461462c
--- /dev/null
+++ b/squeow_sw/build/squeow.lst
@@ -0,0 +1,623 @@
+ARM GAS  /tmp/ccGt6Pje.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"squeow.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Src/squeow.c"
+  20              		.section	.text.audio_play,"ax",%progbits
+  21              		.align	1
+  22              		.global	audio_play
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	audio_play:
+  28              	.LVL0:
+  29              	.LFB332:
+   1:Src/squeow.c  **** #include <main.h>
+   2:Src/squeow.c  **** #include <stdio.h>
+   3:Src/squeow.c  **** #include <stm32g4xx_hal_conf.h>
+   4:Src/squeow.c  **** #include <math.h>
+   5:Src/squeow.c  **** 
+   6:Src/squeow.c  **** #include "squeow.h"
+   7:Src/squeow.c  **** 
+   8:Src/squeow.c  **** /* SQUEOW
+   9:Src/squeow.c  **** 
+  10:Src/squeow.c  **** TIM3 eventi 98304000/(49152×200) 10hz
+  11:Src/squeow.c  **** TIM2 PWM 98304000/2048 48khz
+  12:Src/squeow.c  **** 
+  13:Src/squeow.c  **** risoluzione PWM 4*2048 -> 8192 (13bit)
+  14:Src/squeow.c  **** 
+  15:Src/squeow.c  **** */
+  16:Src/squeow.c  **** 
+  17:Src/squeow.c  **** uint8_t stato_audio;
+  18:Src/squeow.c  **** uint16_t pwm_value, sample_value;
+  19:Src/squeow.c  **** char display_buffer[16];
+  20:Src/squeow.c  **** uint8_t rails_number;
+  21:Src/squeow.c  **** uint16_t samples_ringbuf[SAMPLES_BUFFER_SIZE]; ///< buffer ad anello dei dati RX
+  22:Src/squeow.c  **** uint16_t samples_ringbuf_input_index, samples_ringbuf_output_index;
+  23:Src/squeow.c  **** 
+  24:Src/squeow.c  **** 
+  25:Src/squeow.c  **** void audio_play(uint16_t pbuf, uint8_t size){
+  30              		.loc 1 25 45 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccGt6Pje.s 			page 2
+
+
+  34              		@ link register save eliminated.
+  26:Src/squeow.c  **** /*
+  27:Src/squeow.c  **** 	char display_buffer[16];
+  28:Src/squeow.c  ****         uint16_t static indice;
+  29:Src/squeow.c  ****         indice++;
+  30:Src/squeow.c  ****         snprintf(display_buffer, 10, "n %d", indice);
+  31:Src/squeow.c  ****         ssd1306_SetCursor(0, 1);
+  32:Src/squeow.c  ****         ssd1306_WriteString(display_buffer, Font_11x18, White);
+  33:Src/squeow.c  **** //        ssd1306_UpdateScreen(&hi2c1);
+  34:Src/squeow.c  **** */
+  35:Src/squeow.c  **** 	for (uint8_t i=0; i<size; i++) {
+  35              		.loc 1 35 2 view .LVU1
+  36              	.LBB2:
+  37              		.loc 1 35 7 view .LVU2
+  38              		.loc 1 35 15 is_stmt 0 view .LVU3
+  39 0000 0023     		movs	r3, #0
+  40              		.loc 1 35 2 view .LVU4
+  41 0002 01E0     		b	.L2
+  42              	.LVL1:
+  43              	.L3:
+  36:Src/squeow.c  **** 		
+  37:Src/squeow.c  **** 	}
+  44              		.loc 1 37 2 is_stmt 1 discriminator 3 view .LVU5
+  35:Src/squeow.c  **** 		
+  45              		.loc 1 35 29 discriminator 3 view .LVU6
+  46 0004 0133     		adds	r3, r3, #1
+  47              	.LVL2:
+  35:Src/squeow.c  **** 		
+  48              		.loc 1 35 29 is_stmt 0 discriminator 3 view .LVU7
+  49 0006 DBB2     		uxtb	r3, r3
+  50              	.LVL3:
+  51              	.L2:
+  35:Src/squeow.c  **** 		
+  52              		.loc 1 35 21 is_stmt 1 discriminator 1 view .LVU8
+  53 0008 8B42     		cmp	r3, r1
+  54 000a FBD3     		bcc	.L3
+  55              	.LBE2:
+  38:Src/squeow.c  **** 
+  39:Src/squeow.c  **** }
+  56              		.loc 1 39 1 is_stmt 0 view .LVU9
+  57 000c 7047     		bx	lr
+  58              		.cfi_endproc
+  59              	.LFE332:
+  61              		.section	.text.sat_sub,"ax",%progbits
+  62              		.align	1
+  63              		.global	sat_sub
+  64              		.syntax unified
+  65              		.thumb
+  66              		.thumb_func
+  68              	sat_sub:
+  69              	.LVL4:
+  70              	.LFB333:
+  40:Src/squeow.c  **** 
+  41:Src/squeow.c  **** uint32_t sat_sub(uint16_t x, uint16_t y){
+  71              		.loc 1 41 41 is_stmt 1 view -0
+  72              		.cfi_startproc
+  73              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/ccGt6Pje.s 			page 3
+
+
+  74              		@ frame_needed = 0, uses_anonymous_args = 0
+  75              		@ link register save eliminated.
+  42:Src/squeow.c  ****     uint16_t res = x - y;
+  76              		.loc 1 42 5 view .LVU11
+  77              		.loc 1 42 14 is_stmt 0 view .LVU12
+  78 0000 411A     		subs	r1, r0, r1
+  79              	.LVL5:
+  80              		.loc 1 42 14 view .LVU13
+  81 0002 89B2     		uxth	r1, r1
+  82              	.LVL6:
+  43:Src/squeow.c  ****     res &= -(res <= x);
+  83              		.loc 1 43 5 is_stmt 1 view .LVU14
+  84              		.loc 1 43 9 is_stmt 0 view .LVU15
+  85 0004 8842     		cmp	r0, r1
+  86 0006 4FF0FF30 		mov	r0, #-1
+  87              	.LVL7:
+  88              		.loc 1 43 9 view .LVU16
+  89 000a 38BF     		it	cc
+  90 000c 0020     		movcc	r0, #0
+  91              	.LVL8:
+  44:Src/squeow.c  ****     return res;
+  92              		.loc 1 44 5 is_stmt 1 view .LVU17
+  45:Src/squeow.c  **** }
+  93              		.loc 1 45 1 is_stmt 0 view .LVU18
+  94 000e 0840     		ands	r0, r0, r1
+  95              	.LVL9:
+  96              		.loc 1 45 1 view .LVU19
+  97 0010 7047     		bx	lr
+  98              		.cfi_endproc
+  99              	.LFE333:
+ 101              		.global	__aeabi_dadd
+ 102              		.global	__aeabi_dcmpge
+ 103              		.global	__aeabi_dmul
+ 104              		.global	__aeabi_d2uiz
+ 105              		.section	.text.u16_sine,"ax",%progbits
+ 106              		.align	1
+ 107              		.global	u16_sine
+ 108              		.syntax unified
+ 109              		.thumb
+ 110              		.thumb_func
+ 112              	u16_sine:
+ 113              	.LFB334:
+  46:Src/squeow.c  **** 
+  47:Src/squeow.c  **** uint16_t u16_sine(void){
+ 114              		.loc 1 47 24 is_stmt 1 view -0
+ 115              		.cfi_startproc
+ 116              		@ args = 0, pretend = 0, frame = 0
+ 117              		@ frame_needed = 0, uses_anonymous_args = 0
+ 118 0000 10B5     		push	{r4, lr}
+ 119              	.LCFI0:
+ 120              		.cfi_def_cfa_offset 8
+ 121              		.cfi_offset 4, -8
+ 122              		.cfi_offset 14, -4
+  48:Src/squeow.c  ****         static double angle;
+ 123              		.loc 1 48 9 view .LVU21
+  49:Src/squeow.c  ****         angle += SINE_INCREMENT;
+ 124              		.loc 1 49 9 view .LVU22
+ARM GAS  /tmp/ccGt6Pje.s 			page 4
+
+
+ 125              		.loc 1 49 15 is_stmt 0 view .LVU23
+ 126 0002 1B4C     		ldr	r4, .L10+24
+ 127 0004 14A3     		adr	r3, .L10
+ 128 0006 D3E90023 		ldrd	r2, [r3]
+ 129 000a D4E90001 		ldrd	r0, [r4]
+ 130 000e FFF7FEFF 		bl	__aeabi_dadd
+ 131              	.LVL10:
+ 132 0012 0246     		mov	r2, r0
+ 133 0014 0B46     		mov	r3, r1
+ 134 0016 C4E90023 		strd	r2, [r4]
+  50:Src/squeow.c  ****          if(angle >= 6.28) angle = 0;
+ 135              		.loc 1 50 10 is_stmt 1 view .LVU24
+ 136              		.loc 1 50 12 is_stmt 0 view .LVU25
+ 137 001a 11A3     		adr	r3, .L10+8
+ 138 001c D3E90023 		ldrd	r2, [r3]
+ 139 0020 FFF7FEFF 		bl	__aeabi_dcmpge
+ 140              	.LVL11:
+ 141 0024 18B1     		cbz	r0, .L6
+ 142              		.loc 1 50 28 is_stmt 1 discriminator 1 view .LVU26
+ 143              		.loc 1 50 34 is_stmt 0 discriminator 1 view .LVU27
+ 144 0026 0020     		movs	r0, #0
+ 145 0028 0021     		movs	r1, #0
+ 146 002a C4E90001 		strd	r0, [r4]
+ 147              	.L6:
+  51:Src/squeow.c  ****         return (uint16_t)((sin(angle)*0x7fff)+0x7fff);
+ 148              		.loc 1 51 9 is_stmt 1 view .LVU28
+ 149              		.loc 1 51 28 is_stmt 0 view .LVU29
+ 150 002e 104B     		ldr	r3, .L10+24
+ 151 0030 93ED000B 		vldr.64	d0, [r3]
+ 152 0034 FFF7FEFF 		bl	sin
+ 153              	.LVL12:
+ 154 0038 51EC100B 		vmov	r0, r1, d0
+ 155              		.loc 1 51 38 view .LVU30
+ 156 003c 0AA3     		adr	r3, .L10+16
+ 157 003e D3E90023 		ldrd	r2, [r3]
+ 158 0042 FFF7FEFF 		bl	__aeabi_dmul
+ 159              	.LVL13:
+ 160              		.loc 1 51 46 view .LVU31
+ 161 0046 08A3     		adr	r3, .L10+16
+ 162 0048 D3E90023 		ldrd	r2, [r3]
+ 163 004c FFF7FEFF 		bl	__aeabi_dadd
+ 164              	.LVL14:
+ 165              		.loc 1 51 16 view .LVU32
+ 166 0050 FFF7FEFF 		bl	__aeabi_d2uiz
+ 167              	.LVL15:
+  52:Src/squeow.c  **** }
+ 168              		.loc 1 52 1 view .LVU33
+ 169 0054 80B2     		uxth	r0, r0
+ 170 0056 10BD     		pop	{r4, pc}
+ 171              	.L11:
+ 172              		.align	3
+ 173              	.L10:
+ 174 0058 7F6ABC74 		.word	1958505087
+ 175 005c 9318D43F 		.word	1070864531
+ 176 0060 1F85EB51 		.word	1374389535
+ 177 0064 B81E1940 		.word	1075388088
+ 178 0068 00000000 		.word	0
+ARM GAS  /tmp/ccGt6Pje.s 			page 5
+
+
+ 179 006c C0FFDF40 		.word	1088421824
+ 180 0070 00000000 		.word	angle.1
+ 181              		.cfi_endproc
+ 182              	.LFE334:
+ 184              		.section	.text.u12_sine,"ax",%progbits
+ 185              		.align	1
+ 186              		.global	u12_sine
+ 187              		.syntax unified
+ 188              		.thumb
+ 189              		.thumb_func
+ 191              	u12_sine:
+ 192              	.LFB335:
+  53:Src/squeow.c  **** 
+  54:Src/squeow.c  **** uint16_t u12_sine(void){
+ 193              		.loc 1 54 24 is_stmt 1 view -0
+ 194              		.cfi_startproc
+ 195              		@ args = 0, pretend = 0, frame = 0
+ 196              		@ frame_needed = 0, uses_anonymous_args = 0
+ 197 0000 10B5     		push	{r4, lr}
+ 198              	.LCFI1:
+ 199              		.cfi_def_cfa_offset 8
+ 200              		.cfi_offset 4, -8
+ 201              		.cfi_offset 14, -4
+  55:Src/squeow.c  ****         static double angle;
+ 202              		.loc 1 55 9 view .LVU35
+  56:Src/squeow.c  ****         angle += SINE_INCREMENT;
+ 203              		.loc 1 56 9 view .LVU36
+ 204              		.loc 1 56 15 is_stmt 0 view .LVU37
+ 205 0002 1B4C     		ldr	r4, .L17+24
+ 206 0004 14A3     		adr	r3, .L17
+ 207 0006 D3E90023 		ldrd	r2, [r3]
+ 208 000a D4E90001 		ldrd	r0, [r4]
+ 209 000e FFF7FEFF 		bl	__aeabi_dadd
+ 210              	.LVL16:
+ 211 0012 0246     		mov	r2, r0
+ 212 0014 0B46     		mov	r3, r1
+ 213 0016 C4E90023 		strd	r2, [r4]
+  57:Src/squeow.c  ****          if(angle >= 6.28) angle = 0;
+ 214              		.loc 1 57 10 is_stmt 1 view .LVU38
+ 215              		.loc 1 57 12 is_stmt 0 view .LVU39
+ 216 001a 11A3     		adr	r3, .L17+8
+ 217 001c D3E90023 		ldrd	r2, [r3]
+ 218 0020 FFF7FEFF 		bl	__aeabi_dcmpge
+ 219              	.LVL17:
+ 220 0024 18B1     		cbz	r0, .L13
+ 221              		.loc 1 57 28 is_stmt 1 discriminator 1 view .LVU40
+ 222              		.loc 1 57 34 is_stmt 0 discriminator 1 view .LVU41
+ 223 0026 0020     		movs	r0, #0
+ 224 0028 0021     		movs	r1, #0
+ 225 002a C4E90001 		strd	r0, [r4]
+ 226              	.L13:
+  58:Src/squeow.c  ****         return (uint16_t)((sin(angle)*0x7ff)+0x7ff);
+ 227              		.loc 1 58 9 is_stmt 1 view .LVU42
+ 228              		.loc 1 58 28 is_stmt 0 view .LVU43
+ 229 002e 104B     		ldr	r3, .L17+24
+ 230 0030 93ED000B 		vldr.64	d0, [r3]
+ 231 0034 FFF7FEFF 		bl	sin
+ARM GAS  /tmp/ccGt6Pje.s 			page 6
+
+
+ 232              	.LVL18:
+ 233 0038 51EC100B 		vmov	r0, r1, d0
+ 234              		.loc 1 58 38 view .LVU44
+ 235 003c 0AA3     		adr	r3, .L17+16
+ 236 003e D3E90023 		ldrd	r2, [r3]
+ 237 0042 FFF7FEFF 		bl	__aeabi_dmul
+ 238              	.LVL19:
+ 239              		.loc 1 58 45 view .LVU45
+ 240 0046 08A3     		adr	r3, .L17+16
+ 241 0048 D3E90023 		ldrd	r2, [r3]
+ 242 004c FFF7FEFF 		bl	__aeabi_dadd
+ 243              	.LVL20:
+ 244              		.loc 1 58 16 view .LVU46
+ 245 0050 FFF7FEFF 		bl	__aeabi_d2uiz
+ 246              	.LVL21:
+  59:Src/squeow.c  **** }
+ 247              		.loc 1 59 1 view .LVU47
+ 248 0054 80B2     		uxth	r0, r0
+ 249 0056 10BD     		pop	{r4, pc}
+ 250              	.L18:
+ 251              		.align	3
+ 252              	.L17:
+ 253 0058 7F6ABC74 		.word	1958505087
+ 254 005c 9318D43F 		.word	1070864531
+ 255 0060 1F85EB51 		.word	1374389535
+ 256 0064 B81E1940 		.word	1075388088
+ 257 0068 00000000 		.word	0
+ 258 006c 00FC9F40 		.word	1084226560
+ 259 0070 00000000 		.word	angle.0
+ 260              		.cfi_endproc
+ 261              	.LFE335:
+ 263              		.section	.text.sample,"ax",%progbits
+ 264              		.align	1
+ 265              		.global	sample
+ 266              		.syntax unified
+ 267              		.thumb
+ 268              		.thumb_func
+ 270              	sample:
+ 271              	.LFB336:
+  60:Src/squeow.c  **** 
+  61:Src/squeow.c  **** uint16_t sample(void){
+ 272              		.loc 1 61 22 is_stmt 1 view -0
+ 273              		.cfi_startproc
+ 274              		@ args = 0, pretend = 0, frame = 0
+ 275              		@ frame_needed = 0, uses_anonymous_args = 0
+ 276              		@ link register save eliminated.
+  62:Src/squeow.c  **** /*
+  63:Src/squeow.c  ****                         stato_audio == STATO_AUDIO_ADC;
+  64:Src/squeow.c  ****                         HAL_ADC_Start(&hadc1);
+  65:Src/squeow.c  ****                         if (HAL_ADC_PollForConversion(&hadc1, 10) == HAL_OK){
+  66:Src/squeow.c  **** //                              store_sample(HAL_ADC_GetValue(&hadc1) << 4);
+  67:Src/squeow.c  ****                                 sample_value = HAL_ADC_GetValue(&hadc1);
+  68:Src/squeow.c  ****                         }
+  69:Src/squeow.c  ****                         HAL_ADC_Stop(&hadc1);
+  70:Src/squeow.c  ****                         */
+  71:Src/squeow.c  **** }
+ 277              		.loc 1 71 1 view .LVU49
+ARM GAS  /tmp/ccGt6Pje.s 			page 7
+
+
+ 278 0000 7047     		bx	lr
+ 279              		.cfi_endproc
+ 280              	.LFE336:
+ 282              		.section	.text.store_sample,"ax",%progbits
+ 283              		.align	1
+ 284              		.global	store_sample
+ 285              		.syntax unified
+ 286              		.thumb
+ 287              		.thumb_func
+ 289              	store_sample:
+ 290              	.LVL22:
+ 291              	.LFB338:
+  72:Src/squeow.c  **** 
+  73:Src/squeow.c  **** void store_samples(uint16_t *data, uint16_t size){
+  74:Src/squeow.c  ****         for(uint16_t i = 0; i < size; ++i) {
+  75:Src/squeow.c  ****               samples_ringbuf[samples_ringbuf_input_index] = data[i];
+  76:Src/squeow.c  ****                 store_sample(data[i]);
+  77:Src/squeow.c  ****         }
+  78:Src/squeow.c  **** }
+  79:Src/squeow.c  **** 
+  80:Src/squeow.c  **** void store_sample(uint16_t sample){
+ 292              		.loc 1 80 35 view -0
+ 293              		.cfi_startproc
+ 294              		@ args = 0, pretend = 0, frame = 0
+ 295              		@ frame_needed = 0, uses_anonymous_args = 0
+ 296              		.loc 1 80 35 is_stmt 0 view .LVU51
+ 297 0000 08B5     		push	{r3, lr}
+ 298              	.LCFI2:
+ 299              		.cfi_def_cfa_offset 8
+ 300              		.cfi_offset 3, -8
+ 301              		.cfi_offset 14, -4
+  81:Src/squeow.c  ****                 samples_ringbuf[samples_ringbuf_input_index] = sample;
+ 302              		.loc 1 81 17 is_stmt 1 view .LVU52
+ 303              		.loc 1 81 32 is_stmt 0 view .LVU53
+ 304 0002 054B     		ldr	r3, .L22
+ 305 0004 1988     		ldrh	r1, [r3]
+ 306              		.loc 1 81 62 view .LVU54
+ 307 0006 054A     		ldr	r2, .L22+4
+ 308 0008 22F81100 		strh	r0, [r2, r1, lsl #1]	@ movhi
+  82:Src/squeow.c  ****                 ringbuf_increment(&samples_ringbuf_input_index, SAMPLES_BUFFER_SIZE_MASK);
+ 309              		.loc 1 82 17 is_stmt 1 view .LVU55
+ 310 000c 40F2FF31 		movw	r1, #1023
+ 311 0010 1846     		mov	r0, r3
+ 312              	.LVL23:
+ 313              		.loc 1 82 17 is_stmt 0 view .LVU56
+ 314 0012 FFF7FEFF 		bl	ringbuf_increment
+ 315              	.LVL24:
+  83:Src/squeow.c  **** }
+ 316              		.loc 1 83 1 view .LVU57
+ 317 0016 08BD     		pop	{r3, pc}
+ 318              	.L23:
+ 319              		.align	2
+ 320              	.L22:
+ 321 0018 00000000 		.word	samples_ringbuf_input_index
+ 322 001c 00000000 		.word	samples_ringbuf
+ 323              		.cfi_endproc
+ 324              	.LFE338:
+ARM GAS  /tmp/ccGt6Pje.s 			page 8
+
+
+ 326              		.section	.text.store_samples,"ax",%progbits
+ 327              		.align	1
+ 328              		.global	store_samples
+ 329              		.syntax unified
+ 330              		.thumb
+ 331              		.thumb_func
+ 333              	store_samples:
+ 334              	.LVL25:
+ 335              	.LFB337:
+  73:Src/squeow.c  ****         for(uint16_t i = 0; i < size; ++i) {
+ 336              		.loc 1 73 50 is_stmt 1 view -0
+ 337              		.cfi_startproc
+ 338              		@ args = 0, pretend = 0, frame = 0
+ 339              		@ frame_needed = 0, uses_anonymous_args = 0
+  73:Src/squeow.c  ****         for(uint16_t i = 0; i < size; ++i) {
+ 340              		.loc 1 73 50 is_stmt 0 view .LVU59
+ 341 0000 70B5     		push	{r4, r5, r6, lr}
+ 342              	.LCFI3:
+ 343              		.cfi_def_cfa_offset 16
+ 344              		.cfi_offset 4, -16
+ 345              		.cfi_offset 5, -12
+ 346              		.cfi_offset 6, -8
+ 347              		.cfi_offset 14, -4
+ 348 0002 0646     		mov	r6, r0
+ 349 0004 0D46     		mov	r5, r1
+  74:Src/squeow.c  ****               samples_ringbuf[samples_ringbuf_input_index] = data[i];
+ 350              		.loc 1 74 9 is_stmt 1 view .LVU60
+ 351              	.LBB3:
+  74:Src/squeow.c  ****               samples_ringbuf[samples_ringbuf_input_index] = data[i];
+ 352              		.loc 1 74 13 view .LVU61
+ 353              	.LVL26:
+  74:Src/squeow.c  ****               samples_ringbuf[samples_ringbuf_input_index] = data[i];
+ 354              		.loc 1 74 22 is_stmt 0 view .LVU62
+ 355 0006 0024     		movs	r4, #0
+  74:Src/squeow.c  ****               samples_ringbuf[samples_ringbuf_input_index] = data[i];
+ 356              		.loc 1 74 9 view .LVU63
+ 357 0008 0AE0     		b	.L25
+ 358              	.LVL27:
+ 359              	.L26:
+  75:Src/squeow.c  ****                 store_sample(data[i]);
+ 360              		.loc 1 75 15 is_stmt 1 discriminator 3 view .LVU64
+  75:Src/squeow.c  ****                 store_sample(data[i]);
+ 361              		.loc 1 75 30 is_stmt 0 discriminator 3 view .LVU65
+ 362 000a 074B     		ldr	r3, .L28
+ 363 000c 1A88     		ldrh	r2, [r3]
+  75:Src/squeow.c  ****                 store_sample(data[i]);
+ 364              		.loc 1 75 66 discriminator 3 view .LVU66
+ 365 000e 36F81400 		ldrh	r0, [r6, r4, lsl #1]
+  75:Src/squeow.c  ****                 store_sample(data[i]);
+ 366              		.loc 1 75 60 discriminator 3 view .LVU67
+ 367 0012 064B     		ldr	r3, .L28+4
+ 368 0014 23F81200 		strh	r0, [r3, r2, lsl #1]	@ movhi
+  76:Src/squeow.c  ****         }
+ 369              		.loc 1 76 17 is_stmt 1 discriminator 3 view .LVU68
+ 370 0018 FFF7FEFF 		bl	store_sample
+ 371              	.LVL28:
+  74:Src/squeow.c  ****               samples_ringbuf[samples_ringbuf_input_index] = data[i];
+ARM GAS  /tmp/ccGt6Pje.s 			page 9
+
+
+ 372              		.loc 1 74 39 discriminator 3 view .LVU69
+ 373 001c 0134     		adds	r4, r4, #1
+ 374              	.LVL29:
+  74:Src/squeow.c  ****               samples_ringbuf[samples_ringbuf_input_index] = data[i];
+ 375              		.loc 1 74 39 is_stmt 0 discriminator 3 view .LVU70
+ 376 001e A4B2     		uxth	r4, r4
+ 377              	.LVL30:
+ 378              	.L25:
+  74:Src/squeow.c  ****               samples_ringbuf[samples_ringbuf_input_index] = data[i];
+ 379              		.loc 1 74 31 is_stmt 1 discriminator 1 view .LVU71
+ 380 0020 AC42     		cmp	r4, r5
+ 381 0022 F2D3     		bcc	.L26
+ 382              	.LBE3:
+  78:Src/squeow.c  **** 
+ 383              		.loc 1 78 1 is_stmt 0 view .LVU72
+ 384 0024 70BD     		pop	{r4, r5, r6, pc}
+ 385              	.LVL31:
+ 386              	.L29:
+  78:Src/squeow.c  **** 
+ 387              		.loc 1 78 1 view .LVU73
+ 388 0026 00BF     		.align	2
+ 389              	.L28:
+ 390 0028 00000000 		.word	samples_ringbuf_input_index
+ 391 002c 00000000 		.word	samples_ringbuf
+ 392              		.cfi_endproc
+ 393              	.LFE337:
+ 395              		.section	.bss.angle.0,"aw",%nobits
+ 396              		.align	3
+ 399              	angle.0:
+ 400 0000 00000000 		.space	8
+ 400      00000000 
+ 401              		.section	.bss.angle.1,"aw",%nobits
+ 402              		.align	3
+ 405              	angle.1:
+ 406 0000 00000000 		.space	8
+ 406      00000000 
+ 407              		.global	samples_ringbuf_output_index
+ 408              		.section	.bss.samples_ringbuf_output_index,"aw",%nobits
+ 409              		.align	1
+ 412              	samples_ringbuf_output_index:
+ 413 0000 0000     		.space	2
+ 414              		.global	samples_ringbuf_input_index
+ 415              		.section	.bss.samples_ringbuf_input_index,"aw",%nobits
+ 416              		.align	1
+ 419              	samples_ringbuf_input_index:
+ 420 0000 0000     		.space	2
+ 421              		.global	samples_ringbuf
+ 422              		.section	.bss.samples_ringbuf,"aw",%nobits
+ 423              		.align	2
+ 426              	samples_ringbuf:
+ 427 0000 00000000 		.space	2048
+ 427      00000000 
+ 427      00000000 
+ 427      00000000 
+ 427      00000000 
+ 428              		.global	rails_number
+ 429              		.section	.bss.rails_number,"aw",%nobits
+ARM GAS  /tmp/ccGt6Pje.s 			page 10
+
+
+ 432              	rails_number:
+ 433 0000 00       		.space	1
+ 434              		.global	display_buffer
+ 435              		.section	.bss.display_buffer,"aw",%nobits
+ 436              		.align	2
+ 439              	display_buffer:
+ 440 0000 00000000 		.space	16
+ 440      00000000 
+ 440      00000000 
+ 440      00000000 
+ 441              		.global	sample_value
+ 442              		.section	.bss.sample_value,"aw",%nobits
+ 443              		.align	1
+ 446              	sample_value:
+ 447 0000 0000     		.space	2
+ 448              		.global	pwm_value
+ 449              		.section	.bss.pwm_value,"aw",%nobits
+ 450              		.align	1
+ 453              	pwm_value:
+ 454 0000 0000     		.space	2
+ 455              		.global	stato_audio
+ 456              		.section	.bss.stato_audio,"aw",%nobits
+ 459              	stato_audio:
+ 460 0000 00       		.space	1
+ 461              		.text
+ 462              	.Letext0:
+ 463              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 464              		.file 3 "Inc/squeow.h"
+ 465              		.file 4 "/usr/include/newlib/math.h"
+ARM GAS  /tmp/ccGt6Pje.s 			page 11
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 squeow.c
+     /tmp/ccGt6Pje.s:21     .text.audio_play:00000000 $t
+     /tmp/ccGt6Pje.s:27     .text.audio_play:00000000 audio_play
+     /tmp/ccGt6Pje.s:62     .text.sat_sub:00000000 $t
+     /tmp/ccGt6Pje.s:68     .text.sat_sub:00000000 sat_sub
+     /tmp/ccGt6Pje.s:106    .text.u16_sine:00000000 $t
+     /tmp/ccGt6Pje.s:112    .text.u16_sine:00000000 u16_sine
+     /tmp/ccGt6Pje.s:174    .text.u16_sine:00000058 $d
+     /tmp/ccGt6Pje.s:405    .bss.angle.1:00000000 angle.1
+     /tmp/ccGt6Pje.s:185    .text.u12_sine:00000000 $t
+     /tmp/ccGt6Pje.s:191    .text.u12_sine:00000000 u12_sine
+     /tmp/ccGt6Pje.s:253    .text.u12_sine:00000058 $d
+     /tmp/ccGt6Pje.s:399    .bss.angle.0:00000000 angle.0
+     /tmp/ccGt6Pje.s:264    .text.sample:00000000 $t
+     /tmp/ccGt6Pje.s:270    .text.sample:00000000 sample
+     /tmp/ccGt6Pje.s:283    .text.store_sample:00000000 $t
+     /tmp/ccGt6Pje.s:289    .text.store_sample:00000000 store_sample
+     /tmp/ccGt6Pje.s:321    .text.store_sample:00000018 $d
+     /tmp/ccGt6Pje.s:419    .bss.samples_ringbuf_input_index:00000000 samples_ringbuf_input_index
+     /tmp/ccGt6Pje.s:426    .bss.samples_ringbuf:00000000 samples_ringbuf
+     /tmp/ccGt6Pje.s:327    .text.store_samples:00000000 $t
+     /tmp/ccGt6Pje.s:333    .text.store_samples:00000000 store_samples
+     /tmp/ccGt6Pje.s:390    .text.store_samples:00000028 $d
+     /tmp/ccGt6Pje.s:396    .bss.angle.0:00000000 $d
+     /tmp/ccGt6Pje.s:402    .bss.angle.1:00000000 $d
+     /tmp/ccGt6Pje.s:412    .bss.samples_ringbuf_output_index:00000000 samples_ringbuf_output_index
+     /tmp/ccGt6Pje.s:409    .bss.samples_ringbuf_output_index:00000000 $d
+     /tmp/ccGt6Pje.s:416    .bss.samples_ringbuf_input_index:00000000 $d
+     /tmp/ccGt6Pje.s:423    .bss.samples_ringbuf:00000000 $d
+     /tmp/ccGt6Pje.s:432    .bss.rails_number:00000000 rails_number
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diff --git a/squeow_sw/build/squeow.o b/squeow_sw/build/squeow.o
new file mode 100644
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diff --git a/squeow_sw/build/squeow_codice.elf b/squeow_sw/build/squeow_codice.elf
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new file mode 100644
index 0000000..95f322f
--- /dev/null
+++ b/squeow_sw/build/squeow_codice.hex
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diff --git a/squeow_sw/build/squeow_codice.map b/squeow_sw/build/squeow_codice.map
new file mode 100644
index 0000000..e3866b2
--- /dev/null
+++ b/squeow_sw/build/squeow_codice.map
@@ -0,0 +1,4659 @@
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+ .debug_loc     0x00000000      0x238 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_scalbn.o)
+ .debug_aranges
+                0x00000000       0x20 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_scalbn.o)
+ .debug_ranges  0x00000000       0x50 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_scalbn.o)
+ .debug_line    0x00000000      0x229 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_scalbn.o)
+ .debug_str     0x00000000      0x234 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_scalbn.o)
+ .comment       0x00000000       0x34 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_scalbn.o)
+ .debug_frame   0x00000000       0x2c /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_scalbn.o)
+ .ARM.attributes
+                0x00000000       0x34 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_scalbn.o)
+ .text          0x00000000        0x4 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+ .data          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+ .bss           0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+ .debug_info    0x00000000       0xa3 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+ .debug_abbrev  0x00000000       0x6a /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+ .debug_loc     0x00000000       0x15 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+ .debug_aranges
+                0x00000000       0x20 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+ .debug_line    0x00000000       0x75 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+ .debug_str     0x00000000      0x181 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+ .comment       0x00000000       0x34 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+ .debug_frame   0x00000000       0x20 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+ .ARM.attributes
+                0x00000000       0x34 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+ .text          0x00000000      0x254 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+ .data          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+ .bss           0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+ .debug_line    0x00000000       0xf5 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+ .debug_line_str
+                0x00000000       0x9c /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+ .debug_info    0x00000000       0x3c /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+ .debug_abbrev  0x00000000       0x1f /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+ .debug_aranges
+                0x00000000       0x20 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+ .debug_str     0x00000000       0xbe /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+ .debug_frame   0x00000000       0x30 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+ .ARM.attributes
+                0x00000000       0x22 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+ .data          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+ .bss           0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+ .data          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldivdf3.o)
+ .bss           0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldivdf3.o)
+ .text          0x00000000      0x110 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+ .data          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+ .bss           0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+ .debug_line    0x00000000       0xa6 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+ .debug_line_str
+                0x00000000       0x9c /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+ .debug_info    0x00000000       0xc0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+ .debug_abbrev  0x00000000       0x21 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+ .debug_aranges
+                0x00000000       0x20 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+ .debug_str     0x00000000      0x15d /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+ .debug_frame   0x00000000       0xc4 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+ .ARM.attributes
+                0x00000000       0x22 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+ .data          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_fixdfsi.o)
+ .bss           0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_fixdfsi.o)
+ .data          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_fixunsdfsi.o)
+ .bss           0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_fixunsdfsi.o)
+ .data          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o)
+ .bss           0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o)
+ .data          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o)
+ .bss           0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o)
+ .ARM.extab     0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o)
+ .data          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o)
+ .bss           0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o)
+ .text          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtend.o
+ .data          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtend.o
+ .bss           0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtend.o
+ .rodata        0x00000000       0x24 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtend.o
+ .eh_frame      0x00000000        0x4 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtend.o
+ .text          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtn.o
+ .data          0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtn.o
+ .bss           0x00000000        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtn.o
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+RAM              0x20000000         0x00008000         xrw
+FLASH            0x08000000         0x00020000         xr
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crti.o
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+LOAD build/main.o
+LOAD build/squeow.o
+LOAD build/si5351.o
+LOAD build/stm32g4xx_it.o
+LOAD build/stm32g4xx_hal_msp.o
+LOAD build/stm32g4xx_hal.o
+LOAD build/stm32g4xx_hal_rcc.o
+LOAD build/stm32g4xx_hal_rcc_ex.o
+LOAD build/stm32g4xx_hal_flash.o
+LOAD build/stm32g4xx_hal_flash_ex.o
+LOAD build/stm32g4xx_hal_flash_ramfunc.o
+LOAD build/stm32g4xx_hal_gpio.o
+LOAD build/stm32g4xx_hal_exti.o
+LOAD build/stm32g4xx_hal_dma.o
+LOAD build/stm32g4xx_hal_dma_ex.o
+LOAD build/stm32g4xx_hal_pwr.o
+LOAD build/stm32g4xx_hal_pwr_ex.o
+LOAD build/stm32g4xx_hal_cortex.o
+LOAD build/stm32g4xx_hal_adc.o
+LOAD build/stm32g4xx_hal_adc_ex.o
+LOAD build/stm32g4xx_ll_adc.o
+LOAD build/stm32g4xx_hal_i2c.o
+LOAD build/stm32g4xx_hal_i2c_ex.o
+LOAD build/stm32g4xx_hal_tim.o
+LOAD build/stm32g4xx_hal_tim_ex.o
+LOAD build/stm32g4xx_hal_uart.o
+LOAD build/stm32g4xx_hal_uart_ex.o
+LOAD build/system_stm32g4xx.o
+LOAD build/usb_device.o
+LOAD build/usbd_conf.o
+LOAD build/usbd_desc.o
+LOAD build/usbd_audio_if.o
+LOAD build/stm32g4xx_hal_pcd.o
+LOAD build/stm32g4xx_hal_pcd_ex.o
+LOAD build/stm32g4xx_ll_usb.o
+LOAD build/usbd_core.o
+LOAD build/usbd_ctlreq.o
+LOAD build/usbd_ioreq.o
+LOAD build/usbd_audio.o
+LOAD build/startup_stm32g431xx.o
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a
+END GROUP
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a
+END GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtend.o
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtn.o
+                0x20008000                        _estack = (ORIGIN (RAM) + LENGTH (RAM))
+                0x00000200                        _Min_Heap_Size = 0x200
+                0x00000400                        _Min_Stack_Size = 0x400
+
+.isr_vector     0x08000000      0x1d8
+                0x08000000                        . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector    0x08000000      0x1d8 build/startup_stm32g431xx.o
+                0x08000000                g_pfnVectors
+                0x080001d8                        . = ALIGN (0x4)
+
+.text           0x080001d8     0x7e30
+                0x080001d8                        . = ALIGN (0x4)
+ *(.text)
+ .text          0x080001d8       0x88 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+ .text          0x08000260       0x48 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-init.o)
+                0x08000260                __libc_init_array
+ .text          0x080002a8       0xa4 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-memset.o)
+                0x080002a8                memset
+ .text          0x0800034c      0x378 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+                0x0800034c                __aeabi_drsub
+                0x08000354                __aeabi_dsub
+                0x08000354                __subdf3
+                0x08000358                __adddf3
+                0x08000358                __aeabi_dadd
+                0x080005d0                __aeabi_ui2d
+                0x080005d0                __floatunsidf
+                0x080005f0                __floatsidf
+                0x080005f0                __aeabi_i2d
+                0x08000614                __extendsfdf2
+                0x08000614                __aeabi_f2d
+                0x08000658                __aeabi_ul2d
+                0x08000658                __floatundidf
+                0x08000668                __floatdidf
+                0x08000668                __aeabi_l2d
+ .text          0x080006c4      0x424 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldivdf3.o)
+                0x080006c4                __aeabi_dmul
+                0x080006c4                __muldf3
+                0x08000918                __aeabi_ddiv
+                0x08000918                __divdf3
+ .text          0x08000ae8       0x50 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_fixdfsi.o)
+                0x08000ae8                __fixdfsi
+                0x08000ae8                __aeabi_d2iz
+ .text          0x08000b38       0x40 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_fixunsdfsi.o)
+                0x08000b38                __fixunsdfsi
+                0x08000b38                __aeabi_d2uiz
+ .text          0x08000b78       0x30 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o)
+                0x08000b78                __aeabi_uldivmod
+ .text          0x08000ba8      0x2bc /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o)
+                0x08000ba8                __udivmoddi4
+ .text          0x08000e64        0x4 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o)
+                0x08000e64                __aeabi_ldiv0
+                0x08000e64                __aeabi_idiv0
+ *(.text*)
+ .text.MX_GPIO_Init
+                0x08000e68       0x7c build/main.o
+ .text.Error_Handler
+                0x08000ee4        0x4 build/main.o
+                0x08000ee4                Error_Handler
+ .text.MX_TIM2_Init
+                0x08000ee8       0xf0 build/main.o
+ .text.MX_I2C1_Init
+                0x08000fd8       0x54 build/main.o
+ .text.MX_TIM3_Init
+                0x0800102c       0x6c build/main.o
+ .text.MX_ADC1_Init
+                0x08001098       0x98 build/main.o
+ .text.MX_ADC2_Init
+                0x08001130       0xbc build/main.o
+ .text.MX_USART1_UART_Init
+                0x080011ec       0x60 build/main.o
+ .text.SystemClock_Config
+                0x0800124c       0x84 build/main.o
+                0x0800124c                SystemClock_Config
+ .text.main     0x080012d0       0xac build/main.o
+                0x080012d0                main
+ .text.si5351_write8
+                0x0800137c       0x3c build/si5351.o
+                0x0800137c                si5351_write8
+ .text.si5351_read8
+                0x080013b8       0x38 build/si5351.o
+                0x080013b8                si5351_read8
+ .text.CalcRegisters
+                0x080013f0      0x1bc build/si5351.o
+                0x080013f0                CalcRegisters
+ .text.si5351_initialize
+                0x080015ac       0xcc build/si5351.o
+                0x080015ac                si5351_initialize
+ .text.si5351_set_frequency
+                0x08001678       0x98 build/si5351.o
+                0x08001678                si5351_set_frequency
+ .text.si5351_on_clk
+                0x08001710       0x1c build/si5351.o
+                0x08001710                si5351_on_clk
+ .text.NMI_Handler
+                0x0800172c        0x2 build/stm32g4xx_it.o
+                0x0800172c                NMI_Handler
+ .text.HardFault_Handler
+                0x0800172e        0x2 build/stm32g4xx_it.o
+                0x0800172e                HardFault_Handler
+ .text.MemManage_Handler
+                0x08001730        0x2 build/stm32g4xx_it.o
+                0x08001730                MemManage_Handler
+ .text.BusFault_Handler
+                0x08001732        0x2 build/stm32g4xx_it.o
+                0x08001732                BusFault_Handler
+ .text.UsageFault_Handler
+                0x08001734        0x2 build/stm32g4xx_it.o
+                0x08001734                UsageFault_Handler
+ .text.SVC_Handler
+                0x08001736        0x2 build/stm32g4xx_it.o
+                0x08001736                SVC_Handler
+ .text.DebugMon_Handler
+                0x08001738        0x2 build/stm32g4xx_it.o
+                0x08001738                DebugMon_Handler
+ .text.PendSV_Handler
+                0x0800173a        0x2 build/stm32g4xx_it.o
+                0x0800173a                PendSV_Handler
+ .text.SysTick_Handler
+                0x0800173c        0x8 build/stm32g4xx_it.o
+                0x0800173c                SysTick_Handler
+ .text.USB_LP_IRQHandler
+                0x08001744       0x10 build/stm32g4xx_it.o
+                0x08001744                USB_LP_IRQHandler
+ .text.TIM3_IRQHandler
+                0x08001754       0x10 build/stm32g4xx_it.o
+                0x08001754                TIM3_IRQHandler
+ .text.HAL_MspInit
+                0x08001764       0x38 build/stm32g4xx_hal_msp.o
+                0x08001764                HAL_MspInit
+ .text.HAL_ADC_MspInit
+                0x0800179c      0x10c build/stm32g4xx_hal_msp.o
+                0x0800179c                HAL_ADC_MspInit
+ .text.HAL_I2C_MspInit
+                0x080018a8       0xb4 build/stm32g4xx_hal_msp.o
+                0x080018a8                HAL_I2C_MspInit
+ .text.HAL_TIM_Base_MspInit
+                0x0800195c       0x60 build/stm32g4xx_hal_msp.o
+                0x0800195c                HAL_TIM_Base_MspInit
+ .text.HAL_TIM_MspPostInit
+                0x080019bc       0x4c build/stm32g4xx_hal_msp.o
+                0x080019bc                HAL_TIM_MspPostInit
+ .text.HAL_UART_MspInit
+                0x08001a08       0x88 build/stm32g4xx_hal_msp.o
+                0x08001a08                HAL_UART_MspInit
+ .text.HAL_InitTick
+                0x08001a90       0x50 build/stm32g4xx_hal.o
+                0x08001a90                HAL_InitTick
+ .text.HAL_Init
+                0x08001ae0       0x1e build/stm32g4xx_hal.o
+                0x08001ae0                HAL_Init
+ *fill*         0x08001afe        0x2 
+ .text.HAL_IncTick
+                0x08001b00       0x18 build/stm32g4xx_hal.o
+                0x08001b00                HAL_IncTick
+ .text.HAL_GetTick
+                0x08001b18        0xc build/stm32g4xx_hal.o
+                0x08001b18                HAL_GetTick
+ .text.HAL_Delay
+                0x08001b24       0x28 build/stm32g4xx_hal.o
+                0x08001b24                HAL_Delay
+ .text.RCC_GetSysClockFreqFromPLLSource
+                0x08001b4c       0x58 build/stm32g4xx_hal_rcc.o
+ .text.HAL_RCC_OscConfig
+                0x08001ba4      0x4e8 build/stm32g4xx_hal_rcc.o
+                0x08001ba4                HAL_RCC_OscConfig
+ .text.HAL_RCC_MCOConfig
+                0x0800208c       0x5c build/stm32g4xx_hal_rcc.o
+                0x0800208c                HAL_RCC_MCOConfig
+ .text.HAL_RCC_GetSysClockFreq
+                0x080020e8       0x88 build/stm32g4xx_hal_rcc.o
+                0x080020e8                HAL_RCC_GetSysClockFreq
+ .text.HAL_RCC_ClockConfig
+                0x08002170      0x1f8 build/stm32g4xx_hal_rcc.o
+                0x08002170                HAL_RCC_ClockConfig
+ .text.HAL_RCC_GetHCLKFreq
+                0x08002368        0xc build/stm32g4xx_hal_rcc.o
+                0x08002368                HAL_RCC_GetHCLKFreq
+ .text.HAL_RCC_GetPCLK1Freq
+                0x08002374       0x24 build/stm32g4xx_hal_rcc.o
+                0x08002374                HAL_RCC_GetPCLK1Freq
+ .text.HAL_RCC_GetPCLK2Freq
+                0x08002398       0x24 build/stm32g4xx_hal_rcc.o
+                0x08002398                HAL_RCC_GetPCLK2Freq
+ .text.HAL_RCCEx_PeriphCLKConfig
+                0x080023bc      0x2e4 build/stm32g4xx_hal_rcc_ex.o
+                0x080023bc                HAL_RCCEx_PeriphCLKConfig
+ .text.HAL_GPIO_Init
+                0x080026a0      0x1d4 build/stm32g4xx_hal_gpio.o
+                0x080026a0                HAL_GPIO_Init
+ .text.HAL_PWREx_ControlVoltageScaling
+                0x08002874      0x10c build/stm32g4xx_hal_pwr_ex.o
+                0x08002874                HAL_PWREx_ControlVoltageScaling
+ .text.HAL_PWREx_DisableUCPDDeadBattery
+                0x08002980       0x10 build/stm32g4xx_hal_pwr_ex.o
+                0x08002980                HAL_PWREx_DisableUCPDDeadBattery
+ .text.__NVIC_EnableIRQ
+                0x08002990       0x1c build/stm32g4xx_hal_cortex.o
+ .text.__NVIC_SetPriority
+                0x080029ac       0x28 build/stm32g4xx_hal_cortex.o
+ .text.NVIC_EncodePriority
+                0x080029d4       0x3e build/stm32g4xx_hal_cortex.o
+ *fill*         0x08002a12        0x2 
+ .text.HAL_NVIC_SetPriorityGrouping
+                0x08002a14       0x24 build/stm32g4xx_hal_cortex.o
+                0x08002a14                HAL_NVIC_SetPriorityGrouping
+ .text.HAL_NVIC_SetPriority
+                0x08002a38       0x20 build/stm32g4xx_hal_cortex.o
+                0x08002a38                HAL_NVIC_SetPriority
+ .text.HAL_NVIC_EnableIRQ
+                0x08002a58        0x8 build/stm32g4xx_hal_cortex.o
+                0x08002a58                HAL_NVIC_EnableIRQ
+ .text.HAL_SYSTICK_Config
+                0x08002a60       0x28 build/stm32g4xx_hal_cortex.o
+                0x08002a60                HAL_SYSTICK_Config
+ .text.LL_ADC_REG_SetSequencerRanks
+                0x08002a88       0x30 build/stm32g4xx_hal_adc.o
+ .text.LL_ADC_SetChannelSamplingTime
+                0x08002ab8       0x2c build/stm32g4xx_hal_adc.o
+ .text.HAL_ADC_Init
+                0x08002ae4      0x240 build/stm32g4xx_hal_adc.o
+                0x08002ae4                HAL_ADC_Init
+ .text.HAL_ADC_ConfigChannel
+                0x08002d24      0x464 build/stm32g4xx_hal_adc.o
+                0x08002d24                HAL_ADC_ConfigChannel
+ .text.HAL_ADCEx_MultiModeConfigChannel
+                0x08003188      0x114 build/stm32g4xx_hal_adc_ex.o
+                0x08003188                HAL_ADCEx_MultiModeConfigChannel
+ .text.I2C_Flush_TXDR
+                0x0800329c       0x22 build/stm32g4xx_hal_i2c.o
+ .text.I2C_TransferConfig
+                0x080032be       0x3c build/stm32g4xx_hal_i2c.o
+ .text.I2C_IsErrorOccurred
+                0x080032fa      0x12c build/stm32g4xx_hal_i2c.o
+ .text.I2C_WaitOnTXISFlagUntilTimeout
+                0x08003426       0x56 build/stm32g4xx_hal_i2c.o
+ .text.I2C_WaitOnFlagUntilTimeout
+                0x0800347c       0x56 build/stm32g4xx_hal_i2c.o
+ *fill*         0x080034d2        0x2 
+ .text.I2C_RequestMemoryWrite
+                0x080034d4       0x7c build/stm32g4xx_hal_i2c.o
+ .text.I2C_RequestMemoryRead
+                0x08003550       0x78 build/stm32g4xx_hal_i2c.o
+ .text.I2C_WaitOnSTOPFlagUntilTimeout
+                0x080035c8       0x50 build/stm32g4xx_hal_i2c.o
+ .text.HAL_I2C_Init
+                0x08003618       0xbc build/stm32g4xx_hal_i2c.o
+                0x08003618                HAL_I2C_Init
+ .text.HAL_I2C_Mem_Write
+                0x080036d4      0x1a8 build/stm32g4xx_hal_i2c.o
+                0x080036d4                HAL_I2C_Mem_Write
+ .text.HAL_I2C_Mem_Read
+                0x0800387c      0x1b0 build/stm32g4xx_hal_i2c.o
+                0x0800387c                HAL_I2C_Mem_Read
+ .text.HAL_I2C_IsDeviceReady
+                0x08003a2c      0x16c build/stm32g4xx_hal_i2c.o
+                0x08003a2c                HAL_I2C_IsDeviceReady
+ .text.HAL_I2CEx_ConfigAnalogFilter
+                0x08003b98       0x5c build/stm32g4xx_hal_i2c_ex.o
+                0x08003b98                HAL_I2CEx_ConfigAnalogFilter
+ .text.HAL_I2CEx_ConfigDigitalFilter
+                0x08003bf4       0x58 build/stm32g4xx_hal_i2c_ex.o
+                0x08003bf4                HAL_I2CEx_ConfigDigitalFilter
+ .text.TIM_OC1_SetConfig
+                0x08003c4c       0x9c build/stm32g4xx_hal_tim.o
+ .text.TIM_OC3_SetConfig
+                0x08003ce8       0x8c build/stm32g4xx_hal_tim.o
+ .text.TIM_OC4_SetConfig
+                0x08003d74       0x8c build/stm32g4xx_hal_tim.o
+ .text.TIM_OC5_SetConfig
+                0x08003e00       0x68 build/stm32g4xx_hal_tim.o
+ .text.TIM_OC6_SetConfig
+                0x08003e68       0x6c build/stm32g4xx_hal_tim.o
+ .text.TIM_TI1_ConfigInputStage
+                0x08003ed4       0x26 build/stm32g4xx_hal_tim.o
+ .text.TIM_TI2_ConfigInputStage
+                0x08003efa       0x28 build/stm32g4xx_hal_tim.o
+ .text.TIM_ITRx_SetConfig
+                0x08003f22       0x14 build/stm32g4xx_hal_tim.o
+ *fill*         0x08003f36        0x2 
+ .text.HAL_TIM_Base_Start_IT
+                0x08003f38       0x84 build/stm32g4xx_hal_tim.o
+                0x08003f38                HAL_TIM_Base_Start_IT
+ .text.HAL_TIM_PWM_MspInit
+                0x08003fbc        0x2 build/stm32g4xx_hal_tim.o
+                0x08003fbc                HAL_TIM_PWM_MspInit
+ .text.HAL_TIM_PeriodElapsedCallback
+                0x08003fbe        0x2 build/stm32g4xx_hal_tim.o
+                0x08003fbe                HAL_TIM_PeriodElapsedCallback
+ .text.HAL_TIM_OC_DelayElapsedCallback
+                0x08003fc0        0x2 build/stm32g4xx_hal_tim.o
+                0x08003fc0                HAL_TIM_OC_DelayElapsedCallback
+ .text.HAL_TIM_IC_CaptureCallback
+                0x08003fc2        0x2 build/stm32g4xx_hal_tim.o
+                0x08003fc2                HAL_TIM_IC_CaptureCallback
+ .text.HAL_TIM_PWM_PulseFinishedCallback
+                0x08003fc4        0x2 build/stm32g4xx_hal_tim.o
+                0x08003fc4                HAL_TIM_PWM_PulseFinishedCallback
+ .text.HAL_TIM_TriggerCallback
+                0x08003fc6        0x2 build/stm32g4xx_hal_tim.o
+                0x08003fc6                HAL_TIM_TriggerCallback
+ .text.HAL_TIM_IRQHandler
+                0x08003fc8      0x21e build/stm32g4xx_hal_tim.o
+                0x08003fc8                HAL_TIM_IRQHandler
+ *fill*         0x080041e6        0x2 
+ .text.TIM_Base_SetConfig
+                0x080041e8       0xb8 build/stm32g4xx_hal_tim.o
+                0x080041e8                TIM_Base_SetConfig
+ .text.HAL_TIM_Base_Init
+                0x080042a0       0x60 build/stm32g4xx_hal_tim.o
+                0x080042a0                HAL_TIM_Base_Init
+ .text.HAL_TIM_PWM_Init
+                0x08004300       0x60 build/stm32g4xx_hal_tim.o
+                0x08004300                HAL_TIM_PWM_Init
+ .text.TIM_OC2_SetConfig
+                0x08004360       0x8c build/stm32g4xx_hal_tim.o
+                0x08004360                TIM_OC2_SetConfig
+ .text.HAL_TIM_PWM_ConfigChannel
+                0x080043ec      0x13a build/stm32g4xx_hal_tim.o
+                0x080043ec                HAL_TIM_PWM_ConfigChannel
+ .text.TIM_ETR_SetConfig
+                0x08004526       0x1a build/stm32g4xx_hal_tim.o
+                0x08004526                TIM_ETR_SetConfig
+ .text.HAL_TIM_ConfigClockSource
+                0x08004540      0x138 build/stm32g4xx_hal_tim.o
+                0x08004540                HAL_TIM_ConfigClockSource
+ .text.TIM_CCxChannelCmd
+                0x08004678       0x1e build/stm32g4xx_hal_tim.o
+                0x08004678                TIM_CCxChannelCmd
+ *fill*         0x08004696        0x2 
+ .text.HAL_TIM_PWM_Start
+                0x08004698      0x160 build/stm32g4xx_hal_tim.o
+                0x08004698                HAL_TIM_PWM_Start
+ .text.HAL_TIMEx_MasterConfigSynchronization
+                0x080047f8       0x94 build/stm32g4xx_hal_tim_ex.o
+                0x080047f8                HAL_TIMEx_MasterConfigSynchronization
+ .text.HAL_TIMEx_CommutCallback
+                0x0800488c        0x2 build/stm32g4xx_hal_tim_ex.o
+                0x0800488c                HAL_TIMEx_CommutCallback
+ .text.HAL_TIMEx_BreakCallback
+                0x0800488e        0x2 build/stm32g4xx_hal_tim_ex.o
+                0x0800488e                HAL_TIMEx_BreakCallback
+ .text.HAL_TIMEx_Break2Callback
+                0x08004890        0x2 build/stm32g4xx_hal_tim_ex.o
+                0x08004890                HAL_TIMEx_Break2Callback
+ .text.HAL_TIMEx_EncoderIndexCallback
+                0x08004892        0x2 build/stm32g4xx_hal_tim_ex.o
+                0x08004892                HAL_TIMEx_EncoderIndexCallback
+ .text.HAL_TIMEx_DirectionChangeCallback
+                0x08004894        0x2 build/stm32g4xx_hal_tim_ex.o
+                0x08004894                HAL_TIMEx_DirectionChangeCallback
+ .text.HAL_TIMEx_IndexErrorCallback
+                0x08004896        0x2 build/stm32g4xx_hal_tim_ex.o
+                0x08004896                HAL_TIMEx_IndexErrorCallback
+ .text.HAL_TIMEx_TransitionErrorCallback
+                0x08004898        0x2 build/stm32g4xx_hal_tim_ex.o
+                0x08004898                HAL_TIMEx_TransitionErrorCallback
+ *fill*         0x0800489a        0x2 
+ .text.UART_SetConfig
+                0x0800489c      0x344 build/stm32g4xx_hal_uart.o
+                0x0800489c                UART_SetConfig
+ .text.UART_AdvFeatureConfig
+                0x08004be0       0xca build/stm32g4xx_hal_uart.o
+                0x08004be0                UART_AdvFeatureConfig
+ .text.UART_WaitOnFlagUntilTimeout
+                0x08004caa       0xd8 build/stm32g4xx_hal_uart.o
+                0x08004caa                UART_WaitOnFlagUntilTimeout
+ .text.UART_CheckIdleState
+                0x08004d82       0x74 build/stm32g4xx_hal_uart.o
+                0x08004d82                UART_CheckIdleState
+ .text.HAL_UART_Init
+                0x08004df6       0x66 build/stm32g4xx_hal_uart.o
+                0x08004df6                HAL_UART_Init
+ .text.UARTEx_SetNbDataToProcess
+                0x08004e5c       0x4c build/stm32g4xx_hal_uart_ex.o
+ .text.HAL_UARTEx_DisableFifoMode
+                0x08004ea8       0x3e build/stm32g4xx_hal_uart_ex.o
+                0x08004ea8                HAL_UARTEx_DisableFifoMode
+ .text.HAL_UARTEx_SetTxFifoThreshold
+                0x08004ee6       0x4a build/stm32g4xx_hal_uart_ex.o
+                0x08004ee6                HAL_UARTEx_SetTxFifoThreshold
+ .text.HAL_UARTEx_SetRxFifoThreshold
+                0x08004f30       0x4a build/stm32g4xx_hal_uart_ex.o
+                0x08004f30                HAL_UARTEx_SetRxFifoThreshold
+ *fill*         0x08004f7a        0x2 
+ .text.SystemInit
+                0x08004f7c       0x14 build/system_stm32g4xx.o
+                0x08004f7c                SystemInit
+ .text.MX_USB_Device_Init
+                0x08004f90       0x54 build/usb_device.o
+                0x08004f90                MX_USB_Device_Init
+ .text.USBD_Get_USB_Status
+                0x08004fe4       0x14 build/usbd_conf.o
+ .text.SystemClockConfig_Resume
+                0x08004ff8        0x8 build/usbd_conf.o
+ .text.HAL_PCD_MspInit
+                0x08005000       0x60 build/usbd_conf.o
+                0x08005000                HAL_PCD_MspInit
+ .text.HAL_PCD_SetupStageCallback
+                0x08005060       0x10 build/usbd_conf.o
+                0x08005060                HAL_PCD_SetupStageCallback
+ .text.HAL_PCD_DataOutStageCallback
+                0x08005070       0x18 build/usbd_conf.o
+                0x08005070                HAL_PCD_DataOutStageCallback
+ .text.HAL_PCD_DataInStageCallback
+                0x08005088       0x16 build/usbd_conf.o
+                0x08005088                HAL_PCD_DataInStageCallback
+ .text.HAL_PCD_SOFCallback
+                0x0800509e        0xc build/usbd_conf.o
+                0x0800509e                HAL_PCD_SOFCallback
+ .text.HAL_PCD_ResetCallback
+                0x080050aa       0x24 build/usbd_conf.o
+                0x080050aa                HAL_PCD_ResetCallback
+ *fill*         0x080050ce        0x2 
+ .text.HAL_PCD_SuspendCallback
+                0x080050d0       0x20 build/usbd_conf.o
+                0x080050d0                HAL_PCD_SuspendCallback
+ .text.HAL_PCD_ResumeCallback
+                0x080050f0       0x28 build/usbd_conf.o
+                0x080050f0                HAL_PCD_ResumeCallback
+ .text.USBD_LL_Init
+                0x08005118       0x6c build/usbd_conf.o
+                0x08005118                USBD_LL_Init
+ .text.USBD_LL_Start
+                0x08005184       0x10 build/usbd_conf.o
+                0x08005184                USBD_LL_Start
+ .text.USBD_LL_OpenEP
+                0x08005194       0x16 build/usbd_conf.o
+                0x08005194                USBD_LL_OpenEP
+ .text.USBD_LL_CloseEP
+                0x080051aa       0x10 build/usbd_conf.o
+                0x080051aa                USBD_LL_CloseEP
+ .text.USBD_LL_StallEP
+                0x080051ba       0x10 build/usbd_conf.o
+                0x080051ba                USBD_LL_StallEP
+ .text.USBD_LL_ClearStallEP
+                0x080051ca       0x10 build/usbd_conf.o
+                0x080051ca                USBD_LL_ClearStallEP
+ .text.USBD_LL_IsStallEP
+                0x080051da       0x2e build/usbd_conf.o
+                0x080051da                USBD_LL_IsStallEP
+ .text.USBD_LL_SetUSBAddress
+                0x08005208       0x10 build/usbd_conf.o
+                0x08005208                USBD_LL_SetUSBAddress
+ .text.USBD_LL_Transmit
+                0x08005218       0x10 build/usbd_conf.o
+                0x08005218                USBD_LL_Transmit
+ .text.USBD_LL_PrepareReceive
+                0x08005228       0x10 build/usbd_conf.o
+                0x08005228                USBD_LL_PrepareReceive
+ .text.USBD_LL_GetRxDataSize
+                0x08005238        0xc build/usbd_conf.o
+                0x08005238                USBD_LL_GetRxDataSize
+ .text.HAL_PCDEx_LPM_Callback
+                0x08005244       0x48 build/usbd_conf.o
+                0x08005244                HAL_PCDEx_LPM_Callback
+ .text.USBD_static_malloc
+                0x0800528c        0x8 build/usbd_conf.o
+                0x0800528c                USBD_static_malloc
+ .text.USBD_static_free
+                0x08005294        0x2 build/usbd_conf.o
+                0x08005294                USBD_static_free
+ *fill*         0x08005296        0x2 
+ .text.USBD_AUDIO_DeviceDescriptor
+                0x08005298        0xc build/usbd_desc.o
+                0x08005298                USBD_AUDIO_DeviceDescriptor
+ .text.USBD_AUDIO_LangIDStrDescriptor
+                0x080052a4        0xc build/usbd_desc.o
+                0x080052a4                USBD_AUDIO_LangIDStrDescriptor
+ .text.IntToUnicode
+                0x080052b0       0x46 build/usbd_desc.o
+ *fill*         0x080052f6        0x2 
+ .text.Get_SerialNum
+                0x080052f8       0x38 build/usbd_desc.o
+ .text.USBD_AUDIO_SerialStrDescriptor
+                0x08005330       0x14 build/usbd_desc.o
+                0x08005330                USBD_AUDIO_SerialStrDescriptor
+ .text.USBD_AUDIO_ProductStrDescriptor
+                0x08005344       0x24 build/usbd_desc.o
+                0x08005344                USBD_AUDIO_ProductStrDescriptor
+ .text.USBD_AUDIO_ManufacturerStrDescriptor
+                0x08005368       0x1c build/usbd_desc.o
+                0x08005368                USBD_AUDIO_ManufacturerStrDescriptor
+ .text.USBD_AUDIO_ConfigStrDescriptor
+                0x08005384       0x24 build/usbd_desc.o
+                0x08005384                USBD_AUDIO_ConfigStrDescriptor
+ .text.USBD_AUDIO_InterfaceStrDescriptor
+                0x080053a8       0x24 build/usbd_desc.o
+                0x080053a8                USBD_AUDIO_InterfaceStrDescriptor
+ .text.AUDIO_Init_FS
+                0x080053cc        0x4 build/usbd_audio_if.o
+ .text.AUDIO_DeInit_FS
+                0x080053d0        0x4 build/usbd_audio_if.o
+ .text.AUDIO_AudioCmd_FS
+                0x080053d4        0x4 build/usbd_audio_if.o
+ .text.AUDIO_VolumeCtl_FS
+                0x080053d8        0x4 build/usbd_audio_if.o
+ .text.AUDIO_MuteCtl_FS
+                0x080053dc        0x4 build/usbd_audio_if.o
+ .text.AUDIO_PeriodicTC_FS
+                0x080053e0        0x4 build/usbd_audio_if.o
+ .text.AUDIO_GetState_FS
+                0x080053e4        0x4 build/usbd_audio_if.o
+ .text.HAL_PCD_EP_DB_Receive
+                0x080053e8      0x118 build/stm32g4xx_hal_pcd.o
+ .text.HAL_PCD_Init
+                0x08005500       0xe4 build/stm32g4xx_hal_pcd.o
+                0x08005500                HAL_PCD_Init
+ .text.HAL_PCD_Start
+                0x080055e4       0x2a build/stm32g4xx_hal_pcd.o
+                0x080055e4                HAL_PCD_Start
+ .text.HAL_PCD_EP_DB_Transmit
+                0x0800560e      0x410 build/stm32g4xx_hal_pcd.o
+ .text.PCD_EP_ISR_Handler
+                0x08005a1e      0x516 build/stm32g4xx_hal_pcd.o
+ .text.HAL_PCD_SetAddress
+                0x08005f34       0x28 build/stm32g4xx_hal_pcd.o
+                0x08005f34                HAL_PCD_SetAddress
+ .text.HAL_PCD_IRQHandler
+                0x08005f5c      0x1b2 build/stm32g4xx_hal_pcd.o
+                0x08005f5c                HAL_PCD_IRQHandler
+ .text.HAL_PCD_EP_Open
+                0x0800610e       0x84 build/stm32g4xx_hal_pcd.o
+                0x0800610e                HAL_PCD_EP_Open
+ .text.HAL_PCD_EP_Close
+                0x08006192       0x64 build/stm32g4xx_hal_pcd.o
+                0x08006192                HAL_PCD_EP_Close
+ .text.HAL_PCD_EP_Receive
+                0x080061f6       0x44 build/stm32g4xx_hal_pcd.o
+                0x080061f6                HAL_PCD_EP_Receive
+ .text.HAL_PCD_EP_GetRxCount
+                0x0800623a       0x12 build/stm32g4xx_hal_pcd.o
+                0x0800623a                HAL_PCD_EP_GetRxCount
+ .text.HAL_PCD_EP_Transmit
+                0x0800624c       0x50 build/stm32g4xx_hal_pcd.o
+                0x0800624c                HAL_PCD_EP_Transmit
+ .text.HAL_PCD_EP_SetStall
+                0x0800629c       0x6a build/stm32g4xx_hal_pcd.o
+                0x0800629c                HAL_PCD_EP_SetStall
+ .text.HAL_PCD_EP_ClrStall
+                0x08006306       0x76 build/stm32g4xx_hal_pcd.o
+                0x08006306                HAL_PCD_EP_ClrStall
+ .text.HAL_PCDEx_PMAConfig
+                0x0800637c       0x38 build/stm32g4xx_hal_pcd_ex.o
+                0x0800637c                HAL_PCDEx_PMAConfig
+ .text.HAL_PCDEx_ActivateLPM
+                0x080063b4       0x2c build/stm32g4xx_hal_pcd_ex.o
+                0x080063b4                HAL_PCDEx_ActivateLPM
+ .text.USB_EnableGlobalInt
+                0x080063e0       0x12 build/stm32g4xx_ll_usb.o
+                0x080063e0                USB_EnableGlobalInt
+ .text.USB_DisableGlobalInt
+                0x080063f2       0x14 build/stm32g4xx_ll_usb.o
+                0x080063f2                USB_DisableGlobalInt
+ .text.USB_DevInit
+                0x08006406       0x22 build/stm32g4xx_ll_usb.o
+                0x08006406                USB_DevInit
+ .text.USB_ActivateEndpoint
+                0x08006428      0x396 build/stm32g4xx_ll_usb.o
+                0x08006428                USB_ActivateEndpoint
+ .text.USB_DeactivateEndpoint
+                0x080067be      0x1d6 build/stm32g4xx_ll_usb.o
+                0x080067be                USB_DeactivateEndpoint
+ .text.USB_EPSetStall
+                0x08006994       0x4a build/stm32g4xx_ll_usb.o
+                0x08006994                USB_EPSetStall
+ .text.USB_EPClearStall
+                0x080069de       0xa2 build/stm32g4xx_ll_usb.o
+                0x080069de                USB_EPClearStall
+ .text.USB_SetDevAddress
+                0x08006a80        0xc build/stm32g4xx_ll_usb.o
+                0x08006a80                USB_SetDevAddress
+ .text.USB_DevConnect
+                0x08006a8c       0x16 build/stm32g4xx_ll_usb.o
+                0x08006a8c                USB_DevConnect
+ .text.USB_ReadInterrupts
+                0x08006aa2        0x8 build/stm32g4xx_ll_usb.o
+                0x08006aa2                USB_ReadInterrupts
+ .text.USB_WritePMA
+                0x08006aaa       0x24 build/stm32g4xx_ll_usb.o
+                0x08006aaa                USB_WritePMA
+ .text.USB_EPStartXfer
+                0x08006ace      0x760 build/stm32g4xx_ll_usb.o
+                0x08006ace                USB_EPStartXfer
+ .text.USB_ReadPMA
+                0x0800722e       0x30 build/stm32g4xx_ll_usb.o
+                0x0800722e                USB_ReadPMA
+ .text.USBD_Init
+                0x0800725e       0x2e build/usbd_core.o
+                0x0800725e                USBD_Init
+ .text.USBD_RegisterClass
+                0x0800728c       0x2e build/usbd_core.o
+                0x0800728c                USBD_RegisterClass
+ .text.USBD_Start
+                0x080072ba        0x8 build/usbd_core.o
+                0x080072ba                USBD_Start
+ .text.USBD_SetClassConfig
+                0x080072c2       0x12 build/usbd_core.o
+                0x080072c2                USBD_SetClassConfig
+ .text.USBD_ClrClassConfig
+                0x080072d4       0x10 build/usbd_core.o
+                0x080072d4                USBD_ClrClassConfig
+ .text.USBD_LL_SetupStage
+                0x080072e4       0x58 build/usbd_core.o
+                0x080072e4                USBD_LL_SetupStage
+ .text.USBD_LL_DataOutStage
+                0x0800733c       0x78 build/usbd_core.o
+                0x0800733c                USBD_LL_DataOutStage
+ .text.USBD_LL_DataInStage
+                0x080073b4       0xbe build/usbd_core.o
+                0x080073b4                USBD_LL_DataInStage
+ .text.USBD_LL_Reset
+                0x08007472       0x5a build/usbd_core.o
+                0x08007472                USBD_LL_Reset
+ .text.USBD_LL_SetSpeed
+                0x080074cc        0x6 build/usbd_core.o
+                0x080074cc                USBD_LL_SetSpeed
+ .text.USBD_LL_Suspend
+                0x080074d2       0x14 build/usbd_core.o
+                0x080074d2                USBD_LL_Suspend
+ .text.USBD_LL_Resume
+                0x080074e6       0x1a build/usbd_core.o
+                0x080074e6                USBD_LL_Resume
+ .text.USBD_LL_SOF
+                0x08007500       0x28 build/usbd_core.o
+                0x08007500                USBD_LL_SOF
+ .text.USBD_GetLen
+                0x08007528       0x14 build/usbd_ctlreq.o
+ .text.USBD_SetFeature
+                0x0800753c       0x14 build/usbd_ctlreq.o
+ .text.USBD_ParseSetupRequest
+                0x08007550       0x28 build/usbd_ctlreq.o
+                0x08007550                USBD_ParseSetupRequest
+ .text.USBD_CtlError
+                0x08007578       0x14 build/usbd_ctlreq.o
+                0x08007578                USBD_CtlError
+ .text.USBD_GetDescriptor
+                0x0800758c      0x1ac build/usbd_ctlreq.o
+ .text.USBD_SetAddress
+                0x08007738       0x50 build/usbd_ctlreq.o
+ .text.USBD_SetConfig
+                0x08007788       0xc8 build/usbd_ctlreq.o
+ .text.USBD_GetConfig
+                0x08007850       0x40 build/usbd_ctlreq.o
+ .text.USBD_GetStatus
+                0x08007890       0x38 build/usbd_ctlreq.o
+ .text.USBD_ClrFeature
+                0x080078c8       0x26 build/usbd_ctlreq.o
+ .text.USBD_StdDevReq
+                0x080078ee       0x70 build/usbd_ctlreq.o
+                0x080078ee                USBD_StdDevReq
+ .text.USBD_StdItfReq
+                0x0800795e       0x68 build/usbd_ctlreq.o
+                0x0800795e                USBD_StdItfReq
+ .text.USBD_StdEPReq
+                0x080079c6      0x1ec build/usbd_ctlreq.o
+                0x080079c6                USBD_StdEPReq
+ .text.USBD_GetString
+                0x08007bb2       0x3a build/usbd_ctlreq.o
+                0x08007bb2                USBD_GetString
+ .text.USBD_CtlSendData
+                0x08007bec       0x1a build/usbd_ioreq.o
+                0x08007bec                USBD_CtlSendData
+ .text.USBD_CtlContinueSendData
+                0x08007c06       0x10 build/usbd_ioreq.o
+                0x08007c06                USBD_CtlContinueSendData
+ .text.USBD_CtlPrepareRx
+                0x08007c16       0x1e build/usbd_ioreq.o
+                0x08007c16                USBD_CtlPrepareRx
+ .text.USBD_CtlContinueRx
+                0x08007c34       0x10 build/usbd_ioreq.o
+                0x08007c34                USBD_CtlContinueRx
+ .text.USBD_CtlSendStatus
+                0x08007c44       0x16 build/usbd_ioreq.o
+                0x08007c44                USBD_CtlSendStatus
+ .text.USBD_CtlReceiveStatus
+                0x08007c5a       0x16 build/usbd_ioreq.o
+                0x08007c5a                USBD_CtlReceiveStatus
+ .text.USBD_AUDIO_GetCfgDesc
+                0x08007c70        0xc build/usbd_audio.o
+ .text.USBD_AUDIO_DataIn
+                0x08007c7c        0x4 build/usbd_audio.o
+ .text.USBD_AUDIO_EP0_RxReady
+                0x08007c80       0x48 build/usbd_audio.o
+ .text.USBD_AUDIO_EP0_TxReady
+                0x08007cc8        0x4 build/usbd_audio.o
+ .text.USBD_AUDIO_SOF
+                0x08007ccc        0x4 build/usbd_audio.o
+ .text.USBD_AUDIO_IsoINIncomplete
+                0x08007cd0        0x4 build/usbd_audio.o
+ .text.USBD_AUDIO_IsoOutIncomplete
+                0x08007cd4        0x4 build/usbd_audio.o
+ .text.USBD_AUDIO_GetDeviceQualifierDesc
+                0x08007cd8        0xc build/usbd_audio.o
+ .text.USBD_AUDIO_DataOut
+                0x08007ce4       0xac build/usbd_audio.o
+ .text.AUDIO_REQ_GetCurrent
+                0x08007d90       0x28 build/usbd_audio.o
+ .text.AUDIO_REQ_SetCurrent
+                0x08007db8       0x34 build/usbd_audio.o
+ .text.USBD_AUDIO_Setup
+                0x08007dec       0xec build/usbd_audio.o
+ .text.USBD_AUDIO_DeInit
+                0x08007ed8       0x36 build/usbd_audio.o
+ .text.USBD_AUDIO_Init
+                0x08007f0e       0x80 build/usbd_audio.o
+ .text.USBD_AUDIO_RegisterInterface
+                0x08007f8e        0xe build/usbd_audio.o
+                0x08007f8e                USBD_AUDIO_RegisterInterface
+ .text.Reset_Handler
+                0x08007f9c       0x50 build/startup_stm32g431xx.o
+                0x08007f9c                Reset_Handler
+ .text.Default_Handler
+                0x08007fec        0x2 build/startup_stm32g431xx.o
+                0x08007fec                RTC_Alarm_IRQHandler
+                0x08007fec                EXTI2_IRQHandler
+                0x08007fec                TIM8_TRG_COM_IRQHandler
+                0x08007fec                TIM8_CC_IRQHandler
+                0x08007fec                TIM1_CC_IRQHandler
+                0x08007fec                USB_HP_IRQHandler
+                0x08007fec                CORDIC_IRQHandler
+                0x08007fec                EXTI3_IRQHandler
+                0x08007fec                I2C3_ER_IRQHandler
+                0x08007fec                EXTI0_IRQHandler
+                0x08007fec                I2C2_EV_IRQHandler
+                0x08007fec                FPU_IRQHandler
+                0x08007fec                FDCAN1_IT1_IRQHandler
+                0x08007fec                TIM1_UP_TIM16_IRQHandler
+                0x08007fec                ADC1_2_IRQHandler
+                0x08007fec                SPI1_IRQHandler
+                0x08007fec                TIM6_DAC_IRQHandler
+                0x08007fec                TIM8_UP_IRQHandler
+                0x08007fec                DMA2_Channel2_IRQHandler
+                0x08007fec                DMA1_Channel4_IRQHandler
+                0x08007fec                USART3_IRQHandler
+                0x08007fec                TIM4_IRQHandler
+                0x08007fec                DMA2_Channel1_IRQHandler
+                0x08007fec                I2C1_EV_IRQHandler
+                0x08007fec                DMA1_Channel6_IRQHandler
+                0x08007fec                UART4_IRQHandler
+                0x08007fec                DMA2_Channel4_IRQHandler
+                0x08007fec                RCC_IRQHandler
+                0x08007fec                DMA1_Channel1_IRQHandler
+                0x08007fec                Default_Handler
+                0x08007fec                RTC_TAMP_LSECSS_IRQHandler
+                0x08007fec                FMAC_IRQHandler
+                0x08007fec                EXTI15_10_IRQHandler
+                0x08007fec                TIM7_IRQHandler
+                0x08007fec                UCPD1_IRQHandler
+                0x08007fec                I2C3_EV_IRQHandler
+                0x08007fec                EXTI9_5_IRQHandler
+                0x08007fec                RTC_WKUP_IRQHandler
+                0x08007fec                PVD_PVM_IRQHandler
+                0x08007fec                SPI2_IRQHandler
+                0x08007fec                DMA2_Channel5_IRQHandler
+                0x08007fec                CRS_IRQHandler
+                0x08007fec                DMA1_Channel5_IRQHandler
+                0x08007fec                EXTI4_IRQHandler
+                0x08007fec                RNG_IRQHandler
+                0x08007fec                TIM1_TRG_COM_TIM17_IRQHandler
+                0x08007fec                DMA1_Channel3_IRQHandler
+                0x08007fec                WWDG_IRQHandler
+                0x08007fec                LPUART1_IRQHandler
+                0x08007fec                DMA2_Channel6_IRQHandler
+                0x08007fec                FDCAN1_IT0_IRQHandler
+                0x08007fec                TIM2_IRQHandler
+                0x08007fec                COMP1_2_3_IRQHandler
+                0x08007fec                EXTI1_IRQHandler
+                0x08007fec                USART2_IRQHandler
+                0x08007fec                I2C2_ER_IRQHandler
+                0x08007fec                DMA1_Channel2_IRQHandler
+                0x08007fec                TIM8_BRK_IRQHandler
+                0x08007fec                FLASH_IRQHandler
+                0x08007fec                USART1_IRQHandler
+                0x08007fec                SPI3_IRQHandler
+                0x08007fec                I2C1_ER_IRQHandler
+                0x08007fec                LPTIM1_IRQHandler
+                0x08007fec                DMAMUX_OVR_IRQHandler
+                0x08007fec                USBWakeUp_IRQHandler
+                0x08007fec                SAI1_IRQHandler
+                0x08007fec                DMA2_Channel3_IRQHandler
+                0x08007fec                COMP4_IRQHandler
+                0x08007fec                TIM1_BRK_TIM15_IRQHandler
+ *(.glue_7)
+ .glue_7        0x08007fee        0x0 linker stubs
+ *(.glue_7t)
+ .glue_7t       0x08007fee        0x0 linker stubs
+ *(.eh_frame)
+ *fill*         0x08007fee        0x2 
+ .eh_frame      0x08007ff0        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+ *(.init)
+ .init          0x08007ff0        0x4 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crti.o
+                0x08007ff0                _init
+ .init          0x08007ff4        0x8 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtn.o
+ *(.fini)
+ .fini          0x08007ffc        0x4 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crti.o
+                0x08007ffc                _fini
+ .fini          0x08008000        0x8 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtn.o
+                0x08008008                        . = ALIGN (0x4)
+                0x08008008                        _etext = .
+
+.vfp11_veneer   0x08008008        0x0
+ .vfp11_veneer  0x08008008        0x0 linker stubs
+
+.v4_bx          0x08008008        0x0
+ .v4_bx         0x08008008        0x0 linker stubs
+
+.iplt           0x08008008        0x0
+ .iplt          0x08008008        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+
+.rodata         0x08008008       0x88
+                0x08008008                        . = ALIGN (0x4)
+ *(.rodata)
+ *(.rodata*)
+ .rodata.UARTPrescTable
+                0x08008008       0x18 build/stm32g4xx_hal_uart.o
+                0x08008008                UARTPrescTable
+ .rodata.denominator.0
+                0x08008020        0x8 build/stm32g4xx_hal_uart_ex.o
+ .rodata.numerator.1
+                0x08008028        0x8 build/stm32g4xx_hal_uart_ex.o
+ .rodata.APBPrescTable
+                0x08008030        0x8 build/system_stm32g4xx.o
+                0x08008030                APBPrescTable
+ .rodata.AHBPrescTable
+                0x08008038       0x10 build/system_stm32g4xx.o
+                0x08008038                AHBPrescTable
+ .rodata.USBD_AUDIO_ProductStrDescriptor.str1.4
+                0x08008048       0x12 build/usbd_desc.o
+ *fill*         0x0800805a        0x2 
+ .rodata.USBD_AUDIO_ManufacturerStrDescriptor.str1.4
+                0x0800805c       0x13 build/usbd_desc.o
+ *fill*         0x0800806f        0x1 
+ .rodata.USBD_AUDIO_ConfigStrDescriptor.str1.4
+                0x08008070        0xd build/usbd_desc.o
+ *fill*         0x0800807d        0x3 
+ .rodata.USBD_AUDIO_InterfaceStrDescriptor.str1.4
+                0x08008080       0x10 build/usbd_desc.o
+                0x08008090                        . = ALIGN (0x4)
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM            0x08008090        0x8
+                0x08008090                        __exidx_start = .
+ *(.ARM.exidx*)
+ .ARM.exidx     0x08008090        0x8 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o)
+                0x08008098                        __exidx_end = .
+
+.rel.dyn        0x08008098        0x0
+ .rel.iplt      0x08008098        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+
+.preinit_array  0x08008098        0x0
+                0x08008098                        PROVIDE (__preinit_array_start = .)
+ *(.preinit_array*)
+                0x08008098                        PROVIDE (__preinit_array_end = .)
+
+.init_array     0x08008098        0x4
+                0x08008098                        PROVIDE (__init_array_start = .)
+ *(SORT_BY_NAME(.init_array.*))
+ *(.init_array*)
+ .init_array    0x08008098        0x4 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+                0x0800809c                        PROVIDE (__init_array_end = .)
+
+.fini_array     0x0800809c        0x4
+                0x0800809c                        PROVIDE (__fini_array_start = .)
+ *(SORT_BY_NAME(.fini_array.*))
+ *(.fini_array*)
+ .fini_array    0x0800809c        0x4 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+                0x080080a0                        PROVIDE (__fini_array_end = .)
+                0x080080a0                        _sidata = LOADADDR (.data)
+
+.data           0x20000000      0x130 load address 0x080080a0
+                0x20000000                        . = ALIGN (0x4)
+                0x20000000                        _sdata = .
+ *(.data)
+ *(.data*)
+ .data.uwTickFreq
+                0x20000000        0x4 build/stm32g4xx_hal.o
+                0x20000000                uwTickFreq
+ .data.uwTickPrio
+                0x20000004        0x4 build/stm32g4xx_hal.o
+                0x20000004                uwTickPrio
+ .data.SystemCoreClock
+                0x20000008        0x4 build/system_stm32g4xx.o
+                0x20000008                SystemCoreClock
+ .data.USBD_StringSerial
+                0x2000000c       0x1a build/usbd_desc.o
+                0x2000000c                USBD_StringSerial
+ *fill*         0x20000026        0x2 
+ .data.USBD_LangIDDesc
+                0x20000028        0x4 build/usbd_desc.o
+                0x20000028                USBD_LangIDDesc
+ .data.USBD_AUDIO_DeviceDesc
+                0x2000002c       0x12 build/usbd_desc.o
+                0x2000002c                USBD_AUDIO_DeviceDesc
+ *fill*         0x2000003e        0x2 
+ .data.AUDIO_Desc
+                0x20000040       0x20 build/usbd_desc.o
+                0x20000040                AUDIO_Desc
+ .data.USBD_AUDIO_fops_FS
+                0x20000060       0x1c build/usbd_audio_if.o
+                0x20000060                USBD_AUDIO_fops_FS
+ .data.USBD_AUDIO_DeviceQualifierDesc
+                0x2000007c        0xa build/usbd_audio.o
+ *fill*         0x20000086        0x2 
+ .data.USBD_AUDIO_CfgDesc
+                0x20000088       0x6d build/usbd_audio.o
+ *fill*         0x200000f5        0x3 
+ .data.USBD_AUDIO
+                0x200000f8       0x38 build/usbd_audio.o
+                0x200000f8                USBD_AUDIO
+                0x20000130                        . = ALIGN (0x4)
+                0x20000130                        _edata = .
+
+.tm_clone_table
+                0x20000130        0x0 load address 0x080081d0
+ .tm_clone_table
+                0x20000130        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+ .tm_clone_table
+                0x20000130        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtend.o
+
+.igot.plt       0x20000130        0x0 load address 0x080081d0
+ .igot.plt      0x20000130        0x0 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+                0x20000130                        . = ALIGN (0x4)
+
+.bss            0x20000130     0x2610 load address 0x080081d0
+                0x20000130                        _sbss = .
+                0x20000130                        __bss_start__ = _sbss
+ *(.bss)
+ .bss           0x20000130       0x1c /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+ *(.bss*)
+ .bss.huart1    0x2000014c       0x90 build/main.o
+                0x2000014c                huart1
+ .bss.htim3     0x200001dc       0x4c build/main.o
+                0x200001dc                htim3
+ .bss.htim2     0x20000228       0x4c build/main.o
+                0x20000228                htim2
+ .bss.hi2c1     0x20000274       0x4c build/main.o
+                0x20000274                hi2c1
+ .bss.hadc2     0x200002c0       0x6c build/main.o
+                0x200002c0                hadc2
+ .bss.hadc1     0x2000032c       0x6c build/main.o
+                0x2000032c                hadc1
+ .bss.oeb       0x20000398        0x1 build/si5351.o
+                0x20000398                oeb
+ *fill*         0x20000399        0x3 
+ .bss.HAL_RCC_ADC12_CLK_ENABLED
+                0x2000039c        0x4 build/stm32g4xx_hal_msp.o
+ .bss.uwTick    0x200003a0        0x4 build/stm32g4xx_hal.o
+                0x200003a0                uwTick
+ .bss.hUsbDeviceFS
+                0x200003a4      0x2d0 build/usb_device.o
+                0x200003a4                hUsbDeviceFS
+ .bss.mem.0     0x20000674     0x1bd4 build/usbd_conf.o
+ .bss.hpcd_USB_FS
+                0x20002248      0x2f4 build/usbd_conf.o
+                0x20002248                hpcd_USB_FS
+ .bss.USBD_StrDesc
+                0x2000253c      0x200 build/usbd_desc.o
+                0x2000253c                USBD_StrDesc
+ .bss.cfgidx.0  0x2000273c        0x1 build/usbd_ctlreq.o
+ *(COMMON)
+                0x20002740                        . = ALIGN (0x4)
+ *fill*         0x2000273d        0x3 
+                0x20002740                        _ebss = .
+                0x20002740                        __bss_end__ = _ebss
+
+._user_heap_stack
+                0x20002740      0x600 load address 0x080081d0
+                0x20002740                        . = ALIGN (0x8)
+                [!provide]                        PROVIDE (end = .)
+                [!provide]                        PROVIDE (_end = .)
+                0x20002940                        . = (. + _Min_Heap_Size)
+ *fill*         0x20002740      0x200 
+                0x20002d40                        . = (. + _Min_Stack_Size)
+ *fill*         0x20002940      0x400 
+                0x20002d40                        . = ALIGN (0x8)
+
+/DISCARD/
+ libc.a(*)
+ libm.a(*)
+ libgcc.a(*)
+
+.ARM.attributes
+                0x00000000       0x30
+ *(.ARM.attributes)
+ .ARM.attributes
+                0x00000000       0x22 /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crti.o
+ .ARM.attributes
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+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc.a
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a
+LOAD /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a
+
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+
+Cross Reference Table
+
+Symbol                                            File
+ADC1_2_IRQHandler                                 build/startup_stm32g431xx.o
+ADC_ConversionStop                                build/stm32g4xx_hal_adc.o
+                                                  build/stm32g4xx_hal_adc_ex.o
+ADC_DMAConvCplt                                   build/stm32g4xx_hal_adc.o
+                                                  build/stm32g4xx_hal_adc_ex.o
+ADC_DMAError                                      build/stm32g4xx_hal_adc.o
+                                                  build/stm32g4xx_hal_adc_ex.o
+ADC_DMAHalfConvCplt                               build/stm32g4xx_hal_adc.o
+                                                  build/stm32g4xx_hal_adc_ex.o
+ADC_Disable                                       build/stm32g4xx_hal_adc.o
+                                                  build/stm32g4xx_hal_adc_ex.o
+ADC_Enable                                        build/stm32g4xx_hal_adc.o
+                                                  build/stm32g4xx_hal_adc_ex.o
+AHBPrescTable                                     build/system_stm32g4xx.o
+                                                  build/stm32g4xx_hal_rcc.o
+APBPrescTable                                     build/system_stm32g4xx.o
+                                                  build/stm32g4xx_hal_rcc.o
+AUDIO_Desc                                        build/usbd_desc.o
+                                                  build/usb_device.o
+BusFault_Handler                                  build/stm32g4xx_it.o
+COMP1_2_3_IRQHandler                              build/startup_stm32g431xx.o
+COMP4_IRQHandler                                  build/startup_stm32g431xx.o
+CORDIC_IRQHandler                                 build/startup_stm32g431xx.o
+CRS_IRQHandler                                    build/startup_stm32g431xx.o
+CalcRegisters                                     build/si5351.o
+DMA1_Channel1_IRQHandler                          build/startup_stm32g431xx.o
+DMA1_Channel2_IRQHandler                          build/startup_stm32g431xx.o
+DMA1_Channel3_IRQHandler                          build/startup_stm32g431xx.o
+DMA1_Channel4_IRQHandler                          build/startup_stm32g431xx.o
+DMA1_Channel5_IRQHandler                          build/startup_stm32g431xx.o
+DMA1_Channel6_IRQHandler                          build/startup_stm32g431xx.o
+DMA2_Channel1_IRQHandler                          build/startup_stm32g431xx.o
+DMA2_Channel2_IRQHandler                          build/startup_stm32g431xx.o
+DMA2_Channel3_IRQHandler                          build/startup_stm32g431xx.o
+DMA2_Channel4_IRQHandler                          build/startup_stm32g431xx.o
+DMA2_Channel5_IRQHandler                          build/startup_stm32g431xx.o
+DMA2_Channel6_IRQHandler                          build/startup_stm32g431xx.o
+DMAMUX_OVR_IRQHandler                             build/startup_stm32g431xx.o
+DebugMon_Handler                                  build/stm32g4xx_it.o
+Default_Handler                                   build/startup_stm32g431xx.o
+EXTI0_IRQHandler                                  build/startup_stm32g431xx.o
+EXTI15_10_IRQHandler                              build/startup_stm32g431xx.o
+EXTI1_IRQHandler                                  build/startup_stm32g431xx.o
+EXTI2_IRQHandler                                  build/startup_stm32g431xx.o
+EXTI3_IRQHandler                                  build/startup_stm32g431xx.o
+EXTI4_IRQHandler                                  build/startup_stm32g431xx.o
+EXTI9_5_IRQHandler                                build/startup_stm32g431xx.o
+Error_Handler                                     build/main.o
+                                                  build/usbd_conf.o
+                                                  build/usb_device.o
+                                                  build/stm32g4xx_hal_msp.o
+FDCAN1_IT0_IRQHandler                             build/startup_stm32g431xx.o
+FDCAN1_IT1_IRQHandler                             build/startup_stm32g431xx.o
+FLASH_FlushCaches                                 build/stm32g4xx_hal_flash_ex.o
+                                                  build/stm32g4xx_hal_flash.o
+FLASH_IRQHandler                                  build/startup_stm32g431xx.o
+FLASH_PageErase                                   build/stm32g4xx_hal_flash_ex.o
+                                                  build/stm32g4xx_hal_flash.o
+FLASH_WaitForLastOperation                        build/stm32g4xx_hal_flash.o
+                                                  build/stm32g4xx_hal_flash_ex.o
+FMAC_IRQHandler                                   build/startup_stm32g431xx.o
+FPU_IRQHandler                                    build/startup_stm32g431xx.o
+HAL_ADCEx_Calibration_GetValue                    build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_Calibration_SetValue                    build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_Calibration_Start                       build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_DisableInjectedQueue                    build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_DisableVoltageRegulator                 build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_EnableInjectedQueue                     build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_EndOfSamplingCallback                   build/stm32g4xx_hal_adc_ex.o
+                                                  build/stm32g4xx_hal_adc.o
+HAL_ADCEx_EnterADCDeepPowerDownMode               build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_InjectedConfigChannel                   build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_InjectedConvCpltCallback                build/stm32g4xx_hal_adc_ex.o
+                                                  build/stm32g4xx_hal_adc.o
+HAL_ADCEx_InjectedGetValue                        build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_InjectedPollForConversion               build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_InjectedQueueOverflowCallback           build/stm32g4xx_hal_adc_ex.o
+                                                  build/stm32g4xx_hal_adc.o
+HAL_ADCEx_InjectedStart                           build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_InjectedStart_IT                        build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_InjectedStop                            build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_InjectedStop_IT                         build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_LevelOutOfWindow2Callback               build/stm32g4xx_hal_adc_ex.o
+                                                  build/stm32g4xx_hal_adc.o
+HAL_ADCEx_LevelOutOfWindow3Callback               build/stm32g4xx_hal_adc_ex.o
+                                                  build/stm32g4xx_hal_adc.o
+HAL_ADCEx_MultiModeConfigChannel                  build/stm32g4xx_hal_adc_ex.o
+                                                  build/main.o
+HAL_ADCEx_MultiModeGetValue                       build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_MultiModeStart_DMA                      build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_MultiModeStop_DMA                       build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_RegularMultiModeStop_DMA                build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_RegularStop                             build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_RegularStop_DMA                         build/stm32g4xx_hal_adc_ex.o
+HAL_ADCEx_RegularStop_IT                          build/stm32g4xx_hal_adc_ex.o
+HAL_ADC_AnalogWDGConfig                           build/stm32g4xx_hal_adc.o
+HAL_ADC_ConfigChannel                             build/stm32g4xx_hal_adc.o
+                                                  build/main.o
+HAL_ADC_ConvCpltCallback                          build/stm32g4xx_hal_adc.o
+HAL_ADC_ConvHalfCpltCallback                      build/stm32g4xx_hal_adc.o
+HAL_ADC_DeInit                                    build/stm32g4xx_hal_adc.o
+HAL_ADC_ErrorCallback                             build/stm32g4xx_hal_adc.o
+HAL_ADC_GetError                                  build/stm32g4xx_hal_adc.o
+HAL_ADC_GetState                                  build/stm32g4xx_hal_adc.o
+HAL_ADC_GetValue                                  build/stm32g4xx_hal_adc.o
+HAL_ADC_IRQHandler                                build/stm32g4xx_hal_adc.o
+HAL_ADC_Init                                      build/stm32g4xx_hal_adc.o
+                                                  build/main.o
+HAL_ADC_LevelOutOfWindowCallback                  build/stm32g4xx_hal_adc.o
+HAL_ADC_MspDeInit                                 build/stm32g4xx_hal_msp.o
+HAL_ADC_MspInit                                   build/stm32g4xx_hal_msp.o
+HAL_ADC_PollForConversion                         build/stm32g4xx_hal_adc.o
+HAL_ADC_PollForEvent                              build/stm32g4xx_hal_adc.o
+HAL_ADC_Start                                     build/stm32g4xx_hal_adc.o
+HAL_ADC_StartSampling                             build/stm32g4xx_hal_adc.o
+HAL_ADC_Start_DMA                                 build/stm32g4xx_hal_adc.o
+HAL_ADC_Start_IT                                  build/stm32g4xx_hal_adc.o
+HAL_ADC_Stop                                      build/stm32g4xx_hal_adc.o
+HAL_ADC_StopSampling                              build/stm32g4xx_hal_adc.o
+HAL_ADC_Stop_DMA                                  build/stm32g4xx_hal_adc.o
+HAL_ADC_Stop_IT                                   build/stm32g4xx_hal_adc.o
+HAL_DBGMCU_DisableDBGSleepMode                    build/stm32g4xx_hal.o
+HAL_DBGMCU_DisableDBGStandbyMode                  build/stm32g4xx_hal.o
+HAL_DBGMCU_DisableDBGStopMode                     build/stm32g4xx_hal.o
+HAL_DBGMCU_EnableDBGSleepMode                     build/stm32g4xx_hal.o
+HAL_DBGMCU_EnableDBGStandbyMode                   build/stm32g4xx_hal.o
+HAL_DBGMCU_EnableDBGStopMode                      build/stm32g4xx_hal.o
+HAL_DMAEx_ConfigMuxRequestGenerator               build/stm32g4xx_hal_dma_ex.o
+HAL_DMAEx_ConfigMuxSync                           build/stm32g4xx_hal_dma_ex.o
+HAL_DMAEx_DisableMuxRequestGenerator              build/stm32g4xx_hal_dma_ex.o
+HAL_DMAEx_EnableMuxRequestGenerator               build/stm32g4xx_hal_dma_ex.o
+HAL_DMAEx_MUX_IRQHandler                          build/stm32g4xx_hal_dma_ex.o
+HAL_DMA_Abort                                     build/stm32g4xx_hal_dma.o
+                                                  build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_adc_ex.o
+                                                  build/stm32g4xx_hal_adc.o
+HAL_DMA_Abort_IT                                  build/stm32g4xx_hal_dma.o
+                                                  build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+                                                  build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_i2c.o
+HAL_DMA_DeInit                                    build/stm32g4xx_hal_dma.o
+HAL_DMA_GetError                                  build/stm32g4xx_hal_dma.o
+                                                  build/stm32g4xx_hal_uart.o
+HAL_DMA_GetState                                  build/stm32g4xx_hal_dma.o
+                                                  build/stm32g4xx_hal_i2c.o
+HAL_DMA_IRQHandler                                build/stm32g4xx_hal_dma.o
+HAL_DMA_Init                                      build/stm32g4xx_hal_dma.o
+HAL_DMA_PollForTransfer                           build/stm32g4xx_hal_dma.o
+HAL_DMA_RegisterCallback                          build/stm32g4xx_hal_dma.o
+HAL_DMA_Start                                     build/stm32g4xx_hal_dma.o
+HAL_DMA_Start_IT                                  build/stm32g4xx_hal_dma.o
+                                                  build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+                                                  build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_i2c.o
+                                                  build/stm32g4xx_hal_adc_ex.o
+                                                  build/stm32g4xx_hal_adc.o
+HAL_DMA_UnRegisterCallback                        build/stm32g4xx_hal_dma.o
+HAL_DeInit                                        build/stm32g4xx_hal.o
+HAL_Delay                                         build/stm32g4xx_hal.o
+                                                  build/stm32g4xx_hal_pcd_ex.o
+                                                  build/usbd_conf.o
+                                                  build/main.o
+HAL_EXTI_ClearConfigLine                          build/stm32g4xx_hal_exti.o
+HAL_EXTI_ClearPending                             build/stm32g4xx_hal_exti.o
+HAL_EXTI_GenerateSWI                              build/stm32g4xx_hal_exti.o
+HAL_EXTI_GetConfigLine                            build/stm32g4xx_hal_exti.o
+HAL_EXTI_GetHandle                                build/stm32g4xx_hal_exti.o
+HAL_EXTI_GetPending                               build/stm32g4xx_hal_exti.o
+HAL_EXTI_IRQHandler                               build/stm32g4xx_hal_exti.o
+HAL_EXTI_RegisterCallback                         build/stm32g4xx_hal_exti.o
+HAL_EXTI_SetConfigLine                            build/stm32g4xx_hal_exti.o
+HAL_FLASHEx_DisableDebugger                       build/stm32g4xx_hal_flash_ex.o
+HAL_FLASHEx_DisableRunPowerDown                   build/stm32g4xx_hal_flash_ramfunc.o
+HAL_FLASHEx_EnableDebugger                        build/stm32g4xx_hal_flash_ex.o
+HAL_FLASHEx_EnableRunPowerDown                    build/stm32g4xx_hal_flash_ramfunc.o
+HAL_FLASHEx_EnableSecMemProtection                build/stm32g4xx_hal_flash_ex.o
+HAL_FLASHEx_Erase                                 build/stm32g4xx_hal_flash_ex.o
+HAL_FLASHEx_Erase_IT                              build/stm32g4xx_hal_flash_ex.o
+HAL_FLASHEx_OBGetConfig                           build/stm32g4xx_hal_flash_ex.o
+HAL_FLASHEx_OBProgram                             build/stm32g4xx_hal_flash_ex.o
+HAL_FLASH_EndOfOperationCallback                  build/stm32g4xx_hal_flash.o
+HAL_FLASH_GetError                                build/stm32g4xx_hal_flash.o
+HAL_FLASH_IRQHandler                              build/stm32g4xx_hal_flash.o
+HAL_FLASH_Lock                                    build/stm32g4xx_hal_flash.o
+HAL_FLASH_OB_Launch                               build/stm32g4xx_hal_flash.o
+HAL_FLASH_OB_Lock                                 build/stm32g4xx_hal_flash.o
+HAL_FLASH_OB_Unlock                               build/stm32g4xx_hal_flash.o
+HAL_FLASH_OperationErrorCallback                  build/stm32g4xx_hal_flash.o
+HAL_FLASH_Program                                 build/stm32g4xx_hal_flash.o
+HAL_FLASH_Program_IT                              build/stm32g4xx_hal_flash.o
+HAL_FLASH_Unlock                                  build/stm32g4xx_hal_flash.o
+HAL_GPIO_DeInit                                   build/stm32g4xx_hal_gpio.o
+                                                  build/stm32g4xx_hal_msp.o
+HAL_GPIO_EXTI_Callback                            build/stm32g4xx_hal_gpio.o
+HAL_GPIO_EXTI_IRQHandler                          build/stm32g4xx_hal_gpio.o
+HAL_GPIO_Init                                     build/stm32g4xx_hal_gpio.o
+                                                  build/stm32g4xx_hal_rcc_ex.o
+                                                  build/stm32g4xx_hal_rcc.o
+                                                  build/stm32g4xx_hal_msp.o
+                                                  build/main.o
+HAL_GPIO_LockPin                                  build/stm32g4xx_hal_gpio.o
+HAL_GPIO_ReadPin                                  build/stm32g4xx_hal_gpio.o
+HAL_GPIO_TogglePin                                build/stm32g4xx_hal_gpio.o
+HAL_GPIO_WritePin                                 build/stm32g4xx_hal_gpio.o
+HAL_GetDEVID                                      build/stm32g4xx_hal.o
+HAL_GetHalVersion                                 build/stm32g4xx_hal.o
+HAL_GetREVID                                      build/stm32g4xx_hal.o
+HAL_GetTick                                       build/stm32g4xx_hal.o
+                                                  build/stm32g4xx_hal_pcd_ex.o
+                                                  build/stm32g4xx_hal_uart_ex.o
+                                                  build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+                                                  build/stm32g4xx_hal_i2c.o
+                                                  build/stm32g4xx_hal_adc_ex.o
+                                                  build/stm32g4xx_hal_adc.o
+                                                  build/stm32g4xx_hal_dma.o
+                                                  build/stm32g4xx_hal_flash.o
+                                                  build/stm32g4xx_hal_rcc_ex.o
+                                                  build/stm32g4xx_hal_rcc.o
+HAL_GetTickFreq                                   build/stm32g4xx_hal.o
+HAL_GetTickPrio                                   build/stm32g4xx_hal.o
+HAL_HalfDuplex_EnableReceiver                     build/stm32g4xx_hal_uart.o
+HAL_HalfDuplex_EnableTransmitter                  build/stm32g4xx_hal_uart.o
+HAL_HalfDuplex_Init                               build/stm32g4xx_hal_uart.o
+HAL_I2CEx_ConfigAnalogFilter                      build/stm32g4xx_hal_i2c_ex.o
+                                                  build/main.o
+HAL_I2CEx_ConfigDigitalFilter                     build/stm32g4xx_hal_i2c_ex.o
+                                                  build/main.o
+HAL_I2CEx_DisableFastModePlus                     build/stm32g4xx_hal_i2c_ex.o
+HAL_I2CEx_DisableWakeUp                           build/stm32g4xx_hal_i2c_ex.o
+HAL_I2CEx_EnableFastModePlus                      build/stm32g4xx_hal_i2c_ex.o
+HAL_I2CEx_EnableWakeUp                            build/stm32g4xx_hal_i2c_ex.o
+HAL_I2C_AbortCpltCallback                         build/stm32g4xx_hal_i2c.o
+HAL_I2C_AddrCallback                              build/stm32g4xx_hal_i2c.o
+HAL_I2C_DeInit                                    build/stm32g4xx_hal_i2c.o
+HAL_I2C_DisableListen_IT                          build/stm32g4xx_hal_i2c.o
+HAL_I2C_ER_IRQHandler                             build/stm32g4xx_hal_i2c.o
+HAL_I2C_EV_IRQHandler                             build/stm32g4xx_hal_i2c.o
+HAL_I2C_EnableListen_IT                           build/stm32g4xx_hal_i2c.o
+HAL_I2C_ErrorCallback                             build/stm32g4xx_hal_i2c.o
+HAL_I2C_GetError                                  build/stm32g4xx_hal_i2c.o
+HAL_I2C_GetMode                                   build/stm32g4xx_hal_i2c.o
+HAL_I2C_GetState                                  build/stm32g4xx_hal_i2c.o
+HAL_I2C_Init                                      build/stm32g4xx_hal_i2c.o
+                                                  build/main.o
+HAL_I2C_IsDeviceReady                             build/stm32g4xx_hal_i2c.o
+                                                  build/si5351.o
+HAL_I2C_ListenCpltCallback                        build/stm32g4xx_hal_i2c.o
+HAL_I2C_MasterRxCpltCallback                      build/stm32g4xx_hal_i2c.o
+HAL_I2C_MasterTxCpltCallback                      build/stm32g4xx_hal_i2c.o
+HAL_I2C_Master_Abort_IT                           build/stm32g4xx_hal_i2c.o
+HAL_I2C_Master_Receive                            build/stm32g4xx_hal_i2c.o
+HAL_I2C_Master_Receive_DMA                        build/stm32g4xx_hal_i2c.o
+HAL_I2C_Master_Receive_IT                         build/stm32g4xx_hal_i2c.o
+HAL_I2C_Master_Seq_Receive_DMA                    build/stm32g4xx_hal_i2c.o
+HAL_I2C_Master_Seq_Receive_IT                     build/stm32g4xx_hal_i2c.o
+HAL_I2C_Master_Seq_Transmit_DMA                   build/stm32g4xx_hal_i2c.o
+HAL_I2C_Master_Seq_Transmit_IT                    build/stm32g4xx_hal_i2c.o
+HAL_I2C_Master_Transmit                           build/stm32g4xx_hal_i2c.o
+HAL_I2C_Master_Transmit_DMA                       build/stm32g4xx_hal_i2c.o
+HAL_I2C_Master_Transmit_IT                        build/stm32g4xx_hal_i2c.o
+HAL_I2C_MemRxCpltCallback                         build/stm32g4xx_hal_i2c.o
+HAL_I2C_MemTxCpltCallback                         build/stm32g4xx_hal_i2c.o
+HAL_I2C_Mem_Read                                  build/stm32g4xx_hal_i2c.o
+                                                  build/si5351.o
+HAL_I2C_Mem_Read_DMA                              build/stm32g4xx_hal_i2c.o
+HAL_I2C_Mem_Read_IT                               build/stm32g4xx_hal_i2c.o
+HAL_I2C_Mem_Write                                 build/stm32g4xx_hal_i2c.o
+                                                  build/si5351.o
+HAL_I2C_Mem_Write_DMA                             build/stm32g4xx_hal_i2c.o
+HAL_I2C_Mem_Write_IT                              build/stm32g4xx_hal_i2c.o
+HAL_I2C_MspDeInit                                 build/stm32g4xx_hal_msp.o
+HAL_I2C_MspInit                                   build/stm32g4xx_hal_msp.o
+HAL_I2C_SlaveRxCpltCallback                       build/stm32g4xx_hal_i2c.o
+HAL_I2C_SlaveTxCpltCallback                       build/stm32g4xx_hal_i2c.o
+HAL_I2C_Slave_Receive                             build/stm32g4xx_hal_i2c.o
+HAL_I2C_Slave_Receive_DMA                         build/stm32g4xx_hal_i2c.o
+HAL_I2C_Slave_Receive_IT                          build/stm32g4xx_hal_i2c.o
+HAL_I2C_Slave_Seq_Receive_DMA                     build/stm32g4xx_hal_i2c.o
+HAL_I2C_Slave_Seq_Receive_IT                      build/stm32g4xx_hal_i2c.o
+HAL_I2C_Slave_Seq_Transmit_DMA                    build/stm32g4xx_hal_i2c.o
+HAL_I2C_Slave_Seq_Transmit_IT                     build/stm32g4xx_hal_i2c.o
+HAL_I2C_Slave_Transmit                            build/stm32g4xx_hal_i2c.o
+HAL_I2C_Slave_Transmit_DMA                        build/stm32g4xx_hal_i2c.o
+HAL_I2C_Slave_Transmit_IT                         build/stm32g4xx_hal_i2c.o
+HAL_IncTick                                       build/stm32g4xx_hal.o
+                                                  build/stm32g4xx_it.o
+HAL_Init                                          build/stm32g4xx_hal.o
+                                                  build/main.o
+HAL_InitTick                                      build/stm32g4xx_hal.o
+                                                  build/stm32g4xx_hal_rcc.o
+HAL_LIN_Init                                      build/stm32g4xx_hal_uart.o
+HAL_LIN_SendBreak                                 build/stm32g4xx_hal_uart.o
+HAL_MPU_ConfigRegion                              build/stm32g4xx_hal_cortex.o
+HAL_MPU_Disable                                   build/stm32g4xx_hal_cortex.o
+HAL_MPU_Enable                                    build/stm32g4xx_hal_cortex.o
+HAL_MspDeInit                                     build/stm32g4xx_hal.o
+HAL_MspInit                                       build/stm32g4xx_hal_msp.o
+HAL_MultiProcessorEx_AddressLength_Set            build/stm32g4xx_hal_uart_ex.o
+HAL_MultiProcessor_DisableMuteMode                build/stm32g4xx_hal_uart.o
+HAL_MultiProcessor_EnableMuteMode                 build/stm32g4xx_hal_uart.o
+HAL_MultiProcessor_EnterMuteMode                  build/stm32g4xx_hal_uart.o
+HAL_MultiProcessor_Init                           build/stm32g4xx_hal_uart.o
+HAL_NVIC_ClearPendingIRQ                          build/stm32g4xx_hal_cortex.o
+HAL_NVIC_DisableIRQ                               build/stm32g4xx_hal_cortex.o
+                                                  build/usbd_conf.o
+                                                  build/stm32g4xx_hal_msp.o
+HAL_NVIC_EnableIRQ                                build/stm32g4xx_hal_cortex.o
+                                                  build/usbd_conf.o
+                                                  build/stm32g4xx_hal_msp.o
+HAL_NVIC_GetActive                                build/stm32g4xx_hal_cortex.o
+HAL_NVIC_GetPendingIRQ                            build/stm32g4xx_hal_cortex.o
+HAL_NVIC_GetPriority                              build/stm32g4xx_hal_cortex.o
+HAL_NVIC_GetPriorityGrouping                      build/stm32g4xx_hal_cortex.o
+HAL_NVIC_SetPendingIRQ                            build/stm32g4xx_hal_cortex.o
+HAL_NVIC_SetPriority                              build/stm32g4xx_hal_cortex.o
+                                                  build/usbd_conf.o
+                                                  build/stm32g4xx_hal.o
+                                                  build/stm32g4xx_hal_msp.o
+HAL_NVIC_SetPriorityGrouping                      build/stm32g4xx_hal_cortex.o
+                                                  build/stm32g4xx_hal.o
+HAL_NVIC_SystemReset                              build/stm32g4xx_hal_cortex.o
+HAL_PCDEx_ActivateBCD                             build/stm32g4xx_hal_pcd_ex.o
+HAL_PCDEx_ActivateLPM                             build/stm32g4xx_hal_pcd_ex.o
+                                                  build/stm32g4xx_hal_pcd.o
+HAL_PCDEx_BCD_Callback                            build/stm32g4xx_hal_pcd_ex.o
+HAL_PCDEx_BCD_VBUSDetect                          build/stm32g4xx_hal_pcd_ex.o
+HAL_PCDEx_DeActivateBCD                           build/stm32g4xx_hal_pcd_ex.o
+HAL_PCDEx_DeActivateLPM                           build/stm32g4xx_hal_pcd_ex.o
+HAL_PCDEx_LPM_Callback                            build/usbd_conf.o
+                                                  build/stm32g4xx_hal_pcd.o
+HAL_PCDEx_PMAConfig                               build/stm32g4xx_hal_pcd_ex.o
+                                                  build/usbd_conf.o
+HAL_PCD_ActivateRemoteWakeup                      build/stm32g4xx_hal_pcd.o
+HAL_PCD_ConnectCallback                           build/usbd_conf.o
+HAL_PCD_DataInStageCallback                       build/usbd_conf.o
+HAL_PCD_DataOutStageCallback                      build/usbd_conf.o
+HAL_PCD_DeActivateRemoteWakeup                    build/stm32g4xx_hal_pcd.o
+HAL_PCD_DeInit                                    build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_DevConnect                                build/stm32g4xx_hal_pcd.o
+HAL_PCD_DevDisconnect                             build/stm32g4xx_hal_pcd.o
+HAL_PCD_DisconnectCallback                        build/usbd_conf.o
+HAL_PCD_EP_Close                                  build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_EP_ClrStall                               build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_EP_Flush                                  build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_EP_GetRxCount                             build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_EP_Open                                   build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_EP_Receive                                build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_EP_SetStall                               build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_EP_Transmit                               build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_GetState                                  build/stm32g4xx_hal_pcd.o
+HAL_PCD_IRQHandler                                build/stm32g4xx_hal_pcd.o
+                                                  build/stm32g4xx_it.o
+HAL_PCD_ISOINIncompleteCallback                   build/usbd_conf.o
+HAL_PCD_ISOOUTIncompleteCallback                  build/usbd_conf.o
+HAL_PCD_Init                                      build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_MspDeInit                                 build/usbd_conf.o
+HAL_PCD_MspInit                                   build/usbd_conf.o
+HAL_PCD_ResetCallback                             build/usbd_conf.o
+HAL_PCD_ResumeCallback                            build/usbd_conf.o
+HAL_PCD_SOFCallback                               build/usbd_conf.o
+HAL_PCD_SetAddress                                build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_SetupStageCallback                        build/usbd_conf.o
+HAL_PCD_Start                                     build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_Stop                                      build/stm32g4xx_hal_pcd.o
+                                                  build/usbd_conf.o
+HAL_PCD_SuspendCallback                           build/usbd_conf.o
+HAL_PWREx_ConfigPVM                               build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_ControlVoltageScaling                   build/stm32g4xx_hal_pwr_ex.o
+                                                  build/main.o
+HAL_PWREx_DisableBatteryCharging                  build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_DisableGPIOPullDown                     build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_DisableGPIOPullUp                       build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_DisableInternalWakeUpLine               build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_DisableLowPowerRunMode                  build/stm32g4xx_hal_pwr_ex.o
+                                                  build/stm32g4xx_hal_pwr.o
+HAL_PWREx_DisablePVM1                             build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_DisablePVM2                             build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_DisablePVM3                             build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_DisablePVM4                             build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_DisablePullUpPullDownConfig             build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_DisableSRAM2ContentRetention            build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_DisableUCPDDeadBattery                  build/stm32g4xx_hal_pwr_ex.o
+                                                  build/stm32g4xx_hal_msp.o
+HAL_PWREx_DisableUCPDStandbyMode                  build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnableBatteryCharging                   build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnableGPIOPullDown                      build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnableGPIOPullUp                        build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnableInternalWakeUpLine                build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnableLowPowerRunMode                   build/stm32g4xx_hal_pwr_ex.o
+                                                  build/stm32g4xx_hal_pwr.o
+HAL_PWREx_EnablePVM1                              build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnablePVM2                              build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnablePVM3                              build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnablePVM4                              build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnablePullUpPullDownConfig              build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnableSRAM2ContentRetention             build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnableUCPDDeadBattery                   build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnableUCPDStandbyMode                   build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnterSHUTDOWNMode                       build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_EnterSTOP0Mode                          build/stm32g4xx_hal_pwr_ex.o
+                                                  build/stm32g4xx_hal_pwr.o
+HAL_PWREx_EnterSTOP1Mode                          build/stm32g4xx_hal_pwr_ex.o
+                                                  build/stm32g4xx_hal_pwr.o
+HAL_PWREx_GetVoltageRange                         build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_PVD_PVM_IRQHandler                      build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_PVM1Callback                            build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_PVM2Callback                            build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_PVM3Callback                            build/stm32g4xx_hal_pwr_ex.o
+HAL_PWREx_PVM4Callback                            build/stm32g4xx_hal_pwr_ex.o
+HAL_PWR_ConfigPVD                                 build/stm32g4xx_hal_pwr.o
+HAL_PWR_DeInit                                    build/stm32g4xx_hal_pwr.o
+HAL_PWR_DisableBkUpAccess                         build/stm32g4xx_hal_pwr.o
+                                                  build/stm32g4xx_hal_rcc_ex.o
+HAL_PWR_DisablePVD                                build/stm32g4xx_hal_pwr.o
+HAL_PWR_DisableSEVOnPend                          build/stm32g4xx_hal_pwr.o
+HAL_PWR_DisableSleepOnExit                        build/stm32g4xx_hal_pwr.o
+HAL_PWR_DisableWakeUpPin                          build/stm32g4xx_hal_pwr.o
+HAL_PWR_EnableBkUpAccess                          build/stm32g4xx_hal_pwr.o
+                                                  build/stm32g4xx_hal_rcc_ex.o
+HAL_PWR_EnablePVD                                 build/stm32g4xx_hal_pwr.o
+HAL_PWR_EnableSEVOnPend                           build/stm32g4xx_hal_pwr.o
+HAL_PWR_EnableSleepOnExit                         build/stm32g4xx_hal_pwr.o
+HAL_PWR_EnableWakeUpPin                           build/stm32g4xx_hal_pwr.o
+HAL_PWR_EnterSLEEPMode                            build/stm32g4xx_hal_pwr.o
+HAL_PWR_EnterSTANDBYMode                          build/stm32g4xx_hal_pwr.o
+HAL_PWR_EnterSTOPMode                             build/stm32g4xx_hal_pwr.o
+HAL_PWR_PVDCallback                               build/stm32g4xx_hal_pwr.o
+                                                  build/stm32g4xx_hal_pwr_ex.o
+HAL_RCCEx_CRSConfig                               build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_CRSGetSynchronizationInfo               build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_CRSSoftwareSynchronizationGenerate      build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_CRSWaitSynchronization                  build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_CRS_ErrorCallback                       build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_CRS_ExpectedSyncCallback                build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_CRS_IRQHandler                          build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_CRS_SyncOkCallback                      build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_CRS_SyncWarnCallback                    build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_DisableLSCO                             build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_DisableLSECSS                           build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_EnableLSCO                              build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_EnableLSECSS                            build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_EnableLSECSS_IT                         build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_GetPeriphCLKConfig                      build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_GetPeriphCLKFreq                        build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_LSECSS_Callback                         build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_LSECSS_IRQHandler                       build/stm32g4xx_hal_rcc_ex.o
+HAL_RCCEx_PeriphCLKConfig                         build/stm32g4xx_hal_rcc_ex.o
+                                                  build/usbd_conf.o
+                                                  build/stm32g4xx_hal_msp.o
+HAL_RCC_CSSCallback                               build/stm32g4xx_hal_rcc.o
+HAL_RCC_ClockConfig                               build/stm32g4xx_hal_rcc.o
+                                                  build/main.o
+HAL_RCC_DeInit                                    build/stm32g4xx_hal_rcc.o
+HAL_RCC_DisableLSECSS                             build/stm32g4xx_hal_rcc.o
+HAL_RCC_EnableCSS                                 build/stm32g4xx_hal_rcc.o
+HAL_RCC_EnableLSECSS                              build/stm32g4xx_hal_rcc.o
+HAL_RCC_GetClockConfig                            build/stm32g4xx_hal_rcc.o
+HAL_RCC_GetHCLKFreq                               build/stm32g4xx_hal_rcc.o
+HAL_RCC_GetOscConfig                              build/stm32g4xx_hal_rcc.o
+HAL_RCC_GetPCLK1Freq                              build/stm32g4xx_hal_rcc.o
+                                                  build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_rcc_ex.o
+HAL_RCC_GetPCLK2Freq                              build/stm32g4xx_hal_rcc.o
+                                                  build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_rcc_ex.o
+HAL_RCC_GetSysClockFreq                           build/stm32g4xx_hal_rcc.o
+                                                  build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_rcc_ex.o
+HAL_RCC_MCOConfig                                 build/stm32g4xx_hal_rcc.o
+                                                  build/main.o
+HAL_RCC_NMI_IRQHandler                            build/stm32g4xx_hal_rcc.o
+HAL_RCC_OscConfig                                 build/stm32g4xx_hal_rcc.o
+                                                  build/main.o
+HAL_RS485Ex_Init                                  build/stm32g4xx_hal_uart_ex.o
+HAL_ResumeTick                                    build/stm32g4xx_hal.o
+HAL_SYSCFG_CCMSRAMErase                           build/stm32g4xx_hal.o
+HAL_SYSCFG_CCMSRAM_WriteProtectionEnable          build/stm32g4xx_hal.o
+HAL_SYSCFG_DisableIOSwitchBooster                 build/stm32g4xx_hal.o
+HAL_SYSCFG_DisableIOSwitchVDD                     build/stm32g4xx_hal.o
+HAL_SYSCFG_DisableMemorySwappingBank              build/stm32g4xx_hal.o
+HAL_SYSCFG_DisableVREFBUF                         build/stm32g4xx_hal.o
+HAL_SYSCFG_EnableIOSwitchBooster                  build/stm32g4xx_hal.o
+HAL_SYSCFG_EnableIOSwitchVDD                      build/stm32g4xx_hal.o
+HAL_SYSCFG_EnableMemorySwappingBank               build/stm32g4xx_hal.o
+HAL_SYSCFG_EnableVREFBUF                          build/stm32g4xx_hal.o
+HAL_SYSCFG_VREFBUF_HighImpedanceConfig            build/stm32g4xx_hal.o
+HAL_SYSCFG_VREFBUF_TrimmingConfig                 build/stm32g4xx_hal.o
+HAL_SYSCFG_VREFBUF_VoltageScalingConfig           build/stm32g4xx_hal.o
+HAL_SYSTICK_CLKSourceConfig                       build/stm32g4xx_hal_cortex.o
+HAL_SYSTICK_Callback                              build/stm32g4xx_hal_cortex.o
+HAL_SYSTICK_Config                                build/stm32g4xx_hal_cortex.o
+                                                  build/stm32g4xx_hal.o
+HAL_SYSTICK_IRQHandler                            build/stm32g4xx_hal_cortex.o
+HAL_SetTickFreq                                   build/stm32g4xx_hal.o
+HAL_SuspendTick                                   build/stm32g4xx_hal.o
+HAL_TIMEx_Break2Callback                          build/stm32g4xx_hal_tim_ex.o
+                                                  build/stm32g4xx_hal_tim.o
+HAL_TIMEx_BreakCallback                           build/stm32g4xx_hal_tim_ex.o
+                                                  build/stm32g4xx_hal_tim.o
+HAL_TIMEx_CommutCallback                          build/stm32g4xx_hal_tim_ex.o
+                                                  build/stm32g4xx_hal_tim.o
+HAL_TIMEx_CommutHalfCpltCallback                  build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_ConfigAsymmetricalDeadTime              build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_ConfigBreakDeadTime                     build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_ConfigBreakInput                        build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_ConfigCommutEvent                       build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_ConfigCommutEvent_DMA                   build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_ConfigCommutEvent_IT                    build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_ConfigDeadTime                          build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_ConfigEncoderIndex                      build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_ConfigSlaveModePreload                  build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_DirectionChangeCallback                 build/stm32g4xx_hal_tim_ex.o
+                                                  build/stm32g4xx_hal_tim.o
+HAL_TIMEx_DisableAsymmetricalDeadTime             build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_DisableDeadTimePreload                  build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_DisableEncoderFirstIndex                build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_DisableEncoderIndex                     build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_DisableSlaveModePreload                 build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_DisarmBreakInput                        build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_DitheringDisable                        build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_DitheringEnable                         build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_EnableAsymmetricalDeadTime              build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_EnableDeadTimePreload                   build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_EnableEncoderFirstIndex                 build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_EnableEncoderIndex                      build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_EnableSlaveModePreload                  build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_EncoderIndexCallback                    build/stm32g4xx_hal_tim_ex.o
+                                                  build/stm32g4xx_hal_tim.o
+HAL_TIMEx_GetChannelNState                        build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_GroupChannel5                           build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_DeInit                       build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_GetState                     build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Init                         build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_MspDeInit                    build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_MspInit                      build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Start                        build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Start_DMA                    build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Start_IT                     build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Stop                         build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Stop_DMA                     build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Stop_IT                      build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_IndexErrorCallback                      build/stm32g4xx_hal_tim_ex.o
+                                                  build/stm32g4xx_hal_tim.o
+HAL_TIMEx_MasterConfigSynchronization             build/stm32g4xx_hal_tim_ex.o
+                                                  build/main.o
+HAL_TIMEx_OCN_Start                               build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_OCN_Start_DMA                           build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_OCN_Start_IT                            build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_OCN_Stop                                build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_OCN_Stop_DMA                            build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_OCN_Stop_IT                             build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_OC_ConfigPulseOnCompare                 build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_OnePulseN_Start                         build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_OnePulseN_Start_IT                      build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_OnePulseN_Stop                          build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_OnePulseN_Stop_IT                       build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_PWMN_Start                              build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_PWMN_Start_DMA                          build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_PWMN_Start_IT                           build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_PWMN_Stop                               build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_PWMN_Stop_DMA                           build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_PWMN_Stop_IT                            build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_ReArmBreakInput                         build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_RemapConfig                             build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_TISelection                             build/stm32g4xx_hal_tim_ex.o
+HAL_TIMEx_TransitionErrorCallback                 build/stm32g4xx_hal_tim_ex.o
+                                                  build/stm32g4xx_hal_tim.o
+HAL_TIM_Base_DeInit                               build/stm32g4xx_hal_tim.o
+HAL_TIM_Base_GetState                             build/stm32g4xx_hal_tim.o
+HAL_TIM_Base_Init                                 build/stm32g4xx_hal_tim.o
+                                                  build/main.o
+HAL_TIM_Base_MspDeInit                            build/stm32g4xx_hal_msp.o
+HAL_TIM_Base_MspInit                              build/stm32g4xx_hal_msp.o
+HAL_TIM_Base_Start                                build/stm32g4xx_hal_tim.o
+HAL_TIM_Base_Start_DMA                            build/stm32g4xx_hal_tim.o
+HAL_TIM_Base_Start_IT                             build/stm32g4xx_hal_tim.o
+                                                  build/main.o
+HAL_TIM_Base_Stop                                 build/stm32g4xx_hal_tim.o
+HAL_TIM_Base_Stop_DMA                             build/stm32g4xx_hal_tim.o
+HAL_TIM_Base_Stop_IT                              build/stm32g4xx_hal_tim.o
+HAL_TIM_ConfigClockSource                         build/stm32g4xx_hal_tim.o
+                                                  build/main.o
+HAL_TIM_ConfigOCrefClear                          build/stm32g4xx_hal_tim.o
+HAL_TIM_ConfigTI1Input                            build/stm32g4xx_hal_tim.o
+HAL_TIM_DMABurstState                             build/stm32g4xx_hal_tim.o
+HAL_TIM_DMABurst_MultiReadStart                   build/stm32g4xx_hal_tim.o
+HAL_TIM_DMABurst_MultiWriteStart                  build/stm32g4xx_hal_tim.o
+HAL_TIM_DMABurst_ReadStart                        build/stm32g4xx_hal_tim.o
+HAL_TIM_DMABurst_ReadStop                         build/stm32g4xx_hal_tim.o
+HAL_TIM_DMABurst_WriteStart                       build/stm32g4xx_hal_tim.o
+HAL_TIM_DMABurst_WriteStop                        build/stm32g4xx_hal_tim.o
+HAL_TIM_Encoder_DeInit                            build/stm32g4xx_hal_tim.o
+HAL_TIM_Encoder_GetState                          build/stm32g4xx_hal_tim.o
+HAL_TIM_Encoder_Init                              build/stm32g4xx_hal_tim.o
+HAL_TIM_Encoder_MspDeInit                         build/stm32g4xx_hal_tim.o
+HAL_TIM_Encoder_MspInit                           build/stm32g4xx_hal_tim.o
+HAL_TIM_Encoder_Start                             build/stm32g4xx_hal_tim.o
+HAL_TIM_Encoder_Start_DMA                         build/stm32g4xx_hal_tim.o
+HAL_TIM_Encoder_Start_IT                          build/stm32g4xx_hal_tim.o
+HAL_TIM_Encoder_Stop                              build/stm32g4xx_hal_tim.o
+HAL_TIM_Encoder_Stop_DMA                          build/stm32g4xx_hal_tim.o
+HAL_TIM_Encoder_Stop_IT                           build/stm32g4xx_hal_tim.o
+HAL_TIM_ErrorCallback                             build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+HAL_TIM_GenerateEvent                             build/stm32g4xx_hal_tim.o
+HAL_TIM_GetActiveChannel                          build/stm32g4xx_hal_tim.o
+HAL_TIM_GetChannelState                           build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_CaptureCallback                        build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_CaptureHalfCpltCallback                build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_ConfigChannel                          build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_DeInit                                 build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_GetState                               build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_Init                                   build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_MspDeInit                              build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_MspInit                                build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_Start                                  build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_Start_DMA                              build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_Start_IT                               build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_Stop                                   build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_Stop_DMA                               build/stm32g4xx_hal_tim.o
+HAL_TIM_IC_Stop_IT                                build/stm32g4xx_hal_tim.o
+HAL_TIM_IRQHandler                                build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_it.o
+HAL_TIM_MspPostInit                               build/stm32g4xx_hal_msp.o
+                                                  build/main.o
+HAL_TIM_OC_ConfigChannel                          build/stm32g4xx_hal_tim.o
+HAL_TIM_OC_DeInit                                 build/stm32g4xx_hal_tim.o
+HAL_TIM_OC_DelayElapsedCallback                   build/stm32g4xx_hal_tim.o
+HAL_TIM_OC_GetState                               build/stm32g4xx_hal_tim.o
+HAL_TIM_OC_Init                                   build/stm32g4xx_hal_tim.o
+HAL_TIM_OC_MspDeInit                              build/stm32g4xx_hal_tim.o
+HAL_TIM_OC_MspInit                                build/stm32g4xx_hal_tim.o
+HAL_TIM_OC_Start                                  build/stm32g4xx_hal_tim.o
+HAL_TIM_OC_Start_DMA                              build/stm32g4xx_hal_tim.o
+HAL_TIM_OC_Start_IT                               build/stm32g4xx_hal_tim.o
+HAL_TIM_OC_Stop                                   build/stm32g4xx_hal_tim.o
+HAL_TIM_OC_Stop_DMA                               build/stm32g4xx_hal_tim.o
+HAL_TIM_OC_Stop_IT                                build/stm32g4xx_hal_tim.o
+HAL_TIM_OnePulse_ConfigChannel                    build/stm32g4xx_hal_tim.o
+HAL_TIM_OnePulse_DeInit                           build/stm32g4xx_hal_tim.o
+HAL_TIM_OnePulse_GetState                         build/stm32g4xx_hal_tim.o
+HAL_TIM_OnePulse_Init                             build/stm32g4xx_hal_tim.o
+HAL_TIM_OnePulse_MspDeInit                        build/stm32g4xx_hal_tim.o
+HAL_TIM_OnePulse_MspInit                          build/stm32g4xx_hal_tim.o
+HAL_TIM_OnePulse_Start                            build/stm32g4xx_hal_tim.o
+HAL_TIM_OnePulse_Start_IT                         build/stm32g4xx_hal_tim.o
+HAL_TIM_OnePulse_Stop                             build/stm32g4xx_hal_tim.o
+HAL_TIM_OnePulse_Stop_IT                          build/stm32g4xx_hal_tim.o
+HAL_TIM_PWM_ConfigChannel                         build/stm32g4xx_hal_tim.o
+                                                  build/main.o
+HAL_TIM_PWM_DeInit                                build/stm32g4xx_hal_tim.o
+HAL_TIM_PWM_GetState                              build/stm32g4xx_hal_tim.o
+HAL_TIM_PWM_Init                                  build/stm32g4xx_hal_tim.o
+                                                  build/main.o
+HAL_TIM_PWM_MspDeInit                             build/stm32g4xx_hal_tim.o
+HAL_TIM_PWM_MspInit                               build/stm32g4xx_hal_tim.o
+HAL_TIM_PWM_PulseFinishedCallback                 build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+HAL_TIM_PWM_PulseFinishedHalfCpltCallback         build/stm32g4xx_hal_tim.o
+HAL_TIM_PWM_Start                                 build/stm32g4xx_hal_tim.o
+                                                  build/main.o
+HAL_TIM_PWM_Start_DMA                             build/stm32g4xx_hal_tim.o
+HAL_TIM_PWM_Start_IT                              build/stm32g4xx_hal_tim.o
+HAL_TIM_PWM_Stop                                  build/stm32g4xx_hal_tim.o
+HAL_TIM_PWM_Stop_DMA                              build/stm32g4xx_hal_tim.o
+HAL_TIM_PWM_Stop_IT                               build/stm32g4xx_hal_tim.o
+HAL_TIM_PeriodElapsedCallback                     build/stm32g4xx_hal_tim.o
+HAL_TIM_PeriodElapsedHalfCpltCallback             build/stm32g4xx_hal_tim.o
+HAL_TIM_ReadCapturedValue                         build/stm32g4xx_hal_tim.o
+HAL_TIM_SlaveConfigSynchro                        build/stm32g4xx_hal_tim.o
+HAL_TIM_SlaveConfigSynchro_IT                     build/stm32g4xx_hal_tim.o
+HAL_TIM_TriggerCallback                           build/stm32g4xx_hal_tim.o
+HAL_TIM_TriggerHalfCpltCallback                   build/stm32g4xx_hal_tim.o
+HAL_UARTEx_DisableFifoMode                        build/stm32g4xx_hal_uart_ex.o
+                                                  build/main.o
+HAL_UARTEx_DisableStopMode                        build/stm32g4xx_hal_uart_ex.o
+HAL_UARTEx_EnableFifoMode                         build/stm32g4xx_hal_uart_ex.o
+HAL_UARTEx_EnableStopMode                         build/stm32g4xx_hal_uart_ex.o
+HAL_UARTEx_ReceiveToIdle                          build/stm32g4xx_hal_uart_ex.o
+HAL_UARTEx_ReceiveToIdle_DMA                      build/stm32g4xx_hal_uart_ex.o
+HAL_UARTEx_ReceiveToIdle_IT                       build/stm32g4xx_hal_uart_ex.o
+HAL_UARTEx_RxEventCallback                        build/stm32g4xx_hal_uart.o
+HAL_UARTEx_RxFifoFullCallback                     build/stm32g4xx_hal_uart_ex.o
+                                                  build/stm32g4xx_hal_uart.o
+HAL_UARTEx_SetRxFifoThreshold                     build/stm32g4xx_hal_uart_ex.o
+                                                  build/main.o
+HAL_UARTEx_SetTxFifoThreshold                     build/stm32g4xx_hal_uart_ex.o
+                                                  build/main.o
+HAL_UARTEx_StopModeWakeUpSourceConfig             build/stm32g4xx_hal_uart_ex.o
+HAL_UARTEx_TxFifoEmptyCallback                    build/stm32g4xx_hal_uart_ex.o
+                                                  build/stm32g4xx_hal_uart.o
+HAL_UARTEx_WakeupCallback                         build/stm32g4xx_hal_uart_ex.o
+                                                  build/stm32g4xx_hal_uart.o
+HAL_UART_Abort                                    build/stm32g4xx_hal_uart.o
+HAL_UART_AbortCpltCallback                        build/stm32g4xx_hal_uart.o
+HAL_UART_AbortReceive                             build/stm32g4xx_hal_uart.o
+HAL_UART_AbortReceiveCpltCallback                 build/stm32g4xx_hal_uart.o
+HAL_UART_AbortReceive_IT                          build/stm32g4xx_hal_uart.o
+HAL_UART_AbortTransmit                            build/stm32g4xx_hal_uart.o
+HAL_UART_AbortTransmitCpltCallback                build/stm32g4xx_hal_uart.o
+HAL_UART_AbortTransmit_IT                         build/stm32g4xx_hal_uart.o
+HAL_UART_Abort_IT                                 build/stm32g4xx_hal_uart.o
+HAL_UART_DMAPause                                 build/stm32g4xx_hal_uart.o
+HAL_UART_DMAResume                                build/stm32g4xx_hal_uart.o
+HAL_UART_DMAStop                                  build/stm32g4xx_hal_uart.o
+HAL_UART_DeInit                                   build/stm32g4xx_hal_uart.o
+HAL_UART_DisableReceiverTimeout                   build/stm32g4xx_hal_uart.o
+HAL_UART_EnableReceiverTimeout                    build/stm32g4xx_hal_uart.o
+HAL_UART_ErrorCallback                            build/stm32g4xx_hal_uart.o
+HAL_UART_GetError                                 build/stm32g4xx_hal_uart.o
+HAL_UART_GetState                                 build/stm32g4xx_hal_uart.o
+HAL_UART_IRQHandler                               build/stm32g4xx_hal_uart.o
+HAL_UART_Init                                     build/stm32g4xx_hal_uart.o
+                                                  build/main.o
+HAL_UART_MspDeInit                                build/stm32g4xx_hal_msp.o
+HAL_UART_MspInit                                  build/stm32g4xx_hal_msp.o
+                                                  build/stm32g4xx_hal_uart_ex.o
+HAL_UART_Receive                                  build/stm32g4xx_hal_uart.o
+HAL_UART_Receive_DMA                              build/stm32g4xx_hal_uart.o
+HAL_UART_Receive_IT                               build/stm32g4xx_hal_uart.o
+HAL_UART_ReceiverTimeout_Config                   build/stm32g4xx_hal_uart.o
+HAL_UART_RxCpltCallback                           build/stm32g4xx_hal_uart.o
+HAL_UART_RxHalfCpltCallback                       build/stm32g4xx_hal_uart.o
+HAL_UART_Transmit                                 build/stm32g4xx_hal_uart.o
+HAL_UART_Transmit_DMA                             build/stm32g4xx_hal_uart.o
+HAL_UART_Transmit_IT                              build/stm32g4xx_hal_uart.o
+HAL_UART_TxCpltCallback                           build/stm32g4xx_hal_uart.o
+HAL_UART_TxHalfCpltCallback                       build/stm32g4xx_hal_uart.o
+HalfTransfer_CallBack_FS                          build/usbd_audio_if.o
+HardFault_Handler                                 build/stm32g4xx_it.o
+I2C1_ER_IRQHandler                                build/startup_stm32g431xx.o
+I2C1_EV_IRQHandler                                build/startup_stm32g431xx.o
+I2C2_ER_IRQHandler                                build/startup_stm32g431xx.o
+I2C2_EV_IRQHandler                                build/startup_stm32g431xx.o
+I2C3_ER_IRQHandler                                build/startup_stm32g431xx.o
+I2C3_EV_IRQHandler                                build/startup_stm32g431xx.o
+LPTIM1_IRQHandler                                 build/startup_stm32g431xx.o
+LPUART1_IRQHandler                                build/startup_stm32g431xx.o
+MX_USB_Device_Init                                build/usb_device.o
+                                                  build/main.o
+MemManage_Handler                                 build/stm32g4xx_it.o
+NMI_Handler                                       build/stm32g4xx_it.o
+PVD_PVM_IRQHandler                                build/startup_stm32g431xx.o
+PendSV_Handler                                    build/stm32g4xx_it.o
+RCC_IRQHandler                                    build/startup_stm32g431xx.o
+RNG_IRQHandler                                    build/startup_stm32g431xx.o
+RTC_Alarm_IRQHandler                              build/startup_stm32g431xx.o
+RTC_TAMP_LSECSS_IRQHandler                        build/startup_stm32g431xx.o
+RTC_WKUP_IRQHandler                               build/startup_stm32g431xx.o
+Reset_Handler                                     build/startup_stm32g431xx.o
+SAI1_IRQHandler                                   build/startup_stm32g431xx.o
+SPI1_IRQHandler                                   build/startup_stm32g431xx.o
+SPI2_IRQHandler                                   build/startup_stm32g431xx.o
+SPI3_IRQHandler                                   build/startup_stm32g431xx.o
+SVC_Handler                                       build/stm32g4xx_it.o
+SysTick_Handler                                   build/stm32g4xx_it.o
+SystemClock_Config                                build/main.o
+                                                  build/usbd_conf.o
+SystemCoreClock                                   build/system_stm32g4xx.o
+                                                  build/stm32g4xx_hal_adc_ex.o
+                                                  build/stm32g4xx_hal_adc.o
+                                                  build/stm32g4xx_hal_pwr_ex.o
+                                                  build/stm32g4xx_hal_rcc.o
+                                                  build/stm32g4xx_hal.o
+SystemCoreClockUpdate                             build/system_stm32g4xx.o
+SystemInit                                        build/system_stm32g4xx.o
+                                                  build/startup_stm32g431xx.o
+TIM1_BRK_TIM15_IRQHandler                         build/startup_stm32g431xx.o
+TIM1_CC_IRQHandler                                build/startup_stm32g431xx.o
+TIM1_TRG_COM_TIM17_IRQHandler                     build/startup_stm32g431xx.o
+TIM1_UP_TIM16_IRQHandler                          build/startup_stm32g431xx.o
+TIM2_IRQHandler                                   build/startup_stm32g431xx.o
+TIM3_IRQHandler                                   build/stm32g4xx_it.o
+TIM4_IRQHandler                                   build/startup_stm32g431xx.o
+TIM6_DAC_IRQHandler                               build/startup_stm32g431xx.o
+TIM7_IRQHandler                                   build/startup_stm32g431xx.o
+TIM8_BRK_IRQHandler                               build/startup_stm32g431xx.o
+TIM8_CC_IRQHandler                                build/startup_stm32g431xx.o
+TIM8_TRG_COM_IRQHandler                           build/startup_stm32g431xx.o
+TIM8_UP_IRQHandler                                build/startup_stm32g431xx.o
+TIMEx_DMACommutationCplt                          build/stm32g4xx_hal_tim_ex.o
+                                                  build/stm32g4xx_hal_tim.o
+TIMEx_DMACommutationHalfCplt                      build/stm32g4xx_hal_tim_ex.o
+                                                  build/stm32g4xx_hal_tim.o
+TIM_Base_SetConfig                                build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+TIM_CCxChannelCmd                                 build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+TIM_DMACaptureCplt                                build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+TIM_DMACaptureHalfCplt                            build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+TIM_DMADelayPulseHalfCplt                         build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+TIM_DMAError                                      build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+TIM_ETR_SetConfig                                 build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+TIM_OC2_SetConfig                                 build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+TIM_TI1_SetConfig                                 build/stm32g4xx_hal_tim.o
+                                                  build/stm32g4xx_hal_tim_ex.o
+TransferComplete_CallBack_FS                      build/usbd_audio_if.o
+UART4_IRQHandler                                  build/startup_stm32g431xx.o
+UARTPrescTable                                    build/stm32g4xx_hal_uart.o
+UART_AdvFeatureConfig                             build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_uart_ex.o
+UART_CheckIdleState                               build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_uart_ex.o
+UART_SetConfig                                    build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_uart_ex.o
+UART_Start_Receive_DMA                            build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_uart_ex.o
+UART_Start_Receive_IT                             build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_uart_ex.o
+UART_WaitOnFlagUntilTimeout                       build/stm32g4xx_hal_uart.o
+                                                  build/stm32g4xx_hal_uart_ex.o
+UCPD1_IRQHandler                                  build/startup_stm32g431xx.o
+USART1_IRQHandler                                 build/startup_stm32g431xx.o
+USART2_IRQHandler                                 build/startup_stm32g431xx.o
+USART3_IRQHandler                                 build/startup_stm32g431xx.o
+USBD_AUDIO                                        build/usbd_audio.o
+                                                  build/usb_device.o
+USBD_AUDIO_ConfigStrDescriptor                    build/usbd_desc.o
+USBD_AUDIO_DeviceDesc                             build/usbd_desc.o
+USBD_AUDIO_DeviceDescriptor                       build/usbd_desc.o
+USBD_AUDIO_InterfaceStrDescriptor                 build/usbd_desc.o
+USBD_AUDIO_LangIDStrDescriptor                    build/usbd_desc.o
+USBD_AUDIO_ManufacturerStrDescriptor              build/usbd_desc.o
+USBD_AUDIO_ProductStrDescriptor                   build/usbd_desc.o
+USBD_AUDIO_RegisterInterface                      build/usbd_audio.o
+                                                  build/usb_device.o
+USBD_AUDIO_SerialStrDescriptor                    build/usbd_desc.o
+USBD_AUDIO_Sync                                   build/usbd_audio.o
+                                                  build/usbd_audio_if.o
+USBD_AUDIO_fops_FS                                build/usbd_audio_if.o
+                                                  build/usb_device.o
+USBD_ClrClassConfig                               build/usbd_core.o
+                                                  build/usbd_ctlreq.o
+USBD_CtlContinueRx                                build/usbd_ioreq.o
+                                                  build/usbd_core.o
+USBD_CtlContinueSendData                          build/usbd_ioreq.o
+                                                  build/usbd_core.o
+USBD_CtlError                                     build/usbd_ctlreq.o
+                                                  build/usbd_audio.o
+USBD_CtlPrepareRx                                 build/usbd_ioreq.o
+                                                  build/usbd_audio.o
+USBD_CtlReceiveStatus                             build/usbd_ioreq.o
+                                                  build/usbd_core.o
+USBD_CtlSendData                                  build/usbd_ioreq.o
+                                                  build/usbd_audio.o
+                                                  build/usbd_ctlreq.o
+USBD_CtlSendStatus                                build/usbd_ioreq.o
+                                                  build/usbd_ctlreq.o
+                                                  build/usbd_core.o
+USBD_DeInit                                       build/usbd_core.o
+USBD_GetRxCount                                   build/usbd_ioreq.o
+USBD_GetString                                    build/usbd_ctlreq.o
+                                                  build/usbd_desc.o
+USBD_Init                                         build/usbd_core.o
+                                                  build/usb_device.o
+USBD_LL_ClearStallEP                              build/usbd_conf.o
+                                                  build/usbd_ctlreq.o
+USBD_LL_CloseEP                                   build/usbd_conf.o
+                                                  build/usbd_audio.o
+USBD_LL_DataInStage                               build/usbd_core.o
+                                                  build/usbd_conf.o
+USBD_LL_DataOutStage                              build/usbd_core.o
+                                                  build/usbd_conf.o
+USBD_LL_DeInit                                    build/usbd_conf.o
+                                                  build/usbd_core.o
+USBD_LL_Delay                                     build/usbd_conf.o
+USBD_LL_DevConnected                              build/usbd_core.o
+                                                  build/usbd_conf.o
+USBD_LL_DevDisconnected                           build/usbd_core.o
+                                                  build/usbd_conf.o
+USBD_LL_FlushEP                                   build/usbd_conf.o
+USBD_LL_GetRxDataSize                             build/usbd_conf.o
+                                                  build/usbd_audio.o
+                                                  build/usbd_ioreq.o
+USBD_LL_Init                                      build/usbd_conf.o
+                                                  build/usbd_core.o
+USBD_LL_IsStallEP                                 build/usbd_conf.o
+                                                  build/usbd_ctlreq.o
+USBD_LL_IsoINIncomplete                           build/usbd_core.o
+                                                  build/usbd_conf.o
+USBD_LL_IsoOUTIncomplete                          build/usbd_core.o
+                                                  build/usbd_conf.o
+USBD_LL_OpenEP                                    build/usbd_conf.o
+                                                  build/usbd_audio.o
+                                                  build/usbd_core.o
+USBD_LL_PrepareReceive                            build/usbd_conf.o
+                                                  build/usbd_audio.o
+                                                  build/usbd_ioreq.o
+                                                  build/usbd_core.o
+USBD_LL_Reset                                     build/usbd_core.o
+                                                  build/usbd_conf.o
+USBD_LL_Resume                                    build/usbd_core.o
+                                                  build/usbd_conf.o
+USBD_LL_SOF                                       build/usbd_core.o
+                                                  build/usbd_conf.o
+USBD_LL_SetSpeed                                  build/usbd_core.o
+                                                  build/usbd_conf.o
+USBD_LL_SetUSBAddress                             build/usbd_conf.o
+                                                  build/usbd_ctlreq.o
+USBD_LL_SetupStage                                build/usbd_core.o
+                                                  build/usbd_conf.o
+USBD_LL_StallEP                                   build/usbd_conf.o
+                                                  build/usbd_ctlreq.o
+                                                  build/usbd_core.o
+USBD_LL_Start                                     build/usbd_conf.o
+                                                  build/usbd_core.o
+USBD_LL_Stop                                      build/usbd_conf.o
+                                                  build/usbd_core.o
+USBD_LL_Suspend                                   build/usbd_core.o
+                                                  build/usbd_conf.o
+USBD_LL_Transmit                                  build/usbd_conf.o
+                                                  build/usbd_ioreq.o
+USBD_LangIDDesc                                   build/usbd_desc.o
+USBD_ParseSetupRequest                            build/usbd_ctlreq.o
+                                                  build/usbd_core.o
+USBD_RegisterClass                                build/usbd_core.o
+                                                  build/usb_device.o
+USBD_RunTestMode                                  build/usbd_core.o
+USBD_SetClassConfig                               build/usbd_core.o
+                                                  build/usbd_ctlreq.o
+USBD_Start                                        build/usbd_core.o
+                                                  build/usb_device.o
+USBD_StdDevReq                                    build/usbd_ctlreq.o
+                                                  build/usbd_core.o
+USBD_StdEPReq                                     build/usbd_ctlreq.o
+                                                  build/usbd_core.o
+USBD_StdItfReq                                    build/usbd_ctlreq.o
+                                                  build/usbd_core.o
+USBD_Stop                                         build/usbd_core.o
+USBD_StrDesc                                      build/usbd_desc.o
+USBD_StringSerial                                 build/usbd_desc.o
+USBD_static_free                                  build/usbd_conf.o
+                                                  build/usbd_audio.o
+USBD_static_malloc                                build/usbd_conf.o
+                                                  build/usbd_audio.o
+USBWakeUp_IRQHandler                              build/startup_stm32g431xx.o
+USB_ActivateEndpoint                              build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_ActivateRemoteWakeup                          build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_CoreInit                                      build/stm32g4xx_ll_usb.o
+USB_DeActivateRemoteWakeup                        build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_DeactivateEndpoint                            build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_DevConnect                                    build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_DevDisconnect                                 build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_DevInit                                       build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_DisableGlobalInt                              build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_EPClearStall                                  build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_EPSetStall                                    build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_EPStartXfer                                   build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_EnableGlobalInt                               build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_HP_IRQHandler                                 build/startup_stm32g431xx.o
+USB_LP_IRQHandler                                 build/stm32g4xx_it.o
+USB_ReadInterrupts                                build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_ReadPMA                                       build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_SetCurrentMode                                build/stm32g4xx_ll_usb.o
+USB_SetDevAddress                                 build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_StopDevice                                    build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+USB_WritePMA                                      build/stm32g4xx_ll_usb.o
+                                                  build/stm32g4xx_hal_pcd.o
+UsageFault_Handler                                build/stm32g4xx_it.o
+WWDG_IRQHandler                                   build/startup_stm32g431xx.o
+_ITM_deregisterTMCloneTable                       /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+_ITM_registerTMCloneTable                         /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+__TMC_END__                                       /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtend.o
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+__adddf3                                          /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+__aeabi_cdcmpeq                                   /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+__aeabi_cdcmple                                   /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+__aeabi_cdrcmple                                  /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+__aeabi_d2iz                                      /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_fixdfsi.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_sin.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_rem_pio2.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_cos.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-e_rem_pio2.o)
+                                                  build/si5351.o
+__aeabi_d2uiz                                     /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_fixunsdfsi.o)
+                                                  build/si5351.o
+                                                  build/squeow.o
+__aeabi_dadd                                      /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_scalbn.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_floor.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_sin.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_rem_pio2.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_cos.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-e_rem_pio2.o)
+                                                  build/si5351.o
+                                                  build/squeow.o
+__aeabi_dcmpeq                                    /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_rem_pio2.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-e_rem_pio2.o)
+__aeabi_dcmpge                                    /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_rem_pio2.o)
+                                                  build/squeow.o
+__aeabi_dcmpgt                                    /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_floor.o)
+__aeabi_dcmple                                    /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+__aeabi_dcmplt                                    /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+__aeabi_ddiv                                      /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldivdf3.o)
+                                                  build/si5351.o
+__aeabi_dmul                                      /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldivdf3.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_scalbn.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_sin.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_rem_pio2.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_cos.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-e_rem_pio2.o)
+                                                  build/si5351.o
+                                                  build/squeow.o
+__aeabi_drsub                                     /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+__aeabi_dsub                                      /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_sin.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_rem_pio2.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_cos.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-e_rem_pio2.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_sin.o)
+                                                  build/si5351.o
+__aeabi_f2d                                       /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+__aeabi_i2d                                       /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_rem_pio2.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-e_rem_pio2.o)
+                                                  build/si5351.o
+__aeabi_idiv0                                     /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o)
+__aeabi_l2d                                       /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+__aeabi_ldiv0                                     /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o)
+__aeabi_ui2d                                      /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+                                                  build/si5351.o
+__aeabi_ul2d                                      /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+__aeabi_uldivmod                                  /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o)
+                                                  build/stm32g4xx_hal_uart.o
+__atexit_dummy                                    /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-__atexit.o)
+__bss_end__                                       /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+__bss_start__                                     /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+__call_exitprocs                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-__call_atexit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-__atexit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-exit.o)
+__cmpdf2                                          /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+__deregister_frame_info                           /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+__divdf3                                          /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldivdf3.o)
+__dso_handle                                      /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+__eqdf2                                           /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+__extendsfdf2                                     /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+__fini_array_end                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-fini.o)
+__fini_array_start                                /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-fini.o)
+__fixdfsi                                         /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_fixdfsi.o)
+__fixunsdfsi                                      /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_fixunsdfsi.o)
+__floatdidf                                       /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+__floatsidf                                       /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+__floatundidf                                     /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+__floatunsidf                                     /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+__gedf2                                           /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+__gtdf2                                           /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+__ieee754_rem_pio2                                /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-e_rem_pio2.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_sin.o)
+__init_array_end                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-init.o)
+__init_array_start                                /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-init.o)
+__kernel_cos                                      /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_cos.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_sin.o)
+__kernel_rem_pio2                                 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_rem_pio2.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-e_rem_pio2.o)
+__kernel_sin                                      /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_sin.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_sin.o)
+__ledf2                                           /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+__libc_fini_array                                 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-fini.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+__libc_init_array                                 /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-init.o)
+                                                  build/startup_stm32g431xx.o
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+__ltdf2                                           /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+__muldf3                                          /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldivdf3.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldf3.o)
+__nedf2                                           /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o)
+__on_exit_args                                    /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-__atexit.o)
+__preinit_array_end                               /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-init.o)
+__preinit_array_start                             /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-init.o)
+__register_exitproc                               /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-__atexit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-atexit.o)
+__register_frame_info                             /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crtbegin.o
+__sf_fake_stderr                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-impure.o)
+__sf_fake_stdin                                   /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-impure.o)
+__sf_fake_stdout                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-impure.o)
+__stack                                           /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+__subdf3                                          /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o)
+__udivmoddi4                                      /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o)
+_ebss                                             build/startup_stm32g431xx.o
+_edata                                            build/startup_stm32g431xx.o
+_estack                                           build/startup_stm32g431xx.o
+_exit                                             /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a(_exit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-exit.o)
+_fini                                             /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crti.o
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-fini.o)
+_global_atexit                                    /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-__call_atexit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-__atexit.o)
+_global_impure_ptr                                /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-impure.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-exit.o)
+_impure_ptr                                       /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-impure.o)
+_init                                             /usr/lib/gcc/arm-none-eabi/12.2.1/thumb/v7e-m+fp/hard/crti.o
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-init.o)
+_mainCRTStartup                                   /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+_sbss                                             build/startup_stm32g431xx.o
+_sdata                                            build/startup_stm32g431xx.o
+_sidata                                           build/startup_stm32g431xx.o
+_stack_init                                       /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+_start                                            /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+atexit                                            /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-atexit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+audio_play                                        build/squeow.o
+display_buffer                                    build/squeow.o
+exit                                              /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-exit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+fabs                                              /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_fabs.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-e_rem_pio2.o)
+floor                                             /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_floor.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_rem_pio2.o)
+g_pfnVectors                                      build/startup_stm32g431xx.o
+hUsbDeviceFS                                      build/usb_device.o
+                                                  build/usbd_audio_if.o
+hadc1                                             build/main.o
+hadc2                                             build/main.o
+hardware_init_hook                                /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+hi2c1                                             build/main.o
+                                                  build/si5351.o
+hpcd_USB_FS                                       build/usbd_conf.o
+                                                  build/stm32g4xx_it.o
+htim2                                             build/main.o
+htim3                                             build/main.o
+                                                  build/stm32g4xx_it.o
+huart1                                            build/main.o
+main                                              build/main.o
+                                                  build/startup_stm32g431xx.o
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+malloc                                            /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-__atexit.o)
+memset                                            /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-memset.o)
+                                                  build/usbd_audio.o
+                                                  build/usbd_conf.o
+                                                  build/stm32g4xx_hal_msp.o
+                                                  build/main.o
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+oeb                                               build/si5351.o
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+                                                  build/stm32g4xx_hal_flash_ex.o
+pwm_value                                         build/squeow.o
+rails_number                                      build/squeow.o
+ringbuf_increment                                 build/squeow.o
+sample                                            build/squeow.o
+sample_value                                      build/squeow.o
+samples_ringbuf                                   build/squeow.o
+samples_ringbuf_input_index                       build/squeow.o
+samples_ringbuf_output_index                      build/squeow.o
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+scalbn                                            /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_scalbn.o)
+                                                  /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_rem_pio2.o)
+si5351_initialize                                 build/si5351.o
+                                                  build/main.o
+si5351_off_clk                                    build/si5351.o
+si5351_on_clk                                     build/si5351.o
+                                                  build/main.o
+si5351_read8                                      build/si5351.o
+si5351_set_frequency                              build/si5351.o
+                                                  build/main.o
+si5351_write8                                     build/si5351.o
+sin                                               /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-s_sin.o)
+                                                  build/squeow.o
+software_init_hook                                /usr/lib/gcc/arm-none-eabi/12.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
+stato_audio                                       build/squeow.o
+store_sample                                      build/squeow.o
+store_samples                                     build/squeow.o
+u12_sine                                          build/squeow.o
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+uwTickFreq                                        build/stm32g4xx_hal.o
+uwTickPrio                                        build/stm32g4xx_hal.o
+                                                  build/stm32g4xx_hal_rcc.o
diff --git a/squeow_sw/build/startup_stm32g431xx.d b/squeow_sw/build/startup_stm32g431xx.d
new file mode 100644
index 0000000..9054cbf
--- /dev/null
+++ b/squeow_sw/build/startup_stm32g431xx.d
@@ -0,0 +1 @@
+build/startup_stm32g431xx.o: startup_stm32g431xx.s
diff --git a/squeow_sw/build/startup_stm32g431xx.o b/squeow_sw/build/startup_stm32g431xx.o
new file mode 100644
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diff --git a/squeow_sw/build/stm32g4xx_hal.d b/squeow_sw/build/stm32g4xx_hal.d
new file mode 100644
index 0000000..1b38c73
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal.d
@@ -0,0 +1,73 @@
+build/stm32g4xx_hal.o: Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal.lst b/squeow_sw/build/stm32g4xx_hal.lst
new file mode 100644
index 0000000..8d53536
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal.lst
@@ -0,0 +1,2204 @@
+ARM GAS  /tmp/ccDAvPw5.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c"
+  20              		.section	.text.HAL_MspInit,"ax",%progbits
+  21              		.align	1
+  22              		.weak	HAL_MspInit
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	HAL_MspInit:
+  28              	.LFB331:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @file    stm32g4xx_hal.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief   HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *          This is the common part of the HAL initialization
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   ******************************************************************************
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @attention
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * Copyright (c) 2019 STMicroelectronics.
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * All rights reserved.
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * in the root directory of this software component.
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   ******************************************************************************
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   @verbatim
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   ==============================================================================
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****                      ##### How to use this driver #####
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   ==============================================================================
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     [..]
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     The common HAL driver contains a set of generic and common APIs that can be
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     used by the PPP peripheral drivers and the user to start using the HAL.
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     [..]
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     The HAL contains two APIs' categories:
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****          (+) Common HAL APIs
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****          (+) Services HAL APIs
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   @endverbatim
+ARM GAS  /tmp/ccDAvPw5.s 			page 2
+
+
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   ******************************************************************************
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /* Includes ------------------------------------------------------------------*/
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #include "stm32g4xx_hal.h"
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @{
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /** @defgroup HAL HAL
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief HAL module driver
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @{
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #ifdef HAL_MODULE_ENABLED
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /* Private typedef -----------------------------------------------------------*/
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /* Private define ------------------------------------------------------------*/
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief STM32G4xx HAL Driver version number V1.2.2
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define __STM32G4xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define __STM32G4xx_HAL_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define __STM32G4xx_HAL_VERSION_SUB2   (0x02U) /*!< [15:8]  sub2 version */
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define __STM32G4xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define __STM32G4xx_HAL_VERSION         ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****                                          |(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****                                          |(__STM32G4xx_HAL_VERSION_SUB2 << 8U )\
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****                                          |(__STM32G4xx_HAL_VERSION_RC))
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #if defined(VREFBUF)
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define VREFBUF_TIMEOUT_VALUE     10U   /* 10 ms */
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #endif /* VREFBUF */
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /* ------------ SYSCFG registers bit address in the alias region ------------ */
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /* ---  MEMRMP Register ---*/
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /* Alias word address of FB_MODE bit */
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define MEMRMP_OFFSET           SYSCFG_OFFSET
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define FB_MODE_BitNumber       ((uint8_t)0x8)
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define FB_MODE_BB              (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /* --- GPC Register ---*/
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /* Alias word address of CCMER bit */
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define SCSR_OFFSET             (SYSCFG_OFFSET + 0x18)
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define CCMER_BitNumber         ((uint8_t)0x0)
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #define SCSR_CCMER_BB           (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (CCMER_BitNumber * 4))
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /* Private macro -------------------------------------------------------------*/
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /* Exported variables ---------------------------------------------------------*/
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /** @defgroup HAL_Exported_Variables HAL Exported Variables
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @{
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** __IO uint32_t uwTick;
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+ARM GAS  /tmp/ccDAvPw5.s 			page 3
+
+
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @}
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /* Private function prototypes -----------------------------------------------*/
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /* Exported functions --------------------------------------------------------*/
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /** @defgroup HAL_Exported_Functions HAL Exported Functions
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @{
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *  @brief    HAL Initialization and de-initialization functions
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** @verbatim
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****  ===============================================================================
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****               ##### Initialization and Configuration functions #####
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****  ===============================================================================
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     [..]  This section provides functions allowing to:
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Initialize the Flash interface the NVIC allocation and initial time base
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****           clock configuration.
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) De-Initialize common part of the HAL.
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Configure the time base source to have 1ms time base with a dedicated
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****           Tick interrupt priority.
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****         (++) SysTick timer is used by default as source of time base, but user
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****              can eventually implement his proper time base source (a general purpose
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****              timer for example or other time source), keeping in mind that Time base
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****              duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****              handled in milliseconds basis.
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****         (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****              at the beginning of the program after reset by HAL_Init() or at any time
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****              when clock is configured, by HAL_RCC_ClockConfig().
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****         (++) Source of time base is configured  to generate interrupts at regular
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****              time intervals. Care must be taken if HAL_Delay() is called from a
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****              peripheral ISR process, the Tick interrupt line must have higher priority
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****             (numerically lower) than the peripheral interrupt. Otherwise the caller
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****             ISR process will be blocked.
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****        (++) functions affecting time base configurations are declared as __weak
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****              to make  override possible  in case of other  implementations in user file.
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** @endverbatim
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @{
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  This function is used to configure the Flash prefetch, the Instruction and Data caches,
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *         the time base source, NVIC and any required global low level hardware
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *         by calling the HAL_MspInit() callback function to be optionally defined in user file
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *         stm32g4xx_hal_msp.c.
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note   HAL_Init() function is called at the beginning of program after reset and before
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *         the clock configuration.
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note   In the default implementation the System Timer (Systick) is used as source of time base
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *         The Systick configuration is based on HSI clock, as HSI is the clock
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *         used after a system Reset and the NVIC configuration is set to Priority group 4.
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *         Once done, time base tick starts incrementing: the tick variable counter is incremented
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *         each 1ms in the SysTick_Handler() interrupt handler.
+ARM GAS  /tmp/ccDAvPw5.s 			page 4
+
+
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval HAL status
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** HAL_StatusTypeDef HAL_Init(void)
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   HAL_StatusTypeDef  status = HAL_OK;
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Configure Flash prefetch, Instruction cache, Data cache */
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Default configuration at reset is:                      */
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* - Prefetch disabled                                     */
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* - Instruction cache enabled                             */
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* - Data cache enabled                                    */
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #if (INSTRUCTION_CACHE_ENABLE == 0U)
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #endif /* INSTRUCTION_CACHE_ENABLE */
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #if (DATA_CACHE_ENABLE == 0U)
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_FLASH_DATA_CACHE_DISABLE();
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #endif /* DATA_CACHE_ENABLE */
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #if (PREFETCH_ENABLE != 0U)
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #endif /* PREFETCH_ENABLE */
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Set Interrupt Group Priority */
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     status = HAL_ERROR;
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   }
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   else
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     /* Init the low level hardware */
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     HAL_MspInit();
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   }
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Return function status */
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   return status;
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  This function de-initializes common part of the HAL and stops the source of time base.
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note   This function is optional.
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval HAL status
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** HAL_StatusTypeDef HAL_DeInit(void)
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Reset of all peripherals */
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_APB1_FORCE_RESET();
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_APB1_RELEASE_RESET();
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_APB2_FORCE_RESET();
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_APB2_RELEASE_RESET();
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_AHB1_FORCE_RESET();
+ARM GAS  /tmp/ccDAvPw5.s 			page 5
+
+
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_AHB1_RELEASE_RESET();
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_AHB2_FORCE_RESET();
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_AHB2_RELEASE_RESET();
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_AHB3_FORCE_RESET();
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_AHB3_RELEASE_RESET();
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* De-Init the low level hardware */
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   HAL_MspDeInit();
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Return function status */
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   return HAL_OK;
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Initialize the MSP.
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** __weak void HAL_MspInit(void)
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+  29              		.loc 1 222 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****             the HAL_MspInit could be implemented in the user file
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****    */
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+  34              		.loc 1 226 1 view .LVU1
+  35 0000 7047     		bx	lr
+  36              		.cfi_endproc
+  37              	.LFE331:
+  39              		.section	.text.HAL_MspDeInit,"ax",%progbits
+  40              		.align	1
+  41              		.weak	HAL_MspDeInit
+  42              		.syntax unified
+  43              		.thumb
+  44              		.thumb_func
+  46              	HAL_MspDeInit:
+  47              	.LFB332:
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  DeInitializes the MSP.
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** __weak void HAL_MspDeInit(void)
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+  48              		.loc 1 233 1 view -0
+  49              		.cfi_startproc
+  50              		@ args = 0, pretend = 0, frame = 0
+  51              		@ frame_needed = 0, uses_anonymous_args = 0
+  52              		@ link register save eliminated.
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****             the HAL_MspDeInit could be implemented in the user file
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****    */
+ARM GAS  /tmp/ccDAvPw5.s 			page 6
+
+
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+  53              		.loc 1 237 1 view .LVU3
+  54 0000 7047     		bx	lr
+  55              		.cfi_endproc
+  56              	.LFE332:
+  58              		.section	.text.HAL_DeInit,"ax",%progbits
+  59              		.align	1
+  60              		.global	HAL_DeInit
+  61              		.syntax unified
+  62              		.thumb
+  63              		.thumb_func
+  65              	HAL_DeInit:
+  66              	.LFB330:
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Reset of all peripherals */
+  67              		.loc 1 193 1 view -0
+  68              		.cfi_startproc
+  69              		@ args = 0, pretend = 0, frame = 0
+  70              		@ frame_needed = 0, uses_anonymous_args = 0
+  71 0000 10B5     		push	{r4, lr}
+  72              	.LCFI0:
+  73              		.cfi_def_cfa_offset 8
+  74              		.cfi_offset 4, -8
+  75              		.cfi_offset 14, -4
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_APB1_RELEASE_RESET();
+  76              		.loc 1 195 3 view .LVU5
+  77 0002 094B     		ldr	r3, .L5
+  78 0004 4FF0FF32 		mov	r2, #-1
+  79 0008 9A63     		str	r2, [r3, #56]
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  80              		.loc 1 196 3 view .LVU6
+  81 000a 0024     		movs	r4, #0
+  82 000c 9C63     		str	r4, [r3, #56]
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_APB2_RELEASE_RESET();
+  83              		.loc 1 198 3 view .LVU7
+  84 000e 1A64     		str	r2, [r3, #64]
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  85              		.loc 1 199 3 view .LVU8
+  86 0010 1C64     		str	r4, [r3, #64]
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_AHB1_RELEASE_RESET();
+  87              		.loc 1 201 3 view .LVU9
+  88 0012 9A62     		str	r2, [r3, #40]
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  89              		.loc 1 202 3 view .LVU10
+  90 0014 9C62     		str	r4, [r3, #40]
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_AHB2_RELEASE_RESET();
+  91              		.loc 1 204 3 view .LVU11
+  92 0016 DA62     		str	r2, [r3, #44]
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  93              		.loc 1 205 3 view .LVU12
+  94 0018 DC62     		str	r4, [r3, #44]
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   __HAL_RCC_AHB3_RELEASE_RESET();
+  95              		.loc 1 207 3 view .LVU13
+  96 001a 1A63     		str	r2, [r3, #48]
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+  97              		.loc 1 208 3 view .LVU14
+  98 001c 1C63     		str	r4, [r3, #48]
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ARM GAS  /tmp/ccDAvPw5.s 			page 7
+
+
+  99              		.loc 1 211 3 view .LVU15
+ 100 001e FFF7FEFF 		bl	HAL_MspDeInit
+ 101              	.LVL0:
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 102              		.loc 1 214 3 view .LVU16
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 103              		.loc 1 215 1 is_stmt 0 view .LVU17
+ 104 0022 2046     		mov	r0, r4
+ 105 0024 10BD     		pop	{r4, pc}
+ 106              	.L6:
+ 107 0026 00BF     		.align	2
+ 108              	.L5:
+ 109 0028 00100240 		.word	1073876992
+ 110              		.cfi_endproc
+ 111              	.LFE330:
+ 113              		.section	.text.HAL_InitTick,"ax",%progbits
+ 114              		.align	1
+ 115              		.weak	HAL_InitTick
+ 116              		.syntax unified
+ 117              		.thumb
+ 118              		.thumb_func
+ 120              	HAL_InitTick:
+ 121              	.LVL1:
+ 122              	.LFB333:
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief This function configures the source of the time base:
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *        The time source is configured to have 1ms time base with a dedicated
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *        Tick interrupt priority.
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note This function is called  automatically at the beginning of program after
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note In the default implementation, SysTick timer is the source of time base.
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       It is used to generate interrupts at regular time intervals.
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       The SysTick interrupt must have higher priority (numerically lower)
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       The function is declared as __weak  to be overwritten  in case of other
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       implementation  in user file.
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @param TickPriority: Tick interrupt priority.
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval HAL status
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 123              		.loc 1 256 1 is_stmt 1 view -0
+ 124              		.cfi_startproc
+ 125              		@ args = 0, pretend = 0, frame = 0
+ 126              		@ frame_needed = 0, uses_anonymous_args = 0
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   HAL_StatusTypeDef  status = HAL_OK;
+ 127              		.loc 1 257 3 view .LVU19
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   if (uwTickFreq != 0U)
+ 128              		.loc 1 259 3 view .LVU20
+ 129              		.loc 1 259 18 is_stmt 0 view .LVU21
+ 130 0000 104B     		ldr	r3, .L18
+ 131 0002 1B68     		ldr	r3, [r3]
+ 132              		.loc 1 259 6 view .LVU22
+ 133 0004 0BB9     		cbnz	r3, .L16
+ARM GAS  /tmp/ccDAvPw5.s 			page 8
+
+
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     /* Configure the SysTick to have interrupt in 1ms time basis*/
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     {
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       /* Configure the SysTick IRQ priority */
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       {
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****         HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****         uwTickPrio = TickPriority;
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       }
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       else
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       {
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****         status = HAL_ERROR;
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       }
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     }
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     else
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     {
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       status = HAL_ERROR;
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     }
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   }
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   else
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     status = HAL_ERROR;
+ 134              		.loc 1 282 12 view .LVU23
+ 135 0006 0120     		movs	r0, #1
+ 136              	.LVL2:
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   }
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Return function status */
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   return status;
+ 137              		.loc 1 286 3 is_stmt 1 view .LVU24
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 138              		.loc 1 287 1 is_stmt 0 view .LVU25
+ 139 0008 7047     		bx	lr
+ 140              	.LVL3:
+ 141              	.L16:
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   HAL_StatusTypeDef  status = HAL_OK;
+ 142              		.loc 1 256 1 view .LVU26
+ 143 000a 10B5     		push	{r4, lr}
+ 144              	.LCFI1:
+ 145              		.cfi_def_cfa_offset 8
+ 146              		.cfi_offset 4, -8
+ 147              		.cfi_offset 14, -4
+ 148 000c 0446     		mov	r4, r0
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     {
+ 149              		.loc 1 262 5 is_stmt 1 view .LVU27
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     {
+ 150              		.loc 1 262 53 is_stmt 0 view .LVU28
+ 151 000e 4FF47A70 		mov	r0, #1000
+ 152              	.LVL4:
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     {
+ 153              		.loc 1 262 53 view .LVU29
+ 154 0012 B0FBF3F3 		udiv	r3, r0, r3
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     {
+ 155              		.loc 1 262 9 view .LVU30
+ 156 0016 0C4A     		ldr	r2, .L18+4
+ 157 0018 1068     		ldr	r0, [r2]
+ARM GAS  /tmp/ccDAvPw5.s 			page 9
+
+
+ 158 001a B0FBF3F0 		udiv	r0, r0, r3
+ 159 001e FFF7FEFF 		bl	HAL_SYSTICK_Config
+ 160              	.LVL5:
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     {
+ 161              		.loc 1 262 8 view .LVU31
+ 162 0022 68B9     		cbnz	r0, .L10
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       {
+ 163              		.loc 1 265 7 is_stmt 1 view .LVU32
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       {
+ 164              		.loc 1 265 10 is_stmt 0 view .LVU33
+ 165 0024 0F2C     		cmp	r4, #15
+ 166 0026 01D9     		bls	.L17
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       }
+ 167              		.loc 1 272 16 view .LVU34
+ 168 0028 0120     		movs	r0, #1
+ 169 002a 0AE0     		b	.L8
+ 170              	.L17:
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****         uwTickPrio = TickPriority;
+ 171              		.loc 1 267 9 is_stmt 1 view .LVU35
+ 172 002c 0022     		movs	r2, #0
+ 173 002e 2146     		mov	r1, r4
+ 174 0030 4FF0FF30 		mov	r0, #-1
+ 175 0034 FFF7FEFF 		bl	HAL_NVIC_SetPriority
+ 176              	.LVL6:
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       }
+ 177              		.loc 1 268 9 view .LVU36
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       }
+ 178              		.loc 1 268 20 is_stmt 0 view .LVU37
+ 179 0038 044B     		ldr	r3, .L18+8
+ 180 003a 1C60     		str	r4, [r3]
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 181              		.loc 1 257 22 view .LVU38
+ 182 003c 0020     		movs	r0, #0
+ 183 003e 00E0     		b	.L8
+ 184              	.L10:
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     }
+ 185              		.loc 1 277 14 view .LVU39
+ 186 0040 0120     		movs	r0, #1
+ 187              	.L8:
+ 188              	.LVL7:
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 189              		.loc 1 286 3 is_stmt 1 view .LVU40
+ 190              		.loc 1 287 1 is_stmt 0 view .LVU41
+ 191 0042 10BD     		pop	{r4, pc}
+ 192              	.LVL8:
+ 193              	.L19:
+ 194              		.loc 1 287 1 view .LVU42
+ 195              		.align	2
+ 196              	.L18:
+ 197 0044 00000000 		.word	uwTickFreq
+ 198 0048 00000000 		.word	SystemCoreClock
+ 199 004c 00000000 		.word	uwTickPrio
+ 200              		.cfi_endproc
+ 201              	.LFE333:
+ 203              		.section	.text.HAL_Init,"ax",%progbits
+ 204              		.align	1
+ 205              		.global	HAL_Init
+ARM GAS  /tmp/ccDAvPw5.s 			page 10
+
+
+ 206              		.syntax unified
+ 207              		.thumb
+ 208              		.thumb_func
+ 210              	HAL_Init:
+ 211              	.LFB329:
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   HAL_StatusTypeDef  status = HAL_OK;
+ 212              		.loc 1 149 1 is_stmt 1 view -0
+ 213              		.cfi_startproc
+ 214              		@ args = 0, pretend = 0, frame = 0
+ 215              		@ frame_needed = 0, uses_anonymous_args = 0
+ 216 0000 10B5     		push	{r4, lr}
+ 217              	.LCFI2:
+ 218              		.cfi_def_cfa_offset 8
+ 219              		.cfi_offset 4, -8
+ 220              		.cfi_offset 14, -4
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Configure Flash prefetch, Instruction cache, Data cache */
+ 221              		.loc 1 150 3 view .LVU44
+ 222              	.LVL9:
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 223              		.loc 1 169 3 view .LVU45
+ 224 0002 0320     		movs	r0, #3
+ 225 0004 FFF7FEFF 		bl	HAL_NVIC_SetPriorityGrouping
+ 226              	.LVL10:
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 227              		.loc 1 172 3 view .LVU46
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 228              		.loc 1 172 7 is_stmt 0 view .LVU47
+ 229 0008 0020     		movs	r0, #0
+ 230 000a FFF7FEFF 		bl	HAL_InitTick
+ 231              	.LVL11:
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 232              		.loc 1 172 6 view .LVU48
+ 233 000e 10B1     		cbz	r0, .L24
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   }
+ 234              		.loc 1 174 12 view .LVU49
+ 235 0010 0124     		movs	r4, #1
+ 236              	.L21:
+ 237              	.LVL12:
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 238              		.loc 1 183 3 is_stmt 1 view .LVU50
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 239              		.loc 1 185 1 is_stmt 0 view .LVU51
+ 240 0012 2046     		mov	r0, r4
+ 241 0014 10BD     		pop	{r4, pc}
+ 242              	.LVL13:
+ 243              	.L24:
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 244              		.loc 1 185 1 view .LVU52
+ 245 0016 0446     		mov	r4, r0
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   }
+ 246              		.loc 1 179 5 is_stmt 1 view .LVU53
+ 247 0018 FFF7FEFF 		bl	HAL_MspInit
+ 248              	.LVL14:
+ 249 001c F9E7     		b	.L21
+ 250              		.cfi_endproc
+ 251              	.LFE329:
+ 253              		.section	.text.HAL_IncTick,"ax",%progbits
+ARM GAS  /tmp/ccDAvPw5.s 			page 11
+
+
+ 254              		.align	1
+ 255              		.weak	HAL_IncTick
+ 256              		.syntax unified
+ 257              		.thumb
+ 258              		.thumb_func
+ 260              	HAL_IncTick:
+ 261              	.LFB334:
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @}
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *  @brief    HAL Control functions
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** @verbatim
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****  ===============================================================================
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****                       ##### HAL Control functions #####
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****  ===============================================================================
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     [..]  This section provides functions allowing to:
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Provide a tick value in millisecond
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Provide a blocking delay in millisecond
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Suspend the time base source interrupt
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Resume the time base source interrupt
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Get the HAL API driver version
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Get the device identifier
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Get the device revision identifier
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** @endverbatim
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @{
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief This function is called to increment a global variable "uwTick"
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *        used as application time base.
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note In the default implementation, this variable is incremented each 1ms
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       in SysTick ISR.
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note This function is declared as __weak to be overwritten in case of other
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *      implementations in user file.
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** __weak void HAL_IncTick(void)
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 262              		.loc 1 323 1 view -0
+ 263              		.cfi_startproc
+ 264              		@ args = 0, pretend = 0, frame = 0
+ 265              		@ frame_needed = 0, uses_anonymous_args = 0
+ 266              		@ link register save eliminated.
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   uwTick += uwTickFreq;
+ 267              		.loc 1 324 3 view .LVU55
+ 268              		.loc 1 324 10 is_stmt 0 view .LVU56
+ 269 0000 034A     		ldr	r2, .L26
+ 270 0002 1368     		ldr	r3, [r2]
+ 271 0004 0349     		ldr	r1, .L26+4
+ 272 0006 0968     		ldr	r1, [r1]
+ 273 0008 0B44     		add	r3, r3, r1
+ 274 000a 1360     		str	r3, [r2]
+ARM GAS  /tmp/ccDAvPw5.s 			page 12
+
+
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 275              		.loc 1 325 1 view .LVU57
+ 276 000c 7047     		bx	lr
+ 277              	.L27:
+ 278 000e 00BF     		.align	2
+ 279              	.L26:
+ 280 0010 00000000 		.word	uwTick
+ 281 0014 00000000 		.word	uwTickFreq
+ 282              		.cfi_endproc
+ 283              	.LFE334:
+ 285              		.section	.text.HAL_GetTick,"ax",%progbits
+ 286              		.align	1
+ 287              		.weak	HAL_GetTick
+ 288              		.syntax unified
+ 289              		.thumb
+ 290              		.thumb_func
+ 292              	HAL_GetTick:
+ 293              	.LFB335:
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief Provides a tick value in millisecond.
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note This function is declared as __weak to be overwritten in case of other
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       implementations in user file.
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval tick value
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** __weak uint32_t HAL_GetTick(void)
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 294              		.loc 1 334 1 is_stmt 1 view -0
+ 295              		.cfi_startproc
+ 296              		@ args = 0, pretend = 0, frame = 0
+ 297              		@ frame_needed = 0, uses_anonymous_args = 0
+ 298              		@ link register save eliminated.
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   return uwTick;
+ 299              		.loc 1 335 3 view .LVU59
+ 300              		.loc 1 335 10 is_stmt 0 view .LVU60
+ 301 0000 014B     		ldr	r3, .L29
+ 302 0002 1868     		ldr	r0, [r3]
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 303              		.loc 1 336 1 view .LVU61
+ 304 0004 7047     		bx	lr
+ 305              	.L30:
+ 306 0006 00BF     		.align	2
+ 307              	.L29:
+ 308 0008 00000000 		.word	uwTick
+ 309              		.cfi_endproc
+ 310              	.LFE335:
+ 312              		.section	.text.HAL_GetTickPrio,"ax",%progbits
+ 313              		.align	1
+ 314              		.global	HAL_GetTickPrio
+ 315              		.syntax unified
+ 316              		.thumb
+ 317              		.thumb_func
+ 319              	HAL_GetTickPrio:
+ 320              	.LFB336:
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief This function returns a tick priority.
+ARM GAS  /tmp/ccDAvPw5.s 			page 13
+
+
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval tick priority
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** uint32_t HAL_GetTickPrio(void)
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 321              		.loc 1 343 1 is_stmt 1 view -0
+ 322              		.cfi_startproc
+ 323              		@ args = 0, pretend = 0, frame = 0
+ 324              		@ frame_needed = 0, uses_anonymous_args = 0
+ 325              		@ link register save eliminated.
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   return uwTickPrio;
+ 326              		.loc 1 344 3 view .LVU63
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 327              		.loc 1 345 1 is_stmt 0 view .LVU64
+ 328 0000 014B     		ldr	r3, .L32
+ 329 0002 1868     		ldr	r0, [r3]
+ 330 0004 7047     		bx	lr
+ 331              	.L33:
+ 332 0006 00BF     		.align	2
+ 333              	.L32:
+ 334 0008 00000000 		.word	uwTickPrio
+ 335              		.cfi_endproc
+ 336              	.LFE336:
+ 338              		.section	.text.HAL_SetTickFreq,"ax",%progbits
+ 339              		.align	1
+ 340              		.global	HAL_SetTickFreq
+ 341              		.syntax unified
+ 342              		.thumb
+ 343              		.thumb_func
+ 345              	HAL_SetTickFreq:
+ 346              	.LVL15:
+ 347              	.LFB337:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief Set new tick Freq.
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval status
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 348              		.loc 1 352 1 is_stmt 1 view -0
+ 349              		.cfi_startproc
+ 350              		@ args = 0, pretend = 0, frame = 0
+ 351              		@ frame_needed = 0, uses_anonymous_args = 0
+ 352              		.loc 1 352 1 is_stmt 0 view .LVU66
+ 353 0000 10B5     		push	{r4, lr}
+ 354              	.LCFI3:
+ 355              		.cfi_def_cfa_offset 8
+ 356              		.cfi_offset 4, -8
+ 357              		.cfi_offset 14, -4
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   HAL_StatusTypeDef status  = HAL_OK;
+ 358              		.loc 1 353 3 is_stmt 1 view .LVU67
+ 359              	.LVL16:
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   uint32_t prevTickFreq;
+ 360              		.loc 1 354 3 view .LVU68
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   assert_param(IS_TICKFREQ(Freq));
+ 361              		.loc 1 356 3 view .LVU69
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ARM GAS  /tmp/ccDAvPw5.s 			page 14
+
+
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   if (uwTickFreq != Freq)
+ 362              		.loc 1 358 3 view .LVU70
+ 363              		.loc 1 358 18 is_stmt 0 view .LVU71
+ 364 0002 084B     		ldr	r3, .L39
+ 365 0004 1C68     		ldr	r4, [r3]
+ 366              		.loc 1 358 6 view .LVU72
+ 367 0006 8442     		cmp	r4, r0
+ 368 0008 01D1     		bne	.L38
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   uint32_t prevTickFreq;
+ 369              		.loc 1 353 21 view .LVU73
+ 370 000a 0020     		movs	r0, #0
+ 371              	.LVL17:
+ 372              	.L35:
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     /* Back up uwTickFreq frequency */
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     prevTickFreq = uwTickFreq;
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     /* Update uwTickFreq global variable used by HAL_InitTick() */
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     uwTickFreq = Freq;
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     /* Apply the new tick Freq  */
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     status = HAL_InitTick(uwTickPrio);
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     if (status != HAL_OK)
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     {
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       /* Restore previous tick frequency */
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       uwTickFreq = prevTickFreq;
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     }
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   }
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   return status;
+ 373              		.loc 1 376 3 is_stmt 1 view .LVU74
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 374              		.loc 1 377 1 is_stmt 0 view .LVU75
+ 375 000c 10BD     		pop	{r4, pc}
+ 376              	.LVL18:
+ 377              	.L38:
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 378              		.loc 1 361 5 is_stmt 1 view .LVU76
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 379              		.loc 1 364 5 view .LVU77
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 380              		.loc 1 364 16 is_stmt 0 view .LVU78
+ 381 000e 1860     		str	r0, [r3]
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 382              		.loc 1 367 5 is_stmt 1 view .LVU79
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 383              		.loc 1 367 14 is_stmt 0 view .LVU80
+ 384 0010 054B     		ldr	r3, .L39+4
+ 385 0012 1868     		ldr	r0, [r3]
+ 386              	.LVL19:
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 387              		.loc 1 367 14 view .LVU81
+ 388 0014 FFF7FEFF 		bl	HAL_InitTick
+ 389              	.LVL20:
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     {
+ 390              		.loc 1 369 5 is_stmt 1 view .LVU82
+ARM GAS  /tmp/ccDAvPw5.s 			page 15
+
+
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     {
+ 391              		.loc 1 369 8 is_stmt 0 view .LVU83
+ 392 0018 0028     		cmp	r0, #0
+ 393 001a F7D0     		beq	.L35
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     }
+ 394              		.loc 1 372 7 is_stmt 1 view .LVU84
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     }
+ 395              		.loc 1 372 18 is_stmt 0 view .LVU85
+ 396 001c 014B     		ldr	r3, .L39
+ 397 001e 1C60     		str	r4, [r3]
+ 398 0020 F4E7     		b	.L35
+ 399              	.L40:
+ 400 0022 00BF     		.align	2
+ 401              	.L39:
+ 402 0024 00000000 		.word	uwTickFreq
+ 403 0028 00000000 		.word	uwTickPrio
+ 404              		.cfi_endproc
+ 405              	.LFE337:
+ 407              		.section	.text.HAL_GetTickFreq,"ax",%progbits
+ 408              		.align	1
+ 409              		.global	HAL_GetTickFreq
+ 410              		.syntax unified
+ 411              		.thumb
+ 412              		.thumb_func
+ 414              	HAL_GetTickFreq:
+ 415              	.LFB338:
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief Returns tick frequency.
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval tick period in Hz
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** uint32_t HAL_GetTickFreq(void)
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 416              		.loc 1 384 1 is_stmt 1 view -0
+ 417              		.cfi_startproc
+ 418              		@ args = 0, pretend = 0, frame = 0
+ 419              		@ frame_needed = 0, uses_anonymous_args = 0
+ 420              		@ link register save eliminated.
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   return uwTickFreq;
+ 421              		.loc 1 385 3 view .LVU87
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 422              		.loc 1 386 1 is_stmt 0 view .LVU88
+ 423 0000 014B     		ldr	r3, .L42
+ 424 0002 1868     		ldr	r0, [r3]
+ 425 0004 7047     		bx	lr
+ 426              	.L43:
+ 427 0006 00BF     		.align	2
+ 428              	.L42:
+ 429 0008 00000000 		.word	uwTickFreq
+ 430              		.cfi_endproc
+ 431              	.LFE338:
+ 433              		.section	.text.HAL_Delay,"ax",%progbits
+ 434              		.align	1
+ 435              		.weak	HAL_Delay
+ 436              		.syntax unified
+ 437              		.thumb
+ 438              		.thumb_func
+ARM GAS  /tmp/ccDAvPw5.s 			page 16
+
+
+ 440              	HAL_Delay:
+ 441              	.LVL21:
+ 442              	.LFB339:
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief This function provides minimum delay (in milliseconds) based
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *        on variable incremented.
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note In the default implementation , SysTick timer is the source of time base.
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       It is used to generate interrupts at regular time intervals where uwTick
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       is incremented.
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note This function is declared as __weak to be overwritten in case of other
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       implementations in user file.
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @param Delay specifies the delay time length, in milliseconds.
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** __weak void HAL_Delay(uint32_t Delay)
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 443              		.loc 1 400 1 is_stmt 1 view -0
+ 444              		.cfi_startproc
+ 445              		@ args = 0, pretend = 0, frame = 0
+ 446              		@ frame_needed = 0, uses_anonymous_args = 0
+ 447              		.loc 1 400 1 is_stmt 0 view .LVU90
+ 448 0000 38B5     		push	{r3, r4, r5, lr}
+ 449              	.LCFI4:
+ 450              		.cfi_def_cfa_offset 16
+ 451              		.cfi_offset 3, -16
+ 452              		.cfi_offset 4, -12
+ 453              		.cfi_offset 5, -8
+ 454              		.cfi_offset 14, -4
+ 455 0002 0446     		mov	r4, r0
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   uint32_t tickstart = HAL_GetTick();
+ 456              		.loc 1 401 3 is_stmt 1 view .LVU91
+ 457              		.loc 1 401 24 is_stmt 0 view .LVU92
+ 458 0004 FFF7FEFF 		bl	HAL_GetTick
+ 459              	.LVL22:
+ 460              		.loc 1 401 24 view .LVU93
+ 461 0008 0546     		mov	r5, r0
+ 462              	.LVL23:
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   uint32_t wait = Delay;
+ 463              		.loc 1 402 3 is_stmt 1 view .LVU94
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Add a freq to guarantee minimum wait */
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   if (wait < HAL_MAX_DELAY)
+ 464              		.loc 1 405 3 view .LVU95
+ 465              		.loc 1 405 6 is_stmt 0 view .LVU96
+ 466 000a B4F1FF3F 		cmp	r4, #-1
+ 467 000e 02D0     		beq	.L46
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     wait += (uint32_t)(uwTickFreq);
+ 468              		.loc 1 407 5 is_stmt 1 view .LVU97
+ 469              		.loc 1 407 13 is_stmt 0 view .LVU98
+ 470 0010 044B     		ldr	r3, .L48
+ 471 0012 1B68     		ldr	r3, [r3]
+ 472              		.loc 1 407 10 view .LVU99
+ 473 0014 1C44     		add	r4, r4, r3
+ 474              	.LVL24:
+ 475              	.L46:
+ARM GAS  /tmp/ccDAvPw5.s 			page 17
+
+
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   }
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   while ((HAL_GetTick() - tickstart) < wait)
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   }
+ 476              		.loc 1 412 3 is_stmt 1 discriminator 1 view .LVU100
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 477              		.loc 1 410 38 discriminator 1 view .LVU101
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 478              		.loc 1 410 11 is_stmt 0 discriminator 1 view .LVU102
+ 479 0016 FFF7FEFF 		bl	HAL_GetTick
+ 480              	.LVL25:
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 481              		.loc 1 410 25 discriminator 1 view .LVU103
+ 482 001a 401B     		subs	r0, r0, r5
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 483              		.loc 1 410 38 discriminator 1 view .LVU104
+ 484 001c A042     		cmp	r0, r4
+ 485 001e FAD3     		bcc	.L46
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 486              		.loc 1 413 1 view .LVU105
+ 487 0020 38BD     		pop	{r3, r4, r5, pc}
+ 488              	.LVL26:
+ 489              	.L49:
+ 490              		.loc 1 413 1 view .LVU106
+ 491 0022 00BF     		.align	2
+ 492              	.L48:
+ 493 0024 00000000 		.word	uwTickFreq
+ 494              		.cfi_endproc
+ 495              	.LFE339:
+ 497              		.section	.text.HAL_SuspendTick,"ax",%progbits
+ 498              		.align	1
+ 499              		.weak	HAL_SuspendTick
+ 500              		.syntax unified
+ 501              		.thumb
+ 502              		.thumb_func
+ 504              	HAL_SuspendTick:
+ 505              	.LFB340:
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief Suspends Tick increment.
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note In the default implementation , SysTick timer is the source of time base. It is
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       is called, the SysTick interrupt will be disabled and so Tick increment
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       is suspended.
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note This function is declared as __weak to be overwritten in case of other
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       implementations in user file.
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** __weak void HAL_SuspendTick(void)
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 506              		.loc 1 426 1 is_stmt 1 view -0
+ 507              		.cfi_startproc
+ 508              		@ args = 0, pretend = 0, frame = 0
+ 509              		@ frame_needed = 0, uses_anonymous_args = 0
+ 510              		@ link register save eliminated.
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Disable SysTick Interrupt */
+ARM GAS  /tmp/ccDAvPw5.s 			page 18
+
+
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+ 511              		.loc 1 428 3 view .LVU108
+ 512 0000 4FF0E022 		mov	r2, #-536813568
+ 513 0004 1369     		ldr	r3, [r2, #16]
+ 514 0006 23F00203 		bic	r3, r3, #2
+ 515 000a 1361     		str	r3, [r2, #16]
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 516              		.loc 1 429 1 is_stmt 0 view .LVU109
+ 517 000c 7047     		bx	lr
+ 518              		.cfi_endproc
+ 519              	.LFE340:
+ 521              		.section	.text.HAL_ResumeTick,"ax",%progbits
+ 522              		.align	1
+ 523              		.weak	HAL_ResumeTick
+ 524              		.syntax unified
+ 525              		.thumb
+ 526              		.thumb_func
+ 528              	HAL_ResumeTick:
+ 529              	.LFB341:
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief Resume Tick increment.
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note In the default implementation , SysTick timer is the source of time base. It is
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       is called, the SysTick interrupt will be enabled and so Tick increment
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       is resumed.
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note This function is declared as __weak to be overwritten in case of other
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *       implementations in user file.
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** __weak void HAL_ResumeTick(void)
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 530              		.loc 1 442 1 is_stmt 1 view -0
+ 531              		.cfi_startproc
+ 532              		@ args = 0, pretend = 0, frame = 0
+ 533              		@ frame_needed = 0, uses_anonymous_args = 0
+ 534              		@ link register save eliminated.
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Enable SysTick Interrupt */
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+ 535              		.loc 1 444 3 view .LVU111
+ 536 0000 4FF0E022 		mov	r2, #-536813568
+ 537 0004 1369     		ldr	r3, [r2, #16]
+ 538 0006 43F00203 		orr	r3, r3, #2
+ 539 000a 1361     		str	r3, [r2, #16]
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 540              		.loc 1 445 1 is_stmt 0 view .LVU112
+ 541 000c 7047     		bx	lr
+ 542              		.cfi_endproc
+ 543              	.LFE341:
+ 545              		.section	.text.HAL_GetHalVersion,"ax",%progbits
+ 546              		.align	1
+ 547              		.global	HAL_GetHalVersion
+ 548              		.syntax unified
+ 549              		.thumb
+ 550              		.thumb_func
+ 552              	HAL_GetHalVersion:
+ 553              	.LFB342:
+ARM GAS  /tmp/ccDAvPw5.s 			page 19
+
+
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Returns the HAL revision.
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** uint32_t HAL_GetHalVersion(void)
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 554              		.loc 1 452 1 is_stmt 1 view -0
+ 555              		.cfi_startproc
+ 556              		@ args = 0, pretend = 0, frame = 0
+ 557              		@ frame_needed = 0, uses_anonymous_args = 0
+ 558              		@ link register save eliminated.
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   return __STM32G4xx_HAL_VERSION;
+ 559              		.loc 1 453 3 view .LVU114
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 560              		.loc 1 454 1 is_stmt 0 view .LVU115
+ 561 0000 0048     		ldr	r0, .L53
+ 562 0002 7047     		bx	lr
+ 563              	.L54:
+ 564              		.align	2
+ 565              	.L53:
+ 566 0004 00020201 		.word	16908800
+ 567              		.cfi_endproc
+ 568              	.LFE342:
+ 570              		.section	.text.HAL_GetREVID,"ax",%progbits
+ 571              		.align	1
+ 572              		.global	HAL_GetREVID
+ 573              		.syntax unified
+ 574              		.thumb
+ 575              		.thumb_func
+ 577              	HAL_GetREVID:
+ 578              	.LFB343:
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Returns the device revision identifier.
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval Device revision identifier
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** uint32_t HAL_GetREVID(void)
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 579              		.loc 1 461 1 is_stmt 1 view -0
+ 580              		.cfi_startproc
+ 581              		@ args = 0, pretend = 0, frame = 0
+ 582              		@ frame_needed = 0, uses_anonymous_args = 0
+ 583              		@ link register save eliminated.
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16U);
+ 584              		.loc 1 462 3 view .LVU117
+ 585              		.loc 1 462 18 is_stmt 0 view .LVU118
+ 586 0000 014B     		ldr	r3, .L56
+ 587 0002 1868     		ldr	r0, [r3]
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 588              		.loc 1 463 1 view .LVU119
+ 589 0004 000C     		lsrs	r0, r0, #16
+ 590 0006 7047     		bx	lr
+ 591              	.L57:
+ 592              		.align	2
+ 593              	.L56:
+ 594 0008 002004E0 		.word	-536600576
+ARM GAS  /tmp/ccDAvPw5.s 			page 20
+
+
+ 595              		.cfi_endproc
+ 596              	.LFE343:
+ 598              		.section	.text.HAL_GetDEVID,"ax",%progbits
+ 599              		.align	1
+ 600              		.global	HAL_GetDEVID
+ 601              		.syntax unified
+ 602              		.thumb
+ 603              		.thumb_func
+ 605              	HAL_GetDEVID:
+ 606              	.LFB344:
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Returns the device identifier.
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval Device identifier
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** uint32_t HAL_GetDEVID(void)
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 607              		.loc 1 470 1 is_stmt 1 view -0
+ 608              		.cfi_startproc
+ 609              		@ args = 0, pretend = 0, frame = 0
+ 610              		@ frame_needed = 0, uses_anonymous_args = 0
+ 611              		@ link register save eliminated.
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
+ 612              		.loc 1 471 3 view .LVU121
+ 613              		.loc 1 471 17 is_stmt 0 view .LVU122
+ 614 0000 024B     		ldr	r3, .L59
+ 615 0002 1868     		ldr	r0, [r3]
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 616              		.loc 1 472 1 view .LVU123
+ 617 0004 C0F30B00 		ubfx	r0, r0, #0, #12
+ 618 0008 7047     		bx	lr
+ 619              	.L60:
+ 620 000a 00BF     		.align	2
+ 621              	.L59:
+ 622 000c 002004E0 		.word	-536600576
+ 623              		.cfi_endproc
+ 624              	.LFE344:
+ 626              		.section	.text.HAL_DBGMCU_EnableDBGSleepMode,"ax",%progbits
+ 627              		.align	1
+ 628              		.global	HAL_DBGMCU_EnableDBGSleepMode
+ 629              		.syntax unified
+ 630              		.thumb
+ 631              		.thumb_func
+ 633              	HAL_DBGMCU_EnableDBGSleepMode:
+ 634              	.LFB345:
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @}
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *  @brief    HAL Debug functions
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** @verbatim
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****  ===============================================================================
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****                       ##### HAL Debug functions #####
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****  ===============================================================================
+ARM GAS  /tmp/ccDAvPw5.s 			page 21
+
+
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     [..]  This section provides functions allowing to:
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Enable/Disable Debug module during SLEEP mode
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Enable/Disable Debug module during STANDBY mode
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** @endverbatim
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @{
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Enable the Debug Module during SLEEP mode.
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_DBGMCU_EnableDBGSleepMode(void)
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 635              		.loc 1 499 1 is_stmt 1 view -0
+ 636              		.cfi_startproc
+ 637              		@ args = 0, pretend = 0, frame = 0
+ 638              		@ frame_needed = 0, uses_anonymous_args = 0
+ 639              		@ link register save eliminated.
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+ 640              		.loc 1 500 3 view .LVU125
+ 641 0000 024A     		ldr	r2, .L62
+ 642 0002 5368     		ldr	r3, [r2, #4]
+ 643 0004 43F00103 		orr	r3, r3, #1
+ 644 0008 5360     		str	r3, [r2, #4]
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 645              		.loc 1 501 1 is_stmt 0 view .LVU126
+ 646 000a 7047     		bx	lr
+ 647              	.L63:
+ 648              		.align	2
+ 649              	.L62:
+ 650 000c 002004E0 		.word	-536600576
+ 651              		.cfi_endproc
+ 652              	.LFE345:
+ 654              		.section	.text.HAL_DBGMCU_DisableDBGSleepMode,"ax",%progbits
+ 655              		.align	1
+ 656              		.global	HAL_DBGMCU_DisableDBGSleepMode
+ 657              		.syntax unified
+ 658              		.thumb
+ 659              		.thumb_func
+ 661              	HAL_DBGMCU_DisableDBGSleepMode:
+ 662              	.LFB346:
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Disable the Debug Module during SLEEP mode.
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_DBGMCU_DisableDBGSleepMode(void)
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 663              		.loc 1 508 1 is_stmt 1 view -0
+ 664              		.cfi_startproc
+ 665              		@ args = 0, pretend = 0, frame = 0
+ 666              		@ frame_needed = 0, uses_anonymous_args = 0
+ 667              		@ link register save eliminated.
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+ 668              		.loc 1 509 3 view .LVU128
+ARM GAS  /tmp/ccDAvPw5.s 			page 22
+
+
+ 669 0000 024A     		ldr	r2, .L65
+ 670 0002 5368     		ldr	r3, [r2, #4]
+ 671 0004 23F00103 		bic	r3, r3, #1
+ 672 0008 5360     		str	r3, [r2, #4]
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 673              		.loc 1 510 1 is_stmt 0 view .LVU129
+ 674 000a 7047     		bx	lr
+ 675              	.L66:
+ 676              		.align	2
+ 677              	.L65:
+ 678 000c 002004E0 		.word	-536600576
+ 679              		.cfi_endproc
+ 680              	.LFE346:
+ 682              		.section	.text.HAL_DBGMCU_EnableDBGStopMode,"ax",%progbits
+ 683              		.align	1
+ 684              		.global	HAL_DBGMCU_EnableDBGStopMode
+ 685              		.syntax unified
+ 686              		.thumb
+ 687              		.thumb_func
+ 689              	HAL_DBGMCU_EnableDBGStopMode:
+ 690              	.LFB347:
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Enable the Debug Module during STOP0/STOP1/STOP2 modes.
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_DBGMCU_EnableDBGStopMode(void)
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 691              		.loc 1 517 1 is_stmt 1 view -0
+ 692              		.cfi_startproc
+ 693              		@ args = 0, pretend = 0, frame = 0
+ 694              		@ frame_needed = 0, uses_anonymous_args = 0
+ 695              		@ link register save eliminated.
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+ 696              		.loc 1 518 3 view .LVU131
+ 697 0000 024A     		ldr	r2, .L68
+ 698 0002 5368     		ldr	r3, [r2, #4]
+ 699 0004 43F00203 		orr	r3, r3, #2
+ 700 0008 5360     		str	r3, [r2, #4]
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 701              		.loc 1 519 1 is_stmt 0 view .LVU132
+ 702 000a 7047     		bx	lr
+ 703              	.L69:
+ 704              		.align	2
+ 705              	.L68:
+ 706 000c 002004E0 		.word	-536600576
+ 707              		.cfi_endproc
+ 708              	.LFE347:
+ 710              		.section	.text.HAL_DBGMCU_DisableDBGStopMode,"ax",%progbits
+ 711              		.align	1
+ 712              		.global	HAL_DBGMCU_DisableDBGStopMode
+ 713              		.syntax unified
+ 714              		.thumb
+ 715              		.thumb_func
+ 717              	HAL_DBGMCU_DisableDBGStopMode:
+ 718              	.LFB348:
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ARM GAS  /tmp/ccDAvPw5.s 			page 23
+
+
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Disable the Debug Module during STOP0/STOP1/STOP2 modes.
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_DBGMCU_DisableDBGStopMode(void)
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 719              		.loc 1 526 1 is_stmt 1 view -0
+ 720              		.cfi_startproc
+ 721              		@ args = 0, pretend = 0, frame = 0
+ 722              		@ frame_needed = 0, uses_anonymous_args = 0
+ 723              		@ link register save eliminated.
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+ 724              		.loc 1 527 3 view .LVU134
+ 725 0000 024A     		ldr	r2, .L71
+ 726 0002 5368     		ldr	r3, [r2, #4]
+ 727 0004 23F00203 		bic	r3, r3, #2
+ 728 0008 5360     		str	r3, [r2, #4]
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 729              		.loc 1 528 1 is_stmt 0 view .LVU135
+ 730 000a 7047     		bx	lr
+ 731              	.L72:
+ 732              		.align	2
+ 733              	.L71:
+ 734 000c 002004E0 		.word	-536600576
+ 735              		.cfi_endproc
+ 736              	.LFE348:
+ 738              		.section	.text.HAL_DBGMCU_EnableDBGStandbyMode,"ax",%progbits
+ 739              		.align	1
+ 740              		.global	HAL_DBGMCU_EnableDBGStandbyMode
+ 741              		.syntax unified
+ 742              		.thumb
+ 743              		.thumb_func
+ 745              	HAL_DBGMCU_EnableDBGStandbyMode:
+ 746              	.LFB349:
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Enable the Debug Module during STANDBY mode.
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_DBGMCU_EnableDBGStandbyMode(void)
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 747              		.loc 1 535 1 is_stmt 1 view -0
+ 748              		.cfi_startproc
+ 749              		@ args = 0, pretend = 0, frame = 0
+ 750              		@ frame_needed = 0, uses_anonymous_args = 0
+ 751              		@ link register save eliminated.
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+ 752              		.loc 1 536 3 view .LVU137
+ 753 0000 024A     		ldr	r2, .L74
+ 754 0002 5368     		ldr	r3, [r2, #4]
+ 755 0004 43F00403 		orr	r3, r3, #4
+ 756 0008 5360     		str	r3, [r2, #4]
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 757              		.loc 1 537 1 is_stmt 0 view .LVU138
+ 758 000a 7047     		bx	lr
+ 759              	.L75:
+ 760              		.align	2
+ARM GAS  /tmp/ccDAvPw5.s 			page 24
+
+
+ 761              	.L74:
+ 762 000c 002004E0 		.word	-536600576
+ 763              		.cfi_endproc
+ 764              	.LFE349:
+ 766              		.section	.text.HAL_DBGMCU_DisableDBGStandbyMode,"ax",%progbits
+ 767              		.align	1
+ 768              		.global	HAL_DBGMCU_DisableDBGStandbyMode
+ 769              		.syntax unified
+ 770              		.thumb
+ 771              		.thumb_func
+ 773              	HAL_DBGMCU_DisableDBGStandbyMode:
+ 774              	.LFB350:
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Disable the Debug Module during STANDBY mode.
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_DBGMCU_DisableDBGStandbyMode(void)
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 775              		.loc 1 544 1 is_stmt 1 view -0
+ 776              		.cfi_startproc
+ 777              		@ args = 0, pretend = 0, frame = 0
+ 778              		@ frame_needed = 0, uses_anonymous_args = 0
+ 779              		@ link register save eliminated.
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+ 780              		.loc 1 545 3 view .LVU140
+ 781 0000 024A     		ldr	r2, .L77
+ 782 0002 5368     		ldr	r3, [r2, #4]
+ 783 0004 23F00403 		bic	r3, r3, #4
+ 784 0008 5360     		str	r3, [r2, #4]
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 785              		.loc 1 546 1 is_stmt 0 view .LVU141
+ 786 000a 7047     		bx	lr
+ 787              	.L78:
+ 788              		.align	2
+ 789              	.L77:
+ 790 000c 002004E0 		.word	-536600576
+ 791              		.cfi_endproc
+ 792              	.LFE350:
+ 794              		.section	.text.HAL_SYSCFG_CCMSRAMErase,"ax",%progbits
+ 795              		.align	1
+ 796              		.global	HAL_SYSCFG_CCMSRAMErase
+ 797              		.syntax unified
+ 798              		.thumb
+ 799              		.thumb_func
+ 801              	HAL_SYSCFG_CCMSRAMErase:
+ 802              	.LFB351:
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @}
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *  @brief    HAL SYSCFG configuration functions
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** @verbatim
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****  ===============================================================================
+ARM GAS  /tmp/ccDAvPw5.s 			page 25
+
+
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****                       ##### HAL SYSCFG configuration functions #####
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****  ===============================================================================
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     [..]  This section provides functions allowing to:
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Start a hardware CCMSRAM erase operation
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Enable/Disable the Internal FLASH Bank Swapping
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Configure the Voltage reference buffer
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Enable/Disable the Voltage reference buffer
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       (+) Enable/Disable the I/O analog switch voltage booster
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** @endverbatim
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @{
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Start a hardware CCMSRAM erase operation.
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note   As long as CCMSRAM is not erased the CCMER bit will be set.
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *         This bit is automatically reset at the end of the CCMSRAM erase operation.
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_SYSCFG_CCMSRAMErase(void)
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 803              		.loc 1 577 1 is_stmt 1 view -0
+ 804              		.cfi_startproc
+ 805              		@ args = 0, pretend = 0, frame = 0
+ 806              		@ frame_needed = 0, uses_anonymous_args = 0
+ 807              		@ link register save eliminated.
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* unlock the write protection of the CCMER bit */
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   SYSCFG->SKR = 0xCA;
+ 808              		.loc 1 579 3 view .LVU143
+ 809              		.loc 1 579 15 is_stmt 0 view .LVU144
+ 810 0000 044B     		ldr	r3, .L80
+ 811 0002 CA22     		movs	r2, #202
+ 812 0004 5A62     		str	r2, [r3, #36]
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   SYSCFG->SKR = 0x53;
+ 813              		.loc 1 580 3 is_stmt 1 view .LVU145
+ 814              		.loc 1 580 15 is_stmt 0 view .LVU146
+ 815 0006 5322     		movs	r2, #83
+ 816 0008 5A62     		str	r2, [r3, #36]
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Starts a hardware CCMSRAM erase operation*/
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
+ 817              		.loc 1 582 3 is_stmt 1 view .LVU147
+ 818 000a 9A69     		ldr	r2, [r3, #24]
+ 819 000c 42F00102 		orr	r2, r2, #1
+ 820 0010 9A61     		str	r2, [r3, #24]
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 821              		.loc 1 583 1 is_stmt 0 view .LVU148
+ 822 0012 7047     		bx	lr
+ 823              	.L81:
+ 824              		.align	2
+ 825              	.L80:
+ 826 0014 00000140 		.word	1073807360
+ 827              		.cfi_endproc
+ 828              	.LFE351:
+ 830              		.section	.text.HAL_SYSCFG_EnableMemorySwappingBank,"ax",%progbits
+ 831              		.align	1
+ 832              		.global	HAL_SYSCFG_EnableMemorySwappingBank
+ 833              		.syntax unified
+ARM GAS  /tmp/ccDAvPw5.s 			page 26
+
+
+ 834              		.thumb
+ 835              		.thumb_func
+ 837              	HAL_SYSCFG_EnableMemorySwappingBank:
+ 838              	.LFB352:
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Enable the Internal FLASH Bank Swapping.
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note   This function can be used only for STM32G4xx devices.
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *         and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00040000)
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_SYSCFG_EnableMemorySwappingBank(void)
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 839              		.loc 1 596 1 is_stmt 1 view -0
+ 840              		.cfi_startproc
+ 841              		@ args = 0, pretend = 0, frame = 0
+ 842              		@ frame_needed = 0, uses_anonymous_args = 0
+ 843              		@ link register save eliminated.
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE);
+ 844              		.loc 1 597 3 view .LVU150
+ 845 0000 024A     		ldr	r2, .L83
+ 846 0002 1368     		ldr	r3, [r2]
+ 847 0004 43F48073 		orr	r3, r3, #256
+ 848 0008 1360     		str	r3, [r2]
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 849              		.loc 1 598 1 is_stmt 0 view .LVU151
+ 850 000a 7047     		bx	lr
+ 851              	.L84:
+ 852              		.align	2
+ 853              	.L83:
+ 854 000c 00000140 		.word	1073807360
+ 855              		.cfi_endproc
+ 856              	.LFE352:
+ 858              		.section	.text.HAL_SYSCFG_DisableMemorySwappingBank,"ax",%progbits
+ 859              		.align	1
+ 860              		.global	HAL_SYSCFG_DisableMemorySwappingBank
+ 861              		.syntax unified
+ 862              		.thumb
+ 863              		.thumb_func
+ 865              	HAL_SYSCFG_DisableMemorySwappingBank:
+ 866              	.LFB353:
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Disable the Internal FLASH Bank Swapping.
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note   This function can be used only for STM32G4xx devices.
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *         and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00040000)
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_SYSCFG_DisableMemorySwappingBank(void)
+ARM GAS  /tmp/ccDAvPw5.s 			page 27
+
+
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 867              		.loc 1 611 1 is_stmt 1 view -0
+ 868              		.cfi_startproc
+ 869              		@ args = 0, pretend = 0, frame = 0
+ 870              		@ frame_needed = 0, uses_anonymous_args = 0
+ 871              		@ link register save eliminated.
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE);
+ 872              		.loc 1 612 3 view .LVU153
+ 873 0000 024A     		ldr	r2, .L86
+ 874 0002 1368     		ldr	r3, [r2]
+ 875 0004 23F48073 		bic	r3, r3, #256
+ 876 0008 1360     		str	r3, [r2]
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 877              		.loc 1 613 1 is_stmt 0 view .LVU154
+ 878 000a 7047     		bx	lr
+ 879              	.L87:
+ 880              		.align	2
+ 881              	.L86:
+ 882 000c 00000140 		.word	1073807360
+ 883              		.cfi_endproc
+ 884              	.LFE353:
+ 886              		.section	.text.HAL_SYSCFG_VREFBUF_VoltageScalingConfig,"ax",%progbits
+ 887              		.align	1
+ 888              		.global	HAL_SYSCFG_VREFBUF_VoltageScalingConfig
+ 889              		.syntax unified
+ 890              		.thumb
+ 891              		.thumb_func
+ 893              	HAL_SYSCFG_VREFBUF_VoltageScalingConfig:
+ 894              	.LVL27:
+ 895              	.LFB354:
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #if defined(VREFBUF)
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief Configure the internal voltage reference buffer voltage scale.
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @param  VoltageScaling: specifies the output voltage to achieve
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *          This parameter can be one of the following values:
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREFBUF_OUT around 2.048 V.
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *                                                This requires VDDA equal to or higher than 2.4 V
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREFBUF_OUT around 2.5 V.
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *                                                This requires VDDA equal to or higher than 2.8 V
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREFBUF_OUT around 2.9 V.
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *                                                This requires VDDA equal to or higher than 3.15 
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 896              		.loc 1 629 1 is_stmt 1 view -0
+ 897              		.cfi_startproc
+ 898              		@ args = 0, pretend = 0, frame = 0
+ 899              		@ frame_needed = 0, uses_anonymous_args = 0
+ 900              		@ link register save eliminated.
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Check the parameters */
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+ 901              		.loc 1 631 3 view .LVU156
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+ 902              		.loc 1 633 3 view .LVU157
+ARM GAS  /tmp/ccDAvPw5.s 			page 28
+
+
+ 903 0000 034A     		ldr	r2, .L89
+ 904 0002 136B     		ldr	r3, [r2, #48]
+ 905 0004 23F03003 		bic	r3, r3, #48
+ 906 0008 0343     		orrs	r3, r3, r0
+ 907 000a 1363     		str	r3, [r2, #48]
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 908              		.loc 1 634 1 is_stmt 0 view .LVU158
+ 909 000c 7047     		bx	lr
+ 910              	.L90:
+ 911 000e 00BF     		.align	2
+ 912              	.L89:
+ 913 0010 00000140 		.word	1073807360
+ 914              		.cfi_endproc
+ 915              	.LFE354:
+ 917              		.section	.text.HAL_SYSCFG_VREFBUF_HighImpedanceConfig,"ax",%progbits
+ 918              		.align	1
+ 919              		.global	HAL_SYSCFG_VREFBUF_HighImpedanceConfig
+ 920              		.syntax unified
+ 921              		.thumb
+ 922              		.thumb_func
+ 924              	HAL_SYSCFG_VREFBUF_HighImpedanceConfig:
+ 925              	.LVL28:
+ 926              	.LFB355:
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief Configure the internal voltage reference buffer high impedance mode.
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @param  Mode: specifies the high impedance mode
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *          This parameter can be one of the following values:
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFI
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 927              		.loc 1 645 1 is_stmt 1 view -0
+ 928              		.cfi_startproc
+ 929              		@ args = 0, pretend = 0, frame = 0
+ 930              		@ frame_needed = 0, uses_anonymous_args = 0
+ 931              		@ link register save eliminated.
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Check the parameters */
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+ 932              		.loc 1 647 3 view .LVU160
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+ 933              		.loc 1 649 3 view .LVU161
+ 934 0000 034A     		ldr	r2, .L92
+ 935 0002 136B     		ldr	r3, [r2, #48]
+ 936 0004 23F00203 		bic	r3, r3, #2
+ 937 0008 0343     		orrs	r3, r3, r0
+ 938 000a 1363     		str	r3, [r2, #48]
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 939              		.loc 1 650 1 is_stmt 0 view .LVU162
+ 940 000c 7047     		bx	lr
+ 941              	.L93:
+ 942 000e 00BF     		.align	2
+ 943              	.L92:
+ 944 0010 00000140 		.word	1073807360
+ARM GAS  /tmp/ccDAvPw5.s 			page 29
+
+
+ 945              		.cfi_endproc
+ 946              	.LFE355:
+ 948              		.section	.text.HAL_SYSCFG_VREFBUF_TrimmingConfig,"ax",%progbits
+ 949              		.align	1
+ 950              		.global	HAL_SYSCFG_VREFBUF_TrimmingConfig
+ 951              		.syntax unified
+ 952              		.thumb
+ 953              		.thumb_func
+ 955              	HAL_SYSCFG_VREFBUF_TrimmingConfig:
+ 956              	.LVL29:
+ 957              	.LFB356:
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @param TrimmingValue specifies trimming code for VREFBUF calibration
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *        This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 958              		.loc 1 659 1 is_stmt 1 view -0
+ 959              		.cfi_startproc
+ 960              		@ args = 0, pretend = 0, frame = 0
+ 961              		@ frame_needed = 0, uses_anonymous_args = 0
+ 962              		@ link register save eliminated.
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Check the parameters */
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+ 963              		.loc 1 661 3 view .LVU164
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+ 964              		.loc 1 663 3 view .LVU165
+ 965 0000 034A     		ldr	r2, .L95
+ 966 0002 536B     		ldr	r3, [r2, #52]
+ 967 0004 23F03F03 		bic	r3, r3, #63
+ 968 0008 0343     		orrs	r3, r3, r0
+ 969 000a 5363     		str	r3, [r2, #52]
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 970              		.loc 1 664 1 is_stmt 0 view .LVU166
+ 971 000c 7047     		bx	lr
+ 972              	.L96:
+ 973 000e 00BF     		.align	2
+ 974              	.L95:
+ 975 0010 00000140 		.word	1073807360
+ 976              		.cfi_endproc
+ 977              	.LFE356:
+ 979              		.section	.text.HAL_SYSCFG_EnableVREFBUF,"ax",%progbits
+ 980              		.align	1
+ 981              		.global	HAL_SYSCFG_EnableVREFBUF
+ 982              		.syntax unified
+ 983              		.thumb
+ 984              		.thumb_func
+ 986              	HAL_SYSCFG_EnableVREFBUF:
+ 987              	.LFB357:
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval HAL_OK/HAL_TIMEOUT
+ARM GAS  /tmp/ccDAvPw5.s 			page 30
+
+
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 988              		.loc 1 671 1 is_stmt 1 view -0
+ 989              		.cfi_startproc
+ 990              		@ args = 0, pretend = 0, frame = 0
+ 991              		@ frame_needed = 0, uses_anonymous_args = 0
+ 992 0000 10B5     		push	{r4, lr}
+ 993              	.LCFI5:
+ 994              		.cfi_def_cfa_offset 8
+ 995              		.cfi_offset 4, -8
+ 996              		.cfi_offset 14, -4
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   uint32_t tickstart;
+ 997              		.loc 1 672 3 view .LVU168
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+ 998              		.loc 1 674 3 view .LVU169
+ 999 0002 0B4A     		ldr	r2, .L104
+ 1000 0004 136B     		ldr	r3, [r2, #48]
+ 1001 0006 43F00103 		orr	r3, r3, #1
+ 1002 000a 1363     		str	r3, [r2, #48]
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Get Start Tick*/
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   tickstart = HAL_GetTick();
+ 1003              		.loc 1 677 3 view .LVU170
+ 1004              		.loc 1 677 15 is_stmt 0 view .LVU171
+ 1005 000c FFF7FEFF 		bl	HAL_GetTick
+ 1006              	.LVL30:
+ 1007 0010 0446     		mov	r4, r0
+ 1008              	.LVL31:
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   /* Wait for VRR bit  */
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U)
+ 1009              		.loc 1 680 3 is_stmt 1 view .LVU172
+ 1010              	.L98:
+ 1011              		.loc 1 680 50 view .LVU173
+ 1012              		.loc 1 680 10 is_stmt 0 view .LVU174
+ 1013 0012 074B     		ldr	r3, .L104
+ 1014 0014 1B6B     		ldr	r3, [r3, #48]
+ 1015              		.loc 1 680 50 view .LVU175
+ 1016 0016 13F0080F 		tst	r3, #8
+ 1017 001a 06D1     		bne	.L103
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   {
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+ 1018              		.loc 1 682 5 is_stmt 1 view .LVU176
+ 1019              		.loc 1 682 10 is_stmt 0 view .LVU177
+ 1020 001c FFF7FEFF 		bl	HAL_GetTick
+ 1021              	.LVL32:
+ 1022              		.loc 1 682 24 view .LVU178
+ 1023 0020 001B     		subs	r0, r0, r4
+ 1024              		.loc 1 682 8 view .LVU179
+ 1025 0022 0A28     		cmp	r0, #10
+ 1026 0024 F5D9     		bls	.L98
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     {
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****       return HAL_TIMEOUT;
+ 1027              		.loc 1 684 14 view .LVU180
+ 1028 0026 0320     		movs	r0, #3
+ARM GAS  /tmp/ccDAvPw5.s 			page 31
+
+
+ 1029 0028 00E0     		b	.L99
+ 1030              	.L103:
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****     }
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   }
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   return HAL_OK;
+ 1031              		.loc 1 688 10 view .LVU181
+ 1032 002a 0020     		movs	r0, #0
+ 1033              	.L99:
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 1034              		.loc 1 689 1 view .LVU182
+ 1035 002c 10BD     		pop	{r4, pc}
+ 1036              	.LVL33:
+ 1037              	.L105:
+ 1038              		.loc 1 689 1 view .LVU183
+ 1039 002e 00BF     		.align	2
+ 1040              	.L104:
+ 1041 0030 00000140 		.word	1073807360
+ 1042              		.cfi_endproc
+ 1043              	.LFE357:
+ 1045              		.section	.text.HAL_SYSCFG_DisableVREFBUF,"ax",%progbits
+ 1046              		.align	1
+ 1047              		.global	HAL_SYSCFG_DisableVREFBUF
+ 1048              		.syntax unified
+ 1049              		.thumb
+ 1050              		.thumb_func
+ 1052              	HAL_SYSCFG_DisableVREFBUF:
+ 1053              	.LFB358:
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_SYSCFG_DisableVREFBUF(void)
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 1054              		.loc 1 697 1 is_stmt 1 view -0
+ 1055              		.cfi_startproc
+ 1056              		@ args = 0, pretend = 0, frame = 0
+ 1057              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1058              		@ link register save eliminated.
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+ 1059              		.loc 1 698 3 view .LVU185
+ 1060 0000 024A     		ldr	r2, .L107
+ 1061 0002 136B     		ldr	r3, [r2, #48]
+ 1062 0004 23F00103 		bic	r3, r3, #1
+ 1063 0008 1363     		str	r3, [r2, #48]
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 1064              		.loc 1 699 1 is_stmt 0 view .LVU186
+ 1065 000a 7047     		bx	lr
+ 1066              	.L108:
+ 1067              		.align	2
+ 1068              	.L107:
+ 1069 000c 00000140 		.word	1073807360
+ 1070              		.cfi_endproc
+ 1071              	.LFE358:
+ 1073              		.section	.text.HAL_SYSCFG_EnableIOSwitchBooster,"ax",%progbits
+ARM GAS  /tmp/ccDAvPw5.s 			page 32
+
+
+ 1074              		.align	1
+ 1075              		.global	HAL_SYSCFG_EnableIOSwitchBooster
+ 1076              		.syntax unified
+ 1077              		.thumb
+ 1078              		.thumb_func
+ 1080              	HAL_SYSCFG_EnableIOSwitchBooster:
+ 1081              	.LFB359:
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** #endif /* VREFBUF */
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Enable the I/O analog switch voltage booster
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_SYSCFG_EnableIOSwitchBooster(void)
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 1082              		.loc 1 708 1 is_stmt 1 view -0
+ 1083              		.cfi_startproc
+ 1084              		@ args = 0, pretend = 0, frame = 0
+ 1085              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1086              		@ link register save eliminated.
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+ 1087              		.loc 1 709 3 view .LVU188
+ 1088 0000 024A     		ldr	r2, .L110
+ 1089 0002 5368     		ldr	r3, [r2, #4]
+ 1090 0004 43F48073 		orr	r3, r3, #256
+ 1091 0008 5360     		str	r3, [r2, #4]
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 1092              		.loc 1 710 1 is_stmt 0 view .LVU189
+ 1093 000a 7047     		bx	lr
+ 1094              	.L111:
+ 1095              		.align	2
+ 1096              	.L110:
+ 1097 000c 00000140 		.word	1073807360
+ 1098              		.cfi_endproc
+ 1099              	.LFE359:
+ 1101              		.section	.text.HAL_SYSCFG_DisableIOSwitchBooster,"ax",%progbits
+ 1102              		.align	1
+ 1103              		.global	HAL_SYSCFG_DisableIOSwitchBooster
+ 1104              		.syntax unified
+ 1105              		.thumb
+ 1106              		.thumb_func
+ 1108              	HAL_SYSCFG_DisableIOSwitchBooster:
+ 1109              	.LFB360:
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Disable the I/O analog switch voltage booster
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_SYSCFG_DisableIOSwitchBooster(void)
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 1110              		.loc 1 718 1 is_stmt 1 view -0
+ 1111              		.cfi_startproc
+ 1112              		@ args = 0, pretend = 0, frame = 0
+ 1113              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1114              		@ link register save eliminated.
+ARM GAS  /tmp/ccDAvPw5.s 			page 33
+
+
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+ 1115              		.loc 1 719 3 view .LVU191
+ 1116 0000 024A     		ldr	r2, .L113
+ 1117 0002 5368     		ldr	r3, [r2, #4]
+ 1118 0004 23F48073 		bic	r3, r3, #256
+ 1119 0008 5360     		str	r3, [r2, #4]
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 1120              		.loc 1 720 1 is_stmt 0 view .LVU192
+ 1121 000a 7047     		bx	lr
+ 1122              	.L114:
+ 1123              		.align	2
+ 1124              	.L113:
+ 1125 000c 00000140 		.word	1073807360
+ 1126              		.cfi_endproc
+ 1127              	.LFE360:
+ 1129              		.section	.text.HAL_SYSCFG_EnableIOSwitchVDD,"ax",%progbits
+ 1130              		.align	1
+ 1131              		.global	HAL_SYSCFG_EnableIOSwitchVDD
+ 1132              		.syntax unified
+ 1133              		.thumb
+ 1134              		.thumb_func
+ 1136              	HAL_SYSCFG_EnableIOSwitchVDD:
+ 1137              	.LFB361:
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Enable the I/O analog switch voltage by VDD
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_SYSCFG_EnableIOSwitchVDD(void)
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 1138              		.loc 1 728 1 is_stmt 1 view -0
+ 1139              		.cfi_startproc
+ 1140              		@ args = 0, pretend = 0, frame = 0
+ 1141              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1142              		@ link register save eliminated.
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
+ 1143              		.loc 1 729 3 view .LVU194
+ 1144 0000 024A     		ldr	r2, .L116
+ 1145 0002 5368     		ldr	r3, [r2, #4]
+ 1146 0004 43F40073 		orr	r3, r3, #512
+ 1147 0008 5360     		str	r3, [r2, #4]
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 1148              		.loc 1 730 1 is_stmt 0 view .LVU195
+ 1149 000a 7047     		bx	lr
+ 1150              	.L117:
+ 1151              		.align	2
+ 1152              	.L116:
+ 1153 000c 00000140 		.word	1073807360
+ 1154              		.cfi_endproc
+ 1155              	.LFE361:
+ 1157              		.section	.text.HAL_SYSCFG_DisableIOSwitchVDD,"ax",%progbits
+ 1158              		.align	1
+ 1159              		.global	HAL_SYSCFG_DisableIOSwitchVDD
+ 1160              		.syntax unified
+ 1161              		.thumb
+ 1162              		.thumb_func
+ARM GAS  /tmp/ccDAvPw5.s 			page 34
+
+
+ 1164              	HAL_SYSCFG_DisableIOSwitchVDD:
+ 1165              	.LFB362:
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /**
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @brief  Disable the I/O analog switch voltage by VDD
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   *
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_SYSCFG_DisableIOSwitchVDD(void)
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 1166              		.loc 1 738 1 is_stmt 1 view -0
+ 1167              		.cfi_startproc
+ 1168              		@ args = 0, pretend = 0, frame = 0
+ 1169              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1170              		@ link register save eliminated.
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
+ 1171              		.loc 1 739 3 view .LVU197
+ 1172 0000 024A     		ldr	r2, .L119
+ 1173 0002 5368     		ldr	r3, [r2, #4]
+ 1174 0004 23F40073 		bic	r3, r3, #512
+ 1175 0008 5360     		str	r3, [r2, #4]
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 1176              		.loc 1 740 1 is_stmt 0 view .LVU198
+ 1177 000a 7047     		bx	lr
+ 1178              	.L120:
+ 1179              		.align	2
+ 1180              	.L119:
+ 1181 000c 00000140 		.word	1073807360
+ 1182              		.cfi_endproc
+ 1183              	.LFE362:
+ 1185              		.section	.text.HAL_SYSCFG_CCMSRAM_WriteProtectionEnable,"ax",%progbits
+ 1186              		.align	1
+ 1187              		.global	HAL_SYSCFG_CCMSRAM_WriteProtectionEnable
+ 1188              		.syntax unified
+ 1189              		.thumb
+ 1190              		.thumb_func
+ 1192              	HAL_SYSCFG_CCMSRAM_WriteProtectionEnable:
+ 1193              	.LVL34:
+ 1194              	.LFB363:
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** /** @brief  CCMSRAM page write protection enable
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @param Page: This parameter is a long 32bit value and can be a value of @ref SYSCFG_CCMSRAMWRP
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @note   write protection can only be disabled by a system reset
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   * @retval None
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   */
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page)
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** {
+ 1195              		.loc 1 749 1 is_stmt 1 view -0
+ 1196              		.cfi_startproc
+ 1197              		@ args = 0, pretend = 0, frame = 0
+ 1198              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1199              		@ link register save eliminated.
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE(Page));
+ 1200              		.loc 1 750 3 view .LVU200
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** 
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ****   SET_BIT(SYSCFG->SWPR, (uint32_t)(Page));
+ARM GAS  /tmp/ccDAvPw5.s 			page 35
+
+
+ 1201              		.loc 1 752 3 view .LVU201
+ 1202 0000 024A     		ldr	r2, .L122
+ 1203 0002 136A     		ldr	r3, [r2, #32]
+ 1204 0004 0343     		orrs	r3, r3, r0
+ 1205 0006 1362     		str	r3, [r2, #32]
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c **** }
+ 1206              		.loc 1 753 1 is_stmt 0 view .LVU202
+ 1207 0008 7047     		bx	lr
+ 1208              	.L123:
+ 1209 000a 00BF     		.align	2
+ 1210              	.L122:
+ 1211 000c 00000140 		.word	1073807360
+ 1212              		.cfi_endproc
+ 1213              	.LFE363:
+ 1215              		.global	uwTickFreq
+ 1216              		.section	.data.uwTickFreq,"aw"
+ 1217              		.align	2
+ 1220              	uwTickFreq:
+ 1221 0000 01000000 		.word	1
+ 1222              		.global	uwTickPrio
+ 1223              		.section	.data.uwTickPrio,"aw"
+ 1224              		.align	2
+ 1227              	uwTickPrio:
+ 1228 0000 10000000 		.word	16
+ 1229              		.global	uwTick
+ 1230              		.section	.bss.uwTick,"aw",%nobits
+ 1231              		.align	2
+ 1234              	uwTick:
+ 1235 0000 00000000 		.space	4
+ 1236              		.text
+ 1237              	.Letext0:
+ 1238              		.file 2 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 1239              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 1240              		.file 4 "Drivers/CMSIS/Include/core_cm4.h"
+ 1241              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 1242              		.file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
+ 1243              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ 1244              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"
+ARM GAS  /tmp/ccDAvPw5.s 			page 36
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal.c
+     /tmp/ccDAvPw5.s:21     .text.HAL_MspInit:00000000 $t
+     /tmp/ccDAvPw5.s:27     .text.HAL_MspInit:00000000 HAL_MspInit
+     /tmp/ccDAvPw5.s:40     .text.HAL_MspDeInit:00000000 $t
+     /tmp/ccDAvPw5.s:46     .text.HAL_MspDeInit:00000000 HAL_MspDeInit
+     /tmp/ccDAvPw5.s:59     .text.HAL_DeInit:00000000 $t
+     /tmp/ccDAvPw5.s:65     .text.HAL_DeInit:00000000 HAL_DeInit
+     /tmp/ccDAvPw5.s:109    .text.HAL_DeInit:00000028 $d
+     /tmp/ccDAvPw5.s:114    .text.HAL_InitTick:00000000 $t
+     /tmp/ccDAvPw5.s:120    .text.HAL_InitTick:00000000 HAL_InitTick
+     /tmp/ccDAvPw5.s:197    .text.HAL_InitTick:00000044 $d
+     /tmp/ccDAvPw5.s:1220   .data.uwTickFreq:00000000 uwTickFreq
+     /tmp/ccDAvPw5.s:1227   .data.uwTickPrio:00000000 uwTickPrio
+     /tmp/ccDAvPw5.s:204    .text.HAL_Init:00000000 $t
+     /tmp/ccDAvPw5.s:210    .text.HAL_Init:00000000 HAL_Init
+     /tmp/ccDAvPw5.s:254    .text.HAL_IncTick:00000000 $t
+     /tmp/ccDAvPw5.s:260    .text.HAL_IncTick:00000000 HAL_IncTick
+     /tmp/ccDAvPw5.s:280    .text.HAL_IncTick:00000010 $d
+     /tmp/ccDAvPw5.s:1234   .bss.uwTick:00000000 uwTick
+     /tmp/ccDAvPw5.s:286    .text.HAL_GetTick:00000000 $t
+     /tmp/ccDAvPw5.s:292    .text.HAL_GetTick:00000000 HAL_GetTick
+     /tmp/ccDAvPw5.s:308    .text.HAL_GetTick:00000008 $d
+     /tmp/ccDAvPw5.s:313    .text.HAL_GetTickPrio:00000000 $t
+     /tmp/ccDAvPw5.s:319    .text.HAL_GetTickPrio:00000000 HAL_GetTickPrio
+     /tmp/ccDAvPw5.s:334    .text.HAL_GetTickPrio:00000008 $d
+     /tmp/ccDAvPw5.s:339    .text.HAL_SetTickFreq:00000000 $t
+     /tmp/ccDAvPw5.s:345    .text.HAL_SetTickFreq:00000000 HAL_SetTickFreq
+     /tmp/ccDAvPw5.s:402    .text.HAL_SetTickFreq:00000024 $d
+     /tmp/ccDAvPw5.s:408    .text.HAL_GetTickFreq:00000000 $t
+     /tmp/ccDAvPw5.s:414    .text.HAL_GetTickFreq:00000000 HAL_GetTickFreq
+     /tmp/ccDAvPw5.s:429    .text.HAL_GetTickFreq:00000008 $d
+     /tmp/ccDAvPw5.s:434    .text.HAL_Delay:00000000 $t
+     /tmp/ccDAvPw5.s:440    .text.HAL_Delay:00000000 HAL_Delay
+     /tmp/ccDAvPw5.s:493    .text.HAL_Delay:00000024 $d
+     /tmp/ccDAvPw5.s:498    .text.HAL_SuspendTick:00000000 $t
+     /tmp/ccDAvPw5.s:504    .text.HAL_SuspendTick:00000000 HAL_SuspendTick
+     /tmp/ccDAvPw5.s:522    .text.HAL_ResumeTick:00000000 $t
+     /tmp/ccDAvPw5.s:528    .text.HAL_ResumeTick:00000000 HAL_ResumeTick
+     /tmp/ccDAvPw5.s:546    .text.HAL_GetHalVersion:00000000 $t
+     /tmp/ccDAvPw5.s:552    .text.HAL_GetHalVersion:00000000 HAL_GetHalVersion
+     /tmp/ccDAvPw5.s:566    .text.HAL_GetHalVersion:00000004 $d
+     /tmp/ccDAvPw5.s:571    .text.HAL_GetREVID:00000000 $t
+     /tmp/ccDAvPw5.s:577    .text.HAL_GetREVID:00000000 HAL_GetREVID
+     /tmp/ccDAvPw5.s:594    .text.HAL_GetREVID:00000008 $d
+     /tmp/ccDAvPw5.s:599    .text.HAL_GetDEVID:00000000 $t
+     /tmp/ccDAvPw5.s:605    .text.HAL_GetDEVID:00000000 HAL_GetDEVID
+     /tmp/ccDAvPw5.s:622    .text.HAL_GetDEVID:0000000c $d
+     /tmp/ccDAvPw5.s:627    .text.HAL_DBGMCU_EnableDBGSleepMode:00000000 $t
+     /tmp/ccDAvPw5.s:633    .text.HAL_DBGMCU_EnableDBGSleepMode:00000000 HAL_DBGMCU_EnableDBGSleepMode
+     /tmp/ccDAvPw5.s:650    .text.HAL_DBGMCU_EnableDBGSleepMode:0000000c $d
+     /tmp/ccDAvPw5.s:655    .text.HAL_DBGMCU_DisableDBGSleepMode:00000000 $t
+     /tmp/ccDAvPw5.s:661    .text.HAL_DBGMCU_DisableDBGSleepMode:00000000 HAL_DBGMCU_DisableDBGSleepMode
+     /tmp/ccDAvPw5.s:678    .text.HAL_DBGMCU_DisableDBGSleepMode:0000000c $d
+     /tmp/ccDAvPw5.s:683    .text.HAL_DBGMCU_EnableDBGStopMode:00000000 $t
+     /tmp/ccDAvPw5.s:689    .text.HAL_DBGMCU_EnableDBGStopMode:00000000 HAL_DBGMCU_EnableDBGStopMode
+     /tmp/ccDAvPw5.s:706    .text.HAL_DBGMCU_EnableDBGStopMode:0000000c $d
+ARM GAS  /tmp/ccDAvPw5.s 			page 37
+
+
+     /tmp/ccDAvPw5.s:711    .text.HAL_DBGMCU_DisableDBGStopMode:00000000 $t
+     /tmp/ccDAvPw5.s:717    .text.HAL_DBGMCU_DisableDBGStopMode:00000000 HAL_DBGMCU_DisableDBGStopMode
+     /tmp/ccDAvPw5.s:734    .text.HAL_DBGMCU_DisableDBGStopMode:0000000c $d
+     /tmp/ccDAvPw5.s:739    .text.HAL_DBGMCU_EnableDBGStandbyMode:00000000 $t
+     /tmp/ccDAvPw5.s:745    .text.HAL_DBGMCU_EnableDBGStandbyMode:00000000 HAL_DBGMCU_EnableDBGStandbyMode
+     /tmp/ccDAvPw5.s:762    .text.HAL_DBGMCU_EnableDBGStandbyMode:0000000c $d
+     /tmp/ccDAvPw5.s:767    .text.HAL_DBGMCU_DisableDBGStandbyMode:00000000 $t
+     /tmp/ccDAvPw5.s:773    .text.HAL_DBGMCU_DisableDBGStandbyMode:00000000 HAL_DBGMCU_DisableDBGStandbyMode
+     /tmp/ccDAvPw5.s:790    .text.HAL_DBGMCU_DisableDBGStandbyMode:0000000c $d
+     /tmp/ccDAvPw5.s:795    .text.HAL_SYSCFG_CCMSRAMErase:00000000 $t
+     /tmp/ccDAvPw5.s:801    .text.HAL_SYSCFG_CCMSRAMErase:00000000 HAL_SYSCFG_CCMSRAMErase
+     /tmp/ccDAvPw5.s:826    .text.HAL_SYSCFG_CCMSRAMErase:00000014 $d
+     /tmp/ccDAvPw5.s:831    .text.HAL_SYSCFG_EnableMemorySwappingBank:00000000 $t
+     /tmp/ccDAvPw5.s:837    .text.HAL_SYSCFG_EnableMemorySwappingBank:00000000 HAL_SYSCFG_EnableMemorySwappingBank
+     /tmp/ccDAvPw5.s:854    .text.HAL_SYSCFG_EnableMemorySwappingBank:0000000c $d
+     /tmp/ccDAvPw5.s:859    .text.HAL_SYSCFG_DisableMemorySwappingBank:00000000 $t
+     /tmp/ccDAvPw5.s:865    .text.HAL_SYSCFG_DisableMemorySwappingBank:00000000 HAL_SYSCFG_DisableMemorySwappingBank
+     /tmp/ccDAvPw5.s:882    .text.HAL_SYSCFG_DisableMemorySwappingBank:0000000c $d
+     /tmp/ccDAvPw5.s:887    .text.HAL_SYSCFG_VREFBUF_VoltageScalingConfig:00000000 $t
+     /tmp/ccDAvPw5.s:893    .text.HAL_SYSCFG_VREFBUF_VoltageScalingConfig:00000000 HAL_SYSCFG_VREFBUF_VoltageScalingConfig
+     /tmp/ccDAvPw5.s:913    .text.HAL_SYSCFG_VREFBUF_VoltageScalingConfig:00000010 $d
+     /tmp/ccDAvPw5.s:918    .text.HAL_SYSCFG_VREFBUF_HighImpedanceConfig:00000000 $t
+     /tmp/ccDAvPw5.s:924    .text.HAL_SYSCFG_VREFBUF_HighImpedanceConfig:00000000 HAL_SYSCFG_VREFBUF_HighImpedanceConfig
+     /tmp/ccDAvPw5.s:944    .text.HAL_SYSCFG_VREFBUF_HighImpedanceConfig:00000010 $d
+     /tmp/ccDAvPw5.s:949    .text.HAL_SYSCFG_VREFBUF_TrimmingConfig:00000000 $t
+     /tmp/ccDAvPw5.s:955    .text.HAL_SYSCFG_VREFBUF_TrimmingConfig:00000000 HAL_SYSCFG_VREFBUF_TrimmingConfig
+     /tmp/ccDAvPw5.s:975    .text.HAL_SYSCFG_VREFBUF_TrimmingConfig:00000010 $d
+     /tmp/ccDAvPw5.s:980    .text.HAL_SYSCFG_EnableVREFBUF:00000000 $t
+     /tmp/ccDAvPw5.s:986    .text.HAL_SYSCFG_EnableVREFBUF:00000000 HAL_SYSCFG_EnableVREFBUF
+     /tmp/ccDAvPw5.s:1041   .text.HAL_SYSCFG_EnableVREFBUF:00000030 $d
+     /tmp/ccDAvPw5.s:1046   .text.HAL_SYSCFG_DisableVREFBUF:00000000 $t
+     /tmp/ccDAvPw5.s:1052   .text.HAL_SYSCFG_DisableVREFBUF:00000000 HAL_SYSCFG_DisableVREFBUF
+     /tmp/ccDAvPw5.s:1069   .text.HAL_SYSCFG_DisableVREFBUF:0000000c $d
+     /tmp/ccDAvPw5.s:1074   .text.HAL_SYSCFG_EnableIOSwitchBooster:00000000 $t
+     /tmp/ccDAvPw5.s:1080   .text.HAL_SYSCFG_EnableIOSwitchBooster:00000000 HAL_SYSCFG_EnableIOSwitchBooster
+     /tmp/ccDAvPw5.s:1097   .text.HAL_SYSCFG_EnableIOSwitchBooster:0000000c $d
+     /tmp/ccDAvPw5.s:1102   .text.HAL_SYSCFG_DisableIOSwitchBooster:00000000 $t
+     /tmp/ccDAvPw5.s:1108   .text.HAL_SYSCFG_DisableIOSwitchBooster:00000000 HAL_SYSCFG_DisableIOSwitchBooster
+     /tmp/ccDAvPw5.s:1125   .text.HAL_SYSCFG_DisableIOSwitchBooster:0000000c $d
+     /tmp/ccDAvPw5.s:1130   .text.HAL_SYSCFG_EnableIOSwitchVDD:00000000 $t
+     /tmp/ccDAvPw5.s:1136   .text.HAL_SYSCFG_EnableIOSwitchVDD:00000000 HAL_SYSCFG_EnableIOSwitchVDD
+     /tmp/ccDAvPw5.s:1153   .text.HAL_SYSCFG_EnableIOSwitchVDD:0000000c $d
+     /tmp/ccDAvPw5.s:1158   .text.HAL_SYSCFG_DisableIOSwitchVDD:00000000 $t
+     /tmp/ccDAvPw5.s:1164   .text.HAL_SYSCFG_DisableIOSwitchVDD:00000000 HAL_SYSCFG_DisableIOSwitchVDD
+     /tmp/ccDAvPw5.s:1181   .text.HAL_SYSCFG_DisableIOSwitchVDD:0000000c $d
+     /tmp/ccDAvPw5.s:1186   .text.HAL_SYSCFG_CCMSRAM_WriteProtectionEnable:00000000 $t
+     /tmp/ccDAvPw5.s:1192   .text.HAL_SYSCFG_CCMSRAM_WriteProtectionEnable:00000000 HAL_SYSCFG_CCMSRAM_WriteProtectionEnable
+     /tmp/ccDAvPw5.s:1211   .text.HAL_SYSCFG_CCMSRAM_WriteProtectionEnable:0000000c $d
+     /tmp/ccDAvPw5.s:1217   .data.uwTickFreq:00000000 $d
+     /tmp/ccDAvPw5.s:1224   .data.uwTickPrio:00000000 $d
+     /tmp/ccDAvPw5.s:1231   .bss.uwTick:00000000 $d
+
+UNDEFINED SYMBOLS
+HAL_SYSTICK_Config
+HAL_NVIC_SetPriority
+SystemCoreClock
+HAL_NVIC_SetPriorityGrouping
+ARM GAS  /tmp/ccDAvPw5.s 			page 38
+
+
diff --git a/squeow_sw/build/stm32g4xx_hal.o b/squeow_sw/build/stm32g4xx_hal.o
new file mode 100644
index 0000000000000000000000000000000000000000..95dd48650f31b795193a629e6ce2046331db92ec
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HcmV?d00001

diff --git a/squeow_sw/build/stm32g4xx_hal_adc.d b/squeow_sw/build/stm32g4xx_hal_adc.d
new file mode 100644
index 0000000..bbcdbfd
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_adc.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_adc.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_adc.lst b/squeow_sw/build/stm32g4xx_hal_adc.lst
new file mode 100644
index 0000000..00bc0b1
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_adc.lst
@@ -0,0 +1,22275 @@
+ARM GAS  /tmp/ccICigVb.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_adc.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c"
+  20              		.section	.text.LL_ADC_REG_SetSequencerRanks,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	LL_ADC_REG_SetSequencerRanks:
+  27              	.LVL0:
+  28              	.LFB171:
+  29              		.file 2 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"
+   1:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @file    stm32g4xx_ll_adc.h
+   4:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief   Header file of ADC LL module.
+   6:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ******************************************************************************
+   7:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @attention
+   8:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+   9:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * Copyright (c) 2019 STMicroelectronics.
+  10:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * All rights reserved.
+  11:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+  12:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * in the root directory of this software component.
+  14:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+  16:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ******************************************************************************
+  17:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+  18:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  19:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #ifndef STM32G4xx_LL_ADC_H
+  21:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define STM32G4xx_LL_ADC_H
+  22:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  23:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #ifdef __cplusplus
+  24:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** extern "C" {
+  25:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif
+  26:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  27:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #include "stm32g4xx.h"
+  29:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ARM GAS  /tmp/ccICigVb.s 			page 2
+
+
+  30:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @addtogroup STM32G4xx_LL_Driver
+  31:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+  32:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+  33:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  34:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
+  35:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  36:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL ADC
+  37:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+  38:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+  39:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  40:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  43:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Private constants ---------------------------------------------------------*/
+  44:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_Private_Constants ADC Private Constants
+  45:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+  46:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+  47:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  48:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC group regular sequencer:                             */
+  49:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
+  50:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - sequencer register offset                                                */
+  51:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - sequencer rank bits position into the selected register                  */
+  52:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  53:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal register offset for ADC group regular sequencer configuration */
+  54:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (offset placed into a spare area of literal definition) */
+  55:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SQR1_REGOFFSET                 (0x00000000UL)
+  56:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SQR2_REGOFFSET                 (0x00000100UL)
+  57:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SQR3_REGOFFSET                 (0x00000200UL)
+  58:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SQR4_REGOFFSET                 (0x00000300UL)
+  59:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  60:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
+  61:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                             | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+  62:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SQRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_
+  63:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+  64:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  65:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of ADC group regular sequencer bits information to be inserted  */
+  66:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* into ADC group regular sequencer ranks literals definition.                */
+  67:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ1_Pos)
+  68:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ2_Pos)
+  69:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ3_Pos)
+  70:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ4_Pos)
+  71:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ5_Pos)
+  72:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ6_Pos)
+  73:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ7_Pos)
+  74:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ8_Pos)
+  75:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ9_Pos)
+  76:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
+  77:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
+  78:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
+  79:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
+  80:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
+  81:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
+  82:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
+  83:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  84:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  85:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  86:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC group injected sequencer:                            */
+ARM GAS  /tmp/ccICigVb.s 			page 3
+
+
+  87:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
+  88:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - data register offset                                                     */
+  89:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - sequencer rank bits position into the selected register                  */
+  90:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  91:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal register offset for ADC group injected data register */
+  92:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (offset placed into a spare area of literal definition) */
+  93:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_JDR1_REGOFFSET                 (0x00000000UL)
+  94:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_JDR2_REGOFFSET                 (0x00000100UL)
+  95:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_JDR3_REGOFFSET                 (0x00000200UL)
+  96:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_JDR4_REGOFFSET                 (0x00000300UL)
+  97:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  98:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
+  99:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                             | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+ 100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+ 101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_JDRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_
+ 102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of ADC group injected sequencer bits information to be inserted */
+ 104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* into ADC group injected sequencer ranks literals definition.               */
+ 105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ1_Pos)
+ 106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ2_Pos)
+ 107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ3_Pos)
+ 108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ4_Pos)
+ 109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC group regular trigger:                               */
+ 113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
+ 114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - regular trigger source                                                   */
+ 115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - regular trigger edge                                                     */
+ 116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (
+ 117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Mask containing trigger source masks for each of possible                  */
+ 119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+ 120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+ 121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U *
+ 122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_CFGR_EXTSEL)                            << (4U *
+ 123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_CFGR_EXTSEL)                            << (4U *
+ 124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_CFGR_EXTSEL)                            << (4U *
+ 125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Mask containing trigger edge masks for each of possible                    */
+ 127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+ 128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+ 129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 
+ 130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 
+ 131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 
+ 132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 
+ 133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of ADC group regular trigger bits information.                  */
+ 135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (ADC_CFGR_EXTSEL_Pos)
+ 136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (ADC_CFGR_EXTEN_Pos)
+ 137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC group injected trigger:                              */
+ 141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
+ 142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - injected trigger source                                                  */
+ 143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - injected trigger edge                                                    */
+ARM GAS  /tmp/ccICigVb.s 			page 4
+
+
+ 144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (
+ 145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Mask containing trigger source masks for each of possible                  */
+ 147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+ 148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+ 149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U
+ 150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_JSQR_JEXTSEL)                             << (4U
+ 151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_JSQR_JEXTSEL)                             << (4U
+ 152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_JSQR_JEXTSEL)                             << (4U
+ 153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Mask containing trigger edge masks for each of possible                    */
+ 155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+ 156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+ 157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U *
+ 158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U *
+ 159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U *
+ 160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U *
+ 161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of ADC group injected trigger bits information.                 */
+ 163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (ADC_JSQR_JEXTSEL_Pos)
+ 164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (ADC_JSQR_JEXTEN_Pos)
+ 165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC channel:                                             */
+ 172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
+ 173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - channel identifier defined by number                                     */
+ 174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - channel identifier defined by bitfield                                   */
+ 175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - channel differentiation between external channels (connected to          */
+ 176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*   GPIO pins) and internal channels (connected to internal paths)           */
+ 177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - channel sampling time defined by SMPRx register offset                   */
+ 178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*   and SMPx bits positions into SMPRx register                              */
+ 179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)
+ 180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)
+ 181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
+ 182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MA
+ 183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                             | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+ 184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+ 185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMB
+ 186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Channel differentiation between external and internal channels */
+ 188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */
+ 189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_INTERNAL_CH_2       (0x00080000UL) /* Marker of internal channel for other A
+ 190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH
+ 191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal register offset for ADC channel sampling time configuration */
+ 193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (offset placed into a spare area of literal definition) */
+ 194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SMPR1_REGOFFSET                (0x00000000UL)
+ 195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SMPR2_REGOFFSET                (0x02000000UL)
+ 196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+ 197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SMPRX_REGOFFSET_POS            (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CH
+ 198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000UL)
+ 200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Value equivalent to bitfield "ADC_CH
+ARM GAS  /tmp/ccICigVb.s 			page 5
+
+
+ 201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of channels ID number information to be inserted into           */
+ 203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* channels literals definition.                                              */
+ 204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_0_NUMBER               (0x00000000UL)
+ 205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_1_NUMBER               (ADC_CFGR_AWD1CH_0)
+ 206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_2_NUMBER               (ADC_CFGR_AWD1CH_1)
+ 207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_3_NUMBER               (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+ 208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_4_NUMBER               (ADC_CFGR_AWD1CH_2)
+ 209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_5_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+ 210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_6_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+ 211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_7_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH
+ 212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_8_NUMBER               (ADC_CFGR_AWD1CH_3)
+ 213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_9_NUMBER               (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
+ 214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_10_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
+ 215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_11_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH
+ 216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_12_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
+ 217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_13_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH
+ 218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_14_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH
+ 219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_15_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
+ 220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                             ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+ 221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4)
+ 222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
+ 223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
+ 224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of channels ID bitfield information to be inserted into         */
+ 226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* channels literals definition.                                              */
+ 227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)
+ 228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)
+ 229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)
+ 230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)
+ 231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)
+ 232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)
+ 233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)
+ 234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)
+ 235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)
+ 236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)
+ 237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)
+ 238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)
+ 239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)
+ 240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)
+ 241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)
+ 242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)
+ 243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
+ 244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
+ 245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
+ 246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of channels sampling time information to be inserted into       */
+ 248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* channels literals definition.                                              */
+ 249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOF
+ 250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOF
+ 251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOF
+ 252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOF
+ 253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOF
+ 254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOF
+ 255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOF
+ 256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOF
+ 257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOF
+ARM GAS  /tmp/ccICigVb.s 			page 6
+
+
+ 258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOF
+ 259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOF
+ 260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOF
+ 261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOF
+ 262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOF
+ 263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOF
+ 264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOF
+ 265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOF
+ 266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOF
+ 267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOF
+ 268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC mode single or differential ended:                   */
+ 271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
+ 272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* the relevant bits for:                                                     */
+ 273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (concatenation of multiple bits used in different registers)               */
+ 274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - ADC calibration: calibration start, calibration factor get or set        */
+ 275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - ADC channels: set each ADC channel ending mode                           */
+ 276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)
+ 277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
+ 278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFS
+ 279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* B
+ 280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000UL)                           /* Selection o
+ 281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16UL)                                   /* Selection o
+ 282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bi
+ 283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC analog watchdog:                                     */
+ 285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
+ 286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (concatenation of multiple bits used in different analog watchdogs,        */
+ 287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (feature of several watchdogs not available on all STM32 families)).       */
+ 288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - analog watchdog 1: monitored channel defined by number,                  */
+ 289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*   selection of ADC group (ADC groups regular and-or injected).             */
+ 290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
+ 291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*   selection on groups.                                                     */
+ 292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal register offset for ADC analog watchdog channel configuration */
+ 294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)
+ 295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)
+ 296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)
+ 297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
+ 299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
+ 300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
+ 301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)
+ 302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD
+ 304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | 
+ 306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
+ 307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+ 308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CRX_REGOFFSET_POS          (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_
+ 310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal register offset for ADC analog watchdog threshold configuration */
+ 312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
+ 313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
+ 314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)
+ARM GAS  /tmp/ccICigVb.s 			page 7
+
+
+ 315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD
+ 316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC_
+ 317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TRX_BIT_HIGH_MASK          (0x00010000UL)                   /* Selection of 1 bit t
+ 318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TRX_BIT_HIGH_POS           (16UL)                           /* Selection of 1 bit t
+ 319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TRX_BIT_HIGH_SHIFT4        (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD
+ 320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC offset:                                              */
+ 322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal register offset for ADC offset number configuration */
+ 323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_OFR1_REGOFFSET                 (0x00000000UL)
+ 324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_OFR2_REGOFFSET                 (0x00000001UL)
+ 325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_OFR3_REGOFFSET                 (0x00000002UL)
+ 326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_OFR4_REGOFFSET                 (0x00000003UL)
+ 327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
+ 328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                             | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+ 329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* ADC registers bits positions */
+ 332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CFGR_RES_BITOFFSET_POS         (ADC_CFGR_RES_Pos)
+ 333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (ADC_CFGR_AWD1SGL_Pos)
+ 334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CFGR_AWD1EN_BITOFFSET_POS      (ADC_CFGR_AWD1EN_Pos)
+ 335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (ADC_CFGR_JAWD1EN_Pos)
+ 336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_TR1_HT1_BITOFFSET_POS          (ADC_TR1_HT1_Pos)
+ 337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* ADC registers bits groups */
+ 340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JA
+ 341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* ADC internal channels related definitions */
+ 344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal voltage reference VrefInt */
+ 345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage referen
+ 346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define VREFINT_CAL_VREF                   (3000UL)                     /* Analog voltage reference
+ 347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Temperature sensor */
+ 348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sen
+ 349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sen
+ 350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Internal temperature sen
+ 351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define TEMPSENSOR_CAL2_TEMP               (130L)                       /* Internal temperature sen
+ 352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define TEMPSENSOR_CAL_VREFANALOG          (3000UL)                     /* Analog voltage reference
+ 353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Private macros ------------------------------------------------------------*/
+ 360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_Private_Macros ADC Private Macros
+ 361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Driver macro reserved for internal use: set a pointer to
+ 366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a register from a register basis from which an offset
+ 367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is applied.
+ 368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __REG__ Register basis from which the offset is applied.
+ 369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ 370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Pointer to register address
+ 371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ARM GAS  /tmp/ccICigVb.s 			page 8
+
+
+ 372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
+ 373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+ 374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Exported types ------------------------------------------------------------*/
+ 381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(USE_FULL_LL_DRIVER)
+ 382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+ 383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Structure definition of some features of ADC common parameters
+ 388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and multimode
+ 389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (all ADC instances belonging to the same ADC common instance).
+ 390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
+ 391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is conditioned to ADC instances state (all ADC instances
+ 392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sharing the same ADC common instance):
+ 393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         All ADC instances sharing the same ADC common instance must be
+ 394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         disabled.
+ 395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** typedef struct
+ 397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and 
+ 399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_COMMON
+ 400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              @note On this STM32 series, if ADC group injected is u
+ 401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    clock ratio constraints between ADC clock and AH
+ 402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    must be respected. Refer to reference manual.
+ 403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independ
+ 408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_
+ 409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t MultiDMATransfer;            /*!< Set ADC multimode conversion data transfer: no transfe
+ 413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_
+ 414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.
+ 418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_
+ 419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+ 422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** } LL_ADC_CommonInitTypeDef;
+ 424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Structure definition of some features of ADC instance.
+ 427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   These parameters have an impact on ADC scope: ADC instance.
+ 428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Affects both group regular and group injected (availability
+ARM GAS  /tmp/ccICigVb.s 			page 9
+
+
+ 429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of ADC group injected depends on STM32 families).
+ 430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to corresponding unitary functions into
+ 431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+ 432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The setting of these parameters by function @ref LL_ADC_Init()
+ 433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is conditioned to ADC state:
+ 434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instance must be disabled.
+ 435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This condition is applied to all ADC features, for efficiency
+ 436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and compatibility over all STM32 families. However, the different
+ 437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         features can be set under different ADC state conditions
+ 438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (setting possible with ADC enabled without conversion on going,
+ 439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC enabled with conversion on going, ...)
+ 440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Each feature can be updated afterwards with a unitary function
+ 441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and potentially with ADC in a different state than disabled,
+ 442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         refer to description of each function for setting
+ 443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         conditioned to ADC state.
+ 444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** typedef struct
+ 446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t Resolution;                  /*!< Set ADC resolution.
+ 448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_RESOLU
+ 449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
+ 453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_DATA_A
+ 454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t LowPowerMode;                /*!< Set ADC low power mode.
+ 458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_LP_MOD
+ 459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** } LL_ADC_InitTypeDef;
+ 463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Structure definition of some features of ADC group regular.
+ 466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   These parameters have an impact on ADC scope: ADC group regular.
+ 467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to corresponding unitary functions into
+ 468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ 469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (functions with prefix "REG").
+ 470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
+ 471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is conditioned to ADC state:
+ 472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instance must be disabled.
+ 473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This condition is applied to all ADC features, for efficiency
+ 474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and compatibility over all STM32 families. However, the different
+ 475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         features can be set under different ADC state conditions
+ 476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (setting possible with ADC enabled without conversion on going,
+ 477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC enabled with conversion on going, ...)
+ 478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Each feature can be updated afterwards with a unitary function
+ 479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and potentially with ADC in a different state than disabled,
+ 480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         refer to description of each function for setting
+ 481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         conditioned to ADC state.
+ 482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** typedef struct
+ 484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: inter
+ARM GAS  /tmp/ccICigVb.s 			page 10
+
+
+ 486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_REG_TR
+ 487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              @note On this STM32 series, setting trigger source to 
+ 488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    (default setting for compatibility with some ADC
+ 489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    In case of need to modify trigger edge, use func
+ 490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
+ 494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_REG_SE
+ 495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: se
+ 499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_REG_SE
+ 500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              @note This parameter has an effect only if group regul
+ 501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    (scan length of 2 ranks or more).
+ 502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regula
+ 506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_REG_CO
+ 507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              Note: It is not possible to enable both ADC group regu
+ 508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no tra
+ 512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_REG_DM
+ 513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
+ 517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              data preserved or overwritten.
+ 518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_REG_OV
+ 519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** } LL_ADC_REG_InitTypeDef;
+ 523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Structure definition of some features of ADC group injected.
+ 526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   These parameters have an impact on ADC scope: ADC group injected.
+ 527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to corresponding unitary functions into
+ 528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ 529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (functions with prefix "INJ").
+ 530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
+ 531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is conditioned to ADC state:
+ 532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instance must be disabled.
+ 533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This condition is applied to all ADC features, for efficiency
+ 534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and compatibility over all STM32 families. However, the different
+ 535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         features can be set under different ADC state conditions
+ 536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (setting possible with ADC enabled without conversion on going,
+ 537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC enabled with conversion on going, ...)
+ 538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Each feature can be updated afterwards with a unitary function
+ 539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and potentially with ADC in a different state than disabled,
+ 540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         refer to description of each function for setting
+ 541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         conditioned to ADC state.
+ 542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ARM GAS  /tmp/ccICigVb.s 			page 11
+
+
+ 543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** typedef struct
+ 544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: inte
+ 546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TR
+ 547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              @note On this STM32 series, setting trigger source to 
+ 548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    (default setting for compatibility with some ADC
+ 549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    In case of need to modify trigger edge, use func
+ 550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
+ 554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SE
+ 555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: s
+ 559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SE
+ 560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              @note This parameter has an effect only if group injec
+ 561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    (scan length of 2 ranks or more).
+ 562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent
+ 566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TR
+ 567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              Note: This parameter must be set to set to independent
+ 568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** } LL_ADC_INJ_InitTypeDef;
+ 572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* USE_FULL_LL_DRIVER */
+ 577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Exported constants --------------------------------------------------------*/
+ 579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+ 580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_FLAG ADC flags
+ 584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief    Flags defines which can be used with LL_ADC_ReadReg function
+ 585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
+ 588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end o
+ 589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end o
+ 590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overr
+ 591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end o
+ 592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end 
+ 593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end 
+ 594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected cont
+ 595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 *
+ 596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 *
+ 597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 *
+ 598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master in
+ARM GAS  /tmp/ccICigVb.s 			page 12
+
+
+ 600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave ins
+ 601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master gr
+ 602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave gro
+ 603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master gr
+ 604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave gro
+ 605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master gr
+ 606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave gro
+ 607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master gr
+ 608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave gro
+ 609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master gr
+ 610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave gro
+ 611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master gr
+ 612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave gro
+ 613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master gr
+ 614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave gro
+ 615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master an
+ 616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave ana
+ 617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master an
+ 618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave ana
+ 619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master an
+ 620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave ana
+ 621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+ 622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+ 627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
+ 628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance re
+ 631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regul
+ 632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regul
+ 633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regul
+ 634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regul
+ 635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injec
+ 636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injec
+ 637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injec
+ 638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watc
+ 639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watc
+ 640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watc
+ 641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
+ 646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* List of ADC registers intended to be used (most commonly) with             */
+ 649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* DMA transfer.                                                              */
+ 650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
+ 651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000UL) /* ADC group regular conversion data re
+ 652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    (0x00000001UL) /* ADC group regular conversion data re
+ 654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+ 655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ARM GAS  /tmp/ccICigVb.s 			page 13
+
+
+ 657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
+ 660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*
+ 663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*
+ 664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*
+ 665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                                        /*
+ 666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*
+ 667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*
+ 668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*
+ 669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*
+ 670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*
+ 671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*
+ 672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*
+ 673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*
+ 674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*
+ 675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*
+ 676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*
+ 677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
+ 682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Note: Other measurement paths to internal channels may be available        */
+ 685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       (connections to other peripherals).                                  */
+ 686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       If they are not listed below, they do not require any specific       */
+ 687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       path enable. In this case, Access to measurement path is done        */
+ 688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       only by selecting the corresponding ADC internal channel.            */
+ 689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)         /*!< ADC measurement paths all di
+ 690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to inte
+ 691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_VSENSESEL)    /*!< ADC measurement path to inte
+ 692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATSEL)      /*!< ADC measurement path to inte
+ 693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
+ 698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_RESOLUTION_12B              (0x00000000UL)                      /*!< ADC resolution 
+ 701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 
+ 702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution 
+ 703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution 
+ 704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
+ 709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000UL)         /*!< ADC conversion data alignmen
+ 712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR_ALIGN)       /*!< ADC conversion data alignmen
+ 713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 14
+
+
+ 714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
+ 718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_LP_MODE_NONE                (0x00000000UL)                      /*!< No ADC low powe
+ 721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power m
+ 722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number
+ 727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel
+ 730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel
+ 731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel
+ 732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel
+ 733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
+ 738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_DISABLE              (0x00000000UL)         /*!< ADC offset disabled (among A
+ 741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_ENABLE               (ADC_OFR1_OFFSET1_EN)  /*!< ADC offset enabled (among AD
+ 742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
+ 747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_SIGN_NEGATIVE        (0x00000000UL)       /*!< ADC offset is negative (among 
+ 750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_SIGN_POSITIVE        (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among 
+ 751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
+ 756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_SATURATION_DISABLE   (0x00000000UL)          /*!< ADC offset saturation is di
+ 759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_SATURATION_ENABLE    (ADC_OFR1_SATEN)        /*!< ADC offset saturation is en
+ 760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
+ 764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_GROUP_REGULAR               (0x00000001UL) /*!< ADC group regular (available on all 
+ 767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_GROUP_INJECTED              (0x00000002UL) /*!< ADC group injected (not available on
+ 768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL) /*!< ADC both groups regular and injected
+ 769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ARM GAS  /tmp/ccICigVb.s 			page 15
+
+
+ 771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
+ 774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNE
+ 777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNE
+ 778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNE
+ 779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNE
+ 780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNE
+ 781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNE
+ 782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNE
+ 783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNE
+ 784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNE
+ 785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNE
+ 786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNE
+ 787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNE
+ 788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNE
+ 789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNE
+ 790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNE
+ 791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNE
+ 792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNE
+ 793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNE
+ 794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNE
+ 795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_TEMPSENSOR_ADC1     (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_TEMPSENSOR_ADC5     (LL_ADC_CHANNEL_4  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP1             (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP2             (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CH
+ 801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP3_ADC2        (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CH
+ 802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP3_ADC3        (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CH
+ 803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP4             (LL_ADC_CHANNEL_5  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP5             (LL_ADC_CHANNEL_3  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP6             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CH
+ 806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
+ 811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000UL)                                          
+ 814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger internal: SW start.
+ 815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EX
+ 816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EX
+ 818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                         
+ 820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)     
+ 823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)     
+ 826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL
+ARM GAS  /tmp/ccICigVb.s 			page 16
+
+
+ 828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_CH1       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EX
+ 833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)     
+ 836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)     
+ 839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM3_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                         
+ 841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM3_CH4       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EX
+ 847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM4_CH1       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EX
+ 849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EX
+ 852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL
+ 857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL
+ 859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)     
+ 861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM8_CH1       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EX
+ 863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO     (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)     
+ 868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, TIM20 is not available on al
+ 870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EX
+ 871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, TIM20 is not available on al
+ 873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM20_CH1      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EX
+ 874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, TIM20 is not available on al
+ 876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM20_CH2      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL
+ 877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM20_CH3      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EX
+ 880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ARM GAS  /tmp/ccICigVb.s 			page 17
+
+
+ 885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL
+ 886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EX
+ 892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EX
+ 898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL
+ 901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL
+ 904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL
+ 907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL
+ 910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EX
+ 913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2     (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EX
+ 916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_LPTIM_OUT      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL
+ 919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
+ 925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group r
+ 928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group r
+ 929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group r
+ 930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE  ADC group regular - Sampling mode
+ 935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SAMPLING_MODE_NORMAL               (0x00000000UL)       /*!< ADC conversions sam
+ 938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SAMPLING_MODE_BULB                 (ADC_CFGR2_BULB)     /*!< ADC conversions sam
+ 939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                                                 Note: First convers
+ 940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED    (ADC_CFGR2_SMPTRIG)  /*!< ADC conversions sam
+ 941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                                                  Trigger rising edg
+ARM GAS  /tmp/ccICigVb.s 			page 18
+
+
+ 942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                                                  Trigger falling ed
+ 943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
+ 948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)          /*!< ADC conversions are perform
+ 951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are perform
+ 952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
+ 957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000UL)                        /*!< ADC conversio
+ 960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                  ADC_CFGR_DMAEN)    /*!< ADC conversio
+ 961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)    /*!< ADC conversio
+ 962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_SMPR1_SMPPLUS)
+ 967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configur
+ 968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT      (0x00000000UL)      /*!< ADC sampling time let to d
+ 971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling ti
+ 972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif
+ 976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion d
+ 978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)         /*!< ADC group regular behavior i
+ 981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior i
+ 982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
+ 987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000UL)                                          
+ 990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L
+ 991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1             
+ 992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L
+ 993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                            
+ 994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L
+ 995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1             
+ 996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L
+ 997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                           
+ 998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L
+ARM GAS  /tmp/ccICigVb.s 			page 19
+
+
+ 999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1             
+1000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L
+1001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                            
+1002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L
+1003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1             
+1004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L
+1005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
+1010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                                          
+1013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                       
+1014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISC
+1015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                
+1016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISC
+1017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                     
+1018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISC
+1019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                
+1020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISC
+1021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
+1026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
+1029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
+1030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
+1031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
+1032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
+1033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
+1034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
+1035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
+1036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
+1037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS
+1038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS
+1039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS
+1040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS
+1041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS
+1042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS
+1043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS
+1044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
+1049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000UL)                                          
+1052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger internal: SW start
+1053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         
+1054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    
+ARM GAS  /tmp/ccICigVb.s 			page 20
+
+
+1056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXT
+1058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    
+1061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    
+1063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_
+1065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_
+1068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXT
+1073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    
+1076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_
+1079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    
+1081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_
+1084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_
+1091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_
+1093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_
+1095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXT
+1098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM16_CH1      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO     (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    
+1105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, TIM20 is not available on al
+1107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2    (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_
+1108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, TIM20 is not available on al
+1110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_
+1111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Trigger available only on ADC3/4/5 instances. On this ST
+ARM GAS  /tmp/ccICigVb.s 			page 21
+
+
+1113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_
+1114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Trigger available only on ADC1/2 instances. On this STM3
+1116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXT
+1120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_
+1126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_
+1138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10    (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_
+1150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
+1159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group i
+1162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group i
+1163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group i
+1164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
+1169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ARM GAS  /tmp/ccICigVb.s 			page 22
+
+
+1170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000UL)         /*!< ADC group injected conversio
+1172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversio
+1173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode
+1178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL)         /* Group injected sequence co
+1181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence co
+1182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence co
+1183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
+1188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                  /*!< ADC group injected 
+1191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected 
+1192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected 
+1193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected 
+1194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
+1199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000UL)         /*!< ADC group injected sequencer
+1202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer
+1203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
+1208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
+1211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
+1212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
+1213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)
+1214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+1219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000UL)                                          
+1222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_6CYCLES_5      (                                        ADC_SMPR2_SMP10
+1223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_12CYCLES_5     (                    ADC_SMPR2_SMP10_1                  
+1224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_24CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10
+1225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2                                      
+1226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10
+ARM GAS  /tmp/ccICigVb.s 			page 23
+
+
+1227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                  
+1228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10
+1229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
+1234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< A
+1237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< A
+1238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< A
+1239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+1244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!<
+1247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!<
+1248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!<
+1249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
+1254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_DISABLE                 (0x00000000UL)                                          
+1257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                              
+1258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JA
+1259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JA
+1260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)              
+1261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)              
+1264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)              
+1267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)              
+1270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)              
+1273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)              
+1276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)              
+1279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)              
+1282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+ARM GAS  /tmp/ccICigVb.s 			page 24
+
+
+1284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)              
+1285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)              
+1288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)              
+1291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)              
+1294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)              
+1297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)              
+1300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)              
+1303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)              
+1306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)              
+1309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)              
+1312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)              
+1315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)   
+1318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | 
+1319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | 
+1320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG       ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_M
+1321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_M
+1322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_M
+1323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG       ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_M
+1324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_M
+1325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_M
+1326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)   
+1327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | 
+1328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | 
+1329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP1_REG          ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK)   
+1330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP1_INJ          ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) | 
+1331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) | 
+1332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP2_REG          ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK)   
+1333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP2_INJ          ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) | 
+1334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) | 
+1335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK)   
+1336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) | 
+1337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) | 
+1338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK)   
+1339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) | 
+1340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) | 
+ARM GAS  /tmp/ccICigVb.s 			page 25
+
+
+1341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP4_REG          ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK)   
+1342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP4_INJ          ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) | 
+1343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP4_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) | 
+1344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP5_REG          ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK)   
+1345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP5_INJ          ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) | 
+1346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP5_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) | 
+1347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP6_REG          ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK)   
+1348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP6_INJ          ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) | 
+1349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP6_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) | 
+1350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
+1355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1              ) /*!< ADC analog watchdog thr
+1358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_THRESHOLD_LOW           (              ADC_TR1_LT1) /*!< ADC analog watchdog thr
+1359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog bot
+1360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG  Analog watchdog - filtering config
+1365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_NONE          (0x00000000UL)                                          
+1368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_2SAMPLES      (                                        ADC_TR1_AWDFILT
+1369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_3SAMPLES      (                    ADC_TR1_AWDFILT_1                  
+1370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_4SAMPLES      (                    ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT
+1371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_5SAMPLES      (ADC_TR1_AWDFILT_2                                      
+1372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_6SAMPLES      (ADC_TR1_AWDFILT_2 |                     ADC_TR1_AWDFILT
+1373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_7SAMPLES      (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1                  
+1374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_8SAMPLES      (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT
+1375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
+1380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_DISABLE                 (0x00000000UL)                                        /*
+1383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*
+1384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*
+1385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*
+1386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*
+1387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
+1392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_REG_CONT                (0x00000000UL)         /*!< ADC oversampling discontinuo
+1395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuo
+1396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ARM GAS  /tmp/ccICigVb.s 			page 26
+
+
+1398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
+1401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_2                 (0x00000000UL)                                          
+1404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_4                 (                                      ADC_CFGR2_OVSR_0)
+1405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_8                 (                   ADC_CFGR2_OVSR_1                   )
+1406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_16                (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
+1407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2                                      )
+1408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2                    | ADC_CFGR2_OVSR_0)
+1409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1                   )
+1410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
+1411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift
+1416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                                          
+1419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                       
+1420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1 
+1421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 
+1422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                    
+1423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    
+1424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 
+1425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 
+1426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                       
+1427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+1432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode
+1433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_INDEPENDENT           (0x00000000UL)                                          
+1436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_SIMULT       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1       
+1437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_INTERL       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_
+1438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                 ADC_CCR_DUAL_2                  | ADC_
+1439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3                                   | ADC_
+1440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                   ADC_
+1441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                  ADC_CCR_DUAL_1       
+1442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                  ADC_CCR_DUAL_1 | ADC_
+1443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer
+1448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_REG_DMA_EACH_ADC        (0x00000000UL)                                     /*!
+1451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (                 ADC_CCR_MDMA_1                 ) /*!
+1452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B   (                 ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!
+1453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1                 ) /*!
+1454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B   (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!
+ARM GAS  /tmp/ccICigVb.s 			page 27
+
+
+1455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
+1460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE   (0x00000000UL)                                          
+1463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES  (                                                      A
+1464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES  (                                    ADC_CCR_DELAY_1    
+1465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES  (                                    ADC_CCR_DELAY_1 | A
+1466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  (                  ADC_CCR_DELAY_2                      
+1467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (                  ADC_CCR_DELAY_2                   | A
+1468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1    
+1469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | A
+1470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (ADC_CCR_DELAY_3                                        
+1471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3                                     | A
+1472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1    
+1473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1 | A
+1474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave
+1479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimod
+1482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimod
+1483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimod
+1484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+1489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
+1492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,
+1493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         not timeout values.
+1494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         For details on delays values, refer to descriptions in source code
+1495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         above each literal definition.
+1496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
+1500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       not timeout values.                                                  */
+1501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       Timeout values for ADC operations are dependent to device clock      */
+1502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       configuration (system clock versus ADC clock),                       */
+1503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       and therefore must be defined in user application.                   */
+1504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       Indications for estimation of ADC timeout delays, for this           */
+1505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       STM32 series:                                                        */
+1506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       - ADC calibration time: maximum delay is 112/fADC.                   */
+1507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*         (refer to device datasheet, parameter "tCAL")                      */
+1508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       - ADC enable time: maximum delay is 1 conversion cycle.              */
+1509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*         (refer to device datasheet, parameter "tSTAB")                     */
+1510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
+1511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
+ARM GAS  /tmp/ccICigVb.s 			page 28
+
+
+1512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*         cycles                                                             */
+1513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       - ADC conversion time: duration depending on ADC clock and ADC       */
+1514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*         configuration.                                                     */
+1515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*         (refer to device reference manual, section "Timing")               */
+1516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
+1518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Delay set to maximum value (refer to device datasheet,                     */
+1519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* parameter "tADCVREG_STUP").                                                */
+1520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Unit: us                                                                   */
+1521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)  /*!< Delay for ADC stabilization time (ADC vol
+1522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Delay for internal voltage reference stabilization time.                   */
+1524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Delay set to maximum value (refer to device datasheet,                     */
+1525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* parameter "tstart_vrefint").                                               */
+1526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Unit: us                                                                   */
+1527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DELAY_VREFINT_STAB_US           ( 12UL)  /*!< Delay for internal voltage reference s
+1528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Delay for temperature sensor stabilization time.                           */
+1530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Literal set to maximum value (refer to device datasheet,                   */
+1531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* parameter "tSTART").                                                       */
+1532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Unit: us                                                                   */
+1533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DELAY_TEMPSENSOR_STAB_US        (120UL)  /*!< Delay for temperature sensor stabiliza
+1534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Delay required between ADC end of calibration and ADC enable.              */
+1536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Note: On this STM32 series, a minimum number of ADC clock cycles           */
+1537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       are required between ADC end of calibration and ADC enable.          */
+1538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       Wait time can be computed in user application by waiting for the     */
+1539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       equivalent number of CPU cycles, by taking into account              */
+1540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       ratio of CPU clock versus ADC clock prescalers.                      */
+1541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Unit: ADC clock cycles.                                                    */
+1542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES   (  4UL)  /*!< Delay required between ADC end of cali
+1543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Exported macro ------------------------------------------------------------*/
+1554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+1555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+1559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Write a value in ADC register
+1564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __INSTANCE__ ADC Instance
+1565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __REG__ Register to be written
+1566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __VALUE__ Value to be written in the register
+1567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+1568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ARM GAS  /tmp/ccICigVb.s 			page 29
+
+
+1569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE
+1570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Read a value in ADC register
+1573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __INSTANCE__ ADC Instance
+1574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __REG__ Register to be read
+1575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Register value
+1576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+1578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+1583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to get ADC channel number in decimal format
+1588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from literals LL_ADC_CHANNEL_x.
+1589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Example:
+1590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+1591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           will return decimal number "4".
+1592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The input can be a value from functions where a channel
+1593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number is returned, either defined with number
+1594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or with bitfield (only one bit must be set).
+1595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+1596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+1597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+1598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+1599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+1600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+1601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+1602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+1603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+1604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+1605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+1606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+1607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+1608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+1609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+1610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+1611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+1612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+1613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+1614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+1615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+1616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+1617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+1618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+1619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+1620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+1621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+1622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+1623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+1624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+1625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+ARM GAS  /tmp/ccICigVb.s 			page 30
+
+
+1626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+1627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+1628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+1629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+1630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+1631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+1632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+1633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+1634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+1635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+1636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+1637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0 and Max_Data=18
+1638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
+1640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ?                               \
+1641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (                                                                                       \
+1642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
+1643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                                       \
+1644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    :                                                                                       \
+1645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (                                                                                       \
+1646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (uint32_t)POSITION_VAL((__CHANNEL__))                                               \
+1647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                                       \
+1648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+1649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+1652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from number in decimal format.
+1653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Example:
+1654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+1655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           will return a data equivalent to "LL_ADC_CHANNEL_4".
+1656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+1657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+1658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+1659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+1660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+1661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+1662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+1663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+1664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+1665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+1666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+1667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+1668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+1669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+1670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+1671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+1672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+1673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+1674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+1675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+1676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+1677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+1678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+1679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+1680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+1681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+1682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+ARM GAS  /tmp/ccICigVb.s 			page 31
+
+
+1683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+1684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+1685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+1686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+1687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+1688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+1689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+1690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+1691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+1692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+1693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+1694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+1695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+1696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+1697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+1698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+1699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+1700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      comparison with internal channel parameter to be done
+1701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+1702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                             
+1704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__DECIMAL_NB__) <= 9UL) ?                                                                     
+1705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (                                                                                               
+1706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |     
+1707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                             |     
+1708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))      
+1709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                                               
+1710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    :                                                                                               
+1711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (                                                                                               
+1712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                   
+1713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                   
+1714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_PO
+1715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                                               
+1716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+1717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to determine whether the selected channel
+1720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         corresponds to literal definitions of driver.
+1721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The different literal definitions of ADC channels are:
+1722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC internal channel:
+1723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+1724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC external channel (channel connected to a GPIO pin):
+1725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+1726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The channel parameter must be a value defined from literal
+1727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+1728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+1729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+1730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         must not be a value from functions where a channel number is
+1731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         returned from ADC registers,
+1732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         because internal and external channels share the same channel
+1733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number in ADC registers. The differentiation is made only with
+1734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         parameters definitions of driver.
+1735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+1736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+1737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+1738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+1739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+ARM GAS  /tmp/ccICigVb.s 			page 32
+
+
+1740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+1741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+1742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+1743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+1744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+1745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+1746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+1747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+1748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+1749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+1750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+1751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+1752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+1753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+1754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+1755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+1756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+1757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+1758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+1759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+1760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+1761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+1762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+1763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+1764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+1765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+1766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+1767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+1768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+1769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+1770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+1771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+1772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+1773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+1774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+1775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+1776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+1777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channe
+1778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channe
+1779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
+1781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
+1782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to convert a channel defined from parameter
+1785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+1786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+1787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         to its equivalent parameter definition of a ADC external channel
+1788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+1789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The channel parameter can be, additionally to a value
+1790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         defined from parameter definition of a ADC internal channel
+1791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+1792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a value defined from parameter definition of
+1793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+1794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or a value from functions where a channel number is returned
+1795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from ADC registers.
+1796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+ARM GAS  /tmp/ccICigVb.s 			page 33
+
+
+1797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+1798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+1799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+1800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+1801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+1802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+1803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+1804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+1805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+1806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+1807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+1808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+1809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+1810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+1811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+1812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+1813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+1814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+1815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+1816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+1817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+1818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+1819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+1820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+1821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+1822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+1823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+1824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+1825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+1826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+1827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+1828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+1829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+1830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+1831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+1832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+1833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+1834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+1835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+1836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+1837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+1838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+1839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+1840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1
+1841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2
+1842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3
+1843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4
+1844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5
+1845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+1846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+1847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+1848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+1849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+1850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+1851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+1852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+1853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+ARM GAS  /tmp/ccICigVb.s 			page 34
+
+
+1854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+1855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+1856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+1857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+1858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
+1860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+1861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to determine whether the internal channel
+1864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         selected is available on the ADC instance selected.
+1865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The channel parameter must be a value defined from parameter
+1866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+1867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+1868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         must not be a value defined from parameter definition of
+1869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+1870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or a value from functions where a channel number is
+1871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         returned from ADC registers,
+1872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         because internal and external channels share the same channel
+1873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number in ADC registers. The differentiation is made only with
+1874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         parameters definitions of driver.
+1875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_INSTANCE__ ADC instance
+1876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+1877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+1878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+1879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+1880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+1881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+1882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+1883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+1884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+1885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+1886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+1887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+1888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+1889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+1890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+1891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+1892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+1893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+1894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+1895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+1896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+1897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value "0" if the internal channel selected is not available on the ADC instance selecte
+1898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Value "1" if the internal channel selected is available on the ADC instance selected.
+1899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+1901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+1902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((((__ADC_INSTANCE__) == ADC1)                                               \
+1903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+1905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+1906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+ARM GAS  /tmp/ccICigVb.s 			page 35
+
+
+1911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC2)                                               \
+1912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+1914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+1915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC3)                                               \
+1919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
+1921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC4)                                               \
+1927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6)         ||                    \
+1929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC5)                                               \
+1934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5)         ||                    \
+1936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) ||                    \
+1937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4)         ||                    \
+1938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+1943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #elif defined(STM32G471xx)
+1944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+1945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((((__ADC_INSTANCE__) == ADC1)                                               \
+1946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+1948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+1949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC2)                                               \
+1955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+1957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+1958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC3)                                               \
+1962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
+1964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+ARM GAS  /tmp/ccICigVb.s 			page 36
+
+
+1968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+1969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+1970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+1971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((((__ADC_INSTANCE__) == ADC1)                                               \
+1972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+1974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+1975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC2)                                               \
+1981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+1983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+1984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+1987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #elif defined(STM32G491xx) || defined(STM32G4A1xx)
+1988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+1989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((((__ADC_INSTANCE__) == ADC1)                                               \
+1990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+1992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+1993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC2)                                               \
+1999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+2000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+2001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+2002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+2004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+2005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC3)                                               \
+2006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+2007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
+2008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6)         ||                    \
+2009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+2010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+2012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif
+2014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to define ADC analog watchdog parameter:
+2017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         define a single channel to monitor with analog watchdog
+2018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from sequencer channel and groups definition.
+2019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+2020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example:
+2021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           LL_ADC_SetAnalogWDMonitChannels(
+2022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC1, LL_ADC_AWD1,
+2023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+2024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+ARM GAS  /tmp/ccICigVb.s 			page 37
+
+
+2025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+2026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+2027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+2028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+2029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+2030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+2031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+2032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+2033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+2034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+2035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+2036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+2037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+2038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+2039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+2040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+2041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+2042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+2043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+2044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+2045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+2046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+2047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+2048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+2049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+2050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+2051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+2052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+2053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+2054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+2055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+2056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+2057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+2058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+2059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+2060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+2061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+2062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+2063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+2064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+2065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+2066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+2067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      comparison with internal channel parameter to be done
+2068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+2069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __GROUP__ This parameter can be one of the following values:
+2070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_GROUP_REGULAR
+2071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_GROUP_INJECTED
+2072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+2073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+2074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_DISABLE
+2075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+2076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+2077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+2078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+2079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+2080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+2081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+ARM GAS  /tmp/ccICigVb.s 			page 38
+
+
+2082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+2083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+2084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+2085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+2086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+2087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+2088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+2089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+2090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+2091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+2092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+2093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+2094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+2095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+2096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+2097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+2098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+2099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+2100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+2101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+2102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+2103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+2104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+2105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+2106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+2107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+2108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+2109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+2110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+2111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+2112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+2113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+2114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+2115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+2116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+2117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+2118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+2119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+2120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+2121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+2122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+2123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+2124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+2125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+2126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+2127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+2128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+2129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+2130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+2131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+2132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+2133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+2134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+2135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
+2136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
+2137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+2138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG  (0)(1)
+ARM GAS  /tmp/ccICigVb.s 			page 39
+
+
+2139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ  (0)(1)
+2140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
+2141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG  (0)(5)
+2142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ  (0)(5)
+2143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
+2144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(6)
+2145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(6)
+2146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (6)
+2147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (0)(1)
+2148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (0)(1)
+2149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ         (1)
+2150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (0)(2)
+2151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (0)(2)
+2152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ         (2)
+2153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     (0)(2)
+2154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     (0)(2)
+2155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ    (2)
+2156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     (0)(3)
+2157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     (0)(3)
+2158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ    (3)
+2159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG          (0)(5)
+2160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ          (0)(5)
+2161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ         (5)
+2162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG          (0)(5)
+2163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ          (0)(5)
+2164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ         (5)
+2165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG          (0)(4)
+2166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ          (0)(4)
+2167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ         (4)
+2168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+2169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
+2170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+2171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+2172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+2173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+2174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+2175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+2176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+2177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+2178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                    
+2180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                           
+2181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                  
+2182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    :                                                                                               
+2183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                          
+2184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                 
+2185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    :                                                                                               
+2186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) 
+2187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to set the value of ADC analog watchdog threshold high
+2191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or low in function of ADC resolution, when ADC resolution is
+2192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         different of 12 bits.
+2193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
+2194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or @ref LL_ADC_SetAnalogWDThresholds().
+2195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example, with a ADC resolution of 8 bits, to set the value of
+ARM GAS  /tmp/ccICigVb.s 			page 40
+
+
+2196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog threshold high (on 8 bits):
+2197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           LL_ADC_SetAnalogWDThresholds
+2198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *            (< ADCx param >,
+2199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8
+2200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *            );
+2201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+2202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+2207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+2208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+2210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+2211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to get the value of ADC analog watchdog threshold high
+2214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or low in function of ADC resolution, when ADC resolution is
+2215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         different of 12 bits.
+2216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+2217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example, with a ADC resolution of 8 bits, to get the value of
+2218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog threshold high (on 8 bits):
+2219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+2220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *            (LL_ADC_RESOLUTION_8B,
+2221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+2222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *            );
+2223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+2224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+2229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+2230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+2232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+2233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to get the ADC analog watchdog threshold high
+2236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or low from raw value containing both thresholds concatenated.
+2237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+2238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example, to get analog watchdog threshold high from the register raw value:
+2239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both
+2240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
+2241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+2242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+2243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+2244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+2245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)       \
+2247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_
+2248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to set the ADC calibration value with both single ended
+2251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and differential modes calibration factors concatenated.
+2252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().
+ARM GAS  /tmp/ccICigVb.s 			page 41
+
+
+2253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example, to set calibration factors single ended to 0x55
+2254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and differential ended to 0x2A:
+2255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           LL_ADC_SetCalibrationFactor(
+2256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC1,
+2257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
+2258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
+2259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
+2260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+2261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIA
+2263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__)
+2264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+2266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to get the ADC multimode conversion data of ADC master
+2268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or ADC slave from raw value with both ADC conversion data concatenated.
+2269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This macro is intended to be used when multimode transfer by DMA
+2270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+2271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         In this case the transferred data need to processed with this macro
+2272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         to separate the conversion data of ADC master and ADC slave.
+2273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+2274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_MASTER
+2275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_SLAVE
+2276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+2277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+2278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) 
+2280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_C
+2281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+2282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+2284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to select, from a ADC instance, to which ADC instance
+2286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         it has a dependence in multimode (ADC master of the corresponding
+2287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC common instance).
+2288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of device with multimode available and a mix of
+2289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instances compliant and not compliant with multimode feature,
+2290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instances not compliant with multimode feature are
+2291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         considered as master instances (do not depend to
+2292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         any other ADC instance).
+2293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADCx__ ADC instance
+2294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
+2295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC5)
+2297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+2298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ( ( ((__ADCx__) == ADC2)                                                     \
+2299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     )?                                                                         \
+2300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     (ADC1)                                                                     \
+2301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     :                                                                          \
+2302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     ( ( ((__ADCx__) == ADC4)                                                   \
+2303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )?                                                                       \
+2304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       (ADC3)                                                                   \
+2305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       :                                                                        \
+2306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       (__ADCx__)                                                               \
+2307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     )                                                                          \
+2308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #else
+ARM GAS  /tmp/ccICigVb.s 			page 42
+
+
+2310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+2311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ( ( ((__ADCx__) == ADC2)                                                     \
+2312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     )?                                                                         \
+2313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     (ADC1)                                                                     \
+2314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     :                                                                          \
+2315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     (__ADCx__)                                                                 \
+2316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC5 */
+2318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+2319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to select the ADC common instance
+2322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         to which is belonging the selected ADC instance.
+2323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   ADC common register instance can be used for:
+2324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Set parameters common to several ADC instances
+2325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Multimode (for devices with several ADC instances)
+2326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+2327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADCx__ ADC instance
+2328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval ADC common register instance
+2329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC345_COMMON)
+2331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
+2332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2))                              \
+2333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     ? (                                                                        \
+2334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (ADC12_COMMON)                                                          \
+2335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       :                                                                        \
+2337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       (                                                                        \
+2338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (ADC345_COMMON)                                                         \
+2339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #else
+2342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_COMMON_INSTANCE(__ADCx__)  (ADC12_COMMON)
+2343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC345_COMMON */
+2344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to check if all ADC instances sharing the same
+2346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC common instance are disabled.
+2347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This check is required by functions with setting conditioned to
+2348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+2349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         All ADC instances of the ADC common group must be disabled.
+2350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+2351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On devices with only 1 ADC common instance, parameter of this macro
+2352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is useless and can be ignored (parameter kept for compatibility
+2353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         with devices featuring several ADC common instances).
+2354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADCXY_COMMON__ ADC common instance
+2355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value "0" if all ADC instances sharing the same ADC common instance
+2357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         are disabled.
+2358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Value "1" if at least one ADC instance sharing the same ADC common instance
+2359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is enabled.
+2360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC345_COMMON)
+2362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC4) &&  defined(ADC5)
+2363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+2364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
+2365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     ? (                                                                        \
+2366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (LL_ADC_IsEnabled(ADC1) |                                               \
+ARM GAS  /tmp/ccICigVb.s 			page 43
+
+
+2367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         LL_ADC_IsEnabled(ADC2)  )                                              \
+2368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       :                                                                        \
+2370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       (                                                                        \
+2371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (LL_ADC_IsEnabled(ADC3) |                                               \
+2372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         LL_ADC_IsEnabled(ADC4) |                                               \
+2373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         LL_ADC_IsEnabled(ADC5)  )                                              \
+2374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #else
+2377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+2378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
+2379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     ? (                                                                        \
+2380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (LL_ADC_IsEnabled(ADC1) |                                               \
+2381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         LL_ADC_IsEnabled(ADC2)  )                                              \
+2382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       :                                                                        \
+2384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       (LL_ADC_IsEnabled(ADC3))                                                 \
+2385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC4 && ADC5 */
+2387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #else
+2388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+2389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
+2390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif
+2391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to define the ADC conversion data full-scale digital
+2394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         value corresponding to the selected ADC resolution.
+2395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   ADC conversion data full-scale corresponds to voltage range
+2396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         determined by analog voltage references Vref+ and Vref-
+2397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (refer to reference manual).
+2398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+2399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion dat
+2404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+2406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
+2407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to convert the ADC conversion data from
+2410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a resolution to another resolution.
+2411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __DATA__ ADC conversion data to be converted
+2412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
+2413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This parameter can be one of the following values:
+2414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+2419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This parameter can be one of the following values:
+2420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+ARM GAS  /tmp/ccICigVb.s 			page 44
+
+
+2424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval ADC conversion data to the requested resolution
+2425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+2427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                          __ADC_RESOLUTION_CURRENT__,\
+2428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                          __ADC_RESOLUTION_TARGET__)          \
+2429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** (((__DATA__)                                                                 \
+2430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \
+2431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****  >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \
+2432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** )
+2433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to calculate the voltage (unit: mVolt)
+2436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         corresponding to a ADC conversion data (unit: digital value).
+2437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Analog reference voltage (Vref+) must be either known from
+2438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         user board environment or can be calculated using ADC measurement
+2439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+2440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+2441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+2442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                       (unit: digital value).
+2443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+2444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+2449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+2451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                       __ADC_DATA__,\
+2452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                       __ADC_RESOLUTION__)                    \
+2453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
+2454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
+2455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** )
+2456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to calculate analog reference voltage (Vref+)
+2459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (unit: mVolt) from ADC conversion data of internal voltage
+2460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         reference VrefInt.
+2461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Computation is using VrefInt calibration value
+2462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         stored in system memory for each device during production.
+2463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This voltage depends on user board environment: voltage level
+2464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         connected to pin Vref+.
+2465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         On devices with small package, the pin Vref+ is not present
+2466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and internally bonded to pin Vdda.
+2467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, calibration data of internal voltage reference
+2468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         VrefInt corresponds to a resolution of 12 bits,
+2469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         this is the recommended ADC resolution to convert voltage of
+2470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal voltage reference VrefInt.
+2471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Otherwise, this macro performs the processing to scale
+2472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion data to 12 bits.
+2473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+2474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of internal voltage reference VrefInt (unit: digital value).
+2475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+2476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Analog reference voltage (unit: mV)
+ARM GAS  /tmp/ccICigVb.s 			page 45
+
+
+2481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+2483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                          __ADC_RESOLUTION__)                 \
+2484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
+2485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****  / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
+2486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                     (__ADC_RESOLUTION__),                    \
+2487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                     LL_ADC_RESOLUTION_12B)                   \
+2488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** )
+2489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+2492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from ADC conversion data of internal temperature sensor.
+2493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Computation is using temperature sensor calibration values
+2494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         stored in system memory for each device during production.
+2495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Calculation formula:
+2496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
+2497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+2498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+2499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
+2500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
+2501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+2502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
+2503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                            TEMP_DEGC_CAL1 (calibrated in factory)
+2504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
+2505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                            TEMP_DEGC_CAL2 (calibrated in factory)
+2506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Caution: Calculation relevancy under reserve that calibration
+2507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  parameters are correct (address and data).
+2508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  To calculate temperature using temperature sensor
+2509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  datasheet typical values (generic values less, therefore
+2510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  less accurate than calibrated values),
+2511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+2512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   As calculation input, the analog reference voltage (Vref+) must be
+2513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         defined as it impacts the ADC LSB equivalent voltage.
+2514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Analog reference voltage (Vref+) must be either known from
+2515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         user board environment or can be calculated using ADC measurement
+2516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+2517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, calibration data of temperature sensor
+2518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         corresponds to a resolution of 12 bits,
+2519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         this is the recommended ADC resolution to convert voltage of
+2520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         temperature sensor.
+2521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Otherwise, this macro performs the processing to scale
+2522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion data to 12 bits.
+2523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
+2524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+2525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                 temperature sensor (unit: digital value).
+2526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
+2527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                 sensor voltage has been measured.
+2528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This parameter can be one of the following values:
+2529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Temperature (unit: degree Celsius)
+2534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+2536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                   __TEMPSENSOR_ADC_DATA__,\
+2537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                   __ADC_RESOLUTION__)                            \
+ARM GAS  /tmp/ccICigVb.s 			page 46
+
+
+2538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
+2539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                   (__ADC_RESOLUTION__),          \
+2540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                   LL_ADC_RESOLUTION_12B)         \
+2541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                  * (__VREFANALOG_VOLTAGE__))                                     \
+2542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                 / TEMPSENSOR_CAL_VREFANALOG)                                     \
+2543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
+2544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
+2545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+2546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****  ) + TEMPSENSOR_CAL1_TEMP                                                        \
+2547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** )
+2548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+2551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from ADC conversion data of internal temperature sensor.
+2552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Computation is using temperature sensor typical values
+2553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (refer to device datasheet).
+2554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Calculation formula:
+2555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+2556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                         / Avg_Slope + CALx_TEMP
+2557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
+2558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                   (unit: digital value)
+2559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                Avg_Slope        = temperature sensor slope
+2560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                   (unit: uV/Degree Celsius)
+2561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
+2562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                   temperature CALx_TEMP (unit: mV)
+2563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Caution: Calculation relevancy under reserve the temperature sensor
+2564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  of the current device has characteristics in line with
+2565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  datasheet typical values.
+2566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  If temperature sensor calibration values are available on
+2567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+2568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  temperature calculation will be more accurate using
+2569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+2570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   As calculation input, the analog reference voltage (Vref+) must be
+2571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         defined as it impacts the ADC LSB equivalent voltage.
+2572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Analog reference voltage (Vref+) must be either known from
+2573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         user board environment or can be calculated using ADC measurement
+2574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+2575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   ADC measurement data must correspond to a resolution of 12 bits
+2576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (full scale digital value 4095). If not the case, the data must be
+2577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         preliminarily rescaled to an equivalent resolution of 12 bits.
+2578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical v
+2579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                       On STM32G4, refer to device datasheet parameter "Avg_Slop
+2580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical
+2581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                       On STM32G4, refer to device datasheet parameter "V30" (co
+2582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature s
+2583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
+2584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit:
+2585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor volta
+2586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This parameter can be one of the following values:
+2587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Temperature (unit: degree Celsius)
+2592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+2594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              __TEMPSENSOR_TYP_CALX_V__,\
+ARM GAS  /tmp/ccICigVb.s 			page 47
+
+
+2595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              __TEMPSENSOR_CALX_TEMP__,\
+2596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              __VREFANALOG_VOLTAGE__,\
+2597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              __TEMPSENSOR_ADC_DATA__,\
+2598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              __ADC_RESOLUTION__)            \
+2599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
+2600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
+2601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****               * 1000UL)                                                     \
+2602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     -                                                                       \
+2603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
+2604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****               * 1000UL)                                                     \
+2605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                        \
+2606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                \
+2607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****  ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                    \
+2608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** )
+2609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+2612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+2616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Exported functions --------------------------------------------------------*/
+2620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+2621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+2622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+2625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+2626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Note: LL ADC functions to set DMA transfer are located into sections of    */
+2628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       configuration of ADC instance, groups and multimode (if available):  */
+2629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
+2630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Function to help to configure DMA transfer from ADC: retrieve the
+2633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC register address from ADC instance and a list of ADC registers
+2634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         intended to be used (most commonly) with DMA transfer.
+2635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   These ADC registers are data registers:
+2636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         when ADC conversion data is available in ADC data registers,
+2637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC generates a DMA transfer request.
+2638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This macro is intended to be used with LL DMA driver, refer to
+2639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         function "LL_DMA_ConfigAddresses()".
+2640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example:
+2641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           LL_DMA_ConfigAddresses(DMA1,
+2642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                  LL_DMA_CHANNEL_1,
+2643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+2644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                  (uint32_t)&< array or variable >,
+2645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+2646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with several ADC: in multimode, some devices
+2647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use a different data register outside of ADC instance scope
+2648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (common data register). This macro manages this register difference,
+2649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         only ADC instance has to be set as parameter.
+2650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n
+2651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n
+ARM GAS  /tmp/ccICigVb.s 			page 48
+
+
+2652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr
+2653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+2654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Register This parameter can be one of the following values:
+2655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+2656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+2657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+2658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) Available on devices with several ADC instances.
+2659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval ADC register address
+2660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+2662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+2663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t data_reg_addr;
+2665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
+2667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+2668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     /* Retrieve address of register DR */
+2669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     data_reg_addr = (uint32_t) &(ADCx->DR);
+2670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   }
+2671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+2672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+2673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     /* Retrieve address of register CDR */
+2674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+2675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   }
+2676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return data_reg_addr;
+2678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #else
+2680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+2681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Prevent unused argument(s) compilation warning */
+2683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (void)(Register);
+2684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Retrieve address of register DR */
+2686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t) &(ADCx->DR);
+2687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+2689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+2692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to
+2695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+2696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set parameter common to several ADC: Clock source and prescaler.
+2700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, if ADC group injected is used, some
+2701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         clock ratio constraints between ADC clock and AHB clock
+2702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         must be respected.
+2703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to reference manual.
+2704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+2705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+2706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         All ADC instances of the ADC common group must be disabled.
+2707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+2708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instance or by using helper macro helper macro
+ARM GAS  /tmp/ccICigVb.s 			page 49
+
+
+2709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+2710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n
+2711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      PRESC          LL_ADC_SetCommonClock
+2712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+2713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  CommonClock This parameter can be one of the following values:
+2715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+2716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+2717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+2718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+2719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+2720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+2721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+2722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+2723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+2724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+2725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+2726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+2727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+2728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+2729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+2730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+2731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+2733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
+2735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get parameter common to several ADC: Clock source and prescaler.
+2739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n
+2740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      PRESC          LL_ADC_GetCommonClock
+2741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+2742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+2744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+2745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+2746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+2747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+2748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+2749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+2750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+2751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+2752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+2753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+2754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+2755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+2756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+2757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+2758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+2759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
+2761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
+2763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 50
+
+
+2766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set parameter common to several ADC: measurement path to
+2767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal channels (VrefInt, temperature sensor, ...).
+2768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Configure all paths (overwrite current configuration).
+2769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   One or several values can be selected.
+2770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+2771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+2772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         The values not selected are removed from configuration.
+2773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Stabilization time of measurement path to internal channel:
+2774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         After enabling internal paths, before starting ADC conversion,
+2775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a delay is required for internal voltage reference and
+2776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         temperature sensor stabilization time.
+2777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet.
+2778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+2779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+2780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   ADC internal channel sampling time constraint:
+2781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         For ADC conversion of internal channels,
+2782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a sampling time minimum value is required.
+2783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet.
+2784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
+2785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalCh\n
+2786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalCh
+2787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+2788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  PathInternal This parameter can be a combination of the following values:
+2790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+2791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+2792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+2793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+2794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+2795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Path
+2797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal)
+2799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set parameter common to several ADC: measurement path to
+2803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal channels (VrefInt, temperature sensor, ...).
+2804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Add paths to the current configuration.
+2805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   One or several values can be selected.
+2806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+2807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+2808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Stabilization time of measurement path to internal channel:
+2809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         After enabling internal paths, before starting ADC conversion,
+2810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a delay is required for internal voltage reference and
+2811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         temperature sensor stabilization time.
+2812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet.
+2813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+2814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+2815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   ADC internal channel sampling time constraint:
+2816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         For ADC conversion of internal channels,
+2817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a sampling time minimum value is required.
+2818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet.
+2819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChAdd\n
+2820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalChAdd\n
+2821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalChAdd
+2822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+ARM GAS  /tmp/ccICigVb.s 			page 51
+
+
+2823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  PathInternal This parameter can be a combination of the following values:
+2825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+2826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+2827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+2828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+2829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+2830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t P
+2832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCxy_COMMON->CCR, PathInternal);
+2834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set parameter common to several ADC: measurement path to
+2838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal channels (VrefInt, temperature sensor, ...).
+2839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Remove paths to the current configuration.
+2840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   One or several values can be selected.
+2841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+2842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+2843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChRem\n
+2844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalChRem\n
+2845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalChRem
+2846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+2847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  PathInternal This parameter can be a combination of the following values:
+2849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+2850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+2851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+2852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+2853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+2854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t P
+2856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
+2858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get parameter common to several ADC: measurement path to internal
+2862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         channels (VrefInt, temperature sensor, ...).
+2863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   One or several values can be selected.
+2864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+2865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+2866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
+2867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VSENSESEL      LL_ADC_GetCommonPathInternalCh\n
+2868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VBATSEL        LL_ADC_GetCommonPathInternalCh
+2869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+2870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be a combination of the following values:
+2872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+2873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+2874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+2875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+2876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+2878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSE
+ARM GAS  /tmp/ccICigVb.s 			page 52
+
+
+2880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+2884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC ins
+2887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+2888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC calibration factor in the mode single-ended
+2892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or differential (for devices with differential mode available).
+2893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function is intended to set calibration parameters
+2894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without having to perform a new calibration using
+2895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref LL_ADC_StartCalibration().
+2896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with differential mode available:
+2897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Calibration of offset is specific to each of
+2898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         single-ended and differential modes
+2899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (calibration factor must be specified for each of these
+2900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         differential modes, if used afterwards and if the application
+2901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         requires their calibration).
+2902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of setting calibration factors of both modes single ended
+2903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
+2904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         both calibration factors must be concatenated.
+2905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         To perform this processing, use helper macro
+2906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
+2907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+2908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+2909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled, without calibration on going, without conversion
+2910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on going on group regular.
+2911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n
+2912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor
+2913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+2914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SingleDiff This parameter can be one of the following values:
+2915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SINGLE_ENDED
+2916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+2917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
+2918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+2919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+2920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t C
+2922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CALFACT,
+2924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
+2925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLED
+2926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC calibration factor in the mode single-ended
+2930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or differential (for devices with differential mode available).
+2931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Calibration factors are set by hardware after performing
+2932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a calibration run using function @ref LL_ADC_StartCalibration().
+2933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with differential mode available:
+2934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Calibration of offset is specific to each of
+2935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         single-ended and differential modes
+2936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n
+ARM GAS  /tmp/ccICigVb.s 			page 53
+
+
+2937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor
+2938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+2939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SingleDiff This parameter can be one of the following values:
+2940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SINGLE_ENDED
+2941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+2942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0x7F
+2943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+2945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Retrieve bits with position in register depending on parameter           */
+2947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* "SingleDiff".                                                            */
+2948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */
+2949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* containing other bits reserved for other purpose.                        */
+2950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CALFACT,
+2951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC
+2952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                                                   ADC_SINGLEDIFF_CA
+2953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC resolution.
+2957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to reference manual for alignments formats
+2958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         dependencies to ADC resolutions.
+2959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+2960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+2961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+2962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+2963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     RES            LL_ADC_SetResolution
+2964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+2965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Resolution This parameter can be one of the following values:
+2966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+2971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+2973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
+2975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC resolution.
+2979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to reference manual for alignments formats
+2980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         dependencies to ADC resolutions.
+2981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     RES            LL_ADC_GetResolution
+2982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+2983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+2984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
+2990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
+2992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ARM GAS  /tmp/ccICigVb.s 			page 54
+
+
+2994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC conversion data alignment.
+2996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Refer to reference manual for alignments formats
+2997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         dependencies to ADC resolutions.
+2998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+2999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     ALIGN          LL_ADC_SetDataAlignment
+3003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  DataAlignment This parameter can be one of the following values:
+3005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+3006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+3007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+3010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
+3012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC conversion data alignment.
+3016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Refer to reference manual for alignments formats
+3017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         dependencies to ADC resolutions.
+3018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     ALIGN          LL_ADC_GetDataAlignment
+3019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+3022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+3023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+3025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
+3027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC low power mode.
+3031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Description of ADC low power modes:
+3032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC low power mode "auto wait": Dynamic low power mode,
+3033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions occurrences are limited to the minimum necessary
+3034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           in order to reduce power consumption.
+3035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           New ADC conversion starts only when the previous
+3036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           unitary conversion data (for ADC group regular)
+3037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           or previous sequence conversions data (for ADC group injected)
+3038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           has been retrieved by user software.
+3039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           In the meantime, ADC remains idle: does not performs any
+3040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           other conversion.
+3041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This mode allows to automatically adapt the ADC conversions
+3042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           triggers to the speed of the software that reads the data.
+3043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Moreover, this avoids risk of overrun for low frequency
+3044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           applications.
+3045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           How to use this low power mode:
+3046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - It is not recommended to use with interruption or DMA
+3047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             since these modes have to clear immediately the EOC flag
+3048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (by CPU to free the IRQ pending event or by DMA).
+3049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Auto wait will work but fort a very short time, discarding
+3050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             its intended benefit (except specific case of high load of CPU
+ARM GAS  /tmp/ccICigVb.s 			page 55
+
+
+3051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             or DMA transfers which can justify usage of auto wait).
+3052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Do use with polling: 1. Start conversion,
+3053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             2. Later on, when conversion data is needed: poll for end of
+3054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             conversion  to ensure that conversion is completed and
+3055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             retrieve ADC conversion data. This will trig another
+3056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC conversion start.
+3057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC low power mode "auto power-off" (feature available on
+3058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+3059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the ADC automatically powers-off after a conversion and
+3060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           automatically wakes up when a new conversion is triggered
+3061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (with startup time between trigger and start of sampling).
+3062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This feature can be combined with low power mode "auto wait".
+3063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   With ADC low power mode "auto wait", the ADC conversion data read
+3064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is corresponding to previous ADC conversion start, independently
+3065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of delay during which ADC was idle.
+3066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Therefore, the ADC conversion data may be outdated: does not
+3067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         correspond to the current voltage level on the selected
+3068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC channel.
+3069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode
+3074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  LowPowerMode This parameter can be one of the following values:
+3076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_LP_MODE_NONE
+3077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_LP_AUTOWAIT
+3078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+3081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
+3083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC low power mode:
+3087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Description of ADC low power modes:
+3088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC low power mode "auto wait": Dynamic low power mode,
+3089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions occurrences are limited to the minimum necessary
+3090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           in order to reduce power consumption.
+3091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           New ADC conversion starts only when the previous
+3092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           unitary conversion data (for ADC group regular)
+3093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           or previous sequence conversions data (for ADC group injected)
+3094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           has been retrieved by user software.
+3095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           In the meantime, ADC remains idle: does not performs any
+3096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           other conversion.
+3097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This mode allows to automatically adapt the ADC conversions
+3098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           triggers to the speed of the software that reads the data.
+3099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Moreover, this avoids risk of overrun for low frequency
+3100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           applications.
+3101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           How to use this low power mode:
+3102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - It is not recommended to use with interruption or DMA
+3103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             since these modes have to clear immediately the EOC flag
+3104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (by CPU to free the IRQ pending event or by DMA).
+3105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Auto wait will work but fort a very short time, discarding
+3106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             its intended benefit (except specific case of high load of CPU
+3107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             or DMA transfers which can justify usage of auto wait).
+ARM GAS  /tmp/ccICigVb.s 			page 56
+
+
+3108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Do use with polling: 1. Start conversion,
+3109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             2. Later on, when conversion data is needed: poll for end of
+3110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             conversion  to ensure that conversion is completed and
+3111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             retrieve ADC conversion data. This will trig another
+3112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC conversion start.
+3113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC low power mode "auto power-off" (feature available on
+3114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+3115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the ADC automatically powers-off after a conversion and
+3116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           automatically wakes up when a new conversion is triggered
+3117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (with startup time between trigger and start of sampling).
+3118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This feature can be combined with low power mode "auto wait".
+3119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   With ADC low power mode "auto wait", the ADC conversion data read
+3120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is corresponding to previous ADC conversion start, independently
+3121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of delay during which ADC was idle.
+3122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Therefore, the ADC conversion data may be outdated: does not
+3123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         correspond to the current voltage level on the selected
+3124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC channel.
+3125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode
+3126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_LP_MODE_NONE
+3129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_LP_AUTOWAIT
+3130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
+3132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
+3134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC selected offset number 1, 2, 3 or 4.
+3138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function set the 2 items of offset configuration:
+3139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC channel to which the offset programmed will be applied
+3140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (independently of channel mapped on ADC group regular
+3141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           or group injected)
+3142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Offset level (offset to be subtracted from the raw
+3143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           converted data).
+3144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Caution: Offset format is dependent to ADC resolution:
+3145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         offset has to be left-aligned on bit 11, the LSB (right bits)
+3146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         are set to 0.
+3147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function enables the offset, by default. It can be forced
+3148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         to disable state using function LL_ADC_SetOffsetState().
+3149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If a channel is mapped on several offsets numbers, only the offset
+3150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         with the lowest value is considered for the subtraction.
+3151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On STM32G4, some fast channels are available: fast analog inputs
+3156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         coming from GPIO pads (ADC_IN1..5).
+3157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n
+3158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR1     OFFSET1        LL_ADC_SetOffset\n
+3159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n
+3160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n
+3161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2        LL_ADC_SetOffset\n
+3162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n
+3163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n
+3164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3        LL_ADC_SetOffset\n
+ARM GAS  /tmp/ccICigVb.s 			page 57
+
+
+3165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n
+3166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n
+3167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4        LL_ADC_SetOffset\n
+3168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4_EN     LL_ADC_SetOffset
+3169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be one of the following values:
+3176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+3177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+3178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+3179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+3180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+3181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+3182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+3183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+3184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+3185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+3186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+3187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+3188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+3189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+3190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+3191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+3192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+3193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+3194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+3195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+3196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+3197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+3198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+3199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+3200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+3201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+3202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+3203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+3204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+3205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+3206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+3207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+3208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+3209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+3210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+3211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+3212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+3213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+3214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+3215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+3216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+3217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+3218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32
+3221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ARM GAS  /tmp/ccICigVb.s 			page 58
+
+
+3222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+3225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+3226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+3227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+3231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Channel to which the offset programmed will be applied
+3232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (independently of channel mapped on ADC group regular
+3233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or group injected)
+3234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Usage of the returned channel number:
+3235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To reinject this channel into another function LL_ADC_xxx:
+3236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the returned channel number is only partly formatted on definition
+3237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+3238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           with parts of literals LL_ADC_CHANNEL_x or using
+3239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+3240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Then the selected literal LL_ADC_CHANNEL_x can be used
+3241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           as parameter for another function.
+3242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To get the channel number in decimal format:
+3243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           process the returned value with the helper macro
+3244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+3245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On STM32G4, some fast channels are available: fast analog inputs
+3246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         coming from GPIO pads (ADC_IN1..5).
+3247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n
+3248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n
+3249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n
+3250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel
+3251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+3259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+3260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+3261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+3262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+3263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+3264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+3265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+3266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+3267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+3268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+3269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+3270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+3271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+3272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+3273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+3274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+3275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+3276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+3277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+3278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+ARM GAS  /tmp/ccICigVb.s 			page 59
+
+
+3279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+3280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+3281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+3282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+3283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+3284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+3285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+3286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+3287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+3288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+3289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+3290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+3291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+3292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+3293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+3294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+3295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+3296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+3297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+3298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+3299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+3300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      comparison with internal channel parameter to be done
+3301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+3302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
+3304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
+3308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+3312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Offset level (offset to be subtracted from the raw
+3313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         converted data).
+3314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Caution: Offset format is dependent to ADC resolution:
+3315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         offset has to be left-aligned on bit 11, the LSB (right bits)
+3316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         are set to 0.
+3317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
+3318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
+3319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
+3320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel
+3321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+3328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
+3330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
+3334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ARM GAS  /tmp/ccICigVb.s 			page 60
+
+
+3336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
+3338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         force offset state disable or enable
+3339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without modifying offset channel or offset value.
+3340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function should be needed only in case of offset to be
+3341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         enabled-disabled dynamically, and should not be needed in other cases:
+3342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         function LL_ADC_SetOffset() automatically enables the offset.
+3343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_SetOffsetState\n
+3348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2_EN     LL_ADC_SetOffsetState\n
+3349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3_EN     LL_ADC_SetOffsetState\n
+3350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4_EN     LL_ADC_SetOffsetState
+3351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  OffsetState This parameter can be one of the following values:
+3358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_DISABLE
+3359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_ENABLE
+3360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetStat
+3363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+3367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN,
+3368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              OffsetState);
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+3373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         offset state disabled or enabled.
+3374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_GetOffsetState\n
+3375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2_EN     LL_ADC_GetOffsetState\n
+3376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3_EN     LL_ADC_GetOffsetState\n
+3377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4_EN     LL_ADC_GetOffsetState
+3378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_DISABLE
+3386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_ENABLE
+3387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
+3389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
+ARM GAS  /tmp/ccICigVb.s 			page 61
+
+
+3393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
+3397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         choose offset sign.
+3398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSETPOS      LL_ADC_SetOffsetSign\n
+3403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSETPOS      LL_ADC_SetOffsetSign\n
+3404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSETPOS      LL_ADC_SetOffsetSign\n
+3405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSETPOS      LL_ADC_SetOffsetSign
+3406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  OffsetSign This parameter can be one of the following values:
+3413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+3414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+3415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
+3418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+3422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSETPOS,
+3423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              OffsetSign);
+3424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+3428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         offset sign if positive or negative.
+3429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSETPOS      LL_ADC_GetOffsetSign\n
+3430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSETPOS      LL_ADC_GetOffsetSign\n
+3431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSETPOS      LL_ADC_GetOffsetSign\n
+3432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSETPOS      LL_ADC_GetOffsetSign
+3433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+3441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+3442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety)
+3444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
+3448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ARM GAS  /tmp/ccICigVb.s 			page 62
+
+
+3450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
+3452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         choose offset saturation mode.
+3453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     SATEN          LL_ADC_SetOffsetSaturation\n
+3458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     SATEN          LL_ADC_SetOffsetSaturation\n
+3459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     SATEN          LL_ADC_SetOffsetSaturation\n
+3460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     SATEN          LL_ADC_SetOffsetSaturation
+3461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  OffsetSaturation This parameter can be one of the following values:
+3468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
+3469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
+3470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Offse
+3473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+3477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_SATEN,
+3478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              OffsetSaturation);
+3479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+3483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         offset saturation if enabled or disabled.
+3484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     SATEN          LL_ADC_GetOffsetSaturation\n
+3485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     SATEN          LL_ADC_GetOffsetSaturation\n
+3486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     SATEN          LL_ADC_GetOffsetSaturation\n
+3487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     SATEN          LL_ADC_GetOffsetSaturation
+3488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
+3496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
+3497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
+3499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN);
+3503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC gain compensation.
+ARM GAS  /tmp/ccICigVb.s 			page 63
+
+
+3507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function set the gain compensation coefficient
+3508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         that is applied to raw converted data using the formula:
+3509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           DATA = DATA(raw) * (gain compensation coef) / 4096
+3510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function enables the gain compensation if given
+3511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         coefficient is above 0, otherwise it disables it.
+3512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Gain compensation when enabled is applied to all channels.
+3513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll GCOMP    GCOMPCOEFF     LL_ADC_SetGainCompensation\n
+3518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    GCOMP          LL_ADC_SetGainCompensation
+3519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  GainCompensation This parameter can be:
+3521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         0           Gain compensation will be disabled and value set to 0
+3522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         1 -> 16393  Gain compensation will be enabled with specified value
+3523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
+3526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
+3528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCO
+3529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get the ADC gain compensation value
+3533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll GCOMP    GCOMPCOEFF     LL_ADC_GetGainCompensation\n
+3534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    GCOMP          LL_ADC_GetGainCompensation
+3535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be:
+3537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         0           Gain compensation is disabled
+3538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         1 -> 16393  Gain compensation is enabled with returned value
+3539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx)
+3541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ? READ_BIT(ADCx->GCOMP, ADC_G
+3543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_SMPR1_SMPPLUS)
+3546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC sampling time common configuration impacting
+3548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         settings of sampling time channel wise.
+3549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SMPR1    SMPPLUS        LL_ADC_SetSamplingTimeCommonConfig
+3554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SamplingTimeCommonConfig This parameter can be one of the following values:
+3556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
+3557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
+3558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCom
+3561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
+3563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/ccICigVb.s 			page 64
+
+
+3564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC sampling time common configuration impacting
+3567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         settings of sampling time channel wise.
+3568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SMPR1    SMPPLUS        LL_ADC_GetSamplingTimeCommonConfig
+3569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
+3572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
+3573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
+3575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
+3577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_SMPR1_SMPPLUS */
+3579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+3582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: gr
+3585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+3586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular conversion trigger source:
+3590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal (SW start) or from external peripheral (timer event,
+3591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         external interrupt line).
+3592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting trigger source to external trigger
+3593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         also set trigger polarity to rising edge
+3594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (default setting for compatibility with some ADC on other
+3595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         STM32 families having this setting set by HW default value).
+3596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         In case of need to modify trigger edge, use
+3597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         function @ref LL_ADC_REG_SetTriggerEdge().
+3598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Availability of parameters of trigger sources from timer
+3599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         depends on timers availability on the selected device.
+3600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+3604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n
+3605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource
+3606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  TriggerSource This parameter can be one of the following values:
+3608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+3609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+3610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+3611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1        (1)
+3612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2        (1)
+3613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+3614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+3615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1        (2)
+3616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2        (1)
+3617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3        (2)
+3618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+3619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1        (2)
+3620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4        (1)
+ARM GAS  /tmp/ccICigVb.s 			page 65
+
+
+3621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+3622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1        (2)
+3623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4        (1)
+3624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+3625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
+3626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+3627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+3628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1        (2)
+3629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+3630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
+3631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
+3632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
+3633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2       (1)
+3634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3       (1)
+3635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
+3636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2      (2)
+3637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
+3638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4      (2)
+3639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
+3640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
+3641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
+3642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
+3643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
+3644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
+3645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11     (1)
+3646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2      (2)
+3647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
+3648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+3649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+3650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+3651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             On this STM32 series, all ADCx are not available on all devices. Refer to device da
+3652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+3655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
+3657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion trigger source:
+3661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal (SW start) or from external peripheral (timer event,
+3662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         external interrupt line).
+3663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To determine whether group regular trigger source is
+3664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal (SW start) or external, without detail
+3665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of which peripheral is selected as external trigger,
+3666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (equivalent to
+3667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+3668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+3669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Availability of parameters of trigger sources from timer
+3670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         depends on timers availability on the selected device.
+3671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n
+3672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource
+3673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+3676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+3677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+ARM GAS  /tmp/ccICigVb.s 			page 66
+
+
+3678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1        (1)
+3679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2        (1)
+3680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+3681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+3682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1        (2)
+3683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2        (1)
+3684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3        (2)
+3685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+3686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1        (2)
+3687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4        (1)
+3688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+3689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1        (2)
+3690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4        (1)
+3691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+3692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
+3693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+3694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+3695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1        (2)
+3696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+3697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
+3698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
+3699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
+3700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2       (1)
+3701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3       (1)
+3702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
+3703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2      (2)
+3704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
+3705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4      (2)
+3706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
+3707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
+3708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
+3709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
+3710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
+3711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
+3712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11     (1)
+3713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2      (2)
+3714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
+3715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+3716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+3717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+3718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             On this STM32 series, all ADCx are not available on all devices. Refer to device da
+3719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+3721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
+3723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+3725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */
+3726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U
+3727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */
+3729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* to match with triggers literals definition.                              */
+3730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((TriggerSource
+3731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****            & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
+3732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****           | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
+3733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****          );
+3734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/ccICigVb.s 			page 67
+
+
+3735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion trigger source internal (SW start)
+3738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or external.
+3739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of group regular trigger source set to external trigger,
+3740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         to determine which peripheral is selected as external trigger,
+3741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_REG_GetTriggerSource().
+3742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
+3743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value "0" if trigger source external trigger
+3745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Value "1" if trigger source SW start.
+3746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+3748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1
+3750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular conversion trigger polarity.
+3754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Applicable only for trigger source set to external trigger.
+3755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+3759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge
+3760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ExternalTriggerEdge This parameter can be one of the following values:
+3762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+3763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+3764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+3765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+3768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
+3770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion trigger polarity.
+3774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Applicable only for trigger source set to external trigger.
+3775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge
+3776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+3779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+3780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+3781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
+3783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
+3785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC sampling mode.
+3789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function set the ADC conversion sampling mode
+3790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This mode applies to regular group only.
+3791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Set sampling mode is applied to all conversion of regular group.
+ARM GAS  /tmp/ccICigVb.s 			page 68
+
+
+3792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+3796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    BULB           LL_ADC_REG_SetSamplingMode\n
+3797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    SMPTRIG        LL_ADC_REG_SetSamplingMode
+3798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SamplingMode This parameter can be one of the following values:
+3800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+3801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+3802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+3803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
+3806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
+3808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get the ADC sampling mode
+3812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    BULB           LL_ADC_REG_GetSamplingMode\n
+3813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    SMPTRIG        LL_ADC_REG_GetSamplingMode
+3814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+3817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+3818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+3819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx)
+3821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
+3823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular sequencer length and scan direction.
+3827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Description of ADC group regular sequencer features:
+3828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - For devices with sequencer fully configurable
+3829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+3830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           sequencer length and each rank affectation to a channel
+3831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           are configurable.
+3832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This function performs configuration of:
+3833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence length: Number of ranks in the scan sequence.
+3834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence direction: Unless specified in parameters, sequencer
+3835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             scan direction is forward (from rank 1 to rank n).
+3836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Sequencer ranks are selected using
+3837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           function "LL_ADC_REG_SetSequencerRanks()".
+3838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - For devices with sequencer not fully configurable
+3839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+3840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           sequencer length and each rank affectation to a channel
+3841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           are defined by channel number.
+3842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This function performs configuration of:
+3843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence length: Number of ranks in the scan sequence is
+3844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             defined by number of channels set in the sequence,
+3845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             rank of each channel is fixed by channel HW number.
+3846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+3847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence direction: Unless specified in parameters, sequencer
+3848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             scan direction is forward (from lowest channel number to
+ARM GAS  /tmp/ccICigVb.s 			page 69
+
+
+3849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             highest channel number).
+3850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Sequencer ranks are selected using
+3851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           function "LL_ADC_REG_SetSequencerChannels()".
+3852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+3853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion on only 1 channel.
+3854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+3858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
+3859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SequencerNbRanks This parameter can be one of the following values:
+3861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+3862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+3863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+3864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+3865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+3866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+3867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+3868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+3869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+3870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+3871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+3872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+3873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+3874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+3875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+3876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+3877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+3880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+3882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular sequencer length and scan direction.
+3886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Description of ADC group regular sequencer features:
+3887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - For devices with sequencer fully configurable
+3888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+3889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           sequencer length and each rank affectation to a channel
+3890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           are configurable.
+3891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This function retrieves:
+3892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence length: Number of ranks in the scan sequence.
+3893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence direction: Unless specified in parameters, sequencer
+3894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             scan direction is forward (from rank 1 to rank n).
+3895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Sequencer ranks are selected using
+3896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           function "LL_ADC_REG_SetSequencerRanks()".
+3897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - For devices with sequencer not fully configurable
+3898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+3899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           sequencer length and each rank affectation to a channel
+3900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           are defined by channel number.
+3901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This function retrieves:
+3902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence length: Number of ranks in the scan sequence is
+3903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             defined by number of channels set in the sequence,
+3904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             rank of each channel is fixed by channel HW number.
+3905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ARM GAS  /tmp/ccICigVb.s 			page 70
+
+
+3906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence direction: Unless specified in parameters, sequencer
+3907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             scan direction is forward (from lowest channel number to
+3908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             highest channel number).
+3909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Sequencer ranks are selected using
+3910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           function "LL_ADC_REG_SetSequencerChannels()".
+3911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+3912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion on only 1 channel.
+3913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength
+3914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+3917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+3918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+3919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+3920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+3921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+3922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+3923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+3924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+3925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+3926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+3927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+3928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+3929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+3930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+3931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+3932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+3934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+3936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular sequencer discontinuous mode:
+3940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sequence subdivided and scan conversions interrupted every selected
+3941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number of ranks.
+3942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   It is not possible to enable both ADC group regular
+3943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         continuous mode and sequencer discontinuous mode.
+3944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   It is not possible to enable both ADC auto-injected mode
+3945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and ADC group regular sequencer discontinuous mode.
+3946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+3950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n
+3951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont
+3952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SeqDiscont This parameter can be one of the following values:
+3954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+3955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+3956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+3957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+3958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+3959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+3960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+3961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+3962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ARM GAS  /tmp/ccICigVb.s 			page 71
+
+
+3963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+3966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
+3968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular sequencer discontinuous mode:
+3972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sequence subdivided and scan conversions interrupted every selected
+3973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number of ranks.
+3974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n
+3975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont
+3976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+3979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+3980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+3981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+3982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+3983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+3984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+3985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+3986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+3987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+3989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
+3991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular sequence: channel on the selected
+3995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         scan sequence rank.
+3996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function performs configuration of:
+3997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Channels ordering into each rank of scan sequence:
+3998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           whatever channel can be placed into whatever rank.
+3999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, ADC group regular sequencer is
+4000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         fully configurable: sequencer length and each rank
+4001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         affectation to a channel are configurable.
+4002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+4003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Depending on devices and packages, some channels may not be available.
+4004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet for channels availability.
+4005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, to measure internal channels (VrefInt,
+4006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TempSensor, ...), measurement paths to internal channels must be
+4007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         enabled separately.
+4008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+4009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+4012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+4013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n
+4014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n
+4015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n
+4016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n
+4017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n
+4018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n
+4019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
+ARM GAS  /tmp/ccICigVb.s 			page 72
+
+
+4020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
+4021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
+4022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n
+4023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n
+4024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n
+4025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
+4026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
+4027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n
+4028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks
+4029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+4031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_1
+4032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_2
+4033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_3
+4034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_4
+4035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_5
+4036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_6
+4037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_7
+4038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_8
+4039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_9
+4040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_10
+4041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_11
+4042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_12
+4043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_13
+4044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_14
+4045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_15
+4046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_16
+4047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be one of the following values:
+4048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+4049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+4050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+4051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+4052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+4053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+4054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+4055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+4056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+4057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+4058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+4059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+4060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+4061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+4062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+4063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+4064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+4065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+4066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+4067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+4068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+4069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+4070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+4071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+4072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+4073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+4074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+4075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+4076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+ARM GAS  /tmp/ccICigVb.s 			page 73
+
+
+4077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+4078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+4079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+4080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+4081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+4082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+4083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+4084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+4085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+4086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+4087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+4088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+4089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channe
+4092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+  30              		.loc 2 4092 1 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		@ link register save eliminated.
+  35              		.loc 2 4092 1 is_stmt 0 view .LVU1
+  36 0000 10B4     		push	{r4}
+  37              	.LCFI0:
+  38              		.cfi_def_cfa_offset 4
+  39              		.cfi_offset 4, -4
+4093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "Channel" with bits position          */
+4094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* in register and register position depending on parameter "Rank".         */
+4095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameters "Rank" and "Channel" are used with masks because containing   */
+4096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* other bits reserved for other purpose.                                   */
+4097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> A
+  40              		.loc 2 4097 3 is_stmt 1 view .LVU2
+  41              		.loc 2 4097 25 is_stmt 0 view .LVU3
+  42 0002 3030     		adds	r0, r0, #48
+  43              	.LVL1:
+  44              		.loc 2 4097 25 view .LVU4
+  45 0004 0B0A     		lsrs	r3, r1, #8
+  46 0006 9B00     		lsls	r3, r3, #2
+  47 0008 03F00C03 		and	r3, r3, #12
+  48              	.LVL2:
+4098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+  49              		.loc 2 4099 3 is_stmt 1 view .LVU5
+  50 000c C458     		ldr	r4, [r0, r3]
+  51 000e 01F01F01 		and	r1, r1, #31
+  52              	.LVL3:
+  53              		.loc 2 4099 3 is_stmt 0 view .LVU6
+  54 0012 4FF01F0C 		mov	ip, #31
+  55 0016 0CFA01FC 		lsl	ip, ip, r1
+  56 001a 24EA0C0C 		bic	ip, r4, ip
+  57 001e C2F38462 		ubfx	r2, r2, #26, #5
+  58              	.LVL4:
+  59              		.loc 2 4099 3 view .LVU7
+  60 0022 8A40     		lsls	r2, r2, r1
+  61 0024 4CEA0202 		orr	r2, ip, r2
+  62 0028 C250     		str	r2, [r0, r3]
+4100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+ARM GAS  /tmp/ccICigVb.s 			page 74
+
+
+4101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Ra
+4102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+  63              		.loc 2 4102 1 view .LVU8
+  64 002a 5DF8044B 		ldr	r4, [sp], #4
+  65              	.LCFI1:
+  66              		.cfi_restore 4
+  67              		.cfi_def_cfa_offset 0
+  68 002e 7047     		bx	lr
+  69              		.cfi_endproc
+  70              	.LFE171:
+  72              		.section	.text.LL_ADC_SetChannelSamplingTime,"ax",%progbits
+  73              		.align	1
+  74              		.syntax unified
+  75              		.thumb
+  76              		.thumb_func
+  78              	LL_ADC_SetChannelSamplingTime:
+  79              	.LVL5:
+  80              	.LFB195:
+4103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular sequence: channel on the selected
+4106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         scan sequence rank.
+4107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, ADC group regular sequencer is
+4108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         fully configurable: sequencer length and each rank
+4109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         affectation to a channel are configurable.
+4110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+4111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Depending on devices and packages, some channels may not be available.
+4112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet for channels availability.
+4113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Usage of the returned channel number:
+4114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To reinject this channel into another function LL_ADC_xxx:
+4115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the returned channel number is only partly formatted on definition
+4116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+4117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           with parts of literals LL_ADC_CHANNEL_x or using
+4118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+4119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Then the selected literal LL_ADC_CHANNEL_x can be used
+4120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           as parameter for another function.
+4121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To get the channel number in decimal format:
+4122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           process the returned value with the helper macro
+4123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+4124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n
+4125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n
+4126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n
+4127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n
+4128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n
+4129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n
+4130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
+4131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
+4132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
+4133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n
+4134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n
+4135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n
+4136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
+4137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
+4138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n
+4139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks
+4140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+ARM GAS  /tmp/ccICigVb.s 			page 75
+
+
+4142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_1
+4143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_2
+4144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_3
+4145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_4
+4146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_5
+4147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_6
+4148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_7
+4149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_8
+4150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_9
+4151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_10
+4152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_11
+4153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_12
+4154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_13
+4155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_14
+4156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_15
+4157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_16
+4158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+4160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+4161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+4162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+4163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+4164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+4165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+4166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+4167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+4168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+4169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+4170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+4171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+4172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+4173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+4174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+4175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+4176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+4177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+4178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+4179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+4180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+4181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+4182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+4183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+4184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+4185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+4186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+4187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+4188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+4189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+4190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+4191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+4192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+4193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+4194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+4195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+4196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+4197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+4198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+ARM GAS  /tmp/ccICigVb.s 			page 76
+
+
+4199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+4200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+4201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      comparison with internal channel parameter to be done
+4202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+4203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+4205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK
+4207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)((READ_BIT(*preg,
+4209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                               ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MA
+4210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+4211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                    );
+4212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC continuous conversion mode on ADC group regular.
+4216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Description of ADC continuous conversion mode:
+4217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - single mode: one conversion per trigger
+4218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - continuous mode: after the first trigger, following
+4219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           conversions launched successively automatically.
+4220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   It is not possible to enable both ADC group regular
+4221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         continuous mode and sequencer discontinuous mode.
+4222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+4225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+4226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode
+4227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Continuous This parameter can be one of the following values:
+4229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_CONV_SINGLE
+4230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+4231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+4234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
+4236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC continuous conversion mode on ADC group regular.
+4240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Description of ADC continuous conversion mode:
+4241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - single mode: one conversion per trigger
+4242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - continuous mode: after the first trigger, following
+4243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           conversions launched successively automatically.
+4244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode
+4245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_CONV_SINGLE
+4248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+4249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+4251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
+4253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 77
+
+
+4256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular conversion data transfer: no transfer or
+4257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         transfer by DMA, and DMA requests mode.
+4258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If transfer by DMA selected, specifies the DMA requests
+4259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         mode:
+4260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Limited mode (One shot mode): DMA transfer requests are stopped
+4261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           when number of DMA data transfers (number of
+4262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions) is reached.
+4263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode non-circular.
+4264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Unlimited mode: DMA transfer requests are unlimited,
+4265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           whatever number of DMA data transfers (number of
+4266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions).
+4267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode circular.
+4268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+4269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         mode non-circular:
+4270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         when DMA transfers size will be reached, DMA will stop transfers of
+4271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversions data ADC will raise an overrun error
+4272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *        (overrun flag and interruption if enabled).
+4273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with several ADC instances: ADC multimode DMA
+4274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().
+4275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To configure DMA source address (peripheral address),
+4276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_DMA_GetRegAddr().
+4277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+4280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+4281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     DMAEN          LL_ADC_REG_SetDMATransfer\n
+4282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     DMACFG         LL_ADC_REG_SetDMATransfer
+4283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  DMATransfer This parameter can be one of the following values:
+4285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+4286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+4287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+4288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+4291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
+4293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion data transfer: no transfer or
+4297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         transfer by DMA, and DMA requests mode.
+4298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If transfer by DMA selected, specifies the DMA requests
+4299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         mode:
+4300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Limited mode (One shot mode): DMA transfer requests are stopped
+4301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           when number of DMA data transfers (number of
+4302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions) is reached.
+4303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode non-circular.
+4304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Unlimited mode: DMA transfer requests are unlimited,
+4305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           whatever number of DMA data transfers (number of
+4306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions).
+4307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode circular.
+4308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+4309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         mode non-circular:
+4310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         when DMA transfers size will be reached, DMA will stop transfers of
+4311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversions data ADC will raise an overrun error
+4312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (overrun flag and interruption if enabled).
+ARM GAS  /tmp/ccICigVb.s 			page 78
+
+
+4313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with several ADC instances: ADC multimode DMA
+4314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().
+4315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To configure DMA source address (peripheral address),
+4316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_DMA_GetRegAddr().
+4317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     DMAEN          LL_ADC_REG_GetDMATransfer\n
+4318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     DMACFG         LL_ADC_REG_GetDMATransfer
+4319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+4322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+4323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+4324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+4326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
+4328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular behavior in case of overrun:
+4332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         data preserved or overwritten.
+4333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Compatibility with devices without feature overrun:
+4334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         other devices without this feature have a behavior
+4335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         equivalent to data overwritten.
+4336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         The default setting of overrun is data preserved.
+4337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Therefore, for compatibility with all devices, parameter
+4338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         overrun should be set to data overwritten.
+4339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+4342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+4343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun
+4344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Overrun This parameter can be one of the following values:
+4346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+4347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+4348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
+4351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
+4353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular behavior in case of overrun:
+4357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         data preserved or overwritten.
+4358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun
+4359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+4362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+4363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
+4365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
+4367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 79
+
+
+4370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+4371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: g
+4374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+4375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected conversion trigger source:
+4379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal (SW start) or from external peripheral (timer event,
+4380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         external interrupt line).
+4381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting trigger source to external trigger
+4382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         also set trigger polarity to rising edge
+4383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (default setting for compatibility with some ADC on other
+4384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         STM32 families having this setting set by HW default value).
+4385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         In case of need to modify trigger edge, use
+4386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         function @ref LL_ADC_INJ_SetTriggerEdge().
+4387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Availability of parameters of trigger sources from timer
+4388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         depends on timers availability on the selected device.
+4389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must not be disabled. Can be enabled with or without conversion
+4392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on going on either groups regular or injected.
+4393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
+4394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource
+4395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  TriggerSource This parameter can be one of the following values:
+4397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+4398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+4399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+4400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
+4401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+4402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+4403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
+4404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+4405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
+4406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
+4407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
+4408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+4409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
+4410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
+4411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+4412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+4413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+4414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+4415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
+4416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+4417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+4418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
+4419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+4420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+4421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
+4422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
+4423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
+4424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+4425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
+4426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+ARM GAS  /tmp/ccICigVb.s 			page 80
+
+
+4427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+4428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+4429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+4430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+4431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+4432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+4433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
+4434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
+4435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+4436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+4437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+4438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+4439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             On this STM32 series, all ADCx are not available on all devices. Refer to device da
+4440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+4443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
+4445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion trigger source:
+4449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal (SW start) or from external peripheral (timer event,
+4450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         external interrupt line).
+4451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To determine whether group injected trigger source is
+4452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal (SW start) or external, without detail
+4453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of which peripheral is selected as external trigger,
+4454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (equivalent to
+4455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+4456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+4457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Availability of parameters of trigger sources from timer
+4458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         depends on timers availability on the selected device.
+4459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
+4460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource
+4461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+4464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+4465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+4466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
+4467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+4468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+4469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
+4470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+4471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
+4472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
+4473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
+4474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+4475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
+4476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
+4477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+4478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+4479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+4480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+4481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
+4482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+4483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ARM GAS  /tmp/ccICigVb.s 			page 81
+
+
+4484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
+4485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+4486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+4487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
+4488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
+4489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
+4490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+4491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
+4492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+4493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+4494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+4495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+4496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+4497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+4498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+4499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
+4500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
+4501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+4502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+4503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+4504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+4505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             On this STM32 series, all ADCx are not available on all devices. Refer to device da
+4506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+4508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+4510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+4512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
+4513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 
+4514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
+4516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* to match with triggers literals definition.                              */
+4517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((TriggerSource
+4518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****            & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
+4519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****           | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
+4520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****          );
+4521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion trigger source internal (SW start)
+4525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             or external
+4526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of group injected trigger source set to external trigger,
+4527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         to determine which peripheral is selected as external trigger,
+4528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_INJ_GetTriggerSource.
+4529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
+4530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value "0" if trigger source external trigger
+4532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Value "1" if trigger source SW start.
+4533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+4535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ?
+4537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected conversion trigger polarity.
+ARM GAS  /tmp/ccICigVb.s 			page 82
+
+
+4541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Applicable only for trigger source set to external trigger.
+4542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must not be disabled. Can be enabled with or without conversion
+4545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on going on either groups regular or injected.
+4546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge
+4547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ExternalTriggerEdge This parameter can be one of the following values:
+4549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+4550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+4551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+4552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+4555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
+4557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion trigger polarity.
+4561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Applicable only for trigger source set to external trigger.
+4562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge
+4563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+4566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+4567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+4568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
+4570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
+4572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected sequencer length and scan direction.
+4576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function performs configuration of:
+4577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Sequence length: Number of ranks in the scan sequence.
+4578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Sequence direction: Unless specified in parameters, sequencer
+4579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           scan direction is forward (from rank 1 to rank n).
+4580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+4581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion on only 1 channel.
+4582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must not be disabled. Can be enabled with or without conversion
+4585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on going on either groups regular or injected.
+4586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
+4587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SequencerNbRanks This parameter can be one of the following values:
+4589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+4590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+4591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+4592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+4593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+4596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+ARM GAS  /tmp/ccICigVb.s 			page 83
+
+
+4598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected sequencer length and scan direction.
+4602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function retrieves:
+4603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Sequence length: Number of ranks in the scan sequence.
+4604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Sequence direction: Unless specified in parameters, sequencer
+4605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           scan direction is forward (from rank 1 to rank n).
+4606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+4607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion on only 1 channel.
+4608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
+4609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+4612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+4613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+4614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+4615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+4617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+4619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected sequencer discontinuous mode:
+4623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sequence subdivided and scan conversions interrupted every selected
+4624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number of ranks.
+4625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   It is not possible to enable both ADC group injected
+4626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         auto-injected mode and sequencer discontinuous mode.
+4627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont
+4628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SeqDiscont This parameter can be one of the following values:
+4630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+4631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+4632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+4635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
+4637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected sequencer discontinuous mode:
+4641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sequence subdivided and scan conversions interrupted every selected
+4642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number of ranks.
+4643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont
+4644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+4647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+4648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+4650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
+4652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 84
+
+
+4655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected sequence: channel on the selected
+4656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sequence rank.
+4657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Depending on devices and packages, some channels may not be available.
+4658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet for channels availability.
+4659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, to measure internal channels (VrefInt,
+4660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TempSensor, ...), measurement paths to internal channels must be
+4661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         enabled separately.
+4662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+4663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On STM32G4, some fast channels are available: fast analog inputs
+4664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         coming from GPIO pads (ADC_IN1..5).
+4665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must not be disabled. Can be enabled with or without conversion
+4668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on going on either groups regular or injected.
+4669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
+4670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
+4671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
+4672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
+4673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+4675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_1
+4676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_2
+4677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_3
+4678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_4
+4679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be one of the following values:
+4680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+4681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+4682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+4683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+4684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+4685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+4686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+4687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+4688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+4689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+4690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+4691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+4692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+4693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+4694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+4695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+4696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+4697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+4698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+4699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+4700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+4701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+4702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+4703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+4704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+4705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+4706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+4707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+4708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+4709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+4710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+4711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+ARM GAS  /tmp/ccICigVb.s 			page 85
+
+
+4712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+4713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+4714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+4715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+4716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+4717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+4718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+4719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+4720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+4721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channe
+4724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "Channel" with bits position          */
+4726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* in register depending on parameter "Rank".                               */
+4727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameters "Rank" and "Channel" are used with masks because containing   */
+4728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* other bits reserved for other purpose.                                   */
+4729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->JSQR,
+4730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ
+4731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Ra
+4732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected sequence: channel on the selected
+4736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sequence rank.
+4737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Depending on devices and packages, some channels may not be available.
+4738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet for channels availability.
+4739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Usage of the returned channel number:
+4740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To reinject this channel into another function LL_ADC_xxx:
+4741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the returned channel number is only partly formatted on definition
+4742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+4743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           with parts of literals LL_ADC_CHANNEL_x or using
+4744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+4745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Then the selected literal LL_ADC_CHANNEL_x can be used
+4746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           as parameter for another function.
+4747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To get the channel number in decimal format:
+4748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           process the returned value with the helper macro
+4749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+4750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n
+4751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n
+4752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n
+4753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks
+4754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+4756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_1
+4757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_2
+4758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_3
+4759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_4
+4760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+4762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+4763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+4764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+4765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+4766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+4767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+4768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+ARM GAS  /tmp/ccICigVb.s 			page 86
+
+
+4769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+4770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+4771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+4772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+4773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+4774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+4775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+4776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+4777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+4778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+4779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+4780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+4781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+4782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+4783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+4784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+4785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+4786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+4787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+4788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+4789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+4790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+4791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+4792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+4793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+4794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+4795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+4796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+4797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+4798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+4799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+4800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+4801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+4802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+4803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      comparison with internal channel parameter to be done
+4804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+4805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+4807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)((READ_BIT(ADCx->JSQR,
+4809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                               (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) <
+4810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                      >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+4811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                    );
+4812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected conversion trigger:
+4816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         independent or from ADC group regular.
+4817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This mode can be used to extend number of data registers
+4818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         updated after one ADC conversion trigger and with data
+4819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         permanently kept (not erased by successive conversions of scan of
+4820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC sequencer ranks), up to 5 data registers:
+4821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         1 data register on ADC group regular, 4 data registers
+4822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on ADC group injected.
+4823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC group injected injected trigger source is set to an
+4824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         external trigger, this feature must be must be set to
+4825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         independent trigger.
+ARM GAS  /tmp/ccICigVb.s 			page 87
+
+
+4826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC group injected automatic trigger is compliant only with
+4827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         group injected trigger source set to SW start, without any
+4828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         further action on  ADC group injected conversion start or stop:
+4829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         in this case, ADC group injected is controlled only
+4830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from ADC group regular.
+4831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   It is not possible to enable both ADC group injected
+4832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         auto-injected mode and sequencer discontinuous mode.
+4833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+4836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+4837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto
+4838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  TrigAuto This parameter can be one of the following values:
+4840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+4841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+4842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+4845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
+4847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion trigger:
+4851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         independent or from ADC group regular.
+4852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto
+4853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+4856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+4857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+4859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
+4861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected contexts queue mode.
+4865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   A context is a setting of group injected sequencer:
+4866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - group injected trigger
+4867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - sequencer length
+4868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - sequencer ranks
+4869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         If contexts queue is disabled:
+4870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - only 1 sequence can be configured
+4871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           and is active perpetually.
+4872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         If contexts queue is enabled:
+4873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - up to 2 contexts can be queued
+4874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           and are checked in and out as a FIFO stack (first-in, first-out).
+4875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - If a new context is set when queues is full, error is triggered
+4876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           by interruption "Injected Queue Overflow".
+4877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Two behaviors are possible when all contexts have been processed:
+4878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the contexts queue can maintain the last context active perpetually
+4879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           or can be empty and injected group triggers are disabled.
+4880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Triggers can be only external (not internal SW start)
+4881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Caution: The sequence must be fully configured in one time
+4882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (one write of register JSQR makes a check-in of a new context
+ARM GAS  /tmp/ccICigVb.s 			page 88
+
+
+4883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           into the queue).
+4884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Therefore functions to set separately injected trigger and
+4885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           sequencer channels cannot be used, register JSQR must be set
+4886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           using function @ref LL_ADC_INJ_ConfigQueueContext().
+4887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This parameter can be modified only when no conversion is on going
+4888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+4889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   A modification of the context mode (bit JQDIS) causes the contexts
+4890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         queue to be flushed and the register JSQR is cleared.
+4891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+4894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+4895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n
+4896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode
+4897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  QueueMode This parameter can be one of the following values:
+4899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+4900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+4901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+4902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
+4905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
+4907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected context queue mode.
+4911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n
+4912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode
+4913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+4916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+4917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+4918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
+4920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
+4922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set one context on ADC group injected that will be checked in
+4926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         contexts queue.
+4927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   A context is a setting of group injected sequencer:
+4928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - group injected trigger
+4929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - sequencer length
+4930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - sequencer ranks
+4931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This function is intended to be used when contexts queue is enabled,
+4932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         because the sequence must be fully configured in one time
+4933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (functions to set separately injected trigger and sequencer channels
+4934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         cannot be used):
+4935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to function @ref LL_ADC_INJ_SetQueueMode().
+4936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In the contexts queue, only the active context can be read.
+4937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         The parameters of this function can be read using functions:
+4938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_GetTriggerSource()
+4939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_GetTriggerEdge()
+ARM GAS  /tmp/ccICigVb.s 			page 89
+
+
+4940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_GetSequencerRanks()
+4941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, to measure internal channels (VrefInt,
+4942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TempSensor, ...), measurement paths to internal channels must be
+4943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         enabled separately.
+4944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+4945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On STM32G4, some fast channels are available: fast analog inputs
+4946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         coming from GPIO pads (ADC_IN1..5).
+4947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must not be disabled. Can be enabled with or without conversion
+4950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on going on either groups regular or injected.
+4951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n
+4952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n
+4953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n
+4954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n
+4955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n
+4956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n
+4957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext
+4958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  TriggerSource This parameter can be one of the following values:
+4960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+4961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+4962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+4963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
+4964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+4965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+4966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
+4967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+4968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
+4969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
+4970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
+4971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+4972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
+4973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
+4974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+4975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+4976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+4977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+4978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
+4979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+4980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+4981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
+4982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+4983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+4984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
+4985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
+4986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
+4987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+4988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
+4989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+4990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+4991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+4992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+4993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+4994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+4995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+4996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
+ARM GAS  /tmp/ccICigVb.s 			page 90
+
+
+4997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
+4998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+4999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+5001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+5002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ExternalTriggerEdge This parameter can be one of the following values:
+5004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+5005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+5006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+5007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Note: This parameter is discarded in case of SW start:
+5009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
+5010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SequencerNbRanks This parameter can be one of the following values:
+5011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+5012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+5013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+5014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+5015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank1_Channel This parameter can be one of the following values:
+5016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+5017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+5018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+5019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+5020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+5021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+5022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+5033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+5034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+5035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+5036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+5037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+5038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+5039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+5040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+5041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+5042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+5043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+5044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+5045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+5046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+ARM GAS  /tmp/ccICigVb.s 			page 91
+
+
+5054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+5056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+5057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank2_Channel This parameter can be one of the following values:
+5058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+5059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+5060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+5061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+5062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+5063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+5064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+5075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+5076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+5077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+5078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+5079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+5080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+5081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+5082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+5083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+5084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+5085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+5086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+5087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+5088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+5098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+5099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank3_Channel This parameter can be one of the following values:
+5100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+5101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+5102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+5103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+5104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+5105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+5106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+ARM GAS  /tmp/ccICigVb.s 			page 92
+
+
+5111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+5117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+5118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+5119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+5120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+5121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+5122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+5123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+5124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+5125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+5126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+5127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+5128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+5129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+5130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+5140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+5141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank4_Channel This parameter can be one of the following values:
+5142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+5143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+5144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+5145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+5146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+5147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+5148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+5159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+5160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+5161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+5162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+5163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+5164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+5165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+5166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+5167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+ARM GAS  /tmp/ccICigVb.s 			page 93
+
+
+5168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+5169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+5170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+5171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+5172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+5182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+5183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+5184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
+5186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t TriggerSource,
+5187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t ExternalTriggerEdge,
+5188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t SequencerNbRanks,
+5189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t Rank1_Channel,
+5190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t Rank2_Channel,
+5191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t Rank3_Channel,
+5192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t Rank4_Channel)
+5193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "Rankx_Channel" with bits position    */
+5195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */
+5196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */
+5197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* because containing other bits reserved for other purpose.                */
+5198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* If parameter "TriggerSource" is set to SW start, then parameter          */
+5199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* "ExternalTriggerEdge" is discarded.                                      */
+5200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
+5201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->JSQR,
+5202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JEXTSEL |
+5203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JEXTEN  |
+5204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JSQ4    |
+5205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JSQ3    |
+5206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JSQ2    |
+5207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JSQ1    |
+5208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JL,
+5209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (TriggerSource & ADC_JSQR_JEXTSEL)          |
+5210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (ExternalTriggerEdge * (is_trigger_not_sw)) |
+5211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+5212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+5213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+5214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+5215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              SequencerNbRanks
+5216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             );
+5217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+5218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+5221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+5224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ARM GAS  /tmp/ccICigVb.s 			page 94
+
+
+5225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set sampling time of the selected ADC channel
+5229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Unit: ADC clock cycles.
+5230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this device, sampling time is on channel scope: independently
+5231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of channel mapped on ADC group regular or injected.
+5232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
+5233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         converted:
+5234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sampling time constraints must be respected (sampling time can be
+5235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         adjusted in function of ADC clock frequency and sampling time
+5236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         setting).
+5237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet for timings values (parameters TS_vrefint,
+5238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TS_temp, ...).
+5239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Conversion time is the addition of sampling time and processing time.
+5240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         On this STM32 series, ADC processing time is:
+5241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
+5242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
+5243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+5244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+5245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of ADC conversion of internal channel (VrefInt,
+5246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         temperature sensor, ...), a sampling time minimum value
+5247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is required.
+5248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet.
+5249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+5250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+5251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+5252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+5253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n
+5254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n
+5255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n
+5256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n
+5257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n
+5258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n
+5259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n
+5260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n
+5261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n
+5262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n
+5263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
+5264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
+5265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
+5266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
+5267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
+5268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
+5269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
+5270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
+5271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime
+5272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be one of the following values:
+5274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+5275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+5276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+5277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+5278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+5279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+5280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+ARM GAS  /tmp/ccICigVb.s 			page 95
+
+
+5282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+5291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+5292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+5293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+5294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+5295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+5296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+5297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+5298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+5299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+5300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+5301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+5302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+5303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+5304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+5314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+5315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SamplingTime This parameter can be one of the following values:
+5316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)
+5317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+5318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+5319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
+5320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
+5321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
+5322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
+5323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
+5324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles
+5326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             can be replaced by 3.5 ADC clock cycles.
+5327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
+5328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+5329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t Sa
+5331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+  81              		.loc 2 5331 1 is_stmt 1 view -0
+  82              		.cfi_startproc
+  83              		@ args = 0, pretend = 0, frame = 0
+  84              		@ frame_needed = 0, uses_anonymous_args = 0
+  85              		@ link register save eliminated.
+  86              		.loc 2 5331 1 is_stmt 0 view .LVU10
+  87 0000 10B4     		push	{r4}
+ARM GAS  /tmp/ccICigVb.s 			page 96
+
+
+  88              	.LCFI2:
+  89              		.cfi_def_cfa_offset 4
+  90              		.cfi_offset 4, -4
+5332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "SamplingTime" with bits position     */
+5333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* in register and register position depending on parameter "Channel".      */
+5334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameter "Channel" is used with masks because containing                */
+5335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* other bits reserved for other purpose.                                   */
+5336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_M
+  91              		.loc 2 5336 3 is_stmt 1 view .LVU11
+  92              		.loc 2 5336 25 is_stmt 0 view .LVU12
+  93 0002 1430     		adds	r0, r0, #20
+  94              	.LVL6:
+  95              		.loc 2 5336 25 view .LVU13
+  96 0004 4B0E     		lsrs	r3, r1, #25
+  97 0006 9B00     		lsls	r3, r3, #2
+  98 0008 03F00403 		and	r3, r3, #4
+  99              	.LVL7:
+5337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+ 100              		.loc 2 5338 3 is_stmt 1 view .LVU14
+ 101 000c C458     		ldr	r4, [r0, r3]
+ 102 000e C1F30451 		ubfx	r1, r1, #20, #5
+ 103              	.LVL8:
+ 104              		.loc 2 5338 3 is_stmt 0 view .LVU15
+ 105 0012 4FF0070C 		mov	ip, #7
+ 106 0016 0CFA01FC 		lsl	ip, ip, r1
+ 107 001a 24EA0C0C 		bic	ip, r4, ip
+ 108 001e 8A40     		lsls	r2, r2, r1
+ 109              	.LVL9:
+ 110              		.loc 2 5338 3 view .LVU16
+ 111 0020 4CEA0202 		orr	r2, ip, r2
+ 112 0024 C250     		str	r2, [r0, r3]
+5339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BIT
+5340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BIT
+5341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 113              		.loc 2 5341 1 view .LVU17
+ 114 0026 5DF8044B 		ldr	r4, [sp], #4
+ 115              	.LCFI3:
+ 116              		.cfi_restore 4
+ 117              		.cfi_def_cfa_offset 0
+ 118 002a 7047     		bx	lr
+ 119              		.cfi_endproc
+ 120              	.LFE195:
+ 122              		.section	.text.LL_ADC_SetAnalogWDMonitChannels,"ax",%progbits
+ 123              		.align	1
+ 124              		.syntax unified
+ 125              		.thumb
+ 126              		.thumb_func
+ 128              	LL_ADC_SetAnalogWDMonitChannels:
+ 129              	.LVL10:
+ 130              	.LFB199:
+5342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get sampling time of the selected ADC channel
+5345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Unit: ADC clock cycles.
+5346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this device, sampling time is on channel scope: independently
+5347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of channel mapped on ADC group regular or injected.
+ARM GAS  /tmp/ccICigVb.s 			page 97
+
+
+5348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Conversion time is the addition of sampling time and processing time.
+5349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         On this STM32 series, ADC processing time is:
+5350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
+5351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
+5352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+5353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+5354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n
+5355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n
+5356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n
+5357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n
+5358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n
+5359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n
+5360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n
+5361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n
+5362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n
+5363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n
+5364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
+5365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
+5366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
+5367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
+5368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
+5369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
+5370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
+5371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
+5372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime
+5373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be one of the following values:
+5375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+5376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+5377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+5378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+5379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+5380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+5381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+5392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+5393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+5394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+5395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+5396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+5397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+5398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+5399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+5400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+5401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+5402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+5403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+5404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+ARM GAS  /tmp/ccICigVb.s 			page 98
+
+
+5405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+5415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+5416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+5417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)
+5418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+5419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+5420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
+5421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
+5422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
+5423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
+5424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
+5425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles
+5427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             can be replaced by 3.5 ADC clock cycles.
+5428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
+5429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+5431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOF
+5433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(*preg,
+5435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_
+5436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                     >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_P
+5437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                    );
+5438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+5439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set mode single-ended or differential input of the selected
+5442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC channel.
+5443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Channel ending is on channel scope: independently of channel mapped
+5444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on ADC group regular or injected.
+5445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         In differential mode: Differential measurement is carried out
+5446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         between the selected channel 'i' (positive input) and
+5447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         channel 'i+1' (negative input). Only channel 'i' has to be
+5448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         configured, channel 'i+1' is configured automatically.
+5449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Refer to Reference Manual to ensure the selected channel is
+5450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         available in differential mode.
+5451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         For example, internal channels (VrefInt, TempSensor, ...) are
+5452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         not available in differential mode.
+5453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   When configuring a channel 'i' in differential mode,
+5454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the channel 'i+1' is not usable separately.
+5455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On STM32G4, some channels are internally fixed to single-ended inputs
+5456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         configuration:
+5457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC1: Channels 12, 15, 16, 17 and 18
+5458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC2: Channels 15, 17 and 18
+5459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC3: Channels 12, 16, 17 and 18            (1)
+5460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC4: Channels 16, 17 and 18                (1)
+5461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC5: Channels 2, 3, 4, 16, 17 and 18       (1)
+ARM GAS  /tmp/ccICigVb.s 			page 99
+
+
+5462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) ADC3/4/5 are not available on all devices, refer to device datasheet
+5463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             for more details.
+5464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For ADC channels configured in differential mode, both inputs
+5465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         should be biased at (Vref+)/2 +/-200mV.
+5466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (Vref+ is the analog voltage reference)
+5467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+5468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+5469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled.
+5470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   One or several values can be selected.
+5471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+5472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DIFSEL   DIFSEL         LL_ADC_SetChannelSingleDiff
+5473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be one of the following values:
+5475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1
+5476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2
+5477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3
+5478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4
+5479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5
+5480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SingleDiff This parameter can be a combination of the following values:
+5491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SINGLE_ENDED
+5492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+5493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+5494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t Sing
+5496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Bits for single or differential mode selection for each channel are set  */
+5498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* to 1 only when the differential mode is selected, and to 0 when the      */
+5499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* single mode is selected.                                                 */
+5500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   
+5501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   if (SingleDiff == LL_ADC_DIFFERENTIAL_ENDED)
+5502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+5503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     SET_BIT(ADCx->DIFSEL,
+5504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+5505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   }
+5506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   else
+5507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+5508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     CLEAR_BIT(ADCx->DIFSEL,
+5509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+5510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   }
+5511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+5512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get mode single-ended or differential input of the selected
+5515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC channel.
+5516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   When configuring a channel 'i' in differential mode,
+5517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the channel 'i+1' is not usable separately.
+5518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Therefore, to ensure a channel is configured in single-ended mode,
+ARM GAS  /tmp/ccICigVb.s 			page 100
+
+
+5519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the configuration of channel itself and the channel 'i-1' must be
+5520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         read back (to ensure that the selected channel channel has not been
+5521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         configured in differential mode by the previous channel).
+5522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Refer to Reference Manual to ensure the selected channel is
+5523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         available in differential mode.
+5524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         For example, internal channels (VrefInt, TempSensor, ...) are
+5525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         not available in differential mode.
+5526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   When configuring a channel 'i' in differential mode,
+5527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the channel 'i+1' is not usable separately.
+5528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On STM32G4, some channels are internally fixed to single-ended inputs
+5529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         configuration:
+5530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC1: Channels 12, 15, 16, 17 and 18
+5531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC2: Channels 15, 17 and 18
+5532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC3: Channels 12, 16, 17 and 18            (1)
+5533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC4: Channels 16, 17 and 18                (1)
+5534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC5: Channels 2, 3, 4, 16, 17 and 18       (1)
+5535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) ADC3/4/5 are not available on all devices, refer to device datasheet
+5536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             for more details.
+5537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   One or several values can be selected. In this case, the value
+5538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         returned is null if all channels are in single ended-mode.
+5539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+5540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSingleDiff
+5541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be a combination of the following values:
+5543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1
+5544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2
+5545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3
+5546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4
+5547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5
+5548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: channel in single-ended mode, else: channel in differential mode
+5559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
+5561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
+5563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+5564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+5567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: an
+5570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+5571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC analog watchdog monitored channels:
+5575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a single channel, multiple channels or all channels,
+ARM GAS  /tmp/ccICigVb.s 			page 101
+
+
+5576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on ADC groups regular and-or injected.
+5577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Once monitored channels are selected, analog watchdog
+5578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is enabled.
+5579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of need to define a single channel to monitor
+5580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         with analog watchdog from sequencer channel definition,
+5581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+5582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, there are 2 kinds of analog watchdog
+5583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         instance:
+5584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD standard (instance AWD1):
+5585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: can monitor 1 channel or all channels.
+5586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: ADC groups regular and-or injected.
+5587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is not limited (corresponds to
+5588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC resolution configured).
+5589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD flexible (instances AWD2, AWD3):
+5590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: flexible on channels monitored, selection is
+5591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             channel wise, from from 1 to all channels.
+5592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Specificity of this analog watchdog: Multiple channels can
+5593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             be selected. For example:
+5594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+5595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: not selection possible (monitoring on both
+5596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             groups regular and injected).
+5597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Channels selected are monitored on groups regular and injected:
+5598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+5599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+5600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+5601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+5602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             the 2 LSB are ignored.
+5603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+5604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+5605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+5606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+5607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
+5608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
+5609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
+5610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n
+5611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
+5612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
+5613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+5615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+5616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD2
+5617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD3
+5618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDChannelGroup This parameter can be one of the following values:
+5619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_DISABLE
+5620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+5621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+5622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+5623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+5624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+5625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+5626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+5627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+5628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+5629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+5630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+5631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+5632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+ARM GAS  /tmp/ccICigVb.s 			page 102
+
+
+5633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+5634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+5635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+5636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+5637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+5638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+5639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+5640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+5641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+5642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+5643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+5644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+5645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+5646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+5647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+5648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+5649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+5650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+5651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+5652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+5653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+5654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+5655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+5656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+5657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+5658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+5659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+5660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+5661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+5662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+5663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+5664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+5665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+5666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+5667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+5668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+5669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+5670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+5671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+5672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+5673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+5674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+5675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+5676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+5677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+5678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+5679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+5680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
+5681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
+5682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+5683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG  (0)(1)
+5684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ  (0)(1)
+5685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
+5686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG  (0)(5)
+5687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ  (0)(5)
+5688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
+5689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(6)
+ARM GAS  /tmp/ccICigVb.s 			page 103
+
+
+5690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(6)
+5691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (6)
+5692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (0)(1)
+5693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (0)(1)
+5694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ         (1)
+5695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (0)(2)
+5696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (0)(2)
+5697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ         (2)
+5698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     (0)(2)
+5699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     (0)(2)
+5700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ    (2)
+5701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     (0)(3)
+5702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     (0)(3)
+5703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ    (3)
+5704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG          (0)(5)
+5705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ          (0)(5)
+5706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ         (5)
+5707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG          (0)(5)
+5708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ          (0)(5)
+5709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ         (5)
+5710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG          (0)(4)
+5711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ          (0)(4)
+5712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ         (4)
+5713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
+5715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+5724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWD
+5726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 131              		.loc 2 5726 1 is_stmt 1 view -0
+ 132              		.cfi_startproc
+ 133              		@ args = 0, pretend = 0, frame = 0
+ 134              		@ frame_needed = 0, uses_anonymous_args = 0
+ 135              		.loc 2 5726 1 is_stmt 0 view .LVU19
+ 136 0000 00B5     		push	{lr}
+ 137              	.LCFI4:
+ 138              		.cfi_def_cfa_offset 4
+ 139              		.cfi_offset 14, -4
+5727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
+5728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* in register and register position depending on parameter "AWDy".         */
+5729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
+5730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* containing other bits reserved for other purpose.                        */
+5731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> AD
+ 140              		.loc 2 5731 3 is_stmt 1 view .LVU20
+ 141              		.loc 2 5731 25 is_stmt 0 view .LVU21
+ 142 0002 0C30     		adds	r0, r0, #12
+ 143              	.LVL11:
+ 144              		.loc 2 5731 25 view .LVU22
+ 145 0004 C1F3015C 		ubfx	ip, r1, #20, #2
+ARM GAS  /tmp/ccICigVb.s 			page 104
+
+
+ 146 0008 01F00103 		and	r3, r1, #1
+ 147 000c 03EBC303 		add	r3, r3, r3, lsl #3
+ 148 0010 0CEB830C 		add	ip, ip, r3, lsl #2
+ 149              	.LVL12:
+5732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_C
+5733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+ 150              		.loc 2 5734 3 is_stmt 1 view .LVU23
+ 151 0014 50F82C30 		ldr	r3, [r0, ip, lsl #2]
+ 152 0018 21F0024E 		bic	lr, r1, #-2113929216
+ 153 001c 2EF4601E 		bic	lr, lr, #3670016
+ 154 0020 23EA0E03 		bic	r3, r3, lr
+ 155 0024 1140     		ands	r1, r1, r2
+ 156              	.LVL13:
+ 157              		.loc 2 5734 3 is_stmt 0 view .LVU24
+ 158 0026 0B43     		orrs	r3, r3, r1
+ 159 0028 40F82C30 		str	r3, [r0, ip, lsl #2]
+5735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+5736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              AWDChannelGroup & AWDy);
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 160              		.loc 2 5737 1 view .LVU25
+ 161 002c 5DF804FB 		ldr	pc, [sp], #4
+ 162              		.cfi_endproc
+ 163              	.LFE199:
+ 165              		.section	.text.HAL_ADC_MspInit,"ax",%progbits
+ 166              		.align	1
+ 167              		.weak	HAL_ADC_MspInit
+ 168              		.syntax unified
+ 169              		.thumb
+ 170              		.thumb_func
+ 172              	HAL_ADC_MspInit:
+ 173              	.LVL14:
+ 174              	.LFB331:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @file    stm32g4xx_hal_adc.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief   This file provides firmware functions to manage the following
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          functionalities of the Analog to Digital Converter (ADC)
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *           + Peripheral Control functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *           + Peripheral State functions
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          Other functions (extended functions) are available in file
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          "stm32g4xx_hal_adc_ex.c".
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   ******************************************************************************
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @attention
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * Copyright (c) 2019 STMicroelectronics.
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * All rights reserved.
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * in the root directory of this software component.
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   ******************************************************************************
+ARM GAS  /tmp/ccICigVb.s 			page 105
+
+
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   @verbatim
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   ==============================================================================
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                      ##### ADC peripheral features #####
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   ==============================================================================
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   [..]
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) Interrupt generation at the end of regular conversion and in case of
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       analog watchdog or overrun events.
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) Single and continuous conversion modes.
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) Scan mode for conversion of several channels sequentially.
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) Data alignment with in-built data coherency.
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) Programmable sampling time (channel wise)
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) External trigger (timer or EXTI) with configurable polarity
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) DMA request generation for transfer of conversions data of regular group.
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) Configurable delay between conversions in Dual interleaved mode.
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) ADC channels selectable single/differential input.
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) ADC offset shared on 4 offset instances.
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) ADC gain compensation
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) ADC calibration
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) ADC conversion of regular group.
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) ADC supply requirements: 1.62 V to 3.6 V.
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       Vdda or to an external voltage reference).
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                      ##### How to use this driver #####
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   ==============================================================================
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     [..]
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      *** Configuration of top level parameters related to ADC ***
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      ============================================================
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      [..]
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) Enable the ADC interface
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         (++) As prerequisite, ADC clock must be configured at RCC top level.
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         (++) Two clock settings are mandatory:
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****              (+++) ADC clock (core clock, also possibly conversion clock).
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****              (+++) ADC clock (conversions clock).
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    Two possible clock sources: synchronous clock derived from AHB clock
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    or asynchronous clock derived from system clock or PLL (output divider P)
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    running up to 75MHz.
+ARM GAS  /tmp/ccICigVb.s 			page 106
+
+
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****              (+++) Example:
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    Into HAL_ADC_MspInit() (recommended code location) or with
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    other device clock parameters configuration:
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                RCC_ADCCLKSOURCE_PLL enable:                       (optional: if asynchronous clock 
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLL;
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         (++) ADC clock source and clock prescaler are configured at ADC level with
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****              parameter "ClockPrescaler" using function HAL_ADC_Init().
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) ADC pins configuration
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          (++) Enable the clock for the ADC GPIOs
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          (++) Configure these ADC pins in analog mode
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               using function HAL_GPIO_Init()
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) Optionally, in case of usage of ADC with interruptions:
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          (++) Configure the NVIC for ADC
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               into the function of corresponding ADC interruption vector
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               ADCx_IRQHandler().
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) Optionally, in case of usage of DMA:
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               using function HAL_DMA_Init().
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          (++) Configure the NVIC for DMA
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               into the function of corresponding DMA interruption vector
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               DMAx_Channelx_IRQHandler().
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      *** Configuration of ADC, group regular, channels parameters ***
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      ================================================================
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      [..]
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) Configure the ADC parameters (resolution, data alignment, ...)
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         and regular group parameters (conversion trigger, sequencer, ...)
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         using function HAL_ADC_Init().
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) Configure the channels for regular group parameters (channel number,
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         channel rank into sequencer, ..., into regular group)
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         using function HAL_ADC_ConfigChannel().
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) Optionally, configure the analog watchdog parameters (channels
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         monitored, thresholds, ...)
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         using function HAL_ADC_AnalogWDGConfig().
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      *** Execution of ADC conversions ***
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      ====================================
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      [..]
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ARM GAS  /tmp/ccICigVb.s 			page 107
+
+
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) Optionally, perform an automatic ADC calibration to improve the
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         conversion accuracy
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         using function HAL_ADCEx_Calibration_Start().
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) ADC driver can be used among three modes: polling, interruption,
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         transfer by DMA.
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         (++) ADC conversion by polling:
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           (+++) Activate the ADC peripheral and start conversions
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 using function HAL_ADC_Start()
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           (+++) Wait for ADC conversion completion
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 using function HAL_ADC_PollForConversion()
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           (+++) Retrieve conversion results
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 using function HAL_ADC_GetValue()
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           (+++) Stop conversion and disable the ADC peripheral
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 using function HAL_ADC_Stop()
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         (++) ADC conversion by interruption:
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           (+++) Activate the ADC peripheral and start conversions
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 using function HAL_ADC_Start_IT()
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           (+++) Wait for ADC conversion completion by call of function
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 HAL_ADC_ConvCpltCallback()
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 (this function must be implemented in user program)
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           (+++) Retrieve conversion results
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 using function HAL_ADC_GetValue()
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           (+++) Stop conversion and disable the ADC peripheral
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 using function HAL_ADC_Stop_IT()
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         (++) ADC conversion with transfer by DMA:
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           (+++) Activate the ADC peripheral and start conversions
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 using function HAL_ADC_Start_DMA()
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           (+++) Wait for ADC conversion completion by call of function
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 (these functions must be implemented in user program)
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           (+++) Conversion results are automatically transferred by DMA into
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 destination variable address.
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           (+++) Stop conversion and disable the ADC peripheral
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 using function HAL_ADC_Stop_DMA()
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      [..]
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (@) Callback functions must be implemented in user program:
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+@) HAL_ADC_ErrorCallback()
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+@) HAL_ADC_ConvCpltCallback()
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+@) HAL_ADC_ConvHalfCpltCallback
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      *** Deinitialization of ADC ***
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      ============================================================
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      [..]
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) Disable the ADC interface
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (++) ADC clock can be hard reset and disabled at RCC top level.
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         (++) Hard reset of ADC peripherals
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****              using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         (++) ADC clock disable
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****              using the equivalent macro/functions as configuration step.
+ARM GAS  /tmp/ccICigVb.s 			page 108
+
+
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****              (+++) Example:
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    Into HAL_ADC_MspDeInit() (recommended code location) or with
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    other device clock parameters configuration:
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) ADC pins configuration
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          (++) Disable the clock for the ADC GPIOs
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) Optionally, in case of usage of ADC with interruptions:
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          (++) Disable the NVIC for ADC
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     (#) Optionally, in case of usage of DMA:
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          (++) Deinitialize the DMA
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               using function HAL_DMA_Init().
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          (++) Disable the NVIC for DMA
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     [..]
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     *** Callback registration ***
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     =============================================
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     [..]
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      allows the user to configure dynamically the driver callbacks.
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      Use Functions HAL_ADC_RegisterCallback()
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      to register an interrupt callback.
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     [..]
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      Function HAL_ADC_RegisterCallback() allows to register following callbacks:
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) ConvCpltCallback               : ADC conversion complete callback
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) ErrorCallback                  : ADC error callback
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) EndOfSamplingCallback          : ADC end of sampling callback
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) MspInitCallback                : ADC Msp Init callback
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) MspDeInitCallback              : ADC Msp DeInit callback
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      This function takes as parameters the HAL peripheral handle, the Callback ID
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      and a pointer to the user callback function.
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     [..]
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      weak function.
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     [..]
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      and the Callback ID.
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      This function allows to reset following callbacks:
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) ConvCpltCallback               : ADC conversion complete callback
+ARM GAS  /tmp/ccICigVb.s 			page 109
+
+
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) ErrorCallback                  : ADC error callback
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) EndOfSamplingCallback          : ADC end of sampling callback
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) MspInitCallback                : ADC Msp Init callback
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        (+) MspDeInitCallback              : ADC Msp DeInit callback
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      [..]
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      all callbacks are set to the corresponding weak functions:
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      Exception done for MspInit and MspDeInit functions that are
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      these callbacks are null (not registered beforehand).
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     [..]
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      [..]
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     [..]
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      Then, the user first registers the MspInit/MspDeInit user callbacks
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      or HAL_ADC_Init() function.
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      [..]
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      not defined, the callback registration feature is not available and all callbacks
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      are set to the corresponding weak functions.
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   @endverbatim
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   ******************************************************************************
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /* Includes ------------------------------------------------------------------*/
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #include "stm32g4xx_hal.h"
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /** @addtogroup STM32G4xx_HAL_Driver
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @{
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /** @defgroup ADC ADC
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief ADC HAL module driver
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @{
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #ifdef HAL_ADC_MODULE_ENABLED
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ARM GAS  /tmp/ccICigVb.s 			page 110
+
+
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /* Private typedef -----------------------------------------------------------*/
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /* Private define ------------------------------------------------------------*/
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /** @defgroup ADC_Private_Constants ADC Private Constants
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @{
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #define ADC_CFGR_FIELDS_1  ((ADC_CFGR_RES    | ADC_CFGR_ALIGN   |\
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                              ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                              ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                              ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL))   /*!< ADC_CFGR fields of paramete
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /* Timeout values for ADC operations (enable settling time,                   */
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /*   disable settling time, ...).                                             */
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /*   Values defined to be higher than worst cases: low clock frequency,       */
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /*   maximum prescalers.                                                      */
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #define ADC_ENABLE_TIMEOUT              (2UL)    /*!< ADC enable time-out value  */
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #define ADC_DISABLE_TIMEOUT             (2UL)    /*!< ADC disable time-out value */
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /* Timeout to wait for current conversion on going to be completed.           */
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /* Timeout fixed to longest ADC conversion possible, for 1 channel:           */
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /*   - maximum sampling time (640.5 adc_clk)                                  */
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /*   - ADC resolution (Tsar 12 bits= 12.5 adc_clk)                            */
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /*   - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio)   */
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /*   - ADC oversampling ratio 256                                             */
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /*   Calculation: 653 * 4096 * 256 CPU clock cycles max                       */
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /* Unit: cycles of CPU clock.                                                 */
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL)  /*!< ADC conversion completion
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @}
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /* Private macro -------------------------------------------------------------*/
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /* Private variables ---------------------------------------------------------*/
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /* Private function prototypes -----------------------------------------------*/
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /* Exported functions --------------------------------------------------------*/
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions ADC Exported Functions
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @{
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief    ADC Initialization and Configuration functions
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** @verbatim
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****  ===============================================================================
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               ##### Initialization and de-initialization functions #####
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****  ===============================================================================
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     [..]  This section provides functions allowing to:
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Initialize and configure the ADC.
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) De-initialize the ADC.
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** @endverbatim
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @{
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ARM GAS  /tmp/ccICigVb.s 			page 111
+
+
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Initialize the ADC peripheral and regular group according to
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         parameters specified in structure "ADC_InitTypeDef".
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   As prerequisite, ADC clock must be configured at RCC top level
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         (refer to description of RCC configuration for ADC
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         in header of this file).
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Possibility to update parameters on the fly:
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         coming from ADC state reset. Following calls to this function can
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         be used to reconfigure some parameters of ADC_InitTypeDef
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         structure on the fly, without modifying MSP configuration. If ADC
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         before HAL_ADC_Init().
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         The setting of these parameters is conditioned to ADC state.
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         For parameters constraints, see comments of structure
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         "ADC_InitTypeDef".
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   This function configures the ADC within 2 scopes: scope of entire
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         ADC and scope of regular group. For parameters details, see comments
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         of structure "ADC_InitTypeDef".
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Parameters related to common ADC registers (ADC clock mode) are set
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         only if all ADCs are disabled.
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         If this is not the case, these common parameters setting are
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         bypassed without error reporting: it can be the intended behaviour in
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         case of update of a parameter of ADC_InitTypeDef on the fly,
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         without  disabling the other ADCs.
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpCFGR;
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_reg_is_conversion_on_going;
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __IO uint32_t wait_loop_index = 0UL;
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_injected;
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check ADC handle */
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (hadc == NULL)
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     return HAL_ERROR;
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation));
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv));
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode));
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+ARM GAS  /tmp/ccICigVb.s 			page 112
+
+
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* DISCEN and CONT bits cannot be set at the same time */
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == 
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Actions performed only if ADC is coming from state reset:                */
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* - Initialization of ADC MSP                                              */
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (hadc->State == HAL_ADC_STATE_RESET)
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Init the ADC Callback settings */
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak 
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak 
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak 
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak 
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak 
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;  /* Legacy weak 
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->LevelOutOfWindow2Callback     = HAL_ADCEx_LevelOutOfWindow2Callback;      /* Legacy weak 
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->LevelOutOfWindow3Callback     = HAL_ADCEx_LevelOutOfWindow3Callback;      /* Legacy weak 
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->EndOfSamplingCallback         = HAL_ADCEx_EndOfSamplingCallback;          /* Legacy weak 
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (hadc->MspInitCallback == NULL)
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Init the low level hardware */
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->MspInitCallback(hadc);
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Init the low level hardware */
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     HAL_ADC_MspInit(hadc);
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Set ADC error code to none */
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     ADC_CLEAR_ERRORCODE(hadc);
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Initialize Lock */
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->Lock = HAL_UNLOCKED;
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Disable ADC deep power down mode */
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     LL_ADC_DisableDeepPowerDown(hadc->Instance);
+ARM GAS  /tmp/ccICigVb.s 			page 113
+
+
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* System was in deep power down mode, calibration must
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      be relaunched or a previously saved calibration factor
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      re-applied once the ADC voltage regulator is enabled */
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Enable ADC internal voltage regulator */
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     LL_ADC_EnableInternalRegulator(hadc->Instance);
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Note: Variable divided by 2 to compensate partially              */
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*       CPU processing cycles, scaling in us split to not          */
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*       exceed 32 bits register capacity and handle low frequency. */
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     while (wait_loop_index != 0UL)
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       wait_loop_index--;
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Verification that ADC voltage regulator is correctly enabled, whether    */
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* or not ADC is coming from state reset (if any potential problem of       */
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* clocking, voltage regulator would not be enabled).                       */
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Update ADC state machine to error */
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Set ADC error code to ADC peripheral internal error */
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_hal_status = HAL_ERROR;
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Configuration of ADC parameters if previous preliminary actions are      */
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* correctly completed and if there is no conversion on going on regular    */
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* called to update a parameter on the fly).                                */
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       && (tmp_adc_reg_is_conversion_on_going == 0UL)
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      )
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Set ADC state */
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     ADC_STATE_CLR_SET(hadc->State,
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY,
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                       HAL_ADC_STATE_BUSY_INTERNAL);
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Configuration of common ADC parameters                                 */
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Parameters update conditioned to ADC state:                            */
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Parameters that can be updated only when ADC is disabled:              */
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - clock configuration                                                 */
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ARM GAS  /tmp/ccICigVb.s 			page 114
+
+
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Reset configuration of ADC common register CCR:                      */
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*                                                                      */
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*   - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set  */
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*     according to adc->Init.ClockPrescaler. It selects the clock      */
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*    source and sets the clock division factor.                        */
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*                                                                      */
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Some parameters of this register are not reset, since they are set   */
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* by other functions and must be kept in case of usage of this         */
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* function on the fly (update of a parameter of ADC_InitTypeDef        */
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* without needing to reconfigure all other ADC groups/channels         */
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* parameters):                                                         */
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*   - when multimode feature is available, multimode-related           */
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*     (set into HAL_ADC_ConfigChannel() or                             */
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*     HAL_ADCEx_InjectedConfigChannel() )                              */
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Configuration of ADC:                                                  */
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - resolution                               Init.Resolution            */
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - data alignment                           Init.DataAlign             */
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - external trigger to start conversion     Init.ExternalTrigConv      */
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - continuous conversion mode               Init.ContinuousConvMode    */
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - overrun                                  Init.Overrun               */
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - discontinuous mode                       Init.DiscontinuousConvMode */
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - discontinuous mode channel count         Init.NbrOfDiscConversion   */
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)           |
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 hadc->Init.Overrun                                                     |
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 hadc->Init.DataAlign                                                   |
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 hadc->Init.Resolution                                                  |
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Enable external trigger if trigger selection is different of software  */
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* start.                                                                 */
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Note: This configuration keeps the hardware feature of parameter       */
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*       software start.                                                  */
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                   | hadc->Init.ExternalTrigConvEdge
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                  );
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Update Configuration Register CFGR */
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
+ARM GAS  /tmp/ccICigVb.s 			page 115
+
+
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Configuration of sampling mode */
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Parameters update conditioned to ADC state:                            */
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Parameters that can be updated when ADC is disabled or enabled without */
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* conversion on going on regular and injected groups:                    */
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - Gain Compensation               Init.GainCompensation               */
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - DMA continuous request          Init.DMAContinuousRequests          */
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - Oversampling parameters         Init.Oversampling                   */
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        )
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmpCFGR = (ADC_CFGR_DFSDM(hadc)                                            |
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                  ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                  ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (hadc->Init.GainCompensation != 0UL)
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (hadc->Init.OversamplingMode == ENABLE)
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Configuration of Oversampler:                                      */
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*  - Oversampling Ratio                                              */
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*  - Right bit shift                                                 */
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*  - Triggered mode                                                  */
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /*  - Oversampling mode (continued/resumed)                           */
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         MODIFY_REG(hadc->Instance->CFGR2,
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    ADC_CFGR2_OVSR  |
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    ADC_CFGR2_OVSS  |
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    ADC_CFGR2_TROVS |
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    ADC_CFGR2_ROVSM,
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    ADC_CFGR2_ROVSE                       |
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    hadc->Init.Oversampling.Ratio         |
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    hadc->Init.Oversampling.RightBitShift |
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    hadc->Init.Oversampling.TriggeredMode |
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    hadc->Init.Oversampling.OversamplingStopReset
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                   );
+ARM GAS  /tmp/ccICigVb.s 			page 116
+
+
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Disable ADC oversampling scope on ADC group regular */
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Configuration of regular group sequencer:                              */
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* - if scan mode is disabled, regular channels sequence length is set to */
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*   0x00: 1 channel converted (channel on regular rank 1)                */
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*   Parameter "NbrOfConversion" is discarded.                            */
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*   Note: Scan mode is not present by hardware on this device, but       */
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*   emulated by software for alignment over all STM32 devices.           */
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* - if scan mode is enabled, regular channels sequence length is set to  */
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*   parameter "NbrOfConversion".                                         */
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set number of ranks in regular group sequencer */
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Initialize the ADC state */
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Update ADC state machine to error */
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_hal_status = HAL_ERROR;
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return tmp_hal_status;
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Deinitialize the ADC peripheral registers to their default reset
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         values, with deinitialization of the ADC MSP.
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   For devices with several ADCs: reset of ADC common registers is done
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         only if all ADCs sharing the same common group are disabled.
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         all ADC instances use the same core clock at RCC level, disabling
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         the core clock reset all ADC instances).
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         If this is not the case, reset of these common parameters reset is
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         bypassed without error reporting: it can be the intended behavior in
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         case of reset of a single ADC while the other ADCs sharing the same
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         common group is still running.
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
+ARM GAS  /tmp/ccICigVb.s 			page 117
+
+
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         this saves more power by reducing leakage currents
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         and is particularly interesting before entering MCU low-power modes.
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check ADC handle */
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (hadc == NULL)
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     return HAL_ERROR;
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Set ADC state */
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Stop potential conversion on going */
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Disable ADC peripheral if conversions are effectively stopped            */
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Flush register JSQR: reset the queue sequencer when injected             */
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* queue sequencer is enabled and ADC disabled.                             */
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* The software and hardware triggers of the injected sequence are both     */
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* internally disabled just after the completion of the last valid          */
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* injected sequence.                                                       */
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Disable ADC peripheral if conversions are effectively stopped */
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (tmp_hal_status == HAL_OK)
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Disable the ADC peripheral */
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_hal_status = ADC_Disable(hadc);
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check if ADC is effectively disabled */
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (tmp_hal_status == HAL_OK)
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Change ADC state */
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       hadc->State = HAL_ADC_STATE_READY;
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Note: HAL ADC deInit is done independently of ADC conversion stop        */
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /*       and disable return status. In case of status fail, attempt to      */
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /*       perform deinitialization anyway and it is up user code in          */
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /*       in HAL_ADC_MspDeInit() to reset the ADC peripheral using           */
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /*       system RCC hard reset.                                             */
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* ========== Reset ADC registers ========== */
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register IER */
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                               ADC_IT_JQOVF | ADC_IT_OVR  |
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                               ADC_IT_JEOS  | ADC_IT_JEOC |
+ARM GAS  /tmp/ccICigVb.s 			page 118
+
+
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                               ADC_IT_EOS   | ADC_IT_EOC  |
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                               ADC_IT_EOSMP | ADC_IT_RDY));
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register ISR */
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                               ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                               ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                               ADC_FLAG_EOS   | ADC_FLAG_EOC  |
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                               ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register CR */
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      no direct reset applicable.
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      Update CR register to reset value where doable by software */
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register CFGR */
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register CFGR2 */
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS   | ADC_CFGR2_OVSS |
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             ADC_CFGR2_OVSR  | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register SMPR1 */
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register SMPR2 */
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register TR1 */
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register TR2 */
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register TR3 */
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register SQR1 */
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             ADC_SQR1_SQ1 | ADC_SQR1_L);
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register SQR2 */
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register SQR3 */
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register SQR4 */
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+ARM GAS  /tmp/ccICigVb.s 			page 119
+
+
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Register JSQR was reset when the ADC was disabled */
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register DR */
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* bits in access mode read only, no direct reset applicable*/
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register OFR1 */
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register OFR2 */
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register OFR3 */
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register OFR4 */
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* bits in access mode read only, no direct reset applicable*/
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register AWD2CR */
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register AWD3CR */
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register DIFSEL */
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register CALFACT */
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* ========== Reset common ADC registers ========== */
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Software is allowed to change common parameters only when all the other
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      ADCs are disabled.   */
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Reset configuration of ADC common register CCR:
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       - clock mode: CKMODE, PRESCEN
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       - multimode related parameters (when this feature is available): MDMA,
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       - internal measurement paths: Vbat, temperature sensor, Vref (set into
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     */
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* ========== Hard reset ADC peripheral ========== */
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Performs a global reset of the entire ADC peripherals instances        */
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* sharing the same common ADC instance: ADC state is forced to           */
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* a similar state as after device power-on.                              */
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Note: A possible implementation is to add RCC bus reset of ADC         */
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* (for example, using macro                                              */
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)":         */
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (hadc->MspDeInitCallback == NULL)
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ARM GAS  /tmp/ccICigVb.s 			page 120
+
+
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* DeInit the low level hardware */
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->MspDeInitCallback(hadc);
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* DeInit the low level hardware */
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     HAL_ADC_MspDeInit(hadc);
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Set ADC error code to none */
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   ADC_CLEAR_ERRORCODE(hadc);
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset injected channel configuration parameters */
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   hadc->InjectionConfig.ContextQueue = 0;
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   hadc->InjectionConfig.ChannelCount = 0;
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Set ADC state */
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   hadc->State = HAL_ADC_STATE_RESET;
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Process unlocked */
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return tmp_hal_status;
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Initialize the ADC MSP.
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval None
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 175              		.loc 1 914 1 is_stmt 1 view -0
+ 176              		.cfi_startproc
+ 177              		@ args = 0, pretend = 0, frame = 0
+ 178              		@ frame_needed = 0, uses_anonymous_args = 0
+ 179              		@ link register save eliminated.
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   UNUSED(hadc);
+ 180              		.loc 1 916 3 view .LVU27
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* NOTE : This function should not be modified. When the callback is needed,
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             function HAL_ADC_MspInit must be implemented in the user file.
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****    */
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 181              		.loc 1 921 1 is_stmt 0 view .LVU28
+ 182 0000 7047     		bx	lr
+ 183              		.cfi_endproc
+ 184              	.LFE331:
+ 186              		.section	.text.HAL_ADC_Init,"ax",%progbits
+ 187              		.align	1
+ 188              		.global	HAL_ADC_Init
+ 189              		.syntax unified
+ 190              		.thumb
+ARM GAS  /tmp/ccICigVb.s 			page 121
+
+
+ 191              		.thumb_func
+ 193              	HAL_ADC_Init:
+ 194              	.LVL15:
+ 195              	.LFB329:
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 196              		.loc 1 396 1 is_stmt 1 view -0
+ 197              		.cfi_startproc
+ 198              		@ args = 0, pretend = 0, frame = 8
+ 199              		@ frame_needed = 0, uses_anonymous_args = 0
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 200              		.loc 1 396 1 is_stmt 0 view .LVU30
+ 201 0000 30B5     		push	{r4, r5, lr}
+ 202              	.LCFI5:
+ 203              		.cfi_def_cfa_offset 12
+ 204              		.cfi_offset 4, -12
+ 205              		.cfi_offset 5, -8
+ 206              		.cfi_offset 14, -4
+ 207 0002 83B0     		sub	sp, sp, #12
+ 208              	.LCFI6:
+ 209              		.cfi_def_cfa_offset 24
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpCFGR;
+ 210              		.loc 1 397 3 is_stmt 1 view .LVU31
+ 211              	.LVL16:
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_reg_is_conversion_on_going;
+ 212              		.loc 1 398 3 view .LVU32
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __IO uint32_t wait_loop_index = 0UL;
+ 213              		.loc 1 399 3 view .LVU33
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+ 214              		.loc 1 400 3 view .LVU34
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+ 215              		.loc 1 400 17 is_stmt 0 view .LVU35
+ 216 0004 0023     		movs	r3, #0
+ 217 0006 0193     		str	r3, [sp, #4]
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_injected;
+ 218              		.loc 1 401 3 is_stmt 1 view .LVU36
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 219              		.loc 1 402 3 view .LVU37
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 220              		.loc 1 405 3 view .LVU38
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 221              		.loc 1 405 6 is_stmt 0 view .LVU39
+ 222 0008 0028     		cmp	r0, #0
+ 223 000a 00F00D81 		beq	.L31
+ 224 000e 0446     		mov	r4, r0
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+ 225              		.loc 1 411 3 is_stmt 1 view .LVU40
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ 226              		.loc 1 412 3 view .LVU41
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ 227              		.loc 1 413 3 view .LVU42
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation));
+ 228              		.loc 1 414 3 view .LVU43
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ 229              		.loc 1 415 3 view .LVU44
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ 230              		.loc 1 416 3 view .LVU45
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ARM GAS  /tmp/ccICigVb.s 			page 122
+
+
+ 231              		.loc 1 417 3 view .LVU46
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv));
+ 232              		.loc 1 418 3 view .LVU47
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode));
+ 233              		.loc 1 419 3 view .LVU48
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ 234              		.loc 1 420 3 view .LVU49
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+ 235              		.loc 1 421 3 view .LVU50
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+ 236              		.loc 1 422 3 view .LVU51
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+ 237              		.loc 1 423 3 view .LVU52
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+ 238              		.loc 1 424 3 view .LVU53
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 239              		.loc 1 425 3 view .LVU54
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 240              		.loc 1 427 3 view .LVU55
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 241              		.loc 1 434 7 view .LVU56
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 242              		.loc 1 439 3 view .LVU57
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 243              		.loc 1 443 3 view .LVU58
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 244              		.loc 1 443 11 is_stmt 0 view .LVU59
+ 245 0010 C36D     		ldr	r3, [r0, #92]
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 246              		.loc 1 443 6 view .LVU60
+ 247 0012 13B3     		cbz	r3, .L34
+ 248              	.LVL17:
+ 249              	.L10:
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 250              		.loc 1 477 3 is_stmt 1 view .LVU61
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 251              		.loc 1 477 7 is_stmt 0 view .LVU62
+ 252 0014 2368     		ldr	r3, [r4]
+ 253              	.LVL18:
+ 254              	.LBB334:
+ 255              	.LBI334:
+5738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC analog watchdog monitored channel.
+5741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Usage of the returned channel number:
+5742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To reinject this channel into another function LL_ADC_xxx:
+5743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the returned channel number is only partly formatted on definition
+5744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+5745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           with parts of literals LL_ADC_CHANNEL_x or using
+5746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+5747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Then the selected literal LL_ADC_CHANNEL_x can be used
+5748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           as parameter for another function.
+5749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To get the channel number in decimal format:
+5750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           process the returned value with the helper macro
+5751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+5752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Applicable only when the analog watchdog is set to monitor
+5753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           one channel.
+ARM GAS  /tmp/ccICigVb.s 			page 123
+
+
+5754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, there are 2 kinds of analog watchdog
+5755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         instance:
+5756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD standard (instance AWD1):
+5757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: can monitor 1 channel or all channels.
+5758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: ADC groups regular and-or injected.
+5759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is not limited (corresponds to
+5760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC resolution configured).
+5761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD flexible (instances AWD2, AWD3):
+5762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: flexible on channels monitored, selection is
+5763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             channel wise, from from 1 to all channels.
+5764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Specificity of this analog watchdog: Multiple channels can
+5765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             be selected. For example:
+5766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+5767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: not selection possible (monitoring on both
+5768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             groups regular and injected).
+5769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Channels selected are monitored on groups regular and injected:
+5770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+5771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+5772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+5773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+5774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             the 2 LSB are ignored.
+5775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+5776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+5777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+5778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+5779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
+5780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
+5781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
+5782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n
+5783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
+5784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
+5785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+5787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+5788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD2 (1)
+5789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD3 (1)
+5790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On this AWD number, monitored channel can be retrieved
+5792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             if only 1 channel is programmed (or none or all channels).
+5793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             This function cannot retrieve monitored channel if
+5794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             multiple channels are programmed simultaneously
+5795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             by bitfield.
+5796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+5797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_DISABLE
+5798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+5799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+5800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+5801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+5802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+5803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+5804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+5805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+5806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+5807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+5808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+5809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+5810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+ARM GAS  /tmp/ccICigVb.s 			page 124
+
+
+5811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+5812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+5813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+5814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+5815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+5816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+5817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+5818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+5819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+5820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+5821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+5822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+5823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+5824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+5825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+5826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+5827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+5828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+5829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+5830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+5831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+5832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+5833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+5834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+5835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+5836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+5837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+5838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+5839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+5840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+5841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+5842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+5843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+5844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+5845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+5846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+5847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+5848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+5849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+5850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+5851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+5852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+5853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+5854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+5855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+5856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+5857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+5858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.
+5860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
+5862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)
+5864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC
+5865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK);
+5867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ARM GAS  /tmp/ccICigVb.s 			page 125
+
+
+5868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */
+5869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* (parameter value LL_ADC_AWD_DISABLE).                                    */
+5870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Else, the selected AWD is enabled and is monitoring a group of channels  */
+5871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* or a single channel.                                                     */
+5872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   if (AnalogWDMonitChannels != 0UL)
+5873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+5874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     if (AWDy == LL_ADC_AWD1)
+5875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     {
+5876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
+5877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       {
+5878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         /* AWD monitoring a group of channels */
+5879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         AnalogWDMonitChannels = ((AnalogWDMonitChannels
+5880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                   | (ADC_AWD_CR23_CHANNEL_MASK)
+5881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                  )
+5882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                  & (~(ADC_CFGR_AWD1CH))
+5883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                 );
+5884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       }
+5885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       else
+5886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       {
+5887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         /* AWD monitoring a single channel */
+5888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         AnalogWDMonitChannels = (AnalogWDMonitChannels
+5889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                  | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1C
+5890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                 );
+5891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       }
+5892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     }
+5893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     else
+5894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     {
+5895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
+5896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       {
+5897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         /* AWD monitoring a group of channels */
+5898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
+5899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                  | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
+5900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                 );
+5901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       }
+5902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       else
+5903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       {
+5904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         /* AWD monitoring a single channel */
+5905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         /* AWD monitoring a group of channels */
+5906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         AnalogWDMonitChannels = (AnalogWDMonitChannels
+5907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                  | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
+5908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                  | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CF
+5909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                 );
+5910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       }
+5911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     }
+5912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   }
+5913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return AnalogWDMonitChannels;
+5915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+5916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC analog watchdog thresholds value of both thresholds
+5919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         high and low.
+5920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If value of only one threshold high or low must be set,
+5921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_SetAnalogWDThresholds().
+5922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of ADC resolution different of 12 bits,
+5923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog thresholds data require a specific shift.
+5924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+ARM GAS  /tmp/ccICigVb.s 			page 126
+
+
+5925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, there are 2 kinds of analog watchdog
+5926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         instance:
+5927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD standard (instance AWD1):
+5928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: can monitor 1 channel or all channels.
+5929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: ADC groups regular and-or injected.
+5930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is not limited (corresponds to
+5931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC resolution configured).
+5932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD flexible (instances AWD2, AWD3):
+5933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: flexible on channels monitored, selection is
+5934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             channel wise, from from 1 to all channels.
+5935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Specificity of this analog watchdog: Multiple channels can
+5936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             be selected. For example:
+5937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+5938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: not selection possible (monitoring on both
+5939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             groups regular and injected).
+5940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Channels selected are monitored on groups regular and injected:
+5941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+5942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+5943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+5944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+5945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             the 2 LSB are ignored.
+5946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
+5947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         impacted: the comparison of analog watchdog thresholds is done on
+5948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         oversampling final computation (after ratio and shift application):
+5949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC data register bitfield [15:4] (12 most significant bits).
+5950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll TR1      HT1            LL_ADC_ConfigAnalogWDThresholds\n
+5951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR2      HT2            LL_ADC_ConfigAnalogWDThresholds\n
+5952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR3      HT3            LL_ADC_ConfigAnalogWDThresholds\n
+5953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\n
+5954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\n
+5955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds
+5956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+5958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+5959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD2
+5960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD3
+5961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
+5962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
+5963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+5964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWD
+5966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                      uint32_t AWDThresholdLowValue)
+5967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
+5969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* position in register and register position depending on parameter        */
+5970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* "AWDy".                                                                  */
+5971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
+5972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* containing other bits reserved for other purpose.                        */
+5973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC
+5974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+5976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_TR1_HT1 | ADC_TR1_LT1,
+5977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
+5978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+5979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC analog watchdog threshold value of threshold
+ARM GAS  /tmp/ccICigVb.s 			page 127
+
+
+5982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         high or low.
+5983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If values of both thresholds high or low must be set,
+5984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
+5985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of ADC resolution different of 12 bits,
+5986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog thresholds data require a specific shift.
+5987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+5988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, there are 2 kinds of analog watchdog
+5989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         instance:
+5990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD standard (instance AWD1):
+5991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: can monitor 1 channel or all channels.
+5992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: ADC groups regular and-or injected.
+5993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is not limited (corresponds to
+5994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC resolution configured).
+5995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD flexible (instances AWD2, AWD3):
+5996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: flexible on channels monitored, selection is
+5997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             channel wise, from from 1 to all channels.
+5998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Specificity of this analog watchdog: Multiple channels can
+5999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             be selected. For example:
+6000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+6001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: not selection possible (monitoring on both
+6002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             groups regular and injected).
+6003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Channels selected are monitored on groups regular and injected:
+6004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+6005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+6006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+6007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+6008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             the 2 LSB are ignored.
+6009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
+6010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         impacted: the comparison of analog watchdog thresholds is done on
+6011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         oversampling final computation (after ratio and shift application):
+6012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC data register bitfield [15:4] (12 most significant bits).
+6013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is not conditioned to
+6014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC can be disabled, enabled with or without conversion on going
+6016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either ADC groups regular or injected.
+6017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n
+6018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n
+6019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n
+6020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n
+6021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n
+6022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR3      LT3            LL_ADC_SetAnalogWDThresholds
+6023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+6025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+6026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD2
+6027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD3
+6028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+6029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+6030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+6031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+6032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThr
+6035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                   uint32_t AWDThresholdValue)
+6036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "AWDThresholdValue" with bits         */
+6038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* position in register and register position depending on parameters       */
+ARM GAS  /tmp/ccICigVb.s 			page 128
+
+
+6039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* "AWDThresholdsHighLow" and "AWDy".                                       */
+6040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
+6041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* containing other bits reserved for other purpose.                        */
+6042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+6043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_RE
+6044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+6046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              AWDThresholdsHighLow,
+6047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TR
+6048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC analog watchdog threshold value of threshold high,
+6052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         threshold low or raw data with ADC thresholds high and low
+6053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         concatenated.
+6054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If raw data with ADC thresholds high and low is retrieved,
+6055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the data of each threshold high or low can be isolated
+6056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         using helper macro:
+6057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
+6058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of ADC resolution different of 12 bits,
+6059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog thresholds data require a specific shift.
+6060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+6061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n
+6062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n
+6063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n
+6064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n
+6065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n
+6066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR3      LT3            LL_ADC_GetAnalogWDThresholds
+6067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+6069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+6070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD2
+6071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD3
+6072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+6073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+6074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+6075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
+6076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+6077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AW
+6079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+6081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_
+6082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(*preg,
+6084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              (AWDThresholdsHighLow | ADC_TR1_LT1))
+6085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                     >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH
+6086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                         & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
+6087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC analog watchdog filtering configuration
+6091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+6094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+6095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, this feature is only available on first
+ARM GAS  /tmp/ccICigVb.s 			page 129
+
+
+6096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog (AWD1)
+6097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll TR1      AWDFILT        LL_ADC_SetAWDFilteringConfiguration
+6098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+6100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+6101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  FilteringConfig This parameter can be one of the following values:
+6102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_NONE
+6103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+6104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+6105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+6106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+6107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+6108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+6109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+6110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t
+6113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Prevent unused argument(s) compilation warning */
+6115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (void)(AWDy);
+6116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
+6117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC analog watchdog filtering configuration
+6121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, this feature is only available on first
+6122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog (AWD1)
+6123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll TR1      AWDFILT        LL_ADC_GetAWDFilteringConfiguration
+6124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+6126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+6127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be:
+6128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_NONE
+6129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+6130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+6131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+6132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+6133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+6134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+6135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+6136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy)
+6138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Prevent unused argument(s) compilation warning */
+6140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (void)(AWDy);
+6141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
+6142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+6146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: over
+6149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+6150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 130
+
+
+6153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC oversampling scope: ADC groups regular and-or injected
+6154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (availability of ADC group injected depends on STM32 families).
+6155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If both groups regular and injected are selected,
+6156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         specify behavior of ADC group injected interrupting
+6157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         group regular: when ADC group injected is triggered,
+6158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the oversampling on ADC group regular is either
+6159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         temporary stopped and continued, or resumed from start
+6160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (oversampler buffer reset).
+6161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+6164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+6165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n
+6166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n
+6167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope
+6168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  OvsScope This parameter can be one of the following values:
+6170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_DISABLE
+6171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+6172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+6173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
+6174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+6175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
+6178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
+6180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC oversampling scope: ADC groups regular and-or injected
+6184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (availability of ADC group injected depends on STM32 families).
+6185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If both groups regular and injected are selected,
+6186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         specify behavior of ADC group injected interrupting
+6187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         group regular: when ADC group injected is triggered,
+6188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the oversampling on ADC group regular is either
+6189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         temporary stopped and continued, or resumed from start
+6190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (oversampler buffer reset).
+6191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n
+6192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n
+6193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope
+6194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+6196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_DISABLE
+6197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+6198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+6199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
+6200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+6201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
+6203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
+6205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC oversampling discontinuous mode (triggered mode)
+6209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on the selected ADC group.
+ARM GAS  /tmp/ccICigVb.s 			page 131
+
+
+6210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Number of oversampled conversions are done either in:
+6211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - continuous mode (all conversions of oversampling ratio
+6212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           are done from 1 trigger)
+6213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - discontinuous mode (each conversion of oversampling ratio
+6214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           needs a trigger)
+6215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+6218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+6219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, oversampling discontinuous mode
+6220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (triggered mode) can be used only when oversampling is
+6221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         set on group regular only and in resumed mode.
+6222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont
+6223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  OverSamplingDiscont This parameter can be one of the following values:
+6225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_REG_CONT
+6226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_REG_DISCONT
+6227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
+6230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
+6232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC oversampling discontinuous mode (triggered mode)
+6236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on the selected ADC group.
+6237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Number of oversampled conversions are done either in:
+6238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - continuous mode (all conversions of oversampling ratio
+6239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           are done from 1 trigger)
+6240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - discontinuous mode (each conversion of oversampling ratio
+6241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           needs a trigger)
+6242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont
+6243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+6245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_REG_CONT
+6246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_REG_DISCONT
+6247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
+6249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
+6251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC oversampling
+6255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (impacting both ADC groups regular and injected)
+6256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function set the 2 items of oversampling configuration:
+6257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ratio
+6258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - shift
+6259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+6262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+6263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
+6264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
+6265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Ratio This parameter can be one of the following values:
+ARM GAS  /tmp/ccICigVb.s 			page 132
+
+
+6267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_2
+6268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_4
+6269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_8
+6270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_16
+6271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_32
+6272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_64
+6273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_128
+6274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_256
+6275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Shift This parameter can be one of the following values:
+6276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+6277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+6278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+6279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+6280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+6281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+6282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+6283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+6284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+6285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_
+6288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
+6290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC oversampling ratio
+6294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *        (impacting both ADC groups regular and injected)
+6295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
+6296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Ratio This parameter can be one of the following values:
+6298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_2
+6299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_4
+6300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_8
+6301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_16
+6302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_32
+6303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_64
+6304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_128
+6305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_256
+6306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
+6308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
+6310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC oversampling shift
+6314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *        (impacting both ADC groups regular and injected)
+6315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
+6316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Shift This parameter can be one of the following values:
+6318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+6319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+6320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+6321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+6322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+6323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+ARM GAS  /tmp/ccICigVb.s 			page 133
+
+
+6324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+6325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+6326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+6327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
+6329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
+6331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+6335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multim
+6338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+6339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+6342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC multimode configuration to operate in independent mode
+6344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or multimode (for devices with several ADC instances).
+6345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If multimode configuration: the selected ADC instance is
+6346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         either master or slave depending on hardware.
+6347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to reference manual.
+6348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         All ADC instances of the ADC common group must be disabled.
+6351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+6352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instance or by using helper macro
+6353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+6354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      DUAL           LL_ADC_SetMultimode
+6355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Multimode This parameter can be one of the following values:
+6358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+6359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+6360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+6361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+6362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+6363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+6364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+6365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+6366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
+6369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
+6371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC multimode configuration to operate in independent mode
+6375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or multimode (for devices with several ADC instances).
+6376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If multimode configuration: the selected ADC instance is
+6377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         either master or slave depending on hardware.
+6378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to reference manual.
+6379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      DUAL           LL_ADC_GetMultimode
+6380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+ARM GAS  /tmp/ccICigVb.s 			page 134
+
+
+6381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+6383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+6384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+6385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+6386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+6387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+6388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+6389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+6390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+6391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
+6393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
+6395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC multimode conversion data transfer: no transfer
+6399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or transfer by DMA.
+6400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC multimode transfer by DMA is not selected:
+6401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         each ADC uses its own DMA channel, with its individual
+6402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         DMA transfer settings.
+6403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         If ADC multimode transfer by DMA is selected:
+6404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         One DMA channel is used for both ADC (DMA of ADC master)
+6405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Specifies the DMA requests mode:
+6406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Limited mode (One shot mode): DMA transfer requests are stopped
+6407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           when number of DMA data transfers (number of
+6408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions) is reached.
+6409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode non-circular.
+6410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Unlimited mode: DMA transfer requests are unlimited,
+6411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           whatever number of DMA data transfers (number of
+6412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions).
+6413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode circular.
+6414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+6415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         mode non-circular:
+6416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         when DMA transfers size will be reached, DMA will stop transfers of
+6417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversions data ADC will raise an overrun error
+6418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (overrun flag and interruption if enabled).
+6419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   How to retrieve multimode conversion data:
+6420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Whatever multimode transfer by DMA setting: using function
+6421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref LL_ADC_REG_ReadMultiConversionData32().
+6422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         If ADC multimode transfer by DMA is selected: conversion data
+6423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is a raw data with ADC master and slave concatenated.
+6424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         A macro is available to get the conversion data of
+6425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC master or ADC slave: see helper macro
+6426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+6427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         All ADC instances of the ADC common group must be disabled
+6430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or enabled without conversion on going on group regular.
+6431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\n
+6432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      DMACFG         LL_ADC_SetMultiDMATransfer
+6433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  MultiDMATransfer This parameter can be one of the following values:
+6436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+6437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+ARM GAS  /tmp/ccICigVb.s 			page 135
+
+
+6438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+6439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+6440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+6441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMA
+6444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
+6446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC multimode conversion data transfer: no transfer
+6450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or transfer by DMA.
+6451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC multimode transfer by DMA is not selected:
+6452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         each ADC uses its own DMA channel, with its individual
+6453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         DMA transfer settings.
+6454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         If ADC multimode transfer by DMA is selected:
+6455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         One DMA channel is used for both ADC (DMA of ADC master)
+6456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Specifies the DMA requests mode:
+6457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Limited mode (One shot mode): DMA transfer requests are stopped
+6458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           when number of DMA data transfers (number of
+6459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions) is reached.
+6460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode non-circular.
+6461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Unlimited mode: DMA transfer requests are unlimited,
+6462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           whatever number of DMA data transfers (number of
+6463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions).
+6464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode circular.
+6465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+6466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         mode non-circular:
+6467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         when DMA transfers size will be reached, DMA will stop transfers of
+6468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversions data ADC will raise an overrun error
+6469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (overrun flag and interruption if enabled).
+6470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   How to retrieve multimode conversion data:
+6471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Whatever multimode transfer by DMA setting: using function
+6472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref LL_ADC_REG_ReadMultiConversionData32().
+6473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         If ADC multimode transfer by DMA is selected: conversion data
+6474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is a raw data with ADC master and slave concatenated.
+6475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         A macro is available to get the conversion data of
+6476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC master or ADC slave: see helper macro
+6477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+6478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\n
+6479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      DMACFG         LL_ADC_GetMultiDMATransfer
+6480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+6483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+6484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+6485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+6486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+6487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+6488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
+6490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
+6492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 136
+
+
+6495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC multimode delay between 2 sampling phases.
+6496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The sampling delay range depends on ADC resolution:
+6497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC resolution 12 bits can have maximum delay of 12 cycles.
+6498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC resolution 10 bits can have maximum delay of 10 cycles.
+6499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC resolution  8 bits can have maximum delay of  8 cycles.
+6500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC resolution  6 bits can have maximum delay of  6 cycles.
+6501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         All ADC instances of the ADC common group must be disabled.
+6504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+6505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instance or by using helper macro helper macro
+6506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+6507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay
+6508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  MultiTwoSamplingDelay This parameter can be one of the following values:
+6511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+6512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+6513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+6514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+6515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+6516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
+6517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
+6518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
+6519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
+6520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+6521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+6522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+6523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+6524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+6525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+6526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) Parameter available only if ADC resolution is 12 bits.
+6527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Mul
+6530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
+6532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC multimode delay between 2 sampling phases.
+6536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay
+6537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+6540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+6541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+6542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+6543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+6544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+6545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
+6546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
+6547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
+6548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
+6549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+6550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+6551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+ARM GAS  /tmp/ccICigVb.s 			page 137
+
+
+6552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+6553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+6554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+6555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) Parameter available only if ADC resolution is 12 bits.
+6556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
+6558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
+6560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+6562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+6565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+6567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+6568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Put ADC instance in deep power down state.
+6572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
+6573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         state, the internal analog calibration is lost. After exiting from
+6574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         deep power down, calibration must be relaunched or calibration factor
+6575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (preliminarily saved) must be set back into calibration register.
+6576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled.
+6579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown
+6580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
+6584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+6590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_DEEPPWD);
+6591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable ADC deep power down mode.
+6595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
+6596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         state, the internal analog calibration is lost. After exiting from
+6597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         deep power down, calibration must be relaunched or calibration factor
+6598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (preliminarily saved) must be set back into calibration register.
+6599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled.
+6602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
+6603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
+6607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+ARM GAS  /tmp/ccICigVb.s 			page 138
+
+
+6609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
+6612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get the selected ADC instance deep power down state.
+6616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
+6617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: deep power down is disabled, 1: deep power down is enabled.
+6619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
+ 256              		.loc 2 6620 26 is_stmt 1 view .LVU63
+ 257              	.LBB335:
+6621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
+ 258              		.loc 2 6622 3 view .LVU64
+ 259              		.loc 2 6622 12 is_stmt 0 view .LVU65
+ 260 0016 9A68     		ldr	r2, [r3, #8]
+ 261              		.loc 2 6622 74 view .LVU66
+ 262 0018 12F0005F 		tst	r2, #536870912
+ 263 001c 05D0     		beq	.L11
+ 264              	.LVL19:
+ 265              		.loc 2 6622 74 view .LVU67
+ 266              	.LBE335:
+ 267              	.LBE334:
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 268              		.loc 1 480 5 is_stmt 1 view .LVU68
+ 269              	.LBB336:
+ 270              	.LBI336:
+6606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 271              		.loc 2 6606 22 view .LVU69
+ 272              	.LBB337:
+6611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 273              		.loc 2 6611 3 view .LVU70
+ 274 001e 9A68     		ldr	r2, [r3, #8]
+ 275 0020 22F02042 		bic	r2, r2, #-1610612736
+ 276 0024 22F03F02 		bic	r2, r2, #63
+ 277 0028 9A60     		str	r2, [r3, #8]
+ 278              	.LVL20:
+ 279              	.L11:
+6611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 280              		.loc 2 6611 3 is_stmt 0 view .LVU71
+ 281              	.LBE337:
+ 282              	.LBE336:
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 283              		.loc 1 487 3 is_stmt 1 view .LVU72
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 284              		.loc 1 487 7 is_stmt 0 view .LVU73
+ 285 002a 2268     		ldr	r2, [r4]
+ 286              	.LVL21:
+ 287              	.LBB338:
+ 288              	.LBI338:
+6623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable ADC instance internal voltage regulator.
+ARM GAS  /tmp/ccICigVb.s 			page 139
+
+
+6627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, after ADC internal voltage regulator enable,
+6628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a delay for ADC internal voltage regulator stabilization
+6629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is required before performing a ADC calibration or ADC enable.
+6630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet, parameter tADCVREG_STUP.
+6631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
+6632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled.
+6635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
+6636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
+6640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+6646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADVREGEN);
+6647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable ADC internal voltage regulator.
+6651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled.
+6654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
+6655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
+6659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
+6661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get the selected ADC instance internal voltage regulator state.
+6665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
+6666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+6668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
+ 289              		.loc 2 6669 26 is_stmt 1 view .LVU74
+ 290              	.LBB339:
+6670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
+ 291              		.loc 2 6671 3 view .LVU75
+ 292              		.loc 2 6671 12 is_stmt 0 view .LVU76
+ 293 002c 9368     		ldr	r3, [r2, #8]
+ 294              		.loc 2 6671 76 view .LVU77
+ 295 002e 13F0805F 		tst	r3, #268435456
+ 296 0032 1FD1     		bne	.L12
+ 297              	.LVL22:
+ 298              		.loc 2 6671 76 view .LVU78
+ 299              	.LBE339:
+ 300              	.LBE338:
+ARM GAS  /tmp/ccICigVb.s 			page 140
+
+
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 301              		.loc 1 490 5 is_stmt 1 view .LVU79
+ 302              	.LBB340:
+ 303              	.LBI340:
+6639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 304              		.loc 2 6639 22 view .LVU80
+ 305              	.LBB341:
+6644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 306              		.loc 2 6644 3 view .LVU81
+ 307 0034 9368     		ldr	r3, [r2, #8]
+ 308 0036 23F01043 		bic	r3, r3, #-1879048192
+ 309 003a 23F03F03 		bic	r3, r3, #63
+ 310 003e 43F08053 		orr	r3, r3, #268435456
+ 311 0042 9360     		str	r3, [r2, #8]
+ 312              	.LVL23:
+6644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 313              		.loc 2 6644 3 is_stmt 0 view .LVU82
+ 314              	.LBE341:
+ 315              	.LBE340:
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     while (wait_loop_index != 0UL)
+ 316              		.loc 1 495 5 is_stmt 1 view .LVU83
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     while (wait_loop_index != 0UL)
+ 317              		.loc 1 495 89 is_stmt 0 view .LVU84
+ 318 0044 794B     		ldr	r3, .L38
+ 319 0046 1B68     		ldr	r3, [r3]
+ 320 0048 9B09     		lsrs	r3, r3, #6
+ 321 004a 794A     		ldr	r2, .L38+4
+ 322 004c A2FB0323 		umull	r2, r3, r2, r3
+ 323 0050 9B09     		lsrs	r3, r3, #6
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     while (wait_loop_index != 0UL)
+ 324              		.loc 1 495 109 view .LVU85
+ 325 0052 0133     		adds	r3, r3, #1
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     while (wait_loop_index != 0UL)
+ 326              		.loc 1 495 69 view .LVU86
+ 327 0054 5B00     		lsls	r3, r3, #1
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     while (wait_loop_index != 0UL)
+ 328              		.loc 1 495 21 view .LVU87
+ 329 0056 0193     		str	r3, [sp, #4]
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 330              		.loc 1 496 5 is_stmt 1 view .LVU88
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 331              		.loc 1 496 11 is_stmt 0 view .LVU89
+ 332 0058 09E0     		b	.L13
+ 333              	.LVL24:
+ 334              	.L34:
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 335              		.loc 1 466 5 is_stmt 1 view .LVU90
+ 336 005a FFF7FEFF 		bl	HAL_ADC_MspInit
+ 337              	.LVL25:
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 338              		.loc 1 470 5 view .LVU91
+ 339 005e 0023     		movs	r3, #0
+ 340 0060 2366     		str	r3, [r4, #96]
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 341              		.loc 1 473 5 view .LVU92
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 342              		.loc 1 473 16 is_stmt 0 view .LVU93
+ARM GAS  /tmp/ccICigVb.s 			page 141
+
+
+ 343 0062 84F85830 		strb	r3, [r4, #88]
+ 344 0066 D5E7     		b	.L10
+ 345              	.L14:
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 346              		.loc 1 498 7 is_stmt 1 view .LVU94
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 347              		.loc 1 498 22 is_stmt 0 view .LVU95
+ 348 0068 019B     		ldr	r3, [sp, #4]
+ 349 006a 013B     		subs	r3, r3, #1
+ 350 006c 0193     		str	r3, [sp, #4]
+ 351              	.L13:
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 352              		.loc 1 496 28 is_stmt 1 view .LVU96
+ 353 006e 019B     		ldr	r3, [sp, #4]
+ 354 0070 002B     		cmp	r3, #0
+ 355 0072 F9D1     		bne	.L14
+ 356              	.L12:
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 357              		.loc 1 505 3 view .LVU97
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 358              		.loc 1 505 7 is_stmt 0 view .LVU98
+ 359 0074 2268     		ldr	r2, [r4]
+ 360              	.LVL26:
+ 361              	.LBB342:
+ 362              	.LBI342:
+6669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 363              		.loc 2 6669 26 is_stmt 1 view .LVU99
+ 364              	.LBB343:
+ 365              		.loc 2 6671 3 view .LVU100
+ 366              		.loc 2 6671 12 is_stmt 0 view .LVU101
+ 367 0076 9368     		ldr	r3, [r2, #8]
+ 368              		.loc 2 6671 76 view .LVU102
+ 369 0078 13F0805F 		tst	r3, #268435456
+ 370 007c 40F09C80 		bne	.L32
+ 371              	.LVL27:
+ 372              		.loc 2 6671 76 view .LVU103
+ 373              	.LBE343:
+ 374              	.LBE342:
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 375              		.loc 1 508 5 is_stmt 1 view .LVU104
+ 376 0080 E36D     		ldr	r3, [r4, #92]
+ 377 0082 43F01003 		orr	r3, r3, #16
+ 378 0086 E365     		str	r3, [r4, #92]
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 379              		.loc 1 511 5 view .LVU105
+ 380 0088 236E     		ldr	r3, [r4, #96]
+ 381 008a 43F00103 		orr	r3, r3, #1
+ 382 008e 2366     		str	r3, [r4, #96]
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 383              		.loc 1 513 5 view .LVU106
+ 384              	.LVL28:
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 385              		.loc 1 513 20 is_stmt 0 view .LVU107
+ 386 0090 0120     		movs	r0, #1
+ 387              	.LVL29:
+ 388              	.L15:
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ARM GAS  /tmp/ccICigVb.s 			page 142
+
+
+ 389              		.loc 1 520 3 is_stmt 1 view .LVU108
+ 390              	.LBB344:
+ 391              	.LBI344:
+6672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable the selected ADC instance.
+6676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, after ADC enable, a delay for
+6677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC internal analog stabilization is required before performing a
+6678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion start.
+6679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet, parameter tSTAB.
+6680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+6681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is enabled and when conversion clock is active.
+6682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (not only core clock: this ADC has a dual clock domain)
+6683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
+6686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADEN           LL_ADC_Enable
+6687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+6691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+6697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADEN);
+6698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable the selected ADC instance.
+6702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be not disabled. Must be enabled without conversion on going
+6705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+6706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADDIS          LL_ADC_Disable
+6707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+6711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+6717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADDIS);
+6718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get the selected ADC instance enable state.
+6722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+6723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is enabled and when conversion clock is active.
+6724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (not only core clock: this ADC has a dual clock domain)
+6725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADEN           LL_ADC_IsEnabled
+ARM GAS  /tmp/ccICigVb.s 			page 143
+
+
+6726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: ADC is disabled, 1: ADC is enabled.
+6728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+6730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
+6732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get the selected ADC instance disable state.
+6736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
+6737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: no ADC disable command on going.
+6739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
+6741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
+6743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Start ADC calibration in the mode single-ended
+6747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or differential (for devices with differential mode available).
+6748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, a minimum number of ADC clock cycles
+6749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         are required between ADC end of calibration and ADC enable.
+6750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+6751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with differential mode available:
+6752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Calibration of offset is specific to each of
+6753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         single-ended and differential modes
+6754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (calibration run must be performed for each of these
+6755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         differential modes, if used afterwards and if the application
+6756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         requires their calibration).
+6757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled.
+6760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n
+6761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CR       ADCALDIF       LL_ADC_StartCalibration
+6762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SingleDiff This parameter can be one of the following values:
+6764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SINGLE_ENDED
+6765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+6766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+6769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
+6775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
+6776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC calibration state.
+6780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
+6781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: calibration complete, 1: calibration in progress.
+ARM GAS  /tmp/ccICigVb.s 			page 144
+
+
+6783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+6785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
+6787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+6791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regu
+6794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+6795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Start ADC group regular conversion.
+6799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, this function is relevant for both
+6800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal trigger (SW start) and external trigger:
+6801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - If ADC trigger has been set to software start, ADC conversion
+6802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           starts immediately.
+6803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - If ADC trigger has been set to external trigger, ADC conversion
+6804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           will start at next trigger event (on the selected trigger edge)
+6805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           following the ADC start conversion command.
+6806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled without conversion on going on group regular,
+6809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without conversion stop command on going on group regular,
+6810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without ADC disable command on going.
+6811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
+6812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+6816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+6822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADSTART);
+6823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Stop ADC group regular conversion.
+6827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled with conversion on going on group regular,
+6830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without ADC disable command on going.
+6831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
+6832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
+6836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+ARM GAS  /tmp/ccICigVb.s 			page 145
+
+
+6840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+6842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADSTP);
+6843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion state.
+6847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
+6848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: no conversion is on going on ADC group regular.
+6850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
+ 392              		.loc 2 6851 26 view .LVU109
+ 393              	.LBB345:
+6852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
+ 394              		.loc 2 6853 3 view .LVU110
+ 395              		.loc 2 6853 12 is_stmt 0 view .LVU111
+ 396 0092 9368     		ldr	r3, [r2, #8]
+ 397              		.loc 2 6853 74 view .LVU112
+ 398 0094 13F00403 		ands	r3, r3, #4
+ 399 0098 00D0     		beq	.L16
+ 400 009a 0123     		movs	r3, #1
+ 401              	.L16:
+ 402              	.LVL30:
+ 403              		.loc 2 6853 74 view .LVU113
+ 404              	.LBE345:
+ 405              	.LBE344:
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       && (tmp_adc_reg_is_conversion_on_going == 0UL)
+ 406              		.loc 1 522 3 is_stmt 1 view .LVU114
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       && (tmp_adc_reg_is_conversion_on_going == 0UL)
+ 407              		.loc 1 522 13 is_stmt 0 view .LVU115
+ 408 009c E16D     		ldr	r1, [r4, #92]
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       && (tmp_adc_reg_is_conversion_on_going == 0UL)
+ 409              		.loc 1 522 6 view .LVU116
+ 410 009e 11F0100F 		tst	r1, #16
+ 411 00a2 40F0BA80 		bne	.L17
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      )
+ 412              		.loc 1 523 7 view .LVU117
+ 413 00a6 002B     		cmp	r3, #0
+ 414 00a8 40F0B780 		bne	.L17
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY,
+ 415              		.loc 1 527 5 is_stmt 1 view .LVU118
+ 416 00ac E36D     		ldr	r3, [r4, #92]
+ 417              	.LVL31:
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY,
+ 418              		.loc 1 527 5 is_stmt 0 view .LVU119
+ 419 00ae 23F48173 		bic	r3, r3, #258
+ 420 00b2 43F00203 		orr	r3, r3, #2
+ 421 00b6 E365     		str	r3, [r4, #92]
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 422              		.loc 1 536 5 is_stmt 1 view .LVU120
+ 423              	.LVL32:
+ 424              	.LBB346:
+ 425              	.LBI346:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 426              		.loc 2 6729 26 view .LVU121
+ARM GAS  /tmp/ccICigVb.s 			page 146
+
+
+ 427              	.LBB347:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 428              		.loc 2 6731 3 view .LVU122
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 429              		.loc 2 6731 12 is_stmt 0 view .LVU123
+ 430 00b8 9368     		ldr	r3, [r2, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 431              		.loc 2 6731 68 view .LVU124
+ 432 00ba 13F0010F 		tst	r3, #1
+ 433 00be 15D1     		bne	.L18
+ 434              	.LVL33:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 435              		.loc 2 6731 68 view .LVU125
+ 436              	.LBE347:
+ 437              	.LBE346:
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 438              		.loc 1 538 7 is_stmt 1 view .LVU126
+ 439              	.LBB348:
+ 440              	.LBI348:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 441              		.loc 2 6729 26 view .LVU127
+ 442              	.LBB349:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 443              		.loc 2 6731 3 view .LVU128
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 444              		.loc 2 6731 12 is_stmt 0 view .LVU129
+ 445 00c0 4FF0A043 		mov	r3, #1342177280
+ 446 00c4 9A68     		ldr	r2, [r3, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 447              		.loc 2 6731 68 view .LVU130
+ 448 00c6 12F00102 		ands	r2, r2, #1
+ 449 00ca 00D0     		beq	.L19
+ 450 00cc 0122     		movs	r2, #1
+ 451              	.L19:
+ 452              	.LVL34:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 453              		.loc 2 6731 68 view .LVU131
+ 454              	.LBE349:
+ 455              	.LBE348:
+ 456              	.LBB350:
+ 457              	.LBI350:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 458              		.loc 2 6729 26 is_stmt 1 view .LVU132
+ 459              	.LBB351:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 460              		.loc 2 6731 3 view .LVU133
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 461              		.loc 2 6731 12 is_stmt 0 view .LVU134
+ 462 00ce 594B     		ldr	r3, .L38+8
+ 463 00d0 9B68     		ldr	r3, [r3, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 464              		.loc 2 6731 68 view .LVU135
+ 465 00d2 13F00103 		ands	r3, r3, #1
+ 466 00d6 00D0     		beq	.L20
+ 467 00d8 0123     		movs	r3, #1
+ 468              	.L20:
+ 469              	.LVL35:
+ARM GAS  /tmp/ccICigVb.s 			page 147
+
+
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 470              		.loc 2 6731 68 view .LVU136
+ 471              	.LBE351:
+ 472              	.LBE350:
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 473              		.loc 1 538 10 view .LVU137
+ 474 00da 1343     		orrs	r3, r3, r2
+ 475 00dc 06D1     		bne	.L18
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 476              		.loc 1 557 9 is_stmt 1 view .LVU138
+ 477 00de 6368     		ldr	r3, [r4, #4]
+ 478              	.LVL36:
+ 479              	.LBB352:
+ 480              	.LBI352:
+2732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 481              		.loc 2 2732 22 view .LVU139
+ 482              	.LBB353:
+2734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 483              		.loc 2 2734 3 view .LVU140
+ 484 00e0 5549     		ldr	r1, .L38+12
+ 485 00e2 8A68     		ldr	r2, [r1, #8]
+ 486 00e4 22F47C12 		bic	r2, r2, #4128768
+ 487 00e8 1343     		orrs	r3, r3, r2
+ 488              	.LVL37:
+2734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 489              		.loc 2 2734 3 is_stmt 0 view .LVU141
+ 490 00ea 8B60     		str	r3, [r1, #8]
+ 491              	.LVL38:
+ 492              	.L18:
+2734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 493              		.loc 2 2734 3 view .LVU142
+ 494              	.LBE353:
+ 495              	.LBE352:
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 hadc->Init.Overrun                                                     |
+ 496              		.loc 1 570 5 is_stmt 1 view .LVU143
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 hadc->Init.Overrun                                                     |
+ 497              		.loc 1 570 17 is_stmt 0 view .LVU144
+ 498 00ec 627F     		ldrb	r2, [r4, #29]	@ zero_extendqisi2
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 hadc->Init.DataAlign                                                   |
+ 499              		.loc 1 571 27 view .LVU145
+ 500 00ee E36B     		ldr	r3, [r4, #60]
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 hadc->Init.Overrun                                                     |
+ 501              		.loc 1 570 88 view .LVU146
+ 502 00f0 43EA4233 		orr	r3, r3, r2, lsl #13
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 hadc->Init.Resolution                                                  |
+ 503              		.loc 1 572 27 view .LVU147
+ 504 00f4 E268     		ldr	r2, [r4, #12]
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 hadc->Init.DataAlign                                                   |
+ 505              		.loc 1 571 88 view .LVU148
+ 506 00f6 1343     		orrs	r3, r3, r2
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+ 507              		.loc 1 573 27 view .LVU149
+ 508 00f8 A268     		ldr	r2, [r4, #8]
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 hadc->Init.Resolution                                                  |
+ 509              		.loc 1 572 88 view .LVU150
+ 510 00fa 1343     		orrs	r3, r3, r2
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ARM GAS  /tmp/ccICigVb.s 			page 148
+
+
+ 511              		.loc 1 574 17 view .LVU151
+ 512 00fc 94F82420 		ldrb	r2, [r4, #36]	@ zero_extendqisi2
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 hadc->Init.Overrun                                                     |
+ 513              		.loc 1 570 14 view .LVU152
+ 514 0100 43EA0243 		orr	r3, r3, r2, lsl #16
+ 515              	.LVL39:
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 516              		.loc 1 576 5 is_stmt 1 view .LVU153
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 517              		.loc 1 576 8 is_stmt 0 view .LVU154
+ 518 0104 012A     		cmp	r2, #1
+ 519 0106 59D0     		beq	.L35
+ 520              	.L21:
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 521              		.loc 1 586 5 is_stmt 1 view .LVU155
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 522              		.loc 1 586 19 is_stmt 0 view .LVU156
+ 523 0108 E26A     		ldr	r2, [r4, #44]
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 524              		.loc 1 586 8 view .LVU157
+ 525 010a 22B1     		cbz	r2, .L22
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                   | hadc->Init.ExternalTrigConvEdge
+ 526              		.loc 1 588 7 is_stmt 1 view .LVU158
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                   | hadc->Init.ExternalTrigConvEdge
+ 527              		.loc 1 588 48 is_stmt 0 view .LVU159
+ 528 010c 02F47872 		and	r2, r2, #992
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                  );
+ 529              		.loc 1 589 31 view .LVU160
+ 530 0110 216B     		ldr	r1, [r4, #48]
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                  );
+ 531              		.loc 1 589 19 view .LVU161
+ 532 0112 0A43     		orrs	r2, r2, r1
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                   | hadc->Init.ExternalTrigConvEdge
+ 533              		.loc 1 588 15 view .LVU162
+ 534 0114 1343     		orrs	r3, r3, r2
+ 535              	.LVL40:
+ 536              	.L22:
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 537              		.loc 1 594 5 is_stmt 1 view .LVU163
+ 538 0116 2168     		ldr	r1, [r4]
+ 539 0118 CD68     		ldr	r5, [r1, #12]
+ 540 011a 484A     		ldr	r2, .L38+16
+ 541 011c 2A40     		ands	r2, r2, r5
+ 542 011e 1A43     		orrs	r2, r2, r3
+ 543 0120 CA60     		str	r2, [r1, #12]
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 544              		.loc 1 597 5 view .LVU164
+ 545 0122 2268     		ldr	r2, [r4]
+ 546 0124 1369     		ldr	r3, [r2, #16]
+ 547              	.LVL41:
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 548              		.loc 1 597 5 is_stmt 0 view .LVU165
+ 549 0126 23F04063 		bic	r3, r3, #201326592
+ 550 012a 616B     		ldr	r1, [r4, #52]
+ 551 012c 0B43     		orrs	r3, r3, r1
+ 552 012e 1361     		str	r3, [r2, #16]
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ARM GAS  /tmp/ccICigVb.s 			page 149
+
+
+ 553              		.loc 1 606 5 is_stmt 1 view .LVU166
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 554              		.loc 1 606 46 is_stmt 0 view .LVU167
+ 555 0130 2168     		ldr	r1, [r4]
+ 556              	.LVL42:
+ 557              	.LBB354:
+ 558              	.LBI354:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 559              		.loc 2 6851 26 is_stmt 1 view .LVU168
+ 560              	.LBB355:
+ 561              		.loc 2 6853 3 view .LVU169
+ 562              		.loc 2 6853 12 is_stmt 0 view .LVU170
+ 563 0132 8B68     		ldr	r3, [r1, #8]
+ 564              		.loc 2 6853 74 view .LVU171
+ 565 0134 13F00403 		ands	r3, r3, #4
+ 566 0138 00D0     		beq	.L23
+ 567 013a 0123     		movs	r3, #1
+ 568              	.L23:
+ 569              	.LVL43:
+ 570              		.loc 2 6853 74 view .LVU172
+ 571              	.LBE355:
+ 572              	.LBE354:
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ 573              		.loc 1 607 5 is_stmt 1 view .LVU173
+ 574              	.LBB356:
+ 575              	.LBI356:
+6854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular command of conversion stop state
+6858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
+6859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: no command of conversion stop is on going on ADC group regular.
+6861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+6863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
+6865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Start ADC sampling phase for sampling time trigger mode
+6869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function is relevant only when
+6870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+6871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           using @ref LL_ADC_REG_SetSamplingMode
+6872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+6873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled without conversion on going on group regular,
+6876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without conversion stop command on going on group regular,
+6877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without ADC disable command on going.
+6878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    SWTRIG         LL_ADC_REG_StartSamplingPhase
+6879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
+6883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+ARM GAS  /tmp/ccICigVb.s 			page 150
+
+
+6885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Stop ADC sampling phase for sampling time trigger mode and start conversion
+6889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function is relevant only when
+6890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+6891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           using @ref LL_ADC_REG_SetSamplingMode
+6892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+6893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - @ref LL_ADC_REG_StartSamplingPhase has been called to start
+6894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the sampling phase
+6895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled without conversion on going on group regular,
+6898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without conversion stop command on going on group regular,
+6899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without ADC disable command on going.
+6900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    SWTRIG         LL_ADC_REG_StopSamplingPhase
+6901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
+6905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+6907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion data, range fit for
+6911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         all ADC configurations: all ADC resolutions and
+6912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         all oversampling increased data width (for devices
+6913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         with feature oversampling).
+6914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
+6915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+6917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+6919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+6921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion data, range fit for
+6925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC resolution 12 bits.
+6926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with feature oversampling: Oversampling
+6927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         can increase data width, function for extended range
+6928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+6929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
+6930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+6932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+6934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+6936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion data, range fit for
+6940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC resolution 10 bits.
+6941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with feature oversampling: Oversampling
+ARM GAS  /tmp/ccICigVb.s 			page 151
+
+
+6942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         can increase data width, function for extended range
+6943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+6944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
+6945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+6947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
+6949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+6951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion data, range fit for
+6955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC resolution 8 bits.
+6956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with feature oversampling: Oversampling
+6957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         can increase data width, function for extended range
+6958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+6959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
+6960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+6962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
+6964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+6966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion data, range fit for
+6970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC resolution 6 bits.
+6971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with feature oversampling: Oversampling
+6972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         can increase data width, function for extended range
+6973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+6974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
+6975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+6977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
+6979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+6981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+6984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC multimode conversion data of ADC master, ADC slave
+6986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or raw data with ADC master and slave concatenated.
+6987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If raw data with ADC master and slave concatenated is retrieved,
+6988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a macro is available to get the conversion data of
+6989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC master or ADC slave: see helper macro
+6990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+6991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (however this macro is mainly intended for multimode
+6992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         transfer by DMA, because this function can do the same
+6993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         by getting multimode conversion data of ADC master or ADC slave
+6994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         separately).
+6995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n
+6996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32
+6997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+ARM GAS  /tmp/ccICigVb.s 			page 152
+
+
+6999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ConversionData This parameter can be one of the following values:
+7000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_MASTER
+7001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_SLAVE
+7002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+7003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+7004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uin
+7006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
+7008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              ConversionData)
+7009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                     >> (POSITION_VAL(ConversionData) & 0x1FUL)
+7010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                    );
+7011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+7013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+7016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group inj
+7019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+7020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Start ADC group injected conversion.
+7024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, this function is relevant for both
+7025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal trigger (SW start) and external trigger:
+7026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - If ADC trigger has been set to software start, ADC conversion
+7027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           starts immediately.
+7028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - If ADC trigger has been set to external trigger, ADC conversion
+7029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           will start at next trigger event (on the selected trigger edge)
+7030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           following the ADC start conversion command.
+7031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+7032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+7033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled without conversion on going on group injected,
+7034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without conversion stop command on going on group injected,
+7035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without ADC disable command on going.
+7036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion
+7037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
+7041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+7043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+7044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+7045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+7046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+7047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_JADSTART);
+7048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Stop ADC group injected conversion.
+7052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+7053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+7054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled with conversion on going on group injected,
+7055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without ADC disable command on going.
+ARM GAS  /tmp/ccICigVb.s 			page 153
+
+
+7056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion
+7057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
+7061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+7063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+7064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+7065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+7066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+7067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_JADSTP);
+7068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion state.
+7072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
+7073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: no conversion is on going on ADC group injected.
+7075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
+ 576              		.loc 2 7076 26 view .LVU174
+ 577              	.LBB357:
+7077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
+ 578              		.loc 2 7078 3 view .LVU175
+ 579              		.loc 2 7078 12 is_stmt 0 view .LVU176
+ 580 013c 8A68     		ldr	r2, [r1, #8]
+ 581              		.loc 2 7078 76 view .LVU177
+ 582 013e 12F00802 		ands	r2, r2, #8
+ 583 0142 00D0     		beq	.L24
+ 584 0144 0122     		movs	r2, #1
+ 585              	.L24:
+ 586              	.LVL44:
+ 587              		.loc 2 7078 76 view .LVU178
+ 588              	.LBE357:
+ 589              	.LBE356:
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 590              		.loc 1 608 5 is_stmt 1 view .LVU179
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 591              		.loc 1 608 8 is_stmt 0 view .LVU180
+ 592 0146 43BB     		cbnz	r3, .L25
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        )
+ 593              		.loc 1 609 9 view .LVU181
+ 594 0148 3ABB     		cbnz	r2, .L25
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                  ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
+ 595              		.loc 1 612 7 is_stmt 1 view .LVU182
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                  ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+ 596              		.loc 1 613 18 is_stmt 0 view .LVU183
+ 597 014a 237F     		ldrb	r3, [r4, #28]	@ zero_extendqisi2
+ 598              	.LVL45:
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 599              		.loc 1 614 18 view .LVU184
+ 600 014c 94F83820 		ldrb	r2, [r4, #56]	@ zero_extendqisi2
+ 601              	.LVL46:
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 602              		.loc 1 614 18 view .LVU185
+ARM GAS  /tmp/ccICigVb.s 			page 154
+
+
+ 603 0150 5200     		lsls	r2, r2, #1
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                  ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
+ 604              		.loc 1 612 15 view .LVU186
+ 605 0152 42EA8332 		orr	r2, r2, r3, lsl #14
+ 606              	.LVL47:
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 607              		.loc 1 616 7 is_stmt 1 view .LVU187
+ 608 0156 CB68     		ldr	r3, [r1, #12]
+ 609 0158 23F48043 		bic	r3, r3, #16384
+ 610 015c 23F00203 		bic	r3, r3, #2
+ 611 0160 1343     		orrs	r3, r3, r2
+ 612 0162 CB60     		str	r3, [r1, #12]
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 613              		.loc 1 618 7 view .LVU188
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 614              		.loc 1 618 21 is_stmt 0 view .LVU189
+ 615 0164 2369     		ldr	r3, [r4, #16]
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 616              		.loc 1 618 10 view .LVU190
+ 617 0166 73B3     		cbz	r3, .L26
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
+ 618              		.loc 1 620 9 is_stmt 1 view .LVU191
+ 619 0168 2268     		ldr	r2, [r4]
+ 620              	.LVL48:
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
+ 621              		.loc 1 620 9 is_stmt 0 view .LVU192
+ 622 016a 1369     		ldr	r3, [r2, #16]
+ 623 016c 43F48033 		orr	r3, r3, #65536
+ 624 0170 1361     		str	r3, [r2, #16]
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 625              		.loc 1 621 9 is_stmt 1 view .LVU193
+ 626 0172 2268     		ldr	r2, [r4]
+ 627 0174 D2F8C030 		ldr	r3, [r2, #192]
+ 628 0178 23F47F53 		bic	r3, r3, #16320
+ 629 017c 23F03F03 		bic	r3, r3, #63
+ 630 0180 2169     		ldr	r1, [r4, #16]
+ 631 0182 0B43     		orrs	r3, r3, r1
+ 632 0184 C2F8C030 		str	r3, [r2, #192]
+ 633              	.L27:
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 634              		.loc 1 629 7 view .LVU194
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 635              		.loc 1 629 21 is_stmt 0 view .LVU195
+ 636 0188 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 637              		.loc 1 629 10 view .LVU196
+ 638 018c 012B     		cmp	r3, #1
+ 639 018e 29D0     		beq	.L36
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 640              		.loc 1 656 9 is_stmt 1 view .LVU197
+ 641 0190 2268     		ldr	r2, [r4]
+ 642 0192 1369     		ldr	r3, [r2, #16]
+ 643 0194 23F00103 		bic	r3, r3, #1
+ 644 0198 1361     		str	r3, [r2, #16]
+ 645              	.LVL49:
+ 646              	.L25:
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ARM GAS  /tmp/ccICigVb.s 			page 155
+
+
+ 647              		.loc 1 670 5 view .LVU198
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 648              		.loc 1 670 19 is_stmt 0 view .LVU199
+ 649 019a 6369     		ldr	r3, [r4, #20]
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 650              		.loc 1 670 8 view .LVU200
+ 651 019c 012B     		cmp	r3, #1
+ 652 019e 33D0     		beq	.L37
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 653              		.loc 1 677 7 is_stmt 1 view .LVU201
+ 654 01a0 2268     		ldr	r2, [r4]
+ 655 01a2 136B     		ldr	r3, [r2, #48]
+ 656 01a4 23F00F03 		bic	r3, r3, #15
+ 657 01a8 1363     		str	r3, [r2, #48]
+ 658              	.L30:
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 659              		.loc 1 682 5 view .LVU202
+ 660 01aa E36D     		ldr	r3, [r4, #92]
+ 661 01ac 23F00303 		bic	r3, r3, #3
+ 662 01b0 43F00103 		orr	r3, r3, #1
+ 663 01b4 E365     		str	r3, [r4, #92]
+ 664 01b6 35E0     		b	.L9
+ 665              	.LVL50:
+ 666              	.L32:
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpCFGR;
+ 667              		.loc 1 397 21 is_stmt 0 view .LVU203
+ 668 01b8 0020     		movs	r0, #0
+ 669 01ba 6AE7     		b	.L15
+ 670              	.LVL51:
+ 671              	.L35:
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 672              		.loc 1 578 7 is_stmt 1 view .LVU204
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 673              		.loc 1 578 18 is_stmt 0 view .LVU205
+ 674 01bc A26A     		ldr	r2, [r4, #40]
+ 675 01be 013A     		subs	r2, r2, #1
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 676              		.loc 1 578 15 view .LVU206
+ 677 01c0 43EA4243 		orr	r3, r3, r2, lsl #17
+ 678              	.LVL52:
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 679              		.loc 1 578 15 view .LVU207
+ 680 01c4 A0E7     		b	.L21
+ 681              	.LVL53:
+ 682              	.L26:
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
+ 683              		.loc 1 625 9 is_stmt 1 view .LVU208
+ 684 01c6 2268     		ldr	r2, [r4]
+ 685              	.LVL54:
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
+ 686              		.loc 1 625 9 is_stmt 0 view .LVU209
+ 687 01c8 1369     		ldr	r3, [r2, #16]
+ 688 01ca 23F48033 		bic	r3, r3, #65536
+ 689 01ce 1361     		str	r3, [r2, #16]
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 690              		.loc 1 626 9 is_stmt 1 view .LVU210
+ 691 01d0 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/ccICigVb.s 			page 156
+
+
+ 692 01d2 D2F8C030 		ldr	r3, [r2, #192]
+ 693 01d6 23F47F53 		bic	r3, r3, #16320
+ 694 01da 23F03F03 		bic	r3, r3, #63
+ 695 01de C2F8C030 		str	r3, [r2, #192]
+ 696 01e2 D1E7     		b	.L27
+ 697              	.L36:
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
+ 698              		.loc 1 631 9 view .LVU211
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
+ 699              		.loc 1 632 9 view .LVU212
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
+ 700              		.loc 1 633 9 view .LVU213
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 701              		.loc 1 634 9 view .LVU214
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                    ADC_CFGR2_OVSR  |
+ 702              		.loc 1 641 9 view .LVU215
+ 703 01e4 2168     		ldr	r1, [r4]
+ 704 01e6 0B69     		ldr	r3, [r1, #16]
+ 705 01e8 23F4FF63 		bic	r3, r3, #2040
+ 706 01ec 23F00403 		bic	r3, r3, #4
+ 707 01f0 626C     		ldr	r2, [r4, #68]
+ 708 01f2 A56C     		ldr	r5, [r4, #72]
+ 709 01f4 2A43     		orrs	r2, r2, r5
+ 710 01f6 E56C     		ldr	r5, [r4, #76]
+ 711 01f8 2A43     		orrs	r2, r2, r5
+ 712 01fa 256D     		ldr	r5, [r4, #80]
+ 713 01fc 2A43     		orrs	r2, r2, r5
+ 714 01fe 1343     		orrs	r3, r3, r2
+ 715 0200 43F00103 		orr	r3, r3, #1
+ 716 0204 0B61     		str	r3, [r1, #16]
+ 717 0206 C8E7     		b	.L25
+ 718              	.LVL55:
+ 719              	.L37:
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 720              		.loc 1 673 7 view .LVU216
+ 721 0208 2168     		ldr	r1, [r4]
+ 722 020a 0B6B     		ldr	r3, [r1, #48]
+ 723 020c 23F00F03 		bic	r3, r3, #15
+ 724 0210 226A     		ldr	r2, [r4, #32]
+ 725 0212 013A     		subs	r2, r2, #1
+ 726 0214 1343     		orrs	r3, r3, r2
+ 727 0216 0B63     		str	r3, [r1, #48]
+ 728 0218 C7E7     		b	.L30
+ 729              	.LVL56:
+ 730              	.L17:
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 731              		.loc 1 687 5 view .LVU217
+ 732 021a E36D     		ldr	r3, [r4, #92]
+ 733              	.LVL57:
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 734              		.loc 1 687 5 is_stmt 0 view .LVU218
+ 735 021c 43F01003 		orr	r3, r3, #16
+ 736 0220 E365     		str	r3, [r4, #92]
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 737              		.loc 1 689 5 is_stmt 1 view .LVU219
+ 738              	.LVL58:
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ARM GAS  /tmp/ccICigVb.s 			page 157
+
+
+ 739              		.loc 1 689 20 is_stmt 0 view .LVU220
+ 740 0222 0120     		movs	r0, #1
+ 741              	.LVL59:
+ 742              	.L9:
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 743              		.loc 1 694 1 view .LVU221
+ 744 0224 03B0     		add	sp, sp, #12
+ 745              	.LCFI7:
+ 746              		.cfi_remember_state
+ 747              		.cfi_def_cfa_offset 12
+ 748              		@ sp needed
+ 749 0226 30BD     		pop	{r4, r5, pc}
+ 750              	.LVL60:
+ 751              	.L31:
+ 752              	.LCFI8:
+ 753              		.cfi_restore_state
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 754              		.loc 1 407 12 view .LVU222
+ 755 0228 0120     		movs	r0, #1
+ 756              	.LVL61:
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 757              		.loc 1 407 12 view .LVU223
+ 758 022a FBE7     		b	.L9
+ 759              	.L39:
+ 760              		.align	2
+ 761              	.L38:
+ 762 022c 00000000 		.word	SystemCoreClock
+ 763 0230 632D3E05 		.word	87960931
+ 764 0234 00010050 		.word	1342177536
+ 765 0238 00030050 		.word	1342178048
+ 766 023c 0740F0FF 		.word	-1032185
+ 767              		.cfi_endproc
+ 768              	.LFE329:
+ 770              		.section	.text.HAL_ADC_MspDeInit,"ax",%progbits
+ 771              		.align	1
+ 772              		.weak	HAL_ADC_MspDeInit
+ 773              		.syntax unified
+ 774              		.thumb
+ 775              		.thumb_func
+ 777              	HAL_ADC_MspDeInit:
+ 778              	.LVL62:
+ 779              	.LFB332:
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  DeInitialize the ADC MSP.
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   All ADC instances use the same core clock at RCC level, disabling
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         the core clock reset all ADC instances).
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval None
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 780              		.loc 1 931 1 is_stmt 1 view -0
+ 781              		.cfi_startproc
+ 782              		@ args = 0, pretend = 0, frame = 0
+ 783              		@ frame_needed = 0, uses_anonymous_args = 0
+ 784              		@ link register save eliminated.
+ARM GAS  /tmp/ccICigVb.s 			page 158
+
+
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   UNUSED(hadc);
+ 785              		.loc 1 933 3 view .LVU225
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* NOTE : This function should not be modified. When the callback is needed,
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             function HAL_ADC_MspDeInit must be implemented in the user file.
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****    */
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 786              		.loc 1 938 1 is_stmt 0 view .LVU226
+ 787 0000 7047     		bx	lr
+ 788              		.cfi_endproc
+ 789              	.LFE332:
+ 791              		.section	.text.HAL_ADC_PollForConversion,"ax",%progbits
+ 792              		.align	1
+ 793              		.global	HAL_ADC_PollForConversion
+ 794              		.syntax unified
+ 795              		.thumb
+ 796              		.thumb_func
+ 798              	HAL_ADC_PollForConversion:
+ 799              	.LVL63:
+ 800              	.LFB335:
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Register a User ADC Callback
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         To be used instead of the weak predefined callback
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *                the configuration information for the specified ADC.
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param  CallbackID ID of the callback to be registered
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         This parameter can be one of the following values:
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer call
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complet
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue over
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param  pCallback pointer to the Callback function
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef Callb
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                            pADC_CallbackTypeDef pCallback)
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (pCallback == NULL)
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Update the error code */
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     return HAL_ERROR;
+ARM GAS  /tmp/ccICigVb.s 			page 159
+
+
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     switch (CallbackID)
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->ConvCpltCallback = pCallback;
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_CONVERSION_HALF_CB_ID :
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->ConvHalfCpltCallback = pCallback;
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->LevelOutOfWindowCallback = pCallback;
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_ERROR_CB_ID :
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->ErrorCallback = pCallback;
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->InjectedConvCpltCallback = pCallback;
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->InjectedQueueOverflowCallback = pCallback;
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->LevelOutOfWindow2Callback = pCallback;
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->LevelOutOfWindow3Callback = pCallback;
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_END_OF_SAMPLING_CB_ID :
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->EndOfSamplingCallback = pCallback;
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_MSPINIT_CB_ID :
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->MspInitCallback = pCallback;
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_MSPDEINIT_CB_ID :
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->MspDeInitCallback = pCallback;
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       default :
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Update the error code */
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Return error status */
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         status = HAL_ERROR;
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+ARM GAS  /tmp/ccICigVb.s 			page 160
+
+
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else if (HAL_ADC_STATE_RESET == hadc->State)
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     switch (CallbackID)
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_MSPINIT_CB_ID :
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->MspInitCallback = pCallback;
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_MSPDEINIT_CB_ID :
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->MspDeInitCallback = pCallback;
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       default :
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Update the error code */
+1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Return error status */
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         status = HAL_ERROR;
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Update the error code */
+1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Return error status */
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     status =  HAL_ERROR;
+1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return status;
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Unregister a ADC Callback
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         ADC callback is redirected to the weak predefined callback
+1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *                the configuration information for the specified ADC.
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param  CallbackID ID of the callback to be unregistered
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         This parameter can be one of the following values:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer call
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complet
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue over
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+ARM GAS  /tmp/ccICigVb.s 			page 161
+
+
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef Cal
+1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef status = HAL_OK;
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     switch (CallbackID)
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_CONVERSION_HALF_CB_ID :
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+1107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_ERROR_CB_ID :
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+1111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
+1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+1126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
+1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_END_OF_SAMPLING_CB_ID :
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
+1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_MSPINIT_CB_ID :
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_MSPDEINIT_CB_ID :
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
+1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       default :
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Update the error code */
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Return error status */
+ARM GAS  /tmp/ccICigVb.s 			page 162
+
+
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         status =  HAL_ERROR;
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else if (HAL_ADC_STATE_RESET == hadc->State)
+1151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     switch (CallbackID)
+1153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_MSPINIT_CB_ID :
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit          
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case HAL_ADC_MSPDEINIT_CB_ID :
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit        
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       default :
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Update the error code */
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Return error status */
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         status =  HAL_ERROR;
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Update the error code */
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Return error status */
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     status =  HAL_ERROR;
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return status;
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+1182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @}
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief    ADC IO operation functions
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** @verbatim
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****  ===============================================================================
+1194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                       ##### IO operation functions #####
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****  ===============================================================================
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     [..]  This section provides functions allowing to:
+1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Start conversion of regular group.
+1198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Stop conversion of regular group.
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Poll for conversion complete on regular group.
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Poll for conversion event.
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Get result of regular channel conversion.
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Start conversion of regular group and enable interruptions.
+ARM GAS  /tmp/ccICigVb.s 			page 163
+
+
+1203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Stop conversion of regular group and disable interruptions.
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Handle ADC interrupt request
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Start conversion of regular group and enable DMA transfer.
+1206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Stop conversion of regular group and disable ADC DMA transfer.
+1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** @endverbatim
+1208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @{
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+1210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Enable ADC, start conversion of regular group.
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Interruptions enabled in this function: None.
+1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Case of multimode enabled (when multimode feature is available):
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *           if ADC is Slave, ADC is enabled but conversion is not started,
+1216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *           if ADC is master, ADC is enabled and multimode conversion is started.
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status
+1219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+1223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   const ADC_TypeDef *tmpADC_Master;
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+1226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Perform ADC enable and conversion start if no conversion is on going */
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Process locked */
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_LOCK(hadc);
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Enable the ADC peripheral */
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_hal_status = ADC_Enable(hadc);
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Start conversion if ADC is effectively enabled */
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (tmp_hal_status == HAL_OK)
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state                                                        */
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* - Clear state bitfield related to regular group conversion results   */
+1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* - Set state bitfield related to regular operation                    */
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       ADC_STATE_CLR_SET(hadc->State,
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_A
+1248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_REG_BUSY);
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+1251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+1252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         - if ADC instance is master or if multimode feature is not available
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         - if multimode setting is disabled (ADC instance slave in independent mode) */
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          )
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ARM GAS  /tmp/ccICigVb.s 			page 164
+
+
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC error code */
+1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Check if a conversion is on going on ADC group injected */
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Reset ADC error code fields related to regular conversions only */
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Reset all ADC error code fields */
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         ADC_CLEAR_ERRORCODE(hadc);
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Clear ADC group regular conversion flag and overrun flag               */
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* (To ensure of no unknown state from potential previous ADC operations) */
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Process unlocked */
+1280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Unlock before starting ADC conversions: in case of potential         */
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* interruption, to let the process to ADC IRQ Handler.                 */
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_UNLOCK(hadc);
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Enable conversion of regular group.                                  */
+1285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* If software start has been selected, conversion starts immediately.  */
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* If external trigger has been selected, conversion will start at next */
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* trigger event.                                                       */
+1288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Case of multimode enabled (when multimode feature is available):     */
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*    enabled only (conversion is not started),                         */
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*  - if ADC is master, ADC is enabled and conversion is started.       */
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          )
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* ADC instance is not a multimode slave instance with multimode regular conversions enable
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+1302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+1304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Start ADC group regular conversion */
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_REG_StartConversion(hadc->Instance);
+1307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* if Master ADC JAUTO bit is set, update Slave State in setting
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
+1316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ARM GAS  /tmp/ccICigVb.s 			page 165
+
+
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+1319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+1323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+1325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Start ADC group regular conversion */
+1328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       LL_ADC_REG_StartConversion(hadc->Instance);
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Process unlocked */
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_UNLOCK(hadc);
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else
+1338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_hal_status = HAL_BUSY;
+1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return tmp_hal_status;
+1344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Stop ADC conversion of regular group (and injected channels in
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         case of auto_injection mode), disable ADC peripheral.
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note:  ADC peripheral disable is forcing stop of potential
+1350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         conversion on injected group. If injected group is under use, it
+1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+1353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status.
+1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+1358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Process locked */
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_LOCK(hadc);
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Disable ADC peripheral if conversions are effectively stopped */
+1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (tmp_hal_status == HAL_OK)
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* 2. Disable the ADC peripheral */
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_hal_status = ADC_Disable(hadc);
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ARM GAS  /tmp/ccICigVb.s 			page 166
+
+
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check if ADC is effectively disabled */
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (tmp_hal_status == HAL_OK)
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state */
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       ADC_STATE_CLR_SET(hadc->State,
+1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_READY);
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Process unlocked */
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return tmp_hal_status;
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+1390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+1392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Wait for regular group conversion to be completed.
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
+1394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         conversion) are cleared by this function, with an exception:
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         if low power feature "LowPowerAutoWait" is enabled, flags are
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         not cleared to not interfere with this feature until data register
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         is read using function HAL_ADC_GetValue().
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   This function cannot be used in a particular setup: ADC configured
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         in DMA mode and polling for end of each conversion (ADC init
+1400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+1401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         In this case, DMA resets the flag EOC and polling cannot be
+1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         performed on each conversion. Nevertheless, polling can still
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         be performed on the complete sequence (ADC init
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+1405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+1406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param Timeout Timeout value in millisecond.
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status
+1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 801              		.loc 1 1410 1 is_stmt 1 view -0
+ 802              		.cfi_startproc
+ 803              		@ args = 0, pretend = 0, frame = 0
+ 804              		@ frame_needed = 0, uses_anonymous_args = 0
+ 805              		.loc 1 1410 1 is_stmt 0 view .LVU228
+ 806 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 807              	.LCFI9:
+ 808              		.cfi_def_cfa_offset 24
+ 809              		.cfi_offset 4, -24
+ 810              		.cfi_offset 5, -20
+ 811              		.cfi_offset 6, -16
+ 812              		.cfi_offset 7, -12
+ 813              		.cfi_offset 8, -8
+ 814              		.cfi_offset 14, -4
+ 815 0004 0446     		mov	r4, r0
+ 816 0006 0E46     		mov	r6, r1
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tickstart;
+ 817              		.loc 1 1411 3 is_stmt 1 view .LVU229
+1412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_Flag_End;
+ 818              		.loc 1 1412 3 view .LVU230
+ARM GAS  /tmp/ccICigVb.s 			page 167
+
+
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_cfgr;
+ 819              		.loc 1 1413 3 view .LVU231
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+1415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   const ADC_TypeDef *tmpADC_Master;
+ 820              		.loc 1 1415 3 view .LVU232
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+ 821              		.loc 1 1416 3 view .LVU233
+ 822              	.LVL64:
+ 823              	.LBB358:
+ 824              	.LBI358:
+6392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 825              		.loc 2 6392 26 view .LVU234
+ 826              	.LBB359:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 827              		.loc 2 6394 3 view .LVU235
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 828              		.loc 2 6394 21 is_stmt 0 view .LVU236
+ 829 0008 424B     		ldr	r3, .L66
+ 830 000a 9F68     		ldr	r7, [r3, #8]
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 831              		.loc 2 6394 10 view .LVU237
+ 832 000c 07F01F07 		and	r7, r7, #31
+ 833              	.LVL65:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 834              		.loc 2 6394 10 view .LVU238
+ 835              	.LBE359:
+ 836              	.LBE358:
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 837              		.loc 1 1420 3 is_stmt 1 view .LVU239
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* If end of conversion selected to end of sequence conversions */
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ 838              		.loc 1 1423 3 view .LVU240
+ 839              		.loc 1 1423 17 is_stmt 0 view .LVU241
+ 840 0010 8569     		ldr	r5, [r0, #24]
+ 841              		.loc 1 1423 6 view .LVU242
+ 842 0012 082D     		cmp	r5, #8
+ 843 0014 14D0     		beq	.L42
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_Flag_End = ADC_FLAG_EOS;
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* If end of conversion selected to end of unitary conversion */
+1428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else /* ADC_EOC_SINGLE_CONV */
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Verification that ADC configuration is compliant with polling for      */
+1431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* each conversion:                                                       */
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
+1433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* several ranks and polling for end of each conversion.                  */
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* For code simplicity sake, this particular case is generalized to       */
+1435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* ADC configured in DMA mode and and polling for end of each conversion. */
+1436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+1437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 844              		.loc 1 1437 5 is_stmt 1 view .LVU243
+ 845 0016 092F     		cmp	r7, #9
+ARM GAS  /tmp/ccICigVb.s 			page 168
+
+
+ 846 0018 05D8     		bhi	.L43
+ 847 001a 40F22123 		movw	r3, #545
+ 848 001e FB40     		lsrs	r3, r3, r7
+ 849 0020 13F0010F 		tst	r3, #1
+ 850 0024 06D1     		bne	.L60
+ 851              	.L43:
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+1439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+1440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        )
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Check ADC DMA mode in independent mode on ADC group regular */
+1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
+1444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         return HAL_ERROR;
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         tmp_Flag_End = (ADC_FLAG_EOC);
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+1454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Check ADC DMA mode in multimode on ADC group regular */
+1456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_
+ 852              		.loc 1 1456 7 view .LVU244
+ 853              	.LVL66:
+ 854              	.LBB360:
+ 855              	.LBI360:
+6489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 856              		.loc 2 6489 26 view .LVU245
+ 857              	.LBB361:
+6491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 858              		.loc 2 6491 3 view .LVU246
+6491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 859              		.loc 2 6491 21 is_stmt 0 view .LVU247
+ 860 0026 3B4B     		ldr	r3, .L66
+ 861 0028 9B68     		ldr	r3, [r3, #8]
+ 862              	.LVL67:
+6491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 863              		.loc 2 6491 21 view .LVU248
+ 864              	.LBE361:
+ 865              	.LBE360:
+ 866              		.loc 1 1456 10 view .LVU249
+ 867 002a 13F4604F 		tst	r3, #57344
+ 868 002e 2CD1     		bne	.L61
+1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+1459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         return HAL_ERROR;
+1460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+1462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         tmp_Flag_End = (ADC_FLAG_EOC);
+ 869              		.loc 1 1463 22 view .LVU250
+ 870 0030 0425     		movs	r5, #4
+ 871 0032 05E0     		b	.L42
+ 872              	.L60:
+ARM GAS  /tmp/ccICigVb.s 			page 169
+
+
+1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 873              		.loc 1 1443 7 is_stmt 1 view .LVU251
+1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 874              		.loc 1 1443 11 is_stmt 0 view .LVU252
+ 875 0034 0368     		ldr	r3, [r0]
+ 876 0036 DB68     		ldr	r3, [r3, #12]
+1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 877              		.loc 1 1443 10 view .LVU253
+ 878 0038 13F0010F 		tst	r3, #1
+ 879 003c 1FD1     		bne	.L62
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 880              		.loc 1 1450 22 view .LVU254
+ 881 003e 0425     		movs	r5, #4
+ 882              	.L42:
+ 883              	.LVL68:
+1464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check ADC DMA mode */
+1468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
+1469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       return HAL_ERROR;
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmp_Flag_End = (ADC_FLAG_EOC);
+1476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Get tick count */
+1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tickstart = HAL_GetTick();
+ 884              		.loc 1 1481 3 is_stmt 1 view .LVU255
+ 885              		.loc 1 1481 15 is_stmt 0 view .LVU256
+ 886 0040 FFF7FEFF 		bl	HAL_GetTick
+ 887              	.LVL69:
+ 888              		.loc 1 1481 15 view .LVU257
+ 889 0044 8046     		mov	r8, r0
+ 890              	.LVL70:
+1482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Wait until End of unitary conversion or sequence conversions flag is raised */
+1484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ 891              		.loc 1 1484 3 is_stmt 1 view .LVU258
+ 892              	.L46:
+ 893              		.loc 1 1484 47 view .LVU259
+ 894              		.loc 1 1484 15 is_stmt 0 view .LVU260
+ 895 0046 2368     		ldr	r3, [r4]
+ 896              		.loc 1 1484 25 view .LVU261
+ 897 0048 1A68     		ldr	r2, [r3]
+ 898              		.loc 1 1484 47 view .LVU262
+ 899 004a 2A42     		tst	r2, r5
+ 900 004c 23D1     		bne	.L63
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check if timeout is disabled (set to infinite wait) */
+1487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (Timeout != HAL_MAX_DELAY)
+ 901              		.loc 1 1487 5 is_stmt 1 view .LVU263
+ARM GAS  /tmp/ccICigVb.s 			page 170
+
+
+ 902              		.loc 1 1487 8 is_stmt 0 view .LVU264
+ 903 004e B6F1FF3F 		cmp	r6, #-1
+ 904 0052 F8D0     		beq	.L46
+1488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ 905              		.loc 1 1489 7 is_stmt 1 view .LVU265
+ 906              		.loc 1 1489 13 is_stmt 0 view .LVU266
+ 907 0054 FFF7FEFF 		bl	HAL_GetTick
+ 908              	.LVL71:
+ 909              		.loc 1 1489 27 view .LVU267
+ 910 0058 A0EB0800 		sub	r0, r0, r8
+ 911              		.loc 1 1489 10 view .LVU268
+ 912 005c B042     		cmp	r0, r6
+ 913 005e 01D8     		bhi	.L47
+ 914              		.loc 1 1489 51 discriminator 1 view .LVU269
+ 915 0060 002E     		cmp	r6, #0
+ 916 0062 F0D1     		bne	.L46
+ 917              	.L47:
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* New check to avoid false timeout detection in case of preemption */
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ 918              		.loc 1 1492 9 is_stmt 1 view .LVU270
+ 919              		.loc 1 1492 18 is_stmt 0 view .LVU271
+ 920 0064 2368     		ldr	r3, [r4]
+ 921              		.loc 1 1492 28 view .LVU272
+ 922 0066 1B68     		ldr	r3, [r3]
+ 923              		.loc 1 1492 12 view .LVU273
+ 924 0068 2B42     		tst	r3, r5
+ 925 006a ECD1     		bne	.L46
+1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+1494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Update ADC state machine to timeout */
+1495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ 926              		.loc 1 1495 11 is_stmt 1 view .LVU274
+ 927 006c E36D     		ldr	r3, [r4, #92]
+ 928 006e 43F00403 		orr	r3, r3, #4
+ 929 0072 E365     		str	r3, [r4, #92]
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Process unlocked */
+1498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           __HAL_UNLOCK(hadc);
+ 930              		.loc 1 1498 11 view .LVU275
+ 931              		.loc 1 1498 11 view .LVU276
+ 932 0074 0023     		movs	r3, #0
+ 933 0076 84F85830 		strb	r3, [r4, #88]
+ 934              		.loc 1 1498 11 view .LVU277
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           return HAL_TIMEOUT;
+ 935              		.loc 1 1500 11 view .LVU278
+ 936              		.loc 1 1500 18 is_stmt 0 view .LVU279
+ 937 007a 0320     		movs	r0, #3
+ 938 007c 45E0     		b	.L44
+ 939              	.LVL72:
+ 940              	.L62:
+1445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         return HAL_ERROR;
+ 941              		.loc 1 1445 9 is_stmt 1 view .LVU280
+ 942 007e C36D     		ldr	r3, [r0, #92]
+ 943 0080 43F02003 		orr	r3, r3, #32
+ 944 0084 C365     		str	r3, [r0, #92]
+ARM GAS  /tmp/ccICigVb.s 			page 171
+
+
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 945              		.loc 1 1446 9 view .LVU281
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 946              		.loc 1 1446 16 is_stmt 0 view .LVU282
+ 947 0086 0120     		movs	r0, #1
+ 948              	.LVL73:
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 949              		.loc 1 1446 16 view .LVU283
+ 950 0088 3FE0     		b	.L44
+ 951              	.LVL74:
+ 952              	.L61:
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         return HAL_ERROR;
+ 953              		.loc 1 1458 9 is_stmt 1 view .LVU284
+ 954 008a E36D     		ldr	r3, [r4, #92]
+ 955 008c 43F02003 		orr	r3, r3, #32
+ 956 0090 E365     		str	r3, [r4, #92]
+1459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 957              		.loc 1 1459 9 view .LVU285
+1459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 958              		.loc 1 1459 16 is_stmt 0 view .LVU286
+ 959 0092 0120     		movs	r0, #1
+ 960              	.LVL75:
+1459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 961              		.loc 1 1459 16 view .LVU287
+ 962 0094 39E0     		b	.L44
+ 963              	.LVL76:
+ 964              	.L63:
+1501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Update ADC state machine */
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ 965              		.loc 1 1507 3 is_stmt 1 view .LVU288
+ 966 0096 E26D     		ldr	r2, [r4, #92]
+ 967 0098 42F40072 		orr	r2, r2, #512
+ 968 009c E265     		str	r2, [r4, #92]
+1508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Determine whether any further conversion upcoming on group regular       */
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* by external trigger, continuous mode or scan sequence on going.          */
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ 969              		.loc 1 1511 3 view .LVU289
+ 970              	.LVL77:
+ 971              	.LBB362:
+ 972              	.LBI362:
+3747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 973              		.loc 2 3747 26 view .LVU290
+ 974              	.LBB363:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 975              		.loc 2 3749 3 view .LVU291
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 976              		.loc 2 3749 12 is_stmt 0 view .LVU292
+ 977 009e DA68     		ldr	r2, [r3, #12]
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 978              		.loc 2 3749 103 view .LVU293
+ 979 00a0 12F4406F 		tst	r2, #3072
+ARM GAS  /tmp/ccICigVb.s 			page 172
+
+
+ 980 00a4 11D1     		bne	.L49
+ 981              	.LVL78:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 982              		.loc 2 3749 103 view .LVU294
+ 983              	.LBE363:
+ 984              	.LBE362:
+1512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       && (hadc->Init.ContinuousConvMode == DISABLE)
+ 985              		.loc 1 1512 21 view .LVU295
+ 986 00a6 627F     		ldrb	r2, [r4, #29]	@ zero_extendqisi2
+ 987              		.loc 1 1512 7 view .LVU296
+ 988 00a8 7AB9     		cbnz	r2, .L49
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      )
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check whether end of sequence is reached */
+1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+ 989              		.loc 1 1516 5 is_stmt 1 view .LVU297
+ 990              		.loc 1 1516 9 is_stmt 0 view .LVU298
+ 991 00aa 1A68     		ldr	r2, [r3]
+ 992              		.loc 1 1516 8 view .LVU299
+ 993 00ac 12F0080F 		tst	r2, #8
+ 994 00b0 0BD0     		beq	.L49
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state */
+1519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ 995              		.loc 1 1519 7 is_stmt 1 view .LVU300
+ 996 00b2 E26D     		ldr	r2, [r4, #92]
+ 997 00b4 22F48072 		bic	r2, r2, #256
+ 998 00b8 E265     		str	r2, [r4, #92]
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ 999              		.loc 1 1521 7 view .LVU301
+ 1000              		.loc 1 1521 16 is_stmt 0 view .LVU302
+ 1001 00ba E26D     		ldr	r2, [r4, #92]
+ 1002              		.loc 1 1521 10 view .LVU303
+ 1003 00bc 12F4805F 		tst	r2, #4096
+ 1004 00c0 03D1     		bne	.L49
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ 1005              		.loc 1 1523 9 is_stmt 1 view .LVU304
+ 1006 00c2 E26D     		ldr	r2, [r4, #92]
+ 1007 00c4 42F00102 		orr	r2, r2, #1
+ 1008 00c8 E265     		str	r2, [r4, #92]
+ 1009              	.L49:
+1524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Get relevant register CFGR in ADC instance of ADC master or slave        */
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* in function of multimode state (for devices with multimode               */
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* available).                                                              */
+1531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ 1010              		.loc 1 1532 3 view .LVU305
+ 1011              		.loc 1 1532 8 is_stmt 0 view .LVU306
+ 1012 00ca 134A     		ldr	r2, .L66+4
+ 1013 00cc 9342     		cmp	r3, r2
+ 1014 00ce 0CD0     		beq	.L64
+ARM GAS  /tmp/ccICigVb.s 			page 173
+
+
+ 1015 00d0 1A46     		mov	r2, r3
+ 1016              	.L50:
+ 1017              		.loc 1 1532 6 discriminator 4 view .LVU307
+ 1018 00d2 9342     		cmp	r3, r2
+ 1019 00d4 0CD0     		beq	.L51
+ 1020 00d6 092F     		cmp	r7, #9
+ 1021 00d8 05D8     		bhi	.L52
+ 1022 00da 40F22121 		movw	r1, #545
+ 1023 00de F940     		lsrs	r1, r1, r7
+ 1024 00e0 11F0010F 		tst	r1, #1
+ 1025 00e4 04D1     		bne	.L51
+ 1026              	.L52:
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+1536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      )
+1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Retrieve handle ADC CFGR register */
+1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Retrieve Master ADC CFGR register */
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ 1027              		.loc 1 1544 5 is_stmt 1 discriminator 4 view .LVU308
+ 1028              	.LVL79:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+ 1029              		.loc 1 1545 5 discriminator 4 view .LVU309
+ 1030              		.loc 1 1545 14 is_stmt 0 discriminator 4 view .LVU310
+ 1031 00e6 D268     		ldr	r2, [r2, #12]
+ 1032              	.LVL80:
+ 1033              		.loc 1 1545 14 discriminator 4 view .LVU311
+ 1034 00e8 03E0     		b	.L53
+ 1035              	.LVL81:
+ 1036              	.L64:
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1037              		.loc 1 1532 8 view .LVU312
+ 1038 00ea 4FF0A042 		mov	r2, #1342177280
+ 1039 00ee F0E7     		b	.L50
+ 1040              	.L51:
+1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 1041              		.loc 1 1539 5 is_stmt 1 view .LVU313
+1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 1042              		.loc 1 1539 14 is_stmt 0 view .LVU314
+ 1043 00f0 DA68     		ldr	r2, [r3, #12]
+ 1044              	.LVL82:
+ 1045              	.L53:
+1546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Retrieve handle ADC CFGR register */
+1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+1550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Clear polled flag */
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (tmp_Flag_End == ADC_FLAG_EOS)
+ 1046              		.loc 1 1553 3 is_stmt 1 view .LVU315
+ 1047              		.loc 1 1553 6 is_stmt 0 view .LVU316
+ARM GAS  /tmp/ccICigVb.s 			page 174
+
+
+ 1048 00f2 082D     		cmp	r5, #8
+ 1049 00f4 06D0     		beq	.L65
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
+1556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else
+1558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Clear end of conversion EOC flag of regular group if low power feature */
+1560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* "LowPowerAutoWait " is disabled, to not interfere with this feature    */
+1561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* until data register is read using function HAL_ADC_GetValue().         */
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
+ 1050              		.loc 1 1562 5 is_stmt 1 view .LVU317
+ 1051              		.loc 1 1562 8 is_stmt 0 view .LVU318
+ 1052 00f6 12F4804F 		tst	r2, #16384
+ 1053 00fa 08D1     		bne	.L58
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ 1054              		.loc 1 1564 7 is_stmt 1 view .LVU319
+ 1055 00fc 0C22     		movs	r2, #12
+ 1056              	.LVL83:
+ 1057              		.loc 1 1564 7 is_stmt 0 view .LVU320
+ 1058 00fe 1A60     		str	r2, [r3]
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return HAL_OK;
+ 1059              		.loc 1 1569 10 view .LVU321
+ 1060 0100 0020     		movs	r0, #0
+ 1061 0102 02E0     		b	.L44
+ 1062              	.LVL84:
+ 1063              	.L65:
+1555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 1064              		.loc 1 1555 5 is_stmt 1 view .LVU322
+ 1065 0104 0822     		movs	r2, #8
+ 1066              	.LVL85:
+1555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 1067              		.loc 1 1555 5 is_stmt 0 view .LVU323
+ 1068 0106 1A60     		str	r2, [r3]
+ 1069              		.loc 1 1569 10 view .LVU324
+ 1070 0108 0020     		movs	r0, #0
+ 1071              	.LVL86:
+ 1072              	.L44:
+1570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1073              		.loc 1 1570 1 view .LVU325
+ 1074 010a BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 1075              	.LVL87:
+ 1076              	.L58:
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1077              		.loc 1 1569 10 view .LVU326
+ 1078 010e 0020     		movs	r0, #0
+ 1079 0110 FBE7     		b	.L44
+ 1080              	.L67:
+ 1081 0112 00BF     		.align	2
+ 1082              	.L66:
+ 1083 0114 00030050 		.word	1342178048
+ 1084 0118 00010050 		.word	1342177536
+ARM GAS  /tmp/ccICigVb.s 			page 175
+
+
+ 1085              		.cfi_endproc
+ 1086              	.LFE335:
+ 1088              		.section	.text.HAL_ADC_PollForEvent,"ax",%progbits
+ 1089              		.align	1
+ 1090              		.global	HAL_ADC_PollForEvent
+ 1091              		.syntax unified
+ 1092              		.thumb
+ 1093              		.thumb_func
+ 1095              	HAL_ADC_PollForEvent:
+ 1096              	.LVL88:
+ 1097              	.LFB336:
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+1573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Poll for ADC event.
+1574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+1575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param EventType the ADC event type.
+1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          This parameter can be one of the following values:
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *            @arg @ref ADC_AWD1_EVENT   ADC Analog watchdog 1 event (main analog watchdog, presen
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event (additional analog watchdog, 
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event (additional analog watchdog, 
+1581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *            @arg @ref ADC_JQOVF_EVENT  ADC Injected context queue overflow event
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param Timeout Timeout value in millisecond.
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         Indeed, the latter is reset only if hadc->Init.Overrun field is set
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
+1587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         by a new converted data as soon as OVR is cleared.
+1588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         To reset OVR flag once the preserved data is retrieved, the user can resort
+1589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+1590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status
+1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeou
+1593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 1098              		.loc 1 1593 1 is_stmt 1 view -0
+ 1099              		.cfi_startproc
+ 1100              		@ args = 0, pretend = 0, frame = 0
+ 1101              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1102              		.loc 1 1593 1 is_stmt 0 view .LVU328
+ 1103 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 1104              	.LCFI10:
+ 1105              		.cfi_def_cfa_offset 24
+ 1106              		.cfi_offset 4, -24
+ 1107              		.cfi_offset 5, -20
+ 1108              		.cfi_offset 6, -16
+ 1109              		.cfi_offset 7, -12
+ 1110              		.cfi_offset 8, -8
+ 1111              		.cfi_offset 14, -4
+ 1112 0004 0646     		mov	r6, r0
+ 1113 0006 0D46     		mov	r5, r1
+ 1114 0008 1746     		mov	r7, r2
+1594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tickstart;
+ 1115              		.loc 1 1594 3 is_stmt 1 view .LVU329
+1595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 1116              		.loc 1 1597 3 view .LVU330
+ARM GAS  /tmp/ccICigVb.s 			page 176
+
+
+1598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_EVENT_TYPE(EventType));
+ 1117              		.loc 1 1598 3 view .LVU331
+1599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Get tick count */
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tickstart = HAL_GetTick();
+ 1118              		.loc 1 1601 3 view .LVU332
+ 1119              		.loc 1 1601 15 is_stmt 0 view .LVU333
+ 1120 000a FFF7FEFF 		bl	HAL_GetTick
+ 1121              	.LVL89:
+ 1122              		.loc 1 1601 15 view .LVU334
+ 1123 000e 8046     		mov	r8, r0
+ 1124              	.LVL90:
+1602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check selected event flag */
+1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+ 1125              		.loc 1 1604 3 is_stmt 1 view .LVU335
+ 1126              	.L70:
+ 1127              		.loc 1 1604 46 view .LVU336
+ 1128              		.loc 1 1604 10 is_stmt 0 view .LVU337
+ 1129 0010 3468     		ldr	r4, [r6]
+ 1130 0012 2368     		ldr	r3, [r4]
+ 1131              		.loc 1 1604 46 view .LVU338
+ 1132 0014 35EA0303 		bics	r3, r5, r3
+ 1133 0018 18D0     		beq	.L83
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check if timeout is disabled (set to infinite wait) */
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (Timeout != HAL_MAX_DELAY)
+ 1134              		.loc 1 1607 5 is_stmt 1 view .LVU339
+ 1135              		.loc 1 1607 8 is_stmt 0 view .LVU340
+ 1136 001a B7F1FF3F 		cmp	r7, #-1
+ 1137 001e F7D0     		beq	.L70
+1608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ 1138              		.loc 1 1609 7 is_stmt 1 view .LVU341
+ 1139              		.loc 1 1609 13 is_stmt 0 view .LVU342
+ 1140 0020 FFF7FEFF 		bl	HAL_GetTick
+ 1141              	.LVL91:
+ 1142              		.loc 1 1609 27 view .LVU343
+ 1143 0024 A0EB0800 		sub	r0, r0, r8
+ 1144              		.loc 1 1609 10 view .LVU344
+ 1145 0028 B842     		cmp	r0, r7
+ 1146 002a 01D8     		bhi	.L71
+ 1147              		.loc 1 1609 51 discriminator 1 view .LVU345
+ 1148 002c 002F     		cmp	r7, #0
+ 1149 002e EFD1     		bne	.L70
+ 1150              	.L71:
+1610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* New check to avoid false timeout detection in case of preemption */
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+ 1151              		.loc 1 1612 9 is_stmt 1 view .LVU346
+ 1152              		.loc 1 1612 13 is_stmt 0 view .LVU347
+ 1153 0030 3368     		ldr	r3, [r6]
+ 1154 0032 1B68     		ldr	r3, [r3]
+ 1155              		.loc 1 1612 12 view .LVU348
+ 1156 0034 35EA0303 		bics	r3, r5, r3
+ 1157 0038 EAD0     		beq	.L70
+1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ARM GAS  /tmp/ccICigVb.s 			page 177
+
+
+1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Update ADC state machine to timeout */
+1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ 1158              		.loc 1 1615 11 is_stmt 1 view .LVU349
+ 1159 003a F36D     		ldr	r3, [r6, #92]
+ 1160 003c 43F00403 		orr	r3, r3, #4
+ 1161 0040 F365     		str	r3, [r6, #92]
+1616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Process unlocked */
+1618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           __HAL_UNLOCK(hadc);
+ 1162              		.loc 1 1618 11 view .LVU350
+ 1163              		.loc 1 1618 11 view .LVU351
+ 1164 0042 0023     		movs	r3, #0
+ 1165 0044 86F85830 		strb	r3, [r6, #88]
+ 1166              		.loc 1 1618 11 view .LVU352
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           return HAL_TIMEOUT;
+ 1167              		.loc 1 1620 11 view .LVU353
+ 1168              		.loc 1 1620 18 is_stmt 0 view .LVU354
+ 1169 0048 0320     		movs	r0, #3
+ 1170 004a 29E0     		b	.L72
+ 1171              	.L83:
+1621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   switch (EventType)
+ 1172              		.loc 1 1626 3 is_stmt 1 view .LVU355
+ 1173 004c B5F5807F 		cmp	r5, #256
+ 1174 0050 28D0     		beq	.L74
+ 1175 0052 0BD8     		bhi	.L75
+ 1176 0054 022D     		cmp	r5, #2
+ 1177 0056 1CD0     		beq	.L76
+ 1178 0058 802D     		cmp	r5, #128
+ 1179 005a 35D1     		bne	.L78
+1627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* End Of Sampling event */
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     case ADC_EOSMP_EVENT:
+1630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state */
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Clear the End Of Sampling flag */
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       break;
+1637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Analog watchdog (level out of window) event */
+1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Note: In case of several analog watchdog enabled, if needed to know      */
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* which one triggered and on which ADCx, test ADC state of analog watchdog */
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()".        */
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* For example:                                                             */
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "          */
+1644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) "          */
+1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) "          */
+1646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check analog watchdog 1 flag */
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     case ADC_AWD_EVENT:
+ARM GAS  /tmp/ccICigVb.s 			page 178
+
+
+1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state */
+1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+ 1180              		.loc 1 1650 7 view .LVU356
+ 1181 005c F36D     		ldr	r3, [r6, #92]
+ 1182 005e 43F48033 		orr	r3, r3, #65536
+ 1183 0062 F365     		str	r3, [r6, #92]
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Clear ADC analog watchdog flag */
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+ 1184              		.loc 1 1653 7 view .LVU357
+ 1185 0064 8023     		movs	r3, #128
+ 1186 0066 2360     		str	r3, [r4]
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       break;
+ 1187              		.loc 1 1655 7 view .LVU358
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check analog watchdog 2 flag */
+1658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     case ADC_AWD2_EVENT:
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state */
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+1661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Clear ADC analog watchdog flag */
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+1664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       break;
+1666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check analog watchdog 3 flag */
+1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     case ADC_AWD3_EVENT:
+1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state */
+1670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+1671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Clear ADC analog watchdog flag */
+1673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       break;
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Injected context queue overflow event */
+1678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     case ADC_JQOVF_EVENT:
+1679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state */
+1680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC error code to Injected context queue overflow */
+1683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+1684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Clear ADC Injected context queue overflow flag */
+1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+1687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       break;
+1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Overrun event */
+1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     default: /* Case ADC_OVR_EVENT */
+1692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* If overrun is set to overwrite previous data, overrun event is not     */
+1693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* considered as an error.                                                */
+1694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* (cf ref manual "Managing conversions without using the DMA and without */
+1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* overrun ")                                                             */
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ARM GAS  /tmp/ccICigVb.s 			page 179
+
+
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set ADC state */
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set ADC error code to overrun */
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            otherwise, data register is potentially overwritten by new converted data as soon
+1708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            as OVR is cleared. */
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       break;
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return HAL_OK;
+ 1188              		.loc 1 1715 10 is_stmt 0 view .LVU359
+ 1189 0068 0020     		movs	r0, #0
+1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1190              		.loc 1 1655 7 view .LVU360
+ 1191 006a 19E0     		b	.L72
+ 1192              	.L75:
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1193              		.loc 1 1626 3 view .LVU361
+ 1194 006c B5F5007F 		cmp	r5, #512
+ 1195 0070 21D0     		beq	.L79
+ 1196 0072 B5F5806F 		cmp	r5, #1024
+ 1197 0076 27D1     		bne	.L78
+1680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1198              		.loc 1 1680 7 is_stmt 1 view .LVU362
+ 1199 0078 F36D     		ldr	r3, [r6, #92]
+ 1200 007a 43F48043 		orr	r3, r3, #16384
+ 1201 007e F365     		str	r3, [r6, #92]
+1683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1202              		.loc 1 1683 7 view .LVU363
+ 1203 0080 336E     		ldr	r3, [r6, #96]
+ 1204 0082 43F00803 		orr	r3, r3, #8
+ 1205 0086 3366     		str	r3, [r6, #96]
+1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1206              		.loc 1 1686 7 view .LVU364
+ 1207 0088 4FF48063 		mov	r3, #1024
+ 1208 008c 2360     		str	r3, [r4]
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1209              		.loc 1 1688 7 view .LVU365
+ 1210              		.loc 1 1715 10 is_stmt 0 view .LVU366
+ 1211 008e 0020     		movs	r0, #0
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1212              		.loc 1 1688 7 view .LVU367
+ 1213 0090 06E0     		b	.L72
+ 1214              	.L76:
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1215              		.loc 1 1631 7 is_stmt 1 view .LVU368
+ 1216 0092 F36D     		ldr	r3, [r6, #92]
+ 1217 0094 43F40063 		orr	r3, r3, #2048
+ 1218 0098 F365     		str	r3, [r6, #92]
+ARM GAS  /tmp/ccICigVb.s 			page 180
+
+
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1219              		.loc 1 1634 7 view .LVU369
+ 1220 009a 0223     		movs	r3, #2
+ 1221 009c 2360     		str	r3, [r4]
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1222              		.loc 1 1636 7 view .LVU370
+ 1223              		.loc 1 1715 10 is_stmt 0 view .LVU371
+ 1224 009e 0020     		movs	r0, #0
+ 1225              	.L72:
+1716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1226              		.loc 1 1716 1 view .LVU372
+ 1227 00a0 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 1228              	.LVL92:
+ 1229              	.L74:
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1230              		.loc 1 1660 7 is_stmt 1 view .LVU373
+ 1231 00a4 F36D     		ldr	r3, [r6, #92]
+ 1232 00a6 43F40033 		orr	r3, r3, #131072
+ 1233 00aa F365     		str	r3, [r6, #92]
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1234              		.loc 1 1663 7 view .LVU374
+ 1235 00ac 4FF48073 		mov	r3, #256
+ 1236 00b0 2360     		str	r3, [r4]
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1237              		.loc 1 1665 7 view .LVU375
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1238              		.loc 1 1715 10 is_stmt 0 view .LVU376
+ 1239 00b2 0020     		movs	r0, #0
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1240              		.loc 1 1665 7 view .LVU377
+ 1241 00b4 F4E7     		b	.L72
+ 1242              	.L79:
+1670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1243              		.loc 1 1670 7 is_stmt 1 view .LVU378
+ 1244 00b6 F36D     		ldr	r3, [r6, #92]
+ 1245 00b8 43F48023 		orr	r3, r3, #262144
+ 1246 00bc F365     		str	r3, [r6, #92]
+1673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1247              		.loc 1 1673 7 view .LVU379
+ 1248 00be 4FF40073 		mov	r3, #512
+ 1249 00c2 2360     		str	r3, [r4]
+1675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1250              		.loc 1 1675 7 view .LVU380
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1251              		.loc 1 1715 10 is_stmt 0 view .LVU381
+ 1252 00c4 0020     		movs	r0, #0
+1675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1253              		.loc 1 1675 7 view .LVU382
+ 1254 00c6 EBE7     		b	.L72
+ 1255              	.L78:
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 1256              		.loc 1 1696 7 is_stmt 1 view .LVU383
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 1257              		.loc 1 1696 21 is_stmt 0 view .LVU384
+ 1258 00c8 F36B     		ldr	r3, [r6, #60]
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 1259              		.loc 1 1696 10 view .LVU385
+ARM GAS  /tmp/ccICigVb.s 			page 181
+
+
+ 1260 00ca 4BB9     		cbnz	r3, .L81
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1261              		.loc 1 1699 9 is_stmt 1 view .LVU386
+ 1262 00cc F36D     		ldr	r3, [r6, #92]
+ 1263 00ce 43F48063 		orr	r3, r3, #1024
+ 1264 00d2 F365     		str	r3, [r6, #92]
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 1265              		.loc 1 1702 9 view .LVU387
+ 1266 00d4 336E     		ldr	r3, [r6, #96]
+ 1267 00d6 43F00203 		orr	r3, r3, #2
+ 1268 00da 3366     		str	r3, [r6, #96]
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1269              		.loc 1 1715 10 is_stmt 0 view .LVU388
+ 1270 00dc 0020     		movs	r0, #0
+ 1271 00de DFE7     		b	.L72
+ 1272              	.L81:
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 1273              		.loc 1 1709 9 is_stmt 1 view .LVU389
+ 1274 00e0 1023     		movs	r3, #16
+ 1275 00e2 2360     		str	r3, [r4]
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1276              		.loc 1 1715 10 is_stmt 0 view .LVU390
+ 1277 00e4 0020     		movs	r0, #0
+ 1278 00e6 DBE7     		b	.L72
+ 1279              		.cfi_endproc
+ 1280              	.LFE336:
+ 1282              		.section	.text.HAL_ADC_GetValue,"ax",%progbits
+ 1283              		.align	1
+ 1284              		.global	HAL_ADC_GetValue
+ 1285              		.syntax unified
+ 1286              		.thumb
+ 1287              		.thumb_func
+ 1289              	HAL_ADC_GetValue:
+ 1290              	.LVL93:
+ 1291              	.LFB341:
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+1719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Enable ADC, start conversion of regular group with interruption.
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Interruptions enabled in this function according to initialization
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         setting : EOC (end of conversion), EOS (end of sequence),
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         OVR overrun.
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         Each of these interruptions has its dedicated callback function.
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Case of multimode enabled (when multimode feature is available):
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         HAL_ADC_Start_IT() must be called for ADC Slave first, then for
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         ADC Master.
+1727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         For ADC Slave, ADC is enabled only (conversion is not started).
+1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         For ADC Master, ADC is enabled and multimode conversion is started.
+1729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   To guarantee a proper reset of all interruptions once all the needed
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
+1731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         a correct stop of the IT-based conversions.
+1732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
+1733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         interruption. If required (e.g. in case of oversampling with trigger
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         mode), the user must:
+1735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EO
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          before calling HAL_ADC_Start_IT().
+1738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+ARM GAS  /tmp/ccICigVb.s 			page 182
+
+
+1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status
+1740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
+1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+1743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+1744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   const ADC_TypeDef *tmpADC_Master;
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+1748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+1750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+1751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Perform ADC enable and conversion start if no conversion is on going */
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Process locked */
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_LOCK(hadc);
+1757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Enable the ADC peripheral */
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_hal_status = ADC_Enable(hadc);
+1760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Start conversion if ADC is effectively enabled */
+1762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (tmp_hal_status == HAL_OK)
+1763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state                                                        */
+1765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* - Clear state bitfield related to regular group conversion results   */
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* - Set state bitfield related to regular operation                    */
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       ADC_STATE_CLR_SET(hadc->State,
+1768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_A
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_REG_BUSY);
+1770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         - if ADC instance is master or if multimode feature is not available
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         - if multimode setting is disabled (ADC instance slave in independent mode) */
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          )
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+1780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+1782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC error code */
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Check if a conversion is on going on ADC group injected */
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Reset ADC error code fields related to regular conversions only */
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Reset all ADC error code fields */
+1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         ADC_CLEAR_ERRORCODE(hadc);
+1794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ARM GAS  /tmp/ccICigVb.s 			page 183
+
+
+1796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Clear ADC group regular conversion flag and overrun flag               */
+1797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* (To ensure of no unknown state from potential previous ADC operations) */
+1798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+1799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Process unlocked */
+1801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Unlock before starting ADC conversions: in case of potential         */
+1802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* interruption, to let the process to ADC IRQ Handler.                 */
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_UNLOCK(hadc);
+1804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Disable all interruptions before enabling the desired ones */
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Enable ADC end of conversion interrupt */
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       switch (hadc->Init.EOCSelection)
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_EOC_SEQ_CONV:
+1812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
+1813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+1814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* case ADC_EOC_SINGLE_CONV */
+1815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         default:
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+1817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+1818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Enable ADC overrun interrupt */
+1821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          behavior and no CPU time is lost for a non-processed interruption */
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+1827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Enable conversion of regular group.                                  */
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* If software start has been selected, conversion starts immediately.  */
+1831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* If external trigger has been selected, conversion will start at next */
+1832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* trigger event.                                                       */
+1833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Case of multimode enabled (when multimode feature is available):     */
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
+1835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*    enabled only (conversion is not started),                         */
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*  - if ADC is master, ADC is enabled and conversion is started.       */
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+1838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+1841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          )
+1843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* ADC instance is not a multimode slave instance with multimode regular conversions enable
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+1846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+1847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+1848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Enable as well injected interruptions in case
+1850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+1851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            allows to start regular and injected conversions when JAUTO is
+1852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            set with a single call to HAL_ADC_Start_IT() */
+ARM GAS  /tmp/ccICigVb.s 			page 184
+
+
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           switch (hadc->Init.EOCSelection)
+1854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+1855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             case ADC_EOC_SEQ_CONV:
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+1857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               break;
+1859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* case ADC_EOC_SINGLE_CONV */
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             default:
+1861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+1862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+1863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               break;
+1864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+1866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Start ADC group regular conversion */
+1868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_REG_StartConversion(hadc->Instance);
+1869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+1871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
+1873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+1874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* if Master ADC JAUTO bit is set, Slave injected interruptions
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            are enabled nevertheless (for same reason as above) */
+1876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
+1878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+1879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****              and in resetting HAL_ADC_STATE_INJ_EOC bit */
+1881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+1882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Next, set Slave injected interruptions */
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           switch (hadc->Init.EOCSelection)
+1884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+1885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             case ADC_EOC_SEQ_CONV:
+1886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+1888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               break;
+1889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* case ADC_EOC_SINGLE_CONV */
+1890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             default:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+1892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+1893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               break;
+1894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+1896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+1898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* ADC instance is not a multimode slave instance with multimode regular conversions enabled 
+1899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+1900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+1901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+1902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Enable as well injected interruptions in case
+1904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+1905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          allows to start regular and injected conversions when JAUTO is
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          set with a single call to HAL_ADC_Start_IT() */
+1907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         switch (hadc->Init.EOCSelection)
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+1909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           case ADC_EOC_SEQ_CONV:
+ARM GAS  /tmp/ccICigVb.s 			page 185
+
+
+1910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+1911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+1912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             break;
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* case ADC_EOC_SINGLE_CONV */
+1914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           default:
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+1916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+1917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             break;
+1918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+1919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+1920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Start ADC group regular conversion */
+1922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       LL_ADC_REG_StartConversion(hadc->Instance);
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+1924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+1926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Process unlocked */
+1928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_UNLOCK(hadc);
+1929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else
+1933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_hal_status = HAL_BUSY;
+1935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+1938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return tmp_hal_status;
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+1942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Stop ADC conversion of regular group (and injected group in
+1943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         case of auto_injection mode), disable interrution of
+1944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         end-of-conversion, disable ADC peripheral.
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status.
+1947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
+1949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+1950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+1953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+1954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Process locked */
+1956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_LOCK(hadc);
+1957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+1959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+1960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Disable ADC peripheral if conversions are effectively stopped */
+1962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (tmp_hal_status == HAL_OK)
+1963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+1964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Disable ADC end of conversion interrupt for regular group */
+1965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Disable ADC overrun interrupt */
+1966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+ARM GAS  /tmp/ccICigVb.s 			page 186
+
+
+1967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* 2. Disable the ADC peripheral */
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_hal_status = ADC_Disable(hadc);
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check if ADC is effectively disabled */
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (tmp_hal_status == HAL_OK)
+1973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+1974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state */
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       ADC_STATE_CLR_SET(hadc->State,
+1976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+1977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_READY);
+1978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+1979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+1980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Process unlocked */
+1982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+1983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+1985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return tmp_hal_status;
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+1987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+1988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+1989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
+1990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Interruptions enabled in this function:
+1991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         overrun (if applicable), DMA half transfer, DMA transfer complete.
+1992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         Each of these interruptions has its dedicated callback function.
+1993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
+1994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         is designed for single-ADC mode only. For multimode, the dedicated
+1995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         HAL_ADCEx_MultiModeStart_DMA() function must be used.
+1996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+1997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param pData Destination Buffer address.
+1998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param Length Number of data to be transferred from ADC peripheral to memory
+1999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status.
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
+2002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+2003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+2004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+2005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+2006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+2007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+2009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+2010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Perform ADC enable and conversion start if no conversion is on going */
+2012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+2013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Process locked */
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_LOCK(hadc);
+2016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Ensure that multimode regular conversions are not enabled.   */
+2019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
+2020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((ADC_IS_INDEPENDENT(hadc) != RESET)
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+2022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+2023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ARM GAS  /tmp/ccICigVb.s 			page 187
+
+
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        )
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* ADC_MULTIMODE_SUPPORT */
+2026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Enable the ADC peripheral */
+2028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmp_hal_status = ADC_Enable(hadc);
+2029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Start conversion if ADC is effectively enabled */
+2031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (tmp_hal_status == HAL_OK)
+2032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set ADC state                                                        */
+2034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* - Clear state bitfield related to regular group conversion results   */
+2035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* - Set state bitfield related to regular operation                    */
+2036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         ADC_STATE_CLR_SET(hadc->State,
+2037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                           HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL
+2038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                           HAL_ADC_STATE_REG_BUSY);
+2039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+2041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           - if ADC instance is master or if multimode feature is not available
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           - if multimode setting is disabled (ADC instance slave in independent mode) */
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+2045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+2046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            )
+2047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+2049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+2051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Check if a conversion is on going on ADC group injected */
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+2054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Reset ADC error code fields related to regular conversions only */
+2056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         else
+2059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Reset all ADC error code fields */
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           ADC_CLEAR_ERRORCODE(hadc);
+2062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set the DMA transfer complete callback */
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+2066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set the DMA half transfer complete callback */
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+2069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set the DMA error callback */
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+2072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Manage ADC and DMA start: ADC overrun interruption, DMA start,     */
+2075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* ADC start (in case of SW start):                                   */
+2076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Clear regular group conversion flag and overrun flag               */
+2078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* (To ensure of no unknown state from potential previous ADC         */
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* operations)                                                        */
+2080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+ARM GAS  /tmp/ccICigVb.s 			page 188
+
+
+2081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Process unlocked */
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Unlock before starting ADC conversions: in case of potential         */
+2084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* interruption, to let the process to ADC IRQ Handler.                 */
+2085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         __HAL_UNLOCK(hadc);
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* With DMA, overrun event is always considered as an error even if
+2088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
+2089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            ADC_IT_OVR is enabled. */
+2090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+2091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Enable ADC DMA mode */
+2093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+2094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Start the DMA channel */
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_
+2097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Enable conversion of regular group.                                  */
+2099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* If software start has been selected, conversion starts immediately.  */
+2100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* If external trigger has been selected, conversion will start at next */
+2101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* trigger event.                                                       */
+2102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Start ADC group regular conversion */
+2103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_REG_StartConversion(hadc->Instance);
+2104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+2106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Process unlocked */
+2108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         __HAL_UNLOCK(hadc);
+2109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+2113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+2114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmp_hal_status = HAL_ERROR;
+2116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Process unlocked */
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_UNLOCK(hadc);
+2118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_hal_status = HAL_BUSY;
+2124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+2127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return tmp_hal_status;
+2128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+2129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+2131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Stop ADC conversion of regular group (and injected group in
+2132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         case of auto_injection mode), disable ADC DMA transfer, disable
+2133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         ADC peripheral.
+2134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note:  ADC peripheral disable is forcing stop of potential
+2135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         conversion on ADC group injected. If ADC group injected is under use, it
+2136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+2137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Case of multimode enabled (when multimode feature is available):
+ARM GAS  /tmp/ccICigVb.s 			page 189
+
+
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
+2140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+2141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status.
+2142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+2146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Process locked */
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_LOCK(hadc);
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* 1. Stop potential ADC group regular conversion on going */
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+2155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Disable ADC peripheral if conversions are effectively stopped */
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (tmp_hal_status == HAL_OK)
+2158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+2163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* while DMA transfer is on going)                                        */
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Check if DMA channel effectively disabled */
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (tmp_hal_status != HAL_OK)
+2170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Update ADC state machine to error */
+2172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Disable ADC overrun interrupt */
+2177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* 2. Disable the ADC peripheral */
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
+2181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* to keep in memory a potential failing status.                          */
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (tmp_hal_status == HAL_OK)
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmp_hal_status = ADC_Disable(hadc);
+2185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+2187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (void)ADC_Disable(hadc);
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check if ADC is effectively disabled */
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (tmp_hal_status == HAL_OK)
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state */
+ARM GAS  /tmp/ccICigVb.s 			page 190
+
+
+2195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       ADC_STATE_CLR_SET(hadc->State,
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+2197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_READY);
+2198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Process unlocked */
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+2204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return tmp_hal_status;
+2207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+2208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+2210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Get ADC regular group conversion result.
+2211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Reading register DR automatically clears ADC flag EOC
+2212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         (ADC group regular end of unitary conversion).
+2213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   This function does not clear ADC flag EOS
+2214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         (ADC group regular end of sequence conversion).
+2215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         Occurrence of flag EOS rising:
+2216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          - If sequencer is composed of 1 rank, flag EOS is equivalent
+2217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *            to flag EOC.
+2218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          - If sequencer is composed of several ranks, during the scan
+2219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *            sequence flag EOC only is raised, at the end of the scan sequence
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *            both flags EOC and EOS are raised.
+2221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         To clear this flag, either use function:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         model polling: @ref HAL_ADC_PollForConversion()
+2224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+2225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+2226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval ADC group regular conversion data
+2227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
+2229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 1292              		.loc 1 2229 1 is_stmt 1 view -0
+ 1293              		.cfi_startproc
+ 1294              		@ args = 0, pretend = 0, frame = 0
+ 1295              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1296              		@ link register save eliminated.
+2230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 1297              		.loc 1 2231 3 view .LVU392
+2232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Note: EOC flag is not cleared here by software because automatically     */
+2234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /*       cleared by hardware when reading register DR.                      */
+2235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return ADC converted value */
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return hadc->Instance->DR;
+ 1298              		.loc 1 2237 3 view .LVU393
+ 1299              		.loc 1 2237 14 is_stmt 0 view .LVU394
+ 1300 0000 0368     		ldr	r3, [r0]
+ 1301              		.loc 1 2237 24 view .LVU395
+ 1302 0002 186C     		ldr	r0, [r3, #64]
+ 1303              	.LVL94:
+2238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1304              		.loc 1 2238 1 view .LVU396
+ARM GAS  /tmp/ccICigVb.s 			page 191
+
+
+ 1305 0004 7047     		bx	lr
+ 1306              		.cfi_endproc
+ 1307              	.LFE341:
+ 1309              		.section	.text.HAL_ADC_StartSampling,"ax",%progbits
+ 1310              		.align	1
+ 1311              		.global	HAL_ADC_StartSampling
+ 1312              		.syntax unified
+ 1313              		.thumb
+ 1314              		.thumb_func
+ 1316              	HAL_ADC_StartSampling:
+ 1317              	.LVL95:
+ 1318              	.LFB342:
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+2241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Start ADC conversion sampling phase of regular group
+2242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note:  This function should only be called to start sampling when
+2243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
+2244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         mode has been selected
+2245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         - @ref ADC_SOFTWARE_START has been selected as trigger source
+2246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+2247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status.
+2248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc)
+2250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 1319              		.loc 1 2250 1 is_stmt 1 view -0
+ 1320              		.cfi_startproc
+ 1321              		@ args = 0, pretend = 0, frame = 0
+ 1322              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1323              		@ link register save eliminated.
+2251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+2252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 1324              		.loc 1 2252 3 view .LVU398
+2253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Start sampling */
+2255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
+ 1325              		.loc 1 2255 3 view .LVU399
+ 1326 0000 0268     		ldr	r2, [r0]
+ 1327 0002 1369     		ldr	r3, [r2, #16]
+ 1328 0004 43F00073 		orr	r3, r3, #33554432
+ 1329 0008 1361     		str	r3, [r2, #16]
+2256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+2258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return HAL_OK;
+ 1330              		.loc 1 2258 3 view .LVU400
+2259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1331              		.loc 1 2259 1 is_stmt 0 view .LVU401
+ 1332 000a 0020     		movs	r0, #0
+ 1333              	.LVL96:
+ 1334              		.loc 1 2259 1 view .LVU402
+ 1335 000c 7047     		bx	lr
+ 1336              		.cfi_endproc
+ 1337              	.LFE342:
+ 1339              		.section	.text.HAL_ADC_StopSampling,"ax",%progbits
+ 1340              		.align	1
+ 1341              		.global	HAL_ADC_StopSampling
+ 1342              		.syntax unified
+ 1343              		.thumb
+ARM GAS  /tmp/ccICigVb.s 			page 192
+
+
+ 1344              		.thumb_func
+ 1346              	HAL_ADC_StopSampling:
+ 1347              	.LVL97:
+ 1348              	.LFB343:
+2260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+2262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Stop ADC conversion sampling phase of regular group and start conversion
+2263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note:  This function should only be called to stop sampling when
+2264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
+2265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         mode has been selected
+2266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         - @ref ADC_SOFTWARE_START has been selected as trigger source
+2267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         - after sampling has been started using @ref HAL_ADC_StartSampling.
+2268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+2269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status.
+2270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc)
+2272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 1349              		.loc 1 2272 1 is_stmt 1 view -0
+ 1350              		.cfi_startproc
+ 1351              		@ args = 0, pretend = 0, frame = 0
+ 1352              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1353              		@ link register save eliminated.
+2273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 1354              		.loc 1 2274 3 view .LVU404
+2275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Start sampling */
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
+ 1355              		.loc 1 2277 3 view .LVU405
+ 1356 0000 0268     		ldr	r2, [r0]
+ 1357 0002 1369     		ldr	r3, [r2, #16]
+ 1358 0004 23F00073 		bic	r3, r3, #33554432
+ 1359 0008 1361     		str	r3, [r2, #16]
+2278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return HAL_OK;
+ 1360              		.loc 1 2280 3 view .LVU406
+2281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1361              		.loc 1 2281 1 is_stmt 0 view .LVU407
+ 1362 000a 0020     		movs	r0, #0
+ 1363              	.LVL98:
+ 1364              		.loc 1 2281 1 view .LVU408
+ 1365 000c 7047     		bx	lr
+ 1366              		.cfi_endproc
+ 1367              	.LFE343:
+ 1369              		.section	.text.HAL_ADC_ConvCpltCallback,"ax",%progbits
+ 1370              		.align	1
+ 1371              		.weak	HAL_ADC_ConvCpltCallback
+ 1372              		.syntax unified
+ 1373              		.thumb
+ 1374              		.thumb_func
+ 1376              	HAL_ADC_ConvCpltCallback:
+ 1377              	.LVL99:
+ 1378              	.LFB345:
+2282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+2284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Handle ADC interrupt request.
+ARM GAS  /tmp/ccICigVb.s 			page 193
+
+
+2285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval None
+2287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
+2289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error 
+2291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_isr = hadc->Instance->ISR;
+2292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_ier = hadc->Instance->IER;
+2293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+2295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_cfgr;
+2296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+2297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   const ADC_TypeDef *tmpADC_Master;
+2298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+2299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+2302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+2304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* ========== Check End of Sampling flag for ADC group regular ========== */
+2306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
+2307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Update state machine on end of sampling status if not in error state */
+2309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+2310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state */
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+2313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* End Of Sampling callback */
+2316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+2317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->EndOfSamplingCallback(hadc);
+2318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+2319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     HAL_ADCEx_EndOfSamplingCallback(hadc);
+2320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Clear regular group conversion flag */
+2323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+2324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
+2328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+2329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Update state machine on conversion status if not in error state */
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+2332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state */
+2334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+2335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Determine whether any further conversion upcoming on group regular     */
+2338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* by external trigger, continuous mode or scan sequence on going         */
+2339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* to disable interruption.                                               */
+2340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+2341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ARM GAS  /tmp/ccICigVb.s 			page 194
+
+
+2342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Get relevant register CFGR in ADC instance of ADC master or slave    */
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* in function of multimode state (for devices with multimode           */
+2344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* available).                                                          */
+2345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+2347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+2348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+2349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+2350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          )
+2351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* check CONT bit directly in handle ADC CFGR register */
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+2354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+2356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* else need to check Master ADC CONT bit */
+2358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+2359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+2362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+2363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+2364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Carry on if continuous mode is disabled */
+2366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
+2367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* If End of Sequence is reached, disable interrupts */
+2369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+2370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit         */
+2372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* ADSTART==0 (no conversion on going)                              */
+2373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+2374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+2375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* Disable ADC end of sequence conversion interrupt */
+2376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* Note: Overrun interrupt was enabled with EOC interrupt in      */
+2377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* HAL_Start_IT(), but is not disabled here because can be used   */
+2378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* by overrun IRQ process below.                                  */
+2379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+2380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* Set ADC state */
+2382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+2385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             {
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             }
+2388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+2389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           else
+2390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+2391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* Change ADC state to error state */
+2392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+2393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* Set ADC error code to ADC peripheral internal error */
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+2396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+2397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ARM GAS  /tmp/ccICigVb.s 			page 195
+
+
+2399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Conversion complete callback */
+2402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Note: Into callback function "HAL_ADC_ConvCpltCallback()",             */
+2403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*       to determine if conversion has been triggered from EOC or EOS,   */
+2404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*       possibility to use:                                              */
+2405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*        " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "               */
+2406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+2407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->ConvCpltCallback(hadc);
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     HAL_ADC_ConvCpltCallback(hadc);
+2410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+2411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Clear regular group conversion flag */
+2413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
+2414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*       conversion flags clear induces the release of the preserved data.*/
+2415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*       Therefore, if the preserved data value is needed, it must be     */
+2416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
+2417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
+2421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
+2422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
+2423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Update state machine on conversion status if not in error state */
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+2426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC state */
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Retrieve ADC configuration */
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+2434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Get relevant register CFGR in ADC instance of ADC master or slave  */
+2435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* in function of multimode state (for devices with multimode         */
+2436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* available).                                                        */
+2437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+2440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+2441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+2442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        )
+2443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+2445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+2447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+2450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+2452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+2453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+2454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Disable interruption if no further conversion upcoming by injected     */
+ARM GAS  /tmp/ccICigVb.s 			page 196
+
+
+2456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* external trigger or by automatic injected conversion with regular      */
+2457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* group having no further conversion upcoming (same conditions as        */
+2458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* regular group interruption disabling above),                           */
+2459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* and if injected scan sequence is completed.                            */
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
+2461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
+2463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
+2465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* If End of Sequence is reached, disable interrupts */
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Particular case if injected contexts queue is enabled:             */
+2470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* when the last context has been fully processed, JSQR is reset      */
+2471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* by the hardware. Even if no injected conversion is planned to come */
+2472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* (queue empty, triggers are ignored), it can start again            */
+2473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* immediately after setting a new context (JADSTART is still set).   */
+2474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Therefore, state of HAL ADC injected group is kept to busy.        */
+2475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+2477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit       */
+2478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* JADSTART==0 (no conversion on going)                             */
+2479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+2480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             {
+2481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               /* Disable ADC end of sequence conversion interrupt  */
+2482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+2483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               /* Set ADC state */
+2485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+2486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+2488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               {
+2489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+2490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               }
+2491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             }
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             else
+2493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             {
+2494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               /* Update ADC state machine to error */
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+2496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               /* Set ADC error code to ADC peripheral internal error */
+2498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+2499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             }
+2500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+2501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Injected Conversion complete callback */
+2506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to
+2507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+2508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+2509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               interruption has been triggered by end of conversion or end of
+2510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               sequence.    */
+2511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->InjectedConvCpltCallback(hadc);
+ARM GAS  /tmp/ccICigVb.s 			page 197
+
+
+2513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+2514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     HAL_ADCEx_InjectedConvCpltCallback(hadc);
+2515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+2516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Clear injected group conversion flag */
+2518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+2519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* ========== Check Analog watchdog 1 flag ========== */
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
+2523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Set ADC state */
+2525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+2526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Level out of window 1 callback */
+2528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+2529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->LevelOutOfWindowCallback(hadc);
+2530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+2531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     HAL_ADC_LevelOutOfWindowCallback(hadc);
+2532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+2533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Clear ADC analog watchdog flag */
+2535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+2536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* ========== Check analog watchdog 2 flag ========== */
+2539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
+2540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Set ADC state */
+2542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+2543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Level out of window 2 callback */
+2545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+2546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->LevelOutOfWindow2Callback(hadc);
+2547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+2548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+2549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+2550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Clear ADC analog watchdog flag */
+2552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+2553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* ========== Check analog watchdog 3 flag ========== */
+2556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
+2557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Set ADC state */
+2559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+2560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Level out of window 3 callback */
+2562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+2563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->LevelOutOfWindow3Callback(hadc);
+2564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+2565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+2566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+2567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Clear ADC analog watchdog flag */
+2569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+ARM GAS  /tmp/ccICigVb.s 			page 198
+
+
+2570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* ========== Check Overrun flag ========== */
+2573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
+2574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* If overrun is set to overwrite previous data (default setting),        */
+2576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* overrun event is not considered as an error.                           */
+2577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* (cf ref manual "Managing conversions without using the DMA and without */
+2578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* overrun ")                                                             */
+2579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Exception for usage with DMA overrun event always considered as an     */
+2580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* error.                                                                 */
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+2582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       overrun_error = 1UL;
+2584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+2586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Check DMA configuration */
+2588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+2589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
+2590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Multimode (when feature is available) is enabled,
+2592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            Common Control Register MDMA bits must be checked. */
+2593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_RE
+2594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           overrun_error = 1UL;
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+2599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+2600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Multimode not set or feature not available or ADC independent */
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL)
+2603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           overrun_error = 1UL;
+2605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (overrun_error == 1UL)
+2610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Change ADC state to error state */
+2612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+2613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC error code to overrun */
+2615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+2616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Error callback */
+2618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Note: In case of overrun, ADC conversion data is preserved until     */
+2619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*       flag OVR is reset.                                             */
+2620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*       Therefore, old ADC conversion data can be retrieved in         */
+2621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*       function "HAL_ADC_ErrorCallback()".                            */
+2622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+2623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       hadc->ErrorCallback(hadc);
+2624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+2625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       HAL_ADC_ErrorCallback(hadc);
+2626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ARM GAS  /tmp/ccICigVb.s 			page 199
+
+
+2627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Clear ADC overrun flag */
+2630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+2631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* ========== Check Injected context queue overflow flag ========== */
+2634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
+2635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Change ADC state to overrun state */
+2637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+2638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Set ADC error code to Injected context queue overflow */
+2640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+2641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Clear the Injected context queue overflow flag */
+2643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+2644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Injected context queue overflow callback */
+2646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+2647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->InjectedQueueOverflowCallback(hadc);
+2648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+2649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
+2650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+2651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+2654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+2656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Conversion complete callback in non-blocking mode.
+2657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+2658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval None
+2659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
+2661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 1379              		.loc 1 2661 1 is_stmt 1 view -0
+ 1380              		.cfi_startproc
+ 1381              		@ args = 0, pretend = 0, frame = 0
+ 1382              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1383              		@ link register save eliminated.
+2662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+2663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   UNUSED(hadc);
+ 1384              		.loc 1 2663 3 view .LVU410
+2664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* NOTE : This function should not be modified. When the callback is needed,
+2666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+2667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****    */
+2668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1385              		.loc 1 2668 1 is_stmt 0 view .LVU411
+ 1386 0000 7047     		bx	lr
+ 1387              		.cfi_endproc
+ 1388              	.LFE345:
+ 1390              		.section	.text.HAL_ADC_ConvHalfCpltCallback,"ax",%progbits
+ 1391              		.align	1
+ 1392              		.weak	HAL_ADC_ConvHalfCpltCallback
+ 1393              		.syntax unified
+ 1394              		.thumb
+ARM GAS  /tmp/ccICigVb.s 			page 200
+
+
+ 1395              		.thumb_func
+ 1397              	HAL_ADC_ConvHalfCpltCallback:
+ 1398              	.LVL100:
+ 1399              	.LFB346:
+2669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+2671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Conversion DMA half-transfer callback in non-blocking mode.
+2672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+2673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval None
+2674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
+2676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 1400              		.loc 1 2676 1 is_stmt 1 view -0
+ 1401              		.cfi_startproc
+ 1402              		@ args = 0, pretend = 0, frame = 0
+ 1403              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1404              		@ link register save eliminated.
+2677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+2678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   UNUSED(hadc);
+ 1405              		.loc 1 2678 3 view .LVU413
+2679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* NOTE : This function should not be modified. When the callback is needed,
+2681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+2682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1406              		.loc 1 2683 1 is_stmt 0 view .LVU414
+ 1407 0000 7047     		bx	lr
+ 1408              		.cfi_endproc
+ 1409              	.LFE346:
+ 1411              		.section	.text.ADC_DMAHalfConvCplt,"ax",%progbits
+ 1412              		.align	1
+ 1413              		.global	ADC_DMAHalfConvCplt
+ 1414              		.syntax unified
+ 1415              		.thumb
+ 1416              		.thumb_func
+ 1418              	ADC_DMAHalfConvCplt:
+ 1419              	.LVL101:
+ 1420              	.LFB357:
+2684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+2686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Analog watchdog 1 callback in non-blocking mode.
+2687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+2688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval None
+2689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
+2691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+2692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+2693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   UNUSED(hadc);
+2694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* NOTE : This function should not be modified. When the callback is needed,
+2696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+2697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+2699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+2701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  ADC error callback in non-blocking mode
+2702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         (ADC conversion with interruption or transfer by DMA).
+ARM GAS  /tmp/ccICigVb.s 			page 201
+
+
+2703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   In case of error due to overrun when using ADC with DMA transfer
+2704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+2705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+2706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         - If needed, restart a new ADC conversion using function
+2707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *           "HAL_ADC_Start_DMA()"
+2708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *           (this function is also clearing overrun flag)
+2709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+2710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval None
+2711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+2713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+2714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+2715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   UNUSED(hadc);
+2716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* NOTE : This function should not be modified. When the callback is needed,
+2718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             function HAL_ADC_ErrorCallback must be implemented in the user file.
+2719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+2721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+2723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @}
+2724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+2727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief    Peripheral Control functions
+2728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *
+2729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** @verbatim
+2730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****  ===============================================================================
+2731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****              ##### Peripheral Control functions #####
+2732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****  ===============================================================================
+2733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     [..]  This section provides functions allowing to:
+2734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Configure channels on regular group
+2735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Configure the analog watchdog
+2736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** @endverbatim
+2738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @{
+2739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+2742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Configure a channel to be assigned to ADC group regular.
+2743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   In case of usage of internal measurement channels:
+2744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         Vbat/VrefInt/TempSensor.
+2745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         These internal paths can be disabled using function
+2746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         HAL_ADC_DeInit().
+2747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Possibility to update parameters on the fly:
+2748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         This function initializes channel into ADC group regular,
+2749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         following calls to this function can be used to reconfigure
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
+2751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         without resetting the ADC.
+2752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         The setting of these parameters is conditioned to ADC state:
+2753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         Refer to comments of structure "ADC_ChannelConfTypeDef".
+2754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+2755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param sConfig Structure of ADC channel assigned to ADC group regular.
+2756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status
+2757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
+2759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ARM GAS  /tmp/ccICigVb.s 			page 202
+
+
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+2761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpOffsetShifted;
+2762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_config_internal_channel;
+2763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __IO uint32_t wait_loop_index = 0UL;
+2764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+2765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_injected;
+2766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+2768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+2769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+2770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+2771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
+2772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
+2773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
+2774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+2776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      ignored (considered as reset) */
+2777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENAB
+2778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Verification of channel number */
+2780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+2781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else
+2785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
+2787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Process locked */
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_LOCK(hadc);
+2791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Parameters update conditioned to ADC state:                              */
+2793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Parameters that can be updated when ADC is disabled or enabled without   */
+2794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* conversion on going on regular group:                                    */
+2795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /*  - Channel number                                                        */
+2796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /*  - Channel rank                                                          */
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+2798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Set ADC group regular sequence: channel on the selected scan sequence rank */
+2800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
+2801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Parameters update conditioned to ADC state:                              */
+2803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Parameters that can be updated when ADC is disabled or enabled without   */
+2804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* conversion on going on regular group:                                    */
+2805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - Channel sampling time                                                 */
+2806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - Channel offset                                                        */
+2807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+2808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+2810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         && (tmp_adc_is_conversion_on_going_injected == 0UL)
+2811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        )
+2812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
+2815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set sampling time of the selected ADC channel */
+ARM GAS  /tmp/ccICigVb.s 			page 203
+
+
+2817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES
+2818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set ADC sampling time common configuration */
+2820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5)
+2821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+2823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set sampling time of the selected ADC channel */
+2825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set ADC sampling time common configuration */
+2828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
+2829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Configure the offset: offset enable/disable, channel, offset value */
+2832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Shift the offset with respect to the selected ADC resolution. */
+2834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+2835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
+2836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
+2838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set ADC selected offset number */
+2840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted)
+2841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         assert_param(IS_ADC_OFFSET_SIGN(sConfig->OffsetSign));
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSaturation));
+2844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set ADC selected offset sign & saturation */
+2845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_SetOffsetSign(hadc->Instance, sConfig->OffsetNumber, sConfig->OffsetSign);
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_SetOffsetSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSaturatio
+2847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+2849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Scan each offset register to check if the selected channel is targeted. */
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* If this is the case, the corresponding offset number is disabled.       */
+2852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)
+2853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+2854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
+2856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)
+2858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+2859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
+2861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)
+2863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
+2866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)
+2868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+2869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ARM GAS  /tmp/ccICigVb.s 			page 204
+
+
+2874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Parameters update conditioned to ADC state:                              */
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Parameters that can be updated only when ADC is disabled:                */
+2877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /*  - Single or differential mode                                           */
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+2879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set mode single-ended or differential input of the selected ADC channel */
+2881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
+2882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Configuration of differential mode */
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
+2885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set sampling time of the selected ADC channel */
+2887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits r
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_SetChannelSamplingTime(hadc->Instance,
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_T
+2890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+2891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
+2896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* If internal channel selected, enable dedicated internal buffers and    */
+2897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* paths.                                                                 */
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Note: these internal measurement paths can be disabled using           */
+2899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* HAL_ADC_DeInit().                                                      */
+2900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+2902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+2903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->I
+2904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* If the requested internal measurement path has already been enabled, */
+2906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* bypass the configuration processing.                                 */
+2907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (sConfig->Channel == ADC_CHANNEL_TE
+2908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+2909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+2911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+2913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                          LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_chan
+2914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Delay for temperature sensor stabilization time */
+2916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Wait loop initialization and execution */
+2917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Note: Variable divided by 2 to compensate partially              */
+2918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /*       CPU processing cycles, scaling in us split to not          */
+2919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /*       exceed 32 bits register capacity and handle low frequency. */
+2920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           while (wait_loop_index != 0UL)
+2922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+2923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             wait_loop_index--;
+2924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+2925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PAT
+2928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+2930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ARM GAS  /tmp/ccICigVb.s 			page 205
+
+
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+2932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                          LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+2933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else if ((sConfig->Channel == ADC_CHANNEL_VREFINT)
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+2937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (ADC_VREFINT_INSTANCE(hadc))
+2939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+2940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+2941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                          LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel
+2942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+2945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+2946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* nothing to do */
+2947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+2948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+2949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* If a conversion is on going on regular group, no update on regular       */
+2952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* channel could be done on neither of the channel configuration structure  */
+2953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* parameters.                                                              */
+2954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else
+2955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+2956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Update ADC state machine to error */
+2957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+2958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_hal_status = HAL_ERROR;
+2960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+2961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Process unlocked */
+2963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+2964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+2966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return tmp_hal_status;
+2967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+2968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+2970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Configure the analog watchdog.
+2971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Possibility to update parameters on the fly:
+2972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         This function initializes the selected analog watchdog, successive
+2973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         calls to this function can be used to reconfigure some parameters
+2974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
+2975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         the ADC.
+2976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         The setting of these parameters is conditioned to ADC state.
+2977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         For parameters constraints, see comments of structure
+2978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         "ADC_AnalogWDGConfTypeDef".
+2979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   On this STM32 series, analog watchdog thresholds can be modified
+2980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         while ADC conversion is on going.
+2981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         In this case, some constraints must be taken into account:
+2982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         the programmed threshold values are effective from the next
+2983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         ADC EOC (end of unitary conversion).
+2984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         Considering that registers write delay may happen due to
+2985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         bus activity, this might cause an uncertainty on the
+2986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         effective timing of the new programmed threshold values.
+2987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+ARM GAS  /tmp/ccICigVb.s 			page 206
+
+
+2988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
+2989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status
+2990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+2991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *Analog
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+2993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+2994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpAWDHighThresholdShifted;
+2995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpAWDLowThresholdShifted;
+2996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+2997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_injected;
+2998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+2999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+3000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+3001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
+3002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+3003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(AnalogWDGConfig->FilteringConfig));
+3004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+3005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
+3007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
+3008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
+3009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+3010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
+3011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+3012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Verify thresholds range */
+3014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (hadc->Init.OversamplingMode == ENABLE)
+3015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+3016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Case of oversampling enabled: depending on ratio and shift configuration,
+3017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        analog watchdog thresholds can be higher than ADC resolution.
+3018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        Verify if thresholds are within maximum thresholds range. */
+3019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
+3020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
+3021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+3022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else
+3023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+3024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Verify if thresholds are within the selected ADC resolution */
+3025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+3026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+3027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+3028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Process locked */
+3030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_LOCK(hadc);
+3031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Parameters update conditioned to ADC state:                              */
+3033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Parameters that can be updated when ADC is disabled or enabled without   */
+3034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* conversion on going on ADC groups regular and injected:                  */
+3035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /*  - Analog watchdog channels                                              */
+3036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+3037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+3038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+3039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       && (tmp_adc_is_conversion_on_going_injected == 0UL)
+3040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      )
+3041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+3042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Analog watchdog configuration */
+3043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+3044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ARM GAS  /tmp/ccICigVb.s 			page 207
+
+
+3045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Configuration of analog watchdog:                                    */
+3046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*  - Set the analog watchdog enable mode: one or overall group of      */
+3047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*    channels, on groups regular and-or injected.                      */
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       switch (AnalogWDGConfig->WatchdogMode)
+3049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_ANALOGWATCHDOG_SINGLE_REG:
+3051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GR
+3052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                           LL_ADC_GROUP_REGULAR));
+3053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+3054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+3056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GR
+3057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                           LL_ADC_GROUP_INJECTED));
+3058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+3061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GR
+3062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                           LL_ADC_GROUP_REGULAR_INJECTED));
+3063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+3064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_ANALOGWATCHDOG_ALL_REG:
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG)
+3067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+3068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_ANALOGWATCHDOG_ALL_INJEC:
+3070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ)
+3071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+3072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+3074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_
+3075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+3076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         default: /* ADC_ANALOGWATCHDOG_NONE */
+3078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
+3079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+3080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set the filtering configuration */
+3083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       MODIFY_REG(hadc->Instance->TR1,
+3084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                  ADC_TR1_AWDFILT,
+3085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                  AnalogWDGConfig->FilteringConfig);
+3086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Update state, clear previous result related to AWD1 */
+3088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+3089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Clear flag ADC analog watchdog */
+3091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+3092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* (in case left enabled by previous ADC operations).                 */
+3094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       LL_ADC_ClearFlag_AWD1(hadc->Instance);
+3095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Configure ADC analog watchdog interrupt */
+3097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (AnalogWDGConfig->ITMode == ENABLE)
+3098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_EnableIT_AWD1(hadc->Instance);
+3100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+ARM GAS  /tmp/ccICigVb.s 			page 208
+
+
+3102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_DisableIT_AWD1(hadc->Instance);
+3104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
+3107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+3108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       switch (AnalogWDGConfig->WatchdogMode)
+3110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_ANALOGWATCHDOG_SINGLE_REG:
+3112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+3113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+3114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Update AWD by bitfield to keep the possibility to monitor        */
+3115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* several channels by successive calls of this function.           */
+3116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+3118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig
+3119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           else
+3121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+3122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig
+3123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+3124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+3125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_ANALOGWATCHDOG_ALL_REG:
+3127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_ANALOGWATCHDOG_ALL_INJEC:
+3128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_A
+3130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+3131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         default: /* ADC_ANALOGWATCHDOG_NONE */
+3133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_A
+3134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+3135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+3138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Update state, clear previous result related to AWD2 */
+3140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Clear flag ADC analog watchdog */
+3143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+3144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+3145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* (in case left enabled by previous ADC operations).                 */
+3146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_ClearFlag_AWD2(hadc->Instance);
+3147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Configure ADC analog watchdog interrupt */
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (AnalogWDGConfig->ITMode == ENABLE)
+3150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+3151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_EnableIT_AWD2(hadc->Instance);
+3152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+3153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         else
+3154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+3155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_DisableIT_AWD2(hadc->Instance);
+3156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+ARM GAS  /tmp/ccICigVb.s 			page 209
+
+
+3159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       else
+3160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Update state, clear previous result related to AWD3 */
+3162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+3163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Clear flag ADC analog watchdog */
+3165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+3166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+3167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* (in case left enabled by previous ADC operations).                 */
+3168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_ClearFlag_AWD3(hadc->Instance);
+3169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Configure ADC analog watchdog interrupt */
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (AnalogWDGConfig->ITMode == ENABLE)
+3172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+3173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_EnableIT_AWD3(hadc->Instance);
+3174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+3175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         else
+3176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+3177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_DisableIT_AWD3(hadc->Instance);
+3178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+3179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+3183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Analog watchdog thresholds configuration */
+3185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+3186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+3187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Shift the offset with respect to the selected ADC resolution:        */
+3188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
+3189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* are set to 0.                                                        */
+3190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThre
+3191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThres
+3192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+3193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
+3194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else
+3195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+3196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Shift the offset with respect to the selected ADC resolution:        */
+3197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Thresholds have to be left-aligned on bit 7, the LSB (right bits)    */
+3198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* are set to 0.                                                        */
+3199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThr
+3200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThre
+3201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+3202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+3204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresh
+3205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                   tmpAWDLowThresholdShifted);
+3206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Process unlocked */
+3208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+3209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return function status */
+3211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return tmp_hal_status;
+3212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+3213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 210
+
+
+3216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @}
+3217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+3220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *  @brief    ADC Peripheral State functions
+3221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *
+3222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** @verbatim
+3223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****  ===============================================================================
+3224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             ##### Peripheral state and errors functions #####
+3225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****  ===============================================================================
+3226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     [..]
+3227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     This subsection provides functions to get in run-time the status of the
+3228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     peripheral.
+3229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Check the ADC state
+3230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (+) Check the ADC error code
+3231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** @endverbatim
+3233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @{
+3234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+3237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Return the ADC handle state.
+3238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   ADC state machine is managed by bitfields, ADC status must be
+3239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         compared with states bits.
+3240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         For example:
+3241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+3242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+3243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+3244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval ADC handle state (bitfield on 32 bits)
+3245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
+3247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+3248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+3250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return ADC handle state */
+3252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return hadc->State;
+3253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+3254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+3256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Return the ADC error code.
+3257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval ADC error code (bitfield on 32 bits)
+3259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+3261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+3262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+3263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+3264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return hadc->ErrorCode;
+3266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+3267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+3269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @}
+3270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 211
+
+
+3273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @}
+3274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /** @defgroup ADC_Private_Functions ADC Private Functions
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @{
+3278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+3281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Stop ADC conversion.
+3282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+3283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param ConversionGroup ADC group regular and/or injected.
+3284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *          This parameter can be one of the following values:
+3285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *            @arg @ref ADC_REGULAR_GROUP           ADC regular conversion type.
+3286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *            @arg @ref ADC_INJECTED_GROUP          ADC injected conversion type.
+3287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *            @arg @ref ADC_REGULAR_INJECTED_GROUP  ADC regular and injected conversion type.
+3288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status.
+3289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
+3291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+3292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tickstart;
+3293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t Conversion_Timeout_CPU_cycles = 0UL;
+3294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t conversion_group_reassigned = ConversionGroup;
+3295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_ADC_CR_ADSTART_JADSTART;
+3296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+3297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_injected;
+3298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+3300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+3301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
+3302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Verification if ADC is not already stopped (on regular and injected      */
+3304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* groups) to bypass this function if not needed.                           */
+3305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+3306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+3307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((tmp_adc_is_conversion_on_going_regular != 0UL)
+3308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       || (tmp_adc_is_conversion_on_going_injected != 0UL)
+3309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      )
+3310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+3311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Particular case of continuous auto-injection mode combined with        */
+3312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* auto-delay mode.                                                       */
+3313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
+3314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* injected group stop ADC_CR_JADSTP).                                    */
+3315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1   */
+3316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* (see reference manual).                                                */
+3317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
+3318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         && (hadc->Init.ContinuousConvMode == ENABLE)
+3319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         && (hadc->Init.LowPowerAutoWait == ENABLE)
+3320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        )
+3321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Use stop of regular group */
+3323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       conversion_group_reassigned = ADC_REGULAR_GROUP;
+3324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
+3326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
+3327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
+3329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ARM GAS  /tmp/ccICigVb.s 			page 212
+
+
+3330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Update ADC state machine to error */
+3331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+3332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Set ADC error code to ADC peripheral internal error */
+3334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+3335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           return HAL_ERROR;
+3337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+3338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         Conversion_Timeout_CPU_cycles ++;
+3339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Clear JEOS */
+3342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
+3343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Stop potential conversion on going on ADC group regular */
+3346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (conversion_group_reassigned != ADC_INJECTED_GROUP)
+3347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+3349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+3350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+3352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+3353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Stop ADC group regular conversion */
+3354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_REG_StopConversion(hadc->Instance);
+3355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+3356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Stop potential conversion on going on ADC group injected */
+3360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if (conversion_group_reassigned != ADC_REGULAR_GROUP)
+3361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
+3363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+3364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+3366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+3367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Stop ADC group injected conversion */
+3368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           LL_ADC_INJ_StopConversion(hadc->Instance);
+3369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+3370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Selection of start and stop bits with respect to the regular or injected group */
+3374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     switch (conversion_group_reassigned)
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case ADC_REGULAR_INJECTED_GROUP:
+3377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
+3378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       case ADC_INJECTED_GROUP:
+3380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+3382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Case ADC_REGULAR_GROUP only*/
+3383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       default:
+3384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
+3385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ARM GAS  /tmp/ccICigVb.s 			page 213
+
+
+3387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Wait for conversion effectively stopped */
+3389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tickstart = HAL_GetTick();
+3390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+3392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+3394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* New check to avoid false timeout detection in case of preemption */
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+3397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+3398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Update ADC state machine to error */
+3399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Set ADC error code to ADC peripheral internal error */
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+3403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           return HAL_ERROR;
+3405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+3406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+3410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return HAL status */
+3412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return HAL_OK;
+3413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+3414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+3416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Enable the selected ADC.
+3417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Prerequisite condition to use this function: ADC must be disabled
+3418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
+3419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+3420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status.
+3421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
+3423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+3424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tickstart;
+3425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
+3427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* enabling phase not yet completed: flag ADC ready not yet set).           */
+3428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
+3429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* causes: ADC clock not running, ...).                                     */
+3430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+3431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+3432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check if conditions to enable the ADC are fulfilled */
+3433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_
+3434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+3435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Update ADC state machine to error */
+3437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC error code to ADC peripheral internal error */
+3440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+3441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       return HAL_ERROR;
+3443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ARM GAS  /tmp/ccICigVb.s 			page 214
+
+
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Enable the ADC peripheral */
+3446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     LL_ADC_Enable(hadc->Instance);
+3447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Wait for ADC effectively enabled */
+3449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tickstart = HAL_GetTick();
+3450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+3452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
+3454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           has been cleared (after a calibration), ADEN bit is reset by the
+3455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           calibration logic.
+3456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           The workaround is to continue setting ADEN until ADRDY is becomes 1.
+3457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+3458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           4 ADC clock cycle duration */
+3459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Note: Test of ADC enabled required due to hardware constraint to     */
+3460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /*       not enable ADC if already enabled.                             */
+3461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+3462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_Enable(hadc->Instance);
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+3467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* New check to avoid false timeout detection in case of preemption */
+3469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+3470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+3471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Update ADC state machine to error */
+3472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+3473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Set ADC error code to ADC peripheral internal error */
+3475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+3476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           return HAL_ERROR;
+3478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+3479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+3482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return HAL status */
+3484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return HAL_OK;
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+3486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+3488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  Disable the selected ADC.
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @note   Prerequisite condition to use this function: ADC conversions must be
+3490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   *         stopped.
+3491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hadc ADC handle
+3492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval HAL status.
+3493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
+3495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+3496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tickstart;
+3497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
+3498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Verification if ADC is not already disabled:                             */
+3500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
+ARM GAS  /tmp/ccICigVb.s 			page 215
+
+
+3501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /*       disabled.                                                          */
+3502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+3503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       && (tmp_adc_is_disable_on_going == 0UL)
+3504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      )
+3505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+3506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Check if conditions to disable the ADC are fulfilled */
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+3508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Disable the ADC peripheral */
+3510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       LL_ADC_Disable(hadc->Instance);
+3511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+3514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Update ADC state machine to error */
+3516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+3517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Set ADC error code to ADC peripheral internal error */
+3519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+3520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       return HAL_ERROR;
+3522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Wait for ADC effectively disabled */
+3525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Get tick count */
+3526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tickstart = HAL_GetTick();
+3527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+3531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* New check to avoid false timeout detection in case of preemption */
+3533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+3534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+3535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Update ADC state machine to error */
+3536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+3537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Set ADC error code to ADC peripheral internal error */
+3539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+3540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           return HAL_ERROR;
+3542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+3543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+3546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Return HAL status */
+3548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   return HAL_OK;
+3549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+3550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+3552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  DMA transfer complete callback.
+3553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hdma pointer to DMA handle.
+3554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval None
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+3557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ARM GAS  /tmp/ccICigVb.s 			page 216
+
+
+3558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Retrieve ADC handle corresponding to current DMA handle */
+3559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+3560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Update state machine on conversion status if not in error state */
+3562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
+3563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+3564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Set ADC state */
+3565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+3566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Determine whether any further conversion upcoming on group regular     */
+3568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* by external trigger, continuous mode or scan sequence on going         */
+3569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* to disable interruption.                                               */
+3570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Is it the end of the regular sequence ? */
+3571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
+3572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Are conversions software-triggered ? */
+3574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+3575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Is CONT bit set ? */
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
+3578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+3579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* CONT bit is not set, no more conversions expected */
+3580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+3581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+3582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+3583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+3584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+3585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+3586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+3589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* DMA End of Transfer interrupt was triggered but conversions sequence
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          is not over. If DMACFG is set to 0, conversions are stopped. */
+3592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL)
+3593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+3594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* DMACFG bit is not set, conversions are stopped. */
+3595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+3596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+3597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+3598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+3599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+3600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+3601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Conversion complete callback */
+3604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+3605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     hadc->ConvCpltCallback(hadc);
+3606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+3607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     HAL_ADC_ConvCpltCallback(hadc);
+3608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+3609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+3610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   else /* DMA and-or internal error occurred */
+3611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+3612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+3613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Call HAL ADC Error Callback function */
+ARM GAS  /tmp/ccICigVb.s 			page 217
+
+
+3615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+3616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       hadc->ErrorCallback(hadc);
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+3618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       HAL_ADC_ErrorCallback(hadc);
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+3620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     else
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+3623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Call ADC DMA error callback */
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       hadc->DMA_Handle->XferErrorCallback(hdma);
+3625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+3626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+3627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+3628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+3630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  DMA half transfer complete callback.
+3631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hdma pointer to DMA handle.
+3632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval None
+3633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+3635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 1421              		.loc 1 3635 1 is_stmt 1 view -0
+ 1422              		.cfi_startproc
+ 1423              		@ args = 0, pretend = 0, frame = 0
+ 1424              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1425              		.loc 1 3635 1 is_stmt 0 view .LVU416
+ 1426 0000 08B5     		push	{r3, lr}
+ 1427              	.LCFI11:
+ 1428              		.cfi_def_cfa_offset 8
+ 1429              		.cfi_offset 3, -8
+ 1430              		.cfi_offset 14, -4
+3636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Retrieve ADC handle corresponding to current DMA handle */
+3637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 1431              		.loc 1 3637 3 is_stmt 1 view .LVU417
+ 1432              	.LVL102:
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Half conversion callback */
+3640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+3641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   hadc->ConvHalfCpltCallback(hadc);
+3642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+3643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_ADC_ConvHalfCpltCallback(hadc);
+ 1433              		.loc 1 3643 3 view .LVU418
+ 1434 0002 806A     		ldr	r0, [r0, #40]
+ 1435              	.LVL103:
+ 1436              		.loc 1 3643 3 is_stmt 0 view .LVU419
+ 1437 0004 FFF7FEFF 		bl	HAL_ADC_ConvHalfCpltCallback
+ 1438              	.LVL104:
+3644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+3645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 1439              		.loc 1 3645 1 view .LVU420
+ 1440 0008 08BD     		pop	{r3, pc}
+ 1441              		.cfi_endproc
+ 1442              	.LFE357:
+ 1444              		.section	.text.HAL_ADC_LevelOutOfWindowCallback,"ax",%progbits
+ 1445              		.align	1
+ 1446              		.weak	HAL_ADC_LevelOutOfWindowCallback
+ 1447              		.syntax unified
+ARM GAS  /tmp/ccICigVb.s 			page 218
+
+
+ 1448              		.thumb
+ 1449              		.thumb_func
+ 1451              	HAL_ADC_LevelOutOfWindowCallback:
+ 1452              	.LVL105:
+ 1453              	.LFB347:
+2691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+ 1454              		.loc 1 2691 1 is_stmt 1 view -0
+ 1455              		.cfi_startproc
+ 1456              		@ args = 0, pretend = 0, frame = 0
+ 1457              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1458              		@ link register save eliminated.
+2693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1459              		.loc 1 2693 3 view .LVU422
+2698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1460              		.loc 1 2698 1 is_stmt 0 view .LVU423
+ 1461 0000 7047     		bx	lr
+ 1462              		.cfi_endproc
+ 1463              	.LFE347:
+ 1465              		.section	.text.HAL_ADC_ErrorCallback,"ax",%progbits
+ 1466              		.align	1
+ 1467              		.weak	HAL_ADC_ErrorCallback
+ 1468              		.syntax unified
+ 1469              		.thumb
+ 1470              		.thumb_func
+ 1472              	HAL_ADC_ErrorCallback:
+ 1473              	.LVL106:
+ 1474              	.LFB348:
+2713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+ 1475              		.loc 1 2713 1 is_stmt 1 view -0
+ 1476              		.cfi_startproc
+ 1477              		@ args = 0, pretend = 0, frame = 0
+ 1478              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1479              		@ link register save eliminated.
+2715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1480              		.loc 1 2715 3 view .LVU425
+2720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1481              		.loc 1 2720 1 is_stmt 0 view .LVU426
+ 1482 0000 7047     		bx	lr
+ 1483              		.cfi_endproc
+ 1484              	.LFE348:
+ 1486              		.section	.text.HAL_ADC_IRQHandler,"ax",%progbits
+ 1487              		.align	1
+ 1488              		.global	HAL_ADC_IRQHandler
+ 1489              		.syntax unified
+ 1490              		.thumb
+ 1491              		.thumb_func
+ 1493              	HAL_ADC_IRQHandler:
+ 1494              	.LVL107:
+ 1495              	.LFB344:
+2289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error 
+ 1496              		.loc 1 2289 1 is_stmt 1 view -0
+ 1497              		.cfi_startproc
+ 1498              		@ args = 0, pretend = 0, frame = 0
+ 1499              		@ frame_needed = 0, uses_anonymous_args = 0
+2289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error 
+ 1500              		.loc 1 2289 1 is_stmt 0 view .LVU428
+ 1501 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ARM GAS  /tmp/ccICigVb.s 			page 219
+
+
+ 1502              	.LCFI12:
+ 1503              		.cfi_def_cfa_offset 24
+ 1504              		.cfi_offset 3, -24
+ 1505              		.cfi_offset 4, -20
+ 1506              		.cfi_offset 5, -16
+ 1507              		.cfi_offset 6, -12
+ 1508              		.cfi_offset 7, -8
+ 1509              		.cfi_offset 14, -4
+ 1510 0002 0446     		mov	r4, r0
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_isr = hadc->Instance->ISR;
+ 1511              		.loc 1 2290 3 is_stmt 1 view .LVU429
+ 1512              	.LVL108:
+2291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_ier = hadc->Instance->IER;
+ 1513              		.loc 1 2291 3 view .LVU430
+2291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_ier = hadc->Instance->IER;
+ 1514              		.loc 1 2291 26 is_stmt 0 view .LVU431
+ 1515 0004 0368     		ldr	r3, [r0]
+2291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_ier = hadc->Instance->IER;
+ 1516              		.loc 1 2291 12 view .LVU432
+ 1517 0006 1F68     		ldr	r7, [r3]
+ 1518              	.LVL109:
+2292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+ 1519              		.loc 1 2292 3 is_stmt 1 view .LVU433
+2292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+ 1520              		.loc 1 2292 12 is_stmt 0 view .LVU434
+ 1521 0008 5D68     		ldr	r5, [r3, #4]
+ 1522              	.LVL110:
+2293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+ 1523              		.loc 1 2293 3 is_stmt 1 view .LVU435
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_cfgr;
+ 1524              		.loc 1 2294 3 view .LVU436
+2295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 1525              		.loc 1 2295 3 view .LVU437
+2297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+ 1526              		.loc 1 2297 3 view .LVU438
+2298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+ 1527              		.loc 1 2298 3 view .LVU439
+ 1528              	.LBB364:
+ 1529              	.LBI364:
+6392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1530              		.loc 2 6392 26 view .LVU440
+ 1531              	.LBB365:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1532              		.loc 2 6394 3 view .LVU441
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1533              		.loc 2 6394 21 is_stmt 0 view .LVU442
+ 1534 000a 9A4B     		ldr	r3, .L140
+ 1535 000c 9E68     		ldr	r6, [r3, #8]
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1536              		.loc 2 6394 10 view .LVU443
+ 1537 000e 06F01F06 		and	r6, r6, #31
+ 1538              	.LVL111:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1539              		.loc 2 6394 10 view .LVU444
+ 1540              	.LBE365:
+ 1541              	.LBE364:
+2302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+ARM GAS  /tmp/ccICigVb.s 			page 220
+
+
+ 1542              		.loc 1 2302 3 is_stmt 1 view .LVU445
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1543              		.loc 1 2303 3 view .LVU446
+2306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1544              		.loc 1 2306 3 view .LVU447
+2306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1545              		.loc 1 2306 6 is_stmt 0 view .LVU448
+ 1546 0012 17F0020F 		tst	r7, #2
+ 1547 0016 10D0     		beq	.L94
+2306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1548              		.loc 1 2306 54 discriminator 1 view .LVU449
+ 1549 0018 15F0020F 		tst	r5, #2
+ 1550 001c 0DD0     		beq	.L94
+2309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1551              		.loc 1 2309 5 is_stmt 1 view .LVU450
+2309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1552              		.loc 1 2309 14 is_stmt 0 view .LVU451
+ 1553 001e C36D     		ldr	r3, [r0, #92]
+2309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1554              		.loc 1 2309 8 view .LVU452
+ 1555 0020 13F0100F 		tst	r3, #16
+ 1556 0024 03D1     		bne	.L95
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 1557              		.loc 1 2312 7 is_stmt 1 view .LVU453
+ 1558 0026 C36D     		ldr	r3, [r0, #92]
+ 1559 0028 43F40063 		orr	r3, r3, #2048
+ 1560 002c C365     		str	r3, [r0, #92]
+ 1561              	.L95:
+2319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 1562              		.loc 1 2319 5 view .LVU454
+ 1563 002e 2046     		mov	r0, r4
+ 1564              	.LVL112:
+2319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 1565              		.loc 1 2319 5 is_stmt 0 view .LVU455
+ 1566 0030 FFF7FEFF 		bl	HAL_ADCEx_EndOfSamplingCallback
+ 1567              	.LVL113:
+2323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 1568              		.loc 1 2323 5 is_stmt 1 view .LVU456
+ 1569 0034 2368     		ldr	r3, [r4]
+ 1570 0036 0222     		movs	r2, #2
+ 1571 0038 1A60     		str	r2, [r3]
+ 1572              	.L94:
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+ 1573              		.loc 1 2327 3 view .LVU457
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+ 1574              		.loc 1 2327 6 is_stmt 0 view .LVU458
+ 1575 003a 17F0040F 		tst	r7, #4
+ 1576 003e 02D0     		beq	.L96
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+ 1577              		.loc 1 2327 51 discriminator 1 view .LVU459
+ 1578 0040 15F0040F 		tst	r5, #4
+ 1579 0044 05D1     		bne	.L97
+ 1580              	.L96:
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+ 1581              		.loc 1 2327 94 discriminator 3 view .LVU460
+ 1582 0046 17F0080F 		tst	r7, #8
+ 1583 004a 4DD0     		beq	.L98
+ARM GAS  /tmp/ccICigVb.s 			page 221
+
+
+2328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1584              		.loc 1 2328 51 view .LVU461
+ 1585 004c 15F0080F 		tst	r5, #8
+ 1586 0050 4AD0     		beq	.L98
+ 1587              	.L97:
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1588              		.loc 1 2331 5 is_stmt 1 view .LVU462
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1589              		.loc 1 2331 14 is_stmt 0 view .LVU463
+ 1590 0052 E36D     		ldr	r3, [r4, #92]
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1591              		.loc 1 2331 8 view .LVU464
+ 1592 0054 13F0100F 		tst	r3, #16
+ 1593 0058 03D1     		bne	.L99
+2334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 1594              		.loc 1 2334 7 is_stmt 1 view .LVU465
+ 1595 005a E36D     		ldr	r3, [r4, #92]
+ 1596 005c 43F40073 		orr	r3, r3, #512
+ 1597 0060 E365     		str	r3, [r4, #92]
+ 1598              	.L99:
+2340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1599              		.loc 1 2340 5 view .LVU466
+2340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1600              		.loc 1 2340 9 is_stmt 0 view .LVU467
+ 1601 0062 2368     		ldr	r3, [r4]
+ 1602              	.LVL114:
+ 1603              	.LBB366:
+ 1604              	.LBI366:
+3747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1605              		.loc 2 3747 26 is_stmt 1 view .LVU468
+ 1606              	.LBB367:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1607              		.loc 2 3749 3 view .LVU469
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1608              		.loc 2 3749 12 is_stmt 0 view .LVU470
+ 1609 0064 DA68     		ldr	r2, [r3, #12]
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1610              		.loc 2 3749 103 view .LVU471
+ 1611 0066 12F4406F 		tst	r2, #3072
+ 1612 006a 37D1     		bne	.L100
+ 1613              	.LVL115:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1614              		.loc 2 3749 103 view .LVU472
+ 1615              	.LBE367:
+ 1616              	.LBE366:
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1617              		.loc 1 2346 7 is_stmt 1 view .LVU473
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1618              		.loc 1 2346 12 is_stmt 0 view .LVU474
+ 1619 006c 824A     		ldr	r2, .L140+4
+ 1620 006e 9342     		cmp	r3, r2
+ 1621 0070 0CD0     		beq	.L134
+ 1622 0072 1A46     		mov	r2, r3
+ 1623              	.L101:
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1624              		.loc 1 2346 10 discriminator 4 view .LVU475
+ 1625 0074 9342     		cmp	r3, r2
+ARM GAS  /tmp/ccICigVb.s 			page 222
+
+
+ 1626 0076 0CD0     		beq	.L102
+ 1627 0078 092E     		cmp	r6, #9
+ 1628 007a 05D8     		bhi	.L103
+ 1629 007c 40F22121 		movw	r1, #545
+ 1630 0080 F140     		lsrs	r1, r1, r6
+ 1631 0082 11F0010F 		tst	r1, #1
+ 1632 0086 04D1     		bne	.L102
+ 1633              	.L103:
+2358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+ 1634              		.loc 1 2358 9 is_stmt 1 discriminator 4 view .LVU476
+ 1635              	.LVL116:
+2359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 1636              		.loc 1 2359 9 discriminator 4 view .LVU477
+2359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 1637              		.loc 1 2359 18 is_stmt 0 discriminator 4 view .LVU478
+ 1638 0088 D268     		ldr	r2, [r2, #12]
+ 1639              	.LVL117:
+2359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 1640              		.loc 1 2359 18 discriminator 4 view .LVU479
+ 1641 008a 03E0     		b	.L104
+ 1642              	.LVL118:
+ 1643              	.L134:
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1644              		.loc 1 2346 12 view .LVU480
+ 1645 008c 4FF0A042 		mov	r2, #1342177280
+ 1646 0090 F0E7     		b	.L101
+ 1647              	.L102:
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 1648              		.loc 1 2353 9 is_stmt 1 view .LVU481
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 1649              		.loc 1 2353 18 is_stmt 0 view .LVU482
+ 1650 0092 DA68     		ldr	r2, [r3, #12]
+ 1651              	.LVL119:
+ 1652              	.L104:
+2366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 1653              		.loc 1 2366 7 is_stmt 1 view .LVU483
+2366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 1654              		.loc 1 2366 10 is_stmt 0 view .LVU484
+ 1655 0094 12F4005F 		tst	r2, #8192
+ 1656 0098 20D1     		bne	.L100
+2369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 1657              		.loc 1 2369 9 is_stmt 1 view .LVU485
+2369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 1658              		.loc 1 2369 13 is_stmt 0 view .LVU486
+ 1659 009a 1A68     		ldr	r2, [r3]
+ 1660              	.LVL120:
+2369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 1661              		.loc 1 2369 12 view .LVU487
+ 1662 009c 12F0080F 		tst	r2, #8
+ 1663 00a0 1CD0     		beq	.L100
+2373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 1664              		.loc 1 2373 11 is_stmt 1 view .LVU488
+ 1665              	.LVL121:
+ 1666              	.LBB368:
+ 1667              	.LBI368:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1668              		.loc 2 6851 26 view .LVU489
+ARM GAS  /tmp/ccICigVb.s 			page 223
+
+
+ 1669              	.LBB369:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1670              		.loc 2 6853 3 view .LVU490
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1671              		.loc 2 6853 12 is_stmt 0 view .LVU491
+ 1672 00a2 9A68     		ldr	r2, [r3, #8]
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1673              		.loc 2 6853 74 view .LVU492
+ 1674 00a4 12F0040F 		tst	r2, #4
+ 1675 00a8 10D1     		bne	.L105
+ 1676              	.LVL122:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1677              		.loc 2 6853 74 view .LVU493
+ 1678              	.LBE369:
+ 1679              	.LBE368:
+2379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1680              		.loc 1 2379 13 is_stmt 1 view .LVU494
+ 1681 00aa 5A68     		ldr	r2, [r3, #4]
+ 1682 00ac 22F00C02 		bic	r2, r2, #12
+ 1683 00b0 5A60     		str	r2, [r3, #4]
+2382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1684              		.loc 1 2382 13 view .LVU495
+ 1685 00b2 E36D     		ldr	r3, [r4, #92]
+ 1686 00b4 23F48073 		bic	r3, r3, #256
+ 1687 00b8 E365     		str	r3, [r4, #92]
+2384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             {
+ 1688              		.loc 1 2384 13 view .LVU496
+2384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             {
+ 1689              		.loc 1 2384 22 is_stmt 0 view .LVU497
+ 1690 00ba E36D     		ldr	r3, [r4, #92]
+2384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             {
+ 1691              		.loc 1 2384 16 view .LVU498
+ 1692 00bc 13F4805F 		tst	r3, #4096
+ 1693 00c0 0CD1     		bne	.L100
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             }
+ 1694              		.loc 1 2386 15 is_stmt 1 view .LVU499
+ 1695 00c2 E36D     		ldr	r3, [r4, #92]
+ 1696 00c4 43F00103 		orr	r3, r3, #1
+ 1697 00c8 E365     		str	r3, [r4, #92]
+ 1698 00ca 07E0     		b	.L100
+ 1699              	.LVL123:
+ 1700              	.L105:
+2392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1701              		.loc 1 2392 13 view .LVU500
+ 1702 00cc E36D     		ldr	r3, [r4, #92]
+ 1703 00ce 43F01003 		orr	r3, r3, #16
+ 1704 00d2 E365     		str	r3, [r4, #92]
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 1705              		.loc 1 2395 13 view .LVU501
+ 1706 00d4 236E     		ldr	r3, [r4, #96]
+ 1707 00d6 43F00103 		orr	r3, r3, #1
+ 1708 00da 2366     		str	r3, [r4, #96]
+ 1709              	.LVL124:
+ 1710              	.L100:
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 1711              		.loc 1 2409 5 view .LVU502
+ 1712 00dc 2046     		mov	r0, r4
+ARM GAS  /tmp/ccICigVb.s 			page 224
+
+
+ 1713 00de FFF7FEFF 		bl	HAL_ADC_ConvCpltCallback
+ 1714              	.LVL125:
+2417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 1715              		.loc 1 2417 5 view .LVU503
+ 1716 00e2 2368     		ldr	r3, [r4]
+ 1717 00e4 0C22     		movs	r2, #12
+ 1718 00e6 1A60     		str	r2, [r3]
+ 1719              	.L98:
+2421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
+ 1720              		.loc 1 2421 3 view .LVU504
+2421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
+ 1721              		.loc 1 2421 6 is_stmt 0 view .LVU505
+ 1722 00e8 17F0200F 		tst	r7, #32
+ 1723 00ec 02D0     		beq	.L107
+2421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
+ 1724              		.loc 1 2421 53 discriminator 1 view .LVU506
+ 1725 00ee 15F0200F 		tst	r5, #32
+ 1726 00f2 05D1     		bne	.L108
+ 1727              	.L107:
+2421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
+ 1728              		.loc 1 2421 98 discriminator 3 view .LVU507
+ 1729 00f4 17F0400F 		tst	r7, #64
+ 1730 00f8 5CD0     		beq	.L109
+2422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1731              		.loc 1 2422 53 view .LVU508
+ 1732 00fa 15F0400F 		tst	r5, #64
+ 1733 00fe 59D0     		beq	.L109
+ 1734              	.L108:
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1735              		.loc 1 2425 5 is_stmt 1 view .LVU509
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1736              		.loc 1 2425 14 is_stmt 0 view .LVU510
+ 1737 0100 E36D     		ldr	r3, [r4, #92]
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1738              		.loc 1 2425 8 view .LVU511
+ 1739 0102 13F0100F 		tst	r3, #16
+ 1740 0106 03D1     		bne	.L110
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 1741              		.loc 1 2428 7 is_stmt 1 view .LVU512
+ 1742 0108 E36D     		ldr	r3, [r4, #92]
+ 1743 010a 43F40053 		orr	r3, r3, #8192
+ 1744 010e E365     		str	r3, [r4, #92]
+ 1745              	.L110:
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+ 1746              		.loc 1 2432 5 view .LVU513
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+ 1747              		.loc 1 2432 46 is_stmt 0 view .LVU514
+ 1748 0110 2368     		ldr	r3, [r4]
+ 1749              	.LVL126:
+ 1750              	.LBB370:
+ 1751              	.LBI370:
+4534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1752              		.loc 2 4534 26 is_stmt 1 view .LVU515
+ 1753              	.LBB371:
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1754              		.loc 2 4536 3 view .LVU516
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/ccICigVb.s 			page 225
+
+
+ 1755              		.loc 2 4536 12 is_stmt 0 view .LVU517
+ 1756 0112 DA6C     		ldr	r2, [r3, #76]
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1757              		.loc 2 4536 105 view .LVU518
+ 1758 0114 12F4C07F 		tst	r2, #384
+ 1759 0118 12D1     		bne	.L130
+ 1760 011a 0121     		movs	r1, #1
+ 1761              	.L111:
+ 1762              	.LVL127:
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1763              		.loc 2 4536 105 view .LVU519
+ 1764              	.LBE371:
+ 1765              	.LBE370:
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     /* Get relevant register CFGR in ADC instance of ADC master or slave  */
+ 1766              		.loc 1 2433 5 is_stmt 1 view .LVU520
+ 1767              	.LBB373:
+ 1768              	.LBI373:
+3747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1769              		.loc 2 3747 26 view .LVU521
+ 1770              	.LBB374:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1771              		.loc 2 3749 3 view .LVU522
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1772              		.loc 2 3749 12 is_stmt 0 view .LVU523
+ 1773 011c DA68     		ldr	r2, [r3, #12]
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1774              		.loc 2 3749 103 view .LVU524
+ 1775 011e 12F4406F 		tst	r2, #3072
+ 1776 0122 0FD1     		bne	.L131
+ 1777 0124 0120     		movs	r0, #1
+ 1778              	.L112:
+ 1779              	.LVL128:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1780              		.loc 2 3749 103 view .LVU525
+ 1781              	.LBE374:
+ 1782              	.LBE373:
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1783              		.loc 1 2438 5 is_stmt 1 view .LVU526
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1784              		.loc 1 2438 10 is_stmt 0 view .LVU527
+ 1785 0126 544A     		ldr	r2, .L140+4
+ 1786 0128 9342     		cmp	r3, r2
+ 1787 012a 0DD0     		beq	.L135
+ 1788 012c 1A46     		mov	r2, r3
+ 1789              	.L113:
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1790              		.loc 1 2438 8 discriminator 4 view .LVU528
+ 1791 012e 9342     		cmp	r3, r2
+ 1792 0130 0DD0     		beq	.L114
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ 1793              		.loc 1 2439 9 view .LVU529
+ 1794 0132 66B1     		cbz	r6, .L114
+2440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ 1795              		.loc 1 2440 9 view .LVU530
+ 1796 0134 062E     		cmp	r6, #6
+ 1797 0136 0AD0     		beq	.L114
+2441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        )
+ARM GAS  /tmp/ccICigVb.s 			page 226
+
+
+ 1798              		.loc 1 2441 9 view .LVU531
+ 1799 0138 072E     		cmp	r6, #7
+ 1800 013a 08D0     		beq	.L114
+2448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+ 1801              		.loc 1 2448 7 is_stmt 1 discriminator 4 view .LVU532
+ 1802              	.LVL129:
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 1803              		.loc 1 2449 7 discriminator 4 view .LVU533
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 1804              		.loc 1 2449 16 is_stmt 0 discriminator 4 view .LVU534
+ 1805 013c D268     		ldr	r2, [r2, #12]
+ 1806              	.LVL130:
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 1807              		.loc 1 2449 16 discriminator 4 view .LVU535
+ 1808 013e 07E0     		b	.L116
+ 1809              	.LVL131:
+ 1810              	.L130:
+ 1811              	.LBB376:
+ 1812              	.LBB372:
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1813              		.loc 2 4536 105 view .LVU536
+ 1814 0140 0021     		movs	r1, #0
+ 1815 0142 EBE7     		b	.L111
+ 1816              	.LVL132:
+ 1817              	.L131:
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1818              		.loc 2 4536 105 view .LVU537
+ 1819              	.LBE372:
+ 1820              	.LBE376:
+ 1821              	.LBB377:
+ 1822              	.LBB375:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1823              		.loc 2 3749 103 view .LVU538
+ 1824 0144 0020     		movs	r0, #0
+ 1825 0146 EEE7     		b	.L112
+ 1826              	.LVL133:
+ 1827              	.L135:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1828              		.loc 2 3749 103 view .LVU539
+ 1829              	.LBE375:
+ 1830              	.LBE377:
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1831              		.loc 1 2438 10 view .LVU540
+ 1832 0148 4FF0A042 		mov	r2, #1342177280
+ 1833 014c EFE7     		b	.L113
+ 1834              	.L114:
+2444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 1835              		.loc 1 2444 7 is_stmt 1 view .LVU541
+2444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 1836              		.loc 1 2444 16 is_stmt 0 view .LVU542
+ 1837 014e DA68     		ldr	r2, [r3, #12]
+ 1838              	.LVL134:
+ 1839              	.L116:
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1840              		.loc 1 2460 5 is_stmt 1 view .LVU543
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1841              		.loc 1 2460 8 is_stmt 0 view .LVU544
+ARM GAS  /tmp/ccICigVb.s 			page 227
+
+
+ 1842 0150 51B3     		cbz	r1, .L117
+2462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ 1843              		.loc 1 2462 7 is_stmt 1 view .LVU545
+2462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ 1844              		.loc 1 2462 10 is_stmt 0 view .LVU546
+ 1845 0152 12F0007F 		tst	r2, #33554432
+ 1846 0156 03D0     		beq	.L118
+2462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ 1847              		.loc 1 2462 55 discriminator 1 view .LVU547
+ 1848 0158 30B3     		cbz	r0, .L117
+2463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
+ 1849              		.loc 1 2463 60 view .LVU548
+ 1850 015a 12F4005F 		tst	r2, #8192
+ 1851 015e 23D1     		bne	.L117
+ 1852              	.L118:
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 1853              		.loc 1 2467 9 is_stmt 1 view .LVU549
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 1854              		.loc 1 2467 13 is_stmt 0 view .LVU550
+ 1855 0160 1968     		ldr	r1, [r3]
+ 1856              	.LVL135:
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 1857              		.loc 1 2467 12 view .LVU551
+ 1858 0162 11F0400F 		tst	r1, #64
+ 1859 0166 1FD0     		beq	.L117
+2475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 1860              		.loc 1 2475 11 is_stmt 1 view .LVU552
+2475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 1861              		.loc 1 2475 14 is_stmt 0 view .LVU553
+ 1862 0168 12F4001F 		tst	r2, #2097152
+ 1863 016c 1CD1     		bne	.L117
+2479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             {
+ 1864              		.loc 1 2479 13 is_stmt 1 view .LVU554
+ 1865              	.LVL136:
+ 1866              	.LBB378:
+ 1867              	.LBI378:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1868              		.loc 2 7076 26 view .LVU555
+ 1869              	.LBB379:
+ 1870              		.loc 2 7078 3 view .LVU556
+ 1871              		.loc 2 7078 12 is_stmt 0 view .LVU557
+ 1872 016e 9A68     		ldr	r2, [r3, #8]
+ 1873              	.LVL137:
+ 1874              		.loc 2 7078 76 view .LVU558
+ 1875 0170 12F0080F 		tst	r2, #8
+ 1876 0174 10D1     		bne	.L119
+ 1877              	.LVL138:
+ 1878              		.loc 2 7078 76 view .LVU559
+ 1879              	.LBE379:
+ 1880              	.LBE378:
+2482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1881              		.loc 1 2482 15 is_stmt 1 view .LVU560
+ 1882 0176 5A68     		ldr	r2, [r3, #4]
+ 1883 0178 22F06002 		bic	r2, r2, #96
+ 1884 017c 5A60     		str	r2, [r3, #4]
+2485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1885              		.loc 1 2485 15 view .LVU561
+ARM GAS  /tmp/ccICigVb.s 			page 228
+
+
+ 1886 017e E36D     		ldr	r3, [r4, #92]
+ 1887 0180 23F48053 		bic	r3, r3, #4096
+ 1888 0184 E365     		str	r3, [r4, #92]
+2487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               {
+ 1889              		.loc 1 2487 15 view .LVU562
+2487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               {
+ 1890              		.loc 1 2487 24 is_stmt 0 view .LVU563
+ 1891 0186 E36D     		ldr	r3, [r4, #92]
+2487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               {
+ 1892              		.loc 1 2487 18 view .LVU564
+ 1893 0188 13F4807F 		tst	r3, #256
+ 1894 018c 0CD1     		bne	.L117
+2489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               }
+ 1895              		.loc 1 2489 17 is_stmt 1 view .LVU565
+ 1896 018e E36D     		ldr	r3, [r4, #92]
+ 1897 0190 43F00103 		orr	r3, r3, #1
+ 1898 0194 E365     		str	r3, [r4, #92]
+ 1899 0196 07E0     		b	.L117
+ 1900              	.LVL139:
+ 1901              	.L119:
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1902              		.loc 1 2495 15 view .LVU566
+ 1903 0198 E36D     		ldr	r3, [r4, #92]
+ 1904 019a 43F01003 		orr	r3, r3, #16
+ 1905 019e E365     		str	r3, [r4, #92]
+2498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             }
+ 1906              		.loc 1 2498 15 view .LVU567
+ 1907 01a0 236E     		ldr	r3, [r4, #96]
+ 1908 01a2 43F00103 		orr	r3, r3, #1
+ 1909 01a6 2366     		str	r3, [r4, #96]
+ 1910              	.L117:
+2514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 1911              		.loc 1 2514 5 view .LVU568
+ 1912 01a8 2046     		mov	r0, r4
+ 1913              	.LVL140:
+2514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 1914              		.loc 1 2514 5 is_stmt 0 view .LVU569
+ 1915 01aa FFF7FEFF 		bl	HAL_ADCEx_InjectedConvCpltCallback
+ 1916              	.LVL141:
+2518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 1917              		.loc 1 2518 5 is_stmt 1 view .LVU570
+ 1918 01ae 2368     		ldr	r3, [r4]
+ 1919 01b0 6022     		movs	r2, #96
+ 1920 01b2 1A60     		str	r2, [r3]
+ 1921              	.LVL142:
+ 1922              	.L109:
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1923              		.loc 1 2522 3 view .LVU571
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1924              		.loc 1 2522 6 is_stmt 0 view .LVU572
+ 1925 01b4 17F0800F 		tst	r7, #128
+ 1926 01b8 02D0     		beq	.L121
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1927              		.loc 1 2522 52 discriminator 1 view .LVU573
+ 1928 01ba 15F0800F 		tst	r5, #128
+ 1929 01be 2FD1     		bne	.L136
+ 1930              	.L121:
+ARM GAS  /tmp/ccICigVb.s 			page 229
+
+
+2539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1931              		.loc 1 2539 3 is_stmt 1 view .LVU574
+2539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1932              		.loc 1 2539 6 is_stmt 0 view .LVU575
+ 1933 01c0 17F4807F 		tst	r7, #256
+ 1934 01c4 02D0     		beq	.L122
+2539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1935              		.loc 1 2539 52 discriminator 1 view .LVU576
+ 1936 01c6 15F4807F 		tst	r5, #256
+ 1937 01ca 34D1     		bne	.L137
+ 1938              	.L122:
+2556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1939              		.loc 1 2556 3 is_stmt 1 view .LVU577
+2556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1940              		.loc 1 2556 6 is_stmt 0 view .LVU578
+ 1941 01cc 17F4007F 		tst	r7, #512
+ 1942 01d0 02D0     		beq	.L123
+2556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1943              		.loc 1 2556 52 discriminator 1 view .LVU579
+ 1944 01d2 15F4007F 		tst	r5, #512
+ 1945 01d6 3AD1     		bne	.L138
+ 1946              	.L123:
+2573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1947              		.loc 1 2573 3 is_stmt 1 view .LVU580
+2573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1948              		.loc 1 2573 6 is_stmt 0 view .LVU581
+ 1949 01d8 17F0100F 		tst	r7, #16
+ 1950 01dc 19D0     		beq	.L124
+2573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 1951              		.loc 1 2573 50 discriminator 1 view .LVU582
+ 1952 01de 15F0100F 		tst	r5, #16
+ 1953 01e2 16D0     		beq	.L124
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1954              		.loc 1 2581 5 is_stmt 1 view .LVU583
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1955              		.loc 1 2581 19 is_stmt 0 view .LVU584
+ 1956 01e4 E36B     		ldr	r3, [r4, #60]
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 1957              		.loc 1 2581 8 view .LVU585
+ 1958 01e6 33B1     		cbz	r3, .L125
+2589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 1959              		.loc 1 2589 7 is_stmt 1 view .LVU586
+2589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 1960              		.loc 1 2589 10 is_stmt 0 view .LVU587
+ 1961 01e8 002E     		cmp	r6, #0
+ 1962 01ea 3CD0     		beq	.L126
+2593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 1963              		.loc 1 2593 9 is_stmt 1 view .LVU588
+ 1964              	.LVL143:
+ 1965              	.LBB380:
+ 1966              	.LBI380:
+6489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1967              		.loc 2 6489 26 view .LVU589
+ 1968              	.LBB381:
+6491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1969              		.loc 2 6491 3 view .LVU590
+6491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/ccICigVb.s 			page 230
+
+
+ 1970              		.loc 2 6491 21 is_stmt 0 view .LVU591
+ 1971 01ec 214B     		ldr	r3, .L140
+ 1972 01ee 9B68     		ldr	r3, [r3, #8]
+ 1973              	.LVL144:
+6491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1974              		.loc 2 6491 21 view .LVU592
+ 1975              	.LBE381:
+ 1976              	.LBE380:
+2593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 1977              		.loc 1 2593 12 view .LVU593
+ 1978 01f0 13F4604F 		tst	r3, #57344
+ 1979 01f4 0AD0     		beq	.L127
+ 1980              	.L125:
+ 1981              	.LVL145:
+2612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1982              		.loc 1 2612 7 is_stmt 1 view .LVU594
+ 1983 01f6 E36D     		ldr	r3, [r4, #92]
+ 1984 01f8 43F48063 		orr	r3, r3, #1024
+ 1985 01fc E365     		str	r3, [r4, #92]
+2615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 1986              		.loc 1 2615 7 view .LVU595
+ 1987 01fe 236E     		ldr	r3, [r4, #96]
+ 1988 0200 43F00203 		orr	r3, r3, #2
+ 1989 0204 2366     		str	r3, [r4, #96]
+2625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 1990              		.loc 1 2625 7 view .LVU596
+ 1991 0206 2046     		mov	r0, r4
+ 1992 0208 FFF7FEFF 		bl	HAL_ADC_ErrorCallback
+ 1993              	.LVL146:
+ 1994              	.L127:
+2630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 1995              		.loc 1 2630 5 view .LVU597
+ 1996 020c 2368     		ldr	r3, [r4]
+ 1997 020e 1022     		movs	r2, #16
+ 1998 0210 1A60     		str	r2, [r3]
+ 1999              	.L124:
+2634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 2000              		.loc 1 2634 3 view .LVU598
+2634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 2001              		.loc 1 2634 6 is_stmt 0 view .LVU599
+ 2002 0212 17F4806F 		tst	r7, #1024
+ 2003 0216 02D0     		beq	.L93
+2634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 2004              		.loc 1 2634 54 discriminator 1 view .LVU600
+ 2005 0218 15F4806F 		tst	r5, #1024
+ 2006 021c 2ED1     		bne	.L139
+ 2007              	.L93:
+2653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2008              		.loc 1 2653 1 view .LVU601
+ 2009 021e F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 2010              	.LVL147:
+ 2011              	.L136:
+2525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2012              		.loc 1 2525 5 is_stmt 1 view .LVU602
+ 2013 0220 E36D     		ldr	r3, [r4, #92]
+ 2014 0222 43F48033 		orr	r3, r3, #65536
+ 2015 0226 E365     		str	r3, [r4, #92]
+ARM GAS  /tmp/ccICigVb.s 			page 231
+
+
+2531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2016              		.loc 1 2531 5 view .LVU603
+ 2017 0228 2046     		mov	r0, r4
+ 2018 022a FFF7FEFF 		bl	HAL_ADC_LevelOutOfWindowCallback
+ 2019              	.LVL148:
+2535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 2020              		.loc 1 2535 5 view .LVU604
+ 2021 022e 2368     		ldr	r3, [r4]
+ 2022 0230 8022     		movs	r2, #128
+ 2023 0232 1A60     		str	r2, [r3]
+ 2024 0234 C4E7     		b	.L121
+ 2025              	.L137:
+2542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2026              		.loc 1 2542 5 view .LVU605
+ 2027 0236 E36D     		ldr	r3, [r4, #92]
+ 2028 0238 43F40033 		orr	r3, r3, #131072
+ 2029 023c E365     		str	r3, [r4, #92]
+2548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2030              		.loc 1 2548 5 view .LVU606
+ 2031 023e 2046     		mov	r0, r4
+ 2032 0240 FFF7FEFF 		bl	HAL_ADCEx_LevelOutOfWindow2Callback
+ 2033              	.LVL149:
+2552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 2034              		.loc 1 2552 5 view .LVU607
+ 2035 0244 2368     		ldr	r3, [r4]
+ 2036 0246 4FF48072 		mov	r2, #256
+ 2037 024a 1A60     		str	r2, [r3]
+ 2038 024c BEE7     		b	.L122
+ 2039              	.L138:
+2559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2040              		.loc 1 2559 5 view .LVU608
+ 2041 024e E36D     		ldr	r3, [r4, #92]
+ 2042 0250 43F48023 		orr	r3, r3, #262144
+ 2043 0254 E365     		str	r3, [r4, #92]
+2565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2044              		.loc 1 2565 5 view .LVU609
+ 2045 0256 2046     		mov	r0, r4
+ 2046 0258 FFF7FEFF 		bl	HAL_ADCEx_LevelOutOfWindow3Callback
+ 2047              	.LVL150:
+2569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 2048              		.loc 1 2569 5 view .LVU610
+ 2049 025c 2368     		ldr	r3, [r4]
+ 2050 025e 4FF40072 		mov	r2, #512
+ 2051 0262 1A60     		str	r2, [r3]
+ 2052 0264 B8E7     		b	.L123
+ 2053              	.L126:
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2054              		.loc 1 2602 9 view .LVU611
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2055              		.loc 1 2602 18 is_stmt 0 view .LVU612
+ 2056 0266 2368     		ldr	r3, [r4]
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2057              		.loc 1 2602 28 view .LVU613
+ 2058 0268 DB68     		ldr	r3, [r3, #12]
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2059              		.loc 1 2602 12 view .LVU614
+ 2060 026a 13F0010F 		tst	r3, #1
+ARM GAS  /tmp/ccICigVb.s 			page 232
+
+
+ 2061 026e CDD0     		beq	.L127
+ 2062 0270 C1E7     		b	.L125
+ 2063              	.L141:
+ 2064 0272 00BF     		.align	2
+ 2065              	.L140:
+ 2066 0274 00030050 		.word	1342178048
+ 2067 0278 00010050 		.word	1342177536
+ 2068              	.LVL151:
+ 2069              	.L139:
+2637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2070              		.loc 1 2637 5 is_stmt 1 view .LVU615
+ 2071 027c E36D     		ldr	r3, [r4, #92]
+ 2072 027e 43F48043 		orr	r3, r3, #16384
+ 2073 0282 E365     		str	r3, [r4, #92]
+2640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2074              		.loc 1 2640 5 view .LVU616
+ 2075 0284 236E     		ldr	r3, [r4, #96]
+ 2076 0286 43F00803 		orr	r3, r3, #8
+ 2077 028a 2366     		str	r3, [r4, #96]
+2643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2078              		.loc 1 2643 5 view .LVU617
+ 2079 028c 2368     		ldr	r3, [r4]
+ 2080 028e 4FF48062 		mov	r2, #1024
+ 2081 0292 1A60     		str	r2, [r3]
+2649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2082              		.loc 1 2649 5 view .LVU618
+ 2083 0294 2046     		mov	r0, r4
+ 2084 0296 FFF7FEFF 		bl	HAL_ADCEx_InjectedQueueOverflowCallback
+ 2085              	.LVL152:
+2653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2086              		.loc 1 2653 1 is_stmt 0 view .LVU619
+ 2087 029a C0E7     		b	.L93
+ 2088              		.cfi_endproc
+ 2089              	.LFE344:
+ 2091              		.section	.text.ADC_DMAConvCplt,"ax",%progbits
+ 2092              		.align	1
+ 2093              		.global	ADC_DMAConvCplt
+ 2094              		.syntax unified
+ 2095              		.thumb
+ 2096              		.thumb_func
+ 2098              	ADC_DMAConvCplt:
+ 2099              	.LVL153:
+ 2100              	.LFB356:
+3557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Retrieve ADC handle corresponding to current DMA handle */
+ 2101              		.loc 1 3557 1 is_stmt 1 view -0
+ 2102              		.cfi_startproc
+ 2103              		@ args = 0, pretend = 0, frame = 0
+ 2104              		@ frame_needed = 0, uses_anonymous_args = 0
+3557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Retrieve ADC handle corresponding to current DMA handle */
+ 2105              		.loc 1 3557 1 is_stmt 0 view .LVU621
+ 2106 0000 08B5     		push	{r3, lr}
+ 2107              	.LCFI13:
+ 2108              		.cfi_def_cfa_offset 8
+ 2109              		.cfi_offset 3, -8
+ 2110              		.cfi_offset 14, -4
+ 2111 0002 0346     		mov	r3, r0
+3559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ARM GAS  /tmp/ccICigVb.s 			page 233
+
+
+ 2112              		.loc 1 3559 3 is_stmt 1 view .LVU622
+3559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2113              		.loc 1 3559 22 is_stmt 0 view .LVU623
+ 2114 0004 806A     		ldr	r0, [r0, #40]
+ 2115              	.LVL154:
+3562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 2116              		.loc 1 3562 3 is_stmt 1 view .LVU624
+3562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 2117              		.loc 1 3562 12 is_stmt 0 view .LVU625
+ 2118 0006 C26D     		ldr	r2, [r0, #92]
+3562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 2119              		.loc 1 3562 6 view .LVU626
+ 2120 0008 12F0500F 		tst	r2, #80
+ 2121 000c 30D1     		bne	.L143
+3565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2122              		.loc 1 3565 5 is_stmt 1 view .LVU627
+ 2123 000e C36D     		ldr	r3, [r0, #92]
+ 2124              	.LVL155:
+3565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2125              		.loc 1 3565 5 is_stmt 0 view .LVU628
+ 2126 0010 43F40073 		orr	r3, r3, #512
+ 2127 0014 C365     		str	r3, [r0, #92]
+3571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 2128              		.loc 1 3571 5 is_stmt 1 view .LVU629
+3571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 2129              		.loc 1 3571 14 is_stmt 0 view .LVU630
+ 2130 0016 0368     		ldr	r3, [r0]
+3571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 2131              		.loc 1 3571 24 view .LVU631
+ 2132 0018 1A68     		ldr	r2, [r3]
+3571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 2133              		.loc 1 3571 8 view .LVU632
+ 2134 001a 12F0080F 		tst	r2, #8
+ 2135 001e 14D0     		beq	.L144
+3574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2136              		.loc 1 3574 7 is_stmt 1 view .LVU633
+ 2137              	.LVL156:
+ 2138              	.LBB382:
+ 2139              	.LBI382:
+3747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2140              		.loc 2 3747 26 view .LVU634
+ 2141              	.LBB383:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2142              		.loc 2 3749 3 view .LVU635
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2143              		.loc 2 3749 12 is_stmt 0 view .LVU636
+ 2144 0020 DA68     		ldr	r2, [r3, #12]
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2145              		.loc 2 3749 103 view .LVU637
+ 2146 0022 12F4406F 		tst	r2, #3072
+ 2147 0026 20D1     		bne	.L145
+ 2148              	.LVL157:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2149              		.loc 2 3749 103 view .LVU638
+ 2150              	.LBE383:
+ 2151              	.LBE382:
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ARM GAS  /tmp/ccICigVb.s 			page 234
+
+
+ 2152              		.loc 1 3577 9 is_stmt 1 view .LVU639
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2153              		.loc 1 3577 13 is_stmt 0 view .LVU640
+ 2154 0028 DB68     		ldr	r3, [r3, #12]
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2155              		.loc 1 3577 12 view .LVU641
+ 2156 002a 13F4005F 		tst	r3, #8192
+ 2157 002e 1CD1     		bne	.L145
+3580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ 2158              		.loc 1 3580 11 is_stmt 1 view .LVU642
+ 2159 0030 C36D     		ldr	r3, [r0, #92]
+ 2160 0032 23F48073 		bic	r3, r3, #256
+ 2161 0036 C365     		str	r3, [r0, #92]
+3581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 2162              		.loc 1 3581 11 view .LVU643
+3581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 2163              		.loc 1 3581 20 is_stmt 0 view .LVU644
+ 2164 0038 C36D     		ldr	r3, [r0, #92]
+3581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 2165              		.loc 1 3581 14 view .LVU645
+ 2166 003a 13F4805F 		tst	r3, #4096
+ 2167 003e 14D1     		bne	.L145
+3583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 2168              		.loc 1 3583 13 is_stmt 1 view .LVU646
+ 2169 0040 C36D     		ldr	r3, [r0, #92]
+ 2170 0042 43F00103 		orr	r3, r3, #1
+ 2171 0046 C365     		str	r3, [r0, #92]
+ 2172 0048 0FE0     		b	.L145
+ 2173              	.L144:
+3592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2174              		.loc 1 3592 7 view .LVU647
+3592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2175              		.loc 1 3592 11 is_stmt 0 view .LVU648
+ 2176 004a DB68     		ldr	r3, [r3, #12]
+3592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2177              		.loc 1 3592 10 view .LVU649
+ 2178 004c 13F0020F 		tst	r3, #2
+ 2179 0050 0BD1     		bne	.L145
+3595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ 2180              		.loc 1 3595 9 is_stmt 1 view .LVU650
+ 2181 0052 C36D     		ldr	r3, [r0, #92]
+ 2182 0054 23F48073 		bic	r3, r3, #256
+ 2183 0058 C365     		str	r3, [r0, #92]
+3596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2184              		.loc 1 3596 9 view .LVU651
+3596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2185              		.loc 1 3596 18 is_stmt 0 view .LVU652
+ 2186 005a C36D     		ldr	r3, [r0, #92]
+3596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2187              		.loc 1 3596 12 view .LVU653
+ 2188 005c 13F4805F 		tst	r3, #4096
+ 2189 0060 03D1     		bne	.L145
+3598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 2190              		.loc 1 3598 11 is_stmt 1 view .LVU654
+ 2191 0062 C36D     		ldr	r3, [r0, #92]
+ 2192 0064 43F00103 		orr	r3, r3, #1
+ 2193 0068 C365     		str	r3, [r0, #92]
+ARM GAS  /tmp/ccICigVb.s 			page 235
+
+
+ 2194              	.L145:
+3607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2195              		.loc 1 3607 5 view .LVU655
+ 2196 006a FFF7FEFF 		bl	HAL_ADC_ConvCpltCallback
+ 2197              	.LVL158:
+ 2198              	.L142:
+3627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2199              		.loc 1 3627 1 is_stmt 0 view .LVU656
+ 2200 006e 08BD     		pop	{r3, pc}
+ 2201              	.LVL159:
+ 2202              	.L143:
+3612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 2203              		.loc 1 3612 5 is_stmt 1 view .LVU657
+3612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 2204              		.loc 1 3612 14 is_stmt 0 view .LVU658
+ 2205 0070 C26D     		ldr	r2, [r0, #92]
+3612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 2206              		.loc 1 3612 8 view .LVU659
+ 2207 0072 12F0100F 		tst	r2, #16
+ 2208 0076 04D1     		bne	.L149
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 2209              		.loc 1 3624 7 is_stmt 1 view .LVU660
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 2210              		.loc 1 3624 11 is_stmt 0 view .LVU661
+ 2211 0078 426D     		ldr	r2, [r0, #84]
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 2212              		.loc 1 3624 23 view .LVU662
+ 2213 007a 526B     		ldr	r2, [r2, #52]
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 2214              		.loc 1 3624 7 view .LVU663
+ 2215 007c 1846     		mov	r0, r3
+ 2216              	.LVL160:
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 2217              		.loc 1 3624 7 view .LVU664
+ 2218 007e 9047     		blx	r2
+ 2219              	.LVL161:
+3627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2220              		.loc 1 3627 1 view .LVU665
+ 2221 0080 F5E7     		b	.L142
+ 2222              	.LVL162:
+ 2223              	.L149:
+3618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2224              		.loc 1 3618 7 is_stmt 1 view .LVU666
+ 2225 0082 FFF7FEFF 		bl	HAL_ADC_ErrorCallback
+ 2226              	.LVL163:
+3618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2227              		.loc 1 3618 7 is_stmt 0 view .LVU667
+ 2228 0086 F2E7     		b	.L142
+ 2229              		.cfi_endproc
+ 2230              	.LFE356:
+ 2232              		.section	.text.ADC_DMAError,"ax",%progbits
+ 2233              		.align	1
+ 2234              		.global	ADC_DMAError
+ 2235              		.syntax unified
+ 2236              		.thumb
+ 2237              		.thumb_func
+ 2239              	ADC_DMAError:
+ARM GAS  /tmp/ccICigVb.s 			page 236
+
+
+ 2240              	.LVL164:
+ 2241              	.LFB358:
+3646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** /**
+3648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @brief  DMA error callback.
+3649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @param hdma pointer to DMA handle.
+3650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   * @retval None
+3651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   */
+3652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** void ADC_DMAError(DMA_HandleTypeDef *hdma)
+3653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** {
+ 2242              		.loc 1 3653 1 is_stmt 1 view -0
+ 2243              		.cfi_startproc
+ 2244              		@ args = 0, pretend = 0, frame = 0
+ 2245              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2246              		.loc 1 3653 1 is_stmt 0 view .LVU669
+ 2247 0000 08B5     		push	{r3, lr}
+ 2248              	.LCFI14:
+ 2249              		.cfi_def_cfa_offset 8
+ 2250              		.cfi_offset 3, -8
+ 2251              		.cfi_offset 14, -4
+3654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Retrieve ADC handle corresponding to current DMA handle */
+3655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 2252              		.loc 1 3655 3 is_stmt 1 view .LVU670
+ 2253              		.loc 1 3655 22 is_stmt 0 view .LVU671
+ 2254 0002 806A     		ldr	r0, [r0, #40]
+ 2255              	.LVL165:
+3656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Set ADC state */
+3658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ 2256              		.loc 1 3658 3 is_stmt 1 view .LVU672
+ 2257 0004 C36D     		ldr	r3, [r0, #92]
+ 2258 0006 43F04003 		orr	r3, r3, #64
+ 2259 000a C365     		str	r3, [r0, #92]
+3659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Set ADC error code to DMA error */
+3661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+ 2260              		.loc 1 3661 3 view .LVU673
+ 2261 000c 036E     		ldr	r3, [r0, #96]
+ 2262 000e 43F00403 		orr	r3, r3, #4
+ 2263 0012 0366     		str	r3, [r0, #96]
+3662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+3663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Error callback */
+3664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+3665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   hadc->ErrorCallback(hadc);
+3666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #else
+3667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_ADC_ErrorCallback(hadc);
+ 2264              		.loc 1 3667 3 view .LVU674
+ 2265 0014 FFF7FEFF 		bl	HAL_ADC_ErrorCallback
+ 2266              	.LVL166:
+3668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+3669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 2267              		.loc 1 3669 1 is_stmt 0 view .LVU675
+ 2268 0018 08BD     		pop	{r3, pc}
+ 2269              		.cfi_endproc
+ 2270              	.LFE358:
+ 2272              		.section	.text.HAL_ADC_ConfigChannel,"ax",%progbits
+ 2273              		.align	1
+ARM GAS  /tmp/ccICigVb.s 			page 237
+
+
+ 2274              		.global	HAL_ADC_ConfigChannel
+ 2275              		.syntax unified
+ 2276              		.thumb
+ 2277              		.thumb_func
+ 2279              	HAL_ADC_ConfigChannel:
+ 2280              	.LVL167:
+ 2281              	.LFB349:
+2759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 2282              		.loc 1 2759 1 is_stmt 1 view -0
+ 2283              		.cfi_startproc
+ 2284              		@ args = 0, pretend = 0, frame = 8
+ 2285              		@ frame_needed = 0, uses_anonymous_args = 0
+2759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 2286              		.loc 1 2759 1 is_stmt 0 view .LVU677
+ 2287 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 2288              	.LCFI15:
+ 2289              		.cfi_def_cfa_offset 20
+ 2290              		.cfi_offset 4, -20
+ 2291              		.cfi_offset 5, -16
+ 2292              		.cfi_offset 6, -12
+ 2293              		.cfi_offset 7, -8
+ 2294              		.cfi_offset 14, -4
+ 2295 0002 83B0     		sub	sp, sp, #12
+ 2296              	.LCFI16:
+ 2297              		.cfi_def_cfa_offset 32
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpOffsetShifted;
+ 2298              		.loc 1 2760 3 is_stmt 1 view .LVU678
+ 2299              	.LVL168:
+2761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_config_internal_channel;
+ 2300              		.loc 1 2761 3 view .LVU679
+2762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   __IO uint32_t wait_loop_index = 0UL;
+ 2301              		.loc 1 2762 3 view .LVU680
+2763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+ 2302              		.loc 1 2763 3 view .LVU681
+2763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+ 2303              		.loc 1 2763 17 is_stmt 0 view .LVU682
+ 2304 0004 0023     		movs	r3, #0
+ 2305 0006 0193     		str	r3, [sp, #4]
+2764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_injected;
+ 2306              		.loc 1 2764 3 is_stmt 1 view .LVU683
+2765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2307              		.loc 1 2765 3 view .LVU684
+2768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+ 2308              		.loc 1 2768 3 view .LVU685
+2769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+ 2309              		.loc 1 2769 3 view .LVU686
+2770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
+ 2310              		.loc 1 2770 3 view .LVU687
+2771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
+ 2311              		.loc 1 2771 3 view .LVU688
+2772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
+ 2312              		.loc 1 2772 3 view .LVU689
+2773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2313              		.loc 1 2773 3 view .LVU690
+2777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2314              		.loc 1 2777 3 view .LVU691
+2780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ARM GAS  /tmp/ccICigVb.s 			page 238
+
+
+ 2315              		.loc 1 2780 3 view .LVU692
+2786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 2316              		.loc 1 2786 5 view .LVU693
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2317              		.loc 1 2790 3 view .LVU694
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2318              		.loc 1 2790 3 view .LVU695
+ 2319 0008 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 2320 000c 012B     		cmp	r3, #1
+ 2321 000e 00F01E82 		beq	.L209
+ 2322 0012 0446     		mov	r4, r0
+ 2323 0014 0D46     		mov	r5, r1
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2324              		.loc 1 2790 3 discriminator 2 view .LVU696
+ 2325 0016 0123     		movs	r3, #1
+ 2326 0018 80F85830 		strb	r3, [r0, #88]
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2327              		.loc 1 2790 3 discriminator 2 view .LVU697
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 2328              		.loc 1 2797 3 discriminator 2 view .LVU698
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 2329              		.loc 1 2797 7 is_stmt 0 discriminator 2 view .LVU699
+ 2330 001c 0068     		ldr	r0, [r0]
+ 2331              	.LVL169:
+ 2332              	.LBB384:
+ 2333              	.LBI384:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2334              		.loc 2 6851 26 is_stmt 1 discriminator 2 view .LVU700
+ 2335              	.LBB385:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2336              		.loc 2 6853 3 discriminator 2 view .LVU701
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2337              		.loc 2 6853 12 is_stmt 0 discriminator 2 view .LVU702
+ 2338 001e 8368     		ldr	r3, [r0, #8]
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2339              		.loc 2 6853 74 discriminator 2 view .LVU703
+ 2340 0020 13F0040F 		tst	r3, #4
+ 2341 0024 09D0     		beq	.L154
+ 2342              	.LVL170:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2343              		.loc 2 6853 74 discriminator 2 view .LVU704
+ 2344              	.LBE385:
+ 2345              	.LBE384:
+2957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2346              		.loc 1 2957 5 is_stmt 1 view .LVU705
+ 2347 0026 E36D     		ldr	r3, [r4, #92]
+ 2348 0028 43F02003 		orr	r3, r3, #32
+ 2349 002c E365     		str	r3, [r4, #92]
+2959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 2350              		.loc 1 2959 5 view .LVU706
+ 2351              	.LVL171:
+2959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 2352              		.loc 1 2959 20 is_stmt 0 view .LVU707
+ 2353 002e 0120     		movs	r0, #1
+ 2354              	.LVL172:
+ 2355              	.L155:
+2963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ARM GAS  /tmp/ccICigVb.s 			page 239
+
+
+ 2356              		.loc 1 2963 3 is_stmt 1 view .LVU708
+2963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2357              		.loc 1 2963 3 view .LVU709
+ 2358 0030 0023     		movs	r3, #0
+ 2359 0032 84F85830 		strb	r3, [r4, #88]
+2963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2360              		.loc 1 2963 3 view .LVU710
+2966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 2361              		.loc 1 2966 3 view .LVU711
+ 2362              	.LVL173:
+ 2363              	.L153:
+2967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2364              		.loc 1 2967 1 is_stmt 0 view .LVU712
+ 2365 0036 03B0     		add	sp, sp, #12
+ 2366              	.LCFI17:
+ 2367              		.cfi_remember_state
+ 2368              		.cfi_def_cfa_offset 20
+ 2369              		@ sp needed
+ 2370 0038 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 2371              	.LVL174:
+ 2372              	.L154:
+ 2373              	.LCFI18:
+ 2374              		.cfi_restore_state
+2800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2375              		.loc 1 2800 5 is_stmt 1 view .LVU713
+ 2376 003a 0A68     		ldr	r2, [r1]
+ 2377 003c 4968     		ldr	r1, [r1, #4]
+ 2378              	.LVL175:
+2800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2379              		.loc 1 2800 5 is_stmt 0 view .LVU714
+ 2380 003e FFF7FEFF 		bl	LL_ADC_REG_SetSequencerRanks
+ 2381              	.LVL176:
+2807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 2382              		.loc 1 2807 5 is_stmt 1 view .LVU715
+2807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 2383              		.loc 1 2807 46 is_stmt 0 view .LVU716
+ 2384 0042 2068     		ldr	r0, [r4]
+ 2385              	.LVL177:
+ 2386              	.LBB386:
+ 2387              	.LBI386:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2388              		.loc 2 6851 26 is_stmt 1 view .LVU717
+ 2389              	.LBB387:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2390              		.loc 2 6853 3 view .LVU718
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2391              		.loc 2 6853 12 is_stmt 0 view .LVU719
+ 2392 0044 8368     		ldr	r3, [r0, #8]
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2393              		.loc 2 6853 74 view .LVU720
+ 2394 0046 13F00403 		ands	r3, r3, #4
+ 2395 004a 00D0     		beq	.L156
+ 2396 004c 0123     		movs	r3, #1
+ 2397              	.L156:
+ 2398              	.LVL178:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2399              		.loc 2 6853 74 view .LVU721
+ARM GAS  /tmp/ccICigVb.s 			page 240
+
+
+ 2400              	.LBE387:
+ 2401              	.LBE386:
+2808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ 2402              		.loc 1 2808 5 is_stmt 1 view .LVU722
+ 2403              	.LBB388:
+ 2404              	.LBI388:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2405              		.loc 2 7076 26 view .LVU723
+ 2406              	.LBB389:
+ 2407              		.loc 2 7078 3 view .LVU724
+ 2408              		.loc 2 7078 12 is_stmt 0 view .LVU725
+ 2409 004e 8668     		ldr	r6, [r0, #8]
+ 2410              		.loc 2 7078 76 view .LVU726
+ 2411 0050 16F00806 		ands	r6, r6, #8
+ 2412 0054 00D0     		beq	.L157
+ 2413 0056 0126     		movs	r6, #1
+ 2414              	.L157:
+ 2415              	.LVL179:
+ 2416              		.loc 2 7078 76 view .LVU727
+ 2417              	.LBE389:
+ 2418              	.LBE388:
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 2419              		.loc 1 2809 5 is_stmt 1 view .LVU728
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 2420              		.loc 1 2809 8 is_stmt 0 view .LVU729
+ 2421 0058 002B     		cmp	r3, #0
+ 2422 005a 3ED1     		bne	.L158
+2810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        )
+ 2423              		.loc 1 2810 9 view .LVU730
+ 2424 005c 002E     		cmp	r6, #0
+ 2425 005e 3CD1     		bne	.L158
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2426              		.loc 1 2814 7 is_stmt 1 view .LVU731
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2427              		.loc 1 2814 18 is_stmt 0 view .LVU732
+ 2428 0060 AA68     		ldr	r2, [r5, #8]
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2429              		.loc 1 2814 10 view .LVU733
+ 2430 0062 B2F1004F 		cmp	r2, #-2147483648
+ 2431 0066 6BD0     		beq	.L228
+2825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2432              		.loc 1 2825 9 is_stmt 1 view .LVU734
+ 2433 0068 2968     		ldr	r1, [r5]
+ 2434 006a FFF7FEFF 		bl	LL_ADC_SetChannelSamplingTime
+ 2435              	.LVL180:
+2828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 2436              		.loc 1 2828 9 view .LVU735
+ 2437 006e 2268     		ldr	r2, [r4]
+ 2438              	.LVL181:
+ 2439              	.LBB390:
+ 2440              	.LBI390:
+3560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2441              		.loc 2 3560 22 view .LVU736
+ 2442              	.LBB391:
+3562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2443              		.loc 2 3562 3 view .LVU737
+ 2444 0070 5369     		ldr	r3, [r2, #20]
+ARM GAS  /tmp/ccICigVb.s 			page 241
+
+
+ 2445 0072 23F00043 		bic	r3, r3, #-2147483648
+ 2446 0076 5361     		str	r3, [r2, #20]
+ 2447              	.LVL182:
+ 2448              	.L160:
+3562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2449              		.loc 2 3562 3 is_stmt 0 view .LVU738
+ 2450              	.LBE391:
+ 2451              	.LBE390:
+2835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2452              		.loc 1 2835 7 is_stmt 1 view .LVU739
+2835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2453              		.loc 1 2835 26 is_stmt 0 view .LVU740
+ 2454 0078 6969     		ldr	r1, [r5, #20]
+ 2455 007a 2268     		ldr	r2, [r4]
+ 2456 007c D368     		ldr	r3, [r2, #12]
+ 2457 007e C3F3C103 		ubfx	r3, r3, #3, #2
+ 2458 0082 5B00     		lsls	r3, r3, #1
+2835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2459              		.loc 1 2835 24 view .LVU741
+ 2460 0084 9940     		lsls	r1, r1, r3
+ 2461              	.LVL183:
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2462              		.loc 1 2837 7 is_stmt 1 view .LVU742
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2463              		.loc 1 2837 18 is_stmt 0 view .LVU743
+ 2464 0086 2869     		ldr	r0, [r5, #16]
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2465              		.loc 1 2837 10 view .LVU744
+ 2466 0088 0428     		cmp	r0, #4
+ 2467 008a 66D0     		beq	.L161
+2840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2468              		.loc 1 2840 9 is_stmt 1 view .LVU745
+ 2469              	.LVL184:
+ 2470              	.LBB392:
+ 2471              	.LBI392:
+3220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2472              		.loc 2 3220 22 view .LVU746
+ 2473              	.LBB393:
+3222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2474              		.loc 2 3222 3 view .LVU747
+3222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2475              		.loc 2 3222 25 is_stmt 0 view .LVU748
+ 2476 008c 6032     		adds	r2, r2, #96
+ 2477              	.LVL185:
+3224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ 2478              		.loc 2 3224 3 is_stmt 1 view .LVU749
+ 2479 008e 52F82070 		ldr	r7, [r2, r0, lsl #2]
+ 2480 0092 A84B     		ldr	r3, .L239
+ 2481 0094 3B40     		ands	r3, r3, r7
+ 2482 0096 2F68     		ldr	r7, [r5]
+ 2483 0098 07F0F84C 		and	ip, r7, #2080374784
+ 2484 009c 41EA0C01 		orr	r1, r1, ip
+ 2485              	.LVL186:
+3224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ 2486              		.loc 2 3224 3 is_stmt 0 view .LVU750
+ 2487 00a0 0B43     		orrs	r3, r3, r1
+ 2488 00a2 43F00043 		orr	r3, r3, #-2147483648
+ARM GAS  /tmp/ccICigVb.s 			page 242
+
+
+ 2489 00a6 42F82030 		str	r3, [r2, r0, lsl #2]
+ 2490              	.LVL187:
+3224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ 2491              		.loc 2 3224 3 view .LVU751
+ 2492              	.LBE393:
+ 2493              	.LBE392:
+2842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSaturation));
+ 2494              		.loc 1 2842 9 is_stmt 1 view .LVU752
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* Set ADC selected offset sign & saturation */
+ 2495              		.loc 1 2843 9 view .LVU753
+2845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         LL_ADC_SetOffsetSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSaturatio
+ 2496              		.loc 1 2845 9 view .LVU754
+ 2497 00aa 2368     		ldr	r3, [r4]
+ 2498 00ac 2869     		ldr	r0, [r5, #16]
+ 2499 00ae AA69     		ldr	r2, [r5, #24]
+ 2500              	.LVL188:
+ 2501              	.LBB394:
+ 2502              	.LBI394:
+3417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2503              		.loc 2 3417 22 view .LVU755
+ 2504              	.LBB395:
+3419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2505              		.loc 2 3419 3 view .LVU756
+3419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2506              		.loc 2 3419 25 is_stmt 0 view .LVU757
+ 2507 00b0 6033     		adds	r3, r3, #96
+ 2508              	.LVL189:
+3421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSETPOS,
+ 2509              		.loc 2 3421 3 is_stmt 1 view .LVU758
+ 2510 00b2 53F82010 		ldr	r1, [r3, r0, lsl #2]
+ 2511 00b6 21F08071 		bic	r1, r1, #16777216
+ 2512 00ba 0A43     		orrs	r2, r2, r1
+ 2513              	.LVL190:
+3421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSETPOS,
+ 2514              		.loc 2 3421 3 is_stmt 0 view .LVU759
+ 2515 00bc 43F82020 		str	r2, [r3, r0, lsl #2]
+ 2516              	.LVL191:
+3421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSETPOS,
+ 2517              		.loc 2 3421 3 view .LVU760
+ 2518              	.LBE395:
+ 2519              	.LBE394:
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 2520              		.loc 1 2846 9 is_stmt 1 view .LVU761
+ 2521 00c0 2368     		ldr	r3, [r4]
+ 2522 00c2 2969     		ldr	r1, [r5, #16]
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 2523              		.loc 1 2846 83 is_stmt 0 view .LVU762
+ 2524 00c4 2A7F     		ldrb	r2, [r5, #28]	@ zero_extendqisi2
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 2525              		.loc 1 2846 9 view .LVU763
+ 2526 00c6 012A     		cmp	r2, #1
+ 2527 00c8 44D0     		beq	.L229
+ 2528              	.LVL192:
+ 2529              	.L162:
+ 2530              	.LBB396:
+ 2531              	.LBI396:
+3472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ARM GAS  /tmp/ccICigVb.s 			page 243
+
+
+ 2532              		.loc 2 3472 22 is_stmt 1 discriminator 4 view .LVU764
+ 2533              	.LBB397:
+3474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2534              		.loc 2 3474 3 discriminator 4 view .LVU765
+3474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2535              		.loc 2 3474 25 is_stmt 0 discriminator 4 view .LVU766
+ 2536 00ca 6033     		adds	r3, r3, #96
+ 2537              	.LVL193:
+3476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_SATEN,
+ 2538              		.loc 2 3476 3 is_stmt 1 discriminator 4 view .LVU767
+ 2539 00cc 53F82120 		ldr	r2, [r3, r1, lsl #2]
+ 2540 00d0 22F00072 		bic	r2, r2, #33554432
+ 2541 00d4 3243     		orrs	r2, r2, r6
+ 2542 00d6 43F82120 		str	r2, [r3, r1, lsl #2]
+ 2543              	.LVL194:
+ 2544              	.L158:
+3476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_SATEN,
+ 2545              		.loc 2 3476 3 is_stmt 0 discriminator 4 view .LVU768
+ 2546              	.LBE397:
+ 2547              	.LBE396:
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 2548              		.loc 1 2878 5 is_stmt 1 view .LVU769
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 2549              		.loc 1 2878 9 is_stmt 0 view .LVU770
+ 2550 00da 2368     		ldr	r3, [r4]
+ 2551              	.LVL195:
+ 2552              	.LBB398:
+ 2553              	.LBI398:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2554              		.loc 2 6729 26 is_stmt 1 view .LVU771
+ 2555              	.LBB399:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2556              		.loc 2 6731 3 view .LVU772
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2557              		.loc 2 6731 12 is_stmt 0 view .LVU773
+ 2558 00dc 9A68     		ldr	r2, [r3, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2559              		.loc 2 6731 68 view .LVU774
+ 2560 00de 12F0010F 		tst	r2, #1
+ 2561 00e2 12D1     		bne	.L178
+ 2562              	.LVL196:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2563              		.loc 2 6731 68 view .LVU775
+ 2564              	.LBE399:
+ 2565              	.LBE398:
+2881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2566              		.loc 1 2881 7 is_stmt 1 view .LVU776
+ 2567 00e4 2A68     		ldr	r2, [r5]
+ 2568 00e6 E868     		ldr	r0, [r5, #12]
+ 2569              	.LVL197:
+ 2570              	.LBB400:
+ 2571              	.LBI400:
+5495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2572              		.loc 2 5495 22 view .LVU777
+ 2573              	.LBB401:
+5501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+ 2574              		.loc 2 5501 3 view .LVU778
+ARM GAS  /tmp/ccICigVb.s 			page 244
+
+
+5501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+ 2575              		.loc 2 5501 6 is_stmt 0 view .LVU779
+ 2576 00e8 9349     		ldr	r1, .L239+4
+ 2577 00ea 8842     		cmp	r0, r1
+ 2578 00ec 00F09C80 		beq	.L230
+5508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 2579              		.loc 2 5508 5 is_stmt 1 view .LVU780
+ 2580 00f0 D3F8B010 		ldr	r1, [r3, #176]
+ 2581 00f4 C2F31202 		ubfx	r2, r2, #0, #19
+ 2582              	.LVL198:
+5508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 2583              		.loc 2 5508 5 is_stmt 0 view .LVU781
+ 2584 00f8 21EA0202 		bic	r2, r1, r2
+ 2585 00fc C3F8B020 		str	r2, [r3, #176]
+ 2586              	.LVL199:
+ 2587              	.L180:
+5508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 2588              		.loc 2 5508 5 view .LVU782
+ 2589              	.LBE401:
+ 2590              	.LBE400:
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2591              		.loc 1 2884 7 is_stmt 1 view .LVU783
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2592              		.loc 1 2884 18 is_stmt 0 view .LVU784
+ 2593 0100 EA68     		ldr	r2, [r5, #12]
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2594              		.loc 1 2884 10 view .LVU785
+ 2595 0102 8D4B     		ldr	r3, .L239+4
+ 2596 0104 9A42     		cmp	r2, r3
+ 2597 0106 00F09780 		beq	.L231
+ 2598              	.L178:
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 2599              		.loc 1 2901 5 is_stmt 1 view .LVU786
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 2600              		.loc 1 2901 9 is_stmt 0 view .LVU787
+ 2601 010a 2B68     		ldr	r3, [r5]
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 2602              		.loc 1 2901 8 view .LVU788
+ 2603 010c 8B4A     		ldr	r2, .L239+8
+ 2604 010e 1342     		tst	r3, r2
+ 2605 0110 00F09581 		beq	.L221
+2903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2606              		.loc 1 2903 7 is_stmt 1 view .LVU789
+ 2607              	.LVL200:
+ 2608              	.LBB403:
+ 2609              	.LBI403:
+2877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2610              		.loc 2 2877 26 view .LVU790
+ 2611              	.LBB404:
+2879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2612              		.loc 2 2879 3 view .LVU791
+2879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2613              		.loc 2 2879 21 is_stmt 0 view .LVU792
+ 2614 0114 8A4A     		ldr	r2, .L239+12
+ 2615 0116 9268     		ldr	r2, [r2, #8]
+2879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2616              		.loc 2 2879 10 view .LVU793
+ARM GAS  /tmp/ccICigVb.s 			page 245
+
+
+ 2617 0118 02F0E071 		and	r1, r2, #29360128
+ 2618              	.LVL201:
+2879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2619              		.loc 2 2879 10 view .LVU794
+ 2620              	.LBE404:
+ 2621              	.LBE403:
+2907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ 2622              		.loc 1 2907 7 is_stmt 1 view .LVU795
+2907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ 2623              		.loc 1 2907 10 is_stmt 0 view .LVU796
+ 2624 011c 8948     		ldr	r0, .L239+16
+ 2625 011e 8342     		cmp	r3, r0
+ 2626 0120 00F04481 		beq	.L204
+2907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ 2627              		.loc 1 2907 62 discriminator 1 view .LVU797
+ 2628 0124 8848     		ldr	r0, .L239+20
+ 2629 0126 8342     		cmp	r3, r0
+ 2630 0128 00F04081 		beq	.L204
+ 2631              	.L205:
+2927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2632              		.loc 1 2927 12 is_stmt 1 view .LVU798
+2927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 2633              		.loc 1 2927 15 is_stmt 0 view .LVU799
+ 2634 012c 8748     		ldr	r0, .L239+24
+ 2635 012e 8342     		cmp	r3, r0
+ 2636 0130 00F06281 		beq	.L232
+ 2637              	.L208:
+2935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ 2638              		.loc 1 2935 12 is_stmt 1 view .LVU800
+2935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ 2639              		.loc 1 2935 15 is_stmt 0 view .LVU801
+ 2640 0134 8648     		ldr	r0, .L239+28
+ 2641 0136 8342     		cmp	r3, r0
+ 2642 0138 00F07081 		beq	.L233
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpOffsetShifted;
+ 2643              		.loc 1 2760 21 view .LVU802
+ 2644 013c 0020     		movs	r0, #0
+ 2645 013e 77E7     		b	.L155
+ 2646              	.LVL202:
+ 2647              	.L228:
+2817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 2648              		.loc 1 2817 9 is_stmt 1 view .LVU803
+ 2649 0140 0022     		movs	r2, #0
+ 2650 0142 2968     		ldr	r1, [r5]
+ 2651 0144 FFF7FEFF 		bl	LL_ADC_SetChannelSamplingTime
+ 2652              	.LVL203:
+2820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 2653              		.loc 1 2820 9 view .LVU804
+ 2654 0148 2268     		ldr	r2, [r4]
+ 2655              	.LVL204:
+ 2656              	.LBB405:
+ 2657              	.LBI405:
+3560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2658              		.loc 2 3560 22 view .LVU805
+ 2659              	.LBB406:
+3562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2660              		.loc 2 3562 3 view .LVU806
+ARM GAS  /tmp/ccICigVb.s 			page 246
+
+
+ 2661 014a 5369     		ldr	r3, [r2, #20]
+ 2662 014c 43F00043 		orr	r3, r3, #-2147483648
+ 2663 0150 5361     		str	r3, [r2, #20]
+3563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2664              		.loc 2 3563 1 is_stmt 0 view .LVU807
+ 2665 0152 91E7     		b	.L160
+ 2666              	.LVL205:
+ 2667              	.L229:
+3563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2668              		.loc 2 3563 1 view .LVU808
+ 2669              	.LBE406:
+ 2670              	.LBE405:
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 2671              		.loc 1 2846 9 view .LVU809
+ 2672 0154 4FF00076 		mov	r6, #33554432
+ 2673              	.LVL206:
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 2674              		.loc 1 2846 9 view .LVU810
+ 2675 0158 B7E7     		b	.L162
+ 2676              	.LVL207:
+ 2677              	.L161:
+2852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2678              		.loc 1 2852 9 is_stmt 1 view .LVU811
+ 2679              	.LBB407:
+ 2680              	.LBI407:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2681              		.loc 2 3303 26 view .LVU812
+ 2682              	.LBB408:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2683              		.loc 2 3305 3 view .LVU813
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2684              		.loc 2 3307 3 view .LVU814
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2685              		.loc 2 3307 10 is_stmt 0 view .LVU815
+ 2686 015a 136E     		ldr	r3, [r2, #96]
+ 2687              	.LVL208:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2688              		.loc 2 3307 10 view .LVU816
+ 2689              	.LBE408:
+ 2690              	.LBE407:
+ 2691              	.LBB409:
+ 2692              	.LBI409:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2693              		.loc 2 3303 26 is_stmt 1 view .LVU817
+ 2694              	.LBB410:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2695              		.loc 2 3305 3 view .LVU818
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2696              		.loc 2 3307 3 view .LVU819
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2697              		.loc 2 3307 10 is_stmt 0 view .LVU820
+ 2698 015c 116E     		ldr	r1, [r2, #96]
+ 2699              	.LVL209:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2700              		.loc 2 3307 10 view .LVU821
+ 2701              	.LBE410:
+ 2702              	.LBE409:
+ARM GAS  /tmp/ccICigVb.s 			page 247
+
+
+2852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2703              		.loc 1 2852 13 view .LVU822
+ 2704 015e C1F38461 		ubfx	r1, r1, #26, #5
+2853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2705              		.loc 1 2853 16 view .LVU823
+ 2706 0162 2B68     		ldr	r3, [r5]
+ 2707 0164 C3F31200 		ubfx	r0, r3, #0, #19
+ 2708 0168 78BB     		cbnz	r0, .L163
+2853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2709              		.loc 1 2853 16 discriminator 1 view .LVU824
+ 2710 016a C3F38463 		ubfx	r3, r3, #26, #5
+ 2711              	.L164:
+2852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2712              		.loc 1 2852 12 view .LVU825
+ 2713 016e 9942     		cmp	r1, r3
+ 2714 0170 33D0     		beq	.L234
+ 2715              	.L166:
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2716              		.loc 1 2857 9 is_stmt 1 view .LVU826
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2717              		.loc 1 2857 13 is_stmt 0 view .LVU827
+ 2718 0172 2168     		ldr	r1, [r4]
+ 2719              	.LVL210:
+ 2720              	.LBB411:
+ 2721              	.LBI411:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2722              		.loc 2 3303 26 is_stmt 1 view .LVU828
+ 2723              	.LBB412:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2724              		.loc 2 3305 3 view .LVU829
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2725              		.loc 2 3307 3 view .LVU830
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2726              		.loc 2 3307 10 is_stmt 0 view .LVU831
+ 2727 0174 4B6E     		ldr	r3, [r1, #100]
+ 2728              	.LVL211:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2729              		.loc 2 3307 10 view .LVU832
+ 2730              	.LBE412:
+ 2731              	.LBE411:
+ 2732              	.LBB413:
+ 2733              	.LBI413:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2734              		.loc 2 3303 26 is_stmt 1 view .LVU833
+ 2735              	.LBB414:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2736              		.loc 2 3305 3 view .LVU834
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2737              		.loc 2 3307 3 view .LVU835
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2738              		.loc 2 3307 10 is_stmt 0 view .LVU836
+ 2739 0176 4A6E     		ldr	r2, [r1, #100]
+ 2740              	.LVL212:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2741              		.loc 2 3307 10 view .LVU837
+ 2742              	.LBE414:
+ 2743              	.LBE413:
+ARM GAS  /tmp/ccICigVb.s 			page 248
+
+
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2744              		.loc 1 2857 13 view .LVU838
+ 2745 0178 C2F38462 		ubfx	r2, r2, #26, #5
+2858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2746              		.loc 1 2858 16 view .LVU839
+ 2747 017c 2B68     		ldr	r3, [r5]
+ 2748 017e C3F31200 		ubfx	r0, r3, #0, #19
+ 2749 0182 78BB     		cbnz	r0, .L167
+2858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2750              		.loc 1 2858 16 discriminator 1 view .LVU840
+ 2751 0184 C3F38463 		ubfx	r3, r3, #26, #5
+ 2752              	.L168:
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2753              		.loc 1 2857 12 view .LVU841
+ 2754 0188 9A42     		cmp	r2, r3
+ 2755 018a 33D0     		beq	.L235
+ 2756              	.L170:
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2757              		.loc 1 2862 9 is_stmt 1 view .LVU842
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2758              		.loc 1 2862 13 is_stmt 0 view .LVU843
+ 2759 018c 2168     		ldr	r1, [r4]
+ 2760              	.LVL213:
+ 2761              	.LBB415:
+ 2762              	.LBI415:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2763              		.loc 2 3303 26 is_stmt 1 view .LVU844
+ 2764              	.LBB416:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2765              		.loc 2 3305 3 view .LVU845
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2766              		.loc 2 3307 3 view .LVU846
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2767              		.loc 2 3307 10 is_stmt 0 view .LVU847
+ 2768 018e 8B6E     		ldr	r3, [r1, #104]
+ 2769              	.LVL214:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2770              		.loc 2 3307 10 view .LVU848
+ 2771              	.LBE416:
+ 2772              	.LBE415:
+ 2773              	.LBB417:
+ 2774              	.LBI417:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2775              		.loc 2 3303 26 is_stmt 1 view .LVU849
+ 2776              	.LBB418:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2777              		.loc 2 3305 3 view .LVU850
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2778              		.loc 2 3307 3 view .LVU851
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2779              		.loc 2 3307 10 is_stmt 0 view .LVU852
+ 2780 0190 8A6E     		ldr	r2, [r1, #104]
+ 2781              	.LVL215:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2782              		.loc 2 3307 10 view .LVU853
+ 2783              	.LBE418:
+ 2784              	.LBE417:
+ARM GAS  /tmp/ccICigVb.s 			page 249
+
+
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2785              		.loc 1 2862 13 view .LVU854
+ 2786 0192 C2F38462 		ubfx	r2, r2, #26, #5
+2863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2787              		.loc 1 2863 16 view .LVU855
+ 2788 0196 2B68     		ldr	r3, [r5]
+ 2789 0198 C3F31200 		ubfx	r0, r3, #0, #19
+ 2790 019c 78BB     		cbnz	r0, .L171
+2863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2791              		.loc 1 2863 16 discriminator 1 view .LVU856
+ 2792 019e C3F38463 		ubfx	r3, r3, #26, #5
+ 2793              	.L172:
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2794              		.loc 1 2862 12 view .LVU857
+ 2795 01a2 9A42     		cmp	r2, r3
+ 2796 01a4 33D0     		beq	.L236
+ 2797              	.L174:
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2798              		.loc 1 2867 9 is_stmt 1 view .LVU858
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2799              		.loc 1 2867 13 is_stmt 0 view .LVU859
+ 2800 01a6 2168     		ldr	r1, [r4]
+ 2801              	.LVL216:
+ 2802              	.LBB419:
+ 2803              	.LBI419:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2804              		.loc 2 3303 26 is_stmt 1 view .LVU860
+ 2805              	.LBB420:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2806              		.loc 2 3305 3 view .LVU861
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2807              		.loc 2 3307 3 view .LVU862
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2808              		.loc 2 3307 10 is_stmt 0 view .LVU863
+ 2809 01a8 CB6E     		ldr	r3, [r1, #108]
+ 2810              	.LVL217:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2811              		.loc 2 3307 10 view .LVU864
+ 2812              	.LBE420:
+ 2813              	.LBE419:
+ 2814              	.LBB421:
+ 2815              	.LBI421:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2816              		.loc 2 3303 26 is_stmt 1 view .LVU865
+ 2817              	.LBB422:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2818              		.loc 2 3305 3 view .LVU866
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2819              		.loc 2 3307 3 view .LVU867
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2820              		.loc 2 3307 10 is_stmt 0 view .LVU868
+ 2821 01aa CA6E     		ldr	r2, [r1, #108]
+ 2822              	.LVL218:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2823              		.loc 2 3307 10 view .LVU869
+ 2824              	.LBE422:
+ 2825              	.LBE421:
+ARM GAS  /tmp/ccICigVb.s 			page 250
+
+
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2826              		.loc 1 2867 13 view .LVU870
+ 2827 01ac C2F38462 		ubfx	r2, r2, #26, #5
+2868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2828              		.loc 1 2868 16 view .LVU871
+ 2829 01b0 2B68     		ldr	r3, [r5]
+ 2830 01b2 C3F31200 		ubfx	r0, r3, #0, #19
+ 2831 01b6 78BB     		cbnz	r0, .L175
+2868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 2832              		.loc 1 2868 16 discriminator 1 view .LVU872
+ 2833 01b8 C3F38463 		ubfx	r3, r3, #26, #5
+ 2834              	.L176:
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ 2835              		.loc 1 2867 12 view .LVU873
+ 2836 01bc 9A42     		cmp	r2, r3
+ 2837 01be 8CD1     		bne	.L158
+2870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 2838              		.loc 1 2870 11 is_stmt 1 view .LVU874
+ 2839              	.LVL219:
+ 2840              	.LBB423:
+ 2841              	.LBI423:
+3362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2842              		.loc 2 3362 22 view .LVU875
+ 2843              	.LBB424:
+3364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2844              		.loc 2 3364 3 view .LVU876
+3366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN,
+ 2845              		.loc 2 3366 3 view .LVU877
+ 2846 01c0 CB6E     		ldr	r3, [r1, #108]
+ 2847 01c2 23F00043 		bic	r3, r3, #-2147483648
+ 2848 01c6 CB66     		str	r3, [r1, #108]
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2849              		.loc 2 3369 1 is_stmt 0 view .LVU878
+ 2850 01c8 87E7     		b	.L158
+ 2851              	.LVL220:
+ 2852              	.L163:
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2853              		.loc 2 3369 1 view .LVU879
+ 2854              	.LBE424:
+ 2855              	.LBE423:
+ 2856              	.LBB425:
+ 2857              	.LBI425:
+ 2858              		.file 3 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.2.0
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     08. May 2019
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+ARM GAS  /tmp/ccICigVb.s 			page 251
+
+
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ARM GAS  /tmp/ccICigVb.s 			page 252
+
+
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
+ARM GAS  /tmp/ccICigVb.s 			page 253
+
+
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ARM GAS  /tmp/ccICigVb.s 			page 254
+
+
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccICigVb.s 			page 255
+
+
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ARM GAS  /tmp/ccICigVb.s 			page 256
+
+
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ARM GAS  /tmp/ccICigVb.s 			page 257
+
+
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ARM GAS  /tmp/ccICigVb.s 			page 258
+
+
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ARM GAS  /tmp/ccICigVb.s 			page 259
+
+
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ARM GAS  /tmp/ccICigVb.s 			page 260
+
+
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccICigVb.s 			page 261
+
+
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccICigVb.s 			page 262
+
+
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ARM GAS  /tmp/ccICigVb.s 			page 263
+
+
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ARM GAS  /tmp/ccICigVb.s 			page 264
+
+
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ARM GAS  /tmp/ccICigVb.s 			page 265
+
+
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ARM GAS  /tmp/ccICigVb.s 			page 266
+
+
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 882:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 883:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 885:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 888:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 900:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 901:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 902:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 904:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 906:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 908:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 913:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 915:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 916:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 918:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 922:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 923:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 925:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccICigVb.s 			page 267
+
+
+ 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 928:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 930:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 931:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 932:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 938:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 940:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 942:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 943:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+ 945:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 946:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 947:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 948:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 949:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 950:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ 952:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 953:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 954:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
+ 956:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 958:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 959:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 960:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 961:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 962:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
+ 963:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
+ 964:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 965:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 966:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 967:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+ 968:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 969:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ 970:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_bswap32(value);
+ 971:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 972:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 974:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 975:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 976:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 977:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 978:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 979:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 980:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 982:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ARM GAS  /tmp/ccICigVb.s 			page 268
+
+
+ 984:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 985:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 986:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+ 987:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 989:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 990:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 991:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 992:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 993:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 994:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 995:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 996:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 997:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
+ 998:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 999:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+1000:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1001:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+1002:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1003:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1004:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
+1005:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1006:Drivers/CMSIS/Include/cmsis_gcc.h ****   int16_t result;
+1007:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1008:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+1009:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+1010:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1011:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1014:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1015:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
+1016:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
+1017:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
+1018:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
+1019:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Rotated value
+1020:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1021:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+1022:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1023:Drivers/CMSIS/Include/cmsis_gcc.h ****   op2 %= 32U;
+1024:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (op2 == 0U)
+1025:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1026:Drivers/CMSIS/Include/cmsis_gcc.h ****     return op1;
+1027:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1028:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
+1029:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1030:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1031:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1032:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1033:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Breakpoint
+1034:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
+1035:Drivers/CMSIS/Include/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
+1036:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
+1037:Drivers/CMSIS/Include/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
+1038:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1039:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+1040:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccICigVb.s 			page 269
+
+
+1041:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1042:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1043:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse bit order of value
+1044:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
+1045:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+1046:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+1047:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+ 2859              		.loc 3 1048 31 is_stmt 1 discriminator 2 view .LVU880
+ 2860              	.LBB426:
+1049:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1050:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 2861              		.loc 3 1050 3 discriminator 2 view .LVU881
+1051:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+1053:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+1054:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+1055:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 2862              		.loc 3 1055 4 discriminator 2 view .LVU882
+ 2863              		.syntax unified
+ 2864              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2865 01ca 93FAA3F3 		rbit r3, r3
+ 2866              	@ 0 "" 2
+ 2867              	.LVL221:
+1056:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1057:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+1058:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1059:Drivers/CMSIS/Include/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
+1060:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
+1061:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1062:Drivers/CMSIS/Include/cmsis_gcc.h ****     result <<= 1U;
+1063:Drivers/CMSIS/Include/cmsis_gcc.h ****     result |= value & 1U;
+1064:Drivers/CMSIS/Include/cmsis_gcc.h ****     s--;
+1065:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1066:Drivers/CMSIS/Include/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
+1067:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1068:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 2868              		.loc 3 1068 3 discriminator 2 view .LVU883
+ 2869              		.loc 3 1068 3 is_stmt 0 discriminator 2 view .LVU884
+ 2870              		.thumb
+ 2871              		.syntax unified
+ 2872              	.LBE426:
+ 2873              	.LBE425:
+ 2874              	.LBB427:
+ 2875              	.LBI427:
+1069:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1072:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1073:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Count leading zeros
+1074:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
+1075:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
+1076:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             number of leading zeros in value
+1077:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+ 2876              		.loc 3 1078 30 is_stmt 1 discriminator 2 view .LVU885
+ 2877              	.LBB428:
+ARM GAS  /tmp/ccICigVb.s 			page 270
+
+
+1079:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1080:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+1081:Drivers/CMSIS/Include/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
+1082:Drivers/CMSIS/Include/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
+1083:Drivers/CMSIS/Include/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
+1084:Drivers/CMSIS/Include/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
+1085:Drivers/CMSIS/Include/cmsis_gcc.h ****      is non-zero".
+1086:Drivers/CMSIS/Include/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+1087:Drivers/CMSIS/Include/cmsis_gcc.h ****      single CLZ instruction.
+1088:Drivers/CMSIS/Include/cmsis_gcc.h ****    */
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (value == 0U)
+ 2878              		.loc 3 1089 3 discriminator 2 view .LVU886
+ 2879              		.loc 3 1089 6 is_stmt 0 discriminator 2 view .LVU887
+ 2880 01ce 13B1     		cbz	r3, .L210
+1090:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****     return 32U;
+1092:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1093:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_clz(value);
+ 2881              		.loc 3 1093 3 is_stmt 1 view .LVU888
+ 2882              		.loc 3 1093 10 is_stmt 0 view .LVU889
+ 2883 01d0 B3FA83F3 		clz	r3, r3
+ 2884              	.LVL222:
+ 2885              		.loc 3 1093 10 view .LVU890
+ 2886 01d4 CBE7     		b	.L164
+ 2887              	.LVL223:
+ 2888              	.L210:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 2889              		.loc 3 1091 12 view .LVU891
+ 2890 01d6 2023     		movs	r3, #32
+ 2891              	.LVL224:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 2892              		.loc 3 1091 12 view .LVU892
+ 2893 01d8 C9E7     		b	.L164
+ 2894              	.L234:
+ 2895              	.LBE428:
+ 2896              	.LBE427:
+2855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 2897              		.loc 1 2855 11 is_stmt 1 view .LVU893
+ 2898              	.LVL225:
+ 2899              	.LBB429:
+ 2900              	.LBI429:
+3362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2901              		.loc 2 3362 22 view .LVU894
+ 2902              	.LBB430:
+3364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2903              		.loc 2 3364 3 view .LVU895
+3366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN,
+ 2904              		.loc 2 3366 3 view .LVU896
+ 2905 01da 136E     		ldr	r3, [r2, #96]
+ 2906 01dc 23F00043 		bic	r3, r3, #-2147483648
+ 2907 01e0 1366     		str	r3, [r2, #96]
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2908              		.loc 2 3369 1 is_stmt 0 view .LVU897
+ 2909 01e2 C6E7     		b	.L166
+ 2910              	.LVL226:
+ 2911              	.L167:
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ARM GAS  /tmp/ccICigVb.s 			page 271
+
+
+ 2912              		.loc 2 3369 1 view .LVU898
+ 2913              	.LBE430:
+ 2914              	.LBE429:
+ 2915              	.LBB431:
+ 2916              	.LBI431:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2917              		.loc 3 1048 31 is_stmt 1 discriminator 2 view .LVU899
+ 2918              	.LBB432:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2919              		.loc 3 1050 3 discriminator 2 view .LVU900
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 2920              		.loc 3 1055 4 discriminator 2 view .LVU901
+ 2921              		.syntax unified
+ 2922              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2923 01e4 93FAA3F3 		rbit r3, r3
+ 2924              	@ 0 "" 2
+ 2925              	.LVL227:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2926              		.loc 3 1068 3 discriminator 2 view .LVU902
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2927              		.loc 3 1068 3 is_stmt 0 discriminator 2 view .LVU903
+ 2928              		.thumb
+ 2929              		.syntax unified
+ 2930              	.LBE432:
+ 2931              	.LBE431:
+ 2932              	.LBB433:
+ 2933              	.LBI433:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2934              		.loc 3 1078 30 is_stmt 1 discriminator 2 view .LVU904
+ 2935              	.LBB434:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 2936              		.loc 3 1089 3 discriminator 2 view .LVU905
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 2937              		.loc 3 1089 6 is_stmt 0 discriminator 2 view .LVU906
+ 2938 01e8 13B1     		cbz	r3, .L211
+ 2939              		.loc 3 1093 3 is_stmt 1 view .LVU907
+ 2940              		.loc 3 1093 10 is_stmt 0 view .LVU908
+ 2941 01ea B3FA83F3 		clz	r3, r3
+ 2942              	.LVL228:
+ 2943              		.loc 3 1093 10 view .LVU909
+ 2944 01ee CBE7     		b	.L168
+ 2945              	.LVL229:
+ 2946              	.L211:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 2947              		.loc 3 1091 12 view .LVU910
+ 2948 01f0 2023     		movs	r3, #32
+ 2949              	.LVL230:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 2950              		.loc 3 1091 12 view .LVU911
+ 2951 01f2 C9E7     		b	.L168
+ 2952              	.L235:
+ 2953              	.LBE434:
+ 2954              	.LBE433:
+2860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 2955              		.loc 1 2860 11 is_stmt 1 view .LVU912
+ 2956              	.LVL231:
+ 2957              	.LBB435:
+ARM GAS  /tmp/ccICigVb.s 			page 272
+
+
+ 2958              	.LBI435:
+3362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2959              		.loc 2 3362 22 view .LVU913
+ 2960              	.LBB436:
+3364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2961              		.loc 2 3364 3 view .LVU914
+3366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN,
+ 2962              		.loc 2 3366 3 view .LVU915
+ 2963 01f4 4B6E     		ldr	r3, [r1, #100]
+ 2964 01f6 23F00043 		bic	r3, r3, #-2147483648
+ 2965 01fa 4B66     		str	r3, [r1, #100]
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2966              		.loc 2 3369 1 is_stmt 0 view .LVU916
+ 2967 01fc C6E7     		b	.L170
+ 2968              	.LVL232:
+ 2969              	.L171:
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 2970              		.loc 2 3369 1 view .LVU917
+ 2971              	.LBE436:
+ 2972              	.LBE435:
+ 2973              	.LBB437:
+ 2974              	.LBI437:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2975              		.loc 3 1048 31 is_stmt 1 discriminator 2 view .LVU918
+ 2976              	.LBB438:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2977              		.loc 3 1050 3 discriminator 2 view .LVU919
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 2978              		.loc 3 1055 4 discriminator 2 view .LVU920
+ 2979              		.syntax unified
+ 2980              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2981 01fe 93FAA3F3 		rbit r3, r3
+ 2982              	@ 0 "" 2
+ 2983              	.LVL233:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2984              		.loc 3 1068 3 discriminator 2 view .LVU921
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2985              		.loc 3 1068 3 is_stmt 0 discriminator 2 view .LVU922
+ 2986              		.thumb
+ 2987              		.syntax unified
+ 2988              	.LBE438:
+ 2989              	.LBE437:
+ 2990              	.LBB439:
+ 2991              	.LBI439:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2992              		.loc 3 1078 30 is_stmt 1 discriminator 2 view .LVU923
+ 2993              	.LBB440:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 2994              		.loc 3 1089 3 discriminator 2 view .LVU924
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 2995              		.loc 3 1089 6 is_stmt 0 discriminator 2 view .LVU925
+ 2996 0202 13B1     		cbz	r3, .L212
+ 2997              		.loc 3 1093 3 is_stmt 1 view .LVU926
+ 2998              		.loc 3 1093 10 is_stmt 0 view .LVU927
+ 2999 0204 B3FA83F3 		clz	r3, r3
+ 3000              	.LVL234:
+ 3001              		.loc 3 1093 10 view .LVU928
+ARM GAS  /tmp/ccICigVb.s 			page 273
+
+
+ 3002 0208 CBE7     		b	.L172
+ 3003              	.LVL235:
+ 3004              	.L212:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3005              		.loc 3 1091 12 view .LVU929
+ 3006 020a 2023     		movs	r3, #32
+ 3007              	.LVL236:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3008              		.loc 3 1091 12 view .LVU930
+ 3009 020c C9E7     		b	.L172
+ 3010              	.L236:
+ 3011              	.LBE440:
+ 3012              	.LBE439:
+2865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 3013              		.loc 1 2865 11 is_stmt 1 view .LVU931
+ 3014              	.LVL237:
+ 3015              	.LBB441:
+ 3016              	.LBI441:
+3362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3017              		.loc 2 3362 22 view .LVU932
+ 3018              	.LBB442:
+3364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3019              		.loc 2 3364 3 view .LVU933
+3366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN,
+ 3020              		.loc 2 3366 3 view .LVU934
+ 3021 020e 8B6E     		ldr	r3, [r1, #104]
+ 3022 0210 23F00043 		bic	r3, r3, #-2147483648
+ 3023 0214 8B66     		str	r3, [r1, #104]
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3024              		.loc 2 3369 1 is_stmt 0 view .LVU935
+ 3025 0216 C6E7     		b	.L174
+ 3026              	.LVL238:
+ 3027              	.L175:
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3028              		.loc 2 3369 1 view .LVU936
+ 3029              	.LBE442:
+ 3030              	.LBE441:
+ 3031              	.LBB443:
+ 3032              	.LBI443:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3033              		.loc 3 1048 31 is_stmt 1 discriminator 2 view .LVU937
+ 3034              	.LBB444:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3035              		.loc 3 1050 3 discriminator 2 view .LVU938
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 3036              		.loc 3 1055 4 discriminator 2 view .LVU939
+ 3037              		.syntax unified
+ 3038              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3039 0218 93FAA3F3 		rbit r3, r3
+ 3040              	@ 0 "" 2
+ 3041              	.LVL239:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3042              		.loc 3 1068 3 discriminator 2 view .LVU940
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3043              		.loc 3 1068 3 is_stmt 0 discriminator 2 view .LVU941
+ 3044              		.thumb
+ 3045              		.syntax unified
+ARM GAS  /tmp/ccICigVb.s 			page 274
+
+
+ 3046              	.LBE444:
+ 3047              	.LBE443:
+ 3048              	.LBB445:
+ 3049              	.LBI445:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3050              		.loc 3 1078 30 is_stmt 1 discriminator 2 view .LVU942
+ 3051              	.LBB446:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3052              		.loc 3 1089 3 discriminator 2 view .LVU943
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3053              		.loc 3 1089 6 is_stmt 0 discriminator 2 view .LVU944
+ 3054 021c 13B1     		cbz	r3, .L213
+ 3055              		.loc 3 1093 3 is_stmt 1 view .LVU945
+ 3056              		.loc 3 1093 10 is_stmt 0 view .LVU946
+ 3057 021e B3FA83F3 		clz	r3, r3
+ 3058              	.LVL240:
+ 3059              		.loc 3 1093 10 view .LVU947
+ 3060 0222 CBE7     		b	.L176
+ 3061              	.LVL241:
+ 3062              	.L213:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3063              		.loc 3 1091 12 view .LVU948
+ 3064 0224 2023     		movs	r3, #32
+ 3065              	.LVL242:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3066              		.loc 3 1091 12 view .LVU949
+ 3067 0226 C9E7     		b	.L176
+ 3068              	.LVL243:
+ 3069              	.L230:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3070              		.loc 3 1091 12 view .LVU950
+ 3071              	.LBE446:
+ 3072              	.LBE445:
+ 3073              	.LBB447:
+ 3074              	.LBB402:
+5503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 3075              		.loc 2 5503 5 is_stmt 1 view .LVU951
+ 3076 0228 D3F8B010 		ldr	r1, [r3, #176]
+ 3077 022c C2F31202 		ubfx	r2, r2, #0, #19
+ 3078              	.LVL244:
+5503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 3079              		.loc 2 5503 5 is_stmt 0 view .LVU952
+ 3080 0230 0A43     		orrs	r2, r2, r1
+ 3081 0232 C3F8B020 		str	r2, [r3, #176]
+ 3082              	.LVL245:
+5503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 3083              		.loc 2 5503 5 view .LVU953
+ 3084 0236 63E7     		b	.L180
+ 3085              	.LVL246:
+ 3086              	.L231:
+5503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 3087              		.loc 2 5503 5 view .LVU954
+ 3088              	.LBE402:
+ 3089              	.LBE447:
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_T
+ 3090              		.loc 1 2888 9 is_stmt 1 view .LVU955
+ 3091 0238 2068     		ldr	r0, [r4]
+ARM GAS  /tmp/ccICigVb.s 			page 275
+
+
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3092              		.loc 1 2889 50 is_stmt 0 view .LVU956
+ 3093 023a 2B68     		ldr	r3, [r5]
+ 3094 023c C3F31206 		ubfx	r6, r3, #0, #19
+ 3095 0240 26BB     		cbnz	r6, .L181
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3096              		.loc 1 2889 50 discriminator 1 view .LVU957
+ 3097 0242 9A0E     		lsrs	r2, r3, #26
+ 3098 0244 0132     		adds	r2, r2, #1
+ 3099 0246 02F01F02 		and	r2, r2, #31
+ 3100 024a 092A     		cmp	r2, #9
+ 3101 024c 8CBF     		ite	hi
+ 3102 024e 0022     		movhi	r2, #0
+ 3103 0250 0122     		movls	r2, #1
+ 3104              	.L182:
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_T
+ 3105              		.loc 1 2888 9 view .LVU958
+ 3106 0252 002A     		cmp	r2, #0
+ 3107 0254 52D0     		beq	.L184
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3108              		.loc 1 2889 50 view .LVU959
+ 3109 0256 46BB     		cbnz	r6, .L185
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3110              		.loc 1 2889 50 discriminator 3 view .LVU960
+ 3111 0258 990E     		lsrs	r1, r3, #26
+ 3112 025a 0131     		adds	r1, r1, #1
+ 3113 025c 8906     		lsls	r1, r1, #26
+ 3114 025e 01F0F841 		and	r1, r1, #2080374784
+ 3115              	.L186:
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3116              		.loc 1 2889 50 discriminator 6 view .LVU961
+ 3117 0262 76BB     		cbnz	r6, .L188
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3118              		.loc 1 2889 50 discriminator 7 view .LVU962
+ 3119 0264 9F0E     		lsrs	r7, r3, #26
+ 3120 0266 0137     		adds	r7, r7, #1
+ 3121 0268 07F01F07 		and	r7, r7, #31
+ 3122 026c 0122     		movs	r2, #1
+ 3123 026e BA40     		lsls	r2, r2, r7
+ 3124              	.L189:
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3125              		.loc 1 2889 50 discriminator 10 view .LVU963
+ 3126 0270 1143     		orrs	r1, r1, r2
+ 3127 0272 AEBB     		cbnz	r6, .L191
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3128              		.loc 1 2889 50 discriminator 11 view .LVU964
+ 3129 0274 9B0E     		lsrs	r3, r3, #26
+ 3130 0276 0133     		adds	r3, r3, #1
+ 3131 0278 03F01F03 		and	r3, r3, #31
+ 3132 027c 03EB4303 		add	r3, r3, r3, lsl #1
+ 3133 0280 1B05     		lsls	r3, r3, #20
+ 3134              	.L192:
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_T
+ 3135              		.loc 1 2888 9 view .LVU965
+ 3136 0282 1943     		orrs	r1, r1, r3
+ 3137              	.L194:
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_T
+ARM GAS  /tmp/ccICigVb.s 			page 276
+
+
+ 3138              		.loc 1 2888 9 discriminator 1 view .LVU966
+ 3139 0284 AA68     		ldr	r2, [r5, #8]
+ 3140 0286 FFF7FEFF 		bl	LL_ADC_SetChannelSamplingTime
+ 3141              	.LVL247:
+ 3142 028a 3EE7     		b	.L178
+ 3143              	.L181:
+ 3144              	.LVL248:
+ 3145              	.LBB448:
+ 3146              	.LBI448:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3147              		.loc 3 1048 31 is_stmt 1 discriminator 2 view .LVU967
+ 3148              	.LBB449:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3149              		.loc 3 1050 3 discriminator 2 view .LVU968
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 3150              		.loc 3 1055 4 discriminator 2 view .LVU969
+ 3151              		.syntax unified
+ 3152              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3153 028c 93FAA3F2 		rbit r2, r3
+ 3154              	@ 0 "" 2
+ 3155              	.LVL249:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3156              		.loc 3 1068 3 discriminator 2 view .LVU970
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3157              		.loc 3 1068 3 is_stmt 0 discriminator 2 view .LVU971
+ 3158              		.thumb
+ 3159              		.syntax unified
+ 3160              	.LBE449:
+ 3161              	.LBE448:
+ 3162              	.LBB450:
+ 3163              	.LBI450:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3164              		.loc 3 1078 30 is_stmt 1 discriminator 2 view .LVU972
+ 3165              	.LBB451:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3166              		.loc 3 1089 3 discriminator 2 view .LVU973
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3167              		.loc 3 1089 6 is_stmt 0 discriminator 2 view .LVU974
+ 3168 0290 4AB1     		cbz	r2, .L214
+ 3169              		.loc 3 1093 3 is_stmt 1 view .LVU975
+ 3170              		.loc 3 1093 10 is_stmt 0 view .LVU976
+ 3171 0292 B2FA82F2 		clz	r2, r2
+ 3172              	.LVL250:
+ 3173              	.L183:
+ 3174              		.loc 3 1093 10 view .LVU977
+ 3175              	.LBE451:
+ 3176              	.LBE450:
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3177              		.loc 1 2889 50 view .LVU978
+ 3178 0296 0132     		adds	r2, r2, #1
+ 3179 0298 02F01F02 		and	r2, r2, #31
+ 3180 029c 092A     		cmp	r2, #9
+ 3181 029e 8CBF     		ite	hi
+ 3182 02a0 0022     		movhi	r2, #0
+ 3183 02a2 0122     		movls	r2, #1
+ 3184 02a4 D5E7     		b	.L182
+ 3185              	.LVL251:
+ARM GAS  /tmp/ccICigVb.s 			page 277
+
+
+ 3186              	.L214:
+ 3187              	.LBB453:
+ 3188              	.LBB452:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3189              		.loc 3 1091 12 view .LVU979
+ 3190 02a6 2022     		movs	r2, #32
+ 3191              	.LVL252:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3192              		.loc 3 1091 12 view .LVU980
+ 3193 02a8 F5E7     		b	.L183
+ 3194              	.LVL253:
+ 3195              	.L185:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3196              		.loc 3 1091 12 view .LVU981
+ 3197              	.LBE452:
+ 3198              	.LBE453:
+ 3199              	.LBB454:
+ 3200              	.LBI454:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3201              		.loc 3 1048 31 is_stmt 1 discriminator 4 view .LVU982
+ 3202              	.LBB455:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3203              		.loc 3 1050 3 discriminator 4 view .LVU983
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 3204              		.loc 3 1055 4 discriminator 4 view .LVU984
+ 3205              		.syntax unified
+ 3206              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3207 02aa 93FAA3F1 		rbit r1, r3
+ 3208              	@ 0 "" 2
+ 3209              	.LVL254:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3210              		.loc 3 1068 3 discriminator 4 view .LVU985
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3211              		.loc 3 1068 3 is_stmt 0 discriminator 4 view .LVU986
+ 3212              		.thumb
+ 3213              		.syntax unified
+ 3214              	.LBE455:
+ 3215              	.LBE454:
+ 3216              	.LBB456:
+ 3217              	.LBI456:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3218              		.loc 3 1078 30 is_stmt 1 discriminator 4 view .LVU987
+ 3219              	.LBB457:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3220              		.loc 3 1089 3 discriminator 4 view .LVU988
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3221              		.loc 3 1089 6 is_stmt 0 discriminator 4 view .LVU989
+ 3222 02ae 31B1     		cbz	r1, .L215
+ 3223              		.loc 3 1093 3 is_stmt 1 view .LVU990
+ 3224              		.loc 3 1093 10 is_stmt 0 view .LVU991
+ 3225 02b0 B1FA81F1 		clz	r1, r1
+ 3226              	.LVL255:
+ 3227              	.L187:
+ 3228              		.loc 3 1093 10 view .LVU992
+ 3229              	.LBE457:
+ 3230              	.LBE456:
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ARM GAS  /tmp/ccICigVb.s 			page 278
+
+
+ 3231              		.loc 1 2889 50 view .LVU993
+ 3232 02b4 0131     		adds	r1, r1, #1
+ 3233 02b6 8906     		lsls	r1, r1, #26
+ 3234 02b8 01F0F841 		and	r1, r1, #2080374784
+ 3235 02bc D1E7     		b	.L186
+ 3236              	.LVL256:
+ 3237              	.L215:
+ 3238              	.LBB459:
+ 3239              	.LBB458:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3240              		.loc 3 1091 12 view .LVU994
+ 3241 02be 2021     		movs	r1, #32
+ 3242              	.LVL257:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3243              		.loc 3 1091 12 view .LVU995
+ 3244 02c0 F8E7     		b	.L187
+ 3245              	.LVL258:
+ 3246              	.L188:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3247              		.loc 3 1091 12 view .LVU996
+ 3248              	.LBE458:
+ 3249              	.LBE459:
+ 3250              	.LBB460:
+ 3251              	.LBI460:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3252              		.loc 3 1048 31 is_stmt 1 discriminator 8 view .LVU997
+ 3253              	.LBB461:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3254              		.loc 3 1050 3 discriminator 8 view .LVU998
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 3255              		.loc 3 1055 4 discriminator 8 view .LVU999
+ 3256              		.syntax unified
+ 3257              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3258 02c2 93FAA3F2 		rbit r2, r3
+ 3259              	@ 0 "" 2
+ 3260              	.LVL259:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3261              		.loc 3 1068 3 discriminator 8 view .LVU1000
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3262              		.loc 3 1068 3 is_stmt 0 discriminator 8 view .LVU1001
+ 3263              		.thumb
+ 3264              		.syntax unified
+ 3265              	.LBE461:
+ 3266              	.LBE460:
+ 3267              	.LBB462:
+ 3268              	.LBI462:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3269              		.loc 3 1078 30 is_stmt 1 discriminator 8 view .LVU1002
+ 3270              	.LBB463:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3271              		.loc 3 1089 3 discriminator 8 view .LVU1003
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3272              		.loc 3 1089 6 is_stmt 0 discriminator 8 view .LVU1004
+ 3273 02c6 4AB1     		cbz	r2, .L216
+ 3274              		.loc 3 1093 3 is_stmt 1 view .LVU1005
+ 3275              		.loc 3 1093 10 is_stmt 0 view .LVU1006
+ 3276 02c8 B2FA82F2 		clz	r2, r2
+ARM GAS  /tmp/ccICigVb.s 			page 279
+
+
+ 3277              	.LVL260:
+ 3278              	.L190:
+ 3279              		.loc 3 1093 10 view .LVU1007
+ 3280              	.LBE463:
+ 3281              	.LBE462:
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3282              		.loc 1 2889 50 view .LVU1008
+ 3283 02cc 0132     		adds	r2, r2, #1
+ 3284 02ce 02F01F02 		and	r2, r2, #31
+ 3285 02d2 4FF0010C 		mov	ip, #1
+ 3286 02d6 0CFA02F2 		lsl	r2, ip, r2
+ 3287 02da C9E7     		b	.L189
+ 3288              	.LVL261:
+ 3289              	.L216:
+ 3290              	.LBB465:
+ 3291              	.LBB464:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3292              		.loc 3 1091 12 view .LVU1009
+ 3293 02dc 2022     		movs	r2, #32
+ 3294              	.LVL262:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3295              		.loc 3 1091 12 view .LVU1010
+ 3296 02de F5E7     		b	.L190
+ 3297              	.LVL263:
+ 3298              	.L191:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3299              		.loc 3 1091 12 view .LVU1011
+ 3300              	.LBE464:
+ 3301              	.LBE465:
+ 3302              	.LBB466:
+ 3303              	.LBI466:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3304              		.loc 3 1048 31 is_stmt 1 discriminator 12 view .LVU1012
+ 3305              	.LBB467:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3306              		.loc 3 1050 3 discriminator 12 view .LVU1013
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 3307              		.loc 3 1055 4 discriminator 12 view .LVU1014
+ 3308              		.syntax unified
+ 3309              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3310 02e0 93FAA3F3 		rbit r3, r3
+ 3311              	@ 0 "" 2
+ 3312              	.LVL264:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3313              		.loc 3 1068 3 discriminator 12 view .LVU1015
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3314              		.loc 3 1068 3 is_stmt 0 discriminator 12 view .LVU1016
+ 3315              		.thumb
+ 3316              		.syntax unified
+ 3317              	.LBE467:
+ 3318              	.LBE466:
+ 3319              	.LBB468:
+ 3320              	.LBI468:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3321              		.loc 3 1078 30 is_stmt 1 discriminator 12 view .LVU1017
+ 3322              	.LBB469:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ARM GAS  /tmp/ccICigVb.s 			page 280
+
+
+ 3323              		.loc 3 1089 3 discriminator 12 view .LVU1018
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3324              		.loc 3 1089 6 is_stmt 0 discriminator 12 view .LVU1019
+ 3325 02e4 43B1     		cbz	r3, .L217
+ 3326              		.loc 3 1093 3 is_stmt 1 view .LVU1020
+ 3327              		.loc 3 1093 10 is_stmt 0 view .LVU1021
+ 3328 02e6 B3FA83F3 		clz	r3, r3
+ 3329              	.LVL265:
+ 3330              	.L193:
+ 3331              		.loc 3 1093 10 view .LVU1022
+ 3332              	.LBE469:
+ 3333              	.LBE468:
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3334              		.loc 1 2889 50 view .LVU1023
+ 3335 02ea 0133     		adds	r3, r3, #1
+ 3336 02ec 03F01F03 		and	r3, r3, #31
+ 3337 02f0 03EB4303 		add	r3, r3, r3, lsl #1
+ 3338 02f4 1B05     		lsls	r3, r3, #20
+ 3339 02f6 C4E7     		b	.L192
+ 3340              	.LVL266:
+ 3341              	.L217:
+ 3342              	.LBB471:
+ 3343              	.LBB470:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3344              		.loc 3 1091 12 view .LVU1024
+ 3345 02f8 2023     		movs	r3, #32
+ 3346              	.LVL267:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3347              		.loc 3 1091 12 view .LVU1025
+ 3348 02fa F6E7     		b	.L193
+ 3349              	.LVL268:
+ 3350              	.L184:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3351              		.loc 3 1091 12 view .LVU1026
+ 3352              	.LBE470:
+ 3353              	.LBE471:
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3354              		.loc 1 2889 50 view .LVU1027
+ 3355 02fc 56BB     		cbnz	r6, .L195
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3356              		.loc 1 2889 50 discriminator 13 view .LVU1028
+ 3357 02fe 990E     		lsrs	r1, r3, #26
+ 3358 0300 0131     		adds	r1, r1, #1
+ 3359 0302 8906     		lsls	r1, r1, #26
+ 3360 0304 01F0F841 		and	r1, r1, #2080374784
+ 3361              	.L196:
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3362              		.loc 1 2889 50 discriminator 16 view .LVU1029
+ 3363 0308 86BB     		cbnz	r6, .L198
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3364              		.loc 1 2889 50 discriminator 17 view .LVU1030
+ 3365 030a 9F0E     		lsrs	r7, r3, #26
+ 3366 030c 0137     		adds	r7, r7, #1
+ 3367 030e 07F01F07 		and	r7, r7, #31
+ 3368 0312 0122     		movs	r2, #1
+ 3369 0314 BA40     		lsls	r2, r2, r7
+ 3370              	.L199:
+ARM GAS  /tmp/ccICigVb.s 			page 281
+
+
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3371              		.loc 1 2889 50 discriminator 20 view .LVU1031
+ 3372 0316 1143     		orrs	r1, r1, r2
+ 3373 0318 BEBB     		cbnz	r6, .L201
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3374              		.loc 1 2889 50 discriminator 21 view .LVU1032
+ 3375 031a 9B0E     		lsrs	r3, r3, #26
+ 3376 031c 0133     		adds	r3, r3, #1
+ 3377 031e 03F01F03 		and	r3, r3, #31
+ 3378 0322 03EB4303 		add	r3, r3, r3, lsl #1
+ 3379 0326 1E3B     		subs	r3, r3, #30
+ 3380 0328 1B05     		lsls	r3, r3, #20
+ 3381 032a 43F00073 		orr	r3, r3, #33554432
+ 3382              	.L202:
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_T
+ 3383              		.loc 1 2888 9 discriminator 2 view .LVU1033
+ 3384 032e 1943     		orrs	r1, r1, r3
+ 3385 0330 A8E7     		b	.L194
+ 3386              	.L240:
+ 3387 0332 00BF     		.align	2
+ 3388              	.L239:
+ 3389 0334 00F0FF03 		.word	67104768
+ 3390 0338 00007F40 		.word	1082064896
+ 3391 033c 00000880 		.word	-2146959360
+ 3392 0340 00030050 		.word	1342178048
+ 3393 0344 000021C3 		.word	-1021247488
+ 3394 0348 1000C090 		.word	-1866465264
+ 3395 034c 000052C7 		.word	-950927360
+ 3396 0350 000084CB 		.word	-880541696
+ 3397              	.L195:
+ 3398              	.LVL269:
+ 3399              	.LBB472:
+ 3400              	.LBI472:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3401              		.loc 3 1048 31 is_stmt 1 discriminator 14 view .LVU1034
+ 3402              	.LBB473:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3403              		.loc 3 1050 3 discriminator 14 view .LVU1035
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 3404              		.loc 3 1055 4 discriminator 14 view .LVU1036
+ 3405              		.syntax unified
+ 3406              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3407 0354 93FAA3F1 		rbit r1, r3
+ 3408              	@ 0 "" 2
+ 3409              	.LVL270:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3410              		.loc 3 1068 3 discriminator 14 view .LVU1037
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3411              		.loc 3 1068 3 is_stmt 0 discriminator 14 view .LVU1038
+ 3412              		.thumb
+ 3413              		.syntax unified
+ 3414              	.LBE473:
+ 3415              	.LBE472:
+ 3416              	.LBB474:
+ 3417              	.LBI474:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3418              		.loc 3 1078 30 is_stmt 1 discriminator 14 view .LVU1039
+ARM GAS  /tmp/ccICigVb.s 			page 282
+
+
+ 3419              	.LBB475:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3420              		.loc 3 1089 3 discriminator 14 view .LVU1040
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3421              		.loc 3 1089 6 is_stmt 0 discriminator 14 view .LVU1041
+ 3422 0358 31B1     		cbz	r1, .L218
+ 3423              		.loc 3 1093 3 is_stmt 1 view .LVU1042
+ 3424              		.loc 3 1093 10 is_stmt 0 view .LVU1043
+ 3425 035a B1FA81F1 		clz	r1, r1
+ 3426              	.LVL271:
+ 3427              	.L197:
+ 3428              		.loc 3 1093 10 view .LVU1044
+ 3429              	.LBE475:
+ 3430              	.LBE474:
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3431              		.loc 1 2889 50 view .LVU1045
+ 3432 035e 0131     		adds	r1, r1, #1
+ 3433 0360 8906     		lsls	r1, r1, #26
+ 3434 0362 01F0F841 		and	r1, r1, #2080374784
+ 3435 0366 CFE7     		b	.L196
+ 3436              	.LVL272:
+ 3437              	.L218:
+ 3438              	.LBB477:
+ 3439              	.LBB476:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3440              		.loc 3 1091 12 view .LVU1046
+ 3441 0368 2021     		movs	r1, #32
+ 3442              	.LVL273:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3443              		.loc 3 1091 12 view .LVU1047
+ 3444 036a F8E7     		b	.L197
+ 3445              	.LVL274:
+ 3446              	.L198:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3447              		.loc 3 1091 12 view .LVU1048
+ 3448              	.LBE476:
+ 3449              	.LBE477:
+ 3450              	.LBB478:
+ 3451              	.LBI478:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3452              		.loc 3 1048 31 is_stmt 1 discriminator 18 view .LVU1049
+ 3453              	.LBB479:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3454              		.loc 3 1050 3 discriminator 18 view .LVU1050
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 3455              		.loc 3 1055 4 discriminator 18 view .LVU1051
+ 3456              		.syntax unified
+ 3457              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3458 036c 93FAA3F2 		rbit r2, r3
+ 3459              	@ 0 "" 2
+ 3460              	.LVL275:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3461              		.loc 3 1068 3 discriminator 18 view .LVU1052
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3462              		.loc 3 1068 3 is_stmt 0 discriminator 18 view .LVU1053
+ 3463              		.thumb
+ 3464              		.syntax unified
+ARM GAS  /tmp/ccICigVb.s 			page 283
+
+
+ 3465              	.LBE479:
+ 3466              	.LBE478:
+ 3467              	.LBB480:
+ 3468              	.LBI480:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3469              		.loc 3 1078 30 is_stmt 1 discriminator 18 view .LVU1054
+ 3470              	.LBB481:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3471              		.loc 3 1089 3 discriminator 18 view .LVU1055
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3472              		.loc 3 1089 6 is_stmt 0 discriminator 18 view .LVU1056
+ 3473 0370 4AB1     		cbz	r2, .L219
+ 3474              		.loc 3 1093 3 is_stmt 1 view .LVU1057
+ 3475              		.loc 3 1093 10 is_stmt 0 view .LVU1058
+ 3476 0372 B2FA82F2 		clz	r2, r2
+ 3477              	.LVL276:
+ 3478              	.L200:
+ 3479              		.loc 3 1093 10 view .LVU1059
+ 3480              	.LBE481:
+ 3481              	.LBE480:
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3482              		.loc 1 2889 50 view .LVU1060
+ 3483 0376 0132     		adds	r2, r2, #1
+ 3484 0378 02F01F02 		and	r2, r2, #31
+ 3485 037c 4FF0010C 		mov	ip, #1
+ 3486 0380 0CFA02F2 		lsl	r2, ip, r2
+ 3487 0384 C7E7     		b	.L199
+ 3488              	.LVL277:
+ 3489              	.L219:
+ 3490              	.LBB483:
+ 3491              	.LBB482:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3492              		.loc 3 1091 12 view .LVU1061
+ 3493 0386 2022     		movs	r2, #32
+ 3494              	.LVL278:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3495              		.loc 3 1091 12 view .LVU1062
+ 3496 0388 F5E7     		b	.L200
+ 3497              	.LVL279:
+ 3498              	.L201:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3499              		.loc 3 1091 12 view .LVU1063
+ 3500              	.LBE482:
+ 3501              	.LBE483:
+ 3502              	.LBB484:
+ 3503              	.LBI484:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3504              		.loc 3 1048 31 is_stmt 1 discriminator 22 view .LVU1064
+ 3505              	.LBB485:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3506              		.loc 3 1050 3 discriminator 22 view .LVU1065
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 3507              		.loc 3 1055 4 discriminator 22 view .LVU1066
+ 3508              		.syntax unified
+ 3509              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3510 038a 93FAA3F3 		rbit r3, r3
+ 3511              	@ 0 "" 2
+ARM GAS  /tmp/ccICigVb.s 			page 284
+
+
+ 3512              	.LVL280:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3513              		.loc 3 1068 3 discriminator 22 view .LVU1067
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3514              		.loc 3 1068 3 is_stmt 0 discriminator 22 view .LVU1068
+ 3515              		.thumb
+ 3516              		.syntax unified
+ 3517              	.LBE485:
+ 3518              	.LBE484:
+ 3519              	.LBB486:
+ 3520              	.LBI486:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3521              		.loc 3 1078 30 is_stmt 1 discriminator 22 view .LVU1069
+ 3522              	.LBB487:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3523              		.loc 3 1089 3 discriminator 22 view .LVU1070
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3524              		.loc 3 1089 6 is_stmt 0 discriminator 22 view .LVU1071
+ 3525 038e 5BB1     		cbz	r3, .L220
+ 3526              		.loc 3 1093 3 is_stmt 1 view .LVU1072
+ 3527              		.loc 3 1093 10 is_stmt 0 view .LVU1073
+ 3528 0390 B3FA83F3 		clz	r3, r3
+ 3529              	.LVL281:
+ 3530              	.L203:
+ 3531              		.loc 3 1093 10 view .LVU1074
+ 3532              	.LBE487:
+ 3533              	.LBE486:
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                       sConfig->SamplingTime);
+ 3534              		.loc 1 2889 50 view .LVU1075
+ 3535 0394 0133     		adds	r3, r3, #1
+ 3536 0396 03F01F03 		and	r3, r3, #31
+ 3537 039a 03EB4303 		add	r3, r3, r3, lsl #1
+ 3538 039e 1E3B     		subs	r3, r3, #30
+ 3539 03a0 1B05     		lsls	r3, r3, #20
+ 3540 03a2 43F00073 		orr	r3, r3, #33554432
+ 3541 03a6 C2E7     		b	.L202
+ 3542              	.LVL282:
+ 3543              	.L220:
+ 3544              	.LBB489:
+ 3545              	.LBB488:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3546              		.loc 3 1091 12 view .LVU1076
+ 3547 03a8 2023     		movs	r3, #32
+ 3548              	.LVL283:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3549              		.loc 3 1091 12 view .LVU1077
+ 3550 03aa F3E7     		b	.L203
+ 3551              	.LVL284:
+ 3552              	.L204:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3553              		.loc 3 1091 12 view .LVU1078
+ 3554              	.LBE488:
+ 3555              	.LBE489:
+2908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3556              		.loc 1 2908 11 view .LVU1079
+ 3557 03ac 12F4000F 		tst	r2, #8388608
+ 3558 03b0 7FF4BCAE 		bne	.L205
+ARM GAS  /tmp/ccICigVb.s 			page 285
+
+
+2910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 3559              		.loc 1 2910 9 is_stmt 1 view .LVU1080
+2910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 3560              		.loc 1 2910 13 is_stmt 0 view .LVU1081
+ 3561 03b4 2368     		ldr	r3, [r4]
+2910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 3562              		.loc 1 2910 12 view .LVU1082
+ 3563 03b6 B3F1A04F 		cmp	r3, #1342177280
+ 3564 03ba 01D0     		beq	.L237
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpOffsetShifted;
+ 3565              		.loc 1 2760 21 view .LVU1083
+ 3566 03bc 0020     		movs	r0, #0
+ 3567 03be 37E6     		b	.L155
+ 3568              	.L237:
+2912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                          LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_chan
+ 3569              		.loc 1 2912 11 is_stmt 1 view .LVU1084
+ 3570 03c0 41F40001 		orr	r1, r1, #8388608
+ 3571              	.LVL285:
+ 3572              	.LBB490:
+ 3573              	.LBI490:
+2796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3574              		.loc 2 2796 22 view .LVU1085
+ 3575              	.LBB491:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3576              		.loc 2 2798 3 view .LVU1086
+ 3577 03c4 234A     		ldr	r2, .L241
+ 3578              	.LVL286:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3579              		.loc 2 2798 3 is_stmt 0 view .LVU1087
+ 3580 03c6 9368     		ldr	r3, [r2, #8]
+ 3581 03c8 23F0E073 		bic	r3, r3, #29360128
+ 3582 03cc 1943     		orrs	r1, r1, r3
+ 3583              	.LVL287:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3584              		.loc 2 2798 3 view .LVU1088
+ 3585 03ce 9160     		str	r1, [r2, #8]
+ 3586              	.LVL288:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3587              		.loc 2 2798 3 view .LVU1089
+ 3588              	.LBE491:
+ 3589              	.LBE490:
+2920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           while (wait_loop_index != 0UL)
+ 3590              		.loc 1 2920 11 is_stmt 1 view .LVU1090
+2920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           while (wait_loop_index != 0UL)
+ 3591              		.loc 1 2920 91 is_stmt 0 view .LVU1091
+ 3592 03d0 214B     		ldr	r3, .L241+4
+ 3593 03d2 1B68     		ldr	r3, [r3]
+ 3594 03d4 9B09     		lsrs	r3, r3, #6
+ 3595 03d6 214A     		ldr	r2, .L241+8
+ 3596 03d8 A2FB0323 		umull	r2, r3, r2, r3
+ 3597 03dc 9B09     		lsrs	r3, r3, #6
+2920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           while (wait_loop_index != 0UL)
+ 3598              		.loc 1 2920 71 view .LVU1092
+ 3599 03de 0133     		adds	r3, r3, #1
+ 3600 03e0 03EB4303 		add	r3, r3, r3, lsl #1
+ 3601 03e4 9B00     		lsls	r3, r3, #2
+2920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           while (wait_loop_index != 0UL)
+ARM GAS  /tmp/ccICigVb.s 			page 286
+
+
+ 3602              		.loc 1 2920 27 view .LVU1093
+ 3603 03e6 0193     		str	r3, [sp, #4]
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 3604              		.loc 1 2921 11 is_stmt 1 view .LVU1094
+ 3605              	.L206:
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 3606              		.loc 1 2921 34 view .LVU1095
+ 3607 03e8 019B     		ldr	r3, [sp, #4]
+ 3608 03ea 1BB1     		cbz	r3, .L238
+2923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 3609              		.loc 1 2923 13 view .LVU1096
+2923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 3610              		.loc 1 2923 28 is_stmt 0 view .LVU1097
+ 3611 03ec 019B     		ldr	r3, [sp, #4]
+ 3612 03ee 013B     		subs	r3, r3, #1
+ 3613 03f0 0193     		str	r3, [sp, #4]
+ 3614 03f2 F9E7     		b	.L206
+ 3615              	.L238:
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpOffsetShifted;
+ 3616              		.loc 1 2760 21 view .LVU1098
+ 3617 03f4 0020     		movs	r0, #0
+ 3618 03f6 1BE6     		b	.L155
+ 3619              	.LVL289:
+ 3620              	.L232:
+2927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3621              		.loc 1 2927 55 discriminator 1 view .LVU1099
+ 3622 03f8 12F0807F 		tst	r2, #16777216
+ 3623 03fc 7FF49AAE 		bne	.L208
+2929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 3624              		.loc 1 2929 9 is_stmt 1 view .LVU1100
+2929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 3625              		.loc 1 2929 13 is_stmt 0 view .LVU1101
+ 3626 0400 2268     		ldr	r2, [r4]
+2929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 3627              		.loc 1 2929 12 view .LVU1102
+ 3628 0402 174B     		ldr	r3, .L241+12
+ 3629 0404 9A42     		cmp	r2, r3
+ 3630 0406 1CD0     		beq	.L223
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                          LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+ 3631              		.loc 1 2931 11 is_stmt 1 view .LVU1103
+ 3632 0408 41F08071 		orr	r1, r1, #16777216
+ 3633              	.LVL290:
+ 3634              	.LBB492:
+ 3635              	.LBI492:
+2796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3636              		.loc 2 2796 22 view .LVU1104
+ 3637              	.LBB493:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3638              		.loc 2 2798 3 view .LVU1105
+ 3639 040c 114A     		ldr	r2, .L241
+ 3640 040e 9368     		ldr	r3, [r2, #8]
+ 3641 0410 23F0E073 		bic	r3, r3, #29360128
+ 3642 0414 1943     		orrs	r1, r1, r3
+ 3643              	.LVL291:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3644              		.loc 2 2798 3 is_stmt 0 view .LVU1106
+ 3645 0416 9160     		str	r1, [r2, #8]
+ARM GAS  /tmp/ccICigVb.s 			page 287
+
+
+ 3646              	.LBE493:
+ 3647              	.LBE492:
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpOffsetShifted;
+ 3648              		.loc 1 2760 21 view .LVU1107
+ 3649 0418 0020     		movs	r0, #0
+ 3650              	.LBB495:
+ 3651              	.LBB494:
+2799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3652              		.loc 2 2799 1 view .LVU1108
+ 3653 041a 09E6     		b	.L155
+ 3654              	.LVL292:
+ 3655              	.L233:
+2799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3656              		.loc 2 2799 1 view .LVU1109
+ 3657              	.LBE494:
+ 3658              	.LBE495:
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3659              		.loc 1 2936 16 view .LVU1110
+ 3660 041c 12F4800F 		tst	r2, #4194304
+ 3661 0420 11D1     		bne	.L225
+2938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 3662              		.loc 1 2938 9 is_stmt 1 view .LVU1111
+2938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 3663              		.loc 1 2938 13 is_stmt 0 view .LVU1112
+ 3664 0422 2268     		ldr	r2, [r4]
+2938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 3665              		.loc 1 2938 12 view .LVU1113
+ 3666 0424 0E4B     		ldr	r3, .L241+12
+ 3667 0426 9A42     		cmp	r2, r3
+ 3668 0428 0FD0     		beq	.L226
+2940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                          LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel
+ 3669              		.loc 1 2940 11 is_stmt 1 view .LVU1114
+ 3670 042a 41F48003 		orr	r3, r1, #4194304
+ 3671              	.LVL293:
+ 3672              	.LBB496:
+ 3673              	.LBI496:
+2796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3674              		.loc 2 2796 22 view .LVU1115
+ 3675              	.LBB497:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3676              		.loc 2 2798 3 view .LVU1116
+ 3677 042e 0949     		ldr	r1, .L241
+ 3678              	.LVL294:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3679              		.loc 2 2798 3 is_stmt 0 view .LVU1117
+ 3680 0430 8A68     		ldr	r2, [r1, #8]
+ 3681 0432 22F0E072 		bic	r2, r2, #29360128
+ 3682 0436 1343     		orrs	r3, r3, r2
+ 3683              	.LVL295:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3684              		.loc 2 2798 3 view .LVU1118
+ 3685 0438 8B60     		str	r3, [r1, #8]
+ 3686              	.LBE497:
+ 3687              	.LBE496:
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpOffsetShifted;
+ 3688              		.loc 1 2760 21 view .LVU1119
+ 3689 043a 0020     		movs	r0, #0
+ARM GAS  /tmp/ccICigVb.s 			page 288
+
+
+ 3690              	.LBB499:
+ 3691              	.LBB498:
+2799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3692              		.loc 2 2799 1 view .LVU1120
+ 3693 043c F8E5     		b	.L155
+ 3694              	.LVL296:
+ 3695              	.L221:
+2799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3696              		.loc 2 2799 1 view .LVU1121
+ 3697              	.LBE498:
+ 3698              	.LBE499:
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpOffsetShifted;
+ 3699              		.loc 1 2760 21 view .LVU1122
+ 3700 043e 0020     		movs	r0, #0
+ 3701 0440 F6E5     		b	.L155
+ 3702              	.LVL297:
+ 3703              	.L223:
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpOffsetShifted;
+ 3704              		.loc 1 2760 21 view .LVU1123
+ 3705 0442 0020     		movs	r0, #0
+ 3706 0444 F4E5     		b	.L155
+ 3707              	.L225:
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpOffsetShifted;
+ 3708              		.loc 1 2760 21 view .LVU1124
+ 3709 0446 0020     		movs	r0, #0
+ 3710 0448 F2E5     		b	.L155
+ 3711              	.L226:
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpOffsetShifted;
+ 3712              		.loc 1 2760 21 view .LVU1125
+ 3713 044a 0020     		movs	r0, #0
+ 3714 044c F0E5     		b	.L155
+ 3715              	.LVL298:
+ 3716              	.L209:
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 3717              		.loc 1 2790 3 view .LVU1126
+ 3718 044e 0220     		movs	r0, #2
+ 3719              	.LVL299:
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 3720              		.loc 1 2790 3 view .LVU1127
+ 3721 0450 F1E5     		b	.L153
+ 3722              	.L242:
+ 3723 0452 00BF     		.align	2
+ 3724              	.L241:
+ 3725 0454 00030050 		.word	1342178048
+ 3726 0458 00000000 		.word	SystemCoreClock
+ 3727 045c 632D3E05 		.word	87960931
+ 3728 0460 00010050 		.word	1342177536
+ 3729              		.cfi_endproc
+ 3730              	.LFE349:
+ 3732              		.section	.text.HAL_ADC_AnalogWDGConfig,"ax",%progbits
+ 3733              		.align	1
+ 3734              		.global	HAL_ADC_AnalogWDGConfig
+ 3735              		.syntax unified
+ 3736              		.thumb
+ 3737              		.thumb_func
+ 3739              	HAL_ADC_AnalogWDGConfig:
+ 3740              	.LVL300:
+ARM GAS  /tmp/ccICigVb.s 			page 289
+
+
+ 3741              	.LFB350:
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 3742              		.loc 1 2992 1 is_stmt 1 view -0
+ 3743              		.cfi_startproc
+ 3744              		@ args = 0, pretend = 0, frame = 0
+ 3745              		@ frame_needed = 0, uses_anonymous_args = 0
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 3746              		.loc 1 2992 1 is_stmt 0 view .LVU1129
+ 3747 0000 38B5     		push	{r3, r4, r5, lr}
+ 3748              	.LCFI19:
+ 3749              		.cfi_def_cfa_offset 16
+ 3750              		.cfi_offset 3, -16
+ 3751              		.cfi_offset 4, -12
+ 3752              		.cfi_offset 5, -8
+ 3753              		.cfi_offset 14, -4
+2993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpAWDHighThresholdShifted;
+ 3754              		.loc 1 2993 3 is_stmt 1 view .LVU1130
+ 3755              	.LVL301:
+2994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmpAWDLowThresholdShifted;
+ 3756              		.loc 1 2994 3 view .LVU1131
+2995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+ 3757              		.loc 1 2995 3 view .LVU1132
+2996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_injected;
+ 3758              		.loc 1 2996 3 view .LVU1133
+2997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 3759              		.loc 1 2997 3 view .LVU1134
+3000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
+ 3760              		.loc 1 3000 3 view .LVU1135
+3001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+ 3761              		.loc 1 3001 3 view .LVU1136
+3002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(AnalogWDGConfig->FilteringConfig));
+ 3762              		.loc 1 3002 3 view .LVU1137
+3003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+ 3763              		.loc 1 3003 3 view .LVU1138
+3004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 3764              		.loc 1 3004 3 view .LVU1139
+3006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
+ 3765              		.loc 1 3006 3 view .LVU1140
+3010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 3766              		.loc 1 3010 5 view .LVU1141
+3014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 3767              		.loc 1 3014 3 view .LVU1142
+3025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+ 3768              		.loc 1 3025 5 view .LVU1143
+3026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 3769              		.loc 1 3026 5 view .LVU1144
+3030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 3770              		.loc 1 3030 3 view .LVU1145
+3030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 3771              		.loc 1 3030 3 view .LVU1146
+ 3772 0002 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 3773 0006 012B     		cmp	r3, #1
+ 3774 0008 00F06781 		beq	.L279
+ 3775 000c 0446     		mov	r4, r0
+ 3776 000e 0D46     		mov	r5, r1
+3030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 3777              		.loc 1 3030 3 discriminator 2 view .LVU1147
+ARM GAS  /tmp/ccICigVb.s 			page 290
+
+
+ 3778 0010 0123     		movs	r3, #1
+ 3779 0012 80F85830 		strb	r3, [r0, #88]
+3030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 3780              		.loc 1 3030 3 discriminator 2 view .LVU1148
+3036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 3781              		.loc 1 3036 3 discriminator 2 view .LVU1149
+3036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 3782              		.loc 1 3036 44 is_stmt 0 discriminator 2 view .LVU1150
+ 3783 0016 0068     		ldr	r0, [r0]
+ 3784              	.LVL302:
+ 3785              	.LBB500:
+ 3786              	.LBI500:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3787              		.loc 2 6851 26 is_stmt 1 discriminator 2 view .LVU1151
+ 3788              	.LBB501:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3789              		.loc 2 6853 3 discriminator 2 view .LVU1152
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3790              		.loc 2 6853 12 is_stmt 0 discriminator 2 view .LVU1153
+ 3791 0018 8368     		ldr	r3, [r0, #8]
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3792              		.loc 2 6853 74 discriminator 2 view .LVU1154
+ 3793 001a 13F00403 		ands	r3, r3, #4
+ 3794 001e 00D0     		beq	.L245
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3795              		.loc 2 6853 74 view .LVU1155
+ 3796 0020 0123     		movs	r3, #1
+ 3797              	.L245:
+ 3798              	.LVL303:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3799              		.loc 2 6853 74 view .LVU1156
+ 3800              	.LBE501:
+ 3801              	.LBE500:
+3037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ 3802              		.loc 1 3037 3 is_stmt 1 view .LVU1157
+ 3803              	.LBB502:
+ 3804              	.LBI502:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3805              		.loc 2 7076 26 view .LVU1158
+ 3806              	.LBB503:
+ 3807              		.loc 2 7078 3 view .LVU1159
+ 3808              		.loc 2 7078 12 is_stmt 0 view .LVU1160
+ 3809 0022 8268     		ldr	r2, [r0, #8]
+ 3810              		.loc 2 7078 76 view .LVU1161
+ 3811 0024 12F00802 		ands	r2, r2, #8
+ 3812 0028 00D0     		beq	.L246
+ 3813 002a 0122     		movs	r2, #1
+ 3814              	.L246:
+ 3815              	.LVL304:
+ 3816              		.loc 2 7078 76 view .LVU1162
+ 3817              	.LBE503:
+ 3818              	.LBE502:
+3038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 3819              		.loc 1 3038 3 is_stmt 1 view .LVU1163
+3038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 3820              		.loc 1 3038 6 is_stmt 0 view .LVU1164
+ 3821 002c 002B     		cmp	r3, #0
+ARM GAS  /tmp/ccICigVb.s 			page 291
+
+
+ 3822 002e 40F0EC80 		bne	.L247
+3039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      )
+ 3823              		.loc 1 3039 7 view .LVU1165
+ 3824 0032 002A     		cmp	r2, #0
+ 3825 0034 40F0E980 		bne	.L247
+3043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 3826              		.loc 1 3043 5 is_stmt 1 view .LVU1166
+3043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 3827              		.loc 1 3043 24 is_stmt 0 view .LVU1167
+ 3828 0038 2968     		ldr	r1, [r5]
+ 3829              	.LVL305:
+3043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 3830              		.loc 1 3043 8 view .LVU1168
+ 3831 003a A94B     		ldr	r3, .L291
+ 3832              	.LVL306:
+3043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 3833              		.loc 1 3043 8 view .LVU1169
+ 3834 003c 9942     		cmp	r1, r3
+ 3835 003e 16D0     		beq	.L283
+3109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3836              		.loc 1 3109 7 is_stmt 1 view .LVU1170
+3109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3837              		.loc 1 3109 30 is_stmt 0 view .LVU1171
+ 3838 0040 6B68     		ldr	r3, [r5, #4]
+3109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3839              		.loc 1 3109 7 view .LVU1172
+ 3840 0042 B3F1A07F 		cmp	r3, #20971520
+ 3841 0046 00F09280 		beq	.L259
+ 3842 004a 00F28980 		bhi	.L260
+ 3843 004e B3F5400F 		cmp	r3, #12582912
+ 3844 0052 00F08C80 		beq	.L259
+ 3845 0056 B3F1807F 		cmp	r3, #16777216
+ 3846 005a 00F0BF80 		beq	.L261
+ 3847 005e B3F5000F 		cmp	r3, #8388608
+ 3848 0062 00F0BB80 		beq	.L261
+ 3849              	.L262:
+3133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+ 3850              		.loc 1 3133 11 is_stmt 1 view .LVU1173
+ 3851 0066 0022     		movs	r2, #0
+ 3852              	.LVL307:
+3133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+ 3853              		.loc 1 3133 11 is_stmt 0 view .LVU1174
+ 3854 0068 FFF7FEFF 		bl	LL_ADC_SetAnalogWDMonitChannels
+ 3855              	.LVL308:
+3134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 3856              		.loc 1 3134 11 is_stmt 1 view .LVU1175
+ 3857 006c B9E0     		b	.L267
+ 3858              	.LVL309:
+ 3859              	.L283:
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3860              		.loc 1 3048 7 view .LVU1176
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3861              		.loc 1 3048 30 is_stmt 0 view .LVU1177
+ 3862 006e 6B68     		ldr	r3, [r5, #4]
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3863              		.loc 1 3048 7 view .LVU1178
+ 3864 0070 B3F1A07F 		cmp	r3, #20971520
+ARM GAS  /tmp/ccICigVb.s 			page 292
+
+
+ 3865 0074 51D0     		beq	.L249
+ 3866 0076 1AD8     		bhi	.L250
+ 3867 0078 B3F5400F 		cmp	r3, #12582912
+ 3868 007c 2AD0     		beq	.L251
+ 3869 007e B3F1807F 		cmp	r3, #16777216
+ 3870 0082 08D1     		bne	.L284
+3070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+ 3871              		.loc 1 3070 11 is_stmt 1 view .LVU1179
+ 3872              	.LVL310:
+ 3873              	.LBB504:
+ 3874              	.LBI504:
+5725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3875              		.loc 2 5725 22 view .LVU1180
+ 3876              	.LBB505:
+5731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_C
+ 3877              		.loc 2 5731 3 view .LVU1181
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ 3878              		.loc 2 5734 3 view .LVU1182
+ 3879 0084 C368     		ldr	r3, [r0, #12]
+ 3880 0086 23F0FB43 		bic	r3, r3, #2105540608
+ 3881 008a 23F48003 		bic	r3, r3, #4194304
+ 3882 008e 43F08073 		orr	r3, r3, #16777216
+ 3883 0092 C360     		str	r3, [r0, #12]
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3884              		.loc 2 5737 1 is_stmt 0 view .LVU1183
+ 3885 0094 2AE0     		b	.L257
+ 3886              	.LVL311:
+ 3887              	.L284:
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3888              		.loc 2 5737 1 view .LVU1184
+ 3889              	.LBE505:
+ 3890              	.LBE504:
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3891              		.loc 1 3048 7 view .LVU1185
+ 3892 0096 B3F5000F 		cmp	r3, #8388608
+ 3893 009a 54D1     		bne	.L254
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+ 3894              		.loc 1 3066 11 is_stmt 1 view .LVU1186
+ 3895              	.LVL312:
+ 3896              	.LBB506:
+ 3897              	.LBI506:
+5725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3898              		.loc 2 5725 22 view .LVU1187
+ 3899              	.LBB507:
+5731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_C
+ 3900              		.loc 2 5731 3 view .LVU1188
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ 3901              		.loc 2 5734 3 view .LVU1189
+ 3902 009c C368     		ldr	r3, [r0, #12]
+ 3903 009e 23F0FB43 		bic	r3, r3, #2105540608
+ 3904 00a2 23F48003 		bic	r3, r3, #4194304
+ 3905 00a6 43F40003 		orr	r3, r3, #8388608
+ 3906 00aa C360     		str	r3, [r0, #12]
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3907              		.loc 2 5737 1 is_stmt 0 view .LVU1190
+ 3908 00ac 1EE0     		b	.L257
+ 3909              	.LVL313:
+ARM GAS  /tmp/ccICigVb.s 			page 293
+
+
+ 3910              	.L250:
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3911              		.loc 2 5737 1 view .LVU1191
+ 3912              	.LBE507:
+ 3913              	.LBE506:
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3914              		.loc 1 3048 7 view .LVU1192
+ 3915 00ae B3F1C07F 		cmp	r3, #25165824
+ 3916 00b2 3FD0     		beq	.L255
+ 3917 00b4 B3F1E07F 		cmp	r3, #29360128
+ 3918 00b8 45D1     		bne	.L254
+3061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                           LL_ADC_GROUP_REGULAR_INJECTED));
+ 3919              		.loc 1 3061 11 is_stmt 1 view .LVU1193
+3061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                           LL_ADC_GROUP_REGULAR_INJECTED));
+ 3920              		.loc 1 3061 72 is_stmt 0 view .LVU1194
+ 3921 00ba AA68     		ldr	r2, [r5, #8]
+ 3922              	.LVL314:
+ 3923              	.LBB508:
+ 3924              	.LBI508:
+5725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3925              		.loc 2 5725 22 is_stmt 1 view .LVU1195
+ 3926              	.LBB509:
+5731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_C
+ 3927              		.loc 2 5731 3 view .LVU1196
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ 3928              		.loc 2 5734 3 view .LVU1197
+ 3929 00bc C368     		ldr	r3, [r0, #12]
+ 3930 00be 23F0FB43 		bic	r3, r3, #2105540608
+ 3931 00c2 23F48003 		bic	r3, r3, #4194304
+ 3932 00c6 02F0F842 		and	r2, r2, #2080374784
+ 3933              	.LVL315:
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ 3934              		.loc 2 5734 3 is_stmt 0 view .LVU1198
+ 3935 00ca 42F0E072 		orr	r2, r2, #29360128
+ 3936 00ce 1343     		orrs	r3, r3, r2
+ 3937 00d0 C360     		str	r3, [r0, #12]
+ 3938              	.LVL316:
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3939              		.loc 2 5737 1 view .LVU1199
+ 3940 00d2 0BE0     		b	.L257
+ 3941              	.LVL317:
+ 3942              	.L251:
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3943              		.loc 2 5737 1 view .LVU1200
+ 3944              	.LBE509:
+ 3945              	.LBE508:
+3051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                           LL_ADC_GROUP_REGULAR));
+ 3946              		.loc 1 3051 11 is_stmt 1 view .LVU1201
+3051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                           LL_ADC_GROUP_REGULAR));
+ 3947              		.loc 1 3051 72 is_stmt 0 view .LVU1202
+ 3948 00d4 AA68     		ldr	r2, [r5, #8]
+ 3949              	.LVL318:
+ 3950              	.LBB510:
+ 3951              	.LBI510:
+5725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3952              		.loc 2 5725 22 is_stmt 1 view .LVU1203
+ 3953              	.LBB511:
+ARM GAS  /tmp/ccICigVb.s 			page 294
+
+
+5731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_C
+ 3954              		.loc 2 5731 3 view .LVU1204
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ 3955              		.loc 2 5734 3 view .LVU1205
+ 3956 00d6 C368     		ldr	r3, [r0, #12]
+ 3957 00d8 23F0FB43 		bic	r3, r3, #2105540608
+ 3958 00dc 23F48003 		bic	r3, r3, #4194304
+ 3959 00e0 02F0F842 		and	r2, r2, #2080374784
+ 3960              	.LVL319:
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ 3961              		.loc 2 5734 3 is_stmt 0 view .LVU1206
+ 3962 00e4 42F44002 		orr	r2, r2, #12582912
+ 3963 00e8 1343     		orrs	r3, r3, r2
+ 3964 00ea C360     		str	r3, [r0, #12]
+ 3965              	.LVL320:
+ 3966              	.L257:
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ 3967              		.loc 2 5734 3 view .LVU1207
+ 3968              	.LBE511:
+ 3969              	.LBE510:
+3083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                  ADC_TR1_AWDFILT,
+ 3970              		.loc 1 3083 7 is_stmt 1 view .LVU1208
+ 3971 00ec 2268     		ldr	r2, [r4]
+ 3972 00ee 136A     		ldr	r3, [r2, #32]
+ 3973 00f0 23F4E043 		bic	r3, r3, #28672
+ 3974 00f4 A969     		ldr	r1, [r5, #24]
+ 3975 00f6 0B43     		orrs	r3, r3, r1
+ 3976 00f8 1362     		str	r3, [r2, #32]
+3088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 3977              		.loc 1 3088 7 view .LVU1209
+ 3978 00fa E36D     		ldr	r3, [r4, #92]
+ 3979 00fc 23F48033 		bic	r3, r3, #65536
+ 3980 0100 E365     		str	r3, [r4, #92]
+3094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 3981              		.loc 1 3094 7 view .LVU1210
+ 3982 0102 2368     		ldr	r3, [r4]
+ 3983              	.LVL321:
+ 3984              	.LBB512:
+ 3985              	.LBI512:
+7079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected command of conversion stop state
+7083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing
+7084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: no command of conversion stop is on going on ADC group injected.
+7086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+7088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
+7090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion data, range fit for
+7094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         all ADC configurations: all ADC resolutions and
+7095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         all oversampling increased data width (for devices
+7096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         with feature oversampling).
+ARM GAS  /tmp/ccICigVb.s 			page 295
+
+
+7097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
+7098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
+7099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
+7100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
+7101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+7103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_1
+7104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_2
+7105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_3
+7106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_4
+7107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+7108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+7110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK
+7112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(*preg,
+7114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              ADC_JDR1_JDATA)
+7115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                    );
+7116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion data, range fit for
+7120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC resolution 12 bits.
+7121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with feature oversampling: Oversampling
+7122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         can increase data width, function for extended range
+7123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+7124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
+7125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
+7126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
+7127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
+7128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+7130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_1
+7131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_2
+7132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_3
+7133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_4
+7134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+7135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+7137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK
+7139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint16_t)(READ_BIT(*preg,
+7141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              ADC_JDR1_JDATA)
+7142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                    );
+7143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion data, range fit for
+7147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC resolution 10 bits.
+7148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with feature oversampling: Oversampling
+7149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         can increase data width, function for extended range
+7150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+7151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
+7152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
+7153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
+ARM GAS  /tmp/ccICigVb.s 			page 296
+
+
+7154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
+7155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+7157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_1
+7158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_2
+7159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_3
+7160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_4
+7161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+7162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
+7164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK
+7166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint16_t)(READ_BIT(*preg,
+7168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              ADC_JDR1_JDATA)
+7169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                    );
+7170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion data, range fit for
+7174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC resolution 8 bits.
+7175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with feature oversampling: Oversampling
+7176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         can increase data width, function for extended range
+7177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+7178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
+7179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
+7180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
+7181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
+7182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+7184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_1
+7185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_2
+7186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_3
+7187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_4
+7188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+7189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
+7191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK
+7193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint8_t)(READ_BIT(*preg,
+7195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                             ADC_JDR1_JDATA)
+7196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                   );
+7197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion data, range fit for
+7201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC resolution 6 bits.
+7202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with feature oversampling: Oversampling
+7203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         can increase data width, function for extended range
+7204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+7205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n
+7206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n
+7207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n
+7208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6
+7209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+ARM GAS  /tmp/ccICigVb.s 			page 297
+
+
+7211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_1
+7212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_2
+7213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_3
+7214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_4
+7215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+7216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
+7218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK
+7220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint8_t)(READ_BIT(*preg,
+7222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                             ADC_JDR1_JDATA)
+7223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                   );
+7224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+7228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+7231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+7232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag ADC ready.
+7236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+7237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is enabled and when conversion clock is active.
+7238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (not only core clock: this ADC has a dual clock domain)
+7239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
+7240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
+7244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
+7246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag ADC group regular end of unitary conversion.
+7250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
+7251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
+7255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
+7257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag ADC group regular end of sequence conversions.
+7261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
+7262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
+7266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
+ARM GAS  /tmp/ccICigVb.s 			page 298
+
+
+7268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag ADC group regular overrun.
+7272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
+7273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
+7277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
+7279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag ADC group regular end of sampling phase.
+7283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
+7284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
+7288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
+7290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag ADC group injected end of unitary conversion.
+7294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC
+7295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
+7299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
+7301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag ADC group injected end of sequence conversions.
+7305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS
+7306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+7310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
+7312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag ADC group injected contexts queue overflow.
+7316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF
+7317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
+7321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
+7323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ARM GAS  /tmp/ccICigVb.s 			page 299
+
+
+7325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag ADC analog watchdog 1 flag
+7327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
+7328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+7332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
+7334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag ADC analog watchdog 2.
+7338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
+7339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
+7343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
+7345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag ADC analog watchdog 3.
+7349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
+7350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
+7354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
+7356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Clear flag ADC ready.
+7360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+7361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is enabled and when conversion clock is active.
+7362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (not only core clock: this ADC has a dual clock domain)
+7363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
+7364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
+7368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
+7370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Clear flag ADC group regular end of unitary conversion.
+7374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
+7375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
+7379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
+7381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/ccICigVb.s 			page 300
+
+
+7382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Clear flag ADC group regular end of sequence conversions.
+7385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
+7386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+7390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
+7392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Clear flag ADC group regular overrun.
+7396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
+7397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+7401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
+7403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Clear flag ADC group regular end of sampling phase.
+7407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
+7408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
+7412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
+7414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Clear flag ADC group injected end of unitary conversion.
+7418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC
+7419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
+7423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
+7425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Clear flag ADC group injected end of sequence conversions.
+7429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS
+7430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+7434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
+7436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 301
+
+
+7439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Clear flag ADC group injected contexts queue overflow.
+7440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF
+7441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
+7445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
+7447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Clear flag ADC analog watchdog 1.
+7451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
+7452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+ 3986              		.loc 2 7455 22 view .LVU1211
+ 3987              	.LBB513:
+7456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
+ 3988              		.loc 2 7457 3 view .LVU1212
+ 3989 0104 8022     		movs	r2, #128
+ 3990 0106 1A60     		str	r2, [r3]
+ 3991              	.LVL322:
+ 3992              		.loc 2 7457 3 is_stmt 0 view .LVU1213
+ 3993              	.LBE513:
+ 3994              	.LBE512:
+3097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3995              		.loc 1 3097 7 is_stmt 1 view .LVU1214
+3097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3996              		.loc 1 3097 26 is_stmt 0 view .LVU1215
+ 3997 0108 2B7B     		ldrb	r3, [r5, #12]	@ zero_extendqisi2
+3097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 3998              		.loc 1 3097 10 view .LVU1216
+ 3999 010a 012B     		cmp	r3, #1
+ 4000 010c 22D0     		beq	.L285
+3103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 4001              		.loc 1 3103 9 is_stmt 1 view .LVU1217
+ 4002 010e 2268     		ldr	r2, [r4]
+ 4003              	.LVL323:
+ 4004              	.LBB514:
+ 4005              	.LBI514:
+7458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Clear flag ADC analog watchdog 2.
+7462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
+7463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
+7467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
+7469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 302
+
+
+7472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Clear flag ADC analog watchdog 3.
+7473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
+7474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
+7478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
+7480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+7483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC ready of the ADC master.
+7485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY
+7486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
+7491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0
+7493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC ready of the ADC slave.
+7497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY
+7498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
+7503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0
+7505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.
+7509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC
+7510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
+7515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
+7517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
+7521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC
+7522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
+7527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
+ARM GAS  /tmp/ccICigVb.s 			page 303
+
+
+7529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.
+7533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS
+7534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+7539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
+7541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
+7545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS
+7546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+7551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
+7553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group regular overrun of the ADC master.
+7557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR
+7558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+7563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
+7565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group regular overrun of the ADC slave.
+7569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR
+7570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+7575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
+7577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.
+7581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP
+7582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ARM GAS  /tmp/ccICigVb.s 			page 304
+
+
+7586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
+7587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0
+7589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.
+7593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP
+7594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
+7599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0
+7601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.
+7605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC
+7606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
+7611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL
+7613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
+7617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC
+7618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
+7623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL
+7625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.
+7629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS
+7630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+7635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL
+7637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
+7641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS
+7642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+ARM GAS  /tmp/ccICigVb.s 			page 305
+
+
+7643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+7647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL
+7649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.
+7653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF
+7654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
+7659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0
+7661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.
+7665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF
+7666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
+7671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0
+7673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.
+7677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1
+7678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+7683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL
+7685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode analog watchdog 1 of the ADC slave.
+7689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1
+7690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+7695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL
+7697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 306
+
+
+7700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.
+7701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2
+7702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
+7707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL
+7709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.
+7713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2
+7714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
+7719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL
+7721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.
+7725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3
+7726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
+7731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL
+7733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.
+7737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3
+7738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+7739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+7740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval State of bit (1 or 0).
+7741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
+7743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL
+7745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+7747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+7750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_IT_Management ADC IT management
+7753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+7754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/ccICigVb.s 			page 307
+
+
+7757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable ADC ready.
+7758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
+7759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
+7763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+7765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable interruption ADC group regular end of unitary conversion.
+7769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
+7770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
+7774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
+7776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable interruption ADC group regular end of sequence conversions.
+7780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
+7781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+7785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
+7787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable ADC group regular interruption overrun.
+7791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
+7792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+7796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
+7798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable interruption ADC group regular end of sampling.
+7802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
+7803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
+7807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+7809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable interruption ADC group injected end of unitary conversion.
+7813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC
+ARM GAS  /tmp/ccICigVb.s 			page 308
+
+
+7814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
+7818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+7820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable interruption ADC group injected end of sequence conversions.
+7824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS
+7825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+7829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+7831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable interruption ADC group injected context queue overflow.
+7835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF
+7836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
+7840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+7842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable interruption ADC analog watchdog 1.
+7846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
+7847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+7851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+7853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable interruption ADC analog watchdog 2.
+7857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
+7858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
+7862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+7864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable interruption ADC analog watchdog 3.
+7868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
+7869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+ARM GAS  /tmp/ccICigVb.s 			page 309
+
+
+7871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
+7873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+7875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable interruption ADC ready.
+7879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
+7880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
+7884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+7886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable interruption ADC group regular end of unitary conversion.
+7890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
+7891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
+7895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
+7897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable interruption ADC group regular end of sequence conversions.
+7901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
+7902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+7906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
+7908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable interruption ADC group regular overrun.
+7912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
+7913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+7917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
+7919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable interruption ADC group regular end of sampling.
+7923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
+7924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
+ARM GAS  /tmp/ccICigVb.s 			page 310
+
+
+7928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+7930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable interruption ADC group regular end of unitary conversion.
+7934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC
+7935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
+7939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+7941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable interruption ADC group injected end of sequence conversions.
+7945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS
+7946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+7950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+7952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable interruption ADC group injected context queue overflow.
+7956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF
+7957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
+7961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+7963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable interruption ADC analog watchdog 1.
+7967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
+7968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+ 4006              		.loc 2 7971 22 view .LVU1218
+ 4007              	.LBB515:
+7972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+ 4008              		.loc 2 7973 3 view .LVU1219
+ 4009 0110 5368     		ldr	r3, [r2, #4]
+ 4010 0112 23F08003 		bic	r3, r3, #128
+ 4011 0116 5360     		str	r3, [r2, #4]
+7974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4012              		.loc 2 7974 1 is_stmt 0 view .LVU1220
+ 4013 0118 77E0     		b	.L247
+ 4014              	.LVL324:
+ 4015              	.L249:
+ARM GAS  /tmp/ccICigVb.s 			page 311
+
+
+ 4016              		.loc 2 7974 1 view .LVU1221
+ 4017              	.LBE515:
+ 4018              	.LBE514:
+3056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                           LL_ADC_GROUP_INJECTED));
+ 4019              		.loc 1 3056 11 is_stmt 1 view .LVU1222
+3056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                           LL_ADC_GROUP_INJECTED));
+ 4020              		.loc 1 3056 72 is_stmt 0 view .LVU1223
+ 4021 011a AA68     		ldr	r2, [r5, #8]
+ 4022              	.LVL325:
+ 4023              	.LBB516:
+ 4024              	.LBI516:
+5725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4025              		.loc 2 5725 22 is_stmt 1 view .LVU1224
+ 4026              	.LBB517:
+5731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_C
+ 4027              		.loc 2 5731 3 view .LVU1225
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ 4028              		.loc 2 5734 3 view .LVU1226
+ 4029 011c C368     		ldr	r3, [r0, #12]
+ 4030 011e 23F0FB43 		bic	r3, r3, #2105540608
+ 4031 0122 23F48003 		bic	r3, r3, #4194304
+ 4032 0126 02F0F842 		and	r2, r2, #2080374784
+ 4033              	.LVL326:
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ 4034              		.loc 2 5734 3 is_stmt 0 view .LVU1227
+ 4035 012a 42F0A072 		orr	r2, r2, #20971520
+ 4036 012e 1343     		orrs	r3, r3, r2
+ 4037 0130 C360     		str	r3, [r0, #12]
+ 4038              	.LVL327:
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4039              		.loc 2 5737 1 view .LVU1228
+ 4040 0132 DBE7     		b	.L257
+ 4041              	.LVL328:
+ 4042              	.L255:
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4043              		.loc 2 5737 1 view .LVU1229
+ 4044              	.LBE517:
+ 4045              	.LBE516:
+3074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+ 4046              		.loc 1 3074 11 is_stmt 1 view .LVU1230
+ 4047              	.LBB518:
+ 4048              	.LBI518:
+5725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4049              		.loc 2 5725 22 view .LVU1231
+ 4050              	.LBB519:
+5731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_C
+ 4051              		.loc 2 5731 3 view .LVU1232
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ 4052              		.loc 2 5734 3 view .LVU1233
+ 4053 0134 C368     		ldr	r3, [r0, #12]
+ 4054 0136 23F0FB43 		bic	r3, r3, #2105540608
+ 4055 013a 23F48003 		bic	r3, r3, #4194304
+ 4056 013e 43F0C073 		orr	r3, r3, #25165824
+ 4057 0142 C360     		str	r3, [r0, #12]
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4058              		.loc 2 5737 1 is_stmt 0 view .LVU1234
+ 4059 0144 D2E7     		b	.L257
+ARM GAS  /tmp/ccICigVb.s 			page 312
+
+
+ 4060              	.LVL329:
+ 4061              	.L254:
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4062              		.loc 2 5737 1 view .LVU1235
+ 4063              	.LBE519:
+ 4064              	.LBE518:
+3078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+ 4065              		.loc 1 3078 11 is_stmt 1 view .LVU1236
+ 4066              	.LBB520:
+ 4067              	.LBI520:
+5725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4068              		.loc 2 5725 22 view .LVU1237
+ 4069              	.LBB521:
+5731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_C
+ 4070              		.loc 2 5731 3 view .LVU1238
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ 4071              		.loc 2 5734 3 view .LVU1239
+ 4072 0146 C368     		ldr	r3, [r0, #12]
+ 4073 0148 23F0FB43 		bic	r3, r3, #2105540608
+ 4074 014c 23F48003 		bic	r3, r3, #4194304
+ 4075 0150 C360     		str	r3, [r0, #12]
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4076              		.loc 2 5737 1 is_stmt 0 view .LVU1240
+ 4077 0152 CBE7     		b	.L257
+ 4078              	.LVL330:
+ 4079              	.L285:
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4080              		.loc 2 5737 1 view .LVU1241
+ 4081              	.LBE521:
+ 4082              	.LBE520:
+3099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 4083              		.loc 1 3099 9 is_stmt 1 view .LVU1242
+ 4084 0154 2268     		ldr	r2, [r4]
+ 4085              	.LVL331:
+ 4086              	.LBB522:
+ 4087              	.LBI522:
+7850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4088              		.loc 2 7850 22 view .LVU1243
+ 4089              	.LBB523:
+7852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4090              		.loc 2 7852 3 view .LVU1244
+ 4091 0156 5368     		ldr	r3, [r2, #4]
+ 4092 0158 43F08003 		orr	r3, r3, #128
+ 4093 015c 5360     		str	r3, [r2, #4]
+7853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4094              		.loc 2 7853 1 is_stmt 0 view .LVU1245
+ 4095 015e 54E0     		b	.L247
+ 4096              	.LVL332:
+ 4097              	.L260:
+7853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4098              		.loc 2 7853 1 view .LVU1246
+ 4099              	.LBE523:
+ 4100              	.LBE522:
+3109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4101              		.loc 1 3109 7 view .LVU1247
+ 4102 0160 B3F1C07F 		cmp	r3, #25165824
+ 4103 0164 3AD0     		beq	.L261
+ARM GAS  /tmp/ccICigVb.s 			page 313
+
+
+ 4104 0166 B3F1E07F 		cmp	r3, #29360128
+ 4105 016a 7FF47CAF 		bne	.L262
+ 4106              	.L259:
+3116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 4107              		.loc 1 3116 11 is_stmt 1 view .LVU1248
+3116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 4108              		.loc 1 3116 14 is_stmt 0 view .LVU1249
+ 4109 016e 5D4B     		ldr	r3, .L291+4
+ 4110 0170 9942     		cmp	r1, r3
+ 4111 0172 0DD0     		beq	.L286
+3122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 4112              		.loc 1 3122 13 is_stmt 1 view .LVU1250
+ 4113 0174 AB68     		ldr	r3, [r5, #8]
+ 4114 0176 C3F31202 		ubfx	r2, r3, #0, #19
+ 4115              	.LVL333:
+3122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 4116              		.loc 1 3122 13 is_stmt 0 view .LVU1251
+ 4117 017a 1ABB     		cbnz	r2, .L268
+3122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 4118              		.loc 1 3122 13 discriminator 1 view .LVU1252
+ 4119 017c C3F38463 		ubfx	r3, r3, #26, #5
+ 4120 0180 0122     		movs	r2, #1
+ 4121 0182 9A40     		lsls	r2, r2, r3
+ 4122              	.L269:
+3122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 4123              		.loc 1 3122 13 discriminator 4 view .LVU1253
+ 4124 0184 D0F8A430 		ldr	r3, [r0, #164]
+ 4125 0188 1343     		orrs	r3, r3, r2
+ 4126 018a C0F8A430 		str	r3, [r0, #164]
+ 4127 018e 28E0     		b	.L267
+ 4128              	.LVL334:
+ 4129              	.L286:
+3118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 4130              		.loc 1 3118 13 is_stmt 1 view .LVU1254
+ 4131 0190 AB68     		ldr	r3, [r5, #8]
+ 4132 0192 C3F31202 		ubfx	r2, r3, #0, #19
+ 4133              	.LVL335:
+3118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 4134              		.loc 1 3118 13 is_stmt 0 view .LVU1255
+ 4135 0196 4AB9     		cbnz	r2, .L264
+3118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 4136              		.loc 1 3118 13 discriminator 1 view .LVU1256
+ 4137 0198 C3F38463 		ubfx	r3, r3, #26, #5
+ 4138 019c 0122     		movs	r2, #1
+ 4139 019e 9A40     		lsls	r2, r2, r3
+ 4140              	.L265:
+3118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 4141              		.loc 1 3118 13 discriminator 4 view .LVU1257
+ 4142 01a0 D0F8A030 		ldr	r3, [r0, #160]
+ 4143 01a4 1343     		orrs	r3, r3, r2
+ 4144 01a6 C0F8A030 		str	r3, [r0, #160]
+ 4145 01aa 1AE0     		b	.L267
+ 4146              	.L264:
+ 4147              	.LVL336:
+ 4148              	.LBB524:
+ 4149              	.LBI524:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccICigVb.s 			page 314
+
+
+ 4150              		.loc 3 1048 31 is_stmt 1 discriminator 2 view .LVU1258
+ 4151              	.LBB525:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4152              		.loc 3 1050 3 discriminator 2 view .LVU1259
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 4153              		.loc 3 1055 4 discriminator 2 view .LVU1260
+ 4154              		.syntax unified
+ 4155              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4156 01ac 93FAA3F3 		rbit r3, r3
+ 4157              	@ 0 "" 2
+ 4158              	.LVL337:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4159              		.loc 3 1068 3 discriminator 2 view .LVU1261
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4160              		.loc 3 1068 3 is_stmt 0 discriminator 2 view .LVU1262
+ 4161              		.thumb
+ 4162              		.syntax unified
+ 4163              	.LBE525:
+ 4164              	.LBE524:
+ 4165              	.LBB526:
+ 4166              	.LBI526:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4167              		.loc 3 1078 30 is_stmt 1 discriminator 2 view .LVU1263
+ 4168              	.LBB527:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4169              		.loc 3 1089 3 discriminator 2 view .LVU1264
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4170              		.loc 3 1089 6 is_stmt 0 discriminator 2 view .LVU1265
+ 4171 01b0 33B1     		cbz	r3, .L280
+ 4172              		.loc 3 1093 3 is_stmt 1 view .LVU1266
+ 4173              		.loc 3 1093 10 is_stmt 0 view .LVU1267
+ 4174 01b2 B3FA83F3 		clz	r3, r3
+ 4175              	.LVL338:
+ 4176              	.L266:
+ 4177              		.loc 3 1093 10 view .LVU1268
+ 4178              	.LBE527:
+ 4179              	.LBE526:
+3118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 4180              		.loc 1 3118 13 view .LVU1269
+ 4181 01b6 03F01F03 		and	r3, r3, #31
+ 4182 01ba 0122     		movs	r2, #1
+ 4183 01bc 9A40     		lsls	r2, r2, r3
+ 4184 01be EFE7     		b	.L265
+ 4185              	.LVL339:
+ 4186              	.L280:
+ 4187              	.LBB529:
+ 4188              	.LBB528:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4189              		.loc 3 1091 12 view .LVU1270
+ 4190 01c0 2023     		movs	r3, #32
+ 4191              	.LVL340:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4192              		.loc 3 1091 12 view .LVU1271
+ 4193 01c2 F8E7     		b	.L266
+ 4194              	.LVL341:
+ 4195              	.L268:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ARM GAS  /tmp/ccICigVb.s 			page 315
+
+
+ 4196              		.loc 3 1091 12 view .LVU1272
+ 4197              	.LBE528:
+ 4198              	.LBE529:
+ 4199              	.LBB530:
+ 4200              	.LBI530:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4201              		.loc 3 1048 31 is_stmt 1 discriminator 2 view .LVU1273
+ 4202              	.LBB531:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4203              		.loc 3 1050 3 discriminator 2 view .LVU1274
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 4204              		.loc 3 1055 4 discriminator 2 view .LVU1275
+ 4205              		.syntax unified
+ 4206              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4207 01c4 93FAA3F3 		rbit r3, r3
+ 4208              	@ 0 "" 2
+ 4209              	.LVL342:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4210              		.loc 3 1068 3 discriminator 2 view .LVU1276
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4211              		.loc 3 1068 3 is_stmt 0 discriminator 2 view .LVU1277
+ 4212              		.thumb
+ 4213              		.syntax unified
+ 4214              	.LBE531:
+ 4215              	.LBE530:
+ 4216              	.LBB532:
+ 4217              	.LBI532:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4218              		.loc 3 1078 30 is_stmt 1 discriminator 2 view .LVU1278
+ 4219              	.LBB533:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4220              		.loc 3 1089 3 discriminator 2 view .LVU1279
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4221              		.loc 3 1089 6 is_stmt 0 discriminator 2 view .LVU1280
+ 4222 01c8 33B1     		cbz	r3, .L281
+ 4223              		.loc 3 1093 3 is_stmt 1 view .LVU1281
+ 4224              		.loc 3 1093 10 is_stmt 0 view .LVU1282
+ 4225 01ca B3FA83F3 		clz	r3, r3
+ 4226              	.LVL343:
+ 4227              	.L270:
+ 4228              		.loc 3 1093 10 view .LVU1283
+ 4229              	.LBE533:
+ 4230              	.LBE532:
+3122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 4231              		.loc 1 3122 13 view .LVU1284
+ 4232 01ce 03F01F03 		and	r3, r3, #31
+ 4233 01d2 0122     		movs	r2, #1
+ 4234 01d4 9A40     		lsls	r2, r2, r3
+ 4235 01d6 D5E7     		b	.L269
+ 4236              	.LVL344:
+ 4237              	.L281:
+ 4238              	.LBB535:
+ 4239              	.LBB534:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4240              		.loc 3 1091 12 view .LVU1285
+ 4241 01d8 2023     		movs	r3, #32
+ 4242              	.LVL345:
+ARM GAS  /tmp/ccICigVb.s 			page 316
+
+
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4243              		.loc 3 1091 12 view .LVU1286
+ 4244 01da F8E7     		b	.L270
+ 4245              	.LVL346:
+ 4246              	.L261:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4247              		.loc 3 1091 12 view .LVU1287
+ 4248              	.LBE534:
+ 4249              	.LBE535:
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+ 4250              		.loc 1 3129 11 is_stmt 1 view .LVU1288
+ 4251 01dc 424A     		ldr	r2, .L291+8
+ 4252              	.LVL347:
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+ 4253              		.loc 1 3129 11 is_stmt 0 view .LVU1289
+ 4254 01de FFF7FEFF 		bl	LL_ADC_SetAnalogWDMonitChannels
+ 4255              	.LVL348:
+3130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4256              		.loc 1 3130 11 is_stmt 1 view .LVU1290
+ 4257              	.L267:
+3137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4258              		.loc 1 3137 7 view .LVU1291
+3137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4259              		.loc 1 3137 26 is_stmt 0 view .LVU1292
+ 4260 01e2 2A68     		ldr	r2, [r5]
+3137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4261              		.loc 1 3137 10 view .LVU1293
+ 4262 01e4 3F4B     		ldr	r3, .L291+4
+ 4263 01e6 9A42     		cmp	r2, r3
+ 4264 01e8 44D0     		beq	.L287
+3162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4265              		.loc 1 3162 9 is_stmt 1 view .LVU1294
+ 4266 01ea E36D     		ldr	r3, [r4, #92]
+ 4267 01ec 23F48023 		bic	r3, r3, #262144
+ 4268 01f0 E365     		str	r3, [r4, #92]
+3168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4269              		.loc 1 3168 9 view .LVU1295
+ 4270 01f2 2368     		ldr	r3, [r4]
+ 4271              	.LVL349:
+ 4272              	.LBB536:
+ 4273              	.LBI536:
+7477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4274              		.loc 2 7477 22 view .LVU1296
+ 4275              	.LBB537:
+7479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4276              		.loc 2 7479 3 view .LVU1297
+ 4277 01f4 4FF40072 		mov	r2, #512
+ 4278 01f8 1A60     		str	r2, [r3]
+ 4279              	.LVL350:
+7479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4280              		.loc 2 7479 3 is_stmt 0 view .LVU1298
+ 4281              	.LBE537:
+ 4282              	.LBE536:
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 4283              		.loc 1 3171 9 is_stmt 1 view .LVU1299
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 4284              		.loc 1 3171 28 is_stmt 0 view .LVU1300
+ARM GAS  /tmp/ccICigVb.s 			page 317
+
+
+ 4285 01fa 2B7B     		ldrb	r3, [r5, #12]	@ zero_extendqisi2
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 4286              		.loc 1 3171 12 view .LVU1301
+ 4287 01fc 012B     		cmp	r3, #1
+ 4288 01fe 50D0     		beq	.L288
+3177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 4289              		.loc 1 3177 11 is_stmt 1 view .LVU1302
+ 4290 0200 2268     		ldr	r2, [r4]
+ 4291              	.LVL351:
+ 4292              	.LBB538:
+ 4293              	.LBI538:
+7975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable interruption ADC analog watchdog 2.
+7978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
+7979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
+7983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+7985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable interruption ADC analog watchdog 3.
+7989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
+7990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
+ 4294              		.loc 2 7993 22 view .LVU1303
+ 4295              	.LBB539:
+7994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+ 4296              		.loc 2 7995 3 view .LVU1304
+ 4297 0202 5368     		ldr	r3, [r2, #4]
+ 4298 0204 23F40073 		bic	r3, r3, #512
+ 4299 0208 5360     		str	r3, [r2, #4]
+ 4300              	.LVL352:
+ 4301              	.L247:
+ 4302              		.loc 2 7995 3 is_stmt 0 view .LVU1305
+ 4303              	.LBE539:
+ 4304              	.LBE538:
+3185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 4305              		.loc 1 3185 3 is_stmt 1 view .LVU1306
+3185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 4306              		.loc 1 3185 22 is_stmt 0 view .LVU1307
+ 4307 020a 2B68     		ldr	r3, [r5]
+3185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 4308              		.loc 1 3185 6 view .LVU1308
+ 4309 020c 344A     		ldr	r2, .L291
+ 4310 020e 9342     		cmp	r3, r2
+ 4311 0210 4DD0     		beq	.L289
+3199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThre
+ 4312              		.loc 1 3199 5 is_stmt 1 view .LVU1309
+3199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThre
+ 4313              		.loc 1 3199 34 is_stmt 0 view .LVU1310
+ARM GAS  /tmp/ccICigVb.s 			page 318
+
+
+ 4314 0212 2068     		ldr	r0, [r4]
+ 4315 0214 C268     		ldr	r2, [r0, #12]
+ 4316 0216 02F01802 		and	r2, r2, #24
+ 4317 021a 182A     		cmp	r2, #24
+ 4318 021c 56D0     		beq	.L276
+3199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThre
+ 4319              		.loc 1 3199 34 discriminator 1 view .LVU1311
+ 4320 021e 2969     		ldr	r1, [r5, #16]
+ 4321 0220 C268     		ldr	r2, [r0, #12]
+ 4322 0222 C2F3C102 		ubfx	r2, r2, #3, #2
+ 4323 0226 C2F10202 		rsb	r2, r2, #2
+ 4324 022a 5200     		lsls	r2, r2, #1
+ 4325 022c 02F01E02 		and	r2, r2, #30
+ 4326 0230 21FA02FC 		lsr	ip, r1, r2
+ 4327              	.L277:
+ 4328              	.LVL353:
+3200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 4329              		.loc 1 3200 5 is_stmt 1 discriminator 4 view .LVU1312
+3200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 4330              		.loc 1 3200 34 is_stmt 0 discriminator 4 view .LVU1313
+ 4331 0234 C268     		ldr	r2, [r0, #12]
+ 4332 0236 02F01802 		and	r2, r2, #24
+ 4333 023a 182A     		cmp	r2, #24
+ 4334 023c 4AD0     		beq	.L278
+3200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 4335              		.loc 1 3200 34 discriminator 1 view .LVU1314
+ 4336 023e 6969     		ldr	r1, [r5, #20]
+ 4337 0240 C268     		ldr	r2, [r0, #12]
+ 4338 0242 C2F3C102 		ubfx	r2, r2, #3, #2
+ 4339 0246 C2F10202 		rsb	r2, r2, #2
+ 4340 024a 5200     		lsls	r2, r2, #1
+ 4341 024c 02F01E02 		and	r2, r2, #30
+ 4342 0250 D140     		lsrs	r1, r1, r2
+ 4343              	.L275:
+ 4344              	.LVL354:
+3204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                   tmpAWDLowThresholdShifted);
+ 4345              		.loc 1 3204 3 is_stmt 1 view .LVU1315
+ 4346 0252 2068     		ldr	r0, [r4]
+ 4347              	.LVL355:
+ 4348              	.LBB540:
+ 4349              	.LBI540:
+5965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                      uint32_t AWDThresholdLowValue)
+ 4350              		.loc 2 5965 22 view .LVU1316
+ 4351              	.LBB541:
+5973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4352              		.loc 2 5973 3 view .LVU1317
+5973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4353              		.loc 2 5973 25 is_stmt 0 view .LVU1318
+ 4354 0254 2030     		adds	r0, r0, #32
+ 4355              	.LVL356:
+5973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4356              		.loc 2 5973 25 view .LVU1319
+ 4357 0256 1B0D     		lsrs	r3, r3, #20
+ 4358              	.LVL357:
+5973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4359              		.loc 2 5973 25 view .LVU1320
+ 4360 0258 9B00     		lsls	r3, r3, #2
+ARM GAS  /tmp/ccICigVb.s 			page 319
+
+
+ 4361 025a 03F00C03 		and	r3, r3, #12
+ 4362              	.LVL358:
+5975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_TR1_HT1 | ADC_TR1_LT1,
+ 4363              		.loc 2 5975 3 is_stmt 1 view .LVU1321
+ 4364 025e C258     		ldr	r2, [r0, r3]
+ 4365 0260 02F0F022 		and	r2, r2, #-268374016
+ 4366 0264 41EA0C41 		orr	r1, r1, ip, lsl #16
+ 4367              	.LVL359:
+5975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_TR1_HT1 | ADC_TR1_LT1,
+ 4368              		.loc 2 5975 3 is_stmt 0 view .LVU1322
+ 4369 0268 0A43     		orrs	r2, r2, r1
+ 4370 026a C250     		str	r2, [r0, r3]
+ 4371              	.LVL360:
+5975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_TR1_HT1 | ADC_TR1_LT1,
+ 4372              		.loc 2 5975 3 view .LVU1323
+ 4373              	.LBE541:
+ 4374              	.LBE540:
+3208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4375              		.loc 1 3208 3 is_stmt 1 view .LVU1324
+3208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4376              		.loc 1 3208 3 view .LVU1325
+ 4377 026c 0020     		movs	r0, #0
+ 4378 026e 84F85800 		strb	r0, [r4, #88]
+3208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4379              		.loc 1 3208 3 view .LVU1326
+3211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 4380              		.loc 1 3211 3 view .LVU1327
+ 4381              	.LVL361:
+ 4382              	.L244:
+3212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4383              		.loc 1 3212 1 is_stmt 0 view .LVU1328
+ 4384 0272 38BD     		pop	{r3, r4, r5, pc}
+ 4385              	.LVL362:
+ 4386              	.L287:
+3140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4387              		.loc 1 3140 9 is_stmt 1 view .LVU1329
+ 4388 0274 E36D     		ldr	r3, [r4, #92]
+ 4389 0276 23F40033 		bic	r3, r3, #131072
+ 4390 027a E365     		str	r3, [r4, #92]
+3146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4391              		.loc 1 3146 9 view .LVU1330
+ 4392 027c 2368     		ldr	r3, [r4]
+ 4393              	.LVL363:
+ 4394              	.LBB542:
+ 4395              	.LBI542:
+7466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4396              		.loc 2 7466 22 view .LVU1331
+ 4397              	.LBB543:
+7468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4398              		.loc 2 7468 3 view .LVU1332
+ 4399 027e 4FF48072 		mov	r2, #256
+ 4400 0282 1A60     		str	r2, [r3]
+ 4401              	.LVL364:
+7468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4402              		.loc 2 7468 3 is_stmt 0 view .LVU1333
+ 4403              	.LBE543:
+ 4404              	.LBE542:
+ARM GAS  /tmp/ccICigVb.s 			page 320
+
+
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 4405              		.loc 1 3149 9 is_stmt 1 view .LVU1334
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 4406              		.loc 1 3149 28 is_stmt 0 view .LVU1335
+ 4407 0284 2B7B     		ldrb	r3, [r5, #12]	@ zero_extendqisi2
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 4408              		.loc 1 3149 12 view .LVU1336
+ 4409 0286 012B     		cmp	r3, #1
+ 4410 0288 05D0     		beq	.L290
+3155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 4411              		.loc 1 3155 11 is_stmt 1 view .LVU1337
+ 4412 028a 2268     		ldr	r2, [r4]
+ 4413              	.LVL365:
+ 4414              	.LBB544:
+ 4415              	.LBI544:
+7982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4416              		.loc 2 7982 22 view .LVU1338
+ 4417              	.LBB545:
+7984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4418              		.loc 2 7984 3 view .LVU1339
+ 4419 028c 5368     		ldr	r3, [r2, #4]
+ 4420 028e 23F48073 		bic	r3, r3, #256
+ 4421 0292 5360     		str	r3, [r2, #4]
+7985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4422              		.loc 2 7985 1 is_stmt 0 view .LVU1340
+ 4423 0294 B9E7     		b	.L247
+ 4424              	.LVL366:
+ 4425              	.L290:
+7985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4426              		.loc 2 7985 1 view .LVU1341
+ 4427              	.LBE545:
+ 4428              	.LBE544:
+3151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 4429              		.loc 1 3151 11 is_stmt 1 view .LVU1342
+ 4430 0296 2268     		ldr	r2, [r4]
+ 4431              	.LVL367:
+ 4432              	.LBB546:
+ 4433              	.LBI546:
+7861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4434              		.loc 2 7861 22 view .LVU1343
+ 4435              	.LBB547:
+7863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4436              		.loc 2 7863 3 view .LVU1344
+ 4437 0298 5368     		ldr	r3, [r2, #4]
+ 4438 029a 43F48073 		orr	r3, r3, #256
+ 4439 029e 5360     		str	r3, [r2, #4]
+7864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4440              		.loc 2 7864 1 is_stmt 0 view .LVU1345
+ 4441 02a0 B3E7     		b	.L247
+ 4442              	.LVL368:
+ 4443              	.L288:
+7864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4444              		.loc 2 7864 1 view .LVU1346
+ 4445              	.LBE547:
+ 4446              	.LBE546:
+3173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 4447              		.loc 1 3173 11 is_stmt 1 view .LVU1347
+ARM GAS  /tmp/ccICigVb.s 			page 321
+
+
+ 4448 02a2 2268     		ldr	r2, [r4]
+ 4449              	.LVL369:
+ 4450              	.LBB548:
+ 4451              	.LBI548:
+7872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4452              		.loc 2 7872 22 view .LVU1348
+ 4453              	.LBB549:
+7874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4454              		.loc 2 7874 3 view .LVU1349
+ 4455 02a4 5368     		ldr	r3, [r2, #4]
+ 4456 02a6 43F40073 		orr	r3, r3, #512
+ 4457 02aa 5360     		str	r3, [r2, #4]
+7875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4458              		.loc 2 7875 1 is_stmt 0 view .LVU1350
+ 4459 02ac ADE7     		b	.L247
+ 4460              	.LVL370:
+ 4461              	.L289:
+7875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4462              		.loc 2 7875 1 view .LVU1351
+ 4463              	.LBE549:
+ 4464              	.LBE548:
+3190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThres
+ 4465              		.loc 1 3190 5 is_stmt 1 view .LVU1352
+3190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThres
+ 4466              		.loc 1 3190 34 is_stmt 0 view .LVU1353
+ 4467 02ae 2969     		ldr	r1, [r5, #16]
+ 4468 02b0 2068     		ldr	r0, [r4]
+ 4469 02b2 C268     		ldr	r2, [r0, #12]
+ 4470 02b4 C2F3C102 		ubfx	r2, r2, #3, #2
+ 4471 02b8 5200     		lsls	r2, r2, #1
+3190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThres
+ 4472              		.loc 1 3190 32 view .LVU1354
+ 4473 02ba 01FA02FC 		lsl	ip, r1, r2
+ 4474              	.LVL371:
+3191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 4475              		.loc 1 3191 5 is_stmt 1 view .LVU1355
+3191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 4476              		.loc 1 3191 34 is_stmt 0 view .LVU1356
+ 4477 02be 6969     		ldr	r1, [r5, #20]
+ 4478 02c0 C268     		ldr	r2, [r0, #12]
+ 4479 02c2 C2F3C102 		ubfx	r2, r2, #3, #2
+ 4480 02c6 5200     		lsls	r2, r2, #1
+3191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 4481              		.loc 1 3191 32 view .LVU1357
+ 4482 02c8 9140     		lsls	r1, r1, r2
+ 4483              	.LVL372:
+3191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 4484              		.loc 1 3191 32 view .LVU1358
+ 4485 02ca C2E7     		b	.L275
+ 4486              	.LVL373:
+ 4487              	.L276:
+3199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThre
+ 4488              		.loc 1 3199 34 discriminator 2 view .LVU1359
+ 4489 02cc 2A69     		ldr	r2, [r5, #16]
+ 4490 02ce 4FEA820C 		lsl	ip, r2, #2
+ 4491 02d2 AFE7     		b	.L277
+ 4492              	.LVL374:
+ARM GAS  /tmp/ccICigVb.s 			page 322
+
+
+ 4493              	.L278:
+3200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 4494              		.loc 1 3200 34 discriminator 2 view .LVU1360
+ 4495 02d4 6969     		ldr	r1, [r5, #20]
+ 4496 02d6 8900     		lsls	r1, r1, #2
+ 4497 02d8 BBE7     		b	.L275
+ 4498              	.LVL375:
+ 4499              	.L279:
+3030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4500              		.loc 1 3030 3 view .LVU1361
+ 4501 02da 0220     		movs	r0, #2
+ 4502              	.LVL376:
+3030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4503              		.loc 1 3030 3 view .LVU1362
+ 4504 02dc C9E7     		b	.L244
+ 4505              	.L292:
+ 4506 02de 00BF     		.align	2
+ 4507              	.L291:
+ 4508 02e0 0000C07D 		.word	2109734912
+ 4509 02e4 FFFF1700 		.word	1572863
+ 4510 02e8 FFFF8701 		.word	25690111
+ 4511              		.cfi_endproc
+ 4512              	.LFE350:
+ 4514              		.section	.text.HAL_ADC_GetState,"ax",%progbits
+ 4515              		.align	1
+ 4516              		.global	HAL_ADC_GetState
+ 4517              		.syntax unified
+ 4518              		.thumb
+ 4519              		.thumb_func
+ 4521              	HAL_ADC_GetState:
+ 4522              	.LVL377:
+ 4523              	.LFB351:
+3247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+ 4524              		.loc 1 3247 1 is_stmt 1 view -0
+ 4525              		.cfi_startproc
+ 4526              		@ args = 0, pretend = 0, frame = 0
+ 4527              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4528              		@ link register save eliminated.
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4529              		.loc 1 3249 3 view .LVU1364
+3252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 4530              		.loc 1 3252 3 view .LVU1365
+3252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 4531              		.loc 1 3252 14 is_stmt 0 view .LVU1366
+ 4532 0000 C06D     		ldr	r0, [r0, #92]
+ 4533              	.LVL378:
+3253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4534              		.loc 1 3253 1 view .LVU1367
+ 4535 0002 7047     		bx	lr
+ 4536              		.cfi_endproc
+ 4537              	.LFE351:
+ 4539              		.section	.text.HAL_ADC_GetError,"ax",%progbits
+ 4540              		.align	1
+ 4541              		.global	HAL_ADC_GetError
+ 4542              		.syntax unified
+ 4543              		.thumb
+ 4544              		.thumb_func
+ARM GAS  /tmp/ccICigVb.s 			page 323
+
+
+ 4546              	HAL_ADC_GetError:
+ 4547              	.LVL379:
+ 4548              	.LFB352:
+3261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Check the parameters */
+ 4549              		.loc 1 3261 1 is_stmt 1 view -0
+ 4550              		.cfi_startproc
+ 4551              		@ args = 0, pretend = 0, frame = 0
+ 4552              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4553              		@ link register save eliminated.
+3263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4554              		.loc 1 3263 3 view .LVU1369
+3265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 4555              		.loc 1 3265 3 view .LVU1370
+3265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 4556              		.loc 1 3265 14 is_stmt 0 view .LVU1371
+ 4557 0000 006E     		ldr	r0, [r0, #96]
+ 4558              	.LVL380:
+3266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4559              		.loc 1 3266 1 view .LVU1372
+ 4560 0002 7047     		bx	lr
+ 4561              		.cfi_endproc
+ 4562              	.LFE352:
+ 4564              		.section	.text.ADC_ConversionStop,"ax",%progbits
+ 4565              		.align	1
+ 4566              		.global	ADC_ConversionStop
+ 4567              		.syntax unified
+ 4568              		.thumb
+ 4569              		.thumb_func
+ 4571              	ADC_ConversionStop:
+ 4572              	.LVL381:
+ 4573              	.LFB353:
+3291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tickstart;
+ 4574              		.loc 1 3291 1 is_stmt 1 view -0
+ 4575              		.cfi_startproc
+ 4576              		@ args = 0, pretend = 0, frame = 0
+ 4577              		@ frame_needed = 0, uses_anonymous_args = 0
+3291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tickstart;
+ 4578              		.loc 1 3291 1 is_stmt 0 view .LVU1374
+ 4579 0000 70B5     		push	{r4, r5, r6, lr}
+ 4580              	.LCFI20:
+ 4581              		.cfi_def_cfa_offset 16
+ 4582              		.cfi_offset 4, -16
+ 4583              		.cfi_offset 5, -12
+ 4584              		.cfi_offset 6, -8
+ 4585              		.cfi_offset 14, -4
+ 4586 0002 0446     		mov	r4, r0
+3292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t Conversion_Timeout_CPU_cycles = 0UL;
+ 4587              		.loc 1 3292 3 is_stmt 1 view .LVU1375
+3293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t conversion_group_reassigned = ConversionGroup;
+ 4588              		.loc 1 3293 3 view .LVU1376
+ 4589              	.LVL382:
+3294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_ADC_CR_ADSTART_JADSTART;
+ 4590              		.loc 1 3294 3 view .LVU1377
+3295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+ 4591              		.loc 1 3295 3 view .LVU1378
+3296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_adc_is_conversion_on_going_injected;
+ 4592              		.loc 1 3296 3 view .LVU1379
+ARM GAS  /tmp/ccICigVb.s 			page 324
+
+
+3297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4593              		.loc 1 3297 3 view .LVU1380
+3300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
+ 4594              		.loc 1 3300 3 view .LVU1381
+3301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4595              		.loc 1 3301 3 view .LVU1382
+3305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 4596              		.loc 1 3305 3 view .LVU1383
+3305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 4597              		.loc 1 3305 44 is_stmt 0 view .LVU1384
+ 4598 0004 0368     		ldr	r3, [r0]
+ 4599              	.LVL383:
+ 4600              	.LBB550:
+ 4601              	.LBI550:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4602              		.loc 2 6851 26 is_stmt 1 view .LVU1385
+ 4603              	.LBB551:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4604              		.loc 2 6853 3 view .LVU1386
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4605              		.loc 2 6853 12 is_stmt 0 view .LVU1387
+ 4606 0006 9A68     		ldr	r2, [r3, #8]
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4607              		.loc 2 6853 74 view .LVU1388
+ 4608 0008 12F00402 		ands	r2, r2, #4
+ 4609 000c 00D0     		beq	.L296
+ 4610 000e 0122     		movs	r2, #1
+ 4611              	.L296:
+ 4612              	.LVL384:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4613              		.loc 2 6853 74 view .LVU1389
+ 4614              	.LBE551:
+ 4615              	.LBE550:
+3306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   if ((tmp_adc_is_conversion_on_going_regular != 0UL)
+ 4616              		.loc 1 3306 3 is_stmt 1 view .LVU1390
+ 4617              	.LBB552:
+ 4618              	.LBI552:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4619              		.loc 2 7076 26 view .LVU1391
+ 4620              	.LBB553:
+7078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4621              		.loc 2 7078 3 view .LVU1392
+7078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4622              		.loc 2 7078 12 is_stmt 0 view .LVU1393
+ 4623 0010 9868     		ldr	r0, [r3, #8]
+ 4624              	.LVL385:
+7078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4625              		.loc 2 7078 76 view .LVU1394
+ 4626 0012 10F00800 		ands	r0, r0, #8
+ 4627 0016 00D0     		beq	.L297
+ 4628 0018 0120     		movs	r0, #1
+ 4629              	.L297:
+ 4630              	.LVL386:
+7078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4631              		.loc 2 7078 76 view .LVU1395
+ 4632              	.LBE553:
+ 4633              	.LBE552:
+ARM GAS  /tmp/ccICigVb.s 			page 325
+
+
+3307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       || (tmp_adc_is_conversion_on_going_injected != 0UL)
+ 4634              		.loc 1 3307 3 is_stmt 1 view .LVU1396
+3307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       || (tmp_adc_is_conversion_on_going_injected != 0UL)
+ 4635              		.loc 1 3307 6 is_stmt 0 view .LVU1397
+ 4636 001a 0AB9     		cbnz	r2, .L298
+3308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      )
+ 4637              		.loc 1 3308 7 view .LVU1398
+ 4638 001c 0028     		cmp	r0, #0
+ 4639 001e 6DD0     		beq	.L311
+ 4640              	.L298:
+3317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         && (hadc->Init.ContinuousConvMode == ENABLE)
+ 4641              		.loc 1 3317 5 is_stmt 1 view .LVU1399
+3317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         && (hadc->Init.ContinuousConvMode == ENABLE)
+ 4642              		.loc 1 3317 25 is_stmt 0 view .LVU1400
+ 4643 0020 DA68     		ldr	r2, [r3, #12]
+ 4644              	.LVL387:
+3317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         && (hadc->Init.ContinuousConvMode == ENABLE)
+ 4645              		.loc 1 3317 8 view .LVU1401
+ 4646 0022 12F0007F 		tst	r2, #33554432
+ 4647 0026 04D0     		beq	.L300
+3319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        )
+ 4648              		.loc 1 3319 9 view .LVU1402
+ 4649 0028 A08B     		ldrh	r0, [r4, #28]
+ 4650              	.LVL388:
+3319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        )
+ 4651              		.loc 1 3319 9 view .LVU1403
+ 4652 002a 40F20112 		movw	r2, #257
+ 4653 002e 9042     		cmp	r0, r2
+ 4654 0030 4ED0     		beq	.L317
+ 4655              	.L300:
+3346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4656              		.loc 1 3346 5 is_stmt 1 view .LVU1404
+3346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4657              		.loc 1 3346 8 is_stmt 0 view .LVU1405
+ 4658 0032 0229     		cmp	r1, #2
+ 4659 0034 12D0     		beq	.L305
+ 4660              	.LVL389:
+ 4661              	.L304:
+3349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4662              		.loc 1 3349 7 is_stmt 1 view .LVU1406
+3349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4663              		.loc 1 3349 11 is_stmt 0 view .LVU1407
+ 4664 0036 2368     		ldr	r3, [r4]
+ 4665              	.LVL390:
+ 4666              	.LBB554:
+ 4667              	.LBI554:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4668              		.loc 2 6851 26 is_stmt 1 view .LVU1408
+ 4669              	.LBB555:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4670              		.loc 2 6853 3 view .LVU1409
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4671              		.loc 2 6853 12 is_stmt 0 view .LVU1410
+ 4672 0038 9A68     		ldr	r2, [r3, #8]
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4673              		.loc 2 6853 74 view .LVU1411
+ 4674 003a 12F0040F 		tst	r2, #4
+ARM GAS  /tmp/ccICigVb.s 			page 326
+
+
+ 4675 003e 0BD0     		beq	.L306
+ 4676              	.LVL391:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4677              		.loc 2 6853 74 view .LVU1412
+ 4678              	.LBE555:
+ 4679              	.LBE554:
+3351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 4680              		.loc 1 3351 9 is_stmt 1 view .LVU1413
+ 4681              	.LBB556:
+ 4682              	.LBI556:
+6740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4683              		.loc 2 6740 26 view .LVU1414
+ 4684              	.LBB557:
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4685              		.loc 2 6742 3 view .LVU1415
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4686              		.loc 2 6742 12 is_stmt 0 view .LVU1416
+ 4687 0040 9A68     		ldr	r2, [r3, #8]
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4688              		.loc 2 6742 70 view .LVU1417
+ 4689 0042 12F0020F 		tst	r2, #2
+ 4690 0046 07D1     		bne	.L306
+ 4691              	.LVL392:
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4692              		.loc 2 6742 70 view .LVU1418
+ 4693              	.LBE557:
+ 4694              	.LBE556:
+3354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 4695              		.loc 1 3354 11 is_stmt 1 view .LVU1419
+ 4696              	.LBB558:
+ 4697              	.LBI558:
+6835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4698              		.loc 2 6835 22 view .LVU1420
+ 4699              	.LBB559:
+6840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 4700              		.loc 2 6840 3 view .LVU1421
+ 4701 0048 9A68     		ldr	r2, [r3, #8]
+ 4702 004a 22F00042 		bic	r2, r2, #-2147483648
+ 4703 004e 22F03F02 		bic	r2, r2, #63
+ 4704 0052 42F01002 		orr	r2, r2, #16
+ 4705 0056 9A60     		str	r2, [r3, #8]
+ 4706              	.LVL393:
+ 4707              	.L306:
+6840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 4708              		.loc 2 6840 3 is_stmt 0 view .LVU1422
+ 4709              	.LBE559:
+ 4710              	.LBE558:
+3360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4711              		.loc 1 3360 5 is_stmt 1 view .LVU1423
+3360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4712              		.loc 1 3360 8 is_stmt 0 view .LVU1424
+ 4713 0058 0129     		cmp	r1, #1
+ 4714 005a 47D0     		beq	.L313
+ 4715              	.L305:
+3363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4716              		.loc 1 3363 7 is_stmt 1 view .LVU1425
+3363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ARM GAS  /tmp/ccICigVb.s 			page 327
+
+
+ 4717              		.loc 1 3363 11 is_stmt 0 view .LVU1426
+ 4718 005c 2368     		ldr	r3, [r4]
+ 4719              	.LVL394:
+ 4720              	.LBB560:
+ 4721              	.LBI560:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4722              		.loc 2 7076 26 is_stmt 1 view .LVU1427
+ 4723              	.LBB561:
+7078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4724              		.loc 2 7078 3 view .LVU1428
+7078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4725              		.loc 2 7078 12 is_stmt 0 view .LVU1429
+ 4726 005e 9A68     		ldr	r2, [r3, #8]
+7078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4727              		.loc 2 7078 76 view .LVU1430
+ 4728 0060 12F0080F 		tst	r2, #8
+ 4729 0064 0BD0     		beq	.L308
+ 4730              	.LVL395:
+7078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4731              		.loc 2 7078 76 view .LVU1431
+ 4732              	.LBE561:
+ 4733              	.LBE560:
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 4734              		.loc 1 3365 9 is_stmt 1 view .LVU1432
+ 4735              	.LBB562:
+ 4736              	.LBI562:
+6740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4737              		.loc 2 6740 26 view .LVU1433
+ 4738              	.LBB563:
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4739              		.loc 2 6742 3 view .LVU1434
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4740              		.loc 2 6742 12 is_stmt 0 view .LVU1435
+ 4741 0066 9A68     		ldr	r2, [r3, #8]
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4742              		.loc 2 6742 70 view .LVU1436
+ 4743 0068 12F0020F 		tst	r2, #2
+ 4744 006c 07D1     		bne	.L308
+ 4745              	.LVL396:
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4746              		.loc 2 6742 70 view .LVU1437
+ 4747              	.LBE563:
+ 4748              	.LBE562:
+3368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 4749              		.loc 1 3368 11 is_stmt 1 view .LVU1438
+ 4750              	.LBB564:
+ 4751              	.LBI564:
+7060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4752              		.loc 2 7060 22 view .LVU1439
+ 4753              	.LBB565:
+7065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 4754              		.loc 2 7065 3 view .LVU1440
+ 4755 006e 9A68     		ldr	r2, [r3, #8]
+ 4756 0070 22F00042 		bic	r2, r2, #-2147483648
+ 4757 0074 22F03F02 		bic	r2, r2, #63
+ 4758 0078 42F02002 		orr	r2, r2, #32
+ 4759 007c 9A60     		str	r2, [r3, #8]
+ARM GAS  /tmp/ccICigVb.s 			page 328
+
+
+ 4760              	.LVL397:
+ 4761              	.L308:
+7065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 4762              		.loc 2 7065 3 is_stmt 0 view .LVU1441
+ 4763              	.LBE565:
+ 4764              	.LBE564:
+3374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4765              		.loc 1 3374 5 is_stmt 1 view .LVU1442
+ 4766 007e 0229     		cmp	r1, #2
+ 4767 0080 36D0     		beq	.L314
+ 4768 0082 0329     		cmp	r1, #3
+ 4769 0084 36D1     		bne	.L315
+ 4770 0086 0C25     		movs	r5, #12
+ 4771              	.L307:
+ 4772              	.LVL398:
+3389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4773              		.loc 1 3389 5 view .LVU1443
+3389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4774              		.loc 1 3389 17 is_stmt 0 view .LVU1444
+ 4775 0088 FFF7FEFF 		bl	HAL_GetTick
+ 4776              	.LVL399:
+ 4777 008c 0646     		mov	r6, r0
+ 4778              	.LVL400:
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4779              		.loc 1 3391 5 is_stmt 1 view .LVU1445
+ 4780              	.L309:
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4781              		.loc 1 3391 63 view .LVU1446
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4782              		.loc 1 3391 17 is_stmt 0 view .LVU1447
+ 4783 008e 2368     		ldr	r3, [r4]
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4784              		.loc 1 3391 27 view .LVU1448
+ 4785 0090 9B68     		ldr	r3, [r3, #8]
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4786              		.loc 1 3391 63 view .LVU1449
+ 4787 0092 2B42     		tst	r3, r5
+ 4788 0094 30D0     		beq	.L318
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4789              		.loc 1 3393 7 is_stmt 1 view .LVU1450
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4790              		.loc 1 3393 12 is_stmt 0 view .LVU1451
+ 4791 0096 FFF7FEFF 		bl	HAL_GetTick
+ 4792              	.LVL401:
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4793              		.loc 1 3393 26 view .LVU1452
+ 4794 009a 801B     		subs	r0, r0, r6
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4795              		.loc 1 3393 10 view .LVU1453
+ 4796 009c 0528     		cmp	r0, #5
+ 4797 009e F6D9     		bls	.L309
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 4798              		.loc 1 3396 9 is_stmt 1 view .LVU1454
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 4799              		.loc 1 3396 18 is_stmt 0 view .LVU1455
+ 4800 00a0 2368     		ldr	r3, [r4]
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ARM GAS  /tmp/ccICigVb.s 			page 329
+
+
+ 4801              		.loc 1 3396 28 view .LVU1456
+ 4802 00a2 9B68     		ldr	r3, [r3, #8]
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 4803              		.loc 1 3396 12 view .LVU1457
+ 4804 00a4 2B42     		tst	r3, r5
+ 4805 00a6 F2D0     		beq	.L309
+3399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4806              		.loc 1 3399 11 is_stmt 1 view .LVU1458
+ 4807 00a8 E36D     		ldr	r3, [r4, #92]
+ 4808 00aa 43F01003 		orr	r3, r3, #16
+ 4809 00ae E365     		str	r3, [r4, #92]
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4810              		.loc 1 3402 11 view .LVU1459
+ 4811 00b0 236E     		ldr	r3, [r4, #96]
+ 4812 00b2 43F00103 		orr	r3, r3, #1
+ 4813 00b6 2366     		str	r3, [r4, #96]
+3404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 4814              		.loc 1 3404 11 view .LVU1460
+3404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 4815              		.loc 1 3404 18 is_stmt 0 view .LVU1461
+ 4816 00b8 0120     		movs	r0, #1
+ 4817 00ba 1EE0     		b	.L299
+ 4818              	.LVL402:
+ 4819              	.L320:
+3331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4820              		.loc 1 3331 11 is_stmt 1 view .LVU1462
+ 4821 00bc E36D     		ldr	r3, [r4, #92]
+ 4822 00be 43F01003 		orr	r3, r3, #16
+ 4823 00c2 E365     		str	r3, [r4, #92]
+3334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4824              		.loc 1 3334 11 view .LVU1463
+ 4825 00c4 236E     		ldr	r3, [r4, #96]
+ 4826 00c6 43F00103 		orr	r3, r3, #1
+ 4827 00ca 2366     		str	r3, [r4, #96]
+3336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 4828              		.loc 1 3336 11 view .LVU1464
+3336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 4829              		.loc 1 3336 18 is_stmt 0 view .LVU1465
+ 4830 00cc 0120     		movs	r0, #1
+ 4831 00ce 14E0     		b	.L299
+ 4832              	.LVL403:
+ 4833              	.L317:
+3293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t conversion_group_reassigned = ConversionGroup;
+ 4834              		.loc 1 3293 12 view .LVU1466
+ 4835 00d0 0022     		movs	r2, #0
+ 4836              	.LVL404:
+ 4837              	.L301:
+3326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4838              		.loc 1 3326 54 is_stmt 1 view .LVU1467
+3326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4839              		.loc 1 3326 14 is_stmt 0 view .LVU1468
+ 4840 00d2 1968     		ldr	r1, [r3]
+3326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4841              		.loc 1 3326 54 view .LVU1469
+ 4842 00d4 11F0400F 		tst	r1, #64
+ 4843 00d8 04D1     		bne	.L319
+3328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ARM GAS  /tmp/ccICigVb.s 			page 330
+
+
+ 4844              		.loc 1 3328 9 is_stmt 1 view .LVU1470
+3328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 4845              		.loc 1 3328 12 is_stmt 0 view .LVU1471
+ 4846 00da 0949     		ldr	r1, .L321
+ 4847 00dc 8A42     		cmp	r2, r1
+ 4848 00de EDD8     		bhi	.L320
+3338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 4849              		.loc 1 3338 9 is_stmt 1 view .LVU1472
+3338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 4850              		.loc 1 3338 39 is_stmt 0 view .LVU1473
+ 4851 00e0 0132     		adds	r2, r2, #1
+ 4852              	.LVL405:
+3338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 4853              		.loc 1 3338 39 view .LVU1474
+ 4854 00e2 F6E7     		b	.L301
+ 4855              	.L319:
+3342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 4856              		.loc 1 3342 7 is_stmt 1 view .LVU1475
+ 4857 00e4 4022     		movs	r2, #64
+ 4858              	.LVL406:
+3342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 4859              		.loc 1 3342 7 is_stmt 0 view .LVU1476
+ 4860 00e6 1A60     		str	r2, [r3]
+ 4861              	.LVL407:
+3346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4862              		.loc 1 3346 5 is_stmt 1 view .LVU1477
+3323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4863              		.loc 1 3323 35 is_stmt 0 view .LVU1478
+ 4864 00e8 0121     		movs	r1, #1
+ 4865 00ea A4E7     		b	.L304
+ 4866              	.LVL408:
+ 4867              	.L313:
+3384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+ 4868              		.loc 1 3384 37 view .LVU1479
+ 4869 00ec 0425     		movs	r5, #4
+ 4870 00ee CBE7     		b	.L307
+ 4871              	.L314:
+3380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+ 4872              		.loc 1 3380 37 view .LVU1480
+ 4873 00f0 0825     		movs	r5, #8
+ 4874 00f2 C9E7     		b	.L307
+ 4875              	.L315:
+3384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         break;
+ 4876              		.loc 1 3384 37 view .LVU1481
+ 4877 00f4 0425     		movs	r5, #4
+ 4878 00f6 C7E7     		b	.L307
+ 4879              	.LVL409:
+ 4880              	.L318:
+3412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 4881              		.loc 1 3412 10 view .LVU1482
+ 4882 00f8 0020     		movs	r0, #0
+ 4883              	.LVL410:
+ 4884              	.L299:
+3413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4885              		.loc 1 3413 1 view .LVU1483
+ 4886 00fa 70BD     		pop	{r4, r5, r6, pc}
+ 4887              	.LVL411:
+ARM GAS  /tmp/ccICigVb.s 			page 331
+
+
+ 4888              	.L311:
+3412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 4889              		.loc 1 3412 10 view .LVU1484
+ 4890 00fc 0020     		movs	r0, #0
+ 4891              	.LVL412:
+3412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 4892              		.loc 1 3412 10 view .LVU1485
+ 4893 00fe FCE7     		b	.L299
+ 4894              	.L322:
+ 4895              		.align	2
+ 4896              	.L321:
+ 4897 0100 FFFF3FA3 		.word	-1556086785
+ 4898              		.cfi_endproc
+ 4899              	.LFE353:
+ 4901              		.section	.text.ADC_Enable,"ax",%progbits
+ 4902              		.align	1
+ 4903              		.global	ADC_Enable
+ 4904              		.syntax unified
+ 4905              		.thumb
+ 4906              		.thumb_func
+ 4908              	ADC_Enable:
+ 4909              	.LVL413:
+ 4910              	.LFB354:
+3423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tickstart;
+ 4911              		.loc 1 3423 1 is_stmt 1 view -0
+ 4912              		.cfi_startproc
+ 4913              		@ args = 0, pretend = 0, frame = 0
+ 4914              		@ frame_needed = 0, uses_anonymous_args = 0
+3423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tickstart;
+ 4915              		.loc 1 3423 1 is_stmt 0 view .LVU1487
+ 4916 0000 38B5     		push	{r3, r4, r5, lr}
+ 4917              	.LCFI21:
+ 4918              		.cfi_def_cfa_offset 16
+ 4919              		.cfi_offset 3, -16
+ 4920              		.cfi_offset 4, -12
+ 4921              		.cfi_offset 5, -8
+ 4922              		.cfi_offset 14, -4
+3424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4923              		.loc 1 3424 3 is_stmt 1 view .LVU1488
+3430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 4924              		.loc 1 3430 3 view .LVU1489
+3430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 4925              		.loc 1 3430 7 is_stmt 0 view .LVU1490
+ 4926 0002 0368     		ldr	r3, [r0]
+ 4927              	.LVL414:
+ 4928              	.LBB566:
+ 4929              	.LBI566:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4930              		.loc 2 6729 26 is_stmt 1 view .LVU1491
+ 4931              	.LBB567:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4932              		.loc 2 6731 3 view .LVU1492
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4933              		.loc 2 6731 12 is_stmt 0 view .LVU1493
+ 4934 0004 9A68     		ldr	r2, [r3, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4935              		.loc 2 6731 68 view .LVU1494
+ARM GAS  /tmp/ccICigVb.s 			page 332
+
+
+ 4936 0006 12F0010F 		tst	r2, #1
+ 4937 000a 40D1     		bne	.L329
+ 4938 000c 0446     		mov	r4, r0
+ 4939              	.LVL415:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4940              		.loc 2 6731 68 view .LVU1495
+ 4941              	.LBE567:
+ 4942              	.LBE566:
+3433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+ 4943              		.loc 1 3433 5 is_stmt 1 view .LVU1496
+3433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+ 4944              		.loc 1 3433 24 is_stmt 0 view .LVU1497
+ 4945 000e 9968     		ldr	r1, [r3, #8]
+3433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                                | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+ 4946              		.loc 1 3433 8 view .LVU1498
+ 4947 0010 204A     		ldr	r2, .L332
+ 4948 0012 1142     		tst	r1, r2
+ 4949 0014 09D0     		beq	.L325
+3437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4950              		.loc 1 3437 7 is_stmt 1 view .LVU1499
+ 4951 0016 C36D     		ldr	r3, [r0, #92]
+ 4952 0018 43F01003 		orr	r3, r3, #16
+ 4953 001c C365     		str	r3, [r0, #92]
+3440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4954              		.loc 1 3440 7 view .LVU1500
+ 4955 001e 036E     		ldr	r3, [r0, #96]
+ 4956 0020 43F00103 		orr	r3, r3, #1
+ 4957 0024 0366     		str	r3, [r0, #96]
+3442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 4958              		.loc 1 3442 7 view .LVU1501
+3442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 4959              		.loc 1 3442 14 is_stmt 0 view .LVU1502
+ 4960 0026 0120     		movs	r0, #1
+ 4961              	.LVL416:
+3442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 4962              		.loc 1 3442 14 view .LVU1503
+ 4963 0028 32E0     		b	.L324
+ 4964              	.LVL417:
+ 4965              	.L325:
+3446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4966              		.loc 1 3446 5 is_stmt 1 view .LVU1504
+ 4967              	.LBB568:
+ 4968              	.LBI568:
+6690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4969              		.loc 2 6690 22 view .LVU1505
+ 4970              	.LBB569:
+6695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 4971              		.loc 2 6695 3 view .LVU1506
+ 4972 002a 9A68     		ldr	r2, [r3, #8]
+ 4973 002c 22F00042 		bic	r2, r2, #-2147483648
+ 4974 0030 22F03F02 		bic	r2, r2, #63
+ 4975 0034 42F00102 		orr	r2, r2, #1
+ 4976 0038 9A60     		str	r2, [r3, #8]
+ 4977              	.LVL418:
+6695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 4978              		.loc 2 6695 3 is_stmt 0 view .LVU1507
+ 4979              	.LBE569:
+ARM GAS  /tmp/ccICigVb.s 			page 333
+
+
+ 4980              	.LBE568:
+3449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4981              		.loc 1 3449 5 is_stmt 1 view .LVU1508
+3449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4982              		.loc 1 3449 17 is_stmt 0 view .LVU1509
+ 4983 003a FFF7FEFF 		bl	HAL_GetTick
+ 4984              	.LVL419:
+3449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 4985              		.loc 1 3449 17 view .LVU1510
+ 4986 003e 0546     		mov	r5, r0
+ 4987              	.LVL420:
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4988              		.loc 1 3451 5 is_stmt 1 view .LVU1511
+ 4989              	.L326:
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4990              		.loc 1 3451 51 view .LVU1512
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4991              		.loc 1 3451 12 is_stmt 0 view .LVU1513
+ 4992 0040 2368     		ldr	r3, [r4]
+ 4993 0042 1A68     		ldr	r2, [r3]
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 4994              		.loc 1 3451 51 view .LVU1514
+ 4995 0044 12F0010F 		tst	r2, #1
+ 4996 0048 1FD1     		bne	.L331
+3461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 4997              		.loc 1 3461 7 is_stmt 1 view .LVU1515
+ 4998              	.LVL421:
+ 4999              	.LBB570:
+ 5000              	.LBI570:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5001              		.loc 2 6729 26 view .LVU1516
+ 5002              	.LBB571:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5003              		.loc 2 6731 3 view .LVU1517
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5004              		.loc 2 6731 12 is_stmt 0 view .LVU1518
+ 5005 004a 9A68     		ldr	r2, [r3, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5006              		.loc 2 6731 68 view .LVU1519
+ 5007 004c 12F0010F 		tst	r2, #1
+ 5008 0050 07D1     		bne	.L327
+ 5009              	.LVL422:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5010              		.loc 2 6731 68 view .LVU1520
+ 5011              	.LBE571:
+ 5012              	.LBE570:
+3463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5013              		.loc 1 3463 9 is_stmt 1 view .LVU1521
+ 5014              	.LBB572:
+ 5015              	.LBI572:
+6690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5016              		.loc 2 6690 22 view .LVU1522
+ 5017              	.LBB573:
+6695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 5018              		.loc 2 6695 3 view .LVU1523
+ 5019 0052 9A68     		ldr	r2, [r3, #8]
+ 5020 0054 22F00042 		bic	r2, r2, #-2147483648
+ARM GAS  /tmp/ccICigVb.s 			page 334
+
+
+ 5021 0058 22F03F02 		bic	r2, r2, #63
+ 5022 005c 42F00102 		orr	r2, r2, #1
+ 5023 0060 9A60     		str	r2, [r3, #8]
+ 5024              	.LVL423:
+ 5025              	.L327:
+6695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 5026              		.loc 2 6695 3 is_stmt 0 view .LVU1524
+ 5027              	.LBE573:
+ 5028              	.LBE572:
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5029              		.loc 1 3466 7 is_stmt 1 view .LVU1525
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5030              		.loc 1 3466 12 is_stmt 0 view .LVU1526
+ 5031 0062 FFF7FEFF 		bl	HAL_GetTick
+ 5032              	.LVL424:
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5033              		.loc 1 3466 26 view .LVU1527
+ 5034 0066 431B     		subs	r3, r0, r5
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5035              		.loc 1 3466 10 view .LVU1528
+ 5036 0068 022B     		cmp	r3, #2
+ 5037 006a E9D9     		bls	.L326
+3469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5038              		.loc 1 3469 9 is_stmt 1 view .LVU1529
+3469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5039              		.loc 1 3469 13 is_stmt 0 view .LVU1530
+ 5040 006c 2368     		ldr	r3, [r4]
+ 5041 006e 1B68     		ldr	r3, [r3]
+3469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5042              		.loc 1 3469 12 view .LVU1531
+ 5043 0070 13F0010F 		tst	r3, #1
+ 5044 0074 E4D1     		bne	.L326
+3472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5045              		.loc 1 3472 11 is_stmt 1 view .LVU1532
+ 5046 0076 E36D     		ldr	r3, [r4, #92]
+ 5047 0078 43F01003 		orr	r3, r3, #16
+ 5048 007c E365     		str	r3, [r4, #92]
+3475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5049              		.loc 1 3475 11 view .LVU1533
+ 5050 007e 236E     		ldr	r3, [r4, #96]
+ 5051 0080 43F00103 		orr	r3, r3, #1
+ 5052 0084 2366     		str	r3, [r4, #96]
+3477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 5053              		.loc 1 3477 11 view .LVU1534
+3477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 5054              		.loc 1 3477 18 is_stmt 0 view .LVU1535
+ 5055 0086 0120     		movs	r0, #1
+ 5056 0088 02E0     		b	.L324
+ 5057              	.L331:
+3484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 5058              		.loc 1 3484 10 view .LVU1536
+ 5059 008a 0020     		movs	r0, #0
+ 5060 008c 00E0     		b	.L324
+ 5061              	.LVL425:
+ 5062              	.L329:
+3484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 5063              		.loc 1 3484 10 view .LVU1537
+ARM GAS  /tmp/ccICigVb.s 			page 335
+
+
+ 5064 008e 0020     		movs	r0, #0
+ 5065              	.LVL426:
+ 5066              	.L324:
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5067              		.loc 1 3485 1 view .LVU1538
+ 5068 0090 38BD     		pop	{r3, r4, r5, pc}
+ 5069              	.L333:
+ 5070 0092 00BF     		.align	2
+ 5071              	.L332:
+ 5072 0094 3F000080 		.word	-2147483585
+ 5073              		.cfi_endproc
+ 5074              	.LFE354:
+ 5076              		.section	.text.HAL_ADC_Start,"ax",%progbits
+ 5077              		.align	1
+ 5078              		.global	HAL_ADC_Start
+ 5079              		.syntax unified
+ 5080              		.thumb
+ 5081              		.thumb_func
+ 5083              	HAL_ADC_Start:
+ 5084              	.LVL427:
+ 5085              	.LFB333:
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 5086              		.loc 1 1221 1 is_stmt 1 view -0
+ 5087              		.cfi_startproc
+ 5088              		@ args = 0, pretend = 0, frame = 0
+ 5089              		@ frame_needed = 0, uses_anonymous_args = 0
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 5090              		.loc 1 1221 1 is_stmt 0 view .LVU1540
+ 5091 0000 38B5     		push	{r3, r4, r5, lr}
+ 5092              	.LCFI22:
+ 5093              		.cfi_def_cfa_offset 16
+ 5094              		.cfi_offset 3, -16
+ 5095              		.cfi_offset 4, -12
+ 5096              		.cfi_offset 5, -8
+ 5097              		.cfi_offset 14, -4
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 5098              		.loc 1 1222 3 is_stmt 1 view .LVU1541
+1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+ 5099              		.loc 1 1224 3 view .LVU1542
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+ 5100              		.loc 1 1225 3 view .LVU1543
+ 5101              	.LVL428:
+ 5102              	.LBB574:
+ 5103              	.LBI574:
+6392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5104              		.loc 2 6392 26 view .LVU1544
+ 5105              	.LBB575:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5106              		.loc 2 6394 3 view .LVU1545
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5107              		.loc 2 6394 21 is_stmt 0 view .LVU1546
+ 5108 0002 3C4B     		ldr	r3, .L353
+ 5109 0004 9D68     		ldr	r5, [r3, #8]
+ 5110              	.LVL429:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5111              		.loc 2 6394 21 view .LVU1547
+ 5112              	.LBE575:
+ARM GAS  /tmp/ccICigVb.s 			page 336
+
+
+ 5113              	.LBE574:
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5114              		.loc 1 1229 3 is_stmt 1 view .LVU1548
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 5115              		.loc 1 1232 3 view .LVU1549
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 5116              		.loc 1 1232 7 is_stmt 0 view .LVU1550
+ 5117 0006 0368     		ldr	r3, [r0]
+ 5118              	.LVL430:
+ 5119              	.LBB576:
+ 5120              	.LBI576:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5121              		.loc 2 6851 26 is_stmt 1 view .LVU1551
+ 5122              	.LBB577:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5123              		.loc 2 6853 3 view .LVU1552
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5124              		.loc 2 6853 12 is_stmt 0 view .LVU1553
+ 5125 0008 9B68     		ldr	r3, [r3, #8]
+ 5126              	.LVL431:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5127              		.loc 2 6853 74 view .LVU1554
+ 5128 000a 13F0040F 		tst	r3, #4
+ 5129 000e 6CD1     		bne	.L346
+ 5130 0010 0446     		mov	r4, r0
+ 5131 0012 05F01F05 		and	r5, r5, #31
+ 5132              	.LVL432:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5133              		.loc 2 6853 74 view .LVU1555
+ 5134              	.LBE577:
+ 5135              	.LBE576:
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5136              		.loc 1 1235 5 is_stmt 1 view .LVU1556
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5137              		.loc 1 1235 5 view .LVU1557
+ 5138 0016 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 5139 001a 012B     		cmp	r3, #1
+ 5140 001c 67D0     		beq	.L347
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5141              		.loc 1 1235 5 discriminator 2 view .LVU1558
+ 5142 001e 0123     		movs	r3, #1
+ 5143 0020 80F85830 		strb	r3, [r0, #88]
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5144              		.loc 1 1235 5 discriminator 2 view .LVU1559
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5145              		.loc 1 1238 5 discriminator 2 view .LVU1560
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5146              		.loc 1 1238 22 is_stmt 0 discriminator 2 view .LVU1561
+ 5147 0024 FFF7FEFF 		bl	ADC_Enable
+ 5148              	.LVL433:
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5149              		.loc 1 1241 5 is_stmt 1 discriminator 2 view .LVU1562
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5150              		.loc 1 1241 8 is_stmt 0 discriminator 2 view .LVU1563
+ 5151 0028 0028     		cmp	r0, #0
+ 5152 002a 5AD1     		bne	.L336
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_A
+ARM GAS  /tmp/ccICigVb.s 			page 337
+
+
+ 5153              		.loc 1 1246 7 is_stmt 1 view .LVU1564
+ 5154 002c E36D     		ldr	r3, [r4, #92]
+ 5155 002e 23F47063 		bic	r3, r3, #3840
+ 5156 0032 23F00103 		bic	r3, r3, #1
+ 5157 0036 43F48073 		orr	r3, r3, #256
+ 5158 003a E365     		str	r3, [r4, #92]
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5159              		.loc 1 1254 7 view .LVU1565
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5160              		.loc 1 1254 12 is_stmt 0 view .LVU1566
+ 5161 003c 2368     		ldr	r3, [r4]
+ 5162 003e 2E4A     		ldr	r2, .L353+4
+ 5163 0040 9342     		cmp	r3, r2
+ 5164 0042 32D0     		beq	.L351
+ 5165 0044 1A46     		mov	r2, r3
+ 5166              	.L337:
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5167              		.loc 1 1254 10 discriminator 4 view .LVU1567
+ 5168 0046 9342     		cmp	r3, r2
+ 5169 0048 00D0     		beq	.L338
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          )
+ 5170              		.loc 1 1255 11 view .LVU1568
+ 5171 004a 1DB9     		cbnz	r5, .L339
+ 5172              	.L338:
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5173              		.loc 1 1258 9 is_stmt 1 view .LVU1569
+ 5174 004c E26D     		ldr	r2, [r4, #92]
+ 5175 004e 22F48012 		bic	r2, r2, #1048576
+ 5176 0052 E265     		str	r2, [r4, #92]
+ 5177              	.L339:
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5178              		.loc 1 1264 7 view .LVU1570
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5179              		.loc 1 1264 11 is_stmt 0 view .LVU1571
+ 5180 0054 E26D     		ldr	r2, [r4, #92]
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5181              		.loc 1 1264 10 view .LVU1572
+ 5182 0056 12F4805F 		tst	r2, #4096
+ 5183 005a 29D0     		beq	.L340
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5184              		.loc 1 1267 9 is_stmt 1 view .LVU1573
+ 5185 005c 226E     		ldr	r2, [r4, #96]
+ 5186 005e 22F00602 		bic	r2, r2, #6
+ 5187 0062 2266     		str	r2, [r4, #96]
+ 5188              	.L341:
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5189              		.loc 1 1277 7 view .LVU1574
+ 5190 0064 1C22     		movs	r2, #28
+ 5191 0066 1A60     		str	r2, [r3]
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5192              		.loc 1 1282 7 view .LVU1575
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5193              		.loc 1 1282 7 view .LVU1576
+ 5194 0068 0023     		movs	r3, #0
+ 5195 006a 84F85830 		strb	r3, [r4, #88]
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5196              		.loc 1 1282 7 view .LVU1577
+ARM GAS  /tmp/ccICigVb.s 			page 338
+
+
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5197              		.loc 1 1293 7 view .LVU1578
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5198              		.loc 1 1293 12 is_stmt 0 view .LVU1579
+ 5199 006e 2368     		ldr	r3, [r4]
+ 5200 0070 214A     		ldr	r2, .L353+4
+ 5201 0072 9342     		cmp	r3, r2
+ 5202 0074 1FD0     		beq	.L352
+ 5203 0076 1A46     		mov	r2, r3
+ 5204              	.L342:
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5205              		.loc 1 1293 10 discriminator 4 view .LVU1580
+ 5206 0078 9342     		cmp	r3, r2
+ 5207 007a 1FD0     		beq	.L343
+ 5208 007c 092D     		cmp	r5, #9
+ 5209 007e 05D8     		bhi	.L344
+ 5210 0080 40F22121 		movw	r1, #545
+ 5211 0084 E940     		lsrs	r1, r1, r5
+ 5212 0086 11F0010F 		tst	r1, #1
+ 5213 008a 17D1     		bne	.L343
+ 5214              	.L344:
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* if Master ADC JAUTO bit is set, update Slave State in setting
+ 5215              		.loc 1 1311 9 is_stmt 1 view .LVU1581
+ 5216 008c E36D     		ldr	r3, [r4, #92]
+ 5217 008e 43F48013 		orr	r3, r3, #1048576
+ 5218 0092 E365     		str	r3, [r4, #92]
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
+ 5219              		.loc 1 1314 9 view .LVU1582
+ 5220              	.LVL434:
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5221              		.loc 1 1315 9 view .LVU1583
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5222              		.loc 1 1315 13 is_stmt 0 view .LVU1584
+ 5223 0094 D368     		ldr	r3, [r2, #12]
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5224              		.loc 1 1315 12 view .LVU1585
+ 5225 0096 13F0007F 		tst	r3, #33554432
+ 5226 009a 27D0     		beq	.L335
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 5227              		.loc 1 1317 11 is_stmt 1 view .LVU1586
+ 5228 009c E36D     		ldr	r3, [r4, #92]
+ 5229 009e 23F44053 		bic	r3, r3, #12288
+ 5230 00a2 43F48053 		orr	r3, r3, #4096
+ 5231 00a6 E365     		str	r3, [r4, #92]
+ 5232 00a8 20E0     		b	.L335
+ 5233              	.LVL435:
+ 5234              	.L351:
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5235              		.loc 1 1254 12 is_stmt 0 view .LVU1587
+ 5236 00aa 4FF0A042 		mov	r2, #1342177280
+ 5237 00ae CAE7     		b	.L337
+ 5238              	.L340:
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5239              		.loc 1 1272 9 is_stmt 1 view .LVU1588
+ 5240 00b0 0022     		movs	r2, #0
+ 5241 00b2 2266     		str	r2, [r4, #96]
+ 5242 00b4 D6E7     		b	.L341
+ARM GAS  /tmp/ccICigVb.s 			page 339
+
+
+ 5243              	.L352:
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5244              		.loc 1 1293 12 is_stmt 0 view .LVU1589
+ 5245 00b6 4FF0A042 		mov	r2, #1342177280
+ 5246 00ba DDE7     		b	.L342
+ 5247              	.L343:
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5248              		.loc 1 1300 9 is_stmt 1 view .LVU1590
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5249              		.loc 1 1300 13 is_stmt 0 view .LVU1591
+ 5250 00bc DA68     		ldr	r2, [r3, #12]
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5251              		.loc 1 1300 12 view .LVU1592
+ 5252 00be 12F0007F 		tst	r2, #33554432
+ 5253 00c2 05D0     		beq	.L345
+1302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 5254              		.loc 1 1302 11 is_stmt 1 view .LVU1593
+ 5255 00c4 E26D     		ldr	r2, [r4, #92]
+ 5256 00c6 22F44052 		bic	r2, r2, #12288
+ 5257 00ca 42F48052 		orr	r2, r2, #4096
+ 5258 00ce E265     		str	r2, [r4, #92]
+ 5259              	.L345:
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5260              		.loc 1 1306 9 view .LVU1594
+ 5261              	.LVL436:
+ 5262              	.LBB578:
+ 5263              	.LBI578:
+6815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5264              		.loc 2 6815 22 view .LVU1595
+ 5265              	.LBB579:
+6820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 5266              		.loc 2 6820 3 view .LVU1596
+ 5267 00d0 9A68     		ldr	r2, [r3, #8]
+ 5268 00d2 22F00042 		bic	r2, r2, #-2147483648
+ 5269 00d6 22F03F02 		bic	r2, r2, #63
+ 5270 00da 42F00402 		orr	r2, r2, #4
+ 5271 00de 9A60     		str	r2, [r3, #8]
+6823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 5272              		.loc 2 6823 1 is_stmt 0 view .LVU1597
+ 5273 00e0 04E0     		b	.L335
+ 5274              	.LVL437:
+ 5275              	.L336:
+6823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 5276              		.loc 2 6823 1 view .LVU1598
+ 5277              	.LBE579:
+ 5278              	.LBE578:
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 5279              		.loc 1 1334 7 is_stmt 1 discriminator 1 view .LVU1599
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 5280              		.loc 1 1334 7 discriminator 1 view .LVU1600
+ 5281 00e2 0023     		movs	r3, #0
+ 5282 00e4 84F85830 		strb	r3, [r4, #88]
+ 5283 00e8 00E0     		b	.L335
+ 5284              	.LVL438:
+ 5285              	.L346:
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 5286              		.loc 1 1339 20 is_stmt 0 view .LVU1601
+ARM GAS  /tmp/ccICigVb.s 			page 340
+
+
+ 5287 00ea 0220     		movs	r0, #2
+ 5288              	.LVL439:
+ 5289              	.L335:
+1344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5290              		.loc 1 1344 1 view .LVU1602
+ 5291 00ec 38BD     		pop	{r3, r4, r5, pc}
+ 5292              	.LVL440:
+ 5293              	.L347:
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5294              		.loc 1 1235 5 view .LVU1603
+ 5295 00ee 0220     		movs	r0, #2
+ 5296              	.LVL441:
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5297              		.loc 1 1235 5 view .LVU1604
+ 5298 00f0 FCE7     		b	.L335
+ 5299              	.L354:
+ 5300 00f2 00BF     		.align	2
+ 5301              	.L353:
+ 5302 00f4 00030050 		.word	1342178048
+ 5303 00f8 00010050 		.word	1342177536
+ 5304              		.cfi_endproc
+ 5305              	.LFE333:
+ 5307              		.section	.text.HAL_ADC_Start_IT,"ax",%progbits
+ 5308              		.align	1
+ 5309              		.global	HAL_ADC_Start_IT
+ 5310              		.syntax unified
+ 5311              		.thumb
+ 5312              		.thumb_func
+ 5314              	HAL_ADC_Start_IT:
+ 5315              	.LVL442:
+ 5316              	.LFB337:
+1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 5317              		.loc 1 1742 1 is_stmt 1 view -0
+ 5318              		.cfi_startproc
+ 5319              		@ args = 0, pretend = 0, frame = 0
+ 5320              		@ frame_needed = 0, uses_anonymous_args = 0
+1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 5321              		.loc 1 1742 1 is_stmt 0 view .LVU1606
+ 5322 0000 38B5     		push	{r3, r4, r5, lr}
+ 5323              	.LCFI23:
+ 5324              		.cfi_def_cfa_offset 16
+ 5325              		.cfi_offset 3, -16
+ 5326              		.cfi_offset 4, -12
+ 5327              		.cfi_offset 5, -8
+ 5328              		.cfi_offset 14, -4
+1743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 5329              		.loc 1 1743 3 is_stmt 1 view .LVU1607
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+ 5330              		.loc 1 1745 3 view .LVU1608
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+ 5331              		.loc 1 1746 3 view .LVU1609
+ 5332              	.LVL443:
+ 5333              	.LBB580:
+ 5334              	.LBI580:
+6392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5335              		.loc 2 6392 26 view .LVU1610
+ 5336              	.LBB581:
+ARM GAS  /tmp/ccICigVb.s 			page 341
+
+
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5337              		.loc 2 6394 3 view .LVU1611
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5338              		.loc 2 6394 21 is_stmt 0 view .LVU1612
+ 5339 0002 614B     		ldr	r3, .L382
+ 5340 0004 9D68     		ldr	r5, [r3, #8]
+ 5341              	.LVL444:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5342              		.loc 2 6394 21 view .LVU1613
+ 5343              	.LBE581:
+ 5344              	.LBE580:
+1750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5345              		.loc 1 1750 3 is_stmt 1 view .LVU1614
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 5346              		.loc 1 1753 3 view .LVU1615
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 5347              		.loc 1 1753 7 is_stmt 0 view .LVU1616
+ 5348 0006 0368     		ldr	r3, [r0]
+ 5349              	.LVL445:
+ 5350              	.LBB582:
+ 5351              	.LBI582:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5352              		.loc 2 6851 26 is_stmt 1 view .LVU1617
+ 5353              	.LBB583:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5354              		.loc 2 6853 3 view .LVU1618
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5355              		.loc 2 6853 12 is_stmt 0 view .LVU1619
+ 5356 0008 9B68     		ldr	r3, [r3, #8]
+ 5357              	.LVL446:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5358              		.loc 2 6853 74 view .LVU1620
+ 5359 000a 13F0040F 		tst	r3, #4
+ 5360 000e 40F0B680 		bne	.L372
+ 5361 0012 0446     		mov	r4, r0
+ 5362 0014 05F01F05 		and	r5, r5, #31
+ 5363              	.LVL447:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5364              		.loc 2 6853 74 view .LVU1621
+ 5365              	.LBE583:
+ 5366              	.LBE582:
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5367              		.loc 1 1756 5 is_stmt 1 view .LVU1622
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5368              		.loc 1 1756 5 view .LVU1623
+ 5369 0018 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 5370 001c 012B     		cmp	r3, #1
+ 5371 001e 00F0B080 		beq	.L373
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5372              		.loc 1 1756 5 discriminator 2 view .LVU1624
+ 5373 0022 0123     		movs	r3, #1
+ 5374 0024 80F85830 		strb	r3, [r0, #88]
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5375              		.loc 1 1756 5 discriminator 2 view .LVU1625
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5376              		.loc 1 1759 5 discriminator 2 view .LVU1626
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ARM GAS  /tmp/ccICigVb.s 			page 342
+
+
+ 5377              		.loc 1 1759 22 is_stmt 0 discriminator 2 view .LVU1627
+ 5378 0028 FFF7FEFF 		bl	ADC_Enable
+ 5379              	.LVL448:
+1762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5380              		.loc 1 1762 5 is_stmt 1 discriminator 2 view .LVU1628
+1762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5381              		.loc 1 1762 8 is_stmt 0 discriminator 2 view .LVU1629
+ 5382 002c 0028     		cmp	r0, #0
+ 5383 002e 40F0A280 		bne	.L357
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_A
+ 5384              		.loc 1 1767 7 is_stmt 1 view .LVU1630
+ 5385 0032 E36D     		ldr	r3, [r4, #92]
+ 5386 0034 23F47063 		bic	r3, r3, #3840
+ 5387 0038 23F00103 		bic	r3, r3, #1
+ 5388 003c 43F48073 		orr	r3, r3, #256
+ 5389 0040 E365     		str	r3, [r4, #92]
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5390              		.loc 1 1775 7 view .LVU1631
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5391              		.loc 1 1775 12 is_stmt 0 view .LVU1632
+ 5392 0042 2368     		ldr	r3, [r4]
+ 5393 0044 514A     		ldr	r2, .L382+4
+ 5394 0046 9342     		cmp	r3, r2
+ 5395 0048 52D0     		beq	.L377
+ 5396 004a 1A46     		mov	r2, r3
+ 5397              	.L358:
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5398              		.loc 1 1775 10 discriminator 4 view .LVU1633
+ 5399 004c 9342     		cmp	r3, r2
+ 5400 004e 00D0     		beq	.L359
+1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****          )
+ 5401              		.loc 1 1776 11 view .LVU1634
+ 5402 0050 1DB9     		cbnz	r5, .L360
+ 5403              	.L359:
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5404              		.loc 1 1779 9 is_stmt 1 view .LVU1635
+ 5405 0052 E26D     		ldr	r2, [r4, #92]
+ 5406 0054 22F48012 		bic	r2, r2, #1048576
+ 5407 0058 E265     		str	r2, [r4, #92]
+ 5408              	.L360:
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5409              		.loc 1 1785 7 view .LVU1636
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5410              		.loc 1 1785 16 is_stmt 0 view .LVU1637
+ 5411 005a E26D     		ldr	r2, [r4, #92]
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5412              		.loc 1 1785 10 view .LVU1638
+ 5413 005c 12F4805F 		tst	r2, #4096
+ 5414 0060 49D0     		beq	.L361
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5415              		.loc 1 1788 9 is_stmt 1 view .LVU1639
+ 5416 0062 226E     		ldr	r2, [r4, #96]
+ 5417 0064 22F00602 		bic	r2, r2, #6
+ 5418 0068 2266     		str	r2, [r4, #96]
+ 5419              	.L362:
+1798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5420              		.loc 1 1798 7 view .LVU1640
+ARM GAS  /tmp/ccICigVb.s 			page 343
+
+
+ 5421 006a 1C22     		movs	r2, #28
+ 5422 006c 1A60     		str	r2, [r3]
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5423              		.loc 1 1803 7 view .LVU1641
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5424              		.loc 1 1803 7 view .LVU1642
+ 5425 006e 0023     		movs	r3, #0
+ 5426 0070 84F85830 		strb	r3, [r4, #88]
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5427              		.loc 1 1803 7 view .LVU1643
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5428              		.loc 1 1806 7 view .LVU1644
+ 5429 0074 2268     		ldr	r2, [r4]
+ 5430 0076 5368     		ldr	r3, [r2, #4]
+ 5431 0078 23F01C03 		bic	r3, r3, #28
+ 5432 007c 5360     		str	r3, [r2, #4]
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5433              		.loc 1 1809 7 view .LVU1645
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5434              		.loc 1 1809 25 is_stmt 0 view .LVU1646
+ 5435 007e A369     		ldr	r3, [r4, #24]
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5436              		.loc 1 1809 7 view .LVU1647
+ 5437 0080 082B     		cmp	r3, #8
+ 5438 0082 3BD0     		beq	.L378
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+ 5439              		.loc 1 1816 11 is_stmt 1 view .LVU1648
+ 5440 0084 2268     		ldr	r2, [r4]
+ 5441 0086 5368     		ldr	r3, [r2, #4]
+ 5442 0088 43F00403 		orr	r3, r3, #4
+ 5443 008c 5360     		str	r3, [r2, #4]
+1817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5444              		.loc 1 1817 11 view .LVU1649
+ 5445              	.L364:
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5446              		.loc 1 1824 7 view .LVU1650
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5447              		.loc 1 1824 21 is_stmt 0 view .LVU1651
+ 5448 008e E36B     		ldr	r3, [r4, #60]
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5449              		.loc 1 1824 10 view .LVU1652
+ 5450 0090 23B9     		cbnz	r3, .L365
+1826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5451              		.loc 1 1826 9 is_stmt 1 view .LVU1653
+ 5452 0092 2268     		ldr	r2, [r4]
+ 5453 0094 5368     		ldr	r3, [r2, #4]
+ 5454 0096 43F01003 		orr	r3, r3, #16
+ 5455 009a 5360     		str	r3, [r2, #4]
+ 5456              	.L365:
+1838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5457              		.loc 1 1838 7 view .LVU1654
+1838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5458              		.loc 1 1838 12 is_stmt 0 view .LVU1655
+ 5459 009c 2368     		ldr	r3, [r4]
+ 5460 009e 3B4A     		ldr	r2, .L382+4
+ 5461 00a0 9342     		cmp	r3, r2
+ 5462 00a2 31D0     		beq	.L379
+ARM GAS  /tmp/ccICigVb.s 			page 344
+
+
+ 5463 00a4 1A46     		mov	r2, r3
+ 5464              	.L366:
+1838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5465              		.loc 1 1838 10 discriminator 4 view .LVU1656
+ 5466 00a6 9342     		cmp	r3, r2
+ 5467 00a8 31D0     		beq	.L367
+ 5468 00aa 092D     		cmp	r5, #9
+ 5469 00ac 05D8     		bhi	.L368
+ 5470 00ae 40F22121 		movw	r1, #545
+ 5471 00b2 E940     		lsrs	r1, r1, r5
+ 5472 00b4 11F0010F 		tst	r1, #1
+ 5473 00b8 29D1     		bne	.L367
+ 5474              	.L368:
+1873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* if Master ADC JAUTO bit is set, Slave injected interruptions
+ 5475              		.loc 1 1873 9 is_stmt 1 view .LVU1657
+ 5476 00ba E16D     		ldr	r1, [r4, #92]
+ 5477 00bc 41F48011 		orr	r1, r1, #1048576
+ 5478 00c0 E165     		str	r1, [r4, #92]
+1876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
+ 5479              		.loc 1 1876 9 view .LVU1658
+ 5480              	.LVL449:
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5481              		.loc 1 1877 9 view .LVU1659
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5482              		.loc 1 1877 13 is_stmt 0 view .LVU1660
+ 5483 00c2 D268     		ldr	r2, [r2, #12]
+ 5484              	.LVL450:
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5485              		.loc 1 1877 12 view .LVU1661
+ 5486 00c4 12F0007F 		tst	r2, #33554432
+ 5487 00c8 5AD0     		beq	.L356
+1881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           /* Next, set Slave injected interruptions */
+ 5488              		.loc 1 1881 11 is_stmt 1 view .LVU1662
+ 5489 00ca E26D     		ldr	r2, [r4, #92]
+ 5490 00cc 22F44052 		bic	r2, r2, #12288
+ 5491 00d0 42F48052 		orr	r2, r2, #4096
+ 5492 00d4 E265     		str	r2, [r4, #92]
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 5493              		.loc 1 1883 11 view .LVU1663
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 5494              		.loc 1 1883 29 is_stmt 0 view .LVU1664
+ 5495 00d6 A269     		ldr	r2, [r4, #24]
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 5496              		.loc 1 1883 11 view .LVU1665
+ 5497 00d8 082A     		cmp	r2, #8
+ 5498 00da 42D0     		beq	.L380
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ 5499              		.loc 1 1891 15 is_stmt 1 view .LVU1666
+ 5500 00dc 5A68     		ldr	r2, [r3, #4]
+ 5501 00de 22F04002 		bic	r2, r2, #64
+ 5502 00e2 5A60     		str	r2, [r3, #4]
+1892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               break;
+ 5503              		.loc 1 1892 15 view .LVU1667
+ 5504 00e4 2268     		ldr	r2, [r4]
+ 5505 00e6 5368     		ldr	r3, [r2, #4]
+ 5506 00e8 43F02003 		orr	r3, r3, #32
+ 5507 00ec 5360     		str	r3, [r2, #4]
+ARM GAS  /tmp/ccICigVb.s 			page 345
+
+
+1893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 5508              		.loc 1 1893 15 view .LVU1668
+ 5509 00ee 47E0     		b	.L356
+ 5510              	.LVL451:
+ 5511              	.L377:
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5512              		.loc 1 1775 12 is_stmt 0 view .LVU1669
+ 5513 00f0 4FF0A042 		mov	r2, #1342177280
+ 5514 00f4 AAE7     		b	.L358
+ 5515              	.L361:
+1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5516              		.loc 1 1793 9 is_stmt 1 view .LVU1670
+ 5517 00f6 0022     		movs	r2, #0
+ 5518 00f8 2266     		str	r2, [r4, #96]
+ 5519 00fa B6E7     		b	.L362
+ 5520              	.L378:
+1812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           break;
+ 5521              		.loc 1 1812 11 view .LVU1671
+ 5522 00fc 2268     		ldr	r2, [r4]
+ 5523 00fe 5368     		ldr	r3, [r2, #4]
+ 5524 0100 43F00803 		orr	r3, r3, #8
+ 5525 0104 5360     		str	r3, [r2, #4]
+1813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         /* case ADC_EOC_SINGLE_CONV */
+ 5526              		.loc 1 1813 11 view .LVU1672
+ 5527 0106 C2E7     		b	.L364
+ 5528              	.L379:
+1838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5529              		.loc 1 1838 12 is_stmt 0 view .LVU1673
+ 5530 0108 4FF0A042 		mov	r2, #1342177280
+ 5531 010c CBE7     		b	.L366
+ 5532              	.L367:
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5533              		.loc 1 1845 9 is_stmt 1 view .LVU1674
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5534              		.loc 1 1845 13 is_stmt 0 view .LVU1675
+ 5535 010e DA68     		ldr	r2, [r3, #12]
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5536              		.loc 1 1845 12 view .LVU1676
+ 5537 0110 12F0007F 		tst	r2, #33554432
+ 5538 0114 11D0     		beq	.L369
+1847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5539              		.loc 1 1847 11 is_stmt 1 view .LVU1677
+ 5540 0116 E26D     		ldr	r2, [r4, #92]
+ 5541 0118 22F44052 		bic	r2, r2, #12288
+ 5542 011c 42F48052 		orr	r2, r2, #4096
+ 5543 0120 E265     		str	r2, [r4, #92]
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 5544              		.loc 1 1853 11 view .LVU1678
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 5545              		.loc 1 1853 29 is_stmt 0 view .LVU1679
+ 5546 0122 A269     		ldr	r2, [r4, #24]
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           {
+ 5547              		.loc 1 1853 11 view .LVU1680
+ 5548 0124 082A     		cmp	r2, #8
+ 5549 0126 12D0     		beq	.L381
+1861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ 5550              		.loc 1 1861 15 is_stmt 1 view .LVU1681
+ARM GAS  /tmp/ccICigVb.s 			page 346
+
+
+ 5551 0128 5A68     		ldr	r2, [r3, #4]
+ 5552 012a 22F04002 		bic	r2, r2, #64
+ 5553 012e 5A60     		str	r2, [r3, #4]
+1862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               break;
+ 5554              		.loc 1 1862 15 view .LVU1682
+ 5555 0130 2268     		ldr	r2, [r4]
+ 5556 0132 5368     		ldr	r3, [r2, #4]
+ 5557 0134 43F02003 		orr	r3, r3, #32
+ 5558 0138 5360     		str	r3, [r2, #4]
+1863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****           }
+ 5559              		.loc 1 1863 15 view .LVU1683
+ 5560              	.L369:
+1868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5561              		.loc 1 1868 9 view .LVU1684
+ 5562 013a 2268     		ldr	r2, [r4]
+ 5563              	.LVL452:
+ 5564              	.LBB584:
+ 5565              	.LBI584:
+6815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5566              		.loc 2 6815 22 view .LVU1685
+ 5567              	.LBB585:
+6820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 5568              		.loc 2 6820 3 view .LVU1686
+ 5569 013c 9368     		ldr	r3, [r2, #8]
+ 5570 013e 23F00043 		bic	r3, r3, #-2147483648
+ 5571 0142 23F03F03 		bic	r3, r3, #63
+ 5572 0146 43F00403 		orr	r3, r3, #4
+ 5573 014a 9360     		str	r3, [r2, #8]
+6823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 5574              		.loc 2 6823 1 is_stmt 0 view .LVU1687
+ 5575 014c 18E0     		b	.L356
+ 5576              	.LVL453:
+ 5577              	.L381:
+6823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 5578              		.loc 2 6823 1 view .LVU1688
+ 5579              	.LBE585:
+ 5580              	.LBE584:
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ 5581              		.loc 1 1856 15 is_stmt 1 view .LVU1689
+ 5582 014e 5A68     		ldr	r2, [r3, #4]
+ 5583 0150 22F02002 		bic	r2, r2, #32
+ 5584 0154 5A60     		str	r2, [r3, #4]
+1857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               break;
+ 5585              		.loc 1 1857 15 view .LVU1690
+ 5586 0156 2268     		ldr	r2, [r4]
+ 5587 0158 5368     		ldr	r3, [r2, #4]
+ 5588 015a 43F04003 		orr	r3, r3, #64
+ 5589 015e 5360     		str	r3, [r2, #4]
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* case ADC_EOC_SINGLE_CONV */
+ 5590              		.loc 1 1858 15 view .LVU1691
+ 5591 0160 EBE7     		b	.L369
+ 5592              	.LVL454:
+ 5593              	.L380:
+1886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ 5594              		.loc 1 1886 15 view .LVU1692
+ 5595 0162 5A68     		ldr	r2, [r3, #4]
+ 5596 0164 22F02002 		bic	r2, r2, #32
+ARM GAS  /tmp/ccICigVb.s 			page 347
+
+
+ 5597 0168 5A60     		str	r2, [r3, #4]
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****               break;
+ 5598              		.loc 1 1887 15 view .LVU1693
+ 5599 016a 2268     		ldr	r2, [r4]
+ 5600 016c 5368     		ldr	r3, [r2, #4]
+ 5601 016e 43F04003 		orr	r3, r3, #64
+ 5602 0172 5360     		str	r3, [r2, #4]
+1888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             /* case ADC_EOC_SINGLE_CONV */
+ 5603              		.loc 1 1888 15 view .LVU1694
+ 5604 0174 04E0     		b	.L356
+ 5605              	.LVL455:
+ 5606              	.L357:
+1928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 5607              		.loc 1 1928 7 discriminator 1 view .LVU1695
+1928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 5608              		.loc 1 1928 7 discriminator 1 view .LVU1696
+ 5609 0176 0023     		movs	r3, #0
+ 5610 0178 84F85830 		strb	r3, [r4, #88]
+ 5611 017c 00E0     		b	.L356
+ 5612              	.LVL456:
+ 5613              	.L372:
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 5614              		.loc 1 1934 20 is_stmt 0 view .LVU1697
+ 5615 017e 0220     		movs	r0, #2
+ 5616              	.LVL457:
+ 5617              	.L356:
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5618              		.loc 1 1939 1 view .LVU1698
+ 5619 0180 38BD     		pop	{r3, r4, r5, pc}
+ 5620              	.LVL458:
+ 5621              	.L373:
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5622              		.loc 1 1756 5 view .LVU1699
+ 5623 0182 0220     		movs	r0, #2
+ 5624              	.LVL459:
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5625              		.loc 1 1756 5 view .LVU1700
+ 5626 0184 FCE7     		b	.L356
+ 5627              	.L383:
+ 5628 0186 00BF     		.align	2
+ 5629              	.L382:
+ 5630 0188 00030050 		.word	1342178048
+ 5631 018c 00010050 		.word	1342177536
+ 5632              		.cfi_endproc
+ 5633              	.LFE337:
+ 5635              		.section	.text.HAL_ADC_Start_DMA,"ax",%progbits
+ 5636              		.align	1
+ 5637              		.global	HAL_ADC_Start_DMA
+ 5638              		.syntax unified
+ 5639              		.thumb
+ 5640              		.thumb_func
+ 5642              	HAL_ADC_Start_DMA:
+ 5643              	.LVL460:
+ 5644              	.LFB339:
+2002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 5645              		.loc 1 2002 1 is_stmt 1 view -0
+ 5646              		.cfi_startproc
+ARM GAS  /tmp/ccICigVb.s 			page 348
+
+
+ 5647              		@ args = 0, pretend = 0, frame = 0
+ 5648              		@ frame_needed = 0, uses_anonymous_args = 0
+2002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 5649              		.loc 1 2002 1 is_stmt 0 view .LVU1702
+ 5650 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 5651              	.LCFI24:
+ 5652              		.cfi_def_cfa_offset 24
+ 5653              		.cfi_offset 3, -24
+ 5654              		.cfi_offset 4, -20
+ 5655              		.cfi_offset 5, -16
+ 5656              		.cfi_offset 6, -12
+ 5657              		.cfi_offset 7, -8
+ 5658              		.cfi_offset 14, -4
+ 5659 0002 0446     		mov	r4, r0
+2003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 5660              		.loc 1 2003 3 is_stmt 1 view .LVU1703
+2005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif
+ 5661              		.loc 1 2005 3 view .LVU1704
+ 5662              	.LVL461:
+ 5663              	.LBB586:
+ 5664              	.LBI586:
+6392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5665              		.loc 2 6392 26 view .LVU1705
+ 5666              	.LBB587:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5667              		.loc 2 6394 3 view .LVU1706
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5668              		.loc 2 6394 21 is_stmt 0 view .LVU1707
+ 5669 0004 3A4B     		ldr	r3, .L399
+ 5670 0006 9D68     		ldr	r5, [r3, #8]
+ 5671              	.LVL462:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5672              		.loc 2 6394 21 view .LVU1708
+ 5673              	.LBE587:
+ 5674              	.LBE586:
+2009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5675              		.loc 1 2009 3 is_stmt 1 view .LVU1709
+2012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 5676              		.loc 1 2012 3 view .LVU1710
+2012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 5677              		.loc 1 2012 7 is_stmt 0 view .LVU1711
+ 5678 0008 0068     		ldr	r0, [r0]
+ 5679              	.LVL463:
+ 5680              	.LBB588:
+ 5681              	.LBI588:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5682              		.loc 2 6851 26 is_stmt 1 view .LVU1712
+ 5683              	.LBB589:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5684              		.loc 2 6853 3 view .LVU1713
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5685              		.loc 2 6853 12 is_stmt 0 view .LVU1714
+ 5686 000a 8068     		ldr	r0, [r0, #8]
+ 5687              	.LVL464:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5688              		.loc 2 6853 74 view .LVU1715
+ 5689 000c 10F0040F 		tst	r0, #4
+ARM GAS  /tmp/ccICigVb.s 			page 349
+
+
+ 5690 0010 69D1     		bne	.L394
+ 5691 0012 0E46     		mov	r6, r1
+ 5692 0014 1746     		mov	r7, r2
+ 5693 0016 05F01F05 		and	r5, r5, #31
+ 5694              	.LVL465:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5695              		.loc 2 6853 74 view .LVU1716
+ 5696              	.LBE589:
+ 5697              	.LBE588:
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5698              		.loc 1 2015 5 is_stmt 1 view .LVU1717
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5699              		.loc 1 2015 5 view .LVU1718
+ 5700 001a 94F85830 		ldrb	r3, [r4, #88]	@ zero_extendqisi2
+ 5701 001e 012B     		cmp	r3, #1
+ 5702 0020 63D0     		beq	.L395
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5703              		.loc 1 2015 5 discriminator 2 view .LVU1719
+ 5704 0022 0123     		movs	r3, #1
+ 5705 0024 84F85830 		strb	r3, [r4, #88]
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5706              		.loc 1 2015 5 discriminator 2 view .LVU1720
+2020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5707              		.loc 1 2020 5 discriminator 2 view .LVU1721
+2020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5708              		.loc 1 2020 8 is_stmt 0 discriminator 2 view .LVU1722
+ 5709 0028 45B1     		cbz	r5, .L386
+2022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ 5710              		.loc 1 2022 9 view .LVU1723
+ 5711 002a 052D     		cmp	r5, #5
+ 5712 002c 06D0     		beq	.L386
+2023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****        )
+ 5713              		.loc 1 2023 9 view .LVU1724
+ 5714 002e 092D     		cmp	r5, #9
+ 5715 0030 04D0     		beq	.L386
+2115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Process unlocked */
+ 5716              		.loc 1 2115 7 is_stmt 1 discriminator 1 view .LVU1725
+ 5717              	.LVL466:
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 5718              		.loc 1 2117 7 discriminator 1 view .LVU1726
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 5719              		.loc 1 2117 7 discriminator 1 view .LVU1727
+ 5720 0032 0023     		movs	r3, #0
+ 5721 0034 84F85830 		strb	r3, [r4, #88]
+2115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       /* Process unlocked */
+ 5722              		.loc 1 2115 22 is_stmt 0 discriminator 1 view .LVU1728
+ 5723 0038 0120     		movs	r0, #1
+ 5724 003a 55E0     		b	.L385
+ 5725              	.LVL467:
+ 5726              	.L386:
+2028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5727              		.loc 1 2028 7 is_stmt 1 view .LVU1729
+2028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5728              		.loc 1 2028 24 is_stmt 0 view .LVU1730
+ 5729 003c 2046     		mov	r0, r4
+ 5730 003e FFF7FEFF 		bl	ADC_Enable
+ 5731              	.LVL468:
+ARM GAS  /tmp/ccICigVb.s 			page 350
+
+
+2031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5732              		.loc 1 2031 7 is_stmt 1 view .LVU1731
+2031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 5733              		.loc 1 2031 10 is_stmt 0 view .LVU1732
+ 5734 0042 0028     		cmp	r0, #0
+ 5735 0044 4BD1     		bne	.L388
+2036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                           HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL
+ 5736              		.loc 1 2036 9 is_stmt 1 view .LVU1733
+ 5737 0046 E36D     		ldr	r3, [r4, #92]
+ 5738 0048 23F47063 		bic	r3, r3, #3840
+ 5739 004c 23F00103 		bic	r3, r3, #1
+ 5740 0050 43F48073 		orr	r3, r3, #256
+ 5741 0054 E365     		str	r3, [r4, #92]
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5742              		.loc 1 2044 9 view .LVU1734
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5743              		.loc 1 2044 14 is_stmt 0 view .LVU1735
+ 5744 0056 2368     		ldr	r3, [r4]
+ 5745 0058 264A     		ldr	r2, .L399+4
+ 5746 005a 9342     		cmp	r3, r2
+ 5747 005c 39D0     		beq	.L398
+ 5748 005e 1A46     		mov	r2, r3
+ 5749              	.L389:
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5750              		.loc 1 2044 12 discriminator 4 view .LVU1736
+ 5751 0060 9342     		cmp	r3, r2
+ 5752 0062 00D0     		beq	.L390
+2045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****            )
+ 5753              		.loc 1 2045 13 view .LVU1737
+ 5754 0064 1DB9     		cbnz	r5, .L391
+ 5755              	.L390:
+2048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 5756              		.loc 1 2048 11 is_stmt 1 view .LVU1738
+ 5757 0066 E36D     		ldr	r3, [r4, #92]
+ 5758 0068 23F48013 		bic	r3, r3, #1048576
+ 5759 006c E365     		str	r3, [r4, #92]
+ 5760              	.L391:
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5761              		.loc 1 2053 9 view .LVU1739
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5762              		.loc 1 2053 18 is_stmt 0 view .LVU1740
+ 5763 006e E36D     		ldr	r3, [r4, #92]
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 5764              		.loc 1 2053 12 view .LVU1741
+ 5765 0070 13F4805F 		tst	r3, #4096
+ 5766 0074 30D0     		beq	.L392
+2056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 5767              		.loc 1 2056 11 is_stmt 1 view .LVU1742
+ 5768 0076 236E     		ldr	r3, [r4, #96]
+ 5769 0078 23F00603 		bic	r3, r3, #6
+ 5770 007c 2366     		str	r3, [r4, #96]
+ 5771              	.L393:
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5772              		.loc 1 2065 9 view .LVU1743
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5773              		.loc 1 2065 13 is_stmt 0 view .LVU1744
+ 5774 007e 636D     		ldr	r3, [r4, #84]
+ARM GAS  /tmp/ccICigVb.s 			page 351
+
+
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5775              		.loc 1 2065 44 view .LVU1745
+ 5776 0080 1D4A     		ldr	r2, .L399+8
+ 5777 0082 DA62     		str	r2, [r3, #44]
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5778              		.loc 1 2068 9 is_stmt 1 view .LVU1746
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5779              		.loc 1 2068 13 is_stmt 0 view .LVU1747
+ 5780 0084 636D     		ldr	r3, [r4, #84]
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5781              		.loc 1 2068 48 view .LVU1748
+ 5782 0086 1D4A     		ldr	r2, .L399+12
+ 5783 0088 1A63     		str	r2, [r3, #48]
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5784              		.loc 1 2071 9 is_stmt 1 view .LVU1749
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5785              		.loc 1 2071 13 is_stmt 0 view .LVU1750
+ 5786 008a 636D     		ldr	r3, [r4, #84]
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5787              		.loc 1 2071 45 view .LVU1751
+ 5788 008c 1C4A     		ldr	r2, .L399+16
+ 5789 008e 5A63     		str	r2, [r3, #52]
+2080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5790              		.loc 1 2080 9 is_stmt 1 view .LVU1752
+ 5791 0090 2368     		ldr	r3, [r4]
+ 5792 0092 1C22     		movs	r2, #28
+ 5793 0094 1A60     		str	r2, [r3]
+2085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5794              		.loc 1 2085 9 view .LVU1753
+2085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5795              		.loc 1 2085 9 view .LVU1754
+ 5796 0096 0023     		movs	r3, #0
+ 5797 0098 84F85830 		strb	r3, [r4, #88]
+2085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5798              		.loc 1 2085 9 view .LVU1755
+2090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5799              		.loc 1 2090 9 view .LVU1756
+ 5800 009c 2268     		ldr	r2, [r4]
+ 5801 009e 5368     		ldr	r3, [r2, #4]
+ 5802 00a0 43F01003 		orr	r3, r3, #16
+ 5803 00a4 5360     		str	r3, [r2, #4]
+2093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5804              		.loc 1 2093 9 view .LVU1757
+ 5805 00a6 2268     		ldr	r2, [r4]
+ 5806 00a8 D368     		ldr	r3, [r2, #12]
+ 5807 00aa 43F00103 		orr	r3, r3, #1
+ 5808 00ae D360     		str	r3, [r2, #12]
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5809              		.loc 1 2096 9 view .LVU1758
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5810              		.loc 1 2096 76 is_stmt 0 view .LVU1759
+ 5811 00b0 2168     		ldr	r1, [r4]
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5812              		.loc 1 2096 26 view .LVU1760
+ 5813 00b2 3B46     		mov	r3, r7
+ 5814 00b4 3246     		mov	r2, r6
+ 5815 00b6 4031     		adds	r1, r1, #64
+ARM GAS  /tmp/ccICigVb.s 			page 352
+
+
+ 5816 00b8 606D     		ldr	r0, [r4, #84]
+ 5817              	.LVL469:
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5818              		.loc 1 2096 26 view .LVU1761
+ 5819 00ba FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 5820              	.LVL470:
+2103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5821              		.loc 1 2103 9 is_stmt 1 view .LVU1762
+ 5822 00be 2268     		ldr	r2, [r4]
+ 5823              	.LVL471:
+ 5824              	.LBB590:
+ 5825              	.LBI590:
+6815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5826              		.loc 2 6815 22 view .LVU1763
+ 5827              	.LBB591:
+6820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 5828              		.loc 2 6820 3 view .LVU1764
+ 5829 00c0 9368     		ldr	r3, [r2, #8]
+ 5830 00c2 23F00043 		bic	r3, r3, #-2147483648
+ 5831 00c6 23F03F03 		bic	r3, r3, #63
+ 5832 00ca 43F00403 		orr	r3, r3, #4
+ 5833 00ce 9360     		str	r3, [r2, #8]
+6823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 5834              		.loc 2 6823 1 is_stmt 0 view .LVU1765
+ 5835 00d0 0AE0     		b	.L385
+ 5836              	.LVL472:
+ 5837              	.L398:
+6823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 5838              		.loc 2 6823 1 view .LVU1766
+ 5839              	.LBE591:
+ 5840              	.LBE590:
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 5841              		.loc 1 2044 14 view .LVU1767
+ 5842 00d2 4FF0A042 		mov	r2, #1342177280
+ 5843 00d6 C3E7     		b	.L389
+ 5844              	.L392:
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 5845              		.loc 1 2061 11 is_stmt 1 view .LVU1768
+ 5846 00d8 0023     		movs	r3, #0
+ 5847 00da 2366     		str	r3, [r4, #96]
+ 5848 00dc CFE7     		b	.L393
+ 5849              	.L388:
+2108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5850              		.loc 1 2108 9 view .LVU1769
+2108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 5851              		.loc 1 2108 9 view .LVU1770
+ 5852 00de 0023     		movs	r3, #0
+ 5853 00e0 84F85830 		strb	r3, [r4, #88]
+ 5854 00e4 00E0     		b	.L385
+ 5855              	.LVL473:
+ 5856              	.L394:
+2123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 5857              		.loc 1 2123 20 is_stmt 0 view .LVU1771
+ 5858 00e6 0220     		movs	r0, #2
+ 5859              	.LVL474:
+ 5860              	.L385:
+2128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ARM GAS  /tmp/ccICigVb.s 			page 353
+
+
+ 5861              		.loc 1 2128 1 view .LVU1772
+ 5862 00e8 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 5863              	.LVL475:
+ 5864              	.L395:
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5865              		.loc 1 2015 5 view .LVU1773
+ 5866 00ea 0220     		movs	r0, #2
+ 5867 00ec FCE7     		b	.L385
+ 5868              	.L400:
+ 5869 00ee 00BF     		.align	2
+ 5870              	.L399:
+ 5871 00f0 00030050 		.word	1342178048
+ 5872 00f4 00010050 		.word	1342177536
+ 5873 00f8 00000000 		.word	ADC_DMAConvCplt
+ 5874 00fc 00000000 		.word	ADC_DMAHalfConvCplt
+ 5875 0100 00000000 		.word	ADC_DMAError
+ 5876              		.cfi_endproc
+ 5877              	.LFE339:
+ 5879              		.section	.text.ADC_Disable,"ax",%progbits
+ 5880              		.align	1
+ 5881              		.global	ADC_Disable
+ 5882              		.syntax unified
+ 5883              		.thumb
+ 5884              		.thumb_func
+ 5886              	ADC_Disable:
+ 5887              	.LVL476:
+ 5888              	.LFB355:
+3495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tickstart;
+ 5889              		.loc 1 3495 1 is_stmt 1 view -0
+ 5890              		.cfi_startproc
+ 5891              		@ args = 0, pretend = 0, frame = 0
+ 5892              		@ frame_needed = 0, uses_anonymous_args = 0
+3495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   uint32_t tickstart;
+ 5893              		.loc 1 3495 1 is_stmt 0 view .LVU1775
+ 5894 0000 38B5     		push	{r3, r4, r5, lr}
+ 5895              	.LCFI25:
+ 5896              		.cfi_def_cfa_offset 16
+ 5897              		.cfi_offset 3, -16
+ 5898              		.cfi_offset 4, -12
+ 5899              		.cfi_offset 5, -8
+ 5900              		.cfi_offset 14, -4
+ 5901 0002 0446     		mov	r4, r0
+3496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
+ 5902              		.loc 1 3496 3 is_stmt 1 view .LVU1776
+3497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5903              		.loc 1 3497 3 view .LVU1777
+3497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5904              		.loc 1 3497 48 is_stmt 0 view .LVU1778
+ 5905 0004 0268     		ldr	r2, [r0]
+ 5906              	.LVL477:
+ 5907              	.LBB592:
+ 5908              	.LBI592:
+6740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5909              		.loc 2 6740 26 is_stmt 1 view .LVU1779
+ 5910              	.LBB593:
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5911              		.loc 2 6742 3 view .LVU1780
+ARM GAS  /tmp/ccICigVb.s 			page 354
+
+
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5912              		.loc 2 6742 12 is_stmt 0 view .LVU1781
+ 5913 0006 9368     		ldr	r3, [r2, #8]
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5914              		.loc 2 6742 70 view .LVU1782
+ 5915 0008 13F00203 		ands	r3, r3, #2
+ 5916 000c 00D0     		beq	.L402
+ 5917 000e 0123     		movs	r3, #1
+ 5918              	.L402:
+ 5919              	.LVL478:
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5920              		.loc 2 6742 70 view .LVU1783
+ 5921              	.LBE593:
+ 5922              	.LBE592:
+3502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       && (tmp_adc_is_disable_on_going == 0UL)
+ 5923              		.loc 1 3502 3 is_stmt 1 view .LVU1784
+ 5924              	.LBB594:
+ 5925              	.LBI594:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5926              		.loc 2 6729 26 view .LVU1785
+ 5927              	.LBB595:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5928              		.loc 2 6731 3 view .LVU1786
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5929              		.loc 2 6731 12 is_stmt 0 view .LVU1787
+ 5930 0010 9168     		ldr	r1, [r2, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5931              		.loc 2 6731 68 view .LVU1788
+ 5932 0012 11F0010F 		tst	r1, #1
+ 5933 0016 39D0     		beq	.L407
+ 5934              	.LVL479:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5935              		.loc 2 6731 68 view .LVU1789
+ 5936              	.LBE595:
+ 5937              	.LBE594:
+3503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****      )
+ 5938              		.loc 1 3503 7 view .LVU1790
+ 5939 0018 002B     		cmp	r3, #0
+ 5940 001a 39D1     		bne	.L408
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5941              		.loc 1 3507 5 is_stmt 1 view .LVU1791
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5942              		.loc 1 3507 24 is_stmt 0 view .LVU1792
+ 5943 001c 9368     		ldr	r3, [r2, #8]
+ 5944              	.LVL480:
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5945              		.loc 1 3507 29 view .LVU1793
+ 5946 001e 03F00D03 		and	r3, r3, #13
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5947              		.loc 1 3507 8 view .LVU1794
+ 5948 0022 012B     		cmp	r3, #1
+ 5949 0024 09D0     		beq	.L410
+3516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5950              		.loc 1 3516 7 is_stmt 1 view .LVU1795
+ 5951 0026 E36D     		ldr	r3, [r4, #92]
+ 5952 0028 43F01003 		orr	r3, r3, #16
+ 5953 002c E365     		str	r3, [r4, #92]
+ARM GAS  /tmp/ccICigVb.s 			page 355
+
+
+3519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5954              		.loc 1 3519 7 view .LVU1796
+ 5955 002e 236E     		ldr	r3, [r4, #96]
+ 5956 0030 43F00103 		orr	r3, r3, #1
+ 5957 0034 2366     		str	r3, [r4, #96]
+3521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 5958              		.loc 1 3521 7 view .LVU1797
+3521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 5959              		.loc 1 3521 14 is_stmt 0 view .LVU1798
+ 5960 0036 0120     		movs	r0, #1
+ 5961              	.LVL481:
+3521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 5962              		.loc 1 3521 14 view .LVU1799
+ 5963 0038 29E0     		b	.L403
+ 5964              	.LVL482:
+ 5965              	.L410:
+3510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+ 5966              		.loc 1 3510 7 is_stmt 1 view .LVU1800
+ 5967              	.LBB596:
+ 5968              	.LBI596:
+6710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5969              		.loc 2 6710 22 view .LVU1801
+ 5970              	.LBB597:
+6715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 5971              		.loc 2 6715 3 view .LVU1802
+ 5972 003a 9368     		ldr	r3, [r2, #8]
+ 5973 003c 23F00043 		bic	r3, r3, #-2147483648
+ 5974 0040 23F03F03 		bic	r3, r3, #63
+ 5975 0044 43F00203 		orr	r3, r3, #2
+ 5976 0048 9360     		str	r3, [r2, #8]
+ 5977              	.LVL483:
+6715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 5978              		.loc 2 6715 3 is_stmt 0 view .LVU1803
+ 5979              	.LBE597:
+ 5980              	.LBE596:
+3511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 5981              		.loc 1 3511 7 is_stmt 1 view .LVU1804
+ 5982 004a 2368     		ldr	r3, [r4]
+ 5983 004c 0322     		movs	r2, #3
+ 5984 004e 1A60     		str	r2, [r3]
+3526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5985              		.loc 1 3526 5 view .LVU1805
+3526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5986              		.loc 1 3526 17 is_stmt 0 view .LVU1806
+ 5987 0050 FFF7FEFF 		bl	HAL_GetTick
+ 5988              	.LVL484:
+3526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 5989              		.loc 1 3526 17 view .LVU1807
+ 5990 0054 0546     		mov	r5, r0
+ 5991              	.LVL485:
+3528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5992              		.loc 1 3528 5 is_stmt 1 view .LVU1808
+ 5993              	.L405:
+3528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5994              		.loc 1 3528 47 view .LVU1809
+3528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5995              		.loc 1 3528 17 is_stmt 0 view .LVU1810
+ARM GAS  /tmp/ccICigVb.s 			page 356
+
+
+ 5996 0056 2368     		ldr	r3, [r4]
+3528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5997              		.loc 1 3528 27 view .LVU1811
+ 5998 0058 9B68     		ldr	r3, [r3, #8]
+3528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 5999              		.loc 1 3528 47 view .LVU1812
+ 6000 005a 13F0010F 		tst	r3, #1
+ 6001 005e 13D0     		beq	.L411
+3530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 6002              		.loc 1 3530 7 is_stmt 1 view .LVU1813
+3530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 6003              		.loc 1 3530 12 is_stmt 0 view .LVU1814
+ 6004 0060 FFF7FEFF 		bl	HAL_GetTick
+ 6005              	.LVL486:
+3530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 6006              		.loc 1 3530 26 view .LVU1815
+ 6007 0064 401B     		subs	r0, r0, r5
+3530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 6008              		.loc 1 3530 10 view .LVU1816
+ 6009 0066 0228     		cmp	r0, #2
+ 6010 0068 F5D9     		bls	.L405
+3533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 6011              		.loc 1 3533 9 is_stmt 1 view .LVU1817
+3533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 6012              		.loc 1 3533 18 is_stmt 0 view .LVU1818
+ 6013 006a 2368     		ldr	r3, [r4]
+3533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 6014              		.loc 1 3533 28 view .LVU1819
+ 6015 006c 9B68     		ldr	r3, [r3, #8]
+3533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         {
+ 6016              		.loc 1 3533 12 view .LVU1820
+ 6017 006e 13F0010F 		tst	r3, #1
+ 6018 0072 F0D0     		beq	.L405
+3536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6019              		.loc 1 3536 11 is_stmt 1 view .LVU1821
+ 6020 0074 E36D     		ldr	r3, [r4, #92]
+ 6021 0076 43F01003 		orr	r3, r3, #16
+ 6022 007a E365     		str	r3, [r4, #92]
+3539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6023              		.loc 1 3539 11 view .LVU1822
+ 6024 007c 236E     		ldr	r3, [r4, #96]
+ 6025 007e 43F00103 		orr	r3, r3, #1
+ 6026 0082 2366     		str	r3, [r4, #96]
+3541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 6027              		.loc 1 3541 11 view .LVU1823
+3541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****         }
+ 6028              		.loc 1 3541 18 is_stmt 0 view .LVU1824
+ 6029 0084 0120     		movs	r0, #1
+ 6030 0086 02E0     		b	.L403
+ 6031              	.L411:
+3548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 6032              		.loc 1 3548 10 view .LVU1825
+ 6033 0088 0020     		movs	r0, #0
+ 6034 008a 00E0     		b	.L403
+ 6035              	.LVL487:
+ 6036              	.L407:
+3548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ARM GAS  /tmp/ccICigVb.s 			page 357
+
+
+ 6037              		.loc 1 3548 10 view .LVU1826
+ 6038 008c 0020     		movs	r0, #0
+ 6039              	.LVL488:
+ 6040              	.L403:
+3549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6041              		.loc 1 3549 1 view .LVU1827
+ 6042 008e 38BD     		pop	{r3, r4, r5, pc}
+ 6043              	.LVL489:
+ 6044              	.L408:
+3548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 6045              		.loc 1 3548 10 view .LVU1828
+ 6046 0090 0020     		movs	r0, #0
+ 6047              	.LVL490:
+3548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 6048              		.loc 1 3548 10 view .LVU1829
+ 6049 0092 FCE7     		b	.L403
+ 6050              		.cfi_endproc
+ 6051              	.LFE355:
+ 6053              		.section	.text.HAL_ADC_DeInit,"ax",%progbits
+ 6054              		.align	1
+ 6055              		.global	HAL_ADC_DeInit
+ 6056              		.syntax unified
+ 6057              		.thumb
+ 6058              		.thumb_func
+ 6060              	HAL_ADC_DeInit:
+ 6061              	.LVL491:
+ 6062              	.LFB330:
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 6063              		.loc 1 715 1 is_stmt 1 view -0
+ 6064              		.cfi_startproc
+ 6065              		@ args = 0, pretend = 0, frame = 0
+ 6066              		@ frame_needed = 0, uses_anonymous_args = 0
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 6067              		.loc 1 715 1 is_stmt 0 view .LVU1831
+ 6068 0000 38B5     		push	{r3, r4, r5, lr}
+ 6069              	.LCFI26:
+ 6070              		.cfi_def_cfa_offset 16
+ 6071              		.cfi_offset 3, -16
+ 6072              		.cfi_offset 4, -12
+ 6073              		.cfi_offset 5, -8
+ 6074              		.cfi_offset 14, -4
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6075              		.loc 1 716 3 is_stmt 1 view .LVU1832
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 6076              		.loc 1 719 3 view .LVU1833
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 6077              		.loc 1 719 6 is_stmt 0 view .LVU1834
+ 6078 0002 0028     		cmp	r0, #0
+ 6079 0004 00F0C980 		beq	.L418
+ 6080 0008 0446     		mov	r4, r0
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6081              		.loc 1 725 3 is_stmt 1 view .LVU1835
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6082              		.loc 1 728 3 view .LVU1836
+ 6083 000a C36D     		ldr	r3, [r0, #92]
+ 6084 000c 43F00203 		orr	r3, r3, #2
+ 6085 0010 C365     		str	r3, [r0, #92]
+ARM GAS  /tmp/ccICigVb.s 			page 358
+
+
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6086              		.loc 1 731 3 view .LVU1837
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6087              		.loc 1 731 20 is_stmt 0 view .LVU1838
+ 6088 0012 0321     		movs	r1, #3
+ 6089 0014 FFF7FEFF 		bl	ADC_ConversionStop
+ 6090              	.LVL492:
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6091              		.loc 1 739 3 is_stmt 1 view .LVU1839
+ 6092 0018 2268     		ldr	r2, [r4]
+ 6093 001a D368     		ldr	r3, [r2, #12]
+ 6094 001c 43F40013 		orr	r3, r3, #2097152
+ 6095 0020 D360     		str	r3, [r2, #12]
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 6096              		.loc 1 742 3 view .LVU1840
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 6097              		.loc 1 742 6 is_stmt 0 view .LVU1841
+ 6098 0022 0546     		mov	r5, r0
+ 6099 0024 0028     		cmp	r0, #0
+ 6100 0026 00F09F80 		beq	.L420
+ 6101              	.L414:
+ 6102              	.LVL493:
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                               ADC_IT_JQOVF | ADC_IT_OVR  |
+ 6103              		.loc 1 763 3 is_stmt 1 view .LVU1842
+ 6104 002a 2268     		ldr	r2, [r4]
+ 6105 002c 5368     		ldr	r3, [r2, #4]
+ 6106 002e 23F4FF63 		bic	r3, r3, #2040
+ 6107 0032 23F00703 		bic	r3, r3, #7
+ 6108 0036 5360     		str	r3, [r2, #4]
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                               ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
+ 6109              		.loc 1 770 3 view .LVU1843
+ 6110 0038 2368     		ldr	r3, [r4]
+ 6111 003a 40F2FF72 		movw	r2, #2047
+ 6112 003e 1A60     		str	r2, [r3]
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+ 6113              		.loc 1 781 3 view .LVU1844
+ 6114 0040 2268     		ldr	r2, [r4]
+ 6115 0042 9368     		ldr	r3, [r2, #8]
+ 6116 0044 23F0A043 		bic	r3, r3, #1342177280
+ 6117 0048 9360     		str	r3, [r2, #8]
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6118              		.loc 1 782 3 view .LVU1845
+ 6119 004a 2268     		ldr	r2, [r4]
+ 6120 004c 9368     		ldr	r3, [r2, #8]
+ 6121 004e 43F00053 		orr	r3, r3, #536870912
+ 6122 0052 9360     		str	r3, [r2, #8]
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+ 6123              		.loc 1 785 3 view .LVU1846
+ 6124 0054 2268     		ldr	r2, [r4]
+ 6125 0056 D368     		ldr	r3, [r2, #12]
+ 6126 0058 23F0FF43 		bic	r3, r3, #2139095040
+ 6127 005c 23F4FF03 		bic	r3, r3, #8355840
+ 6128 0060 23F4FF43 		bic	r3, r3, #32640
+ 6129 0064 23F07B03 		bic	r3, r3, #123
+ 6130 0068 D360     		str	r3, [r2, #12]
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6131              		.loc 1 786 3 view .LVU1847
+ARM GAS  /tmp/ccICigVb.s 			page 359
+
+
+ 6132 006a 2268     		ldr	r2, [r4]
+ 6133 006c D368     		ldr	r3, [r2, #12]
+ 6134 006e 43F00043 		orr	r3, r3, #-2147483648
+ 6135 0072 D360     		str	r3, [r2, #12]
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             ADC_CFGR2_OVSR  | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
+ 6136              		.loc 1 789 3 view .LVU1848
+ 6137 0074 2268     		ldr	r2, [r4]
+ 6138 0076 1369     		ldr	r3, [r2, #16]
+ 6139 0078 23F4FF63 		bic	r3, r3, #2040
+ 6140 007c 23F00703 		bic	r3, r3, #7
+ 6141 0080 1361     		str	r3, [r2, #16]
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6142              		.loc 1 793 3 view .LVU1849
+ 6143 0082 2268     		ldr	r2, [r4]
+ 6144 0084 5369     		ldr	r3, [r2, #20]
+ 6145 0086 03F08043 		and	r3, r3, #1073741824
+ 6146 008a 5361     		str	r3, [r2, #20]
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+ 6147              		.loc 1 796 3 view .LVU1850
+ 6148 008c 2268     		ldr	r2, [r4]
+ 6149 008e 9369     		ldr	r3, [r2, #24]
+ 6150 0090 03F07843 		and	r3, r3, #-134217728
+ 6151 0094 9361     		str	r3, [r2, #24]
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6152              		.loc 1 801 3 view .LVU1851
+ 6153 0096 2268     		ldr	r2, [r4]
+ 6154 0098 136A     		ldr	r3, [r2, #32]
+ 6155 009a 03F0F023 		and	r3, r3, #-268374016
+ 6156 009e 1362     		str	r3, [r2, #32]
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6157              		.loc 1 804 3 view .LVU1852
+ 6158 00a0 2268     		ldr	r2, [r4]
+ 6159 00a2 536A     		ldr	r3, [r2, #36]
+ 6160 00a4 03F0FF23 		and	r3, r3, #-16711936
+ 6161 00a8 5362     		str	r3, [r2, #36]
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6162              		.loc 1 807 3 view .LVU1853
+ 6163 00aa 2268     		ldr	r2, [r4]
+ 6164 00ac 936A     		ldr	r3, [r2, #40]
+ 6165 00ae 03F0FF23 		and	r3, r3, #-16711936
+ 6166 00b2 9362     		str	r3, [r2, #40]
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             ADC_SQR1_SQ1 | ADC_SQR1_L);
+ 6167              		.loc 1 810 3 view .LVU1854
+ 6168 00b4 2268     		ldr	r2, [r4]
+ 6169 00b6 116B     		ldr	r1, [r2, #48]
+ 6170 00b8 394B     		ldr	r3, .L422
+ 6171 00ba 0B40     		ands	r3, r3, r1
+ 6172 00bc 1363     		str	r3, [r2, #48]
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
+ 6173              		.loc 1 814 3 view .LVU1855
+ 6174 00be 2268     		ldr	r2, [r4]
+ 6175 00c0 536B     		ldr	r3, [r2, #52]
+ 6176 00c2 3849     		ldr	r1, .L422+4
+ 6177 00c4 0B40     		ands	r3, r3, r1
+ 6178 00c6 5363     		str	r3, [r2, #52]
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****             ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
+ 6179              		.loc 1 818 3 view .LVU1856
+ARM GAS  /tmp/ccICigVb.s 			page 360
+
+
+ 6180 00c8 2268     		ldr	r2, [r4]
+ 6181 00ca 936B     		ldr	r3, [r2, #56]
+ 6182 00cc 0B40     		ands	r3, r3, r1
+ 6183 00ce 9363     		str	r3, [r2, #56]
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6184              		.loc 1 822 3 view .LVU1857
+ 6185 00d0 2268     		ldr	r2, [r4]
+ 6186 00d2 D36B     		ldr	r3, [r2, #60]
+ 6187 00d4 23F4FB63 		bic	r3, r3, #2008
+ 6188 00d8 23F00703 		bic	r3, r3, #7
+ 6189 00dc D363     		str	r3, [r2, #60]
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register OFR2 */
+ 6190              		.loc 1 830 3 view .LVU1858
+ 6191 00de 2168     		ldr	r1, [r4]
+ 6192 00e0 0A6E     		ldr	r2, [r1, #96]
+ 6193 00e2 314B     		ldr	r3, .L422+8
+ 6194 00e4 1A40     		ands	r2, r2, r3
+ 6195 00e6 0A66     		str	r2, [r1, #96]
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register OFR3 */
+ 6196              		.loc 1 832 3 view .LVU1859
+ 6197 00e8 2168     		ldr	r1, [r4]
+ 6198 00ea 4A6E     		ldr	r2, [r1, #100]
+ 6199 00ec 1A40     		ands	r2, r2, r3
+ 6200 00ee 4A66     		str	r2, [r1, #100]
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   /* Reset register OFR4 */
+ 6201              		.loc 1 834 3 view .LVU1860
+ 6202 00f0 2168     		ldr	r1, [r4]
+ 6203 00f2 8A6E     		ldr	r2, [r1, #104]
+ 6204 00f4 1A40     		ands	r2, r2, r3
+ 6205 00f6 8A66     		str	r2, [r1, #104]
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6206              		.loc 1 836 3 view .LVU1861
+ 6207 00f8 2168     		ldr	r1, [r4]
+ 6208 00fa CA6E     		ldr	r2, [r1, #108]
+ 6209 00fc 1340     		ands	r3, r3, r2
+ 6210 00fe CB66     		str	r3, [r1, #108]
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6211              		.loc 1 842 3 view .LVU1862
+ 6212 0100 2268     		ldr	r2, [r4]
+ 6213 0102 D2F8A030 		ldr	r3, [r2, #160]
+ 6214 0106 DB0C     		lsrs	r3, r3, #19
+ 6215 0108 DB04     		lsls	r3, r3, #19
+ 6216 010a C2F8A030 		str	r3, [r2, #160]
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6217              		.loc 1 845 3 view .LVU1863
+ 6218 010e 2268     		ldr	r2, [r4]
+ 6219 0110 D2F8A430 		ldr	r3, [r2, #164]
+ 6220 0114 DB0C     		lsrs	r3, r3, #19
+ 6221 0116 DB04     		lsls	r3, r3, #19
+ 6222 0118 C2F8A430 		str	r3, [r2, #164]
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6223              		.loc 1 848 3 view .LVU1864
+ 6224 011c 2268     		ldr	r2, [r4]
+ 6225 011e D2F8B030 		ldr	r3, [r2, #176]
+ 6226 0122 DB0C     		lsrs	r3, r3, #19
+ 6227 0124 DB04     		lsls	r3, r3, #19
+ 6228 0126 C2F8B030 		str	r3, [r2, #176]
+ARM GAS  /tmp/ccICigVb.s 			page 361
+
+
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6229              		.loc 1 851 3 view .LVU1865
+ 6230 012a 2268     		ldr	r2, [r4]
+ 6231 012c D2F8B430 		ldr	r3, [r2, #180]
+ 6232 0130 23F07F13 		bic	r3, r3, #8323199
+ 6233 0134 C2F8B430 		str	r3, [r2, #180]
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 6234              		.loc 1 858 3 view .LVU1866
+ 6235              	.LVL494:
+ 6236              	.LBB598:
+ 6237              	.LBI598:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 6238              		.loc 2 6729 26 view .LVU1867
+ 6239              	.LBB599:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 6240              		.loc 2 6731 3 view .LVU1868
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 6241              		.loc 2 6731 12 is_stmt 0 view .LVU1869
+ 6242 0138 4FF0A043 		mov	r3, #1342177280
+ 6243 013c 9A68     		ldr	r2, [r3, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 6244              		.loc 2 6731 68 view .LVU1870
+ 6245 013e 12F00102 		ands	r2, r2, #1
+ 6246 0142 00D0     		beq	.L415
+ 6247 0144 0122     		movs	r2, #1
+ 6248              	.L415:
+ 6249              	.LVL495:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 6250              		.loc 2 6731 68 view .LVU1871
+ 6251              	.LBE599:
+ 6252              	.LBE598:
+ 6253              	.LBB600:
+ 6254              	.LBI600:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 6255              		.loc 2 6729 26 is_stmt 1 view .LVU1872
+ 6256              	.LBB601:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 6257              		.loc 2 6731 3 view .LVU1873
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 6258              		.loc 2 6731 12 is_stmt 0 view .LVU1874
+ 6259 0146 194B     		ldr	r3, .L422+12
+ 6260 0148 9B68     		ldr	r3, [r3, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 6261              		.loc 2 6731 68 view .LVU1875
+ 6262 014a 13F00103 		ands	r3, r3, #1
+ 6263 014e 00D0     		beq	.L416
+ 6264 0150 0123     		movs	r3, #1
+ 6265              	.L416:
+ 6266              	.LVL496:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 6267              		.loc 2 6731 68 view .LVU1876
+ 6268              	.LBE601:
+ 6269              	.LBE600:
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 6270              		.loc 1 858 6 view .LVU1877
+ 6271 0152 1343     		orrs	r3, r3, r2
+ 6272 0154 12D0     		beq	.L421
+ARM GAS  /tmp/ccICigVb.s 			page 362
+
+
+ 6273              	.L417:
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6274              		.loc 1 892 3 is_stmt 1 view .LVU1878
+ 6275 0156 0023     		movs	r3, #0
+ 6276 0158 2366     		str	r3, [r4, #96]
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   hadc->InjectionConfig.ChannelCount = 0;
+ 6277              		.loc 1 895 3 view .LVU1879
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   hadc->InjectionConfig.ChannelCount = 0;
+ 6278              		.loc 1 895 38 is_stmt 0 view .LVU1880
+ 6279 015a 6366     		str	r3, [r4, #100]
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6280              		.loc 1 896 3 is_stmt 1 view .LVU1881
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6281              		.loc 1 896 38 is_stmt 0 view .LVU1882
+ 6282 015c A366     		str	r3, [r4, #104]
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6283              		.loc 1 899 3 is_stmt 1 view .LVU1883
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6284              		.loc 1 899 15 is_stmt 0 view .LVU1884
+ 6285 015e E365     		str	r3, [r4, #92]
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6286              		.loc 1 902 3 is_stmt 1 view .LVU1885
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6287              		.loc 1 902 3 view .LVU1886
+ 6288 0160 84F85830 		strb	r3, [r4, #88]
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6289              		.loc 1 902 3 view .LVU1887
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 6290              		.loc 1 905 3 view .LVU1888
+ 6291              	.LVL497:
+ 6292              	.L413:
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6293              		.loc 1 906 1 is_stmt 0 view .LVU1889
+ 6294 0164 2846     		mov	r0, r5
+ 6295 0166 38BD     		pop	{r3, r4, r5, pc}
+ 6296              	.LVL498:
+ 6297              	.L420:
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6298              		.loc 1 745 5 is_stmt 1 view .LVU1890
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6299              		.loc 1 745 22 is_stmt 0 view .LVU1891
+ 6300 0168 2046     		mov	r0, r4
+ 6301              	.LVL499:
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6302              		.loc 1 745 22 view .LVU1892
+ 6303 016a FFF7FEFF 		bl	ADC_Disable
+ 6304              	.LVL500:
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6305              		.loc 1 748 5 is_stmt 1 view .LVU1893
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6306              		.loc 1 748 8 is_stmt 0 view .LVU1894
+ 6307 016e 0546     		mov	r5, r0
+ 6308 0170 0028     		cmp	r0, #0
+ 6309 0172 7FF45AAF 		bne	.L414
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 6310              		.loc 1 751 7 is_stmt 1 view .LVU1895
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ARM GAS  /tmp/ccICigVb.s 			page 363
+
+
+ 6311              		.loc 1 751 19 is_stmt 0 view .LVU1896
+ 6312 0176 0123     		movs	r3, #1
+ 6313 0178 E365     		str	r3, [r4, #92]
+ 6314 017a 56E7     		b	.L414
+ 6315              	.LVL501:
+ 6316              	.L421:
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6317              		.loc 1 867 5 is_stmt 1 view .LVU1897
+ 6318 017c 0C4A     		ldr	r2, .L422+16
+ 6319 017e 9368     		ldr	r3, [r2, #8]
+ 6320 0180 23F0FF73 		bic	r3, r3, #33423360
+ 6321 0184 23F4F733 		bic	r3, r3, #126464
+ 6322 0188 23F48F73 		bic	r3, r3, #286
+ 6323 018c 23F00103 		bic	r3, r3, #1
+ 6324 0190 9360     		str	r3, [r2, #8]
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 6325              		.loc 1 887 5 view .LVU1898
+ 6326 0192 2046     		mov	r0, r4
+ 6327 0194 FFF7FEFF 		bl	HAL_ADC_MspDeInit
+ 6328              	.LVL502:
+ 6329 0198 DDE7     		b	.L417
+ 6330              	.LVL503:
+ 6331              	.L418:
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   }
+ 6332              		.loc 1 721 12 is_stmt 0 view .LVU1899
+ 6333 019a 0125     		movs	r5, #1
+ 6334 019c E2E7     		b	.L413
+ 6335              	.L423:
+ 6336 019e 00BF     		.align	2
+ 6337              	.L422:
+ 6338 01a0 300882E0 		.word	-528349136
+ 6339 01a4 200882E0 		.word	-528349152
+ 6340 01a8 00F0FF03 		.word	67104768
+ 6341 01ac 00010050 		.word	1342177536
+ 6342 01b0 00030050 		.word	1342178048
+ 6343              		.cfi_endproc
+ 6344              	.LFE330:
+ 6346              		.section	.text.HAL_ADC_Stop,"ax",%progbits
+ 6347              		.align	1
+ 6348              		.global	HAL_ADC_Stop
+ 6349              		.syntax unified
+ 6350              		.thumb
+ 6351              		.thumb_func
+ 6353              	HAL_ADC_Stop:
+ 6354              	.LVL504:
+ 6355              	.LFB334:
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 6356              		.loc 1 1356 1 is_stmt 1 view -0
+ 6357              		.cfi_startproc
+ 6358              		@ args = 0, pretend = 0, frame = 0
+ 6359              		@ frame_needed = 0, uses_anonymous_args = 0
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6360              		.loc 1 1357 3 view .LVU1901
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6361              		.loc 1 1360 3 view .LVU1902
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6362              		.loc 1 1363 3 view .LVU1903
+ARM GAS  /tmp/ccICigVb.s 			page 364
+
+
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6363              		.loc 1 1363 3 view .LVU1904
+ 6364 0000 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 6365 0004 012B     		cmp	r3, #1
+ 6366 0006 1AD0     		beq	.L427
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 6367              		.loc 1 1356 1 is_stmt 0 discriminator 2 view .LVU1905
+ 6368 0008 10B5     		push	{r4, lr}
+ 6369              	.LCFI27:
+ 6370              		.cfi_def_cfa_offset 8
+ 6371              		.cfi_offset 4, -8
+ 6372              		.cfi_offset 14, -4
+ 6373 000a 0446     		mov	r4, r0
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6374              		.loc 1 1363 3 is_stmt 1 discriminator 2 view .LVU1906
+ 6375 000c 0123     		movs	r3, #1
+ 6376 000e 80F85830 		strb	r3, [r0, #88]
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6377              		.loc 1 1363 3 discriminator 2 view .LVU1907
+1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6378              		.loc 1 1366 3 discriminator 2 view .LVU1908
+1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6379              		.loc 1 1366 20 is_stmt 0 discriminator 2 view .LVU1909
+ 6380 0012 0321     		movs	r1, #3
+ 6381 0014 FFF7FEFF 		bl	ADC_ConversionStop
+ 6382              	.LVL505:
+1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 6383              		.loc 1 1369 3 is_stmt 1 discriminator 2 view .LVU1910
+1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 6384              		.loc 1 1369 6 is_stmt 0 discriminator 2 view .LVU1911
+ 6385 0018 18B1     		cbz	r0, .L432
+ 6386              	.L426:
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6387              		.loc 1 1385 3 is_stmt 1 view .LVU1912
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6388              		.loc 1 1385 3 view .LVU1913
+ 6389 001a 0023     		movs	r3, #0
+ 6390 001c 84F85830 		strb	r3, [r4, #88]
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6391              		.loc 1 1385 3 view .LVU1914
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 6392              		.loc 1 1388 3 view .LVU1915
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6393              		.loc 1 1389 1 is_stmt 0 view .LVU1916
+ 6394 0020 10BD     		pop	{r4, pc}
+ 6395              	.LVL506:
+ 6396              	.L432:
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6397              		.loc 1 1372 5 is_stmt 1 view .LVU1917
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6398              		.loc 1 1372 22 is_stmt 0 view .LVU1918
+ 6399 0022 2046     		mov	r0, r4
+ 6400              	.LVL507:
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6401              		.loc 1 1372 22 view .LVU1919
+ 6402 0024 FFF7FEFF 		bl	ADC_Disable
+ 6403              	.LVL508:
+ARM GAS  /tmp/ccICigVb.s 			page 365
+
+
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6404              		.loc 1 1375 5 is_stmt 1 view .LVU1920
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6405              		.loc 1 1375 8 is_stmt 0 view .LVU1921
+ 6406 0028 0028     		cmp	r0, #0
+ 6407 002a F6D1     		bne	.L426
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 6408              		.loc 1 1378 7 is_stmt 1 view .LVU1922
+ 6409 002c E36D     		ldr	r3, [r4, #92]
+ 6410 002e 23F48853 		bic	r3, r3, #4352
+ 6411 0032 23F00103 		bic	r3, r3, #1
+ 6412 0036 43F00103 		orr	r3, r3, #1
+ 6413 003a E365     		str	r3, [r4, #92]
+ 6414 003c EDE7     		b	.L426
+ 6415              	.LVL509:
+ 6416              	.L427:
+ 6417              	.LCFI28:
+ 6418              		.cfi_def_cfa_offset 0
+ 6419              		.cfi_restore 4
+ 6420              		.cfi_restore 14
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6421              		.loc 1 1363 3 is_stmt 0 view .LVU1923
+ 6422 003e 0220     		movs	r0, #2
+ 6423              	.LVL510:
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6424              		.loc 1 1389 1 view .LVU1924
+ 6425 0040 7047     		bx	lr
+ 6426              		.cfi_endproc
+ 6427              	.LFE334:
+ 6429              		.section	.text.HAL_ADC_Stop_IT,"ax",%progbits
+ 6430              		.align	1
+ 6431              		.global	HAL_ADC_Stop_IT
+ 6432              		.syntax unified
+ 6433              		.thumb
+ 6434              		.thumb_func
+ 6436              	HAL_ADC_Stop_IT:
+ 6437              	.LVL511:
+ 6438              	.LFB338:
+1949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 6439              		.loc 1 1949 1 is_stmt 1 view -0
+ 6440              		.cfi_startproc
+ 6441              		@ args = 0, pretend = 0, frame = 0
+ 6442              		@ frame_needed = 0, uses_anonymous_args = 0
+1950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6443              		.loc 1 1950 3 view .LVU1926
+1953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6444              		.loc 1 1953 3 view .LVU1927
+1956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6445              		.loc 1 1956 3 view .LVU1928
+1956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6446              		.loc 1 1956 3 view .LVU1929
+ 6447 0000 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 6448 0004 012B     		cmp	r3, #1
+ 6449 0006 1FD0     		beq	.L436
+1949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 6450              		.loc 1 1949 1 is_stmt 0 discriminator 2 view .LVU1930
+ 6451 0008 10B5     		push	{r4, lr}
+ARM GAS  /tmp/ccICigVb.s 			page 366
+
+
+ 6452              	.LCFI29:
+ 6453              		.cfi_def_cfa_offset 8
+ 6454              		.cfi_offset 4, -8
+ 6455              		.cfi_offset 14, -4
+ 6456 000a 0446     		mov	r4, r0
+1956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6457              		.loc 1 1956 3 is_stmt 1 discriminator 2 view .LVU1931
+ 6458 000c 0123     		movs	r3, #1
+ 6459 000e 80F85830 		strb	r3, [r0, #88]
+1956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6460              		.loc 1 1956 3 discriminator 2 view .LVU1932
+1959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6461              		.loc 1 1959 3 discriminator 2 view .LVU1933
+1959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6462              		.loc 1 1959 20 is_stmt 0 discriminator 2 view .LVU1934
+ 6463 0012 0321     		movs	r1, #3
+ 6464 0014 FFF7FEFF 		bl	ADC_ConversionStop
+ 6465              	.LVL512:
+1962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 6466              		.loc 1 1962 3 is_stmt 1 discriminator 2 view .LVU1935
+1962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 6467              		.loc 1 1962 6 is_stmt 0 discriminator 2 view .LVU1936
+ 6468 0018 18B1     		cbz	r0, .L441
+ 6469              	.L435:
+1982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6470              		.loc 1 1982 3 is_stmt 1 view .LVU1937
+1982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6471              		.loc 1 1982 3 view .LVU1938
+ 6472 001a 0023     		movs	r3, #0
+ 6473 001c 84F85830 		strb	r3, [r4, #88]
+1982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6474              		.loc 1 1982 3 view .LVU1939
+1985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 6475              		.loc 1 1985 3 view .LVU1940
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6476              		.loc 1 1986 1 is_stmt 0 view .LVU1941
+ 6477 0020 10BD     		pop	{r4, pc}
+ 6478              	.LVL513:
+ 6479              	.L441:
+1966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6480              		.loc 1 1966 5 is_stmt 1 view .LVU1942
+ 6481 0022 2268     		ldr	r2, [r4]
+ 6482 0024 5368     		ldr	r3, [r2, #4]
+ 6483 0026 23F01C03 		bic	r3, r3, #28
+ 6484 002a 5360     		str	r3, [r2, #4]
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6485              		.loc 1 1969 5 view .LVU1943
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6486              		.loc 1 1969 22 is_stmt 0 view .LVU1944
+ 6487 002c 2046     		mov	r0, r4
+ 6488              	.LVL514:
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6489              		.loc 1 1969 22 view .LVU1945
+ 6490 002e FFF7FEFF 		bl	ADC_Disable
+ 6491              	.LVL515:
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6492              		.loc 1 1972 5 is_stmt 1 view .LVU1946
+ARM GAS  /tmp/ccICigVb.s 			page 367
+
+
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6493              		.loc 1 1972 8 is_stmt 0 view .LVU1947
+ 6494 0032 0028     		cmp	r0, #0
+ 6495 0034 F1D1     		bne	.L435
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 6496              		.loc 1 1975 7 is_stmt 1 view .LVU1948
+ 6497 0036 E36D     		ldr	r3, [r4, #92]
+ 6498 0038 23F48853 		bic	r3, r3, #4352
+ 6499 003c 23F00103 		bic	r3, r3, #1
+ 6500 0040 43F00103 		orr	r3, r3, #1
+ 6501 0044 E365     		str	r3, [r4, #92]
+ 6502 0046 E8E7     		b	.L435
+ 6503              	.LVL516:
+ 6504              	.L436:
+ 6505              	.LCFI30:
+ 6506              		.cfi_def_cfa_offset 0
+ 6507              		.cfi_restore 4
+ 6508              		.cfi_restore 14
+1956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6509              		.loc 1 1956 3 is_stmt 0 view .LVU1949
+ 6510 0048 0220     		movs	r0, #2
+ 6511              	.LVL517:
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6512              		.loc 1 1986 1 view .LVU1950
+ 6513 004a 7047     		bx	lr
+ 6514              		.cfi_endproc
+ 6515              	.LFE338:
+ 6517              		.section	.text.HAL_ADC_Stop_DMA,"ax",%progbits
+ 6518              		.align	1
+ 6519              		.global	HAL_ADC_Stop_DMA
+ 6520              		.syntax unified
+ 6521              		.thumb
+ 6522              		.thumb_func
+ 6524              	HAL_ADC_Stop_DMA:
+ 6525              	.LVL518:
+ 6526              	.LFB340:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 6527              		.loc 1 2144 1 is_stmt 1 view -0
+ 6528              		.cfi_startproc
+ 6529              		@ args = 0, pretend = 0, frame = 0
+ 6530              		@ frame_needed = 0, uses_anonymous_args = 0
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 6531              		.loc 1 2144 1 is_stmt 0 view .LVU1952
+ 6532 0000 38B5     		push	{r3, r4, r5, lr}
+ 6533              	.LCFI31:
+ 6534              		.cfi_def_cfa_offset 16
+ 6535              		.cfi_offset 3, -16
+ 6536              		.cfi_offset 4, -12
+ 6537              		.cfi_offset 5, -8
+ 6538              		.cfi_offset 14, -4
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6539              		.loc 1 2145 3 is_stmt 1 view .LVU1953
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6540              		.loc 1 2148 3 view .LVU1954
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6541              		.loc 1 2151 3 view .LVU1955
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ARM GAS  /tmp/ccICigVb.s 			page 368
+
+
+ 6542              		.loc 1 2151 3 view .LVU1956
+ 6543 0002 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 6544 0006 012B     		cmp	r3, #1
+ 6545 0008 39D0     		beq	.L448
+ 6546 000a 0446     		mov	r4, r0
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6547              		.loc 1 2151 3 discriminator 2 view .LVU1957
+ 6548 000c 0123     		movs	r3, #1
+ 6549 000e 80F85830 		strb	r3, [r0, #88]
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6550              		.loc 1 2151 3 discriminator 2 view .LVU1958
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6551              		.loc 1 2154 3 discriminator 2 view .LVU1959
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6552              		.loc 1 2154 20 is_stmt 0 discriminator 2 view .LVU1960
+ 6553 0012 0321     		movs	r1, #3
+ 6554 0014 FFF7FEFF 		bl	ADC_ConversionStop
+ 6555              	.LVL519:
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 6556              		.loc 1 2157 3 is_stmt 1 discriminator 2 view .LVU1961
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****   {
+ 6557              		.loc 1 2157 6 is_stmt 0 discriminator 2 view .LVU1962
+ 6558 0018 0546     		mov	r5, r0
+ 6559 001a E8B9     		cbnz	r0, .L444
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6560              		.loc 1 2160 5 is_stmt 1 view .LVU1963
+ 6561 001c 2268     		ldr	r2, [r4]
+ 6562 001e D368     		ldr	r3, [r2, #12]
+ 6563 0020 23F00103 		bic	r3, r3, #1
+ 6564 0024 D360     		str	r3, [r2, #12]
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6565              		.loc 1 2164 5 view .LVU1964
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6566              		.loc 1 2164 13 is_stmt 0 view .LVU1965
+ 6567 0026 606D     		ldr	r0, [r4, #84]
+ 6568              	.LVL520:
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6569              		.loc 1 2164 25 view .LVU1966
+ 6570 0028 90F82530 		ldrb	r3, [r0, #37]	@ zero_extendqisi2
+ 6571 002c DBB2     		uxtb	r3, r3
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6572              		.loc 1 2164 8 view .LVU1967
+ 6573 002e 022B     		cmp	r3, #2
+ 6574 0030 17D0     		beq	.L450
+ 6575              	.LVL521:
+ 6576              	.L445:
+2177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6577              		.loc 1 2177 5 is_stmt 1 view .LVU1968
+ 6578 0032 2268     		ldr	r2, [r4]
+ 6579 0034 5368     		ldr	r3, [r2, #4]
+ 6580 0036 23F01003 		bic	r3, r3, #16
+ 6581 003a 5360     		str	r3, [r2, #4]
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6582              		.loc 1 2182 5 view .LVU1969
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6583              		.loc 1 2182 8 is_stmt 0 view .LVU1970
+ 6584 003c DDB9     		cbnz	r5, .L446
+ARM GAS  /tmp/ccICigVb.s 			page 369
+
+
+2184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 6585              		.loc 1 2184 7 is_stmt 1 view .LVU1971
+2184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 6586              		.loc 1 2184 24 is_stmt 0 view .LVU1972
+ 6587 003e 2046     		mov	r0, r4
+ 6588 0040 FFF7FEFF 		bl	ADC_Disable
+ 6589              	.LVL522:
+ 6590 0044 0546     		mov	r5, r0
+ 6591              	.LVL523:
+ 6592              	.L447:
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6593              		.loc 1 2192 5 is_stmt 1 view .LVU1973
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     {
+ 6594              		.loc 1 2192 8 is_stmt 0 view .LVU1974
+ 6595 0046 3DB9     		cbnz	r5, .L444
+2195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 6596              		.loc 1 2195 7 is_stmt 1 view .LVU1975
+ 6597 0048 E36D     		ldr	r3, [r4, #92]
+ 6598 004a 23F48853 		bic	r3, r3, #4352
+ 6599 004e 23F00103 		bic	r3, r3, #1
+ 6600 0052 43F00103 		orr	r3, r3, #1
+ 6601 0056 E365     		str	r3, [r4, #92]
+ 6602              	.LVL524:
+ 6603              	.L444:
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6604              		.loc 1 2203 3 view .LVU1976
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6605              		.loc 1 2203 3 view .LVU1977
+ 6606 0058 0023     		movs	r3, #0
+ 6607 005a 84F85830 		strb	r3, [r4, #88]
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6608              		.loc 1 2203 3 view .LVU1978
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** }
+ 6609              		.loc 1 2206 3 view .LVU1979
+ 6610              	.LVL525:
+ 6611              	.L443:
+2207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6612              		.loc 1 2207 1 is_stmt 0 view .LVU1980
+ 6613 005e 2846     		mov	r0, r5
+ 6614 0060 38BD     		pop	{r3, r4, r5, pc}
+ 6615              	.LVL526:
+ 6616              	.L450:
+2166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6617              		.loc 1 2166 7 is_stmt 1 view .LVU1981
+2166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6618              		.loc 1 2166 24 is_stmt 0 view .LVU1982
+ 6619 0062 FFF7FEFF 		bl	HAL_DMA_Abort
+ 6620              	.LVL527:
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 6621              		.loc 1 2169 7 is_stmt 1 view .LVU1983
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       {
+ 6622              		.loc 1 2169 10 is_stmt 0 view .LVU1984
+ 6623 0066 0546     		mov	r5, r0
+ 6624 0068 0028     		cmp	r0, #0
+ 6625 006a E2D0     		beq	.L445
+2172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****       }
+ 6626              		.loc 1 2172 9 is_stmt 1 view .LVU1985
+ARM GAS  /tmp/ccICigVb.s 			page 370
+
+
+ 6627 006c E36D     		ldr	r3, [r4, #92]
+ 6628 006e 43F04003 		orr	r3, r3, #64
+ 6629 0072 E365     		str	r3, [r4, #92]
+ 6630 0074 DDE7     		b	.L445
+ 6631              	.LVL528:
+ 6632              	.L446:
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 6633              		.loc 1 2188 7 view .LVU1986
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ****     }
+ 6634              		.loc 1 2188 13 is_stmt 0 view .LVU1987
+ 6635 0076 2046     		mov	r0, r4
+ 6636 0078 FFF7FEFF 		bl	ADC_Disable
+ 6637              	.LVL529:
+ 6638 007c E3E7     		b	.L447
+ 6639              	.LVL530:
+ 6640              	.L448:
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c **** 
+ 6641              		.loc 1 2151 3 view .LVU1988
+ 6642 007e 0225     		movs	r5, #2
+ 6643 0080 EDE7     		b	.L443
+ 6644              		.cfi_endproc
+ 6645              	.LFE340:
+ 6647              		.text
+ 6648              	.Letext0:
+ 6649              		.file 4 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 6650              		.file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 6651              		.file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 6652              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 6653              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 6654              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h"
+ 6655              		.file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h"
+ 6656              		.file 11 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
+ 6657              		.file 12 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ARM GAS  /tmp/ccICigVb.s 			page 371
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_adc.c
+     /tmp/ccICigVb.s:21     .text.LL_ADC_REG_SetSequencerRanks:00000000 $t
+     /tmp/ccICigVb.s:26     .text.LL_ADC_REG_SetSequencerRanks:00000000 LL_ADC_REG_SetSequencerRanks
+     /tmp/ccICigVb.s:73     .text.LL_ADC_SetChannelSamplingTime:00000000 $t
+     /tmp/ccICigVb.s:78     .text.LL_ADC_SetChannelSamplingTime:00000000 LL_ADC_SetChannelSamplingTime
+     /tmp/ccICigVb.s:123    .text.LL_ADC_SetAnalogWDMonitChannels:00000000 $t
+     /tmp/ccICigVb.s:128    .text.LL_ADC_SetAnalogWDMonitChannels:00000000 LL_ADC_SetAnalogWDMonitChannels
+     /tmp/ccICigVb.s:166    .text.HAL_ADC_MspInit:00000000 $t
+     /tmp/ccICigVb.s:172    .text.HAL_ADC_MspInit:00000000 HAL_ADC_MspInit
+     /tmp/ccICigVb.s:187    .text.HAL_ADC_Init:00000000 $t
+     /tmp/ccICigVb.s:193    .text.HAL_ADC_Init:00000000 HAL_ADC_Init
+     /tmp/ccICigVb.s:762    .text.HAL_ADC_Init:0000022c $d
+     /tmp/ccICigVb.s:771    .text.HAL_ADC_MspDeInit:00000000 $t
+     /tmp/ccICigVb.s:777    .text.HAL_ADC_MspDeInit:00000000 HAL_ADC_MspDeInit
+     /tmp/ccICigVb.s:792    .text.HAL_ADC_PollForConversion:00000000 $t
+     /tmp/ccICigVb.s:798    .text.HAL_ADC_PollForConversion:00000000 HAL_ADC_PollForConversion
+     /tmp/ccICigVb.s:1083   .text.HAL_ADC_PollForConversion:00000114 $d
+     /tmp/ccICigVb.s:1089   .text.HAL_ADC_PollForEvent:00000000 $t
+     /tmp/ccICigVb.s:1095   .text.HAL_ADC_PollForEvent:00000000 HAL_ADC_PollForEvent
+     /tmp/ccICigVb.s:1283   .text.HAL_ADC_GetValue:00000000 $t
+     /tmp/ccICigVb.s:1289   .text.HAL_ADC_GetValue:00000000 HAL_ADC_GetValue
+     /tmp/ccICigVb.s:1310   .text.HAL_ADC_StartSampling:00000000 $t
+     /tmp/ccICigVb.s:1316   .text.HAL_ADC_StartSampling:00000000 HAL_ADC_StartSampling
+     /tmp/ccICigVb.s:1340   .text.HAL_ADC_StopSampling:00000000 $t
+     /tmp/ccICigVb.s:1346   .text.HAL_ADC_StopSampling:00000000 HAL_ADC_StopSampling
+     /tmp/ccICigVb.s:1370   .text.HAL_ADC_ConvCpltCallback:00000000 $t
+     /tmp/ccICigVb.s:1376   .text.HAL_ADC_ConvCpltCallback:00000000 HAL_ADC_ConvCpltCallback
+     /tmp/ccICigVb.s:1391   .text.HAL_ADC_ConvHalfCpltCallback:00000000 $t
+     /tmp/ccICigVb.s:1397   .text.HAL_ADC_ConvHalfCpltCallback:00000000 HAL_ADC_ConvHalfCpltCallback
+     /tmp/ccICigVb.s:1412   .text.ADC_DMAHalfConvCplt:00000000 $t
+     /tmp/ccICigVb.s:1418   .text.ADC_DMAHalfConvCplt:00000000 ADC_DMAHalfConvCplt
+     /tmp/ccICigVb.s:1445   .text.HAL_ADC_LevelOutOfWindowCallback:00000000 $t
+     /tmp/ccICigVb.s:1451   .text.HAL_ADC_LevelOutOfWindowCallback:00000000 HAL_ADC_LevelOutOfWindowCallback
+     /tmp/ccICigVb.s:1466   .text.HAL_ADC_ErrorCallback:00000000 $t
+     /tmp/ccICigVb.s:1472   .text.HAL_ADC_ErrorCallback:00000000 HAL_ADC_ErrorCallback
+     /tmp/ccICigVb.s:1487   .text.HAL_ADC_IRQHandler:00000000 $t
+     /tmp/ccICigVb.s:1493   .text.HAL_ADC_IRQHandler:00000000 HAL_ADC_IRQHandler
+     /tmp/ccICigVb.s:2066   .text.HAL_ADC_IRQHandler:00000274 $d
+     /tmp/ccICigVb.s:2071   .text.HAL_ADC_IRQHandler:0000027c $t
+     /tmp/ccICigVb.s:2092   .text.ADC_DMAConvCplt:00000000 $t
+     /tmp/ccICigVb.s:2098   .text.ADC_DMAConvCplt:00000000 ADC_DMAConvCplt
+     /tmp/ccICigVb.s:2233   .text.ADC_DMAError:00000000 $t
+     /tmp/ccICigVb.s:2239   .text.ADC_DMAError:00000000 ADC_DMAError
+     /tmp/ccICigVb.s:2273   .text.HAL_ADC_ConfigChannel:00000000 $t
+     /tmp/ccICigVb.s:2279   .text.HAL_ADC_ConfigChannel:00000000 HAL_ADC_ConfigChannel
+     /tmp/ccICigVb.s:3389   .text.HAL_ADC_ConfigChannel:00000334 $d
+     /tmp/ccICigVb.s:3407   .text.HAL_ADC_ConfigChannel:00000354 $t
+     /tmp/ccICigVb.s:3725   .text.HAL_ADC_ConfigChannel:00000454 $d
+     /tmp/ccICigVb.s:3733   .text.HAL_ADC_AnalogWDGConfig:00000000 $t
+     /tmp/ccICigVb.s:3739   .text.HAL_ADC_AnalogWDGConfig:00000000 HAL_ADC_AnalogWDGConfig
+     /tmp/ccICigVb.s:4508   .text.HAL_ADC_AnalogWDGConfig:000002e0 $d
+     /tmp/ccICigVb.s:4515   .text.HAL_ADC_GetState:00000000 $t
+     /tmp/ccICigVb.s:4521   .text.HAL_ADC_GetState:00000000 HAL_ADC_GetState
+     /tmp/ccICigVb.s:4540   .text.HAL_ADC_GetError:00000000 $t
+     /tmp/ccICigVb.s:4546   .text.HAL_ADC_GetError:00000000 HAL_ADC_GetError
+     /tmp/ccICigVb.s:4565   .text.ADC_ConversionStop:00000000 $t
+ARM GAS  /tmp/ccICigVb.s 			page 372
+
+
+     /tmp/ccICigVb.s:4571   .text.ADC_ConversionStop:00000000 ADC_ConversionStop
+     /tmp/ccICigVb.s:4897   .text.ADC_ConversionStop:00000100 $d
+     /tmp/ccICigVb.s:4902   .text.ADC_Enable:00000000 $t
+     /tmp/ccICigVb.s:4908   .text.ADC_Enable:00000000 ADC_Enable
+     /tmp/ccICigVb.s:5072   .text.ADC_Enable:00000094 $d
+     /tmp/ccICigVb.s:5077   .text.HAL_ADC_Start:00000000 $t
+     /tmp/ccICigVb.s:5083   .text.HAL_ADC_Start:00000000 HAL_ADC_Start
+     /tmp/ccICigVb.s:5302   .text.HAL_ADC_Start:000000f4 $d
+     /tmp/ccICigVb.s:5308   .text.HAL_ADC_Start_IT:00000000 $t
+     /tmp/ccICigVb.s:5314   .text.HAL_ADC_Start_IT:00000000 HAL_ADC_Start_IT
+     /tmp/ccICigVb.s:5630   .text.HAL_ADC_Start_IT:00000188 $d
+     /tmp/ccICigVb.s:5636   .text.HAL_ADC_Start_DMA:00000000 $t
+     /tmp/ccICigVb.s:5642   .text.HAL_ADC_Start_DMA:00000000 HAL_ADC_Start_DMA
+     /tmp/ccICigVb.s:5871   .text.HAL_ADC_Start_DMA:000000f0 $d
+     /tmp/ccICigVb.s:5880   .text.ADC_Disable:00000000 $t
+     /tmp/ccICigVb.s:5886   .text.ADC_Disable:00000000 ADC_Disable
+     /tmp/ccICigVb.s:6054   .text.HAL_ADC_DeInit:00000000 $t
+     /tmp/ccICigVb.s:6060   .text.HAL_ADC_DeInit:00000000 HAL_ADC_DeInit
+     /tmp/ccICigVb.s:6338   .text.HAL_ADC_DeInit:000001a0 $d
+     /tmp/ccICigVb.s:6347   .text.HAL_ADC_Stop:00000000 $t
+     /tmp/ccICigVb.s:6353   .text.HAL_ADC_Stop:00000000 HAL_ADC_Stop
+     /tmp/ccICigVb.s:6430   .text.HAL_ADC_Stop_IT:00000000 $t
+     /tmp/ccICigVb.s:6436   .text.HAL_ADC_Stop_IT:00000000 HAL_ADC_Stop_IT
+     /tmp/ccICigVb.s:6518   .text.HAL_ADC_Stop_DMA:00000000 $t
+     /tmp/ccICigVb.s:6524   .text.HAL_ADC_Stop_DMA:00000000 HAL_ADC_Stop_DMA
+
+UNDEFINED SYMBOLS
+SystemCoreClock
+HAL_GetTick
+HAL_ADCEx_EndOfSamplingCallback
+HAL_ADCEx_InjectedConvCpltCallback
+HAL_ADCEx_LevelOutOfWindow2Callback
+HAL_ADCEx_LevelOutOfWindow3Callback
+HAL_ADCEx_InjectedQueueOverflowCallback
+HAL_DMA_Start_IT
+HAL_DMA_Abort
diff --git a/squeow_sw/build/stm32g4xx_hal_adc.o b/squeow_sw/build/stm32g4xx_hal_adc.o
new file mode 100644
index 0000000000000000000000000000000000000000..b5b14b92ce2133060c9e90745e393e1565f09fb6
GIT binary patch
literal 78924
zcmeFadwf*Y^*4OZoSDf?W^y4H2;q`R29#?O5>V6#Aro%l7LuS`)DS|#L~_9-fYu8E
z@rKr-pg*ftthGLBt#_@~OA)LUtv1oxS}!$KYm{n@f|jb4=lfmzoHJ(<^!L2)@AE!?
zz30O|d+)W@UVH7e*Is*_eddHMvlq_MbzQSAT^pyxYMQotoYXv1g<zbvK&#MFA1*8m
zB;KSM{Xyf|<$8aPzN9}V82n2AX3W80aNnWrYj%__Jm_-mt330Fd%=desSjrqE=VT5
z8}!c{axY!dpJ3C+(`t_d3!gcppP~2bhVhU6M(`gO2P=<ED$MP7EzUo@dUW_;vN5DI
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HcmV?d00001

diff --git a/squeow_sw/build/stm32g4xx_hal_adc_ex.d b/squeow_sw/build/stm32g4xx_hal_adc_ex.d
new file mode 100644
index 0000000..e2b3ce6
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_adc_ex.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_adc_ex.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_adc_ex.lst b/squeow_sw/build/stm32g4xx_hal_adc_ex.lst
new file mode 100644
index 0000000..a250384
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_adc_ex.lst
@@ -0,0 +1,17638 @@
+ARM GAS  /tmp/cc3JIfda.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_adc_ex.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c"
+  20              		.section	.text.LL_ADC_SetCalibrationFactor,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	LL_ADC_SetCalibrationFactor:
+  27              	.LVL0:
+  28              	.LFB139:
+  29              		.file 2 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"
+   1:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @file    stm32g4xx_ll_adc.h
+   4:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief   Header file of ADC LL module.
+   6:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ******************************************************************************
+   7:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @attention
+   8:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+   9:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * Copyright (c) 2019 STMicroelectronics.
+  10:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * All rights reserved.
+  11:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+  12:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * in the root directory of this software component.
+  14:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+  16:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ******************************************************************************
+  17:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+  18:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  19:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #ifndef STM32G4xx_LL_ADC_H
+  21:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define STM32G4xx_LL_ADC_H
+  22:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  23:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #ifdef __cplusplus
+  24:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** extern "C" {
+  25:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif
+  26:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  27:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #include "stm32g4xx.h"
+  29:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ARM GAS  /tmp/cc3JIfda.s 			page 2
+
+
+  30:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @addtogroup STM32G4xx_LL_Driver
+  31:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+  32:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+  33:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  34:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
+  35:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  36:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL ADC
+  37:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+  38:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+  39:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  40:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  43:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Private constants ---------------------------------------------------------*/
+  44:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_Private_Constants ADC Private Constants
+  45:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+  46:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+  47:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  48:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC group regular sequencer:                             */
+  49:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
+  50:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - sequencer register offset                                                */
+  51:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - sequencer rank bits position into the selected register                  */
+  52:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  53:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal register offset for ADC group regular sequencer configuration */
+  54:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (offset placed into a spare area of literal definition) */
+  55:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SQR1_REGOFFSET                 (0x00000000UL)
+  56:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SQR2_REGOFFSET                 (0x00000100UL)
+  57:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SQR3_REGOFFSET                 (0x00000200UL)
+  58:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SQR4_REGOFFSET                 (0x00000300UL)
+  59:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  60:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
+  61:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                             | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+  62:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SQRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_
+  63:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+  64:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  65:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of ADC group regular sequencer bits information to be inserted  */
+  66:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* into ADC group regular sequencer ranks literals definition.                */
+  67:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ1_Pos)
+  68:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ2_Pos)
+  69:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ3_Pos)
+  70:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ4_Pos)
+  71:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ5_Pos)
+  72:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ6_Pos)
+  73:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ7_Pos)
+  74:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ8_Pos)
+  75:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ9_Pos)
+  76:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
+  77:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
+  78:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
+  79:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
+  80:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
+  81:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
+  82:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
+  83:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  84:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  85:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  86:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC group injected sequencer:                            */
+ARM GAS  /tmp/cc3JIfda.s 			page 3
+
+
+  87:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
+  88:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - data register offset                                                     */
+  89:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - sequencer rank bits position into the selected register                  */
+  90:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  91:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal register offset for ADC group injected data register */
+  92:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (offset placed into a spare area of literal definition) */
+  93:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_JDR1_REGOFFSET                 (0x00000000UL)
+  94:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_JDR2_REGOFFSET                 (0x00000100UL)
+  95:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_JDR3_REGOFFSET                 (0x00000200UL)
+  96:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_JDR4_REGOFFSET                 (0x00000300UL)
+  97:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+  98:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
+  99:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                             | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+ 100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+ 101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_JDRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_
+ 102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of ADC group injected sequencer bits information to be inserted */
+ 104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* into ADC group injected sequencer ranks literals definition.               */
+ 105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ1_Pos)
+ 106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ2_Pos)
+ 107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ3_Pos)
+ 108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ4_Pos)
+ 109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC group regular trigger:                               */
+ 113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
+ 114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - regular trigger source                                                   */
+ 115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - regular trigger edge                                                     */
+ 116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (
+ 117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Mask containing trigger source masks for each of possible                  */
+ 119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+ 120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+ 121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U *
+ 122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_CFGR_EXTSEL)                            << (4U *
+ 123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_CFGR_EXTSEL)                            << (4U *
+ 124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_CFGR_EXTSEL)                            << (4U *
+ 125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Mask containing trigger edge masks for each of possible                    */
+ 127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+ 128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+ 129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 
+ 130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 
+ 131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 
+ 132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 
+ 133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of ADC group regular trigger bits information.                  */
+ 135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (ADC_CFGR_EXTSEL_Pos)
+ 136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (ADC_CFGR_EXTEN_Pos)
+ 137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC group injected trigger:                              */
+ 141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
+ 142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - injected trigger source                                                  */
+ 143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - injected trigger edge                                                    */
+ARM GAS  /tmp/cc3JIfda.s 			page 4
+
+
+ 144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (
+ 145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Mask containing trigger source masks for each of possible                  */
+ 147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+ 148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+ 149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U
+ 150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_JSQR_JEXTSEL)                             << (4U
+ 151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_JSQR_JEXTSEL)                             << (4U
+ 152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_JSQR_JEXTSEL)                             << (4U
+ 153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Mask containing trigger edge masks for each of possible                    */
+ 155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+ 156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+ 157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U *
+ 158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U *
+ 159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U *
+ 160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U *
+ 161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of ADC group injected trigger bits information.                 */
+ 163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (ADC_JSQR_JEXTSEL_Pos)
+ 164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (ADC_JSQR_JEXTEN_Pos)
+ 165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC channel:                                             */
+ 172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
+ 173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - channel identifier defined by number                                     */
+ 174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - channel identifier defined by bitfield                                   */
+ 175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - channel differentiation between external channels (connected to          */
+ 176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*   GPIO pins) and internal channels (connected to internal paths)           */
+ 177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - channel sampling time defined by SMPRx register offset                   */
+ 178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*   and SMPx bits positions into SMPRx register                              */
+ 179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)
+ 180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)
+ 181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
+ 182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MA
+ 183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                             | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+ 184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+ 185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMB
+ 186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Channel differentiation between external and internal channels */
+ 188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */
+ 189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_INTERNAL_CH_2       (0x00080000UL) /* Marker of internal channel for other A
+ 190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH
+ 191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal register offset for ADC channel sampling time configuration */
+ 193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (offset placed into a spare area of literal definition) */
+ 194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SMPR1_REGOFFSET                (0x00000000UL)
+ 195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SMPR2_REGOFFSET                (0x02000000UL)
+ 196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+ 197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SMPRX_REGOFFSET_POS            (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CH
+ 198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000UL)
+ 200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Value equivalent to bitfield "ADC_CH
+ARM GAS  /tmp/cc3JIfda.s 			page 5
+
+
+ 201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of channels ID number information to be inserted into           */
+ 203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* channels literals definition.                                              */
+ 204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_0_NUMBER               (0x00000000UL)
+ 205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_1_NUMBER               (ADC_CFGR_AWD1CH_0)
+ 206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_2_NUMBER               (ADC_CFGR_AWD1CH_1)
+ 207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_3_NUMBER               (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+ 208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_4_NUMBER               (ADC_CFGR_AWD1CH_2)
+ 209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_5_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+ 210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_6_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+ 211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_7_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH
+ 212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_8_NUMBER               (ADC_CFGR_AWD1CH_3)
+ 213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_9_NUMBER               (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
+ 214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_10_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
+ 215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_11_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH
+ 216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_12_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
+ 217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_13_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH
+ 218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_14_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH
+ 219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_15_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
+ 220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                             ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+ 221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4)
+ 222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
+ 223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
+ 224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of channels ID bitfield information to be inserted into         */
+ 226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* channels literals definition.                                              */
+ 227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)
+ 228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)
+ 229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)
+ 230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)
+ 231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)
+ 232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)
+ 233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)
+ 234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)
+ 235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)
+ 236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)
+ 237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)
+ 238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)
+ 239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)
+ 240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)
+ 241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)
+ 242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)
+ 243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
+ 244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
+ 245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
+ 246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Definition of channels sampling time information to be inserted into       */
+ 248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* channels literals definition.                                              */
+ 249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOF
+ 250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOF
+ 251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOF
+ 252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOF
+ 253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOF
+ 254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOF
+ 255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOF
+ 256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOF
+ 257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOF
+ARM GAS  /tmp/cc3JIfda.s 			page 6
+
+
+ 258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOF
+ 259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOF
+ 260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOF
+ 261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOF
+ 262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOF
+ 263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOF
+ 264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOF
+ 265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOF
+ 266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOF
+ 267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOF
+ 268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC mode single or differential ended:                   */
+ 271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
+ 272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* the relevant bits for:                                                     */
+ 273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (concatenation of multiple bits used in different registers)               */
+ 274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - ADC calibration: calibration start, calibration factor get or set        */
+ 275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - ADC channels: set each ADC channel ending mode                           */
+ 276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)
+ 277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
+ 278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFS
+ 279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* B
+ 280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000UL)                           /* Selection o
+ 281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16UL)                                   /* Selection o
+ 282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bi
+ 283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC analog watchdog:                                     */
+ 285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
+ 286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (concatenation of multiple bits used in different analog watchdogs,        */
+ 287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (feature of several watchdogs not available on all STM32 families)).       */
+ 288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - analog watchdog 1: monitored channel defined by number,                  */
+ 289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*   selection of ADC group (ADC groups regular and-or injected).             */
+ 290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
+ 291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*   selection on groups.                                                     */
+ 292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal register offset for ADC analog watchdog channel configuration */
+ 294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)
+ 295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)
+ 296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)
+ 297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
+ 299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
+ 300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
+ 301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)
+ 302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD
+ 304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | 
+ 306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
+ 307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+ 308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_CRX_REGOFFSET_POS          (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_
+ 310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal register offset for ADC analog watchdog threshold configuration */
+ 312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
+ 313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
+ 314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)
+ARM GAS  /tmp/cc3JIfda.s 			page 7
+
+
+ 315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD
+ 316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC_
+ 317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TRX_BIT_HIGH_MASK          (0x00010000UL)                   /* Selection of 1 bit t
+ 318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TRX_BIT_HIGH_POS           (16UL)                           /* Selection of 1 bit t
+ 319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_AWD_TRX_BIT_HIGH_SHIFT4        (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD
+ 320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal mask for ADC offset:                                              */
+ 322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal register offset for ADC offset number configuration */
+ 323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_OFR1_REGOFFSET                 (0x00000000UL)
+ 324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_OFR2_REGOFFSET                 (0x00000001UL)
+ 325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_OFR3_REGOFFSET                 (0x00000002UL)
+ 326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_OFR4_REGOFFSET                 (0x00000003UL)
+ 327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
+ 328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                             | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+ 329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* ADC registers bits positions */
+ 332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CFGR_RES_BITOFFSET_POS         (ADC_CFGR_RES_Pos)
+ 333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (ADC_CFGR_AWD1SGL_Pos)
+ 334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CFGR_AWD1EN_BITOFFSET_POS      (ADC_CFGR_AWD1EN_Pos)
+ 335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (ADC_CFGR_JAWD1EN_Pos)
+ 336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_TR1_HT1_BITOFFSET_POS          (ADC_TR1_HT1_Pos)
+ 337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* ADC registers bits groups */
+ 340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JA
+ 341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* ADC internal channels related definitions */
+ 344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Internal voltage reference VrefInt */
+ 345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage referen
+ 346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define VREFINT_CAL_VREF                   (3000UL)                     /* Analog voltage reference
+ 347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Temperature sensor */
+ 348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sen
+ 349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sen
+ 350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Internal temperature sen
+ 351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define TEMPSENSOR_CAL2_TEMP               (130L)                       /* Internal temperature sen
+ 352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define TEMPSENSOR_CAL_VREFANALOG          (3000UL)                     /* Analog voltage reference
+ 353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Private macros ------------------------------------------------------------*/
+ 360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_Private_Macros ADC Private Macros
+ 361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Driver macro reserved for internal use: set a pointer to
+ 366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a register from a register basis from which an offset
+ 367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is applied.
+ 368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __REG__ Register basis from which the offset is applied.
+ 369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ 370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Pointer to register address
+ 371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ARM GAS  /tmp/cc3JIfda.s 			page 8
+
+
+ 372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
+ 373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+ 374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Exported types ------------------------------------------------------------*/
+ 381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(USE_FULL_LL_DRIVER)
+ 382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+ 383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Structure definition of some features of ADC common parameters
+ 388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and multimode
+ 389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (all ADC instances belonging to the same ADC common instance).
+ 390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
+ 391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is conditioned to ADC instances state (all ADC instances
+ 392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sharing the same ADC common instance):
+ 393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         All ADC instances sharing the same ADC common instance must be
+ 394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         disabled.
+ 395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** typedef struct
+ 397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and 
+ 399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_COMMON
+ 400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              @note On this STM32 series, if ADC group injected is u
+ 401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    clock ratio constraints between ADC clock and AH
+ 402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    must be respected. Refer to reference manual.
+ 403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independ
+ 408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_
+ 409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t MultiDMATransfer;            /*!< Set ADC multimode conversion data transfer: no transfe
+ 413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_
+ 414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.
+ 418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_
+ 419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+ 422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** } LL_ADC_CommonInitTypeDef;
+ 424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Structure definition of some features of ADC instance.
+ 427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   These parameters have an impact on ADC scope: ADC instance.
+ 428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Affects both group regular and group injected (availability
+ARM GAS  /tmp/cc3JIfda.s 			page 9
+
+
+ 429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of ADC group injected depends on STM32 families).
+ 430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to corresponding unitary functions into
+ 431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+ 432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The setting of these parameters by function @ref LL_ADC_Init()
+ 433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is conditioned to ADC state:
+ 434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instance must be disabled.
+ 435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This condition is applied to all ADC features, for efficiency
+ 436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and compatibility over all STM32 families. However, the different
+ 437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         features can be set under different ADC state conditions
+ 438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (setting possible with ADC enabled without conversion on going,
+ 439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC enabled with conversion on going, ...)
+ 440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Each feature can be updated afterwards with a unitary function
+ 441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and potentially with ADC in a different state than disabled,
+ 442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         refer to description of each function for setting
+ 443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         conditioned to ADC state.
+ 444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** typedef struct
+ 446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t Resolution;                  /*!< Set ADC resolution.
+ 448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_RESOLU
+ 449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
+ 453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_DATA_A
+ 454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t LowPowerMode;                /*!< Set ADC low power mode.
+ 458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_LP_MOD
+ 459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** } LL_ADC_InitTypeDef;
+ 463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Structure definition of some features of ADC group regular.
+ 466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   These parameters have an impact on ADC scope: ADC group regular.
+ 467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to corresponding unitary functions into
+ 468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ 469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (functions with prefix "REG").
+ 470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
+ 471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is conditioned to ADC state:
+ 472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instance must be disabled.
+ 473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This condition is applied to all ADC features, for efficiency
+ 474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and compatibility over all STM32 families. However, the different
+ 475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         features can be set under different ADC state conditions
+ 476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (setting possible with ADC enabled without conversion on going,
+ 477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC enabled with conversion on going, ...)
+ 478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Each feature can be updated afterwards with a unitary function
+ 479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and potentially with ADC in a different state than disabled,
+ 480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         refer to description of each function for setting
+ 481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         conditioned to ADC state.
+ 482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** typedef struct
+ 484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: inter
+ARM GAS  /tmp/cc3JIfda.s 			page 10
+
+
+ 486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_REG_TR
+ 487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              @note On this STM32 series, setting trigger source to 
+ 488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    (default setting for compatibility with some ADC
+ 489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    In case of need to modify trigger edge, use func
+ 490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
+ 494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_REG_SE
+ 495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: se
+ 499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_REG_SE
+ 500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              @note This parameter has an effect only if group regul
+ 501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    (scan length of 2 ranks or more).
+ 502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regula
+ 506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_REG_CO
+ 507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              Note: It is not possible to enable both ADC group regu
+ 508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no tra
+ 512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_REG_DM
+ 513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
+ 517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              data preserved or overwritten.
+ 518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_REG_OV
+ 519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** } LL_ADC_REG_InitTypeDef;
+ 523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Structure definition of some features of ADC group injected.
+ 526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   These parameters have an impact on ADC scope: ADC group injected.
+ 527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to corresponding unitary functions into
+ 528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ 529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (functions with prefix "INJ").
+ 530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
+ 531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is conditioned to ADC state:
+ 532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instance must be disabled.
+ 533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This condition is applied to all ADC features, for efficiency
+ 534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and compatibility over all STM32 families. However, the different
+ 535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         features can be set under different ADC state conditions
+ 536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (setting possible with ADC enabled without conversion on going,
+ 537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC enabled with conversion on going, ...)
+ 538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Each feature can be updated afterwards with a unitary function
+ 539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and potentially with ADC in a different state than disabled,
+ 540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         refer to description of each function for setting
+ 541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         conditioned to ADC state.
+ 542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ARM GAS  /tmp/cc3JIfda.s 			page 11
+
+
+ 543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** typedef struct
+ 544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: inte
+ 546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TR
+ 547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              @note On this STM32 series, setting trigger source to 
+ 548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    (default setting for compatibility with some ADC
+ 549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    In case of need to modify trigger edge, use func
+ 550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
+ 554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SE
+ 555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: s
+ 559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SE
+ 560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              @note This parameter has an effect only if group injec
+ 561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    (scan length of 2 ranks or more).
+ 562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent
+ 566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TR
+ 567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              Note: This parameter must be set to set to independent
+ 568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              This feature can be modified afterwards using unitary 
+ 570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** } LL_ADC_INJ_InitTypeDef;
+ 572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* USE_FULL_LL_DRIVER */
+ 577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Exported constants --------------------------------------------------------*/
+ 579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+ 580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_FLAG ADC flags
+ 584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief    Flags defines which can be used with LL_ADC_ReadReg function
+ 585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
+ 588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end o
+ 589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end o
+ 590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overr
+ 591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end o
+ 592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end 
+ 593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end 
+ 594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected cont
+ 595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 *
+ 596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 *
+ 597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 *
+ 598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master in
+ARM GAS  /tmp/cc3JIfda.s 			page 12
+
+
+ 600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave ins
+ 601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master gr
+ 602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave gro
+ 603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master gr
+ 604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave gro
+ 605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master gr
+ 606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave gro
+ 607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master gr
+ 608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave gro
+ 609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master gr
+ 610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave gro
+ 611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master gr
+ 612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave gro
+ 613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master gr
+ 614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave gro
+ 615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master an
+ 616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave ana
+ 617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master an
+ 618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave ana
+ 619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master an
+ 620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave ana
+ 621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+ 622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+ 627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
+ 628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance re
+ 631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regul
+ 632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regul
+ 633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regul
+ 634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regul
+ 635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injec
+ 636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injec
+ 637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injec
+ 638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watc
+ 639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watc
+ 640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watc
+ 641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
+ 646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* List of ADC registers intended to be used (most commonly) with             */
+ 649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* DMA transfer.                                                              */
+ 650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
+ 651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000UL) /* ADC group regular conversion data re
+ 652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    (0x00000001UL) /* ADC group regular conversion data re
+ 654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+ 655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ARM GAS  /tmp/cc3JIfda.s 			page 13
+
+
+ 657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
+ 660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*
+ 663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*
+ 664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*
+ 665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                                        /*
+ 666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*
+ 667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*
+ 668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*
+ 669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*
+ 670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*
+ 671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*
+ 672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*
+ 673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*
+ 674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*
+ 675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*
+ 676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*
+ 677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
+ 682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Note: Other measurement paths to internal channels may be available        */
+ 685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       (connections to other peripherals).                                  */
+ 686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       If they are not listed below, they do not require any specific       */
+ 687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       path enable. In this case, Access to measurement path is done        */
+ 688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       only by selecting the corresponding ADC internal channel.            */
+ 689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)         /*!< ADC measurement paths all di
+ 690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to inte
+ 691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_VSENSESEL)    /*!< ADC measurement path to inte
+ 692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATSEL)      /*!< ADC measurement path to inte
+ 693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
+ 698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_RESOLUTION_12B              (0x00000000UL)                      /*!< ADC resolution 
+ 701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 
+ 702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution 
+ 703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution 
+ 704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
+ 709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000UL)         /*!< ADC conversion data alignmen
+ 712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR_ALIGN)       /*!< ADC conversion data alignmen
+ 713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/cc3JIfda.s 			page 14
+
+
+ 714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
+ 718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_LP_MODE_NONE                (0x00000000UL)                      /*!< No ADC low powe
+ 721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power m
+ 722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number
+ 727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel
+ 730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel
+ 731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel
+ 732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel
+ 733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
+ 738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_DISABLE              (0x00000000UL)         /*!< ADC offset disabled (among A
+ 741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_ENABLE               (ADC_OFR1_OFFSET1_EN)  /*!< ADC offset enabled (among AD
+ 742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
+ 747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_SIGN_NEGATIVE        (0x00000000UL)       /*!< ADC offset is negative (among 
+ 750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_SIGN_POSITIVE        (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among 
+ 751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
+ 756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_SATURATION_DISABLE   (0x00000000UL)          /*!< ADC offset saturation is di
+ 759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OFFSET_SATURATION_ENABLE    (ADC_OFR1_SATEN)        /*!< ADC offset saturation is en
+ 760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
+ 764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_GROUP_REGULAR               (0x00000001UL) /*!< ADC group regular (available on all 
+ 767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_GROUP_INJECTED              (0x00000002UL) /*!< ADC group injected (not available on
+ 768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL) /*!< ADC both groups regular and injected
+ 769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ARM GAS  /tmp/cc3JIfda.s 			page 15
+
+
+ 771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
+ 774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNE
+ 777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNE
+ 778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNE
+ 779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNE
+ 780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNE
+ 781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNE
+ 782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNE
+ 783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNE
+ 784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNE
+ 785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNE
+ 786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNE
+ 787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNE
+ 788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNE
+ 789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNE
+ 790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNE
+ 791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNE
+ 792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNE
+ 793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNE
+ 794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNE
+ 795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_TEMPSENSOR_ADC1     (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_TEMPSENSOR_ADC5     (LL_ADC_CHANNEL_4  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP1             (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP2             (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CH
+ 801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP3_ADC2        (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CH
+ 802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP3_ADC3        (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CH
+ 803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP4             (LL_ADC_CHANNEL_5  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP5             (LL_ADC_CHANNEL_3  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
+ 805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_CHANNEL_VOPAMP6             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CH
+ 806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
+ 811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000UL)                                          
+ 814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger internal: SW start.
+ 815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EX
+ 816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EX
+ 818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                         
+ 820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)     
+ 823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)     
+ 826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL
+ARM GAS  /tmp/cc3JIfda.s 			page 16
+
+
+ 828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_CH1       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EX
+ 833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)     
+ 836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)     
+ 839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM3_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                         
+ 841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM3_CH4       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EX
+ 847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM4_CH1       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EX
+ 849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EX
+ 852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL
+ 857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL
+ 859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)     
+ 861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM8_CH1       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EX
+ 863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO     (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)     
+ 868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, TIM20 is not available on al
+ 870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EX
+ 871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, TIM20 is not available on al
+ 873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM20_CH1      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EX
+ 874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, TIM20 is not available on al
+ 876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM20_CH2      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL
+ 877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM20_CH3      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EX
+ 880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ARM GAS  /tmp/cc3JIfda.s 			page 17
+
+
+ 885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL
+ 886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EX
+ 892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL
+ 895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EX
+ 898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL
+ 901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL
+ 904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL
+ 907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL
+ 910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+ 912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EX
+ 913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2     (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EX
+ 916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+ 918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_LPTIM_OUT      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL
+ 919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group regular conversion trigger from external perip
+ 920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
+ 925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group r
+ 928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group r
+ 929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group r
+ 930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE  ADC group regular - Sampling mode
+ 935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SAMPLING_MODE_NORMAL               (0x00000000UL)       /*!< ADC conversions sam
+ 938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SAMPLING_MODE_BULB                 (ADC_CFGR2_BULB)     /*!< ADC conversions sam
+ 939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                                                 Note: First convers
+ 940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED    (ADC_CFGR2_SMPTRIG)  /*!< ADC conversions sam
+ 941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                                                  Trigger rising edg
+ARM GAS  /tmp/cc3JIfda.s 			page 18
+
+
+ 942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                                                  Trigger falling ed
+ 943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
+ 948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)          /*!< ADC conversions are perform
+ 951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are perform
+ 952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
+ 957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000UL)                        /*!< ADC conversio
+ 960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                  ADC_CFGR_DMAEN)    /*!< ADC conversio
+ 961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)    /*!< ADC conversio
+ 962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_SMPR1_SMPPLUS)
+ 967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configur
+ 968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT      (0x00000000UL)      /*!< ADC sampling time let to d
+ 971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling ti
+ 972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif
+ 976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion d
+ 978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)         /*!< ADC group regular behavior i
+ 981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior i
+ 982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ 983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ 984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
+ 987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ 988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ 989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000UL)                                          
+ 990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L
+ 991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1             
+ 992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L
+ 993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                            
+ 994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L
+ 995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1             
+ 996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L
+ 997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                           
+ 998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L
+ARM GAS  /tmp/cc3JIfda.s 			page 19
+
+
+ 999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1             
+1000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L
+1001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                            
+1002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L
+1003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1             
+1004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L
+1005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
+1010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                                          
+1013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                       
+1014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISC
+1015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                
+1016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISC
+1017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                     
+1018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISC
+1019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                
+1020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISC
+1021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
+1026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
+1029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
+1030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
+1031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
+1032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
+1033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
+1034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
+1035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
+1036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
+1037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS
+1038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS
+1039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS
+1040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS
+1041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS
+1042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS
+1043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS
+1044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
+1049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000UL)                                          
+1052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger internal: SW start
+1053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         
+1054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    
+ARM GAS  /tmp/cc3JIfda.s 			page 20
+
+
+1056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXT
+1058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    
+1061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    
+1063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_
+1065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_
+1068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXT
+1073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    
+1076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_
+1079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    
+1081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_
+1084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_
+1091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_
+1093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_
+1095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXT
+1098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM16_CH1      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO     (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    
+1105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, TIM20 is not available on al
+1107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2    (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_
+1108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, TIM20 is not available on al
+1110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_
+1111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Trigger available only on ADC3/4/5 instances. On this ST
+ARM GAS  /tmp/cc3JIfda.s 			page 21
+
+
+1113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_
+1114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Trigger available only on ADC1/2 instances. On this STM3
+1116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXT
+1120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_
+1126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_
+1138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10    (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, HRTIM is not available on al
+1146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXT
+1147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_
+1150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            Note: On this STM32 series, this trigger is available on
+1152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXT
+1153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                            ADC group injected conversion trigger from external peri
+1154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
+1159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group i
+1162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group i
+1163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group i
+1164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
+1169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+ARM GAS  /tmp/cc3JIfda.s 			page 22
+
+
+1170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000UL)         /*!< ADC group injected conversio
+1172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversio
+1173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode
+1178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL)         /* Group injected sequence co
+1181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence co
+1182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence co
+1183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
+1188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                  /*!< ADC group injected 
+1191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected 
+1192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected 
+1193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected 
+1194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
+1199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000UL)         /*!< ADC group injected sequencer
+1202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer
+1203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
+1208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
+1211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
+1212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
+1213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)
+1214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+1219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000UL)                                          
+1222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_6CYCLES_5      (                                        ADC_SMPR2_SMP10
+1223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_12CYCLES_5     (                    ADC_SMPR2_SMP10_1                  
+1224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_24CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10
+1225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2                                      
+1226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10
+ARM GAS  /tmp/cc3JIfda.s 			page 23
+
+
+1227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                  
+1228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10
+1229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
+1234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< A
+1237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< A
+1238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< A
+1239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+1244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!<
+1247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!<
+1248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!<
+1249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
+1254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_DISABLE                 (0x00000000UL)                                          
+1257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                              
+1258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JA
+1259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JA
+1260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)              
+1261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)              
+1264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)              
+1267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)              
+1270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)              
+1273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)              
+1276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)              
+1279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)              
+1282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+ARM GAS  /tmp/cc3JIfda.s 			page 24
+
+
+1284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)              
+1285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)              
+1288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)              
+1291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)              
+1294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)              
+1297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)              
+1300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)              
+1303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)              
+1306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)              
+1309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)              
+1312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)              
+1315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JA
+1317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)   
+1318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | 
+1319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | 
+1320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG       ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_M
+1321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_M
+1322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_M
+1323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG       ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_M
+1324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_M
+1325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_M
+1326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)   
+1327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | 
+1328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | 
+1329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP1_REG          ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK)   
+1330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP1_INJ          ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) | 
+1331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) | 
+1332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP2_REG          ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK)   
+1333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP2_INJ          ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) | 
+1334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) | 
+1335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK)   
+1336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) | 
+1337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) | 
+1338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK)   
+1339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) | 
+1340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) | 
+ARM GAS  /tmp/cc3JIfda.s 			page 25
+
+
+1341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP4_REG          ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK)   
+1342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP4_INJ          ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) | 
+1343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP4_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) | 
+1344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP5_REG          ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK)   
+1345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP5_INJ          ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) | 
+1346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP5_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) | 
+1347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP6_REG          ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK)   
+1348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP6_INJ          ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) | 
+1349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_CH_VOPAMP6_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) | 
+1350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
+1355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1              ) /*!< ADC analog watchdog thr
+1358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_THRESHOLD_LOW           (              ADC_TR1_LT1) /*!< ADC analog watchdog thr
+1359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog bot
+1360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG  Analog watchdog - filtering config
+1365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_NONE          (0x00000000UL)                                          
+1368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_2SAMPLES      (                                        ADC_TR1_AWDFILT
+1369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_3SAMPLES      (                    ADC_TR1_AWDFILT_1                  
+1370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_4SAMPLES      (                    ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT
+1371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_5SAMPLES      (ADC_TR1_AWDFILT_2                                      
+1372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_6SAMPLES      (ADC_TR1_AWDFILT_2 |                     ADC_TR1_AWDFILT
+1373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_7SAMPLES      (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1                  
+1374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_AWD_FILTERING_8SAMPLES      (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT
+1375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
+1380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_DISABLE                 (0x00000000UL)                                        /*
+1383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*
+1384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*
+1385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*
+1386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*
+1387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
+1392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_REG_CONT                (0x00000000UL)         /*!< ADC oversampling discontinuo
+1395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuo
+1396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+ARM GAS  /tmp/cc3JIfda.s 			page 26
+
+
+1398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
+1401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_2                 (0x00000000UL)                                          
+1404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_4                 (                                      ADC_CFGR2_OVSR_0)
+1405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_8                 (                   ADC_CFGR2_OVSR_1                   )
+1406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_16                (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
+1407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2                                      )
+1408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2                    | ADC_CFGR2_OVSR_0)
+1409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1                   )
+1410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
+1411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift
+1416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                                          
+1419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                       
+1420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1 
+1421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 
+1422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                    
+1423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    
+1424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 
+1425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 
+1426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                       
+1427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+1432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode
+1433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_INDEPENDENT           (0x00000000UL)                                          
+1436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_SIMULT       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1       
+1437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_INTERL       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_
+1438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                 ADC_CCR_DUAL_2                  | ADC_
+1439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3                                   | ADC_
+1440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                   ADC_
+1441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                  ADC_CCR_DUAL_1       
+1442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                  ADC_CCR_DUAL_1 | ADC_
+1443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer
+1448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_REG_DMA_EACH_ADC        (0x00000000UL)                                     /*!
+1451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (                 ADC_CCR_MDMA_1                 ) /*!
+1452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B   (                 ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!
+1453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1                 ) /*!
+1454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B   (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!
+ARM GAS  /tmp/cc3JIfda.s 			page 27
+
+
+1455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
+1460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE   (0x00000000UL)                                          
+1463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES  (                                                      A
+1464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES  (                                    ADC_CCR_DELAY_1    
+1465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES  (                                    ADC_CCR_DELAY_1 | A
+1466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  (                  ADC_CCR_DELAY_2                      
+1467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (                  ADC_CCR_DELAY_2                   | A
+1468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1    
+1469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | A
+1470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (ADC_CCR_DELAY_3                                        
+1471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3                                     | A
+1472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1    
+1473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1 | A
+1474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave
+1479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimod
+1482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimod
+1483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimod
+1484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+1489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
+1492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,
+1493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         not timeout values.
+1494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         For details on delays values, refer to descriptions in source code
+1495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         above each literal definition.
+1496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
+1500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       not timeout values.                                                  */
+1501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       Timeout values for ADC operations are dependent to device clock      */
+1502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       configuration (system clock versus ADC clock),                       */
+1503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       and therefore must be defined in user application.                   */
+1504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       Indications for estimation of ADC timeout delays, for this           */
+1505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       STM32 series:                                                        */
+1506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       - ADC calibration time: maximum delay is 112/fADC.                   */
+1507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*         (refer to device datasheet, parameter "tCAL")                      */
+1508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       - ADC enable time: maximum delay is 1 conversion cycle.              */
+1509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*         (refer to device datasheet, parameter "tSTAB")                     */
+1510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
+1511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
+ARM GAS  /tmp/cc3JIfda.s 			page 28
+
+
+1512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*         cycles                                                             */
+1513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       - ADC conversion time: duration depending on ADC clock and ADC       */
+1514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*         configuration.                                                     */
+1515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*         (refer to device reference manual, section "Timing")               */
+1516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
+1518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Delay set to maximum value (refer to device datasheet,                     */
+1519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* parameter "tADCVREG_STUP").                                                */
+1520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Unit: us                                                                   */
+1521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)  /*!< Delay for ADC stabilization time (ADC vol
+1522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Delay for internal voltage reference stabilization time.                   */
+1524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Delay set to maximum value (refer to device datasheet,                     */
+1525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* parameter "tstart_vrefint").                                               */
+1526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Unit: us                                                                   */
+1527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DELAY_VREFINT_STAB_US           ( 12UL)  /*!< Delay for internal voltage reference s
+1528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Delay for temperature sensor stabilization time.                           */
+1530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Literal set to maximum value (refer to device datasheet,                   */
+1531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* parameter "tSTART").                                                       */
+1532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Unit: us                                                                   */
+1533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DELAY_TEMPSENSOR_STAB_US        (120UL)  /*!< Delay for temperature sensor stabiliza
+1534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Delay required between ADC end of calibration and ADC enable.              */
+1536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Note: On this STM32 series, a minimum number of ADC clock cycles           */
+1537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       are required between ADC end of calibration and ADC enable.          */
+1538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       Wait time can be computed in user application by waiting for the     */
+1539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       equivalent number of CPU cycles, by taking into account              */
+1540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       ratio of CPU clock versus ADC clock prescalers.                      */
+1541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Unit: ADC clock cycles.                                                    */
+1542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES   (  4UL)  /*!< Delay required between ADC end of cali
+1543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Exported macro ------------------------------------------------------------*/
+1554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+1555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+1559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Write a value in ADC register
+1564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __INSTANCE__ ADC Instance
+1565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __REG__ Register to be written
+1566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __VALUE__ Value to be written in the register
+1567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+1568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ARM GAS  /tmp/cc3JIfda.s 			page 29
+
+
+1569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE
+1570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Read a value in ADC register
+1573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __INSTANCE__ ADC Instance
+1574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __REG__ Register to be read
+1575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Register value
+1576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+1578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+1580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+1583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+1584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to get ADC channel number in decimal format
+1588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from literals LL_ADC_CHANNEL_x.
+1589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Example:
+1590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+1591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           will return decimal number "4".
+1592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The input can be a value from functions where a channel
+1593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number is returned, either defined with number
+1594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or with bitfield (only one bit must be set).
+1595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+1596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+1597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+1598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+1599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+1600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+1601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+1602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+1603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+1604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+1605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+1606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+1607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+1608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+1609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+1610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+1611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+1612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+1613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+1614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+1615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+1616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+1617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+1618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+1619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+1620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+1621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+1622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+1623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+1624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+1625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+ARM GAS  /tmp/cc3JIfda.s 			page 30
+
+
+1626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+1627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+1628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+1629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+1630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+1631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+1632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+1633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+1634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+1635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+1636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+1637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0 and Max_Data=18
+1638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
+1640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ?                               \
+1641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (                                                                                       \
+1642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
+1643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                                       \
+1644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    :                                                                                       \
+1645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (                                                                                       \
+1646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (uint32_t)POSITION_VAL((__CHANNEL__))                                               \
+1647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                                       \
+1648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+1649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+1652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from number in decimal format.
+1653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Example:
+1654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+1655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           will return a data equivalent to "LL_ADC_CHANNEL_4".
+1656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+1657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+1658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+1659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+1660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+1661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+1662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+1663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+1664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+1665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+1666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+1667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+1668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+1669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+1670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+1671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+1672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+1673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+1674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+1675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+1676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+1677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+1678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+1679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+1680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+1681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+1682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+ARM GAS  /tmp/cc3JIfda.s 			page 31
+
+
+1683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+1684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+1685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+1686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+1687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+1688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+1689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+1690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+1691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+1692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+1693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+1694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+1695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+1696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+1697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+1698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+1699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+1700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      comparison with internal channel parameter to be done
+1701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+1702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                             
+1704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__DECIMAL_NB__) <= 9UL) ?                                                                     
+1705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (                                                                                               
+1706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |     
+1707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                             |     
+1708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))      
+1709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                                               
+1710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    :                                                                                               
+1711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (                                                                                               
+1712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                   
+1713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                   
+1714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_PO
+1715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                                               
+1716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+1717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to determine whether the selected channel
+1720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         corresponds to literal definitions of driver.
+1721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The different literal definitions of ADC channels are:
+1722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC internal channel:
+1723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+1724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC external channel (channel connected to a GPIO pin):
+1725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+1726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The channel parameter must be a value defined from literal
+1727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+1728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+1729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+1730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         must not be a value from functions where a channel number is
+1731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         returned from ADC registers,
+1732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         because internal and external channels share the same channel
+1733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number in ADC registers. The differentiation is made only with
+1734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         parameters definitions of driver.
+1735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+1736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+1737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+1738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+1739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+ARM GAS  /tmp/cc3JIfda.s 			page 32
+
+
+1740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+1741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+1742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+1743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+1744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+1745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+1746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+1747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+1748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+1749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+1750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+1751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+1752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+1753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+1754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+1755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+1756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+1757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+1758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+1759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+1760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+1761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+1762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+1763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+1764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+1765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+1766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+1767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+1768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+1769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+1770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+1771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+1772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+1773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+1774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+1775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+1776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+1777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channe
+1778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channe
+1779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
+1781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
+1782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to convert a channel defined from parameter
+1785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+1786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+1787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         to its equivalent parameter definition of a ADC external channel
+1788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+1789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The channel parameter can be, additionally to a value
+1790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         defined from parameter definition of a ADC internal channel
+1791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+1792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a value defined from parameter definition of
+1793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+1794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or a value from functions where a channel number is returned
+1795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from ADC registers.
+1796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+ARM GAS  /tmp/cc3JIfda.s 			page 33
+
+
+1797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+1798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+1799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+1800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+1801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+1802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+1803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+1804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+1805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+1806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+1807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+1808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+1809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+1810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+1811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+1812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+1813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+1814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+1815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+1816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+1817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+1818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+1819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+1820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+1821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+1822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+1823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+1824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+1825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+1826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+1827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+1828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+1829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+1830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+1831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+1832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+1833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+1834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+1835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+1836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+1837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+1838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+1839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+1840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1
+1841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2
+1842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3
+1843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4
+1844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5
+1845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+1846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+1847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+1848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+1849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+1850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+1851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+1852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+1853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+ARM GAS  /tmp/cc3JIfda.s 			page 34
+
+
+1854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+1855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+1856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+1857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+1858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
+1860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+1861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+1862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+1863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to determine whether the internal channel
+1864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         selected is available on the ADC instance selected.
+1865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The channel parameter must be a value defined from parameter
+1866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+1867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+1868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         must not be a value defined from parameter definition of
+1869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+1870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or a value from functions where a channel number is
+1871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         returned from ADC registers,
+1872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         because internal and external channels share the same channel
+1873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number in ADC registers. The differentiation is made only with
+1874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         parameters definitions of driver.
+1875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_INSTANCE__ ADC instance
+1876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+1877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+1878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+1879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+1880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+1881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+1882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+1883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+1884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+1885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+1886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+1887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+1888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+1889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+1890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+1891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+1892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+1893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+1894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+1895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+1896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+1897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value "0" if the internal channel selected is not available on the ADC instance selecte
+1898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Value "1" if the internal channel selected is available on the ADC instance selected.
+1899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+1900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+1901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+1902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((((__ADC_INSTANCE__) == ADC1)                                               \
+1903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+1905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+1906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+ARM GAS  /tmp/cc3JIfda.s 			page 35
+
+
+1911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC2)                                               \
+1912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+1914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+1915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC3)                                               \
+1919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
+1921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC4)                                               \
+1927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6)         ||                    \
+1929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC5)                                               \
+1934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5)         ||                    \
+1936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) ||                    \
+1937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4)         ||                    \
+1938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+1943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #elif defined(STM32G471xx)
+1944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+1945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((((__ADC_INSTANCE__) == ADC1)                                               \
+1946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+1948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+1949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC2)                                               \
+1955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+1957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+1958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC3)                                               \
+1962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
+1964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+ARM GAS  /tmp/cc3JIfda.s 			page 36
+
+
+1968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+1969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+1970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+1971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((((__ADC_INSTANCE__) == ADC1)                                               \
+1972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+1974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+1975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC2)                                               \
+1981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+1983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+1984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+1987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #elif defined(STM32G491xx) || defined(STM32G4A1xx)
+1988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+1989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((((__ADC_INSTANCE__) == ADC1)                                               \
+1990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+1991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+1992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+1993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+1994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+1995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+1996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+1997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+1998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC2)                                               \
+1999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+2000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+2001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+2002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+2004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ||                                                                          \
+2005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__ADC_INSTANCE__) == ADC3)                                               \
+2006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     &&(                                                                        \
+2007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
+2008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6)         ||                    \
+2009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+2010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                           \
+2012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif
+2014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to define ADC analog watchdog parameter:
+2017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         define a single channel to monitor with analog watchdog
+2018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from sequencer channel and groups definition.
+2019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+2020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example:
+2021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           LL_ADC_SetAnalogWDMonitChannels(
+2022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC1, LL_ADC_AWD1,
+2023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+2024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+ARM GAS  /tmp/cc3JIfda.s 			page 37
+
+
+2025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+2026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+2027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+2028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+2029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+2030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+2031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+2032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+2033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+2034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+2035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+2036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+2037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+2038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+2039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+2040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+2041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+2042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+2043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+2044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+2045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+2046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+2047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+2048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+2049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+2050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+2051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+2052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+2053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+2054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+2055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+2056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+2057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+2058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+2059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+2060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+2061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+2062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+2063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+2064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+2065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+2066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+2067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      comparison with internal channel parameter to be done
+2068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+2069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __GROUP__ This parameter can be one of the following values:
+2070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_GROUP_REGULAR
+2071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_GROUP_INJECTED
+2072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+2073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+2074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_DISABLE
+2075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+2076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+2077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+2078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+2079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+2080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+2081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+ARM GAS  /tmp/cc3JIfda.s 			page 38
+
+
+2082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+2083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+2084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+2085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+2086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+2087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+2088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+2089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+2090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+2091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+2092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+2093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+2094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+2095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+2096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+2097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+2098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+2099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+2100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+2101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+2102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+2103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+2104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+2105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+2106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+2107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+2108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+2109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+2110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+2111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+2112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+2113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+2114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+2115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+2116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+2117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+2118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+2119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+2120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+2121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+2122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+2123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+2124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+2125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+2126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+2127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+2128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+2129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+2130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+2131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+2132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+2133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+2134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+2135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
+2136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
+2137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+2138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG  (0)(1)
+ARM GAS  /tmp/cc3JIfda.s 			page 39
+
+
+2139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ  (0)(1)
+2140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
+2141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG  (0)(5)
+2142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ  (0)(5)
+2143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
+2144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(6)
+2145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(6)
+2146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (6)
+2147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (0)(1)
+2148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (0)(1)
+2149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ         (1)
+2150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (0)(2)
+2151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (0)(2)
+2152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ         (2)
+2153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     (0)(2)
+2154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     (0)(2)
+2155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ    (2)
+2156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     (0)(3)
+2157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     (0)(3)
+2158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ    (3)
+2159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG          (0)(5)
+2160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ          (0)(5)
+2161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ         (5)
+2162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG          (0)(5)
+2163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ          (0)(5)
+2164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ         (5)
+2165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG          (0)(4)
+2166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ          (0)(4)
+2167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ         (4)
+2168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+2169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
+2170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+2171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+2172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+2173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+2174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+2175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+2176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+2177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+2178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                    
+2180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                           
+2181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                  
+2182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    :                                                                                               
+2183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                          
+2184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                 
+2185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    :                                                                                               
+2186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) 
+2187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to set the value of ADC analog watchdog threshold high
+2191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or low in function of ADC resolution, when ADC resolution is
+2192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         different of 12 bits.
+2193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
+2194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or @ref LL_ADC_SetAnalogWDThresholds().
+2195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example, with a ADC resolution of 8 bits, to set the value of
+ARM GAS  /tmp/cc3JIfda.s 			page 40
+
+
+2196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog threshold high (on 8 bits):
+2197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           LL_ADC_SetAnalogWDThresholds
+2198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *            (< ADCx param >,
+2199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8
+2200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *            );
+2201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+2202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+2207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+2208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+2210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+2211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to get the value of ADC analog watchdog threshold high
+2214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or low in function of ADC resolution, when ADC resolution is
+2215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         different of 12 bits.
+2216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+2217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example, with a ADC resolution of 8 bits, to get the value of
+2218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog threshold high (on 8 bits):
+2219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+2220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *            (LL_ADC_RESOLUTION_8B,
+2221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+2222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *            );
+2223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+2224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+2229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+2230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+2232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+2233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to get the ADC analog watchdog threshold high
+2236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or low from raw value containing both thresholds concatenated.
+2237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+2238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example, to get analog watchdog threshold high from the register raw value:
+2239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both
+2240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
+2241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+2242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+2243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+2244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+2245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)       \
+2247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_
+2248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to set the ADC calibration value with both single ended
+2251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and differential modes calibration factors concatenated.
+2252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().
+ARM GAS  /tmp/cc3JIfda.s 			page 41
+
+
+2253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example, to set calibration factors single ended to 0x55
+2254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and differential ended to 0x2A:
+2255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           LL_ADC_SetCalibrationFactor(
+2256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC1,
+2257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
+2258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
+2259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
+2260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+2261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIA
+2263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__)
+2264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+2266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to get the ADC multimode conversion data of ADC master
+2268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or ADC slave from raw value with both ADC conversion data concatenated.
+2269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This macro is intended to be used when multimode transfer by DMA
+2270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+2271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         In this case the transferred data need to processed with this macro
+2272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         to separate the conversion data of ADC master and ADC slave.
+2273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+2274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_MASTER
+2275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_SLAVE
+2276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+2277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+2278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) 
+2280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_C
+2281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+2282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+2284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to select, from a ADC instance, to which ADC instance
+2286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         it has a dependence in multimode (ADC master of the corresponding
+2287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC common instance).
+2288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of device with multimode available and a mix of
+2289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instances compliant and not compliant with multimode feature,
+2290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instances not compliant with multimode feature are
+2291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         considered as master instances (do not depend to
+2292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         any other ADC instance).
+2293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADCx__ ADC instance
+2294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
+2295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC5)
+2297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+2298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ( ( ((__ADCx__) == ADC2)                                                     \
+2299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     )?                                                                         \
+2300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     (ADC1)                                                                     \
+2301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     :                                                                          \
+2302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     ( ( ((__ADCx__) == ADC4)                                                   \
+2303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )?                                                                       \
+2304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       (ADC3)                                                                   \
+2305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       :                                                                        \
+2306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       (__ADCx__)                                                               \
+2307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     )                                                                          \
+2308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #else
+ARM GAS  /tmp/cc3JIfda.s 			page 42
+
+
+2310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+2311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ( ( ((__ADCx__) == ADC2)                                                     \
+2312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     )?                                                                         \
+2313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     (ADC1)                                                                     \
+2314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     :                                                                          \
+2315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     (__ADCx__)                                                                 \
+2316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC5 */
+2318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+2319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to select the ADC common instance
+2322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         to which is belonging the selected ADC instance.
+2323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   ADC common register instance can be used for:
+2324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Set parameters common to several ADC instances
+2325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Multimode (for devices with several ADC instances)
+2326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+2327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADCx__ ADC instance
+2328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval ADC common register instance
+2329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC345_COMMON)
+2331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
+2332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2))                              \
+2333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     ? (                                                                        \
+2334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (ADC12_COMMON)                                                          \
+2335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       :                                                                        \
+2337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       (                                                                        \
+2338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (ADC345_COMMON)                                                         \
+2339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #else
+2342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_COMMON_INSTANCE(__ADCx__)  (ADC12_COMMON)
+2343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC345_COMMON */
+2344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to check if all ADC instances sharing the same
+2346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC common instance are disabled.
+2347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This check is required by functions with setting conditioned to
+2348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+2349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         All ADC instances of the ADC common group must be disabled.
+2350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+2351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On devices with only 1 ADC common instance, parameter of this macro
+2352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is useless and can be ignored (parameter kept for compatibility
+2353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         with devices featuring several ADC common instances).
+2354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADCXY_COMMON__ ADC common instance
+2355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value "0" if all ADC instances sharing the same ADC common instance
+2357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         are disabled.
+2358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Value "1" if at least one ADC instance sharing the same ADC common instance
+2359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is enabled.
+2360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC345_COMMON)
+2362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC4) &&  defined(ADC5)
+2363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+2364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
+2365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     ? (                                                                        \
+2366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (LL_ADC_IsEnabled(ADC1) |                                               \
+ARM GAS  /tmp/cc3JIfda.s 			page 43
+
+
+2367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         LL_ADC_IsEnabled(ADC2)  )                                              \
+2368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       :                                                                        \
+2370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       (                                                                        \
+2371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (LL_ADC_IsEnabled(ADC3) |                                               \
+2372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         LL_ADC_IsEnabled(ADC4) |                                               \
+2373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         LL_ADC_IsEnabled(ADC5)  )                                              \
+2374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #else
+2377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+2378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
+2379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     ? (                                                                        \
+2380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****        (LL_ADC_IsEnabled(ADC1) |                                               \
+2381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         LL_ADC_IsEnabled(ADC2)  )                                              \
+2382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       )                                                                        \
+2383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       :                                                                        \
+2384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       (LL_ADC_IsEnabled(ADC3))                                                 \
+2385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   )
+2386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC4 && ADC5 */
+2387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #else
+2388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+2389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
+2390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif
+2391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to define the ADC conversion data full-scale digital
+2394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         value corresponding to the selected ADC resolution.
+2395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   ADC conversion data full-scale corresponds to voltage range
+2396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         determined by analog voltage references Vref+ and Vref-
+2397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (refer to reference manual).
+2398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+2399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion dat
+2404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+2406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
+2407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to convert the ADC conversion data from
+2410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a resolution to another resolution.
+2411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __DATA__ ADC conversion data to be converted
+2412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
+2413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This parameter can be one of the following values:
+2414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+2419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This parameter can be one of the following values:
+2420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+ARM GAS  /tmp/cc3JIfda.s 			page 44
+
+
+2424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval ADC conversion data to the requested resolution
+2425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+2427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                          __ADC_RESOLUTION_CURRENT__,\
+2428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                          __ADC_RESOLUTION_TARGET__)          \
+2429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** (((__DATA__)                                                                 \
+2430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \
+2431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****  >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \
+2432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** )
+2433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to calculate the voltage (unit: mVolt)
+2436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         corresponding to a ADC conversion data (unit: digital value).
+2437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Analog reference voltage (Vref+) must be either known from
+2438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         user board environment or can be calculated using ADC measurement
+2439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+2440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+2441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+2442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                       (unit: digital value).
+2443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+2444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+2449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+2451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                       __ADC_DATA__,\
+2452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                       __ADC_RESOLUTION__)                    \
+2453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
+2454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
+2455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** )
+2456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to calculate analog reference voltage (Vref+)
+2459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (unit: mVolt) from ADC conversion data of internal voltage
+2460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         reference VrefInt.
+2461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Computation is using VrefInt calibration value
+2462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         stored in system memory for each device during production.
+2463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This voltage depends on user board environment: voltage level
+2464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         connected to pin Vref+.
+2465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         On devices with small package, the pin Vref+ is not present
+2466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and internally bonded to pin Vdda.
+2467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, calibration data of internal voltage reference
+2468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         VrefInt corresponds to a resolution of 12 bits,
+2469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         this is the recommended ADC resolution to convert voltage of
+2470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal voltage reference VrefInt.
+2471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Otherwise, this macro performs the processing to scale
+2472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion data to 12 bits.
+2473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+2474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of internal voltage reference VrefInt (unit: digital value).
+2475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+2476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Analog reference voltage (unit: mV)
+ARM GAS  /tmp/cc3JIfda.s 			page 45
+
+
+2481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+2483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                          __ADC_RESOLUTION__)                 \
+2484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
+2485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****  / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
+2486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                     (__ADC_RESOLUTION__),                    \
+2487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                     LL_ADC_RESOLUTION_12B)                   \
+2488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** )
+2489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+2492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from ADC conversion data of internal temperature sensor.
+2493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Computation is using temperature sensor calibration values
+2494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         stored in system memory for each device during production.
+2495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Calculation formula:
+2496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
+2497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+2498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+2499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
+2500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
+2501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+2502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
+2503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                            TEMP_DEGC_CAL1 (calibrated in factory)
+2504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
+2505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                            TEMP_DEGC_CAL2 (calibrated in factory)
+2506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Caution: Calculation relevancy under reserve that calibration
+2507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  parameters are correct (address and data).
+2508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  To calculate temperature using temperature sensor
+2509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  datasheet typical values (generic values less, therefore
+2510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  less accurate than calibrated values),
+2511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+2512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   As calculation input, the analog reference voltage (Vref+) must be
+2513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         defined as it impacts the ADC LSB equivalent voltage.
+2514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Analog reference voltage (Vref+) must be either known from
+2515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         user board environment or can be calculated using ADC measurement
+2516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+2517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, calibration data of temperature sensor
+2518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         corresponds to a resolution of 12 bits,
+2519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         this is the recommended ADC resolution to convert voltage of
+2520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         temperature sensor.
+2521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Otherwise, this macro performs the processing to scale
+2522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion data to 12 bits.
+2523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
+2524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+2525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                 temperature sensor (unit: digital value).
+2526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
+2527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                 sensor voltage has been measured.
+2528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This parameter can be one of the following values:
+2529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Temperature (unit: degree Celsius)
+2534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+2536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                   __TEMPSENSOR_ADC_DATA__,\
+2537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                   __ADC_RESOLUTION__)                            \
+ARM GAS  /tmp/cc3JIfda.s 			page 46
+
+
+2538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
+2539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                   (__ADC_RESOLUTION__),          \
+2540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                   LL_ADC_RESOLUTION_12B)         \
+2541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                  * (__VREFANALOG_VOLTAGE__))                                     \
+2542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                 / TEMPSENSOR_CAL_VREFANALOG)                                     \
+2543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
+2544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
+2545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+2546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****  ) + TEMPSENSOR_CAL1_TEMP                                                        \
+2547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** )
+2548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+2551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from ADC conversion data of internal temperature sensor.
+2552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Computation is using temperature sensor typical values
+2553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (refer to device datasheet).
+2554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Calculation formula:
+2555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+2556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                         / Avg_Slope + CALx_TEMP
+2557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
+2558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                   (unit: digital value)
+2559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                Avg_Slope        = temperature sensor slope
+2560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                   (unit: uV/Degree Celsius)
+2561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
+2562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                   temperature CALx_TEMP (unit: mV)
+2563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Caution: Calculation relevancy under reserve the temperature sensor
+2564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  of the current device has characteristics in line with
+2565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  datasheet typical values.
+2566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  If temperature sensor calibration values are available on
+2567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+2568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  temperature calculation will be more accurate using
+2569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+2570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   As calculation input, the analog reference voltage (Vref+) must be
+2571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         defined as it impacts the ADC LSB equivalent voltage.
+2572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Analog reference voltage (Vref+) must be either known from
+2573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         user board environment or can be calculated using ADC measurement
+2574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+2575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   ADC measurement data must correspond to a resolution of 12 bits
+2576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (full scale digital value 4095). If not the case, the data must be
+2577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         preliminarily rescaled to an equivalent resolution of 12 bits.
+2578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical v
+2579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                       On STM32G4, refer to device datasheet parameter "Avg_Slop
+2580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical
+2581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                       On STM32G4, refer to device datasheet parameter "V30" (co
+2582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature s
+2583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
+2584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit:
+2585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor volta
+2586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This parameter can be one of the following values:
+2587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Temperature (unit: degree Celsius)
+2592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+2594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              __TEMPSENSOR_TYP_CALX_V__,\
+ARM GAS  /tmp/cc3JIfda.s 			page 47
+
+
+2595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              __TEMPSENSOR_CALX_TEMP__,\
+2596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              __VREFANALOG_VOLTAGE__,\
+2597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              __TEMPSENSOR_ADC_DATA__,\
+2598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              __ADC_RESOLUTION__)            \
+2599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
+2600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
+2601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****               * 1000UL)                                                     \
+2602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     -                                                                       \
+2603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
+2604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****               * 1000UL)                                                     \
+2605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****    )                                                                        \
+2606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                \
+2607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****  ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                    \
+2608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** )
+2609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+2612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+2616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Exported functions --------------------------------------------------------*/
+2620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+2621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+2622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+2625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+2626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /* Note: LL ADC functions to set DMA transfer are located into sections of    */
+2628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       configuration of ADC instance, groups and multimode (if available):  */
+2629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
+2630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Function to help to configure DMA transfer from ADC: retrieve the
+2633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC register address from ADC instance and a list of ADC registers
+2634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         intended to be used (most commonly) with DMA transfer.
+2635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   These ADC registers are data registers:
+2636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         when ADC conversion data is available in ADC data registers,
+2637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC generates a DMA transfer request.
+2638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This macro is intended to be used with LL DMA driver, refer to
+2639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         function "LL_DMA_ConfigAddresses()".
+2640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example:
+2641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           LL_DMA_ConfigAddresses(DMA1,
+2642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                  LL_DMA_CHANNEL_1,
+2643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+2644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                  (uint32_t)&< array or variable >,
+2645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+2646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with several ADC: in multimode, some devices
+2647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use a different data register outside of ADC instance scope
+2648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (common data register). This macro manages this register difference,
+2649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         only ADC instance has to be set as parameter.
+2650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n
+2651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n
+ARM GAS  /tmp/cc3JIfda.s 			page 48
+
+
+2652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr
+2653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+2654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Register This parameter can be one of the following values:
+2655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+2656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+2657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+2658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) Available on devices with several ADC instances.
+2659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval ADC register address
+2660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+2662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+2663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t data_reg_addr;
+2665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
+2667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+2668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     /* Retrieve address of register DR */
+2669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     data_reg_addr = (uint32_t) &(ADCx->DR);
+2670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   }
+2671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+2672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+2673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     /* Retrieve address of register CDR */
+2674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+2675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   }
+2676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return data_reg_addr;
+2678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #else
+2680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+2681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Prevent unused argument(s) compilation warning */
+2683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (void)(Register);
+2684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Retrieve address of register DR */
+2686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t) &(ADCx->DR);
+2687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+2689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+2692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to
+2695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+2696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set parameter common to several ADC: Clock source and prescaler.
+2700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, if ADC group injected is used, some
+2701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         clock ratio constraints between ADC clock and AHB clock
+2702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         must be respected.
+2703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to reference manual.
+2704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+2705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+2706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         All ADC instances of the ADC common group must be disabled.
+2707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+2708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instance or by using helper macro helper macro
+ARM GAS  /tmp/cc3JIfda.s 			page 49
+
+
+2709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+2710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n
+2711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      PRESC          LL_ADC_SetCommonClock
+2712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+2713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  CommonClock This parameter can be one of the following values:
+2715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+2716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+2717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+2718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+2719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+2720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+2721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+2722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+2723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+2724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+2725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+2726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+2727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+2728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+2729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+2730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+2731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+2733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
+2735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get parameter common to several ADC: Clock source and prescaler.
+2739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n
+2740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      PRESC          LL_ADC_GetCommonClock
+2741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+2742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+2744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+2745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+2746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+2747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+2748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+2749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+2750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+2751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+2752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+2753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+2754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+2755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+2756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+2757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+2758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+2759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
+2761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
+2763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/cc3JIfda.s 			page 50
+
+
+2766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set parameter common to several ADC: measurement path to
+2767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal channels (VrefInt, temperature sensor, ...).
+2768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Configure all paths (overwrite current configuration).
+2769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   One or several values can be selected.
+2770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+2771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+2772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         The values not selected are removed from configuration.
+2773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Stabilization time of measurement path to internal channel:
+2774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         After enabling internal paths, before starting ADC conversion,
+2775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a delay is required for internal voltage reference and
+2776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         temperature sensor stabilization time.
+2777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet.
+2778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+2779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+2780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   ADC internal channel sampling time constraint:
+2781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         For ADC conversion of internal channels,
+2782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a sampling time minimum value is required.
+2783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet.
+2784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
+2785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalCh\n
+2786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalCh
+2787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+2788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  PathInternal This parameter can be a combination of the following values:
+2790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+2791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+2792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+2793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+2794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+2795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Path
+2797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal)
+2799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set parameter common to several ADC: measurement path to
+2803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal channels (VrefInt, temperature sensor, ...).
+2804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Add paths to the current configuration.
+2805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   One or several values can be selected.
+2806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+2807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+2808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Stabilization time of measurement path to internal channel:
+2809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         After enabling internal paths, before starting ADC conversion,
+2810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a delay is required for internal voltage reference and
+2811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         temperature sensor stabilization time.
+2812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet.
+2813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+2814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+2815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   ADC internal channel sampling time constraint:
+2816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         For ADC conversion of internal channels,
+2817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a sampling time minimum value is required.
+2818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet.
+2819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChAdd\n
+2820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalChAdd\n
+2821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalChAdd
+2822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+ARM GAS  /tmp/cc3JIfda.s 			page 51
+
+
+2823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  PathInternal This parameter can be a combination of the following values:
+2825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+2826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+2827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+2828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+2829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+2830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t P
+2832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCxy_COMMON->CCR, PathInternal);
+2834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set parameter common to several ADC: measurement path to
+2838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal channels (VrefInt, temperature sensor, ...).
+2839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Remove paths to the current configuration.
+2840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   One or several values can be selected.
+2841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+2842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+2843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChRem\n
+2844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalChRem\n
+2845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalChRem
+2846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+2847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  PathInternal This parameter can be a combination of the following values:
+2849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+2850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+2851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+2852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+2853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+2854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t P
+2856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
+2858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get parameter common to several ADC: measurement path to internal
+2862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         channels (VrefInt, temperature sensor, ...).
+2863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   One or several values can be selected.
+2864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+2865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+2866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
+2867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VSENSESEL      LL_ADC_GetCommonPathInternalCh\n
+2868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      VBATSEL        LL_ADC_GetCommonPathInternalCh
+2869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+2870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+2871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be a combination of the following values:
+2872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+2873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+2874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+2875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+2876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+2878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSE
+ARM GAS  /tmp/cc3JIfda.s 			page 52
+
+
+2880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+2884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC ins
+2887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+2888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC calibration factor in the mode single-ended
+2892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or differential (for devices with differential mode available).
+2893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function is intended to set calibration parameters
+2894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without having to perform a new calibration using
+2895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref LL_ADC_StartCalibration().
+2896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with differential mode available:
+2897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Calibration of offset is specific to each of
+2898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         single-ended and differential modes
+2899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (calibration factor must be specified for each of these
+2900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         differential modes, if used afterwards and if the application
+2901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         requires their calibration).
+2902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of setting calibration factors of both modes single ended
+2903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
+2904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         both calibration factors must be concatenated.
+2905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         To perform this processing, use helper macro
+2906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
+2907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+2908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+2909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled, without calibration on going, without conversion
+2910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on going on group regular.
+2911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n
+2912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor
+2913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+2914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SingleDiff This parameter can be one of the following values:
+2915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SINGLE_ENDED
+2916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+2917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
+2918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+2919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+2920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t C
+2922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+  30              		.loc 2 2922 1 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		@ link register save eliminated.
+2923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CALFACT,
+  35              		.loc 2 2923 3 view .LVU1
+  36 0000 D0F8B430 		ldr	r3, [r0, #180]
+  37 0004 01F07F1C 		and	ip, r1, #8323199
+  38 0008 23EA0C0C 		bic	ip, r3, ip
+  39 000c 01F07F03 		and	r3, r1, #127
+  40 0010 DB43     		mvns	r3, r3
+  41 0012 03EA1133 		and	r3, r3, r1, lsr #12
+  42 0016 03F01003 		and	r3, r3, #16
+ARM GAS  /tmp/cc3JIfda.s 			page 53
+
+
+  43 001a 9A40     		lsls	r2, r2, r3
+  44              	.LVL1:
+  45              		.loc 2 2923 3 is_stmt 0 view .LVU2
+  46 001c 4CEA0202 		orr	r2, ip, r2
+  47 0020 C0F8B420 		str	r2, [r0, #180]
+2924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
+2925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLED
+2926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+  48              		.loc 2 2926 1 view .LVU3
+  49 0024 7047     		bx	lr
+  50              		.cfi_endproc
+  51              	.LFE139:
+  53              		.section	.text.LL_ADC_SetChannelSamplingTime,"ax",%progbits
+  54              		.align	1
+  55              		.syntax unified
+  56              		.thumb
+  57              		.thumb_func
+  59              	LL_ADC_SetChannelSamplingTime:
+  60              	.LVL2:
+  61              	.LFB195:
+2927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC calibration factor in the mode single-ended
+2930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or differential (for devices with differential mode available).
+2931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Calibration factors are set by hardware after performing
+2932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a calibration run using function @ref LL_ADC_StartCalibration().
+2933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with differential mode available:
+2934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Calibration of offset is specific to each of
+2935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         single-ended and differential modes
+2936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n
+2937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor
+2938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+2939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SingleDiff This parameter can be one of the following values:
+2940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SINGLE_ENDED
+2941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+2942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0x7F
+2943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+2945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Retrieve bits with position in register depending on parameter           */
+2947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* "SingleDiff".                                                            */
+2948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */
+2949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* containing other bits reserved for other purpose.                        */
+2950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CALFACT,
+2951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC
+2952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                                                   ADC_SINGLEDIFF_CA
+2953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC resolution.
+2957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to reference manual for alignments formats
+2958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         dependencies to ADC resolutions.
+2959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+2960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+2961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+2962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+2963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     RES            LL_ADC_SetResolution
+ARM GAS  /tmp/cc3JIfda.s 			page 54
+
+
+2964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+2965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Resolution This parameter can be one of the following values:
+2966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+2971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+2973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
+2975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC resolution.
+2979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to reference manual for alignments formats
+2980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         dependencies to ADC resolutions.
+2981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     RES            LL_ADC_GetResolution
+2982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+2983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+2984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_12B
+2985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_10B
+2986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_8B
+2987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_RESOLUTION_6B
+2988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+2989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
+2990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+2991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
+2992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+2993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+2994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+2995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC conversion data alignment.
+2996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Refer to reference manual for alignments formats
+2997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         dependencies to ADC resolutions.
+2998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+2999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     ALIGN          LL_ADC_SetDataAlignment
+3003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  DataAlignment This parameter can be one of the following values:
+3005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+3006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+3007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+3010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
+3012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC conversion data alignment.
+3016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Refer to reference manual for alignments formats
+3017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         dependencies to ADC resolutions.
+3018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     ALIGN          LL_ADC_GetDataAlignment
+3019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+ARM GAS  /tmp/cc3JIfda.s 			page 55
+
+
+3021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+3022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+3023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+3025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
+3027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC low power mode.
+3031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Description of ADC low power modes:
+3032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC low power mode "auto wait": Dynamic low power mode,
+3033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions occurrences are limited to the minimum necessary
+3034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           in order to reduce power consumption.
+3035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           New ADC conversion starts only when the previous
+3036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           unitary conversion data (for ADC group regular)
+3037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           or previous sequence conversions data (for ADC group injected)
+3038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           has been retrieved by user software.
+3039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           In the meantime, ADC remains idle: does not performs any
+3040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           other conversion.
+3041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This mode allows to automatically adapt the ADC conversions
+3042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           triggers to the speed of the software that reads the data.
+3043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Moreover, this avoids risk of overrun for low frequency
+3044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           applications.
+3045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           How to use this low power mode:
+3046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - It is not recommended to use with interruption or DMA
+3047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             since these modes have to clear immediately the EOC flag
+3048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (by CPU to free the IRQ pending event or by DMA).
+3049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Auto wait will work but fort a very short time, discarding
+3050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             its intended benefit (except specific case of high load of CPU
+3051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             or DMA transfers which can justify usage of auto wait).
+3052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Do use with polling: 1. Start conversion,
+3053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             2. Later on, when conversion data is needed: poll for end of
+3054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             conversion  to ensure that conversion is completed and
+3055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             retrieve ADC conversion data. This will trig another
+3056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC conversion start.
+3057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC low power mode "auto power-off" (feature available on
+3058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+3059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the ADC automatically powers-off after a conversion and
+3060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           automatically wakes up when a new conversion is triggered
+3061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (with startup time between trigger and start of sampling).
+3062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This feature can be combined with low power mode "auto wait".
+3063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   With ADC low power mode "auto wait", the ADC conversion data read
+3064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is corresponding to previous ADC conversion start, independently
+3065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of delay during which ADC was idle.
+3066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Therefore, the ADC conversion data may be outdated: does not
+3067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         correspond to the current voltage level on the selected
+3068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC channel.
+3069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode
+3074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  LowPowerMode This parameter can be one of the following values:
+3076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_LP_MODE_NONE
+3077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_LP_AUTOWAIT
+ARM GAS  /tmp/cc3JIfda.s 			page 56
+
+
+3078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+3081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
+3083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC low power mode:
+3087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Description of ADC low power modes:
+3088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC low power mode "auto wait": Dynamic low power mode,
+3089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions occurrences are limited to the minimum necessary
+3090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           in order to reduce power consumption.
+3091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           New ADC conversion starts only when the previous
+3092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           unitary conversion data (for ADC group regular)
+3093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           or previous sequence conversions data (for ADC group injected)
+3094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           has been retrieved by user software.
+3095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           In the meantime, ADC remains idle: does not performs any
+3096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           other conversion.
+3097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This mode allows to automatically adapt the ADC conversions
+3098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           triggers to the speed of the software that reads the data.
+3099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Moreover, this avoids risk of overrun for low frequency
+3100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           applications.
+3101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           How to use this low power mode:
+3102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - It is not recommended to use with interruption or DMA
+3103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             since these modes have to clear immediately the EOC flag
+3104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (by CPU to free the IRQ pending event or by DMA).
+3105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Auto wait will work but fort a very short time, discarding
+3106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             its intended benefit (except specific case of high load of CPU
+3107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             or DMA transfers which can justify usage of auto wait).
+3108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Do use with polling: 1. Start conversion,
+3109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             2. Later on, when conversion data is needed: poll for end of
+3110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             conversion  to ensure that conversion is completed and
+3111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             retrieve ADC conversion data. This will trig another
+3112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC conversion start.
+3113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC low power mode "auto power-off" (feature available on
+3114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+3115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the ADC automatically powers-off after a conversion and
+3116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           automatically wakes up when a new conversion is triggered
+3117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (with startup time between trigger and start of sampling).
+3118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This feature can be combined with low power mode "auto wait".
+3119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   With ADC low power mode "auto wait", the ADC conversion data read
+3120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is corresponding to previous ADC conversion start, independently
+3121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of delay during which ADC was idle.
+3122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Therefore, the ADC conversion data may be outdated: does not
+3123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         correspond to the current voltage level on the selected
+3124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC channel.
+3125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode
+3126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_LP_MODE_NONE
+3129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_LP_AUTOWAIT
+3130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
+3132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
+3134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/cc3JIfda.s 			page 57
+
+
+3135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC selected offset number 1, 2, 3 or 4.
+3138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function set the 2 items of offset configuration:
+3139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC channel to which the offset programmed will be applied
+3140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (independently of channel mapped on ADC group regular
+3141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           or group injected)
+3142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Offset level (offset to be subtracted from the raw
+3143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           converted data).
+3144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Caution: Offset format is dependent to ADC resolution:
+3145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         offset has to be left-aligned on bit 11, the LSB (right bits)
+3146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         are set to 0.
+3147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function enables the offset, by default. It can be forced
+3148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         to disable state using function LL_ADC_SetOffsetState().
+3149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If a channel is mapped on several offsets numbers, only the offset
+3150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         with the lowest value is considered for the subtraction.
+3151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On STM32G4, some fast channels are available: fast analog inputs
+3156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         coming from GPIO pads (ADC_IN1..5).
+3157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n
+3158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR1     OFFSET1        LL_ADC_SetOffset\n
+3159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n
+3160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n
+3161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2        LL_ADC_SetOffset\n
+3162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n
+3163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n
+3164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3        LL_ADC_SetOffset\n
+3165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n
+3166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n
+3167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4        LL_ADC_SetOffset\n
+3168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4_EN     LL_ADC_SetOffset
+3169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be one of the following values:
+3176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+3177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+3178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+3179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+3180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+3181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+3182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+3183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+3184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+3185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+3186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+3187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+3188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+3189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+3190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+3191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+ARM GAS  /tmp/cc3JIfda.s 			page 58
+
+
+3192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+3193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+3194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+3195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+3196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+3197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+3198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+3199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+3200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+3201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+3202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+3203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+3204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+3205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+3206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+3207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+3208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+3209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+3210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+3211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+3212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+3213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+3214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+3215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+3216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+3217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+3218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32
+3221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+3225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+3226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+3227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+3231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Channel to which the offset programmed will be applied
+3232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (independently of channel mapped on ADC group regular
+3233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or group injected)
+3234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Usage of the returned channel number:
+3235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To reinject this channel into another function LL_ADC_xxx:
+3236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the returned channel number is only partly formatted on definition
+3237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+3238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           with parts of literals LL_ADC_CHANNEL_x or using
+3239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+3240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Then the selected literal LL_ADC_CHANNEL_x can be used
+3241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           as parameter for another function.
+3242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To get the channel number in decimal format:
+3243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           process the returned value with the helper macro
+3244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+3245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On STM32G4, some fast channels are available: fast analog inputs
+3246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         coming from GPIO pads (ADC_IN1..5).
+3247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n
+3248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n
+ARM GAS  /tmp/cc3JIfda.s 			page 59
+
+
+3249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n
+3250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel
+3251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+3259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+3260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+3261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+3262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+3263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+3264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+3265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+3266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+3267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+3268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+3269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+3270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+3271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+3272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+3273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+3274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+3275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+3276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+3277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+3278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+3279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+3280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+3281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+3282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+3283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+3284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+3285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+3286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+3287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+3288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+3289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+3290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+3291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+3292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+3293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+3294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+3295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+3296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+3297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+3298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+3299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+3300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      comparison with internal channel parameter to be done
+3301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+3302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
+3304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ARM GAS  /tmp/cc3JIfda.s 			page 60
+
+
+3306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
+3308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+3312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Offset level (offset to be subtracted from the raw
+3313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         converted data).
+3314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Caution: Offset format is dependent to ADC resolution:
+3315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         offset has to be left-aligned on bit 11, the LSB (right bits)
+3316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         are set to 0.
+3317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
+3318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
+3319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
+3320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel
+3321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+3328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
+3330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
+3334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
+3338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         force offset state disable or enable
+3339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without modifying offset channel or offset value.
+3340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function should be needed only in case of offset to be
+3341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         enabled-disabled dynamically, and should not be needed in other cases:
+3342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         function LL_ADC_SetOffset() automatically enables the offset.
+3343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_SetOffsetState\n
+3348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2_EN     LL_ADC_SetOffsetState\n
+3349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3_EN     LL_ADC_SetOffsetState\n
+3350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4_EN     LL_ADC_SetOffsetState
+3351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  OffsetState This parameter can be one of the following values:
+3358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_DISABLE
+3359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_ENABLE
+3360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetStat
+ARM GAS  /tmp/cc3JIfda.s 			page 61
+
+
+3363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+3367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN,
+3368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              OffsetState);
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+3373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         offset state disabled or enabled.
+3374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_GetOffsetState\n
+3375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSET2_EN     LL_ADC_GetOffsetState\n
+3376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSET3_EN     LL_ADC_GetOffsetState\n
+3377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSET4_EN     LL_ADC_GetOffsetState
+3378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_DISABLE
+3386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_ENABLE
+3387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
+3389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
+3393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
+3397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         choose offset sign.
+3398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSETPOS      LL_ADC_SetOffsetSign\n
+3403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSETPOS      LL_ADC_SetOffsetSign\n
+3404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSETPOS      LL_ADC_SetOffsetSign\n
+3405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSETPOS      LL_ADC_SetOffsetSign
+3406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  OffsetSign This parameter can be one of the following values:
+3413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+3414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+3415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
+3418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ARM GAS  /tmp/cc3JIfda.s 			page 62
+
+
+3420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+3422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSETPOS,
+3423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              OffsetSign);
+3424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+3428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         offset sign if positive or negative.
+3429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     OFFSETPOS      LL_ADC_GetOffsetSign\n
+3430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     OFFSETPOS      LL_ADC_GetOffsetSign\n
+3431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     OFFSETPOS      LL_ADC_GetOffsetSign\n
+3432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     OFFSETPOS      LL_ADC_GetOffsetSign
+3433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+3441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+3442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety)
+3444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
+3448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
+3452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         choose offset saturation mode.
+3453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     SATEN          LL_ADC_SetOffsetSaturation\n
+3458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     SATEN          LL_ADC_SetOffsetSaturation\n
+3459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     SATEN          LL_ADC_SetOffsetSaturation\n
+3460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     SATEN          LL_ADC_SetOffsetSaturation
+3461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  OffsetSaturation This parameter can be one of the following values:
+3468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
+3469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
+3470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Offse
+3473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+ARM GAS  /tmp/cc3JIfda.s 			page 63
+
+
+3477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_SATEN,
+3478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              OffsetSaturation);
+3479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
+3483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         offset saturation if enabled or disabled.
+3484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll OFR1     SATEN          LL_ADC_GetOffsetSaturation\n
+3485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR2     SATEN          LL_ADC_GetOffsetSaturation\n
+3486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR3     SATEN          LL_ADC_GetOffsetSaturation\n
+3487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         OFR4     SATEN          LL_ADC_GetOffsetSaturation
+3488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Offsety This parameter can be one of the following values:
+3490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_1
+3491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_2
+3492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_3
+3493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_4
+3494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
+3496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
+3497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
+3499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+3501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN);
+3503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC gain compensation.
+3507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function set the gain compensation coefficient
+3508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         that is applied to raw converted data using the formula:
+3509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           DATA = DATA(raw) * (gain compensation coef) / 4096
+3510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function enables the gain compensation if given
+3511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         coefficient is above 0, otherwise it disables it.
+3512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Gain compensation when enabled is applied to all channels.
+3513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll GCOMP    GCOMPCOEFF     LL_ADC_SetGainCompensation\n
+3518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    GCOMP          LL_ADC_SetGainCompensation
+3519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  GainCompensation This parameter can be:
+3521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         0           Gain compensation will be disabled and value set to 0
+3522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         1 -> 16393  Gain compensation will be enabled with specified value
+3523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
+3526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
+3528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCO
+3529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get the ADC gain compensation value
+3533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll GCOMP    GCOMPCOEFF     LL_ADC_GetGainCompensation\n
+ARM GAS  /tmp/cc3JIfda.s 			page 64
+
+
+3534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    GCOMP          LL_ADC_GetGainCompensation
+3535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be:
+3537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         0           Gain compensation is disabled
+3538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         1 -> 16393  Gain compensation is enabled with returned value
+3539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx)
+3541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ? READ_BIT(ADCx->GCOMP, ADC_G
+3543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_SMPR1_SMPPLUS)
+3546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC sampling time common configuration impacting
+3548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         settings of sampling time channel wise.
+3549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+3553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SMPR1    SMPPLUS        LL_ADC_SetSamplingTimeCommonConfig
+3554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SamplingTimeCommonConfig This parameter can be one of the following values:
+3556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
+3557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
+3558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCom
+3561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
+3563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC sampling time common configuration impacting
+3567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         settings of sampling time channel wise.
+3568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SMPR1    SMPPLUS        LL_ADC_GetSamplingTimeCommonConfig
+3569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
+3572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
+3573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
+3575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
+3577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_SMPR1_SMPPLUS */
+3579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+3582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: gr
+3585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+3586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular conversion trigger source:
+3590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal (SW start) or from external peripheral (timer event,
+ARM GAS  /tmp/cc3JIfda.s 			page 65
+
+
+3591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         external interrupt line).
+3592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting trigger source to external trigger
+3593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         also set trigger polarity to rising edge
+3594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (default setting for compatibility with some ADC on other
+3595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         STM32 families having this setting set by HW default value).
+3596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         In case of need to modify trigger edge, use
+3597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         function @ref LL_ADC_REG_SetTriggerEdge().
+3598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Availability of parameters of trigger sources from timer
+3599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         depends on timers availability on the selected device.
+3600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+3604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n
+3605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource
+3606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  TriggerSource This parameter can be one of the following values:
+3608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+3609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+3610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+3611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1        (1)
+3612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2        (1)
+3613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+3614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+3615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1        (2)
+3616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2        (1)
+3617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3        (2)
+3618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+3619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1        (2)
+3620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4        (1)
+3621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+3622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1        (2)
+3623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4        (1)
+3624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+3625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
+3626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+3627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+3628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1        (2)
+3629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+3630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
+3631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
+3632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
+3633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2       (1)
+3634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3       (1)
+3635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
+3636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2      (2)
+3637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
+3638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4      (2)
+3639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
+3640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
+3641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
+3642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
+3643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
+3644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
+3645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11     (1)
+3646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2      (2)
+3647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
+ARM GAS  /tmp/cc3JIfda.s 			page 66
+
+
+3648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+3649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+3650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+3651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             On this STM32 series, all ADCx are not available on all devices. Refer to device da
+3652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+3655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
+3657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion trigger source:
+3661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal (SW start) or from external peripheral (timer event,
+3662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         external interrupt line).
+3663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To determine whether group regular trigger source is
+3664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal (SW start) or external, without detail
+3665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of which peripheral is selected as external trigger,
+3666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (equivalent to
+3667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+3668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+3669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Availability of parameters of trigger sources from timer
+3670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         depends on timers availability on the selected device.
+3671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n
+3672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource
+3673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+3676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+3677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+3678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1        (1)
+3679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2        (1)
+3680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+3681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+3682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1        (2)
+3683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2        (1)
+3684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3        (2)
+3685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+3686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1        (2)
+3687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4        (1)
+3688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+3689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1        (2)
+3690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4        (1)
+3691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+3692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
+3693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+3694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+3695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1        (2)
+3696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+3697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
+3698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
+3699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
+3700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2       (1)
+3701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3       (1)
+3702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
+3703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2      (2)
+3704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
+ARM GAS  /tmp/cc3JIfda.s 			page 67
+
+
+3705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4      (2)
+3706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
+3707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
+3708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
+3709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
+3710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
+3711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
+3712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11     (1)
+3713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2      (2)
+3714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
+3715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+3716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+3717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+3718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             On this STM32 series, all ADCx are not available on all devices. Refer to device da
+3719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+3721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
+3723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+3725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */
+3726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U
+3727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */
+3729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* to match with triggers literals definition.                              */
+3730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((TriggerSource
+3731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****            & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
+3732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****           | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
+3733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****          );
+3734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion trigger source internal (SW start)
+3738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or external.
+3739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of group regular trigger source set to external trigger,
+3740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         to determine which peripheral is selected as external trigger,
+3741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_REG_GetTriggerSource().
+3742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
+3743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value "0" if trigger source external trigger
+3745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Value "1" if trigger source SW start.
+3746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+3748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1
+3750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular conversion trigger polarity.
+3754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Applicable only for trigger source set to external trigger.
+3755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+3759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge
+3760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ExternalTriggerEdge This parameter can be one of the following values:
+ARM GAS  /tmp/cc3JIfda.s 			page 68
+
+
+3762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+3763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+3764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+3765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+3768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
+3770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion trigger polarity.
+3774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Applicable only for trigger source set to external trigger.
+3775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge
+3776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+3779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+3780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+3781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
+3783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
+3785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC sampling mode.
+3789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function set the ADC conversion sampling mode
+3790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This mode applies to regular group only.
+3791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Set sampling mode is applied to all conversion of regular group.
+3792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+3796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    BULB           LL_ADC_REG_SetSamplingMode\n
+3797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    SMPTRIG        LL_ADC_REG_SetSamplingMode
+3798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SamplingMode This parameter can be one of the following values:
+3800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+3801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+3802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+3803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
+3806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
+3808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get the ADC sampling mode
+3812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    BULB           LL_ADC_REG_GetSamplingMode\n
+3813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    SMPTRIG        LL_ADC_REG_GetSamplingMode
+3814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+3817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+3818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+ARM GAS  /tmp/cc3JIfda.s 			page 69
+
+
+3819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx)
+3821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
+3823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular sequencer length and scan direction.
+3827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Description of ADC group regular sequencer features:
+3828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - For devices with sequencer fully configurable
+3829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+3830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           sequencer length and each rank affectation to a channel
+3831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           are configurable.
+3832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This function performs configuration of:
+3833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence length: Number of ranks in the scan sequence.
+3834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence direction: Unless specified in parameters, sequencer
+3835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             scan direction is forward (from rank 1 to rank n).
+3836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Sequencer ranks are selected using
+3837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           function "LL_ADC_REG_SetSequencerRanks()".
+3838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - For devices with sequencer not fully configurable
+3839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+3840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           sequencer length and each rank affectation to a channel
+3841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           are defined by channel number.
+3842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This function performs configuration of:
+3843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence length: Number of ranks in the scan sequence is
+3844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             defined by number of channels set in the sequence,
+3845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             rank of each channel is fixed by channel HW number.
+3846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+3847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence direction: Unless specified in parameters, sequencer
+3848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             scan direction is forward (from lowest channel number to
+3849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             highest channel number).
+3850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Sequencer ranks are selected using
+3851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           function "LL_ADC_REG_SetSequencerChannels()".
+3852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+3853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion on only 1 channel.
+3854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+3858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
+3859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SequencerNbRanks This parameter can be one of the following values:
+3861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+3862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+3863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+3864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+3865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+3866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+3867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+3868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+3869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+3870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+3871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+3872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+3873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+3874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+3875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ARM GAS  /tmp/cc3JIfda.s 			page 70
+
+
+3876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+3877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+3880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+3882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular sequencer length and scan direction.
+3886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Description of ADC group regular sequencer features:
+3887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - For devices with sequencer fully configurable
+3888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+3889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           sequencer length and each rank affectation to a channel
+3890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           are configurable.
+3891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This function retrieves:
+3892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence length: Number of ranks in the scan sequence.
+3893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence direction: Unless specified in parameters, sequencer
+3894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             scan direction is forward (from rank 1 to rank n).
+3895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Sequencer ranks are selected using
+3896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           function "LL_ADC_REG_SetSequencerRanks()".
+3897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - For devices with sequencer not fully configurable
+3898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+3899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           sequencer length and each rank affectation to a channel
+3900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           are defined by channel number.
+3901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This function retrieves:
+3902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence length: Number of ranks in the scan sequence is
+3903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             defined by number of channels set in the sequence,
+3904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             rank of each channel is fixed by channel HW number.
+3905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+3906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - Sequence direction: Unless specified in parameters, sequencer
+3907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             scan direction is forward (from lowest channel number to
+3908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             highest channel number).
+3909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Sequencer ranks are selected using
+3910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           function "LL_ADC_REG_SetSequencerChannels()".
+3911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+3912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion on only 1 channel.
+3913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength
+3914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+3917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+3918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+3919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+3920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+3921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+3922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+3923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+3924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+3925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+3926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+3927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+3928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+3929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+3930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+3931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+3932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ARM GAS  /tmp/cc3JIfda.s 			page 71
+
+
+3933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+3934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+3936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular sequencer discontinuous mode:
+3940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sequence subdivided and scan conversions interrupted every selected
+3941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number of ranks.
+3942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   It is not possible to enable both ADC group regular
+3943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         continuous mode and sequencer discontinuous mode.
+3944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   It is not possible to enable both ADC auto-injected mode
+3945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         and ADC group regular sequencer discontinuous mode.
+3946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+3947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+3948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+3949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+3950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n
+3951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont
+3952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SeqDiscont This parameter can be one of the following values:
+3954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+3955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+3956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+3957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+3958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+3959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+3960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+3961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+3962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+3963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+3964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+3966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+3967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
+3968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular sequencer discontinuous mode:
+3972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sequence subdivided and scan conversions interrupted every selected
+3973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number of ranks.
+3974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n
+3975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont
+3976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+3977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+3978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+3979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+3980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+3981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+3982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+3983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+3984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+3985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+3986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+3987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+3988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+3989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ARM GAS  /tmp/cc3JIfda.s 			page 72
+
+
+3990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
+3991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+3992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+3993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+3994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular sequence: channel on the selected
+3995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         scan sequence rank.
+3996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function performs configuration of:
+3997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Channels ordering into each rank of scan sequence:
+3998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           whatever channel can be placed into whatever rank.
+3999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, ADC group regular sequencer is
+4000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         fully configurable: sequencer length and each rank
+4001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         affectation to a channel are configurable.
+4002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+4003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Depending on devices and packages, some channels may not be available.
+4004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet for channels availability.
+4005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, to measure internal channels (VrefInt,
+4006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TempSensor, ...), measurement paths to internal channels must be
+4007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         enabled separately.
+4008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+4009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+4012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+4013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n
+4014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n
+4015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n
+4016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n
+4017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n
+4018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n
+4019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
+4020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
+4021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
+4022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n
+4023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n
+4024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n
+4025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
+4026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
+4027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n
+4028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks
+4029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+4031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_1
+4032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_2
+4033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_3
+4034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_4
+4035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_5
+4036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_6
+4037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_7
+4038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_8
+4039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_9
+4040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_10
+4041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_11
+4042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_12
+4043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_13
+4044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_14
+4045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_15
+4046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_16
+ARM GAS  /tmp/cc3JIfda.s 			page 73
+
+
+4047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be one of the following values:
+4048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+4049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+4050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+4051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+4052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+4053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+4054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+4055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+4056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+4057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+4058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+4059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+4060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+4061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+4062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+4063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+4064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+4065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+4066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+4067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+4068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+4069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+4070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+4071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+4072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+4073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+4074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+4075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+4076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+4077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+4078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+4079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+4080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+4081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+4082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+4083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+4084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+4085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+4086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+4087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+4088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+4089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channe
+4092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "Channel" with bits position          */
+4094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* in register and register position depending on parameter "Rank".         */
+4095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameters "Rank" and "Channel" are used with masks because containing   */
+4096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* other bits reserved for other purpose.                                   */
+4097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> A
+4098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+4100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+4101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Ra
+4102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ARM GAS  /tmp/cc3JIfda.s 			page 74
+
+
+4104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular sequence: channel on the selected
+4106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         scan sequence rank.
+4107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, ADC group regular sequencer is
+4108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         fully configurable: sequencer length and each rank
+4109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         affectation to a channel are configurable.
+4110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+4111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Depending on devices and packages, some channels may not be available.
+4112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet for channels availability.
+4113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Usage of the returned channel number:
+4114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To reinject this channel into another function LL_ADC_xxx:
+4115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the returned channel number is only partly formatted on definition
+4116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+4117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           with parts of literals LL_ADC_CHANNEL_x or using
+4118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+4119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Then the selected literal LL_ADC_CHANNEL_x can be used
+4120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           as parameter for another function.
+4121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To get the channel number in decimal format:
+4122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           process the returned value with the helper macro
+4123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+4124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n
+4125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n
+4126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n
+4127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n
+4128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n
+4129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n
+4130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
+4131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
+4132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
+4133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n
+4134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n
+4135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n
+4136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
+4137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
+4138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n
+4139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks
+4140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+4142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_1
+4143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_2
+4144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_3
+4145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_4
+4146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_5
+4147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_6
+4148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_7
+4149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_8
+4150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_9
+4151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_10
+4152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_11
+4153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_12
+4154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_13
+4155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_14
+4156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_15
+4157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_RANK_16
+4158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+4160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+ARM GAS  /tmp/cc3JIfda.s 			page 75
+
+
+4161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+4162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+4163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+4164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+4165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+4166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+4167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+4168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+4169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+4170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+4171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+4172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+4173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+4174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+4175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+4176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+4177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+4178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+4179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+4180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+4181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+4182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+4183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+4184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+4185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+4186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+4187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+4188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+4189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+4190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+4191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+4192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+4193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+4194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+4195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+4196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+4197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+4198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+4199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+4200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+4201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      comparison with internal channel parameter to be done
+4202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+4203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+4205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK
+4207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)((READ_BIT(*preg,
+4209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                               ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MA
+4210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+4211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                    );
+4212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC continuous conversion mode on ADC group regular.
+4216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Description of ADC continuous conversion mode:
+4217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - single mode: one conversion per trigger
+ARM GAS  /tmp/cc3JIfda.s 			page 76
+
+
+4218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - continuous mode: after the first trigger, following
+4219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           conversions launched successively automatically.
+4220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   It is not possible to enable both ADC group regular
+4221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         continuous mode and sequencer discontinuous mode.
+4222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+4225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+4226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode
+4227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Continuous This parameter can be one of the following values:
+4229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_CONV_SINGLE
+4230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+4231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+4234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
+4236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC continuous conversion mode on ADC group regular.
+4240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Description of ADC continuous conversion mode:
+4241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - single mode: one conversion per trigger
+4242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - continuous mode: after the first trigger, following
+4243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           conversions launched successively automatically.
+4244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode
+4245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_CONV_SINGLE
+4248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+4249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+4251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
+4253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular conversion data transfer: no transfer or
+4257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         transfer by DMA, and DMA requests mode.
+4258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If transfer by DMA selected, specifies the DMA requests
+4259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         mode:
+4260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Limited mode (One shot mode): DMA transfer requests are stopped
+4261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           when number of DMA data transfers (number of
+4262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions) is reached.
+4263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode non-circular.
+4264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Unlimited mode: DMA transfer requests are unlimited,
+4265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           whatever number of DMA data transfers (number of
+4266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions).
+4267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode circular.
+4268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+4269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         mode non-circular:
+4270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         when DMA transfers size will be reached, DMA will stop transfers of
+4271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversions data ADC will raise an overrun error
+4272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *        (overrun flag and interruption if enabled).
+4273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with several ADC instances: ADC multimode DMA
+4274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().
+ARM GAS  /tmp/cc3JIfda.s 			page 77
+
+
+4275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To configure DMA source address (peripheral address),
+4276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_DMA_GetRegAddr().
+4277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+4280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+4281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     DMAEN          LL_ADC_REG_SetDMATransfer\n
+4282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     DMACFG         LL_ADC_REG_SetDMATransfer
+4283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  DMATransfer This parameter can be one of the following values:
+4285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+4286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+4287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+4288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+4291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
+4293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion data transfer: no transfer or
+4297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         transfer by DMA, and DMA requests mode.
+4298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If transfer by DMA selected, specifies the DMA requests
+4299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         mode:
+4300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Limited mode (One shot mode): DMA transfer requests are stopped
+4301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           when number of DMA data transfers (number of
+4302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions) is reached.
+4303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode non-circular.
+4304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Unlimited mode: DMA transfer requests are unlimited,
+4305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           whatever number of DMA data transfers (number of
+4306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions).
+4307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode circular.
+4308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+4309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         mode non-circular:
+4310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         when DMA transfers size will be reached, DMA will stop transfers of
+4311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversions data ADC will raise an overrun error
+4312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (overrun flag and interruption if enabled).
+4313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with several ADC instances: ADC multimode DMA
+4314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().
+4315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To configure DMA source address (peripheral address),
+4316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_DMA_GetRegAddr().
+4317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     DMAEN          LL_ADC_REG_GetDMATransfer\n
+4318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     DMACFG         LL_ADC_REG_GetDMATransfer
+4319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+4322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+4323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+4324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+4326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
+4328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group regular behavior in case of overrun:
+ARM GAS  /tmp/cc3JIfda.s 			page 78
+
+
+4332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         data preserved or overwritten.
+4333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Compatibility with devices without feature overrun:
+4334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         other devices without this feature have a behavior
+4335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         equivalent to data overwritten.
+4336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         The default setting of overrun is data preserved.
+4337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Therefore, for compatibility with all devices, parameter
+4338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         overrun should be set to data overwritten.
+4339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+4342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+4343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun
+4344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Overrun This parameter can be one of the following values:
+4346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+4347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+4348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
+4351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
+4353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular behavior in case of overrun:
+4357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         data preserved or overwritten.
+4358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun
+4359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+4362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+4363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
+4365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
+4367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+4371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: g
+4374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+4375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected conversion trigger source:
+4379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal (SW start) or from external peripheral (timer event,
+4380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         external interrupt line).
+4381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting trigger source to external trigger
+4382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         also set trigger polarity to rising edge
+4383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (default setting for compatibility with some ADC on other
+4384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         STM32 families having this setting set by HW default value).
+4385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         In case of need to modify trigger edge, use
+4386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         function @ref LL_ADC_INJ_SetTriggerEdge().
+4387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Availability of parameters of trigger sources from timer
+4388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         depends on timers availability on the selected device.
+ARM GAS  /tmp/cc3JIfda.s 			page 79
+
+
+4389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must not be disabled. Can be enabled with or without conversion
+4392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on going on either groups regular or injected.
+4393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
+4394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource
+4395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  TriggerSource This parameter can be one of the following values:
+4397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+4398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+4399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+4400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
+4401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+4402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+4403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
+4404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+4405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
+4406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
+4407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
+4408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+4409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
+4410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
+4411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+4412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+4413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+4414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+4415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
+4416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+4417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+4418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
+4419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+4420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+4421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
+4422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
+4423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
+4424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+4425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
+4426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+4427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+4428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+4429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+4430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+4431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+4432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+4433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
+4434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
+4435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+4436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+4437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+4438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+4439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             On this STM32 series, all ADCx are not available on all devices. Refer to device da
+4440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+4443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
+4445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/cc3JIfda.s 			page 80
+
+
+4446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion trigger source:
+4449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal (SW start) or from external peripheral (timer event,
+4450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         external interrupt line).
+4451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   To determine whether group injected trigger source is
+4452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal (SW start) or external, without detail
+4453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of which peripheral is selected as external trigger,
+4454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (equivalent to
+4455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+4456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+4457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Availability of parameters of trigger sources from timer
+4458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         depends on timers availability on the selected device.
+4459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
+4460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource
+4461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+4464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+4465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+4466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
+4467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+4468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+4469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
+4470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+4471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
+4472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
+4473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
+4474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+4475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
+4476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
+4477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+4478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+4479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+4480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+4481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
+4482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+4483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+4484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
+4485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+4486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+4487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
+4488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
+4489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
+4490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+4491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
+4492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+4493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+4494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+4495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+4496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+4497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+4498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+4499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
+4500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
+4501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+4502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+ARM GAS  /tmp/cc3JIfda.s 			page 81
+
+
+4503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+4504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+4505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             On this STM32 series, all ADCx are not available on all devices. Refer to device da
+4506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+4508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+4510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+4512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
+4513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 
+4514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
+4516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* to match with triggers literals definition.                              */
+4517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((TriggerSource
+4518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****            & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
+4519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****           | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
+4520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****          );
+4521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion trigger source internal (SW start)
+4525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             or external
+4526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of group injected trigger source set to external trigger,
+4527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         to determine which peripheral is selected as external trigger,
+4528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_INJ_GetTriggerSource.
+4529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
+4530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value "0" if trigger source external trigger
+4532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Value "1" if trigger source SW start.
+4533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+4535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ?
+4537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected conversion trigger polarity.
+4541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Applicable only for trigger source set to external trigger.
+4542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must not be disabled. Can be enabled with or without conversion
+4545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on going on either groups regular or injected.
+4546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge
+4547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ExternalTriggerEdge This parameter can be one of the following values:
+4549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+4550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+4551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+4552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+4555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
+4557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/cc3JIfda.s 			page 82
+
+
+4560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion trigger polarity.
+4561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Applicable only for trigger source set to external trigger.
+4562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge
+4563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+4566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+4567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+4568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
+4570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
+4572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected sequencer length and scan direction.
+4576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function performs configuration of:
+4577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Sequence length: Number of ranks in the scan sequence.
+4578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Sequence direction: Unless specified in parameters, sequencer
+4579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           scan direction is forward (from rank 1 to rank n).
+4580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+4581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion on only 1 channel.
+4582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must not be disabled. Can be enabled with or without conversion
+4585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on going on either groups regular or injected.
+4586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
+4587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SequencerNbRanks This parameter can be one of the following values:
+4589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+4590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+4591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+4592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+4593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+4596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+4598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected sequencer length and scan direction.
+4602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function retrieves:
+4603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Sequence length: Number of ranks in the scan sequence.
+4604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Sequence direction: Unless specified in parameters, sequencer
+4605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           scan direction is forward (from rank 1 to rank n).
+4606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+4607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion on only 1 channel.
+4608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
+4609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+4612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+4613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+4614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+4615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+ARM GAS  /tmp/cc3JIfda.s 			page 83
+
+
+4617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+4619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected sequencer discontinuous mode:
+4623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sequence subdivided and scan conversions interrupted every selected
+4624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number of ranks.
+4625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   It is not possible to enable both ADC group injected
+4626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         auto-injected mode and sequencer discontinuous mode.
+4627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont
+4628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SeqDiscont This parameter can be one of the following values:
+4630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+4631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+4632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+4635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
+4637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected sequencer discontinuous mode:
+4641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sequence subdivided and scan conversions interrupted every selected
+4642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         number of ranks.
+4643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont
+4644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+4647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+4648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+4650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
+4652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected sequence: channel on the selected
+4656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sequence rank.
+4657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Depending on devices and packages, some channels may not be available.
+4658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet for channels availability.
+4659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, to measure internal channels (VrefInt,
+4660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TempSensor, ...), measurement paths to internal channels must be
+4661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         enabled separately.
+4662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+4663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On STM32G4, some fast channels are available: fast analog inputs
+4664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         coming from GPIO pads (ADC_IN1..5).
+4665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must not be disabled. Can be enabled with or without conversion
+4668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on going on either groups regular or injected.
+4669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
+4670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
+4671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
+4672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
+4673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+ARM GAS  /tmp/cc3JIfda.s 			page 84
+
+
+4674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+4675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_1
+4676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_2
+4677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_3
+4678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_4
+4679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be one of the following values:
+4680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+4681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+4682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+4683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+4684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+4685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+4686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+4687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+4688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+4689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+4690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+4691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+4692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+4693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+4694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+4695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+4696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+4697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+4698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+4699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+4700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+4701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+4702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+4703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+4704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+4705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+4706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+4707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+4708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+4709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+4710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+4711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+4712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+4713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+4714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+4715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+4716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+4717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+4718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+4719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+4720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+4721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channe
+4724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "Channel" with bits position          */
+4726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* in register depending on parameter "Rank".                               */
+4727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameters "Rank" and "Channel" are used with masks because containing   */
+4728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* other bits reserved for other purpose.                                   */
+4729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->JSQR,
+4730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ
+ARM GAS  /tmp/cc3JIfda.s 			page 85
+
+
+4731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Ra
+4732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected sequence: channel on the selected
+4736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sequence rank.
+4737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Depending on devices and packages, some channels may not be available.
+4738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet for channels availability.
+4739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Usage of the returned channel number:
+4740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To reinject this channel into another function LL_ADC_xxx:
+4741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the returned channel number is only partly formatted on definition
+4742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+4743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           with parts of literals LL_ADC_CHANNEL_x or using
+4744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+4745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Then the selected literal LL_ADC_CHANNEL_x can be used
+4746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           as parameter for another function.
+4747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To get the channel number in decimal format:
+4748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           process the returned value with the helper macro
+4749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+4750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n
+4751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n
+4752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n
+4753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks
+4754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank This parameter can be one of the following values:
+4756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_1
+4757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_2
+4758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_3
+4759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_RANK_4
+4760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+4762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+4763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+4764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+4765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+4766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+4767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+4768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+4769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+4770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+4771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+4772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+4773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+4774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+4775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+4776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+4777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+4778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+4779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+4780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+4781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+4782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+4783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+4784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+4785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+4786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+4787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+ARM GAS  /tmp/cc3JIfda.s 			page 86
+
+
+4788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+4789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+4790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+4791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+4792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+4793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+4794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+4795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+4796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+4797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+4798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+4799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+4800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+4801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+4802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+4803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      comparison with internal channel parameter to be done
+4804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+4805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+4807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)((READ_BIT(ADCx->JSQR,
+4809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                               (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) <
+4810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                      >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+4811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                    );
+4812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected conversion trigger:
+4816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         independent or from ADC group regular.
+4817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This mode can be used to extend number of data registers
+4818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         updated after one ADC conversion trigger and with data
+4819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         permanently kept (not erased by successive conversions of scan of
+4820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC sequencer ranks), up to 5 data registers:
+4821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         1 data register on ADC group regular, 4 data registers
+4822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on ADC group injected.
+4823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC group injected injected trigger source is set to an
+4824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         external trigger, this feature must be must be set to
+4825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         independent trigger.
+4826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC group injected automatic trigger is compliant only with
+4827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         group injected trigger source set to SW start, without any
+4828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         further action on  ADC group injected conversion start or stop:
+4829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         in this case, ADC group injected is controlled only
+4830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         from ADC group regular.
+4831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   It is not possible to enable both ADC group injected
+4832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         auto-injected mode and sequencer discontinuous mode.
+4833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+4836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+4837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto
+4838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  TrigAuto This parameter can be one of the following values:
+4840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+4841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+4842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+ARM GAS  /tmp/cc3JIfda.s 			page 87
+
+
+4845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
+4847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion trigger:
+4851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         independent or from ADC group regular.
+4852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto
+4853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+4856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+4857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+4859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
+4861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC group injected contexts queue mode.
+4865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   A context is a setting of group injected sequencer:
+4866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - group injected trigger
+4867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - sequencer length
+4868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - sequencer ranks
+4869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         If contexts queue is disabled:
+4870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - only 1 sequence can be configured
+4871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           and is active perpetually.
+4872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         If contexts queue is enabled:
+4873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - up to 2 contexts can be queued
+4874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           and are checked in and out as a FIFO stack (first-in, first-out).
+4875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - If a new context is set when queues is full, error is triggered
+4876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           by interruption "Injected Queue Overflow".
+4877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Two behaviors are possible when all contexts have been processed:
+4878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the contexts queue can maintain the last context active perpetually
+4879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           or can be empty and injected group triggers are disabled.
+4880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Triggers can be only external (not internal SW start)
+4881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Caution: The sequence must be fully configured in one time
+4882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           (one write of register JSQR makes a check-in of a new context
+4883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           into the queue).
+4884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Therefore functions to set separately injected trigger and
+4885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           sequencer channels cannot be used, register JSQR must be set
+4886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           using function @ref LL_ADC_INJ_ConfigQueueContext().
+4887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This parameter can be modified only when no conversion is on going
+4888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+4889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   A modification of the context mode (bit JQDIS) causes the contexts
+4890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         queue to be flushed and the register JSQR is cleared.
+4891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+4894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+4895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n
+4896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode
+4897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  QueueMode This parameter can be one of the following values:
+4899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+4900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+4901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+ARM GAS  /tmp/cc3JIfda.s 			page 88
+
+
+4902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+4903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
+4905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
+4907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected context queue mode.
+4911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n
+4912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode
+4913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+4914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+4915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+4916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+4917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+4918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+4919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
+4920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+4921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
+4922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+4923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+4924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+4925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set one context on ADC group injected that will be checked in
+4926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         contexts queue.
+4927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   A context is a setting of group injected sequencer:
+4928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - group injected trigger
+4929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - sequencer length
+4930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - sequencer ranks
+4931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This function is intended to be used when contexts queue is enabled,
+4932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         because the sequence must be fully configured in one time
+4933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (functions to set separately injected trigger and sequencer channels
+4934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         cannot be used):
+4935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to function @ref LL_ADC_INJ_SetQueueMode().
+4936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In the contexts queue, only the active context can be read.
+4937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         The parameters of this function can be read using functions:
+4938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_GetTriggerSource()
+4939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_GetTriggerEdge()
+4940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_GetSequencerRanks()
+4941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, to measure internal channels (VrefInt,
+4942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TempSensor, ...), measurement paths to internal channels must be
+4943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         enabled separately.
+4944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+4945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On STM32G4, some fast channels are available: fast analog inputs
+4946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         coming from GPIO pads (ADC_IN1..5).
+4947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+4948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+4949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must not be disabled. Can be enabled with or without conversion
+4950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on going on either groups regular or injected.
+4951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n
+4952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n
+4953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n
+4954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n
+4955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n
+4956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n
+4957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext
+4958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+ARM GAS  /tmp/cc3JIfda.s 			page 89
+
+
+4959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  TriggerSource This parameter can be one of the following values:
+4960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+4961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+4962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+4963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
+4964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+4965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+4966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
+4967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+4968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
+4969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
+4970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
+4971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+4972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
+4973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
+4974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+4975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+4976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+4977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+4978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
+4979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+4980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+4981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
+4982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+4983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+4984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
+4985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
+4986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
+4987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+4988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
+4989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+4990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+4991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+4992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+4993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+4994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+4995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+4996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
+4997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
+4998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+4999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+5001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+5002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ExternalTriggerEdge This parameter can be one of the following values:
+5004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+5005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+5006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+5007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Note: This parameter is discarded in case of SW start:
+5009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
+5010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SequencerNbRanks This parameter can be one of the following values:
+5011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+5012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+5013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+5014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+5015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank1_Channel This parameter can be one of the following values:
+ARM GAS  /tmp/cc3JIfda.s 			page 90
+
+
+5016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+5017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+5018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+5019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+5020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+5021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+5022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+5033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+5034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+5035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+5036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+5037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+5038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+5039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+5040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+5041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+5042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+5043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+5044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+5045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+5046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+5056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+5057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank2_Channel This parameter can be one of the following values:
+5058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+5059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+5060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+5061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+5062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+5063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+5064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+ARM GAS  /tmp/cc3JIfda.s 			page 91
+
+
+5073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+5075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+5076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+5077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+5078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+5079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+5080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+5081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+5082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+5083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+5084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+5085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+5086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+5087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+5088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+5098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+5099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank3_Channel This parameter can be one of the following values:
+5100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+5101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+5102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+5103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+5104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+5105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+5106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+5117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+5118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+5119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+5120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+5121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+5122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+5123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+5124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+5125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+5126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+5127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+5128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+5129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+ARM GAS  /tmp/cc3JIfda.s 			page 92
+
+
+5130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+5140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+5141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Rank4_Channel This parameter can be one of the following values:
+5142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+5143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+5144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+5145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+5146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+5147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+5148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+5159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+5160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+5161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+5162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+5163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+5164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+5165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+5166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+5167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+5168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+5169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+5170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+5171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+5172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+5182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+5183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+5184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
+5186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t TriggerSource,
+ARM GAS  /tmp/cc3JIfda.s 			page 93
+
+
+5187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t ExternalTriggerEdge,
+5188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t SequencerNbRanks,
+5189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t Rank1_Channel,
+5190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t Rank2_Channel,
+5191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t Rank3_Channel,
+5192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    uint32_t Rank4_Channel)
+5193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "Rankx_Channel" with bits position    */
+5195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */
+5196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */
+5197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* because containing other bits reserved for other purpose.                */
+5198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* If parameter "TriggerSource" is set to SW start, then parameter          */
+5199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* "ExternalTriggerEdge" is discarded.                                      */
+5200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
+5201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->JSQR,
+5202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JEXTSEL |
+5203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JEXTEN  |
+5204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JSQ4    |
+5205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JSQ3    |
+5206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JSQ2    |
+5207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JSQ1    |
+5208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_JSQR_JL,
+5209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (TriggerSource & ADC_JSQR_JEXTSEL)          |
+5210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (ExternalTriggerEdge * (is_trigger_not_sw)) |
+5211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+5212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+5213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+5214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+5215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              SequencerNbRanks
+5216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             );
+5217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+5218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+5221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+5224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+5225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set sampling time of the selected ADC channel
+5229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Unit: ADC clock cycles.
+5230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this device, sampling time is on channel scope: independently
+5231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of channel mapped on ADC group regular or injected.
+5232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
+5233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         converted:
+5234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         sampling time constraints must be respected (sampling time can be
+5235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         adjusted in function of ADC clock frequency and sampling time
+5236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         setting).
+5237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet for timings values (parameters TS_vrefint,
+5238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TS_temp, ...).
+5239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Conversion time is the addition of sampling time and processing time.
+5240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         On this STM32 series, ADC processing time is:
+5241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
+5242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
+5243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+ARM GAS  /tmp/cc3JIfda.s 			page 94
+
+
+5244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+5245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of ADC conversion of internal channel (VrefInt,
+5246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         temperature sensor, ...), a sampling time minimum value
+5247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is required.
+5248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet.
+5249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+5250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+5251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+5252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+5253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n
+5254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n
+5255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n
+5256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n
+5257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n
+5258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n
+5259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n
+5260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n
+5261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n
+5262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n
+5263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
+5264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
+5265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
+5266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
+5267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
+5268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
+5269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
+5270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
+5271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime
+5272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be one of the following values:
+5274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+5275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+5276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+5277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+5278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+5279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+5280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+5291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+5292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+5293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+5294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+5295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+5296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+5297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+5298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+5299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+5300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+ARM GAS  /tmp/cc3JIfda.s 			page 95
+
+
+5301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+5302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+5303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+5304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+5314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+5315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SamplingTime This parameter can be one of the following values:
+5316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)
+5317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+5318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+5319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
+5320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
+5321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
+5322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
+5323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
+5324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles
+5326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             can be replaced by 3.5 ADC clock cycles.
+5327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
+5328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+5329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t Sa
+5331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+  62              		.loc 2 5331 1 is_stmt 1 view -0
+  63              		.cfi_startproc
+  64              		@ args = 0, pretend = 0, frame = 0
+  65              		@ frame_needed = 0, uses_anonymous_args = 0
+  66              		@ link register save eliminated.
+  67              		.loc 2 5331 1 is_stmt 0 view .LVU5
+  68 0000 10B4     		push	{r4}
+  69              	.LCFI0:
+  70              		.cfi_def_cfa_offset 4
+  71              		.cfi_offset 4, -4
+5332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "SamplingTime" with bits position     */
+5333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* in register and register position depending on parameter "Channel".      */
+5334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameter "Channel" is used with masks because containing                */
+5335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* other bits reserved for other purpose.                                   */
+5336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_M
+  72              		.loc 2 5336 3 is_stmt 1 view .LVU6
+  73              		.loc 2 5336 25 is_stmt 0 view .LVU7
+  74 0002 1430     		adds	r0, r0, #20
+  75              	.LVL3:
+  76              		.loc 2 5336 25 view .LVU8
+  77 0004 4B0E     		lsrs	r3, r1, #25
+  78 0006 9B00     		lsls	r3, r3, #2
+  79 0008 03F00403 		and	r3, r3, #4
+  80              	.LVL4:
+5337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+ARM GAS  /tmp/cc3JIfda.s 			page 96
+
+
+  81              		.loc 2 5338 3 is_stmt 1 view .LVU9
+  82 000c C458     		ldr	r4, [r0, r3]
+  83 000e C1F30451 		ubfx	r1, r1, #20, #5
+  84              	.LVL5:
+  85              		.loc 2 5338 3 is_stmt 0 view .LVU10
+  86 0012 4FF0070C 		mov	ip, #7
+  87 0016 0CFA01FC 		lsl	ip, ip, r1
+  88 001a 24EA0C0C 		bic	ip, r4, ip
+  89 001e 8A40     		lsls	r2, r2, r1
+  90              	.LVL6:
+  91              		.loc 2 5338 3 view .LVU11
+  92 0020 4CEA0202 		orr	r2, ip, r2
+  93 0024 C250     		str	r2, [r0, r3]
+5339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BIT
+5340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BIT
+5341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+  94              		.loc 2 5341 1 view .LVU12
+  95 0026 5DF8044B 		ldr	r4, [sp], #4
+  96              	.LCFI1:
+  97              		.cfi_restore 4
+  98              		.cfi_def_cfa_offset 0
+  99 002a 7047     		bx	lr
+ 100              		.cfi_endproc
+ 101              	.LFE195:
+ 103              		.section	.text.HAL_ADCEx_Calibration_Start,"ax",%progbits
+ 104              		.align	1
+ 105              		.global	HAL_ADCEx_Calibration_Start
+ 106              		.syntax unified
+ 107              		.thumb
+ 108              		.thumb_func
+ 110              	HAL_ADCEx_Calibration_Start:
+ 111              	.LVL7:
+ 112              	.LFB329:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @file    stm32g4xx_hal_adc_ex.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief   This file provides firmware functions to manage the following
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *          functionalities of the Analog to Digital Converter (ADC)
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *          peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *           + Peripheral Control functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *          Other functions (generic functions) are available in file
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *          "stm32g4xx_hal_adc.c".
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ******************************************************************************
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @attention
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * Copyright (c) 2019 STMicroelectronics.
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * All rights reserved.
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * in the root directory of this software component.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ******************************************************************************
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   @verbatim
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   [..]
+ARM GAS  /tmp/cc3JIfda.s 			page 97
+
+
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   (@) Sections "ADC peripheral features" and "How to use this driver" are
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       available in file of generic functions "stm32g4xx_hal_adc.c".
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   [..]
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   @endverbatim
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ******************************************************************************
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* Includes ------------------------------------------------------------------*/
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #include "stm32g4xx_hal.h"
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @{
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /** @defgroup ADCEx ADCEx
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief ADC Extended HAL module driver
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @{
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #ifdef HAL_ADC_MODULE_ENABLED
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* Private typedef -----------------------------------------------------------*/
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* Private define ------------------------------------------------------------*/
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @{
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #define ADC_JSQR_FIELDS  ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                            ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                            ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))  /*!< ADC_JSQR fields of parameters tha
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* Fixed timeout value for ADC calibration.                                   */
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* Values defined to be higher than worst cases: low clock frequency,         */
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* maximum prescalers.                                                        */
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* Ex of profile low frequency : f_ADC at f_CPU/3968 (minimum value           */
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* considering both possible ADC clocking scheme:                             */
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /*        - ADC clock from synchronous clock with AHB prescaler 512,          */
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /*          ADC prescaler 4.                                                  */
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /*           Ratio max = 512 *4 = 2048                                        */
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /*        - ADC clock from asynchronous clock (PLLP) with prescaler 256.      */
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /*          Highest CPU clock PLL (PLLR).                                     */
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /*           Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256    */
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /*                     = 3968 )                                               */
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* Calibration_time MAX = 81 / f_ADC                                          */
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /*                      = 81 / (f_CPU/3938) = 318978 CPU cycles               */
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #define ADC_CALIBRATION_TIMEOUT         (318978UL)   /*!< ADC calibration time-out value (unit: CPU
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @}
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* Private macro -------------------------------------------------------------*/
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* Private variables ---------------------------------------------------------*/
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* Private function prototypes -----------------------------------------------*/
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /* Exported functions --------------------------------------------------------*/
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ARM GAS  /tmp/cc3JIfda.s 			page 98
+
+
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @{
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief    Extended IO operation functions
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** @verbatim
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****  ===============================================================================
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                       ##### IO operation functions #####
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****  ===============================================================================
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     [..]  This section provides functions allowing to:
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Perform the ADC self-calibration for single or differential ending.
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Get calibration factors for single or differential ending.
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Set calibration factors for single or differential ending.
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Start conversion of ADC group injected.
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Stop conversion of ADC group injected.
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Poll for conversion complete on ADC group injected.
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Get result of ADC group injected channel conversion.
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Start conversion of ADC group injected and enable interruptions.
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Stop conversion of ADC group injected and disable interruptions.
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) When multimode feature is available, start multimode and enable DMA transfer.
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Stop multimode and disable ADC DMA transfer.
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Get result of multimode conversion.
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** @endverbatim
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @{
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Perform an ADC automatic self-calibration
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         Calibration prerequisite: ADC must be disabled (execute this
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param  hadc       ADC handle
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param  SingleDiff Selection of single-ended or differential input
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         This parameter can be one of the following values:
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 113              		.loc 1 126 1 is_stmt 1 view -0
+ 114              		.cfi_startproc
+ 115              		@ args = 0, pretend = 0, frame = 8
+ 116              		@ frame_needed = 0, uses_anonymous_args = 0
+ 117              		.loc 1 126 1 is_stmt 0 view .LVU14
+ 118 0000 30B5     		push	{r4, r5, lr}
+ 119              	.LCFI2:
+ 120              		.cfi_def_cfa_offset 12
+ 121              		.cfi_offset 4, -12
+ 122              		.cfi_offset 5, -8
+ 123              		.cfi_offset 14, -4
+ 124 0002 83B0     		sub	sp, sp, #12
+ARM GAS  /tmp/cc3JIfda.s 			page 99
+
+
+ 125              	.LCFI3:
+ 126              		.cfi_def_cfa_offset 24
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 127              		.loc 1 127 3 is_stmt 1 view .LVU15
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __IO uint32_t wait_loop_index = 0UL;
+ 128              		.loc 1 128 3 view .LVU16
+ 129              		.loc 1 128 17 is_stmt 0 view .LVU17
+ 130 0004 0023     		movs	r3, #0
+ 131 0006 0193     		str	r3, [sp, #4]
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 132              		.loc 1 131 3 is_stmt 1 view .LVU18
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+ 133              		.loc 1 132 3 view .LVU19
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process locked */
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 134              		.loc 1 135 3 view .LVU20
+ 135              		.loc 1 135 3 view .LVU21
+ 136 0008 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 137 000c 012B     		cmp	r3, #1
+ 138 000e 41D0     		beq	.L11
+ 139 0010 0446     		mov	r4, r0
+ 140 0012 0D46     		mov	r5, r1
+ 141              		.loc 1 135 3 discriminator 2 view .LVU22
+ 142 0014 0123     		movs	r3, #1
+ 143 0016 80F85830 		strb	r3, [r0, #88]
+ 144              		.loc 1 135 3 discriminator 2 view .LVU23
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Calibration prerequisite: ADC must be disabled. */
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Disable the ADC (if not already disabled) */
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_hal_status = ADC_Disable(hadc);
+ 145              		.loc 1 140 3 discriminator 2 view .LVU24
+ 146              		.loc 1 140 20 is_stmt 0 discriminator 2 view .LVU25
+ 147 001a FFF7FEFF 		bl	ADC_Disable
+ 148              	.LVL8:
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check if ADC is effectively disabled */
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (tmp_hal_status == HAL_OK)
+ 149              		.loc 1 143 3 is_stmt 1 discriminator 2 view .LVU26
+ 150              		.loc 1 143 6 is_stmt 0 discriminator 2 view .LVU27
+ 151 001e 80BB     		cbnz	r0, .L6
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Set ADC state */
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     ADC_STATE_CLR_SET(hadc->State,
+ 152              		.loc 1 146 5 is_stmt 1 view .LVU28
+ 153 0020 E36D     		ldr	r3, [r4, #92]
+ 154 0022 23F48853 		bic	r3, r3, #4352
+ 155 0026 23F00203 		bic	r3, r3, #2
+ 156 002a 43F00203 		orr	r3, r3, #2
+ 157 002e E365     		str	r3, [r4, #92]
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                       HAL_ADC_STATE_BUSY_INTERNAL);
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Start ADC calibration in mode single-ended or differential */
+ARM GAS  /tmp/cc3JIfda.s 			page 100
+
+
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
+ 158              		.loc 1 151 5 view .LVU29
+ 159 0030 2268     		ldr	r2, [r4]
+ 160              	.LVL9:
+ 161              	.LBB284:
+ 162              	.LBI284:
+5342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get sampling time of the selected ADC channel
+5345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Unit: ADC clock cycles.
+5346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this device, sampling time is on channel scope: independently
+5347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         of channel mapped on ADC group regular or injected.
+5348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Conversion time is the addition of sampling time and processing time.
+5349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         On this STM32 series, ADC processing time is:
+5350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
+5351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
+5352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+5353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+5354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n
+5355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n
+5356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n
+5357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n
+5358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n
+5359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n
+5360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n
+5361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n
+5362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n
+5363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n
+5364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
+5365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
+5366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
+5367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
+5368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
+5369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
+5370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
+5371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
+5372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime
+5373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be one of the following values:
+5375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_0
+5376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+5377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+5378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+5379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+5380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+5381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_16
+5392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_17
+ARM GAS  /tmp/cc3JIfda.s 			page 101
+
+
+5393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_18
+5394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+5395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+5396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+5397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+5398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+5399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+5400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+5401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+5402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+5403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+5404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+5405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock 
+5415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 A
+5416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+5417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)
+5418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+5419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+5420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
+5421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
+5422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
+5423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
+5424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
+5425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles
+5427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             can be replaced by 3.5 ADC clock cycles.
+5428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
+5429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+5431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOF
+5433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(*preg,
+5435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_
+5436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                     >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_P
+5437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                    );
+5438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+5439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set mode single-ended or differential input of the selected
+5442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC channel.
+5443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Channel ending is on channel scope: independently of channel mapped
+5444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on ADC group regular or injected.
+5445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         In differential mode: Differential measurement is carried out
+5446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         between the selected channel 'i' (positive input) and
+5447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         channel 'i+1' (negative input). Only channel 'i' has to be
+5448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         configured, channel 'i+1' is configured automatically.
+5449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Refer to Reference Manual to ensure the selected channel is
+ARM GAS  /tmp/cc3JIfda.s 			page 102
+
+
+5450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         available in differential mode.
+5451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         For example, internal channels (VrefInt, TempSensor, ...) are
+5452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         not available in differential mode.
+5453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   When configuring a channel 'i' in differential mode,
+5454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the channel 'i+1' is not usable separately.
+5455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On STM32G4, some channels are internally fixed to single-ended inputs
+5456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         configuration:
+5457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC1: Channels 12, 15, 16, 17 and 18
+5458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC2: Channels 15, 17 and 18
+5459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC3: Channels 12, 16, 17 and 18            (1)
+5460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC4: Channels 16, 17 and 18                (1)
+5461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC5: Channels 2, 3, 4, 16, 17 and 18       (1)
+5462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) ADC3/4/5 are not available on all devices, refer to device datasheet
+5463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             for more details.
+5464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For ADC channels configured in differential mode, both inputs
+5465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         should be biased at (Vref+)/2 +/-200mV.
+5466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (Vref+ is the analog voltage reference)
+5467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+5468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+5469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled.
+5470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   One or several values can be selected.
+5471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+5472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DIFSEL   DIFSEL         LL_ADC_SetChannelSingleDiff
+5473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be one of the following values:
+5475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1
+5476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2
+5477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3
+5478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4
+5479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5
+5480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SingleDiff This parameter can be a combination of the following values:
+5491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SINGLE_ENDED
+5492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+5493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+5494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t Sing
+5496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Bits for single or differential mode selection for each channel are set  */
+5498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* to 1 only when the differential mode is selected, and to 0 when the      */
+5499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* single mode is selected.                                                 */
+5500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   
+5501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   if (SingleDiff == LL_ADC_DIFFERENTIAL_ENDED)
+5502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+5503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     SET_BIT(ADCx->DIFSEL,
+5504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+5505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   }
+5506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   else
+ARM GAS  /tmp/cc3JIfda.s 			page 103
+
+
+5507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+5508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     CLEAR_BIT(ADCx->DIFSEL,
+5509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+5510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   }
+5511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+5512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get mode single-ended or differential input of the selected
+5515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC channel.
+5516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   When configuring a channel 'i' in differential mode,
+5517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the channel 'i+1' is not usable separately.
+5518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Therefore, to ensure a channel is configured in single-ended mode,
+5519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the configuration of channel itself and the channel 'i-1' must be
+5520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         read back (to ensure that the selected channel channel has not been
+5521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         configured in differential mode by the previous channel).
+5522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Refer to Reference Manual to ensure the selected channel is
+5523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         available in differential mode.
+5524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         For example, internal channels (VrefInt, TempSensor, ...) are
+5525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         not available in differential mode.
+5526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   When configuring a channel 'i' in differential mode,
+5527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the channel 'i+1' is not usable separately.
+5528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On STM32G4, some channels are internally fixed to single-ended inputs
+5529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         configuration:
+5530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC1: Channels 12, 15, 16, 17 and 18
+5531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC2: Channels 15, 17 and 18
+5532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC3: Channels 12, 16, 17 and 18            (1)
+5533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC4: Channels 16, 17 and 18                (1)
+5534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC5: Channels 2, 3, 4, 16, 17 and 18       (1)
+5535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) ADC3/4/5 are not available on all devices, refer to device datasheet
+5536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             for more details.
+5537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   One or several values can be selected. In this case, the value
+5538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         returned is null if all channels are in single ended-mode.
+5539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+5540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSingleDiff
+5541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Channel This parameter can be a combination of the following values:
+5543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_1
+5544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_2
+5545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_3
+5546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_4
+5547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_5
+5548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_6
+5549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_7
+5550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_8
+5551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_9
+5552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_10
+5553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_11
+5554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_12
+5555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_13
+5556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_14
+5557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_CHANNEL_15
+5558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: channel in single-ended mode, else: channel in differential mode
+5559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
+5561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
+5563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/cc3JIfda.s 			page 104
+
+
+5564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+5567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: an
+5570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+5571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC analog watchdog monitored channels:
+5575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a single channel, multiple channels or all channels,
+5576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on ADC groups regular and-or injected.
+5577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Once monitored channels are selected, analog watchdog
+5578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is enabled.
+5579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of need to define a single channel to monitor
+5580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         with analog watchdog from sequencer channel definition,
+5581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+5582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, there are 2 kinds of analog watchdog
+5583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         instance:
+5584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD standard (instance AWD1):
+5585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: can monitor 1 channel or all channels.
+5586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: ADC groups regular and-or injected.
+5587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is not limited (corresponds to
+5588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC resolution configured).
+5589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD flexible (instances AWD2, AWD3):
+5590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: flexible on channels monitored, selection is
+5591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             channel wise, from from 1 to all channels.
+5592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Specificity of this analog watchdog: Multiple channels can
+5593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             be selected. For example:
+5594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+5595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: not selection possible (monitoring on both
+5596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             groups regular and injected).
+5597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Channels selected are monitored on groups regular and injected:
+5598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+5599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+5600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+5601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+5602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             the 2 LSB are ignored.
+5603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+5604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+5605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+5606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+5607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
+5608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
+5609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
+5610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n
+5611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
+5612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
+5613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+5615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+5616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD2
+5617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD3
+5618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDChannelGroup This parameter can be one of the following values:
+5619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_DISABLE
+5620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+ARM GAS  /tmp/cc3JIfda.s 			page 105
+
+
+5621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+5622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+5623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+5624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+5625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+5626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+5627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+5628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+5629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+5630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+5631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+5632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+5633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+5634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+5635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+5636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+5637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+5638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+5639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+5640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+5641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+5642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+5643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+5644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+5645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+5646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+5647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+5648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+5649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+5650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+5651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+5652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+5653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+5654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+5655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+5656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+5657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+5658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+5659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+5660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+5661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+5662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+5663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+5664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+5665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+5666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+5667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+5668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+5669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+5670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+5671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+5672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+5673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+5674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+5675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+5676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+5677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+ARM GAS  /tmp/cc3JIfda.s 			page 106
+
+
+5678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+5679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+5680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
+5681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
+5682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+5683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG  (0)(1)
+5684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ  (0)(1)
+5685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
+5686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG  (0)(5)
+5687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ  (0)(5)
+5688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
+5689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(6)
+5690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(6)
+5691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (6)
+5692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (0)(1)
+5693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (0)(1)
+5694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ         (1)
+5695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (0)(2)
+5696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (0)(2)
+5697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ         (2)
+5698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     (0)(2)
+5699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     (0)(2)
+5700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ    (2)
+5701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     (0)(3)
+5702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     (0)(3)
+5703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ    (3)
+5704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG          (0)(5)
+5705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ          (0)(5)
+5706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ         (5)
+5707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG          (0)(5)
+5708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ          (0)(5)
+5709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ         (5)
+5710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG          (0)(4)
+5711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ          (0)(4)
+5712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ         (4)
+5713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
+5715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+5716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+5717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+5718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+5719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+5720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+5721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+5722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device da
+5723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+5724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWD
+5726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
+5728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* in register and register position depending on parameter "AWDy".         */
+5729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
+5730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* containing other bits reserved for other purpose.                        */
+5731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> AD
+5732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_C
+5733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+ARM GAS  /tmp/cc3JIfda.s 			page 107
+
+
+5735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+5736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              AWDChannelGroup & AWDy);
+5737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+5738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC analog watchdog monitored channel.
+5741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Usage of the returned channel number:
+5742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To reinject this channel into another function LL_ADC_xxx:
+5743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the returned channel number is only partly formatted on definition
+5744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+5745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           with parts of literals LL_ADC_CHANNEL_x or using
+5746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+5747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Then the selected literal LL_ADC_CHANNEL_x can be used
+5748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           as parameter for another function.
+5749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - To get the channel number in decimal format:
+5750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           process the returned value with the helper macro
+5751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+5752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           Applicable only when the analog watchdog is set to monitor
+5753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           one channel.
+5754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, there are 2 kinds of analog watchdog
+5755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         instance:
+5756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD standard (instance AWD1):
+5757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: can monitor 1 channel or all channels.
+5758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: ADC groups regular and-or injected.
+5759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is not limited (corresponds to
+5760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC resolution configured).
+5761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD flexible (instances AWD2, AWD3):
+5762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: flexible on channels monitored, selection is
+5763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             channel wise, from from 1 to all channels.
+5764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Specificity of this analog watchdog: Multiple channels can
+5765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             be selected. For example:
+5766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+5767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: not selection possible (monitoring on both
+5768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             groups regular and injected).
+5769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Channels selected are monitored on groups regular and injected:
+5770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+5771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+5772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+5773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+5774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             the 2 LSB are ignored.
+5775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+5776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+5777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+5778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+5779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
+5780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
+5781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
+5782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n
+5783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
+5784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
+5785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+5787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+5788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD2 (1)
+5789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD3 (1)
+5790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) On this AWD number, monitored channel can be retrieved
+ARM GAS  /tmp/cc3JIfda.s 			page 108
+
+
+5792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             if only 1 channel is programmed (or none or all channels).
+5793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             This function cannot retrieve monitored channel if
+5794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             multiple channels are programmed simultaneously
+5795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             by bitfield.
+5796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+5797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_DISABLE
+5798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+5799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+5800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+5801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+5802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+5803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+5804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+5805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+5806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+5807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+5808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+5809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+5810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+5811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+5812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+5813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+5814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+5815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+5816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+5817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+5818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+5819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+5820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+5821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+5822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+5823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+5824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+5825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+5826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+5827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+5828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+5829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+5830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+5831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+5832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+5833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+5834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+5835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+5836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+5837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+5838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+5839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+5840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+5841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+5842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+5843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+5844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+5845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+5846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+5847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+5848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ARM GAS  /tmp/cc3JIfda.s 			page 109
+
+
+5849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+5850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+5851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+5852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+5853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+5854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+5855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+5856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+5857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+5858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+5859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.
+5860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
+5862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)
+5864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC
+5865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK);
+5867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */
+5869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* (parameter value LL_ADC_AWD_DISABLE).                                    */
+5870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Else, the selected AWD is enabled and is monitoring a group of channels  */
+5871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* or a single channel.                                                     */
+5872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   if (AnalogWDMonitChannels != 0UL)
+5873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+5874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     if (AWDy == LL_ADC_AWD1)
+5875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     {
+5876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
+5877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       {
+5878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         /* AWD monitoring a group of channels */
+5879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         AnalogWDMonitChannels = ((AnalogWDMonitChannels
+5880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                   | (ADC_AWD_CR23_CHANNEL_MASK)
+5881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                  )
+5882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                  & (~(ADC_CFGR_AWD1CH))
+5883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                 );
+5884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       }
+5885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       else
+5886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       {
+5887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         /* AWD monitoring a single channel */
+5888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         AnalogWDMonitChannels = (AnalogWDMonitChannels
+5889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                  | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1C
+5890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                 );
+5891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       }
+5892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     }
+5893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     else
+5894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     {
+5895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
+5896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       {
+5897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         /* AWD monitoring a group of channels */
+5898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
+5899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                  | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
+5900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                 );
+5901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       }
+5902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       else
+5903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       {
+5904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         /* AWD monitoring a single channel */
+5905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         /* AWD monitoring a group of channels */
+ARM GAS  /tmp/cc3JIfda.s 			page 110
+
+
+5906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****         AnalogWDMonitChannels = (AnalogWDMonitChannels
+5907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                  | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
+5908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                  | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CF
+5909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                 );
+5910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****       }
+5911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****     }
+5912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   }
+5913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return AnalogWDMonitChannels;
+5915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+5916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC analog watchdog thresholds value of both thresholds
+5919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         high and low.
+5920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If value of only one threshold high or low must be set,
+5921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_SetAnalogWDThresholds().
+5922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of ADC resolution different of 12 bits,
+5923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog thresholds data require a specific shift.
+5924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+5925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, there are 2 kinds of analog watchdog
+5926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         instance:
+5927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD standard (instance AWD1):
+5928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: can monitor 1 channel or all channels.
+5929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: ADC groups regular and-or injected.
+5930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is not limited (corresponds to
+5931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC resolution configured).
+5932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD flexible (instances AWD2, AWD3):
+5933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: flexible on channels monitored, selection is
+5934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             channel wise, from from 1 to all channels.
+5935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Specificity of this analog watchdog: Multiple channels can
+5936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             be selected. For example:
+5937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+5938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: not selection possible (monitoring on both
+5939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             groups regular and injected).
+5940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Channels selected are monitored on groups regular and injected:
+5941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+5942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+5943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+5944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+5945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             the 2 LSB are ignored.
+5946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
+5947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         impacted: the comparison of analog watchdog thresholds is done on
+5948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         oversampling final computation (after ratio and shift application):
+5949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC data register bitfield [15:4] (12 most significant bits).
+5950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll TR1      HT1            LL_ADC_ConfigAnalogWDThresholds\n
+5951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR2      HT2            LL_ADC_ConfigAnalogWDThresholds\n
+5952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR3      HT3            LL_ADC_ConfigAnalogWDThresholds\n
+5953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\n
+5954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\n
+5955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds
+5956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+5957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+5958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+5959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD2
+5960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD3
+5961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
+5962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ARM GAS  /tmp/cc3JIfda.s 			page 111
+
+
+5963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+5964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+5965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWD
+5966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                      uint32_t AWDThresholdLowValue)
+5967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+5968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
+5969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* position in register and register position depending on parameter        */
+5970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* "AWDy".                                                                  */
+5971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
+5972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* containing other bits reserved for other purpose.                        */
+5973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC
+5974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+5976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_TR1_HT1 | ADC_TR1_LT1,
+5977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
+5978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+5979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+5980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+5981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC analog watchdog threshold value of threshold
+5982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         high or low.
+5983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If values of both thresholds high or low must be set,
+5984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
+5985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of ADC resolution different of 12 bits,
+5986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog thresholds data require a specific shift.
+5987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+5988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, there are 2 kinds of analog watchdog
+5989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         instance:
+5990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD standard (instance AWD1):
+5991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: can monitor 1 channel or all channels.
+5992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: ADC groups regular and-or injected.
+5993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is not limited (corresponds to
+5994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             ADC resolution configured).
+5995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - AWD flexible (instances AWD2, AWD3):
+5996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - channels monitored: flexible on channels monitored, selection is
+5997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             channel wise, from from 1 to all channels.
+5998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Specificity of this analog watchdog: Multiple channels can
+5999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             be selected. For example:
+6000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+6001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - groups monitored: not selection possible (monitoring on both
+6002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             groups regular and injected).
+6003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             Channels selected are monitored on groups regular and injected:
+6004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+6005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+6006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+6007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+6008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *             the 2 LSB are ignored.
+6009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
+6010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         impacted: the comparison of analog watchdog thresholds is done on
+6011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         oversampling final computation (after ratio and shift application):
+6012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC data register bitfield [15:4] (12 most significant bits).
+6013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is not conditioned to
+6014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC can be disabled, enabled with or without conversion on going
+6016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either ADC groups regular or injected.
+6017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n
+6018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n
+6019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n
+ARM GAS  /tmp/cc3JIfda.s 			page 112
+
+
+6020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n
+6021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n
+6022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR3      LT3            LL_ADC_SetAnalogWDThresholds
+6023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+6025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+6026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD2
+6027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD3
+6028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+6029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+6030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+6031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+6032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThr
+6035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                   uint32_t AWDThresholdValue)
+6036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Set bits with content of parameter "AWDThresholdValue" with bits         */
+6038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* position in register and register position depending on parameters       */
+6039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* "AWDThresholdsHighLow" and "AWDy".                                       */
+6040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
+6041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* containing other bits reserved for other purpose.                        */
+6042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+6043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                              ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_RE
+6044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(*preg,
+6046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              AWDThresholdsHighLow,
+6047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TR
+6048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC analog watchdog threshold value of threshold high,
+6052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         threshold low or raw data with ADC thresholds high and low
+6053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         concatenated.
+6054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If raw data with ADC thresholds high and low is retrieved,
+6055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the data of each threshold high or low can be isolated
+6056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         using helper macro:
+6057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
+6058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of ADC resolution different of 12 bits,
+6059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog thresholds data require a specific shift.
+6060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+6061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n
+6062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n
+6063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n
+6064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n
+6065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n
+6066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         TR3      LT3            LL_ADC_GetAnalogWDThresholds
+6067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+6069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+6070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD2
+6071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD3
+6072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+6073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+6074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+6075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
+6076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ARM GAS  /tmp/cc3JIfda.s 			page 113
+
+
+6077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AW
+6079:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6080:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+6081:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                    ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_
+6082:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6083:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(*preg,
+6084:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              (AWDThresholdsHighLow | ADC_TR1_LT1))
+6085:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                     >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH
+6086:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                         & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
+6087:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6088:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6089:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6090:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC analog watchdog filtering configuration
+6091:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6092:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6093:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+6094:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+6095:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, this feature is only available on first
+6096:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog (AWD1)
+6097:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll TR1      AWDFILT        LL_ADC_SetAWDFilteringConfiguration
+6098:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6099:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+6100:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+6101:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  FilteringConfig This parameter can be one of the following values:
+6102:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_NONE
+6103:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+6104:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+6105:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+6106:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+6107:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+6108:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+6109:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+6110:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6111:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6112:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t
+6113:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6114:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Prevent unused argument(s) compilation warning */
+6115:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (void)(AWDy);
+6116:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
+6117:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6118:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6119:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6120:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC analog watchdog filtering configuration
+6121:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, this feature is only available on first
+6122:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         analog watchdog (AWD1)
+6123:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll TR1      AWDFILT        LL_ADC_GetAWDFilteringConfiguration
+6124:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6125:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  AWDy This parameter can be one of the following values:
+6126:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD1
+6127:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be:
+6128:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_NONE
+6129:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+6130:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+6131:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+6132:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+6133:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+ARM GAS  /tmp/cc3JIfda.s 			page 114
+
+
+6134:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+6135:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+6136:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6137:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy)
+6138:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6139:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Prevent unused argument(s) compilation warning */
+6140:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   (void)(AWDy);
+6141:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
+6142:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6143:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6144:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6145:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+6146:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6147:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6148:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: over
+6149:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+6150:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6151:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6152:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6153:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC oversampling scope: ADC groups regular and-or injected
+6154:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (availability of ADC group injected depends on STM32 families).
+6155:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If both groups regular and injected are selected,
+6156:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         specify behavior of ADC group injected interrupting
+6157:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         group regular: when ADC group injected is triggered,
+6158:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the oversampling on ADC group regular is either
+6159:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         temporary stopped and continued, or resumed from start
+6160:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (oversampler buffer reset).
+6161:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6162:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6163:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+6164:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+6165:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n
+6166:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n
+6167:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope
+6168:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6169:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  OvsScope This parameter can be one of the following values:
+6170:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_DISABLE
+6171:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+6172:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+6173:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
+6174:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+6175:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6176:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6177:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
+6178:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6179:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
+6180:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6181:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6182:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6183:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC oversampling scope: ADC groups regular and-or injected
+6184:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (availability of ADC group injected depends on STM32 families).
+6185:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If both groups regular and injected are selected,
+6186:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         specify behavior of ADC group injected interrupting
+6187:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         group regular: when ADC group injected is triggered,
+6188:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         the oversampling on ADC group regular is either
+6189:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         temporary stopped and continued, or resumed from start
+6190:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (oversampler buffer reset).
+ARM GAS  /tmp/cc3JIfda.s 			page 115
+
+
+6191:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n
+6192:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n
+6193:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope
+6194:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6195:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+6196:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_DISABLE
+6197:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+6198:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+6199:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
+6200:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+6201:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6202:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
+6203:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6204:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
+6205:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6206:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6207:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6208:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC oversampling discontinuous mode (triggered mode)
+6209:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on the selected ADC group.
+6210:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Number of oversampled conversions are done either in:
+6211:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - continuous mode (all conversions of oversampling ratio
+6212:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           are done from 1 trigger)
+6213:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - discontinuous mode (each conversion of oversampling ratio
+6214:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           needs a trigger)
+6215:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6216:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6217:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+6218:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on group regular.
+6219:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, oversampling discontinuous mode
+6220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (triggered mode) can be used only when oversampling is
+6221:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         set on group regular only and in resumed mode.
+6222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont
+6223:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  OverSamplingDiscont This parameter can be one of the following values:
+6225:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_REG_CONT
+6226:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_REG_DISCONT
+6227:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6228:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6229:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
+6230:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6231:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
+6232:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6233:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6234:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6235:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC oversampling discontinuous mode (triggered mode)
+6236:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on the selected ADC group.
+6237:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   Number of oversampled conversions are done either in:
+6238:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - continuous mode (all conversions of oversampling ratio
+6239:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           are done from 1 trigger)
+6240:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - discontinuous mode (each conversion of oversampling ratio
+6241:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           needs a trigger)
+6242:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont
+6243:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6244:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+6245:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_REG_CONT
+6246:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_REG_DISCONT
+6247:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+ARM GAS  /tmp/cc3JIfda.s 			page 116
+
+
+6248:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
+6249:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6250:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
+6251:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6252:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6253:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6254:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC oversampling
+6255:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (impacting both ADC groups regular and injected)
+6256:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function set the 2 items of oversampling configuration:
+6257:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ratio
+6258:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - shift
+6259:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6260:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6261:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be disabled or enabled without conversion on going
+6262:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+6263:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
+6264:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
+6265:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6266:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Ratio This parameter can be one of the following values:
+6267:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_2
+6268:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_4
+6269:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_8
+6270:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_16
+6271:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_32
+6272:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_64
+6273:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_128
+6274:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_256
+6275:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Shift This parameter can be one of the following values:
+6276:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+6277:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+6278:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+6279:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+6280:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+6281:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+6282:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+6283:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+6284:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+6285:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6286:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6287:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_
+6288:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6289:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
+6290:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6291:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6292:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6293:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC oversampling ratio
+6294:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *        (impacting both ADC groups regular and injected)
+6295:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
+6296:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6297:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Ratio This parameter can be one of the following values:
+6298:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_2
+6299:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_4
+6300:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_8
+6301:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_16
+6302:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_32
+6303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_64
+6304:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_128
+ARM GAS  /tmp/cc3JIfda.s 			page 117
+
+
+6305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_RATIO_256
+6306:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
+6308:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6309:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
+6310:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6311:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6312:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6313:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC oversampling shift
+6314:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *        (impacting both ADC groups regular and injected)
+6315:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
+6316:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6317:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Shift This parameter can be one of the following values:
+6318:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+6319:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+6320:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+6321:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+6322:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+6323:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+6324:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+6325:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+6326:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+6327:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6328:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
+6329:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6330:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
+6331:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6332:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6333:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6334:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+6335:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6336:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6337:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multim
+6338:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+6339:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6340:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6341:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+6342:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6343:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC multimode configuration to operate in independent mode
+6344:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or multimode (for devices with several ADC instances).
+6345:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If multimode configuration: the selected ADC instance is
+6346:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         either master or slave depending on hardware.
+6347:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to reference manual.
+6348:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6349:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6350:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         All ADC instances of the ADC common group must be disabled.
+6351:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+6352:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instance or by using helper macro
+6353:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+6354:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      DUAL           LL_ADC_SetMultimode
+6355:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6356:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6357:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  Multimode This parameter can be one of the following values:
+6358:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+6359:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+6360:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+6361:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ARM GAS  /tmp/cc3JIfda.s 			page 118
+
+
+6362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+6363:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+6364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+6365:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+6366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6367:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6368:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
+6369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6370:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
+6371:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6372:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6373:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6374:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC multimode configuration to operate in independent mode
+6375:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or multimode (for devices with several ADC instances).
+6376:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If multimode configuration: the selected ADC instance is
+6377:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         either master or slave depending on hardware.
+6378:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to reference manual.
+6379:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      DUAL           LL_ADC_GetMultimode
+6380:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6381:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6382:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+6383:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+6384:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+6385:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+6386:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+6387:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+6388:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+6389:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+6390:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+6391:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
+6393:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
+6395:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6396:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6397:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6398:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC multimode conversion data transfer: no transfer
+6399:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or transfer by DMA.
+6400:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC multimode transfer by DMA is not selected:
+6401:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         each ADC uses its own DMA channel, with its individual
+6402:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         DMA transfer settings.
+6403:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         If ADC multimode transfer by DMA is selected:
+6404:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         One DMA channel is used for both ADC (DMA of ADC master)
+6405:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Specifies the DMA requests mode:
+6406:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Limited mode (One shot mode): DMA transfer requests are stopped
+6407:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           when number of DMA data transfers (number of
+6408:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions) is reached.
+6409:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode non-circular.
+6410:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Unlimited mode: DMA transfer requests are unlimited,
+6411:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           whatever number of DMA data transfers (number of
+6412:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions).
+6413:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode circular.
+6414:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+6415:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         mode non-circular:
+6416:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         when DMA transfers size will be reached, DMA will stop transfers of
+6417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversions data ADC will raise an overrun error
+6418:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (overrun flag and interruption if enabled).
+ARM GAS  /tmp/cc3JIfda.s 			page 119
+
+
+6419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   How to retrieve multimode conversion data:
+6420:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Whatever multimode transfer by DMA setting: using function
+6421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref LL_ADC_REG_ReadMultiConversionData32().
+6422:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         If ADC multimode transfer by DMA is selected: conversion data
+6423:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is a raw data with ADC master and slave concatenated.
+6424:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         A macro is available to get the conversion data of
+6425:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC master or ADC slave: see helper macro
+6426:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+6427:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6428:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6429:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         All ADC instances of the ADC common group must be disabled
+6430:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or enabled without conversion on going on group regular.
+6431:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\n
+6432:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      DMACFG         LL_ADC_SetMultiDMATransfer
+6433:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6434:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6435:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  MultiDMATransfer This parameter can be one of the following values:
+6436:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+6437:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+6438:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+6439:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+6440:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+6441:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6442:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6443:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMA
+6444:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6445:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
+6446:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6447:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6448:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6449:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC multimode conversion data transfer: no transfer
+6450:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or transfer by DMA.
+6451:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC multimode transfer by DMA is not selected:
+6452:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         each ADC uses its own DMA channel, with its individual
+6453:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         DMA transfer settings.
+6454:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         If ADC multimode transfer by DMA is selected:
+6455:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         One DMA channel is used for both ADC (DMA of ADC master)
+6456:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Specifies the DMA requests mode:
+6457:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Limited mode (One shot mode): DMA transfer requests are stopped
+6458:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           when number of DMA data transfers (number of
+6459:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions) is reached.
+6460:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode non-circular.
+6461:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - Unlimited mode: DMA transfer requests are unlimited,
+6462:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           whatever number of DMA data transfers (number of
+6463:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           ADC conversions).
+6464:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           This ADC mode is intended to be used with DMA mode circular.
+6465:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+6466:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         mode non-circular:
+6467:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         when DMA transfers size will be reached, DMA will stop transfers of
+6468:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversions data ADC will raise an overrun error
+6469:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (overrun flag and interruption if enabled).
+6470:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   How to retrieve multimode conversion data:
+6471:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Whatever multimode transfer by DMA setting: using function
+6472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref LL_ADC_REG_ReadMultiConversionData32().
+6473:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         If ADC multimode transfer by DMA is selected: conversion data
+6474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is a raw data with ADC master and slave concatenated.
+6475:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         A macro is available to get the conversion data of
+ARM GAS  /tmp/cc3JIfda.s 			page 120
+
+
+6476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC master or ADC slave: see helper macro
+6477:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+6478:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\n
+6479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CCR      DMACFG         LL_ADC_GetMultiDMATransfer
+6480:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6481:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6482:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+6483:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+6484:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+6485:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+6486:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+6487:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+6488:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6489:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
+6490:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6491:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
+6492:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6493:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6494:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Set ADC multimode delay between 2 sampling phases.
+6496:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   The sampling delay range depends on ADC resolution:
+6497:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC resolution 12 bits can have maximum delay of 12 cycles.
+6498:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC resolution 10 bits can have maximum delay of 10 cycles.
+6499:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC resolution  8 bits can have maximum delay of  8 cycles.
+6500:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - ADC resolution  6 bits can have maximum delay of  6 cycles.
+6501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6502:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         All ADC instances of the ADC common group must be disabled.
+6504:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+6505:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC instance or by using helper macro helper macro
+6506:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+6507:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay
+6508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6509:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6510:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  MultiTwoSamplingDelay This parameter can be one of the following values:
+6511:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+6512:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+6513:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+6514:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+6515:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+6516:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
+6517:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
+6518:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
+6519:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
+6520:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+6521:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+6522:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+6523:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+6524:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+6525:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+6526:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) Parameter available only if ADC resolution is 12 bits.
+6527:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6528:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6529:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Mul
+6530:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6531:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
+6532:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/cc3JIfda.s 			page 121
+
+
+6533:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6535:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC multimode delay between 2 sampling phases.
+6536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay
+6537:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6538:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6539:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Returned value can be one of the following values:
+6540:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+6541:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+6542:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+6543:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+6544:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+6545:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
+6546:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
+6547:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
+6548:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
+6549:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+6550:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+6551:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+6552:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *
+6553:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+6554:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+6555:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (3) Parameter available only if ADC resolution is 12 bits.
+6556:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6557:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
+6558:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6559:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
+6560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6561:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+6562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6564:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+6565:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6566:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+6567:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+6568:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6569:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6570:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6571:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Put ADC instance in deep power down state.
+6572:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
+6573:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         state, the internal analog calibration is lost. After exiting from
+6574:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         deep power down, calibration must be relaunched or calibration factor
+6575:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (preliminarily saved) must be set back into calibration register.
+6576:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6577:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6578:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled.
+6579:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown
+6580:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6581:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6582:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
+6584:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6585:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6586:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6587:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6589:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ARM GAS  /tmp/cc3JIfda.s 			page 122
+
+
+6590:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_DEEPPWD);
+6591:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6592:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6593:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6594:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable ADC deep power down mode.
+6595:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
+6596:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         state, the internal analog calibration is lost. After exiting from
+6597:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         deep power down, calibration must be relaunched or calibration factor
+6598:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (preliminarily saved) must be set back into calibration register.
+6599:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6600:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6601:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled.
+6602:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
+6603:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6604:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6605:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6606:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
+6607:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6608:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6609:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6610:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6611:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
+6612:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6613:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6614:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6615:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get the selected ADC instance deep power down state.
+6616:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
+6617:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6618:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: deep power down is disabled, 1: deep power down is enabled.
+6619:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6620:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
+6621:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6622:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
+6623:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6624:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6625:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6626:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable ADC instance internal voltage regulator.
+6627:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, after ADC internal voltage regulator enable,
+6628:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a delay for ADC internal voltage regulator stabilization
+6629:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is required before performing a ADC calibration or ADC enable.
+6630:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet, parameter tADCVREG_STUP.
+6631:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
+6632:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6633:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6634:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled.
+6635:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
+6636:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6637:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6638:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6639:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
+6640:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6641:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6642:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6643:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6644:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6645:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+6646:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADVREGEN);
+ARM GAS  /tmp/cc3JIfda.s 			page 123
+
+
+6647:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6648:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6649:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6650:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable ADC internal voltage regulator.
+6651:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6652:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6653:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled.
+6654:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
+6655:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6656:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6657:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
+6659:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
+6661:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6662:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6663:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6664:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get the selected ADC instance internal voltage regulator state.
+6665:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
+6666:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6667:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+6668:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6669:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
+6670:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6671:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
+6672:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6673:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6674:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6675:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Enable the selected ADC instance.
+6676:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, after ADC enable, a delay for
+6677:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC internal analog stabilization is required before performing a
+6678:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC conversion start.
+6679:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to device datasheet, parameter tSTAB.
+6680:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+6681:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is enabled and when conversion clock is active.
+6682:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (not only core clock: this ADC has a dual clock domain)
+6683:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6684:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6685:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
+6686:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADEN           LL_ADC_Enable
+6687:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6688:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6689:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6690:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+6691:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6692:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6693:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6694:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6695:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6696:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+6697:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADEN);
+6698:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6699:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6700:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6701:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Disable the selected ADC instance.
+6702:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6703:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+ARM GAS  /tmp/cc3JIfda.s 			page 124
+
+
+6704:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be not disabled. Must be enabled without conversion on going
+6705:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         on either groups regular or injected.
+6706:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADDIS          LL_ADC_Disable
+6707:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6708:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6709:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6710:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+6711:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6712:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6713:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6714:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6715:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6716:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+6717:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADDIS);
+6718:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6719:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6720:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6721:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get the selected ADC instance enable state.
+6722:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+6723:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         is enabled and when conversion clock is active.
+6724:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (not only core clock: this ADC has a dual clock domain)
+6725:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADEN           LL_ADC_IsEnabled
+6726:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6727:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: ADC is disabled, 1: ADC is enabled.
+6728:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+6730:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
+6732:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6733:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6734:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6735:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get the selected ADC instance disable state.
+6736:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
+6737:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6738:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: no ADC disable command on going.
+6739:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6740:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
+6741:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6742:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
+6743:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6744:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6745:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6746:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Start ADC calibration in the mode single-ended
+6747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or differential (for devices with differential mode available).
+6748:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, a minimum number of ADC clock cycles
+6749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         are required between ADC end of calibration and ADC enable.
+6750:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+6751:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with differential mode available:
+6752:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         Calibration of offset is specific to each of
+6753:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         single-ended and differential modes
+6754:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (calibration run must be performed for each of these
+6755:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         differential modes, if used afterwards and if the application
+6756:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         requires their calibration).
+6757:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6758:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6759:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be ADC disabled.
+6760:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n
+ARM GAS  /tmp/cc3JIfda.s 			page 125
+
+
+6761:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CR       ADCALDIF       LL_ADC_StartCalibration
+6762:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6763:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  SingleDiff This parameter can be one of the following values:
+6764:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_SINGLE_ENDED
+6765:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+6766:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6767:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6768:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+ 163              		.loc 2 6768 22 view .LVU30
+ 164              	.LBB285:
+6769:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6770:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6771:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6772:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6773:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+ 165              		.loc 2 6773 3 view .LVU31
+ 166 0032 9368     		ldr	r3, [r2, #8]
+ 167 0034 23F04043 		bic	r3, r3, #-1073741824
+ 168 0038 23F03F03 		bic	r3, r3, #63
+ 169 003c 05F08045 		and	r5, r5, #1073741824
+ 170              	.LVL10:
+ 171              		.loc 2 6773 3 is_stmt 0 view .LVU32
+ 172 0040 2B43     		orrs	r3, r3, r5
+ 173 0042 43F00043 		orr	r3, r3, #-2147483648
+ 174 0046 9360     		str	r3, [r2, #8]
+ 175              	.LVL11:
+ 176              	.L7:
+ 177              		.loc 2 6773 3 view .LVU33
+ 178              	.LBE285:
+ 179              	.LBE284:
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Wait for calibration completion */
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
+ 180              		.loc 1 154 56 is_stmt 1 view .LVU34
+ 181              		.loc 1 154 12 is_stmt 0 view .LVU35
+ 182 0048 2368     		ldr	r3, [r4]
+ 183              	.LVL12:
+ 184              	.LBB286:
+ 185              	.LBI286:
+6774:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
+6775:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
+6776:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6777:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6778:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6779:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC calibration state.
+6780:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
+6781:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6782:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: calibration complete, 1: calibration in progress.
+6783:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6784:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+ 186              		.loc 2 6784 26 is_stmt 1 view .LVU36
+ 187              	.LBB287:
+6785:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6786:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
+ 188              		.loc 2 6786 3 view .LVU37
+ 189              		.loc 2 6786 12 is_stmt 0 view .LVU38
+ 190 004a 9B68     		ldr	r3, [r3, #8]
+ARM GAS  /tmp/cc3JIfda.s 			page 126
+
+
+ 191              	.LVL13:
+ 192              		.loc 2 6786 70 view .LVU39
+ 193 004c 002B     		cmp	r3, #0
+ 194 004e 06DB     		blt	.L13
+ 195              	.LVL14:
+ 196              		.loc 2 6786 70 view .LVU40
+ 197              	.LBE287:
+ 198              	.LBE286:
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       wait_loop_index++;
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Update ADC state machine to error */
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         ADC_STATE_CLR_SET(hadc->State,
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_BUSY_INTERNAL,
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_ERROR_INTERNAL);
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Process unlocked */
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         __HAL_UNLOCK(hadc);
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         return HAL_ERROR;
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Set ADC state */
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     ADC_STATE_CLR_SET(hadc->State,
+ 199              		.loc 1 172 5 is_stmt 1 view .LVU41
+ 200 0050 E36D     		ldr	r3, [r4, #92]
+ 201 0052 23F00303 		bic	r3, r3, #3
+ 202 0056 43F00103 		orr	r3, r3, #1
+ 203 005a E365     		str	r3, [r4, #92]
+ 204 005c 15E0     		b	.L10
+ 205              	.LVL15:
+ 206              	.L13:
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
+ 207              		.loc 1 156 7 view .LVU42
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
+ 208              		.loc 1 156 22 is_stmt 0 view .LVU43
+ 209 005e 019B     		ldr	r3, [sp, #4]
+ 210 0060 0133     		adds	r3, r3, #1
+ 211 0062 0193     		str	r3, [sp, #4]
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 212              		.loc 1 157 7 is_stmt 1 view .LVU44
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 213              		.loc 1 157 27 is_stmt 0 view .LVU45
+ 214 0064 019A     		ldr	r2, [sp, #4]
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 215              		.loc 1 157 10 view .LVU46
+ 216 0066 0C4B     		ldr	r3, .L14
+ 217 0068 9A42     		cmp	r2, r3
+ 218 006a EDD9     		bls	.L7
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_BUSY_INTERNAL,
+ 219              		.loc 1 160 9 is_stmt 1 view .LVU47
+ 220 006c E36D     		ldr	r3, [r4, #92]
+ 221 006e 23F01203 		bic	r3, r3, #18
+ 222 0072 43F01003 		orr	r3, r3, #16
+ 223 0076 E365     		str	r3, [r4, #92]
+ARM GAS  /tmp/cc3JIfda.s 			page 127
+
+
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 224              		.loc 1 165 9 view .LVU48
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 225              		.loc 1 165 9 view .LVU49
+ 226 0078 0023     		movs	r3, #0
+ 227 007a 84F85830 		strb	r3, [r4, #88]
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 228              		.loc 1 165 9 view .LVU50
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 229              		.loc 1 167 9 view .LVU51
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 230              		.loc 1 167 16 is_stmt 0 view .LVU52
+ 231 007e 0120     		movs	r0, #1
+ 232              	.LVL16:
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 233              		.loc 1 167 16 view .LVU53
+ 234 0080 06E0     		b	.L5
+ 235              	.LVL17:
+ 236              	.L6:
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                       HAL_ADC_STATE_BUSY_INTERNAL,
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                       HAL_ADC_STATE_READY);
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 237              		.loc 1 178 5 is_stmt 1 view .LVU54
+ 238 0082 E36D     		ldr	r3, [r4, #92]
+ 239 0084 43F01003 		orr	r3, r3, #16
+ 240 0088 E365     		str	r3, [r4, #92]
+ 241              	.LVL18:
+ 242              	.L10:
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Note: No need to update variable "tmp_hal_status" here: already set    */
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /*       to state "HAL_ERROR" by function disabling the ADC.              */
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process unlocked */
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 243              		.loc 1 185 3 view .LVU55
+ 244              		.loc 1 185 3 view .LVU56
+ 245 008a 0023     		movs	r3, #0
+ 246 008c 84F85830 		strb	r3, [r4, #88]
+ 247              		.loc 1 185 3 view .LVU57
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return function status */
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 248              		.loc 1 188 3 view .LVU58
+ 249              	.LVL19:
+ 250              	.L5:
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 251              		.loc 1 189 1 is_stmt 0 view .LVU59
+ 252 0090 03B0     		add	sp, sp, #12
+ 253              	.LCFI4:
+ 254              		.cfi_remember_state
+ 255              		.cfi_def_cfa_offset 12
+ 256              		@ sp needed
+ 257 0092 30BD     		pop	{r4, r5, pc}
+ARM GAS  /tmp/cc3JIfda.s 			page 128
+
+
+ 258              	.LVL20:
+ 259              	.L11:
+ 260              	.LCFI5:
+ 261              		.cfi_restore_state
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 262              		.loc 1 135 3 view .LVU60
+ 263 0094 0220     		movs	r0, #2
+ 264              	.LVL21:
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 265              		.loc 1 135 3 view .LVU61
+ 266 0096 FBE7     		b	.L5
+ 267              	.L15:
+ 268              		.align	2
+ 269              	.L14:
+ 270 0098 01DE0400 		.word	318977
+ 271              		.cfi_endproc
+ 272              	.LFE329:
+ 274              		.section	.text.HAL_ADCEx_Calibration_GetValue,"ax",%progbits
+ 275              		.align	1
+ 276              		.global	HAL_ADCEx_Calibration_GetValue
+ 277              		.syntax unified
+ 278              		.thumb
+ 279              		.thumb_func
+ 281              	HAL_ADCEx_Calibration_GetValue:
+ 282              	.LVL22:
+ 283              	.LFB330:
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Get the calibration factor.
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle.
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param SingleDiff This parameter can be only:
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval Calibration value.
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 284              		.loc 1 200 1 is_stmt 1 view -0
+ 285              		.cfi_startproc
+ 286              		@ args = 0, pretend = 0, frame = 0
+ 287              		@ frame_needed = 0, uses_anonymous_args = 0
+ 288              		@ link register save eliminated.
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 289              		.loc 1 202 3 view .LVU63
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+ 290              		.loc 1 203 3 view .LVU64
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return the selected ADC calibration value */
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
+ 291              		.loc 1 206 3 view .LVU65
+ 292              		.loc 1 206 10 is_stmt 0 view .LVU66
+ 293 0000 0368     		ldr	r3, [r0]
+ 294              	.LVL23:
+ 295              	.LBB288:
+ 296              	.LBI288:
+2944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ARM GAS  /tmp/cc3JIfda.s 			page 129
+
+
+ 297              		.loc 2 2944 26 is_stmt 1 view .LVU67
+ 298              	.LBB289:
+2950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC
+ 299              		.loc 2 2950 3 view .LVU68
+2950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC
+ 300              		.loc 2 2950 21 is_stmt 0 view .LVU69
+ 301 0002 D3F8B400 		ldr	r0, [r3, #180]
+ 302              	.LVL24:
+2950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC
+ 303              		.loc 2 2950 21 view .LVU70
+ 304 0006 0840     		ands	r0, r0, r1
+ 305 0008 00F07F10 		and	r0, r0, #8323199
+2951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                                                   ADC_SINGLEDIFF_CA
+ 306              		.loc 2 2951 132 view .LVU71
+ 307 000c 090B     		lsrs	r1, r1, #12
+ 308              	.LVL25:
+2951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                                                   ADC_SINGLEDIFF_CA
+ 309              		.loc 2 2951 132 view .LVU72
+ 310 000e 01F01001 		and	r1, r1, #16
+ 311              	.LVL26:
+2951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                                                                                   ADC_SINGLEDIFF_CA
+ 312              		.loc 2 2951 132 view .LVU73
+ 313              	.LBE289:
+ 314              	.LBE288:
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 315              		.loc 1 207 1 view .LVU74
+ 316 0012 C840     		lsrs	r0, r0, r1
+ 317 0014 7047     		bx	lr
+ 318              		.cfi_endproc
+ 319              	.LFE330:
+ 321              		.section	.text.HAL_ADCEx_Calibration_SetValue,"ax",%progbits
+ 322              		.align	1
+ 323              		.global	HAL_ADCEx_Calibration_SetValue
+ 324              		.syntax unified
+ 325              		.thumb
+ 326              		.thumb_func
+ 328              	HAL_ADCEx_Calibration_SetValue:
+ 329              	.LVL27:
+ 330              	.LFB331:
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Set the calibration factor to overwrite automatic conversion result.
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         ADC must be enabled and no conversion is ongoing.
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param SingleDiff This parameter can be only:
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL state
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                  uint32_t CalibrationFactor)
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 331              		.loc 1 221 1 is_stmt 1 view -0
+ 332              		.cfi_startproc
+ 333              		@ args = 0, pretend = 0, frame = 0
+ 334              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cc3JIfda.s 			page 130
+
+
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 335              		.loc 1 222 3 view .LVU76
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+ 336              		.loc 1 223 3 view .LVU77
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_adc_is_conversion_on_going_injected;
+ 337              		.loc 1 224 3 view .LVU78
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 338              		.loc 1 227 3 view .LVU79
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+ 339              		.loc 1 228 3 view .LVU80
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_CALFACT(CalibrationFactor));
+ 340              		.loc 1 229 3 view .LVU81
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process locked */
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 341              		.loc 1 232 3 view .LVU82
+ 342              		.loc 1 232 3 view .LVU83
+ 343 0000 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 344 0004 012B     		cmp	r3, #1
+ 345 0006 26D0     		beq	.L23
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 346              		.loc 1 221 1 is_stmt 0 discriminator 2 view .LVU84
+ 347 0008 70B5     		push	{r4, r5, r6, lr}
+ 348              	.LCFI6:
+ 349              		.cfi_def_cfa_offset 16
+ 350              		.cfi_offset 4, -16
+ 351              		.cfi_offset 5, -12
+ 352              		.cfi_offset 6, -8
+ 353              		.cfi_offset 14, -4
+ 354 000a 0446     		mov	r4, r0
+ 355              		.loc 1 232 3 is_stmt 1 discriminator 2 view .LVU85
+ 356 000c 0123     		movs	r3, #1
+ 357 000e 80F85830 		strb	r3, [r0, #88]
+ 358              		.loc 1 232 3 discriminator 2 view .LVU86
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Verification of hardware constraints before modifying the calibration    */
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* factors register: ADC must be enabled, no conversion on going.           */
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ 359              		.loc 1 236 3 discriminator 2 view .LVU87
+ 360              		.loc 1 236 44 is_stmt 0 discriminator 2 view .LVU88
+ 361 0012 0068     		ldr	r0, [r0]
+ 362              	.LVL28:
+ 363              	.LBB290:
+ 364              	.LBI290:
+6787:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6788:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6789:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6790:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+6791:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6792:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6793:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regu
+6794:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+6795:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6797:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+ARM GAS  /tmp/cc3JIfda.s 			page 131
+
+
+6798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Start ADC group regular conversion.
+6799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, this function is relevant for both
+6800:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal trigger (SW start) and external trigger:
+6801:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - If ADC trigger has been set to software start, ADC conversion
+6802:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           starts immediately.
+6803:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - If ADC trigger has been set to external trigger, ADC conversion
+6804:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           will start at next trigger event (on the selected trigger edge)
+6805:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           following the ADC start conversion command.
+6806:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6807:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6808:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled without conversion on going on group regular,
+6809:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without conversion stop command on going on group regular,
+6810:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without ADC disable command on going.
+6811:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
+6812:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6813:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6814:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+6816:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6817:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6818:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6819:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6821:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+6822:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADSTART);
+6823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6824:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6825:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6826:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Stop ADC group regular conversion.
+6827:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6828:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6829:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled with conversion on going on group regular,
+6830:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without ADC disable command on going.
+6831:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
+6832:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6833:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6834:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6835:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
+6836:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6837:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+6838:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+6839:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+6840:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+6841:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+6842:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_ADSTP);
+6843:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6844:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6845:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6846:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion state.
+6847:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
+6848:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6849:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: no conversion is on going on ADC group regular.
+6850:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
+ 365              		.loc 2 6851 26 is_stmt 1 discriminator 2 view .LVU89
+ 366              	.LBB291:
+6852:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ARM GAS  /tmp/cc3JIfda.s 			page 132
+
+
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
+ 367              		.loc 2 6853 3 discriminator 2 view .LVU90
+ 368              		.loc 2 6853 12 is_stmt 0 discriminator 2 view .LVU91
+ 369 0014 8368     		ldr	r3, [r0, #8]
+ 370              		.loc 2 6853 74 discriminator 2 view .LVU92
+ 371 0016 13F00403 		ands	r3, r3, #4
+ 372 001a 00D0     		beq	.L19
+ 373              		.loc 2 6853 74 view .LVU93
+ 374 001c 0123     		movs	r3, #1
+ 375              	.L19:
+ 376              	.LVL29:
+ 377              		.loc 2 6853 74 view .LVU94
+ 378              	.LBE291:
+ 379              	.LBE290:
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 380              		.loc 1 237 3 is_stmt 1 view .LVU95
+ 381              	.LBB292:
+ 382              	.LBI292:
+6854:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6855:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6856:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6857:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular command of conversion stop state
+6858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
+6859:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: no command of conversion stop is on going on ADC group regular.
+6861:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6862:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+6863:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6864:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
+6865:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6866:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6867:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6868:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Start ADC sampling phase for sampling time trigger mode
+6869:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function is relevant only when
+6870:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+6871:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           using @ref LL_ADC_REG_SetSamplingMode
+6872:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+6873:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6874:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6875:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled without conversion on going on group regular,
+6876:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without conversion stop command on going on group regular,
+6877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without ADC disable command on going.
+6878:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    SWTRIG         LL_ADC_REG_StartSamplingPhase
+6879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6880:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6881:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6882:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
+6883:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6884:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+6885:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6886:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6887:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6888:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Stop ADC sampling phase for sampling time trigger mode and start conversion
+6889:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   This function is relevant only when
+6890:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+6891:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           using @ref LL_ADC_REG_SetSamplingMode
+6892:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+ARM GAS  /tmp/cc3JIfda.s 			page 133
+
+
+6893:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - @ref LL_ADC_REG_StartSamplingPhase has been called to start
+6894:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           the sampling phase
+6895:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+6896:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+6897:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled without conversion on going on group regular,
+6898:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without conversion stop command on going on group regular,
+6899:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without ADC disable command on going.
+6900:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CFGR2    SWTRIG         LL_ADC_REG_StopSamplingPhase
+6901:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6902:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+6903:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
+6905:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+6907:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6908:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6909:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6910:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion data, range fit for
+6911:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         all ADC configurations: all ADC resolutions and
+6912:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         all oversampling increased data width (for devices
+6913:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         with feature oversampling).
+6914:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
+6915:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6916:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+6917:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6918:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+6919:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6920:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+6921:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6922:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6923:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6924:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion data, range fit for
+6925:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC resolution 12 bits.
+6926:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with feature oversampling: Oversampling
+6927:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         can increase data width, function for extended range
+6928:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+6929:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
+6930:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6931:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+6932:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6933:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+6934:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6935:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+6936:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6937:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6938:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6939:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion data, range fit for
+6940:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC resolution 10 bits.
+6941:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with feature oversampling: Oversampling
+6942:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         can increase data width, function for extended range
+6943:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+6944:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
+6945:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6946:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+6947:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6948:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
+6949:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ARM GAS  /tmp/cc3JIfda.s 			page 134
+
+
+6950:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+6951:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6952:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6953:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6954:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion data, range fit for
+6955:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC resolution 8 bits.
+6956:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with feature oversampling: Oversampling
+6957:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         can increase data width, function for extended range
+6958:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+6959:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
+6960:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6961:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+6962:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6963:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
+6964:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6965:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+6966:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6967:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6968:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6969:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group regular conversion data, range fit for
+6970:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC resolution 6 bits.
+6971:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   For devices with feature oversampling: Oversampling
+6972:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         can increase data width, function for extended range
+6973:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+6974:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
+6975:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+6976:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+6977:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+6978:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
+6979:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+6980:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+6981:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+6982:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+6983:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
+6984:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+6985:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC multimode conversion data of ADC master, ADC slave
+6986:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         or raw data with ADC master and slave concatenated.
+6987:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   If raw data with ADC master and slave concatenated is retrieved,
+6988:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         a macro is available to get the conversion data of
+6989:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC master or ADC slave: see helper macro
+6990:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+6991:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (however this macro is mainly intended for multimode
+6992:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         transfer by DMA, because this function can do the same
+6993:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         by getting multimode conversion data of ADC master or ADC slave
+6994:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         separately).
+6995:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n
+6996:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32
+6997:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCxy_COMMON ADC common instance
+6998:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
+6999:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ConversionData This parameter can be one of the following values:
+7000:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_MASTER
+7001:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_SLAVE
+7002:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+7003:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+7004:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7005:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uin
+7006:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ARM GAS  /tmp/cc3JIfda.s 			page 135
+
+
+7007:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
+7008:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                              ConversionData)
+7009:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                     >> (POSITION_VAL(ConversionData) & 0x1FUL)
+7010:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****                    );
+7011:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7012:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
+7013:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7014:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7015:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @}
+7016:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7017:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7018:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group inj
+7019:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @{
+7020:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7021:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7022:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7023:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Start ADC group injected conversion.
+7024:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, this function is relevant for both
+7025:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         internal trigger (SW start) and external trigger:
+7026:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - If ADC trigger has been set to software start, ADC conversion
+7027:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           starts immediately.
+7028:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         - If ADC trigger has been set to external trigger, ADC conversion
+7029:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           will start at next trigger event (on the selected trigger edge)
+7030:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *           following the ADC start conversion command.
+7031:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+7032:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+7033:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled without conversion on going on group injected,
+7034:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without conversion stop command on going on group injected,
+7035:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without ADC disable command on going.
+7036:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion
+7037:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7038:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7039:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
+7041:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7042:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+7043:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+7044:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+7045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+7046:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+7047:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_JADSTART);
+7048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7049:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7050:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7051:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Stop ADC group injected conversion.
+7052:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @note   On this STM32 series, setting of this feature is conditioned to
+7053:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC state:
+7054:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         ADC must be enabled with conversion on going on group injected,
+7055:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   *         without ADC disable command on going.
+7056:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion
+7057:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7058:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval None
+7059:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7060:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
+7061:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7062:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /* Note: Write register with some additional bits forced to state reset     */
+7063:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       instead of modifying only the selected bit for this function,      */
+ARM GAS  /tmp/cc3JIfda.s 			page 136
+
+
+7064:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   /*       to not interfere with bits with HW property "rs".                  */
+7065:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   MODIFY_REG(ADCx->CR,
+7066:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+7067:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_JADSTP);
+7068:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+7069:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+7070:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** /**
+7071:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @brief  Get ADC group injected conversion state.
+7072:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
+7073:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @param  ADCx ADC instance
+7074:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   * @retval 0: no conversion is on going on ADC group injected.
+7075:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   */
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
+ 383              		.loc 2 7076 26 view .LVU96
+ 384              	.LBB293:
+7077:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+7078:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
+ 385              		.loc 2 7078 3 view .LVU97
+ 386              		.loc 2 7078 12 is_stmt 0 view .LVU98
+ 387 001e 8568     		ldr	r5, [r0, #8]
+ 388              		.loc 2 7078 76 view .LVU99
+ 389 0020 15F00805 		ands	r5, r5, #8
+ 390 0024 00D0     		beq	.L20
+ 391 0026 0125     		movs	r5, #1
+ 392              	.L20:
+ 393              	.LVL30:
+ 394              		.loc 2 7078 76 view .LVU100
+ 395              	.LBE293:
+ 396              	.LBE292:
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ 397              		.loc 1 239 3 is_stmt 1 view .LVU101
+ 398              	.LBB294:
+ 399              	.LBI294:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 400              		.loc 2 6729 26 view .LVU102
+ 401              	.LBB295:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 402              		.loc 2 6731 3 view .LVU103
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 403              		.loc 2 6731 12 is_stmt 0 view .LVU104
+ 404 0028 8668     		ldr	r6, [r0, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 405              		.loc 2 6731 68 view .LVU105
+ 406 002a 16F0010F 		tst	r6, #1
+ 407 002e 01D0     		beq	.L21
+ 408              	.LVL31:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 409              		.loc 2 6731 68 view .LVU106
+ 410              	.LBE295:
+ 411              	.LBE294:
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       && (tmp_adc_is_conversion_on_going_regular == 0UL)
+ 412              		.loc 1 240 7 view .LVU107
+ 413 0030 03B9     		cbnz	r3, .L21
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 414              		.loc 1 241 7 view .LVU108
+ 415 0032 65B1     		cbz	r5, .L28
+ARM GAS  /tmp/cc3JIfda.s 			page 137
+
+
+ 416              	.L21:
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****      )
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Set the selected ADC calibration value */
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Update ADC state machine */
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 417              		.loc 1 250 5 is_stmt 1 view .LVU109
+ 418 0034 E36D     		ldr	r3, [r4, #92]
+ 419              	.LVL32:
+ 420              		.loc 1 250 5 is_stmt 0 view .LVU110
+ 421 0036 43F02003 		orr	r3, r3, #32
+ 422 003a E365     		str	r3, [r4, #92]
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Update ADC error code */
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 423              		.loc 1 252 5 is_stmt 1 view .LVU111
+ 424 003c 236E     		ldr	r3, [r4, #96]
+ 425 003e 43F00103 		orr	r3, r3, #1
+ 426 0042 2366     		str	r3, [r4, #96]
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Update ADC state machine to error */
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_ERROR;
+ 427              		.loc 1 255 5 view .LVU112
+ 428              	.LVL33:
+ 429              		.loc 1 255 20 is_stmt 0 view .LVU113
+ 430 0044 0120     		movs	r0, #1
+ 431              	.LVL34:
+ 432              	.L22:
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process unlocked */
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 433              		.loc 1 259 3 is_stmt 1 view .LVU114
+ 434              		.loc 1 259 3 view .LVU115
+ 435 0046 0023     		movs	r3, #0
+ 436 0048 84F85830 		strb	r3, [r4, #88]
+ 437              		.loc 1 259 3 view .LVU116
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return function status */
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 438              		.loc 1 262 3 view .LVU117
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 439              		.loc 1 263 1 is_stmt 0 view .LVU118
+ 440 004c 70BD     		pop	{r4, r5, r6, pc}
+ 441              	.LVL35:
+ 442              	.L28:
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 443              		.loc 1 245 5 is_stmt 1 view .LVU119
+ 444 004e FFF7FEFF 		bl	LL_ADC_SetCalibrationFactor
+ 445              	.LVL36:
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+ 446              		.loc 1 222 21 is_stmt 0 view .LVU120
+ 447 0052 0020     		movs	r0, #0
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ARM GAS  /tmp/cc3JIfda.s 			page 138
+
+
+ 448              		.loc 1 245 5 view .LVU121
+ 449 0054 F7E7     		b	.L22
+ 450              	.LVL37:
+ 451              	.L23:
+ 452              	.LCFI7:
+ 453              		.cfi_def_cfa_offset 0
+ 454              		.cfi_restore 4
+ 455              		.cfi_restore 5
+ 456              		.cfi_restore 6
+ 457              		.cfi_restore 14
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 458              		.loc 1 232 3 view .LVU122
+ 459 0056 0220     		movs	r0, #2
+ 460              	.LVL38:
+ 461              		.loc 1 263 1 view .LVU123
+ 462 0058 7047     		bx	lr
+ 463              		.cfi_endproc
+ 464              	.LFE331:
+ 466              		.section	.text.HAL_ADCEx_InjectedStart,"ax",%progbits
+ 467              		.align	1
+ 468              		.global	HAL_ADCEx_InjectedStart
+ 469              		.syntax unified
+ 470              		.thumb
+ 471              		.thumb_func
+ 473              	HAL_ADCEx_InjectedStart:
+ 474              	.LVL39:
+ 475              	.LFB332:
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Enable ADC, start conversion of injected group.
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Interruptions enabled in this function: None.
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Case of multimode enabled when multimode feature is available:
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         then for ADC master.
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         For ADC slave, ADC is enabled only (conversion is not started).
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         For ADC master, ADC is enabled and multimode conversion is started.
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle.
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 476              		.loc 1 277 1 is_stmt 1 view -0
+ 477              		.cfi_startproc
+ 478              		@ args = 0, pretend = 0, frame = 0
+ 479              		@ frame_needed = 0, uses_anonymous_args = 0
+ 480              		.loc 1 277 1 is_stmt 0 view .LVU125
+ 481 0000 38B5     		push	{r3, r4, r5, lr}
+ 482              	.LCFI8:
+ 483              		.cfi_def_cfa_offset 16
+ 484              		.cfi_offset 3, -16
+ 485              		.cfi_offset 4, -12
+ 486              		.cfi_offset 5, -8
+ 487              		.cfi_offset 14, -4
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 488              		.loc 1 278 3 is_stmt 1 view .LVU126
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_config_injected_queue;
+ 489              		.loc 1 279 3 view .LVU127
+ARM GAS  /tmp/cc3JIfda.s 			page 139
+
+
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+ 490              		.loc 1 281 3 view .LVU128
+ 491              	.LVL40:
+ 492              	.LBB296:
+ 493              	.LBI296:
+6392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 494              		.loc 2 6392 26 view .LVU129
+ 495              	.LBB297:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 496              		.loc 2 6394 3 view .LVU130
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 497              		.loc 2 6394 21 is_stmt 0 view .LVU131
+ 498 0002 394B     		ldr	r3, .L50
+ 499 0004 9D68     		ldr	r5, [r3, #8]
+ 500              	.LVL41:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 501              		.loc 2 6394 21 view .LVU132
+ 502              	.LBE297:
+ 503              	.LBE296:
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #endif
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 504              		.loc 1 285 3 is_stmt 1 view .LVU133
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+ 505              		.loc 1 287 3 view .LVU134
+ 506              		.loc 1 287 7 is_stmt 0 view .LVU135
+ 507 0006 0368     		ldr	r3, [r0]
+ 508              	.LVL42:
+ 509              	.LBB298:
+ 510              	.LBI298:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 511              		.loc 2 7076 26 is_stmt 1 view .LVU136
+ 512              	.LBB299:
+ 513              		.loc 2 7078 3 view .LVU137
+ 514              		.loc 2 7078 12 is_stmt 0 view .LVU138
+ 515 0008 9A68     		ldr	r2, [r3, #8]
+ 516              		.loc 2 7078 76 view .LVU139
+ 517 000a 12F0080F 		tst	r2, #8
+ 518 000e 67D1     		bne	.L42
+ 519 0010 0446     		mov	r4, r0
+ 520 0012 05F01F05 		and	r5, r5, #31
+ 521              	.LVL43:
+ 522              		.loc 2 7078 76 view .LVU140
+ 523              	.LBE299:
+ 524              	.LBE298:
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     return HAL_BUSY;
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* In case of software trigger detection enabled, JQDIS must be set
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (which can be done only if ADSTART and JADSTART are both cleared).
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****        If JQDIS is not set at that point, returns an error
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****        - since software trigger detection is disabled. User needs to
+ARM GAS  /tmp/cc3JIfda.s 			page 140
+
+
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****          the queue is empty */
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+ 525              		.loc 1 300 5 is_stmt 1 view .LVU141
+ 526              		.loc 1 300 33 is_stmt 0 view .LVU142
+ 527 0016 DA68     		ldr	r2, [r3, #12]
+ 528              	.LVL44:
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
+ 529              		.loc 1 302 5 is_stmt 1 view .LVU143
+ 530              		.loc 1 302 10 is_stmt 0 view .LVU144
+ 531 0018 DB6C     		ldr	r3, [r3, #76]
+ 532              		.loc 1 302 8 view .LVU145
+ 533 001a 13F4C07F 		tst	r3, #384
+ 534 001e 01D1     		bne	.L31
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         && (tmp_config_injected_queue == 0UL)
+ 535              		.loc 1 303 9 view .LVU146
+ 536 0020 002A     		cmp	r2, #0
+ 537 0022 3DDA     		bge	.L47
+ 538              	.L31:
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****        )
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       return HAL_ERROR;
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Process locked */
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_LOCK(hadc);
+ 539              		.loc 1 311 5 is_stmt 1 view .LVU147
+ 540              		.loc 1 311 5 view .LVU148
+ 541 0024 94F85830 		ldrb	r3, [r4, #88]	@ zero_extendqisi2
+ 542 0028 012B     		cmp	r3, #1
+ 543 002a 5BD0     		beq	.L43
+ 544              		.loc 1 311 5 discriminator 2 view .LVU149
+ 545 002c 0123     		movs	r3, #1
+ 546 002e 84F85830 		strb	r3, [r4, #88]
+ 547              		.loc 1 311 5 discriminator 2 view .LVU150
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Enable the ADC peripheral */
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = ADC_Enable(hadc);
+ 548              		.loc 1 314 5 discriminator 2 view .LVU151
+ 549              		.loc 1 314 22 is_stmt 0 discriminator 2 view .LVU152
+ 550 0032 2046     		mov	r0, r4
+ 551              	.LVL45:
+ 552              		.loc 1 314 22 discriminator 2 view .LVU153
+ 553 0034 FFF7FEFF 		bl	ADC_Enable
+ 554              	.LVL46:
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Start conversion if ADC is effectively enabled */
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (tmp_hal_status == HAL_OK)
+ 555              		.loc 1 317 5 is_stmt 1 discriminator 2 view .LVU154
+ 556              		.loc 1 317 8 is_stmt 0 discriminator 2 view .LVU155
+ 557 0038 0028     		cmp	r0, #0
+ 558 003a 4DD1     		bne	.L32
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Check if a regular conversion is ongoing */
+ARM GAS  /tmp/cc3JIfda.s 			page 141
+
+
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
+ 559              		.loc 1 320 7 is_stmt 1 view .LVU156
+ 560              		.loc 1 320 16 is_stmt 0 view .LVU157
+ 561 003c E36D     		ldr	r3, [r4, #92]
+ 562              		.loc 1 320 10 view .LVU158
+ 563 003e 13F4807F 		tst	r3, #256
+ 564 0042 33D0     		beq	.L33
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Reset ADC error code field related to injected conversions only */
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+ 565              		.loc 1 323 9 is_stmt 1 view .LVU159
+ 566 0044 236E     		ldr	r3, [r4, #96]
+ 567 0046 23F00803 		bic	r3, r3, #8
+ 568 004a 2366     		str	r3, [r4, #96]
+ 569              	.L34:
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       else
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Set ADC error code to none */
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         ADC_CLEAR_ERRORCODE(hadc);
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set ADC state                                                        */
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* - Clear state bitfield related to injected group conversion results  */
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* - Set state bitfield related to injected operation                   */
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       ADC_STATE_CLR_SET(hadc->State,
+ 570              		.loc 1 334 7 view .LVU160
+ 571 004c E36D     		ldr	r3, [r4, #92]
+ 572 004e 23F44053 		bic	r3, r3, #12288
+ 573 0052 23F00103 		bic	r3, r3, #1
+ 574 0056 43F48053 		orr	r3, r3, #4096
+ 575 005a E365     		str	r3, [r4, #92]
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                         HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                         HAL_ADC_STATE_INJ_BUSY);
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         - if ADC instance is master or if multimode feature is not available
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         - if multimode setting is disabled (ADC instance slave in independent mode) */
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ 576              		.loc 1 342 7 view .LVU161
+ 577              		.loc 1 342 12 is_stmt 0 view .LVU162
+ 578 005c 2368     		ldr	r3, [r4]
+ 579 005e 234A     		ldr	r2, .L50+4
+ 580 0060 9342     		cmp	r3, r2
+ 581 0062 26D0     		beq	.L48
+ 582 0064 1A46     		mov	r2, r3
+ 583              	.L35:
+ 584              		.loc 1 342 10 discriminator 4 view .LVU163
+ 585 0066 9342     		cmp	r3, r2
+ 586 0068 00D0     		beq	.L36
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 587              		.loc 1 343 11 view .LVU164
+ 588 006a 1DB9     		cbnz	r5, .L37
+ 589              	.L36:
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****          )
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ARM GAS  /tmp/cc3JIfda.s 			page 142
+
+
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ 590              		.loc 1 346 9 is_stmt 1 view .LVU165
+ 591 006c E26D     		ldr	r2, [r4, #92]
+ 592 006e 22F48012 		bic	r2, r2, #1048576
+ 593 0072 E265     		str	r2, [r4, #92]
+ 594              	.L37:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #endif
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Clear ADC group injected group conversion flag */
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* (To ensure of no unknown state from potential previous ADC operations) */
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+ 595              		.loc 1 352 7 view .LVU166
+ 596 0074 6022     		movs	r2, #96
+ 597 0076 1A60     		str	r2, [r3]
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Process unlocked */
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Unlock before starting ADC conversions: in case of potential         */
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* interruption, to let the process to ADC IRQ Handler.                 */
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_UNLOCK(hadc);
+ 598              		.loc 1 357 7 view .LVU167
+ 599              		.loc 1 357 7 view .LVU168
+ 600 0078 0023     		movs	r3, #0
+ 601 007a 84F85830 		strb	r3, [r4, #88]
+ 602              		.loc 1 357 7 view .LVU169
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Enable conversion of injected group, if automatic injected conversion  */
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* is disabled.                                                           */
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* If software start has been selected, conversion starts immediately.    */
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* If external trigger has been selected, conversion will start at next   */
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* trigger event.                                                         */
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Case of multimode enabled (when multimode feature is available):       */
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* if ADC is slave,                                                       */
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*    - ADC is enabled only (conversion is not started),                  */
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*    - if multimode only concerns regular conversion, ADC is enabled     */
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*     and conversion is started.                                         */
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* If ADC is master or independent,                                       */
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*    - ADC is enabled and conversion is started.                         */
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ 603              		.loc 1 372 7 view .LVU170
+ 604              		.loc 1 372 12 is_stmt 0 view .LVU171
+ 605 007e 2368     		ldr	r3, [r4]
+ 606 0080 1A4A     		ldr	r2, .L50+4
+ 607 0082 9342     		cmp	r3, r2
+ 608 0084 18D0     		beq	.L49
+ 609 0086 1A46     		mov	r2, r3
+ 610              	.L38:
+ 611              		.loc 1 372 10 discriminator 4 view .LVU172
+ 612 0088 9342     		cmp	r3, r2
+ 613 008a 18D0     		beq	.L39
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 614              		.loc 1 373 11 view .LVU173
+ 615 008c BDB1     		cbz	r5, .L39
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ 616              		.loc 1 374 11 view .LVU174
+ 617 008e 062D     		cmp	r5, #6
+ARM GAS  /tmp/cc3JIfda.s 			page 143
+
+
+ 618 0090 15D0     		beq	.L39
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ 619              		.loc 1 375 11 view .LVU175
+ 620 0092 072D     		cmp	r5, #7
+ 621 0094 13D0     		beq	.L39
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****          )
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* ADC instance is not a multimode slave instance with multimode injected conversions enabl
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           LL_ADC_INJ_StartConversion(hadc->Instance);
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       else
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* ADC instance is not a multimode slave instance with multimode injected conversions enabl
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ 622              		.loc 1 387 9 is_stmt 1 view .LVU176
+ 623 0096 E36D     		ldr	r3, [r4, #92]
+ 624 0098 43F48013 		orr	r3, r3, #1048576
+ 625 009c E365     		str	r3, [r4, #92]
+ 626 009e 20E0     		b	.L30
+ 627              	.LVL47:
+ 628              	.L47:
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       return HAL_ERROR;
+ 629              		.loc 1 306 7 view .LVU177
+ 630 00a0 C36D     		ldr	r3, [r0, #92]
+ 631 00a2 43F02003 		orr	r3, r3, #32
+ 632 00a6 C365     		str	r3, [r0, #92]
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 633              		.loc 1 307 7 view .LVU178
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 634              		.loc 1 307 14 is_stmt 0 view .LVU179
+ 635 00a8 0120     		movs	r0, #1
+ 636              	.LVL48:
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 637              		.loc 1 307 14 view .LVU180
+ 638 00aa 1AE0     		b	.L30
+ 639              	.LVL49:
+ 640              	.L33:
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 641              		.loc 1 328 9 is_stmt 1 view .LVU181
+ 642 00ac 0023     		movs	r3, #0
+ 643 00ae 2366     		str	r3, [r4, #96]
+ 644 00b0 CCE7     		b	.L34
+ 645              	.L48:
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 646              		.loc 1 342 12 is_stmt 0 view .LVU182
+ 647 00b2 4FF0A042 		mov	r2, #1342177280
+ 648 00b6 D6E7     		b	.L35
+ 649              	.L49:
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 650              		.loc 1 372 12 view .LVU183
+ 651 00b8 4FF0A042 		mov	r2, #1342177280
+ 652 00bc E4E7     		b	.L38
+ 653              	.L39:
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+ARM GAS  /tmp/cc3JIfda.s 			page 144
+
+
+ 654              		.loc 1 379 9 is_stmt 1 view .LVU184
+ 655              	.LVL50:
+ 656              	.LBB300:
+ 657              	.LBI300:
+4858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 658              		.loc 2 4858 26 view .LVU185
+ 659              	.LBB301:
+4860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 660              		.loc 2 4860 3 view .LVU186
+4860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 661              		.loc 2 4860 21 is_stmt 0 view .LVU187
+ 662 00be DA68     		ldr	r2, [r3, #12]
+ 663              	.LVL51:
+4860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 664              		.loc 2 4860 21 view .LVU188
+ 665              	.LBE301:
+ 666              	.LBE300:
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+ 667              		.loc 1 379 12 view .LVU189
+ 668 00c0 12F0007F 		tst	r2, #33554432
+ 669 00c4 0DD1     		bne	.L30
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 670              		.loc 1 381 11 is_stmt 1 view .LVU190
+ 671              	.LVL52:
+ 672              	.LBB302:
+ 673              	.LBI302:
+7040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 674              		.loc 2 7040 22 view .LVU191
+ 675              	.LBB303:
+7045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 676              		.loc 2 7045 3 view .LVU192
+ 677 00c6 9A68     		ldr	r2, [r3, #8]
+ 678 00c8 22F00042 		bic	r2, r2, #-2147483648
+ 679 00cc 22F03F02 		bic	r2, r2, #63
+ 680 00d0 42F00802 		orr	r2, r2, #8
+ 681 00d4 9A60     		str	r2, [r3, #8]
+7048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 682              		.loc 2 7048 1 is_stmt 0 view .LVU193
+ 683 00d6 04E0     		b	.L30
+ 684              	.LVL53:
+ 685              	.L32:
+7048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 686              		.loc 2 7048 1 view .LVU194
+ 687              	.LBE303:
+ 688              	.LBE302:
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #else
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Start ADC group injected conversion */
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         LL_ADC_INJ_StartConversion(hadc->Instance);
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #endif
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ARM GAS  /tmp/cc3JIfda.s 			page 145
+
+
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Process unlocked */
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_UNLOCK(hadc);
+ 689              		.loc 1 401 7 is_stmt 1 view .LVU195
+ 690              		.loc 1 401 7 view .LVU196
+ 691 00d8 0023     		movs	r3, #0
+ 692 00da 84F85830 		strb	r3, [r4, #88]
+ 693              		.loc 1 401 7 view .LVU197
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Return function status */
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     return tmp_hal_status;
+ 694              		.loc 1 405 5 view .LVU198
+ 695              		.loc 1 405 12 is_stmt 0 view .LVU199
+ 696 00de 00E0     		b	.L30
+ 697              	.LVL54:
+ 698              	.L42:
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 699              		.loc 1 289 12 view .LVU200
+ 700 00e0 0220     		movs	r0, #2
+ 701              	.LVL55:
+ 702              	.L30:
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 703              		.loc 1 407 1 view .LVU201
+ 704 00e2 38BD     		pop	{r3, r4, r5, pc}
+ 705              	.LVL56:
+ 706              	.L43:
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 707              		.loc 1 311 5 view .LVU202
+ 708 00e4 0220     		movs	r0, #2
+ 709              	.LVL57:
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 710              		.loc 1 311 5 view .LVU203
+ 711 00e6 FCE7     		b	.L30
+ 712              	.L51:
+ 713              		.align	2
+ 714              	.L50:
+ 715 00e8 00030050 		.word	1342178048
+ 716 00ec 00010050 		.word	1342177536
+ 717              		.cfi_endproc
+ 718              	.LFE332:
+ 720              		.section	.text.HAL_ADCEx_InjectedStop,"ax",%progbits
+ 721              		.align	1
+ 722              		.global	HAL_ADCEx_InjectedStop
+ 723              		.syntax unified
+ 724              		.thumb
+ 725              		.thumb_func
+ 727              	HAL_ADCEx_InjectedStop:
+ 728              	.LVL58:
+ 729              	.LFB333:
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Stop conversion of injected channels. Disable ADC peripheral if
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         no regular conversion is on going.
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   If ADC must be disabled and if conversion is on going on
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         regular group, function HAL_ADC_Stop must be used to stop both
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         injected and regular groups, and disable the ADC.
+ARM GAS  /tmp/cc3JIfda.s 			page 146
+
+
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   If injected group mode auto-injection is enabled,
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         function HAL_ADC_Stop must be used.
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   In case of multimode enabled (when multimode feature is available),
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         For ADC master, conversion is stopped and ADC is disabled.
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         has already stopped conversion of ADC slave).
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle.
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 730              		.loc 1 426 1 is_stmt 1 view -0
+ 731              		.cfi_startproc
+ 732              		@ args = 0, pretend = 0, frame = 0
+ 733              		@ frame_needed = 0, uses_anonymous_args = 0
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 734              		.loc 1 427 3 view .LVU205
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 735              		.loc 1 430 3 view .LVU206
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process locked */
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 736              		.loc 1 433 3 view .LVU207
+ 737              		.loc 1 433 3 view .LVU208
+ 738 0000 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 739 0004 012B     		cmp	r3, #1
+ 740 0006 23D0     		beq	.L56
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 741              		.loc 1 426 1 is_stmt 0 discriminator 2 view .LVU209
+ 742 0008 10B5     		push	{r4, lr}
+ 743              	.LCFI9:
+ 744              		.cfi_def_cfa_offset 8
+ 745              		.cfi_offset 4, -8
+ 746              		.cfi_offset 14, -4
+ 747 000a 0446     		mov	r4, r0
+ 748              		.loc 1 433 3 is_stmt 1 discriminator 2 view .LVU210
+ 749 000c 0123     		movs	r3, #1
+ 750 000e 80F85830 		strb	r3, [r0, #88]
+ 751              		.loc 1 433 3 discriminator 2 view .LVU211
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* 1. Stop potential conversion on going on injected group only. */
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+ 752              		.loc 1 436 3 discriminator 2 view .LVU212
+ 753              		.loc 1 436 20 is_stmt 0 discriminator 2 view .LVU213
+ 754 0012 0221     		movs	r1, #2
+ 755 0014 FFF7FEFF 		bl	ADC_ConversionStop
+ 756              	.LVL59:
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Disable ADC peripheral if injected conversions are effectively stopped   */
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* and if no conversion on regular group is on-going                       */
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (tmp_hal_status == HAL_OK)
+ 757              		.loc 1 440 3 is_stmt 1 discriminator 2 view .LVU214
+ 758              		.loc 1 440 6 is_stmt 0 discriminator 2 view .LVU215
+ 759 0018 40B9     		cbnz	r0, .L54
+ARM GAS  /tmp/cc3JIfda.s 			page 147
+
+
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ 760              		.loc 1 442 5 is_stmt 1 view .LVU216
+ 761              		.loc 1 442 9 is_stmt 0 view .LVU217
+ 762 001a 2368     		ldr	r3, [r4]
+ 763              	.LVL60:
+ 764              	.LBB304:
+ 765              	.LBI304:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 766              		.loc 2 6851 26 is_stmt 1 view .LVU218
+ 767              	.LBB305:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 768              		.loc 2 6853 3 view .LVU219
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 769              		.loc 2 6853 12 is_stmt 0 view .LVU220
+ 770 001c 9B68     		ldr	r3, [r3, #8]
+ 771              	.LVL61:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 772              		.loc 2 6853 74 view .LVU221
+ 773 001e 13F0040F 		tst	r3, #4
+ 774 0022 07D0     		beq	.L55
+ 775              	.LVL62:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 776              		.loc 2 6853 74 view .LVU222
+ 777              	.LBE305:
+ 778              	.LBE304:
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* 2. Disable the ADC peripheral */
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmp_hal_status = ADC_Disable(hadc);
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Check if ADC is effectively disabled */
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (tmp_hal_status == HAL_OK)
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Set ADC state */
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         ADC_STATE_CLR_SET(hadc->State,
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_READY);
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Conversion on injected group is stopped, but ADC not disabled since    */
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* conversion on regular group is still running.                          */
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set ADC state */
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ 779              		.loc 1 461 7 is_stmt 1 view .LVU223
+ 780 0024 E36D     		ldr	r3, [r4, #92]
+ 781 0026 23F48053 		bic	r3, r3, #4096
+ 782 002a E365     		str	r3, [r4, #92]
+ 783              	.L54:
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process unlocked */
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 784              		.loc 1 466 3 view .LVU224
+ 785              		.loc 1 466 3 view .LVU225
+ARM GAS  /tmp/cc3JIfda.s 			page 148
+
+
+ 786 002c 0023     		movs	r3, #0
+ 787 002e 84F85830 		strb	r3, [r4, #88]
+ 788              		.loc 1 466 3 view .LVU226
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return function status */
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 789              		.loc 1 469 3 view .LVU227
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 790              		.loc 1 470 1 is_stmt 0 view .LVU228
+ 791 0032 10BD     		pop	{r4, pc}
+ 792              	.LVL63:
+ 793              	.L55:
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 794              		.loc 1 445 7 is_stmt 1 view .LVU229
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 795              		.loc 1 445 24 is_stmt 0 view .LVU230
+ 796 0034 2046     		mov	r0, r4
+ 797              	.LVL64:
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 798              		.loc 1 445 24 view .LVU231
+ 799 0036 FFF7FEFF 		bl	ADC_Disable
+ 800              	.LVL65:
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 801              		.loc 1 448 7 is_stmt 1 view .LVU232
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 802              		.loc 1 448 10 is_stmt 0 view .LVU233
+ 803 003a 0028     		cmp	r0, #0
+ 804 003c F6D1     		bne	.L54
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 805              		.loc 1 451 9 is_stmt 1 view .LVU234
+ 806 003e E36D     		ldr	r3, [r4, #92]
+ 807 0040 23F48853 		bic	r3, r3, #4352
+ 808 0044 23F00103 		bic	r3, r3, #1
+ 809 0048 43F00103 		orr	r3, r3, #1
+ 810 004c E365     		str	r3, [r4, #92]
+ 811 004e EDE7     		b	.L54
+ 812              	.LVL66:
+ 813              	.L56:
+ 814              	.LCFI10:
+ 815              		.cfi_def_cfa_offset 0
+ 816              		.cfi_restore 4
+ 817              		.cfi_restore 14
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 818              		.loc 1 433 3 is_stmt 0 view .LVU235
+ 819 0050 0220     		movs	r0, #2
+ 820              	.LVL67:
+ 821              		.loc 1 470 1 view .LVU236
+ 822 0052 7047     		bx	lr
+ 823              		.cfi_endproc
+ 824              	.LFE333:
+ 826              		.section	.text.HAL_ADCEx_InjectedPollForConversion,"ax",%progbits
+ 827              		.align	1
+ 828              		.global	HAL_ADCEx_InjectedPollForConversion
+ 829              		.syntax unified
+ 830              		.thumb
+ 831              		.thumb_func
+ 833              	HAL_ADCEx_InjectedPollForConversion:
+ARM GAS  /tmp/cc3JIfda.s 			page 149
+
+
+ 834              	.LVL68:
+ 835              	.LFB334:
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Wait for injected group conversion to be completed.
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param Timeout Timeout value in millisecond.
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Depending on hadc->Init.EOCSelection, JEOS or JEOC is
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         checked and cleared depending on AUTDLY bit status.
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 836              		.loc 1 481 1 is_stmt 1 view -0
+ 837              		.cfi_startproc
+ 838              		@ args = 0, pretend = 0, frame = 0
+ 839              		@ frame_needed = 0, uses_anonymous_args = 0
+ 840              		.loc 1 481 1 is_stmt 0 view .LVU238
+ 841 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 842              	.LCFI11:
+ 843              		.cfi_def_cfa_offset 24
+ 844              		.cfi_offset 4, -24
+ 845              		.cfi_offset 5, -20
+ 846              		.cfi_offset 6, -16
+ 847              		.cfi_offset 7, -12
+ 848              		.cfi_offset 8, -8
+ 849              		.cfi_offset 14, -4
+ 850 0004 0446     		mov	r4, r0
+ 851 0006 0D46     		mov	r5, r1
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tickstart;
+ 852              		.loc 1 482 3 is_stmt 1 view .LVU239
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_Flag_End;
+ 853              		.loc 1 483 3 view .LVU240
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+ 854              		.loc 1 484 3 view .LVU241
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+ 855              		.loc 1 485 3 view .LVU242
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_cfgr;
+ 856              		.loc 1 486 3 view .LVU243
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   const ADC_TypeDef *tmpADC_Master;
+ 857              		.loc 1 488 3 view .LVU244
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+ 858              		.loc 1 489 3 view .LVU245
+ 859              	.LVL69:
+ 860              	.LBB306:
+ 861              	.LBI306:
+6392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 862              		.loc 2 6392 26 view .LVU246
+ 863              	.LBB307:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 864              		.loc 2 6394 3 view .LVU247
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 865              		.loc 2 6394 21 is_stmt 0 view .LVU248
+ 866 0008 3B4B     		ldr	r3, .L87
+ 867 000a 9F68     		ldr	r7, [r3, #8]
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/cc3JIfda.s 			page 150
+
+
+ 868              		.loc 2 6394 10 view .LVU249
+ 869 000c 07F01F07 		and	r7, r7, #31
+ 870              	.LVL70:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 871              		.loc 2 6394 10 view .LVU250
+ 872              	.LBE307:
+ 873              	.LBE306:
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #endif
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 874              		.loc 1 493 3 is_stmt 1 view .LVU251
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* If end of sequence selected */
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ 875              		.loc 1 496 3 view .LVU252
+ 876              		.loc 1 496 17 is_stmt 0 view .LVU253
+ 877 0010 8369     		ldr	r3, [r0, #24]
+ 878              		.loc 1 496 6 view .LVU254
+ 879 0012 082B     		cmp	r3, #8
+ 880 0014 1FD0     		beq	.L83
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_Flag_End = ADC_FLAG_JEOS;
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else /* end of conversion selected */
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_Flag_End = ADC_FLAG_JEOC;
+ 881              		.loc 1 502 18 view .LVU255
+ 882 0016 2026     		movs	r6, #32
+ 883              	.L62:
+ 884              	.LVL71:
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Get timeout */
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tickstart = HAL_GetTick();
+ 885              		.loc 1 506 3 is_stmt 1 view .LVU256
+ 886              		.loc 1 506 15 is_stmt 0 view .LVU257
+ 887 0018 FFF7FEFF 		bl	HAL_GetTick
+ 888              	.LVL72:
+ 889              		.loc 1 506 15 view .LVU258
+ 890 001c 8046     		mov	r8, r0
+ 891              	.LVL73:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Wait until End of Conversion or Sequence flag is raised */
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ 892              		.loc 1 509 3 is_stmt 1 view .LVU259
+ 893              	.L64:
+ 894              		.loc 1 509 47 view .LVU260
+ 895              		.loc 1 509 15 is_stmt 0 view .LVU261
+ 896 001e 2368     		ldr	r3, [r4]
+ 897              		.loc 1 509 25 view .LVU262
+ 898 0020 1A68     		ldr	r2, [r3]
+ 899              		.loc 1 509 47 view .LVU263
+ 900 0022 3242     		tst	r2, r6
+ 901 0024 19D1     		bne	.L84
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Check if timeout is disabled (set to infinite wait) */
+ARM GAS  /tmp/cc3JIfda.s 			page 151
+
+
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (Timeout != HAL_MAX_DELAY)
+ 902              		.loc 1 512 5 is_stmt 1 view .LVU264
+ 903              		.loc 1 512 8 is_stmt 0 view .LVU265
+ 904 0026 B5F1FF3F 		cmp	r5, #-1
+ 905 002a F8D0     		beq	.L64
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ 906              		.loc 1 514 7 is_stmt 1 view .LVU266
+ 907              		.loc 1 514 13 is_stmt 0 view .LVU267
+ 908 002c FFF7FEFF 		bl	HAL_GetTick
+ 909              	.LVL74:
+ 910              		.loc 1 514 27 view .LVU268
+ 911 0030 A0EB0800 		sub	r0, r0, r8
+ 912              		.loc 1 514 10 view .LVU269
+ 913 0034 A842     		cmp	r0, r5
+ 914 0036 01D8     		bhi	.L65
+ 915              		.loc 1 514 51 discriminator 1 view .LVU270
+ 916 0038 002D     		cmp	r5, #0
+ 917 003a F0D1     		bne	.L64
+ 918              	.L65:
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* New check to avoid false timeout detection in case of preemption */
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ 919              		.loc 1 517 9 is_stmt 1 view .LVU271
+ 920              		.loc 1 517 18 is_stmt 0 view .LVU272
+ 921 003c 2368     		ldr	r3, [r4]
+ 922              		.loc 1 517 28 view .LVU273
+ 923 003e 1B68     		ldr	r3, [r3]
+ 924              		.loc 1 517 12 view .LVU274
+ 925 0040 3342     		tst	r3, r6
+ 926 0042 ECD1     		bne	.L64
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           /* Update ADC state machine to timeout */
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ 927              		.loc 1 520 11 is_stmt 1 view .LVU275
+ 928 0044 E36D     		ldr	r3, [r4, #92]
+ 929 0046 43F00403 		orr	r3, r3, #4
+ 930 004a E365     		str	r3, [r4, #92]
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           /* Process unlocked */
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           __HAL_UNLOCK(hadc);
+ 931              		.loc 1 523 11 view .LVU276
+ 932              		.loc 1 523 11 view .LVU277
+ 933 004c 0023     		movs	r3, #0
+ 934 004e 84F85830 		strb	r3, [r4, #88]
+ 935              		.loc 1 523 11 view .LVU278
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           return HAL_TIMEOUT;
+ 936              		.loc 1 525 11 view .LVU279
+ 937              		.loc 1 525 18 is_stmt 0 view .LVU280
+ 938 0052 0320     		movs	r0, #3
+ 939 0054 44E0     		b	.L66
+ 940              	.LVL75:
+ 941              	.L83:
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 942              		.loc 1 498 18 view .LVU281
+ 943 0056 4026     		movs	r6, #64
+ARM GAS  /tmp/cc3JIfda.s 			page 152
+
+
+ 944 0058 DEE7     		b	.L62
+ 945              	.LVL76:
+ 946              	.L84:
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Retrieve ADC configuration */
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+ 947              		.loc 1 532 3 is_stmt 1 view .LVU282
+ 948              	.LBB308:
+ 949              	.LBI308:
+4534:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 950              		.loc 2 4534 26 view .LVU283
+ 951              	.LBB309:
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 952              		.loc 2 4536 3 view .LVU284
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 953              		.loc 2 4536 12 is_stmt 0 view .LVU285
+ 954 005a DA6C     		ldr	r2, [r3, #76]
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 955              		.loc 2 4536 105 view .LVU286
+ 956 005c 12F4C07F 		tst	r2, #384
+ 957 0060 12D1     		bne	.L78
+ 958 0062 0120     		movs	r0, #1
+ 959              	.L68:
+ 960              	.LVL77:
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 961              		.loc 2 4536 105 view .LVU287
+ 962              	.LBE309:
+ 963              	.LBE308:
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+ 964              		.loc 1 533 3 is_stmt 1 view .LVU288
+ 965              	.LBB311:
+ 966              	.LBI311:
+3747:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 967              		.loc 2 3747 26 view .LVU289
+ 968              	.LBB312:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 969              		.loc 2 3749 3 view .LVU290
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 970              		.loc 2 3749 12 is_stmt 0 view .LVU291
+ 971 0064 DA68     		ldr	r2, [r3, #12]
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 972              		.loc 2 3749 103 view .LVU292
+ 973 0066 12F4406F 		tst	r2, #3072
+ 974 006a 0FD1     		bne	.L79
+ 975 006c 0125     		movs	r5, #1
+ 976              	.LVL78:
+ 977              	.L69:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 978              		.loc 2 3749 103 view .LVU293
+ 979              	.LBE312:
+ 980              	.LBE311:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Get relevant register CFGR in ADC instance of ADC master or slave  */
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* in function of multimode state (for devices with multimode         */
+ARM GAS  /tmp/cc3JIfda.s 			page 153
+
+
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* available).                                                        */
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ 981              		.loc 1 538 3 is_stmt 1 view .LVU294
+ 982              		.loc 1 538 8 is_stmt 0 view .LVU295
+ 983 006e 234A     		ldr	r2, .L87+4
+ 984 0070 9342     		cmp	r3, r2
+ 985 0072 0DD0     		beq	.L85
+ 986 0074 1A46     		mov	r2, r3
+ 987              	.L70:
+ 988              		.loc 1 538 6 discriminator 4 view .LVU296
+ 989 0076 9342     		cmp	r3, r2
+ 990 0078 0DD0     		beq	.L71
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 991              		.loc 1 539 7 view .LVU297
+ 992 007a 67B1     		cbz	r7, .L71
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ 993              		.loc 1 540 7 view .LVU298
+ 994 007c 062F     		cmp	r7, #6
+ 995 007e 0AD0     		beq	.L71
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ 996              		.loc 1 541 7 view .LVU299
+ 997 0080 072F     		cmp	r7, #7
+ 998 0082 08D0     		beq	.L71
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****      )
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ 999              		.loc 1 548 5 is_stmt 1 discriminator 4 view .LVU300
+ 1000              	.LVL79:
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+ 1001              		.loc 1 549 5 discriminator 4 view .LVU301
+ 1002              		.loc 1 549 14 is_stmt 0 discriminator 4 view .LVU302
+ 1003 0084 D168     		ldr	r1, [r2, #12]
+ 1004              	.LVL80:
+ 1005              		.loc 1 549 14 discriminator 4 view .LVU303
+ 1006 0086 07E0     		b	.L73
+ 1007              	.LVL81:
+ 1008              	.L78:
+ 1009              	.LBB314:
+ 1010              	.LBB310:
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1011              		.loc 2 4536 105 view .LVU304
+ 1012 0088 0020     		movs	r0, #0
+ 1013 008a EBE7     		b	.L68
+ 1014              	.LVL82:
+ 1015              	.L79:
+4536:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1016              		.loc 2 4536 105 view .LVU305
+ 1017              	.LBE310:
+ 1018              	.LBE314:
+ 1019              	.LBB315:
+ 1020              	.LBB313:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/cc3JIfda.s 			page 154
+
+
+ 1021              		.loc 2 3749 103 view .LVU306
+ 1022 008c 0025     		movs	r5, #0
+ 1023              	.LVL83:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1024              		.loc 2 3749 103 view .LVU307
+ 1025 008e EEE7     		b	.L69
+ 1026              	.LVL84:
+ 1027              	.L85:
+3749:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1028              		.loc 2 3749 103 view .LVU308
+ 1029              	.LBE313:
+ 1030              	.LBE315:
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1031              		.loc 1 538 8 view .LVU309
+ 1032 0090 4FF0A042 		mov	r2, #1342177280
+ 1033 0094 EFE7     		b	.L70
+ 1034              	.L71:
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 1035              		.loc 1 544 5 is_stmt 1 view .LVU310
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 1036              		.loc 1 544 14 is_stmt 0 view .LVU311
+ 1037 0096 D968     		ldr	r1, [r3, #12]
+ 1038              	.LVL85:
+ 1039              	.L73:
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #else
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #endif
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Update ADC state machine */
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+ 1040              		.loc 1 556 3 is_stmt 1 view .LVU312
+ 1041 0098 E26D     		ldr	r2, [r4, #92]
+ 1042 009a 42F40052 		orr	r2, r2, #8192
+ 1043 009e E265     		str	r2, [r4, #92]
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Determine whether any further conversion upcoming on group injected      */
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* by external trigger or by automatic injected conversion                  */
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* from group regular.                                                      */
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL)            ||
+ 1044              		.loc 1 561 3 view .LVU313
+ 1045              		.loc 1 561 6 is_stmt 0 view .LVU314
+ 1046 00a0 30B9     		cbnz	r0, .L74
+ 1047              		.loc 1 561 66 discriminator 1 view .LVU315
+ 1048 00a2 11F0007F 		tst	r1, #33554432
+ 1049 00a6 16D1     		bne	.L75
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL)      &&
+ 1050              		.loc 1 562 57 view .LVU316
+ 1051 00a8 ADB1     		cbz	r5, .L75
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****        ((tmp_adc_reg_is_trigger_source_sw_start != 0UL)  &&
+ 1052              		.loc 1 563 58 view .LVU317
+ 1053 00aa 11F4005F 		tst	r1, #8192
+ 1054 00ae 12D1     		bne	.L75
+ 1055              	.L74:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Check whether end of sequence is reached */
+ARM GAS  /tmp/cc3JIfda.s 			page 155
+
+
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ 1056              		.loc 1 567 5 is_stmt 1 view .LVU318
+ 1057              		.loc 1 567 9 is_stmt 0 view .LVU319
+ 1058 00b0 1A68     		ldr	r2, [r3]
+ 1059              		.loc 1 567 8 view .LVU320
+ 1060 00b2 12F0400F 		tst	r2, #64
+ 1061 00b6 0ED0     		beq	.L75
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Particular case if injected contexts queue is enabled:             */
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* when the last context has been fully processed, JSQR is reset      */
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* by the hardware. Even if no injected conversion is planned to come */
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* (queue empty, triggers are ignored), it can start again            */
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* immediately after setting a new context (JADSTART is still set).   */
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Therefore, state of HAL ADC injected group is kept to busy.        */
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+ 1062              		.loc 1 575 7 is_stmt 1 view .LVU321
+ 1063              		.loc 1 575 10 is_stmt 0 view .LVU322
+ 1064 00b8 11F4001F 		tst	r1, #2097152
+ 1065 00bc 0BD1     		bne	.L75
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Set ADC state */
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ 1066              		.loc 1 578 9 is_stmt 1 view .LVU323
+ 1067 00be E26D     		ldr	r2, [r4, #92]
+ 1068 00c0 22F48052 		bic	r2, r2, #4096
+ 1069 00c4 E265     		str	r2, [r4, #92]
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ 1070              		.loc 1 580 9 view .LVU324
+ 1071              		.loc 1 580 18 is_stmt 0 view .LVU325
+ 1072 00c6 E26D     		ldr	r2, [r4, #92]
+ 1073              		.loc 1 580 12 view .LVU326
+ 1074 00c8 12F4807F 		tst	r2, #256
+ 1075 00cc 03D1     		bne	.L75
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ 1076              		.loc 1 582 11 is_stmt 1 view .LVU327
+ 1077 00ce E26D     		ldr	r2, [r4, #92]
+ 1078 00d0 42F00102 		orr	r2, r2, #1
+ 1079 00d4 E265     		str	r2, [r4, #92]
+ 1080              	.L75:
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Clear polled flag */
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (tmp_Flag_End == ADC_FLAG_JEOS)
+ 1081              		.loc 1 589 3 view .LVU328
+ 1082              		.loc 1 589 6 is_stmt 0 view .LVU329
+ 1083 00d6 402E     		cmp	r6, #64
+ 1084 00d8 04D0     		beq	.L86
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Clear end of sequence JEOS flag of injected group if low power feature */
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* "LowPowerAutoWait " is disabled, to not interfere with this feature.   */
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* For injected groups, no new conversion will start before JEOS is       */
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* cleared.                                                               */
+ARM GAS  /tmp/cc3JIfda.s 			page 156
+
+
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+ 1085              		.loc 1 602 5 is_stmt 1 view .LVU330
+ 1086 00da 2022     		movs	r2, #32
+ 1087 00dc 1A60     		str	r2, [r3]
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return API HAL status */
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return HAL_OK;
+ 1088              		.loc 1 606 10 is_stmt 0 view .LVU331
+ 1089 00de 0020     		movs	r0, #0
+ 1090              	.LVL86:
+ 1091              	.L66:
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 1092              		.loc 1 607 1 view .LVU332
+ 1093 00e0 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 1094              	.LVL87:
+ 1095              	.L86:
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 1096              		.loc 1 595 5 is_stmt 1 view .LVU333
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 1097              		.loc 1 595 8 is_stmt 0 view .LVU334
+ 1098 00e4 11F4804F 		tst	r1, #16384
+ 1099 00e8 03D1     		bne	.L81
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 1100              		.loc 1 597 7 is_stmt 1 view .LVU335
+ 1101 00ea 6022     		movs	r2, #96
+ 1102 00ec 1A60     		str	r2, [r3]
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 1103              		.loc 1 606 10 is_stmt 0 view .LVU336
+ 1104 00ee 0020     		movs	r0, #0
+ 1105              	.LVL88:
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 1106              		.loc 1 606 10 view .LVU337
+ 1107 00f0 F6E7     		b	.L66
+ 1108              	.LVL89:
+ 1109              	.L81:
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 1110              		.loc 1 606 10 view .LVU338
+ 1111 00f2 0020     		movs	r0, #0
+ 1112              	.LVL90:
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 1113              		.loc 1 606 10 view .LVU339
+ 1114 00f4 F4E7     		b	.L66
+ 1115              	.L88:
+ 1116 00f6 00BF     		.align	2
+ 1117              	.L87:
+ 1118 00f8 00030050 		.word	1342178048
+ 1119 00fc 00010050 		.word	1342177536
+ 1120              		.cfi_endproc
+ 1121              	.LFE334:
+ARM GAS  /tmp/cc3JIfda.s 			page 157
+
+
+ 1123              		.section	.text.HAL_ADCEx_InjectedStart_IT,"ax",%progbits
+ 1124              		.align	1
+ 1125              		.global	HAL_ADCEx_InjectedStart_IT
+ 1126              		.syntax unified
+ 1127              		.thumb
+ 1128              		.thumb_func
+ 1130              	HAL_ADCEx_InjectedStart_IT:
+ 1131              	.LVL91:
+ 1132              	.LFB335:
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Enable ADC, start conversion of injected group with interruption.
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Interruptions enabled in this function according to initialization
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         setting : JEOC (end of conversion) or JEOS (end of sequence)
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Case of multimode enabled (when multimode feature is enabled):
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         then for ADC master.
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         For ADC slave, ADC is enabled only (conversion is not started).
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         For ADC master, ADC is enabled and multimode conversion is started.
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle.
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status.
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 1133              		.loc 1 622 1 is_stmt 1 view -0
+ 1134              		.cfi_startproc
+ 1135              		@ args = 0, pretend = 0, frame = 0
+ 1136              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1137              		.loc 1 622 1 is_stmt 0 view .LVU341
+ 1138 0000 38B5     		push	{r3, r4, r5, lr}
+ 1139              	.LCFI12:
+ 1140              		.cfi_def_cfa_offset 16
+ 1141              		.cfi_offset 3, -16
+ 1142              		.cfi_offset 4, -12
+ 1143              		.cfi_offset 5, -8
+ 1144              		.cfi_offset 14, -4
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 1145              		.loc 1 623 3 is_stmt 1 view .LVU342
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_config_injected_queue;
+ 1146              		.loc 1 624 3 view .LVU343
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+ 1147              		.loc 1 626 3 view .LVU344
+ 1148              	.LVL92:
+ 1149              	.LBB316:
+ 1150              	.LBI316:
+6392:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1151              		.loc 2 6392 26 view .LVU345
+ 1152              	.LBB317:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1153              		.loc 2 6394 3 view .LVU346
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1154              		.loc 2 6394 21 is_stmt 0 view .LVU347
+ 1155 0002 4A4B     		ldr	r3, .L114
+ 1156 0004 9D68     		ldr	r5, [r3, #8]
+ 1157              	.LVL93:
+6394:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/cc3JIfda.s 			page 158
+
+
+ 1158              		.loc 2 6394 21 view .LVU348
+ 1159              	.LBE317:
+ 1160              	.LBE316:
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #endif
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 1161              		.loc 1 630 3 is_stmt 1 view .LVU349
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+ 1162              		.loc 1 632 3 view .LVU350
+ 1163              		.loc 1 632 7 is_stmt 0 view .LVU351
+ 1164 0006 0368     		ldr	r3, [r0]
+ 1165              	.LVL94:
+ 1166              	.LBB318:
+ 1167              	.LBI318:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1168              		.loc 2 7076 26 is_stmt 1 view .LVU352
+ 1169              	.LBB319:
+ 1170              		.loc 2 7078 3 view .LVU353
+ 1171              		.loc 2 7078 12 is_stmt 0 view .LVU354
+ 1172 0008 9A68     		ldr	r2, [r3, #8]
+ 1173              		.loc 2 7078 76 view .LVU355
+ 1174 000a 12F0080F 		tst	r2, #8
+ 1175 000e 40F08980 		bne	.L105
+ 1176 0012 0446     		mov	r4, r0
+ 1177 0014 05F01F05 		and	r5, r5, #31
+ 1178              	.LVL95:
+ 1179              		.loc 2 7078 76 view .LVU356
+ 1180              	.LBE319:
+ 1181              	.LBE318:
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     return HAL_BUSY;
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* In case of software trigger detection enabled, JQDIS must be set
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (which can be done only if ADSTART and JADSTART are both cleared).
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****        If JQDIS is not set at that point, returns an error
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****        - since software trigger detection is disabled. User needs to
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****          the queue is empty */
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+ 1182              		.loc 1 645 5 is_stmt 1 view .LVU357
+ 1183              		.loc 1 645 33 is_stmt 0 view .LVU358
+ 1184 0018 DA68     		ldr	r2, [r3, #12]
+ 1185              	.LVL96:
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
+ 1186              		.loc 1 647 5 is_stmt 1 view .LVU359
+ 1187              		.loc 1 647 10 is_stmt 0 view .LVU360
+ 1188 001a DB6C     		ldr	r3, [r3, #76]
+ 1189              		.loc 1 647 8 view .LVU361
+ 1190 001c 13F4C07F 		tst	r3, #384
+ 1191 0020 01D1     		bne	.L91
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         && (tmp_config_injected_queue == 0UL)
+ARM GAS  /tmp/cc3JIfda.s 			page 159
+
+
+ 1192              		.loc 1 648 9 view .LVU362
+ 1193 0022 002A     		cmp	r2, #0
+ 1194 0024 53DA     		bge	.L110
+ 1195              	.L91:
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****        )
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       return HAL_ERROR;
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Process locked */
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_LOCK(hadc);
+ 1196              		.loc 1 656 5 is_stmt 1 view .LVU363
+ 1197              		.loc 1 656 5 view .LVU364
+ 1198 0026 94F85830 		ldrb	r3, [r4, #88]	@ zero_extendqisi2
+ 1199 002a 012B     		cmp	r3, #1
+ 1200 002c 7CD0     		beq	.L106
+ 1201              		.loc 1 656 5 discriminator 2 view .LVU365
+ 1202 002e 0123     		movs	r3, #1
+ 1203 0030 84F85830 		strb	r3, [r4, #88]
+ 1204              		.loc 1 656 5 discriminator 2 view .LVU366
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Enable the ADC peripheral */
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = ADC_Enable(hadc);
+ 1205              		.loc 1 659 5 discriminator 2 view .LVU367
+ 1206              		.loc 1 659 22 is_stmt 0 discriminator 2 view .LVU368
+ 1207 0034 2046     		mov	r0, r4
+ 1208              	.LVL97:
+ 1209              		.loc 1 659 22 discriminator 2 view .LVU369
+ 1210 0036 FFF7FEFF 		bl	ADC_Enable
+ 1211              	.LVL98:
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Start conversion if ADC is effectively enabled */
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (tmp_hal_status == HAL_OK)
+ 1212              		.loc 1 662 5 is_stmt 1 discriminator 2 view .LVU370
+ 1213              		.loc 1 662 8 is_stmt 0 discriminator 2 view .LVU371
+ 1214 003a 0028     		cmp	r0, #0
+ 1215 003c 6ED1     		bne	.L92
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Check if a regular conversion is ongoing */
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
+ 1216              		.loc 1 665 7 is_stmt 1 view .LVU372
+ 1217              		.loc 1 665 16 is_stmt 0 view .LVU373
+ 1218 003e E36D     		ldr	r3, [r4, #92]
+ 1219              		.loc 1 665 10 view .LVU374
+ 1220 0040 13F4807F 		tst	r3, #256
+ 1221 0044 49D0     		beq	.L93
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Reset ADC error code field related to injected conversions only */
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+ 1222              		.loc 1 668 9 is_stmt 1 view .LVU375
+ 1223 0046 236E     		ldr	r3, [r4, #96]
+ 1224 0048 23F00803 		bic	r3, r3, #8
+ 1225 004c 2366     		str	r3, [r4, #96]
+ 1226              	.L94:
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       else
+ARM GAS  /tmp/cc3JIfda.s 			page 160
+
+
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Set ADC error code to none */
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         ADC_CLEAR_ERRORCODE(hadc);
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set ADC state                                                        */
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* - Clear state bitfield related to injected group conversion results  */
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* - Set state bitfield related to injected operation                   */
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       ADC_STATE_CLR_SET(hadc->State,
+ 1227              		.loc 1 679 7 view .LVU376
+ 1228 004e E36D     		ldr	r3, [r4, #92]
+ 1229 0050 23F44053 		bic	r3, r3, #12288
+ 1230 0054 23F00103 		bic	r3, r3, #1
+ 1231 0058 43F48053 		orr	r3, r3, #4096
+ 1232 005c E365     		str	r3, [r4, #92]
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                         HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                         HAL_ADC_STATE_INJ_BUSY);
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         - if ADC instance is master or if multimode feature is not available
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         - if multimode setting is disabled (ADC instance slave in independent mode) */
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ 1233              		.loc 1 687 7 view .LVU377
+ 1234              		.loc 1 687 12 is_stmt 0 view .LVU378
+ 1235 005e 2368     		ldr	r3, [r4]
+ 1236 0060 334A     		ldr	r2, .L114+4
+ 1237 0062 9342     		cmp	r3, r2
+ 1238 0064 3CD0     		beq	.L111
+ 1239 0066 1A46     		mov	r2, r3
+ 1240              	.L95:
+ 1241              		.loc 1 687 10 discriminator 4 view .LVU379
+ 1242 0068 9342     		cmp	r3, r2
+ 1243 006a 00D0     		beq	.L96
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1244              		.loc 1 688 11 view .LVU380
+ 1245 006c 1DB9     		cbnz	r5, .L97
+ 1246              	.L96:
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****          )
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ 1247              		.loc 1 691 9 is_stmt 1 view .LVU381
+ 1248 006e E26D     		ldr	r2, [r4, #92]
+ 1249 0070 22F48012 		bic	r2, r2, #1048576
+ 1250 0074 E265     		str	r2, [r4, #92]
+ 1251              	.L97:
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #endif
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Clear ADC group injected group conversion flag */
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* (To ensure of no unknown state from potential previous ADC operations) */
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+ 1252              		.loc 1 697 7 view .LVU382
+ 1253 0076 6022     		movs	r2, #96
+ 1254 0078 1A60     		str	r2, [r3]
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Process unlocked */
+ARM GAS  /tmp/cc3JIfda.s 			page 161
+
+
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Unlock before starting ADC conversions: in case of potential         */
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* interruption, to let the process to ADC IRQ Handler.                 */
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_UNLOCK(hadc);
+ 1255              		.loc 1 702 7 view .LVU383
+ 1256              		.loc 1 702 7 view .LVU384
+ 1257 007a 0023     		movs	r3, #0
+ 1258 007c 84F85830 		strb	r3, [r4, #88]
+ 1259              		.loc 1 702 7 view .LVU385
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Enable ADC Injected context queue overflow interrupt if this feature   */
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* is enabled.                                                            */
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
+ 1260              		.loc 1 706 7 view .LVU386
+ 1261              		.loc 1 706 16 is_stmt 0 view .LVU387
+ 1262 0080 2368     		ldr	r3, [r4]
+ 1263              		.loc 1 706 26 view .LVU388
+ 1264 0082 DA68     		ldr	r2, [r3, #12]
+ 1265              		.loc 1 706 10 view .LVU389
+ 1266 0084 12F4001F 		tst	r2, #2097152
+ 1267 0088 03D0     		beq	.L98
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
+ 1268              		.loc 1 708 9 is_stmt 1 view .LVU390
+ 1269 008a 5A68     		ldr	r2, [r3, #4]
+ 1270 008c 42F48062 		orr	r2, r2, #1024
+ 1271 0090 5A60     		str	r2, [r3, #4]
+ 1272              	.L98:
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Enable ADC end of conversion interrupt */
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       switch (hadc->Init.EOCSelection)
+ 1273              		.loc 1 712 7 view .LVU391
+ 1274              		.loc 1 712 25 is_stmt 0 view .LVU392
+ 1275 0092 A369     		ldr	r3, [r4, #24]
+ 1276              		.loc 1 712 7 view .LVU393
+ 1277 0094 082B     		cmp	r3, #8
+ 1278 0096 26D0     		beq	.L112
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         case ADC_EOC_SEQ_CONV:
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           break;
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* case ADC_EOC_SINGLE_CONV */
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         default:
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ 1279              		.loc 1 720 11 is_stmt 1 view .LVU394
+ 1280 0098 2268     		ldr	r2, [r4]
+ 1281 009a 5368     		ldr	r3, [r2, #4]
+ 1282 009c 23F04003 		bic	r3, r3, #64
+ 1283 00a0 5360     		str	r3, [r2, #4]
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ 1284              		.loc 1 721 11 view .LVU395
+ 1285 00a2 2268     		ldr	r2, [r4]
+ 1286 00a4 5368     		ldr	r3, [r2, #4]
+ 1287 00a6 43F02003 		orr	r3, r3, #32
+ 1288 00aa 5360     		str	r3, [r2, #4]
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           break;
+ARM GAS  /tmp/cc3JIfda.s 			page 162
+
+
+ 1289              		.loc 1 722 11 view .LVU396
+ 1290              	.L100:
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Enable conversion of injected group, if automatic injected conversion  */
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* is disabled.                                                           */
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* If software start has been selected, conversion starts immediately.    */
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* If external trigger has been selected, conversion will start at next   */
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* trigger event.                                                         */
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Case of multimode enabled (when multimode feature is available):       */
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* if ADC is slave,                                                       */
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*    - ADC is enabled only (conversion is not started),                  */
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*    - if multimode only concerns regular conversion, ADC is enabled     */
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*     and conversion is started.                                         */
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* If ADC is master or independent,                                       */
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*    - ADC is enabled and conversion is started.                         */
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ 1291              		.loc 1 738 7 view .LVU397
+ 1292              		.loc 1 738 12 is_stmt 0 view .LVU398
+ 1293 00ac 2368     		ldr	r3, [r4]
+ 1294 00ae 204A     		ldr	r2, .L114+4
+ 1295 00b0 9342     		cmp	r3, r2
+ 1296 00b2 23D0     		beq	.L113
+ 1297 00b4 1A46     		mov	r2, r3
+ 1298              	.L101:
+ 1299              		.loc 1 738 10 discriminator 4 view .LVU399
+ 1300 00b6 9342     		cmp	r3, r2
+ 1301 00b8 23D0     		beq	.L102
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1302              		.loc 1 739 11 view .LVU400
+ 1303 00ba 15B3     		cbz	r5, .L102
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ 1304              		.loc 1 740 11 view .LVU401
+ 1305 00bc 062D     		cmp	r5, #6
+ 1306 00be 20D0     		beq	.L102
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ 1307              		.loc 1 741 11 view .LVU402
+ 1308 00c0 072D     		cmp	r5, #7
+ 1309 00c2 1ED0     		beq	.L102
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****          )
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* ADC instance is not a multimode slave instance with multimode injected conversions enabl
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           LL_ADC_INJ_StartConversion(hadc->Instance);
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       else
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* ADC instance is not a multimode slave instance with multimode injected conversions enabl
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ 1310              		.loc 1 753 9 is_stmt 1 view .LVU403
+ 1311 00c4 E36D     		ldr	r3, [r4, #92]
+ 1312 00c6 43F48013 		orr	r3, r3, #1048576
+ 1313 00ca E365     		str	r3, [r4, #92]
+ 1314 00cc 2BE0     		b	.L90
+ARM GAS  /tmp/cc3JIfda.s 			page 163
+
+
+ 1315              	.LVL99:
+ 1316              	.L110:
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       return HAL_ERROR;
+ 1317              		.loc 1 651 7 view .LVU404
+ 1318 00ce C36D     		ldr	r3, [r0, #92]
+ 1319 00d0 43F02003 		orr	r3, r3, #32
+ 1320 00d4 C365     		str	r3, [r0, #92]
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 1321              		.loc 1 652 7 view .LVU405
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 1322              		.loc 1 652 14 is_stmt 0 view .LVU406
+ 1323 00d6 0120     		movs	r0, #1
+ 1324              	.LVL100:
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 1325              		.loc 1 652 14 view .LVU407
+ 1326 00d8 25E0     		b	.L90
+ 1327              	.LVL101:
+ 1328              	.L93:
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 1329              		.loc 1 673 9 is_stmt 1 view .LVU408
+ 1330 00da 0023     		movs	r3, #0
+ 1331 00dc 2366     		str	r3, [r4, #96]
+ 1332 00de B6E7     		b	.L94
+ 1333              	.L111:
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1334              		.loc 1 687 12 is_stmt 0 view .LVU409
+ 1335 00e0 4FF0A042 		mov	r2, #1342177280
+ 1336 00e4 C0E7     		b	.L95
+ 1337              	.L112:
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ 1338              		.loc 1 715 11 is_stmt 1 view .LVU410
+ 1339 00e6 2268     		ldr	r2, [r4]
+ 1340 00e8 5368     		ldr	r3, [r2, #4]
+ 1341 00ea 23F02003 		bic	r3, r3, #32
+ 1342 00ee 5360     		str	r3, [r2, #4]
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           break;
+ 1343              		.loc 1 716 11 view .LVU411
+ 1344 00f0 2268     		ldr	r2, [r4]
+ 1345 00f2 5368     		ldr	r3, [r2, #4]
+ 1346 00f4 43F04003 		orr	r3, r3, #64
+ 1347 00f8 5360     		str	r3, [r2, #4]
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* case ADC_EOC_SINGLE_CONV */
+ 1348              		.loc 1 717 11 view .LVU412
+ 1349 00fa D7E7     		b	.L100
+ 1350              	.L113:
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ 1351              		.loc 1 738 12 is_stmt 0 view .LVU413
+ 1352 00fc 4FF0A042 		mov	r2, #1342177280
+ 1353 0100 D9E7     		b	.L101
+ 1354              	.L102:
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+ 1355              		.loc 1 745 9 is_stmt 1 view .LVU414
+ 1356              	.LVL102:
+ 1357              	.LBB320:
+ 1358              	.LBI320:
+4858:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1359              		.loc 2 4858 26 view .LVU415
+ARM GAS  /tmp/cc3JIfda.s 			page 164
+
+
+ 1360              	.LBB321:
+4860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1361              		.loc 2 4860 3 view .LVU416
+4860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1362              		.loc 2 4860 21 is_stmt 0 view .LVU417
+ 1363 0102 DA68     		ldr	r2, [r3, #12]
+ 1364              	.LVL103:
+4860:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1365              		.loc 2 4860 21 view .LVU418
+ 1366              	.LBE321:
+ 1367              	.LBE320:
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+ 1368              		.loc 1 745 12 view .LVU419
+ 1369 0104 12F0007F 		tst	r2, #33554432
+ 1370 0108 0DD1     		bne	.L90
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 1371              		.loc 1 747 11 is_stmt 1 view .LVU420
+ 1372              	.LVL104:
+ 1373              	.LBB322:
+ 1374              	.LBI322:
+7040:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1375              		.loc 2 7040 22 view .LVU421
+ 1376              	.LBB323:
+7045:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 1377              		.loc 2 7045 3 view .LVU422
+ 1378 010a 9A68     		ldr	r2, [r3, #8]
+ 1379 010c 22F00042 		bic	r2, r2, #-2147483648
+ 1380 0110 22F03F02 		bic	r2, r2, #63
+ 1381 0114 42F00802 		orr	r2, r2, #8
+ 1382 0118 9A60     		str	r2, [r3, #8]
+7048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 1383              		.loc 2 7048 1 is_stmt 0 view .LVU423
+ 1384 011a 04E0     		b	.L90
+ 1385              	.LVL105:
+ 1386              	.L92:
+7048:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 1387              		.loc 2 7048 1 view .LVU424
+ 1388              	.LBE323:
+ 1389              	.LBE322:
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #else
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Start ADC group injected conversion */
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         LL_ADC_INJ_StartConversion(hadc->Instance);
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #endif
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Process unlocked */
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_UNLOCK(hadc);
+ 1390              		.loc 1 767 7 is_stmt 1 view .LVU425
+ 1391              		.loc 1 767 7 view .LVU426
+ 1392 011c 0023     		movs	r3, #0
+ 1393 011e 84F85830 		strb	r3, [r4, #88]
+ARM GAS  /tmp/cc3JIfda.s 			page 165
+
+
+ 1394              		.loc 1 767 7 view .LVU427
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Return function status */
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     return tmp_hal_status;
+ 1395              		.loc 1 771 5 view .LVU428
+ 1396              		.loc 1 771 12 is_stmt 0 view .LVU429
+ 1397 0122 00E0     		b	.L90
+ 1398              	.LVL106:
+ 1399              	.L105:
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 1400              		.loc 1 634 12 view .LVU430
+ 1401 0124 0220     		movs	r0, #2
+ 1402              	.LVL107:
+ 1403              	.L90:
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 1404              		.loc 1 773 1 view .LVU431
+ 1405 0126 38BD     		pop	{r3, r4, r5, pc}
+ 1406              	.LVL108:
+ 1407              	.L106:
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1408              		.loc 1 656 5 view .LVU432
+ 1409 0128 0220     		movs	r0, #2
+ 1410              	.LVL109:
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1411              		.loc 1 656 5 view .LVU433
+ 1412 012a FCE7     		b	.L90
+ 1413              	.L115:
+ 1414              		.align	2
+ 1415              	.L114:
+ 1416 012c 00030050 		.word	1342178048
+ 1417 0130 00010050 		.word	1342177536
+ 1418              		.cfi_endproc
+ 1419              	.LFE335:
+ 1421              		.section	.text.HAL_ADCEx_InjectedStop_IT,"ax",%progbits
+ 1422              		.align	1
+ 1423              		.global	HAL_ADCEx_InjectedStop_IT
+ 1424              		.syntax unified
+ 1425              		.thumb
+ 1426              		.thumb_func
+ 1428              	HAL_ADCEx_InjectedStop_IT:
+ 1429              	.LVL110:
+ 1430              	.LFB336:
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Stop conversion of injected channels, disable interruption of
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         end-of-conversion. Disable ADC peripheral if no regular conversion
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         is on going.
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   If ADC must be disabled and if conversion is on going on
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         regular group, function HAL_ADC_Stop must be used to stop both
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         injected and regular groups, and disable the ADC.
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   If injected group mode auto-injection is enabled,
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         function HAL_ADC_Stop must be used.
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Case of multimode enabled (when multimode feature is available):
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         then for ADC slave.
+ARM GAS  /tmp/cc3JIfda.s 			page 166
+
+
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         For ADC master, conversion is stopped and ADC is disabled.
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         has already stopped conversion of ADC slave).
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 1431              		.loc 1 795 1 is_stmt 1 view -0
+ 1432              		.cfi_startproc
+ 1433              		@ args = 0, pretend = 0, frame = 0
+ 1434              		@ frame_needed = 0, uses_anonymous_args = 0
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 1435              		.loc 1 796 3 view .LVU435
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 1436              		.loc 1 799 3 view .LVU436
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process locked */
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 1437              		.loc 1 802 3 view .LVU437
+ 1438              		.loc 1 802 3 view .LVU438
+ 1439 0000 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 1440 0004 012B     		cmp	r3, #1
+ 1441 0006 28D0     		beq	.L120
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 1442              		.loc 1 795 1 is_stmt 0 discriminator 2 view .LVU439
+ 1443 0008 10B5     		push	{r4, lr}
+ 1444              	.LCFI13:
+ 1445              		.cfi_def_cfa_offset 8
+ 1446              		.cfi_offset 4, -8
+ 1447              		.cfi_offset 14, -4
+ 1448 000a 0446     		mov	r4, r0
+ 1449              		.loc 1 802 3 is_stmt 1 discriminator 2 view .LVU440
+ 1450 000c 0123     		movs	r3, #1
+ 1451 000e 80F85830 		strb	r3, [r0, #88]
+ 1452              		.loc 1 802 3 discriminator 2 view .LVU441
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* 1. Stop potential conversion on going on injected group only. */
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+ 1453              		.loc 1 805 3 discriminator 2 view .LVU442
+ 1454              		.loc 1 805 20 is_stmt 0 discriminator 2 view .LVU443
+ 1455 0012 0221     		movs	r1, #2
+ 1456 0014 FFF7FEFF 		bl	ADC_ConversionStop
+ 1457              	.LVL111:
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Disable ADC peripheral if injected conversions are effectively stopped   */
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* and if no conversion on the other group (regular group) is intended to   */
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* continue.                                                                */
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (tmp_hal_status == HAL_OK)
+ 1458              		.loc 1 810 3 is_stmt 1 discriminator 2 view .LVU444
+ 1459              		.loc 1 810 6 is_stmt 0 discriminator 2 view .LVU445
+ 1460 0018 68B9     		cbnz	r0, .L118
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Disable ADC end of conversion interrupt for injected channels */
+ARM GAS  /tmp/cc3JIfda.s 			page 167
+
+
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
+ 1461              		.loc 1 813 5 is_stmt 1 view .LVU446
+ 1462 001a 2268     		ldr	r2, [r4]
+ 1463 001c 5368     		ldr	r3, [r2, #4]
+ 1464 001e 23F48C63 		bic	r3, r3, #1120
+ 1465 0022 5360     		str	r3, [r2, #4]
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ 1466              		.loc 1 815 5 view .LVU447
+ 1467              		.loc 1 815 9 is_stmt 0 view .LVU448
+ 1468 0024 2368     		ldr	r3, [r4]
+ 1469              	.LVL112:
+ 1470              	.LBB324:
+ 1471              	.LBI324:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1472              		.loc 2 6851 26 is_stmt 1 view .LVU449
+ 1473              	.LBB325:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1474              		.loc 2 6853 3 view .LVU450
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1475              		.loc 2 6853 12 is_stmt 0 view .LVU451
+ 1476 0026 9B68     		ldr	r3, [r3, #8]
+ 1477              	.LVL113:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1478              		.loc 2 6853 74 view .LVU452
+ 1479 0028 13F0040F 		tst	r3, #4
+ 1480 002c 07D0     		beq	.L119
+ 1481              	.LVL114:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1482              		.loc 2 6853 74 view .LVU453
+ 1483              	.LBE325:
+ 1484              	.LBE324:
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* 2. Disable the ADC peripheral */
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmp_hal_status = ADC_Disable(hadc);
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Check if ADC is effectively disabled */
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (tmp_hal_status == HAL_OK)
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Set ADC state */
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         ADC_STATE_CLR_SET(hadc->State,
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_READY);
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Conversion on injected group is stopped, but ADC not disabled since    */
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* conversion on regular group is still running.                          */
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set ADC state */
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ 1485              		.loc 1 834 7 is_stmt 1 view .LVU454
+ 1486 002e E36D     		ldr	r3, [r4, #92]
+ 1487 0030 23F48053 		bic	r3, r3, #4096
+ 1488 0034 E365     		str	r3, [r4, #92]
+ 1489              	.L118:
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ARM GAS  /tmp/cc3JIfda.s 			page 168
+
+
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process unlocked */
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 1490              		.loc 1 839 3 view .LVU455
+ 1491              		.loc 1 839 3 view .LVU456
+ 1492 0036 0023     		movs	r3, #0
+ 1493 0038 84F85830 		strb	r3, [r4, #88]
+ 1494              		.loc 1 839 3 view .LVU457
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return function status */
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 1495              		.loc 1 842 3 view .LVU458
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 1496              		.loc 1 843 1 is_stmt 0 view .LVU459
+ 1497 003c 10BD     		pop	{r4, pc}
+ 1498              	.LVL115:
+ 1499              	.L119:
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1500              		.loc 1 818 7 is_stmt 1 view .LVU460
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1501              		.loc 1 818 24 is_stmt 0 view .LVU461
+ 1502 003e 2046     		mov	r0, r4
+ 1503              	.LVL116:
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1504              		.loc 1 818 24 view .LVU462
+ 1505 0040 FFF7FEFF 		bl	ADC_Disable
+ 1506              	.LVL117:
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 1507              		.loc 1 821 7 is_stmt 1 view .LVU463
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 1508              		.loc 1 821 10 is_stmt 0 view .LVU464
+ 1509 0044 0028     		cmp	r0, #0
+ 1510 0046 F6D1     		bne	.L118
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 1511              		.loc 1 824 9 is_stmt 1 view .LVU465
+ 1512 0048 E36D     		ldr	r3, [r4, #92]
+ 1513 004a 23F48853 		bic	r3, r3, #4352
+ 1514 004e 23F00103 		bic	r3, r3, #1
+ 1515 0052 43F00103 		orr	r3, r3, #1
+ 1516 0056 E365     		str	r3, [r4, #92]
+ 1517 0058 EDE7     		b	.L118
+ 1518              	.LVL118:
+ 1519              	.L120:
+ 1520              	.LCFI14:
+ 1521              		.cfi_def_cfa_offset 0
+ 1522              		.cfi_restore 4
+ 1523              		.cfi_restore 14
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1524              		.loc 1 802 3 is_stmt 0 view .LVU466
+ 1525 005a 0220     		movs	r0, #2
+ 1526              	.LVL119:
+ 1527              		.loc 1 843 1 view .LVU467
+ 1528 005c 7047     		bx	lr
+ 1529              		.cfi_endproc
+ 1530              	.LFE336:
+ 1532              		.section	.text.HAL_ADCEx_MultiModeStart_DMA,"ax",%progbits
+ARM GAS  /tmp/cc3JIfda.s 			page 169
+
+
+ 1533              		.align	1
+ 1534              		.global	HAL_ADCEx_MultiModeStart_DMA
+ 1535              		.syntax unified
+ 1536              		.thumb
+ 1537              		.thumb_func
+ 1539              	HAL_ADCEx_MultiModeStart_DMA:
+ 1540              	.LVL120:
+ 1541              	.LFB337:
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Enable ADC, start MultiMode conversion and transfer regular results through DMA.
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Multimode must have been previously configured using
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         HAL_ADCEx_MultiModeConfigChannel() function.
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         Interruptions enabled in this function:
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *          overrun, DMA half transfer, DMA transfer complete.
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         Each of these interruptions has its dedicated callback function.
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   State field of Slave ADC handle is not updated in this configuration:
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *          user should not rely on it for information related to Slave regular
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         conversions.
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param pData Destination Buffer address.
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t L
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 1542              		.loc 1 862 1 is_stmt 1 view -0
+ 1543              		.cfi_startproc
+ 1544              		@ args = 0, pretend = 0, frame = 112
+ 1545              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1546              		.loc 1 862 1 is_stmt 0 view .LVU469
+ 1547 0000 70B5     		push	{r4, r5, r6, lr}
+ 1548              	.LCFI15:
+ 1549              		.cfi_def_cfa_offset 16
+ 1550              		.cfi_offset 4, -16
+ 1551              		.cfi_offset 5, -12
+ 1552              		.cfi_offset 6, -8
+ 1553              		.cfi_offset 14, -4
+ 1554 0002 9CB0     		sub	sp, sp, #112
+ 1555              	.LCFI16:
+ 1556              		.cfi_def_cfa_offset 128
+ 1557 0004 0446     		mov	r4, r0
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 1558              		.loc 1 863 3 is_stmt 1 view .LVU470
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ADC_HandleTypeDef tmphadcSlave;
+ 1559              		.loc 1 864 3 view .LVU471
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ADC_Common_TypeDef *tmpADC_Common;
+ 1560              		.loc 1 865 3 view .LVU472
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ 1561              		.loc 1 868 3 view .LVU473
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ 1562              		.loc 1 869 3 view .LVU474
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ 1563              		.loc 1 870 3 view .LVU475
+ARM GAS  /tmp/cc3JIfda.s 			page 170
+
+
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ 1564              		.loc 1 871 3 view .LVU476
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ 1565              		.loc 1 873 3 view .LVU477
+ 1566              		.loc 1 873 7 is_stmt 0 view .LVU478
+ 1567 0006 0068     		ldr	r0, [r0]
+ 1568              	.LVL121:
+ 1569              	.LBB326:
+ 1570              	.LBI326:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1571              		.loc 2 6851 26 is_stmt 1 view .LVU479
+ 1572              	.LBB327:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1573              		.loc 2 6853 3 view .LVU480
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1574              		.loc 2 6853 12 is_stmt 0 view .LVU481
+ 1575 0008 8068     		ldr	r0, [r0, #8]
+ 1576              	.LVL122:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1577              		.loc 2 6853 74 view .LVU482
+ 1578 000a 10F0040F 		tst	r0, #4
+ 1579 000e 5AD1     		bne	.L132
+ 1580 0010 0E46     		mov	r6, r1
+ 1581 0012 1546     		mov	r5, r2
+ 1582              	.LVL123:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1583              		.loc 2 6853 74 view .LVU483
+ 1584              	.LBE327:
+ 1585              	.LBE326:
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     return HAL_BUSY;
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Process locked */
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_LOCK(hadc);
+ 1586              		.loc 1 880 5 is_stmt 1 view .LVU484
+ 1587              		.loc 1 880 5 view .LVU485
+ 1588 0014 94F85830 		ldrb	r3, [r4, #88]	@ zero_extendqisi2
+ 1589 0018 012B     		cmp	r3, #1
+ 1590 001a 57D0     		beq	.L133
+ 1591              		.loc 1 880 5 discriminator 2 view .LVU486
+ 1592 001c 0123     		movs	r3, #1
+ 1593 001e 84F85830 		strb	r3, [r4, #88]
+ 1594              		.loc 1 880 5 discriminator 2 view .LVU487
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Temporary handle minimum initialization */
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ 1595              		.loc 1 883 5 discriminator 2 view .LVU488
+ 1596 0022 0023     		movs	r3, #0
+ 1597 0024 1893     		str	r3, [sp, #96]
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+ 1598              		.loc 1 884 5 discriminator 2 view .LVU489
+ 1599 0026 1993     		str	r3, [sp, #100]
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Set a temporary handle of the ADC slave associated to the ADC master   */
+ARM GAS  /tmp/cc3JIfda.s 			page 171
+
+
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+ 1600              		.loc 1 887 5 discriminator 2 view .LVU490
+ 1601 0028 2368     		ldr	r3, [r4]
+ 1602 002a B3F1A04F 		cmp	r3, #1342177280
+ 1603 002e 0BD0     		beq	.L135
+ 1604 0030 0023     		movs	r3, #0
+ 1605 0032 0193     		str	r3, [sp, #4]
+ 1606              	.L128:
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (tmphadcSlave.Instance == NULL)
+ 1607              		.loc 1 889 5 view .LVU491
+ 1608              		.loc 1 889 21 is_stmt 0 view .LVU492
+ 1609 0034 019B     		ldr	r3, [sp, #4]
+ 1610              		.loc 1 889 8 view .LVU493
+ 1611 0036 5BB1     		cbz	r3, .L136
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set ADC state */
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Process unlocked */
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_UNLOCK(hadc);
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       return HAL_ERROR;
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Enable the ADC peripherals: master and slave (in case if not already   */
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* enabled previously)                                                    */
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = ADC_Enable(hadc);
+ 1612              		.loc 1 902 5 is_stmt 1 view .LVU494
+ 1613              		.loc 1 902 22 is_stmt 0 view .LVU495
+ 1614 0038 2046     		mov	r0, r4
+ 1615 003a FFF7FEFF 		bl	ADC_Enable
+ 1616              	.LVL124:
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (tmp_hal_status == HAL_OK)
+ 1617              		.loc 1 903 5 is_stmt 1 view .LVU496
+ 1618              		.loc 1 903 8 is_stmt 0 view .LVU497
+ 1619 003e 80B1     		cbz	r0, .L137
+ 1620              	.L130:
+ 1621              	.LVL125:
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmp_hal_status = ADC_Enable(&tmphadcSlave);
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Start multimode conversion of ADCs pair */
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (tmp_hal_status == HAL_OK)
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set ADC state */
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       ADC_STATE_CLR_SET(hadc->State,
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                         (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                         HAL_ADC_STATE_REG_BUSY);
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set ADC error code to none */
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       ADC_CLEAR_ERRORCODE(hadc);
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set the DMA transfer complete callback */
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ARM GAS  /tmp/cc3JIfda.s 			page 172
+
+
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set the DMA half transfer complete callback */
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set the DMA error callback */
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Pointer to the common control register  */
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* start (in case of SW start):                                           */
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Clear regular group conversion flag and overrun flag */
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* (To ensure of no unknown state from potential previous ADC operations) */
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Process unlocked */
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Unlock before starting ADC conversions: in case of potential         */
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* interruption, to let the process to ADC IRQ Handler.                 */
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_UNLOCK(hadc);
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Enable ADC overrun interrupt */
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Start the DMA channel */
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Enable conversion of regular group.                                    */
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* If software start has been selected, conversion starts immediately.    */
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* If external trigger has been selected, conversion will start at next   */
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* trigger event.                                                         */
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Start ADC group regular conversion */
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       LL_ADC_REG_StartConversion(hadc->Instance);
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Process unlocked */
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_UNLOCK(hadc);
+ 1622              		.loc 1 959 7 is_stmt 1 view .LVU498
+ 1623              		.loc 1 959 7 view .LVU499
+ 1624 0040 0023     		movs	r3, #0
+ 1625 0042 84F85830 		strb	r3, [r4, #88]
+ 1626              	.LVL126:
+ 1627              		.loc 1 959 7 view .LVU500
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Return function status */
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     return tmp_hal_status;
+ 1628              		.loc 1 963 5 view .LVU501
+ 1629              		.loc 1 963 12 is_stmt 0 view .LVU502
+ 1630 0046 3FE0     		b	.L126
+ 1631              	.LVL127:
+ 1632              	.L135:
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1633              		.loc 1 887 5 discriminator 1 view .LVU503
+ 1634 0048 03F58073 		add	r3, r3, #256
+ 1635 004c 0193     		str	r3, [sp, #4]
+ARM GAS  /tmp/cc3JIfda.s 			page 173
+
+
+ 1636 004e F1E7     		b	.L128
+ 1637              	.L136:
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1638              		.loc 1 892 7 is_stmt 1 view .LVU504
+ 1639 0050 E36D     		ldr	r3, [r4, #92]
+ 1640 0052 43F02003 		orr	r3, r3, #32
+ 1641 0056 E365     		str	r3, [r4, #92]
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1642              		.loc 1 895 7 view .LVU505
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1643              		.loc 1 895 7 view .LVU506
+ 1644 0058 0023     		movs	r3, #0
+ 1645 005a 84F85830 		strb	r3, [r4, #88]
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1646              		.loc 1 895 7 view .LVU507
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 1647              		.loc 1 897 7 view .LVU508
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 1648              		.loc 1 897 14 is_stmt 0 view .LVU509
+ 1649 005e 0120     		movs	r0, #1
+ 1650 0060 32E0     		b	.L126
+ 1651              	.LVL128:
+ 1652              	.L137:
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 1653              		.loc 1 905 7 is_stmt 1 view .LVU510
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 1654              		.loc 1 905 24 is_stmt 0 view .LVU511
+ 1655 0062 01A8     		add	r0, sp, #4
+ 1656              	.LVL129:
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 1657              		.loc 1 905 24 view .LVU512
+ 1658 0064 FFF7FEFF 		bl	ADC_Enable
+ 1659              	.LVL130:
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 1660              		.loc 1 909 5 is_stmt 1 view .LVU513
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 1661              		.loc 1 909 8 is_stmt 0 view .LVU514
+ 1662 0068 0028     		cmp	r0, #0
+ 1663 006a E9D1     		bne	.L130
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                         (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_
+ 1664              		.loc 1 912 7 is_stmt 1 view .LVU515
+ 1665 006c E36D     		ldr	r3, [r4, #92]
+ 1666 006e 23F47063 		bic	r3, r3, #3840
+ 1667 0072 23F00103 		bic	r3, r3, #1
+ 1668 0076 43F48073 		orr	r3, r3, #256
+ 1669 007a E365     		str	r3, [r4, #92]
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1670              		.loc 1 917 7 view .LVU516
+ 1671 007c 0023     		movs	r3, #0
+ 1672 007e 2366     		str	r3, [r4, #96]
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1673              		.loc 1 920 7 view .LVU517
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1674              		.loc 1 920 11 is_stmt 0 view .LVU518
+ 1675 0080 626D     		ldr	r2, [r4, #84]
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1676              		.loc 1 920 42 view .LVU519
+ARM GAS  /tmp/cc3JIfda.s 			page 174
+
+
+ 1677 0082 1349     		ldr	r1, .L138
+ 1678 0084 D162     		str	r1, [r2, #44]
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1679              		.loc 1 923 7 is_stmt 1 view .LVU520
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1680              		.loc 1 923 11 is_stmt 0 view .LVU521
+ 1681 0086 626D     		ldr	r2, [r4, #84]
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1682              		.loc 1 923 46 view .LVU522
+ 1683 0088 1249     		ldr	r1, .L138+4
+ 1684 008a 1163     		str	r1, [r2, #48]
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1685              		.loc 1 926 7 is_stmt 1 view .LVU523
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1686              		.loc 1 926 11 is_stmt 0 view .LVU524
+ 1687 008c 626D     		ldr	r2, [r4, #84]
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1688              		.loc 1 926 43 view .LVU525
+ 1689 008e 1249     		ldr	r1, .L138+8
+ 1690 0090 5163     		str	r1, [r2, #52]
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1691              		.loc 1 929 7 is_stmt 1 view .LVU526
+ 1692              	.LVL131:
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1693              		.loc 1 936 7 view .LVU527
+ 1694 0092 2268     		ldr	r2, [r4]
+ 1695 0094 1C21     		movs	r1, #28
+ 1696 0096 1160     		str	r1, [r2]
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1697              		.loc 1 941 7 view .LVU528
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1698              		.loc 1 941 7 view .LVU529
+ 1699 0098 84F85830 		strb	r3, [r4, #88]
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1700              		.loc 1 941 7 view .LVU530
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1701              		.loc 1 944 7 view .LVU531
+ 1702 009c 2268     		ldr	r2, [r4]
+ 1703 009e 5368     		ldr	r3, [r2, #4]
+ 1704 00a0 43F01003 		orr	r3, r3, #16
+ 1705 00a4 5360     		str	r3, [r2, #4]
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1706              		.loc 1 947 7 view .LVU532
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1707              		.loc 1 947 24 is_stmt 0 view .LVU533
+ 1708 00a6 2B46     		mov	r3, r5
+ 1709 00a8 3246     		mov	r2, r6
+ 1710 00aa 0C49     		ldr	r1, .L138+12
+ 1711 00ac 606D     		ldr	r0, [r4, #84]
+ 1712              	.LVL132:
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1713              		.loc 1 947 24 view .LVU534
+ 1714 00ae FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 1715              	.LVL133:
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 1716              		.loc 1 954 7 is_stmt 1 view .LVU535
+ 1717 00b2 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/cc3JIfda.s 			page 175
+
+
+ 1718              	.LVL134:
+ 1719              	.LBB328:
+ 1720              	.LBI328:
+6815:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1721              		.loc 2 6815 22 view .LVU536
+ 1722              	.LBB329:
+6820:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 1723              		.loc 2 6820 3 view .LVU537
+ 1724 00b4 9368     		ldr	r3, [r2, #8]
+ 1725 00b6 23F00043 		bic	r3, r3, #-2147483648
+ 1726 00ba 23F03F03 		bic	r3, r3, #63
+ 1727 00be 43F00403 		orr	r3, r3, #4
+ 1728 00c2 9360     		str	r3, [r2, #8]
+6823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 1729              		.loc 2 6823 1 is_stmt 0 view .LVU538
+ 1730 00c4 00E0     		b	.L126
+ 1731              	.LVL135:
+ 1732              	.L132:
+6823:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 1733              		.loc 2 6823 1 view .LVU539
+ 1734              	.LBE329:
+ 1735              	.LBE328:
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 1736              		.loc 1 875 12 view .LVU540
+ 1737 00c6 0220     		movs	r0, #2
+ 1738              	.LVL136:
+ 1739              	.L126:
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 1740              		.loc 1 965 1 view .LVU541
+ 1741 00c8 1CB0     		add	sp, sp, #112
+ 1742              	.LCFI17:
+ 1743              		.cfi_remember_state
+ 1744              		.cfi_def_cfa_offset 16
+ 1745              		@ sp needed
+ 1746 00ca 70BD     		pop	{r4, r5, r6, pc}
+ 1747              	.LVL137:
+ 1748              	.L133:
+ 1749              	.LCFI18:
+ 1750              		.cfi_restore_state
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1751              		.loc 1 880 5 view .LVU542
+ 1752 00cc 0220     		movs	r0, #2
+ 1753 00ce FBE7     		b	.L126
+ 1754              	.L139:
+ 1755              		.align	2
+ 1756              	.L138:
+ 1757 00d0 00000000 		.word	ADC_DMAConvCplt
+ 1758 00d4 00000000 		.word	ADC_DMAHalfConvCplt
+ 1759 00d8 00000000 		.word	ADC_DMAError
+ 1760 00dc 0C030050 		.word	1342178060
+ 1761              		.cfi_endproc
+ 1762              	.LFE337:
+ 1764              		.section	.text.HAL_ADCEx_MultiModeStop_DMA,"ax",%progbits
+ 1765              		.align	1
+ 1766              		.global	HAL_ADCEx_MultiModeStop_DMA
+ 1767              		.syntax unified
+ARM GAS  /tmp/cc3JIfda.s 			page 176
+
+
+ 1768              		.thumb
+ 1769              		.thumb_func
+ 1771              	HAL_ADCEx_MultiModeStop_DMA:
+ 1772              	.LVL138:
+ 1773              	.LFB338:
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Multimode is kept enabled after this function. MultiMode DMA bits
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         resort to HAL_ADCEx_DisableMultiMode() API.
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   In case of DMA configured in circular mode, function
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         HAL_ADC_Stop_DMA() must be called after this function with handle of
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         ADC slave, to properly disable the DMA channel.
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 1774              		.loc 1 981 1 is_stmt 1 view -0
+ 1775              		.cfi_startproc
+ 1776              		@ args = 0, pretend = 0, frame = 112
+ 1777              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1778              		.loc 1 981 1 is_stmt 0 view .LVU544
+ 1779 0000 70B5     		push	{r4, r5, r6, lr}
+ 1780              	.LCFI19:
+ 1781              		.cfi_def_cfa_offset 16
+ 1782              		.cfi_offset 4, -16
+ 1783              		.cfi_offset 5, -12
+ 1784              		.cfi_offset 6, -8
+ 1785              		.cfi_offset 14, -4
+ 1786 0002 9CB0     		sub	sp, sp, #112
+ 1787              	.LCFI20:
+ 1788              		.cfi_def_cfa_offset 128
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 1789              		.loc 1 982 3 is_stmt 1 view .LVU545
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tickstart;
+ 1790              		.loc 1 983 3 view .LVU546
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ADC_HandleTypeDef tmphadcSlave;
+ 1791              		.loc 1 984 3 view .LVU547
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmphadcSlave_conversion_on_going;
+ 1792              		.loc 1 985 3 view .LVU548
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmphadcSlave_disable_status;
+ 1793              		.loc 1 986 3 view .LVU549
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ 1794              		.loc 1 989 3 view .LVU550
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process locked */
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 1795              		.loc 1 992 3 view .LVU551
+ 1796              		.loc 1 992 3 view .LVU552
+ 1797 0004 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 1798 0008 012B     		cmp	r3, #1
+ARM GAS  /tmp/cc3JIfda.s 			page 177
+
+
+ 1799 000a 00F08580 		beq	.L158
+ 1800 000e 0446     		mov	r4, r0
+ 1801              		.loc 1 992 3 discriminator 2 view .LVU553
+ 1802 0010 0123     		movs	r3, #1
+ 1803 0012 80F85830 		strb	r3, [r0, #88]
+ 1804              		.loc 1 992 3 discriminator 2 view .LVU554
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* 1. Stop potential multimode conversion on going, on regular and injected groups */
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+ 1805              		.loc 1 996 3 discriminator 2 view .LVU555
+ 1806              		.loc 1 996 20 is_stmt 0 discriminator 2 view .LVU556
+ 1807 0016 0321     		movs	r1, #3
+ 1808 0018 FFF7FEFF 		bl	ADC_ConversionStop
+ 1809              	.LVL139:
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Disable ADC peripheral if conversions are effectively stopped */
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (tmp_hal_status == HAL_OK)
+ 1810              		.loc 1 999 3 is_stmt 1 discriminator 2 view .LVU557
+ 1811              		.loc 1 999 6 is_stmt 0 discriminator 2 view .LVU558
+ 1812 001c 0546     		mov	r5, r0
+ 1813 001e 0028     		cmp	r0, #0
+ 1814 0020 74D1     		bne	.L142
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Temporary handle minimum initialization */
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ 1815              		.loc 1 1002 5 is_stmt 1 view .LVU559
+ 1816 0022 0023     		movs	r3, #0
+ 1817 0024 1893     		str	r3, [sp, #96]
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+ 1818              		.loc 1 1003 5 view .LVU560
+ 1819 0026 1993     		str	r3, [sp, #100]
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Set a temporary handle of the ADC slave associated to the ADC master   */
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+ 1820              		.loc 1 1006 5 view .LVU561
+ 1821 0028 2368     		ldr	r3, [r4]
+ 1822 002a B3F1A04F 		cmp	r3, #1342177280
+ 1823 002e 0DD0     		beq	.L161
+ 1824              		.loc 1 1006 5 is_stmt 0 discriminator 2 view .LVU562
+ 1825 0030 0023     		movs	r3, #0
+ 1826 0032 0193     		str	r3, [sp, #4]
+ 1827              	.L144:
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (tmphadcSlave.Instance == NULL)
+ 1828              		.loc 1 1008 5 is_stmt 1 view .LVU563
+ 1829              		.loc 1 1008 21 is_stmt 0 view .LVU564
+ 1830 0034 019B     		ldr	r3, [sp, #4]
+ 1831              		.loc 1 1008 8 view .LVU565
+ 1832 0036 6BB1     		cbz	r3, .L162
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Update ADC state machine to error */
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Process unlocked */
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_UNLOCK(hadc);
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ARM GAS  /tmp/cc3JIfda.s 			page 178
+
+
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       return HAL_ERROR;
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Procedure to disable the ADC peripheral: wait for conversions          */
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tickstart = HAL_GetTick();
+ 1833              		.loc 1 1023 5 is_stmt 1 view .LVU566
+ 1834              		.loc 1 1023 17 is_stmt 0 view .LVU567
+ 1835 0038 FFF7FEFF 		bl	HAL_GetTick
+ 1836              	.LVL140:
+ 1837              		.loc 1 1023 17 view .LVU568
+ 1838 003c 0546     		mov	r5, r0
+ 1839              	.LVL141:
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ 1840              		.loc 1 1025 5 is_stmt 1 view .LVU569
+ 1841              		.loc 1 1025 40 is_stmt 0 view .LVU570
+ 1842 003e 019B     		ldr	r3, [sp, #4]
+ 1843              	.LVL142:
+ 1844              	.LBB330:
+ 1845              	.LBI330:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1846              		.loc 2 6851 26 is_stmt 1 view .LVU571
+ 1847              	.LBB331:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1848              		.loc 2 6853 3 view .LVU572
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1849              		.loc 2 6853 12 is_stmt 0 view .LVU573
+ 1850 0040 9B68     		ldr	r3, [r3, #8]
+ 1851              	.LVL143:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1852              		.loc 2 6853 74 view .LVU574
+ 1853 0042 13F00403 		ands	r3, r3, #4
+ 1854 0046 13D0     		beq	.L153
+ 1855 0048 0123     		movs	r3, #1
+ 1856 004a 11E0     		b	.L153
+ 1857              	.LVL144:
+ 1858              	.L161:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1859              		.loc 2 6853 74 view .LVU575
+ 1860              	.LBE331:
+ 1861              	.LBE330:
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1862              		.loc 1 1006 5 discriminator 1 view .LVU576
+ 1863 004c 03F58073 		add	r3, r3, #256
+ 1864 0050 0193     		str	r3, [sp, #4]
+ 1865 0052 EFE7     		b	.L144
+ 1866              	.L162:
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1867              		.loc 1 1011 7 is_stmt 1 view .LVU577
+ 1868 0054 E36D     		ldr	r3, [r4, #92]
+ 1869 0056 43F02003 		orr	r3, r3, #32
+ 1870 005a E365     		str	r3, [r4, #92]
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1871              		.loc 1 1014 7 view .LVU578
+ARM GAS  /tmp/cc3JIfda.s 			page 179
+
+
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1872              		.loc 1 1014 7 view .LVU579
+ 1873 005c 0023     		movs	r3, #0
+ 1874 005e 84F85830 		strb	r3, [r4, #88]
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1875              		.loc 1 1014 7 view .LVU580
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 1876              		.loc 1 1016 7 view .LVU581
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 1877              		.loc 1 1016 14 is_stmt 0 view .LVU582
+ 1878 0062 0125     		movs	r5, #1
+ 1879 0064 55E0     		b	.L141
+ 1880              	.LVL145:
+ 1881              	.L148:
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****            || (tmphadcSlave_conversion_on_going == 1UL)
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           )
+1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* New check to avoid false timeout detection in case of preemption */
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             || (tmphadcSlave_conversion_on_going == 1UL)
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****            )
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           /* Update ADC state machine to error */
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           /* Process unlocked */
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           __HAL_UNLOCK(hadc);
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           return HAL_ERROR;
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ 1882              		.loc 1 1048 7 is_stmt 1 view .LVU583
+ 1883              		.loc 1 1048 42 is_stmt 0 view .LVU584
+ 1884 0066 019B     		ldr	r3, [sp, #4]
+ 1885              	.LVL146:
+ 1886              	.LBB332:
+ 1887              	.LBI332:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1888              		.loc 2 6851 26 is_stmt 1 view .LVU585
+ 1889              	.LBB333:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1890              		.loc 2 6853 3 view .LVU586
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1891              		.loc 2 6853 12 is_stmt 0 view .LVU587
+ 1892 0068 9B68     		ldr	r3, [r3, #8]
+ 1893              	.LVL147:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1894              		.loc 2 6853 74 view .LVU588
+ 1895 006a 13F00403 		ands	r3, r3, #4
+ 1896 006e 21D1     		bne	.L151
+ 1897              	.LVL148:
+ARM GAS  /tmp/cc3JIfda.s 			page 180
+
+
+ 1898              	.L153:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1899              		.loc 2 6853 74 view .LVU589
+ 1900              	.LBE333:
+ 1901              	.LBE332:
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           )
+ 1902              		.loc 1 1027 12 is_stmt 1 view .LVU590
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****            || (tmphadcSlave_conversion_on_going == 1UL)
+ 1903              		.loc 1 1026 13 is_stmt 0 view .LVU591
+ 1904 0070 2268     		ldr	r2, [r4]
+ 1905              	.LVL149:
+ 1906              	.LBB335:
+ 1907              	.LBI335:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1908              		.loc 2 6851 26 is_stmt 1 view .LVU592
+ 1909              	.LBB336:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1910              		.loc 2 6853 3 view .LVU593
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1911              		.loc 2 6853 12 is_stmt 0 view .LVU594
+ 1912 0072 9268     		ldr	r2, [r2, #8]
+ 1913              	.LVL150:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1914              		.loc 2 6853 74 view .LVU595
+ 1915 0074 12F0040F 		tst	r2, #4
+ 1916 0078 01D1     		bne	.L154
+ 1917              	.LVL151:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1918              		.loc 2 6853 74 view .LVU596
+ 1919              	.LBE336:
+ 1920              	.LBE335:
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           )
+ 1921              		.loc 1 1027 12 view .LVU597
+ 1922 007a 012B     		cmp	r3, #1
+ 1923 007c 1CD1     		bne	.L163
+ 1924              	.L154:
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 1925              		.loc 1 1030 7 is_stmt 1 view .LVU598
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 1926              		.loc 1 1030 12 is_stmt 0 view .LVU599
+ 1927 007e FFF7FEFF 		bl	HAL_GetTick
+ 1928              	.LVL152:
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 1929              		.loc 1 1030 26 view .LVU600
+ 1930 0082 431B     		subs	r3, r0, r5
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 1931              		.loc 1 1030 10 view .LVU601
+ 1932 0084 052B     		cmp	r3, #5
+ 1933 0086 EED9     		bls	.L148
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ 1934              		.loc 1 1033 9 is_stmt 1 view .LVU602
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ 1935              		.loc 1 1033 44 is_stmt 0 view .LVU603
+ 1936 0088 019B     		ldr	r3, [sp, #4]
+ 1937              	.LVL153:
+ 1938              	.LBB337:
+ 1939              	.LBI337:
+ARM GAS  /tmp/cc3JIfda.s 			page 181
+
+
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1940              		.loc 2 6851 26 is_stmt 1 view .LVU604
+ 1941              	.LBB338:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1942              		.loc 2 6853 3 view .LVU605
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1943              		.loc 2 6853 12 is_stmt 0 view .LVU606
+ 1944 008a 9B68     		ldr	r3, [r3, #8]
+ 1945              	.LVL154:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1946              		.loc 2 6853 74 view .LVU607
+ 1947 008c 13F00403 		ands	r3, r3, #4
+ 1948 0090 00D0     		beq	.L149
+ 1949 0092 0123     		movs	r3, #1
+ 1950              	.L149:
+ 1951              	.LVL155:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1952              		.loc 2 6853 74 view .LVU608
+ 1953              	.LBE338:
+ 1954              	.LBE337:
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             || (tmphadcSlave_conversion_on_going == 1UL)
+ 1955              		.loc 1 1034 9 is_stmt 1 view .LVU609
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             || (tmphadcSlave_conversion_on_going == 1UL)
+ 1956              		.loc 1 1034 14 is_stmt 0 view .LVU610
+ 1957 0094 2268     		ldr	r2, [r4]
+ 1958              	.LVL156:
+ 1959              	.LBB339:
+ 1960              	.LBI339:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 1961              		.loc 2 6851 26 is_stmt 1 view .LVU611
+ 1962              	.LBB340:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1963              		.loc 2 6853 3 view .LVU612
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1964              		.loc 2 6853 12 is_stmt 0 view .LVU613
+ 1965 0096 9268     		ldr	r2, [r2, #8]
+ 1966              	.LVL157:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1967              		.loc 2 6853 74 view .LVU614
+ 1968 0098 12F0040F 		tst	r2, #4
+ 1969 009c 01D1     		bne	.L150
+ 1970              	.LVL158:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1971              		.loc 2 6853 74 view .LVU615
+ 1972              	.LBE340:
+ 1973              	.LBE339:
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****            )
+ 1974              		.loc 1 1035 13 view .LVU616
+ 1975 009e 012B     		cmp	r3, #1
+ 1976 00a0 E1D1     		bne	.L148
+ 1977              	.L150:
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1978              		.loc 1 1039 11 is_stmt 1 view .LVU617
+ 1979 00a2 E36D     		ldr	r3, [r4, #92]
+ 1980              	.LVL159:
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1981              		.loc 1 1039 11 is_stmt 0 view .LVU618
+ARM GAS  /tmp/cc3JIfda.s 			page 182
+
+
+ 1982 00a4 43F01003 		orr	r3, r3, #16
+ 1983 00a8 E365     		str	r3, [r4, #92]
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1984              		.loc 1 1042 11 is_stmt 1 view .LVU619
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1985              		.loc 1 1042 11 view .LVU620
+ 1986 00aa 0023     		movs	r3, #0
+ 1987 00ac 84F85830 		strb	r3, [r4, #88]
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 1988              		.loc 1 1042 11 view .LVU621
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 1989              		.loc 1 1044 11 view .LVU622
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 1990              		.loc 1 1044 18 is_stmt 0 view .LVU623
+ 1991 00b0 0125     		movs	r5, #1
+ 1992              	.LVL160:
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 1993              		.loc 1 1044 18 view .LVU624
+ 1994 00b2 2EE0     		b	.L141
+ 1995              	.LVL161:
+ 1996              	.L151:
+ 1997              	.LBB341:
+ 1998              	.LBB334:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 1999              		.loc 2 6853 74 view .LVU625
+ 2000 00b4 0123     		movs	r3, #1
+ 2001 00b6 DBE7     		b	.L153
+ 2002              	.LVL162:
+ 2003              	.L163:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2004              		.loc 2 6853 74 view .LVU626
+ 2005              	.LBE334:
+ 2006              	.LBE341:
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* while DMA transfer is on going)                                        */
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Note: DMA channel of ADC slave should be stopped after this function   */
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /*       with HAL_ADC_Stop_DMA() API.                                     */
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+ 2007              		.loc 1 1055 5 is_stmt 1 view .LVU627
+ 2008              		.loc 1 1055 22 is_stmt 0 view .LVU628
+ 2009 00b8 606D     		ldr	r0, [r4, #84]
+ 2010 00ba FFF7FEFF 		bl	HAL_DMA_Abort
+ 2011              	.LVL163:
+ 2012              		.loc 1 1055 22 view .LVU629
+ 2013 00be 0546     		mov	r5, r0
+ 2014              	.LVL164:
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Check if DMA channel effectively disabled */
+1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (tmp_hal_status == HAL_ERROR)
+ 2015              		.loc 1 1058 5 is_stmt 1 view .LVU630
+ 2016              		.loc 1 1058 8 is_stmt 0 view .LVU631
+ 2017 00c0 0128     		cmp	r0, #1
+ 2018 00c2 10D0     		beq	.L164
+ 2019              	.L155:
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ARM GAS  /tmp/cc3JIfda.s 			page 183
+
+
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Update ADC state machine to error */
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Disable ADC overrun interrupt */
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+ 2020              		.loc 1 1065 5 is_stmt 1 view .LVU632
+ 2021 00c4 2268     		ldr	r2, [r4]
+ 2022 00c6 5368     		ldr	r3, [r2, #4]
+ 2023 00c8 23F01003 		bic	r3, r3, #16
+ 2024 00cc 5360     		str	r3, [r2, #4]
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* 2. Disable the ADC peripherals: master and slave */
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* memory a potential failing status.                                     */
+1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (tmp_hal_status == HAL_OK)
+ 2025              		.loc 1 1070 5 view .LVU633
+ 2026              		.loc 1 1070 8 is_stmt 0 view .LVU634
+ 2027 00ce 7DB9     		cbnz	r5, .L156
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
+ 2028              		.loc 1 1072 7 is_stmt 1 view .LVU635
+ 2029              		.loc 1 1072 37 is_stmt 0 view .LVU636
+ 2030 00d0 01A8     		add	r0, sp, #4
+ 2031              	.LVL165:
+ 2032              		.loc 1 1072 37 view .LVU637
+ 2033 00d2 FFF7FEFF 		bl	ADC_Disable
+ 2034              	.LVL166:
+ 2035 00d6 0646     		mov	r6, r0
+ 2036              	.LVL167:
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if ((ADC_Disable(hadc) == HAL_OK)           &&
+ 2037              		.loc 1 1073 7 is_stmt 1 view .LVU638
+ 2038              		.loc 1 1073 12 is_stmt 0 view .LVU639
+ 2039 00d8 2046     		mov	r0, r4
+ 2040 00da FFF7FEFF 		bl	ADC_Disable
+ 2041              	.LVL168:
+ 2042              		.loc 1 1073 10 view .LVU640
+ 2043 00de 68B9     		cbnz	r0, .L157
+ 2044              		.loc 1 1073 51 discriminator 1 view .LVU641
+ 2045 00e0 66B9     		cbnz	r6, .L157
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           (tmphadcSlave_disable_status == HAL_OK))
+1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         tmp_hal_status = HAL_OK;
+ 2046              		.loc 1 1076 24 view .LVU642
+ 2047 00e2 3546     		mov	r5, r6
+ 2048 00e4 0AE0     		b	.L157
+ 2049              	.LVL169:
+ 2050              	.L164:
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 2051              		.loc 1 1061 7 is_stmt 1 view .LVU643
+ 2052 00e6 E36D     		ldr	r3, [r4, #92]
+ 2053 00e8 43F04003 		orr	r3, r3, #64
+ 2054 00ec E365     		str	r3, [r4, #92]
+ 2055 00ee E9E7     		b	.L155
+ 2056              	.L156:
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ARM GAS  /tmp/cc3JIfda.s 			page 184
+
+
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* In case of error, attempt to disable ADC master and slave without status assert */
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (void) ADC_Disable(hadc);
+ 2057              		.loc 1 1082 7 view .LVU644
+ 2058              		.loc 1 1082 14 is_stmt 0 view .LVU645
+ 2059 00f0 2046     		mov	r0, r4
+ 2060              	.LVL170:
+ 2061              		.loc 1 1082 14 view .LVU646
+ 2062 00f2 FFF7FEFF 		bl	ADC_Disable
+ 2063              	.LVL171:
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (void) ADC_Disable(&tmphadcSlave);
+ 2064              		.loc 1 1083 7 is_stmt 1 view .LVU647
+ 2065              		.loc 1 1083 14 is_stmt 0 view .LVU648
+ 2066 00f6 01A8     		add	r0, sp, #4
+ 2067 00f8 FFF7FEFF 		bl	ADC_Disable
+ 2068              	.LVL172:
+ 2069              	.L157:
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Set ADC state (ADC master) */
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     ADC_STATE_CLR_SET(hadc->State,
+ 2070              		.loc 1 1087 5 is_stmt 1 view .LVU649
+ 2071 00fc E36D     		ldr	r3, [r4, #92]
+ 2072 00fe 23F48853 		bic	r3, r3, #4352
+ 2073 0102 23F00103 		bic	r3, r3, #1
+ 2074 0106 43F00103 		orr	r3, r3, #1
+ 2075 010a E365     		str	r3, [r4, #92]
+ 2076              	.LVL173:
+ 2077              	.L142:
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                       HAL_ADC_STATE_READY);
+1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process unlocked */
+1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 2078              		.loc 1 1093 3 view .LVU650
+ 2079              		.loc 1 1093 3 view .LVU651
+ 2080 010c 0023     		movs	r3, #0
+ 2081 010e 84F85830 		strb	r3, [r4, #88]
+ 2082              		.loc 1 1093 3 view .LVU652
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return function status */
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 2083              		.loc 1 1096 3 view .LVU653
+ 2084              	.LVL174:
+ 2085              	.L141:
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 2086              		.loc 1 1097 1 is_stmt 0 view .LVU654
+ 2087 0112 2846     		mov	r0, r5
+ 2088 0114 1CB0     		add	sp, sp, #112
+ 2089              	.LCFI21:
+ 2090              		.cfi_remember_state
+ 2091              		.cfi_def_cfa_offset 16
+ 2092              		@ sp needed
+ 2093 0116 70BD     		pop	{r4, r5, r6, pc}
+ 2094              	.LVL175:
+ARM GAS  /tmp/cc3JIfda.s 			page 185
+
+
+ 2095              	.L158:
+ 2096              	.LCFI22:
+ 2097              		.cfi_restore_state
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2098              		.loc 1 992 3 view .LVU655
+ 2099 0118 0225     		movs	r5, #2
+ 2100 011a FAE7     		b	.L141
+ 2101              		.cfi_endproc
+ 2102              	.LFE338:
+ 2104              		.section	.text.HAL_ADCEx_MultiModeGetValue,"ax",%progbits
+ 2105              		.align	1
+ 2106              		.global	HAL_ADCEx_MultiModeGetValue
+ 2107              		.syntax unified
+ 2108              		.thumb
+ 2109              		.thumb_func
+ 2111              	HAL_ADCEx_MultiModeGetValue:
+ 2112              	.LVL176:
+ 2113              	.LFB339:
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Return the last ADC Master and Slave regular conversions results when in multimode conf
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval The converted data values.
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 2114              		.loc 1 1105 1 is_stmt 1 view -0
+ 2115              		.cfi_startproc
+ 2116              		@ args = 0, pretend = 0, frame = 0
+ 2117              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2118              		@ link register save eliminated.
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   const ADC_Common_TypeDef *tmpADC_Common;
+ 2119              		.loc 1 1106 3 view .LVU657
+1107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ 2120              		.loc 1 1109 3 view .LVU658
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Prevent unused argument(s) compilation warning if no assert_param check */
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below               */
+1113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   UNUSED(hadc);
+ 2121              		.loc 1 1113 3 view .LVU659
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Pointer to the common control register  */
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+ 2122              		.loc 1 1116 3 view .LVU660
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return the multi mode conversion value */
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmpADC_Common->CDR;
+ 2123              		.loc 1 1119 3 view .LVU661
+ 2124              		.loc 1 1119 23 is_stmt 0 view .LVU662
+ 2125 0000 014B     		ldr	r3, .L166
+ 2126 0002 D868     		ldr	r0, [r3, #12]
+ 2127              	.LVL177:
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 2128              		.loc 1 1120 1 view .LVU663
+ 2129 0004 7047     		bx	lr
+ARM GAS  /tmp/cc3JIfda.s 			page 186
+
+
+ 2130              	.L167:
+ 2131 0006 00BF     		.align	2
+ 2132              	.L166:
+ 2133 0008 00030050 		.word	1342178048
+ 2134              		.cfi_endproc
+ 2135              	.LFE339:
+ 2137              		.section	.text.HAL_ADCEx_InjectedGetValue,"ax",%progbits
+ 2138              		.align	1
+ 2139              		.global	HAL_ADCEx_InjectedGetValue
+ 2140              		.syntax unified
+ 2141              		.thumb
+ 2142              		.thumb_func
+ 2144              	HAL_ADCEx_InjectedGetValue:
+ 2145              	.LVL178:
+ 2146              	.LFB340:
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #endif /* ADC_MULTIMODE_SUPPORT */
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Get ADC injected group conversion result.
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Reading register JDRx automatically clears ADC flag JEOC
+1126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         (ADC group injected end of unitary conversion).
+1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   This function does not clear ADC flag JEOS
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         (ADC group injected end of sequence conversion)
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         Occurrence of flag JEOS rising:
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
+1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *            to flag JEOC.
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *          - If sequencer is composed of several ranks, during the scan
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *            sequence flag JEOC only is raised, at the end of the scan sequence
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *            both flags JEOC and EOS are raised.
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         Flag JEOS must not be cleared by this function because
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         it would not be compliant with low power features
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         (feature low power auto-wait, not available on all STM32 families).
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         To clear this flag, either use function:
+1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param InjectedRank the converted ADC injected rank.
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *          This parameter can be one of the following values:
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *            @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *            @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *            @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *            @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval ADC group injected conversion data
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
+1152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 2147              		.loc 1 1152 1 is_stmt 1 view -0
+ 2148              		.cfi_startproc
+ 2149              		@ args = 0, pretend = 0, frame = 0
+ 2150              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2151              		@ link register save eliminated.
+1153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_jdr;
+ 2152              		.loc 1 1153 3 view .LVU665
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ARM GAS  /tmp/cc3JIfda.s 			page 187
+
+
+ 2153              		.loc 1 1156 3 view .LVU666
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+ 2154              		.loc 1 1157 3 view .LVU667
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Get ADC converted value */
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   switch (InjectedRank)
+ 2155              		.loc 1 1160 3 view .LVU668
+ 2156 0000 40F21523 		movw	r3, #533
+ 2157 0004 9942     		cmp	r1, r3
+ 2158 0006 0FD0     		beq	.L169
+ 2159 0008 40F21B33 		movw	r3, #795
+ 2160 000c 9942     		cmp	r1, r3
+ 2161 000e 07D0     		beq	.L170
+ 2162 0010 40F20F13 		movw	r3, #271
+ 2163 0014 9942     		cmp	r1, r3
+ 2164 0016 0BD0     		beq	.L175
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_4:
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmp_jdr = hadc->Instance->JDR4;
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_3:
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmp_jdr = hadc->Instance->JDR3;
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_2:
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmp_jdr = hadc->Instance->JDR2;
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_1:
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     default:
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmp_jdr = hadc->Instance->JDR1;
+ 2165              		.loc 1 1173 7 view .LVU669
+ 2166              		.loc 1 1173 21 is_stmt 0 view .LVU670
+ 2167 0018 0368     		ldr	r3, [r0]
+ 2168              		.loc 1 1173 15 view .LVU671
+ 2169 001a D3F88000 		ldr	r0, [r3, #128]
+ 2170              	.LVL179:
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+ 2171              		.loc 1 1174 7 is_stmt 1 view .LVU672
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return ADC converted value */
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_jdr;
+ 2172              		.loc 1 1178 3 view .LVU673
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 2173              		.loc 1 1179 1 is_stmt 0 view .LVU674
+ 2174 001e 7047     		bx	lr
+ 2175              	.LVL180:
+ 2176              	.L170:
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+ 2177              		.loc 1 1163 7 is_stmt 1 view .LVU675
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+ 2178              		.loc 1 1163 21 is_stmt 0 view .LVU676
+ 2179 0020 0368     		ldr	r3, [r0]
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+ 2180              		.loc 1 1163 15 view .LVU677
+ 2181 0022 D3F88C00 		ldr	r0, [r3, #140]
+ 2182              	.LVL181:
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_3:
+ARM GAS  /tmp/cc3JIfda.s 			page 188
+
+
+ 2183              		.loc 1 1164 7 is_stmt 1 view .LVU678
+ 2184 0026 7047     		bx	lr
+ 2185              	.LVL182:
+ 2186              	.L169:
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+ 2187              		.loc 1 1166 7 view .LVU679
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+ 2188              		.loc 1 1166 21 is_stmt 0 view .LVU680
+ 2189 0028 0368     		ldr	r3, [r0]
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+ 2190              		.loc 1 1166 15 view .LVU681
+ 2191 002a D3F88800 		ldr	r0, [r3, #136]
+ 2192              	.LVL183:
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_2:
+ 2193              		.loc 1 1167 7 is_stmt 1 view .LVU682
+ 2194 002e 7047     		bx	lr
+ 2195              	.LVL184:
+ 2196              	.L175:
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+ 2197              		.loc 1 1169 7 view .LVU683
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+ 2198              		.loc 1 1169 21 is_stmt 0 view .LVU684
+ 2199 0030 0368     		ldr	r3, [r0]
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       break;
+ 2200              		.loc 1 1169 15 view .LVU685
+ 2201 0032 D3F88400 		ldr	r0, [r3, #132]
+ 2202              	.LVL185:
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_1:
+ 2203              		.loc 1 1170 7 is_stmt 1 view .LVU686
+ 2204 0036 7047     		bx	lr
+ 2205              		.cfi_endproc
+ 2206              	.LFE340:
+ 2208              		.section	.text.HAL_ADCEx_InjectedConvCpltCallback,"ax",%progbits
+ 2209              		.align	1
+ 2210              		.weak	HAL_ADCEx_InjectedConvCpltCallback
+ 2211              		.syntax unified
+ 2212              		.thumb
+ 2213              		.thumb_func
+ 2215              	HAL_ADCEx_InjectedConvCpltCallback:
+ 2216              	.LVL186:
+ 2217              	.LFB341:
+1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Injected conversion complete callback in non-blocking mode.
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval None
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 2218              		.loc 1 1187 1 view -0
+ 2219              		.cfi_startproc
+ 2220              		@ args = 0, pretend = 0, frame = 0
+ 2221              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2222              		@ link register save eliminated.
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Prevent unused argument(s) compilation warning */
+1189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   UNUSED(hadc);
+ 2223              		.loc 1 1189 3 view .LVU688
+ARM GAS  /tmp/cc3JIfda.s 			page 189
+
+
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* NOTE : This function should not be modified. When the callback is needed,
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 2224              		.loc 1 1194 1 is_stmt 0 view .LVU689
+ 2225 0000 7047     		bx	lr
+ 2226              		.cfi_endproc
+ 2227              	.LFE341:
+ 2229              		.section	.text.HAL_ADCEx_InjectedQueueOverflowCallback,"ax",%progbits
+ 2230              		.align	1
+ 2231              		.weak	HAL_ADCEx_InjectedQueueOverflowCallback
+ 2232              		.syntax unified
+ 2233              		.thumb
+ 2234              		.thumb_func
+ 2236              	HAL_ADCEx_InjectedQueueOverflowCallback:
+ 2237              	.LVL187:
+ 2238              	.LFB342:
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Injected context queue overflow callback.
+1198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   This callback is called if injected context queue is enabled
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             (parameter "QueueInjectedContext" in injected channel configuration)
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             and if a new injected context is set when queue is full (maximum 2
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             contexts).
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+1203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval None
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
+1206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 2239              		.loc 1 1206 1 is_stmt 1 view -0
+ 2240              		.cfi_startproc
+ 2241              		@ args = 0, pretend = 0, frame = 0
+ 2242              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2243              		@ link register save eliminated.
+1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Prevent unused argument(s) compilation warning */
+1208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   UNUSED(hadc);
+ 2244              		.loc 1 1208 3 view .LVU691
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* NOTE : This function should not be modified. When the callback is needed,
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 2245              		.loc 1 1213 1 is_stmt 0 view .LVU692
+ 2246 0000 7047     		bx	lr
+ 2247              		.cfi_endproc
+ 2248              	.LFE342:
+ 2250              		.section	.text.HAL_ADCEx_LevelOutOfWindow2Callback,"ax",%progbits
+ 2251              		.align	1
+ 2252              		.weak	HAL_ADCEx_LevelOutOfWindow2Callback
+ 2253              		.syntax unified
+ 2254              		.thumb
+ 2255              		.thumb_func
+ 2257              	HAL_ADCEx_LevelOutOfWindow2Callback:
+ 2258              	.LVL188:
+ 2259              	.LFB343:
+1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ARM GAS  /tmp/cc3JIfda.s 			page 190
+
+
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Analog watchdog 2 callback in non-blocking mode.
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval None
+1219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 2260              		.loc 1 1221 1 is_stmt 1 view -0
+ 2261              		.cfi_startproc
+ 2262              		@ args = 0, pretend = 0, frame = 0
+ 2263              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2264              		@ link register save eliminated.
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Prevent unused argument(s) compilation warning */
+1223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   UNUSED(hadc);
+ 2265              		.loc 1 1223 3 view .LVU694
+1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* NOTE : This function should not be modified. When the callback is needed,
+1226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 2266              		.loc 1 1228 1 is_stmt 0 view .LVU695
+ 2267 0000 7047     		bx	lr
+ 2268              		.cfi_endproc
+ 2269              	.LFE343:
+ 2271              		.section	.text.HAL_ADCEx_LevelOutOfWindow3Callback,"ax",%progbits
+ 2272              		.align	1
+ 2273              		.weak	HAL_ADCEx_LevelOutOfWindow3Callback
+ 2274              		.syntax unified
+ 2275              		.thumb
+ 2276              		.thumb_func
+ 2278              	HAL_ADCEx_LevelOutOfWindow3Callback:
+ 2279              	.LVL189:
+ 2280              	.LFB344:
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Analog watchdog 3 callback in non-blocking mode.
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval None
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 2281              		.loc 1 1236 1 is_stmt 1 view -0
+ 2282              		.cfi_startproc
+ 2283              		@ args = 0, pretend = 0, frame = 0
+ 2284              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2285              		@ link register save eliminated.
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Prevent unused argument(s) compilation warning */
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   UNUSED(hadc);
+ 2286              		.loc 1 1238 3 view .LVU697
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* NOTE : This function should not be modified. When the callback is needed,
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 2287              		.loc 1 1243 1 is_stmt 0 view .LVU698
+ 2288 0000 7047     		bx	lr
+ 2289              		.cfi_endproc
+ARM GAS  /tmp/cc3JIfda.s 			page 191
+
+
+ 2290              	.LFE344:
+ 2292              		.section	.text.HAL_ADCEx_EndOfSamplingCallback,"ax",%progbits
+ 2293              		.align	1
+ 2294              		.weak	HAL_ADCEx_EndOfSamplingCallback
+ 2295              		.syntax unified
+ 2296              		.thumb
+ 2297              		.thumb_func
+ 2299              	HAL_ADCEx_EndOfSamplingCallback:
+ 2300              	.LVL190:
+ 2301              	.LFB345:
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  End Of Sampling callback in non-blocking mode.
+1248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval None
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
+1252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 2302              		.loc 1 1252 1 is_stmt 1 view -0
+ 2303              		.cfi_startproc
+ 2304              		@ args = 0, pretend = 0, frame = 0
+ 2305              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2306              		@ link register save eliminated.
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Prevent unused argument(s) compilation warning */
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   UNUSED(hadc);
+ 2307              		.loc 1 1254 3 view .LVU700
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* NOTE : This function should not be modified. When the callback is needed,
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 2308              		.loc 1 1259 1 is_stmt 0 view .LVU701
+ 2309 0000 7047     		bx	lr
+ 2310              		.cfi_endproc
+ 2311              	.LFE345:
+ 2313              		.section	.text.HAL_ADCEx_RegularStop,"ax",%progbits
+ 2314              		.align	1
+ 2315              		.global	HAL_ADCEx_RegularStop
+ 2316              		.syntax unified
+ 2317              		.thumb
+ 2318              		.thumb_func
+ 2320              	HAL_ADCEx_RegularStop:
+ 2321              	.LVL191:
+ 2322              	.LFB346:
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Stop ADC conversion of regular group (and injected channels in
+1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         case of auto_injection mode), disable ADC peripheral if no
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         conversion is on going on injected group.
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status.
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 2323              		.loc 1 1269 1 is_stmt 1 view -0
+ 2324              		.cfi_startproc
+ARM GAS  /tmp/cc3JIfda.s 			page 192
+
+
+ 2325              		@ args = 0, pretend = 0, frame = 0
+ 2326              		@ frame_needed = 0, uses_anonymous_args = 0
+1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 2327              		.loc 1 1270 3 view .LVU703
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 2328              		.loc 1 1273 3 view .LVU704
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process locked */
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 2329              		.loc 1 1276 3 view .LVU705
+ 2330              		.loc 1 1276 3 view .LVU706
+ 2331 0000 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 2332 0004 012B     		cmp	r3, #1
+ 2333 0006 26D0     		beq	.L185
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 2334              		.loc 1 1269 1 is_stmt 0 discriminator 2 view .LVU707
+ 2335 0008 10B5     		push	{r4, lr}
+ 2336              	.LCFI23:
+ 2337              		.cfi_def_cfa_offset 8
+ 2338              		.cfi_offset 4, -8
+ 2339              		.cfi_offset 14, -4
+ 2340 000a 0446     		mov	r4, r0
+ 2341              		.loc 1 1276 3 is_stmt 1 discriminator 2 view .LVU708
+ 2342 000c 0121     		movs	r1, #1
+ 2343 000e 80F85810 		strb	r1, [r0, #88]
+ 2344              		.loc 1 1276 3 discriminator 2 view .LVU709
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* 1. Stop potential regular conversion on going */
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+ 2345              		.loc 1 1279 3 discriminator 2 view .LVU710
+ 2346              		.loc 1 1279 20 is_stmt 0 discriminator 2 view .LVU711
+ 2347 0012 FFF7FEFF 		bl	ADC_ConversionStop
+ 2348              	.LVL192:
+1280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Disable ADC peripheral if regular conversions are effectively stopped
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****      and if no injected conversions are on-going */
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (tmp_hal_status == HAL_OK)
+ 2349              		.loc 1 1283 3 is_stmt 1 discriminator 2 view .LVU712
+ 2350              		.loc 1 1283 6 is_stmt 0 discriminator 2 view .LVU713
+ 2351 0016 60B9     		cbnz	r0, .L183
+1284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Clear HAL_ADC_STATE_REG_BUSY bit */
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ 2352              		.loc 1 1286 5 is_stmt 1 view .LVU714
+ 2353 0018 E36D     		ldr	r3, [r4, #92]
+ 2354 001a 23F48073 		bic	r3, r3, #256
+ 2355 001e E365     		str	r3, [r4, #92]
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ 2356              		.loc 1 1288 5 view .LVU715
+ 2357              		.loc 1 1288 9 is_stmt 0 view .LVU716
+ 2358 0020 2368     		ldr	r3, [r4]
+ 2359              	.LVL193:
+ 2360              	.LBB342:
+ 2361              	.LBI342:
+ARM GAS  /tmp/cc3JIfda.s 			page 193
+
+
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2362              		.loc 2 7076 26 is_stmt 1 view .LVU717
+ 2363              	.LBB343:
+ 2364              		.loc 2 7078 3 view .LVU718
+ 2365              		.loc 2 7078 12 is_stmt 0 view .LVU719
+ 2366 0022 9B68     		ldr	r3, [r3, #8]
+ 2367              	.LVL194:
+ 2368              		.loc 2 7078 76 view .LVU720
+ 2369 0024 13F0080F 		tst	r3, #8
+ 2370 0028 07D0     		beq	.L184
+ 2371              	.LVL195:
+ 2372              		.loc 2 7078 76 view .LVU721
+ 2373              	.LBE343:
+ 2374              	.LBE342:
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* 2. Disable the ADC peripheral */
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmp_hal_status = ADC_Disable(hadc);
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Check if ADC is effectively disabled */
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (tmp_hal_status == HAL_OK)
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Set ADC state */
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         ADC_STATE_CLR_SET(hadc->State,
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_INJ_BUSY,
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_READY);
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Conversion on injected group is stopped, but ADC not disabled since    */
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* conversion on regular group is still running.                          */
+1304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ 2375              		.loc 1 1306 7 is_stmt 1 view .LVU722
+ 2376 002a E36D     		ldr	r3, [r4, #92]
+ 2377 002c 43F48053 		orr	r3, r3, #4096
+ 2378 0030 E365     		str	r3, [r4, #92]
+ 2379              	.L183:
+1307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process unlocked */
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 2380              		.loc 1 1311 3 view .LVU723
+ 2381              		.loc 1 1311 3 view .LVU724
+ 2382 0032 0023     		movs	r3, #0
+ 2383 0034 84F85830 		strb	r3, [r4, #88]
+ 2384              		.loc 1 1311 3 view .LVU725
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return function status */
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 2385              		.loc 1 1314 3 view .LVU726
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 2386              		.loc 1 1315 1 is_stmt 0 view .LVU727
+ 2387 0038 10BD     		pop	{r4, pc}
+ 2388              	.LVL196:
+ 2389              	.L184:
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ARM GAS  /tmp/cc3JIfda.s 			page 194
+
+
+ 2390              		.loc 1 1291 7 is_stmt 1 view .LVU728
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2391              		.loc 1 1291 24 is_stmt 0 view .LVU729
+ 2392 003a 2046     		mov	r0, r4
+ 2393              	.LVL197:
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2394              		.loc 1 1291 24 view .LVU730
+ 2395 003c FFF7FEFF 		bl	ADC_Disable
+ 2396              	.LVL198:
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 2397              		.loc 1 1294 7 is_stmt 1 view .LVU731
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 2398              		.loc 1 1294 10 is_stmt 0 view .LVU732
+ 2399 0040 0028     		cmp	r0, #0
+ 2400 0042 F6D1     		bne	.L183
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_INJ_BUSY,
+ 2401              		.loc 1 1297 9 is_stmt 1 view .LVU733
+ 2402 0044 E36D     		ldr	r3, [r4, #92]
+ 2403 0046 23F48053 		bic	r3, r3, #4096
+ 2404 004a 23F00103 		bic	r3, r3, #1
+ 2405 004e 43F00103 		orr	r3, r3, #1
+ 2406 0052 E365     		str	r3, [r4, #92]
+ 2407 0054 EDE7     		b	.L183
+ 2408              	.LVL199:
+ 2409              	.L185:
+ 2410              	.LCFI24:
+ 2411              		.cfi_def_cfa_offset 0
+ 2412              		.cfi_restore 4
+ 2413              		.cfi_restore 14
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2414              		.loc 1 1276 3 is_stmt 0 view .LVU734
+ 2415 0056 0220     		movs	r0, #2
+ 2416              	.LVL200:
+ 2417              		.loc 1 1315 1 view .LVU735
+ 2418 0058 7047     		bx	lr
+ 2419              		.cfi_endproc
+ 2420              	.LFE346:
+ 2422              		.section	.text.HAL_ADCEx_RegularStop_IT,"ax",%progbits
+ 2423              		.align	1
+ 2424              		.global	HAL_ADCEx_RegularStop_IT
+ 2425              		.syntax unified
+ 2426              		.thumb
+ 2427              		.thumb_func
+ 2429              	HAL_ADCEx_RegularStop_IT:
+ 2430              	.LVL201:
+ 2431              	.LFB347:
+1316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Stop ADC conversion of ADC groups regular and injected,
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         disable interrution of end-of-conversion,
+1321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         disable ADC peripheral if no conversion is on going
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         on injected group.
+1323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status.
+1325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
+ARM GAS  /tmp/cc3JIfda.s 			page 195
+
+
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 2432              		.loc 1 1327 1 is_stmt 1 view -0
+ 2433              		.cfi_startproc
+ 2434              		@ args = 0, pretend = 0, frame = 0
+ 2435              		@ frame_needed = 0, uses_anonymous_args = 0
+1328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 2436              		.loc 1 1328 3 view .LVU737
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 2437              		.loc 1 1331 3 view .LVU738
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process locked */
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 2438              		.loc 1 1334 3 view .LVU739
+ 2439              		.loc 1 1334 3 view .LVU740
+ 2440 0000 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 2441 0004 012B     		cmp	r3, #1
+ 2442 0006 2BD0     		beq	.L194
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 2443              		.loc 1 1327 1 is_stmt 0 discriminator 2 view .LVU741
+ 2444 0008 10B5     		push	{r4, lr}
+ 2445              	.LCFI25:
+ 2446              		.cfi_def_cfa_offset 8
+ 2447              		.cfi_offset 4, -8
+ 2448              		.cfi_offset 14, -4
+ 2449 000a 0446     		mov	r4, r0
+ 2450              		.loc 1 1334 3 is_stmt 1 discriminator 2 view .LVU742
+ 2451 000c 0121     		movs	r1, #1
+ 2452 000e 80F85810 		strb	r1, [r0, #88]
+ 2453              		.loc 1 1334 3 discriminator 2 view .LVU743
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* 1. Stop potential regular conversion on going */
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+ 2454              		.loc 1 1337 3 discriminator 2 view .LVU744
+ 2455              		.loc 1 1337 20 is_stmt 0 discriminator 2 view .LVU745
+ 2456 0012 FFF7FEFF 		bl	ADC_ConversionStop
+ 2457              	.LVL202:
+1338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Disable ADC peripheral if conversions are effectively stopped
+1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     and if no injected conversion is on-going */
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (tmp_hal_status == HAL_OK)
+ 2458              		.loc 1 1341 3 is_stmt 1 discriminator 2 view .LVU746
+ 2459              		.loc 1 1341 6 is_stmt 0 discriminator 2 view .LVU747
+ 2460 0016 88B9     		cbnz	r0, .L192
+1342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Clear HAL_ADC_STATE_REG_BUSY bit */
+1344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ 2461              		.loc 1 1344 5 is_stmt 1 view .LVU748
+ 2462 0018 E36D     		ldr	r3, [r4, #92]
+ 2463 001a 23F48073 		bic	r3, r3, #256
+ 2464 001e E365     		str	r3, [r4, #92]
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Disable all regular-related interrupts */
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+ 2465              		.loc 1 1347 5 view .LVU749
+ 2466 0020 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/cc3JIfda.s 			page 196
+
+
+ 2467 0022 5368     		ldr	r3, [r2, #4]
+ 2468 0024 23F01C03 		bic	r3, r3, #28
+ 2469 0028 5360     		str	r3, [r2, #4]
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* 2. Disable ADC peripheral if no injected conversions are on-going */
+1350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ 2470              		.loc 1 1350 5 view .LVU750
+ 2471              		.loc 1 1350 9 is_stmt 0 view .LVU751
+ 2472 002a 2368     		ldr	r3, [r4]
+ 2473              	.LVL203:
+ 2474              	.LBB344:
+ 2475              	.LBI344:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2476              		.loc 2 7076 26 is_stmt 1 view .LVU752
+ 2477              	.LBB345:
+ 2478              		.loc 2 7078 3 view .LVU753
+ 2479              		.loc 2 7078 12 is_stmt 0 view .LVU754
+ 2480 002c 9B68     		ldr	r3, [r3, #8]
+ 2481              	.LVL204:
+ 2482              		.loc 2 7078 76 view .LVU755
+ 2483 002e 13F0080F 		tst	r3, #8
+ 2484 0032 07D0     		beq	.L193
+ 2485              	.LVL205:
+ 2486              		.loc 2 7078 76 view .LVU756
+ 2487              	.LBE345:
+ 2488              	.LBE344:
+1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmp_hal_status = ADC_Disable(hadc);
+1353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* if no issue reported */
+1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (tmp_hal_status == HAL_OK)
+1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Set ADC state */
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         ADC_STATE_CLR_SET(hadc->State,
+1358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_INJ_BUSY,
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_READY);
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ 2489              		.loc 1 1364 7 is_stmt 1 view .LVU757
+ 2490 0034 E36D     		ldr	r3, [r4, #92]
+ 2491 0036 43F48053 		orr	r3, r3, #4096
+ 2492 003a E365     		str	r3, [r4, #92]
+ 2493              	.L192:
+1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process unlocked */
+1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 2494              		.loc 1 1369 3 view .LVU758
+ 2495              		.loc 1 1369 3 view .LVU759
+ 2496 003c 0023     		movs	r3, #0
+ 2497 003e 84F85830 		strb	r3, [r4, #88]
+ 2498              		.loc 1 1369 3 view .LVU760
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return function status */
+ARM GAS  /tmp/cc3JIfda.s 			page 197
+
+
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 2499              		.loc 1 1372 3 view .LVU761
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 2500              		.loc 1 1373 1 is_stmt 0 view .LVU762
+ 2501 0042 10BD     		pop	{r4, pc}
+ 2502              	.LVL206:
+ 2503              	.L193:
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* if no issue reported */
+ 2504              		.loc 1 1352 7 is_stmt 1 view .LVU763
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* if no issue reported */
+ 2505              		.loc 1 1352 24 is_stmt 0 view .LVU764
+ 2506 0044 2046     		mov	r0, r4
+ 2507              	.LVL207:
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* if no issue reported */
+ 2508              		.loc 1 1352 24 view .LVU765
+ 2509 0046 FFF7FEFF 		bl	ADC_Disable
+ 2510              	.LVL208:
+1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 2511              		.loc 1 1354 7 is_stmt 1 view .LVU766
+1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 2512              		.loc 1 1354 10 is_stmt 0 view .LVU767
+ 2513 004a 0028     		cmp	r0, #0
+ 2514 004c F6D1     		bne	.L192
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_INJ_BUSY,
+ 2515              		.loc 1 1357 9 is_stmt 1 view .LVU768
+ 2516 004e E36D     		ldr	r3, [r4, #92]
+ 2517 0050 23F48053 		bic	r3, r3, #4096
+ 2518 0054 23F00103 		bic	r3, r3, #1
+ 2519 0058 43F00103 		orr	r3, r3, #1
+ 2520 005c E365     		str	r3, [r4, #92]
+ 2521 005e EDE7     		b	.L192
+ 2522              	.LVL209:
+ 2523              	.L194:
+ 2524              	.LCFI26:
+ 2525              		.cfi_def_cfa_offset 0
+ 2526              		.cfi_restore 4
+ 2527              		.cfi_restore 14
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2528              		.loc 1 1334 3 is_stmt 0 view .LVU769
+ 2529 0060 0220     		movs	r0, #2
+ 2530              	.LVL210:
+ 2531              		.loc 1 1373 1 view .LVU770
+ 2532 0062 7047     		bx	lr
+ 2533              		.cfi_endproc
+ 2534              	.LFE347:
+ 2536              		.section	.text.HAL_ADCEx_RegularStop_DMA,"ax",%progbits
+ 2537              		.align	1
+ 2538              		.global	HAL_ADCEx_RegularStop_DMA
+ 2539              		.syntax unified
+ 2540              		.thumb
+ 2541              		.thumb_func
+ 2543              	HAL_ADCEx_RegularStop_DMA:
+ 2544              	.LVL211:
+ 2545              	.LFB348:
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Stop ADC conversion of regular group (and injected group in
+ARM GAS  /tmp/cc3JIfda.s 			page 198
+
+
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         case of auto_injection mode), disable ADC DMA transfer, disable
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         ADC peripheral if no conversion is on going
+1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         on injected group.
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         For multimode (when multimode feature is available),
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+1384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status.
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
+1387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 2546              		.loc 1 1387 1 is_stmt 1 view -0
+ 2547              		.cfi_startproc
+ 2548              		@ args = 0, pretend = 0, frame = 0
+ 2549              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2550              		.loc 1 1387 1 is_stmt 0 view .LVU772
+ 2551 0000 38B5     		push	{r3, r4, r5, lr}
+ 2552              	.LCFI27:
+ 2553              		.cfi_def_cfa_offset 16
+ 2554              		.cfi_offset 3, -16
+ 2555              		.cfi_offset 4, -12
+ 2556              		.cfi_offset 5, -8
+ 2557              		.cfi_offset 14, -4
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 2558              		.loc 1 1388 3 is_stmt 1 view .LVU773
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 2559              		.loc 1 1391 3 view .LVU774
+1392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process locked */
+1394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 2560              		.loc 1 1394 3 view .LVU775
+ 2561              		.loc 1 1394 3 view .LVU776
+ 2562 0002 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 2563 0006 012B     		cmp	r3, #1
+ 2564 0008 41D0     		beq	.L206
+ 2565 000a 0446     		mov	r4, r0
+ 2566              		.loc 1 1394 3 discriminator 2 view .LVU777
+ 2567 000c 0121     		movs	r1, #1
+ 2568 000e 80F85810 		strb	r1, [r0, #88]
+ 2569              		.loc 1 1394 3 discriminator 2 view .LVU778
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* 1. Stop potential regular conversion on going */
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+ 2570              		.loc 1 1397 3 discriminator 2 view .LVU779
+ 2571              		.loc 1 1397 20 is_stmt 0 discriminator 2 view .LVU780
+ 2572 0012 FFF7FEFF 		bl	ADC_ConversionStop
+ 2573              	.LVL212:
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Disable ADC peripheral if conversions are effectively stopped
+1400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****      and if no injected conversion is on-going */
+1401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (tmp_hal_status == HAL_OK)
+ 2574              		.loc 1 1401 3 is_stmt 1 discriminator 2 view .LVU781
+ 2575              		.loc 1 1401 6 is_stmt 0 discriminator 2 view .LVU782
+ 2576 0016 0546     		mov	r5, r0
+ 2577 0018 20B1     		cbz	r0, .L208
+ARM GAS  /tmp/cc3JIfda.s 			page 199
+
+
+ 2578              	.LVL213:
+ 2579              	.L201:
+1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Clear HAL_ADC_STATE_REG_BUSY bit */
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+1405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* while DMA transfer is on going)                                        */
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+1412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Check if DMA channel effectively disabled */
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (tmp_hal_status != HAL_OK)
+1415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Update ADC state machine to error */
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Disable ADC overrun interrupt */
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* 2. Disable the ADC peripheral */
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* to keep in memory a potential failing status.                          */
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+1427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (tmp_hal_status == HAL_OK)
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         tmp_hal_status = ADC_Disable(hadc);
+1431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       else
+1433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         (void)ADC_Disable(hadc);
+1435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Check if ADC is effectively disabled */
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (tmp_hal_status == HAL_OK)
+1439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Set ADC state */
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         ADC_STATE_CLR_SET(hadc->State,
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_INJ_BUSY,
+1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_READY);
+1444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process unlocked */
+1453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 2580              		.loc 1 1453 3 is_stmt 1 view .LVU783
+ 2581              		.loc 1 1453 3 view .LVU784
+ 2582 001a 0023     		movs	r3, #0
+ARM GAS  /tmp/cc3JIfda.s 			page 200
+
+
+ 2583 001c 84F85830 		strb	r3, [r4, #88]
+ 2584              		.loc 1 1453 3 view .LVU785
+1454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return function status */
+1456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 2585              		.loc 1 1456 3 view .LVU786
+ 2586              	.LVL214:
+ 2587              	.L200:
+1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 2588              		.loc 1 1457 1 is_stmt 0 view .LVU787
+ 2589 0020 2846     		mov	r0, r5
+ 2590 0022 38BD     		pop	{r3, r4, r5, pc}
+ 2591              	.LVL215:
+ 2592              	.L208:
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2593              		.loc 1 1404 5 is_stmt 1 view .LVU788
+ 2594 0024 E36D     		ldr	r3, [r4, #92]
+ 2595 0026 23F48073 		bic	r3, r3, #256
+ 2596 002a E365     		str	r3, [r4, #92]
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2597              		.loc 1 1407 5 view .LVU789
+ 2598 002c 2268     		ldr	r2, [r4]
+ 2599 002e D368     		ldr	r3, [r2, #12]
+ 2600 0030 23F00103 		bic	r3, r3, #1
+ 2601 0034 D360     		str	r3, [r2, #12]
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2602              		.loc 1 1411 5 view .LVU790
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2603              		.loc 1 1411 22 is_stmt 0 view .LVU791
+ 2604 0036 606D     		ldr	r0, [r4, #84]
+ 2605              	.LVL216:
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2606              		.loc 1 1411 22 view .LVU792
+ 2607 0038 FFF7FEFF 		bl	HAL_DMA_Abort
+ 2608              	.LVL217:
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 2609              		.loc 1 1414 5 is_stmt 1 view .LVU793
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 2610              		.loc 1 1414 8 is_stmt 0 view .LVU794
+ 2611 003c 0546     		mov	r5, r0
+ 2612 003e 18B1     		cbz	r0, .L202
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 2613              		.loc 1 1417 7 is_stmt 1 view .LVU795
+ 2614 0040 E36D     		ldr	r3, [r4, #92]
+ 2615 0042 43F04003 		orr	r3, r3, #64
+ 2616 0046 E365     		str	r3, [r4, #92]
+ 2617              	.L202:
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2618              		.loc 1 1421 5 view .LVU796
+ 2619 0048 2268     		ldr	r2, [r4]
+ 2620 004a 5368     		ldr	r3, [r2, #4]
+ 2621 004c 23F01003 		bic	r3, r3, #16
+ 2622 0050 5360     		str	r3, [r2, #4]
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 2623              		.loc 1 1426 5 view .LVU797
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 2624              		.loc 1 1426 9 is_stmt 0 view .LVU798
+ARM GAS  /tmp/cc3JIfda.s 			page 201
+
+
+ 2625 0052 2368     		ldr	r3, [r4]
+ 2626              	.LVL218:
+ 2627              	.LBB346:
+ 2628              	.LBI346:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2629              		.loc 2 7076 26 is_stmt 1 view .LVU799
+ 2630              	.LBB347:
+ 2631              		.loc 2 7078 3 view .LVU800
+ 2632              		.loc 2 7078 12 is_stmt 0 view .LVU801
+ 2633 0054 9B68     		ldr	r3, [r3, #8]
+ 2634              	.LVL219:
+ 2635              		.loc 2 7078 76 view .LVU802
+ 2636 0056 13F0080F 		tst	r3, #8
+ 2637 005a 04D0     		beq	.L203
+ 2638              	.LVL220:
+ 2639              		.loc 2 7078 76 view .LVU803
+ 2640              	.LBE347:
+ 2641              	.LBE346:
+1448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 2642              		.loc 1 1448 7 is_stmt 1 view .LVU804
+ 2643 005c E36D     		ldr	r3, [r4, #92]
+ 2644 005e 43F48053 		orr	r3, r3, #4096
+ 2645 0062 E365     		str	r3, [r4, #92]
+ 2646 0064 D9E7     		b	.L201
+ 2647              	.LVL221:
+ 2648              	.L203:
+1428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 2649              		.loc 1 1428 7 view .LVU805
+1428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 2650              		.loc 1 1428 10 is_stmt 0 view .LVU806
+ 2651 0066 75B9     		cbnz	r5, .L204
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 2652              		.loc 1 1430 9 is_stmt 1 view .LVU807
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 2653              		.loc 1 1430 26 is_stmt 0 view .LVU808
+ 2654 0068 2046     		mov	r0, r4
+ 2655              	.LVL222:
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 2656              		.loc 1 1430 26 view .LVU809
+ 2657 006a FFF7FEFF 		bl	ADC_Disable
+ 2658              	.LVL223:
+ 2659 006e 0546     		mov	r5, r0
+ 2660              	.LVL224:
+ 2661              	.L205:
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 2662              		.loc 1 1438 7 is_stmt 1 view .LVU810
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 2663              		.loc 1 1438 10 is_stmt 0 view .LVU811
+ 2664 0070 002D     		cmp	r5, #0
+ 2665 0072 D2D1     		bne	.L201
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                           HAL_ADC_STATE_INJ_BUSY,
+ 2666              		.loc 1 1441 9 is_stmt 1 view .LVU812
+ 2667 0074 E36D     		ldr	r3, [r4, #92]
+ 2668 0076 23F48053 		bic	r3, r3, #4096
+ 2669 007a 23F00103 		bic	r3, r3, #1
+ 2670 007e 43F00103 		orr	r3, r3, #1
+ 2671 0082 E365     		str	r3, [r4, #92]
+ARM GAS  /tmp/cc3JIfda.s 			page 202
+
+
+ 2672 0084 C9E7     		b	.L201
+ 2673              	.LVL225:
+ 2674              	.L204:
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 2675              		.loc 1 1434 9 view .LVU813
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 2676              		.loc 1 1434 15 is_stmt 0 view .LVU814
+ 2677 0086 2046     		mov	r0, r4
+ 2678              	.LVL226:
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 2679              		.loc 1 1434 15 view .LVU815
+ 2680 0088 FFF7FEFF 		bl	ADC_Disable
+ 2681              	.LVL227:
+ 2682 008c F0E7     		b	.L205
+ 2683              	.LVL228:
+ 2684              	.L206:
+1394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2685              		.loc 1 1394 3 view .LVU816
+ 2686 008e 0225     		movs	r5, #2
+ 2687 0090 C6E7     		b	.L200
+ 2688              		.cfi_endproc
+ 2689              	.LFE348:
+ 2691              		.section	.text.HAL_ADCEx_RegularMultiModeStop_DMA,"ax",%progbits
+ 2692              		.align	1
+ 2693              		.global	HAL_ADCEx_RegularMultiModeStop_DMA
+ 2694              		.syntax unified
+ 2695              		.thumb
+ 2696              		.thumb_func
+ 2698              	HAL_ADCEx_RegularMultiModeStop_DMA:
+ 2699              	.LVL229:
+ 2700              	.LFB349:
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+1460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripher
+1462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Multimode is kept enabled after this function. Multimode DMA bits
+1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+1464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+1465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         resort to HAL_ADCEx_DisableMultiMode() API.
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   In case of DMA configured in circular mode, function
+1468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
+1469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         ADC slave, to properly disable the DMA channel.
+1470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 2701              		.loc 1 1474 1 is_stmt 1 view -0
+ 2702              		.cfi_startproc
+ 2703              		@ args = 0, pretend = 0, frame = 112
+ 2704              		@ frame_needed = 0, uses_anonymous_args = 0
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 2705              		.loc 1 1475 3 view .LVU818
+1476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tickstart;
+ 2706              		.loc 1 1476 3 view .LVU819
+1477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ADC_HandleTypeDef tmphadcSlave;
+ARM GAS  /tmp/cc3JIfda.s 			page 203
+
+
+ 2707              		.loc 1 1477 3 view .LVU820
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmphadcSlave_conversion_on_going;
+ 2708              		.loc 1 1478 3 view .LVU821
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ 2709              		.loc 1 1481 3 view .LVU822
+1482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process locked */
+1484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 2710              		.loc 1 1484 3 view .LVU823
+ 2711              		.loc 1 1484 3 view .LVU824
+ 2712 0000 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 2713 0004 012B     		cmp	r3, #1
+ 2714 0006 00F08680 		beq	.L226
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 2715              		.loc 1 1474 1 is_stmt 0 discriminator 2 view .LVU825
+ 2716 000a 30B5     		push	{r4, r5, lr}
+ 2717              	.LCFI28:
+ 2718              		.cfi_def_cfa_offset 12
+ 2719              		.cfi_offset 4, -12
+ 2720              		.cfi_offset 5, -8
+ 2721              		.cfi_offset 14, -4
+ 2722 000c 9DB0     		sub	sp, sp, #116
+ 2723              	.LCFI29:
+ 2724              		.cfi_def_cfa_offset 128
+ 2725 000e 0446     		mov	r4, r0
+ 2726              		.loc 1 1484 3 is_stmt 1 discriminator 2 view .LVU826
+ 2727 0010 0121     		movs	r1, #1
+ 2728 0012 80F85810 		strb	r1, [r0, #88]
+ 2729              		.loc 1 1484 3 discriminator 2 view .LVU827
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* 1. Stop potential multimode conversion on going, on regular groups */
+1488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+ 2730              		.loc 1 1488 3 discriminator 2 view .LVU828
+ 2731              		.loc 1 1488 20 is_stmt 0 discriminator 2 view .LVU829
+ 2732 0016 FFF7FEFF 		bl	ADC_ConversionStop
+ 2733              	.LVL230:
+1489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Disable ADC peripheral if conversions are effectively stopped */
+1491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (tmp_hal_status == HAL_OK)
+ 2734              		.loc 1 1491 3 is_stmt 1 discriminator 2 view .LVU830
+ 2735              		.loc 1 1491 6 is_stmt 0 discriminator 2 view .LVU831
+ 2736 001a 0028     		cmp	r0, #0
+ 2737 001c 76D1     		bne	.L211
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Clear HAL_ADC_STATE_REG_BUSY bit */
+1494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ 2738              		.loc 1 1494 5 is_stmt 1 view .LVU832
+ 2739 001e E36D     		ldr	r3, [r4, #92]
+ 2740 0020 23F48073 		bic	r3, r3, #256
+ 2741 0024 E365     		str	r3, [r4, #92]
+1495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Temporary handle minimum initialization */
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ 2742              		.loc 1 1497 5 view .LVU833
+ARM GAS  /tmp/cc3JIfda.s 			page 204
+
+
+ 2743 0026 0023     		movs	r3, #0
+ 2744 0028 1893     		str	r3, [sp, #96]
+1498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+ 2745              		.loc 1 1498 5 view .LVU834
+ 2746 002a 1993     		str	r3, [sp, #100]
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Set a temporary handle of the ADC slave associated to the ADC master   */
+1501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+ 2747              		.loc 1 1501 5 view .LVU835
+ 2748 002c 2368     		ldr	r3, [r4]
+ 2749 002e B3F1A04F 		cmp	r3, #1342177280
+ 2750 0032 0DD0     		beq	.L231
+ 2751              		.loc 1 1501 5 is_stmt 0 discriminator 2 view .LVU836
+ 2752 0034 0023     		movs	r3, #0
+ 2753 0036 0193     		str	r3, [sp, #4]
+ 2754              	.L213:
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (tmphadcSlave.Instance == NULL)
+ 2755              		.loc 1 1503 5 is_stmt 1 view .LVU837
+ 2756              		.loc 1 1503 21 is_stmt 0 view .LVU838
+ 2757 0038 019B     		ldr	r3, [sp, #4]
+ 2758              		.loc 1 1503 8 view .LVU839
+ 2759 003a 6BB1     		cbz	r3, .L232
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Update ADC state machine to error */
+1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Process unlocked */
+1509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       __HAL_UNLOCK(hadc);
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       return HAL_ERROR;
+1512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Procedure to disable the ADC peripheral: wait for conversions          */
+1515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
+1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tickstart = HAL_GetTick();
+ 2760              		.loc 1 1518 5 is_stmt 1 view .LVU840
+ 2761              		.loc 1 1518 17 is_stmt 0 view .LVU841
+ 2762 003c FFF7FEFF 		bl	HAL_GetTick
+ 2763              	.LVL231:
+ 2764              		.loc 1 1518 17 view .LVU842
+ 2765 0040 0546     		mov	r5, r0
+ 2766              	.LVL232:
+1519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ 2767              		.loc 1 1520 5 is_stmt 1 view .LVU843
+ 2768              		.loc 1 1520 40 is_stmt 0 view .LVU844
+ 2769 0042 019B     		ldr	r3, [sp, #4]
+ 2770              	.LVL233:
+ 2771              	.LBB348:
+ 2772              	.LBI348:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2773              		.loc 2 6851 26 is_stmt 1 view .LVU845
+ 2774              	.LBB349:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/cc3JIfda.s 			page 205
+
+
+ 2775              		.loc 2 6853 3 view .LVU846
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2776              		.loc 2 6853 12 is_stmt 0 view .LVU847
+ 2777 0044 9B68     		ldr	r3, [r3, #8]
+ 2778              	.LVL234:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2779              		.loc 2 6853 74 view .LVU848
+ 2780 0046 13F00403 		ands	r3, r3, #4
+ 2781 004a 13D0     		beq	.L222
+ 2782 004c 0123     		movs	r3, #1
+ 2783 004e 11E0     		b	.L222
+ 2784              	.LVL235:
+ 2785              	.L231:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2786              		.loc 2 6853 74 view .LVU849
+ 2787              	.LBE349:
+ 2788              	.LBE348:
+1501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2789              		.loc 1 1501 5 discriminator 1 view .LVU850
+ 2790 0050 03F58073 		add	r3, r3, #256
+ 2791 0054 0193     		str	r3, [sp, #4]
+ 2792 0056 EFE7     		b	.L213
+ 2793              	.L232:
+1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2794              		.loc 1 1506 7 is_stmt 1 view .LVU851
+ 2795 0058 E36D     		ldr	r3, [r4, #92]
+ 2796 005a 43F02003 		orr	r3, r3, #32
+ 2797 005e E365     		str	r3, [r4, #92]
+1509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2798              		.loc 1 1509 7 view .LVU852
+1509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2799              		.loc 1 1509 7 view .LVU853
+ 2800 0060 0023     		movs	r3, #0
+ 2801 0062 84F85830 		strb	r3, [r4, #88]
+1509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2802              		.loc 1 1509 7 view .LVU854
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 2803              		.loc 1 1511 7 view .LVU855
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 2804              		.loc 1 1511 14 is_stmt 0 view .LVU856
+ 2805 0066 0120     		movs	r0, #1
+ 2806              	.LVL236:
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 2807              		.loc 1 1511 14 view .LVU857
+ 2808 0068 53E0     		b	.L210
+ 2809              	.LVL237:
+ 2810              	.L217:
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****            || (tmphadcSlave_conversion_on_going == 1UL)
+1523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           )
+1524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* New check to avoid false timeout detection in case of preemption */
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             || (tmphadcSlave_conversion_on_going == 1UL)
+ARM GAS  /tmp/cc3JIfda.s 			page 206
+
+
+1531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****            )
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           /* Update ADC state machine to error */
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           /* Process unlocked */
+1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           __HAL_UNLOCK(hadc);
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           return HAL_ERROR;
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ 2811              		.loc 1 1543 7 is_stmt 1 view .LVU858
+ 2812              		.loc 1 1543 42 is_stmt 0 view .LVU859
+ 2813 006a 019B     		ldr	r3, [sp, #4]
+ 2814              	.LVL238:
+ 2815              	.LBB350:
+ 2816              	.LBI350:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2817              		.loc 2 6851 26 is_stmt 1 view .LVU860
+ 2818              	.LBB351:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2819              		.loc 2 6853 3 view .LVU861
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2820              		.loc 2 6853 12 is_stmt 0 view .LVU862
+ 2821 006c 9B68     		ldr	r3, [r3, #8]
+ 2822              	.LVL239:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2823              		.loc 2 6853 74 view .LVU863
+ 2824 006e 13F00403 		ands	r3, r3, #4
+ 2825 0072 21D1     		bne	.L220
+ 2826              	.LVL240:
+ 2827              	.L222:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2828              		.loc 2 6853 74 view .LVU864
+ 2829              	.LBE351:
+ 2830              	.LBE350:
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           )
+ 2831              		.loc 1 1522 12 is_stmt 1 view .LVU865
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****            || (tmphadcSlave_conversion_on_going == 1UL)
+ 2832              		.loc 1 1521 13 is_stmt 0 view .LVU866
+ 2833 0074 2268     		ldr	r2, [r4]
+ 2834              	.LVL241:
+ 2835              	.LBB353:
+ 2836              	.LBI353:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2837              		.loc 2 6851 26 is_stmt 1 view .LVU867
+ 2838              	.LBB354:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2839              		.loc 2 6853 3 view .LVU868
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2840              		.loc 2 6853 12 is_stmt 0 view .LVU869
+ 2841 0076 9268     		ldr	r2, [r2, #8]
+ 2842              	.LVL242:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2843              		.loc 2 6853 74 view .LVU870
+ARM GAS  /tmp/cc3JIfda.s 			page 207
+
+
+ 2844 0078 12F0040F 		tst	r2, #4
+ 2845 007c 01D1     		bne	.L223
+ 2846              	.LVL243:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2847              		.loc 2 6853 74 view .LVU871
+ 2848              	.LBE354:
+ 2849              	.LBE353:
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           )
+ 2850              		.loc 1 1522 12 view .LVU872
+ 2851 007e 012B     		cmp	r3, #1
+ 2852 0080 1CD1     		bne	.L233
+ 2853              	.L223:
+1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 2854              		.loc 1 1525 7 is_stmt 1 view .LVU873
+1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 2855              		.loc 1 1525 12 is_stmt 0 view .LVU874
+ 2856 0082 FFF7FEFF 		bl	HAL_GetTick
+ 2857              	.LVL244:
+1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 2858              		.loc 1 1525 26 view .LVU875
+ 2859 0086 431B     		subs	r3, r0, r5
+1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 2860              		.loc 1 1525 10 view .LVU876
+ 2861 0088 052B     		cmp	r3, #5
+ 2862 008a EED9     		bls	.L217
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ 2863              		.loc 1 1528 9 is_stmt 1 view .LVU877
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ 2864              		.loc 1 1528 44 is_stmt 0 view .LVU878
+ 2865 008c 019B     		ldr	r3, [sp, #4]
+ 2866              	.LVL245:
+ 2867              	.LBB355:
+ 2868              	.LBI355:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2869              		.loc 2 6851 26 is_stmt 1 view .LVU879
+ 2870              	.LBB356:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2871              		.loc 2 6853 3 view .LVU880
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2872              		.loc 2 6853 12 is_stmt 0 view .LVU881
+ 2873 008e 9B68     		ldr	r3, [r3, #8]
+ 2874              	.LVL246:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2875              		.loc 2 6853 74 view .LVU882
+ 2876 0090 13F00403 		ands	r3, r3, #4
+ 2877 0094 00D0     		beq	.L218
+ 2878 0096 0123     		movs	r3, #1
+ 2879              	.L218:
+ 2880              	.LVL247:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2881              		.loc 2 6853 74 view .LVU883
+ 2882              	.LBE356:
+ 2883              	.LBE355:
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             || (tmphadcSlave_conversion_on_going == 1UL)
+ 2884              		.loc 1 1529 9 is_stmt 1 view .LVU884
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             || (tmphadcSlave_conversion_on_going == 1UL)
+ 2885              		.loc 1 1529 14 is_stmt 0 view .LVU885
+ARM GAS  /tmp/cc3JIfda.s 			page 208
+
+
+ 2886 0098 2268     		ldr	r2, [r4]
+ 2887              	.LVL248:
+ 2888              	.LBB357:
+ 2889              	.LBI357:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2890              		.loc 2 6851 26 is_stmt 1 view .LVU886
+ 2891              	.LBB358:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2892              		.loc 2 6853 3 view .LVU887
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2893              		.loc 2 6853 12 is_stmt 0 view .LVU888
+ 2894 009a 9268     		ldr	r2, [r2, #8]
+ 2895              	.LVL249:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2896              		.loc 2 6853 74 view .LVU889
+ 2897 009c 12F0040F 		tst	r2, #4
+ 2898 00a0 01D1     		bne	.L219
+ 2899              	.LVL250:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2900              		.loc 2 6853 74 view .LVU890
+ 2901              	.LBE358:
+ 2902              	.LBE357:
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****            )
+ 2903              		.loc 1 1530 13 view .LVU891
+ 2904 00a2 012B     		cmp	r3, #1
+ 2905 00a4 E1D1     		bne	.L217
+ 2906              	.L219:
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2907              		.loc 1 1534 11 is_stmt 1 view .LVU892
+ 2908 00a6 E36D     		ldr	r3, [r4, #92]
+ 2909              	.LVL251:
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2910              		.loc 1 1534 11 is_stmt 0 view .LVU893
+ 2911 00a8 43F01003 		orr	r3, r3, #16
+ 2912 00ac E365     		str	r3, [r4, #92]
+1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2913              		.loc 1 1537 11 is_stmt 1 view .LVU894
+1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2914              		.loc 1 1537 11 view .LVU895
+ 2915 00ae 0023     		movs	r3, #0
+ 2916 00b0 84F85830 		strb	r3, [r4, #88]
+1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 2917              		.loc 1 1537 11 view .LVU896
+1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 2918              		.loc 1 1539 11 view .LVU897
+1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 2919              		.loc 1 1539 18 is_stmt 0 view .LVU898
+ 2920 00b4 0120     		movs	r0, #1
+ 2921 00b6 2CE0     		b	.L210
+ 2922              	.LVL252:
+ 2923              	.L220:
+ 2924              	.LBB359:
+ 2925              	.LBB352:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2926              		.loc 2 6853 74 view .LVU899
+ 2927 00b8 0123     		movs	r3, #1
+ 2928 00ba DBE7     		b	.L222
+ARM GAS  /tmp/cc3JIfda.s 			page 209
+
+
+ 2929              	.LVL253:
+ 2930              	.L233:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 2931              		.loc 2 6853 74 view .LVU900
+ 2932              	.LBE352:
+ 2933              	.LBE359:
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+1547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* while DMA transfer is on going)                                        */
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Note: DMA channel of ADC slave should be stopped after this function   */
+1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
+1550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+ 2934              		.loc 1 1550 5 is_stmt 1 view .LVU901
+ 2935              		.loc 1 1550 22 is_stmt 0 view .LVU902
+ 2936 00bc 606D     		ldr	r0, [r4, #84]
+ 2937 00be FFF7FEFF 		bl	HAL_DMA_Abort
+ 2938              	.LVL254:
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Check if DMA channel effectively disabled */
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (tmp_hal_status != HAL_OK)
+ 2939              		.loc 1 1553 5 is_stmt 1 view .LVU903
+ 2940              		.loc 1 1553 8 is_stmt 0 view .LVU904
+ 2941 00c2 18B1     		cbz	r0, .L224
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Update ADC state machine to error */
+1556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ 2942              		.loc 1 1556 7 is_stmt 1 view .LVU905
+ 2943 00c4 E36D     		ldr	r3, [r4, #92]
+ 2944 00c6 43F04003 		orr	r3, r3, #64
+ 2945 00ca E365     		str	r3, [r4, #92]
+ 2946              	.L224:
+1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Disable ADC overrun interrupt */
+1560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+ 2947              		.loc 1 1560 5 view .LVU906
+ 2948 00cc 2268     		ldr	r2, [r4]
+ 2949 00ce 5368     		ldr	r3, [r2, #4]
+ 2950 00d0 23F01003 		bic	r3, r3, #16
+ 2951 00d4 5360     		str	r3, [r2, #4]
+1561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* 2. Disable the ADC peripherals: master and slave if no injected        */
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /*   conversion is on-going.                                              */
+1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* memory a potential failing status.                                     */
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (tmp_hal_status == HAL_OK)
+ 2952              		.loc 1 1566 5 view .LVU907
+ 2953              		.loc 1 1566 8 is_stmt 0 view .LVU908
+ 2954 00d6 C8B9     		cbnz	r0, .L211
+1567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ 2955              		.loc 1 1568 7 is_stmt 1 view .LVU909
+ 2956              		.loc 1 1568 11 is_stmt 0 view .LVU910
+ 2957 00d8 2368     		ldr	r3, [r4]
+ 2958              	.LVL255:
+ 2959              	.LBB360:
+ARM GAS  /tmp/cc3JIfda.s 			page 210
+
+
+ 2960              	.LBI360:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2961              		.loc 2 7076 26 is_stmt 1 view .LVU911
+ 2962              	.LBB361:
+ 2963              		.loc 2 7078 3 view .LVU912
+ 2964              		.loc 2 7078 12 is_stmt 0 view .LVU913
+ 2965 00da 9B68     		ldr	r3, [r3, #8]
+ 2966              	.LVL256:
+ 2967              		.loc 2 7078 76 view .LVU914
+ 2968 00dc 13F0080F 		tst	r3, #8
+ 2969 00e0 0BD1     		bne	.L225
+ 2970              	.LVL257:
+ 2971              		.loc 2 7078 76 view .LVU915
+ 2972              	.LBE361:
+ 2973              	.LBE360:
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         tmp_hal_status =  ADC_Disable(hadc);
+ 2974              		.loc 1 1570 9 is_stmt 1 view .LVU916
+ 2975              		.loc 1 1570 27 is_stmt 0 view .LVU917
+ 2976 00e2 2046     		mov	r0, r4
+ 2977              	.LVL258:
+ 2978              		.loc 1 1570 27 view .LVU918
+ 2979 00e4 FFF7FEFF 		bl	ADC_Disable
+ 2980              	.LVL259:
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         if (tmp_hal_status == HAL_OK)
+ 2981              		.loc 1 1571 9 is_stmt 1 view .LVU919
+ 2982              		.loc 1 1571 12 is_stmt 0 view .LVU920
+ 2983 00e8 80B9     		cbnz	r0, .L211
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+1573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL)
+ 2984              		.loc 1 1573 11 is_stmt 1 view .LVU921
+ 2985              		.loc 1 1573 15 is_stmt 0 view .LVU922
+ 2986 00ea 019B     		ldr	r3, [sp, #4]
+ 2987              	.LVL260:
+ 2988              	.LBB362:
+ 2989              	.LBI362:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 2990              		.loc 2 7076 26 is_stmt 1 view .LVU923
+ 2991              	.LBB363:
+ 2992              		.loc 2 7078 3 view .LVU924
+ 2993              		.loc 2 7078 12 is_stmt 0 view .LVU925
+ 2994 00ec 9B68     		ldr	r3, [r3, #8]
+ 2995              	.LVL261:
+ 2996              		.loc 2 7078 76 view .LVU926
+ 2997 00ee 13F0080F 		tst	r3, #8
+ 2998 00f2 02D1     		bne	.L225
+ 2999              	.LVL262:
+ 3000              		.loc 2 7078 76 view .LVU927
+ 3001              	.LBE363:
+ 3002              	.LBE362:
+1574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           {
+1575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****             tmp_hal_status =  ADC_Disable(&tmphadcSlave);
+ 3003              		.loc 1 1575 13 is_stmt 1 view .LVU928
+ 3004              		.loc 1 1575 31 is_stmt 0 view .LVU929
+ 3005 00f4 01A8     		add	r0, sp, #4
+ 3006              	.LVL263:
+ 3007              		.loc 1 1575 31 view .LVU930
+ARM GAS  /tmp/cc3JIfda.s 			page 211
+
+
+ 3008 00f6 FFF7FEFF 		bl	ADC_Disable
+ 3009              	.LVL264:
+ 3010              	.L225:
+1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           }
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (tmp_hal_status == HAL_OK)
+ 3011              		.loc 1 1580 7 is_stmt 1 view .LVU931
+ 3012              		.loc 1 1580 10 is_stmt 0 view .LVU932
+ 3013 00fa 38B9     		cbnz	r0, .L211
+1581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Both Master and Slave ADC's could be disabled. Update Master State */
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+ 3014              		.loc 1 1584 9 is_stmt 1 view .LVU933
+ 3015 00fc E36D     		ldr	r3, [r4, #92]
+ 3016 00fe 23F48053 		bic	r3, r3, #4096
+ 3017 0102 23F00103 		bic	r3, r3, #1
+ 3018 0106 43F00103 		orr	r3, r3, #1
+ 3019 010a E365     		str	r3, [r4, #92]
+ 3020              	.LVL265:
+ 3021              	.L211:
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       else
+1587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* injected (Master or Slave) conversions are still on-going,
+1589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****            no Master State change */
+1590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3022              		.loc 1 1590 7 view .LVU934
+1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+1593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process unlocked */
+1595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 3023              		.loc 1 1595 3 view .LVU935
+ 3024              		.loc 1 1595 3 view .LVU936
+ 3025 010c 0023     		movs	r3, #0
+ 3026 010e 84F85830 		strb	r3, [r4, #88]
+ 3027              		.loc 1 1595 3 view .LVU937
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return function status */
+1598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 3028              		.loc 1 1598 3 view .LVU938
+ 3029              	.LVL266:
+ 3030              	.L210:
+1599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 3031              		.loc 1 1599 1 is_stmt 0 view .LVU939
+ 3032 0112 1DB0     		add	sp, sp, #116
+ 3033              	.LCFI30:
+ 3034              		.cfi_def_cfa_offset 12
+ 3035              		@ sp needed
+ 3036 0114 30BD     		pop	{r4, r5, pc}
+ 3037              	.LVL267:
+ 3038              	.L226:
+ 3039              	.LCFI31:
+ 3040              		.cfi_def_cfa_offset 0
+ARM GAS  /tmp/cc3JIfda.s 			page 212
+
+
+ 3041              		.cfi_restore 4
+ 3042              		.cfi_restore 5
+ 3043              		.cfi_restore 14
+1484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3044              		.loc 1 1484 3 view .LVU940
+ 3045 0116 0220     		movs	r0, #2
+ 3046              	.LVL268:
+ 3047              		.loc 1 1599 1 view .LVU941
+ 3048 0118 7047     		bx	lr
+ 3049              		.cfi_endproc
+ 3050              	.LFE349:
+ 3052              		.section	.text.HAL_ADCEx_InjectedConfigChannel,"ax",%progbits
+ 3053              		.align	1
+ 3054              		.global	HAL_ADCEx_InjectedConfigChannel
+ 3055              		.syntax unified
+ 3056              		.thumb
+ 3057              		.thumb_func
+ 3059              	HAL_ADCEx_InjectedConfigChannel:
+ 3060              	.LVL269:
+ 3061              	.LFB350:
+1600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #endif /* ADC_MULTIMODE_SUPPORT */
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @}
+1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief    ADC Extended Peripheral Control functions
+1608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** @verbatim
+1610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****  ===============================================================================
+1611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****              ##### Peripheral Control functions #####
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****  ===============================================================================
+1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     [..]  This section provides functions allowing to:
+1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Configure channels on injected group
+1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Configure multimode when multimode feature is available
+1616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Enable or Disable Injected Queue
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Disable ADC voltage regulator
+1618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (+) Enter ADC deep-power-down mode
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** @endverbatim
+1621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @{
+1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Configure a channel to be assigned to ADC group injected.
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Possibility to update parameters on the fly:
+1627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         This function initializes injected group, following calls to this
+1628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         function can be used to reconfigure some parameters of structure
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
+1630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         The setting of these parameters is conditioned to ADC state:
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         Refer to comments of structure "ADC_InjectionConfTypeDef".
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   In case of usage of internal measurement channels:
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         Vbat/VrefInt/TempSensor.
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         These internal paths can be disabled using function
+1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         HAL_ADC_DeInit().
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Caution: For Injected Context Queue use, a context must be fully
+ARM GAS  /tmp/cc3JIfda.s 			page 213
+
+
+1637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         defined before start of injected conversion. All channels are configured
+1638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         consecutively for the same ADC instance. Therefore, the number of calls to
+1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         InjectedNbrOfConversion for each context.
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *  - Example 1: If 1 context is intended to be used (or if there is no use of the
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *    Injected Queue Context feature) and if the context contains 3 injected ranks
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *    (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
+1644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *    called once for each channel (i.e. 3 times) before starting a conversion.
+1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *    This function must not be called to configure a 4th injected channel:
+1646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *    it would start a new context into context queue.
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *  - Example 2: If 2 contexts are intended to be used and each of them contains
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *    3 injected ranks (InjectedNbrOfConversion = 3),
+1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
+1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *    for each context (3 channels x 2 contexts = 6 calls). Conversion can
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *    start once the 1st context is set, that is after the first three
+1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *    HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param sConfigInjected Structure of ADC injected group and ADC channel for
+1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         injected group.
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+1658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 3062              		.loc 1 1659 1 is_stmt 1 view -0
+ 3063              		.cfi_startproc
+ 3064              		@ args = 0, pretend = 0, frame = 8
+ 3065              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3066              		.loc 1 1659 1 is_stmt 0 view .LVU943
+ 3067 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 3068              	.LCFI32:
+ 3069              		.cfi_def_cfa_offset 20
+ 3070              		.cfi_offset 4, -20
+ 3071              		.cfi_offset 5, -16
+ 3072              		.cfi_offset 6, -12
+ 3073              		.cfi_offset 7, -8
+ 3074              		.cfi_offset 14, -4
+ 3075 0002 83B0     		sub	sp, sp, #12
+ 3076              	.LCFI33:
+ 3077              		.cfi_def_cfa_offset 32
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 3078              		.loc 1 1660 3 is_stmt 1 view .LVU944
+ 3079              	.LVL270:
+1661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmpOffsetShifted;
+ 3080              		.loc 1 1661 3 view .LVU945
+1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_config_internal_channel;
+ 3081              		.loc 1 1662 3 view .LVU946
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+ 3082              		.loc 1 1663 3 view .LVU947
+1664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_adc_is_conversion_on_going_injected;
+ 3083              		.loc 1 1664 3 view .LVU948
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __IO uint32_t wait_loop_index = 0;
+ 3084              		.loc 1 1665 3 view .LVU949
+ 3085              		.loc 1 1665 17 is_stmt 0 view .LVU950
+ 3086 0004 0023     		movs	r3, #0
+ 3087 0006 0193     		str	r3, [sp, #4]
+1666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
+ARM GAS  /tmp/cc3JIfda.s 			page 214
+
+
+ 3088              		.loc 1 1667 3 is_stmt 1 view .LVU951
+ 3089              	.LVL271:
+1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+1670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 3090              		.loc 1 1670 3 view .LVU952
+1671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+ 3091              		.loc 1 1671 3 view .LVU953
+1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
+ 3092              		.loc 1 1672 3 view .LVU954
+1673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+ 3093              		.loc 1 1673 3 view .LVU955
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
+ 3094              		.loc 1 1674 3 view .LVU956
+1675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+ 3095              		.loc 1 1675 3 view .LVU957
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv));
+ 3096              		.loc 1 1676 3 view .LVU958
+1677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
+ 3097              		.loc 1 1677 3 view .LVU959
+1678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
+ 3098              		.loc 1 1678 3 view .LVU960
+1679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_OFFSET_SIGN(sConfigInjected->InjectedOffsetSign));
+ 3099              		.loc 1 1679 3 view .LVU961
+1680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedOffsetSaturation));
+ 3100              		.loc 1 1680 3 view .LVU962
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
+ 3101              		.loc 1 1681 3 view .LVU963
+1682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ 3102              		.loc 1 1683 3 view .LVU964
+ 3103              		.loc 1 1683 17 is_stmt 0 view .LVU965
+ 3104 0008 4269     		ldr	r2, [r0, #20]
+1684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+ 3105              		.loc 1 1685 5 is_stmt 1 view .LVU966
+1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
+ 3106              		.loc 1 1686 5 view .LVU967
+1687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+ 3107              		.loc 1 1687 5 view .LVU968
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+1692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****      ignored (considered as reset) */
+1693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->In
+ 3108              		.loc 1 1693 3 view .LVU969
+1694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* JDISCEN and JAUTO bits can't be set at the same time  */
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->Au
+ 3109              		.loc 1 1696 3 view .LVU970
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*  DISCEN and JAUTO bits can't be set at the same time */
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv
+ 3110              		.loc 1 1699 3 view .LVU971
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Verification of channel number */
+ARM GAS  /tmp/cc3JIfda.s 			page 215
+
+
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
+ 3111              		.loc 1 1702 3 view .LVU972
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+1706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
+ 3112              		.loc 1 1708 5 view .LVU973
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process locked */
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 3113              		.loc 1 1712 3 view .LVU974
+ 3114              		.loc 1 1712 3 view .LVU975
+ 3115 000a 90F85830 		ldrb	r3, [r0, #88]	@ zero_extendqisi2
+ 3116 000e 012B     		cmp	r3, #1
+ 3117 0010 00F0CC82 		beq	.L306
+ 3118 0014 0446     		mov	r4, r0
+ 3119 0016 0D46     		mov	r5, r1
+ 3120              		.loc 1 1712 3 discriminator 2 view .LVU976
+ 3121 0018 0123     		movs	r3, #1
+ 3122 001a 80F85830 		strb	r3, [r0, #88]
+ 3123              		.loc 1 1712 3 discriminator 2 view .LVU977
+1713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Configuration of injected group sequencer:                               */
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Hardware constraint: Must fully define injected context register JSQR    */
+1716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* before make it entering into injected sequencer queue.                   */
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*                                                                          */
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* - if scan mode is disabled:                                              */
+1719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*    * Injected channels sequence length is set to 0x00: 1 channel         */
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*      converted (channel on injected rank 1)                              */
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*    * Injected context register JSQR setting is simple: register is fully */
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*      defined on one call of this function (for injected rank 1) and can  */
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*      be entered into queue directly.                                     */
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* - if scan mode is enabled:                                               */
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*    * Injected channels sequence length is set to parameter               */
+1727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*      "InjectedNbrOfConversion".                                          */
+1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*    * Injected context register JSQR setting more complex: register is    */
+1729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*      fully defined over successive calls of this function, for each      */
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*      injected channel rank. It is entered into queue only when all       */
+1731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*      injected ranks have been set.                                       */
+1732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*   Note: Scan mode is not present by hardware on this device, but used    */
+1733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*   by software for alignment over all STM32 devices.                      */
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
+ 3124              		.loc 1 1735 3 discriminator 2 view .LVU978
+ 3125              		.loc 1 1735 6 is_stmt 0 discriminator 2 view .LVU979
+ 3126 001e AAB1     		cbz	r2, .L236
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (sConfigInjected->InjectedNbrOfConversion == 1U))
+ 3127              		.loc 1 1736 23 discriminator 1 view .LVU980
+ 3128 0020 0B6A     		ldr	r3, [r1, #32]
+1735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       (sConfigInjected->InjectedNbrOfConversion == 1U))
+ 3129              		.loc 1 1735 54 discriminator 1 view .LVU981
+ 3130 0022 012B     		cmp	r3, #1
+ 3131 0024 12D0     		beq	.L236
+ARM GAS  /tmp/cc3JIfda.s 			page 216
+
+
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Configuration of context register JSQR:                                */
+1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
+1740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /*    (scan mode disabled, only rank 1 used)                              */
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /*  - external trigger to start conversion                                */
+1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /*  - external trigger polarity                                           */
+1743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /*  - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
+1744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Enable external trigger if trigger selection is different of         */
+1748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* software start.                                                      */
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Note: This configuration keeps the hardware feature of parameter     */
+1750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
+1751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*       software start.                                                */
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECT
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                            | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEX
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                            | sConfigInjected->ExternalTrigInjecConvEdge
+1757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                           );
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       else
+1760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECT
+1762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
+1765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* For debug and informative reasons, hadc handle saves JSQR setting */
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+1770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+1771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Case of scan mode enabled, several channels to set into injected group */
+1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* sequencer.                                                             */
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /*                                                                        */
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Procedure to define injected context register JSQR over successive     */
+1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* calls of this function, for each injected channel rank:                */
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* 1. Start new context and set parameters related to all injected        */
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /*    channels: injected sequence length and trigger.                     */
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /*   call of the context under setting                                    */
+1782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (hadc->InjectionConfig.ChannelCount == 0U)
+ 3132              		.loc 1 1782 5 is_stmt 1 view .LVU982
+ 3133              		.loc 1 1782 30 is_stmt 0 view .LVU983
+ 3134 0026 826E     		ldr	r2, [r0, #104]
+ 3135              		.loc 1 1782 8 view .LVU984
+ 3136 0028 002A     		cmp	r2, #0
+ 3137 002a 40F0B980 		bne	.L307
+1783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Initialize number of channels that will be configured on the context */
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*  being built                                                         */
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
+ 3138              		.loc 1 1786 7 is_stmt 1 view .LVU985
+ARM GAS  /tmp/cc3JIfda.s 			page 217
+
+
+ 3139              		.loc 1 1786 42 is_stmt 0 view .LVU986
+ 3140 002e 8366     		str	r3, [r0, #104]
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****          call, this context will be written in JSQR register at the last call.
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****          At this point, the context is merely reset  */
+1790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       hadc->InjectionConfig.ContextQueue = 0x00000000U;
+ 3141              		.loc 1 1790 7 is_stmt 1 view .LVU987
+ 3142              		.loc 1 1790 42 is_stmt 0 view .LVU988
+ 3143 0030 0023     		movs	r3, #0
+ 3144 0032 4366     		str	r3, [r0, #100]
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Configuration of context register JSQR:                              */
+1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*  - number of ranks in injected group sequencer                       */
+1794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*  - external trigger to start conversion                              */
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*  - external trigger polarity                                         */
+1796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Enable external trigger if trigger selection is different of         */
+1798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* software start.                                                      */
+1799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Note: This configuration keeps the hardware feature of parameter     */
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
+1801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*       software start.                                                */
+1802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ 3145              		.loc 1 1802 7 is_stmt 1 view .LVU989
+ 3146              		.loc 1 1802 26 is_stmt 0 view .LVU990
+ 3147 0034 8B6A     		ldr	r3, [r1, #40]
+ 3148              		.loc 1 1802 10 view .LVU991
+ 3149 0036 002B     		cmp	r3, #0
+ 3150 0038 00F0AF80 		beq	.L242
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)
+ 3151              		.loc 1 1804 9 is_stmt 1 view .LVU992
+ 3152              		.loc 1 1804 60 is_stmt 0 view .LVU993
+ 3153 003c 0A6A     		ldr	r2, [r1, #32]
+ 3154              		.loc 1 1804 86 view .LVU994
+ 3155 003e 013A     		subs	r2, r2, #1
+1805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                            | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEX
+ 3156              		.loc 1 1805 86 view .LVU995
+ 3157 0040 03F07C03 		and	r3, r3, #124
+ 3158              		.loc 1 1805 44 view .LVU996
+ 3159 0044 1A43     		orrs	r2, r2, r3
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                            | sConfigInjected->ExternalTrigInjecConvEdge
+ 3160              		.loc 1 1806 61 view .LVU997
+ 3161 0046 CB6A     		ldr	r3, [r1, #44]
+1804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                            | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEX
+ 3162              		.loc 1 1804 41 view .LVU998
+ 3163 0048 1A43     		orrs	r2, r2, r3
+ 3164              	.LVL272:
+1804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                            | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEX
+ 3165              		.loc 1 1804 41 view .LVU999
+ 3166 004a AAE0     		b	.L241
+ 3167              	.LVL273:
+ 3168              	.L236:
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 3169              		.loc 1 1745 5 is_stmt 1 view .LVU1000
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 3170              		.loc 1 1745 24 is_stmt 0 view .LVU1001
+ 3171 004c 6B68     		ldr	r3, [r5, #4]
+ARM GAS  /tmp/cc3JIfda.s 			page 218
+
+
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 3172              		.loc 1 1745 8 view .LVU1002
+ 3173 004e 092B     		cmp	r3, #9
+ 3174 0050 00F08380 		beq	.L322
+ 3175              	.LVL274:
+ 3176              	.L238:
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                           );
+1808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       else
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U));
+1812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* 2. Continue setting of context under definition with parameter       */
+1817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /*    related to each channel: channel rank sequence                    */
+1818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Clear the old JSQx bits for the selected rank */
+1819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
+1820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Set the JSQx bits for the selected rank */
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjecte
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Decrease channel count  */
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     hadc->InjectionConfig.ChannelCount--;
+1826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
+1828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           call, aggregate the setting to those already built during the previous
+1829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course)  */
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
+1831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* 4. End of context setting: if this is the last channel set, then write context
+1833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         into register JSQR and make it enter into queue                   */
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (hadc->InjectionConfig.ChannelCount == 0U)
+1835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Parameters update conditioned to ADC state:                              */
+1841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Parameters that can be updated when ADC is disabled or enabled without   */
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* conversion on going on injected group:                                   */
+1843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*  - Injected context queue: Queue disable (active context is kept) or     */
+1844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*    enable (context decremented, up to 2 contexts queued)                 */
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
+1846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*    mode is disabled.                                                     */
+1847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ 3177              		.loc 1 1847 3 is_stmt 1 view .LVU1003
+ 3178              		.loc 1 1847 7 is_stmt 0 view .LVU1004
+ 3179 0054 2368     		ldr	r3, [r4]
+ 3180              	.LVL275:
+ 3181              	.LBB364:
+ 3182              	.LBI364:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3183              		.loc 2 7076 26 is_stmt 1 view .LVU1005
+ 3184              	.LBB365:
+ 3185              		.loc 2 7078 3 view .LVU1006
+ARM GAS  /tmp/cc3JIfda.s 			page 219
+
+
+ 3186              		.loc 2 7078 12 is_stmt 0 view .LVU1007
+ 3187 0056 9A68     		ldr	r2, [r3, #8]
+ 3188              		.loc 2 7078 76 view .LVU1008
+ 3189 0058 12F0080F 		tst	r2, #8
+ 3190 005c 10D1     		bne	.L243
+ 3191              	.LVL276:
+ 3192              		.loc 2 7078 76 view .LVU1009
+ 3193              	.LBE365:
+ 3194              	.LBE364:
+1848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* If auto-injected mode is disabled: no constraint                       */
+1850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (sConfigInjected->AutoInjectedConv == DISABLE)
+ 3195              		.loc 1 1850 5 is_stmt 1 view .LVU1010
+ 3196              		.loc 1 1850 24 is_stmt 0 view .LVU1011
+ 3197 005e 95F82520 		ldrb	r2, [r5, #37]	@ zero_extendqisi2
+ 3198              		.loc 1 1850 8 view .LVU1012
+ 3199 0062 002A     		cmp	r2, #0
+ 3200 0064 40F0BB80 		bne	.L244
+1851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       MODIFY_REG(hadc->Instance->CFGR,
+ 3201              		.loc 1 1852 7 is_stmt 1 view .LVU1013
+ 3202 0068 DA68     		ldr	r2, [r3, #12]
+ 3203 006a 22F44012 		bic	r2, r2, #3145728
+ 3204 006e 95F82600 		ldrb	r0, [r5, #38]	@ zero_extendqisi2
+ 3205              	.LVL277:
+ 3206              		.loc 1 1852 7 is_stmt 0 view .LVU1014
+ 3207 0072 95F82410 		ldrb	r1, [r5, #36]	@ zero_extendqisi2
+ 3208 0076 0905     		lsls	r1, r1, #20
+ 3209 0078 41EA4051 		orr	r1, r1, r0, lsl #21
+ 3210 007c 0A43     		orrs	r2, r2, r1
+ 3211 007e DA60     		str	r2, [r3, #12]
+ 3212              	.L243:
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
+1854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext)    
+1855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousCon
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* If auto-injected mode is enabled: Injected discontinuous setting is    */
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* discarded.                                                             */
+1859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       MODIFY_REG(hadc->Instance->CFGR,
+1862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
+1863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext));
+1864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+1867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Parameters update conditioned to ADC state:                              */
+1869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Parameters that can be updated when ADC is disabled or enabled without   */
+1870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* conversion on going on regular and injected groups:                      */
+1871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*  - Automatic injected conversion: can be enabled if injected group       */
+1872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*    external triggers are disabled.                                       */
+1873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*  - Channel sampling time                                                 */
+1874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*  - Channel offset                                                        */
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ 3213              		.loc 1 1875 3 is_stmt 1 view .LVU1015
+ 3214              		.loc 1 1875 44 is_stmt 0 view .LVU1016
+ARM GAS  /tmp/cc3JIfda.s 			page 220
+
+
+ 3215 0080 2268     		ldr	r2, [r4]
+ 3216              	.LVL278:
+ 3217              	.LBB366:
+ 3218              	.LBI366:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3219              		.loc 2 6851 26 is_stmt 1 view .LVU1017
+ 3220              	.LBB367:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3221              		.loc 2 6853 3 view .LVU1018
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3222              		.loc 2 6853 12 is_stmt 0 view .LVU1019
+ 3223 0082 9368     		ldr	r3, [r2, #8]
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3224              		.loc 2 6853 74 view .LVU1020
+ 3225 0084 13F00403 		ands	r3, r3, #4
+ 3226 0088 00D0     		beq	.L245
+ 3227 008a 0123     		movs	r3, #1
+ 3228              	.L245:
+ 3229              	.LVL279:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3230              		.loc 2 6853 74 view .LVU1021
+ 3231              	.LBE367:
+ 3232              	.LBE366:
+1876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 3233              		.loc 1 1876 3 is_stmt 1 view .LVU1022
+ 3234              	.LBB368:
+ 3235              	.LBI368:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3236              		.loc 2 7076 26 view .LVU1023
+ 3237              	.LBB369:
+ 3238              		.loc 2 7078 3 view .LVU1024
+ 3239              		.loc 2 7078 12 is_stmt 0 view .LVU1025
+ 3240 008c 9668     		ldr	r6, [r2, #8]
+ 3241              		.loc 2 7078 76 view .LVU1026
+ 3242 008e 16F00806 		ands	r6, r6, #8
+ 3243 0092 00D0     		beq	.L246
+ 3244 0094 0126     		movs	r6, #1
+ 3245              	.L246:
+ 3246              	.LVL280:
+ 3247              		.loc 2 7078 76 view .LVU1027
+ 3248              	.LBE369:
+ 3249              	.LBE368:
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ 3250              		.loc 1 1878 3 is_stmt 1 view .LVU1028
+ 3251              		.loc 1 1878 6 is_stmt 0 view .LVU1029
+ 3252 0096 002B     		cmp	r3, #0
+ 3253 0098 40F04081 		bne	.L308
+1879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 3254              		.loc 1 1879 7 view .LVU1030
+ 3255 009c 002E     		cmp	r6, #0
+ 3256 009e 40F07281 		bne	.L309
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****      )
+1881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+1882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* If injected group external triggers are disabled (set to injected      */
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* software start): no constraint                                         */
+1884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+ARM GAS  /tmp/cc3JIfda.s 			page 221
+
+
+ 3257              		.loc 1 1884 5 is_stmt 1 view .LVU1031
+ 3258              		.loc 1 1884 25 is_stmt 0 view .LVU1032
+ 3259 00a2 AB6A     		ldr	r3, [r5, #40]
+ 3260              	.LVL281:
+ 3261              		.loc 1 1884 8 view .LVU1033
+ 3262 00a4 1BB1     		cbz	r3, .L248
+1885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
+ 3263              		.loc 1 1885 28 view .LVU1034
+ 3264 00a6 EB6A     		ldr	r3, [r5, #44]
+ 3265              		.loc 1 1885 9 view .LVU1035
+ 3266 00a8 002B     		cmp	r3, #0
+ 3267 00aa 40F0A780 		bne	.L249
+ 3268              	.L248:
+1886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (sConfigInjected->AutoInjectedConv == ENABLE)
+ 3269              		.loc 1 1887 7 is_stmt 1 view .LVU1036
+ 3270              		.loc 1 1887 26 is_stmt 0 view .LVU1037
+ 3271 00ae 95F82530 		ldrb	r3, [r5, #37]	@ zero_extendqisi2
+ 3272              		.loc 1 1887 10 view .LVU1038
+ 3273 00b2 012B     		cmp	r3, #1
+ 3274 00b4 00F09C80 		beq	.L323
+1888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+1890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       else
+1892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+ 3275              		.loc 1 1893 9 is_stmt 1 view .LVU1039
+ 3276 00b8 D368     		ldr	r3, [r2, #12]
+ 3277 00ba 23F00073 		bic	r3, r3, #33554432
+ 3278 00be D360     		str	r3, [r2, #12]
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmpOffsetShifted;
+ 3279              		.loc 1 1660 21 is_stmt 0 view .LVU1040
+ 3280 00c0 0027     		movs	r7, #0
+ 3281              	.LVL282:
+ 3282              	.L251:
+1894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* If Automatic injected conversion was intended to be set and could not  */
+1897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* due to injected group external triggers enabled, error is reported.    */
+1898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+1899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (sConfigInjected->AutoInjectedConv == ENABLE)
+1901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Update ADC state machine to error */
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+1904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         tmp_hal_status = HAL_ERROR;
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       else
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+1910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (sConfigInjected->InjecOversamplingMode == ENABLE)
+ 3283              		.loc 1 1913 5 is_stmt 1 view .LVU1041
+ARM GAS  /tmp/cc3JIfda.s 			page 222
+
+
+ 3284              		.loc 1 1913 24 is_stmt 0 view .LVU1042
+ 3285 00c2 95F83030 		ldrb	r3, [r5, #48]	@ zero_extendqisi2
+ 3286              		.loc 1 1913 8 view .LVU1043
+ 3287 00c6 012B     		cmp	r3, #1
+ 3288 00c8 00F0A780 		beq	.L324
+1914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
+1916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
+1917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*  JOVSE must be reset in case of triggered regular mode  */
+1919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFG
+1920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Configuration of Injected Oversampler:                                 */
+1922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*  - Oversampling Ratio                                                  */
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*  - Right bit shift                                                     */
+1924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Enable OverSampling mode */
+1926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       MODIFY_REG(hadc->Instance->CFGR2,
+1927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  ADC_CFGR2_JOVSE |
+1928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  ADC_CFGR2_OVSR  |
+1929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  ADC_CFGR2_OVSS,
+1930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  ADC_CFGR2_JOVSE                                  |
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  sConfigInjected->InjecOversampling.Ratio         |
+1932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  sConfigInjected->InjecOversampling.RightBitShift
+1933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                 );
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+1936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Disable Regular OverSampling */
+1938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
+ 3289              		.loc 1 1938 7 is_stmt 1 view .LVU1044
+ 3290 00cc 2268     		ldr	r2, [r4]
+ 3291 00ce 1369     		ldr	r3, [r2, #16]
+ 3292 00d0 23F00203 		bic	r3, r3, #2
+ 3293 00d4 1361     		str	r3, [r2, #16]
+ 3294              	.L254:
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
+1942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
+ 3295              		.loc 1 1942 5 view .LVU1045
+ 3296              		.loc 1 1942 24 is_stmt 0 view .LVU1046
+ 3297 00d6 AA68     		ldr	r2, [r5, #8]
+ 3298              		.loc 1 1942 8 view .LVU1047
+ 3299 00d8 B2F1004F 		cmp	r2, #-2147483648
+ 3300 00dc 00F0A980 		beq	.L325
+1943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set sampling time of the selected ADC channel */
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLI
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set ADC sampling time common configuration */
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
+1949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set sampling time of the selected ADC channel */
+1953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInject
+ARM GAS  /tmp/cc3JIfda.s 			page 223
+
+
+ 3301              		.loc 1 1953 7 is_stmt 1 view .LVU1048
+ 3302 00e0 2968     		ldr	r1, [r5]
+ 3303 00e2 2068     		ldr	r0, [r4]
+ 3304 00e4 FFF7FEFF 		bl	LL_ADC_SetChannelSamplingTime
+ 3305              	.LVL283:
+1954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set ADC sampling time common configuration */
+1956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
+ 3306              		.loc 1 1956 7 view .LVU1049
+ 3307 00e8 2268     		ldr	r2, [r4]
+ 3308              	.LVL284:
+ 3309              	.LBB370:
+ 3310              	.LBI370:
+3560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3311              		.loc 2 3560 22 view .LVU1050
+ 3312              	.LBB371:
+3562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3313              		.loc 2 3562 3 view .LVU1051
+ 3314 00ea 5369     		ldr	r3, [r2, #20]
+ 3315 00ec 23F00043 		bic	r3, r3, #-2147483648
+ 3316 00f0 5361     		str	r3, [r2, #20]
+ 3317              	.LVL285:
+ 3318              	.L256:
+3562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3319              		.loc 2 3562 3 is_stmt 0 view .LVU1052
+ 3320              	.LBE371:
+ 3321              	.LBE370:
+1957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Configure the offset: offset enable/disable, channel, offset value */
+1960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Shift the offset with respect to the selected ADC resolution. */
+1962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+1963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
+ 3322              		.loc 1 1963 5 is_stmt 1 view .LVU1053
+ 3323              		.loc 1 1963 24 is_stmt 0 view .LVU1054
+ 3324 00f2 6A69     		ldr	r2, [r5, #20]
+ 3325 00f4 2168     		ldr	r1, [r4]
+ 3326 00f6 CB68     		ldr	r3, [r1, #12]
+ 3327 00f8 C3F3C103 		ubfx	r3, r3, #3, #2
+ 3328 00fc 5B00     		lsls	r3, r3, #1
+ 3329              		.loc 1 1963 22 view .LVU1055
+ 3330 00fe 9A40     		lsls	r2, r2, r3
+ 3331              	.LVL286:
+1964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
+ 3332              		.loc 1 1965 5 is_stmt 1 view .LVU1056
+ 3333              		.loc 1 1965 24 is_stmt 0 view .LVU1057
+ 3334 0100 D5F810C0 		ldr	ip, [r5, #16]
+ 3335              		.loc 1 1965 8 view .LVU1058
+ 3336 0104 BCF1040F 		cmp	ip, #4
+ 3337 0108 00F0A180 		beq	.L257
+1966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set ADC selected offset number */
+1968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->Inje
+ 3338              		.loc 1 1968 7 is_stmt 1 view .LVU1059
+ 3339              	.LVL287:
+ARM GAS  /tmp/cc3JIfda.s 			page 224
+
+
+ 3340              	.LBB372:
+ 3341              	.LBI372:
+3220:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3342              		.loc 2 3220 22 view .LVU1060
+ 3343              	.LBB373:
+3222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3344              		.loc 2 3222 3 view .LVU1061
+3222:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3345              		.loc 2 3222 25 is_stmt 0 view .LVU1062
+ 3346 010c 6031     		adds	r1, r1, #96
+ 3347              	.LVL288:
+3224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ 3348              		.loc 2 3224 3 is_stmt 1 view .LVU1063
+ 3349 010e 51F82C00 		ldr	r0, [r1, ip, lsl #2]
+ 3350 0112 A24B     		ldr	r3, .L335
+ 3351 0114 0340     		ands	r3, r3, r0
+ 3352 0116 2868     		ldr	r0, [r5]
+ 3353 0118 00F0F840 		and	r0, r0, #2080374784
+ 3354 011c 0243     		orrs	r2, r2, r0
+ 3355              	.LVL289:
+3224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ 3356              		.loc 2 3224 3 is_stmt 0 view .LVU1064
+ 3357 011e 1343     		orrs	r3, r3, r2
+ 3358 0120 43F00043 		orr	r3, r3, #-2147483648
+ 3359 0124 41F82C30 		str	r3, [r1, ip, lsl #2]
+ 3360              	.LVL290:
+3224:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ 3361              		.loc 2 3224 3 view .LVU1065
+ 3362              	.LBE373:
+ 3363              	.LBE372:
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                        tmpOffsetShifted);
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+1971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set ADC selected offset sign & saturation */
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       LL_ADC_SetOffsetSign(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->
+ 3364              		.loc 1 1972 7 is_stmt 1 view .LVU1066
+ 3365 0128 2368     		ldr	r3, [r4]
+ 3366 012a 2869     		ldr	r0, [r5, #16]
+ 3367 012c AA69     		ldr	r2, [r5, #24]
+ 3368              	.LVL291:
+ 3369              	.LBB374:
+ 3370              	.LBI374:
+3417:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3371              		.loc 2 3417 22 view .LVU1067
+ 3372              	.LBB375:
+3419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3373              		.loc 2 3419 3 view .LVU1068
+3419:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3374              		.loc 2 3419 25 is_stmt 0 view .LVU1069
+ 3375 012e 6033     		adds	r3, r3, #96
+ 3376              	.LVL292:
+3421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSETPOS,
+ 3377              		.loc 2 3421 3 is_stmt 1 view .LVU1070
+ 3378 0130 53F82010 		ldr	r1, [r3, r0, lsl #2]
+ 3379 0134 21F08071 		bic	r1, r1, #16777216
+ 3380 0138 0A43     		orrs	r2, r2, r1
+ 3381              	.LVL293:
+3421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSETPOS,
+ARM GAS  /tmp/cc3JIfda.s 			page 225
+
+
+ 3382              		.loc 2 3421 3 is_stmt 0 view .LVU1071
+ 3383 013a 43F82020 		str	r2, [r3, r0, lsl #2]
+ 3384              	.LVL294:
+3421:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSETPOS,
+ 3385              		.loc 2 3421 3 view .LVU1072
+ 3386              	.LBE375:
+ 3387              	.LBE374:
+1973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       LL_ADC_SetOffsetSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber,
+ 3388              		.loc 1 1973 7 is_stmt 1 view .LVU1073
+ 3389 013e 2368     		ldr	r3, [r4]
+ 3390 0140 2869     		ldr	r0, [r5, #16]
+1974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                  (sConfigInjected->InjectedOffsetSaturation == ENABLE) ? LL_ADC_OFF
+ 3391              		.loc 1 1974 50 is_stmt 0 view .LVU1074
+ 3392 0142 2A7F     		ldrb	r2, [r5, #28]	@ zero_extendqisi2
+1973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       LL_ADC_SetOffsetSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber,
+ 3393              		.loc 1 1973 7 view .LVU1075
+ 3394 0144 012A     		cmp	r2, #1
+ 3395 0146 7FD0     		beq	.L326
+ 3396              	.LVL295:
+ 3397              	.L258:
+ 3398              	.LBB376:
+ 3399              	.LBI376:
+3472:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3400              		.loc 2 3472 22 is_stmt 1 discriminator 4 view .LVU1076
+ 3401              	.LBB377:
+3474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3402              		.loc 2 3474 3 discriminator 4 view .LVU1077
+3474:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3403              		.loc 2 3474 25 is_stmt 0 discriminator 4 view .LVU1078
+ 3404 0148 6033     		adds	r3, r3, #96
+ 3405              	.LVL296:
+3476:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_SATEN,
+ 3406              		.loc 2 3476 3 is_stmt 1 discriminator 4 view .LVU1079
+ 3407 014a 53F82020 		ldr	r2, [r3, r0, lsl #2]
+ 3408 014e 22F00072 		bic	r2, r2, #33554432
+ 3409 0152 3243     		orrs	r2, r2, r6
+ 3410 0154 43F82020 		str	r2, [r3, r0, lsl #2]
+ 3411              	.LVL297:
+3479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3412              		.loc 2 3479 1 is_stmt 0 discriminator 4 view .LVU1080
+ 3413 0158 E1E0     		b	.L247
+ 3414              	.LVL298:
+ 3415              	.L322:
+3479:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3416              		.loc 2 3479 1 discriminator 4 view .LVU1081
+ 3417              	.LBE377:
+ 3418              	.LBE376:
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 3419              		.loc 1 1752 7 is_stmt 1 view .LVU1082
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 3420              		.loc 1 1752 26 is_stmt 0 view .LVU1083
+ 3421 015a AA6A     		ldr	r2, [r5, #40]
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 3422              		.loc 1 1752 10 view .LVU1084
+ 3423 015c BAB1     		cbz	r2, .L239
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                            | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEX
+ 3424              		.loc 1 1754 9 is_stmt 1 view .LVU1085
+ARM GAS  /tmp/cc3JIfda.s 			page 226
+
+
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                            | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEX
+ 3425              		.loc 1 1754 44 is_stmt 0 view .LVU1086
+ 3426 015e 2B68     		ldr	r3, [r5]
+ 3427 0160 9B0E     		lsrs	r3, r3, #26
+ 3428 0162 5B02     		lsls	r3, r3, #9
+ 3429 0164 03F47853 		and	r3, r3, #15872
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                            | sConfigInjected->ExternalTrigInjecConvEdge
+ 3430              		.loc 1 1755 86 view .LVU1087
+ 3431 0168 02F07C02 		and	r2, r2, #124
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                            | sConfigInjected->ExternalTrigInjecConvEdge
+ 3432              		.loc 1 1755 44 view .LVU1088
+ 3433 016c 1343     		orrs	r3, r3, r2
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                           );
+ 3434              		.loc 1 1756 61 view .LVU1089
+ 3435 016e EA6A     		ldr	r2, [r5, #44]
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                            | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEX
+ 3436              		.loc 1 1754 41 view .LVU1090
+ 3437 0170 1343     		orrs	r3, r3, r2
+ 3438              	.LVL299:
+ 3439              	.L240:
+1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* For debug and informative reasons, hadc handle saves JSQR setting */
+ 3440              		.loc 1 1764 7 is_stmt 1 view .LVU1091
+ 3441 0172 2168     		ldr	r1, [r4]
+ 3442              	.LVL300:
+1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* For debug and informative reasons, hadc handle saves JSQR setting */
+ 3443              		.loc 1 1764 7 is_stmt 0 view .LVU1092
+ 3444 0174 CA6C     		ldr	r2, [r1, #76]
+ 3445 0176 22F07B42 		bic	r2, r2, #-83886080
+ 3446 017a 22F46F02 		bic	r2, r2, #15663104
+ 3447 017e 22F43F42 		bic	r2, r2, #48896
+ 3448 0182 22F0FF02 		bic	r2, r2, #255
+ 3449 0186 1A43     		orrs	r2, r2, r3
+ 3450 0188 CA64     		str	r2, [r1, #76]
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3451              		.loc 1 1766 7 is_stmt 1 view .LVU1093
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3452              		.loc 1 1766 42 is_stmt 0 view .LVU1094
+ 3453 018a 6366     		str	r3, [r4, #100]
+ 3454 018c 62E7     		b	.L238
+ 3455              	.LVL301:
+ 3456              	.L239:
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3457              		.loc 1 1761 9 is_stmt 1 view .LVU1095
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3458              		.loc 1 1761 44 is_stmt 0 view .LVU1096
+ 3459 018e 2B68     		ldr	r3, [r5]
+ 3460 0190 9B0E     		lsrs	r3, r3, #26
+ 3461 0192 5B02     		lsls	r3, r3, #9
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3462              		.loc 1 1761 41 view .LVU1097
+ 3463 0194 03F47853 		and	r3, r3, #15872
+ 3464              	.LVL302:
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3465              		.loc 1 1761 41 view .LVU1098
+ 3466 0198 EBE7     		b	.L240
+ 3467              	.LVL303:
+ 3468              	.L242:
+ARM GAS  /tmp/cc3JIfda.s 			page 227
+
+
+1811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3469              		.loc 1 1811 9 is_stmt 1 view .LVU1099
+1811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3470              		.loc 1 1811 60 is_stmt 0 view .LVU1100
+ 3471 019a 0A6A     		ldr	r2, [r1, #32]
+1811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3472              		.loc 1 1811 41 view .LVU1101
+ 3473 019c 013A     		subs	r2, r2, #1
+ 3474              	.LVL304:
+1811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3475              		.loc 1 1811 41 view .LVU1102
+ 3476 019e 00E0     		b	.L241
+ 3477              	.LVL305:
+ 3478              	.L307:
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3479              		.loc 1 1667 12 view .LVU1103
+ 3480 01a0 0022     		movs	r2, #0
+ 3481              	.LVL306:
+ 3482              	.L241:
+1819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3483              		.loc 1 1819 5 is_stmt 1 view .LVU1104
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3484              		.loc 1 1822 5 view .LVU1105
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3485              		.loc 1 1822 40 is_stmt 0 view .LVU1106
+ 3486 01a2 2B68     		ldr	r3, [r5]
+ 3487 01a4 C3F38463 		ubfx	r3, r3, #26, #5
+ 3488 01a8 6968     		ldr	r1, [r5, #4]
+ 3489              	.LVL307:
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3490              		.loc 1 1822 40 view .LVU1107
+ 3491 01aa 01F01F01 		and	r1, r1, #31
+ 3492 01ae 8B40     		lsls	r3, r3, r1
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3493              		.loc 1 1822 37 view .LVU1108
+ 3494 01b0 1343     		orrs	r3, r3, r2
+ 3495              	.LVL308:
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3496              		.loc 1 1825 5 is_stmt 1 view .LVU1109
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3497              		.loc 1 1825 26 is_stmt 0 view .LVU1110
+ 3498 01b2 A16E     		ldr	r1, [r4, #104]
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3499              		.loc 1 1825 39 view .LVU1111
+ 3500 01b4 0139     		subs	r1, r1, #1
+ 3501 01b6 A166     		str	r1, [r4, #104]
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3502              		.loc 1 1830 5 is_stmt 1 view .LVU1112
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3503              		.loc 1 1830 26 is_stmt 0 view .LVU1113
+ 3504 01b8 626E     		ldr	r2, [r4, #100]
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3505              		.loc 1 1830 40 view .LVU1114
+ 3506 01ba 1343     		orrs	r3, r3, r2
+ 3507              	.LVL309:
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3508              		.loc 1 1830 40 view .LVU1115
+ARM GAS  /tmp/cc3JIfda.s 			page 228
+
+
+ 3509 01bc 6366     		str	r3, [r4, #100]
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 3510              		.loc 1 1834 5 is_stmt 1 view .LVU1116
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 3511              		.loc 1 1834 8 is_stmt 0 view .LVU1117
+ 3512 01be 0029     		cmp	r1, #0
+ 3513 01c0 7FF448AF 		bne	.L238
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 3514              		.loc 1 1836 7 is_stmt 1 view .LVU1118
+ 3515 01c4 2168     		ldr	r1, [r4]
+ 3516 01c6 CA6C     		ldr	r2, [r1, #76]
+ 3517 01c8 22F07B42 		bic	r2, r2, #-83886080
+ 3518 01cc 22F46F02 		bic	r2, r2, #15663104
+ 3519 01d0 22F43F42 		bic	r2, r2, #48896
+ 3520 01d4 22F0FF02 		bic	r2, r2, #255
+ 3521 01d8 1343     		orrs	r3, r3, r2
+ 3522 01da CB64     		str	r3, [r1, #76]
+ 3523 01dc 3AE7     		b	.L238
+ 3524              	.LVL310:
+ 3525              	.L244:
+1861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
+ 3526              		.loc 1 1861 7 view .LVU1119
+ 3527 01de DA68     		ldr	r2, [r3, #12]
+ 3528 01e0 22F44012 		bic	r2, r2, #3145728
+ 3529 01e4 95F82610 		ldrb	r1, [r5, #38]	@ zero_extendqisi2
+ 3530 01e8 42EA4152 		orr	r2, r2, r1, lsl #21
+ 3531 01ec DA60     		str	r2, [r3, #12]
+ 3532 01ee 47E7     		b	.L243
+ 3533              	.LVL311:
+ 3534              	.L323:
+1889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3535              		.loc 1 1889 9 view .LVU1120
+ 3536 01f0 D368     		ldr	r3, [r2, #12]
+ 3537 01f2 43F00073 		orr	r3, r3, #33554432
+ 3538 01f6 D360     		str	r3, [r2, #12]
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmpOffsetShifted;
+ 3539              		.loc 1 1660 21 is_stmt 0 view .LVU1121
+ 3540 01f8 0027     		movs	r7, #0
+ 3541 01fa 62E7     		b	.L251
+ 3542              	.L249:
+1900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 3543              		.loc 1 1900 7 is_stmt 1 view .LVU1122
+1900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 3544              		.loc 1 1900 26 is_stmt 0 view .LVU1123
+ 3545 01fc 95F82570 		ldrb	r7, [r5, #37]	@ zero_extendqisi2
+1900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 3546              		.loc 1 1900 10 view .LVU1124
+ 3547 0200 012F     		cmp	r7, #1
+ 3548 0202 05D0     		beq	.L327
+1909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3549              		.loc 1 1909 9 is_stmt 1 view .LVU1125
+ 3550 0204 D368     		ldr	r3, [r2, #12]
+ 3551 0206 23F00073 		bic	r3, r3, #33554432
+ 3552 020a D360     		str	r3, [r2, #12]
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmpOffsetShifted;
+ 3553              		.loc 1 1660 21 is_stmt 0 view .LVU1126
+ 3554 020c 0027     		movs	r7, #0
+ARM GAS  /tmp/cc3JIfda.s 			page 229
+
+
+ 3555 020e 58E7     		b	.L251
+ 3556              	.L327:
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3557              		.loc 1 1903 9 is_stmt 1 view .LVU1127
+ 3558 0210 E36D     		ldr	r3, [r4, #92]
+ 3559 0212 43F02003 		orr	r3, r3, #32
+ 3560 0216 E365     		str	r3, [r4, #92]
+1905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3561              		.loc 1 1905 9 view .LVU1128
+ 3562              	.LVL312:
+1905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3563              		.loc 1 1905 9 is_stmt 0 view .LVU1129
+ 3564 0218 53E7     		b	.L251
+ 3565              	.LVL313:
+ 3566              	.L324:
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
+ 3567              		.loc 1 1915 7 is_stmt 1 view .LVU1130
+1916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3568              		.loc 1 1916 7 view .LVU1131
+1919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3569              		.loc 1 1919 7 view .LVU1132
+1926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  ADC_CFGR2_JOVSE |
+ 3570              		.loc 1 1926 7 view .LVU1133
+ 3571 021a 2168     		ldr	r1, [r4]
+ 3572 021c 0B69     		ldr	r3, [r1, #16]
+ 3573 021e 23F4FF73 		bic	r3, r3, #510
+ 3574 0222 6A6B     		ldr	r2, [r5, #52]
+ 3575 0224 A86B     		ldr	r0, [r5, #56]
+ 3576 0226 0243     		orrs	r2, r2, r0
+ 3577 0228 1343     		orrs	r3, r3, r2
+ 3578 022a 43F00203 		orr	r3, r3, #2
+ 3579 022e 0B61     		str	r3, [r1, #16]
+ 3580 0230 51E7     		b	.L254
+ 3581              	.L325:
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 3582              		.loc 1 1945 7 view .LVU1134
+ 3583 0232 0022     		movs	r2, #0
+ 3584 0234 2968     		ldr	r1, [r5]
+ 3585 0236 2068     		ldr	r0, [r4]
+ 3586 0238 FFF7FEFF 		bl	LL_ADC_SetChannelSamplingTime
+ 3587              	.LVL314:
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 3588              		.loc 1 1948 7 view .LVU1135
+ 3589 023c 2268     		ldr	r2, [r4]
+ 3590              	.LVL315:
+ 3591              	.LBB378:
+ 3592              	.LBI378:
+3560:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3593              		.loc 2 3560 22 view .LVU1136
+ 3594              	.LBB379:
+3562:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3595              		.loc 2 3562 3 view .LVU1137
+ 3596 023e 5369     		ldr	r3, [r2, #20]
+ 3597 0240 43F00043 		orr	r3, r3, #-2147483648
+ 3598 0244 5361     		str	r3, [r2, #20]
+3563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3599              		.loc 2 3563 1 is_stmt 0 view .LVU1138
+ARM GAS  /tmp/cc3JIfda.s 			page 230
+
+
+ 3600 0246 54E7     		b	.L256
+ 3601              	.LVL316:
+ 3602              	.L326:
+3563:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3603              		.loc 2 3563 1 view .LVU1139
+ 3604              	.LBE379:
+ 3605              	.LBE378:
+1973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                  (sConfigInjected->InjectedOffsetSaturation == ENABLE) ? LL_ADC_OFF
+ 3606              		.loc 1 1973 7 view .LVU1140
+ 3607 0248 4FF00076 		mov	r6, #33554432
+ 3608              	.LVL317:
+1973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                  (sConfigInjected->InjectedOffsetSaturation == ENABLE) ? LL_ADC_OFF
+ 3609              		.loc 1 1973 7 view .LVU1141
+ 3610 024c 7CE7     		b	.L258
+ 3611              	.LVL318:
+ 3612              	.L257:
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+1976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+1977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+1978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Scan each offset register to check if the selected channel is targeted. */
+1979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* If this is the case, the corresponding offset number is disabled.       */
+1980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+ 3613              		.loc 1 1980 7 is_stmt 1 view .LVU1142
+ 3614              	.LBB380:
+ 3615              	.LBI380:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3616              		.loc 2 3303 26 view .LVU1143
+ 3617              	.LBB381:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3618              		.loc 2 3305 3 view .LVU1144
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3619              		.loc 2 3307 3 view .LVU1145
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3620              		.loc 2 3307 10 is_stmt 0 view .LVU1146
+ 3621 024e 0B6E     		ldr	r3, [r1, #96]
+ 3622              	.LVL319:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3623              		.loc 2 3307 10 view .LVU1147
+ 3624              	.LBE381:
+ 3625              	.LBE380:
+ 3626              	.LBB382:
+ 3627              	.LBI382:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3628              		.loc 2 3303 26 is_stmt 1 view .LVU1148
+ 3629              	.LBB383:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3630              		.loc 2 3305 3 view .LVU1149
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3631              		.loc 2 3307 3 view .LVU1150
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3632              		.loc 2 3307 10 is_stmt 0 view .LVU1151
+ 3633 0250 0A6E     		ldr	r2, [r1, #96]
+ 3634              	.LVL320:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3635              		.loc 2 3307 10 view .LVU1152
+ 3636              	.LBE383:
+ 3637              	.LBE382:
+ARM GAS  /tmp/cc3JIfda.s 			page 231
+
+
+ 3638              		.loc 1 1980 11 view .LVU1153
+ 3639 0252 C2F38462 		ubfx	r2, r2, #26, #5
+1981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ 3640              		.loc 1 1981 14 view .LVU1154
+ 3641 0256 2B68     		ldr	r3, [r5]
+ 3642 0258 C3F31200 		ubfx	r0, r3, #0, #19
+ 3643 025c 78BB     		cbnz	r0, .L259
+ 3644              		.loc 1 1981 14 discriminator 1 view .LVU1155
+ 3645 025e C3F38463 		ubfx	r3, r3, #26, #5
+ 3646              	.L260:
+1980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ 3647              		.loc 1 1980 10 view .LVU1156
+ 3648 0262 9A42     		cmp	r2, r3
+ 3649 0264 33D0     		beq	.L328
+ 3650              	.L262:
+1982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
+1984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+ 3651              		.loc 1 1985 7 is_stmt 1 view .LVU1157
+ 3652              		.loc 1 1985 11 is_stmt 0 view .LVU1158
+ 3653 0266 2168     		ldr	r1, [r4]
+ 3654              	.LVL321:
+ 3655              	.LBB384:
+ 3656              	.LBI384:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3657              		.loc 2 3303 26 is_stmt 1 view .LVU1159
+ 3658              	.LBB385:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3659              		.loc 2 3305 3 view .LVU1160
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3660              		.loc 2 3307 3 view .LVU1161
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3661              		.loc 2 3307 10 is_stmt 0 view .LVU1162
+ 3662 0268 4B6E     		ldr	r3, [r1, #100]
+ 3663              	.LVL322:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3664              		.loc 2 3307 10 view .LVU1163
+ 3665              	.LBE385:
+ 3666              	.LBE384:
+ 3667              	.LBB386:
+ 3668              	.LBI386:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3669              		.loc 2 3303 26 is_stmt 1 view .LVU1164
+ 3670              	.LBB387:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3671              		.loc 2 3305 3 view .LVU1165
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3672              		.loc 2 3307 3 view .LVU1166
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3673              		.loc 2 3307 10 is_stmt 0 view .LVU1167
+ 3674 026a 4A6E     		ldr	r2, [r1, #100]
+ 3675              	.LVL323:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3676              		.loc 2 3307 10 view .LVU1168
+ 3677              	.LBE387:
+ 3678              	.LBE386:
+ARM GAS  /tmp/cc3JIfda.s 			page 232
+
+
+ 3679              		.loc 1 1985 11 view .LVU1169
+ 3680 026c C2F38462 		ubfx	r2, r2, #26, #5
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ 3681              		.loc 1 1986 14 view .LVU1170
+ 3682 0270 2B68     		ldr	r3, [r5]
+ 3683 0272 C3F31200 		ubfx	r0, r3, #0, #19
+ 3684 0276 78BB     		cbnz	r0, .L263
+ 3685              		.loc 1 1986 14 discriminator 1 view .LVU1171
+ 3686 0278 C3F38463 		ubfx	r3, r3, #26, #5
+ 3687              	.L264:
+1985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ 3688              		.loc 1 1985 10 view .LVU1172
+ 3689 027c 9A42     		cmp	r2, r3
+ 3690 027e 33D0     		beq	.L329
+ 3691              	.L266:
+1987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
+1989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+ 3692              		.loc 1 1990 7 is_stmt 1 view .LVU1173
+ 3693              		.loc 1 1990 11 is_stmt 0 view .LVU1174
+ 3694 0280 2168     		ldr	r1, [r4]
+ 3695              	.LVL324:
+ 3696              	.LBB388:
+ 3697              	.LBI388:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3698              		.loc 2 3303 26 is_stmt 1 view .LVU1175
+ 3699              	.LBB389:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3700              		.loc 2 3305 3 view .LVU1176
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3701              		.loc 2 3307 3 view .LVU1177
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3702              		.loc 2 3307 10 is_stmt 0 view .LVU1178
+ 3703 0282 8B6E     		ldr	r3, [r1, #104]
+ 3704              	.LVL325:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3705              		.loc 2 3307 10 view .LVU1179
+ 3706              	.LBE389:
+ 3707              	.LBE388:
+ 3708              	.LBB390:
+ 3709              	.LBI390:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3710              		.loc 2 3303 26 is_stmt 1 view .LVU1180
+ 3711              	.LBB391:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3712              		.loc 2 3305 3 view .LVU1181
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3713              		.loc 2 3307 3 view .LVU1182
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3714              		.loc 2 3307 10 is_stmt 0 view .LVU1183
+ 3715 0284 8A6E     		ldr	r2, [r1, #104]
+ 3716              	.LVL326:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3717              		.loc 2 3307 10 view .LVU1184
+ 3718              	.LBE391:
+ 3719              	.LBE390:
+ARM GAS  /tmp/cc3JIfda.s 			page 233
+
+
+ 3720              		.loc 1 1990 11 view .LVU1185
+ 3721 0286 C2F38462 		ubfx	r2, r2, #26, #5
+1991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ 3722              		.loc 1 1991 14 view .LVU1186
+ 3723 028a 2B68     		ldr	r3, [r5]
+ 3724 028c C3F31200 		ubfx	r0, r3, #0, #19
+ 3725 0290 78BB     		cbnz	r0, .L267
+ 3726              		.loc 1 1991 14 discriminator 1 view .LVU1187
+ 3727 0292 C3F38463 		ubfx	r3, r3, #26, #5
+ 3728              	.L268:
+1990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ 3729              		.loc 1 1990 10 view .LVU1188
+ 3730 0296 9A42     		cmp	r2, r3
+ 3731 0298 33D0     		beq	.L330
+ 3732              	.L270:
+1992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
+1994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+1995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+ 3733              		.loc 1 1995 7 is_stmt 1 view .LVU1189
+ 3734              		.loc 1 1995 11 is_stmt 0 view .LVU1190
+ 3735 029a 2168     		ldr	r1, [r4]
+ 3736              	.LVL327:
+ 3737              	.LBB392:
+ 3738              	.LBI392:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3739              		.loc 2 3303 26 is_stmt 1 view .LVU1191
+ 3740              	.LBB393:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3741              		.loc 2 3305 3 view .LVU1192
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3742              		.loc 2 3307 3 view .LVU1193
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3743              		.loc 2 3307 10 is_stmt 0 view .LVU1194
+ 3744 029c CB6E     		ldr	r3, [r1, #108]
+ 3745              	.LVL328:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3746              		.loc 2 3307 10 view .LVU1195
+ 3747              	.LBE393:
+ 3748              	.LBE392:
+ 3749              	.LBB394:
+ 3750              	.LBI394:
+3303:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3751              		.loc 2 3303 26 is_stmt 1 view .LVU1196
+ 3752              	.LBB395:
+3305:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3753              		.loc 2 3305 3 view .LVU1197
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3754              		.loc 2 3307 3 view .LVU1198
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3755              		.loc 2 3307 10 is_stmt 0 view .LVU1199
+ 3756 029e CA6E     		ldr	r2, [r1, #108]
+ 3757              	.LVL329:
+3307:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 3758              		.loc 2 3307 10 view .LVU1200
+ 3759              	.LBE395:
+ 3760              	.LBE394:
+ARM GAS  /tmp/cc3JIfda.s 			page 234
+
+
+ 3761              		.loc 1 1995 11 view .LVU1201
+ 3762 02a0 C2F38462 		ubfx	r2, r2, #26, #5
+1996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ 3763              		.loc 1 1996 14 view .LVU1202
+ 3764 02a4 2B68     		ldr	r3, [r5]
+ 3765 02a6 C3F31200 		ubfx	r0, r3, #0, #19
+ 3766 02aa 78BB     		cbnz	r0, .L271
+ 3767              		.loc 1 1996 14 discriminator 1 view .LVU1203
+ 3768 02ac C3F38463 		ubfx	r3, r3, #26, #5
+ 3769              	.L272:
+1995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ 3770              		.loc 1 1995 10 view .LVU1204
+ 3771 02b0 9A42     		cmp	r2, r3
+ 3772 02b2 34D1     		bne	.L247
+1997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+1998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
+ 3773              		.loc 1 1998 9 is_stmt 1 view .LVU1205
+ 3774              	.LVL330:
+ 3775              	.LBB396:
+ 3776              	.LBI396:
+3362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3777              		.loc 2 3362 22 view .LVU1206
+ 3778              	.LBB397:
+3364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3779              		.loc 2 3364 3 view .LVU1207
+3366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN,
+ 3780              		.loc 2 3366 3 view .LVU1208
+ 3781 02b4 CB6E     		ldr	r3, [r1, #108]
+ 3782 02b6 23F00043 		bic	r3, r3, #-2147483648
+ 3783 02ba CB66     		str	r3, [r1, #108]
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3784              		.loc 2 3369 1 is_stmt 0 view .LVU1209
+ 3785 02bc 2FE0     		b	.L247
+ 3786              	.LVL331:
+ 3787              	.L259:
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3788              		.loc 2 3369 1 view .LVU1210
+ 3789              	.LBE397:
+ 3790              	.LBE396:
+ 3791              	.LBB398:
+ 3792              	.LBI398:
+ 3793              		.file 3 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.2.0
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     08. May 2019
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+ARM GAS  /tmp/cc3JIfda.s 			page 235
+
+
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ARM GAS  /tmp/cc3JIfda.s 			page 236
+
+
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ARM GAS  /tmp/cc3JIfda.s 			page 237
+
+
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ARM GAS  /tmp/cc3JIfda.s 			page 238
+
+
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/cc3JIfda.s 			page 239
+
+
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ARM GAS  /tmp/cc3JIfda.s 			page 240
+
+
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/cc3JIfda.s 			page 241
+
+
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/cc3JIfda.s 			page 242
+
+
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/cc3JIfda.s 			page 243
+
+
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ARM GAS  /tmp/cc3JIfda.s 			page 244
+
+
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ARM GAS  /tmp/cc3JIfda.s 			page 245
+
+
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ARM GAS  /tmp/cc3JIfda.s 			page 246
+
+
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ARM GAS  /tmp/cc3JIfda.s 			page 247
+
+
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/cc3JIfda.s 			page 248
+
+
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ARM GAS  /tmp/cc3JIfda.s 			page 249
+
+
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/cc3JIfda.s 			page 250
+
+
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 882:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 883:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 885:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 888:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 900:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 901:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 902:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 904:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 906:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 908:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 913:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 915:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 916:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 918:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 922:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 923:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 925:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/cc3JIfda.s 			page 251
+
+
+ 928:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 930:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 931:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 932:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 938:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 940:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 942:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 943:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+ 945:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 946:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 947:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 948:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 949:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 950:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ 952:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 953:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 954:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
+ 956:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 958:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 959:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 960:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 961:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 962:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
+ 963:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
+ 964:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 965:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 966:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 967:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+ 968:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 969:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ 970:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_bswap32(value);
+ 971:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 972:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 974:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 975:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 976:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 977:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 978:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 979:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 980:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 982:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 984:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ARM GAS  /tmp/cc3JIfda.s 			page 252
+
+
+ 985:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 986:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+ 987:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 989:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 990:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 991:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 992:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 993:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 994:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 995:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 996:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 997:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
+ 998:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 999:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+1000:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1001:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+1002:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1003:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1004:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
+1005:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1006:Drivers/CMSIS/Include/cmsis_gcc.h ****   int16_t result;
+1007:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1008:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+1009:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+1010:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1011:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1014:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1015:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
+1016:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
+1017:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
+1018:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
+1019:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Rotated value
+1020:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1021:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+1022:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1023:Drivers/CMSIS/Include/cmsis_gcc.h ****   op2 %= 32U;
+1024:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (op2 == 0U)
+1025:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1026:Drivers/CMSIS/Include/cmsis_gcc.h ****     return op1;
+1027:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1028:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
+1029:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1030:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1031:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1032:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1033:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Breakpoint
+1034:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
+1035:Drivers/CMSIS/Include/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
+1036:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
+1037:Drivers/CMSIS/Include/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
+1038:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1039:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+1040:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1041:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cc3JIfda.s 			page 253
+
+
+1042:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1043:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse bit order of value
+1044:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
+1045:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+1046:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+1047:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+ 3794              		.loc 3 1048 31 is_stmt 1 discriminator 2 view .LVU1211
+ 3795              	.LBB399:
+1049:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1050:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 3796              		.loc 3 1050 3 discriminator 2 view .LVU1212
+1051:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+1053:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+1054:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+1055:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 3797              		.loc 3 1055 4 discriminator 2 view .LVU1213
+ 3798              		.syntax unified
+ 3799              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3800 02be 93FAA3F3 		rbit r3, r3
+ 3801              	@ 0 "" 2
+ 3802              	.LVL332:
+1056:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1057:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+1058:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1059:Drivers/CMSIS/Include/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
+1060:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
+1061:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1062:Drivers/CMSIS/Include/cmsis_gcc.h ****     result <<= 1U;
+1063:Drivers/CMSIS/Include/cmsis_gcc.h ****     result |= value & 1U;
+1064:Drivers/CMSIS/Include/cmsis_gcc.h ****     s--;
+1065:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1066:Drivers/CMSIS/Include/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
+1067:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1068:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 3803              		.loc 3 1068 3 discriminator 2 view .LVU1214
+ 3804              		.loc 3 1068 3 is_stmt 0 discriminator 2 view .LVU1215
+ 3805              		.thumb
+ 3806              		.syntax unified
+ 3807              	.LBE399:
+ 3808              	.LBE398:
+ 3809              	.LBB400:
+ 3810              	.LBI400:
+1069:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1072:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1073:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Count leading zeros
+1074:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
+1075:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
+1076:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             number of leading zeros in value
+1077:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+ 3811              		.loc 3 1078 30 is_stmt 1 discriminator 2 view .LVU1216
+ 3812              	.LBB401:
+1079:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/cc3JIfda.s 			page 254
+
+
+1080:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+1081:Drivers/CMSIS/Include/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
+1082:Drivers/CMSIS/Include/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
+1083:Drivers/CMSIS/Include/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
+1084:Drivers/CMSIS/Include/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
+1085:Drivers/CMSIS/Include/cmsis_gcc.h ****      is non-zero".
+1086:Drivers/CMSIS/Include/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+1087:Drivers/CMSIS/Include/cmsis_gcc.h ****      single CLZ instruction.
+1088:Drivers/CMSIS/Include/cmsis_gcc.h ****    */
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (value == 0U)
+ 3813              		.loc 3 1089 3 discriminator 2 view .LVU1217
+ 3814              		.loc 3 1089 6 is_stmt 0 discriminator 2 view .LVU1218
+ 3815 02c2 13B1     		cbz	r3, .L310
+1090:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****     return 32U;
+1092:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1093:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_clz(value);
+ 3816              		.loc 3 1093 3 is_stmt 1 view .LVU1219
+ 3817              		.loc 3 1093 10 is_stmt 0 view .LVU1220
+ 3818 02c4 B3FA83F3 		clz	r3, r3
+ 3819              	.LVL333:
+ 3820              		.loc 3 1093 10 view .LVU1221
+ 3821 02c8 CBE7     		b	.L260
+ 3822              	.LVL334:
+ 3823              	.L310:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3824              		.loc 3 1091 12 view .LVU1222
+ 3825 02ca 2023     		movs	r3, #32
+ 3826              	.LVL335:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3827              		.loc 3 1091 12 view .LVU1223
+ 3828 02cc C9E7     		b	.L260
+ 3829              	.L328:
+ 3830              	.LBE401:
+ 3831              	.LBE400:
+1983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3832              		.loc 1 1983 9 is_stmt 1 view .LVU1224
+ 3833              	.LVL336:
+ 3834              	.LBB402:
+ 3835              	.LBI402:
+3362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3836              		.loc 2 3362 22 view .LVU1225
+ 3837              	.LBB403:
+3364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3838              		.loc 2 3364 3 view .LVU1226
+3366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN,
+ 3839              		.loc 2 3366 3 view .LVU1227
+ 3840 02ce 0B6E     		ldr	r3, [r1, #96]
+ 3841 02d0 23F00043 		bic	r3, r3, #-2147483648
+ 3842 02d4 0B66     		str	r3, [r1, #96]
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3843              		.loc 2 3369 1 is_stmt 0 view .LVU1228
+ 3844 02d6 C6E7     		b	.L262
+ 3845              	.LVL337:
+ 3846              	.L263:
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3847              		.loc 2 3369 1 view .LVU1229
+ARM GAS  /tmp/cc3JIfda.s 			page 255
+
+
+ 3848              	.LBE403:
+ 3849              	.LBE402:
+ 3850              	.LBB404:
+ 3851              	.LBI404:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3852              		.loc 3 1048 31 is_stmt 1 discriminator 2 view .LVU1230
+ 3853              	.LBB405:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3854              		.loc 3 1050 3 discriminator 2 view .LVU1231
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 3855              		.loc 3 1055 4 discriminator 2 view .LVU1232
+ 3856              		.syntax unified
+ 3857              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3858 02d8 93FAA3F3 		rbit r3, r3
+ 3859              	@ 0 "" 2
+ 3860              	.LVL338:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3861              		.loc 3 1068 3 discriminator 2 view .LVU1233
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3862              		.loc 3 1068 3 is_stmt 0 discriminator 2 view .LVU1234
+ 3863              		.thumb
+ 3864              		.syntax unified
+ 3865              	.LBE405:
+ 3866              	.LBE404:
+ 3867              	.LBB406:
+ 3868              	.LBI406:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3869              		.loc 3 1078 30 is_stmt 1 discriminator 2 view .LVU1235
+ 3870              	.LBB407:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3871              		.loc 3 1089 3 discriminator 2 view .LVU1236
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3872              		.loc 3 1089 6 is_stmt 0 discriminator 2 view .LVU1237
+ 3873 02dc 13B1     		cbz	r3, .L311
+ 3874              		.loc 3 1093 3 is_stmt 1 view .LVU1238
+ 3875              		.loc 3 1093 10 is_stmt 0 view .LVU1239
+ 3876 02de B3FA83F3 		clz	r3, r3
+ 3877              	.LVL339:
+ 3878              		.loc 3 1093 10 view .LVU1240
+ 3879 02e2 CBE7     		b	.L264
+ 3880              	.LVL340:
+ 3881              	.L311:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3882              		.loc 3 1091 12 view .LVU1241
+ 3883 02e4 2023     		movs	r3, #32
+ 3884              	.LVL341:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3885              		.loc 3 1091 12 view .LVU1242
+ 3886 02e6 C9E7     		b	.L264
+ 3887              	.L329:
+ 3888              	.LBE407:
+ 3889              	.LBE406:
+1988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3890              		.loc 1 1988 9 is_stmt 1 view .LVU1243
+ 3891              	.LVL342:
+ 3892              	.LBB408:
+ 3893              	.LBI408:
+ARM GAS  /tmp/cc3JIfda.s 			page 256
+
+
+3362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3894              		.loc 2 3362 22 view .LVU1244
+ 3895              	.LBB409:
+3364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3896              		.loc 2 3364 3 view .LVU1245
+3366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN,
+ 3897              		.loc 2 3366 3 view .LVU1246
+ 3898 02e8 4B6E     		ldr	r3, [r1, #100]
+ 3899 02ea 23F00043 		bic	r3, r3, #-2147483648
+ 3900 02ee 4B66     		str	r3, [r1, #100]
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3901              		.loc 2 3369 1 is_stmt 0 view .LVU1247
+ 3902 02f0 C6E7     		b	.L266
+ 3903              	.LVL343:
+ 3904              	.L267:
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3905              		.loc 2 3369 1 view .LVU1248
+ 3906              	.LBE409:
+ 3907              	.LBE408:
+ 3908              	.LBB410:
+ 3909              	.LBI410:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3910              		.loc 3 1048 31 is_stmt 1 discriminator 2 view .LVU1249
+ 3911              	.LBB411:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3912              		.loc 3 1050 3 discriminator 2 view .LVU1250
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 3913              		.loc 3 1055 4 discriminator 2 view .LVU1251
+ 3914              		.syntax unified
+ 3915              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3916 02f2 93FAA3F3 		rbit r3, r3
+ 3917              	@ 0 "" 2
+ 3918              	.LVL344:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3919              		.loc 3 1068 3 discriminator 2 view .LVU1252
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3920              		.loc 3 1068 3 is_stmt 0 discriminator 2 view .LVU1253
+ 3921              		.thumb
+ 3922              		.syntax unified
+ 3923              	.LBE411:
+ 3924              	.LBE410:
+ 3925              	.LBB412:
+ 3926              	.LBI412:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3927              		.loc 3 1078 30 is_stmt 1 discriminator 2 view .LVU1254
+ 3928              	.LBB413:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3929              		.loc 3 1089 3 discriminator 2 view .LVU1255
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3930              		.loc 3 1089 6 is_stmt 0 discriminator 2 view .LVU1256
+ 3931 02f6 13B1     		cbz	r3, .L312
+ 3932              		.loc 3 1093 3 is_stmt 1 view .LVU1257
+ 3933              		.loc 3 1093 10 is_stmt 0 view .LVU1258
+ 3934 02f8 B3FA83F3 		clz	r3, r3
+ 3935              	.LVL345:
+ 3936              		.loc 3 1093 10 view .LVU1259
+ 3937 02fc CBE7     		b	.L268
+ARM GAS  /tmp/cc3JIfda.s 			page 257
+
+
+ 3938              	.LVL346:
+ 3939              	.L312:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3940              		.loc 3 1091 12 view .LVU1260
+ 3941 02fe 2023     		movs	r3, #32
+ 3942              	.LVL347:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3943              		.loc 3 1091 12 view .LVU1261
+ 3944 0300 C9E7     		b	.L268
+ 3945              	.L330:
+ 3946              	.LBE413:
+ 3947              	.LBE412:
+1993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+ 3948              		.loc 1 1993 9 is_stmt 1 view .LVU1262
+ 3949              	.LVL348:
+ 3950              	.LBB414:
+ 3951              	.LBI414:
+3362:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 3952              		.loc 2 3362 22 view .LVU1263
+ 3953              	.LBB415:
+3364:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3954              		.loc 2 3364 3 view .LVU1264
+3366:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_OFR1_OFFSET1_EN,
+ 3955              		.loc 2 3366 3 view .LVU1265
+ 3956 0302 8B6E     		ldr	r3, [r1, #104]
+ 3957 0304 23F00043 		bic	r3, r3, #-2147483648
+ 3958 0308 8B66     		str	r3, [r1, #104]
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3959              		.loc 2 3369 1 is_stmt 0 view .LVU1266
+ 3960 030a C6E7     		b	.L270
+ 3961              	.LVL349:
+ 3962              	.L271:
+3369:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 3963              		.loc 2 3369 1 view .LVU1267
+ 3964              	.LBE415:
+ 3965              	.LBE414:
+ 3966              	.LBB416:
+ 3967              	.LBI416:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3968              		.loc 3 1048 31 is_stmt 1 discriminator 2 view .LVU1268
+ 3969              	.LBB417:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3970              		.loc 3 1050 3 discriminator 2 view .LVU1269
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 3971              		.loc 3 1055 4 discriminator 2 view .LVU1270
+ 3972              		.syntax unified
+ 3973              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3974 030c 93FAA3F3 		rbit r3, r3
+ 3975              	@ 0 "" 2
+ 3976              	.LVL350:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3977              		.loc 3 1068 3 discriminator 2 view .LVU1271
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3978              		.loc 3 1068 3 is_stmt 0 discriminator 2 view .LVU1272
+ 3979              		.thumb
+ 3980              		.syntax unified
+ 3981              	.LBE417:
+ARM GAS  /tmp/cc3JIfda.s 			page 258
+
+
+ 3982              	.LBE416:
+ 3983              	.LBB418:
+ 3984              	.LBI418:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3985              		.loc 3 1078 30 is_stmt 1 discriminator 2 view .LVU1273
+ 3986              	.LBB419:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3987              		.loc 3 1089 3 discriminator 2 view .LVU1274
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 3988              		.loc 3 1089 6 is_stmt 0 discriminator 2 view .LVU1275
+ 3989 0310 13B1     		cbz	r3, .L313
+ 3990              		.loc 3 1093 3 is_stmt 1 view .LVU1276
+ 3991              		.loc 3 1093 10 is_stmt 0 view .LVU1277
+ 3992 0312 B3FA83F3 		clz	r3, r3
+ 3993              	.LVL351:
+ 3994              		.loc 3 1093 10 view .LVU1278
+ 3995 0316 CBE7     		b	.L272
+ 3996              	.LVL352:
+ 3997              	.L313:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 3998              		.loc 3 1091 12 view .LVU1279
+ 3999 0318 2023     		movs	r3, #32
+ 4000              	.LVL353:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4001              		.loc 3 1091 12 view .LVU1280
+ 4002 031a C9E7     		b	.L272
+ 4003              	.LVL354:
+ 4004              	.L308:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4005              		.loc 3 1091 12 view .LVU1281
+ 4006              	.LBE419:
+ 4007              	.LBE418:
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmpOffsetShifted;
+ 4008              		.loc 1 1660 21 view .LVU1282
+ 4009 031c 0027     		movs	r7, #0
+ 4010              	.LVL355:
+ 4011              	.L247:
+1999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+2001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Parameters update conditioned to ADC state:                              */
+2005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Parameters that can be updated only when ADC is disabled:                */
+2006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*  - Single or differential mode                                           */
+2007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ 4012              		.loc 1 2007 3 is_stmt 1 view .LVU1283
+ 4013              		.loc 1 2007 7 is_stmt 0 view .LVU1284
+ 4014 031e 2368     		ldr	r3, [r4]
+ 4015              	.LVL356:
+ 4016              	.LBB420:
+ 4017              	.LBI420:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4018              		.loc 2 6729 26 is_stmt 1 view .LVU1285
+ 4019              	.LBB421:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4020              		.loc 2 6731 3 view .LVU1286
+ARM GAS  /tmp/cc3JIfda.s 			page 259
+
+
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4021              		.loc 2 6731 12 is_stmt 0 view .LVU1287
+ 4022 0320 9A68     		ldr	r2, [r3, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4023              		.loc 2 6731 68 view .LVU1288
+ 4024 0322 12F0010F 		tst	r2, #1
+ 4025 0326 10D1     		bne	.L274
+ 4026              	.LVL357:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4027              		.loc 2 6731 68 view .LVU1289
+ 4028              	.LBE421:
+ 4029              	.LBE420:
+2008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Set mode single-ended or differential input of the selected ADC channel */
+2010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->
+ 4030              		.loc 1 2010 5 is_stmt 1 view .LVU1290
+ 4031 0328 2A68     		ldr	r2, [r5]
+ 4032 032a E868     		ldr	r0, [r5, #12]
+ 4033              	.LVL358:
+ 4034              	.LBB422:
+ 4035              	.LBI422:
+5495:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4036              		.loc 2 5495 22 view .LVU1291
+ 4037              	.LBB423:
+5501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+ 4038              		.loc 2 5501 3 view .LVU1292
+5501:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****   {
+ 4039              		.loc 2 5501 6 is_stmt 0 view .LVU1293
+ 4040 032c 1C49     		ldr	r1, .L335+4
+ 4041 032e 8842     		cmp	r0, r1
+ 4042 0330 2BD0     		beq	.L331
+5508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 4043              		.loc 2 5508 5 is_stmt 1 view .LVU1294
+ 4044 0332 D3F8B010 		ldr	r1, [r3, #176]
+ 4045 0336 C2F31202 		ubfx	r2, r2, #0, #19
+ 4046              	.LVL359:
+5508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 4047              		.loc 2 5508 5 is_stmt 0 view .LVU1295
+ 4048 033a 21EA0202 		bic	r2, r1, r2
+ 4049 033e C3F8B020 		str	r2, [r3, #176]
+ 4050              	.LVL360:
+ 4051              	.L276:
+5508:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 4052              		.loc 2 5508 5 view .LVU1296
+ 4053              	.LBE423:
+ 4054              	.LBE422:
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Configuration of differential mode */
+2013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range
+2014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
+ 4055              		.loc 1 2014 5 is_stmt 1 view .LVU1297
+ 4056              		.loc 1 2014 24 is_stmt 0 view .LVU1298
+ 4057 0342 EA68     		ldr	r2, [r5, #12]
+ 4058              		.loc 1 2014 8 view .LVU1299
+ 4059 0344 164B     		ldr	r3, .L335+4
+ 4060 0346 9A42     		cmp	r2, r3
+ 4061 0348 38D0     		beq	.L332
+ARM GAS  /tmp/cc3JIfda.s 			page 260
+
+
+ 4062              	.L274:
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+2016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Set sampling time of the selected ADC channel */
+2017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       LL_ADC_SetChannelSamplingTime(hadc->Instance,
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                     (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_
+2019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+2020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Management of internal measurement channels: Vbat/VrefInt/TempSensor   */
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* internal measurement paths enable: If internal channel selected,       */
+2026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* enable dedicated internal buffers and path.                            */
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Note: these internal measurement paths can be disabled using           */
+2028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* HAL_ADC_DeInit().                                                      */
+2029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
+ 4063              		.loc 1 2030 3 is_stmt 1 view .LVU1300
+ 4064              		.loc 1 2030 7 is_stmt 0 view .LVU1301
+ 4065 034a 2B68     		ldr	r3, [r5]
+ 4066              		.loc 1 2030 6 view .LVU1302
+ 4067 034c 154A     		ldr	r2, .L335+8
+ 4068 034e 1342     		tst	r3, r2
+ 4069 0350 13D0     		beq	.L300
+2031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Ins
+ 4070              		.loc 1 2032 5 is_stmt 1 view .LVU1303
+ 4071              	.LVL361:
+ 4072              	.LBB425:
+ 4073              	.LBI425:
+2877:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4074              		.loc 2 2877 26 view .LVU1304
+ 4075              	.LBB426:
+2879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4076              		.loc 2 2879 3 view .LVU1305
+2879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4077              		.loc 2 2879 21 is_stmt 0 view .LVU1306
+ 4078 0352 154A     		ldr	r2, .L335+12
+ 4079 0354 9268     		ldr	r2, [r2, #8]
+2879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4080              		.loc 2 2879 10 view .LVU1307
+ 4081 0356 02F0E071 		and	r1, r2, #29360128
+ 4082              	.LVL362:
+2879:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4083              		.loc 2 2879 10 view .LVU1308
+ 4084              	.LBE426:
+ 4085              	.LBE425:
+2033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* If the requested internal measurement path has already been enabled,   */
+2035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* bypass the configuration processing.                                   */
+2036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC1)
+ 4086              		.loc 1 2036 5 is_stmt 1 view .LVU1309
+ 4087              		.loc 1 2036 8 is_stmt 0 view .LVU1310
+ 4088 035a 1448     		ldr	r0, .L335+16
+ 4089 035c 8342     		cmp	r3, r0
+ 4090 035e 00F0DC80 		beq	.L301
+2037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****          || (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC5))
+ARM GAS  /tmp/cc3JIfda.s 			page 261
+
+
+ 4091              		.loc 1 2037 10 view .LVU1311
+ 4092 0362 1348     		ldr	r0, .L335+20
+ 4093 0364 8342     		cmp	r3, r0
+ 4094 0366 00F0D880 		beq	.L301
+ 4095              	.L302:
+2038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+2039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+2040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+2041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                        LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channe
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Delay for temperature sensor stabilization time */
+2046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Wait loop initialization and execution */
+2047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /* Note: Variable divided by 2 to compensate partially              */
+2048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /*       CPU processing cycles, scaling in us split to not          */
+2049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         /*       exceed 32 bits register capacity and handle low frequency. */
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000U
+2051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         while (wait_loop_index != 0UL)
+2052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****           wait_loop_index--;
+2054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+2055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+2056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
+ 4096              		.loc 1 2057 10 is_stmt 1 view .LVU1312
+ 4097              		.loc 1 2057 13 is_stmt 0 view .LVU1313
+ 4098 036a 1248     		ldr	r0, .L335+24
+ 4099 036c 8342     		cmp	r3, r0
+ 4100 036e 00F0F980 		beq	.L333
+ 4101              	.L305:
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****              && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+2059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+2062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+2063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                        LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+2066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
+ 4102              		.loc 1 2066 10 is_stmt 1 view .LVU1314
+ 4103              		.loc 1 2066 13 is_stmt 0 view .LVU1315
+ 4104 0372 1148     		ldr	r0, .L335+28
+ 4105 0374 8342     		cmp	r3, r0
+ 4106 0376 00F00781 		beq	.L334
+ 4107              	.LVL363:
+ 4108              	.L300:
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****              && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+2069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (ADC_VREFINT_INSTANCE(hadc))
+2070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+2072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                        LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+2073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+2075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else
+2076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ARM GAS  /tmp/cc3JIfda.s 			page 262
+
+
+2077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* nothing to do */
+2078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+ 4109              		.loc 1 2078 5 is_stmt 1 view .LVU1316
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process unlocked */
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 4110              		.loc 1 2082 3 view .LVU1317
+ 4111              		.loc 1 2082 3 view .LVU1318
+ 4112 037a 0023     		movs	r3, #0
+ 4113 037c 84F85830 		strb	r3, [r4, #88]
+ 4114              		.loc 1 2082 3 view .LVU1319
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return function status */
+2085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 4115              		.loc 1 2085 3 view .LVU1320
+ 4116              	.LVL364:
+ 4117              	.L235:
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 4118              		.loc 1 2086 1 is_stmt 0 view .LVU1321
+ 4119 0380 3846     		mov	r0, r7
+ 4120 0382 03B0     		add	sp, sp, #12
+ 4121              	.LCFI34:
+ 4122              		.cfi_remember_state
+ 4123              		.cfi_def_cfa_offset 20
+ 4124              		@ sp needed
+ 4125 0384 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 4126              	.LVL365:
+ 4127              	.L309:
+ 4128              	.LCFI35:
+ 4129              		.cfi_restore_state
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmpOffsetShifted;
+ 4130              		.loc 1 1660 21 view .LVU1322
+ 4131 0386 0027     		movs	r7, #0
+ 4132 0388 C9E7     		b	.L247
+ 4133              	.LVL366:
+ 4134              	.L331:
+ 4135              	.LBB427:
+ 4136              	.LBB424:
+5503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 4137              		.loc 2 5503 5 is_stmt 1 view .LVU1323
+ 4138 038a D3F8B010 		ldr	r1, [r3, #176]
+ 4139 038e C2F31202 		ubfx	r2, r2, #0, #19
+ 4140              	.LVL367:
+5503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 4141              		.loc 2 5503 5 is_stmt 0 view .LVU1324
+ 4142 0392 0A43     		orrs	r2, r2, r1
+ 4143 0394 C3F8B020 		str	r2, [r3, #176]
+ 4144              	.LVL368:
+5503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 4145              		.loc 2 5503 5 view .LVU1325
+ 4146 0398 D3E7     		b	.L276
+ 4147              	.L336:
+ 4148 039a 00BF     		.align	2
+ 4149              	.L335:
+ 4150 039c 00F0FF03 		.word	67104768
+ 4151 03a0 00007F40 		.word	1082064896
+ARM GAS  /tmp/cc3JIfda.s 			page 263
+
+
+ 4152 03a4 00000880 		.word	-2146959360
+ 4153 03a8 00030050 		.word	1342178048
+ 4154 03ac 000021C3 		.word	-1021247488
+ 4155 03b0 1000C090 		.word	-1866465264
+ 4156 03b4 000052C7 		.word	-950927360
+ 4157 03b8 000084CB 		.word	-880541696
+ 4158              	.LVL369:
+ 4159              	.L332:
+5503:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****             Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
+ 4160              		.loc 2 5503 5 view .LVU1326
+ 4161              	.LBE424:
+ 4162              	.LBE427:
+2017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                     (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_
+ 4163              		.loc 1 2017 7 is_stmt 1 view .LVU1327
+ 4164 03bc 2068     		ldr	r0, [r4]
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4165              		.loc 1 2018 48 is_stmt 0 view .LVU1328
+ 4166 03be 2B68     		ldr	r3, [r5]
+ 4167 03c0 C3F31206 		ubfx	r6, r3, #0, #19
+ 4168 03c4 3EBB     		cbnz	r6, .L277
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4169              		.loc 1 2018 48 discriminator 1 view .LVU1329
+ 4170 03c6 9A0E     		lsrs	r2, r3, #26
+ 4171 03c8 0132     		adds	r2, r2, #1
+ 4172 03ca 02F01F02 		and	r2, r2, #31
+ 4173 03ce 092A     		cmp	r2, #9
+ 4174 03d0 8CBF     		ite	hi
+ 4175 03d2 0022     		movhi	r2, #0
+ 4176 03d4 0122     		movls	r2, #1
+ 4177              	.L278:
+2017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                     (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_
+ 4178              		.loc 1 2017 7 view .LVU1330
+ 4179 03d6 002A     		cmp	r2, #0
+ 4180 03d8 55D0     		beq	.L280
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4181              		.loc 1 2018 48 view .LVU1331
+ 4182 03da 5EBB     		cbnz	r6, .L281
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4183              		.loc 1 2018 48 discriminator 3 view .LVU1332
+ 4184 03dc 990E     		lsrs	r1, r3, #26
+ 4185 03de 0131     		adds	r1, r1, #1
+ 4186 03e0 8906     		lsls	r1, r1, #26
+ 4187 03e2 01F0F841 		and	r1, r1, #2080374784
+ 4188              	.L282:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4189              		.loc 1 2018 48 discriminator 6 view .LVU1333
+ 4190 03e6 8EBB     		cbnz	r6, .L284
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4191              		.loc 1 2018 48 discriminator 7 view .LVU1334
+ 4192 03e8 4FEA936C 		lsr	ip, r3, #26
+ 4193 03ec 0CF1010C 		add	ip, ip, #1
+ 4194 03f0 0CF01F0C 		and	ip, ip, #31
+ 4195 03f4 0122     		movs	r2, #1
+ 4196 03f6 02FA0CF2 		lsl	r2, r2, ip
+ 4197              	.L285:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4198              		.loc 1 2018 48 discriminator 10 view .LVU1335
+ARM GAS  /tmp/cc3JIfda.s 			page 264
+
+
+ 4199 03fa 1143     		orrs	r1, r1, r2
+ 4200 03fc AEBB     		cbnz	r6, .L287
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4201              		.loc 1 2018 48 discriminator 11 view .LVU1336
+ 4202 03fe 9B0E     		lsrs	r3, r3, #26
+ 4203 0400 0133     		adds	r3, r3, #1
+ 4204 0402 03F01F03 		and	r3, r3, #31
+ 4205 0406 03EB4303 		add	r3, r3, r3, lsl #1
+ 4206 040a 1B05     		lsls	r3, r3, #20
+ 4207              	.L288:
+2017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                     (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_
+ 4208              		.loc 1 2017 7 view .LVU1337
+ 4209 040c 1943     		orrs	r1, r1, r3
+ 4210              	.L290:
+2017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                     (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_
+ 4211              		.loc 1 2017 7 discriminator 1 view .LVU1338
+ 4212 040e AA68     		ldr	r2, [r5, #8]
+ 4213 0410 FFF7FEFF 		bl	LL_ADC_SetChannelSamplingTime
+ 4214              	.LVL370:
+ 4215 0414 99E7     		b	.L274
+ 4216              	.L277:
+ 4217              	.LVL371:
+ 4218              	.LBB428:
+ 4219              	.LBI428:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4220              		.loc 3 1048 31 is_stmt 1 discriminator 2 view .LVU1339
+ 4221              	.LBB429:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4222              		.loc 3 1050 3 discriminator 2 view .LVU1340
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 4223              		.loc 3 1055 4 discriminator 2 view .LVU1341
+ 4224              		.syntax unified
+ 4225              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4226 0416 93FAA3F2 		rbit r2, r3
+ 4227              	@ 0 "" 2
+ 4228              	.LVL372:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4229              		.loc 3 1068 3 discriminator 2 view .LVU1342
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4230              		.loc 3 1068 3 is_stmt 0 discriminator 2 view .LVU1343
+ 4231              		.thumb
+ 4232              		.syntax unified
+ 4233              	.LBE429:
+ 4234              	.LBE428:
+ 4235              	.LBB430:
+ 4236              	.LBI430:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4237              		.loc 3 1078 30 is_stmt 1 discriminator 2 view .LVU1344
+ 4238              	.LBB431:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4239              		.loc 3 1089 3 discriminator 2 view .LVU1345
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4240              		.loc 3 1089 6 is_stmt 0 discriminator 2 view .LVU1346
+ 4241 041a 4AB1     		cbz	r2, .L314
+ 4242              		.loc 3 1093 3 is_stmt 1 view .LVU1347
+ 4243              		.loc 3 1093 10 is_stmt 0 view .LVU1348
+ 4244 041c B2FA82F2 		clz	r2, r2
+ARM GAS  /tmp/cc3JIfda.s 			page 265
+
+
+ 4245              	.LVL373:
+ 4246              	.L279:
+ 4247              		.loc 3 1093 10 view .LVU1349
+ 4248              	.LBE431:
+ 4249              	.LBE430:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4250              		.loc 1 2018 48 view .LVU1350
+ 4251 0420 0132     		adds	r2, r2, #1
+ 4252 0422 02F01F02 		and	r2, r2, #31
+ 4253 0426 092A     		cmp	r2, #9
+ 4254 0428 8CBF     		ite	hi
+ 4255 042a 0022     		movhi	r2, #0
+ 4256 042c 0122     		movls	r2, #1
+ 4257 042e D2E7     		b	.L278
+ 4258              	.LVL374:
+ 4259              	.L314:
+ 4260              	.LBB433:
+ 4261              	.LBB432:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4262              		.loc 3 1091 12 view .LVU1351
+ 4263 0430 2022     		movs	r2, #32
+ 4264              	.LVL375:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4265              		.loc 3 1091 12 view .LVU1352
+ 4266 0432 F5E7     		b	.L279
+ 4267              	.LVL376:
+ 4268              	.L281:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4269              		.loc 3 1091 12 view .LVU1353
+ 4270              	.LBE432:
+ 4271              	.LBE433:
+ 4272              	.LBB434:
+ 4273              	.LBI434:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4274              		.loc 3 1048 31 is_stmt 1 discriminator 4 view .LVU1354
+ 4275              	.LBB435:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4276              		.loc 3 1050 3 discriminator 4 view .LVU1355
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 4277              		.loc 3 1055 4 discriminator 4 view .LVU1356
+ 4278              		.syntax unified
+ 4279              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4280 0434 93FAA3F1 		rbit r1, r3
+ 4281              	@ 0 "" 2
+ 4282              	.LVL377:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4283              		.loc 3 1068 3 discriminator 4 view .LVU1357
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4284              		.loc 3 1068 3 is_stmt 0 discriminator 4 view .LVU1358
+ 4285              		.thumb
+ 4286              		.syntax unified
+ 4287              	.LBE435:
+ 4288              	.LBE434:
+ 4289              	.LBB436:
+ 4290              	.LBI436:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4291              		.loc 3 1078 30 is_stmt 1 discriminator 4 view .LVU1359
+ARM GAS  /tmp/cc3JIfda.s 			page 266
+
+
+ 4292              	.LBB437:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4293              		.loc 3 1089 3 discriminator 4 view .LVU1360
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4294              		.loc 3 1089 6 is_stmt 0 discriminator 4 view .LVU1361
+ 4295 0438 31B1     		cbz	r1, .L315
+ 4296              		.loc 3 1093 3 is_stmt 1 view .LVU1362
+ 4297              		.loc 3 1093 10 is_stmt 0 view .LVU1363
+ 4298 043a B1FA81F1 		clz	r1, r1
+ 4299              	.LVL378:
+ 4300              	.L283:
+ 4301              		.loc 3 1093 10 view .LVU1364
+ 4302              	.LBE437:
+ 4303              	.LBE436:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4304              		.loc 1 2018 48 view .LVU1365
+ 4305 043e 0131     		adds	r1, r1, #1
+ 4306 0440 8906     		lsls	r1, r1, #26
+ 4307 0442 01F0F841 		and	r1, r1, #2080374784
+ 4308 0446 CEE7     		b	.L282
+ 4309              	.LVL379:
+ 4310              	.L315:
+ 4311              	.LBB439:
+ 4312              	.LBB438:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4313              		.loc 3 1091 12 view .LVU1366
+ 4314 0448 2021     		movs	r1, #32
+ 4315              	.LVL380:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4316              		.loc 3 1091 12 view .LVU1367
+ 4317 044a F8E7     		b	.L283
+ 4318              	.LVL381:
+ 4319              	.L284:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4320              		.loc 3 1091 12 view .LVU1368
+ 4321              	.LBE438:
+ 4322              	.LBE439:
+ 4323              	.LBB440:
+ 4324              	.LBI440:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4325              		.loc 3 1048 31 is_stmt 1 discriminator 8 view .LVU1369
+ 4326              	.LBB441:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4327              		.loc 3 1050 3 discriminator 8 view .LVU1370
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 4328              		.loc 3 1055 4 discriminator 8 view .LVU1371
+ 4329              		.syntax unified
+ 4330              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4331 044c 93FAA3F2 		rbit r2, r3
+ 4332              	@ 0 "" 2
+ 4333              	.LVL382:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4334              		.loc 3 1068 3 discriminator 8 view .LVU1372
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4335              		.loc 3 1068 3 is_stmt 0 discriminator 8 view .LVU1373
+ 4336              		.thumb
+ 4337              		.syntax unified
+ARM GAS  /tmp/cc3JIfda.s 			page 267
+
+
+ 4338              	.LBE441:
+ 4339              	.LBE440:
+ 4340              	.LBB442:
+ 4341              	.LBI442:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4342              		.loc 3 1078 30 is_stmt 1 discriminator 8 view .LVU1374
+ 4343              	.LBB443:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4344              		.loc 3 1089 3 discriminator 8 view .LVU1375
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4345              		.loc 3 1089 6 is_stmt 0 discriminator 8 view .LVU1376
+ 4346 0450 4AB1     		cbz	r2, .L316
+ 4347              		.loc 3 1093 3 is_stmt 1 view .LVU1377
+ 4348              		.loc 3 1093 10 is_stmt 0 view .LVU1378
+ 4349 0452 B2FA82F2 		clz	r2, r2
+ 4350              	.LVL383:
+ 4351              	.L286:
+ 4352              		.loc 3 1093 10 view .LVU1379
+ 4353              	.LBE443:
+ 4354              	.LBE442:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4355              		.loc 1 2018 48 view .LVU1380
+ 4356 0456 0132     		adds	r2, r2, #1
+ 4357 0458 02F01F02 		and	r2, r2, #31
+ 4358 045c 4FF0010C 		mov	ip, #1
+ 4359 0460 0CFA02F2 		lsl	r2, ip, r2
+ 4360 0464 C9E7     		b	.L285
+ 4361              	.LVL384:
+ 4362              	.L316:
+ 4363              	.LBB445:
+ 4364              	.LBB444:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4365              		.loc 3 1091 12 view .LVU1381
+ 4366 0466 2022     		movs	r2, #32
+ 4367              	.LVL385:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4368              		.loc 3 1091 12 view .LVU1382
+ 4369 0468 F5E7     		b	.L286
+ 4370              	.LVL386:
+ 4371              	.L287:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4372              		.loc 3 1091 12 view .LVU1383
+ 4373              	.LBE444:
+ 4374              	.LBE445:
+ 4375              	.LBB446:
+ 4376              	.LBI446:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4377              		.loc 3 1048 31 is_stmt 1 discriminator 12 view .LVU1384
+ 4378              	.LBB447:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4379              		.loc 3 1050 3 discriminator 12 view .LVU1385
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 4380              		.loc 3 1055 4 discriminator 12 view .LVU1386
+ 4381              		.syntax unified
+ 4382              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4383 046a 93FAA3F3 		rbit r3, r3
+ 4384              	@ 0 "" 2
+ARM GAS  /tmp/cc3JIfda.s 			page 268
+
+
+ 4385              	.LVL387:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4386              		.loc 3 1068 3 discriminator 12 view .LVU1387
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4387              		.loc 3 1068 3 is_stmt 0 discriminator 12 view .LVU1388
+ 4388              		.thumb
+ 4389              		.syntax unified
+ 4390              	.LBE447:
+ 4391              	.LBE446:
+ 4392              	.LBB448:
+ 4393              	.LBI448:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4394              		.loc 3 1078 30 is_stmt 1 discriminator 12 view .LVU1389
+ 4395              	.LBB449:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4396              		.loc 3 1089 3 discriminator 12 view .LVU1390
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4397              		.loc 3 1089 6 is_stmt 0 discriminator 12 view .LVU1391
+ 4398 046e 43B1     		cbz	r3, .L317
+ 4399              		.loc 3 1093 3 is_stmt 1 view .LVU1392
+ 4400              		.loc 3 1093 10 is_stmt 0 view .LVU1393
+ 4401 0470 B3FA83F3 		clz	r3, r3
+ 4402              	.LVL388:
+ 4403              	.L289:
+ 4404              		.loc 3 1093 10 view .LVU1394
+ 4405              	.LBE449:
+ 4406              	.LBE448:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4407              		.loc 1 2018 48 view .LVU1395
+ 4408 0474 0133     		adds	r3, r3, #1
+ 4409 0476 03F01F03 		and	r3, r3, #31
+ 4410 047a 03EB4303 		add	r3, r3, r3, lsl #1
+ 4411 047e 1B05     		lsls	r3, r3, #20
+ 4412 0480 C4E7     		b	.L288
+ 4413              	.LVL389:
+ 4414              	.L317:
+ 4415              	.LBB451:
+ 4416              	.LBB450:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4417              		.loc 3 1091 12 view .LVU1396
+ 4418 0482 2023     		movs	r3, #32
+ 4419              	.LVL390:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4420              		.loc 3 1091 12 view .LVU1397
+ 4421 0484 F6E7     		b	.L289
+ 4422              	.LVL391:
+ 4423              	.L280:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4424              		.loc 3 1091 12 view .LVU1398
+ 4425              	.LBE450:
+ 4426              	.LBE451:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4427              		.loc 1 2018 48 view .LVU1399
+ 4428 0486 E6B9     		cbnz	r6, .L291
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4429              		.loc 1 2018 48 discriminator 13 view .LVU1400
+ 4430 0488 990E     		lsrs	r1, r3, #26
+ARM GAS  /tmp/cc3JIfda.s 			page 269
+
+
+ 4431 048a 0131     		adds	r1, r1, #1
+ 4432 048c 8906     		lsls	r1, r1, #26
+ 4433 048e 01F0F841 		and	r1, r1, #2080374784
+ 4434              	.L292:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4435              		.loc 1 2018 48 discriminator 16 view .LVU1401
+ 4436 0492 16BB     		cbnz	r6, .L294
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4437              		.loc 1 2018 48 discriminator 17 view .LVU1402
+ 4438 0494 4FEA936C 		lsr	ip, r3, #26
+ 4439 0498 0CF1010C 		add	ip, ip, #1
+ 4440 049c 0CF01F0C 		and	ip, ip, #31
+ 4441 04a0 0122     		movs	r2, #1
+ 4442 04a2 02FA0CF2 		lsl	r2, r2, ip
+ 4443              	.L295:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4444              		.loc 1 2018 48 discriminator 20 view .LVU1403
+ 4445 04a6 1143     		orrs	r1, r1, r2
+ 4446 04a8 36BB     		cbnz	r6, .L297
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4447              		.loc 1 2018 48 discriminator 21 view .LVU1404
+ 4448 04aa 9B0E     		lsrs	r3, r3, #26
+ 4449 04ac 0133     		adds	r3, r3, #1
+ 4450 04ae 03F01F03 		and	r3, r3, #31
+ 4451 04b2 03EB4303 		add	r3, r3, r3, lsl #1
+ 4452 04b6 1E3B     		subs	r3, r3, #30
+ 4453 04b8 1B05     		lsls	r3, r3, #20
+ 4454 04ba 43F00073 		orr	r3, r3, #33554432
+ 4455              	.L298:
+2017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                     (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_
+ 4456              		.loc 1 2017 7 discriminator 2 view .LVU1405
+ 4457 04be 1943     		orrs	r1, r1, r3
+ 4458 04c0 A5E7     		b	.L290
+ 4459              	.L291:
+ 4460              	.LVL392:
+ 4461              	.LBB452:
+ 4462              	.LBI452:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4463              		.loc 3 1048 31 is_stmt 1 discriminator 14 view .LVU1406
+ 4464              	.LBB453:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4465              		.loc 3 1050 3 discriminator 14 view .LVU1407
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 4466              		.loc 3 1055 4 discriminator 14 view .LVU1408
+ 4467              		.syntax unified
+ 4468              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4469 04c2 93FAA3F1 		rbit r1, r3
+ 4470              	@ 0 "" 2
+ 4471              	.LVL393:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4472              		.loc 3 1068 3 discriminator 14 view .LVU1409
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4473              		.loc 3 1068 3 is_stmt 0 discriminator 14 view .LVU1410
+ 4474              		.thumb
+ 4475              		.syntax unified
+ 4476              	.LBE453:
+ 4477              	.LBE452:
+ARM GAS  /tmp/cc3JIfda.s 			page 270
+
+
+ 4478              	.LBB454:
+ 4479              	.LBI454:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4480              		.loc 3 1078 30 is_stmt 1 discriminator 14 view .LVU1411
+ 4481              	.LBB455:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4482              		.loc 3 1089 3 discriminator 14 view .LVU1412
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4483              		.loc 3 1089 6 is_stmt 0 discriminator 14 view .LVU1413
+ 4484 04c6 31B1     		cbz	r1, .L318
+ 4485              		.loc 3 1093 3 is_stmt 1 view .LVU1414
+ 4486              		.loc 3 1093 10 is_stmt 0 view .LVU1415
+ 4487 04c8 B1FA81F1 		clz	r1, r1
+ 4488              	.LVL394:
+ 4489              	.L293:
+ 4490              		.loc 3 1093 10 view .LVU1416
+ 4491              	.LBE455:
+ 4492              	.LBE454:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4493              		.loc 1 2018 48 view .LVU1417
+ 4494 04cc 0131     		adds	r1, r1, #1
+ 4495 04ce 8906     		lsls	r1, r1, #26
+ 4496 04d0 01F0F841 		and	r1, r1, #2080374784
+ 4497 04d4 DDE7     		b	.L292
+ 4498              	.LVL395:
+ 4499              	.L318:
+ 4500              	.LBB457:
+ 4501              	.LBB456:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4502              		.loc 3 1091 12 view .LVU1418
+ 4503 04d6 2021     		movs	r1, #32
+ 4504              	.LVL396:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4505              		.loc 3 1091 12 view .LVU1419
+ 4506 04d8 F8E7     		b	.L293
+ 4507              	.LVL397:
+ 4508              	.L294:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4509              		.loc 3 1091 12 view .LVU1420
+ 4510              	.LBE456:
+ 4511              	.LBE457:
+ 4512              	.LBB458:
+ 4513              	.LBI458:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4514              		.loc 3 1048 31 is_stmt 1 discriminator 18 view .LVU1421
+ 4515              	.LBB459:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4516              		.loc 3 1050 3 discriminator 18 view .LVU1422
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 4517              		.loc 3 1055 4 discriminator 18 view .LVU1423
+ 4518              		.syntax unified
+ 4519              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4520 04da 93FAA3F2 		rbit r2, r3
+ 4521              	@ 0 "" 2
+ 4522              	.LVL398:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4523              		.loc 3 1068 3 discriminator 18 view .LVU1424
+ARM GAS  /tmp/cc3JIfda.s 			page 271
+
+
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4524              		.loc 3 1068 3 is_stmt 0 discriminator 18 view .LVU1425
+ 4525              		.thumb
+ 4526              		.syntax unified
+ 4527              	.LBE459:
+ 4528              	.LBE458:
+ 4529              	.LBB460:
+ 4530              	.LBI460:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4531              		.loc 3 1078 30 is_stmt 1 discriminator 18 view .LVU1426
+ 4532              	.LBB461:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4533              		.loc 3 1089 3 discriminator 18 view .LVU1427
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4534              		.loc 3 1089 6 is_stmt 0 discriminator 18 view .LVU1428
+ 4535 04de 4AB1     		cbz	r2, .L319
+ 4536              		.loc 3 1093 3 is_stmt 1 view .LVU1429
+ 4537              		.loc 3 1093 10 is_stmt 0 view .LVU1430
+ 4538 04e0 B2FA82F2 		clz	r2, r2
+ 4539              	.LVL399:
+ 4540              	.L296:
+ 4541              		.loc 3 1093 10 view .LVU1431
+ 4542              	.LBE461:
+ 4543              	.LBE460:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4544              		.loc 1 2018 48 view .LVU1432
+ 4545 04e4 0132     		adds	r2, r2, #1
+ 4546 04e6 02F01F02 		and	r2, r2, #31
+ 4547 04ea 4FF0010C 		mov	ip, #1
+ 4548 04ee 0CFA02F2 		lsl	r2, ip, r2
+ 4549 04f2 D8E7     		b	.L295
+ 4550              	.LVL400:
+ 4551              	.L319:
+ 4552              	.LBB463:
+ 4553              	.LBB462:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4554              		.loc 3 1091 12 view .LVU1433
+ 4555 04f4 2022     		movs	r2, #32
+ 4556              	.LVL401:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4557              		.loc 3 1091 12 view .LVU1434
+ 4558 04f6 F5E7     		b	.L296
+ 4559              	.LVL402:
+ 4560              	.L297:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4561              		.loc 3 1091 12 view .LVU1435
+ 4562              	.LBE462:
+ 4563              	.LBE463:
+ 4564              	.LBB464:
+ 4565              	.LBI464:
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4566              		.loc 3 1048 31 is_stmt 1 discriminator 22 view .LVU1436
+ 4567              	.LBB465:
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4568              		.loc 3 1050 3 discriminator 22 view .LVU1437
+1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 4569              		.loc 3 1055 4 discriminator 22 view .LVU1438
+ARM GAS  /tmp/cc3JIfda.s 			page 272
+
+
+ 4570              		.syntax unified
+ 4571              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4572 04f8 93FAA3F3 		rbit r3, r3
+ 4573              	@ 0 "" 2
+ 4574              	.LVL403:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4575              		.loc 3 1068 3 discriminator 22 view .LVU1439
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4576              		.loc 3 1068 3 is_stmt 0 discriminator 22 view .LVU1440
+ 4577              		.thumb
+ 4578              		.syntax unified
+ 4579              	.LBE465:
+ 4580              	.LBE464:
+ 4581              	.LBB466:
+ 4582              	.LBI466:
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4583              		.loc 3 1078 30 is_stmt 1 discriminator 22 view .LVU1441
+ 4584              	.LBB467:
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4585              		.loc 3 1089 3 discriminator 22 view .LVU1442
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 4586              		.loc 3 1089 6 is_stmt 0 discriminator 22 view .LVU1443
+ 4587 04fc 5BB1     		cbz	r3, .L320
+ 4588              		.loc 3 1093 3 is_stmt 1 view .LVU1444
+ 4589              		.loc 3 1093 10 is_stmt 0 view .LVU1445
+ 4590 04fe B3FA83F3 		clz	r3, r3
+ 4591              	.LVL404:
+ 4592              	.L299:
+ 4593              		.loc 3 1093 10 view .LVU1446
+ 4594              	.LBE467:
+ 4595              	.LBE466:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                                                                + 1UL) & 0x1FUL)), s
+ 4596              		.loc 1 2018 48 view .LVU1447
+ 4597 0502 0133     		adds	r3, r3, #1
+ 4598 0504 03F01F03 		and	r3, r3, #31
+ 4599 0508 03EB4303 		add	r3, r3, r3, lsl #1
+ 4600 050c 1E3B     		subs	r3, r3, #30
+ 4601 050e 1B05     		lsls	r3, r3, #20
+ 4602 0510 43F00073 		orr	r3, r3, #33554432
+ 4603 0514 D3E7     		b	.L298
+ 4604              	.LVL405:
+ 4605              	.L320:
+ 4606              	.LBB469:
+ 4607              	.LBB468:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4608              		.loc 3 1091 12 view .LVU1448
+ 4609 0516 2023     		movs	r3, #32
+ 4610              	.LVL406:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4611              		.loc 3 1091 12 view .LVU1449
+ 4612 0518 F3E7     		b	.L299
+ 4613              	.LVL407:
+ 4614              	.L301:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 4615              		.loc 3 1091 12 view .LVU1450
+ 4616              	.LBE468:
+ 4617              	.LBE469:
+ARM GAS  /tmp/cc3JIfda.s 			page 273
+
+
+2038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 4618              		.loc 1 2038 9 view .LVU1451
+ 4619 051a 12F4000F 		tst	r2, #8388608
+ 4620 051e 7FF424AF 		bne	.L302
+2040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 4621              		.loc 1 2040 7 is_stmt 1 view .LVU1452
+2040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 4622              		.loc 1 2040 11 is_stmt 0 view .LVU1453
+ 4623 0522 2368     		ldr	r3, [r4]
+2040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 4624              		.loc 1 2040 10 view .LVU1454
+ 4625 0524 B3F1A04F 		cmp	r3, #1342177280
+ 4626 0528 7FF427AF 		bne	.L300
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                        LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channe
+ 4627              		.loc 1 2042 9 is_stmt 1 view .LVU1455
+ 4628 052c 41F40001 		orr	r1, r1, #8388608
+ 4629              	.LVL408:
+ 4630              	.LBB470:
+ 4631              	.LBI470:
+2796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4632              		.loc 2 2796 22 view .LVU1456
+ 4633              	.LBB471:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4634              		.loc 2 2798 3 view .LVU1457
+ 4635 0530 1F4A     		ldr	r2, .L337
+ 4636              	.LVL409:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4637              		.loc 2 2798 3 is_stmt 0 view .LVU1458
+ 4638 0532 9368     		ldr	r3, [r2, #8]
+ 4639 0534 23F0E073 		bic	r3, r3, #29360128
+ 4640 0538 1943     		orrs	r1, r1, r3
+ 4641              	.LVL410:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4642              		.loc 2 2798 3 view .LVU1459
+ 4643 053a 9160     		str	r1, [r2, #8]
+ 4644              	.LVL411:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4645              		.loc 2 2798 3 view .LVU1460
+ 4646              	.LBE471:
+ 4647              	.LBE470:
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         while (wait_loop_index != 0UL)
+ 4648              		.loc 1 2050 9 is_stmt 1 view .LVU1461
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         while (wait_loop_index != 0UL)
+ 4649              		.loc 1 2050 90 is_stmt 0 view .LVU1462
+ 4650 053c 1D4B     		ldr	r3, .L337+4
+ 4651 053e 1B68     		ldr	r3, [r3]
+ 4652 0540 9B09     		lsrs	r3, r3, #6
+ 4653 0542 1D4A     		ldr	r2, .L337+8
+ 4654 0544 A2FB0323 		umull	r2, r3, r2, r3
+ 4655 0548 9B09     		lsrs	r3, r3, #6
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         while (wait_loop_index != 0UL)
+ 4656              		.loc 1 2050 69 view .LVU1463
+ 4657 054a 03EB4303 		add	r3, r3, r3, lsl #1
+ 4658 054e 9B00     		lsls	r3, r3, #2
+ 4659 0550 1833     		adds	r3, r3, #24
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         while (wait_loop_index != 0UL)
+ 4660              		.loc 1 2050 25 view .LVU1464
+ARM GAS  /tmp/cc3JIfda.s 			page 274
+
+
+ 4661 0552 0193     		str	r3, [sp, #4]
+2051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+ 4662              		.loc 1 2051 9 is_stmt 1 view .LVU1465
+2051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+ 4663              		.loc 1 2051 15 is_stmt 0 view .LVU1466
+ 4664 0554 02E0     		b	.L303
+ 4665              	.L304:
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 4666              		.loc 1 2053 11 is_stmt 1 view .LVU1467
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         }
+ 4667              		.loc 1 2053 26 is_stmt 0 view .LVU1468
+ 4668 0556 019B     		ldr	r3, [sp, #4]
+ 4669 0558 013B     		subs	r3, r3, #1
+ 4670 055a 0193     		str	r3, [sp, #4]
+ 4671              	.L303:
+2051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         {
+ 4672              		.loc 1 2051 32 is_stmt 1 view .LVU1469
+ 4673 055c 019B     		ldr	r3, [sp, #4]
+ 4674 055e 002B     		cmp	r3, #0
+ 4675 0560 F9D1     		bne	.L304
+ 4676 0562 0AE7     		b	.L300
+ 4677              	.LVL412:
+ 4678              	.L333:
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 4679              		.loc 1 2058 14 is_stmt 0 view .LVU1470
+ 4680 0564 12F0807F 		tst	r2, #16777216
+ 4681 0568 7FF403AF 		bne	.L305
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 4682              		.loc 1 2060 7 is_stmt 1 view .LVU1471
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 4683              		.loc 1 2060 11 is_stmt 0 view .LVU1472
+ 4684 056c 2268     		ldr	r2, [r4]
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 4685              		.loc 1 2060 10 view .LVU1473
+ 4686 056e 134B     		ldr	r3, .L337+12
+ 4687 0570 9A42     		cmp	r2, r3
+ 4688 0572 3FF402AF 		beq	.L300
+2062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                        LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+ 4689              		.loc 1 2062 9 is_stmt 1 view .LVU1474
+ 4690 0576 41F08071 		orr	r1, r1, #16777216
+ 4691              	.LVL413:
+ 4692              	.LBB472:
+ 4693              	.LBI472:
+2796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4694              		.loc 2 2796 22 view .LVU1475
+ 4695              	.LBB473:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4696              		.loc 2 2798 3 view .LVU1476
+ 4697 057a 0D4A     		ldr	r2, .L337
+ 4698 057c 9368     		ldr	r3, [r2, #8]
+ 4699 057e 23F0E073 		bic	r3, r3, #29360128
+ 4700 0582 1943     		orrs	r1, r1, r3
+ 4701              	.LVL414:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4702              		.loc 2 2798 3 is_stmt 0 view .LVU1477
+ 4703 0584 9160     		str	r1, [r2, #8]
+2799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ARM GAS  /tmp/cc3JIfda.s 			page 275
+
+
+ 4704              		.loc 2 2799 1 view .LVU1478
+ 4705 0586 F8E6     		b	.L300
+ 4706              	.LVL415:
+ 4707              	.L334:
+2799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4708              		.loc 2 2799 1 view .LVU1479
+ 4709              	.LBE473:
+ 4710              	.LBE472:
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+ 4711              		.loc 1 2067 14 view .LVU1480
+ 4712 0588 12F4800F 		tst	r2, #4194304
+ 4713 058c 7FF4F5AE 		bne	.L300
+2069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 4714              		.loc 1 2069 7 is_stmt 1 view .LVU1481
+2069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 4715              		.loc 1 2069 11 is_stmt 0 view .LVU1482
+ 4716 0590 2268     		ldr	r2, [r4]
+2069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+ 4717              		.loc 1 2069 10 view .LVU1483
+ 4718 0592 0A4B     		ldr	r3, .L337+12
+ 4719 0594 9A42     		cmp	r2, r3
+ 4720 0596 3FF4F0AE 		beq	.L300
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                                        LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ 4721              		.loc 1 2071 9 is_stmt 1 view .LVU1484
+ 4722 059a 41F48001 		orr	r1, r1, #4194304
+ 4723              	.LVL416:
+ 4724              	.LBB474:
+ 4725              	.LBI474:
+2796:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4726              		.loc 2 2796 22 view .LVU1485
+ 4727              	.LBB475:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4728              		.loc 2 2798 3 view .LVU1486
+ 4729 059e 044A     		ldr	r2, .L337
+ 4730 05a0 9368     		ldr	r3, [r2, #8]
+ 4731 05a2 23F0E073 		bic	r3, r3, #29360128
+ 4732 05a6 1943     		orrs	r1, r1, r3
+ 4733              	.LVL417:
+2798:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4734              		.loc 2 2798 3 is_stmt 0 view .LVU1487
+ 4735 05a8 9160     		str	r1, [r2, #8]
+2799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4736              		.loc 2 2799 1 view .LVU1488
+ 4737 05aa E6E6     		b	.L300
+ 4738              	.LVL418:
+ 4739              	.L306:
+2799:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** 
+ 4740              		.loc 2 2799 1 view .LVU1489
+ 4741              	.LBE475:
+ 4742              	.LBE474:
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 4743              		.loc 1 1712 3 view .LVU1490
+ 4744 05ac 0227     		movs	r7, #2
+ 4745 05ae E7E6     		b	.L235
+ 4746              	.L338:
+ 4747              		.align	2
+ 4748              	.L337:
+ARM GAS  /tmp/cc3JIfda.s 			page 276
+
+
+ 4749 05b0 00030050 		.word	1342178048
+ 4750 05b4 00000000 		.word	SystemCoreClock
+ 4751 05b8 632D3E05 		.word	87960931
+ 4752 05bc 00010050 		.word	1342177536
+ 4753              		.cfi_endproc
+ 4754              	.LFE350:
+ 4756              		.section	.text.HAL_ADCEx_MultiModeConfigChannel,"ax",%progbits
+ 4757              		.align	1
+ 4758              		.global	HAL_ADCEx_MultiModeConfigChannel
+ 4759              		.syntax unified
+ 4760              		.thumb
+ 4761              		.thumb_func
+ 4763              	HAL_ADCEx_MultiModeConfigChannel:
+ 4764              	.LVL419:
+ 4765              	.LFB351:
+2087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #if defined(ADC_MULTIMODE_SUPPORT)
+2089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+2090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Enable ADC multimode and configure multimode parameters
+2091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Possibility to update parameters on the fly:
+2092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         This function initializes multimode parameters, following
+2093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         calls to this function can be used to reconfigure some parameters
+2094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         of structure "ADC_MultiModeTypeDef" on the fly, without resetting
+2095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         the ADCs.
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         The setting of these parameters is conditioned to ADC state.
+2097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         For parameters constraints, see comments of structure
+2098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         "ADC_MultiModeTypeDef".
+2099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   To move back configuration from multimode to single mode, ADC must
+2100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         be reset (using function HAL_ADC_Init() ).
+2101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc Master ADC handle
+2102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param multimode Structure of ADC multimode configuration
+2103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+2104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+2105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *m
+2106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 4766              		.loc 1 2106 1 is_stmt 1 view -0
+ 4767              		.cfi_startproc
+ 4768              		@ args = 0, pretend = 0, frame = 112
+ 4769              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4770              		@ link register save eliminated.
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 4771              		.loc 1 2107 3 view .LVU1492
+2108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ADC_Common_TypeDef *tmpADC_Common;
+ 4772              		.loc 1 2108 3 view .LVU1493
+2109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ADC_HandleTypeDef tmphadcSlave;
+ 4773              		.loc 1 2109 3 view .LVU1494
+2110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmphadcSlave_conversion_on_going;
+ 4774              		.loc 1 2110 3 view .LVU1495
+2111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+2113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ 4775              		.loc 1 2113 3 view .LVU1496
+2114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_MULTIMODE(multimode->Mode));
+ 4776              		.loc 1 2114 3 view .LVU1497
+2115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (multimode->Mode != ADC_MODE_INDEPENDENT)
+ 4777              		.loc 1 2115 3 view .LVU1498
+2116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+ARM GAS  /tmp/cc3JIfda.s 			page 277
+
+
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
+ 4778              		.loc 1 2117 5 view .LVU1499
+2118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
+ 4779              		.loc 1 2118 5 view .LVU1500
+2119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process locked */
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 4780              		.loc 1 2122 3 view .LVU1501
+ 4781              		.loc 1 2122 3 view .LVU1502
+ 4782 0000 90F85820 		ldrb	r2, [r0, #88]	@ zero_extendqisi2
+ 4783 0004 012A     		cmp	r2, #1
+ 4784 0006 7FD0     		beq	.L352
+2106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 4785              		.loc 1 2106 1 is_stmt 0 discriminator 2 view .LVU1503
+ 4786 0008 10B4     		push	{r4}
+ 4787              	.LCFI36:
+ 4788              		.cfi_def_cfa_offset 4
+ 4789              		.cfi_offset 4, -4
+ 4790 000a 9DB0     		sub	sp, sp, #116
+ 4791              	.LCFI37:
+ 4792              		.cfi_def_cfa_offset 120
+ 4793 000c 0346     		mov	r3, r0
+ 4794              		.loc 1 2122 3 is_stmt 1 discriminator 2 view .LVU1504
+ 4795 000e 0122     		movs	r2, #1
+ 4796 0010 80F85820 		strb	r2, [r0, #88]
+ 4797              		.loc 1 2122 3 discriminator 2 view .LVU1505
+2123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Temporary handle minimum initialization */
+2125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ 4798              		.loc 1 2125 3 discriminator 2 view .LVU1506
+ 4799 0014 0022     		movs	r2, #0
+ 4800 0016 1892     		str	r2, [sp, #96]
+2126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+ 4801              		.loc 1 2126 3 discriminator 2 view .LVU1507
+ 4802 0018 1992     		str	r2, [sp, #100]
+2127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+ 4803              		.loc 1 2128 3 discriminator 2 view .LVU1508
+ 4804 001a 0068     		ldr	r0, [r0]
+ 4805              	.LVL420:
+ 4806              		.loc 1 2128 3 is_stmt 0 discriminator 2 view .LVU1509
+ 4807 001c B0F1A04F 		cmp	r0, #1342177280
+ 4808 0020 39D0     		beq	.L359
+ 4809 0022 0022     		movs	r2, #0
+ 4810 0024 0192     		str	r2, [sp, #4]
+ 4811              	.L342:
+2129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (tmphadcSlave.Instance == NULL)
+ 4812              		.loc 1 2130 3 is_stmt 1 view .LVU1510
+ 4813              		.loc 1 2130 19 is_stmt 0 view .LVU1511
+ 4814 0026 019A     		ldr	r2, [sp, #4]
+ 4815              		.loc 1 2130 6 view .LVU1512
+ 4816 0028 002A     		cmp	r2, #0
+ 4817 002a 37D0     		beq	.L360
+2131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Update ADC state machine to error */
+ARM GAS  /tmp/cc3JIfda.s 			page 278
+
+
+2133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+2134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Process unlocked */
+2136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     __HAL_UNLOCK(hadc);
+2137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     return HAL_ERROR;
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Parameters update conditioned to ADC state:                              */
+2142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Parameters that can be updated when ADC is disabled or enabled without   */
+2143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* conversion on going on regular group:                                    */
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*  - Multimode DMA configuration                                           */
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /*  - Multimode DMA mode                                                    */
+2146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ 4818              		.loc 1 2146 3 is_stmt 1 view .LVU1513
+ 4819              	.LVL421:
+ 4820              	.LBB476:
+ 4821              	.LBI476:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4822              		.loc 2 6851 26 view .LVU1514
+ 4823              	.LBB477:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4824              		.loc 2 6853 3 view .LVU1515
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4825              		.loc 2 6853 12 is_stmt 0 view .LVU1516
+ 4826 002c 9268     		ldr	r2, [r2, #8]
+ 4827              	.LVL422:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4828              		.loc 2 6853 74 view .LVU1517
+ 4829 002e 12F00402 		ands	r2, r2, #4
+ 4830 0032 00D0     		beq	.L344
+ 4831 0034 0122     		movs	r2, #1
+ 4832              	.L344:
+ 4833              	.LVL423:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4834              		.loc 2 6853 74 view .LVU1518
+ 4835              	.LBE477:
+ 4836              	.LBE476:
+2147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ 4837              		.loc 1 2147 3 is_stmt 1 view .LVU1519
+ 4838              	.LBB478:
+ 4839              	.LBI478:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4840              		.loc 2 6851 26 view .LVU1520
+ 4841              	.LBB479:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4842              		.loc 2 6853 3 view .LVU1521
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4843              		.loc 2 6853 12 is_stmt 0 view .LVU1522
+ 4844 0036 8068     		ldr	r0, [r0, #8]
+ 4845              	.LVL424:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4846              		.loc 2 6853 74 view .LVU1523
+ 4847 0038 10F0040F 		tst	r0, #4
+ 4848 003c 54D1     		bne	.L345
+ 4849              	.LVL425:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/cc3JIfda.s 			page 279
+
+
+ 4850              		.loc 2 6853 74 view .LVU1524
+ 4851              	.LBE479:
+ 4852              	.LBE478:
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       && (tmphadcSlave_conversion_on_going == 0UL))
+ 4853              		.loc 1 2148 7 view .LVU1525
+ 4854 003e 002A     		cmp	r2, #0
+ 4855 0040 52D1     		bne	.L345
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Pointer to the common control register */
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+ 4856              		.loc 1 2151 5 is_stmt 1 view .LVU1526
+ 4857              	.LVL426:
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* If multimode is selected, configure all multimode parameters.          */
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Otherwise, reset multimode parameters (can be used in case of          */
+2155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* transition from multimode to independent mode).                        */
+2156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     if (multimode->Mode != ADC_MODE_INDEPENDENT)
+ 4858              		.loc 1 2156 5 view .LVU1527
+ 4859              		.loc 1 2156 18 is_stmt 0 view .LVU1528
+ 4860 0042 0A68     		ldr	r2, [r1]
+ 4861              	.LVL427:
+ 4862              		.loc 1 2156 8 view .LVU1529
+ 4863 0044 002A     		cmp	r2, #0
+ 4864 0046 32D0     		beq	.L346
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+2158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
+ 4865              		.loc 1 2158 7 is_stmt 1 view .LVU1530
+ 4866 0048 304C     		ldr	r4, .L361
+ 4867 004a A268     		ldr	r2, [r4, #8]
+ 4868 004c 22F46042 		bic	r2, r2, #57344
+ 4869 0050 4868     		ldr	r0, [r1, #4]
+ 4870 0052 93F838C0 		ldrb	ip, [r3, #56]	@ zero_extendqisi2
+ 4871 0056 40EA4C30 		orr	r0, r0, ip, lsl #13
+ 4872 005a 0243     		orrs	r2, r2, r0
+ 4873 005c A260     		str	r2, [r4, #8]
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  multimode->DMAAccessMode |
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                  ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Parameters that can be updated only when ADC is disabled:                */
+2163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*  - Multimode mode selection                                              */
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*  - Multimode delay                                                       */
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*    Note: Delay range depends on selected resolution:                     */
+2166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*      from 1 to 12 clock cycles for 12 bits                               */
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*      from 1 to 10 clock cycles for 10 bits,                              */
+2168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*      from 1 to 8 clock cycles for 8 bits                                 */
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*      from 1 to 6 clock cycles for 6 bits                                 */
+2170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*    If a higher delay is selected, it will be clipped to maximum delay    */
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*    range                                                                 */
+2172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ 4874              		.loc 1 2172 7 view .LVU1531
+ 4875              	.LVL428:
+ 4876              	.LBB480:
+ 4877              	.LBI480:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4878              		.loc 2 6729 26 view .LVU1532
+ 4879              	.LBB481:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ARM GAS  /tmp/cc3JIfda.s 			page 280
+
+
+ 4880              		.loc 2 6731 3 view .LVU1533
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4881              		.loc 2 6731 12 is_stmt 0 view .LVU1534
+ 4882 005e 4FF0A042 		mov	r2, #1342177280
+ 4883 0062 9068     		ldr	r0, [r2, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4884              		.loc 2 6731 68 view .LVU1535
+ 4885 0064 10F00100 		ands	r0, r0, #1
+ 4886 0068 00D0     		beq	.L347
+ 4887 006a 0120     		movs	r0, #1
+ 4888              	.L347:
+ 4889              	.LVL429:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4890              		.loc 2 6731 68 view .LVU1536
+ 4891              	.LBE481:
+ 4892              	.LBE480:
+ 4893              	.LBB482:
+ 4894              	.LBI482:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4895              		.loc 2 6729 26 is_stmt 1 view .LVU1537
+ 4896              	.LBB483:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4897              		.loc 2 6731 3 view .LVU1538
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4898              		.loc 2 6731 12 is_stmt 0 view .LVU1539
+ 4899 006c 284A     		ldr	r2, .L361+4
+ 4900 006e 9268     		ldr	r2, [r2, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4901              		.loc 2 6731 68 view .LVU1540
+ 4902 0070 12F00102 		ands	r2, r2, #1
+ 4903 0074 00D0     		beq	.L348
+ 4904 0076 0122     		movs	r2, #1
+ 4905              	.L348:
+ 4906              	.LVL430:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4907              		.loc 2 6731 68 view .LVU1541
+ 4908              	.LBE483:
+ 4909              	.LBE482:
+ 4910              		.loc 1 2172 10 view .LVU1542
+ 4911 0078 0243     		orrs	r2, r2, r0
+ 4912 007a 41D1     		bne	.L353
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+2174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         MODIFY_REG(tmpADC_Common->CCR,
+ 4913              		.loc 1 2174 9 is_stmt 1 view .LVU1543
+ 4914 007c 234C     		ldr	r4, .L361
+ 4915 007e A268     		ldr	r2, [r4, #8]
+ 4916 0080 22F47162 		bic	r2, r2, #3856
+ 4917 0084 22F00F02 		bic	r2, r2, #15
+ 4918 0088 0868     		ldr	r0, [r1]
+ 4919 008a 8968     		ldr	r1, [r1, #8]
+ 4920              	.LVL431:
+ 4921              		.loc 1 2174 9 is_stmt 0 view .LVU1544
+ 4922 008c 0143     		orrs	r1, r1, r0
+ 4923 008e 0A43     		orrs	r2, r2, r1
+ 4924 0090 A260     		str	r2, [r4, #8]
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ADC_Common_TypeDef *tmpADC_Common;
+ 4925              		.loc 1 2107 21 view .LVU1545
+ARM GAS  /tmp/cc3JIfda.s 			page 281
+
+
+ 4926 0092 0020     		movs	r0, #0
+ 4927 0094 2DE0     		b	.L349
+ 4928              	.LVL432:
+ 4929              	.L359:
+2128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 4930              		.loc 1 2128 3 discriminator 1 view .LVU1546
+ 4931 0096 1E4A     		ldr	r2, .L361+4
+ 4932 0098 0192     		str	r2, [sp, #4]
+ 4933 009a C4E7     		b	.L342
+ 4934              	.L360:
+2133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 4935              		.loc 1 2133 5 is_stmt 1 view .LVU1547
+ 4936 009c DA6D     		ldr	r2, [r3, #92]
+ 4937 009e 42F02002 		orr	r2, r2, #32
+ 4938 00a2 DA65     		str	r2, [r3, #92]
+2136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 4939              		.loc 1 2136 5 view .LVU1548
+2136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 4940              		.loc 1 2136 5 view .LVU1549
+ 4941 00a4 0022     		movs	r2, #0
+ 4942 00a6 83F85820 		strb	r2, [r3, #88]
+2136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 4943              		.loc 1 2136 5 view .LVU1550
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 4944              		.loc 1 2138 5 view .LVU1551
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+ 4945              		.loc 1 2138 12 is_stmt 0 view .LVU1552
+ 4946 00aa 0120     		movs	r0, #1
+ 4947 00ac 24E0     		b	.L340
+ 4948              	.LVL433:
+ 4949              	.L346:
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                    ADC_CCR_DUAL |
+2176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                    ADC_CCR_DELAY,
+2177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                    multimode->Mode |
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                    multimode->TwoSamplingDelay
+2179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****                   );
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+2181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     else /* ADC_MODE_INDEPENDENT */
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     {
+2184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
+ 4950              		.loc 1 2184 7 is_stmt 1 view .LVU1553
+ 4951 00ae 1749     		ldr	r1, .L361
+ 4952              	.LVL434:
+ 4953              		.loc 1 2184 7 is_stmt 0 view .LVU1554
+ 4954 00b0 8A68     		ldr	r2, [r1, #8]
+ 4955 00b2 22F46042 		bic	r2, r2, #57344
+ 4956 00b6 8A60     		str	r2, [r1, #8]
+2185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /* Parameters that can be updated only when ADC is disabled:                */
+2187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*  - Multimode mode selection                                              */
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       /*  - Multimode delay                                                       */
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ 4957              		.loc 1 2189 7 is_stmt 1 view .LVU1555
+ 4958              	.LVL435:
+ 4959              	.LBB484:
+ 4960              	.LBI484:
+ARM GAS  /tmp/cc3JIfda.s 			page 282
+
+
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4961              		.loc 2 6729 26 view .LVU1556
+ 4962              	.LBB485:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4963              		.loc 2 6731 3 view .LVU1557
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4964              		.loc 2 6731 12 is_stmt 0 view .LVU1558
+ 4965 00b8 4FF0A042 		mov	r2, #1342177280
+ 4966 00bc 9168     		ldr	r1, [r2, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4967              		.loc 2 6731 68 view .LVU1559
+ 4968 00be 11F00101 		ands	r1, r1, #1
+ 4969 00c2 00D0     		beq	.L350
+ 4970 00c4 0121     		movs	r1, #1
+ 4971              	.L350:
+ 4972              	.LVL436:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4973              		.loc 2 6731 68 view .LVU1560
+ 4974              	.LBE485:
+ 4975              	.LBE484:
+ 4976              	.LBB486:
+ 4977              	.LBI486:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 4978              		.loc 2 6729 26 is_stmt 1 view .LVU1561
+ 4979              	.LBB487:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4980              		.loc 2 6731 3 view .LVU1562
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4981              		.loc 2 6731 12 is_stmt 0 view .LVU1563
+ 4982 00c6 124A     		ldr	r2, .L361+4
+ 4983 00c8 9268     		ldr	r2, [r2, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4984              		.loc 2 6731 68 view .LVU1564
+ 4985 00ca 12F00102 		ands	r2, r2, #1
+ 4986 00ce 00D0     		beq	.L351
+ 4987 00d0 0122     		movs	r2, #1
+ 4988              	.L351:
+ 4989              	.LVL437:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 4990              		.loc 2 6731 68 view .LVU1565
+ 4991              	.LBE487:
+ 4992              	.LBE486:
+ 4993              		.loc 1 2189 10 view .LVU1566
+ 4994 00d2 0A43     		orrs	r2, r2, r1
+ 4995 00d4 16D1     		bne	.L354
+2190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       {
+2191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****         CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
+ 4996              		.loc 1 2191 9 is_stmt 1 view .LVU1567
+ 4997 00d6 0D49     		ldr	r1, .L361
+ 4998 00d8 8A68     		ldr	r2, [r1, #8]
+ 4999 00da 22F47162 		bic	r2, r2, #3856
+ 5000 00de 22F00F02 		bic	r2, r2, #15
+ 5001 00e2 8A60     		str	r2, [r1, #8]
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ADC_Common_TypeDef *tmpADC_Common;
+ 5002              		.loc 1 2107 21 is_stmt 0 view .LVU1568
+ 5003 00e4 0020     		movs	r0, #0
+ 5004 00e6 04E0     		b	.L349
+ARM GAS  /tmp/cc3JIfda.s 			page 283
+
+
+ 5005              	.LVL438:
+ 5006              	.L345:
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       }
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     }
+2194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* If one of the ADC sharing the same common group is enabled, no update    */
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* could be done on neither of the multimode structure parameters.          */
+2197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+2198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Update ADC state machine to error */
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 5007              		.loc 1 2200 5 is_stmt 1 view .LVU1569
+ 5008 00e8 DA6D     		ldr	r2, [r3, #92]
+ 5009              	.LVL439:
+ 5010              		.loc 1 2200 5 is_stmt 0 view .LVU1570
+ 5011 00ea 42F02002 		orr	r2, r2, #32
+ 5012 00ee DA65     		str	r2, [r3, #92]
+2201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_ERROR;
+ 5013              		.loc 1 2202 5 is_stmt 1 view .LVU1571
+ 5014              	.LVL440:
+ 5015              		.loc 1 2202 20 is_stmt 0 view .LVU1572
+ 5016 00f0 0120     		movs	r0, #1
+ 5017              	.LVL441:
+ 5018              	.L349:
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Process unlocked */
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 5019              		.loc 1 2206 3 is_stmt 1 view .LVU1573
+ 5020              		.loc 1 2206 3 view .LVU1574
+ 5021 00f2 0022     		movs	r2, #0
+ 5022 00f4 83F85820 		strb	r2, [r3, #88]
+ 5023              		.loc 1 2206 3 view .LVU1575
+2207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Return function status */
+2209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 5024              		.loc 1 2209 3 view .LVU1576
+ 5025              	.LVL442:
+ 5026              	.L340:
+2210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 5027              		.loc 1 2210 1 is_stmt 0 view .LVU1577
+ 5028 00f8 1DB0     		add	sp, sp, #116
+ 5029              	.LCFI38:
+ 5030              		.cfi_remember_state
+ 5031              		.cfi_def_cfa_offset 4
+ 5032              		@ sp needed
+ 5033 00fa 5DF8044B 		ldr	r4, [sp], #4
+ 5034              	.LCFI39:
+ 5035              		.cfi_restore 4
+ 5036              		.cfi_def_cfa_offset 0
+ 5037 00fe 7047     		bx	lr
+ 5038              	.LVL443:
+ 5039              	.L353:
+ 5040              	.LCFI40:
+ 5041              		.cfi_restore_state
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ADC_Common_TypeDef *tmpADC_Common;
+ARM GAS  /tmp/cc3JIfda.s 			page 284
+
+
+ 5042              		.loc 1 2107 21 view .LVU1578
+ 5043 0100 0020     		movs	r0, #0
+ 5044 0102 F6E7     		b	.L349
+ 5045              	.LVL444:
+ 5046              	.L354:
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   ADC_Common_TypeDef *tmpADC_Common;
+ 5047              		.loc 1 2107 21 view .LVU1579
+ 5048 0104 0020     		movs	r0, #0
+ 5049 0106 F4E7     		b	.L349
+ 5050              	.LVL445:
+ 5051              	.L352:
+ 5052              	.LCFI41:
+ 5053              		.cfi_def_cfa_offset 0
+ 5054              		.cfi_restore 4
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+ 5055              		.loc 1 2122 3 view .LVU1580
+ 5056 0108 0220     		movs	r0, #2
+ 5057              	.LVL446:
+ 5058              		.loc 1 2210 1 view .LVU1581
+ 5059 010a 7047     		bx	lr
+ 5060              	.L362:
+ 5061              		.align	2
+ 5062              	.L361:
+ 5063 010c 00030050 		.word	1342178048
+ 5064 0110 00010050 		.word	1342177536
+ 5065              		.cfi_endproc
+ 5066              	.LFE351:
+ 5068              		.section	.text.HAL_ADCEx_EnableInjectedQueue,"ax",%progbits
+ 5069              		.align	1
+ 5070              		.global	HAL_ADCEx_EnableInjectedQueue
+ 5071              		.syntax unified
+ 5072              		.thumb
+ 5073              		.thumb_func
+ 5075              	HAL_ADCEx_EnableInjectedQueue:
+ 5076              	.LVL447:
+ 5077              	.LFB352:
+2211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** #endif /* ADC_MULTIMODE_SUPPORT */
+2212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+2214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Enable Injected Queue
+2215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   This function resets CFGR register JQDIS bit in order to enable the
+2216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+2217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         are both equal to 0 to ensure that no regular nor injected
+2218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         conversion is ongoing.
+2219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+2221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 5078              		.loc 1 2223 1 is_stmt 1 view -0
+ 5079              		.cfi_startproc
+ 5080              		@ args = 0, pretend = 0, frame = 0
+ 5081              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5082              		@ link register save eliminated.
+2224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 5083              		.loc 1 2224 3 view .LVU1583
+2225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+ARM GAS  /tmp/cc3JIfda.s 			page 285
+
+
+ 5084              		.loc 1 2225 3 view .LVU1584
+2226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_adc_is_conversion_on_going_injected;
+ 5085              		.loc 1 2226 3 view .LVU1585
+2227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+2229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 5086              		.loc 1 2229 3 view .LVU1586
+2230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ 5087              		.loc 1 2231 3 view .LVU1587
+ 5088              		.loc 1 2231 44 is_stmt 0 view .LVU1588
+ 5089 0000 0168     		ldr	r1, [r0]
+ 5090              	.LVL448:
+ 5091              	.LBB488:
+ 5092              	.LBI488:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5093              		.loc 2 6851 26 is_stmt 1 view .LVU1589
+ 5094              	.LBB489:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5095              		.loc 2 6853 3 view .LVU1590
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5096              		.loc 2 6853 12 is_stmt 0 view .LVU1591
+ 5097 0002 8B68     		ldr	r3, [r1, #8]
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5098              		.loc 2 6853 74 view .LVU1592
+ 5099 0004 13F00403 		ands	r3, r3, #4
+ 5100 0008 00D0     		beq	.L364
+ 5101 000a 0123     		movs	r3, #1
+ 5102              	.L364:
+ 5103              	.LVL449:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5104              		.loc 2 6853 74 view .LVU1593
+ 5105              	.LBE489:
+ 5106              	.LBE488:
+2232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 5107              		.loc 1 2232 3 is_stmt 1 view .LVU1594
+ 5108              	.LBB490:
+ 5109              	.LBI490:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5110              		.loc 2 7076 26 view .LVU1595
+ 5111              	.LBB491:
+ 5112              		.loc 2 7078 3 view .LVU1596
+ 5113              		.loc 2 7078 12 is_stmt 0 view .LVU1597
+ 5114 000c 8A68     		ldr	r2, [r1, #8]
+ 5115              		.loc 2 7078 76 view .LVU1598
+ 5116 000e 12F00802 		ands	r2, r2, #8
+ 5117 0012 00D0     		beq	.L365
+ 5118 0014 0122     		movs	r2, #1
+ 5119              	.L365:
+ 5120              	.LVL450:
+ 5121              		.loc 2 7078 76 view .LVU1599
+ 5122              	.LBE491:
+ 5123              	.LBE490:
+2233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Parameter can be set only if no conversion is on-going */
+2235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ 5124              		.loc 1 2235 3 is_stmt 1 view .LVU1600
+ARM GAS  /tmp/cc3JIfda.s 			page 286
+
+
+ 5125              		.loc 1 2235 6 is_stmt 0 view .LVU1601
+ 5126 0016 53B9     		cbnz	r3, .L367
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 5127              		.loc 1 2236 7 view .LVU1602
+ 5128 0018 5AB9     		cbnz	r2, .L368
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****      )
+2238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+ 5129              		.loc 1 2239 5 is_stmt 1 view .LVU1603
+ 5130 001a CB68     		ldr	r3, [r1, #12]
+ 5131              	.LVL451:
+ 5132              		.loc 1 2239 5 is_stmt 0 view .LVU1604
+ 5133 001c 23F00043 		bic	r3, r3, #-2147483648
+ 5134 0020 CB60     		str	r3, [r1, #12]
+2240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     /* Update state, clear previous result related to injected queue overflow */
+2242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+ 5135              		.loc 1 2242 5 is_stmt 1 view .LVU1605
+ 5136 0022 C36D     		ldr	r3, [r0, #92]
+ 5137 0024 23F48043 		bic	r3, r3, #16384
+ 5138 0028 C365     		str	r3, [r0, #92]
+2243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_OK;
+ 5139              		.loc 1 2244 5 view .LVU1606
+ 5140              	.LVL452:
+ 5141              		.loc 1 2244 20 is_stmt 0 view .LVU1607
+ 5142 002a 0020     		movs	r0, #0
+ 5143              	.LVL453:
+ 5144              		.loc 1 2244 20 view .LVU1608
+ 5145 002c 7047     		bx	lr
+ 5146              	.LVL454:
+ 5147              	.L367:
+2245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+2247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_ERROR;
+ 5148              		.loc 1 2248 20 view .LVU1609
+ 5149 002e 0120     		movs	r0, #1
+ 5150              	.LVL455:
+ 5151              		.loc 1 2248 20 view .LVU1610
+ 5152 0030 7047     		bx	lr
+ 5153              	.LVL456:
+ 5154              	.L368:
+ 5155              		.loc 1 2248 20 view .LVU1611
+ 5156 0032 0120     		movs	r0, #1
+ 5157              	.LVL457:
+2249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 5158              		.loc 1 2251 3 is_stmt 1 view .LVU1612
+2252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 5159              		.loc 1 2252 1 is_stmt 0 view .LVU1613
+ 5160 0034 7047     		bx	lr
+ 5161              		.cfi_endproc
+ 5162              	.LFE352:
+ 5164              		.section	.text.HAL_ADCEx_DisableInjectedQueue,"ax",%progbits
+ 5165              		.align	1
+ARM GAS  /tmp/cc3JIfda.s 			page 287
+
+
+ 5166              		.global	HAL_ADCEx_DisableInjectedQueue
+ 5167              		.syntax unified
+ 5168              		.thumb
+ 5169              		.thumb_func
+ 5171              	HAL_ADCEx_DisableInjectedQueue:
+ 5172              	.LVL458:
+ 5173              	.LFB353:
+2253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+2255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Disable Injected Queue
+2256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   This function sets CFGR register JQDIS bit in order to disable the
+2257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+2258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         are both equal to 0 to ensure that no regular nor injected
+2259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         conversion is ongoing.
+2260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+2261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+2262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+2263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
+2264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 5174              		.loc 1 2264 1 is_stmt 1 view -0
+ 5175              		.cfi_startproc
+ 5176              		@ args = 0, pretend = 0, frame = 0
+ 5177              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5178              		@ link register save eliminated.
+2265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 5179              		.loc 1 2265 3 view .LVU1615
+2266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_adc_is_conversion_on_going_regular;
+ 5180              		.loc 1 2266 3 view .LVU1616
+2267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   uint32_t tmp_adc_is_conversion_on_going_injected;
+ 5181              		.loc 1 2267 3 view .LVU1617
+2268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+2270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 5182              		.loc 1 2270 3 view .LVU1618
+2271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ 5183              		.loc 1 2272 3 view .LVU1619
+ 5184              		.loc 1 2272 44 is_stmt 0 view .LVU1620
+ 5185 0000 0168     		ldr	r1, [r0]
+ 5186              	.LVL459:
+ 5187              	.LBB492:
+ 5188              	.LBI492:
+6851:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5189              		.loc 2 6851 26 is_stmt 1 view .LVU1621
+ 5190              	.LBB493:
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5191              		.loc 2 6853 3 view .LVU1622
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5192              		.loc 2 6853 12 is_stmt 0 view .LVU1623
+ 5193 0002 8B68     		ldr	r3, [r1, #8]
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5194              		.loc 2 6853 74 view .LVU1624
+ 5195 0004 13F00403 		ands	r3, r3, #4
+ 5196 0008 00D0     		beq	.L370
+ 5197 000a 0123     		movs	r3, #1
+ 5198              	.L370:
+ 5199              	.LVL460:
+ARM GAS  /tmp/cc3JIfda.s 			page 288
+
+
+6853:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5200              		.loc 2 6853 74 view .LVU1625
+ 5201              	.LBE493:
+ 5202              	.LBE492:
+2273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 5203              		.loc 1 2273 3 is_stmt 1 view .LVU1626
+ 5204              	.LBB494:
+ 5205              	.LBI494:
+7076:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5206              		.loc 2 7076 26 view .LVU1627
+ 5207              	.LBB495:
+ 5208              		.loc 2 7078 3 view .LVU1628
+ 5209              		.loc 2 7078 12 is_stmt 0 view .LVU1629
+ 5210 000c 8A68     		ldr	r2, [r1, #8]
+ 5211              		.loc 2 7078 76 view .LVU1630
+ 5212 000e 12F00802 		ands	r2, r2, #8
+ 5213 0012 00D0     		beq	.L371
+ 5214 0014 0122     		movs	r2, #1
+ 5215              	.L371:
+ 5216              	.LVL461:
+ 5217              		.loc 2 7078 76 view .LVU1631
+ 5218              	.LBE495:
+ 5219              	.LBE494:
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Parameter can be set only if no conversion is on-going */
+2276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ 5220              		.loc 1 2276 3 is_stmt 1 view .LVU1632
+ 5221              		.loc 1 2276 6 is_stmt 0 view .LVU1633
+ 5222 0016 53B9     		cbnz	r3, .L373
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****       && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 5223              		.loc 1 2277 7 view .LVU1634
+ 5224 0018 5AB9     		cbnz	r2, .L374
+2278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****      )
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
+ 5225              		.loc 1 2280 5 is_stmt 1 view .LVU1635
+ 5226              	.LVL462:
+ 5227              	.LBB496:
+ 5228              	.LBI496:
+4904:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5229              		.loc 2 4904 22 view .LVU1636
+ 5230              	.LBB497:
+4906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5231              		.loc 2 4906 3 view .LVU1637
+ 5232 001a CB68     		ldr	r3, [r1, #12]
+ 5233              	.LVL463:
+4906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5234              		.loc 2 4906 3 is_stmt 0 view .LVU1638
+ 5235 001c 23F00043 		bic	r3, r3, #-2147483648
+ 5236 0020 23F40013 		bic	r3, r3, #2097152
+ 5237 0024 43F00043 		orr	r3, r3, #-2147483648
+ 5238 0028 CB60     		str	r3, [r1, #12]
+ 5239              	.LVL464:
+4906:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5240              		.loc 2 4906 3 view .LVU1639
+ 5241              	.LBE497:
+ 5242              	.LBE496:
+ARM GAS  /tmp/cc3JIfda.s 			page 289
+
+
+2281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_OK;
+ 5243              		.loc 1 2281 5 is_stmt 1 view .LVU1640
+ 5244              		.loc 1 2281 20 is_stmt 0 view .LVU1641
+ 5245 002a 0020     		movs	r0, #0
+ 5246              	.LVL465:
+ 5247              		.loc 1 2281 20 view .LVU1642
+ 5248 002c 7047     		bx	lr
+ 5249              	.LVL466:
+ 5250              	.L373:
+2282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+2284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_ERROR;
+ 5251              		.loc 1 2285 20 view .LVU1643
+ 5252 002e 0120     		movs	r0, #1
+ 5253              	.LVL467:
+ 5254              		.loc 1 2285 20 view .LVU1644
+ 5255 0030 7047     		bx	lr
+ 5256              	.LVL468:
+ 5257              	.L374:
+ 5258              		.loc 1 2285 20 view .LVU1645
+ 5259 0032 0120     		movs	r0, #1
+ 5260              	.LVL469:
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 5261              		.loc 1 2288 3 is_stmt 1 view .LVU1646
+2289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 5262              		.loc 1 2289 1 is_stmt 0 view .LVU1647
+ 5263 0034 7047     		bx	lr
+ 5264              		.cfi_endproc
+ 5265              	.LFE353:
+ 5267              		.section	.text.HAL_ADCEx_DisableVoltageRegulator,"ax",%progbits
+ 5268              		.align	1
+ 5269              		.global	HAL_ADCEx_DisableVoltageRegulator
+ 5270              		.syntax unified
+ 5271              		.thumb
+ 5272              		.thumb_func
+ 5274              	HAL_ADCEx_DisableVoltageRegulator:
+ 5275              	.LVL470:
+ 5276              	.LFB354:
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+2292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Disable ADC voltage regulator.
+2293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Disabling voltage regulator allows to save power. This operation can
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         be carried out only when ADC is disabled.
+2295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   To enable again the voltage regulator, the user is expected to
+2296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         resort to HAL_ADC_Init() API.
+2297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+2298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+2299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
+2301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 5277              		.loc 1 2301 1 is_stmt 1 view -0
+ 5278              		.cfi_startproc
+ 5279              		@ args = 0, pretend = 0, frame = 0
+ 5280              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cc3JIfda.s 			page 290
+
+
+ 5281              		@ link register save eliminated.
+2302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 5282              		.loc 1 2302 3 view .LVU1649
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+2305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 5283              		.loc 1 2305 3 view .LVU1650
+2306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+2308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ 5284              		.loc 1 2308 3 view .LVU1651
+ 5285              		.loc 1 2308 7 is_stmt 0 view .LVU1652
+ 5286 0000 0368     		ldr	r3, [r0]
+ 5287              	.LVL471:
+ 5288              	.LBB498:
+ 5289              	.LBI498:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5290              		.loc 2 6729 26 is_stmt 1 view .LVU1653
+ 5291              	.LBB499:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5292              		.loc 2 6731 3 view .LVU1654
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5293              		.loc 2 6731 12 is_stmt 0 view .LVU1655
+ 5294 0002 9A68     		ldr	r2, [r3, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5295              		.loc 2 6731 68 view .LVU1656
+ 5296 0004 12F0010F 		tst	r2, #1
+ 5297 0008 07D1     		bne	.L377
+ 5298              	.LVL472:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5299              		.loc 2 6731 68 view .LVU1657
+ 5300              	.LBE499:
+ 5301              	.LBE498:
+2309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     LL_ADC_DisableInternalRegulator(hadc->Instance);
+ 5302              		.loc 1 2310 5 is_stmt 1 view .LVU1658
+ 5303              	.LBB500:
+ 5304              	.LBI500:
+6658:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5305              		.loc 2 6658 22 view .LVU1659
+ 5306              	.LBB501:
+6660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5307              		.loc 2 6660 3 view .LVU1660
+ 5308 000a 9A68     		ldr	r2, [r3, #8]
+ 5309 000c 22F01042 		bic	r2, r2, #-1879048192
+ 5310 0010 22F03F02 		bic	r2, r2, #63
+ 5311 0014 9A60     		str	r2, [r3, #8]
+ 5312              	.LVL473:
+6660:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5313              		.loc 2 6660 3 is_stmt 0 view .LVU1661
+ 5314              	.LBE501:
+ 5315              	.LBE500:
+2311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_OK;
+ 5316              		.loc 1 2311 5 is_stmt 1 view .LVU1662
+ 5317              		.loc 1 2311 20 is_stmt 0 view .LVU1663
+ 5318 0016 0020     		movs	r0, #0
+ 5319              	.LVL474:
+ARM GAS  /tmp/cc3JIfda.s 			page 291
+
+
+ 5320              		.loc 1 2311 20 view .LVU1664
+ 5321 0018 7047     		bx	lr
+ 5322              	.LVL475:
+ 5323              	.L377:
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+2314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_ERROR;
+ 5324              		.loc 1 2315 20 view .LVU1665
+ 5325 001a 0120     		movs	r0, #1
+ 5326              	.LVL476:
+2316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 5327              		.loc 1 2318 3 is_stmt 1 view .LVU1666
+2319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 5328              		.loc 1 2319 1 is_stmt 0 view .LVU1667
+ 5329 001c 7047     		bx	lr
+ 5330              		.cfi_endproc
+ 5331              	.LFE354:
+ 5333              		.section	.text.HAL_ADCEx_EnterADCDeepPowerDownMode,"ax",%progbits
+ 5334              		.align	1
+ 5335              		.global	HAL_ADCEx_EnterADCDeepPowerDownMode
+ 5336              		.syntax unified
+ 5337              		.thumb
+ 5338              		.thumb_func
+ 5340              	HAL_ADCEx_EnterADCDeepPowerDownMode:
+ 5341              	.LVL477:
+ 5342              	.LFB355:
+2320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** /**
+2322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @brief  Enter ADC deep-power-down mode
+2323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   This mode is achieved in setting DEEPPWD bit and allows to save power
+2324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         in reducing leakage currents. It is particularly interesting before
+2325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         entering stop modes.
+2326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   Setting DEEPPWD automatically clears ADVREGEN bit and disables the
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         ADC voltage regulator. This means that this API encompasses
+2328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
+2329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         calibration is lost.
+2330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @note   To exit the ADC deep-power-down mode, the user is expected to
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         resort to HAL_ADC_Init() API as well as to relaunch a calibration
+2332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
+2333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   *         saved calibration factor.
+2334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @param hadc ADC handle
+2335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   * @retval HAL status
+2336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   */
+2337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
+2338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** {
+ 5343              		.loc 1 2338 1 is_stmt 1 view -0
+ 5344              		.cfi_startproc
+ 5345              		@ args = 0, pretend = 0, frame = 0
+ 5346              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5347              		@ link register save eliminated.
+2339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status;
+ 5348              		.loc 1 2339 3 view .LVU1669
+2340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Check the parameters */
+ARM GAS  /tmp/cc3JIfda.s 			page 292
+
+
+2342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 5349              		.loc 1 2342 3 view .LVU1670
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+2345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ 5350              		.loc 1 2345 3 view .LVU1671
+ 5351              		.loc 1 2345 7 is_stmt 0 view .LVU1672
+ 5352 0000 0268     		ldr	r2, [r0]
+ 5353              	.LVL478:
+ 5354              	.LBB502:
+ 5355              	.LBI502:
+6729:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5356              		.loc 2 6729 26 is_stmt 1 view .LVU1673
+ 5357              	.LBB503:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5358              		.loc 2 6731 3 view .LVU1674
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5359              		.loc 2 6731 12 is_stmt 0 view .LVU1675
+ 5360 0002 9368     		ldr	r3, [r2, #8]
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5361              		.loc 2 6731 68 view .LVU1676
+ 5362 0004 13F0010F 		tst	r3, #1
+ 5363 0008 09D1     		bne	.L380
+ 5364              	.LVL479:
+6731:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** }
+ 5365              		.loc 2 6731 68 view .LVU1677
+ 5366              	.LBE503:
+ 5367              	.LBE502:
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     LL_ADC_EnableDeepPowerDown(hadc->Instance);
+ 5368              		.loc 1 2347 5 is_stmt 1 view .LVU1678
+ 5369              	.LBB504:
+ 5370              	.LBI504:
+6583:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h **** {
+ 5371              		.loc 2 6583 22 view .LVU1679
+ 5372              	.LBB505:
+6588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 5373              		.loc 2 6588 3 view .LVU1680
+ 5374 000a 9368     		ldr	r3, [r2, #8]
+ 5375 000c 23F02043 		bic	r3, r3, #-1610612736
+ 5376 0010 23F03F03 		bic	r3, r3, #63
+ 5377 0014 43F00053 		orr	r3, r3, #536870912
+ 5378 0018 9360     		str	r3, [r2, #8]
+ 5379              	.LVL480:
+6588:Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ****              ADC_CR_BITS_PROPERTY_RS,
+ 5380              		.loc 2 6588 3 is_stmt 0 view .LVU1681
+ 5381              	.LBE505:
+ 5382              	.LBE504:
+2348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_OK;
+ 5383              		.loc 1 2348 5 is_stmt 1 view .LVU1682
+ 5384              		.loc 1 2348 20 is_stmt 0 view .LVU1683
+ 5385 001a 0020     		movs	r0, #0
+ 5386              	.LVL481:
+ 5387              		.loc 1 2348 20 view .LVU1684
+ 5388 001c 7047     		bx	lr
+ 5389              	.LVL482:
+ 5390              	.L380:
+ARM GAS  /tmp/cc3JIfda.s 			page 293
+
+
+2349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   else
+2351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   {
+2352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****     tmp_hal_status = HAL_ERROR;
+ 5391              		.loc 1 2352 20 view .LVU1685
+ 5392 001e 0120     		movs	r0, #1
+ 5393              	.LVL483:
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   }
+2354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** 
+2355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 5394              		.loc 1 2355 3 is_stmt 1 view .LVU1686
+2356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c **** }
+ 5395              		.loc 1 2356 1 is_stmt 0 view .LVU1687
+ 5396 0020 7047     		bx	lr
+ 5397              		.cfi_endproc
+ 5398              	.LFE355:
+ 5400              		.text
+ 5401              	.Letext0:
+ 5402              		.file 4 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 5403              		.file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 5404              		.file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 5405              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 5406              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 5407              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h"
+ 5408              		.file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h"
+ 5409              		.file 11 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
+ 5410              		.file 12 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ARM GAS  /tmp/cc3JIfda.s 			page 294
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_adc_ex.c
+     /tmp/cc3JIfda.s:21     .text.LL_ADC_SetCalibrationFactor:00000000 $t
+     /tmp/cc3JIfda.s:26     .text.LL_ADC_SetCalibrationFactor:00000000 LL_ADC_SetCalibrationFactor
+     /tmp/cc3JIfda.s:54     .text.LL_ADC_SetChannelSamplingTime:00000000 $t
+     /tmp/cc3JIfda.s:59     .text.LL_ADC_SetChannelSamplingTime:00000000 LL_ADC_SetChannelSamplingTime
+     /tmp/cc3JIfda.s:104    .text.HAL_ADCEx_Calibration_Start:00000000 $t
+     /tmp/cc3JIfda.s:110    .text.HAL_ADCEx_Calibration_Start:00000000 HAL_ADCEx_Calibration_Start
+     /tmp/cc3JIfda.s:270    .text.HAL_ADCEx_Calibration_Start:00000098 $d
+     /tmp/cc3JIfda.s:275    .text.HAL_ADCEx_Calibration_GetValue:00000000 $t
+     /tmp/cc3JIfda.s:281    .text.HAL_ADCEx_Calibration_GetValue:00000000 HAL_ADCEx_Calibration_GetValue
+     /tmp/cc3JIfda.s:322    .text.HAL_ADCEx_Calibration_SetValue:00000000 $t
+     /tmp/cc3JIfda.s:328    .text.HAL_ADCEx_Calibration_SetValue:00000000 HAL_ADCEx_Calibration_SetValue
+     /tmp/cc3JIfda.s:467    .text.HAL_ADCEx_InjectedStart:00000000 $t
+     /tmp/cc3JIfda.s:473    .text.HAL_ADCEx_InjectedStart:00000000 HAL_ADCEx_InjectedStart
+     /tmp/cc3JIfda.s:715    .text.HAL_ADCEx_InjectedStart:000000e8 $d
+     /tmp/cc3JIfda.s:721    .text.HAL_ADCEx_InjectedStop:00000000 $t
+     /tmp/cc3JIfda.s:727    .text.HAL_ADCEx_InjectedStop:00000000 HAL_ADCEx_InjectedStop
+     /tmp/cc3JIfda.s:827    .text.HAL_ADCEx_InjectedPollForConversion:00000000 $t
+     /tmp/cc3JIfda.s:833    .text.HAL_ADCEx_InjectedPollForConversion:00000000 HAL_ADCEx_InjectedPollForConversion
+     /tmp/cc3JIfda.s:1118   .text.HAL_ADCEx_InjectedPollForConversion:000000f8 $d
+     /tmp/cc3JIfda.s:1124   .text.HAL_ADCEx_InjectedStart_IT:00000000 $t
+     /tmp/cc3JIfda.s:1130   .text.HAL_ADCEx_InjectedStart_IT:00000000 HAL_ADCEx_InjectedStart_IT
+     /tmp/cc3JIfda.s:1416   .text.HAL_ADCEx_InjectedStart_IT:0000012c $d
+     /tmp/cc3JIfda.s:1422   .text.HAL_ADCEx_InjectedStop_IT:00000000 $t
+     /tmp/cc3JIfda.s:1428   .text.HAL_ADCEx_InjectedStop_IT:00000000 HAL_ADCEx_InjectedStop_IT
+     /tmp/cc3JIfda.s:1533   .text.HAL_ADCEx_MultiModeStart_DMA:00000000 $t
+     /tmp/cc3JIfda.s:1539   .text.HAL_ADCEx_MultiModeStart_DMA:00000000 HAL_ADCEx_MultiModeStart_DMA
+     /tmp/cc3JIfda.s:1757   .text.HAL_ADCEx_MultiModeStart_DMA:000000d0 $d
+     /tmp/cc3JIfda.s:1765   .text.HAL_ADCEx_MultiModeStop_DMA:00000000 $t
+     /tmp/cc3JIfda.s:1771   .text.HAL_ADCEx_MultiModeStop_DMA:00000000 HAL_ADCEx_MultiModeStop_DMA
+     /tmp/cc3JIfda.s:2105   .text.HAL_ADCEx_MultiModeGetValue:00000000 $t
+     /tmp/cc3JIfda.s:2111   .text.HAL_ADCEx_MultiModeGetValue:00000000 HAL_ADCEx_MultiModeGetValue
+     /tmp/cc3JIfda.s:2133   .text.HAL_ADCEx_MultiModeGetValue:00000008 $d
+     /tmp/cc3JIfda.s:2138   .text.HAL_ADCEx_InjectedGetValue:00000000 $t
+     /tmp/cc3JIfda.s:2144   .text.HAL_ADCEx_InjectedGetValue:00000000 HAL_ADCEx_InjectedGetValue
+     /tmp/cc3JIfda.s:2209   .text.HAL_ADCEx_InjectedConvCpltCallback:00000000 $t
+     /tmp/cc3JIfda.s:2215   .text.HAL_ADCEx_InjectedConvCpltCallback:00000000 HAL_ADCEx_InjectedConvCpltCallback
+     /tmp/cc3JIfda.s:2230   .text.HAL_ADCEx_InjectedQueueOverflowCallback:00000000 $t
+     /tmp/cc3JIfda.s:2236   .text.HAL_ADCEx_InjectedQueueOverflowCallback:00000000 HAL_ADCEx_InjectedQueueOverflowCallback
+     /tmp/cc3JIfda.s:2251   .text.HAL_ADCEx_LevelOutOfWindow2Callback:00000000 $t
+     /tmp/cc3JIfda.s:2257   .text.HAL_ADCEx_LevelOutOfWindow2Callback:00000000 HAL_ADCEx_LevelOutOfWindow2Callback
+     /tmp/cc3JIfda.s:2272   .text.HAL_ADCEx_LevelOutOfWindow3Callback:00000000 $t
+     /tmp/cc3JIfda.s:2278   .text.HAL_ADCEx_LevelOutOfWindow3Callback:00000000 HAL_ADCEx_LevelOutOfWindow3Callback
+     /tmp/cc3JIfda.s:2293   .text.HAL_ADCEx_EndOfSamplingCallback:00000000 $t
+     /tmp/cc3JIfda.s:2299   .text.HAL_ADCEx_EndOfSamplingCallback:00000000 HAL_ADCEx_EndOfSamplingCallback
+     /tmp/cc3JIfda.s:2314   .text.HAL_ADCEx_RegularStop:00000000 $t
+     /tmp/cc3JIfda.s:2320   .text.HAL_ADCEx_RegularStop:00000000 HAL_ADCEx_RegularStop
+     /tmp/cc3JIfda.s:2423   .text.HAL_ADCEx_RegularStop_IT:00000000 $t
+     /tmp/cc3JIfda.s:2429   .text.HAL_ADCEx_RegularStop_IT:00000000 HAL_ADCEx_RegularStop_IT
+     /tmp/cc3JIfda.s:2537   .text.HAL_ADCEx_RegularStop_DMA:00000000 $t
+     /tmp/cc3JIfda.s:2543   .text.HAL_ADCEx_RegularStop_DMA:00000000 HAL_ADCEx_RegularStop_DMA
+     /tmp/cc3JIfda.s:2692   .text.HAL_ADCEx_RegularMultiModeStop_DMA:00000000 $t
+     /tmp/cc3JIfda.s:2698   .text.HAL_ADCEx_RegularMultiModeStop_DMA:00000000 HAL_ADCEx_RegularMultiModeStop_DMA
+     /tmp/cc3JIfda.s:3053   .text.HAL_ADCEx_InjectedConfigChannel:00000000 $t
+     /tmp/cc3JIfda.s:3059   .text.HAL_ADCEx_InjectedConfigChannel:00000000 HAL_ADCEx_InjectedConfigChannel
+     /tmp/cc3JIfda.s:4150   .text.HAL_ADCEx_InjectedConfigChannel:0000039c $d
+ARM GAS  /tmp/cc3JIfda.s 			page 295
+
+
+     /tmp/cc3JIfda.s:4164   .text.HAL_ADCEx_InjectedConfigChannel:000003bc $t
+     /tmp/cc3JIfda.s:4749   .text.HAL_ADCEx_InjectedConfigChannel:000005b0 $d
+     /tmp/cc3JIfda.s:4757   .text.HAL_ADCEx_MultiModeConfigChannel:00000000 $t
+     /tmp/cc3JIfda.s:4763   .text.HAL_ADCEx_MultiModeConfigChannel:00000000 HAL_ADCEx_MultiModeConfigChannel
+     /tmp/cc3JIfda.s:5063   .text.HAL_ADCEx_MultiModeConfigChannel:0000010c $d
+     /tmp/cc3JIfda.s:5069   .text.HAL_ADCEx_EnableInjectedQueue:00000000 $t
+     /tmp/cc3JIfda.s:5075   .text.HAL_ADCEx_EnableInjectedQueue:00000000 HAL_ADCEx_EnableInjectedQueue
+     /tmp/cc3JIfda.s:5165   .text.HAL_ADCEx_DisableInjectedQueue:00000000 $t
+     /tmp/cc3JIfda.s:5171   .text.HAL_ADCEx_DisableInjectedQueue:00000000 HAL_ADCEx_DisableInjectedQueue
+     /tmp/cc3JIfda.s:5268   .text.HAL_ADCEx_DisableVoltageRegulator:00000000 $t
+     /tmp/cc3JIfda.s:5274   .text.HAL_ADCEx_DisableVoltageRegulator:00000000 HAL_ADCEx_DisableVoltageRegulator
+     /tmp/cc3JIfda.s:5334   .text.HAL_ADCEx_EnterADCDeepPowerDownMode:00000000 $t
+     /tmp/cc3JIfda.s:5340   .text.HAL_ADCEx_EnterADCDeepPowerDownMode:00000000 HAL_ADCEx_EnterADCDeepPowerDownMode
+
+UNDEFINED SYMBOLS
+ADC_Disable
+ADC_Enable
+ADC_ConversionStop
+HAL_GetTick
+HAL_DMA_Start_IT
+ADC_DMAConvCplt
+ADC_DMAHalfConvCplt
+ADC_DMAError
+HAL_DMA_Abort
+SystemCoreClock
diff --git a/squeow_sw/build/stm32g4xx_hal_adc_ex.o b/squeow_sw/build/stm32g4xx_hal_adc_ex.o
new file mode 100644
index 0000000000000000000000000000000000000000..db2bd398fdf40a2749ba8bdbd31adc0b4f093e01
GIT binary patch
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diff --git a/squeow_sw/build/stm32g4xx_hal_cortex.d b/squeow_sw/build/stm32g4xx_hal_cortex.d
new file mode 100644
index 0000000..129f1ad
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_cortex.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_cortex.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_cortex.lst b/squeow_sw/build/stm32g4xx_hal_cortex.lst
new file mode 100644
index 0000000..85879c4
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_cortex.lst
@@ -0,0 +1,5185 @@
+ARM GAS  /tmp/ccVsbRnC.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_cortex.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c"
+  20              		.section	.text.__NVIC_EnableIRQ,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	__NVIC_EnableIRQ:
+  27              	.LVL0:
+  28              	.LFB106:
+  29              		.file 2 "Drivers/CMSIS/Include/core_cm4.h"
+   1:Drivers/CMSIS/Include/core_cm4.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/core_cm4.h ****  * @file     core_cm4.h
+   3:Drivers/CMSIS/Include/core_cm4.h ****  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+   4:Drivers/CMSIS/Include/core_cm4.h ****  * @version  V5.1.0
+   5:Drivers/CMSIS/Include/core_cm4.h ****  * @date     13. March 2019
+   6:Drivers/CMSIS/Include/core_cm4.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/core_cm4.h **** /*
+   8:Drivers/CMSIS/Include/core_cm4.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/core_cm4.h ****  *
+  10:Drivers/CMSIS/Include/core_cm4.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/core_cm4.h ****  *
+  12:Drivers/CMSIS/Include/core_cm4.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/core_cm4.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/core_cm4.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/core_cm4.h ****  *
+  16:Drivers/CMSIS/Include/core_cm4.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/core_cm4.h ****  *
+  18:Drivers/CMSIS/Include/core_cm4.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/core_cm4.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/core_cm4.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/core_cm4.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/core_cm4.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/core_cm4.h ****  */
+  24:Drivers/CMSIS/Include/core_cm4.h **** 
+  25:Drivers/CMSIS/Include/core_cm4.h **** #if   defined ( __ICCARM__ )
+  26:Drivers/CMSIS/Include/core_cm4.h ****   #pragma system_include         /* treat file as system include file for MISRA check */
+  27:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__clang__)
+  28:Drivers/CMSIS/Include/core_cm4.h ****   #pragma clang system_header   /* treat file as system include file */
+  29:Drivers/CMSIS/Include/core_cm4.h **** #endif
+ARM GAS  /tmp/ccVsbRnC.s 			page 2
+
+
+  30:Drivers/CMSIS/Include/core_cm4.h **** 
+  31:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_GENERIC
+  32:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_GENERIC
+  33:Drivers/CMSIS/Include/core_cm4.h **** 
+  34:Drivers/CMSIS/Include/core_cm4.h **** #include <stdint.h>
+  35:Drivers/CMSIS/Include/core_cm4.h **** 
+  36:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus
+  37:Drivers/CMSIS/Include/core_cm4.h ****  extern "C" {
+  38:Drivers/CMSIS/Include/core_cm4.h **** #endif
+  39:Drivers/CMSIS/Include/core_cm4.h **** 
+  40:Drivers/CMSIS/Include/core_cm4.h **** /**
+  41:Drivers/CMSIS/Include/core_cm4.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  42:Drivers/CMSIS/Include/core_cm4.h ****   CMSIS violates the following MISRA-C:2004 rules:
+  43:Drivers/CMSIS/Include/core_cm4.h **** 
+  44:Drivers/CMSIS/Include/core_cm4.h ****    \li Required Rule 8.5, object/function definition in header file.<br>
+  45:Drivers/CMSIS/Include/core_cm4.h ****      Function definitions in header files are used to allow 'inlining'.
+  46:Drivers/CMSIS/Include/core_cm4.h **** 
+  47:Drivers/CMSIS/Include/core_cm4.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+  48:Drivers/CMSIS/Include/core_cm4.h ****      Unions are used for effective representation of core registers.
+  49:Drivers/CMSIS/Include/core_cm4.h **** 
+  50:Drivers/CMSIS/Include/core_cm4.h ****    \li Advisory Rule 19.7, Function-like macro defined.<br>
+  51:Drivers/CMSIS/Include/core_cm4.h ****      Function-like macros are used to allow more efficient code.
+  52:Drivers/CMSIS/Include/core_cm4.h ****  */
+  53:Drivers/CMSIS/Include/core_cm4.h **** 
+  54:Drivers/CMSIS/Include/core_cm4.h **** 
+  55:Drivers/CMSIS/Include/core_cm4.h **** /*******************************************************************************
+  56:Drivers/CMSIS/Include/core_cm4.h ****  *                 CMSIS definitions
+  57:Drivers/CMSIS/Include/core_cm4.h ****  ******************************************************************************/
+  58:Drivers/CMSIS/Include/core_cm4.h **** /**
+  59:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup Cortex_M4
+  60:Drivers/CMSIS/Include/core_cm4.h ****   @{
+  61:Drivers/CMSIS/Include/core_cm4.h ****  */
+  62:Drivers/CMSIS/Include/core_cm4.h **** 
+  63:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_version.h"
+  64:Drivers/CMSIS/Include/core_cm4.h **** 
+  65:Drivers/CMSIS/Include/core_cm4.h **** /* CMSIS CM4 definitions */
+  66:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] C
+  67:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  C
+  68:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+  69:Drivers/CMSIS/Include/core_cm4.h ****                                     __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL
+  70:Drivers/CMSIS/Include/core_cm4.h **** 
+  71:Drivers/CMSIS/Include/core_cm4.h **** #define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+  72:Drivers/CMSIS/Include/core_cm4.h **** 
+  73:Drivers/CMSIS/Include/core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not.
+  74:Drivers/CMSIS/Include/core_cm4.h ****     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun
+  75:Drivers/CMSIS/Include/core_cm4.h **** */
+  76:Drivers/CMSIS/Include/core_cm4.h **** #if defined ( __CC_ARM )
+  77:Drivers/CMSIS/Include/core_cm4.h ****   #if defined __TARGET_FPU_VFP
+  78:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+  79:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
+  80:Drivers/CMSIS/Include/core_cm4.h ****     #else
+  81:Drivers/CMSIS/Include/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+  82:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
+  83:Drivers/CMSIS/Include/core_cm4.h ****     #endif
+  84:Drivers/CMSIS/Include/core_cm4.h ****   #else
+  85:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
+  86:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+ARM GAS  /tmp/ccVsbRnC.s 			page 3
+
+
+  87:Drivers/CMSIS/Include/core_cm4.h **** 
+  88:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  89:Drivers/CMSIS/Include/core_cm4.h ****   #if defined __ARM_FP
+  90:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+  91:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
+  92:Drivers/CMSIS/Include/core_cm4.h ****     #else
+  93:Drivers/CMSIS/Include/core_cm4.h ****       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN
+  94:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
+  95:Drivers/CMSIS/Include/core_cm4.h ****     #endif
+  96:Drivers/CMSIS/Include/core_cm4.h ****   #else
+  97:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
+  98:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+  99:Drivers/CMSIS/Include/core_cm4.h **** 
+ 100:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __GNUC__ )
+ 101:Drivers/CMSIS/Include/core_cm4.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ 102:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 103:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
+ 104:Drivers/CMSIS/Include/core_cm4.h ****     #else
+ 105:Drivers/CMSIS/Include/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 106:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
+ 107:Drivers/CMSIS/Include/core_cm4.h ****     #endif
+ 108:Drivers/CMSIS/Include/core_cm4.h ****   #else
+ 109:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
+ 110:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+ 111:Drivers/CMSIS/Include/core_cm4.h **** 
+ 112:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __ICCARM__ )
+ 113:Drivers/CMSIS/Include/core_cm4.h ****   #if defined __ARMVFP__
+ 114:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 115:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
+ 116:Drivers/CMSIS/Include/core_cm4.h ****     #else
+ 117:Drivers/CMSIS/Include/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 118:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
+ 119:Drivers/CMSIS/Include/core_cm4.h ****     #endif
+ 120:Drivers/CMSIS/Include/core_cm4.h ****   #else
+ 121:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
+ 122:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+ 123:Drivers/CMSIS/Include/core_cm4.h **** 
+ 124:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TI_ARM__ )
+ 125:Drivers/CMSIS/Include/core_cm4.h ****   #if defined __TI_VFP_SUPPORT__
+ 126:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 127:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
+ 128:Drivers/CMSIS/Include/core_cm4.h ****     #else
+ 129:Drivers/CMSIS/Include/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 130:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
+ 131:Drivers/CMSIS/Include/core_cm4.h ****     #endif
+ 132:Drivers/CMSIS/Include/core_cm4.h ****   #else
+ 133:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
+ 134:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+ 135:Drivers/CMSIS/Include/core_cm4.h **** 
+ 136:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TASKING__ )
+ 137:Drivers/CMSIS/Include/core_cm4.h ****   #if defined __FPU_VFP__
+ 138:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 139:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
+ 140:Drivers/CMSIS/Include/core_cm4.h ****     #else
+ 141:Drivers/CMSIS/Include/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 142:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
+ 143:Drivers/CMSIS/Include/core_cm4.h ****     #endif
+ARM GAS  /tmp/ccVsbRnC.s 			page 4
+
+
+ 144:Drivers/CMSIS/Include/core_cm4.h ****   #else
+ 145:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
+ 146:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+ 147:Drivers/CMSIS/Include/core_cm4.h **** 
+ 148:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __CSMC__ )
+ 149:Drivers/CMSIS/Include/core_cm4.h ****   #if ( __CSMC__ & 0x400U)
+ 150:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 151:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
+ 152:Drivers/CMSIS/Include/core_cm4.h ****     #else
+ 153:Drivers/CMSIS/Include/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 154:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
+ 155:Drivers/CMSIS/Include/core_cm4.h ****     #endif
+ 156:Drivers/CMSIS/Include/core_cm4.h ****   #else
+ 157:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
+ 158:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+ 159:Drivers/CMSIS/Include/core_cm4.h **** 
+ 160:Drivers/CMSIS/Include/core_cm4.h **** #endif
+ 161:Drivers/CMSIS/Include/core_cm4.h **** 
+ 162:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+ 163:Drivers/CMSIS/Include/core_cm4.h **** 
+ 164:Drivers/CMSIS/Include/core_cm4.h **** 
+ 165:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus
+ 166:Drivers/CMSIS/Include/core_cm4.h **** }
+ 167:Drivers/CMSIS/Include/core_cm4.h **** #endif
+ 168:Drivers/CMSIS/Include/core_cm4.h **** 
+ 169:Drivers/CMSIS/Include/core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */
+ 170:Drivers/CMSIS/Include/core_cm4.h **** 
+ 171:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CMSIS_GENERIC
+ 172:Drivers/CMSIS/Include/core_cm4.h **** 
+ 173:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT
+ 174:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_DEPENDANT
+ 175:Drivers/CMSIS/Include/core_cm4.h **** 
+ 176:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus
+ 177:Drivers/CMSIS/Include/core_cm4.h ****  extern "C" {
+ 178:Drivers/CMSIS/Include/core_cm4.h **** #endif
+ 179:Drivers/CMSIS/Include/core_cm4.h **** 
+ 180:Drivers/CMSIS/Include/core_cm4.h **** /* check device defines and use defaults */
+ 181:Drivers/CMSIS/Include/core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES
+ 182:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef __CM4_REV
+ 183:Drivers/CMSIS/Include/core_cm4.h ****     #define __CM4_REV               0x0000U
+ 184:Drivers/CMSIS/Include/core_cm4.h ****     #warning "__CM4_REV not defined in device header file; using default!"
+ 185:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+ 186:Drivers/CMSIS/Include/core_cm4.h **** 
+ 187:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef __FPU_PRESENT
+ 188:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_PRESENT             0U
+ 189:Drivers/CMSIS/Include/core_cm4.h ****     #warning "__FPU_PRESENT not defined in device header file; using default!"
+ 190:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+ 191:Drivers/CMSIS/Include/core_cm4.h **** 
+ 192:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef __MPU_PRESENT
+ 193:Drivers/CMSIS/Include/core_cm4.h ****     #define __MPU_PRESENT             0U
+ 194:Drivers/CMSIS/Include/core_cm4.h ****     #warning "__MPU_PRESENT not defined in device header file; using default!"
+ 195:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+ 196:Drivers/CMSIS/Include/core_cm4.h **** 
+ 197:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef __NVIC_PRIO_BITS
+ 198:Drivers/CMSIS/Include/core_cm4.h ****     #define __NVIC_PRIO_BITS          3U
+ 199:Drivers/CMSIS/Include/core_cm4.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ 200:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+ARM GAS  /tmp/ccVsbRnC.s 			page 5
+
+
+ 201:Drivers/CMSIS/Include/core_cm4.h **** 
+ 202:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef __Vendor_SysTickConfig
+ 203:Drivers/CMSIS/Include/core_cm4.h ****     #define __Vendor_SysTickConfig    0U
+ 204:Drivers/CMSIS/Include/core_cm4.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ 205:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+ 206:Drivers/CMSIS/Include/core_cm4.h **** #endif
+ 207:Drivers/CMSIS/Include/core_cm4.h **** 
+ 208:Drivers/CMSIS/Include/core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */
+ 209:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 210:Drivers/CMSIS/Include/core_cm4.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
+ 211:Drivers/CMSIS/Include/core_cm4.h **** 
+ 212:Drivers/CMSIS/Include/core_cm4.h ****     <strong>IO Type Qualifiers</strong> are used
+ 213:Drivers/CMSIS/Include/core_cm4.h ****     \li to specify the access to peripheral variables.
+ 214:Drivers/CMSIS/Include/core_cm4.h ****     \li for automatic generation of peripheral register debug information.
+ 215:Drivers/CMSIS/Include/core_cm4.h **** */
+ 216:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus
+ 217:Drivers/CMSIS/Include/core_cm4.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
+ 218:Drivers/CMSIS/Include/core_cm4.h **** #else
+ 219:Drivers/CMSIS/Include/core_cm4.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
+ 220:Drivers/CMSIS/Include/core_cm4.h **** #endif
+ 221:Drivers/CMSIS/Include/core_cm4.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
+ 222:Drivers/CMSIS/Include/core_cm4.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
+ 223:Drivers/CMSIS/Include/core_cm4.h **** 
+ 224:Drivers/CMSIS/Include/core_cm4.h **** /* following defines should be used for structure members */
+ 225:Drivers/CMSIS/Include/core_cm4.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+ 226:Drivers/CMSIS/Include/core_cm4.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+ 227:Drivers/CMSIS/Include/core_cm4.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+ 228:Drivers/CMSIS/Include/core_cm4.h **** 
+ 229:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group Cortex_M4 */
+ 230:Drivers/CMSIS/Include/core_cm4.h **** 
+ 231:Drivers/CMSIS/Include/core_cm4.h **** 
+ 232:Drivers/CMSIS/Include/core_cm4.h **** 
+ 233:Drivers/CMSIS/Include/core_cm4.h **** /*******************************************************************************
+ 234:Drivers/CMSIS/Include/core_cm4.h ****  *                 Register Abstraction
+ 235:Drivers/CMSIS/Include/core_cm4.h ****   Core Register contain:
+ 236:Drivers/CMSIS/Include/core_cm4.h ****   - Core Register
+ 237:Drivers/CMSIS/Include/core_cm4.h ****   - Core NVIC Register
+ 238:Drivers/CMSIS/Include/core_cm4.h ****   - Core SCB Register
+ 239:Drivers/CMSIS/Include/core_cm4.h ****   - Core SysTick Register
+ 240:Drivers/CMSIS/Include/core_cm4.h ****   - Core Debug Register
+ 241:Drivers/CMSIS/Include/core_cm4.h ****   - Core MPU Register
+ 242:Drivers/CMSIS/Include/core_cm4.h ****   - Core FPU Register
+ 243:Drivers/CMSIS/Include/core_cm4.h ****  ******************************************************************************/
+ 244:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 245:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
+ 246:Drivers/CMSIS/Include/core_cm4.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
+ 247:Drivers/CMSIS/Include/core_cm4.h **** */
+ 248:Drivers/CMSIS/Include/core_cm4.h **** 
+ 249:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 250:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup    CMSIS_core_register
+ 251:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
+ 252:Drivers/CMSIS/Include/core_cm4.h ****   \brief      Core Register type definitions.
+ 253:Drivers/CMSIS/Include/core_cm4.h ****   @{
+ 254:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 255:Drivers/CMSIS/Include/core_cm4.h **** 
+ 256:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 257:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Union type to access the Application Program Status Register (APSR).
+ARM GAS  /tmp/ccVsbRnC.s 			page 6
+
+
+ 258:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 259:Drivers/CMSIS/Include/core_cm4.h **** typedef union
+ 260:Drivers/CMSIS/Include/core_cm4.h **** {
+ 261:Drivers/CMSIS/Include/core_cm4.h ****   struct
+ 262:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 263:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+ 264:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+ 265:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+ 266:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+ 267:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+ 268:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+ 269:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+ 270:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+ 271:Drivers/CMSIS/Include/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
+ 272:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 273:Drivers/CMSIS/Include/core_cm4.h **** } APSR_Type;
+ 274:Drivers/CMSIS/Include/core_cm4.h **** 
+ 275:Drivers/CMSIS/Include/core_cm4.h **** /* APSR Register Definitions */
+ 276:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
+ 277:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
+ 278:Drivers/CMSIS/Include/core_cm4.h **** 
+ 279:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
+ 280:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
+ 281:Drivers/CMSIS/Include/core_cm4.h **** 
+ 282:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
+ 283:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
+ 284:Drivers/CMSIS/Include/core_cm4.h **** 
+ 285:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
+ 286:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
+ 287:Drivers/CMSIS/Include/core_cm4.h **** 
+ 288:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Pos                         27U                                            /*!< APSR
+ 289:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR
+ 290:Drivers/CMSIS/Include/core_cm4.h **** 
+ 291:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Pos                        16U                                            /*!< APSR
+ 292:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR
+ 293:Drivers/CMSIS/Include/core_cm4.h **** 
+ 294:Drivers/CMSIS/Include/core_cm4.h **** 
+ 295:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 296:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ 297:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 298:Drivers/CMSIS/Include/core_cm4.h **** typedef union
+ 299:Drivers/CMSIS/Include/core_cm4.h **** {
+ 300:Drivers/CMSIS/Include/core_cm4.h ****   struct
+ 301:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 302:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+ 303:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+ 304:Drivers/CMSIS/Include/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
+ 305:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 306:Drivers/CMSIS/Include/core_cm4.h **** } IPSR_Type;
+ 307:Drivers/CMSIS/Include/core_cm4.h **** 
+ 308:Drivers/CMSIS/Include/core_cm4.h **** /* IPSR Register Definitions */
+ 309:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
+ 310:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
+ 311:Drivers/CMSIS/Include/core_cm4.h **** 
+ 312:Drivers/CMSIS/Include/core_cm4.h **** 
+ 313:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 314:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ARM GAS  /tmp/ccVsbRnC.s 			page 7
+
+
+ 315:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 316:Drivers/CMSIS/Include/core_cm4.h **** typedef union
+ 317:Drivers/CMSIS/Include/core_cm4.h **** {
+ 318:Drivers/CMSIS/Include/core_cm4.h ****   struct
+ 319:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 320:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+ 321:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+ 322:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+ 323:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+ 324:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+ 325:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+ 326:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+ 327:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+ 328:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+ 329:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+ 330:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+ 331:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+ 332:Drivers/CMSIS/Include/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
+ 333:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 334:Drivers/CMSIS/Include/core_cm4.h **** } xPSR_Type;
+ 335:Drivers/CMSIS/Include/core_cm4.h **** 
+ 336:Drivers/CMSIS/Include/core_cm4.h **** /* xPSR Register Definitions */
+ 337:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
+ 338:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
+ 339:Drivers/CMSIS/Include/core_cm4.h **** 
+ 340:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
+ 341:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
+ 342:Drivers/CMSIS/Include/core_cm4.h **** 
+ 343:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
+ 344:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
+ 345:Drivers/CMSIS/Include/core_cm4.h **** 
+ 346:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
+ 347:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
+ 348:Drivers/CMSIS/Include/core_cm4.h **** 
+ 349:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Pos                         27U                                            /*!< xPSR
+ 350:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR
+ 351:Drivers/CMSIS/Include/core_cm4.h **** 
+ 352:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR
+ 353:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR
+ 354:Drivers/CMSIS/Include/core_cm4.h **** 
+ 355:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
+ 356:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
+ 357:Drivers/CMSIS/Include/core_cm4.h **** 
+ 358:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Pos                        16U                                            /*!< xPSR
+ 359:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR
+ 360:Drivers/CMSIS/Include/core_cm4.h **** 
+ 361:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR
+ 362:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR
+ 363:Drivers/CMSIS/Include/core_cm4.h **** 
+ 364:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
+ 365:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
+ 366:Drivers/CMSIS/Include/core_cm4.h **** 
+ 367:Drivers/CMSIS/Include/core_cm4.h **** 
+ 368:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 369:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Union type to access the Control Registers (CONTROL).
+ 370:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 371:Drivers/CMSIS/Include/core_cm4.h **** typedef union
+ARM GAS  /tmp/ccVsbRnC.s 			page 8
+
+
+ 372:Drivers/CMSIS/Include/core_cm4.h **** {
+ 373:Drivers/CMSIS/Include/core_cm4.h ****   struct
+ 374:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 375:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+ 376:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+ 377:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+ 378:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+ 379:Drivers/CMSIS/Include/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
+ 380:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 381:Drivers/CMSIS/Include/core_cm4.h **** } CONTROL_Type;
+ 382:Drivers/CMSIS/Include/core_cm4.h **** 
+ 383:Drivers/CMSIS/Include/core_cm4.h **** /* CONTROL Register Definitions */
+ 384:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Pos                    2U                                            /*!< CONT
+ 385:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONT
+ 386:Drivers/CMSIS/Include/core_cm4.h **** 
+ 387:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
+ 388:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
+ 389:Drivers/CMSIS/Include/core_cm4.h **** 
+ 390:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONT
+ 391:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONT
+ 392:Drivers/CMSIS/Include/core_cm4.h **** 
+ 393:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CORE */
+ 394:Drivers/CMSIS/Include/core_cm4.h **** 
+ 395:Drivers/CMSIS/Include/core_cm4.h **** 
+ 396:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 397:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup    CMSIS_core_register
+ 398:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+ 399:Drivers/CMSIS/Include/core_cm4.h ****   \brief      Type definitions for the NVIC Registers
+ 400:Drivers/CMSIS/Include/core_cm4.h ****   @{
+ 401:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 402:Drivers/CMSIS/Include/core_cm4.h **** 
+ 403:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 404:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ 405:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 406:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
+ 407:Drivers/CMSIS/Include/core_cm4.h **** {
+ 408:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+ 409:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[24U];
+ 410:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
+ 411:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED1[24U];
+ 412:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
+ 413:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED2[24U];
+ 414:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
+ 415:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED3[24U];
+ 416:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+ 417:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED4[56U];
+ 418:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bi
+ 419:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED5[644U];
+ 420:Drivers/CMSIS/Include/core_cm4.h ****   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Regis
+ 421:Drivers/CMSIS/Include/core_cm4.h **** }  NVIC_Type;
+ 422:Drivers/CMSIS/Include/core_cm4.h **** 
+ 423:Drivers/CMSIS/Include/core_cm4.h **** /* Software Triggered Interrupt Register Definitions */
+ 424:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: I
+ 425:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: I
+ 426:Drivers/CMSIS/Include/core_cm4.h **** 
+ 427:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_NVIC */
+ 428:Drivers/CMSIS/Include/core_cm4.h **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 9
+
+
+ 429:Drivers/CMSIS/Include/core_cm4.h **** 
+ 430:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 431:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 432:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
+ 433:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the System Control Block Registers
+ 434:Drivers/CMSIS/Include/core_cm4.h ****   @{
+ 435:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 436:Drivers/CMSIS/Include/core_cm4.h **** 
+ 437:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 438:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the System Control Block (SCB).
+ 439:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 440:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
+ 441:Drivers/CMSIS/Include/core_cm4.h **** {
+ 442:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+ 443:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
+ 444:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+ 445:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
+ 446:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+ 447:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
+ 448:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registe
+ 449:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
+ 450:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Regist
+ 451:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+ 452:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+ 453:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register
+ 454:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+ 455:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register 
+ 456:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+ 457:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+ 458:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+ 459:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+ 460:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Regis
+ 461:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[5U];
+ 462:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Regis
+ 463:Drivers/CMSIS/Include/core_cm4.h **** } SCB_Type;
+ 464:Drivers/CMSIS/Include/core_cm4.h **** 
+ 465:Drivers/CMSIS/Include/core_cm4.h **** /* SCB CPUID Register Definitions */
+ 466:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
+ 467:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
+ 468:Drivers/CMSIS/Include/core_cm4.h **** 
+ 469:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
+ 470:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
+ 471:Drivers/CMSIS/Include/core_cm4.h **** 
+ 472:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
+ 473:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
+ 474:Drivers/CMSIS/Include/core_cm4.h **** 
+ 475:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
+ 476:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
+ 477:Drivers/CMSIS/Include/core_cm4.h **** 
+ 478:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
+ 479:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
+ 480:Drivers/CMSIS/Include/core_cm4.h **** 
+ 481:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Interrupt Control State Register Definitions */
+ 482:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
+ 483:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
+ 484:Drivers/CMSIS/Include/core_cm4.h **** 
+ 485:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
+ARM GAS  /tmp/ccVsbRnC.s 			page 10
+
+
+ 486:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
+ 487:Drivers/CMSIS/Include/core_cm4.h **** 
+ 488:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
+ 489:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
+ 490:Drivers/CMSIS/Include/core_cm4.h **** 
+ 491:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
+ 492:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
+ 493:Drivers/CMSIS/Include/core_cm4.h **** 
+ 494:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
+ 495:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
+ 496:Drivers/CMSIS/Include/core_cm4.h **** 
+ 497:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
+ 498:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
+ 499:Drivers/CMSIS/Include/core_cm4.h **** 
+ 500:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
+ 501:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
+ 502:Drivers/CMSIS/Include/core_cm4.h **** 
+ 503:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
+ 504:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
+ 505:Drivers/CMSIS/Include/core_cm4.h **** 
+ 506:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB 
+ 507:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB 
+ 508:Drivers/CMSIS/Include/core_cm4.h **** 
+ 509:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
+ 510:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
+ 511:Drivers/CMSIS/Include/core_cm4.h **** 
+ 512:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Vector Table Offset Register Definitions */
+ 513:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB 
+ 514:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB 
+ 515:Drivers/CMSIS/Include/core_cm4.h **** 
+ 516:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
+ 517:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
+ 518:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
+ 519:Drivers/CMSIS/Include/core_cm4.h **** 
+ 520:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
+ 521:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
+ 522:Drivers/CMSIS/Include/core_cm4.h **** 
+ 523:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
+ 524:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
+ 525:Drivers/CMSIS/Include/core_cm4.h **** 
+ 526:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB 
+ 527:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB 
+ 528:Drivers/CMSIS/Include/core_cm4.h **** 
+ 529:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
+ 530:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
+ 531:Drivers/CMSIS/Include/core_cm4.h **** 
+ 532:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
+ 533:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
+ 534:Drivers/CMSIS/Include/core_cm4.h **** 
+ 535:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB 
+ 536:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB 
+ 537:Drivers/CMSIS/Include/core_cm4.h **** 
+ 538:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Control Register Definitions */
+ 539:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
+ 540:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
+ 541:Drivers/CMSIS/Include/core_cm4.h **** 
+ 542:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
+ARM GAS  /tmp/ccVsbRnC.s 			page 11
+
+
+ 543:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
+ 544:Drivers/CMSIS/Include/core_cm4.h **** 
+ 545:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
+ 546:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
+ 547:Drivers/CMSIS/Include/core_cm4.h **** 
+ 548:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configuration Control Register Definitions */
+ 549:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
+ 550:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
+ 551:Drivers/CMSIS/Include/core_cm4.h **** 
+ 552:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB 
+ 553:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB 
+ 554:Drivers/CMSIS/Include/core_cm4.h **** 
+ 555:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB 
+ 556:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB 
+ 557:Drivers/CMSIS/Include/core_cm4.h **** 
+ 558:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
+ 559:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
+ 560:Drivers/CMSIS/Include/core_cm4.h **** 
+ 561:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB 
+ 562:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB 
+ 563:Drivers/CMSIS/Include/core_cm4.h **** 
+ 564:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB 
+ 565:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB 
+ 566:Drivers/CMSIS/Include/core_cm4.h **** 
+ 567:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Handler Control and State Register Definitions */
+ 568:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB 
+ 569:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB 
+ 570:Drivers/CMSIS/Include/core_cm4.h **** 
+ 571:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB 
+ 572:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB 
+ 573:Drivers/CMSIS/Include/core_cm4.h **** 
+ 574:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB 
+ 575:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB 
+ 576:Drivers/CMSIS/Include/core_cm4.h **** 
+ 577:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
+ 578:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
+ 579:Drivers/CMSIS/Include/core_cm4.h **** 
+ 580:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB 
+ 581:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB 
+ 582:Drivers/CMSIS/Include/core_cm4.h **** 
+ 583:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB 
+ 584:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB 
+ 585:Drivers/CMSIS/Include/core_cm4.h **** 
+ 586:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB 
+ 587:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB 
+ 588:Drivers/CMSIS/Include/core_cm4.h **** 
+ 589:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB 
+ 590:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB 
+ 591:Drivers/CMSIS/Include/core_cm4.h **** 
+ 592:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB 
+ 593:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB 
+ 594:Drivers/CMSIS/Include/core_cm4.h **** 
+ 595:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB 
+ 596:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB 
+ 597:Drivers/CMSIS/Include/core_cm4.h **** 
+ 598:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB 
+ 599:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB 
+ARM GAS  /tmp/ccVsbRnC.s 			page 12
+
+
+ 600:Drivers/CMSIS/Include/core_cm4.h **** 
+ 601:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB 
+ 602:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB 
+ 603:Drivers/CMSIS/Include/core_cm4.h **** 
+ 604:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB 
+ 605:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB 
+ 606:Drivers/CMSIS/Include/core_cm4.h **** 
+ 607:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB 
+ 608:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB 
+ 609:Drivers/CMSIS/Include/core_cm4.h **** 
+ 610:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */
+ 611:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB 
+ 612:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB 
+ 613:Drivers/CMSIS/Include/core_cm4.h **** 
+ 614:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB 
+ 615:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB 
+ 616:Drivers/CMSIS/Include/core_cm4.h **** 
+ 617:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB 
+ 618:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB 
+ 619:Drivers/CMSIS/Include/core_cm4.h **** 
+ 620:Drivers/CMSIS/Include/core_cm4.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+ 621:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB 
+ 622:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB 
+ 623:Drivers/CMSIS/Include/core_cm4.h **** 
+ 624:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB 
+ 625:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB 
+ 626:Drivers/CMSIS/Include/core_cm4.h **** 
+ 627:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB 
+ 628:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB 
+ 629:Drivers/CMSIS/Include/core_cm4.h **** 
+ 630:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB 
+ 631:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB 
+ 632:Drivers/CMSIS/Include/core_cm4.h **** 
+ 633:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB 
+ 634:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB 
+ 635:Drivers/CMSIS/Include/core_cm4.h **** 
+ 636:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB 
+ 637:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB 
+ 638:Drivers/CMSIS/Include/core_cm4.h **** 
+ 639:Drivers/CMSIS/Include/core_cm4.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+ 640:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB 
+ 641:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB 
+ 642:Drivers/CMSIS/Include/core_cm4.h **** 
+ 643:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB 
+ 644:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB 
+ 645:Drivers/CMSIS/Include/core_cm4.h **** 
+ 646:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB 
+ 647:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB 
+ 648:Drivers/CMSIS/Include/core_cm4.h **** 
+ 649:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB 
+ 650:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB 
+ 651:Drivers/CMSIS/Include/core_cm4.h **** 
+ 652:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB 
+ 653:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB 
+ 654:Drivers/CMSIS/Include/core_cm4.h **** 
+ 655:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB 
+ 656:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB 
+ARM GAS  /tmp/ccVsbRnC.s 			page 13
+
+
+ 657:Drivers/CMSIS/Include/core_cm4.h **** 
+ 658:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB 
+ 659:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB 
+ 660:Drivers/CMSIS/Include/core_cm4.h **** 
+ 661:Drivers/CMSIS/Include/core_cm4.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+ 662:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB 
+ 663:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB 
+ 664:Drivers/CMSIS/Include/core_cm4.h **** 
+ 665:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB 
+ 666:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB 
+ 667:Drivers/CMSIS/Include/core_cm4.h **** 
+ 668:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB 
+ 669:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB 
+ 670:Drivers/CMSIS/Include/core_cm4.h **** 
+ 671:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB 
+ 672:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB 
+ 673:Drivers/CMSIS/Include/core_cm4.h **** 
+ 674:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB 
+ 675:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB 
+ 676:Drivers/CMSIS/Include/core_cm4.h **** 
+ 677:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB 
+ 678:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB 
+ 679:Drivers/CMSIS/Include/core_cm4.h **** 
+ 680:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Hard Fault Status Register Definitions */
+ 681:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB 
+ 682:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB 
+ 683:Drivers/CMSIS/Include/core_cm4.h **** 
+ 684:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB 
+ 685:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB 
+ 686:Drivers/CMSIS/Include/core_cm4.h **** 
+ 687:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB 
+ 688:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB 
+ 689:Drivers/CMSIS/Include/core_cm4.h **** 
+ 690:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Debug Fault Status Register Definitions */
+ 691:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB 
+ 692:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB 
+ 693:Drivers/CMSIS/Include/core_cm4.h **** 
+ 694:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB 
+ 695:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB 
+ 696:Drivers/CMSIS/Include/core_cm4.h **** 
+ 697:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB 
+ 698:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB 
+ 699:Drivers/CMSIS/Include/core_cm4.h **** 
+ 700:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB 
+ 701:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB 
+ 702:Drivers/CMSIS/Include/core_cm4.h **** 
+ 703:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB 
+ 704:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB 
+ 705:Drivers/CMSIS/Include/core_cm4.h **** 
+ 706:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCB */
+ 707:Drivers/CMSIS/Include/core_cm4.h **** 
+ 708:Drivers/CMSIS/Include/core_cm4.h **** 
+ 709:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 710:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 711:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ 712:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the System Control and ID Register not in the SCB
+ 713:Drivers/CMSIS/Include/core_cm4.h ****   @{
+ARM GAS  /tmp/ccVsbRnC.s 			page 14
+
+
+ 714:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 715:Drivers/CMSIS/Include/core_cm4.h **** 
+ 716:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 717:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the System Control and ID Register not in the SCB.
+ 718:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 719:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
+ 720:Drivers/CMSIS/Include/core_cm4.h **** {
+ 721:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[1U];
+ 722:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Regist
+ 723:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+ 724:Drivers/CMSIS/Include/core_cm4.h **** } SCnSCB_Type;
+ 725:Drivers/CMSIS/Include/core_cm4.h **** 
+ 726:Drivers/CMSIS/Include/core_cm4.h **** /* Interrupt Controller Type Register Definitions */
+ 727:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: I
+ 728:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: I
+ 729:Drivers/CMSIS/Include/core_cm4.h **** 
+ 730:Drivers/CMSIS/Include/core_cm4.h **** /* Auxiliary Control Register Definitions */
+ 731:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: 
+ 732:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: 
+ 733:Drivers/CMSIS/Include/core_cm4.h **** 
+ 734:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: 
+ 735:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: 
+ 736:Drivers/CMSIS/Include/core_cm4.h **** 
+ 737:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: 
+ 738:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: 
+ 739:Drivers/CMSIS/Include/core_cm4.h **** 
+ 740:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: 
+ 741:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: 
+ 742:Drivers/CMSIS/Include/core_cm4.h **** 
+ 743:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: 
+ 744:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: 
+ 745:Drivers/CMSIS/Include/core_cm4.h **** 
+ 746:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */
+ 747:Drivers/CMSIS/Include/core_cm4.h **** 
+ 748:Drivers/CMSIS/Include/core_cm4.h **** 
+ 749:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 750:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 751:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+ 752:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the System Timer Registers.
+ 753:Drivers/CMSIS/Include/core_cm4.h ****   @{
+ 754:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 755:Drivers/CMSIS/Include/core_cm4.h **** 
+ 756:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 757:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the System Timer (SysTick).
+ 758:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 759:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
+ 760:Drivers/CMSIS/Include/core_cm4.h **** {
+ 761:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
+ 762:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+ 763:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
+ 764:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+ 765:Drivers/CMSIS/Include/core_cm4.h **** } SysTick_Type;
+ 766:Drivers/CMSIS/Include/core_cm4.h **** 
+ 767:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Control / Status Register Definitions */
+ 768:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
+ 769:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
+ 770:Drivers/CMSIS/Include/core_cm4.h **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 15
+
+
+ 771:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
+ 772:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
+ 773:Drivers/CMSIS/Include/core_cm4.h **** 
+ 774:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
+ 775:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
+ 776:Drivers/CMSIS/Include/core_cm4.h **** 
+ 777:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
+ 778:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
+ 779:Drivers/CMSIS/Include/core_cm4.h **** 
+ 780:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Reload Register Definitions */
+ 781:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
+ 782:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
+ 783:Drivers/CMSIS/Include/core_cm4.h **** 
+ 784:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Current Register Definitions */
+ 785:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
+ 786:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
+ 787:Drivers/CMSIS/Include/core_cm4.h **** 
+ 788:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Calibration Register Definitions */
+ 789:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
+ 790:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
+ 791:Drivers/CMSIS/Include/core_cm4.h **** 
+ 792:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
+ 793:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
+ 794:Drivers/CMSIS/Include/core_cm4.h **** 
+ 795:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
+ 796:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
+ 797:Drivers/CMSIS/Include/core_cm4.h **** 
+ 798:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SysTick */
+ 799:Drivers/CMSIS/Include/core_cm4.h **** 
+ 800:Drivers/CMSIS/Include/core_cm4.h **** 
+ 801:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 802:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 803:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+ 804:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+ 805:Drivers/CMSIS/Include/core_cm4.h ****   @{
+ 806:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 807:Drivers/CMSIS/Include/core_cm4.h **** 
+ 808:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 809:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ 810:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 811:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
+ 812:Drivers/CMSIS/Include/core_cm4.h **** {
+ 813:Drivers/CMSIS/Include/core_cm4.h ****   __OM  union
+ 814:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 815:Drivers/CMSIS/Include/core_cm4.h ****     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+ 816:Drivers/CMSIS/Include/core_cm4.h ****     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+ 817:Drivers/CMSIS/Include/core_cm4.h ****     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+ 818:Drivers/CMSIS/Include/core_cm4.h ****   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+ 819:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[864U];
+ 820:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+ 821:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED1[15U];
+ 822:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+ 823:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED2[15U];
+ 824:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+ 825:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED3[32U];
+ 826:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED4[43U];
+ 827:Drivers/CMSIS/Include/core_cm4.h ****   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+ARM GAS  /tmp/ccVsbRnC.s 			page 16
+
+
+ 828:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+ 829:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED5[6U];
+ 830:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Re
+ 831:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Re
+ 832:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Re
+ 833:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Re
+ 834:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Re
+ 835:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Re
+ 836:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Re
+ 837:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Re
+ 838:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Re
+ 839:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Re
+ 840:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Re
+ 841:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Re
+ 842:Drivers/CMSIS/Include/core_cm4.h **** } ITM_Type;
+ 843:Drivers/CMSIS/Include/core_cm4.h **** 
+ 844:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Privilege Register Definitions */
+ 845:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM 
+ 846:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM 
+ 847:Drivers/CMSIS/Include/core_cm4.h **** 
+ 848:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Control Register Definitions */
+ 849:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM 
+ 850:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM 
+ 851:Drivers/CMSIS/Include/core_cm4.h **** 
+ 852:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM 
+ 853:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM 
+ 854:Drivers/CMSIS/Include/core_cm4.h **** 
+ 855:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM 
+ 856:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM 
+ 857:Drivers/CMSIS/Include/core_cm4.h **** 
+ 858:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM 
+ 859:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM 
+ 860:Drivers/CMSIS/Include/core_cm4.h **** 
+ 861:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM 
+ 862:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM 
+ 863:Drivers/CMSIS/Include/core_cm4.h **** 
+ 864:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM 
+ 865:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM 
+ 866:Drivers/CMSIS/Include/core_cm4.h **** 
+ 867:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM 
+ 868:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM 
+ 869:Drivers/CMSIS/Include/core_cm4.h **** 
+ 870:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM 
+ 871:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM 
+ 872:Drivers/CMSIS/Include/core_cm4.h **** 
+ 873:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM 
+ 874:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM 
+ 875:Drivers/CMSIS/Include/core_cm4.h **** 
+ 876:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Lock Status Register Definitions */
+ 877:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM 
+ 878:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM 
+ 879:Drivers/CMSIS/Include/core_cm4.h **** 
+ 880:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Pos                  1U                                            /*!< ITM 
+ 881:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM 
+ 882:Drivers/CMSIS/Include/core_cm4.h **** 
+ 883:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Pos                 0U                                            /*!< ITM 
+ 884:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM 
+ARM GAS  /tmp/ccVsbRnC.s 			page 17
+
+
+ 885:Drivers/CMSIS/Include/core_cm4.h **** 
+ 886:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */
+ 887:Drivers/CMSIS/Include/core_cm4.h **** 
+ 888:Drivers/CMSIS/Include/core_cm4.h **** 
+ 889:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 890:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 891:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+ 892:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+ 893:Drivers/CMSIS/Include/core_cm4.h ****   @{
+ 894:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 895:Drivers/CMSIS/Include/core_cm4.h **** 
+ 896:Drivers/CMSIS/Include/core_cm4.h **** /**
+ 897:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ 898:Drivers/CMSIS/Include/core_cm4.h ****  */
+ 899:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
+ 900:Drivers/CMSIS/Include/core_cm4.h **** {
+ 901:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+ 902:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+ 903:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+ 904:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Registe
+ 905:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+ 906:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+ 907:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Registe
+ 908:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register 
+ 909:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+ 910:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+ 911:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+ 912:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[1U];
+ 913:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+ 914:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+ 915:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+ 916:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED1[1U];
+ 917:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+ 918:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+ 919:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+ 920:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED2[1U];
+ 921:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+ 922:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+ 923:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+ 924:Drivers/CMSIS/Include/core_cm4.h **** } DWT_Type;
+ 925:Drivers/CMSIS/Include/core_cm4.h **** 
+ 926:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Control Register Definitions */
+ 927:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTR
+ 928:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTR
+ 929:Drivers/CMSIS/Include/core_cm4.h **** 
+ 930:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTR
+ 931:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTR
+ 932:Drivers/CMSIS/Include/core_cm4.h **** 
+ 933:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTR
+ 934:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTR
+ 935:Drivers/CMSIS/Include/core_cm4.h **** 
+ 936:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTR
+ 937:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTR
+ 938:Drivers/CMSIS/Include/core_cm4.h **** 
+ 939:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTR
+ 940:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTR
+ 941:Drivers/CMSIS/Include/core_cm4.h **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 18
+
+
+ 942:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTR
+ 943:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTR
+ 944:Drivers/CMSIS/Include/core_cm4.h **** 
+ 945:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTR
+ 946:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTR
+ 947:Drivers/CMSIS/Include/core_cm4.h **** 
+ 948:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTR
+ 949:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTR
+ 950:Drivers/CMSIS/Include/core_cm4.h **** 
+ 951:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTR
+ 952:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTR
+ 953:Drivers/CMSIS/Include/core_cm4.h **** 
+ 954:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTR
+ 955:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTR
+ 956:Drivers/CMSIS/Include/core_cm4.h **** 
+ 957:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTR
+ 958:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTR
+ 959:Drivers/CMSIS/Include/core_cm4.h **** 
+ 960:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTR
+ 961:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTR
+ 962:Drivers/CMSIS/Include/core_cm4.h **** 
+ 963:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTR
+ 964:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTR
+ 965:Drivers/CMSIS/Include/core_cm4.h **** 
+ 966:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTR
+ 967:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTR
+ 968:Drivers/CMSIS/Include/core_cm4.h **** 
+ 969:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTR
+ 970:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTR
+ 971:Drivers/CMSIS/Include/core_cm4.h **** 
+ 972:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTR
+ 973:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTR
+ 974:Drivers/CMSIS/Include/core_cm4.h **** 
+ 975:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTR
+ 976:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTR
+ 977:Drivers/CMSIS/Include/core_cm4.h **** 
+ 978:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTR
+ 979:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTR
+ 980:Drivers/CMSIS/Include/core_cm4.h **** 
+ 981:Drivers/CMSIS/Include/core_cm4.h **** /* DWT CPI Count Register Definitions */
+ 982:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPI
+ 983:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPI
+ 984:Drivers/CMSIS/Include/core_cm4.h **** 
+ 985:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */
+ 986:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXC
+ 987:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXC
+ 988:Drivers/CMSIS/Include/core_cm4.h **** 
+ 989:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Sleep Count Register Definitions */
+ 990:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLE
+ 991:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLE
+ 992:Drivers/CMSIS/Include/core_cm4.h **** 
+ 993:Drivers/CMSIS/Include/core_cm4.h **** /* DWT LSU Count Register Definitions */
+ 994:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSU
+ 995:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSU
+ 996:Drivers/CMSIS/Include/core_cm4.h **** 
+ 997:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */
+ 998:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOL
+ARM GAS  /tmp/ccVsbRnC.s 			page 19
+
+
+ 999:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOL
+1000:Drivers/CMSIS/Include/core_cm4.h **** 
+1001:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Mask Register Definitions */
+1002:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MAS
+1003:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MAS
+1004:Drivers/CMSIS/Include/core_cm4.h **** 
+1005:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Function Register Definitions */
+1006:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUN
+1007:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUN
+1008:Drivers/CMSIS/Include/core_cm4.h **** 
+1009:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUN
+1010:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUN
+1011:Drivers/CMSIS/Include/core_cm4.h **** 
+1012:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUN
+1013:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUN
+1014:Drivers/CMSIS/Include/core_cm4.h **** 
+1015:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUN
+1016:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUN
+1017:Drivers/CMSIS/Include/core_cm4.h **** 
+1018:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUN
+1019:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUN
+1020:Drivers/CMSIS/Include/core_cm4.h **** 
+1021:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUN
+1022:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUN
+1023:Drivers/CMSIS/Include/core_cm4.h **** 
+1024:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUN
+1025:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUN
+1026:Drivers/CMSIS/Include/core_cm4.h **** 
+1027:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUN
+1028:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUN
+1029:Drivers/CMSIS/Include/core_cm4.h **** 
+1030:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUN
+1031:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUN
+1032:Drivers/CMSIS/Include/core_cm4.h **** 
+1033:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */
+1034:Drivers/CMSIS/Include/core_cm4.h **** 
+1035:Drivers/CMSIS/Include/core_cm4.h **** 
+1036:Drivers/CMSIS/Include/core_cm4.h **** /**
+1037:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
+1038:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+1039:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the Trace Port Interface (TPI)
+1040:Drivers/CMSIS/Include/core_cm4.h ****   @{
+1041:Drivers/CMSIS/Include/core_cm4.h ****  */
+1042:Drivers/CMSIS/Include/core_cm4.h **** 
+1043:Drivers/CMSIS/Include/core_cm4.h **** /**
+1044:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Trace Port Interface Register (TPI).
+1045:Drivers/CMSIS/Include/core_cm4.h ****  */
+1046:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
+1047:Drivers/CMSIS/Include/core_cm4.h **** {
+1048:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Reg
+1049:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Regis
+1050:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[2U];
+1051:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Reg
+1052:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED1[55U];
+1053:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register *
+1054:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED2[131U];
+1055:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Regis
+ARM GAS  /tmp/ccVsbRnC.s 			page 20
+
+
+1056:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Regi
+1057:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counte
+1058:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED3[759U];
+1059:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+1060:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+1061:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+1062:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED4[1U];
+1063:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+1064:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+1065:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+1066:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED5[39U];
+1067:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+1068:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+1069:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED7[8U];
+1070:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+1071:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+1072:Drivers/CMSIS/Include/core_cm4.h **** } TPI_Type;
+1073:Drivers/CMSIS/Include/core_cm4.h **** 
+1074:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
+1075:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACP
+1076:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACP
+1077:Drivers/CMSIS/Include/core_cm4.h **** 
+1078:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */
+1079:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPP
+1080:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPP
+1081:Drivers/CMSIS/Include/core_cm4.h **** 
+1082:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */
+1083:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFS
+1084:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFS
+1085:Drivers/CMSIS/Include/core_cm4.h **** 
+1086:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFS
+1087:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFS
+1088:Drivers/CMSIS/Include/core_cm4.h **** 
+1089:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFS
+1090:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFS
+1091:Drivers/CMSIS/Include/core_cm4.h **** 
+1092:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFS
+1093:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFS
+1094:Drivers/CMSIS/Include/core_cm4.h **** 
+1095:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */
+1096:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFC
+1097:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFC
+1098:Drivers/CMSIS/Include/core_cm4.h **** 
+1099:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFC
+1100:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFC
+1101:Drivers/CMSIS/Include/core_cm4.h **** 
+1102:Drivers/CMSIS/Include/core_cm4.h **** /* TPI TRIGGER Register Definitions */
+1103:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRI
+1104:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRI
+1105:Drivers/CMSIS/Include/core_cm4.h **** 
+1106:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
+1107:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
+1108:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIF
+1109:Drivers/CMSIS/Include/core_cm4.h **** 
+1110:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
+1111:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIF
+1112:Drivers/CMSIS/Include/core_cm4.h **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 21
+
+
+1113:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
+1114:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIF
+1115:Drivers/CMSIS/Include/core_cm4.h **** 
+1116:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
+1117:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIF
+1118:Drivers/CMSIS/Include/core_cm4.h **** 
+1119:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIF
+1120:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIF
+1121:Drivers/CMSIS/Include/core_cm4.h **** 
+1122:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIF
+1123:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIF
+1124:Drivers/CMSIS/Include/core_cm4.h **** 
+1125:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIF
+1126:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIF
+1127:Drivers/CMSIS/Include/core_cm4.h **** 
+1128:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */
+1129:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITA
+1130:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITA
+1131:Drivers/CMSIS/Include/core_cm4.h **** 
+1132:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITA
+1133:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITA
+1134:Drivers/CMSIS/Include/core_cm4.h **** 
+1135:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
+1136:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
+1137:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIF
+1138:Drivers/CMSIS/Include/core_cm4.h **** 
+1139:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
+1140:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIF
+1141:Drivers/CMSIS/Include/core_cm4.h **** 
+1142:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
+1143:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIF
+1144:Drivers/CMSIS/Include/core_cm4.h **** 
+1145:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
+1146:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIF
+1147:Drivers/CMSIS/Include/core_cm4.h **** 
+1148:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIF
+1149:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIF
+1150:Drivers/CMSIS/Include/core_cm4.h **** 
+1151:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIF
+1152:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIF
+1153:Drivers/CMSIS/Include/core_cm4.h **** 
+1154:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIF
+1155:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIF
+1156:Drivers/CMSIS/Include/core_cm4.h **** 
+1157:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */
+1158:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITA
+1159:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITA
+1160:Drivers/CMSIS/Include/core_cm4.h **** 
+1161:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITA
+1162:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITA
+1163:Drivers/CMSIS/Include/core_cm4.h **** 
+1164:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration Mode Control Register Definitions */
+1165:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITC
+1166:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITC
+1167:Drivers/CMSIS/Include/core_cm4.h **** 
+1168:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVID Register Definitions */
+1169:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEV
+ARM GAS  /tmp/ccVsbRnC.s 			page 22
+
+
+1170:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEV
+1171:Drivers/CMSIS/Include/core_cm4.h **** 
+1172:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEV
+1173:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEV
+1174:Drivers/CMSIS/Include/core_cm4.h **** 
+1175:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEV
+1176:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEV
+1177:Drivers/CMSIS/Include/core_cm4.h **** 
+1178:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEV
+1179:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEV
+1180:Drivers/CMSIS/Include/core_cm4.h **** 
+1181:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEV
+1182:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEV
+1183:Drivers/CMSIS/Include/core_cm4.h **** 
+1184:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEV
+1185:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEV
+1186:Drivers/CMSIS/Include/core_cm4.h **** 
+1187:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVTYPE Register Definitions */
+1188:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEV
+1189:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEV
+1190:Drivers/CMSIS/Include/core_cm4.h **** 
+1191:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEV
+1192:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEV
+1193:Drivers/CMSIS/Include/core_cm4.h **** 
+1194:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */
+1195:Drivers/CMSIS/Include/core_cm4.h **** 
+1196:Drivers/CMSIS/Include/core_cm4.h **** 
+1197:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+1198:Drivers/CMSIS/Include/core_cm4.h **** /**
+1199:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
+1200:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+1201:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the Memory Protection Unit (MPU)
+1202:Drivers/CMSIS/Include/core_cm4.h ****   @{
+1203:Drivers/CMSIS/Include/core_cm4.h ****  */
+1204:Drivers/CMSIS/Include/core_cm4.h **** 
+1205:Drivers/CMSIS/Include/core_cm4.h **** /**
+1206:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Memory Protection Unit (MPU).
+1207:Drivers/CMSIS/Include/core_cm4.h ****  */
+1208:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
+1209:Drivers/CMSIS/Include/core_cm4.h **** {
+1210:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+1211:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+1212:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+1213:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register
+1214:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Re
+1215:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address 
+1216:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and
+1217:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address 
+1218:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and
+1219:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address 
+1220:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and
+1221:Drivers/CMSIS/Include/core_cm4.h **** } MPU_Type;
+1222:Drivers/CMSIS/Include/core_cm4.h **** 
+1223:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_RALIASES                  4U
+1224:Drivers/CMSIS/Include/core_cm4.h **** 
+1225:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Type Register Definitions */
+1226:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU 
+ARM GAS  /tmp/ccVsbRnC.s 			page 23
+
+
+1227:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU 
+1228:Drivers/CMSIS/Include/core_cm4.h **** 
+1229:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU 
+1230:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU 
+1231:Drivers/CMSIS/Include/core_cm4.h **** 
+1232:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU 
+1233:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU 
+1234:Drivers/CMSIS/Include/core_cm4.h **** 
+1235:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Control Register Definitions */
+1236:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU 
+1237:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU 
+1238:Drivers/CMSIS/Include/core_cm4.h **** 
+1239:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU 
+1240:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU 
+1241:Drivers/CMSIS/Include/core_cm4.h **** 
+1242:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU 
+1243:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU 
+1244:Drivers/CMSIS/Include/core_cm4.h **** 
+1245:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Number Register Definitions */
+1246:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU 
+1247:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU 
+1248:Drivers/CMSIS/Include/core_cm4.h **** 
+1249:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Base Address Register Definitions */
+1250:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU 
+1251:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU 
+1252:Drivers/CMSIS/Include/core_cm4.h **** 
+1253:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU 
+1254:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU 
+1255:Drivers/CMSIS/Include/core_cm4.h **** 
+1256:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU 
+1257:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU 
+1258:Drivers/CMSIS/Include/core_cm4.h **** 
+1259:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */
+1260:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU 
+1261:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU 
+1262:Drivers/CMSIS/Include/core_cm4.h **** 
+1263:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU 
+1264:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU 
+1265:Drivers/CMSIS/Include/core_cm4.h **** 
+1266:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU 
+1267:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU 
+1268:Drivers/CMSIS/Include/core_cm4.h **** 
+1269:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU 
+1270:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU 
+1271:Drivers/CMSIS/Include/core_cm4.h **** 
+1272:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Pos                     18U                                            /*!< MPU 
+1273:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU 
+1274:Drivers/CMSIS/Include/core_cm4.h **** 
+1275:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Pos                     17U                                            /*!< MPU 
+1276:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU 
+1277:Drivers/CMSIS/Include/core_cm4.h **** 
+1278:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Pos                     16U                                            /*!< MPU 
+1279:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU 
+1280:Drivers/CMSIS/Include/core_cm4.h **** 
+1281:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU 
+1282:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU 
+1283:Drivers/CMSIS/Include/core_cm4.h **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 24
+
+
+1284:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU 
+1285:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU 
+1286:Drivers/CMSIS/Include/core_cm4.h **** 
+1287:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU 
+1288:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU 
+1289:Drivers/CMSIS/Include/core_cm4.h **** 
+1290:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_MPU */
+1291:Drivers/CMSIS/Include/core_cm4.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+1292:Drivers/CMSIS/Include/core_cm4.h **** 
+1293:Drivers/CMSIS/Include/core_cm4.h **** 
+1294:Drivers/CMSIS/Include/core_cm4.h **** /**
+1295:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
+1296:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+1297:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the Floating Point Unit (FPU)
+1298:Drivers/CMSIS/Include/core_cm4.h ****   @{
+1299:Drivers/CMSIS/Include/core_cm4.h ****  */
+1300:Drivers/CMSIS/Include/core_cm4.h **** 
+1301:Drivers/CMSIS/Include/core_cm4.h **** /**
+1302:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Floating Point Unit (FPU).
+1303:Drivers/CMSIS/Include/core_cm4.h ****  */
+1304:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
+1305:Drivers/CMSIS/Include/core_cm4.h **** {
+1306:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[1U];
+1307:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control R
+1308:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address R
+1309:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Co
+1310:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 
+1311:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 
+1312:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 
+1313:Drivers/CMSIS/Include/core_cm4.h **** } FPU_Type;
+1314:Drivers/CMSIS/Include/core_cm4.h **** 
+1315:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Control Register Definitions */
+1316:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCC
+1317:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCC
+1318:Drivers/CMSIS/Include/core_cm4.h **** 
+1319:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCC
+1320:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCC
+1321:Drivers/CMSIS/Include/core_cm4.h **** 
+1322:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCC
+1323:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCC
+1324:Drivers/CMSIS/Include/core_cm4.h **** 
+1325:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCC
+1326:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCC
+1327:Drivers/CMSIS/Include/core_cm4.h **** 
+1328:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCC
+1329:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCC
+1330:Drivers/CMSIS/Include/core_cm4.h **** 
+1331:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCC
+1332:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCC
+1333:Drivers/CMSIS/Include/core_cm4.h **** 
+1334:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCC
+1335:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCC
+1336:Drivers/CMSIS/Include/core_cm4.h **** 
+1337:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCC
+1338:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCC
+1339:Drivers/CMSIS/Include/core_cm4.h **** 
+1340:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCC
+ARM GAS  /tmp/ccVsbRnC.s 			page 25
+
+
+1341:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCC
+1342:Drivers/CMSIS/Include/core_cm4.h **** 
+1343:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Address Register Definitions */
+1344:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCA
+1345:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCA
+1346:Drivers/CMSIS/Include/core_cm4.h **** 
+1347:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */
+1348:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDS
+1349:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDS
+1350:Drivers/CMSIS/Include/core_cm4.h **** 
+1351:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDS
+1352:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDS
+1353:Drivers/CMSIS/Include/core_cm4.h **** 
+1354:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDS
+1355:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDS
+1356:Drivers/CMSIS/Include/core_cm4.h **** 
+1357:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDS
+1358:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDS
+1359:Drivers/CMSIS/Include/core_cm4.h **** 
+1360:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 0 Definitions */
+1361:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR
+1362:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR
+1363:Drivers/CMSIS/Include/core_cm4.h **** 
+1364:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR
+1365:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR
+1366:Drivers/CMSIS/Include/core_cm4.h **** 
+1367:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR
+1368:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR
+1369:Drivers/CMSIS/Include/core_cm4.h **** 
+1370:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR
+1371:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR
+1372:Drivers/CMSIS/Include/core_cm4.h **** 
+1373:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR
+1374:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR
+1375:Drivers/CMSIS/Include/core_cm4.h **** 
+1376:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR
+1377:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR
+1378:Drivers/CMSIS/Include/core_cm4.h **** 
+1379:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR
+1380:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR
+1381:Drivers/CMSIS/Include/core_cm4.h **** 
+1382:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR
+1383:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR
+1384:Drivers/CMSIS/Include/core_cm4.h **** 
+1385:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 1 Definitions */
+1386:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR
+1387:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR
+1388:Drivers/CMSIS/Include/core_cm4.h **** 
+1389:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR
+1390:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR
+1391:Drivers/CMSIS/Include/core_cm4.h **** 
+1392:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR
+1393:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR
+1394:Drivers/CMSIS/Include/core_cm4.h **** 
+1395:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR
+1396:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR
+1397:Drivers/CMSIS/Include/core_cm4.h **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 26
+
+
+1398:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 2 Definitions */
+1399:Drivers/CMSIS/Include/core_cm4.h **** 
+1400:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR
+1401:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR
+1402:Drivers/CMSIS/Include/core_cm4.h **** 
+1403:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_FPU */
+1404:Drivers/CMSIS/Include/core_cm4.h **** 
+1405:Drivers/CMSIS/Include/core_cm4.h **** 
+1406:Drivers/CMSIS/Include/core_cm4.h **** /**
+1407:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
+1408:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+1409:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the Core Debug Registers
+1410:Drivers/CMSIS/Include/core_cm4.h ****   @{
+1411:Drivers/CMSIS/Include/core_cm4.h ****  */
+1412:Drivers/CMSIS/Include/core_cm4.h **** 
+1413:Drivers/CMSIS/Include/core_cm4.h **** /**
+1414:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Core Debug Register (CoreDebug).
+1415:Drivers/CMSIS/Include/core_cm4.h ****  */
+1416:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
+1417:Drivers/CMSIS/Include/core_cm4.h **** {
+1418:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status
+1419:Drivers/CMSIS/Include/core_cm4.h ****   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Reg
+1420:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Registe
+1421:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Cont
+1422:Drivers/CMSIS/Include/core_cm4.h **** } CoreDebug_Type;
+1423:Drivers/CMSIS/Include/core_cm4.h **** 
+1424:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Halting Control and Status Register Definitions */
+1425:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< Core
+1426:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< Core
+1427:Drivers/CMSIS/Include/core_cm4.h **** 
+1428:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< Core
+1429:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< Core
+1430:Drivers/CMSIS/Include/core_cm4.h **** 
+1431:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< Core
+1432:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< Core
+1433:Drivers/CMSIS/Include/core_cm4.h **** 
+1434:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< Core
+1435:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< Core
+1436:Drivers/CMSIS/Include/core_cm4.h **** 
+1437:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< Core
+1438:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< Core
+1439:Drivers/CMSIS/Include/core_cm4.h **** 
+1440:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< Core
+1441:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< Core
+1442:Drivers/CMSIS/Include/core_cm4.h **** 
+1443:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< Core
+1444:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< Core
+1445:Drivers/CMSIS/Include/core_cm4.h **** 
+1446:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< Core
+1447:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< Core
+1448:Drivers/CMSIS/Include/core_cm4.h **** 
+1449:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< Core
+1450:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< Core
+1451:Drivers/CMSIS/Include/core_cm4.h **** 
+1452:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< Core
+1453:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< Core
+1454:Drivers/CMSIS/Include/core_cm4.h **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 27
+
+
+1455:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< Core
+1456:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< Core
+1457:Drivers/CMSIS/Include/core_cm4.h **** 
+1458:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< Core
+1459:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< Core
+1460:Drivers/CMSIS/Include/core_cm4.h **** 
+1461:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Core Register Selector Register Definitions */
+1462:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< Core
+1463:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< Core
+1464:Drivers/CMSIS/Include/core_cm4.h **** 
+1465:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< Core
+1466:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< Core
+1467:Drivers/CMSIS/Include/core_cm4.h **** 
+1468:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */
+1469:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< Core
+1470:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< Core
+1471:Drivers/CMSIS/Include/core_cm4.h **** 
+1472:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< Core
+1473:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< Core
+1474:Drivers/CMSIS/Include/core_cm4.h **** 
+1475:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< Core
+1476:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< Core
+1477:Drivers/CMSIS/Include/core_cm4.h **** 
+1478:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< Core
+1479:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< Core
+1480:Drivers/CMSIS/Include/core_cm4.h **** 
+1481:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< Core
+1482:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< Core
+1483:Drivers/CMSIS/Include/core_cm4.h **** 
+1484:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< Core
+1485:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< Core
+1486:Drivers/CMSIS/Include/core_cm4.h **** 
+1487:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< Core
+1488:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< Core
+1489:Drivers/CMSIS/Include/core_cm4.h **** 
+1490:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< Core
+1491:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< Core
+1492:Drivers/CMSIS/Include/core_cm4.h **** 
+1493:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< Core
+1494:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< Core
+1495:Drivers/CMSIS/Include/core_cm4.h **** 
+1496:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< Core
+1497:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< Core
+1498:Drivers/CMSIS/Include/core_cm4.h **** 
+1499:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< Core
+1500:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< Core
+1501:Drivers/CMSIS/Include/core_cm4.h **** 
+1502:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< Core
+1503:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< Core
+1504:Drivers/CMSIS/Include/core_cm4.h **** 
+1505:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< Core
+1506:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< Core
+1507:Drivers/CMSIS/Include/core_cm4.h **** 
+1508:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CoreDebug */
+1509:Drivers/CMSIS/Include/core_cm4.h **** 
+1510:Drivers/CMSIS/Include/core_cm4.h **** 
+1511:Drivers/CMSIS/Include/core_cm4.h **** /**
+ARM GAS  /tmp/ccVsbRnC.s 			page 28
+
+
+1512:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup    CMSIS_core_register
+1513:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
+1514:Drivers/CMSIS/Include/core_cm4.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+1515:Drivers/CMSIS/Include/core_cm4.h ****   @{
+1516:Drivers/CMSIS/Include/core_cm4.h ****  */
+1517:Drivers/CMSIS/Include/core_cm4.h **** 
+1518:Drivers/CMSIS/Include/core_cm4.h **** /**
+1519:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
+1520:Drivers/CMSIS/Include/core_cm4.h ****   \param[in] field  Name of the register bit field.
+1521:Drivers/CMSIS/Include/core_cm4.h ****   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+1522:Drivers/CMSIS/Include/core_cm4.h ****   \return           Masked and shifted value.
+1523:Drivers/CMSIS/Include/core_cm4.h **** */
+1524:Drivers/CMSIS/Include/core_cm4.h **** #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+1525:Drivers/CMSIS/Include/core_cm4.h **** 
+1526:Drivers/CMSIS/Include/core_cm4.h **** /**
+1527:Drivers/CMSIS/Include/core_cm4.h ****   \brief     Mask and shift a register value to extract a bit filed value.
+1528:Drivers/CMSIS/Include/core_cm4.h ****   \param[in] field  Name of the register bit field.
+1529:Drivers/CMSIS/Include/core_cm4.h ****   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+1530:Drivers/CMSIS/Include/core_cm4.h ****   \return           Masked and shifted bit field value.
+1531:Drivers/CMSIS/Include/core_cm4.h **** */
+1532:Drivers/CMSIS/Include/core_cm4.h **** #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+1533:Drivers/CMSIS/Include/core_cm4.h **** 
+1534:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_core_bitfield */
+1535:Drivers/CMSIS/Include/core_cm4.h **** 
+1536:Drivers/CMSIS/Include/core_cm4.h **** 
+1537:Drivers/CMSIS/Include/core_cm4.h **** /**
+1538:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup    CMSIS_core_register
+1539:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup   CMSIS_core_base     Core Definitions
+1540:Drivers/CMSIS/Include/core_cm4.h ****   \brief      Definitions for base addresses, unions, and structures.
+1541:Drivers/CMSIS/Include/core_cm4.h ****   @{
+1542:Drivers/CMSIS/Include/core_cm4.h ****  */
+1543:Drivers/CMSIS/Include/core_cm4.h **** 
+1544:Drivers/CMSIS/Include/core_cm4.h **** /* Memory mapping of Core Hardware */
+1545:Drivers/CMSIS/Include/core_cm4.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
+1546:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+1547:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+1548:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+1549:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address 
+1550:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+1551:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+1552:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
+1553:Drivers/CMSIS/Include/core_cm4.h **** 
+1554:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register 
+1555:Drivers/CMSIS/Include/core_cm4.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
+1556:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
+1557:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
+1558:Drivers/CMSIS/Include/core_cm4.h **** #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct
+1559:Drivers/CMSIS/Include/core_cm4.h **** #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct
+1560:Drivers/CMSIS/Include/core_cm4.h **** #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct
+1561:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration
+1562:Drivers/CMSIS/Include/core_cm4.h **** 
+1563:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+1564:Drivers/CMSIS/Include/core_cm4.h ****   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit *
+1565:Drivers/CMSIS/Include/core_cm4.h ****   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit *
+1566:Drivers/CMSIS/Include/core_cm4.h **** #endif
+1567:Drivers/CMSIS/Include/core_cm4.h **** 
+1568:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+ARM GAS  /tmp/ccVsbRnC.s 			page 29
+
+
+1569:Drivers/CMSIS/Include/core_cm4.h **** #define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+1570:Drivers/CMSIS/Include/core_cm4.h **** 
+1571:Drivers/CMSIS/Include/core_cm4.h **** /*@} */
+1572:Drivers/CMSIS/Include/core_cm4.h **** 
+1573:Drivers/CMSIS/Include/core_cm4.h **** 
+1574:Drivers/CMSIS/Include/core_cm4.h **** 
+1575:Drivers/CMSIS/Include/core_cm4.h **** /*******************************************************************************
+1576:Drivers/CMSIS/Include/core_cm4.h ****  *                Hardware Abstraction Layer
+1577:Drivers/CMSIS/Include/core_cm4.h ****   Core Function Interface contains:
+1578:Drivers/CMSIS/Include/core_cm4.h ****   - Core NVIC Functions
+1579:Drivers/CMSIS/Include/core_cm4.h ****   - Core SysTick Functions
+1580:Drivers/CMSIS/Include/core_cm4.h ****   - Core Debug Functions
+1581:Drivers/CMSIS/Include/core_cm4.h ****   - Core Register Access Functions
+1582:Drivers/CMSIS/Include/core_cm4.h ****  ******************************************************************************/
+1583:Drivers/CMSIS/Include/core_cm4.h **** /**
+1584:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+1585:Drivers/CMSIS/Include/core_cm4.h **** */
+1586:Drivers/CMSIS/Include/core_cm4.h **** 
+1587:Drivers/CMSIS/Include/core_cm4.h **** 
+1588:Drivers/CMSIS/Include/core_cm4.h **** 
+1589:Drivers/CMSIS/Include/core_cm4.h **** /* ##########################   NVIC functions  #################################### */
+1590:Drivers/CMSIS/Include/core_cm4.h **** /**
+1591:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_Core_FunctionInterface
+1592:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+1593:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
+1594:Drivers/CMSIS/Include/core_cm4.h ****   @{
+1595:Drivers/CMSIS/Include/core_cm4.h ****  */
+1596:Drivers/CMSIS/Include/core_cm4.h **** 
+1597:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_NVIC_VIRTUAL
+1598:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+1599:Drivers/CMSIS/Include/core_cm4.h ****     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+1600:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+1601:Drivers/CMSIS/Include/core_cm4.h ****   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+1602:Drivers/CMSIS/Include/core_cm4.h **** #else
+1603:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+1604:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+1605:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+1606:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+1607:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+1608:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+1609:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+1610:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+1611:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_GetActive              __NVIC_GetActive
+1612:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_SetPriority            __NVIC_SetPriority
+1613:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_GetPriority            __NVIC_GetPriority
+1614:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_SystemReset            __NVIC_SystemReset
+1615:Drivers/CMSIS/Include/core_cm4.h **** #endif /* CMSIS_NVIC_VIRTUAL */
+1616:Drivers/CMSIS/Include/core_cm4.h **** 
+1617:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_VECTAB_VIRTUAL
+1618:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+1619:Drivers/CMSIS/Include/core_cm4.h ****     #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+1620:Drivers/CMSIS/Include/core_cm4.h ****   #endif
+1621:Drivers/CMSIS/Include/core_cm4.h ****   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+1622:Drivers/CMSIS/Include/core_cm4.h **** #else
+1623:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_SetVector              __NVIC_SetVector
+1624:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_GetVector              __NVIC_GetVector
+1625:Drivers/CMSIS/Include/core_cm4.h **** #endif  /* (CMSIS_VECTAB_VIRTUAL) */
+ARM GAS  /tmp/ccVsbRnC.s 			page 30
+
+
+1626:Drivers/CMSIS/Include/core_cm4.h **** 
+1627:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_USER_IRQ_OFFSET          16
+1628:Drivers/CMSIS/Include/core_cm4.h **** 
+1629:Drivers/CMSIS/Include/core_cm4.h **** 
+1630:Drivers/CMSIS/Include/core_cm4.h **** /* The following EXC_RETURN values are saved the LR on exception entry */
+1631:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after ret
+1632:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after retu
+1633:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after retu
+1634:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after ret
+1635:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after retu
+1636:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after retu
+1637:Drivers/CMSIS/Include/core_cm4.h **** 
+1638:Drivers/CMSIS/Include/core_cm4.h **** 
+1639:Drivers/CMSIS/Include/core_cm4.h **** /**
+1640:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Set Priority Grouping
+1641:Drivers/CMSIS/Include/core_cm4.h ****   \details Sets the priority grouping field using the required unlock sequence.
+1642:Drivers/CMSIS/Include/core_cm4.h ****            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+1643:Drivers/CMSIS/Include/core_cm4.h ****            Only values from 0..7 are used.
+1644:Drivers/CMSIS/Include/core_cm4.h ****            In case of a conflict between priority grouping and available
+1645:Drivers/CMSIS/Include/core_cm4.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+1646:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      PriorityGroup  Priority grouping field.
+1647:Drivers/CMSIS/Include/core_cm4.h ****  */
+1648:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+1649:Drivers/CMSIS/Include/core_cm4.h **** {
+1650:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t reg_value;
+1651:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 a
+1652:Drivers/CMSIS/Include/core_cm4.h **** 
+1653:Drivers/CMSIS/Include/core_cm4.h ****   reg_value  =  SCB->AIRCR;                                                   /* read old register 
+1654:Drivers/CMSIS/Include/core_cm4.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
+1655:Drivers/CMSIS/Include/core_cm4.h ****   reg_value  =  (reg_value                                   |
+1656:Drivers/CMSIS/Include/core_cm4.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+1657:Drivers/CMSIS/Include/core_cm4.h ****                 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key a
+1658:Drivers/CMSIS/Include/core_cm4.h ****   SCB->AIRCR =  reg_value;
+1659:Drivers/CMSIS/Include/core_cm4.h **** }
+1660:Drivers/CMSIS/Include/core_cm4.h **** 
+1661:Drivers/CMSIS/Include/core_cm4.h **** 
+1662:Drivers/CMSIS/Include/core_cm4.h **** /**
+1663:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Get Priority Grouping
+1664:Drivers/CMSIS/Include/core_cm4.h ****   \details Reads the priority grouping field from the NVIC Interrupt Controller.
+1665:Drivers/CMSIS/Include/core_cm4.h ****   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+1666:Drivers/CMSIS/Include/core_cm4.h ****  */
+1667:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+1668:Drivers/CMSIS/Include/core_cm4.h **** {
+1669:Drivers/CMSIS/Include/core_cm4.h ****   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+1670:Drivers/CMSIS/Include/core_cm4.h **** }
+1671:Drivers/CMSIS/Include/core_cm4.h **** 
+1672:Drivers/CMSIS/Include/core_cm4.h **** 
+1673:Drivers/CMSIS/Include/core_cm4.h **** /**
+1674:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Enable Interrupt
+1675:Drivers/CMSIS/Include/core_cm4.h ****   \details Enables a device specific interrupt in the NVIC interrupt controller.
+1676:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
+1677:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
+1678:Drivers/CMSIS/Include/core_cm4.h ****  */
+1679:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+1680:Drivers/CMSIS/Include/core_cm4.h **** {
+  30              		.loc 2 1680 1 view -0
+  31              		.cfi_startproc
+ARM GAS  /tmp/ccVsbRnC.s 			page 31
+
+
+  32              		@ args = 0, pretend = 0, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		@ link register save eliminated.
+1681:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
+  35              		.loc 2 1681 3 view .LVU1
+  36              		.loc 2 1681 6 is_stmt 0 view .LVU2
+  37 0000 0028     		cmp	r0, #0
+  38              	.LVL1:
+  39              		.loc 2 1681 6 view .LVU3
+  40 0002 07DB     		blt	.L1
+1682:Drivers/CMSIS/Include/core_cm4.h ****   {
+1683:Drivers/CMSIS/Include/core_cm4.h ****     __COMPILER_BARRIER();
+  41              		.loc 2 1683 5 is_stmt 1 view .LVU4
+1684:Drivers/CMSIS/Include/core_cm4.h ****     NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  42              		.loc 2 1684 5 view .LVU5
+  43              		.loc 2 1684 81 is_stmt 0 view .LVU6
+  44 0004 00F01F02 		and	r2, r0, #31
+  45              		.loc 2 1684 34 view .LVU7
+  46 0008 4009     		lsrs	r0, r0, #5
+  47              		.loc 2 1684 45 view .LVU8
+  48 000a 0123     		movs	r3, #1
+  49 000c 9340     		lsls	r3, r3, r2
+  50              		.loc 2 1684 43 view .LVU9
+  51 000e 024A     		ldr	r2, .L3
+  52 0010 42F82030 		str	r3, [r2, r0, lsl #2]
+1685:Drivers/CMSIS/Include/core_cm4.h ****     __COMPILER_BARRIER();
+  53              		.loc 2 1685 5 is_stmt 1 view .LVU10
+  54              	.L1:
+1686:Drivers/CMSIS/Include/core_cm4.h ****   }
+1687:Drivers/CMSIS/Include/core_cm4.h **** }
+  55              		.loc 2 1687 1 is_stmt 0 view .LVU11
+  56 0014 7047     		bx	lr
+  57              	.L4:
+  58 0016 00BF     		.align	2
+  59              	.L3:
+  60 0018 00E100E0 		.word	-536813312
+  61              		.cfi_endproc
+  62              	.LFE106:
+  64              		.section	.text.__NVIC_DisableIRQ,"ax",%progbits
+  65              		.align	1
+  66              		.syntax unified
+  67              		.thumb
+  68              		.thumb_func
+  70              	__NVIC_DisableIRQ:
+  71              	.LVL2:
+  72              	.LFB108:
+1688:Drivers/CMSIS/Include/core_cm4.h **** 
+1689:Drivers/CMSIS/Include/core_cm4.h **** 
+1690:Drivers/CMSIS/Include/core_cm4.h **** /**
+1691:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Get Interrupt Enable status
+1692:Drivers/CMSIS/Include/core_cm4.h ****   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+1693:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
+1694:Drivers/CMSIS/Include/core_cm4.h ****   \return             0  Interrupt is not enabled.
+1695:Drivers/CMSIS/Include/core_cm4.h ****   \return             1  Interrupt is enabled.
+1696:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
+1697:Drivers/CMSIS/Include/core_cm4.h ****  */
+1698:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+ARM GAS  /tmp/ccVsbRnC.s 			page 32
+
+
+1699:Drivers/CMSIS/Include/core_cm4.h **** {
+1700:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
+1701:Drivers/CMSIS/Include/core_cm4.h ****   {
+1702:Drivers/CMSIS/Include/core_cm4.h ****     return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
+1703:Drivers/CMSIS/Include/core_cm4.h ****   }
+1704:Drivers/CMSIS/Include/core_cm4.h ****   else
+1705:Drivers/CMSIS/Include/core_cm4.h ****   {
+1706:Drivers/CMSIS/Include/core_cm4.h ****     return(0U);
+1707:Drivers/CMSIS/Include/core_cm4.h ****   }
+1708:Drivers/CMSIS/Include/core_cm4.h **** }
+1709:Drivers/CMSIS/Include/core_cm4.h **** 
+1710:Drivers/CMSIS/Include/core_cm4.h **** 
+1711:Drivers/CMSIS/Include/core_cm4.h **** /**
+1712:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Disable Interrupt
+1713:Drivers/CMSIS/Include/core_cm4.h ****   \details Disables a device specific interrupt in the NVIC interrupt controller.
+1714:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
+1715:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
+1716:Drivers/CMSIS/Include/core_cm4.h ****  */
+1717:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+1718:Drivers/CMSIS/Include/core_cm4.h **** {
+  73              		.loc 2 1718 1 is_stmt 1 view -0
+  74              		.cfi_startproc
+  75              		@ args = 0, pretend = 0, frame = 0
+  76              		@ frame_needed = 0, uses_anonymous_args = 0
+  77              		@ link register save eliminated.
+1719:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
+  78              		.loc 2 1719 3 view .LVU13
+  79              		.loc 2 1719 6 is_stmt 0 view .LVU14
+  80 0000 0028     		cmp	r0, #0
+  81              	.LVL3:
+  82              		.loc 2 1719 6 view .LVU15
+  83 0002 0CDB     		blt	.L5
+1720:Drivers/CMSIS/Include/core_cm4.h ****   {
+1721:Drivers/CMSIS/Include/core_cm4.h ****     NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  84              		.loc 2 1721 5 is_stmt 1 view .LVU16
+  85              		.loc 2 1721 81 is_stmt 0 view .LVU17
+  86 0004 00F01F02 		and	r2, r0, #31
+  87              		.loc 2 1721 34 view .LVU18
+  88 0008 4009     		lsrs	r0, r0, #5
+  89              		.loc 2 1721 45 view .LVU19
+  90 000a 0123     		movs	r3, #1
+  91 000c 9340     		lsls	r3, r3, r2
+  92              		.loc 2 1721 43 view .LVU20
+  93 000e 2030     		adds	r0, r0, #32
+  94 0010 034A     		ldr	r2, .L7
+  95 0012 42F82030 		str	r3, [r2, r0, lsl #2]
+1722:Drivers/CMSIS/Include/core_cm4.h ****     __DSB();
+  96              		.loc 2 1722 5 is_stmt 1 view .LVU21
+  97              	.LBB36:
+  98              	.LBI36:
+  99              		.file 3 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.2.0
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     08. May 2019
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+ARM GAS  /tmp/ccVsbRnC.s 			page 33
+
+
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccVsbRnC.s 			page 34
+
+
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
+ARM GAS  /tmp/ccVsbRnC.s 			page 35
+
+
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
+ARM GAS  /tmp/ccVsbRnC.s 			page 36
+
+
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccVsbRnC.s 			page 37
+
+
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ARM GAS  /tmp/ccVsbRnC.s 			page 38
+
+
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 39
+
+
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/ccVsbRnC.s 			page 40
+
+
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ARM GAS  /tmp/ccVsbRnC.s 			page 41
+
+
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ARM GAS  /tmp/ccVsbRnC.s 			page 42
+
+
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 43
+
+
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ARM GAS  /tmp/ccVsbRnC.s 			page 44
+
+
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccVsbRnC.s 			page 45
+
+
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccVsbRnC.s 			page 46
+
+
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ARM GAS  /tmp/ccVsbRnC.s 			page 47
+
+
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ARM GAS  /tmp/ccVsbRnC.s 			page 48
+
+
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 882:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 883:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 885:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 888:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 900:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 901:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 902:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 904:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 906:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 908:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 913:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 915:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 916:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 918:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 49
+
+
+ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 922:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 923:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 925:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 928:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 930:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 931:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 932:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 938:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 940:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 942:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 943:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+ 100              		.loc 3 944 27 view .LVU22
+ 101              	.LBB37:
+ 945:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 946:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 102              		.loc 3 946 3 view .LVU23
+ 103              		.syntax unified
+ 104              	@ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 105 0016 BFF34F8F 		dsb 0xF
+ 106              	@ 0 "" 2
+ 107              		.thumb
+ 108              		.syntax unified
+ 109              	.LBE37:
+ 110              	.LBE36:
+1723:Drivers/CMSIS/Include/core_cm4.h ****     __ISB();
+ 111              		.loc 2 1723 5 view .LVU24
+ 112              	.LBB38:
+ 113              	.LBI38:
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 114              		.loc 3 933 27 view .LVU25
+ 115              	.LBB39:
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 116              		.loc 3 935 3 view .LVU26
+ 117              		.syntax unified
+ 118              	@ 935 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 119 001a BFF36F8F 		isb 0xF
+ 120              	@ 0 "" 2
+ 121              		.thumb
+ 122              		.syntax unified
+ 123              	.L5:
+ 124              	.LBE39:
+ 125              	.LBE38:
+ARM GAS  /tmp/ccVsbRnC.s 			page 50
+
+
+1724:Drivers/CMSIS/Include/core_cm4.h ****   }
+1725:Drivers/CMSIS/Include/core_cm4.h **** }
+ 126              		.loc 2 1725 1 is_stmt 0 view .LVU27
+ 127 001e 7047     		bx	lr
+ 128              	.L8:
+ 129              		.align	2
+ 130              	.L7:
+ 131 0020 00E100E0 		.word	-536813312
+ 132              		.cfi_endproc
+ 133              	.LFE108:
+ 135              		.section	.text.__NVIC_SetPriority,"ax",%progbits
+ 136              		.align	1
+ 137              		.syntax unified
+ 138              		.thumb
+ 139              		.thumb_func
+ 141              	__NVIC_SetPriority:
+ 142              	.LVL4:
+ 143              	.LFB113:
+1726:Drivers/CMSIS/Include/core_cm4.h **** 
+1727:Drivers/CMSIS/Include/core_cm4.h **** 
+1728:Drivers/CMSIS/Include/core_cm4.h **** /**
+1729:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Get Pending Interrupt
+1730:Drivers/CMSIS/Include/core_cm4.h ****   \details Reads the NVIC pending register and returns the pending bit for the specified device spe
+1731:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
+1732:Drivers/CMSIS/Include/core_cm4.h ****   \return             0  Interrupt status is not pending.
+1733:Drivers/CMSIS/Include/core_cm4.h ****   \return             1  Interrupt status is pending.
+1734:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
+1735:Drivers/CMSIS/Include/core_cm4.h ****  */
+1736:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+1737:Drivers/CMSIS/Include/core_cm4.h **** {
+1738:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
+1739:Drivers/CMSIS/Include/core_cm4.h ****   {
+1740:Drivers/CMSIS/Include/core_cm4.h ****     return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
+1741:Drivers/CMSIS/Include/core_cm4.h ****   }
+1742:Drivers/CMSIS/Include/core_cm4.h ****   else
+1743:Drivers/CMSIS/Include/core_cm4.h ****   {
+1744:Drivers/CMSIS/Include/core_cm4.h ****     return(0U);
+1745:Drivers/CMSIS/Include/core_cm4.h ****   }
+1746:Drivers/CMSIS/Include/core_cm4.h **** }
+1747:Drivers/CMSIS/Include/core_cm4.h **** 
+1748:Drivers/CMSIS/Include/core_cm4.h **** 
+1749:Drivers/CMSIS/Include/core_cm4.h **** /**
+1750:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Set Pending Interrupt
+1751:Drivers/CMSIS/Include/core_cm4.h ****   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+1752:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
+1753:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
+1754:Drivers/CMSIS/Include/core_cm4.h ****  */
+1755:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+1756:Drivers/CMSIS/Include/core_cm4.h **** {
+1757:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
+1758:Drivers/CMSIS/Include/core_cm4.h ****   {
+1759:Drivers/CMSIS/Include/core_cm4.h ****     NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+1760:Drivers/CMSIS/Include/core_cm4.h ****   }
+1761:Drivers/CMSIS/Include/core_cm4.h **** }
+1762:Drivers/CMSIS/Include/core_cm4.h **** 
+1763:Drivers/CMSIS/Include/core_cm4.h **** 
+1764:Drivers/CMSIS/Include/core_cm4.h **** /**
+ARM GAS  /tmp/ccVsbRnC.s 			page 51
+
+
+1765:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Clear Pending Interrupt
+1766:Drivers/CMSIS/Include/core_cm4.h ****   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+1767:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
+1768:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
+1769:Drivers/CMSIS/Include/core_cm4.h ****  */
+1770:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+1771:Drivers/CMSIS/Include/core_cm4.h **** {
+1772:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
+1773:Drivers/CMSIS/Include/core_cm4.h ****   {
+1774:Drivers/CMSIS/Include/core_cm4.h ****     NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+1775:Drivers/CMSIS/Include/core_cm4.h ****   }
+1776:Drivers/CMSIS/Include/core_cm4.h **** }
+1777:Drivers/CMSIS/Include/core_cm4.h **** 
+1778:Drivers/CMSIS/Include/core_cm4.h **** 
+1779:Drivers/CMSIS/Include/core_cm4.h **** /**
+1780:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Get Active Interrupt
+1781:Drivers/CMSIS/Include/core_cm4.h ****   \details Reads the active register in the NVIC and returns the active bit for the device specific
+1782:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
+1783:Drivers/CMSIS/Include/core_cm4.h ****   \return             0  Interrupt status is not active.
+1784:Drivers/CMSIS/Include/core_cm4.h ****   \return             1  Interrupt status is active.
+1785:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
+1786:Drivers/CMSIS/Include/core_cm4.h ****  */
+1787:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+1788:Drivers/CMSIS/Include/core_cm4.h **** {
+1789:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
+1790:Drivers/CMSIS/Include/core_cm4.h ****   {
+1791:Drivers/CMSIS/Include/core_cm4.h ****     return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
+1792:Drivers/CMSIS/Include/core_cm4.h ****   }
+1793:Drivers/CMSIS/Include/core_cm4.h ****   else
+1794:Drivers/CMSIS/Include/core_cm4.h ****   {
+1795:Drivers/CMSIS/Include/core_cm4.h ****     return(0U);
+1796:Drivers/CMSIS/Include/core_cm4.h ****   }
+1797:Drivers/CMSIS/Include/core_cm4.h **** }
+1798:Drivers/CMSIS/Include/core_cm4.h **** 
+1799:Drivers/CMSIS/Include/core_cm4.h **** 
+1800:Drivers/CMSIS/Include/core_cm4.h **** /**
+1801:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Set Interrupt Priority
+1802:Drivers/CMSIS/Include/core_cm4.h ****   \details Sets the priority of a device specific interrupt or a processor exception.
+1803:Drivers/CMSIS/Include/core_cm4.h ****            The interrupt number can be positive to specify a device specific interrupt,
+1804:Drivers/CMSIS/Include/core_cm4.h ****            or negative to specify a processor exception.
+1805:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Interrupt number.
+1806:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]  priority  Priority to set.
+1807:Drivers/CMSIS/Include/core_cm4.h ****   \note    The priority cannot be set for every processor exception.
+1808:Drivers/CMSIS/Include/core_cm4.h ****  */
+1809:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+1810:Drivers/CMSIS/Include/core_cm4.h **** {
+ 144              		.loc 2 1810 1 is_stmt 1 view -0
+ 145              		.cfi_startproc
+ 146              		@ args = 0, pretend = 0, frame = 0
+ 147              		@ frame_needed = 0, uses_anonymous_args = 0
+ 148              		@ link register save eliminated.
+1811:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
+ 149              		.loc 2 1811 3 view .LVU29
+ 150              		.loc 2 1811 6 is_stmt 0 view .LVU30
+ 151 0000 0028     		cmp	r0, #0
+ 152              	.LVL5:
+ 153              		.loc 2 1811 6 view .LVU31
+ARM GAS  /tmp/ccVsbRnC.s 			page 52
+
+
+ 154 0002 08DB     		blt	.L10
+1812:Drivers/CMSIS/Include/core_cm4.h ****   {
+1813:Drivers/CMSIS/Include/core_cm4.h ****     NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u
+ 155              		.loc 2 1813 5 is_stmt 1 view .LVU32
+ 156              		.loc 2 1813 48 is_stmt 0 view .LVU33
+ 157 0004 0901     		lsls	r1, r1, #4
+ 158              	.LVL6:
+ 159              		.loc 2 1813 48 view .LVU34
+ 160 0006 C9B2     		uxtb	r1, r1
+ 161              		.loc 2 1813 46 view .LVU35
+ 162 0008 00F16040 		add	r0, r0, #-536870912
+ 163 000c 00F56140 		add	r0, r0, #57600
+ 164 0010 80F80013 		strb	r1, [r0, #768]
+ 165 0014 7047     		bx	lr
+ 166              	.LVL7:
+ 167              	.L10:
+1814:Drivers/CMSIS/Include/core_cm4.h ****   }
+1815:Drivers/CMSIS/Include/core_cm4.h ****   else
+1816:Drivers/CMSIS/Include/core_cm4.h ****   {
+1817:Drivers/CMSIS/Include/core_cm4.h ****     SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u
+ 168              		.loc 2 1817 5 is_stmt 1 view .LVU36
+ 169              		.loc 2 1817 32 is_stmt 0 view .LVU37
+ 170 0016 00F00F00 		and	r0, r0, #15
+ 171              		.loc 2 1817 48 view .LVU38
+ 172 001a 0901     		lsls	r1, r1, #4
+ 173              	.LVL8:
+ 174              		.loc 2 1817 48 view .LVU39
+ 175 001c C9B2     		uxtb	r1, r1
+ 176              		.loc 2 1817 46 view .LVU40
+ 177 001e 014B     		ldr	r3, .L12
+ 178 0020 1954     		strb	r1, [r3, r0]
+1818:Drivers/CMSIS/Include/core_cm4.h ****   }
+1819:Drivers/CMSIS/Include/core_cm4.h **** }
+ 179              		.loc 2 1819 1 view .LVU41
+ 180 0022 7047     		bx	lr
+ 181              	.L13:
+ 182              		.align	2
+ 183              	.L12:
+ 184 0024 14ED00E0 		.word	-536810220
+ 185              		.cfi_endproc
+ 186              	.LFE113:
+ 188              		.section	.text.__NVIC_GetPriority,"ax",%progbits
+ 189              		.align	1
+ 190              		.syntax unified
+ 191              		.thumb
+ 192              		.thumb_func
+ 194              	__NVIC_GetPriority:
+ 195              	.LVL9:
+ 196              	.LFB114:
+1820:Drivers/CMSIS/Include/core_cm4.h **** 
+1821:Drivers/CMSIS/Include/core_cm4.h **** 
+1822:Drivers/CMSIS/Include/core_cm4.h **** /**
+1823:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Get Interrupt Priority
+1824:Drivers/CMSIS/Include/core_cm4.h ****   \details Reads the priority of a device specific interrupt or a processor exception.
+1825:Drivers/CMSIS/Include/core_cm4.h ****            The interrupt number can be positive to specify a device specific interrupt,
+1826:Drivers/CMSIS/Include/core_cm4.h ****            or negative to specify a processor exception.
+1827:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]   IRQn  Interrupt number.
+ARM GAS  /tmp/ccVsbRnC.s 			page 53
+
+
+1828:Drivers/CMSIS/Include/core_cm4.h ****   \return             Interrupt Priority.
+1829:Drivers/CMSIS/Include/core_cm4.h ****                       Value is aligned automatically to the implemented priority bits of the microc
+1830:Drivers/CMSIS/Include/core_cm4.h ****  */
+1831:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+1832:Drivers/CMSIS/Include/core_cm4.h **** {
+ 197              		.loc 2 1832 1 is_stmt 1 view -0
+ 198              		.cfi_startproc
+ 199              		@ args = 0, pretend = 0, frame = 0
+ 200              		@ frame_needed = 0, uses_anonymous_args = 0
+ 201              		@ link register save eliminated.
+1833:Drivers/CMSIS/Include/core_cm4.h **** 
+1834:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
+ 202              		.loc 2 1834 3 view .LVU43
+ 203              		.loc 2 1834 6 is_stmt 0 view .LVU44
+ 204 0000 0028     		cmp	r0, #0
+ 205              	.LVL10:
+ 206              		.loc 2 1834 6 view .LVU45
+ 207 0002 07DB     		blt	.L15
+1835:Drivers/CMSIS/Include/core_cm4.h ****   {
+1836:Drivers/CMSIS/Include/core_cm4.h ****     return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+ 208              		.loc 2 1836 5 is_stmt 1 view .LVU46
+ 209              		.loc 2 1836 31 is_stmt 0 view .LVU47
+ 210 0004 00F16040 		add	r0, r0, #-536870912
+ 211 0008 00F56140 		add	r0, r0, #57600
+ 212 000c 90F80003 		ldrb	r0, [r0, #768]	@ zero_extendqisi2
+ 213              		.loc 2 1836 64 view .LVU48
+ 214 0010 0009     		lsrs	r0, r0, #4
+ 215 0012 7047     		bx	lr
+ 216              	.L15:
+1837:Drivers/CMSIS/Include/core_cm4.h ****   }
+1838:Drivers/CMSIS/Include/core_cm4.h ****   else
+1839:Drivers/CMSIS/Include/core_cm4.h ****   {
+1840:Drivers/CMSIS/Include/core_cm4.h ****     return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ 217              		.loc 2 1840 5 is_stmt 1 view .LVU49
+ 218              		.loc 2 1840 50 is_stmt 0 view .LVU50
+ 219 0014 00F00F00 		and	r0, r0, #15
+ 220              		.loc 2 1840 31 view .LVU51
+ 221 0018 014B     		ldr	r3, .L17
+ 222 001a 185C     		ldrb	r0, [r3, r0]	@ zero_extendqisi2
+ 223              		.loc 2 1840 64 view .LVU52
+ 224 001c 0009     		lsrs	r0, r0, #4
+1841:Drivers/CMSIS/Include/core_cm4.h ****   }
+1842:Drivers/CMSIS/Include/core_cm4.h **** }
+ 225              		.loc 2 1842 1 view .LVU53
+ 226 001e 7047     		bx	lr
+ 227              	.L18:
+ 228              		.align	2
+ 229              	.L17:
+ 230 0020 14ED00E0 		.word	-536810220
+ 231              		.cfi_endproc
+ 232              	.LFE114:
+ 234              		.section	.text.NVIC_EncodePriority,"ax",%progbits
+ 235              		.align	1
+ 236              		.syntax unified
+ 237              		.thumb
+ 238              		.thumb_func
+ 240              	NVIC_EncodePriority:
+ARM GAS  /tmp/ccVsbRnC.s 			page 54
+
+
+ 241              	.LVL11:
+ 242              	.LFB115:
+1843:Drivers/CMSIS/Include/core_cm4.h **** 
+1844:Drivers/CMSIS/Include/core_cm4.h **** 
+1845:Drivers/CMSIS/Include/core_cm4.h **** /**
+1846:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Encode Priority
+1847:Drivers/CMSIS/Include/core_cm4.h ****   \details Encodes the priority for an interrupt with the given priority group,
+1848:Drivers/CMSIS/Include/core_cm4.h ****            preemptive priority value, and subpriority value.
+1849:Drivers/CMSIS/Include/core_cm4.h ****            In case of a conflict between priority grouping and available
+1850:Drivers/CMSIS/Include/core_cm4.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+1851:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]     PriorityGroup  Used priority group.
+1852:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+1853:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]       SubPriority  Subpriority value (starting from 0).
+1854:Drivers/CMSIS/Include/core_cm4.h ****   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetP
+1855:Drivers/CMSIS/Include/core_cm4.h ****  */
+1856:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
+1857:Drivers/CMSIS/Include/core_cm4.h **** {
+ 243              		.loc 2 1857 1 is_stmt 1 view -0
+ 244              		.cfi_startproc
+ 245              		@ args = 0, pretend = 0, frame = 0
+ 246              		@ frame_needed = 0, uses_anonymous_args = 0
+ 247              		.loc 2 1857 1 is_stmt 0 view .LVU55
+ 248 0000 00B5     		push	{lr}
+ 249              	.LCFI0:
+ 250              		.cfi_def_cfa_offset 4
+ 251              		.cfi_offset 14, -4
+1858:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
+ 252              		.loc 2 1858 3 is_stmt 1 view .LVU56
+ 253              		.loc 2 1858 12 is_stmt 0 view .LVU57
+ 254 0002 00F00700 		and	r0, r0, #7
+ 255              	.LVL12:
+1859:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t PreemptPriorityBits;
+ 256              		.loc 2 1859 3 is_stmt 1 view .LVU58
+1860:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t SubPriorityBits;
+ 257              		.loc 2 1860 3 view .LVU59
+1861:Drivers/CMSIS/Include/core_cm4.h **** 
+1862:Drivers/CMSIS/Include/core_cm4.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
+ 258              		.loc 2 1862 3 view .LVU60
+ 259              		.loc 2 1862 31 is_stmt 0 view .LVU61
+ 260 0006 C0F1070C 		rsb	ip, r0, #7
+ 261              		.loc 2 1862 23 view .LVU62
+ 262 000a BCF1040F 		cmp	ip, #4
+ 263 000e 28BF     		it	cs
+ 264 0010 4FF0040C 		movcs	ip, #4
+ 265              	.LVL13:
+1863:Drivers/CMSIS/Include/core_cm4.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
+ 266              		.loc 2 1863 3 is_stmt 1 view .LVU63
+ 267              		.loc 2 1863 44 is_stmt 0 view .LVU64
+ 268 0014 031D     		adds	r3, r0, #4
+ 269              		.loc 2 1863 109 view .LVU65
+ 270 0016 062B     		cmp	r3, #6
+ 271 0018 0FD9     		bls	.L21
+ 272              		.loc 2 1863 109 discriminator 1 view .LVU66
+ 273 001a C31E     		subs	r3, r0, #3
+ 274              	.L20:
+ 275              	.LVL14:
+1864:Drivers/CMSIS/Include/core_cm4.h **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 55
+
+
+1865:Drivers/CMSIS/Include/core_cm4.h ****   return (
+ 276              		.loc 2 1865 3 is_stmt 1 discriminator 4 view .LVU67
+1866:Drivers/CMSIS/Include/core_cm4.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
+ 277              		.loc 2 1866 30 is_stmt 0 discriminator 4 view .LVU68
+ 278 001c 4FF0FF3E 		mov	lr, #-1
+ 279 0020 0EFA0CF0 		lsl	r0, lr, ip
+ 280              	.LVL15:
+ 281              		.loc 2 1866 30 discriminator 4 view .LVU69
+ 282 0024 21EA0001 		bic	r1, r1, r0
+ 283              	.LVL16:
+ 284              		.loc 2 1866 82 discriminator 4 view .LVU70
+ 285 0028 9940     		lsls	r1, r1, r3
+1867:Drivers/CMSIS/Include/core_cm4.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+ 286              		.loc 2 1867 30 discriminator 4 view .LVU71
+ 287 002a 0EFA03FE 		lsl	lr, lr, r3
+ 288 002e 22EA0E02 		bic	r2, r2, lr
+ 289              	.LVL17:
+1868:Drivers/CMSIS/Include/core_cm4.h ****          );
+1869:Drivers/CMSIS/Include/core_cm4.h **** }
+ 290              		.loc 2 1869 1 discriminator 4 view .LVU72
+ 291 0032 41EA0200 		orr	r0, r1, r2
+ 292 0036 5DF804FB 		ldr	pc, [sp], #4
+ 293              	.LVL18:
+ 294              	.L21:
+1863:Drivers/CMSIS/Include/core_cm4.h **** 
+ 295              		.loc 2 1863 109 view .LVU73
+ 296 003a 0023     		movs	r3, #0
+ 297 003c EEE7     		b	.L20
+ 298              		.cfi_endproc
+ 299              	.LFE115:
+ 301              		.section	.text.NVIC_DecodePriority,"ax",%progbits
+ 302              		.align	1
+ 303              		.syntax unified
+ 304              		.thumb
+ 305              		.thumb_func
+ 307              	NVIC_DecodePriority:
+ 308              	.LVL19:
+ 309              	.LFB116:
+1870:Drivers/CMSIS/Include/core_cm4.h **** 
+1871:Drivers/CMSIS/Include/core_cm4.h **** 
+1872:Drivers/CMSIS/Include/core_cm4.h **** /**
+1873:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Decode Priority
+1874:Drivers/CMSIS/Include/core_cm4.h ****   \details Decodes an interrupt priority value with a given priority group to
+1875:Drivers/CMSIS/Include/core_cm4.h ****            preemptive priority value and subpriority value.
+1876:Drivers/CMSIS/Include/core_cm4.h ****            In case of a conflict between priority grouping and available
+1877:Drivers/CMSIS/Include/core_cm4.h ****            priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+1878:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC
+1879:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]     PriorityGroup  Used priority group.
+1880:Drivers/CMSIS/Include/core_cm4.h ****   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+1881:Drivers/CMSIS/Include/core_cm4.h ****   \param [out]     pSubPriority  Subpriority value (starting from 0).
+1882:Drivers/CMSIS/Include/core_cm4.h ****  */
+1883:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons
+1884:Drivers/CMSIS/Include/core_cm4.h **** {
+ 310              		.loc 2 1884 1 is_stmt 1 view -0
+ 311              		.cfi_startproc
+ 312              		@ args = 0, pretend = 0, frame = 0
+ 313              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccVsbRnC.s 			page 56
+
+
+ 314              		.loc 2 1884 1 is_stmt 0 view .LVU75
+ 315 0000 10B5     		push	{r4, lr}
+ 316              	.LCFI1:
+ 317              		.cfi_def_cfa_offset 8
+ 318              		.cfi_offset 4, -8
+ 319              		.cfi_offset 14, -4
+1885:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
+ 320              		.loc 2 1885 3 is_stmt 1 view .LVU76
+ 321              		.loc 2 1885 12 is_stmt 0 view .LVU77
+ 322 0002 01F00701 		and	r1, r1, #7
+ 323              	.LVL20:
+1886:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t PreemptPriorityBits;
+ 324              		.loc 2 1886 3 is_stmt 1 view .LVU78
+1887:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t SubPriorityBits;
+ 325              		.loc 2 1887 3 view .LVU79
+1888:Drivers/CMSIS/Include/core_cm4.h **** 
+1889:Drivers/CMSIS/Include/core_cm4.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
+ 326              		.loc 2 1889 3 view .LVU80
+ 327              		.loc 2 1889 31 is_stmt 0 view .LVU81
+ 328 0006 C1F1070C 		rsb	ip, r1, #7
+ 329              		.loc 2 1889 23 view .LVU82
+ 330 000a BCF1040F 		cmp	ip, #4
+ 331 000e 28BF     		it	cs
+ 332 0010 4FF0040C 		movcs	ip, #4
+ 333              	.LVL21:
+1890:Drivers/CMSIS/Include/core_cm4.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
+ 334              		.loc 2 1890 3 is_stmt 1 view .LVU83
+ 335              		.loc 2 1890 44 is_stmt 0 view .LVU84
+ 336 0014 0C1D     		adds	r4, r1, #4
+ 337              		.loc 2 1890 109 view .LVU85
+ 338 0016 062C     		cmp	r4, #6
+ 339 0018 0FD9     		bls	.L25
+ 340              		.loc 2 1890 109 discriminator 1 view .LVU86
+ 341 001a 0339     		subs	r1, r1, #3
+ 342              	.LVL22:
+ 343              	.L24:
+1891:Drivers/CMSIS/Include/core_cm4.h **** 
+1892:Drivers/CMSIS/Include/core_cm4.h ****   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1
+ 344              		.loc 2 1892 3 is_stmt 1 discriminator 4 view .LVU87
+ 345              		.loc 2 1892 33 is_stmt 0 discriminator 4 view .LVU88
+ 346 001c 20FA01F4 		lsr	r4, r0, r1
+ 347              	.LVL23:
+ 348              		.loc 2 1892 53 discriminator 4 view .LVU89
+ 349 0020 4FF0FF3E 		mov	lr, #-1
+ 350 0024 0EFA0CFC 		lsl	ip, lr, ip
+ 351              	.LVL24:
+ 352              		.loc 2 1892 53 discriminator 4 view .LVU90
+ 353 0028 24EA0C04 		bic	r4, r4, ip
+ 354              		.loc 2 1892 21 discriminator 4 view .LVU91
+ 355 002c 1460     		str	r4, [r2]
+1893:Drivers/CMSIS/Include/core_cm4.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
+ 356              		.loc 2 1893 3 is_stmt 1 discriminator 4 view .LVU92
+ 357              		.loc 2 1893 53 is_stmt 0 discriminator 4 view .LVU93
+ 358 002e 0EFA01FE 		lsl	lr, lr, r1
+ 359 0032 20EA0E00 		bic	r0, r0, lr
+ 360              	.LVL25:
+ 361              		.loc 2 1893 21 discriminator 4 view .LVU94
+ARM GAS  /tmp/ccVsbRnC.s 			page 57
+
+
+ 362 0036 1860     		str	r0, [r3]
+1894:Drivers/CMSIS/Include/core_cm4.h **** }
+ 363              		.loc 2 1894 1 discriminator 4 view .LVU95
+ 364 0038 10BD     		pop	{r4, pc}
+ 365              	.LVL26:
+ 366              	.L25:
+1890:Drivers/CMSIS/Include/core_cm4.h **** 
+ 367              		.loc 2 1890 109 view .LVU96
+ 368 003a 0021     		movs	r1, #0
+ 369              	.LVL27:
+1890:Drivers/CMSIS/Include/core_cm4.h **** 
+ 370              		.loc 2 1890 109 view .LVU97
+ 371 003c EEE7     		b	.L24
+ 372              		.cfi_endproc
+ 373              	.LFE116:
+ 375              		.section	.text.__NVIC_SystemReset,"ax",%progbits
+ 376              		.align	1
+ 377              		.syntax unified
+ 378              		.thumb
+ 379              		.thumb_func
+ 381              	__NVIC_SystemReset:
+ 382              	.LFB119:
+1895:Drivers/CMSIS/Include/core_cm4.h **** 
+1896:Drivers/CMSIS/Include/core_cm4.h **** 
+1897:Drivers/CMSIS/Include/core_cm4.h **** /**
+1898:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Set Interrupt Vector
+1899:Drivers/CMSIS/Include/core_cm4.h ****   \details Sets an interrupt vector in SRAM based interrupt vector table.
+1900:Drivers/CMSIS/Include/core_cm4.h ****            The interrupt number can be positive to specify a device specific interrupt,
+1901:Drivers/CMSIS/Include/core_cm4.h ****            or negative to specify a processor exception.
+1902:Drivers/CMSIS/Include/core_cm4.h ****            VTOR must been relocated to SRAM before.
+1903:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]   IRQn      Interrupt number
+1904:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]   vector    Address of interrupt handler function
+1905:Drivers/CMSIS/Include/core_cm4.h ****  */
+1906:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+1907:Drivers/CMSIS/Include/core_cm4.h **** {
+1908:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t vectors = (uint32_t )SCB->VTOR;
+1909:Drivers/CMSIS/Include/core_cm4.h ****   (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+1910:Drivers/CMSIS/Include/core_cm4.h ****   /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+1911:Drivers/CMSIS/Include/core_cm4.h **** }
+1912:Drivers/CMSIS/Include/core_cm4.h **** 
+1913:Drivers/CMSIS/Include/core_cm4.h **** 
+1914:Drivers/CMSIS/Include/core_cm4.h **** /**
+1915:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Get Interrupt Vector
+1916:Drivers/CMSIS/Include/core_cm4.h ****   \details Reads an interrupt vector from interrupt vector table.
+1917:Drivers/CMSIS/Include/core_cm4.h ****            The interrupt number can be positive to specify a device specific interrupt,
+1918:Drivers/CMSIS/Include/core_cm4.h ****            or negative to specify a processor exception.
+1919:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]   IRQn      Interrupt number.
+1920:Drivers/CMSIS/Include/core_cm4.h ****   \return                 Address of interrupt handler function
+1921:Drivers/CMSIS/Include/core_cm4.h ****  */
+1922:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+1923:Drivers/CMSIS/Include/core_cm4.h **** {
+1924:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t vectors = (uint32_t )SCB->VTOR;
+1925:Drivers/CMSIS/Include/core_cm4.h ****   return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+1926:Drivers/CMSIS/Include/core_cm4.h **** }
+1927:Drivers/CMSIS/Include/core_cm4.h **** 
+1928:Drivers/CMSIS/Include/core_cm4.h **** 
+1929:Drivers/CMSIS/Include/core_cm4.h **** /**
+ARM GAS  /tmp/ccVsbRnC.s 			page 58
+
+
+1930:Drivers/CMSIS/Include/core_cm4.h ****   \brief   System Reset
+1931:Drivers/CMSIS/Include/core_cm4.h ****   \details Initiates a system reset request to reset the MCU.
+1932:Drivers/CMSIS/Include/core_cm4.h ****  */
+1933:Drivers/CMSIS/Include/core_cm4.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+1934:Drivers/CMSIS/Include/core_cm4.h **** {
+ 383              		.loc 2 1934 1 is_stmt 1 view -0
+ 384              		.cfi_startproc
+ 385              		@ Volatile: function does not return.
+ 386              		@ args = 0, pretend = 0, frame = 0
+ 387              		@ frame_needed = 0, uses_anonymous_args = 0
+ 388              		@ link register save eliminated.
+1935:Drivers/CMSIS/Include/core_cm4.h ****   __DSB();                                                          /* Ensure all outstanding memor
+ 389              		.loc 2 1935 3 view .LVU99
+ 390              	.LBB40:
+ 391              	.LBI40:
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 392              		.loc 3 944 27 view .LVU100
+ 393              	.LBB41:
+ 394              		.loc 3 946 3 view .LVU101
+ 395              		.syntax unified
+ 396              	@ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 397 0000 BFF34F8F 		dsb 0xF
+ 398              	@ 0 "" 2
+ 399              		.thumb
+ 400              		.syntax unified
+ 401              	.LBE41:
+ 402              	.LBE40:
+1936:Drivers/CMSIS/Include/core_cm4.h ****                                                                        buffered write are completed
+1937:Drivers/CMSIS/Include/core_cm4.h ****   SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+ 403              		.loc 2 1937 3 view .LVU102
+1938:Drivers/CMSIS/Include/core_cm4.h ****                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ 404              		.loc 2 1938 32 is_stmt 0 view .LVU103
+ 405 0004 0549     		ldr	r1, .L29
+ 406 0006 CA68     		ldr	r2, [r1, #12]
+ 407              		.loc 2 1938 40 view .LVU104
+ 408 0008 02F4E062 		and	r2, r2, #1792
+1937:Drivers/CMSIS/Include/core_cm4.h ****                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ 409              		.loc 2 1937 17 view .LVU105
+ 410 000c 044B     		ldr	r3, .L29+4
+ 411 000e 1343     		orrs	r3, r3, r2
+1937:Drivers/CMSIS/Include/core_cm4.h ****                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ 412              		.loc 2 1937 15 view .LVU106
+ 413 0010 CB60     		str	r3, [r1, #12]
+1939:Drivers/CMSIS/Include/core_cm4.h ****                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchange
+1940:Drivers/CMSIS/Include/core_cm4.h ****   __DSB();                                                          /* Ensure completion of memory 
+ 414              		.loc 2 1940 3 is_stmt 1 view .LVU107
+ 415              	.LBB42:
+ 416              	.LBI42:
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 417              		.loc 3 944 27 view .LVU108
+ 418              	.LBB43:
+ 419              		.loc 3 946 3 view .LVU109
+ 420              		.syntax unified
+ 421              	@ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 422 0012 BFF34F8F 		dsb 0xF
+ 423              	@ 0 "" 2
+ 424              		.thumb
+ARM GAS  /tmp/ccVsbRnC.s 			page 59
+
+
+ 425              		.syntax unified
+ 426              	.L28:
+ 427              	.LBE43:
+ 428              	.LBE42:
+1941:Drivers/CMSIS/Include/core_cm4.h **** 
+1942:Drivers/CMSIS/Include/core_cm4.h ****   for(;;)                                                           /* wait until reset */
+ 429              		.loc 2 1942 3 discriminator 1 view .LVU110
+1943:Drivers/CMSIS/Include/core_cm4.h ****   {
+1944:Drivers/CMSIS/Include/core_cm4.h ****     __NOP();
+ 430              		.loc 2 1944 5 discriminator 1 view .LVU111
+ 431              		.syntax unified
+ 432              	@ 1944 "Drivers/CMSIS/Include/core_cm4.h" 1
+ 433 0016 00BF     		nop
+ 434              	@ 0 "" 2
+1942:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 435              		.loc 2 1942 3 discriminator 1 view .LVU112
+ 436              		.thumb
+ 437              		.syntax unified
+ 438 0018 FDE7     		b	.L28
+ 439              	.L30:
+ 440 001a 00BF     		.align	2
+ 441              	.L29:
+ 442 001c 00ED00E0 		.word	-536810240
+ 443 0020 0400FA05 		.word	100270084
+ 444              		.cfi_endproc
+ 445              	.LFE119:
+ 447              		.section	.text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits
+ 448              		.align	1
+ 449              		.global	HAL_NVIC_SetPriorityGrouping
+ 450              		.syntax unified
+ 451              		.thumb
+ 452              		.thumb_func
+ 454              	HAL_NVIC_SetPriorityGrouping:
+ 455              	.LVL28:
+ 456              	.LFB329:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @file    stm32g4xx_hal_cortex.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief   CORTEX HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *          functionalities of the CORTEX:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *           + Initialization and Configuration functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *           + Peripheral Control functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   ******************************************************************************
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @attention
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * Copyright (c) 2019 STMicroelectronics.
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * All rights reserved.
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * in the root directory of this software component.
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   ******************************************************************************
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   @verbatim
+ARM GAS  /tmp/ccVsbRnC.s 			page 60
+
+
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   ==============================================================================
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                         ##### How to use this driver #####
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   ==============================================================================
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     [..]
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     *** How to configure Interrupts using CORTEX HAL driver ***
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     ===========================================================
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     [..]
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     This section provides functions allowing to configure the NVIC interrupts (IRQ).
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     The Cortex-M4 exceptions are managed by CMSIS functions.
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****          The pending IRQ priority will be managed only by the sub priority.
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****      -@- IRQ priority order (sorted by highest to lowest priority):
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****         (+@) Lowest pre-emption priority
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****         (+@) Lowest sub priority
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****         (+@) Lowest hardware priority (IRQ number)
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     [..]
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     *** How to configure SysTick using CORTEX HAL driver ***
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     ========================================================
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     [..]
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     Setup SysTick Timer for time base.
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****    (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****        is a CMSIS function that:
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****         (++) Configures the SysTick Reload register with value passed as function parameter.
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****         (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****         (++) Resets the SysTick Counter register.
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****         (++) Enables the SysTick Interrupt.
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****         (++) Starts the SysTick Counter.
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****        inside the stm32g4xx_hal_cortex.h file.
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****    (+) You can change the SysTick IRQ priority by calling the
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****    (+) To adjust the SysTick time base, use the following formula:
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****        (++) Reload Value should not exceed 0xFFFFFF
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   @endverbatim
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   ******************************************************************************
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   The table below gives the allowed values of the pre-emption priority and subpriority according
+ARM GAS  /tmp/ccVsbRnC.s 			page 61
+
+
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     ===============================================================================================
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****       NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |     
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     ===============================================================================================
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****      NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bi
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                            |                                   |                             | 4 bi
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     -----------------------------------------------------------------------------------------------
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****      NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bi
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                            |                                   |                             | 3 bi
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     -----------------------------------------------------------------------------------------------
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****      NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bi
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                            |                                   |                             | 2 bi
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     -----------------------------------------------------------------------------------------------
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****      NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bi
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                            |                                   |                             | 1 bi
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     -----------------------------------------------------------------------------------------------
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****      NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bi
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                            |                                   |                             | 0 bi
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     ===============================================================================================
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** #include "stm32g4xx_hal.h"
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** @addtogroup STM32G4xx_HAL_Driver
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @{
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** @addtogroup CORTEX
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @{
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Private functions ---------------------------------------------------------*/
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @{
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group1
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****  *  @brief    Initialization and Configuration functions
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****  *
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** @verbatim
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   ==============================================================================
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****               ##### Initialization and Configuration functions #####
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   ==============================================================================
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     [..]
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+ARM GAS  /tmp/ccVsbRnC.s 			page 62
+
+
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****       SysTick functionalities
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** @endverbatim
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @{
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Set the priority grouping field (pre-emption priority and subpriority)
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         using the required unlock sequence.
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  PriorityGroup: The priority grouping bits length.
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         This parameter can be one of the following values:
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_0: 0 bit  for pre-emption priority,
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                                    4 bits for subpriority
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_1: 1 bit  for pre-emption priority,
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                                    3 bits for subpriority
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                                    2 bits for subpriority
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                                    1 bit  for subpriority
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                                    0 bit  for subpriority
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         The pending IRQ priority will be managed only by the subpriority.
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 457              		.loc 1 164 1 view -0
+ 458              		.cfi_startproc
+ 459              		@ args = 0, pretend = 0, frame = 0
+ 460              		@ frame_needed = 0, uses_anonymous_args = 0
+ 461              		@ link register save eliminated.
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Check the parameters */
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ 462              		.loc 1 166 3 view .LVU114
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   NVIC_SetPriorityGrouping(PriorityGroup);
+ 463              		.loc 1 169 3 view .LVU115
+ 464              	.LBB44:
+ 465              	.LBI44:
+1648:Drivers/CMSIS/Include/core_cm4.h **** {
+ 466              		.loc 2 1648 22 view .LVU116
+ 467              	.LBB45:
+1650:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 a
+ 468              		.loc 2 1650 3 view .LVU117
+1651:Drivers/CMSIS/Include/core_cm4.h **** 
+ 469              		.loc 2 1651 3 view .LVU118
+1653:Drivers/CMSIS/Include/core_cm4.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
+ 470              		.loc 2 1653 3 view .LVU119
+1653:Drivers/CMSIS/Include/core_cm4.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
+ 471              		.loc 2 1653 14 is_stmt 0 view .LVU120
+ 472 0000 074A     		ldr	r2, .L32
+ 473 0002 D368     		ldr	r3, [r2, #12]
+ 474              	.LVL29:
+1654:Drivers/CMSIS/Include/core_cm4.h ****   reg_value  =  (reg_value                                   |
+ARM GAS  /tmp/ccVsbRnC.s 			page 63
+
+
+ 475              		.loc 2 1654 3 is_stmt 1 view .LVU121
+1654:Drivers/CMSIS/Include/core_cm4.h ****   reg_value  =  (reg_value                                   |
+ 476              		.loc 2 1654 13 is_stmt 0 view .LVU122
+ 477 0004 23F4E063 		bic	r3, r3, #1792
+ 478              	.LVL30:
+1654:Drivers/CMSIS/Include/core_cm4.h ****   reg_value  =  (reg_value                                   |
+ 479              		.loc 2 1654 13 view .LVU123
+ 480 0008 1B04     		lsls	r3, r3, #16
+ 481 000a 1B0C     		lsrs	r3, r3, #16
+ 482              	.LVL31:
+1655:Drivers/CMSIS/Include/core_cm4.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ 483              		.loc 2 1655 3 is_stmt 1 view .LVU124
+1657:Drivers/CMSIS/Include/core_cm4.h ****   SCB->AIRCR =  reg_value;
+ 484              		.loc 2 1657 35 is_stmt 0 view .LVU125
+ 485 000c 0002     		lsls	r0, r0, #8
+ 486              	.LVL32:
+1657:Drivers/CMSIS/Include/core_cm4.h ****   SCB->AIRCR =  reg_value;
+ 487              		.loc 2 1657 35 view .LVU126
+ 488 000e 00F4E060 		and	r0, r0, #1792
+1656:Drivers/CMSIS/Include/core_cm4.h ****                 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key a
+ 489              		.loc 2 1656 62 view .LVU127
+ 490 0012 0343     		orrs	r3, r3, r0
+ 491              	.LVL33:
+1655:Drivers/CMSIS/Include/core_cm4.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ 492              		.loc 2 1655 14 view .LVU128
+ 493 0014 43F0BF63 		orr	r3, r3, #100139008
+ 494 0018 43F40033 		orr	r3, r3, #131072
+ 495              	.LVL34:
+1658:Drivers/CMSIS/Include/core_cm4.h **** }
+ 496              		.loc 2 1658 3 is_stmt 1 view .LVU129
+1658:Drivers/CMSIS/Include/core_cm4.h **** }
+ 497              		.loc 2 1658 14 is_stmt 0 view .LVU130
+ 498 001c D360     		str	r3, [r2, #12]
+ 499              	.LVL35:
+1658:Drivers/CMSIS/Include/core_cm4.h **** }
+ 500              		.loc 2 1658 14 view .LVU131
+ 501              	.LBE45:
+ 502              	.LBE44:
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 503              		.loc 1 170 1 view .LVU132
+ 504 001e 7047     		bx	lr
+ 505              	.L33:
+ 506              		.align	2
+ 507              	.L32:
+ 508 0020 00ED00E0 		.word	-536810240
+ 509              		.cfi_endproc
+ 510              	.LFE329:
+ 512              		.section	.text.HAL_NVIC_SetPriority,"ax",%progbits
+ 513              		.align	1
+ 514              		.global	HAL_NVIC_SetPriority
+ 515              		.syntax unified
+ 516              		.thumb
+ 517              		.thumb_func
+ 519              	HAL_NVIC_SetPriority:
+ 520              	.LVL36:
+ 521              	.LFB330:
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 64
+
+
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Set the priority of an interrupt.
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  IRQn: External interrupt number.
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  PreemptPriority: The pre-emption priority for the IRQn channel.
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         This parameter can be a value between 0 and 15
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         A lower priority value indicates a higher priority
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  SubPriority: the subpriority level for the IRQ channel.
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         This parameter can be a value between 0 and 15
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         A lower priority value indicates a higher priority.
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 522              		.loc 1 186 1 is_stmt 1 view -0
+ 523              		.cfi_startproc
+ 524              		@ args = 0, pretend = 0, frame = 0
+ 525              		@ frame_needed = 0, uses_anonymous_args = 0
+ 526              		.loc 1 186 1 is_stmt 0 view .LVU134
+ 527 0000 10B5     		push	{r4, lr}
+ 528              	.LCFI2:
+ 529              		.cfi_def_cfa_offset 8
+ 530              		.cfi_offset 4, -8
+ 531              		.cfi_offset 14, -4
+ 532 0002 0446     		mov	r4, r0
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   uint32_t prioritygroup;
+ 533              		.loc 1 187 3 is_stmt 1 view .LVU135
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Check the parameters */
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ 534              		.loc 1 190 3 view .LVU136
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+ 535              		.loc 1 191 3 view .LVU137
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   prioritygroup = NVIC_GetPriorityGrouping();
+ 536              		.loc 1 193 3 view .LVU138
+ 537              	.LBB46:
+ 538              	.LBI46:
+1667:Drivers/CMSIS/Include/core_cm4.h **** {
+ 539              		.loc 2 1667 26 view .LVU139
+ 540              	.LBB47:
+1669:Drivers/CMSIS/Include/core_cm4.h **** }
+ 541              		.loc 2 1669 3 view .LVU140
+1669:Drivers/CMSIS/Include/core_cm4.h **** }
+ 542              		.loc 2 1669 26 is_stmt 0 view .LVU141
+ 543 0004 054B     		ldr	r3, .L36
+ 544 0006 D868     		ldr	r0, [r3, #12]
+ 545              	.LVL37:
+1669:Drivers/CMSIS/Include/core_cm4.h **** }
+ 546              		.loc 2 1669 26 view .LVU142
+ 547              	.LBE47:
+ 548              	.LBE46:
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+ 549              		.loc 1 195 3 is_stmt 1 view .LVU143
+ 550 0008 C0F30220 		ubfx	r0, r0, #8, #3
+ARM GAS  /tmp/ccVsbRnC.s 			page 65
+
+
+ 551              	.LVL38:
+ 552              		.loc 1 195 3 is_stmt 0 view .LVU144
+ 553 000c FFF7FEFF 		bl	NVIC_EncodePriority
+ 554              	.LVL39:
+ 555              		.loc 1 195 3 view .LVU145
+ 556 0010 0146     		mov	r1, r0
+ 557 0012 2046     		mov	r0, r4
+ 558 0014 FFF7FEFF 		bl	__NVIC_SetPriority
+ 559              	.LVL40:
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 560              		.loc 1 196 1 view .LVU146
+ 561 0018 10BD     		pop	{r4, pc}
+ 562              	.L37:
+ 563 001a 00BF     		.align	2
+ 564              	.L36:
+ 565 001c 00ED00E0 		.word	-536810240
+ 566              		.cfi_endproc
+ 567              	.LFE330:
+ 569              		.section	.text.HAL_NVIC_EnableIRQ,"ax",%progbits
+ 570              		.align	1
+ 571              		.global	HAL_NVIC_EnableIRQ
+ 572              		.syntax unified
+ 573              		.thumb
+ 574              		.thumb_func
+ 576              	HAL_NVIC_EnableIRQ:
+ 577              	.LVL41:
+ 578              	.LFB331:
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         function should be called before.
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 579              		.loc 1 208 1 is_stmt 1 view -0
+ 580              		.cfi_startproc
+ 581              		@ args = 0, pretend = 0, frame = 0
+ 582              		@ frame_needed = 0, uses_anonymous_args = 0
+ 583              		.loc 1 208 1 is_stmt 0 view .LVU148
+ 584 0000 08B5     		push	{r3, lr}
+ 585              	.LCFI3:
+ 586              		.cfi_def_cfa_offset 8
+ 587              		.cfi_offset 3, -8
+ 588              		.cfi_offset 14, -4
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Check the parameters */
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+ 589              		.loc 1 210 3 is_stmt 1 view .LVU149
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Enable interrupt */
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   NVIC_EnableIRQ(IRQn);
+ 590              		.loc 1 213 3 view .LVU150
+ 591 0002 FFF7FEFF 		bl	__NVIC_EnableIRQ
+ARM GAS  /tmp/ccVsbRnC.s 			page 66
+
+
+ 592              	.LVL42:
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 593              		.loc 1 214 1 is_stmt 0 view .LVU151
+ 594 0006 08BD     		pop	{r3, pc}
+ 595              		.cfi_endproc
+ 596              	.LFE331:
+ 598              		.section	.text.HAL_NVIC_DisableIRQ,"ax",%progbits
+ 599              		.align	1
+ 600              		.global	HAL_NVIC_DisableIRQ
+ 601              		.syntax unified
+ 602              		.thumb
+ 603              		.thumb_func
+ 605              	HAL_NVIC_DisableIRQ:
+ 606              	.LVL43:
+ 607              	.LFB332:
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 608              		.loc 1 224 1 is_stmt 1 view -0
+ 609              		.cfi_startproc
+ 610              		@ args = 0, pretend = 0, frame = 0
+ 611              		@ frame_needed = 0, uses_anonymous_args = 0
+ 612              		.loc 1 224 1 is_stmt 0 view .LVU153
+ 613 0000 08B5     		push	{r3, lr}
+ 614              	.LCFI4:
+ 615              		.cfi_def_cfa_offset 8
+ 616              		.cfi_offset 3, -8
+ 617              		.cfi_offset 14, -4
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Check the parameters */
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+ 618              		.loc 1 226 3 is_stmt 1 view .LVU154
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Disable interrupt */
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   NVIC_DisableIRQ(IRQn);
+ 619              		.loc 1 229 3 view .LVU155
+ 620 0002 FFF7FEFF 		bl	__NVIC_DisableIRQ
+ 621              	.LVL44:
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 622              		.loc 1 230 1 is_stmt 0 view .LVU156
+ 623 0006 08BD     		pop	{r3, pc}
+ 624              		.cfi_endproc
+ 625              	.LFE332:
+ 627              		.section	.text.HAL_NVIC_SystemReset,"ax",%progbits
+ 628              		.align	1
+ 629              		.global	HAL_NVIC_SystemReset
+ 630              		.syntax unified
+ 631              		.thumb
+ 632              		.thumb_func
+ 634              	HAL_NVIC_SystemReset:
+ 635              	.LFB333:
+ARM GAS  /tmp/ccVsbRnC.s 			page 67
+
+
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Initiate a system reset request to reset the MCU.
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void)
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 636              		.loc 1 237 1 is_stmt 1 view -0
+ 637              		.cfi_startproc
+ 638              		@ Volatile: function does not return.
+ 639              		@ args = 0, pretend = 0, frame = 0
+ 640              		@ frame_needed = 0, uses_anonymous_args = 0
+ 641 0000 08B5     		push	{r3, lr}
+ 642              	.LCFI5:
+ 643              		.cfi_def_cfa_offset 8
+ 644              		.cfi_offset 3, -8
+ 645              		.cfi_offset 14, -4
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* System Reset */
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   NVIC_SystemReset();
+ 646              		.loc 1 239 3 view .LVU158
+ 647 0002 FFF7FEFF 		bl	__NVIC_SystemReset
+ 648              	.LVL45:
+ 649              		.cfi_endproc
+ 650              	.LFE333:
+ 652              		.section	.text.HAL_SYSTICK_Config,"ax",%progbits
+ 653              		.align	1
+ 654              		.global	HAL_SYSTICK_Config
+ 655              		.syntax unified
+ 656              		.thumb
+ 657              		.thumb_func
+ 659              	HAL_SYSTICK_Config:
+ 660              	.LVL46:
+ 661              	.LFB334:
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (Sys
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         Counter is in free running mode to generate periodic interrupts.
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval status:  - 0  Function succeeded.
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                  - 1  Function failed.
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 662              		.loc 1 250 1 view -0
+ 663              		.cfi_startproc
+ 664              		@ args = 0, pretend = 0, frame = 0
+ 665              		@ frame_needed = 0, uses_anonymous_args = 0
+ 666              		@ link register save eliminated.
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****    return SysTick_Config(TicksNumb);
+ 667              		.loc 1 251 4 view .LVU160
+ 668              	.LBB48:
+ 669              	.LBI48:
+1945:Drivers/CMSIS/Include/core_cm4.h ****   }
+1946:Drivers/CMSIS/Include/core_cm4.h **** }
+1947:Drivers/CMSIS/Include/core_cm4.h **** 
+1948:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_NVICFunctions */
+ARM GAS  /tmp/ccVsbRnC.s 			page 68
+
+
+1949:Drivers/CMSIS/Include/core_cm4.h **** 
+1950:Drivers/CMSIS/Include/core_cm4.h **** 
+1951:Drivers/CMSIS/Include/core_cm4.h **** /* ##########################  MPU functions  #################################### */
+1952:Drivers/CMSIS/Include/core_cm4.h **** 
+1953:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+1954:Drivers/CMSIS/Include/core_cm4.h **** 
+1955:Drivers/CMSIS/Include/core_cm4.h **** #include "mpu_armv7.h"
+1956:Drivers/CMSIS/Include/core_cm4.h **** 
+1957:Drivers/CMSIS/Include/core_cm4.h **** #endif
+1958:Drivers/CMSIS/Include/core_cm4.h **** 
+1959:Drivers/CMSIS/Include/core_cm4.h **** 
+1960:Drivers/CMSIS/Include/core_cm4.h **** /* ##########################  FPU functions  #################################### */
+1961:Drivers/CMSIS/Include/core_cm4.h **** /**
+1962:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_Core_FunctionInterface
+1963:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_Core_FpuFunctions FPU Functions
+1964:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Function that provides FPU type.
+1965:Drivers/CMSIS/Include/core_cm4.h ****   @{
+1966:Drivers/CMSIS/Include/core_cm4.h ****  */
+1967:Drivers/CMSIS/Include/core_cm4.h **** 
+1968:Drivers/CMSIS/Include/core_cm4.h **** /**
+1969:Drivers/CMSIS/Include/core_cm4.h ****   \brief   get FPU type
+1970:Drivers/CMSIS/Include/core_cm4.h ****   \details returns the FPU type
+1971:Drivers/CMSIS/Include/core_cm4.h ****   \returns
+1972:Drivers/CMSIS/Include/core_cm4.h ****    - \b  0: No FPU
+1973:Drivers/CMSIS/Include/core_cm4.h ****    - \b  1: Single precision FPU
+1974:Drivers/CMSIS/Include/core_cm4.h ****    - \b  2: Double + Single precision FPU
+1975:Drivers/CMSIS/Include/core_cm4.h ****  */
+1976:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void)
+1977:Drivers/CMSIS/Include/core_cm4.h **** {
+1978:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t mvfr0;
+1979:Drivers/CMSIS/Include/core_cm4.h **** 
+1980:Drivers/CMSIS/Include/core_cm4.h ****   mvfr0 = FPU->MVFR0;
+1981:Drivers/CMSIS/Include/core_cm4.h ****   if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+1982:Drivers/CMSIS/Include/core_cm4.h ****   {
+1983:Drivers/CMSIS/Include/core_cm4.h ****     return 1U;           /* Single precision FPU */
+1984:Drivers/CMSIS/Include/core_cm4.h ****   }
+1985:Drivers/CMSIS/Include/core_cm4.h ****   else
+1986:Drivers/CMSIS/Include/core_cm4.h ****   {
+1987:Drivers/CMSIS/Include/core_cm4.h ****     return 0U;           /* No FPU */
+1988:Drivers/CMSIS/Include/core_cm4.h ****   }
+1989:Drivers/CMSIS/Include/core_cm4.h **** }
+1990:Drivers/CMSIS/Include/core_cm4.h **** 
+1991:Drivers/CMSIS/Include/core_cm4.h **** 
+1992:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_FpuFunctions */
+1993:Drivers/CMSIS/Include/core_cm4.h **** 
+1994:Drivers/CMSIS/Include/core_cm4.h **** 
+1995:Drivers/CMSIS/Include/core_cm4.h **** 
+1996:Drivers/CMSIS/Include/core_cm4.h **** /* ##################################    SysTick function  ########################################
+1997:Drivers/CMSIS/Include/core_cm4.h **** /**
+1998:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_Core_FunctionInterface
+1999:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+2000:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Functions that configure the System.
+2001:Drivers/CMSIS/Include/core_cm4.h ****   @{
+2002:Drivers/CMSIS/Include/core_cm4.h ****  */
+2003:Drivers/CMSIS/Include/core_cm4.h **** 
+2004:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+2005:Drivers/CMSIS/Include/core_cm4.h **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 69
+
+
+2006:Drivers/CMSIS/Include/core_cm4.h **** /**
+2007:Drivers/CMSIS/Include/core_cm4.h ****   \brief   System Tick Configuration
+2008:Drivers/CMSIS/Include/core_cm4.h ****   \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+2009:Drivers/CMSIS/Include/core_cm4.h ****            Counter is in free running mode to generate periodic interrupts.
+2010:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]  ticks  Number of ticks between two interrupts.
+2011:Drivers/CMSIS/Include/core_cm4.h ****   \return          0  Function succeeded.
+2012:Drivers/CMSIS/Include/core_cm4.h ****   \return          1  Function failed.
+2013:Drivers/CMSIS/Include/core_cm4.h ****   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+2014:Drivers/CMSIS/Include/core_cm4.h ****            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.
+2015:Drivers/CMSIS/Include/core_cm4.h ****            must contain a vendor-specific implementation of this function.
+2016:Drivers/CMSIS/Include/core_cm4.h ****  */
+2017:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+ 670              		.loc 2 2017 26 view .LVU161
+ 671              	.LBB49:
+2018:Drivers/CMSIS/Include/core_cm4.h **** {
+2019:Drivers/CMSIS/Include/core_cm4.h ****   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ 672              		.loc 2 2019 3 view .LVU162
+ 673              		.loc 2 2019 14 is_stmt 0 view .LVU163
+ 674 0000 0138     		subs	r0, r0, #1
+ 675              	.LVL47:
+ 676              		.loc 2 2019 6 view .LVU164
+ 677 0002 B0F1807F 		cmp	r0, #16777216
+ 678 0006 0BD2     		bcs	.L46
+2020:Drivers/CMSIS/Include/core_cm4.h ****   {
+2021:Drivers/CMSIS/Include/core_cm4.h ****     return (1UL);                                                   /* Reload value impossible */
+2022:Drivers/CMSIS/Include/core_cm4.h ****   }
+2023:Drivers/CMSIS/Include/core_cm4.h **** 
+2024:Drivers/CMSIS/Include/core_cm4.h ****   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+ 679              		.loc 2 2024 3 is_stmt 1 view .LVU165
+ 680              		.loc 2 2024 18 is_stmt 0 view .LVU166
+ 681 0008 4FF0E023 		mov	r3, #-536813568
+ 682 000c 5861     		str	r0, [r3, #20]
+2025:Drivers/CMSIS/Include/core_cm4.h ****   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int
+ 683              		.loc 2 2025 3 is_stmt 1 view .LVU167
+ 684              	.LVL48:
+ 685              	.LBB50:
+ 686              	.LBI50:
+1809:Drivers/CMSIS/Include/core_cm4.h **** {
+ 687              		.loc 2 1809 22 view .LVU168
+ 688              	.LBB51:
+1811:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 689              		.loc 2 1811 3 view .LVU169
+1817:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 690              		.loc 2 1817 5 view .LVU170
+1817:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 691              		.loc 2 1817 46 is_stmt 0 view .LVU171
+ 692 000e 054A     		ldr	r2, .L47
+ 693 0010 F021     		movs	r1, #240
+ 694 0012 82F82310 		strb	r1, [r2, #35]
+ 695              	.LVL49:
+1817:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 696              		.loc 2 1817 46 view .LVU172
+ 697              	.LBE51:
+ 698              	.LBE50:
+2026:Drivers/CMSIS/Include/core_cm4.h ****   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Val
+ 699              		.loc 2 2026 3 is_stmt 1 view .LVU173
+ 700              		.loc 2 2026 18 is_stmt 0 view .LVU174
+ARM GAS  /tmp/ccVsbRnC.s 			page 70
+
+
+ 701 0016 0020     		movs	r0, #0
+ 702              	.LVL50:
+ 703              		.loc 2 2026 18 view .LVU175
+ 704 0018 9861     		str	r0, [r3, #24]
+2027:Drivers/CMSIS/Include/core_cm4.h ****   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+ 705              		.loc 2 2027 3 is_stmt 1 view .LVU176
+ 706              		.loc 2 2027 18 is_stmt 0 view .LVU177
+ 707 001a 0722     		movs	r2, #7
+ 708 001c 1A61     		str	r2, [r3, #16]
+2028:Drivers/CMSIS/Include/core_cm4.h ****                    SysTick_CTRL_TICKINT_Msk   |
+2029:Drivers/CMSIS/Include/core_cm4.h ****                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTi
+2030:Drivers/CMSIS/Include/core_cm4.h ****   return (0UL);                                                     /* Function successful */
+ 709              		.loc 2 2030 3 is_stmt 1 view .LVU178
+ 710              		.loc 2 2030 10 is_stmt 0 view .LVU179
+ 711 001e 7047     		bx	lr
+ 712              	.L46:
+2021:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 713              		.loc 2 2021 12 view .LVU180
+ 714 0020 0120     		movs	r0, #1
+ 715              	.LVL51:
+2021:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 716              		.loc 2 2021 12 view .LVU181
+ 717              	.LBE49:
+ 718              	.LBE48:
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 719              		.loc 1 252 1 view .LVU182
+ 720 0022 7047     		bx	lr
+ 721              	.L48:
+ 722              		.align	2
+ 723              	.L47:
+ 724 0024 00ED00E0 		.word	-536810240
+ 725              		.cfi_endproc
+ 726              	.LFE334:
+ 728              		.section	.text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits
+ 729              		.align	1
+ 730              		.global	HAL_NVIC_GetPriorityGrouping
+ 731              		.syntax unified
+ 732              		.thumb
+ 733              		.thumb_func
+ 735              	HAL_NVIC_GetPriorityGrouping:
+ 736              	.LFB335:
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @}
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group2
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****  *  @brief   Cortex control functions
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****  *
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** @verbatim
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   ==============================================================================
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                       ##### Peripheral Control functions #####
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   ==============================================================================
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     [..]
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****       This subsection provides a set of functions allowing to control the CORTEX
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****       (NVIC, SYSTICK, MPU) functionalities.
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ARM GAS  /tmp/ccVsbRnC.s 			page 71
+
+
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** @endverbatim
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @{
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Get the priority grouping field from the NVIC Interrupt Controller.
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void)
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 737              		.loc 1 278 1 is_stmt 1 view -0
+ 738              		.cfi_startproc
+ 739              		@ args = 0, pretend = 0, frame = 0
+ 740              		@ frame_needed = 0, uses_anonymous_args = 0
+ 741              		@ link register save eliminated.
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Get the PRIGROUP[10:8] field value */
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   return NVIC_GetPriorityGrouping();
+ 742              		.loc 1 280 3 view .LVU184
+ 743              	.LBB52:
+ 744              	.LBI52:
+1667:Drivers/CMSIS/Include/core_cm4.h **** {
+ 745              		.loc 2 1667 26 view .LVU185
+ 746              	.LBB53:
+1669:Drivers/CMSIS/Include/core_cm4.h **** }
+ 747              		.loc 2 1669 3 view .LVU186
+1669:Drivers/CMSIS/Include/core_cm4.h **** }
+ 748              		.loc 2 1669 26 is_stmt 0 view .LVU187
+ 749 0000 024B     		ldr	r3, .L50
+ 750 0002 D868     		ldr	r0, [r3, #12]
+ 751              	.LBE53:
+ 752              	.LBE52:
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 753              		.loc 1 281 1 view .LVU188
+ 754 0004 C0F30220 		ubfx	r0, r0, #8, #3
+ 755 0008 7047     		bx	lr
+ 756              	.L51:
+ 757 000a 00BF     		.align	2
+ 758              	.L50:
+ 759 000c 00ED00E0 		.word	-536810240
+ 760              		.cfi_endproc
+ 761              	.LFE335:
+ 763              		.section	.text.HAL_NVIC_GetPriority,"ax",%progbits
+ 764              		.align	1
+ 765              		.global	HAL_NVIC_GetPriority
+ 766              		.syntax unified
+ 767              		.thumb
+ 768              		.thumb_func
+ 770              	HAL_NVIC_GetPriority:
+ 771              	.LVL52:
+ 772              	.LFB336:
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Get the priority of an interrupt.
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  IRQn: External interrupt number.
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param   PriorityGroup: the priority grouping bits length.
+ARM GAS  /tmp/ccVsbRnC.s 			page 72
+
+
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         This parameter can be one of the following values:
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                                      4 bits for subpriority
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                                      3 bits for subpriority
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                                      2 bits for subpriority
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                                      1 bit for subpriority
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                                      0 bit for subpriority
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint3
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 773              		.loc 1 305 1 is_stmt 1 view -0
+ 774              		.cfi_startproc
+ 775              		@ args = 0, pretend = 0, frame = 0
+ 776              		@ frame_needed = 0, uses_anonymous_args = 0
+ 777              		.loc 1 305 1 is_stmt 0 view .LVU190
+ 778 0000 70B5     		push	{r4, r5, r6, lr}
+ 779              	.LCFI6:
+ 780              		.cfi_def_cfa_offset 16
+ 781              		.cfi_offset 4, -16
+ 782              		.cfi_offset 5, -12
+ 783              		.cfi_offset 6, -8
+ 784              		.cfi_offset 14, -4
+ 785 0002 0C46     		mov	r4, r1
+ 786 0004 1546     		mov	r5, r2
+ 787 0006 1E46     		mov	r6, r3
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Check the parameters */
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ 788              		.loc 1 307 3 is_stmt 1 view .LVU191
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****  /* Get priority for Cortex-M system or device specific interrupts */
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+ 789              		.loc 1 309 3 view .LVU192
+ 790 0008 FFF7FEFF 		bl	__NVIC_GetPriority
+ 791              	.LVL53:
+ 792              		.loc 1 309 3 is_stmt 0 view .LVU193
+ 793 000c 3346     		mov	r3, r6
+ 794 000e 2A46     		mov	r2, r5
+ 795 0010 2146     		mov	r1, r4
+ 796 0012 FFF7FEFF 		bl	NVIC_DecodePriority
+ 797              	.LVL54:
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 798              		.loc 1 310 1 view .LVU194
+ 799 0016 70BD     		pop	{r4, r5, r6, pc}
+ 800              		.loc 1 310 1 view .LVU195
+ 801              		.cfi_endproc
+ 802              	.LFE336:
+ 804              		.section	.text.HAL_NVIC_SetPendingIRQ,"ax",%progbits
+ 805              		.align	1
+ 806              		.global	HAL_NVIC_SetPendingIRQ
+ 807              		.syntax unified
+ 808              		.thumb
+ARM GAS  /tmp/ccVsbRnC.s 			page 73
+
+
+ 809              		.thumb_func
+ 811              	HAL_NVIC_SetPendingIRQ:
+ 812              	.LVL55:
+ 813              	.LFB337:
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Set Pending bit of an external interrupt.
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  IRQn External interrupt number
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 814              		.loc 1 320 1 is_stmt 1 view -0
+ 815              		.cfi_startproc
+ 816              		@ args = 0, pretend = 0, frame = 0
+ 817              		@ frame_needed = 0, uses_anonymous_args = 0
+ 818              		@ link register save eliminated.
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Check the parameters */
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+ 819              		.loc 1 322 3 view .LVU197
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Set interrupt pending */
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   NVIC_SetPendingIRQ(IRQn);
+ 820              		.loc 1 325 3 view .LVU198
+ 821              	.LBB54:
+ 822              	.LBI54:
+1755:Drivers/CMSIS/Include/core_cm4.h **** {
+ 823              		.loc 2 1755 22 view .LVU199
+ 824              	.LBB55:
+1757:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 825              		.loc 2 1757 3 view .LVU200
+1757:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 826              		.loc 2 1757 6 is_stmt 0 view .LVU201
+ 827 0000 0028     		cmp	r0, #0
+ 828              	.LVL56:
+1757:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 829              		.loc 2 1757 6 view .LVU202
+ 830 0002 08DB     		blt	.L54
+1759:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 831              		.loc 2 1759 5 is_stmt 1 view .LVU203
+1759:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 832              		.loc 2 1759 81 is_stmt 0 view .LVU204
+ 833 0004 00F01F02 		and	r2, r0, #31
+1759:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 834              		.loc 2 1759 34 view .LVU205
+ 835 0008 4009     		lsrs	r0, r0, #5
+1759:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 836              		.loc 2 1759 45 view .LVU206
+ 837 000a 0123     		movs	r3, #1
+ 838 000c 9340     		lsls	r3, r3, r2
+1759:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 839              		.loc 2 1759 43 view .LVU207
+ 840 000e 4030     		adds	r0, r0, #64
+ 841 0010 014A     		ldr	r2, .L56
+ 842 0012 42F82030 		str	r3, [r2, r0, lsl #2]
+ARM GAS  /tmp/ccVsbRnC.s 			page 74
+
+
+ 843              	.LVL57:
+ 844              	.L54:
+1759:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 845              		.loc 2 1759 43 view .LVU208
+ 846              	.LBE55:
+ 847              	.LBE54:
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 848              		.loc 1 326 1 view .LVU209
+ 849 0016 7047     		bx	lr
+ 850              	.L57:
+ 851              		.align	2
+ 852              	.L56:
+ 853 0018 00E100E0 		.word	-536813312
+ 854              		.cfi_endproc
+ 855              	.LFE337:
+ 857              		.section	.text.HAL_NVIC_GetPendingIRQ,"ax",%progbits
+ 858              		.align	1
+ 859              		.global	HAL_NVIC_GetPendingIRQ
+ 860              		.syntax unified
+ 861              		.thumb
+ 862              		.thumb_func
+ 864              	HAL_NVIC_GetPendingIRQ:
+ 865              	.LVL58:
+ 866              	.LFB338:
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Get Pending Interrupt (read the pending register in the NVIC
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         and return the pending bit for the specified interrupt).
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *          This parameter can be an enumerator of IRQn_Type enumeration
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval status: - 0  Interrupt status is not pending.
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                 - 1  Interrupt status is pending.
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 867              		.loc 1 338 1 is_stmt 1 view -0
+ 868              		.cfi_startproc
+ 869              		@ args = 0, pretend = 0, frame = 0
+ 870              		@ frame_needed = 0, uses_anonymous_args = 0
+ 871              		@ link register save eliminated.
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Check the parameters */
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+ 872              		.loc 1 340 3 view .LVU211
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Return 1 if pending else 0 */
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   return NVIC_GetPendingIRQ(IRQn);
+ 873              		.loc 1 343 3 view .LVU212
+ 874              	.LBB56:
+ 875              	.LBI56:
+1736:Drivers/CMSIS/Include/core_cm4.h **** {
+ 876              		.loc 2 1736 26 view .LVU213
+ 877              	.LBB57:
+1738:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 878              		.loc 2 1738 3 view .LVU214
+1738:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 879              		.loc 2 1738 6 is_stmt 0 view .LVU215
+ARM GAS  /tmp/ccVsbRnC.s 			page 75
+
+
+ 880 0000 0028     		cmp	r0, #0
+ 881              	.LVL59:
+1738:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 882              		.loc 2 1738 6 view .LVU216
+ 883 0002 0BDB     		blt	.L60
+1740:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 884              		.loc 2 1740 5 is_stmt 1 view .LVU217
+1740:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 885              		.loc 2 1740 54 is_stmt 0 view .LVU218
+ 886 0004 4309     		lsrs	r3, r0, #5
+1740:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 887              		.loc 2 1740 35 view .LVU219
+ 888 0006 4033     		adds	r3, r3, #64
+ 889 0008 054A     		ldr	r2, .L61
+ 890 000a 52F82330 		ldr	r3, [r2, r3, lsl #2]
+1740:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 891              		.loc 2 1740 91 view .LVU220
+ 892 000e 00F01F00 		and	r0, r0, #31
+1740:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 893              		.loc 2 1740 103 view .LVU221
+ 894 0012 23FA00F0 		lsr	r0, r3, r0
+1740:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 895              		.loc 2 1740 12 view .LVU222
+ 896 0016 00F00100 		and	r0, r0, #1
+ 897 001a 7047     		bx	lr
+ 898              	.L60:
+1744:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 899              		.loc 2 1744 11 view .LVU223
+ 900 001c 0020     		movs	r0, #0
+ 901              	.LVL60:
+1744:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 902              		.loc 2 1744 11 view .LVU224
+ 903              	.LBE57:
+ 904              	.LBE56:
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 905              		.loc 1 344 1 view .LVU225
+ 906 001e 7047     		bx	lr
+ 907              	.L62:
+ 908              		.align	2
+ 909              	.L61:
+ 910 0020 00E100E0 		.word	-536813312
+ 911              		.cfi_endproc
+ 912              	.LFE338:
+ 914              		.section	.text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits
+ 915              		.align	1
+ 916              		.global	HAL_NVIC_ClearPendingIRQ
+ 917              		.syntax unified
+ 918              		.thumb
+ 919              		.thumb_func
+ 921              	HAL_NVIC_ClearPendingIRQ:
+ 922              	.LVL61:
+ 923              	.LFB339:
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Clear the pending bit of an external interrupt.
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ARM GAS  /tmp/ccVsbRnC.s 			page 76
+
+
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 924              		.loc 1 354 1 is_stmt 1 view -0
+ 925              		.cfi_startproc
+ 926              		@ args = 0, pretend = 0, frame = 0
+ 927              		@ frame_needed = 0, uses_anonymous_args = 0
+ 928              		@ link register save eliminated.
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Check the parameters */
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+ 929              		.loc 1 356 3 view .LVU227
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Clear pending interrupt */
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   NVIC_ClearPendingIRQ(IRQn);
+ 930              		.loc 1 359 3 view .LVU228
+ 931              	.LBB58:
+ 932              	.LBI58:
+1770:Drivers/CMSIS/Include/core_cm4.h **** {
+ 933              		.loc 2 1770 22 view .LVU229
+ 934              	.LBB59:
+1772:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 935              		.loc 2 1772 3 view .LVU230
+1772:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 936              		.loc 2 1772 6 is_stmt 0 view .LVU231
+ 937 0000 0028     		cmp	r0, #0
+ 938              	.LVL62:
+1772:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 939              		.loc 2 1772 6 view .LVU232
+ 940 0002 08DB     		blt	.L63
+1774:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 941              		.loc 2 1774 5 is_stmt 1 view .LVU233
+1774:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 942              		.loc 2 1774 81 is_stmt 0 view .LVU234
+ 943 0004 00F01F02 		and	r2, r0, #31
+1774:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 944              		.loc 2 1774 34 view .LVU235
+ 945 0008 4009     		lsrs	r0, r0, #5
+1774:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 946              		.loc 2 1774 45 view .LVU236
+ 947 000a 0123     		movs	r3, #1
+ 948 000c 9340     		lsls	r3, r3, r2
+1774:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 949              		.loc 2 1774 43 view .LVU237
+ 950 000e 6030     		adds	r0, r0, #96
+ 951 0010 014A     		ldr	r2, .L65
+ 952 0012 42F82030 		str	r3, [r2, r0, lsl #2]
+ 953              	.LVL63:
+ 954              	.L63:
+1774:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 955              		.loc 2 1774 43 view .LVU238
+ 956              	.LBE59:
+ 957              	.LBE58:
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 958              		.loc 1 360 1 view .LVU239
+ 959 0016 7047     		bx	lr
+ARM GAS  /tmp/ccVsbRnC.s 			page 77
+
+
+ 960              	.L66:
+ 961              		.align	2
+ 962              	.L65:
+ 963 0018 00E100E0 		.word	-536813312
+ 964              		.cfi_endproc
+ 965              	.LFE339:
+ 967              		.section	.text.HAL_NVIC_GetActive,"ax",%progbits
+ 968              		.align	1
+ 969              		.global	HAL_NVIC_GetActive
+ 970              		.syntax unified
+ 971              		.thumb
+ 972              		.thumb_func
+ 974              	HAL_NVIC_GetActive:
+ 975              	.LVL64:
+ 976              	.LFB340:
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief Get active interrupt (read the active register in NVIC and return the active bit).
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param IRQn External interrupt number
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval status: - 0  Interrupt status is not pending.
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                 - 1  Interrupt status is pending.
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 977              		.loc 1 371 1 is_stmt 1 view -0
+ 978              		.cfi_startproc
+ 979              		@ args = 0, pretend = 0, frame = 0
+ 980              		@ frame_needed = 0, uses_anonymous_args = 0
+ 981              		@ link register save eliminated.
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Return 1 if active else 0 */
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   return NVIC_GetActive(IRQn);
+ 982              		.loc 1 373 3 view .LVU241
+ 983              	.LBB60:
+ 984              	.LBI60:
+1787:Drivers/CMSIS/Include/core_cm4.h **** {
+ 985              		.loc 2 1787 26 view .LVU242
+ 986              	.LBB61:
+1789:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 987              		.loc 2 1789 3 view .LVU243
+1789:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 988              		.loc 2 1789 6 is_stmt 0 view .LVU244
+ 989 0000 0028     		cmp	r0, #0
+ 990              	.LVL65:
+1789:Drivers/CMSIS/Include/core_cm4.h ****   {
+ 991              		.loc 2 1789 6 view .LVU245
+ 992 0002 0BDB     		blt	.L69
+1791:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 993              		.loc 2 1791 5 is_stmt 1 view .LVU246
+1791:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 994              		.loc 2 1791 54 is_stmt 0 view .LVU247
+ 995 0004 4309     		lsrs	r3, r0, #5
+1791:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 996              		.loc 2 1791 35 view .LVU248
+ 997 0006 8033     		adds	r3, r3, #128
+ 998 0008 054A     		ldr	r2, .L70
+ARM GAS  /tmp/ccVsbRnC.s 			page 78
+
+
+ 999 000a 52F82330 		ldr	r3, [r2, r3, lsl #2]
+1791:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 1000              		.loc 2 1791 91 view .LVU249
+ 1001 000e 00F01F00 		and	r0, r0, #31
+1791:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 1002              		.loc 2 1791 103 view .LVU250
+ 1003 0012 23FA00F0 		lsr	r0, r3, r0
+1791:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 1004              		.loc 2 1791 12 view .LVU251
+ 1005 0016 00F00100 		and	r0, r0, #1
+ 1006 001a 7047     		bx	lr
+ 1007              	.L69:
+1795:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 1008              		.loc 2 1795 11 view .LVU252
+ 1009 001c 0020     		movs	r0, #0
+ 1010              	.LVL66:
+1795:Drivers/CMSIS/Include/core_cm4.h ****   }
+ 1011              		.loc 2 1795 11 view .LVU253
+ 1012              	.LBE61:
+ 1013              	.LBE60:
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 1014              		.loc 1 374 1 view .LVU254
+ 1015 001e 7047     		bx	lr
+ 1016              	.L71:
+ 1017              		.align	2
+ 1018              	.L70:
+ 1019 0020 00E100E0 		.word	-536813312
+ 1020              		.cfi_endproc
+ 1021              	.LFE340:
+ 1023              		.section	.text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits
+ 1024              		.align	1
+ 1025              		.global	HAL_SYSTICK_CLKSourceConfig
+ 1026              		.syntax unified
+ 1027              		.thumb
+ 1028              		.thumb_func
+ 1030              	HAL_SYSTICK_CLKSourceConfig:
+ 1031              	.LVL67:
+ 1032              	.LFB341:
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Configure the SysTick clock source.
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  CLKSource: specifies the SysTick clock source.
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *          This parameter can be one of the following values:
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock 
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 1033              		.loc 1 385 1 is_stmt 1 view -0
+ 1034              		.cfi_startproc
+ 1035              		@ args = 0, pretend = 0, frame = 0
+ 1036              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1037              		@ link register save eliminated.
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Check the parameters */
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+ 1038              		.loc 1 387 3 view .LVU256
+ARM GAS  /tmp/ccVsbRnC.s 			page 79
+
+
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+ 1039              		.loc 1 388 3 view .LVU257
+ 1040              		.loc 1 388 6 is_stmt 0 view .LVU258
+ 1041 0000 0428     		cmp	r0, #4
+ 1042 0002 06D0     		beq	.L75
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   {
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   }
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   else
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   {
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+ 1043              		.loc 1 394 5 is_stmt 1 view .LVU259
+ 1044              		.loc 1 394 12 is_stmt 0 view .LVU260
+ 1045 0004 4FF0E022 		mov	r2, #-536813568
+ 1046 0008 1369     		ldr	r3, [r2, #16]
+ 1047              		.loc 1 394 19 view .LVU261
+ 1048 000a 23F00403 		bic	r3, r3, #4
+ 1049 000e 1361     		str	r3, [r2, #16]
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   }
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 1050              		.loc 1 396 1 view .LVU262
+ 1051 0010 7047     		bx	lr
+ 1052              	.L75:
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   }
+ 1053              		.loc 1 390 5 is_stmt 1 view .LVU263
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   }
+ 1054              		.loc 1 390 12 is_stmt 0 view .LVU264
+ 1055 0012 4FF0E022 		mov	r2, #-536813568
+ 1056 0016 1369     		ldr	r3, [r2, #16]
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   }
+ 1057              		.loc 1 390 19 view .LVU265
+ 1058 0018 43F00403 		orr	r3, r3, #4
+ 1059 001c 1361     		str	r3, [r2, #16]
+ 1060 001e 7047     		bx	lr
+ 1061              		.cfi_endproc
+ 1062              	.LFE341:
+ 1064              		.section	.text.HAL_SYSTICK_Callback,"ax",%progbits
+ 1065              		.align	1
+ 1066              		.weak	HAL_SYSTICK_Callback
+ 1067              		.syntax unified
+ 1068              		.thumb
+ 1069              		.thumb_func
+ 1071              	HAL_SYSTICK_Callback:
+ 1072              	.LFB343:
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Handle SYSTICK interrupt request.
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void)
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   HAL_SYSTICK_Callback();
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  SYSTICK callback.
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ARM GAS  /tmp/ccVsbRnC.s 			page 80
+
+
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void)
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 1073              		.loc 1 412 1 is_stmt 1 view -0
+ 1074              		.cfi_startproc
+ 1075              		@ args = 0, pretend = 0, frame = 0
+ 1076              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1077              		@ link register save eliminated.
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****             the HAL_SYSTICK_Callback could be implemented in the user file
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****    */
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 1078              		.loc 1 416 1 view .LVU267
+ 1079 0000 7047     		bx	lr
+ 1080              		.cfi_endproc
+ 1081              	.LFE343:
+ 1083              		.section	.text.HAL_SYSTICK_IRQHandler,"ax",%progbits
+ 1084              		.align	1
+ 1085              		.global	HAL_SYSTICK_IRQHandler
+ 1086              		.syntax unified
+ 1087              		.thumb
+ 1088              		.thumb_func
+ 1090              	HAL_SYSTICK_IRQHandler:
+ 1091              	.LFB342:
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   HAL_SYSTICK_Callback();
+ 1092              		.loc 1 403 1 view -0
+ 1093              		.cfi_startproc
+ 1094              		@ args = 0, pretend = 0, frame = 0
+ 1095              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1096 0000 08B5     		push	{r3, lr}
+ 1097              	.LCFI7:
+ 1098              		.cfi_def_cfa_offset 8
+ 1099              		.cfi_offset 3, -8
+ 1100              		.cfi_offset 14, -4
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 1101              		.loc 1 404 3 view .LVU269
+ 1102 0002 FFF7FEFF 		bl	HAL_SYSTICK_Callback
+ 1103              	.LVL68:
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 1104              		.loc 1 405 1 is_stmt 0 view .LVU270
+ 1105 0006 08BD     		pop	{r3, pc}
+ 1106              		.cfi_endproc
+ 1107              	.LFE342:
+ 1109              		.section	.text.HAL_MPU_Enable,"ax",%progbits
+ 1110              		.align	1
+ 1111              		.global	HAL_MPU_Enable
+ 1112              		.syntax unified
+ 1113              		.thumb
+ 1114              		.thumb_func
+ 1116              	HAL_MPU_Enable:
+ 1117              	.LVL69:
+ 1118              	.LFB344:
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** #if (__MPU_PRESENT == 1)
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Enable the MPU.
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
+ARM GAS  /tmp/ccVsbRnC.s 			page 81
+
+
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *          NMI, FAULTMASK and privileged accessto the default memory 
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *          This parameter can be one of the following values:
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *            @arg MPU_HFNMI_PRIVDEF_NONE
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *            @arg MPU_HARDFAULT_NMI
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *            @arg MPU_PRIVILEGED_DEFAULT
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *            @arg MPU_HFNMI_PRIVDEF
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control)
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 1119              		.loc 1 431 1 is_stmt 1 view -0
+ 1120              		.cfi_startproc
+ 1121              		@ args = 0, pretend = 0, frame = 0
+ 1122              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1123              		@ link register save eliminated.
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Enable the MPU */
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
+ 1124              		.loc 1 433 3 view .LVU272
+ 1125              		.loc 1 433 28 is_stmt 0 view .LVU273
+ 1126 0000 40F00100 		orr	r0, r0, #1
+ 1127              	.LVL70:
+ 1128              		.loc 1 433 13 view .LVU274
+ 1129 0004 034B     		ldr	r3, .L80
+ 1130 0006 C3F89400 		str	r0, [r3, #148]
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Ensure MPU setting take effects */
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   __DSB();
+ 1131              		.loc 1 436 3 is_stmt 1 view .LVU275
+ 1132              	.LBB62:
+ 1133              	.LBI62:
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1134              		.loc 3 944 27 view .LVU276
+ 1135              	.LBB63:
+ 1136              		.loc 3 946 3 view .LVU277
+ 1137              		.syntax unified
+ 1138              	@ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1139 000a BFF34F8F 		dsb 0xF
+ 1140              	@ 0 "" 2
+ 1141              		.thumb
+ 1142              		.syntax unified
+ 1143              	.LBE63:
+ 1144              	.LBE62:
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   __ISB();
+ 1145              		.loc 1 437 3 view .LVU278
+ 1146              	.LBB64:
+ 1147              	.LBI64:
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1148              		.loc 3 933 27 view .LVU279
+ 1149              	.LBB65:
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1150              		.loc 3 935 3 view .LVU280
+ 1151              		.syntax unified
+ 1152              	@ 935 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1153 000e BFF36F8F 		isb 0xF
+ 1154              	@ 0 "" 2
+ 1155              		.thumb
+ 1156              		.syntax unified
+ARM GAS  /tmp/ccVsbRnC.s 			page 82
+
+
+ 1157              	.LBE65:
+ 1158              	.LBE64:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 1159              		.loc 1 438 1 is_stmt 0 view .LVU281
+ 1160 0012 7047     		bx	lr
+ 1161              	.L81:
+ 1162              		.align	2
+ 1163              	.L80:
+ 1164 0014 00ED00E0 		.word	-536810240
+ 1165              		.cfi_endproc
+ 1166              	.LFE344:
+ 1168              		.section	.text.HAL_MPU_Disable,"ax",%progbits
+ 1169              		.align	1
+ 1170              		.global	HAL_MPU_Disable
+ 1171              		.syntax unified
+ 1172              		.thumb
+ 1173              		.thumb_func
+ 1175              	HAL_MPU_Disable:
+ 1176              	.LFB345:
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Disable the MPU.
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_MPU_Disable(void)
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 1177              		.loc 1 446 1 is_stmt 1 view -0
+ 1178              		.cfi_startproc
+ 1179              		@ args = 0, pretend = 0, frame = 0
+ 1180              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1181              		@ link register save eliminated.
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Make sure outstanding transfers are done */
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   __DMB();
+ 1182              		.loc 1 448 3 view .LVU283
+ 1183              	.LBB66:
+ 1184              	.LBI66:
+ 947:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 948:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 949:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 950:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ 952:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 953:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 954:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
+ 1185              		.loc 3 955 27 view .LVU284
+ 1186              	.LBB67:
+ 956:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 1187              		.loc 3 957 3 view .LVU285
+ 1188              		.syntax unified
+ 1189              	@ 957 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1190 0000 BFF35F8F 		dmb 0xF
+ 1191              	@ 0 "" 2
+ 1192              		.thumb
+ 1193              		.syntax unified
+ARM GAS  /tmp/ccVsbRnC.s 			page 83
+
+
+ 1194              	.LBE67:
+ 1195              	.LBE66:
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Disable the MPU and clear the control register*/
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   MPU->CTRL  = 0;
+ 1196              		.loc 1 451 3 view .LVU286
+ 1197              		.loc 1 451 14 is_stmt 0 view .LVU287
+ 1198 0004 024B     		ldr	r3, .L83
+ 1199 0006 0022     		movs	r2, #0
+ 1200 0008 C3F89420 		str	r2, [r3, #148]
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 1201              		.loc 1 452 1 view .LVU288
+ 1202 000c 7047     		bx	lr
+ 1203              	.L84:
+ 1204 000e 00BF     		.align	2
+ 1205              	.L83:
+ 1206 0010 00ED00E0 		.word	-536810240
+ 1207              		.cfi_endproc
+ 1208              	.LFE345:
+ 1210              		.section	.text.HAL_MPU_ConfigRegion,"ax",%progbits
+ 1211              		.align	1
+ 1212              		.global	HAL_MPU_ConfigRegion
+ 1213              		.syntax unified
+ 1214              		.thumb
+ 1215              		.thumb_func
+ 1217              	HAL_MPU_ConfigRegion:
+ 1218              	.LVL71:
+ 1219              	.LFB346:
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @brief  Initialize and configure the Region and the memory to be protected.
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   *                the initialization and configuration information.
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   * @retval None
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   */
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
+ 1220              		.loc 1 462 1 is_stmt 1 view -0
+ 1221              		.cfi_startproc
+ 1222              		@ args = 0, pretend = 0, frame = 0
+ 1223              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1224              		@ link register save eliminated.
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Check the parameters */
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+ 1225              		.loc 1 464 3 view .LVU290
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+ 1226              		.loc 1 465 3 view .LVU291
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   /* Set the Region number */
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   MPU->RNR = MPU_Init->Number;
+ 1227              		.loc 1 468 3 view .LVU292
+ 1228              		.loc 1 468 22 is_stmt 0 view .LVU293
+ 1229 0000 4278     		ldrb	r2, [r0, #1]	@ zero_extendqisi2
+ 1230              		.loc 1 468 12 view .LVU294
+ 1231 0002 164B     		ldr	r3, .L88
+ 1232 0004 C3F89820 		str	r2, [r3, #152]
+ARM GAS  /tmp/ccVsbRnC.s 			page 84
+
+
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   if ((MPU_Init->Enable) != 0U)
+ 1233              		.loc 1 470 3 is_stmt 1 view .LVU295
+ 1234              		.loc 1 470 16 is_stmt 0 view .LVU296
+ 1235 0008 0378     		ldrb	r3, [r0]	@ zero_extendqisi2
+ 1236              		.loc 1 470 6 view .LVU297
+ 1237 000a FBB1     		cbz	r3, .L86
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   {
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     /* Check the parameters */
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ 1238              		.loc 1 473 5 is_stmt 1 view .LVU298
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ 1239              		.loc 1 474 5 view .LVU299
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ 1240              		.loc 1 475 5 view .LVU300
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ 1241              		.loc 1 476 5 view .LVU301
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ 1242              		.loc 1 477 5 view .LVU302
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ 1243              		.loc 1 478 5 view .LVU303
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ 1244              		.loc 1 479 5 view .LVU304
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+ 1245              		.loc 1 480 5 view .LVU305
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     MPU->RBAR = MPU_Init->BaseAddress;
+ 1246              		.loc 1 482 5 view .LVU306
+ 1247              		.loc 1 482 25 is_stmt 0 view .LVU307
+ 1248 000c 4368     		ldr	r3, [r0, #4]
+ 1249              		.loc 1 482 15 view .LVU308
+ 1250 000e 134A     		ldr	r2, .L88
+ 1251 0010 C2F89C30 		str	r3, [r2, #156]
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     MPU->RASR = ((uint32_t)MPU_Init->DisableExec        << MPU_RASR_XN_Pos)   |
+ 1252              		.loc 1 483 5 is_stmt 1 view .LVU309
+ 1253              		.loc 1 483 36 is_stmt 0 view .LVU310
+ 1254 0014 017B     		ldrb	r1, [r0, #12]	@ zero_extendqisi2
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->AccessPermission   << MPU_RASR_AP_Pos)   |
+ 1255              		.loc 1 484 36 view .LVU311
+ 1256 0016 C37A     		ldrb	r3, [r0, #11]	@ zero_extendqisi2
+ 1257              		.loc 1 484 57 view .LVU312
+ 1258 0018 1B06     		lsls	r3, r3, #24
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     MPU->RASR = ((uint32_t)MPU_Init->DisableExec        << MPU_RASR_XN_Pos)   |
+ 1259              		.loc 1 483 79 view .LVU313
+ 1260 001a 43EA0173 		orr	r3, r3, r1, lsl #28
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->TypeExtField       << MPU_RASR_TEX_Pos)  |
+ 1261              		.loc 1 485 36 view .LVU314
+ 1262 001e 817A     		ldrb	r1, [r0, #10]	@ zero_extendqisi2
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->AccessPermission   << MPU_RASR_AP_Pos)   |
+ 1263              		.loc 1 484 79 view .LVU315
+ 1264 0020 43EAC143 		orr	r3, r3, r1, lsl #19
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsShareable        << MPU_RASR_S_Pos)    |
+ 1265              		.loc 1 486 36 view .LVU316
+ 1266 0024 417B     		ldrb	r1, [r0, #13]	@ zero_extendqisi2
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->TypeExtField       << MPU_RASR_TEX_Pos)  |
+ 1267              		.loc 1 485 79 view .LVU317
+ 1268 0026 43EA8143 		orr	r3, r3, r1, lsl #18
+ARM GAS  /tmp/ccVsbRnC.s 			page 85
+
+
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsCacheable        << MPU_RASR_C_Pos)    |
+ 1269              		.loc 1 487 36 view .LVU318
+ 1270 002a 817B     		ldrb	r1, [r0, #14]	@ zero_extendqisi2
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsShareable        << MPU_RASR_S_Pos)    |
+ 1271              		.loc 1 486 79 view .LVU319
+ 1272 002c 43EA4143 		orr	r3, r3, r1, lsl #17
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsBufferable       << MPU_RASR_B_Pos)    |
+ 1273              		.loc 1 488 36 view .LVU320
+ 1274 0030 C17B     		ldrb	r1, [r0, #15]	@ zero_extendqisi2
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsCacheable        << MPU_RASR_C_Pos)    |
+ 1275              		.loc 1 487 79 view .LVU321
+ 1276 0032 43EA0143 		orr	r3, r3, r1, lsl #16
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->SubRegionDisable   << MPU_RASR_SRD_Pos)  |
+ 1277              		.loc 1 489 36 view .LVU322
+ 1278 0036 417A     		ldrb	r1, [r0, #9]	@ zero_extendqisi2
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsBufferable       << MPU_RASR_B_Pos)    |
+ 1279              		.loc 1 488 79 view .LVU323
+ 1280 0038 43EA0123 		orr	r3, r3, r1, lsl #8
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->Size               << MPU_RASR_SIZE_Pos) |
+ 1281              		.loc 1 490 36 view .LVU324
+ 1282 003c 017A     		ldrb	r1, [r0, #8]	@ zero_extendqisi2
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->SubRegionDisable   << MPU_RASR_SRD_Pos)  |
+ 1283              		.loc 1 489 79 view .LVU325
+ 1284 003e 43EA4103 		orr	r3, r3, r1, lsl #1
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->Enable             << MPU_RASR_ENABLE_Pos);
+ 1285              		.loc 1 491 36 view .LVU326
+ 1286 0042 0178     		ldrb	r1, [r0]	@ zero_extendqisi2
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->Size               << MPU_RASR_SIZE_Pos) |
+ 1287              		.loc 1 490 79 view .LVU327
+ 1288 0044 0B43     		orrs	r3, r3, r1
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->AccessPermission   << MPU_RASR_AP_Pos)   |
+ 1289              		.loc 1 483 15 view .LVU328
+ 1290 0046 C2F8A030 		str	r3, [r2, #160]
+ 1291 004a 7047     		bx	lr
+ 1292              	.L86:
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   }
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   else
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   {
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     MPU->RBAR = 0x00;
+ 1293              		.loc 1 495 5 is_stmt 1 view .LVU329
+ 1294              		.loc 1 495 15 is_stmt 0 view .LVU330
+ 1295 004c 034B     		ldr	r3, .L88
+ 1296 004e 0022     		movs	r2, #0
+ 1297 0050 C3F89C20 		str	r2, [r3, #156]
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****     MPU->RASR = 0x00;
+ 1298              		.loc 1 496 5 is_stmt 1 view .LVU331
+ 1299              		.loc 1 496 15 is_stmt 0 view .LVU332
+ 1300 0054 C3F8A020 		str	r2, [r3, #160]
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****   }
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
+ 1301              		.loc 1 498 1 view .LVU333
+ 1302 0058 7047     		bx	lr
+ 1303              	.L89:
+ 1304 005a 00BF     		.align	2
+ 1305              	.L88:
+ 1306 005c 00ED00E0 		.word	-536810240
+ 1307              		.cfi_endproc
+ARM GAS  /tmp/ccVsbRnC.s 			page 86
+
+
+ 1308              	.LFE346:
+ 1310              		.text
+ 1311              	.Letext0:
+ 1312              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 1313              		.file 5 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 1314              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"
+ARM GAS  /tmp/ccVsbRnC.s 			page 87
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_cortex.c
+     /tmp/ccVsbRnC.s:21     .text.__NVIC_EnableIRQ:00000000 $t
+     /tmp/ccVsbRnC.s:26     .text.__NVIC_EnableIRQ:00000000 __NVIC_EnableIRQ
+     /tmp/ccVsbRnC.s:60     .text.__NVIC_EnableIRQ:00000018 $d
+     /tmp/ccVsbRnC.s:65     .text.__NVIC_DisableIRQ:00000000 $t
+     /tmp/ccVsbRnC.s:70     .text.__NVIC_DisableIRQ:00000000 __NVIC_DisableIRQ
+     /tmp/ccVsbRnC.s:131    .text.__NVIC_DisableIRQ:00000020 $d
+     /tmp/ccVsbRnC.s:136    .text.__NVIC_SetPriority:00000000 $t
+     /tmp/ccVsbRnC.s:141    .text.__NVIC_SetPriority:00000000 __NVIC_SetPriority
+     /tmp/ccVsbRnC.s:184    .text.__NVIC_SetPriority:00000024 $d
+     /tmp/ccVsbRnC.s:189    .text.__NVIC_GetPriority:00000000 $t
+     /tmp/ccVsbRnC.s:194    .text.__NVIC_GetPriority:00000000 __NVIC_GetPriority
+     /tmp/ccVsbRnC.s:230    .text.__NVIC_GetPriority:00000020 $d
+     /tmp/ccVsbRnC.s:235    .text.NVIC_EncodePriority:00000000 $t
+     /tmp/ccVsbRnC.s:240    .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority
+     /tmp/ccVsbRnC.s:302    .text.NVIC_DecodePriority:00000000 $t
+     /tmp/ccVsbRnC.s:307    .text.NVIC_DecodePriority:00000000 NVIC_DecodePriority
+     /tmp/ccVsbRnC.s:376    .text.__NVIC_SystemReset:00000000 $t
+     /tmp/ccVsbRnC.s:381    .text.__NVIC_SystemReset:00000000 __NVIC_SystemReset
+     /tmp/ccVsbRnC.s:442    .text.__NVIC_SystemReset:0000001c $d
+     /tmp/ccVsbRnC.s:448    .text.HAL_NVIC_SetPriorityGrouping:00000000 $t
+     /tmp/ccVsbRnC.s:454    .text.HAL_NVIC_SetPriorityGrouping:00000000 HAL_NVIC_SetPriorityGrouping
+     /tmp/ccVsbRnC.s:508    .text.HAL_NVIC_SetPriorityGrouping:00000020 $d
+     /tmp/ccVsbRnC.s:513    .text.HAL_NVIC_SetPriority:00000000 $t
+     /tmp/ccVsbRnC.s:519    .text.HAL_NVIC_SetPriority:00000000 HAL_NVIC_SetPriority
+     /tmp/ccVsbRnC.s:565    .text.HAL_NVIC_SetPriority:0000001c $d
+     /tmp/ccVsbRnC.s:570    .text.HAL_NVIC_EnableIRQ:00000000 $t
+     /tmp/ccVsbRnC.s:576    .text.HAL_NVIC_EnableIRQ:00000000 HAL_NVIC_EnableIRQ
+     /tmp/ccVsbRnC.s:599    .text.HAL_NVIC_DisableIRQ:00000000 $t
+     /tmp/ccVsbRnC.s:605    .text.HAL_NVIC_DisableIRQ:00000000 HAL_NVIC_DisableIRQ
+     /tmp/ccVsbRnC.s:628    .text.HAL_NVIC_SystemReset:00000000 $t
+     /tmp/ccVsbRnC.s:634    .text.HAL_NVIC_SystemReset:00000000 HAL_NVIC_SystemReset
+     /tmp/ccVsbRnC.s:653    .text.HAL_SYSTICK_Config:00000000 $t
+     /tmp/ccVsbRnC.s:659    .text.HAL_SYSTICK_Config:00000000 HAL_SYSTICK_Config
+     /tmp/ccVsbRnC.s:724    .text.HAL_SYSTICK_Config:00000024 $d
+     /tmp/ccVsbRnC.s:729    .text.HAL_NVIC_GetPriorityGrouping:00000000 $t
+     /tmp/ccVsbRnC.s:735    .text.HAL_NVIC_GetPriorityGrouping:00000000 HAL_NVIC_GetPriorityGrouping
+     /tmp/ccVsbRnC.s:759    .text.HAL_NVIC_GetPriorityGrouping:0000000c $d
+     /tmp/ccVsbRnC.s:764    .text.HAL_NVIC_GetPriority:00000000 $t
+     /tmp/ccVsbRnC.s:770    .text.HAL_NVIC_GetPriority:00000000 HAL_NVIC_GetPriority
+     /tmp/ccVsbRnC.s:805    .text.HAL_NVIC_SetPendingIRQ:00000000 $t
+     /tmp/ccVsbRnC.s:811    .text.HAL_NVIC_SetPendingIRQ:00000000 HAL_NVIC_SetPendingIRQ
+     /tmp/ccVsbRnC.s:853    .text.HAL_NVIC_SetPendingIRQ:00000018 $d
+     /tmp/ccVsbRnC.s:858    .text.HAL_NVIC_GetPendingIRQ:00000000 $t
+     /tmp/ccVsbRnC.s:864    .text.HAL_NVIC_GetPendingIRQ:00000000 HAL_NVIC_GetPendingIRQ
+     /tmp/ccVsbRnC.s:910    .text.HAL_NVIC_GetPendingIRQ:00000020 $d
+     /tmp/ccVsbRnC.s:915    .text.HAL_NVIC_ClearPendingIRQ:00000000 $t
+     /tmp/ccVsbRnC.s:921    .text.HAL_NVIC_ClearPendingIRQ:00000000 HAL_NVIC_ClearPendingIRQ
+     /tmp/ccVsbRnC.s:963    .text.HAL_NVIC_ClearPendingIRQ:00000018 $d
+     /tmp/ccVsbRnC.s:968    .text.HAL_NVIC_GetActive:00000000 $t
+     /tmp/ccVsbRnC.s:974    .text.HAL_NVIC_GetActive:00000000 HAL_NVIC_GetActive
+     /tmp/ccVsbRnC.s:1019   .text.HAL_NVIC_GetActive:00000020 $d
+     /tmp/ccVsbRnC.s:1024   .text.HAL_SYSTICK_CLKSourceConfig:00000000 $t
+     /tmp/ccVsbRnC.s:1030   .text.HAL_SYSTICK_CLKSourceConfig:00000000 HAL_SYSTICK_CLKSourceConfig
+     /tmp/ccVsbRnC.s:1065   .text.HAL_SYSTICK_Callback:00000000 $t
+     /tmp/ccVsbRnC.s:1071   .text.HAL_SYSTICK_Callback:00000000 HAL_SYSTICK_Callback
+ARM GAS  /tmp/ccVsbRnC.s 			page 88
+
+
+     /tmp/ccVsbRnC.s:1084   .text.HAL_SYSTICK_IRQHandler:00000000 $t
+     /tmp/ccVsbRnC.s:1090   .text.HAL_SYSTICK_IRQHandler:00000000 HAL_SYSTICK_IRQHandler
+     /tmp/ccVsbRnC.s:1110   .text.HAL_MPU_Enable:00000000 $t
+     /tmp/ccVsbRnC.s:1116   .text.HAL_MPU_Enable:00000000 HAL_MPU_Enable
+     /tmp/ccVsbRnC.s:1164   .text.HAL_MPU_Enable:00000014 $d
+     /tmp/ccVsbRnC.s:1169   .text.HAL_MPU_Disable:00000000 $t
+     /tmp/ccVsbRnC.s:1175   .text.HAL_MPU_Disable:00000000 HAL_MPU_Disable
+     /tmp/ccVsbRnC.s:1206   .text.HAL_MPU_Disable:00000010 $d
+     /tmp/ccVsbRnC.s:1211   .text.HAL_MPU_ConfigRegion:00000000 $t
+     /tmp/ccVsbRnC.s:1217   .text.HAL_MPU_ConfigRegion:00000000 HAL_MPU_ConfigRegion
+     /tmp/ccVsbRnC.s:1306   .text.HAL_MPU_ConfigRegion:0000005c $d
+
+NO UNDEFINED SYMBOLS
diff --git a/squeow_sw/build/stm32g4xx_hal_cortex.o b/squeow_sw/build/stm32g4xx_hal_cortex.o
new file mode 100644
index 0000000000000000000000000000000000000000..38bad6156ca8e4fe395f654e7c7f7aebceb2a4e8
GIT binary patch
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diff --git a/squeow_sw/build/stm32g4xx_hal_dma.d b/squeow_sw/build/stm32g4xx_hal_dma.d
new file mode 100644
index 0000000..e4464a4
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_dma.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_dma.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_dma.lst b/squeow_sw/build/stm32g4xx_hal_dma.lst
new file mode 100644
index 0000000..238971c
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_dma.lst
@@ -0,0 +1,3886 @@
+ARM GAS  /tmp/ccCGP7ew.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_dma.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c"
+  20              		.section	.text.DMA_SetConfig,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	DMA_SetConfig:
+  27              	.LVL0:
+  28              	.LFB341:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @file    stm32g4xx_hal_dma.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief   DMA HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *         This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *         functionalities of the Direct Memory Access (DMA) peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *           + IO operation functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *           + Peripheral State and errors functions
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   ******************************************************************************
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @attention
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * Copyright (c) 2019 STMicroelectronics.
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * All rights reserved.
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * in the root directory of this software component.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   ******************************************************************************
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   @verbatim
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   ==============================================================================
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****                         ##### How to use this driver #####
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   ==============================================================================
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   [..]
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****    (#) Enable and configure the peripheral to be connected to the DMA Channel
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        (except for internal SRAM / FLASH memories: no initialization is
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        necessary). Please refer to the Reference manual for connection between peripherals
+ARM GAS  /tmp/ccCGP7ew.s 			page 2
+
+
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        and DMA requests.
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****    (#) For a given Channel, program the required configuration through the following parameters:
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        Channel request, Transfer Direction, Source and Destination data formats,
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        using HAL_DMA_Init() function.
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        thanks to:
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or  __HAL_RCC_DMA2_CLK_ENABLE() ;
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       (##) DMAMUX1:      __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****    (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of er
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        detection.
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****    (#) Use HAL_DMA_Abort() function to abort the current transfer
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      *** Polling mode IO operation ***
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      =================================
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     [..]
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****               address and destination address and the Length of data to be transferred
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****               case a fixed Timeout can be configured by User depending from his application.
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      *** Interrupt mode IO operation ***
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      ===================================
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     [..]
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****               Source address and destination address and the Length of data to be transferred.
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****               In this case the DMA interrupt is configured
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****               add his own function to register callbacks with HAL_DMA_RegisterCallback().
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      *** DMA HAL driver macros list ***
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      =============================================
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       [..]
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        Below the list of macros in DMA HAL driver.
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred 
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      [..]
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       (@) You can refer to the DMA HAL driver header file for more useful macros
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   @endverbatim
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ARM GAS  /tmp/ccCGP7ew.s 			page 3
+
+
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /* Includes ------------------------------------------------------------------*/
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** #include "stm32g4xx_hal.h"
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @{
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /** @defgroup DMA DMA
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief DMA HAL module driver
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @{
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** #ifdef HAL_DMA_MODULE_ENABLED
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /* Private typedef -----------------------------------------------------------*/
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /* Private define ------------------------------------------------------------*/
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /* Private macro -------------------------------------------------------------*/
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /* Private variables ---------------------------------------------------------*/
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /* Private function prototypes -----------------------------------------------*/
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /** @defgroup DMA_Private_Functions DMA Private Functions
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @{
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @}
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /* Exported functions ---------------------------------------------------------*/
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions DMA Exported Functions
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @{
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *  @brief   Initialization and de-initialization functions
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** @verbatim
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****  ===============================================================================
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****              ##### Initialization and de-initialization functions  #####
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****  ===============================================================================
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     [..]
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     This section provides functions allowing to initialize the DMA Channel source
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     and destination addresses, incrementation and data sizes, transfer direction,
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     [..]
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     reference manual.
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** @endverbatim
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @{
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ARM GAS  /tmp/ccCGP7ew.s 			page 4
+
+
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Initialize the DMA according to the specified
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *         parameters in the DMA_InitTypeDef and initialize the associated handle.
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *               the configuration information for the specified DMA Channel.
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval HAL status
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t tmp;
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Check the DMA handle allocation */
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (hdma == NULL)
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     return HAL_ERROR;
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Check the parameters */
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Compute the channel index */
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* DMA1 */
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Ch
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA1;
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* DMA2 */
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Ch
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA2;
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Change DMA peripheral state */
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->State = HAL_DMA_STATE_BUSY;
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Get the CR register value */
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   tmp = hdma->Instance->CCR;
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  |
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****                       DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****                       DMA_CCR_DIR   | DMA_CCR_MEM2MEM));
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Prepare the DMA Channel configuration */
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   tmp |=  hdma->Init.Direction        |
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ARM GAS  /tmp/ccCGP7ew.s 			page 5
+
+
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.Mode                | hdma->Init.Priority;
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Write to DMA Channel CR register */
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->Instance->CCR = tmp;
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Initialize parameters for DMAMUX channel :
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* if memory to memory force the request to 0*/
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->Init.Request = DMA_REQUEST_MEM2MEM;
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Set peripheral request  to DMAMUX channel */
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Clear the DMAMUX synchro overrun flag */
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (((hdma->Init.Request >  0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Initialize parameters for DMAMUX request generator :
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     */
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Reset the DMAMUX request generator register*/
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxRequestGen->RGCR = 0U;
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Clear the DMAMUX request generator overrun flag */
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxRequestGen = 0U;
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxRequestGenStatus = 0U;
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxRequestGenStatusMask = 0U;
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Initialize the error code */
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Initialize the DMA state*/
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->State  = HAL_DMA_STATE_READY;
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Allocate lock resource and initialize it */
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->Lock = HAL_UNLOCKED;
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return HAL_OK;
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  DeInitialize the DMA peripheral.
+ARM GAS  /tmp/ccCGP7ew.s 			page 6
+
+
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *               the configuration information for the specified DMA Channel.
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval HAL status
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Check the DMA handle allocation */
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (NULL == hdma)
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     return HAL_ERROR;
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Check the parameters */
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Disable the selected DMA Channelx */
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   __HAL_DMA_DISABLE(hdma);
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Compute the channel index */
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* DMA1 */
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Ch
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA1;
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* DMA2 */
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Ch
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA2;
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Reset DMA Channel control register */
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->Instance->CCR  = 0;
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Clear all flags */
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Initialize parameters for DMAMUX channel :
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Reset the DMAMUX channel that corresponds to the DMA channel */
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxChannel->CCR = 0;
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Clear the DMAMUX synchro overrun flag */
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Reset Request generator parameters if any */
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (((hdma->Init.Request >  0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Initialize parameters for DMAMUX request generator :
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     */
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+ARM GAS  /tmp/ccCGP7ew.s 			page 7
+
+
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Reset the DMAMUX request generator register*/
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxRequestGen->RGCR = 0U;
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Clear the DMAMUX request generator overrun flag */
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxRequestGen = 0U;
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxRequestGenStatus = 0U;
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxRequestGenStatusMask = 0U;
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Clean callbacks */
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->XferCpltCallback = NULL;
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->XferHalfCpltCallback = NULL;
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->XferErrorCallback = NULL;
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->XferAbortCallback = NULL;
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Initialize the error code */
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Initialize the DMA state */
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->State = HAL_DMA_STATE_RESET;
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Release Lock */
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   __HAL_UNLOCK(hdma);
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return HAL_OK;
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @}
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *  @brief   Input and Output operation functions
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** @verbatim
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****  ===============================================================================
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****                       #####  IO operation functions  #####
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****  ===============================================================================
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     [..]  This section provides functions allowing to:
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       (+) Configure the source, destination address and data length and Start DMA transfer
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       (+) Configure the source, destination address and data length and
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           Start DMA transfer with interrupt
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       (+) Abort DMA transfer
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       (+) Poll for transfer complete
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       (+) Handle DMA interrupt request
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** @endverbatim
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @{
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Start the DMA Transfer.
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *               the configuration information for the specified DMA Channel.
+ARM GAS  /tmp/ccCGP7ew.s 			page 8
+
+
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  SrcAddress The source memory Buffer address
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  DstAddress The destination memory Buffer address
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  DataLength The length of data to be transferred from source to destination (up to 256Kb
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval HAL status
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, 
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Check the parameters */
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Process locked */
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   __HAL_LOCK(hdma);
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (HAL_DMA_STATE_READY == hdma->State)
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Change DMA peripheral state */
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->State = HAL_DMA_STATE_BUSY;
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Disable the peripheral */
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_DMA_DISABLE(hdma);
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Configure the source, destination address and the data length & clear flags*/
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Enable the Peripheral */
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_DMA_ENABLE(hdma);
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Process Unlocked */
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     status = HAL_BUSY;
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return status;
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Start the DMA Transfer with interrupt enabled.
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *               the configuration information for the specified DMA Channel.
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  SrcAddress The source memory Buffer address
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  DstAddress The destination memory Buffer address
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  DataLength The length of data to be transferred from source to destination (up to 256Kb
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval HAL status
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****                                    uint32_t DataLength)
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Check the parameters */
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Process locked */
+ARM GAS  /tmp/ccCGP7ew.s 			page 9
+
+
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   __HAL_LOCK(hdma);
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (HAL_DMA_STATE_READY == hdma->State)
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Change DMA peripheral state */
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->State = HAL_DMA_STATE_BUSY;
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Disable the peripheral */
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_DMA_DISABLE(hdma);
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Configure the source, destination address and the data length & clear flags*/
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Enable the transfer complete interrupt */
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Enable the transfer Error interrupt */
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if (NULL != hdma->XferHalfCpltCallback)
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Enable the Half transfer complete interrupt as well */
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     else
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Check if DMAMUX Synchronization is enabled*/
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Enable DMAMUX sync overrun IT*/
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if (hdma->DMAmuxRequestGen != 0U)
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* enable the request gen overrun IT*/
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Enable the Peripheral */
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_DMA_ENABLE(hdma);
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Process Unlocked */
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Remain BUSY */
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     status = HAL_BUSY;
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return status;
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Abort the DMA Transfer.
+ARM GAS  /tmp/ccCGP7ew.s 			page 10
+
+
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *               the configuration information for the specified DMA Channel.
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     * @retval HAL status
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if(hdma->State != HAL_DMA_STATE_BUSY)
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* no transfer ongoing */
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     status = HAL_ERROR;
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      /* Disable DMA IT */
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      /* disable the DMAMUX sync overrun IT*/
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      /* Disable the channel */
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      __HAL_DMA_DISABLE(hdma);
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      /* Clear all flags */
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      /* Clear the DMAMUX synchro overrun flag */
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      if (hdma->DMAmuxRequestGen != 0U)
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      {
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        /* disable the request gen overrun IT*/
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        /* Clear the DMAMUX request generator overrun flag */
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      }
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }  
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Change the DMA state */
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->State = HAL_DMA_STATE_READY;
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Process Unlocked */
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   __HAL_UNLOCK(hdma);
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return status;
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Aborts the DMA Transfer in Interrupt mode.
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *              the configuration information for the specified DMA Channel.
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval HAL status
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ARM GAS  /tmp/ccCGP7ew.s 			page 11
+
+
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (HAL_DMA_STATE_BUSY != hdma->State)
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* no transfer ongoing */
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Change the DMA state */
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->State = HAL_DMA_STATE_READY;
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Process Unlocked */
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     status = HAL_ERROR;
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Disable DMA IT */
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Disable the channel */
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_DMA_DISABLE(hdma);
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* disable the DMAMUX sync overrun IT*/
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Clear all flags */
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Clear the DMAMUX synchro overrun flag */
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if (hdma->DMAmuxRequestGen != 0U)
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* disable the request gen overrun IT*/
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Clear the DMAMUX request generator overrun flag */
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Change the DMA state */
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->State = HAL_DMA_STATE_READY;
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Process Unlocked */
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Call User Abort callback */
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if (hdma->XferAbortCallback != NULL)
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->XferAbortCallback(hdma);
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return status;
+ARM GAS  /tmp/ccCGP7ew.s 			page 12
+
+
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Polling for transfer complete.
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *              the configuration information for the specified DMA Channel.
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  CompleteLevel Specifies the DMA level complete.
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  Timeout       Timeout duration.
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval HAL status
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef Com
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****                                           uint32_t Timeout)
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t temp;
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t tickstart;
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (HAL_DMA_STATE_BUSY != hdma->State)
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* no transfer ongoing */
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     return HAL_ERROR;
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Polling mode not supported in circular mode */
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC))
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     return HAL_ERROR;
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Get the level transfer complete flag */
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Transfer Complete flag */
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     temp = (uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU);
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Half Transfer Complete flag */
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     temp = (uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU);
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Get tick */
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   tickstart = HAL_GetTick();
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   while (0U == (hdma->DmaBaseAddress->ISR & temp))
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if ((0U != (hdma->DmaBaseAddress->ISR & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU)
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* When a DMA transfer error occurs */
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* A hardware clear of its EN bits is performed */
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Clear all flags */
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Update error code */
+ARM GAS  /tmp/ccCGP7ew.s 			page 13
+
+
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->ErrorCode = HAL_DMA_ERROR_TE;
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Change the DMA state */
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->State = HAL_DMA_STATE_READY;
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Process Unlocked */
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       __HAL_UNLOCK(hdma);
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       return HAL_ERROR;
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Check for the Timeout */
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if (Timeout != HAL_MAX_DELAY)
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       {
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         /* Update error code */
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         /* Change the DMA state */
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->State = HAL_DMA_STATE_READY;
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         /* Process Unlocked */
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         __HAL_UNLOCK(hdma);
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         return HAL_ERROR;
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       }
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /*Check for DMAMUX Request generator (if used) overrun status */
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (hdma->DMAmuxRequestGen != 0U)
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Disable the request gen overrun interrupt */
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Clear the DMAMUX request generator overrun flag */
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Update error code */
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Check for DMAMUX Synchronization overrun */
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Clear the DMAMUX synchro overrun flag */
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Update error code */
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
+ARM GAS  /tmp/ccCGP7ew.s 			page 14
+
+
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Clear the transfer complete flag */
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU));
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* The selected Channelx EN bit is cleared (DMA is disabled and
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     all transfers are complete) */
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->State = HAL_DMA_STATE_READY;
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Clear the half transfer complete flag */
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU));
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Process unlocked */
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   __HAL_UNLOCK(hdma);
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return HAL_OK;
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Handle DMA interrupt request.
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *               the configuration information for the specified DMA Channel.
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval None
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t source_it = hdma->Instance->CCR;
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Half Transfer Complete Interrupt management ******************************/
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if ((0U != (flag_it & ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (sourc
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Disable the half transfer interrupt */
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Clear the half transfer complete flag */
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1FU));
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* DMA peripheral state is not updated in Half Transfer */
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* but in Transfer Complete case */
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if (hdma->XferHalfCpltCallback != NULL)
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Half transfer callback */
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->XferHalfCpltCallback(hdma);
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Transfer Complete Interrupt management ***********************************/
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU))))
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****            && (0U != (source_it & DMA_IT_TC)))
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ARM GAS  /tmp/ccCGP7ew.s 			page 15
+
+
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Disable the transfer complete and error interrupt */
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Change the DMA state */
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->State = HAL_DMA_STATE_READY;
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Clear the transfer complete flag */
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1FU));
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Process Unlocked */
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if (hdma->XferCpltCallback != NULL)
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Transfer complete callback */
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->XferCpltCallback(hdma);
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Transfer Error Interrupt management **************************************/
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU))))
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****            && (0U != (source_it & DMA_IT_TE)))
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* When a DMA transfer error occurs */
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* A hardware clear of its EN bits is performed */
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Disable ALL DMA IT */
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Clear all flags */
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Update error code */
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_TE;
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Change the DMA state */
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->State = HAL_DMA_STATE_READY;
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Process Unlocked */
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     if (hdma->XferErrorCallback != NULL)
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       /* Transfer error callback */
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       hdma->XferErrorCallback(hdma);
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Nothing To Do */
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return;
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Register callbacks
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *                               the configuration information for the specified DMA Channel.
+ARM GAS  /tmp/ccCGP7ew.s 			page 16
+
+
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  CallbackID           User Callback identifier
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  pCallback            pointer to private callbacsk function which has pointer to
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *                               a DMA_HandleTypeDef structure as parameter.
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval HAL status
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Process locked */
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   __HAL_LOCK(hdma);
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (HAL_DMA_STATE_READY == hdma->State)
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     switch (CallbackID)
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       case  HAL_DMA_XFER_CPLT_CB_ID:
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferCpltCallback = pCallback;
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferHalfCpltCallback = pCallback;
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       case  HAL_DMA_XFER_ERROR_CB_ID:
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferErrorCallback = pCallback;
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       case  HAL_DMA_XFER_ABORT_CB_ID:
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferAbortCallback = pCallback;
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       default:
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         status = HAL_ERROR;
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     status = HAL_ERROR;
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Release Lock */
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   __HAL_UNLOCK(hdma);
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return status;
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  UnRegister callbacks
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *                               the configuration information for the specified DMA Channel.
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  CallbackID           User Callback identifier
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval HAL status
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ARM GAS  /tmp/ccCGP7ew.s 			page 17
+
+
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Process locked */
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   __HAL_LOCK(hdma);
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (HAL_DMA_STATE_READY == hdma->State)
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     switch (CallbackID)
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       case  HAL_DMA_XFER_CPLT_CB_ID:
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferCpltCallback = NULL;
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferHalfCpltCallback = NULL;
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       case  HAL_DMA_XFER_ERROR_CB_ID:
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferErrorCallback = NULL;
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       case  HAL_DMA_XFER_ABORT_CB_ID:
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferAbortCallback = NULL;
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       case   HAL_DMA_XFER_ALL_CB_ID:
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferCpltCallback = NULL;
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferHalfCpltCallback = NULL;
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferErrorCallback = NULL;
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferAbortCallback = NULL;
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       default:
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         status = HAL_ERROR;
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     status = HAL_ERROR;
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Release Lock */
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   __HAL_UNLOCK(hdma);
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return status;
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @}
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
+ARM GAS  /tmp/ccCGP7ew.s 			page 18
+
+
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *  @brief    Peripheral State and Errors functions
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** @verbatim
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****  ===============================================================================
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****             ##### Peripheral State and Errors functions #####
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****  ===============================================================================
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     [..]
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     This subsection provides functions allowing to
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       (+) Check the DMA state
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       (+) Get error code
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** @endverbatim
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @{
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Return the DMA hande state.
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *               the configuration information for the specified DMA Channel.
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval HAL state
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Return DMA handle state */
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return hdma->State;
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Return the DMA error code.
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *              the configuration information for the specified DMA Channel.
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval DMA Error Code
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return hdma->ErrorCode;
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @}
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @}
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /** @addtogroup DMA_Private_Functions
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @{
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Sets the DMA Transfer parameter.
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *                     the configuration information for the specified DMA Channel.
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  SrcAddress The source memory Buffer address
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  DstAddress The destination memory Buffer address
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  DataLength The length of data to be transferred from source to destination
+ARM GAS  /tmp/ccCGP7ew.s 			page 19
+
+
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval HAL status
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+  29              		.loc 1 1003 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+  34              		.loc 1 1003 1 is_stmt 0 view .LVU1
+  35 0000 30B4     		push	{r4, r5}
+  36              	.LCFI0:
+  37              		.cfi_def_cfa_offset 8
+  38              		.cfi_offset 4, -8
+  39              		.cfi_offset 5, -4
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Clear the DMAMUX synchro overrun flag */
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+  40              		.loc 1 1005 3 is_stmt 1 view .LVU2
+  41              		.loc 1 1005 7 is_stmt 0 view .LVU3
+  42 0002 C46C     		ldr	r4, [r0, #76]
+  43              		.loc 1 1005 34 view .LVU4
+  44 0004 056D     		ldr	r5, [r0, #80]
+  45 0006 6560     		str	r5, [r4, #4]
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if (hdma->DMAmuxRequestGen != 0U)
+  46              		.loc 1 1007 3 is_stmt 1 view .LVU5
+  47              		.loc 1 1007 11 is_stmt 0 view .LVU6
+  48 0008 446D     		ldr	r4, [r0, #84]
+  49              		.loc 1 1007 6 view .LVU7
+  50 000a 14B1     		cbz	r4, .L2
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Clear the DMAMUX request generator overrun flag */
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+  51              		.loc 1 1010 5 is_stmt 1 view .LVU8
+  52              		.loc 1 1010 9 is_stmt 0 view .LVU9
+  53 000c 846D     		ldr	r4, [r0, #88]
+  54              		.loc 1 1010 41 view .LVU10
+  55 000e C56D     		ldr	r5, [r0, #92]
+  56 0010 6560     		str	r5, [r4, #4]
+  57              	.L2:
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Clear all flags */
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
+  58              		.loc 1 1014 3 is_stmt 1 view .LVU11
+  59              		.loc 1 1014 54 is_stmt 0 view .LVU12
+  60 0012 446C     		ldr	r4, [r0, #68]
+  61              		.loc 1 1014 69 view .LVU13
+  62 0014 04F01F0C 		and	ip, r4, #31
+  63              		.loc 1 1014 46 view .LVU14
+  64 0018 0124     		movs	r4, #1
+  65 001a 04FA0CF4 		lsl	r4, r4, ip
+  66              		.loc 1 1014 30 view .LVU15
+  67 001e 056C     		ldr	r5, [r0, #64]
+  68 0020 6C60     		str	r4, [r5, #4]
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Configure DMA Channel data length */
+ARM GAS  /tmp/ccCGP7ew.s 			page 20
+
+
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->Instance->CNDTR = DataLength;
+  69              		.loc 1 1017 3 is_stmt 1 view .LVU16
+  70              		.loc 1 1017 7 is_stmt 0 view .LVU17
+  71 0022 0468     		ldr	r4, [r0]
+  72              		.loc 1 1017 25 view .LVU18
+  73 0024 6360     		str	r3, [r4, #4]
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Memory to Peripheral */
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  74              		.loc 1 1020 3 is_stmt 1 view .LVU19
+  75              		.loc 1 1020 18 is_stmt 0 view .LVU20
+  76 0026 8368     		ldr	r3, [r0, #8]
+  77              	.LVL1:
+  78              		.loc 1 1020 6 view .LVU21
+  79 0028 102B     		cmp	r3, #16
+  80 002a 05D0     		beq	.L6
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Configure DMA Channel destination address */
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->Instance->CPAR = DstAddress;
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Configure DMA Channel source address */
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->Instance->CMAR = SrcAddress;
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Peripheral to Memory */
+1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Configure DMA Channel source address */
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->Instance->CPAR = SrcAddress;
+  81              		.loc 1 1032 5 is_stmt 1 view .LVU22
+  82              		.loc 1 1032 9 is_stmt 0 view .LVU23
+  83 002c 0368     		ldr	r3, [r0]
+  84              		.loc 1 1032 26 view .LVU24
+  85 002e 9960     		str	r1, [r3, #8]
+  86              	.LVL2:
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* Configure DMA Channel destination address */
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->Instance->CMAR = DstAddress;
+  87              		.loc 1 1035 5 is_stmt 1 view .LVU25
+  88              		.loc 1 1035 9 is_stmt 0 view .LVU26
+  89 0030 0368     		ldr	r3, [r0]
+  90              		.loc 1 1035 26 view .LVU27
+  91 0032 DA60     		str	r2, [r3, #12]
+  92              	.L1:
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+  93              		.loc 1 1037 1 view .LVU28
+  94 0034 30BC     		pop	{r4, r5}
+  95              	.LCFI1:
+  96              		.cfi_remember_state
+  97              		.cfi_restore 5
+  98              		.cfi_restore 4
+  99              		.cfi_def_cfa_offset 0
+ 100 0036 7047     		bx	lr
+ 101              	.LVL3:
+ 102              	.L6:
+ 103              	.LCFI2:
+ 104              		.cfi_restore_state
+ARM GAS  /tmp/ccCGP7ew.s 			page 21
+
+
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 105              		.loc 1 1023 5 is_stmt 1 view .LVU29
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 106              		.loc 1 1023 9 is_stmt 0 view .LVU30
+ 107 0038 0368     		ldr	r3, [r0]
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 108              		.loc 1 1023 26 view .LVU31
+ 109 003a 9A60     		str	r2, [r3, #8]
+ 110              	.LVL4:
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 111              		.loc 1 1026 5 is_stmt 1 view .LVU32
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 112              		.loc 1 1026 9 is_stmt 0 view .LVU33
+ 113 003c 0368     		ldr	r3, [r0]
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 114              		.loc 1 1026 26 view .LVU34
+ 115 003e D960     		str	r1, [r3, #12]
+ 116 0040 F8E7     		b	.L1
+ 117              		.cfi_endproc
+ 118              	.LFE341:
+ 120              		.section	.text.DMA_CalcDMAMUXChannelBaseAndMask,"ax",%progbits
+ 121              		.align	1
+ 122              		.syntax unified
+ 123              		.thumb
+ 124              		.thumb_func
+ 126              	DMA_CalcDMAMUXChannelBaseAndMask:
+ 127              	.LVL5:
+ 128              	.LFB342:
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on stream num
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma        pointer to a DMA_HandleTypeDef structure that contains
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *                     the configuration information for the specified DMA Stream.
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval None
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 129              		.loc 1 1046 1 is_stmt 1 view -0
+ 130              		.cfi_startproc
+ 131              		@ args = 0, pretend = 0, frame = 0
+ 132              		@ frame_needed = 0, uses_anonymous_args = 0
+ 133              		@ link register save eliminated.
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t dmamux_base_addr;
+ 134              		.loc 1 1047 3 view .LVU36
+1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t channel_number;
+ 135              		.loc 1 1048 3 view .LVU37
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase;
+ 136              		.loc 1 1049 3 view .LVU38
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* check if instance is not outside the DMA channel range */
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
+ 137              		.loc 1 1052 3 view .LVU39
+ 138              		.loc 1 1052 21 is_stmt 0 view .LVU40
+ 139 0000 0368     		ldr	r3, [r0]
+ 140              		.loc 1 1052 6 view .LVU41
+ 141 0002 0C4A     		ldr	r2, .L10
+ 142 0004 9342     		cmp	r3, r2
+ARM GAS  /tmp/ccCGP7ew.s 			page 22
+
+
+ 143 0006 13D8     		bhi	.L9
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* DMA1 */
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     DMAMUX1_ChannelBase = DMAMUX1_Channel0;
+ 144              		.loc 1 1055 25 view .LVU42
+ 145 0008 0B49     		ldr	r1, .L10+4
+ 146              	.L8:
+ 147              	.LVL6:
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   else
+1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     /* DMA2 */
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     DMAMUX1_ChannelBase = DMAMUX1_Channel8;
+1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** #elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB)
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     DMAMUX1_ChannelBase = DMAMUX1_Channel6;
+1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** #else
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     DMAMUX1_ChannelBase = DMAMUX1_Channel7;
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** #endif /* STM32G4x1xx) */
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase;
+ 148              		.loc 1 1068 3 is_stmt 1 view .LVU43
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
+ 149              		.loc 1 1069 3 view .LVU44
+ 150              		.loc 1 1069 47 is_stmt 0 view .LVU45
+ 151 000a DBB2     		uxtb	r3, r3
+ 152              		.loc 1 1069 56 view .LVU46
+ 153 000c 083B     		subs	r3, r3, #8
+ 154              		.loc 1 1069 18 view .LVU47
+ 155 000e 0B4A     		ldr	r2, .L10+8
+ 156 0010 A2FB0323 		umull	r2, r3, r2, r3
+ 157              	.LVL7:
+1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelInde
+ 158              		.loc 1 1070 3 is_stmt 1 view .LVU48
+ 159              		.loc 1 1070 87 is_stmt 0 view .LVU49
+ 160 0014 426C     		ldr	r2, [r0, #68]
+ 161              		.loc 1 1070 109 view .LVU50
+ 162 0016 22F00302 		bic	r2, r2, #3
+ 163              		.loc 1 1070 51 view .LVU51
+ 164 001a 0A44     		add	r2, r2, r1
+ 165              		.loc 1 1070 23 view .LVU52
+ 166 001c 8264     		str	r2, [r0, #72]
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+ 167              		.loc 1 1071 3 is_stmt 1 view .LVU53
+ 168              		.loc 1 1071 29 is_stmt 0 view .LVU54
+ 169 001e 084A     		ldr	r2, .L10+12
+ 170 0020 C264     		str	r2, [r0, #76]
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
+ 171              		.loc 1 1072 3 is_stmt 1 view .LVU55
+ 172              		.loc 1 1072 58 is_stmt 0 view .LVU56
+ 173 0022 C3F30413 		ubfx	r3, r3, #4, #5
+ 174              	.LVL8:
+ 175              		.loc 1 1072 39 view .LVU57
+ 176 0026 0122     		movs	r2, #1
+ 177 0028 02FA03F3 		lsl	r3, r2, r3
+ 178              		.loc 1 1072 33 view .LVU58
+ 179 002c 0365     		str	r3, [r0, #80]
+ARM GAS  /tmp/ccCGP7ew.s 			page 23
+
+
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 180              		.loc 1 1073 1 view .LVU59
+ 181 002e 7047     		bx	lr
+ 182              	.LVL9:
+ 183              	.L9:
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** #else
+ 184              		.loc 1 1063 25 view .LVU60
+ 185 0030 0449     		ldr	r1, .L10+16
+ 186 0032 EAE7     		b	.L8
+ 187              	.L11:
+ 188              		.align	2
+ 189              	.L10:
+ 190 0034 07040240 		.word	1073873927
+ 191 0038 00080240 		.word	1073874944
+ 192 003c CDCCCCCC 		.word	-858993459
+ 193 0040 80080240 		.word	1073875072
+ 194 0044 20080240 		.word	1073874976
+ 195              		.cfi_endproc
+ 196              	.LFE342:
+ 198              		.section	.text.DMA_CalcDMAMUXRequestGenBaseAndMask,"ax",%progbits
+ 199              		.align	1
+ 200              		.syntax unified
+ 201              		.thumb
+ 202              		.thumb_func
+ 204              	DMA_CalcDMAMUXRequestGenBaseAndMask:
+ 205              	.LVL10:
+ 206              	.LFB343:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** /**
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @brief  Updates the DMA handle with the DMAMUX  request generator params
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @param  hdma        pointer to a DMA_HandleTypeDef structure that contains
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   *                     the configuration information for the specified DMA Channel.
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   * @retval None
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   */
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** {
+ 207              		.loc 1 1083 1 is_stmt 1 view -0
+ 208              		.cfi_startproc
+ 209              		@ args = 0, pretend = 0, frame = 0
+ 210              		@ frame_needed = 0, uses_anonymous_args = 0
+ 211              		@ link register save eliminated.
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
+ 212              		.loc 1 1084 3 view .LVU62
+ 213              		.loc 1 1084 12 is_stmt 0 view .LVU63
+ 214 0000 0379     		ldrb	r3, [r0, #4]	@ zero_extendqisi2
+ 215              	.LVL11:
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* DMA Channels are connected to DMAMUX1 request generator blocks*/
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGener
+ 216              		.loc 1 1087 3 is_stmt 1 view .LVU64
+ 217              		.loc 1 1087 58 is_stmt 0 view .LVU65
+ 218 0002 074A     		ldr	r2, .L13
+ 219 0004 1A44     		add	r2, r2, r3
+ 220 0006 9200     		lsls	r2, r2, #2
+ 221              		.loc 1 1087 26 view .LVU66
+ 222 0008 4265     		str	r2, [r0, #84]
+ARM GAS  /tmp/ccCGP7ew.s 			page 24
+
+
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
+ 223              		.loc 1 1089 3 is_stmt 1 view .LVU67
+ 224              		.loc 1 1089 32 is_stmt 0 view .LVU68
+ 225 000a 064A     		ldr	r2, .L13+4
+ 226 000c 8265     		str	r2, [r0, #88]
+1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU);
+ 227              		.loc 1 1091 3 is_stmt 1 view .LVU69
+ 228              		.loc 1 1091 55 is_stmt 0 view .LVU70
+ 229 000e 013B     		subs	r3, r3, #1
+ 230              	.LVL12:
+ 231              		.loc 1 1091 61 view .LVU71
+ 232 0010 03F01F03 		and	r3, r3, #31
+ 233              	.LVL13:
+ 234              		.loc 1 1091 42 view .LVU72
+ 235 0014 0122     		movs	r2, #1
+ 236 0016 02FA03F3 		lsl	r3, r2, r3
+ 237              		.loc 1 1091 36 view .LVU73
+ 238 001a C365     		str	r3, [r0, #92]
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 239              		.loc 1 1092 1 view .LVU74
+ 240 001c 7047     		bx	lr
+ 241              	.L14:
+ 242 001e 00BF     		.align	2
+ 243              	.L13:
+ 244 0020 3F820010 		.word	268468799
+ 245 0024 40090240 		.word	1073875264
+ 246              		.cfi_endproc
+ 247              	.LFE343:
+ 249              		.section	.text.HAL_DMA_Init,"ax",%progbits
+ 250              		.align	1
+ 251              		.global	HAL_DMA_Init
+ 252              		.syntax unified
+ 253              		.thumb
+ 254              		.thumb_func
+ 256              	HAL_DMA_Init:
+ 257              	.LVL14:
+ 258              	.LFB329:
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t tmp;
+ 259              		.loc 1 153 1 is_stmt 1 view -0
+ 260              		.cfi_startproc
+ 261              		@ args = 0, pretend = 0, frame = 0
+ 262              		@ frame_needed = 0, uses_anonymous_args = 0
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 263              		.loc 1 154 3 view .LVU76
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 264              		.loc 1 157 3 view .LVU77
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 265              		.loc 1 157 6 is_stmt 0 view .LVU78
+ 266 0000 0028     		cmp	r0, #0
+ 267 0002 5BD0     		beq	.L22
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t tmp;
+ 268              		.loc 1 153 1 view .LVU79
+ 269 0004 10B5     		push	{r4, lr}
+ 270              	.LCFI3:
+ 271              		.cfi_def_cfa_offset 8
+ARM GAS  /tmp/ccCGP7ew.s 			page 25
+
+
+ 272              		.cfi_offset 4, -8
+ 273              		.cfi_offset 14, -4
+ 274 0006 0446     		mov	r4, r0
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ 275              		.loc 1 163 3 is_stmt 1 view .LVU80
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ 276              		.loc 1 164 3 view .LVU81
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ 277              		.loc 1 165 3 view .LVU82
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ 278              		.loc 1 166 3 view .LVU83
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ 279              		.loc 1 167 3 view .LVU84
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ 280              		.loc 1 168 3 view .LVU85
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+ 281              		.loc 1 169 3 view .LVU86
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 282              		.loc 1 170 3 view .LVU87
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 283              		.loc 1 172 3 view .LVU88
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 284              		.loc 1 175 3 view .LVU89
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 285              		.loc 1 175 22 is_stmt 0 view .LVU90
+ 286 0008 0168     		ldr	r1, [r0]
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 287              		.loc 1 175 6 view .LVU91
+ 288 000a 2D4B     		ldr	r3, .L29
+ 289 000c 9942     		cmp	r1, r3
+ 290 000e 3DD8     		bhi	.L17
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA1;
+ 291              		.loc 1 178 5 is_stmt 1 view .LVU92
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA1;
+ 292              		.loc 1 178 53 is_stmt 0 view .LVU93
+ 293 0010 2C4B     		ldr	r3, .L29+4
+ 294 0012 0B44     		add	r3, r3, r1
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA1;
+ 295              		.loc 1 178 80 view .LVU94
+ 296 0014 2C4A     		ldr	r2, .L29+8
+ 297 0016 A2FB0323 		umull	r2, r3, r2, r3
+ 298 001a 1B09     		lsrs	r3, r3, #4
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA1;
+ 299              		.loc 1 178 135 view .LVU95
+ 300 001c 9B00     		lsls	r3, r3, #2
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA1;
+ 301              		.loc 1 178 24 view .LVU96
+ 302 001e 4364     		str	r3, [r0, #68]
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 303              		.loc 1 179 5 is_stmt 1 view .LVU97
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 304              		.loc 1 179 26 is_stmt 0 view .LVU98
+ 305 0020 2A4B     		ldr	r3, .L29+12
+ 306 0022 0364     		str	r3, [r0, #64]
+ 307              	.L18:
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 308              		.loc 1 189 3 is_stmt 1 view .LVU99
+ARM GAS  /tmp/ccCGP7ew.s 			page 26
+
+
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 309              		.loc 1 189 15 is_stmt 0 view .LVU100
+ 310 0024 0223     		movs	r3, #2
+ 311 0026 84F82530 		strb	r3, [r4, #37]
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 312              		.loc 1 192 3 is_stmt 1 view .LVU101
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 313              		.loc 1 192 7 is_stmt 0 view .LVU102
+ 314 002a 0A68     		ldr	r2, [r1]
+ 315              	.LVL15:
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****                       DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |
+ 316              		.loc 1 195 3 is_stmt 1 view .LVU103
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****                       DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |
+ 317              		.loc 1 195 7 is_stmt 0 view .LVU104
+ 318 002c 22F4FF42 		bic	r2, r2, #32640
+ 319              	.LVL16:
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****                       DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |
+ 320              		.loc 1 195 7 view .LVU105
+ 321 0030 22F07002 		bic	r2, r2, #112
+ 322              	.LVL17:
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 323              		.loc 1 200 3 is_stmt 1 view .LVU106
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 324              		.loc 1 200 21 is_stmt 0 view .LVU107
+ 325 0034 A368     		ldr	r3, [r4, #8]
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 326              		.loc 1 201 21 view .LVU108
+ 327 0036 E068     		ldr	r0, [r4, #12]
+ 328              	.LVL18:
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 329              		.loc 1 200 39 view .LVU109
+ 330 0038 0343     		orrs	r3, r3, r0
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 331              		.loc 1 201 54 view .LVU110
+ 332 003a 2069     		ldr	r0, [r4, #16]
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 333              		.loc 1 201 42 view .LVU111
+ 334 003c 0343     		orrs	r3, r3, r0
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.Mode                | hdma->Init.Priority;
+ 335              		.loc 1 202 21 view .LVU112
+ 336 003e 6069     		ldr	r0, [r4, #20]
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 337              		.loc 1 201 72 view .LVU113
+ 338 0040 0343     		orrs	r3, r3, r0
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.Mode                | hdma->Init.Priority;
+ 339              		.loc 1 202 54 view .LVU114
+ 340 0042 A069     		ldr	r0, [r4, #24]
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.Mode                | hdma->Init.Priority;
+ 341              		.loc 1 202 42 view .LVU115
+ 342 0044 0343     		orrs	r3, r3, r0
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 343              		.loc 1 203 21 view .LVU116
+ 344 0046 E069     		ldr	r0, [r4, #28]
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.Mode                | hdma->Init.Priority;
+ 345              		.loc 1 202 72 view .LVU117
+ 346 0048 0343     		orrs	r3, r3, r0
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ARM GAS  /tmp/ccCGP7ew.s 			page 27
+
+
+ 347              		.loc 1 203 54 view .LVU118
+ 348 004a 206A     		ldr	r0, [r4, #32]
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 349              		.loc 1 203 42 view .LVU119
+ 350 004c 0343     		orrs	r3, r3, r0
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 351              		.loc 1 200 7 view .LVU120
+ 352 004e 1343     		orrs	r3, r3, r2
+ 353              	.LVL19:
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 354              		.loc 1 206 3 is_stmt 1 view .LVU121
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 355              		.loc 1 206 23 is_stmt 0 view .LVU122
+ 356 0050 0B60     		str	r3, [r1]
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 357              		.loc 1 211 3 is_stmt 1 view .LVU123
+ 358 0052 2046     		mov	r0, r4
+ 359 0054 FFF7FEFF 		bl	DMA_CalcDMAMUXChannelBaseAndMask
+ 360              	.LVL20:
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 361              		.loc 1 213 3 view .LVU124
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 362              		.loc 1 213 17 is_stmt 0 view .LVU125
+ 363 0058 A368     		ldr	r3, [r4, #8]
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 364              		.loc 1 213 6 view .LVU126
+ 365 005a B3F5804F 		cmp	r3, #16384
+ 366 005e 20D0     		beq	.L27
+ 367              	.L19:
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 368              		.loc 1 220 3 is_stmt 1 view .LVU127
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 369              		.loc 1 220 7 is_stmt 0 view .LVU128
+ 370 0060 A36C     		ldr	r3, [r4, #72]
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 371              		.loc 1 220 50 view .LVU129
+ 372 0062 2279     		ldrb	r2, [r4, #4]	@ zero_extendqisi2
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 373              		.loc 1 220 28 view .LVU130
+ 374 0064 1A60     		str	r2, [r3]
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 375              		.loc 1 223 3 is_stmt 1 view .LVU131
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 376              		.loc 1 223 7 is_stmt 0 view .LVU132
+ 377 0066 E36C     		ldr	r3, [r4, #76]
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 378              		.loc 1 223 40 view .LVU133
+ 379 0068 226D     		ldr	r2, [r4, #80]
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 380              		.loc 1 223 34 view .LVU134
+ 381 006a 5A60     		str	r2, [r3, #4]
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 382              		.loc 1 225 3 is_stmt 1 view .LVU135
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 383              		.loc 1 225 19 is_stmt 0 view .LVU136
+ 384 006c 6368     		ldr	r3, [r4, #4]
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ARM GAS  /tmp/ccCGP7ew.s 			page 28
+
+
+ 385              		.loc 1 225 35 view .LVU137
+ 386 006e 013B     		subs	r3, r3, #1
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 387              		.loc 1 225 6 view .LVU138
+ 388 0070 032B     		cmp	r3, #3
+ 389 0072 19D9     		bls	.L28
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxRequestGenStatus = 0U;
+ 390              		.loc 1 240 5 is_stmt 1 view .LVU139
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxRequestGenStatus = 0U;
+ 391              		.loc 1 240 28 is_stmt 0 view .LVU140
+ 392 0074 0023     		movs	r3, #0
+ 393 0076 6365     		str	r3, [r4, #84]
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxRequestGenStatusMask = 0U;
+ 394              		.loc 1 241 5 is_stmt 1 view .LVU141
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DMAmuxRequestGenStatusMask = 0U;
+ 395              		.loc 1 241 34 is_stmt 0 view .LVU142
+ 396 0078 A365     		str	r3, [r4, #88]
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 397              		.loc 1 242 5 is_stmt 1 view .LVU143
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 398              		.loc 1 242 38 is_stmt 0 view .LVU144
+ 399 007a E365     		str	r3, [r4, #92]
+ 400              	.L21:
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 401              		.loc 1 246 3 is_stmt 1 view .LVU145
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 402              		.loc 1 246 19 is_stmt 0 view .LVU146
+ 403 007c 0020     		movs	r0, #0
+ 404 007e E063     		str	r0, [r4, #60]
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 405              		.loc 1 249 3 is_stmt 1 view .LVU147
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 406              		.loc 1 249 16 is_stmt 0 view .LVU148
+ 407 0080 0123     		movs	r3, #1
+ 408 0082 84F82530 		strb	r3, [r4, #37]
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 409              		.loc 1 252 3 is_stmt 1 view .LVU149
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 410              		.loc 1 252 14 is_stmt 0 view .LVU150
+ 411 0086 84F82400 		strb	r0, [r4, #36]
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 412              		.loc 1 254 3 is_stmt 1 view .LVU151
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 413              		.loc 1 255 1 is_stmt 0 view .LVU152
+ 414 008a 10BD     		pop	{r4, pc}
+ 415              	.LVL21:
+ 416              	.L17:
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA2;
+ 417              		.loc 1 184 5 is_stmt 1 view .LVU153
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA2;
+ 418              		.loc 1 184 53 is_stmt 0 view .LVU154
+ 419 008c 104B     		ldr	r3, .L29+16
+ 420 008e 0B44     		add	r3, r3, r1
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA2;
+ 421              		.loc 1 184 80 view .LVU155
+ 422 0090 0D4A     		ldr	r2, .L29+8
+ 423 0092 A2FB0323 		umull	r2, r3, r2, r3
+ARM GAS  /tmp/ccCGP7ew.s 			page 29
+
+
+ 424 0096 1B09     		lsrs	r3, r3, #4
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA2;
+ 425              		.loc 1 184 135 view .LVU156
+ 426 0098 9B00     		lsls	r3, r3, #2
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA2;
+ 427              		.loc 1 184 24 view .LVU157
+ 428 009a 4364     		str	r3, [r0, #68]
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 429              		.loc 1 185 5 is_stmt 1 view .LVU158
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 430              		.loc 1 185 26 is_stmt 0 view .LVU159
+ 431 009c 0D4B     		ldr	r3, .L29+20
+ 432 009e 0364     		str	r3, [r0, #64]
+ 433 00a0 C0E7     		b	.L18
+ 434              	.LVL22:
+ 435              	.L27:
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 436              		.loc 1 216 5 is_stmt 1 view .LVU160
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 437              		.loc 1 216 24 is_stmt 0 view .LVU161
+ 438 00a2 0023     		movs	r3, #0
+ 439 00a4 6360     		str	r3, [r4, #4]
+ 440 00a6 DBE7     		b	.L19
+ 441              	.L28:
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 442              		.loc 1 230 5 is_stmt 1 view .LVU162
+ 443 00a8 2046     		mov	r0, r4
+ 444 00aa FFF7FEFF 		bl	DMA_CalcDMAMUXRequestGenBaseAndMask
+ 445              	.LVL23:
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 446              		.loc 1 233 5 view .LVU163
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 447              		.loc 1 233 9 is_stmt 0 view .LVU164
+ 448 00ae 636D     		ldr	r3, [r4, #84]
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 449              		.loc 1 233 34 view .LVU165
+ 450 00b0 0022     		movs	r2, #0
+ 451 00b2 1A60     		str	r2, [r3]
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 452              		.loc 1 236 5 is_stmt 1 view .LVU166
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 453              		.loc 1 236 9 is_stmt 0 view .LVU167
+ 454 00b4 A36D     		ldr	r3, [r4, #88]
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 455              		.loc 1 236 47 view .LVU168
+ 456 00b6 E26D     		ldr	r2, [r4, #92]
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 457              		.loc 1 236 41 view .LVU169
+ 458 00b8 5A60     		str	r2, [r3, #4]
+ 459 00ba DFE7     		b	.L21
+ 460              	.LVL24:
+ 461              	.L22:
+ 462              	.LCFI4:
+ 463              		.cfi_def_cfa_offset 0
+ 464              		.cfi_restore 4
+ 465              		.cfi_restore 14
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ARM GAS  /tmp/ccCGP7ew.s 			page 30
+
+
+ 466              		.loc 1 159 12 view .LVU170
+ 467 00bc 0120     		movs	r0, #1
+ 468              	.LVL25:
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 469              		.loc 1 255 1 view .LVU171
+ 470 00be 7047     		bx	lr
+ 471              	.L30:
+ 472              		.align	2
+ 473              	.L29:
+ 474 00c0 07040240 		.word	1073873927
+ 475 00c4 F8FFFDBF 		.word	-1073872904
+ 476 00c8 CDCCCCCC 		.word	-858993459
+ 477 00cc 00000240 		.word	1073872896
+ 478 00d0 F8FBFDBF 		.word	-1073873928
+ 479 00d4 00040240 		.word	1073873920
+ 480              		.cfi_endproc
+ 481              	.LFE329:
+ 483              		.section	.text.HAL_DMA_DeInit,"ax",%progbits
+ 484              		.align	1
+ 485              		.global	HAL_DMA_DeInit
+ 486              		.syntax unified
+ 487              		.thumb
+ 488              		.thumb_func
+ 490              	HAL_DMA_DeInit:
+ 491              	.LVL26:
+ 492              	.LFB330:
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 493              		.loc 1 264 1 is_stmt 1 view -0
+ 494              		.cfi_startproc
+ 495              		@ args = 0, pretend = 0, frame = 0
+ 496              		@ frame_needed = 0, uses_anonymous_args = 0
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 497              		.loc 1 267 3 view .LVU173
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 498              		.loc 1 267 6 is_stmt 0 view .LVU174
+ 499 0000 0028     		cmp	r0, #0
+ 500 0002 4BD0     		beq	.L36
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 501              		.loc 1 264 1 view .LVU175
+ 502 0004 38B5     		push	{r3, r4, r5, lr}
+ 503              	.LCFI5:
+ 504              		.cfi_def_cfa_offset 16
+ 505              		.cfi_offset 3, -16
+ 506              		.cfi_offset 4, -12
+ 507              		.cfi_offset 5, -8
+ 508              		.cfi_offset 14, -4
+ 509 0006 0446     		mov	r4, r0
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 510              		.loc 1 273 3 is_stmt 1 view .LVU176
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 511              		.loc 1 276 3 view .LVU177
+ 512 0008 0268     		ldr	r2, [r0]
+ 513 000a 1368     		ldr	r3, [r2]
+ 514 000c 23F00103 		bic	r3, r3, #1
+ 515 0010 1360     		str	r3, [r2]
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 516              		.loc 1 279 3 view .LVU178
+ARM GAS  /tmp/ccCGP7ew.s 			page 31
+
+
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 517              		.loc 1 279 22 is_stmt 0 view .LVU179
+ 518 0012 0268     		ldr	r2, [r0]
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 519              		.loc 1 279 6 view .LVU180
+ 520 0014 224B     		ldr	r3, .L42
+ 521 0016 9A42     		cmp	r2, r3
+ 522 0018 2CD8     		bhi	.L33
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA1;
+ 523              		.loc 1 282 5 is_stmt 1 view .LVU181
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA1;
+ 524              		.loc 1 282 53 is_stmt 0 view .LVU182
+ 525 001a 224B     		ldr	r3, .L42+4
+ 526 001c 1344     		add	r3, r3, r2
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA1;
+ 527              		.loc 1 282 80 view .LVU183
+ 528 001e 2249     		ldr	r1, .L42+8
+ 529 0020 A1FB0313 		umull	r1, r3, r1, r3
+ 530 0024 1B09     		lsrs	r3, r3, #4
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA1;
+ 531              		.loc 1 282 135 view .LVU184
+ 532 0026 9B00     		lsls	r3, r3, #2
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA1;
+ 533              		.loc 1 282 24 view .LVU185
+ 534 0028 4364     		str	r3, [r0, #68]
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 535              		.loc 1 283 5 is_stmt 1 view .LVU186
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 536              		.loc 1 283 26 is_stmt 0 view .LVU187
+ 537 002a 204B     		ldr	r3, .L42+12
+ 538 002c 0364     		str	r3, [r0, #64]
+ 539              	.L34:
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 540              		.loc 1 293 3 is_stmt 1 view .LVU188
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 541              		.loc 1 293 24 is_stmt 0 view .LVU189
+ 542 002e 0025     		movs	r5, #0
+ 543 0030 1560     		str	r5, [r2]
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 544              		.loc 1 296 3 is_stmt 1 view .LVU190
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 545              		.loc 1 296 54 is_stmt 0 view .LVU191
+ 546 0032 636C     		ldr	r3, [r4, #68]
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 547              		.loc 1 296 69 view .LVU192
+ 548 0034 03F01F02 		and	r2, r3, #31
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 549              		.loc 1 296 7 view .LVU193
+ 550 0038 216C     		ldr	r1, [r4, #64]
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 551              		.loc 1 296 46 view .LVU194
+ 552 003a 0123     		movs	r3, #1
+ 553 003c 9340     		lsls	r3, r3, r2
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 554              		.loc 1 296 30 view .LVU195
+ 555 003e 4B60     		str	r3, [r1, #4]
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ARM GAS  /tmp/ccCGP7ew.s 			page 32
+
+
+ 556              		.loc 1 301 3 is_stmt 1 view .LVU196
+ 557 0040 2046     		mov	r0, r4
+ 558              	.LVL27:
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 559              		.loc 1 301 3 is_stmt 0 view .LVU197
+ 560 0042 FFF7FEFF 		bl	DMA_CalcDMAMUXChannelBaseAndMask
+ 561              	.LVL28:
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 562              		.loc 1 304 3 is_stmt 1 view .LVU198
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 563              		.loc 1 304 7 is_stmt 0 view .LVU199
+ 564 0046 A36C     		ldr	r3, [r4, #72]
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 565              		.loc 1 304 28 view .LVU200
+ 566 0048 1D60     		str	r5, [r3]
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 567              		.loc 1 307 3 is_stmt 1 view .LVU201
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 568              		.loc 1 307 7 is_stmt 0 view .LVU202
+ 569 004a E36C     		ldr	r3, [r4, #76]
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 570              		.loc 1 307 40 view .LVU203
+ 571 004c 226D     		ldr	r2, [r4, #80]
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 572              		.loc 1 307 34 view .LVU204
+ 573 004e 5A60     		str	r2, [r3, #4]
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 574              		.loc 1 310 3 is_stmt 1 view .LVU205
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 575              		.loc 1 310 19 is_stmt 0 view .LVU206
+ 576 0050 6368     		ldr	r3, [r4, #4]
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 577              		.loc 1 310 35 view .LVU207
+ 578 0052 013B     		subs	r3, r3, #1
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 579              		.loc 1 310 6 view .LVU208
+ 580 0054 032B     		cmp	r3, #3
+ 581 0056 18D9     		bls	.L41
+ 582              	.L35:
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxRequestGenStatus = 0U;
+ 583              		.loc 1 324 3 is_stmt 1 view .LVU209
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxRequestGenStatus = 0U;
+ 584              		.loc 1 324 26 is_stmt 0 view .LVU210
+ 585 0058 0020     		movs	r0, #0
+ 586 005a 6065     		str	r0, [r4, #84]
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxRequestGenStatusMask = 0U;
+ 587              		.loc 1 325 3 is_stmt 1 view .LVU211
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->DMAmuxRequestGenStatusMask = 0U;
+ 588              		.loc 1 325 32 is_stmt 0 view .LVU212
+ 589 005c A065     		str	r0, [r4, #88]
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 590              		.loc 1 326 3 is_stmt 1 view .LVU213
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 591              		.loc 1 326 36 is_stmt 0 view .LVU214
+ 592 005e E065     		str	r0, [r4, #92]
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->XferHalfCpltCallback = NULL;
+ 593              		.loc 1 329 3 is_stmt 1 view .LVU215
+ARM GAS  /tmp/ccCGP7ew.s 			page 33
+
+
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->XferHalfCpltCallback = NULL;
+ 594              		.loc 1 329 26 is_stmt 0 view .LVU216
+ 595 0060 E062     		str	r0, [r4, #44]
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->XferErrorCallback = NULL;
+ 596              		.loc 1 330 3 is_stmt 1 view .LVU217
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->XferErrorCallback = NULL;
+ 597              		.loc 1 330 30 is_stmt 0 view .LVU218
+ 598 0062 2063     		str	r0, [r4, #48]
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->XferAbortCallback = NULL;
+ 599              		.loc 1 331 3 is_stmt 1 view .LVU219
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   hdma->XferAbortCallback = NULL;
+ 600              		.loc 1 331 27 is_stmt 0 view .LVU220
+ 601 0064 6063     		str	r0, [r4, #52]
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 602              		.loc 1 332 3 is_stmt 1 view .LVU221
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 603              		.loc 1 332 27 is_stmt 0 view .LVU222
+ 604 0066 A063     		str	r0, [r4, #56]
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 605              		.loc 1 335 3 is_stmt 1 view .LVU223
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 606              		.loc 1 335 19 is_stmt 0 view .LVU224
+ 607 0068 E063     		str	r0, [r4, #60]
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 608              		.loc 1 338 3 is_stmt 1 view .LVU225
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 609              		.loc 1 338 15 is_stmt 0 view .LVU226
+ 610 006a 84F82500 		strb	r0, [r4, #37]
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 611              		.loc 1 341 3 is_stmt 1 view .LVU227
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 612              		.loc 1 341 3 view .LVU228
+ 613 006e 84F82400 		strb	r0, [r4, #36]
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 614              		.loc 1 341 3 view .LVU229
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 615              		.loc 1 343 3 view .LVU230
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 616              		.loc 1 344 1 is_stmt 0 view .LVU231
+ 617 0072 38BD     		pop	{r3, r4, r5, pc}
+ 618              	.LVL29:
+ 619              	.L33:
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA2;
+ 620              		.loc 1 288 5 is_stmt 1 view .LVU232
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA2;
+ 621              		.loc 1 288 53 is_stmt 0 view .LVU233
+ 622 0074 0E4B     		ldr	r3, .L42+16
+ 623 0076 1344     		add	r3, r3, r2
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA2;
+ 624              		.loc 1 288 80 view .LVU234
+ 625 0078 0B49     		ldr	r1, .L42+8
+ 626 007a A1FB0313 		umull	r1, r3, r1, r3
+ 627 007e 1B09     		lsrs	r3, r3, #4
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA2;
+ 628              		.loc 1 288 135 view .LVU235
+ 629 0080 9B00     		lsls	r3, r3, #2
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->DmaBaseAddress = DMA2;
+ARM GAS  /tmp/ccCGP7ew.s 			page 34
+
+
+ 630              		.loc 1 288 24 view .LVU236
+ 631 0082 4364     		str	r3, [r0, #68]
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 632              		.loc 1 289 5 is_stmt 1 view .LVU237
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 633              		.loc 1 289 26 is_stmt 0 view .LVU238
+ 634 0084 0B4B     		ldr	r3, .L42+20
+ 635 0086 0364     		str	r3, [r0, #64]
+ 636 0088 D1E7     		b	.L34
+ 637              	.LVL30:
+ 638              	.L41:
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 639              		.loc 1 315 5 is_stmt 1 view .LVU239
+ 640 008a 2046     		mov	r0, r4
+ 641 008c FFF7FEFF 		bl	DMA_CalcDMAMUXRequestGenBaseAndMask
+ 642              	.LVL31:
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 643              		.loc 1 318 5 view .LVU240
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 644              		.loc 1 318 9 is_stmt 0 view .LVU241
+ 645 0090 636D     		ldr	r3, [r4, #84]
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 646              		.loc 1 318 34 view .LVU242
+ 647 0092 1D60     		str	r5, [r3]
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 648              		.loc 1 321 5 is_stmt 1 view .LVU243
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 649              		.loc 1 321 9 is_stmt 0 view .LVU244
+ 650 0094 A36D     		ldr	r3, [r4, #88]
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 651              		.loc 1 321 47 view .LVU245
+ 652 0096 E26D     		ldr	r2, [r4, #92]
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 653              		.loc 1 321 41 view .LVU246
+ 654 0098 5A60     		str	r2, [r3, #4]
+ 655 009a DDE7     		b	.L35
+ 656              	.LVL32:
+ 657              	.L36:
+ 658              	.LCFI6:
+ 659              		.cfi_def_cfa_offset 0
+ 660              		.cfi_restore 3
+ 661              		.cfi_restore 4
+ 662              		.cfi_restore 5
+ 663              		.cfi_restore 14
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 664              		.loc 1 269 12 view .LVU247
+ 665 009c 0120     		movs	r0, #1
+ 666              	.LVL33:
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 667              		.loc 1 344 1 view .LVU248
+ 668 009e 7047     		bx	lr
+ 669              	.L43:
+ 670              		.align	2
+ 671              	.L42:
+ 672 00a0 07040240 		.word	1073873927
+ 673 00a4 F8FFFDBF 		.word	-1073872904
+ 674 00a8 CDCCCCCC 		.word	-858993459
+ARM GAS  /tmp/ccCGP7ew.s 			page 35
+
+
+ 675 00ac 00000240 		.word	1073872896
+ 676 00b0 F8FBFDBF 		.word	-1073873928
+ 677 00b4 00040240 		.word	1073873920
+ 678              		.cfi_endproc
+ 679              	.LFE330:
+ 681              		.section	.text.HAL_DMA_Start,"ax",%progbits
+ 682              		.align	1
+ 683              		.global	HAL_DMA_Start
+ 684              		.syntax unified
+ 685              		.thumb
+ 686              		.thumb_func
+ 688              	HAL_DMA_Start:
+ 689              	.LVL34:
+ 690              	.LFB331:
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 691              		.loc 1 379 1 is_stmt 1 view -0
+ 692              		.cfi_startproc
+ 693              		@ args = 0, pretend = 0, frame = 0
+ 694              		@ frame_needed = 0, uses_anonymous_args = 0
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 695              		.loc 1 379 1 is_stmt 0 view .LVU250
+ 696 0000 70B5     		push	{r4, r5, r6, lr}
+ 697              	.LCFI7:
+ 698              		.cfi_def_cfa_offset 16
+ 699              		.cfi_offset 4, -16
+ 700              		.cfi_offset 5, -12
+ 701              		.cfi_offset 6, -8
+ 702              		.cfi_offset 14, -4
+ 703 0002 0446     		mov	r4, r0
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 704              		.loc 1 380 3 is_stmt 1 view .LVU251
+ 705              	.LVL35:
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 706              		.loc 1 383 3 view .LVU252
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 707              		.loc 1 386 3 view .LVU253
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 708              		.loc 1 386 3 view .LVU254
+ 709 0004 90F82400 		ldrb	r0, [r0, #36]	@ zero_extendqisi2
+ 710              	.LVL36:
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 711              		.loc 1 386 3 is_stmt 0 view .LVU255
+ 712 0008 0128     		cmp	r0, #1
+ 713 000a 20D0     		beq	.L47
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 714              		.loc 1 386 3 is_stmt 1 discriminator 2 view .LVU256
+ 715 000c 0120     		movs	r0, #1
+ 716 000e 84F82400 		strb	r0, [r4, #36]
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 717              		.loc 1 386 3 discriminator 2 view .LVU257
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 718              		.loc 1 388 3 discriminator 2 view .LVU258
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 719              		.loc 1 388 34 is_stmt 0 discriminator 2 view .LVU259
+ 720 0012 94F82500 		ldrb	r0, [r4, #37]	@ zero_extendqisi2
+ 721 0016 C0B2     		uxtb	r0, r0
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ARM GAS  /tmp/ccCGP7ew.s 			page 36
+
+
+ 722              		.loc 1 388 6 discriminator 2 view .LVU260
+ 723 0018 0128     		cmp	r0, #1
+ 724 001a 04D0     		beq	.L49
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     status = HAL_BUSY;
+ 725              		.loc 1 406 5 is_stmt 1 view .LVU261
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     status = HAL_BUSY;
+ 726              		.loc 1 406 5 view .LVU262
+ 727 001c 0023     		movs	r3, #0
+ 728              	.LVL37:
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     status = HAL_BUSY;
+ 729              		.loc 1 406 5 is_stmt 0 view .LVU263
+ 730 001e 84F82430 		strb	r3, [r4, #36]
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     status = HAL_BUSY;
+ 731              		.loc 1 406 5 is_stmt 1 view .LVU264
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 732              		.loc 1 407 5 view .LVU265
+ 733              	.LVL38:
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 734              		.loc 1 407 12 is_stmt 0 view .LVU266
+ 735 0022 0220     		movs	r0, #2
+ 736              	.LVL39:
+ 737              	.L45:
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 738              		.loc 1 410 1 view .LVU267
+ 739 0024 70BD     		pop	{r4, r5, r6, pc}
+ 740              	.LVL40:
+ 741              	.L49:
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 742              		.loc 1 391 5 is_stmt 1 view .LVU268
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 743              		.loc 1 391 17 is_stmt 0 view .LVU269
+ 744 0026 0220     		movs	r0, #2
+ 745 0028 84F82500 		strb	r0, [r4, #37]
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 746              		.loc 1 392 5 is_stmt 1 view .LVU270
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 747              		.loc 1 392 21 is_stmt 0 view .LVU271
+ 748 002c 0025     		movs	r5, #0
+ 749 002e E563     		str	r5, [r4, #60]
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 750              		.loc 1 395 5 is_stmt 1 view .LVU272
+ 751 0030 2668     		ldr	r6, [r4]
+ 752 0032 3068     		ldr	r0, [r6]
+ 753 0034 20F00100 		bic	r0, r0, #1
+ 754 0038 3060     		str	r0, [r6]
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 755              		.loc 1 398 5 view .LVU273
+ 756 003a 2046     		mov	r0, r4
+ 757 003c FFF7FEFF 		bl	DMA_SetConfig
+ 758              	.LVL41:
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 759              		.loc 1 401 5 view .LVU274
+ 760 0040 2268     		ldr	r2, [r4]
+ 761 0042 1368     		ldr	r3, [r2]
+ 762 0044 43F00103 		orr	r3, r3, #1
+ 763 0048 1360     		str	r3, [r2]
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ARM GAS  /tmp/ccCGP7ew.s 			page 37
+
+
+ 764              		.loc 1 380 21 is_stmt 0 view .LVU275
+ 765 004a 2846     		mov	r0, r5
+ 766 004c EAE7     		b	.L45
+ 767              	.LVL42:
+ 768              	.L47:
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 769              		.loc 1 386 3 view .LVU276
+ 770 004e 0220     		movs	r0, #2
+ 771 0050 E8E7     		b	.L45
+ 772              		.cfi_endproc
+ 773              	.LFE331:
+ 775              		.section	.text.HAL_DMA_Start_IT,"ax",%progbits
+ 776              		.align	1
+ 777              		.global	HAL_DMA_Start_IT
+ 778              		.syntax unified
+ 779              		.thumb
+ 780              		.thumb_func
+ 782              	HAL_DMA_Start_IT:
+ 783              	.LVL43:
+ 784              	.LFB332:
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 785              		.loc 1 423 1 is_stmt 1 view -0
+ 786              		.cfi_startproc
+ 787              		@ args = 0, pretend = 0, frame = 0
+ 788              		@ frame_needed = 0, uses_anonymous_args = 0
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 789              		.loc 1 423 1 is_stmt 0 view .LVU278
+ 790 0000 38B5     		push	{r3, r4, r5, lr}
+ 791              	.LCFI8:
+ 792              		.cfi_def_cfa_offset 16
+ 793              		.cfi_offset 3, -16
+ 794              		.cfi_offset 4, -12
+ 795              		.cfi_offset 5, -8
+ 796              		.cfi_offset 14, -4
+ 797 0002 0446     		mov	r4, r0
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 798              		.loc 1 424 3 is_stmt 1 view .LVU279
+ 799              	.LVL44:
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 800              		.loc 1 427 3 view .LVU280
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 801              		.loc 1 430 3 view .LVU281
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 802              		.loc 1 430 3 view .LVU282
+ 803 0004 90F82400 		ldrb	r0, [r0, #36]	@ zero_extendqisi2
+ 804              	.LVL45:
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 805              		.loc 1 430 3 is_stmt 0 view .LVU283
+ 806 0008 0128     		cmp	r0, #1
+ 807 000a 41D0     		beq	.L57
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 808              		.loc 1 430 3 is_stmt 1 discriminator 2 view .LVU284
+ 809 000c 0120     		movs	r0, #1
+ 810 000e 84F82400 		strb	r0, [r4, #36]
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 811              		.loc 1 430 3 discriminator 2 view .LVU285
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ARM GAS  /tmp/ccCGP7ew.s 			page 38
+
+
+ 812              		.loc 1 432 3 discriminator 2 view .LVU286
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 813              		.loc 1 432 34 is_stmt 0 discriminator 2 view .LVU287
+ 814 0012 94F82500 		ldrb	r0, [r4, #37]	@ zero_extendqisi2
+ 815 0016 C0B2     		uxtb	r0, r0
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 816              		.loc 1 432 6 discriminator 2 view .LVU288
+ 817 0018 0128     		cmp	r0, #1
+ 818 001a 04D0     		beq	.L59
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 819              		.loc 1 477 5 is_stmt 1 view .LVU289
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 820              		.loc 1 477 5 view .LVU290
+ 821 001c 0023     		movs	r3, #0
+ 822              	.LVL46:
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 823              		.loc 1 477 5 is_stmt 0 view .LVU291
+ 824 001e 84F82430 		strb	r3, [r4, #36]
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 825              		.loc 1 477 5 is_stmt 1 view .LVU292
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 826              		.loc 1 480 5 view .LVU293
+ 827              	.LVL47:
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 828              		.loc 1 480 12 is_stmt 0 view .LVU294
+ 829 0022 0220     		movs	r0, #2
+ 830              	.LVL48:
+ 831              	.L51:
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 832              		.loc 1 483 1 view .LVU295
+ 833 0024 38BD     		pop	{r3, r4, r5, pc}
+ 834              	.LVL49:
+ 835              	.L59:
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 836              		.loc 1 435 5 is_stmt 1 view .LVU296
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 837              		.loc 1 435 17 is_stmt 0 view .LVU297
+ 838 0026 0220     		movs	r0, #2
+ 839 0028 84F82500 		strb	r0, [r4, #37]
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 840              		.loc 1 436 5 is_stmt 1 view .LVU298
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 841              		.loc 1 436 21 is_stmt 0 view .LVU299
+ 842 002c 0020     		movs	r0, #0
+ 843 002e E063     		str	r0, [r4, #60]
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 844              		.loc 1 439 5 is_stmt 1 view .LVU300
+ 845 0030 2568     		ldr	r5, [r4]
+ 846 0032 2868     		ldr	r0, [r5]
+ 847 0034 20F00100 		bic	r0, r0, #1
+ 848 0038 2860     		str	r0, [r5]
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 849              		.loc 1 442 5 view .LVU301
+ 850 003a 2046     		mov	r0, r4
+ 851 003c FFF7FEFF 		bl	DMA_SetConfig
+ 852              	.LVL50:
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ARM GAS  /tmp/ccCGP7ew.s 			page 39
+
+
+ 853              		.loc 1 446 5 view .LVU302
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 854              		.loc 1 446 21 is_stmt 0 view .LVU303
+ 855 0040 236B     		ldr	r3, [r4, #48]
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 856              		.loc 1 446 8 view .LVU304
+ 857 0042 D3B1     		cbz	r3, .L53
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 858              		.loc 1 449 7 is_stmt 1 view .LVU305
+ 859 0044 2268     		ldr	r2, [r4]
+ 860 0046 1368     		ldr	r3, [r2]
+ 861 0048 43F00E03 		orr	r3, r3, #14
+ 862 004c 1360     		str	r3, [r2]
+ 863              	.L54:
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 864              		.loc 1 458 5 view .LVU306
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 865              		.loc 1 458 14 is_stmt 0 view .LVU307
+ 866 004e A36C     		ldr	r3, [r4, #72]
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 867              		.loc 1 458 29 view .LVU308
+ 868 0050 1A68     		ldr	r2, [r3]
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 869              		.loc 1 458 8 view .LVU309
+ 870 0052 12F4803F 		tst	r2, #65536
+ 871 0056 03D0     		beq	.L55
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 872              		.loc 1 461 7 is_stmt 1 view .LVU310
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 873              		.loc 1 461 26 is_stmt 0 view .LVU311
+ 874 0058 1A68     		ldr	r2, [r3]
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 875              		.loc 1 461 32 view .LVU312
+ 876 005a 42F48072 		orr	r2, r2, #256
+ 877 005e 1A60     		str	r2, [r3]
+ 878              	.L55:
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 879              		.loc 1 464 5 is_stmt 1 view .LVU313
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 880              		.loc 1 464 13 is_stmt 0 view .LVU314
+ 881 0060 636D     		ldr	r3, [r4, #84]
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 882              		.loc 1 464 8 view .LVU315
+ 883 0062 1BB1     		cbz	r3, .L56
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 884              		.loc 1 468 7 is_stmt 1 view .LVU316
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 885              		.loc 1 468 29 is_stmt 0 view .LVU317
+ 886 0064 1A68     		ldr	r2, [r3]
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 887              		.loc 1 468 36 view .LVU318
+ 888 0066 42F48072 		orr	r2, r2, #256
+ 889 006a 1A60     		str	r2, [r3]
+ 890              	.L56:
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 891              		.loc 1 472 5 is_stmt 1 view .LVU319
+ 892 006c 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/ccCGP7ew.s 			page 40
+
+
+ 893 006e 1368     		ldr	r3, [r2]
+ 894 0070 43F00103 		orr	r3, r3, #1
+ 895 0074 1360     		str	r3, [r2]
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 896              		.loc 1 424 21 is_stmt 0 view .LVU320
+ 897 0076 0020     		movs	r0, #0
+ 898 0078 D4E7     		b	.L51
+ 899              	.L53:
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
+ 900              		.loc 1 453 7 is_stmt 1 view .LVU321
+ 901 007a 2268     		ldr	r2, [r4]
+ 902 007c 1368     		ldr	r3, [r2]
+ 903 007e 23F00403 		bic	r3, r3, #4
+ 904 0082 1360     		str	r3, [r2]
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 905              		.loc 1 454 7 view .LVU322
+ 906 0084 2268     		ldr	r2, [r4]
+ 907 0086 1368     		ldr	r3, [r2]
+ 908 0088 43F00A03 		orr	r3, r3, #10
+ 909 008c 1360     		str	r3, [r2]
+ 910 008e DEE7     		b	.L54
+ 911              	.LVL51:
+ 912              	.L57:
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 913              		.loc 1 430 3 is_stmt 0 view .LVU323
+ 914 0090 0220     		movs	r0, #2
+ 915 0092 C7E7     		b	.L51
+ 916              		.cfi_endproc
+ 917              	.LFE332:
+ 919              		.section	.text.HAL_DMA_Abort,"ax",%progbits
+ 920              		.align	1
+ 921              		.global	HAL_DMA_Abort
+ 922              		.syntax unified
+ 923              		.thumb
+ 924              		.thumb_func
+ 926              	HAL_DMA_Abort:
+ 927              	.LVL52:
+ 928              	.LFB333:
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 929              		.loc 1 492 1 is_stmt 1 view -0
+ 930              		.cfi_startproc
+ 931              		@ args = 0, pretend = 0, frame = 0
+ 932              		@ frame_needed = 0, uses_anonymous_args = 0
+ 933              		@ link register save eliminated.
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 934              		.loc 1 492 1 is_stmt 0 view .LVU325
+ 935 0000 0346     		mov	r3, r0
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 936              		.loc 1 493 3 is_stmt 1 view .LVU326
+ 937              	.LVL53:
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 938              		.loc 1 495 3 view .LVU327
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 939              		.loc 1 495 10 is_stmt 0 view .LVU328
+ 940 0002 90F82520 		ldrb	r2, [r0, #37]	@ zero_extendqisi2
+ 941 0006 D2B2     		uxtb	r2, r2
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ARM GAS  /tmp/ccCGP7ew.s 			page 41
+
+
+ 942              		.loc 1 495 5 view .LVU329
+ 943 0008 022A     		cmp	r2, #2
+ 944 000a 09D0     		beq	.L61
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 945              		.loc 1 498 5 is_stmt 1 view .LVU330
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 946              		.loc 1 498 21 is_stmt 0 view .LVU331
+ 947 000c 0422     		movs	r2, #4
+ 948 000e C263     		str	r2, [r0, #60]
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 949              		.loc 1 500 5 is_stmt 1 view .LVU332
+ 950              	.LVL54:
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 951              		.loc 1 500 12 is_stmt 0 view .LVU333
+ 952 0010 0120     		movs	r0, #1
+ 953              	.LVL55:
+ 954              	.L62:
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 955              		.loc 1 530 3 is_stmt 1 view .LVU334
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 956              		.loc 1 530 15 is_stmt 0 view .LVU335
+ 957 0012 0122     		movs	r2, #1
+ 958 0014 83F82520 		strb	r2, [r3, #37]
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 959              		.loc 1 533 3 is_stmt 1 view .LVU336
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 960              		.loc 1 533 3 view .LVU337
+ 961 0018 0022     		movs	r2, #0
+ 962 001a 83F82420 		strb	r2, [r3, #36]
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 963              		.loc 1 533 3 view .LVU338
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 964              		.loc 1 535 3 view .LVU339
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 965              		.loc 1 536 1 is_stmt 0 view .LVU340
+ 966 001e 7047     		bx	lr
+ 967              	.LVL56:
+ 968              	.L61:
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 969              		.loc 1 505 6 is_stmt 1 view .LVU341
+ 970 0020 0168     		ldr	r1, [r0]
+ 971 0022 0A68     		ldr	r2, [r1]
+ 972 0024 22F00E02 		bic	r2, r2, #14
+ 973 0028 0A60     		str	r2, [r1]
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 974              		.loc 1 508 6 view .LVU342
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 975              		.loc 1 508 10 is_stmt 0 view .LVU343
+ 976 002a 816C     		ldr	r1, [r0, #72]
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 977              		.loc 1 508 25 view .LVU344
+ 978 002c 0A68     		ldr	r2, [r1]
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 979              		.loc 1 508 31 view .LVU345
+ 980 002e 22F48072 		bic	r2, r2, #256
+ 981 0032 0A60     		str	r2, [r1]
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ARM GAS  /tmp/ccCGP7ew.s 			page 42
+
+
+ 982              		.loc 1 511 6 is_stmt 1 view .LVU346
+ 983 0034 0168     		ldr	r1, [r0]
+ 984 0036 0A68     		ldr	r2, [r1]
+ 985 0038 22F00102 		bic	r2, r2, #1
+ 986 003c 0A60     		str	r2, [r1]
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 987              		.loc 1 514 6 view .LVU347
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 988              		.loc 1 514 57 is_stmt 0 view .LVU348
+ 989 003e 426C     		ldr	r2, [r0, #68]
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 990              		.loc 1 514 72 view .LVU349
+ 991 0040 02F01F01 		and	r1, r2, #31
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 992              		.loc 1 514 10 view .LVU350
+ 993 0044 006C     		ldr	r0, [r0, #64]
+ 994              	.LVL57:
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 995              		.loc 1 514 49 view .LVU351
+ 996 0046 0122     		movs	r2, #1
+ 997 0048 8A40     		lsls	r2, r2, r1
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 998              		.loc 1 514 33 view .LVU352
+ 999 004a 4260     		str	r2, [r0, #4]
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 1000              		.loc 1 517 6 is_stmt 1 view .LVU353
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 1001              		.loc 1 517 10 is_stmt 0 view .LVU354
+ 1002 004c DA6C     		ldr	r2, [r3, #76]
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 1003              		.loc 1 517 43 view .LVU355
+ 1004 004e 196D     		ldr	r1, [r3, #80]
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 1005              		.loc 1 517 37 view .LVU356
+ 1006 0050 5160     		str	r1, [r2, #4]
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      {
+ 1007              		.loc 1 519 6 is_stmt 1 view .LVU357
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      {
+ 1008              		.loc 1 519 14 is_stmt 0 view .LVU358
+ 1009 0052 5A6D     		ldr	r2, [r3, #84]
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      {
+ 1010              		.loc 1 519 9 view .LVU359
+ 1011 0054 42B1     		cbz	r2, .L63
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 1012              		.loc 1 523 8 is_stmt 1 view .LVU360
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 1013              		.loc 1 523 30 is_stmt 0 view .LVU361
+ 1014 0056 1168     		ldr	r1, [r2]
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      
+ 1015              		.loc 1 523 37 view .LVU362
+ 1016 0058 21F48071 		bic	r1, r1, #256
+ 1017 005c 1160     		str	r1, [r2]
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      }
+ 1018              		.loc 1 526 8 is_stmt 1 view .LVU363
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      }
+ 1019              		.loc 1 526 12 is_stmt 0 view .LVU364
+ 1020 005e 9A6D     		ldr	r2, [r3, #88]
+ARM GAS  /tmp/ccCGP7ew.s 			page 43
+
+
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      }
+ 1021              		.loc 1 526 50 view .LVU365
+ 1022 0060 D96D     		ldr	r1, [r3, #92]
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****      }
+ 1023              		.loc 1 526 44 view .LVU366
+ 1024 0062 5160     		str	r1, [r2, #4]
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1025              		.loc 1 493 21 view .LVU367
+ 1026 0064 0020     		movs	r0, #0
+ 1027 0066 D4E7     		b	.L62
+ 1028              	.L63:
+ 1029 0068 0020     		movs	r0, #0
+ 1030 006a D2E7     		b	.L62
+ 1031              		.cfi_endproc
+ 1032              	.LFE333:
+ 1034              		.section	.text.HAL_DMA_Abort_IT,"ax",%progbits
+ 1035              		.align	1
+ 1036              		.global	HAL_DMA_Abort_IT
+ 1037              		.syntax unified
+ 1038              		.thumb
+ 1039              		.thumb_func
+ 1041              	HAL_DMA_Abort_IT:
+ 1042              	.LVL58:
+ 1043              	.LFB334:
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1044              		.loc 1 545 1 is_stmt 1 view -0
+ 1045              		.cfi_startproc
+ 1046              		@ args = 0, pretend = 0, frame = 0
+ 1047              		@ frame_needed = 0, uses_anonymous_args = 0
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1048              		.loc 1 545 1 is_stmt 0 view .LVU369
+ 1049 0000 08B5     		push	{r3, lr}
+ 1050              	.LCFI9:
+ 1051              		.cfi_def_cfa_offset 8
+ 1052              		.cfi_offset 3, -8
+ 1053              		.cfi_offset 14, -4
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1054              		.loc 1 546 3 is_stmt 1 view .LVU370
+ 1055              	.LVL59:
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1056              		.loc 1 548 3 view .LVU371
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1057              		.loc 1 548 33 is_stmt 0 view .LVU372
+ 1058 0002 90F82530 		ldrb	r3, [r0, #37]	@ zero_extendqisi2
+ 1059 0006 DBB2     		uxtb	r3, r3
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1060              		.loc 1 548 6 view .LVU373
+ 1061 0008 022B     		cmp	r3, #2
+ 1062 000a 09D0     		beq	.L65
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1063              		.loc 1 551 5 is_stmt 1 view .LVU374
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1064              		.loc 1 551 21 is_stmt 0 view .LVU375
+ 1065 000c 0423     		movs	r3, #4
+ 1066 000e C363     		str	r3, [r0, #60]
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1067              		.loc 1 554 5 is_stmt 1 view .LVU376
+ARM GAS  /tmp/ccCGP7ew.s 			page 44
+
+
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1068              		.loc 1 554 17 is_stmt 0 view .LVU377
+ 1069 0010 0123     		movs	r3, #1
+ 1070 0012 80F82530 		strb	r3, [r0, #37]
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1071              		.loc 1 557 5 is_stmt 1 view .LVU378
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1072              		.loc 1 557 5 view .LVU379
+ 1073 0016 0022     		movs	r2, #0
+ 1074 0018 80F82420 		strb	r2, [r0, #36]
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1075              		.loc 1 557 5 view .LVU380
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1076              		.loc 1 559 5 view .LVU381
+ 1077              	.LVL60:
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1078              		.loc 1 559 12 is_stmt 0 view .LVU382
+ 1079 001c 1846     		mov	r0, r3
+ 1080              	.LVL61:
+ 1081              	.L66:
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 1082              		.loc 1 600 3 is_stmt 1 view .LVU383
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1083              		.loc 1 601 1 is_stmt 0 view .LVU384
+ 1084 001e 08BD     		pop	{r3, pc}
+ 1085              	.LVL62:
+ 1086              	.L65:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1087              		.loc 1 564 5 is_stmt 1 view .LVU385
+ 1088 0020 0268     		ldr	r2, [r0]
+ 1089 0022 1368     		ldr	r3, [r2]
+ 1090 0024 23F00E03 		bic	r3, r3, #14
+ 1091 0028 1360     		str	r3, [r2]
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1092              		.loc 1 567 5 view .LVU386
+ 1093 002a 0268     		ldr	r2, [r0]
+ 1094 002c 1368     		ldr	r3, [r2]
+ 1095 002e 23F00103 		bic	r3, r3, #1
+ 1096 0032 1360     		str	r3, [r2]
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1097              		.loc 1 570 5 view .LVU387
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1098              		.loc 1 570 9 is_stmt 0 view .LVU388
+ 1099 0034 826C     		ldr	r2, [r0, #72]
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1100              		.loc 1 570 24 view .LVU389
+ 1101 0036 1368     		ldr	r3, [r2]
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1102              		.loc 1 570 30 view .LVU390
+ 1103 0038 23F48073 		bic	r3, r3, #256
+ 1104 003c 1360     		str	r3, [r2]
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1105              		.loc 1 573 5 is_stmt 1 view .LVU391
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1106              		.loc 1 573 56 is_stmt 0 view .LVU392
+ 1107 003e 436C     		ldr	r3, [r0, #68]
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ARM GAS  /tmp/ccCGP7ew.s 			page 45
+
+
+ 1108              		.loc 1 573 71 view .LVU393
+ 1109 0040 03F01F02 		and	r2, r3, #31
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1110              		.loc 1 573 9 view .LVU394
+ 1111 0044 016C     		ldr	r1, [r0, #64]
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1112              		.loc 1 573 48 view .LVU395
+ 1113 0046 0123     		movs	r3, #1
+ 1114 0048 9340     		lsls	r3, r3, r2
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1115              		.loc 1 573 32 view .LVU396
+ 1116 004a 4B60     		str	r3, [r1, #4]
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1117              		.loc 1 576 5 is_stmt 1 view .LVU397
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1118              		.loc 1 576 9 is_stmt 0 view .LVU398
+ 1119 004c C36C     		ldr	r3, [r0, #76]
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1120              		.loc 1 576 42 view .LVU399
+ 1121 004e 026D     		ldr	r2, [r0, #80]
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1122              		.loc 1 576 36 view .LVU400
+ 1123 0050 5A60     		str	r2, [r3, #4]
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1124              		.loc 1 578 5 is_stmt 1 view .LVU401
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1125              		.loc 1 578 13 is_stmt 0 view .LVU402
+ 1126 0052 436D     		ldr	r3, [r0, #84]
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1127              		.loc 1 578 8 view .LVU403
+ 1128 0054 33B1     		cbz	r3, .L67
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1129              		.loc 1 582 7 is_stmt 1 view .LVU404
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1130              		.loc 1 582 29 is_stmt 0 view .LVU405
+ 1131 0056 1A68     		ldr	r2, [r3]
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1132              		.loc 1 582 36 view .LVU406
+ 1133 0058 22F48072 		bic	r2, r2, #256
+ 1134 005c 1A60     		str	r2, [r3]
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1135              		.loc 1 585 7 is_stmt 1 view .LVU407
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1136              		.loc 1 585 11 is_stmt 0 view .LVU408
+ 1137 005e 836D     		ldr	r3, [r0, #88]
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1138              		.loc 1 585 49 view .LVU409
+ 1139 0060 C26D     		ldr	r2, [r0, #92]
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1140              		.loc 1 585 43 view .LVU410
+ 1141 0062 5A60     		str	r2, [r3, #4]
+ 1142              	.L67:
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1143              		.loc 1 589 5 is_stmt 1 view .LVU411
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1144              		.loc 1 589 17 is_stmt 0 view .LVU412
+ 1145 0064 0123     		movs	r3, #1
+ARM GAS  /tmp/ccCGP7ew.s 			page 46
+
+
+ 1146 0066 80F82530 		strb	r3, [r0, #37]
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1147              		.loc 1 592 5 is_stmt 1 view .LVU413
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1148              		.loc 1 592 5 view .LVU414
+ 1149 006a 0023     		movs	r3, #0
+ 1150 006c 80F82430 		strb	r3, [r0, #36]
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1151              		.loc 1 592 5 view .LVU415
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1152              		.loc 1 595 5 view .LVU416
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1153              		.loc 1 595 13 is_stmt 0 view .LVU417
+ 1154 0070 836B     		ldr	r3, [r0, #56]
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1155              		.loc 1 595 8 view .LVU418
+ 1156 0072 13B1     		cbz	r3, .L68
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1157              		.loc 1 597 7 is_stmt 1 view .LVU419
+ 1158 0074 9847     		blx	r3
+ 1159              	.LVL63:
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1160              		.loc 1 546 21 is_stmt 0 view .LVU420
+ 1161 0076 0020     		movs	r0, #0
+ 1162 0078 D1E7     		b	.L66
+ 1163              	.LVL64:
+ 1164              	.L68:
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1165              		.loc 1 546 21 view .LVU421
+ 1166 007a 0020     		movs	r0, #0
+ 1167              	.LVL65:
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1168              		.loc 1 546 21 view .LVU422
+ 1169 007c CFE7     		b	.L66
+ 1170              		.cfi_endproc
+ 1171              	.LFE334:
+ 1173              		.section	.text.HAL_DMA_PollForTransfer,"ax",%progbits
+ 1174              		.align	1
+ 1175              		.global	HAL_DMA_PollForTransfer
+ 1176              		.syntax unified
+ 1177              		.thumb
+ 1178              		.thumb_func
+ 1180              	HAL_DMA_PollForTransfer:
+ 1181              	.LVL66:
+ 1182              	.LFB335:
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t temp;
+ 1183              		.loc 1 613 1 is_stmt 1 view -0
+ 1184              		.cfi_startproc
+ 1185              		@ args = 0, pretend = 0, frame = 0
+ 1186              		@ frame_needed = 0, uses_anonymous_args = 0
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t temp;
+ 1187              		.loc 1 613 1 is_stmt 0 view .LVU424
+ 1188 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 1189              	.LCFI10:
+ 1190              		.cfi_def_cfa_offset 24
+ 1191              		.cfi_offset 4, -24
+ 1192              		.cfi_offset 5, -20
+ARM GAS  /tmp/ccCGP7ew.s 			page 47
+
+
+ 1193              		.cfi_offset 6, -16
+ 1194              		.cfi_offset 7, -12
+ 1195              		.cfi_offset 8, -8
+ 1196              		.cfi_offset 14, -4
+ 1197 0004 0446     		mov	r4, r0
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t tickstart;
+ 1198              		.loc 1 614 3 is_stmt 1 view .LVU425
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1199              		.loc 1 615 3 view .LVU426
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1200              		.loc 1 617 3 view .LVU427
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1201              		.loc 1 617 33 is_stmt 0 view .LVU428
+ 1202 0006 90F82530 		ldrb	r3, [r0, #37]	@ zero_extendqisi2
+ 1203 000a DBB2     		uxtb	r3, r3
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1204              		.loc 1 617 6 view .LVU429
+ 1205 000c 022B     		cmp	r3, #2
+ 1206 000e 07D0     		beq	.L71
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 1207              		.loc 1 620 5 is_stmt 1 view .LVU430
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 1208              		.loc 1 620 21 is_stmt 0 view .LVU431
+ 1209 0010 0423     		movs	r3, #4
+ 1210 0012 C363     		str	r3, [r0, #60]
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     return HAL_ERROR;
+ 1211              		.loc 1 621 5 is_stmt 1 view .LVU432
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     return HAL_ERROR;
+ 1212              		.loc 1 621 5 view .LVU433
+ 1213 0014 0023     		movs	r3, #0
+ 1214 0016 80F82430 		strb	r3, [r0, #36]
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     return HAL_ERROR;
+ 1215              		.loc 1 621 5 view .LVU434
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1216              		.loc 1 622 5 view .LVU435
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1217              		.loc 1 622 12 is_stmt 0 view .LVU436
+ 1218 001a 0120     		movs	r0, #1
+ 1219              	.LVL67:
+ 1220              	.L72:
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1221              		.loc 1 733 1 view .LVU437
+ 1222 001c BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 1223              	.LVL68:
+ 1224              	.L71:
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1225              		.loc 1 733 1 view .LVU438
+ 1226 0020 0F46     		mov	r7, r1
+ 1227 0022 1546     		mov	r5, r2
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1228              		.loc 1 626 3 is_stmt 1 view .LVU439
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1229              		.loc 1 626 18 is_stmt 0 view .LVU440
+ 1230 0024 0368     		ldr	r3, [r0]
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1231              		.loc 1 626 28 view .LVU441
+ 1232 0026 1B68     		ldr	r3, [r3]
+ARM GAS  /tmp/ccCGP7ew.s 			page 48
+
+
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1233              		.loc 1 626 6 view .LVU442
+ 1234 0028 13F0200F 		tst	r3, #32
+ 1235 002c 2BD1     		bne	.L86
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1236              		.loc 1 633 3 is_stmt 1 view .LVU443
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1237              		.loc 1 633 6 is_stmt 0 view .LVU444
+ 1238 002e 79BB     		cbnz	r1, .L74
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1239              		.loc 1 637 5 is_stmt 1 view .LVU445
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1240              		.loc 1 637 43 is_stmt 0 view .LVU446
+ 1241 0030 436C     		ldr	r3, [r0, #68]
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1242              		.loc 1 637 58 view .LVU447
+ 1243 0032 03F01F03 		and	r3, r3, #31
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1244              		.loc 1 637 10 view .LVU448
+ 1245 0036 0226     		movs	r6, #2
+ 1246 0038 9E40     		lsls	r6, r6, r3
+ 1247              	.LVL69:
+ 1248              	.L75:
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1249              		.loc 1 646 3 is_stmt 1 view .LVU449
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1250              		.loc 1 646 15 is_stmt 0 view .LVU450
+ 1251 003a FFF7FEFF 		bl	HAL_GetTick
+ 1252              	.LVL70:
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1253              		.loc 1 646 15 view .LVU451
+ 1254 003e 8046     		mov	r8, r0
+ 1255              	.LVL71:
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1256              		.loc 1 648 3 is_stmt 1 view .LVU452
+ 1257              	.L78:
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1258              		.loc 1 648 13 view .LVU453
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1259              		.loc 1 648 21 is_stmt 0 view .LVU454
+ 1260 0040 226C     		ldr	r2, [r4, #64]
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1261              		.loc 1 648 37 view .LVU455
+ 1262 0042 1368     		ldr	r3, [r2]
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1263              		.loc 1 648 13 view .LVU456
+ 1264 0044 3342     		tst	r3, r6
+ 1265 0046 34D1     		bne	.L87
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1266              		.loc 1 650 5 is_stmt 1 view .LVU457
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1267              		.loc 1 650 37 is_stmt 0 view .LVU458
+ 1268 0048 1168     		ldr	r1, [r2]
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1269              		.loc 1 650 77 view .LVU459
+ 1270 004a 636C     		ldr	r3, [r4, #68]
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ARM GAS  /tmp/ccCGP7ew.s 			page 49
+
+
+ 1271              		.loc 1 650 92 view .LVU460
+ 1272 004c 03F01F03 		and	r3, r3, #31
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1273              		.loc 1 650 69 view .LVU461
+ 1274 0050 4FF0080C 		mov	ip, #8
+ 1275 0054 0CFA03FC 		lsl	ip, ip, r3
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1276              		.loc 1 650 8 view .LVU462
+ 1277 0058 11EA0C0F 		tst	r1, ip
+ 1278 005c 1ED1     		bne	.L88
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1279              		.loc 1 669 5 is_stmt 1 view .LVU463
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1280              		.loc 1 669 8 is_stmt 0 view .LVU464
+ 1281 005e B5F1FF3F 		cmp	r5, #-1
+ 1282 0062 EDD0     		beq	.L78
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       {
+ 1283              		.loc 1 671 7 is_stmt 1 view .LVU465
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       {
+ 1284              		.loc 1 671 13 is_stmt 0 view .LVU466
+ 1285 0064 FFF7FEFF 		bl	HAL_GetTick
+ 1286              	.LVL72:
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       {
+ 1287              		.loc 1 671 27 view .LVU467
+ 1288 0068 A0EB0800 		sub	r0, r0, r8
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       {
+ 1289              		.loc 1 671 10 view .LVU468
+ 1290 006c A842     		cmp	r0, r5
+ 1291 006e 01D8     		bhi	.L79
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       {
+ 1292              		.loc 1 671 51 discriminator 1 view .LVU469
+ 1293 0070 002D     		cmp	r5, #0
+ 1294 0072 E5D1     		bne	.L78
+ 1295              	.L79:
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1296              		.loc 1 674 9 is_stmt 1 view .LVU470
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1297              		.loc 1 674 25 is_stmt 0 view .LVU471
+ 1298 0074 2023     		movs	r3, #32
+ 1299 0076 E363     		str	r3, [r4, #60]
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1300              		.loc 1 677 9 is_stmt 1 view .LVU472
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1301              		.loc 1 677 21 is_stmt 0 view .LVU473
+ 1302 0078 0120     		movs	r0, #1
+ 1303 007a 84F82500 		strb	r0, [r4, #37]
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1304              		.loc 1 680 9 is_stmt 1 view .LVU474
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1305              		.loc 1 680 9 view .LVU475
+ 1306 007e 0023     		movs	r3, #0
+ 1307 0080 84F82430 		strb	r3, [r4, #36]
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1308              		.loc 1 680 9 view .LVU476
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       }
+ 1309              		.loc 1 682 9 view .LVU477
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****       }
+ARM GAS  /tmp/ccCGP7ew.s 			page 50
+
+
+ 1310              		.loc 1 682 16 is_stmt 0 view .LVU478
+ 1311 0084 CAE7     		b	.L72
+ 1312              	.LVL73:
+ 1313              	.L86:
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     return HAL_ERROR;
+ 1314              		.loc 1 628 5 is_stmt 1 view .LVU479
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     return HAL_ERROR;
+ 1315              		.loc 1 628 21 is_stmt 0 view .LVU480
+ 1316 0086 4FF48073 		mov	r3, #256
+ 1317 008a C363     		str	r3, [r0, #60]
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1318              		.loc 1 629 5 is_stmt 1 view .LVU481
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1319              		.loc 1 629 12 is_stmt 0 view .LVU482
+ 1320 008c 0120     		movs	r0, #1
+ 1321              	.LVL74:
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1322              		.loc 1 629 12 view .LVU483
+ 1323 008e C5E7     		b	.L72
+ 1324              	.LVL75:
+ 1325              	.L74:
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1326              		.loc 1 642 5 is_stmt 1 view .LVU484
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1327              		.loc 1 642 43 is_stmt 0 view .LVU485
+ 1328 0090 436C     		ldr	r3, [r0, #68]
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1329              		.loc 1 642 58 view .LVU486
+ 1330 0092 03F01F03 		and	r3, r3, #31
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1331              		.loc 1 642 10 view .LVU487
+ 1332 0096 0426     		movs	r6, #4
+ 1333 0098 9E40     		lsls	r6, r6, r3
+ 1334              	.LVL76:
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1335              		.loc 1 642 10 view .LVU488
+ 1336 009a CEE7     		b	.L75
+ 1337              	.LVL77:
+ 1338              	.L88:
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1339              		.loc 1 655 7 is_stmt 1 view .LVU489
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1340              		.loc 1 655 60 is_stmt 0 view .LVU490
+ 1341 009c 0120     		movs	r0, #1
+ 1342 009e 00FA03F3 		lsl	r3, r0, r3
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1343              		.loc 1 655 34 view .LVU491
+ 1344 00a2 5360     		str	r3, [r2, #4]
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1345              		.loc 1 658 7 is_stmt 1 view .LVU492
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1346              		.loc 1 658 23 is_stmt 0 view .LVU493
+ 1347 00a4 E063     		str	r0, [r4, #60]
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1348              		.loc 1 661 7 is_stmt 1 view .LVU494
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1349              		.loc 1 661 19 is_stmt 0 view .LVU495
+ARM GAS  /tmp/ccCGP7ew.s 			page 51
+
+
+ 1350 00a6 84F82500 		strb	r0, [r4, #37]
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1351              		.loc 1 664 7 is_stmt 1 view .LVU496
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1352              		.loc 1 664 7 view .LVU497
+ 1353 00aa 0023     		movs	r3, #0
+ 1354 00ac 84F82430 		strb	r3, [r4, #36]
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1355              		.loc 1 664 7 view .LVU498
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1356              		.loc 1 666 7 view .LVU499
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1357              		.loc 1 666 14 is_stmt 0 view .LVU500
+ 1358 00b0 B4E7     		b	.L72
+ 1359              	.L87:
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1360              		.loc 1 688 3 is_stmt 1 view .LVU501
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1361              		.loc 1 688 11 is_stmt 0 view .LVU502
+ 1362 00b2 636D     		ldr	r3, [r4, #84]
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1363              		.loc 1 688 6 view .LVU503
+ 1364 00b4 7BB1     		cbz	r3, .L81
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1365              		.loc 1 691 5 is_stmt 1 view .LVU504
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1366              		.loc 1 691 14 is_stmt 0 view .LVU505
+ 1367 00b6 A26D     		ldr	r2, [r4, #88]
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1368              		.loc 1 691 38 view .LVU506
+ 1369 00b8 1168     		ldr	r1, [r2]
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1370              		.loc 1 691 51 view .LVU507
+ 1371 00ba E26D     		ldr	r2, [r4, #92]
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1372              		.loc 1 691 8 view .LVU508
+ 1373 00bc 1142     		tst	r1, r2
+ 1374 00be 0AD0     		beq	.L81
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1375              		.loc 1 694 7 is_stmt 1 view .LVU509
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1376              		.loc 1 694 29 is_stmt 0 view .LVU510
+ 1377 00c0 1A68     		ldr	r2, [r3]
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1378              		.loc 1 694 36 view .LVU511
+ 1379 00c2 42F48072 		orr	r2, r2, #256
+ 1380 00c6 1A60     		str	r2, [r3]
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1381              		.loc 1 697 7 is_stmt 1 view .LVU512
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1382              		.loc 1 697 11 is_stmt 0 view .LVU513
+ 1383 00c8 A36D     		ldr	r3, [r4, #88]
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1384              		.loc 1 697 49 view .LVU514
+ 1385 00ca E26D     		ldr	r2, [r4, #92]
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1386              		.loc 1 697 43 view .LVU515
+ARM GAS  /tmp/ccCGP7ew.s 			page 52
+
+
+ 1387 00cc 5A60     		str	r2, [r3, #4]
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1388              		.loc 1 700 7 is_stmt 1 view .LVU516
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1389              		.loc 1 700 11 is_stmt 0 view .LVU517
+ 1390 00ce E36B     		ldr	r3, [r4, #60]
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1391              		.loc 1 700 23 view .LVU518
+ 1392 00d0 43F48063 		orr	r3, r3, #1024
+ 1393 00d4 E363     		str	r3, [r4, #60]
+ 1394              	.L81:
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1395              		.loc 1 705 3 is_stmt 1 view .LVU519
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1396              		.loc 1 705 12 is_stmt 0 view .LVU520
+ 1397 00d6 E36C     		ldr	r3, [r4, #76]
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1398              		.loc 1 705 33 view .LVU521
+ 1399 00d8 1968     		ldr	r1, [r3]
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1400              		.loc 1 705 45 view .LVU522
+ 1401 00da 226D     		ldr	r2, [r4, #80]
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1402              		.loc 1 705 6 view .LVU523
+ 1403 00dc 1142     		tst	r1, r2
+ 1404 00de 04D0     		beq	.L82
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1405              		.loc 1 708 5 is_stmt 1 view .LVU524
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1406              		.loc 1 708 36 is_stmt 0 view .LVU525
+ 1407 00e0 5A60     		str	r2, [r3, #4]
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1408              		.loc 1 711 5 is_stmt 1 view .LVU526
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1409              		.loc 1 711 9 is_stmt 0 view .LVU527
+ 1410 00e2 E36B     		ldr	r3, [r4, #60]
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1411              		.loc 1 711 21 view .LVU528
+ 1412 00e4 43F40073 		orr	r3, r3, #512
+ 1413 00e8 E363     		str	r3, [r4, #60]
+ 1414              	.L82:
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1415              		.loc 1 714 3 is_stmt 1 view .LVU529
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1416              		.loc 1 714 6 is_stmt 0 view .LVU530
+ 1417 00ea 6FB9     		cbnz	r7, .L83
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1418              		.loc 1 717 5 is_stmt 1 view .LVU531
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1419              		.loc 1 717 66 is_stmt 0 view .LVU532
+ 1420 00ec 636C     		ldr	r3, [r4, #68]
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1421              		.loc 1 717 81 view .LVU533
+ 1422 00ee 03F01F02 		and	r2, r3, #31
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1423              		.loc 1 717 9 view .LVU534
+ 1424 00f2 216C     		ldr	r1, [r4, #64]
+ARM GAS  /tmp/ccCGP7ew.s 			page 53
+
+
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1425              		.loc 1 717 58 view .LVU535
+ 1426 00f4 0223     		movs	r3, #2
+ 1427 00f6 9340     		lsls	r3, r3, r2
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1428              		.loc 1 717 32 view .LVU536
+ 1429 00f8 4B60     		str	r3, [r1, #4]
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1430              		.loc 1 721 5 is_stmt 1 view .LVU537
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1431              		.loc 1 721 17 is_stmt 0 view .LVU538
+ 1432 00fa 0123     		movs	r3, #1
+ 1433 00fc 84F82530 		strb	r3, [r4, #37]
+ 1434              	.L84:
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1435              		.loc 1 730 3 is_stmt 1 view .LVU539
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1436              		.loc 1 730 3 view .LVU540
+ 1437 0100 0020     		movs	r0, #0
+ 1438 0102 84F82400 		strb	r0, [r4, #36]
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1439              		.loc 1 730 3 view .LVU541
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 1440              		.loc 1 732 3 view .LVU542
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 1441              		.loc 1 732 10 is_stmt 0 view .LVU543
+ 1442 0106 89E7     		b	.L72
+ 1443              	.L83:
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1444              		.loc 1 726 5 is_stmt 1 view .LVU544
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1445              		.loc 1 726 66 is_stmt 0 view .LVU545
+ 1446 0108 636C     		ldr	r3, [r4, #68]
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1447              		.loc 1 726 81 view .LVU546
+ 1448 010a 03F01F02 		and	r2, r3, #31
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1449              		.loc 1 726 9 view .LVU547
+ 1450 010e 216C     		ldr	r1, [r4, #64]
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1451              		.loc 1 726 58 view .LVU548
+ 1452 0110 0423     		movs	r3, #4
+ 1453 0112 9340     		lsls	r3, r3, r2
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1454              		.loc 1 726 32 view .LVU549
+ 1455 0114 4B60     		str	r3, [r1, #4]
+ 1456 0116 F3E7     		b	.L84
+ 1457              		.cfi_endproc
+ 1458              	.LFE335:
+ 1460              		.section	.text.HAL_DMA_IRQHandler,"ax",%progbits
+ 1461              		.align	1
+ 1462              		.global	HAL_DMA_IRQHandler
+ 1463              		.syntax unified
+ 1464              		.thumb
+ 1465              		.thumb_func
+ 1467              	HAL_DMA_IRQHandler:
+ 1468              	.LVL78:
+ARM GAS  /tmp/ccCGP7ew.s 			page 54
+
+
+ 1469              	.LFB336:
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+ 1470              		.loc 1 742 1 is_stmt 1 view -0
+ 1471              		.cfi_startproc
+ 1472              		@ args = 0, pretend = 0, frame = 0
+ 1473              		@ frame_needed = 0, uses_anonymous_args = 0
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+ 1474              		.loc 1 742 1 is_stmt 0 view .LVU551
+ 1475 0000 38B5     		push	{r3, r4, r5, lr}
+ 1476              	.LCFI11:
+ 1477              		.cfi_def_cfa_offset 16
+ 1478              		.cfi_offset 3, -16
+ 1479              		.cfi_offset 4, -12
+ 1480              		.cfi_offset 5, -8
+ 1481              		.cfi_offset 14, -4
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t source_it = hdma->Instance->CCR;
+ 1482              		.loc 1 743 3 is_stmt 1 view .LVU552
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t source_it = hdma->Instance->CCR;
+ 1483              		.loc 1 743 26 is_stmt 0 view .LVU553
+ 1484 0002 036C     		ldr	r3, [r0, #64]
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   uint32_t source_it = hdma->Instance->CCR;
+ 1485              		.loc 1 743 12 view .LVU554
+ 1486 0004 1968     		ldr	r1, [r3]
+ 1487              	.LVL79:
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1488              		.loc 1 744 3 is_stmt 1 view .LVU555
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1489              		.loc 1 744 28 is_stmt 0 view .LVU556
+ 1490 0006 0468     		ldr	r4, [r0]
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1491              		.loc 1 744 12 view .LVU557
+ 1492 0008 2568     		ldr	r5, [r4]
+ 1493              	.LVL80:
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1494              		.loc 1 747 3 is_stmt 1 view .LVU558
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1495              		.loc 1 747 57 is_stmt 0 view .LVU559
+ 1496 000a 436C     		ldr	r3, [r0, #68]
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1497              		.loc 1 747 72 view .LVU560
+ 1498 000c 03F01F03 		and	r3, r3, #31
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1499              		.loc 1 747 49 view .LVU561
+ 1500 0010 0422     		movs	r2, #4
+ 1501 0012 9A40     		lsls	r2, r2, r3
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1502              		.loc 1 747 6 view .LVU562
+ 1503 0014 0A42     		tst	r2, r1
+ 1504 0016 15D0     		beq	.L90
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1505              		.loc 1 747 84 discriminator 1 view .LVU563
+ 1506 0018 15F0040F 		tst	r5, #4
+ 1507 001c 12D0     		beq	.L90
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1508              		.loc 1 750 5 is_stmt 1 view .LVU564
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1509              		.loc 1 750 24 is_stmt 0 view .LVU565
+ARM GAS  /tmp/ccCGP7ew.s 			page 55
+
+
+ 1510 001e 2368     		ldr	r3, [r4]
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1511              		.loc 1 750 8 view .LVU566
+ 1512 0020 13F0200F 		tst	r3, #32
+ 1513 0024 03D1     		bne	.L91
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1514              		.loc 1 753 7 is_stmt 1 view .LVU567
+ 1515 0026 2368     		ldr	r3, [r4]
+ 1516 0028 23F00403 		bic	r3, r3, #4
+ 1517 002c 2360     		str	r3, [r4]
+ 1518              	.L91:
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1519              		.loc 1 756 5 view .LVU568
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1520              		.loc 1 756 67 is_stmt 0 view .LVU569
+ 1521 002e 436C     		ldr	r3, [r0, #68]
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1522              		.loc 1 756 82 view .LVU570
+ 1523 0030 03F01F02 		and	r2, r3, #31
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1524              		.loc 1 756 9 view .LVU571
+ 1525 0034 016C     		ldr	r1, [r0, #64]
+ 1526              	.LVL81:
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1527              		.loc 1 756 59 view .LVU572
+ 1528 0036 0423     		movs	r3, #4
+ 1529 0038 9340     		lsls	r3, r3, r2
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1530              		.loc 1 756 32 view .LVU573
+ 1531 003a 4B60     		str	r3, [r1, #4]
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1532              		.loc 1 761 5 is_stmt 1 view .LVU574
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1533              		.loc 1 761 13 is_stmt 0 view .LVU575
+ 1534 003c 036B     		ldr	r3, [r0, #48]
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1535              		.loc 1 761 8 view .LVU576
+ 1536 003e 03B1     		cbz	r3, .L89
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1537              		.loc 1 764 7 is_stmt 1 view .LVU577
+ 1538 0040 9847     		blx	r3
+ 1539              	.LVL82:
+ 1540              	.L89:
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1541              		.loc 1 823 1 is_stmt 0 view .LVU578
+ 1542 0042 38BD     		pop	{r3, r4, r5, pc}
+ 1543              	.LVL83:
+ 1544              	.L90:
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****            && (0U != (source_it & DMA_IT_TC)))
+ 1545              		.loc 1 768 8 is_stmt 1 view .LVU579
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****            && (0U != (source_it & DMA_IT_TC)))
+ 1546              		.loc 1 768 54 is_stmt 0 view .LVU580
+ 1547 0044 0222     		movs	r2, #2
+ 1548 0046 9A40     		lsls	r2, r2, r3
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****            && (0U != (source_it & DMA_IT_TC)))
+ 1549              		.loc 1 768 11 view .LVU581
+ 1550 0048 0A42     		tst	r2, r1
+ARM GAS  /tmp/ccCGP7ew.s 			page 56
+
+
+ 1551 004a 1CD0     		beq	.L93
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1552              		.loc 1 769 12 view .LVU582
+ 1553 004c 15F0020F 		tst	r5, #2
+ 1554 0050 19D0     		beq	.L93
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1555              		.loc 1 771 5 is_stmt 1 view .LVU583
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1556              		.loc 1 771 24 is_stmt 0 view .LVU584
+ 1557 0052 2368     		ldr	r3, [r4]
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1558              		.loc 1 771 8 view .LVU585
+ 1559 0054 13F0200F 		tst	r3, #32
+ 1560 0058 06D1     		bne	.L94
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1561              		.loc 1 774 7 is_stmt 1 view .LVU586
+ 1562 005a 2368     		ldr	r3, [r4]
+ 1563 005c 23F00A03 		bic	r3, r3, #10
+ 1564 0060 2360     		str	r3, [r4]
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1565              		.loc 1 777 7 view .LVU587
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1566              		.loc 1 777 19 is_stmt 0 view .LVU588
+ 1567 0062 0123     		movs	r3, #1
+ 1568 0064 80F82530 		strb	r3, [r0, #37]
+ 1569              	.L94:
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1570              		.loc 1 780 5 is_stmt 1 view .LVU589
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1571              		.loc 1 780 67 is_stmt 0 view .LVU590
+ 1572 0068 436C     		ldr	r3, [r0, #68]
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1573              		.loc 1 780 82 view .LVU591
+ 1574 006a 03F01F02 		and	r2, r3, #31
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1575              		.loc 1 780 9 view .LVU592
+ 1576 006e 016C     		ldr	r1, [r0, #64]
+ 1577              	.LVL84:
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1578              		.loc 1 780 59 view .LVU593
+ 1579 0070 0223     		movs	r3, #2
+ 1580 0072 9340     		lsls	r3, r3, r2
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1581              		.loc 1 780 32 view .LVU594
+ 1582 0074 4B60     		str	r3, [r1, #4]
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1583              		.loc 1 783 5 is_stmt 1 view .LVU595
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1584              		.loc 1 783 5 view .LVU596
+ 1585 0076 0023     		movs	r3, #0
+ 1586 0078 80F82430 		strb	r3, [r0, #36]
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1587              		.loc 1 783 5 view .LVU597
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1588              		.loc 1 785 5 view .LVU598
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1589              		.loc 1 785 13 is_stmt 0 view .LVU599
+ARM GAS  /tmp/ccCGP7ew.s 			page 57
+
+
+ 1590 007c C36A     		ldr	r3, [r0, #44]
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1591              		.loc 1 785 8 view .LVU600
+ 1592 007e 002B     		cmp	r3, #0
+ 1593 0080 DFD0     		beq	.L89
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1594              		.loc 1 788 7 is_stmt 1 view .LVU601
+ 1595 0082 9847     		blx	r3
+ 1596              	.LVL85:
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1597              		.loc 1 788 7 is_stmt 0 view .LVU602
+ 1598 0084 DDE7     		b	.L89
+ 1599              	.LVL86:
+ 1600              	.L93:
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****            && (0U != (source_it & DMA_IT_TE)))
+ 1601              		.loc 1 792 8 is_stmt 1 view .LVU603
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****            && (0U != (source_it & DMA_IT_TE)))
+ 1602              		.loc 1 792 54 is_stmt 0 view .LVU604
+ 1603 0086 0822     		movs	r2, #8
+ 1604 0088 02FA03F3 		lsl	r3, r2, r3
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****            && (0U != (source_it & DMA_IT_TE)))
+ 1605              		.loc 1 792 11 view .LVU605
+ 1606 008c 0B42     		tst	r3, r1
+ 1607 008e D8D0     		beq	.L89
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1608              		.loc 1 793 12 view .LVU606
+ 1609 0090 15F0080F 		tst	r5, #8
+ 1610 0094 D5D0     		beq	.L89
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1611              		.loc 1 798 5 is_stmt 1 view .LVU607
+ 1612 0096 2368     		ldr	r3, [r4]
+ 1613 0098 23F00E03 		bic	r3, r3, #14
+ 1614 009c 2360     		str	r3, [r4]
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1615              		.loc 1 801 5 view .LVU608
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1616              		.loc 1 801 66 is_stmt 0 view .LVU609
+ 1617 009e 436C     		ldr	r3, [r0, #68]
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1618              		.loc 1 801 81 view .LVU610
+ 1619 00a0 03F01F03 		and	r3, r3, #31
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1620              		.loc 1 801 9 view .LVU611
+ 1621 00a4 016C     		ldr	r1, [r0, #64]
+ 1622              	.LVL87:
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1623              		.loc 1 801 58 view .LVU612
+ 1624 00a6 0122     		movs	r2, #1
+ 1625 00a8 02FA03F3 		lsl	r3, r2, r3
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1626              		.loc 1 801 32 view .LVU613
+ 1627 00ac 4B60     		str	r3, [r1, #4]
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1628              		.loc 1 804 5 is_stmt 1 view .LVU614
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1629              		.loc 1 804 21 is_stmt 0 view .LVU615
+ 1630 00ae C263     		str	r2, [r0, #60]
+ARM GAS  /tmp/ccCGP7ew.s 			page 58
+
+
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1631              		.loc 1 807 5 is_stmt 1 view .LVU616
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1632              		.loc 1 807 17 is_stmt 0 view .LVU617
+ 1633 00b0 80F82520 		strb	r2, [r0, #37]
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1634              		.loc 1 810 5 is_stmt 1 view .LVU618
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1635              		.loc 1 810 5 view .LVU619
+ 1636 00b4 0023     		movs	r3, #0
+ 1637 00b6 80F82430 		strb	r3, [r0, #36]
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1638              		.loc 1 810 5 view .LVU620
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1639              		.loc 1 812 5 view .LVU621
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1640              		.loc 1 812 13 is_stmt 0 view .LVU622
+ 1641 00ba 436B     		ldr	r3, [r0, #52]
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1642              		.loc 1 812 8 view .LVU623
+ 1643 00bc 002B     		cmp	r3, #0
+ 1644 00be C0D0     		beq	.L89
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     }
+ 1645              		.loc 1 815 7 is_stmt 1 view .LVU624
+ 1646 00c0 9847     		blx	r3
+ 1647              	.LVL88:
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return;
+ 1648              		.loc 1 821 3 view .LVU625
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 1649              		.loc 1 822 3 view .LVU626
+ 1650 00c2 BEE7     		b	.L89
+ 1651              		.cfi_endproc
+ 1652              	.LFE336:
+ 1654              		.section	.text.HAL_DMA_RegisterCallback,"ax",%progbits
+ 1655              		.align	1
+ 1656              		.global	HAL_DMA_RegisterCallback
+ 1657              		.syntax unified
+ 1658              		.thumb
+ 1659              		.thumb_func
+ 1661              	HAL_DMA_RegisterCallback:
+ 1662              	.LVL89:
+ 1663              	.LFB337:
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1664              		.loc 1 836 1 view -0
+ 1665              		.cfi_startproc
+ 1666              		@ args = 0, pretend = 0, frame = 0
+ 1667              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1668              		@ link register save eliminated.
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1669              		.loc 1 836 1 is_stmt 0 view .LVU628
+ 1670 0000 0346     		mov	r3, r0
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1671              		.loc 1 837 3 is_stmt 1 view .LVU629
+ 1672              	.LVL90:
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1673              		.loc 1 840 3 view .LVU630
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ARM GAS  /tmp/ccCGP7ew.s 			page 59
+
+
+ 1674              		.loc 1 840 3 view .LVU631
+ 1675 0002 90F82400 		ldrb	r0, [r0, #36]	@ zero_extendqisi2
+ 1676              	.LVL91:
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1677              		.loc 1 840 3 is_stmt 0 view .LVU632
+ 1678 0006 0128     		cmp	r0, #1
+ 1679 0008 1ED0     		beq	.L104
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1680              		.loc 1 840 3 is_stmt 1 discriminator 2 view .LVU633
+ 1681 000a 0120     		movs	r0, #1
+ 1682 000c 83F82400 		strb	r0, [r3, #36]
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1683              		.loc 1 840 3 discriminator 2 view .LVU634
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1684              		.loc 1 842 3 discriminator 2 view .LVU635
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1685              		.loc 1 842 34 is_stmt 0 discriminator 2 view .LVU636
+ 1686 0010 93F82500 		ldrb	r0, [r3, #37]	@ zero_extendqisi2
+ 1687 0014 C0B2     		uxtb	r0, r0
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1688              		.loc 1 842 6 discriminator 2 view .LVU637
+ 1689 0016 0128     		cmp	r0, #1
+ 1690 0018 04D0     		beq	.L107
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1691              		.loc 1 869 12 view .LVU638
+ 1692 001a 0120     		movs	r0, #1
+ 1693              	.L98:
+ 1694              	.LVL92:
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1695              		.loc 1 873 3 is_stmt 1 view .LVU639
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1696              		.loc 1 873 3 view .LVU640
+ 1697 001c 0022     		movs	r2, #0
+ 1698              	.LVL93:
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1699              		.loc 1 873 3 is_stmt 0 view .LVU641
+ 1700 001e 83F82420 		strb	r2, [r3, #36]
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1701              		.loc 1 873 3 is_stmt 1 view .LVU642
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 1702              		.loc 1 875 3 view .LVU643
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 1703              		.loc 1 875 10 is_stmt 0 view .LVU644
+ 1704 0022 7047     		bx	lr
+ 1705              	.LVL94:
+ 1706              	.L107:
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1707              		.loc 1 844 5 is_stmt 1 view .LVU645
+ 1708 0024 0329     		cmp	r1, #3
+ 1709 0026 F9D8     		bhi	.L98
+ 1710 0028 DFE801F0 		tbb	[pc, r1]
+ 1711              	.L100:
+ 1712 002c 02       		.byte	(.L103-.L100)/2
+ 1713 002d 05       		.byte	(.L102-.L100)/2
+ 1714 002e 08       		.byte	(.L101-.L100)/2
+ 1715 002f 0B       		.byte	(.L99-.L100)/2
+ 1716              		.p2align 1
+ARM GAS  /tmp/ccCGP7ew.s 			page 60
+
+
+ 1717              	.L103:
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1718              		.loc 1 847 9 view .LVU646
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1719              		.loc 1 847 32 is_stmt 0 view .LVU647
+ 1720 0030 DA62     		str	r2, [r3, #44]
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1721              		.loc 1 848 9 is_stmt 1 view .LVU648
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1722              		.loc 1 837 21 is_stmt 0 view .LVU649
+ 1723 0032 0846     		mov	r0, r1
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1724              		.loc 1 848 9 view .LVU650
+ 1725 0034 F2E7     		b	.L98
+ 1726              	.L102:
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1727              		.loc 1 851 9 is_stmt 1 view .LVU651
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1728              		.loc 1 851 36 is_stmt 0 view .LVU652
+ 1729 0036 1A63     		str	r2, [r3, #48]
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1730              		.loc 1 852 9 is_stmt 1 view .LVU653
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1731              		.loc 1 837 21 is_stmt 0 view .LVU654
+ 1732 0038 0020     		movs	r0, #0
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1733              		.loc 1 852 9 view .LVU655
+ 1734 003a EFE7     		b	.L98
+ 1735              	.L101:
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1736              		.loc 1 855 9 is_stmt 1 view .LVU656
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1737              		.loc 1 855 33 is_stmt 0 view .LVU657
+ 1738 003c 5A63     		str	r2, [r3, #52]
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1739              		.loc 1 856 9 is_stmt 1 view .LVU658
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1740              		.loc 1 837 21 is_stmt 0 view .LVU659
+ 1741 003e 0020     		movs	r0, #0
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1742              		.loc 1 856 9 view .LVU660
+ 1743 0040 ECE7     		b	.L98
+ 1744              	.L99:
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1745              		.loc 1 859 9 is_stmt 1 view .LVU661
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1746              		.loc 1 859 33 is_stmt 0 view .LVU662
+ 1747 0042 9A63     		str	r2, [r3, #56]
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1748              		.loc 1 860 9 is_stmt 1 view .LVU663
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1749              		.loc 1 837 21 is_stmt 0 view .LVU664
+ 1750 0044 0020     		movs	r0, #0
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1751              		.loc 1 860 9 view .LVU665
+ 1752 0046 E9E7     		b	.L98
+ 1753              	.L104:
+ARM GAS  /tmp/ccCGP7ew.s 			page 61
+
+
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1754              		.loc 1 840 3 view .LVU666
+ 1755 0048 0220     		movs	r0, #2
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1756              		.loc 1 876 1 view .LVU667
+ 1757 004a 7047     		bx	lr
+ 1758              		.cfi_endproc
+ 1759              	.LFE337:
+ 1761              		.section	.text.HAL_DMA_UnRegisterCallback,"ax",%progbits
+ 1762              		.align	1
+ 1763              		.global	HAL_DMA_UnRegisterCallback
+ 1764              		.syntax unified
+ 1765              		.thumb
+ 1766              		.thumb_func
+ 1768              	HAL_DMA_UnRegisterCallback:
+ 1769              	.LVL95:
+ 1770              	.LFB338:
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1771              		.loc 1 887 1 is_stmt 1 view -0
+ 1772              		.cfi_startproc
+ 1773              		@ args = 0, pretend = 0, frame = 0
+ 1774              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1775              		@ link register save eliminated.
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1776              		.loc 1 887 1 is_stmt 0 view .LVU669
+ 1777 0000 0346     		mov	r3, r0
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1778              		.loc 1 888 3 is_stmt 1 view .LVU670
+ 1779              	.LVL96:
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1780              		.loc 1 891 3 view .LVU671
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1781              		.loc 1 891 3 view .LVU672
+ 1782 0002 90F82420 		ldrb	r2, [r0, #36]	@ zero_extendqisi2
+ 1783 0006 012A     		cmp	r2, #1
+ 1784 0008 26D0     		beq	.L117
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1785              		.loc 1 891 3 discriminator 2 view .LVU673
+ 1786 000a 0122     		movs	r2, #1
+ 1787 000c 80F82420 		strb	r2, [r0, #36]
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1788              		.loc 1 891 3 discriminator 2 view .LVU674
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1789              		.loc 1 893 3 discriminator 2 view .LVU675
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1790              		.loc 1 893 34 is_stmt 0 discriminator 2 view .LVU676
+ 1791 0010 90F82500 		ldrb	r0, [r0, #37]	@ zero_extendqisi2
+ 1792              	.LVL97:
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1793              		.loc 1 893 34 discriminator 2 view .LVU677
+ 1794 0014 C0B2     		uxtb	r0, r0
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   {
+ 1795              		.loc 1 893 6 discriminator 2 view .LVU678
+ 1796 0016 9042     		cmp	r0, r2
+ 1797 0018 04D0     		beq	.L120
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   }
+ 1798              		.loc 1 927 12 view .LVU679
+ARM GAS  /tmp/ccCGP7ew.s 			page 62
+
+
+ 1799 001a 0120     		movs	r0, #1
+ 1800              	.L110:
+ 1801              	.LVL98:
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1802              		.loc 1 931 3 is_stmt 1 view .LVU680
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1803              		.loc 1 931 3 view .LVU681
+ 1804 001c 0022     		movs	r2, #0
+ 1805 001e 83F82420 		strb	r2, [r3, #36]
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1806              		.loc 1 931 3 view .LVU682
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 1807              		.loc 1 933 3 view .LVU683
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 1808              		.loc 1 933 10 is_stmt 0 view .LVU684
+ 1809 0022 7047     		bx	lr
+ 1810              	.LVL99:
+ 1811              	.L120:
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****     {
+ 1812              		.loc 1 895 5 is_stmt 1 view .LVU685
+ 1813 0024 0429     		cmp	r1, #4
+ 1814 0026 F9D8     		bhi	.L110
+ 1815 0028 DFE801F0 		tbb	[pc, r1]
+ 1816              	.L112:
+ 1817 002c 03       		.byte	(.L116-.L112)/2
+ 1818 002d 07       		.byte	(.L115-.L112)/2
+ 1819 002e 0A       		.byte	(.L114-.L112)/2
+ 1820 002f 0D       		.byte	(.L113-.L112)/2
+ 1821 0030 10       		.byte	(.L111-.L112)/2
+ 1822 0031 00       		.p2align 1
+ 1823              	.L116:
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1824              		.loc 1 898 9 view .LVU686
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1825              		.loc 1 898 32 is_stmt 0 view .LVU687
+ 1826 0032 0022     		movs	r2, #0
+ 1827 0034 DA62     		str	r2, [r3, #44]
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1828              		.loc 1 899 9 is_stmt 1 view .LVU688
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1829              		.loc 1 888 21 is_stmt 0 view .LVU689
+ 1830 0036 0846     		mov	r0, r1
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1831              		.loc 1 899 9 view .LVU690
+ 1832 0038 F0E7     		b	.L110
+ 1833              	.L115:
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1834              		.loc 1 902 9 is_stmt 1 view .LVU691
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1835              		.loc 1 902 36 is_stmt 0 view .LVU692
+ 1836 003a 0020     		movs	r0, #0
+ 1837 003c 1863     		str	r0, [r3, #48]
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1838              		.loc 1 903 9 is_stmt 1 view .LVU693
+ 1839 003e EDE7     		b	.L110
+ 1840              	.L114:
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ARM GAS  /tmp/ccCGP7ew.s 			page 63
+
+
+ 1841              		.loc 1 906 9 view .LVU694
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1842              		.loc 1 906 33 is_stmt 0 view .LVU695
+ 1843 0040 0020     		movs	r0, #0
+ 1844 0042 5863     		str	r0, [r3, #52]
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1845              		.loc 1 907 9 is_stmt 1 view .LVU696
+ 1846 0044 EAE7     		b	.L110
+ 1847              	.L113:
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1848              		.loc 1 910 9 view .LVU697
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1849              		.loc 1 910 33 is_stmt 0 view .LVU698
+ 1850 0046 0020     		movs	r0, #0
+ 1851 0048 9863     		str	r0, [r3, #56]
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1852              		.loc 1 911 9 is_stmt 1 view .LVU699
+ 1853 004a E7E7     		b	.L110
+ 1854              	.L111:
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferHalfCpltCallback = NULL;
+ 1855              		.loc 1 914 9 view .LVU700
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferHalfCpltCallback = NULL;
+ 1856              		.loc 1 914 32 is_stmt 0 view .LVU701
+ 1857 004c 0020     		movs	r0, #0
+ 1858 004e D862     		str	r0, [r3, #44]
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferErrorCallback = NULL;
+ 1859              		.loc 1 915 9 is_stmt 1 view .LVU702
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferErrorCallback = NULL;
+ 1860              		.loc 1 915 36 is_stmt 0 view .LVU703
+ 1861 0050 1863     		str	r0, [r3, #48]
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferAbortCallback = NULL;
+ 1862              		.loc 1 916 9 is_stmt 1 view .LVU704
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         hdma->XferAbortCallback = NULL;
+ 1863              		.loc 1 916 33 is_stmt 0 view .LVU705
+ 1864 0052 5863     		str	r0, [r3, #52]
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1865              		.loc 1 917 9 is_stmt 1 view .LVU706
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****         break;
+ 1866              		.loc 1 917 33 is_stmt 0 view .LVU707
+ 1867 0054 9863     		str	r0, [r3, #56]
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1868              		.loc 1 918 9 is_stmt 1 view .LVU708
+ 1869 0056 E1E7     		b	.L110
+ 1870              	.LVL100:
+ 1871              	.L117:
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1872              		.loc 1 891 3 is_stmt 0 view .LVU709
+ 1873 0058 0220     		movs	r0, #2
+ 1874              	.LVL101:
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1875              		.loc 1 934 1 view .LVU710
+ 1876 005a 7047     		bx	lr
+ 1877              		.cfi_endproc
+ 1878              	.LFE338:
+ 1880              		.section	.text.HAL_DMA_GetState,"ax",%progbits
+ 1881              		.align	1
+ 1882              		.global	HAL_DMA_GetState
+ARM GAS  /tmp/ccCGP7ew.s 			page 64
+
+
+ 1883              		.syntax unified
+ 1884              		.thumb
+ 1885              		.thumb_func
+ 1887              	HAL_DMA_GetState:
+ 1888              	.LVL102:
+ 1889              	.LFB339:
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   /* Return DMA handle state */
+ 1890              		.loc 1 965 1 is_stmt 1 view -0
+ 1891              		.cfi_startproc
+ 1892              		@ args = 0, pretend = 0, frame = 0
+ 1893              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1894              		@ link register save eliminated.
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 1895              		.loc 1 967 3 view .LVU712
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 1896              		.loc 1 967 14 is_stmt 0 view .LVU713
+ 1897 0000 90F82500 		ldrb	r0, [r0, #37]	@ zero_extendqisi2
+ 1898              	.LVL103:
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1899              		.loc 1 968 1 view .LVU714
+ 1900 0004 7047     		bx	lr
+ 1901              		.cfi_endproc
+ 1902              	.LFE339:
+ 1904              		.section	.text.HAL_DMA_GetError,"ax",%progbits
+ 1905              		.align	1
+ 1906              		.global	HAL_DMA_GetError
+ 1907              		.syntax unified
+ 1908              		.thumb
+ 1909              		.thumb_func
+ 1911              	HAL_DMA_GetError:
+ 1912              	.LVL104:
+ 1913              	.LFB340:
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ****   return hdma->ErrorCode;
+ 1914              		.loc 1 977 1 is_stmt 1 view -0
+ 1915              		.cfi_startproc
+ 1916              		@ args = 0, pretend = 0, frame = 0
+ 1917              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1918              		@ link register save eliminated.
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 1919              		.loc 1 978 3 view .LVU716
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** }
+ 1920              		.loc 1 978 14 is_stmt 0 view .LVU717
+ 1921 0000 C06B     		ldr	r0, [r0, #60]
+ 1922              	.LVL105:
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c **** 
+ 1923              		.loc 1 979 1 view .LVU718
+ 1924 0002 7047     		bx	lr
+ 1925              		.cfi_endproc
+ 1926              	.LFE340:
+ 1928              		.text
+ 1929              	.Letext0:
+ 1930              		.file 2 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 1931              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 1932              		.file 4 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 1933              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 1934              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ARM GAS  /tmp/ccCGP7ew.s 			page 65
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_dma.c
+     /tmp/ccCGP7ew.s:21     .text.DMA_SetConfig:00000000 $t
+     /tmp/ccCGP7ew.s:26     .text.DMA_SetConfig:00000000 DMA_SetConfig
+     /tmp/ccCGP7ew.s:121    .text.DMA_CalcDMAMUXChannelBaseAndMask:00000000 $t
+     /tmp/ccCGP7ew.s:126    .text.DMA_CalcDMAMUXChannelBaseAndMask:00000000 DMA_CalcDMAMUXChannelBaseAndMask
+     /tmp/ccCGP7ew.s:190    .text.DMA_CalcDMAMUXChannelBaseAndMask:00000034 $d
+     /tmp/ccCGP7ew.s:199    .text.DMA_CalcDMAMUXRequestGenBaseAndMask:00000000 $t
+     /tmp/ccCGP7ew.s:204    .text.DMA_CalcDMAMUXRequestGenBaseAndMask:00000000 DMA_CalcDMAMUXRequestGenBaseAndMask
+     /tmp/ccCGP7ew.s:244    .text.DMA_CalcDMAMUXRequestGenBaseAndMask:00000020 $d
+     /tmp/ccCGP7ew.s:250    .text.HAL_DMA_Init:00000000 $t
+     /tmp/ccCGP7ew.s:256    .text.HAL_DMA_Init:00000000 HAL_DMA_Init
+     /tmp/ccCGP7ew.s:474    .text.HAL_DMA_Init:000000c0 $d
+     /tmp/ccCGP7ew.s:484    .text.HAL_DMA_DeInit:00000000 $t
+     /tmp/ccCGP7ew.s:490    .text.HAL_DMA_DeInit:00000000 HAL_DMA_DeInit
+     /tmp/ccCGP7ew.s:672    .text.HAL_DMA_DeInit:000000a0 $d
+     /tmp/ccCGP7ew.s:682    .text.HAL_DMA_Start:00000000 $t
+     /tmp/ccCGP7ew.s:688    .text.HAL_DMA_Start:00000000 HAL_DMA_Start
+     /tmp/ccCGP7ew.s:776    .text.HAL_DMA_Start_IT:00000000 $t
+     /tmp/ccCGP7ew.s:782    .text.HAL_DMA_Start_IT:00000000 HAL_DMA_Start_IT
+     /tmp/ccCGP7ew.s:920    .text.HAL_DMA_Abort:00000000 $t
+     /tmp/ccCGP7ew.s:926    .text.HAL_DMA_Abort:00000000 HAL_DMA_Abort
+     /tmp/ccCGP7ew.s:1035   .text.HAL_DMA_Abort_IT:00000000 $t
+     /tmp/ccCGP7ew.s:1041   .text.HAL_DMA_Abort_IT:00000000 HAL_DMA_Abort_IT
+     /tmp/ccCGP7ew.s:1174   .text.HAL_DMA_PollForTransfer:00000000 $t
+     /tmp/ccCGP7ew.s:1180   .text.HAL_DMA_PollForTransfer:00000000 HAL_DMA_PollForTransfer
+     /tmp/ccCGP7ew.s:1461   .text.HAL_DMA_IRQHandler:00000000 $t
+     /tmp/ccCGP7ew.s:1467   .text.HAL_DMA_IRQHandler:00000000 HAL_DMA_IRQHandler
+     /tmp/ccCGP7ew.s:1655   .text.HAL_DMA_RegisterCallback:00000000 $t
+     /tmp/ccCGP7ew.s:1661   .text.HAL_DMA_RegisterCallback:00000000 HAL_DMA_RegisterCallback
+     /tmp/ccCGP7ew.s:1712   .text.HAL_DMA_RegisterCallback:0000002c $d
+     /tmp/ccCGP7ew.s:1716   .text.HAL_DMA_RegisterCallback:00000030 $t
+     /tmp/ccCGP7ew.s:1762   .text.HAL_DMA_UnRegisterCallback:00000000 $t
+     /tmp/ccCGP7ew.s:1768   .text.HAL_DMA_UnRegisterCallback:00000000 HAL_DMA_UnRegisterCallback
+     /tmp/ccCGP7ew.s:1817   .text.HAL_DMA_UnRegisterCallback:0000002c $d
+     /tmp/ccCGP7ew.s:1881   .text.HAL_DMA_GetState:00000000 $t
+     /tmp/ccCGP7ew.s:1887   .text.HAL_DMA_GetState:00000000 HAL_DMA_GetState
+     /tmp/ccCGP7ew.s:1905   .text.HAL_DMA_GetError:00000000 $t
+     /tmp/ccCGP7ew.s:1911   .text.HAL_DMA_GetError:00000000 HAL_DMA_GetError
+     /tmp/ccCGP7ew.s:1822   .text.HAL_DMA_UnRegisterCallback:00000031 $d
+     /tmp/ccCGP7ew.s:1822   .text.HAL_DMA_UnRegisterCallback:00000032 $t
+
+UNDEFINED SYMBOLS
+HAL_GetTick
diff --git a/squeow_sw/build/stm32g4xx_hal_dma.o b/squeow_sw/build/stm32g4xx_hal_dma.o
new file mode 100644
index 0000000000000000000000000000000000000000..860faa43332b0493d40835b39b751863cc96479c
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diff --git a/squeow_sw/build/stm32g4xx_hal_dma_ex.d b/squeow_sw/build/stm32g4xx_hal_dma_ex.d
new file mode 100644
index 0000000..e1efffc
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_dma_ex.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_dma_ex.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_dma_ex.lst b/squeow_sw/build/stm32g4xx_hal_dma_ex.lst
new file mode 100644
index 0000000..4ce96e8
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_dma_ex.lst
@@ -0,0 +1,1981 @@
+ARM GAS  /tmp/ccF4OHvs.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_dma_ex.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c"
+  20              		.section	.text.HAL_DMAEx_ConfigMuxSync,"ax",%progbits
+  21              		.align	1
+  22              		.global	HAL_DMAEx_ConfigMuxSync
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	HAL_DMAEx_ConfigMuxSync:
+  28              	.LVL0:
+  29              	.LFB329:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @file    stm32g4xx_hal_dma_ex.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @brief   DMA Extension HAL module driver
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *         This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *         functionalities of the DMA Extension peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *           + Extended features functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   ******************************************************************************
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @attention
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * Copyright (c) 2019 STMicroelectronics.
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * All rights reserved.
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * in the root directory of this software component.
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   ******************************************************************************
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   @verbatim
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   ==============================================================================
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****                         ##### How to use this driver #####
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   ==============================================================================
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   [..]
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   The DMA Extension HAL driver can be used as follows:
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****    (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****    (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator func
+ARM GAS  /tmp/ccF4OHvs.s 			page 2
+
+
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****        Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can t
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****        to respectively enable/disable the request generator.
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****    (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called fro
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****        the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****        As only one interrupt line is available for all DMAMUX channels and request generators , HAL
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****        called with, as parameter, the appropriate DMA handle as many as used DMAs in the user proje
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****       (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   @endverbatim
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /* Includes ------------------------------------------------------------------*/
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** #include "stm32g4xx_hal.h"
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @{
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /** @defgroup DMAEx DMAEx
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @brief DMA Extended HAL module driver
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @{
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** #ifdef HAL_DMA_MODULE_ENABLED
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /* Private typedef -----------------------------------------------------------*/
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /* Private define ------------------------------------------------------------*/
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /* Private macro -------------------------------------------------------------*/
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /* Private variables ---------------------------------------------------------*/
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /* Private Constants ---------------------------------------------------------*/
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /* Private function prototypes -----------------------------------------------*/
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /* Private functions ---------------------------------------------------------*/
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @{
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *  @brief   Extended features functions
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** @verbatim
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****  ===============================================================================
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****                 #####  Extended features functions  #####
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****  ===============================================================================
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     [..]  This section provides functions allowing to:
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator func
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****        Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can t
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****        to respectively enable/disable the request generator.
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** @endverbatim
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @{
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ARM GAS  /tmp/ccF4OHvs.s 			page 3
+
+
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /**
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @brief  Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *                     the configuration information for the specified DMA channel.
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @param  pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchroniza
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @retval HAL status
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pS
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** {
+  30              		.loc 1 96 1 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		@ link register save eliminated.
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   /* Check the parameters */
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  35              		.loc 1 98 3 view .LVU1
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+  36              		.loc 1 100 3 view .LVU2
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
+  37              		.loc 1 102 3 view .LVU3
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
+  38              		.loc 1 103 3 view .LVU4
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
+  39              		.loc 1 104 3 view .LVU5
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
+  40              		.loc 1 105 3 view .LVU6
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   /*Check if the DMA state is ready */
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   if (hdma->State == HAL_DMA_STATE_READY)
+  41              		.loc 1 108 3 view .LVU7
+  42              		.loc 1 108 11 is_stmt 0 view .LVU8
+  43 0000 90F82530 		ldrb	r3, [r0, #37]	@ zero_extendqisi2
+  44 0004 DBB2     		uxtb	r3, r3
+  45              		.loc 1 108 6 view .LVU9
+  46 0006 012B     		cmp	r3, #1
+  47 0008 21D1     		bne	.L3
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   {
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /* Process Locked */
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     __HAL_LOCK(hdma);
+  48              		.loc 1 111 5 is_stmt 1 view .LVU10
+  49              		.loc 1 111 5 view .LVU11
+  50 000a 90F82430 		ldrb	r3, [r0, #36]	@ zero_extendqisi2
+  51 000e 012B     		cmp	r3, #1
+  52 0010 1FD0     		beq	.L4
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   /* Check the parameters */
+  53              		.loc 1 96 1 is_stmt 0 discriminator 2 view .LVU12
+  54 0012 30B4     		push	{r4, r5}
+  55              	.LCFI0:
+  56              		.cfi_def_cfa_offset 8
+  57              		.cfi_offset 4, -8
+  58              		.cfi_offset 5, -4
+  59              		.loc 1 111 5 is_stmt 1 discriminator 2 view .LVU13
+  60 0014 0123     		movs	r3, #1
+ARM GAS  /tmp/ccF4OHvs.s 			page 4
+
+
+  61 0016 80F82430 		strb	r3, [r0, #36]
+  62              		.loc 1 111 5 discriminator 2 view .LVU14
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     MODIFY_REG(hdma->DMAmuxChannel->CCR, \
+  63              		.loc 1 114 5 discriminator 2 view .LVU15
+  64 001a 846C     		ldr	r4, [r0, #72]
+  65 001c 2268     		ldr	r2, [r4]
+  66 001e D2B2     		uxtb	r2, r2
+  67 0020 CB68     		ldr	r3, [r1, #12]
+  68 0022 013B     		subs	r3, r3, #1
+  69 0024 DB04     		lsls	r3, r3, #19
+  70 0026 0D68     		ldr	r5, [r1]
+  71 0028 43EA0563 		orr	r3, r3, r5, lsl #24
+  72 002c 4D68     		ldr	r5, [r1, #4]
+  73 002e 2B43     		orrs	r3, r3, r5
+  74 0030 91F808C0 		ldrb	ip, [r1, #8]	@ zero_extendqisi2
+  75 0034 43EA0C43 		orr	r3, r3, ip, lsl #16
+  76 0038 497A     		ldrb	r1, [r1, #9]	@ zero_extendqisi2
+  77              	.LVL1:
+  78              		.loc 1 114 5 is_stmt 0 discriminator 2 view .LVU16
+  79 003a 43EA4123 		orr	r3, r3, r1, lsl #9
+  80 003e 1343     		orrs	r3, r3, r2
+  81 0040 2360     		str	r3, [r4]
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****                (~DMAMUX_CxCR_DMAREQ_ID), \
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****                ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNum
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****                pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****                ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /* Process UnLocked */
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     __HAL_UNLOCK(hdma);
+  82              		.loc 1 121 5 is_stmt 1 discriminator 2 view .LVU17
+  83              		.loc 1 121 5 discriminator 2 view .LVU18
+  84 0042 0023     		movs	r3, #0
+  85 0044 80F82430 		strb	r3, [r0, #36]
+  86              		.loc 1 121 5 discriminator 2 view .LVU19
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     return HAL_OK;
+  87              		.loc 1 123 5 discriminator 2 view .LVU20
+  88              		.loc 1 123 12 is_stmt 0 discriminator 2 view .LVU21
+  89 0048 1846     		mov	r0, r3
+  90              	.LVL2:
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   else
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   {
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /*DMA State not Ready*/
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     return HAL_ERROR;
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** }
+  91              		.loc 1 130 1 discriminator 2 view .LVU22
+  92 004a 30BC     		pop	{r4, r5}
+  93              	.LCFI1:
+  94              		.cfi_restore 5
+  95              		.cfi_restore 4
+  96              		.cfi_def_cfa_offset 0
+  97 004c 7047     		bx	lr
+  98              	.LVL3:
+ARM GAS  /tmp/ccF4OHvs.s 			page 5
+
+
+  99              	.L3:
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 100              		.loc 1 128 12 view .LVU23
+ 101 004e 0120     		movs	r0, #1
+ 102              	.LVL4:
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 103              		.loc 1 128 12 view .LVU24
+ 104 0050 7047     		bx	lr
+ 105              	.LVL5:
+ 106              	.L4:
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 107              		.loc 1 111 5 view .LVU25
+ 108 0052 0220     		movs	r0, #2
+ 109              	.LVL6:
+ 110              		.loc 1 130 1 view .LVU26
+ 111 0054 7047     		bx	lr
+ 112              		.cfi_endproc
+ 113              	.LFE329:
+ 115              		.section	.text.HAL_DMAEx_ConfigMuxRequestGenerator,"ax",%progbits
+ 116              		.align	1
+ 117              		.global	HAL_DMAEx_ConfigMuxRequestGenerator
+ 118              		.syntax unified
+ 119              		.thumb
+ 120              		.thumb_func
+ 122              	HAL_DMAEx_ConfigMuxRequestGenerator:
+ 123              	.LVL7:
+ 124              	.LFB330:
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /**
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @brief  Configure the DMAMUX request generator block used by the given DMA channel (instance).
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *                     the configuration information for the specified DMA channel.
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @param  pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *         contains the request generator parameters.
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @retval HAL status
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****                                                       HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRe
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** {
+ 125              		.loc 1 143 1 is_stmt 1 view -0
+ 126              		.cfi_startproc
+ 127              		@ args = 0, pretend = 0, frame = 0
+ 128              		@ frame_needed = 0, uses_anonymous_args = 0
+ 129              		@ link register save eliminated.
+ 130              		.loc 1 143 1 is_stmt 0 view .LVU28
+ 131 0000 0246     		mov	r2, r0
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   /* Check the parameters */
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ 132              		.loc 1 145 3 is_stmt 1 view .LVU29
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+ 133              		.loc 1 147 3 view .LVU30
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
+ 134              		.loc 1 149 3 view .LVU31
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
+ARM GAS  /tmp/ccF4OHvs.s 			page 6
+
+
+ 135              		.loc 1 150 3 view .LVU32
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   /* check if the DMA state is ready
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****      and DMA is using a DMAMUX request generator block
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
+ 136              		.loc 1 155 3 view .LVU33
+ 137              		.loc 1 155 12 is_stmt 0 view .LVU34
+ 138 0002 90F82530 		ldrb	r3, [r0, #37]	@ zero_extendqisi2
+ 139 0006 D8B2     		uxtb	r0, r3
+ 140              	.LVL8:
+ 141              		.loc 1 155 6 view .LVU35
+ 142 0008 0128     		cmp	r0, #1
+ 143 000a 24D1     		bne	.L12
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   /* Check the parameters */
+ 144              		.loc 1 143 1 discriminator 1 view .LVU36
+ 145 000c 10B4     		push	{r4}
+ 146              	.LCFI2:
+ 147              		.cfi_def_cfa_offset 4
+ 148              		.cfi_offset 4, -4
+ 149              		.loc 1 155 52 discriminator 1 view .LVU37
+ 150 000e 546D     		ldr	r4, [r2, #84]
+ 151              		.loc 1 155 44 discriminator 1 view .LVU38
+ 152 0010 E4B1     		cbz	r4, .L10
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   {
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /* Process Locked */
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     __HAL_LOCK(hdma);
+ 153              		.loc 1 158 5 is_stmt 1 view .LVU39
+ 154              		.loc 1 158 5 view .LVU40
+ 155 0012 92F82430 		ldrb	r3, [r2, #36]	@ zero_extendqisi2
+ 156 0016 012B     		cmp	r3, #1
+ 157 0018 1FD0     		beq	.L13
+ 158              		.loc 1 158 5 discriminator 2 view .LVU41
+ 159 001a 0123     		movs	r3, #1
+ 160 001c 82F82430 		strb	r3, [r2, #36]
+ 161              		.loc 1 158 5 discriminator 2 view .LVU42
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /* Set the request generator new parameters */
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
+ 162              		.loc 1 161 5 discriminator 2 view .LVU43
+ 163              		.loc 1 161 59 is_stmt 0 discriminator 2 view .LVU44
+ 164 0020 0868     		ldr	r0, [r1]
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****                                    ((pRequestGeneratorConfig->RequestNumber - 1U) << (POSITION_VAL(
+ 165              		.loc 1 162 61 discriminator 2 view .LVU45
+ 166 0022 8B68     		ldr	r3, [r1, #8]
+ 167              		.loc 1 162 77 discriminator 2 view .LVU46
+ 168 0024 03F1FF3C 		add	ip, r3, #-1
+ 169              	.LVL9:
+ 170              	.LBB6:
+ 171              	.LBI6:
+ 172              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.2.0
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     08. May 2019
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+ARM GAS  /tmp/ccF4OHvs.s 			page 7
+
+
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccF4OHvs.s 			page 8
+
+
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
+ARM GAS  /tmp/ccF4OHvs.s 			page 9
+
+
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
+ARM GAS  /tmp/ccF4OHvs.s 			page 10
+
+
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccF4OHvs.s 			page 11
+
+
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ARM GAS  /tmp/ccF4OHvs.s 			page 12
+
+
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccF4OHvs.s 			page 13
+
+
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/ccF4OHvs.s 			page 14
+
+
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ARM GAS  /tmp/ccF4OHvs.s 			page 15
+
+
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ARM GAS  /tmp/ccF4OHvs.s 			page 16
+
+
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccF4OHvs.s 			page 17
+
+
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ARM GAS  /tmp/ccF4OHvs.s 			page 18
+
+
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccF4OHvs.s 			page 19
+
+
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccF4OHvs.s 			page 20
+
+
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ARM GAS  /tmp/ccF4OHvs.s 			page 21
+
+
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ARM GAS  /tmp/ccF4OHvs.s 			page 22
+
+
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 882:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 883:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 885:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 888:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 900:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 901:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 902:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 904:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 906:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 908:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 913:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 915:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 916:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 918:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccF4OHvs.s 			page 23
+
+
+ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 922:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 923:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 925:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 928:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 930:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 931:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 932:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 938:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 940:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 942:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 943:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+ 945:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 946:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 947:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 948:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 949:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 950:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ 952:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 953:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 954:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
+ 956:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 958:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 959:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 960:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 961:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 962:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
+ 963:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
+ 964:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 965:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 966:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 967:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+ 968:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 969:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ 970:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_bswap32(value);
+ 971:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 972:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 974:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 975:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ARM GAS  /tmp/ccF4OHvs.s 			page 24
+
+
+ 976:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 977:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 978:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 979:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 980:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 982:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 984:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 985:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 986:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+ 987:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 989:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 990:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 991:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 992:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 993:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 994:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 995:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 996:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 997:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
+ 998:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 999:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+1000:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1001:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+1002:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1003:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1004:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
+1005:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1006:Drivers/CMSIS/Include/cmsis_gcc.h ****   int16_t result;
+1007:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1008:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+1009:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+1010:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1011:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1014:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1015:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
+1016:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
+1017:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
+1018:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
+1019:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Rotated value
+1020:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1021:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+1022:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1023:Drivers/CMSIS/Include/cmsis_gcc.h ****   op2 %= 32U;
+1024:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (op2 == 0U)
+1025:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1026:Drivers/CMSIS/Include/cmsis_gcc.h ****     return op1;
+1027:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1028:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
+1029:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1030:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1031:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1032:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/ccF4OHvs.s 			page 25
+
+
+1033:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Breakpoint
+1034:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
+1035:Drivers/CMSIS/Include/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
+1036:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
+1037:Drivers/CMSIS/Include/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
+1038:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1039:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+1040:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1041:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1042:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1043:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse bit order of value
+1044:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
+1045:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+1046:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+1047:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+ 173              		.loc 2 1048 31 is_stmt 1 discriminator 2 view .LVU47
+ 174              	.LBB7:
+1049:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1050:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 175              		.loc 2 1050 3 discriminator 2 view .LVU48
+1051:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+1053:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+1054:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+1055:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 176              		.loc 2 1055 4 discriminator 2 view .LVU49
+ 177 0028 4FF47803 		mov	r3, #16252928
+ 178              		.syntax unified
+ 179              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 180 002c 93FAA3F3 		rbit r3, r3
+ 181              	@ 0 "" 2
+ 182              	.LVL10:
+1056:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1057:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+1058:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1059:Drivers/CMSIS/Include/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
+1060:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
+1061:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1062:Drivers/CMSIS/Include/cmsis_gcc.h ****     result <<= 1U;
+1063:Drivers/CMSIS/Include/cmsis_gcc.h ****     result |= value & 1U;
+1064:Drivers/CMSIS/Include/cmsis_gcc.h ****     s--;
+1065:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1066:Drivers/CMSIS/Include/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
+1067:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1068:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 183              		.loc 2 1068 3 discriminator 2 view .LVU50
+ 184              		.loc 2 1068 3 is_stmt 0 discriminator 2 view .LVU51
+ 185              		.thumb
+ 186              		.syntax unified
+ 187              	.LBE7:
+ 188              	.LBE6:
+ 189              	.LBB8:
+ 190              	.LBI8:
+1069:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccF4OHvs.s 			page 26
+
+
+1072:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1073:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Count leading zeros
+1074:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
+1075:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
+1076:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             number of leading zeros in value
+1077:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+ 191              		.loc 2 1078 30 is_stmt 1 discriminator 2 view .LVU52
+ 192              	.LBB9:
+1079:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1080:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+1081:Drivers/CMSIS/Include/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
+1082:Drivers/CMSIS/Include/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
+1083:Drivers/CMSIS/Include/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
+1084:Drivers/CMSIS/Include/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
+1085:Drivers/CMSIS/Include/cmsis_gcc.h ****      is non-zero".
+1086:Drivers/CMSIS/Include/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+1087:Drivers/CMSIS/Include/cmsis_gcc.h ****      single CLZ instruction.
+1088:Drivers/CMSIS/Include/cmsis_gcc.h ****    */
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (value == 0U)
+ 193              		.loc 2 1089 3 discriminator 2 view .LVU53
+ 194              		.loc 2 1089 6 is_stmt 0 discriminator 2 view .LVU54
+ 195 0030 7BB1     		cbz	r3, .L14
+1090:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****     return 32U;
+1092:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1093:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_clz(value);
+ 196              		.loc 2 1093 3 is_stmt 1 view .LVU55
+ 197              		.loc 2 1093 10 is_stmt 0 view .LVU56
+ 198 0032 B3FA83F3 		clz	r3, r3
+ 199              	.LVL11:
+ 200              	.L11:
+ 201              		.loc 2 1093 10 view .LVU57
+ 202              	.LBE9:
+ 203              	.LBE8:
+ 204              		.loc 1 162 121 view .LVU58
+ 205 0036 03F01F03 		and	r3, r3, #31
+ 206              		.loc 1 162 83 view .LVU59
+ 207 003a 0CFA03F3 		lsl	r3, ip, r3
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****                                    ((pRequestGeneratorConfig->RequestNumber - 1U) << (POSITION_VAL(
+ 208              		.loc 1 161 70 view .LVU60
+ 209 003e 0343     		orrs	r3, r3, r0
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****                                    pRequestGeneratorConfig->Polarity;
+ 210              		.loc 1 163 59 view .LVU61
+ 211 0040 4968     		ldr	r1, [r1, #4]
+ 212              	.LVL12:
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****                                    pRequestGeneratorConfig->Polarity;
+ 213              		.loc 1 162 131 view .LVU62
+ 214 0042 0B43     		orrs	r3, r3, r1
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****                                    ((pRequestGeneratorConfig->RequestNumber - 1U) << (POSITION_VAL(
+ 215              		.loc 1 161 34 view .LVU63
+ 216 0044 2360     		str	r3, [r4]
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /* Process UnLocked */
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     __HAL_UNLOCK(hdma);
+ 217              		.loc 1 165 5 is_stmt 1 view .LVU64
+ 218              		.loc 1 165 5 view .LVU65
+ 219 0046 0020     		movs	r0, #0
+ARM GAS  /tmp/ccF4OHvs.s 			page 27
+
+
+ 220 0048 82F82400 		strb	r0, [r2, #36]
+ 221              		.loc 1 165 5 view .LVU66
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     return HAL_OK;
+ 222              		.loc 1 167 5 view .LVU67
+ 223              	.L10:
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   else
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   {
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     return HAL_ERROR;
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** }
+ 224              		.loc 1 173 1 is_stmt 0 view .LVU68
+ 225 004c 5DF8044B 		ldr	r4, [sp], #4
+ 226              	.LCFI3:
+ 227              		.cfi_remember_state
+ 228              		.cfi_restore 4
+ 229              		.cfi_def_cfa_offset 0
+ 230 0050 7047     		bx	lr
+ 231              	.LVL13:
+ 232              	.L14:
+ 233              	.LCFI4:
+ 234              		.cfi_restore_state
+ 235              	.LBB11:
+ 236              	.LBB10:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 237              		.loc 2 1091 12 view .LVU69
+ 238 0052 2023     		movs	r3, #32
+ 239              	.LVL14:
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 240              		.loc 2 1091 12 view .LVU70
+ 241 0054 EFE7     		b	.L11
+ 242              	.LVL15:
+ 243              	.L12:
+ 244              	.LCFI5:
+ 245              		.cfi_def_cfa_offset 0
+ 246              		.cfi_restore 4
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 247              		.loc 2 1091 12 view .LVU71
+ 248              	.LBE10:
+ 249              	.LBE11:
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 250              		.loc 1 171 12 view .LVU72
+ 251 0056 0120     		movs	r0, #1
+ 252              		.loc 1 173 1 view .LVU73
+ 253 0058 7047     		bx	lr
+ 254              	.L13:
+ 255              	.LCFI6:
+ 256              		.cfi_def_cfa_offset 4
+ 257              		.cfi_offset 4, -4
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 258              		.loc 1 158 5 view .LVU74
+ 259 005a 0220     		movs	r0, #2
+ 260 005c F6E7     		b	.L10
+ 261              		.cfi_endproc
+ 262              	.LFE330:
+ 264              		.section	.text.HAL_DMAEx_EnableMuxRequestGenerator,"ax",%progbits
+ARM GAS  /tmp/ccF4OHvs.s 			page 28
+
+
+ 265              		.align	1
+ 266              		.global	HAL_DMAEx_EnableMuxRequestGenerator
+ 267              		.syntax unified
+ 268              		.thumb
+ 269              		.thumb_func
+ 271              	HAL_DMAEx_EnableMuxRequestGenerator:
+ 272              	.LVL16:
+ 273              	.LFB331:
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /**
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @brief  Enable the DMAMUX request generator block used by the given DMA channel (instance).
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *                     the configuration information for the specified DMA channel.
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @retval HAL status
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** {
+ 274              		.loc 1 182 1 is_stmt 1 view -0
+ 275              		.cfi_startproc
+ 276              		@ args = 0, pretend = 0, frame = 0
+ 277              		@ frame_needed = 0, uses_anonymous_args = 0
+ 278              		@ link register save eliminated.
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   /* Check the parameters */
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ 279              		.loc 1 184 3 view .LVU76
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   /* check if the DMA state is ready
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****      and DMA is using a DMAMUX request generator block
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
+ 280              		.loc 1 189 3 view .LVU77
+ 281              		.loc 1 189 12 is_stmt 0 view .LVU78
+ 282 0000 90F82530 		ldrb	r3, [r0, #37]	@ zero_extendqisi2
+ 283              		.loc 1 189 6 view .LVU79
+ 284 0004 3BB1     		cbz	r3, .L21
+ 285              		.loc 1 189 52 discriminator 1 view .LVU80
+ 286 0006 436D     		ldr	r3, [r0, #84]
+ 287              		.loc 1 189 44 discriminator 1 view .LVU81
+ 288 0008 3BB1     		cbz	r3, .L22
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   {
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /* Enable the request generator*/
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
+ 289              		.loc 1 193 5 is_stmt 1 view .LVU82
+ 290              		.loc 1 193 27 is_stmt 0 view .LVU83
+ 291 000a 1A68     		ldr	r2, [r3]
+ 292              		.loc 1 193 34 view .LVU84
+ 293 000c 42F48032 		orr	r2, r2, #65536
+ 294 0010 1A60     		str	r2, [r3]
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     return HAL_OK;
+ 295              		.loc 1 195 5 is_stmt 1 view .LVU85
+ 296              		.loc 1 195 12 is_stmt 0 view .LVU86
+ 297 0012 0020     		movs	r0, #0
+ 298              	.LVL17:
+ 299              		.loc 1 195 12 view .LVU87
+ 300 0014 7047     		bx	lr
+ARM GAS  /tmp/ccF4OHvs.s 			page 29
+
+
+ 301              	.LVL18:
+ 302              	.L21:
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   else
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   {
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     return HAL_ERROR;
+ 303              		.loc 1 199 12 view .LVU88
+ 304 0016 0120     		movs	r0, #1
+ 305              	.LVL19:
+ 306              		.loc 1 199 12 view .LVU89
+ 307 0018 7047     		bx	lr
+ 308              	.LVL20:
+ 309              	.L22:
+ 310              		.loc 1 199 12 view .LVU90
+ 311 001a 0120     		movs	r0, #1
+ 312              	.LVL21:
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** }
+ 313              		.loc 1 201 1 view .LVU91
+ 314 001c 7047     		bx	lr
+ 315              		.cfi_endproc
+ 316              	.LFE331:
+ 318              		.section	.text.HAL_DMAEx_DisableMuxRequestGenerator,"ax",%progbits
+ 319              		.align	1
+ 320              		.global	HAL_DMAEx_DisableMuxRequestGenerator
+ 321              		.syntax unified
+ 322              		.thumb
+ 323              		.thumb_func
+ 325              	HAL_DMAEx_DisableMuxRequestGenerator:
+ 326              	.LVL22:
+ 327              	.LFB332:
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /**
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @brief  Disable the DMAMUX request generator block used by the given DMA channel (instance).
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *                     the configuration information for the specified DMA channel.
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @retval HAL status
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** {
+ 328              		.loc 1 210 1 is_stmt 1 view -0
+ 329              		.cfi_startproc
+ 330              		@ args = 0, pretend = 0, frame = 0
+ 331              		@ frame_needed = 0, uses_anonymous_args = 0
+ 332              		@ link register save eliminated.
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   /* Check the parameters */
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ 333              		.loc 1 212 3 view .LVU93
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   /* check if the DMA state is ready
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****      and DMA is using a DMAMUX request generator block
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
+ 334              		.loc 1 217 3 view .LVU94
+ 335              		.loc 1 217 12 is_stmt 0 view .LVU95
+ 336 0000 90F82530 		ldrb	r3, [r0, #37]	@ zero_extendqisi2
+ 337              		.loc 1 217 6 view .LVU96
+ARM GAS  /tmp/ccF4OHvs.s 			page 30
+
+
+ 338 0004 3BB1     		cbz	r3, .L25
+ 339              		.loc 1 217 52 discriminator 1 view .LVU97
+ 340 0006 436D     		ldr	r3, [r0, #84]
+ 341              		.loc 1 217 44 discriminator 1 view .LVU98
+ 342 0008 3BB1     		cbz	r3, .L26
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   {
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /* Disable the request generator*/
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
+ 343              		.loc 1 221 5 is_stmt 1 view .LVU99
+ 344              		.loc 1 221 27 is_stmt 0 view .LVU100
+ 345 000a 1A68     		ldr	r2, [r3]
+ 346              		.loc 1 221 34 view .LVU101
+ 347 000c 22F48032 		bic	r2, r2, #65536
+ 348 0010 1A60     		str	r2, [r3]
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     return HAL_OK;
+ 349              		.loc 1 223 5 is_stmt 1 view .LVU102
+ 350              		.loc 1 223 12 is_stmt 0 view .LVU103
+ 351 0012 0020     		movs	r0, #0
+ 352              	.LVL23:
+ 353              		.loc 1 223 12 view .LVU104
+ 354 0014 7047     		bx	lr
+ 355              	.LVL24:
+ 356              	.L25:
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   else
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   {
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     return HAL_ERROR;
+ 357              		.loc 1 227 12 view .LVU105
+ 358 0016 0120     		movs	r0, #1
+ 359              	.LVL25:
+ 360              		.loc 1 227 12 view .LVU106
+ 361 0018 7047     		bx	lr
+ 362              	.LVL26:
+ 363              	.L26:
+ 364              		.loc 1 227 12 view .LVU107
+ 365 001a 0120     		movs	r0, #1
+ 366              	.LVL27:
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** }
+ 367              		.loc 1 229 1 view .LVU108
+ 368 001c 7047     		bx	lr
+ 369              		.cfi_endproc
+ 370              	.LFE332:
+ 372              		.section	.text.HAL_DMAEx_MUX_IRQHandler,"ax",%progbits
+ 373              		.align	1
+ 374              		.global	HAL_DMAEx_MUX_IRQHandler
+ 375              		.syntax unified
+ 376              		.thumb
+ 377              		.thumb_func
+ 379              	HAL_DMAEx_MUX_IRQHandler:
+ 380              	.LVL28:
+ 381              	.LFB333:
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** /**
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @brief  Handles DMAMUX interrupt request.
+ARM GAS  /tmp/ccF4OHvs.s 			page 31
+
+
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   *               the configuration information for the specified DMA channel.
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   * @retval None
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   */
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** {
+ 382              		.loc 1 238 1 is_stmt 1 view -0
+ 383              		.cfi_startproc
+ 384              		@ args = 0, pretend = 0, frame = 0
+ 385              		@ frame_needed = 0, uses_anonymous_args = 0
+ 386              		.loc 1 238 1 is_stmt 0 view .LVU110
+ 387 0000 10B5     		push	{r4, lr}
+ 388              	.LCFI7:
+ 389              		.cfi_def_cfa_offset 8
+ 390              		.cfi_offset 4, -8
+ 391              		.cfi_offset 14, -4
+ 392 0002 0446     		mov	r4, r0
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   /* Check for DMAMUX Synchronization overrun */
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+ 393              		.loc 1 240 3 is_stmt 1 view .LVU111
+ 394              		.loc 1 240 12 is_stmt 0 view .LVU112
+ 395 0004 C36C     		ldr	r3, [r0, #76]
+ 396              		.loc 1 240 33 view .LVU113
+ 397 0006 1A68     		ldr	r2, [r3]
+ 398              		.loc 1 240 45 view .LVU114
+ 399 0008 036D     		ldr	r3, [r0, #80]
+ 400              		.loc 1 240 6 view .LVU115
+ 401 000a 1A42     		tst	r2, r3
+ 402 000c 0ED0     		beq	.L28
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   {
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /* Disable the synchro overrun interrupt */
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+ 403              		.loc 1 243 5 is_stmt 1 view .LVU116
+ 404              		.loc 1 243 9 is_stmt 0 view .LVU117
+ 405 000e 826C     		ldr	r2, [r0, #72]
+ 406              		.loc 1 243 24 view .LVU118
+ 407 0010 1368     		ldr	r3, [r2]
+ 408              		.loc 1 243 30 view .LVU119
+ 409 0012 23F48073 		bic	r3, r3, #256
+ 410 0016 1360     		str	r3, [r2]
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /* Clear the DMAMUX synchro overrun flag */
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 411              		.loc 1 246 5 is_stmt 1 view .LVU120
+ 412              		.loc 1 246 9 is_stmt 0 view .LVU121
+ 413 0018 C36C     		ldr	r3, [r0, #76]
+ 414              		.loc 1 246 42 view .LVU122
+ 415 001a 026D     		ldr	r2, [r0, #80]
+ 416              		.loc 1 246 36 view .LVU123
+ 417 001c 5A60     		str	r2, [r3, #4]
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /* Update error code */
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+ 418              		.loc 1 249 5 is_stmt 1 view .LVU124
+ 419              		.loc 1 249 9 is_stmt 0 view .LVU125
+ 420 001e C36B     		ldr	r3, [r0, #60]
+ 421              		.loc 1 249 21 view .LVU126
+ARM GAS  /tmp/ccF4OHvs.s 			page 32
+
+
+ 422 0020 43F40073 		orr	r3, r3, #512
+ 423 0024 C363     		str	r3, [r0, #60]
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     if (hdma->XferErrorCallback != NULL)
+ 424              		.loc 1 251 5 is_stmt 1 view .LVU127
+ 425              		.loc 1 251 13 is_stmt 0 view .LVU128
+ 426 0026 436B     		ldr	r3, [r0, #52]
+ 427              		.loc 1 251 8 view .LVU129
+ 428 0028 03B1     		cbz	r3, .L28
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     {
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****       /* Transfer error callback */
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****       hdma->XferErrorCallback(hdma);
+ 429              		.loc 1 254 7 is_stmt 1 view .LVU130
+ 430 002a 9847     		blx	r3
+ 431              	.LVL29:
+ 432              	.L28:
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     }
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   if (hdma->DMAmuxRequestGen != 0)
+ 433              		.loc 1 258 3 view .LVU131
+ 434              		.loc 1 258 11 is_stmt 0 view .LVU132
+ 435 002c 636D     		ldr	r3, [r4, #84]
+ 436              		.loc 1 258 6 view .LVU133
+ 437 002e 9BB1     		cbz	r3, .L27
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   {
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+ 438              		.loc 1 261 5 is_stmt 1 view .LVU134
+ 439              		.loc 1 261 14 is_stmt 0 view .LVU135
+ 440 0030 A26D     		ldr	r2, [r4, #88]
+ 441              		.loc 1 261 38 view .LVU136
+ 442 0032 1168     		ldr	r1, [r2]
+ 443              		.loc 1 261 51 view .LVU137
+ 444 0034 E26D     		ldr	r2, [r4, #92]
+ 445              		.loc 1 261 8 view .LVU138
+ 446 0036 1142     		tst	r1, r2
+ 447 0038 0ED0     		beq	.L27
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     {
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****       /* Disable the request gen overrun interrupt */
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+ 448              		.loc 1 264 7 is_stmt 1 view .LVU139
+ 449              		.loc 1 264 29 is_stmt 0 view .LVU140
+ 450 003a 1A68     		ldr	r2, [r3]
+ 451              		.loc 1 264 36 view .LVU141
+ 452 003c 22F48072 		bic	r2, r2, #256
+ 453 0040 1A60     		str	r2, [r3]
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****       /* Clear the DMAMUX request generator overrun flag */
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 454              		.loc 1 267 7 is_stmt 1 view .LVU142
+ 455              		.loc 1 267 11 is_stmt 0 view .LVU143
+ 456 0042 A36D     		ldr	r3, [r4, #88]
+ 457              		.loc 1 267 49 view .LVU144
+ 458 0044 E26D     		ldr	r2, [r4, #92]
+ 459              		.loc 1 267 43 view .LVU145
+ 460 0046 5A60     		str	r2, [r3, #4]
+ARM GAS  /tmp/ccF4OHvs.s 			page 33
+
+
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****       /* Update error code */
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****       hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+ 461              		.loc 1 270 7 is_stmt 1 view .LVU146
+ 462              		.loc 1 270 11 is_stmt 0 view .LVU147
+ 463 0048 E36B     		ldr	r3, [r4, #60]
+ 464              		.loc 1 270 23 view .LVU148
+ 465 004a 43F48063 		orr	r3, r3, #1024
+ 466 004e E363     		str	r3, [r4, #60]
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** 
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****       if (hdma->XferErrorCallback != NULL)
+ 467              		.loc 1 272 7 is_stmt 1 view .LVU149
+ 468              		.loc 1 272 15 is_stmt 0 view .LVU150
+ 469 0050 636B     		ldr	r3, [r4, #52]
+ 470              		.loc 1 272 10 view .LVU151
+ 471 0052 0BB1     		cbz	r3, .L27
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****       {
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****         /* Transfer error callback */
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****         hdma->XferErrorCallback(hdma);
+ 472              		.loc 1 275 9 is_stmt 1 view .LVU152
+ 473 0054 2046     		mov	r0, r4
+ 474 0056 9847     		blx	r3
+ 475              	.LVL30:
+ 476              	.L27:
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****       }
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****     }
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ****   }
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c **** }
+ 477              		.loc 1 279 1 is_stmt 0 view .LVU153
+ 478 0058 10BD     		pop	{r4, pc}
+ 479              		.loc 1 279 1 view .LVU154
+ 480              		.cfi_endproc
+ 481              	.LFE333:
+ 483              		.text
+ 484              	.Letext0:
+ 485              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 486              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 487              		.file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 488              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 489              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 490              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h"
+ARM GAS  /tmp/ccF4OHvs.s 			page 34
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_dma_ex.c
+     /tmp/ccF4OHvs.s:21     .text.HAL_DMAEx_ConfigMuxSync:00000000 $t
+     /tmp/ccF4OHvs.s:27     .text.HAL_DMAEx_ConfigMuxSync:00000000 HAL_DMAEx_ConfigMuxSync
+     /tmp/ccF4OHvs.s:116    .text.HAL_DMAEx_ConfigMuxRequestGenerator:00000000 $t
+     /tmp/ccF4OHvs.s:122    .text.HAL_DMAEx_ConfigMuxRequestGenerator:00000000 HAL_DMAEx_ConfigMuxRequestGenerator
+     /tmp/ccF4OHvs.s:265    .text.HAL_DMAEx_EnableMuxRequestGenerator:00000000 $t
+     /tmp/ccF4OHvs.s:271    .text.HAL_DMAEx_EnableMuxRequestGenerator:00000000 HAL_DMAEx_EnableMuxRequestGenerator
+     /tmp/ccF4OHvs.s:319    .text.HAL_DMAEx_DisableMuxRequestGenerator:00000000 $t
+     /tmp/ccF4OHvs.s:325    .text.HAL_DMAEx_DisableMuxRequestGenerator:00000000 HAL_DMAEx_DisableMuxRequestGenerator
+     /tmp/ccF4OHvs.s:373    .text.HAL_DMAEx_MUX_IRQHandler:00000000 $t
+     /tmp/ccF4OHvs.s:379    .text.HAL_DMAEx_MUX_IRQHandler:00000000 HAL_DMAEx_MUX_IRQHandler
+
+NO UNDEFINED SYMBOLS
diff --git a/squeow_sw/build/stm32g4xx_hal_dma_ex.o b/squeow_sw/build/stm32g4xx_hal_dma_ex.o
new file mode 100644
index 0000000000000000000000000000000000000000..b6da9eae083d74a5e14ce3ddb4dc9f9f71ab3491
GIT binary patch
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HcmV?d00001

diff --git a/squeow_sw/build/stm32g4xx_hal_exti.d b/squeow_sw/build/stm32g4xx_hal_exti.d
new file mode 100644
index 0000000..bbb39dd
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_exti.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_exti.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_exti.lst b/squeow_sw/build/stm32g4xx_hal_exti.lst
new file mode 100644
index 0000000..e5947be
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_exti.lst
@@ -0,0 +1,1855 @@
+ARM GAS  /tmp/ccx3buCY.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_exti.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c"
+  20              		.section	.text.HAL_EXTI_SetConfigLine,"ax",%progbits
+  21              		.align	1
+  22              		.global	HAL_EXTI_SetConfigLine
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	HAL_EXTI_SetConfigLine:
+  28              	.LVL0:
+  29              	.LFB329:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @file    stm32g4xx_hal_exti.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @brief   EXTI HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *           + Initialization and de-initialization functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *           + IO operation functions
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   ******************************************************************************
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @attention
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * Copyright (c) 2019 STMicroelectronics.
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * All rights reserved.
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * in the root directory of this software component.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   ******************************************************************************
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   @verbatim
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   ==============================================================================
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****                     ##### EXTI Peripheral features #####
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   ==============================================================================
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   [..]
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     (+) Each Exti line can be configured within this driver.
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ARM GAS  /tmp/ccx3buCY.s 			page 2
+
+
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     (+) Exti line can be configured in 3 different modes
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Interrupt
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Event
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Both of them
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     (+) Configurable Exti lines can be configured with 3 different triggers
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Rising
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Falling
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Both of them
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     (+) When set in interrupt mode, configurable Exti lines have two different
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         interrupt pending registers which allow to distinguish which transition
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         occurs:
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Rising edge pending interrupt
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Falling
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         be selected through multiplexer.
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****                      ##### How to use this driver #####
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   ==============================================================================
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   [..]
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Choose the interrupt line number by setting "Line" member from
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****              EXTI_ConfigTypeDef structure.
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Configure the interrupt and/or event mode using "Mode" member from
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****              EXTI_ConfigTypeDef structure.
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) For configurable lines, configure rising and/or falling trigger
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****              "Trigger" member from EXTI_ConfigTypeDef structure.
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****              member from GPIO_InitTypeDef structure.
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     (#) Get current Exti configuration of a dedicated line using
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         HAL_EXTI_GetConfigLine().
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Provide exiting handle as parameter.
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Provide exiting handle as parameter.
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Provide exiting handle as first parameter.
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Provide which callback will be registered using one value from
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****              EXTI_CallbackIDTypeDef.
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****         (++) Provide callback function pointer.
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   @endverbatim
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /* Includes ------------------------------------------------------------------*/
+ARM GAS  /tmp/ccx3buCY.s 			page 3
+
+
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** #include "stm32g4xx_hal.h"
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @{
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /** @addtogroup EXTI
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @{
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /** MISRA C:2012 deviation rule has been granted for following rule:
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * of bounds [0,3] in following API :
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * HAL_EXTI_SetConfigLine
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * HAL_EXTI_GetConfigLine
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * HAL_EXTI_ClearConfigLine
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** #ifdef HAL_EXTI_MODULE_ENABLED
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /* Private typedef -----------------------------------------------------------*/
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /* Private defines ------------------------------------------------------------*/
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /** @defgroup EXTI_Private_Constants EXTI Private Constants
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @{
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** #define EXTI_MODE_OFFSET                    0x08U   /* 0x20: offset between MCU IMR/EMR registers *
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** #define EXTI_CONFIG_OFFSET                  0x08U   /* 0x20: offset between MCU Rising/Falling conf
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /**
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @}
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /* Private macros ------------------------------------------------------------*/
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /* Private variables ---------------------------------------------------------*/
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /* Private function prototypes -----------------------------------------------*/
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /* Exported functions --------------------------------------------------------*/
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @{
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group1
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *  @brief    Configuration functions
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** @verbatim
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****  ===============================================================================
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****               ##### Configuration functions #####
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****  ===============================================================================
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** @endverbatim
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @{
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /**
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @brief  Set configuration of a dedicated Exti line.
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  pExtiConfig Pointer on EXTI configuration to be set.
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @retval HAL Status.
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ARM GAS  /tmp/ccx3buCY.s 			page 4
+
+
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** {
+  30              		.loc 1 145 1 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		@ link register save eliminated.
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   __IO uint32_t *regaddr;
+  35              		.loc 1 146 3 view .LVU1
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t regval;
+  36              		.loc 1 147 3 view .LVU2
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t linepos;
+  37              		.loc 1 148 3 view .LVU3
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t maskline;
+  38              		.loc 1 149 3 view .LVU4
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t offset;
+  39              		.loc 1 150 3 view .LVU5
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check null pointer */
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   if ((hexti == NULL) || (pExtiConfig == NULL))
+  40              		.loc 1 153 3 view .LVU6
+  41              		.loc 1 153 6 is_stmt 0 view .LVU7
+  42 0000 0028     		cmp	r0, #0
+  43 0002 5ED0     		beq	.L12
+  44              		.loc 1 153 23 discriminator 1 view .LVU8
+  45 0004 0029     		cmp	r1, #0
+  46 0006 5ED0     		beq	.L13
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   __IO uint32_t *regaddr;
+  47              		.loc 1 145 1 view .LVU9
+  48 0008 F0B4     		push	{r4, r5, r6, r7}
+  49              	.LCFI0:
+  50              		.cfi_def_cfa_offset 16
+  51              		.cfi_offset 4, -16
+  52              		.cfi_offset 5, -12
+  53              		.cfi_offset 6, -8
+  54              		.cfi_offset 7, -4
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     return HAL_ERROR;
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check parameters */
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  55              		.loc 1 159 3 is_stmt 1 view .LVU10
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+  56              		.loc 1 160 3 view .LVU11
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Assign line number to handle */
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   hexti->Line = pExtiConfig->Line;
+  57              		.loc 1 163 3 view .LVU12
+  58              		.loc 1 163 28 is_stmt 0 view .LVU13
+  59 000a 0A68     		ldr	r2, [r1]
+  60              		.loc 1 163 15 view .LVU14
+  61 000c 0260     		str	r2, [r0]
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Compute line register offset */
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  62              		.loc 1 166 3 is_stmt 1 view .LVU15
+ARM GAS  /tmp/ccx3buCY.s 			page 5
+
+
+  63              		.loc 1 166 10 is_stmt 0 view .LVU16
+  64 000e C2F30043 		ubfx	r3, r2, #16, #1
+  65              	.LVL1:
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Compute line position */
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  66              		.loc 1 168 3 is_stmt 1 view .LVU17
+  67              		.loc 1 168 11 is_stmt 0 view .LVU18
+  68 0012 02F01F04 		and	r4, r2, #31
+  69              	.LVL2:
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Compute line mask */
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   maskline = (1uL << linepos);
+  70              		.loc 1 170 3 is_stmt 1 view .LVU19
+  71              		.loc 1 170 12 is_stmt 0 view .LVU20
+  72 0016 0120     		movs	r0, #1
+  73              	.LVL3:
+  74              		.loc 1 170 12 view .LVU21
+  75 0018 A040     		lsls	r0, r0, r4
+  76              	.LVL4:
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Configure triggers for configurable lines */
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+  77              		.loc 1 173 3 is_stmt 1 view .LVU22
+  78              		.loc 1 173 6 is_stmt 0 view .LVU23
+  79 001a 12F0007F 		tst	r2, #33554432
+  80 001e 1BD0     		beq	.L3
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+  81              		.loc 1 175 5 is_stmt 1 view .LVU24
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Configure rising trigger */
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+  82              		.loc 1 178 5 view .LVU25
+  83              		.loc 1 178 29 is_stmt 0 view .LVU26
+  84 0020 4FEA431C 		lsl	ip, r3, #5
+  85              		.loc 1 178 13 view .LVU27
+  86 0024 294F     		ldr	r7, .L19
+  87              	.LVL5:
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regval = *regaddr;
+  88              		.loc 1 179 5 is_stmt 1 view .LVU28
+  89              		.loc 1 179 12 is_stmt 0 view .LVU29
+  90 0026 5CF80750 		ldr	r5, [ip, r7]
+  91              	.LVL6:
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Mask or set line */
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
+  92              		.loc 1 182 5 is_stmt 1 view .LVU30
+  93              		.loc 1 182 21 is_stmt 0 view .LVU31
+  94 002a 8E68     		ldr	r6, [r1, #8]
+  95              		.loc 1 182 8 view .LVU32
+  96 002c 16F0010F 		tst	r6, #1
+  97 0030 29D0     		beq	.L4
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     {
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval |= maskline;
+  98              		.loc 1 184 7 is_stmt 1 view .LVU33
+  99              		.loc 1 184 14 is_stmt 0 view .LVU34
+ 100 0032 0543     		orrs	r5, r5, r0
+ 101              	.LVL7:
+ARM GAS  /tmp/ccx3buCY.s 			page 6
+
+
+ 102              	.L5:
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     else
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     {
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval &= ~maskline;
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Store rising trigger mode */
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     *regaddr = regval;
+ 103              		.loc 1 192 5 is_stmt 1 view .LVU35
+ 104              		.loc 1 192 14 is_stmt 0 view .LVU36
+ 105 0034 4CF80750 		str	r5, [ip, r7]
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Configure falling trigger */
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ 106              		.loc 1 195 5 is_stmt 1 view .LVU37
+ 107              		.loc 1 195 13 is_stmt 0 view .LVU38
+ 108 0038 254E     		ldr	r6, .L19+4
+ 109              	.LVL8:
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regval = *regaddr;
+ 110              		.loc 1 196 5 is_stmt 1 view .LVU39
+ 111              		.loc 1 196 12 is_stmt 0 view .LVU40
+ 112 003a 5CF80650 		ldr	r5, [ip, r6]
+ 113              	.LVL9:
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Mask or set line */
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
+ 114              		.loc 1 199 5 is_stmt 1 view .LVU41
+ 115              		.loc 1 199 8 is_stmt 0 view .LVU42
+ 116 003e 8F68     		ldr	r7, [r1, #8]
+ 117 0040 17F0020F 		tst	r7, #2
+ 118 0044 22D0     		beq	.L6
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     {
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval |= maskline;
+ 119              		.loc 1 201 7 is_stmt 1 view .LVU43
+ 120              		.loc 1 201 14 is_stmt 0 view .LVU44
+ 121 0046 0543     		orrs	r5, r5, r0
+ 122              	.LVL10:
+ 123              	.L7:
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     else
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     {
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval &= ~maskline;
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Store falling trigger mode */
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     *regaddr = regval;
+ 124              		.loc 1 209 5 is_stmt 1 view .LVU45
+ 125              		.loc 1 209 14 is_stmt 0 view .LVU46
+ 126 0048 4CF80650 		str	r5, [ip, r6]
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Configure gpio port selection in case of gpio exti line */
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ 127              		.loc 1 212 5 is_stmt 1 view .LVU47
+ 128              		.loc 1 212 28 is_stmt 0 view .LVU48
+ 129 004c 0D68     		ldr	r5, [r1]
+ 130              	.LVL11:
+ARM GAS  /tmp/ccx3buCY.s 			page 7
+
+
+ 131              		.loc 1 212 28 view .LVU49
+ 132 004e 05F0C06C 		and	ip, r5, #100663296
+ 133              	.LVL12:
+ 134              		.loc 1 212 8 view .LVU50
+ 135 0052 BCF1C06F 		cmp	ip, #100663296
+ 136 0056 1CD0     		beq	.L18
+ 137              	.LVL13:
+ 138              	.L3:
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     {
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       assert_param(IS_EXTI_GPIO_PIN(linepos));
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval = SYSCFG->EXTICR[linepos >> 2u];
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Configure interrupt mode : read current mode */
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+ 139              		.loc 1 225 3 is_stmt 1 view .LVU51
+ 140              		.loc 1 225 26 is_stmt 0 view .LVU52
+ 141 0058 5B01     		lsls	r3, r3, #5
+ 142              	.LVL14:
+ 143              		.loc 1 225 11 view .LVU53
+ 144 005a 03F18042 		add	r2, r3, #1073741824
+ 145 005e 02F58232 		add	r2, r2, #66560
+ 146              	.LVL15:
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regval = *regaddr;
+ 147              		.loc 1 226 3 is_stmt 1 view .LVU54
+ 148              		.loc 1 226 10 is_stmt 0 view .LVU55
+ 149 0062 1468     		ldr	r4, [r2]
+ 150              	.LVL16:
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Mask or set line */
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
+ 151              		.loc 1 229 3 is_stmt 1 view .LVU56
+ 152              		.loc 1 229 6 is_stmt 0 view .LVU57
+ 153 0064 4D68     		ldr	r5, [r1, #4]
+ 154 0066 15F0010F 		tst	r5, #1
+ 155 006a 24D0     		beq	.L8
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regval |= maskline;
+ 156              		.loc 1 231 5 is_stmt 1 view .LVU58
+ 157              		.loc 1 231 12 is_stmt 0 view .LVU59
+ 158 006c 0443     		orrs	r4, r4, r0
+ 159              	.LVL17:
+ 160              	.L9:
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   else
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regval &= ~maskline;
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Store interrupt mode */
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *regaddr = regval;
+ARM GAS  /tmp/ccx3buCY.s 			page 8
+
+
+ 161              		.loc 1 239 3 is_stmt 1 view .LVU60
+ 162              		.loc 1 239 12 is_stmt 0 view .LVU61
+ 163 006e 1460     		str	r4, [r2]
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Configure event mode : read current mode */
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+ 164              		.loc 1 242 3 is_stmt 1 view .LVU62
+ 165              		.loc 1 242 11 is_stmt 0 view .LVU63
+ 166 0070 184C     		ldr	r4, .L19+8
+ 167              	.LVL18:
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regval = *regaddr;
+ 168              		.loc 1 243 3 is_stmt 1 view .LVU64
+ 169              		.loc 1 243 10 is_stmt 0 view .LVU65
+ 170 0072 1A59     		ldr	r2, [r3, r4]
+ 171              	.LVL19:
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Mask or set line */
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
+ 172              		.loc 1 246 3 is_stmt 1 view .LVU66
+ 173              		.loc 1 246 19 is_stmt 0 view .LVU67
+ 174 0074 4968     		ldr	r1, [r1, #4]
+ 175              	.LVL20:
+ 176              		.loc 1 246 6 view .LVU68
+ 177 0076 11F0020F 		tst	r1, #2
+ 178 007a 1FD0     		beq	.L10
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regval |= maskline;
+ 179              		.loc 1 248 5 is_stmt 1 view .LVU69
+ 180              		.loc 1 248 12 is_stmt 0 view .LVU70
+ 181 007c 0243     		orrs	r2, r2, r0
+ 182              	.LVL21:
+ 183              	.L11:
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   else
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regval &= ~maskline;
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Store event mode */
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *regaddr = regval;
+ 184              		.loc 1 256 3 is_stmt 1 view .LVU71
+ 185              		.loc 1 256 12 is_stmt 0 view .LVU72
+ 186 007e 1A51     		str	r2, [r3, r4]
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   return HAL_OK;
+ 187              		.loc 1 258 3 is_stmt 1 view .LVU73
+ 188              		.loc 1 258 10 is_stmt 0 view .LVU74
+ 189 0080 0020     		movs	r0, #0
+ 190              	.LVL22:
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** }
+ 191              		.loc 1 259 1 view .LVU75
+ 192 0082 F0BC     		pop	{r4, r5, r6, r7}
+ 193              	.LCFI1:
+ 194              		.cfi_remember_state
+ 195              		.cfi_restore 7
+ 196              		.cfi_restore 6
+ 197              		.cfi_restore 5
+ARM GAS  /tmp/ccx3buCY.s 			page 9
+
+
+ 198              		.cfi_restore 4
+ 199              		.cfi_def_cfa_offset 0
+ 200              	.LVL23:
+ 201              		.loc 1 259 1 view .LVU76
+ 202 0084 7047     		bx	lr
+ 203              	.LVL24:
+ 204              	.L4:
+ 205              	.LCFI2:
+ 206              		.cfi_restore_state
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 207              		.loc 1 188 7 is_stmt 1 view .LVU77
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 208              		.loc 1 188 14 is_stmt 0 view .LVU78
+ 209 0086 25EA0005 		bic	r5, r5, r0
+ 210              	.LVL25:
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 211              		.loc 1 188 14 view .LVU79
+ 212 008a D3E7     		b	.L5
+ 213              	.LVL26:
+ 214              	.L6:
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 215              		.loc 1 205 7 is_stmt 1 view .LVU80
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 216              		.loc 1 205 14 is_stmt 0 view .LVU81
+ 217 008c 25EA0005 		bic	r5, r5, r0
+ 218              	.LVL27:
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 219              		.loc 1 205 14 view .LVU82
+ 220 0090 DAE7     		b	.L7
+ 221              	.LVL28:
+ 222              	.L18:
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       assert_param(IS_EXTI_GPIO_PIN(linepos));
+ 223              		.loc 1 214 7 is_stmt 1 view .LVU83
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 224              		.loc 1 215 7 view .LVU84
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 225              		.loc 1 217 7 view .LVU85
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 226              		.loc 1 217 39 is_stmt 0 view .LVU86
+ 227 0092 A408     		lsrs	r4, r4, #2
+ 228              	.LVL29:
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 229              		.loc 1 217 14 view .LVU87
+ 230 0094 104F     		ldr	r7, .L19+12
+ 231 0096 0234     		adds	r4, r4, #2
+ 232 0098 57F82460 		ldr	r6, [r7, r4, lsl #2]
+ 233              	.LVL30:
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 234              		.loc 1 218 7 is_stmt 1 view .LVU88
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 235              		.loc 1 218 80 is_stmt 0 view .LVU89
+ 236 009c 02F00302 		and	r2, r2, #3
+ 237              	.LVL31:
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 238              		.loc 1 218 69 view .LVU90
+ 239 00a0 9200     		lsls	r2, r2, #2
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ARM GAS  /tmp/ccx3buCY.s 			page 10
+
+
+ 240              		.loc 1 218 40 view .LVU91
+ 241 00a2 0725     		movs	r5, #7
+ 242 00a4 9540     		lsls	r5, r5, r2
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 243              		.loc 1 218 14 view .LVU92
+ 244 00a6 26EA0506 		bic	r6, r6, r5
+ 245              	.LVL32:
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 246              		.loc 1 219 7 is_stmt 1 view .LVU93
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 247              		.loc 1 219 29 is_stmt 0 view .LVU94
+ 248 00aa CD68     		ldr	r5, [r1, #12]
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 249              		.loc 1 219 39 view .LVU95
+ 250 00ac 9540     		lsls	r5, r5, r2
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 251              		.loc 1 219 14 view .LVU96
+ 252 00ae 3543     		orrs	r5, r5, r6
+ 253              	.LVL33:
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 254              		.loc 1 220 7 is_stmt 1 view .LVU97
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 255              		.loc 1 220 37 is_stmt 0 view .LVU98
+ 256 00b0 47F82450 		str	r5, [r7, r4, lsl #2]
+ 257 00b4 D0E7     		b	.L3
+ 258              	.LVL34:
+ 259              	.L8:
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 260              		.loc 1 235 5 is_stmt 1 view .LVU99
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 261              		.loc 1 235 12 is_stmt 0 view .LVU100
+ 262 00b6 24EA0004 		bic	r4, r4, r0
+ 263              	.LVL35:
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 264              		.loc 1 235 12 view .LVU101
+ 265 00ba D8E7     		b	.L9
+ 266              	.LVL36:
+ 267              	.L10:
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 268              		.loc 1 252 5 is_stmt 1 view .LVU102
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 269              		.loc 1 252 12 is_stmt 0 view .LVU103
+ 270 00bc 22EA0002 		bic	r2, r2, r0
+ 271              	.LVL37:
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 272              		.loc 1 252 12 view .LVU104
+ 273 00c0 DDE7     		b	.L11
+ 274              	.LVL38:
+ 275              	.L12:
+ 276              	.LCFI3:
+ 277              		.cfi_def_cfa_offset 0
+ 278              		.cfi_restore 4
+ 279              		.cfi_restore 5
+ 280              		.cfi_restore 6
+ 281              		.cfi_restore 7
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 282              		.loc 1 155 12 view .LVU105
+ARM GAS  /tmp/ccx3buCY.s 			page 11
+
+
+ 283 00c2 0120     		movs	r0, #1
+ 284              	.LVL39:
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 285              		.loc 1 155 12 view .LVU106
+ 286 00c4 7047     		bx	lr
+ 287              	.LVL40:
+ 288              	.L13:
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 289              		.loc 1 155 12 view .LVU107
+ 290 00c6 0120     		movs	r0, #1
+ 291              	.LVL41:
+ 292              		.loc 1 259 1 view .LVU108
+ 293 00c8 7047     		bx	lr
+ 294              	.L20:
+ 295 00ca 00BF     		.align	2
+ 296              	.L19:
+ 297 00cc 08040140 		.word	1073808392
+ 298 00d0 0C040140 		.word	1073808396
+ 299 00d4 04040140 		.word	1073808388
+ 300 00d8 00000140 		.word	1073807360
+ 301              		.cfi_endproc
+ 302              	.LFE329:
+ 304              		.section	.text.HAL_EXTI_GetConfigLine,"ax",%progbits
+ 305              		.align	1
+ 306              		.global	HAL_EXTI_GetConfigLine
+ 307              		.syntax unified
+ 308              		.thumb
+ 309              		.thumb_func
+ 311              	HAL_EXTI_GetConfigLine:
+ 312              	.LVL42:
+ 313              	.LFB330:
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /**
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @brief  Get configuration of a dedicated Exti line.
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  pExtiConfig Pointer on structure to store Exti configuration.
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @retval HAL Status.
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** {
+ 314              		.loc 1 269 1 is_stmt 1 view -0
+ 315              		.cfi_startproc
+ 316              		@ args = 0, pretend = 0, frame = 0
+ 317              		@ frame_needed = 0, uses_anonymous_args = 0
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   __IO uint32_t *regaddr;
+ 318              		.loc 1 270 3 view .LVU110
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t regval;
+ 319              		.loc 1 271 3 view .LVU111
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t linepos;
+ 320              		.loc 1 272 3 view .LVU112
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t maskline;
+ 321              		.loc 1 273 3 view .LVU113
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t offset;
+ 322              		.loc 1 274 3 view .LVU114
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check null pointer */
+ARM GAS  /tmp/ccx3buCY.s 			page 12
+
+
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   if ((hexti == NULL) || (pExtiConfig == NULL))
+ 323              		.loc 1 277 3 view .LVU115
+ 324              		.loc 1 277 6 is_stmt 0 view .LVU116
+ 325 0000 0028     		cmp	r0, #0
+ 326 0002 4AD0     		beq	.L28
+ 327              		.loc 1 277 23 discriminator 1 view .LVU117
+ 328 0004 0029     		cmp	r1, #0
+ 329 0006 4AD0     		beq	.L29
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   __IO uint32_t *regaddr;
+ 330              		.loc 1 269 1 view .LVU118
+ 331 0008 10B5     		push	{r4, lr}
+ 332              	.LCFI4:
+ 333              		.cfi_def_cfa_offset 8
+ 334              		.cfi_offset 4, -8
+ 335              		.cfi_offset 14, -4
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     return HAL_ERROR;
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check the parameter */
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(hexti->Line));
+ 336              		.loc 1 283 3 is_stmt 1 view .LVU119
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Store handle line number to configuration structure */
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   pExtiConfig->Line = hexti->Line;
+ 337              		.loc 1 286 3 view .LVU120
+ 338              		.loc 1 286 28 is_stmt 0 view .LVU121
+ 339 000a 0368     		ldr	r3, [r0]
+ 340              		.loc 1 286 21 view .LVU122
+ 341 000c 0B60     		str	r3, [r1]
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Compute line register offset and line mask */
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ 342              		.loc 1 289 3 is_stmt 1 view .LVU123
+ 343              		.loc 1 289 10 is_stmt 0 view .LVU124
+ 344 000e C3F30040 		ubfx	r0, r3, #16, #1
+ 345              	.LVL43:
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Compute line position */
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ 346              		.loc 1 291 3 is_stmt 1 view .LVU125
+ 347              		.loc 1 291 11 is_stmt 0 view .LVU126
+ 348 0012 03F01F0E 		and	lr, r3, #31
+ 349              	.LVL44:
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Compute mask */
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   maskline = (1uL << linepos);
+ 350              		.loc 1 293 3 is_stmt 1 view .LVU127
+ 351              		.loc 1 293 12 is_stmt 0 view .LVU128
+ 352 0016 0122     		movs	r2, #1
+ 353 0018 02FA0EF2 		lsl	r2, r2, lr
+ 354              	.LVL45:
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* 1] Get core mode : interrupt */
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+ 355              		.loc 1 296 3 is_stmt 1 view .LVU129
+ 356              		.loc 1 296 26 is_stmt 0 view .LVU130
+ 357 001c 4001     		lsls	r0, r0, #5
+ 358              	.LVL46:
+ARM GAS  /tmp/ccx3buCY.s 			page 13
+
+
+ 359              		.loc 1 296 11 view .LVU131
+ 360 001e 00F1804C 		add	ip, r0, #1073741824
+ 361 0022 0CF5823C 		add	ip, ip, #66560
+ 362              	.LVL47:
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regval = *regaddr;
+ 363              		.loc 1 297 3 is_stmt 1 view .LVU132
+ 364              		.loc 1 297 10 is_stmt 0 view .LVU133
+ 365 0026 DCF80040 		ldr	r4, [ip]
+ 366              	.LVL48:
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check if selected line is enable */
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   if ((regval & maskline) != 0x00u)
+ 367              		.loc 1 300 3 is_stmt 1 view .LVU134
+ 368              		.loc 1 300 6 is_stmt 0 view .LVU135
+ 369 002a 2242     		tst	r2, r4
+ 370 002c 24D0     		beq	.L23
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+ 371              		.loc 1 302 5 is_stmt 1 view .LVU136
+ 372              		.loc 1 302 23 is_stmt 0 view .LVU137
+ 373 002e 0124     		movs	r4, #1
+ 374              	.LVL49:
+ 375              		.loc 1 302 23 view .LVU138
+ 376 0030 4C60     		str	r4, [r1, #4]
+ 377              	.L24:
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   else
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     pExtiConfig->Mode = EXTI_MODE_NONE;
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Get event mode */
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+ 378              		.loc 1 310 3 is_stmt 1 view .LVU139
+ 379              		.loc 1 310 11 is_stmt 0 view .LVU140
+ 380 0032 1D4C     		ldr	r4, .L37
+ 381              	.LVL50:
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regval = *regaddr;
+ 382              		.loc 1 311 3 is_stmt 1 view .LVU141
+ 383              		.loc 1 311 10 is_stmt 0 view .LVU142
+ 384 0034 0459     		ldr	r4, [r0, r4]
+ 385              	.LVL51:
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check if selected line is enable */
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   if ((regval & maskline) != 0x00u)
+ 386              		.loc 1 314 3 is_stmt 1 view .LVU143
+ 387              		.loc 1 314 6 is_stmt 0 view .LVU144
+ 388 0036 2242     		tst	r2, r4
+ 389 0038 03D0     		beq	.L25
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     pExtiConfig->Mode |= EXTI_MODE_EVENT;
+ 390              		.loc 1 316 5 is_stmt 1 view .LVU145
+ 391              		.loc 1 316 16 is_stmt 0 view .LVU146
+ 392 003a 4C68     		ldr	r4, [r1, #4]
+ 393              	.LVL52:
+ 394              		.loc 1 316 23 view .LVU147
+ 395 003c 44F00204 		orr	r4, r4, #2
+ARM GAS  /tmp/ccx3buCY.s 			page 14
+
+
+ 396 0040 4C60     		str	r4, [r1, #4]
+ 397              	.L25:
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Get default Trigger and GPIOSel configuration */
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ 398              		.loc 1 320 3 is_stmt 1 view .LVU148
+ 399              		.loc 1 320 24 is_stmt 0 view .LVU149
+ 400 0042 0024     		movs	r4, #0
+ 401 0044 8C60     		str	r4, [r1, #8]
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   pExtiConfig->GPIOSel = 0x00u;
+ 402              		.loc 1 321 3 is_stmt 1 view .LVU150
+ 403              		.loc 1 321 24 is_stmt 0 view .LVU151
+ 404 0046 CC60     		str	r4, [r1, #12]
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* 2] Get trigger for configurable lines : rising */
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+ 405              		.loc 1 324 3 is_stmt 1 view .LVU152
+ 406              		.loc 1 324 6 is_stmt 0 view .LVU153
+ 407 0048 13F0007F 		tst	r3, #33554432
+ 408 004c 29D0     		beq	.L30
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ 409              		.loc 1 326 5 is_stmt 1 view .LVU154
+ 410              		.loc 1 326 13 is_stmt 0 view .LVU155
+ 411 004e 174C     		ldr	r4, .L37+4
+ 412              	.LVL53:
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regval = *regaddr;
+ 413              		.loc 1 327 5 is_stmt 1 view .LVU156
+ 414              		.loc 1 327 12 is_stmt 0 view .LVU157
+ 415 0050 0459     		ldr	r4, [r0, r4]
+ 416              	.LVL54:
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Check if configuration of selected line is enable */
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     if ((regval & maskline) != 0x00u)
+ 417              		.loc 1 330 5 is_stmt 1 view .LVU158
+ 418              		.loc 1 330 8 is_stmt 0 view .LVU159
+ 419 0052 2242     		tst	r2, r4
+ 420 0054 01D0     		beq	.L26
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     {
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+ 421              		.loc 1 332 7 is_stmt 1 view .LVU160
+ 422              		.loc 1 332 28 is_stmt 0 view .LVU161
+ 423 0056 0124     		movs	r4, #1
+ 424              	.LVL55:
+ 425              		.loc 1 332 28 view .LVU162
+ 426 0058 8C60     		str	r4, [r1, #8]
+ 427              	.L26:
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Get falling configuration */
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ 428              		.loc 1 336 5 is_stmt 1 view .LVU163
+ 429              		.loc 1 336 13 is_stmt 0 view .LVU164
+ 430 005a 154C     		ldr	r4, .L37+8
+ 431              	.LVL56:
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regval = *regaddr;
+ARM GAS  /tmp/ccx3buCY.s 			page 15
+
+
+ 432              		.loc 1 337 5 is_stmt 1 view .LVU165
+ 433              		.loc 1 337 12 is_stmt 0 view .LVU166
+ 434 005c 0059     		ldr	r0, [r0, r4]
+ 435              	.LVL57:
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Check if configuration of selected line is enable */
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     if ((regval & maskline) != 0x00u)
+ 436              		.loc 1 340 5 is_stmt 1 view .LVU167
+ 437              		.loc 1 340 8 is_stmt 0 view .LVU168
+ 438 005e 0242     		tst	r2, r0
+ 439 0060 03D0     		beq	.L27
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     {
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+ 440              		.loc 1 342 7 is_stmt 1 view .LVU169
+ 441              		.loc 1 342 18 is_stmt 0 view .LVU170
+ 442 0062 8A68     		ldr	r2, [r1, #8]
+ 443              	.LVL58:
+ 444              		.loc 1 342 28 view .LVU171
+ 445 0064 42F00202 		orr	r2, r2, #2
+ 446 0068 8A60     		str	r2, [r1, #8]
+ 447              	.L27:
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Get Gpio port selection for gpio lines */
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ 448              		.loc 1 346 5 is_stmt 1 view .LVU172
+ 449              		.loc 1 346 28 is_stmt 0 view .LVU173
+ 450 006a 03F0C062 		and	r2, r3, #100663296
+ 451              		.loc 1 346 8 view .LVU174
+ 452 006e B2F1C06F 		cmp	r2, #100663296
+ 453 0072 04D0     		beq	.L36
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     {
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       assert_param(IS_EXTI_GPIO_PIN(linepos));
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval = SYSCFG->EXTICR[linepos >> 2u];
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       pExtiConfig->GPIOSel = ((regval >> (SYSCFG_EXTICR1_EXTI1_Pos * ((linepos & 0x03u)))));
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   return HAL_OK;
+ 454              		.loc 1 355 10 view .LVU175
+ 455 0074 0020     		movs	r0, #0
+ 456              	.LVL59:
+ 457              		.loc 1 355 10 view .LVU176
+ 458 0076 15E0     		b	.L22
+ 459              	.LVL60:
+ 460              	.L23:
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 461              		.loc 1 306 5 is_stmt 1 view .LVU177
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 462              		.loc 1 306 23 is_stmt 0 view .LVU178
+ 463 0078 0024     		movs	r4, #0
+ 464              	.LVL61:
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 465              		.loc 1 306 23 view .LVU179
+ 466 007a 4C60     		str	r4, [r1, #4]
+ 467 007c D9E7     		b	.L24
+ARM GAS  /tmp/ccx3buCY.s 			page 16
+
+
+ 468              	.LVL62:
+ 469              	.L36:
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 470              		.loc 1 348 7 is_stmt 1 view .LVU180
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       pExtiConfig->GPIOSel = ((regval >> (SYSCFG_EXTICR1_EXTI1_Pos * ((linepos & 0x03u)))));
+ 471              		.loc 1 350 7 view .LVU181
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       pExtiConfig->GPIOSel = ((regval >> (SYSCFG_EXTICR1_EXTI1_Pos * ((linepos & 0x03u)))));
+ 472              		.loc 1 350 39 is_stmt 0 view .LVU182
+ 473 007e 4FEA9E02 		lsr	r2, lr, #2
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       pExtiConfig->GPIOSel = ((regval >> (SYSCFG_EXTICR1_EXTI1_Pos * ((linepos & 0x03u)))));
+ 474              		.loc 1 350 14 view .LVU183
+ 475 0082 0232     		adds	r2, r2, #2
+ 476 0084 0B48     		ldr	r0, .L37+12
+ 477              	.LVL63:
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       pExtiConfig->GPIOSel = ((regval >> (SYSCFG_EXTICR1_EXTI1_Pos * ((linepos & 0x03u)))));
+ 478              		.loc 1 350 14 view .LVU184
+ 479 0086 50F82220 		ldr	r2, [r0, r2, lsl #2]
+ 480              	.LVL64:
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 481              		.loc 1 351 7 is_stmt 1 view .LVU185
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 482              		.loc 1 351 80 is_stmt 0 view .LVU186
+ 483 008a 03F00303 		and	r3, r3, #3
+ 484              	.LVL65:
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 485              		.loc 1 351 68 view .LVU187
+ 486 008e 9B00     		lsls	r3, r3, #2
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 487              		.loc 1 351 39 view .LVU188
+ 488 0090 22FA03F3 		lsr	r3, r2, r3
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 489              		.loc 1 351 28 view .LVU189
+ 490 0094 CB60     		str	r3, [r1, #12]
+ 491              		.loc 1 355 10 view .LVU190
+ 492 0096 0020     		movs	r0, #0
+ 493 0098 04E0     		b	.L22
+ 494              	.LVL66:
+ 495              	.L28:
+ 496              	.LCFI5:
+ 497              		.cfi_def_cfa_offset 0
+ 498              		.cfi_restore 4
+ 499              		.cfi_restore 14
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 500              		.loc 1 279 12 view .LVU191
+ 501 009a 0120     		movs	r0, #1
+ 502              	.LVL67:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 503              		.loc 1 279 12 view .LVU192
+ 504 009c 7047     		bx	lr
+ 505              	.LVL68:
+ 506              	.L29:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 507              		.loc 1 279 12 view .LVU193
+ 508 009e 0120     		movs	r0, #1
+ 509              	.LVL69:
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** }
+ 510              		.loc 1 356 1 view .LVU194
+ARM GAS  /tmp/ccx3buCY.s 			page 17
+
+
+ 511 00a0 7047     		bx	lr
+ 512              	.LVL70:
+ 513              	.L30:
+ 514              	.LCFI6:
+ 515              		.cfi_def_cfa_offset 8
+ 516              		.cfi_offset 4, -8
+ 517              		.cfi_offset 14, -4
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** }
+ 518              		.loc 1 355 10 view .LVU195
+ 519 00a2 0020     		movs	r0, #0
+ 520              	.LVL71:
+ 521              	.L22:
+ 522              		.loc 1 356 1 view .LVU196
+ 523 00a4 10BD     		pop	{r4, pc}
+ 524              	.L38:
+ 525 00a6 00BF     		.align	2
+ 526              	.L37:
+ 527 00a8 04040140 		.word	1073808388
+ 528 00ac 08040140 		.word	1073808392
+ 529 00b0 0C040140 		.word	1073808396
+ 530 00b4 00000140 		.word	1073807360
+ 531              		.cfi_endproc
+ 532              	.LFE330:
+ 534              		.section	.text.HAL_EXTI_ClearConfigLine,"ax",%progbits
+ 535              		.align	1
+ 536              		.global	HAL_EXTI_ClearConfigLine
+ 537              		.syntax unified
+ 538              		.thumb
+ 539              		.thumb_func
+ 541              	HAL_EXTI_ClearConfigLine:
+ 542              	.LVL72:
+ 543              	.LFB331:
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /**
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @brief  Clear whole configuration of a dedicated Exti line.
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @retval HAL Status.
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** {
+ 544              		.loc 1 365 1 is_stmt 1 view -0
+ 545              		.cfi_startproc
+ 546              		@ args = 0, pretend = 0, frame = 0
+ 547              		@ frame_needed = 0, uses_anonymous_args = 0
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   __IO uint32_t *regaddr;
+ 548              		.loc 1 366 3 view .LVU198
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t regval;
+ 549              		.loc 1 367 3 view .LVU199
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t linepos;
+ 550              		.loc 1 368 3 view .LVU200
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t maskline;
+ 551              		.loc 1 369 3 view .LVU201
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t offset;
+ 552              		.loc 1 370 3 view .LVU202
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check null pointer */
+ARM GAS  /tmp/ccx3buCY.s 			page 18
+
+
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   if (hexti == NULL)
+ 553              		.loc 1 373 3 view .LVU203
+ 554              		.loc 1 373 6 is_stmt 0 view .LVU204
+ 555 0000 0028     		cmp	r0, #0
+ 556 0002 40D0     		beq	.L41
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   __IO uint32_t *regaddr;
+ 557              		.loc 1 365 1 view .LVU205
+ 558 0004 30B5     		push	{r4, r5, lr}
+ 559              	.LCFI7:
+ 560              		.cfi_def_cfa_offset 12
+ 561              		.cfi_offset 4, -12
+ 562              		.cfi_offset 5, -8
+ 563              		.cfi_offset 14, -4
+ 564 0006 8446     		mov	ip, r0
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     return HAL_ERROR;
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check the parameter */
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(hexti->Line));
+ 565              		.loc 1 379 3 is_stmt 1 view .LVU206
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* compute line register offset and line mask */
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ 566              		.loc 1 382 3 view .LVU207
+ 567              		.loc 1 382 19 is_stmt 0 view .LVU208
+ 568 0008 0468     		ldr	r4, [r0]
+ 569              		.loc 1 382 10 view .LVU209
+ 570 000a C4F30043 		ubfx	r3, r4, #16, #1
+ 571              	.LVL73:
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* compute line position */
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   linepos = (hexti->Line & EXTI_PIN_MASK);
+ 572              		.loc 1 384 3 is_stmt 1 view .LVU210
+ 573              		.loc 1 384 11 is_stmt 0 view .LVU211
+ 574 000e 04F01F0E 		and	lr, r4, #31
+ 575              	.LVL74:
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* compute line mask */
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   maskline = (1uL << linepos);
+ 576              		.loc 1 386 3 is_stmt 1 view .LVU212
+ 577              		.loc 1 386 12 is_stmt 0 view .LVU213
+ 578 0012 0122     		movs	r2, #1
+ 579 0014 02FA0EF2 		lsl	r2, r2, lr
+ 580              	.LVL75:
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* 1] Clear interrupt mode */
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+ 581              		.loc 1 389 3 is_stmt 1 view .LVU214
+ 582              		.loc 1 389 26 is_stmt 0 view .LVU215
+ 583 0018 5B01     		lsls	r3, r3, #5
+ 584              	.LVL76:
+ 585              		.loc 1 389 11 view .LVU216
+ 586 001a 03F18041 		add	r1, r3, #1073741824
+ 587 001e 01F58231 		add	r1, r1, #66560
+ 588              	.LVL77:
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regval = (*regaddr & ~maskline);
+ 589              		.loc 1 390 3 is_stmt 1 view .LVU217
+ 590              		.loc 1 390 13 is_stmt 0 view .LVU218
+ARM GAS  /tmp/ccx3buCY.s 			page 19
+
+
+ 591 0022 0868     		ldr	r0, [r1]
+ 592              	.LVL78:
+ 593              		.loc 1 390 24 view .LVU219
+ 594 0024 D543     		mvns	r5, r2
+ 595              		.loc 1 390 10 view .LVU220
+ 596 0026 20EA0200 		bic	r0, r0, r2
+ 597              	.LVL79:
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *regaddr = regval;
+ 598              		.loc 1 391 3 is_stmt 1 view .LVU221
+ 599              		.loc 1 391 12 is_stmt 0 view .LVU222
+ 600 002a 0860     		str	r0, [r1]
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* 2] Clear event mode */
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+ 601              		.loc 1 394 3 is_stmt 1 view .LVU223
+ 602              		.loc 1 394 11 is_stmt 0 view .LVU224
+ 603 002c 1848     		ldr	r0, .L49
+ 604              	.LVL80:
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regval = (*regaddr & ~maskline);
+ 605              		.loc 1 395 3 is_stmt 1 view .LVU225
+ 606              		.loc 1 395 13 is_stmt 0 view .LVU226
+ 607 002e 1958     		ldr	r1, [r3, r0]
+ 608              	.LVL81:
+ 609              		.loc 1 395 10 view .LVU227
+ 610 0030 21EA0202 		bic	r2, r1, r2
+ 611              	.LVL82:
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *regaddr = regval;
+ 612              		.loc 1 396 3 is_stmt 1 view .LVU228
+ 613              		.loc 1 396 12 is_stmt 0 view .LVU229
+ 614 0034 1A50     		str	r2, [r3, r0]
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* 3] Clear triggers in case of configurable lines */
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   if ((hexti->Line & EXTI_CONFIG) != 0x00u)
+ 615              		.loc 1 399 3 is_stmt 1 view .LVU230
+ 616              		.loc 1 399 13 is_stmt 0 view .LVU231
+ 617 0036 DCF80020 		ldr	r2, [ip]
+ 618              	.LVL83:
+ 619              		.loc 1 399 6 view .LVU232
+ 620 003a 12F0007F 		tst	r2, #33554432
+ 621 003e 24D0     		beq	.L42
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ 622              		.loc 1 401 5 is_stmt 1 view .LVU233
+ 623              		.loc 1 401 13 is_stmt 0 view .LVU234
+ 624 0040 1449     		ldr	r1, .L49+4
+ 625              	.LVL84:
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regval = (*regaddr & ~maskline);
+ 626              		.loc 1 402 5 is_stmt 1 view .LVU235
+ 627              		.loc 1 402 15 is_stmt 0 view .LVU236
+ 628 0042 5A58     		ldr	r2, [r3, r1]
+ 629              		.loc 1 402 12 view .LVU237
+ 630 0044 2A40     		ands	r2, r2, r5
+ 631              	.LVL85:
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     *regaddr = regval;
+ 632              		.loc 1 403 5 is_stmt 1 view .LVU238
+ 633              		.loc 1 403 14 is_stmt 0 view .LVU239
+ 634 0046 5A50     		str	r2, [r3, r1]
+ARM GAS  /tmp/ccx3buCY.s 			page 20
+
+
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ 635              		.loc 1 405 5 is_stmt 1 view .LVU240
+ 636              		.loc 1 405 13 is_stmt 0 view .LVU241
+ 637 0048 134A     		ldr	r2, .L49+8
+ 638              	.LVL86:
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     regval = (*regaddr & ~maskline);
+ 639              		.loc 1 406 5 is_stmt 1 view .LVU242
+ 640              		.loc 1 406 15 is_stmt 0 view .LVU243
+ 641 004a 9958     		ldr	r1, [r3, r2]
+ 642              	.LVL87:
+ 643              		.loc 1 406 12 view .LVU244
+ 644 004c 0D40     		ands	r5, r5, r1
+ 645              	.LVL88:
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     *regaddr = regval;
+ 646              		.loc 1 407 5 is_stmt 1 view .LVU245
+ 647              		.loc 1 407 14 is_stmt 0 view .LVU246
+ 648 004e 9D50     		str	r5, [r3, r2]
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Get Gpio port selection for gpio lines */
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+ 649              		.loc 1 410 5 is_stmt 1 view .LVU247
+ 650              		.loc 1 410 15 is_stmt 0 view .LVU248
+ 651 0050 DCF80030 		ldr	r3, [ip]
+ 652              	.LVL89:
+ 653              		.loc 1 410 22 view .LVU249
+ 654 0054 03F0C063 		and	r3, r3, #100663296
+ 655              		.loc 1 410 8 view .LVU250
+ 656 0058 B3F1C06F 		cmp	r3, #100663296
+ 657 005c 01D0     		beq	.L48
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     {
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       assert_param(IS_EXTI_GPIO_PIN(linepos));
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval = SYSCFG->EXTICR[linepos >> 2u];
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   return HAL_OK;
+ 658              		.loc 1 420 10 view .LVU251
+ 659 005e 0020     		movs	r0, #0
+ 660 0060 14E0     		b	.L40
+ 661              	.L48:
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 662              		.loc 1 412 7 is_stmt 1 view .LVU252
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 663              		.loc 1 414 7 view .LVU253
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 664              		.loc 1 414 39 is_stmt 0 view .LVU254
+ 665 0062 4FEA9E0E 		lsr	lr, lr, #2
+ 666              	.LVL90:
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 667              		.loc 1 414 14 view .LVU255
+ 668 0066 0D49     		ldr	r1, .L49+12
+ 669 0068 0EF1020E 		add	lr, lr, #2
+ 670 006c 51F82E30 		ldr	r3, [r1, lr, lsl #2]
+ARM GAS  /tmp/ccx3buCY.s 			page 21
+
+
+ 671              	.LVL91:
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 672              		.loc 1 415 7 is_stmt 1 view .LVU256
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 673              		.loc 1 415 80 is_stmt 0 view .LVU257
+ 674 0070 04F00304 		and	r4, r4, #3
+ 675              	.LVL92:
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 676              		.loc 1 415 69 view .LVU258
+ 677 0074 A400     		lsls	r4, r4, #2
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 678              		.loc 1 415 40 view .LVU259
+ 679 0076 0722     		movs	r2, #7
+ 680 0078 A240     		lsls	r2, r2, r4
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 681              		.loc 1 415 14 view .LVU260
+ 682 007a 23EA0203 		bic	r3, r3, r2
+ 683              	.LVL93:
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 684              		.loc 1 416 7 is_stmt 1 view .LVU261
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 685              		.loc 1 416 37 is_stmt 0 view .LVU262
+ 686 007e 41F82E30 		str	r3, [r1, lr, lsl #2]
+ 687              		.loc 1 420 10 view .LVU263
+ 688 0082 0020     		movs	r0, #0
+ 689 0084 02E0     		b	.L40
+ 690              	.LVL94:
+ 691              	.L41:
+ 692              	.LCFI8:
+ 693              		.cfi_def_cfa_offset 0
+ 694              		.cfi_restore 4
+ 695              		.cfi_restore 5
+ 696              		.cfi_restore 14
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 697              		.loc 1 375 12 view .LVU264
+ 698 0086 0120     		movs	r0, #1
+ 699              	.LVL95:
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** }
+ 700              		.loc 1 421 1 view .LVU265
+ 701 0088 7047     		bx	lr
+ 702              	.LVL96:
+ 703              	.L42:
+ 704              	.LCFI9:
+ 705              		.cfi_def_cfa_offset 12
+ 706              		.cfi_offset 4, -12
+ 707              		.cfi_offset 5, -8
+ 708              		.cfi_offset 14, -4
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** }
+ 709              		.loc 1 420 10 view .LVU266
+ 710 008a 0020     		movs	r0, #0
+ 711              	.LVL97:
+ 712              	.L40:
+ 713              		.loc 1 421 1 view .LVU267
+ 714 008c 30BD     		pop	{r4, r5, pc}
+ 715              	.L50:
+ 716 008e 00BF     		.align	2
+ 717              	.L49:
+ARM GAS  /tmp/ccx3buCY.s 			page 22
+
+
+ 718 0090 04040140 		.word	1073808388
+ 719 0094 08040140 		.word	1073808392
+ 720 0098 0C040140 		.word	1073808396
+ 721 009c 00000140 		.word	1073807360
+ 722              		.cfi_endproc
+ 723              	.LFE331:
+ 725              		.section	.text.HAL_EXTI_RegisterCallback,"ax",%progbits
+ 726              		.align	1
+ 727              		.global	HAL_EXTI_RegisterCallback
+ 728              		.syntax unified
+ 729              		.thumb
+ 730              		.thumb_func
+ 732              	HAL_EXTI_RegisterCallback:
+ 733              	.LVL98:
+ 734              	.LFB332:
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /**
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @brief  Register callback for a dedicated Exti line.
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  CallbackID User callback identifier.
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  pPendingCbfn function pointer to be stored as callback.
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @retval HAL Status.
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef Callb
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** {
+ 735              		.loc 1 433 1 is_stmt 1 view -0
+ 736              		.cfi_startproc
+ 737              		@ args = 0, pretend = 0, frame = 0
+ 738              		@ frame_needed = 0, uses_anonymous_args = 0
+ 739              		@ link register save eliminated.
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 740              		.loc 1 434 3 view .LVU269
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check the parameters */
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   assert_param(IS_EXTI_CB(CallbackID));
+ 741              		.loc 1 437 3 view .LVU270
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   switch (CallbackID)
+ 742              		.loc 1 439 3 view .LVU271
+ 743 0000 11B9     		cbnz	r1, .L52
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* set common callback */
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     case  HAL_EXTI_COMMON_CB_ID:
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       hexti->PendingCallback = pPendingCbfn;
+ 744              		.loc 1 443 7 view .LVU272
+ 745              		.loc 1 443 30 is_stmt 0 view .LVU273
+ 746 0002 4260     		str	r2, [r0, #4]
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       break;
+ 747              		.loc 1 444 7 is_stmt 1 view .LVU274
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 748              		.loc 1 434 21 is_stmt 0 view .LVU275
+ 749 0004 0846     		mov	r0, r1
+ 750              	.LVL99:
+ 751              		.loc 1 444 7 view .LVU276
+ 752 0006 7047     		bx	lr
+ARM GAS  /tmp/ccx3buCY.s 			page 23
+
+
+ 753              	.LVL100:
+ 754              	.L52:
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     default:
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       hexti->PendingCallback = NULL;
+ 755              		.loc 1 447 7 is_stmt 1 view .LVU277
+ 756              		.loc 1 447 30 is_stmt 0 view .LVU278
+ 757 0008 0023     		movs	r3, #0
+ 758 000a 4360     		str	r3, [r0, #4]
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       status = HAL_ERROR;
+ 759              		.loc 1 448 7 is_stmt 1 view .LVU279
+ 760              	.LVL101:
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       break;
+ 761              		.loc 1 449 7 view .LVU280
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       status = HAL_ERROR;
+ 762              		.loc 1 448 14 is_stmt 0 view .LVU281
+ 763 000c 0120     		movs	r0, #1
+ 764              	.LVL102:
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   return status;
+ 765              		.loc 1 452 3 is_stmt 1 view .LVU282
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** }
+ 766              		.loc 1 453 1 is_stmt 0 view .LVU283
+ 767 000e 7047     		bx	lr
+ 768              		.cfi_endproc
+ 769              	.LFE332:
+ 771              		.section	.text.HAL_EXTI_GetHandle,"ax",%progbits
+ 772              		.align	1
+ 773              		.global	HAL_EXTI_GetHandle
+ 774              		.syntax unified
+ 775              		.thumb
+ 776              		.thumb_func
+ 778              	HAL_EXTI_GetHandle:
+ 779              	.LVL103:
+ 780              	.LFB333:
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /**
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @brief  Store line number as handle private field.
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  ExtiLine Exti line number.
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @retval HAL Status.
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** {
+ 781              		.loc 1 464 1 is_stmt 1 view -0
+ 782              		.cfi_startproc
+ 783              		@ args = 0, pretend = 0, frame = 0
+ 784              		@ frame_needed = 0, uses_anonymous_args = 0
+ 785              		@ link register save eliminated.
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check the parameters */
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(ExtiLine));
+ 786              		.loc 1 466 3 view .LVU285
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check null pointer */
+ARM GAS  /tmp/ccx3buCY.s 			page 24
+
+
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   if (hexti == NULL)
+ 787              		.loc 1 469 3 view .LVU286
+ 788              		.loc 1 469 6 is_stmt 0 view .LVU287
+ 789 0000 10B1     		cbz	r0, .L56
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     return HAL_ERROR;
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   else
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Store line number as handle private field */
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     hexti->Line = ExtiLine;
+ 790              		.loc 1 476 5 is_stmt 1 view .LVU288
+ 791              		.loc 1 476 17 is_stmt 0 view .LVU289
+ 792 0002 0160     		str	r1, [r0]
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     return HAL_OK;
+ 793              		.loc 1 478 5 is_stmt 1 view .LVU290
+ 794              		.loc 1 478 12 is_stmt 0 view .LVU291
+ 795 0004 0020     		movs	r0, #0
+ 796              	.LVL104:
+ 797              		.loc 1 478 12 view .LVU292
+ 798 0006 7047     		bx	lr
+ 799              	.LVL105:
+ 800              	.L56:
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 801              		.loc 1 471 12 view .LVU293
+ 802 0008 0120     		movs	r0, #1
+ 803              	.LVL106:
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** }
+ 804              		.loc 1 480 1 view .LVU294
+ 805 000a 7047     		bx	lr
+ 806              		.cfi_endproc
+ 807              	.LFE333:
+ 809              		.section	.text.HAL_EXTI_IRQHandler,"ax",%progbits
+ 810              		.align	1
+ 811              		.global	HAL_EXTI_IRQHandler
+ 812              		.syntax unified
+ 813              		.thumb
+ 814              		.thumb_func
+ 816              	HAL_EXTI_IRQHandler:
+ 817              	.LVL107:
+ 818              	.LFB334:
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /**
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @}
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group2
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *  @brief EXTI IO functions.
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** @verbatim
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****  ===============================================================================
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****                        ##### IO operation functions #####
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****  ===============================================================================
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ARM GAS  /tmp/ccx3buCY.s 			page 25
+
+
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** @endverbatim
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @{
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /**
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @brief  Handle EXTI interrupt request.
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @retval none.
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** {
+ 819              		.loc 1 505 1 is_stmt 1 view -0
+ 820              		.cfi_startproc
+ 821              		@ args = 0, pretend = 0, frame = 0
+ 822              		@ frame_needed = 0, uses_anonymous_args = 0
+ 823              		.loc 1 505 1 is_stmt 0 view .LVU296
+ 824 0000 10B5     		push	{r4, lr}
+ 825              	.LCFI10:
+ 826              		.cfi_def_cfa_offset 8
+ 827              		.cfi_offset 4, -8
+ 828              		.cfi_offset 14, -4
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   __IO uint32_t *regaddr;
+ 829              		.loc 1 506 3 is_stmt 1 view .LVU297
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t regval;
+ 830              		.loc 1 507 3 view .LVU298
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t maskline;
+ 831              		.loc 1 508 3 view .LVU299
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t offset;
+ 832              		.loc 1 509 3 view .LVU300
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Compute line register offset */
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ 833              		.loc 1 512 3 view .LVU301
+ 834              		.loc 1 512 19 is_stmt 0 view .LVU302
+ 835 0002 0368     		ldr	r3, [r0]
+ 836              		.loc 1 512 10 view .LVU303
+ 837 0004 C3F30042 		ubfx	r2, r3, #16, #1
+ 838              	.LVL108:
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* compute line mask */
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+ 839              		.loc 1 514 3 is_stmt 1 view .LVU304
+ 840              		.loc 1 514 35 is_stmt 0 view .LVU305
+ 841 0008 03F01F03 		and	r3, r3, #31
+ 842              		.loc 1 514 12 view .LVU306
+ 843 000c 0121     		movs	r1, #1
+ 844 000e 9940     		lsls	r1, r1, r3
+ 845              	.LVL109:
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Get pending bit  */
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
+ 846              		.loc 1 517 3 is_stmt 1 view .LVU307
+ 847              		.loc 1 517 25 is_stmt 0 view .LVU308
+ 848 0010 5301     		lsls	r3, r2, #5
+ 849              		.loc 1 517 11 view .LVU309
+ 850 0012 044A     		ldr	r2, .L60
+ 851              	.LVL110:
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regval = (*regaddr & maskline);
+ARM GAS  /tmp/ccx3buCY.s 			page 26
+
+
+ 852              		.loc 1 518 3 is_stmt 1 view .LVU310
+ 853              		.loc 1 518 13 is_stmt 0 view .LVU311
+ 854 0014 9C58     		ldr	r4, [r3, r2]
+ 855              	.LVL111:
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   if (regval != 0x00u)
+ 856              		.loc 1 520 3 is_stmt 1 view .LVU312
+ 857              		.loc 1 520 6 is_stmt 0 view .LVU313
+ 858 0016 0C42     		tst	r4, r1
+ 859 0018 03D0     		beq	.L57
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   {
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Clear pending bit */
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     *regaddr = maskline;
+ 860              		.loc 1 523 5 is_stmt 1 view .LVU314
+ 861              		.loc 1 523 14 is_stmt 0 view .LVU315
+ 862 001a 9950     		str	r1, [r3, r2]
+ 863              	.LVL112:
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     /* Call pending callback */
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     if (hexti->PendingCallback != NULL)
+ 864              		.loc 1 526 5 is_stmt 1 view .LVU316
+ 865              		.loc 1 526 14 is_stmt 0 view .LVU317
+ 866 001c 4368     		ldr	r3, [r0, #4]
+ 867              	.LVL113:
+ 868              		.loc 1 526 8 view .LVU318
+ 869 001e 03B1     		cbz	r3, .L57
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     {
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****       hexti->PendingCallback();
+ 870              		.loc 1 528 7 is_stmt 1 view .LVU319
+ 871 0020 9847     		blx	r3
+ 872              	.LVL114:
+ 873              	.L57:
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****     }
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   }
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** }
+ 874              		.loc 1 531 1 is_stmt 0 view .LVU320
+ 875 0022 10BD     		pop	{r4, pc}
+ 876              	.L61:
+ 877              		.loc 1 531 1 view .LVU321
+ 878              		.align	2
+ 879              	.L60:
+ 880 0024 14040140 		.word	1073808404
+ 881              		.cfi_endproc
+ 882              	.LFE334:
+ 884              		.section	.text.HAL_EXTI_GetPending,"ax",%progbits
+ 885              		.align	1
+ 886              		.global	HAL_EXTI_GetPending
+ 887              		.syntax unified
+ 888              		.thumb
+ 889              		.thumb_func
+ 891              	HAL_EXTI_GetPending:
+ 892              	.LVL115:
+ 893              	.LFB335:
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /**
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @brief  Get interrupt pending bit of a dedicated line.
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  hexti Exti handle.
+ARM GAS  /tmp/ccx3buCY.s 			page 27
+
+
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  Edge unused
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @retval 1 if interrupt is pending else 0.
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** {
+ 894              		.loc 1 540 1 is_stmt 1 view -0
+ 895              		.cfi_startproc
+ 896              		@ args = 0, pretend = 0, frame = 0
+ 897              		@ frame_needed = 0, uses_anonymous_args = 0
+ 898              		@ link register save eliminated.
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   __IO uint32_t *regaddr;
+ 899              		.loc 1 541 3 view .LVU323
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t regval;
+ 900              		.loc 1 542 3 view .LVU324
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t linepos;
+ 901              		.loc 1 543 3 view .LVU325
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t maskline;
+ 902              		.loc 1 544 3 view .LVU326
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t offset;
+ 903              		.loc 1 545 3 view .LVU327
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check parameters */
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(hexti->Line));
+ 904              		.loc 1 548 3 view .LVU328
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ 905              		.loc 1 549 3 view .LVU329
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   UNUSED(Edge);
+ 906              		.loc 1 550 3 view .LVU330
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Compute line register offset */
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ 907              		.loc 1 553 3 view .LVU331
+ 908              		.loc 1 553 19 is_stmt 0 view .LVU332
+ 909 0000 0368     		ldr	r3, [r0]
+ 910              		.loc 1 553 10 view .LVU333
+ 911 0002 C3F30041 		ubfx	r1, r3, #16, #1
+ 912              	.LVL116:
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Compute line position */
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   linepos = (hexti->Line & EXTI_PIN_MASK);
+ 913              		.loc 1 555 3 is_stmt 1 view .LVU334
+ 914              		.loc 1 555 11 is_stmt 0 view .LVU335
+ 915 0006 03F01F03 		and	r3, r3, #31
+ 916              	.LVL117:
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Compute line mask */
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   maskline = (1uL << linepos);
+ 917              		.loc 1 557 3 is_stmt 1 view .LVU336
+ 918              		.loc 1 557 12 is_stmt 0 view .LVU337
+ 919 000a 0122     		movs	r2, #1
+ 920 000c 9A40     		lsls	r2, r2, r3
+ 921              	.LVL118:
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Get pending bit */
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
+ 922              		.loc 1 560 3 is_stmt 1 view .LVU338
+ 923              		.loc 1 560 25 is_stmt 0 view .LVU339
+ 924 000e 4901     		lsls	r1, r1, #5
+ 925              	.LVL119:
+ARM GAS  /tmp/ccx3buCY.s 			page 28
+
+
+ 926              		.loc 1 560 11 view .LVU340
+ 927 0010 0248     		ldr	r0, .L63
+ 928              	.LVL120:
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* return 1 if bit is set else 0 */
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regval = ((*regaddr & maskline) >> linepos);
+ 929              		.loc 1 563 3 is_stmt 1 view .LVU341
+ 930              		.loc 1 563 14 is_stmt 0 view .LVU342
+ 931 0012 0858     		ldr	r0, [r1, r0]
+ 932              	.LVL121:
+ 933              		.loc 1 563 23 view .LVU343
+ 934 0014 1040     		ands	r0, r0, r2
+ 935              	.LVL122:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   return regval;
+ 936              		.loc 1 564 3 is_stmt 1 view .LVU344
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** }
+ 937              		.loc 1 565 1 is_stmt 0 view .LVU345
+ 938 0016 D840     		lsrs	r0, r0, r3
+ 939              	.LVL123:
+ 940              		.loc 1 565 1 view .LVU346
+ 941 0018 7047     		bx	lr
+ 942              	.L64:
+ 943 001a 00BF     		.align	2
+ 944              	.L63:
+ 945 001c 14040140 		.word	1073808404
+ 946              		.cfi_endproc
+ 947              	.LFE335:
+ 949              		.section	.text.HAL_EXTI_ClearPending,"ax",%progbits
+ 950              		.align	1
+ 951              		.global	HAL_EXTI_ClearPending
+ 952              		.syntax unified
+ 953              		.thumb
+ 954              		.thumb_func
+ 956              	HAL_EXTI_ClearPending:
+ 957              	.LVL124:
+ 958              	.LFB336:
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /**
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @brief  Clear interrupt pending bit of a dedicated line.
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  Edge unused
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @retval None.
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** {
+ 959              		.loc 1 575 1 is_stmt 1 view -0
+ 960              		.cfi_startproc
+ 961              		@ args = 0, pretend = 0, frame = 0
+ 962              		@ frame_needed = 0, uses_anonymous_args = 0
+ 963              		@ link register save eliminated.
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   __IO uint32_t *regaddr;
+ 964              		.loc 1 576 3 view .LVU348
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t maskline;
+ 965              		.loc 1 577 3 view .LVU349
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t offset;
+ 966              		.loc 1 578 3 view .LVU350
+ARM GAS  /tmp/ccx3buCY.s 			page 29
+
+
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check parameters */
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(hexti->Line));
+ 967              		.loc 1 581 3 view .LVU351
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ 968              		.loc 1 582 3 view .LVU352
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   UNUSED(Edge);
+ 969              		.loc 1 583 3 view .LVU353
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Compute line register offset */
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ 970              		.loc 1 586 3 view .LVU354
+ 971              		.loc 1 586 19 is_stmt 0 view .LVU355
+ 972 0000 0368     		ldr	r3, [r0]
+ 973              		.loc 1 586 10 view .LVU356
+ 974 0002 C3F30042 		ubfx	r2, r3, #16, #1
+ 975              	.LVL125:
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Compute line mask */
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+ 976              		.loc 1 588 3 is_stmt 1 view .LVU357
+ 977              		.loc 1 588 35 is_stmt 0 view .LVU358
+ 978 0006 03F01F03 		and	r3, r3, #31
+ 979              		.loc 1 588 12 view .LVU359
+ 980 000a 0121     		movs	r1, #1
+ 981              	.LVL126:
+ 982              		.loc 1 588 12 view .LVU360
+ 983 000c 9940     		lsls	r1, r1, r3
+ 984              	.LVL127:
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Get pending register address */
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
+ 985              		.loc 1 591 3 is_stmt 1 view .LVU361
+ 986              		.loc 1 591 25 is_stmt 0 view .LVU362
+ 987 000e 5301     		lsls	r3, r2, #5
+ 988              		.loc 1 591 11 view .LVU363
+ 989 0010 014A     		ldr	r2, .L66
+ 990              	.LVL128:
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Clear Pending bit */
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *regaddr =  maskline;
+ 991              		.loc 1 594 3 is_stmt 1 view .LVU364
+ 992              		.loc 1 594 12 is_stmt 0 view .LVU365
+ 993 0012 9950     		str	r1, [r3, r2]
+ 994              	.LVL129:
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** }
+ 995              		.loc 1 595 1 view .LVU366
+ 996 0014 7047     		bx	lr
+ 997              	.L67:
+ 998 0016 00BF     		.align	2
+ 999              	.L66:
+ 1000 0018 14040140 		.word	1073808404
+ 1001              		.cfi_endproc
+ 1002              	.LFE336:
+ 1004              		.section	.text.HAL_EXTI_GenerateSWI,"ax",%progbits
+ 1005              		.align	1
+ 1006              		.global	HAL_EXTI_GenerateSWI
+ 1007              		.syntax unified
+ARM GAS  /tmp/ccx3buCY.s 			page 30
+
+
+ 1008              		.thumb
+ 1009              		.thumb_func
+ 1011              	HAL_EXTI_GenerateSWI:
+ 1012              	.LVL130:
+ 1013              	.LFB337:
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** /**
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @brief  Generate a software interrupt for a dedicated line.
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   * @retval None.
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   */
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** {
+ 1014              		.loc 1 604 1 is_stmt 1 view -0
+ 1015              		.cfi_startproc
+ 1016              		@ args = 0, pretend = 0, frame = 0
+ 1017              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1018              		@ link register save eliminated.
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   __IO uint32_t *regaddr;
+ 1019              		.loc 1 605 3 view .LVU368
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t maskline;
+ 1020              		.loc 1 606 3 view .LVU369
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   uint32_t offset;
+ 1021              		.loc 1 607 3 view .LVU370
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* Check parameter */
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(hexti->Line));
+ 1022              		.loc 1 610 3 view .LVU371
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ 1023              		.loc 1 611 3 view .LVU372
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* compute line register offset */
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ 1024              		.loc 1 614 3 view .LVU373
+ 1025              		.loc 1 614 19 is_stmt 0 view .LVU374
+ 1026 0000 0368     		ldr	r3, [r0]
+ 1027              		.loc 1 614 10 view .LVU375
+ 1028 0002 C3F30042 		ubfx	r2, r3, #16, #1
+ 1029              	.LVL131:
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   /* compute line mask */
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+ 1030              		.loc 1 616 3 is_stmt 1 view .LVU376
+ 1031              		.loc 1 616 35 is_stmt 0 view .LVU377
+ 1032 0006 03F01F03 		and	r3, r3, #31
+ 1033              		.loc 1 616 12 view .LVU378
+ 1034 000a 0121     		movs	r1, #1
+ 1035 000c 9940     		lsls	r1, r1, r3
+ 1036              	.LVL132:
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** 
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
+ 1037              		.loc 1 618 3 is_stmt 1 view .LVU379
+ 1038              		.loc 1 618 28 is_stmt 0 view .LVU380
+ 1039 000e 5301     		lsls	r3, r2, #5
+ 1040              		.loc 1 618 11 view .LVU381
+ 1041 0010 014A     		ldr	r2, .L69
+ 1042              	.LVL133:
+ARM GAS  /tmp/ccx3buCY.s 			page 31
+
+
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ****   *regaddr = maskline;
+ 1043              		.loc 1 619 3 is_stmt 1 view .LVU382
+ 1044              		.loc 1 619 12 is_stmt 0 view .LVU383
+ 1045 0012 9950     		str	r1, [r3, r2]
+ 1046              	.LVL134:
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c **** }
+ 1047              		.loc 1 620 1 view .LVU384
+ 1048 0014 7047     		bx	lr
+ 1049              	.L70:
+ 1050 0016 00BF     		.align	2
+ 1051              	.L69:
+ 1052 0018 10040140 		.word	1073808400
+ 1053              		.cfi_endproc
+ 1054              	.LFE337:
+ 1056              		.text
+ 1057              	.Letext0:
+ 1058              		.file 2 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 1059              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 1060              		.file 4 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 1061              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h"
+ARM GAS  /tmp/ccx3buCY.s 			page 32
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_exti.c
+     /tmp/ccx3buCY.s:21     .text.HAL_EXTI_SetConfigLine:00000000 $t
+     /tmp/ccx3buCY.s:27     .text.HAL_EXTI_SetConfigLine:00000000 HAL_EXTI_SetConfigLine
+     /tmp/ccx3buCY.s:297    .text.HAL_EXTI_SetConfigLine:000000cc $d
+     /tmp/ccx3buCY.s:305    .text.HAL_EXTI_GetConfigLine:00000000 $t
+     /tmp/ccx3buCY.s:311    .text.HAL_EXTI_GetConfigLine:00000000 HAL_EXTI_GetConfigLine
+     /tmp/ccx3buCY.s:527    .text.HAL_EXTI_GetConfigLine:000000a8 $d
+     /tmp/ccx3buCY.s:535    .text.HAL_EXTI_ClearConfigLine:00000000 $t
+     /tmp/ccx3buCY.s:541    .text.HAL_EXTI_ClearConfigLine:00000000 HAL_EXTI_ClearConfigLine
+     /tmp/ccx3buCY.s:718    .text.HAL_EXTI_ClearConfigLine:00000090 $d
+     /tmp/ccx3buCY.s:726    .text.HAL_EXTI_RegisterCallback:00000000 $t
+     /tmp/ccx3buCY.s:732    .text.HAL_EXTI_RegisterCallback:00000000 HAL_EXTI_RegisterCallback
+     /tmp/ccx3buCY.s:772    .text.HAL_EXTI_GetHandle:00000000 $t
+     /tmp/ccx3buCY.s:778    .text.HAL_EXTI_GetHandle:00000000 HAL_EXTI_GetHandle
+     /tmp/ccx3buCY.s:810    .text.HAL_EXTI_IRQHandler:00000000 $t
+     /tmp/ccx3buCY.s:816    .text.HAL_EXTI_IRQHandler:00000000 HAL_EXTI_IRQHandler
+     /tmp/ccx3buCY.s:880    .text.HAL_EXTI_IRQHandler:00000024 $d
+     /tmp/ccx3buCY.s:885    .text.HAL_EXTI_GetPending:00000000 $t
+     /tmp/ccx3buCY.s:891    .text.HAL_EXTI_GetPending:00000000 HAL_EXTI_GetPending
+     /tmp/ccx3buCY.s:945    .text.HAL_EXTI_GetPending:0000001c $d
+     /tmp/ccx3buCY.s:950    .text.HAL_EXTI_ClearPending:00000000 $t
+     /tmp/ccx3buCY.s:956    .text.HAL_EXTI_ClearPending:00000000 HAL_EXTI_ClearPending
+     /tmp/ccx3buCY.s:1000   .text.HAL_EXTI_ClearPending:00000018 $d
+     /tmp/ccx3buCY.s:1005   .text.HAL_EXTI_GenerateSWI:00000000 $t
+     /tmp/ccx3buCY.s:1011   .text.HAL_EXTI_GenerateSWI:00000000 HAL_EXTI_GenerateSWI
+     /tmp/ccx3buCY.s:1052   .text.HAL_EXTI_GenerateSWI:00000018 $d
+
+NO UNDEFINED SYMBOLS
diff --git a/squeow_sw/build/stm32g4xx_hal_exti.o b/squeow_sw/build/stm32g4xx_hal_exti.o
new file mode 100644
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literal 0
HcmV?d00001

diff --git a/squeow_sw/build/stm32g4xx_hal_flash.d b/squeow_sw/build/stm32g4xx_hal_flash.d
new file mode 100644
index 0000000..67251ec
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_flash.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_flash.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_flash.lst b/squeow_sw/build/stm32g4xx_hal_flash.lst
new file mode 100644
index 0000000..ef31959
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_flash.lst
@@ -0,0 +1,3454 @@
+ARM GAS  /tmp/ccsIWRCI.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_flash.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c"
+  20              		.section	.text.FLASH_Program_DoubleWord,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	FLASH_Program_DoubleWord:
+  27              	.LVL0:
+  28              	.LFB341:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @file    stm32g4xx_hal_flash.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief   FLASH HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *          functionalities of the internal FLASH memory:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *           + Program operations functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *           + Memory Control functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *           + Peripheral Errors functions
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   @verbatim
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   ==============================================================================
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                         ##### FLASH peripheral features #####
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   ==============================================================================
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****        to the Flash memory. It implements the erase and program Flash memory operations
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****        and the read and write protection mechanisms.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   [..] The Flash memory interface accelerates code execution with a system of instruction
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****        prefetch and cache lines.
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   [..] The FLASH main features are:
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       (+) Flash memory read operations
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       (+) Flash memory program/erase operations
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       (+) Read / write protections
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       (+) Option bytes programming
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       (+) Prefetch on I-Code
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       (+) 32 cache lines of 4*64 or 2*128 bits on I-Code
+ARM GAS  /tmp/ccsIWRCI.s 			page 2
+
+
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       (+) 8 cache lines of 4*64 or 2*128 bits on D-Code
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       (+) Error code correction (ECC) : Data in flash are 72-bits word
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****           (8 bits added per double word)
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                         ##### How to use this driver #####
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   ==============================================================================
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     [..]
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       This driver provides functions and macros to configure and program the FLASH
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       memory of all STM32G4xx devices.
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       (#) Flash Memory IO Programming functions:
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                 HAL_FLASH_Lock() functions
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****            (++) Program functions: double word and fast program (full row programming)
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****            (++) There are two modes of programming :
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****             (+++) Polling mode using HAL_FLASH_Program() function
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****             (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       (#) Interrupts and flags management functions:
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****            (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****            (++) Callback functions are called when the flash operations are finished :
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                 HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                 HAL_FLASH_OperationErrorCallback()
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****            (++) Get error flag status by calling HAL_GetError()
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       (#) Option bytes management functions:
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****            (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                 HAL_FLASH_OB_Lock() functions
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****            (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                 In this case, a reset is generated
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     [..]
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       In addition to these functions, this driver includes a set of macros allowing
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       to handle the following operations:
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****        (+) Set the latency
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****        (+) Enable/Disable the prefetch buffer
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****        (+) Enable/Disable the Instruction cache and the Data cache
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****        (+) Reset the Instruction cache and the Data cache
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****        (+) Enable/Disable the Flash power-down during low-power run and sleep modes
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****        (+) Enable/Disable the Flash interrupts
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****        (+) Monitor the Flash flags status
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   @endverbatim
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   ******************************************************************************
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @attention
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * Copyright (c) 2019 STMicroelectronics.
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * All rights reserved.
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * the root directory of this software component.
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   ******************************************************************************
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /* Includes ------------------------------------------------------------------*/
+ARM GAS  /tmp/ccsIWRCI.s 			page 3
+
+
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** #include "stm32g4xx_hal.h"
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @{
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /** @defgroup FLASH FLASH
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief FLASH HAL module driver
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @{
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** #ifdef HAL_FLASH_MODULE_ENABLED
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /* Private typedef -----------------------------------------------------------*/
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /* Private defines -----------------------------------------------------------*/
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /** @defgroup FLASH_Private_Constants FLASH Private Constants
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @{
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** #define FLASH_NB_DOUBLE_WORDS_IN_ROW  32
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @}
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /* Private macros ------------------------------------------------------------*/
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /* Private variables ---------------------------------------------------------*/
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /** @defgroup FLASH_Private_Variables FLASH Private Variables
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @{
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Variable used for Program/Erase sectors under interruption
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** FLASH_ProcessTypeDef pFlash  = {.Lock = HAL_UNLOCKED,
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                                 .ErrorCode = HAL_FLASH_ERROR_NONE,
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                                 .ProcedureOnGoing = FLASH_PROC_NONE,
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                                 .Address = 0U,
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                                 .Bank = FLASH_BANK_1,
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                                 .Page = 0U,
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                                 .NbPagesToErase = 0U,
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                                 .CacheToReactivate = FLASH_CACHE_DISABLED};
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @}
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /* Private function prototypes -----------------------------------------------*/
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /** @defgroup FLASH_Private_Functions FLASH Private Functions
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @{
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** static void          FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** static void          FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @}
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /* Exported functions --------------------------------------------------------*/
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @{
+ARM GAS  /tmp/ccsIWRCI.s 			page 4
+
+
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *  @brief   Programming operation functions
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** @verbatim
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****  ===============================================================================
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                   ##### Programming operation functions #####
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****  ===============================================================================
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     [..]
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     This subsection provides a set of functions allowing to manage the FLASH
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     program operations.
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** @endverbatim
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @{
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Program double word or fast program of a row at a specified address.
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  TypeProgram Indicate the way to program at a specified address.
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *         This parameter can be a value of @ref FLASH_Type_Program.
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  Address specifies the address to be programmed.
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  Data specifies the data to be programmed.
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *         This parameter is the data for the double word program and the address where
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *         are stored the data for the row fast program.
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval HAL_Status
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status;
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t prog_bit = 0;
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Check the parameters */
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Process Locked */
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   __HAL_LOCK(&pFlash);
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Wait for last operation to be completed */
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (status == HAL_OK)
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       /* Program double-word (64-bit) at a specified address */
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       FLASH_Program_DoubleWord(Address, Data);
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       prog_bit = FLASH_CR_PG;
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       /* Fast program a 32 row double-word (64-bit) at a specified address */
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       FLASH_Program_Fast(Address, (uint32_t)Data);
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ARM GAS  /tmp/ccsIWRCI.s 			page 5
+
+
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       /* If it is the last row, the bit will be cleared at the end of the operation */
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         prog_bit = FLASH_CR_FSTPG;
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     else
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       /* Nothing to do */
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Wait for last operation to be completed */
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* If the program operation is completed, disable the PG or FSTPG Bit */
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     if (prog_bit != 0U)
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       CLEAR_BIT(FLASH->CR, prog_bit);
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Process Unlocked */
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   __HAL_UNLOCK(&pFlash);
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* return status */
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   return status;
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Program double word or fast program of a row at a specified address with interrupt enab
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  TypeProgram Indicate the way to program at a specified address.
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *         This parameter can be a value of @ref FLASH_Type_Program.
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  Address specifies the address to be programmed.
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  Data specifies the data to be programmed.
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *         This parameter is the data for the double word program and the address where
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *         are stored the data for the row fast program.
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval HAL_Status
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status;
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Check the parameters */
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Process Locked */
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   __HAL_LOCK(&pFlash);
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Reset error code */
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Wait for last operation to be completed */
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (status != HAL_OK)
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ARM GAS  /tmp/ccsIWRCI.s 			page 6
+
+
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Process Unlocked */
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     __HAL_UNLOCK(&pFlash);
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   else
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Set internal variables used by the IRQ handler */
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     else
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     pFlash.Address = Address;
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Enable End of Operation and Error interrupts */
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       /* Program double-word (64-bit) at a specified address */
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       FLASH_Program_DoubleWord(Address, Data);
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       /* Fast program a 32 row double-word (64-bit) at a specified address */
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       FLASH_Program_Fast(Address, (uint32_t)Data);
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     else
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       /* Nothing to do */
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   return status;
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Handle FLASH interrupt request.
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval None
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** void HAL_FLASH_IRQHandler(void)
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t tmp_page;
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t error;
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   FLASH_ProcedureTypeDef procedure;
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** #if defined (FLASH_OPTR_DBANK)
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** #endif
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Disable the FSTPG Bit only if it is the last row programmed */
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ARM GAS  /tmp/ccsIWRCI.s 			page 7
+
+
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Check FLASH operation error flags */
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (error != 0U)
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Save the error code */
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     pFlash.ErrorCode |= error;
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Clear error programming flags */
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     __HAL_FLASH_CLEAR_FLAG(error);
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Flush the caches to be sure of the data consistency */
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     FLASH_FlushCaches() ;
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* FLASH error interrupt user callback */
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     procedure = pFlash.ProcedureOnGoing;
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     if (procedure == FLASH_PROC_PAGE_ERASE)
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       HAL_FLASH_OperationErrorCallback(pFlash.Page);
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     else if (procedure == FLASH_PROC_MASS_ERASE)
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       HAL_FLASH_OperationErrorCallback(pFlash.Bank);
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     else if ((procedure == FLASH_PROC_PROGRAM) ||
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****              (procedure == FLASH_PROC_PROGRAM_LAST))
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       HAL_FLASH_OperationErrorCallback(pFlash.Address);
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     else
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       /* Nothing to do */
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /*Stop the procedure ongoing*/
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Check FLASH End of Operation flag  */
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Clear FLASH End of Operation pending bit */
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       /* Nb of pages to erased can be decreased */
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       pFlash.NbPagesToErase--;
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       /* Check if there are still pages to erase*/
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       if (pFlash.NbPagesToErase != 0U)
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         /* Indicate user which page has been erased*/
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         HAL_FLASH_EndOfOperationCallback(pFlash.Page);
+ARM GAS  /tmp/ccsIWRCI.s 			page 8
+
+
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         /* Increment page number */
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         pFlash.Page++;
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         tmp_page = pFlash.Page;
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         FLASH_PageErase(tmp_page, pFlash.Bank);
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       else
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         /* No more pages to Erase */
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         /* Reset Address and stop Erase pages procedure */
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         pFlash.Page = 0xFFFFFFFFU;
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         /* Flush the caches to be sure of the data consistency */
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         FLASH_FlushCaches() ;
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         /* FLASH EOP interrupt user callback */
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         HAL_FLASH_EndOfOperationCallback(pFlash.Page);
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     else
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       /* Flush the caches to be sure of the data consistency */
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       FLASH_FlushCaches() ;
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       procedure = pFlash.ProcedureOnGoing;
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       if (procedure == FLASH_PROC_MASS_ERASE)
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         /* MassErase ended. Return the selected bank */
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         /* FLASH EOP interrupt user callback */
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       else if ((procedure == FLASH_PROC_PROGRAM) ||
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                (procedure == FLASH_PROC_PROGRAM_LAST))
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         /* Program ended. Return the selected address */
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         /* FLASH EOP interrupt user callback */
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       else
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         /* Nothing to do */
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       /*Clear the procedure ongoing*/
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Disable End of Operation and Error interrupts */
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Process Unlocked */
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     __HAL_UNLOCK(&pFlash);
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ARM GAS  /tmp/ccsIWRCI.s 			page 9
+
+
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  FLASH end of operation interrupt callback.
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure:
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *           @arg Mass Erase: Bank number which has been requested to erase
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *           @arg Page Erase: Page which has been erased
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *                            (if 0xFFFFFFFF, it means that all the selected pages have been erase
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *           @arg Program: Address which was selected for data program
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval None
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Prevent unused argument(s) compilation warning */
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   UNUSED(ReturnValue);
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****    */
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  FLASH operation error interrupt callback.
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure:
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *           @arg Mass Erase: Bank number which has been requested to erase
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *           @arg Page Erase: Page number which returned an error
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *           @arg Program: Address which was selected for data program
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval None
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Prevent unused argument(s) compilation warning */
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   UNUSED(ReturnValue);
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****    */
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @}
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief   Management functions
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** @verbatim
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****  ===============================================================================
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                       ##### Peripheral Control functions #####
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****  ===============================================================================
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     [..]
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     This subsection provides a set of functions allowing to control the FLASH
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     memory operations.
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** @endverbatim
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @{
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ARM GAS  /tmp/ccsIWRCI.s 			page 10
+
+
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Unlock the FLASH control register access.
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval HAL_Status
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Authorize the FLASH Registers access */
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* verify Flash is unlocked */
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       status = HAL_ERROR;
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   return status;
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Lock the FLASH control register access.
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval HAL_Status
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Lock(void)
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Set the LOCK Bit to lock the FLASH Registers access */
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* verify Flash is locked */
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     status = HAL_OK;
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   return status;
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Unlock the FLASH Option Bytes Registers access.
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval HAL_Status
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Authorizes the Option Byte register programming */
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+ARM GAS  /tmp/ccsIWRCI.s 			page 11
+
+
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* verify option bytes are unlocked */
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       status = HAL_ERROR;
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   return status;
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Lock the FLASH Option Bytes Registers access.
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval HAL_Status
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Verify option bytes are locked */
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     status = HAL_OK;
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   return status;
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Launch the option byte loading.
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval HAL_Status
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Set the bit to force the option byte reloading */
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Wait for last operation to be completed */
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   return (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @}
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief   Peripheral Errors functions
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** @verbatim
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****  ===============================================================================
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                 ##### Peripheral Errors functions #####
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****  ===============================================================================
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     [..]
+ARM GAS  /tmp/ccsIWRCI.s 			page 12
+
+
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     This subsection permits to get in run-time Errors of the FLASH peripheral.
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** @endverbatim
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @{
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Get the specific FLASH error flag.
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval FLASH_ErrorCode. The returned value can be:
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_NONE: No error set
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_OP: FLASH Operation error
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *            @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** uint32_t HAL_FLASH_GetError(void)
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   return pFlash.ErrorCode;
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @}
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @}
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /* Private functions ---------------------------------------------------------*/
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /** @addtogroup FLASH_Private_Functions
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @{
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Wait for a FLASH operation to complete.
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  Timeout maximum flash operation timeout.
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval HAL_Status
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****      Even if the FLASH operation fails, the BUSY flag will be reset and an error
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****      flag will be set */
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ARM GAS  /tmp/ccsIWRCI.s 			page 13
+
+
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t tickstart = HAL_GetTick();
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t error;
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     if ((HAL_GetTick() - tickstart) > Timeout)
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       return HAL_TIMEOUT;
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Check FLASH operation error flags */
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (error != 0u)
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Save the error code */
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     pFlash.ErrorCode |= error;
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Clear error programming flags */
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     __HAL_FLASH_CLEAR_FLAG(error);
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     return HAL_ERROR;
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Check FLASH End of Operation flag  */
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     /* Clear FLASH End of Operation pending bit */
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* If there is an error flag set */
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   return HAL_OK;
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Program double-word (64-bit) at a specified address.
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  Address specifies the address to be programmed.
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  Data specifies the data to be programmed.
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval None
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+  29              		.loc 1 700 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+  34              		.loc 1 700 1 is_stmt 0 view .LVU1
+  35 0000 10B4     		push	{r4}
+  36              	.LCFI0:
+  37              		.cfi_def_cfa_offset 4
+  38              		.cfi_offset 4, -4
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Check the parameters */
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+  39              		.loc 1 702 3 is_stmt 1 view .LVU2
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ARM GAS  /tmp/ccsIWRCI.s 			page 14
+
+
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Set PG bit */
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   SET_BIT(FLASH->CR, FLASH_CR_PG);
+  40              		.loc 1 705 3 view .LVU3
+  41 0002 064C     		ldr	r4, .L3
+  42 0004 6169     		ldr	r1, [r4, #20]
+  43 0006 41F00101 		orr	r1, r1, #1
+  44 000a 6161     		str	r1, [r4, #20]
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Program first word */
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *(uint32_t *)Address = (uint32_t)Data;
+  45              		.loc 1 708 3 view .LVU4
+  46              		.loc 1 708 24 is_stmt 0 view .LVU5
+  47 000c 0260     		str	r2, [r0]
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Barrier to ensure programming is performed in 2 steps, in right order
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     (independently of compiler optimization behavior) */
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   __ISB();
+  48              		.loc 1 712 3 is_stmt 1 view .LVU6
+  49              	.LBB10:
+  50              	.LBI10:
+  51              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.2.0
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     08. May 2019
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+ARM GAS  /tmp/ccsIWRCI.s 			page 15
+
+
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccsIWRCI.s 			page 16
+
+
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccsIWRCI.s 			page 17
+
+
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ARM GAS  /tmp/ccsIWRCI.s 			page 18
+
+
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccsIWRCI.s 			page 19
+
+
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccsIWRCI.s 			page 20
+
+
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/ccsIWRCI.s 			page 21
+
+
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ARM GAS  /tmp/ccsIWRCI.s 			page 22
+
+
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccsIWRCI.s 			page 23
+
+
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ARM GAS  /tmp/ccsIWRCI.s 			page 24
+
+
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ARM GAS  /tmp/ccsIWRCI.s 			page 25
+
+
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ARM GAS  /tmp/ccsIWRCI.s 			page 26
+
+
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ARM GAS  /tmp/ccsIWRCI.s 			page 27
+
+
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ARM GAS  /tmp/ccsIWRCI.s 			page 28
+
+
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccsIWRCI.s 			page 29
+
+
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 882:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 883:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 885:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 888:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ARM GAS  /tmp/ccsIWRCI.s 			page 30
+
+
+ 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 900:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 901:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 902:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 904:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 906:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 908:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 913:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 915:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 916:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 918:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 922:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 923:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 925:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 928:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 930:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 931:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 932:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+  52              		.loc 2 933 27 view .LVU7
+  53              	.LBB11:
+ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+  54              		.loc 2 935 3 view .LVU8
+  55              		.syntax unified
+  56              	@ 935 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+  57 000e BFF36F8F 		isb 0xF
+  58              	@ 0 "" 2
+  59              		.thumb
+  60              		.syntax unified
+  61              	.LBE11:
+  62              	.LBE10:
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Program second word */
+ARM GAS  /tmp/ccsIWRCI.s 			page 31
+
+
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
+  63              		.loc 1 715 3 view .LVU9
+  64              		.loc 1 715 31 is_stmt 0 view .LVU10
+  65 0012 4360     		str	r3, [r0, #4]
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+  66              		.loc 1 716 1 view .LVU11
+  67 0014 5DF8044B 		ldr	r4, [sp], #4
+  68              	.LCFI1:
+  69              		.cfi_restore 4
+  70              		.cfi_def_cfa_offset 0
+  71 0018 7047     		bx	lr
+  72              	.L4:
+  73 001a 00BF     		.align	2
+  74              	.L3:
+  75 001c 00200240 		.word	1073881088
+  76              		.cfi_endproc
+  77              	.LFE341:
+  79              		.section	.text.FLASH_Program_Fast,"ax",%progbits
+  80              		.align	1
+  81              		.syntax unified
+  82              		.thumb
+  83              		.thumb_func
+  85              	FLASH_Program_Fast:
+  86              	.LVL1:
+  87              	.LFB342:
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** /**
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @brief  Fast program a row double-word (64-bit) at a specified address.
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  Address specifies the address to be programmed.
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @param  DataAddress specifies the address where the data are stored.
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   * @retval None
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   */
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** {
+  88              		.loc 1 725 1 is_stmt 1 view -0
+  89              		.cfi_startproc
+  90              		@ args = 0, pretend = 0, frame = 0
+  91              		@ frame_needed = 0, uses_anonymous_args = 0
+  92              		@ link register save eliminated.
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint8_t row_index = (2 * FLASH_NB_DOUBLE_WORDS_IN_ROW);
+  93              		.loc 1 726 3 view .LVU13
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t *dest_addr = (uint32_t *)Address;
+  94              		.loc 1 727 3 view .LVU14
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t *src_addr = (uint32_t *)DataAddress;
+  95              		.loc 1 728 3 view .LVU15
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t primask_bit;
+  96              		.loc 1 729 3 view .LVU16
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Check the parameters */
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
+  97              		.loc 1 732 3 view .LVU17
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Set FSTPG bit */
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
+  98              		.loc 1 735 3 view .LVU18
+  99 0000 094A     		ldr	r2, .L7
+ 100 0002 5369     		ldr	r3, [r2, #20]
+ARM GAS  /tmp/ccsIWRCI.s 			page 32
+
+
+ 101 0004 43F48023 		orr	r3, r3, #262144
+ 102 0008 5361     		str	r3, [r2, #20]
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Enter critical section: Disable interrupts to avoid any interruption during the loop */
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   primask_bit = __get_PRIMASK();
+ 103              		.loc 1 738 3 view .LVU19
+ 104              	.LBB12:
+ 105              	.LBI12:
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 106              		.loc 2 449 31 view .LVU20
+ 107              	.LBB13:
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 108              		.loc 2 451 3 view .LVU21
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 109              		.loc 2 453 3 view .LVU22
+ 110              		.syntax unified
+ 111              	@ 453 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 112 000a EFF3108C 		MRS ip, primask
+ 113              	@ 0 "" 2
+ 114              	.LVL2:
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 115              		.loc 2 454 3 view .LVU23
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 116              		.loc 2 454 3 is_stmt 0 view .LVU24
+ 117              		.thumb
+ 118              		.syntax unified
+ 119              	.LBE13:
+ 120              	.LBE12:
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   __disable_irq();
+ 121              		.loc 1 739 3 is_stmt 1 view .LVU25
+ 122              	.LBB14:
+ 123              	.LBI14:
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 124              		.loc 2 207 27 view .LVU26
+ 125              	.LBB15:
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 126              		.loc 2 209 3 view .LVU27
+ 127              		.syntax unified
+ 128              	@ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 129 000e 72B6     		cpsid i
+ 130              	@ 0 "" 2
+ 131              		.thumb
+ 132              		.syntax unified
+ 133              	.LBE15:
+ 134              	.LBE14:
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t *dest_addr = (uint32_t *)Address;
+ 135              		.loc 1 726 11 is_stmt 0 view .LVU28
+ 136 0010 4023     		movs	r3, #64
+ 137              	.LVL3:
+ 138              	.L6:
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Program the double words of the row */
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   do
+ 139              		.loc 1 742 3 is_stmt 1 discriminator 1 view .LVU29
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     *dest_addr = *src_addr;
+ 140              		.loc 1 744 5 discriminator 1 view .LVU30
+ARM GAS  /tmp/ccsIWRCI.s 			page 33
+
+
+ 141              		.loc 1 744 18 is_stmt 0 discriminator 1 view .LVU31
+ 142 0012 51F8042B 		ldr	r2, [r1], #4
+ 143              	.LVL4:
+ 144              		.loc 1 744 16 discriminator 1 view .LVU32
+ 145 0016 40F8042B 		str	r2, [r0], #4
+ 146              	.LVL5:
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     dest_addr++;
+ 147              		.loc 1 745 5 is_stmt 1 discriminator 1 view .LVU33
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     src_addr++;
+ 148              		.loc 1 746 5 discriminator 1 view .LVU34
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     row_index--;
+ 149              		.loc 1 747 5 discriminator 1 view .LVU35
+ 150              		.loc 1 747 14 is_stmt 0 discriminator 1 view .LVU36
+ 151 001a 013B     		subs	r3, r3, #1
+ 152              	.LVL6:
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   while (row_index != 0U);
+ 153              		.loc 1 749 20 is_stmt 1 discriminator 1 view .LVU37
+ 154 001c 13F0FF03 		ands	r3, r3, #255
+ 155              	.LVL7:
+ 156              		.loc 1 749 20 is_stmt 0 discriminator 1 view .LVU38
+ 157 0020 F7D1     		bne	.L6
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Exit critical section: restore previous priority mask */
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   __set_PRIMASK(primask_bit);
+ 158              		.loc 1 752 3 is_stmt 1 view .LVU39
+ 159              	.LBB16:
+ 160              	.LBI16:
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 161              		.loc 2 479 27 view .LVU40
+ 162              	.LBB17:
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 163              		.loc 2 481 3 view .LVU41
+ 164              		.syntax unified
+ 165              	@ 481 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 166 0022 8CF31088 		MSR primask, ip
+ 167              	@ 0 "" 2
+ 168              		.thumb
+ 169              		.syntax unified
+ 170              	.LBE17:
+ 171              	.LBE16:
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 172              		.loc 1 753 1 is_stmt 0 view .LVU42
+ 173 0026 7047     		bx	lr
+ 174              	.L8:
+ 175              		.align	2
+ 176              	.L7:
+ 177 0028 00200240 		.word	1073881088
+ 178              		.cfi_endproc
+ 179              	.LFE342:
+ 181              		.section	.text.HAL_FLASH_EndOfOperationCallback,"ax",%progbits
+ 182              		.align	1
+ 183              		.weak	HAL_FLASH_EndOfOperationCallback
+ 184              		.syntax unified
+ 185              		.thumb
+ 186              		.thumb_func
+ 188              	HAL_FLASH_EndOfOperationCallback:
+ARM GAS  /tmp/ccsIWRCI.s 			page 34
+
+
+ 189              	.LVL8:
+ 190              	.LFB332:
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Prevent unused argument(s) compilation warning */
+ 191              		.loc 1 442 1 is_stmt 1 view -0
+ 192              		.cfi_startproc
+ 193              		@ args = 0, pretend = 0, frame = 0
+ 194              		@ frame_needed = 0, uses_anonymous_args = 0
+ 195              		@ link register save eliminated.
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 196              		.loc 1 444 3 view .LVU44
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 197              		.loc 1 449 1 is_stmt 0 view .LVU45
+ 198 0000 7047     		bx	lr
+ 199              		.cfi_endproc
+ 200              	.LFE332:
+ 202              		.section	.text.HAL_FLASH_OperationErrorCallback,"ax",%progbits
+ 203              		.align	1
+ 204              		.weak	HAL_FLASH_OperationErrorCallback
+ 205              		.syntax unified
+ 206              		.thumb
+ 207              		.thumb_func
+ 209              	HAL_FLASH_OperationErrorCallback:
+ 210              	.LVL9:
+ 211              	.LFB333:
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Prevent unused argument(s) compilation warning */
+ 212              		.loc 1 460 1 is_stmt 1 view -0
+ 213              		.cfi_startproc
+ 214              		@ args = 0, pretend = 0, frame = 0
+ 215              		@ frame_needed = 0, uses_anonymous_args = 0
+ 216              		@ link register save eliminated.
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 217              		.loc 1 462 3 view .LVU47
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 218              		.loc 1 467 1 is_stmt 0 view .LVU48
+ 219 0000 7047     		bx	lr
+ 220              		.cfi_endproc
+ 221              	.LFE333:
+ 223              		.section	.text.HAL_FLASH_IRQHandler,"ax",%progbits
+ 224              		.align	1
+ 225              		.global	HAL_FLASH_IRQHandler
+ 226              		.syntax unified
+ 227              		.thumb
+ 228              		.thumb_func
+ 230              	HAL_FLASH_IRQHandler:
+ 231              	.LFB331:
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t tmp_page;
+ 232              		.loc 1 302 1 is_stmt 1 view -0
+ 233              		.cfi_startproc
+ 234              		@ args = 0, pretend = 0, frame = 0
+ 235              		@ frame_needed = 0, uses_anonymous_args = 0
+ 236 0000 10B5     		push	{r4, lr}
+ 237              	.LCFI2:
+ 238              		.cfi_def_cfa_offset 8
+ 239              		.cfi_offset 4, -8
+ 240              		.cfi_offset 14, -4
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t error;
+ 241              		.loc 1 303 3 view .LVU50
+ARM GAS  /tmp/ccsIWRCI.s 			page 35
+
+
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   FLASH_ProcedureTypeDef procedure;
+ 242              		.loc 1 304 3 view .LVU51
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 243              		.loc 1 305 3 view .LVU52
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** #if defined (FLASH_OPTR_DBANK)
+ 244              		.loc 1 308 3 view .LVU53
+ 245 0002 454A     		ldr	r2, .L31
+ 246 0004 5369     		ldr	r3, [r2, #20]
+ 247 0006 23F4FF73 		bic	r3, r3, #510
+ 248 000a 23F00103 		bic	r3, r3, #1
+ 249 000e 5361     		str	r3, [r2, #20]
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 250              		.loc 1 314 3 view .LVU54
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 251              		.loc 1 314 13 is_stmt 0 view .LVU55
+ 252 0010 424B     		ldr	r3, .L31+4
+ 253 0012 1B7A     		ldrb	r3, [r3, #8]	@ zero_extendqisi2
+ 254 0014 DBB2     		uxtb	r3, r3
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 255              		.loc 1 314 6 view .LVU56
+ 256 0016 042B     		cmp	r3, #4
+ 257 0018 3AD0     		beq	.L25
+ 258              	.L12:
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 259              		.loc 1 320 3 is_stmt 1 view .LVU57
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 260              		.loc 1 320 17 is_stmt 0 view .LVU58
+ 261 001a 3F4B     		ldr	r3, .L31
+ 262 001c 1B69     		ldr	r3, [r3, #16]
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 263              		.loc 1 320 9 view .LVU59
+ 264 001e 4CF2FA32 		movw	r2, #50170
+ 265              	.LVL10:
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 266              		.loc 1 322 3 is_stmt 1 view .LVU60
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 267              		.loc 1 322 6 is_stmt 0 view .LVU61
+ 268 0022 1340     		ands	r3, r3, r2
+ 269              	.LVL11:
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 270              		.loc 1 322 6 view .LVU62
+ 271 0024 15D0     		beq	.L13
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 272              		.loc 1 325 5 is_stmt 1 view .LVU63
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 273              		.loc 1 325 11 is_stmt 0 view .LVU64
+ 274 0026 3D49     		ldr	r1, .L31+4
+ 275 0028 4A68     		ldr	r2, [r1, #4]
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 276              		.loc 1 325 22 view .LVU65
+ 277 002a 1A43     		orrs	r2, r2, r3
+ 278 002c 4A60     		str	r2, [r1, #4]
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 279              		.loc 1 328 5 is_stmt 1 view .LVU66
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 280              		.loc 1 328 5 view .LVU67
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ARM GAS  /tmp/ccsIWRCI.s 			page 36
+
+
+ 281              		.loc 1 328 5 view .LVU68
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 282              		.loc 1 328 5 view .LVU69
+ 283 002e 3A4A     		ldr	r2, .L31
+ 284 0030 1361     		str	r3, [r2, #16]
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 285              		.loc 1 328 5 view .LVU70
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 286              		.loc 1 331 5 view .LVU71
+ 287 0032 FFF7FEFF 		bl	FLASH_FlushCaches
+ 288              	.LVL12:
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     if (procedure == FLASH_PROC_PAGE_ERASE)
+ 289              		.loc 1 334 5 view .LVU72
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     if (procedure == FLASH_PROC_PAGE_ERASE)
+ 290              		.loc 1 334 15 is_stmt 0 view .LVU73
+ 291 0036 394B     		ldr	r3, .L31+4
+ 292 0038 1B7A     		ldrb	r3, [r3, #8]	@ zero_extendqisi2
+ 293 003a DBB2     		uxtb	r3, r3
+ 294              	.LVL13:
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 295              		.loc 1 335 5 is_stmt 1 view .LVU74
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 296              		.loc 1 335 8 is_stmt 0 view .LVU75
+ 297 003c 012B     		cmp	r3, #1
+ 298 003e 2CD0     		beq	.L26
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 299              		.loc 1 339 10 is_stmt 1 view .LVU76
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 300              		.loc 1 339 13 is_stmt 0 view .LVU77
+ 301 0040 022B     		cmp	r3, #2
+ 302 0042 2FD0     		beq	.L27
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****              (procedure == FLASH_PROC_PROGRAM_LAST))
+ 303              		.loc 1 343 10 is_stmt 1 view .LVU78
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****              (procedure == FLASH_PROC_PROGRAM_LAST))
+ 304              		.loc 1 343 48 is_stmt 0 view .LVU79
+ 305 0044 033B     		subs	r3, r3, #3
+ 306              	.LVL14:
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****              (procedure == FLASH_PROC_PROGRAM_LAST))
+ 307              		.loc 1 343 48 view .LVU80
+ 308 0046 DBB2     		uxtb	r3, r3
+ 309              	.LVL15:
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****              (procedure == FLASH_PROC_PROGRAM_LAST))
+ 310              		.loc 1 343 13 view .LVU81
+ 311 0048 012B     		cmp	r3, #1
+ 312 004a 30D9     		bls	.L28
+ 313              	.LVL16:
+ 314              	.L16:
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 315              		.loc 1 351 5 is_stmt 1 view .LVU82
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 316              		.loc 1 354 5 view .LVU83
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 317              		.loc 1 354 29 is_stmt 0 view .LVU84
+ 318 004c 334B     		ldr	r3, .L31+4
+ 319 004e 0022     		movs	r2, #0
+ 320 0050 1A72     		strb	r2, [r3, #8]
+ 321              	.LVL17:
+ARM GAS  /tmp/ccsIWRCI.s 			page 37
+
+
+ 322              	.L13:
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 323              		.loc 1 358 3 is_stmt 1 view .LVU85
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 324              		.loc 1 358 7 is_stmt 0 view .LVU86
+ 325 0052 314B     		ldr	r3, .L31
+ 326 0054 1B69     		ldr	r3, [r3, #16]
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 327              		.loc 1 358 6 view .LVU87
+ 328 0056 13F0010F 		tst	r3, #1
+ 329 005a 47D0     		beq	.L18
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 330              		.loc 1 361 5 is_stmt 1 discriminator 4 view .LVU88
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 331              		.loc 1 361 5 discriminator 4 view .LVU89
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 332              		.loc 1 361 5 discriminator 4 view .LVU90
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 333              		.loc 1 361 5 discriminator 4 view .LVU91
+ 334 005c 2E4B     		ldr	r3, .L31
+ 335 005e 0122     		movs	r2, #1
+ 336 0060 1A61     		str	r2, [r3, #16]
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 337              		.loc 1 361 5 discriminator 4 view .LVU92
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 338              		.loc 1 363 5 discriminator 4 view .LVU93
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 339              		.loc 1 363 15 is_stmt 0 discriminator 4 view .LVU94
+ 340 0062 2E4B     		ldr	r3, .L31+4
+ 341 0064 1B7A     		ldrb	r3, [r3, #8]	@ zero_extendqisi2
+ 342 0066 DBB2     		uxtb	r3, r3
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 343              		.loc 1 363 8 discriminator 4 view .LVU95
+ 344 0068 9342     		cmp	r3, r2
+ 345 006a 31D1     		bne	.L19
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 346              		.loc 1 366 7 is_stmt 1 view .LVU96
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 347              		.loc 1 366 13 is_stmt 0 view .LVU97
+ 348 006c 2B4B     		ldr	r3, .L31+4
+ 349 006e 9A69     		ldr	r2, [r3, #24]
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 350              		.loc 1 366 28 view .LVU98
+ 351 0070 013A     		subs	r2, r2, #1
+ 352 0072 9A61     		str	r2, [r3, #24]
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 353              		.loc 1 369 7 is_stmt 1 view .LVU99
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 354              		.loc 1 369 17 is_stmt 0 view .LVU100
+ 355 0074 9B69     		ldr	r3, [r3, #24]
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 356              		.loc 1 369 10 view .LVU101
+ 357 0076 FBB1     		cbz	r3, .L20
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 358              		.loc 1 372 9 is_stmt 1 view .LVU102
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 359              		.loc 1 372 48 is_stmt 0 view .LVU103
+ARM GAS  /tmp/ccsIWRCI.s 			page 38
+
+
+ 360 0078 284C     		ldr	r4, .L31+4
+ 361 007a 6069     		ldr	r0, [r4, #20]
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 362              		.loc 1 372 9 view .LVU104
+ 363 007c FFF7FEFF 		bl	HAL_FLASH_EndOfOperationCallback
+ 364              	.LVL18:
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         tmp_page = pFlash.Page;
+ 365              		.loc 1 375 9 is_stmt 1 view .LVU105
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         tmp_page = pFlash.Page;
+ 366              		.loc 1 375 15 is_stmt 0 view .LVU106
+ 367 0080 6369     		ldr	r3, [r4, #20]
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         tmp_page = pFlash.Page;
+ 368              		.loc 1 375 20 view .LVU107
+ 369 0082 0133     		adds	r3, r3, #1
+ 370 0084 6361     		str	r3, [r4, #20]
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         FLASH_PageErase(tmp_page, pFlash.Bank);
+ 371              		.loc 1 376 9 is_stmt 1 view .LVU108
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         FLASH_PageErase(tmp_page, pFlash.Bank);
+ 372              		.loc 1 376 18 is_stmt 0 view .LVU109
+ 373 0086 6069     		ldr	r0, [r4, #20]
+ 374              	.LVL19:
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 375              		.loc 1 377 9 is_stmt 1 view .LVU110
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 376              		.loc 1 377 41 is_stmt 0 view .LVU111
+ 377 0088 2169     		ldr	r1, [r4, #16]
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 378              		.loc 1 377 9 view .LVU112
+ 379 008a FFF7FEFF 		bl	FLASH_PageErase
+ 380              	.LVL20:
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 381              		.loc 1 377 9 view .LVU113
+ 382 008e 2DE0     		b	.L18
+ 383              	.LVL21:
+ 384              	.L25:
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 385              		.loc 1 316 5 is_stmt 1 view .LVU114
+ 386 0090 5369     		ldr	r3, [r2, #20]
+ 387 0092 23F48023 		bic	r3, r3, #262144
+ 388 0096 5361     		str	r3, [r2, #20]
+ 389 0098 BFE7     		b	.L12
+ 390              	.LVL22:
+ 391              	.L26:
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 392              		.loc 1 337 7 view .LVU115
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 393              		.loc 1 337 46 is_stmt 0 view .LVU116
+ 394 009a 204B     		ldr	r3, .L31+4
+ 395              	.LVL23:
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 396              		.loc 1 337 46 view .LVU117
+ 397 009c 5869     		ldr	r0, [r3, #20]
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 398              		.loc 1 337 7 view .LVU118
+ 399 009e FFF7FEFF 		bl	HAL_FLASH_OperationErrorCallback
+ 400              	.LVL24:
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ARM GAS  /tmp/ccsIWRCI.s 			page 39
+
+
+ 401              		.loc 1 337 7 view .LVU119
+ 402 00a2 D3E7     		b	.L16
+ 403              	.LVL25:
+ 404              	.L27:
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 405              		.loc 1 341 7 is_stmt 1 view .LVU120
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 406              		.loc 1 341 46 is_stmt 0 view .LVU121
+ 407 00a4 1D4B     		ldr	r3, .L31+4
+ 408              	.LVL26:
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 409              		.loc 1 341 46 view .LVU122
+ 410 00a6 1869     		ldr	r0, [r3, #16]
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 411              		.loc 1 341 7 view .LVU123
+ 412 00a8 FFF7FEFF 		bl	HAL_FLASH_OperationErrorCallback
+ 413              	.LVL27:
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 414              		.loc 1 341 7 view .LVU124
+ 415 00ac CEE7     		b	.L16
+ 416              	.LVL28:
+ 417              	.L28:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 418              		.loc 1 346 7 is_stmt 1 view .LVU125
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 419              		.loc 1 346 46 is_stmt 0 view .LVU126
+ 420 00ae 1B4B     		ldr	r3, .L31+4
+ 421 00b0 D868     		ldr	r0, [r3, #12]
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 422              		.loc 1 346 7 view .LVU127
+ 423 00b2 FFF7FEFF 		bl	HAL_FLASH_OperationErrorCallback
+ 424              	.LVL29:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 425              		.loc 1 346 7 view .LVU128
+ 426 00b6 C9E7     		b	.L16
+ 427              	.LVL30:
+ 428              	.L20:
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ 429              		.loc 1 383 9 is_stmt 1 view .LVU129
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ 430              		.loc 1 383 21 is_stmt 0 view .LVU130
+ 431 00b8 184C     		ldr	r4, .L31+4
+ 432 00ba 4FF0FF33 		mov	r3, #-1
+ 433 00be 6361     		str	r3, [r4, #20]
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 434              		.loc 1 384 9 is_stmt 1 view .LVU131
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 435              		.loc 1 384 33 is_stmt 0 view .LVU132
+ 436 00c0 0023     		movs	r3, #0
+ 437 00c2 2372     		strb	r3, [r4, #8]
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 438              		.loc 1 387 9 is_stmt 1 view .LVU133
+ 439 00c4 FFF7FEFF 		bl	FLASH_FlushCaches
+ 440              	.LVL31:
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 441              		.loc 1 390 9 view .LVU134
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ARM GAS  /tmp/ccsIWRCI.s 			page 40
+
+
+ 442              		.loc 1 390 48 is_stmt 0 view .LVU135
+ 443 00c8 6069     		ldr	r0, [r4, #20]
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 444              		.loc 1 390 9 view .LVU136
+ 445 00ca FFF7FEFF 		bl	HAL_FLASH_EndOfOperationCallback
+ 446              	.LVL32:
+ 447 00ce 0DE0     		b	.L18
+ 448              	.L19:
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 449              		.loc 1 396 7 is_stmt 1 view .LVU137
+ 450 00d0 FFF7FEFF 		bl	FLASH_FlushCaches
+ 451              	.LVL33:
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       if (procedure == FLASH_PROC_MASS_ERASE)
+ 452              		.loc 1 398 7 view .LVU138
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       if (procedure == FLASH_PROC_MASS_ERASE)
+ 453              		.loc 1 398 17 is_stmt 0 view .LVU139
+ 454 00d4 114B     		ldr	r3, .L31+4
+ 455 00d6 1B7A     		ldrb	r3, [r3, #8]	@ zero_extendqisi2
+ 456 00d8 DBB2     		uxtb	r3, r3
+ 457              	.LVL34:
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 458              		.loc 1 399 7 is_stmt 1 view .LVU140
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 459              		.loc 1 399 10 is_stmt 0 view .LVU141
+ 460 00da 022B     		cmp	r3, #2
+ 461 00dc 12D0     		beq	.L29
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                (procedure == FLASH_PROC_PROGRAM_LAST))
+ 462              		.loc 1 405 12 is_stmt 1 view .LVU142
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                (procedure == FLASH_PROC_PROGRAM_LAST))
+ 463              		.loc 1 405 50 is_stmt 0 view .LVU143
+ 464 00de 033B     		subs	r3, r3, #3
+ 465              	.LVL35:
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                (procedure == FLASH_PROC_PROGRAM_LAST))
+ 466              		.loc 1 405 50 view .LVU144
+ 467 00e0 DBB2     		uxtb	r3, r3
+ 468              	.LVL36:
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****                (procedure == FLASH_PROC_PROGRAM_LAST))
+ 469              		.loc 1 405 15 view .LVU145
+ 470 00e2 012B     		cmp	r3, #1
+ 471 00e4 13D9     		bls	.L30
+ 472              	.LVL37:
+ 473              	.L22:
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 474              		.loc 1 415 7 is_stmt 1 view .LVU146
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 475              		.loc 1 418 7 view .LVU147
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 476              		.loc 1 418 31 is_stmt 0 view .LVU148
+ 477 00e6 0D4B     		ldr	r3, .L31+4
+ 478 00e8 0022     		movs	r2, #0
+ 479 00ea 1A72     		strb	r2, [r3, #8]
+ 480              	.LVL38:
+ 481              	.L18:
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 482              		.loc 1 422 3 is_stmt 1 view .LVU149
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 483              		.loc 1 422 13 is_stmt 0 view .LVU150
+ARM GAS  /tmp/ccsIWRCI.s 			page 41
+
+
+ 484 00ec 0B4B     		ldr	r3, .L31+4
+ 485 00ee 1B7A     		ldrb	r3, [r3, #8]	@ zero_extendqisi2
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 486              		.loc 1 422 6 view .LVU151
+ 487 00f0 3BB9     		cbnz	r3, .L11
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 488              		.loc 1 425 5 is_stmt 1 discriminator 4 view .LVU152
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 489              		.loc 1 425 5 discriminator 4 view .LVU153
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 490              		.loc 1 425 5 discriminator 4 view .LVU154
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 491              		.loc 1 425 5 discriminator 4 view .LVU155
+ 492 00f2 094A     		ldr	r2, .L31
+ 493 00f4 5369     		ldr	r3, [r2, #20]
+ 494 00f6 23F04073 		bic	r3, r3, #50331648
+ 495 00fa 5361     		str	r3, [r2, #20]
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 496              		.loc 1 425 5 discriminator 4 view .LVU156
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 497              		.loc 1 428 5 discriminator 4 view .LVU157
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 498              		.loc 1 428 5 discriminator 4 view .LVU158
+ 499 00fc 074B     		ldr	r3, .L31+4
+ 500 00fe 0022     		movs	r2, #0
+ 501 0100 1A70     		strb	r2, [r3]
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 502              		.loc 1 428 5 discriminator 4 view .LVU159
+ 503              	.L11:
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 504              		.loc 1 430 1 is_stmt 0 view .LVU160
+ 505 0102 10BD     		pop	{r4, pc}
+ 506              	.LVL39:
+ 507              	.L29:
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 508              		.loc 1 403 9 is_stmt 1 view .LVU161
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 509              		.loc 1 403 48 is_stmt 0 view .LVU162
+ 510 0104 054B     		ldr	r3, .L31+4
+ 511              	.LVL40:
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 512              		.loc 1 403 48 view .LVU163
+ 513 0106 1869     		ldr	r0, [r3, #16]
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 514              		.loc 1 403 9 view .LVU164
+ 515 0108 FFF7FEFF 		bl	HAL_FLASH_EndOfOperationCallback
+ 516              	.LVL41:
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 517              		.loc 1 403 9 view .LVU165
+ 518 010c EBE7     		b	.L22
+ 519              	.LVL42:
+ 520              	.L30:
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 521              		.loc 1 410 9 is_stmt 1 view .LVU166
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 522              		.loc 1 410 48 is_stmt 0 view .LVU167
+ 523 010e 034B     		ldr	r3, .L31+4
+ARM GAS  /tmp/ccsIWRCI.s 			page 42
+
+
+ 524 0110 D868     		ldr	r0, [r3, #12]
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 525              		.loc 1 410 9 view .LVU168
+ 526 0112 FFF7FEFF 		bl	HAL_FLASH_EndOfOperationCallback
+ 527              	.LVL43:
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 528              		.loc 1 410 9 view .LVU169
+ 529 0116 E6E7     		b	.L22
+ 530              	.L32:
+ 531              		.align	2
+ 532              	.L31:
+ 533 0118 00200240 		.word	1073881088
+ 534 011c 00000000 		.word	pFlash
+ 535              		.cfi_endproc
+ 536              	.LFE331:
+ 538              		.section	.text.HAL_FLASH_Unlock,"ax",%progbits
+ 539              		.align	1
+ 540              		.global	HAL_FLASH_Unlock
+ 541              		.syntax unified
+ 542              		.thumb
+ 543              		.thumb_func
+ 545              	HAL_FLASH_Unlock:
+ 546              	.LFB334:
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 547              		.loc 1 493 1 is_stmt 1 view -0
+ 548              		.cfi_startproc
+ 549              		@ args = 0, pretend = 0, frame = 0
+ 550              		@ frame_needed = 0, uses_anonymous_args = 0
+ 551              		@ link register save eliminated.
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 552              		.loc 1 494 3 view .LVU171
+ 553              	.LVL44:
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 554              		.loc 1 496 3 view .LVU172
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 555              		.loc 1 496 7 is_stmt 0 view .LVU173
+ 556 0000 094B     		ldr	r3, .L38
+ 557 0002 5B69     		ldr	r3, [r3, #20]
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 558              		.loc 1 496 6 view .LVU174
+ 559 0004 002B     		cmp	r3, #0
+ 560 0006 01DB     		blt	.L37
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 561              		.loc 1 494 21 view .LVU175
+ 562 0008 0020     		movs	r0, #0
+ 563 000a 7047     		bx	lr
+ 564              	.L37:
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+ 565              		.loc 1 499 5 is_stmt 1 view .LVU176
+ 566 000c 064B     		ldr	r3, .L38
+ 567 000e 074A     		ldr	r2, .L38+4
+ 568 0010 9A60     		str	r2, [r3, #8]
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 569              		.loc 1 500 5 view .LVU177
+ 570 0012 02F18832 		add	r2, r2, #-2004318072
+ 571 0016 9A60     		str	r2, [r3, #8]
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ARM GAS  /tmp/ccsIWRCI.s 			page 43
+
+
+ 572              		.loc 1 503 5 view .LVU178
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 573              		.loc 1 503 9 is_stmt 0 view .LVU179
+ 574 0018 5B69     		ldr	r3, [r3, #20]
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 575              		.loc 1 503 8 view .LVU180
+ 576 001a 002B     		cmp	r3, #0
+ 577 001c 01DB     		blt	.L36
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 578              		.loc 1 494 21 view .LVU181
+ 579 001e 0020     		movs	r0, #0
+ 580 0020 7047     		bx	lr
+ 581              	.L36:
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 582              		.loc 1 505 14 view .LVU182
+ 583 0022 0120     		movs	r0, #1
+ 584              	.LVL45:
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 585              		.loc 1 509 3 is_stmt 1 view .LVU183
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 586              		.loc 1 510 1 is_stmt 0 view .LVU184
+ 587 0024 7047     		bx	lr
+ 588              	.L39:
+ 589 0026 00BF     		.align	2
+ 590              	.L38:
+ 591 0028 00200240 		.word	1073881088
+ 592 002c 23016745 		.word	1164378403
+ 593              		.cfi_endproc
+ 594              	.LFE334:
+ 596              		.section	.text.HAL_FLASH_Lock,"ax",%progbits
+ 597              		.align	1
+ 598              		.global	HAL_FLASH_Lock
+ 599              		.syntax unified
+ 600              		.thumb
+ 601              		.thumb_func
+ 603              	HAL_FLASH_Lock:
+ 604              	.LFB335:
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 605              		.loc 1 517 1 is_stmt 1 view -0
+ 606              		.cfi_startproc
+ 607              		@ args = 0, pretend = 0, frame = 0
+ 608              		@ frame_needed = 0, uses_anonymous_args = 0
+ 609              		@ link register save eliminated.
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 610              		.loc 1 518 3 view .LVU186
+ 611              	.LVL46:
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 612              		.loc 1 521 3 view .LVU187
+ 613 0000 054B     		ldr	r3, .L43
+ 614 0002 5A69     		ldr	r2, [r3, #20]
+ 615 0004 42F00042 		orr	r2, r2, #-2147483648
+ 616 0008 5A61     		str	r2, [r3, #20]
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 617              		.loc 1 524 3 view .LVU188
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 618              		.loc 1 524 7 is_stmt 0 view .LVU189
+ 619 000a 5B69     		ldr	r3, [r3, #20]
+ARM GAS  /tmp/ccsIWRCI.s 			page 44
+
+
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 620              		.loc 1 524 6 view .LVU190
+ 621 000c 002B     		cmp	r3, #0
+ 622 000e 01DB     		blt	.L42
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 623              		.loc 1 518 21 view .LVU191
+ 624 0010 0120     		movs	r0, #1
+ 625 0012 7047     		bx	lr
+ 626              	.L42:
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 627              		.loc 1 526 12 view .LVU192
+ 628 0014 0020     		movs	r0, #0
+ 629              	.LVL47:
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 630              		.loc 1 529 3 is_stmt 1 view .LVU193
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 631              		.loc 1 530 1 is_stmt 0 view .LVU194
+ 632 0016 7047     		bx	lr
+ 633              	.L44:
+ 634              		.align	2
+ 635              	.L43:
+ 636 0018 00200240 		.word	1073881088
+ 637              		.cfi_endproc
+ 638              	.LFE335:
+ 640              		.section	.text.HAL_FLASH_OB_Unlock,"ax",%progbits
+ 641              		.align	1
+ 642              		.global	HAL_FLASH_OB_Unlock
+ 643              		.syntax unified
+ 644              		.thumb
+ 645              		.thumb_func
+ 647              	HAL_FLASH_OB_Unlock:
+ 648              	.LFB336:
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 649              		.loc 1 537 1 is_stmt 1 view -0
+ 650              		.cfi_startproc
+ 651              		@ args = 0, pretend = 0, frame = 0
+ 652              		@ frame_needed = 0, uses_anonymous_args = 0
+ 653              		@ link register save eliminated.
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 654              		.loc 1 538 3 view .LVU196
+ 655              	.LVL48:
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 656              		.loc 1 540 3 view .LVU197
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 657              		.loc 1 540 7 is_stmt 0 view .LVU198
+ 658 0000 0A4B     		ldr	r3, .L49
+ 659 0002 5B69     		ldr	r3, [r3, #20]
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 660              		.loc 1 540 6 view .LVU199
+ 661 0004 13F0804F 		tst	r3, #1073741824
+ 662 0008 0BD0     		beq	.L47
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+ 663              		.loc 1 543 5 is_stmt 1 view .LVU200
+ 664 000a 084B     		ldr	r3, .L49
+ 665 000c 084A     		ldr	r2, .L49+4
+ 666 000e DA60     		str	r2, [r3, #12]
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ARM GAS  /tmp/ccsIWRCI.s 			page 45
+
+
+ 667              		.loc 1 544 5 view .LVU201
+ 668 0010 02F14432 		add	r2, r2, #1145324612
+ 669 0014 DA60     		str	r2, [r3, #12]
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 670              		.loc 1 547 5 view .LVU202
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 671              		.loc 1 547 9 is_stmt 0 view .LVU203
+ 672 0016 5B69     		ldr	r3, [r3, #20]
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 673              		.loc 1 547 8 view .LVU204
+ 674 0018 13F0804F 		tst	r3, #1073741824
+ 675 001c 03D1     		bne	.L48
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 676              		.loc 1 538 21 view .LVU205
+ 677 001e 0020     		movs	r0, #0
+ 678 0020 7047     		bx	lr
+ 679              	.L47:
+ 680 0022 0020     		movs	r0, #0
+ 681 0024 7047     		bx	lr
+ 682              	.L48:
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 683              		.loc 1 549 14 view .LVU206
+ 684 0026 0120     		movs	r0, #1
+ 685              	.LVL49:
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 686              		.loc 1 553 3 is_stmt 1 view .LVU207
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 687              		.loc 1 554 1 is_stmt 0 view .LVU208
+ 688 0028 7047     		bx	lr
+ 689              	.L50:
+ 690 002a 00BF     		.align	2
+ 691              	.L49:
+ 692 002c 00200240 		.word	1073881088
+ 693 0030 3B2A1908 		.word	135866939
+ 694              		.cfi_endproc
+ 695              	.LFE336:
+ 697              		.section	.text.HAL_FLASH_OB_Lock,"ax",%progbits
+ 698              		.align	1
+ 699              		.global	HAL_FLASH_OB_Lock
+ 700              		.syntax unified
+ 701              		.thumb
+ 702              		.thumb_func
+ 704              	HAL_FLASH_OB_Lock:
+ 705              	.LFB337:
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 706              		.loc 1 561 1 is_stmt 1 view -0
+ 707              		.cfi_startproc
+ 708              		@ args = 0, pretend = 0, frame = 0
+ 709              		@ frame_needed = 0, uses_anonymous_args = 0
+ 710              		@ link register save eliminated.
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 711              		.loc 1 562 3 view .LVU210
+ 712              	.LVL50:
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 713              		.loc 1 565 3 view .LVU211
+ 714 0000 064B     		ldr	r3, .L54
+ 715 0002 5A69     		ldr	r2, [r3, #20]
+ARM GAS  /tmp/ccsIWRCI.s 			page 46
+
+
+ 716 0004 42F08042 		orr	r2, r2, #1073741824
+ 717 0008 5A61     		str	r2, [r3, #20]
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 718              		.loc 1 568 3 view .LVU212
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 719              		.loc 1 568 7 is_stmt 0 view .LVU213
+ 720 000a 5B69     		ldr	r3, [r3, #20]
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 721              		.loc 1 568 6 view .LVU214
+ 722 000c 13F0804F 		tst	r3, #1073741824
+ 723 0010 01D1     		bne	.L53
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 724              		.loc 1 562 21 view .LVU215
+ 725 0012 0120     		movs	r0, #1
+ 726 0014 7047     		bx	lr
+ 727              	.L53:
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 728              		.loc 1 570 12 view .LVU216
+ 729 0016 0020     		movs	r0, #0
+ 730              	.LVL51:
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 731              		.loc 1 573 3 is_stmt 1 view .LVU217
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 732              		.loc 1 574 1 is_stmt 0 view .LVU218
+ 733 0018 7047     		bx	lr
+ 734              	.L55:
+ 735 001a 00BF     		.align	2
+ 736              	.L54:
+ 737 001c 00200240 		.word	1073881088
+ 738              		.cfi_endproc
+ 739              	.LFE337:
+ 741              		.section	.text.HAL_FLASH_GetError,"ax",%progbits
+ 742              		.align	1
+ 743              		.global	HAL_FLASH_GetError
+ 744              		.syntax unified
+ 745              		.thumb
+ 746              		.thumb_func
+ 748              	HAL_FLASH_GetError:
+ 749              	.LFB339:
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   return pFlash.ErrorCode;
+ 750              		.loc 1 629 1 is_stmt 1 view -0
+ 751              		.cfi_startproc
+ 752              		@ args = 0, pretend = 0, frame = 0
+ 753              		@ frame_needed = 0, uses_anonymous_args = 0
+ 754              		@ link register save eliminated.
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 755              		.loc 1 630 3 view .LVU220
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 756              		.loc 1 630 16 is_stmt 0 view .LVU221
+ 757 0000 014B     		ldr	r3, .L57
+ 758 0002 5868     		ldr	r0, [r3, #4]
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 759              		.loc 1 631 1 view .LVU222
+ 760 0004 7047     		bx	lr
+ 761              	.L58:
+ 762 0006 00BF     		.align	2
+ 763              	.L57:
+ARM GAS  /tmp/ccsIWRCI.s 			page 47
+
+
+ 764 0008 00000000 		.word	pFlash
+ 765              		.cfi_endproc
+ 766              	.LFE339:
+ 768              		.section	.text.FLASH_WaitForLastOperation,"ax",%progbits
+ 769              		.align	1
+ 770              		.global	FLASH_WaitForLastOperation
+ 771              		.syntax unified
+ 772              		.thumb
+ 773              		.thumb_func
+ 775              	FLASH_WaitForLastOperation:
+ 776              	.LVL52:
+ 777              	.LFB340:
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ 778              		.loc 1 653 1 is_stmt 1 view -0
+ 779              		.cfi_startproc
+ 780              		@ args = 0, pretend = 0, frame = 0
+ 781              		@ frame_needed = 0, uses_anonymous_args = 0
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ 782              		.loc 1 653 1 is_stmt 0 view .LVU224
+ 783 0000 38B5     		push	{r3, r4, r5, lr}
+ 784              	.LCFI3:
+ 785              		.cfi_def_cfa_offset 16
+ 786              		.cfi_offset 3, -16
+ 787              		.cfi_offset 4, -12
+ 788              		.cfi_offset 5, -8
+ 789              		.cfi_offset 14, -4
+ 790 0002 0546     		mov	r5, r0
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t error;
+ 791              		.loc 1 658 3 is_stmt 1 view .LVU225
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t error;
+ 792              		.loc 1 658 24 is_stmt 0 view .LVU226
+ 793 0004 FFF7FEFF 		bl	HAL_GetTick
+ 794              	.LVL53:
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t error;
+ 795              		.loc 1 658 24 view .LVU227
+ 796 0008 0446     		mov	r4, r0
+ 797              	.LVL54:
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 798              		.loc 1 659 3 is_stmt 1 view .LVU228
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 799              		.loc 1 661 3 view .LVU229
+ 800              	.L60:
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 801              		.loc 1 661 10 view .LVU230
+ 802 000a 134B     		ldr	r3, .L70
+ 803 000c 1B69     		ldr	r3, [r3, #16]
+ 804 000e 13F4803F 		tst	r3, #65536
+ 805 0012 06D0     		beq	.L68
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 806              		.loc 1 663 5 view .LVU231
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 807              		.loc 1 663 10 is_stmt 0 view .LVU232
+ 808 0014 FFF7FEFF 		bl	HAL_GetTick
+ 809              	.LVL55:
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 810              		.loc 1 663 24 view .LVU233
+ 811 0018 001B     		subs	r0, r0, r4
+ARM GAS  /tmp/ccsIWRCI.s 			page 48
+
+
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 812              		.loc 1 663 8 view .LVU234
+ 813 001a A842     		cmp	r0, r5
+ 814 001c F5D9     		bls	.L60
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 815              		.loc 1 665 14 view .LVU235
+ 816 001e 0320     		movs	r0, #3
+ 817              	.L61:
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 818              		.loc 1 691 1 view .LVU236
+ 819 0020 38BD     		pop	{r3, r4, r5, pc}
+ 820              	.LVL56:
+ 821              	.L68:
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (error != 0u)
+ 822              		.loc 1 670 3 is_stmt 1 view .LVU237
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (error != 0u)
+ 823              		.loc 1 670 17 is_stmt 0 view .LVU238
+ 824 0022 0D4B     		ldr	r3, .L70
+ 825 0024 1B69     		ldr	r3, [r3, #16]
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   if (error != 0u)
+ 826              		.loc 1 670 9 view .LVU239
+ 827 0026 4CF2FA32 		movw	r2, #50170
+ 828              	.LVL57:
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 829              		.loc 1 671 3 is_stmt 1 view .LVU240
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 830              		.loc 1 671 6 is_stmt 0 view .LVU241
+ 831 002a 1340     		ands	r3, r3, r2
+ 832              	.LVL58:
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 833              		.loc 1 671 6 view .LVU242
+ 834 002c 09D1     		bne	.L69
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 835              		.loc 1 683 3 is_stmt 1 view .LVU243
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 836              		.loc 1 683 7 is_stmt 0 view .LVU244
+ 837 002e 0A4B     		ldr	r3, .L70
+ 838              	.LVL59:
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 839              		.loc 1 683 7 view .LVU245
+ 840 0030 1B69     		ldr	r3, [r3, #16]
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 841              		.loc 1 683 6 view .LVU246
+ 842 0032 13F0010F 		tst	r3, #1
+ 843 0036 0CD0     		beq	.L66
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 844              		.loc 1 686 5 is_stmt 1 discriminator 4 view .LVU247
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 845              		.loc 1 686 5 discriminator 4 view .LVU248
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 846              		.loc 1 686 5 discriminator 4 view .LVU249
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 847              		.loc 1 686 5 discriminator 4 view .LVU250
+ 848 0038 074B     		ldr	r3, .L70
+ 849 003a 0122     		movs	r2, #1
+ 850 003c 1A61     		str	r2, [r3, #16]
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ARM GAS  /tmp/ccsIWRCI.s 			page 49
+
+
+ 851              		.loc 1 690 10 is_stmt 0 discriminator 4 view .LVU251
+ 852 003e 0020     		movs	r0, #0
+ 853 0040 EEE7     		b	.L61
+ 854              	.LVL60:
+ 855              	.L69:
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 856              		.loc 1 674 5 is_stmt 1 view .LVU252
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 857              		.loc 1 674 11 is_stmt 0 view .LVU253
+ 858 0042 0649     		ldr	r1, .L70+4
+ 859 0044 4A68     		ldr	r2, [r1, #4]
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 860              		.loc 1 674 22 view .LVU254
+ 861 0046 1A43     		orrs	r2, r2, r3
+ 862 0048 4A60     		str	r2, [r1, #4]
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 863              		.loc 1 677 5 is_stmt 1 view .LVU255
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 864              		.loc 1 677 5 view .LVU256
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 865              		.loc 1 677 5 view .LVU257
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 866              		.loc 1 677 5 view .LVU258
+ 867 004a 034A     		ldr	r2, .L70
+ 868 004c 1361     		str	r3, [r2, #16]
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 869              		.loc 1 677 5 view .LVU259
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 870              		.loc 1 679 5 view .LVU260
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 871              		.loc 1 679 12 is_stmt 0 view .LVU261
+ 872 004e 0120     		movs	r0, #1
+ 873 0050 E6E7     		b	.L61
+ 874              	.LVL61:
+ 875              	.L66:
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 876              		.loc 1 690 10 view .LVU262
+ 877 0052 0020     		movs	r0, #0
+ 878 0054 E4E7     		b	.L61
+ 879              	.L71:
+ 880 0056 00BF     		.align	2
+ 881              	.L70:
+ 882 0058 00200240 		.word	1073881088
+ 883 005c 00000000 		.word	pFlash
+ 884              		.cfi_endproc
+ 885              	.LFE340:
+ 887              		.section	.text.HAL_FLASH_Program,"ax",%progbits
+ 888              		.align	1
+ 889              		.global	HAL_FLASH_Program
+ 890              		.syntax unified
+ 891              		.thumb
+ 892              		.thumb_func
+ 894              	HAL_FLASH_Program:
+ 895              	.LVL62:
+ 896              	.LFB329:
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status;
+ 897              		.loc 1 174 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccsIWRCI.s 			page 50
+
+
+ 898              		.cfi_startproc
+ 899              		@ args = 0, pretend = 0, frame = 0
+ 900              		@ frame_needed = 0, uses_anonymous_args = 0
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status;
+ 901              		.loc 1 174 1 is_stmt 0 view .LVU264
+ 902 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 903              	.LCFI4:
+ 904              		.cfi_def_cfa_offset 24
+ 905              		.cfi_offset 3, -24
+ 906              		.cfi_offset 4, -20
+ 907              		.cfi_offset 5, -16
+ 908              		.cfi_offset 6, -12
+ 909              		.cfi_offset 7, -8
+ 910              		.cfi_offset 14, -4
+ 911 0002 1646     		mov	r6, r2
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   uint32_t prog_bit = 0;
+ 912              		.loc 1 175 3 is_stmt 1 view .LVU265
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 913              		.loc 1 176 3 view .LVU266
+ 914              	.LVL63:
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 915              		.loc 1 179 3 view .LVU267
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 916              		.loc 1 182 3 view .LVU268
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 917              		.loc 1 182 3 view .LVU269
+ 918 0004 1B4A     		ldr	r2, .L83
+ 919              	.LVL64:
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 920              		.loc 1 182 3 is_stmt 0 view .LVU270
+ 921 0006 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+ 922 0008 012A     		cmp	r2, #1
+ 923 000a 31D0     		beq	.L77
+ 924 000c 0446     		mov	r4, r0
+ 925 000e 0D46     		mov	r5, r1
+ 926 0010 1F46     		mov	r7, r3
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 927              		.loc 1 182 3 is_stmt 1 discriminator 2 view .LVU271
+ 928 0012 184B     		ldr	r3, .L83
+ 929 0014 0122     		movs	r2, #1
+ 930 0016 1A70     		strb	r2, [r3]
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 931              		.loc 1 182 3 discriminator 2 view .LVU272
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 932              		.loc 1 185 3 discriminator 2 view .LVU273
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 933              		.loc 1 185 12 is_stmt 0 discriminator 2 view .LVU274
+ 934 0018 4FF47A70 		mov	r0, #1000
+ 935              	.LVL65:
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 936              		.loc 1 185 12 discriminator 2 view .LVU275
+ 937 001c FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 938              	.LVL66:
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 939              		.loc 1 187 3 is_stmt 1 discriminator 2 view .LVU276
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 940              		.loc 1 187 6 is_stmt 0 discriminator 2 view .LVU277
+ARM GAS  /tmp/ccsIWRCI.s 			page 51
+
+
+ 941 0020 80B9     		cbnz	r0, .L74
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 942              		.loc 1 189 5 is_stmt 1 view .LVU278
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 943              		.loc 1 189 22 is_stmt 0 view .LVU279
+ 944 0022 144B     		ldr	r3, .L83
+ 945 0024 5860     		str	r0, [r3, #4]
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 946              		.loc 1 191 5 is_stmt 1 view .LVU280
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 947              		.loc 1 191 8 is_stmt 0 view .LVU281
+ 948 0026 8CB1     		cbz	r4, .L81
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 949              		.loc 1 197 10 is_stmt 1 view .LVU282
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 950              		.loc 1 197 54 is_stmt 0 view .LVU283
+ 951 0028 631E     		subs	r3, r4, #1
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 952              		.loc 1 197 13 view .LVU284
+ 953 002a 012B     		cmp	r3, #1
+ 954 002c 15D9     		bls	.L82
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 955              		.loc 1 176 12 view .LVU285
+ 956 002e 0024     		movs	r4, #0
+ 957              	.LVL67:
+ 958              	.L76:
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 959              		.loc 1 211 5 is_stmt 1 view .LVU286
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 960              		.loc 1 214 5 view .LVU287
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 961              		.loc 1 214 14 is_stmt 0 view .LVU288
+ 962 0030 4FF47A70 		mov	r0, #1000
+ 963 0034 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 964              	.LVL68:
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 965              		.loc 1 217 5 is_stmt 1 view .LVU289
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 966              		.loc 1 217 8 is_stmt 0 view .LVU290
+ 967 0038 24B1     		cbz	r4, .L74
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 968              		.loc 1 219 7 is_stmt 1 view .LVU291
+ 969 003a 0F4A     		ldr	r2, .L83+4
+ 970 003c 5369     		ldr	r3, [r2, #20]
+ 971 003e 23EA0403 		bic	r3, r3, r4
+ 972 0042 5361     		str	r3, [r2, #20]
+ 973              	.LVL69:
+ 974              	.L74:
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 975              		.loc 1 224 3 view .LVU292
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 976              		.loc 1 224 3 view .LVU293
+ 977 0044 0B4B     		ldr	r3, .L83
+ 978 0046 0022     		movs	r2, #0
+ 979 0048 1A70     		strb	r2, [r3]
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 980              		.loc 1 224 3 view .LVU294
+ARM GAS  /tmp/ccsIWRCI.s 			page 52
+
+
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 981              		.loc 1 227 3 view .LVU295
+ 982              	.LVL70:
+ 983              	.L73:
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 984              		.loc 1 228 1 is_stmt 0 view .LVU296
+ 985 004a F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 986              	.LVL71:
+ 987              	.L81:
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       prog_bit = FLASH_CR_PG;
+ 988              		.loc 1 194 7 is_stmt 1 view .LVU297
+ 989 004c 3246     		mov	r2, r6
+ 990 004e 3B46     		mov	r3, r7
+ 991 0050 2846     		mov	r0, r5
+ 992              	.LVL72:
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       prog_bit = FLASH_CR_PG;
+ 993              		.loc 1 194 7 is_stmt 0 view .LVU298
+ 994 0052 FFF7FEFF 		bl	FLASH_Program_DoubleWord
+ 995              	.LVL73:
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 996              		.loc 1 195 7 is_stmt 1 view .LVU299
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 997              		.loc 1 195 16 is_stmt 0 view .LVU300
+ 998 0056 0124     		movs	r4, #1
+ 999              	.LVL74:
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 1000              		.loc 1 195 16 view .LVU301
+ 1001 0058 EAE7     		b	.L76
+ 1002              	.LVL75:
+ 1003              	.L82:
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1004              		.loc 1 200 7 is_stmt 1 view .LVU302
+ 1005 005a 3146     		mov	r1, r6
+ 1006 005c 2846     		mov	r0, r5
+ 1007              	.LVL76:
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1008              		.loc 1 200 7 is_stmt 0 view .LVU303
+ 1009 005e FFF7FEFF 		bl	FLASH_Program_Fast
+ 1010              	.LVL77:
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 1011              		.loc 1 203 7 is_stmt 1 view .LVU304
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       {
+ 1012              		.loc 1 203 10 is_stmt 0 view .LVU305
+ 1013 0062 022C     		cmp	r4, #2
+ 1014 0064 01D0     		beq	.L79
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1015              		.loc 1 176 12 view .LVU306
+ 1016 0066 0024     		movs	r4, #0
+ 1017              	.LVL78:
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1018              		.loc 1 176 12 view .LVU307
+ 1019 0068 E2E7     		b	.L76
+ 1020              	.LVL79:
+ 1021              	.L79:
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 1022              		.loc 1 205 18 view .LVU308
+ 1023 006a 4FF48024 		mov	r4, #262144
+ARM GAS  /tmp/ccsIWRCI.s 			page 53
+
+
+ 1024              	.LVL80:
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****       }
+ 1025              		.loc 1 205 18 view .LVU309
+ 1026 006e DFE7     		b	.L76
+ 1027              	.LVL81:
+ 1028              	.L77:
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1029              		.loc 1 182 3 view .LVU310
+ 1030 0070 0220     		movs	r0, #2
+ 1031              	.LVL82:
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1032              		.loc 1 182 3 view .LVU311
+ 1033 0072 EAE7     		b	.L73
+ 1034              	.L84:
+ 1035              		.align	2
+ 1036              	.L83:
+ 1037 0074 00000000 		.word	pFlash
+ 1038 0078 00200240 		.word	1073881088
+ 1039              		.cfi_endproc
+ 1040              	.LFE329:
+ 1042              		.section	.text.HAL_FLASH_Program_IT,"ax",%progbits
+ 1043              		.align	1
+ 1044              		.global	HAL_FLASH_Program_IT
+ 1045              		.syntax unified
+ 1046              		.thumb
+ 1047              		.thumb_func
+ 1049              	HAL_FLASH_Program_IT:
+ 1050              	.LVL83:
+ 1051              	.LFB330:
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status;
+ 1052              		.loc 1 242 1 is_stmt 1 view -0
+ 1053              		.cfi_startproc
+ 1054              		@ args = 0, pretend = 0, frame = 0
+ 1055              		@ frame_needed = 0, uses_anonymous_args = 0
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   HAL_StatusTypeDef status;
+ 1056              		.loc 1 242 1 is_stmt 0 view .LVU313
+ 1057 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 1058              	.LCFI5:
+ 1059              		.cfi_def_cfa_offset 24
+ 1060              		.cfi_offset 4, -24
+ 1061              		.cfi_offset 5, -20
+ 1062              		.cfi_offset 6, -16
+ 1063              		.cfi_offset 7, -12
+ 1064              		.cfi_offset 8, -8
+ 1065              		.cfi_offset 14, -4
+ 1066 0004 1646     		mov	r6, r2
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1067              		.loc 1 243 3 is_stmt 1 view .LVU314
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1068              		.loc 1 246 3 view .LVU315
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1069              		.loc 1 249 3 view .LVU316
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1070              		.loc 1 249 3 view .LVU317
+ 1071 0006 1D4A     		ldr	r2, .L95
+ 1072              	.LVL84:
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ARM GAS  /tmp/ccsIWRCI.s 			page 54
+
+
+ 1073              		.loc 1 249 3 is_stmt 0 view .LVU318
+ 1074 0008 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+ 1075 000a 012A     		cmp	r2, #1
+ 1076 000c 32D0     		beq	.L91
+ 1077 000e 0446     		mov	r4, r0
+ 1078 0010 0D46     		mov	r5, r1
+ 1079 0012 1F46     		mov	r7, r3
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1080              		.loc 1 249 3 is_stmt 1 discriminator 2 view .LVU319
+ 1081 0014 194A     		ldr	r2, .L95
+ 1082 0016 0123     		movs	r3, #1
+ 1083 0018 1370     		strb	r3, [r2]
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1084              		.loc 1 249 3 discriminator 2 view .LVU320
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1085              		.loc 1 252 3 discriminator 2 view .LVU321
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1086              		.loc 1 252 20 is_stmt 0 discriminator 2 view .LVU322
+ 1087 001a 0023     		movs	r3, #0
+ 1088 001c 5360     		str	r3, [r2, #4]
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1089              		.loc 1 255 3 is_stmt 1 discriminator 2 view .LVU323
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1090              		.loc 1 255 12 is_stmt 0 discriminator 2 view .LVU324
+ 1091 001e 4FF47A70 		mov	r0, #1000
+ 1092              	.LVL85:
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1093              		.loc 1 255 12 discriminator 2 view .LVU325
+ 1094 0022 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1095              	.LVL86:
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 1096              		.loc 1 257 3 is_stmt 1 discriminator 2 view .LVU326
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   {
+ 1097              		.loc 1 257 6 is_stmt 0 discriminator 2 view .LVU327
+ 1098 0026 8046     		mov	r8, r0
+ 1099 0028 28B1     		cbz	r0, .L87
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 1100              		.loc 1 260 5 is_stmt 1 view .LVU328
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 1101              		.loc 1 260 5 view .LVU329
+ 1102 002a 144B     		ldr	r3, .L95
+ 1103 002c 0022     		movs	r2, #0
+ 1104 002e 1A70     		strb	r2, [r3]
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   }
+ 1105              		.loc 1 260 5 view .LVU330
+ 1106              	.LVL87:
+ 1107              	.L86:
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1108              		.loc 1 295 1 is_stmt 0 view .LVU331
+ 1109 0030 4046     		mov	r0, r8
+ 1110 0032 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 1111              	.LVL88:
+ 1112              	.L87:
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 1113              		.loc 1 265 5 is_stmt 1 view .LVU332
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 1114              		.loc 1 265 8 is_stmt 0 view .LVU333
+ARM GAS  /tmp/ccsIWRCI.s 			page 55
+
+
+ 1115 0036 022C     		cmp	r4, #2
+ 1116 0038 12D0     		beq	.L93
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 1117              		.loc 1 271 7 is_stmt 1 view .LVU334
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 1118              		.loc 1 271 31 is_stmt 0 view .LVU335
+ 1119 003a 104B     		ldr	r3, .L95
+ 1120 003c 0322     		movs	r2, #3
+ 1121 003e 1A72     		strb	r2, [r3, #8]
+ 1122              	.L89:
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1123              		.loc 1 273 5 is_stmt 1 view .LVU336
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1124              		.loc 1 273 20 is_stmt 0 view .LVU337
+ 1125 0040 0E4B     		ldr	r3, .L95
+ 1126 0042 DD60     		str	r5, [r3, #12]
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1127              		.loc 1 276 5 is_stmt 1 view .LVU338
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1128              		.loc 1 276 5 view .LVU339
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1129              		.loc 1 276 5 view .LVU340
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1130              		.loc 1 276 5 view .LVU341
+ 1131 0044 0E4A     		ldr	r2, .L95+4
+ 1132 0046 5369     		ldr	r3, [r2, #20]
+ 1133 0048 43F04073 		orr	r3, r3, #50331648
+ 1134 004c 5361     		str	r3, [r2, #20]
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1135              		.loc 1 276 5 view .LVU342
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 1136              		.loc 1 278 5 view .LVU343
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 1137              		.loc 1 278 8 is_stmt 0 view .LVU344
+ 1138 004e 5CB1     		cbz	r4, .L94
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 1139              		.loc 1 283 10 is_stmt 1 view .LVU345
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 1140              		.loc 1 283 54 is_stmt 0 view .LVU346
+ 1141 0050 013C     		subs	r4, r4, #1
+ 1142              	.LVL89:
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     {
+ 1143              		.loc 1 283 13 view .LVU347
+ 1144 0052 012C     		cmp	r4, #1
+ 1145 0054 ECD8     		bhi	.L86
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 1146              		.loc 1 286 7 is_stmt 1 view .LVU348
+ 1147 0056 3146     		mov	r1, r6
+ 1148 0058 2846     		mov	r0, r5
+ 1149              	.LVL90:
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 1150              		.loc 1 286 7 is_stmt 0 view .LVU349
+ 1151 005a FFF7FEFF 		bl	FLASH_Program_Fast
+ 1152              	.LVL91:
+ 1153 005e E7E7     		b	.L86
+ 1154              	.LVL92:
+ 1155              	.L93:
+ARM GAS  /tmp/ccsIWRCI.s 			page 56
+
+
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 1156              		.loc 1 267 7 is_stmt 1 view .LVU350
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 1157              		.loc 1 267 31 is_stmt 0 view .LVU351
+ 1158 0060 064B     		ldr	r3, .L95
+ 1159 0062 0422     		movs	r2, #4
+ 1160 0064 1A72     		strb	r2, [r3, #8]
+ 1161 0066 EBE7     		b	.L89
+ 1162              	.L94:
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 1163              		.loc 1 281 7 is_stmt 1 view .LVU352
+ 1164 0068 3246     		mov	r2, r6
+ 1165 006a 3B46     		mov	r3, r7
+ 1166 006c 2846     		mov	r0, r5
+ 1167              	.LVL93:
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****     }
+ 1168              		.loc 1 281 7 is_stmt 0 view .LVU353
+ 1169 006e FFF7FEFF 		bl	FLASH_Program_DoubleWord
+ 1170              	.LVL94:
+ 1171 0072 DDE7     		b	.L86
+ 1172              	.LVL95:
+ 1173              	.L91:
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1174              		.loc 1 249 3 view .LVU354
+ 1175 0074 4FF00208 		mov	r8, #2
+ 1176 0078 DAE7     		b	.L86
+ 1177              	.L96:
+ 1178 007a 00BF     		.align	2
+ 1179              	.L95:
+ 1180 007c 00000000 		.word	pFlash
+ 1181 0080 00200240 		.word	1073881088
+ 1182              		.cfi_endproc
+ 1183              	.LFE330:
+ 1185              		.section	.text.HAL_FLASH_OB_Launch,"ax",%progbits
+ 1186              		.align	1
+ 1187              		.global	HAL_FLASH_OB_Launch
+ 1188              		.syntax unified
+ 1189              		.thumb
+ 1190              		.thumb_func
+ 1192              	HAL_FLASH_OB_Launch:
+ 1193              	.LFB338:
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ****   /* Set the bit to force the option byte reloading */
+ 1194              		.loc 1 581 1 is_stmt 1 view -0
+ 1195              		.cfi_startproc
+ 1196              		@ args = 0, pretend = 0, frame = 0
+ 1197              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1198 0000 08B5     		push	{r3, lr}
+ 1199              	.LCFI6:
+ 1200              		.cfi_def_cfa_offset 8
+ 1201              		.cfi_offset 3, -8
+ 1202              		.cfi_offset 14, -4
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1203              		.loc 1 583 3 view .LVU356
+ 1204 0002 054A     		ldr	r2, .L99
+ 1205 0004 5369     		ldr	r3, [r2, #20]
+ 1206 0006 43F00063 		orr	r3, r3, #134217728
+ 1207 000a 5361     		str	r3, [r2, #20]
+ARM GAS  /tmp/ccsIWRCI.s 			page 57
+
+
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 1208              		.loc 1 586 3 view .LVU357
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** }
+ 1209              		.loc 1 586 11 is_stmt 0 view .LVU358
+ 1210 000c 4FF47A70 		mov	r0, #1000
+ 1211 0010 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1212              	.LVL96:
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c **** 
+ 1213              		.loc 1 587 1 view .LVU359
+ 1214 0014 08BD     		pop	{r3, pc}
+ 1215              	.L100:
+ 1216 0016 00BF     		.align	2
+ 1217              	.L99:
+ 1218 0018 00200240 		.word	1073881088
+ 1219              		.cfi_endproc
+ 1220              	.LFE338:
+ 1222              		.global	pFlash
+ 1223              		.section	.data.pFlash,"aw"
+ 1224              		.align	2
+ 1227              	pFlash:
+ 1228 0000 00       		.byte	0
+ 1229 0001 000000   		.space	3
+ 1230 0004 00000000 		.word	0
+ 1231 0008 00       		.byte	0
+ 1232 0009 000000   		.space	3
+ 1233 000c 00000000 		.word	0
+ 1234 0010 01000000 		.word	1
+ 1235 0014 00000000 		.word	0
+ 1236 0018 00000000 		.word	0
+ 1237 001c 00       		.byte	0
+ 1238 001d 000000   		.space	3
+ 1239              		.text
+ 1240              	.Letext0:
+ 1241              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 1242              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 1243              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 1244              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"
+ 1245              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ 1246              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h"
+ARM GAS  /tmp/ccsIWRCI.s 			page 58
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_flash.c
+     /tmp/ccsIWRCI.s:21     .text.FLASH_Program_DoubleWord:00000000 $t
+     /tmp/ccsIWRCI.s:26     .text.FLASH_Program_DoubleWord:00000000 FLASH_Program_DoubleWord
+     /tmp/ccsIWRCI.s:75     .text.FLASH_Program_DoubleWord:0000001c $d
+     /tmp/ccsIWRCI.s:80     .text.FLASH_Program_Fast:00000000 $t
+     /tmp/ccsIWRCI.s:85     .text.FLASH_Program_Fast:00000000 FLASH_Program_Fast
+     /tmp/ccsIWRCI.s:177    .text.FLASH_Program_Fast:00000028 $d
+     /tmp/ccsIWRCI.s:182    .text.HAL_FLASH_EndOfOperationCallback:00000000 $t
+     /tmp/ccsIWRCI.s:188    .text.HAL_FLASH_EndOfOperationCallback:00000000 HAL_FLASH_EndOfOperationCallback
+     /tmp/ccsIWRCI.s:203    .text.HAL_FLASH_OperationErrorCallback:00000000 $t
+     /tmp/ccsIWRCI.s:209    .text.HAL_FLASH_OperationErrorCallback:00000000 HAL_FLASH_OperationErrorCallback
+     /tmp/ccsIWRCI.s:224    .text.HAL_FLASH_IRQHandler:00000000 $t
+     /tmp/ccsIWRCI.s:230    .text.HAL_FLASH_IRQHandler:00000000 HAL_FLASH_IRQHandler
+     /tmp/ccsIWRCI.s:533    .text.HAL_FLASH_IRQHandler:00000118 $d
+     /tmp/ccsIWRCI.s:1227   .data.pFlash:00000000 pFlash
+     /tmp/ccsIWRCI.s:539    .text.HAL_FLASH_Unlock:00000000 $t
+     /tmp/ccsIWRCI.s:545    .text.HAL_FLASH_Unlock:00000000 HAL_FLASH_Unlock
+     /tmp/ccsIWRCI.s:591    .text.HAL_FLASH_Unlock:00000028 $d
+     /tmp/ccsIWRCI.s:597    .text.HAL_FLASH_Lock:00000000 $t
+     /tmp/ccsIWRCI.s:603    .text.HAL_FLASH_Lock:00000000 HAL_FLASH_Lock
+     /tmp/ccsIWRCI.s:636    .text.HAL_FLASH_Lock:00000018 $d
+     /tmp/ccsIWRCI.s:641    .text.HAL_FLASH_OB_Unlock:00000000 $t
+     /tmp/ccsIWRCI.s:647    .text.HAL_FLASH_OB_Unlock:00000000 HAL_FLASH_OB_Unlock
+     /tmp/ccsIWRCI.s:692    .text.HAL_FLASH_OB_Unlock:0000002c $d
+     /tmp/ccsIWRCI.s:698    .text.HAL_FLASH_OB_Lock:00000000 $t
+     /tmp/ccsIWRCI.s:704    .text.HAL_FLASH_OB_Lock:00000000 HAL_FLASH_OB_Lock
+     /tmp/ccsIWRCI.s:737    .text.HAL_FLASH_OB_Lock:0000001c $d
+     /tmp/ccsIWRCI.s:742    .text.HAL_FLASH_GetError:00000000 $t
+     /tmp/ccsIWRCI.s:748    .text.HAL_FLASH_GetError:00000000 HAL_FLASH_GetError
+     /tmp/ccsIWRCI.s:764    .text.HAL_FLASH_GetError:00000008 $d
+     /tmp/ccsIWRCI.s:769    .text.FLASH_WaitForLastOperation:00000000 $t
+     /tmp/ccsIWRCI.s:775    .text.FLASH_WaitForLastOperation:00000000 FLASH_WaitForLastOperation
+     /tmp/ccsIWRCI.s:882    .text.FLASH_WaitForLastOperation:00000058 $d
+     /tmp/ccsIWRCI.s:888    .text.HAL_FLASH_Program:00000000 $t
+     /tmp/ccsIWRCI.s:894    .text.HAL_FLASH_Program:00000000 HAL_FLASH_Program
+     /tmp/ccsIWRCI.s:1037   .text.HAL_FLASH_Program:00000074 $d
+     /tmp/ccsIWRCI.s:1043   .text.HAL_FLASH_Program_IT:00000000 $t
+     /tmp/ccsIWRCI.s:1049   .text.HAL_FLASH_Program_IT:00000000 HAL_FLASH_Program_IT
+     /tmp/ccsIWRCI.s:1180   .text.HAL_FLASH_Program_IT:0000007c $d
+     /tmp/ccsIWRCI.s:1186   .text.HAL_FLASH_OB_Launch:00000000 $t
+     /tmp/ccsIWRCI.s:1192   .text.HAL_FLASH_OB_Launch:00000000 HAL_FLASH_OB_Launch
+     /tmp/ccsIWRCI.s:1218   .text.HAL_FLASH_OB_Launch:00000018 $d
+     /tmp/ccsIWRCI.s:1224   .data.pFlash:00000000 $d
+
+UNDEFINED SYMBOLS
+FLASH_FlushCaches
+FLASH_PageErase
+HAL_GetTick
diff --git a/squeow_sw/build/stm32g4xx_hal_flash.o b/squeow_sw/build/stm32g4xx_hal_flash.o
new file mode 100644
index 0000000000000000000000000000000000000000..5a7e51bedf9ee2df18c5def7d1dbaac0b32f03e7
GIT binary patch
literal 18448
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diff --git a/squeow_sw/build/stm32g4xx_hal_flash_ex.d b/squeow_sw/build/stm32g4xx_hal_flash_ex.d
new file mode 100644
index 0000000..5b28f56
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_flash_ex.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_flash_ex.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_flash_ex.lst b/squeow_sw/build/stm32g4xx_hal_flash_ex.lst
new file mode 100644
index 0000000..316f1ef
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_flash_ex.lst
@@ -0,0 +1,4194 @@
+ARM GAS  /tmp/ccudk1nZ.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_flash_ex.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c"
+  20              		.section	.text.FLASH_MassErase,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	FLASH_MassErase:
+  27              	.LVL0:
+  28              	.LFB336:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @file    stm32g4xx_hal_flash_ex.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief   Extended FLASH HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *          functionalities of the FLASH extended peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *           + Extended programming operations functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   @verbatim
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   ==============================================================================
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****                    ##### Flash Extended features #####
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   ==============================================================================
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   [..] Comparing to other previous devices, the FLASH interface for STM32G4xx
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****        devices contains the following additional features
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****        (+) Capacity up to 512 Kbytes with dual bank architecture supporting read-while-write
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****            capability (RWW)
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****        (+) Dual bank 64-bits memory organization with possibility of single bank 128-bits
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****        (+) Protected areas including WRP, PCROP and Securable memory
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****                         ##### How to use this driver #####
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   ==============================================================================
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   [..] This driver provides functions to configure and program the FLASH memory
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****        of all STM32G4xx devices. It includes
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (#) Flash Memory Erase functions:
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****                 HAL_FLASH_Lock() functions
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****            (++) Erase function: Erase pages, or mass erase banks
+ARM GAS  /tmp/ccudk1nZ.s 			page 2
+
+
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****            (++) There are two modes of erase :
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****              (+++) Polling Mode using HAL_FLASHEx_Erase()
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****              (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to:
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Configure the write protection areas (WRP)
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Set the Read protection Level (RDP)
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Program the user Option Bytes
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Configure the Proprietary Code ReadOut protection areas (PCROP)
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Configure the Securable memory areas
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Configure the Boot Lock
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to:
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Get the configuration of write protection areas (WRP)
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Get the level of read protection (RDP)
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Get the value of the user Option Bytes
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Get the configuration of Proprietary Code ReadOut Protection areas (PCROP)
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Get the configuration of Securable memory areas
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Get the status of Boot Lock
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (#) Activation of Securable memory area: Use HAL_FLASHEx_EnableSecMemProtection()
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         (++) Deny the access to securable memory area
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (#) Enable or disable debugger: Use HAL_FLASHEx_EnableDebugger() or
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****           HAL_FLASHEx_DisableDebugger()
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   @endverbatim
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   ******************************************************************************
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @attention
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * Copyright (c) 2019 STMicroelectronics.
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * All rights reserved.
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * the root directory of this software component.
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   ******************************************************************************
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /* Includes ------------------------------------------------------------------*/
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #include "stm32g4xx_hal.h"
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @{
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /** @defgroup FLASHEx FLASHEx
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief FLASH Extended HAL module driver
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @{
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #ifdef HAL_FLASH_MODULE_ENABLED
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /* Private typedef -----------------------------------------------------------*/
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /* Private define ------------------------------------------------------------*/
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /* Private macro -------------------------------------------------------------*/
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /* Private variables ---------------------------------------------------------*/
+ARM GAS  /tmp/ccudk1nZ.s 			page 3
+
+
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /* Private function prototypes -----------------------------------------------*/
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @{
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static void              FLASH_MassErase(uint32_t Banks);
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRD
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static void              FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDP
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static uint32_t          FLASH_OB_GetRDP(void);
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static uint32_t          FLASH_OB_GetUser(void);
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static void              FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecMemBank, uint32_t SecMemSize);
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static void              FLASH_OB_GetSecMem(uint32_t SecMemBank, uint32_t *SecMemSize);
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig);
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static uint32_t          FLASH_OB_GetBootLock(void);
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @}
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /* Exported functions -------------------------------------------------------*/
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @{
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief   Extended IO operation functions
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** @verbatim
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****  ===============================================================================
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****                 ##### Extended programming operation functions #####
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****  ===============================================================================
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     [..]
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     This subsection provides a set of functions allowing to manage the Extended FLASH
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     programming operations Operations.
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** @endverbatim
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @{
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Perform a mass erase or erase the specified FLASH memory pages.
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         contains the configuration information for the erasing.
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param[out]  PageError pointer to variable that contains the configuration
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         information on faulty page in case of error (0xFFFFFFFF means that all
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         the pages have been correctly erased).
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval HAL_Status
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t page_index;
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Check the parameters */
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+ARM GAS  /tmp/ccudk1nZ.s 			page 4
+
+
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Process Locked */
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   __HAL_LOCK(&pFlash);
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (status == HAL_OK)
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Deactivate the cache if they are activated to avoid data misbehavior */
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         /* Disable data cache  */
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         __HAL_FLASH_DATA_CACHE_DISABLE();
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       else
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Disable data cache  */
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       __HAL_FLASH_DATA_CACHE_DISABLE();
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Mass erase to be done */
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       FLASH_MassErase(pEraseInit->Banks);
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Wait for last operation to be completed */
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* If the erase operation is completed, disable the MER1 and MER2 Bits */
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #else
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* If the erase operation is completed, disable the MER1 Bit */
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /*Initialization of PageError variable*/
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       *PageError = 0xFFFFFFFFU;
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ARM GAS  /tmp/ccudk1nZ.s 			page 5
+
+
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); pa
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         FLASH_PageErase(page_index, pEraseInit->Banks);
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         /* Wait for last operation to be completed */
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         /* If the erase operation is completed, disable the PER Bit */
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         if (status != HAL_OK)
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         {
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****           /* In case of error, stop erase procedure and return the faulty page */
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****           *PageError = page_index;
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****           break;
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         }
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Flush the caches to be sure of the data consistency */
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     FLASH_FlushCaches();
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Process Unlocked */
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   __HAL_UNLOCK(&pFlash);
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   return status;
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         contains the configuration information for the erasing.
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval HAL_Status
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Process Locked */
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   __HAL_LOCK(&pFlash);
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Check the parameters */
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Deactivate the cache if they are activated to avoid data misbehavior */
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Disable data cache  */
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       __HAL_FLASH_DATA_CACHE_DISABLE();
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else
+ARM GAS  /tmp/ccudk1nZ.s 			page 6
+
+
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Disable data cache  */
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     __HAL_FLASH_DATA_CACHE_DISABLE();
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Enable End of Operation and Error interrupts */
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   pFlash.Bank = pEraseInit->Banks;
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Mass erase to be done */
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     FLASH_MassErase(pEraseInit->Banks);
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Erase by page to be done */
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.NbPagesToErase = pEraseInit->NbPages;
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.Page = pEraseInit->Page;
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /*Erase 1st page and wait for IT */
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   return status;
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Program Option bytes.
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         contains the configuration information for the programming.
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   New option bytes configuration will be taken into account in two cases:
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval HAL_Status
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Check the parameters */
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+ARM GAS  /tmp/ccudk1nZ.s 			page 7
+
+
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Process Locked */
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   __HAL_LOCK(&pFlash);
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Write protection configuration */
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Configure of Write protection on the selected area */
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       status = HAL_ERROR;
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Read protection configuration */
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Configure the Read protection level */
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK)
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       status = HAL_ERROR;
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* User Configuration */
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Configure the user option bytes */
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK)
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       status = HAL_ERROR;
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* PCROP Configuration */
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr)
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Configure the Proprietary code readout protection */
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       if (FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         status = HAL_ERROR;
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Securable memory Configuration */
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0U)
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Configure the securable memory area */
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (FLASH_OB_SecMemConfig(pOBInit->SecBank, pOBInit->SecSize) != HAL_OK)
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       status = HAL_ERROR;
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ARM GAS  /tmp/ccudk1nZ.s 			page 8
+
+
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Boot Entry Point Configuration */
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U)
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Configure the boot unique entry point option */
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (FLASH_OB_BootLockConfig(pOBInit->BootEntryPoint) != HAL_OK)
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       status = HAL_ERROR;
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Process Unlocked */
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   __HAL_UNLOCK(&pFlash);
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   return status;
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Get the Option bytes configuration.
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that contains the
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         configuration information.
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         which area is requested for the WRP and PCROP, else no information will be returned.
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval None
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) 
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #else
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pOBInit->OptionType |= OPTIONBYTE_WRP;
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Get write protection on the selected area */
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Get Read protection level */
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   pOBInit->RDPLevel = FLASH_OB_GetRDP();
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Get the user option bytes */
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   pOBInit->USERConfig = FLASH_OB_GetUser();
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2))
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #else
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (pOBInit->PCROPConfig == FLASH_BANK_1)
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pOBInit->OptionType |= OPTIONBYTE_PCROP;
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Get the Proprietary code readout protection */
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr)
+ARM GAS  /tmp/ccudk1nZ.s 			page 9
+
+
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK;
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Get the boot entry point */
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   pOBInit->BootEntryPoint = FLASH_OB_GetBootLock();
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Get the securable memory area configuration */
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((pOBInit->SecBank == FLASH_BANK_1) || (pOBInit->SecBank == FLASH_BANK_2))
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #else
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (pOBInit->SecBank == FLASH_BANK_1)
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pOBInit->OptionType |= OPTIONBYTE_SEC;
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     FLASH_OB_GetSecMem(pOBInit->SecBank, &(pOBInit->SecSize));
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Enable the FLASH Securable Memory protection.
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  Bank: Bank to be protected
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_1: Bank1 to be protected
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_2: Bank2 to be protected (*)
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected (*)
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   (*) availability depends on devices
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval HAL Status
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank)
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Check the parameters */
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     assert_param(IS_FLASH_BANK(Bank));
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Enable the Securable Memory Protection Bit for the bank 1 if requested */
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((Bank & FLASH_BANK_1) != 0U)
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1);
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Enable the Securable Memory Protection Bit for the bank 2 if requested */
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((Bank & FLASH_BANK_2) != 0U)
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT2);
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1);
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   return HAL_OK;
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ARM GAS  /tmp/ccudk1nZ.s 			page 10
+
+
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Enable Debugger.
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   After calling this API, flash interface allow debugger intrusion.
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval None
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** void HAL_FLASHEx_EnableDebugger(void)
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   FLASH->ACR |= FLASH_ACR_DBG_SWEN;
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Disable Debugger.
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   After calling this API, Debugger is disabled: it's no more possible to
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         break, see CPU register, etc...
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval None
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** void HAL_FLASHEx_DisableDebugger(void)
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   FLASH->ACR &= ~FLASH_ACR_DBG_SWEN;
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @}
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @}
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /* Private functions ---------------------------------------------------------*/
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Functions
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @{
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Mass erase of FLASH memory.
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  Banks Banks to be erased.
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter can be one of the following values:
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_1: Bank1 to be erased
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_2: Bank2 to be erased (*)
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased (*)
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   (*) availability depends on devices
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval None
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static void FLASH_MassErase(uint32_t Banks)
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+  29              		.loc 1 534 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ARM GAS  /tmp/ccudk1nZ.s 			page 11
+
+
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Check the parameters */
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     assert_param(IS_FLASH_BANK(Banks));
+  34              		.loc 1 540 5 view .LVU1
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Set the Mass Erase Bit for the bank 1 if requested */
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((Banks & FLASH_BANK_1) != 0U)
+  35              		.loc 1 543 5 view .LVU2
+  36              		.loc 1 543 8 is_stmt 0 view .LVU3
+  37 0000 10F0010F 		tst	r0, #1
+  38 0004 04D0     		beq	.L2
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       SET_BIT(FLASH->CR, FLASH_CR_MER1);
+  39              		.loc 1 545 7 is_stmt 1 view .LVU4
+  40 0006 054A     		ldr	r2, .L3
+  41 0008 5369     		ldr	r3, [r2, #20]
+  42 000a 43F00403 		orr	r3, r3, #4
+  43 000e 5361     		str	r3, [r2, #20]
+  44              	.L2:
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Set the Mass Erase Bit for the bank 2 if requested */
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((Banks & FLASH_BANK_2) != 0U)
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       SET_BIT(FLASH->CR, FLASH_CR_MER2);
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Proceed to erase all sectors */
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   SET_BIT(FLASH->CR, FLASH_CR_STRT);
+  45              		.loc 1 564 3 view .LVU5
+  46 0010 024A     		ldr	r2, .L3
+  47 0012 5369     		ldr	r3, [r2, #20]
+  48 0014 43F48033 		orr	r3, r3, #65536
+  49 0018 5361     		str	r3, [r2, #20]
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+  50              		.loc 1 565 1 is_stmt 0 view .LVU6
+  51 001a 7047     		bx	lr
+  52              	.L4:
+  53              		.align	2
+  54              	.L3:
+  55 001c 00200240 		.word	1073881088
+  56              		.cfi_endproc
+  57              	.LFE336:
+  59              		.section	.text.FLASH_OB_GetSecMem,"ax",%progbits
+  60              		.align	1
+  61              		.syntax unified
+  62              		.thumb
+  63              		.thumb_func
+  65              	FLASH_OB_GetSecMem:
+ARM GAS  /tmp/ccudk1nZ.s 			page 12
+
+
+  66              	.LVL1:
+  67              	.LFB345:
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Erase the specified FLASH memory page.
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  Page FLASH page to erase.
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter must be a value between 0 and (max number of pages in the bank - 1).
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  Banks Bank where the page will be erased.
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter can be one of the following values:
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_1: Page in bank 1 to be erased
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_2: Page in bank 2 to be erased (*)
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   (*) availability depends on devices
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval None
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** void FLASH_PageErase(uint32_t Page, uint32_t Banks)
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Check the parameters */
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_PAGE(Page));
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((Banks & FLASH_BANK_1) != 0U)
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       SET_BIT(FLASH->CR, FLASH_CR_BKER);
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Proceed to erase the page */
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos));
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   SET_BIT(FLASH->CR, FLASH_CR_PER);
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   SET_BIT(FLASH->CR, FLASH_CR_STRT);
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Flush the instruction and data caches.
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval None
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** void FLASH_FlushCaches(void)
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Flush instruction cache  */
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((cache == FLASH_CACHE_ICACHE_ENABLED) ||
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ARM GAS  /tmp/ccudk1nZ.s 			page 13
+
+
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Disable instruction cache */
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Reset instruction cache */
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Enable instruction cache */
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Flush data cache */
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((cache == FLASH_CACHE_DCACHE_ENABLED) ||
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Reset data cache */
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     __HAL_FLASH_DATA_CACHE_RESET();
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Enable data cache */
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     __HAL_FLASH_DATA_CACHE_ENABLE();
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Reset internal variable */
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Configure the write protection area into Option Bytes.
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   When the memory read protection level is selected (RDP level = 1),
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         it is not possible to program or erase Flash memory if the CPU debug
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         features are connected (JTAG or single wire) or boot code is being
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         executed from RAM or System flash, even if WRP is not activated.
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   New option bytes configuration will be taken into account in two cases:
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  WRPArea specifies the area to be configured.
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter can be one of the following values:
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (*)
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (*)
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   (*) availability depends on devices
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  WRPStartOffset specifies the start page of the write protected area.
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter can be page number between 0 and (max number of pages in the bank - 1).
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  WRDPEndOffset specifies the end page of the write protected area.
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter can be page number between WRPStartOffset and (max number of pages in th
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval HAL_Status
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRD
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Check the parameters */
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_OB_WRPAREA(WRPArea));
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_PAGE(WRPStartOffset));
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_PAGE(WRDPEndOffset));
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ARM GAS  /tmp/ccudk1nZ.s 			page 14
+
+
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (status == HAL_OK)
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Configure the write protected area */
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (WRPArea == OB_WRPAREA_BANK1_AREAA)
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       FLASH->WRP1AR = ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset);
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset);
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       FLASH->WRP2AR = ((WRDPEndOffset << FLASH_WRP2AR_WRP2A_END_Pos) | WRPStartOffset);
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       FLASH->WRP2BR = ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset);
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Nothing to do */
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Set OPTSTRT Bit */
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Wait for last operation to be completed */
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   return status;
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Set the read protection level into Option Bytes.
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   New option bytes configuration will be taken into account in two cases:
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         to go back to level 1 or 0 !!!
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  RDPLevel specifies the read protection level.
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter can be one of the following values:
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_RDP_LEVEL_0: No protection
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_RDP_LEVEL_1: Memory Read protection
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_RDP_LEVEL_2: Full chip protection
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval HAL_Status
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ARM GAS  /tmp/ccudk1nZ.s 			page 15
+
+
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Check the parameters */
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_OB_RDP_LEVEL(RDPLevel));
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (status == HAL_OK)
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Configure the RDP level in the option bytes register */
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Set OPTSTRT Bit */
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Wait for last operation to be completed */
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   return status;
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Program the FLASH User Option Bytes.
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   New option bytes configuration will be taken into account in two cases:
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  UserType The FLASH User Option Bytes to be modified.
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter can be a combination of @ref FLASH_OB_USER_Type.
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  UserConfig The selected User Option Bytes values:
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY ,
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW,
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_nBOOT1,
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_SRAM_PE, @ref FLASH_OB_USER_CCMSRAM_RST,
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_NRST_MODE, @ref FLASH_OB_USER_INTERNAL_RESET_HOLDER
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   (*) availability depends on devices
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval HAL_Status
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t optr_reg_val = 0;
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t optr_reg_mask = 0;
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Check the parameters */
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_OB_USER_TYPE(UserType));
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (status == HAL_OK)
+ARM GAS  /tmp/ccudk1nZ.s 			page 16
+
+
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_BOR_LEV) != 0U)
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* BOR level option byte should be modified */
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for BOR level option byte */
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_BOR_LEV;
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_nRST_STOP) != 0U)
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* nRST_STOP option byte should be modified */
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for nRST_STOP option byte */
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nRST_STOP;
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_nRST_STDBY) != 0U)
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* nRST_STDBY option byte should be modified */
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for nRST_STDBY option byte */
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_nRST_SHDW) != 0U)
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* nRST_SHDW option byte should be modified */
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for nRST_SHDW option byte */
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_IWDG_SW) != 0U)
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* IWDG_SW option byte should be modified */
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for IWDG_SW option byte */
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IWDG_SW;
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_IWDG_STOP) != 0U)
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* IWDG_STOP option byte should be modified */
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for IWDG_STOP option byte */
+ARM GAS  /tmp/ccudk1nZ.s 			page 17
+
+
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_IWDG_STDBY) != 0U)
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* IWDG_STDBY option byte should be modified */
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for IWDG_STDBY option byte */
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_WWDG_SW) != 0U)
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* WWDG_SW option byte should be modified */
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for WWDG_SW option byte */
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_WWDG_SW;
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_BFB2)
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_BFB2) != 0U)
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* BFB2 option byte should be modified */
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for BFB2 option byte */
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_BFB2;
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_nBOOT1) != 0U)
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* nBOOT1 option byte should be modified */
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for nBOOT1 option byte */
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nBOOT1;
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_SRAM_PE) != 0U)
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* SRAM_PE option byte should be modified */
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_SRAM_PARITY(UserConfig & FLASH_OPTR_SRAM_PE));
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for SRAM_PE option byte */
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_PE);
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_SRAM_PE;
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_CCMSRAM_RST) != 0U)
+ARM GAS  /tmp/ccudk1nZ.s 			page 18
+
+
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* CCMSRAM_RST option byte should be modified */
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_CCMSRAM_RST(UserConfig & FLASH_OPTR_CCMSRAM_RST));
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for CCMSRAM_RST option byte */
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_CCMSRAM_RST);
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_CCMSRAM_RST;
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_nSWBOOT0) != 0U)
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* nSWBOOT0 option byte should be modified */
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for nSWBOOT0 option byte */
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_nBOOT0) != 0U)
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* nBOOT0 option byte should be modified */
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for nBOOT0 option byte */
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nBOOT0;
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_NRST_MODE) != 0U)
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Reset Configuration option byte should be modified */
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_NRST_MODE(UserConfig & FLASH_OPTR_NRST_MODE));
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for Reset Configuration option byte */
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_NRST_MODE);
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_NRST_MODE;
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if ((UserType & OB_USER_IRHEN) != 0U)
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* IRH option byte should be modified */
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       assert_param(IS_OB_USER_IRHEN(UserConfig & FLASH_OPTR_IRHEN));
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Set value and mask for IRH option byte */
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_val |= (UserConfig & FLASH_OPTR_IRHEN);
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IRHEN;
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Configure the option bytes register */
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Set OPTSTRT Bit */
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Wait for last operation to be completed */
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ARM GAS  /tmp/ccudk1nZ.s 			page 19
+
+
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   return status;
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Configure the Proprietary code readout protection area into Option Bytes.
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   New option bytes configuration will be taken into account in two cases:
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP option).
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 (*)
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE.
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   (*) availability depends on devices
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  PCROPStartAddr specifies the start address of the Proprietary code readout protection.
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter can be an address between begin and end of the bank.
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  PCROPEndAddr specifies the end address of the Proprietary code readout protection.
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter can be an address between PCROPStartAddr and end of the bank.
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval HAL_Status
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t reg_value;
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t bank1_addr;
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t bank2_addr;
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Check the parameters */
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (status == HAL_OK)
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Get the information about the bank swapping */
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       bank1_addr = FLASH_BASE;
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else
+1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       bank2_addr = FLASH_BASE;
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #else
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     bank1_addr = FLASH_BASE;
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ARM GAS  /tmp/ccudk1nZ.s 			page 20
+
+
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Configure the Proprietary code readout protection */
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
+1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       else
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         /* Nothing to do */
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Configure the Proprietary code readout protection */
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
+1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       else
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         /* Nothing to do */
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP))
+1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Set OPTSTRT Bit */
+ARM GAS  /tmp/ccudk1nZ.s 			page 21
+
+
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Wait for last operation to be completed */
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   return status;
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Configure the Securable memory area into Option Bytes.
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   New option bytes configuration will be taken into account in two cases:
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  SecBank specifies bank of securable memory area to be configured.
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_1: Securable memory in Bank1 to be configured
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_2: Securable memory in Bank2 to be configured (*)
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   (*) availability depends on devices
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  SecSize specifies the number of pages of the Securable memory area,
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         starting from first page of the bank.
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This parameter can be page number between 0 and (max number of pages in the bank - 1)
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval HAL Status
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecBank, uint32_t SecSize)
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Check the parameters */
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_BANK_EXCLUSIVE(SecBank));
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_OB_SECMEM_SIZE(SecSize));
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+1113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (status == HAL_OK)
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Configure the write protected area */
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (SecBank == FLASH_BANK_1)
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1, SecSize);
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else if (SecBank == FLASH_BANK_2)
+1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       MODIFY_REG(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2, SecSize);
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+1126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else
+1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Nothing to do */
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Set OPTSTRT Bit */
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+ARM GAS  /tmp/ccudk1nZ.s 			page 22
+
+
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Wait for last operation to be completed */
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   return status;
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Configure the Boot Lock into Option Bytes.
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   New option bytes configuration will be taken into account in two cases:
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param  BootLockConfig specifies the boot lock configuration.
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+1151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_BOOT_LOCK_ENABLE: Enable Boot Lock
+1152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_BOOT_LOCK_DISABLE: Disable Boot Lock
+1153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval HAL_Status
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig)
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Check the parameters */
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_OB_BOOT_LOCK(BootLockConfig));
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (status == HAL_OK)
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_BOOT_LOCK, BootLockConfig);
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Set OPTSTRT Bit */
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Wait for last operation to be completed */
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   return status;
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Return the Securable memory area configuration into Option Bytes.
+1182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param[in]  SecBank specifies the bank where securable memory area is located.
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_1: Securable memory in Bank1
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_2: Securable memory in Bank2 (*)
+1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note   (*) availability depends on devices
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param[out]  SecSize specifies the number of pages used in the securable
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****                  memory area of the bank.
+1189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval None
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ARM GAS  /tmp/ccudk1nZ.s 			page 23
+
+
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static void FLASH_OB_GetSecMem(uint32_t SecBank, uint32_t *SecSize)
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+  68              		.loc 1 1192 1 is_stmt 1 view -0
+  69              		.cfi_startproc
+  70              		@ args = 0, pretend = 0, frame = 0
+  71              		@ frame_needed = 0, uses_anonymous_args = 0
+  72              		@ link register save eliminated.
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Get the configuration of the securable memory area */
+1194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (SecBank == FLASH_BANK_1)
+  73              		.loc 1 1194 3 view .LVU8
+  74              		.loc 1 1194 6 is_stmt 0 view .LVU9
+  75 0000 0128     		cmp	r0, #1
+  76 0002 00D0     		beq	.L7
+  77              	.L5:
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *SecSize = READ_BIT(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1);
+1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else if (SecBank == FLASH_BANK_2)
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *SecSize = READ_BIT(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2);
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Nothing to do */
+1206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+1208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+  78              		.loc 1 1208 1 view .LVU10
+  79 0004 7047     		bx	lr
+  80              	.L7:
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+  81              		.loc 1 1196 5 is_stmt 1 view .LVU11
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+  82              		.loc 1 1196 16 is_stmt 0 view .LVU12
+  83 0006 034B     		ldr	r3, .L8
+  84 0008 1B6F     		ldr	r3, [r3, #112]
+  85 000a 03F07F03 		and	r3, r3, #127
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+  86              		.loc 1 1196 14 view .LVU13
+  87 000e 0B60     		str	r3, [r1]
+  88              		.loc 1 1208 1 view .LVU14
+  89 0010 F8E7     		b	.L5
+  90              	.L9:
+  91 0012 00BF     		.align	2
+  92              	.L8:
+  93 0014 00200240 		.word	1073881088
+  94              		.cfi_endproc
+  95              	.LFE345:
+  97              		.section	.text.FLASH_OB_GetBootLock,"ax",%progbits
+  98              		.align	1
+  99              		.syntax unified
+ 100              		.thumb
+ 101              		.thumb_func
+ 103              	FLASH_OB_GetBootLock:
+ 104              	.LFB346:
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ARM GAS  /tmp/ccudk1nZ.s 			page 24
+
+
+1210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Return the Boot Lock configuration into Option Byte.
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval BootLockConfig.
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This return value can be one of the following values:
+1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_BOOT_LOCK_ENABLE: Boot lock enabled
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_BOOT_LOCK_DISABLE: Boot lock disabled
+1216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetBootLock(void)
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 105              		.loc 1 1218 1 is_stmt 1 view -0
+ 106              		.cfi_startproc
+ 107              		@ args = 0, pretend = 0, frame = 0
+ 108              		@ frame_needed = 0, uses_anonymous_args = 0
+ 109              		@ link register save eliminated.
+1219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   return (READ_REG(FLASH->SEC1R) & FLASH_SEC1R_BOOT_LOCK);
+ 110              		.loc 1 1219 3 view .LVU16
+ 111              		.loc 1 1219 11 is_stmt 0 view .LVU17
+ 112 0000 024B     		ldr	r3, .L11
+ 113 0002 186F     		ldr	r0, [r3, #112]
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 114              		.loc 1 1220 1 view .LVU18
+ 115 0004 00F48030 		and	r0, r0, #65536
+ 116 0008 7047     		bx	lr
+ 117              	.L12:
+ 118 000a 00BF     		.align	2
+ 119              	.L11:
+ 120 000c 00200240 		.word	1073881088
+ 121              		.cfi_endproc
+ 122              	.LFE346:
+ 124              		.section	.text.FLASH_OB_GetWRP,"ax",%progbits
+ 125              		.align	1
+ 126              		.syntax unified
+ 127              		.thumb
+ 128              		.thumb_func
+ 130              	FLASH_OB_GetWRP:
+ 131              	.LVL2:
+ 132              	.LFB347:
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+1223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Return the Write Protection configuration into Option Bytes.
+1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param[in]  WRPArea specifies the area to be returned.
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+1226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32G43x/STM32G44x
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32G43x/STM32G44x
+1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param[out]  WRPStartOffset specifies the address where to copied the start page
+1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *              of the write protected area.
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param[out]  WRDPEndOffset specifies the address where to copied the end page of
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *              the write protected area.
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval None
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 133              		.loc 1 1237 1 is_stmt 1 view -0
+ 134              		.cfi_startproc
+ 135              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/ccudk1nZ.s 			page 25
+
+
+ 136              		@ frame_needed = 0, uses_anonymous_args = 0
+ 137              		@ link register save eliminated.
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Get the configuration of the write protected area */
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (WRPArea == OB_WRPAREA_BANK1_AREAA)
+ 138              		.loc 1 1239 3 view .LVU20
+ 139              		.loc 1 1239 6 is_stmt 0 view .LVU21
+ 140 0000 48B9     		cbnz	r0, .L14
+1240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
+ 141              		.loc 1 1241 5 is_stmt 1 view .LVU22
+ 142              		.loc 1 1241 23 is_stmt 0 view .LVU23
+ 143 0002 0B48     		ldr	r0, .L17
+ 144              	.LVL3:
+ 145              		.loc 1 1241 23 view .LVU24
+ 146 0004 C36A     		ldr	r3, [r0, #44]
+ 147 0006 03F03F03 		and	r3, r3, #63
+ 148              		.loc 1 1241 21 view .LVU25
+ 149 000a 0B60     		str	r3, [r1]
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos
+ 150              		.loc 1 1242 5 is_stmt 1 view .LVU26
+ 151              		.loc 1 1242 23 is_stmt 0 view .LVU27
+ 152 000c C36A     		ldr	r3, [r0, #44]
+ 153              		.loc 1 1242 71 view .LVU28
+ 154 000e C3F30543 		ubfx	r3, r3, #16, #6
+ 155              		.loc 1 1242 20 view .LVU29
+ 156 0012 1360     		str	r3, [r2]
+ 157 0014 7047     		bx	lr
+ 158              	.LVL4:
+ 159              	.L14:
+1243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
+ 160              		.loc 1 1244 8 is_stmt 1 view .LVU30
+ 161              		.loc 1 1244 11 is_stmt 0 view .LVU31
+ 162 0016 0128     		cmp	r0, #1
+ 163 0018 00D0     		beq	.L16
+ 164              	.LVL5:
+ 165              	.L13:
+1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos
+1248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
+1251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Nothing to do */
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ARM GAS  /tmp/ccudk1nZ.s 			page 26
+
+
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 166              		.loc 1 1265 1 view .LVU32
+ 167 001a 7047     		bx	lr
+ 168              	.LVL6:
+ 169              	.L16:
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos
+ 170              		.loc 1 1246 5 is_stmt 1 view .LVU33
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos
+ 171              		.loc 1 1246 23 is_stmt 0 view .LVU34
+ 172 001c 0448     		ldr	r0, .L17
+ 173              	.LVL7:
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos
+ 174              		.loc 1 1246 23 view .LVU35
+ 175 001e 036B     		ldr	r3, [r0, #48]
+ 176 0020 03F03F03 		and	r3, r3, #63
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos
+ 177              		.loc 1 1246 21 view .LVU36
+ 178 0024 0B60     		str	r3, [r1]
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 179              		.loc 1 1247 5 is_stmt 1 view .LVU37
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 180              		.loc 1 1247 23 is_stmt 0 view .LVU38
+ 181 0026 036B     		ldr	r3, [r0, #48]
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 182              		.loc 1 1247 71 view .LVU39
+ 183 0028 C3F30543 		ubfx	r3, r3, #16, #6
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 184              		.loc 1 1247 20 view .LVU40
+ 185 002c 1360     		str	r3, [r2]
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 186              		.loc 1 1264 3 is_stmt 1 view .LVU41
+ 187              		.loc 1 1265 1 is_stmt 0 view .LVU42
+ 188 002e F4E7     		b	.L13
+ 189              	.L18:
+ 190              		.align	2
+ 191              	.L17:
+ 192 0030 00200240 		.word	1073881088
+ 193              		.cfi_endproc
+ 194              	.LFE347:
+ 196              		.section	.text.FLASH_OB_GetRDP,"ax",%progbits
+ 197              		.align	1
+ 198              		.syntax unified
+ 199              		.thumb
+ 200              		.thumb_func
+ 202              	FLASH_OB_GetRDP:
+ 203              	.LFB348:
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Return the FLASH Read Protection level into Option Bytes.
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval RDP_Level
+1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This return value can be one of the following values:
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_RDP_LEVEL_0: No protection
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *            @arg OB_RDP_LEVEL_2: Full chip protection
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetRDP(void)
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ARM GAS  /tmp/ccudk1nZ.s 			page 27
+
+
+ 204              		.loc 1 1276 1 is_stmt 1 view -0
+ 205              		.cfi_startproc
+ 206              		@ args = 0, pretend = 0, frame = 0
+ 207              		@ frame_needed = 0, uses_anonymous_args = 0
+ 208              		@ link register save eliminated.
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
+ 209              		.loc 1 1277 3 view .LVU44
+ 210              		.loc 1 1277 24 is_stmt 0 view .LVU45
+ 211 0000 044B     		ldr	r3, .L22
+ 212 0002 186A     		ldr	r0, [r3, #32]
+ 213              		.loc 1 1277 12 view .LVU46
+ 214 0004 C0B2     		uxtb	r0, r0
+ 215              	.LVL8:
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
+ 216              		.loc 1 1279 3 is_stmt 1 view .LVU47
+ 217              		.loc 1 1279 6 is_stmt 0 view .LVU48
+ 218 0006 AA28     		cmp	r0, #170
+ 219 0008 02D0     		beq	.L19
+ 220              		.loc 1 1279 37 discriminator 1 view .LVU49
+ 221 000a CC28     		cmp	r0, #204
+ 222 000c 00D0     		beq	.L19
+1280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     return (OB_RDP_LEVEL_1);
+ 223              		.loc 1 1281 12 view .LVU50
+ 224 000e BB20     		movs	r0, #187
+ 225              	.LVL9:
+ 226              	.L19:
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else
+1284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     return rdp_level;
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 227              		.loc 1 1287 1 view .LVU51
+ 228 0010 7047     		bx	lr
+ 229              	.L23:
+ 230 0012 00BF     		.align	2
+ 231              	.L22:
+ 232 0014 00200240 		.word	1073881088
+ 233              		.cfi_endproc
+ 234              	.LFE348:
+ 236              		.section	.text.FLASH_OB_GetUser,"ax",%progbits
+ 237              		.align	1
+ 238              		.syntax unified
+ 239              		.thumb
+ 240              		.thumb_func
+ 242              	FLASH_OB_GetUser:
+ 243              	.LFB349:
+1288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Return the FLASH User Option Byte value.
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval OB_user_config
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         This return value is a combination of @ref FLASH_OB_USER_BOR_LEVEL,
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
+ARM GAS  /tmp/ccudk1nZ.s 			page 28
+
+
+1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW,
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_DBANK (*),
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE,
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_CCMSRAM_RST, @ref OB_USER_nSWBOOT0,@ref FLASH_OB_USER_nBOOT0,
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *         @ref FLASH_OB_USER_NRST_MODE, @ref FLASH_OB_USER_INTERNAL_RESET_HOLDER
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @note  (*) availability depends on devices
+1302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetUser(void)
+1304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 244              		.loc 1 1304 1 is_stmt 1 view -0
+ 245              		.cfi_startproc
+ 246              		@ args = 0, pretend = 0, frame = 0
+ 247              		@ frame_needed = 0, uses_anonymous_args = 0
+ 248              		@ link register save eliminated.
+1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t user_config = READ_REG(FLASH->OPTR);
+ 249              		.loc 1 1305 3 view .LVU53
+ 250              		.loc 1 1305 12 is_stmt 0 view .LVU54
+ 251 0000 024B     		ldr	r3, .L25
+ 252 0002 186A     		ldr	r0, [r3, #32]
+ 253              	.LVL10:
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   CLEAR_BIT(user_config, FLASH_OPTR_RDP);
+ 254              		.loc 1 1306 3 is_stmt 1 view .LVU55
+1307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   return user_config;
+ 255              		.loc 1 1308 3 view .LVU56
+1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 256              		.loc 1 1309 1 is_stmt 0 view .LVU57
+ 257 0004 20F0FF00 		bic	r0, r0, #255
+ 258              	.LVL11:
+ 259              		.loc 1 1309 1 view .LVU58
+ 260 0008 7047     		bx	lr
+ 261              	.L26:
+ 262 000a 00BF     		.align	2
+ 263              	.L25:
+ 264 000c 00200240 		.word	1073881088
+ 265              		.cfi_endproc
+ 266              	.LFE349:
+ 268              		.section	.text.FLASH_OB_GetPCROP,"ax",%progbits
+ 269              		.align	1
+ 270              		.syntax unified
+ 271              		.thumb
+ 272              		.thumb_func
+ 274              	FLASH_OB_GetPCROP:
+ 275              	.LVL12:
+ 276              	.LFB350:
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** /**
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @brief  Return the FLASH PCROP configuration into Option Bytes.
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param[in,out] PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP opt
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *        This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *        with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE.
+1316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param[out] PCROPStartAddr specifies the address where to copied the start address
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *        of the Proprietary code readout protection.
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @param[out] PCROPEndAddr specifies the address where to copied the end address of
+1319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *        the Proprietary code readout protection.
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   * @retval None
+1321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   */
+ARM GAS  /tmp/ccudk1nZ.s 			page 29
+
+
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAd
+1323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** {
+ 277              		.loc 1 1323 1 is_stmt 1 view -0
+ 278              		.cfi_startproc
+ 279              		@ args = 0, pretend = 0, frame = 0
+ 280              		@ frame_needed = 0, uses_anonymous_args = 0
+ 281              		@ link register save eliminated.
+ 282              		.loc 1 1323 1 is_stmt 0 view .LVU60
+ 283 0000 30B4     		push	{r4, r5}
+ 284              	.LCFI0:
+ 285              		.cfi_def_cfa_offset 8
+ 286              		.cfi_offset 4, -8
+ 287              		.cfi_offset 5, -4
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t reg_value;
+ 288              		.loc 1 1324 3 is_stmt 1 view .LVU61
+1325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t bank1_addr;
+ 289              		.loc 1 1325 3 view .LVU62
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t bank2_addr;
+1328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Get the information about the bank swapping */
+1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)
+1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     bank1_addr = FLASH_BASE;
+1333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else
+1336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
+1338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     bank2_addr = FLASH_BASE;
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #else
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   bank1_addr = FLASH_BASE;
+ 290              		.loc 1 1341 3 view .LVU63
+ 291              	.LVL13:
+1342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
+1350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
+1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
+1353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       *PCROPEndAddr = (reg_value << 4) + FLASH_BASE;
+1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
+1358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       *PCROPEndAddr = (reg_value << 4) + FLASH_BASE;
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else
+ARM GAS  /tmp/ccudk1nZ.s 			page 30
+
+
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Nothing to do */
+1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   else
+1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
+ 292              		.loc 1 1371 5 view .LVU64
+ 293              		.loc 1 1371 11 is_stmt 0 view .LVU65
+ 294 0002 0368     		ldr	r3, [r0]
+ 295              		.loc 1 1371 8 view .LVU66
+ 296 0004 13F0010F 		tst	r3, #1
+ 297 0008 0DD0     		beq	.L28
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
+ 298              		.loc 1 1373 7 is_stmt 1 view .LVU67
+ 299              		.loc 1 1373 26 is_stmt 0 view .LVU68
+ 300 000a 0B4D     		ldr	r5, .L30
+ 301 000c 6C6A     		ldr	r4, [r5, #36]
+ 302              	.LVL14:
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       *PCROPStartAddr = (reg_value << 3) + bank1_addr;
+ 303              		.loc 1 1374 7 is_stmt 1 view .LVU69
+ 304              		.loc 1 1374 36 is_stmt 0 view .LVU70
+ 305 000e 0B4B     		ldr	r3, .L30+4
+ 306 0010 03EAC404 		and	r4, r3, r4, lsl #3
+ 307              	.LVL15:
+ 308              		.loc 1 1374 42 view .LVU71
+ 309 0014 04F10064 		add	r4, r4, #134217728
+ 310              		.loc 1 1374 23 view .LVU72
+ 311 0018 0C60     		str	r4, [r1]
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
+ 312              		.loc 1 1376 7 is_stmt 1 view .LVU73
+ 313              		.loc 1 1376 24 is_stmt 0 view .LVU74
+ 314 001a A96A     		ldr	r1, [r5, #40]
+ 315              	.LVL16:
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       *PCROPEndAddr = (reg_value << 3) + bank1_addr;
+ 316              		.loc 1 1377 7 is_stmt 1 view .LVU75
+ 317              		.loc 1 1377 34 is_stmt 0 view .LVU76
+ 318 001c 03EAC103 		and	r3, r3, r1, lsl #3
+ 319              		.loc 1 1377 40 view .LVU77
+ 320 0020 03F10063 		add	r3, r3, #134217728
+ 321              		.loc 1 1377 21 view .LVU78
+ 322 0024 1360     		str	r3, [r2]
+ 323              	.LVL17:
+ 324              	.L28:
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       *PCROPStartAddr = (reg_value << 3) + bank2_addr;
+1384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
+1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       *PCROPEndAddr = (reg_value << 3) + bank2_addr;
+1387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ARM GAS  /tmp/ccudk1nZ.s 			page 31
+
+
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     else
+1390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       /* Nothing to do */
+1392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 325              		.loc 1 1392 5 is_stmt 1 view .LVU79
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+1394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
+ 326              		.loc 1 1395 3 view .LVU80
+ 327              		.loc 1 1395 20 is_stmt 0 view .LVU81
+ 328 0026 044B     		ldr	r3, .L30
+ 329 0028 9A6A     		ldr	r2, [r3, #40]
+ 330              	.LVL18:
+ 331              		.loc 1 1395 46 view .LVU82
+ 332 002a 02F00042 		and	r2, r2, #-2147483648
+ 333              		.loc 1 1395 3 view .LVU83
+ 334 002e 0368     		ldr	r3, [r0]
+ 335              		.loc 1 1395 16 view .LVU84
+ 336 0030 1343     		orrs	r3, r3, r2
+ 337 0032 0360     		str	r3, [r0]
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 338              		.loc 1 1396 1 view .LVU85
+ 339 0034 30BC     		pop	{r4, r5}
+ 340              	.LCFI1:
+ 341              		.cfi_restore 5
+ 342              		.cfi_restore 4
+ 343              		.cfi_def_cfa_offset 0
+ 344 0036 7047     		bx	lr
+ 345              	.L31:
+ 346              		.align	2
+ 347              	.L30:
+ 348 0038 00200240 		.word	1073881088
+ 349 003c F8FF0100 		.word	131064
+ 350              		.cfi_endproc
+ 351              	.LFE350:
+ 353              		.section	.text.FLASH_OB_WRPConfig,"ax",%progbits
+ 354              		.align	1
+ 355              		.syntax unified
+ 356              		.thumb
+ 357              		.thumb_func
+ 359              	FLASH_OB_WRPConfig:
+ 360              	.LVL19:
+ 361              	.LFB339:
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 362              		.loc 1 668 1 is_stmt 1 view -0
+ 363              		.cfi_startproc
+ 364              		@ args = 0, pretend = 0, frame = 0
+ 365              		@ frame_needed = 0, uses_anonymous_args = 0
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 366              		.loc 1 668 1 is_stmt 0 view .LVU87
+ 367 0000 70B5     		push	{r4, r5, r6, lr}
+ 368              	.LCFI2:
+ 369              		.cfi_def_cfa_offset 16
+ 370              		.cfi_offset 4, -16
+ 371              		.cfi_offset 5, -12
+ 372              		.cfi_offset 6, -8
+ARM GAS  /tmp/ccudk1nZ.s 			page 32
+
+
+ 373              		.cfi_offset 14, -4
+ 374 0002 0546     		mov	r5, r0
+ 375 0004 0C46     		mov	r4, r1
+ 376 0006 1646     		mov	r6, r2
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 377              		.loc 1 669 3 is_stmt 1 view .LVU88
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_PAGE(WRPStartOffset));
+ 378              		.loc 1 672 3 view .LVU89
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_PAGE(WRDPEndOffset));
+ 379              		.loc 1 673 3 view .LVU90
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 380              		.loc 1 674 3 view .LVU91
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 381              		.loc 1 677 3 view .LVU92
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 382              		.loc 1 677 12 is_stmt 0 view .LVU93
+ 383 0008 4FF47A70 		mov	r0, #1000
+ 384              	.LVL20:
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 385              		.loc 1 677 12 view .LVU94
+ 386 000c FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 387              	.LVL21:
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 388              		.loc 1 679 3 is_stmt 1 view .LVU95
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 389              		.loc 1 679 6 is_stmt 0 view .LVU96
+ 390 0010 68B9     		cbnz	r0, .L33
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 391              		.loc 1 682 5 is_stmt 1 view .LVU97
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 392              		.loc 1 682 8 is_stmt 0 view .LVU98
+ 393 0012 6DB9     		cbnz	r5, .L34
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 394              		.loc 1 684 7 is_stmt 1 view .LVU99
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 395              		.loc 1 684 70 is_stmt 0 view .LVU100
+ 396 0014 44EA0644 		orr	r4, r4, r6, lsl #16
+ 397              	.LVL22:
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 398              		.loc 1 684 21 view .LVU101
+ 399 0018 094B     		ldr	r3, .L37
+ 400 001a DC62     		str	r4, [r3, #44]
+ 401              	.L35:
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 402              		.loc 1 703 5 is_stmt 1 view .LVU102
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 403              		.loc 1 706 5 view .LVU103
+ 404 001c 084A     		ldr	r2, .L37
+ 405 001e 5369     		ldr	r3, [r2, #20]
+ 406 0020 43F40033 		orr	r3, r3, #131072
+ 407 0024 5361     		str	r3, [r2, #20]
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 408              		.loc 1 709 5 view .LVU104
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 409              		.loc 1 709 14 is_stmt 0 view .LVU105
+ 410 0026 4FF47A70 		mov	r0, #1000
+ 411 002a FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ARM GAS  /tmp/ccudk1nZ.s 			page 33
+
+
+ 412              	.LVL23:
+ 413              	.L33:
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 414              		.loc 1 712 3 is_stmt 1 view .LVU106
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 415              		.loc 1 713 1 is_stmt 0 view .LVU107
+ 416 002e 70BD     		pop	{r4, r5, r6, pc}
+ 417              	.LVL24:
+ 418              	.L34:
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 419              		.loc 1 686 10 is_stmt 1 view .LVU108
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 420              		.loc 1 686 13 is_stmt 0 view .LVU109
+ 421 0030 012D     		cmp	r5, #1
+ 422 0032 F3D1     		bne	.L35
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 423              		.loc 1 688 7 is_stmt 1 view .LVU110
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 424              		.loc 1 688 70 is_stmt 0 view .LVU111
+ 425 0034 44EA0644 		orr	r4, r4, r6, lsl #16
+ 426              	.LVL25:
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 427              		.loc 1 688 21 view .LVU112
+ 428 0038 014B     		ldr	r3, .L37
+ 429 003a 1C63     		str	r4, [r3, #48]
+ 430 003c EEE7     		b	.L35
+ 431              	.L38:
+ 432 003e 00BF     		.align	2
+ 433              	.L37:
+ 434 0040 00200240 		.word	1073881088
+ 435              		.cfi_endproc
+ 436              	.LFE339:
+ 438              		.section	.text.FLASH_OB_RDPConfig,"ax",%progbits
+ 439              		.align	1
+ 440              		.syntax unified
+ 441              		.thumb
+ 442              		.thumb_func
+ 444              	FLASH_OB_RDPConfig:
+ 445              	.LVL26:
+ 446              	.LFB340:
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 447              		.loc 1 733 1 is_stmt 1 view -0
+ 448              		.cfi_startproc
+ 449              		@ args = 0, pretend = 0, frame = 0
+ 450              		@ frame_needed = 0, uses_anonymous_args = 0
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 451              		.loc 1 733 1 is_stmt 0 view .LVU114
+ 452 0000 10B5     		push	{r4, lr}
+ 453              	.LCFI3:
+ 454              		.cfi_def_cfa_offset 8
+ 455              		.cfi_offset 4, -8
+ 456              		.cfi_offset 14, -4
+ 457 0002 0446     		mov	r4, r0
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 458              		.loc 1 734 3 is_stmt 1 view .LVU115
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 459              		.loc 1 737 3 view .LVU116
+ARM GAS  /tmp/ccudk1nZ.s 			page 34
+
+
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 460              		.loc 1 740 3 view .LVU117
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 461              		.loc 1 740 12 is_stmt 0 view .LVU118
+ 462 0004 4FF47A70 		mov	r0, #1000
+ 463              	.LVL27:
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 464              		.loc 1 740 12 view .LVU119
+ 465 0008 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 466              	.LVL28:
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 467              		.loc 1 742 3 is_stmt 1 view .LVU120
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 468              		.loc 1 742 6 is_stmt 0 view .LVU121
+ 469 000c 00B1     		cbz	r0, .L42
+ 470              	.L40:
+ 471              	.LVL29:
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 472              		.loc 1 754 3 is_stmt 1 view .LVU122
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 473              		.loc 1 755 1 is_stmt 0 view .LVU123
+ 474 000e 10BD     		pop	{r4, pc}
+ 475              	.LVL30:
+ 476              	.L42:
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 477              		.loc 1 745 5 is_stmt 1 view .LVU124
+ 478 0010 074A     		ldr	r2, .L43
+ 479 0012 136A     		ldr	r3, [r2, #32]
+ 480 0014 23F0FF03 		bic	r3, r3, #255
+ 481 0018 2343     		orrs	r3, r3, r4
+ 482 001a 1362     		str	r3, [r2, #32]
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 483              		.loc 1 748 5 view .LVU125
+ 484 001c 5369     		ldr	r3, [r2, #20]
+ 485 001e 43F40033 		orr	r3, r3, #131072
+ 486 0022 5361     		str	r3, [r2, #20]
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 487              		.loc 1 751 5 view .LVU126
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 488              		.loc 1 751 14 is_stmt 0 view .LVU127
+ 489 0024 4FF47A70 		mov	r0, #1000
+ 490 0028 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 491              	.LVL31:
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 492              		.loc 1 751 14 view .LVU128
+ 493 002c EFE7     		b	.L40
+ 494              	.L44:
+ 495 002e 00BF     		.align	2
+ 496              	.L43:
+ 497 0030 00200240 		.word	1073881088
+ 498              		.cfi_endproc
+ 499              	.LFE340:
+ 501              		.section	.text.FLASH_OB_UserConfig,"ax",%progbits
+ 502              		.align	1
+ 503              		.syntax unified
+ 504              		.thumb
+ 505              		.thumb_func
+ARM GAS  /tmp/ccudk1nZ.s 			page 35
+
+
+ 507              	FLASH_OB_UserConfig:
+ 508              	.LVL32:
+ 509              	.LFB341:
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t optr_reg_val = 0;
+ 510              		.loc 1 780 1 is_stmt 1 view -0
+ 511              		.cfi_startproc
+ 512              		@ args = 0, pretend = 0, frame = 0
+ 513              		@ frame_needed = 0, uses_anonymous_args = 0
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t optr_reg_val = 0;
+ 514              		.loc 1 780 1 is_stmt 0 view .LVU130
+ 515 0000 38B5     		push	{r3, r4, r5, lr}
+ 516              	.LCFI4:
+ 517              		.cfi_def_cfa_offset 16
+ 518              		.cfi_offset 3, -16
+ 519              		.cfi_offset 4, -12
+ 520              		.cfi_offset 5, -8
+ 521              		.cfi_offset 14, -4
+ 522 0002 0446     		mov	r4, r0
+ 523 0004 0D46     		mov	r5, r1
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t optr_reg_mask = 0;
+ 524              		.loc 1 781 3 is_stmt 1 view .LVU131
+ 525              	.LVL33:
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 526              		.loc 1 782 3 view .LVU132
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 527              		.loc 1 783 3 view .LVU133
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 528              		.loc 1 786 3 view .LVU134
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 529              		.loc 1 789 3 view .LVU135
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 530              		.loc 1 789 12 is_stmt 0 view .LVU136
+ 531 0006 4FF47A70 		mov	r0, #1000
+ 532              	.LVL34:
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 533              		.loc 1 789 12 view .LVU137
+ 534 000a FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 535              	.LVL35:
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 536              		.loc 1 791 3 is_stmt 1 view .LVU138
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 537              		.loc 1 791 6 is_stmt 0 view .LVU139
+ 538 000e 0028     		cmp	r0, #0
+ 539 0010 40F08780 		bne	.L46
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 540              		.loc 1 793 5 is_stmt 1 view .LVU140
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 541              		.loc 1 793 8 is_stmt 0 view .LVU141
+ 542 0014 14F00103 		ands	r3, r4, #1
+ 543 0018 04D0     		beq	.L62
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 544              		.loc 1 796 7 is_stmt 1 view .LVU142
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_BOR_LEV;
+ 545              		.loc 1 799 7 view .LVU143
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_BOR_LEV;
+ 546              		.loc 1 799 35 is_stmt 0 view .LVU144
+ 547 001a 05F4E063 		and	r3, r5, #1792
+ARM GAS  /tmp/ccudk1nZ.s 			page 36
+
+
+ 548              	.LVL36:
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 549              		.loc 1 800 7 is_stmt 1 view .LVU145
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 550              		.loc 1 800 21 is_stmt 0 view .LVU146
+ 551 001e 4FF4E062 		mov	r2, #1792
+ 552 0022 00E0     		b	.L47
+ 553              	.LVL37:
+ 554              	.L62:
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 555              		.loc 1 782 12 view .LVU147
+ 556 0024 1A46     		mov	r2, r3
+ 557              	.LVL38:
+ 558              	.L47:
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 559              		.loc 1 803 5 is_stmt 1 view .LVU148
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 560              		.loc 1 803 8 is_stmt 0 view .LVU149
+ 561 0026 14F0020F 		tst	r4, #2
+ 562 002a 04D0     		beq	.L48
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 563              		.loc 1 806 7 is_stmt 1 view .LVU150
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nRST_STOP;
+ 564              		.loc 1 809 7 view .LVU151
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nRST_STOP;
+ 565              		.loc 1 809 35 is_stmt 0 view .LVU152
+ 566 002c 05F48051 		and	r1, r5, #4096
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nRST_STOP;
+ 567              		.loc 1 809 20 view .LVU153
+ 568 0030 0B43     		orrs	r3, r3, r1
+ 569              	.LVL39:
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 570              		.loc 1 810 7 is_stmt 1 view .LVU154
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 571              		.loc 1 810 21 is_stmt 0 view .LVU155
+ 572 0032 42F48052 		orr	r2, r2, #4096
+ 573              	.LVL40:
+ 574              	.L48:
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 575              		.loc 1 813 5 is_stmt 1 view .LVU156
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 576              		.loc 1 813 8 is_stmt 0 view .LVU157
+ 577 0036 14F0040F 		tst	r4, #4
+ 578 003a 04D0     		beq	.L49
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 579              		.loc 1 816 7 is_stmt 1 view .LVU158
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
+ 580              		.loc 1 819 7 view .LVU159
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
+ 581              		.loc 1 819 35 is_stmt 0 view .LVU160
+ 582 003c 05F40051 		and	r1, r5, #8192
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
+ 583              		.loc 1 819 20 view .LVU161
+ 584 0040 0B43     		orrs	r3, r3, r1
+ 585              	.LVL41:
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 586              		.loc 1 820 7 is_stmt 1 view .LVU162
+ARM GAS  /tmp/ccudk1nZ.s 			page 37
+
+
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 587              		.loc 1 820 21 is_stmt 0 view .LVU163
+ 588 0042 42F40052 		orr	r2, r2, #8192
+ 589              	.LVL42:
+ 590              	.L49:
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 591              		.loc 1 823 5 is_stmt 1 view .LVU164
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 592              		.loc 1 823 8 is_stmt 0 view .LVU165
+ 593 0046 14F4805F 		tst	r4, #4096
+ 594 004a 04D0     		beq	.L50
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 595              		.loc 1 826 7 is_stmt 1 view .LVU166
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
+ 596              		.loc 1 829 7 view .LVU167
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
+ 597              		.loc 1 829 35 is_stmt 0 view .LVU168
+ 598 004c 05F48041 		and	r1, r5, #16384
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
+ 599              		.loc 1 829 20 view .LVU169
+ 600 0050 0B43     		orrs	r3, r3, r1
+ 601              	.LVL43:
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 602              		.loc 1 830 7 is_stmt 1 view .LVU170
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 603              		.loc 1 830 21 is_stmt 0 view .LVU171
+ 604 0052 42F48042 		orr	r2, r2, #16384
+ 605              	.LVL44:
+ 606              	.L50:
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 607              		.loc 1 833 5 is_stmt 1 view .LVU172
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 608              		.loc 1 833 8 is_stmt 0 view .LVU173
+ 609 0056 14F0080F 		tst	r4, #8
+ 610 005a 04D0     		beq	.L51
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 611              		.loc 1 836 7 is_stmt 1 view .LVU174
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IWDG_SW;
+ 612              		.loc 1 839 7 view .LVU175
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IWDG_SW;
+ 613              		.loc 1 839 35 is_stmt 0 view .LVU176
+ 614 005c 05F48031 		and	r1, r5, #65536
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IWDG_SW;
+ 615              		.loc 1 839 20 view .LVU177
+ 616 0060 0B43     		orrs	r3, r3, r1
+ 617              	.LVL45:
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 618              		.loc 1 840 7 is_stmt 1 view .LVU178
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 619              		.loc 1 840 21 is_stmt 0 view .LVU179
+ 620 0062 42F48032 		orr	r2, r2, #65536
+ 621              	.LVL46:
+ 622              	.L51:
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 623              		.loc 1 843 5 is_stmt 1 view .LVU180
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 624              		.loc 1 843 8 is_stmt 0 view .LVU181
+ARM GAS  /tmp/ccudk1nZ.s 			page 38
+
+
+ 625 0066 14F0100F 		tst	r4, #16
+ 626 006a 04D0     		beq	.L52
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 627              		.loc 1 846 7 is_stmt 1 view .LVU182
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
+ 628              		.loc 1 849 7 view .LVU183
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
+ 629              		.loc 1 849 35 is_stmt 0 view .LVU184
+ 630 006c 05F40031 		and	r1, r5, #131072
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
+ 631              		.loc 1 849 20 view .LVU185
+ 632 0070 0B43     		orrs	r3, r3, r1
+ 633              	.LVL47:
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 634              		.loc 1 850 7 is_stmt 1 view .LVU186
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 635              		.loc 1 850 21 is_stmt 0 view .LVU187
+ 636 0072 42F40032 		orr	r2, r2, #131072
+ 637              	.LVL48:
+ 638              	.L52:
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 639              		.loc 1 853 5 is_stmt 1 view .LVU188
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 640              		.loc 1 853 8 is_stmt 0 view .LVU189
+ 641 0076 14F0200F 		tst	r4, #32
+ 642 007a 04D0     		beq	.L53
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 643              		.loc 1 856 7 is_stmt 1 view .LVU190
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
+ 644              		.loc 1 859 7 view .LVU191
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
+ 645              		.loc 1 859 35 is_stmt 0 view .LVU192
+ 646 007c 05F48021 		and	r1, r5, #262144
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
+ 647              		.loc 1 859 20 view .LVU193
+ 648 0080 0B43     		orrs	r3, r3, r1
+ 649              	.LVL49:
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 650              		.loc 1 860 7 is_stmt 1 view .LVU194
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 651              		.loc 1 860 21 is_stmt 0 view .LVU195
+ 652 0082 42F48022 		orr	r2, r2, #262144
+ 653              	.LVL50:
+ 654              	.L53:
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 655              		.loc 1 863 5 is_stmt 1 view .LVU196
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 656              		.loc 1 863 8 is_stmt 0 view .LVU197
+ 657 0086 14F0400F 		tst	r4, #64
+ 658 008a 04D0     		beq	.L54
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 659              		.loc 1 866 7 is_stmt 1 view .LVU198
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_WWDG_SW;
+ 660              		.loc 1 869 7 view .LVU199
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_WWDG_SW;
+ 661              		.loc 1 869 35 is_stmt 0 view .LVU200
+ 662 008c 05F40021 		and	r1, r5, #524288
+ARM GAS  /tmp/ccudk1nZ.s 			page 39
+
+
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_WWDG_SW;
+ 663              		.loc 1 869 20 view .LVU201
+ 664 0090 0B43     		orrs	r3, r3, r1
+ 665              	.LVL51:
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 666              		.loc 1 870 7 is_stmt 1 view .LVU202
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 667              		.loc 1 870 21 is_stmt 0 view .LVU203
+ 668 0092 42F40022 		orr	r2, r2, #524288
+ 669              	.LVL52:
+ 670              	.L54:
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 671              		.loc 1 885 5 is_stmt 1 view .LVU204
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 672              		.loc 1 885 8 is_stmt 0 view .LVU205
+ 673 0096 14F4007F 		tst	r4, #512
+ 674 009a 04D0     		beq	.L55
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 675              		.loc 1 888 7 is_stmt 1 view .LVU206
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nBOOT1;
+ 676              		.loc 1 891 7 view .LVU207
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nBOOT1;
+ 677              		.loc 1 891 35 is_stmt 0 view .LVU208
+ 678 009c 05F40001 		and	r1, r5, #8388608
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nBOOT1;
+ 679              		.loc 1 891 20 view .LVU209
+ 680 00a0 0B43     		orrs	r3, r3, r1
+ 681              	.LVL53:
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 682              		.loc 1 892 7 is_stmt 1 view .LVU210
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 683              		.loc 1 892 21 is_stmt 0 view .LVU211
+ 684 00a2 42F40002 		orr	r2, r2, #8388608
+ 685              	.LVL54:
+ 686              	.L55:
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 687              		.loc 1 895 5 is_stmt 1 view .LVU212
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 688              		.loc 1 895 8 is_stmt 0 view .LVU213
+ 689 00a6 14F4806F 		tst	r4, #1024
+ 690 00aa 04D0     		beq	.L56
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 691              		.loc 1 898 7 is_stmt 1 view .LVU214
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_SRAM_PE;
+ 692              		.loc 1 901 7 view .LVU215
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_SRAM_PE;
+ 693              		.loc 1 901 35 is_stmt 0 view .LVU216
+ 694 00ac 05F08071 		and	r1, r5, #16777216
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_SRAM_PE;
+ 695              		.loc 1 901 20 view .LVU217
+ 696 00b0 0B43     		orrs	r3, r3, r1
+ 697              	.LVL55:
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 698              		.loc 1 902 7 is_stmt 1 view .LVU218
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 699              		.loc 1 902 21 is_stmt 0 view .LVU219
+ 700 00b2 42F08072 		orr	r2, r2, #16777216
+ARM GAS  /tmp/ccudk1nZ.s 			page 40
+
+
+ 701              	.LVL56:
+ 702              	.L56:
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 703              		.loc 1 905 5 is_stmt 1 view .LVU220
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 704              		.loc 1 905 8 is_stmt 0 view .LVU221
+ 705 00b6 14F4006F 		tst	r4, #2048
+ 706 00ba 04D0     		beq	.L57
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 707              		.loc 1 908 7 is_stmt 1 view .LVU222
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_CCMSRAM_RST;
+ 708              		.loc 1 911 7 view .LVU223
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_CCMSRAM_RST;
+ 709              		.loc 1 911 35 is_stmt 0 view .LVU224
+ 710 00bc 05F00071 		and	r1, r5, #33554432
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_CCMSRAM_RST;
+ 711              		.loc 1 911 20 view .LVU225
+ 712 00c0 0B43     		orrs	r3, r3, r1
+ 713              	.LVL57:
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 714              		.loc 1 912 7 is_stmt 1 view .LVU226
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 715              		.loc 1 912 21 is_stmt 0 view .LVU227
+ 716 00c2 42F00072 		orr	r2, r2, #33554432
+ 717              	.LVL58:
+ 718              	.L57:
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 719              		.loc 1 915 5 is_stmt 1 view .LVU228
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 720              		.loc 1 915 8 is_stmt 0 view .LVU229
+ 721 00c6 14F4005F 		tst	r4, #8192
+ 722 00ca 04D0     		beq	.L58
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 723              		.loc 1 918 7 is_stmt 1 view .LVU230
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
+ 724              		.loc 1 921 7 view .LVU231
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
+ 725              		.loc 1 921 35 is_stmt 0 view .LVU232
+ 726 00cc 05F08061 		and	r1, r5, #67108864
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
+ 727              		.loc 1 921 20 view .LVU233
+ 728 00d0 0B43     		orrs	r3, r3, r1
+ 729              	.LVL59:
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 730              		.loc 1 922 7 is_stmt 1 view .LVU234
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 731              		.loc 1 922 21 is_stmt 0 view .LVU235
+ 732 00d2 42F08062 		orr	r2, r2, #67108864
+ 733              	.LVL60:
+ 734              	.L58:
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 735              		.loc 1 925 5 is_stmt 1 view .LVU236
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 736              		.loc 1 925 8 is_stmt 0 view .LVU237
+ 737 00d6 14F4804F 		tst	r4, #16384
+ 738 00da 04D0     		beq	.L59
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ARM GAS  /tmp/ccudk1nZ.s 			page 41
+
+
+ 739              		.loc 1 928 7 is_stmt 1 view .LVU238
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nBOOT0;
+ 740              		.loc 1 931 7 view .LVU239
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nBOOT0;
+ 741              		.loc 1 931 35 is_stmt 0 view .LVU240
+ 742 00dc 05F00061 		and	r1, r5, #134217728
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_nBOOT0;
+ 743              		.loc 1 931 20 view .LVU241
+ 744 00e0 0B43     		orrs	r3, r3, r1
+ 745              	.LVL61:
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 746              		.loc 1 932 7 is_stmt 1 view .LVU242
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 747              		.loc 1 932 21 is_stmt 0 view .LVU243
+ 748 00e2 42F00062 		orr	r2, r2, #134217728
+ 749              	.LVL62:
+ 750              	.L59:
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 751              		.loc 1 935 5 is_stmt 1 view .LVU244
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 752              		.loc 1 935 8 is_stmt 0 view .LVU245
+ 753 00e6 14F4004F 		tst	r4, #32768
+ 754 00ea 04D0     		beq	.L60
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 755              		.loc 1 938 7 is_stmt 1 view .LVU246
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_NRST_MODE;
+ 756              		.loc 1 941 7 view .LVU247
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_NRST_MODE;
+ 757              		.loc 1 941 35 is_stmt 0 view .LVU248
+ 758 00ec 05F04051 		and	r1, r5, #805306368
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_NRST_MODE;
+ 759              		.loc 1 941 20 view .LVU249
+ 760 00f0 0B43     		orrs	r3, r3, r1
+ 761              	.LVL63:
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 762              		.loc 1 942 7 is_stmt 1 view .LVU250
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 763              		.loc 1 942 21 is_stmt 0 view .LVU251
+ 764 00f2 42F04052 		orr	r2, r2, #805306368
+ 765              	.LVL64:
+ 766              	.L60:
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 767              		.loc 1 945 5 is_stmt 1 view .LVU252
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 768              		.loc 1 945 8 is_stmt 0 view .LVU253
+ 769 00f6 14F4803F 		tst	r4, #65536
+ 770 00fa 04D0     		beq	.L61
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 771              		.loc 1 948 7 is_stmt 1 view .LVU254
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IRHEN;
+ 772              		.loc 1 951 7 view .LVU255
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IRHEN;
+ 773              		.loc 1 951 35 is_stmt 0 view .LVU256
+ 774 00fc 05F08045 		and	r5, r5, #1073741824
+ 775              	.LVL65:
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       optr_reg_mask |= FLASH_OPTR_IRHEN;
+ 776              		.loc 1 951 20 view .LVU257
+ARM GAS  /tmp/ccudk1nZ.s 			page 42
+
+
+ 777 0100 2B43     		orrs	r3, r3, r5
+ 778              	.LVL66:
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 779              		.loc 1 952 7 is_stmt 1 view .LVU258
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 780              		.loc 1 952 21 is_stmt 0 view .LVU259
+ 781 0102 42F08042 		orr	r2, r2, #1073741824
+ 782              	.LVL67:
+ 783              	.L61:
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 784              		.loc 1 956 5 is_stmt 1 view .LVU260
+ 785 0106 0748     		ldr	r0, .L64
+ 786 0108 016A     		ldr	r1, [r0, #32]
+ 787 010a 21EA0202 		bic	r2, r1, r2
+ 788              	.LVL68:
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 789              		.loc 1 956 5 is_stmt 0 view .LVU261
+ 790 010e 1343     		orrs	r3, r3, r2
+ 791              	.LVL69:
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 792              		.loc 1 956 5 view .LVU262
+ 793 0110 0362     		str	r3, [r0, #32]
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 794              		.loc 1 959 5 is_stmt 1 view .LVU263
+ 795 0112 4369     		ldr	r3, [r0, #20]
+ 796 0114 43F40033 		orr	r3, r3, #131072
+ 797 0118 4361     		str	r3, [r0, #20]
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 798              		.loc 1 962 5 view .LVU264
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 799              		.loc 1 962 14 is_stmt 0 view .LVU265
+ 800 011a 4FF47A70 		mov	r0, #1000
+ 801 011e FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 802              	.LVL70:
+ 803              	.L46:
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 804              		.loc 1 965 3 is_stmt 1 view .LVU266
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 805              		.loc 1 966 1 is_stmt 0 view .LVU267
+ 806 0122 38BD     		pop	{r3, r4, r5, pc}
+ 807              	.LVL71:
+ 808              	.L65:
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 809              		.loc 1 966 1 view .LVU268
+ 810              		.align	2
+ 811              	.L64:
+ 812 0124 00200240 		.word	1073881088
+ 813              		.cfi_endproc
+ 814              	.LFE341:
+ 816              		.section	.text.FLASH_OB_PCROPConfig,"ax",%progbits
+ 817              		.align	1
+ 818              		.syntax unified
+ 819              		.thumb
+ 820              		.thumb_func
+ 822              	FLASH_OB_PCROPConfig:
+ 823              	.LVL72:
+ 824              	.LFB342:
+ARM GAS  /tmp/ccudk1nZ.s 			page 43
+
+
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 825              		.loc 1 986 1 is_stmt 1 view -0
+ 826              		.cfi_startproc
+ 827              		@ args = 0, pretend = 0, frame = 0
+ 828              		@ frame_needed = 0, uses_anonymous_args = 0
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 829              		.loc 1 986 1 is_stmt 0 view .LVU270
+ 830 0000 70B5     		push	{r4, r5, r6, lr}
+ 831              	.LCFI5:
+ 832              		.cfi_def_cfa_offset 16
+ 833              		.cfi_offset 4, -16
+ 834              		.cfi_offset 5, -12
+ 835              		.cfi_offset 6, -8
+ 836              		.cfi_offset 14, -4
+ 837 0002 0446     		mov	r4, r0
+ 838 0004 0E46     		mov	r6, r1
+ 839 0006 1546     		mov	r5, r2
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t reg_value;
+ 840              		.loc 1 987 3 is_stmt 1 view .LVU271
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t bank1_addr;
+ 841              		.loc 1 988 3 view .LVU272
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 842              		.loc 1 989 3 view .LVU273
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
+ 843              		.loc 1 995 3 view .LVU274
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
+ 844              		.loc 1 996 3 view .LVU275
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
+ 845              		.loc 1 997 3 view .LVU276
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 846              		.loc 1 998 3 view .LVU277
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 847              		.loc 1 1001 3 view .LVU278
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 848              		.loc 1 1001 12 is_stmt 0 view .LVU279
+ 849 0008 4FF47A70 		mov	r0, #1000
+ 850              	.LVL73:
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 851              		.loc 1 1001 12 view .LVU280
+ 852 000c FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 853              	.LVL74:
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 854              		.loc 1 1003 3 is_stmt 1 view .LVU281
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 855              		.loc 1 1003 6 is_stmt 0 view .LVU282
+ 856 0010 38BB     		cbnz	r0, .L67
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 857              		.loc 1 1018 5 is_stmt 1 view .LVU283
+ 858              	.LVL75:
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 859              		.loc 1 1050 7 view .LVU284
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 860              		.loc 1 1050 10 is_stmt 0 view .LVU285
+ 861 0012 14F0010F 		tst	r4, #1
+ 862 0016 14D0     		beq	.L68
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
+ 863              		.loc 1 1052 9 is_stmt 1 view .LVU286
+ARM GAS  /tmp/ccudk1nZ.s 			page 44
+
+
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
+ 864              		.loc 1 1052 38 is_stmt 0 view .LVU287
+ 865 0018 06F17841 		add	r1, r6, #-134217728
+ 866              	.LVL76:
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 867              		.loc 1 1053 9 is_stmt 1 view .LVU288
+ 868 001c 114A     		ldr	r2, .L70
+ 869 001e 536A     		ldr	r3, [r2, #36]
+ 870 0020 23F47F53 		bic	r3, r3, #16320
+ 871 0024 23F03F03 		bic	r3, r3, #63
+ 872 0028 43EAD103 		orr	r3, r3, r1, lsr #3
+ 873 002c 5362     		str	r3, [r2, #36]
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
+ 874              		.loc 1 1055 9 view .LVU289
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
+ 875              		.loc 1 1055 36 is_stmt 0 view .LVU290
+ 876 002e 05F17845 		add	r5, r5, #-134217728
+ 877              	.LVL77:
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+ 878              		.loc 1 1056 9 is_stmt 1 view .LVU291
+ 879 0032 936A     		ldr	r3, [r2, #40]
+ 880 0034 23F47F53 		bic	r3, r3, #16320
+ 881 0038 23F03F03 		bic	r3, r3, #63
+ 882 003c 43EAD503 		orr	r3, r3, r5, lsr #3
+ 883 0040 9362     		str	r3, [r2, #40]
+ 884              	.LVL78:
+ 885              	.L68:
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 886              		.loc 1 1071 7 view .LVU292
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 887              		.loc 1 1074 5 view .LVU293
+ 888 0042 084A     		ldr	r2, .L70
+ 889 0044 936A     		ldr	r3, [r2, #40]
+ 890 0046 23F00043 		bic	r3, r3, #-2147483648
+ 891 004a 04F00044 		and	r4, r4, #-2147483648
+ 892              	.LVL79:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 893              		.loc 1 1074 5 is_stmt 0 view .LVU294
+ 894 004e 1C43     		orrs	r4, r4, r3
+ 895 0050 9462     		str	r4, [r2, #40]
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 896              		.loc 1 1077 5 is_stmt 1 view .LVU295
+ 897 0052 5369     		ldr	r3, [r2, #20]
+ 898 0054 43F40033 		orr	r3, r3, #131072
+ 899 0058 5361     		str	r3, [r2, #20]
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 900              		.loc 1 1080 5 view .LVU296
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 901              		.loc 1 1080 14 is_stmt 0 view .LVU297
+ 902 005a 4FF47A70 		mov	r0, #1000
+ 903 005e FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 904              	.LVL80:
+ 905              	.L67:
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 906              		.loc 1 1083 3 is_stmt 1 view .LVU298
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 907              		.loc 1 1084 1 is_stmt 0 view .LVU299
+ARM GAS  /tmp/ccudk1nZ.s 			page 45
+
+
+ 908 0062 70BD     		pop	{r4, r5, r6, pc}
+ 909              	.LVL81:
+ 910              	.L71:
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 911              		.loc 1 1084 1 view .LVU300
+ 912              		.align	2
+ 913              	.L70:
+ 914 0064 00200240 		.word	1073881088
+ 915              		.cfi_endproc
+ 916              	.LFE342:
+ 918              		.section	.text.FLASH_OB_SecMemConfig,"ax",%progbits
+ 919              		.align	1
+ 920              		.syntax unified
+ 921              		.thumb
+ 922              		.thumb_func
+ 924              	FLASH_OB_SecMemConfig:
+ 925              	.LVL82:
+ 926              	.LFB343:
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 927              		.loc 1 1104 1 is_stmt 1 view -0
+ 928              		.cfi_startproc
+ 929              		@ args = 0, pretend = 0, frame = 0
+ 930              		@ frame_needed = 0, uses_anonymous_args = 0
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 931              		.loc 1 1104 1 is_stmt 0 view .LVU302
+ 932 0000 38B5     		push	{r3, r4, r5, lr}
+ 933              	.LCFI6:
+ 934              		.cfi_def_cfa_offset 16
+ 935              		.cfi_offset 3, -16
+ 936              		.cfi_offset 4, -12
+ 937              		.cfi_offset 5, -8
+ 938              		.cfi_offset 14, -4
+ 939 0002 0446     		mov	r4, r0
+ 940 0004 0D46     		mov	r5, r1
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 941              		.loc 1 1105 3 is_stmt 1 view .LVU303
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   assert_param(IS_OB_SECMEM_SIZE(SecSize));
+ 942              		.loc 1 1108 3 view .LVU304
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 943              		.loc 1 1109 3 view .LVU305
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 944              		.loc 1 1112 3 view .LVU306
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 945              		.loc 1 1112 12 is_stmt 0 view .LVU307
+ 946 0006 4FF47A70 		mov	r0, #1000
+ 947              	.LVL83:
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 948              		.loc 1 1112 12 view .LVU308
+ 949 000a FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 950              	.LVL84:
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 951              		.loc 1 1114 3 is_stmt 1 view .LVU309
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 952              		.loc 1 1114 6 is_stmt 0 view .LVU310
+ 953 000e 50B9     		cbnz	r0, .L73
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 954              		.loc 1 1117 5 is_stmt 1 view .LVU311
+ARM GAS  /tmp/ccudk1nZ.s 			page 46
+
+
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 955              		.loc 1 1117 8 is_stmt 0 view .LVU312
+ 956 0010 012C     		cmp	r4, #1
+ 957 0012 09D0     		beq	.L76
+ 958              	.L74:
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 959              		.loc 1 1133 5 is_stmt 1 view .LVU313
+ 960 0014 084A     		ldr	r2, .L77
+ 961 0016 5369     		ldr	r3, [r2, #20]
+ 962 0018 43F40033 		orr	r3, r3, #131072
+ 963 001c 5361     		str	r3, [r2, #20]
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 964              		.loc 1 1136 5 view .LVU314
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 965              		.loc 1 1136 14 is_stmt 0 view .LVU315
+ 966 001e 4FF47A70 		mov	r0, #1000
+ 967 0022 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 968              	.LVL85:
+ 969              	.L73:
+1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 970              		.loc 1 1139 3 is_stmt 1 view .LVU316
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 971              		.loc 1 1140 1 is_stmt 0 view .LVU317
+ 972 0026 38BD     		pop	{r3, r4, r5, pc}
+ 973              	.LVL86:
+ 974              	.L76:
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 975              		.loc 1 1119 7 is_stmt 1 view .LVU318
+ 976 0028 034A     		ldr	r2, .L77
+ 977 002a 136F     		ldr	r3, [r2, #112]
+ 978 002c 23F07F03 		bic	r3, r3, #127
+ 979 0030 2B43     		orrs	r3, r3, r5
+ 980 0032 1367     		str	r3, [r2, #112]
+ 981 0034 EEE7     		b	.L74
+ 982              	.L78:
+ 983 0036 00BF     		.align	2
+ 984              	.L77:
+ 985 0038 00200240 		.word	1073881088
+ 986              		.cfi_endproc
+ 987              	.LFE343:
+ 989              		.section	.text.FLASH_OB_BootLockConfig,"ax",%progbits
+ 990              		.align	1
+ 991              		.syntax unified
+ 992              		.thumb
+ 993              		.thumb_func
+ 995              	FLASH_OB_BootLockConfig:
+ 996              	.LVL87:
+ 997              	.LFB344:
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 998              		.loc 1 1157 1 view -0
+ 999              		.cfi_startproc
+ 1000              		@ args = 0, pretend = 0, frame = 0
+ 1001              		@ frame_needed = 0, uses_anonymous_args = 0
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 1002              		.loc 1 1157 1 is_stmt 0 view .LVU320
+ 1003 0000 10B5     		push	{r4, lr}
+ 1004              	.LCFI7:
+ARM GAS  /tmp/ccudk1nZ.s 			page 47
+
+
+ 1005              		.cfi_def_cfa_offset 8
+ 1006              		.cfi_offset 4, -8
+ 1007              		.cfi_offset 14, -4
+ 1008 0002 0446     		mov	r4, r0
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1009              		.loc 1 1158 3 is_stmt 1 view .LVU321
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1010              		.loc 1 1161 3 view .LVU322
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1011              		.loc 1 1164 3 view .LVU323
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1012              		.loc 1 1164 12 is_stmt 0 view .LVU324
+ 1013 0004 4FF47A70 		mov	r0, #1000
+ 1014              	.LVL88:
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1015              		.loc 1 1164 12 view .LVU325
+ 1016 0008 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1017              	.LVL89:
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1018              		.loc 1 1166 3 is_stmt 1 view .LVU326
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1019              		.loc 1 1166 6 is_stmt 0 view .LVU327
+ 1020 000c 00B1     		cbz	r0, .L82
+ 1021              	.L80:
+ 1022              	.LVL90:
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1023              		.loc 1 1177 3 is_stmt 1 view .LVU328
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1024              		.loc 1 1178 1 is_stmt 0 view .LVU329
+ 1025 000e 10BD     		pop	{r4, pc}
+ 1026              	.LVL91:
+ 1027              	.L82:
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1028              		.loc 1 1168 5 is_stmt 1 view .LVU330
+ 1029 0010 074A     		ldr	r2, .L83
+ 1030 0012 136F     		ldr	r3, [r2, #112]
+ 1031 0014 23F48033 		bic	r3, r3, #65536
+ 1032 0018 2343     		orrs	r3, r3, r4
+ 1033 001a 1367     		str	r3, [r2, #112]
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1034              		.loc 1 1171 5 view .LVU331
+ 1035 001c 5369     		ldr	r3, [r2, #20]
+ 1036 001e 43F40033 		orr	r3, r3, #131072
+ 1037 0022 5361     		str	r3, [r2, #20]
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1038              		.loc 1 1174 5 view .LVU332
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1039              		.loc 1 1174 14 is_stmt 0 view .LVU333
+ 1040 0024 4FF47A70 		mov	r0, #1000
+ 1041 0028 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1042              	.LVL92:
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1043              		.loc 1 1174 14 view .LVU334
+ 1044 002c EFE7     		b	.L80
+ 1045              	.L84:
+ 1046 002e 00BF     		.align	2
+ 1047              	.L83:
+ARM GAS  /tmp/ccudk1nZ.s 			page 48
+
+
+ 1048 0030 00200240 		.word	1073881088
+ 1049              		.cfi_endproc
+ 1050              	.LFE344:
+ 1052              		.section	.text.HAL_FLASHEx_OBProgram,"ax",%progbits
+ 1053              		.align	1
+ 1054              		.global	HAL_FLASHEx_OBProgram
+ 1055              		.syntax unified
+ 1056              		.thumb
+ 1057              		.thumb_func
+ 1059              	HAL_FLASHEx_OBProgram:
+ 1060              	.LVL93:
+ 1061              	.LFB331:
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1062              		.loc 1 311 1 is_stmt 1 view -0
+ 1063              		.cfi_startproc
+ 1064              		@ args = 0, pretend = 0, frame = 0
+ 1065              		@ frame_needed = 0, uses_anonymous_args = 0
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1066              		.loc 1 311 1 is_stmt 0 view .LVU336
+ 1067 0000 38B5     		push	{r3, r4, r5, lr}
+ 1068              	.LCFI8:
+ 1069              		.cfi_def_cfa_offset 16
+ 1070              		.cfi_offset 3, -16
+ 1071              		.cfi_offset 4, -12
+ 1072              		.cfi_offset 5, -8
+ 1073              		.cfi_offset 14, -4
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1074              		.loc 1 312 3 is_stmt 1 view .LVU337
+ 1075              	.LVL94:
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1076              		.loc 1 315 3 view .LVU338
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1077              		.loc 1 318 3 view .LVU339
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1078              		.loc 1 318 3 view .LVU340
+ 1079 0002 2E4B     		ldr	r3, .L108
+ 1080 0004 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 1081 0006 012B     		cmp	r3, #1
+ 1082 0008 56D0     		beq	.L93
+ 1083 000a 0446     		mov	r4, r0
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1084              		.loc 1 318 3 discriminator 2 view .LVU341
+ 1085 000c 2B4B     		ldr	r3, .L108
+ 1086 000e 0122     		movs	r2, #1
+ 1087 0010 1A70     		strb	r2, [r3]
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1088              		.loc 1 318 3 discriminator 2 view .LVU342
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1089              		.loc 1 320 3 discriminator 2 view .LVU343
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1090              		.loc 1 320 20 is_stmt 0 discriminator 2 view .LVU344
+ 1091 0012 0022     		movs	r2, #0
+ 1092 0014 5A60     		str	r2, [r3, #4]
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1093              		.loc 1 323 3 is_stmt 1 discriminator 2 view .LVU345
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1094              		.loc 1 323 15 is_stmt 0 discriminator 2 view .LVU346
+ARM GAS  /tmp/ccudk1nZ.s 			page 49
+
+
+ 1095 0016 0368     		ldr	r3, [r0]
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1096              		.loc 1 323 6 discriminator 2 view .LVU347
+ 1097 0018 13F0010F 		tst	r3, #1
+ 1098 001c 1DD1     		bne	.L102
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1099              		.loc 1 312 21 view .LVU348
+ 1100 001e 0025     		movs	r5, #0
+ 1101              	.LVL95:
+ 1102              	.L87:
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1103              		.loc 1 333 3 is_stmt 1 view .LVU349
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1104              		.loc 1 333 15 is_stmt 0 view .LVU350
+ 1105 0020 2368     		ldr	r3, [r4]
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1106              		.loc 1 333 6 view .LVU351
+ 1107 0022 13F0020F 		tst	r3, #2
+ 1108 0026 22D1     		bne	.L103
+ 1109              	.LVL96:
+ 1110              	.L88:
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1111              		.loc 1 343 3 is_stmt 1 view .LVU352
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1112              		.loc 1 343 15 is_stmt 0 view .LVU353
+ 1113 0028 2368     		ldr	r3, [r4]
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1114              		.loc 1 343 6 view .LVU354
+ 1115 002a 13F0040F 		tst	r3, #4
+ 1116 002e 25D1     		bne	.L104
+ 1117              	.LVL97:
+ 1118              	.L89:
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1119              		.loc 1 353 3 is_stmt 1 view .LVU355
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1120              		.loc 1 353 15 is_stmt 0 view .LVU356
+ 1121 0030 2368     		ldr	r3, [r4]
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1122              		.loc 1 353 6 view .LVU357
+ 1123 0032 13F0080F 		tst	r3, #8
+ 1124 0036 03D0     		beq	.L90
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1125              		.loc 1 355 5 is_stmt 1 view .LVU358
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1126              		.loc 1 355 16 is_stmt 0 view .LVU359
+ 1127 0038 216A     		ldr	r1, [r4, #32]
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1128              		.loc 1 355 43 view .LVU360
+ 1129 003a 626A     		ldr	r2, [r4, #36]
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1130              		.loc 1 355 8 view .LVU361
+ 1131 003c 9142     		cmp	r1, r2
+ 1132 003e 25D1     		bne	.L105
+ 1133              	.LVL98:
+ 1134              	.L90:
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1135              		.loc 1 366 3 is_stmt 1 view .LVU362
+ARM GAS  /tmp/ccudk1nZ.s 			page 50
+
+
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1136              		.loc 1 366 15 is_stmt 0 view .LVU363
+ 1137 0040 2368     		ldr	r3, [r4]
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1138              		.loc 1 366 6 view .LVU364
+ 1139 0042 13F0200F 		tst	r3, #32
+ 1140 0046 28D1     		bne	.L106
+ 1141              	.LVL99:
+ 1142              	.L91:
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1143              		.loc 1 376 3 is_stmt 1 view .LVU365
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1144              		.loc 1 376 15 is_stmt 0 view .LVU366
+ 1145 0048 2368     		ldr	r3, [r4]
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1146              		.loc 1 376 6 view .LVU367
+ 1147 004a 13F0100F 		tst	r3, #16
+ 1148 004e 2CD1     		bne	.L107
+ 1149              	.LVL100:
+ 1150              	.L92:
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1151              		.loc 1 386 3 is_stmt 1 view .LVU368
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1152              		.loc 1 386 3 view .LVU369
+ 1153 0050 1A4B     		ldr	r3, .L108
+ 1154 0052 0022     		movs	r2, #0
+ 1155 0054 1A70     		strb	r2, [r3]
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1156              		.loc 1 386 3 view .LVU370
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1157              		.loc 1 388 3 view .LVU371
+ 1158              	.LVL101:
+ 1159              	.L86:
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1160              		.loc 1 389 1 is_stmt 0 view .LVU372
+ 1161 0056 2846     		mov	r0, r5
+ 1162 0058 38BD     		pop	{r3, r4, r5, pc}
+ 1163              	.LVL102:
+ 1164              	.L102:
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1165              		.loc 1 326 5 is_stmt 1 view .LVU373
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1166              		.loc 1 326 9 is_stmt 0 view .LVU374
+ 1167 005a C268     		ldr	r2, [r0, #12]
+ 1168 005c 8168     		ldr	r1, [r0, #8]
+ 1169 005e 4068     		ldr	r0, [r0, #4]
+ 1170              	.LVL103:
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1171              		.loc 1 326 9 view .LVU375
+ 1172 0060 FFF7FEFF 		bl	FLASH_OB_WRPConfig
+ 1173              	.LVL104:
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1174              		.loc 1 326 8 view .LVU376
+ 1175 0064 0546     		mov	r5, r0
+ 1176 0066 0028     		cmp	r0, #0
+ 1177 0068 DAD0     		beq	.L87
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ARM GAS  /tmp/ccudk1nZ.s 			page 51
+
+
+ 1178              		.loc 1 328 14 view .LVU377
+ 1179 006a 0125     		movs	r5, #1
+ 1180 006c D8E7     		b	.L87
+ 1181              	.LVL105:
+ 1182              	.L103:
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1183              		.loc 1 336 5 is_stmt 1 view .LVU378
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1184              		.loc 1 336 9 is_stmt 0 view .LVU379
+ 1185 006e 2069     		ldr	r0, [r4, #16]
+ 1186 0070 FFF7FEFF 		bl	FLASH_OB_RDPConfig
+ 1187              	.LVL106:
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1188              		.loc 1 336 8 view .LVU380
+ 1189 0074 0028     		cmp	r0, #0
+ 1190 0076 D7D0     		beq	.L88
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1191              		.loc 1 338 14 view .LVU381
+ 1192 0078 0125     		movs	r5, #1
+ 1193              	.LVL107:
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1194              		.loc 1 338 14 view .LVU382
+ 1195 007a D5E7     		b	.L88
+ 1196              	.LVL108:
+ 1197              	.L104:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1198              		.loc 1 346 5 is_stmt 1 view .LVU383
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1199              		.loc 1 346 9 is_stmt 0 view .LVU384
+ 1200 007c A169     		ldr	r1, [r4, #24]
+ 1201 007e 6069     		ldr	r0, [r4, #20]
+ 1202 0080 FFF7FEFF 		bl	FLASH_OB_UserConfig
+ 1203              	.LVL109:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1204              		.loc 1 346 8 view .LVU385
+ 1205 0084 0028     		cmp	r0, #0
+ 1206 0086 D3D0     		beq	.L89
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1207              		.loc 1 348 14 view .LVU386
+ 1208 0088 0125     		movs	r5, #1
+ 1209              	.LVL110:
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1210              		.loc 1 348 14 view .LVU387
+ 1211 008a D1E7     		b	.L89
+ 1212              	.LVL111:
+ 1213              	.L105:
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1214              		.loc 1 358 7 is_stmt 1 view .LVU388
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1215              		.loc 1 358 11 is_stmt 0 view .LVU389
+ 1216 008c E069     		ldr	r0, [r4, #28]
+ 1217 008e FFF7FEFF 		bl	FLASH_OB_PCROPConfig
+ 1218              	.LVL112:
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1219              		.loc 1 358 10 view .LVU390
+ 1220 0092 0028     		cmp	r0, #0
+ 1221 0094 D4D0     		beq	.L90
+ARM GAS  /tmp/ccudk1nZ.s 			page 52
+
+
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+ 1222              		.loc 1 360 16 view .LVU391
+ 1223 0096 0125     		movs	r5, #1
+ 1224              	.LVL113:
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+ 1225              		.loc 1 360 16 view .LVU392
+ 1226 0098 D2E7     		b	.L90
+ 1227              	.LVL114:
+ 1228              	.L106:
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1229              		.loc 1 369 5 is_stmt 1 view .LVU393
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1230              		.loc 1 369 9 is_stmt 0 view .LVU394
+ 1231 009a 216B     		ldr	r1, [r4, #48]
+ 1232 009c E06A     		ldr	r0, [r4, #44]
+ 1233 009e FFF7FEFF 		bl	FLASH_OB_SecMemConfig
+ 1234              	.LVL115:
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1235              		.loc 1 369 8 view .LVU395
+ 1236 00a2 0028     		cmp	r0, #0
+ 1237 00a4 D0D0     		beq	.L91
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1238              		.loc 1 371 14 view .LVU396
+ 1239 00a6 0125     		movs	r5, #1
+ 1240              	.LVL116:
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1241              		.loc 1 371 14 view .LVU397
+ 1242 00a8 CEE7     		b	.L91
+ 1243              	.LVL117:
+ 1244              	.L107:
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1245              		.loc 1 379 5 is_stmt 1 view .LVU398
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1246              		.loc 1 379 9 is_stmt 0 view .LVU399
+ 1247 00aa A06A     		ldr	r0, [r4, #40]
+ 1248 00ac FFF7FEFF 		bl	FLASH_OB_BootLockConfig
+ 1249              	.LVL118:
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1250              		.loc 1 379 8 view .LVU400
+ 1251 00b0 0028     		cmp	r0, #0
+ 1252 00b2 CDD0     		beq	.L92
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1253              		.loc 1 381 14 view .LVU401
+ 1254 00b4 0125     		movs	r5, #1
+ 1255              	.LVL119:
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1256              		.loc 1 381 14 view .LVU402
+ 1257 00b6 CBE7     		b	.L92
+ 1258              	.LVL120:
+ 1259              	.L93:
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1260              		.loc 1 318 3 view .LVU403
+ 1261 00b8 0225     		movs	r5, #2
+ 1262 00ba CCE7     		b	.L86
+ 1263              	.L109:
+ 1264              		.align	2
+ 1265              	.L108:
+ARM GAS  /tmp/ccudk1nZ.s 			page 53
+
+
+ 1266 00bc 00000000 		.word	pFlash
+ 1267              		.cfi_endproc
+ 1268              	.LFE331:
+ 1270              		.section	.text.HAL_FLASHEx_OBGetConfig,"ax",%progbits
+ 1271              		.align	1
+ 1272              		.global	HAL_FLASHEx_OBGetConfig
+ 1273              		.syntax unified
+ 1274              		.thumb
+ 1275              		.thumb_func
+ 1277              	HAL_FLASHEx_OBGetConfig:
+ 1278              	.LVL121:
+ 1279              	.LFB332:
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
+ 1280              		.loc 1 400 1 is_stmt 1 view -0
+ 1281              		.cfi_startproc
+ 1282              		@ args = 0, pretend = 0, frame = 0
+ 1283              		@ frame_needed = 0, uses_anonymous_args = 0
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
+ 1284              		.loc 1 400 1 is_stmt 0 view .LVU405
+ 1285 0000 10B5     		push	{r4, lr}
+ 1286              	.LCFI9:
+ 1287              		.cfi_def_cfa_offset 8
+ 1288              		.cfi_offset 4, -8
+ 1289              		.cfi_offset 14, -4
+ 1290 0002 0446     		mov	r4, r0
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1291              		.loc 1 401 3 is_stmt 1 view .LVU406
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1292              		.loc 1 401 23 is_stmt 0 view .LVU407
+ 1293 0004 0623     		movs	r3, #6
+ 1294 0006 0360     		str	r3, [r0]
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 1295              		.loc 1 407 3 is_stmt 1 view .LVU408
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 1296              		.loc 1 407 15 is_stmt 0 view .LVU409
+ 1297 0008 4068     		ldr	r0, [r0, #4]
+ 1298              	.LVL122:
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 1299              		.loc 1 407 6 view .LVU410
+ 1300 000a 0128     		cmp	r0, #1
+ 1301 000c 13D9     		bls	.L115
+ 1302              	.L111:
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1303              		.loc 1 416 3 is_stmt 1 view .LVU411
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1304              		.loc 1 416 23 is_stmt 0 view .LVU412
+ 1305 000e FFF7FEFF 		bl	FLASH_OB_GetRDP
+ 1306              	.LVL123:
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1307              		.loc 1 416 21 view .LVU413
+ 1308 0012 2061     		str	r0, [r4, #16]
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1309              		.loc 1 419 3 is_stmt 1 view .LVU414
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1310              		.loc 1 419 25 is_stmt 0 view .LVU415
+ 1311 0014 FFF7FEFF 		bl	FLASH_OB_GetUser
+ 1312              	.LVL124:
+ARM GAS  /tmp/ccudk1nZ.s 			page 54
+
+
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1313              		.loc 1 419 23 view .LVU416
+ 1314 0018 A061     		str	r0, [r4, #24]
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 1315              		.loc 1 424 3 is_stmt 1 view .LVU417
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 1316              		.loc 1 424 14 is_stmt 0 view .LVU418
+ 1317 001a E369     		ldr	r3, [r4, #28]
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 1318              		.loc 1 424 6 view .LVU419
+ 1319 001c 012B     		cmp	r3, #1
+ 1320 001e 13D0     		beq	.L116
+ 1321              	.L112:
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1322              		.loc 1 432 3 is_stmt 1 view .LVU420
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1323              		.loc 1 432 10 is_stmt 0 view .LVU421
+ 1324 0020 2368     		ldr	r3, [r4]
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1325              		.loc 1 432 23 view .LVU422
+ 1326 0022 43F01003 		orr	r3, r3, #16
+ 1327 0026 2360     		str	r3, [r4]
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1328              		.loc 1 435 3 is_stmt 1 view .LVU423
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1329              		.loc 1 435 29 is_stmt 0 view .LVU424
+ 1330 0028 FFF7FEFF 		bl	FLASH_OB_GetBootLock
+ 1331              	.LVL125:
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1332              		.loc 1 435 27 view .LVU425
+ 1333 002c A062     		str	r0, [r4, #40]
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 1334              		.loc 1 441 3 is_stmt 1 view .LVU426
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 1335              		.loc 1 441 14 is_stmt 0 view .LVU427
+ 1336 002e E06A     		ldr	r0, [r4, #44]
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 1337              		.loc 1 441 6 view .LVU428
+ 1338 0030 0128     		cmp	r0, #1
+ 1339 0032 16D0     		beq	.L117
+ 1340              	.L110:
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1341              		.loc 1 447 1 view .LVU429
+ 1342 0034 10BD     		pop	{r4, pc}
+ 1343              	.LVL126:
+ 1344              	.L115:
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Get write protection on the selected area */
+ 1345              		.loc 1 410 5 is_stmt 1 view .LVU430
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Get write protection on the selected area */
+ 1346              		.loc 1 410 25 is_stmt 0 view .LVU431
+ 1347 0036 2246     		mov	r2, r4
+ 1348 0038 0723     		movs	r3, #7
+ 1349 003a 42F80C3B 		str	r3, [r2], #12
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1350              		.loc 1 412 5 is_stmt 1 view .LVU432
+ 1351 003e 04F10801 		add	r1, r4, #8
+ 1352 0042 FFF7FEFF 		bl	FLASH_OB_GetWRP
+ARM GAS  /tmp/ccudk1nZ.s 			page 55
+
+
+ 1353              	.LVL127:
+ 1354 0046 E2E7     		b	.L111
+ 1355              	.L116:
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Get the Proprietary code readout protection */
+ 1356              		.loc 1 427 5 view .LVU433
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Get the Proprietary code readout protection */
+ 1357              		.loc 1 427 12 is_stmt 0 view .LVU434
+ 1358 0048 2368     		ldr	r3, [r4]
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Get the Proprietary code readout protection */
+ 1359              		.loc 1 427 25 view .LVU435
+ 1360 004a 43F00803 		orr	r3, r3, #8
+ 1361 004e 2246     		mov	r2, r4
+ 1362 0050 42F8243B 		str	r3, [r2], #36
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1363              		.loc 1 429 5 is_stmt 1 view .LVU436
+ 1364 0054 04F12001 		add	r1, r4, #32
+ 1365 0058 04F11C00 		add	r0, r4, #28
+ 1366 005c FFF7FEFF 		bl	FLASH_OB_GetPCROP
+ 1367              	.LVL128:
+ 1368 0060 DEE7     		b	.L112
+ 1369              	.L117:
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     FLASH_OB_GetSecMem(pOBInit->SecBank, &(pOBInit->SecSize));
+ 1370              		.loc 1 444 5 view .LVU437
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     FLASH_OB_GetSecMem(pOBInit->SecBank, &(pOBInit->SecSize));
+ 1371              		.loc 1 444 12 is_stmt 0 view .LVU438
+ 1372 0062 2368     		ldr	r3, [r4]
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     FLASH_OB_GetSecMem(pOBInit->SecBank, &(pOBInit->SecSize));
+ 1373              		.loc 1 444 25 view .LVU439
+ 1374 0064 43F02003 		orr	r3, r3, #32
+ 1375 0068 2146     		mov	r1, r4
+ 1376 006a 41F8303B 		str	r3, [r1], #48
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1377              		.loc 1 445 5 is_stmt 1 view .LVU440
+ 1378 006e FFF7FEFF 		bl	FLASH_OB_GetSecMem
+ 1379              	.LVL129:
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1380              		.loc 1 447 1 is_stmt 0 view .LVU441
+ 1381 0072 DFE7     		b	.L110
+ 1382              		.cfi_endproc
+ 1383              	.LFE332:
+ 1385              		.section	.text.HAL_FLASHEx_EnableSecMemProtection,"ax",%progbits
+ 1386              		.align	1
+ 1387              		.global	HAL_FLASHEx_EnableSecMemProtection
+ 1388              		.syntax unified
+ 1389              		.thumb
+ 1390              		.thumb_func
+ 1392              	HAL_FLASHEx_EnableSecMemProtection:
+ 1393              	.LVL130:
+ 1394              	.LFB333:
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #if defined (FLASH_OPTR_DBANK)
+ 1395              		.loc 1 460 1 is_stmt 1 view -0
+ 1396              		.cfi_startproc
+ 1397              		@ args = 0, pretend = 0, frame = 0
+ 1398              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1399              		@ link register save eliminated.
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1400              		.loc 1 482 5 view .LVU443
+ARM GAS  /tmp/ccudk1nZ.s 			page 56
+
+
+ 1401 0000 034A     		ldr	r2, .L119
+ 1402 0002 5369     		ldr	r3, [r2, #20]
+ 1403 0004 43F08053 		orr	r3, r3, #268435456
+ 1404 0008 5361     		str	r3, [r2, #20]
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1405              		.loc 1 485 3 view .LVU444
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1406              		.loc 1 486 1 is_stmt 0 view .LVU445
+ 1407 000a 0020     		movs	r0, #0
+ 1408              	.LVL131:
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1409              		.loc 1 486 1 view .LVU446
+ 1410 000c 7047     		bx	lr
+ 1411              	.L120:
+ 1412 000e 00BF     		.align	2
+ 1413              	.L119:
+ 1414 0010 00200240 		.word	1073881088
+ 1415              		.cfi_endproc
+ 1416              	.LFE333:
+ 1418              		.section	.text.HAL_FLASHEx_EnableDebugger,"ax",%progbits
+ 1419              		.align	1
+ 1420              		.global	HAL_FLASHEx_EnableDebugger
+ 1421              		.syntax unified
+ 1422              		.thumb
+ 1423              		.thumb_func
+ 1425              	HAL_FLASHEx_EnableDebugger:
+ 1426              	.LFB334:
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   FLASH->ACR |= FLASH_ACR_DBG_SWEN;
+ 1427              		.loc 1 494 1 is_stmt 1 view -0
+ 1428              		.cfi_startproc
+ 1429              		@ args = 0, pretend = 0, frame = 0
+ 1430              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1431              		@ link register save eliminated.
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1432              		.loc 1 495 3 view .LVU448
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1433              		.loc 1 495 8 is_stmt 0 view .LVU449
+ 1434 0000 024A     		ldr	r2, .L122
+ 1435 0002 1368     		ldr	r3, [r2]
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1436              		.loc 1 495 14 view .LVU450
+ 1437 0004 43F48023 		orr	r3, r3, #262144
+ 1438 0008 1360     		str	r3, [r2]
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1439              		.loc 1 496 1 view .LVU451
+ 1440 000a 7047     		bx	lr
+ 1441              	.L123:
+ 1442              		.align	2
+ 1443              	.L122:
+ 1444 000c 00200240 		.word	1073881088
+ 1445              		.cfi_endproc
+ 1446              	.LFE334:
+ 1448              		.section	.text.HAL_FLASHEx_DisableDebugger,"ax",%progbits
+ 1449              		.align	1
+ 1450              		.global	HAL_FLASHEx_DisableDebugger
+ 1451              		.syntax unified
+ 1452              		.thumb
+ARM GAS  /tmp/ccudk1nZ.s 			page 57
+
+
+ 1453              		.thumb_func
+ 1455              	HAL_FLASHEx_DisableDebugger:
+ 1456              	.LFB335:
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   FLASH->ACR &= ~FLASH_ACR_DBG_SWEN;
+ 1457              		.loc 1 506 1 is_stmt 1 view -0
+ 1458              		.cfi_startproc
+ 1459              		@ args = 0, pretend = 0, frame = 0
+ 1460              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1461              		@ link register save eliminated.
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1462              		.loc 1 507 3 view .LVU453
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1463              		.loc 1 507 8 is_stmt 0 view .LVU454
+ 1464 0000 024A     		ldr	r2, .L125
+ 1465 0002 1368     		ldr	r3, [r2]
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1466              		.loc 1 507 14 view .LVU455
+ 1467 0004 23F48023 		bic	r3, r3, #262144
+ 1468 0008 1360     		str	r3, [r2]
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1469              		.loc 1 508 1 view .LVU456
+ 1470 000a 7047     		bx	lr
+ 1471              	.L126:
+ 1472              		.align	2
+ 1473              	.L125:
+ 1474 000c 00200240 		.word	1073881088
+ 1475              		.cfi_endproc
+ 1476              	.LFE335:
+ 1478              		.section	.text.FLASH_PageErase,"ax",%progbits
+ 1479              		.align	1
+ 1480              		.global	FLASH_PageErase
+ 1481              		.syntax unified
+ 1482              		.thumb
+ 1483              		.thumb_func
+ 1485              	FLASH_PageErase:
+ 1486              	.LVL132:
+ 1487              	.LFB337:
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   /* Check the parameters */
+ 1488              		.loc 1 579 1 is_stmt 1 view -0
+ 1489              		.cfi_startproc
+ 1490              		@ args = 0, pretend = 0, frame = 0
+ 1491              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1492              		@ link register save eliminated.
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1493              		.loc 1 581 3 view .LVU458
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   SET_BIT(FLASH->CR, FLASH_CR_PER);
+ 1494              		.loc 1 604 3 view .LVU459
+ 1495 0000 084B     		ldr	r3, .L128
+ 1496 0002 5A69     		ldr	r2, [r3, #20]
+ 1497 0004 22F4FC72 		bic	r2, r2, #504
+ 1498 0008 C000     		lsls	r0, r0, #3
+ 1499              	.LVL133:
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   SET_BIT(FLASH->CR, FLASH_CR_PER);
+ 1500              		.loc 1 604 3 is_stmt 0 view .LVU460
+ 1501 000a 00F4FF60 		and	r0, r0, #2040
+ 1502 000e 0243     		orrs	r2, r2, r0
+ 1503 0010 5A61     		str	r2, [r3, #20]
+ARM GAS  /tmp/ccudk1nZ.s 			page 58
+
+
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   SET_BIT(FLASH->CR, FLASH_CR_STRT);
+ 1504              		.loc 1 605 3 is_stmt 1 view .LVU461
+ 1505 0012 5A69     		ldr	r2, [r3, #20]
+ 1506 0014 42F00202 		orr	r2, r2, #2
+ 1507 0018 5A61     		str	r2, [r3, #20]
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1508              		.loc 1 606 3 view .LVU462
+ 1509 001a 5A69     		ldr	r2, [r3, #20]
+ 1510 001c 42F48032 		orr	r2, r2, #65536
+ 1511 0020 5A61     		str	r2, [r3, #20]
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1512              		.loc 1 607 1 is_stmt 0 view .LVU463
+ 1513 0022 7047     		bx	lr
+ 1514              	.L129:
+ 1515              		.align	2
+ 1516              	.L128:
+ 1517 0024 00200240 		.word	1073881088
+ 1518              		.cfi_endproc
+ 1519              	.LFE337:
+ 1521              		.section	.text.HAL_FLASHEx_Erase_IT,"ax",%progbits
+ 1522              		.align	1
+ 1523              		.global	HAL_FLASHEx_Erase_IT
+ 1524              		.syntax unified
+ 1525              		.thumb
+ 1526              		.thumb_func
+ 1528              	HAL_FLASHEx_Erase_IT:
+ 1529              	.LVL134:
+ 1530              	.LFB330:
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1531              		.loc 1 238 1 is_stmt 1 view -0
+ 1532              		.cfi_startproc
+ 1533              		@ args = 0, pretend = 0, frame = 0
+ 1534              		@ frame_needed = 0, uses_anonymous_args = 0
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1535              		.loc 1 239 3 view .LVU465
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1536              		.loc 1 242 3 view .LVU466
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1537              		.loc 1 242 3 view .LVU467
+ 1538 0000 294A     		ldr	r2, .L143
+ 1539 0002 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+ 1540 0004 012A     		cmp	r2, #1
+ 1541 0006 4DD0     		beq	.L137
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1542              		.loc 1 238 1 is_stmt 0 discriminator 2 view .LVU468
+ 1543 0008 08B5     		push	{r3, lr}
+ 1544              	.LCFI10:
+ 1545              		.cfi_def_cfa_offset 8
+ 1546              		.cfi_offset 3, -8
+ 1547              		.cfi_offset 14, -4
+ 1548 000a 0346     		mov	r3, r0
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1549              		.loc 1 242 3 is_stmt 1 discriminator 2 view .LVU469
+ 1550 000c 264A     		ldr	r2, .L143
+ 1551 000e 0121     		movs	r1, #1
+ 1552 0010 1170     		strb	r1, [r2]
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ARM GAS  /tmp/ccudk1nZ.s 			page 59
+
+
+ 1553              		.loc 1 242 3 discriminator 2 view .LVU470
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1554              		.loc 1 245 3 discriminator 2 view .LVU471
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1555              		.loc 1 247 3 discriminator 2 view .LVU472
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1556              		.loc 1 247 20 is_stmt 0 discriminator 2 view .LVU473
+ 1557 0012 0021     		movs	r1, #0
+ 1558 0014 5160     		str	r1, [r2, #4]
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1559              		.loc 1 250 3 is_stmt 1 discriminator 2 view .LVU474
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1560              		.loc 1 250 7 is_stmt 0 discriminator 2 view .LVU475
+ 1561 0016 254A     		ldr	r2, .L143+4
+ 1562 0018 1268     		ldr	r2, [r2]
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1563              		.loc 1 250 6 discriminator 2 view .LVU476
+ 1564 001a 12F4007F 		tst	r2, #512
+ 1565 001e 27D0     		beq	.L132
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1566              		.loc 1 252 5 is_stmt 1 view .LVU477
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1567              		.loc 1 252 9 is_stmt 0 view .LVU478
+ 1568 0020 224A     		ldr	r2, .L143+4
+ 1569 0022 1268     		ldr	r2, [r2]
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1570              		.loc 1 252 8 view .LVU479
+ 1571 0024 12F4806F 		tst	r2, #1024
+ 1572 0028 1ED0     		beq	.L133
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
+ 1573              		.loc 1 255 7 is_stmt 1 view .LVU480
+ 1574 002a 2049     		ldr	r1, .L143+4
+ 1575 002c 0A68     		ldr	r2, [r1]
+ 1576 002e 22F48062 		bic	r2, r2, #1024
+ 1577 0032 0A60     		str	r2, [r1]
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1578              		.loc 1 256 7 view .LVU481
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1579              		.loc 1 256 32 is_stmt 0 view .LVU482
+ 1580 0034 1C4A     		ldr	r2, .L143
+ 1581 0036 0321     		movs	r1, #3
+ 1582 0038 1177     		strb	r1, [r2, #28]
+ 1583              	.L134:
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1584              		.loc 1 275 3 is_stmt 1 discriminator 4 view .LVU483
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1585              		.loc 1 275 3 discriminator 4 view .LVU484
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1586              		.loc 1 275 3 discriminator 4 view .LVU485
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1587              		.loc 1 275 3 discriminator 4 view .LVU486
+ 1588 003a 1C49     		ldr	r1, .L143+4
+ 1589 003c 4A69     		ldr	r2, [r1, #20]
+ 1590 003e 42F04072 		orr	r2, r2, #50331648
+ 1591 0042 4A61     		str	r2, [r1, #20]
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1592              		.loc 1 275 3 discriminator 4 view .LVU487
+ARM GAS  /tmp/ccudk1nZ.s 			page 60
+
+
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1593              		.loc 1 277 3 discriminator 4 view .LVU488
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1594              		.loc 1 277 27 is_stmt 0 discriminator 4 view .LVU489
+ 1595 0044 5968     		ldr	r1, [r3, #4]
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1596              		.loc 1 277 15 discriminator 4 view .LVU490
+ 1597 0046 184A     		ldr	r2, .L143
+ 1598 0048 1161     		str	r1, [r2, #16]
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1599              		.loc 1 279 3 is_stmt 1 discriminator 4 view .LVU491
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1600              		.loc 1 279 17 is_stmt 0 discriminator 4 view .LVU492
+ 1601 004a 1A68     		ldr	r2, [r3]
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1602              		.loc 1 279 6 discriminator 4 view .LVU493
+ 1603 004c 012A     		cmp	r2, #1
+ 1604 004e 21D0     		beq	.L142
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.NbPagesToErase = pEraseInit->NbPages;
+ 1605              		.loc 1 288 5 is_stmt 1 view .LVU494
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.NbPagesToErase = pEraseInit->NbPages;
+ 1606              		.loc 1 288 29 is_stmt 0 view .LVU495
+ 1607 0050 154A     		ldr	r2, .L143
+ 1608 0052 0121     		movs	r1, #1
+ 1609 0054 1172     		strb	r1, [r2, #8]
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.Page = pEraseInit->Page;
+ 1610              		.loc 1 289 5 is_stmt 1 view .LVU496
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.Page = pEraseInit->Page;
+ 1611              		.loc 1 289 39 is_stmt 0 view .LVU497
+ 1612 0056 D968     		ldr	r1, [r3, #12]
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.Page = pEraseInit->Page;
+ 1613              		.loc 1 289 27 view .LVU498
+ 1614 0058 9161     		str	r1, [r2, #24]
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1615              		.loc 1 290 5 is_stmt 1 view .LVU499
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1616              		.loc 1 290 29 is_stmt 0 view .LVU500
+ 1617 005a 9868     		ldr	r0, [r3, #8]
+ 1618              	.LVL135:
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1619              		.loc 1 290 17 view .LVU501
+ 1620 005c 5061     		str	r0, [r2, #20]
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1621              		.loc 1 293 5 is_stmt 1 view .LVU502
+ 1622 005e 5968     		ldr	r1, [r3, #4]
+ 1623 0060 FFF7FEFF 		bl	FLASH_PageErase
+ 1624              	.LVL136:
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1625              		.loc 1 296 10 is_stmt 0 view .LVU503
+ 1626 0064 0020     		movs	r0, #0
+ 1627              	.L131:
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1628              		.loc 1 297 1 view .LVU504
+ 1629 0066 08BD     		pop	{r3, pc}
+ 1630              	.LVL137:
+ 1631              	.L133:
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ARM GAS  /tmp/ccudk1nZ.s 			page 61
+
+
+ 1632              		.loc 1 260 7 is_stmt 1 view .LVU505
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1633              		.loc 1 260 32 is_stmt 0 view .LVU506
+ 1634 0068 0F4A     		ldr	r2, .L143
+ 1635 006a 0121     		movs	r1, #1
+ 1636 006c 1177     		strb	r1, [r2, #28]
+ 1637 006e E4E7     		b	.L134
+ 1638              	.L132:
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1639              		.loc 1 263 8 is_stmt 1 view .LVU507
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1640              		.loc 1 263 12 is_stmt 0 view .LVU508
+ 1641 0070 0E4A     		ldr	r2, .L143+4
+ 1642 0072 1268     		ldr	r2, [r2]
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1643              		.loc 1 263 11 view .LVU509
+ 1644 0074 12F4806F 		tst	r2, #1024
+ 1645 0078 08D0     		beq	.L135
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+ 1646              		.loc 1 266 5 is_stmt 1 view .LVU510
+ 1647 007a 0C49     		ldr	r1, .L143+4
+ 1648 007c 0A68     		ldr	r2, [r1]
+ 1649 007e 22F48062 		bic	r2, r2, #1024
+ 1650 0082 0A60     		str	r2, [r1]
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1651              		.loc 1 267 5 view .LVU511
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1652              		.loc 1 267 30 is_stmt 0 view .LVU512
+ 1653 0084 084A     		ldr	r2, .L143
+ 1654 0086 0221     		movs	r1, #2
+ 1655 0088 1177     		strb	r1, [r2, #28]
+ 1656 008a D6E7     		b	.L134
+ 1657              	.L135:
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1658              		.loc 1 271 5 is_stmt 1 view .LVU513
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1659              		.loc 1 271 30 is_stmt 0 view .LVU514
+ 1660 008c 064A     		ldr	r2, .L143
+ 1661 008e 0021     		movs	r1, #0
+ 1662 0090 1177     		strb	r1, [r2, #28]
+ 1663 0092 D2E7     		b	.L134
+ 1664              	.L142:
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     FLASH_MassErase(pEraseInit->Banks);
+ 1665              		.loc 1 282 5 is_stmt 1 view .LVU515
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     FLASH_MassErase(pEraseInit->Banks);
+ 1666              		.loc 1 282 29 is_stmt 0 view .LVU516
+ 1667 0094 044A     		ldr	r2, .L143
+ 1668 0096 0221     		movs	r1, #2
+ 1669 0098 1172     		strb	r1, [r2, #8]
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1670              		.loc 1 283 5 is_stmt 1 view .LVU517
+ 1671 009a 5868     		ldr	r0, [r3, #4]
+ 1672              	.LVL138:
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1673              		.loc 1 283 5 is_stmt 0 view .LVU518
+ 1674 009c FFF7FEFF 		bl	FLASH_MassErase
+ 1675              	.LVL139:
+ARM GAS  /tmp/ccudk1nZ.s 			page 62
+
+
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1676              		.loc 1 296 10 view .LVU519
+ 1677 00a0 0020     		movs	r0, #0
+ 1678 00a2 E0E7     		b	.L131
+ 1679              	.LVL140:
+ 1680              	.L137:
+ 1681              	.LCFI11:
+ 1682              		.cfi_def_cfa_offset 0
+ 1683              		.cfi_restore 3
+ 1684              		.cfi_restore 14
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1685              		.loc 1 242 3 view .LVU520
+ 1686 00a4 0220     		movs	r0, #2
+ 1687              	.LVL141:
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1688              		.loc 1 297 1 view .LVU521
+ 1689 00a6 7047     		bx	lr
+ 1690              	.L144:
+ 1691              		.align	2
+ 1692              	.L143:
+ 1693 00a8 00000000 		.word	pFlash
+ 1694 00ac 00200240 		.word	1073881088
+ 1695              		.cfi_endproc
+ 1696              	.LFE330:
+ 1698              		.section	.text.FLASH_FlushCaches,"ax",%progbits
+ 1699              		.align	1
+ 1700              		.global	FLASH_FlushCaches
+ 1701              		.syntax unified
+ 1702              		.thumb
+ 1703              		.thumb_func
+ 1705              	FLASH_FlushCaches:
+ 1706              	.LFB338:
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
+ 1707              		.loc 1 614 1 is_stmt 1 view -0
+ 1708              		.cfi_startproc
+ 1709              		@ args = 0, pretend = 0, frame = 0
+ 1710              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1711              		@ link register save eliminated.
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1712              		.loc 1 615 3 view .LVU523
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1713              		.loc 1 615 22 is_stmt 0 view .LVU524
+ 1714 0000 164B     		ldr	r3, .L150
+ 1715 0002 1B7F     		ldrb	r3, [r3, #28]	@ zero_extendqisi2
+ 1716 0004 DBB2     		uxtb	r3, r3
+ 1717              	.LVL142:
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+ 1718              		.loc 1 618 3 is_stmt 1 view .LVU525
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+ 1719              		.loc 1 618 6 is_stmt 0 view .LVU526
+ 1720 0006 012B     		cmp	r3, #1
+ 1721 0008 01D0     		beq	.L146
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+ 1722              		.loc 1 618 45 discriminator 1 view .LVU527
+ 1723 000a 032B     		cmp	r3, #3
+ 1724 000c 10D1     		bne	.L147
+ 1725              	.L146:
+ARM GAS  /tmp/ccudk1nZ.s 			page 63
+
+
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Reset instruction cache */
+ 1726              		.loc 1 622 5 is_stmt 1 view .LVU528
+ 1727 000e 144A     		ldr	r2, .L150+4
+ 1728 0010 1168     		ldr	r1, [r2]
+ 1729 0012 21F40071 		bic	r1, r1, #512
+ 1730 0016 1160     		str	r1, [r2]
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Enable instruction cache */
+ 1731              		.loc 1 624 5 view .LVU529
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Enable instruction cache */
+ 1732              		.loc 1 624 5 view .LVU530
+ 1733 0018 1168     		ldr	r1, [r2]
+ 1734 001a 41F40061 		orr	r1, r1, #2048
+ 1735 001e 1160     		str	r1, [r2]
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Enable instruction cache */
+ 1736              		.loc 1 624 5 view .LVU531
+ 1737 0020 1168     		ldr	r1, [r2]
+ 1738 0022 21F40061 		bic	r1, r1, #2048
+ 1739 0026 1160     		str	r1, [r2]
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Enable instruction cache */
+ 1740              		.loc 1 624 5 view .LVU532
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1741              		.loc 1 626 5 view .LVU533
+ 1742 0028 1168     		ldr	r1, [r2]
+ 1743 002a 41F40071 		orr	r1, r1, #512
+ 1744 002e 1160     		str	r1, [r2]
+ 1745              	.L147:
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+ 1746              		.loc 1 630 3 view .LVU534
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+ 1747              		.loc 1 630 45 is_stmt 0 view .LVU535
+ 1748 0030 023B     		subs	r3, r3, #2
+ 1749              	.LVL143:
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+ 1750              		.loc 1 630 45 view .LVU536
+ 1751 0032 DBB2     		uxtb	r3, r3
+ 1752              	.LVL144:
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
+ 1753              		.loc 1 630 6 view .LVU537
+ 1754 0034 012B     		cmp	r3, #1
+ 1755 0036 03D9     		bls	.L149
+ 1756              	.L148:
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1757              		.loc 1 640 3 is_stmt 1 view .LVU538
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1758              		.loc 1 640 28 is_stmt 0 view .LVU539
+ 1759 0038 084B     		ldr	r3, .L150
+ 1760 003a 0022     		movs	r2, #0
+ 1761 003c 1A77     		strb	r2, [r3, #28]
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1762              		.loc 1 641 1 view .LVU540
+ 1763 003e 7047     		bx	lr
+ 1764              	.L149:
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Enable data cache */
+ 1765              		.loc 1 634 5 is_stmt 1 view .LVU541
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Enable data cache */
+ 1766              		.loc 1 634 5 view .LVU542
+ 1767 0040 074B     		ldr	r3, .L150+4
+ARM GAS  /tmp/ccudk1nZ.s 			page 64
+
+
+ 1768 0042 1A68     		ldr	r2, [r3]
+ 1769 0044 42F48052 		orr	r2, r2, #4096
+ 1770 0048 1A60     		str	r2, [r3]
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Enable data cache */
+ 1771              		.loc 1 634 5 view .LVU543
+ 1772 004a 1A68     		ldr	r2, [r3]
+ 1773 004c 22F48052 		bic	r2, r2, #4096
+ 1774 0050 1A60     		str	r2, [r3]
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     /* Enable data cache */
+ 1775              		.loc 1 634 5 view .LVU544
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1776              		.loc 1 636 5 view .LVU545
+ 1777 0052 1A68     		ldr	r2, [r3]
+ 1778 0054 42F48062 		orr	r2, r2, #1024
+ 1779 0058 1A60     		str	r2, [r3]
+ 1780 005a EDE7     		b	.L148
+ 1781              	.L151:
+ 1782              		.align	2
+ 1783              	.L150:
+ 1784 005c 00000000 		.word	pFlash
+ 1785 0060 00200240 		.word	1073881088
+ 1786              		.cfi_endproc
+ 1787              	.LFE338:
+ 1789              		.section	.text.HAL_FLASHEx_Erase,"ax",%progbits
+ 1790              		.align	1
+ 1791              		.global	HAL_FLASHEx_Erase
+ 1792              		.syntax unified
+ 1793              		.thumb
+ 1794              		.thumb_func
+ 1796              	HAL_FLASHEx_Erase:
+ 1797              	.LVL145:
+ 1798              	.LFB329:
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 1799              		.loc 1 139 1 view -0
+ 1800              		.cfi_startproc
+ 1801              		@ args = 0, pretend = 0, frame = 0
+ 1802              		@ frame_needed = 0, uses_anonymous_args = 0
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   HAL_StatusTypeDef status;
+ 1803              		.loc 1 139 1 is_stmt 0 view .LVU547
+ 1804 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 1805              	.LCFI12:
+ 1806              		.cfi_def_cfa_offset 24
+ 1807              		.cfi_offset 3, -24
+ 1808              		.cfi_offset 4, -20
+ 1809              		.cfi_offset 5, -16
+ 1810              		.cfi_offset 6, -12
+ 1811              		.cfi_offset 7, -8
+ 1812              		.cfi_offset 14, -4
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   uint32_t page_index;
+ 1813              		.loc 1 140 3 is_stmt 1 view .LVU548
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1814              		.loc 1 141 3 view .LVU549
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1815              		.loc 1 144 3 view .LVU550
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1816              		.loc 1 147 3 view .LVU551
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ARM GAS  /tmp/ccudk1nZ.s 			page 65
+
+
+ 1817              		.loc 1 147 3 view .LVU552
+ 1818 0002 384B     		ldr	r3, .L168
+ 1819 0004 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 1820 0006 012B     		cmp	r3, #1
+ 1821 0008 69D0     		beq	.L164
+ 1822 000a 0446     		mov	r4, r0
+ 1823 000c 0E46     		mov	r6, r1
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1824              		.loc 1 147 3 discriminator 2 view .LVU553
+ 1825 000e 354B     		ldr	r3, .L168
+ 1826 0010 0122     		movs	r2, #1
+ 1827 0012 1A70     		strb	r2, [r3]
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1828              		.loc 1 147 3 discriminator 2 view .LVU554
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1829              		.loc 1 150 3 discriminator 2 view .LVU555
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1830              		.loc 1 150 12 is_stmt 0 discriminator 2 view .LVU556
+ 1831 0014 4FF47A70 		mov	r0, #1000
+ 1832              	.LVL146:
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1833              		.loc 1 150 12 discriminator 2 view .LVU557
+ 1834 0018 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1835              	.LVL147:
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1836              		.loc 1 152 3 is_stmt 1 discriminator 2 view .LVU558
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   {
+ 1837              		.loc 1 152 6 is_stmt 0 discriminator 2 view .LVU559
+ 1838 001c 0746     		mov	r7, r0
+ 1839 001e 0028     		cmp	r0, #0
+ 1840 0020 58D1     		bne	.L154
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1841              		.loc 1 154 5 is_stmt 1 view .LVU560
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1842              		.loc 1 154 22 is_stmt 0 view .LVU561
+ 1843 0022 304B     		ldr	r3, .L168
+ 1844 0024 0022     		movs	r2, #0
+ 1845 0026 5A60     		str	r2, [r3, #4]
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1846              		.loc 1 157 5 is_stmt 1 view .LVU562
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1847              		.loc 1 157 9 is_stmt 0 view .LVU563
+ 1848 0028 2F4B     		ldr	r3, .L168+4
+ 1849 002a 1B68     		ldr	r3, [r3]
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1850              		.loc 1 157 8 view .LVU564
+ 1851 002c 13F4007F 		tst	r3, #512
+ 1852 0030 2DD0     		beq	.L155
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1853              		.loc 1 159 7 is_stmt 1 view .LVU565
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1854              		.loc 1 159 11 is_stmt 0 view .LVU566
+ 1855 0032 2D4B     		ldr	r3, .L168+4
+ 1856 0034 1B68     		ldr	r3, [r3]
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1857              		.loc 1 159 10 view .LVU567
+ 1858 0036 13F4806F 		tst	r3, #1024
+ARM GAS  /tmp/ccudk1nZ.s 			page 66
+
+
+ 1859 003a 24D0     		beq	.L156
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
+ 1860              		.loc 1 162 9 is_stmt 1 view .LVU568
+ 1861 003c 2A4A     		ldr	r2, .L168+4
+ 1862 003e 1368     		ldr	r3, [r2]
+ 1863 0040 23F48063 		bic	r3, r3, #1024
+ 1864 0044 1360     		str	r3, [r2]
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+ 1865              		.loc 1 163 9 view .LVU569
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+ 1866              		.loc 1 163 34 is_stmt 0 view .LVU570
+ 1867 0046 274B     		ldr	r3, .L168
+ 1868 0048 0322     		movs	r2, #3
+ 1869 004a 1A77     		strb	r2, [r3, #28]
+ 1870              	.L157:
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1871              		.loc 1 181 5 is_stmt 1 view .LVU571
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1872              		.loc 1 181 19 is_stmt 0 view .LVU572
+ 1873 004c 2368     		ldr	r3, [r4]
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1874              		.loc 1 181 8 view .LVU573
+ 1875 004e 012B     		cmp	r3, #1
+ 1876 0050 2FD0     		beq	.L166
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1877              		.loc 1 200 7 is_stmt 1 view .LVU574
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1878              		.loc 1 200 18 is_stmt 0 view .LVU575
+ 1879 0052 4FF0FF33 		mov	r3, #-1
+ 1880 0056 3360     		str	r3, [r6]
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1881              		.loc 1 202 7 is_stmt 1 view .LVU576
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1882              		.loc 1 202 23 is_stmt 0 view .LVU577
+ 1883 0058 A568     		ldr	r5, [r4, #8]
+ 1884              	.LVL148:
+ 1885              	.L161:
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1886              		.loc 1 202 54 is_stmt 1 discriminator 1 view .LVU578
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1887              		.loc 1 202 67 is_stmt 0 discriminator 1 view .LVU579
+ 1888 005a A368     		ldr	r3, [r4, #8]
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1889              		.loc 1 202 86 discriminator 1 view .LVU580
+ 1890 005c E268     		ldr	r2, [r4, #12]
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1891              		.loc 1 202 74 discriminator 1 view .LVU581
+ 1892 005e 1344     		add	r3, r3, r2
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1893              		.loc 1 202 54 discriminator 1 view .LVU582
+ 1894 0060 AB42     		cmp	r3, r5
+ 1895 0062 35D9     		bls	.L160
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1896              		.loc 1 204 9 is_stmt 1 view .LVU583
+ 1897 0064 6168     		ldr	r1, [r4, #4]
+ 1898 0066 2846     		mov	r0, r5
+ 1899 0068 FFF7FEFF 		bl	FLASH_PageErase
+ARM GAS  /tmp/ccudk1nZ.s 			page 67
+
+
+ 1900              	.LVL149:
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1901              		.loc 1 207 9 view .LVU584
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1902              		.loc 1 207 18 is_stmt 0 view .LVU585
+ 1903 006c 4FF47A70 		mov	r0, #1000
+ 1904 0070 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1905              	.LVL150:
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1906              		.loc 1 210 9 is_stmt 1 view .LVU586
+ 1907 0074 1C4A     		ldr	r2, .L168+4
+ 1908 0076 5369     		ldr	r3, [r2, #20]
+ 1909 0078 23F4FD73 		bic	r3, r3, #506
+ 1910 007c 5361     		str	r3, [r2, #20]
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         {
+ 1911              		.loc 1 212 9 view .LVU587
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         {
+ 1912              		.loc 1 212 12 is_stmt 0 view .LVU588
+ 1913 007e 0746     		mov	r7, r0
+ 1914 0080 28BB     		cbnz	r0, .L167
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1915              		.loc 1 202 108 is_stmt 1 discriminator 2 view .LVU589
+ 1916 0082 0135     		adds	r5, r5, #1
+ 1917              	.LVL151:
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       {
+ 1918              		.loc 1 202 108 is_stmt 0 discriminator 2 view .LVU590
+ 1919 0084 E9E7     		b	.L161
+ 1920              	.LVL152:
+ 1921              	.L156:
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+ 1922              		.loc 1 167 9 is_stmt 1 view .LVU591
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       }
+ 1923              		.loc 1 167 34 is_stmt 0 view .LVU592
+ 1924 0086 174B     		ldr	r3, .L168
+ 1925 0088 0122     		movs	r2, #1
+ 1926 008a 1A77     		strb	r2, [r3, #28]
+ 1927 008c DEE7     		b	.L157
+ 1928              	.L155:
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1929              		.loc 1 170 10 is_stmt 1 view .LVU593
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1930              		.loc 1 170 14 is_stmt 0 view .LVU594
+ 1931 008e 164B     		ldr	r3, .L168+4
+ 1932 0090 1B68     		ldr	r3, [r3]
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     {
+ 1933              		.loc 1 170 13 view .LVU595
+ 1934 0092 13F4806F 		tst	r3, #1024
+ 1935 0096 08D0     		beq	.L158
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****       pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
+ 1936              		.loc 1 173 7 is_stmt 1 view .LVU596
+ 1937 0098 134A     		ldr	r2, .L168+4
+ 1938 009a 1368     		ldr	r3, [r2]
+ 1939 009c 23F48063 		bic	r3, r3, #1024
+ 1940 00a0 1360     		str	r3, [r2]
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1941              		.loc 1 174 7 view .LVU597
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ARM GAS  /tmp/ccudk1nZ.s 			page 68
+
+
+ 1942              		.loc 1 174 32 is_stmt 0 view .LVU598
+ 1943 00a2 104B     		ldr	r3, .L168
+ 1944 00a4 0222     		movs	r2, #2
+ 1945 00a6 1A77     		strb	r2, [r3, #28]
+ 1946 00a8 D0E7     		b	.L157
+ 1947              	.L158:
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1948              		.loc 1 178 7 is_stmt 1 view .LVU599
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****     }
+ 1949              		.loc 1 178 32 is_stmt 0 view .LVU600
+ 1950 00aa 0E4B     		ldr	r3, .L168
+ 1951 00ac 0022     		movs	r2, #0
+ 1952 00ae 1A77     		strb	r2, [r3, #28]
+ 1953 00b0 CCE7     		b	.L157
+ 1954              	.L166:
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1955              		.loc 1 184 7 is_stmt 1 view .LVU601
+ 1956 00b2 6068     		ldr	r0, [r4, #4]
+ 1957              	.LVL153:
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1958              		.loc 1 184 7 is_stmt 0 view .LVU602
+ 1959 00b4 FFF7FEFF 		bl	FLASH_MassErase
+ 1960              	.LVL154:
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1961              		.loc 1 187 7 is_stmt 1 view .LVU603
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1962              		.loc 1 187 16 is_stmt 0 view .LVU604
+ 1963 00b8 4FF47A70 		mov	r0, #1000
+ 1964 00bc FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1965              	.LVL155:
+ 1966 00c0 0746     		mov	r7, r0
+ 1967              	.LVL156:
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** #endif
+ 1968              		.loc 1 194 7 is_stmt 1 view .LVU605
+ 1969 00c2 094A     		ldr	r2, .L168+4
+ 1970 00c4 5369     		ldr	r3, [r2, #20]
+ 1971 00c6 23F00403 		bic	r3, r3, #4
+ 1972 00ca 5361     		str	r3, [r2, #20]
+ 1973 00cc 00E0     		b	.L160
+ 1974              	.LVL157:
+ 1975              	.L167:
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****           break;
+ 1976              		.loc 1 215 11 view .LVU606
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****           break;
+ 1977              		.loc 1 215 22 is_stmt 0 view .LVU607
+ 1978 00ce 3560     		str	r5, [r6]
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****         }
+ 1979              		.loc 1 216 11 is_stmt 1 view .LVU608
+ 1980              	.LVL158:
+ 1981              	.L160:
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ****   }
+ 1982              		.loc 1 222 5 view .LVU609
+ 1983 00d0 FFF7FEFF 		bl	FLASH_FlushCaches
+ 1984              	.LVL159:
+ 1985              	.L154:
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1986              		.loc 1 226 3 view .LVU610
+ARM GAS  /tmp/ccudk1nZ.s 			page 69
+
+
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1987              		.loc 1 226 3 view .LVU611
+ 1988 00d4 034B     		ldr	r3, .L168
+ 1989 00d6 0022     		movs	r2, #0
+ 1990 00d8 1A70     		strb	r2, [r3]
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1991              		.loc 1 226 3 view .LVU612
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** }
+ 1992              		.loc 1 228 3 view .LVU613
+ 1993              	.LVL160:
+ 1994              	.L153:
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 1995              		.loc 1 229 1 is_stmt 0 view .LVU614
+ 1996 00da 3846     		mov	r0, r7
+ 1997 00dc F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 1998              	.LVL161:
+ 1999              	.L164:
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c **** 
+ 2000              		.loc 1 147 3 view .LVU615
+ 2001 00de 0227     		movs	r7, #2
+ 2002 00e0 FBE7     		b	.L153
+ 2003              	.L169:
+ 2004 00e2 00BF     		.align	2
+ 2005              	.L168:
+ 2006 00e4 00000000 		.word	pFlash
+ 2007 00e8 00200240 		.word	1073881088
+ 2008              		.cfi_endproc
+ 2009              	.LFE329:
+ 2011              		.text
+ 2012              	.Letext0:
+ 2013              		.file 2 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 2014              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 2015              		.file 4 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 2016              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"
+ARM GAS  /tmp/ccudk1nZ.s 			page 70
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_flash_ex.c
+     /tmp/ccudk1nZ.s:21     .text.FLASH_MassErase:00000000 $t
+     /tmp/ccudk1nZ.s:26     .text.FLASH_MassErase:00000000 FLASH_MassErase
+     /tmp/ccudk1nZ.s:55     .text.FLASH_MassErase:0000001c $d
+     /tmp/ccudk1nZ.s:60     .text.FLASH_OB_GetSecMem:00000000 $t
+     /tmp/ccudk1nZ.s:65     .text.FLASH_OB_GetSecMem:00000000 FLASH_OB_GetSecMem
+     /tmp/ccudk1nZ.s:93     .text.FLASH_OB_GetSecMem:00000014 $d
+     /tmp/ccudk1nZ.s:98     .text.FLASH_OB_GetBootLock:00000000 $t
+     /tmp/ccudk1nZ.s:103    .text.FLASH_OB_GetBootLock:00000000 FLASH_OB_GetBootLock
+     /tmp/ccudk1nZ.s:120    .text.FLASH_OB_GetBootLock:0000000c $d
+     /tmp/ccudk1nZ.s:125    .text.FLASH_OB_GetWRP:00000000 $t
+     /tmp/ccudk1nZ.s:130    .text.FLASH_OB_GetWRP:00000000 FLASH_OB_GetWRP
+     /tmp/ccudk1nZ.s:192    .text.FLASH_OB_GetWRP:00000030 $d
+     /tmp/ccudk1nZ.s:197    .text.FLASH_OB_GetRDP:00000000 $t
+     /tmp/ccudk1nZ.s:202    .text.FLASH_OB_GetRDP:00000000 FLASH_OB_GetRDP
+     /tmp/ccudk1nZ.s:232    .text.FLASH_OB_GetRDP:00000014 $d
+     /tmp/ccudk1nZ.s:237    .text.FLASH_OB_GetUser:00000000 $t
+     /tmp/ccudk1nZ.s:242    .text.FLASH_OB_GetUser:00000000 FLASH_OB_GetUser
+     /tmp/ccudk1nZ.s:264    .text.FLASH_OB_GetUser:0000000c $d
+     /tmp/ccudk1nZ.s:269    .text.FLASH_OB_GetPCROP:00000000 $t
+     /tmp/ccudk1nZ.s:274    .text.FLASH_OB_GetPCROP:00000000 FLASH_OB_GetPCROP
+     /tmp/ccudk1nZ.s:348    .text.FLASH_OB_GetPCROP:00000038 $d
+     /tmp/ccudk1nZ.s:354    .text.FLASH_OB_WRPConfig:00000000 $t
+     /tmp/ccudk1nZ.s:359    .text.FLASH_OB_WRPConfig:00000000 FLASH_OB_WRPConfig
+     /tmp/ccudk1nZ.s:434    .text.FLASH_OB_WRPConfig:00000040 $d
+     /tmp/ccudk1nZ.s:439    .text.FLASH_OB_RDPConfig:00000000 $t
+     /tmp/ccudk1nZ.s:444    .text.FLASH_OB_RDPConfig:00000000 FLASH_OB_RDPConfig
+     /tmp/ccudk1nZ.s:497    .text.FLASH_OB_RDPConfig:00000030 $d
+     /tmp/ccudk1nZ.s:502    .text.FLASH_OB_UserConfig:00000000 $t
+     /tmp/ccudk1nZ.s:507    .text.FLASH_OB_UserConfig:00000000 FLASH_OB_UserConfig
+     /tmp/ccudk1nZ.s:812    .text.FLASH_OB_UserConfig:00000124 $d
+     /tmp/ccudk1nZ.s:817    .text.FLASH_OB_PCROPConfig:00000000 $t
+     /tmp/ccudk1nZ.s:822    .text.FLASH_OB_PCROPConfig:00000000 FLASH_OB_PCROPConfig
+     /tmp/ccudk1nZ.s:914    .text.FLASH_OB_PCROPConfig:00000064 $d
+     /tmp/ccudk1nZ.s:919    .text.FLASH_OB_SecMemConfig:00000000 $t
+     /tmp/ccudk1nZ.s:924    .text.FLASH_OB_SecMemConfig:00000000 FLASH_OB_SecMemConfig
+     /tmp/ccudk1nZ.s:985    .text.FLASH_OB_SecMemConfig:00000038 $d
+     /tmp/ccudk1nZ.s:990    .text.FLASH_OB_BootLockConfig:00000000 $t
+     /tmp/ccudk1nZ.s:995    .text.FLASH_OB_BootLockConfig:00000000 FLASH_OB_BootLockConfig
+     /tmp/ccudk1nZ.s:1048   .text.FLASH_OB_BootLockConfig:00000030 $d
+     /tmp/ccudk1nZ.s:1053   .text.HAL_FLASHEx_OBProgram:00000000 $t
+     /tmp/ccudk1nZ.s:1059   .text.HAL_FLASHEx_OBProgram:00000000 HAL_FLASHEx_OBProgram
+     /tmp/ccudk1nZ.s:1266   .text.HAL_FLASHEx_OBProgram:000000bc $d
+     /tmp/ccudk1nZ.s:1271   .text.HAL_FLASHEx_OBGetConfig:00000000 $t
+     /tmp/ccudk1nZ.s:1277   .text.HAL_FLASHEx_OBGetConfig:00000000 HAL_FLASHEx_OBGetConfig
+     /tmp/ccudk1nZ.s:1386   .text.HAL_FLASHEx_EnableSecMemProtection:00000000 $t
+     /tmp/ccudk1nZ.s:1392   .text.HAL_FLASHEx_EnableSecMemProtection:00000000 HAL_FLASHEx_EnableSecMemProtection
+     /tmp/ccudk1nZ.s:1414   .text.HAL_FLASHEx_EnableSecMemProtection:00000010 $d
+     /tmp/ccudk1nZ.s:1419   .text.HAL_FLASHEx_EnableDebugger:00000000 $t
+     /tmp/ccudk1nZ.s:1425   .text.HAL_FLASHEx_EnableDebugger:00000000 HAL_FLASHEx_EnableDebugger
+     /tmp/ccudk1nZ.s:1444   .text.HAL_FLASHEx_EnableDebugger:0000000c $d
+     /tmp/ccudk1nZ.s:1449   .text.HAL_FLASHEx_DisableDebugger:00000000 $t
+     /tmp/ccudk1nZ.s:1455   .text.HAL_FLASHEx_DisableDebugger:00000000 HAL_FLASHEx_DisableDebugger
+     /tmp/ccudk1nZ.s:1474   .text.HAL_FLASHEx_DisableDebugger:0000000c $d
+     /tmp/ccudk1nZ.s:1479   .text.FLASH_PageErase:00000000 $t
+     /tmp/ccudk1nZ.s:1485   .text.FLASH_PageErase:00000000 FLASH_PageErase
+ARM GAS  /tmp/ccudk1nZ.s 			page 71
+
+
+     /tmp/ccudk1nZ.s:1517   .text.FLASH_PageErase:00000024 $d
+     /tmp/ccudk1nZ.s:1522   .text.HAL_FLASHEx_Erase_IT:00000000 $t
+     /tmp/ccudk1nZ.s:1528   .text.HAL_FLASHEx_Erase_IT:00000000 HAL_FLASHEx_Erase_IT
+     /tmp/ccudk1nZ.s:1693   .text.HAL_FLASHEx_Erase_IT:000000a8 $d
+     /tmp/ccudk1nZ.s:1699   .text.FLASH_FlushCaches:00000000 $t
+     /tmp/ccudk1nZ.s:1705   .text.FLASH_FlushCaches:00000000 FLASH_FlushCaches
+     /tmp/ccudk1nZ.s:1784   .text.FLASH_FlushCaches:0000005c $d
+     /tmp/ccudk1nZ.s:1790   .text.HAL_FLASHEx_Erase:00000000 $t
+     /tmp/ccudk1nZ.s:1796   .text.HAL_FLASHEx_Erase:00000000 HAL_FLASHEx_Erase
+     /tmp/ccudk1nZ.s:2006   .text.HAL_FLASHEx_Erase:000000e4 $d
+
+UNDEFINED SYMBOLS
+FLASH_WaitForLastOperation
+pFlash
diff --git a/squeow_sw/build/stm32g4xx_hal_flash_ex.o b/squeow_sw/build/stm32g4xx_hal_flash_ex.o
new file mode 100644
index 0000000000000000000000000000000000000000..517619e75836f2b9f106aaffa2f68d8d011f9023
GIT binary patch
literal 25116
zcmdUXdwf*Yx%S$7&z?-K6PSc+fC&i_h1>uI6d`vYAtWS#h}vXwfeD5rCKE)D)zn%q
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diff --git a/squeow_sw/build/stm32g4xx_hal_flash_ramfunc.d b/squeow_sw/build/stm32g4xx_hal_flash_ramfunc.d
new file mode 100644
index 0000000..9569685
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_flash_ramfunc.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_flash_ramfunc.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_flash_ramfunc.lst b/squeow_sw/build/stm32g4xx_hal_flash_ramfunc.lst
new file mode 100644
index 0000000..19c2e58
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_flash_ramfunc.lst
@@ -0,0 +1,236 @@
+ARM GAS  /tmp/cc8dOzXH.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_flash_ramfunc.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c"
+  20              		.section	.RamFunc,"ax",%progbits
+  21              		.align	1
+  22              		.global	HAL_FLASHEx_EnableRunPowerDown
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	HAL_FLASHEx_EnableRunPowerDown:
+  28              	.LFB329:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @file    stm32g4xx_hal_flash_ramfunc.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @brief   FLASH RAMFUNC driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   *          This file provides a Flash firmware functions which should be
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   *          executed from internal SRAM
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   *            + FLASH Power Down in Run mode
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   *            + FLASH DBANK User Option Byte
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   *
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   *
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   @verbatim
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   ==============================================================================
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****                    ##### Flash RAM functions #####
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   ==============================================================================
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****     *** ARM Compiler ***
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****     --------------------
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****     [..] RAM functions are defined using the toolchain options.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****          Functions that are executed in RAM should reside in a separate
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****          source module. Using the 'Options for File' dialog you can simply change
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****          the 'Code / Const' area of a module to a memory space in physical RAM.
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****          Available memory areas are declared in the 'Target' tab of the
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****          Options for Target' dialog.
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****     *** ICCARM Compiler ***
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****     -----------------------
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****     [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****     *** GNU Compiler ***
+ARM GAS  /tmp/cc8dOzXH.s 			page 2
+
+
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****     --------------------
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****     [..] RAM functions are defined using a specific toolchain attribute
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****          "__attribute__((section(".RamFunc")))".
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   @endverbatim
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   ******************************************************************************
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @attention
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   *
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * Copyright (c) 2019 STMicroelectronics.
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * All rights reserved.
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   *
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * the root directory of this software component.
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   ******************************************************************************
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   */
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /* Includes ------------------------------------------------------------------*/
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** #include "stm32g4xx_hal.h"
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @{
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   */
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @brief FLASH functions executed from RAM
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @{
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   */
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** #ifdef HAL_FLASH_MODULE_ENABLED
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /* Private typedef -----------------------------------------------------------*/
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /* Private define ------------------------------------------------------------*/
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /* Private macro -------------------------------------------------------------*/
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /* Private variables ---------------------------------------------------------*/
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /* Private function prototypes -----------------------------------------------*/
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /* Exported functions -------------------------------------------------------*/
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH_RAMFUNC Exported Functions
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @{
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   */
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****  *  @brief   Data transfers functions
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****  *
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** @verbatim
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****  ===============================================================================
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****                       ##### ramfunc functions #####
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****  ===============================================================================
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****     [..]
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****     This subsection provides a set of functions that should be executed from RAM.
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** @endverbatim
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @{
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   */
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /**
+ARM GAS  /tmp/cc8dOzXH.s 			page 3
+
+
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @brief  Enable the Power down in Run Mode
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @note   This function should be called and executed from SRAM memory.
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @retval None
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   */
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** {
+  29              		.loc 1 93 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   /* Enable the Power Down in Run mode*/
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   __HAL_FLASH_POWER_DOWN_ENABLE();
+  34              		.loc 1 95 3 view .LVU1
+  35              		.loc 1 95 3 view .LVU2
+  36 0000 054B     		ldr	r3, .L2
+  37 0002 064A     		ldr	r2, .L2+4
+  38 0004 5A60     		str	r2, [r3, #4]
+  39              		.loc 1 95 3 view .LVU3
+  40 0006 064A     		ldr	r2, .L2+8
+  41 0008 5A60     		str	r2, [r3, #4]
+  42              		.loc 1 95 3 view .LVU4
+  43 000a 1A68     		ldr	r2, [r3]
+  44 000c 42F40052 		orr	r2, r2, #8192
+  45 0010 1A60     		str	r2, [r3]
+  46              		.loc 1 95 3 view .LVU5
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   return HAL_OK;
+  47              		.loc 1 97 3 view .LVU6
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** }
+  48              		.loc 1 99 1 is_stmt 0 view .LVU7
+  49 0012 0020     		movs	r0, #0
+  50 0014 7047     		bx	lr
+  51              	.L3:
+  52 0016 00BF     		.align	2
+  53              	.L2:
+  54 0018 00200240 		.word	1073881088
+  55 001c 37261504 		.word	68494903
+  56 0020 FDFCFBFA 		.word	-84148995
+  57              		.cfi_endproc
+  58              	.LFE329:
+  60              		.align	1
+  61              		.global	HAL_FLASHEx_DisableRunPowerDown
+  62              		.syntax unified
+  63              		.thumb
+  64              		.thumb_func
+  66              	HAL_FLASHEx_DisableRunPowerDown:
+  67              	.LFB330:
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** /**
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @brief  Disable the Power down in Run Mode
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @note   This function should be called and executed from SRAM memory.
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   * @retval None
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   */
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** {
+ARM GAS  /tmp/cc8dOzXH.s 			page 4
+
+
+  68              		.loc 1 107 1 is_stmt 1 view -0
+  69              		.cfi_startproc
+  70              		@ args = 0, pretend = 0, frame = 0
+  71              		@ frame_needed = 0, uses_anonymous_args = 0
+  72              		@ link register save eliminated.
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   /* Disable the Power Down in Run mode*/
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   __HAL_FLASH_POWER_DOWN_DISABLE();
+  73              		.loc 1 109 3 view .LVU9
+  74              		.loc 1 109 3 view .LVU10
+  75 0024 054B     		ldr	r3, .L5
+  76 0026 064A     		ldr	r2, .L5+4
+  77 0028 5A60     		str	r2, [r3, #4]
+  78              		.loc 1 109 3 view .LVU11
+  79 002a 064A     		ldr	r2, .L5+8
+  80 002c 5A60     		str	r2, [r3, #4]
+  81              		.loc 1 109 3 view .LVU12
+  82 002e 1A68     		ldr	r2, [r3]
+  83 0030 22F40052 		bic	r2, r2, #8192
+  84 0034 1A60     		str	r2, [r3]
+  85              		.loc 1 109 3 view .LVU13
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** 
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ****   return HAL_OK;
+  86              		.loc 1 111 3 view .LVU14
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c **** }
+  87              		.loc 1 112 1 is_stmt 0 view .LVU15
+  88 0036 0020     		movs	r0, #0
+  89 0038 7047     		bx	lr
+  90              	.L6:
+  91 003a 00BF     		.align	2
+  92              	.L5:
+  93 003c 00200240 		.word	1073881088
+  94 0040 37261504 		.word	68494903
+  95 0044 FDFCFBFA 		.word	-84148995
+  96              		.cfi_endproc
+  97              	.LFE330:
+  99              		.text
+ 100              	.Letext0:
+ 101              		.file 2 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 102              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 103              		.file 4 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ARM GAS  /tmp/cc8dOzXH.s 			page 5
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_flash_ramfunc.c
+     /tmp/cc8dOzXH.s:21     .RamFunc:00000000 $t
+     /tmp/cc8dOzXH.s:27     .RamFunc:00000000 HAL_FLASHEx_EnableRunPowerDown
+     /tmp/cc8dOzXH.s:54     .RamFunc:00000018 $d
+     /tmp/cc8dOzXH.s:60     .RamFunc:00000024 $t
+     /tmp/cc8dOzXH.s:66     .RamFunc:00000024 HAL_FLASHEx_DisableRunPowerDown
+     /tmp/cc8dOzXH.s:93     .RamFunc:0000003c $d
+
+NO UNDEFINED SYMBOLS
diff --git a/squeow_sw/build/stm32g4xx_hal_flash_ramfunc.o b/squeow_sw/build/stm32g4xx_hal_flash_ramfunc.o
new file mode 100644
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diff --git a/squeow_sw/build/stm32g4xx_hal_gpio.d b/squeow_sw/build/stm32g4xx_hal_gpio.d
new file mode 100644
index 0000000..2568a10
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_gpio.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_gpio.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_gpio.lst b/squeow_sw/build/stm32g4xx_hal_gpio.lst
new file mode 100644
index 0000000..b40056d
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_gpio.lst
@@ -0,0 +1,1691 @@
+ARM GAS  /tmp/ccY6DPpN.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_gpio.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c"
+  20              		.section	.text.HAL_GPIO_Init,"ax",%progbits
+  21              		.align	1
+  22              		.global	HAL_GPIO_Init
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	HAL_GPIO_Init:
+  28              	.LVL0:
+  29              	.LFB329:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @file    stm32g4xx_hal_gpio.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @brief   GPIO HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *           + IO operation functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   ******************************************************************************
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @attention
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * Copyright (c) 2019 STMicroelectronics.
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * All rights reserved.
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * in the root directory of this software component.
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   ******************************************************************************
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   @verbatim
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   ==============================================================================
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****                     ##### GPIO Peripheral features #####
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   ==============================================================================
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   [..]
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         configured by software in several modes:
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (++) Input mode
+ARM GAS  /tmp/ccY6DPpN.s 			page 2
+
+
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (++) Analog mode
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (++) Output mode
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (++) Alternate function mode
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (++) External interrupt/event lines
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (+) During and just after reset, the alternate functions and external interrupt
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         lines are not active and the I/O ports are configured in input floating mode.
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         activated or not.
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         type and the IO speed can be selected depending on the VDD value.
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         multiplexer that allows only one peripheral alternate function (AF) connected
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****        to an IO pin at a time. In this way, there can be no conflict between peripherals
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****        sharing the same IO pin.
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (+) All ports have external interrupt/event capability. To use external interrupt
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         lines, the port must be configured in input mode. All available GPIO pins are
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (+) The external interrupt/event controller consists of up to 44 edge detectors
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (16 lines are connected to GPIO) for generating event/interrupt requests (each
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         input line can be independently configured to select the type (interrupt or event)
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         and the corresponding trigger event (rising or falling or both). Each line can
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         also be masked independently.
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****                      ##### How to use this driver #####
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   ==============================================================================
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   [..]
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****              structure.
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (++) In case of Output or alternate function mode selection: the speed is
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****              configured through "Speed" member from GPIO_InitTypeDef structure.
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (++) In alternate mode is selection, the alternate function connected to the IO
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****              is configured through "Alternate" member from GPIO_InitTypeDef structure.
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (++) Analog mode is required when a pin is to be used as ADC channel
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****              or DAC output.
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (++) In case of external interrupt/event selection the "Mode" member from
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****              GPIO_InitTypeDef structure select the type (interrupt or event) and
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****              the corresponding trigger event (rising or falling or both).
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         HAL_NVIC_EnableIRQ().
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (#) To set/reset the level of a pin configured in output mode use
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ARM GAS  /tmp/ccY6DPpN.s 			page 3
+
+
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (#) During and just after reset, the alternate functions are not
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         active and the GPIO pins are configured in input floating mode (except JTAG
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         pins).
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         priority over the GPIO function.
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         The HSE has priority over the GPIO function.
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   @endverbatim
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   ******************************************************************************
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /* Includes ------------------------------------------------------------------*/
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** #include "stm32g4xx_hal.h"
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /** @addtogroup STM32G4xx_HAL_Driver
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @{
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /** @addtogroup GPIO
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @{
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /** MISRA C:2012 deviation rule has been granted for following rules:
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * range of the shift operator in following API :
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * HAL_GPIO_Init
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * HAL_GPIO_DeInit
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** #ifdef HAL_GPIO_MODULE_ENABLED
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /* Private typedef -----------------------------------------------------------*/
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /* Private defines -----------------------------------------------------------*/
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /** @addtogroup GPIO_Private_Constants GPIO Private Constants
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @{
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** #define GPIO_NUMBER           (16U)
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /**
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @}
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /* Private macros ------------------------------------------------------------*/
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /* Private variables ---------------------------------------------------------*/
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /* Private function prototypes -----------------------------------------------*/
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /* Exported functions --------------------------------------------------------*/
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /** @addtogroup GPIO_Exported_Functions
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @{
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+ARM GAS  /tmp/ccY6DPpN.s 			page 4
+
+
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *  @brief    Initialization and Configuration functions
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** @verbatim
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****  ===============================================================================
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****               ##### Initialization and de-initialization functions #####
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****  ===============================================================================
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** @endverbatim
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @{
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /**
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *         the configuration information for the specified GPIO peripheral.
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @retval None
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** {
+  30              		.loc 1 163 1 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 8
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		.loc 1 163 1 is_stmt 0 view .LVU1
+  35 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+  36              	.LCFI0:
+  37              		.cfi_def_cfa_offset 20
+  38              		.cfi_offset 4, -20
+  39              		.cfi_offset 5, -16
+  40              		.cfi_offset 6, -12
+  41              		.cfi_offset 7, -8
+  42              		.cfi_offset 14, -4
+  43 0002 83B0     		sub	sp, sp, #12
+  44              	.LCFI1:
+  45              		.cfi_def_cfa_offset 32
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   uint32_t position = 0x00U;
+  46              		.loc 1 164 3 is_stmt 1 view .LVU2
+  47              	.LVL1:
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   uint32_t iocurrent;
+  48              		.loc 1 165 3 view .LVU3
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   uint32_t temp;
+  49              		.loc 1 166 3 view .LVU4
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Check the parameters */
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  50              		.loc 1 169 3 view .LVU5
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  51              		.loc 1 170 3 view .LVU6
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+  52              		.loc 1 171 3 view .LVU7
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Configure the port pins */
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   while (((GPIO_Init->Pin) >> position) != 0U)
+  53              		.loc 1 174 3 view .LVU8
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   uint32_t iocurrent;
+  54              		.loc 1 164 12 is_stmt 0 view .LVU9
+ARM GAS  /tmp/ccY6DPpN.s 			page 5
+
+
+  55 0004 0023     		movs	r3, #0
+  56              		.loc 1 174 9 view .LVU10
+  57 0006 62E0     		b	.L2
+  58              	.LVL2:
+  59              	.L21:
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     /* Get current io position */
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     iocurrent = (GPIO_Init->Pin) & (1UL << position);
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     if (iocurrent != 0x00u)
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     {
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /*--------------------- GPIO Mode Configuration ------------------------*/
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /* In case of Output or Alternate function mode selection */
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****          ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         /* Check the Speed parameter */
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+  60              		.loc 1 187 9 is_stmt 1 view .LVU11
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         /* Configure the IO Speed */
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp = GPIOx->OSPEEDR;
+  61              		.loc 1 189 9 view .LVU12
+  62              		.loc 1 189 14 is_stmt 0 view .LVU13
+  63 0008 8568     		ldr	r5, [r0, #8]
+  64              	.LVL3:
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+  65              		.loc 1 190 9 is_stmt 1 view .LVU14
+  66              		.loc 1 190 53 is_stmt 0 view .LVU15
+  67 000a 5E00     		lsls	r6, r3, #1
+  68              		.loc 1 190 40 view .LVU16
+  69 000c 0324     		movs	r4, #3
+  70 000e B440     		lsls	r4, r4, r6
+  71              		.loc 1 190 14 view .LVU17
+  72 0010 25EA0405 		bic	r5, r5, r4
+  73              	.LVL4:
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= (GPIO_Init->Speed << (position * 2U));
+  74              		.loc 1 191 9 is_stmt 1 view .LVU18
+  75              		.loc 1 191 27 is_stmt 0 view .LVU19
+  76 0014 CC68     		ldr	r4, [r1, #12]
+  77              		.loc 1 191 35 view .LVU20
+  78 0016 B440     		lsls	r4, r4, r6
+  79              		.loc 1 191 14 view .LVU21
+  80 0018 2C43     		orrs	r4, r4, r5
+  81              	.LVL5:
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         GPIOx->OSPEEDR = temp;
+  82              		.loc 1 192 9 is_stmt 1 view .LVU22
+  83              		.loc 1 192 24 is_stmt 0 view .LVU23
+  84 001a 8460     		str	r4, [r0, #8]
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         /* Configure the IO Output Type */
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp = GPIOx->OTYPER;
+  85              		.loc 1 195 9 is_stmt 1 view .LVU24
+  86              		.loc 1 195 14 is_stmt 0 view .LVU25
+  87 001c 4568     		ldr	r5, [r0, #4]
+  88              	.LVL6:
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(GPIO_OTYPER_OT0 << position) ;
+  89              		.loc 1 196 9 is_stmt 1 view .LVU26
+ARM GAS  /tmp/ccY6DPpN.s 			page 6
+
+
+  90              		.loc 1 196 14 is_stmt 0 view .LVU27
+  91 001e 25EA0C05 		bic	r5, r5, ip
+  92              	.LVL7:
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+  93              		.loc 1 197 9 is_stmt 1 view .LVU28
+  94              		.loc 1 197 29 is_stmt 0 view .LVU29
+  95 0022 4C68     		ldr	r4, [r1, #4]
+  96              		.loc 1 197 51 view .LVU30
+  97 0024 C4F30014 		ubfx	r4, r4, #4, #1
+  98              		.loc 1 197 71 view .LVU31
+  99 0028 9C40     		lsls	r4, r4, r3
+ 100              		.loc 1 197 14 view .LVU32
+ 101 002a 2C43     		orrs	r4, r4, r5
+ 102              	.LVL8:
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         GPIOx->OTYPER = temp;
+ 103              		.loc 1 198 9 is_stmt 1 view .LVU33
+ 104              		.loc 1 198 23 is_stmt 0 view .LVU34
+ 105 002c 4460     		str	r4, [r0, #4]
+ 106 002e 5FE0     		b	.L4
+ 107              	.LVL9:
+ 108              	.L22:
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       }
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         /* Check the Pull parameter */
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         /* Activate the Pull-up or Pull down resistor for the current IO */
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp = GPIOx->PUPDR;
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         GPIOx->PUPDR = temp;
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       }
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /* In case of Alternate function mode selection */
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         /* Check the Alternate function parameters */
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ 109              		.loc 1 217 9 is_stmt 1 view .LVU35
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+ 110              		.loc 1 218 9 view .LVU36
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         /* Configure Alternate function mapped with the current IO */
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp = GPIOx->AFR[position >> 3U];
+ 111              		.loc 1 221 9 view .LVU37
+ 112              		.loc 1 221 36 is_stmt 0 view .LVU38
+ 113 0030 DD08     		lsrs	r5, r3, #3
+ 114              		.loc 1 221 14 view .LVU39
+ 115 0032 0835     		adds	r5, r5, #8
+ 116 0034 50F82540 		ldr	r4, [r0, r5, lsl #2]
+ 117              	.LVL10:
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(0xFU << ((position & 0x07U) * 4U));
+ 118              		.loc 1 222 9 is_stmt 1 view .LVU40
+ 119              		.loc 1 222 38 is_stmt 0 view .LVU41
+ 120 0038 03F0070C 		and	ip, r3, #7
+ARM GAS  /tmp/ccY6DPpN.s 			page 7
+
+
+ 121              		.loc 1 222 47 view .LVU42
+ 122 003c 4FEA8C0C 		lsl	ip, ip, #2
+ 123              		.loc 1 222 24 view .LVU43
+ 124 0040 4FF00F0E 		mov	lr, #15
+ 125 0044 0EFA0CFE 		lsl	lr, lr, ip
+ 126              		.loc 1 222 14 view .LVU44
+ 127 0048 24EA0E0E 		bic	lr, r4, lr
+ 128              	.LVL11:
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
+ 129              		.loc 1 223 9 is_stmt 1 view .LVU45
+ 130              		.loc 1 223 28 is_stmt 0 view .LVU46
+ 131 004c 0C69     		ldr	r4, [r1, #16]
+ 132              		.loc 1 223 41 view .LVU47
+ 133 004e 04FA0CF4 		lsl	r4, r4, ip
+ 134              		.loc 1 223 14 view .LVU48
+ 135 0052 44EA0E04 		orr	r4, r4, lr
+ 136              	.LVL12:
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         GPIOx->AFR[position >> 3U] = temp;
+ 137              		.loc 1 224 9 is_stmt 1 view .LVU49
+ 138              		.loc 1 224 36 is_stmt 0 view .LVU50
+ 139 0056 40F82540 		str	r4, [r0, r5, lsl #2]
+ 140 005a 60E0     		b	.L6
+ 141              	.LVL13:
+ 142              	.L23:
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       }
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       temp = GPIOx->MODER;
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       GPIOx->MODER = temp;
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /*--------------------- EXTI Mode Configuration ------------------------*/
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /* Configure the External Interrupt or event for the current IO */
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         /* Enable SYSCFG Clock */
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp = SYSCFG->EXTICR[position >> 2U];
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(0x0FUL << (4U * (position & 0x03U)));
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 143              		.loc 1 242 18 view .LVU51
+ 144 005c 0524     		movs	r4, #5
+ 145 005e 00E0     		b	.L7
+ 146              	.L13:
+ 147 0060 0024     		movs	r4, #0
+ 148              	.L7:
+ 149              		.loc 1 242 40 discriminator 24 view .LVU52
+ 150 0062 04FA0EF4 		lsl	r4, r4, lr
+ 151              		.loc 1 242 14 discriminator 24 view .LVU53
+ 152 0066 2C43     		orrs	r4, r4, r5
+ 153              	.LVL14:
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2U] = temp;
+ 154              		.loc 1 243 9 is_stmt 1 discriminator 24 view .LVU54
+ 155              		.loc 1 243 40 is_stmt 0 discriminator 24 view .LVU55
+ 156 0068 0CF1020C 		add	ip, ip, #2
+ARM GAS  /tmp/ccY6DPpN.s 			page 8
+
+
+ 157 006c 554D     		ldr	r5, .L24
+ 158 006e 45F82C40 		str	r4, [r5, ip, lsl #2]
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         /* Clear Rising Falling edge configuration */
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp = EXTI->RTSR1;
+ 159              		.loc 1 246 9 is_stmt 1 discriminator 24 view .LVU56
+ 160              		.loc 1 246 14 is_stmt 0 discriminator 24 view .LVU57
+ 161 0072 554C     		ldr	r4, .L24+4
+ 162              	.LVL15:
+ 163              		.loc 1 246 14 discriminator 24 view .LVU58
+ 164 0074 A568     		ldr	r5, [r4, #8]
+ 165              	.LVL16:
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(iocurrent);
+ 166              		.loc 1 247 9 is_stmt 1 discriminator 24 view .LVU59
+ 167              		.loc 1 247 17 is_stmt 0 discriminator 24 view .LVU60
+ 168 0076 D443     		mvns	r4, r2
+ 169              		.loc 1 247 14 discriminator 24 view .LVU61
+ 170 0078 25EA0206 		bic	r6, r5, r2
+ 171              	.LVL17:
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
+ 172              		.loc 1 248 9 is_stmt 1 discriminator 24 view .LVU62
+ 173              		.loc 1 248 12 is_stmt 0 discriminator 24 view .LVU63
+ 174 007c 4F68     		ldr	r7, [r1, #4]
+ 175 007e 17F4801F 		tst	r7, #1048576
+ 176 0082 01D0     		beq	.L8
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         {
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****           temp |= iocurrent;
+ 177              		.loc 1 250 11 is_stmt 1 view .LVU64
+ 178              		.loc 1 250 16 is_stmt 0 view .LVU65
+ 179 0084 42EA0506 		orr	r6, r2, r5
+ 180              	.LVL18:
+ 181              	.L8:
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         }
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->RTSR1 = temp;
+ 182              		.loc 1 252 9 is_stmt 1 view .LVU66
+ 183              		.loc 1 252 21 is_stmt 0 view .LVU67
+ 184 0088 4F4D     		ldr	r5, .L24+4
+ 185 008a AE60     		str	r6, [r5, #8]
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp = EXTI->FTSR1;
+ 186              		.loc 1 254 9 is_stmt 1 view .LVU68
+ 187              		.loc 1 254 14 is_stmt 0 view .LVU69
+ 188 008c ED68     		ldr	r5, [r5, #12]
+ 189              	.LVL19:
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(iocurrent);
+ 190              		.loc 1 255 9 is_stmt 1 view .LVU70
+ 191              		.loc 1 255 14 is_stmt 0 view .LVU71
+ 192 008e 04EA0506 		and	r6, r4, r5
+ 193              	.LVL20:
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
+ 194              		.loc 1 256 9 is_stmt 1 view .LVU72
+ 195              		.loc 1 256 12 is_stmt 0 view .LVU73
+ 196 0092 4F68     		ldr	r7, [r1, #4]
+ 197 0094 17F4001F 		tst	r7, #2097152
+ 198 0098 01D0     		beq	.L9
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         {
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****           temp |= iocurrent;
+ARM GAS  /tmp/ccY6DPpN.s 			page 9
+
+
+ 199              		.loc 1 258 11 is_stmt 1 view .LVU74
+ 200              		.loc 1 258 16 is_stmt 0 view .LVU75
+ 201 009a 42EA0506 		orr	r6, r2, r5
+ 202              	.LVL21:
+ 203              	.L9:
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         }
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->FTSR1 = temp;
+ 204              		.loc 1 260 9 is_stmt 1 view .LVU76
+ 205              		.loc 1 260 21 is_stmt 0 view .LVU77
+ 206 009e 4A4D     		ldr	r5, .L24+4
+ 207 00a0 EE60     		str	r6, [r5, #12]
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp = EXTI->EMR1;
+ 208              		.loc 1 262 9 is_stmt 1 view .LVU78
+ 209              		.loc 1 262 14 is_stmt 0 view .LVU79
+ 210 00a2 6D68     		ldr	r5, [r5, #4]
+ 211              	.LVL22:
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(iocurrent);
+ 212              		.loc 1 263 9 is_stmt 1 view .LVU80
+ 213              		.loc 1 263 14 is_stmt 0 view .LVU81
+ 214 00a4 04EA0506 		and	r6, r4, r5
+ 215              	.LVL23:
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
+ 216              		.loc 1 264 9 is_stmt 1 view .LVU82
+ 217              		.loc 1 264 12 is_stmt 0 view .LVU83
+ 218 00a8 4F68     		ldr	r7, [r1, #4]
+ 219 00aa 17F4003F 		tst	r7, #131072
+ 220 00ae 01D0     		beq	.L10
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         {
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****           temp |= iocurrent;
+ 221              		.loc 1 266 11 is_stmt 1 view .LVU84
+ 222              		.loc 1 266 16 is_stmt 0 view .LVU85
+ 223 00b0 42EA0506 		orr	r6, r2, r5
+ 224              	.LVL24:
+ 225              	.L10:
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         }
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->EMR1 = temp;
+ 226              		.loc 1 268 9 is_stmt 1 view .LVU86
+ 227              		.loc 1 268 20 is_stmt 0 view .LVU87
+ 228 00b4 444D     		ldr	r5, .L24+4
+ 229 00b6 6E60     		str	r6, [r5, #4]
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         /* Clear EXTI line configuration */
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp = EXTI->IMR1;
+ 230              		.loc 1 271 9 is_stmt 1 view .LVU88
+ 231              		.loc 1 271 14 is_stmt 0 view .LVU89
+ 232 00b8 2D68     		ldr	r5, [r5]
+ 233              	.LVL25:
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(iocurrent);
+ 234              		.loc 1 272 9 is_stmt 1 view .LVU90
+ 235              		.loc 1 272 14 is_stmt 0 view .LVU91
+ 236 00ba 2C40     		ands	r4, r4, r5
+ 237              	.LVL26:
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
+ 238              		.loc 1 273 9 is_stmt 1 view .LVU92
+ 239              		.loc 1 273 23 is_stmt 0 view .LVU93
+ 240 00bc 4E68     		ldr	r6, [r1, #4]
+ARM GAS  /tmp/ccY6DPpN.s 			page 10
+
+
+ 241              		.loc 1 273 12 view .LVU94
+ 242 00be 16F4803F 		tst	r6, #65536
+ 243 00c2 01D0     		beq	.L11
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         {
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****           temp |= iocurrent;
+ 244              		.loc 1 275 11 is_stmt 1 view .LVU95
+ 245              		.loc 1 275 16 is_stmt 0 view .LVU96
+ 246 00c4 42EA0504 		orr	r4, r2, r5
+ 247              	.LVL27:
+ 248              	.L11:
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         }
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->IMR1 = temp;
+ 249              		.loc 1 277 9 is_stmt 1 view .LVU97
+ 250              		.loc 1 277 20 is_stmt 0 view .LVU98
+ 251 00c8 3F4A     		ldr	r2, .L24+4
+ 252              	.LVL28:
+ 253              		.loc 1 277 20 view .LVU99
+ 254 00ca 1460     		str	r4, [r2]
+ 255              	.LVL29:
+ 256              	.L3:
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       }
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     }
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     position++;
+ 257              		.loc 1 281 5 is_stmt 1 view .LVU100
+ 258              		.loc 1 281 13 is_stmt 0 view .LVU101
+ 259 00cc 0133     		adds	r3, r3, #1
+ 260              	.LVL30:
+ 261              	.L2:
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 262              		.loc 1 174 41 is_stmt 1 view .LVU102
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 263              		.loc 1 174 21 is_stmt 0 view .LVU103
+ 264 00ce 0A68     		ldr	r2, [r1]
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 265              		.loc 1 174 41 view .LVU104
+ 266 00d0 32FA03F4 		lsrs	r4, r2, r3
+ 267 00d4 74D0     		beq	.L20
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 268              		.loc 1 177 5 is_stmt 1 view .LVU105
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 269              		.loc 1 177 41 is_stmt 0 view .LVU106
+ 270 00d6 4FF0010C 		mov	ip, #1
+ 271 00da 0CFA03FC 		lsl	ip, ip, r3
+ 272              	.LVL31:
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     {
+ 273              		.loc 1 179 5 is_stmt 1 view .LVU107
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     {
+ 274              		.loc 1 179 8 is_stmt 0 view .LVU108
+ 275 00de 1CEA0202 		ands	r2, ip, r2
+ 276              	.LVL32:
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     {
+ 277              		.loc 1 179 8 view .LVU109
+ 278 00e2 F3D0     		beq	.L3
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****          ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+ 279              		.loc 1 183 7 is_stmt 1 view .LVU110
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****          ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+ARM GAS  /tmp/ccY6DPpN.s 			page 11
+
+
+ 280              		.loc 1 183 21 is_stmt 0 view .LVU111
+ 281 00e4 4C68     		ldr	r4, [r1, #4]
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****          ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+ 282              		.loc 1 183 28 view .LVU112
+ 283 00e6 04F00304 		and	r4, r4, #3
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****          ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+ 284              		.loc 1 183 57 view .LVU113
+ 285 00ea 013C     		subs	r4, r4, #1
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****          ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+ 286              		.loc 1 183 9 view .LVU114
+ 287 00ec 012C     		cmp	r4, #1
+ 288 00ee 8BD9     		bls	.L21
+ 289              	.L4:
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 290              		.loc 1 201 7 is_stmt 1 view .LVU115
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 291              		.loc 1 201 21 is_stmt 0 view .LVU116
+ 292 00f0 4C68     		ldr	r4, [r1, #4]
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 293              		.loc 1 201 28 view .LVU117
+ 294 00f2 04F00304 		and	r4, r4, #3
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 295              		.loc 1 201 10 view .LVU118
+ 296 00f6 032C     		cmp	r4, #3
+ 297 00f8 0CD0     		beq	.L5
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 298              		.loc 1 204 9 is_stmt 1 view .LVU119
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ 299              		.loc 1 207 9 view .LVU120
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ 300              		.loc 1 207 14 is_stmt 0 view .LVU121
+ 301 00fa C468     		ldr	r4, [r0, #12]
+ 302              	.LVL33:
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 303              		.loc 1 208 9 is_stmt 1 view .LVU122
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 304              		.loc 1 208 49 is_stmt 0 view .LVU123
+ 305 00fc 5D00     		lsls	r5, r3, #1
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 306              		.loc 1 208 36 view .LVU124
+ 307 00fe 4FF0030C 		mov	ip, #3
+ 308 0102 0CFA05FC 		lsl	ip, ip, r5
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 309              		.loc 1 208 14 view .LVU125
+ 310 0106 24EA0C0C 		bic	ip, r4, ip
+ 311              	.LVL34:
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         GPIOx->PUPDR = temp;
+ 312              		.loc 1 209 9 is_stmt 1 view .LVU126
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         GPIOx->PUPDR = temp;
+ 313              		.loc 1 209 28 is_stmt 0 view .LVU127
+ 314 010a 8C68     		ldr	r4, [r1, #8]
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         GPIOx->PUPDR = temp;
+ 315              		.loc 1 209 36 view .LVU128
+ 316 010c AC40     		lsls	r4, r4, r5
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         GPIOx->PUPDR = temp;
+ 317              		.loc 1 209 14 view .LVU129
+ 318 010e 44EA0C04 		orr	r4, r4, ip
+ARM GAS  /tmp/ccY6DPpN.s 			page 12
+
+
+ 319              	.LVL35:
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       }
+ 320              		.loc 1 210 9 is_stmt 1 view .LVU130
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       }
+ 321              		.loc 1 210 22 is_stmt 0 view .LVU131
+ 322 0112 C460     		str	r4, [r0, #12]
+ 323              	.LVL36:
+ 324              	.L5:
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 325              		.loc 1 214 7 is_stmt 1 view .LVU132
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 326              		.loc 1 214 21 is_stmt 0 view .LVU133
+ 327 0114 4C68     		ldr	r4, [r1, #4]
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 328              		.loc 1 214 28 view .LVU134
+ 329 0116 04F00304 		and	r4, r4, #3
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 330              		.loc 1 214 10 view .LVU135
+ 331 011a 022C     		cmp	r4, #2
+ 332 011c 88D0     		beq	.L22
+ 333              	.L6:
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+ 334              		.loc 1 228 7 is_stmt 1 view .LVU136
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+ 335              		.loc 1 228 12 is_stmt 0 view .LVU137
+ 336 011e 0468     		ldr	r4, [r0]
+ 337              	.LVL37:
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 338              		.loc 1 229 7 is_stmt 1 view .LVU138
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 339              		.loc 1 229 47 is_stmt 0 view .LVU139
+ 340 0120 4FEA430E 		lsl	lr, r3, #1
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 341              		.loc 1 229 34 view .LVU140
+ 342 0124 4FF0030C 		mov	ip, #3
+ 343 0128 0CFA0EFC 		lsl	ip, ip, lr
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 344              		.loc 1 229 12 view .LVU141
+ 345 012c 24EA0C0C 		bic	ip, r4, ip
+ 346              	.LVL38:
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       GPIOx->MODER = temp;
+ 347              		.loc 1 230 7 is_stmt 1 view .LVU142
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       GPIOx->MODER = temp;
+ 348              		.loc 1 230 26 is_stmt 0 view .LVU143
+ 349 0130 4C68     		ldr	r4, [r1, #4]
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       GPIOx->MODER = temp;
+ 350              		.loc 1 230 33 view .LVU144
+ 351 0132 04F00304 		and	r4, r4, #3
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       GPIOx->MODER = temp;
+ 352              		.loc 1 230 46 view .LVU145
+ 353 0136 04FA0EF4 		lsl	r4, r4, lr
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       GPIOx->MODER = temp;
+ 354              		.loc 1 230 12 view .LVU146
+ 355 013a 44EA0C04 		orr	r4, r4, ip
+ 356              	.LVL39:
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 357              		.loc 1 231 7 is_stmt 1 view .LVU147
+ARM GAS  /tmp/ccY6DPpN.s 			page 13
+
+
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 358              		.loc 1 231 20 is_stmt 0 view .LVU148
+ 359 013e 0460     		str	r4, [r0]
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 360              		.loc 1 235 7 is_stmt 1 view .LVU149
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 361              		.loc 1 235 21 is_stmt 0 view .LVU150
+ 362 0140 4C68     		ldr	r4, [r1, #4]
+ 363              	.LVL40:
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 364              		.loc 1 235 10 view .LVU151
+ 365 0142 14F4403F 		tst	r4, #196608
+ 366 0146 C1D0     		beq	.L3
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 367              		.loc 1 238 9 is_stmt 1 view .LVU152
+ 368              	.LBB2:
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 369              		.loc 1 238 9 view .LVU153
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 370              		.loc 1 238 9 view .LVU154
+ 371 0148 204C     		ldr	r4, .L24+8
+ 372 014a 256E     		ldr	r5, [r4, #96]
+ 373 014c 45F00105 		orr	r5, r5, #1
+ 374 0150 2566     		str	r5, [r4, #96]
+ 375              	.LVL41:
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 376              		.loc 1 238 9 view .LVU155
+ 377 0152 246E     		ldr	r4, [r4, #96]
+ 378 0154 04F00104 		and	r4, r4, #1
+ 379 0158 0194     		str	r4, [sp, #4]
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 380              		.loc 1 238 9 view .LVU156
+ 381 015a 019C     		ldr	r4, [sp, #4]
+ 382              	.LBE2:
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 383              		.loc 1 238 9 view .LVU157
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(0x0FUL << (4U * (position & 0x03U)));
+ 384              		.loc 1 240 9 view .LVU158
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(0x0FUL << (4U * (position & 0x03U)));
+ 385              		.loc 1 240 40 is_stmt 0 view .LVU159
+ 386 015c 4FEA930C 		lsr	ip, r3, #2
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp &= ~(0x0FUL << (4U * (position & 0x03U)));
+ 387              		.loc 1 240 14 view .LVU160
+ 388 0160 0CF10205 		add	r5, ip, #2
+ 389 0164 174C     		ldr	r4, .L24
+ 390 0166 54F82550 		ldr	r5, [r4, r5, lsl #2]
+ 391              	.LVL42:
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 392              		.loc 1 241 9 is_stmt 1 view .LVU161
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 393              		.loc 1 241 45 is_stmt 0 view .LVU162
+ 394 016a 03F0030E 		and	lr, r3, #3
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 395              		.loc 1 241 33 view .LVU163
+ 396 016e 4FEA8E0E 		lsl	lr, lr, #2
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 397              		.loc 1 241 26 view .LVU164
+ARM GAS  /tmp/ccY6DPpN.s 			page 14
+
+
+ 398 0172 0F24     		movs	r4, #15
+ 399 0174 04FA0EF4 		lsl	r4, r4, lr
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 400              		.loc 1 241 14 view .LVU165
+ 401 0178 25EA0405 		bic	r5, r5, r4
+ 402              	.LVL43:
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2U] = temp;
+ 403              		.loc 1 242 9 is_stmt 1 view .LVU166
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2U] = temp;
+ 404              		.loc 1 242 18 is_stmt 0 view .LVU167
+ 405 017c B0F1904F 		cmp	r0, #1207959552
+ 406 0180 3FF46EAF 		beq	.L13
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2U] = temp;
+ 407              		.loc 1 242 18 discriminator 1 view .LVU168
+ 408 0184 124C     		ldr	r4, .L24+12
+ 409 0186 A042     		cmp	r0, r4
+ 410 0188 12D0     		beq	.L14
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2U] = temp;
+ 411              		.loc 1 242 18 discriminator 3 view .LVU169
+ 412 018a 04F58064 		add	r4, r4, #1024
+ 413 018e A042     		cmp	r0, r4
+ 414 0190 10D0     		beq	.L15
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2U] = temp;
+ 415              		.loc 1 242 18 discriminator 5 view .LVU170
+ 416 0192 04F58064 		add	r4, r4, #1024
+ 417 0196 A042     		cmp	r0, r4
+ 418 0198 0ED0     		beq	.L16
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2U] = temp;
+ 419              		.loc 1 242 18 discriminator 7 view .LVU171
+ 420 019a 04F58064 		add	r4, r4, #1024
+ 421 019e A042     		cmp	r0, r4
+ 422 01a0 0CD0     		beq	.L17
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2U] = temp;
+ 423              		.loc 1 242 18 discriminator 9 view .LVU172
+ 424 01a2 04F58064 		add	r4, r4, #1024
+ 425 01a6 A042     		cmp	r0, r4
+ 426 01a8 3FF458AF 		beq	.L23
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2U] = temp;
+ 427              		.loc 1 242 18 view .LVU173
+ 428 01ac 0624     		movs	r4, #6
+ 429 01ae 58E7     		b	.L7
+ 430              	.L14:
+ 431 01b0 0124     		movs	r4, #1
+ 432 01b2 56E7     		b	.L7
+ 433              	.L15:
+ 434 01b4 0224     		movs	r4, #2
+ 435 01b6 54E7     		b	.L7
+ 436              	.L16:
+ 437 01b8 0324     		movs	r4, #3
+ 438 01ba 52E7     		b	.L7
+ 439              	.L17:
+ 440 01bc 0424     		movs	r4, #4
+ 441 01be 50E7     		b	.L7
+ 442              	.LVL44:
+ 443              	.L20:
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   }
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** }
+ARM GAS  /tmp/ccY6DPpN.s 			page 15
+
+
+ 444              		.loc 1 283 1 view .LVU174
+ 445 01c0 03B0     		add	sp, sp, #12
+ 446              	.LCFI2:
+ 447              		.cfi_def_cfa_offset 20
+ 448              		@ sp needed
+ 449 01c2 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 450              	.L25:
+ 451              		.align	2
+ 452              	.L24:
+ 453 01c4 00000140 		.word	1073807360
+ 454 01c8 00040140 		.word	1073808384
+ 455 01cc 00100240 		.word	1073876992
+ 456 01d0 00040048 		.word	1207960576
+ 457              		.cfi_endproc
+ 458              	.LFE329:
+ 460              		.section	.text.HAL_GPIO_DeInit,"ax",%progbits
+ 461              		.align	1
+ 462              		.global	HAL_GPIO_DeInit
+ 463              		.syntax unified
+ 464              		.thumb
+ 465              		.thumb_func
+ 467              	HAL_GPIO_DeInit:
+ 468              	.LVL45:
+ 469              	.LFB330:
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /**
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIO_Pin specifies the port bit to be written.
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @retval None
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** {
+ 470              		.loc 1 293 1 is_stmt 1 view -0
+ 471              		.cfi_startproc
+ 472              		@ args = 0, pretend = 0, frame = 0
+ 473              		@ frame_needed = 0, uses_anonymous_args = 0
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   uint32_t position = 0x00U;
+ 474              		.loc 1 294 3 view .LVU176
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   uint32_t iocurrent;
+ 475              		.loc 1 295 3 view .LVU177
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   uint32_t tmp;
+ 476              		.loc 1 296 3 view .LVU178
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Check the parameters */
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ 477              		.loc 1 299 3 view .LVU179
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
+ 478              		.loc 1 300 3 view .LVU180
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Configure the port pins */
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   while ((GPIO_Pin >> position) != 0U)
+ 479              		.loc 1 303 3 view .LVU181
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   uint32_t iocurrent;
+ 480              		.loc 1 294 12 is_stmt 0 view .LVU182
+ 481 0000 0023     		movs	r3, #0
+ARM GAS  /tmp/ccY6DPpN.s 			page 16
+
+
+ 482              	.LVL46:
+ 483              		.loc 1 303 33 is_stmt 1 view .LVU183
+ 484 0002 31FA03F2 		lsrs	r2, r1, r3
+ 485 0006 00F08180 		beq	.L41
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   uint32_t position = 0x00U;
+ 486              		.loc 1 293 1 is_stmt 0 view .LVU184
+ 487 000a F0B5     		push	{r4, r5, r6, r7, lr}
+ 488              	.LCFI3:
+ 489              		.cfi_def_cfa_offset 20
+ 490              		.cfi_offset 4, -20
+ 491              		.cfi_offset 5, -16
+ 492              		.cfi_offset 6, -12
+ 493              		.cfi_offset 7, -8
+ 494              		.cfi_offset 14, -4
+ 495 000c 2EE0     		b	.L31
+ 496              	.LVL47:
+ 497              	.L44:
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     /* Get current io position */
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     iocurrent = (GPIO_Pin) & (1UL << position);
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     if (iocurrent != 0x00u)
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     {
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /*------------------------- EXTI Mode Configuration --------------------*/
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /* Clear the External Interrupt or Event for the current IO */
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       tmp = SYSCFG->EXTICR[position >> 2U];
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       tmp &= (0x0FUL << (4U * (position & 0x03U)));
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+ 498              		.loc 1 315 19 view .LVU185
+ 499 000e 0525     		movs	r5, #5
+ 500 0010 00E0     		b	.L29
+ 501              	.L32:
+ 502 0012 0025     		movs	r5, #0
+ 503              	.L29:
+ 504              		.loc 1 315 41 discriminator 24 view .LVU186
+ 505 0014 05FA0CF5 		lsl	r5, r5, ip
+ 506              		.loc 1 315 10 discriminator 24 view .LVU187
+ 507 0018 A542     		cmp	r5, r4
+ 508 001a 5BD0     		beq	.L42
+ 509              	.LVL48:
+ 510              	.L30:
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         /* Clear EXTI line configuration */
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->IMR1 &= ~(iocurrent);
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->EMR1 &= ~(iocurrent);
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         /* Clear Rising Falling edge configuration */
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->FTSR1 &= ~(iocurrent);
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->RTSR1 &= ~(iocurrent);
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         tmp = 0x0FUL << (4U * (position & 0x03U));
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2U] &= ~tmp;
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       }
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /*------------------------- GPIO Mode Configuration --------------------*/
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /* Configure IO in Analog Mode */
+ARM GAS  /tmp/ccY6DPpN.s 			page 17
+
+
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
+ 511              		.loc 1 331 7 is_stmt 1 view .LVU188
+ 512              		.loc 1 331 12 is_stmt 0 view .LVU189
+ 513 001c 0468     		ldr	r4, [r0]
+ 514              		.loc 1 331 54 view .LVU190
+ 515 001e 5D00     		lsls	r5, r3, #1
+ 516              		.loc 1 331 41 view .LVU191
+ 517 0020 4FF0030C 		mov	ip, #3
+ 518 0024 0CFA05FC 		lsl	ip, ip, r5
+ 519              		.loc 1 331 20 view .LVU192
+ 520 0028 44EA0C04 		orr	r4, r4, ip
+ 521 002c 0460     		str	r4, [r0]
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /* Configure the default Alternate Function in current IO */
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u));
+ 522              		.loc 1 334 7 is_stmt 1 view .LVU193
+ 523              		.loc 1 334 17 is_stmt 0 view .LVU194
+ 524 002e 4FEAD30E 		lsr	lr, r3, #3
+ 525 0032 0EF1080E 		add	lr, lr, #8
+ 526 0036 50F82E40 		ldr	r4, [r0, lr, lsl #2]
+ 527              		.loc 1 334 58 view .LVU195
+ 528 003a 03F00706 		and	r6, r3, #7
+ 529              		.loc 1 334 67 view .LVU196
+ 530 003e B600     		lsls	r6, r6, #2
+ 531              		.loc 1 334 44 view .LVU197
+ 532 0040 0F25     		movs	r5, #15
+ 533 0042 B540     		lsls	r5, r5, r6
+ 534              		.loc 1 334 34 view .LVU198
+ 535 0044 24EA0504 		bic	r4, r4, r5
+ 536 0048 40F82E40 		str	r4, [r0, lr, lsl #2]
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
+ 537              		.loc 1 337 7 is_stmt 1 view .LVU199
+ 538              		.loc 1 337 12 is_stmt 0 view .LVU200
+ 539 004c C468     		ldr	r4, [r0, #12]
+ 540              		.loc 1 337 20 view .LVU201
+ 541 004e 24EA0C04 		bic	r4, r4, ip
+ 542 0052 C460     		str	r4, [r0, #12]
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /* Configure the default value IO Output Type */
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position);
+ 543              		.loc 1 340 7 is_stmt 1 view .LVU202
+ 544              		.loc 1 340 12 is_stmt 0 view .LVU203
+ 545 0054 4468     		ldr	r4, [r0, #4]
+ 546              		.loc 1 340 22 view .LVU204
+ 547 0056 24EA0202 		bic	r2, r4, r2
+ 548              	.LVL49:
+ 549              		.loc 1 340 22 view .LVU205
+ 550 005a 4260     		str	r2, [r0, #4]
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       /* Configure the default value for IO Speed */
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
+ 551              		.loc 1 343 7 is_stmt 1 view .LVU206
+ 552              		.loc 1 343 12 is_stmt 0 view .LVU207
+ 553 005c 8268     		ldr	r2, [r0, #8]
+ 554              		.loc 1 343 22 view .LVU208
+ARM GAS  /tmp/ccY6DPpN.s 			page 18
+
+
+ 555 005e 22EA0C02 		bic	r2, r2, ip
+ 556 0062 8260     		str	r2, [r0, #8]
+ 557              	.L28:
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     }
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     position++;
+ 558              		.loc 1 346 5 is_stmt 1 view .LVU209
+ 559              		.loc 1 346 13 is_stmt 0 view .LVU210
+ 560 0064 0133     		adds	r3, r3, #1
+ 561              	.LVL50:
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 562              		.loc 1 303 33 is_stmt 1 view .LVU211
+ 563 0066 31FA03F2 		lsrs	r2, r1, r3
+ 564 006a 4ED0     		beq	.L43
+ 565              	.LVL51:
+ 566              	.L31:
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 567              		.loc 1 306 5 view .LVU212
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 568              		.loc 1 306 35 is_stmt 0 view .LVU213
+ 569 006c 0122     		movs	r2, #1
+ 570 006e 9A40     		lsls	r2, r2, r3
+ 571              	.LVL52:
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     {
+ 572              		.loc 1 308 5 is_stmt 1 view .LVU214
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     {
+ 573              		.loc 1 308 8 is_stmt 0 view .LVU215
+ 574 0070 12EA0107 		ands	r7, r2, r1
+ 575              	.LVL53:
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     {
+ 576              		.loc 1 308 8 view .LVU216
+ 577 0074 F6D0     		beq	.L28
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       tmp &= (0x0FUL << (4U * (position & 0x03U)));
+ 578              		.loc 1 313 7 is_stmt 1 view .LVU217
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       tmp &= (0x0FUL << (4U * (position & 0x03U)));
+ 579              		.loc 1 313 37 is_stmt 0 view .LVU218
+ 580 0076 4FEA930E 		lsr	lr, r3, #2
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       tmp &= (0x0FUL << (4U * (position & 0x03U)));
+ 581              		.loc 1 313 11 view .LVU219
+ 582 007a 0EF10205 		add	r5, lr, #2
+ 583 007e 244C     		ldr	r4, .L45
+ 584 0080 54F82540 		ldr	r4, [r4, r5, lsl #2]
+ 585              	.LVL54:
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+ 586              		.loc 1 314 7 is_stmt 1 view .LVU220
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+ 587              		.loc 1 314 41 is_stmt 0 view .LVU221
+ 588 0084 03F0030C 		and	ip, r3, #3
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+ 589              		.loc 1 314 29 view .LVU222
+ 590 0088 4FEA8C0C 		lsl	ip, ip, #2
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+ 591              		.loc 1 314 22 view .LVU223
+ 592 008c 0F25     		movs	r5, #15
+ 593 008e 05FA0CF6 		lsl	r6, r5, ip
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+ 594              		.loc 1 314 11 view .LVU224
+ARM GAS  /tmp/ccY6DPpN.s 			page 19
+
+
+ 595 0092 3440     		ands	r4, r4, r6
+ 596              	.LVL55:
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 597              		.loc 1 315 7 is_stmt 1 view .LVU225
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 598              		.loc 1 315 19 is_stmt 0 view .LVU226
+ 599 0094 B0F1904F 		cmp	r0, #1207959552
+ 600 0098 BBD0     		beq	.L32
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 601              		.loc 1 315 19 discriminator 1 view .LVU227
+ 602 009a 1E4D     		ldr	r5, .L45+4
+ 603 009c A842     		cmp	r0, r5
+ 604 009e 11D0     		beq	.L33
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 605              		.loc 1 315 19 discriminator 3 view .LVU228
+ 606 00a0 05F58065 		add	r5, r5, #1024
+ 607 00a4 A842     		cmp	r0, r5
+ 608 00a6 0FD0     		beq	.L34
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 609              		.loc 1 315 19 discriminator 5 view .LVU229
+ 610 00a8 05F58065 		add	r5, r5, #1024
+ 611 00ac A842     		cmp	r0, r5
+ 612 00ae 0DD0     		beq	.L35
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 613              		.loc 1 315 19 discriminator 7 view .LVU230
+ 614 00b0 05F58065 		add	r5, r5, #1024
+ 615 00b4 A842     		cmp	r0, r5
+ 616 00b6 0BD0     		beq	.L36
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 617              		.loc 1 315 19 discriminator 9 view .LVU231
+ 618 00b8 05F58065 		add	r5, r5, #1024
+ 619 00bc A842     		cmp	r0, r5
+ 620 00be A6D0     		beq	.L44
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       {
+ 621              		.loc 1 315 19 view .LVU232
+ 622 00c0 0625     		movs	r5, #6
+ 623 00c2 A7E7     		b	.L29
+ 624              	.L33:
+ 625 00c4 0125     		movs	r5, #1
+ 626 00c6 A5E7     		b	.L29
+ 627              	.L34:
+ 628 00c8 0225     		movs	r5, #2
+ 629 00ca A3E7     		b	.L29
+ 630              	.L35:
+ 631 00cc 0325     		movs	r5, #3
+ 632 00ce A1E7     		b	.L29
+ 633              	.L36:
+ 634 00d0 0425     		movs	r5, #4
+ 635 00d2 9FE7     		b	.L29
+ 636              	.L42:
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->EMR1 &= ~(iocurrent);
+ 637              		.loc 1 318 9 is_stmt 1 view .LVU233
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->EMR1 &= ~(iocurrent);
+ 638              		.loc 1 318 13 is_stmt 0 view .LVU234
+ 639 00d4 104C     		ldr	r4, .L45+8
+ 640              	.LVL56:
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->EMR1 &= ~(iocurrent);
+ARM GAS  /tmp/ccY6DPpN.s 			page 20
+
+
+ 641              		.loc 1 318 13 view .LVU235
+ 642 00d6 2568     		ldr	r5, [r4]
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->EMR1 &= ~(iocurrent);
+ 643              		.loc 1 318 20 view .LVU236
+ 644 00d8 25EA0705 		bic	r5, r5, r7
+ 645 00dc 2560     		str	r5, [r4]
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 646              		.loc 1 319 9 is_stmt 1 view .LVU237
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 647              		.loc 1 319 13 is_stmt 0 view .LVU238
+ 648 00de 6568     		ldr	r5, [r4, #4]
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 649              		.loc 1 319 20 view .LVU239
+ 650 00e0 25EA0705 		bic	r5, r5, r7
+ 651 00e4 6560     		str	r5, [r4, #4]
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->RTSR1 &= ~(iocurrent);
+ 652              		.loc 1 322 9 is_stmt 1 view .LVU240
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->RTSR1 &= ~(iocurrent);
+ 653              		.loc 1 322 13 is_stmt 0 view .LVU241
+ 654 00e6 E568     		ldr	r5, [r4, #12]
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         EXTI->RTSR1 &= ~(iocurrent);
+ 655              		.loc 1 322 21 view .LVU242
+ 656 00e8 25EA0705 		bic	r5, r5, r7
+ 657 00ec E560     		str	r5, [r4, #12]
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 658              		.loc 1 323 9 is_stmt 1 view .LVU243
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 659              		.loc 1 323 13 is_stmt 0 view .LVU244
+ 660 00ee A568     		ldr	r5, [r4, #8]
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 661              		.loc 1 323 21 view .LVU245
+ 662 00f0 25EA0705 		bic	r5, r5, r7
+ 663 00f4 A560     		str	r5, [r4, #8]
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2U] &= ~tmp;
+ 664              		.loc 1 325 9 is_stmt 1 view .LVU246
+ 665              	.LVL57:
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       }
+ 666              		.loc 1 326 9 view .LVU247
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       }
+ 667              		.loc 1 326 23 is_stmt 0 view .LVU248
+ 668 00f6 064F     		ldr	r7, .L45
+ 669              	.LVL58:
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       }
+ 670              		.loc 1 326 23 view .LVU249
+ 671 00f8 0EF10204 		add	r4, lr, #2
+ 672 00fc 57F82450 		ldr	r5, [r7, r4, lsl #2]
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****       }
+ 673              		.loc 1 326 40 view .LVU250
+ 674 0100 25EA0605 		bic	r5, r5, r6
+ 675 0104 47F82450 		str	r5, [r7, r4, lsl #2]
+ 676 0108 88E7     		b	.L30
+ 677              	.LVL59:
+ 678              	.L43:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   }
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** }
+ 679              		.loc 1 348 1 view .LVU251
+ 680 010a F0BD     		pop	{r4, r5, r6, r7, pc}
+ARM GAS  /tmp/ccY6DPpN.s 			page 21
+
+
+ 681              	.LVL60:
+ 682              	.L41:
+ 683              	.LCFI4:
+ 684              		.cfi_def_cfa_offset 0
+ 685              		.cfi_restore 4
+ 686              		.cfi_restore 5
+ 687              		.cfi_restore 6
+ 688              		.cfi_restore 7
+ 689              		.cfi_restore 14
+ 690              		.loc 1 348 1 view .LVU252
+ 691 010c 7047     		bx	lr
+ 692              	.L46:
+ 693 010e 00BF     		.align	2
+ 694              	.L45:
+ 695 0110 00000140 		.word	1073807360
+ 696 0114 00040048 		.word	1207960576
+ 697 0118 00040140 		.word	1073808384
+ 698              		.cfi_endproc
+ 699              	.LFE330:
+ 701              		.section	.text.HAL_GPIO_ReadPin,"ax",%progbits
+ 702              		.align	1
+ 703              		.global	HAL_GPIO_ReadPin
+ 704              		.syntax unified
+ 705              		.thumb
+ 706              		.thumb_func
+ 708              	HAL_GPIO_ReadPin:
+ 709              	.LVL61:
+ 710              	.LFB331:
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /**
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @}
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /** @addtogroup GPIO_Exported_Functions_Group2
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** @verbatim
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****  ===============================================================================
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****                        ##### IO operation functions #####
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****  ===============================================================================
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** @endverbatim
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @{
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /**
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @brief  Read the specified input port pin.
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIO_Pin specifies the port bit to read.
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @retval The input port pin value.
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** {
+ 711              		.loc 1 374 1 is_stmt 1 view -0
+ 712              		.cfi_startproc
+ 713              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/ccY6DPpN.s 			page 22
+
+
+ 714              		@ frame_needed = 0, uses_anonymous_args = 0
+ 715              		@ link register save eliminated.
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   GPIO_PinState bitstatus;
+ 716              		.loc 1 375 3 view .LVU254
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Check the parameters */
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
+ 717              		.loc 1 378 3 view .LVU255
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
+ 718              		.loc 1 380 3 view .LVU256
+ 719              		.loc 1 380 13 is_stmt 0 view .LVU257
+ 720 0000 0369     		ldr	r3, [r0, #16]
+ 721              		.loc 1 380 6 view .LVU258
+ 722 0002 1942     		tst	r1, r3
+ 723 0004 01D0     		beq	.L49
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     bitstatus = GPIO_PIN_SET;
+ 724              		.loc 1 382 15 view .LVU259
+ 725 0006 0120     		movs	r0, #1
+ 726              	.LVL62:
+ 727              		.loc 1 382 15 view .LVU260
+ 728 0008 7047     		bx	lr
+ 729              	.LVL63:
+ 730              	.L49:
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   }
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   else
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     bitstatus = GPIO_PIN_RESET;
+ 731              		.loc 1 386 15 view .LVU261
+ 732 000a 0020     		movs	r0, #0
+ 733              	.LVL64:
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   }
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   return bitstatus;
+ 734              		.loc 1 388 3 is_stmt 1 view .LVU262
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** }
+ 735              		.loc 1 389 1 is_stmt 0 view .LVU263
+ 736 000c 7047     		bx	lr
+ 737              		.cfi_endproc
+ 738              	.LFE331:
+ 740              		.section	.text.HAL_GPIO_WritePin,"ax",%progbits
+ 741              		.align	1
+ 742              		.global	HAL_GPIO_WritePin
+ 743              		.syntax unified
+ 744              		.thumb
+ 745              		.thumb_func
+ 747              	HAL_GPIO_WritePin:
+ 748              	.LVL65:
+ 749              	.LFB332:
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /**
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @brief  Set or clear the selected data port bit.
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *         accesses. In this way, there is no risk of an IRQ occurring between
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *         the read and the modify access.
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *
+ARM GAS  /tmp/ccY6DPpN.s 			page 23
+
+
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIO_Pin specifies the port bit to be written.
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  PinState specifies the value to be written to the selected bit.
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *         This parameter can be one of the GPIO_PinState enum values:
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *            @arg GPIO_PIN_RESET: to clear the port pin
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *            @arg GPIO_PIN_SET: to set the port pin
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @retval None
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** {
+ 750              		.loc 1 408 1 is_stmt 1 view -0
+ 751              		.cfi_startproc
+ 752              		@ args = 0, pretend = 0, frame = 0
+ 753              		@ frame_needed = 0, uses_anonymous_args = 0
+ 754              		@ link register save eliminated.
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Check the parameters */
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
+ 755              		.loc 1 410 3 view .LVU265
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN_ACTION(PinState));
+ 756              		.loc 1 411 3 view .LVU266
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   if (PinState != GPIO_PIN_RESET)
+ 757              		.loc 1 413 3 view .LVU267
+ 758              		.loc 1 413 6 is_stmt 0 view .LVU268
+ 759 0000 0AB1     		cbz	r2, .L51
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ 760              		.loc 1 415 5 is_stmt 1 view .LVU269
+ 761              		.loc 1 415 17 is_stmt 0 view .LVU270
+ 762 0002 8161     		str	r1, [r0, #24]
+ 763 0004 7047     		bx	lr
+ 764              	.L51:
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   }
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   else
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     GPIOx->BRR = (uint32_t)GPIO_Pin;
+ 765              		.loc 1 419 5 is_stmt 1 view .LVU271
+ 766              		.loc 1 419 16 is_stmt 0 view .LVU272
+ 767 0006 8162     		str	r1, [r0, #40]
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   }
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** }
+ 768              		.loc 1 421 1 view .LVU273
+ 769 0008 7047     		bx	lr
+ 770              		.cfi_endproc
+ 771              	.LFE332:
+ 773              		.section	.text.HAL_GPIO_TogglePin,"ax",%progbits
+ 774              		.align	1
+ 775              		.global	HAL_GPIO_TogglePin
+ 776              		.syntax unified
+ 777              		.thumb
+ 778              		.thumb_func
+ 780              	HAL_GPIO_TogglePin:
+ 781              	.LVL66:
+ 782              	.LFB333:
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /**
+ARM GAS  /tmp/ccY6DPpN.s 			page 24
+
+
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @brief  Toggle the specified GPIO pin.
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIO_Pin specifies the pin to be toggled.
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @retval None
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** {
+ 783              		.loc 1 431 1 is_stmt 1 view -0
+ 784              		.cfi_startproc
+ 785              		@ args = 0, pretend = 0, frame = 0
+ 786              		@ frame_needed = 0, uses_anonymous_args = 0
+ 787              		@ link register save eliminated.
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   uint32_t odr;
+ 788              		.loc 1 432 3 view .LVU275
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Check the parameters */
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
+ 789              		.loc 1 435 3 view .LVU276
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* get current Output Data Register value */
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   odr = GPIOx->ODR;
+ 790              		.loc 1 438 3 view .LVU277
+ 791              		.loc 1 438 7 is_stmt 0 view .LVU278
+ 792 0000 4369     		ldr	r3, [r0, #20]
+ 793              	.LVL67:
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Set selected pins that were at low level, and reset ones that were high */
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+ 794              		.loc 1 441 3 is_stmt 1 view .LVU279
+ 795              		.loc 1 441 23 is_stmt 0 view .LVU280
+ 796 0002 01EA0302 		and	r2, r1, r3
+ 797              		.loc 1 441 59 view .LVU281
+ 798 0006 21EA0301 		bic	r1, r1, r3
+ 799              	.LVL68:
+ 800              		.loc 1 441 51 view .LVU282
+ 801 000a 41EA0241 		orr	r1, r1, r2, lsl #16
+ 802              		.loc 1 441 15 view .LVU283
+ 803 000e 8161     		str	r1, [r0, #24]
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** }
+ 804              		.loc 1 442 1 view .LVU284
+ 805 0010 7047     		bx	lr
+ 806              		.cfi_endproc
+ 807              	.LFE333:
+ 809              		.section	.text.HAL_GPIO_LockPin,"ax",%progbits
+ 810              		.align	1
+ 811              		.global	HAL_GPIO_LockPin
+ 812              		.syntax unified
+ 813              		.thumb
+ 814              		.thumb_func
+ 816              	HAL_GPIO_LockPin:
+ 817              	.LVL69:
+ 818              	.LFB334:
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /**
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @brief  Lock GPIO Pins configuration registers.
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ARM GAS  /tmp/ccY6DPpN.s 			page 25
+
+
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @note   The configuration of the locked GPIO pins can no longer be modified
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *         until the next reset.
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIO_Pin specifies the port bits to be locked.
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @retval None
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** {
+ 819              		.loc 1 456 1 is_stmt 1 view -0
+ 820              		.cfi_startproc
+ 821              		@ args = 0, pretend = 0, frame = 8
+ 822              		@ frame_needed = 0, uses_anonymous_args = 0
+ 823              		@ link register save eliminated.
+ 824              		.loc 1 456 1 is_stmt 0 view .LVU286
+ 825 0000 82B0     		sub	sp, sp, #8
+ 826              	.LCFI5:
+ 827              		.cfi_def_cfa_offset 8
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   __IO uint32_t tmp = GPIO_LCKR_LCKK;
+ 828              		.loc 1 457 3 is_stmt 1 view .LVU287
+ 829              		.loc 1 457 17 is_stmt 0 view .LVU288
+ 830 0002 4FF48033 		mov	r3, #65536
+ 831 0006 0193     		str	r3, [sp, #4]
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Check the parameters */
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+ 832              		.loc 1 460 3 is_stmt 1 view .LVU289
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
+ 833              		.loc 1 461 3 view .LVU290
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Apply lock key write sequence */
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   tmp |= GPIO_Pin;
+ 834              		.loc 1 464 3 view .LVU291
+ 835              		.loc 1 464 7 is_stmt 0 view .LVU292
+ 836 0008 019B     		ldr	r3, [sp, #4]
+ 837 000a 0B43     		orrs	r3, r3, r1
+ 838 000c 0193     		str	r3, [sp, #4]
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   GPIOx->LCKR = tmp;
+ 839              		.loc 1 466 3 is_stmt 1 view .LVU293
+ 840              		.loc 1 466 15 is_stmt 0 view .LVU294
+ 841 000e 019B     		ldr	r3, [sp, #4]
+ 842 0010 C361     		str	r3, [r0, #28]
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   GPIOx->LCKR = GPIO_Pin;
+ 843              		.loc 1 468 3 is_stmt 1 view .LVU295
+ 844              		.loc 1 468 15 is_stmt 0 view .LVU296
+ 845 0012 C161     		str	r1, [r0, #28]
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   GPIOx->LCKR = tmp;
+ 846              		.loc 1 470 3 is_stmt 1 view .LVU297
+ 847              		.loc 1 470 15 is_stmt 0 view .LVU298
+ 848 0014 019B     		ldr	r3, [sp, #4]
+ 849 0016 C361     		str	r3, [r0, #28]
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Read LCKK register. This read is mandatory to complete key lock sequence */
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   tmp = GPIOx->LCKR;
+ARM GAS  /tmp/ccY6DPpN.s 			page 26
+
+
+ 850              		.loc 1 472 3 is_stmt 1 view .LVU299
+ 851              		.loc 1 472 14 is_stmt 0 view .LVU300
+ 852 0018 C369     		ldr	r3, [r0, #28]
+ 853              		.loc 1 472 7 view .LVU301
+ 854 001a 0193     		str	r3, [sp, #4]
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* read again in order to confirm lock is active */
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
+ 855              		.loc 1 475 3 is_stmt 1 view .LVU302
+ 856              		.loc 1 475 13 is_stmt 0 view .LVU303
+ 857 001c C369     		ldr	r3, [r0, #28]
+ 858              		.loc 1 475 6 view .LVU304
+ 859 001e 13F4803F 		tst	r3, #65536
+ 860 0022 02D0     		beq	.L56
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     return HAL_OK;
+ 861              		.loc 1 477 12 view .LVU305
+ 862 0024 0020     		movs	r0, #0
+ 863              	.LVL70:
+ 864              	.L55:
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   }
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   else
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     return HAL_ERROR;
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   }
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** }
+ 865              		.loc 1 483 1 view .LVU306
+ 866 0026 02B0     		add	sp, sp, #8
+ 867              	.LCFI6:
+ 868              		.cfi_remember_state
+ 869              		.cfi_def_cfa_offset 0
+ 870              		@ sp needed
+ 871 0028 7047     		bx	lr
+ 872              	.LVL71:
+ 873              	.L56:
+ 874              	.LCFI7:
+ 875              		.cfi_restore_state
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   }
+ 876              		.loc 1 481 12 view .LVU307
+ 877 002a 0120     		movs	r0, #1
+ 878              	.LVL72:
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   }
+ 879              		.loc 1 481 12 view .LVU308
+ 880 002c FBE7     		b	.L55
+ 881              		.cfi_endproc
+ 882              	.LFE334:
+ 884              		.section	.text.HAL_GPIO_EXTI_Callback,"ax",%progbits
+ 885              		.align	1
+ 886              		.weak	HAL_GPIO_EXTI_Callback
+ 887              		.syntax unified
+ 888              		.thumb
+ 889              		.thumb_func
+ 891              	HAL_GPIO_EXTI_Callback:
+ 892              	.LVL73:
+ 893              	.LFB336:
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /**
+ARM GAS  /tmp/ccY6DPpN.s 			page 27
+
+
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @brief  Handle EXTI interrupt request.
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @retval None
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** {
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* EXTI line interrupt detected */
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     HAL_GPIO_EXTI_Callback(GPIO_Pin);
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   }
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** }
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** /**
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @brief  EXTI line detection callback.
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   * @retval None
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   */
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** {
+ 894              		.loc 1 506 1 is_stmt 1 view -0
+ 895              		.cfi_startproc
+ 896              		@ args = 0, pretend = 0, frame = 0
+ 897              		@ frame_needed = 0, uses_anonymous_args = 0
+ 898              		@ link register save eliminated.
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* Prevent unused argument(s) compilation warning */
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   UNUSED(GPIO_Pin);
+ 899              		.loc 1 508 3 view .LVU310
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* NOTE: This function should not be modified, when the callback is needed,
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****            the HAL_GPIO_EXTI_Callback could be implemented in the user file
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****    */
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** }
+ 900              		.loc 1 513 1 is_stmt 0 view .LVU311
+ 901 0000 7047     		bx	lr
+ 902              		.cfi_endproc
+ 903              	.LFE336:
+ 905              		.section	.text.HAL_GPIO_EXTI_IRQHandler,"ax",%progbits
+ 906              		.align	1
+ 907              		.global	HAL_GPIO_EXTI_IRQHandler
+ 908              		.syntax unified
+ 909              		.thumb
+ 910              		.thumb_func
+ 912              	HAL_GPIO_EXTI_IRQHandler:
+ 913              	.LVL74:
+ 914              	.LFB335:
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* EXTI line interrupt detected */
+ 915              		.loc 1 491 1 is_stmt 1 view -0
+ 916              		.cfi_startproc
+ 917              		@ args = 0, pretend = 0, frame = 0
+ 918              		@ frame_needed = 0, uses_anonymous_args = 0
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   /* EXTI line interrupt detected */
+ 919              		.loc 1 491 1 is_stmt 0 view .LVU313
+ 920 0000 08B5     		push	{r3, lr}
+ 921              	.LCFI8:
+ 922              		.cfi_def_cfa_offset 8
+ARM GAS  /tmp/ccY6DPpN.s 			page 28
+
+
+ 923              		.cfi_offset 3, -8
+ 924              		.cfi_offset 14, -4
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 925              		.loc 1 493 3 is_stmt 1 view .LVU314
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 926              		.loc 1 493 7 is_stmt 0 view .LVU315
+ 927 0002 054B     		ldr	r3, .L63
+ 928 0004 5B69     		ldr	r3, [r3, #20]
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   {
+ 929              		.loc 1 493 6 view .LVU316
+ 930 0006 0342     		tst	r3, r0
+ 931 0008 00D1     		bne	.L62
+ 932              	.LVL75:
+ 933              	.L59:
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 934              		.loc 1 498 1 view .LVU317
+ 935 000a 08BD     		pop	{r3, pc}
+ 936              	.LVL76:
+ 937              	.L62:
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****     HAL_GPIO_EXTI_Callback(GPIO_Pin);
+ 938              		.loc 1 495 5 is_stmt 1 view .LVU318
+ 939 000c 024B     		ldr	r3, .L63
+ 940 000e 5861     		str	r0, [r3, #20]
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ****   }
+ 941              		.loc 1 496 5 view .LVU319
+ 942 0010 FFF7FEFF 		bl	HAL_GPIO_EXTI_Callback
+ 943              	.LVL77:
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c **** 
+ 944              		.loc 1 498 1 is_stmt 0 view .LVU320
+ 945 0014 F9E7     		b	.L59
+ 946              	.L64:
+ 947 0016 00BF     		.align	2
+ 948              	.L63:
+ 949 0018 00040140 		.word	1073808384
+ 950              		.cfi_endproc
+ 951              	.LFE335:
+ 953              		.text
+ 954              	.Letext0:
+ 955              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 956              		.file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 957              		.file 4 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 958              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"
+ARM GAS  /tmp/ccY6DPpN.s 			page 29
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_gpio.c
+     /tmp/ccY6DPpN.s:21     .text.HAL_GPIO_Init:00000000 $t
+     /tmp/ccY6DPpN.s:27     .text.HAL_GPIO_Init:00000000 HAL_GPIO_Init
+     /tmp/ccY6DPpN.s:453    .text.HAL_GPIO_Init:000001c4 $d
+     /tmp/ccY6DPpN.s:461    .text.HAL_GPIO_DeInit:00000000 $t
+     /tmp/ccY6DPpN.s:467    .text.HAL_GPIO_DeInit:00000000 HAL_GPIO_DeInit
+     /tmp/ccY6DPpN.s:695    .text.HAL_GPIO_DeInit:00000110 $d
+     /tmp/ccY6DPpN.s:702    .text.HAL_GPIO_ReadPin:00000000 $t
+     /tmp/ccY6DPpN.s:708    .text.HAL_GPIO_ReadPin:00000000 HAL_GPIO_ReadPin
+     /tmp/ccY6DPpN.s:741    .text.HAL_GPIO_WritePin:00000000 $t
+     /tmp/ccY6DPpN.s:747    .text.HAL_GPIO_WritePin:00000000 HAL_GPIO_WritePin
+     /tmp/ccY6DPpN.s:774    .text.HAL_GPIO_TogglePin:00000000 $t
+     /tmp/ccY6DPpN.s:780    .text.HAL_GPIO_TogglePin:00000000 HAL_GPIO_TogglePin
+     /tmp/ccY6DPpN.s:810    .text.HAL_GPIO_LockPin:00000000 $t
+     /tmp/ccY6DPpN.s:816    .text.HAL_GPIO_LockPin:00000000 HAL_GPIO_LockPin
+     /tmp/ccY6DPpN.s:885    .text.HAL_GPIO_EXTI_Callback:00000000 $t
+     /tmp/ccY6DPpN.s:891    .text.HAL_GPIO_EXTI_Callback:00000000 HAL_GPIO_EXTI_Callback
+     /tmp/ccY6DPpN.s:906    .text.HAL_GPIO_EXTI_IRQHandler:00000000 $t
+     /tmp/ccY6DPpN.s:912    .text.HAL_GPIO_EXTI_IRQHandler:00000000 HAL_GPIO_EXTI_IRQHandler
+     /tmp/ccY6DPpN.s:949    .text.HAL_GPIO_EXTI_IRQHandler:00000018 $d
+
+NO UNDEFINED SYMBOLS
diff --git a/squeow_sw/build/stm32g4xx_hal_gpio.o b/squeow_sw/build/stm32g4xx_hal_gpio.o
new file mode 100644
index 0000000000000000000000000000000000000000..412b8a929e28a9db6a0fdf7cd4d84b5e4012512c
GIT binary patch
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diff --git a/squeow_sw/build/stm32g4xx_hal_i2c.d b/squeow_sw/build/stm32g4xx_hal_i2c.d
new file mode 100644
index 0000000..146fb77
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_i2c.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_i2c.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_i2c.lst b/squeow_sw/build/stm32g4xx_hal_i2c.lst
new file mode 100644
index 0000000..2734b40
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_i2c.lst
@@ -0,0 +1,25797 @@
+ARM GAS  /tmp/ccbUHtu7.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_i2c.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c"
+  20              		.section	.text.I2C_Flush_TXDR,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	I2C_Flush_TXDR:
+  27              	.LVL0:
+  28              	.LFB392:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @file    stm32g4xx_hal_i2c.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief   I2C HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *           + IO operation functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *           + Peripheral State and Errors functions
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   ******************************************************************************
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @attention
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * Copyright (c) 2019 STMicroelectronics.
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * All rights reserved.
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * in the root directory of this software component.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   ******************************************************************************
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   @verbatim
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   ==============================================================================
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                         ##### How to use this driver #####
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   ==============================================================================
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     The I2C HAL driver can be used as follows:
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     (#) Declare a I2C_HandleTypeDef handle structure, for example:
+ARM GAS  /tmp/ccbUHtu7.s 			page 2
+
+
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_HandleTypeDef  hi2c;
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (##) Enable the I2Cx interface clock
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (##) I2C pins configuration
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             (+++) Enable the clock for the I2C GPIOs
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             (+++) Configure I2C pins as alternate function open-drain
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (##) NVIC configuration if you need to use interrupt process
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             (+++) Configure the I2Cx interrupt priority
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             (+++) Enable the NVIC I2C IRQ Channel
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (##) DMA Configuration if you need to use DMA process
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             (+++) Declare a DMA_HandleTypeDef handle structure for
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                   the transmit or receive channel
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             (+++) Enable the DMAx interface clock using
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             (+++) Configure the DMA handle parameters
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             (+++) Configure the DMA Tx or Rx channel
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                   the DMA Tx or Rx channel
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addres
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level H
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceRead
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     *** Polling mode IO operation ***
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     =================================
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit(
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     *** Polling mode IO MEM operation ***
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     =====================================
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_W
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     *** Interrupt mode IO operation ***
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     ===================================
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Trans
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receiv
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmi
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ARM GAS  /tmp/ccbUHtu7.s 			page 3
+
+
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            This action will inform Master to generate a Stop condition to discard the communication
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     *** Interrupt mode or DMA mode IO sequential operation ***
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     ==========================================================
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           when a direction change during transfer
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) A specific option field manage the different steps of a sequential transfer
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfac
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            no sequential mode
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start con
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             and data to transfer without a final stop condition
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a 
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             start condition, address and data to transfer without a final stop cond
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             an then permit a call the same master sequential interface several time
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_D
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart 
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             and with new data to transfer if the direction change or manage only th
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             transfer
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             if no direction change and without a final stop condition in both cases
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart 
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             and with new data to transfer if the direction change or manage only th
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             transfer
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             if no direction change and with a final stop condition in both cases
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a re
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             after several call of the same master sequential interface several time
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             (link with option I2C_FIRST_AND_NEXT_FRAME).
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             Usage can, transfer several bytes one by one using
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               HAL_I2C_Master_Seq_Transmit_IT
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               or HAL_I2C_Master_Seq_Receive_IT
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               or HAL_I2C_Master_Seq_Transmit_DMA
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               or HAL_I2C_Master_Seq_Receive_DMA
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit 
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               Receive sequence permit to call the opposite interface Receive or Tra
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               without stopping the communication and so generate a restart conditio
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart c
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             each call of the same master sequential
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             interface.
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             Usage can, transfer several bytes one by one with a restart with slave 
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             each bytes using
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               HAL_I2C_Master_Seq_Transmit_IT
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               or HAL_I2C_Master_Seq_Receive_IT
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               or HAL_I2C_Master_Seq_Transmit_DMA
+ARM GAS  /tmp/ccbUHtu7.s 			page 4
+
+
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               or HAL_I2C_Master_Seq_Receive_DMA
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             generation of STOP condition.
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Different sequential I2C interfaces are listed below:
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is execut
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltC
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed 
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_A
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             HAL_I2C_DisableListen_IT()
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code to check the Address Match Code and the transmission direction reques
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (Write/Read).
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is execute
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCa
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed a
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            This action will inform Master to generate a Stop condition to discard the communication
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     *** Interrupt mode IO MEM operation ***
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     =======================================
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address 
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           HAL_I2C_Mem_Write_IT()
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           HAL_I2C_Mem_Read_IT()
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     *** DMA mode IO operation ***
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     ==============================
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           HAL_I2C_Master_Transmit_DMA()
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+ARM GAS  /tmp/ccbUHtu7.s 			page 5
+
+
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           HAL_I2C_Master_Receive_DMA()
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           HAL_I2C_Slave_Transmit_DMA()
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           HAL_I2C_Slave_Receive_DMA()
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            This action will inform Master to generate a Stop condition to discard the communication
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     *** DMA mode IO MEM operation ***
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     =================================
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           HAL_I2C_Mem_Write_DMA()
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           HAL_I2C_Mem_Read_DMA()
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      *** I2C HAL driver macros list ***
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      ==================================
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      [..]
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        Below the list of most used macros in I2C HAL driver.
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      *** Callback registration ***
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      =============================================
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      allows the user to configure dynamically the driver callbacks.
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      to register an interrupt callback.
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ARM GAS  /tmp/ccbUHtu7.s 			page 6
+
+
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      Function HAL_I2C_RegisterCallback() allows to register following callbacks:
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) ListenCpltCallback   : callback for end of listen mode.
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) ErrorCallback        : callback for error detection.
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) AbortCpltCallback    : callback for abort completion process.
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) MspInitCallback      : callback for Msp Init.
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) MspDeInitCallback    : callback for Msp DeInit.
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      This function takes as parameters the HAL peripheral handle, the Callback ID
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      and a pointer to the user callback function.
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCall
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      weak function.
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      and the Callback ID.
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      This function allows to reset following callbacks:
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) ListenCpltCallback   : callback for end of listen mode.
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) ErrorCallback        : callback for error detection.
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) AbortCpltCallback    : callback for abort completion process.
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) MspInitCallback      : callback for Msp Init.
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (+) MspDeInitCallback    : callback for Msp DeInit.
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      all callbacks are set to the corresponding weak functions:
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      Exception done for MspInit and MspDeInit functions that are
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      these callbacks are null (not registered beforehand).
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      Then, the user first registers the MspInit/MspDeInit user callbacks
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      or HAL_I2C_Init() function.
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      not defined, the callback registration feature is not available and all callbacks
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      are set to the corresponding weak functions.
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 7
+
+
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****      [..]
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (@) You can refer to the I2C HAL driver header file for more useful macros
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   @endverbatim
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Includes ------------------------------------------------------------------*/
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #include "stm32g4xx_hal.h"
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /** @addtogroup STM32G4xx_HAL_Driver
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @{
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /** @defgroup I2C I2C
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief I2C HAL module driver
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @{
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #ifdef HAL_I2C_MODULE_ENABLED
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private typedef -----------------------------------------------------------*/
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private define ------------------------------------------------------------*/
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /** @defgroup I2C_Private_Define I2C Private Define
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @{
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define MAX_NBYTE_SIZE      255U
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define SLAVE_ADDR_SHIFT     7U
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define SLAVE_ADDR_MSK       0x06U
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private define for @ref PreviousState usage */
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                          (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                               (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /*!< Mask State define, keep only RX and TX bits */
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /*!< Default Value */
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                               (uint32_t)HAL_I2C_MODE_MASTER))
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                               (uint32_t)HAL_I2C_MODE_MASTER))
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                               (uint32_t)HAL_I2C_MODE_SLAVE))
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+ARM GAS  /tmp/ccbUHtu7.s 			page 8
+
+
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                               (uint32_t)HAL_I2C_MODE_SLAVE))
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                               (uint32_t)HAL_I2C_MODE_MEM))
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                               (uint32_t)HAL_I2C_MODE_MEM))
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private define to centralize the enable/disable of Interrupts */
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /*!< Bit field can be combinated with
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                          @ref I2C_XFER_LISTEN_IT */
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /*!< Bit field can be combinated with
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                          @ref I2C_XFER_LISTEN_IT */
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /*!< Bit field can be combinated with @ref I2
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                          and @ref I2C_XFER_RX_IT */
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /*!< Bit definition to manage addition of glo
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                          and NACK treatment */
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /*!< Bit definition to manage only STOP evene
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /*!< Bit definition to manage only Reload of 
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private define Sequential Transfer Options default/reset value */
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @}
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private macro -------------------------------------------------------------*/
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Macro to get remaining data to transfer on DMA side */
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__)     __HAL_DMA_GET_COUNTER(__HANDLE__)
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private variables ---------------------------------------------------------*/
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private function prototypes -----------------------------------------------*/
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /** @defgroup I2C_Private_Functions I2C Private Functions
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @{
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private functions to handle DMA transfer */
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private functions to handle IT transfer */
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 9
+
+
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private functions to handle IT transfer */
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                 uint16_t MemAddress, uint16_t MemAddSize, uint32_t 
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                 uint32_t Tickstart);
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t T
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                uint32_t Tickstart);
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private functions for I2C transfer IRQ handler */
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                            uint32_t ITSources);
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                           uint32_t ITSources);
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                             uint32_t ITSources);
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                            uint32_t ITSources);
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private functions to handle flags during polling transfer */
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                     uint32_t Timeout, uint32_t Tickstart);
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                         uint32_t Tickstart);
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                         uint32_t Tickstart);
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                         uint32_t Tickstart);
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                              uint32_t Tickstart);
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private functions to centralize the enable/disable of Interrupts */
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private function to treat different error callback */
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private function to flush TXDR register */
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private function to handle  start, restart or stop a transfer */
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                uint32_t Request);
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Private function to Convert Specific options */
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @}
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /* Exported functions --------------------------------------------------------*/
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions I2C Exported Functions
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @{
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ARM GAS  /tmp/ccbUHtu7.s 			page 10
+
+
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *  @brief    Initialization and Configuration functions
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** @verbatim
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****  ===============================================================================
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               ##### Initialization and de-initialization functions #####
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****  ===============================================================================
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]  This subsection provides a set of functions allowing to initialize and
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           deinitialize the I2Cx peripheral:
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) User must Implement HAL_I2C_MspInit() function in which he configures
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Call the function HAL_I2C_Init() to configure the selected device with
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           the selected configuration:
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) Clock Timing
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) Own Address 1
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) Addressing mode (Master, Slave)
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) Dual Addressing mode
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) Own Address 2
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) Own Address 2 Mask
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) General call mode
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) Nostretch mode
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           of the selected I2Cx peripheral.
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** @endverbatim
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @{
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Initializes the I2C according to the specified parameters
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in the I2C_InitTypeDef and initialize the associated handle.
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the I2C handle allocation */
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c == NULL)
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_RESET)
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 11
+
+
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Allocate lock resource and initialize it */
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Lock = HAL_UNLOCKED;
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init the I2C Callback settings */
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback 
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback 
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->MspInitCallback == NULL)
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->MspInitCallback(hi2c);
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     HAL_I2C_MspInit(hi2c);
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_BUSY;
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable the selected I2C peripheral */
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_I2C_DISABLE(hi2c);
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Configure I2Cx: Frequency range */
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable Own Address1 before set the Own Address1 configuration */
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Configure I2Cx: Own Address1 and ack own address1 mode */
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else /* I2C_ADDRESSINGMODE_10BIT */
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Configure I2Cx: Addressing Master mode */
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+ARM GAS  /tmp/ccbUHtu7.s 			page 12
+
+
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable Own Address2 before set the Own Address2 configuration */
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Configure I2Cx: Dual mode and Own Address2 */
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Configure I2Cx: Generalcall and NoStretch mode */
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Enable the selected I2C peripheral */
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_I2C_ENABLE(hi2c);
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_READY;
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return HAL_OK;
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  DeInitialize the I2C peripheral.
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the I2C handle allocation */
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c == NULL)
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_BUSY;
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable the I2C Peripheral Clock */
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_I2C_DISABLE(hi2c);
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->MspDeInitCallback == NULL)
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->MspDeInitCallback(hi2c);
+ARM GAS  /tmp/ccbUHtu7.s 			page 13
+
+
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_MspDeInit(hi2c);
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_RESET;
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Release Lock */
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return HAL_OK;
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief Initialize the I2C MSP.
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(hi2c);
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             the HAL_I2C_MspInit could be implemented in the user file
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****    */
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief DeInitialize the I2C MSP.
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(hi2c);
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             the HAL_I2C_MspDeInit could be implemented in the user file
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****    */
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Register a User I2C Callback
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         To be used instead of the weak predefined callback
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  CallbackID ID of the callback to be registered
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         This parameter can be one of the following values:
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ARM GAS  /tmp/ccbUHtu7.s 			page 14
+
+
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pCallback pointer to the Callback function
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Callb
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                            pI2C_CallbackTypeDef pCallback)
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (pCallback == NULL)
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Update the error code */
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process locked */
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (HAL_I2C_STATE_READY == hi2c->State)
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     switch (CallbackID)
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MasterTxCpltCallback = pCallback;
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MasterRxCpltCallback = pCallback;
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->SlaveTxCpltCallback = pCallback;
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->SlaveRxCpltCallback = pCallback;
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ListenCpltCallback = pCallback;
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MemTxCpltCallback = pCallback;
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ARM GAS  /tmp/ccbUHtu7.s 			page 15
+
+
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MemRxCpltCallback = pCallback;
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_ERROR_CB_ID :
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCallback = pCallback;
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_ABORT_CB_ID :
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->AbortCpltCallback = pCallback;
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MSPINIT_CB_ID :
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MspInitCallback = pCallback;
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MSPDEINIT_CB_ID :
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MspDeInitCallback = pCallback;
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       default :
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update the error code */
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Return error status */
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         status =  HAL_ERROR;
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if (HAL_I2C_STATE_RESET == hi2c->State)
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     switch (CallbackID)
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MSPINIT_CB_ID :
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MspInitCallback = pCallback;
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MSPDEINIT_CB_ID :
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MspDeInitCallback = pCallback;
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       default :
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update the error code */
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Return error status */
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         status =  HAL_ERROR;
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Update the error code */
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Return error status */
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     status =  HAL_ERROR;
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccbUHtu7.s 			page 16
+
+
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Release Lock */
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return status;
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Unregister an I2C Callback
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         I2C callback is redirected to the weak predefined callback
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  CallbackID ID of the callback to be unregistered
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         This parameter can be one of the following values:
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         This parameter can be one of the following values:
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Cal
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process locked */
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (HAL_I2C_STATE_READY == hi2c->State)
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     switch (CallbackID)
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallb
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallb
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallba
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallba
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallbac
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ARM GAS  /tmp/ccbUHtu7.s 			page 17
+
+
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_ERROR_CB_ID :
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback    
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_ABORT_CB_ID :
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MSPINIT_CB_ID :
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit          
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MSPDEINIT_CB_ID :
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit        
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       default :
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update the error code */
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Return error status */
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         status =  HAL_ERROR;
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if (HAL_I2C_STATE_RESET == hi2c->State)
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     switch (CallbackID)
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MSPINIT_CB_ID :
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit          
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       case HAL_I2C_MSPDEINIT_CB_ID :
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit        
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       default :
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update the error code */
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Return error status */
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         status =  HAL_ERROR;
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         break;
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 18
+
+
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Update the error code */
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Return error status */
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     status =  HAL_ERROR;
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Release Lock */
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return status;
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Register the Slave Address Match I2C Callback
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pCallback pointer to the Address Match Callback function
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pC
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (pCallback == NULL)
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Update the error code */
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process locked */
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (HAL_I2C_STATE_READY == hi2c->State)
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->AddrCallback = pCallback;
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Update the error code */
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Return error status */
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     status =  HAL_ERROR;
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Release Lock */
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return status;
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  UnRegister the Slave Address Match I2C Callback
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined cal
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ARM GAS  /tmp/ccbUHtu7.s 			page 19
+
+
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process locked */
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (HAL_I2C_STATE_READY == hi2c->State)
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Update the error code */
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Return error status */
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     status =  HAL_ERROR;
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Release Lock */
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return status;
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @}
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *  @brief   Data transfers functions
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** @verbatim
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****  ===============================================================================
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                       ##### IO operation functions #####
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****  ===============================================================================
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     This subsection provides a set of functions allowing to manage the I2C data
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     transfers.
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     (#) There are two modes of transfer:
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (++) Blocking mode : The communication is performed in the polling mode.
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             The status of all data processing is returned by the same function
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             after finishing transfer.
+1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        (++) No-Blocking mode : The communication is performed using Interrupts
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             or DMA. These functions return the status of the transfer startup.
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             The end of the data processing will be indicated through the
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             using DMA mode.
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     (#) Blocking mode functions are :
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Master_Transmit()
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Master_Receive()
+ARM GAS  /tmp/ccbUHtu7.s 			page 20
+
+
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Transmit()
+1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Receive()
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Mem_Write()
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Mem_Read()
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_IsDeviceReady()
+1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     (#) No-Blocking mode functions with Interrupt are :
+1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Master_Transmit_IT()
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Master_Receive_IT()
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Transmit_IT()
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Receive_IT()
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Mem_Write_IT()
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Mem_Read_IT()
+1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Master_Seq_Transmit_IT()
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Master_Seq_Receive_IT()
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Seq_Transmit_IT()
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Seq_Receive_IT()
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_EnableListen_IT()
+1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_DisableListen_IT()
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Master_Abort_IT()
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     (#) No-Blocking mode functions with DMA are :
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Master_Transmit_DMA()
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Master_Receive_DMA()
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Transmit_DMA()
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Receive_DMA()
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Mem_Write_DMA()
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Mem_Read_DMA()
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Master_Seq_Transmit_DMA()
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Master_Seq_Receive_DMA()
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Seq_Receive_DMA()
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_MasterTxCpltCallback()
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_MasterRxCpltCallback()
+1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_SlaveTxCpltCallback()
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_SlaveRxCpltCallback()
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_MemTxCpltCallback()
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_MemRxCpltCallback()
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_AddrCallback()
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_ListenCpltCallback()
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_ErrorCallback()
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (++) HAL_I2C_AbortCpltCallback()
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** @endverbatim
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @{
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+1107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Transmits in master mode an amount of data in blocking mode.
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+1111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+ARM GAS  /tmp/ccbUHtu7.s 			page 21
+
+
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pD
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                           uint16_t Size, uint32_t Timeout)
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK
+1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr  = pData;
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address */
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+1151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+1153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     while (hi2c->XferCount > 0U)
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Wait until TXIS flag is set */
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Write data to TXDR */
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Increment Buffer pointer */
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+ARM GAS  /tmp/ccbUHtu7.s 			page 22
+
+
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Wait until TCR flag is set */
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           return HAL_ERROR;
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+1182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferSize = MAX_NBYTE_SIZE;
+1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+1189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         else
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferSize = hi2c->XferCount;
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+1194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until STOPF flag is set */
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear STOP Flag */
+1206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear Configuration Register 2 */
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_RESET_CR2(hi2c);
+1210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+1226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Receives in master mode an amount of data in blocking mode.
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ARM GAS  /tmp/ccbUHtu7.s 			page 23
+
+
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pDa
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          uint16_t Size, uint32_t Timeout)
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+1240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+1248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr  = pData;
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address */
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     while (hi2c->XferCount > 0U)
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Wait until RXNE flag is set */
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+1284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ARM GAS  /tmp/ccbUHtu7.s 			page 24
+
+
+1285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Read data from RXDR */
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+1288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Increment Buffer pointer */
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Wait until TCR flag is set */
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           return HAL_ERROR;
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+1302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferSize = MAX_NBYTE_SIZE;
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+1307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         else
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferSize = hi2c->XferCount;
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+1316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+1319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until STOPF flag is set */
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear STOP Flag */
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear Configuration Register 2 */
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_RESET_CR2(hi2c);
+1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+1333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+1338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+ARM GAS  /tmp/ccbUHtu7.s 			page 25
+
+
+1342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+1344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Transmits in slave mode an amount of data in blocking mode.
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+1353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          uint32_t Timeout)
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+1358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr  = pData;
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until ADDR flag is set */
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear ADDR flag */
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+1394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* If 10bit addressing mode is selected */
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Wait until ADDR flag is set */
+ARM GAS  /tmp/ccbUHtu7.s 			page 26
+
+
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+1400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+1401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Disable Address Acknowledge */
+1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+1405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Clear ADDR flag */
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until DIR flag is set Transmitter mode */
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+1412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     while (hi2c->XferCount > 0U)
+1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Wait until TXIS flag is set */
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Disable Address Acknowledge */
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+1427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Write data to TXDR */
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Increment Buffer pointer */
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+1433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+1435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until AF flag is set */
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+1439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Flush TX register */
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Flush_TXDR(hi2c);
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear AF flag */
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until STOP flag is set */
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ARM GAS  /tmp/ccbUHtu7.s 			page 27
+
+
+1456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear STOP flag */
+1461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+1462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until BUSY flag is reset */
+1464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+1465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable Address Acknowledge */
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+1476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+1483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+1487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+1489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Receive in slave mode an amount of data in blocking mode
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+1495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+1498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                         uint32_t Timeout)
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+1501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+1505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+1508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+ARM GAS  /tmp/ccbUHtu7.s 			page 28
+
+
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr  = pData;
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize = hi2c->XferCount;
+1523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+1524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+1527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until ADDR flag is set */
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear ADDR flag */
+1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until DIR flag is reset Receiver mode */
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     while (hi2c->XferCount > 0U)
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Wait until RXNE flag is set */
+1550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+1552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Disable Address Acknowledge */
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Store Last receive data if any */
+1556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+1558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Read data from RXDR */
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+1560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Increment Buffer pointer */
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->pBuffPtr++;
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferCount--;
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferSize--;
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+1567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ARM GAS  /tmp/ccbUHtu7.s 			page 29
+
+
+1570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Read data from RXDR */
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+1573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Increment Buffer pointer */
+1575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until STOP flag is set */
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear STOP flag */
+1590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until BUSY flag is reset */
+1593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+1594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+1598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable Address Acknowledge */
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+1610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+1616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+1618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ARM GAS  /tmp/ccbUHtu7.s 			page 30
+
+
+1627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t 
+1628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                              uint16_t Size)
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+1630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_BUSY;
+1637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+1644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+1658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+1661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address */
+1664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRIT
+1666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+1671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               process unlock */
+1673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+1675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* possible to enable all of these */
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+1677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+1678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+1679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+1683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 31
+
+
+1684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+1687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+1690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+1693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+1694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                             uint16_t Size)
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+1706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_BUSY;
+1708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+1716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+1719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+1727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+1729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+1731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+1732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address */
+1735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 32
+
+
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+1743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               process unlock */
+1744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* possible to enable all of these */
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+1748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+1750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+1760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+1768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+1780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+1783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               process unlock */
+1794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+1796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* possible to enable all of these */
+1797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ARM GAS  /tmp/ccbUHtu7.s 			page 33
+
+
+1798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+1799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+1802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+1804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+1808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
+1811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+1817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+1818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+1819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+1826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+1827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+1829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+1833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+1835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+1843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               process unlock */
+1844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+1846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* possible to enable all of these */
+1847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+1848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+1850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+1852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+1854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 34
+
+
+1855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+1857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
+1861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+1864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+1868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+1869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t
+1870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                               uint16_t Size)
+1871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+1872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+1873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+1874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+1878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_BUSY;
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+1886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+1888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+1892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+1893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+1894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+1898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+1899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+1901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+1904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferSize > 0U)
+1907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->hdmatx != NULL)
+1909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+1910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set the I2C DMA transfer complete callback */
+1911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+ARM GAS  /tmp/ccbUHtu7.s 			page 35
+
+
+1912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set the DMA error callback */
+1914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set the unused DMA callbacks to NULL */
+1917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferHalfCpltCallback = NULL;
+1918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+1919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Enable the DMA channel */
+1921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->
+1922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+1924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+1925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+1926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C state */
+1927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+1928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+1929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C error code */
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+1932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+1935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+1938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (dmaxferstatus == HAL_OK)
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+1941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Send Slave Address */
+1942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART 
+1943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_
+1944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update XferCount value */
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->XferCount -= hi2c->XferSize;
+1947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+1949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+1950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Note : The I2C interrupts must be enabled after unlocking current process
+1952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                   to avoid the risk of I2C interrupt handle execution before current
+1953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                   process unlock */
+1954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Enable ERR and NACK interrupts */
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+1956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Enable DMA Request */
+1958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+1959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+1960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+1961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+1962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C state */
+1963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+1964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+1965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C error code */
+1967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+1968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 36
+
+
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+1971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+1973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+1974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+1976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+1977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update Transfer ISR function pointer */
+1978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferISR = I2C_Master_ISR_IT;
+1979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Send Slave Address */
+1981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set NBYTES to write and generate START condition */
+1982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+1983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+1984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+1987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+1989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+1990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 process unlock */
+1991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+1992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* possible to enable all of these */
+1993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+1994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+1995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+1996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+1997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+1998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+1999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+2001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+2003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+2005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+2007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
+2008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+2016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t 
+2017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                              uint16_t Size)
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+2019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+2020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccbUHtu7.s 			page 37
+
+
+2026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_BUSY;
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+2033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+2034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+2035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+2038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+2039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+2040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+2041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+2045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+2046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+2051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferSize > 0U)
+2054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->hdmarx != NULL)
+2056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set the I2C DMA transfer complete callback */
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+2059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set the DMA error callback */
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+2062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set the unused DMA callbacks to NULL */
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferHalfCpltCallback = NULL;
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+2066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Enable the DMA channel */
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p
+2069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+2070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+2072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+2073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C state */
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+2075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+2076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C error code */
+2078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+2081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 38
+
+
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+2084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+2085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (dmaxferstatus == HAL_OK)
+2087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+2088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Send Slave Address */
+2089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART *
+2090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_
+2091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update XferCount value */
+2093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->XferCount -= hi2c->XferSize;
+2094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+2097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Note : The I2C interrupts must be enabled after unlocking current process
+2099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                   to avoid the risk of I2C interrupt handle execution before current
+2100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                   process unlock */
+2101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Enable ERR and NACK interrupts */
+2102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+2103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Enable DMA Request */
+2105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+2106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+2108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+2109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C state */
+2110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+2111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+2112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C error code */
+2114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+2115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+2118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+2121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update Transfer ISR function pointer */
+2125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferISR = I2C_Master_ISR_IT;
+2126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Send Slave Address */
+2128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set NBYTES to read and generate START condition */
+2129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+2131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+2136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+2137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 process unlock */
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* possible to enable all of these */
+ARM GAS  /tmp/ccbUHtu7.s 			page 39
+
+
+2140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+2141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+2142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+2143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+2146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+2150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
+2155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size
+2162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+2163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+2176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+2177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+2181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+2184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+2185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->hdmatx != NULL)
+2187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the I2C DMA transfer complete callback */
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+2190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the DMA error callback */
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the unused DMA callbacks to NULL */
+2195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferHalfCpltCallback = NULL;
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ARM GAS  /tmp/ccbUHtu7.s 			page 40
+
+
+2197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable the DMA channel */
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+2201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C state */
+2205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+2207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C error code */
+2209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+2210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (dmaxferstatus == HAL_OK)
+2218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable Address Acknowledge */
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+2221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+2226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+2227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 process unlock */
+2228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR, STOP, NACK, ADDR interrupts */
+2229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+2230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable DMA Request */
+2232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+2233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C state */
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+2238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C error code */
+2241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+2242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+2250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+2252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+ARM GAS  /tmp/ccbUHtu7.s 			page 41
+
+
+2254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+2256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+2258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
+2259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+2264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+2265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+2266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+2267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+2268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+2275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+2281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+2282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+2285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+2287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+2288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+2289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->hdmarx != NULL)
+2291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the I2C DMA transfer complete callback */
+2293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the DMA error callback */
+2296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+2297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the unused DMA callbacks to NULL */
+2299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferHalfCpltCallback = NULL;
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+2301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable the DMA channel */
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa
+2304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+2305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C state */
+2309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+2310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ARM GAS  /tmp/ccbUHtu7.s 			page 42
+
+
+2311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C error code */
+2313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+2314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (dmaxferstatus == HAL_OK)
+2322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable Address Acknowledge */
+2324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+2325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+2330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 process unlock */
+2332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR, STOP, NACK, ADDR interrupts */
+2333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+2334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable DMA Request */
+2336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+2337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C state */
+2341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+2342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C error code */
+2345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+2354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+2356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+2358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Write an amount of data in blocking mode to a specific memory address
+2362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+2367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+ARM GAS  /tmp/ccbUHtu7.s 			page 43
+
+
+2368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+2371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+2372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+2373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddre
+2374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                     uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Ti
+2375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+2376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+2377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+2379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+2380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+2390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+2393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+2394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK
+2396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+2401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MEM;
+2402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+2403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr  = pData;
+2406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+2407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address and Memory Address */
+2410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL
+2411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+2421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST
+2422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccbUHtu7.s 			page 44
+
+
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+2426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS
+2427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     do
+2430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Wait until TXIS flag is set */
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+2434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+2435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+2436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Write data to TXDR */
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Increment Buffer pointer */
+2441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+2442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+2444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+2445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+2447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+2448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Wait until TCR flag is set */
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+2450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+2451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           return HAL_ERROR;
+2452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+2453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+2456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferSize = MAX_NBYTE_SIZE;
+2457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+2458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+2459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         else
+2461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+2462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferSize = hi2c->XferCount;
+2463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+2465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+2466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     } while (hi2c->XferCount > 0U);
+2469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+2471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until STOPF flag is reset */
+2472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+2473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear STOP Flag */
+2478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+2479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear Configuration Register 2 */
+2481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_RESET_CR2(hi2c);
+ARM GAS  /tmp/ccbUHtu7.s 			page 45
+
+
+2482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+2484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+2485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+2487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+2488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+2490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+2494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+2496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+2498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Read an amount of data in blocking mode from a specific memory address
+2499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+2504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+2505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+2508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+2509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+2510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddres
+2511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Tim
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+2513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+2514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+2516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+2517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+2524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+2530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+2531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK
+2533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+2538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MEM;
+ARM GAS  /tmp/ccbUHtu7.s 			page 46
+
+
+2539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+2540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr  = pData;
+2543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+2544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+2545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address and Memory Address */
+2547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_
+2548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address */
+2555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+2556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+2559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+2560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+2561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+2565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+2566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+2567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     do
+2570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Wait until RXNE flag is set */
+2572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+2573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+2574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+2575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+2576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Read data from RXDR */
+2578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+2579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Increment Buffer pointer */
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+2582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+2584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+2585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+2587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+2588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Wait until TCR flag is set */
+2589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+2590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+2591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           return HAL_ERROR;
+2592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+2593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ARM GAS  /tmp/ccbUHtu7.s 			page 47
+
+
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferSize = MAX_NBYTE_SIZE;
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+2598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+2599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+2600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         else
+2601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferSize = hi2c->XferCount;
+2603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+2604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+2605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+2606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+2607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     } while (hi2c->XferCount > 0U);
+2608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+2610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until STOPF flag is reset */
+2611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+2612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear STOP Flag */
+2617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+2618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear Configuration Register 2 */
+2620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_RESET_CR2(hi2c);
+2621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+2623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+2624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+2626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+2627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+2629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+2631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+2633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+2635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+2636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory addres
+2637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+2642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+2643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+2646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+2647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd
+2648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+2649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+2650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+2651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+2652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 48
+
+
+2653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+2654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+2655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+2662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+2665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_BUSY;
+2667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+2670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+2673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+2674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+2676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+2677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+2678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+2681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+2682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+2683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+2684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+2688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+2689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+2693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+2694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address and Memory Address */
+2697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstar
+2698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         != HAL_OK)
+2699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+2706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+2707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+2709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+ARM GAS  /tmp/ccbUHtu7.s 			page 49
+
+
+2710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+2712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+2713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               process unlock */
+2714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+2716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* possible to enable all of these */
+2717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+2718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+2719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+2720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+2722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+2724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+2726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+2728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+2730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory addre
+2731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+2736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+2737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+2740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+2741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAdd
+2742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+2743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+2744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+2745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+2746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+2748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+2749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+2756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+2759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_BUSY;
+2761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+2764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+ARM GAS  /tmp/ccbUHtu7.s 			page 50
+
+
+2767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+2768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+2770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+2771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+2772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+2775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+2776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+2777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+2778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+2782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+2787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+2788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address and Memory Address */
+2791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart
+2792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+2799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ
+2800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+2802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+2803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+2805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+2806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               process unlock */
+2807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* possible to enable all of these */
+2810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+2811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+2812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+2813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+2815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+2817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+2819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+2821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+2822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
+2823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ARM GAS  /tmp/ccbUHtu7.s 			page 51
+
+
+2824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+2828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+2829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+2832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+2833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemA
+2834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                         uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+2835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+2836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+2838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+2839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+2841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+2842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+2849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+2852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_BUSY;
+2854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+2860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+2861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+2863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+2865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+2868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+2869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+2870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+2880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ARM GAS  /tmp/ccbUHtu7.s 			page 52
+
+
+2881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address and Memory Address */
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstar
+2885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         != HAL_OK)
+2886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->hdmatx != NULL)
+2894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the I2C DMA transfer complete callback */
+2896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+2897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the DMA error callback */
+2899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+2900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the unused DMA callbacks to NULL */
+2902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferHalfCpltCallback = NULL;
+2903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+2904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable the DMA channel */
+2906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX
+2907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+2908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C state */
+2912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_READY;
+2913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+2914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C error code */
+2916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+2917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (dmaxferstatus == HAL_OK)
+2925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Send Slave Address */
+2927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+2928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+2929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update XferCount value */
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount -= hi2c->XferSize;
+2932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+2937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+ARM GAS  /tmp/ccbUHtu7.s 			page 53
+
+
+2938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 process unlock */
+2939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR and NACK interrupts */
+2940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+2941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable DMA Request */
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+2944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+2946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C state */
+2948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_READY;
+2949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+2950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C error code */
+2952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+2953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+2955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+2958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+2961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+2963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+2965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+2966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+2967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+2969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+2970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+2975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+2976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be read
+2978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+2979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+2980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd
+2981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+2982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+2983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+2984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+2985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+2986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+2988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+2989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+2994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ARM GAS  /tmp/ccbUHtu7.s 			page 54
+
+
+2995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+2996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+2997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+2998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+2999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_BUSY;
+3001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+3004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+3007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+3008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+3010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+3011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+3012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+3017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+3018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+3020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+3022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+3023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+3027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+3028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address and Memory Address */
+3031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart
+3032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+3034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+3036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->hdmarx != NULL)
+3039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the I2C DMA transfer complete callback */
+3041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+3042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the DMA error callback */
+3044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+3045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the unused DMA callbacks to NULL */
+3047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferHalfCpltCallback = NULL;
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+3049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable the DMA channel */
+3051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa
+ARM GAS  /tmp/ccbUHtu7.s 			page 55
+
+
+3052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+3053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C state */
+3057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_READY;
+3058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C error code */
+3061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+3062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+3064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+3067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (dmaxferstatus == HAL_OK)
+3070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+3072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_RE
+3073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update XferCount value */
+3075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount -= hi2c->XferSize;
+3076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+3078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+3081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+3082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 process unlock */
+3083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR and NACK interrupts */
+3084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+3085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable DMA Request */
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+3088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C state */
+3092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_READY;
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+3094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C error code */
+3096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+3097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+3099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+3102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+3105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+3107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+ARM GAS  /tmp/ccbUHtu7.s 			page 56
+
+
+3109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+3111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+3113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Checks if target device is ready for communication.
+3114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @note   This function is used with Memory devices
+3115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+3118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+3119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Trials Number of trials
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+3121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+3122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+3123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Tria
+3124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                         uint32_t Timeout)
+3125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+3126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+3127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __IO uint32_t I2C_Trials = 0UL;
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   FlagStatus tmp1;
+3131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   FlagStatus tmp2;
+3132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+3134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+3136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_BUSY;
+3138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_BUSY;
+3144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+3145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     do
+3147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Generate Start */
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
+3150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+3152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Wait until STOPF flag is set or a NACK flag is set*/
+3153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tickstart = HAL_GetTick();
+3154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+3156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       while ((tmp1 == RESET) && (tmp2 == RESET))
+3159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (Timeout != HAL_MAX_DELAY)
+3161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+3162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+3163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+3164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Update I2C state */
+3165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             hi2c->State = HAL_I2C_STATE_READY;
+ARM GAS  /tmp/ccbUHtu7.s 			page 57
+
+
+3166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Update I2C error code */
+3168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+3169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Process Unlocked */
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             __HAL_UNLOCK(hi2c);
+3172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             return HAL_ERROR;
+3174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+3175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+3176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+3178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+3179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Check if the NACKF flag has not been set */
+3182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+3183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Wait until STOPF flag is reset */
+3185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+3186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+3187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           return HAL_ERROR;
+3188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+3189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Clear STOP Flag */
+3191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+3192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Device is ready */
+3194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+3195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+3197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+3198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_OK;
+3200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+3202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Wait until STOPF flag is reset */
+3204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+3205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+3206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           return HAL_ERROR;
+3207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+3208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Clear NACK Flag */
+3210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+3211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Clear STOP Flag, auto generated with autoend*/
+3213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+3214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Check if the maximum allowed number of trials has been reached */
+3217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (I2C_Trials == Trials)
+3218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Generate Stop */
+3220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR2 |= I2C_CR2_STOP;
+3221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Wait until STOPF flag is reset */
+ARM GAS  /tmp/ccbUHtu7.s 			page 58
+
+
+3223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+3224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+3225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           return HAL_ERROR;
+3226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+3227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Clear STOP Flag */
+3229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+3230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Increment Trials */
+3233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Trials++;
+3234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     } while (I2C_Trials < Trials);
+3235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Update I2C state */
+3237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+3238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Update I2C error code */
+3240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+3241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+3243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+3244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+3246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+3248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+3250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+3252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+3254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Inte
+3255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+3256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+3259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+3260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+3261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+3262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+3263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+3264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+3265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint
+3266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                  uint16_t Size, uint32_t XferOptions)
+3267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+3268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+3269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+3270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+3272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+3273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+3275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+ARM GAS  /tmp/ccbUHtu7.s 			page 59
+
+
+3280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+3281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+3282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+3287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+3288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+3290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+3291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+3293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+3294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+3298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+3299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* If transfer direction not change and there is no request to start another frame,
+3302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        do not generate Restart Condition */
+3303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Mean Previous state is same as current state */
+3304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+3305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+3306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xferrequest = I2C_NO_STARTSTOP;
+3308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Convert OTHER_xxx XferOptions if any */
+3312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_ConvertOtherXferOptions(hi2c);
+3313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update xfermode accordingly if no reload is necessary */
+3315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+3316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         xfermode = hi2c->XferOptions;
+3318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address and set NBYTES to write */
+3322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+3323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+3325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+3326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+3328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+3329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               process unlock */
+3330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+3331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+3333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+3335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+ARM GAS  /tmp/ccbUHtu7.s 			page 60
+
+
+3337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+3339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+3341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+3342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+3343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+3346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+3347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+3348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+3349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+3350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+3351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+3352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin
+3353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                   uint16_t Size, uint32_t XferOptions)
+3354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+3355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+3356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+3357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+3358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+3360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+3361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+3363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+3368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+3369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+3370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+3376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+3378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+3382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+3387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* If transfer direction not change and there is no request to start another frame,
+3390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        do not generate Restart Condition */
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Mean Previous state is same as current state */
+3392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ARM GAS  /tmp/ccbUHtu7.s 			page 61
+
+
+3394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xferrequest = I2C_NO_STARTSTOP;
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Convert OTHER_xxx XferOptions if any */
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_ConvertOtherXferOptions(hi2c);
+3401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update xfermode accordingly if no reload is necessary */
+3403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+3404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         xfermode = hi2c->XferOptions;
+3406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferSize > 0U)
+3410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->hdmatx != NULL)
+3412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set the I2C DMA transfer complete callback */
+3414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+3415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set the DMA error callback */
+3417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+3418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set the unused DMA callbacks to NULL */
+3420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferHalfCpltCallback = NULL;
+3421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+3422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Enable the DMA channel */
+3424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->
+3425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+3426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+3428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C state */
+3430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+3431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+3432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C error code */
+3434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+3435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+3437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+3440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (dmaxferstatus == HAL_OK)
+3443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Send Slave Address and set NBYTES to write */
+3445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+3446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update XferCount value */
+3448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->XferCount -= hi2c->XferSize;
+3449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+ARM GAS  /tmp/ccbUHtu7.s 			page 62
+
+
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+3452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Note : The I2C interrupts must be enabled after unlocking current process
+3454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                   to avoid the risk of I2C interrupt handle execution before current
+3455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                   process unlock */
+3456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Enable ERR and NACK interrupts */
+3457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+3458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Enable DMA Request */
+3460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+3461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+3463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C state */
+3465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+3467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C error code */
+3469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+3470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+3472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+3473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+3475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update Transfer ISR function pointer */
+3480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferISR = I2C_Master_ISR_IT;
+3481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Send Slave Address */
+3483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set NBYTES to write and generate START condition */
+3484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+3486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+3488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+3491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+3492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 process unlock */
+3493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+3494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* possible to enable all of these */
+3495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+3496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+3497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+3498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+3501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+3503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+3505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 63
+
+
+3508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+3509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Inter
+3510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+3511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+3514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+3515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+3516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+3517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+3518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+3519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+3520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8
+3521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                 uint16_t Size, uint32_t XferOptions)
+3522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+3523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+3524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_READ;
+3525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+3527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+3528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+3530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+3535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+3536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+3537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+3542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+3543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+3545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+3546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+3548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+3549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+3553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+3554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* If transfer direction not change and there is no request to start another frame,
+3557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        do not generate Restart Condition */
+3558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Mean Previous state is same as current state */
+3559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+3560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+3561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xferrequest = I2C_NO_STARTSTOP;
+3563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+ARM GAS  /tmp/ccbUHtu7.s 			page 64
+
+
+3565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Convert OTHER_xxx XferOptions if any */
+3567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_ConvertOtherXferOptions(hi2c);
+3568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update xfermode accordingly if no reload is necessary */
+3570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+3571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         xfermode = hi2c->XferOptions;
+3573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Slave Address and set NBYTES to read */
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+3578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+3580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+3581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+3583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+3584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               process unlock */
+3585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+3586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+3588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+3590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+3592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+3594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+3596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+3597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+3598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+3601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+3602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+3603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+3604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+3605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+3606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+3607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint
+3608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                  uint16_t Size, uint32_t XferOptions)
+3609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+3610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+3611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_READ;
+3612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+3613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+3615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+3616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+3618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+3620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 65
+
+
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+3623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+3625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+3630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+3631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+3633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+3634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+3636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+3637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+3641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+3642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* If transfer direction not change and there is no request to start another frame,
+3645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        do not generate Restart Condition */
+3646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Mean Previous state is same as current state */
+3647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+3648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+3649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xferrequest = I2C_NO_STARTSTOP;
+3651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Convert OTHER_xxx XferOptions if any */
+3655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_ConvertOtherXferOptions(hi2c);
+3656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update xfermode accordingly if no reload is necessary */
+3658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+3659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         xfermode = hi2c->XferOptions;
+3661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferSize > 0U)
+3665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->hdmarx != NULL)
+3667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set the I2C DMA transfer complete callback */
+3669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set the DMA error callback */
+3672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+3673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set the unused DMA callbacks to NULL */
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferHalfCpltCallback = NULL;
+3676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+3677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Enable the DMA channel */
+ARM GAS  /tmp/ccbUHtu7.s 			page 66
+
+
+3679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p
+3680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C state */
+3685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+3686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+3687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C error code */
+3689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+3690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+3692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+3693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+3695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (dmaxferstatus == HAL_OK)
+3698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Send Slave Address and set NBYTES to read */
+3700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+3701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update XferCount value */
+3703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->XferCount -= hi2c->XferSize;
+3704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+3706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+3707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Note : The I2C interrupts must be enabled after unlocking current process
+3709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                   to avoid the risk of I2C interrupt handle execution before current
+3710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                   process unlock */
+3711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Enable ERR and NACK interrupts */
+3712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+3713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Enable DMA Request */
+3715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+3716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+3718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C state */
+3720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+3721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+3722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Update I2C error code */
+3724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+3725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+3727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+3728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+3730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update Transfer ISR function pointer */
+3735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferISR = I2C_Master_ISR_IT;
+ARM GAS  /tmp/ccbUHtu7.s 			page 67
+
+
+3736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Send Slave Address */
+3738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set NBYTES to read and generate START condition */
+3739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+3740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+3741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+3743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+3746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+3747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 process unlock */
+3748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+3749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* possible to enable all of these */
+3750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+3751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+3752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+3753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+3756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+3758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+3760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+3762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+3764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit
+3765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+3766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+3769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+3770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+3771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+3772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+3773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S
+3774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                 uint32_t XferOptions)
+3775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+3776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+3777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+3778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+3780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+3782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+3784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+3785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+3788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+3789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+3791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 68
+
+
+3793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+3794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* and then toggle the HAL slave RX state to TX state */
+3795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+3796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable associated Interrupts */
+3798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+3799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Abort DMA Xfer if any */
+3801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+3802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+3804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->hdmarx != NULL)
+3806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+3807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Set the I2C DMA Abort callback :
+3808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+3809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+3810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Abort DMA RX */
+3812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+3813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+3814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Call Directly XferAbortCallback function in case of error */
+3815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+3816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+3817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+3818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+3822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+3823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+3824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+3826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+3827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+3832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+3833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+3834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+3836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Clear ADDR flag after prepare the transfer parameters */
+3838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* This action will generate an acknowledge to the Master */
+3839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+3840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+3843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+3844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+3846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     to avoid the risk of I2C interrupt handle execution before current
+3847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     process unlock */
+3848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* REnable ADDR interrupt */
+3849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+ARM GAS  /tmp/ccbUHtu7.s 			page 69
+
+
+3850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+3852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+3854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+3856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+3857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+3858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+3860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit
+3861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+3862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+3865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+3866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+3867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+3868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+3869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t 
+3870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                  uint32_t XferOptions)
+3871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+3872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+3873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+3875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+3876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+3878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+3879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+3880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+3882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+3883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+3889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+3890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+3892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* and then toggle the HAL slave RX state to TX state */
+3893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+3894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable associated Interrupts */
+3896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+3897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+3899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Abort DMA Xfer if any */
+3901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->hdmarx != NULL)
+3902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+3903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+3904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Set the I2C DMA Abort callback :
+3906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ARM GAS  /tmp/ccbUHtu7.s 			page 70
+
+
+3907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+3908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Abort DMA RX */
+3910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+3911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+3912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Call Directly XferAbortCallback function in case of error */
+3913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+3914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+3915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+3916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+3919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+3921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+3922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+3923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Abort DMA Xfer if any */
+3925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->hdmatx != NULL)
+3926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+3927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Set the I2C DMA Abort callback :
+3928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+3929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+3930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Abort DMA TX */
+3932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+3933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+3934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Call Directly XferAbortCallback function in case of error */
+3935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+3936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+3937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+3938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+3939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Nothing to do */
+3943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+3946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+3947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+3948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+3950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+3951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+3956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+3957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+3958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->hdmatx != NULL)
+3960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the I2C DMA transfer complete callback */
+3962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+3963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 71
+
+
+3964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the DMA error callback */
+3965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+3966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the unused DMA callbacks to NULL */
+3968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferHalfCpltCallback = NULL;
+3969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+3970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable the DMA channel */
+3972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX
+3973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+3974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C state */
+3978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+3979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+3980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C error code */
+3982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+3983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+3985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+3988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (dmaxferstatus == HAL_OK)
+3991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+3992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update XferCount value */
+3993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount -= hi2c->XferSize;
+3994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+3995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Reset XferSize */
+3996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = 0;
+3997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+3998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+3999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C state */
+4001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+4002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+4003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C error code */
+4005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+4006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+4008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+4009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+4011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+4014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Clear ADDR flag after prepare the transfer parameters */
+4016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* This action will generate an acknowledge to the Master */
+4017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+4018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+ARM GAS  /tmp/ccbUHtu7.s 			page 72
+
+
+4021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+4022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable DMA Request */
+4024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+4025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+4027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     to avoid the risk of I2C interrupt handle execution before current
+4028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     process unlock */
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable ERR, STOP, NACK, ADDR interrupts */
+4030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+4031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+4033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+4035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+4037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with
+4042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+4043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+4046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+4047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+4048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+4049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Si
+4051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                uint32_t XferOptions)
+4052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+4054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+4055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+4057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+4059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+4061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+4062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+4065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+4066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+4068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+4069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+4071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* and then toggle the HAL slave TX state to RX state */
+4072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+4073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable associated Interrupts */
+4075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+4076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ARM GAS  /tmp/ccbUHtu7.s 			page 73
+
+
+4078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+4079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+4080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Abort DMA Xfer if any */
+4082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->hdmatx != NULL)
+4083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+4084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Set the I2C DMA Abort callback :
+4085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+4086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+4087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Abort DMA TX */
+4089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+4090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+4091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Call Directly XferAbortCallback function in case of error */
+4092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+4093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+4094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+4095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+4096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+4099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+4100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+4101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+4103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+4104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+4106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+4107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+4108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+4109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+4110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+4111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+4113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Clear ADDR flag after prepare the transfer parameters */
+4115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* This action will generate an acknowledge to the Master */
+4116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+4117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+4120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+4121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+4123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     to avoid the risk of I2C interrupt handle execution before current
+4124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     process unlock */
+4125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* REnable ADDR interrupt */
+4126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+4127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+4129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+4131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+4133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ARM GAS  /tmp/ccbUHtu7.s 			page 74
+
+
+4135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with
+4138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+4139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+4142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+4143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+4144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+4145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S
+4147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                 uint32_t XferOptions)
+4148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+4150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+4152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+4153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+4155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+4157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+4159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+4160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+4163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+4164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+4166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+4167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+4169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* and then toggle the HAL slave TX state to RX state */
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+4171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable associated Interrupts */
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+4174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+4176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+4177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Abort DMA Xfer if any */
+4178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->hdmatx != NULL)
+4179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+4180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+4181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Set the I2C DMA Abort callback :
+4183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+4184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+4185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Abort DMA TX */
+4187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+4188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+4189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Call Directly XferAbortCallback function in case of error */
+4190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+4191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ARM GAS  /tmp/ccbUHtu7.s 			page 75
+
+
+4192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+4193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+4194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+4196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+4198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+4199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+4200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Abort DMA Xfer if any */
+4202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->hdmarx != NULL)
+4203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+4204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Set the I2C DMA Abort callback :
+4205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+4206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+4207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Abort DMA RX */
+4209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+4210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+4211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Call Directly XferAbortCallback function in case of error */
+4212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+4213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+4214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+4215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+4216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+4218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Nothing to do */
+4220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+4223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+4224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+4225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+4227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+4228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Prepare transfer parameters */
+4230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+4231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+4232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+4233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+4234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+4235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->hdmarx != NULL)
+4237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the I2C DMA transfer complete callback */
+4239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+4240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the DMA error callback */
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+4243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the unused DMA callbacks to NULL */
+4245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferHalfCpltCallback = NULL;
+4246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+4247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable the DMA channel */
+ARM GAS  /tmp/ccbUHtu7.s 			page 76
+
+
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
+4250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        (uint32_t)pData, hi2c->XferSize);
+4251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+4253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C state */
+4255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+4256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+4257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C error code */
+4259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+4260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+4262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+4263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+4265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (dmaxferstatus == HAL_OK)
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update XferCount value */
+4270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount -= hi2c->XferSize;
+4271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Reset XferSize */
+4273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = 0;
+4274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+4276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C state */
+4278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+4279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+4280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update I2C error code */
+4282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+4283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+4285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+4286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+4288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+4291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Clear ADDR flag after prepare the transfer parameters */
+4293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* This action will generate an acknowledge to the Master */
+4294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+4295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+4298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+4299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable DMA Request */
+4301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+4302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+4304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     to avoid the risk of I2C interrupt handle execution before current
+4305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     process unlock */
+ARM GAS  /tmp/ccbUHtu7.s 			page 77
+
+
+4306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* REnable ADDR interrupt */
+4307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+4308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+4310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+4312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+4314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Enable the Address listen mode with Interrupt.
+4319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+4322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+4326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_LISTEN;
+4328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR = I2C_Slave_ISR_IT;
+4329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable the Address Match interrupt */
+4331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+4332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+4334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+4336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+4338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Disable the Address listen mode with Interrupt.
+4343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C
+4345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+4346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+4348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+4350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmp;
+4351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable Address listen mode only if a transfer is not ongoing */
+4353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_LISTEN)
+4354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+4356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+4357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+4358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode = HAL_I2C_MODE_NONE;
+4359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR = NULL;
+4360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable the Address Match interrupt */
+4362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+ARM GAS  /tmp/ccbUHtu7.s 			page 78
+
+
+4363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+4365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+4367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_BUSY;
+4369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
+4374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+4377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+4378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+4379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+4381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+4383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Locked */
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+4386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable Interrupts and Store Previous state */
+4388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+4389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+4391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+4392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+4394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+4396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+4397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+4399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Do nothing */
+4401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set State at HAL_I2C_STATE_ABORT */
+4404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_ABORT;
+4405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+4407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfe
+4408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+4409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+4411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+4412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+4414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+4415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               process unlock */
+4416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+4417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_OK;
+4419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccbUHtu7.s 			page 79
+
+
+4420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+4421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wrong usage of abort function */
+4423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* This function should be used only in case of abort monitored by master device */
+4424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+4425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @}
+4430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+4433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @{
+4434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  This function handles I2C event interrupt request.
+4438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+4441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+4443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Get current IT Flags and IT sources value */
+4445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+4446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+4447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* I2C events treatment -------------------------------------*/
+4449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->XferISR != NULL)
+4450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR(hi2c, itflags, itsources);
+4452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  This function handles I2C error interrupt request.
+4457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+4460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+4462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+4464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+4465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmperror;
+4466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* I2C Bus error interrupt occurred ------------------------------------*/
+4468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
+4469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+4470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+4472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear BERR flag */
+4474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+4475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 80
+
+
+4477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+4478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
+4479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+4480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+4482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear OVR flag */
+4484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+4485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+4488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
+4489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+4490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+4492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear ARLO flag */
+4494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+4495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Store current volatile hi2c->ErrorCode, misra rule */
+4498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   tmperror = hi2c->ErrorCode;
+4499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Call the Error Callback in case of Error detected */
+4501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_
+4502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_ITError(hi2c, tmperror);
+4504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Master Tx Transfer completed callback.
+4509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+4512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+4514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(hi2c);
+4517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+4520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****    */
+4521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Master Rx Transfer completed callback.
+4525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+4530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(hi2c);
+4533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 81
+
+
+4534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+4536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****    */
+4537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /** @brief  Slave Tx Transfer completed callback.
+4540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+4543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+4545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(hi2c);
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+4551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****    */
+4552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Slave Rx Transfer completed callback.
+4556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+4559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+4561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(hi2c);
+4564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+4567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****    */
+4568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Slave Address Match callback.
+4572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFE
+4575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  AddrMatchCode Address Match Code
+4576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+4577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrM
+4579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(hi2c);
+4582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(TransferDirection);
+4583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(AddrMatchCode);
+4584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             the HAL_I2C_AddrCallback() could be implemented in the user file
+4587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****    */
+4588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ARM GAS  /tmp/ccbUHtu7.s 			page 82
+
+
+4591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Listen Complete callback.
+4592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+4595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+4597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(hi2c);
+4600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+4603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****    */
+4604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Memory Tx Transfer completed callback.
+4608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+4611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+4613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(hi2c);
+4616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+4619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****    */
+4620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Memory Rx Transfer completed callback.
+4624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+4627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+4629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(hi2c);
+4632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+4635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****    */
+4636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  I2C error callback.
+4640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+4643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+4645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(hi2c);
+ARM GAS  /tmp/ccbUHtu7.s 			page 83
+
+
+4648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             the HAL_I2C_ErrorCallback could be implemented in the user file
+4651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****    */
+4652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  I2C abort callback.
+4656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+4659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+4661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(hi2c);
+4664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             the HAL_I2C_AbortCpltCallback could be implemented in the user file
+4667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****    */
+4668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @}
+4672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+4675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *  @brief   Peripheral State, Mode and Error functions
+4676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *
+4677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** @verbatim
+4678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****  ===============================================================================
+4679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             ##### Peripheral State, Mode and Error functions #####
+4680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****  ===============================================================================
+4681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     [..]
+4682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     This subsection permit to get in run-time the status of the peripheral
+4683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     and the data flow.
+4684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** @endverbatim
+4686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @{
+4687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Return the I2C handle state.
+4691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL state
+4694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+4696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Return I2C handle state */
+4698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return hi2c->State;
+4699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Returns the I2C Master, Slave, Memory or no mode.
+4703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         the configuration information for I2C module
+ARM GAS  /tmp/ccbUHtu7.s 			page 84
+
+
+4705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL mode
+4706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+4708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return hi2c->Mode;
+4710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Return the I2C error code.
+4714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *              the configuration information for the specified I2C.
+4716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval I2C Error Code
+4717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+4719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return hi2c->ErrorCode;
+4721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @}
+4725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @}
+4729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /** @addtogroup I2C_Private_Functions
+4732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @{
+4733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+4737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+4740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ITSources Interrupt sources enabled.
+4741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+4742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+4744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                            uint32_t ITSources)
+4745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint16_t devaddress;
+4747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+4748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process Locked */
+4750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+4751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+4753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+4754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear NACK Flag */
+4756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+4757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set corresponding Error Code */
+4759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* No need to generate STOP, it is automatically done */
+4760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Error callback will be send during stop flag treatment */
+4761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ARM GAS  /tmp/ccbUHtu7.s 			page 85
+
+
+4762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Flush TX register */
+4764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Flush_TXDR(hi2c);
+4765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+4767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+4768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Remove RXNE flag on temporary variable as read done */
+4770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tmpITFlags &= ~I2C_FLAG_RXNE;
+4771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Read data from RXDR */
+4773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+4774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Increment Buffer pointer */
+4776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr++;
+4777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize--;
+4779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount--;
+4780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+4782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+4783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Write data to TXDR */
+4785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+4786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Increment Buffer pointer */
+4788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr++;
+4789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize--;
+4791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount--;
+4792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+4794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+4795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+4797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+4799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->XferCount > MAX_NBYTE_SIZE)
+4801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+4802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->XferSize = MAX_NBYTE_SIZE;
+4803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START
+4804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+4805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+4806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+4807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->XferSize = hi2c->XferCount;
+4808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+4809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+4810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+4811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              hi2c->XferOptions, I2C_NO_STARTSTOP);
+4812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+4813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         else
+4814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+4815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+4816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+4817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+4818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ARM GAS  /tmp/ccbUHtu7.s 			page 86
+
+
+4819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+4821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call TxCpltCallback() if no stop mode is set */
+4823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+4824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+4825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Call I2C Master Sequential complete process */
+4826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_ITMasterSeqCplt(hi2c);
+4827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+4828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+4829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+4830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Wrong size Status regarding TCR flag event */
+4831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Call the corresponding callback to inform upper layer of End of Transfer */
+4832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+4833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+4834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+4837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+4838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount == 0U)
+4840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+4842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+4843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Generate a stop condition in case of no transfer option */
+4844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+4845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+4846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Generate Stop */
+4847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->Instance->CR2 |= I2C_CR2_STOP;
+4848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+4849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         else
+4850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+4851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Call I2C Master Sequential complete process */
+4852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_ITMasterSeqCplt(hi2c);
+4853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+4854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+4855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+4857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Wrong size Status regarding TC flag event */
+4859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+4860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+4861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+4864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Nothing to do */
+4866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+4869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+4870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call I2C Master complete process */
+4872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_ITMasterCplt(hi2c, tmpITFlags);
+4873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process Unlocked */
+ARM GAS  /tmp/ccbUHtu7.s 			page 87
+
+
+4876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+4877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return HAL_OK;
+4879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+4880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+4882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+4883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+4886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ITSources Interrupt sources enabled.
+4887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+4888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+4889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+4890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                           uint32_t ITSources)
+4891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+4892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+4893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+4894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process locked */
+4896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+4897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check if STOPF is set */
+4899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+4900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+4901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call I2C Slave complete process */
+4903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_ITSlaveCplt(hi2c, tmpITFlags);
+4904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+4907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+4908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Check that I2C transfer finished */
+4910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+4911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Mean XferCount == 0*/
+4912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* So clear Flag NACKF only */
+4913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount == 0U)
+4914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+4916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+4917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            Warning[Pa134]: left and right operands are identical */
+4918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+4919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Call I2C Listen complete process */
+4920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_ITListenCplt(hi2c, tmpITFlags);
+4921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+4922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)
+4923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+4924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Clear NACK Flag */
+4925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+4926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Flush TX register */
+4928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_Flush_TXDR(hi2c);
+4929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Last Byte is Transmitted */
+4931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Call I2C Slave Sequential complete process */
+4932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_ITSlaveSeqCplt(hi2c);
+ARM GAS  /tmp/ccbUHtu7.s 			page 88
+
+
+4933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+4934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+4935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+4936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Clear NACK Flag */
+4937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+4938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+4939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+4941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+4943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Clear NACK Flag */
+4944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+4945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set ErrorCode corresponding to a Non-Acknowledge */
+4947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+4948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+4950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+4951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Call the corresponding callback to inform upper layer of End of Transfer */
+4952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_ITError(hi2c, hi2c->ErrorCode);
+4953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+4954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+4957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+4958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > 0U)
+4960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Read data from RXDR */
+4962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+4963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Increment Buffer pointer */
+4965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+4966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+4968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+4969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((hi2c->XferCount == 0U) && \
+4972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (tmpoptions != I2C_NO_OPTION_FRAME))
+4973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call I2C Slave Sequential complete process */
+4975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_ITSlaveSeqCplt(hi2c);
+4976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+4977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
+4979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+4980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_ITAddrCplt(hi2c, tmpITFlags);
+4982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+4983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+4984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+4985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+4986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Write data to TXDR only if XferCount not reach "0" */
+4987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* A TXIS flag can be set, during STOP treatment      */
+4988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Check if all Data have already been sent */
+4989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+ARM GAS  /tmp/ccbUHtu7.s 			page 89
+
+
+4990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > 0U)
+4991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+4992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Write data to TXDR */
+4993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+4994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Increment Buffer pointer */
+4996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+4997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+4998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+4999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+5000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+5002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+5004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Last Byte is Transmitted */
+5006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Call I2C Slave Sequential complete process */
+5007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_ITSlaveSeqCplt(hi2c);
+5008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Nothing to do */
+5014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process Unlocked */
+5017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+5018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return HAL_OK;
+5020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+5021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+5023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+5024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+5025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+5026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+5027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ITSources Interrupt sources enabled.
+5028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+5029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+5030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+5031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                             uint32_t ITSources)
+5032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+5033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint16_t devaddress;
+5034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+5035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process Locked */
+5037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+5038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+5040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+5041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear NACK Flag */
+5043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set corresponding Error Code */
+5046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ARM GAS  /tmp/ccbUHtu7.s 			page 90
+
+
+5047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* No need to generate STOP, it is automatically done */
+5049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* But enable STOP interrupt, to treat it */
+5050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Error callback will be send during stop flag treatment */
+5051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+5052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Flush TX register */
+5054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Flush_TXDR(hi2c);
+5055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+5057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+5058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable TC interrupt */
+5060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+5061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount != 0U)
+5063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Recover Slave address */
+5065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+5066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Prepare the new XferSize to transfer */
+5068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->XferCount > MAX_NBYTE_SIZE)
+5069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->XferSize = MAX_NBYTE_SIZE;
+5071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         xfermode = I2C_RELOAD_MODE;
+5072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+5074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->XferSize = hi2c->XferCount;
+5076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+5077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+5078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           xfermode = hi2c->XferOptions;
+5079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+5080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         else
+5081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+5082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           xfermode = I2C_AUTOEND_MODE;
+5083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+5084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the new XferSize in Nbytes register */
+5087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+5088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Update XferCount value */
+5090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount -= hi2c->XferSize;
+5091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable DMA Request */
+5093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+5094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+5096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+5098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+5100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+5103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccbUHtu7.s 			page 91
+
+
+5104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call TxCpltCallback() if no stop mode is set */
+5105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+5106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Call I2C Master Sequential complete process */
+5108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_ITMasterSeqCplt(hi2c);
+5109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+5111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Wrong size Status regarding TCR flag event */
+5113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Call the corresponding callback to inform upper layer of End of Transfer */
+5114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+5115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+5119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+5120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount == 0U)
+5122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+5124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Generate a stop condition in case of no transfer option */
+5126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+5127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+5128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Generate Stop */
+5129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->Instance->CR2 |= I2C_CR2_STOP;
+5130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+5131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         else
+5132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+5133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Call I2C Master Sequential complete process */
+5134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_ITMasterSeqCplt(hi2c);
+5135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+5136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+5139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Wrong size Status regarding TC flag event */
+5141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+5142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+5143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+5146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+5147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call I2C Master complete process */
+5149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_ITMasterCplt(hi2c, ITFlags);
+5150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Nothing to do */
+5154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process Unlocked */
+5157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+5158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return HAL_OK;
+5160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ARM GAS  /tmp/ccbUHtu7.s 			page 92
+
+
+5161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+5163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+5164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+5165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+5166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+5167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ITSources Interrupt sources enabled.
+5168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+5169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+5170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+5171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                            uint32_t ITSources)
+5172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+5173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+5174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t treatdmanack = 0U;
+5175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate;
+5176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process locked */
+5178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+5179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check if STOPF is set */
+5181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+5182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+5183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call I2C Slave complete process */
+5185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_ITSlaveCplt(hi2c, ITFlags);
+5186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+5189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+5190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Check that I2C transfer finished */
+5192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+5193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Mean XferCount == 0 */
+5194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* So clear Flag NACKF only */
+5195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+5196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+5197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Split check of hdmarx, for MISRA compliance */
+5199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->hdmarx != NULL)
+5200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+5202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+5203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
+5204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+5205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             treatdmanack = 1U;
+5206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+5207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+5208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Split check of hdmatx, for MISRA compliance  */
+5211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (hi2c->hdmatx != NULL)
+5212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+5214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+5215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
+5216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+5217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             treatdmanack = 1U;
+ARM GAS  /tmp/ccbUHtu7.s 			page 93
+
+
+5218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+5219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+5220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (treatdmanack == 1U)
+5223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+5225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+5226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****              Warning[Pa134]: left and right operands are identical */
+5227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+5228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Call I2C Listen complete process */
+5229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_ITListenCplt(hi2c, ITFlags);
+5230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+5231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAM
+5232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+5233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Clear NACK Flag */
+5234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Flush TX register */
+5237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_Flush_TXDR(hi2c);
+5238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Last Byte is Transmitted */
+5240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Call I2C Slave Sequential complete process */
+5241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_ITSlaveSeqCplt(hi2c);
+5242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+5243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         else
+5244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+5245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Clear NACK Flag */
+5246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+5248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+5250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+5252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Clear NACK Flag */
+5253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Set ErrorCode corresponding to a Non-Acknowledge */
+5256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+5257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+5259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         tmpstate = hi2c->State;
+5260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+5262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+5263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+5264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+5265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+5266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+5267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN
+5268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+5269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+5270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+5271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           else
+5272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+5273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Do nothing */
+5274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ARM GAS  /tmp/ccbUHtu7.s 			page 94
+
+
+5275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Call the corresponding callback to inform upper layer of End of Transfer */
+5277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_ITError(hi2c, hi2c->ErrorCode);
+5278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+5279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+5282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Only Clear NACK Flag, no DMA treatment is pending */
+5284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
+5288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+5289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_ITAddrCplt(hi2c, ITFlags);
+5291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Nothing to do */
+5295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process Unlocked */
+5298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+5299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return HAL_OK;
+5301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+5302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+5304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Master sends target device address followed by internal memory address for write reques
+5305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+5306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+5307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+5308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+5309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+5310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+5311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+5312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+5313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+5314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+5315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+5316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                 uint16_t MemAddress, uint16_t MemAddSize, uint32_t 
+5317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                 uint32_t Tickstart)
+5318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+5319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI
+5320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Wait until TXIS flag is set */
+5322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+5323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+5325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* If Memory address size is 8Bit */
+5328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+5329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Memory Address */
+5331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ARM GAS  /tmp/ccbUHtu7.s 			page 95
+
+
+5332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* If Memory address size is 16Bit */
+5334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send MSB of Memory Address */
+5337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+5338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until TXIS flag is set */
+5340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+5341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+5343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send LSB of Memory Address */
+5346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+5347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Wait until TCR flag is set */
+5350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+5351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+5353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return HAL_OK;
+5356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+5357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+5359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Master sends target device address followed by internal memory address for read request
+5360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+5361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+5362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+5363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+5364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+5365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+5366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+5367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+5368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+5369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+5370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+5371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t T
+5372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                uint32_t Tickstart)
+5373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+5374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR
+5375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Wait until TXIS flag is set */
+5377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+5378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+5380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* If Memory address size is 8Bit */
+5383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+5384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send Memory Address */
+5386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+5387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* If Memory address size is 16Bit */
+ARM GAS  /tmp/ccbUHtu7.s 			page 96
+
+
+5389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send MSB of Memory Address */
+5392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+5393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until TXIS flag is set */
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+5396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+5398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Send LSB of Memory Address */
+5401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+5402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Wait until TC flag is set */
+5405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+5406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     return HAL_ERROR;
+5408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return HAL_OK;
+5411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+5412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+5414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  I2C Address complete process callback.
+5415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+5416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+5417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+5418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+5419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+5420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+5421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint8_t transferdirection;
+5422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint16_t slaveaddrcode;
+5423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint16_t ownadd1code;
+5424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint16_t ownadd2code;
+5425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+5427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(ITFlags);
+5428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* In case of Listen state, need to inform upper layer of address match code event */
+5430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+5431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     transferdirection = I2C_GET_DIR(hi2c);
+5433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+5434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+5435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+5436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* If 10bits addressing mode is selected */
+5438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+5439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
+5441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         slaveaddrcode = ownadd1code;
+5443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->AddrEventCount++;
+5444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->AddrEventCount == 2U)
+5445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ARM GAS  /tmp/ccbUHtu7.s 			page 97
+
+
+5446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Reset Address Event counter */
+5447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->AddrEventCount = 0U;
+5448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Clear ADDR flag */
+5450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+5451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Process Unlocked */
+5453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           __HAL_UNLOCK(hi2c);
+5454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Call Slave Addr callback */
+5456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+5458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+5460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+5462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+5464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+5465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         slaveaddrcode = ownadd2code;
+5466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Disable ADDR Interrupts */
+5468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+5469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+5471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+5472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Call Slave Addr callback */
+5474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+5476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+5478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+5480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* else 7 bits addressing mode is selected */
+5482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+5483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable ADDR Interrupts */
+5485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+5486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+5488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+5489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call Slave Addr callback */
+5491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+5493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+5495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Else clear address flag only */
+5499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear ADDR flag */
+5502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ARM GAS  /tmp/ccbUHtu7.s 			page 98
+
+
+5503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+5505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+5506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+5508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+5510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  I2C Master sequential complete process.
+5511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+5512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+5513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+5514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
+5515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+5516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Reset I2C handle mode */
+5517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+5518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* No Generate Stop, to permit restart mode */
+5520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+5521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+5522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State         = HAL_I2C_STATE_READY;
+5524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+5525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+5526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable Interrupts */
+5528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+5529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+5531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+5532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+5534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->MasterTxCpltCallback(hi2c);
+5536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     HAL_I2C_MasterTxCpltCallback(hi2c);
+5538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+5541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State         = HAL_I2C_STATE_READY;
+5544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+5545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+5546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable Interrupts */
+5548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+5549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+5551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+5552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+5554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->MasterRxCpltCallback(hi2c);
+5556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     HAL_I2C_MasterRxCpltCallback(hi2c);
+5558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccbUHtu7.s 			page 99
+
+
+5560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+5561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+5563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  I2C Slave sequential complete process.
+5564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+5565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+5566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+5567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+5569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+5570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Reset I2C handle mode */
+5572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+5573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* If a DMA is ongoing, Update handle size context */
+5575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+5576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable DMA Request */
+5578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+5579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+5581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable DMA Request */
+5583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+5584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Do nothing */
+5588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+5591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+5593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State         = HAL_I2C_STATE_LISTEN;
+5594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+5595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable Interrupts */
+5597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+5598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+5600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+5601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+5603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->SlaveTxCpltCallback(hi2c);
+5605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     HAL_I2C_SlaveTxCpltCallback(hi2c);
+5607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+5611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+5613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State         = HAL_I2C_STATE_LISTEN;
+5614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+5615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable Interrupts */
+ARM GAS  /tmp/ccbUHtu7.s 			page 100
+
+
+5617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+5618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+5620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+5621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+5623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->SlaveRxCpltCallback(hi2c);
+5625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     HAL_I2C_SlaveRxCpltCallback(hi2c);
+5627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Nothing to do */
+5632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+5634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+5636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  I2C Master complete process.
+5637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+5638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+5639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+5640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+5641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+5642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+5643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmperror;
+5644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+5645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __IO uint32_t tmpreg;
+5646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Clear STOP Flag */
+5648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+5649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable Interrupts and Store Previous state */
+5651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+5652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+5654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+5655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+5657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+5659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+5660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Do nothing */
+5664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Clear Configuration Register 2 */
+5667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_RESET_CR2(hi2c);
+5668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Reset handle parameters */
+5670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferISR       = NULL;
+5671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+5672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
+ARM GAS  /tmp/ccbUHtu7.s 			page 101
+
+
+5674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear NACK Flag */
+5676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set acknowledge error code */
+5679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+5680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Fetch Last receive data if any */
+5683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+5684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Read data from RXDR */
+5686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tmpreg = (uint8_t)hi2c->Instance->RXDR;
+5687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     UNUSED(tmpreg);
+5688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Flush TX register */
+5691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_Flush_TXDR(hi2c);
+5692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Store current volatile hi2c->ErrorCode, misra rule */
+5694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   tmperror = hi2c->ErrorCode;
+5695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Call the corresponding callback to inform upper layer of End of Transfer */
+5697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
+5698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+5700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_ITError(hi2c, hi2c->ErrorCode);
+5701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+5703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+5704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+5706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+5707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->Mode == HAL_I2C_MODE_MEM)
+5709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode = HAL_I2C_MODE_NONE;
+5711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+5713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+5714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+5716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->MemTxCpltCallback(hi2c);
+5718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       HAL_I2C_MemTxCpltCallback(hi2c);
+5720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+5723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode = HAL_I2C_MODE_NONE;
+5725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+5727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+5728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+5730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ARM GAS  /tmp/ccbUHtu7.s 			page 102
+
+
+5731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->MasterTxCpltCallback(hi2c);
+5732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       HAL_I2C_MasterTxCpltCallback(hi2c);
+5734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+5738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+5739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+5741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+5742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->Mode == HAL_I2C_MODE_MEM)
+5744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode = HAL_I2C_MODE_NONE;
+5746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+5748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+5749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+5751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->MemRxCpltCallback(hi2c);
+5753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       HAL_I2C_MemRxCpltCallback(hi2c);
+5755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+5758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode = HAL_I2C_MODE_NONE;
+5760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+5762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+5763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+5765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->MasterRxCpltCallback(hi2c);
+5767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       HAL_I2C_MasterRxCpltCallback(hi2c);
+5769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Nothing to do */
+5775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+5777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+5779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  I2C Slave complete process.
+5780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+5781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+5782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+5783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+5784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+5785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+5786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+5787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ARM GAS  /tmp/ccbUHtu7.s 			page 103
+
+
+5788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+5789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Clear STOP Flag */
+5791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+5792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable Interrupts and Store Previous state */
+5794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+5795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+5797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+5798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+5800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+5802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+5803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Do nothing */
+5807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable Address Acknowledge */
+5810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Instance->CR2 |= I2C_CR2_NACK;
+5811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Clear Configuration Register 2 */
+5813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_RESET_CR2(hi2c);
+5814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Flush TX register */
+5816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_Flush_TXDR(hi2c);
+5817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* If a DMA is ongoing, Update handle size context */
+5819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+5820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable DMA Request */
+5822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+5823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->hdmatx != NULL)
+5825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
+5827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+5830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable DMA Request */
+5832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+5833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->hdmarx != NULL)
+5835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
+5837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Do nothing */
+5842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Store Last receive data if any */
+ARM GAS  /tmp/ccbUHtu7.s 			page 104
+
+
+5845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+5846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Remove RXNE flag on temporary variable as read done */
+5848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tmpITFlags &= ~I2C_FLAG_RXNE;
+5849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Read data from RXDR */
+5851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+5852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Increment Buffer pointer */
+5854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr++;
+5855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((hi2c->XferSize > 0U))
+5857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+5859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+5860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* All data are not transferred, so set error code accordingly */
+5864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->XferCount != 0U)
+5865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set ErrorCode corresponding to a Non-Acknowledge */
+5867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+5868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+5871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferISR = NULL;
+5872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+5874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+5876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_ITError(hi2c, hi2c->ErrorCode);
+5877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+5879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_LISTEN)
+5880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call I2C Listen complete process */
+5882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_ITListenCplt(hi2c, tmpITFlags);
+5883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+5886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
+5888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_ITSlaveSeqCplt(hi2c);
+5889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+5891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+5892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+5893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+5895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+5896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+5898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ListenCpltCallback(hi2c);
+5900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     HAL_I2C_ListenCpltCallback(hi2c);
+ARM GAS  /tmp/ccbUHtu7.s 			page 105
+
+
+5902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Call the corresponding callback to inform upper layer of End of Transfer */
+5905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+5906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+5908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+5909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+5911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+5912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+5914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->SlaveRxCpltCallback(hi2c);
+5916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     HAL_I2C_SlaveRxCpltCallback(hi2c);
+5918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+5921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+5923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+5924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+5926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+5927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+5929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->SlaveTxCpltCallback(hi2c);
+5931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     HAL_I2C_SlaveTxCpltCallback(hi2c);
+5933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+5936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+5938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  I2C Listen complete process.
+5939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+5940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+5941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+5942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+5943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+5944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+5945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Reset handle parameters */
+5946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+5947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+5948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_READY;
+5949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+5950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferISR = NULL;
+5951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Store Last receive data if any */
+5953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
+5954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+5955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Read data from RXDR */
+5956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+5957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Increment Buffer pointer */
+ARM GAS  /tmp/ccbUHtu7.s 			page 106
+
+
+5959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr++;
+5960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((hi2c->XferSize > 0U))
+5962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+5963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+5964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+5965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set ErrorCode corresponding to a Non-Acknowledge */
+5967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+5968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+5969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+5970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable all Interrupts*/
+5972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+5973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Clear NACK Flag */
+5975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Process Unlocked */
+5978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+5979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+5981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->ListenCpltCallback(hi2c);
+5983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+5984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_ListenCpltCallback(hi2c);
+5985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+5987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+5989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  I2C interrupts error process.
+5990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+5991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  ErrorCode Error code to handle.
+5992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+5993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+5994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+5995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+5996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+5997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmppreviousstate;
+5998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+5999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Reset handle parameters */
+6000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode          = HAL_I2C_MODE_NONE;
+6001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+6002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferCount     = 0U;
+6003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Set new error code */
+6005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->ErrorCode |= ErrorCode;
+6006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable Interrupts */
+6008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
+6009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+6010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+6011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable all interrupts, except interrupts related to LISTEN state */
+6013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+6014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* keep HAL_I2C_STATE_LISTEN if set */
+ARM GAS  /tmp/ccbUHtu7.s 			page 107
+
+
+6016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State         = HAL_I2C_STATE_LISTEN;
+6017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR       = I2C_Slave_ISR_IT;
+6018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+6020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable all interrupts */
+6022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+6023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* If state is an abort treatment on going, don't change state */
+6025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* This change will be do later */
+6026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->State != HAL_I2C_STATE_ABORT)
+6027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set HAL_I2C_STATE_READY */
+6029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State         = HAL_I2C_STATE_READY;
+6030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+6032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Abort DMA TX transfer if any */
+6035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   tmppreviousstate = hi2c->PreviousState;
+6036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
+6037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+6038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+6040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+6042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+6045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the I2C DMA Abort callback :
+6047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+6048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+6049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+6051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+6052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Abort DMA TX */
+6054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+6055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+6056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Call Directly XferAbortCallback function in case of error */
+6057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+6058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+6059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+6061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TreatErrorCallback(hi2c);
+6063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Abort DMA RX transfer if any */
+6066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
+6067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+6068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+6070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+6072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ARM GAS  /tmp/ccbUHtu7.s 			page 108
+
+
+6073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+6075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Set the I2C DMA Abort callback :
+6077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+6078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+6079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+6081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+6082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Abort DMA RX */
+6084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+6085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+6086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+6087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+6088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+6089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+6091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TreatErrorCallback(hi2c);
+6093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+6096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_TreatErrorCallback(hi2c);
+6098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  I2C Error callback treatment.
+6103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+6104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+6105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+6107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+6108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_ABORT)
+6109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+6111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+6112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+6114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->AbortCpltCallback(hi2c);
+6119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+6120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     HAL_I2C_AbortCpltCallback(hi2c);
+6121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+6124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+6126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+6128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 109
+
+
+6130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCallback(hi2c);
+6133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #else
+6134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     HAL_I2C_ErrorCallback(hi2c);
+6135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  I2C Tx data register flush process.
+6141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+6142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+6143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+6145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+  29              		.loc 1 6145 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+6146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* If a pending TXIS flag is set */
+6147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Write a dummy data in TXDR to clear it */
+6148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+  34              		.loc 1 6148 3 view .LVU1
+  35              		.loc 1 6148 7 is_stmt 0 view .LVU2
+  36 0000 0368     		ldr	r3, [r0]
+  37 0002 9A69     		ldr	r2, [r3, #24]
+  38              		.loc 1 6148 6 view .LVU3
+  39 0004 12F0020F 		tst	r2, #2
+  40 0008 01D0     		beq	.L2
+6149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->TXDR = 0x00U;
+  41              		.loc 1 6150 5 is_stmt 1 view .LVU4
+  42              		.loc 1 6150 26 is_stmt 0 view .LVU5
+  43 000a 0022     		movs	r2, #0
+  44 000c 9A62     		str	r2, [r3, #40]
+  45              	.L2:
+6151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Flush TX register if not empty */
+6154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  46              		.loc 1 6154 3 is_stmt 1 view .LVU6
+  47              		.loc 1 6154 7 is_stmt 0 view .LVU7
+  48 000e 0368     		ldr	r3, [r0]
+  49 0010 9A69     		ldr	r2, [r3, #24]
+  50              		.loc 1 6154 6 view .LVU8
+  51 0012 12F0010F 		tst	r2, #1
+  52 0016 03D1     		bne	.L1
+6155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+  53              		.loc 1 6156 5 is_stmt 1 view .LVU9
+  54 0018 9A69     		ldr	r2, [r3, #24]
+  55 001a 42F00102 		orr	r2, r2, #1
+  56 001e 9A61     		str	r2, [r3, #24]
+  57              	.L1:
+6157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccbUHtu7.s 			page 110
+
+
+6158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+  58              		.loc 1 6158 1 is_stmt 0 view .LVU10
+  59 0020 7047     		bx	lr
+  60              		.cfi_endproc
+  61              	.LFE392:
+  63              		.section	.text.I2C_TransferConfig,"ax",%progbits
+  64              		.align	1
+  65              		.syntax unified
+  66              		.thumb
+  67              		.thumb_func
+  69              	I2C_TransferConfig:
+  70              	.LVL1:
+  71              	.LFB404:
+6159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  DMA I2C master transmit process complete callback.
+6162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hdma DMA handle
+6163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+6164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+6166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+6167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+6168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+6169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable DMA Request */
+6171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+6172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* If last transfer, enable STOP interrupt */
+6174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->XferCount == 0U)
+6175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable STOP interrupt */
+6177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+6178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* else prepare a new DMA transfer and enable TCReload interrupt */
+6180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+6181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Update Buffer pointer */
+6183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr += hi2c->XferSize;
+6184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set the XferSize to transfer */
+6186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+6187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+6189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+6191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+6193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable the DMA channel */
+6196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+6197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+6198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+6200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+6201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+ARM GAS  /tmp/ccbUHtu7.s 			page 111
+
+
+6203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable TC interrupts */
+6205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+6206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  DMA I2C slave transmit process complete callback.
+6212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hdma DMA handle
+6213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+6214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+6216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+6217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+6218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+6219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+6220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+6222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable DMA Request */
+6224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+6225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Last Byte is Transmitted */
+6227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call I2C Slave Sequential complete process */
+6228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_ITSlaveSeqCplt(hi2c);
+6229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+6231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* No specific action, Master fully manage the generation of STOP condition */
+6233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Mean that this generation can arrive at any time, at the end or during DMA process */
+6234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* So STOP condition should be manage through Interrupt treatment */
+6235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief DMA I2C master receive process complete callback.
+6240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hdma DMA handle
+6241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+6242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+6244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+6245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+6246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+6247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable DMA Request */
+6249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+6250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* If last transfer, enable STOP interrupt */
+6252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->XferCount == 0U)
+6253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable STOP interrupt */
+6255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+6256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* else prepare a new DMA transfer and enable TCReload interrupt */
+6258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+6259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 112
+
+
+6260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Update Buffer pointer */
+6261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->pBuffPtr += hi2c->XferSize;
+6262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Set the XferSize to transfer */
+6264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+6265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+6267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+6269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+6271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable the DMA channel */
+6274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
+6275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+6276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+6278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+6279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     else
+6281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable TC interrupts */
+6283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+6284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  DMA I2C slave receive process complete callback.
+6290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hdma DMA handle
+6291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+6292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+6294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+6295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+6296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+6297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+6298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
+6300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (tmpoptions != I2C_NO_OPTION_FRAME))
+6301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable DMA Request */
+6303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+6304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Call I2C Slave Sequential complete process */
+6306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_ITSlaveSeqCplt(hi2c);
+6307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+6309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* No specific action, Master fully manage the generation of STOP condition */
+6311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Mean that this generation can arrive at any time, at the end or during DMA process */
+6312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* So STOP condition should be manage through Interrupt treatment */
+6313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ARM GAS  /tmp/ccbUHtu7.s 			page 113
+
+
+6317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  DMA I2C communication error callback.
+6318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param hdma DMA handle
+6319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+6320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+6322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+6323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+6324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+6325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable Acknowledge */
+6327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Instance->CR2 |= I2C_CR2_NACK;
+6328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Call the corresponding callback to inform upper layer of End of Transfer */
+6330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+6331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief DMA I2C communication abort callback
+6335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *        (To be called at end of DMA Abort procedure).
+6336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param hdma DMA handle.
+6337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+6338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+6340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+6341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+6342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+6343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Reset AbortCpltCallback */
+6345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->hdmatx != NULL)
+6346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->hdmatx->XferAbortCallback = NULL;
+6348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->hdmarx != NULL)
+6350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->hdmarx->XferAbortCallback = NULL;
+6352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_TreatErrorCallback(hi2c);
+6355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  This function handles I2C Communication Timeout. It waits
+6359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                until a flag is no longer in the specified status.
+6360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+6361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+6362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Flag Specifies the I2C flag to check.
+6363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Status The actual Flag status (SET or RESET).
+6364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+6365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+6366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+6367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta
+6369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                     uint32_t Timeout, uint32_t Tickstart)
+6370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+6371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+6372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Check for the Timeout */
+ARM GAS  /tmp/ccbUHtu7.s 			page 114
+
+
+6374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (Timeout != HAL_MAX_DELAY)
+6375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+6377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+6378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+6379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+6380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+6381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+6383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+6384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+6385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+6386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return HAL_OK;
+6389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
+6393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+6394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+6395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+6396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+6397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+6398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+6400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                         uint32_t Tickstart)
+6401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+6402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+6403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Check if an error is detected */
+6405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+6406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+6408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Check for the Timeout */
+6411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (Timeout != HAL_MAX_DELAY)
+6412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+6414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+6415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+6416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+6417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+6418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+6420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+6421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+6423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+6424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return HAL_OK;
+6427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+ARM GAS  /tmp/ccbUHtu7.s 			page 115
+
+
+6431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+6432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+6433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+6434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+6435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+6436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+6438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                         uint32_t Tickstart)
+6439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+6440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+6441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Check if an error is detected */
+6443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+6444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+6446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Check for the Timeout */
+6449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+6450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+6452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State = HAL_I2C_STATE_READY;
+6453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode = HAL_I2C_MODE_NONE;
+6454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+6456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+6457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+6459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return HAL_OK;
+6462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
+6466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+6467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+6468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+6469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+6470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+6471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+6473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                                         uint32_t Tickstart)
+6474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+6475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+6476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Check if an error is detected */
+6478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+6479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+6481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Check if a STOPF is detected */
+6484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+6485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Check if an RXNE is pending */
+6487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Store Last receive data if any */
+ARM GAS  /tmp/ccbUHtu7.s 			page 116
+
+
+6488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+6489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+6490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Return HAL_OK */
+6491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* The Reading of data from RXDR will be done in caller function */
+6492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_OK;
+6493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+6494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       else
+6495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+6496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+6497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+6498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+6499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+6500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+6501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         else
+6502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+6503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+6504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+6505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Clear STOP Flag */
+6507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+6508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Clear Configuration Register 2 */
+6510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_RESET_CR2(hi2c);
+6511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+6513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+6514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Process Unlocked */
+6516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+6517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+6519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+6520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Check for the Timeout */
+6523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+6524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+6526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State = HAL_I2C_STATE_READY;
+6527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Process Unlocked */
+6529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+6530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+6532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return HAL_OK;
+6535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  This function handles errors detection during an I2C Communication.
+6539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+6540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+6541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+6542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+6543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval HAL status
+6544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ARM GAS  /tmp/ccbUHtu7.s 			page 117
+
+
+6545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Ti
+6546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+6547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+6548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itflag   = hi2c->Instance->ISR;
+6549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t error_code = 0;
+6550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart = Tickstart;
+6551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmp1;
+6552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_ModeTypeDef tmp2;
+6553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
+6555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear NACKF Flag */
+6557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+6558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Wait until STOP Flag is set or timeout occurred */
+6560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* AutoEnd should be initiate after AF */
+6561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
+6562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Check for the Timeout */
+6564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       if (Timeout != HAL_MAX_DELAY)
+6565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+6566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+6567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+6568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
+6569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           tmp2 = hi2c->Mode;
+6570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* In case of I2C still busy, try to regenerate a STOP manually */
+6572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
+6573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               (tmp1 != I2C_CR2_STOP) && \
+6574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               (tmp2 != HAL_I2C_MODE_SLAVE))
+6575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+6576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Generate Stop */
+6577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             hi2c->Instance->CR2 |= I2C_CR2_STOP;
+6578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             
+6579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Update Tick with new reference */
+6580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             tickstart = HAL_GetTick();
+6581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+6582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           
+6583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+6584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+6585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             /* Check for the Timeout */
+6586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
+6587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             {
+6588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+6589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               hi2c->State = HAL_I2C_STATE_READY;
+6590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               hi2c->Mode = HAL_I2C_MODE_NONE;
+6591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               
+6592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               /* Process Unlocked */
+6593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               __HAL_UNLOCK(hi2c);
+6594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               
+6595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               status = HAL_ERROR;
+6596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             }
+6597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+6598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+6599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+6600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 118
+
+
+6602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* In case STOP Flag is detected, clear it */
+6603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (status == HAL_OK)
+6604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Clear STOP Flag */
+6606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+6607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     error_code |= HAL_I2C_ERROR_AF;
+6610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     status = HAL_ERROR;
+6612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Refresh Content of Status register */
+6615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   itflag = hi2c->Instance->ISR;
+6616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Then verify if an additional errors occurs */
+6618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check if a Bus error occurred */
+6619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
+6620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     error_code |= HAL_I2C_ERROR_BERR;
+6622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear BERR flag */
+6624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+6625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     status = HAL_ERROR;
+6627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check if an Over-Run/Under-Run error occurred */
+6630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
+6631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     error_code |= HAL_I2C_ERROR_OVR;
+6633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear OVR flag */
+6635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+6636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     status = HAL_ERROR;
+6638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check if an Arbitration Loss error occurred */
+6641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
+6642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     error_code |= HAL_I2C_ERROR_ARLO;
+6644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear ARLO flag */
+6646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+6647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     status = HAL_ERROR;
+6649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (status != HAL_OK)
+6652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Flush TX register */
+6654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_Flush_TXDR(hi2c);
+6655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Clear Configuration Register 2 */
+6657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     I2C_RESET_CR2(hi2c);
+6658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 119
+
+
+6659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode |= error_code;
+6660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+6661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode = HAL_I2C_MODE_NONE;
+6662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Process Unlocked */
+6664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return status;
+6668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+6669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag ar
+6672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+6673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  DevAddress Specifies the slave address to be programmed.
+6674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Size Specifies the number of bytes to be programmed.
+6675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *   This parameter must be a value between 0 and 255.
+6676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Mode New state of the I2C START condition generation.
+6677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *   This parameter can be one of the following values:
+6678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+6679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+6680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+6681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  Request New state of the I2C START condition generation.
+6682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *   This parameter can be one of the following values:
+6683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+6684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+6685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+6686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+6687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+6688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t
+6690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                uint32_t Request)
+6691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+  72              		.loc 1 6691 1 is_stmt 1 view -0
+  73              		.cfi_startproc
+  74              		@ args = 4, pretend = 0, frame = 0
+  75              		@ frame_needed = 0, uses_anonymous_args = 0
+  76              		@ link register save eliminated.
+  77              		.loc 1 6691 1 is_stmt 0 view .LVU12
+  78 0000 10B4     		push	{r4}
+  79              	.LCFI0:
+  80              		.cfi_def_cfa_offset 4
+  81              		.cfi_offset 4, -4
+  82 0002 019C     		ldr	r4, [sp, #4]
+6692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+6693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  83              		.loc 1 6693 3 is_stmt 1 view .LVU13
+6694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_TRANSFER_MODE(Mode));
+  84              		.loc 1 6694 3 view .LVU14
+6695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_TRANSFER_REQUEST(Request));
+  85              		.loc 1 6695 3 view .LVU15
+6696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+6698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+  86              		.loc 1 6698 3 view .LVU16
+  87              		.loc 1 6698 52 is_stmt 0 view .LVU17
+  88 0004 C1F30901 		ubfx	r1, r1, #0, #10
+ARM GAS  /tmp/ccbUHtu7.s 			page 120
+
+
+  89              	.LVL2:
+  90              		.loc 1 6698 68 view .LVU18
+  91 0008 41EA0241 		orr	r1, r1, r2, lsl #16
+6699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+  92              		.loc 1 6699 87 view .LVU19
+  93 000c 1943     		orrs	r1, r1, r3
+6698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+  94              		.loc 1 6698 19 view .LVU20
+  95 000e 2143     		orrs	r1, r1, r4
+6698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                             (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+  96              		.loc 1 6698 12 view .LVU21
+  97 0010 21F00041 		bic	r1, r1, #-2147483648
+  98              	.LVL3:
+6700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                               (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+6701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* update CR2 register */
+6703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   MODIFY_REG(hi2c->Instance->CR2, \
+  99              		.loc 1 6703 3 is_stmt 1 view .LVU22
+ 100 0014 0268     		ldr	r2, [r0]
+ 101              	.LVL4:
+ 102              		.loc 1 6703 3 is_stmt 0 view .LVU23
+ 103 0016 5368     		ldr	r3, [r2, #4]
+ 104              	.LVL5:
+ 105              		.loc 1 6703 3 view .LVU24
+ 106 0018 640D     		lsrs	r4, r4, #21
+ 107 001a 04F48064 		and	r4, r4, #1024
+ 108 001e 44F07F74 		orr	r4, r4, #66846720
+ 109 0022 44F45834 		orr	r4, r4, #221184
+ 110 0026 44F47F74 		orr	r4, r4, #1020
+ 111 002a 44F00304 		orr	r4, r4, #3
+ 112 002e 23EA0403 		bic	r3, r3, r4
+ 113 0032 0B43     		orrs	r3, r3, r1
+ 114 0034 5360     		str	r3, [r2, #4]
+6704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****              ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+6705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
+6706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                 I2C_CR2_START | I2C_CR2_STOP)), tmp);
+6707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 115              		.loc 1 6707 1 view .LVU25
+ 116 0036 5DF8044B 		ldr	r4, [sp], #4
+ 117              	.LCFI1:
+ 118              		.cfi_restore 4
+ 119              		.cfi_def_cfa_offset 0
+ 120              	.LVL6:
+ 121              		.loc 1 6707 1 view .LVU26
+ 122 003a 7047     		bx	lr
+ 123              		.cfi_endproc
+ 124              	.LFE404:
+ 126              		.section	.text.I2C_Enable_IRQ,"ax",%progbits
+ 127              		.align	1
+ 128              		.syntax unified
+ 129              		.thumb
+ 130              		.thumb_func
+ 132              	I2C_Enable_IRQ:
+ 133              	.LVL7:
+ 134              	.LFB405:
+6708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ARM GAS  /tmp/ccbUHtu7.s 			page 121
+
+
+6710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Manage the enabling of Interrupts.
+6711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+6712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+6713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+6714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+6715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+6717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+ 135              		.loc 1 6717 1 is_stmt 1 view -0
+ 136              		.cfi_startproc
+ 137              		@ args = 0, pretend = 0, frame = 0
+ 138              		@ frame_needed = 0, uses_anonymous_args = 0
+ 139              		@ link register save eliminated.
+6718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpisr = 0U;
+ 140              		.loc 1 6718 3 view .LVU28
+6719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+ 141              		.loc 1 6720 3 view .LVU29
+ 142              		.loc 1 6720 12 is_stmt 0 view .LVU30
+ 143 0000 436B     		ldr	r3, [r0, #52]
+ 144              		.loc 1 6720 6 view .LVU31
+ 145 0002 1A4A     		ldr	r2, .L20
+ 146 0004 9342     		cmp	r3, r2
+ 147 0006 15D0     		beq	.L7
+ 148              		.loc 1 6720 45 discriminator 1 view .LVU32
+ 149 0008 194A     		ldr	r2, .L20+4
+ 150 000a 9342     		cmp	r3, r2
+ 151 000c 12D0     		beq	.L7
+6721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (hi2c->XferISR == I2C_Slave_ISR_DMA))
+6722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+6724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR, STOP, NACK and ADDR interrupts */
+6726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+6727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (InterruptRequest == I2C_XFER_ERROR_IT)
+6730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR and NACK interrupts */
+6732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+6733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (InterruptRequest == I2C_XFER_CPLT_IT)
+6736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable STOP interrupts */
+6738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+6739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (InterruptRequest == I2C_XFER_RELOAD_IT)
+6742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable TC interrupts */
+6744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmpisr |= I2C_IT_TCI;
+6745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+6748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ARM GAS  /tmp/ccbUHtu7.s 			page 122
+
+
+ 152              		.loc 1 6749 5 is_stmt 1 view .LVU33
+ 153              		.loc 1 6749 8 is_stmt 0 view .LVU34
+ 154 000e 11F4004F 		tst	r1, #32768
+ 155 0012 28D1     		bne	.L17
+6718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 156              		.loc 1 6718 12 view .LVU35
+ 157 0014 0023     		movs	r3, #0
+ 158              	.L12:
+ 159              	.LVL8:
+6750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR, STOP, NACK, and ADDR interrupts */
+6752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ 160              		.loc 1 6755 5 is_stmt 1 view .LVU36
+ 161              		.loc 1 6755 8 is_stmt 0 view .LVU37
+ 162 0016 11F0010F 		tst	r1, #1
+ 163 001a 01D0     		beq	.L13
+6756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+6758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+ 164              		.loc 1 6758 7 is_stmt 1 view .LVU38
+ 165              		.loc 1 6758 14 is_stmt 0 view .LVU39
+ 166 001c 43F0F203 		orr	r3, r3, #242
+ 167              	.LVL9:
+ 168              	.L13:
+6759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ 169              		.loc 1 6761 5 is_stmt 1 view .LVU40
+ 170              		.loc 1 6761 8 is_stmt 0 view .LVU41
+ 171 0020 11F0020F 		tst	r1, #2
+ 172 0024 01D0     		beq	.L14
+6762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+6764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+ 173              		.loc 1 6764 7 is_stmt 1 view .LVU42
+ 174              		.loc 1 6764 14 is_stmt 0 view .LVU43
+ 175 0026 43F0F403 		orr	r3, r3, #244
+ 176              	.LVL10:
+ 177              	.L14:
+6765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (InterruptRequest == I2C_XFER_CPLT_IT)
+ 178              		.loc 1 6767 5 is_stmt 1 view .LVU44
+ 179              		.loc 1 6767 8 is_stmt 0 view .LVU45
+ 180 002a 2029     		cmp	r1, #32
+ 181 002c 0ED1     		bne	.L11
+6768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Enable STOP interrupts */
+6770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmpisr |= I2C_IT_STOPI;
+ 182              		.loc 1 6770 7 is_stmt 1 view .LVU46
+ 183              		.loc 1 6770 14 is_stmt 0 view .LVU47
+ 184 002e 43F02003 		orr	r3, r3, #32
+ 185              	.LVL11:
+ 186              		.loc 1 6770 14 view .LVU48
+ARM GAS  /tmp/ccbUHtu7.s 			page 123
+
+
+ 187 0032 0BE0     		b	.L11
+ 188              	.LVL12:
+ 189              	.L7:
+6723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 190              		.loc 1 6723 5 is_stmt 1 view .LVU49
+6723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 191              		.loc 1 6723 8 is_stmt 0 view .LVU50
+ 192 0034 11F4004F 		tst	r1, #32768
+ 193 0038 03D1     		bne	.L15
+6729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 194              		.loc 1 6729 5 is_stmt 1 view .LVU51
+6729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 195              		.loc 1 6729 8 is_stmt 0 view .LVU52
+ 196 003a 1029     		cmp	r1, #16
+ 197 003c 0BD0     		beq	.L16
+6718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 198              		.loc 1 6718 12 view .LVU53
+ 199 003e 0023     		movs	r3, #0
+ 200 0040 00E0     		b	.L9
+ 201              	.L15:
+6726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 202              		.loc 1 6726 14 view .LVU54
+ 203 0042 B823     		movs	r3, #184
+ 204              	.L9:
+ 205              	.LVL13:
+6735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 206              		.loc 1 6735 5 is_stmt 1 view .LVU55
+6735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 207              		.loc 1 6735 8 is_stmt 0 view .LVU56
+ 208 0044 2029     		cmp	r1, #32
+ 209 0046 08D0     		beq	.L18
+ 210              	.L10:
+6741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 211              		.loc 1 6741 5 is_stmt 1 view .LVU57
+6741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 212              		.loc 1 6741 8 is_stmt 0 view .LVU58
+ 213 0048 4029     		cmp	r1, #64
+ 214 004a 09D0     		beq	.L19
+ 215              	.L11:
+6771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Enable interrupts only at the end */
+6775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* to avoid the risk of I2C interrupt handle execution before */
+6776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* all interrupts requested done */
+6777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+ 216              		.loc 1 6777 3 is_stmt 1 view .LVU59
+ 217 004c 0168     		ldr	r1, [r0]
+ 218              	.LVL14:
+ 219              		.loc 1 6777 3 is_stmt 0 view .LVU60
+ 220 004e 0A68     		ldr	r2, [r1]
+ 221 0050 1343     		orrs	r3, r3, r2
+ 222              	.LVL15:
+ 223              		.loc 1 6777 3 view .LVU61
+ 224 0052 0B60     		str	r3, [r1]
+6778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 225              		.loc 1 6778 1 view .LVU62
+ARM GAS  /tmp/ccbUHtu7.s 			page 124
+
+
+ 226 0054 7047     		bx	lr
+ 227              	.LVL16:
+ 228              	.L16:
+6732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 229              		.loc 1 6732 14 view .LVU63
+ 230 0056 9023     		movs	r3, #144
+ 231 0058 F4E7     		b	.L9
+ 232              	.LVL17:
+ 233              	.L18:
+6738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 234              		.loc 1 6738 7 is_stmt 1 view .LVU64
+6738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 235              		.loc 1 6738 14 is_stmt 0 view .LVU65
+ 236 005a 43F06003 		orr	r3, r3, #96
+ 237              	.LVL18:
+6738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 238              		.loc 1 6738 14 view .LVU66
+ 239 005e F3E7     		b	.L10
+ 240              	.L19:
+6744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 241              		.loc 1 6744 7 is_stmt 1 view .LVU67
+6744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 242              		.loc 1 6744 14 is_stmt 0 view .LVU68
+ 243 0060 43F04003 		orr	r3, r3, #64
+ 244              	.LVL19:
+6744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 245              		.loc 1 6744 14 view .LVU69
+ 246 0064 F2E7     		b	.L11
+ 247              	.LVL20:
+ 248              	.L17:
+6752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 249              		.loc 1 6752 14 view .LVU70
+ 250 0066 B823     		movs	r3, #184
+ 251 0068 D5E7     		b	.L12
+ 252              	.L21:
+ 253 006a 00BF     		.align	2
+ 254              	.L20:
+ 255 006c 00000000 		.word	I2C_Master_ISR_DMA
+ 256 0070 00000000 		.word	I2C_Slave_ISR_DMA
+ 257              		.cfi_endproc
+ 258              	.LFE405:
+ 260              		.section	.text.I2C_Disable_IRQ,"ax",%progbits
+ 261              		.align	1
+ 262              		.syntax unified
+ 263              		.thumb
+ 264              		.thumb_func
+ 266              	I2C_Disable_IRQ:
+ 267              	.LVL21:
+ 268              	.LFB406:
+6779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Manage the disabling of Interrupts.
+6782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+6783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+6784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+6785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+6786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+ARM GAS  /tmp/ccbUHtu7.s 			page 125
+
+
+6787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+6788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+ 269              		.loc 1 6788 1 is_stmt 1 view -0
+ 270              		.cfi_startproc
+ 271              		@ args = 0, pretend = 0, frame = 0
+ 272              		@ frame_needed = 0, uses_anonymous_args = 0
+ 273              		@ link register save eliminated.
+6789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpisr = 0U;
+ 274              		.loc 1 6789 3 view .LVU72
+6790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ 275              		.loc 1 6791 3 view .LVU73
+ 276              		.loc 1 6791 6 is_stmt 0 view .LVU74
+ 277 0000 11F0010F 		tst	r1, #1
+ 278 0004 09D0     		beq	.L29
+6792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable TC and TXI interrupts */
+6794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+ 279              		.loc 1 6794 5 is_stmt 1 view .LVU75
+ 280              	.LVL22:
+6795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+ 281              		.loc 1 6796 5 view .LVU76
+ 282              		.loc 1 6796 24 is_stmt 0 view .LVU77
+ 283 0006 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 284              		.loc 1 6796 8 view .LVU78
+ 285 000a 03F02803 		and	r3, r3, #40
+ 286 000e 282B     		cmp	r3, #40
+ 287 0010 01D0     		beq	.L32
+6797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable NACK and STOP interrupts */
+6799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ 288              		.loc 1 6799 14 view .LVU79
+ 289 0012 F223     		movs	r3, #242
+ 290 0014 02E0     		b	.L23
+ 291              	.L32:
+6794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 292              		.loc 1 6794 12 view .LVU80
+ 293 0016 4223     		movs	r3, #66
+ 294 0018 00E0     		b	.L23
+ 295              	.LVL23:
+ 296              	.L29:
+6789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 297              		.loc 1 6789 12 view .LVU81
+ 298 001a 0023     		movs	r3, #0
+ 299              	.LVL24:
+ 300              	.L23:
+6800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ 301              		.loc 1 6803 3 is_stmt 1 view .LVU82
+ 302              		.loc 1 6803 6 is_stmt 0 view .LVU83
+ 303 001c 11F0020F 		tst	r1, #2
+ 304 0020 09D0     		beq	.L24
+6804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable TC and RXI interrupts */
+ARM GAS  /tmp/ccbUHtu7.s 			page 126
+
+
+6806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+ 305              		.loc 1 6806 5 is_stmt 1 view .LVU84
+ 306              		.loc 1 6806 12 is_stmt 0 view .LVU85
+ 307 0022 43F0440C 		orr	ip, r3, #68
+ 308              	.LVL25:
+6807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+ 309              		.loc 1 6808 5 is_stmt 1 view .LVU86
+ 310              		.loc 1 6808 24 is_stmt 0 view .LVU87
+ 311 0026 90F84120 		ldrb	r2, [r0, #65]	@ zero_extendqisi2
+ 312              		.loc 1 6808 8 view .LVU88
+ 313 002a 02F02802 		and	r2, r2, #40
+ 314 002e 282A     		cmp	r2, #40
+ 315 0030 10D0     		beq	.L31
+6809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+6810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       /* Disable NACK and STOP interrupts */
+6811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ 316              		.loc 1 6811 7 is_stmt 1 view .LVU89
+ 317              		.loc 1 6811 14 is_stmt 0 view .LVU90
+ 318 0032 43F0F403 		orr	r3, r3, #244
+ 319              	.LVL26:
+ 320              	.L24:
+6812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+6813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ 321              		.loc 1 6815 3 is_stmt 1 view .LVU91
+ 322              		.loc 1 6815 6 is_stmt 0 view .LVU92
+ 323 0036 11F4004F 		tst	r1, #32768
+ 324 003a 0DD1     		bne	.L33
+ 325              	.L25:
+6816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Disable ADDR, NACK and STOP interrupts */
+6818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+6819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (InterruptRequest == I2C_XFER_ERROR_IT)
+ 326              		.loc 1 6821 3 is_stmt 1 view .LVU93
+ 327              		.loc 1 6821 6 is_stmt 0 view .LVU94
+ 328 003c 1029     		cmp	r1, #16
+ 329 003e 0ED0     		beq	.L34
+ 330              	.L26:
+6822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable ERR and NACK interrupts */
+6824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+6825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (InterruptRequest == I2C_XFER_CPLT_IT)
+ 331              		.loc 1 6827 3 is_stmt 1 view .LVU95
+ 332              		.loc 1 6827 6 is_stmt 0 view .LVU96
+ 333 0040 2029     		cmp	r1, #32
+ 334 0042 0FD0     		beq	.L35
+ 335              	.L27:
+6828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable STOP interrupts */
+6830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tmpisr |= I2C_IT_STOPI;
+6831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccbUHtu7.s 			page 127
+
+
+6832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (InterruptRequest == I2C_XFER_RELOAD_IT)
+ 336              		.loc 1 6833 3 is_stmt 1 view .LVU97
+ 337              		.loc 1 6833 6 is_stmt 0 view .LVU98
+ 338 0044 4029     		cmp	r1, #64
+ 339 0046 10D0     		beq	.L36
+ 340              	.L28:
+6834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Enable TC interrupts */
+6836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     tmpisr |= I2C_IT_TCI;
+6837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Disable interrupts only at the end */
+6840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* to avoid a breaking situation like at "t" time */
+6841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* all disable interrupts request are not done */
+6842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+ 341              		.loc 1 6842 3 is_stmt 1 view .LVU99
+ 342 0048 0168     		ldr	r1, [r0]
+ 343              	.LVL27:
+ 344              		.loc 1 6842 3 is_stmt 0 view .LVU100
+ 345 004a 0A68     		ldr	r2, [r1]
+ 346 004c 22EA0303 		bic	r3, r2, r3
+ 347              	.LVL28:
+ 348              		.loc 1 6842 3 view .LVU101
+ 349 0050 0B60     		str	r3, [r1]
+6843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 350              		.loc 1 6843 1 view .LVU102
+ 351 0052 7047     		bx	lr
+ 352              	.LVL29:
+ 353              	.L31:
+6806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 354              		.loc 1 6806 12 view .LVU103
+ 355 0054 6346     		mov	r3, ip
+ 356 0056 EEE7     		b	.L24
+ 357              	.LVL30:
+ 358              	.L33:
+6818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 359              		.loc 1 6818 5 is_stmt 1 view .LVU104
+6818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 360              		.loc 1 6818 12 is_stmt 0 view .LVU105
+ 361 0058 43F0B803 		orr	r3, r3, #184
+ 362              	.LVL31:
+6818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 363              		.loc 1 6818 12 view .LVU106
+ 364 005c EEE7     		b	.L25
+ 365              	.L34:
+6824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 366              		.loc 1 6824 5 is_stmt 1 view .LVU107
+6824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 367              		.loc 1 6824 12 is_stmt 0 view .LVU108
+ 368 005e 43F09003 		orr	r3, r3, #144
+ 369              	.LVL32:
+6824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 370              		.loc 1 6824 12 view .LVU109
+ 371 0062 EDE7     		b	.L26
+ 372              	.L35:
+6830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccbUHtu7.s 			page 128
+
+
+ 373              		.loc 1 6830 5 is_stmt 1 view .LVU110
+6830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 374              		.loc 1 6830 12 is_stmt 0 view .LVU111
+ 375 0064 43F02003 		orr	r3, r3, #32
+ 376              	.LVL33:
+6830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 377              		.loc 1 6830 12 view .LVU112
+ 378 0068 ECE7     		b	.L27
+ 379              	.L36:
+6836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 380              		.loc 1 6836 5 is_stmt 1 view .LVU113
+6836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 381              		.loc 1 6836 12 is_stmt 0 view .LVU114
+ 382 006a 43F04003 		orr	r3, r3, #64
+ 383              	.LVL34:
+6836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 384              		.loc 1 6836 12 view .LVU115
+ 385 006e EBE7     		b	.L28
+ 386              		.cfi_endproc
+ 387              	.LFE406:
+ 389              		.section	.text.I2C_ConvertOtherXferOptions,"ax",%progbits
+ 390              		.align	1
+ 391              		.syntax unified
+ 392              		.thumb
+ 393              		.thumb_func
+ 395              	I2C_ConvertOtherXferOptions:
+ 396              	.LVL35:
+ 397              	.LFB407:
+6844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+6845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+6846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @brief  Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
+6847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+6848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   * @retval None
+6849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   */
+6850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+6851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** {
+ 398              		.loc 1 6851 1 is_stmt 1 view -0
+ 399              		.cfi_startproc
+ 400              		@ args = 0, pretend = 0, frame = 0
+ 401              		@ frame_needed = 0, uses_anonymous_args = 0
+ 402              		@ link register save eliminated.
+6852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* if user set XferOptions to I2C_OTHER_FRAME            */
+6853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* it request implicitly to generate a restart condition */
+6854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* set XferOptions to I2C_FIRST_FRAME                    */
+6855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->XferOptions == I2C_OTHER_FRAME)
+ 403              		.loc 1 6855 3 view .LVU117
+ 404              		.loc 1 6855 11 is_stmt 0 view .LVU118
+ 405 0000 C36A     		ldr	r3, [r0, #44]
+ 406              		.loc 1 6855 6 view .LVU119
+ 407 0002 AA2B     		cmp	r3, #170
+ 408 0004 04D0     		beq	.L40
+6856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_FIRST_FRAME;
+6858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+6860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* it request implicitly to generate a restart condition    */
+6861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* then generate a stop condition at the end of transfer    */
+ARM GAS  /tmp/ccbUHtu7.s 			page 129
+
+
+6862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
+6863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+ 409              		.loc 1 6863 8 is_stmt 1 view .LVU120
+ 410              		.loc 1 6863 16 is_stmt 0 view .LVU121
+ 411 0006 C36A     		ldr	r3, [r0, #44]
+ 412              		.loc 1 6863 11 view .LVU122
+ 413 0008 B3F52A4F 		cmp	r3, #43520
+ 414 000c 03D0     		beq	.L41
+ 415              	.L37:
+6864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+6866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   else
+6868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+6869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     /* Nothing to do */
+6870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+6871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 416              		.loc 1 6871 1 view .LVU123
+ 417 000e 7047     		bx	lr
+ 418              	.L40:
+6857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 419              		.loc 1 6857 5 is_stmt 1 view .LVU124
+6857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 420              		.loc 1 6857 23 is_stmt 0 view .LVU125
+ 421 0010 0023     		movs	r3, #0
+ 422 0012 C362     		str	r3, [r0, #44]
+ 423 0014 7047     		bx	lr
+ 424              	.L41:
+6865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 425              		.loc 1 6865 5 is_stmt 1 view .LVU126
+6865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 426              		.loc 1 6865 23 is_stmt 0 view .LVU127
+ 427 0016 4FF00073 		mov	r3, #33554432
+ 428 001a C362     		str	r3, [r0, #44]
+6870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 429              		.loc 1 6870 3 is_stmt 1 view .LVU128
+ 430              		.loc 1 6871 1 is_stmt 0 view .LVU129
+ 431 001c F7E7     		b	.L37
+ 432              		.cfi_endproc
+ 433              	.LFE407:
+ 435              		.section	.text.I2C_IsErrorOccurred,"ax",%progbits
+ 436              		.align	1
+ 437              		.syntax unified
+ 438              		.thumb
+ 439              		.thumb_func
+ 441              	I2C_IsErrorOccurred:
+ 442              	.LVL36:
+ 443              	.LFB403:
+6546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 444              		.loc 1 6546 1 is_stmt 1 view -0
+ 445              		.cfi_startproc
+ 446              		@ args = 0, pretend = 0, frame = 0
+ 447              		@ frame_needed = 0, uses_anonymous_args = 0
+6546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 448              		.loc 1 6546 1 is_stmt 0 view .LVU131
+ 449 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 450              	.LCFI2:
+ARM GAS  /tmp/ccbUHtu7.s 			page 130
+
+
+ 451              		.cfi_def_cfa_offset 24
+ 452              		.cfi_offset 4, -24
+ 453              		.cfi_offset 5, -20
+ 454              		.cfi_offset 6, -16
+ 455              		.cfi_offset 7, -12
+ 456              		.cfi_offset 8, -8
+ 457              		.cfi_offset 14, -4
+ 458 0004 0446     		mov	r4, r0
+6547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itflag   = hi2c->Instance->ISR;
+ 459              		.loc 1 6547 3 is_stmt 1 view .LVU132
+ 460              	.LVL37:
+6548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t error_code = 0;
+ 461              		.loc 1 6548 3 view .LVU133
+6548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t error_code = 0;
+ 462              		.loc 1 6548 27 is_stmt 0 view .LVU134
+ 463 0006 0368     		ldr	r3, [r0]
+6548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t error_code = 0;
+ 464              		.loc 1 6548 12 view .LVU135
+ 465 0008 9F69     		ldr	r7, [r3, #24]
+ 466              	.LVL38:
+6549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart = Tickstart;
+ 467              		.loc 1 6549 3 is_stmt 1 view .LVU136
+6550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmp1;
+ 468              		.loc 1 6550 3 view .LVU137
+6551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_ModeTypeDef tmp2;
+ 469              		.loc 1 6551 3 view .LVU138
+6552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 470              		.loc 1 6552 3 view .LVU139
+6554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 471              		.loc 1 6554 3 view .LVU140
+6554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 472              		.loc 1 6554 6 is_stmt 0 view .LVU141
+ 473 000a 17F01007 		ands	r7, r7, #16
+ 474              	.LVL39:
+6554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 475              		.loc 1 6554 6 view .LVU142
+ 476 000e 4CD0     		beq	.L59
+ 477 0010 0E46     		mov	r6, r1
+ 478 0012 9046     		mov	r8, r2
+6557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 479              		.loc 1 6557 5 is_stmt 1 view .LVU143
+ 480 0014 1022     		movs	r2, #16
+ 481              	.LVL40:
+6557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 482              		.loc 1 6557 5 is_stmt 0 view .LVU144
+ 483 0016 DA61     		str	r2, [r3, #28]
+6561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 484              		.loc 1 6561 5 is_stmt 1 view .LVU145
+6547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itflag   = hi2c->Instance->ISR;
+ 485              		.loc 1 6547 21 is_stmt 0 view .LVU146
+ 486 0018 0025     		movs	r5, #0
+ 487              	.LVL41:
+ 488              	.L45:
+6561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 489              		.loc 1 6561 64 is_stmt 1 view .LVU147
+6561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 490              		.loc 1 6561 13 is_stmt 0 view .LVU148
+ARM GAS  /tmp/ccbUHtu7.s 			page 131
+
+
+ 491 001a 2368     		ldr	r3, [r4]
+ 492 001c 9869     		ldr	r0, [r3, #24]
+6561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 493              		.loc 1 6561 64 view .LVU149
+ 494 001e 10F0200F 		tst	r0, #32
+ 495 0022 3BD1     		bne	.L52
+6561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 496              		.loc 1 6561 64 discriminator 1 view .LVU150
+ 497 0024 002D     		cmp	r5, #0
+ 498 0026 39D1     		bne	.L52
+6564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 499              		.loc 1 6564 7 is_stmt 1 view .LVU151
+6564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 500              		.loc 1 6564 10 is_stmt 0 view .LVU152
+ 501 0028 B6F1FF3F 		cmp	r6, #-1
+ 502 002c F5D0     		beq	.L45
+6566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 503              		.loc 1 6566 9 is_stmt 1 view .LVU153
+6566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 504              		.loc 1 6566 15 is_stmt 0 view .LVU154
+ 505 002e FFF7FEFF 		bl	HAL_GetTick
+ 506              	.LVL42:
+6566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 507              		.loc 1 6566 29 view .LVU155
+ 508 0032 A0EB0800 		sub	r0, r0, r8
+6566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 509              		.loc 1 6566 12 view .LVU156
+ 510 0036 B042     		cmp	r0, r6
+ 511 0038 01D8     		bhi	.L46
+6566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 512              		.loc 1 6566 53 discriminator 1 view .LVU157
+ 513 003a 002E     		cmp	r6, #0
+ 514 003c EDD1     		bne	.L45
+ 515              	.L46:
+6568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           tmp2 = hi2c->Mode;
+ 516              		.loc 1 6568 11 is_stmt 1 view .LVU158
+6568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           tmp2 = hi2c->Mode;
+ 517              		.loc 1 6568 33 is_stmt 0 view .LVU159
+ 518 003e 2168     		ldr	r1, [r4]
+6568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           tmp2 = hi2c->Mode;
+ 519              		.loc 1 6568 43 view .LVU160
+ 520 0040 4B68     		ldr	r3, [r1, #4]
+6568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           tmp2 = hi2c->Mode;
+ 521              		.loc 1 6568 16 view .LVU161
+ 522 0042 03F48043 		and	r3, r3, #16384
+ 523              	.LVL43:
+6569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 524              		.loc 1 6569 11 is_stmt 1 view .LVU162
+6569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 525              		.loc 1 6569 16 is_stmt 0 view .LVU163
+ 526 0046 94F84220 		ldrb	r2, [r4, #66]	@ zero_extendqisi2
+ 527 004a D2B2     		uxtb	r2, r2
+ 528              	.LVL44:
+6572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               (tmp1 != I2C_CR2_STOP) && \
+ 529              		.loc 1 6572 11 is_stmt 1 view .LVU164
+6572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               (tmp1 != I2C_CR2_STOP) && \
+ 530              		.loc 1 6572 16 is_stmt 0 view .LVU165
+ARM GAS  /tmp/ccbUHtu7.s 			page 132
+
+
+ 531 004c 8869     		ldr	r0, [r1, #24]
+6572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               (tmp1 != I2C_CR2_STOP) && \
+ 532              		.loc 1 6572 14 view .LVU166
+ 533 004e 10F4004F 		tst	r0, #32768
+ 534 0052 02D0     		beq	.L49
+6572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               (tmp1 != I2C_CR2_STOP) && \
+ 535              		.loc 1 6572 66 discriminator 1 view .LVU167
+ 536 0054 0BB9     		cbnz	r3, .L49
+6573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               (tmp2 != HAL_I2C_MODE_SLAVE))
+ 537              		.loc 1 6573 38 view .LVU168
+ 538 0056 202A     		cmp	r2, #32
+ 539 0058 18D1     		bne	.L62
+ 540              	.LVL45:
+ 541              	.L49:
+6583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 542              		.loc 1 6583 59 is_stmt 1 view .LVU169
+6583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 543              		.loc 1 6583 18 is_stmt 0 view .LVU170
+ 544 005a 2368     		ldr	r3, [r4]
+ 545 005c 9B69     		ldr	r3, [r3, #24]
+6583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 546              		.loc 1 6583 59 view .LVU171
+ 547 005e 13F0200F 		tst	r3, #32
+ 548 0062 DAD1     		bne	.L45
+6586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             {
+ 549              		.loc 1 6586 13 is_stmt 1 view .LVU172
+6586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             {
+ 550              		.loc 1 6586 18 is_stmt 0 view .LVU173
+ 551 0064 FFF7FEFF 		bl	HAL_GetTick
+ 552              	.LVL46:
+6586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             {
+ 553              		.loc 1 6586 32 view .LVU174
+ 554 0068 A0EB0800 		sub	r0, r0, r8
+6586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             {
+ 555              		.loc 1 6586 16 view .LVU175
+ 556 006c 1928     		cmp	r0, #25
+ 557 006e F4D9     		bls	.L49
+6588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               hi2c->State = HAL_I2C_STATE_READY;
+ 558              		.loc 1 6588 15 is_stmt 1 view .LVU176
+6588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               hi2c->State = HAL_I2C_STATE_READY;
+ 559              		.loc 1 6588 19 is_stmt 0 view .LVU177
+ 560 0070 636C     		ldr	r3, [r4, #68]
+6588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               hi2c->State = HAL_I2C_STATE_READY;
+ 561              		.loc 1 6588 31 view .LVU178
+ 562 0072 43F02003 		orr	r3, r3, #32
+ 563 0076 6364     		str	r3, [r4, #68]
+6589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               hi2c->Mode = HAL_I2C_MODE_NONE;
+ 564              		.loc 1 6589 15 is_stmt 1 view .LVU179
+6589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               hi2c->Mode = HAL_I2C_MODE_NONE;
+ 565              		.loc 1 6589 27 is_stmt 0 view .LVU180
+ 566 0078 2023     		movs	r3, #32
+ 567 007a 84F84130 		strb	r3, [r4, #65]
+6590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               
+ 568              		.loc 1 6590 15 is_stmt 1 view .LVU181
+6590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               
+ 569              		.loc 1 6590 26 is_stmt 0 view .LVU182
+ 570 007e 0023     		movs	r3, #0
+ARM GAS  /tmp/ccbUHtu7.s 			page 133
+
+
+ 571 0080 84F84230 		strb	r3, [r4, #66]
+6593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               
+ 572              		.loc 1 6593 15 is_stmt 1 view .LVU183
+6593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               
+ 573              		.loc 1 6593 15 view .LVU184
+ 574 0084 84F84030 		strb	r3, [r4, #64]
+6593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****               
+ 575              		.loc 1 6593 15 view .LVU185
+6595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             }
+ 576              		.loc 1 6595 15 view .LVU186
+ 577              	.LVL47:
+6595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             }
+ 578              		.loc 1 6595 22 is_stmt 0 view .LVU187
+ 579 0088 0125     		movs	r5, #1
+ 580 008a E6E7     		b	.L49
+ 581              	.LVL48:
+ 582              	.L62:
+6577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             
+ 583              		.loc 1 6577 13 is_stmt 1 view .LVU188
+6577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             
+ 584              		.loc 1 6577 27 is_stmt 0 view .LVU189
+ 585 008c 4B68     		ldr	r3, [r1, #4]
+ 586              	.LVL49:
+6577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****             
+ 587              		.loc 1 6577 33 view .LVU190
+ 588 008e 43F48043 		orr	r3, r3, #16384
+ 589 0092 4B60     		str	r3, [r1, #4]
+6580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 590              		.loc 1 6580 13 is_stmt 1 view .LVU191
+6580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 591              		.loc 1 6580 25 is_stmt 0 view .LVU192
+ 592 0094 FFF7FEFF 		bl	HAL_GetTick
+ 593              	.LVL50:
+6580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 594              		.loc 1 6580 25 view .LVU193
+ 595 0098 8046     		mov	r8, r0
+ 596              	.LVL51:
+6580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 597              		.loc 1 6580 25 view .LVU194
+ 598 009a DEE7     		b	.L49
+ 599              	.LVL52:
+ 600              	.L52:
+6603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 601              		.loc 1 6603 5 is_stmt 1 view .LVU195
+6603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 602              		.loc 1 6603 8 is_stmt 0 view .LVU196
+ 603 009c 002D     		cmp	r5, #0
+ 604 009e 40D1     		bne	.L60
+6606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 605              		.loc 1 6606 7 is_stmt 1 view .LVU197
+ 606 00a0 2022     		movs	r2, #32
+ 607 00a2 DA61     		str	r2, [r3, #28]
+6609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 608              		.loc 1 6609 16 is_stmt 0 view .LVU198
+ 609 00a4 0427     		movs	r7, #4
+6611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 610              		.loc 1 6611 12 view .LVU199
+ARM GAS  /tmp/ccbUHtu7.s 			page 134
+
+
+ 611 00a6 0125     		movs	r5, #1
+ 612              	.LVL53:
+6611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 613              		.loc 1 6611 12 view .LVU200
+ 614 00a8 00E0     		b	.L43
+ 615              	.LVL54:
+ 616              	.L59:
+6547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itflag   = hi2c->Instance->ISR;
+ 617              		.loc 1 6547 21 view .LVU201
+ 618 00aa 0025     		movs	r5, #0
+ 619              	.LVL55:
+ 620              	.L43:
+6615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 621              		.loc 1 6615 3 is_stmt 1 view .LVU202
+6615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 622              		.loc 1 6615 16 is_stmt 0 view .LVU203
+ 623 00ac 2268     		ldr	r2, [r4]
+6615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 624              		.loc 1 6615 10 view .LVU204
+ 625 00ae 9369     		ldr	r3, [r2, #24]
+ 626              	.LVL56:
+6619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 627              		.loc 1 6619 3 is_stmt 1 view .LVU205
+6619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 628              		.loc 1 6619 6 is_stmt 0 view .LVU206
+ 629 00b0 13F4807F 		tst	r3, #256
+ 630 00b4 05D0     		beq	.L54
+6621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 631              		.loc 1 6621 5 is_stmt 1 view .LVU207
+6621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 632              		.loc 1 6621 16 is_stmt 0 view .LVU208
+ 633 00b6 47F00107 		orr	r7, r7, #1
+ 634              	.LVL57:
+6624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 635              		.loc 1 6624 5 is_stmt 1 view .LVU209
+ 636 00ba 4FF48071 		mov	r1, #256
+ 637 00be D161     		str	r1, [r2, #28]
+6626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 638              		.loc 1 6626 5 view .LVU210
+ 639              	.LVL58:
+6626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 640              		.loc 1 6626 12 is_stmt 0 view .LVU211
+ 641 00c0 0125     		movs	r5, #1
+ 642              	.LVL59:
+ 643              	.L54:
+6630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 644              		.loc 1 6630 3 is_stmt 1 view .LVU212
+6630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 645              		.loc 1 6630 6 is_stmt 0 view .LVU213
+ 646 00c2 13F4806F 		tst	r3, #1024
+ 647 00c6 06D0     		beq	.L55
+6632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 648              		.loc 1 6632 5 is_stmt 1 view .LVU214
+6632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 649              		.loc 1 6632 16 is_stmt 0 view .LVU215
+ 650 00c8 47F00807 		orr	r7, r7, #8
+ 651              	.LVL60:
+ARM GAS  /tmp/ccbUHtu7.s 			page 135
+
+
+6635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 652              		.loc 1 6635 5 is_stmt 1 view .LVU216
+ 653 00cc 2268     		ldr	r2, [r4]
+ 654 00ce 4FF48061 		mov	r1, #1024
+ 655 00d2 D161     		str	r1, [r2, #28]
+6637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 656              		.loc 1 6637 5 view .LVU217
+ 657              	.LVL61:
+6637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 658              		.loc 1 6637 12 is_stmt 0 view .LVU218
+ 659 00d4 0125     		movs	r5, #1
+ 660              	.LVL62:
+ 661              	.L55:
+6641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 662              		.loc 1 6641 3 is_stmt 1 view .LVU219
+6641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 663              		.loc 1 6641 6 is_stmt 0 view .LVU220
+ 664 00d6 13F4007F 		tst	r3, #512
+ 665 00da 24D0     		beq	.L56
+6643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 666              		.loc 1 6643 5 is_stmt 1 view .LVU221
+6643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 667              		.loc 1 6643 16 is_stmt 0 view .LVU222
+ 668 00dc 47F00207 		orr	r7, r7, #2
+ 669              	.LVL63:
+6646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 670              		.loc 1 6646 5 is_stmt 1 view .LVU223
+ 671 00e0 2368     		ldr	r3, [r4]
+ 672              	.LVL64:
+6646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 673              		.loc 1 6646 5 is_stmt 0 view .LVU224
+ 674 00e2 4FF40072 		mov	r2, #512
+ 675 00e6 DA61     		str	r2, [r3, #28]
+6648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 676              		.loc 1 6648 5 is_stmt 1 view .LVU225
+ 677              	.LVL65:
+6651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 678              		.loc 1 6651 3 view .LVU226
+6648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 679              		.loc 1 6648 12 is_stmt 0 view .LVU227
+ 680 00e8 0125     		movs	r5, #1
+ 681              	.LVL66:
+ 682              	.L57:
+6654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 683              		.loc 1 6654 5 is_stmt 1 view .LVU228
+ 684 00ea 2046     		mov	r0, r4
+ 685 00ec FFF7FEFF 		bl	I2C_Flush_TXDR
+ 686              	.LVL67:
+6657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 687              		.loc 1 6657 5 view .LVU229
+ 688 00f0 2268     		ldr	r2, [r4]
+ 689 00f2 5368     		ldr	r3, [r2, #4]
+ 690 00f4 23F0FF73 		bic	r3, r3, #33423360
+ 691 00f8 23F48B33 		bic	r3, r3, #71168
+ 692 00fc 23F4FF73 		bic	r3, r3, #510
+ 693 0100 23F00103 		bic	r3, r3, #1
+ 694 0104 5360     		str	r3, [r2, #4]
+ARM GAS  /tmp/ccbUHtu7.s 			page 136
+
+
+6659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 695              		.loc 1 6659 5 view .LVU230
+6659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 696              		.loc 1 6659 9 is_stmt 0 view .LVU231
+ 697 0106 636C     		ldr	r3, [r4, #68]
+6659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 698              		.loc 1 6659 21 view .LVU232
+ 699 0108 3B43     		orrs	r3, r3, r7
+ 700 010a 6364     		str	r3, [r4, #68]
+6660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode = HAL_I2C_MODE_NONE;
+ 701              		.loc 1 6660 5 is_stmt 1 view .LVU233
+6660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode = HAL_I2C_MODE_NONE;
+ 702              		.loc 1 6660 17 is_stmt 0 view .LVU234
+ 703 010c 2023     		movs	r3, #32
+ 704 010e 84F84130 		strb	r3, [r4, #65]
+6661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 705              		.loc 1 6661 5 is_stmt 1 view .LVU235
+6661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 706              		.loc 1 6661 16 is_stmt 0 view .LVU236
+ 707 0112 0023     		movs	r3, #0
+ 708 0114 84F84230 		strb	r3, [r4, #66]
+6664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 709              		.loc 1 6664 5 is_stmt 1 view .LVU237
+6664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 710              		.loc 1 6664 5 view .LVU238
+ 711 0118 84F84030 		strb	r3, [r4, #64]
+ 712              	.L58:
+6664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 713              		.loc 1 6664 5 discriminator 1 view .LVU239
+6667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 714              		.loc 1 6667 3 discriminator 1 view .LVU240
+6668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 715              		.loc 1 6668 1 is_stmt 0 discriminator 1 view .LVU241
+ 716 011c 2846     		mov	r0, r5
+ 717 011e BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 718              	.LVL68:
+ 719              	.L60:
+6609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 720              		.loc 1 6609 16 view .LVU242
+ 721 0122 0427     		movs	r7, #4
+ 722 0124 C2E7     		b	.L43
+ 723              	.LVL69:
+ 724              	.L56:
+6651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 725              		.loc 1 6651 3 is_stmt 1 view .LVU243
+6651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 726              		.loc 1 6651 6 is_stmt 0 view .LVU244
+ 727 0126 002D     		cmp	r5, #0
+ 728 0128 F8D0     		beq	.L58
+ 729 012a DEE7     		b	.L57
+ 730              		.cfi_endproc
+ 731              	.LFE403:
+ 733              		.section	.text.I2C_WaitOnTXISFlagUntilTimeout,"ax",%progbits
+ 734              		.align	1
+ 735              		.syntax unified
+ 736              		.thumb
+ 737              		.thumb_func
+ARM GAS  /tmp/ccbUHtu7.s 			page 137
+
+
+ 739              	I2C_WaitOnTXISFlagUntilTimeout:
+ 740              	.LVL70:
+ 741              	.LFB400:
+6401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+ 742              		.loc 1 6401 1 is_stmt 1 view -0
+ 743              		.cfi_startproc
+ 744              		@ args = 0, pretend = 0, frame = 0
+ 745              		@ frame_needed = 0, uses_anonymous_args = 0
+6401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+ 746              		.loc 1 6401 1 is_stmt 0 view .LVU246
+ 747 0000 70B5     		push	{r4, r5, r6, lr}
+ 748              	.LCFI3:
+ 749              		.cfi_def_cfa_offset 16
+ 750              		.cfi_offset 4, -16
+ 751              		.cfi_offset 5, -12
+ 752              		.cfi_offset 6, -8
+ 753              		.cfi_offset 14, -4
+ 754 0002 0446     		mov	r4, r0
+ 755 0004 0D46     		mov	r5, r1
+ 756 0006 1646     		mov	r6, r2
+6402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 757              		.loc 1 6402 3 is_stmt 1 view .LVU247
+ 758              	.LVL71:
+ 759              	.L66:
+6402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 760              		.loc 1 6402 50 view .LVU248
+6402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 761              		.loc 1 6402 10 is_stmt 0 view .LVU249
+ 762 0008 2368     		ldr	r3, [r4]
+ 763 000a 9B69     		ldr	r3, [r3, #24]
+6402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 764              		.loc 1 6402 50 view .LVU250
+ 765 000c 13F0020F 		tst	r3, #2
+ 766 0010 1DD1     		bne	.L71
+6405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 767              		.loc 1 6405 5 is_stmt 1 view .LVU251
+6405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 768              		.loc 1 6405 9 is_stmt 0 view .LVU252
+ 769 0012 3246     		mov	r2, r6
+ 770 0014 2946     		mov	r1, r5
+ 771 0016 2046     		mov	r0, r4
+ 772 0018 FFF7FEFF 		bl	I2C_IsErrorOccurred
+ 773              	.LVL72:
+6405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 774              		.loc 1 6405 8 view .LVU253
+ 775 001c C8B9     		cbnz	r0, .L69
+6411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 776              		.loc 1 6411 5 is_stmt 1 view .LVU254
+6411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 777              		.loc 1 6411 8 is_stmt 0 view .LVU255
+ 778 001e B5F1FF3F 		cmp	r5, #-1
+ 779 0022 F1D0     		beq	.L66
+6413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 780              		.loc 1 6413 7 is_stmt 1 view .LVU256
+6413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 781              		.loc 1 6413 13 is_stmt 0 view .LVU257
+ 782 0024 FFF7FEFF 		bl	HAL_GetTick
+ARM GAS  /tmp/ccbUHtu7.s 			page 138
+
+
+ 783              	.LVL73:
+6413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 784              		.loc 1 6413 27 view .LVU258
+ 785 0028 801B     		subs	r0, r0, r6
+6413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 786              		.loc 1 6413 10 view .LVU259
+ 787 002a A842     		cmp	r0, r5
+ 788 002c 01D8     		bhi	.L67
+6413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 789              		.loc 1 6413 51 discriminator 1 view .LVU260
+ 790 002e 002D     		cmp	r5, #0
+ 791 0030 EAD1     		bne	.L66
+ 792              	.L67:
+6415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+ 793              		.loc 1 6415 9 is_stmt 1 view .LVU261
+6415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+ 794              		.loc 1 6415 13 is_stmt 0 view .LVU262
+ 795 0032 636C     		ldr	r3, [r4, #68]
+6415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+ 796              		.loc 1 6415 25 view .LVU263
+ 797 0034 43F02003 		orr	r3, r3, #32
+ 798 0038 6364     		str	r3, [r4, #68]
+6416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+ 799              		.loc 1 6416 9 is_stmt 1 view .LVU264
+6416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+ 800              		.loc 1 6416 21 is_stmt 0 view .LVU265
+ 801 003a 2023     		movs	r3, #32
+ 802 003c 84F84130 		strb	r3, [r4, #65]
+6417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 803              		.loc 1 6417 9 is_stmt 1 view .LVU266
+6417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 804              		.loc 1 6417 20 is_stmt 0 view .LVU267
+ 805 0040 0023     		movs	r3, #0
+ 806 0042 84F84230 		strb	r3, [r4, #66]
+6420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 807              		.loc 1 6420 9 is_stmt 1 view .LVU268
+6420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 808              		.loc 1 6420 9 view .LVU269
+ 809 0046 84F84030 		strb	r3, [r4, #64]
+6420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 810              		.loc 1 6420 9 view .LVU270
+6422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 811              		.loc 1 6422 9 view .LVU271
+6422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 812              		.loc 1 6422 16 is_stmt 0 view .LVU272
+ 813 004a 0120     		movs	r0, #1
+ 814 004c 00E0     		b	.L65
+ 815              	.L71:
+6426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 816              		.loc 1 6426 10 view .LVU273
+ 817 004e 0020     		movs	r0, #0
+ 818              	.L65:
+6427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 819              		.loc 1 6427 1 view .LVU274
+ 820 0050 70BD     		pop	{r4, r5, r6, pc}
+ 821              	.LVL74:
+ 822              	.L69:
+ARM GAS  /tmp/ccbUHtu7.s 			page 139
+
+
+6407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 823              		.loc 1 6407 14 view .LVU275
+ 824 0052 0120     		movs	r0, #1
+ 825 0054 FCE7     		b	.L65
+ 826              		.cfi_endproc
+ 827              	.LFE400:
+ 829              		.section	.text.I2C_WaitOnFlagUntilTimeout,"ax",%progbits
+ 830              		.align	1
+ 831              		.syntax unified
+ 832              		.thumb
+ 833              		.thumb_func
+ 835              	I2C_WaitOnFlagUntilTimeout:
+ 836              	.LVL75:
+ 837              	.LFB399:
+6370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+ 838              		.loc 1 6370 1 is_stmt 1 view -0
+ 839              		.cfi_startproc
+ 840              		@ args = 4, pretend = 0, frame = 0
+ 841              		@ frame_needed = 0, uses_anonymous_args = 0
+6370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+ 842              		.loc 1 6370 1 is_stmt 0 view .LVU277
+ 843 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 844              	.LCFI4:
+ 845              		.cfi_def_cfa_offset 24
+ 846              		.cfi_offset 4, -24
+ 847              		.cfi_offset 5, -20
+ 848              		.cfi_offset 6, -16
+ 849              		.cfi_offset 7, -12
+ 850              		.cfi_offset 8, -8
+ 851              		.cfi_offset 14, -4
+ 852 0004 0646     		mov	r6, r0
+ 853 0006 8846     		mov	r8, r1
+ 854 0008 1746     		mov	r7, r2
+ 855 000a 1D46     		mov	r5, r3
+6371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 856              		.loc 1 6371 3 is_stmt 1 view .LVU278
+ 857              	.LVL76:
+ 858              	.L74:
+6371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 859              		.loc 1 6371 41 view .LVU279
+6371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 860              		.loc 1 6371 10 is_stmt 0 view .LVU280
+ 861 000c 3468     		ldr	r4, [r6]
+ 862 000e A469     		ldr	r4, [r4, #24]
+ 863 0010 38EA0404 		bics	r4, r8, r4
+ 864 0014 0CBF     		ite	eq
+ 865 0016 0124     		moveq	r4, #1
+ 866 0018 0024     		movne	r4, #0
+6371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 867              		.loc 1 6371 41 view .LVU281
+ 868 001a BC42     		cmp	r4, r7
+ 869 001c 18D1     		bne	.L79
+6374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 870              		.loc 1 6374 5 is_stmt 1 view .LVU282
+6374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 871              		.loc 1 6374 8 is_stmt 0 view .LVU283
+ 872 001e B5F1FF3F 		cmp	r5, #-1
+ARM GAS  /tmp/ccbUHtu7.s 			page 140
+
+
+ 873 0022 F3D0     		beq	.L74
+6376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 874              		.loc 1 6376 7 is_stmt 1 view .LVU284
+6376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 875              		.loc 1 6376 13 is_stmt 0 view .LVU285
+ 876 0024 FFF7FEFF 		bl	HAL_GetTick
+ 877              	.LVL77:
+6376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 878              		.loc 1 6376 27 view .LVU286
+ 879 0028 069B     		ldr	r3, [sp, #24]
+ 880 002a C01A     		subs	r0, r0, r3
+6376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 881              		.loc 1 6376 10 view .LVU287
+ 882 002c A842     		cmp	r0, r5
+ 883 002e 01D8     		bhi	.L75
+6376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 884              		.loc 1 6376 51 discriminator 1 view .LVU288
+ 885 0030 002D     		cmp	r5, #0
+ 886 0032 EBD1     		bne	.L74
+ 887              	.L75:
+6378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+ 888              		.loc 1 6378 9 is_stmt 1 view .LVU289
+6378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+ 889              		.loc 1 6378 13 is_stmt 0 view .LVU290
+ 890 0034 736C     		ldr	r3, [r6, #68]
+6378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+ 891              		.loc 1 6378 25 view .LVU291
+ 892 0036 43F02003 		orr	r3, r3, #32
+ 893 003a 7364     		str	r3, [r6, #68]
+6379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+ 894              		.loc 1 6379 9 is_stmt 1 view .LVU292
+6379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+ 895              		.loc 1 6379 21 is_stmt 0 view .LVU293
+ 896 003c 2023     		movs	r3, #32
+ 897 003e 86F84130 		strb	r3, [r6, #65]
+6380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 898              		.loc 1 6380 9 is_stmt 1 view .LVU294
+6380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 899              		.loc 1 6380 20 is_stmt 0 view .LVU295
+ 900 0042 0023     		movs	r3, #0
+ 901 0044 86F84230 		strb	r3, [r6, #66]
+6383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+ 902              		.loc 1 6383 9 is_stmt 1 view .LVU296
+6383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+ 903              		.loc 1 6383 9 view .LVU297
+ 904 0048 86F84030 		strb	r3, [r6, #64]
+6383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+ 905              		.loc 1 6383 9 view .LVU298
+6384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 906              		.loc 1 6384 9 view .LVU299
+6384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 907              		.loc 1 6384 16 is_stmt 0 view .LVU300
+ 908 004c 0120     		movs	r0, #1
+ 909 004e 00E0     		b	.L76
+ 910              	.L79:
+6388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 911              		.loc 1 6388 10 view .LVU301
+ARM GAS  /tmp/ccbUHtu7.s 			page 141
+
+
+ 912 0050 0020     		movs	r0, #0
+ 913              	.L76:
+6389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 914              		.loc 1 6389 1 view .LVU302
+ 915 0052 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+6389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 916              		.loc 1 6389 1 view .LVU303
+ 917              		.cfi_endproc
+ 918              	.LFE399:
+ 920              		.section	.text.I2C_RequestMemoryWrite,"ax",%progbits
+ 921              		.align	1
+ 922              		.syntax unified
+ 923              		.thumb
+ 924              		.thumb_func
+ 926              	I2C_RequestMemoryWrite:
+ 927              	.LVL78:
+ 928              	.LFB382:
+5318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI
+ 929              		.loc 1 5318 1 is_stmt 1 view -0
+ 930              		.cfi_startproc
+ 931              		@ args = 8, pretend = 0, frame = 0
+ 932              		@ frame_needed = 0, uses_anonymous_args = 0
+5318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI
+ 933              		.loc 1 5318 1 is_stmt 0 view .LVU305
+ 934 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 935              	.LCFI5:
+ 936              		.cfi_def_cfa_offset 24
+ 937              		.cfi_offset 4, -24
+ 938              		.cfi_offset 5, -20
+ 939              		.cfi_offset 6, -16
+ 940              		.cfi_offset 7, -12
+ 941              		.cfi_offset 8, -8
+ 942              		.cfi_offset 14, -4
+ 943 0004 82B0     		sub	sp, sp, #8
+ 944              	.LCFI6:
+ 945              		.cfi_def_cfa_offset 32
+ 946 0006 0446     		mov	r4, r0
+ 947 0008 9046     		mov	r8, r2
+ 948 000a 1D46     		mov	r5, r3
+ 949 000c 089E     		ldr	r6, [sp, #32]
+ 950 000e 099F     		ldr	r7, [sp, #36]
+5319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 951              		.loc 1 5319 3 is_stmt 1 view .LVU306
+ 952 0010 194B     		ldr	r3, .L89
+ 953              	.LVL79:
+5319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 954              		.loc 1 5319 3 is_stmt 0 view .LVU307
+ 955 0012 0093     		str	r3, [sp]
+ 956 0014 4FF08073 		mov	r3, #16777216
+ 957 0018 EAB2     		uxtb	r2, r5
+ 958              	.LVL80:
+5319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 959              		.loc 1 5319 3 view .LVU308
+ 960 001a FFF7FEFF 		bl	I2C_TransferConfig
+ 961              	.LVL81:
+5322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 962              		.loc 1 5322 3 is_stmt 1 view .LVU309
+ARM GAS  /tmp/ccbUHtu7.s 			page 142
+
+
+5322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 963              		.loc 1 5322 7 is_stmt 0 view .LVU310
+ 964 001e 3A46     		mov	r2, r7
+ 965 0020 3146     		mov	r1, r6
+ 966 0022 2046     		mov	r0, r4
+ 967 0024 FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 968              	.LVL82:
+5322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 969              		.loc 1 5322 6 view .LVU311
+ 970 0028 F8B9     		cbnz	r0, .L84
+5328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 971              		.loc 1 5328 3 is_stmt 1 view .LVU312
+5328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 972              		.loc 1 5328 6 is_stmt 0 view .LVU313
+ 973 002a 012D     		cmp	r5, #1
+ 974 002c 0ED1     		bne	.L82
+5331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 975              		.loc 1 5331 5 is_stmt 1 view .LVU314
+5331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 976              		.loc 1 5331 9 is_stmt 0 view .LVU315
+ 977 002e 2368     		ldr	r3, [r4]
+5331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 978              		.loc 1 5331 28 view .LVU316
+ 979 0030 5FFA88F2 		uxtb	r2, r8
+5331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 980              		.loc 1 5331 26 view .LVU317
+ 981 0034 9A62     		str	r2, [r3, #40]
+ 982              	.L83:
+5350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 983              		.loc 1 5350 3 is_stmt 1 view .LVU318
+5350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 984              		.loc 1 5350 7 is_stmt 0 view .LVU319
+ 985 0036 0097     		str	r7, [sp]
+ 986 0038 3346     		mov	r3, r6
+ 987 003a 0022     		movs	r2, #0
+ 988 003c 8021     		movs	r1, #128
+ 989 003e 2046     		mov	r0, r4
+ 990 0040 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 991              	.LVL83:
+5350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 992              		.loc 1 5350 6 view .LVU320
+ 993 0044 A8B9     		cbnz	r0, .L88
+ 994              	.L81:
+5356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 995              		.loc 1 5356 1 view .LVU321
+ 996 0046 02B0     		add	sp, sp, #8
+ 997              	.LCFI7:
+ 998              		.cfi_remember_state
+ 999              		.cfi_def_cfa_offset 24
+ 1000              		@ sp needed
+ 1001 0048 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 1002              	.LVL84:
+ 1003              	.L82:
+ 1004              	.LCFI8:
+ 1005              		.cfi_restore_state
+5337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1006              		.loc 1 5337 5 is_stmt 1 view .LVU322
+ARM GAS  /tmp/ccbUHtu7.s 			page 143
+
+
+5337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1007              		.loc 1 5337 9 is_stmt 0 view .LVU323
+ 1008 004c 2368     		ldr	r3, [r4]
+5337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1009              		.loc 1 5337 28 view .LVU324
+ 1010 004e 4FEA1822 		lsr	r2, r8, #8
+5337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1011              		.loc 1 5337 26 view .LVU325
+ 1012 0052 9A62     		str	r2, [r3, #40]
+5340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1013              		.loc 1 5340 5 is_stmt 1 view .LVU326
+5340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1014              		.loc 1 5340 9 is_stmt 0 view .LVU327
+ 1015 0054 3A46     		mov	r2, r7
+ 1016 0056 3146     		mov	r1, r6
+ 1017 0058 2046     		mov	r0, r4
+ 1018 005a FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 1019              	.LVL85:
+5340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1020              		.loc 1 5340 8 view .LVU328
+ 1021 005e 30B9     		cbnz	r0, .L85
+5346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1022              		.loc 1 5346 5 is_stmt 1 view .LVU329
+5346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1023              		.loc 1 5346 9 is_stmt 0 view .LVU330
+ 1024 0060 2368     		ldr	r3, [r4]
+5346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1025              		.loc 1 5346 28 view .LVU331
+ 1026 0062 5FFA88F2 		uxtb	r2, r8
+5346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1027              		.loc 1 5346 26 view .LVU332
+ 1028 0066 9A62     		str	r2, [r3, #40]
+ 1029 0068 E5E7     		b	.L83
+ 1030              	.L84:
+5324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1031              		.loc 1 5324 12 view .LVU333
+ 1032 006a 0120     		movs	r0, #1
+ 1033 006c EBE7     		b	.L81
+ 1034              	.L85:
+5342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 1035              		.loc 1 5342 14 view .LVU334
+ 1036 006e 0120     		movs	r0, #1
+ 1037 0070 E9E7     		b	.L81
+ 1038              	.L88:
+5352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1039              		.loc 1 5352 12 view .LVU335
+ 1040 0072 0120     		movs	r0, #1
+ 1041 0074 E7E7     		b	.L81
+ 1042              	.L90:
+ 1043 0076 00BF     		.align	2
+ 1044              	.L89:
+ 1045 0078 00200080 		.word	-2147475456
+ 1046              		.cfi_endproc
+ 1047              	.LFE382:
+ 1049              		.section	.text.I2C_RequestMemoryRead,"ax",%progbits
+ 1050              		.align	1
+ 1051              		.syntax unified
+ARM GAS  /tmp/ccbUHtu7.s 			page 144
+
+
+ 1052              		.thumb
+ 1053              		.thumb_func
+ 1055              	I2C_RequestMemoryRead:
+ 1056              	.LVL86:
+ 1057              	.LFB383:
+5373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR
+ 1058              		.loc 1 5373 1 is_stmt 1 view -0
+ 1059              		.cfi_startproc
+ 1060              		@ args = 8, pretend = 0, frame = 0
+ 1061              		@ frame_needed = 0, uses_anonymous_args = 0
+5373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR
+ 1062              		.loc 1 5373 1 is_stmt 0 view .LVU337
+ 1063 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 1064              	.LCFI9:
+ 1065              		.cfi_def_cfa_offset 24
+ 1066              		.cfi_offset 4, -24
+ 1067              		.cfi_offset 5, -20
+ 1068              		.cfi_offset 6, -16
+ 1069              		.cfi_offset 7, -12
+ 1070              		.cfi_offset 8, -8
+ 1071              		.cfi_offset 14, -4
+ 1072 0004 82B0     		sub	sp, sp, #8
+ 1073              	.LCFI10:
+ 1074              		.cfi_def_cfa_offset 32
+ 1075 0006 0446     		mov	r4, r0
+ 1076 0008 9046     		mov	r8, r2
+ 1077 000a 1D46     		mov	r5, r3
+ 1078 000c 089E     		ldr	r6, [sp, #32]
+ 1079 000e 099F     		ldr	r7, [sp, #36]
+5374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1080              		.loc 1 5374 3 is_stmt 1 view .LVU338
+ 1081 0010 184B     		ldr	r3, .L100
+ 1082              	.LVL87:
+5374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1083              		.loc 1 5374 3 is_stmt 0 view .LVU339
+ 1084 0012 0093     		str	r3, [sp]
+ 1085 0014 0023     		movs	r3, #0
+ 1086 0016 EAB2     		uxtb	r2, r5
+ 1087              	.LVL88:
+5374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1088              		.loc 1 5374 3 view .LVU340
+ 1089 0018 FFF7FEFF 		bl	I2C_TransferConfig
+ 1090              	.LVL89:
+5377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1091              		.loc 1 5377 3 is_stmt 1 view .LVU341
+5377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1092              		.loc 1 5377 7 is_stmt 0 view .LVU342
+ 1093 001c 3A46     		mov	r2, r7
+ 1094 001e 3146     		mov	r1, r6
+ 1095 0020 2046     		mov	r0, r4
+ 1096 0022 FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 1097              	.LVL90:
+5377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1098              		.loc 1 5377 6 view .LVU343
+ 1099 0026 F8B9     		cbnz	r0, .L95
+5383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1100              		.loc 1 5383 3 is_stmt 1 view .LVU344
+ARM GAS  /tmp/ccbUHtu7.s 			page 145
+
+
+5383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1101              		.loc 1 5383 6 is_stmt 0 view .LVU345
+ 1102 0028 012D     		cmp	r5, #1
+ 1103 002a 0ED1     		bne	.L93
+5386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1104              		.loc 1 5386 5 is_stmt 1 view .LVU346
+5386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1105              		.loc 1 5386 9 is_stmt 0 view .LVU347
+ 1106 002c 2368     		ldr	r3, [r4]
+5386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1107              		.loc 1 5386 28 view .LVU348
+ 1108 002e 5FFA88F2 		uxtb	r2, r8
+5386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1109              		.loc 1 5386 26 view .LVU349
+ 1110 0032 9A62     		str	r2, [r3, #40]
+ 1111              	.L94:
+5405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1112              		.loc 1 5405 3 is_stmt 1 view .LVU350
+5405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1113              		.loc 1 5405 7 is_stmt 0 view .LVU351
+ 1114 0034 0097     		str	r7, [sp]
+ 1115 0036 3346     		mov	r3, r6
+ 1116 0038 0022     		movs	r2, #0
+ 1117 003a 4021     		movs	r1, #64
+ 1118 003c 2046     		mov	r0, r4
+ 1119 003e FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 1120              	.LVL91:
+5405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1121              		.loc 1 5405 6 view .LVU352
+ 1122 0042 A8B9     		cbnz	r0, .L99
+ 1123              	.L92:
+5411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1124              		.loc 1 5411 1 view .LVU353
+ 1125 0044 02B0     		add	sp, sp, #8
+ 1126              	.LCFI11:
+ 1127              		.cfi_remember_state
+ 1128              		.cfi_def_cfa_offset 24
+ 1129              		@ sp needed
+ 1130 0046 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 1131              	.LVL92:
+ 1132              	.L93:
+ 1133              	.LCFI12:
+ 1134              		.cfi_restore_state
+5392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1135              		.loc 1 5392 5 is_stmt 1 view .LVU354
+5392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1136              		.loc 1 5392 9 is_stmt 0 view .LVU355
+ 1137 004a 2368     		ldr	r3, [r4]
+5392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1138              		.loc 1 5392 28 view .LVU356
+ 1139 004c 4FEA1822 		lsr	r2, r8, #8
+5392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1140              		.loc 1 5392 26 view .LVU357
+ 1141 0050 9A62     		str	r2, [r3, #40]
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1142              		.loc 1 5395 5 is_stmt 1 view .LVU358
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccbUHtu7.s 			page 146
+
+
+ 1143              		.loc 1 5395 9 is_stmt 0 view .LVU359
+ 1144 0052 3A46     		mov	r2, r7
+ 1145 0054 3146     		mov	r1, r6
+ 1146 0056 2046     		mov	r0, r4
+ 1147 0058 FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 1148              	.LVL93:
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1149              		.loc 1 5395 8 view .LVU360
+ 1150 005c 30B9     		cbnz	r0, .L96
+5401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1151              		.loc 1 5401 5 is_stmt 1 view .LVU361
+5401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1152              		.loc 1 5401 9 is_stmt 0 view .LVU362
+ 1153 005e 2368     		ldr	r3, [r4]
+5401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1154              		.loc 1 5401 28 view .LVU363
+ 1155 0060 5FFA88F2 		uxtb	r2, r8
+5401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1156              		.loc 1 5401 26 view .LVU364
+ 1157 0064 9A62     		str	r2, [r3, #40]
+ 1158 0066 E5E7     		b	.L94
+ 1159              	.L95:
+5379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1160              		.loc 1 5379 12 view .LVU365
+ 1161 0068 0120     		movs	r0, #1
+ 1162 006a EBE7     		b	.L92
+ 1163              	.L96:
+5397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 1164              		.loc 1 5397 14 view .LVU366
+ 1165 006c 0120     		movs	r0, #1
+ 1166 006e E9E7     		b	.L92
+ 1167              	.L99:
+5407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1168              		.loc 1 5407 12 view .LVU367
+ 1169 0070 0120     		movs	r0, #1
+ 1170 0072 E7E7     		b	.L92
+ 1171              	.L101:
+ 1172              		.align	2
+ 1173              	.L100:
+ 1174 0074 00200080 		.word	-2147475456
+ 1175              		.cfi_endproc
+ 1176              	.LFE383:
+ 1178              		.section	.text.I2C_WaitOnSTOPFlagUntilTimeout,"ax",%progbits
+ 1179              		.align	1
+ 1180              		.syntax unified
+ 1181              		.thumb
+ 1182              		.thumb_func
+ 1184              	I2C_WaitOnSTOPFlagUntilTimeout:
+ 1185              	.LVL94:
+ 1186              	.LFB401:
+6439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ 1187              		.loc 1 6439 1 is_stmt 1 view -0
+ 1188              		.cfi_startproc
+ 1189              		@ args = 0, pretend = 0, frame = 0
+ 1190              		@ frame_needed = 0, uses_anonymous_args = 0
+6439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ 1191              		.loc 1 6439 1 is_stmt 0 view .LVU369
+ARM GAS  /tmp/ccbUHtu7.s 			page 147
+
+
+ 1192 0000 70B5     		push	{r4, r5, r6, lr}
+ 1193              	.LCFI13:
+ 1194              		.cfi_def_cfa_offset 16
+ 1195              		.cfi_offset 4, -16
+ 1196              		.cfi_offset 5, -12
+ 1197              		.cfi_offset 6, -8
+ 1198              		.cfi_offset 14, -4
+ 1199 0002 0546     		mov	r5, r0
+ 1200 0004 0C46     		mov	r4, r1
+ 1201 0006 1646     		mov	r6, r2
+6440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1202              		.loc 1 6440 3 is_stmt 1 view .LVU370
+ 1203              	.LVL95:
+ 1204              	.L103:
+6440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1205              		.loc 1 6440 51 view .LVU371
+6440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1206              		.loc 1 6440 10 is_stmt 0 view .LVU372
+ 1207 0008 2B68     		ldr	r3, [r5]
+ 1208 000a 9B69     		ldr	r3, [r3, #24]
+6440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1209              		.loc 1 6440 51 view .LVU373
+ 1210 000c 13F0200F 		tst	r3, #32
+ 1211 0010 1AD1     		bne	.L109
+6443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1212              		.loc 1 6443 5 is_stmt 1 view .LVU374
+6443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1213              		.loc 1 6443 9 is_stmt 0 view .LVU375
+ 1214 0012 3246     		mov	r2, r6
+ 1215 0014 2146     		mov	r1, r4
+ 1216 0016 2846     		mov	r0, r5
+ 1217 0018 FFF7FEFF 		bl	I2C_IsErrorOccurred
+ 1218              	.LVL96:
+6443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1219              		.loc 1 6443 8 view .LVU376
+ 1220 001c B0B9     		cbnz	r0, .L107
+6449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1221              		.loc 1 6449 5 is_stmt 1 view .LVU377
+6449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1222              		.loc 1 6449 11 is_stmt 0 view .LVU378
+ 1223 001e FFF7FEFF 		bl	HAL_GetTick
+ 1224              	.LVL97:
+6449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1225              		.loc 1 6449 25 view .LVU379
+ 1226 0022 801B     		subs	r0, r0, r6
+6449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1227              		.loc 1 6449 8 view .LVU380
+ 1228 0024 A042     		cmp	r0, r4
+ 1229 0026 01D8     		bhi	.L105
+6449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1230              		.loc 1 6449 49 discriminator 1 view .LVU381
+ 1231 0028 002C     		cmp	r4, #0
+ 1232 002a EDD1     		bne	.L103
+ 1233              	.L105:
+6451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State = HAL_I2C_STATE_READY;
+ 1234              		.loc 1 6451 7 is_stmt 1 view .LVU382
+6451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State = HAL_I2C_STATE_READY;
+ARM GAS  /tmp/ccbUHtu7.s 			page 148
+
+
+ 1235              		.loc 1 6451 11 is_stmt 0 view .LVU383
+ 1236 002c 6B6C     		ldr	r3, [r5, #68]
+6451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State = HAL_I2C_STATE_READY;
+ 1237              		.loc 1 6451 23 view .LVU384
+ 1238 002e 43F02003 		orr	r3, r3, #32
+ 1239 0032 6B64     		str	r3, [r5, #68]
+6452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1240              		.loc 1 6452 7 is_stmt 1 view .LVU385
+6452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1241              		.loc 1 6452 19 is_stmt 0 view .LVU386
+ 1242 0034 2023     		movs	r3, #32
+ 1243 0036 85F84130 		strb	r3, [r5, #65]
+6453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1244              		.loc 1 6453 7 is_stmt 1 view .LVU387
+6453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1245              		.loc 1 6453 18 is_stmt 0 view .LVU388
+ 1246 003a 0023     		movs	r3, #0
+ 1247 003c 85F84230 		strb	r3, [r5, #66]
+6456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1248              		.loc 1 6456 7 is_stmt 1 view .LVU389
+6456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1249              		.loc 1 6456 7 view .LVU390
+ 1250 0040 85F84030 		strb	r3, [r5, #64]
+6456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1251              		.loc 1 6456 7 view .LVU391
+6458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 1252              		.loc 1 6458 7 view .LVU392
+6458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 1253              		.loc 1 6458 14 is_stmt 0 view .LVU393
+ 1254 0044 0120     		movs	r0, #1
+ 1255              	.L104:
+6462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1256              		.loc 1 6462 1 view .LVU394
+ 1257 0046 70BD     		pop	{r4, r5, r6, pc}
+ 1258              	.LVL98:
+ 1259              	.L109:
+6461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 1260              		.loc 1 6461 10 view .LVU395
+ 1261 0048 0020     		movs	r0, #0
+ 1262 004a FCE7     		b	.L104
+ 1263              	.L107:
+6445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 1264              		.loc 1 6445 14 view .LVU396
+ 1265 004c 0120     		movs	r0, #1
+ 1266 004e FAE7     		b	.L104
+ 1267              		.cfi_endproc
+ 1268              	.LFE401:
+ 1270              		.section	.text.I2C_WaitOnRXNEFlagUntilTimeout,"ax",%progbits
+ 1271              		.align	1
+ 1272              		.syntax unified
+ 1273              		.thumb
+ 1274              		.thumb_func
+ 1276              	I2C_WaitOnRXNEFlagUntilTimeout:
+ 1277              	.LVL99:
+ 1278              	.LFB402:
+6474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ 1279              		.loc 1 6474 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccbUHtu7.s 			page 149
+
+
+ 1280              		.cfi_startproc
+ 1281              		@ args = 0, pretend = 0, frame = 0
+ 1282              		@ frame_needed = 0, uses_anonymous_args = 0
+6474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ 1283              		.loc 1 6474 1 is_stmt 0 view .LVU398
+ 1284 0000 70B5     		push	{r4, r5, r6, lr}
+ 1285              	.LCFI14:
+ 1286              		.cfi_def_cfa_offset 16
+ 1287              		.cfi_offset 4, -16
+ 1288              		.cfi_offset 5, -12
+ 1289              		.cfi_offset 6, -8
+ 1290              		.cfi_offset 14, -4
+ 1291 0002 0446     		mov	r4, r0
+ 1292 0004 0D46     		mov	r5, r1
+ 1293 0006 1646     		mov	r6, r2
+6475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1294              		.loc 1 6475 3 is_stmt 1 view .LVU399
+ 1295              	.LVL100:
+ 1296              	.L111:
+6475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1297              		.loc 1 6475 50 view .LVU400
+6475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1298              		.loc 1 6475 10 is_stmt 0 view .LVU401
+ 1299 0008 2368     		ldr	r3, [r4]
+ 1300 000a 9B69     		ldr	r3, [r3, #24]
+6475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1301              		.loc 1 6475 50 view .LVU402
+ 1302 000c 13F0040F 		tst	r3, #4
+ 1303 0010 49D1     		bne	.L121
+6478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1304              		.loc 1 6478 5 is_stmt 1 view .LVU403
+6478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1305              		.loc 1 6478 9 is_stmt 0 view .LVU404
+ 1306 0012 3246     		mov	r2, r6
+ 1307 0014 2946     		mov	r1, r5
+ 1308 0016 2046     		mov	r0, r4
+ 1309 0018 FFF7FEFF 		bl	I2C_IsErrorOccurred
+ 1310              	.LVL101:
+6478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1311              		.loc 1 6478 8 view .LVU405
+ 1312 001c 0146     		mov	r1, r0
+ 1313 001e 0028     		cmp	r0, #0
+ 1314 0020 43D1     		bne	.L119
+6484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1315              		.loc 1 6484 5 is_stmt 1 view .LVU406
+6484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1316              		.loc 1 6484 9 is_stmt 0 view .LVU407
+ 1317 0022 2368     		ldr	r3, [r4]
+ 1318 0024 9A69     		ldr	r2, [r3, #24]
+6484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1319              		.loc 1 6484 8 view .LVU408
+ 1320 0026 12F0200F 		tst	r2, #32
+ 1321 002a 13D1     		bne	.L122
+6523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1322              		.loc 1 6523 5 is_stmt 1 view .LVU409
+6523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1323              		.loc 1 6523 11 is_stmt 0 view .LVU410
+ARM GAS  /tmp/ccbUHtu7.s 			page 150
+
+
+ 1324 002c FFF7FEFF 		bl	HAL_GetTick
+ 1325              	.LVL102:
+6523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1326              		.loc 1 6523 25 view .LVU411
+ 1327 0030 801B     		subs	r0, r0, r6
+6523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1328              		.loc 1 6523 8 view .LVU412
+ 1329 0032 A842     		cmp	r0, r5
+ 1330 0034 01D8     		bhi	.L117
+6523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1331              		.loc 1 6523 49 discriminator 1 view .LVU413
+ 1332 0036 002D     		cmp	r5, #0
+ 1333 0038 E6D1     		bne	.L111
+ 1334              	.L117:
+6525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State = HAL_I2C_STATE_READY;
+ 1335              		.loc 1 6525 7 is_stmt 1 view .LVU414
+6525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State = HAL_I2C_STATE_READY;
+ 1336              		.loc 1 6525 11 is_stmt 0 view .LVU415
+ 1337 003a 636C     		ldr	r3, [r4, #68]
+6525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->State = HAL_I2C_STATE_READY;
+ 1338              		.loc 1 6525 23 view .LVU416
+ 1339 003c 43F02003 		orr	r3, r3, #32
+ 1340 0040 6364     		str	r3, [r4, #68]
+6526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1341              		.loc 1 6526 7 is_stmt 1 view .LVU417
+6526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1342              		.loc 1 6526 19 is_stmt 0 view .LVU418
+ 1343 0042 2023     		movs	r3, #32
+ 1344 0044 84F84130 		strb	r3, [r4, #65]
+6529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1345              		.loc 1 6529 7 is_stmt 1 view .LVU419
+6529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1346              		.loc 1 6529 7 view .LVU420
+ 1347 0048 0023     		movs	r3, #0
+ 1348 004a 84F84030 		strb	r3, [r4, #64]
+6529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1349              		.loc 1 6529 7 view .LVU421
+6531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 1350              		.loc 1 6531 7 view .LVU422
+6531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 1351              		.loc 1 6531 14 is_stmt 0 view .LVU423
+ 1352 004e 0121     		movs	r1, #1
+ 1353              	.L112:
+6535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1354              		.loc 1 6535 1 view .LVU424
+ 1355 0050 0846     		mov	r0, r1
+ 1356 0052 70BD     		pop	{r4, r5, r6, pc}
+ 1357              	.LVL103:
+ 1358              	.L122:
+6488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 1359              		.loc 1 6488 7 is_stmt 1 view .LVU425
+6488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 1360              		.loc 1 6488 12 is_stmt 0 view .LVU426
+ 1361 0054 9A69     		ldr	r2, [r3, #24]
+6488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 1362              		.loc 1 6488 10 view .LVU427
+ 1363 0056 12F0040F 		tst	r2, #4
+ARM GAS  /tmp/ccbUHtu7.s 			page 151
+
+
+ 1364 005a 02D0     		beq	.L114
+6488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 1365              		.loc 1 6488 68 discriminator 1 view .LVU428
+ 1366 005c 228D     		ldrh	r2, [r4, #40]
+6488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 1367              		.loc 1 6488 60 discriminator 1 view .LVU429
+ 1368 005e 002A     		cmp	r2, #0
+ 1369 0060 F6D1     		bne	.L112
+ 1370              	.L114:
+6496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 1371              		.loc 1 6496 9 is_stmt 1 view .LVU430
+6496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 1372              		.loc 1 6496 13 is_stmt 0 view .LVU431
+ 1373 0062 9A69     		ldr	r2, [r3, #24]
+6496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 1374              		.loc 1 6496 12 view .LVU432
+ 1375 0064 12F0100F 		tst	r2, #16
+ 1376 0068 1AD0     		beq	.L115
+6498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ 1377              		.loc 1 6498 11 is_stmt 1 view .LVU433
+ 1378 006a 1022     		movs	r2, #16
+ 1379 006c DA61     		str	r2, [r3, #28]
+6499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 1380              		.loc 1 6499 11 view .LVU434
+6499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 1381              		.loc 1 6499 27 is_stmt 0 view .LVU435
+ 1382 006e 0423     		movs	r3, #4
+ 1383 0070 6364     		str	r3, [r4, #68]
+ 1384              	.L116:
+6507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1385              		.loc 1 6507 9 is_stmt 1 view .LVU436
+ 1386 0072 2368     		ldr	r3, [r4]
+ 1387 0074 2022     		movs	r2, #32
+ 1388 0076 DA61     		str	r2, [r3, #28]
+6510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1389              		.loc 1 6510 9 view .LVU437
+ 1390 0078 2168     		ldr	r1, [r4]
+ 1391 007a 4B68     		ldr	r3, [r1, #4]
+ 1392 007c 23F0FF73 		bic	r3, r3, #33423360
+ 1393 0080 23F48B33 		bic	r3, r3, #71168
+ 1394 0084 23F4FF73 		bic	r3, r3, #510
+ 1395 0088 23F00103 		bic	r3, r3, #1
+ 1396 008c 4B60     		str	r3, [r1, #4]
+6512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1397              		.loc 1 6512 9 view .LVU438
+6512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1398              		.loc 1 6512 21 is_stmt 0 view .LVU439
+ 1399 008e 84F84120 		strb	r2, [r4, #65]
+6513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1400              		.loc 1 6513 9 is_stmt 1 view .LVU440
+6513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1401              		.loc 1 6513 20 is_stmt 0 view .LVU441
+ 1402 0092 0023     		movs	r3, #0
+ 1403 0094 84F84230 		strb	r3, [r4, #66]
+6516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1404              		.loc 1 6516 9 is_stmt 1 view .LVU442
+6516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 152
+
+
+ 1405              		.loc 1 6516 9 view .LVU443
+ 1406 0098 84F84030 		strb	r3, [r4, #64]
+6516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1407              		.loc 1 6516 9 view .LVU444
+6518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 1408              		.loc 1 6518 9 view .LVU445
+6518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 1409              		.loc 1 6518 16 is_stmt 0 view .LVU446
+ 1410 009c 0121     		movs	r1, #1
+ 1411 009e D7E7     		b	.L112
+ 1412              	.L115:
+6503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 1413              		.loc 1 6503 11 is_stmt 1 view .LVU447
+6503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 1414              		.loc 1 6503 27 is_stmt 0 view .LVU448
+ 1415 00a0 0023     		movs	r3, #0
+ 1416 00a2 6364     		str	r3, [r4, #68]
+ 1417 00a4 E5E7     		b	.L116
+ 1418              	.L121:
+6534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 1419              		.loc 1 6534 10 view .LVU449
+ 1420 00a6 0021     		movs	r1, #0
+ 1421 00a8 D2E7     		b	.L112
+ 1422              	.L119:
+6480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 1423              		.loc 1 6480 14 view .LVU450
+ 1424 00aa 0121     		movs	r1, #1
+ 1425 00ac D0E7     		b	.L112
+ 1426              		.cfi_endproc
+ 1427              	.LFE402:
+ 1429              		.section	.text.HAL_I2C_MspInit,"ax",%progbits
+ 1430              		.align	1
+ 1431              		.weak	HAL_I2C_MspInit
+ 1432              		.syntax unified
+ 1433              		.thumb
+ 1434              		.thumb_func
+ 1436              	HAL_I2C_MspInit:
+ 1437              	.LVL104:
+ 1438              	.LFB331:
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 1439              		.loc 1 681 1 is_stmt 1 view -0
+ 1440              		.cfi_startproc
+ 1441              		@ args = 0, pretend = 0, frame = 0
+ 1442              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1443              		@ link register save eliminated.
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1444              		.loc 1 683 3 view .LVU452
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1445              		.loc 1 688 1 is_stmt 0 view .LVU453
+ 1446 0000 7047     		bx	lr
+ 1447              		.cfi_endproc
+ 1448              	.LFE331:
+ 1450              		.section	.text.HAL_I2C_Init,"ax",%progbits
+ 1451              		.align	1
+ 1452              		.global	HAL_I2C_Init
+ 1453              		.syntax unified
+ 1454              		.thumb
+ARM GAS  /tmp/ccbUHtu7.s 			page 153
+
+
+ 1455              		.thumb_func
+ 1457              	HAL_I2C_Init:
+ 1458              	.LVL105:
+ 1459              	.LFB329:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the I2C handle allocation */
+ 1460              		.loc 1 525 1 is_stmt 1 view -0
+ 1461              		.cfi_startproc
+ 1462              		@ args = 0, pretend = 0, frame = 0
+ 1463              		@ frame_needed = 0, uses_anonymous_args = 0
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1464              		.loc 1 527 3 view .LVU455
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1465              		.loc 1 527 6 is_stmt 0 view .LVU456
+ 1466 0000 0028     		cmp	r0, #0
+ 1467 0002 59D0     		beq	.L130
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the I2C handle allocation */
+ 1468              		.loc 1 525 1 view .LVU457
+ 1469 0004 10B5     		push	{r4, lr}
+ 1470              	.LCFI15:
+ 1471              		.cfi_def_cfa_offset 8
+ 1472              		.cfi_offset 4, -8
+ 1473              		.cfi_offset 14, -4
+ 1474 0006 0446     		mov	r4, r0
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+ 1475              		.loc 1 533 3 is_stmt 1 view .LVU458
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+ 1476              		.loc 1 534 3 view .LVU459
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+ 1477              		.loc 1 535 3 view .LVU460
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+ 1478              		.loc 1 536 3 view .LVU461
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+ 1479              		.loc 1 537 3 view .LVU462
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+ 1480              		.loc 1 538 3 view .LVU463
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+ 1481              		.loc 1 539 3 view .LVU464
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1482              		.loc 1 540 3 view .LVU465
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1483              		.loc 1 542 3 view .LVU466
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1484              		.loc 1 542 11 is_stmt 0 view .LVU467
+ 1485 0008 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1486              		.loc 1 542 6 view .LVU468
+ 1487 000c 002B     		cmp	r3, #0
+ 1488 000e 43D0     		beq	.L135
+ 1489              	.LVL106:
+ 1490              	.L126:
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1491              		.loc 1 573 3 is_stmt 1 view .LVU469
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1492              		.loc 1 573 15 is_stmt 0 view .LVU470
+ 1493 0010 2423     		movs	r3, #36
+ 1494 0012 84F84130 		strb	r3, [r4, #65]
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 154
+
+
+ 1495              		.loc 1 576 3 is_stmt 1 view .LVU471
+ 1496 0016 2268     		ldr	r2, [r4]
+ 1497 0018 1368     		ldr	r3, [r2]
+ 1498 001a 23F00103 		bic	r3, r3, #1
+ 1499 001e 1360     		str	r3, [r2]
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1500              		.loc 1 580 3 view .LVU472
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1501              		.loc 1 580 39 is_stmt 0 view .LVU473
+ 1502 0020 6368     		ldr	r3, [r4, #4]
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1503              		.loc 1 580 7 view .LVU474
+ 1504 0022 2268     		ldr	r2, [r4]
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1505              		.loc 1 580 47 view .LVU475
+ 1506 0024 23F07063 		bic	r3, r3, #251658240
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1507              		.loc 1 580 27 view .LVU476
+ 1508 0028 1361     		str	r3, [r2, #16]
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1509              		.loc 1 584 3 is_stmt 1 view .LVU477
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1510              		.loc 1 584 7 is_stmt 0 view .LVU478
+ 1511 002a 2268     		ldr	r2, [r4]
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1512              		.loc 1 584 17 view .LVU479
+ 1513 002c 9368     		ldr	r3, [r2, #8]
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1514              		.loc 1 584 24 view .LVU480
+ 1515 002e 23F40043 		bic	r3, r3, #32768
+ 1516 0032 9360     		str	r3, [r2, #8]
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1517              		.loc 1 587 3 is_stmt 1 view .LVU481
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1518              		.loc 1 587 17 is_stmt 0 view .LVU482
+ 1519 0034 E368     		ldr	r3, [r4, #12]
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1520              		.loc 1 587 6 view .LVU483
+ 1521 0036 012B     		cmp	r3, #1
+ 1522 0038 33D0     		beq	.L136
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1523              		.loc 1 593 5 is_stmt 1 view .LVU484
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1524              		.loc 1 593 75 is_stmt 0 view .LVU485
+ 1525 003a A368     		ldr	r3, [r4, #8]
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1526              		.loc 1 593 9 view .LVU486
+ 1527 003c 2268     		ldr	r2, [r4]
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1528              		.loc 1 593 63 view .LVU487
+ 1529 003e 43F40443 		orr	r3, r3, #33792
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1530              		.loc 1 593 26 view .LVU488
+ 1531 0042 9360     		str	r3, [r2, #8]
+ 1532              	.L128:
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1533              		.loc 1 598 3 is_stmt 1 view .LVU489
+ARM GAS  /tmp/ccbUHtu7.s 			page 155
+
+
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1534              		.loc 1 598 17 is_stmt 0 view .LVU490
+ 1535 0044 E368     		ldr	r3, [r4, #12]
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1536              		.loc 1 598 6 view .LVU491
+ 1537 0046 022B     		cmp	r3, #2
+ 1538 0048 31D0     		beq	.L137
+ 1539              	.L129:
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1540              		.loc 1 603 3 is_stmt 1 view .LVU492
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1541              		.loc 1 603 7 is_stmt 0 view .LVU493
+ 1542 004a 2268     		ldr	r2, [r4]
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1543              		.loc 1 603 17 view .LVU494
+ 1544 004c 5368     		ldr	r3, [r2, #4]
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1545              		.loc 1 603 23 view .LVU495
+ 1546 004e 43F00073 		orr	r3, r3, #33554432
+ 1547 0052 43F40043 		orr	r3, r3, #32768
+ 1548 0056 5360     		str	r3, [r2, #4]
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1549              		.loc 1 607 3 is_stmt 1 view .LVU496
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1550              		.loc 1 607 7 is_stmt 0 view .LVU497
+ 1551 0058 2268     		ldr	r2, [r4]
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1552              		.loc 1 607 17 view .LVU498
+ 1553 005a D368     		ldr	r3, [r2, #12]
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1554              		.loc 1 607 24 view .LVU499
+ 1555 005c 23F40043 		bic	r3, r3, #32768
+ 1556 0060 D360     		str	r3, [r2, #12]
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1557              		.loc 1 610 3 is_stmt 1 view .LVU500
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1558              		.loc 1 610 37 is_stmt 0 view .LVU501
+ 1559 0062 2369     		ldr	r3, [r4, #16]
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1560              		.loc 1 610 66 view .LVU502
+ 1561 0064 6269     		ldr	r2, [r4, #20]
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1562              		.loc 1 610 54 view .LVU503
+ 1563 0066 1343     		orrs	r3, r3, r2
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1564              		.loc 1 611 38 view .LVU504
+ 1565 0068 A169     		ldr	r1, [r4, #24]
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1566              		.loc 1 610 7 view .LVU505
+ 1567 006a 2268     		ldr	r2, [r4]
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1568              		.loc 1 610 79 view .LVU506
+ 1569 006c 43EA0123 		orr	r3, r3, r1, lsl #8
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1570              		.loc 1 610 24 view .LVU507
+ 1571 0070 D360     		str	r3, [r2, #12]
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 156
+
+
+ 1572              		.loc 1 615 3 is_stmt 1 view .LVU508
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1573              		.loc 1 615 36 is_stmt 0 view .LVU509
+ 1574 0072 E369     		ldr	r3, [r4, #28]
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1575              		.loc 1 615 65 view .LVU510
+ 1576 0074 216A     		ldr	r1, [r4, #32]
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1577              		.loc 1 615 7 view .LVU511
+ 1578 0076 2268     		ldr	r2, [r4]
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1579              		.loc 1 615 53 view .LVU512
+ 1580 0078 0B43     		orrs	r3, r3, r1
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1581              		.loc 1 615 23 view .LVU513
+ 1582 007a 1360     		str	r3, [r2]
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1583              		.loc 1 618 3 is_stmt 1 view .LVU514
+ 1584 007c 2268     		ldr	r2, [r4]
+ 1585 007e 1368     		ldr	r3, [r2]
+ 1586 0080 43F00103 		orr	r3, r3, #1
+ 1587 0084 1360     		str	r3, [r2]
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_READY;
+ 1588              		.loc 1 620 3 view .LVU515
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_READY;
+ 1589              		.loc 1 620 19 is_stmt 0 view .LVU516
+ 1590 0086 0020     		movs	r0, #0
+ 1591 0088 6064     		str	r0, [r4, #68]
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 1592              		.loc 1 621 3 is_stmt 1 view .LVU517
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 1593              		.loc 1 621 15 is_stmt 0 view .LVU518
+ 1594 008a 2023     		movs	r3, #32
+ 1595 008c 84F84130 		strb	r3, [r4, #65]
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1596              		.loc 1 622 3 is_stmt 1 view .LVU519
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1597              		.loc 1 622 23 is_stmt 0 view .LVU520
+ 1598 0090 2063     		str	r0, [r4, #48]
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1599              		.loc 1 623 3 is_stmt 1 view .LVU521
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1600              		.loc 1 623 14 is_stmt 0 view .LVU522
+ 1601 0092 84F84200 		strb	r0, [r4, #66]
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 1602              		.loc 1 625 3 is_stmt 1 view .LVU523
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1603              		.loc 1 626 1 is_stmt 0 view .LVU524
+ 1604 0096 10BD     		pop	{r4, pc}
+ 1605              	.LVL107:
+ 1606              	.L135:
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1607              		.loc 1 545 5 is_stmt 1 view .LVU525
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1608              		.loc 1 545 16 is_stmt 0 view .LVU526
+ 1609 0098 80F84030 		strb	r3, [r0, #64]
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ARM GAS  /tmp/ccbUHtu7.s 			page 157
+
+
+ 1610              		.loc 1 569 5 is_stmt 1 view .LVU527
+ 1611 009c FFF7FEFF 		bl	HAL_I2C_MspInit
+ 1612              	.LVL108:
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 1613              		.loc 1 569 5 is_stmt 0 view .LVU528
+ 1614 00a0 B6E7     		b	.L126
+ 1615              	.L136:
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1616              		.loc 1 589 5 is_stmt 1 view .LVU529
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1617              		.loc 1 589 56 is_stmt 0 view .LVU530
+ 1618 00a2 A368     		ldr	r3, [r4, #8]
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1619              		.loc 1 589 9 view .LVU531
+ 1620 00a4 2268     		ldr	r2, [r4]
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1621              		.loc 1 589 44 view .LVU532
+ 1622 00a6 43F40043 		orr	r3, r3, #32768
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1623              		.loc 1 589 26 view .LVU533
+ 1624 00aa 9360     		str	r3, [r2, #8]
+ 1625 00ac CAE7     		b	.L128
+ 1626              	.L137:
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1627              		.loc 1 600 5 is_stmt 1 view .LVU534
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1628              		.loc 1 600 9 is_stmt 0 view .LVU535
+ 1629 00ae 2368     		ldr	r3, [r4]
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1630              		.loc 1 600 25 view .LVU536
+ 1631 00b0 4FF40062 		mov	r2, #2048
+ 1632 00b4 5A60     		str	r2, [r3, #4]
+ 1633 00b6 C8E7     		b	.L129
+ 1634              	.LVL109:
+ 1635              	.L130:
+ 1636              	.LCFI16:
+ 1637              		.cfi_def_cfa_offset 0
+ 1638              		.cfi_restore 4
+ 1639              		.cfi_restore 14
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1640              		.loc 1 529 12 view .LVU537
+ 1641 00b8 0120     		movs	r0, #1
+ 1642              	.LVL110:
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1643              		.loc 1 626 1 view .LVU538
+ 1644 00ba 7047     		bx	lr
+ 1645              		.cfi_endproc
+ 1646              	.LFE329:
+ 1648              		.section	.text.HAL_I2C_MspDeInit,"ax",%progbits
+ 1649              		.align	1
+ 1650              		.weak	HAL_I2C_MspDeInit
+ 1651              		.syntax unified
+ 1652              		.thumb
+ 1653              		.thumb_func
+ 1655              	HAL_I2C_MspDeInit:
+ 1656              	.LVL111:
+ 1657              	.LFB332:
+ARM GAS  /tmp/ccbUHtu7.s 			page 158
+
+
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 1658              		.loc 1 697 1 is_stmt 1 view -0
+ 1659              		.cfi_startproc
+ 1660              		@ args = 0, pretend = 0, frame = 0
+ 1661              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1662              		@ link register save eliminated.
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1663              		.loc 1 699 3 view .LVU540
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1664              		.loc 1 704 1 is_stmt 0 view .LVU541
+ 1665 0000 7047     		bx	lr
+ 1666              		.cfi_endproc
+ 1667              	.LFE332:
+ 1669              		.section	.text.HAL_I2C_DeInit,"ax",%progbits
+ 1670              		.align	1
+ 1671              		.global	HAL_I2C_DeInit
+ 1672              		.syntax unified
+ 1673              		.thumb
+ 1674              		.thumb_func
+ 1676              	HAL_I2C_DeInit:
+ 1677              	.LVL112:
+ 1678              	.LFB330:
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the I2C handle allocation */
+ 1679              		.loc 1 635 1 is_stmt 1 view -0
+ 1680              		.cfi_startproc
+ 1681              		@ args = 0, pretend = 0, frame = 0
+ 1682              		@ frame_needed = 0, uses_anonymous_args = 0
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1683              		.loc 1 637 3 view .LVU543
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1684              		.loc 1 637 6 is_stmt 0 view .LVU544
+ 1685 0000 A8B1     		cbz	r0, .L141
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the I2C handle allocation */
+ 1686              		.loc 1 635 1 view .LVU545
+ 1687 0002 10B5     		push	{r4, lr}
+ 1688              	.LCFI17:
+ 1689              		.cfi_def_cfa_offset 8
+ 1690              		.cfi_offset 4, -8
+ 1691              		.cfi_offset 14, -4
+ 1692 0004 0446     		mov	r4, r0
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1693              		.loc 1 643 3 is_stmt 1 view .LVU546
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1694              		.loc 1 645 3 view .LVU547
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1695              		.loc 1 645 15 is_stmt 0 view .LVU548
+ 1696 0006 2423     		movs	r3, #36
+ 1697 0008 80F84130 		strb	r3, [r0, #65]
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1698              		.loc 1 648 3 is_stmt 1 view .LVU549
+ 1699 000c 0268     		ldr	r2, [r0]
+ 1700 000e 1368     		ldr	r3, [r2]
+ 1701 0010 23F00103 		bic	r3, r3, #1
+ 1702 0014 1360     		str	r3, [r2]
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 1703              		.loc 1 660 3 view .LVU550
+ 1704 0016 FFF7FEFF 		bl	HAL_I2C_MspDeInit
+ARM GAS  /tmp/ccbUHtu7.s 			page 159
+
+
+ 1705              	.LVL113:
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_RESET;
+ 1706              		.loc 1 663 3 view .LVU551
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_RESET;
+ 1707              		.loc 1 663 19 is_stmt 0 view .LVU552
+ 1708 001a 0020     		movs	r0, #0
+ 1709 001c 6064     		str	r0, [r4, #68]
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 1710              		.loc 1 664 3 is_stmt 1 view .LVU553
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 1711              		.loc 1 664 15 is_stmt 0 view .LVU554
+ 1712 001e 84F84100 		strb	r0, [r4, #65]
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1713              		.loc 1 665 3 is_stmt 1 view .LVU555
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1714              		.loc 1 665 23 is_stmt 0 view .LVU556
+ 1715 0022 2063     		str	r0, [r4, #48]
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1716              		.loc 1 666 3 is_stmt 1 view .LVU557
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1717              		.loc 1 666 14 is_stmt 0 view .LVU558
+ 1718 0024 84F84200 		strb	r0, [r4, #66]
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1719              		.loc 1 669 3 is_stmt 1 view .LVU559
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1720              		.loc 1 669 3 view .LVU560
+ 1721 0028 84F84000 		strb	r0, [r4, #64]
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1722              		.loc 1 669 3 view .LVU561
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 1723              		.loc 1 671 3 view .LVU562
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1724              		.loc 1 672 1 is_stmt 0 view .LVU563
+ 1725 002c 10BD     		pop	{r4, pc}
+ 1726              	.LVL114:
+ 1727              	.L141:
+ 1728              	.LCFI18:
+ 1729              		.cfi_def_cfa_offset 0
+ 1730              		.cfi_restore 4
+ 1731              		.cfi_restore 14
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 1732              		.loc 1 639 12 view .LVU564
+ 1733 002e 0120     		movs	r0, #1
+ 1734              	.LVL115:
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1735              		.loc 1 672 1 view .LVU565
+ 1736 0030 7047     		bx	lr
+ 1737              		.cfi_endproc
+ 1738              	.LFE330:
+ 1740              		.section	.text.HAL_I2C_Master_Transmit,"ax",%progbits
+ 1741              		.align	1
+ 1742              		.global	HAL_I2C_Master_Transmit
+ 1743              		.syntax unified
+ 1744              		.thumb
+ 1745              		.thumb_func
+ 1747              	HAL_I2C_Master_Transmit:
+ 1748              	.LVL116:
+ARM GAS  /tmp/ccbUHtu7.s 			page 160
+
+
+ 1749              	.LFB333:
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 1750              		.loc 1 1119 1 is_stmt 1 view -0
+ 1751              		.cfi_startproc
+ 1752              		@ args = 4, pretend = 0, frame = 0
+ 1753              		@ frame_needed = 0, uses_anonymous_args = 0
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 1754              		.loc 1 1119 1 is_stmt 0 view .LVU567
+ 1755 0000 2DE9F047 		push	{r4, r5, r6, r7, r8, r9, r10, lr}
+ 1756              	.LCFI19:
+ 1757              		.cfi_def_cfa_offset 32
+ 1758              		.cfi_offset 4, -32
+ 1759              		.cfi_offset 5, -28
+ 1760              		.cfi_offset 6, -24
+ 1761              		.cfi_offset 7, -20
+ 1762              		.cfi_offset 8, -16
+ 1763              		.cfi_offset 9, -12
+ 1764              		.cfi_offset 10, -8
+ 1765              		.cfi_offset 14, -4
+ 1766 0004 82B0     		sub	sp, sp, #8
+ 1767              	.LCFI20:
+ 1768              		.cfi_def_cfa_offset 40
+ 1769 0006 0F46     		mov	r7, r1
+ 1770 0008 0A9E     		ldr	r6, [sp, #40]
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1771              		.loc 1 1120 3 is_stmt 1 view .LVU568
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1772              		.loc 1 1122 3 view .LVU569
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1773              		.loc 1 1122 11 is_stmt 0 view .LVU570
+ 1774 000a 90F84110 		ldrb	r1, [r0, #65]	@ zero_extendqisi2
+ 1775              	.LVL117:
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1776              		.loc 1 1122 11 view .LVU571
+ 1777 000e C9B2     		uxtb	r1, r1
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 1778              		.loc 1 1122 6 view .LVU572
+ 1779 0010 2029     		cmp	r1, #32
+ 1780 0012 40F0A380 		bne	.L154
+ 1781 0016 0446     		mov	r4, r0
+ 1782 0018 9046     		mov	r8, r2
+ 1783 001a 9946     		mov	r9, r3
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1784              		.loc 1 1125 5 is_stmt 1 view .LVU573
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1785              		.loc 1 1125 5 view .LVU574
+ 1786 001c 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 1787              	.LVL118:
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1788              		.loc 1 1125 5 is_stmt 0 view .LVU575
+ 1789 0020 012B     		cmp	r3, #1
+ 1790 0022 00F09F80 		beq	.L155
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1791              		.loc 1 1125 5 is_stmt 1 discriminator 2 view .LVU576
+ 1792 0026 4FF0010A 		mov	r10, #1
+ 1793 002a 80F840A0 		strb	r10, [r0, #64]
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 161
+
+
+ 1794              		.loc 1 1125 5 discriminator 2 view .LVU577
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1795              		.loc 1 1128 5 discriminator 2 view .LVU578
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1796              		.loc 1 1128 17 is_stmt 0 discriminator 2 view .LVU579
+ 1797 002e FFF7FEFF 		bl	HAL_GetTick
+ 1798              	.LVL119:
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1799              		.loc 1 1128 17 discriminator 2 view .LVU580
+ 1800 0032 0546     		mov	r5, r0
+ 1801              	.LVL120:
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1802              		.loc 1 1130 5 is_stmt 1 discriminator 2 view .LVU581
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1803              		.loc 1 1130 9 is_stmt 0 discriminator 2 view .LVU582
+ 1804 0034 0090     		str	r0, [sp]
+ 1805 0036 1923     		movs	r3, #25
+ 1806 0038 5246     		mov	r2, r10
+ 1807 003a 4FF40041 		mov	r1, #32768
+ 1808 003e 2046     		mov	r0, r4
+ 1809              	.LVL121:
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1810              		.loc 1 1130 9 discriminator 2 view .LVU583
+ 1811 0040 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 1812              	.LVL122:
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1813              		.loc 1 1130 8 discriminator 2 view .LVU584
+ 1814 0044 0028     		cmp	r0, #0
+ 1815 0046 40F08F80 		bne	.L156
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 1816              		.loc 1 1135 5 is_stmt 1 view .LVU585
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 1817              		.loc 1 1135 21 is_stmt 0 view .LVU586
+ 1818 004a 2123     		movs	r3, #33
+ 1819 004c 84F84130 		strb	r3, [r4, #65]
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 1820              		.loc 1 1136 5 is_stmt 1 view .LVU587
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 1821              		.loc 1 1136 21 is_stmt 0 view .LVU588
+ 1822 0050 1023     		movs	r3, #16
+ 1823 0052 84F84230 		strb	r3, [r4, #66]
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1824              		.loc 1 1137 5 is_stmt 1 view .LVU589
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1825              		.loc 1 1137 21 is_stmt 0 view .LVU590
+ 1826 0056 0023     		movs	r3, #0
+ 1827 0058 6364     		str	r3, [r4, #68]
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 1828              		.loc 1 1140 5 is_stmt 1 view .LVU591
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 1829              		.loc 1 1140 21 is_stmt 0 view .LVU592
+ 1830 005a C4F82480 		str	r8, [r4, #36]
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 1831              		.loc 1 1141 5 is_stmt 1 view .LVU593
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 1832              		.loc 1 1141 21 is_stmt 0 view .LVU594
+ 1833 005e A4F82A90 		strh	r9, [r4, #42]	@ movhi
+ARM GAS  /tmp/ccbUHtu7.s 			page 162
+
+
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1834              		.loc 1 1142 5 is_stmt 1 view .LVU595
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1835              		.loc 1 1142 21 is_stmt 0 view .LVU596
+ 1836 0062 6363     		str	r3, [r4, #52]
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1837              		.loc 1 1146 5 is_stmt 1 view .LVU597
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1838              		.loc 1 1146 13 is_stmt 0 view .LVU598
+ 1839 0064 638D     		ldrh	r3, [r4, #42]
+ 1840 0066 9BB2     		uxth	r3, r3
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1841              		.loc 1 1146 8 view .LVU599
+ 1842 0068 FF2B     		cmp	r3, #255
+ 1843 006a 0AD9     		bls	.L148
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 1844              		.loc 1 1148 7 is_stmt 1 view .LVU600
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 1845              		.loc 1 1148 22 is_stmt 0 view .LVU601
+ 1846 006c FF22     		movs	r2, #255
+ 1847 006e 2285     		strh	r2, [r4, #40]	@ movhi
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 1848              		.loc 1 1149 7 is_stmt 1 view .LVU602
+ 1849 0070 414B     		ldr	r3, .L162
+ 1850 0072 0093     		str	r3, [sp]
+ 1851 0074 4FF08073 		mov	r3, #16777216
+ 1852 0078 3946     		mov	r1, r7
+ 1853 007a 2046     		mov	r0, r4
+ 1854 007c FFF7FEFF 		bl	I2C_TransferConfig
+ 1855              	.LVL123:
+ 1856 0080 18E0     		b	.L150
+ 1857              	.L148:
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 1858              		.loc 1 1154 7 view .LVU603
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 1859              		.loc 1 1154 28 is_stmt 0 view .LVU604
+ 1860 0082 628D     		ldrh	r2, [r4, #42]
+ 1861 0084 92B2     		uxth	r2, r2
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 1862              		.loc 1 1154 22 view .LVU605
+ 1863 0086 2285     		strh	r2, [r4, #40]	@ movhi
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 1864              		.loc 1 1155 7 is_stmt 1 view .LVU606
+ 1865 0088 3B4B     		ldr	r3, .L162
+ 1866 008a 0093     		str	r3, [sp]
+ 1867 008c 4FF00073 		mov	r3, #33554432
+ 1868 0090 D2B2     		uxtb	r2, r2
+ 1869 0092 3946     		mov	r1, r7
+ 1870 0094 2046     		mov	r0, r4
+ 1871 0096 FFF7FEFF 		bl	I2C_TransferConfig
+ 1872              	.LVL124:
+ 1873 009a 0BE0     		b	.L150
+ 1874              	.L152:
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 1875              		.loc 1 1191 11 view .LVU607
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 1876              		.loc 1 1191 32 is_stmt 0 view .LVU608
+ARM GAS  /tmp/ccbUHtu7.s 			page 163
+
+
+ 1877 009c 628D     		ldrh	r2, [r4, #42]
+ 1878 009e 92B2     		uxth	r2, r2
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 1879              		.loc 1 1191 26 view .LVU609
+ 1880 00a0 2285     		strh	r2, [r4, #40]	@ movhi
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 1881              		.loc 1 1192 11 is_stmt 1 view .LVU610
+ 1882 00a2 0023     		movs	r3, #0
+ 1883 00a4 0093     		str	r3, [sp]
+ 1884 00a6 4FF00073 		mov	r3, #33554432
+ 1885 00aa D2B2     		uxtb	r2, r2
+ 1886 00ac 3946     		mov	r1, r7
+ 1887 00ae 2046     		mov	r0, r4
+ 1888 00b0 FFF7FEFF 		bl	I2C_TransferConfig
+ 1889              	.LVL125:
+ 1890              	.L150:
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1891              		.loc 1 1159 28 view .LVU611
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1892              		.loc 1 1159 16 is_stmt 0 view .LVU612
+ 1893 00b4 638D     		ldrh	r3, [r4, #42]
+ 1894 00b6 9BB2     		uxth	r3, r3
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1895              		.loc 1 1159 28 view .LVU613
+ 1896 00b8 002B     		cmp	r3, #0
+ 1897 00ba 33D0     		beq	.L161
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 1898              		.loc 1 1162 7 is_stmt 1 view .LVU614
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 1899              		.loc 1 1162 11 is_stmt 0 view .LVU615
+ 1900 00bc 2A46     		mov	r2, r5
+ 1901 00be 3146     		mov	r1, r6
+ 1902 00c0 2046     		mov	r0, r4
+ 1903 00c2 FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 1904              	.LVL126:
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 1905              		.loc 1 1162 10 view .LVU616
+ 1906 00c6 0028     		cmp	r0, #0
+ 1907 00c8 50D1     		bne	.L157
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1908              		.loc 1 1167 7 is_stmt 1 view .LVU617
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1909              		.loc 1 1167 35 is_stmt 0 view .LVU618
+ 1910 00ca 626A     		ldr	r2, [r4, #36]
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1911              		.loc 1 1167 11 view .LVU619
+ 1912 00cc 2368     		ldr	r3, [r4]
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1913              		.loc 1 1167 30 view .LVU620
+ 1914 00ce 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1915              		.loc 1 1167 28 view .LVU621
+ 1916 00d0 9A62     		str	r2, [r3, #40]
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1917              		.loc 1 1170 7 is_stmt 1 view .LVU622
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1918              		.loc 1 1170 11 is_stmt 0 view .LVU623
+ARM GAS  /tmp/ccbUHtu7.s 			page 164
+
+
+ 1919 00d2 636A     		ldr	r3, [r4, #36]
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1920              		.loc 1 1170 21 view .LVU624
+ 1921 00d4 0133     		adds	r3, r3, #1
+ 1922 00d6 6362     		str	r3, [r4, #36]
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+ 1923              		.loc 1 1172 7 is_stmt 1 view .LVU625
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+ 1924              		.loc 1 1172 11 is_stmt 0 view .LVU626
+ 1925 00d8 638D     		ldrh	r3, [r4, #42]
+ 1926 00da 9BB2     		uxth	r3, r3
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+ 1927              		.loc 1 1172 22 view .LVU627
+ 1928 00dc 013B     		subs	r3, r3, #1
+ 1929 00de 9BB2     		uxth	r3, r3
+ 1930 00e0 6385     		strh	r3, [r4, #42]	@ movhi
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1931              		.loc 1 1173 7 is_stmt 1 view .LVU628
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1932              		.loc 1 1173 11 is_stmt 0 view .LVU629
+ 1933 00e2 238D     		ldrh	r3, [r4, #40]
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1934              		.loc 1 1173 21 view .LVU630
+ 1935 00e4 013B     		subs	r3, r3, #1
+ 1936 00e6 9BB2     		uxth	r3, r3
+ 1937 00e8 2385     		strh	r3, [r4, #40]	@ movhi
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 1938              		.loc 1 1175 7 is_stmt 1 view .LVU631
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 1939              		.loc 1 1175 16 is_stmt 0 view .LVU632
+ 1940 00ea 628D     		ldrh	r2, [r4, #42]
+ 1941 00ec 92B2     		uxth	r2, r2
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 1942              		.loc 1 1175 10 view .LVU633
+ 1943 00ee 002A     		cmp	r2, #0
+ 1944 00f0 E0D0     		beq	.L150
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 1945              		.loc 1 1175 35 discriminator 1 view .LVU634
+ 1946 00f2 002B     		cmp	r3, #0
+ 1947 00f4 DED1     		bne	.L150
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 1948              		.loc 1 1178 9 is_stmt 1 view .LVU635
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 1949              		.loc 1 1178 13 is_stmt 0 view .LVU636
+ 1950 00f6 0095     		str	r5, [sp]
+ 1951 00f8 3346     		mov	r3, r6
+ 1952 00fa 0022     		movs	r2, #0
+ 1953 00fc 8021     		movs	r1, #128
+ 1954 00fe 2046     		mov	r0, r4
+ 1955 0100 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 1956              	.LVL127:
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 1957              		.loc 1 1178 12 view .LVU637
+ 1958 0104 A0BB     		cbnz	r0, .L158
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 1959              		.loc 1 1183 9 is_stmt 1 view .LVU638
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ARM GAS  /tmp/ccbUHtu7.s 			page 165
+
+
+ 1960              		.loc 1 1183 17 is_stmt 0 view .LVU639
+ 1961 0106 638D     		ldrh	r3, [r4, #42]
+ 1962 0108 9BB2     		uxth	r3, r3
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 1963              		.loc 1 1183 12 view .LVU640
+ 1964 010a FF2B     		cmp	r3, #255
+ 1965 010c C6D9     		bls	.L152
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 1966              		.loc 1 1185 11 is_stmt 1 view .LVU641
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 1967              		.loc 1 1185 26 is_stmt 0 view .LVU642
+ 1968 010e FF22     		movs	r2, #255
+ 1969 0110 2285     		strh	r2, [r4, #40]	@ movhi
+1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 1970              		.loc 1 1186 11 is_stmt 1 view .LVU643
+ 1971 0112 0023     		movs	r3, #0
+ 1972 0114 0093     		str	r3, [sp]
+ 1973 0116 4FF08073 		mov	r3, #16777216
+ 1974 011a 3946     		mov	r1, r7
+ 1975 011c 2046     		mov	r0, r4
+ 1976 011e FFF7FEFF 		bl	I2C_TransferConfig
+ 1977              	.LVL128:
+ 1978 0122 C7E7     		b	.L150
+ 1979              	.L161:
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1980              		.loc 1 1200 5 view .LVU644
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1981              		.loc 1 1200 9 is_stmt 0 view .LVU645
+ 1982 0124 2A46     		mov	r2, r5
+ 1983 0126 3146     		mov	r1, r6
+ 1984 0128 2046     		mov	r0, r4
+ 1985 012a FFF7FEFF 		bl	I2C_WaitOnSTOPFlagUntilTimeout
+ 1986              	.LVL129:
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 1987              		.loc 1 1200 8 view .LVU646
+ 1988 012e 08BB     		cbnz	r0, .L159
+1206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1989              		.loc 1 1206 5 is_stmt 1 view .LVU647
+ 1990 0130 2368     		ldr	r3, [r4]
+ 1991 0132 2022     		movs	r2, #32
+ 1992 0134 DA61     		str	r2, [r3, #28]
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 1993              		.loc 1 1209 5 view .LVU648
+ 1994 0136 2168     		ldr	r1, [r4]
+ 1995 0138 4B68     		ldr	r3, [r1, #4]
+ 1996 013a 23F0FF73 		bic	r3, r3, #33423360
+ 1997 013e 23F48B33 		bic	r3, r3, #71168
+ 1998 0142 23F4FF73 		bic	r3, r3, #510
+ 1999 0146 23F00103 		bic	r3, r3, #1
+ 2000 014a 4B60     		str	r3, [r1, #4]
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 2001              		.loc 1 1211 5 view .LVU649
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 2002              		.loc 1 1211 17 is_stmt 0 view .LVU650
+ 2003 014c 84F84120 		strb	r2, [r4, #65]
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2004              		.loc 1 1212 5 is_stmt 1 view .LVU651
+ARM GAS  /tmp/ccbUHtu7.s 			page 166
+
+
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2005              		.loc 1 1212 17 is_stmt 0 view .LVU652
+ 2006 0150 0023     		movs	r3, #0
+ 2007 0152 84F84230 		strb	r3, [r4, #66]
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2008              		.loc 1 1215 5 is_stmt 1 view .LVU653
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2009              		.loc 1 1215 5 view .LVU654
+ 2010 0156 84F84030 		strb	r3, [r4, #64]
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2011              		.loc 1 1215 5 view .LVU655
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 2012              		.loc 1 1217 5 view .LVU656
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 2013              		.loc 1 1217 12 is_stmt 0 view .LVU657
+ 2014 015a 00E0     		b	.L147
+ 2015              	.LVL130:
+ 2016              	.L154:
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 2017              		.loc 1 1221 12 view .LVU658
+ 2018 015c 0220     		movs	r0, #2
+ 2019              	.LVL131:
+ 2020              	.L147:
+1223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2021              		.loc 1 1223 1 view .LVU659
+ 2022 015e 02B0     		add	sp, sp, #8
+ 2023              	.LCFI21:
+ 2024              		.cfi_remember_state
+ 2025              		.cfi_def_cfa_offset 32
+ 2026              		@ sp needed
+ 2027 0160 BDE8F087 		pop	{r4, r5, r6, r7, r8, r9, r10, pc}
+ 2028              	.LVL132:
+ 2029              	.L155:
+ 2030              	.LCFI22:
+ 2031              		.cfi_restore_state
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2032              		.loc 1 1125 5 view .LVU660
+ 2033 0164 0220     		movs	r0, #2
+ 2034              	.LVL133:
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2035              		.loc 1 1125 5 view .LVU661
+ 2036 0166 FAE7     		b	.L147
+ 2037              	.LVL134:
+ 2038              	.L156:
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2039              		.loc 1 1132 14 view .LVU662
+ 2040 0168 0120     		movs	r0, #1
+ 2041 016a F8E7     		b	.L147
+ 2042              	.L157:
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 2043              		.loc 1 1164 16 view .LVU663
+ 2044 016c 0120     		movs	r0, #1
+ 2045 016e F6E7     		b	.L147
+ 2046              	.L158:
+1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 2047              		.loc 1 1180 18 view .LVU664
+ 2048 0170 0120     		movs	r0, #1
+ARM GAS  /tmp/ccbUHtu7.s 			page 167
+
+
+ 2049 0172 F4E7     		b	.L147
+ 2050              	.L159:
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2051              		.loc 1 1202 14 view .LVU665
+ 2052 0174 0120     		movs	r0, #1
+ 2053 0176 F2E7     		b	.L147
+ 2054              	.L163:
+ 2055              		.align	2
+ 2056              	.L162:
+ 2057 0178 00200080 		.word	-2147475456
+ 2058              		.cfi_endproc
+ 2059              	.LFE333:
+ 2061              		.section	.text.HAL_I2C_Master_Receive,"ax",%progbits
+ 2062              		.align	1
+ 2063              		.global	HAL_I2C_Master_Receive
+ 2064              		.syntax unified
+ 2065              		.thumb
+ 2066              		.thumb_func
+ 2068              	HAL_I2C_Master_Receive:
+ 2069              	.LVL135:
+ 2070              	.LFB334:
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 2071              		.loc 1 1238 1 is_stmt 1 view -0
+ 2072              		.cfi_startproc
+ 2073              		@ args = 4, pretend = 0, frame = 0
+ 2074              		@ frame_needed = 0, uses_anonymous_args = 0
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 2075              		.loc 1 1238 1 is_stmt 0 view .LVU667
+ 2076 0000 2DE9F047 		push	{r4, r5, r6, r7, r8, r9, r10, lr}
+ 2077              	.LCFI23:
+ 2078              		.cfi_def_cfa_offset 32
+ 2079              		.cfi_offset 4, -32
+ 2080              		.cfi_offset 5, -28
+ 2081              		.cfi_offset 6, -24
+ 2082              		.cfi_offset 7, -20
+ 2083              		.cfi_offset 8, -16
+ 2084              		.cfi_offset 9, -12
+ 2085              		.cfi_offset 10, -8
+ 2086              		.cfi_offset 14, -4
+ 2087 0004 82B0     		sub	sp, sp, #8
+ 2088              	.LCFI24:
+ 2089              		.cfi_def_cfa_offset 40
+ 2090 0006 0F46     		mov	r7, r1
+ 2091 0008 0A9E     		ldr	r6, [sp, #40]
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2092              		.loc 1 1239 3 is_stmt 1 view .LVU668
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 2093              		.loc 1 1241 3 view .LVU669
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 2094              		.loc 1 1241 11 is_stmt 0 view .LVU670
+ 2095 000a 90F84110 		ldrb	r1, [r0, #65]	@ zero_extendqisi2
+ 2096              	.LVL136:
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 2097              		.loc 1 1241 11 view .LVU671
+ 2098 000e C9B2     		uxtb	r1, r1
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 2099              		.loc 1 1241 6 view .LVU672
+ARM GAS  /tmp/ccbUHtu7.s 			page 168
+
+
+ 2100 0010 2029     		cmp	r1, #32
+ 2101 0012 40F0A280 		bne	.L172
+ 2102 0016 0446     		mov	r4, r0
+ 2103 0018 9046     		mov	r8, r2
+ 2104 001a 9946     		mov	r9, r3
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2105              		.loc 1 1244 5 is_stmt 1 view .LVU673
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2106              		.loc 1 1244 5 view .LVU674
+ 2107 001c 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 2108              	.LVL137:
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2109              		.loc 1 1244 5 is_stmt 0 view .LVU675
+ 2110 0020 012B     		cmp	r3, #1
+ 2111 0022 00F09E80 		beq	.L173
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2112              		.loc 1 1244 5 is_stmt 1 discriminator 2 view .LVU676
+ 2113 0026 4FF0010A 		mov	r10, #1
+ 2114 002a 80F840A0 		strb	r10, [r0, #64]
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2115              		.loc 1 1244 5 discriminator 2 view .LVU677
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2116              		.loc 1 1247 5 discriminator 2 view .LVU678
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2117              		.loc 1 1247 17 is_stmt 0 discriminator 2 view .LVU679
+ 2118 002e FFF7FEFF 		bl	HAL_GetTick
+ 2119              	.LVL138:
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2120              		.loc 1 1247 17 discriminator 2 view .LVU680
+ 2121 0032 0546     		mov	r5, r0
+ 2122              	.LVL139:
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2123              		.loc 1 1249 5 is_stmt 1 discriminator 2 view .LVU681
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2124              		.loc 1 1249 9 is_stmt 0 discriminator 2 view .LVU682
+ 2125 0034 0090     		str	r0, [sp]
+ 2126 0036 1923     		movs	r3, #25
+ 2127 0038 5246     		mov	r2, r10
+ 2128 003a 4FF40041 		mov	r1, #32768
+ 2129 003e 2046     		mov	r0, r4
+ 2130              	.LVL140:
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2131              		.loc 1 1249 9 discriminator 2 view .LVU683
+ 2132 0040 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2133              	.LVL141:
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2134              		.loc 1 1249 8 discriminator 2 view .LVU684
+ 2135 0044 0028     		cmp	r0, #0
+ 2136 0046 40F08E80 		bne	.L174
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 2137              		.loc 1 1254 5 is_stmt 1 view .LVU685
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 2138              		.loc 1 1254 21 is_stmt 0 view .LVU686
+ 2139 004a 2223     		movs	r3, #34
+ 2140 004c 84F84130 		strb	r3, [r4, #65]
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 2141              		.loc 1 1255 5 is_stmt 1 view .LVU687
+ARM GAS  /tmp/ccbUHtu7.s 			page 169
+
+
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 2142              		.loc 1 1255 21 is_stmt 0 view .LVU688
+ 2143 0050 1023     		movs	r3, #16
+ 2144 0052 84F84230 		strb	r3, [r4, #66]
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2145              		.loc 1 1256 5 is_stmt 1 view .LVU689
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2146              		.loc 1 1256 21 is_stmt 0 view .LVU690
+ 2147 0056 0023     		movs	r3, #0
+ 2148 0058 6364     		str	r3, [r4, #68]
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 2149              		.loc 1 1259 5 is_stmt 1 view .LVU691
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 2150              		.loc 1 1259 21 is_stmt 0 view .LVU692
+ 2151 005a C4F82480 		str	r8, [r4, #36]
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 2152              		.loc 1 1260 5 is_stmt 1 view .LVU693
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 2153              		.loc 1 1260 21 is_stmt 0 view .LVU694
+ 2154 005e A4F82A90 		strh	r9, [r4, #42]	@ movhi
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2155              		.loc 1 1261 5 is_stmt 1 view .LVU695
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2156              		.loc 1 1261 21 is_stmt 0 view .LVU696
+ 2157 0062 6363     		str	r3, [r4, #52]
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2158              		.loc 1 1265 5 is_stmt 1 view .LVU697
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2159              		.loc 1 1265 13 is_stmt 0 view .LVU698
+ 2160 0064 638D     		ldrh	r3, [r4, #42]
+ 2161 0066 9BB2     		uxth	r3, r3
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2162              		.loc 1 1265 8 view .LVU699
+ 2163 0068 FF2B     		cmp	r3, #255
+ 2164 006a 0AD9     		bls	.L166
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 2165              		.loc 1 1267 7 is_stmt 1 view .LVU700
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 2166              		.loc 1 1267 22 is_stmt 0 view .LVU701
+ 2167 006c FF22     		movs	r2, #255
+ 2168 006e 2285     		strh	r2, [r4, #40]	@ movhi
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 2169              		.loc 1 1268 7 is_stmt 1 view .LVU702
+ 2170 0070 414B     		ldr	r3, .L180
+ 2171 0072 0093     		str	r3, [sp]
+ 2172 0074 4FF08073 		mov	r3, #16777216
+ 2173 0078 3946     		mov	r1, r7
+ 2174 007a 2046     		mov	r0, r4
+ 2175 007c FFF7FEFF 		bl	I2C_TransferConfig
+ 2176              	.LVL142:
+ 2177 0080 18E0     		b	.L168
+ 2178              	.L166:
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2179              		.loc 1 1273 7 view .LVU703
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2180              		.loc 1 1273 28 is_stmt 0 view .LVU704
+ 2181 0082 628D     		ldrh	r2, [r4, #42]
+ARM GAS  /tmp/ccbUHtu7.s 			page 170
+
+
+ 2182 0084 92B2     		uxth	r2, r2
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2183              		.loc 1 1273 22 view .LVU705
+ 2184 0086 2285     		strh	r2, [r4, #40]	@ movhi
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 2185              		.loc 1 1274 7 is_stmt 1 view .LVU706
+ 2186 0088 3B4B     		ldr	r3, .L180
+ 2187 008a 0093     		str	r3, [sp]
+ 2188 008c 4FF00073 		mov	r3, #33554432
+ 2189 0090 D2B2     		uxtb	r2, r2
+ 2190 0092 3946     		mov	r1, r7
+ 2191 0094 2046     		mov	r0, r4
+ 2192 0096 FFF7FEFF 		bl	I2C_TransferConfig
+ 2193              	.LVL143:
+ 2194 009a 0BE0     		b	.L168
+ 2195              	.L170:
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2196              		.loc 1 1311 11 view .LVU707
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2197              		.loc 1 1311 32 is_stmt 0 view .LVU708
+ 2198 009c 628D     		ldrh	r2, [r4, #42]
+ 2199 009e 92B2     		uxth	r2, r2
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2200              		.loc 1 1311 26 view .LVU709
+ 2201 00a0 2285     		strh	r2, [r4, #40]	@ movhi
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 2202              		.loc 1 1312 11 is_stmt 1 view .LVU710
+ 2203 00a2 0023     		movs	r3, #0
+ 2204 00a4 0093     		str	r3, [sp]
+ 2205 00a6 4FF00073 		mov	r3, #33554432
+ 2206 00aa D2B2     		uxtb	r2, r2
+ 2207 00ac 3946     		mov	r1, r7
+ 2208 00ae 2046     		mov	r0, r4
+ 2209 00b0 FFF7FEFF 		bl	I2C_TransferConfig
+ 2210              	.LVL144:
+ 2211              	.L168:
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2212              		.loc 1 1278 28 view .LVU711
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2213              		.loc 1 1278 16 is_stmt 0 view .LVU712
+ 2214 00b4 638D     		ldrh	r3, [r4, #42]
+ 2215 00b6 9BB2     		uxth	r3, r3
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2216              		.loc 1 1278 28 view .LVU713
+ 2217 00b8 002B     		cmp	r3, #0
+ 2218 00ba 32D0     		beq	.L179
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2219              		.loc 1 1281 7 is_stmt 1 view .LVU714
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2220              		.loc 1 1281 11 is_stmt 0 view .LVU715
+ 2221 00bc 2A46     		mov	r2, r5
+ 2222 00be 3146     		mov	r1, r6
+ 2223 00c0 2046     		mov	r0, r4
+ 2224 00c2 FFF7FEFF 		bl	I2C_WaitOnRXNEFlagUntilTimeout
+ 2225              	.LVL145:
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2226              		.loc 1 1281 10 view .LVU716
+ARM GAS  /tmp/ccbUHtu7.s 			page 171
+
+
+ 2227 00c6 0028     		cmp	r0, #0
+ 2228 00c8 4FD1     		bne	.L175
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2229              		.loc 1 1287 7 is_stmt 1 view .LVU717
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2230              		.loc 1 1287 38 is_stmt 0 view .LVU718
+ 2231 00ca 2368     		ldr	r3, [r4]
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2232              		.loc 1 1287 48 view .LVU719
+ 2233 00cc 5A6A     		ldr	r2, [r3, #36]
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2234              		.loc 1 1287 12 view .LVU720
+ 2235 00ce 636A     		ldr	r3, [r4, #36]
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2236              		.loc 1 1287 23 view .LVU721
+ 2237 00d0 1A70     		strb	r2, [r3]
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2238              		.loc 1 1290 7 is_stmt 1 view .LVU722
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2239              		.loc 1 1290 11 is_stmt 0 view .LVU723
+ 2240 00d2 636A     		ldr	r3, [r4, #36]
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2241              		.loc 1 1290 21 view .LVU724
+ 2242 00d4 0133     		adds	r3, r3, #1
+ 2243 00d6 6362     		str	r3, [r4, #36]
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 2244              		.loc 1 1292 7 is_stmt 1 view .LVU725
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 2245              		.loc 1 1292 11 is_stmt 0 view .LVU726
+ 2246 00d8 228D     		ldrh	r2, [r4, #40]
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 2247              		.loc 1 1292 21 view .LVU727
+ 2248 00da 013A     		subs	r2, r2, #1
+ 2249 00dc 92B2     		uxth	r2, r2
+ 2250 00de 2285     		strh	r2, [r4, #40]	@ movhi
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2251              		.loc 1 1293 7 is_stmt 1 view .LVU728
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2252              		.loc 1 1293 11 is_stmt 0 view .LVU729
+ 2253 00e0 638D     		ldrh	r3, [r4, #42]
+ 2254 00e2 9BB2     		uxth	r3, r3
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2255              		.loc 1 1293 22 view .LVU730
+ 2256 00e4 013B     		subs	r3, r3, #1
+ 2257 00e6 9BB2     		uxth	r3, r3
+ 2258 00e8 6385     		strh	r3, [r4, #42]	@ movhi
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2259              		.loc 1 1295 7 is_stmt 1 view .LVU731
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2260              		.loc 1 1295 16 is_stmt 0 view .LVU732
+ 2261 00ea 638D     		ldrh	r3, [r4, #42]
+ 2262 00ec 9BB2     		uxth	r3, r3
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2263              		.loc 1 1295 10 view .LVU733
+ 2264 00ee 002B     		cmp	r3, #0
+ 2265 00f0 E0D0     		beq	.L168
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ARM GAS  /tmp/ccbUHtu7.s 			page 172
+
+
+ 2266              		.loc 1 1295 35 discriminator 1 view .LVU734
+ 2267 00f2 002A     		cmp	r2, #0
+ 2268 00f4 DED1     		bne	.L168
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 2269              		.loc 1 1298 9 is_stmt 1 view .LVU735
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 2270              		.loc 1 1298 13 is_stmt 0 view .LVU736
+ 2271 00f6 0095     		str	r5, [sp]
+ 2272 00f8 3346     		mov	r3, r6
+ 2273 00fa 8021     		movs	r1, #128
+ 2274 00fc 2046     		mov	r0, r4
+ 2275 00fe FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2276              	.LVL146:
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 2277              		.loc 1 1298 12 view .LVU737
+ 2278 0102 A0BB     		cbnz	r0, .L176
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 2279              		.loc 1 1303 9 is_stmt 1 view .LVU738
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 2280              		.loc 1 1303 17 is_stmt 0 view .LVU739
+ 2281 0104 638D     		ldrh	r3, [r4, #42]
+ 2282 0106 9BB2     		uxth	r3, r3
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 2283              		.loc 1 1303 12 view .LVU740
+ 2284 0108 FF2B     		cmp	r3, #255
+ 2285 010a C7D9     		bls	.L170
+1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 2286              		.loc 1 1305 11 is_stmt 1 view .LVU741
+1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 2287              		.loc 1 1305 26 is_stmt 0 view .LVU742
+ 2288 010c FF22     		movs	r2, #255
+ 2289 010e 2285     		strh	r2, [r4, #40]	@ movhi
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 2290              		.loc 1 1306 11 is_stmt 1 view .LVU743
+ 2291 0110 0023     		movs	r3, #0
+ 2292 0112 0093     		str	r3, [sp]
+ 2293 0114 4FF08073 		mov	r3, #16777216
+ 2294 0118 3946     		mov	r1, r7
+ 2295 011a 2046     		mov	r0, r4
+ 2296 011c FFF7FEFF 		bl	I2C_TransferConfig
+ 2297              	.LVL147:
+ 2298 0120 C8E7     		b	.L168
+ 2299              	.L179:
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2300              		.loc 1 1320 5 view .LVU744
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2301              		.loc 1 1320 9 is_stmt 0 view .LVU745
+ 2302 0122 2A46     		mov	r2, r5
+ 2303 0124 3146     		mov	r1, r6
+ 2304 0126 2046     		mov	r0, r4
+ 2305 0128 FFF7FEFF 		bl	I2C_WaitOnSTOPFlagUntilTimeout
+ 2306              	.LVL148:
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2307              		.loc 1 1320 8 view .LVU746
+ 2308 012c 08BB     		cbnz	r0, .L177
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2309              		.loc 1 1326 5 is_stmt 1 view .LVU747
+ARM GAS  /tmp/ccbUHtu7.s 			page 173
+
+
+ 2310 012e 2368     		ldr	r3, [r4]
+ 2311 0130 2022     		movs	r2, #32
+ 2312 0132 DA61     		str	r2, [r3, #28]
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2313              		.loc 1 1329 5 view .LVU748
+ 2314 0134 2168     		ldr	r1, [r4]
+ 2315 0136 4B68     		ldr	r3, [r1, #4]
+ 2316 0138 23F0FF73 		bic	r3, r3, #33423360
+ 2317 013c 23F48B33 		bic	r3, r3, #71168
+ 2318 0140 23F4FF73 		bic	r3, r3, #510
+ 2319 0144 23F00103 		bic	r3, r3, #1
+ 2320 0148 4B60     		str	r3, [r1, #4]
+1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 2321              		.loc 1 1331 5 view .LVU749
+1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 2322              		.loc 1 1331 17 is_stmt 0 view .LVU750
+ 2323 014a 84F84120 		strb	r2, [r4, #65]
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2324              		.loc 1 1332 5 is_stmt 1 view .LVU751
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2325              		.loc 1 1332 17 is_stmt 0 view .LVU752
+ 2326 014e 0023     		movs	r3, #0
+ 2327 0150 84F84230 		strb	r3, [r4, #66]
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2328              		.loc 1 1335 5 is_stmt 1 view .LVU753
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2329              		.loc 1 1335 5 view .LVU754
+ 2330 0154 84F84030 		strb	r3, [r4, #64]
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2331              		.loc 1 1335 5 view .LVU755
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 2332              		.loc 1 1337 5 view .LVU756
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 2333              		.loc 1 1337 12 is_stmt 0 view .LVU757
+ 2334 0158 00E0     		b	.L165
+ 2335              	.LVL149:
+ 2336              	.L172:
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 2337              		.loc 1 1341 12 view .LVU758
+ 2338 015a 0220     		movs	r0, #2
+ 2339              	.LVL150:
+ 2340              	.L165:
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2341              		.loc 1 1343 1 view .LVU759
+ 2342 015c 02B0     		add	sp, sp, #8
+ 2343              	.LCFI25:
+ 2344              		.cfi_remember_state
+ 2345              		.cfi_def_cfa_offset 32
+ 2346              		@ sp needed
+ 2347 015e BDE8F087 		pop	{r4, r5, r6, r7, r8, r9, r10, pc}
+ 2348              	.LVL151:
+ 2349              	.L173:
+ 2350              	.LCFI26:
+ 2351              		.cfi_restore_state
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2352              		.loc 1 1244 5 view .LVU760
+ 2353 0162 0220     		movs	r0, #2
+ARM GAS  /tmp/ccbUHtu7.s 			page 174
+
+
+ 2354              	.LVL152:
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2355              		.loc 1 1244 5 view .LVU761
+ 2356 0164 FAE7     		b	.L165
+ 2357              	.LVL153:
+ 2358              	.L174:
+1251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2359              		.loc 1 1251 14 view .LVU762
+ 2360 0166 0120     		movs	r0, #1
+ 2361 0168 F8E7     		b	.L165
+ 2362              	.L175:
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 2363              		.loc 1 1283 16 view .LVU763
+ 2364 016a 0120     		movs	r0, #1
+ 2365 016c F6E7     		b	.L165
+ 2366              	.L176:
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 2367              		.loc 1 1300 18 view .LVU764
+ 2368 016e 0120     		movs	r0, #1
+ 2369 0170 F4E7     		b	.L165
+ 2370              	.L177:
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2371              		.loc 1 1322 14 view .LVU765
+ 2372 0172 0120     		movs	r0, #1
+ 2373 0174 F2E7     		b	.L165
+ 2374              	.L181:
+ 2375 0176 00BF     		.align	2
+ 2376              	.L180:
+ 2377 0178 00240080 		.word	-2147474432
+ 2378              		.cfi_endproc
+ 2379              	.LFE334:
+ 2381              		.section	.text.HAL_I2C_Slave_Transmit,"ax",%progbits
+ 2382              		.align	1
+ 2383              		.global	HAL_I2C_Slave_Transmit
+ 2384              		.syntax unified
+ 2385              		.thumb
+ 2386              		.thumb_func
+ 2388              	HAL_I2C_Slave_Transmit:
+ 2389              	.LVL154:
+ 2390              	.LFB335:
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 2391              		.loc 1 1356 1 is_stmt 1 view -0
+ 2392              		.cfi_startproc
+ 2393              		@ args = 0, pretend = 0, frame = 0
+ 2394              		@ frame_needed = 0, uses_anonymous_args = 0
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 2395              		.loc 1 1356 1 is_stmt 0 view .LVU767
+ 2396 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 2397              	.LCFI27:
+ 2398              		.cfi_def_cfa_offset 24
+ 2399              		.cfi_offset 4, -24
+ 2400              		.cfi_offset 5, -20
+ 2401              		.cfi_offset 6, -16
+ 2402              		.cfi_offset 7, -12
+ 2403              		.cfi_offset 8, -8
+ 2404              		.cfi_offset 14, -4
+ 2405 0004 82B0     		sub	sp, sp, #8
+ARM GAS  /tmp/ccbUHtu7.s 			page 175
+
+
+ 2406              	.LCFI28:
+ 2407              		.cfi_def_cfa_offset 32
+ 2408 0006 1D46     		mov	r5, r3
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2409              		.loc 1 1357 3 is_stmt 1 view .LVU768
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 2410              		.loc 1 1359 3 view .LVU769
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 2411              		.loc 1 1359 11 is_stmt 0 view .LVU770
+ 2412 0008 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 2413              	.LVL155:
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 2414              		.loc 1 1359 11 view .LVU771
+ 2415 000c DBB2     		uxtb	r3, r3
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 2416              		.loc 1 1359 6 view .LVU772
+ 2417 000e 202B     		cmp	r3, #32
+ 2418 0010 40F0C880 		bne	.L195
+ 2419 0014 0446     		mov	r4, r0
+ 2420 0016 0F46     		mov	r7, r1
+ 2421 0018 9046     		mov	r8, r2
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2422              		.loc 1 1361 5 is_stmt 1 view .LVU773
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2423              		.loc 1 1361 8 is_stmt 0 view .LVU774
+ 2424 001a 0029     		cmp	r1, #0
+ 2425 001c 52D0     		beq	.L184
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2426              		.loc 1 1361 25 discriminator 1 view .LVU775
+ 2427 001e 002A     		cmp	r2, #0
+ 2428 0020 50D0     		beq	.L184
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2429              		.loc 1 1367 5 is_stmt 1 view .LVU776
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2430              		.loc 1 1367 5 view .LVU777
+ 2431 0022 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 2432 0026 012B     		cmp	r3, #1
+ 2433 0028 00F0C080 		beq	.L196
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2434              		.loc 1 1367 5 discriminator 2 view .LVU778
+ 2435 002c 0123     		movs	r3, #1
+ 2436 002e 80F84030 		strb	r3, [r0, #64]
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2437              		.loc 1 1367 5 discriminator 2 view .LVU779
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2438              		.loc 1 1370 5 discriminator 2 view .LVU780
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2439              		.loc 1 1370 17 is_stmt 0 discriminator 2 view .LVU781
+ 2440 0032 FFF7FEFF 		bl	HAL_GetTick
+ 2441              	.LVL156:
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2442              		.loc 1 1370 17 discriminator 2 view .LVU782
+ 2443 0036 0646     		mov	r6, r0
+ 2444              	.LVL157:
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 2445              		.loc 1 1372 5 is_stmt 1 discriminator 2 view .LVU783
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ARM GAS  /tmp/ccbUHtu7.s 			page 176
+
+
+ 2446              		.loc 1 1372 21 is_stmt 0 discriminator 2 view .LVU784
+ 2447 0038 2123     		movs	r3, #33
+ 2448 003a 84F84130 		strb	r3, [r4, #65]
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 2449              		.loc 1 1373 5 is_stmt 1 discriminator 2 view .LVU785
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 2450              		.loc 1 1373 21 is_stmt 0 discriminator 2 view .LVU786
+ 2451 003e 2023     		movs	r3, #32
+ 2452 0040 84F84230 		strb	r3, [r4, #66]
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2453              		.loc 1 1374 5 is_stmt 1 discriminator 2 view .LVU787
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2454              		.loc 1 1374 21 is_stmt 0 discriminator 2 view .LVU788
+ 2455 0044 0022     		movs	r2, #0
+ 2456 0046 6264     		str	r2, [r4, #68]
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 2457              		.loc 1 1377 5 is_stmt 1 discriminator 2 view .LVU789
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 2458              		.loc 1 1377 21 is_stmt 0 discriminator 2 view .LVU790
+ 2459 0048 6762     		str	r7, [r4, #36]
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 2460              		.loc 1 1378 5 is_stmt 1 discriminator 2 view .LVU791
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 2461              		.loc 1 1378 21 is_stmt 0 discriminator 2 view .LVU792
+ 2462 004a A4F82A80 		strh	r8, [r4, #42]	@ movhi
+1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2463              		.loc 1 1379 5 is_stmt 1 discriminator 2 view .LVU793
+1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2464              		.loc 1 1379 21 is_stmt 0 discriminator 2 view .LVU794
+ 2465 004e 6263     		str	r2, [r4, #52]
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2466              		.loc 1 1382 5 is_stmt 1 discriminator 2 view .LVU795
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2467              		.loc 1 1382 9 is_stmt 0 discriminator 2 view .LVU796
+ 2468 0050 2168     		ldr	r1, [r4]
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2469              		.loc 1 1382 19 discriminator 2 view .LVU797
+ 2470 0052 4B68     		ldr	r3, [r1, #4]
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2471              		.loc 1 1382 25 discriminator 2 view .LVU798
+ 2472 0054 23F40043 		bic	r3, r3, #32768
+ 2473 0058 4B60     		str	r3, [r1, #4]
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2474              		.loc 1 1385 5 is_stmt 1 discriminator 2 view .LVU799
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2475              		.loc 1 1385 9 is_stmt 0 discriminator 2 view .LVU800
+ 2476 005a 0090     		str	r0, [sp]
+ 2477 005c 2B46     		mov	r3, r5
+ 2478 005e 0821     		movs	r1, #8
+ 2479 0060 2046     		mov	r0, r4
+ 2480              	.LVL158:
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2481              		.loc 1 1385 9 discriminator 2 view .LVU801
+ 2482 0062 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2483              	.LVL159:
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2484              		.loc 1 1385 8 discriminator 2 view .LVU802
+ARM GAS  /tmp/ccbUHtu7.s 			page 177
+
+
+ 2485 0066 0028     		cmp	r0, #0
+ 2486 0068 31D1     		bne	.L198
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2487              		.loc 1 1393 5 is_stmt 1 view .LVU803
+ 2488 006a 2368     		ldr	r3, [r4]
+ 2489 006c 0822     		movs	r2, #8
+ 2490 006e DA61     		str	r2, [r3, #28]
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2491              		.loc 1 1396 5 view .LVU804
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2492              		.loc 1 1396 19 is_stmt 0 view .LVU805
+ 2493 0070 E368     		ldr	r3, [r4, #12]
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2494              		.loc 1 1396 8 view .LVU806
+ 2495 0072 022B     		cmp	r3, #2
+ 2496 0074 32D0     		beq	.L199
+ 2497              	.L187:
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2498              		.loc 1 1411 5 is_stmt 1 view .LVU807
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2499              		.loc 1 1411 9 is_stmt 0 view .LVU808
+ 2500 0076 0096     		str	r6, [sp]
+ 2501 0078 2B46     		mov	r3, r5
+ 2502 007a 0022     		movs	r2, #0
+ 2503 007c 4FF48031 		mov	r1, #65536
+ 2504 0080 2046     		mov	r0, r4
+ 2505 0082 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2506              	.LVL160:
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2507              		.loc 1 1411 8 view .LVU809
+ 2508 0086 0028     		cmp	r0, #0
+ 2509 0088 3BD1     		bne	.L200
+ 2510              	.L189:
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2511              		.loc 1 1418 28 is_stmt 1 view .LVU810
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2512              		.loc 1 1418 16 is_stmt 0 view .LVU811
+ 2513 008a 638D     		ldrh	r3, [r4, #42]
+ 2514 008c 9BB2     		uxth	r3, r3
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2515              		.loc 1 1418 28 view .LVU812
+ 2516 008e 002B     		cmp	r3, #0
+ 2517 0090 45D0     		beq	.L201
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2518              		.loc 1 1421 7 is_stmt 1 view .LVU813
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2519              		.loc 1 1421 11 is_stmt 0 view .LVU814
+ 2520 0092 3246     		mov	r2, r6
+ 2521 0094 2946     		mov	r1, r5
+ 2522 0096 2046     		mov	r0, r4
+ 2523 0098 FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 2524              	.LVL161:
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2525              		.loc 1 1421 10 view .LVU815
+ 2526 009c 0028     		cmp	r0, #0
+ 2527 009e 37D1     		bne	.L202
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 178
+
+
+ 2528              		.loc 1 1429 7 is_stmt 1 view .LVU816
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2529              		.loc 1 1429 35 is_stmt 0 view .LVU817
+ 2530 00a0 626A     		ldr	r2, [r4, #36]
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2531              		.loc 1 1429 11 view .LVU818
+ 2532 00a2 2368     		ldr	r3, [r4]
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2533              		.loc 1 1429 30 view .LVU819
+ 2534 00a4 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2535              		.loc 1 1429 28 view .LVU820
+ 2536 00a6 9A62     		str	r2, [r3, #40]
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2537              		.loc 1 1432 7 is_stmt 1 view .LVU821
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2538              		.loc 1 1432 11 is_stmt 0 view .LVU822
+ 2539 00a8 636A     		ldr	r3, [r4, #36]
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2540              		.loc 1 1432 21 view .LVU823
+ 2541 00aa 0133     		adds	r3, r3, #1
+ 2542 00ac 6362     		str	r3, [r4, #36]
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2543              		.loc 1 1434 7 is_stmt 1 view .LVU824
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2544              		.loc 1 1434 11 is_stmt 0 view .LVU825
+ 2545 00ae B4F82AC0 		ldrh	ip, [r4, #42]
+ 2546 00b2 1FFA8CFC 		uxth	ip, ip
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2547              		.loc 1 1434 22 view .LVU826
+ 2548 00b6 0CF1FF3C 		add	ip, ip, #-1
+ 2549 00ba 1FFA8CFC 		uxth	ip, ip
+ 2550 00be A4F82AC0 		strh	ip, [r4, #42]	@ movhi
+ 2551 00c2 E2E7     		b	.L189
+ 2552              	.LVL162:
+ 2553              	.L184:
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 2554              		.loc 1 1363 7 is_stmt 1 view .LVU827
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 2555              		.loc 1 1363 23 is_stmt 0 view .LVU828
+ 2556 00c4 4FF40073 		mov	r3, #512
+ 2557 00c8 6364     		str	r3, [r4, #68]
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2558              		.loc 1 1364 7 is_stmt 1 view .LVU829
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2559              		.loc 1 1364 15 is_stmt 0 view .LVU830
+ 2560 00ca 0120     		movs	r0, #1
+ 2561              	.LVL163:
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2562              		.loc 1 1364 15 view .LVU831
+ 2563 00cc 6BE0     		b	.L183
+ 2564              	.LVL164:
+ 2565              	.L198:
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2566              		.loc 1 1388 7 is_stmt 1 view .LVU832
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2567              		.loc 1 1388 11 is_stmt 0 view .LVU833
+ARM GAS  /tmp/ccbUHtu7.s 			page 179
+
+
+ 2568 00ce 2268     		ldr	r2, [r4]
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2569              		.loc 1 1388 21 view .LVU834
+ 2570 00d0 5368     		ldr	r3, [r2, #4]
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2571              		.loc 1 1388 27 view .LVU835
+ 2572 00d2 43F40043 		orr	r3, r3, #32768
+ 2573 00d6 5360     		str	r3, [r2, #4]
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2574              		.loc 1 1389 7 is_stmt 1 view .LVU836
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2575              		.loc 1 1389 14 is_stmt 0 view .LVU837
+ 2576 00d8 0120     		movs	r0, #1
+ 2577 00da 64E0     		b	.L183
+ 2578              	.L199:
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2579              		.loc 1 1399 7 is_stmt 1 view .LVU838
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2580              		.loc 1 1399 11 is_stmt 0 view .LVU839
+ 2581 00dc 0096     		str	r6, [sp]
+ 2582 00de 2B46     		mov	r3, r5
+ 2583 00e0 0022     		movs	r2, #0
+ 2584 00e2 0821     		movs	r1, #8
+ 2585 00e4 2046     		mov	r0, r4
+ 2586 00e6 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2587              	.LVL165:
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2588              		.loc 1 1399 10 view .LVU840
+ 2589 00ea 18B9     		cbnz	r0, .L203
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2590              		.loc 1 1407 7 is_stmt 1 view .LVU841
+ 2591 00ec 2368     		ldr	r3, [r4]
+ 2592 00ee 0822     		movs	r2, #8
+ 2593 00f0 DA61     		str	r2, [r3, #28]
+ 2594 00f2 C0E7     		b	.L187
+ 2595              	.L203:
+1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+ 2596              		.loc 1 1402 9 view .LVU842
+1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+ 2597              		.loc 1 1402 13 is_stmt 0 view .LVU843
+ 2598 00f4 2268     		ldr	r2, [r4]
+1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+ 2599              		.loc 1 1402 23 view .LVU844
+ 2600 00f6 5368     		ldr	r3, [r2, #4]
+1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+ 2601              		.loc 1 1402 29 view .LVU845
+ 2602 00f8 43F40043 		orr	r3, r3, #32768
+ 2603 00fc 5360     		str	r3, [r2, #4]
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 2604              		.loc 1 1403 9 is_stmt 1 view .LVU846
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 2605              		.loc 1 1403 16 is_stmt 0 view .LVU847
+ 2606 00fe 0120     		movs	r0, #1
+ 2607 0100 51E0     		b	.L183
+ 2608              	.L200:
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2609              		.loc 1 1414 7 is_stmt 1 view .LVU848
+ARM GAS  /tmp/ccbUHtu7.s 			page 180
+
+
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2610              		.loc 1 1414 11 is_stmt 0 view .LVU849
+ 2611 0102 2268     		ldr	r2, [r4]
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2612              		.loc 1 1414 21 view .LVU850
+ 2613 0104 5368     		ldr	r3, [r2, #4]
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2614              		.loc 1 1414 27 view .LVU851
+ 2615 0106 43F40043 		orr	r3, r3, #32768
+ 2616 010a 5360     		str	r3, [r2, #4]
+1415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2617              		.loc 1 1415 7 is_stmt 1 view .LVU852
+1415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2618              		.loc 1 1415 14 is_stmt 0 view .LVU853
+ 2619 010c 0120     		movs	r0, #1
+ 2620 010e 4AE0     		b	.L183
+ 2621              	.L202:
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+ 2622              		.loc 1 1424 9 is_stmt 1 view .LVU854
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+ 2623              		.loc 1 1424 13 is_stmt 0 view .LVU855
+ 2624 0110 2268     		ldr	r2, [r4]
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+ 2625              		.loc 1 1424 23 view .LVU856
+ 2626 0112 5368     		ldr	r3, [r2, #4]
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         return HAL_ERROR;
+ 2627              		.loc 1 1424 29 view .LVU857
+ 2628 0114 43F40043 		orr	r3, r3, #32768
+ 2629 0118 5360     		str	r3, [r2, #4]
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 2630              		.loc 1 1425 9 is_stmt 1 view .LVU858
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 2631              		.loc 1 1425 16 is_stmt 0 view .LVU859
+ 2632 011a 0120     		movs	r0, #1
+ 2633 011c 43E0     		b	.L183
+ 2634              	.L201:
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2635              		.loc 1 1438 5 is_stmt 1 view .LVU860
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2636              		.loc 1 1438 9 is_stmt 0 view .LVU861
+ 2637 011e 0096     		str	r6, [sp]
+ 2638 0120 2B46     		mov	r3, r5
+ 2639 0122 0022     		movs	r2, #0
+ 2640 0124 1021     		movs	r1, #16
+ 2641 0126 2046     		mov	r0, r4
+ 2642 0128 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2643              	.LVL166:
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2644              		.loc 1 1438 8 view .LVU862
+ 2645 012c 30B1     		cbz	r0, .L192
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2646              		.loc 1 1441 7 is_stmt 1 view .LVU863
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2647              		.loc 1 1441 11 is_stmt 0 view .LVU864
+ 2648 012e 2268     		ldr	r2, [r4]
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2649              		.loc 1 1441 21 view .LVU865
+ARM GAS  /tmp/ccbUHtu7.s 			page 181
+
+
+ 2650 0130 5368     		ldr	r3, [r2, #4]
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2651              		.loc 1 1441 27 view .LVU866
+ 2652 0132 43F40043 		orr	r3, r3, #32768
+ 2653 0136 5360     		str	r3, [r2, #4]
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2654              		.loc 1 1442 7 is_stmt 1 view .LVU867
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2655              		.loc 1 1442 14 is_stmt 0 view .LVU868
+ 2656 0138 0120     		movs	r0, #1
+ 2657 013a 34E0     		b	.L183
+ 2658              	.L192:
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2659              		.loc 1 1446 5 is_stmt 1 view .LVU869
+ 2660 013c 2046     		mov	r0, r4
+ 2661 013e FFF7FEFF 		bl	I2C_Flush_TXDR
+ 2662              	.LVL167:
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2663              		.loc 1 1449 5 view .LVU870
+ 2664 0142 2368     		ldr	r3, [r4]
+ 2665 0144 1022     		movs	r2, #16
+ 2666 0146 DA61     		str	r2, [r3, #28]
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2667              		.loc 1 1452 5 view .LVU871
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2668              		.loc 1 1452 9 is_stmt 0 view .LVU872
+ 2669 0148 3246     		mov	r2, r6
+ 2670 014a 2946     		mov	r1, r5
+ 2671 014c 2046     		mov	r0, r4
+ 2672 014e FFF7FEFF 		bl	I2C_WaitOnSTOPFlagUntilTimeout
+ 2673              	.LVL168:
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2674              		.loc 1 1452 8 view .LVU873
+ 2675 0152 30B1     		cbz	r0, .L193
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2676              		.loc 1 1455 7 is_stmt 1 view .LVU874
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2677              		.loc 1 1455 11 is_stmt 0 view .LVU875
+ 2678 0154 2268     		ldr	r2, [r4]
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2679              		.loc 1 1455 21 view .LVU876
+ 2680 0156 5368     		ldr	r3, [r2, #4]
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2681              		.loc 1 1455 27 view .LVU877
+ 2682 0158 43F40043 		orr	r3, r3, #32768
+ 2683 015c 5360     		str	r3, [r2, #4]
+1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2684              		.loc 1 1457 7 is_stmt 1 view .LVU878
+1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2685              		.loc 1 1457 14 is_stmt 0 view .LVU879
+ 2686 015e 0120     		movs	r0, #1
+ 2687 0160 21E0     		b	.L183
+ 2688              	.L193:
+1461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2689              		.loc 1 1461 5 is_stmt 1 view .LVU880
+ 2690 0162 2368     		ldr	r3, [r4]
+ 2691 0164 2022     		movs	r2, #32
+ARM GAS  /tmp/ccbUHtu7.s 			page 182
+
+
+ 2692 0166 DA61     		str	r2, [r3, #28]
+1464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2693              		.loc 1 1464 5 view .LVU881
+1464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2694              		.loc 1 1464 9 is_stmt 0 view .LVU882
+ 2695 0168 0096     		str	r6, [sp]
+ 2696 016a 2B46     		mov	r3, r5
+ 2697 016c 0122     		movs	r2, #1
+ 2698 016e 4FF40041 		mov	r1, #32768
+ 2699 0172 2046     		mov	r0, r4
+ 2700 0174 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2701              	.LVL169:
+1464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2702              		.loc 1 1464 8 view .LVU883
+ 2703 0178 30B1     		cbz	r0, .L194
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2704              		.loc 1 1467 7 is_stmt 1 view .LVU884
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2705              		.loc 1 1467 11 is_stmt 0 view .LVU885
+ 2706 017a 2268     		ldr	r2, [r4]
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2707              		.loc 1 1467 21 view .LVU886
+ 2708 017c 5368     		ldr	r3, [r2, #4]
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2709              		.loc 1 1467 27 view .LVU887
+ 2710 017e 43F40043 		orr	r3, r3, #32768
+ 2711 0182 5360     		str	r3, [r2, #4]
+1468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2712              		.loc 1 1468 7 is_stmt 1 view .LVU888
+1468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2713              		.loc 1 1468 14 is_stmt 0 view .LVU889
+ 2714 0184 0120     		movs	r0, #1
+ 2715 0186 0EE0     		b	.L183
+ 2716              	.L194:
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2717              		.loc 1 1472 5 is_stmt 1 view .LVU890
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2718              		.loc 1 1472 9 is_stmt 0 view .LVU891
+ 2719 0188 2268     		ldr	r2, [r4]
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2720              		.loc 1 1472 19 view .LVU892
+ 2721 018a 5368     		ldr	r3, [r2, #4]
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2722              		.loc 1 1472 25 view .LVU893
+ 2723 018c 43F40043 		orr	r3, r3, #32768
+ 2724 0190 5360     		str	r3, [r2, #4]
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 2725              		.loc 1 1474 5 is_stmt 1 view .LVU894
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 2726              		.loc 1 1474 17 is_stmt 0 view .LVU895
+ 2727 0192 2023     		movs	r3, #32
+ 2728 0194 84F84130 		strb	r3, [r4, #65]
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2729              		.loc 1 1475 5 is_stmt 1 view .LVU896
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2730              		.loc 1 1475 17 is_stmt 0 view .LVU897
+ 2731 0198 0023     		movs	r3, #0
+ARM GAS  /tmp/ccbUHtu7.s 			page 183
+
+
+ 2732 019a 84F84230 		strb	r3, [r4, #66]
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2733              		.loc 1 1478 5 is_stmt 1 view .LVU898
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2734              		.loc 1 1478 5 view .LVU899
+ 2735 019e 84F84030 		strb	r3, [r4, #64]
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2736              		.loc 1 1478 5 view .LVU900
+1480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 2737              		.loc 1 1480 5 view .LVU901
+1480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 2738              		.loc 1 1480 12 is_stmt 0 view .LVU902
+ 2739 01a2 00E0     		b	.L183
+ 2740              	.LVL170:
+ 2741              	.L195:
+1484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 2742              		.loc 1 1484 12 view .LVU903
+ 2743 01a4 0220     		movs	r0, #2
+ 2744              	.LVL171:
+ 2745              	.L183:
+1486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2746              		.loc 1 1486 1 view .LVU904
+ 2747 01a6 02B0     		add	sp, sp, #8
+ 2748              	.LCFI29:
+ 2749              		.cfi_remember_state
+ 2750              		.cfi_def_cfa_offset 24
+ 2751              		@ sp needed
+ 2752 01a8 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 2753              	.LVL172:
+ 2754              	.L196:
+ 2755              	.LCFI30:
+ 2756              		.cfi_restore_state
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2757              		.loc 1 1367 5 view .LVU905
+ 2758 01ac 0220     		movs	r0, #2
+ 2759              	.LVL173:
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2760              		.loc 1 1367 5 view .LVU906
+ 2761 01ae FAE7     		b	.L183
+ 2762              		.cfi_endproc
+ 2763              	.LFE335:
+ 2765              		.section	.text.HAL_I2C_Slave_Receive,"ax",%progbits
+ 2766              		.align	1
+ 2767              		.global	HAL_I2C_Slave_Receive
+ 2768              		.syntax unified
+ 2769              		.thumb
+ 2770              		.thumb_func
+ 2772              	HAL_I2C_Slave_Receive:
+ 2773              	.LVL174:
+ 2774              	.LFB336:
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 2775              		.loc 1 1499 1 is_stmt 1 view -0
+ 2776              		.cfi_startproc
+ 2777              		@ args = 0, pretend = 0, frame = 0
+ 2778              		@ frame_needed = 0, uses_anonymous_args = 0
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 2779              		.loc 1 1499 1 is_stmt 0 view .LVU908
+ARM GAS  /tmp/ccbUHtu7.s 			page 184
+
+
+ 2780 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 2781              	.LCFI31:
+ 2782              		.cfi_def_cfa_offset 24
+ 2783              		.cfi_offset 4, -24
+ 2784              		.cfi_offset 5, -20
+ 2785              		.cfi_offset 6, -16
+ 2786              		.cfi_offset 7, -12
+ 2787              		.cfi_offset 8, -8
+ 2788              		.cfi_offset 14, -4
+ 2789 0004 82B0     		sub	sp, sp, #8
+ 2790              	.LCFI32:
+ 2791              		.cfi_def_cfa_offset 32
+ 2792 0006 1D46     		mov	r5, r3
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2793              		.loc 1 1500 3 is_stmt 1 view .LVU909
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 2794              		.loc 1 1502 3 view .LVU910
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 2795              		.loc 1 1502 11 is_stmt 0 view .LVU911
+ 2796 0008 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 2797              	.LVL175:
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 2798              		.loc 1 1502 11 view .LVU912
+ 2799 000c DBB2     		uxtb	r3, r3
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 2800              		.loc 1 1502 6 view .LVU913
+ 2801 000e 202B     		cmp	r3, #32
+ 2802 0010 40F0AF80 		bne	.L215
+ 2803 0014 0446     		mov	r4, r0
+ 2804 0016 0E46     		mov	r6, r1
+ 2805 0018 9046     		mov	r8, r2
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2806              		.loc 1 1504 5 is_stmt 1 view .LVU914
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2807              		.loc 1 1504 8 is_stmt 0 view .LVU915
+ 2808 001a 61B3     		cbz	r1, .L206
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2809              		.loc 1 1504 25 discriminator 1 view .LVU916
+ 2810 001c 5AB3     		cbz	r2, .L206
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2811              		.loc 1 1510 5 is_stmt 1 view .LVU917
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2812              		.loc 1 1510 5 view .LVU918
+ 2813 001e 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 2814 0022 012B     		cmp	r3, #1
+ 2815 0024 00F0A980 		beq	.L216
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2816              		.loc 1 1510 5 discriminator 2 view .LVU919
+ 2817 0028 0123     		movs	r3, #1
+ 2818 002a 80F84030 		strb	r3, [r0, #64]
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2819              		.loc 1 1510 5 discriminator 2 view .LVU920
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2820              		.loc 1 1513 5 discriminator 2 view .LVU921
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2821              		.loc 1 1513 17 is_stmt 0 discriminator 2 view .LVU922
+ 2822 002e FFF7FEFF 		bl	HAL_GetTick
+ARM GAS  /tmp/ccbUHtu7.s 			page 185
+
+
+ 2823              	.LVL176:
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2824              		.loc 1 1513 17 discriminator 2 view .LVU923
+ 2825 0032 0746     		mov	r7, r0
+ 2826              	.LVL177:
+1515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 2827              		.loc 1 1515 5 is_stmt 1 discriminator 2 view .LVU924
+1515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 2828              		.loc 1 1515 21 is_stmt 0 discriminator 2 view .LVU925
+ 2829 0034 2223     		movs	r3, #34
+ 2830 0036 84F84130 		strb	r3, [r4, #65]
+1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 2831              		.loc 1 1516 5 is_stmt 1 discriminator 2 view .LVU926
+1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 2832              		.loc 1 1516 21 is_stmt 0 discriminator 2 view .LVU927
+ 2833 003a 2023     		movs	r3, #32
+ 2834 003c 84F84230 		strb	r3, [r4, #66]
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2835              		.loc 1 1517 5 is_stmt 1 discriminator 2 view .LVU928
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2836              		.loc 1 1517 21 is_stmt 0 discriminator 2 view .LVU929
+ 2837 0040 0022     		movs	r2, #0
+ 2838 0042 6264     		str	r2, [r4, #68]
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 2839              		.loc 1 1520 5 is_stmt 1 discriminator 2 view .LVU930
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 2840              		.loc 1 1520 21 is_stmt 0 discriminator 2 view .LVU931
+ 2841 0044 6662     		str	r6, [r4, #36]
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize = hi2c->XferCount;
+ 2842              		.loc 1 1521 5 is_stmt 1 discriminator 2 view .LVU932
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize = hi2c->XferCount;
+ 2843              		.loc 1 1521 21 is_stmt 0 discriminator 2 view .LVU933
+ 2844 0046 A4F82A80 		strh	r8, [r4, #42]	@ movhi
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 2845              		.loc 1 1522 5 is_stmt 1 discriminator 2 view .LVU934
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 2846              		.loc 1 1522 26 is_stmt 0 discriminator 2 view .LVU935
+ 2847 004a 638D     		ldrh	r3, [r4, #42]
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 2848              		.loc 1 1522 20 discriminator 2 view .LVU936
+ 2849 004c 2385     		strh	r3, [r4, #40]	@ movhi
+1523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2850              		.loc 1 1523 5 is_stmt 1 discriminator 2 view .LVU937
+1523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2851              		.loc 1 1523 21 is_stmt 0 discriminator 2 view .LVU938
+ 2852 004e 6263     		str	r2, [r4, #52]
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2853              		.loc 1 1526 5 is_stmt 1 discriminator 2 view .LVU939
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2854              		.loc 1 1526 9 is_stmt 0 discriminator 2 view .LVU940
+ 2855 0050 2168     		ldr	r1, [r4]
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2856              		.loc 1 1526 19 discriminator 2 view .LVU941
+ 2857 0052 4B68     		ldr	r3, [r1, #4]
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2858              		.loc 1 1526 25 discriminator 2 view .LVU942
+ 2859 0054 23F40043 		bic	r3, r3, #32768
+ARM GAS  /tmp/ccbUHtu7.s 			page 186
+
+
+ 2860 0058 4B60     		str	r3, [r1, #4]
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2861              		.loc 1 1529 5 is_stmt 1 discriminator 2 view .LVU943
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2862              		.loc 1 1529 9 is_stmt 0 discriminator 2 view .LVU944
+ 2863 005a 0090     		str	r0, [sp]
+ 2864 005c 2B46     		mov	r3, r5
+ 2865 005e 0821     		movs	r1, #8
+ 2866 0060 2046     		mov	r0, r4
+ 2867              	.LVL178:
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2868              		.loc 1 1529 9 discriminator 2 view .LVU945
+ 2869 0062 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2870              	.LVL179:
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2871              		.loc 1 1529 8 discriminator 2 view .LVU946
+ 2872 0066 58B1     		cbz	r0, .L208
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2873              		.loc 1 1532 7 is_stmt 1 view .LVU947
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2874              		.loc 1 1532 11 is_stmt 0 view .LVU948
+ 2875 0068 2268     		ldr	r2, [r4]
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2876              		.loc 1 1532 21 view .LVU949
+ 2877 006a 5368     		ldr	r3, [r2, #4]
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2878              		.loc 1 1532 27 view .LVU950
+ 2879 006c 43F40043 		orr	r3, r3, #32768
+ 2880 0070 5360     		str	r3, [r2, #4]
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2881              		.loc 1 1533 7 is_stmt 1 view .LVU951
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2882              		.loc 1 1533 14 is_stmt 0 view .LVU952
+ 2883 0072 0120     		movs	r0, #1
+ 2884 0074 7EE0     		b	.L205
+ 2885              	.LVL180:
+ 2886              	.L206:
+1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 2887              		.loc 1 1506 7 is_stmt 1 view .LVU953
+1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 2888              		.loc 1 1506 23 is_stmt 0 view .LVU954
+ 2889 0076 4FF40073 		mov	r3, #512
+ 2890 007a 6364     		str	r3, [r4, #68]
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2891              		.loc 1 1507 7 is_stmt 1 view .LVU955
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2892              		.loc 1 1507 15 is_stmt 0 view .LVU956
+ 2893 007c 0120     		movs	r0, #1
+ 2894              	.LVL181:
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2895              		.loc 1 1507 15 view .LVU957
+ 2896 007e 79E0     		b	.L205
+ 2897              	.LVL182:
+ 2898              	.L208:
+1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2899              		.loc 1 1537 5 is_stmt 1 view .LVU958
+ 2900 0080 2368     		ldr	r3, [r4]
+ARM GAS  /tmp/ccbUHtu7.s 			page 187
+
+
+ 2901 0082 0822     		movs	r2, #8
+ 2902 0084 DA61     		str	r2, [r3, #28]
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2903              		.loc 1 1540 5 view .LVU959
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2904              		.loc 1 1540 9 is_stmt 0 view .LVU960
+ 2905 0086 0097     		str	r7, [sp]
+ 2906 0088 2B46     		mov	r3, r5
+ 2907 008a 0122     		movs	r2, #1
+ 2908 008c 4FF48031 		mov	r1, #65536
+ 2909 0090 2046     		mov	r0, r4
+ 2910 0092 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2911              	.LVL183:
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2912              		.loc 1 1540 8 view .LVU961
+ 2913 0096 D0B1     		cbz	r0, .L209
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2914              		.loc 1 1543 7 is_stmt 1 view .LVU962
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2915              		.loc 1 1543 11 is_stmt 0 view .LVU963
+ 2916 0098 2268     		ldr	r2, [r4]
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2917              		.loc 1 1543 21 view .LVU964
+ 2918 009a 5368     		ldr	r3, [r2, #4]
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 2919              		.loc 1 1543 27 view .LVU965
+ 2920 009c 43F40043 		orr	r3, r3, #32768
+ 2921 00a0 5360     		str	r3, [r2, #4]
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2922              		.loc 1 1544 7 is_stmt 1 view .LVU966
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2923              		.loc 1 1544 14 is_stmt 0 view .LVU967
+ 2924 00a2 0120     		movs	r0, #1
+ 2925 00a4 66E0     		b	.L205
+ 2926              	.L210:
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2927              		.loc 1 1572 7 is_stmt 1 view .LVU968
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2928              		.loc 1 1572 38 is_stmt 0 view .LVU969
+ 2929 00a6 2368     		ldr	r3, [r4]
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2930              		.loc 1 1572 48 view .LVU970
+ 2931 00a8 5A6A     		ldr	r2, [r3, #36]
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2932              		.loc 1 1572 12 view .LVU971
+ 2933 00aa 636A     		ldr	r3, [r4, #36]
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2934              		.loc 1 1572 23 view .LVU972
+ 2935 00ac 1A70     		strb	r2, [r3]
+1575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2936              		.loc 1 1575 7 is_stmt 1 view .LVU973
+1575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2937              		.loc 1 1575 11 is_stmt 0 view .LVU974
+ 2938 00ae 636A     		ldr	r3, [r4, #36]
+1575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2939              		.loc 1 1575 21 view .LVU975
+ 2940 00b0 0133     		adds	r3, r3, #1
+ARM GAS  /tmp/ccbUHtu7.s 			page 188
+
+
+ 2941 00b2 6362     		str	r3, [r4, #36]
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+ 2942              		.loc 1 1577 7 is_stmt 1 view .LVU976
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+ 2943              		.loc 1 1577 11 is_stmt 0 view .LVU977
+ 2944 00b4 B4F82AC0 		ldrh	ip, [r4, #42]
+ 2945 00b8 1FFA8CFC 		uxth	ip, ip
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+ 2946              		.loc 1 1577 22 view .LVU978
+ 2947 00bc 0CF1FF3C 		add	ip, ip, #-1
+ 2948 00c0 1FFA8CFC 		uxth	ip, ip
+ 2949 00c4 A4F82AC0 		strh	ip, [r4, #42]	@ movhi
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2950              		.loc 1 1578 7 is_stmt 1 view .LVU979
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2951              		.loc 1 1578 11 is_stmt 0 view .LVU980
+ 2952 00c8 238D     		ldrh	r3, [r4, #40]
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 2953              		.loc 1 1578 21 view .LVU981
+ 2954 00ca 013B     		subs	r3, r3, #1
+ 2955 00cc 2385     		strh	r3, [r4, #40]	@ movhi
+ 2956              	.L209:
+1547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2957              		.loc 1 1547 28 is_stmt 1 view .LVU982
+1547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2958              		.loc 1 1547 16 is_stmt 0 view .LVU983
+ 2959 00ce 638D     		ldrh	r3, [r4, #42]
+ 2960 00d0 9BB2     		uxth	r3, r3
+1547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 2961              		.loc 1 1547 28 view .LVU984
+ 2962 00d2 03B3     		cbz	r3, .L218
+1550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2963              		.loc 1 1550 7 is_stmt 1 view .LVU985
+1550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2964              		.loc 1 1550 11 is_stmt 0 view .LVU986
+ 2965 00d4 3A46     		mov	r2, r7
+ 2966 00d6 2946     		mov	r1, r5
+ 2967 00d8 2046     		mov	r0, r4
+ 2968 00da FFF7FEFF 		bl	I2C_WaitOnRXNEFlagUntilTimeout
+ 2969              	.LVL184:
+1550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 2970              		.loc 1 1550 10 view .LVU987
+ 2971 00de 0028     		cmp	r0, #0
+ 2972 00e0 E1D0     		beq	.L210
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2973              		.loc 1 1553 9 is_stmt 1 view .LVU988
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2974              		.loc 1 1553 13 is_stmt 0 view .LVU989
+ 2975 00e2 2268     		ldr	r2, [r4]
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2976              		.loc 1 1553 23 view .LVU990
+ 2977 00e4 5368     		ldr	r3, [r2, #4]
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2978              		.loc 1 1553 29 view .LVU991
+ 2979 00e6 43F40043 		orr	r3, r3, #32768
+ 2980 00ea 5360     		str	r3, [r2, #4]
+1556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ARM GAS  /tmp/ccbUHtu7.s 			page 189
+
+
+ 2981              		.loc 1 1556 9 is_stmt 1 view .LVU992
+1556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 2982              		.loc 1 1556 13 is_stmt 0 view .LVU993
+ 2983 00ec 2368     		ldr	r3, [r4]
+ 2984 00ee 9A69     		ldr	r2, [r3, #24]
+1556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 2985              		.loc 1 1556 12 view .LVU994
+ 2986 00f0 12F0040F 		tst	r2, #4
+ 2987 00f4 0DD0     		beq	.L211
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2988              		.loc 1 1559 11 is_stmt 1 view .LVU995
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2989              		.loc 1 1559 52 is_stmt 0 view .LVU996
+ 2990 00f6 5A6A     		ldr	r2, [r3, #36]
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2991              		.loc 1 1559 16 view .LVU997
+ 2992 00f8 636A     		ldr	r3, [r4, #36]
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2993              		.loc 1 1559 27 view .LVU998
+ 2994 00fa 1A70     		strb	r2, [r3]
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2995              		.loc 1 1562 11 is_stmt 1 view .LVU999
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2996              		.loc 1 1562 15 is_stmt 0 view .LVU1000
+ 2997 00fc 636A     		ldr	r3, [r4, #36]
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 2998              		.loc 1 1562 25 view .LVU1001
+ 2999 00fe 0133     		adds	r3, r3, #1
+ 3000 0100 6362     		str	r3, [r4, #36]
+1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferSize--;
+ 3001              		.loc 1 1564 11 is_stmt 1 view .LVU1002
+1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferSize--;
+ 3002              		.loc 1 1564 15 is_stmt 0 view .LVU1003
+ 3003 0102 638D     		ldrh	r3, [r4, #42]
+ 3004 0104 9BB2     		uxth	r3, r3
+1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           hi2c->XferSize--;
+ 3005              		.loc 1 1564 26 view .LVU1004
+ 3006 0106 013B     		subs	r3, r3, #1
+ 3007 0108 9BB2     		uxth	r3, r3
+ 3008 010a 6385     		strh	r3, [r4, #42]	@ movhi
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 3009              		.loc 1 1565 11 is_stmt 1 view .LVU1005
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 3010              		.loc 1 1565 15 is_stmt 0 view .LVU1006
+ 3011 010c 238D     		ldrh	r3, [r4, #40]
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 3012              		.loc 1 1565 25 view .LVU1007
+ 3013 010e 013B     		subs	r3, r3, #1
+ 3014 0110 2385     		strh	r3, [r4, #40]	@ movhi
+ 3015              	.L211:
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 3016              		.loc 1 1568 9 is_stmt 1 view .LVU1008
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 3017              		.loc 1 1568 16 is_stmt 0 view .LVU1009
+ 3018 0112 0120     		movs	r0, #1
+ 3019 0114 2EE0     		b	.L205
+ 3020              	.L218:
+ARM GAS  /tmp/ccbUHtu7.s 			page 190
+
+
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3021              		.loc 1 1582 5 is_stmt 1 view .LVU1010
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3022              		.loc 1 1582 9 is_stmt 0 view .LVU1011
+ 3023 0116 3A46     		mov	r2, r7
+ 3024 0118 2946     		mov	r1, r5
+ 3025 011a 2046     		mov	r0, r4
+ 3026 011c FFF7FEFF 		bl	I2C_WaitOnSTOPFlagUntilTimeout
+ 3027              	.LVL185:
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3028              		.loc 1 1582 8 view .LVU1012
+ 3029 0120 30B1     		cbz	r0, .L213
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 3030              		.loc 1 1585 7 is_stmt 1 view .LVU1013
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 3031              		.loc 1 1585 11 is_stmt 0 view .LVU1014
+ 3032 0122 2268     		ldr	r2, [r4]
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 3033              		.loc 1 1585 21 view .LVU1015
+ 3034 0124 5368     		ldr	r3, [r2, #4]
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 3035              		.loc 1 1585 27 view .LVU1016
+ 3036 0126 43F40043 		orr	r3, r3, #32768
+ 3037 012a 5360     		str	r3, [r2, #4]
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3038              		.loc 1 1586 7 is_stmt 1 view .LVU1017
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3039              		.loc 1 1586 14 is_stmt 0 view .LVU1018
+ 3040 012c 0120     		movs	r0, #1
+ 3041 012e 21E0     		b	.L205
+ 3042              	.L213:
+1590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3043              		.loc 1 1590 5 is_stmt 1 view .LVU1019
+ 3044 0130 2368     		ldr	r3, [r4]
+ 3045 0132 2022     		movs	r2, #32
+ 3046 0134 DA61     		str	r2, [r3, #28]
+1593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3047              		.loc 1 1593 5 view .LVU1020
+1593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3048              		.loc 1 1593 9 is_stmt 0 view .LVU1021
+ 3049 0136 0097     		str	r7, [sp]
+ 3050 0138 2B46     		mov	r3, r5
+ 3051 013a 0122     		movs	r2, #1
+ 3052 013c 4FF40041 		mov	r1, #32768
+ 3053 0140 2046     		mov	r0, r4
+ 3054 0142 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 3055              	.LVL186:
+1593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3056              		.loc 1 1593 8 view .LVU1022
+ 3057 0146 30B1     		cbz	r0, .L214
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 3058              		.loc 1 1596 7 is_stmt 1 view .LVU1023
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 3059              		.loc 1 1596 11 is_stmt 0 view .LVU1024
+ 3060 0148 2268     		ldr	r2, [r4]
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 3061              		.loc 1 1596 21 view .LVU1025
+ARM GAS  /tmp/ccbUHtu7.s 			page 191
+
+
+ 3062 014a 5368     		ldr	r3, [r2, #4]
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 3063              		.loc 1 1596 27 view .LVU1026
+ 3064 014c 43F40043 		orr	r3, r3, #32768
+ 3065 0150 5360     		str	r3, [r2, #4]
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3066              		.loc 1 1597 7 is_stmt 1 view .LVU1027
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3067              		.loc 1 1597 14 is_stmt 0 view .LVU1028
+ 3068 0152 0120     		movs	r0, #1
+ 3069 0154 0EE0     		b	.L205
+ 3070              	.L214:
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3071              		.loc 1 1601 5 is_stmt 1 view .LVU1029
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3072              		.loc 1 1601 9 is_stmt 0 view .LVU1030
+ 3073 0156 2268     		ldr	r2, [r4]
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3074              		.loc 1 1601 19 view .LVU1031
+ 3075 0158 5368     		ldr	r3, [r2, #4]
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3076              		.loc 1 1601 25 view .LVU1032
+ 3077 015a 43F40043 		orr	r3, r3, #32768
+ 3078 015e 5360     		str	r3, [r2, #4]
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 3079              		.loc 1 1603 5 is_stmt 1 view .LVU1033
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 3080              		.loc 1 1603 17 is_stmt 0 view .LVU1034
+ 3081 0160 2023     		movs	r3, #32
+ 3082 0162 84F84130 		strb	r3, [r4, #65]
+1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3083              		.loc 1 1604 5 is_stmt 1 view .LVU1035
+1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3084              		.loc 1 1604 17 is_stmt 0 view .LVU1036
+ 3085 0166 0023     		movs	r3, #0
+ 3086 0168 84F84230 		strb	r3, [r4, #66]
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3087              		.loc 1 1607 5 is_stmt 1 view .LVU1037
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3088              		.loc 1 1607 5 view .LVU1038
+ 3089 016c 84F84030 		strb	r3, [r4, #64]
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3090              		.loc 1 1607 5 view .LVU1039
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3091              		.loc 1 1609 5 view .LVU1040
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3092              		.loc 1 1609 12 is_stmt 0 view .LVU1041
+ 3093 0170 00E0     		b	.L205
+ 3094              	.LVL187:
+ 3095              	.L215:
+1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3096              		.loc 1 1613 12 view .LVU1042
+ 3097 0172 0220     		movs	r0, #2
+ 3098              	.LVL188:
+ 3099              	.L205:
+1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3100              		.loc 1 1615 1 view .LVU1043
+ARM GAS  /tmp/ccbUHtu7.s 			page 192
+
+
+ 3101 0174 02B0     		add	sp, sp, #8
+ 3102              	.LCFI33:
+ 3103              		.cfi_remember_state
+ 3104              		.cfi_def_cfa_offset 24
+ 3105              		@ sp needed
+ 3106 0176 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 3107              	.LVL189:
+ 3108              	.L216:
+ 3109              	.LCFI34:
+ 3110              		.cfi_restore_state
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3111              		.loc 1 1510 5 view .LVU1044
+ 3112 017a 0220     		movs	r0, #2
+ 3113              	.LVL190:
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3114              		.loc 1 1510 5 view .LVU1045
+ 3115 017c FAE7     		b	.L205
+ 3116              		.cfi_endproc
+ 3117              	.LFE336:
+ 3119              		.section	.text.HAL_I2C_Master_Transmit_IT,"ax",%progbits
+ 3120              		.align	1
+ 3121              		.global	HAL_I2C_Master_Transmit_IT
+ 3122              		.syntax unified
+ 3123              		.thumb
+ 3124              		.thumb_func
+ 3126              	HAL_I2C_Master_Transmit_IT:
+ 3127              	.LVL191:
+ 3128              	.LFB337:
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 3129              		.loc 1 1629 1 is_stmt 1 view -0
+ 3130              		.cfi_startproc
+ 3131              		@ args = 0, pretend = 0, frame = 0
+ 3132              		@ frame_needed = 0, uses_anonymous_args = 0
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 3133              		.loc 1 1629 1 is_stmt 0 view .LVU1047
+ 3134 0000 30B5     		push	{r4, r5, lr}
+ 3135              	.LCFI35:
+ 3136              		.cfi_def_cfa_offset 12
+ 3137              		.cfi_offset 4, -12
+ 3138              		.cfi_offset 5, -8
+ 3139              		.cfi_offset 14, -4
+ 3140 0002 83B0     		sub	sp, sp, #12
+ 3141              	.LCFI36:
+ 3142              		.cfi_def_cfa_offset 24
+ 3143 0004 0446     		mov	r4, r0
+1630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3144              		.loc 1 1630 3 is_stmt 1 view .LVU1048
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3145              		.loc 1 1632 3 view .LVU1049
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3146              		.loc 1 1632 11 is_stmt 0 view .LVU1050
+ 3147 0006 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 3148              	.LVL192:
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3149              		.loc 1 1632 11 view .LVU1051
+ 3150 000a C0B2     		uxtb	r0, r0
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 193
+
+
+ 3151              		.loc 1 1632 6 view .LVU1052
+ 3152 000c 2028     		cmp	r0, #32
+ 3153 000e 37D1     		bne	.L223
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3154              		.loc 1 1634 5 is_stmt 1 view .LVU1053
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3155              		.loc 1 1634 9 is_stmt 0 view .LVU1054
+ 3156 0010 2068     		ldr	r0, [r4]
+ 3157 0012 8069     		ldr	r0, [r0, #24]
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3158              		.loc 1 1634 8 view .LVU1055
+ 3159 0014 10F4004F 		tst	r0, #32768
+ 3160 0018 34D1     		bne	.L224
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3161              		.loc 1 1640 5 is_stmt 1 view .LVU1056
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3162              		.loc 1 1640 5 view .LVU1057
+ 3163 001a 94F84000 		ldrb	r0, [r4, #64]	@ zero_extendqisi2
+ 3164 001e 0128     		cmp	r0, #1
+ 3165 0020 32D0     		beq	.L225
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3166              		.loc 1 1640 5 discriminator 2 view .LVU1058
+ 3167 0022 0120     		movs	r0, #1
+ 3168 0024 84F84000 		strb	r0, [r4, #64]
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3169              		.loc 1 1640 5 discriminator 2 view .LVU1059
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 3170              		.loc 1 1642 5 discriminator 2 view .LVU1060
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 3171              		.loc 1 1642 23 is_stmt 0 discriminator 2 view .LVU1061
+ 3172 0028 2120     		movs	r0, #33
+ 3173 002a 84F84100 		strb	r0, [r4, #65]
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3174              		.loc 1 1643 5 is_stmt 1 discriminator 2 view .LVU1062
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3175              		.loc 1 1643 23 is_stmt 0 discriminator 2 view .LVU1063
+ 3176 002e 1020     		movs	r0, #16
+ 3177 0030 84F84200 		strb	r0, [r4, #66]
+1644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3178              		.loc 1 1644 5 is_stmt 1 discriminator 2 view .LVU1064
+1644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3179              		.loc 1 1644 23 is_stmt 0 discriminator 2 view .LVU1065
+ 3180 0034 0020     		movs	r0, #0
+ 3181 0036 6064     		str	r0, [r4, #68]
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3182              		.loc 1 1647 5 is_stmt 1 discriminator 2 view .LVU1066
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3183              		.loc 1 1647 23 is_stmt 0 discriminator 2 view .LVU1067
+ 3184 0038 6262     		str	r2, [r4, #36]
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3185              		.loc 1 1648 5 is_stmt 1 discriminator 2 view .LVU1068
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3186              		.loc 1 1648 23 is_stmt 0 discriminator 2 view .LVU1069
+ 3187 003a 6385     		strh	r3, [r4, #42]	@ movhi
+1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 3188              		.loc 1 1649 5 is_stmt 1 discriminator 2 view .LVU1070
+1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ARM GAS  /tmp/ccbUHtu7.s 			page 194
+
+
+ 3189              		.loc 1 1649 23 is_stmt 0 discriminator 2 view .LVU1071
+ 3190 003c 134B     		ldr	r3, .L227
+ 3191              	.LVL193:
+1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 3192              		.loc 1 1649 23 discriminator 2 view .LVU1072
+ 3193 003e E362     		str	r3, [r4, #44]
+ 3194              	.LVL194:
+1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3195              		.loc 1 1650 5 is_stmt 1 discriminator 2 view .LVU1073
+1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3196              		.loc 1 1650 23 is_stmt 0 discriminator 2 view .LVU1074
+ 3197 0040 134B     		ldr	r3, .L227+4
+ 3198 0042 6363     		str	r3, [r4, #52]
+1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3199              		.loc 1 1652 5 is_stmt 1 discriminator 2 view .LVU1075
+1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3200              		.loc 1 1652 13 is_stmt 0 discriminator 2 view .LVU1076
+ 3201 0044 638D     		ldrh	r3, [r4, #42]
+ 3202 0046 9BB2     		uxth	r3, r3
+1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3203              		.loc 1 1652 8 discriminator 2 view .LVU1077
+ 3204 0048 FF2B     		cmp	r3, #255
+ 3205 004a 14D9     		bls	.L221
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 3206              		.loc 1 1654 7 is_stmt 1 view .LVU1078
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 3207              		.loc 1 1654 22 is_stmt 0 view .LVU1079
+ 3208 004c FF23     		movs	r3, #255
+ 3209 004e 2385     		strh	r3, [r4, #40]	@ movhi
+1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3210              		.loc 1 1655 7 is_stmt 1 view .LVU1080
+ 3211              	.LVL195:
+1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3212              		.loc 1 1655 16 is_stmt 0 view .LVU1081
+ 3213 0050 4FF08073 		mov	r3, #16777216
+ 3214              	.LVL196:
+ 3215              	.L222:
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3216              		.loc 1 1665 5 is_stmt 1 view .LVU1082
+ 3217 0054 0F4A     		ldr	r2, .L227+8
+ 3218              	.LVL197:
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3219              		.loc 1 1665 5 is_stmt 0 view .LVU1083
+ 3220 0056 0092     		str	r2, [sp]
+ 3221              	.LVL198:
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3222              		.loc 1 1665 5 view .LVU1084
+ 3223 0058 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 3224 005c 2046     		mov	r0, r4
+ 3225 005e FFF7FEFF 		bl	I2C_TransferConfig
+ 3226              	.LVL199:
+1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3227              		.loc 1 1668 5 is_stmt 1 view .LVU1085
+1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3228              		.loc 1 1668 5 view .LVU1086
+ 3229 0062 0025     		movs	r5, #0
+ 3230 0064 84F84050 		strb	r5, [r4, #64]
+ARM GAS  /tmp/ccbUHtu7.s 			page 195
+
+
+1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3231              		.loc 1 1668 5 view .LVU1087
+1678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3232              		.loc 1 1678 5 view .LVU1088
+ 3233 0068 0121     		movs	r1, #1
+ 3234 006a 2046     		mov	r0, r4
+ 3235 006c FFF7FEFF 		bl	I2C_Enable_IRQ
+ 3236              	.LVL200:
+1680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3237              		.loc 1 1680 5 view .LVU1089
+1680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3238              		.loc 1 1680 12 is_stmt 0 view .LVU1090
+ 3239 0070 2846     		mov	r0, r5
+ 3240              	.LVL201:
+ 3241              	.L220:
+1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3242              		.loc 1 1686 1 view .LVU1091
+ 3243 0072 03B0     		add	sp, sp, #12
+ 3244              	.LCFI37:
+ 3245              		.cfi_remember_state
+ 3246              		.cfi_def_cfa_offset 12
+ 3247              		@ sp needed
+ 3248 0074 30BD     		pop	{r4, r5, pc}
+ 3249              	.LVL202:
+ 3250              	.L221:
+ 3251              	.LCFI38:
+ 3252              		.cfi_restore_state
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3253              		.loc 1 1659 7 is_stmt 1 view .LVU1092
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3254              		.loc 1 1659 28 is_stmt 0 view .LVU1093
+ 3255 0076 638D     		ldrh	r3, [r4, #42]
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3256              		.loc 1 1659 22 view .LVU1094
+ 3257 0078 2385     		strh	r3, [r4, #40]	@ movhi
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3258              		.loc 1 1660 7 is_stmt 1 view .LVU1095
+ 3259              	.LVL203:
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3260              		.loc 1 1660 16 is_stmt 0 view .LVU1096
+ 3261 007a 4FF00073 		mov	r3, #33554432
+ 3262 007e E9E7     		b	.L222
+ 3263              	.LVL204:
+ 3264              	.L223:
+1684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3265              		.loc 1 1684 12 view .LVU1097
+ 3266 0080 0220     		movs	r0, #2
+ 3267 0082 F6E7     		b	.L220
+ 3268              	.L224:
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3269              		.loc 1 1636 14 view .LVU1098
+ 3270 0084 0220     		movs	r0, #2
+ 3271 0086 F4E7     		b	.L220
+ 3272              	.L225:
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3273              		.loc 1 1640 5 view .LVU1099
+ 3274 0088 0220     		movs	r0, #2
+ARM GAS  /tmp/ccbUHtu7.s 			page 196
+
+
+ 3275 008a F2E7     		b	.L220
+ 3276              	.L228:
+ 3277              		.align	2
+ 3278              	.L227:
+ 3279 008c 0000FFFF 		.word	-65536
+ 3280 0090 00000000 		.word	I2C_Master_ISR_IT
+ 3281 0094 00200080 		.word	-2147475456
+ 3282              		.cfi_endproc
+ 3283              	.LFE337:
+ 3285              		.section	.text.HAL_I2C_Master_Receive_IT,"ax",%progbits
+ 3286              		.align	1
+ 3287              		.global	HAL_I2C_Master_Receive_IT
+ 3288              		.syntax unified
+ 3289              		.thumb
+ 3290              		.thumb_func
+ 3292              	HAL_I2C_Master_Receive_IT:
+ 3293              	.LVL205:
+ 3294              	.LFB338:
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 3295              		.loc 1 1700 1 is_stmt 1 view -0
+ 3296              		.cfi_startproc
+ 3297              		@ args = 0, pretend = 0, frame = 0
+ 3298              		@ frame_needed = 0, uses_anonymous_args = 0
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 3299              		.loc 1 1700 1 is_stmt 0 view .LVU1101
+ 3300 0000 30B5     		push	{r4, r5, lr}
+ 3301              	.LCFI39:
+ 3302              		.cfi_def_cfa_offset 12
+ 3303              		.cfi_offset 4, -12
+ 3304              		.cfi_offset 5, -8
+ 3305              		.cfi_offset 14, -4
+ 3306 0002 83B0     		sub	sp, sp, #12
+ 3307              	.LCFI40:
+ 3308              		.cfi_def_cfa_offset 24
+ 3309 0004 0446     		mov	r4, r0
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3310              		.loc 1 1701 3 is_stmt 1 view .LVU1102
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3311              		.loc 1 1703 3 view .LVU1103
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3312              		.loc 1 1703 11 is_stmt 0 view .LVU1104
+ 3313 0006 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 3314              	.LVL206:
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3315              		.loc 1 1703 11 view .LVU1105
+ 3316 000a C0B2     		uxtb	r0, r0
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3317              		.loc 1 1703 6 view .LVU1106
+ 3318 000c 2028     		cmp	r0, #32
+ 3319 000e 37D1     		bne	.L233
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3320              		.loc 1 1705 5 is_stmt 1 view .LVU1107
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3321              		.loc 1 1705 9 is_stmt 0 view .LVU1108
+ 3322 0010 2068     		ldr	r0, [r4]
+ 3323 0012 8069     		ldr	r0, [r0, #24]
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccbUHtu7.s 			page 197
+
+
+ 3324              		.loc 1 1705 8 view .LVU1109
+ 3325 0014 10F4004F 		tst	r0, #32768
+ 3326 0018 34D1     		bne	.L234
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3327              		.loc 1 1711 5 is_stmt 1 view .LVU1110
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3328              		.loc 1 1711 5 view .LVU1111
+ 3329 001a 94F84000 		ldrb	r0, [r4, #64]	@ zero_extendqisi2
+ 3330 001e 0128     		cmp	r0, #1
+ 3331 0020 32D0     		beq	.L235
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3332              		.loc 1 1711 5 discriminator 2 view .LVU1112
+ 3333 0022 0120     		movs	r0, #1
+ 3334 0024 84F84000 		strb	r0, [r4, #64]
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3335              		.loc 1 1711 5 discriminator 2 view .LVU1113
+1713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 3336              		.loc 1 1713 5 discriminator 2 view .LVU1114
+1713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 3337              		.loc 1 1713 23 is_stmt 0 discriminator 2 view .LVU1115
+ 3338 0028 2220     		movs	r0, #34
+ 3339 002a 84F84100 		strb	r0, [r4, #65]
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3340              		.loc 1 1714 5 is_stmt 1 discriminator 2 view .LVU1116
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3341              		.loc 1 1714 23 is_stmt 0 discriminator 2 view .LVU1117
+ 3342 002e 1020     		movs	r0, #16
+ 3343 0030 84F84200 		strb	r0, [r4, #66]
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3344              		.loc 1 1715 5 is_stmt 1 discriminator 2 view .LVU1118
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3345              		.loc 1 1715 23 is_stmt 0 discriminator 2 view .LVU1119
+ 3346 0034 0020     		movs	r0, #0
+ 3347 0036 6064     		str	r0, [r4, #68]
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3348              		.loc 1 1718 5 is_stmt 1 discriminator 2 view .LVU1120
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3349              		.loc 1 1718 23 is_stmt 0 discriminator 2 view .LVU1121
+ 3350 0038 6262     		str	r2, [r4, #36]
+1719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3351              		.loc 1 1719 5 is_stmt 1 discriminator 2 view .LVU1122
+1719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3352              		.loc 1 1719 23 is_stmt 0 discriminator 2 view .LVU1123
+ 3353 003a 6385     		strh	r3, [r4, #42]	@ movhi
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 3354              		.loc 1 1720 5 is_stmt 1 discriminator 2 view .LVU1124
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 3355              		.loc 1 1720 23 is_stmt 0 discriminator 2 view .LVU1125
+ 3356 003c 134B     		ldr	r3, .L237
+ 3357              	.LVL207:
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 3358              		.loc 1 1720 23 discriminator 2 view .LVU1126
+ 3359 003e E362     		str	r3, [r4, #44]
+ 3360              	.LVL208:
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3361              		.loc 1 1721 5 is_stmt 1 discriminator 2 view .LVU1127
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 198
+
+
+ 3362              		.loc 1 1721 23 is_stmt 0 discriminator 2 view .LVU1128
+ 3363 0040 134B     		ldr	r3, .L237+4
+ 3364 0042 6363     		str	r3, [r4, #52]
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3365              		.loc 1 1723 5 is_stmt 1 discriminator 2 view .LVU1129
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3366              		.loc 1 1723 13 is_stmt 0 discriminator 2 view .LVU1130
+ 3367 0044 638D     		ldrh	r3, [r4, #42]
+ 3368 0046 9BB2     		uxth	r3, r3
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3369              		.loc 1 1723 8 discriminator 2 view .LVU1131
+ 3370 0048 FF2B     		cmp	r3, #255
+ 3371 004a 14D9     		bls	.L231
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 3372              		.loc 1 1725 7 is_stmt 1 view .LVU1132
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 3373              		.loc 1 1725 22 is_stmt 0 view .LVU1133
+ 3374 004c FF23     		movs	r3, #255
+ 3375 004e 2385     		strh	r3, [r4, #40]	@ movhi
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3376              		.loc 1 1726 7 is_stmt 1 view .LVU1134
+ 3377              	.LVL209:
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3378              		.loc 1 1726 16 is_stmt 0 view .LVU1135
+ 3379 0050 4FF08073 		mov	r3, #16777216
+ 3380              	.LVL210:
+ 3381              	.L232:
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3382              		.loc 1 1736 5 is_stmt 1 view .LVU1136
+ 3383 0054 0F4A     		ldr	r2, .L237+8
+ 3384              	.LVL211:
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3385              		.loc 1 1736 5 is_stmt 0 view .LVU1137
+ 3386 0056 0092     		str	r2, [sp]
+ 3387              	.LVL212:
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3388              		.loc 1 1736 5 view .LVU1138
+ 3389 0058 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 3390 005c 2046     		mov	r0, r4
+ 3391 005e FFF7FEFF 		bl	I2C_TransferConfig
+ 3392              	.LVL213:
+1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3393              		.loc 1 1739 5 is_stmt 1 view .LVU1139
+1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3394              		.loc 1 1739 5 view .LVU1140
+ 3395 0062 0025     		movs	r5, #0
+ 3396 0064 84F84050 		strb	r5, [r4, #64]
+1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3397              		.loc 1 1739 5 view .LVU1141
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3398              		.loc 1 1749 5 view .LVU1142
+ 3399 0068 0221     		movs	r1, #2
+ 3400 006a 2046     		mov	r0, r4
+ 3401 006c FFF7FEFF 		bl	I2C_Enable_IRQ
+ 3402              	.LVL214:
+1751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3403              		.loc 1 1751 5 view .LVU1143
+ARM GAS  /tmp/ccbUHtu7.s 			page 199
+
+
+1751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3404              		.loc 1 1751 12 is_stmt 0 view .LVU1144
+ 3405 0070 2846     		mov	r0, r5
+ 3406              	.LVL215:
+ 3407              	.L230:
+1757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3408              		.loc 1 1757 1 view .LVU1145
+ 3409 0072 03B0     		add	sp, sp, #12
+ 3410              	.LCFI41:
+ 3411              		.cfi_remember_state
+ 3412              		.cfi_def_cfa_offset 12
+ 3413              		@ sp needed
+ 3414 0074 30BD     		pop	{r4, r5, pc}
+ 3415              	.LVL216:
+ 3416              	.L231:
+ 3417              	.LCFI42:
+ 3418              		.cfi_restore_state
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3419              		.loc 1 1730 7 is_stmt 1 view .LVU1146
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3420              		.loc 1 1730 28 is_stmt 0 view .LVU1147
+ 3421 0076 638D     		ldrh	r3, [r4, #42]
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3422              		.loc 1 1730 22 view .LVU1148
+ 3423 0078 2385     		strh	r3, [r4, #40]	@ movhi
+1731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3424              		.loc 1 1731 7 is_stmt 1 view .LVU1149
+ 3425              	.LVL217:
+1731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3426              		.loc 1 1731 16 is_stmt 0 view .LVU1150
+ 3427 007a 4FF00073 		mov	r3, #33554432
+ 3428 007e E9E7     		b	.L232
+ 3429              	.LVL218:
+ 3430              	.L233:
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3431              		.loc 1 1755 12 view .LVU1151
+ 3432 0080 0220     		movs	r0, #2
+ 3433 0082 F6E7     		b	.L230
+ 3434              	.L234:
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3435              		.loc 1 1707 14 view .LVU1152
+ 3436 0084 0220     		movs	r0, #2
+ 3437 0086 F4E7     		b	.L230
+ 3438              	.L235:
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3439              		.loc 1 1711 5 view .LVU1153
+ 3440 0088 0220     		movs	r0, #2
+ 3441 008a F2E7     		b	.L230
+ 3442              	.L238:
+ 3443              		.align	2
+ 3444              	.L237:
+ 3445 008c 0000FFFF 		.word	-65536
+ 3446 0090 00000000 		.word	I2C_Master_ISR_IT
+ 3447 0094 00240080 		.word	-2147474432
+ 3448              		.cfi_endproc
+ 3449              	.LFE338:
+ 3451              		.section	.text.HAL_I2C_Slave_Transmit_IT,"ax",%progbits
+ARM GAS  /tmp/ccbUHtu7.s 			page 200
+
+
+ 3452              		.align	1
+ 3453              		.global	HAL_I2C_Slave_Transmit_IT
+ 3454              		.syntax unified
+ 3455              		.thumb
+ 3456              		.thumb_func
+ 3458              	HAL_I2C_Slave_Transmit_IT:
+ 3459              	.LVL219:
+ 3460              	.LFB339:
+1768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 3461              		.loc 1 1768 1 is_stmt 1 view -0
+ 3462              		.cfi_startproc
+ 3463              		@ args = 0, pretend = 0, frame = 0
+ 3464              		@ frame_needed = 0, uses_anonymous_args = 0
+1768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 3465              		.loc 1 1768 1 is_stmt 0 view .LVU1155
+ 3466 0000 38B5     		push	{r3, r4, r5, lr}
+ 3467              	.LCFI43:
+ 3468              		.cfi_def_cfa_offset 16
+ 3469              		.cfi_offset 3, -16
+ 3470              		.cfi_offset 4, -12
+ 3471              		.cfi_offset 5, -8
+ 3472              		.cfi_offset 14, -4
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3473              		.loc 1 1769 3 is_stmt 1 view .LVU1156
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3474              		.loc 1 1769 11 is_stmt 0 view .LVU1157
+ 3475 0002 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 3476 0006 DBB2     		uxtb	r3, r3
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3477              		.loc 1 1769 6 view .LVU1158
+ 3478 0008 202B     		cmp	r3, #32
+ 3479 000a 23D1     		bne	.L241
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3480              		.loc 1 1772 5 is_stmt 1 view .LVU1159
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3481              		.loc 1 1772 5 view .LVU1160
+ 3482 000c 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 3483 0010 012B     		cmp	r3, #1
+ 3484 0012 21D0     		beq	.L242
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3485              		.loc 1 1772 5 discriminator 2 view .LVU1161
+ 3486 0014 0123     		movs	r3, #1
+ 3487 0016 80F84030 		strb	r3, [r0, #64]
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3488              		.loc 1 1772 5 discriminator 2 view .LVU1162
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 3489              		.loc 1 1774 5 discriminator 2 view .LVU1163
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 3490              		.loc 1 1774 23 is_stmt 0 discriminator 2 view .LVU1164
+ 3491 001a 2123     		movs	r3, #33
+ 3492 001c 80F84130 		strb	r3, [r0, #65]
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3493              		.loc 1 1775 5 is_stmt 1 discriminator 2 view .LVU1165
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3494              		.loc 1 1775 23 is_stmt 0 discriminator 2 view .LVU1166
+ 3495 0020 2023     		movs	r3, #32
+ 3496 0022 80F84230 		strb	r3, [r0, #66]
+ARM GAS  /tmp/ccbUHtu7.s 			page 201
+
+
+1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3497              		.loc 1 1776 5 is_stmt 1 discriminator 2 view .LVU1167
+1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3498              		.loc 1 1776 23 is_stmt 0 discriminator 2 view .LVU1168
+ 3499 0026 0024     		movs	r4, #0
+ 3500 0028 4464     		str	r4, [r0, #68]
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3501              		.loc 1 1779 5 is_stmt 1 discriminator 2 view .LVU1169
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3502              		.loc 1 1779 9 is_stmt 0 discriminator 2 view .LVU1170
+ 3503 002a 0568     		ldr	r5, [r0]
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3504              		.loc 1 1779 19 discriminator 2 view .LVU1171
+ 3505 002c 6B68     		ldr	r3, [r5, #4]
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3506              		.loc 1 1779 25 discriminator 2 view .LVU1172
+ 3507 002e 23F40043 		bic	r3, r3, #32768
+ 3508 0032 6B60     		str	r3, [r5, #4]
+1782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3509              		.loc 1 1782 5 is_stmt 1 discriminator 2 view .LVU1173
+1782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3510              		.loc 1 1782 23 is_stmt 0 discriminator 2 view .LVU1174
+ 3511 0034 4162     		str	r1, [r0, #36]
+1783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 3512              		.loc 1 1783 5 is_stmt 1 discriminator 2 view .LVU1175
+1783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 3513              		.loc 1 1783 23 is_stmt 0 discriminator 2 view .LVU1176
+ 3514 0036 4285     		strh	r2, [r0, #42]	@ movhi
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3515              		.loc 1 1784 5 is_stmt 1 discriminator 2 view .LVU1177
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3516              		.loc 1 1784 29 is_stmt 0 discriminator 2 view .LVU1178
+ 3517 0038 438D     		ldrh	r3, [r0, #42]
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3518              		.loc 1 1784 23 discriminator 2 view .LVU1179
+ 3519 003a 0385     		strh	r3, [r0, #40]	@ movhi
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 3520              		.loc 1 1785 5 is_stmt 1 discriminator 2 view .LVU1180
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 3521              		.loc 1 1785 23 is_stmt 0 discriminator 2 view .LVU1181
+ 3522 003c 074B     		ldr	r3, .L244
+ 3523 003e C362     		str	r3, [r0, #44]
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3524              		.loc 1 1786 5 is_stmt 1 discriminator 2 view .LVU1182
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3525              		.loc 1 1786 23 is_stmt 0 discriminator 2 view .LVU1183
+ 3526 0040 074B     		ldr	r3, .L244+4
+ 3527 0042 4363     		str	r3, [r0, #52]
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3528              		.loc 1 1789 5 is_stmt 1 discriminator 2 view .LVU1184
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3529              		.loc 1 1789 5 discriminator 2 view .LVU1185
+ 3530 0044 80F84040 		strb	r4, [r0, #64]
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3531              		.loc 1 1789 5 discriminator 2 view .LVU1186
+1799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3532              		.loc 1 1799 5 discriminator 2 view .LVU1187
+ARM GAS  /tmp/ccbUHtu7.s 			page 202
+
+
+ 3533 0048 48F20101 		movw	r1, #32769
+ 3534              	.LVL220:
+1799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3535              		.loc 1 1799 5 is_stmt 0 discriminator 2 view .LVU1188
+ 3536 004c FFF7FEFF 		bl	I2C_Enable_IRQ
+ 3537              	.LVL221:
+1801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3538              		.loc 1 1801 5 is_stmt 1 discriminator 2 view .LVU1189
+1801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3539              		.loc 1 1801 12 is_stmt 0 discriminator 2 view .LVU1190
+ 3540 0050 2046     		mov	r0, r4
+ 3541              	.L240:
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3542              		.loc 1 1807 1 view .LVU1191
+ 3543 0052 38BD     		pop	{r3, r4, r5, pc}
+ 3544              	.LVL222:
+ 3545              	.L241:
+1805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3546              		.loc 1 1805 12 view .LVU1192
+ 3547 0054 0220     		movs	r0, #2
+ 3548              	.LVL223:
+1805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3549              		.loc 1 1805 12 view .LVU1193
+ 3550 0056 FCE7     		b	.L240
+ 3551              	.LVL224:
+ 3552              	.L242:
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3553              		.loc 1 1772 5 view .LVU1194
+ 3554 0058 0220     		movs	r0, #2
+ 3555              	.LVL225:
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3556              		.loc 1 1772 5 view .LVU1195
+ 3557 005a FAE7     		b	.L240
+ 3558              	.L245:
+ 3559              		.align	2
+ 3560              	.L244:
+ 3561 005c 0000FFFF 		.word	-65536
+ 3562 0060 00000000 		.word	I2C_Slave_ISR_IT
+ 3563              		.cfi_endproc
+ 3564              	.LFE339:
+ 3566              		.section	.text.HAL_I2C_Slave_Receive_IT,"ax",%progbits
+ 3567              		.align	1
+ 3568              		.global	HAL_I2C_Slave_Receive_IT
+ 3569              		.syntax unified
+ 3570              		.thumb
+ 3571              		.thumb_func
+ 3573              	HAL_I2C_Slave_Receive_IT:
+ 3574              	.LVL226:
+ 3575              	.LFB340:
+1818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 3576              		.loc 1 1818 1 is_stmt 1 view -0
+ 3577              		.cfi_startproc
+ 3578              		@ args = 0, pretend = 0, frame = 0
+ 3579              		@ frame_needed = 0, uses_anonymous_args = 0
+1818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 3580              		.loc 1 1818 1 is_stmt 0 view .LVU1197
+ 3581 0000 38B5     		push	{r3, r4, r5, lr}
+ARM GAS  /tmp/ccbUHtu7.s 			page 203
+
+
+ 3582              	.LCFI44:
+ 3583              		.cfi_def_cfa_offset 16
+ 3584              		.cfi_offset 3, -16
+ 3585              		.cfi_offset 4, -12
+ 3586              		.cfi_offset 5, -8
+ 3587              		.cfi_offset 14, -4
+1819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3588              		.loc 1 1819 3 is_stmt 1 view .LVU1198
+1819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3589              		.loc 1 1819 11 is_stmt 0 view .LVU1199
+ 3590 0002 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 3591 0006 DBB2     		uxtb	r3, r3
+1819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3592              		.loc 1 1819 6 view .LVU1200
+ 3593 0008 202B     		cmp	r3, #32
+ 3594 000a 23D1     		bne	.L248
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3595              		.loc 1 1822 5 is_stmt 1 view .LVU1201
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3596              		.loc 1 1822 5 view .LVU1202
+ 3597 000c 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 3598 0010 012B     		cmp	r3, #1
+ 3599 0012 21D0     		beq	.L249
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3600              		.loc 1 1822 5 discriminator 2 view .LVU1203
+ 3601 0014 0123     		movs	r3, #1
+ 3602 0016 80F84030 		strb	r3, [r0, #64]
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3603              		.loc 1 1822 5 discriminator 2 view .LVU1204
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 3604              		.loc 1 1824 5 discriminator 2 view .LVU1205
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 3605              		.loc 1 1824 23 is_stmt 0 discriminator 2 view .LVU1206
+ 3606 001a 2223     		movs	r3, #34
+ 3607 001c 80F84130 		strb	r3, [r0, #65]
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3608              		.loc 1 1825 5 is_stmt 1 discriminator 2 view .LVU1207
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3609              		.loc 1 1825 23 is_stmt 0 discriminator 2 view .LVU1208
+ 3610 0020 2023     		movs	r3, #32
+ 3611 0022 80F84230 		strb	r3, [r0, #66]
+1826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3612              		.loc 1 1826 5 is_stmt 1 discriminator 2 view .LVU1209
+1826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3613              		.loc 1 1826 23 is_stmt 0 discriminator 2 view .LVU1210
+ 3614 0026 0024     		movs	r4, #0
+ 3615 0028 4464     		str	r4, [r0, #68]
+1829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3616              		.loc 1 1829 5 is_stmt 1 discriminator 2 view .LVU1211
+1829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3617              		.loc 1 1829 9 is_stmt 0 discriminator 2 view .LVU1212
+ 3618 002a 0568     		ldr	r5, [r0]
+1829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3619              		.loc 1 1829 19 discriminator 2 view .LVU1213
+ 3620 002c 6B68     		ldr	r3, [r5, #4]
+1829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3621              		.loc 1 1829 25 discriminator 2 view .LVU1214
+ARM GAS  /tmp/ccbUHtu7.s 			page 204
+
+
+ 3622 002e 23F40043 		bic	r3, r3, #32768
+ 3623 0032 6B60     		str	r3, [r5, #4]
+1832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3624              		.loc 1 1832 5 is_stmt 1 discriminator 2 view .LVU1215
+1832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3625              		.loc 1 1832 23 is_stmt 0 discriminator 2 view .LVU1216
+ 3626 0034 4162     		str	r1, [r0, #36]
+1833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 3627              		.loc 1 1833 5 is_stmt 1 discriminator 2 view .LVU1217
+1833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 3628              		.loc 1 1833 23 is_stmt 0 discriminator 2 view .LVU1218
+ 3629 0036 4285     		strh	r2, [r0, #42]	@ movhi
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3630              		.loc 1 1834 5 is_stmt 1 discriminator 2 view .LVU1219
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3631              		.loc 1 1834 29 is_stmt 0 discriminator 2 view .LVU1220
+ 3632 0038 438D     		ldrh	r3, [r0, #42]
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3633              		.loc 1 1834 23 discriminator 2 view .LVU1221
+ 3634 003a 0385     		strh	r3, [r0, #40]	@ movhi
+1835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 3635              		.loc 1 1835 5 is_stmt 1 discriminator 2 view .LVU1222
+1835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 3636              		.loc 1 1835 23 is_stmt 0 discriminator 2 view .LVU1223
+ 3637 003c 074B     		ldr	r3, .L251
+ 3638 003e C362     		str	r3, [r0, #44]
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3639              		.loc 1 1836 5 is_stmt 1 discriminator 2 view .LVU1224
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3640              		.loc 1 1836 23 is_stmt 0 discriminator 2 view .LVU1225
+ 3641 0040 074B     		ldr	r3, .L251+4
+ 3642 0042 4363     		str	r3, [r0, #52]
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3643              		.loc 1 1839 5 is_stmt 1 discriminator 2 view .LVU1226
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3644              		.loc 1 1839 5 discriminator 2 view .LVU1227
+ 3645 0044 80F84040 		strb	r4, [r0, #64]
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3646              		.loc 1 1839 5 discriminator 2 view .LVU1228
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3647              		.loc 1 1849 5 discriminator 2 view .LVU1229
+ 3648 0048 48F20201 		movw	r1, #32770
+ 3649              	.LVL227:
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3650              		.loc 1 1849 5 is_stmt 0 discriminator 2 view .LVU1230
+ 3651 004c FFF7FEFF 		bl	I2C_Enable_IRQ
+ 3652              	.LVL228:
+1851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3653              		.loc 1 1851 5 is_stmt 1 discriminator 2 view .LVU1231
+1851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3654              		.loc 1 1851 12 is_stmt 0 discriminator 2 view .LVU1232
+ 3655 0050 2046     		mov	r0, r4
+ 3656              	.L247:
+1857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3657              		.loc 1 1857 1 view .LVU1233
+ 3658 0052 38BD     		pop	{r3, r4, r5, pc}
+ 3659              	.LVL229:
+ARM GAS  /tmp/ccbUHtu7.s 			page 205
+
+
+ 3660              	.L248:
+1855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3661              		.loc 1 1855 12 view .LVU1234
+ 3662 0054 0220     		movs	r0, #2
+ 3663              	.LVL230:
+1855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3664              		.loc 1 1855 12 view .LVU1235
+ 3665 0056 FCE7     		b	.L247
+ 3666              	.LVL231:
+ 3667              	.L249:
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3668              		.loc 1 1822 5 view .LVU1236
+ 3669 0058 0220     		movs	r0, #2
+ 3670              	.LVL232:
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3671              		.loc 1 1822 5 view .LVU1237
+ 3672 005a FAE7     		b	.L247
+ 3673              	.L252:
+ 3674              		.align	2
+ 3675              	.L251:
+ 3676 005c 0000FFFF 		.word	-65536
+ 3677 0060 00000000 		.word	I2C_Slave_ISR_IT
+ 3678              		.cfi_endproc
+ 3679              	.LFE340:
+ 3681              		.section	.text.HAL_I2C_Master_Transmit_DMA,"ax",%progbits
+ 3682              		.align	1
+ 3683              		.global	HAL_I2C_Master_Transmit_DMA
+ 3684              		.syntax unified
+ 3685              		.thumb
+ 3686              		.thumb_func
+ 3688              	HAL_I2C_Master_Transmit_DMA:
+ 3689              	.LVL233:
+ 3690              	.LFB341:
+1871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 3691              		.loc 1 1871 1 is_stmt 1 view -0
+ 3692              		.cfi_startproc
+ 3693              		@ args = 0, pretend = 0, frame = 0
+ 3694              		@ frame_needed = 0, uses_anonymous_args = 0
+1871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 3695              		.loc 1 1871 1 is_stmt 0 view .LVU1239
+ 3696 0000 70B5     		push	{r4, r5, r6, lr}
+ 3697              	.LCFI45:
+ 3698              		.cfi_def_cfa_offset 16
+ 3699              		.cfi_offset 4, -16
+ 3700              		.cfi_offset 5, -12
+ 3701              		.cfi_offset 6, -8
+ 3702              		.cfi_offset 14, -4
+ 3703 0002 82B0     		sub	sp, sp, #8
+ 3704              	.LCFI46:
+ 3705              		.cfi_def_cfa_offset 24
+ 3706 0004 0446     		mov	r4, r0
+1872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 3707              		.loc 1 1872 3 is_stmt 1 view .LVU1240
+1873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3708              		.loc 1 1873 3 view .LVU1241
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3709              		.loc 1 1875 3 view .LVU1242
+ARM GAS  /tmp/ccbUHtu7.s 			page 206
+
+
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3710              		.loc 1 1875 11 is_stmt 0 view .LVU1243
+ 3711 0006 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 3712              	.LVL234:
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3713              		.loc 1 1875 11 view .LVU1244
+ 3714 000a C0B2     		uxtb	r0, r0
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 3715              		.loc 1 1875 6 view .LVU1245
+ 3716 000c 2028     		cmp	r0, #32
+ 3717 000e 40F08D80 		bne	.L262
+ 3718 0012 0D46     		mov	r5, r1
+ 3719 0014 1146     		mov	r1, r2
+ 3720              	.LVL235:
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3721              		.loc 1 1877 5 is_stmt 1 view .LVU1246
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3722              		.loc 1 1877 9 is_stmt 0 view .LVU1247
+ 3723 0016 2268     		ldr	r2, [r4]
+ 3724              	.LVL236:
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3725              		.loc 1 1877 9 view .LVU1248
+ 3726 0018 9269     		ldr	r2, [r2, #24]
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3727              		.loc 1 1877 8 view .LVU1249
+ 3728 001a 12F4004F 		tst	r2, #32768
+ 3729 001e 40F08880 		bne	.L263
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3730              		.loc 1 1883 5 is_stmt 1 view .LVU1250
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3731              		.loc 1 1883 5 view .LVU1251
+ 3732 0022 94F84020 		ldrb	r2, [r4, #64]	@ zero_extendqisi2
+ 3733 0026 012A     		cmp	r2, #1
+ 3734 0028 00F08580 		beq	.L264
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3735              		.loc 1 1883 5 discriminator 2 view .LVU1252
+ 3736 002c 0122     		movs	r2, #1
+ 3737 002e 84F84020 		strb	r2, [r4, #64]
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3738              		.loc 1 1883 5 discriminator 2 view .LVU1253
+1885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 3739              		.loc 1 1885 5 discriminator 2 view .LVU1254
+1885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 3740              		.loc 1 1885 23 is_stmt 0 discriminator 2 view .LVU1255
+ 3741 0032 2122     		movs	r2, #33
+ 3742 0034 84F84120 		strb	r2, [r4, #65]
+1886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3743              		.loc 1 1886 5 is_stmt 1 discriminator 2 view .LVU1256
+1886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3744              		.loc 1 1886 23 is_stmt 0 discriminator 2 view .LVU1257
+ 3745 0038 1022     		movs	r2, #16
+ 3746 003a 84F84220 		strb	r2, [r4, #66]
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3747              		.loc 1 1887 5 is_stmt 1 discriminator 2 view .LVU1258
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3748              		.loc 1 1887 23 is_stmt 0 discriminator 2 view .LVU1259
+ 3749 003e 0022     		movs	r2, #0
+ARM GAS  /tmp/ccbUHtu7.s 			page 207
+
+
+ 3750 0040 6264     		str	r2, [r4, #68]
+1890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3751              		.loc 1 1890 5 is_stmt 1 discriminator 2 view .LVU1260
+1890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3752              		.loc 1 1890 23 is_stmt 0 discriminator 2 view .LVU1261
+ 3753 0042 6162     		str	r1, [r4, #36]
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3754              		.loc 1 1891 5 is_stmt 1 discriminator 2 view .LVU1262
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3755              		.loc 1 1891 23 is_stmt 0 discriminator 2 view .LVU1263
+ 3756 0044 6385     		strh	r3, [r4, #42]	@ movhi
+1892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 3757              		.loc 1 1892 5 is_stmt 1 discriminator 2 view .LVU1264
+1892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 3758              		.loc 1 1892 23 is_stmt 0 discriminator 2 view .LVU1265
+ 3759 0046 3D4B     		ldr	r3, .L268
+ 3760              	.LVL237:
+1892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 3761              		.loc 1 1892 23 discriminator 2 view .LVU1266
+ 3762 0048 E362     		str	r3, [r4, #44]
+ 3763              	.LVL238:
+1893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3764              		.loc 1 1893 5 is_stmt 1 discriminator 2 view .LVU1267
+1893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3765              		.loc 1 1893 23 is_stmt 0 discriminator 2 view .LVU1268
+ 3766 004a 3D4B     		ldr	r3, .L268+4
+ 3767 004c 6363     		str	r3, [r4, #52]
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3768              		.loc 1 1895 5 is_stmt 1 discriminator 2 view .LVU1269
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3769              		.loc 1 1895 13 is_stmt 0 discriminator 2 view .LVU1270
+ 3770 004e 638D     		ldrh	r3, [r4, #42]
+ 3771 0050 9BB2     		uxth	r3, r3
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3772              		.loc 1 1895 8 discriminator 2 view .LVU1271
+ 3773 0052 FF2B     		cmp	r3, #255
+ 3774 0054 27D9     		bls	.L255
+1897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 3775              		.loc 1 1897 7 is_stmt 1 view .LVU1272
+1897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 3776              		.loc 1 1897 22 is_stmt 0 view .LVU1273
+ 3777 0056 FF23     		movs	r3, #255
+ 3778 0058 2385     		strh	r3, [r4, #40]	@ movhi
+1898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3779              		.loc 1 1898 7 is_stmt 1 view .LVU1274
+ 3780              	.LVL239:
+1898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3781              		.loc 1 1898 16 is_stmt 0 view .LVU1275
+ 3782 005a 4FF08076 		mov	r6, #16777216
+ 3783              	.LVL240:
+ 3784              	.L256:
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3785              		.loc 1 1906 5 is_stmt 1 view .LVU1276
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 3786              		.loc 1 1906 13 is_stmt 0 view .LVU1277
+ 3787 005e 228D     		ldrh	r2, [r4, #40]
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccbUHtu7.s 			page 208
+
+
+ 3788              		.loc 1 1906 8 view .LVU1278
+ 3789 0060 002A     		cmp	r2, #0
+ 3790 0062 4FD0     		beq	.L257
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 3791              		.loc 1 1908 7 is_stmt 1 view .LVU1279
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 3792              		.loc 1 1908 15 is_stmt 0 view .LVU1280
+ 3793 0064 A36B     		ldr	r3, [r4, #56]
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 3794              		.loc 1 1908 10 view .LVU1281
+ 3795 0066 1BB3     		cbz	r3, .L258
+1911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3796              		.loc 1 1911 9 is_stmt 1 view .LVU1282
+1911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3797              		.loc 1 1911 40 is_stmt 0 view .LVU1283
+ 3798 0068 364A     		ldr	r2, .L268+8
+ 3799 006a DA62     		str	r2, [r3, #44]
+1914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3800              		.loc 1 1914 9 is_stmt 1 view .LVU1284
+1914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3801              		.loc 1 1914 13 is_stmt 0 view .LVU1285
+ 3802 006c A36B     		ldr	r3, [r4, #56]
+1914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3803              		.loc 1 1914 41 view .LVU1286
+ 3804 006e 364A     		ldr	r2, .L268+12
+ 3805 0070 5A63     		str	r2, [r3, #52]
+1917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 3806              		.loc 1 1917 9 is_stmt 1 view .LVU1287
+1917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 3807              		.loc 1 1917 13 is_stmt 0 view .LVU1288
+ 3808 0072 A26B     		ldr	r2, [r4, #56]
+1917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 3809              		.loc 1 1917 44 view .LVU1289
+ 3810 0074 0023     		movs	r3, #0
+ 3811 0076 1363     		str	r3, [r2, #48]
+1918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3812              		.loc 1 1918 9 is_stmt 1 view .LVU1290
+1918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3813              		.loc 1 1918 13 is_stmt 0 view .LVU1291
+ 3814 0078 A26B     		ldr	r2, [r4, #56]
+1918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3815              		.loc 1 1918 41 view .LVU1292
+ 3816 007a 9363     		str	r3, [r2, #56]
+1921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 3817              		.loc 1 1921 9 is_stmt 1 view .LVU1293
+1921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 3818              		.loc 1 1921 88 is_stmt 0 view .LVU1294
+ 3819 007c 2268     		ldr	r2, [r4]
+1921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 3820              		.loc 1 1921 25 view .LVU1295
+ 3821 007e 238D     		ldrh	r3, [r4, #40]
+ 3822 0080 2832     		adds	r2, r2, #40
+ 3823 0082 A06B     		ldr	r0, [r4, #56]
+ 3824 0084 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3825              	.LVL241:
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 3826              		.loc 1 1939 7 is_stmt 1 view .LVU1296
+ARM GAS  /tmp/ccbUHtu7.s 			page 209
+
+
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 3827              		.loc 1 1939 10 is_stmt 0 view .LVU1297
+ 3828 0088 00B3     		cbz	r0, .L267
+1963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 3829              		.loc 1 1963 9 is_stmt 1 view .LVU1298
+1963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 3830              		.loc 1 1963 25 is_stmt 0 view .LVU1299
+ 3831 008a 2023     		movs	r3, #32
+ 3832 008c 84F84130 		strb	r3, [r4, #65]
+1964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3833              		.loc 1 1964 9 is_stmt 1 view .LVU1300
+1964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3834              		.loc 1 1964 25 is_stmt 0 view .LVU1301
+ 3835 0090 0022     		movs	r2, #0
+ 3836 0092 84F84220 		strb	r2, [r4, #66]
+1967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3837              		.loc 1 1967 9 is_stmt 1 view .LVU1302
+1967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3838              		.loc 1 1967 13 is_stmt 0 view .LVU1303
+ 3839 0096 636C     		ldr	r3, [r4, #68]
+1967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3840              		.loc 1 1967 25 view .LVU1304
+ 3841 0098 43F01003 		orr	r3, r3, #16
+ 3842 009c 6364     		str	r3, [r4, #68]
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3843              		.loc 1 1970 9 is_stmt 1 view .LVU1305
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3844              		.loc 1 1970 9 view .LVU1306
+ 3845 009e 84F84020 		strb	r2, [r4, #64]
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3846              		.loc 1 1970 9 view .LVU1307
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 3847              		.loc 1 1972 9 view .LVU1308
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 3848              		.loc 1 1972 16 is_stmt 0 view .LVU1309
+ 3849 00a2 0120     		movs	r0, #1
+ 3850              	.LVL242:
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 3851              		.loc 1 1972 16 view .LVU1310
+ 3852 00a4 43E0     		b	.L254
+ 3853              	.LVL243:
+ 3854              	.L255:
+1902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3855              		.loc 1 1902 7 is_stmt 1 view .LVU1311
+1902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3856              		.loc 1 1902 28 is_stmt 0 view .LVU1312
+ 3857 00a6 638D     		ldrh	r3, [r4, #42]
+1902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3858              		.loc 1 1902 22 view .LVU1313
+ 3859 00a8 2385     		strh	r3, [r4, #40]	@ movhi
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3860              		.loc 1 1903 7 is_stmt 1 view .LVU1314
+ 3861              	.LVL244:
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3862              		.loc 1 1903 16 is_stmt 0 view .LVU1315
+ 3863 00aa 4FF00076 		mov	r6, #33554432
+ 3864 00ae D6E7     		b	.L256
+ARM GAS  /tmp/ccbUHtu7.s 			page 210
+
+
+ 3865              	.LVL245:
+ 3866              	.L258:
+1927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 3867              		.loc 1 1927 9 is_stmt 1 view .LVU1316
+1927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 3868              		.loc 1 1927 25 is_stmt 0 view .LVU1317
+ 3869 00b0 2023     		movs	r3, #32
+ 3870 00b2 84F84130 		strb	r3, [r4, #65]
+1928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3871              		.loc 1 1928 9 is_stmt 1 view .LVU1318
+1928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3872              		.loc 1 1928 25 is_stmt 0 view .LVU1319
+ 3873 00b6 0022     		movs	r2, #0
+ 3874 00b8 84F84220 		strb	r2, [r4, #66]
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3875              		.loc 1 1931 9 is_stmt 1 view .LVU1320
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3876              		.loc 1 1931 13 is_stmt 0 view .LVU1321
+ 3877 00bc 636C     		ldr	r3, [r4, #68]
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3878              		.loc 1 1931 25 view .LVU1322
+ 3879 00be 43F08003 		orr	r3, r3, #128
+ 3880 00c2 6364     		str	r3, [r4, #68]
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3881              		.loc 1 1934 9 is_stmt 1 view .LVU1323
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3882              		.loc 1 1934 9 view .LVU1324
+ 3883 00c4 84F84020 		strb	r2, [r4, #64]
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3884              		.loc 1 1934 9 view .LVU1325
+1936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 3885              		.loc 1 1936 9 view .LVU1326
+1936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 3886              		.loc 1 1936 16 is_stmt 0 view .LVU1327
+ 3887 00c8 0120     		movs	r0, #1
+ 3888 00ca 30E0     		b	.L254
+ 3889              	.LVL246:
+ 3890              	.L267:
+1943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3891              		.loc 1 1943 9 is_stmt 1 view .LVU1328
+ 3892 00cc 1F4B     		ldr	r3, .L268+16
+ 3893 00ce 0093     		str	r3, [sp]
+ 3894 00d0 3346     		mov	r3, r6
+ 3895 00d2 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 3896 00d6 2946     		mov	r1, r5
+ 3897 00d8 2046     		mov	r0, r4
+ 3898              	.LVL247:
+1943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3899              		.loc 1 1943 9 is_stmt 0 view .LVU1329
+ 3900 00da FFF7FEFF 		bl	I2C_TransferConfig
+ 3901              	.LVL248:
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3902              		.loc 1 1946 9 is_stmt 1 view .LVU1330
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3903              		.loc 1 1946 13 is_stmt 0 view .LVU1331
+ 3904 00de 638D     		ldrh	r3, [r4, #42]
+ 3905 00e0 9BB2     		uxth	r3, r3
+ARM GAS  /tmp/ccbUHtu7.s 			page 211
+
+
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3906              		.loc 1 1946 32 view .LVU1332
+ 3907 00e2 228D     		ldrh	r2, [r4, #40]
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3908              		.loc 1 1946 25 view .LVU1333
+ 3909 00e4 9B1A     		subs	r3, r3, r2
+ 3910 00e6 9BB2     		uxth	r3, r3
+ 3911 00e8 6385     		strh	r3, [r4, #42]	@ movhi
+1949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3912              		.loc 1 1949 9 is_stmt 1 view .LVU1334
+1949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3913              		.loc 1 1949 9 view .LVU1335
+ 3914 00ea 0023     		movs	r3, #0
+ 3915 00ec 84F84030 		strb	r3, [r4, #64]
+1949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3916              		.loc 1 1949 9 view .LVU1336
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3917              		.loc 1 1955 9 view .LVU1337
+ 3918 00f0 1021     		movs	r1, #16
+ 3919 00f2 2046     		mov	r0, r4
+ 3920 00f4 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 3921              	.LVL249:
+1958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 3922              		.loc 1 1958 9 view .LVU1338
+1958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 3923              		.loc 1 1958 13 is_stmt 0 view .LVU1339
+ 3924 00f8 2268     		ldr	r2, [r4]
+1958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 3925              		.loc 1 1958 23 view .LVU1340
+ 3926 00fa 1368     		ldr	r3, [r2]
+1958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 3927              		.loc 1 1958 29 view .LVU1341
+ 3928 00fc 43F48043 		orr	r3, r3, #16384
+ 3929 0100 1360     		str	r3, [r2]
+ 3930 0102 11E0     		b	.L261
+ 3931              	.LVL250:
+ 3932              	.L257:
+1978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3933              		.loc 1 1978 7 is_stmt 1 view .LVU1342
+1978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3934              		.loc 1 1978 21 is_stmt 0 view .LVU1343
+ 3935 0104 124B     		ldr	r3, .L268+20
+ 3936 0106 6363     		str	r3, [r4, #52]
+1982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 3937              		.loc 1 1982 7 is_stmt 1 view .LVU1344
+ 3938 0108 104B     		ldr	r3, .L268+16
+ 3939 010a 0093     		str	r3, [sp]
+ 3940 010c 4FF00073 		mov	r3, #33554432
+ 3941 0110 D2B2     		uxtb	r2, r2
+ 3942 0112 2946     		mov	r1, r5
+ 3943              	.LVL251:
+1982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 3944              		.loc 1 1982 7 is_stmt 0 view .LVU1345
+ 3945 0114 2046     		mov	r0, r4
+ 3946 0116 FFF7FEFF 		bl	I2C_TransferConfig
+ 3947              	.LVL252:
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 212
+
+
+ 3948              		.loc 1 1986 7 is_stmt 1 view .LVU1346
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3949              		.loc 1 1986 7 view .LVU1347
+ 3950 011a 0023     		movs	r3, #0
+ 3951 011c 84F84030 		strb	r3, [r4, #64]
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3952              		.loc 1 1986 7 view .LVU1348
+1995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3953              		.loc 1 1995 7 view .LVU1349
+ 3954 0120 0121     		movs	r1, #1
+ 3955 0122 2046     		mov	r0, r4
+ 3956 0124 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 3957              	.LVL253:
+ 3958              	.L261:
+1998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3959              		.loc 1 1998 5 view .LVU1350
+1998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3960              		.loc 1 1998 12 is_stmt 0 view .LVU1351
+ 3961 0128 0020     		movs	r0, #0
+ 3962 012a 00E0     		b	.L254
+ 3963              	.LVL254:
+ 3964              	.L262:
+2002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 3965              		.loc 1 2002 12 view .LVU1352
+ 3966 012c 0220     		movs	r0, #2
+ 3967              	.LVL255:
+ 3968              	.L254:
+2004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3969              		.loc 1 2004 1 view .LVU1353
+ 3970 012e 02B0     		add	sp, sp, #8
+ 3971              	.LCFI47:
+ 3972              		.cfi_remember_state
+ 3973              		.cfi_def_cfa_offset 16
+ 3974              		@ sp needed
+ 3975 0130 70BD     		pop	{r4, r5, r6, pc}
+ 3976              	.LVL256:
+ 3977              	.L263:
+ 3978              	.LCFI48:
+ 3979              		.cfi_restore_state
+1879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 3980              		.loc 1 1879 14 view .LVU1354
+ 3981 0132 0220     		movs	r0, #2
+ 3982 0134 FBE7     		b	.L254
+ 3983              	.L264:
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 3984              		.loc 1 1883 5 view .LVU1355
+ 3985 0136 0220     		movs	r0, #2
+ 3986 0138 F9E7     		b	.L254
+ 3987              	.L269:
+ 3988 013a 00BF     		.align	2
+ 3989              	.L268:
+ 3990 013c 0000FFFF 		.word	-65536
+ 3991 0140 00000000 		.word	I2C_Master_ISR_DMA
+ 3992 0144 00000000 		.word	I2C_DMAMasterTransmitCplt
+ 3993 0148 00000000 		.word	I2C_DMAError
+ 3994 014c 00200080 		.word	-2147475456
+ 3995 0150 00000000 		.word	I2C_Master_ISR_IT
+ARM GAS  /tmp/ccbUHtu7.s 			page 213
+
+
+ 3996              		.cfi_endproc
+ 3997              	.LFE341:
+ 3999              		.section	.text.HAL_I2C_Master_Receive_DMA,"ax",%progbits
+ 4000              		.align	1
+ 4001              		.global	HAL_I2C_Master_Receive_DMA
+ 4002              		.syntax unified
+ 4003              		.thumb
+ 4004              		.thumb_func
+ 4006              	HAL_I2C_Master_Receive_DMA:
+ 4007              	.LVL257:
+ 4008              	.LFB342:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 4009              		.loc 1 2018 1 is_stmt 1 view -0
+ 4010              		.cfi_startproc
+ 4011              		@ args = 0, pretend = 0, frame = 0
+ 4012              		@ frame_needed = 0, uses_anonymous_args = 0
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 4013              		.loc 1 2018 1 is_stmt 0 view .LVU1357
+ 4014 0000 70B5     		push	{r4, r5, r6, lr}
+ 4015              	.LCFI49:
+ 4016              		.cfi_def_cfa_offset 16
+ 4017              		.cfi_offset 4, -16
+ 4018              		.cfi_offset 5, -12
+ 4019              		.cfi_offset 6, -8
+ 4020              		.cfi_offset 14, -4
+ 4021 0002 82B0     		sub	sp, sp, #8
+ 4022              	.LCFI50:
+ 4023              		.cfi_def_cfa_offset 24
+ 4024 0004 0446     		mov	r4, r0
+2019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 4025              		.loc 1 2019 3 is_stmt 1 view .LVU1358
+2020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4026              		.loc 1 2020 3 view .LVU1359
+2022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4027              		.loc 1 2022 3 view .LVU1360
+2022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4028              		.loc 1 2022 11 is_stmt 0 view .LVU1361
+ 4029 0006 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 4030              	.LVL258:
+2022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4031              		.loc 1 2022 11 view .LVU1362
+ 4032 000a C0B2     		uxtb	r0, r0
+2022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4033              		.loc 1 2022 6 view .LVU1363
+ 4034 000c 2028     		cmp	r0, #32
+ 4035 000e 40F08C80 		bne	.L279
+ 4036 0012 0D46     		mov	r5, r1
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4037              		.loc 1 2024 5 is_stmt 1 view .LVU1364
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4038              		.loc 1 2024 9 is_stmt 0 view .LVU1365
+ 4039 0014 2168     		ldr	r1, [r4]
+ 4040              	.LVL259:
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4041              		.loc 1 2024 9 view .LVU1366
+ 4042 0016 8969     		ldr	r1, [r1, #24]
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccbUHtu7.s 			page 214
+
+
+ 4043              		.loc 1 2024 8 view .LVU1367
+ 4044 0018 11F4004F 		tst	r1, #32768
+ 4045 001c 40F08880 		bne	.L280
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4046              		.loc 1 2030 5 is_stmt 1 view .LVU1368
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4047              		.loc 1 2030 5 view .LVU1369
+ 4048 0020 94F84010 		ldrb	r1, [r4, #64]	@ zero_extendqisi2
+ 4049 0024 0129     		cmp	r1, #1
+ 4050 0026 00F08580 		beq	.L281
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4051              		.loc 1 2030 5 discriminator 2 view .LVU1370
+ 4052 002a 0121     		movs	r1, #1
+ 4053 002c 84F84010 		strb	r1, [r4, #64]
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4054              		.loc 1 2030 5 discriminator 2 view .LVU1371
+2032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 4055              		.loc 1 2032 5 discriminator 2 view .LVU1372
+2032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 4056              		.loc 1 2032 23 is_stmt 0 discriminator 2 view .LVU1373
+ 4057 0030 2221     		movs	r1, #34
+ 4058 0032 84F84110 		strb	r1, [r4, #65]
+2033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 4059              		.loc 1 2033 5 is_stmt 1 discriminator 2 view .LVU1374
+2033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 4060              		.loc 1 2033 23 is_stmt 0 discriminator 2 view .LVU1375
+ 4061 0036 1021     		movs	r1, #16
+ 4062 0038 84F84210 		strb	r1, [r4, #66]
+2034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4063              		.loc 1 2034 5 is_stmt 1 discriminator 2 view .LVU1376
+2034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4064              		.loc 1 2034 23 is_stmt 0 discriminator 2 view .LVU1377
+ 4065 003c 0021     		movs	r1, #0
+ 4066 003e 6164     		str	r1, [r4, #68]
+2037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 4067              		.loc 1 2037 5 is_stmt 1 discriminator 2 view .LVU1378
+2037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 4068              		.loc 1 2037 23 is_stmt 0 discriminator 2 view .LVU1379
+ 4069 0040 6262     		str	r2, [r4, #36]
+2038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4070              		.loc 1 2038 5 is_stmt 1 discriminator 2 view .LVU1380
+2038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4071              		.loc 1 2038 23 is_stmt 0 discriminator 2 view .LVU1381
+ 4072 0042 6385     		strh	r3, [r4, #42]	@ movhi
+2039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 4073              		.loc 1 2039 5 is_stmt 1 discriminator 2 view .LVU1382
+2039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 4074              		.loc 1 2039 23 is_stmt 0 discriminator 2 view .LVU1383
+ 4075 0044 3C4B     		ldr	r3, .L285
+ 4076              	.LVL260:
+2039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 4077              		.loc 1 2039 23 discriminator 2 view .LVU1384
+ 4078 0046 E362     		str	r3, [r4, #44]
+ 4079              	.LVL261:
+2040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4080              		.loc 1 2040 5 is_stmt 1 discriminator 2 view .LVU1385
+2040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 215
+
+
+ 4081              		.loc 1 2040 23 is_stmt 0 discriminator 2 view .LVU1386
+ 4082 0048 3C4B     		ldr	r3, .L285+4
+ 4083 004a 6363     		str	r3, [r4, #52]
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4084              		.loc 1 2042 5 is_stmt 1 discriminator 2 view .LVU1387
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4085              		.loc 1 2042 13 is_stmt 0 discriminator 2 view .LVU1388
+ 4086 004c 638D     		ldrh	r3, [r4, #42]
+ 4087 004e 9BB2     		uxth	r3, r3
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4088              		.loc 1 2042 8 discriminator 2 view .LVU1389
+ 4089 0050 FF2B     		cmp	r3, #255
+ 4090 0052 27D9     		bls	.L272
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 4091              		.loc 1 2044 7 is_stmt 1 view .LVU1390
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 4092              		.loc 1 2044 22 is_stmt 0 view .LVU1391
+ 4093 0054 FF23     		movs	r3, #255
+ 4094 0056 2385     		strh	r3, [r4, #40]	@ movhi
+2045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4095              		.loc 1 2045 7 is_stmt 1 view .LVU1392
+ 4096              	.LVL262:
+2045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4097              		.loc 1 2045 16 is_stmt 0 view .LVU1393
+ 4098 0058 4FF08076 		mov	r6, #16777216
+ 4099              	.LVL263:
+ 4100              	.L273:
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4101              		.loc 1 2053 5 is_stmt 1 view .LVU1394
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4102              		.loc 1 2053 13 is_stmt 0 view .LVU1395
+ 4103 005c 218D     		ldrh	r1, [r4, #40]
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4104              		.loc 1 2053 8 view .LVU1396
+ 4105 005e 0029     		cmp	r1, #0
+ 4106 0060 4FD0     		beq	.L274
+2055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 4107              		.loc 1 2055 7 is_stmt 1 view .LVU1397
+2055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 4108              		.loc 1 2055 15 is_stmt 0 view .LVU1398
+ 4109 0062 E36B     		ldr	r3, [r4, #60]
+2055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 4110              		.loc 1 2055 10 view .LVU1399
+ 4111 0064 1BB3     		cbz	r3, .L275
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4112              		.loc 1 2058 9 is_stmt 1 view .LVU1400
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4113              		.loc 1 2058 40 is_stmt 0 view .LVU1401
+ 4114 0066 3649     		ldr	r1, .L285+8
+ 4115 0068 D962     		str	r1, [r3, #44]
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4116              		.loc 1 2061 9 is_stmt 1 view .LVU1402
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4117              		.loc 1 2061 13 is_stmt 0 view .LVU1403
+ 4118 006a E36B     		ldr	r3, [r4, #60]
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4119              		.loc 1 2061 41 view .LVU1404
+ARM GAS  /tmp/ccbUHtu7.s 			page 216
+
+
+ 4120 006c 3549     		ldr	r1, .L285+12
+ 4121 006e 5963     		str	r1, [r3, #52]
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+ 4122              		.loc 1 2064 9 is_stmt 1 view .LVU1405
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+ 4123              		.loc 1 2064 13 is_stmt 0 view .LVU1406
+ 4124 0070 E16B     		ldr	r1, [r4, #60]
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+ 4125              		.loc 1 2064 44 view .LVU1407
+ 4126 0072 0023     		movs	r3, #0
+ 4127 0074 0B63     		str	r3, [r1, #48]
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4128              		.loc 1 2065 9 is_stmt 1 view .LVU1408
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4129              		.loc 1 2065 13 is_stmt 0 view .LVU1409
+ 4130 0076 E16B     		ldr	r1, [r4, #60]
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4131              		.loc 1 2065 41 view .LVU1410
+ 4132 0078 8B63     		str	r3, [r1, #56]
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 4133              		.loc 1 2068 9 is_stmt 1 view .LVU1411
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 4134              		.loc 1 2068 71 is_stmt 0 view .LVU1412
+ 4135 007a 2168     		ldr	r1, [r4]
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 4136              		.loc 1 2068 25 view .LVU1413
+ 4137 007c 238D     		ldrh	r3, [r4, #40]
+ 4138 007e 2431     		adds	r1, r1, #36
+ 4139 0080 E06B     		ldr	r0, [r4, #60]
+ 4140 0082 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 4141              	.LVL264:
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 4142              		.loc 1 2086 7 is_stmt 1 view .LVU1414
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 4143              		.loc 1 2086 10 is_stmt 0 view .LVU1415
+ 4144 0086 00B3     		cbz	r0, .L284
+2110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4145              		.loc 1 2110 9 is_stmt 1 view .LVU1416
+2110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4146              		.loc 1 2110 25 is_stmt 0 view .LVU1417
+ 4147 0088 2023     		movs	r3, #32
+ 4148 008a 84F84130 		strb	r3, [r4, #65]
+2111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4149              		.loc 1 2111 9 is_stmt 1 view .LVU1418
+2111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4150              		.loc 1 2111 25 is_stmt 0 view .LVU1419
+ 4151 008e 0022     		movs	r2, #0
+ 4152 0090 84F84220 		strb	r2, [r4, #66]
+2114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4153              		.loc 1 2114 9 is_stmt 1 view .LVU1420
+2114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4154              		.loc 1 2114 13 is_stmt 0 view .LVU1421
+ 4155 0094 636C     		ldr	r3, [r4, #68]
+2114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4156              		.loc 1 2114 25 view .LVU1422
+ 4157 0096 43F01003 		orr	r3, r3, #16
+ 4158 009a 6364     		str	r3, [r4, #68]
+ARM GAS  /tmp/ccbUHtu7.s 			page 217
+
+
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4159              		.loc 1 2117 9 is_stmt 1 view .LVU1423
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4160              		.loc 1 2117 9 view .LVU1424
+ 4161 009c 84F84020 		strb	r2, [r4, #64]
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4162              		.loc 1 2117 9 view .LVU1425
+2119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 4163              		.loc 1 2119 9 view .LVU1426
+2119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 4164              		.loc 1 2119 16 is_stmt 0 view .LVU1427
+ 4165 00a0 0120     		movs	r0, #1
+ 4166              	.LVL265:
+2119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 4167              		.loc 1 2119 16 view .LVU1428
+ 4168 00a2 43E0     		b	.L271
+ 4169              	.LVL266:
+ 4170              	.L272:
+2049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 4171              		.loc 1 2049 7 is_stmt 1 view .LVU1429
+2049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 4172              		.loc 1 2049 28 is_stmt 0 view .LVU1430
+ 4173 00a4 638D     		ldrh	r3, [r4, #42]
+2049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 4174              		.loc 1 2049 22 view .LVU1431
+ 4175 00a6 2385     		strh	r3, [r4, #40]	@ movhi
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4176              		.loc 1 2050 7 is_stmt 1 view .LVU1432
+ 4177              	.LVL267:
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4178              		.loc 1 2050 16 is_stmt 0 view .LVU1433
+ 4179 00a8 4FF00076 		mov	r6, #33554432
+ 4180 00ac D6E7     		b	.L273
+ 4181              	.LVL268:
+ 4182              	.L275:
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4183              		.loc 1 2074 9 is_stmt 1 view .LVU1434
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4184              		.loc 1 2074 25 is_stmt 0 view .LVU1435
+ 4185 00ae 2023     		movs	r3, #32
+ 4186 00b0 84F84130 		strb	r3, [r4, #65]
+2075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4187              		.loc 1 2075 9 is_stmt 1 view .LVU1436
+2075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4188              		.loc 1 2075 25 is_stmt 0 view .LVU1437
+ 4189 00b4 0022     		movs	r2, #0
+ 4190              	.LVL269:
+2075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4191              		.loc 1 2075 25 view .LVU1438
+ 4192 00b6 84F84220 		strb	r2, [r4, #66]
+2078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4193              		.loc 1 2078 9 is_stmt 1 view .LVU1439
+2078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4194              		.loc 1 2078 13 is_stmt 0 view .LVU1440
+ 4195 00ba 636C     		ldr	r3, [r4, #68]
+2078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4196              		.loc 1 2078 25 view .LVU1441
+ARM GAS  /tmp/ccbUHtu7.s 			page 218
+
+
+ 4197 00bc 43F08003 		orr	r3, r3, #128
+ 4198 00c0 6364     		str	r3, [r4, #68]
+2081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4199              		.loc 1 2081 9 is_stmt 1 view .LVU1442
+2081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4200              		.loc 1 2081 9 view .LVU1443
+ 4201 00c2 84F84020 		strb	r2, [r4, #64]
+2081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4202              		.loc 1 2081 9 view .LVU1444
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 4203              		.loc 1 2083 9 view .LVU1445
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 4204              		.loc 1 2083 16 is_stmt 0 view .LVU1446
+ 4205 00c6 0120     		movs	r0, #1
+ 4206 00c8 30E0     		b	.L271
+ 4207              	.LVL270:
+ 4208              	.L284:
+2090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4209              		.loc 1 2090 9 is_stmt 1 view .LVU1447
+ 4210 00ca 1F4B     		ldr	r3, .L285+16
+ 4211 00cc 0093     		str	r3, [sp]
+ 4212 00ce 3346     		mov	r3, r6
+ 4213 00d0 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 4214 00d4 2946     		mov	r1, r5
+ 4215 00d6 2046     		mov	r0, r4
+ 4216              	.LVL271:
+2090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4217              		.loc 1 2090 9 is_stmt 0 view .LVU1448
+ 4218 00d8 FFF7FEFF 		bl	I2C_TransferConfig
+ 4219              	.LVL272:
+2093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4220              		.loc 1 2093 9 is_stmt 1 view .LVU1449
+2093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4221              		.loc 1 2093 13 is_stmt 0 view .LVU1450
+ 4222 00dc 638D     		ldrh	r3, [r4, #42]
+ 4223 00de 9BB2     		uxth	r3, r3
+2093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4224              		.loc 1 2093 32 view .LVU1451
+ 4225 00e0 228D     		ldrh	r2, [r4, #40]
+2093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4226              		.loc 1 2093 25 view .LVU1452
+ 4227 00e2 9B1A     		subs	r3, r3, r2
+ 4228 00e4 9BB2     		uxth	r3, r3
+ 4229 00e6 6385     		strh	r3, [r4, #42]	@ movhi
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4230              		.loc 1 2096 9 is_stmt 1 view .LVU1453
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4231              		.loc 1 2096 9 view .LVU1454
+ 4232 00e8 0023     		movs	r3, #0
+ 4233 00ea 84F84030 		strb	r3, [r4, #64]
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4234              		.loc 1 2096 9 view .LVU1455
+2102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4235              		.loc 1 2102 9 view .LVU1456
+ 4236 00ee 1021     		movs	r1, #16
+ 4237 00f0 2046     		mov	r0, r4
+ 4238 00f2 FFF7FEFF 		bl	I2C_Enable_IRQ
+ARM GAS  /tmp/ccbUHtu7.s 			page 219
+
+
+ 4239              	.LVL273:
+2105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 4240              		.loc 1 2105 9 view .LVU1457
+2105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 4241              		.loc 1 2105 13 is_stmt 0 view .LVU1458
+ 4242 00f6 2268     		ldr	r2, [r4]
+2105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 4243              		.loc 1 2105 23 view .LVU1459
+ 4244 00f8 1368     		ldr	r3, [r2]
+2105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 4245              		.loc 1 2105 29 view .LVU1460
+ 4246 00fa 43F40043 		orr	r3, r3, #32768
+ 4247 00fe 1360     		str	r3, [r2]
+ 4248 0100 11E0     		b	.L278
+ 4249              	.LVL274:
+ 4250              	.L274:
+2125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4251              		.loc 1 2125 7 is_stmt 1 view .LVU1461
+2125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4252              		.loc 1 2125 21 is_stmt 0 view .LVU1462
+ 4253 0102 124B     		ldr	r3, .L285+20
+ 4254 0104 6363     		str	r3, [r4, #52]
+2129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 4255              		.loc 1 2129 7 is_stmt 1 view .LVU1463
+ 4256 0106 104B     		ldr	r3, .L285+16
+ 4257 0108 0093     		str	r3, [sp]
+ 4258 010a 4FF00073 		mov	r3, #33554432
+ 4259 010e CAB2     		uxtb	r2, r1
+ 4260              	.LVL275:
+2129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 4261              		.loc 1 2129 7 is_stmt 0 view .LVU1464
+ 4262 0110 2946     		mov	r1, r5
+ 4263 0112 2046     		mov	r0, r4
+ 4264 0114 FFF7FEFF 		bl	I2C_TransferConfig
+ 4265              	.LVL276:
+2133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4266              		.loc 1 2133 7 is_stmt 1 view .LVU1465
+2133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4267              		.loc 1 2133 7 view .LVU1466
+ 4268 0118 0023     		movs	r3, #0
+ 4269 011a 84F84030 		strb	r3, [r4, #64]
+2133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4270              		.loc 1 2133 7 view .LVU1467
+2142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4271              		.loc 1 2142 7 view .LVU1468
+ 4272 011e 0121     		movs	r1, #1
+ 4273 0120 2046     		mov	r0, r4
+ 4274 0122 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 4275              	.LVL277:
+ 4276              	.L278:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 4277              		.loc 1 2145 5 view .LVU1469
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 4278              		.loc 1 2145 12 is_stmt 0 view .LVU1470
+ 4279 0126 0020     		movs	r0, #0
+ 4280 0128 00E0     		b	.L271
+ 4281              	.LVL278:
+ARM GAS  /tmp/ccbUHtu7.s 			page 220
+
+
+ 4282              	.L279:
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 4283              		.loc 1 2149 12 view .LVU1471
+ 4284 012a 0220     		movs	r0, #2
+ 4285              	.LVL279:
+ 4286              	.L271:
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4287              		.loc 1 2151 1 view .LVU1472
+ 4288 012c 02B0     		add	sp, sp, #8
+ 4289              	.LCFI51:
+ 4290              		.cfi_remember_state
+ 4291              		.cfi_def_cfa_offset 16
+ 4292              		@ sp needed
+ 4293 012e 70BD     		pop	{r4, r5, r6, pc}
+ 4294              	.LVL280:
+ 4295              	.L280:
+ 4296              	.LCFI52:
+ 4297              		.cfi_restore_state
+2026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4298              		.loc 1 2026 14 view .LVU1473
+ 4299 0130 0220     		movs	r0, #2
+ 4300 0132 FBE7     		b	.L271
+ 4301              	.L281:
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4302              		.loc 1 2030 5 view .LVU1474
+ 4303 0134 0220     		movs	r0, #2
+ 4304 0136 F9E7     		b	.L271
+ 4305              	.L286:
+ 4306              		.align	2
+ 4307              	.L285:
+ 4308 0138 0000FFFF 		.word	-65536
+ 4309 013c 00000000 		.word	I2C_Master_ISR_DMA
+ 4310 0140 00000000 		.word	I2C_DMAMasterReceiveCplt
+ 4311 0144 00000000 		.word	I2C_DMAError
+ 4312 0148 00240080 		.word	-2147474432
+ 4313 014c 00000000 		.word	I2C_Master_ISR_IT
+ 4314              		.cfi_endproc
+ 4315              	.LFE342:
+ 4317              		.section	.text.HAL_I2C_Slave_Transmit_DMA,"ax",%progbits
+ 4318              		.align	1
+ 4319              		.global	HAL_I2C_Slave_Transmit_DMA
+ 4320              		.syntax unified
+ 4321              		.thumb
+ 4322              		.thumb_func
+ 4324              	HAL_I2C_Slave_Transmit_DMA:
+ 4325              	.LVL281:
+ 4326              	.LFB343:
+2162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 4327              		.loc 1 2162 1 is_stmt 1 view -0
+ 4328              		.cfi_startproc
+ 4329              		@ args = 0, pretend = 0, frame = 0
+ 4330              		@ frame_needed = 0, uses_anonymous_args = 0
+2162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 4331              		.loc 1 2162 1 is_stmt 0 view .LVU1476
+ 4332 0000 38B5     		push	{r3, r4, r5, lr}
+ 4333              	.LCFI53:
+ 4334              		.cfi_def_cfa_offset 16
+ARM GAS  /tmp/ccbUHtu7.s 			page 221
+
+
+ 4335              		.cfi_offset 3, -16
+ 4336              		.cfi_offset 4, -12
+ 4337              		.cfi_offset 5, -8
+ 4338              		.cfi_offset 14, -4
+2163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4339              		.loc 1 2163 3 is_stmt 1 view .LVU1477
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4340              		.loc 1 2165 3 view .LVU1478
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4341              		.loc 1 2165 11 is_stmt 0 view .LVU1479
+ 4342 0002 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 4343 0006 DBB2     		uxtb	r3, r3
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4344              		.loc 1 2165 6 view .LVU1480
+ 4345 0008 202B     		cmp	r3, #32
+ 4346 000a 63D1     		bne	.L294
+ 4347 000c 0446     		mov	r4, r0
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4348              		.loc 1 2167 5 is_stmt 1 view .LVU1481
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4349              		.loc 1 2167 8 is_stmt 0 view .LVU1482
+ 4350 000e 0029     		cmp	r1, #0
+ 4351 0010 3AD0     		beq	.L289
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4352              		.loc 1 2167 25 discriminator 1 view .LVU1483
+ 4353 0012 002A     		cmp	r2, #0
+ 4354 0014 38D0     		beq	.L289
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4355              		.loc 1 2173 5 is_stmt 1 view .LVU1484
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4356              		.loc 1 2173 5 view .LVU1485
+ 4357 0016 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 4358 001a 012B     		cmp	r3, #1
+ 4359 001c 5DD0     		beq	.L295
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4360              		.loc 1 2173 5 discriminator 2 view .LVU1486
+ 4361 001e 0123     		movs	r3, #1
+ 4362 0020 80F84030 		strb	r3, [r0, #64]
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4363              		.loc 1 2173 5 discriminator 2 view .LVU1487
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 4364              		.loc 1 2175 5 discriminator 2 view .LVU1488
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 4365              		.loc 1 2175 23 is_stmt 0 discriminator 2 view .LVU1489
+ 4366 0024 2123     		movs	r3, #33
+ 4367 0026 80F84130 		strb	r3, [r0, #65]
+2176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 4368              		.loc 1 2176 5 is_stmt 1 discriminator 2 view .LVU1490
+2176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 4369              		.loc 1 2176 23 is_stmt 0 discriminator 2 view .LVU1491
+ 4370 002a 2023     		movs	r3, #32
+ 4371 002c 80F84230 		strb	r3, [r0, #66]
+2177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4372              		.loc 1 2177 5 is_stmt 1 discriminator 2 view .LVU1492
+2177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4373              		.loc 1 2177 23 is_stmt 0 discriminator 2 view .LVU1493
+ 4374 0030 0023     		movs	r3, #0
+ARM GAS  /tmp/ccbUHtu7.s 			page 222
+
+
+ 4375 0032 4364     		str	r3, [r0, #68]
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 4376              		.loc 1 2180 5 is_stmt 1 discriminator 2 view .LVU1494
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 4377              		.loc 1 2180 23 is_stmt 0 discriminator 2 view .LVU1495
+ 4378 0034 4162     		str	r1, [r0, #36]
+2181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 4379              		.loc 1 2181 5 is_stmt 1 discriminator 2 view .LVU1496
+2181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 4380              		.loc 1 2181 23 is_stmt 0 discriminator 2 view .LVU1497
+ 4381 0036 4285     		strh	r2, [r0, #42]	@ movhi
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4382              		.loc 1 2182 5 is_stmt 1 discriminator 2 view .LVU1498
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4383              		.loc 1 2182 29 is_stmt 0 discriminator 2 view .LVU1499
+ 4384 0038 438D     		ldrh	r3, [r0, #42]
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4385              		.loc 1 2182 23 discriminator 2 view .LVU1500
+ 4386 003a 0385     		strh	r3, [r0, #40]	@ movhi
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 4387              		.loc 1 2183 5 is_stmt 1 discriminator 2 view .LVU1501
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 4388              		.loc 1 2183 23 is_stmt 0 discriminator 2 view .LVU1502
+ 4389 003c 284B     		ldr	r3, .L299
+ 4390 003e C362     		str	r3, [r0, #44]
+2184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4391              		.loc 1 2184 5 is_stmt 1 discriminator 2 view .LVU1503
+2184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4392              		.loc 1 2184 23 is_stmt 0 discriminator 2 view .LVU1504
+ 4393 0040 284B     		ldr	r3, .L299+4
+ 4394 0042 4363     		str	r3, [r0, #52]
+2186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4395              		.loc 1 2186 5 is_stmt 1 discriminator 2 view .LVU1505
+2186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4396              		.loc 1 2186 13 is_stmt 0 discriminator 2 view .LVU1506
+ 4397 0044 836B     		ldr	r3, [r0, #56]
+2186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4398              		.loc 1 2186 8 discriminator 2 view .LVU1507
+ 4399 0046 23B3     		cbz	r3, .L291
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4400              		.loc 1 2189 7 is_stmt 1 view .LVU1508
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4401              		.loc 1 2189 38 is_stmt 0 view .LVU1509
+ 4402 0048 274A     		ldr	r2, .L299+8
+ 4403              	.LVL282:
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4404              		.loc 1 2189 38 view .LVU1510
+ 4405 004a DA62     		str	r2, [r3, #44]
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4406              		.loc 1 2192 7 is_stmt 1 view .LVU1511
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4407              		.loc 1 2192 11 is_stmt 0 view .LVU1512
+ 4408 004c 836B     		ldr	r3, [r0, #56]
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4409              		.loc 1 2192 39 view .LVU1513
+ 4410 004e 274A     		ldr	r2, .L299+12
+ 4411 0050 5A63     		str	r2, [r3, #52]
+ARM GAS  /tmp/ccbUHtu7.s 			page 223
+
+
+2195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 4412              		.loc 1 2195 7 is_stmt 1 view .LVU1514
+2195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 4413              		.loc 1 2195 11 is_stmt 0 view .LVU1515
+ 4414 0052 826B     		ldr	r2, [r0, #56]
+2195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 4415              		.loc 1 2195 42 view .LVU1516
+ 4416 0054 0023     		movs	r3, #0
+ 4417 0056 1363     		str	r3, [r2, #48]
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4418              		.loc 1 2196 7 is_stmt 1 view .LVU1517
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4419              		.loc 1 2196 11 is_stmt 0 view .LVU1518
+ 4420 0058 826B     		ldr	r2, [r0, #56]
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4421              		.loc 1 2196 39 view .LVU1519
+ 4422 005a 9363     		str	r3, [r2, #56]
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 4423              		.loc 1 2199 7 is_stmt 1 view .LVU1520
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 4424              		.loc 1 2199 86 is_stmt 0 view .LVU1521
+ 4425 005c 0268     		ldr	r2, [r0]
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 4426              		.loc 1 2199 23 view .LVU1522
+ 4427 005e 038D     		ldrh	r3, [r0, #40]
+ 4428 0060 2832     		adds	r2, r2, #40
+ 4429 0062 806B     		ldr	r0, [r0, #56]
+ 4430              	.LVL283:
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 4431              		.loc 1 2199 23 view .LVU1523
+ 4432 0064 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 4433              	.LVL284:
+2217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4434              		.loc 1 2217 5 is_stmt 1 view .LVU1524
+2217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4435              		.loc 1 2217 8 is_stmt 0 view .LVU1525
+ 4436 0068 0546     		mov	r5, r0
+ 4437 006a 00B3     		cbz	r0, .L298
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4438              		.loc 1 2237 7 is_stmt 1 view .LVU1526
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4439              		.loc 1 2237 23 is_stmt 0 view .LVU1527
+ 4440 006c 2823     		movs	r3, #40
+ 4441 006e 84F84130 		strb	r3, [r4, #65]
+2238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4442              		.loc 1 2238 7 is_stmt 1 view .LVU1528
+2238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4443              		.loc 1 2238 23 is_stmt 0 view .LVU1529
+ 4444 0072 0022     		movs	r2, #0
+ 4445 0074 84F84220 		strb	r2, [r4, #66]
+2241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4446              		.loc 1 2241 7 is_stmt 1 view .LVU1530
+2241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4447              		.loc 1 2241 11 is_stmt 0 view .LVU1531
+ 4448 0078 636C     		ldr	r3, [r4, #68]
+2241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4449              		.loc 1 2241 23 view .LVU1532
+ARM GAS  /tmp/ccbUHtu7.s 			page 224
+
+
+ 4450 007a 43F01003 		orr	r3, r3, #16
+ 4451 007e 6364     		str	r3, [r4, #68]
+2244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4452              		.loc 1 2244 7 is_stmt 1 view .LVU1533
+2244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4453              		.loc 1 2244 7 view .LVU1534
+ 4454 0080 84F84020 		strb	r2, [r4, #64]
+2244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4455              		.loc 1 2244 7 view .LVU1535
+2246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4456              		.loc 1 2246 7 view .LVU1536
+2246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4457              		.loc 1 2246 14 is_stmt 0 view .LVU1537
+ 4458 0084 0125     		movs	r5, #1
+ 4459 0086 26E0     		b	.L288
+ 4460              	.LVL285:
+ 4461              	.L289:
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 4462              		.loc 1 2169 7 is_stmt 1 view .LVU1538
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 4463              		.loc 1 2169 23 is_stmt 0 view .LVU1539
+ 4464 0088 4FF40073 		mov	r3, #512
+ 4465 008c 6364     		str	r3, [r4, #68]
+2170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4466              		.loc 1 2170 7 is_stmt 1 view .LVU1540
+2170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4467              		.loc 1 2170 15 is_stmt 0 view .LVU1541
+ 4468 008e 0125     		movs	r5, #1
+ 4469 0090 21E0     		b	.L288
+ 4470              	.L291:
+2205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4471              		.loc 1 2205 7 is_stmt 1 view .LVU1542
+2205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4472              		.loc 1 2205 23 is_stmt 0 view .LVU1543
+ 4473 0092 2823     		movs	r3, #40
+ 4474 0094 80F84130 		strb	r3, [r0, #65]
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4475              		.loc 1 2206 7 is_stmt 1 view .LVU1544
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4476              		.loc 1 2206 23 is_stmt 0 view .LVU1545
+ 4477 0098 0022     		movs	r2, #0
+ 4478              	.LVL286:
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4479              		.loc 1 2206 23 view .LVU1546
+ 4480 009a 80F84220 		strb	r2, [r0, #66]
+2209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4481              		.loc 1 2209 7 is_stmt 1 view .LVU1547
+2209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4482              		.loc 1 2209 11 is_stmt 0 view .LVU1548
+ 4483 009e 436C     		ldr	r3, [r0, #68]
+2209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4484              		.loc 1 2209 23 view .LVU1549
+ 4485 00a0 43F08003 		orr	r3, r3, #128
+ 4486 00a4 4364     		str	r3, [r0, #68]
+2212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4487              		.loc 1 2212 7 is_stmt 1 view .LVU1550
+2212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 225
+
+
+ 4488              		.loc 1 2212 7 view .LVU1551
+ 4489 00a6 80F84020 		strb	r2, [r0, #64]
+2212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4490              		.loc 1 2212 7 view .LVU1552
+2214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4491              		.loc 1 2214 7 view .LVU1553
+2214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4492              		.loc 1 2214 14 is_stmt 0 view .LVU1554
+ 4493 00aa 0125     		movs	r5, #1
+ 4494 00ac 13E0     		b	.L288
+ 4495              	.LVL287:
+ 4496              	.L298:
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4497              		.loc 1 2220 7 is_stmt 1 view .LVU1555
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4498              		.loc 1 2220 11 is_stmt 0 view .LVU1556
+ 4499 00ae 2268     		ldr	r2, [r4]
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4500              		.loc 1 2220 21 view .LVU1557
+ 4501 00b0 5368     		ldr	r3, [r2, #4]
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4502              		.loc 1 2220 27 view .LVU1558
+ 4503 00b2 23F40043 		bic	r3, r3, #32768
+ 4504 00b6 5360     		str	r3, [r2, #4]
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4505              		.loc 1 2223 7 is_stmt 1 view .LVU1559
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4506              		.loc 1 2223 7 view .LVU1560
+ 4507 00b8 0023     		movs	r3, #0
+ 4508 00ba 84F84030 		strb	r3, [r4, #64]
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4509              		.loc 1 2223 7 view .LVU1561
+2229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4510              		.loc 1 2229 7 view .LVU1562
+ 4511 00be 4FF40041 		mov	r1, #32768
+ 4512 00c2 2046     		mov	r0, r4
+ 4513              	.LVL288:
+2229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4514              		.loc 1 2229 7 is_stmt 0 view .LVU1563
+ 4515 00c4 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 4516              	.LVL289:
+2232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4517              		.loc 1 2232 7 is_stmt 1 view .LVU1564
+2232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4518              		.loc 1 2232 11 is_stmt 0 view .LVU1565
+ 4519 00c8 2268     		ldr	r2, [r4]
+2232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4520              		.loc 1 2232 21 view .LVU1566
+ 4521 00ca 1368     		ldr	r3, [r2]
+2232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4522              		.loc 1 2232 27 view .LVU1567
+ 4523 00cc 43F48043 		orr	r3, r3, #16384
+ 4524 00d0 1360     		str	r3, [r2]
+2249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 4525              		.loc 1 2249 5 is_stmt 1 view .LVU1568
+2249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 4526              		.loc 1 2249 12 is_stmt 0 view .LVU1569
+ARM GAS  /tmp/ccbUHtu7.s 			page 226
+
+
+ 4527 00d2 00E0     		b	.L288
+ 4528              	.LVL290:
+ 4529              	.L294:
+2253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 4530              		.loc 1 2253 12 view .LVU1570
+ 4531 00d4 0225     		movs	r5, #2
+ 4532              	.LVL291:
+ 4533              	.L288:
+2255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4534              		.loc 1 2255 1 view .LVU1571
+ 4535 00d6 2846     		mov	r0, r5
+ 4536 00d8 38BD     		pop	{r3, r4, r5, pc}
+ 4537              	.LVL292:
+ 4538              	.L295:
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4539              		.loc 1 2173 5 view .LVU1572
+ 4540 00da 0225     		movs	r5, #2
+ 4541 00dc FBE7     		b	.L288
+ 4542              	.L300:
+ 4543 00de 00BF     		.align	2
+ 4544              	.L299:
+ 4545 00e0 0000FFFF 		.word	-65536
+ 4546 00e4 00000000 		.word	I2C_Slave_ISR_DMA
+ 4547 00e8 00000000 		.word	I2C_DMASlaveTransmitCplt
+ 4548 00ec 00000000 		.word	I2C_DMAError
+ 4549              		.cfi_endproc
+ 4550              	.LFE343:
+ 4552              		.section	.text.HAL_I2C_Slave_Receive_DMA,"ax",%progbits
+ 4553              		.align	1
+ 4554              		.global	HAL_I2C_Slave_Receive_DMA
+ 4555              		.syntax unified
+ 4556              		.thumb
+ 4557              		.thumb_func
+ 4559              	HAL_I2C_Slave_Receive_DMA:
+ 4560              	.LVL293:
+ 4561              	.LFB344:
+2266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 4562              		.loc 1 2266 1 is_stmt 1 view -0
+ 4563              		.cfi_startproc
+ 4564              		@ args = 0, pretend = 0, frame = 0
+ 4565              		@ frame_needed = 0, uses_anonymous_args = 0
+2266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 4566              		.loc 1 2266 1 is_stmt 0 view .LVU1574
+ 4567 0000 38B5     		push	{r3, r4, r5, lr}
+ 4568              	.LCFI54:
+ 4569              		.cfi_def_cfa_offset 16
+ 4570              		.cfi_offset 3, -16
+ 4571              		.cfi_offset 4, -12
+ 4572              		.cfi_offset 5, -8
+ 4573              		.cfi_offset 14, -4
+2267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4574              		.loc 1 2267 3 is_stmt 1 view .LVU1575
+2269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4575              		.loc 1 2269 3 view .LVU1576
+2269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4576              		.loc 1 2269 11 is_stmt 0 view .LVU1577
+ 4577 0002 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ARM GAS  /tmp/ccbUHtu7.s 			page 227
+
+
+ 4578 0006 DBB2     		uxtb	r3, r3
+2269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4579              		.loc 1 2269 6 view .LVU1578
+ 4580 0008 202B     		cmp	r3, #32
+ 4581 000a 65D1     		bne	.L308
+ 4582 000c 0446     		mov	r4, r0
+2271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4583              		.loc 1 2271 5 is_stmt 1 view .LVU1579
+2271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4584              		.loc 1 2271 8 is_stmt 0 view .LVU1580
+ 4585 000e 0029     		cmp	r1, #0
+ 4586 0010 3CD0     		beq	.L303
+2271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4587              		.loc 1 2271 25 discriminator 1 view .LVU1581
+ 4588 0012 002A     		cmp	r2, #0
+ 4589 0014 3AD0     		beq	.L303
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4590              		.loc 1 2277 5 is_stmt 1 view .LVU1582
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4591              		.loc 1 2277 5 view .LVU1583
+ 4592 0016 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 4593 001a 012B     		cmp	r3, #1
+ 4594 001c 5FD0     		beq	.L309
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4595              		.loc 1 2277 5 discriminator 2 view .LVU1584
+ 4596 001e 0123     		movs	r3, #1
+ 4597 0020 80F84030 		strb	r3, [r0, #64]
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4598              		.loc 1 2277 5 discriminator 2 view .LVU1585
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 4599              		.loc 1 2279 5 discriminator 2 view .LVU1586
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 4600              		.loc 1 2279 23 is_stmt 0 discriminator 2 view .LVU1587
+ 4601 0024 2223     		movs	r3, #34
+ 4602 0026 80F84130 		strb	r3, [r0, #65]
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 4603              		.loc 1 2280 5 is_stmt 1 discriminator 2 view .LVU1588
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 4604              		.loc 1 2280 23 is_stmt 0 discriminator 2 view .LVU1589
+ 4605 002a 2023     		movs	r3, #32
+ 4606 002c 80F84230 		strb	r3, [r0, #66]
+2281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4607              		.loc 1 2281 5 is_stmt 1 discriminator 2 view .LVU1590
+2281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4608              		.loc 1 2281 23 is_stmt 0 discriminator 2 view .LVU1591
+ 4609 0030 0023     		movs	r3, #0
+ 4610 0032 4364     		str	r3, [r0, #68]
+2284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 4611              		.loc 1 2284 5 is_stmt 1 discriminator 2 view .LVU1592
+2284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 4612              		.loc 1 2284 23 is_stmt 0 discriminator 2 view .LVU1593
+ 4613 0034 4162     		str	r1, [r0, #36]
+2285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 4614              		.loc 1 2285 5 is_stmt 1 discriminator 2 view .LVU1594
+2285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 4615              		.loc 1 2285 23 is_stmt 0 discriminator 2 view .LVU1595
+ 4616 0036 4285     		strh	r2, [r0, #42]	@ movhi
+ARM GAS  /tmp/ccbUHtu7.s 			page 228
+
+
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4617              		.loc 1 2286 5 is_stmt 1 discriminator 2 view .LVU1596
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4618              		.loc 1 2286 29 is_stmt 0 discriminator 2 view .LVU1597
+ 4619 0038 438D     		ldrh	r3, [r0, #42]
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4620              		.loc 1 2286 23 discriminator 2 view .LVU1598
+ 4621 003a 0385     		strh	r3, [r0, #40]	@ movhi
+2287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 4622              		.loc 1 2287 5 is_stmt 1 discriminator 2 view .LVU1599
+2287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 4623              		.loc 1 2287 23 is_stmt 0 discriminator 2 view .LVU1600
+ 4624 003c 294B     		ldr	r3, .L313
+ 4625 003e C362     		str	r3, [r0, #44]
+2288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4626              		.loc 1 2288 5 is_stmt 1 discriminator 2 view .LVU1601
+2288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4627              		.loc 1 2288 23 is_stmt 0 discriminator 2 view .LVU1602
+ 4628 0040 294B     		ldr	r3, .L313+4
+ 4629 0042 4363     		str	r3, [r0, #52]
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4630              		.loc 1 2290 5 is_stmt 1 discriminator 2 view .LVU1603
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4631              		.loc 1 2290 13 is_stmt 0 discriminator 2 view .LVU1604
+ 4632 0044 C36B     		ldr	r3, [r0, #60]
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4633              		.loc 1 2290 8 discriminator 2 view .LVU1605
+ 4634 0046 33B3     		cbz	r3, .L305
+2293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4635              		.loc 1 2293 7 is_stmt 1 view .LVU1606
+2293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4636              		.loc 1 2293 38 is_stmt 0 view .LVU1607
+ 4637 0048 284A     		ldr	r2, .L313+8
+ 4638              	.LVL294:
+2293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4639              		.loc 1 2293 38 view .LVU1608
+ 4640 004a DA62     		str	r2, [r3, #44]
+2296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4641              		.loc 1 2296 7 is_stmt 1 view .LVU1609
+2296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4642              		.loc 1 2296 11 is_stmt 0 view .LVU1610
+ 4643 004c C36B     		ldr	r3, [r0, #60]
+2296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4644              		.loc 1 2296 39 view .LVU1611
+ 4645 004e 284A     		ldr	r2, .L313+12
+ 4646 0050 5A63     		str	r2, [r3, #52]
+2299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 4647              		.loc 1 2299 7 is_stmt 1 view .LVU1612
+2299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 4648              		.loc 1 2299 11 is_stmt 0 view .LVU1613
+ 4649 0052 C26B     		ldr	r2, [r0, #60]
+2299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 4650              		.loc 1 2299 42 view .LVU1614
+ 4651 0054 0023     		movs	r3, #0
+ 4652 0056 1363     		str	r3, [r2, #48]
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4653              		.loc 1 2300 7 is_stmt 1 view .LVU1615
+ARM GAS  /tmp/ccbUHtu7.s 			page 229
+
+
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4654              		.loc 1 2300 11 is_stmt 0 view .LVU1616
+ 4655 0058 C26B     		ldr	r2, [r0, #60]
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4656              		.loc 1 2300 39 view .LVU1617
+ 4657 005a 9363     		str	r3, [r2, #56]
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 4658              		.loc 1 2303 7 is_stmt 1 view .LVU1618
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 4659              		.loc 1 2303 69 is_stmt 0 view .LVU1619
+ 4660 005c 0068     		ldr	r0, [r0]
+ 4661              	.LVL295:
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 4662              		.loc 1 2303 23 view .LVU1620
+ 4663 005e 238D     		ldrh	r3, [r4, #40]
+ 4664 0060 0A46     		mov	r2, r1
+ 4665 0062 00F12401 		add	r1, r0, #36
+ 4666              	.LVL296:
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 4667              		.loc 1 2303 23 view .LVU1621
+ 4668 0066 E06B     		ldr	r0, [r4, #60]
+ 4669 0068 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 4670              	.LVL297:
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4671              		.loc 1 2321 5 is_stmt 1 view .LVU1622
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4672              		.loc 1 2321 8 is_stmt 0 view .LVU1623
+ 4673 006c 0546     		mov	r5, r0
+ 4674 006e 00B3     		cbz	r0, .L312
+2341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4675              		.loc 1 2341 7 is_stmt 1 view .LVU1624
+2341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4676              		.loc 1 2341 23 is_stmt 0 view .LVU1625
+ 4677 0070 2823     		movs	r3, #40
+ 4678 0072 84F84130 		strb	r3, [r4, #65]
+2342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4679              		.loc 1 2342 7 is_stmt 1 view .LVU1626
+2342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4680              		.loc 1 2342 23 is_stmt 0 view .LVU1627
+ 4681 0076 0022     		movs	r2, #0
+ 4682 0078 84F84220 		strb	r2, [r4, #66]
+2345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4683              		.loc 1 2345 7 is_stmt 1 view .LVU1628
+2345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4684              		.loc 1 2345 11 is_stmt 0 view .LVU1629
+ 4685 007c 636C     		ldr	r3, [r4, #68]
+2345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4686              		.loc 1 2345 23 view .LVU1630
+ 4687 007e 43F01003 		orr	r3, r3, #16
+ 4688 0082 6364     		str	r3, [r4, #68]
+2348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4689              		.loc 1 2348 7 is_stmt 1 view .LVU1631
+2348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4690              		.loc 1 2348 7 view .LVU1632
+ 4691 0084 84F84020 		strb	r2, [r4, #64]
+2348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4692              		.loc 1 2348 7 view .LVU1633
+ARM GAS  /tmp/ccbUHtu7.s 			page 230
+
+
+2350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4693              		.loc 1 2350 7 view .LVU1634
+2350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4694              		.loc 1 2350 14 is_stmt 0 view .LVU1635
+ 4695 0088 0125     		movs	r5, #1
+ 4696 008a 26E0     		b	.L302
+ 4697              	.LVL298:
+ 4698              	.L303:
+2273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 4699              		.loc 1 2273 7 is_stmt 1 view .LVU1636
+2273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 4700              		.loc 1 2273 23 is_stmt 0 view .LVU1637
+ 4701 008c 4FF40073 		mov	r3, #512
+ 4702 0090 6364     		str	r3, [r4, #68]
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4703              		.loc 1 2274 7 is_stmt 1 view .LVU1638
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4704              		.loc 1 2274 15 is_stmt 0 view .LVU1639
+ 4705 0092 0125     		movs	r5, #1
+ 4706 0094 21E0     		b	.L302
+ 4707              	.L305:
+2309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4708              		.loc 1 2309 7 is_stmt 1 view .LVU1640
+2309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4709              		.loc 1 2309 23 is_stmt 0 view .LVU1641
+ 4710 0096 2823     		movs	r3, #40
+ 4711 0098 80F84130 		strb	r3, [r0, #65]
+2310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4712              		.loc 1 2310 7 is_stmt 1 view .LVU1642
+2310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4713              		.loc 1 2310 23 is_stmt 0 view .LVU1643
+ 4714 009c 0022     		movs	r2, #0
+ 4715              	.LVL299:
+2310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4716              		.loc 1 2310 23 view .LVU1644
+ 4717 009e 80F84220 		strb	r2, [r0, #66]
+2313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4718              		.loc 1 2313 7 is_stmt 1 view .LVU1645
+2313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4719              		.loc 1 2313 11 is_stmt 0 view .LVU1646
+ 4720 00a2 436C     		ldr	r3, [r0, #68]
+2313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4721              		.loc 1 2313 23 view .LVU1647
+ 4722 00a4 43F08003 		orr	r3, r3, #128
+ 4723 00a8 4364     		str	r3, [r0, #68]
+2316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4724              		.loc 1 2316 7 is_stmt 1 view .LVU1648
+2316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4725              		.loc 1 2316 7 view .LVU1649
+ 4726 00aa 80F84020 		strb	r2, [r0, #64]
+2316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4727              		.loc 1 2316 7 view .LVU1650
+2318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4728              		.loc 1 2318 7 view .LVU1651
+2318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4729              		.loc 1 2318 14 is_stmt 0 view .LVU1652
+ 4730 00ae 0125     		movs	r5, #1
+ARM GAS  /tmp/ccbUHtu7.s 			page 231
+
+
+ 4731 00b0 13E0     		b	.L302
+ 4732              	.LVL300:
+ 4733              	.L312:
+2324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4734              		.loc 1 2324 7 is_stmt 1 view .LVU1653
+2324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4735              		.loc 1 2324 11 is_stmt 0 view .LVU1654
+ 4736 00b2 2268     		ldr	r2, [r4]
+2324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4737              		.loc 1 2324 21 view .LVU1655
+ 4738 00b4 5368     		ldr	r3, [r2, #4]
+2324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4739              		.loc 1 2324 27 view .LVU1656
+ 4740 00b6 23F40043 		bic	r3, r3, #32768
+ 4741 00ba 5360     		str	r3, [r2, #4]
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4742              		.loc 1 2327 7 is_stmt 1 view .LVU1657
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4743              		.loc 1 2327 7 view .LVU1658
+ 4744 00bc 0023     		movs	r3, #0
+ 4745 00be 84F84030 		strb	r3, [r4, #64]
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4746              		.loc 1 2327 7 view .LVU1659
+2333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4747              		.loc 1 2333 7 view .LVU1660
+ 4748 00c2 4FF40041 		mov	r1, #32768
+ 4749 00c6 2046     		mov	r0, r4
+ 4750              	.LVL301:
+2333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4751              		.loc 1 2333 7 is_stmt 0 view .LVU1661
+ 4752 00c8 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 4753              	.LVL302:
+2336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4754              		.loc 1 2336 7 is_stmt 1 view .LVU1662
+2336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4755              		.loc 1 2336 11 is_stmt 0 view .LVU1663
+ 4756 00cc 2268     		ldr	r2, [r4]
+2336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4757              		.loc 1 2336 21 view .LVU1664
+ 4758 00ce 1368     		ldr	r3, [r2]
+2336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4759              		.loc 1 2336 27 view .LVU1665
+ 4760 00d0 43F40043 		orr	r3, r3, #32768
+ 4761 00d4 1360     		str	r3, [r2]
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 4762              		.loc 1 2353 5 is_stmt 1 view .LVU1666
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 4763              		.loc 1 2353 12 is_stmt 0 view .LVU1667
+ 4764 00d6 00E0     		b	.L302
+ 4765              	.LVL303:
+ 4766              	.L308:
+2357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 4767              		.loc 1 2357 12 view .LVU1668
+ 4768 00d8 0225     		movs	r5, #2
+ 4769              	.LVL304:
+ 4770              	.L302:
+2359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ARM GAS  /tmp/ccbUHtu7.s 			page 232
+
+
+ 4771              		.loc 1 2359 1 view .LVU1669
+ 4772 00da 2846     		mov	r0, r5
+ 4773 00dc 38BD     		pop	{r3, r4, r5, pc}
+ 4774              	.LVL305:
+ 4775              	.L309:
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4776              		.loc 1 2277 5 view .LVU1670
+ 4777 00de 0225     		movs	r5, #2
+ 4778 00e0 FBE7     		b	.L302
+ 4779              	.L314:
+ 4780 00e2 00BF     		.align	2
+ 4781              	.L313:
+ 4782 00e4 0000FFFF 		.word	-65536
+ 4783 00e8 00000000 		.word	I2C_Slave_ISR_DMA
+ 4784 00ec 00000000 		.word	I2C_DMASlaveReceiveCplt
+ 4785 00f0 00000000 		.word	I2C_DMAError
+ 4786              		.cfi_endproc
+ 4787              	.LFE344:
+ 4789              		.section	.text.HAL_I2C_Mem_Write,"ax",%progbits
+ 4790              		.align	1
+ 4791              		.global	HAL_I2C_Mem_Write
+ 4792              		.syntax unified
+ 4793              		.thumb
+ 4794              		.thumb_func
+ 4796              	HAL_I2C_Mem_Write:
+ 4797              	.LVL306:
+ 4798              	.LFB345:
+2375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 4799              		.loc 1 2375 1 is_stmt 1 view -0
+ 4800              		.cfi_startproc
+ 4801              		@ args = 12, pretend = 0, frame = 0
+ 4802              		@ frame_needed = 0, uses_anonymous_args = 0
+2375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 4803              		.loc 1 2375 1 is_stmt 0 view .LVU1672
+ 4804 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 4805              	.LCFI55:
+ 4806              		.cfi_def_cfa_offset 36
+ 4807              		.cfi_offset 4, -36
+ 4808              		.cfi_offset 5, -32
+ 4809              		.cfi_offset 6, -28
+ 4810              		.cfi_offset 7, -24
+ 4811              		.cfi_offset 8, -20
+ 4812              		.cfi_offset 9, -16
+ 4813              		.cfi_offset 10, -12
+ 4814              		.cfi_offset 11, -8
+ 4815              		.cfi_offset 14, -4
+ 4816 0004 83B0     		sub	sp, sp, #12
+ 4817              	.LCFI56:
+ 4818              		.cfi_def_cfa_offset 48
+ 4819 0006 0E46     		mov	r6, r1
+ 4820 0008 BDF834A0 		ldrh	r10, [sp, #52]
+ 4821 000c 0E9D     		ldr	r5, [sp, #56]
+2376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4822              		.loc 1 2376 3 is_stmt 1 view .LVU1673
+2379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4823              		.loc 1 2379 3 view .LVU1674
+2381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 233
+
+
+ 4824              		.loc 1 2381 3 view .LVU1675
+2381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4825              		.loc 1 2381 11 is_stmt 0 view .LVU1676
+ 4826 000e 90F84110 		ldrb	r1, [r0, #65]	@ zero_extendqisi2
+ 4827              	.LVL307:
+2381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4828              		.loc 1 2381 11 view .LVU1677
+ 4829 0012 C9B2     		uxtb	r1, r1
+2381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 4830              		.loc 1 2381 6 view .LVU1678
+ 4831 0014 2029     		cmp	r1, #32
+ 4832 0016 40F0BB80 		bne	.L325
+ 4833 001a 0446     		mov	r4, r0
+ 4834 001c 9046     		mov	r8, r2
+ 4835 001e 9946     		mov	r9, r3
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4836              		.loc 1 2383 5 is_stmt 1 view .LVU1679
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4837              		.loc 1 2383 8 is_stmt 0 view .LVU1680
+ 4838 0020 0C9B     		ldr	r3, [sp, #48]
+ 4839              	.LVL308:
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4840              		.loc 1 2383 8 view .LVU1681
+ 4841 0022 CBB1     		cbz	r3, .L317
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4842              		.loc 1 2383 25 discriminator 1 view .LVU1682
+ 4843 0024 BAF1000F 		cmp	r10, #0
+ 4844 0028 16D0     		beq	.L317
+2390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4845              		.loc 1 2390 5 is_stmt 1 view .LVU1683
+2390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4846              		.loc 1 2390 5 view .LVU1684
+ 4847 002a 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 4848 002e 012B     		cmp	r3, #1
+ 4849 0030 00F0B280 		beq	.L326
+2390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4850              		.loc 1 2390 5 discriminator 2 view .LVU1685
+ 4851 0034 4FF0010B 		mov	fp, #1
+ 4852 0038 80F840B0 		strb	fp, [r0, #64]
+2390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4853              		.loc 1 2390 5 discriminator 2 view .LVU1686
+2393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4854              		.loc 1 2393 5 discriminator 2 view .LVU1687
+2393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4855              		.loc 1 2393 17 is_stmt 0 discriminator 2 view .LVU1688
+ 4856 003c FFF7FEFF 		bl	HAL_GetTick
+ 4857              	.LVL309:
+2393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4858              		.loc 1 2393 17 discriminator 2 view .LVU1689
+ 4859 0040 0746     		mov	r7, r0
+ 4860              	.LVL310:
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4861              		.loc 1 2395 5 is_stmt 1 discriminator 2 view .LVU1690
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4862              		.loc 1 2395 9 is_stmt 0 discriminator 2 view .LVU1691
+ 4863 0042 0090     		str	r0, [sp]
+ 4864 0044 1923     		movs	r3, #25
+ARM GAS  /tmp/ccbUHtu7.s 			page 234
+
+
+ 4865 0046 5A46     		mov	r2, fp
+ 4866 0048 4FF40041 		mov	r1, #32768
+ 4867 004c 2046     		mov	r0, r4
+ 4868              	.LVL311:
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4869              		.loc 1 2395 9 discriminator 2 view .LVU1692
+ 4870 004e FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 4871              	.LVL312:
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4872              		.loc 1 2395 8 discriminator 2 view .LVU1693
+ 4873 0052 30B1     		cbz	r0, .L332
+2397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4874              		.loc 1 2397 14 view .LVU1694
+ 4875 0054 0120     		movs	r0, #1
+ 4876 0056 9CE0     		b	.L316
+ 4877              	.LVL313:
+ 4878              	.L317:
+2385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 4879              		.loc 1 2385 7 is_stmt 1 view .LVU1695
+2385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 4880              		.loc 1 2385 23 is_stmt 0 view .LVU1696
+ 4881 0058 4FF40073 		mov	r3, #512
+ 4882 005c 6364     		str	r3, [r4, #68]
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4883              		.loc 1 2386 7 is_stmt 1 view .LVU1697
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4884              		.loc 1 2386 15 is_stmt 0 view .LVU1698
+ 4885 005e 0120     		movs	r0, #1
+ 4886              	.LVL314:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4887              		.loc 1 2386 15 view .LVU1699
+ 4888 0060 97E0     		b	.L316
+ 4889              	.LVL315:
+ 4890              	.L332:
+2400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MEM;
+ 4891              		.loc 1 2400 5 is_stmt 1 view .LVU1700
+2400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MEM;
+ 4892              		.loc 1 2400 21 is_stmt 0 view .LVU1701
+ 4893 0062 2123     		movs	r3, #33
+ 4894 0064 84F84130 		strb	r3, [r4, #65]
+2401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 4895              		.loc 1 2401 5 is_stmt 1 view .LVU1702
+2401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 4896              		.loc 1 2401 21 is_stmt 0 view .LVU1703
+ 4897 0068 4023     		movs	r3, #64
+ 4898 006a 84F84230 		strb	r3, [r4, #66]
+2402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4899              		.loc 1 2402 5 is_stmt 1 view .LVU1704
+2402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4900              		.loc 1 2402 21 is_stmt 0 view .LVU1705
+ 4901 006e 0023     		movs	r3, #0
+ 4902 0070 6364     		str	r3, [r4, #68]
+2405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 4903              		.loc 1 2405 5 is_stmt 1 view .LVU1706
+2405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 4904              		.loc 1 2405 21 is_stmt 0 view .LVU1707
+ 4905 0072 0C9A     		ldr	r2, [sp, #48]
+ARM GAS  /tmp/ccbUHtu7.s 			page 235
+
+
+ 4906 0074 6262     		str	r2, [r4, #36]
+2406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 4907              		.loc 1 2406 5 is_stmt 1 view .LVU1708
+2406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 4908              		.loc 1 2406 21 is_stmt 0 view .LVU1709
+ 4909 0076 A4F82AA0 		strh	r10, [r4, #42]	@ movhi
+2407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4910              		.loc 1 2407 5 is_stmt 1 view .LVU1710
+2407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4911              		.loc 1 2407 21 is_stmt 0 view .LVU1711
+ 4912 007a 6363     		str	r3, [r4, #52]
+2410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4913              		.loc 1 2410 5 is_stmt 1 view .LVU1712
+2410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4914              		.loc 1 2410 9 is_stmt 0 view .LVU1713
+ 4915 007c 0197     		str	r7, [sp, #4]
+ 4916 007e 0095     		str	r5, [sp]
+ 4917 0080 4B46     		mov	r3, r9
+ 4918 0082 4246     		mov	r2, r8
+ 4919 0084 3146     		mov	r1, r6
+ 4920 0086 2046     		mov	r0, r4
+ 4921 0088 FFF7FEFF 		bl	I2C_RequestMemoryWrite
+ 4922              	.LVL316:
+2410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4923              		.loc 1 2410 8 view .LVU1714
+ 4924 008c 70B9     		cbnz	r0, .L333
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4925              		.loc 1 2418 5 is_stmt 1 view .LVU1715
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4926              		.loc 1 2418 13 is_stmt 0 view .LVU1716
+ 4927 008e 638D     		ldrh	r3, [r4, #42]
+ 4928 0090 9BB2     		uxth	r3, r3
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4929              		.loc 1 2418 8 view .LVU1717
+ 4930 0092 FF2B     		cmp	r3, #255
+ 4931 0094 0FD9     		bls	.L320
+2420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST
+ 4932              		.loc 1 2420 7 is_stmt 1 view .LVU1718
+2420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST
+ 4933              		.loc 1 2420 22 is_stmt 0 view .LVU1719
+ 4934 0096 FF22     		movs	r2, #255
+ 4935 0098 2285     		strh	r2, [r4, #40]	@ movhi
+2421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4936              		.loc 1 2421 7 is_stmt 1 view .LVU1720
+ 4937 009a 0023     		movs	r3, #0
+ 4938 009c 0093     		str	r3, [sp]
+ 4939 009e 4FF08073 		mov	r3, #16777216
+ 4940 00a2 3146     		mov	r1, r6
+ 4941 00a4 2046     		mov	r0, r4
+ 4942 00a6 FFF7FEFF 		bl	I2C_TransferConfig
+ 4943              	.LVL317:
+ 4944 00aa 21E0     		b	.L324
+ 4945              	.L333:
+2413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 4946              		.loc 1 2413 7 view .LVU1721
+2413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 4947              		.loc 1 2413 7 view .LVU1722
+ARM GAS  /tmp/ccbUHtu7.s 			page 236
+
+
+ 4948 00ac 0023     		movs	r3, #0
+ 4949 00ae 84F84030 		strb	r3, [r4, #64]
+2413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 4950              		.loc 1 2413 7 view .LVU1723
+2414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4951              		.loc 1 2414 7 view .LVU1724
+2414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4952              		.loc 1 2414 14 is_stmt 0 view .LVU1725
+ 4953 00b2 5846     		mov	r0, fp
+ 4954 00b4 6DE0     		b	.L316
+ 4955              	.L320:
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS
+ 4956              		.loc 1 2425 7 is_stmt 1 view .LVU1726
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS
+ 4957              		.loc 1 2425 28 is_stmt 0 view .LVU1727
+ 4958 00b6 628D     		ldrh	r2, [r4, #42]
+ 4959 00b8 92B2     		uxth	r2, r2
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS
+ 4960              		.loc 1 2425 22 view .LVU1728
+ 4961 00ba 2285     		strh	r2, [r4, #40]	@ movhi
+2426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 4962              		.loc 1 2426 7 is_stmt 1 view .LVU1729
+ 4963 00bc 0023     		movs	r3, #0
+ 4964 00be 0093     		str	r3, [sp]
+ 4965 00c0 4FF00073 		mov	r3, #33554432
+ 4966 00c4 D2B2     		uxtb	r2, r2
+ 4967 00c6 3146     		mov	r1, r6
+ 4968 00c8 2046     		mov	r0, r4
+ 4969 00ca FFF7FEFF 		bl	I2C_TransferConfig
+ 4970              	.LVL318:
+ 4971 00ce 0FE0     		b	.L324
+ 4972              	.L323:
+2462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 4973              		.loc 1 2462 11 view .LVU1730
+2462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 4974              		.loc 1 2462 32 is_stmt 0 view .LVU1731
+ 4975 00d0 628D     		ldrh	r2, [r4, #42]
+ 4976 00d2 92B2     		uxth	r2, r2
+2462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 4977              		.loc 1 2462 26 view .LVU1732
+ 4978 00d4 2285     		strh	r2, [r4, #40]	@ movhi
+2463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 4979              		.loc 1 2463 11 is_stmt 1 view .LVU1733
+ 4980 00d6 0023     		movs	r3, #0
+ 4981 00d8 0093     		str	r3, [sp]
+ 4982 00da 4FF00073 		mov	r3, #33554432
+ 4983 00de D2B2     		uxtb	r2, r2
+ 4984 00e0 3146     		mov	r1, r6
+ 4985 00e2 2046     		mov	r0, r4
+ 4986 00e4 FFF7FEFF 		bl	I2C_TransferConfig
+ 4987              	.LVL319:
+ 4988              	.L322:
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4989              		.loc 1 2468 30 view .LVU1734
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4990              		.loc 1 2468 18 is_stmt 0 view .LVU1735
+ 4991 00e8 638D     		ldrh	r3, [r4, #42]
+ARM GAS  /tmp/ccbUHtu7.s 			page 237
+
+
+ 4992 00ea 9BB2     		uxth	r3, r3
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 4993              		.loc 1 2468 30 view .LVU1736
+ 4994 00ec 002B     		cmp	r3, #0
+ 4995 00ee 33D0     		beq	.L334
+ 4996              	.L324:
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 4997              		.loc 1 2429 5 is_stmt 1 view .LVU1737
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 4998              		.loc 1 2432 7 view .LVU1738
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 4999              		.loc 1 2432 11 is_stmt 0 view .LVU1739
+ 5000 00f0 3A46     		mov	r2, r7
+ 5001 00f2 2946     		mov	r1, r5
+ 5002 00f4 2046     		mov	r0, r4
+ 5003 00f6 FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 5004              	.LVL320:
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 5005              		.loc 1 2432 10 view .LVU1740
+ 5006 00fa 0028     		cmp	r0, #0
+ 5007 00fc 4ED1     		bne	.L328
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5008              		.loc 1 2438 7 is_stmt 1 view .LVU1741
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5009              		.loc 1 2438 35 is_stmt 0 view .LVU1742
+ 5010 00fe 626A     		ldr	r2, [r4, #36]
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5011              		.loc 1 2438 11 view .LVU1743
+ 5012 0100 2368     		ldr	r3, [r4]
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5013              		.loc 1 2438 30 view .LVU1744
+ 5014 0102 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5015              		.loc 1 2438 28 view .LVU1745
+ 5016 0104 9A62     		str	r2, [r3, #40]
+2441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5017              		.loc 1 2441 7 is_stmt 1 view .LVU1746
+2441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5018              		.loc 1 2441 11 is_stmt 0 view .LVU1747
+ 5019 0106 636A     		ldr	r3, [r4, #36]
+2441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5020              		.loc 1 2441 21 view .LVU1748
+ 5021 0108 0133     		adds	r3, r3, #1
+ 5022 010a 6362     		str	r3, [r4, #36]
+2443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+ 5023              		.loc 1 2443 7 is_stmt 1 view .LVU1749
+2443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+ 5024              		.loc 1 2443 11 is_stmt 0 view .LVU1750
+ 5025 010c 638D     		ldrh	r3, [r4, #42]
+ 5026 010e 9BB2     		uxth	r3, r3
+2443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+ 5027              		.loc 1 2443 22 view .LVU1751
+ 5028 0110 013B     		subs	r3, r3, #1
+ 5029 0112 9BB2     		uxth	r3, r3
+ 5030 0114 6385     		strh	r3, [r4, #42]	@ movhi
+2444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5031              		.loc 1 2444 7 is_stmt 1 view .LVU1752
+ARM GAS  /tmp/ccbUHtu7.s 			page 238
+
+
+2444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5032              		.loc 1 2444 11 is_stmt 0 view .LVU1753
+ 5033 0116 238D     		ldrh	r3, [r4, #40]
+2444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5034              		.loc 1 2444 21 view .LVU1754
+ 5035 0118 013B     		subs	r3, r3, #1
+ 5036 011a 9BB2     		uxth	r3, r3
+ 5037 011c 2385     		strh	r3, [r4, #40]	@ movhi
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 5038              		.loc 1 2446 7 is_stmt 1 view .LVU1755
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 5039              		.loc 1 2446 16 is_stmt 0 view .LVU1756
+ 5040 011e 628D     		ldrh	r2, [r4, #42]
+ 5041 0120 92B2     		uxth	r2, r2
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 5042              		.loc 1 2446 10 view .LVU1757
+ 5043 0122 002A     		cmp	r2, #0
+ 5044 0124 E0D0     		beq	.L322
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 5045              		.loc 1 2446 35 discriminator 1 view .LVU1758
+ 5046 0126 002B     		cmp	r3, #0
+ 5047 0128 DED1     		bne	.L322
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 5048              		.loc 1 2449 9 is_stmt 1 view .LVU1759
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 5049              		.loc 1 2449 13 is_stmt 0 view .LVU1760
+ 5050 012a 0097     		str	r7, [sp]
+ 5051 012c 2B46     		mov	r3, r5
+ 5052 012e 0022     		movs	r2, #0
+ 5053 0130 8021     		movs	r1, #128
+ 5054 0132 2046     		mov	r0, r4
+ 5055 0134 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 5056              	.LVL321:
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 5057              		.loc 1 2449 12 view .LVU1761
+ 5058 0138 90BB     		cbnz	r0, .L329
+2454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 5059              		.loc 1 2454 9 is_stmt 1 view .LVU1762
+2454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 5060              		.loc 1 2454 17 is_stmt 0 view .LVU1763
+ 5061 013a 638D     		ldrh	r3, [r4, #42]
+ 5062 013c 9BB2     		uxth	r3, r3
+2454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 5063              		.loc 1 2454 12 view .LVU1764
+ 5064 013e FF2B     		cmp	r3, #255
+ 5065 0140 C6D9     		bls	.L323
+2456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 5066              		.loc 1 2456 11 is_stmt 1 view .LVU1765
+2456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 5067              		.loc 1 2456 26 is_stmt 0 view .LVU1766
+ 5068 0142 FF22     		movs	r2, #255
+ 5069 0144 2285     		strh	r2, [r4, #40]	@ movhi
+2457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 5070              		.loc 1 2457 11 is_stmt 1 view .LVU1767
+ 5071 0146 0023     		movs	r3, #0
+ 5072 0148 0093     		str	r3, [sp]
+ 5073 014a 4FF08073 		mov	r3, #16777216
+ARM GAS  /tmp/ccbUHtu7.s 			page 239
+
+
+ 5074 014e 3146     		mov	r1, r6
+ 5075 0150 2046     		mov	r0, r4
+ 5076 0152 FFF7FEFF 		bl	I2C_TransferConfig
+ 5077              	.LVL322:
+ 5078 0156 C7E7     		b	.L322
+ 5079              	.L334:
+2472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5080              		.loc 1 2472 5 view .LVU1768
+2472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5081              		.loc 1 2472 9 is_stmt 0 view .LVU1769
+ 5082 0158 3A46     		mov	r2, r7
+ 5083 015a 2946     		mov	r1, r5
+ 5084 015c 2046     		mov	r0, r4
+ 5085 015e FFF7FEFF 		bl	I2C_WaitOnSTOPFlagUntilTimeout
+ 5086              	.LVL323:
+2472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5087              		.loc 1 2472 8 view .LVU1770
+ 5088 0162 F8B9     		cbnz	r0, .L330
+2478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5089              		.loc 1 2478 5 is_stmt 1 view .LVU1771
+ 5090 0164 2368     		ldr	r3, [r4]
+ 5091 0166 2022     		movs	r2, #32
+ 5092 0168 DA61     		str	r2, [r3, #28]
+2481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5093              		.loc 1 2481 5 view .LVU1772
+ 5094 016a 2168     		ldr	r1, [r4]
+ 5095 016c 4B68     		ldr	r3, [r1, #4]
+ 5096 016e 23F0FF73 		bic	r3, r3, #33423360
+ 5097 0172 23F48B33 		bic	r3, r3, #71168
+ 5098 0176 23F4FF73 		bic	r3, r3, #510
+ 5099 017a 23F00103 		bic	r3, r3, #1
+ 5100 017e 4B60     		str	r3, [r1, #4]
+2483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 5101              		.loc 1 2483 5 view .LVU1773
+2483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 5102              		.loc 1 2483 17 is_stmt 0 view .LVU1774
+ 5103 0180 84F84120 		strb	r2, [r4, #65]
+2484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5104              		.loc 1 2484 5 is_stmt 1 view .LVU1775
+2484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5105              		.loc 1 2484 17 is_stmt 0 view .LVU1776
+ 5106 0184 0023     		movs	r3, #0
+ 5107 0186 84F84230 		strb	r3, [r4, #66]
+2487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5108              		.loc 1 2487 5 is_stmt 1 view .LVU1777
+2487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5109              		.loc 1 2487 5 view .LVU1778
+ 5110 018a 84F84030 		strb	r3, [r4, #64]
+2487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5111              		.loc 1 2487 5 view .LVU1779
+2489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 5112              		.loc 1 2489 5 view .LVU1780
+2489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 5113              		.loc 1 2489 12 is_stmt 0 view .LVU1781
+ 5114 018e 00E0     		b	.L316
+ 5115              	.LVL324:
+ 5116              	.L325:
+ARM GAS  /tmp/ccbUHtu7.s 			page 240
+
+
+2493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 5117              		.loc 1 2493 12 view .LVU1782
+ 5118 0190 0220     		movs	r0, #2
+ 5119              	.LVL325:
+ 5120              	.L316:
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5121              		.loc 1 2495 1 view .LVU1783
+ 5122 0192 03B0     		add	sp, sp, #12
+ 5123              	.LCFI57:
+ 5124              		.cfi_remember_state
+ 5125              		.cfi_def_cfa_offset 36
+ 5126              		@ sp needed
+ 5127 0194 BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 5128              	.LVL326:
+ 5129              	.L326:
+ 5130              	.LCFI58:
+ 5131              		.cfi_restore_state
+2390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5132              		.loc 1 2390 5 view .LVU1784
+ 5133 0198 0220     		movs	r0, #2
+ 5134              	.LVL327:
+2390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5135              		.loc 1 2390 5 view .LVU1785
+ 5136 019a FAE7     		b	.L316
+ 5137              	.LVL328:
+ 5138              	.L328:
+2434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 5139              		.loc 1 2434 16 view .LVU1786
+ 5140 019c 0120     		movs	r0, #1
+ 5141 019e F8E7     		b	.L316
+ 5142              	.L329:
+2451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 5143              		.loc 1 2451 18 view .LVU1787
+ 5144 01a0 0120     		movs	r0, #1
+ 5145 01a2 F6E7     		b	.L316
+ 5146              	.L330:
+2474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5147              		.loc 1 2474 14 view .LVU1788
+ 5148 01a4 0120     		movs	r0, #1
+ 5149 01a6 F4E7     		b	.L316
+ 5150              		.cfi_endproc
+ 5151              	.LFE345:
+ 5153              		.section	.text.HAL_I2C_Mem_Read,"ax",%progbits
+ 5154              		.align	1
+ 5155              		.global	HAL_I2C_Mem_Read
+ 5156              		.syntax unified
+ 5157              		.thumb
+ 5158              		.thumb_func
+ 5160              	HAL_I2C_Mem_Read:
+ 5161              	.LVL329:
+ 5162              	.LFB346:
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 5163              		.loc 1 2512 1 is_stmt 1 view -0
+ 5164              		.cfi_startproc
+ 5165              		@ args = 12, pretend = 0, frame = 0
+ 5166              		@ frame_needed = 0, uses_anonymous_args = 0
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ARM GAS  /tmp/ccbUHtu7.s 			page 241
+
+
+ 5167              		.loc 1 2512 1 is_stmt 0 view .LVU1790
+ 5168 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 5169              	.LCFI59:
+ 5170              		.cfi_def_cfa_offset 36
+ 5171              		.cfi_offset 4, -36
+ 5172              		.cfi_offset 5, -32
+ 5173              		.cfi_offset 6, -28
+ 5174              		.cfi_offset 7, -24
+ 5175              		.cfi_offset 8, -20
+ 5176              		.cfi_offset 9, -16
+ 5177              		.cfi_offset 10, -12
+ 5178              		.cfi_offset 11, -8
+ 5179              		.cfi_offset 14, -4
+ 5180 0004 83B0     		sub	sp, sp, #12
+ 5181              	.LCFI60:
+ 5182              		.cfi_def_cfa_offset 48
+ 5183 0006 0E46     		mov	r6, r1
+ 5184 0008 BDF834A0 		ldrh	r10, [sp, #52]
+ 5185 000c 0E9D     		ldr	r5, [sp, #56]
+2513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5186              		.loc 1 2513 3 is_stmt 1 view .LVU1791
+2516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5187              		.loc 1 2516 3 view .LVU1792
+2518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 5188              		.loc 1 2518 3 view .LVU1793
+2518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 5189              		.loc 1 2518 11 is_stmt 0 view .LVU1794
+ 5190 000e 90F84110 		ldrb	r1, [r0, #65]	@ zero_extendqisi2
+ 5191              	.LVL330:
+2518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 5192              		.loc 1 2518 11 view .LVU1795
+ 5193 0012 C9B2     		uxtb	r1, r1
+2518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 5194              		.loc 1 2518 6 view .LVU1796
+ 5195 0014 2029     		cmp	r1, #32
+ 5196 0016 40F0BC80 		bne	.L345
+ 5197 001a 0446     		mov	r4, r0
+ 5198 001c 9046     		mov	r8, r2
+ 5199 001e 9946     		mov	r9, r3
+2520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5200              		.loc 1 2520 5 is_stmt 1 view .LVU1797
+2520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5201              		.loc 1 2520 8 is_stmt 0 view .LVU1798
+ 5202 0020 0C9B     		ldr	r3, [sp, #48]
+ 5203              	.LVL331:
+2520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5204              		.loc 1 2520 8 view .LVU1799
+ 5205 0022 CBB1     		cbz	r3, .L337
+2520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5206              		.loc 1 2520 25 discriminator 1 view .LVU1800
+ 5207 0024 BAF1000F 		cmp	r10, #0
+ 5208 0028 16D0     		beq	.L337
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5209              		.loc 1 2527 5 is_stmt 1 view .LVU1801
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5210              		.loc 1 2527 5 view .LVU1802
+ 5211 002a 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ARM GAS  /tmp/ccbUHtu7.s 			page 242
+
+
+ 5212 002e 012B     		cmp	r3, #1
+ 5213 0030 00F0B380 		beq	.L346
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5214              		.loc 1 2527 5 discriminator 2 view .LVU1803
+ 5215 0034 4FF0010B 		mov	fp, #1
+ 5216 0038 80F840B0 		strb	fp, [r0, #64]
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5217              		.loc 1 2527 5 discriminator 2 view .LVU1804
+2530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5218              		.loc 1 2530 5 discriminator 2 view .LVU1805
+2530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5219              		.loc 1 2530 17 is_stmt 0 discriminator 2 view .LVU1806
+ 5220 003c FFF7FEFF 		bl	HAL_GetTick
+ 5221              	.LVL332:
+2530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5222              		.loc 1 2530 17 discriminator 2 view .LVU1807
+ 5223 0040 0746     		mov	r7, r0
+ 5224              	.LVL333:
+2532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5225              		.loc 1 2532 5 is_stmt 1 discriminator 2 view .LVU1808
+2532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5226              		.loc 1 2532 9 is_stmt 0 discriminator 2 view .LVU1809
+ 5227 0042 0090     		str	r0, [sp]
+ 5228 0044 1923     		movs	r3, #25
+ 5229 0046 5A46     		mov	r2, fp
+ 5230 0048 4FF40041 		mov	r1, #32768
+ 5231 004c 2046     		mov	r0, r4
+ 5232              	.LVL334:
+2532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5233              		.loc 1 2532 9 discriminator 2 view .LVU1810
+ 5234 004e FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 5235              	.LVL335:
+2532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5236              		.loc 1 2532 8 discriminator 2 view .LVU1811
+ 5237 0052 30B1     		cbz	r0, .L352
+2534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5238              		.loc 1 2534 14 view .LVU1812
+ 5239 0054 0120     		movs	r0, #1
+ 5240 0056 9DE0     		b	.L336
+ 5241              	.LVL336:
+ 5242              	.L337:
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 5243              		.loc 1 2522 7 is_stmt 1 view .LVU1813
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 5244              		.loc 1 2522 23 is_stmt 0 view .LVU1814
+ 5245 0058 4FF40073 		mov	r3, #512
+ 5246 005c 6364     		str	r3, [r4, #68]
+2523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5247              		.loc 1 2523 7 is_stmt 1 view .LVU1815
+2523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5248              		.loc 1 2523 15 is_stmt 0 view .LVU1816
+ 5249 005e 0120     		movs	r0, #1
+ 5250              	.LVL337:
+2523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5251              		.loc 1 2523 15 view .LVU1817
+ 5252 0060 98E0     		b	.L336
+ 5253              	.LVL338:
+ARM GAS  /tmp/ccbUHtu7.s 			page 243
+
+
+ 5254              	.L352:
+2537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MEM;
+ 5255              		.loc 1 2537 5 is_stmt 1 view .LVU1818
+2537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MEM;
+ 5256              		.loc 1 2537 21 is_stmt 0 view .LVU1819
+ 5257 0062 2223     		movs	r3, #34
+ 5258 0064 84F84130 		strb	r3, [r4, #65]
+2538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 5259              		.loc 1 2538 5 is_stmt 1 view .LVU1820
+2538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 5260              		.loc 1 2538 21 is_stmt 0 view .LVU1821
+ 5261 0068 4023     		movs	r3, #64
+ 5262 006a 84F84230 		strb	r3, [r4, #66]
+2539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5263              		.loc 1 2539 5 is_stmt 1 view .LVU1822
+2539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5264              		.loc 1 2539 21 is_stmt 0 view .LVU1823
+ 5265 006e 0023     		movs	r3, #0
+ 5266 0070 6364     		str	r3, [r4, #68]
+2542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 5267              		.loc 1 2542 5 is_stmt 1 view .LVU1824
+2542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 5268              		.loc 1 2542 21 is_stmt 0 view .LVU1825
+ 5269 0072 0C9A     		ldr	r2, [sp, #48]
+ 5270 0074 6262     		str	r2, [r4, #36]
+2543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 5271              		.loc 1 2543 5 is_stmt 1 view .LVU1826
+2543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 5272              		.loc 1 2543 21 is_stmt 0 view .LVU1827
+ 5273 0076 A4F82AA0 		strh	r10, [r4, #42]	@ movhi
+2544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5274              		.loc 1 2544 5 is_stmt 1 view .LVU1828
+2544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5275              		.loc 1 2544 21 is_stmt 0 view .LVU1829
+ 5276 007a 6363     		str	r3, [r4, #52]
+2547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5277              		.loc 1 2547 5 is_stmt 1 view .LVU1830
+2547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5278              		.loc 1 2547 9 is_stmt 0 view .LVU1831
+ 5279 007c 0197     		str	r7, [sp, #4]
+ 5280 007e 0095     		str	r5, [sp]
+ 5281 0080 4B46     		mov	r3, r9
+ 5282 0082 4246     		mov	r2, r8
+ 5283 0084 3146     		mov	r1, r6
+ 5284 0086 2046     		mov	r0, r4
+ 5285 0088 FFF7FEFF 		bl	I2C_RequestMemoryRead
+ 5286              	.LVL339:
+2547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5287              		.loc 1 2547 8 view .LVU1832
+ 5288 008c 70B9     		cbnz	r0, .L353
+2556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5289              		.loc 1 2556 5 is_stmt 1 view .LVU1833
+2556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5290              		.loc 1 2556 13 is_stmt 0 view .LVU1834
+ 5291 008e 638D     		ldrh	r3, [r4, #42]
+ 5292 0090 9BB2     		uxth	r3, r3
+2556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccbUHtu7.s 			page 244
+
+
+ 5293              		.loc 1 2556 8 view .LVU1835
+ 5294 0092 FF2B     		cmp	r3, #255
+ 5295 0094 0FD9     		bls	.L340
+2558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 5296              		.loc 1 2558 7 is_stmt 1 view .LVU1836
+2558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 5297              		.loc 1 2558 22 is_stmt 0 view .LVU1837
+ 5298 0096 FF22     		movs	r2, #255
+ 5299 0098 2285     		strh	r2, [r4, #40]	@ movhi
+2559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 5300              		.loc 1 2559 7 is_stmt 1 view .LVU1838
+ 5301 009a 444B     		ldr	r3, .L355
+ 5302 009c 0093     		str	r3, [sp]
+ 5303 009e 4FF08073 		mov	r3, #16777216
+ 5304 00a2 3146     		mov	r1, r6
+ 5305 00a4 2046     		mov	r0, r4
+ 5306 00a6 FFF7FEFF 		bl	I2C_TransferConfig
+ 5307              	.LVL340:
+ 5308 00aa 21E0     		b	.L344
+ 5309              	.L353:
+2550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 5310              		.loc 1 2550 7 view .LVU1839
+2550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 5311              		.loc 1 2550 7 view .LVU1840
+ 5312 00ac 0023     		movs	r3, #0
+ 5313 00ae 84F84030 		strb	r3, [r4, #64]
+2550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 5314              		.loc 1 2550 7 view .LVU1841
+2551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5315              		.loc 1 2551 7 view .LVU1842
+2551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5316              		.loc 1 2551 14 is_stmt 0 view .LVU1843
+ 5317 00b2 5846     		mov	r0, fp
+ 5318 00b4 6EE0     		b	.L336
+ 5319              	.L340:
+2564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5320              		.loc 1 2564 7 is_stmt 1 view .LVU1844
+2564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5321              		.loc 1 2564 28 is_stmt 0 view .LVU1845
+ 5322 00b6 628D     		ldrh	r2, [r4, #42]
+ 5323 00b8 92B2     		uxth	r2, r2
+2564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5324              		.loc 1 2564 22 view .LVU1846
+ 5325 00ba 2285     		strh	r2, [r4, #40]	@ movhi
+2565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 5326              		.loc 1 2565 7 is_stmt 1 view .LVU1847
+ 5327 00bc 3B4B     		ldr	r3, .L355
+ 5328 00be 0093     		str	r3, [sp]
+ 5329 00c0 4FF00073 		mov	r3, #33554432
+ 5330 00c4 D2B2     		uxtb	r2, r2
+ 5331 00c6 3146     		mov	r1, r6
+ 5332 00c8 2046     		mov	r0, r4
+ 5333 00ca FFF7FEFF 		bl	I2C_TransferConfig
+ 5334              	.LVL341:
+ 5335 00ce 0FE0     		b	.L344
+ 5336              	.L343:
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ARM GAS  /tmp/ccbUHtu7.s 			page 245
+
+
+ 5337              		.loc 1 2602 11 view .LVU1848
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5338              		.loc 1 2602 32 is_stmt 0 view .LVU1849
+ 5339 00d0 628D     		ldrh	r2, [r4, #42]
+ 5340 00d2 92B2     		uxth	r2, r2
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5341              		.loc 1 2602 26 view .LVU1850
+ 5342 00d4 2285     		strh	r2, [r4, #40]	@ movhi
+2603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 5343              		.loc 1 2603 11 is_stmt 1 view .LVU1851
+ 5344 00d6 0023     		movs	r3, #0
+ 5345 00d8 0093     		str	r3, [sp]
+ 5346 00da 4FF00073 		mov	r3, #33554432
+ 5347 00de D2B2     		uxtb	r2, r2
+ 5348 00e0 3146     		mov	r1, r6
+ 5349 00e2 2046     		mov	r0, r4
+ 5350 00e4 FFF7FEFF 		bl	I2C_TransferConfig
+ 5351              	.LVL342:
+ 5352              	.L342:
+2607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5353              		.loc 1 2607 30 view .LVU1852
+2607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5354              		.loc 1 2607 18 is_stmt 0 view .LVU1853
+ 5355 00e8 638D     		ldrh	r3, [r4, #42]
+ 5356 00ea 9BB2     		uxth	r3, r3
+2607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5357              		.loc 1 2607 30 view .LVU1854
+ 5358 00ec 002B     		cmp	r3, #0
+ 5359 00ee 34D0     		beq	.L354
+ 5360              	.L344:
+2569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5361              		.loc 1 2569 5 is_stmt 1 view .LVU1855
+2572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 5362              		.loc 1 2572 7 view .LVU1856
+2572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 5363              		.loc 1 2572 11 is_stmt 0 view .LVU1857
+ 5364 00f0 0097     		str	r7, [sp]
+ 5365 00f2 2B46     		mov	r3, r5
+ 5366 00f4 0022     		movs	r2, #0
+ 5367 00f6 0421     		movs	r1, #4
+ 5368 00f8 2046     		mov	r0, r4
+ 5369 00fa FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 5370              	.LVL343:
+2572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 5371              		.loc 1 2572 10 view .LVU1858
+ 5372 00fe 0028     		cmp	r0, #0
+ 5373 0100 4DD1     		bne	.L348
+2578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5374              		.loc 1 2578 7 is_stmt 1 view .LVU1859
+2578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5375              		.loc 1 2578 38 is_stmt 0 view .LVU1860
+ 5376 0102 2368     		ldr	r3, [r4]
+2578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5377              		.loc 1 2578 48 view .LVU1861
+ 5378 0104 5A6A     		ldr	r2, [r3, #36]
+2578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5379              		.loc 1 2578 12 view .LVU1862
+ARM GAS  /tmp/ccbUHtu7.s 			page 246
+
+
+ 5380 0106 636A     		ldr	r3, [r4, #36]
+2578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5381              		.loc 1 2578 23 view .LVU1863
+ 5382 0108 1A70     		strb	r2, [r3]
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5383              		.loc 1 2581 7 is_stmt 1 view .LVU1864
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5384              		.loc 1 2581 11 is_stmt 0 view .LVU1865
+ 5385 010a 636A     		ldr	r3, [r4, #36]
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5386              		.loc 1 2581 21 view .LVU1866
+ 5387 010c 0133     		adds	r3, r3, #1
+ 5388 010e 6362     		str	r3, [r4, #36]
+2583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 5389              		.loc 1 2583 7 is_stmt 1 view .LVU1867
+2583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 5390              		.loc 1 2583 11 is_stmt 0 view .LVU1868
+ 5391 0110 228D     		ldrh	r2, [r4, #40]
+2583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 5392              		.loc 1 2583 21 view .LVU1869
+ 5393 0112 013A     		subs	r2, r2, #1
+ 5394 0114 92B2     		uxth	r2, r2
+ 5395 0116 2285     		strh	r2, [r4, #40]	@ movhi
+2584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5396              		.loc 1 2584 7 is_stmt 1 view .LVU1870
+2584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5397              		.loc 1 2584 11 is_stmt 0 view .LVU1871
+ 5398 0118 638D     		ldrh	r3, [r4, #42]
+ 5399 011a 9BB2     		uxth	r3, r3
+2584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5400              		.loc 1 2584 22 view .LVU1872
+ 5401 011c 013B     		subs	r3, r3, #1
+ 5402 011e 9BB2     		uxth	r3, r3
+ 5403 0120 6385     		strh	r3, [r4, #42]	@ movhi
+2586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 5404              		.loc 1 2586 7 is_stmt 1 view .LVU1873
+2586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 5405              		.loc 1 2586 16 is_stmt 0 view .LVU1874
+ 5406 0122 638D     		ldrh	r3, [r4, #42]
+ 5407 0124 9BB2     		uxth	r3, r3
+2586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 5408              		.loc 1 2586 10 view .LVU1875
+ 5409 0126 002B     		cmp	r3, #0
+ 5410 0128 DED0     		beq	.L342
+2586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 5411              		.loc 1 2586 35 discriminator 1 view .LVU1876
+ 5412 012a 002A     		cmp	r2, #0
+ 5413 012c DCD1     		bne	.L342
+2589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 5414              		.loc 1 2589 9 is_stmt 1 view .LVU1877
+2589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 5415              		.loc 1 2589 13 is_stmt 0 view .LVU1878
+ 5416 012e 0097     		str	r7, [sp]
+ 5417 0130 2B46     		mov	r3, r5
+ 5418 0132 8021     		movs	r1, #128
+ 5419 0134 2046     		mov	r0, r4
+ 5420 0136 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ARM GAS  /tmp/ccbUHtu7.s 			page 247
+
+
+ 5421              	.LVL344:
+2589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 5422              		.loc 1 2589 12 view .LVU1879
+ 5423 013a 90BB     		cbnz	r0, .L349
+2594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 5424              		.loc 1 2594 9 is_stmt 1 view .LVU1880
+2594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 5425              		.loc 1 2594 17 is_stmt 0 view .LVU1881
+ 5426 013c 638D     		ldrh	r3, [r4, #42]
+ 5427 013e 9BB2     		uxth	r3, r3
+2594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 5428              		.loc 1 2594 12 view .LVU1882
+ 5429 0140 FF2B     		cmp	r3, #255
+ 5430 0142 C5D9     		bls	.L343
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+ 5431              		.loc 1 2596 11 is_stmt 1 view .LVU1883
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+ 5432              		.loc 1 2596 26 is_stmt 0 view .LVU1884
+ 5433 0144 FF22     		movs	r2, #255
+ 5434 0146 2285     		strh	r2, [r4, #40]	@ movhi
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 5435              		.loc 1 2597 11 is_stmt 1 view .LVU1885
+ 5436 0148 0023     		movs	r3, #0
+ 5437 014a 0093     		str	r3, [sp]
+ 5438 014c 4FF08073 		mov	r3, #16777216
+ 5439 0150 3146     		mov	r1, r6
+ 5440 0152 2046     		mov	r0, r4
+ 5441 0154 FFF7FEFF 		bl	I2C_TransferConfig
+ 5442              	.LVL345:
+ 5443 0158 C6E7     		b	.L342
+ 5444              	.L354:
+2611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5445              		.loc 1 2611 5 view .LVU1886
+2611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5446              		.loc 1 2611 9 is_stmt 0 view .LVU1887
+ 5447 015a 3A46     		mov	r2, r7
+ 5448 015c 2946     		mov	r1, r5
+ 5449 015e 2046     		mov	r0, r4
+ 5450 0160 FFF7FEFF 		bl	I2C_WaitOnSTOPFlagUntilTimeout
+ 5451              	.LVL346:
+2611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5452              		.loc 1 2611 8 view .LVU1888
+ 5453 0164 F8B9     		cbnz	r0, .L350
+2617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5454              		.loc 1 2617 5 is_stmt 1 view .LVU1889
+ 5455 0166 2368     		ldr	r3, [r4]
+ 5456 0168 2022     		movs	r2, #32
+ 5457 016a DA61     		str	r2, [r3, #28]
+2620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5458              		.loc 1 2620 5 view .LVU1890
+ 5459 016c 2168     		ldr	r1, [r4]
+ 5460 016e 4B68     		ldr	r3, [r1, #4]
+ 5461 0170 23F0FF73 		bic	r3, r3, #33423360
+ 5462 0174 23F48B33 		bic	r3, r3, #71168
+ 5463 0178 23F4FF73 		bic	r3, r3, #510
+ 5464 017c 23F00103 		bic	r3, r3, #1
+ 5465 0180 4B60     		str	r3, [r1, #4]
+ARM GAS  /tmp/ccbUHtu7.s 			page 248
+
+
+2622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 5466              		.loc 1 2622 5 view .LVU1891
+2622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 5467              		.loc 1 2622 17 is_stmt 0 view .LVU1892
+ 5468 0182 84F84120 		strb	r2, [r4, #65]
+2623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5469              		.loc 1 2623 5 is_stmt 1 view .LVU1893
+2623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5470              		.loc 1 2623 17 is_stmt 0 view .LVU1894
+ 5471 0186 0023     		movs	r3, #0
+ 5472 0188 84F84230 		strb	r3, [r4, #66]
+2626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5473              		.loc 1 2626 5 is_stmt 1 view .LVU1895
+2626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5474              		.loc 1 2626 5 view .LVU1896
+ 5475 018c 84F84030 		strb	r3, [r4, #64]
+2626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5476              		.loc 1 2626 5 view .LVU1897
+2628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 5477              		.loc 1 2628 5 view .LVU1898
+2628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 5478              		.loc 1 2628 12 is_stmt 0 view .LVU1899
+ 5479 0190 00E0     		b	.L336
+ 5480              	.LVL347:
+ 5481              	.L345:
+2632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 5482              		.loc 1 2632 12 view .LVU1900
+ 5483 0192 0220     		movs	r0, #2
+ 5484              	.LVL348:
+ 5485              	.L336:
+2634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ 5486              		.loc 1 2634 1 view .LVU1901
+ 5487 0194 03B0     		add	sp, sp, #12
+ 5488              	.LCFI61:
+ 5489              		.cfi_remember_state
+ 5490              		.cfi_def_cfa_offset 36
+ 5491              		@ sp needed
+ 5492 0196 BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 5493              	.LVL349:
+ 5494              	.L346:
+ 5495              	.LCFI62:
+ 5496              		.cfi_restore_state
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5497              		.loc 1 2527 5 view .LVU1902
+ 5498 019a 0220     		movs	r0, #2
+ 5499              	.LVL350:
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5500              		.loc 1 2527 5 view .LVU1903
+ 5501 019c FAE7     		b	.L336
+ 5502              	.LVL351:
+ 5503              	.L348:
+2574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 5504              		.loc 1 2574 16 view .LVU1904
+ 5505 019e 0120     		movs	r0, #1
+ 5506 01a0 F8E7     		b	.L336
+ 5507              	.L349:
+2591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ARM GAS  /tmp/ccbUHtu7.s 			page 249
+
+
+ 5508              		.loc 1 2591 18 view .LVU1905
+ 5509 01a2 0120     		movs	r0, #1
+ 5510 01a4 F6E7     		b	.L336
+ 5511              	.L350:
+2613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5512              		.loc 1 2613 14 view .LVU1906
+ 5513 01a6 0120     		movs	r0, #1
+ 5514 01a8 F4E7     		b	.L336
+ 5515              	.L356:
+ 5516 01aa 00BF     		.align	2
+ 5517              	.L355:
+ 5518 01ac 00240080 		.word	-2147474432
+ 5519              		.cfi_endproc
+ 5520              	.LFE346:
+ 5522              		.section	.text.HAL_I2C_Mem_Write_IT,"ax",%progbits
+ 5523              		.align	1
+ 5524              		.global	HAL_I2C_Mem_Write_IT
+ 5525              		.syntax unified
+ 5526              		.thumb
+ 5527              		.thumb_func
+ 5529              	HAL_I2C_Mem_Write_IT:
+ 5530              	.LVL352:
+ 5531              	.LFB347:
+2649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 5532              		.loc 1 2649 1 is_stmt 1 view -0
+ 5533              		.cfi_startproc
+ 5534              		@ args = 8, pretend = 0, frame = 0
+ 5535              		@ frame_needed = 0, uses_anonymous_args = 0
+2649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 5536              		.loc 1 2649 1 is_stmt 0 view .LVU1908
+ 5537 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 5538              	.LCFI63:
+ 5539              		.cfi_def_cfa_offset 24
+ 5540              		.cfi_offset 4, -24
+ 5541              		.cfi_offset 5, -20
+ 5542              		.cfi_offset 6, -16
+ 5543              		.cfi_offset 7, -12
+ 5544              		.cfi_offset 8, -8
+ 5545              		.cfi_offset 14, -4
+ 5546 0004 82B0     		sub	sp, sp, #8
+ 5547              	.LCFI64:
+ 5548              		.cfi_def_cfa_offset 32
+ 5549 0006 0446     		mov	r4, r0
+ 5550 0008 BDF82480 		ldrh	r8, [sp, #36]
+2650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 5551              		.loc 1 2650 3 is_stmt 1 view .LVU1909
+2651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5552              		.loc 1 2651 3 view .LVU1910
+2654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5553              		.loc 1 2654 3 view .LVU1911
+2656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 5554              		.loc 1 2656 3 view .LVU1912
+2656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 5555              		.loc 1 2656 11 is_stmt 0 view .LVU1913
+ 5556 000c 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 5557              	.LVL353:
+2656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 250
+
+
+ 5558              		.loc 1 2656 11 view .LVU1914
+ 5559 0010 C0B2     		uxtb	r0, r0
+2656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 5560              		.loc 1 2656 6 view .LVU1915
+ 5561 0012 2028     		cmp	r0, #32
+ 5562 0014 58D1     		bne	.L364
+ 5563 0016 0D46     		mov	r5, r1
+ 5564 0018 1746     		mov	r7, r2
+ 5565 001a 1E46     		mov	r6, r3
+2658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5566              		.loc 1 2658 5 is_stmt 1 view .LVU1916
+2658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5567              		.loc 1 2658 8 is_stmt 0 view .LVU1917
+ 5568 001c 089B     		ldr	r3, [sp, #32]
+ 5569              	.LVL354:
+2658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5570              		.loc 1 2658 8 view .LVU1918
+ 5571 001e 002B     		cmp	r3, #0
+ 5572 0020 38D0     		beq	.L359
+2658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5573              		.loc 1 2658 25 discriminator 1 view .LVU1919
+ 5574 0022 B8F1000F 		cmp	r8, #0
+ 5575 0026 35D0     		beq	.L359
+2664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5576              		.loc 1 2664 5 is_stmt 1 view .LVU1920
+2664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5577              		.loc 1 2664 9 is_stmt 0 view .LVU1921
+ 5578 0028 2368     		ldr	r3, [r4]
+ 5579 002a 9B69     		ldr	r3, [r3, #24]
+2664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5580              		.loc 1 2664 8 view .LVU1922
+ 5581 002c 13F4004F 		tst	r3, #32768
+ 5582 0030 4FD1     		bne	.L365
+2670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5583              		.loc 1 2670 5 is_stmt 1 view .LVU1923
+2670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5584              		.loc 1 2670 5 view .LVU1924
+ 5585 0032 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 5586 0036 012B     		cmp	r3, #1
+ 5587 0038 4DD0     		beq	.L366
+2670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5588              		.loc 1 2670 5 discriminator 2 view .LVU1925
+ 5589 003a 0123     		movs	r3, #1
+ 5590 003c 84F84030 		strb	r3, [r4, #64]
+2670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5591              		.loc 1 2670 5 discriminator 2 view .LVU1926
+2673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5592              		.loc 1 2673 5 discriminator 2 view .LVU1927
+2673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5593              		.loc 1 2673 17 is_stmt 0 discriminator 2 view .LVU1928
+ 5594 0040 FFF7FEFF 		bl	HAL_GetTick
+ 5595              	.LVL355:
+2675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 5596              		.loc 1 2675 5 is_stmt 1 discriminator 2 view .LVU1929
+2675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 5597              		.loc 1 2675 23 is_stmt 0 discriminator 2 view .LVU1930
+ 5598 0044 2123     		movs	r3, #33
+ARM GAS  /tmp/ccbUHtu7.s 			page 251
+
+
+ 5599 0046 84F84130 		strb	r3, [r4, #65]
+2676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 5600              		.loc 1 2676 5 is_stmt 1 discriminator 2 view .LVU1931
+2676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 5601              		.loc 1 2676 23 is_stmt 0 discriminator 2 view .LVU1932
+ 5602 004a 4023     		movs	r3, #64
+ 5603 004c 84F84230 		strb	r3, [r4, #66]
+2677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5604              		.loc 1 2677 5 is_stmt 1 discriminator 2 view .LVU1933
+2677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5605              		.loc 1 2677 23 is_stmt 0 discriminator 2 view .LVU1934
+ 5606 0050 0023     		movs	r3, #0
+ 5607 0052 6364     		str	r3, [r4, #68]
+2680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 5608              		.loc 1 2680 5 is_stmt 1 discriminator 2 view .LVU1935
+2680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 5609              		.loc 1 2680 23 is_stmt 0 discriminator 2 view .LVU1936
+ 5610 0054 089B     		ldr	r3, [sp, #32]
+ 5611 0056 6362     		str	r3, [r4, #36]
+2681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 5612              		.loc 1 2681 5 is_stmt 1 discriminator 2 view .LVU1937
+2681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 5613              		.loc 1 2681 23 is_stmt 0 discriminator 2 view .LVU1938
+ 5614 0058 A4F82A80 		strh	r8, [r4, #42]	@ movhi
+2682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 5615              		.loc 1 2682 5 is_stmt 1 discriminator 2 view .LVU1939
+2682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 5616              		.loc 1 2682 23 is_stmt 0 discriminator 2 view .LVU1940
+ 5617 005c 1F4B     		ldr	r3, .L368
+ 5618 005e E362     		str	r3, [r4, #44]
+2683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5619              		.loc 1 2683 5 is_stmt 1 discriminator 2 view .LVU1941
+2683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5620              		.loc 1 2683 23 is_stmt 0 discriminator 2 view .LVU1942
+ 5621 0060 1F4B     		ldr	r3, .L368+4
+ 5622 0062 6363     		str	r3, [r4, #52]
+2685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5623              		.loc 1 2685 5 is_stmt 1 discriminator 2 view .LVU1943
+2685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5624              		.loc 1 2685 13 is_stmt 0 discriminator 2 view .LVU1944
+ 5625 0064 638D     		ldrh	r3, [r4, #42]
+ 5626 0066 9BB2     		uxth	r3, r3
+2685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5627              		.loc 1 2685 8 discriminator 2 view .LVU1945
+ 5628 0068 FF2B     		cmp	r3, #255
+ 5629 006a 18D9     		bls	.L361
+2687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 5630              		.loc 1 2687 7 is_stmt 1 view .LVU1946
+2687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 5631              		.loc 1 2687 22 is_stmt 0 view .LVU1947
+ 5632 006c FF23     		movs	r3, #255
+ 5633 006e 2385     		strh	r3, [r4, #40]	@ movhi
+2688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5634              		.loc 1 2688 7 is_stmt 1 view .LVU1948
+ 5635              	.LVL356:
+2688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5636              		.loc 1 2688 16 is_stmt 0 view .LVU1949
+ARM GAS  /tmp/ccbUHtu7.s 			page 252
+
+
+ 5637 0070 4FF08078 		mov	r8, #16777216
+ 5638              	.LVL357:
+ 5639              	.L362:
+2697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         != HAL_OK)
+ 5640              		.loc 1 2697 5 is_stmt 1 view .LVU1950
+2697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         != HAL_OK)
+ 5641              		.loc 1 2697 9 is_stmt 0 view .LVU1951
+ 5642 0074 0190     		str	r0, [sp, #4]
+ 5643 0076 1923     		movs	r3, #25
+ 5644 0078 0093     		str	r3, [sp]
+ 5645 007a 3346     		mov	r3, r6
+ 5646 007c 3A46     		mov	r2, r7
+ 5647 007e 2946     		mov	r1, r5
+ 5648 0080 2046     		mov	r0, r4
+ 5649              	.LVL358:
+2697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         != HAL_OK)
+ 5650              		.loc 1 2697 9 view .LVU1952
+ 5651 0082 FFF7FEFF 		bl	I2C_RequestMemoryWrite
+ 5652              	.LVL359:
+2697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         != HAL_OK)
+ 5653              		.loc 1 2697 8 view .LVU1953
+ 5654 0086 0646     		mov	r6, r0
+ 5655 0088 70B1     		cbz	r0, .L363
+2701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 5656              		.loc 1 2701 7 is_stmt 1 view .LVU1954
+2701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 5657              		.loc 1 2701 7 view .LVU1955
+ 5658 008a 0023     		movs	r3, #0
+ 5659 008c 84F84030 		strb	r3, [r4, #64]
+2701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 5660              		.loc 1 2701 7 view .LVU1956
+2702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5661              		.loc 1 2702 7 view .LVU1957
+2702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5662              		.loc 1 2702 14 is_stmt 0 view .LVU1958
+ 5663 0090 0126     		movs	r6, #1
+ 5664 0092 1AE0     		b	.L358
+ 5665              	.LVL360:
+ 5666              	.L359:
+2660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 5667              		.loc 1 2660 7 is_stmt 1 view .LVU1959
+2660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 5668              		.loc 1 2660 23 is_stmt 0 view .LVU1960
+ 5669 0094 4FF40073 		mov	r3, #512
+ 5670 0098 6364     		str	r3, [r4, #68]
+2661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5671              		.loc 1 2661 7 is_stmt 1 view .LVU1961
+2661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5672              		.loc 1 2661 15 is_stmt 0 view .LVU1962
+ 5673 009a 0126     		movs	r6, #1
+ 5674 009c 15E0     		b	.L358
+ 5675              	.LVL361:
+ 5676              	.L361:
+2692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 5677              		.loc 1 2692 7 is_stmt 1 view .LVU1963
+2692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 5678              		.loc 1 2692 28 is_stmt 0 view .LVU1964
+ARM GAS  /tmp/ccbUHtu7.s 			page 253
+
+
+ 5679 009e 638D     		ldrh	r3, [r4, #42]
+2692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 5680              		.loc 1 2692 22 view .LVU1965
+ 5681 00a0 2385     		strh	r3, [r4, #40]	@ movhi
+2693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5682              		.loc 1 2693 7 is_stmt 1 view .LVU1966
+ 5683              	.LVL362:
+2693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5684              		.loc 1 2693 16 is_stmt 0 view .LVU1967
+ 5685 00a2 4FF00078 		mov	r8, #33554432
+ 5686 00a6 E5E7     		b	.L362
+ 5687              	.LVL363:
+ 5688              	.L363:
+2706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5689              		.loc 1 2706 5 is_stmt 1 view .LVU1968
+ 5690 00a8 0027     		movs	r7, #0
+ 5691 00aa 0097     		str	r7, [sp]
+ 5692 00ac 4346     		mov	r3, r8
+ 5693 00ae 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 5694 00b2 2946     		mov	r1, r5
+ 5695 00b4 2046     		mov	r0, r4
+ 5696 00b6 FFF7FEFF 		bl	I2C_TransferConfig
+ 5697              	.LVL364:
+2709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5698              		.loc 1 2709 5 view .LVU1969
+2709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5699              		.loc 1 2709 5 view .LVU1970
+ 5700 00ba 84F84070 		strb	r7, [r4, #64]
+2709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5701              		.loc 1 2709 5 view .LVU1971
+2719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5702              		.loc 1 2719 5 view .LVU1972
+ 5703 00be 0121     		movs	r1, #1
+ 5704 00c0 2046     		mov	r0, r4
+ 5705 00c2 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 5706              	.LVL365:
+2721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 5707              		.loc 1 2721 5 view .LVU1973
+2721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 5708              		.loc 1 2721 12 is_stmt 0 view .LVU1974
+ 5709 00c6 00E0     		b	.L358
+ 5710              	.LVL366:
+ 5711              	.L364:
+2725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 5712              		.loc 1 2725 12 view .LVU1975
+ 5713 00c8 0226     		movs	r6, #2
+ 5714              	.LVL367:
+ 5715              	.L358:
+2727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5716              		.loc 1 2727 1 view .LVU1976
+ 5717 00ca 3046     		mov	r0, r6
+ 5718 00cc 02B0     		add	sp, sp, #8
+ 5719              	.LCFI65:
+ 5720              		.cfi_remember_state
+ 5721              		.cfi_def_cfa_offset 24
+ 5722              		@ sp needed
+ 5723 00ce BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ARM GAS  /tmp/ccbUHtu7.s 			page 254
+
+
+ 5724              	.LVL368:
+ 5725              	.L365:
+ 5726              	.LCFI66:
+ 5727              		.cfi_restore_state
+2666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5728              		.loc 1 2666 14 view .LVU1977
+ 5729 00d2 0226     		movs	r6, #2
+ 5730 00d4 F9E7     		b	.L358
+ 5731              	.L366:
+2670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5732              		.loc 1 2670 5 view .LVU1978
+ 5733 00d6 0226     		movs	r6, #2
+ 5734 00d8 F7E7     		b	.L358
+ 5735              	.L369:
+ 5736 00da 00BF     		.align	2
+ 5737              	.L368:
+ 5738 00dc 0000FFFF 		.word	-65536
+ 5739 00e0 00000000 		.word	I2C_Master_ISR_IT
+ 5740              		.cfi_endproc
+ 5741              	.LFE347:
+ 5743              		.section	.text.HAL_I2C_Mem_Read_IT,"ax",%progbits
+ 5744              		.align	1
+ 5745              		.global	HAL_I2C_Mem_Read_IT
+ 5746              		.syntax unified
+ 5747              		.thumb
+ 5748              		.thumb_func
+ 5750              	HAL_I2C_Mem_Read_IT:
+ 5751              	.LVL369:
+ 5752              	.LFB348:
+2743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 5753              		.loc 1 2743 1 is_stmt 1 view -0
+ 5754              		.cfi_startproc
+ 5755              		@ args = 8, pretend = 0, frame = 0
+ 5756              		@ frame_needed = 0, uses_anonymous_args = 0
+2743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 5757              		.loc 1 2743 1 is_stmt 0 view .LVU1980
+ 5758 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 5759              	.LCFI67:
+ 5760              		.cfi_def_cfa_offset 24
+ 5761              		.cfi_offset 4, -24
+ 5762              		.cfi_offset 5, -20
+ 5763              		.cfi_offset 6, -16
+ 5764              		.cfi_offset 7, -12
+ 5765              		.cfi_offset 8, -8
+ 5766              		.cfi_offset 14, -4
+ 5767 0004 82B0     		sub	sp, sp, #8
+ 5768              	.LCFI68:
+ 5769              		.cfi_def_cfa_offset 32
+ 5770 0006 0446     		mov	r4, r0
+ 5771 0008 BDF82480 		ldrh	r8, [sp, #36]
+2744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 5772              		.loc 1 2744 3 is_stmt 1 view .LVU1981
+2745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5773              		.loc 1 2745 3 view .LVU1982
+2748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5774              		.loc 1 2748 3 view .LVU1983
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 255
+
+
+ 5775              		.loc 1 2750 3 view .LVU1984
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 5776              		.loc 1 2750 11 is_stmt 0 view .LVU1985
+ 5777 000c 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 5778              	.LVL370:
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 5779              		.loc 1 2750 11 view .LVU1986
+ 5780 0010 C0B2     		uxtb	r0, r0
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 5781              		.loc 1 2750 6 view .LVU1987
+ 5782 0012 2028     		cmp	r0, #32
+ 5783 0014 59D1     		bne	.L377
+ 5784 0016 0D46     		mov	r5, r1
+ 5785 0018 1746     		mov	r7, r2
+ 5786 001a 1E46     		mov	r6, r3
+2752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5787              		.loc 1 2752 5 is_stmt 1 view .LVU1988
+2752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5788              		.loc 1 2752 8 is_stmt 0 view .LVU1989
+ 5789 001c 089B     		ldr	r3, [sp, #32]
+ 5790              	.LVL371:
+2752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5791              		.loc 1 2752 8 view .LVU1990
+ 5792 001e 002B     		cmp	r3, #0
+ 5793 0020 38D0     		beq	.L372
+2752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5794              		.loc 1 2752 25 discriminator 1 view .LVU1991
+ 5795 0022 B8F1000F 		cmp	r8, #0
+ 5796 0026 35D0     		beq	.L372
+2758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5797              		.loc 1 2758 5 is_stmt 1 view .LVU1992
+2758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5798              		.loc 1 2758 9 is_stmt 0 view .LVU1993
+ 5799 0028 2368     		ldr	r3, [r4]
+ 5800 002a 9B69     		ldr	r3, [r3, #24]
+2758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5801              		.loc 1 2758 8 view .LVU1994
+ 5802 002c 13F4004F 		tst	r3, #32768
+ 5803 0030 50D1     		bne	.L378
+2764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5804              		.loc 1 2764 5 is_stmt 1 view .LVU1995
+2764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5805              		.loc 1 2764 5 view .LVU1996
+ 5806 0032 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 5807 0036 012B     		cmp	r3, #1
+ 5808 0038 4ED0     		beq	.L379
+2764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5809              		.loc 1 2764 5 discriminator 2 view .LVU1997
+ 5810 003a 0123     		movs	r3, #1
+ 5811 003c 84F84030 		strb	r3, [r4, #64]
+2764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5812              		.loc 1 2764 5 discriminator 2 view .LVU1998
+2767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5813              		.loc 1 2767 5 discriminator 2 view .LVU1999
+2767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5814              		.loc 1 2767 17 is_stmt 0 discriminator 2 view .LVU2000
+ 5815 0040 FFF7FEFF 		bl	HAL_GetTick
+ARM GAS  /tmp/ccbUHtu7.s 			page 256
+
+
+ 5816              	.LVL372:
+2769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 5817              		.loc 1 2769 5 is_stmt 1 discriminator 2 view .LVU2001
+2769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 5818              		.loc 1 2769 23 is_stmt 0 discriminator 2 view .LVU2002
+ 5819 0044 2223     		movs	r3, #34
+ 5820 0046 84F84130 		strb	r3, [r4, #65]
+2770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 5821              		.loc 1 2770 5 is_stmt 1 discriminator 2 view .LVU2003
+2770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 5822              		.loc 1 2770 23 is_stmt 0 discriminator 2 view .LVU2004
+ 5823 004a 4023     		movs	r3, #64
+ 5824 004c 84F84230 		strb	r3, [r4, #66]
+2771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5825              		.loc 1 2771 5 is_stmt 1 discriminator 2 view .LVU2005
+2771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5826              		.loc 1 2771 23 is_stmt 0 discriminator 2 view .LVU2006
+ 5827 0050 0023     		movs	r3, #0
+ 5828 0052 6364     		str	r3, [r4, #68]
+2774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 5829              		.loc 1 2774 5 is_stmt 1 discriminator 2 view .LVU2007
+2774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 5830              		.loc 1 2774 23 is_stmt 0 discriminator 2 view .LVU2008
+ 5831 0054 089B     		ldr	r3, [sp, #32]
+ 5832 0056 6362     		str	r3, [r4, #36]
+2775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 5833              		.loc 1 2775 5 is_stmt 1 discriminator 2 view .LVU2009
+2775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 5834              		.loc 1 2775 23 is_stmt 0 discriminator 2 view .LVU2010
+ 5835 0058 A4F82A80 		strh	r8, [r4, #42]	@ movhi
+2776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 5836              		.loc 1 2776 5 is_stmt 1 discriminator 2 view .LVU2011
+2776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 5837              		.loc 1 2776 23 is_stmt 0 discriminator 2 view .LVU2012
+ 5838 005c 1F4B     		ldr	r3, .L381
+ 5839 005e E362     		str	r3, [r4, #44]
+2777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5840              		.loc 1 2777 5 is_stmt 1 discriminator 2 view .LVU2013
+2777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5841              		.loc 1 2777 23 is_stmt 0 discriminator 2 view .LVU2014
+ 5842 0060 1F4B     		ldr	r3, .L381+4
+ 5843 0062 6363     		str	r3, [r4, #52]
+2779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5844              		.loc 1 2779 5 is_stmt 1 discriminator 2 view .LVU2015
+2779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5845              		.loc 1 2779 13 is_stmt 0 discriminator 2 view .LVU2016
+ 5846 0064 638D     		ldrh	r3, [r4, #42]
+ 5847 0066 9BB2     		uxth	r3, r3
+2779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5848              		.loc 1 2779 8 discriminator 2 view .LVU2017
+ 5849 0068 FF2B     		cmp	r3, #255
+ 5850 006a 18D9     		bls	.L374
+2781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 5851              		.loc 1 2781 7 is_stmt 1 view .LVU2018
+2781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 5852              		.loc 1 2781 22 is_stmt 0 view .LVU2019
+ 5853 006c FF23     		movs	r3, #255
+ARM GAS  /tmp/ccbUHtu7.s 			page 257
+
+
+ 5854 006e 2385     		strh	r3, [r4, #40]	@ movhi
+2782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5855              		.loc 1 2782 7 is_stmt 1 view .LVU2020
+ 5856              	.LVL373:
+2782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5857              		.loc 1 2782 16 is_stmt 0 view .LVU2021
+ 5858 0070 4FF08078 		mov	r8, #16777216
+ 5859              	.LVL374:
+ 5860              	.L375:
+2791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5861              		.loc 1 2791 5 is_stmt 1 view .LVU2022
+2791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5862              		.loc 1 2791 9 is_stmt 0 view .LVU2023
+ 5863 0074 0190     		str	r0, [sp, #4]
+ 5864 0076 1923     		movs	r3, #25
+ 5865 0078 0093     		str	r3, [sp]
+ 5866 007a 3346     		mov	r3, r6
+ 5867 007c 3A46     		mov	r2, r7
+ 5868 007e 2946     		mov	r1, r5
+ 5869 0080 2046     		mov	r0, r4
+ 5870              	.LVL375:
+2791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5871              		.loc 1 2791 9 view .LVU2024
+ 5872 0082 FFF7FEFF 		bl	I2C_RequestMemoryRead
+ 5873              	.LVL376:
+2791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 5874              		.loc 1 2791 8 view .LVU2025
+ 5875 0086 0646     		mov	r6, r0
+ 5876 0088 70B1     		cbz	r0, .L376
+2794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 5877              		.loc 1 2794 7 is_stmt 1 view .LVU2026
+2794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 5878              		.loc 1 2794 7 view .LVU2027
+ 5879 008a 0023     		movs	r3, #0
+ 5880 008c 84F84030 		strb	r3, [r4, #64]
+2794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 5881              		.loc 1 2794 7 view .LVU2028
+2795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5882              		.loc 1 2795 7 view .LVU2029
+2795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5883              		.loc 1 2795 14 is_stmt 0 view .LVU2030
+ 5884 0090 0126     		movs	r6, #1
+ 5885 0092 1BE0     		b	.L371
+ 5886              	.LVL377:
+ 5887              	.L372:
+2754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 5888              		.loc 1 2754 7 is_stmt 1 view .LVU2031
+2754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 5889              		.loc 1 2754 23 is_stmt 0 view .LVU2032
+ 5890 0094 4FF40073 		mov	r3, #512
+ 5891 0098 6364     		str	r3, [r4, #68]
+2755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5892              		.loc 1 2755 7 is_stmt 1 view .LVU2033
+2755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5893              		.loc 1 2755 15 is_stmt 0 view .LVU2034
+ 5894 009a 0126     		movs	r6, #1
+ 5895 009c 16E0     		b	.L371
+ARM GAS  /tmp/ccbUHtu7.s 			page 258
+
+
+ 5896              	.LVL378:
+ 5897              	.L374:
+2786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 5898              		.loc 1 2786 7 is_stmt 1 view .LVU2035
+2786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 5899              		.loc 1 2786 28 is_stmt 0 view .LVU2036
+ 5900 009e 638D     		ldrh	r3, [r4, #42]
+2786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 5901              		.loc 1 2786 22 view .LVU2037
+ 5902 00a0 2385     		strh	r3, [r4, #40]	@ movhi
+2787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5903              		.loc 1 2787 7 is_stmt 1 view .LVU2038
+ 5904              	.LVL379:
+2787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5905              		.loc 1 2787 16 is_stmt 0 view .LVU2039
+ 5906 00a2 4FF00078 		mov	r8, #33554432
+ 5907 00a6 E5E7     		b	.L375
+ 5908              	.LVL380:
+ 5909              	.L376:
+2799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5910              		.loc 1 2799 5 is_stmt 1 view .LVU2040
+ 5911 00a8 0E4B     		ldr	r3, .L381+8
+ 5912 00aa 0093     		str	r3, [sp]
+ 5913 00ac 4346     		mov	r3, r8
+ 5914 00ae 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 5915 00b2 2946     		mov	r1, r5
+ 5916 00b4 2046     		mov	r0, r4
+ 5917 00b6 FFF7FEFF 		bl	I2C_TransferConfig
+ 5918              	.LVL381:
+2802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5919              		.loc 1 2802 5 view .LVU2041
+2802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5920              		.loc 1 2802 5 view .LVU2042
+ 5921 00ba 0023     		movs	r3, #0
+ 5922 00bc 84F84030 		strb	r3, [r4, #64]
+2802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5923              		.loc 1 2802 5 view .LVU2043
+2812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5924              		.loc 1 2812 5 view .LVU2044
+ 5925 00c0 0221     		movs	r1, #2
+ 5926 00c2 2046     		mov	r0, r4
+ 5927 00c4 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 5928              	.LVL382:
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 5929              		.loc 1 2814 5 view .LVU2045
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 5930              		.loc 1 2814 12 is_stmt 0 view .LVU2046
+ 5931 00c8 00E0     		b	.L371
+ 5932              	.LVL383:
+ 5933              	.L377:
+2818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 5934              		.loc 1 2818 12 view .LVU2047
+ 5935 00ca 0226     		movs	r6, #2
+ 5936              	.LVL384:
+ 5937              	.L371:
+2820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** /**
+ 5938              		.loc 1 2820 1 view .LVU2048
+ARM GAS  /tmp/ccbUHtu7.s 			page 259
+
+
+ 5939 00cc 3046     		mov	r0, r6
+ 5940 00ce 02B0     		add	sp, sp, #8
+ 5941              	.LCFI69:
+ 5942              		.cfi_remember_state
+ 5943              		.cfi_def_cfa_offset 24
+ 5944              		@ sp needed
+ 5945 00d0 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 5946              	.LVL385:
+ 5947              	.L378:
+ 5948              	.LCFI70:
+ 5949              		.cfi_restore_state
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 5950              		.loc 1 2760 14 view .LVU2049
+ 5951 00d4 0226     		movs	r6, #2
+ 5952 00d6 F9E7     		b	.L371
+ 5953              	.L379:
+2764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5954              		.loc 1 2764 5 view .LVU2050
+ 5955 00d8 0226     		movs	r6, #2
+ 5956 00da F7E7     		b	.L371
+ 5957              	.L382:
+ 5958              		.align	2
+ 5959              	.L381:
+ 5960 00dc 0000FFFF 		.word	-65536
+ 5961 00e0 00000000 		.word	I2C_Master_ISR_IT
+ 5962 00e4 00240080 		.word	-2147474432
+ 5963              		.cfi_endproc
+ 5964              	.LFE348:
+ 5966              		.section	.text.HAL_I2C_Mem_Write_DMA,"ax",%progbits
+ 5967              		.align	1
+ 5968              		.global	HAL_I2C_Mem_Write_DMA
+ 5969              		.syntax unified
+ 5970              		.thumb
+ 5971              		.thumb_func
+ 5973              	HAL_I2C_Mem_Write_DMA:
+ 5974              	.LVL386:
+ 5975              	.LFB349:
+2835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 5976              		.loc 1 2835 1 is_stmt 1 view -0
+ 5977              		.cfi_startproc
+ 5978              		@ args = 8, pretend = 0, frame = 0
+ 5979              		@ frame_needed = 0, uses_anonymous_args = 0
+2835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 5980              		.loc 1 2835 1 is_stmt 0 view .LVU2052
+ 5981 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 5982              	.LCFI71:
+ 5983              		.cfi_def_cfa_offset 24
+ 5984              		.cfi_offset 4, -24
+ 5985              		.cfi_offset 5, -20
+ 5986              		.cfi_offset 6, -16
+ 5987              		.cfi_offset 7, -12
+ 5988              		.cfi_offset 8, -8
+ 5989              		.cfi_offset 14, -4
+ 5990 0004 82B0     		sub	sp, sp, #8
+ 5991              	.LCFI72:
+ 5992              		.cfi_def_cfa_offset 32
+ 5993 0006 0446     		mov	r4, r0
+ARM GAS  /tmp/ccbUHtu7.s 			page 260
+
+
+ 5994 0008 BDF82480 		ldrh	r8, [sp, #36]
+2836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 5995              		.loc 1 2836 3 is_stmt 1 view .LVU2053
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 5996              		.loc 1 2837 3 view .LVU2054
+2838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5997              		.loc 1 2838 3 view .LVU2055
+2841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 5998              		.loc 1 2841 3 view .LVU2056
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 5999              		.loc 1 2843 3 view .LVU2057
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 6000              		.loc 1 2843 11 is_stmt 0 view .LVU2058
+ 6001 000c 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 6002              	.LVL387:
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 6003              		.loc 1 2843 11 view .LVU2059
+ 6004 0010 C0B2     		uxtb	r0, r0
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 6005              		.loc 1 2843 6 view .LVU2060
+ 6006 0012 2028     		cmp	r0, #32
+ 6007 0014 40F09880 		bne	.L393
+ 6008 0018 0D46     		mov	r5, r1
+ 6009 001a 1746     		mov	r7, r2
+ 6010 001c 1E46     		mov	r6, r3
+2845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6011              		.loc 1 2845 5 is_stmt 1 view .LVU2061
+2845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6012              		.loc 1 2845 8 is_stmt 0 view .LVU2062
+ 6013 001e 089B     		ldr	r3, [sp, #32]
+ 6014              	.LVL388:
+2845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6015              		.loc 1 2845 8 view .LVU2063
+ 6016 0020 002B     		cmp	r3, #0
+ 6017 0022 59D0     		beq	.L385
+2845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6018              		.loc 1 2845 25 discriminator 1 view .LVU2064
+ 6019 0024 B8F1000F 		cmp	r8, #0
+ 6020 0028 56D0     		beq	.L385
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6021              		.loc 1 2851 5 is_stmt 1 view .LVU2065
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6022              		.loc 1 2851 9 is_stmt 0 view .LVU2066
+ 6023 002a 2368     		ldr	r3, [r4]
+ 6024 002c 9B69     		ldr	r3, [r3, #24]
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6025              		.loc 1 2851 8 view .LVU2067
+ 6026 002e 13F4004F 		tst	r3, #32768
+ 6027 0032 40F08E80 		bne	.L394
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6028              		.loc 1 2857 5 is_stmt 1 view .LVU2068
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6029              		.loc 1 2857 5 view .LVU2069
+ 6030 0036 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 6031 003a 012B     		cmp	r3, #1
+ 6032 003c 00F08B80 		beq	.L395
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 261
+
+
+ 6033              		.loc 1 2857 5 discriminator 2 view .LVU2070
+ 6034 0040 0123     		movs	r3, #1
+ 6035 0042 84F84030 		strb	r3, [r4, #64]
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6036              		.loc 1 2857 5 discriminator 2 view .LVU2071
+2860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6037              		.loc 1 2860 5 discriminator 2 view .LVU2072
+2860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6038              		.loc 1 2860 17 is_stmt 0 discriminator 2 view .LVU2073
+ 6039 0046 FFF7FEFF 		bl	HAL_GetTick
+ 6040              	.LVL389:
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 6041              		.loc 1 2862 5 is_stmt 1 discriminator 2 view .LVU2074
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 6042              		.loc 1 2862 23 is_stmt 0 discriminator 2 view .LVU2075
+ 6043 004a 2123     		movs	r3, #33
+ 6044 004c 84F84130 		strb	r3, [r4, #65]
+2863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 6045              		.loc 1 2863 5 is_stmt 1 discriminator 2 view .LVU2076
+2863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 6046              		.loc 1 2863 23 is_stmt 0 discriminator 2 view .LVU2077
+ 6047 0050 4023     		movs	r3, #64
+ 6048 0052 84F84230 		strb	r3, [r4, #66]
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6049              		.loc 1 2864 5 is_stmt 1 discriminator 2 view .LVU2078
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6050              		.loc 1 2864 23 is_stmt 0 discriminator 2 view .LVU2079
+ 6051 0056 0023     		movs	r3, #0
+ 6052 0058 6364     		str	r3, [r4, #68]
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 6053              		.loc 1 2867 5 is_stmt 1 discriminator 2 view .LVU2080
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 6054              		.loc 1 2867 23 is_stmt 0 discriminator 2 view .LVU2081
+ 6055 005a 089B     		ldr	r3, [sp, #32]
+ 6056 005c 6362     		str	r3, [r4, #36]
+2868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 6057              		.loc 1 2868 5 is_stmt 1 discriminator 2 view .LVU2082
+2868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 6058              		.loc 1 2868 23 is_stmt 0 discriminator 2 view .LVU2083
+ 6059 005e A4F82A80 		strh	r8, [r4, #42]	@ movhi
+2869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 6060              		.loc 1 2869 5 is_stmt 1 discriminator 2 view .LVU2084
+2869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 6061              		.loc 1 2869 23 is_stmt 0 discriminator 2 view .LVU2085
+ 6062 0062 3E4B     		ldr	r3, .L400
+ 6063 0064 E362     		str	r3, [r4, #44]
+2870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6064              		.loc 1 2870 5 is_stmt 1 discriminator 2 view .LVU2086
+2870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6065              		.loc 1 2870 23 is_stmt 0 discriminator 2 view .LVU2087
+ 6066 0066 3E4B     		ldr	r3, .L400+4
+ 6067 0068 6363     		str	r3, [r4, #52]
+2872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6068              		.loc 1 2872 5 is_stmt 1 discriminator 2 view .LVU2088
+2872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6069              		.loc 1 2872 13 is_stmt 0 discriminator 2 view .LVU2089
+ 6070 006a 638D     		ldrh	r3, [r4, #42]
+ARM GAS  /tmp/ccbUHtu7.s 			page 262
+
+
+ 6071 006c 9BB2     		uxth	r3, r3
+2872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6072              		.loc 1 2872 8 discriminator 2 view .LVU2090
+ 6073 006e FF2B     		cmp	r3, #255
+ 6074 0070 37D9     		bls	.L387
+2874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 6075              		.loc 1 2874 7 is_stmt 1 view .LVU2091
+2874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 6076              		.loc 1 2874 22 is_stmt 0 view .LVU2092
+ 6077 0072 FF23     		movs	r3, #255
+ 6078 0074 2385     		strh	r3, [r4, #40]	@ movhi
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6079              		.loc 1 2875 7 is_stmt 1 view .LVU2093
+ 6080              	.LVL390:
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6081              		.loc 1 2875 16 is_stmt 0 view .LVU2094
+ 6082 0076 4FF08078 		mov	r8, #16777216
+ 6083              	.LVL391:
+ 6084              	.L388:
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         != HAL_OK)
+ 6085              		.loc 1 2884 5 is_stmt 1 view .LVU2095
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         != HAL_OK)
+ 6086              		.loc 1 2884 9 is_stmt 0 view .LVU2096
+ 6087 007a 0190     		str	r0, [sp, #4]
+ 6088 007c 1923     		movs	r3, #25
+ 6089 007e 0093     		str	r3, [sp]
+ 6090 0080 3346     		mov	r3, r6
+ 6091 0082 3A46     		mov	r2, r7
+ 6092 0084 2946     		mov	r1, r5
+ 6093 0086 2046     		mov	r0, r4
+ 6094              	.LVL392:
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         != HAL_OK)
+ 6095              		.loc 1 2884 9 view .LVU2097
+ 6096 0088 FFF7FEFF 		bl	I2C_RequestMemoryWrite
+ 6097              	.LVL393:
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         != HAL_OK)
+ 6098              		.loc 1 2884 8 view .LVU2098
+ 6099 008c 0028     		cmp	r0, #0
+ 6100 008e 2DD1     		bne	.L398
+2893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6101              		.loc 1 2893 5 is_stmt 1 view .LVU2099
+2893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6102              		.loc 1 2893 13 is_stmt 0 view .LVU2100
+ 6103 0090 A36B     		ldr	r3, [r4, #56]
+2893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6104              		.loc 1 2893 8 view .LVU2101
+ 6105 0092 002B     		cmp	r3, #0
+ 6106 0094 2FD0     		beq	.L390
+2896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6107              		.loc 1 2896 7 is_stmt 1 view .LVU2102
+2896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6108              		.loc 1 2896 38 is_stmt 0 view .LVU2103
+ 6109 0096 334A     		ldr	r2, .L400+8
+ 6110 0098 DA62     		str	r2, [r3, #44]
+2899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6111              		.loc 1 2899 7 is_stmt 1 view .LVU2104
+2899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 263
+
+
+ 6112              		.loc 1 2899 11 is_stmt 0 view .LVU2105
+ 6113 009a A36B     		ldr	r3, [r4, #56]
+2899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6114              		.loc 1 2899 39 view .LVU2106
+ 6115 009c 324A     		ldr	r2, .L400+12
+ 6116 009e 5A63     		str	r2, [r3, #52]
+2902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 6117              		.loc 1 2902 7 is_stmt 1 view .LVU2107
+2902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 6118              		.loc 1 2902 11 is_stmt 0 view .LVU2108
+ 6119 00a0 A26B     		ldr	r2, [r4, #56]
+2902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 6120              		.loc 1 2902 42 view .LVU2109
+ 6121 00a2 0023     		movs	r3, #0
+ 6122 00a4 1363     		str	r3, [r2, #48]
+2903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6123              		.loc 1 2903 7 is_stmt 1 view .LVU2110
+2903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6124              		.loc 1 2903 11 is_stmt 0 view .LVU2111
+ 6125 00a6 A26B     		ldr	r2, [r4, #56]
+2903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6126              		.loc 1 2903 39 view .LVU2112
+ 6127 00a8 9363     		str	r3, [r2, #56]
+2906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 6128              		.loc 1 2906 7 is_stmt 1 view .LVU2113
+2906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 6129              		.loc 1 2906 86 is_stmt 0 view .LVU2114
+ 6130 00aa 2268     		ldr	r2, [r4]
+2906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 6131              		.loc 1 2906 23 view .LVU2115
+ 6132 00ac 238D     		ldrh	r3, [r4, #40]
+ 6133 00ae 2832     		adds	r2, r2, #40
+ 6134 00b0 0899     		ldr	r1, [sp, #32]
+ 6135 00b2 A06B     		ldr	r0, [r4, #56]
+ 6136 00b4 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 6137              	.LVL394:
+2924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6138              		.loc 1 2924 5 is_stmt 1 view .LVU2116
+2924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6139              		.loc 1 2924 8 is_stmt 0 view .LVU2117
+ 6140 00b8 0646     		mov	r6, r0
+ 6141 00ba 50B3     		cbz	r0, .L399
+2948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6142              		.loc 1 2948 7 is_stmt 1 view .LVU2118
+2948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6143              		.loc 1 2948 23 is_stmt 0 view .LVU2119
+ 6144 00bc 2023     		movs	r3, #32
+ 6145 00be 84F84130 		strb	r3, [r4, #65]
+2949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6146              		.loc 1 2949 7 is_stmt 1 view .LVU2120
+2949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6147              		.loc 1 2949 23 is_stmt 0 view .LVU2121
+ 6148 00c2 0022     		movs	r2, #0
+ 6149 00c4 84F84220 		strb	r2, [r4, #66]
+2952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6150              		.loc 1 2952 7 is_stmt 1 view .LVU2122
+2952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 264
+
+
+ 6151              		.loc 1 2952 11 is_stmt 0 view .LVU2123
+ 6152 00c8 636C     		ldr	r3, [r4, #68]
+2952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6153              		.loc 1 2952 23 view .LVU2124
+ 6154 00ca 43F01003 		orr	r3, r3, #16
+ 6155 00ce 6364     		str	r3, [r4, #68]
+2955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6156              		.loc 1 2955 7 is_stmt 1 view .LVU2125
+2955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6157              		.loc 1 2955 7 view .LVU2126
+ 6158 00d0 84F84020 		strb	r2, [r4, #64]
+2955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6159              		.loc 1 2955 7 view .LVU2127
+2957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6160              		.loc 1 2957 7 view .LVU2128
+2957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6161              		.loc 1 2957 14 is_stmt 0 view .LVU2129
+ 6162 00d4 0126     		movs	r6, #1
+ 6163 00d6 38E0     		b	.L384
+ 6164              	.LVL395:
+ 6165              	.L385:
+2847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 6166              		.loc 1 2847 7 is_stmt 1 view .LVU2130
+2847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 6167              		.loc 1 2847 23 is_stmt 0 view .LVU2131
+ 6168 00d8 4FF40073 		mov	r3, #512
+ 6169 00dc 6364     		str	r3, [r4, #68]
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6170              		.loc 1 2848 7 is_stmt 1 view .LVU2132
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6171              		.loc 1 2848 15 is_stmt 0 view .LVU2133
+ 6172 00de 0126     		movs	r6, #1
+ 6173 00e0 33E0     		b	.L384
+ 6174              	.LVL396:
+ 6175              	.L387:
+2879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 6176              		.loc 1 2879 7 is_stmt 1 view .LVU2134
+2879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 6177              		.loc 1 2879 28 is_stmt 0 view .LVU2135
+ 6178 00e2 638D     		ldrh	r3, [r4, #42]
+2879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 6179              		.loc 1 2879 22 view .LVU2136
+ 6180 00e4 2385     		strh	r3, [r4, #40]	@ movhi
+2880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6181              		.loc 1 2880 7 is_stmt 1 view .LVU2137
+ 6182              	.LVL397:
+2880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6183              		.loc 1 2880 16 is_stmt 0 view .LVU2138
+ 6184 00e6 4FF00078 		mov	r8, #33554432
+ 6185 00ea C6E7     		b	.L388
+ 6186              	.LVL398:
+ 6187              	.L398:
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 6188              		.loc 1 2888 7 is_stmt 1 view .LVU2139
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 6189              		.loc 1 2888 7 view .LVU2140
+ 6190 00ec 0023     		movs	r3, #0
+ARM GAS  /tmp/ccbUHtu7.s 			page 265
+
+
+ 6191 00ee 84F84030 		strb	r3, [r4, #64]
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 6192              		.loc 1 2888 7 view .LVU2141
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6193              		.loc 1 2889 7 view .LVU2142
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6194              		.loc 1 2889 14 is_stmt 0 view .LVU2143
+ 6195 00f2 0126     		movs	r6, #1
+ 6196 00f4 29E0     		b	.L384
+ 6197              	.L390:
+2912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6198              		.loc 1 2912 7 is_stmt 1 view .LVU2144
+2912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6199              		.loc 1 2912 23 is_stmt 0 view .LVU2145
+ 6200 00f6 2023     		movs	r3, #32
+ 6201 00f8 84F84130 		strb	r3, [r4, #65]
+2913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6202              		.loc 1 2913 7 is_stmt 1 view .LVU2146
+2913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6203              		.loc 1 2913 23 is_stmt 0 view .LVU2147
+ 6204 00fc 0022     		movs	r2, #0
+ 6205 00fe 84F84220 		strb	r2, [r4, #66]
+2916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6206              		.loc 1 2916 7 is_stmt 1 view .LVU2148
+2916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6207              		.loc 1 2916 11 is_stmt 0 view .LVU2149
+ 6208 0102 636C     		ldr	r3, [r4, #68]
+2916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6209              		.loc 1 2916 23 view .LVU2150
+ 6210 0104 43F08003 		orr	r3, r3, #128
+ 6211 0108 6364     		str	r3, [r4, #68]
+2919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6212              		.loc 1 2919 7 is_stmt 1 view .LVU2151
+2919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6213              		.loc 1 2919 7 view .LVU2152
+ 6214 010a 84F84020 		strb	r2, [r4, #64]
+2919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6215              		.loc 1 2919 7 view .LVU2153
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6216              		.loc 1 2921 7 view .LVU2154
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6217              		.loc 1 2921 14 is_stmt 0 view .LVU2155
+ 6218 010e 0126     		movs	r6, #1
+ 6219 0110 1BE0     		b	.L384
+ 6220              	.LVL399:
+ 6221              	.L399:
+2928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6222              		.loc 1 2928 7 is_stmt 1 view .LVU2156
+ 6223 0112 0027     		movs	r7, #0
+ 6224 0114 0097     		str	r7, [sp]
+ 6225 0116 4346     		mov	r3, r8
+ 6226 0118 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 6227 011c 2946     		mov	r1, r5
+ 6228 011e 2046     		mov	r0, r4
+ 6229              	.LVL400:
+2928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6230              		.loc 1 2928 7 is_stmt 0 view .LVU2157
+ARM GAS  /tmp/ccbUHtu7.s 			page 266
+
+
+ 6231 0120 FFF7FEFF 		bl	I2C_TransferConfig
+ 6232              	.LVL401:
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6233              		.loc 1 2931 7 is_stmt 1 view .LVU2158
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6234              		.loc 1 2931 11 is_stmt 0 view .LVU2159
+ 6235 0124 638D     		ldrh	r3, [r4, #42]
+ 6236 0126 9BB2     		uxth	r3, r3
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6237              		.loc 1 2931 30 view .LVU2160
+ 6238 0128 228D     		ldrh	r2, [r4, #40]
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6239              		.loc 1 2931 23 view .LVU2161
+ 6240 012a 9B1A     		subs	r3, r3, r2
+ 6241 012c 9BB2     		uxth	r3, r3
+ 6242 012e 6385     		strh	r3, [r4, #42]	@ movhi
+2934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6243              		.loc 1 2934 7 is_stmt 1 view .LVU2162
+2934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6244              		.loc 1 2934 7 view .LVU2163
+ 6245 0130 84F84070 		strb	r7, [r4, #64]
+2934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6246              		.loc 1 2934 7 view .LVU2164
+2940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6247              		.loc 1 2940 7 view .LVU2165
+ 6248 0134 1021     		movs	r1, #16
+ 6249 0136 2046     		mov	r0, r4
+ 6250 0138 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 6251              	.LVL402:
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6252              		.loc 1 2943 7 view .LVU2166
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6253              		.loc 1 2943 11 is_stmt 0 view .LVU2167
+ 6254 013c 2268     		ldr	r2, [r4]
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6255              		.loc 1 2943 21 view .LVU2168
+ 6256 013e 1368     		ldr	r3, [r2]
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6257              		.loc 1 2943 27 view .LVU2169
+ 6258 0140 43F48043 		orr	r3, r3, #16384
+ 6259 0144 1360     		str	r3, [r2]
+2960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 6260              		.loc 1 2960 5 is_stmt 1 view .LVU2170
+2960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 6261              		.loc 1 2960 12 is_stmt 0 view .LVU2171
+ 6262 0146 00E0     		b	.L384
+ 6263              	.LVL403:
+ 6264              	.L393:
+2964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 6265              		.loc 1 2964 12 view .LVU2172
+ 6266 0148 0226     		movs	r6, #2
+ 6267              	.LVL404:
+ 6268              	.L384:
+2966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6269              		.loc 1 2966 1 view .LVU2173
+ 6270 014a 3046     		mov	r0, r6
+ 6271 014c 02B0     		add	sp, sp, #8
+ARM GAS  /tmp/ccbUHtu7.s 			page 267
+
+
+ 6272              	.LCFI73:
+ 6273              		.cfi_remember_state
+ 6274              		.cfi_def_cfa_offset 24
+ 6275              		@ sp needed
+ 6276 014e BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 6277              	.LVL405:
+ 6278              	.L394:
+ 6279              	.LCFI74:
+ 6280              		.cfi_restore_state
+2853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6281              		.loc 1 2853 14 view .LVU2174
+ 6282 0152 0226     		movs	r6, #2
+ 6283 0154 F9E7     		b	.L384
+ 6284              	.L395:
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6285              		.loc 1 2857 5 view .LVU2175
+ 6286 0156 0226     		movs	r6, #2
+ 6287 0158 F7E7     		b	.L384
+ 6288              	.L401:
+ 6289 015a 00BF     		.align	2
+ 6290              	.L400:
+ 6291 015c 0000FFFF 		.word	-65536
+ 6292 0160 00000000 		.word	I2C_Master_ISR_DMA
+ 6293 0164 00000000 		.word	I2C_DMAMasterTransmitCplt
+ 6294 0168 00000000 		.word	I2C_DMAError
+ 6295              		.cfi_endproc
+ 6296              	.LFE349:
+ 6298              		.section	.text.HAL_I2C_Mem_Read_DMA,"ax",%progbits
+ 6299              		.align	1
+ 6300              		.global	HAL_I2C_Mem_Read_DMA
+ 6301              		.syntax unified
+ 6302              		.thumb
+ 6303              		.thumb_func
+ 6305              	HAL_I2C_Mem_Read_DMA:
+ 6306              	.LVL406:
+ 6307              	.LFB350:
+2982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 6308              		.loc 1 2982 1 is_stmt 1 view -0
+ 6309              		.cfi_startproc
+ 6310              		@ args = 8, pretend = 0, frame = 0
+ 6311              		@ frame_needed = 0, uses_anonymous_args = 0
+2982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 6312              		.loc 1 2982 1 is_stmt 0 view .LVU2177
+ 6313 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 6314              	.LCFI75:
+ 6315              		.cfi_def_cfa_offset 24
+ 6316              		.cfi_offset 4, -24
+ 6317              		.cfi_offset 5, -20
+ 6318              		.cfi_offset 6, -16
+ 6319              		.cfi_offset 7, -12
+ 6320              		.cfi_offset 8, -8
+ 6321              		.cfi_offset 14, -4
+ 6322 0004 82B0     		sub	sp, sp, #8
+ 6323              	.LCFI76:
+ 6324              		.cfi_def_cfa_offset 32
+ 6325 0006 0446     		mov	r4, r0
+ 6326 0008 BDF82480 		ldrh	r8, [sp, #36]
+ARM GAS  /tmp/ccbUHtu7.s 			page 268
+
+
+2983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 6327              		.loc 1 2983 3 is_stmt 1 view .LVU2178
+2984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 6328              		.loc 1 2984 3 view .LVU2179
+2985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6329              		.loc 1 2985 3 view .LVU2180
+2988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6330              		.loc 1 2988 3 view .LVU2181
+2990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 6331              		.loc 1 2990 3 view .LVU2182
+2990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 6332              		.loc 1 2990 11 is_stmt 0 view .LVU2183
+ 6333 000c 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 6334              	.LVL407:
+2990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 6335              		.loc 1 2990 11 view .LVU2184
+ 6336 0010 C0B2     		uxtb	r0, r0
+2990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 6337              		.loc 1 2990 6 view .LVU2185
+ 6338 0012 2028     		cmp	r0, #32
+ 6339 0014 40F09980 		bne	.L412
+ 6340 0018 0D46     		mov	r5, r1
+ 6341 001a 1746     		mov	r7, r2
+ 6342 001c 1E46     		mov	r6, r3
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6343              		.loc 1 2992 5 is_stmt 1 view .LVU2186
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6344              		.loc 1 2992 8 is_stmt 0 view .LVU2187
+ 6345 001e 089B     		ldr	r3, [sp, #32]
+ 6346              	.LVL408:
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6347              		.loc 1 2992 8 view .LVU2188
+ 6348 0020 002B     		cmp	r3, #0
+ 6349 0022 59D0     		beq	.L404
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6350              		.loc 1 2992 25 discriminator 1 view .LVU2189
+ 6351 0024 B8F1000F 		cmp	r8, #0
+ 6352 0028 56D0     		beq	.L404
+2998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6353              		.loc 1 2998 5 is_stmt 1 view .LVU2190
+2998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6354              		.loc 1 2998 9 is_stmt 0 view .LVU2191
+ 6355 002a 2368     		ldr	r3, [r4]
+ 6356 002c 9B69     		ldr	r3, [r3, #24]
+2998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6357              		.loc 1 2998 8 view .LVU2192
+ 6358 002e 13F4004F 		tst	r3, #32768
+ 6359 0032 40F08F80 		bne	.L413
+3004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6360              		.loc 1 3004 5 is_stmt 1 view .LVU2193
+3004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6361              		.loc 1 3004 5 view .LVU2194
+ 6362 0036 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 6363 003a 012B     		cmp	r3, #1
+ 6364 003c 00F08C80 		beq	.L414
+3004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6365              		.loc 1 3004 5 discriminator 2 view .LVU2195
+ARM GAS  /tmp/ccbUHtu7.s 			page 269
+
+
+ 6366 0040 0123     		movs	r3, #1
+ 6367 0042 84F84030 		strb	r3, [r4, #64]
+3004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6368              		.loc 1 3004 5 discriminator 2 view .LVU2196
+3007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6369              		.loc 1 3007 5 discriminator 2 view .LVU2197
+3007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6370              		.loc 1 3007 17 is_stmt 0 discriminator 2 view .LVU2198
+ 6371 0046 FFF7FEFF 		bl	HAL_GetTick
+ 6372              	.LVL409:
+3009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 6373              		.loc 1 3009 5 is_stmt 1 discriminator 2 view .LVU2199
+3009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 6374              		.loc 1 3009 23 is_stmt 0 discriminator 2 view .LVU2200
+ 6375 004a 2223     		movs	r3, #34
+ 6376 004c 84F84130 		strb	r3, [r4, #65]
+3010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 6377              		.loc 1 3010 5 is_stmt 1 discriminator 2 view .LVU2201
+3010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 6378              		.loc 1 3010 23 is_stmt 0 discriminator 2 view .LVU2202
+ 6379 0050 4023     		movs	r3, #64
+ 6380 0052 84F84230 		strb	r3, [r4, #66]
+3011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6381              		.loc 1 3011 5 is_stmt 1 discriminator 2 view .LVU2203
+3011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6382              		.loc 1 3011 23 is_stmt 0 discriminator 2 view .LVU2204
+ 6383 0056 0023     		movs	r3, #0
+ 6384 0058 6364     		str	r3, [r4, #68]
+3014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 6385              		.loc 1 3014 5 is_stmt 1 discriminator 2 view .LVU2205
+3014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 6386              		.loc 1 3014 23 is_stmt 0 discriminator 2 view .LVU2206
+ 6387 005a 089B     		ldr	r3, [sp, #32]
+ 6388 005c 6362     		str	r3, [r4, #36]
+3015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 6389              		.loc 1 3015 5 is_stmt 1 discriminator 2 view .LVU2207
+3015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 6390              		.loc 1 3015 23 is_stmt 0 discriminator 2 view .LVU2208
+ 6391 005e A4F82A80 		strh	r8, [r4, #42]	@ movhi
+3016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 6392              		.loc 1 3016 5 is_stmt 1 discriminator 2 view .LVU2209
+3016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 6393              		.loc 1 3016 23 is_stmt 0 discriminator 2 view .LVU2210
+ 6394 0062 3E4B     		ldr	r3, .L419
+ 6395 0064 E362     		str	r3, [r4, #44]
+3017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6396              		.loc 1 3017 5 is_stmt 1 discriminator 2 view .LVU2211
+3017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6397              		.loc 1 3017 23 is_stmt 0 discriminator 2 view .LVU2212
+ 6398 0066 3E4B     		ldr	r3, .L419+4
+ 6399 0068 6363     		str	r3, [r4, #52]
+3019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6400              		.loc 1 3019 5 is_stmt 1 discriminator 2 view .LVU2213
+3019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6401              		.loc 1 3019 13 is_stmt 0 discriminator 2 view .LVU2214
+ 6402 006a 638D     		ldrh	r3, [r4, #42]
+ 6403 006c 9BB2     		uxth	r3, r3
+ARM GAS  /tmp/ccbUHtu7.s 			page 270
+
+
+3019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6404              		.loc 1 3019 8 discriminator 2 view .LVU2215
+ 6405 006e FF2B     		cmp	r3, #255
+ 6406 0070 37D9     		bls	.L406
+3021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 6407              		.loc 1 3021 7 is_stmt 1 view .LVU2216
+3021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 6408              		.loc 1 3021 22 is_stmt 0 view .LVU2217
+ 6409 0072 FF23     		movs	r3, #255
+ 6410 0074 2385     		strh	r3, [r4, #40]	@ movhi
+3022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6411              		.loc 1 3022 7 is_stmt 1 view .LVU2218
+ 6412              	.LVL410:
+3022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6413              		.loc 1 3022 16 is_stmt 0 view .LVU2219
+ 6414 0076 4FF08078 		mov	r8, #16777216
+ 6415              	.LVL411:
+ 6416              	.L407:
+3031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6417              		.loc 1 3031 5 is_stmt 1 view .LVU2220
+3031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6418              		.loc 1 3031 9 is_stmt 0 view .LVU2221
+ 6419 007a 0190     		str	r0, [sp, #4]
+ 6420 007c 1923     		movs	r3, #25
+ 6421 007e 0093     		str	r3, [sp]
+ 6422 0080 3346     		mov	r3, r6
+ 6423 0082 3A46     		mov	r2, r7
+ 6424 0084 2946     		mov	r1, r5
+ 6425 0086 2046     		mov	r0, r4
+ 6426              	.LVL412:
+3031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6427              		.loc 1 3031 9 view .LVU2222
+ 6428 0088 FFF7FEFF 		bl	I2C_RequestMemoryRead
+ 6429              	.LVL413:
+3031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6430              		.loc 1 3031 8 view .LVU2223
+ 6431 008c 0028     		cmp	r0, #0
+ 6432 008e 2DD1     		bne	.L417
+3038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6433              		.loc 1 3038 5 is_stmt 1 view .LVU2224
+3038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6434              		.loc 1 3038 13 is_stmt 0 view .LVU2225
+ 6435 0090 E36B     		ldr	r3, [r4, #60]
+3038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6436              		.loc 1 3038 8 view .LVU2226
+ 6437 0092 002B     		cmp	r3, #0
+ 6438 0094 2FD0     		beq	.L409
+3041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6439              		.loc 1 3041 7 is_stmt 1 view .LVU2227
+3041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6440              		.loc 1 3041 38 is_stmt 0 view .LVU2228
+ 6441 0096 334A     		ldr	r2, .L419+8
+ 6442 0098 DA62     		str	r2, [r3, #44]
+3044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6443              		.loc 1 3044 7 is_stmt 1 view .LVU2229
+3044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6444              		.loc 1 3044 11 is_stmt 0 view .LVU2230
+ARM GAS  /tmp/ccbUHtu7.s 			page 271
+
+
+ 6445 009a E36B     		ldr	r3, [r4, #60]
+3044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6446              		.loc 1 3044 39 view .LVU2231
+ 6447 009c 324A     		ldr	r2, .L419+12
+ 6448 009e 5A63     		str	r2, [r3, #52]
+3047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 6449              		.loc 1 3047 7 is_stmt 1 view .LVU2232
+3047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 6450              		.loc 1 3047 11 is_stmt 0 view .LVU2233
+ 6451 00a0 E26B     		ldr	r2, [r4, #60]
+3047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 6452              		.loc 1 3047 42 view .LVU2234
+ 6453 00a2 0023     		movs	r3, #0
+ 6454 00a4 1363     		str	r3, [r2, #48]
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6455              		.loc 1 3048 7 is_stmt 1 view .LVU2235
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6456              		.loc 1 3048 11 is_stmt 0 view .LVU2236
+ 6457 00a6 E26B     		ldr	r2, [r4, #60]
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6458              		.loc 1 3048 39 view .LVU2237
+ 6459 00a8 9363     		str	r3, [r2, #56]
+3051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 6460              		.loc 1 3051 7 is_stmt 1 view .LVU2238
+3051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 6461              		.loc 1 3051 69 is_stmt 0 view .LVU2239
+ 6462 00aa 2168     		ldr	r1, [r4]
+3051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 6463              		.loc 1 3051 23 view .LVU2240
+ 6464 00ac 238D     		ldrh	r3, [r4, #40]
+ 6465 00ae 089A     		ldr	r2, [sp, #32]
+ 6466 00b0 2431     		adds	r1, r1, #36
+ 6467 00b2 E06B     		ldr	r0, [r4, #60]
+ 6468 00b4 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 6469              	.LVL414:
+3069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6470              		.loc 1 3069 5 is_stmt 1 view .LVU2241
+3069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6471              		.loc 1 3069 8 is_stmt 0 view .LVU2242
+ 6472 00b8 0646     		mov	r6, r0
+ 6473 00ba 50B3     		cbz	r0, .L418
+3092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6474              		.loc 1 3092 7 is_stmt 1 view .LVU2243
+3092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6475              		.loc 1 3092 23 is_stmt 0 view .LVU2244
+ 6476 00bc 2023     		movs	r3, #32
+ 6477 00be 84F84130 		strb	r3, [r4, #65]
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6478              		.loc 1 3093 7 is_stmt 1 view .LVU2245
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6479              		.loc 1 3093 23 is_stmt 0 view .LVU2246
+ 6480 00c2 0022     		movs	r2, #0
+ 6481 00c4 84F84220 		strb	r2, [r4, #66]
+3096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6482              		.loc 1 3096 7 is_stmt 1 view .LVU2247
+3096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6483              		.loc 1 3096 11 is_stmt 0 view .LVU2248
+ARM GAS  /tmp/ccbUHtu7.s 			page 272
+
+
+ 6484 00c8 636C     		ldr	r3, [r4, #68]
+3096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6485              		.loc 1 3096 23 view .LVU2249
+ 6486 00ca 43F01003 		orr	r3, r3, #16
+ 6487 00ce 6364     		str	r3, [r4, #68]
+3099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6488              		.loc 1 3099 7 is_stmt 1 view .LVU2250
+3099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6489              		.loc 1 3099 7 view .LVU2251
+ 6490 00d0 84F84020 		strb	r2, [r4, #64]
+3099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6491              		.loc 1 3099 7 view .LVU2252
+3101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6492              		.loc 1 3101 7 view .LVU2253
+3101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6493              		.loc 1 3101 14 is_stmt 0 view .LVU2254
+ 6494 00d4 0126     		movs	r6, #1
+ 6495 00d6 39E0     		b	.L403
+ 6496              	.LVL415:
+ 6497              	.L404:
+2994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 6498              		.loc 1 2994 7 is_stmt 1 view .LVU2255
+2994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 6499              		.loc 1 2994 23 is_stmt 0 view .LVU2256
+ 6500 00d8 4FF40073 		mov	r3, #512
+ 6501 00dc 6364     		str	r3, [r4, #68]
+2995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6502              		.loc 1 2995 7 is_stmt 1 view .LVU2257
+2995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6503              		.loc 1 2995 15 is_stmt 0 view .LVU2258
+ 6504 00de 0126     		movs	r6, #1
+ 6505 00e0 34E0     		b	.L403
+ 6506              	.LVL416:
+ 6507              	.L406:
+3026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 6508              		.loc 1 3026 7 is_stmt 1 view .LVU2259
+3026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 6509              		.loc 1 3026 28 is_stmt 0 view .LVU2260
+ 6510 00e2 638D     		ldrh	r3, [r4, #42]
+3026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 6511              		.loc 1 3026 22 view .LVU2261
+ 6512 00e4 2385     		strh	r3, [r4, #40]	@ movhi
+3027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6513              		.loc 1 3027 7 is_stmt 1 view .LVU2262
+ 6514              	.LVL417:
+3027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6515              		.loc 1 3027 16 is_stmt 0 view .LVU2263
+ 6516 00e6 4FF00078 		mov	r8, #33554432
+ 6517 00ea C6E7     		b	.L407
+ 6518              	.LVL418:
+ 6519              	.L417:
+3034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 6520              		.loc 1 3034 7 is_stmt 1 view .LVU2264
+3034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 6521              		.loc 1 3034 7 view .LVU2265
+ 6522 00ec 0023     		movs	r3, #0
+ 6523 00ee 84F84030 		strb	r3, [r4, #64]
+ARM GAS  /tmp/ccbUHtu7.s 			page 273
+
+
+3034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return HAL_ERROR;
+ 6524              		.loc 1 3034 7 view .LVU2266
+3035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6525              		.loc 1 3035 7 view .LVU2267
+3035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6526              		.loc 1 3035 14 is_stmt 0 view .LVU2268
+ 6527 00f2 0126     		movs	r6, #1
+ 6528 00f4 2AE0     		b	.L403
+ 6529              	.L409:
+3057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6530              		.loc 1 3057 7 is_stmt 1 view .LVU2269
+3057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6531              		.loc 1 3057 23 is_stmt 0 view .LVU2270
+ 6532 00f6 2023     		movs	r3, #32
+ 6533 00f8 84F84130 		strb	r3, [r4, #65]
+3058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6534              		.loc 1 3058 7 is_stmt 1 view .LVU2271
+3058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6535              		.loc 1 3058 23 is_stmt 0 view .LVU2272
+ 6536 00fc 0022     		movs	r2, #0
+ 6537 00fe 84F84220 		strb	r2, [r4, #66]
+3061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6538              		.loc 1 3061 7 is_stmt 1 view .LVU2273
+3061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6539              		.loc 1 3061 11 is_stmt 0 view .LVU2274
+ 6540 0102 636C     		ldr	r3, [r4, #68]
+3061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6541              		.loc 1 3061 23 view .LVU2275
+ 6542 0104 43F08003 		orr	r3, r3, #128
+ 6543 0108 6364     		str	r3, [r4, #68]
+3064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6544              		.loc 1 3064 7 is_stmt 1 view .LVU2276
+3064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6545              		.loc 1 3064 7 view .LVU2277
+ 6546 010a 84F84020 		strb	r2, [r4, #64]
+3064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6547              		.loc 1 3064 7 view .LVU2278
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6548              		.loc 1 3066 7 view .LVU2279
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6549              		.loc 1 3066 14 is_stmt 0 view .LVU2280
+ 6550 010e 0126     		movs	r6, #1
+ 6551 0110 1CE0     		b	.L403
+ 6552              	.LVL419:
+ 6553              	.L418:
+3072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6554              		.loc 1 3072 7 is_stmt 1 view .LVU2281
+ 6555 0112 164B     		ldr	r3, .L419+16
+ 6556 0114 0093     		str	r3, [sp]
+ 6557 0116 4346     		mov	r3, r8
+ 6558 0118 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 6559 011c 2946     		mov	r1, r5
+ 6560 011e 2046     		mov	r0, r4
+ 6561              	.LVL420:
+3072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6562              		.loc 1 3072 7 is_stmt 0 view .LVU2282
+ 6563 0120 FFF7FEFF 		bl	I2C_TransferConfig
+ARM GAS  /tmp/ccbUHtu7.s 			page 274
+
+
+ 6564              	.LVL421:
+3075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6565              		.loc 1 3075 7 is_stmt 1 view .LVU2283
+3075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6566              		.loc 1 3075 11 is_stmt 0 view .LVU2284
+ 6567 0124 638D     		ldrh	r3, [r4, #42]
+ 6568 0126 9BB2     		uxth	r3, r3
+3075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6569              		.loc 1 3075 30 view .LVU2285
+ 6570 0128 228D     		ldrh	r2, [r4, #40]
+3075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6571              		.loc 1 3075 23 view .LVU2286
+ 6572 012a 9B1A     		subs	r3, r3, r2
+ 6573 012c 9BB2     		uxth	r3, r3
+ 6574 012e 6385     		strh	r3, [r4, #42]	@ movhi
+3078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6575              		.loc 1 3078 7 is_stmt 1 view .LVU2287
+3078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6576              		.loc 1 3078 7 view .LVU2288
+ 6577 0130 0023     		movs	r3, #0
+ 6578 0132 84F84030 		strb	r3, [r4, #64]
+3078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6579              		.loc 1 3078 7 view .LVU2289
+3084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6580              		.loc 1 3084 7 view .LVU2290
+ 6581 0136 1021     		movs	r1, #16
+ 6582 0138 2046     		mov	r0, r4
+ 6583 013a FFF7FEFF 		bl	I2C_Enable_IRQ
+ 6584              	.LVL422:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6585              		.loc 1 3087 7 view .LVU2291
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6586              		.loc 1 3087 11 is_stmt 0 view .LVU2292
+ 6587 013e 2268     		ldr	r2, [r4]
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6588              		.loc 1 3087 21 view .LVU2293
+ 6589 0140 1368     		ldr	r3, [r2]
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6590              		.loc 1 3087 27 view .LVU2294
+ 6591 0142 43F40043 		orr	r3, r3, #32768
+ 6592 0146 1360     		str	r3, [r2]
+3104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 6593              		.loc 1 3104 5 is_stmt 1 view .LVU2295
+3104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 6594              		.loc 1 3104 12 is_stmt 0 view .LVU2296
+ 6595 0148 00E0     		b	.L403
+ 6596              	.LVL423:
+ 6597              	.L412:
+3108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 6598              		.loc 1 3108 12 view .LVU2297
+ 6599 014a 0226     		movs	r6, #2
+ 6600              	.LVL424:
+ 6601              	.L403:
+3110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6602              		.loc 1 3110 1 view .LVU2298
+ 6603 014c 3046     		mov	r0, r6
+ 6604 014e 02B0     		add	sp, sp, #8
+ARM GAS  /tmp/ccbUHtu7.s 			page 275
+
+
+ 6605              	.LCFI77:
+ 6606              		.cfi_remember_state
+ 6607              		.cfi_def_cfa_offset 24
+ 6608              		@ sp needed
+ 6609 0150 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 6610              	.LVL425:
+ 6611              	.L413:
+ 6612              	.LCFI78:
+ 6613              		.cfi_restore_state
+3000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6614              		.loc 1 3000 14 view .LVU2299
+ 6615 0154 0226     		movs	r6, #2
+ 6616 0156 F9E7     		b	.L403
+ 6617              	.L414:
+3004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6618              		.loc 1 3004 5 view .LVU2300
+ 6619 0158 0226     		movs	r6, #2
+ 6620 015a F7E7     		b	.L403
+ 6621              	.L420:
+ 6622              		.align	2
+ 6623              	.L419:
+ 6624 015c 0000FFFF 		.word	-65536
+ 6625 0160 00000000 		.word	I2C_Master_ISR_DMA
+ 6626 0164 00000000 		.word	I2C_DMAMasterReceiveCplt
+ 6627 0168 00000000 		.word	I2C_DMAError
+ 6628 016c 00240080 		.word	-2147474432
+ 6629              		.cfi_endproc
+ 6630              	.LFE350:
+ 6632              		.section	.text.HAL_I2C_IsDeviceReady,"ax",%progbits
+ 6633              		.align	1
+ 6634              		.global	HAL_I2C_IsDeviceReady
+ 6635              		.syntax unified
+ 6636              		.thumb
+ 6637              		.thumb_func
+ 6639              	HAL_I2C_IsDeviceReady:
+ 6640              	.LVL426:
+ 6641              	.LFB351:
+3125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 6642              		.loc 1 3125 1 is_stmt 1 view -0
+ 6643              		.cfi_startproc
+ 6644              		@ args = 0, pretend = 0, frame = 8
+ 6645              		@ frame_needed = 0, uses_anonymous_args = 0
+3125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tickstart;
+ 6646              		.loc 1 3125 1 is_stmt 0 view .LVU2302
+ 6647 0000 2DE9F043 		push	{r4, r5, r6, r7, r8, r9, lr}
+ 6648              	.LCFI79:
+ 6649              		.cfi_def_cfa_offset 28
+ 6650              		.cfi_offset 4, -28
+ 6651              		.cfi_offset 5, -24
+ 6652              		.cfi_offset 6, -20
+ 6653              		.cfi_offset 7, -16
+ 6654              		.cfi_offset 8, -12
+ 6655              		.cfi_offset 9, -8
+ 6656              		.cfi_offset 14, -4
+ 6657 0004 85B0     		sub	sp, sp, #20
+ 6658              	.LCFI80:
+ 6659              		.cfi_def_cfa_offset 48
+ARM GAS  /tmp/ccbUHtu7.s 			page 276
+
+
+ 6660 0006 1D46     		mov	r5, r3
+3126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6661              		.loc 1 3126 3 is_stmt 1 view .LVU2303
+3128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6662              		.loc 1 3128 3 view .LVU2304
+3128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6663              		.loc 1 3128 17 is_stmt 0 view .LVU2305
+ 6664 0008 0023     		movs	r3, #0
+ 6665              	.LVL427:
+3128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6666              		.loc 1 3128 17 view .LVU2306
+ 6667 000a 0393     		str	r3, [sp, #12]
+3130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   FlagStatus tmp2;
+ 6668              		.loc 1 3130 3 is_stmt 1 view .LVU2307
+3131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6669              		.loc 1 3131 3 view .LVU2308
+3133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 6670              		.loc 1 3133 3 view .LVU2309
+3133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 6671              		.loc 1 3133 11 is_stmt 0 view .LVU2310
+ 6672 000c 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 6673 0010 DBB2     		uxtb	r3, r3
+3133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 6674              		.loc 1 3133 6 view .LVU2311
+ 6675 0012 202B     		cmp	r3, #32
+ 6676 0014 40F09E80 		bne	.L433
+ 6677 0018 0646     		mov	r6, r0
+ 6678 001a 8946     		mov	r9, r1
+ 6679 001c 9046     		mov	r8, r2
+3135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6680              		.loc 1 3135 5 is_stmt 1 view .LVU2312
+3135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6681              		.loc 1 3135 9 is_stmt 0 view .LVU2313
+ 6682 001e 0368     		ldr	r3, [r0]
+ 6683 0020 9B69     		ldr	r3, [r3, #24]
+3135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6684              		.loc 1 3135 8 view .LVU2314
+ 6685 0022 13F4004F 		tst	r3, #32768
+ 6686 0026 40F09780 		bne	.L434
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6687              		.loc 1 3141 5 is_stmt 1 view .LVU2315
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6688              		.loc 1 3141 5 view .LVU2316
+ 6689 002a 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 6690 002e 012B     		cmp	r3, #1
+ 6691 0030 00F09480 		beq	.L435
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6692              		.loc 1 3141 5 discriminator 2 view .LVU2317
+ 6693 0034 0123     		movs	r3, #1
+ 6694 0036 80F84030 		strb	r3, [r0, #64]
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6695              		.loc 1 3141 5 discriminator 2 view .LVU2318
+3143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 6696              		.loc 1 3143 5 discriminator 2 view .LVU2319
+3143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 6697              		.loc 1 3143 17 is_stmt 0 discriminator 2 view .LVU2320
+ 6698 003a 2423     		movs	r3, #36
+ARM GAS  /tmp/ccbUHtu7.s 			page 277
+
+
+ 6699 003c 80F84130 		strb	r3, [r0, #65]
+3144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6700              		.loc 1 3144 5 is_stmt 1 discriminator 2 view .LVU2321
+3144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6701              		.loc 1 3144 21 is_stmt 0 discriminator 2 view .LVU2322
+ 6702 0040 0023     		movs	r3, #0
+ 6703 0042 4364     		str	r3, [r0, #68]
+ 6704 0044 44E0     		b	.L432
+ 6705              	.LVL428:
+ 6706              	.L443:
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6707              		.loc 1 3149 29 discriminator 1 view .LVU2323
+ 6708 0046 C9F30903 		ubfx	r3, r9, #0, #10
+ 6709 004a 43F00073 		orr	r3, r3, #33554432
+ 6710 004e 43F40053 		orr	r3, r3, #8192
+ 6711 0052 44E0     		b	.L424
+ 6712              	.LVL429:
+ 6713              	.L426:
+3177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ 6714              		.loc 1 3177 9 is_stmt 1 view .LVU2324
+3177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ 6715              		.loc 1 3177 16 is_stmt 0 view .LVU2325
+ 6716 0054 3368     		ldr	r3, [r6]
+ 6717 0056 9C69     		ldr	r4, [r3, #24]
+ 6718              	.LVL430:
+3177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ 6719              		.loc 1 3177 16 view .LVU2326
+ 6720 0058 C4F34014 		ubfx	r4, r4, #5, #1
+ 6721              	.LVL431:
+3178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 6722              		.loc 1 3178 9 is_stmt 1 view .LVU2327
+3178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 6723              		.loc 1 3178 16 is_stmt 0 view .LVU2328
+ 6724 005c 9B69     		ldr	r3, [r3, #24]
+ 6725 005e C3F30013 		ubfx	r3, r3, #4, #1
+ 6726              	.LVL432:
+ 6727              	.L425:
+3158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 6728              		.loc 1 3158 30 is_stmt 1 view .LVU2329
+ 6729 0062 C4B9     		cbnz	r4, .L428
+3158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 6730              		.loc 1 3158 30 is_stmt 0 discriminator 1 view .LVU2330
+ 6731 0064 BBB9     		cbnz	r3, .L428
+3160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 6732              		.loc 1 3160 9 is_stmt 1 view .LVU2331
+3160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 6733              		.loc 1 3160 12 is_stmt 0 view .LVU2332
+ 6734 0066 B5F1FF3F 		cmp	r5, #-1
+ 6735 006a F3D0     		beq	.L426
+3162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 6736              		.loc 1 3162 11 is_stmt 1 view .LVU2333
+3162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 6737              		.loc 1 3162 17 is_stmt 0 view .LVU2334
+ 6738 006c FFF7FEFF 		bl	HAL_GetTick
+ 6739              	.LVL433:
+3162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 6740              		.loc 1 3162 31 view .LVU2335
+ARM GAS  /tmp/ccbUHtu7.s 			page 278
+
+
+ 6741 0070 C01B     		subs	r0, r0, r7
+3162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 6742              		.loc 1 3162 14 view .LVU2336
+ 6743 0072 A842     		cmp	r0, r5
+ 6744 0074 01D8     		bhi	.L427
+3162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 6745              		.loc 1 3162 55 discriminator 1 view .LVU2337
+ 6746 0076 002D     		cmp	r5, #0
+ 6747 0078 ECD1     		bne	.L426
+ 6748              	.L427:
+3165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6749              		.loc 1 3165 13 is_stmt 1 view .LVU2338
+3165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6750              		.loc 1 3165 25 is_stmt 0 view .LVU2339
+ 6751 007a 2023     		movs	r3, #32
+ 6752 007c 86F84130 		strb	r3, [r6, #65]
+3168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6753              		.loc 1 3168 13 is_stmt 1 view .LVU2340
+3168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6754              		.loc 1 3168 17 is_stmt 0 view .LVU2341
+ 6755 0080 736C     		ldr	r3, [r6, #68]
+3168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6756              		.loc 1 3168 29 view .LVU2342
+ 6757 0082 43F02003 		orr	r3, r3, #32
+ 6758 0086 7364     		str	r3, [r6, #68]
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6759              		.loc 1 3171 13 is_stmt 1 view .LVU2343
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6760              		.loc 1 3171 13 view .LVU2344
+ 6761 0088 0023     		movs	r3, #0
+ 6762 008a 86F84030 		strb	r3, [r6, #64]
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6763              		.loc 1 3171 13 view .LVU2345
+3173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 6764              		.loc 1 3173 13 view .LVU2346
+3173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 6765              		.loc 1 3173 20 is_stmt 0 view .LVU2347
+ 6766 008e 0120     		movs	r0, #1
+ 6767              	.LVL434:
+ 6768              	.L422:
+3251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6769              		.loc 1 3251 1 view .LVU2348
+ 6770 0090 05B0     		add	sp, sp, #20
+ 6771              	.LCFI81:
+ 6772              		.cfi_remember_state
+ 6773              		.cfi_def_cfa_offset 28
+ 6774              		@ sp needed
+ 6775 0092 BDE8F083 		pop	{r4, r5, r6, r7, r8, r9, pc}
+ 6776              	.LVL435:
+ 6777              	.L428:
+ 6778              	.LCFI82:
+ 6779              		.cfi_restore_state
+3182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 6780              		.loc 1 3182 7 is_stmt 1 view .LVU2349
+3182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 6781              		.loc 1 3182 11 is_stmt 0 view .LVU2350
+ 6782 0096 3368     		ldr	r3, [r6]
+ARM GAS  /tmp/ccbUHtu7.s 			page 279
+
+
+ 6783              	.LVL436:
+3182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 6784              		.loc 1 3182 11 view .LVU2351
+ 6785 0098 9B69     		ldr	r3, [r3, #24]
+3182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 6786              		.loc 1 3182 10 view .LVU2352
+ 6787 009a 13F0100F 		tst	r3, #16
+ 6788 009e 2BD0     		beq	.L440
+3204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 6789              		.loc 1 3204 9 is_stmt 1 view .LVU2353
+3204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 6790              		.loc 1 3204 13 is_stmt 0 view .LVU2354
+ 6791 00a0 0097     		str	r7, [sp]
+ 6792 00a2 2B46     		mov	r3, r5
+ 6793 00a4 0022     		movs	r2, #0
+ 6794 00a6 2021     		movs	r1, #32
+ 6795 00a8 3046     		mov	r0, r6
+ 6796 00aa FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 6797              	.LVL437:
+3204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 6798              		.loc 1 3204 12 view .LVU2355
+ 6799 00ae 0028     		cmp	r0, #0
+ 6800 00b0 58D1     		bne	.L437
+3210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6801              		.loc 1 3210 9 is_stmt 1 view .LVU2356
+ 6802 00b2 3368     		ldr	r3, [r6]
+ 6803 00b4 1022     		movs	r2, #16
+ 6804 00b6 DA61     		str	r2, [r3, #28]
+3213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 6805              		.loc 1 3213 9 view .LVU2357
+ 6806 00b8 3368     		ldr	r3, [r6]
+ 6807 00ba 2022     		movs	r2, #32
+ 6808 00bc DA61     		str	r2, [r3, #28]
+3217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 6809              		.loc 1 3217 7 view .LVU2358
+3217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 6810              		.loc 1 3217 22 is_stmt 0 view .LVU2359
+ 6811 00be 039B     		ldr	r3, [sp, #12]
+3217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 6812              		.loc 1 3217 10 view .LVU2360
+ 6813 00c0 4345     		cmp	r3, r8
+ 6814 00c2 2AD0     		beq	.L441
+ 6815              	.L431:
+3233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     } while (I2C_Trials < Trials);
+ 6816              		.loc 1 3233 7 is_stmt 1 view .LVU2361
+3233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     } while (I2C_Trials < Trials);
+ 6817              		.loc 1 3233 17 is_stmt 0 view .LVU2362
+ 6818 00c4 039B     		ldr	r3, [sp, #12]
+ 6819 00c6 0133     		adds	r3, r3, #1
+ 6820 00c8 0393     		str	r3, [sp, #12]
+3234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6821              		.loc 1 3234 25 is_stmt 1 view .LVU2363
+ 6822 00ca 039B     		ldr	r3, [sp, #12]
+ 6823 00cc 4345     		cmp	r3, r8
+ 6824 00ce 35D2     		bcs	.L442
+ 6825              	.LVL438:
+ 6826              	.L432:
+ARM GAS  /tmp/ccbUHtu7.s 			page 280
+
+
+3146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 6827              		.loc 1 3146 5 view .LVU2364
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6828              		.loc 1 3149 7 view .LVU2365
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6829              		.loc 1 3149 29 is_stmt 0 view .LVU2366
+ 6830 00d0 F368     		ldr	r3, [r6, #12]
+ 6831 00d2 012B     		cmp	r3, #1
+ 6832 00d4 B7D0     		beq	.L443
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6833              		.loc 1 3149 29 discriminator 2 view .LVU2367
+ 6834 00d6 C9F30903 		ubfx	r3, r9, #0, #10
+ 6835 00da 43F42053 		orr	r3, r3, #10240
+ 6836              	.L424:
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6837              		.loc 1 3149 11 discriminator 4 view .LVU2368
+ 6838 00de 3268     		ldr	r2, [r6]
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6839              		.loc 1 3149 27 discriminator 4 view .LVU2369
+ 6840 00e0 5360     		str	r3, [r2, #4]
+3153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6841              		.loc 1 3153 7 is_stmt 1 discriminator 4 view .LVU2370
+3153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6842              		.loc 1 3153 19 is_stmt 0 discriminator 4 view .LVU2371
+ 6843 00e2 FFF7FEFF 		bl	HAL_GetTick
+ 6844              	.LVL439:
+ 6845 00e6 0746     		mov	r7, r0
+ 6846              	.LVL440:
+3155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ 6847              		.loc 1 3155 7 is_stmt 1 discriminator 4 view .LVU2372
+3155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ 6848              		.loc 1 3155 14 is_stmt 0 discriminator 4 view .LVU2373
+ 6849 00e8 3368     		ldr	r3, [r6]
+ 6850 00ea 9C69     		ldr	r4, [r3, #24]
+ 6851 00ec C4F34014 		ubfx	r4, r4, #5, #1
+ 6852              	.LVL441:
+3156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6853              		.loc 1 3156 7 is_stmt 1 discriminator 4 view .LVU2374
+3156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6854              		.loc 1 3156 14 is_stmt 0 discriminator 4 view .LVU2375
+ 6855 00f0 9B69     		ldr	r3, [r3, #24]
+ 6856 00f2 C3F30013 		ubfx	r3, r3, #4, #1
+ 6857              	.LVL442:
+3158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 6858              		.loc 1 3158 7 is_stmt 1 discriminator 4 view .LVU2376
+3158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 6859              		.loc 1 3158 13 is_stmt 0 discriminator 4 view .LVU2377
+ 6860 00f6 B4E7     		b	.L425
+ 6861              	.LVL443:
+ 6862              	.L440:
+3185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 6863              		.loc 1 3185 9 is_stmt 1 view .LVU2378
+3185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 6864              		.loc 1 3185 13 is_stmt 0 view .LVU2379
+ 6865 00f8 0097     		str	r7, [sp]
+ 6866 00fa 2B46     		mov	r3, r5
+ 6867 00fc 0022     		movs	r2, #0
+ARM GAS  /tmp/ccbUHtu7.s 			page 281
+
+
+ 6868 00fe 2021     		movs	r1, #32
+ 6869 0100 3046     		mov	r0, r6
+ 6870 0102 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 6871              	.LVL444:
+3185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 6872              		.loc 1 3185 12 view .LVU2380
+ 6873 0106 58BB     		cbnz	r0, .L436
+3191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6874              		.loc 1 3191 9 is_stmt 1 view .LVU2381
+ 6875 0108 3268     		ldr	r2, [r6]
+ 6876 010a 2023     		movs	r3, #32
+ 6877 010c D361     		str	r3, [r2, #28]
+3194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6878              		.loc 1 3194 9 view .LVU2382
+3194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6879              		.loc 1 3194 21 is_stmt 0 view .LVU2383
+ 6880 010e 86F84130 		strb	r3, [r6, #65]
+3197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6881              		.loc 1 3197 9 is_stmt 1 view .LVU2384
+3197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6882              		.loc 1 3197 9 view .LVU2385
+ 6883 0112 0023     		movs	r3, #0
+ 6884 0114 86F84030 		strb	r3, [r6, #64]
+3197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6885              		.loc 1 3197 9 view .LVU2386
+3199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 6886              		.loc 1 3199 9 view .LVU2387
+3199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 6887              		.loc 1 3199 16 is_stmt 0 view .LVU2388
+ 6888 0118 BAE7     		b	.L422
+ 6889              	.L441:
+3220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6890              		.loc 1 3220 9 is_stmt 1 view .LVU2389
+3220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6891              		.loc 1 3220 13 is_stmt 0 view .LVU2390
+ 6892 011a 3268     		ldr	r2, [r6]
+3220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6893              		.loc 1 3220 23 view .LVU2391
+ 6894 011c 5368     		ldr	r3, [r2, #4]
+3220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6895              		.loc 1 3220 29 view .LVU2392
+ 6896 011e 43F48043 		orr	r3, r3, #16384
+ 6897 0122 5360     		str	r3, [r2, #4]
+3223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 6898              		.loc 1 3223 9 is_stmt 1 view .LVU2393
+3223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 6899              		.loc 1 3223 13 is_stmt 0 view .LVU2394
+ 6900 0124 0097     		str	r7, [sp]
+ 6901 0126 2B46     		mov	r3, r5
+ 6902 0128 0022     		movs	r2, #0
+ 6903 012a 2021     		movs	r1, #32
+ 6904 012c 3046     		mov	r0, r6
+ 6905 012e FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 6906              	.LVL445:
+3223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 6907              		.loc 1 3223 12 view .LVU2395
+ 6908 0132 C8B9     		cbnz	r0, .L438
+ARM GAS  /tmp/ccbUHtu7.s 			page 282
+
+
+3229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 6909              		.loc 1 3229 9 is_stmt 1 view .LVU2396
+ 6910 0134 3368     		ldr	r3, [r6]
+ 6911 0136 2022     		movs	r2, #32
+ 6912 0138 DA61     		str	r2, [r3, #28]
+ 6913 013a C3E7     		b	.L431
+ 6914              	.L442:
+3237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6915              		.loc 1 3237 5 view .LVU2397
+3237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6916              		.loc 1 3237 17 is_stmt 0 view .LVU2398
+ 6917 013c 2023     		movs	r3, #32
+ 6918 013e 86F84130 		strb	r3, [r6, #65]
+3240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6919              		.loc 1 3240 5 is_stmt 1 view .LVU2399
+3240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6920              		.loc 1 3240 9 is_stmt 0 view .LVU2400
+ 6921 0142 736C     		ldr	r3, [r6, #68]
+3240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6922              		.loc 1 3240 21 view .LVU2401
+ 6923 0144 43F02003 		orr	r3, r3, #32
+ 6924 0148 7364     		str	r3, [r6, #68]
+3243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6925              		.loc 1 3243 5 is_stmt 1 view .LVU2402
+3243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6926              		.loc 1 3243 5 view .LVU2403
+ 6927 014a 0023     		movs	r3, #0
+ 6928 014c 86F84030 		strb	r3, [r6, #64]
+3243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6929              		.loc 1 3243 5 view .LVU2404
+3245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 6930              		.loc 1 3245 5 view .LVU2405
+3245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 6931              		.loc 1 3245 12 is_stmt 0 view .LVU2406
+ 6932 0150 0120     		movs	r0, #1
+ 6933 0152 9DE7     		b	.L422
+ 6934              	.LVL446:
+ 6935              	.L433:
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 6936              		.loc 1 3249 12 view .LVU2407
+ 6937 0154 0220     		movs	r0, #2
+ 6938              	.LVL447:
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 6939              		.loc 1 3249 12 view .LVU2408
+ 6940 0156 9BE7     		b	.L422
+ 6941              	.LVL448:
+ 6942              	.L434:
+3137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6943              		.loc 1 3137 14 view .LVU2409
+ 6944 0158 0220     		movs	r0, #2
+ 6945              	.LVL449:
+3137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 6946              		.loc 1 3137 14 view .LVU2410
+ 6947 015a 99E7     		b	.L422
+ 6948              	.LVL450:
+ 6949              	.L435:
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 283
+
+
+ 6950              		.loc 1 3141 5 view .LVU2411
+ 6951 015c 0220     		movs	r0, #2
+ 6952              	.LVL451:
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6953              		.loc 1 3141 5 view .LVU2412
+ 6954 015e 97E7     		b	.L422
+ 6955              	.LVL452:
+ 6956              	.L436:
+3187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 6957              		.loc 1 3187 18 view .LVU2413
+ 6958 0160 0120     		movs	r0, #1
+ 6959 0162 95E7     		b	.L422
+ 6960              	.L437:
+3206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 6961              		.loc 1 3206 18 view .LVU2414
+ 6962 0164 0120     		movs	r0, #1
+ 6963 0166 93E7     		b	.L422
+ 6964              	.L438:
+3225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 6965              		.loc 1 3225 18 view .LVU2415
+ 6966 0168 0120     		movs	r0, #1
+ 6967 016a 91E7     		b	.L422
+ 6968              		.cfi_endproc
+ 6969              	.LFE351:
+ 6971              		.section	.text.HAL_I2C_Master_Seq_Transmit_IT,"ax",%progbits
+ 6972              		.align	1
+ 6973              		.global	HAL_I2C_Master_Seq_Transmit_IT
+ 6974              		.syntax unified
+ 6975              		.thumb
+ 6976              		.thumb_func
+ 6978              	HAL_I2C_Master_Seq_Transmit_IT:
+ 6979              	.LVL453:
+ 6980              	.LFB352:
+3267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 6981              		.loc 1 3267 1 is_stmt 1 view -0
+ 6982              		.cfi_startproc
+ 6983              		@ args = 4, pretend = 0, frame = 0
+ 6984              		@ frame_needed = 0, uses_anonymous_args = 0
+3267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 6985              		.loc 1 3267 1 is_stmt 0 view .LVU2417
+ 6986 0000 70B5     		push	{r4, r5, r6, lr}
+ 6987              	.LCFI83:
+ 6988              		.cfi_def_cfa_offset 16
+ 6989              		.cfi_offset 4, -16
+ 6990              		.cfi_offset 5, -12
+ 6991              		.cfi_offset 6, -8
+ 6992              		.cfi_offset 14, -4
+ 6993 0002 82B0     		sub	sp, sp, #8
+ 6994              	.LCFI84:
+ 6995              		.cfi_def_cfa_offset 24
+ 6996 0004 0446     		mov	r4, r0
+3268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+ 6997              		.loc 1 3268 3 is_stmt 1 view .LVU2418
+3269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 6998              		.loc 1 3269 3 view .LVU2419
+ 6999              	.LVL454:
+3272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 284
+
+
+ 7000              		.loc 1 3272 3 view .LVU2420
+3274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7001              		.loc 1 3274 3 view .LVU2421
+3274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7002              		.loc 1 3274 11 is_stmt 0 view .LVU2422
+ 7003 0006 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 7004              	.LVL455:
+3274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7005              		.loc 1 3274 11 view .LVU2423
+ 7006 000a C0B2     		uxtb	r0, r0
+3274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7007              		.loc 1 3274 6 view .LVU2424
+ 7008 000c 2028     		cmp	r0, #32
+ 7009 000e 49D1     		bne	.L450
+ 7010 0010 0D46     		mov	r5, r1
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7011              		.loc 1 3277 5 is_stmt 1 view .LVU2425
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7012              		.loc 1 3277 5 view .LVU2426
+ 7013 0012 94F84010 		ldrb	r1, [r4, #64]	@ zero_extendqisi2
+ 7014              	.LVL456:
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7015              		.loc 1 3277 5 is_stmt 0 view .LVU2427
+ 7016 0016 0129     		cmp	r1, #1
+ 7017 0018 46D0     		beq	.L451
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7018              		.loc 1 3277 5 is_stmt 1 discriminator 2 view .LVU2428
+ 7019 001a 0121     		movs	r1, #1
+ 7020 001c 84F84010 		strb	r1, [r4, #64]
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7021              		.loc 1 3277 5 discriminator 2 view .LVU2429
+3279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7022              		.loc 1 3279 5 discriminator 2 view .LVU2430
+3279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7023              		.loc 1 3279 21 is_stmt 0 discriminator 2 view .LVU2431
+ 7024 0020 2121     		movs	r1, #33
+ 7025 0022 84F84110 		strb	r1, [r4, #65]
+3280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7026              		.loc 1 3280 5 is_stmt 1 discriminator 2 view .LVU2432
+3280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7027              		.loc 1 3280 21 is_stmt 0 discriminator 2 view .LVU2433
+ 7028 0026 1021     		movs	r1, #16
+ 7029 0028 84F84210 		strb	r1, [r4, #66]
+3281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7030              		.loc 1 3281 5 is_stmt 1 discriminator 2 view .LVU2434
+3281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7031              		.loc 1 3281 21 is_stmt 0 discriminator 2 view .LVU2435
+ 7032 002c 0021     		movs	r1, #0
+ 7033 002e 6164     		str	r1, [r4, #68]
+3284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7034              		.loc 1 3284 5 is_stmt 1 discriminator 2 view .LVU2436
+3284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7035              		.loc 1 3284 23 is_stmt 0 discriminator 2 view .LVU2437
+ 7036 0030 6262     		str	r2, [r4, #36]
+3285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7037              		.loc 1 3285 5 is_stmt 1 discriminator 2 view .LVU2438
+3285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ARM GAS  /tmp/ccbUHtu7.s 			page 285
+
+
+ 7038              		.loc 1 3285 23 is_stmt 0 discriminator 2 view .LVU2439
+ 7039 0032 6385     		strh	r3, [r4, #42]	@ movhi
+3286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 7040              		.loc 1 3286 5 is_stmt 1 discriminator 2 view .LVU2440
+3286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 7041              		.loc 1 3286 23 is_stmt 0 discriminator 2 view .LVU2441
+ 7042 0034 069B     		ldr	r3, [sp, #24]
+ 7043              	.LVL457:
+3286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 7044              		.loc 1 3286 23 discriminator 2 view .LVU2442
+ 7045 0036 E362     		str	r3, [r4, #44]
+ 7046              	.LVL458:
+3287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7047              		.loc 1 3287 5 is_stmt 1 discriminator 2 view .LVU2443
+3287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7048              		.loc 1 3287 23 is_stmt 0 discriminator 2 view .LVU2444
+ 7049 0038 1C4B     		ldr	r3, .L455
+ 7050 003a 6363     		str	r3, [r4, #52]
+3290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7051              		.loc 1 3290 5 is_stmt 1 discriminator 2 view .LVU2445
+3290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7052              		.loc 1 3290 13 is_stmt 0 discriminator 2 view .LVU2446
+ 7053 003c 638D     		ldrh	r3, [r4, #42]
+ 7054 003e 9BB2     		uxth	r3, r3
+3290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7055              		.loc 1 3290 8 discriminator 2 view .LVU2447
+ 7056 0040 FF2B     		cmp	r3, #255
+ 7057 0042 0ED9     		bls	.L446
+3292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 7058              		.loc 1 3292 7 is_stmt 1 view .LVU2448
+3292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 7059              		.loc 1 3292 22 is_stmt 0 view .LVU2449
+ 7060 0044 FF23     		movs	r3, #255
+ 7061 0046 2385     		strh	r3, [r4, #40]	@ movhi
+3293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7062              		.loc 1 3293 7 is_stmt 1 view .LVU2450
+ 7063              	.LVL459:
+3293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7064              		.loc 1 3293 16 is_stmt 0 view .LVU2451
+ 7065 0048 4FF08076 		mov	r6, #16777216
+ 7066              	.LVL460:
+ 7067              	.L447:
+3304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7068              		.loc 1 3304 5 is_stmt 1 view .LVU2452
+3304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7069              		.loc 1 3304 14 is_stmt 0 view .LVU2453
+ 7070 004c 236B     		ldr	r3, [r4, #48]
+3304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7071              		.loc 1 3304 8 view .LVU2454
+ 7072 004e 112B     		cmp	r3, #17
+ 7073 0050 0BD1     		bne	.L448
+3305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7074              		.loc 1 3305 10 view .LVU2455
+ 7075 0052 069B     		ldr	r3, [sp, #24]
+ 7076 0054 AA2B     		cmp	r3, #170
+ 7077 0056 08D0     		beq	.L448
+3305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccbUHtu7.s 			page 286
+
+
+ 7078              		.loc 1 3305 10 discriminator 2 view .LVU2456
+ 7079 0058 B3F52A4F 		cmp	r3, #43520
+ 7080 005c 05D0     		beq	.L448
+3307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7081              		.loc 1 3307 19 view .LVU2457
+ 7082 005e 0023     		movs	r3, #0
+ 7083 0060 0CE0     		b	.L449
+ 7084              	.LVL461:
+ 7085              	.L446:
+3297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7086              		.loc 1 3297 7 is_stmt 1 view .LVU2458
+3297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7087              		.loc 1 3297 28 is_stmt 0 view .LVU2459
+ 7088 0062 638D     		ldrh	r3, [r4, #42]
+3297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7089              		.loc 1 3297 22 view .LVU2460
+ 7090 0064 2385     		strh	r3, [r4, #40]	@ movhi
+3298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7091              		.loc 1 3298 7 is_stmt 1 view .LVU2461
+3298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7092              		.loc 1 3298 16 is_stmt 0 view .LVU2462
+ 7093 0066 E66A     		ldr	r6, [r4, #44]
+ 7094              	.LVL462:
+3298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7095              		.loc 1 3298 16 view .LVU2463
+ 7096 0068 F0E7     		b	.L447
+ 7097              	.L448:
+3312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7098              		.loc 1 3312 7 is_stmt 1 view .LVU2464
+ 7099 006a 2046     		mov	r0, r4
+ 7100 006c FFF7FEFF 		bl	I2C_ConvertOtherXferOptions
+ 7101              	.LVL463:
+3315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7102              		.loc 1 3315 7 view .LVU2465
+3315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7103              		.loc 1 3315 15 is_stmt 0 view .LVU2466
+ 7104 0070 638D     		ldrh	r3, [r4, #42]
+ 7105 0072 9BB2     		uxth	r3, r3
+3315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7106              		.loc 1 3315 10 view .LVU2467
+ 7107 0074 FF2B     		cmp	r3, #255
+ 7108 0076 13D8     		bhi	.L453
+3317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7109              		.loc 1 3317 9 is_stmt 1 view .LVU2468
+3317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7110              		.loc 1 3317 18 is_stmt 0 view .LVU2469
+ 7111 0078 E66A     		ldr	r6, [r4, #44]
+ 7112              	.LVL464:
+3269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7113              		.loc 1 3269 12 view .LVU2470
+ 7114 007a 0D4B     		ldr	r3, .L455+4
+ 7115              	.L449:
+ 7116              	.LVL465:
+3322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7117              		.loc 1 3322 5 is_stmt 1 view .LVU2471
+ 7118 007c 0093     		str	r3, [sp]
+ 7119 007e 3346     		mov	r3, r6
+ARM GAS  /tmp/ccbUHtu7.s 			page 287
+
+
+ 7120              	.LVL466:
+3322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7121              		.loc 1 3322 5 is_stmt 0 view .LVU2472
+ 7122 0080 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 7123 0084 2946     		mov	r1, r5
+ 7124 0086 2046     		mov	r0, r4
+ 7125 0088 FFF7FEFF 		bl	I2C_TransferConfig
+ 7126              	.LVL467:
+3325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7127              		.loc 1 3325 5 is_stmt 1 view .LVU2473
+3325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7128              		.loc 1 3325 5 view .LVU2474
+ 7129 008c 0025     		movs	r5, #0
+ 7130 008e 84F84050 		strb	r5, [r4, #64]
+3325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7131              		.loc 1 3325 5 view .LVU2475
+3330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7132              		.loc 1 3330 5 view .LVU2476
+ 7133 0092 0121     		movs	r1, #1
+ 7134 0094 2046     		mov	r0, r4
+ 7135 0096 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 7136              	.LVL468:
+3332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 7137              		.loc 1 3332 5 view .LVU2477
+3332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 7138              		.loc 1 3332 12 is_stmt 0 view .LVU2478
+ 7139 009a 2846     		mov	r0, r5
+ 7140              	.LVL469:
+ 7141              	.L445:
+3338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7142              		.loc 1 3338 1 view .LVU2479
+ 7143 009c 02B0     		add	sp, sp, #8
+ 7144              	.LCFI85:
+ 7145              		.cfi_remember_state
+ 7146              		.cfi_def_cfa_offset 16
+ 7147              		@ sp needed
+ 7148 009e 70BD     		pop	{r4, r5, r6, pc}
+ 7149              	.LVL470:
+ 7150              	.L453:
+ 7151              	.LCFI86:
+ 7152              		.cfi_restore_state
+3269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7153              		.loc 1 3269 12 view .LVU2480
+ 7154 00a0 034B     		ldr	r3, .L455+4
+ 7155 00a2 EBE7     		b	.L449
+ 7156              	.LVL471:
+ 7157              	.L450:
+3336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 7158              		.loc 1 3336 12 view .LVU2481
+ 7159 00a4 0220     		movs	r0, #2
+ 7160 00a6 F9E7     		b	.L445
+ 7161              	.LVL472:
+ 7162              	.L451:
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7163              		.loc 1 3277 5 view .LVU2482
+ 7164 00a8 0220     		movs	r0, #2
+ 7165 00aa F7E7     		b	.L445
+ARM GAS  /tmp/ccbUHtu7.s 			page 288
+
+
+ 7166              	.L456:
+ 7167              		.align	2
+ 7168              	.L455:
+ 7169 00ac 00000000 		.word	I2C_Master_ISR_IT
+ 7170 00b0 00200080 		.word	-2147475456
+ 7171              		.cfi_endproc
+ 7172              	.LFE352:
+ 7174              		.section	.text.HAL_I2C_Master_Seq_Transmit_DMA,"ax",%progbits
+ 7175              		.align	1
+ 7176              		.global	HAL_I2C_Master_Seq_Transmit_DMA
+ 7177              		.syntax unified
+ 7178              		.thumb
+ 7179              		.thumb_func
+ 7181              	HAL_I2C_Master_Seq_Transmit_DMA:
+ 7182              	.LVL473:
+ 7183              	.LFB353:
+3354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 7184              		.loc 1 3354 1 is_stmt 1 view -0
+ 7185              		.cfi_startproc
+ 7186              		@ args = 4, pretend = 0, frame = 0
+ 7187              		@ frame_needed = 0, uses_anonymous_args = 0
+3354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 7188              		.loc 1 3354 1 is_stmt 0 view .LVU2484
+ 7189 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 7190              	.LCFI87:
+ 7191              		.cfi_def_cfa_offset 24
+ 7192              		.cfi_offset 4, -24
+ 7193              		.cfi_offset 5, -20
+ 7194              		.cfi_offset 6, -16
+ 7195              		.cfi_offset 7, -12
+ 7196              		.cfi_offset 8, -8
+ 7197              		.cfi_offset 14, -4
+ 7198 0004 82B0     		sub	sp, sp, #8
+ 7199              	.LCFI88:
+ 7200              		.cfi_def_cfa_offset 32
+ 7201 0006 0446     		mov	r4, r0
+ 7202 0008 1546     		mov	r5, r2
+ 7203 000a 089A     		ldr	r2, [sp, #32]
+ 7204              	.LVL474:
+3355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+ 7205              		.loc 1 3355 3 is_stmt 1 view .LVU2485
+3356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 7206              		.loc 1 3356 3 view .LVU2486
+3357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7207              		.loc 1 3357 3 view .LVU2487
+3360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7208              		.loc 1 3360 3 view .LVU2488
+3362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7209              		.loc 1 3362 3 view .LVU2489
+3362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7210              		.loc 1 3362 11 is_stmt 0 view .LVU2490
+ 7211 000c 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 7212              	.LVL475:
+3362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7213              		.loc 1 3362 11 view .LVU2491
+ 7214 0010 C0B2     		uxtb	r0, r0
+3362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 289
+
+
+ 7215              		.loc 1 3362 6 view .LVU2492
+ 7216 0012 2028     		cmp	r0, #32
+ 7217 0014 40F09D80 		bne	.L468
+ 7218 0018 0E46     		mov	r6, r1
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7219              		.loc 1 3365 5 is_stmt 1 view .LVU2493
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7220              		.loc 1 3365 5 view .LVU2494
+ 7221 001a 94F84010 		ldrb	r1, [r4, #64]	@ zero_extendqisi2
+ 7222              	.LVL476:
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7223              		.loc 1 3365 5 is_stmt 0 view .LVU2495
+ 7224 001e 0129     		cmp	r1, #1
+ 7225 0020 00F09B80 		beq	.L469
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7226              		.loc 1 3365 5 is_stmt 1 discriminator 2 view .LVU2496
+ 7227 0024 0121     		movs	r1, #1
+ 7228 0026 84F84010 		strb	r1, [r4, #64]
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7229              		.loc 1 3365 5 discriminator 2 view .LVU2497
+3367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7230              		.loc 1 3367 5 discriminator 2 view .LVU2498
+3367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7231              		.loc 1 3367 21 is_stmt 0 discriminator 2 view .LVU2499
+ 7232 002a 2121     		movs	r1, #33
+ 7233 002c 84F84110 		strb	r1, [r4, #65]
+3368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7234              		.loc 1 3368 5 is_stmt 1 discriminator 2 view .LVU2500
+3368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7235              		.loc 1 3368 21 is_stmt 0 discriminator 2 view .LVU2501
+ 7236 0030 1021     		movs	r1, #16
+ 7237 0032 84F84210 		strb	r1, [r4, #66]
+3369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7238              		.loc 1 3369 5 is_stmt 1 discriminator 2 view .LVU2502
+3369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7239              		.loc 1 3369 21 is_stmt 0 discriminator 2 view .LVU2503
+ 7240 0036 0021     		movs	r1, #0
+ 7241 0038 6164     		str	r1, [r4, #68]
+3372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7242              		.loc 1 3372 5 is_stmt 1 discriminator 2 view .LVU2504
+3372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7243              		.loc 1 3372 23 is_stmt 0 discriminator 2 view .LVU2505
+ 7244 003a 6562     		str	r5, [r4, #36]
+3373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7245              		.loc 1 3373 5 is_stmt 1 discriminator 2 view .LVU2506
+3373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7246              		.loc 1 3373 23 is_stmt 0 discriminator 2 view .LVU2507
+ 7247 003c 6385     		strh	r3, [r4, #42]	@ movhi
+3374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 7248              		.loc 1 3374 5 is_stmt 1 discriminator 2 view .LVU2508
+3374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 7249              		.loc 1 3374 23 is_stmt 0 discriminator 2 view .LVU2509
+ 7250 003e E262     		str	r2, [r4, #44]
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7251              		.loc 1 3375 5 is_stmt 1 discriminator 2 view .LVU2510
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7252              		.loc 1 3375 23 is_stmt 0 discriminator 2 view .LVU2511
+ARM GAS  /tmp/ccbUHtu7.s 			page 290
+
+
+ 7253 0040 474B     		ldr	r3, .L475
+ 7254              	.LVL477:
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7255              		.loc 1 3375 23 discriminator 2 view .LVU2512
+ 7256 0042 6363     		str	r3, [r4, #52]
+3378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7257              		.loc 1 3378 5 is_stmt 1 discriminator 2 view .LVU2513
+3378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7258              		.loc 1 3378 13 is_stmt 0 discriminator 2 view .LVU2514
+ 7259 0044 638D     		ldrh	r3, [r4, #42]
+ 7260 0046 9BB2     		uxth	r3, r3
+3378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7261              		.loc 1 3378 8 discriminator 2 view .LVU2515
+ 7262 0048 FF2B     		cmp	r3, #255
+ 7263 004a 0ED9     		bls	.L459
+3380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 7264              		.loc 1 3380 7 is_stmt 1 view .LVU2516
+3380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 7265              		.loc 1 3380 22 is_stmt 0 view .LVU2517
+ 7266 004c FF23     		movs	r3, #255
+ 7267 004e 2385     		strh	r3, [r4, #40]	@ movhi
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7268              		.loc 1 3381 7 is_stmt 1 view .LVU2518
+ 7269              	.LVL478:
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7270              		.loc 1 3381 16 is_stmt 0 view .LVU2519
+ 7271 0050 4FF08077 		mov	r7, #16777216
+ 7272              	.LVL479:
+ 7273              	.L460:
+3392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7274              		.loc 1 3392 5 is_stmt 1 view .LVU2520
+3392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7275              		.loc 1 3392 14 is_stmt 0 view .LVU2521
+ 7276 0054 236B     		ldr	r3, [r4, #48]
+3392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7277              		.loc 1 3392 8 view .LVU2522
+ 7278 0056 112B     		cmp	r3, #17
+ 7279 0058 0BD1     		bne	.L461
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7280              		.loc 1 3393 10 view .LVU2523
+ 7281 005a AA2A     		cmp	r2, #170
+ 7282 005c 09D0     		beq	.L461
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7283              		.loc 1 3393 10 discriminator 2 view .LVU2524
+ 7284 005e B2F52A4F 		cmp	r2, #43520
+ 7285 0062 06D0     		beq	.L461
+3395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7286              		.loc 1 3395 19 view .LVU2525
+ 7287 0064 4FF00008 		mov	r8, #0
+ 7288 0068 0DE0     		b	.L462
+ 7289              	.LVL480:
+ 7290              	.L459:
+3385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7291              		.loc 1 3385 7 is_stmt 1 view .LVU2526
+3385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7292              		.loc 1 3385 28 is_stmt 0 view .LVU2527
+ 7293 006a 638D     		ldrh	r3, [r4, #42]
+ARM GAS  /tmp/ccbUHtu7.s 			page 291
+
+
+3385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7294              		.loc 1 3385 22 view .LVU2528
+ 7295 006c 2385     		strh	r3, [r4, #40]	@ movhi
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7296              		.loc 1 3386 7 is_stmt 1 view .LVU2529
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7297              		.loc 1 3386 16 is_stmt 0 view .LVU2530
+ 7298 006e E76A     		ldr	r7, [r4, #44]
+ 7299              	.LVL481:
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7300              		.loc 1 3386 16 view .LVU2531
+ 7301 0070 F0E7     		b	.L460
+ 7302              	.L461:
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7303              		.loc 1 3400 7 is_stmt 1 view .LVU2532
+ 7304 0072 2046     		mov	r0, r4
+ 7305 0074 FFF7FEFF 		bl	I2C_ConvertOtherXferOptions
+ 7306              	.LVL482:
+3403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7307              		.loc 1 3403 7 view .LVU2533
+3403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7308              		.loc 1 3403 15 is_stmt 0 view .LVU2534
+ 7309 0078 638D     		ldrh	r3, [r4, #42]
+ 7310 007a 9BB2     		uxth	r3, r3
+3403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7311              		.loc 1 3403 10 view .LVU2535
+ 7312 007c FF2B     		cmp	r3, #255
+ 7313 007e 27D8     		bhi	.L471
+3405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7314              		.loc 1 3405 9 is_stmt 1 view .LVU2536
+3405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7315              		.loc 1 3405 18 is_stmt 0 view .LVU2537
+ 7316 0080 E76A     		ldr	r7, [r4, #44]
+ 7317              	.LVL483:
+3356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 7318              		.loc 1 3356 12 view .LVU2538
+ 7319 0082 DFF8EC80 		ldr	r8, .L475+16
+ 7320              	.L462:
+ 7321              	.LVL484:
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7322              		.loc 1 3409 5 is_stmt 1 view .LVU2539
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7323              		.loc 1 3409 13 is_stmt 0 view .LVU2540
+ 7324 0086 228D     		ldrh	r2, [r4, #40]
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7325              		.loc 1 3409 8 view .LVU2541
+ 7326 0088 002A     		cmp	r2, #0
+ 7327 008a 4ED0     		beq	.L463
+3411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7328              		.loc 1 3411 7 is_stmt 1 view .LVU2542
+3411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7329              		.loc 1 3411 15 is_stmt 0 view .LVU2543
+ 7330 008c A36B     		ldr	r3, [r4, #56]
+3411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7331              		.loc 1 3411 10 view .LVU2544
+ 7332 008e 13B3     		cbz	r3, .L464
+3414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 292
+
+
+ 7333              		.loc 1 3414 9 is_stmt 1 view .LVU2545
+3414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7334              		.loc 1 3414 40 is_stmt 0 view .LVU2546
+ 7335 0090 344A     		ldr	r2, .L475+4
+ 7336 0092 DA62     		str	r2, [r3, #44]
+3417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7337              		.loc 1 3417 9 is_stmt 1 view .LVU2547
+3417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7338              		.loc 1 3417 13 is_stmt 0 view .LVU2548
+ 7339 0094 A36B     		ldr	r3, [r4, #56]
+3417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7340              		.loc 1 3417 41 view .LVU2549
+ 7341 0096 344A     		ldr	r2, .L475+8
+ 7342 0098 5A63     		str	r2, [r3, #52]
+3420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 7343              		.loc 1 3420 9 is_stmt 1 view .LVU2550
+3420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 7344              		.loc 1 3420 13 is_stmt 0 view .LVU2551
+ 7345 009a A26B     		ldr	r2, [r4, #56]
+3420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 7346              		.loc 1 3420 44 view .LVU2552
+ 7347 009c 0023     		movs	r3, #0
+ 7348 009e 1363     		str	r3, [r2, #48]
+3421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7349              		.loc 1 3421 9 is_stmt 1 view .LVU2553
+3421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7350              		.loc 1 3421 13 is_stmt 0 view .LVU2554
+ 7351 00a0 A26B     		ldr	r2, [r4, #56]
+3421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7352              		.loc 1 3421 41 view .LVU2555
+ 7353 00a2 9363     		str	r3, [r2, #56]
+3424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 7354              		.loc 1 3424 9 is_stmt 1 view .LVU2556
+3424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 7355              		.loc 1 3424 88 is_stmt 0 view .LVU2557
+ 7356 00a4 2268     		ldr	r2, [r4]
+3424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 7357              		.loc 1 3424 25 view .LVU2558
+ 7358 00a6 238D     		ldrh	r3, [r4, #40]
+ 7359 00a8 2832     		adds	r2, r2, #40
+ 7360 00aa 2946     		mov	r1, r5
+ 7361 00ac A06B     		ldr	r0, [r4, #56]
+ 7362 00ae FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 7363              	.LVL485:
+3442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7364              		.loc 1 3442 7 is_stmt 1 view .LVU2559
+3442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7365              		.loc 1 3442 10 is_stmt 0 view .LVU2560
+ 7366 00b2 F0B1     		cbz	r0, .L474
+3465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 7367              		.loc 1 3465 9 is_stmt 1 view .LVU2561
+3465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 7368              		.loc 1 3465 25 is_stmt 0 view .LVU2562
+ 7369 00b4 2023     		movs	r3, #32
+ 7370 00b6 84F84130 		strb	r3, [r4, #65]
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7371              		.loc 1 3466 9 is_stmt 1 view .LVU2563
+ARM GAS  /tmp/ccbUHtu7.s 			page 293
+
+
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7372              		.loc 1 3466 25 is_stmt 0 view .LVU2564
+ 7373 00ba 0022     		movs	r2, #0
+ 7374 00bc 84F84220 		strb	r2, [r4, #66]
+3469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7375              		.loc 1 3469 9 is_stmt 1 view .LVU2565
+3469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7376              		.loc 1 3469 13 is_stmt 0 view .LVU2566
+ 7377 00c0 636C     		ldr	r3, [r4, #68]
+3469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7378              		.loc 1 3469 25 view .LVU2567
+ 7379 00c2 43F01003 		orr	r3, r3, #16
+ 7380 00c6 6364     		str	r3, [r4, #68]
+3472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7381              		.loc 1 3472 9 is_stmt 1 view .LVU2568
+3472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7382              		.loc 1 3472 9 view .LVU2569
+ 7383 00c8 84F84020 		strb	r2, [r4, #64]
+3472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7384              		.loc 1 3472 9 view .LVU2570
+3474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7385              		.loc 1 3474 9 view .LVU2571
+3474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7386              		.loc 1 3474 16 is_stmt 0 view .LVU2572
+ 7387 00cc 0120     		movs	r0, #1
+ 7388              	.LVL486:
+3474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7389              		.loc 1 3474 16 view .LVU2573
+ 7390 00ce 41E0     		b	.L458
+ 7391              	.LVL487:
+ 7392              	.L471:
+3356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 7393              		.loc 1 3356 12 view .LVU2574
+ 7394 00d0 DFF89C80 		ldr	r8, .L475+16
+ 7395 00d4 D7E7     		b	.L462
+ 7396              	.LVL488:
+ 7397              	.L464:
+3430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 7398              		.loc 1 3430 9 is_stmt 1 view .LVU2575
+3430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 7399              		.loc 1 3430 25 is_stmt 0 view .LVU2576
+ 7400 00d6 2023     		movs	r3, #32
+ 7401 00d8 84F84130 		strb	r3, [r4, #65]
+3431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7402              		.loc 1 3431 9 is_stmt 1 view .LVU2577
+3431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7403              		.loc 1 3431 25 is_stmt 0 view .LVU2578
+ 7404 00dc 0022     		movs	r2, #0
+ 7405 00de 84F84220 		strb	r2, [r4, #66]
+3434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7406              		.loc 1 3434 9 is_stmt 1 view .LVU2579
+3434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7407              		.loc 1 3434 13 is_stmt 0 view .LVU2580
+ 7408 00e2 636C     		ldr	r3, [r4, #68]
+3434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7409              		.loc 1 3434 25 view .LVU2581
+ 7410 00e4 43F08003 		orr	r3, r3, #128
+ARM GAS  /tmp/ccbUHtu7.s 			page 294
+
+
+ 7411 00e8 6364     		str	r3, [r4, #68]
+3437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7412              		.loc 1 3437 9 is_stmt 1 view .LVU2582
+3437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7413              		.loc 1 3437 9 view .LVU2583
+ 7414 00ea 84F84020 		strb	r2, [r4, #64]
+3437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7415              		.loc 1 3437 9 view .LVU2584
+3439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7416              		.loc 1 3439 9 view .LVU2585
+3439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7417              		.loc 1 3439 16 is_stmt 0 view .LVU2586
+ 7418 00ee 0120     		movs	r0, #1
+ 7419 00f0 30E0     		b	.L458
+ 7420              	.LVL489:
+ 7421              	.L474:
+3445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7422              		.loc 1 3445 9 is_stmt 1 view .LVU2587
+ 7423 00f2 CDF80080 		str	r8, [sp]
+ 7424 00f6 3B46     		mov	r3, r7
+ 7425 00f8 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 7426 00fc 3146     		mov	r1, r6
+ 7427 00fe 2046     		mov	r0, r4
+ 7428              	.LVL490:
+3445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7429              		.loc 1 3445 9 is_stmt 0 view .LVU2588
+ 7430 0100 FFF7FEFF 		bl	I2C_TransferConfig
+ 7431              	.LVL491:
+3448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7432              		.loc 1 3448 9 is_stmt 1 view .LVU2589
+3448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7433              		.loc 1 3448 13 is_stmt 0 view .LVU2590
+ 7434 0104 638D     		ldrh	r3, [r4, #42]
+ 7435 0106 9BB2     		uxth	r3, r3
+3448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7436              		.loc 1 3448 32 view .LVU2591
+ 7437 0108 228D     		ldrh	r2, [r4, #40]
+3448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7438              		.loc 1 3448 25 view .LVU2592
+ 7439 010a 9B1A     		subs	r3, r3, r2
+ 7440 010c 9BB2     		uxth	r3, r3
+ 7441 010e 6385     		strh	r3, [r4, #42]	@ movhi
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7442              		.loc 1 3451 9 is_stmt 1 view .LVU2593
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7443              		.loc 1 3451 9 view .LVU2594
+ 7444 0110 0023     		movs	r3, #0
+ 7445 0112 84F84030 		strb	r3, [r4, #64]
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7446              		.loc 1 3451 9 view .LVU2595
+3457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7447              		.loc 1 3457 9 view .LVU2596
+ 7448 0116 1021     		movs	r1, #16
+ 7449 0118 2046     		mov	r0, r4
+ 7450 011a FFF7FEFF 		bl	I2C_Enable_IRQ
+ 7451              	.LVL492:
+3460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ARM GAS  /tmp/ccbUHtu7.s 			page 295
+
+
+ 7452              		.loc 1 3460 9 view .LVU2597
+3460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7453              		.loc 1 3460 13 is_stmt 0 view .LVU2598
+ 7454 011e 2268     		ldr	r2, [r4]
+3460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7455              		.loc 1 3460 23 view .LVU2599
+ 7456 0120 1368     		ldr	r3, [r2]
+3460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7457              		.loc 1 3460 29 view .LVU2600
+ 7458 0122 43F48043 		orr	r3, r3, #16384
+ 7459 0126 1360     		str	r3, [r2]
+ 7460 0128 11E0     		b	.L467
+ 7461              	.LVL493:
+ 7462              	.L463:
+3480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7463              		.loc 1 3480 7 is_stmt 1 view .LVU2601
+3480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7464              		.loc 1 3480 21 is_stmt 0 view .LVU2602
+ 7465 012a 104B     		ldr	r3, .L475+12
+ 7466 012c 6363     		str	r3, [r4, #52]
+3484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 7467              		.loc 1 3484 7 is_stmt 1 view .LVU2603
+ 7468 012e 104B     		ldr	r3, .L475+16
+ 7469 0130 0093     		str	r3, [sp]
+ 7470 0132 4FF00073 		mov	r3, #33554432
+ 7471 0136 D2B2     		uxtb	r2, r2
+ 7472 0138 3146     		mov	r1, r6
+ 7473 013a 2046     		mov	r0, r4
+ 7474 013c FFF7FEFF 		bl	I2C_TransferConfig
+ 7475              	.LVL494:
+3488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7476              		.loc 1 3488 7 view .LVU2604
+3488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7477              		.loc 1 3488 7 view .LVU2605
+ 7478 0140 0023     		movs	r3, #0
+ 7479 0142 84F84030 		strb	r3, [r4, #64]
+3488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7480              		.loc 1 3488 7 view .LVU2606
+3497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7481              		.loc 1 3497 7 view .LVU2607
+ 7482 0146 0121     		movs	r1, #1
+ 7483 0148 2046     		mov	r0, r4
+ 7484 014a FFF7FEFF 		bl	I2C_Enable_IRQ
+ 7485              	.LVL495:
+ 7486              	.L467:
+3500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 7487              		.loc 1 3500 5 view .LVU2608
+3500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 7488              		.loc 1 3500 12 is_stmt 0 view .LVU2609
+ 7489 014e 0020     		movs	r0, #0
+ 7490 0150 00E0     		b	.L458
+ 7491              	.LVL496:
+ 7492              	.L468:
+3504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 7493              		.loc 1 3504 12 view .LVU2610
+ 7494 0152 0220     		movs	r0, #2
+ 7495              	.LVL497:
+ARM GAS  /tmp/ccbUHtu7.s 			page 296
+
+
+ 7496              	.L458:
+3506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7497              		.loc 1 3506 1 view .LVU2611
+ 7498 0154 02B0     		add	sp, sp, #8
+ 7499              	.LCFI89:
+ 7500              		.cfi_remember_state
+ 7501              		.cfi_def_cfa_offset 24
+ 7502              		@ sp needed
+ 7503 0156 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 7504              	.LVL498:
+ 7505              	.L469:
+ 7506              	.LCFI90:
+ 7507              		.cfi_restore_state
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7508              		.loc 1 3365 5 view .LVU2612
+ 7509 015a 0220     		movs	r0, #2
+ 7510 015c FAE7     		b	.L458
+ 7511              	.L476:
+ 7512 015e 00BF     		.align	2
+ 7513              	.L475:
+ 7514 0160 00000000 		.word	I2C_Master_ISR_DMA
+ 7515 0164 00000000 		.word	I2C_DMAMasterTransmitCplt
+ 7516 0168 00000000 		.word	I2C_DMAError
+ 7517 016c 00000000 		.word	I2C_Master_ISR_IT
+ 7518 0170 00200080 		.word	-2147475456
+ 7519              		.cfi_endproc
+ 7520              	.LFE353:
+ 7522              		.section	.text.HAL_I2C_Master_Seq_Receive_IT,"ax",%progbits
+ 7523              		.align	1
+ 7524              		.global	HAL_I2C_Master_Seq_Receive_IT
+ 7525              		.syntax unified
+ 7526              		.thumb
+ 7527              		.thumb_func
+ 7529              	HAL_I2C_Master_Seq_Receive_IT:
+ 7530              	.LVL499:
+ 7531              	.LFB354:
+3522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 7532              		.loc 1 3522 1 is_stmt 1 view -0
+ 7533              		.cfi_startproc
+ 7534              		@ args = 4, pretend = 0, frame = 0
+ 7535              		@ frame_needed = 0, uses_anonymous_args = 0
+3522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 7536              		.loc 1 3522 1 is_stmt 0 view .LVU2614
+ 7537 0000 70B5     		push	{r4, r5, r6, lr}
+ 7538              	.LCFI91:
+ 7539              		.cfi_def_cfa_offset 16
+ 7540              		.cfi_offset 4, -16
+ 7541              		.cfi_offset 5, -12
+ 7542              		.cfi_offset 6, -8
+ 7543              		.cfi_offset 14, -4
+ 7544 0002 82B0     		sub	sp, sp, #8
+ 7545              	.LCFI92:
+ 7546              		.cfi_def_cfa_offset 24
+ 7547 0004 0446     		mov	r4, r0
+3523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_READ;
+ 7548              		.loc 1 3523 3 is_stmt 1 view .LVU2615
+3524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 297
+
+
+ 7549              		.loc 1 3524 3 view .LVU2616
+ 7550              	.LVL500:
+3527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7551              		.loc 1 3527 3 view .LVU2617
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7552              		.loc 1 3529 3 view .LVU2618
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7553              		.loc 1 3529 11 is_stmt 0 view .LVU2619
+ 7554 0006 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 7555              	.LVL501:
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7556              		.loc 1 3529 11 view .LVU2620
+ 7557 000a C0B2     		uxtb	r0, r0
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7558              		.loc 1 3529 6 view .LVU2621
+ 7559 000c 2028     		cmp	r0, #32
+ 7560 000e 49D1     		bne	.L483
+ 7561 0010 0D46     		mov	r5, r1
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7562              		.loc 1 3532 5 is_stmt 1 view .LVU2622
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7563              		.loc 1 3532 5 view .LVU2623
+ 7564 0012 94F84010 		ldrb	r1, [r4, #64]	@ zero_extendqisi2
+ 7565              	.LVL502:
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7566              		.loc 1 3532 5 is_stmt 0 view .LVU2624
+ 7567 0016 0129     		cmp	r1, #1
+ 7568 0018 46D0     		beq	.L484
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7569              		.loc 1 3532 5 is_stmt 1 discriminator 2 view .LVU2625
+ 7570 001a 0121     		movs	r1, #1
+ 7571 001c 84F84010 		strb	r1, [r4, #64]
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7572              		.loc 1 3532 5 discriminator 2 view .LVU2626
+3534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7573              		.loc 1 3534 5 discriminator 2 view .LVU2627
+3534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7574              		.loc 1 3534 21 is_stmt 0 discriminator 2 view .LVU2628
+ 7575 0020 2221     		movs	r1, #34
+ 7576 0022 84F84110 		strb	r1, [r4, #65]
+3535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7577              		.loc 1 3535 5 is_stmt 1 discriminator 2 view .LVU2629
+3535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7578              		.loc 1 3535 21 is_stmt 0 discriminator 2 view .LVU2630
+ 7579 0026 1021     		movs	r1, #16
+ 7580 0028 84F84210 		strb	r1, [r4, #66]
+3536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7581              		.loc 1 3536 5 is_stmt 1 discriminator 2 view .LVU2631
+3536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7582              		.loc 1 3536 21 is_stmt 0 discriminator 2 view .LVU2632
+ 7583 002c 0021     		movs	r1, #0
+ 7584 002e 6164     		str	r1, [r4, #68]
+3539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7585              		.loc 1 3539 5 is_stmt 1 discriminator 2 view .LVU2633
+3539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7586              		.loc 1 3539 23 is_stmt 0 discriminator 2 view .LVU2634
+ 7587 0030 6262     		str	r2, [r4, #36]
+ARM GAS  /tmp/ccbUHtu7.s 			page 298
+
+
+3540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7588              		.loc 1 3540 5 is_stmt 1 discriminator 2 view .LVU2635
+3540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7589              		.loc 1 3540 23 is_stmt 0 discriminator 2 view .LVU2636
+ 7590 0032 6385     		strh	r3, [r4, #42]	@ movhi
+3541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 7591              		.loc 1 3541 5 is_stmt 1 discriminator 2 view .LVU2637
+3541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 7592              		.loc 1 3541 23 is_stmt 0 discriminator 2 view .LVU2638
+ 7593 0034 069B     		ldr	r3, [sp, #24]
+ 7594              	.LVL503:
+3541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 7595              		.loc 1 3541 23 discriminator 2 view .LVU2639
+ 7596 0036 E362     		str	r3, [r4, #44]
+ 7597              	.LVL504:
+3542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7598              		.loc 1 3542 5 is_stmt 1 discriminator 2 view .LVU2640
+3542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7599              		.loc 1 3542 23 is_stmt 0 discriminator 2 view .LVU2641
+ 7600 0038 1C4B     		ldr	r3, .L488
+ 7601 003a 6363     		str	r3, [r4, #52]
+3545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7602              		.loc 1 3545 5 is_stmt 1 discriminator 2 view .LVU2642
+3545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7603              		.loc 1 3545 13 is_stmt 0 discriminator 2 view .LVU2643
+ 7604 003c 638D     		ldrh	r3, [r4, #42]
+ 7605 003e 9BB2     		uxth	r3, r3
+3545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7606              		.loc 1 3545 8 discriminator 2 view .LVU2644
+ 7607 0040 FF2B     		cmp	r3, #255
+ 7608 0042 0ED9     		bls	.L479
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 7609              		.loc 1 3547 7 is_stmt 1 view .LVU2645
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 7610              		.loc 1 3547 22 is_stmt 0 view .LVU2646
+ 7611 0044 FF23     		movs	r3, #255
+ 7612 0046 2385     		strh	r3, [r4, #40]	@ movhi
+3548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7613              		.loc 1 3548 7 is_stmt 1 view .LVU2647
+ 7614              	.LVL505:
+3548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7615              		.loc 1 3548 16 is_stmt 0 view .LVU2648
+ 7616 0048 4FF08076 		mov	r6, #16777216
+ 7617              	.LVL506:
+ 7618              	.L480:
+3559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7619              		.loc 1 3559 5 is_stmt 1 view .LVU2649
+3559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7620              		.loc 1 3559 14 is_stmt 0 view .LVU2650
+ 7621 004c 236B     		ldr	r3, [r4, #48]
+3559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7622              		.loc 1 3559 8 view .LVU2651
+ 7623 004e 122B     		cmp	r3, #18
+ 7624 0050 0BD1     		bne	.L481
+3560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7625              		.loc 1 3560 10 view .LVU2652
+ 7626 0052 069B     		ldr	r3, [sp, #24]
+ARM GAS  /tmp/ccbUHtu7.s 			page 299
+
+
+ 7627 0054 AA2B     		cmp	r3, #170
+ 7628 0056 08D0     		beq	.L481
+3560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7629              		.loc 1 3560 10 discriminator 2 view .LVU2653
+ 7630 0058 B3F52A4F 		cmp	r3, #43520
+ 7631 005c 05D0     		beq	.L481
+3562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7632              		.loc 1 3562 19 view .LVU2654
+ 7633 005e 0023     		movs	r3, #0
+ 7634 0060 0CE0     		b	.L482
+ 7635              	.LVL507:
+ 7636              	.L479:
+3552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7637              		.loc 1 3552 7 is_stmt 1 view .LVU2655
+3552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7638              		.loc 1 3552 28 is_stmt 0 view .LVU2656
+ 7639 0062 638D     		ldrh	r3, [r4, #42]
+3552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7640              		.loc 1 3552 22 view .LVU2657
+ 7641 0064 2385     		strh	r3, [r4, #40]	@ movhi
+3553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7642              		.loc 1 3553 7 is_stmt 1 view .LVU2658
+3553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7643              		.loc 1 3553 16 is_stmt 0 view .LVU2659
+ 7644 0066 E66A     		ldr	r6, [r4, #44]
+ 7645              	.LVL508:
+3553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7646              		.loc 1 3553 16 view .LVU2660
+ 7647 0068 F0E7     		b	.L480
+ 7648              	.L481:
+3567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7649              		.loc 1 3567 7 is_stmt 1 view .LVU2661
+ 7650 006a 2046     		mov	r0, r4
+ 7651 006c FFF7FEFF 		bl	I2C_ConvertOtherXferOptions
+ 7652              	.LVL509:
+3570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7653              		.loc 1 3570 7 view .LVU2662
+3570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7654              		.loc 1 3570 15 is_stmt 0 view .LVU2663
+ 7655 0070 638D     		ldrh	r3, [r4, #42]
+ 7656 0072 9BB2     		uxth	r3, r3
+3570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7657              		.loc 1 3570 10 view .LVU2664
+ 7658 0074 FF2B     		cmp	r3, #255
+ 7659 0076 13D8     		bhi	.L486
+3572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7660              		.loc 1 3572 9 is_stmt 1 view .LVU2665
+3572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7661              		.loc 1 3572 18 is_stmt 0 view .LVU2666
+ 7662 0078 E66A     		ldr	r6, [r4, #44]
+ 7663              	.LVL510:
+3524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7664              		.loc 1 3524 12 view .LVU2667
+ 7665 007a 0D4B     		ldr	r3, .L488+4
+ 7666              	.L482:
+ 7667              	.LVL511:
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 300
+
+
+ 7668              		.loc 1 3577 5 is_stmt 1 view .LVU2668
+ 7669 007c 0093     		str	r3, [sp]
+ 7670 007e 3346     		mov	r3, r6
+ 7671              	.LVL512:
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7672              		.loc 1 3577 5 is_stmt 0 view .LVU2669
+ 7673 0080 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 7674 0084 2946     		mov	r1, r5
+ 7675 0086 2046     		mov	r0, r4
+ 7676 0088 FFF7FEFF 		bl	I2C_TransferConfig
+ 7677              	.LVL513:
+3580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7678              		.loc 1 3580 5 is_stmt 1 view .LVU2670
+3580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7679              		.loc 1 3580 5 view .LVU2671
+ 7680 008c 0025     		movs	r5, #0
+ 7681 008e 84F84050 		strb	r5, [r4, #64]
+3580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7682              		.loc 1 3580 5 view .LVU2672
+3585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7683              		.loc 1 3585 5 view .LVU2673
+ 7684 0092 0221     		movs	r1, #2
+ 7685 0094 2046     		mov	r0, r4
+ 7686 0096 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 7687              	.LVL514:
+3587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 7688              		.loc 1 3587 5 view .LVU2674
+3587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 7689              		.loc 1 3587 12 is_stmt 0 view .LVU2675
+ 7690 009a 2846     		mov	r0, r5
+ 7691              	.LVL515:
+ 7692              	.L478:
+3593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7693              		.loc 1 3593 1 view .LVU2676
+ 7694 009c 02B0     		add	sp, sp, #8
+ 7695              	.LCFI93:
+ 7696              		.cfi_remember_state
+ 7697              		.cfi_def_cfa_offset 16
+ 7698              		@ sp needed
+ 7699 009e 70BD     		pop	{r4, r5, r6, pc}
+ 7700              	.LVL516:
+ 7701              	.L486:
+ 7702              	.LCFI94:
+ 7703              		.cfi_restore_state
+3524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7704              		.loc 1 3524 12 view .LVU2677
+ 7705 00a0 034B     		ldr	r3, .L488+4
+ 7706 00a2 EBE7     		b	.L482
+ 7707              	.LVL517:
+ 7708              	.L483:
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 7709              		.loc 1 3591 12 view .LVU2678
+ 7710 00a4 0220     		movs	r0, #2
+ 7711 00a6 F9E7     		b	.L478
+ 7712              	.LVL518:
+ 7713              	.L484:
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 301
+
+
+ 7714              		.loc 1 3532 5 view .LVU2679
+ 7715 00a8 0220     		movs	r0, #2
+ 7716 00aa F7E7     		b	.L478
+ 7717              	.L489:
+ 7718              		.align	2
+ 7719              	.L488:
+ 7720 00ac 00000000 		.word	I2C_Master_ISR_IT
+ 7721 00b0 00240080 		.word	-2147474432
+ 7722              		.cfi_endproc
+ 7723              	.LFE354:
+ 7725              		.section	.text.HAL_I2C_Master_Seq_Receive_DMA,"ax",%progbits
+ 7726              		.align	1
+ 7727              		.global	HAL_I2C_Master_Seq_Receive_DMA
+ 7728              		.syntax unified
+ 7729              		.thumb
+ 7730              		.thumb_func
+ 7732              	HAL_I2C_Master_Seq_Receive_DMA:
+ 7733              	.LVL519:
+ 7734              	.LFB355:
+3609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 7735              		.loc 1 3609 1 is_stmt 1 view -0
+ 7736              		.cfi_startproc
+ 7737              		@ args = 4, pretend = 0, frame = 0
+ 7738              		@ frame_needed = 0, uses_anonymous_args = 0
+3609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 7739              		.loc 1 3609 1 is_stmt 0 view .LVU2681
+ 7740 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 7741              	.LCFI95:
+ 7742              		.cfi_def_cfa_offset 24
+ 7743              		.cfi_offset 4, -24
+ 7744              		.cfi_offset 5, -20
+ 7745              		.cfi_offset 6, -16
+ 7746              		.cfi_offset 7, -12
+ 7747              		.cfi_offset 8, -8
+ 7748              		.cfi_offset 14, -4
+ 7749 0004 82B0     		sub	sp, sp, #8
+ 7750              	.LCFI96:
+ 7751              		.cfi_def_cfa_offset 32
+ 7752 0006 0446     		mov	r4, r0
+ 7753 0008 1546     		mov	r5, r2
+ 7754 000a 089A     		ldr	r2, [sp, #32]
+ 7755              	.LVL520:
+3610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_READ;
+ 7756              		.loc 1 3610 3 is_stmt 1 view .LVU2682
+3611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 7757              		.loc 1 3611 3 view .LVU2683
+3612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7758              		.loc 1 3612 3 view .LVU2684
+3615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7759              		.loc 1 3615 3 view .LVU2685
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7760              		.loc 1 3617 3 view .LVU2686
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7761              		.loc 1 3617 11 is_stmt 0 view .LVU2687
+ 7762 000c 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 7763              	.LVL521:
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 302
+
+
+ 7764              		.loc 1 3617 11 view .LVU2688
+ 7765 0010 C0B2     		uxtb	r0, r0
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 7766              		.loc 1 3617 6 view .LVU2689
+ 7767 0012 2028     		cmp	r0, #32
+ 7768 0014 40F09D80 		bne	.L501
+ 7769 0018 0E46     		mov	r6, r1
+3620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7770              		.loc 1 3620 5 is_stmt 1 view .LVU2690
+3620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7771              		.loc 1 3620 5 view .LVU2691
+ 7772 001a 94F84010 		ldrb	r1, [r4, #64]	@ zero_extendqisi2
+ 7773              	.LVL522:
+3620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7774              		.loc 1 3620 5 is_stmt 0 view .LVU2692
+ 7775 001e 0129     		cmp	r1, #1
+ 7776 0020 00F09B80 		beq	.L502
+3620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7777              		.loc 1 3620 5 is_stmt 1 discriminator 2 view .LVU2693
+ 7778 0024 0121     		movs	r1, #1
+ 7779 0026 84F84010 		strb	r1, [r4, #64]
+3620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7780              		.loc 1 3620 5 discriminator 2 view .LVU2694
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7781              		.loc 1 3622 5 discriminator 2 view .LVU2695
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7782              		.loc 1 3622 21 is_stmt 0 discriminator 2 view .LVU2696
+ 7783 002a 2221     		movs	r1, #34
+ 7784 002c 84F84110 		strb	r1, [r4, #65]
+3623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7785              		.loc 1 3623 5 is_stmt 1 discriminator 2 view .LVU2697
+3623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7786              		.loc 1 3623 21 is_stmt 0 discriminator 2 view .LVU2698
+ 7787 0030 1021     		movs	r1, #16
+ 7788 0032 84F84210 		strb	r1, [r4, #66]
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7789              		.loc 1 3624 5 is_stmt 1 discriminator 2 view .LVU2699
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7790              		.loc 1 3624 21 is_stmt 0 discriminator 2 view .LVU2700
+ 7791 0036 0021     		movs	r1, #0
+ 7792 0038 6164     		str	r1, [r4, #68]
+3627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7793              		.loc 1 3627 5 is_stmt 1 discriminator 2 view .LVU2701
+3627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7794              		.loc 1 3627 23 is_stmt 0 discriminator 2 view .LVU2702
+ 7795 003a 6562     		str	r5, [r4, #36]
+3628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7796              		.loc 1 3628 5 is_stmt 1 discriminator 2 view .LVU2703
+3628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7797              		.loc 1 3628 23 is_stmt 0 discriminator 2 view .LVU2704
+ 7798 003c 6385     		strh	r3, [r4, #42]	@ movhi
+3629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 7799              		.loc 1 3629 5 is_stmt 1 discriminator 2 view .LVU2705
+3629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 7800              		.loc 1 3629 23 is_stmt 0 discriminator 2 view .LVU2706
+ 7801 003e E262     		str	r2, [r4, #44]
+3630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 303
+
+
+ 7802              		.loc 1 3630 5 is_stmt 1 discriminator 2 view .LVU2707
+3630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7803              		.loc 1 3630 23 is_stmt 0 discriminator 2 view .LVU2708
+ 7804 0040 474B     		ldr	r3, .L508
+ 7805              	.LVL523:
+3630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7806              		.loc 1 3630 23 discriminator 2 view .LVU2709
+ 7807 0042 6363     		str	r3, [r4, #52]
+3633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7808              		.loc 1 3633 5 is_stmt 1 discriminator 2 view .LVU2710
+3633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7809              		.loc 1 3633 13 is_stmt 0 discriminator 2 view .LVU2711
+ 7810 0044 638D     		ldrh	r3, [r4, #42]
+ 7811 0046 9BB2     		uxth	r3, r3
+3633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7812              		.loc 1 3633 8 discriminator 2 view .LVU2712
+ 7813 0048 FF2B     		cmp	r3, #255
+ 7814 004a 0ED9     		bls	.L492
+3635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 7815              		.loc 1 3635 7 is_stmt 1 view .LVU2713
+3635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 7816              		.loc 1 3635 22 is_stmt 0 view .LVU2714
+ 7817 004c FF23     		movs	r3, #255
+ 7818 004e 2385     		strh	r3, [r4, #40]	@ movhi
+3636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7819              		.loc 1 3636 7 is_stmt 1 view .LVU2715
+ 7820              	.LVL524:
+3636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7821              		.loc 1 3636 16 is_stmt 0 view .LVU2716
+ 7822 0050 4FF08077 		mov	r7, #16777216
+ 7823              	.LVL525:
+ 7824              	.L493:
+3647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7825              		.loc 1 3647 5 is_stmt 1 view .LVU2717
+3647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7826              		.loc 1 3647 14 is_stmt 0 view .LVU2718
+ 7827 0054 236B     		ldr	r3, [r4, #48]
+3647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7828              		.loc 1 3647 8 view .LVU2719
+ 7829 0056 122B     		cmp	r3, #18
+ 7830 0058 0BD1     		bne	.L494
+3648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7831              		.loc 1 3648 10 view .LVU2720
+ 7832 005a AA2A     		cmp	r2, #170
+ 7833 005c 09D0     		beq	.L494
+3648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7834              		.loc 1 3648 10 discriminator 2 view .LVU2721
+ 7835 005e B2F52A4F 		cmp	r2, #43520
+ 7836 0062 06D0     		beq	.L494
+3650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7837              		.loc 1 3650 19 view .LVU2722
+ 7838 0064 4FF00008 		mov	r8, #0
+ 7839 0068 0DE0     		b	.L495
+ 7840              	.LVL526:
+ 7841              	.L492:
+3640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7842              		.loc 1 3640 7 is_stmt 1 view .LVU2723
+ARM GAS  /tmp/ccbUHtu7.s 			page 304
+
+
+3640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7843              		.loc 1 3640 28 is_stmt 0 view .LVU2724
+ 7844 006a 638D     		ldrh	r3, [r4, #42]
+3640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7845              		.loc 1 3640 22 view .LVU2725
+ 7846 006c 2385     		strh	r3, [r4, #40]	@ movhi
+3641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7847              		.loc 1 3641 7 is_stmt 1 view .LVU2726
+3641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7848              		.loc 1 3641 16 is_stmt 0 view .LVU2727
+ 7849 006e E76A     		ldr	r7, [r4, #44]
+ 7850              	.LVL527:
+3641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 7851              		.loc 1 3641 16 view .LVU2728
+ 7852 0070 F0E7     		b	.L493
+ 7853              	.L494:
+3655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7854              		.loc 1 3655 7 is_stmt 1 view .LVU2729
+ 7855 0072 2046     		mov	r0, r4
+ 7856 0074 FFF7FEFF 		bl	I2C_ConvertOtherXferOptions
+ 7857              	.LVL528:
+3658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7858              		.loc 1 3658 7 view .LVU2730
+3658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7859              		.loc 1 3658 15 is_stmt 0 view .LVU2731
+ 7860 0078 638D     		ldrh	r3, [r4, #42]
+ 7861 007a 9BB2     		uxth	r3, r3
+3658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7862              		.loc 1 3658 10 view .LVU2732
+ 7863 007c FF2B     		cmp	r3, #255
+ 7864 007e 27D8     		bhi	.L504
+3660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7865              		.loc 1 3660 9 is_stmt 1 view .LVU2733
+3660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7866              		.loc 1 3660 18 is_stmt 0 view .LVU2734
+ 7867 0080 E76A     		ldr	r7, [r4, #44]
+ 7868              	.LVL529:
+3611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 7869              		.loc 1 3611 12 view .LVU2735
+ 7870 0082 DFF8EC80 		ldr	r8, .L508+16
+ 7871              	.L495:
+ 7872              	.LVL530:
+3664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7873              		.loc 1 3664 5 is_stmt 1 view .LVU2736
+3664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7874              		.loc 1 3664 13 is_stmt 0 view .LVU2737
+ 7875 0086 228D     		ldrh	r2, [r4, #40]
+3664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 7876              		.loc 1 3664 8 view .LVU2738
+ 7877 0088 002A     		cmp	r2, #0
+ 7878 008a 4ED0     		beq	.L496
+3666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7879              		.loc 1 3666 7 is_stmt 1 view .LVU2739
+3666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7880              		.loc 1 3666 15 is_stmt 0 view .LVU2740
+ 7881 008c E36B     		ldr	r3, [r4, #60]
+3666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ARM GAS  /tmp/ccbUHtu7.s 			page 305
+
+
+ 7882              		.loc 1 3666 10 view .LVU2741
+ 7883 008e 13B3     		cbz	r3, .L497
+3669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7884              		.loc 1 3669 9 is_stmt 1 view .LVU2742
+3669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7885              		.loc 1 3669 40 is_stmt 0 view .LVU2743
+ 7886 0090 344A     		ldr	r2, .L508+4
+ 7887 0092 DA62     		str	r2, [r3, #44]
+3672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7888              		.loc 1 3672 9 is_stmt 1 view .LVU2744
+3672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7889              		.loc 1 3672 13 is_stmt 0 view .LVU2745
+ 7890 0094 E36B     		ldr	r3, [r4, #60]
+3672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7891              		.loc 1 3672 41 view .LVU2746
+ 7892 0096 344A     		ldr	r2, .L508+8
+ 7893 0098 5A63     		str	r2, [r3, #52]
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+ 7894              		.loc 1 3675 9 is_stmt 1 view .LVU2747
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+ 7895              		.loc 1 3675 13 is_stmt 0 view .LVU2748
+ 7896 009a E26B     		ldr	r2, [r4, #60]
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+ 7897              		.loc 1 3675 44 view .LVU2749
+ 7898 009c 0023     		movs	r3, #0
+ 7899 009e 1363     		str	r3, [r2, #48]
+3676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7900              		.loc 1 3676 9 is_stmt 1 view .LVU2750
+3676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7901              		.loc 1 3676 13 is_stmt 0 view .LVU2751
+ 7902 00a0 E26B     		ldr	r2, [r4, #60]
+3676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7903              		.loc 1 3676 41 view .LVU2752
+ 7904 00a2 9363     		str	r3, [r2, #56]
+3679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 7905              		.loc 1 3679 9 is_stmt 1 view .LVU2753
+3679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 7906              		.loc 1 3679 71 is_stmt 0 view .LVU2754
+ 7907 00a4 2168     		ldr	r1, [r4]
+3679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 7908              		.loc 1 3679 25 view .LVU2755
+ 7909 00a6 238D     		ldrh	r3, [r4, #40]
+ 7910 00a8 2A46     		mov	r2, r5
+ 7911 00aa 2431     		adds	r1, r1, #36
+ 7912 00ac E06B     		ldr	r0, [r4, #60]
+ 7913 00ae FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 7914              	.LVL531:
+3697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7915              		.loc 1 3697 7 is_stmt 1 view .LVU2756
+3697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 7916              		.loc 1 3697 10 is_stmt 0 view .LVU2757
+ 7917 00b2 F0B1     		cbz	r0, .L507
+3720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 7918              		.loc 1 3720 9 is_stmt 1 view .LVU2758
+3720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 7919              		.loc 1 3720 25 is_stmt 0 view .LVU2759
+ 7920 00b4 2023     		movs	r3, #32
+ARM GAS  /tmp/ccbUHtu7.s 			page 306
+
+
+ 7921 00b6 84F84130 		strb	r3, [r4, #65]
+3721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7922              		.loc 1 3721 9 is_stmt 1 view .LVU2760
+3721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7923              		.loc 1 3721 25 is_stmt 0 view .LVU2761
+ 7924 00ba 0022     		movs	r2, #0
+ 7925 00bc 84F84220 		strb	r2, [r4, #66]
+3724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7926              		.loc 1 3724 9 is_stmt 1 view .LVU2762
+3724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7927              		.loc 1 3724 13 is_stmt 0 view .LVU2763
+ 7928 00c0 636C     		ldr	r3, [r4, #68]
+3724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7929              		.loc 1 3724 25 view .LVU2764
+ 7930 00c2 43F01003 		orr	r3, r3, #16
+ 7931 00c6 6364     		str	r3, [r4, #68]
+3727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7932              		.loc 1 3727 9 is_stmt 1 view .LVU2765
+3727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7933              		.loc 1 3727 9 view .LVU2766
+ 7934 00c8 84F84020 		strb	r2, [r4, #64]
+3727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7935              		.loc 1 3727 9 view .LVU2767
+3729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7936              		.loc 1 3729 9 view .LVU2768
+3729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7937              		.loc 1 3729 16 is_stmt 0 view .LVU2769
+ 7938 00cc 0120     		movs	r0, #1
+ 7939              	.LVL532:
+3729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7940              		.loc 1 3729 16 view .LVU2770
+ 7941 00ce 41E0     		b	.L491
+ 7942              	.LVL533:
+ 7943              	.L504:
+3611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 7944              		.loc 1 3611 12 view .LVU2771
+ 7945 00d0 DFF89C80 		ldr	r8, .L508+16
+ 7946 00d4 D7E7     		b	.L495
+ 7947              	.LVL534:
+ 7948              	.L497:
+3685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 7949              		.loc 1 3685 9 is_stmt 1 view .LVU2772
+3685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 7950              		.loc 1 3685 25 is_stmt 0 view .LVU2773
+ 7951 00d6 2023     		movs	r3, #32
+ 7952 00d8 84F84130 		strb	r3, [r4, #65]
+3686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7953              		.loc 1 3686 9 is_stmt 1 view .LVU2774
+3686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7954              		.loc 1 3686 25 is_stmt 0 view .LVU2775
+ 7955 00dc 0022     		movs	r2, #0
+ 7956 00de 84F84220 		strb	r2, [r4, #66]
+3689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7957              		.loc 1 3689 9 is_stmt 1 view .LVU2776
+3689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7958              		.loc 1 3689 13 is_stmt 0 view .LVU2777
+ 7959 00e2 636C     		ldr	r3, [r4, #68]
+ARM GAS  /tmp/ccbUHtu7.s 			page 307
+
+
+3689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7960              		.loc 1 3689 25 view .LVU2778
+ 7961 00e4 43F08003 		orr	r3, r3, #128
+ 7962 00e8 6364     		str	r3, [r4, #68]
+3692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7963              		.loc 1 3692 9 is_stmt 1 view .LVU2779
+3692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7964              		.loc 1 3692 9 view .LVU2780
+ 7965 00ea 84F84020 		strb	r2, [r4, #64]
+3692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7966              		.loc 1 3692 9 view .LVU2781
+3694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7967              		.loc 1 3694 9 view .LVU2782
+3694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 7968              		.loc 1 3694 16 is_stmt 0 view .LVU2783
+ 7969 00ee 0120     		movs	r0, #1
+ 7970 00f0 30E0     		b	.L491
+ 7971              	.LVL535:
+ 7972              	.L507:
+3700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7973              		.loc 1 3700 9 is_stmt 1 view .LVU2784
+ 7974 00f2 CDF80080 		str	r8, [sp]
+ 7975 00f6 3B46     		mov	r3, r7
+ 7976 00f8 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 7977 00fc 3146     		mov	r1, r6
+ 7978 00fe 2046     		mov	r0, r4
+ 7979              	.LVL536:
+3700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7980              		.loc 1 3700 9 is_stmt 0 view .LVU2785
+ 7981 0100 FFF7FEFF 		bl	I2C_TransferConfig
+ 7982              	.LVL537:
+3703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7983              		.loc 1 3703 9 is_stmt 1 view .LVU2786
+3703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7984              		.loc 1 3703 13 is_stmt 0 view .LVU2787
+ 7985 0104 638D     		ldrh	r3, [r4, #42]
+ 7986 0106 9BB2     		uxth	r3, r3
+3703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7987              		.loc 1 3703 32 view .LVU2788
+ 7988 0108 228D     		ldrh	r2, [r4, #40]
+3703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7989              		.loc 1 3703 25 view .LVU2789
+ 7990 010a 9B1A     		subs	r3, r3, r2
+ 7991 010c 9BB2     		uxth	r3, r3
+ 7992 010e 6385     		strh	r3, [r4, #42]	@ movhi
+3706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7993              		.loc 1 3706 9 is_stmt 1 view .LVU2790
+3706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7994              		.loc 1 3706 9 view .LVU2791
+ 7995 0110 0023     		movs	r3, #0
+ 7996 0112 84F84030 		strb	r3, [r4, #64]
+3706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7997              		.loc 1 3706 9 view .LVU2792
+3712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 7998              		.loc 1 3712 9 view .LVU2793
+ 7999 0116 1021     		movs	r1, #16
+ 8000 0118 2046     		mov	r0, r4
+ARM GAS  /tmp/ccbUHtu7.s 			page 308
+
+
+ 8001 011a FFF7FEFF 		bl	I2C_Enable_IRQ
+ 8002              	.LVL538:
+3715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 8003              		.loc 1 3715 9 view .LVU2794
+3715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 8004              		.loc 1 3715 13 is_stmt 0 view .LVU2795
+ 8005 011e 2268     		ldr	r2, [r4]
+3715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 8006              		.loc 1 3715 23 view .LVU2796
+ 8007 0120 1368     		ldr	r3, [r2]
+3715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 8008              		.loc 1 3715 29 view .LVU2797
+ 8009 0122 43F40043 		orr	r3, r3, #32768
+ 8010 0126 1360     		str	r3, [r2]
+ 8011 0128 11E0     		b	.L500
+ 8012              	.LVL539:
+ 8013              	.L496:
+3735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8014              		.loc 1 3735 7 is_stmt 1 view .LVU2798
+3735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8015              		.loc 1 3735 21 is_stmt 0 view .LVU2799
+ 8016 012a 104B     		ldr	r3, .L508+12
+ 8017 012c 6363     		str	r3, [r4, #52]
+3739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 8018              		.loc 1 3739 7 is_stmt 1 view .LVU2800
+ 8019 012e 104B     		ldr	r3, .L508+16
+ 8020 0130 0093     		str	r3, [sp]
+ 8021 0132 4FF00073 		mov	r3, #33554432
+ 8022 0136 D2B2     		uxtb	r2, r2
+ 8023 0138 3146     		mov	r1, r6
+ 8024 013a 2046     		mov	r0, r4
+ 8025 013c FFF7FEFF 		bl	I2C_TransferConfig
+ 8026              	.LVL540:
+3743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8027              		.loc 1 3743 7 view .LVU2801
+3743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8028              		.loc 1 3743 7 view .LVU2802
+ 8029 0140 0023     		movs	r3, #0
+ 8030 0142 84F84030 		strb	r3, [r4, #64]
+3743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8031              		.loc 1 3743 7 view .LVU2803
+3752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8032              		.loc 1 3752 7 view .LVU2804
+ 8033 0146 0121     		movs	r1, #1
+ 8034 0148 2046     		mov	r0, r4
+ 8035 014a FFF7FEFF 		bl	I2C_Enable_IRQ
+ 8036              	.LVL541:
+ 8037              	.L500:
+3755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 8038              		.loc 1 3755 5 view .LVU2805
+3755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 8039              		.loc 1 3755 12 is_stmt 0 view .LVU2806
+ 8040 014e 0020     		movs	r0, #0
+ 8041 0150 00E0     		b	.L491
+ 8042              	.LVL542:
+ 8043              	.L501:
+3759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccbUHtu7.s 			page 309
+
+
+ 8044              		.loc 1 3759 12 view .LVU2807
+ 8045 0152 0220     		movs	r0, #2
+ 8046              	.LVL543:
+ 8047              	.L491:
+3761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8048              		.loc 1 3761 1 view .LVU2808
+ 8049 0154 02B0     		add	sp, sp, #8
+ 8050              	.LCFI97:
+ 8051              		.cfi_remember_state
+ 8052              		.cfi_def_cfa_offset 24
+ 8053              		@ sp needed
+ 8054 0156 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 8055              	.LVL544:
+ 8056              	.L502:
+ 8057              	.LCFI98:
+ 8058              		.cfi_restore_state
+3620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8059              		.loc 1 3620 5 view .LVU2809
+ 8060 015a 0220     		movs	r0, #2
+ 8061 015c FAE7     		b	.L491
+ 8062              	.L509:
+ 8063 015e 00BF     		.align	2
+ 8064              	.L508:
+ 8065 0160 00000000 		.word	I2C_Master_ISR_DMA
+ 8066 0164 00000000 		.word	I2C_DMAMasterReceiveCplt
+ 8067 0168 00000000 		.word	I2C_DMAError
+ 8068 016c 00000000 		.word	I2C_Master_ISR_IT
+ 8069 0170 00240080 		.word	-2147474432
+ 8070              		.cfi_endproc
+ 8071              	.LFE355:
+ 8073              		.section	.text.HAL_I2C_Slave_Seq_Transmit_IT,"ax",%progbits
+ 8074              		.align	1
+ 8075              		.global	HAL_I2C_Slave_Seq_Transmit_IT
+ 8076              		.syntax unified
+ 8077              		.thumb
+ 8078              		.thumb_func
+ 8080              	HAL_I2C_Slave_Seq_Transmit_IT:
+ 8081              	.LVL545:
+ 8082              	.LFB356:
+3775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+ 8083              		.loc 1 3775 1 is_stmt 1 view -0
+ 8084              		.cfi_startproc
+ 8085              		@ args = 0, pretend = 0, frame = 0
+ 8086              		@ frame_needed = 0, uses_anonymous_args = 0
+3775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+ 8087              		.loc 1 3775 1 is_stmt 0 view .LVU2811
+ 8088 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 8089              	.LCFI99:
+ 8090              		.cfi_def_cfa_offset 24
+ 8091              		.cfi_offset 3, -24
+ 8092              		.cfi_offset 4, -20
+ 8093              		.cfi_offset 5, -16
+ 8094              		.cfi_offset 6, -12
+ 8095              		.cfi_offset 7, -8
+ 8096              		.cfi_offset 14, -4
+ 8097 0002 0446     		mov	r4, r0
+3777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 310
+
+
+ 8098              		.loc 1 3777 3 is_stmt 1 view .LVU2812
+3779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 8099              		.loc 1 3779 3 view .LVU2813
+3779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 8100              		.loc 1 3779 22 is_stmt 0 view .LVU2814
+ 8101 0004 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 8102              	.LVL546:
+3779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 8103              		.loc 1 3779 6 view .LVU2815
+ 8104 0008 00F02800 		and	r0, r0, #40
+ 8105 000c 2828     		cmp	r0, #40
+ 8106 000e 5AD1     		bne	.L516
+ 8107 0010 0F46     		mov	r7, r1
+ 8108 0012 1646     		mov	r6, r2
+ 8109 0014 1D46     		mov	r5, r3
+3781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8110              		.loc 1 3781 5 is_stmt 1 view .LVU2816
+3781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8111              		.loc 1 3781 8 is_stmt 0 view .LVU2817
+ 8112 0016 01B1     		cbz	r1, .L512
+3781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8113              		.loc 1 3781 25 discriminator 1 view .LVU2818
+ 8114 0018 22B9     		cbnz	r2, .L513
+ 8115              	.L512:
+3783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8116              		.loc 1 3783 7 is_stmt 1 view .LVU2819
+3783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8117              		.loc 1 3783 23 is_stmt 0 view .LVU2820
+ 8118 001a 4FF40073 		mov	r3, #512
+ 8119              	.LVL547:
+3783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8120              		.loc 1 3783 23 view .LVU2821
+ 8121 001e 6364     		str	r3, [r4, #68]
+3784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8122              		.loc 1 3784 7 is_stmt 1 view .LVU2822
+3784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8123              		.loc 1 3784 15 is_stmt 0 view .LVU2823
+ 8124 0020 0120     		movs	r0, #1
+ 8125 0022 51E0     		b	.L511
+ 8126              	.LVL548:
+ 8127              	.L513:
+3788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8128              		.loc 1 3788 5 is_stmt 1 view .LVU2824
+ 8129 0024 48F20101 		movw	r1, #32769
+ 8130              	.LVL549:
+3788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8131              		.loc 1 3788 5 is_stmt 0 view .LVU2825
+ 8132 0028 2046     		mov	r0, r4
+ 8133 002a FFF7FEFF 		bl	I2C_Disable_IRQ
+ 8134              	.LVL550:
+3791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8135              		.loc 1 3791 5 is_stmt 1 view .LVU2826
+3791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8136              		.loc 1 3791 5 view .LVU2827
+ 8137 002e 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 8138 0032 012B     		cmp	r3, #1
+ 8139 0034 49D0     		beq	.L517
+ARM GAS  /tmp/ccbUHtu7.s 			page 311
+
+
+3791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8140              		.loc 1 3791 5 discriminator 2 view .LVU2828
+ 8141 0036 0123     		movs	r3, #1
+ 8142 0038 84F84030 		strb	r3, [r4, #64]
+3791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8143              		.loc 1 3791 5 discriminator 2 view .LVU2829
+3795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8144              		.loc 1 3795 5 discriminator 2 view .LVU2830
+3795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8145              		.loc 1 3795 13 is_stmt 0 discriminator 2 view .LVU2831
+ 8146 003c 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 8147 0040 DBB2     		uxtb	r3, r3
+3795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8148              		.loc 1 3795 8 discriminator 2 view .LVU2832
+ 8149 0042 2A2B     		cmp	r3, #42
+ 8150 0044 24D0     		beq	.L519
+ 8151              	.L514:
+3821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 8152              		.loc 1 3821 5 is_stmt 1 view .LVU2833
+3821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 8153              		.loc 1 3821 21 is_stmt 0 view .LVU2834
+ 8154 0046 2923     		movs	r3, #41
+ 8155 0048 84F84130 		strb	r3, [r4, #65]
+3822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8156              		.loc 1 3822 5 is_stmt 1 view .LVU2835
+3822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8157              		.loc 1 3822 21 is_stmt 0 view .LVU2836
+ 8158 004c 2023     		movs	r3, #32
+ 8159 004e 84F84230 		strb	r3, [r4, #66]
+3823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8160              		.loc 1 3823 5 is_stmt 1 view .LVU2837
+3823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8161              		.loc 1 3823 21 is_stmt 0 view .LVU2838
+ 8162 0052 0023     		movs	r3, #0
+ 8163 0054 6364     		str	r3, [r4, #68]
+3826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8164              		.loc 1 3826 5 is_stmt 1 view .LVU2839
+3826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8165              		.loc 1 3826 9 is_stmt 0 view .LVU2840
+ 8166 0056 2268     		ldr	r2, [r4]
+3826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8167              		.loc 1 3826 19 view .LVU2841
+ 8168 0058 5368     		ldr	r3, [r2, #4]
+3826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8169              		.loc 1 3826 25 view .LVU2842
+ 8170 005a 23F40043 		bic	r3, r3, #32768
+ 8171 005e 5360     		str	r3, [r2, #4]
+3829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 8172              		.loc 1 3829 5 is_stmt 1 view .LVU2843
+3829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 8173              		.loc 1 3829 23 is_stmt 0 view .LVU2844
+ 8174 0060 6762     		str	r7, [r4, #36]
+3830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 8175              		.loc 1 3830 5 is_stmt 1 view .LVU2845
+3830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 8176              		.loc 1 3830 23 is_stmt 0 view .LVU2846
+ 8177 0062 6685     		strh	r6, [r4, #42]	@ movhi
+ARM GAS  /tmp/ccbUHtu7.s 			page 312
+
+
+3831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8178              		.loc 1 3831 5 is_stmt 1 view .LVU2847
+3831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8179              		.loc 1 3831 29 is_stmt 0 view .LVU2848
+ 8180 0064 638D     		ldrh	r3, [r4, #42]
+3831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8181              		.loc 1 3831 23 view .LVU2849
+ 8182 0066 2385     		strh	r3, [r4, #40]	@ movhi
+3832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 8183              		.loc 1 3832 5 is_stmt 1 view .LVU2850
+3832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 8184              		.loc 1 3832 23 is_stmt 0 view .LVU2851
+ 8185 0068 E562     		str	r5, [r4, #44]
+3833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8186              		.loc 1 3833 5 is_stmt 1 view .LVU2852
+3833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8187              		.loc 1 3833 23 is_stmt 0 view .LVU2853
+ 8188 006a 194B     		ldr	r3, .L520
+ 8189 006c 6363     		str	r3, [r4, #52]
+3835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8190              		.loc 1 3835 5 is_stmt 1 view .LVU2854
+3835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8191              		.loc 1 3835 9 is_stmt 0 view .LVU2855
+ 8192 006e 2368     		ldr	r3, [r4]
+ 8193 0070 9A69     		ldr	r2, [r3, #24]
+3835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8194              		.loc 1 3835 8 view .LVU2856
+ 8195 0072 12F4803F 		tst	r2, #65536
+ 8196 0076 01D0     		beq	.L515
+3839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8197              		.loc 1 3839 7 is_stmt 1 view .LVU2857
+ 8198 0078 0822     		movs	r2, #8
+ 8199 007a DA61     		str	r2, [r3, #28]
+ 8200              	.L515:
+3843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8201              		.loc 1 3843 5 view .LVU2858
+3843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8202              		.loc 1 3843 5 view .LVU2859
+ 8203 007c 0025     		movs	r5, #0
+ 8204              	.LVL551:
+3843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8205              		.loc 1 3843 5 is_stmt 0 view .LVU2860
+ 8206 007e 84F84050 		strb	r5, [r4, #64]
+3843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8207              		.loc 1 3843 5 is_stmt 1 view .LVU2861
+3849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8208              		.loc 1 3849 5 view .LVU2862
+ 8209 0082 48F20101 		movw	r1, #32769
+ 8210 0086 2046     		mov	r0, r4
+ 8211 0088 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 8212              	.LVL552:
+3851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 8213              		.loc 1 3851 5 view .LVU2863
+3851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 8214              		.loc 1 3851 12 is_stmt 0 view .LVU2864
+ 8215 008c 2846     		mov	r0, r5
+ 8216 008e 1BE0     		b	.L511
+ARM GAS  /tmp/ccbUHtu7.s 			page 313
+
+
+ 8217              	.LVL553:
+ 8218              	.L519:
+3798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8219              		.loc 1 3798 7 is_stmt 1 view .LVU2865
+ 8220 0090 0221     		movs	r1, #2
+ 8221 0092 2046     		mov	r0, r4
+ 8222 0094 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 8223              	.LVL554:
+3801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8224              		.loc 1 3801 7 view .LVU2866
+3801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8225              		.loc 1 3801 16 is_stmt 0 view .LVU2867
+ 8226 0098 2368     		ldr	r3, [r4]
+3801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8227              		.loc 1 3801 26 view .LVU2868
+ 8228 009a 1A68     		ldr	r2, [r3]
+3801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8229              		.loc 1 3801 10 view .LVU2869
+ 8230 009c 12F4004F 		tst	r2, #32768
+ 8231 00a0 D1D0     		beq	.L514
+3803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8232              		.loc 1 3803 9 is_stmt 1 view .LVU2870
+3803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8233              		.loc 1 3803 23 is_stmt 0 view .LVU2871
+ 8234 00a2 1A68     		ldr	r2, [r3]
+3803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8235              		.loc 1 3803 29 view .LVU2872
+ 8236 00a4 22F40042 		bic	r2, r2, #32768
+ 8237 00a8 1A60     		str	r2, [r3]
+3805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 8238              		.loc 1 3805 9 is_stmt 1 view .LVU2873
+3805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 8239              		.loc 1 3805 17 is_stmt 0 view .LVU2874
+ 8240 00aa E36B     		ldr	r3, [r4, #60]
+3805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 8241              		.loc 1 3805 12 view .LVU2875
+ 8242 00ac 002B     		cmp	r3, #0
+ 8243 00ae CAD0     		beq	.L514
+3809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8244              		.loc 1 3809 11 is_stmt 1 view .LVU2876
+3809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8245              		.loc 1 3809 43 is_stmt 0 view .LVU2877
+ 8246 00b0 084A     		ldr	r2, .L520+4
+ 8247 00b2 9A63     		str	r2, [r3, #56]
+3812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 8248              		.loc 1 3812 11 is_stmt 1 view .LVU2878
+3812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 8249              		.loc 1 3812 15 is_stmt 0 view .LVU2879
+ 8250 00b4 E06B     		ldr	r0, [r4, #60]
+ 8251 00b6 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 8252              	.LVL555:
+3812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 8253              		.loc 1 3812 14 view .LVU2880
+ 8254 00ba 0028     		cmp	r0, #0
+ 8255 00bc C3D0     		beq	.L514
+3815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8256              		.loc 1 3815 13 is_stmt 1 view .LVU2881
+ARM GAS  /tmp/ccbUHtu7.s 			page 314
+
+
+3815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8257              		.loc 1 3815 17 is_stmt 0 view .LVU2882
+ 8258 00be E06B     		ldr	r0, [r4, #60]
+3815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8259              		.loc 1 3815 25 view .LVU2883
+ 8260 00c0 836B     		ldr	r3, [r0, #56]
+3815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8261              		.loc 1 3815 13 view .LVU2884
+ 8262 00c2 9847     		blx	r3
+ 8263              	.LVL556:
+ 8264 00c4 BFE7     		b	.L514
+ 8265              	.LVL557:
+ 8266              	.L516:
+3855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 8267              		.loc 1 3855 12 view .LVU2885
+ 8268 00c6 0120     		movs	r0, #1
+ 8269              	.LVL558:
+ 8270              	.L511:
+3857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8271              		.loc 1 3857 1 view .LVU2886
+ 8272 00c8 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 8273              	.LVL559:
+ 8274              	.L517:
+3791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8275              		.loc 1 3791 5 view .LVU2887
+ 8276 00ca 0220     		movs	r0, #2
+ 8277 00cc FCE7     		b	.L511
+ 8278              	.L521:
+ 8279 00ce 00BF     		.align	2
+ 8280              	.L520:
+ 8281 00d0 00000000 		.word	I2C_Slave_ISR_IT
+ 8282 00d4 00000000 		.word	I2C_DMAAbort
+ 8283              		.cfi_endproc
+ 8284              	.LFE356:
+ 8286              		.section	.text.HAL_I2C_Slave_Seq_Transmit_DMA,"ax",%progbits
+ 8287              		.align	1
+ 8288              		.global	HAL_I2C_Slave_Seq_Transmit_DMA
+ 8289              		.syntax unified
+ 8290              		.thumb
+ 8291              		.thumb_func
+ 8293              	HAL_I2C_Slave_Seq_Transmit_DMA:
+ 8294              	.LVL560:
+ 8295              	.LFB357:
+3871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 8296              		.loc 1 3871 1 is_stmt 1 view -0
+ 8297              		.cfi_startproc
+ 8298              		@ args = 0, pretend = 0, frame = 0
+ 8299              		@ frame_needed = 0, uses_anonymous_args = 0
+3871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 8300              		.loc 1 3871 1 is_stmt 0 view .LVU2889
+ 8301 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 8302              	.LCFI100:
+ 8303              		.cfi_def_cfa_offset 24
+ 8304              		.cfi_offset 3, -24
+ 8305              		.cfi_offset 4, -20
+ 8306              		.cfi_offset 5, -16
+ 8307              		.cfi_offset 6, -12
+ARM GAS  /tmp/ccbUHtu7.s 			page 315
+
+
+ 8308              		.cfi_offset 7, -8
+ 8309              		.cfi_offset 14, -4
+ 8310 0002 0446     		mov	r4, r0
+3872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8311              		.loc 1 3872 3 is_stmt 1 view .LVU2890
+3875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8312              		.loc 1 3875 3 view .LVU2891
+3877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 8313              		.loc 1 3877 3 view .LVU2892
+3877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 8314              		.loc 1 3877 22 is_stmt 0 view .LVU2893
+ 8315 0004 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 8316              	.LVL561:
+3877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 8317              		.loc 1 3877 6 view .LVU2894
+ 8318 0008 00F02800 		and	r0, r0, #40
+ 8319 000c 2828     		cmp	r0, #40
+ 8320 000e 40F0BB80 		bne	.L533
+ 8321 0012 0F46     		mov	r7, r1
+ 8322 0014 1646     		mov	r6, r2
+ 8323 0016 1D46     		mov	r5, r3
+3879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8324              		.loc 1 3879 5 is_stmt 1 view .LVU2895
+3879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8325              		.loc 1 3879 8 is_stmt 0 view .LVU2896
+ 8326 0018 0029     		cmp	r1, #0
+ 8327 001a 51D0     		beq	.L524
+3879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8328              		.loc 1 3879 25 discriminator 1 view .LVU2897
+ 8329 001c 002A     		cmp	r2, #0
+ 8330 001e 4FD0     		beq	.L524
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8331              		.loc 1 3886 5 is_stmt 1 view .LVU2898
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8332              		.loc 1 3886 5 view .LVU2899
+ 8333 0020 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 8334              	.LVL562:
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8335              		.loc 1 3886 5 is_stmt 0 view .LVU2900
+ 8336 0024 012B     		cmp	r3, #1
+ 8337 0026 00F0B280 		beq	.L534
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8338              		.loc 1 3886 5 is_stmt 1 discriminator 2 view .LVU2901
+ 8339 002a 0123     		movs	r3, #1
+ 8340 002c 84F84030 		strb	r3, [r4, #64]
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8341              		.loc 1 3886 5 discriminator 2 view .LVU2902
+3889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8342              		.loc 1 3889 5 discriminator 2 view .LVU2903
+ 8343 0030 48F20101 		movw	r1, #32769
+ 8344              	.LVL563:
+3889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8345              		.loc 1 3889 5 is_stmt 0 discriminator 2 view .LVU2904
+ 8346 0034 2046     		mov	r0, r4
+ 8347 0036 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 8348              	.LVL564:
+3893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccbUHtu7.s 			page 316
+
+
+ 8349              		.loc 1 3893 5 is_stmt 1 discriminator 2 view .LVU2905
+3893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8350              		.loc 1 3893 13 is_stmt 0 discriminator 2 view .LVU2906
+ 8351 003a 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 8352 003e DBB2     		uxtb	r3, r3
+3893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8353              		.loc 1 3893 8 discriminator 2 view .LVU2907
+ 8354 0040 2A2B     		cmp	r3, #42
+ 8355 0042 42D0     		beq	.L537
+3918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8356              		.loc 1 3918 10 is_stmt 1 view .LVU2908
+3918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8357              		.loc 1 3918 18 is_stmt 0 view .LVU2909
+ 8358 0044 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 8359 0048 DBB2     		uxtb	r3, r3
+3918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8360              		.loc 1 3918 13 view .LVU2910
+ 8361 004a 292B     		cmp	r3, #41
+ 8362 004c 59D0     		beq	.L538
+ 8363              	.L527:
+3943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8364              		.loc 1 3943 5 is_stmt 1 view .LVU2911
+3945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 8365              		.loc 1 3945 5 view .LVU2912
+3945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 8366              		.loc 1 3945 21 is_stmt 0 view .LVU2913
+ 8367 004e 2923     		movs	r3, #41
+ 8368 0050 84F84130 		strb	r3, [r4, #65]
+3946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8369              		.loc 1 3946 5 is_stmt 1 view .LVU2914
+3946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8370              		.loc 1 3946 21 is_stmt 0 view .LVU2915
+ 8371 0054 2023     		movs	r3, #32
+ 8372 0056 84F84230 		strb	r3, [r4, #66]
+3947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8373              		.loc 1 3947 5 is_stmt 1 view .LVU2916
+3947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8374              		.loc 1 3947 21 is_stmt 0 view .LVU2917
+ 8375 005a 0023     		movs	r3, #0
+ 8376 005c 6364     		str	r3, [r4, #68]
+3950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8377              		.loc 1 3950 5 is_stmt 1 view .LVU2918
+3950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8378              		.loc 1 3950 9 is_stmt 0 view .LVU2919
+ 8379 005e 2268     		ldr	r2, [r4]
+3950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8380              		.loc 1 3950 19 view .LVU2920
+ 8381 0060 5368     		ldr	r3, [r2, #4]
+3950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8382              		.loc 1 3950 25 view .LVU2921
+ 8383 0062 23F40043 		bic	r3, r3, #32768
+ 8384 0066 5360     		str	r3, [r2, #4]
+3953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 8385              		.loc 1 3953 5 is_stmt 1 view .LVU2922
+3953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 8386              		.loc 1 3953 23 is_stmt 0 view .LVU2923
+ 8387 0068 6762     		str	r7, [r4, #36]
+ARM GAS  /tmp/ccbUHtu7.s 			page 317
+
+
+3954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 8388              		.loc 1 3954 5 is_stmt 1 view .LVU2924
+3954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 8389              		.loc 1 3954 23 is_stmt 0 view .LVU2925
+ 8390 006a 6685     		strh	r6, [r4, #42]	@ movhi
+3955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8391              		.loc 1 3955 5 is_stmt 1 view .LVU2926
+3955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8392              		.loc 1 3955 29 is_stmt 0 view .LVU2927
+ 8393 006c 638D     		ldrh	r3, [r4, #42]
+3955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8394              		.loc 1 3955 23 view .LVU2928
+ 8395 006e 2385     		strh	r3, [r4, #40]	@ movhi
+3956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 8396              		.loc 1 3956 5 is_stmt 1 view .LVU2929
+3956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 8397              		.loc 1 3956 23 is_stmt 0 view .LVU2930
+ 8398 0070 E562     		str	r5, [r4, #44]
+3957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8399              		.loc 1 3957 5 is_stmt 1 view .LVU2931
+3957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8400              		.loc 1 3957 23 is_stmt 0 view .LVU2932
+ 8401 0072 484B     		ldr	r3, .L539
+ 8402 0074 6363     		str	r3, [r4, #52]
+3959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8403              		.loc 1 3959 5 is_stmt 1 view .LVU2933
+3959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8404              		.loc 1 3959 13 is_stmt 0 view .LVU2934
+ 8405 0076 A36B     		ldr	r3, [r4, #56]
+3959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8406              		.loc 1 3959 8 view .LVU2935
+ 8407 0078 002B     		cmp	r3, #0
+ 8408 007a 59D0     		beq	.L528
+3962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8409              		.loc 1 3962 7 is_stmt 1 view .LVU2936
+3962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8410              		.loc 1 3962 38 is_stmt 0 view .LVU2937
+ 8411 007c 464A     		ldr	r2, .L539+4
+ 8412 007e DA62     		str	r2, [r3, #44]
+3965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8413              		.loc 1 3965 7 is_stmt 1 view .LVU2938
+3965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8414              		.loc 1 3965 11 is_stmt 0 view .LVU2939
+ 8415 0080 A36B     		ldr	r3, [r4, #56]
+3965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8416              		.loc 1 3965 39 view .LVU2940
+ 8417 0082 464A     		ldr	r2, .L539+8
+ 8418 0084 5A63     		str	r2, [r3, #52]
+3968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 8419              		.loc 1 3968 7 is_stmt 1 view .LVU2941
+3968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 8420              		.loc 1 3968 11 is_stmt 0 view .LVU2942
+ 8421 0086 A26B     		ldr	r2, [r4, #56]
+3968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 8422              		.loc 1 3968 42 view .LVU2943
+ 8423 0088 0023     		movs	r3, #0
+ 8424 008a 1363     		str	r3, [r2, #48]
+ARM GAS  /tmp/ccbUHtu7.s 			page 318
+
+
+3969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8425              		.loc 1 3969 7 is_stmt 1 view .LVU2944
+3969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8426              		.loc 1 3969 11 is_stmt 0 view .LVU2945
+ 8427 008c A26B     		ldr	r2, [r4, #56]
+3969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8428              		.loc 1 3969 39 view .LVU2946
+ 8429 008e 9363     		str	r3, [r2, #56]
+3972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 8430              		.loc 1 3972 7 is_stmt 1 view .LVU2947
+3972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 8431              		.loc 1 3972 86 is_stmt 0 view .LVU2948
+ 8432 0090 2268     		ldr	r2, [r4]
+3972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 8433              		.loc 1 3972 23 view .LVU2949
+ 8434 0092 238D     		ldrh	r3, [r4, #40]
+ 8435 0094 2832     		adds	r2, r2, #40
+ 8436 0096 3946     		mov	r1, r7
+ 8437 0098 A06B     		ldr	r0, [r4, #56]
+ 8438 009a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 8439              	.LVL565:
+3990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8440              		.loc 1 3990 5 is_stmt 1 view .LVU2950
+3990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8441              		.loc 1 3990 8 is_stmt 0 view .LVU2951
+ 8442 009e 0546     		mov	r5, r0
+ 8443              	.LVL566:
+3990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8444              		.loc 1 3990 8 view .LVU2952
+ 8445 00a0 0028     		cmp	r0, #0
+ 8446 00a2 53D0     		beq	.L529
+4001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 8447              		.loc 1 4001 7 is_stmt 1 view .LVU2953
+4001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 8448              		.loc 1 4001 23 is_stmt 0 view .LVU2954
+ 8449 00a4 2823     		movs	r3, #40
+ 8450 00a6 84F84130 		strb	r3, [r4, #65]
+4002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8451              		.loc 1 4002 7 is_stmt 1 view .LVU2955
+4002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8452              		.loc 1 4002 23 is_stmt 0 view .LVU2956
+ 8453 00aa 0022     		movs	r2, #0
+ 8454 00ac 84F84220 		strb	r2, [r4, #66]
+4005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8455              		.loc 1 4005 7 is_stmt 1 view .LVU2957
+4005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8456              		.loc 1 4005 11 is_stmt 0 view .LVU2958
+ 8457 00b0 636C     		ldr	r3, [r4, #68]
+4005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8458              		.loc 1 4005 23 view .LVU2959
+ 8459 00b2 43F01003 		orr	r3, r3, #16
+ 8460 00b6 6364     		str	r3, [r4, #68]
+4008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8461              		.loc 1 4008 7 is_stmt 1 view .LVU2960
+4008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8462              		.loc 1 4008 7 view .LVU2961
+ 8463 00b8 84F84020 		strb	r2, [r4, #64]
+ARM GAS  /tmp/ccbUHtu7.s 			page 319
+
+
+4008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8464              		.loc 1 4008 7 view .LVU2962
+4010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8465              		.loc 1 4010 7 view .LVU2963
+4010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8466              		.loc 1 4010 14 is_stmt 0 view .LVU2964
+ 8467 00bc 0125     		movs	r5, #1
+ 8468 00be 64E0     		b	.L523
+ 8469              	.LVL567:
+ 8470              	.L524:
+3881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8471              		.loc 1 3881 7 is_stmt 1 view .LVU2965
+3881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8472              		.loc 1 3881 23 is_stmt 0 view .LVU2966
+ 8473 00c0 4FF40073 		mov	r3, #512
+ 8474              	.LVL568:
+3881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8475              		.loc 1 3881 23 view .LVU2967
+ 8476 00c4 6364     		str	r3, [r4, #68]
+3882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8477              		.loc 1 3882 7 is_stmt 1 view .LVU2968
+3882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8478              		.loc 1 3882 15 is_stmt 0 view .LVU2969
+ 8479 00c6 0125     		movs	r5, #1
+ 8480              	.LVL569:
+3882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8481              		.loc 1 3882 15 view .LVU2970
+ 8482 00c8 5FE0     		b	.L523
+ 8483              	.LVL570:
+ 8484              	.L537:
+3896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8485              		.loc 1 3896 7 is_stmt 1 view .LVU2971
+ 8486 00ca 0221     		movs	r1, #2
+ 8487 00cc 2046     		mov	r0, r4
+ 8488 00ce FFF7FEFF 		bl	I2C_Disable_IRQ
+ 8489              	.LVL571:
+3898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8490              		.loc 1 3898 7 view .LVU2972
+3898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8491              		.loc 1 3898 16 is_stmt 0 view .LVU2973
+ 8492 00d2 2368     		ldr	r3, [r4]
+3898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8493              		.loc 1 3898 26 view .LVU2974
+ 8494 00d4 1A68     		ldr	r2, [r3]
+3898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8495              		.loc 1 3898 10 view .LVU2975
+ 8496 00d6 12F4004F 		tst	r2, #32768
+ 8497 00da B8D0     		beq	.L527
+3901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 8498              		.loc 1 3901 9 is_stmt 1 view .LVU2976
+3901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 8499              		.loc 1 3901 17 is_stmt 0 view .LVU2977
+ 8500 00dc E26B     		ldr	r2, [r4, #60]
+3901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 8501              		.loc 1 3901 12 view .LVU2978
+ 8502 00de 002A     		cmp	r2, #0
+ 8503 00e0 B5D0     		beq	.L527
+ARM GAS  /tmp/ccbUHtu7.s 			page 320
+
+
+3903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8504              		.loc 1 3903 11 is_stmt 1 view .LVU2979
+3903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8505              		.loc 1 3903 25 is_stmt 0 view .LVU2980
+ 8506 00e2 1A68     		ldr	r2, [r3]
+3903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8507              		.loc 1 3903 31 view .LVU2981
+ 8508 00e4 22F40042 		bic	r2, r2, #32768
+ 8509 00e8 1A60     		str	r2, [r3]
+3907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8510              		.loc 1 3907 11 is_stmt 1 view .LVU2982
+3907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8511              		.loc 1 3907 15 is_stmt 0 view .LVU2983
+ 8512 00ea E36B     		ldr	r3, [r4, #60]
+3907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8513              		.loc 1 3907 43 view .LVU2984
+ 8514 00ec 2C4A     		ldr	r2, .L539+12
+ 8515 00ee 9A63     		str	r2, [r3, #56]
+3910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 8516              		.loc 1 3910 11 is_stmt 1 view .LVU2985
+3910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 8517              		.loc 1 3910 15 is_stmt 0 view .LVU2986
+ 8518 00f0 E06B     		ldr	r0, [r4, #60]
+ 8519 00f2 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 8520              	.LVL572:
+3910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 8521              		.loc 1 3910 14 view .LVU2987
+ 8522 00f6 0028     		cmp	r0, #0
+ 8523 00f8 A9D0     		beq	.L527
+3913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8524              		.loc 1 3913 13 is_stmt 1 view .LVU2988
+3913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8525              		.loc 1 3913 17 is_stmt 0 view .LVU2989
+ 8526 00fa E06B     		ldr	r0, [r4, #60]
+3913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8527              		.loc 1 3913 25 view .LVU2990
+ 8528 00fc 836B     		ldr	r3, [r0, #56]
+3913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8529              		.loc 1 3913 13 view .LVU2991
+ 8530 00fe 9847     		blx	r3
+ 8531              	.LVL573:
+ 8532 0100 A5E7     		b	.L527
+ 8533              	.L538:
+3920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8534              		.loc 1 3920 7 is_stmt 1 view .LVU2992
+3920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8535              		.loc 1 3920 16 is_stmt 0 view .LVU2993
+ 8536 0102 2368     		ldr	r3, [r4]
+3920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8537              		.loc 1 3920 26 view .LVU2994
+ 8538 0104 1A68     		ldr	r2, [r3]
+3920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8539              		.loc 1 3920 10 view .LVU2995
+ 8540 0106 12F4804F 		tst	r2, #16384
+ 8541 010a A0D0     		beq	.L527
+3922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8542              		.loc 1 3922 9 is_stmt 1 view .LVU2996
+ARM GAS  /tmp/ccbUHtu7.s 			page 321
+
+
+3922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8543              		.loc 1 3922 23 is_stmt 0 view .LVU2997
+ 8544 010c 1A68     		ldr	r2, [r3]
+3922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8545              		.loc 1 3922 29 view .LVU2998
+ 8546 010e 22F48042 		bic	r2, r2, #16384
+ 8547 0112 1A60     		str	r2, [r3]
+3925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 8548              		.loc 1 3925 9 is_stmt 1 view .LVU2999
+3925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 8549              		.loc 1 3925 17 is_stmt 0 view .LVU3000
+ 8550 0114 A36B     		ldr	r3, [r4, #56]
+3925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 8551              		.loc 1 3925 12 view .LVU3001
+ 8552 0116 002B     		cmp	r3, #0
+ 8553 0118 99D0     		beq	.L527
+3929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8554              		.loc 1 3929 11 is_stmt 1 view .LVU3002
+3929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8555              		.loc 1 3929 43 is_stmt 0 view .LVU3003
+ 8556 011a 214A     		ldr	r2, .L539+12
+ 8557 011c 9A63     		str	r2, [r3, #56]
+3932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 8558              		.loc 1 3932 11 is_stmt 1 view .LVU3004
+3932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 8559              		.loc 1 3932 15 is_stmt 0 view .LVU3005
+ 8560 011e A06B     		ldr	r0, [r4, #56]
+ 8561 0120 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 8562              	.LVL574:
+3932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 8563              		.loc 1 3932 14 view .LVU3006
+ 8564 0124 0028     		cmp	r0, #0
+ 8565 0126 92D0     		beq	.L527
+3935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8566              		.loc 1 3935 13 is_stmt 1 view .LVU3007
+3935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8567              		.loc 1 3935 17 is_stmt 0 view .LVU3008
+ 8568 0128 A06B     		ldr	r0, [r4, #56]
+3935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8569              		.loc 1 3935 25 view .LVU3009
+ 8570 012a 836B     		ldr	r3, [r0, #56]
+3935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8571              		.loc 1 3935 13 view .LVU3010
+ 8572 012c 9847     		blx	r3
+ 8573              	.LVL575:
+ 8574 012e 8EE7     		b	.L527
+ 8575              	.L528:
+3978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 8576              		.loc 1 3978 7 is_stmt 1 view .LVU3011
+3978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 8577              		.loc 1 3978 23 is_stmt 0 view .LVU3012
+ 8578 0130 2823     		movs	r3, #40
+ 8579 0132 84F84130 		strb	r3, [r4, #65]
+3979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8580              		.loc 1 3979 7 is_stmt 1 view .LVU3013
+3979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8581              		.loc 1 3979 23 is_stmt 0 view .LVU3014
+ARM GAS  /tmp/ccbUHtu7.s 			page 322
+
+
+ 8582 0136 0022     		movs	r2, #0
+ 8583 0138 84F84220 		strb	r2, [r4, #66]
+3982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8584              		.loc 1 3982 7 is_stmt 1 view .LVU3015
+3982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8585              		.loc 1 3982 11 is_stmt 0 view .LVU3016
+ 8586 013c 636C     		ldr	r3, [r4, #68]
+3982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8587              		.loc 1 3982 23 view .LVU3017
+ 8588 013e 43F08003 		orr	r3, r3, #128
+ 8589 0142 6364     		str	r3, [r4, #68]
+3985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8590              		.loc 1 3985 7 is_stmt 1 view .LVU3018
+3985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8591              		.loc 1 3985 7 view .LVU3019
+ 8592 0144 84F84020 		strb	r2, [r4, #64]
+3985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8593              		.loc 1 3985 7 view .LVU3020
+3987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8594              		.loc 1 3987 7 view .LVU3021
+3987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8595              		.loc 1 3987 14 is_stmt 0 view .LVU3022
+ 8596 0148 0125     		movs	r5, #1
+ 8597              	.LVL576:
+3987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8598              		.loc 1 3987 14 view .LVU3023
+ 8599 014a 1EE0     		b	.L523
+ 8600              	.LVL577:
+ 8601              	.L529:
+3993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8602              		.loc 1 3993 7 is_stmt 1 view .LVU3024
+3993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8603              		.loc 1 3993 11 is_stmt 0 view .LVU3025
+ 8604 014c 638D     		ldrh	r3, [r4, #42]
+ 8605 014e 9BB2     		uxth	r3, r3
+3993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8606              		.loc 1 3993 30 view .LVU3026
+ 8607 0150 228D     		ldrh	r2, [r4, #40]
+3993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8608              		.loc 1 3993 23 view .LVU3027
+ 8609 0152 9B1A     		subs	r3, r3, r2
+ 8610 0154 9BB2     		uxth	r3, r3
+ 8611 0156 6385     		strh	r3, [r4, #42]	@ movhi
+3996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8612              		.loc 1 3996 7 is_stmt 1 view .LVU3028
+3996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8613              		.loc 1 3996 22 is_stmt 0 view .LVU3029
+ 8614 0158 0023     		movs	r3, #0
+ 8615 015a 2385     		strh	r3, [r4, #40]	@ movhi
+4013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8616              		.loc 1 4013 5 is_stmt 1 view .LVU3030
+4013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8617              		.loc 1 4013 9 is_stmt 0 view .LVU3031
+ 8618 015c 2368     		ldr	r3, [r4]
+ 8619 015e 9A69     		ldr	r2, [r3, #24]
+4013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8620              		.loc 1 4013 8 view .LVU3032
+ARM GAS  /tmp/ccbUHtu7.s 			page 323
+
+
+ 8621 0160 12F4803F 		tst	r2, #65536
+ 8622 0164 0DD1     		bne	.L531
+ 8623              	.L532:
+4021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8624              		.loc 1 4021 5 is_stmt 1 view .LVU3033
+4021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8625              		.loc 1 4021 5 view .LVU3034
+ 8626 0166 0023     		movs	r3, #0
+ 8627 0168 84F84030 		strb	r3, [r4, #64]
+4021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8628              		.loc 1 4021 5 view .LVU3035
+4024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8629              		.loc 1 4024 5 view .LVU3036
+4024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8630              		.loc 1 4024 9 is_stmt 0 view .LVU3037
+ 8631 016c 2268     		ldr	r2, [r4]
+4024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8632              		.loc 1 4024 19 view .LVU3038
+ 8633 016e 1368     		ldr	r3, [r2]
+4024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8634              		.loc 1 4024 25 view .LVU3039
+ 8635 0170 43F48043 		orr	r3, r3, #16384
+ 8636 0174 1360     		str	r3, [r2]
+4030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8637              		.loc 1 4030 5 is_stmt 1 view .LVU3040
+ 8638 0176 4FF40041 		mov	r1, #32768
+ 8639 017a 2046     		mov	r0, r4
+ 8640              	.LVL578:
+4030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8641              		.loc 1 4030 5 is_stmt 0 view .LVU3041
+ 8642 017c FFF7FEFF 		bl	I2C_Enable_IRQ
+ 8643              	.LVL579:
+4032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 8644              		.loc 1 4032 5 is_stmt 1 view .LVU3042
+4032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 8645              		.loc 1 4032 12 is_stmt 0 view .LVU3043
+ 8646 0180 03E0     		b	.L523
+ 8647              	.LVL580:
+ 8648              	.L531:
+4017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8649              		.loc 1 4017 7 is_stmt 1 view .LVU3044
+ 8650 0182 0822     		movs	r2, #8
+ 8651 0184 DA61     		str	r2, [r3, #28]
+ 8652 0186 EEE7     		b	.L532
+ 8653              	.LVL581:
+ 8654              	.L533:
+4036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 8655              		.loc 1 4036 12 is_stmt 0 view .LVU3045
+ 8656 0188 0125     		movs	r5, #1
+ 8657              	.LVL582:
+ 8658              	.L523:
+4038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8659              		.loc 1 4038 1 view .LVU3046
+ 8660 018a 2846     		mov	r0, r5
+ 8661 018c F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 8662              	.LVL583:
+ 8663              	.L534:
+ARM GAS  /tmp/ccbUHtu7.s 			page 324
+
+
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8664              		.loc 1 3886 5 view .LVU3047
+ 8665 018e 0225     		movs	r5, #2
+ 8666              	.LVL584:
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8667              		.loc 1 3886 5 view .LVU3048
+ 8668 0190 FBE7     		b	.L523
+ 8669              	.L540:
+ 8670 0192 00BF     		.align	2
+ 8671              	.L539:
+ 8672 0194 00000000 		.word	I2C_Slave_ISR_DMA
+ 8673 0198 00000000 		.word	I2C_DMASlaveTransmitCplt
+ 8674 019c 00000000 		.word	I2C_DMAError
+ 8675 01a0 00000000 		.word	I2C_DMAAbort
+ 8676              		.cfi_endproc
+ 8677              	.LFE357:
+ 8679              		.section	.text.HAL_I2C_Slave_Seq_Receive_IT,"ax",%progbits
+ 8680              		.align	1
+ 8681              		.global	HAL_I2C_Slave_Seq_Receive_IT
+ 8682              		.syntax unified
+ 8683              		.thumb
+ 8684              		.thumb_func
+ 8686              	HAL_I2C_Slave_Seq_Receive_IT:
+ 8687              	.LVL585:
+ 8688              	.LFB358:
+4052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+ 8689              		.loc 1 4052 1 is_stmt 1 view -0
+ 8690              		.cfi_startproc
+ 8691              		@ args = 0, pretend = 0, frame = 0
+ 8692              		@ frame_needed = 0, uses_anonymous_args = 0
+4052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Check the parameters */
+ 8693              		.loc 1 4052 1 is_stmt 0 view .LVU3050
+ 8694 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 8695              	.LCFI101:
+ 8696              		.cfi_def_cfa_offset 24
+ 8697              		.cfi_offset 3, -24
+ 8698              		.cfi_offset 4, -20
+ 8699              		.cfi_offset 5, -16
+ 8700              		.cfi_offset 6, -12
+ 8701              		.cfi_offset 7, -8
+ 8702              		.cfi_offset 14, -4
+ 8703 0002 0446     		mov	r4, r0
+4054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8704              		.loc 1 4054 3 is_stmt 1 view .LVU3051
+4056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 8705              		.loc 1 4056 3 view .LVU3052
+4056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 8706              		.loc 1 4056 22 is_stmt 0 view .LVU3053
+ 8707 0004 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 8708              	.LVL586:
+4056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 8709              		.loc 1 4056 6 view .LVU3054
+ 8710 0008 00F02800 		and	r0, r0, #40
+ 8711 000c 2828     		cmp	r0, #40
+ 8712 000e 5AD1     		bne	.L547
+ 8713 0010 0F46     		mov	r7, r1
+ 8714 0012 1646     		mov	r6, r2
+ARM GAS  /tmp/ccbUHtu7.s 			page 325
+
+
+ 8715 0014 1D46     		mov	r5, r3
+4058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8716              		.loc 1 4058 5 is_stmt 1 view .LVU3055
+4058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8717              		.loc 1 4058 8 is_stmt 0 view .LVU3056
+ 8718 0016 01B1     		cbz	r1, .L543
+4058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8719              		.loc 1 4058 25 discriminator 1 view .LVU3057
+ 8720 0018 22B9     		cbnz	r2, .L544
+ 8721              	.L543:
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8722              		.loc 1 4060 7 is_stmt 1 view .LVU3058
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8723              		.loc 1 4060 23 is_stmt 0 view .LVU3059
+ 8724 001a 4FF40073 		mov	r3, #512
+ 8725              	.LVL587:
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8726              		.loc 1 4060 23 view .LVU3060
+ 8727 001e 6364     		str	r3, [r4, #68]
+4061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8728              		.loc 1 4061 7 is_stmt 1 view .LVU3061
+4061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8729              		.loc 1 4061 15 is_stmt 0 view .LVU3062
+ 8730 0020 0120     		movs	r0, #1
+ 8731 0022 51E0     		b	.L542
+ 8732              	.LVL588:
+ 8733              	.L544:
+4065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8734              		.loc 1 4065 5 is_stmt 1 view .LVU3063
+ 8735 0024 48F20201 		movw	r1, #32770
+ 8736              	.LVL589:
+4065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8737              		.loc 1 4065 5 is_stmt 0 view .LVU3064
+ 8738 0028 2046     		mov	r0, r4
+ 8739 002a FFF7FEFF 		bl	I2C_Disable_IRQ
+ 8740              	.LVL590:
+4068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8741              		.loc 1 4068 5 is_stmt 1 view .LVU3065
+4068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8742              		.loc 1 4068 5 view .LVU3066
+ 8743 002e 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 8744 0032 012B     		cmp	r3, #1
+ 8745 0034 49D0     		beq	.L548
+4068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8746              		.loc 1 4068 5 discriminator 2 view .LVU3067
+ 8747 0036 0123     		movs	r3, #1
+ 8748 0038 84F84030 		strb	r3, [r4, #64]
+4068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8749              		.loc 1 4068 5 discriminator 2 view .LVU3068
+4072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8750              		.loc 1 4072 5 discriminator 2 view .LVU3069
+4072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8751              		.loc 1 4072 13 is_stmt 0 discriminator 2 view .LVU3070
+ 8752 003c 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 8753 0040 DBB2     		uxtb	r3, r3
+4072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8754              		.loc 1 4072 8 discriminator 2 view .LVU3071
+ARM GAS  /tmp/ccbUHtu7.s 			page 326
+
+
+ 8755 0042 292B     		cmp	r3, #41
+ 8756 0044 24D0     		beq	.L550
+ 8757              	.L545:
+4098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 8758              		.loc 1 4098 5 is_stmt 1 view .LVU3072
+4098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 8759              		.loc 1 4098 21 is_stmt 0 view .LVU3073
+ 8760 0046 2A23     		movs	r3, #42
+ 8761 0048 84F84130 		strb	r3, [r4, #65]
+4099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8762              		.loc 1 4099 5 is_stmt 1 view .LVU3074
+4099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8763              		.loc 1 4099 21 is_stmt 0 view .LVU3075
+ 8764 004c 2023     		movs	r3, #32
+ 8765 004e 84F84230 		strb	r3, [r4, #66]
+4100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8766              		.loc 1 4100 5 is_stmt 1 view .LVU3076
+4100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8767              		.loc 1 4100 21 is_stmt 0 view .LVU3077
+ 8768 0052 0023     		movs	r3, #0
+ 8769 0054 6364     		str	r3, [r4, #68]
+4103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8770              		.loc 1 4103 5 is_stmt 1 view .LVU3078
+4103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8771              		.loc 1 4103 9 is_stmt 0 view .LVU3079
+ 8772 0056 2268     		ldr	r2, [r4]
+4103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8773              		.loc 1 4103 19 view .LVU3080
+ 8774 0058 5368     		ldr	r3, [r2, #4]
+4103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8775              		.loc 1 4103 25 view .LVU3081
+ 8776 005a 23F40043 		bic	r3, r3, #32768
+ 8777 005e 5360     		str	r3, [r2, #4]
+4106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 8778              		.loc 1 4106 5 is_stmt 1 view .LVU3082
+4106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 8779              		.loc 1 4106 23 is_stmt 0 view .LVU3083
+ 8780 0060 6762     		str	r7, [r4, #36]
+4107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 8781              		.loc 1 4107 5 is_stmt 1 view .LVU3084
+4107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 8782              		.loc 1 4107 23 is_stmt 0 view .LVU3085
+ 8783 0062 6685     		strh	r6, [r4, #42]	@ movhi
+4108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8784              		.loc 1 4108 5 is_stmt 1 view .LVU3086
+4108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8785              		.loc 1 4108 29 is_stmt 0 view .LVU3087
+ 8786 0064 638D     		ldrh	r3, [r4, #42]
+4108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8787              		.loc 1 4108 23 view .LVU3088
+ 8788 0066 2385     		strh	r3, [r4, #40]	@ movhi
+4109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 8789              		.loc 1 4109 5 is_stmt 1 view .LVU3089
+4109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 8790              		.loc 1 4109 23 is_stmt 0 view .LVU3090
+ 8791 0068 E562     		str	r5, [r4, #44]
+4110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 327
+
+
+ 8792              		.loc 1 4110 5 is_stmt 1 view .LVU3091
+4110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8793              		.loc 1 4110 23 is_stmt 0 view .LVU3092
+ 8794 006a 194B     		ldr	r3, .L551
+ 8795 006c 6363     		str	r3, [r4, #52]
+4112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8796              		.loc 1 4112 5 is_stmt 1 view .LVU3093
+4112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8797              		.loc 1 4112 9 is_stmt 0 view .LVU3094
+ 8798 006e 2368     		ldr	r3, [r4]
+ 8799 0070 9A69     		ldr	r2, [r3, #24]
+4112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8800              		.loc 1 4112 8 view .LVU3095
+ 8801 0072 12F4803F 		tst	r2, #65536
+ 8802 0076 01D1     		bne	.L546
+4116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8803              		.loc 1 4116 7 is_stmt 1 view .LVU3096
+ 8804 0078 0822     		movs	r2, #8
+ 8805 007a DA61     		str	r2, [r3, #28]
+ 8806              	.L546:
+4120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8807              		.loc 1 4120 5 view .LVU3097
+4120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8808              		.loc 1 4120 5 view .LVU3098
+ 8809 007c 0025     		movs	r5, #0
+ 8810              	.LVL591:
+4120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8811              		.loc 1 4120 5 is_stmt 0 view .LVU3099
+ 8812 007e 84F84050 		strb	r5, [r4, #64]
+4120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8813              		.loc 1 4120 5 is_stmt 1 view .LVU3100
+4126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8814              		.loc 1 4126 5 view .LVU3101
+ 8815 0082 48F20201 		movw	r1, #32770
+ 8816 0086 2046     		mov	r0, r4
+ 8817 0088 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 8818              	.LVL592:
+4128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 8819              		.loc 1 4128 5 view .LVU3102
+4128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 8820              		.loc 1 4128 12 is_stmt 0 view .LVU3103
+ 8821 008c 2846     		mov	r0, r5
+ 8822 008e 1BE0     		b	.L542
+ 8823              	.LVL593:
+ 8824              	.L550:
+4075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8825              		.loc 1 4075 7 is_stmt 1 view .LVU3104
+ 8826 0090 0121     		movs	r1, #1
+ 8827 0092 2046     		mov	r0, r4
+ 8828 0094 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 8829              	.LVL594:
+4077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8830              		.loc 1 4077 7 view .LVU3105
+4077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8831              		.loc 1 4077 16 is_stmt 0 view .LVU3106
+ 8832 0098 2368     		ldr	r3, [r4]
+4077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ARM GAS  /tmp/ccbUHtu7.s 			page 328
+
+
+ 8833              		.loc 1 4077 26 view .LVU3107
+ 8834 009a 1A68     		ldr	r2, [r3]
+4077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 8835              		.loc 1 4077 10 view .LVU3108
+ 8836 009c 12F4804F 		tst	r2, #16384
+ 8837 00a0 D1D0     		beq	.L545
+4079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8838              		.loc 1 4079 9 is_stmt 1 view .LVU3109
+4079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8839              		.loc 1 4079 23 is_stmt 0 view .LVU3110
+ 8840 00a2 1A68     		ldr	r2, [r3]
+4079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8841              		.loc 1 4079 29 view .LVU3111
+ 8842 00a4 22F48042 		bic	r2, r2, #16384
+ 8843 00a8 1A60     		str	r2, [r3]
+4082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 8844              		.loc 1 4082 9 is_stmt 1 view .LVU3112
+4082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 8845              		.loc 1 4082 17 is_stmt 0 view .LVU3113
+ 8846 00aa A36B     		ldr	r3, [r4, #56]
+4082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 8847              		.loc 1 4082 12 view .LVU3114
+ 8848 00ac 002B     		cmp	r3, #0
+ 8849 00ae CAD0     		beq	.L545
+4086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8850              		.loc 1 4086 11 is_stmt 1 view .LVU3115
+4086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8851              		.loc 1 4086 43 is_stmt 0 view .LVU3116
+ 8852 00b0 084A     		ldr	r2, .L551+4
+ 8853 00b2 9A63     		str	r2, [r3, #56]
+4089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 8854              		.loc 1 4089 11 is_stmt 1 view .LVU3117
+4089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 8855              		.loc 1 4089 15 is_stmt 0 view .LVU3118
+ 8856 00b4 A06B     		ldr	r0, [r4, #56]
+ 8857 00b6 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 8858              	.LVL595:
+4089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 8859              		.loc 1 4089 14 view .LVU3119
+ 8860 00ba 0028     		cmp	r0, #0
+ 8861 00bc C3D0     		beq	.L545
+4092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8862              		.loc 1 4092 13 is_stmt 1 view .LVU3120
+4092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8863              		.loc 1 4092 17 is_stmt 0 view .LVU3121
+ 8864 00be A06B     		ldr	r0, [r4, #56]
+4092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8865              		.loc 1 4092 25 view .LVU3122
+ 8866 00c0 836B     		ldr	r3, [r0, #56]
+4092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 8867              		.loc 1 4092 13 view .LVU3123
+ 8868 00c2 9847     		blx	r3
+ 8869              	.LVL596:
+ 8870 00c4 BFE7     		b	.L545
+ 8871              	.LVL597:
+ 8872              	.L547:
+4132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccbUHtu7.s 			page 329
+
+
+ 8873              		.loc 1 4132 12 view .LVU3124
+ 8874 00c6 0120     		movs	r0, #1
+ 8875              	.LVL598:
+ 8876              	.L542:
+4134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8877              		.loc 1 4134 1 view .LVU3125
+ 8878 00c8 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 8879              	.LVL599:
+ 8880              	.L548:
+4068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8881              		.loc 1 4068 5 view .LVU3126
+ 8882 00ca 0220     		movs	r0, #2
+ 8883 00cc FCE7     		b	.L542
+ 8884              	.L552:
+ 8885 00ce 00BF     		.align	2
+ 8886              	.L551:
+ 8887 00d0 00000000 		.word	I2C_Slave_ISR_IT
+ 8888 00d4 00000000 		.word	I2C_DMAAbort
+ 8889              		.cfi_endproc
+ 8890              	.LFE358:
+ 8892              		.section	.text.HAL_I2C_Slave_Seq_Receive_DMA,"ax",%progbits
+ 8893              		.align	1
+ 8894              		.global	HAL_I2C_Slave_Seq_Receive_DMA
+ 8895              		.syntax unified
+ 8896              		.thumb
+ 8897              		.thumb_func
+ 8899              	HAL_I2C_Slave_Seq_Receive_DMA:
+ 8900              	.LVL600:
+ 8901              	.LFB359:
+4148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 8902              		.loc 1 4148 1 is_stmt 1 view -0
+ 8903              		.cfi_startproc
+ 8904              		@ args = 0, pretend = 0, frame = 0
+ 8905              		@ frame_needed = 0, uses_anonymous_args = 0
+4148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 8906              		.loc 1 4148 1 is_stmt 0 view .LVU3128
+ 8907 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 8908              	.LCFI102:
+ 8909              		.cfi_def_cfa_offset 24
+ 8910              		.cfi_offset 3, -24
+ 8911              		.cfi_offset 4, -20
+ 8912              		.cfi_offset 5, -16
+ 8913              		.cfi_offset 6, -12
+ 8914              		.cfi_offset 7, -8
+ 8915              		.cfi_offset 14, -4
+ 8916 0002 0446     		mov	r4, r0
+4149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8917              		.loc 1 4149 3 is_stmt 1 view .LVU3129
+4152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8918              		.loc 1 4152 3 view .LVU3130
+4154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 8919              		.loc 1 4154 3 view .LVU3131
+4154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 8920              		.loc 1 4154 22 is_stmt 0 view .LVU3132
+ 8921 0004 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 8922              	.LVL601:
+4154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 330
+
+
+ 8923              		.loc 1 4154 6 view .LVU3133
+ 8924 0008 00F02800 		and	r0, r0, #40
+ 8925 000c 2828     		cmp	r0, #40
+ 8926 000e 40F0B980 		bne	.L564
+ 8927 0012 0F46     		mov	r7, r1
+ 8928 0014 1646     		mov	r6, r2
+ 8929 0016 1D46     		mov	r5, r3
+4156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8930              		.loc 1 4156 5 is_stmt 1 view .LVU3134
+4156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8931              		.loc 1 4156 8 is_stmt 0 view .LVU3135
+ 8932 0018 01B1     		cbz	r1, .L555
+4156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8933              		.loc 1 4156 25 discriminator 1 view .LVU3136
+ 8934 001a 22B9     		cbnz	r2, .L556
+ 8935              	.L555:
+4158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8936              		.loc 1 4158 7 is_stmt 1 view .LVU3137
+4158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8937              		.loc 1 4158 23 is_stmt 0 view .LVU3138
+ 8938 001c 4FF40073 		mov	r3, #512
+ 8939              	.LVL602:
+4158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8940              		.loc 1 4158 23 view .LVU3139
+ 8941 0020 6364     		str	r3, [r4, #68]
+4159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8942              		.loc 1 4159 7 is_stmt 1 view .LVU3140
+4159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8943              		.loc 1 4159 15 is_stmt 0 view .LVU3141
+ 8944 0022 0125     		movs	r5, #1
+ 8945              	.LVL603:
+4159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 8946              		.loc 1 4159 15 view .LVU3142
+ 8947 0024 AFE0     		b	.L554
+ 8948              	.LVL604:
+ 8949              	.L556:
+4163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8950              		.loc 1 4163 5 is_stmt 1 view .LVU3143
+ 8951 0026 48F20201 		movw	r1, #32770
+ 8952              	.LVL605:
+4163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8953              		.loc 1 4163 5 is_stmt 0 view .LVU3144
+ 8954 002a 2046     		mov	r0, r4
+ 8955 002c FFF7FEFF 		bl	I2C_Disable_IRQ
+ 8956              	.LVL606:
+4166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8957              		.loc 1 4166 5 is_stmt 1 view .LVU3145
+4166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8958              		.loc 1 4166 5 view .LVU3146
+ 8959 0030 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 8960 0034 012B     		cmp	r3, #1
+ 8961 0036 00F0A880 		beq	.L565
+4166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8962              		.loc 1 4166 5 discriminator 2 view .LVU3147
+ 8963 003a 0123     		movs	r3, #1
+ 8964 003c 84F84030 		strb	r3, [r4, #64]
+4166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 331
+
+
+ 8965              		.loc 1 4166 5 discriminator 2 view .LVU3148
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8966              		.loc 1 4170 5 discriminator 2 view .LVU3149
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8967              		.loc 1 4170 13 is_stmt 0 discriminator 2 view .LVU3150
+ 8968 0040 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 8969 0044 DBB2     		uxtb	r3, r3
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8970              		.loc 1 4170 8 discriminator 2 view .LVU3151
+ 8971 0046 292B     		cmp	r3, #41
+ 8972 0048 3DD0     		beq	.L568
+4195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8973              		.loc 1 4195 10 is_stmt 1 view .LVU3152
+4195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8974              		.loc 1 4195 18 is_stmt 0 view .LVU3153
+ 8975 004a 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 8976 004e DBB2     		uxtb	r3, r3
+4195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 8977              		.loc 1 4195 13 view .LVU3154
+ 8978 0050 2A2B     		cmp	r3, #42
+ 8979 0052 54D0     		beq	.L569
+ 8980              	.L558:
+4220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8981              		.loc 1 4220 5 is_stmt 1 view .LVU3155
+4222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 8982              		.loc 1 4222 5 view .LVU3156
+4222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 8983              		.loc 1 4222 21 is_stmt 0 view .LVU3157
+ 8984 0054 2A23     		movs	r3, #42
+ 8985 0056 84F84130 		strb	r3, [r4, #65]
+4223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8986              		.loc 1 4223 5 is_stmt 1 view .LVU3158
+4223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8987              		.loc 1 4223 21 is_stmt 0 view .LVU3159
+ 8988 005a 2023     		movs	r3, #32
+ 8989 005c 84F84230 		strb	r3, [r4, #66]
+4224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8990              		.loc 1 4224 5 is_stmt 1 view .LVU3160
+4224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8991              		.loc 1 4224 21 is_stmt 0 view .LVU3161
+ 8992 0060 0023     		movs	r3, #0
+ 8993 0062 6364     		str	r3, [r4, #68]
+4227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8994              		.loc 1 4227 5 is_stmt 1 view .LVU3162
+4227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8995              		.loc 1 4227 9 is_stmt 0 view .LVU3163
+ 8996 0064 2268     		ldr	r2, [r4]
+4227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8997              		.loc 1 4227 19 view .LVU3164
+ 8998 0066 5368     		ldr	r3, [r2, #4]
+4227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 8999              		.loc 1 4227 25 view .LVU3165
+ 9000 0068 23F40043 		bic	r3, r3, #32768
+ 9001 006c 5360     		str	r3, [r2, #4]
+4230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 9002              		.loc 1 4230 5 is_stmt 1 view .LVU3166
+4230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ARM GAS  /tmp/ccbUHtu7.s 			page 332
+
+
+ 9003              		.loc 1 4230 23 is_stmt 0 view .LVU3167
+ 9004 006e 6762     		str	r7, [r4, #36]
+4231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 9005              		.loc 1 4231 5 is_stmt 1 view .LVU3168
+4231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 9006              		.loc 1 4231 23 is_stmt 0 view .LVU3169
+ 9007 0070 6685     		strh	r6, [r4, #42]	@ movhi
+4232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 9008              		.loc 1 4232 5 is_stmt 1 view .LVU3170
+4232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 9009              		.loc 1 4232 29 is_stmt 0 view .LVU3171
+ 9010 0072 638D     		ldrh	r3, [r4, #42]
+4232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 9011              		.loc 1 4232 23 view .LVU3172
+ 9012 0074 2385     		strh	r3, [r4, #40]	@ movhi
+4233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 9013              		.loc 1 4233 5 is_stmt 1 view .LVU3173
+4233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 9014              		.loc 1 4233 23 is_stmt 0 view .LVU3174
+ 9015 0076 E562     		str	r5, [r4, #44]
+4234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9016              		.loc 1 4234 5 is_stmt 1 view .LVU3175
+4234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9017              		.loc 1 4234 23 is_stmt 0 view .LVU3176
+ 9018 0078 454B     		ldr	r3, .L570
+ 9019 007a 6363     		str	r3, [r4, #52]
+4236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9020              		.loc 1 4236 5 is_stmt 1 view .LVU3177
+4236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9021              		.loc 1 4236 13 is_stmt 0 view .LVU3178
+ 9022 007c E36B     		ldr	r3, [r4, #60]
+4236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9023              		.loc 1 4236 8 view .LVU3179
+ 9024 007e 002B     		cmp	r3, #0
+ 9025 0080 54D0     		beq	.L559
+4239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9026              		.loc 1 4239 7 is_stmt 1 view .LVU3180
+4239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9027              		.loc 1 4239 38 is_stmt 0 view .LVU3181
+ 9028 0082 444A     		ldr	r2, .L570+4
+ 9029 0084 DA62     		str	r2, [r3, #44]
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9030              		.loc 1 4242 7 is_stmt 1 view .LVU3182
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9031              		.loc 1 4242 11 is_stmt 0 view .LVU3183
+ 9032 0086 E36B     		ldr	r3, [r4, #60]
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9033              		.loc 1 4242 39 view .LVU3184
+ 9034 0088 434A     		ldr	r2, .L570+8
+ 9035 008a 5A63     		str	r2, [r3, #52]
+4245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 9036              		.loc 1 4245 7 is_stmt 1 view .LVU3185
+4245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 9037              		.loc 1 4245 11 is_stmt 0 view .LVU3186
+ 9038 008c E26B     		ldr	r2, [r4, #60]
+4245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 9039              		.loc 1 4245 42 view .LVU3187
+ARM GAS  /tmp/ccbUHtu7.s 			page 333
+
+
+ 9040 008e 0023     		movs	r3, #0
+ 9041 0090 1363     		str	r3, [r2, #48]
+4246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9042              		.loc 1 4246 7 is_stmt 1 view .LVU3188
+4246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9043              		.loc 1 4246 11 is_stmt 0 view .LVU3189
+ 9044 0092 E26B     		ldr	r2, [r4, #60]
+4246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9045              		.loc 1 4246 39 view .LVU3190
+ 9046 0094 9363     		str	r3, [r2, #56]
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        (uint32_t)pData, hi2c->XferSize);
+ 9047              		.loc 1 4249 7 is_stmt 1 view .LVU3191
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        (uint32_t)pData, hi2c->XferSize);
+ 9048              		.loc 1 4249 69 is_stmt 0 view .LVU3192
+ 9049 0096 2168     		ldr	r1, [r4]
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                        (uint32_t)pData, hi2c->XferSize);
+ 9050              		.loc 1 4249 23 view .LVU3193
+ 9051 0098 238D     		ldrh	r3, [r4, #40]
+ 9052 009a 3A46     		mov	r2, r7
+ 9053 009c 2431     		adds	r1, r1, #36
+ 9054 009e E06B     		ldr	r0, [r4, #60]
+ 9055 00a0 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 9056              	.LVL607:
+4267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9057              		.loc 1 4267 5 is_stmt 1 view .LVU3194
+4267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9058              		.loc 1 4267 8 is_stmt 0 view .LVU3195
+ 9059 00a4 0546     		mov	r5, r0
+ 9060              	.LVL608:
+4267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9061              		.loc 1 4267 8 view .LVU3196
+ 9062 00a6 0028     		cmp	r0, #0
+ 9063 00a8 4ED0     		beq	.L560
+4278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 9064              		.loc 1 4278 7 is_stmt 1 view .LVU3197
+4278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 9065              		.loc 1 4278 23 is_stmt 0 view .LVU3198
+ 9066 00aa 2823     		movs	r3, #40
+ 9067 00ac 84F84130 		strb	r3, [r4, #65]
+4279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9068              		.loc 1 4279 7 is_stmt 1 view .LVU3199
+4279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9069              		.loc 1 4279 23 is_stmt 0 view .LVU3200
+ 9070 00b0 0022     		movs	r2, #0
+ 9071 00b2 84F84220 		strb	r2, [r4, #66]
+4282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9072              		.loc 1 4282 7 is_stmt 1 view .LVU3201
+4282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9073              		.loc 1 4282 11 is_stmt 0 view .LVU3202
+ 9074 00b6 636C     		ldr	r3, [r4, #68]
+4282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9075              		.loc 1 4282 23 view .LVU3203
+ 9076 00b8 43F01003 		orr	r3, r3, #16
+ 9077 00bc 6364     		str	r3, [r4, #68]
+4285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9078              		.loc 1 4285 7 is_stmt 1 view .LVU3204
+4285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 334
+
+
+ 9079              		.loc 1 4285 7 view .LVU3205
+ 9080 00be 84F84020 		strb	r2, [r4, #64]
+4285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9081              		.loc 1 4285 7 view .LVU3206
+4287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 9082              		.loc 1 4287 7 view .LVU3207
+4287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 9083              		.loc 1 4287 14 is_stmt 0 view .LVU3208
+ 9084 00c2 0125     		movs	r5, #1
+ 9085 00c4 5FE0     		b	.L554
+ 9086              	.LVL609:
+ 9087              	.L568:
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9088              		.loc 1 4173 7 is_stmt 1 view .LVU3209
+ 9089 00c6 0121     		movs	r1, #1
+ 9090 00c8 2046     		mov	r0, r4
+ 9091 00ca FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9092              	.LVL610:
+4175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 9093              		.loc 1 4175 7 view .LVU3210
+4175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 9094              		.loc 1 4175 16 is_stmt 0 view .LVU3211
+ 9095 00ce 2368     		ldr	r3, [r4]
+4175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 9096              		.loc 1 4175 26 view .LVU3212
+ 9097 00d0 1A68     		ldr	r2, [r3]
+4175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 9098              		.loc 1 4175 10 view .LVU3213
+ 9099 00d2 12F4804F 		tst	r2, #16384
+ 9100 00d6 BDD0     		beq	.L558
+4178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 9101              		.loc 1 4178 9 is_stmt 1 view .LVU3214
+4178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 9102              		.loc 1 4178 17 is_stmt 0 view .LVU3215
+ 9103 00d8 A26B     		ldr	r2, [r4, #56]
+4178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 9104              		.loc 1 4178 12 view .LVU3216
+ 9105 00da 002A     		cmp	r2, #0
+ 9106 00dc BAD0     		beq	.L558
+4180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9107              		.loc 1 4180 11 is_stmt 1 view .LVU3217
+4180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9108              		.loc 1 4180 25 is_stmt 0 view .LVU3218
+ 9109 00de 1A68     		ldr	r2, [r3]
+4180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9110              		.loc 1 4180 31 view .LVU3219
+ 9111 00e0 22F48042 		bic	r2, r2, #16384
+ 9112 00e4 1A60     		str	r2, [r3]
+4184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9113              		.loc 1 4184 11 is_stmt 1 view .LVU3220
+4184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9114              		.loc 1 4184 15 is_stmt 0 view .LVU3221
+ 9115 00e6 A36B     		ldr	r3, [r4, #56]
+4184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9116              		.loc 1 4184 43 view .LVU3222
+ 9117 00e8 2C4A     		ldr	r2, .L570+12
+ 9118 00ea 9A63     		str	r2, [r3, #56]
+ARM GAS  /tmp/ccbUHtu7.s 			page 335
+
+
+4187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 9119              		.loc 1 4187 11 is_stmt 1 view .LVU3223
+4187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 9120              		.loc 1 4187 15 is_stmt 0 view .LVU3224
+ 9121 00ec A06B     		ldr	r0, [r4, #56]
+ 9122 00ee FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 9123              	.LVL611:
+4187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 9124              		.loc 1 4187 14 view .LVU3225
+ 9125 00f2 0028     		cmp	r0, #0
+ 9126 00f4 AED0     		beq	.L558
+4190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 9127              		.loc 1 4190 13 is_stmt 1 view .LVU3226
+4190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 9128              		.loc 1 4190 17 is_stmt 0 view .LVU3227
+ 9129 00f6 A06B     		ldr	r0, [r4, #56]
+4190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 9130              		.loc 1 4190 25 view .LVU3228
+ 9131 00f8 836B     		ldr	r3, [r0, #56]
+4190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 9132              		.loc 1 4190 13 view .LVU3229
+ 9133 00fa 9847     		blx	r3
+ 9134              	.LVL612:
+ 9135 00fc AAE7     		b	.L558
+ 9136              	.L569:
+4197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 9137              		.loc 1 4197 7 is_stmt 1 view .LVU3230
+4197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 9138              		.loc 1 4197 16 is_stmt 0 view .LVU3231
+ 9139 00fe 2368     		ldr	r3, [r4]
+4197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 9140              		.loc 1 4197 26 view .LVU3232
+ 9141 0100 1A68     		ldr	r2, [r3]
+4197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 9142              		.loc 1 4197 10 view .LVU3233
+ 9143 0102 12F4004F 		tst	r2, #32768
+ 9144 0106 A5D0     		beq	.L558
+4199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9145              		.loc 1 4199 9 is_stmt 1 view .LVU3234
+4199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9146              		.loc 1 4199 23 is_stmt 0 view .LVU3235
+ 9147 0108 1A68     		ldr	r2, [r3]
+4199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9148              		.loc 1 4199 29 view .LVU3236
+ 9149 010a 22F40042 		bic	r2, r2, #32768
+ 9150 010e 1A60     		str	r2, [r3]
+4202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 9151              		.loc 1 4202 9 is_stmt 1 view .LVU3237
+4202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 9152              		.loc 1 4202 17 is_stmt 0 view .LVU3238
+ 9153 0110 E36B     		ldr	r3, [r4, #60]
+4202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 9154              		.loc 1 4202 12 view .LVU3239
+ 9155 0112 002B     		cmp	r3, #0
+ 9156 0114 9ED0     		beq	.L558
+4206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9157              		.loc 1 4206 11 is_stmt 1 view .LVU3240
+ARM GAS  /tmp/ccbUHtu7.s 			page 336
+
+
+4206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9158              		.loc 1 4206 43 is_stmt 0 view .LVU3241
+ 9159 0116 214A     		ldr	r2, .L570+12
+ 9160 0118 9A63     		str	r2, [r3, #56]
+4209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 9161              		.loc 1 4209 11 is_stmt 1 view .LVU3242
+4209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 9162              		.loc 1 4209 15 is_stmt 0 view .LVU3243
+ 9163 011a E06B     		ldr	r0, [r4, #60]
+ 9164 011c FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 9165              	.LVL613:
+4209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 9166              		.loc 1 4209 14 view .LVU3244
+ 9167 0120 0028     		cmp	r0, #0
+ 9168 0122 97D0     		beq	.L558
+4212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 9169              		.loc 1 4212 13 is_stmt 1 view .LVU3245
+4212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 9170              		.loc 1 4212 17 is_stmt 0 view .LVU3246
+ 9171 0124 E06B     		ldr	r0, [r4, #60]
+4212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 9172              		.loc 1 4212 25 view .LVU3247
+ 9173 0126 836B     		ldr	r3, [r0, #56]
+4212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 9174              		.loc 1 4212 13 view .LVU3248
+ 9175 0128 9847     		blx	r3
+ 9176              	.LVL614:
+ 9177 012a 93E7     		b	.L558
+ 9178              	.L559:
+4255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 9179              		.loc 1 4255 7 is_stmt 1 view .LVU3249
+4255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 9180              		.loc 1 4255 23 is_stmt 0 view .LVU3250
+ 9181 012c 2823     		movs	r3, #40
+ 9182 012e 84F84130 		strb	r3, [r4, #65]
+4256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9183              		.loc 1 4256 7 is_stmt 1 view .LVU3251
+4256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9184              		.loc 1 4256 23 is_stmt 0 view .LVU3252
+ 9185 0132 0022     		movs	r2, #0
+ 9186 0134 84F84220 		strb	r2, [r4, #66]
+4259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9187              		.loc 1 4259 7 is_stmt 1 view .LVU3253
+4259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9188              		.loc 1 4259 11 is_stmt 0 view .LVU3254
+ 9189 0138 636C     		ldr	r3, [r4, #68]
+4259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9190              		.loc 1 4259 23 view .LVU3255
+ 9191 013a 43F08003 		orr	r3, r3, #128
+ 9192 013e 6364     		str	r3, [r4, #68]
+4262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9193              		.loc 1 4262 7 is_stmt 1 view .LVU3256
+4262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9194              		.loc 1 4262 7 view .LVU3257
+ 9195 0140 84F84020 		strb	r2, [r4, #64]
+4262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9196              		.loc 1 4262 7 view .LVU3258
+ARM GAS  /tmp/ccbUHtu7.s 			page 337
+
+
+4264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 9197              		.loc 1 4264 7 view .LVU3259
+4264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 9198              		.loc 1 4264 14 is_stmt 0 view .LVU3260
+ 9199 0144 0125     		movs	r5, #1
+ 9200              	.LVL615:
+4264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 9201              		.loc 1 4264 14 view .LVU3261
+ 9202 0146 1EE0     		b	.L554
+ 9203              	.LVL616:
+ 9204              	.L560:
+4270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9205              		.loc 1 4270 7 is_stmt 1 view .LVU3262
+4270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9206              		.loc 1 4270 11 is_stmt 0 view .LVU3263
+ 9207 0148 638D     		ldrh	r3, [r4, #42]
+ 9208 014a 9BB2     		uxth	r3, r3
+4270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9209              		.loc 1 4270 30 view .LVU3264
+ 9210 014c 228D     		ldrh	r2, [r4, #40]
+4270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9211              		.loc 1 4270 23 view .LVU3265
+ 9212 014e 9B1A     		subs	r3, r3, r2
+ 9213 0150 9BB2     		uxth	r3, r3
+ 9214 0152 6385     		strh	r3, [r4, #42]	@ movhi
+4273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 9215              		.loc 1 4273 7 is_stmt 1 view .LVU3266
+4273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 9216              		.loc 1 4273 22 is_stmt 0 view .LVU3267
+ 9217 0154 0023     		movs	r3, #0
+ 9218 0156 2385     		strh	r3, [r4, #40]	@ movhi
+4290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9219              		.loc 1 4290 5 is_stmt 1 view .LVU3268
+4290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9220              		.loc 1 4290 9 is_stmt 0 view .LVU3269
+ 9221 0158 2368     		ldr	r3, [r4]
+ 9222 015a 9A69     		ldr	r2, [r3, #24]
+4290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9223              		.loc 1 4290 8 view .LVU3270
+ 9224 015c 12F4803F 		tst	r2, #65536
+ 9225 0160 0DD0     		beq	.L562
+ 9226              	.L563:
+4298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9227              		.loc 1 4298 5 is_stmt 1 view .LVU3271
+4298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9228              		.loc 1 4298 5 view .LVU3272
+ 9229 0162 0023     		movs	r3, #0
+ 9230 0164 84F84030 		strb	r3, [r4, #64]
+4298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9231              		.loc 1 4298 5 view .LVU3273
+4301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9232              		.loc 1 4301 5 view .LVU3274
+4301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9233              		.loc 1 4301 9 is_stmt 0 view .LVU3275
+ 9234 0168 2268     		ldr	r2, [r4]
+4301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9235              		.loc 1 4301 19 view .LVU3276
+ARM GAS  /tmp/ccbUHtu7.s 			page 338
+
+
+ 9236 016a 1368     		ldr	r3, [r2]
+4301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9237              		.loc 1 4301 25 view .LVU3277
+ 9238 016c 43F40043 		orr	r3, r3, #32768
+ 9239 0170 1360     		str	r3, [r2]
+4307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9240              		.loc 1 4307 5 is_stmt 1 view .LVU3278
+ 9241 0172 48F20201 		movw	r1, #32770
+ 9242 0176 2046     		mov	r0, r4
+ 9243              	.LVL617:
+4307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9244              		.loc 1 4307 5 is_stmt 0 view .LVU3279
+ 9245 0178 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 9246              	.LVL618:
+4309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9247              		.loc 1 4309 5 is_stmt 1 view .LVU3280
+4309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9248              		.loc 1 4309 12 is_stmt 0 view .LVU3281
+ 9249 017c 03E0     		b	.L554
+ 9250              	.LVL619:
+ 9251              	.L562:
+4294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 9252              		.loc 1 4294 7 is_stmt 1 view .LVU3282
+ 9253 017e 0822     		movs	r2, #8
+ 9254 0180 DA61     		str	r2, [r3, #28]
+ 9255 0182 EEE7     		b	.L563
+ 9256              	.LVL620:
+ 9257              	.L564:
+4313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9258              		.loc 1 4313 12 is_stmt 0 view .LVU3283
+ 9259 0184 0125     		movs	r5, #1
+ 9260              	.LVL621:
+ 9261              	.L554:
+4315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9262              		.loc 1 4315 1 view .LVU3284
+ 9263 0186 2846     		mov	r0, r5
+ 9264 0188 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 9265              	.LVL622:
+ 9266              	.L565:
+4166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9267              		.loc 1 4166 5 view .LVU3285
+ 9268 018a 0225     		movs	r5, #2
+ 9269              	.LVL623:
+4166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9270              		.loc 1 4166 5 view .LVU3286
+ 9271 018c FBE7     		b	.L554
+ 9272              	.L571:
+ 9273 018e 00BF     		.align	2
+ 9274              	.L570:
+ 9275 0190 00000000 		.word	I2C_Slave_ISR_DMA
+ 9276 0194 00000000 		.word	I2C_DMASlaveReceiveCplt
+ 9277 0198 00000000 		.word	I2C_DMAError
+ 9278 019c 00000000 		.word	I2C_DMAAbort
+ 9279              		.cfi_endproc
+ 9280              	.LFE359:
+ 9282              		.section	.text.HAL_I2C_EnableListen_IT,"ax",%progbits
+ 9283              		.align	1
+ARM GAS  /tmp/ccbUHtu7.s 			page 339
+
+
+ 9284              		.global	HAL_I2C_EnableListen_IT
+ 9285              		.syntax unified
+ 9286              		.thumb
+ 9287              		.thumb_func
+ 9289              	HAL_I2C_EnableListen_IT:
+ 9290              	.LVL624:
+ 9291              	.LFB360:
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 9292              		.loc 1 4324 1 is_stmt 1 view -0
+ 9293              		.cfi_startproc
+ 9294              		@ args = 0, pretend = 0, frame = 0
+ 9295              		@ frame_needed = 0, uses_anonymous_args = 0
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 9296              		.loc 1 4324 1 is_stmt 0 view .LVU3288
+ 9297 0000 08B5     		push	{r3, lr}
+ 9298              	.LCFI103:
+ 9299              		.cfi_def_cfa_offset 8
+ 9300              		.cfi_offset 3, -8
+ 9301              		.cfi_offset 14, -4
+4325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9302              		.loc 1 4325 3 is_stmt 1 view .LVU3289
+4325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9303              		.loc 1 4325 11 is_stmt 0 view .LVU3290
+ 9304 0002 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 9305 0006 DBB2     		uxtb	r3, r3
+4325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9306              		.loc 1 4325 6 view .LVU3291
+ 9307 0008 202B     		cmp	r3, #32
+ 9308 000a 01D0     		beq	.L576
+4337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9309              		.loc 1 4337 12 view .LVU3292
+ 9310 000c 0220     		movs	r0, #2
+ 9311              	.LVL625:
+ 9312              	.L573:
+4339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9313              		.loc 1 4339 1 view .LVU3293
+ 9314 000e 08BD     		pop	{r3, pc}
+ 9315              	.LVL626:
+ 9316              	.L576:
+4327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR = I2C_Slave_ISR_IT;
+ 9317              		.loc 1 4327 5 is_stmt 1 view .LVU3294
+4327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR = I2C_Slave_ISR_IT;
+ 9318              		.loc 1 4327 17 is_stmt 0 view .LVU3295
+ 9319 0010 2823     		movs	r3, #40
+ 9320 0012 80F84130 		strb	r3, [r0, #65]
+4328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9321              		.loc 1 4328 5 is_stmt 1 view .LVU3296
+4328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9322              		.loc 1 4328 19 is_stmt 0 view .LVU3297
+ 9323 0016 044B     		ldr	r3, .L577
+ 9324 0018 4363     		str	r3, [r0, #52]
+4331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9325              		.loc 1 4331 5 is_stmt 1 view .LVU3298
+ 9326 001a 4FF40041 		mov	r1, #32768
+ 9327 001e FFF7FEFF 		bl	I2C_Enable_IRQ
+ 9328              	.LVL627:
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccbUHtu7.s 			page 340
+
+
+ 9329              		.loc 1 4333 5 view .LVU3299
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9330              		.loc 1 4333 12 is_stmt 0 view .LVU3300
+ 9331 0022 0020     		movs	r0, #0
+ 9332 0024 F3E7     		b	.L573
+ 9333              	.L578:
+ 9334 0026 00BF     		.align	2
+ 9335              	.L577:
+ 9336 0028 00000000 		.word	I2C_Slave_ISR_IT
+ 9337              		.cfi_endproc
+ 9338              	.LFE360:
+ 9340              		.section	.text.HAL_I2C_DisableListen_IT,"ax",%progbits
+ 9341              		.align	1
+ 9342              		.global	HAL_I2C_DisableListen_IT
+ 9343              		.syntax unified
+ 9344              		.thumb
+ 9345              		.thumb_func
+ 9347              	HAL_I2C_DisableListen_IT:
+ 9348              	.LVL628:
+ 9349              	.LFB361:
+4348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ 9350              		.loc 1 4348 1 is_stmt 1 view -0
+ 9351              		.cfi_startproc
+ 9352              		@ args = 0, pretend = 0, frame = 0
+ 9353              		@ frame_needed = 0, uses_anonymous_args = 0
+4350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9354              		.loc 1 4350 3 view .LVU3302
+4353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9355              		.loc 1 4353 3 view .LVU3303
+4353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9356              		.loc 1 4353 11 is_stmt 0 view .LVU3304
+ 9357 0000 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 9358 0004 DBB2     		uxtb	r3, r3
+4353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9359              		.loc 1 4353 6 view .LVU3305
+ 9360 0006 282B     		cmp	r3, #40
+ 9361 0008 01D0     		beq	.L586
+4368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9362              		.loc 1 4368 12 view .LVU3306
+ 9363 000a 0220     		movs	r0, #2
+ 9364              	.LVL629:
+4370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9365              		.loc 1 4370 1 view .LVU3307
+ 9366 000c 7047     		bx	lr
+ 9367              	.LVL630:
+ 9368              	.L586:
+4348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ 9369              		.loc 1 4348 1 view .LVU3308
+ 9370 000e 10B5     		push	{r4, lr}
+ 9371              	.LCFI104:
+ 9372              		.cfi_def_cfa_offset 8
+ 9373              		.cfi_offset 4, -8
+ 9374              		.cfi_offset 14, -4
+4355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ 9375              		.loc 1 4355 5 is_stmt 1 view .LVU3309
+4355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ 9376              		.loc 1 4355 26 is_stmt 0 view .LVU3310
+ARM GAS  /tmp/ccbUHtu7.s 			page 341
+
+
+ 9377 0010 90F84120 		ldrb	r2, [r0, #65]	@ zero_extendqisi2
+ 9378              	.LVL631:
+4356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 9379              		.loc 1 4356 5 is_stmt 1 view .LVU3311
+4356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 9380              		.loc 1 4356 48 is_stmt 0 view .LVU3312
+ 9381 0014 90F84230 		ldrb	r3, [r0, #66]	@ zero_extendqisi2
+4356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 9382              		.loc 1 4356 31 view .LVU3313
+ 9383 0018 02F00302 		and	r2, r2, #3
+ 9384              	.LVL632:
+4356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 9385              		.loc 1 4356 31 view .LVU3314
+ 9386 001c 1343     		orrs	r3, r3, r2
+4356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 9387              		.loc 1 4356 25 view .LVU3315
+ 9388 001e 0363     		str	r3, [r0, #48]
+4357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode = HAL_I2C_MODE_NONE;
+ 9389              		.loc 1 4357 5 is_stmt 1 view .LVU3316
+4357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->Mode = HAL_I2C_MODE_NONE;
+ 9390              		.loc 1 4357 17 is_stmt 0 view .LVU3317
+ 9391 0020 2023     		movs	r3, #32
+ 9392 0022 80F84130 		strb	r3, [r0, #65]
+4358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR = NULL;
+ 9393              		.loc 1 4358 5 is_stmt 1 view .LVU3318
+4358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR = NULL;
+ 9394              		.loc 1 4358 16 is_stmt 0 view .LVU3319
+ 9395 0026 0024     		movs	r4, #0
+ 9396 0028 80F84240 		strb	r4, [r0, #66]
+4359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9397              		.loc 1 4359 5 is_stmt 1 view .LVU3320
+4359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9398              		.loc 1 4359 19 is_stmt 0 view .LVU3321
+ 9399 002c 4463     		str	r4, [r0, #52]
+4362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9400              		.loc 1 4362 5 is_stmt 1 view .LVU3322
+ 9401 002e 4FF40041 		mov	r1, #32768
+ 9402 0032 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9403              	.LVL633:
+4364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9404              		.loc 1 4364 5 view .LVU3323
+4364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9405              		.loc 1 4364 12 is_stmt 0 view .LVU3324
+ 9406 0036 2046     		mov	r0, r4
+4370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9407              		.loc 1 4370 1 view .LVU3325
+ 9408 0038 10BD     		pop	{r4, pc}
+ 9409              		.cfi_endproc
+ 9410              	.LFE361:
+ 9412              		.section	.text.HAL_I2C_Master_Abort_IT,"ax",%progbits
+ 9413              		.align	1
+ 9414              		.global	HAL_I2C_Master_Abort_IT
+ 9415              		.syntax unified
+ 9416              		.thumb
+ 9417              		.thumb_func
+ 9419              	HAL_I2C_Master_Abort_IT:
+ 9420              	.LVL634:
+ARM GAS  /tmp/ccbUHtu7.s 			page 342
+
+
+ 9421              	.LFB362:
+4381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+ 9422              		.loc 1 4381 1 is_stmt 1 view -0
+ 9423              		.cfi_startproc
+ 9424              		@ args = 0, pretend = 0, frame = 0
+ 9425              		@ frame_needed = 0, uses_anonymous_args = 0
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9426              		.loc 1 4382 3 view .LVU3327
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9427              		.loc 1 4382 11 is_stmt 0 view .LVU3328
+ 9428 0000 90F84230 		ldrb	r3, [r0, #66]	@ zero_extendqisi2
+ 9429 0004 DBB2     		uxtb	r3, r3
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9430              		.loc 1 4382 6 view .LVU3329
+ 9431 0006 102B     		cmp	r3, #16
+ 9432 0008 36D1     		bne	.L591
+4381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+ 9433              		.loc 1 4381 1 view .LVU3330
+ 9434 000a 30B5     		push	{r4, r5, lr}
+ 9435              	.LCFI105:
+ 9436              		.cfi_def_cfa_offset 12
+ 9437              		.cfi_offset 4, -12
+ 9438              		.cfi_offset 5, -8
+ 9439              		.cfi_offset 14, -4
+ 9440 000c 83B0     		sub	sp, sp, #12
+ 9441              	.LCFI106:
+ 9442              		.cfi_def_cfa_offset 24
+ 9443 000e 0446     		mov	r4, r0
+ 9444 0010 0D46     		mov	r5, r1
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9445              		.loc 1 4385 5 is_stmt 1 view .LVU3331
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9446              		.loc 1 4385 5 view .LVU3332
+ 9447 0012 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 9448 0016 012B     		cmp	r3, #1
+ 9449 0018 30D0     		beq	.L592
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9450              		.loc 1 4385 5 discriminator 2 view .LVU3333
+ 9451 001a 0123     		movs	r3, #1
+ 9452 001c 80F84030 		strb	r3, [r0, #64]
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9453              		.loc 1 4385 5 discriminator 2 view .LVU3334
+4388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9454              		.loc 1 4388 5 discriminator 2 view .LVU3335
+4388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9455              		.loc 1 4388 13 is_stmt 0 discriminator 2 view .LVU3336
+ 9456 0020 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 9457 0024 DBB2     		uxtb	r3, r3
+4388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9458              		.loc 1 4388 8 discriminator 2 view .LVU3337
+ 9459 0026 212B     		cmp	r3, #33
+ 9460 0028 1AD0     		beq	.L597
+4393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9461              		.loc 1 4393 10 is_stmt 1 view .LVU3338
+4393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9462              		.loc 1 4393 18 is_stmt 0 view .LVU3339
+ 9463 002a 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ARM GAS  /tmp/ccbUHtu7.s 			page 343
+
+
+ 9464 002e DBB2     		uxtb	r3, r3
+4393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 9465              		.loc 1 4393 13 view .LVU3340
+ 9466 0030 222B     		cmp	r3, #34
+ 9467 0032 1BD0     		beq	.L598
+ 9468              	.LVL635:
+ 9469              	.L590:
+4401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9470              		.loc 1 4401 5 is_stmt 1 view .LVU3341
+4404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9471              		.loc 1 4404 5 view .LVU3342
+4404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9472              		.loc 1 4404 17 is_stmt 0 view .LVU3343
+ 9473 0034 6023     		movs	r3, #96
+ 9474 0036 84F84130 		strb	r3, [r4, #65]
+4408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9475              		.loc 1 4408 5 is_stmt 1 view .LVU3344
+ 9476 003a 114B     		ldr	r3, .L599
+ 9477 003c 0093     		str	r3, [sp]
+ 9478 003e 4FF00073 		mov	r3, #33554432
+ 9479 0042 0122     		movs	r2, #1
+ 9480 0044 2946     		mov	r1, r5
+ 9481 0046 2046     		mov	r0, r4
+ 9482 0048 FFF7FEFF 		bl	I2C_TransferConfig
+ 9483              	.LVL636:
+4411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9484              		.loc 1 4411 5 view .LVU3345
+4411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9485              		.loc 1 4411 5 view .LVU3346
+ 9486 004c 0025     		movs	r5, #0
+ 9487 004e 84F84050 		strb	r5, [r4, #64]
+4411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9488              		.loc 1 4411 5 view .LVU3347
+4416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9489              		.loc 1 4416 5 view .LVU3348
+ 9490 0052 2021     		movs	r1, #32
+ 9491 0054 2046     		mov	r0, r4
+ 9492 0056 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 9493              	.LVL637:
+4418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9494              		.loc 1 4418 5 view .LVU3349
+4418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9495              		.loc 1 4418 12 is_stmt 0 view .LVU3350
+ 9496 005a 2846     		mov	r0, r5
+ 9497              	.L588:
+4426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9498              		.loc 1 4426 1 view .LVU3351
+ 9499 005c 03B0     		add	sp, sp, #12
+ 9500              	.LCFI107:
+ 9501              		.cfi_remember_state
+ 9502              		.cfi_def_cfa_offset 12
+ 9503              		@ sp needed
+ 9504 005e 30BD     		pop	{r4, r5, pc}
+ 9505              	.LVL638:
+ 9506              	.L597:
+ 9507              	.LCFI108:
+ 9508              		.cfi_restore_state
+ARM GAS  /tmp/ccbUHtu7.s 			page 344
+
+
+4390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ 9509              		.loc 1 4390 7 is_stmt 1 view .LVU3352
+ 9510 0060 0121     		movs	r1, #1
+ 9511              	.LVL639:
+4390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ 9512              		.loc 1 4390 7 is_stmt 0 view .LVU3353
+ 9513 0062 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9514              	.LVL640:
+4391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 9515              		.loc 1 4391 7 is_stmt 1 view .LVU3354
+4391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 9516              		.loc 1 4391 27 is_stmt 0 view .LVU3355
+ 9517 0066 1123     		movs	r3, #17
+ 9518 0068 2363     		str	r3, [r4, #48]
+ 9519 006a E3E7     		b	.L590
+ 9520              	.LVL641:
+ 9521              	.L598:
+4395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ 9522              		.loc 1 4395 7 is_stmt 1 view .LVU3356
+ 9523 006c 0221     		movs	r1, #2
+ 9524              	.LVL642:
+4395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ 9525              		.loc 1 4395 7 is_stmt 0 view .LVU3357
+ 9526 006e FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9527              	.LVL643:
+4396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 9528              		.loc 1 4396 7 is_stmt 1 view .LVU3358
+4396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 9529              		.loc 1 4396 27 is_stmt 0 view .LVU3359
+ 9530 0072 1223     		movs	r3, #18
+ 9531 0074 2363     		str	r3, [r4, #48]
+ 9532 0076 DDE7     		b	.L590
+ 9533              	.LVL644:
+ 9534              	.L591:
+ 9535              	.LCFI109:
+ 9536              		.cfi_def_cfa_offset 0
+ 9537              		.cfi_restore 4
+ 9538              		.cfi_restore 5
+ 9539              		.cfi_restore 14
+4424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9540              		.loc 1 4424 12 view .LVU3360
+ 9541 0078 0120     		movs	r0, #1
+ 9542              	.LVL645:
+4426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9543              		.loc 1 4426 1 view .LVU3361
+ 9544 007a 7047     		bx	lr
+ 9545              	.LVL646:
+ 9546              	.L592:
+ 9547              	.LCFI110:
+ 9548              		.cfi_def_cfa_offset 24
+ 9549              		.cfi_offset 4, -12
+ 9550              		.cfi_offset 5, -8
+ 9551              		.cfi_offset 14, -4
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9552              		.loc 1 4385 5 view .LVU3362
+ 9553 007c 0220     		movs	r0, #2
+ 9554              	.LVL647:
+ARM GAS  /tmp/ccbUHtu7.s 			page 345
+
+
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9555              		.loc 1 4385 5 view .LVU3363
+ 9556 007e EDE7     		b	.L588
+ 9557              	.L600:
+ 9558              		.align	2
+ 9559              	.L599:
+ 9560 0080 00400080 		.word	-2147467264
+ 9561              		.cfi_endproc
+ 9562              	.LFE362:
+ 9564              		.section	.text.HAL_I2C_EV_IRQHandler,"ax",%progbits
+ 9565              		.align	1
+ 9566              		.global	HAL_I2C_EV_IRQHandler
+ 9567              		.syntax unified
+ 9568              		.thumb
+ 9569              		.thumb_func
+ 9571              	HAL_I2C_EV_IRQHandler:
+ 9572              	.LVL648:
+ 9573              	.LFB363:
+4443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Get current IT Flags and IT sources value */
+ 9574              		.loc 1 4443 1 is_stmt 1 view -0
+ 9575              		.cfi_startproc
+ 9576              		@ args = 0, pretend = 0, frame = 0
+ 9577              		@ frame_needed = 0, uses_anonymous_args = 0
+4443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Get current IT Flags and IT sources value */
+ 9578              		.loc 1 4443 1 is_stmt 0 view .LVU3365
+ 9579 0000 08B5     		push	{r3, lr}
+ 9580              	.LCFI111:
+ 9581              		.cfi_def_cfa_offset 8
+ 9582              		.cfi_offset 3, -8
+ 9583              		.cfi_offset 14, -4
+4445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 9584              		.loc 1 4445 3 is_stmt 1 view .LVU3366
+4445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 9585              		.loc 1 4445 24 is_stmt 0 view .LVU3367
+ 9586 0002 0368     		ldr	r3, [r0]
+4445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 9587              		.loc 1 4445 12 view .LVU3368
+ 9588 0004 9969     		ldr	r1, [r3, #24]
+ 9589              	.LVL649:
+4446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9590              		.loc 1 4446 3 is_stmt 1 view .LVU3369
+4446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9591              		.loc 1 4446 12 is_stmt 0 view .LVU3370
+ 9592 0006 1A68     		ldr	r2, [r3]
+ 9593              	.LVL650:
+4449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9594              		.loc 1 4449 3 is_stmt 1 view .LVU3371
+4449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9595              		.loc 1 4449 11 is_stmt 0 view .LVU3372
+ 9596 0008 436B     		ldr	r3, [r0, #52]
+4449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9597              		.loc 1 4449 6 view .LVU3373
+ 9598 000a 03B1     		cbz	r3, .L601
+4451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9599              		.loc 1 4451 5 is_stmt 1 view .LVU3374
+ 9600 000c 9847     		blx	r3
+ 9601              	.LVL651:
+ARM GAS  /tmp/ccbUHtu7.s 			page 346
+
+
+ 9602              	.L601:
+4453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9603              		.loc 1 4453 1 is_stmt 0 view .LVU3375
+ 9604 000e 08BD     		pop	{r3, pc}
+ 9605              		.cfi_endproc
+ 9606              	.LFE363:
+ 9608              		.section	.text.HAL_I2C_MasterTxCpltCallback,"ax",%progbits
+ 9609              		.align	1
+ 9610              		.weak	HAL_I2C_MasterTxCpltCallback
+ 9611              		.syntax unified
+ 9612              		.thumb
+ 9613              		.thumb_func
+ 9615              	HAL_I2C_MasterTxCpltCallback:
+ 9616              	.LVL652:
+ 9617              	.LFB365:
+4514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 9618              		.loc 1 4514 1 is_stmt 1 view -0
+ 9619              		.cfi_startproc
+ 9620              		@ args = 0, pretend = 0, frame = 0
+ 9621              		@ frame_needed = 0, uses_anonymous_args = 0
+ 9622              		@ link register save eliminated.
+4516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9623              		.loc 1 4516 3 view .LVU3377
+4521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9624              		.loc 1 4521 1 is_stmt 0 view .LVU3378
+ 9625 0000 7047     		bx	lr
+ 9626              		.cfi_endproc
+ 9627              	.LFE365:
+ 9629              		.section	.text.HAL_I2C_MasterRxCpltCallback,"ax",%progbits
+ 9630              		.align	1
+ 9631              		.weak	HAL_I2C_MasterRxCpltCallback
+ 9632              		.syntax unified
+ 9633              		.thumb
+ 9634              		.thumb_func
+ 9636              	HAL_I2C_MasterRxCpltCallback:
+ 9637              	.LVL653:
+ 9638              	.LFB366:
+4530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 9639              		.loc 1 4530 1 is_stmt 1 view -0
+ 9640              		.cfi_startproc
+ 9641              		@ args = 0, pretend = 0, frame = 0
+ 9642              		@ frame_needed = 0, uses_anonymous_args = 0
+ 9643              		@ link register save eliminated.
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9644              		.loc 1 4532 3 view .LVU3380
+4537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9645              		.loc 1 4537 1 is_stmt 0 view .LVU3381
+ 9646 0000 7047     		bx	lr
+ 9647              		.cfi_endproc
+ 9648              	.LFE366:
+ 9650              		.section	.text.I2C_ITMasterSeqCplt,"ax",%progbits
+ 9651              		.align	1
+ 9652              		.syntax unified
+ 9653              		.thumb
+ 9654              		.thumb_func
+ 9656              	I2C_ITMasterSeqCplt:
+ 9657              	.LVL654:
+ARM GAS  /tmp/ccbUHtu7.s 			page 347
+
+
+ 9658              	.LFB385:
+5515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Reset I2C handle mode */
+ 9659              		.loc 1 5515 1 is_stmt 1 view -0
+ 9660              		.cfi_startproc
+ 9661              		@ args = 0, pretend = 0, frame = 0
+ 9662              		@ frame_needed = 0, uses_anonymous_args = 0
+5515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Reset I2C handle mode */
+ 9663              		.loc 1 5515 1 is_stmt 0 view .LVU3383
+ 9664 0000 38B5     		push	{r3, r4, r5, lr}
+ 9665              	.LCFI112:
+ 9666              		.cfi_def_cfa_offset 16
+ 9667              		.cfi_offset 3, -16
+ 9668              		.cfi_offset 4, -12
+ 9669              		.cfi_offset 5, -8
+ 9670              		.cfi_offset 14, -4
+ 9671 0002 0446     		mov	r4, r0
+5517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9672              		.loc 1 5517 3 is_stmt 1 view .LVU3384
+5517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9673              		.loc 1 5517 14 is_stmt 0 view .LVU3385
+ 9674 0004 0023     		movs	r3, #0
+ 9675 0006 80F84230 		strb	r3, [r0, #66]
+5521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9676              		.loc 1 5521 3 is_stmt 1 view .LVU3386
+5521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9677              		.loc 1 5521 11 is_stmt 0 view .LVU3387
+ 9678 000a 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 9679 000e DBB2     		uxtb	r3, r3
+5521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9680              		.loc 1 5521 6 view .LVU3388
+ 9681 0010 212B     		cmp	r3, #33
+ 9682 0012 0FD0     		beq	.L610
+5543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ 9683              		.loc 1 5543 5 is_stmt 1 view .LVU3389
+5543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ 9684              		.loc 1 5543 25 is_stmt 0 view .LVU3390
+ 9685 0014 2023     		movs	r3, #32
+ 9686 0016 80F84130 		strb	r3, [r0, #65]
+5544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+ 9687              		.loc 1 5544 5 is_stmt 1 view .LVU3391
+5544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+ 9688              		.loc 1 5544 25 is_stmt 0 view .LVU3392
+ 9689 001a 1223     		movs	r3, #18
+ 9690 001c 0363     		str	r3, [r0, #48]
+5545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9691              		.loc 1 5545 5 is_stmt 1 view .LVU3393
+5545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9692              		.loc 1 5545 25 is_stmt 0 view .LVU3394
+ 9693 001e 0025     		movs	r5, #0
+ 9694 0020 4563     		str	r5, [r0, #52]
+5548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9695              		.loc 1 5548 5 is_stmt 1 view .LVU3395
+ 9696 0022 0221     		movs	r1, #2
+ 9697 0024 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9698              	.LVL655:
+5551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9699              		.loc 1 5551 5 view .LVU3396
+ARM GAS  /tmp/ccbUHtu7.s 			page 348
+
+
+5551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9700              		.loc 1 5551 5 view .LVU3397
+ 9701 0028 84F84050 		strb	r5, [r4, #64]
+5551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9702              		.loc 1 5551 5 view .LVU3398
+5557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 9703              		.loc 1 5557 5 view .LVU3399
+ 9704 002c 2046     		mov	r0, r4
+ 9705 002e FFF7FEFF 		bl	HAL_I2C_MasterRxCpltCallback
+ 9706              	.LVL656:
+ 9707              	.L606:
+5560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9708              		.loc 1 5560 1 is_stmt 0 view .LVU3400
+ 9709 0032 38BD     		pop	{r3, r4, r5, pc}
+ 9710              	.LVL657:
+ 9711              	.L610:
+5523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ 9712              		.loc 1 5523 5 is_stmt 1 view .LVU3401
+5523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ 9713              		.loc 1 5523 25 is_stmt 0 view .LVU3402
+ 9714 0034 2023     		movs	r3, #32
+ 9715 0036 80F84130 		strb	r3, [r0, #65]
+5524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+ 9716              		.loc 1 5524 5 is_stmt 1 view .LVU3403
+5524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+ 9717              		.loc 1 5524 25 is_stmt 0 view .LVU3404
+ 9718 003a 1123     		movs	r3, #17
+ 9719 003c 0363     		str	r3, [r0, #48]
+5525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9720              		.loc 1 5525 5 is_stmt 1 view .LVU3405
+5525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9721              		.loc 1 5525 25 is_stmt 0 view .LVU3406
+ 9722 003e 0025     		movs	r5, #0
+ 9723 0040 4563     		str	r5, [r0, #52]
+5528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9724              		.loc 1 5528 5 is_stmt 1 view .LVU3407
+ 9725 0042 0121     		movs	r1, #1
+ 9726 0044 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9727              	.LVL658:
+5531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9728              		.loc 1 5531 5 view .LVU3408
+5531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9729              		.loc 1 5531 5 view .LVU3409
+ 9730 0048 84F84050 		strb	r5, [r4, #64]
+5531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9731              		.loc 1 5531 5 view .LVU3410
+5537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 9732              		.loc 1 5537 5 view .LVU3411
+ 9733 004c 2046     		mov	r0, r4
+ 9734 004e FFF7FEFF 		bl	HAL_I2C_MasterTxCpltCallback
+ 9735              	.LVL659:
+ 9736 0052 EEE7     		b	.L606
+ 9737              		.cfi_endproc
+ 9738              	.LFE385:
+ 9740              		.section	.text.HAL_I2C_SlaveTxCpltCallback,"ax",%progbits
+ 9741              		.align	1
+ 9742              		.weak	HAL_I2C_SlaveTxCpltCallback
+ARM GAS  /tmp/ccbUHtu7.s 			page 349
+
+
+ 9743              		.syntax unified
+ 9744              		.thumb
+ 9745              		.thumb_func
+ 9747              	HAL_I2C_SlaveTxCpltCallback:
+ 9748              	.LVL660:
+ 9749              	.LFB367:
+4545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 9750              		.loc 1 4545 1 view -0
+ 9751              		.cfi_startproc
+ 9752              		@ args = 0, pretend = 0, frame = 0
+ 9753              		@ frame_needed = 0, uses_anonymous_args = 0
+ 9754              		@ link register save eliminated.
+4547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9755              		.loc 1 4547 3 view .LVU3413
+4552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9756              		.loc 1 4552 1 is_stmt 0 view .LVU3414
+ 9757 0000 7047     		bx	lr
+ 9758              		.cfi_endproc
+ 9759              	.LFE367:
+ 9761              		.section	.text.HAL_I2C_SlaveRxCpltCallback,"ax",%progbits
+ 9762              		.align	1
+ 9763              		.weak	HAL_I2C_SlaveRxCpltCallback
+ 9764              		.syntax unified
+ 9765              		.thumb
+ 9766              		.thumb_func
+ 9768              	HAL_I2C_SlaveRxCpltCallback:
+ 9769              	.LVL661:
+ 9770              	.LFB368:
+4561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 9771              		.loc 1 4561 1 is_stmt 1 view -0
+ 9772              		.cfi_startproc
+ 9773              		@ args = 0, pretend = 0, frame = 0
+ 9774              		@ frame_needed = 0, uses_anonymous_args = 0
+ 9775              		@ link register save eliminated.
+4563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9776              		.loc 1 4563 3 view .LVU3416
+4568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9777              		.loc 1 4568 1 is_stmt 0 view .LVU3417
+ 9778 0000 7047     		bx	lr
+ 9779              		.cfi_endproc
+ 9780              	.LFE368:
+ 9782              		.section	.text.I2C_ITSlaveSeqCplt,"ax",%progbits
+ 9783              		.align	1
+ 9784              		.syntax unified
+ 9785              		.thumb
+ 9786              		.thumb_func
+ 9788              	I2C_ITSlaveSeqCplt:
+ 9789              	.LVL662:
+ 9790              	.LFB386:
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ 9791              		.loc 1 5568 1 is_stmt 1 view -0
+ 9792              		.cfi_startproc
+ 9793              		@ args = 0, pretend = 0, frame = 0
+ 9794              		@ frame_needed = 0, uses_anonymous_args = 0
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ 9795              		.loc 1 5568 1 is_stmt 0 view .LVU3419
+ 9796 0000 10B5     		push	{r4, lr}
+ARM GAS  /tmp/ccbUHtu7.s 			page 350
+
+
+ 9797              	.LCFI113:
+ 9798              		.cfi_def_cfa_offset 8
+ 9799              		.cfi_offset 4, -8
+ 9800              		.cfi_offset 14, -4
+ 9801 0002 0446     		mov	r4, r0
+5569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9802              		.loc 1 5569 3 is_stmt 1 view .LVU3420
+5569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9803              		.loc 1 5569 26 is_stmt 0 view .LVU3421
+ 9804 0004 0368     		ldr	r3, [r0]
+5569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9805              		.loc 1 5569 12 view .LVU3422
+ 9806 0006 1A68     		ldr	r2, [r3]
+ 9807              	.LVL663:
+5572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9808              		.loc 1 5572 3 is_stmt 1 view .LVU3423
+5572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9809              		.loc 1 5572 14 is_stmt 0 view .LVU3424
+ 9810 0008 0021     		movs	r1, #0
+ 9811 000a 80F84210 		strb	r1, [r0, #66]
+5575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9812              		.loc 1 5575 3 is_stmt 1 view .LVU3425
+5575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9813              		.loc 1 5575 6 is_stmt 0 view .LVU3426
+ 9814 000e 12F4804F 		tst	r2, #16384
+ 9815 0012 0ED0     		beq	.L614
+5578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9816              		.loc 1 5578 5 is_stmt 1 view .LVU3427
+5578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9817              		.loc 1 5578 19 is_stmt 0 view .LVU3428
+ 9818 0014 1A68     		ldr	r2, [r3]
+ 9819              	.LVL664:
+5578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9820              		.loc 1 5578 25 view .LVU3429
+ 9821 0016 22F48042 		bic	r2, r2, #16384
+ 9822 001a 1A60     		str	r2, [r3]
+ 9823              	.L615:
+5588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9824              		.loc 1 5588 3 is_stmt 1 view .LVU3430
+5590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9825              		.loc 1 5590 3 view .LVU3431
+5590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9826              		.loc 1 5590 11 is_stmt 0 view .LVU3432
+ 9827 001c 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 9828 0020 DBB2     		uxtb	r3, r3
+5590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9829              		.loc 1 5590 6 view .LVU3433
+ 9830 0022 292B     		cmp	r3, #41
+ 9831 0024 0DD0     		beq	.L619
+5610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9832              		.loc 1 5610 8 is_stmt 1 view .LVU3434
+5610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9833              		.loc 1 5610 16 is_stmt 0 view .LVU3435
+ 9834 0026 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 9835 002a DBB2     		uxtb	r3, r3
+5610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9836              		.loc 1 5610 11 view .LVU3436
+ARM GAS  /tmp/ccbUHtu7.s 			page 351
+
+
+ 9837 002c 2A2B     		cmp	r3, #42
+ 9838 002e 18D0     		beq	.L620
+ 9839              	.LVL665:
+ 9840              	.L613:
+5633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9841              		.loc 1 5633 1 view .LVU3437
+ 9842 0030 10BD     		pop	{r4, pc}
+ 9843              	.LVL666:
+ 9844              	.L614:
+5580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9845              		.loc 1 5580 8 is_stmt 1 view .LVU3438
+5580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9846              		.loc 1 5580 11 is_stmt 0 view .LVU3439
+ 9847 0032 12F4004F 		tst	r2, #32768
+ 9848 0036 F1D0     		beq	.L615
+5583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9849              		.loc 1 5583 5 is_stmt 1 view .LVU3440
+5583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9850              		.loc 1 5583 19 is_stmt 0 view .LVU3441
+ 9851 0038 1A68     		ldr	r2, [r3]
+ 9852              	.LVL667:
+5583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9853              		.loc 1 5583 25 view .LVU3442
+ 9854 003a 22F40042 		bic	r2, r2, #32768
+ 9855 003e 1A60     		str	r2, [r3]
+ 9856 0040 ECE7     		b	.L615
+ 9857              	.L619:
+5593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ 9858              		.loc 1 5593 5 is_stmt 1 view .LVU3443
+5593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ 9859              		.loc 1 5593 25 is_stmt 0 view .LVU3444
+ 9860 0042 2823     		movs	r3, #40
+ 9861 0044 84F84130 		strb	r3, [r4, #65]
+5594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9862              		.loc 1 5594 5 is_stmt 1 view .LVU3445
+5594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9863              		.loc 1 5594 25 is_stmt 0 view .LVU3446
+ 9864 0048 2123     		movs	r3, #33
+ 9865 004a 2363     		str	r3, [r4, #48]
+5597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9866              		.loc 1 5597 5 is_stmt 1 view .LVU3447
+ 9867 004c 0121     		movs	r1, #1
+ 9868 004e 2046     		mov	r0, r4
+ 9869              	.LVL668:
+5597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9870              		.loc 1 5597 5 is_stmt 0 view .LVU3448
+ 9871 0050 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9872              	.LVL669:
+5600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9873              		.loc 1 5600 5 is_stmt 1 view .LVU3449
+5600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9874              		.loc 1 5600 5 view .LVU3450
+ 9875 0054 0023     		movs	r3, #0
+ 9876 0056 84F84030 		strb	r3, [r4, #64]
+5600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9877              		.loc 1 5600 5 view .LVU3451
+5606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ARM GAS  /tmp/ccbUHtu7.s 			page 352
+
+
+ 9878              		.loc 1 5606 5 view .LVU3452
+ 9879 005a 2046     		mov	r0, r4
+ 9880 005c FFF7FEFF 		bl	HAL_I2C_SlaveTxCpltCallback
+ 9881              	.LVL670:
+ 9882 0060 E6E7     		b	.L613
+ 9883              	.LVL671:
+ 9884              	.L620:
+5613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ 9885              		.loc 1 5613 5 view .LVU3453
+5613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ 9886              		.loc 1 5613 25 is_stmt 0 view .LVU3454
+ 9887 0062 2823     		movs	r3, #40
+ 9888 0064 84F84130 		strb	r3, [r4, #65]
+5614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9889              		.loc 1 5614 5 is_stmt 1 view .LVU3455
+5614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9890              		.loc 1 5614 25 is_stmt 0 view .LVU3456
+ 9891 0068 2223     		movs	r3, #34
+ 9892 006a 2363     		str	r3, [r4, #48]
+5617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9893              		.loc 1 5617 5 is_stmt 1 view .LVU3457
+ 9894 006c 0221     		movs	r1, #2
+ 9895 006e 2046     		mov	r0, r4
+ 9896              	.LVL672:
+5617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9897              		.loc 1 5617 5 is_stmt 0 view .LVU3458
+ 9898 0070 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9899              	.LVL673:
+5620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9900              		.loc 1 5620 5 is_stmt 1 view .LVU3459
+5620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9901              		.loc 1 5620 5 view .LVU3460
+ 9902 0074 0023     		movs	r3, #0
+ 9903 0076 84F84030 		strb	r3, [r4, #64]
+5620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9904              		.loc 1 5620 5 view .LVU3461
+5626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 9905              		.loc 1 5626 5 view .LVU3462
+ 9906 007a 2046     		mov	r0, r4
+ 9907 007c FFF7FEFF 		bl	HAL_I2C_SlaveRxCpltCallback
+ 9908              	.LVL674:
+5632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 9909              		.loc 1 5632 3 view .LVU3463
+5633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9910              		.loc 1 5633 1 is_stmt 0 view .LVU3464
+ 9911 0080 D6E7     		b	.L613
+ 9912              		.cfi_endproc
+ 9913              	.LFE386:
+ 9915              		.section	.text.I2C_DMASlaveTransmitCplt,"ax",%progbits
+ 9916              		.align	1
+ 9917              		.syntax unified
+ 9918              		.thumb
+ 9919              		.thumb_func
+ 9921              	I2C_DMASlaveTransmitCplt:
+ 9922              	.LVL675:
+ 9923              	.LFB394:
+6216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ARM GAS  /tmp/ccbUHtu7.s 			page 353
+
+
+ 9924              		.loc 1 6216 1 is_stmt 1 view -0
+ 9925              		.cfi_startproc
+ 9926              		@ args = 0, pretend = 0, frame = 0
+ 9927              		@ frame_needed = 0, uses_anonymous_args = 0
+6216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 9928              		.loc 1 6216 1 is_stmt 0 view .LVU3466
+ 9929 0000 08B5     		push	{r3, lr}
+ 9930              	.LCFI114:
+ 9931              		.cfi_def_cfa_offset 8
+ 9932              		.cfi_offset 3, -8
+ 9933              		.cfi_offset 14, -4
+6218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 9934              		.loc 1 6218 3 is_stmt 1 view .LVU3467
+6218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 9935              		.loc 1 6218 22 is_stmt 0 view .LVU3468
+ 9936 0002 806A     		ldr	r0, [r0, #40]
+ 9937              	.LVL676:
+6219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9938              		.loc 1 6219 3 is_stmt 1 view .LVU3469
+6219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9939              		.loc 1 6219 12 is_stmt 0 view .LVU3470
+ 9940 0004 C36A     		ldr	r3, [r0, #44]
+ 9941              	.LVL677:
+6221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9942              		.loc 1 6221 3 is_stmt 1 view .LVU3471
+6221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9943              		.loc 1 6221 6 is_stmt 0 view .LVU3472
+ 9944 0006 B3F1807F 		cmp	r3, #16777216
+ 9945 000a 00D0     		beq	.L622
+6221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 9946              		.loc 1 6221 38 discriminator 1 view .LVU3473
+ 9947 000c 33B9     		cbnz	r3, .L621
+ 9948              	.L622:
+6224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9949              		.loc 1 6224 5 is_stmt 1 view .LVU3474
+6224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9950              		.loc 1 6224 9 is_stmt 0 view .LVU3475
+ 9951 000e 0268     		ldr	r2, [r0]
+6224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9952              		.loc 1 6224 19 view .LVU3476
+ 9953 0010 1368     		ldr	r3, [r2]
+ 9954              	.LVL678:
+6224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9955              		.loc 1 6224 25 view .LVU3477
+ 9956 0012 23F48043 		bic	r3, r3, #16384
+ 9957 0016 1360     		str	r3, [r2]
+6228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 9958              		.loc 1 6228 5 is_stmt 1 view .LVU3478
+ 9959 0018 FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 9960              	.LVL679:
+ 9961              	.L621:
+6236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9962              		.loc 1 6236 1 is_stmt 0 view .LVU3479
+ 9963 001c 08BD     		pop	{r3, pc}
+ 9964              		.cfi_endproc
+ 9965              	.LFE394:
+ 9967              		.section	.text.I2C_DMASlaveReceiveCplt,"ax",%progbits
+ARM GAS  /tmp/ccbUHtu7.s 			page 354
+
+
+ 9968              		.align	1
+ 9969              		.syntax unified
+ 9970              		.thumb
+ 9971              		.thumb_func
+ 9973              	I2C_DMASlaveReceiveCplt:
+ 9974              	.LVL680:
+ 9975              	.LFB396:
+6294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 9976              		.loc 1 6294 1 is_stmt 1 view -0
+ 9977              		.cfi_startproc
+ 9978              		@ args = 0, pretend = 0, frame = 0
+ 9979              		@ frame_needed = 0, uses_anonymous_args = 0
+6294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 9980              		.loc 1 6294 1 is_stmt 0 view .LVU3481
+ 9981 0000 08B5     		push	{r3, lr}
+ 9982              	.LCFI115:
+ 9983              		.cfi_def_cfa_offset 8
+ 9984              		.cfi_offset 3, -8
+ 9985              		.cfi_offset 14, -4
+6296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 9986              		.loc 1 6296 3 is_stmt 1 view .LVU3482
+6296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 9987              		.loc 1 6296 22 is_stmt 0 view .LVU3483
+ 9988 0002 806A     		ldr	r0, [r0, #40]
+ 9989              	.LVL681:
+6297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9990              		.loc 1 6297 3 is_stmt 1 view .LVU3484
+6297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 9991              		.loc 1 6297 12 is_stmt 0 view .LVU3485
+ 9992 0004 C26A     		ldr	r2, [r0, #44]
+ 9993              	.LVL682:
+6299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (tmpoptions != I2C_NO_OPTION_FRAME))
+ 9994              		.loc 1 6299 3 is_stmt 1 view .LVU3486
+6299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (tmpoptions != I2C_NO_OPTION_FRAME))
+ 9995              		.loc 1 6299 8 is_stmt 0 view .LVU3487
+ 9996 0006 C36B     		ldr	r3, [r0, #60]
+ 9997 0008 1B68     		ldr	r3, [r3]
+ 9998 000a 5B68     		ldr	r3, [r3, #4]
+6299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (tmpoptions != I2C_NO_OPTION_FRAME))
+ 9999              		.loc 1 6299 6 view .LVU3488
+ 10000 000c 13B9     		cbnz	r3, .L625
+6299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (tmpoptions != I2C_NO_OPTION_FRAME))
+ 10001              		.loc 1 6299 53 discriminator 1 view .LVU3489
+ 10002 000e 12F5803F 		cmn	r2, #65536
+ 10003 0012 00D1     		bne	.L628
+ 10004              	.LVL683:
+ 10005              	.L625:
+6314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10006              		.loc 1 6314 1 view .LVU3490
+ 10007 0014 08BD     		pop	{r3, pc}
+ 10008              	.LVL684:
+ 10009              	.L628:
+6303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10010              		.loc 1 6303 5 is_stmt 1 view .LVU3491
+6303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10011              		.loc 1 6303 9 is_stmt 0 view .LVU3492
+ 10012 0016 0268     		ldr	r2, [r0]
+ARM GAS  /tmp/ccbUHtu7.s 			page 355
+
+
+ 10013              	.LVL685:
+6303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10014              		.loc 1 6303 19 view .LVU3493
+ 10015 0018 1368     		ldr	r3, [r2]
+6303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10016              		.loc 1 6303 25 view .LVU3494
+ 10017 001a 23F40043 		bic	r3, r3, #32768
+ 10018 001e 1360     		str	r3, [r2]
+6306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10019              		.loc 1 6306 5 is_stmt 1 view .LVU3495
+ 10020 0020 FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 10021              	.LVL686:
+6313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 10022              		.loc 1 6313 3 view .LVU3496
+6314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10023              		.loc 1 6314 1 is_stmt 0 view .LVU3497
+ 10024 0024 F6E7     		b	.L625
+ 10025              		.cfi_endproc
+ 10026              	.LFE396:
+ 10028              		.section	.text.HAL_I2C_AddrCallback,"ax",%progbits
+ 10029              		.align	1
+ 10030              		.weak	HAL_I2C_AddrCallback
+ 10031              		.syntax unified
+ 10032              		.thumb
+ 10033              		.thumb_func
+ 10035              	HAL_I2C_AddrCallback:
+ 10036              	.LVL687:
+ 10037              	.LFB369:
+4579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10038              		.loc 1 4579 1 is_stmt 1 view -0
+ 10039              		.cfi_startproc
+ 10040              		@ args = 0, pretend = 0, frame = 0
+ 10041              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10042              		@ link register save eliminated.
+4581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(TransferDirection);
+ 10043              		.loc 1 4581 3 view .LVU3499
+4582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   UNUSED(AddrMatchCode);
+ 10044              		.loc 1 4582 3 view .LVU3500
+4583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10045              		.loc 1 4583 3 view .LVU3501
+4588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10046              		.loc 1 4588 1 is_stmt 0 view .LVU3502
+ 10047 0000 7047     		bx	lr
+ 10048              		.cfi_endproc
+ 10049              	.LFE369:
+ 10051              		.section	.text.I2C_ITAddrCplt,"ax",%progbits
+ 10052              		.align	1
+ 10053              		.syntax unified
+ 10054              		.thumb
+ 10055              		.thumb_func
+ 10057              	I2C_ITAddrCplt:
+ 10058              	.LVL688:
+ 10059              	.LFB384:
+5420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint8_t transferdirection;
+ 10060              		.loc 1 5420 1 is_stmt 1 view -0
+ 10061              		.cfi_startproc
+ 10062              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/ccbUHtu7.s 			page 356
+
+
+ 10063              		@ frame_needed = 0, uses_anonymous_args = 0
+5420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint8_t transferdirection;
+ 10064              		.loc 1 5420 1 is_stmt 0 view .LVU3504
+ 10065 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 10066              	.LCFI116:
+ 10067              		.cfi_def_cfa_offset 24
+ 10068              		.cfi_offset 3, -24
+ 10069              		.cfi_offset 4, -20
+ 10070              		.cfi_offset 5, -16
+ 10071              		.cfi_offset 6, -12
+ 10072              		.cfi_offset 7, -8
+ 10073              		.cfi_offset 14, -4
+ 10074 0002 0446     		mov	r4, r0
+5421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint16_t slaveaddrcode;
+ 10075              		.loc 1 5421 3 is_stmt 1 view .LVU3505
+5422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint16_t ownadd1code;
+ 10076              		.loc 1 5422 3 view .LVU3506
+5423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint16_t ownadd2code;
+ 10077              		.loc 1 5423 3 view .LVU3507
+5424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10078              		.loc 1 5424 3 view .LVU3508
+5427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10079              		.loc 1 5427 3 view .LVU3509
+5430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10080              		.loc 1 5430 3 view .LVU3510
+5430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10081              		.loc 1 5430 22 is_stmt 0 view .LVU3511
+ 10082 0004 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+5430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10083              		.loc 1 5430 6 view .LVU3512
+ 10084 0008 03F02803 		and	r3, r3, #40
+ 10085 000c 282B     		cmp	r3, #40
+ 10086 000e 06D0     		beq	.L636
+5502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10087              		.loc 1 5502 5 is_stmt 1 view .LVU3513
+ 10088 0010 0368     		ldr	r3, [r0]
+ 10089 0012 0822     		movs	r2, #8
+ 10090 0014 DA61     		str	r2, [r3, #28]
+5505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10091              		.loc 1 5505 5 view .LVU3514
+5505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10092              		.loc 1 5505 5 view .LVU3515
+ 10093 0016 0023     		movs	r3, #0
+ 10094 0018 80F84030 		strb	r3, [r0, #64]
+5505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10095              		.loc 1 5505 5 view .LVU3516
+ 10096              	.LVL689:
+ 10097              	.L630:
+5507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10098              		.loc 1 5507 1 is_stmt 0 view .LVU3517
+ 10099 001c F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 10100              	.LVL690:
+ 10101              	.L636:
+5432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+ 10102              		.loc 1 5432 5 is_stmt 1 view .LVU3518
+5432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+ 10103              		.loc 1 5432 25 is_stmt 0 view .LVU3519
+ARM GAS  /tmp/ccbUHtu7.s 			page 357
+
+
+ 10104 001e 0368     		ldr	r3, [r0]
+ 10105 0020 9E69     		ldr	r6, [r3, #24]
+5432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+ 10106              		.loc 1 5432 23 view .LVU3520
+ 10107 0022 C6F30046 		ubfx	r6, r6, #16, #1
+ 10108              	.LVL691:
+5433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+ 10109              		.loc 1 5433 5 is_stmt 1 view .LVU3521
+5433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+ 10110              		.loc 1 5433 25 is_stmt 0 view .LVU3522
+ 10111 0026 9A69     		ldr	r2, [r3, #24]
+ 10112 0028 120C     		lsrs	r2, r2, #16
+5433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+ 10113              		.loc 1 5433 23 view .LVU3523
+ 10114 002a 02F0FE05 		and	r5, r2, #254
+ 10115              	.LVL692:
+5434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+ 10116              		.loc 1 5434 5 is_stmt 1 view .LVU3524
+5434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+ 10117              		.loc 1 5434 25 is_stmt 0 view .LVU3525
+ 10118 002e 9A68     		ldr	r2, [r3, #8]
+5434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+ 10119              		.loc 1 5434 23 view .LVU3526
+ 10120 0030 C2F30902 		ubfx	r2, r2, #0, #10
+ 10121              	.LVL693:
+5435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10122              		.loc 1 5435 5 is_stmt 1 view .LVU3527
+5435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10123              		.loc 1 5435 25 is_stmt 0 view .LVU3528
+ 10124 0034 DF68     		ldr	r7, [r3, #12]
+5435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10125              		.loc 1 5435 23 view .LVU3529
+ 10126 0036 07F0FE07 		and	r7, r7, #254
+ 10127              	.LVL694:
+5438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10128              		.loc 1 5438 5 is_stmt 1 view .LVU3530
+5438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10129              		.loc 1 5438 19 is_stmt 0 view .LVU3531
+ 10130 003a C168     		ldr	r1, [r0, #12]
+ 10131              	.LVL695:
+5438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10132              		.loc 1 5438 8 view .LVU3532
+ 10133 003c 0229     		cmp	r1, #2
+ 10134 003e 22D1     		bne	.L632
+5440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 10135              		.loc 1 5440 7 is_stmt 1 view .LVU3533
+5440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 10136              		.loc 1 5440 44 is_stmt 0 view .LVU3534
+ 10137 0040 85EAD215 		eor	r5, r5, r2, lsr #7
+ 10138              	.LVL696:
+5440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 10139              		.loc 1 5440 10 view .LVU3535
+ 10140 0044 15F0060F 		tst	r5, #6
+ 10141 0048 10D1     		bne	.L633
+5442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         hi2c->AddrEventCount++;
+ 10142              		.loc 1 5442 9 is_stmt 1 view .LVU3536
+ 10143              	.LVL697:
+ARM GAS  /tmp/ccbUHtu7.s 			page 358
+
+
+5443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->AddrEventCount == 2U)
+ 10144              		.loc 1 5443 9 view .LVU3537
+5443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->AddrEventCount == 2U)
+ 10145              		.loc 1 5443 13 is_stmt 0 view .LVU3538
+ 10146 004a 816C     		ldr	r1, [r0, #72]
+5443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->AddrEventCount == 2U)
+ 10147              		.loc 1 5443 29 view .LVU3539
+ 10148 004c 0131     		adds	r1, r1, #1
+ 10149 004e 8164     		str	r1, [r0, #72]
+5444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 10150              		.loc 1 5444 9 is_stmt 1 view .LVU3540
+5444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 10151              		.loc 1 5444 17 is_stmt 0 view .LVU3541
+ 10152 0050 816C     		ldr	r1, [r0, #72]
+5444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 10153              		.loc 1 5444 12 view .LVU3542
+ 10154 0052 0229     		cmp	r1, #2
+ 10155 0054 E2D1     		bne	.L630
+5447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10156              		.loc 1 5447 11 is_stmt 1 view .LVU3543
+5447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10157              		.loc 1 5447 32 is_stmt 0 view .LVU3544
+ 10158 0056 0021     		movs	r1, #0
+ 10159 0058 8164     		str	r1, [r0, #72]
+5450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10160              		.loc 1 5450 11 is_stmt 1 view .LVU3545
+ 10161 005a 0820     		movs	r0, #8
+ 10162              	.LVL698:
+5450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10163              		.loc 1 5450 11 is_stmt 0 view .LVU3546
+ 10164 005c D861     		str	r0, [r3, #28]
+5453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10165              		.loc 1 5453 11 is_stmt 1 view .LVU3547
+5453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10166              		.loc 1 5453 11 view .LVU3548
+ 10167 005e 84F84010 		strb	r1, [r4, #64]
+5453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10168              		.loc 1 5453 11 view .LVU3549
+5459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10169              		.loc 1 5459 11 view .LVU3550
+ 10170 0062 3146     		mov	r1, r6
+ 10171 0064 2046     		mov	r0, r4
+ 10172 0066 FFF7FEFF 		bl	HAL_I2C_AddrCallback
+ 10173              	.LVL699:
+5459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10174              		.loc 1 5459 11 is_stmt 0 view .LVU3551
+ 10175 006a D7E7     		b	.L630
+ 10176              	.LVL700:
+ 10177              	.L633:
+5465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10178              		.loc 1 5465 9 is_stmt 1 view .LVU3552
+5468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10179              		.loc 1 5468 9 view .LVU3553
+ 10180 006c 4FF40041 		mov	r1, #32768
+ 10181 0070 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10182              	.LVL701:
+5471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 359
+
+
+ 10183              		.loc 1 5471 9 view .LVU3554
+5471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10184              		.loc 1 5471 9 view .LVU3555
+ 10185 0074 0023     		movs	r3, #0
+ 10186 0076 84F84030 		strb	r3, [r4, #64]
+5471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10187              		.loc 1 5471 9 view .LVU3556
+5477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10188              		.loc 1 5477 9 view .LVU3557
+ 10189 007a 3A46     		mov	r2, r7
+ 10190 007c 3146     		mov	r1, r6
+ 10191 007e 2046     		mov	r0, r4
+ 10192 0080 FFF7FEFF 		bl	HAL_I2C_AddrCallback
+ 10193              	.LVL702:
+ 10194 0084 CAE7     		b	.L630
+ 10195              	.LVL703:
+ 10196              	.L632:
+5485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10197              		.loc 1 5485 7 view .LVU3558
+ 10198 0086 4FF40041 		mov	r1, #32768
+ 10199 008a FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10200              	.LVL704:
+5488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10201              		.loc 1 5488 7 view .LVU3559
+5488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10202              		.loc 1 5488 7 view .LVU3560
+ 10203 008e 0023     		movs	r3, #0
+ 10204 0090 84F84030 		strb	r3, [r4, #64]
+5488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10205              		.loc 1 5488 7 view .LVU3561
+5494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10206              		.loc 1 5494 7 view .LVU3562
+ 10207 0094 2A46     		mov	r2, r5
+ 10208 0096 3146     		mov	r1, r6
+ 10209 0098 2046     		mov	r0, r4
+ 10210 009a FFF7FEFF 		bl	HAL_I2C_AddrCallback
+ 10211              	.LVL705:
+ 10212 009e BDE7     		b	.L630
+ 10213              		.cfi_endproc
+ 10214              	.LFE384:
+ 10216              		.section	.text.HAL_I2C_ListenCpltCallback,"ax",%progbits
+ 10217              		.align	1
+ 10218              		.weak	HAL_I2C_ListenCpltCallback
+ 10219              		.syntax unified
+ 10220              		.thumb
+ 10221              		.thumb_func
+ 10223              	HAL_I2C_ListenCpltCallback:
+ 10224              	.LVL706:
+ 10225              	.LFB370:
+4597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10226              		.loc 1 4597 1 view -0
+ 10227              		.cfi_startproc
+ 10228              		@ args = 0, pretend = 0, frame = 0
+ 10229              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10230              		@ link register save eliminated.
+4599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10231              		.loc 1 4599 3 view .LVU3564
+ARM GAS  /tmp/ccbUHtu7.s 			page 360
+
+
+4604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10232              		.loc 1 4604 1 is_stmt 0 view .LVU3565
+ 10233 0000 7047     		bx	lr
+ 10234              		.cfi_endproc
+ 10235              	.LFE370:
+ 10237              		.section	.text.I2C_ITListenCplt,"ax",%progbits
+ 10238              		.align	1
+ 10239              		.syntax unified
+ 10240              		.thumb
+ 10241              		.thumb_func
+ 10243              	I2C_ITListenCplt:
+ 10244              	.LVL707:
+ 10245              	.LFB389:
+5944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Reset handle parameters */
+ 10246              		.loc 1 5944 1 is_stmt 1 view -0
+ 10247              		.cfi_startproc
+ 10248              		@ args = 0, pretend = 0, frame = 0
+ 10249              		@ frame_needed = 0, uses_anonymous_args = 0
+5944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Reset handle parameters */
+ 10250              		.loc 1 5944 1 is_stmt 0 view .LVU3567
+ 10251 0000 10B5     		push	{r4, lr}
+ 10252              	.LCFI117:
+ 10253              		.cfi_def_cfa_offset 8
+ 10254              		.cfi_offset 4, -8
+ 10255              		.cfi_offset 14, -4
+ 10256 0002 0446     		mov	r4, r0
+5946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 10257              		.loc 1 5946 3 is_stmt 1 view .LVU3568
+5946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 10258              		.loc 1 5946 21 is_stmt 0 view .LVU3569
+ 10259 0004 174B     		ldr	r3, .L641
+ 10260 0006 C362     		str	r3, [r0, #44]
+5947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_READY;
+ 10261              		.loc 1 5947 3 is_stmt 1 view .LVU3570
+5947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_READY;
+ 10262              		.loc 1 5947 23 is_stmt 0 view .LVU3571
+ 10263 0008 0023     		movs	r3, #0
+ 10264 000a 0363     		str	r3, [r0, #48]
+5948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 10265              		.loc 1 5948 3 is_stmt 1 view .LVU3572
+5948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 10266              		.loc 1 5948 15 is_stmt 0 view .LVU3573
+ 10267 000c 2022     		movs	r2, #32
+ 10268 000e 80F84120 		strb	r2, [r0, #65]
+5949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferISR = NULL;
+ 10269              		.loc 1 5949 3 is_stmt 1 view .LVU3574
+5949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferISR = NULL;
+ 10270              		.loc 1 5949 14 is_stmt 0 view .LVU3575
+ 10271 0012 80F84230 		strb	r3, [r0, #66]
+5950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10272              		.loc 1 5950 3 is_stmt 1 view .LVU3576
+5950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10273              		.loc 1 5950 17 is_stmt 0 view .LVU3577
+ 10274 0016 4363     		str	r3, [r0, #52]
+5953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10275              		.loc 1 5953 3 is_stmt 1 view .LVU3578
+5953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccbUHtu7.s 			page 361
+
+
+ 10276              		.loc 1 5953 6 is_stmt 0 view .LVU3579
+ 10277 0018 11F0040F 		tst	r1, #4
+ 10278 001c 13D0     		beq	.L639
+5956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10279              		.loc 1 5956 5 is_stmt 1 view .LVU3580
+5956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10280              		.loc 1 5956 36 is_stmt 0 view .LVU3581
+ 10281 001e 0368     		ldr	r3, [r0]
+5956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10282              		.loc 1 5956 46 view .LVU3582
+ 10283 0020 5A6A     		ldr	r2, [r3, #36]
+5956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10284              		.loc 1 5956 10 view .LVU3583
+ 10285 0022 436A     		ldr	r3, [r0, #36]
+5956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10286              		.loc 1 5956 21 view .LVU3584
+ 10287 0024 1A70     		strb	r2, [r3]
+5959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10288              		.loc 1 5959 5 is_stmt 1 view .LVU3585
+5959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10289              		.loc 1 5959 9 is_stmt 0 view .LVU3586
+ 10290 0026 436A     		ldr	r3, [r0, #36]
+5959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10291              		.loc 1 5959 19 view .LVU3587
+ 10292 0028 0133     		adds	r3, r3, #1
+ 10293 002a 4362     		str	r3, [r0, #36]
+5961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10294              		.loc 1 5961 5 is_stmt 1 view .LVU3588
+5961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10295              		.loc 1 5961 14 is_stmt 0 view .LVU3589
+ 10296 002c 038D     		ldrh	r3, [r0, #40]
+5961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10297              		.loc 1 5961 8 view .LVU3590
+ 10298 002e 53B1     		cbz	r3, .L639
+5963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 10299              		.loc 1 5963 7 is_stmt 1 view .LVU3591
+5963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 10300              		.loc 1 5963 21 is_stmt 0 view .LVU3592
+ 10301 0030 013B     		subs	r3, r3, #1
+ 10302 0032 0385     		strh	r3, [r0, #40]	@ movhi
+5964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10303              		.loc 1 5964 7 is_stmt 1 view .LVU3593
+5964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10304              		.loc 1 5964 11 is_stmt 0 view .LVU3594
+ 10305 0034 438D     		ldrh	r3, [r0, #42]
+ 10306 0036 9BB2     		uxth	r3, r3
+5964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10307              		.loc 1 5964 22 view .LVU3595
+ 10308 0038 013B     		subs	r3, r3, #1
+ 10309 003a 9BB2     		uxth	r3, r3
+ 10310 003c 4385     		strh	r3, [r0, #42]	@ movhi
+5967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10311              		.loc 1 5967 7 is_stmt 1 view .LVU3596
+5967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10312              		.loc 1 5967 11 is_stmt 0 view .LVU3597
+ 10313 003e 436C     		ldr	r3, [r0, #68]
+5967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ARM GAS  /tmp/ccbUHtu7.s 			page 362
+
+
+ 10314              		.loc 1 5967 23 view .LVU3598
+ 10315 0040 43F00403 		orr	r3, r3, #4
+ 10316 0044 4364     		str	r3, [r0, #68]
+ 10317              	.L639:
+5972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10318              		.loc 1 5972 3 is_stmt 1 view .LVU3599
+ 10319 0046 48F20301 		movw	r1, #32771
+ 10320              	.LVL708:
+5972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10321              		.loc 1 5972 3 is_stmt 0 view .LVU3600
+ 10322 004a 2046     		mov	r0, r4
+ 10323              	.LVL709:
+5972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10324              		.loc 1 5972 3 view .LVU3601
+ 10325 004c FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10326              	.LVL710:
+5975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10327              		.loc 1 5975 3 is_stmt 1 view .LVU3602
+ 10328 0050 2368     		ldr	r3, [r4]
+ 10329 0052 1022     		movs	r2, #16
+ 10330 0054 DA61     		str	r2, [r3, #28]
+5978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10331              		.loc 1 5978 3 view .LVU3603
+5978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10332              		.loc 1 5978 3 view .LVU3604
+ 10333 0056 0023     		movs	r3, #0
+ 10334 0058 84F84030 		strb	r3, [r4, #64]
+5978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10335              		.loc 1 5978 3 view .LVU3605
+5984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10336              		.loc 1 5984 3 view .LVU3606
+ 10337 005c 2046     		mov	r0, r4
+ 10338 005e FFF7FEFF 		bl	HAL_I2C_ListenCpltCallback
+ 10339              	.LVL711:
+5986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10340              		.loc 1 5986 1 is_stmt 0 view .LVU3607
+ 10341 0062 10BD     		pop	{r4, pc}
+ 10342              	.LVL712:
+ 10343              	.L642:
+5986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10344              		.loc 1 5986 1 view .LVU3608
+ 10345              		.align	2
+ 10346              	.L641:
+ 10347 0064 0000FFFF 		.word	-65536
+ 10348              		.cfi_endproc
+ 10349              	.LFE389:
+ 10351              		.section	.text.HAL_I2C_MemTxCpltCallback,"ax",%progbits
+ 10352              		.align	1
+ 10353              		.weak	HAL_I2C_MemTxCpltCallback
+ 10354              		.syntax unified
+ 10355              		.thumb
+ 10356              		.thumb_func
+ 10358              	HAL_I2C_MemTxCpltCallback:
+ 10359              	.LVL713:
+ 10360              	.LFB371:
+4613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10361              		.loc 1 4613 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccbUHtu7.s 			page 363
+
+
+ 10362              		.cfi_startproc
+ 10363              		@ args = 0, pretend = 0, frame = 0
+ 10364              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10365              		@ link register save eliminated.
+4615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10366              		.loc 1 4615 3 view .LVU3610
+4620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10367              		.loc 1 4620 1 is_stmt 0 view .LVU3611
+ 10368 0000 7047     		bx	lr
+ 10369              		.cfi_endproc
+ 10370              	.LFE371:
+ 10372              		.section	.text.HAL_I2C_MemRxCpltCallback,"ax",%progbits
+ 10373              		.align	1
+ 10374              		.weak	HAL_I2C_MemRxCpltCallback
+ 10375              		.syntax unified
+ 10376              		.thumb
+ 10377              		.thumb_func
+ 10379              	HAL_I2C_MemRxCpltCallback:
+ 10380              	.LVL714:
+ 10381              	.LFB372:
+4629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10382              		.loc 1 4629 1 is_stmt 1 view -0
+ 10383              		.cfi_startproc
+ 10384              		@ args = 0, pretend = 0, frame = 0
+ 10385              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10386              		@ link register save eliminated.
+4631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10387              		.loc 1 4631 3 view .LVU3613
+4636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10388              		.loc 1 4636 1 is_stmt 0 view .LVU3614
+ 10389 0000 7047     		bx	lr
+ 10390              		.cfi_endproc
+ 10391              	.LFE372:
+ 10393              		.section	.text.HAL_I2C_ErrorCallback,"ax",%progbits
+ 10394              		.align	1
+ 10395              		.weak	HAL_I2C_ErrorCallback
+ 10396              		.syntax unified
+ 10397              		.thumb
+ 10398              		.thumb_func
+ 10400              	HAL_I2C_ErrorCallback:
+ 10401              	.LVL715:
+ 10402              	.LFB373:
+4645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10403              		.loc 1 4645 1 is_stmt 1 view -0
+ 10404              		.cfi_startproc
+ 10405              		@ args = 0, pretend = 0, frame = 0
+ 10406              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10407              		@ link register save eliminated.
+4647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10408              		.loc 1 4647 3 view .LVU3616
+4652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10409              		.loc 1 4652 1 is_stmt 0 view .LVU3617
+ 10410 0000 7047     		bx	lr
+ 10411              		.cfi_endproc
+ 10412              	.LFE373:
+ 10414              		.section	.text.HAL_I2C_AbortCpltCallback,"ax",%progbits
+ 10415              		.align	1
+ARM GAS  /tmp/ccbUHtu7.s 			page 364
+
+
+ 10416              		.weak	HAL_I2C_AbortCpltCallback
+ 10417              		.syntax unified
+ 10418              		.thumb
+ 10419              		.thumb_func
+ 10421              	HAL_I2C_AbortCpltCallback:
+ 10422              	.LVL716:
+ 10423              	.LFB374:
+4661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10424              		.loc 1 4661 1 is_stmt 1 view -0
+ 10425              		.cfi_startproc
+ 10426              		@ args = 0, pretend = 0, frame = 0
+ 10427              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10428              		@ link register save eliminated.
+4663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10429              		.loc 1 4663 3 view .LVU3619
+4668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10430              		.loc 1 4668 1 is_stmt 0 view .LVU3620
+ 10431 0000 7047     		bx	lr
+ 10432              		.cfi_endproc
+ 10433              	.LFE374:
+ 10435              		.section	.text.I2C_TreatErrorCallback,"ax",%progbits
+ 10436              		.align	1
+ 10437              		.syntax unified
+ 10438              		.thumb
+ 10439              		.thumb_func
+ 10441              	I2C_TreatErrorCallback:
+ 10442              	.LVL717:
+ 10443              	.LFB391:
+6107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_ABORT)
+ 10444              		.loc 1 6107 1 is_stmt 1 view -0
+ 10445              		.cfi_startproc
+ 10446              		@ args = 0, pretend = 0, frame = 0
+ 10447              		@ frame_needed = 0, uses_anonymous_args = 0
+6107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_ABORT)
+ 10448              		.loc 1 6107 1 is_stmt 0 view .LVU3622
+ 10449 0000 08B5     		push	{r3, lr}
+ 10450              	.LCFI118:
+ 10451              		.cfi_def_cfa_offset 8
+ 10452              		.cfi_offset 3, -8
+ 10453              		.cfi_offset 14, -4
+6108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10454              		.loc 1 6108 3 is_stmt 1 view .LVU3623
+6108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10455              		.loc 1 6108 11 is_stmt 0 view .LVU3624
+ 10456 0002 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 10457 0006 DBB2     		uxtb	r3, r3
+6108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10458              		.loc 1 6108 6 view .LVU3625
+ 10459 0008 602B     		cmp	r3, #96
+ 10460 000a 06D0     		beq	.L651
+6125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10461              		.loc 1 6125 5 is_stmt 1 view .LVU3626
+6125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10462              		.loc 1 6125 25 is_stmt 0 view .LVU3627
+ 10463 000c 0023     		movs	r3, #0
+ 10464 000e 0363     		str	r3, [r0, #48]
+6128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 365
+
+
+ 10465              		.loc 1 6128 5 is_stmt 1 view .LVU3628
+6128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10466              		.loc 1 6128 5 view .LVU3629
+ 10467 0010 80F84030 		strb	r3, [r0, #64]
+6128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10468              		.loc 1 6128 5 view .LVU3630
+6134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10469              		.loc 1 6134 5 view .LVU3631
+ 10470 0014 FFF7FEFF 		bl	HAL_I2C_ErrorCallback
+ 10471              	.LVL718:
+ 10472              	.L647:
+6137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10473              		.loc 1 6137 1 is_stmt 0 view .LVU3632
+ 10474 0018 08BD     		pop	{r3, pc}
+ 10475              	.LVL719:
+ 10476              	.L651:
+6110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 10477              		.loc 1 6110 5 is_stmt 1 view .LVU3633
+6110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 10478              		.loc 1 6110 17 is_stmt 0 view .LVU3634
+ 10479 001a 2023     		movs	r3, #32
+ 10480 001c 80F84130 		strb	r3, [r0, #65]
+6111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10481              		.loc 1 6111 5 is_stmt 1 view .LVU3635
+6111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10482              		.loc 1 6111 25 is_stmt 0 view .LVU3636
+ 10483 0020 0023     		movs	r3, #0
+ 10484 0022 0363     		str	r3, [r0, #48]
+6114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10485              		.loc 1 6114 5 is_stmt 1 view .LVU3637
+6114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10486              		.loc 1 6114 5 view .LVU3638
+ 10487 0024 80F84030 		strb	r3, [r0, #64]
+6114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10488              		.loc 1 6114 5 view .LVU3639
+6120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10489              		.loc 1 6120 5 view .LVU3640
+ 10490 0028 FFF7FEFF 		bl	HAL_I2C_AbortCpltCallback
+ 10491              	.LVL720:
+6120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10492              		.loc 1 6120 5 is_stmt 0 view .LVU3641
+ 10493 002c F4E7     		b	.L647
+ 10494              		.cfi_endproc
+ 10495              	.LFE391:
+ 10497              		.section	.text.I2C_ITError,"ax",%progbits
+ 10498              		.align	1
+ 10499              		.syntax unified
+ 10500              		.thumb
+ 10501              		.thumb_func
+ 10503              	I2C_ITError:
+ 10504              	.LVL721:
+ 10505              	.LFB390:
+5995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ 10506              		.loc 1 5995 1 is_stmt 1 view -0
+ 10507              		.cfi_startproc
+ 10508              		@ args = 0, pretend = 0, frame = 0
+ 10509              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccbUHtu7.s 			page 366
+
+
+5995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ 10510              		.loc 1 5995 1 is_stmt 0 view .LVU3643
+ 10511 0000 10B5     		push	{r4, lr}
+ 10512              	.LCFI119:
+ 10513              		.cfi_def_cfa_offset 8
+ 10514              		.cfi_offset 4, -8
+ 10515              		.cfi_offset 14, -4
+ 10516 0002 0446     		mov	r4, r0
+5996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmppreviousstate;
+ 10517              		.loc 1 5996 3 is_stmt 1 view .LVU3644
+5996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmppreviousstate;
+ 10518              		.loc 1 5996 24 is_stmt 0 view .LVU3645
+ 10519 0004 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 10520              	.LVL722:
+5997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10521              		.loc 1 5997 3 is_stmt 1 view .LVU3646
+6000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+ 10522              		.loc 1 6000 3 view .LVU3647
+6000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+ 10523              		.loc 1 6000 23 is_stmt 0 view .LVU3648
+ 10524 0008 0022     		movs	r2, #0
+ 10525 000a 80F84220 		strb	r2, [r0, #66]
+6001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferCount     = 0U;
+ 10526              		.loc 1 6001 3 is_stmt 1 view .LVU3649
+6001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferCount     = 0U;
+ 10527              		.loc 1 6001 23 is_stmt 0 view .LVU3650
+ 10528 000e 3B48     		ldr	r0, .L666
+ 10529              	.LVL723:
+6001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferCount     = 0U;
+ 10530              		.loc 1 6001 23 view .LVU3651
+ 10531 0010 E062     		str	r0, [r4, #44]
+6002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10532              		.loc 1 6002 3 is_stmt 1 view .LVU3652
+6002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10533              		.loc 1 6002 23 is_stmt 0 view .LVU3653
+ 10534 0012 6285     		strh	r2, [r4, #42]	@ movhi
+6005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10535              		.loc 1 6005 3 is_stmt 1 view .LVU3654
+6005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10536              		.loc 1 6005 7 is_stmt 0 view .LVU3655
+ 10537 0014 626C     		ldr	r2, [r4, #68]
+6005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10538              		.loc 1 6005 19 view .LVU3656
+ 10539 0016 0A43     		orrs	r2, r2, r1
+ 10540 0018 6264     		str	r2, [r4, #68]
+6008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ 10541              		.loc 1 6008 3 is_stmt 1 view .LVU3657
+6009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ 10542              		.loc 1 6009 50 is_stmt 0 view .LVU3658
+ 10543 001a 283B     		subs	r3, r3, #40
+ 10544              	.LVL724:
+6009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ 10545              		.loc 1 6009 50 view .LVU3659
+ 10546 001c DBB2     		uxtb	r3, r3
+6008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ 10547              		.loc 1 6008 6 view .LVU3660
+ 10548 001e 022B     		cmp	r3, #2
+ARM GAS  /tmp/ccbUHtu7.s 			page 367
+
+
+ 10549 0020 19D8     		bhi	.L653
+6013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10550              		.loc 1 6013 5 is_stmt 1 view .LVU3661
+ 10551 0022 0321     		movs	r1, #3
+ 10552              	.LVL725:
+6013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10553              		.loc 1 6013 5 is_stmt 0 view .LVU3662
+ 10554 0024 2046     		mov	r0, r4
+ 10555 0026 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10556              	.LVL726:
+6016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR       = I2C_Slave_ISR_IT;
+ 10557              		.loc 1 6016 5 is_stmt 1 view .LVU3663
+6016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferISR       = I2C_Slave_ISR_IT;
+ 10558              		.loc 1 6016 25 is_stmt 0 view .LVU3664
+ 10559 002a 2823     		movs	r3, #40
+ 10560 002c 84F84130 		strb	r3, [r4, #65]
+6017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10561              		.loc 1 6017 5 is_stmt 1 view .LVU3665
+6017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10562              		.loc 1 6017 25 is_stmt 0 view .LVU3666
+ 10563 0030 334B     		ldr	r3, .L666+4
+ 10564 0032 6363     		str	r3, [r4, #52]
+ 10565              	.L654:
+6035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
+ 10566              		.loc 1 6035 3 is_stmt 1 view .LVU3667
+6035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
+ 10567              		.loc 1 6035 20 is_stmt 0 view .LVU3668
+ 10568 0034 236B     		ldr	r3, [r4, #48]
+ 10569              	.LVL727:
+6036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ 10570              		.loc 1 6036 3 is_stmt 1 view .LVU3669
+6036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ 10571              		.loc 1 6036 12 is_stmt 0 view .LVU3670
+ 10572 0036 A26B     		ldr	r2, [r4, #56]
+6036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ 10573              		.loc 1 6036 6 view .LVU3671
+ 10574 0038 1AB1     		cbz	r2, .L656
+6036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ 10575              		.loc 1 6036 30 discriminator 1 view .LVU3672
+ 10576 003a 112B     		cmp	r3, #17
+ 10577 003c 1BD0     		beq	.L657
+6036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ 10578              		.loc 1 6036 81 discriminator 2 view .LVU3673
+ 10579 003e 212B     		cmp	r3, #33
+ 10580 0040 19D0     		beq	.L657
+ 10581              	.L656:
+6066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ 10582              		.loc 1 6066 8 is_stmt 1 view .LVU3674
+6066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ 10583              		.loc 1 6066 17 is_stmt 0 view .LVU3675
+ 10584 0042 E26B     		ldr	r2, [r4, #60]
+6066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ 10585              		.loc 1 6066 11 view .LVU3676
+ 10586 0044 1AB1     		cbz	r2, .L661
+6066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ 10587              		.loc 1 6066 35 discriminator 1 view .LVU3677
+ 10588 0046 122B     		cmp	r3, #18
+ARM GAS  /tmp/ccbUHtu7.s 			page 368
+
+
+ 10589 0048 36D0     		beq	.L662
+6066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ 10590              		.loc 1 6066 86 discriminator 2 view .LVU3678
+ 10591 004a 222B     		cmp	r3, #34
+ 10592 004c 34D0     		beq	.L662
+ 10593              	.L661:
+6097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10594              		.loc 1 6097 5 is_stmt 1 view .LVU3679
+ 10595 004e 2046     		mov	r0, r4
+ 10596 0050 FFF7FEFF 		bl	I2C_TreatErrorCallback
+ 10597              	.LVL728:
+ 10598              	.L652:
+6099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10599              		.loc 1 6099 1 is_stmt 0 view .LVU3680
+ 10600 0054 10BD     		pop	{r4, pc}
+ 10601              	.LVL729:
+ 10602              	.L653:
+6022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10603              		.loc 1 6022 5 is_stmt 1 view .LVU3681
+ 10604 0056 48F20301 		movw	r1, #32771
+ 10605              	.LVL730:
+6022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10606              		.loc 1 6022 5 is_stmt 0 view .LVU3682
+ 10607 005a 2046     		mov	r0, r4
+ 10608 005c FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10609              	.LVL731:
+6026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10610              		.loc 1 6026 5 is_stmt 1 view .LVU3683
+6026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10611              		.loc 1 6026 13 is_stmt 0 view .LVU3684
+ 10612 0060 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 10613 0064 DBB2     		uxtb	r3, r3
+6026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10614              		.loc 1 6026 8 view .LVU3685
+ 10615 0066 602B     		cmp	r3, #96
+ 10616 0068 02D0     		beq	.L655
+6029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10617              		.loc 1 6029 7 is_stmt 1 view .LVU3686
+6029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10618              		.loc 1 6029 27 is_stmt 0 view .LVU3687
+ 10619 006a 2023     		movs	r3, #32
+ 10620 006c 84F84130 		strb	r3, [r4, #65]
+ 10621              	.L655:
+6031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10622              		.loc 1 6031 5 is_stmt 1 view .LVU3688
+6031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10623              		.loc 1 6031 25 is_stmt 0 view .LVU3689
+ 10624 0070 0023     		movs	r3, #0
+ 10625 0072 6363     		str	r3, [r4, #52]
+ 10626 0074 DEE7     		b	.L654
+ 10627              	.LVL732:
+ 10628              	.L657:
+6039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10629              		.loc 1 6039 5 is_stmt 1 view .LVU3690
+6039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10630              		.loc 1 6039 14 is_stmt 0 view .LVU3691
+ 10631 0076 2368     		ldr	r3, [r4]
+ARM GAS  /tmp/ccbUHtu7.s 			page 369
+
+
+ 10632              	.LVL733:
+6039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10633              		.loc 1 6039 24 view .LVU3692
+ 10634 0078 1A68     		ldr	r2, [r3]
+6039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10635              		.loc 1 6039 8 view .LVU3693
+ 10636 007a 12F4804F 		tst	r2, #16384
+ 10637 007e 03D0     		beq	.L658
+6041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10638              		.loc 1 6041 7 is_stmt 1 view .LVU3694
+6041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10639              		.loc 1 6041 21 is_stmt 0 view .LVU3695
+ 10640 0080 1A68     		ldr	r2, [r3]
+6041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10641              		.loc 1 6041 27 view .LVU3696
+ 10642 0082 22F48042 		bic	r2, r2, #16384
+ 10643 0086 1A60     		str	r2, [r3]
+ 10644              	.L658:
+6044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10645              		.loc 1 6044 5 is_stmt 1 view .LVU3697
+6044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10646              		.loc 1 6044 9 is_stmt 0 view .LVU3698
+ 10647 0088 A06B     		ldr	r0, [r4, #56]
+ 10648 008a FFF7FEFF 		bl	HAL_DMA_GetState
+ 10649              	.LVL734:
+6044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10650              		.loc 1 6044 8 view .LVU3699
+ 10651 008e 0128     		cmp	r0, #1
+ 10652 0090 0ED0     		beq	.L659
+6048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10653              		.loc 1 6048 7 is_stmt 1 view .LVU3700
+6048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10654              		.loc 1 6048 11 is_stmt 0 view .LVU3701
+ 10655 0092 A36B     		ldr	r3, [r4, #56]
+6048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10656              		.loc 1 6048 39 view .LVU3702
+ 10657 0094 1B4A     		ldr	r2, .L666+8
+ 10658 0096 9A63     		str	r2, [r3, #56]
+6051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10659              		.loc 1 6051 7 is_stmt 1 view .LVU3703
+6051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10660              		.loc 1 6051 7 view .LVU3704
+ 10661 0098 0023     		movs	r3, #0
+ 10662 009a 84F84030 		strb	r3, [r4, #64]
+6051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10663              		.loc 1 6051 7 view .LVU3705
+6054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 10664              		.loc 1 6054 7 view .LVU3706
+6054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 10665              		.loc 1 6054 11 is_stmt 0 view .LVU3707
+ 10666 009e A06B     		ldr	r0, [r4, #56]
+ 10667 00a0 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 10668              	.LVL735:
+6054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 10669              		.loc 1 6054 10 view .LVU3708
+ 10670 00a4 0028     		cmp	r0, #0
+ 10671 00a6 D5D0     		beq	.L652
+ARM GAS  /tmp/ccbUHtu7.s 			page 370
+
+
+6057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 10672              		.loc 1 6057 9 is_stmt 1 view .LVU3709
+6057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 10673              		.loc 1 6057 13 is_stmt 0 view .LVU3710
+ 10674 00a8 A06B     		ldr	r0, [r4, #56]
+6057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 10675              		.loc 1 6057 21 view .LVU3711
+ 10676 00aa 836B     		ldr	r3, [r0, #56]
+6057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 10677              		.loc 1 6057 9 view .LVU3712
+ 10678 00ac 9847     		blx	r3
+ 10679              	.LVL736:
+ 10680 00ae D1E7     		b	.L652
+ 10681              	.L659:
+6062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10682              		.loc 1 6062 7 is_stmt 1 view .LVU3713
+ 10683 00b0 2046     		mov	r0, r4
+ 10684 00b2 FFF7FEFF 		bl	I2C_TreatErrorCallback
+ 10685              	.LVL737:
+ 10686 00b6 CDE7     		b	.L652
+ 10687              	.LVL738:
+ 10688              	.L662:
+6069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10689              		.loc 1 6069 5 view .LVU3714
+6069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10690              		.loc 1 6069 14 is_stmt 0 view .LVU3715
+ 10691 00b8 2368     		ldr	r3, [r4]
+ 10692              	.LVL739:
+6069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10693              		.loc 1 6069 24 view .LVU3716
+ 10694 00ba 1A68     		ldr	r2, [r3]
+6069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10695              		.loc 1 6069 8 view .LVU3717
+ 10696 00bc 12F4004F 		tst	r2, #32768
+ 10697 00c0 03D0     		beq	.L663
+6071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10698              		.loc 1 6071 7 is_stmt 1 view .LVU3718
+6071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10699              		.loc 1 6071 21 is_stmt 0 view .LVU3719
+ 10700 00c2 1A68     		ldr	r2, [r3]
+6071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10701              		.loc 1 6071 27 view .LVU3720
+ 10702 00c4 22F40042 		bic	r2, r2, #32768
+ 10703 00c8 1A60     		str	r2, [r3]
+ 10704              	.L663:
+6074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10705              		.loc 1 6074 5 is_stmt 1 view .LVU3721
+6074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10706              		.loc 1 6074 9 is_stmt 0 view .LVU3722
+ 10707 00ca E06B     		ldr	r0, [r4, #60]
+ 10708 00cc FFF7FEFF 		bl	HAL_DMA_GetState
+ 10709              	.LVL740:
+6074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10710              		.loc 1 6074 8 view .LVU3723
+ 10711 00d0 0128     		cmp	r0, #1
+ 10712 00d2 0ED0     		beq	.L664
+6078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 371
+
+
+ 10713              		.loc 1 6078 7 is_stmt 1 view .LVU3724
+6078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10714              		.loc 1 6078 11 is_stmt 0 view .LVU3725
+ 10715 00d4 E36B     		ldr	r3, [r4, #60]
+6078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10716              		.loc 1 6078 39 view .LVU3726
+ 10717 00d6 0B4A     		ldr	r2, .L666+8
+ 10718 00d8 9A63     		str	r2, [r3, #56]
+6081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10719              		.loc 1 6081 7 is_stmt 1 view .LVU3727
+6081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10720              		.loc 1 6081 7 view .LVU3728
+ 10721 00da 0023     		movs	r3, #0
+ 10722 00dc 84F84030 		strb	r3, [r4, #64]
+6081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10723              		.loc 1 6081 7 view .LVU3729
+6084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 10724              		.loc 1 6084 7 view .LVU3730
+6084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 10725              		.loc 1 6084 11 is_stmt 0 view .LVU3731
+ 10726 00e0 E06B     		ldr	r0, [r4, #60]
+ 10727 00e2 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 10728              	.LVL741:
+6084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 10729              		.loc 1 6084 10 view .LVU3732
+ 10730 00e6 0028     		cmp	r0, #0
+ 10731 00e8 B4D0     		beq	.L652
+6087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 10732              		.loc 1 6087 9 is_stmt 1 view .LVU3733
+6087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 10733              		.loc 1 6087 13 is_stmt 0 view .LVU3734
+ 10734 00ea E06B     		ldr	r0, [r4, #60]
+6087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 10735              		.loc 1 6087 21 view .LVU3735
+ 10736 00ec 836B     		ldr	r3, [r0, #56]
+6087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 10737              		.loc 1 6087 9 view .LVU3736
+ 10738 00ee 9847     		blx	r3
+ 10739              	.LVL742:
+ 10740 00f0 B0E7     		b	.L652
+ 10741              	.L664:
+6092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10742              		.loc 1 6092 7 is_stmt 1 view .LVU3737
+ 10743 00f2 2046     		mov	r0, r4
+ 10744 00f4 FFF7FEFF 		bl	I2C_TreatErrorCallback
+ 10745              	.LVL743:
+ 10746 00f8 ACE7     		b	.L652
+ 10747              	.L667:
+ 10748 00fa 00BF     		.align	2
+ 10749              	.L666:
+ 10750 00fc 0000FFFF 		.word	-65536
+ 10751 0100 00000000 		.word	I2C_Slave_ISR_IT
+ 10752 0104 00000000 		.word	I2C_DMAAbort
+ 10753              		.cfi_endproc
+ 10754              	.LFE390:
+ 10756              		.section	.text.I2C_ITSlaveCplt,"ax",%progbits
+ 10757              		.align	1
+ARM GAS  /tmp/ccbUHtu7.s 			page 372
+
+
+ 10758              		.syntax unified
+ 10759              		.thumb
+ 10760              		.thumb_func
+ 10762              	I2C_ITSlaveCplt:
+ 10763              	.LVL744:
+ 10764              	.LFB388:
+5785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ 10765              		.loc 1 5785 1 view -0
+ 10766              		.cfi_startproc
+ 10767              		@ args = 0, pretend = 0, frame = 0
+ 10768              		@ frame_needed = 0, uses_anonymous_args = 0
+5785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ 10769              		.loc 1 5785 1 is_stmt 0 view .LVU3739
+ 10770 0000 70B5     		push	{r4, r5, r6, lr}
+ 10771              	.LCFI120:
+ 10772              		.cfi_def_cfa_offset 16
+ 10773              		.cfi_offset 4, -16
+ 10774              		.cfi_offset 5, -12
+ 10775              		.cfi_offset 6, -8
+ 10776              		.cfi_offset 14, -4
+ 10777 0002 0446     		mov	r4, r0
+ 10778 0004 0D46     		mov	r5, r1
+5786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 10779              		.loc 1 5786 3 is_stmt 1 view .LVU3740
+5786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 10780              		.loc 1 5786 26 is_stmt 0 view .LVU3741
+ 10781 0006 0268     		ldr	r2, [r0]
+5786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 10782              		.loc 1 5786 12 view .LVU3742
+ 10783 0008 1668     		ldr	r6, [r2]
+ 10784              	.LVL745:
+5787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ 10785              		.loc 1 5787 3 is_stmt 1 view .LVU3743
+5788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10786              		.loc 1 5788 3 view .LVU3744
+5788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10787              		.loc 1 5788 24 is_stmt 0 view .LVU3745
+ 10788 000a 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 10789 000e DBB2     		uxtb	r3, r3
+ 10790              	.LVL746:
+5791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10791              		.loc 1 5791 3 is_stmt 1 view .LVU3746
+ 10792 0010 2021     		movs	r1, #32
+ 10793              	.LVL747:
+5791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10794              		.loc 1 5791 3 is_stmt 0 view .LVU3747
+ 10795 0012 D161     		str	r1, [r2, #28]
+5794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10796              		.loc 1 5794 3 is_stmt 1 view .LVU3748
+5794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10797              		.loc 1 5794 6 is_stmt 0 view .LVU3749
+ 10798 0014 212B     		cmp	r3, #33
+ 10799 0016 0DD0     		beq	.L669
+5794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10800              		.loc 1 5794 43 discriminator 1 view .LVU3750
+ 10801 0018 292B     		cmp	r3, #41
+ 10802 001a 0BD0     		beq	.L669
+ARM GAS  /tmp/ccbUHtu7.s 			page 373
+
+
+5799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10803              		.loc 1 5799 8 is_stmt 1 view .LVU3751
+5799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10804              		.loc 1 5799 11 is_stmt 0 view .LVU3752
+ 10805 001c 222B     		cmp	r3, #34
+ 10806 001e 01D0     		beq	.L672
+5799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10807              		.loc 1 5799 48 discriminator 1 view .LVU3753
+ 10808 0020 2A2B     		cmp	r3, #42
+ 10809 0022 0ED1     		bne	.L671
+ 10810              	.L672:
+5801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ 10811              		.loc 1 5801 5 is_stmt 1 view .LVU3754
+ 10812 0024 48F20201 		movw	r1, #32770
+ 10813 0028 2046     		mov	r0, r4
+ 10814              	.LVL748:
+5801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ 10815              		.loc 1 5801 5 is_stmt 0 view .LVU3755
+ 10816 002a FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10817              	.LVL749:
+5802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10818              		.loc 1 5802 5 is_stmt 1 view .LVU3756
+5802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10819              		.loc 1 5802 25 is_stmt 0 view .LVU3757
+ 10820 002e 2223     		movs	r3, #34
+ 10821 0030 2363     		str	r3, [r4, #48]
+ 10822 0032 06E0     		b	.L671
+ 10823              	.LVL750:
+ 10824              	.L669:
+5796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ 10825              		.loc 1 5796 5 is_stmt 1 view .LVU3758
+ 10826 0034 48F20101 		movw	r1, #32769
+ 10827 0038 2046     		mov	r0, r4
+ 10828              	.LVL751:
+5796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ 10829              		.loc 1 5796 5 is_stmt 0 view .LVU3759
+ 10830 003a FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10831              	.LVL752:
+5797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10832              		.loc 1 5797 5 is_stmt 1 view .LVU3760
+5797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10833              		.loc 1 5797 25 is_stmt 0 view .LVU3761
+ 10834 003e 2123     		movs	r3, #33
+ 10835 0040 2363     		str	r3, [r4, #48]
+ 10836              	.L671:
+5810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10837              		.loc 1 5810 3 is_stmt 1 view .LVU3762
+5810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10838              		.loc 1 5810 7 is_stmt 0 view .LVU3763
+ 10839 0042 2268     		ldr	r2, [r4]
+5810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10840              		.loc 1 5810 17 view .LVU3764
+ 10841 0044 5368     		ldr	r3, [r2, #4]
+5810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10842              		.loc 1 5810 23 view .LVU3765
+ 10843 0046 43F40043 		orr	r3, r3, #32768
+ 10844 004a 5360     		str	r3, [r2, #4]
+ARM GAS  /tmp/ccbUHtu7.s 			page 374
+
+
+5813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10845              		.loc 1 5813 3 is_stmt 1 view .LVU3766
+ 10846 004c 2268     		ldr	r2, [r4]
+ 10847 004e 5368     		ldr	r3, [r2, #4]
+ 10848 0050 23F0FF73 		bic	r3, r3, #33423360
+ 10849 0054 23F48B33 		bic	r3, r3, #71168
+ 10850 0058 23F4FF73 		bic	r3, r3, #510
+ 10851 005c 23F00103 		bic	r3, r3, #1
+ 10852 0060 5360     		str	r3, [r2, #4]
+5816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10853              		.loc 1 5816 3 view .LVU3767
+ 10854 0062 2046     		mov	r0, r4
+ 10855 0064 FFF7FEFF 		bl	I2C_Flush_TXDR
+ 10856              	.LVL753:
+5819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10857              		.loc 1 5819 3 view .LVU3768
+5819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10858              		.loc 1 5819 6 is_stmt 0 view .LVU3769
+ 10859 0068 16F4804F 		tst	r6, #16384
+ 10860 006c 40D0     		beq	.L673
+5822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10861              		.loc 1 5822 5 is_stmt 1 view .LVU3770
+5822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10862              		.loc 1 5822 9 is_stmt 0 view .LVU3771
+ 10863 006e 2268     		ldr	r2, [r4]
+5822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10864              		.loc 1 5822 19 view .LVU3772
+ 10865 0070 1368     		ldr	r3, [r2]
+5822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10866              		.loc 1 5822 25 view .LVU3773
+ 10867 0072 23F48043 		bic	r3, r3, #16384
+ 10868 0076 1360     		str	r3, [r2]
+5824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10869              		.loc 1 5824 5 is_stmt 1 view .LVU3774
+5824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10870              		.loc 1 5824 13 is_stmt 0 view .LVU3775
+ 10871 0078 A36B     		ldr	r3, [r4, #56]
+5824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10872              		.loc 1 5824 8 view .LVU3776
+ 10873 007a 1BB1     		cbz	r3, .L674
+5826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10874              		.loc 1 5826 7 is_stmt 1 view .LVU3777
+5826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10875              		.loc 1 5826 35 is_stmt 0 view .LVU3778
+ 10876 007c 1B68     		ldr	r3, [r3]
+ 10877 007e 5B68     		ldr	r3, [r3, #4]
+5826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10878              		.loc 1 5826 25 view .LVU3779
+ 10879 0080 9BB2     		uxth	r3, r3
+5826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10880              		.loc 1 5826 23 view .LVU3780
+ 10881 0082 6385     		strh	r3, [r4, #42]	@ movhi
+ 10882              	.L674:
+5842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10883              		.loc 1 5842 3 is_stmt 1 view .LVU3781
+5845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10884              		.loc 1 5845 3 view .LVU3782
+ARM GAS  /tmp/ccbUHtu7.s 			page 375
+
+
+5845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10885              		.loc 1 5845 6 is_stmt 0 view .LVU3783
+ 10886 0084 15F0040F 		tst	r5, #4
+ 10887 0088 11D0     		beq	.L675
+5848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10888              		.loc 1 5848 5 is_stmt 1 view .LVU3784
+5848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10889              		.loc 1 5848 16 is_stmt 0 view .LVU3785
+ 10890 008a 25F00405 		bic	r5, r5, #4
+ 10891              	.LVL754:
+5851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10892              		.loc 1 5851 5 is_stmt 1 view .LVU3786
+5851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10893              		.loc 1 5851 36 is_stmt 0 view .LVU3787
+ 10894 008e 2368     		ldr	r3, [r4]
+5851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10895              		.loc 1 5851 46 view .LVU3788
+ 10896 0090 5A6A     		ldr	r2, [r3, #36]
+5851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10897              		.loc 1 5851 10 view .LVU3789
+ 10898 0092 636A     		ldr	r3, [r4, #36]
+5851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10899              		.loc 1 5851 21 view .LVU3790
+ 10900 0094 1A70     		strb	r2, [r3]
+5854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10901              		.loc 1 5854 5 is_stmt 1 view .LVU3791
+5854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10902              		.loc 1 5854 9 is_stmt 0 view .LVU3792
+ 10903 0096 636A     		ldr	r3, [r4, #36]
+5854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10904              		.loc 1 5854 19 view .LVU3793
+ 10905 0098 0133     		adds	r3, r3, #1
+ 10906 009a 6362     		str	r3, [r4, #36]
+5856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10907              		.loc 1 5856 5 is_stmt 1 view .LVU3794
+5856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10908              		.loc 1 5856 14 is_stmt 0 view .LVU3795
+ 10909 009c 238D     		ldrh	r3, [r4, #40]
+5856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10910              		.loc 1 5856 8 view .LVU3796
+ 10911 009e 33B1     		cbz	r3, .L675
+5858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 10912              		.loc 1 5858 7 is_stmt 1 view .LVU3797
+5858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 10913              		.loc 1 5858 21 is_stmt 0 view .LVU3798
+ 10914 00a0 013B     		subs	r3, r3, #1
+ 10915 00a2 2385     		strh	r3, [r4, #40]	@ movhi
+5859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10916              		.loc 1 5859 7 is_stmt 1 view .LVU3799
+5859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10917              		.loc 1 5859 11 is_stmt 0 view .LVU3800
+ 10918 00a4 638D     		ldrh	r3, [r4, #42]
+ 10919 00a6 9BB2     		uxth	r3, r3
+5859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 10920              		.loc 1 5859 22 view .LVU3801
+ 10921 00a8 013B     		subs	r3, r3, #1
+ 10922 00aa 9BB2     		uxth	r3, r3
+ARM GAS  /tmp/ccbUHtu7.s 			page 376
+
+
+ 10923 00ac 6385     		strh	r3, [r4, #42]	@ movhi
+ 10924              	.L675:
+5864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10925              		.loc 1 5864 3 is_stmt 1 view .LVU3802
+5864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10926              		.loc 1 5864 11 is_stmt 0 view .LVU3803
+ 10927 00ae 638D     		ldrh	r3, [r4, #42]
+ 10928 00b0 9BB2     		uxth	r3, r3
+5864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10929              		.loc 1 5864 6 view .LVU3804
+ 10930 00b2 1BB1     		cbz	r3, .L676
+5867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10931              		.loc 1 5867 5 is_stmt 1 view .LVU3805
+5867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10932              		.loc 1 5867 9 is_stmt 0 view .LVU3806
+ 10933 00b4 636C     		ldr	r3, [r4, #68]
+5867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 10934              		.loc 1 5867 21 view .LVU3807
+ 10935 00b6 43F00403 		orr	r3, r3, #4
+ 10936 00ba 6364     		str	r3, [r4, #68]
+ 10937              	.L676:
+5870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferISR = NULL;
+ 10938              		.loc 1 5870 3 is_stmt 1 view .LVU3808
+5870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferISR = NULL;
+ 10939              		.loc 1 5870 14 is_stmt 0 view .LVU3809
+ 10940 00bc 0023     		movs	r3, #0
+ 10941 00be 84F84230 		strb	r3, [r4, #66]
+5871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10942              		.loc 1 5871 3 is_stmt 1 view .LVU3810
+5871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10943              		.loc 1 5871 17 is_stmt 0 view .LVU3811
+ 10944 00c2 6363     		str	r3, [r4, #52]
+5873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10945              		.loc 1 5873 3 is_stmt 1 view .LVU3812
+5873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10946              		.loc 1 5873 11 is_stmt 0 view .LVU3813
+ 10947 00c4 636C     		ldr	r3, [r4, #68]
+5873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10948              		.loc 1 5873 6 view .LVU3814
+ 10949 00c6 1BBB     		cbnz	r3, .L682
+5885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10950              		.loc 1 5885 8 is_stmt 1 view .LVU3815
+5885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10951              		.loc 1 5885 16 is_stmt 0 view .LVU3816
+ 10952 00c8 E36A     		ldr	r3, [r4, #44]
+5885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10953              		.loc 1 5885 11 view .LVU3817
+ 10954 00ca 13F5803F 		cmn	r3, #65536
+ 10955 00ce 2DD1     		bne	.L683
+5905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10956              		.loc 1 5905 8 is_stmt 1 view .LVU3818
+5905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10957              		.loc 1 5905 16 is_stmt 0 view .LVU3819
+ 10958 00d0 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 10959 00d4 DBB2     		uxtb	r3, r3
+5905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10960              		.loc 1 5905 11 view .LVU3820
+ARM GAS  /tmp/ccbUHtu7.s 			page 377
+
+
+ 10961 00d6 222B     		cmp	r3, #34
+ 10962 00d8 38D0     		beq	.L684
+5922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 10963              		.loc 1 5922 5 is_stmt 1 view .LVU3821
+5922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 10964              		.loc 1 5922 17 is_stmt 0 view .LVU3822
+ 10965 00da 2023     		movs	r3, #32
+ 10966 00dc 84F84130 		strb	r3, [r4, #65]
+5923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10967              		.loc 1 5923 5 is_stmt 1 view .LVU3823
+5923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10968              		.loc 1 5923 25 is_stmt 0 view .LVU3824
+ 10969 00e0 0023     		movs	r3, #0
+ 10970 00e2 2363     		str	r3, [r4, #48]
+5926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10971              		.loc 1 5926 5 is_stmt 1 view .LVU3825
+5926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10972              		.loc 1 5926 5 view .LVU3826
+ 10973 00e4 84F84030 		strb	r3, [r4, #64]
+5926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10974              		.loc 1 5926 5 view .LVU3827
+5932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10975              		.loc 1 5932 5 view .LVU3828
+ 10976 00e8 2046     		mov	r0, r4
+ 10977 00ea FFF7FEFF 		bl	HAL_I2C_SlaveTxCpltCallback
+ 10978              	.LVL755:
+5935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10979              		.loc 1 5935 1 is_stmt 0 view .LVU3829
+ 10980 00ee 2CE0     		b	.L668
+ 10981              	.LVL756:
+ 10982              	.L673:
+5829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10983              		.loc 1 5829 8 is_stmt 1 view .LVU3830
+5829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 10984              		.loc 1 5829 11 is_stmt 0 view .LVU3831
+ 10985 00f0 16F4004F 		tst	r6, #32768
+ 10986 00f4 C6D0     		beq	.L674
+5832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10987              		.loc 1 5832 5 is_stmt 1 view .LVU3832
+5832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10988              		.loc 1 5832 9 is_stmt 0 view .LVU3833
+ 10989 00f6 2268     		ldr	r2, [r4]
+5832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10990              		.loc 1 5832 19 view .LVU3834
+ 10991 00f8 1368     		ldr	r3, [r2]
+5832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 10992              		.loc 1 5832 25 view .LVU3835
+ 10993 00fa 23F40043 		bic	r3, r3, #32768
+ 10994 00fe 1360     		str	r3, [r2]
+5834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10995              		.loc 1 5834 5 is_stmt 1 view .LVU3836
+5834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10996              		.loc 1 5834 13 is_stmt 0 view .LVU3837
+ 10997 0100 E36B     		ldr	r3, [r4, #60]
+5834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 10998              		.loc 1 5834 8 view .LVU3838
+ 10999 0102 002B     		cmp	r3, #0
+ARM GAS  /tmp/ccbUHtu7.s 			page 378
+
+
+ 11000 0104 BED0     		beq	.L674
+5836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 11001              		.loc 1 5836 7 is_stmt 1 view .LVU3839
+5836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 11002              		.loc 1 5836 35 is_stmt 0 view .LVU3840
+ 11003 0106 1B68     		ldr	r3, [r3]
+ 11004 0108 5B68     		ldr	r3, [r3, #4]
+5836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 11005              		.loc 1 5836 25 view .LVU3841
+ 11006 010a 9BB2     		uxth	r3, r3
+5836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 11007              		.loc 1 5836 23 view .LVU3842
+ 11008 010c 6385     		strh	r3, [r4, #42]	@ movhi
+ 11009 010e B9E7     		b	.L674
+ 11010              	.LVL757:
+ 11011              	.L682:
+5876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11012              		.loc 1 5876 5 is_stmt 1 view .LVU3843
+5876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11013              		.loc 1 5876 27 is_stmt 0 view .LVU3844
+ 11014 0110 616C     		ldr	r1, [r4, #68]
+5876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11015              		.loc 1 5876 5 view .LVU3845
+ 11016 0112 2046     		mov	r0, r4
+ 11017 0114 FFF7FEFF 		bl	I2C_ITError
+ 11018              	.LVL758:
+5879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11019              		.loc 1 5879 5 is_stmt 1 view .LVU3846
+5879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11020              		.loc 1 5879 13 is_stmt 0 view .LVU3847
+ 11021 0118 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11022 011c DBB2     		uxtb	r3, r3
+5879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11023              		.loc 1 5879 8 view .LVU3848
+ 11024 011e 282B     		cmp	r3, #40
+ 11025 0120 13D1     		bne	.L668
+5882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 11026              		.loc 1 5882 7 is_stmt 1 view .LVU3849
+ 11027 0122 2946     		mov	r1, r5
+ 11028 0124 2046     		mov	r0, r4
+ 11029 0126 FFF7FEFF 		bl	I2C_ITListenCplt
+ 11030              	.LVL759:
+ 11031 012a 0EE0     		b	.L668
+ 11032              	.L683:
+5888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11033              		.loc 1 5888 5 view .LVU3850
+ 11034 012c 2046     		mov	r0, r4
+ 11035 012e FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 11036              	.LVL760:
+5890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 11037              		.loc 1 5890 5 view .LVU3851
+5890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 11038              		.loc 1 5890 23 is_stmt 0 view .LVU3852
+ 11039 0132 0C4B     		ldr	r3, .L685
+ 11040 0134 E362     		str	r3, [r4, #44]
+5891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11041              		.loc 1 5891 5 is_stmt 1 view .LVU3853
+ARM GAS  /tmp/ccbUHtu7.s 			page 379
+
+
+5891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11042              		.loc 1 5891 17 is_stmt 0 view .LVU3854
+ 11043 0136 2023     		movs	r3, #32
+ 11044 0138 84F84130 		strb	r3, [r4, #65]
+5892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11045              		.loc 1 5892 5 is_stmt 1 view .LVU3855
+5892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11046              		.loc 1 5892 25 is_stmt 0 view .LVU3856
+ 11047 013c 0023     		movs	r3, #0
+ 11048 013e 2363     		str	r3, [r4, #48]
+5895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11049              		.loc 1 5895 5 is_stmt 1 view .LVU3857
+5895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11050              		.loc 1 5895 5 view .LVU3858
+ 11051 0140 84F84030 		strb	r3, [r4, #64]
+5895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11052              		.loc 1 5895 5 view .LVU3859
+5901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 11053              		.loc 1 5901 5 view .LVU3860
+ 11054 0144 2046     		mov	r0, r4
+ 11055 0146 FFF7FEFF 		bl	HAL_I2C_ListenCpltCallback
+ 11056              	.LVL761:
+ 11057              	.L668:
+5935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11058              		.loc 1 5935 1 is_stmt 0 view .LVU3861
+ 11059 014a 70BD     		pop	{r4, r5, r6, pc}
+ 11060              	.LVL762:
+ 11061              	.L684:
+5907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11062              		.loc 1 5907 5 is_stmt 1 view .LVU3862
+5907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11063              		.loc 1 5907 17 is_stmt 0 view .LVU3863
+ 11064 014c 2023     		movs	r3, #32
+ 11065 014e 84F84130 		strb	r3, [r4, #65]
+5908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11066              		.loc 1 5908 5 is_stmt 1 view .LVU3864
+5908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11067              		.loc 1 5908 25 is_stmt 0 view .LVU3865
+ 11068 0152 0023     		movs	r3, #0
+ 11069 0154 2363     		str	r3, [r4, #48]
+5911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11070              		.loc 1 5911 5 is_stmt 1 view .LVU3866
+5911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11071              		.loc 1 5911 5 view .LVU3867
+ 11072 0156 84F84030 		strb	r3, [r4, #64]
+5911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11073              		.loc 1 5911 5 view .LVU3868
+5917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 11074              		.loc 1 5917 5 view .LVU3869
+ 11075 015a 2046     		mov	r0, r4
+ 11076 015c FFF7FEFF 		bl	HAL_I2C_SlaveRxCpltCallback
+ 11077              	.LVL763:
+ 11078 0160 F3E7     		b	.L668
+ 11079              	.L686:
+ 11080 0162 00BF     		.align	2
+ 11081              	.L685:
+ 11082 0164 0000FFFF 		.word	-65536
+ARM GAS  /tmp/ccbUHtu7.s 			page 380
+
+
+ 11083              		.cfi_endproc
+ 11084              	.LFE388:
+ 11086              		.section	.text.I2C_Slave_ISR_IT,"ax",%progbits
+ 11087              		.align	1
+ 11088              		.syntax unified
+ 11089              		.thumb
+ 11090              		.thumb_func
+ 11092              	I2C_Slave_ISR_IT:
+ 11093              	.LVL764:
+ 11094              	.LFB379:
+4891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 11095              		.loc 1 4891 1 view -0
+ 11096              		.cfi_startproc
+ 11097              		@ args = 0, pretend = 0, frame = 0
+ 11098              		@ frame_needed = 0, uses_anonymous_args = 0
+4891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 11099              		.loc 1 4891 1 is_stmt 0 view .LVU3871
+ 11100 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 11101              	.LCFI121:
+ 11102              		.cfi_def_cfa_offset 24
+ 11103              		.cfi_offset 3, -24
+ 11104              		.cfi_offset 4, -20
+ 11105              		.cfi_offset 5, -16
+ 11106              		.cfi_offset 6, -12
+ 11107              		.cfi_offset 7, -8
+ 11108              		.cfi_offset 14, -4
+4892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 11109              		.loc 1 4892 3 is_stmt 1 view .LVU3872
+4892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 11110              		.loc 1 4892 12 is_stmt 0 view .LVU3873
+ 11111 0002 C76A     		ldr	r7, [r0, #44]
+ 11112              	.LVL765:
+4893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11113              		.loc 1 4893 3 is_stmt 1 view .LVU3874
+4896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11114              		.loc 1 4896 3 view .LVU3875
+4896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11115              		.loc 1 4896 3 view .LVU3876
+ 11116 0004 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 11117 0008 012B     		cmp	r3, #1
+ 11118 000a 00F09E80 		beq	.L701
+ 11119 000e 0446     		mov	r4, r0
+ 11120 0010 0D46     		mov	r5, r1
+ 11121 0012 1646     		mov	r6, r2
+4896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11122              		.loc 1 4896 3 discriminator 2 view .LVU3877
+ 11123 0014 0123     		movs	r3, #1
+ 11124 0016 80F84030 		strb	r3, [r0, #64]
+4896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11125              		.loc 1 4896 3 discriminator 2 view .LVU3878
+4899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 11126              		.loc 1 4899 3 discriminator 2 view .LVU3879
+4899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 11127              		.loc 1 4899 6 is_stmt 0 discriminator 2 view .LVU3880
+ 11128 001a 11F0200F 		tst	r1, #32
+ 11129 001e 02D0     		beq	.L689
+4899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ARM GAS  /tmp/ccbUHtu7.s 			page 381
+
+
+ 11130              		.loc 1 4899 61 discriminator 1 view .LVU3881
+ 11131 0020 12F0200F 		tst	r2, #32
+ 11132 0024 19D1     		bne	.L703
+ 11133              	.LVL766:
+ 11134              	.L689:
+4906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 11135              		.loc 1 4906 3 is_stmt 1 view .LVU3882
+4906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 11136              		.loc 1 4906 6 is_stmt 0 view .LVU3883
+ 11137 0026 15F0100F 		tst	r5, #16
+ 11138 002a 3ED0     		beq	.L690
+4906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 11139              		.loc 1 4906 58 discriminator 1 view .LVU3884
+ 11140 002c 16F0100F 		tst	r6, #16
+ 11141 0030 3BD0     		beq	.L690
+4913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11142              		.loc 1 4913 5 is_stmt 1 view .LVU3885
+4913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11143              		.loc 1 4913 13 is_stmt 0 view .LVU3886
+ 11144 0032 638D     		ldrh	r3, [r4, #42]
+ 11145 0034 9BB2     		uxth	r3, r3
+4913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11146              		.loc 1 4913 8 view .LVU3887
+ 11147 0036 43BB     		cbnz	r3, .L691
+4915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 11148              		.loc 1 4915 7 is_stmt 1 view .LVU3888
+4915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 11149              		.loc 1 4915 16 is_stmt 0 view .LVU3889
+ 11150 0038 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11151 003c DBB2     		uxtb	r3, r3
+4915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 11152              		.loc 1 4915 10 view .LVU3890
+ 11153 003e 282B     		cmp	r3, #40
+ 11154 0040 0ED0     		beq	.L704
+ 11155              	.L692:
+4922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11156              		.loc 1 4922 12 is_stmt 1 view .LVU3891
+4922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11157              		.loc 1 4922 21 is_stmt 0 view .LVU3892
+ 11158 0042 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11159 0046 DBB2     		uxtb	r3, r3
+4922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11160              		.loc 1 4922 15 view .LVU3893
+ 11161 0048 292B     		cmp	r3, #41
+ 11162 004a 11D0     		beq	.L705
+ 11163              	.L694:
+4937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11164              		.loc 1 4937 9 is_stmt 1 view .LVU3894
+ 11165 004c 2368     		ldr	r3, [r4]
+ 11166 004e 1022     		movs	r2, #16
+ 11167 0050 DA61     		str	r2, [r3, #28]
+ 11168              	.L693:
+5014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11169              		.loc 1 5014 3 view .LVU3895
+5017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11170              		.loc 1 5017 3 view .LVU3896
+5017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 382
+
+
+ 11171              		.loc 1 5017 3 view .LVU3897
+ 11172 0052 0020     		movs	r0, #0
+ 11173 0054 84F84000 		strb	r0, [r4, #64]
+5017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11174              		.loc 1 5017 3 view .LVU3898
+5019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 11175              		.loc 1 5019 3 view .LVU3899
+ 11176              	.LVL767:
+ 11177              	.L688:
+5020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11178              		.loc 1 5020 1 is_stmt 0 view .LVU3900
+ 11179 0058 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 11180              	.LVL768:
+ 11181              	.L703:
+4903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11182              		.loc 1 4903 5 is_stmt 1 view .LVU3901
+ 11183 005a FFF7FEFF 		bl	I2C_ITSlaveCplt
+ 11184              	.LVL769:
+4903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11185              		.loc 1 4903 5 is_stmt 0 view .LVU3902
+ 11186 005e E2E7     		b	.L689
+ 11187              	.L704:
+4915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 11188              		.loc 1 4915 49 discriminator 1 view .LVU3903
+ 11189 0060 B7F1007F 		cmp	r7, #33554432
+ 11190 0064 EDD1     		bne	.L692
+4920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11191              		.loc 1 4920 9 is_stmt 1 view .LVU3904
+ 11192 0066 2946     		mov	r1, r5
+ 11193 0068 2046     		mov	r0, r4
+ 11194 006a FFF7FEFF 		bl	I2C_ITListenCplt
+ 11195              	.LVL770:
+ 11196 006e F0E7     		b	.L693
+ 11197              	.L705:
+4922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11198              		.loc 1 4922 62 is_stmt 0 discriminator 1 view .LVU3905
+ 11199 0070 17F5803F 		cmn	r7, #65536
+ 11200 0074 EAD0     		beq	.L694
+4925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11201              		.loc 1 4925 9 is_stmt 1 view .LVU3906
+ 11202 0076 2368     		ldr	r3, [r4]
+ 11203 0078 1022     		movs	r2, #16
+ 11204 007a DA61     		str	r2, [r3, #28]
+4928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11205              		.loc 1 4928 9 view .LVU3907
+ 11206 007c 2046     		mov	r0, r4
+ 11207 007e FFF7FEFF 		bl	I2C_Flush_TXDR
+ 11208              	.LVL771:
+4932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11209              		.loc 1 4932 9 view .LVU3908
+ 11210 0082 2046     		mov	r0, r4
+ 11211 0084 FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 11212              	.LVL772:
+ 11213 0088 E3E7     		b	.L693
+ 11214              	.L691:
+4944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11215              		.loc 1 4944 7 view .LVU3909
+ARM GAS  /tmp/ccbUHtu7.s 			page 383
+
+
+ 11216 008a 2368     		ldr	r3, [r4]
+ 11217 008c 1022     		movs	r2, #16
+ 11218 008e DA61     		str	r2, [r3, #28]
+4947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11219              		.loc 1 4947 7 view .LVU3910
+4947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11220              		.loc 1 4947 11 is_stmt 0 view .LVU3911
+ 11221 0090 636C     		ldr	r3, [r4, #68]
+4947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11222              		.loc 1 4947 23 view .LVU3912
+ 11223 0092 43F00403 		orr	r3, r3, #4
+ 11224 0096 6364     		str	r3, [r4, #68]
+4949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11225              		.loc 1 4949 7 is_stmt 1 view .LVU3913
+4949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11226              		.loc 1 4949 10 is_stmt 0 view .LVU3914
+ 11227 0098 17B1     		cbz	r7, .L695
+4949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11228              		.loc 1 4949 43 discriminator 1 view .LVU3915
+ 11229 009a B7F1807F 		cmp	r7, #16777216
+ 11230 009e D8D1     		bne	.L693
+ 11231              	.L695:
+4952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11232              		.loc 1 4952 9 is_stmt 1 view .LVU3916
+4952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11233              		.loc 1 4952 31 is_stmt 0 view .LVU3917
+ 11234 00a0 616C     		ldr	r1, [r4, #68]
+4952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11235              		.loc 1 4952 9 view .LVU3918
+ 11236 00a2 2046     		mov	r0, r4
+ 11237 00a4 FFF7FEFF 		bl	I2C_ITError
+ 11238              	.LVL773:
+ 11239 00a8 D3E7     		b	.L693
+ 11240              	.L690:
+4956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 11241              		.loc 1 4956 8 is_stmt 1 view .LVU3919
+4956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 11242              		.loc 1 4956 11 is_stmt 0 view .LVU3920
+ 11243 00aa 15F0040F 		tst	r5, #4
+ 11244 00ae 1FD0     		beq	.L696
+4956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 11245              		.loc 1 4956 65 discriminator 1 view .LVU3921
+ 11246 00b0 16F0040F 		tst	r6, #4
+ 11247 00b4 1CD0     		beq	.L696
+4959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11248              		.loc 1 4959 5 is_stmt 1 view .LVU3922
+4959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11249              		.loc 1 4959 13 is_stmt 0 view .LVU3923
+ 11250 00b6 638D     		ldrh	r3, [r4, #42]
+ 11251 00b8 9BB2     		uxth	r3, r3
+4959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11252              		.loc 1 4959 8 view .LVU3924
+ 11253 00ba 73B1     		cbz	r3, .L697
+4962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11254              		.loc 1 4962 7 is_stmt 1 view .LVU3925
+4962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11255              		.loc 1 4962 38 is_stmt 0 view .LVU3926
+ARM GAS  /tmp/ccbUHtu7.s 			page 384
+
+
+ 11256 00bc 2368     		ldr	r3, [r4]
+4962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11257              		.loc 1 4962 48 view .LVU3927
+ 11258 00be 5A6A     		ldr	r2, [r3, #36]
+4962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11259              		.loc 1 4962 12 view .LVU3928
+ 11260 00c0 636A     		ldr	r3, [r4, #36]
+4962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11261              		.loc 1 4962 23 view .LVU3929
+ 11262 00c2 1A70     		strb	r2, [r3]
+4965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11263              		.loc 1 4965 7 is_stmt 1 view .LVU3930
+4965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11264              		.loc 1 4965 11 is_stmt 0 view .LVU3931
+ 11265 00c4 636A     		ldr	r3, [r4, #36]
+4965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11266              		.loc 1 4965 21 view .LVU3932
+ 11267 00c6 0133     		adds	r3, r3, #1
+ 11268 00c8 6362     		str	r3, [r4, #36]
+4967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 11269              		.loc 1 4967 7 is_stmt 1 view .LVU3933
+4967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 11270              		.loc 1 4967 11 is_stmt 0 view .LVU3934
+ 11271 00ca 238D     		ldrh	r3, [r4, #40]
+4967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferCount--;
+ 11272              		.loc 1 4967 21 view .LVU3935
+ 11273 00cc 013B     		subs	r3, r3, #1
+ 11274 00ce 2385     		strh	r3, [r4, #40]	@ movhi
+4968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 11275              		.loc 1 4968 7 is_stmt 1 view .LVU3936
+4968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 11276              		.loc 1 4968 11 is_stmt 0 view .LVU3937
+ 11277 00d0 638D     		ldrh	r3, [r4, #42]
+ 11278 00d2 9BB2     		uxth	r3, r3
+4968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 11279              		.loc 1 4968 22 view .LVU3938
+ 11280 00d4 013B     		subs	r3, r3, #1
+ 11281 00d6 9BB2     		uxth	r3, r3
+ 11282 00d8 6385     		strh	r3, [r4, #42]	@ movhi
+ 11283              	.L697:
+4971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (tmpoptions != I2C_NO_OPTION_FRAME))
+ 11284              		.loc 1 4971 5 is_stmt 1 view .LVU3939
+4971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (tmpoptions != I2C_NO_OPTION_FRAME))
+ 11285              		.loc 1 4971 14 is_stmt 0 view .LVU3940
+ 11286 00da 638D     		ldrh	r3, [r4, #42]
+ 11287 00dc 9BB2     		uxth	r3, r3
+4971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (tmpoptions != I2C_NO_OPTION_FRAME))
+ 11288              		.loc 1 4971 8 view .LVU3941
+ 11289 00de 002B     		cmp	r3, #0
+ 11290 00e0 B7D1     		bne	.L693
+4971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (tmpoptions != I2C_NO_OPTION_FRAME))
+ 11291              		.loc 1 4971 33 discriminator 1 view .LVU3942
+ 11292 00e2 17F5803F 		cmn	r7, #65536
+ 11293 00e6 B4D0     		beq	.L693
+4975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 11294              		.loc 1 4975 7 is_stmt 1 view .LVU3943
+ 11295 00e8 2046     		mov	r0, r4
+ARM GAS  /tmp/ccbUHtu7.s 			page 385
+
+
+ 11296 00ea FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 11297              	.LVL774:
+ 11298 00ee B0E7     		b	.L693
+ 11299              	.L696:
+4978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 11300              		.loc 1 4978 8 view .LVU3944
+4978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 11301              		.loc 1 4978 11 is_stmt 0 view .LVU3945
+ 11302 00f0 15F0080F 		tst	r5, #8
+ 11303 00f4 02D0     		beq	.L698
+4978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 11304              		.loc 1 4978 65 discriminator 1 view .LVU3946
+ 11305 00f6 16F0080F 		tst	r6, #8
+ 11306 00fa 18D1     		bne	.L706
+ 11307              	.L698:
+4983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 11308              		.loc 1 4983 8 is_stmt 1 view .LVU3947
+4983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 11309              		.loc 1 4983 11 is_stmt 0 view .LVU3948
+ 11310 00fc 15F0020F 		tst	r5, #2
+ 11311 0100 A7D0     		beq	.L693
+4983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 11312              		.loc 1 4983 65 discriminator 1 view .LVU3949
+ 11313 0102 16F0020F 		tst	r6, #2
+ 11314 0106 A4D0     		beq	.L693
+4990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11315              		.loc 1 4990 5 is_stmt 1 view .LVU3950
+4990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11316              		.loc 1 4990 13 is_stmt 0 view .LVU3951
+ 11317 0108 638D     		ldrh	r3, [r4, #42]
+ 11318 010a 9BB2     		uxth	r3, r3
+4990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11319              		.loc 1 4990 8 view .LVU3952
+ 11320 010c A3B1     		cbz	r3, .L699
+4993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11321              		.loc 1 4993 7 is_stmt 1 view .LVU3953
+4993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11322              		.loc 1 4993 35 is_stmt 0 view .LVU3954
+ 11323 010e 626A     		ldr	r2, [r4, #36]
+4993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11324              		.loc 1 4993 11 view .LVU3955
+ 11325 0110 2368     		ldr	r3, [r4]
+4993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11326              		.loc 1 4993 30 view .LVU3956
+ 11327 0112 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+4993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11328              		.loc 1 4993 28 view .LVU3957
+ 11329 0114 9A62     		str	r2, [r3, #40]
+4996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11330              		.loc 1 4996 7 is_stmt 1 view .LVU3958
+4996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11331              		.loc 1 4996 11 is_stmt 0 view .LVU3959
+ 11332 0116 636A     		ldr	r3, [r4, #36]
+4996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11333              		.loc 1 4996 21 view .LVU3960
+ 11334 0118 0133     		adds	r3, r3, #1
+ 11335 011a 6362     		str	r3, [r4, #36]
+ARM GAS  /tmp/ccbUHtu7.s 			page 386
+
+
+4998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+ 11336              		.loc 1 4998 7 is_stmt 1 view .LVU3961
+4998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+ 11337              		.loc 1 4998 11 is_stmt 0 view .LVU3962
+ 11338 011c 638D     		ldrh	r3, [r4, #42]
+ 11339 011e 9BB2     		uxth	r3, r3
+4998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       hi2c->XferSize--;
+ 11340              		.loc 1 4998 22 view .LVU3963
+ 11341 0120 013B     		subs	r3, r3, #1
+ 11342 0122 9BB2     		uxth	r3, r3
+ 11343 0124 6385     		strh	r3, [r4, #42]	@ movhi
+4999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 11344              		.loc 1 4999 7 is_stmt 1 view .LVU3964
+4999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 11345              		.loc 1 4999 11 is_stmt 0 view .LVU3965
+ 11346 0126 238D     		ldrh	r3, [r4, #40]
+4999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 11347              		.loc 1 4999 21 view .LVU3966
+ 11348 0128 013B     		subs	r3, r3, #1
+ 11349 012a 2385     		strh	r3, [r4, #40]	@ movhi
+ 11350 012c 91E7     		b	.L693
+ 11351              	.L706:
+4981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11352              		.loc 1 4981 5 is_stmt 1 view .LVU3967
+ 11353 012e 2946     		mov	r1, r5
+ 11354 0130 2046     		mov	r0, r4
+ 11355 0132 FFF7FEFF 		bl	I2C_ITAddrCplt
+ 11356              	.LVL775:
+ 11357 0136 8CE7     		b	.L693
+ 11358              	.L699:
+5003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11359              		.loc 1 5003 7 view .LVU3968
+5003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11360              		.loc 1 5003 10 is_stmt 0 view .LVU3969
+ 11361 0138 B7F1807F 		cmp	r7, #16777216
+ 11362 013c 01D0     		beq	.L700
+5003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11363              		.loc 1 5003 42 discriminator 1 view .LVU3970
+ 11364 013e 002F     		cmp	r7, #0
+ 11365 0140 87D1     		bne	.L693
+ 11366              	.L700:
+5007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11367              		.loc 1 5007 9 is_stmt 1 view .LVU3971
+ 11368 0142 2046     		mov	r0, r4
+ 11369 0144 FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 11370              	.LVL776:
+ 11371 0148 83E7     		b	.L693
+ 11372              	.LVL777:
+ 11373              	.L701:
+4896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11374              		.loc 1 4896 3 is_stmt 0 view .LVU3972
+ 11375 014a 0220     		movs	r0, #2
+ 11376              	.LVL778:
+4896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11377              		.loc 1 4896 3 view .LVU3973
+ 11378 014c 84E7     		b	.L688
+ 11379              		.cfi_endproc
+ARM GAS  /tmp/ccbUHtu7.s 			page 387
+
+
+ 11380              	.LFE379:
+ 11382              		.section	.text.I2C_ITMasterCplt,"ax",%progbits
+ 11383              		.align	1
+ 11384              		.syntax unified
+ 11385              		.thumb
+ 11386              		.thumb_func
+ 11388              	I2C_ITMasterCplt:
+ 11389              	.LVL779:
+ 11390              	.LFB387:
+5642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmperror;
+ 11391              		.loc 1 5642 1 is_stmt 1 view -0
+ 11392              		.cfi_startproc
+ 11393              		@ args = 0, pretend = 0, frame = 8
+ 11394              		@ frame_needed = 0, uses_anonymous_args = 0
+5642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmperror;
+ 11395              		.loc 1 5642 1 is_stmt 0 view .LVU3975
+ 11396 0000 30B5     		push	{r4, r5, lr}
+ 11397              	.LCFI122:
+ 11398              		.cfi_def_cfa_offset 12
+ 11399              		.cfi_offset 4, -12
+ 11400              		.cfi_offset 5, -8
+ 11401              		.cfi_offset 14, -4
+ 11402 0002 83B0     		sub	sp, sp, #12
+ 11403              	.LCFI123:
+ 11404              		.cfi_def_cfa_offset 24
+ 11405 0004 0446     		mov	r4, r0
+ 11406 0006 0D46     		mov	r5, r1
+5643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 11407              		.loc 1 5643 3 is_stmt 1 view .LVU3976
+5644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   __IO uint32_t tmpreg;
+ 11408              		.loc 1 5644 3 view .LVU3977
+ 11409              	.LVL780:
+5645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11410              		.loc 1 5645 3 view .LVU3978
+5648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11411              		.loc 1 5648 3 view .LVU3979
+ 11412 0008 0368     		ldr	r3, [r0]
+ 11413 000a 2022     		movs	r2, #32
+ 11414 000c DA61     		str	r2, [r3, #28]
+5651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11415              		.loc 1 5651 3 view .LVU3980
+5651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11416              		.loc 1 5651 11 is_stmt 0 view .LVU3981
+ 11417 000e 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 11418 0012 DBB2     		uxtb	r3, r3
+5651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11419              		.loc 1 5651 6 view .LVU3982
+ 11420 0014 212B     		cmp	r3, #33
+ 11421 0016 33D0     		beq	.L719
+5656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11422              		.loc 1 5656 8 is_stmt 1 view .LVU3983
+5656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11423              		.loc 1 5656 16 is_stmt 0 view .LVU3984
+ 11424 0018 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 11425 001c DBB2     		uxtb	r3, r3
+5656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11426              		.loc 1 5656 11 view .LVU3985
+ARM GAS  /tmp/ccbUHtu7.s 			page 388
+
+
+ 11427 001e 222B     		cmp	r3, #34
+ 11428 0020 34D0     		beq	.L720
+ 11429              	.LVL781:
+ 11430              	.L709:
+5664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11431              		.loc 1 5664 3 is_stmt 1 view .LVU3986
+5667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11432              		.loc 1 5667 3 view .LVU3987
+ 11433 0022 2268     		ldr	r2, [r4]
+ 11434 0024 5368     		ldr	r3, [r2, #4]
+ 11435 0026 23F0FF73 		bic	r3, r3, #33423360
+ 11436 002a 23F48B33 		bic	r3, r3, #71168
+ 11437 002e 23F4FF73 		bic	r3, r3, #510
+ 11438 0032 23F00103 		bic	r3, r3, #1
+ 11439 0036 5360     		str	r3, [r2, #4]
+5670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+ 11440              		.loc 1 5670 3 view .LVU3988
+5670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+ 11441              		.loc 1 5670 23 is_stmt 0 view .LVU3989
+ 11442 0038 0023     		movs	r3, #0
+ 11443 003a 6363     		str	r3, [r4, #52]
+5671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11444              		.loc 1 5671 3 is_stmt 1 view .LVU3990
+5671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11445              		.loc 1 5671 23 is_stmt 0 view .LVU3991
+ 11446 003c A3F58033 		sub	r3, r3, #65536
+ 11447 0040 E362     		str	r3, [r4, #44]
+5673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11448              		.loc 1 5673 3 is_stmt 1 view .LVU3992
+5673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11449              		.loc 1 5673 6 is_stmt 0 view .LVU3993
+ 11450 0042 15F0100F 		tst	r5, #16
+ 11451 0046 06D0     		beq	.L710
+5676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11452              		.loc 1 5676 5 is_stmt 1 view .LVU3994
+ 11453 0048 2368     		ldr	r3, [r4]
+ 11454 004a 1022     		movs	r2, #16
+ 11455 004c DA61     		str	r2, [r3, #28]
+5679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11456              		.loc 1 5679 5 view .LVU3995
+5679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11457              		.loc 1 5679 9 is_stmt 0 view .LVU3996
+ 11458 004e 636C     		ldr	r3, [r4, #68]
+5679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11459              		.loc 1 5679 21 view .LVU3997
+ 11460 0050 43F00403 		orr	r3, r3, #4
+ 11461 0054 6364     		str	r3, [r4, #68]
+ 11462              	.L710:
+5683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11463              		.loc 1 5683 3 is_stmt 1 view .LVU3998
+5683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11464              		.loc 1 5683 12 is_stmt 0 view .LVU3999
+ 11465 0056 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11466 005a DBB2     		uxtb	r3, r3
+5683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11467              		.loc 1 5683 6 view .LVU4000
+ 11468 005c 602B     		cmp	r3, #96
+ARM GAS  /tmp/ccbUHtu7.s 			page 389
+
+
+ 11469 005e 1BD0     		beq	.L721
+ 11470              	.L711:
+5691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11471              		.loc 1 5691 3 is_stmt 1 view .LVU4001
+ 11472 0060 2046     		mov	r0, r4
+ 11473 0062 FFF7FEFF 		bl	I2C_Flush_TXDR
+ 11474              	.LVL782:
+5694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11475              		.loc 1 5694 3 view .LVU4002
+5694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11476              		.loc 1 5694 12 is_stmt 0 view .LVU4003
+ 11477 0066 626C     		ldr	r2, [r4, #68]
+ 11478              	.LVL783:
+5697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11479              		.loc 1 5697 3 is_stmt 1 view .LVU4004
+5697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11480              		.loc 1 5697 12 is_stmt 0 view .LVU4005
+ 11481 0068 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11482 006c DBB2     		uxtb	r3, r3
+5697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11483              		.loc 1 5697 6 view .LVU4006
+ 11484 006e 602B     		cmp	r3, #96
+ 11485 0070 00D0     		beq	.L712
+5697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11486              		.loc 1 5697 44 discriminator 1 view .LVU4007
+ 11487 0072 D2B1     		cbz	r2, .L713
+ 11488              	.L712:
+5700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11489              		.loc 1 5700 5 is_stmt 1 view .LVU4008
+5700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11490              		.loc 1 5700 27 is_stmt 0 view .LVU4009
+ 11491 0074 616C     		ldr	r1, [r4, #68]
+5700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11492              		.loc 1 5700 5 view .LVU4010
+ 11493 0076 2046     		mov	r0, r4
+ 11494 0078 FFF7FEFF 		bl	I2C_ITError
+ 11495              	.LVL784:
+ 11496              	.L707:
+5776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11497              		.loc 1 5776 1 view .LVU4011
+ 11498 007c 03B0     		add	sp, sp, #12
+ 11499              	.LCFI124:
+ 11500              		.cfi_remember_state
+ 11501              		.cfi_def_cfa_offset 12
+ 11502              		@ sp needed
+ 11503 007e 30BD     		pop	{r4, r5, pc}
+ 11504              	.LVL785:
+ 11505              	.L719:
+ 11506              	.LCFI125:
+ 11507              		.cfi_restore_state
+5653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ 11508              		.loc 1 5653 5 is_stmt 1 view .LVU4012
+ 11509 0080 0121     		movs	r1, #1
+ 11510              	.LVL786:
+5653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ 11511              		.loc 1 5653 5 is_stmt 0 view .LVU4013
+ 11512 0082 FFF7FEFF 		bl	I2C_Disable_IRQ
+ARM GAS  /tmp/ccbUHtu7.s 			page 390
+
+
+ 11513              	.LVL787:
+5654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11514              		.loc 1 5654 5 is_stmt 1 view .LVU4014
+5654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11515              		.loc 1 5654 25 is_stmt 0 view .LVU4015
+ 11516 0086 1123     		movs	r3, #17
+ 11517 0088 2363     		str	r3, [r4, #48]
+ 11518 008a CAE7     		b	.L709
+ 11519              	.LVL788:
+ 11520              	.L720:
+5658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ 11521              		.loc 1 5658 5 is_stmt 1 view .LVU4016
+ 11522 008c 0221     		movs	r1, #2
+ 11523              	.LVL789:
+5658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ 11524              		.loc 1 5658 5 is_stmt 0 view .LVU4017
+ 11525 008e FFF7FEFF 		bl	I2C_Disable_IRQ
+ 11526              	.LVL790:
+5659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11527              		.loc 1 5659 5 is_stmt 1 view .LVU4018
+5659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11528              		.loc 1 5659 25 is_stmt 0 view .LVU4019
+ 11529 0092 1223     		movs	r3, #18
+ 11530 0094 2363     		str	r3, [r4, #48]
+ 11531 0096 C4E7     		b	.L709
+ 11532              	.L721:
+5683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11533              		.loc 1 5683 44 discriminator 1 view .LVU4020
+ 11534 0098 15F0040F 		tst	r5, #4
+ 11535 009c E0D0     		beq	.L711
+5686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     UNUSED(tmpreg);
+ 11536              		.loc 1 5686 5 is_stmt 1 view .LVU4021
+5686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     UNUSED(tmpreg);
+ 11537              		.loc 1 5686 27 is_stmt 0 view .LVU4022
+ 11538 009e 2368     		ldr	r3, [r4]
+5686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     UNUSED(tmpreg);
+ 11539              		.loc 1 5686 37 view .LVU4023
+ 11540 00a0 5B6A     		ldr	r3, [r3, #36]
+ 11541 00a2 DBB2     		uxtb	r3, r3
+5686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     UNUSED(tmpreg);
+ 11542              		.loc 1 5686 12 view .LVU4024
+ 11543 00a4 0193     		str	r3, [sp, #4]
+5687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11544              		.loc 1 5687 5 is_stmt 1 view .LVU4025
+ 11545 00a6 019B     		ldr	r3, [sp, #4]
+ 11546 00a8 DAE7     		b	.L711
+ 11547              	.LVL791:
+ 11548              	.L713:
+5703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11549              		.loc 1 5703 8 view .LVU4026
+5703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11550              		.loc 1 5703 16 is_stmt 0 view .LVU4027
+ 11551 00aa 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11552 00ae DBB2     		uxtb	r3, r3
+5703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11553              		.loc 1 5703 11 view .LVU4028
+ 11554 00b0 212B     		cmp	r3, #33
+ARM GAS  /tmp/ccbUHtu7.s 			page 391
+
+
+ 11555 00b2 17D0     		beq	.L722
+5738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11556              		.loc 1 5738 8 is_stmt 1 view .LVU4029
+5738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11557              		.loc 1 5738 16 is_stmt 0 view .LVU4030
+ 11558 00b4 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11559 00b8 DBB2     		uxtb	r3, r3
+5738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 11560              		.loc 1 5738 11 view .LVU4031
+ 11561 00ba 222B     		cmp	r3, #34
+ 11562 00bc DED1     		bne	.L707
+5740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11563              		.loc 1 5740 5 is_stmt 1 view .LVU4032
+5740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11564              		.loc 1 5740 17 is_stmt 0 view .LVU4033
+ 11565 00be 2023     		movs	r3, #32
+ 11566 00c0 84F84130 		strb	r3, [r4, #65]
+5741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11567              		.loc 1 5741 5 is_stmt 1 view .LVU4034
+5741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11568              		.loc 1 5741 25 is_stmt 0 view .LVU4035
+ 11569 00c4 0023     		movs	r3, #0
+ 11570 00c6 2363     		str	r3, [r4, #48]
+5743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11571              		.loc 1 5743 5 is_stmt 1 view .LVU4036
+5743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11572              		.loc 1 5743 13 is_stmt 0 view .LVU4037
+ 11573 00c8 94F84230 		ldrb	r3, [r4, #66]	@ zero_extendqisi2
+ 11574 00cc DBB2     		uxtb	r3, r3
+5743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11575              		.loc 1 5743 8 view .LVU4038
+ 11576 00ce 402B     		cmp	r3, #64
+ 11577 00d0 24D0     		beq	.L723
+5759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11578              		.loc 1 5759 7 is_stmt 1 view .LVU4039
+5759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11579              		.loc 1 5759 18 is_stmt 0 view .LVU4040
+ 11580 00d2 0023     		movs	r3, #0
+ 11581 00d4 84F84230 		strb	r3, [r4, #66]
+5762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11582              		.loc 1 5762 7 is_stmt 1 view .LVU4041
+5762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11583              		.loc 1 5762 7 view .LVU4042
+ 11584 00d8 84F84030 		strb	r3, [r4, #64]
+5762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11585              		.loc 1 5762 7 view .LVU4043
+5768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 11586              		.loc 1 5768 7 view .LVU4044
+ 11587 00dc 2046     		mov	r0, r4
+ 11588 00de FFF7FEFF 		bl	HAL_I2C_MasterRxCpltCallback
+ 11589              	.LVL792:
+5775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 11590              		.loc 1 5775 3 view .LVU4045
+5776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11591              		.loc 1 5776 1 is_stmt 0 view .LVU4046
+ 11592 00e2 CBE7     		b	.L707
+ 11593              	.LVL793:
+ARM GAS  /tmp/ccbUHtu7.s 			page 392
+
+
+ 11594              	.L722:
+5705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11595              		.loc 1 5705 5 is_stmt 1 view .LVU4047
+5705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11596              		.loc 1 5705 17 is_stmt 0 view .LVU4048
+ 11597 00e4 2023     		movs	r3, #32
+ 11598 00e6 84F84130 		strb	r3, [r4, #65]
+5706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11599              		.loc 1 5706 5 is_stmt 1 view .LVU4049
+5706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11600              		.loc 1 5706 25 is_stmt 0 view .LVU4050
+ 11601 00ea 0023     		movs	r3, #0
+ 11602 00ec 2363     		str	r3, [r4, #48]
+5708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11603              		.loc 1 5708 5 is_stmt 1 view .LVU4051
+5708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11604              		.loc 1 5708 13 is_stmt 0 view .LVU4052
+ 11605 00ee 94F84230 		ldrb	r3, [r4, #66]	@ zero_extendqisi2
+ 11606 00f2 DBB2     		uxtb	r3, r3
+5708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11607              		.loc 1 5708 8 view .LVU4053
+ 11608 00f4 402B     		cmp	r3, #64
+ 11609 00f6 08D0     		beq	.L724
+5724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11610              		.loc 1 5724 7 is_stmt 1 view .LVU4054
+5724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11611              		.loc 1 5724 18 is_stmt 0 view .LVU4055
+ 11612 00f8 0023     		movs	r3, #0
+ 11613 00fa 84F84230 		strb	r3, [r4, #66]
+5727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11614              		.loc 1 5727 7 is_stmt 1 view .LVU4056
+5727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11615              		.loc 1 5727 7 view .LVU4057
+ 11616 00fe 84F84030 		strb	r3, [r4, #64]
+5727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11617              		.loc 1 5727 7 view .LVU4058
+5733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 11618              		.loc 1 5733 7 view .LVU4059
+ 11619 0102 2046     		mov	r0, r4
+ 11620 0104 FFF7FEFF 		bl	HAL_I2C_MasterTxCpltCallback
+ 11621              	.LVL794:
+5733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 11622              		.loc 1 5733 7 is_stmt 0 view .LVU4060
+ 11623 0108 B8E7     		b	.L707
+ 11624              	.LVL795:
+ 11625              	.L724:
+5710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11626              		.loc 1 5710 7 is_stmt 1 view .LVU4061
+5710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11627              		.loc 1 5710 18 is_stmt 0 view .LVU4062
+ 11628 010a 0023     		movs	r3, #0
+ 11629 010c 84F84230 		strb	r3, [r4, #66]
+5713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11630              		.loc 1 5713 7 is_stmt 1 view .LVU4063
+5713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11631              		.loc 1 5713 7 view .LVU4064
+ 11632 0110 84F84030 		strb	r3, [r4, #64]
+ARM GAS  /tmp/ccbUHtu7.s 			page 393
+
+
+5713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11633              		.loc 1 5713 7 view .LVU4065
+5719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 11634              		.loc 1 5719 7 view .LVU4066
+ 11635 0114 2046     		mov	r0, r4
+ 11636 0116 FFF7FEFF 		bl	HAL_I2C_MemTxCpltCallback
+ 11637              	.LVL796:
+5719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 11638              		.loc 1 5719 7 is_stmt 0 view .LVU4067
+ 11639 011a AFE7     		b	.L707
+ 11640              	.LVL797:
+ 11641              	.L723:
+5745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11642              		.loc 1 5745 7 is_stmt 1 view .LVU4068
+5745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11643              		.loc 1 5745 18 is_stmt 0 view .LVU4069
+ 11644 011c 0023     		movs	r3, #0
+ 11645 011e 84F84230 		strb	r3, [r4, #66]
+5748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11646              		.loc 1 5748 7 is_stmt 1 view .LVU4070
+5748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11647              		.loc 1 5748 7 view .LVU4071
+ 11648 0122 84F84030 		strb	r3, [r4, #64]
+5748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11649              		.loc 1 5748 7 view .LVU4072
+5754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 11650              		.loc 1 5754 7 view .LVU4073
+ 11651 0126 2046     		mov	r0, r4
+ 11652 0128 FFF7FEFF 		bl	HAL_I2C_MemRxCpltCallback
+ 11653              	.LVL798:
+5754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 11654              		.loc 1 5754 7 is_stmt 0 view .LVU4074
+ 11655 012c A6E7     		b	.L707
+ 11656              		.cfi_endproc
+ 11657              	.LFE387:
+ 11659              		.section	.text.I2C_Master_ISR_IT,"ax",%progbits
+ 11660              		.align	1
+ 11661              		.syntax unified
+ 11662              		.thumb
+ 11663              		.thumb_func
+ 11665              	I2C_Master_ISR_IT:
+ 11666              	.LVL799:
+ 11667              	.LFB378:
+4745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint16_t devaddress;
+ 11668              		.loc 1 4745 1 is_stmt 1 view -0
+ 11669              		.cfi_startproc
+ 11670              		@ args = 0, pretend = 0, frame = 0
+ 11671              		@ frame_needed = 0, uses_anonymous_args = 0
+4746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 11672              		.loc 1 4746 3 view .LVU4076
+4747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11673              		.loc 1 4747 3 view .LVU4077
+4750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11674              		.loc 1 4750 3 view .LVU4078
+4750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11675              		.loc 1 4750 3 view .LVU4079
+ 11676 0000 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ARM GAS  /tmp/ccbUHtu7.s 			page 394
+
+
+ 11677 0004 012B     		cmp	r3, #1
+ 11678 0006 00F0B980 		beq	.L739
+4745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint16_t devaddress;
+ 11679              		.loc 1 4745 1 is_stmt 0 discriminator 2 view .LVU4080
+ 11680 000a 70B5     		push	{r4, r5, r6, lr}
+ 11681              	.LCFI126:
+ 11682              		.cfi_def_cfa_offset 16
+ 11683              		.cfi_offset 4, -16
+ 11684              		.cfi_offset 5, -12
+ 11685              		.cfi_offset 6, -8
+ 11686              		.cfi_offset 14, -4
+ 11687 000c 82B0     		sub	sp, sp, #8
+ 11688              	.LCFI127:
+ 11689              		.cfi_def_cfa_offset 24
+ 11690 000e 0446     		mov	r4, r0
+ 11691 0010 0D46     		mov	r5, r1
+ 11692 0012 1646     		mov	r6, r2
+4750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11693              		.loc 1 4750 3 is_stmt 1 discriminator 2 view .LVU4081
+ 11694 0014 0123     		movs	r3, #1
+ 11695 0016 80F84030 		strb	r3, [r0, #64]
+4750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11696              		.loc 1 4750 3 discriminator 2 view .LVU4082
+4752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 11697              		.loc 1 4752 3 discriminator 2 view .LVU4083
+4752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 11698              		.loc 1 4752 6 is_stmt 0 discriminator 2 view .LVU4084
+ 11699 001a 11F0100F 		tst	r1, #16
+ 11700 001e 02D0     		beq	.L727
+4752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 11701              		.loc 1 4752 58 discriminator 1 view .LVU4085
+ 11702 0020 12F0100F 		tst	r2, #16
+ 11703 0024 22D1     		bne	.L744
+ 11704              	.L727:
+4766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 11705              		.loc 1 4766 8 is_stmt 1 view .LVU4086
+4766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 11706              		.loc 1 4766 11 is_stmt 0 view .LVU4087
+ 11707 0026 15F0040F 		tst	r5, #4
+ 11708 002a 29D0     		beq	.L729
+4766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 11709              		.loc 1 4766 65 discriminator 1 view .LVU4088
+ 11710 002c 16F0040F 		tst	r6, #4
+ 11711 0030 26D0     		beq	.L729
+4770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11712              		.loc 1 4770 5 is_stmt 1 view .LVU4089
+4770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11713              		.loc 1 4770 16 is_stmt 0 view .LVU4090
+ 11714 0032 25F00405 		bic	r5, r5, #4
+ 11715              	.LVL800:
+4773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11716              		.loc 1 4773 5 is_stmt 1 view .LVU4091
+4773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11717              		.loc 1 4773 36 is_stmt 0 view .LVU4092
+ 11718 0036 2368     		ldr	r3, [r4]
+4773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11719              		.loc 1 4773 46 view .LVU4093
+ARM GAS  /tmp/ccbUHtu7.s 			page 395
+
+
+ 11720 0038 5A6A     		ldr	r2, [r3, #36]
+ 11721              	.LVL801:
+4773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11722              		.loc 1 4773 10 view .LVU4094
+ 11723 003a 636A     		ldr	r3, [r4, #36]
+4773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11724              		.loc 1 4773 21 view .LVU4095
+ 11725 003c 1A70     		strb	r2, [r3]
+4776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11726              		.loc 1 4776 5 is_stmt 1 view .LVU4096
+4776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11727              		.loc 1 4776 9 is_stmt 0 view .LVU4097
+ 11728 003e 636A     		ldr	r3, [r4, #36]
+4776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11729              		.loc 1 4776 19 view .LVU4098
+ 11730 0040 0133     		adds	r3, r3, #1
+ 11731 0042 6362     		str	r3, [r4, #36]
+4778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount--;
+ 11732              		.loc 1 4778 5 is_stmt 1 view .LVU4099
+4778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount--;
+ 11733              		.loc 1 4778 9 is_stmt 0 view .LVU4100
+ 11734 0044 238D     		ldrh	r3, [r4, #40]
+4778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount--;
+ 11735              		.loc 1 4778 19 view .LVU4101
+ 11736 0046 013B     		subs	r3, r3, #1
+ 11737 0048 2385     		strh	r3, [r4, #40]	@ movhi
+4779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11738              		.loc 1 4779 5 is_stmt 1 view .LVU4102
+4779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11739              		.loc 1 4779 9 is_stmt 0 view .LVU4103
+ 11740 004a 638D     		ldrh	r3, [r4, #42]
+ 11741 004c 9BB2     		uxth	r3, r3
+4779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11742              		.loc 1 4779 20 view .LVU4104
+ 11743 004e 013B     		subs	r3, r3, #1
+ 11744 0050 9BB2     		uxth	r3, r3
+ 11745 0052 6385     		strh	r3, [r4, #42]	@ movhi
+ 11746              	.LVL802:
+ 11747              	.L728:
+4866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11748              		.loc 1 4866 3 is_stmt 1 view .LVU4105
+4868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 11749              		.loc 1 4868 3 view .LVU4106
+4868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 11750              		.loc 1 4868 6 is_stmt 0 view .LVU4107
+ 11751 0054 15F0200F 		tst	r5, #32
+ 11752 0058 03D0     		beq	.L738
+4868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 11753              		.loc 1 4868 61 discriminator 1 view .LVU4108
+ 11754 005a 16F0200F 		tst	r6, #32
+ 11755 005e 40F08880 		bne	.L745
+ 11756              	.L738:
+4876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11757              		.loc 1 4876 3 is_stmt 1 view .LVU4109
+4876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11758              		.loc 1 4876 3 view .LVU4110
+ 11759 0062 0020     		movs	r0, #0
+ARM GAS  /tmp/ccbUHtu7.s 			page 396
+
+
+ 11760 0064 84F84000 		strb	r0, [r4, #64]
+4876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11761              		.loc 1 4876 3 view .LVU4111
+4878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 11762              		.loc 1 4878 3 view .LVU4112
+4879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11763              		.loc 1 4879 1 is_stmt 0 view .LVU4113
+ 11764 0068 02B0     		add	sp, sp, #8
+ 11765              	.LCFI128:
+ 11766              		.cfi_remember_state
+ 11767              		.cfi_def_cfa_offset 16
+ 11768              		@ sp needed
+ 11769 006a 70BD     		pop	{r4, r5, r6, pc}
+ 11770              	.LVL803:
+ 11771              	.L744:
+ 11772              	.LCFI129:
+ 11773              		.cfi_restore_state
+4756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11774              		.loc 1 4756 5 is_stmt 1 view .LVU4114
+ 11775 006c 0368     		ldr	r3, [r0]
+ 11776 006e 1022     		movs	r2, #16
+ 11777              	.LVL804:
+4756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11778              		.loc 1 4756 5 is_stmt 0 view .LVU4115
+ 11779 0070 DA61     		str	r2, [r3, #28]
+4761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11780              		.loc 1 4761 5 is_stmt 1 view .LVU4116
+4761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11781              		.loc 1 4761 9 is_stmt 0 view .LVU4117
+ 11782 0072 436C     		ldr	r3, [r0, #68]
+4761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11783              		.loc 1 4761 21 view .LVU4118
+ 11784 0074 43F00403 		orr	r3, r3, #4
+ 11785 0078 4364     		str	r3, [r0, #68]
+4764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11786              		.loc 1 4764 5 is_stmt 1 view .LVU4119
+ 11787 007a FFF7FEFF 		bl	I2C_Flush_TXDR
+ 11788              	.LVL805:
+4764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11789              		.loc 1 4764 5 is_stmt 0 view .LVU4120
+ 11790 007e E9E7     		b	.L728
+ 11791              	.LVL806:
+ 11792              	.L729:
+4781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 11793              		.loc 1 4781 8 is_stmt 1 view .LVU4121
+4781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 11794              		.loc 1 4781 11 is_stmt 0 view .LVU4122
+ 11795 0080 15F0020F 		tst	r5, #2
+ 11796 0084 12D0     		beq	.L730
+4781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 11797              		.loc 1 4781 65 discriminator 1 view .LVU4123
+ 11798 0086 16F0020F 		tst	r6, #2
+ 11799 008a 0FD0     		beq	.L730
+4785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11800              		.loc 1 4785 5 is_stmt 1 view .LVU4124
+4785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11801              		.loc 1 4785 33 is_stmt 0 view .LVU4125
+ARM GAS  /tmp/ccbUHtu7.s 			page 397
+
+
+ 11802 008c 626A     		ldr	r2, [r4, #36]
+ 11803              	.LVL807:
+4785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11804              		.loc 1 4785 9 view .LVU4126
+ 11805 008e 2368     		ldr	r3, [r4]
+4785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11806              		.loc 1 4785 28 view .LVU4127
+ 11807 0090 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+4785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11808              		.loc 1 4785 26 view .LVU4128
+ 11809 0092 9A62     		str	r2, [r3, #40]
+4788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11810              		.loc 1 4788 5 is_stmt 1 view .LVU4129
+4788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11811              		.loc 1 4788 9 is_stmt 0 view .LVU4130
+ 11812 0094 636A     		ldr	r3, [r4, #36]
+4788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11813              		.loc 1 4788 19 view .LVU4131
+ 11814 0096 0133     		adds	r3, r3, #1
+ 11815 0098 6362     		str	r3, [r4, #36]
+4790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount--;
+ 11816              		.loc 1 4790 5 is_stmt 1 view .LVU4132
+4790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount--;
+ 11817              		.loc 1 4790 9 is_stmt 0 view .LVU4133
+ 11818 009a 238D     		ldrh	r3, [r4, #40]
+4790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     hi2c->XferCount--;
+ 11819              		.loc 1 4790 19 view .LVU4134
+ 11820 009c 013B     		subs	r3, r3, #1
+ 11821 009e 2385     		strh	r3, [r4, #40]	@ movhi
+4791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11822              		.loc 1 4791 5 is_stmt 1 view .LVU4135
+4791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11823              		.loc 1 4791 9 is_stmt 0 view .LVU4136
+ 11824 00a0 638D     		ldrh	r3, [r4, #42]
+ 11825 00a2 9BB2     		uxth	r3, r3
+4791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 11826              		.loc 1 4791 20 view .LVU4137
+ 11827 00a4 013B     		subs	r3, r3, #1
+ 11828 00a6 9BB2     		uxth	r3, r3
+ 11829 00a8 6385     		strh	r3, [r4, #42]	@ movhi
+ 11830 00aa D3E7     		b	.L728
+ 11831              	.LVL808:
+ 11832              	.L730:
+4793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 11833              		.loc 1 4793 8 is_stmt 1 view .LVU4138
+4793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 11834              		.loc 1 4793 11 is_stmt 0 view .LVU4139
+ 11835 00ac 15F0800F 		tst	r5, #128
+ 11836 00b0 3FD0     		beq	.L731
+4793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 11837              		.loc 1 4793 64 discriminator 1 view .LVU4140
+ 11838 00b2 16F0400F 		tst	r6, #64
+ 11839 00b6 3CD0     		beq	.L731
+4796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11840              		.loc 1 4796 5 is_stmt 1 view .LVU4141
+4796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11841              		.loc 1 4796 14 is_stmt 0 view .LVU4142
+ARM GAS  /tmp/ccbUHtu7.s 			page 398
+
+
+ 11842 00b8 638D     		ldrh	r3, [r4, #42]
+ 11843 00ba 9BB2     		uxth	r3, r3
+4796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11844              		.loc 1 4796 8 view .LVU4143
+ 11845 00bc 5BB3     		cbz	r3, .L732
+4796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11846              		.loc 1 4796 41 discriminator 1 view .LVU4144
+ 11847 00be 238D     		ldrh	r3, [r4, #40]
+4796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11848              		.loc 1 4796 33 discriminator 1 view .LVU4145
+ 11849 00c0 4BBB     		cbnz	r3, .L732
+4798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11850              		.loc 1 4798 7 is_stmt 1 view .LVU4146
+4798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11851              		.loc 1 4798 35 is_stmt 0 view .LVU4147
+ 11852 00c2 2368     		ldr	r3, [r4]
+4798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11853              		.loc 1 4798 45 view .LVU4148
+ 11854 00c4 5968     		ldr	r1, [r3, #4]
+ 11855              	.LVL809:
+4798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 11856              		.loc 1 4798 18 view .LVU4149
+ 11857 00c6 C1F30901 		ubfx	r1, r1, #0, #10
+ 11858              	.LVL810:
+4800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11859              		.loc 1 4800 7 is_stmt 1 view .LVU4150
+4800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11860              		.loc 1 4800 15 is_stmt 0 view .LVU4151
+ 11861 00ca 638D     		ldrh	r3, [r4, #42]
+ 11862 00cc 9BB2     		uxth	r3, r3
+4800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11863              		.loc 1 4800 10 view .LVU4152
+ 11864 00ce FF2B     		cmp	r3, #255
+ 11865 00d0 0ED8     		bhi	.L746
+4807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 11866              		.loc 1 4807 9 is_stmt 1 view .LVU4153
+4807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 11867              		.loc 1 4807 30 is_stmt 0 view .LVU4154
+ 11868 00d2 628D     		ldrh	r2, [r4, #42]
+ 11869              	.LVL811:
+4807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 11870              		.loc 1 4807 30 view .LVU4155
+ 11871 00d4 92B2     		uxth	r2, r2
+4807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 11872              		.loc 1 4807 24 view .LVU4156
+ 11873 00d6 2285     		strh	r2, [r4, #40]	@ movhi
+4808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 11874              		.loc 1 4808 9 is_stmt 1 view .LVU4157
+4808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 11875              		.loc 1 4808 17 is_stmt 0 view .LVU4158
+ 11876 00d8 E36A     		ldr	r3, [r4, #44]
+4808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 11877              		.loc 1 4808 12 view .LVU4159
+ 11878 00da 13F5803F 		cmn	r3, #65536
+ 11879 00de 11D0     		beq	.L734
+4810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              hi2c->XferOptions, I2C_NO_STARTSTOP);
+ 11880              		.loc 1 4810 11 is_stmt 1 view .LVU4160
+ARM GAS  /tmp/ccbUHtu7.s 			page 399
+
+
+4811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 11881              		.loc 1 4811 34 is_stmt 0 view .LVU4161
+ 11882 00e0 E36A     		ldr	r3, [r4, #44]
+4810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              hi2c->XferOptions, I2C_NO_STARTSTOP);
+ 11883              		.loc 1 4810 11 view .LVU4162
+ 11884 00e2 0020     		movs	r0, #0
+ 11885              	.LVL812:
+4810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              hi2c->XferOptions, I2C_NO_STARTSTOP);
+ 11886              		.loc 1 4810 11 view .LVU4163
+ 11887 00e4 0090     		str	r0, [sp]
+ 11888 00e6 D2B2     		uxtb	r2, r2
+ 11889 00e8 2046     		mov	r0, r4
+ 11890 00ea FFF7FEFF 		bl	I2C_TransferConfig
+ 11891              	.LVL813:
+4810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              hi2c->XferOptions, I2C_NO_STARTSTOP);
+ 11892              		.loc 1 4810 11 view .LVU4164
+ 11893 00ee B1E7     		b	.L728
+ 11894              	.LVL814:
+ 11895              	.L746:
+4802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START
+ 11896              		.loc 1 4802 9 is_stmt 1 view .LVU4165
+4802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START
+ 11897              		.loc 1 4802 24 is_stmt 0 view .LVU4166
+ 11898 00f0 FF22     		movs	r2, #255
+ 11899              	.LVL815:
+4802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START
+ 11900              		.loc 1 4802 24 view .LVU4167
+ 11901 00f2 2285     		strh	r2, [r4, #40]	@ movhi
+4803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11902              		.loc 1 4803 9 is_stmt 1 view .LVU4168
+ 11903 00f4 0023     		movs	r3, #0
+ 11904 00f6 0093     		str	r3, [sp]
+ 11905 00f8 4FF08073 		mov	r3, #16777216
+ 11906 00fc 2046     		mov	r0, r4
+ 11907              	.LVL816:
+4803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11908              		.loc 1 4803 9 is_stmt 0 view .LVU4169
+ 11909 00fe FFF7FEFF 		bl	I2C_TransferConfig
+ 11910              	.LVL817:
+4803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11911              		.loc 1 4803 9 view .LVU4170
+ 11912 0102 A7E7     		b	.L728
+ 11913              	.LVL818:
+ 11914              	.L734:
+4815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ 11915              		.loc 1 4815 11 is_stmt 1 view .LVU4171
+ 11916 0104 0023     		movs	r3, #0
+ 11917 0106 0093     		str	r3, [sp]
+ 11918 0108 4FF00073 		mov	r3, #33554432
+ 11919 010c D2B2     		uxtb	r2, r2
+ 11920 010e 2046     		mov	r0, r4
+ 11921              	.LVL819:
+4815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ 11922              		.loc 1 4815 11 is_stmt 0 view .LVU4172
+ 11923 0110 FFF7FEFF 		bl	I2C_TransferConfig
+ 11924              	.LVL820:
+4815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                              I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ARM GAS  /tmp/ccbUHtu7.s 			page 400
+
+
+ 11925              		.loc 1 4815 11 view .LVU4173
+ 11926 0114 9EE7     		b	.L728
+ 11927              	.LVL821:
+ 11928              	.L732:
+4823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11929              		.loc 1 4823 7 is_stmt 1 view .LVU4174
+4823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11930              		.loc 1 4823 11 is_stmt 0 view .LVU4175
+ 11931 0116 2368     		ldr	r3, [r4]
+ 11932 0118 5B68     		ldr	r3, [r3, #4]
+4823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11933              		.loc 1 4823 10 view .LVU4176
+ 11934 011a 13F0007F 		tst	r3, #33554432
+ 11935 011e 03D1     		bne	.L735
+4826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11936              		.loc 1 4826 9 is_stmt 1 view .LVU4177
+ 11937 0120 2046     		mov	r0, r4
+ 11938              	.LVL822:
+4826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11939              		.loc 1 4826 9 is_stmt 0 view .LVU4178
+ 11940 0122 FFF7FEFF 		bl	I2C_ITMasterSeqCplt
+ 11941              	.LVL823:
+4826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11942              		.loc 1 4826 9 view .LVU4179
+ 11943 0126 95E7     		b	.L728
+ 11944              	.LVL824:
+ 11945              	.L735:
+4832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11946              		.loc 1 4832 9 is_stmt 1 view .LVU4180
+ 11947 0128 4021     		movs	r1, #64
+ 11948              	.LVL825:
+4832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11949              		.loc 1 4832 9 is_stmt 0 view .LVU4181
+ 11950 012a 2046     		mov	r0, r4
+ 11951              	.LVL826:
+4832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11952              		.loc 1 4832 9 view .LVU4182
+ 11953 012c FFF7FEFF 		bl	I2C_ITError
+ 11954              	.LVL827:
+4832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 11955              		.loc 1 4832 9 view .LVU4183
+ 11956 0130 90E7     		b	.L728
+ 11957              	.LVL828:
+ 11958              	.L731:
+4836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 11959              		.loc 1 4836 8 is_stmt 1 view .LVU4184
+4836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 11960              		.loc 1 4836 11 is_stmt 0 view .LVU4185
+ 11961 0132 15F0400F 		tst	r5, #64
+ 11962 0136 8DD0     		beq	.L728
+4836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 11963              		.loc 1 4836 63 discriminator 1 view .LVU4186
+ 11964 0138 16F0400F 		tst	r6, #64
+ 11965 013c 8AD0     		beq	.L728
+4839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11966              		.loc 1 4839 5 is_stmt 1 view .LVU4187
+4839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccbUHtu7.s 			page 401
+
+
+ 11967              		.loc 1 4839 13 is_stmt 0 view .LVU4188
+ 11968 013e 638D     		ldrh	r3, [r4, #42]
+ 11969 0140 9BB2     		uxth	r3, r3
+4839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 11970              		.loc 1 4839 8 view .LVU4189
+ 11971 0142 8BB9     		cbnz	r3, .L736
+4841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11972              		.loc 1 4841 7 is_stmt 1 view .LVU4190
+4841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11973              		.loc 1 4841 11 is_stmt 0 view .LVU4191
+ 11974 0144 2368     		ldr	r3, [r4]
+ 11975 0146 5A68     		ldr	r2, [r3, #4]
+ 11976              	.LVL829:
+4841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 11977              		.loc 1 4841 10 view .LVU4192
+ 11978 0148 12F0007F 		tst	r2, #33554432
+ 11979 014c 82D1     		bne	.L728
+4844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 11980              		.loc 1 4844 9 is_stmt 1 view .LVU4193
+4844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 11981              		.loc 1 4844 17 is_stmt 0 view .LVU4194
+ 11982 014e E26A     		ldr	r2, [r4, #44]
+4844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 11983              		.loc 1 4844 12 view .LVU4195
+ 11984 0150 12F5803F 		cmn	r2, #65536
+ 11985 0154 04D1     		bne	.L737
+4847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 11986              		.loc 1 4847 11 is_stmt 1 view .LVU4196
+4847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 11987              		.loc 1 4847 25 is_stmt 0 view .LVU4197
+ 11988 0156 5A68     		ldr	r2, [r3, #4]
+4847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 11989              		.loc 1 4847 31 view .LVU4198
+ 11990 0158 42F48042 		orr	r2, r2, #16384
+ 11991 015c 5A60     		str	r2, [r3, #4]
+ 11992 015e 79E7     		b	.L728
+ 11993              	.L737:
+4852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 11994              		.loc 1 4852 11 is_stmt 1 view .LVU4199
+ 11995 0160 2046     		mov	r0, r4
+ 11996              	.LVL830:
+4852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 11997              		.loc 1 4852 11 is_stmt 0 view .LVU4200
+ 11998 0162 FFF7FEFF 		bl	I2C_ITMasterSeqCplt
+ 11999              	.LVL831:
+4852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12000              		.loc 1 4852 11 view .LVU4201
+ 12001 0166 75E7     		b	.L728
+ 12002              	.LVL832:
+ 12003              	.L736:
+4860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12004              		.loc 1 4860 7 is_stmt 1 view .LVU4202
+ 12005 0168 4021     		movs	r1, #64
+ 12006              	.LVL833:
+4860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12007              		.loc 1 4860 7 is_stmt 0 view .LVU4203
+ 12008 016a 2046     		mov	r0, r4
+ARM GAS  /tmp/ccbUHtu7.s 			page 402
+
+
+ 12009              	.LVL834:
+4860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12010              		.loc 1 4860 7 view .LVU4204
+ 12011 016c FFF7FEFF 		bl	I2C_ITError
+ 12012              	.LVL835:
+4860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12013              		.loc 1 4860 7 view .LVU4205
+ 12014 0170 70E7     		b	.L728
+ 12015              	.LVL836:
+ 12016              	.L745:
+4872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12017              		.loc 1 4872 5 is_stmt 1 view .LVU4206
+ 12018 0172 2946     		mov	r1, r5
+ 12019 0174 2046     		mov	r0, r4
+ 12020 0176 FFF7FEFF 		bl	I2C_ITMasterCplt
+ 12021              	.LVL837:
+ 12022 017a 72E7     		b	.L738
+ 12023              	.LVL838:
+ 12024              	.L739:
+ 12025              	.LCFI130:
+ 12026              		.cfi_def_cfa_offset 0
+ 12027              		.cfi_restore 4
+ 12028              		.cfi_restore 5
+ 12029              		.cfi_restore 6
+ 12030              		.cfi_restore 14
+4750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12031              		.loc 1 4750 3 is_stmt 0 view .LVU4207
+ 12032 017c 0220     		movs	r0, #2
+ 12033              	.LVL839:
+4879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12034              		.loc 1 4879 1 view .LVU4208
+ 12035 017e 7047     		bx	lr
+ 12036              		.cfi_endproc
+ 12037              	.LFE378:
+ 12039              		.section	.text.I2C_Slave_ISR_DMA,"ax",%progbits
+ 12040              		.align	1
+ 12041              		.syntax unified
+ 12042              		.thumb
+ 12043              		.thumb_func
+ 12045              	I2C_Slave_ISR_DMA:
+ 12046              	.LVL840:
+ 12047              	.LFB381:
+5172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 12048              		.loc 1 5172 1 is_stmt 1 view -0
+ 12049              		.cfi_startproc
+ 12050              		@ args = 0, pretend = 0, frame = 0
+ 12051              		@ frame_needed = 0, uses_anonymous_args = 0
+5172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 12052              		.loc 1 5172 1 is_stmt 0 view .LVU4210
+ 12053 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 12054              	.LCFI131:
+ 12055              		.cfi_def_cfa_offset 24
+ 12056              		.cfi_offset 3, -24
+ 12057              		.cfi_offset 4, -20
+ 12058              		.cfi_offset 5, -16
+ 12059              		.cfi_offset 6, -12
+ 12060              		.cfi_offset 7, -8
+ARM GAS  /tmp/ccbUHtu7.s 			page 403
+
+
+ 12061              		.cfi_offset 14, -4
+5173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t treatdmanack = 0U;
+ 12062              		.loc 1 5173 3 is_stmt 1 view .LVU4211
+5173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t treatdmanack = 0U;
+ 12063              		.loc 1 5173 12 is_stmt 0 view .LVU4212
+ 12064 0002 C76A     		ldr	r7, [r0, #44]
+ 12065              	.LVL841:
+5174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate;
+ 12066              		.loc 1 5174 3 is_stmt 1 view .LVU4213
+5175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12067              		.loc 1 5175 3 view .LVU4214
+5178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12068              		.loc 1 5178 3 view .LVU4215
+5178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12069              		.loc 1 5178 3 view .LVU4216
+ 12070 0004 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 12071 0008 012B     		cmp	r3, #1
+ 12072 000a 00F08780 		beq	.L764
+ 12073 000e 0446     		mov	r4, r0
+ 12074 0010 0D46     		mov	r5, r1
+ 12075 0012 1646     		mov	r6, r2
+5178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12076              		.loc 1 5178 3 discriminator 2 view .LVU4217
+ 12077 0014 0123     		movs	r3, #1
+ 12078 0016 80F84030 		strb	r3, [r0, #64]
+5178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12079              		.loc 1 5178 3 discriminator 2 view .LVU4218
+5181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 12080              		.loc 1 5181 3 discriminator 2 view .LVU4219
+5181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 12081              		.loc 1 5181 6 is_stmt 0 discriminator 2 view .LVU4220
+ 12082 001a 11F0200F 		tst	r1, #32
+ 12083 001e 02D0     		beq	.L749
+5181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 12084              		.loc 1 5181 58 discriminator 1 view .LVU4221
+ 12085 0020 12F0200F 		tst	r2, #32
+ 12086 0024 12D1     		bne	.L769
+ 12087              	.LVL842:
+ 12088              	.L749:
+5188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 12089              		.loc 1 5188 3 is_stmt 1 view .LVU4222
+5188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 12090              		.loc 1 5188 6 is_stmt 0 view .LVU4223
+ 12091 0026 15F0100F 		tst	r5, #16
+ 12092 002a 68D0     		beq	.L750
+5188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 12093              		.loc 1 5188 55 discriminator 1 view .LVU4224
+ 12094 002c 16F0100F 		tst	r6, #16
+ 12095 0030 65D0     		beq	.L750
+5195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+ 12096              		.loc 1 5195 5 is_stmt 1 view .LVU4225
+5195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+ 12097              		.loc 1 5195 8 is_stmt 0 view .LVU4226
+ 12098 0032 16F4404F 		tst	r6, #49152
+ 12099 0036 5ED0     		beq	.L751
+5199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12100              		.loc 1 5199 7 is_stmt 1 view .LVU4227
+ARM GAS  /tmp/ccbUHtu7.s 			page 404
+
+
+5199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12101              		.loc 1 5199 15 is_stmt 0 view .LVU4228
+ 12102 0038 E36B     		ldr	r3, [r4, #60]
+5199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12103              		.loc 1 5199 10 view .LVU4229
+ 12104 003a 53B1     		cbz	r3, .L765
+5201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12105              		.loc 1 5201 9 is_stmt 1 view .LVU4230
+5201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12106              		.loc 1 5201 12 is_stmt 0 view .LVU4231
+ 12107 003c 16F40042 		ands	r2, r6, #32768
+ 12108 0040 08D0     		beq	.L752
+5203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 12109              		.loc 1 5203 11 is_stmt 1 view .LVU4232
+5203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 12110              		.loc 1 5203 15 is_stmt 0 view .LVU4233
+ 12111 0042 1B68     		ldr	r3, [r3]
+ 12112 0044 5B68     		ldr	r3, [r3, #4]
+5203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 12113              		.loc 1 5203 14 view .LVU4234
+ 12114 0046 3BB3     		cbz	r3, .L766
+5174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate;
+ 12115              		.loc 1 5174 12 view .LVU4235
+ 12116 0048 0022     		movs	r2, #0
+ 12117 004a 03E0     		b	.L752
+ 12118              	.LVL843:
+ 12119              	.L769:
+5185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12120              		.loc 1 5185 5 is_stmt 1 view .LVU4236
+ 12121 004c FFF7FEFF 		bl	I2C_ITSlaveCplt
+ 12122              	.LVL844:
+5185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12123              		.loc 1 5185 5 is_stmt 0 view .LVU4237
+ 12124 0050 E9E7     		b	.L749
+ 12125              	.L765:
+5174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate;
+ 12126              		.loc 1 5174 12 view .LVU4238
+ 12127 0052 0022     		movs	r2, #0
+ 12128              	.L752:
+ 12129              	.LVL845:
+5211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12130              		.loc 1 5211 7 is_stmt 1 view .LVU4239
+5211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12131              		.loc 1 5211 15 is_stmt 0 view .LVU4240
+ 12132 0054 A36B     		ldr	r3, [r4, #56]
+5211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12133              		.loc 1 5211 10 view .LVU4241
+ 12134 0056 2BB1     		cbz	r3, .L753
+5213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12135              		.loc 1 5213 9 is_stmt 1 view .LVU4242
+5213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12136              		.loc 1 5213 12 is_stmt 0 view .LVU4243
+ 12137 0058 16F4804F 		tst	r6, #16384
+ 12138 005c 02D0     		beq	.L753
+5215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 12139              		.loc 1 5215 11 is_stmt 1 view .LVU4244
+5215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ARM GAS  /tmp/ccbUHtu7.s 			page 405
+
+
+ 12140              		.loc 1 5215 15 is_stmt 0 view .LVU4245
+ 12141 005e 1B68     		ldr	r3, [r3]
+ 12142 0060 5B68     		ldr	r3, [r3, #4]
+5215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 12143              		.loc 1 5215 14 view .LVU4246
+ 12144 0062 DBB1     		cbz	r3, .L754
+ 12145              	.L753:
+5222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12146              		.loc 1 5222 7 is_stmt 1 view .LVU4247
+5222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12147              		.loc 1 5222 10 is_stmt 0 view .LVU4248
+ 12148 0064 012A     		cmp	r2, #1
+ 12149 0066 19D0     		beq	.L754
+5253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12150              		.loc 1 5253 9 is_stmt 1 view .LVU4249
+ 12151 0068 2368     		ldr	r3, [r4]
+ 12152 006a 1022     		movs	r2, #16
+ 12153              	.LVL846:
+5253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12154              		.loc 1 5253 9 is_stmt 0 view .LVU4250
+ 12155 006c DA61     		str	r2, [r3, #28]
+5256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12156              		.loc 1 5256 9 is_stmt 1 view .LVU4251
+5256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12157              		.loc 1 5256 13 is_stmt 0 view .LVU4252
+ 12158 006e 636C     		ldr	r3, [r4, #68]
+5256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12159              		.loc 1 5256 25 view .LVU4253
+ 12160 0070 43F00403 		orr	r3, r3, #4
+ 12161 0074 6364     		str	r3, [r4, #68]
+5259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12162              		.loc 1 5259 9 is_stmt 1 view .LVU4254
+5259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12163              		.loc 1 5259 18 is_stmt 0 view .LVU4255
+ 12164 0076 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 12165 007a DBB2     		uxtb	r3, r3
+ 12166              	.LVL847:
+5261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12167              		.loc 1 5261 9 is_stmt 1 view .LVU4256
+5261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12168              		.loc 1 5261 12 is_stmt 0 view .LVU4257
+ 12169 007c 17B1     		cbz	r7, .L759
+5261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12170              		.loc 1 5261 45 discriminator 1 view .LVU4258
+ 12171 007e B7F1807F 		cmp	r7, #16777216
+ 12172 0082 42D1     		bne	.L757
+ 12173              	.L759:
+5263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 12174              		.loc 1 5263 11 is_stmt 1 view .LVU4259
+ 12175 0084 213B     		subs	r3, r3, #33
+ 12176              	.LVL848:
+5263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           {
+ 12177              		.loc 1 5263 11 is_stmt 0 view .LVU4260
+ 12178 0086 092B     		cmp	r3, #9
+ 12179 0088 2DD8     		bhi	.L760
+ 12180 008a DFE803F0 		tbb	[pc, r3]
+ 12181              	.L762:
+ARM GAS  /tmp/ccbUHtu7.s 			page 406
+
+
+ 12182 008e 2A       		.byte	(.L763-.L762)/2
+ 12183 008f 31       		.byte	(.L761-.L762)/2
+ 12184 0090 2C       		.byte	(.L760-.L762)/2
+ 12185 0091 2C       		.byte	(.L760-.L762)/2
+ 12186 0092 2C       		.byte	(.L760-.L762)/2
+ 12187 0093 2C       		.byte	(.L760-.L762)/2
+ 12188 0094 2C       		.byte	(.L760-.L762)/2
+ 12189 0095 2C       		.byte	(.L760-.L762)/2
+ 12190 0096 2A       		.byte	(.L763-.L762)/2
+ 12191 0097 31       		.byte	(.L761-.L762)/2
+ 12192              	.LVL849:
+ 12193              		.p2align 1
+ 12194              	.L766:
+5205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 12195              		.loc 1 5205 26 view .LVU4261
+ 12196 0098 0122     		movs	r2, #1
+ 12197 009a DBE7     		b	.L752
+ 12198              	.LVL850:
+ 12199              	.L754:
+5224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 12200              		.loc 1 5224 9 is_stmt 1 view .LVU4262
+5224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 12201              		.loc 1 5224 18 is_stmt 0 view .LVU4263
+ 12202 009c 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 12203 00a0 DBB2     		uxtb	r3, r3
+5224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 12204              		.loc 1 5224 12 view .LVU4264
+ 12205 00a2 282B     		cmp	r3, #40
+ 12206 00a4 08D0     		beq	.L770
+ 12207              	.L756:
+5231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12208              		.loc 1 5231 14 is_stmt 1 view .LVU4265
+5231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12209              		.loc 1 5231 23 is_stmt 0 view .LVU4266
+ 12210 00a6 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 12211 00aa DBB2     		uxtb	r3, r3
+5231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12212              		.loc 1 5231 17 view .LVU4267
+ 12213 00ac 292B     		cmp	r3, #41
+ 12214 00ae 0BD0     		beq	.L771
+ 12215              	.L758:
+5246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12216              		.loc 1 5246 11 is_stmt 1 view .LVU4268
+ 12217 00b0 2368     		ldr	r3, [r4]
+ 12218 00b2 1022     		movs	r2, #16
+ 12219 00b4 DA61     		str	r2, [r3, #28]
+ 12220 00b6 28E0     		b	.L757
+ 12221              	.L770:
+5224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 12222              		.loc 1 5224 51 is_stmt 0 discriminator 1 view .LVU4269
+ 12223 00b8 B7F1007F 		cmp	r7, #33554432
+ 12224 00bc F3D1     		bne	.L756
+5229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12225              		.loc 1 5229 11 is_stmt 1 view .LVU4270
+ 12226 00be 2946     		mov	r1, r5
+ 12227 00c0 2046     		mov	r0, r4
+ 12228 00c2 FFF7FEFF 		bl	I2C_ITListenCplt
+ARM GAS  /tmp/ccbUHtu7.s 			page 407
+
+
+ 12229              	.LVL851:
+ 12230 00c6 20E0     		b	.L757
+ 12231              	.L771:
+5231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12232              		.loc 1 5231 64 is_stmt 0 discriminator 1 view .LVU4271
+ 12233 00c8 17F5803F 		cmn	r7, #65536
+ 12234 00cc F0D0     		beq	.L758
+5234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12235              		.loc 1 5234 11 is_stmt 1 view .LVU4272
+ 12236 00ce 2368     		ldr	r3, [r4]
+ 12237 00d0 1022     		movs	r2, #16
+ 12238 00d2 DA61     		str	r2, [r3, #28]
+5237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12239              		.loc 1 5237 11 view .LVU4273
+ 12240 00d4 2046     		mov	r0, r4
+ 12241 00d6 FFF7FEFF 		bl	I2C_Flush_TXDR
+ 12242              	.LVL852:
+5241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12243              		.loc 1 5241 11 view .LVU4274
+ 12244 00da 2046     		mov	r0, r4
+ 12245 00dc FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 12246              	.LVL853:
+ 12247 00e0 13E0     		b	.L757
+ 12248              	.LVL854:
+ 12249              	.L763:
+5265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 12250              		.loc 1 5265 13 view .LVU4275
+5265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 12251              		.loc 1 5265 33 is_stmt 0 view .LVU4276
+ 12252 00e2 2123     		movs	r3, #33
+ 12253              	.LVL855:
+5265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 12254              		.loc 1 5265 33 view .LVU4277
+ 12255 00e4 2363     		str	r3, [r4, #48]
+ 12256              	.L760:
+5277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12257              		.loc 1 5277 11 is_stmt 1 view .LVU4278
+5277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12258              		.loc 1 5277 33 is_stmt 0 view .LVU4279
+ 12259 00e6 616C     		ldr	r1, [r4, #68]
+5277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12260              		.loc 1 5277 11 view .LVU4280
+ 12261 00e8 2046     		mov	r0, r4
+ 12262 00ea FFF7FEFF 		bl	I2C_ITError
+ 12263              	.LVL856:
+ 12264 00ee 0CE0     		b	.L757
+ 12265              	.LVL857:
+ 12266              	.L761:
+5269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 12267              		.loc 1 5269 13 is_stmt 1 view .LVU4281
+5269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 12268              		.loc 1 5269 33 is_stmt 0 view .LVU4282
+ 12269 00f0 2223     		movs	r3, #34
+ 12270              	.LVL858:
+5269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****           }
+ 12271              		.loc 1 5269 33 view .LVU4283
+ 12272 00f2 2363     		str	r3, [r4, #48]
+ARM GAS  /tmp/ccbUHtu7.s 			page 408
+
+
+ 12273 00f4 F7E7     		b	.L760
+ 12274              	.LVL859:
+ 12275              	.L751:
+5284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12276              		.loc 1 5284 7 is_stmt 1 view .LVU4284
+ 12277 00f6 2368     		ldr	r3, [r4]
+ 12278 00f8 1022     		movs	r2, #16
+ 12279 00fa DA61     		str	r2, [r3, #28]
+ 12280 00fc 05E0     		b	.L757
+ 12281              	.L750:
+5287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 12282              		.loc 1 5287 8 view .LVU4285
+5287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 12283              		.loc 1 5287 11 is_stmt 0 view .LVU4286
+ 12284 00fe 15F0080F 		tst	r5, #8
+ 12285 0102 02D0     		beq	.L757
+5287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 12286              		.loc 1 5287 62 discriminator 1 view .LVU4287
+ 12287 0104 16F0080F 		tst	r6, #8
+ 12288 0108 03D1     		bne	.L772
+ 12289              	.LVL860:
+ 12290              	.L757:
+5295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12291              		.loc 1 5295 3 is_stmt 1 view .LVU4288
+5298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12292              		.loc 1 5298 3 view .LVU4289
+5298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12293              		.loc 1 5298 3 view .LVU4290
+ 12294 010a 0020     		movs	r0, #0
+ 12295 010c 84F84000 		strb	r0, [r4, #64]
+5298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12296              		.loc 1 5298 3 view .LVU4291
+5300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 12297              		.loc 1 5300 3 view .LVU4292
+ 12298              	.LVL861:
+ 12299              	.L748:
+5301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12300              		.loc 1 5301 1 is_stmt 0 view .LVU4293
+ 12301 0110 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 12302              	.LVL862:
+ 12303              	.L772:
+5290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12304              		.loc 1 5290 5 is_stmt 1 view .LVU4294
+ 12305 0112 2946     		mov	r1, r5
+ 12306 0114 2046     		mov	r0, r4
+ 12307 0116 FFF7FEFF 		bl	I2C_ITAddrCplt
+ 12308              	.LVL863:
+ 12309 011a F6E7     		b	.L757
+ 12310              	.LVL864:
+ 12311              	.L764:
+5178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12312              		.loc 1 5178 3 is_stmt 0 view .LVU4295
+ 12313 011c 0220     		movs	r0, #2
+ 12314              	.LVL865:
+5178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12315              		.loc 1 5178 3 view .LVU4296
+ 12316 011e F7E7     		b	.L748
+ARM GAS  /tmp/ccbUHtu7.s 			page 409
+
+
+ 12317              		.cfi_endproc
+ 12318              	.LFE381:
+ 12320              		.section	.text.I2C_Master_ISR_DMA,"ax",%progbits
+ 12321              		.align	1
+ 12322              		.syntax unified
+ 12323              		.thumb
+ 12324              		.thumb_func
+ 12326              	I2C_Master_ISR_DMA:
+ 12327              	.LVL866:
+ 12328              	.LFB380:
+5032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint16_t devaddress;
+ 12329              		.loc 1 5032 1 is_stmt 1 view -0
+ 12330              		.cfi_startproc
+ 12331              		@ args = 0, pretend = 0, frame = 0
+ 12332              		@ frame_needed = 0, uses_anonymous_args = 0
+5033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t xfermode;
+ 12333              		.loc 1 5033 3 view .LVU4298
+5034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12334              		.loc 1 5034 3 view .LVU4299
+5037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12335              		.loc 1 5037 3 view .LVU4300
+5037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12336              		.loc 1 5037 3 view .LVU4301
+ 12337 0000 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 12338 0004 012B     		cmp	r3, #1
+ 12339 0006 00F09A80 		beq	.L786
+5032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint16_t devaddress;
+ 12340              		.loc 1 5032 1 is_stmt 0 discriminator 2 view .LVU4302
+ 12341 000a 10B5     		push	{r4, lr}
+ 12342              	.LCFI132:
+ 12343              		.cfi_def_cfa_offset 8
+ 12344              		.cfi_offset 4, -8
+ 12345              		.cfi_offset 14, -4
+ 12346 000c 82B0     		sub	sp, sp, #8
+ 12347              	.LCFI133:
+ 12348              		.cfi_def_cfa_offset 16
+ 12349 000e 0446     		mov	r4, r0
+5037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12350              		.loc 1 5037 3 is_stmt 1 discriminator 2 view .LVU4303
+ 12351 0010 0123     		movs	r3, #1
+ 12352 0012 80F84030 		strb	r3, [r0, #64]
+5037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12353              		.loc 1 5037 3 discriminator 2 view .LVU4304
+5039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 12354              		.loc 1 5039 3 discriminator 2 view .LVU4305
+5039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 12355              		.loc 1 5039 6 is_stmt 0 discriminator 2 view .LVU4306
+ 12356 0016 11F0100F 		tst	r1, #16
+ 12357 001a 02D0     		beq	.L775
+5039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 12358              		.loc 1 5039 55 discriminator 1 view .LVU4307
+ 12359 001c 12F0100F 		tst	r2, #16
+ 12360 0020 32D1     		bne	.L792
+ 12361              	.L775:
+5056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12362              		.loc 1 5056 8 is_stmt 1 view .LVU4308
+5056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ARM GAS  /tmp/ccbUHtu7.s 			page 410
+
+
+ 12363              		.loc 1 5056 11 is_stmt 0 view .LVU4309
+ 12364 0022 11F0800F 		tst	r1, #128
+ 12365 0026 60D0     		beq	.L777
+5056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12366              		.loc 1 5056 61 discriminator 1 view .LVU4310
+ 12367 0028 12F0400F 		tst	r2, #64
+ 12368 002c 5DD0     		beq	.L777
+5060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12369              		.loc 1 5060 5 is_stmt 1 view .LVU4311
+ 12370 002e 2268     		ldr	r2, [r4]
+ 12371              	.LVL867:
+5060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12372              		.loc 1 5060 5 is_stmt 0 view .LVU4312
+ 12373 0030 1368     		ldr	r3, [r2]
+ 12374 0032 23F04003 		bic	r3, r3, #64
+ 12375 0036 1360     		str	r3, [r2]
+5062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 12376              		.loc 1 5062 5 is_stmt 1 view .LVU4313
+5062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 12377              		.loc 1 5062 13 is_stmt 0 view .LVU4314
+ 12378 0038 638D     		ldrh	r3, [r4, #42]
+ 12379 003a 9BB2     		uxth	r3, r3
+5062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 12380              		.loc 1 5062 8 view .LVU4315
+ 12381 003c 002B     		cmp	r3, #0
+ 12382 003e 46D0     		beq	.L778
+5065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12383              		.loc 1 5065 7 is_stmt 1 view .LVU4316
+5065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12384              		.loc 1 5065 35 is_stmt 0 view .LVU4317
+ 12385 0040 2368     		ldr	r3, [r4]
+5065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12386              		.loc 1 5065 45 view .LVU4318
+ 12387 0042 5968     		ldr	r1, [r3, #4]
+ 12388              	.LVL868:
+5065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12389              		.loc 1 5065 18 view .LVU4319
+ 12390 0044 C1F30901 		ubfx	r1, r1, #0, #10
+ 12391              	.LVL869:
+5068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12392              		.loc 1 5068 7 is_stmt 1 view .LVU4320
+5068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12393              		.loc 1 5068 15 is_stmt 0 view .LVU4321
+ 12394 0048 638D     		ldrh	r3, [r4, #42]
+ 12395 004a 9BB2     		uxth	r3, r3
+5068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12396              		.loc 1 5068 10 view .LVU4322
+ 12397 004c FF2B     		cmp	r3, #255
+ 12398 004e 2DD9     		bls	.L779
+5070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         xfermode = I2C_RELOAD_MODE;
+ 12399              		.loc 1 5070 9 is_stmt 1 view .LVU4323
+5070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         xfermode = I2C_RELOAD_MODE;
+ 12400              		.loc 1 5070 24 is_stmt 0 view .LVU4324
+ 12401 0050 FF23     		movs	r3, #255
+ 12402 0052 2385     		strh	r3, [r4, #40]	@ movhi
+5071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12403              		.loc 1 5071 9 is_stmt 1 view .LVU4325
+ARM GAS  /tmp/ccbUHtu7.s 			page 411
+
+
+ 12404              	.LVL870:
+5071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12405              		.loc 1 5071 18 is_stmt 0 view .LVU4326
+ 12406 0054 4FF08073 		mov	r3, #16777216
+ 12407              	.LVL871:
+ 12408              	.L780:
+5087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12409              		.loc 1 5087 7 is_stmt 1 view .LVU4327
+ 12410 0058 0022     		movs	r2, #0
+ 12411 005a 0092     		str	r2, [sp]
+ 12412 005c 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 12413 0060 2046     		mov	r0, r4
+ 12414              	.LVL872:
+5087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12415              		.loc 1 5087 7 is_stmt 0 view .LVU4328
+ 12416 0062 FFF7FEFF 		bl	I2C_TransferConfig
+ 12417              	.LVL873:
+5090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12418              		.loc 1 5090 7 is_stmt 1 view .LVU4329
+5090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12419              		.loc 1 5090 11 is_stmt 0 view .LVU4330
+ 12420 0066 638D     		ldrh	r3, [r4, #42]
+ 12421 0068 9BB2     		uxth	r3, r3
+5090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12422              		.loc 1 5090 30 view .LVU4331
+ 12423 006a 228D     		ldrh	r2, [r4, #40]
+5090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12424              		.loc 1 5090 23 view .LVU4332
+ 12425 006c 9B1A     		subs	r3, r3, r2
+ 12426 006e 9BB2     		uxth	r3, r3
+ 12427 0070 6385     		strh	r3, [r4, #42]	@ movhi
+5093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12428              		.loc 1 5093 7 is_stmt 1 view .LVU4333
+5093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12429              		.loc 1 5093 15 is_stmt 0 view .LVU4334
+ 12430 0072 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 12431 0076 DBB2     		uxtb	r3, r3
+5093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12432              		.loc 1 5093 10 view .LVU4335
+ 12433 0078 222B     		cmp	r3, #34
+ 12434 007a 22D0     		beq	.L793
+5099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12435              		.loc 1 5099 9 is_stmt 1 view .LVU4336
+5099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12436              		.loc 1 5099 13 is_stmt 0 view .LVU4337
+ 12437 007c 2268     		ldr	r2, [r4]
+5099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12438              		.loc 1 5099 23 view .LVU4338
+ 12439 007e 1368     		ldr	r3, [r2]
+5099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12440              		.loc 1 5099 29 view .LVU4339
+ 12441 0080 43F48043 		orr	r3, r3, #16384
+ 12442 0084 1360     		str	r3, [r2]
+ 12443 0086 0CE0     		b	.L776
+ 12444              	.LVL874:
+ 12445              	.L792:
+5043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccbUHtu7.s 			page 412
+
+
+ 12446              		.loc 1 5043 5 is_stmt 1 view .LVU4340
+ 12447 0088 0368     		ldr	r3, [r0]
+ 12448 008a 1022     		movs	r2, #16
+ 12449              	.LVL875:
+5043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12450              		.loc 1 5043 5 is_stmt 0 view .LVU4341
+ 12451 008c DA61     		str	r2, [r3, #28]
+5046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12452              		.loc 1 5046 5 is_stmt 1 view .LVU4342
+5046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12453              		.loc 1 5046 9 is_stmt 0 view .LVU4343
+ 12454 008e 436C     		ldr	r3, [r0, #68]
+5046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12455              		.loc 1 5046 21 view .LVU4344
+ 12456 0090 43F00403 		orr	r3, r3, #4
+ 12457 0094 4364     		str	r3, [r0, #68]
+5051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12458              		.loc 1 5051 5 is_stmt 1 view .LVU4345
+ 12459 0096 2021     		movs	r1, #32
+ 12460              	.LVL876:
+5051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12461              		.loc 1 5051 5 is_stmt 0 view .LVU4346
+ 12462 0098 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 12463              	.LVL877:
+5054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12464              		.loc 1 5054 5 is_stmt 1 view .LVU4347
+ 12465 009c 2046     		mov	r0, r4
+ 12466 009e FFF7FEFF 		bl	I2C_Flush_TXDR
+ 12467              	.LVL878:
+ 12468              	.L776:
+5154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12469              		.loc 1 5154 3 view .LVU4348
+5157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12470              		.loc 1 5157 3 view .LVU4349
+5157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12471              		.loc 1 5157 3 view .LVU4350
+ 12472 00a2 0020     		movs	r0, #0
+ 12473 00a4 84F84000 		strb	r0, [r4, #64]
+5157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12474              		.loc 1 5157 3 view .LVU4351
+5159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 12475              		.loc 1 5159 3 view .LVU4352
+5160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12476              		.loc 1 5160 1 is_stmt 0 view .LVU4353
+ 12477 00a8 02B0     		add	sp, sp, #8
+ 12478              	.LCFI134:
+ 12479              		.cfi_remember_state
+ 12480              		.cfi_def_cfa_offset 8
+ 12481              		@ sp needed
+ 12482 00aa 10BD     		pop	{r4, pc}
+ 12483              	.LVL879:
+ 12484              	.L779:
+ 12485              	.LCFI135:
+ 12486              		.cfi_restore_state
+5075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 12487              		.loc 1 5075 9 is_stmt 1 view .LVU4354
+5075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ARM GAS  /tmp/ccbUHtu7.s 			page 413
+
+
+ 12488              		.loc 1 5075 30 is_stmt 0 view .LVU4355
+ 12489 00ac 638D     		ldrh	r3, [r4, #42]
+5075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 12490              		.loc 1 5075 24 view .LVU4356
+ 12491 00ae 2385     		strh	r3, [r4, #40]	@ movhi
+5076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12492              		.loc 1 5076 9 is_stmt 1 view .LVU4357
+5076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12493              		.loc 1 5076 17 is_stmt 0 view .LVU4358
+ 12494 00b0 E36A     		ldr	r3, [r4, #44]
+5076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12495              		.loc 1 5076 12 view .LVU4359
+ 12496 00b2 13F5803F 		cmn	r3, #65536
+ 12497 00b6 01D0     		beq	.L787
+5078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12498              		.loc 1 5078 11 is_stmt 1 view .LVU4360
+5078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12499              		.loc 1 5078 20 is_stmt 0 view .LVU4361
+ 12500 00b8 E36A     		ldr	r3, [r4, #44]
+ 12501              	.LVL880:
+5078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12502              		.loc 1 5078 20 view .LVU4362
+ 12503 00ba CDE7     		b	.L780
+ 12504              	.LVL881:
+ 12505              	.L787:
+5082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12506              		.loc 1 5082 20 view .LVU4363
+ 12507 00bc 4FF00073 		mov	r3, #33554432
+ 12508 00c0 CAE7     		b	.L780
+ 12509              	.LVL882:
+ 12510              	.L793:
+5095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12511              		.loc 1 5095 9 is_stmt 1 view .LVU4364
+5095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12512              		.loc 1 5095 13 is_stmt 0 view .LVU4365
+ 12513 00c2 2268     		ldr	r2, [r4]
+5095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12514              		.loc 1 5095 23 view .LVU4366
+ 12515 00c4 1368     		ldr	r3, [r2]
+5095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12516              		.loc 1 5095 29 view .LVU4367
+ 12517 00c6 43F40043 		orr	r3, r3, #32768
+ 12518 00ca 1360     		str	r3, [r2]
+ 12519 00cc E9E7     		b	.L776
+ 12520              	.LVL883:
+ 12521              	.L778:
+5105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12522              		.loc 1 5105 7 is_stmt 1 view .LVU4368
+5105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12523              		.loc 1 5105 11 is_stmt 0 view .LVU4369
+ 12524 00ce 2368     		ldr	r3, [r4]
+ 12525 00d0 5B68     		ldr	r3, [r3, #4]
+5105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12526              		.loc 1 5105 10 view .LVU4370
+ 12527 00d2 13F0007F 		tst	r3, #33554432
+ 12528 00d6 03D1     		bne	.L782
+5108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ARM GAS  /tmp/ccbUHtu7.s 			page 414
+
+
+ 12529              		.loc 1 5108 9 is_stmt 1 view .LVU4371
+ 12530 00d8 2046     		mov	r0, r4
+ 12531              	.LVL884:
+5108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12532              		.loc 1 5108 9 is_stmt 0 view .LVU4372
+ 12533 00da FFF7FEFF 		bl	I2C_ITMasterSeqCplt
+ 12534              	.LVL885:
+5108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12535              		.loc 1 5108 9 view .LVU4373
+ 12536 00de E0E7     		b	.L776
+ 12537              	.LVL886:
+ 12538              	.L782:
+5114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12539              		.loc 1 5114 9 is_stmt 1 view .LVU4374
+ 12540 00e0 4021     		movs	r1, #64
+ 12541              	.LVL887:
+5114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12542              		.loc 1 5114 9 is_stmt 0 view .LVU4375
+ 12543 00e2 2046     		mov	r0, r4
+ 12544              	.LVL888:
+5114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       }
+ 12545              		.loc 1 5114 9 view .LVU4376
+ 12546 00e4 FFF7FEFF 		bl	I2C_ITError
+ 12547              	.LVL889:
+ 12548 00e8 DBE7     		b	.L776
+ 12549              	.LVL890:
+ 12550              	.L777:
+5118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12551              		.loc 1 5118 8 is_stmt 1 view .LVU4377
+5118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12552              		.loc 1 5118 11 is_stmt 0 view .LVU4378
+ 12553 00ea 11F0400F 		tst	r1, #64
+ 12554 00ee 1CD0     		beq	.L783
+5118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12555              		.loc 1 5118 60 discriminator 1 view .LVU4379
+ 12556 00f0 12F0400F 		tst	r2, #64
+ 12557 00f4 19D0     		beq	.L783
+5121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 12558              		.loc 1 5121 5 is_stmt 1 view .LVU4380
+5121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 12559              		.loc 1 5121 13 is_stmt 0 view .LVU4381
+ 12560 00f6 638D     		ldrh	r3, [r4, #42]
+ 12561 00f8 9BB2     		uxth	r3, r3
+5121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 12562              		.loc 1 5121 8 view .LVU4382
+ 12563 00fa 8BB9     		cbnz	r3, .L784
+5123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12564              		.loc 1 5123 7 is_stmt 1 view .LVU4383
+5123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12565              		.loc 1 5123 11 is_stmt 0 view .LVU4384
+ 12566 00fc 2368     		ldr	r3, [r4]
+ 12567 00fe 5A68     		ldr	r2, [r3, #4]
+ 12568              	.LVL891:
+5123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       {
+ 12569              		.loc 1 5123 10 view .LVU4385
+ 12570 0100 12F0007F 		tst	r2, #33554432
+ 12571 0104 CDD1     		bne	.L776
+ARM GAS  /tmp/ccbUHtu7.s 			page 415
+
+
+5126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12572              		.loc 1 5126 9 is_stmt 1 view .LVU4386
+5126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12573              		.loc 1 5126 17 is_stmt 0 view .LVU4387
+ 12574 0106 E26A     		ldr	r2, [r4, #44]
+5126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         {
+ 12575              		.loc 1 5126 12 view .LVU4388
+ 12576 0108 12F5803F 		cmn	r2, #65536
+ 12577 010c 04D1     		bne	.L785
+5129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12578              		.loc 1 5129 11 is_stmt 1 view .LVU4389
+5129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12579              		.loc 1 5129 25 is_stmt 0 view .LVU4390
+ 12580 010e 5A68     		ldr	r2, [r3, #4]
+5129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12581              		.loc 1 5129 31 view .LVU4391
+ 12582 0110 42F48042 		orr	r2, r2, #16384
+ 12583 0114 5A60     		str	r2, [r3, #4]
+ 12584 0116 C4E7     		b	.L776
+ 12585              	.L785:
+5134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12586              		.loc 1 5134 11 is_stmt 1 view .LVU4392
+ 12587 0118 2046     		mov	r0, r4
+ 12588              	.LVL892:
+5134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12589              		.loc 1 5134 11 is_stmt 0 view .LVU4393
+ 12590 011a FFF7FEFF 		bl	I2C_ITMasterSeqCplt
+ 12591              	.LVL893:
+5134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****         }
+ 12592              		.loc 1 5134 11 view .LVU4394
+ 12593 011e C0E7     		b	.L776
+ 12594              	.LVL894:
+ 12595              	.L784:
+5142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12596              		.loc 1 5142 7 is_stmt 1 view .LVU4395
+ 12597 0120 4021     		movs	r1, #64
+ 12598              	.LVL895:
+5142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12599              		.loc 1 5142 7 is_stmt 0 view .LVU4396
+ 12600 0122 2046     		mov	r0, r4
+ 12601              	.LVL896:
+5142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12602              		.loc 1 5142 7 view .LVU4397
+ 12603 0124 FFF7FEFF 		bl	I2C_ITError
+ 12604              	.LVL897:
+5142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12605              		.loc 1 5142 7 view .LVU4398
+ 12606 0128 BBE7     		b	.L776
+ 12607              	.LVL898:
+ 12608              	.L783:
+5145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 12609              		.loc 1 5145 8 is_stmt 1 view .LVU4399
+5145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 12610              		.loc 1 5145 11 is_stmt 0 view .LVU4400
+ 12611 012a 11F0200F 		tst	r1, #32
+ 12612 012e B8D0     		beq	.L776
+5145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ARM GAS  /tmp/ccbUHtu7.s 			page 416
+
+
+ 12613              		.loc 1 5145 63 discriminator 1 view .LVU4401
+ 12614 0130 12F0200F 		tst	r2, #32
+ 12615 0134 B5D0     		beq	.L776
+5149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12616              		.loc 1 5149 5 is_stmt 1 view .LVU4402
+ 12617 0136 2046     		mov	r0, r4
+ 12618              	.LVL899:
+5149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12619              		.loc 1 5149 5 is_stmt 0 view .LVU4403
+ 12620 0138 FFF7FEFF 		bl	I2C_ITMasterCplt
+ 12621              	.LVL900:
+5149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12622              		.loc 1 5149 5 view .LVU4404
+ 12623 013c B1E7     		b	.L776
+ 12624              	.LVL901:
+ 12625              	.L786:
+ 12626              	.LCFI136:
+ 12627              		.cfi_def_cfa_offset 0
+ 12628              		.cfi_restore 4
+ 12629              		.cfi_restore 14
+5037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12630              		.loc 1 5037 3 view .LVU4405
+ 12631 013e 0220     		movs	r0, #2
+ 12632              	.LVL902:
+5160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12633              		.loc 1 5160 1 view .LVU4406
+ 12634 0140 7047     		bx	lr
+ 12635              		.cfi_endproc
+ 12636              	.LFE380:
+ 12638              		.section	.text.I2C_DMAError,"ax",%progbits
+ 12639              		.align	1
+ 12640              		.syntax unified
+ 12641              		.thumb
+ 12642              		.thumb_func
+ 12644              	I2C_DMAError:
+ 12645              	.LVL903:
+ 12646              	.LFB397:
+6322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 12647              		.loc 1 6322 1 is_stmt 1 view -0
+ 12648              		.cfi_startproc
+ 12649              		@ args = 0, pretend = 0, frame = 0
+ 12650              		@ frame_needed = 0, uses_anonymous_args = 0
+6322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 12651              		.loc 1 6322 1 is_stmt 0 view .LVU4408
+ 12652 0000 08B5     		push	{r3, lr}
+ 12653              	.LCFI137:
+ 12654              		.cfi_def_cfa_offset 8
+ 12655              		.cfi_offset 3, -8
+ 12656              		.cfi_offset 14, -4
+6324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12657              		.loc 1 6324 3 is_stmt 1 view .LVU4409
+6324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12658              		.loc 1 6324 22 is_stmt 0 view .LVU4410
+ 12659 0002 806A     		ldr	r0, [r0, #40]
+ 12660              	.LVL904:
+6327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12661              		.loc 1 6327 3 is_stmt 1 view .LVU4411
+ARM GAS  /tmp/ccbUHtu7.s 			page 417
+
+
+6327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12662              		.loc 1 6327 7 is_stmt 0 view .LVU4412
+ 12663 0004 0268     		ldr	r2, [r0]
+6327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12664              		.loc 1 6327 17 view .LVU4413
+ 12665 0006 5368     		ldr	r3, [r2, #4]
+6327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12666              		.loc 1 6327 23 view .LVU4414
+ 12667 0008 43F40043 		orr	r3, r3, #32768
+ 12668 000c 5360     		str	r3, [r2, #4]
+6330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 12669              		.loc 1 6330 3 is_stmt 1 view .LVU4415
+ 12670 000e 1021     		movs	r1, #16
+ 12671 0010 FFF7FEFF 		bl	I2C_ITError
+ 12672              	.LVL905:
+6331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12673              		.loc 1 6331 1 is_stmt 0 view .LVU4416
+ 12674 0014 08BD     		pop	{r3, pc}
+ 12675              		.cfi_endproc
+ 12676              	.LFE397:
+ 12678              		.section	.text.I2C_DMAMasterTransmitCplt,"ax",%progbits
+ 12679              		.align	1
+ 12680              		.syntax unified
+ 12681              		.thumb
+ 12682              		.thumb_func
+ 12684              	I2C_DMAMasterTransmitCplt:
+ 12685              	.LVL906:
+ 12686              	.LFB393:
+6166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 12687              		.loc 1 6166 1 is_stmt 1 view -0
+ 12688              		.cfi_startproc
+ 12689              		@ args = 0, pretend = 0, frame = 0
+ 12690              		@ frame_needed = 0, uses_anonymous_args = 0
+6166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 12691              		.loc 1 6166 1 is_stmt 0 view .LVU4418
+ 12692 0000 10B5     		push	{r4, lr}
+ 12693              	.LCFI138:
+ 12694              		.cfi_def_cfa_offset 8
+ 12695              		.cfi_offset 4, -8
+ 12696              		.cfi_offset 14, -4
+6168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12697              		.loc 1 6168 3 is_stmt 1 view .LVU4419
+6168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12698              		.loc 1 6168 22 is_stmt 0 view .LVU4420
+ 12699 0002 846A     		ldr	r4, [r0, #40]
+ 12700              	.LVL907:
+6171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12701              		.loc 1 6171 3 is_stmt 1 view .LVU4421
+6171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12702              		.loc 1 6171 7 is_stmt 0 view .LVU4422
+ 12703 0004 2268     		ldr	r2, [r4]
+6171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12704              		.loc 1 6171 17 view .LVU4423
+ 12705 0006 1368     		ldr	r3, [r2]
+6171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12706              		.loc 1 6171 23 view .LVU4424
+ 12707 0008 23F48043 		bic	r3, r3, #16384
+ARM GAS  /tmp/ccbUHtu7.s 			page 418
+
+
+ 12708 000c 1360     		str	r3, [r2]
+6174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 12709              		.loc 1 6174 3 is_stmt 1 view .LVU4425
+6174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 12710              		.loc 1 6174 11 is_stmt 0 view .LVU4426
+ 12711 000e 638D     		ldrh	r3, [r4, #42]
+ 12712 0010 9BB2     		uxth	r3, r3
+6174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 12713              		.loc 1 6174 6 view .LVU4427
+ 12714 0012 ABB1     		cbz	r3, .L803
+6183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12715              		.loc 1 6183 5 is_stmt 1 view .LVU4428
+6183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12716              		.loc 1 6183 9 is_stmt 0 view .LVU4429
+ 12717 0014 616A     		ldr	r1, [r4, #36]
+6183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12718              		.loc 1 6183 27 view .LVU4430
+ 12719 0016 238D     		ldrh	r3, [r4, #40]
+6183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12720              		.loc 1 6183 20 view .LVU4431
+ 12721 0018 1944     		add	r1, r1, r3
+ 12722 001a 6162     		str	r1, [r4, #36]
+6186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 12723              		.loc 1 6186 5 is_stmt 1 view .LVU4432
+6186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 12724              		.loc 1 6186 13 is_stmt 0 view .LVU4433
+ 12725 001c 638D     		ldrh	r3, [r4, #42]
+ 12726 001e 9BB2     		uxth	r3, r3
+6186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 12727              		.loc 1 6186 8 view .LVU4434
+ 12728 0020 FF2B     		cmp	r3, #255
+ 12729 0022 12D9     		bls	.L799
+6188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12730              		.loc 1 6188 7 is_stmt 1 view .LVU4435
+6188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12731              		.loc 1 6188 22 is_stmt 0 view .LVU4436
+ 12732 0024 FF23     		movs	r3, #255
+ 12733 0026 2385     		strh	r3, [r4, #40]	@ movhi
+ 12734              	.L800:
+6196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 12735              		.loc 1 6196 5 is_stmt 1 view .LVU4437
+6196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 12736              		.loc 1 6196 81 is_stmt 0 view .LVU4438
+ 12737 0028 2268     		ldr	r2, [r4]
+6196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 12738              		.loc 1 6196 9 view .LVU4439
+ 12739 002a 238D     		ldrh	r3, [r4, #40]
+ 12740 002c 2832     		adds	r2, r2, #40
+ 12741 002e A06B     		ldr	r0, [r4, #56]
+ 12742              	.LVL908:
+6196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 12743              		.loc 1 6196 9 view .LVU4440
+ 12744 0030 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 12745              	.LVL909:
+6196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 12746              		.loc 1 6196 8 view .LVU4441
+ 12747 0034 60B1     		cbz	r0, .L801
+ARM GAS  /tmp/ccbUHtu7.s 			page 419
+
+
+6200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12748              		.loc 1 6200 7 is_stmt 1 view .LVU4442
+ 12749 0036 1021     		movs	r1, #16
+ 12750 0038 2046     		mov	r0, r4
+ 12751 003a FFF7FEFF 		bl	I2C_ITError
+ 12752              	.LVL910:
+ 12753              	.L796:
+6208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12754              		.loc 1 6208 1 is_stmt 0 view .LVU4443
+ 12755 003e 10BD     		pop	{r4, pc}
+ 12756              	.LVL911:
+ 12757              	.L803:
+6177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12758              		.loc 1 6177 5 is_stmt 1 view .LVU4444
+ 12759 0040 2021     		movs	r1, #32
+ 12760 0042 2046     		mov	r0, r4
+ 12761              	.LVL912:
+6177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12762              		.loc 1 6177 5 is_stmt 0 view .LVU4445
+ 12763 0044 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 12764              	.LVL913:
+ 12765 0048 F9E7     		b	.L796
+ 12766              	.LVL914:
+ 12767              	.L799:
+6192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12768              		.loc 1 6192 7 is_stmt 1 view .LVU4446
+6192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12769              		.loc 1 6192 28 is_stmt 0 view .LVU4447
+ 12770 004a 638D     		ldrh	r3, [r4, #42]
+6192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12771              		.loc 1 6192 22 view .LVU4448
+ 12772 004c 2385     		strh	r3, [r4, #40]	@ movhi
+ 12773 004e EBE7     		b	.L800
+ 12774              	.LVL915:
+ 12775              	.L801:
+6205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12776              		.loc 1 6205 7 is_stmt 1 view .LVU4449
+ 12777 0050 4021     		movs	r1, #64
+ 12778 0052 2046     		mov	r0, r4
+ 12779 0054 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 12780              	.LVL916:
+6208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12781              		.loc 1 6208 1 is_stmt 0 view .LVU4450
+ 12782 0058 F1E7     		b	.L796
+ 12783              		.cfi_endproc
+ 12784              	.LFE393:
+ 12786              		.section	.text.I2C_DMAMasterReceiveCplt,"ax",%progbits
+ 12787              		.align	1
+ 12788              		.syntax unified
+ 12789              		.thumb
+ 12790              		.thumb_func
+ 12792              	I2C_DMAMasterReceiveCplt:
+ 12793              	.LVL917:
+ 12794              	.LFB395:
+6244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 12795              		.loc 1 6244 1 is_stmt 1 view -0
+ 12796              		.cfi_startproc
+ARM GAS  /tmp/ccbUHtu7.s 			page 420
+
+
+ 12797              		@ args = 0, pretend = 0, frame = 0
+ 12798              		@ frame_needed = 0, uses_anonymous_args = 0
+6244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 12799              		.loc 1 6244 1 is_stmt 0 view .LVU4452
+ 12800 0000 10B5     		push	{r4, lr}
+ 12801              	.LCFI139:
+ 12802              		.cfi_def_cfa_offset 8
+ 12803              		.cfi_offset 4, -8
+ 12804              		.cfi_offset 14, -4
+6246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12805              		.loc 1 6246 3 is_stmt 1 view .LVU4453
+6246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12806              		.loc 1 6246 22 is_stmt 0 view .LVU4454
+ 12807 0002 846A     		ldr	r4, [r0, #40]
+ 12808              	.LVL918:
+6249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12809              		.loc 1 6249 3 is_stmt 1 view .LVU4455
+6249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12810              		.loc 1 6249 7 is_stmt 0 view .LVU4456
+ 12811 0004 2268     		ldr	r2, [r4]
+6249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12812              		.loc 1 6249 17 view .LVU4457
+ 12813 0006 1368     		ldr	r3, [r2]
+6249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12814              		.loc 1 6249 23 view .LVU4458
+ 12815 0008 23F40043 		bic	r3, r3, #32768
+ 12816 000c 1360     		str	r3, [r2]
+6252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 12817              		.loc 1 6252 3 is_stmt 1 view .LVU4459
+6252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 12818              		.loc 1 6252 11 is_stmt 0 view .LVU4460
+ 12819 000e 638D     		ldrh	r3, [r4, #42]
+ 12820 0010 9BB2     		uxth	r3, r3
+6252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 12821              		.loc 1 6252 6 view .LVU4461
+ 12822 0012 ABB1     		cbz	r3, .L811
+6261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12823              		.loc 1 6261 5 is_stmt 1 view .LVU4462
+6261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12824              		.loc 1 6261 9 is_stmt 0 view .LVU4463
+ 12825 0014 626A     		ldr	r2, [r4, #36]
+6261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12826              		.loc 1 6261 27 view .LVU4464
+ 12827 0016 238D     		ldrh	r3, [r4, #40]
+6261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12828              		.loc 1 6261 20 view .LVU4465
+ 12829 0018 1A44     		add	r2, r2, r3
+ 12830 001a 6262     		str	r2, [r4, #36]
+6264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 12831              		.loc 1 6264 5 is_stmt 1 view .LVU4466
+6264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 12832              		.loc 1 6264 13 is_stmt 0 view .LVU4467
+ 12833 001c 638D     		ldrh	r3, [r4, #42]
+ 12834 001e 9BB2     		uxth	r3, r3
+6264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     {
+ 12835              		.loc 1 6264 8 view .LVU4468
+ 12836 0020 FF2B     		cmp	r3, #255
+ARM GAS  /tmp/ccbUHtu7.s 			page 421
+
+
+ 12837 0022 12D9     		bls	.L807
+6266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12838              		.loc 1 6266 7 is_stmt 1 view .LVU4469
+6266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12839              		.loc 1 6266 22 is_stmt 0 view .LVU4470
+ 12840 0024 FF23     		movs	r3, #255
+ 12841 0026 2385     		strh	r3, [r4, #40]	@ movhi
+ 12842              	.L808:
+6274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 12843              		.loc 1 6274 5 is_stmt 1 view .LVU4471
+6274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 12844              		.loc 1 6274 55 is_stmt 0 view .LVU4472
+ 12845 0028 2168     		ldr	r1, [r4]
+6274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 12846              		.loc 1 6274 9 view .LVU4473
+ 12847 002a 238D     		ldrh	r3, [r4, #40]
+ 12848 002c 2431     		adds	r1, r1, #36
+ 12849 002e E06B     		ldr	r0, [r4, #60]
+ 12850              	.LVL919:
+6274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 12851              		.loc 1 6274 9 view .LVU4474
+ 12852 0030 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 12853              	.LVL920:
+6274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 12854              		.loc 1 6274 8 view .LVU4475
+ 12855 0034 60B1     		cbz	r0, .L809
+6278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12856              		.loc 1 6278 7 is_stmt 1 view .LVU4476
+ 12857 0036 1021     		movs	r1, #16
+ 12858 0038 2046     		mov	r0, r4
+ 12859 003a FFF7FEFF 		bl	I2C_ITError
+ 12860              	.LVL921:
+ 12861              	.L804:
+6286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12862              		.loc 1 6286 1 is_stmt 0 view .LVU4477
+ 12863 003e 10BD     		pop	{r4, pc}
+ 12864              	.LVL922:
+ 12865              	.L811:
+6255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12866              		.loc 1 6255 5 is_stmt 1 view .LVU4478
+ 12867 0040 2021     		movs	r1, #32
+ 12868 0042 2046     		mov	r0, r4
+ 12869              	.LVL923:
+6255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12870              		.loc 1 6255 5 is_stmt 0 view .LVU4479
+ 12871 0044 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 12872              	.LVL924:
+ 12873 0048 F9E7     		b	.L804
+ 12874              	.LVL925:
+ 12875              	.L807:
+6270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12876              		.loc 1 6270 7 is_stmt 1 view .LVU4480
+6270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12877              		.loc 1 6270 28 is_stmt 0 view .LVU4481
+ 12878 004a 638D     		ldrh	r3, [r4, #42]
+6270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12879              		.loc 1 6270 22 view .LVU4482
+ARM GAS  /tmp/ccbUHtu7.s 			page 422
+
+
+ 12880 004c 2385     		strh	r3, [r4, #40]	@ movhi
+ 12881 004e EBE7     		b	.L808
+ 12882              	.LVL926:
+ 12883              	.L809:
+6283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****     }
+ 12884              		.loc 1 6283 7 is_stmt 1 view .LVU4483
+ 12885 0050 4021     		movs	r1, #64
+ 12886 0052 2046     		mov	r0, r4
+ 12887 0054 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 12888              	.LVL927:
+6286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12889              		.loc 1 6286 1 is_stmt 0 view .LVU4484
+ 12890 0058 F1E7     		b	.L804
+ 12891              		.cfi_endproc
+ 12892              	.LFE395:
+ 12894              		.section	.text.HAL_I2C_ER_IRQHandler,"ax",%progbits
+ 12895              		.align	1
+ 12896              		.global	HAL_I2C_ER_IRQHandler
+ 12897              		.syntax unified
+ 12898              		.thumb
+ 12899              		.thumb_func
+ 12901              	HAL_I2C_ER_IRQHandler:
+ 12902              	.LVL928:
+ 12903              	.LFB364:
+4462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+ 12904              		.loc 1 4462 1 is_stmt 1 view -0
+ 12905              		.cfi_startproc
+ 12906              		@ args = 0, pretend = 0, frame = 0
+ 12907              		@ frame_needed = 0, uses_anonymous_args = 0
+4462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+ 12908              		.loc 1 4462 1 is_stmt 0 view .LVU4486
+ 12909 0000 10B5     		push	{r4, lr}
+ 12910              	.LCFI140:
+ 12911              		.cfi_def_cfa_offset 8
+ 12912              		.cfi_offset 4, -8
+ 12913              		.cfi_offset 14, -4
+4463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 12914              		.loc 1 4463 3 is_stmt 1 view .LVU4487
+4463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 12915              		.loc 1 4463 24 is_stmt 0 view .LVU4488
+ 12916 0002 0268     		ldr	r2, [r0]
+4463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 12917              		.loc 1 4463 12 view .LVU4489
+ 12918 0004 9369     		ldr	r3, [r2, #24]
+ 12919              	.LVL929:
+4464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmperror;
+ 12920              		.loc 1 4464 3 is_stmt 1 view .LVU4490
+4464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   uint32_t tmperror;
+ 12921              		.loc 1 4464 12 is_stmt 0 view .LVU4491
+ 12922 0006 1168     		ldr	r1, [r2]
+ 12923              	.LVL930:
+4465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12924              		.loc 1 4465 3 is_stmt 1 view .LVU4492
+4468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 12925              		.loc 1 4468 3 view .LVU4493
+4468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 12926              		.loc 1 4468 6 is_stmt 0 view .LVU4494
+ARM GAS  /tmp/ccbUHtu7.s 			page 423
+
+
+ 12927 0008 13F4807F 		tst	r3, #256
+ 12928 000c 09D0     		beq	.L813
+4468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 12929              		.loc 1 4468 57 discriminator 1 view .LVU4495
+ 12930 000e 11F0800F 		tst	r1, #128
+ 12931 0012 06D0     		beq	.L813
+4471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12932              		.loc 1 4471 5 is_stmt 1 view .LVU4496
+4471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12933              		.loc 1 4471 9 is_stmt 0 view .LVU4497
+ 12934 0014 446C     		ldr	r4, [r0, #68]
+4471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12935              		.loc 1 4471 21 view .LVU4498
+ 12936 0016 44F00104 		orr	r4, r4, #1
+ 12937 001a 4464     		str	r4, [r0, #68]
+4474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12938              		.loc 1 4474 5 is_stmt 1 view .LVU4499
+ 12939 001c 4FF48074 		mov	r4, #256
+ 12940 0020 D461     		str	r4, [r2, #28]
+ 12941              	.L813:
+4478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 12942              		.loc 1 4478 3 view .LVU4500
+4478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 12943              		.loc 1 4478 6 is_stmt 0 view .LVU4501
+ 12944 0022 13F4806F 		tst	r3, #1024
+ 12945 0026 0AD0     		beq	.L814
+4478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 12946              		.loc 1 4478 56 discriminator 1 view .LVU4502
+ 12947 0028 11F0800F 		tst	r1, #128
+ 12948 002c 07D0     		beq	.L814
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12949              		.loc 1 4481 5 is_stmt 1 view .LVU4503
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12950              		.loc 1 4481 9 is_stmt 0 view .LVU4504
+ 12951 002e 426C     		ldr	r2, [r0, #68]
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12952              		.loc 1 4481 21 view .LVU4505
+ 12953 0030 42F00802 		orr	r2, r2, #8
+ 12954 0034 4264     		str	r2, [r0, #68]
+4484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12955              		.loc 1 4484 5 is_stmt 1 view .LVU4506
+ 12956 0036 0268     		ldr	r2, [r0]
+ 12957 0038 4FF48064 		mov	r4, #1024
+ 12958 003c D461     		str	r4, [r2, #28]
+ 12959              	.L814:
+4488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 12960              		.loc 1 4488 3 view .LVU4507
+4488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 12961              		.loc 1 4488 6 is_stmt 0 view .LVU4508
+ 12962 003e 13F4007F 		tst	r3, #512
+ 12963 0042 0AD0     		beq	.L815
+4488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 12964              		.loc 1 4488 57 discriminator 1 view .LVU4509
+ 12965 0044 11F0800F 		tst	r1, #128
+ 12966 0048 07D0     		beq	.L815
+4491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12967              		.loc 1 4491 5 is_stmt 1 view .LVU4510
+ARM GAS  /tmp/ccbUHtu7.s 			page 424
+
+
+4491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12968              		.loc 1 4491 9 is_stmt 0 view .LVU4511
+ 12969 004a 436C     		ldr	r3, [r0, #68]
+ 12970              	.LVL931:
+4491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12971              		.loc 1 4491 21 view .LVU4512
+ 12972 004c 43F00203 		orr	r3, r3, #2
+ 12973 0050 4364     		str	r3, [r0, #68]
+4494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12974              		.loc 1 4494 5 is_stmt 1 view .LVU4513
+ 12975 0052 0368     		ldr	r3, [r0]
+ 12976 0054 4FF40072 		mov	r2, #512
+ 12977 0058 DA61     		str	r2, [r3, #28]
+ 12978              	.L815:
+4498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12979              		.loc 1 4498 3 view .LVU4514
+4498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12980              		.loc 1 4498 12 is_stmt 0 view .LVU4515
+ 12981 005a 416C     		ldr	r1, [r0, #68]
+ 12982              	.LVL932:
+4501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 12983              		.loc 1 4501 3 is_stmt 1 view .LVU4516
+4501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 12984              		.loc 1 4501 6 is_stmt 0 view .LVU4517
+ 12985 005c 11F00B0F 		tst	r1, #11
+ 12986 0060 00D1     		bne	.L818
+ 12987              	.LVL933:
+ 12988              	.L812:
+4505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12989              		.loc 1 4505 1 view .LVU4518
+ 12990 0062 10BD     		pop	{r4, pc}
+ 12991              	.LVL934:
+ 12992              	.L818:
+4503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 12993              		.loc 1 4503 5 is_stmt 1 view .LVU4519
+ 12994 0064 FFF7FEFF 		bl	I2C_ITError
+ 12995              	.LVL935:
+4505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 12996              		.loc 1 4505 1 is_stmt 0 view .LVU4520
+ 12997 0068 FBE7     		b	.L812
+ 12998              		.cfi_endproc
+ 12999              	.LFE364:
+ 13001              		.section	.text.I2C_DMAAbort,"ax",%progbits
+ 13002              		.align	1
+ 13003              		.syntax unified
+ 13004              		.thumb
+ 13005              		.thumb_func
+ 13007              	I2C_DMAAbort:
+ 13008              	.LVL936:
+ 13009              	.LFB398:
+6340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 13010              		.loc 1 6340 1 is_stmt 1 view -0
+ 13011              		.cfi_startproc
+ 13012              		@ args = 0, pretend = 0, frame = 0
+ 13013              		@ frame_needed = 0, uses_anonymous_args = 0
+6340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 13014              		.loc 1 6340 1 is_stmt 0 view .LVU4522
+ARM GAS  /tmp/ccbUHtu7.s 			page 425
+
+
+ 13015 0000 08B5     		push	{r3, lr}
+ 13016              	.LCFI141:
+ 13017              		.cfi_def_cfa_offset 8
+ 13018              		.cfi_offset 3, -8
+ 13019              		.cfi_offset 14, -4
+6342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 13020              		.loc 1 6342 3 is_stmt 1 view .LVU4523
+6342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 13021              		.loc 1 6342 22 is_stmt 0 view .LVU4524
+ 13022 0002 806A     		ldr	r0, [r0, #40]
+ 13023              	.LVL937:
+6345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 13024              		.loc 1 6345 3 is_stmt 1 view .LVU4525
+6345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 13025              		.loc 1 6345 11 is_stmt 0 view .LVU4526
+ 13026 0004 836B     		ldr	r3, [r0, #56]
+6345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 13027              		.loc 1 6345 6 view .LVU4527
+ 13028 0006 0BB1     		cbz	r3, .L820
+6347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 13029              		.loc 1 6347 5 is_stmt 1 view .LVU4528
+6347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 13030              		.loc 1 6347 37 is_stmt 0 view .LVU4529
+ 13031 0008 0022     		movs	r2, #0
+ 13032 000a 9A63     		str	r2, [r3, #56]
+ 13033              	.L820:
+6349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 13034              		.loc 1 6349 3 is_stmt 1 view .LVU4530
+6349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 13035              		.loc 1 6349 11 is_stmt 0 view .LVU4531
+ 13036 000c C36B     		ldr	r3, [r0, #60]
+6349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   {
+ 13037              		.loc 1 6349 6 view .LVU4532
+ 13038 000e 0BB1     		cbz	r3, .L821
+6351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 13039              		.loc 1 6351 5 is_stmt 1 view .LVU4533
+6351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   }
+ 13040              		.loc 1 6351 37 is_stmt 0 view .LVU4534
+ 13041 0010 0022     		movs	r2, #0
+ 13042 0012 9A63     		str	r2, [r3, #56]
+ 13043              	.L821:
+6354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 13044              		.loc 1 6354 3 is_stmt 1 view .LVU4535
+ 13045 0014 FFF7FEFF 		bl	I2C_TreatErrorCallback
+ 13046              	.LVL938:
+6355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 13047              		.loc 1 6355 1 is_stmt 0 view .LVU4536
+ 13048 0018 08BD     		pop	{r3, pc}
+ 13049              		.cfi_endproc
+ 13050              	.LFE398:
+ 13052              		.section	.text.HAL_I2C_GetState,"ax",%progbits
+ 13053              		.align	1
+ 13054              		.global	HAL_I2C_GetState
+ 13055              		.syntax unified
+ 13056              		.thumb
+ 13057              		.thumb_func
+ 13059              	HAL_I2C_GetState:
+ARM GAS  /tmp/ccbUHtu7.s 			page 426
+
+
+ 13060              	.LVL939:
+ 13061              	.LFB375:
+4696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   /* Return I2C handle state */
+ 13062              		.loc 1 4696 1 is_stmt 1 view -0
+ 13063              		.cfi_startproc
+ 13064              		@ args = 0, pretend = 0, frame = 0
+ 13065              		@ frame_needed = 0, uses_anonymous_args = 0
+ 13066              		@ link register save eliminated.
+4698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 13067              		.loc 1 4698 3 view .LVU4538
+4698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 13068              		.loc 1 4698 14 is_stmt 0 view .LVU4539
+ 13069 0000 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 13070              	.LVL940:
+4699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 13071              		.loc 1 4699 1 view .LVU4540
+ 13072 0004 7047     		bx	lr
+ 13073              		.cfi_endproc
+ 13074              	.LFE375:
+ 13076              		.section	.text.HAL_I2C_GetMode,"ax",%progbits
+ 13077              		.align	1
+ 13078              		.global	HAL_I2C_GetMode
+ 13079              		.syntax unified
+ 13080              		.thumb
+ 13081              		.thumb_func
+ 13083              	HAL_I2C_GetMode:
+ 13084              	.LVL941:
+ 13085              	.LFB376:
+4708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return hi2c->Mode;
+ 13086              		.loc 1 4708 1 is_stmt 1 view -0
+ 13087              		.cfi_startproc
+ 13088              		@ args = 0, pretend = 0, frame = 0
+ 13089              		@ frame_needed = 0, uses_anonymous_args = 0
+ 13090              		@ link register save eliminated.
+4709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 13091              		.loc 1 4709 3 view .LVU4542
+4709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 13092              		.loc 1 4709 14 is_stmt 0 view .LVU4543
+ 13093 0000 90F84200 		ldrb	r0, [r0, #66]	@ zero_extendqisi2
+ 13094              	.LVL942:
+4710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 13095              		.loc 1 4710 1 view .LVU4544
+ 13096 0004 7047     		bx	lr
+ 13097              		.cfi_endproc
+ 13098              	.LFE376:
+ 13100              		.section	.text.HAL_I2C_GetError,"ax",%progbits
+ 13101              		.align	1
+ 13102              		.global	HAL_I2C_GetError
+ 13103              		.syntax unified
+ 13104              		.thumb
+ 13105              		.thumb_func
+ 13107              	HAL_I2C_GetError:
+ 13108              	.LVL943:
+ 13109              	.LFB377:
+4719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c ****   return hi2c->ErrorCode;
+ 13110              		.loc 1 4719 1 is_stmt 1 view -0
+ 13111              		.cfi_startproc
+ARM GAS  /tmp/ccbUHtu7.s 			page 427
+
+
+ 13112              		@ args = 0, pretend = 0, frame = 0
+ 13113              		@ frame_needed = 0, uses_anonymous_args = 0
+ 13114              		@ link register save eliminated.
+4720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 13115              		.loc 1 4720 3 view .LVU4546
+4720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** }
+ 13116              		.loc 1 4720 14 is_stmt 0 view .LVU4547
+ 13117 0000 406C     		ldr	r0, [r0, #68]
+ 13118              	.LVL944:
+4721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c **** 
+ 13119              		.loc 1 4721 1 view .LVU4548
+ 13120 0002 7047     		bx	lr
+ 13121              		.cfi_endproc
+ 13122              	.LFE377:
+ 13124              		.text
+ 13125              	.Letext0:
+ 13126              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 13127              		.file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 13128              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 13129              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 13130              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 13131              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h"
+ 13132              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ARM GAS  /tmp/ccbUHtu7.s 			page 428
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_i2c.c
+     /tmp/ccbUHtu7.s:21     .text.I2C_Flush_TXDR:00000000 $t
+     /tmp/ccbUHtu7.s:26     .text.I2C_Flush_TXDR:00000000 I2C_Flush_TXDR
+     /tmp/ccbUHtu7.s:64     .text.I2C_TransferConfig:00000000 $t
+     /tmp/ccbUHtu7.s:69     .text.I2C_TransferConfig:00000000 I2C_TransferConfig
+     /tmp/ccbUHtu7.s:127    .text.I2C_Enable_IRQ:00000000 $t
+     /tmp/ccbUHtu7.s:132    .text.I2C_Enable_IRQ:00000000 I2C_Enable_IRQ
+     /tmp/ccbUHtu7.s:255    .text.I2C_Enable_IRQ:0000006c $d
+     /tmp/ccbUHtu7.s:12326  .text.I2C_Master_ISR_DMA:00000000 I2C_Master_ISR_DMA
+     /tmp/ccbUHtu7.s:12045  .text.I2C_Slave_ISR_DMA:00000000 I2C_Slave_ISR_DMA
+     /tmp/ccbUHtu7.s:261    .text.I2C_Disable_IRQ:00000000 $t
+     /tmp/ccbUHtu7.s:266    .text.I2C_Disable_IRQ:00000000 I2C_Disable_IRQ
+     /tmp/ccbUHtu7.s:390    .text.I2C_ConvertOtherXferOptions:00000000 $t
+     /tmp/ccbUHtu7.s:395    .text.I2C_ConvertOtherXferOptions:00000000 I2C_ConvertOtherXferOptions
+     /tmp/ccbUHtu7.s:436    .text.I2C_IsErrorOccurred:00000000 $t
+     /tmp/ccbUHtu7.s:441    .text.I2C_IsErrorOccurred:00000000 I2C_IsErrorOccurred
+     /tmp/ccbUHtu7.s:734    .text.I2C_WaitOnTXISFlagUntilTimeout:00000000 $t
+     /tmp/ccbUHtu7.s:739    .text.I2C_WaitOnTXISFlagUntilTimeout:00000000 I2C_WaitOnTXISFlagUntilTimeout
+     /tmp/ccbUHtu7.s:830    .text.I2C_WaitOnFlagUntilTimeout:00000000 $t
+     /tmp/ccbUHtu7.s:835    .text.I2C_WaitOnFlagUntilTimeout:00000000 I2C_WaitOnFlagUntilTimeout
+     /tmp/ccbUHtu7.s:921    .text.I2C_RequestMemoryWrite:00000000 $t
+     /tmp/ccbUHtu7.s:926    .text.I2C_RequestMemoryWrite:00000000 I2C_RequestMemoryWrite
+     /tmp/ccbUHtu7.s:1045   .text.I2C_RequestMemoryWrite:00000078 $d
+     /tmp/ccbUHtu7.s:1050   .text.I2C_RequestMemoryRead:00000000 $t
+     /tmp/ccbUHtu7.s:1055   .text.I2C_RequestMemoryRead:00000000 I2C_RequestMemoryRead
+     /tmp/ccbUHtu7.s:1174   .text.I2C_RequestMemoryRead:00000074 $d
+     /tmp/ccbUHtu7.s:1179   .text.I2C_WaitOnSTOPFlagUntilTimeout:00000000 $t
+     /tmp/ccbUHtu7.s:1184   .text.I2C_WaitOnSTOPFlagUntilTimeout:00000000 I2C_WaitOnSTOPFlagUntilTimeout
+     /tmp/ccbUHtu7.s:1271   .text.I2C_WaitOnRXNEFlagUntilTimeout:00000000 $t
+     /tmp/ccbUHtu7.s:1276   .text.I2C_WaitOnRXNEFlagUntilTimeout:00000000 I2C_WaitOnRXNEFlagUntilTimeout
+     /tmp/ccbUHtu7.s:1430   .text.HAL_I2C_MspInit:00000000 $t
+     /tmp/ccbUHtu7.s:1436   .text.HAL_I2C_MspInit:00000000 HAL_I2C_MspInit
+     /tmp/ccbUHtu7.s:1451   .text.HAL_I2C_Init:00000000 $t
+     /tmp/ccbUHtu7.s:1457   .text.HAL_I2C_Init:00000000 HAL_I2C_Init
+     /tmp/ccbUHtu7.s:1649   .text.HAL_I2C_MspDeInit:00000000 $t
+     /tmp/ccbUHtu7.s:1655   .text.HAL_I2C_MspDeInit:00000000 HAL_I2C_MspDeInit
+     /tmp/ccbUHtu7.s:1670   .text.HAL_I2C_DeInit:00000000 $t
+     /tmp/ccbUHtu7.s:1676   .text.HAL_I2C_DeInit:00000000 HAL_I2C_DeInit
+     /tmp/ccbUHtu7.s:1741   .text.HAL_I2C_Master_Transmit:00000000 $t
+     /tmp/ccbUHtu7.s:1747   .text.HAL_I2C_Master_Transmit:00000000 HAL_I2C_Master_Transmit
+     /tmp/ccbUHtu7.s:2057   .text.HAL_I2C_Master_Transmit:00000178 $d
+     /tmp/ccbUHtu7.s:2062   .text.HAL_I2C_Master_Receive:00000000 $t
+     /tmp/ccbUHtu7.s:2068   .text.HAL_I2C_Master_Receive:00000000 HAL_I2C_Master_Receive
+     /tmp/ccbUHtu7.s:2377   .text.HAL_I2C_Master_Receive:00000178 $d
+     /tmp/ccbUHtu7.s:2382   .text.HAL_I2C_Slave_Transmit:00000000 $t
+     /tmp/ccbUHtu7.s:2388   .text.HAL_I2C_Slave_Transmit:00000000 HAL_I2C_Slave_Transmit
+     /tmp/ccbUHtu7.s:2766   .text.HAL_I2C_Slave_Receive:00000000 $t
+     /tmp/ccbUHtu7.s:2772   .text.HAL_I2C_Slave_Receive:00000000 HAL_I2C_Slave_Receive
+     /tmp/ccbUHtu7.s:3120   .text.HAL_I2C_Master_Transmit_IT:00000000 $t
+     /tmp/ccbUHtu7.s:3126   .text.HAL_I2C_Master_Transmit_IT:00000000 HAL_I2C_Master_Transmit_IT
+     /tmp/ccbUHtu7.s:3279   .text.HAL_I2C_Master_Transmit_IT:0000008c $d
+     /tmp/ccbUHtu7.s:11665  .text.I2C_Master_ISR_IT:00000000 I2C_Master_ISR_IT
+     /tmp/ccbUHtu7.s:3286   .text.HAL_I2C_Master_Receive_IT:00000000 $t
+     /tmp/ccbUHtu7.s:3292   .text.HAL_I2C_Master_Receive_IT:00000000 HAL_I2C_Master_Receive_IT
+     /tmp/ccbUHtu7.s:3445   .text.HAL_I2C_Master_Receive_IT:0000008c $d
+     /tmp/ccbUHtu7.s:3452   .text.HAL_I2C_Slave_Transmit_IT:00000000 $t
+ARM GAS  /tmp/ccbUHtu7.s 			page 429
+
+
+     /tmp/ccbUHtu7.s:3458   .text.HAL_I2C_Slave_Transmit_IT:00000000 HAL_I2C_Slave_Transmit_IT
+     /tmp/ccbUHtu7.s:3561   .text.HAL_I2C_Slave_Transmit_IT:0000005c $d
+     /tmp/ccbUHtu7.s:11092  .text.I2C_Slave_ISR_IT:00000000 I2C_Slave_ISR_IT
+     /tmp/ccbUHtu7.s:3567   .text.HAL_I2C_Slave_Receive_IT:00000000 $t
+     /tmp/ccbUHtu7.s:3573   .text.HAL_I2C_Slave_Receive_IT:00000000 HAL_I2C_Slave_Receive_IT
+     /tmp/ccbUHtu7.s:3676   .text.HAL_I2C_Slave_Receive_IT:0000005c $d
+     /tmp/ccbUHtu7.s:3682   .text.HAL_I2C_Master_Transmit_DMA:00000000 $t
+     /tmp/ccbUHtu7.s:3688   .text.HAL_I2C_Master_Transmit_DMA:00000000 HAL_I2C_Master_Transmit_DMA
+     /tmp/ccbUHtu7.s:3990   .text.HAL_I2C_Master_Transmit_DMA:0000013c $d
+     /tmp/ccbUHtu7.s:12684  .text.I2C_DMAMasterTransmitCplt:00000000 I2C_DMAMasterTransmitCplt
+     /tmp/ccbUHtu7.s:12644  .text.I2C_DMAError:00000000 I2C_DMAError
+     /tmp/ccbUHtu7.s:4000   .text.HAL_I2C_Master_Receive_DMA:00000000 $t
+     /tmp/ccbUHtu7.s:4006   .text.HAL_I2C_Master_Receive_DMA:00000000 HAL_I2C_Master_Receive_DMA
+     /tmp/ccbUHtu7.s:4308   .text.HAL_I2C_Master_Receive_DMA:00000138 $d
+     /tmp/ccbUHtu7.s:12792  .text.I2C_DMAMasterReceiveCplt:00000000 I2C_DMAMasterReceiveCplt
+     /tmp/ccbUHtu7.s:4318   .text.HAL_I2C_Slave_Transmit_DMA:00000000 $t
+     /tmp/ccbUHtu7.s:4324   .text.HAL_I2C_Slave_Transmit_DMA:00000000 HAL_I2C_Slave_Transmit_DMA
+     /tmp/ccbUHtu7.s:4545   .text.HAL_I2C_Slave_Transmit_DMA:000000e0 $d
+     /tmp/ccbUHtu7.s:9921   .text.I2C_DMASlaveTransmitCplt:00000000 I2C_DMASlaveTransmitCplt
+     /tmp/ccbUHtu7.s:4553   .text.HAL_I2C_Slave_Receive_DMA:00000000 $t
+     /tmp/ccbUHtu7.s:4559   .text.HAL_I2C_Slave_Receive_DMA:00000000 HAL_I2C_Slave_Receive_DMA
+     /tmp/ccbUHtu7.s:4782   .text.HAL_I2C_Slave_Receive_DMA:000000e4 $d
+     /tmp/ccbUHtu7.s:9973   .text.I2C_DMASlaveReceiveCplt:00000000 I2C_DMASlaveReceiveCplt
+     /tmp/ccbUHtu7.s:4790   .text.HAL_I2C_Mem_Write:00000000 $t
+     /tmp/ccbUHtu7.s:4796   .text.HAL_I2C_Mem_Write:00000000 HAL_I2C_Mem_Write
+     /tmp/ccbUHtu7.s:5154   .text.HAL_I2C_Mem_Read:00000000 $t
+     /tmp/ccbUHtu7.s:5160   .text.HAL_I2C_Mem_Read:00000000 HAL_I2C_Mem_Read
+     /tmp/ccbUHtu7.s:5518   .text.HAL_I2C_Mem_Read:000001ac $d
+     /tmp/ccbUHtu7.s:5523   .text.HAL_I2C_Mem_Write_IT:00000000 $t
+     /tmp/ccbUHtu7.s:5529   .text.HAL_I2C_Mem_Write_IT:00000000 HAL_I2C_Mem_Write_IT
+     /tmp/ccbUHtu7.s:5738   .text.HAL_I2C_Mem_Write_IT:000000dc $d
+     /tmp/ccbUHtu7.s:5744   .text.HAL_I2C_Mem_Read_IT:00000000 $t
+     /tmp/ccbUHtu7.s:5750   .text.HAL_I2C_Mem_Read_IT:00000000 HAL_I2C_Mem_Read_IT
+     /tmp/ccbUHtu7.s:5960   .text.HAL_I2C_Mem_Read_IT:000000dc $d
+     /tmp/ccbUHtu7.s:5967   .text.HAL_I2C_Mem_Write_DMA:00000000 $t
+     /tmp/ccbUHtu7.s:5973   .text.HAL_I2C_Mem_Write_DMA:00000000 HAL_I2C_Mem_Write_DMA
+     /tmp/ccbUHtu7.s:6291   .text.HAL_I2C_Mem_Write_DMA:0000015c $d
+     /tmp/ccbUHtu7.s:6299   .text.HAL_I2C_Mem_Read_DMA:00000000 $t
+     /tmp/ccbUHtu7.s:6305   .text.HAL_I2C_Mem_Read_DMA:00000000 HAL_I2C_Mem_Read_DMA
+     /tmp/ccbUHtu7.s:6624   .text.HAL_I2C_Mem_Read_DMA:0000015c $d
+     /tmp/ccbUHtu7.s:6633   .text.HAL_I2C_IsDeviceReady:00000000 $t
+     /tmp/ccbUHtu7.s:6639   .text.HAL_I2C_IsDeviceReady:00000000 HAL_I2C_IsDeviceReady
+     /tmp/ccbUHtu7.s:6972   .text.HAL_I2C_Master_Seq_Transmit_IT:00000000 $t
+     /tmp/ccbUHtu7.s:6978   .text.HAL_I2C_Master_Seq_Transmit_IT:00000000 HAL_I2C_Master_Seq_Transmit_IT
+     /tmp/ccbUHtu7.s:7169   .text.HAL_I2C_Master_Seq_Transmit_IT:000000ac $d
+     /tmp/ccbUHtu7.s:7175   .text.HAL_I2C_Master_Seq_Transmit_DMA:00000000 $t
+     /tmp/ccbUHtu7.s:7181   .text.HAL_I2C_Master_Seq_Transmit_DMA:00000000 HAL_I2C_Master_Seq_Transmit_DMA
+     /tmp/ccbUHtu7.s:7514   .text.HAL_I2C_Master_Seq_Transmit_DMA:00000160 $d
+     /tmp/ccbUHtu7.s:7523   .text.HAL_I2C_Master_Seq_Receive_IT:00000000 $t
+     /tmp/ccbUHtu7.s:7529   .text.HAL_I2C_Master_Seq_Receive_IT:00000000 HAL_I2C_Master_Seq_Receive_IT
+     /tmp/ccbUHtu7.s:7720   .text.HAL_I2C_Master_Seq_Receive_IT:000000ac $d
+     /tmp/ccbUHtu7.s:7726   .text.HAL_I2C_Master_Seq_Receive_DMA:00000000 $t
+     /tmp/ccbUHtu7.s:7732   .text.HAL_I2C_Master_Seq_Receive_DMA:00000000 HAL_I2C_Master_Seq_Receive_DMA
+     /tmp/ccbUHtu7.s:8065   .text.HAL_I2C_Master_Seq_Receive_DMA:00000160 $d
+     /tmp/ccbUHtu7.s:8074   .text.HAL_I2C_Slave_Seq_Transmit_IT:00000000 $t
+     /tmp/ccbUHtu7.s:8080   .text.HAL_I2C_Slave_Seq_Transmit_IT:00000000 HAL_I2C_Slave_Seq_Transmit_IT
+     /tmp/ccbUHtu7.s:8281   .text.HAL_I2C_Slave_Seq_Transmit_IT:000000d0 $d
+ARM GAS  /tmp/ccbUHtu7.s 			page 430
+
+
+     /tmp/ccbUHtu7.s:13007  .text.I2C_DMAAbort:00000000 I2C_DMAAbort
+     /tmp/ccbUHtu7.s:8287   .text.HAL_I2C_Slave_Seq_Transmit_DMA:00000000 $t
+     /tmp/ccbUHtu7.s:8293   .text.HAL_I2C_Slave_Seq_Transmit_DMA:00000000 HAL_I2C_Slave_Seq_Transmit_DMA
+     /tmp/ccbUHtu7.s:8672   .text.HAL_I2C_Slave_Seq_Transmit_DMA:00000194 $d
+     /tmp/ccbUHtu7.s:8680   .text.HAL_I2C_Slave_Seq_Receive_IT:00000000 $t
+     /tmp/ccbUHtu7.s:8686   .text.HAL_I2C_Slave_Seq_Receive_IT:00000000 HAL_I2C_Slave_Seq_Receive_IT
+     /tmp/ccbUHtu7.s:8887   .text.HAL_I2C_Slave_Seq_Receive_IT:000000d0 $d
+     /tmp/ccbUHtu7.s:8893   .text.HAL_I2C_Slave_Seq_Receive_DMA:00000000 $t
+     /tmp/ccbUHtu7.s:8899   .text.HAL_I2C_Slave_Seq_Receive_DMA:00000000 HAL_I2C_Slave_Seq_Receive_DMA
+     /tmp/ccbUHtu7.s:9275   .text.HAL_I2C_Slave_Seq_Receive_DMA:00000190 $d
+     /tmp/ccbUHtu7.s:9283   .text.HAL_I2C_EnableListen_IT:00000000 $t
+     /tmp/ccbUHtu7.s:9289   .text.HAL_I2C_EnableListen_IT:00000000 HAL_I2C_EnableListen_IT
+     /tmp/ccbUHtu7.s:9336   .text.HAL_I2C_EnableListen_IT:00000028 $d
+     /tmp/ccbUHtu7.s:9341   .text.HAL_I2C_DisableListen_IT:00000000 $t
+     /tmp/ccbUHtu7.s:9347   .text.HAL_I2C_DisableListen_IT:00000000 HAL_I2C_DisableListen_IT
+     /tmp/ccbUHtu7.s:9413   .text.HAL_I2C_Master_Abort_IT:00000000 $t
+     /tmp/ccbUHtu7.s:9419   .text.HAL_I2C_Master_Abort_IT:00000000 HAL_I2C_Master_Abort_IT
+     /tmp/ccbUHtu7.s:9560   .text.HAL_I2C_Master_Abort_IT:00000080 $d
+     /tmp/ccbUHtu7.s:9565   .text.HAL_I2C_EV_IRQHandler:00000000 $t
+     /tmp/ccbUHtu7.s:9571   .text.HAL_I2C_EV_IRQHandler:00000000 HAL_I2C_EV_IRQHandler
+     /tmp/ccbUHtu7.s:9609   .text.HAL_I2C_MasterTxCpltCallback:00000000 $t
+     /tmp/ccbUHtu7.s:9615   .text.HAL_I2C_MasterTxCpltCallback:00000000 HAL_I2C_MasterTxCpltCallback
+     /tmp/ccbUHtu7.s:9630   .text.HAL_I2C_MasterRxCpltCallback:00000000 $t
+     /tmp/ccbUHtu7.s:9636   .text.HAL_I2C_MasterRxCpltCallback:00000000 HAL_I2C_MasterRxCpltCallback
+     /tmp/ccbUHtu7.s:9651   .text.I2C_ITMasterSeqCplt:00000000 $t
+     /tmp/ccbUHtu7.s:9656   .text.I2C_ITMasterSeqCplt:00000000 I2C_ITMasterSeqCplt
+     /tmp/ccbUHtu7.s:9741   .text.HAL_I2C_SlaveTxCpltCallback:00000000 $t
+     /tmp/ccbUHtu7.s:9747   .text.HAL_I2C_SlaveTxCpltCallback:00000000 HAL_I2C_SlaveTxCpltCallback
+     /tmp/ccbUHtu7.s:9762   .text.HAL_I2C_SlaveRxCpltCallback:00000000 $t
+     /tmp/ccbUHtu7.s:9768   .text.HAL_I2C_SlaveRxCpltCallback:00000000 HAL_I2C_SlaveRxCpltCallback
+     /tmp/ccbUHtu7.s:9783   .text.I2C_ITSlaveSeqCplt:00000000 $t
+     /tmp/ccbUHtu7.s:9788   .text.I2C_ITSlaveSeqCplt:00000000 I2C_ITSlaveSeqCplt
+     /tmp/ccbUHtu7.s:9916   .text.I2C_DMASlaveTransmitCplt:00000000 $t
+     /tmp/ccbUHtu7.s:9968   .text.I2C_DMASlaveReceiveCplt:00000000 $t
+     /tmp/ccbUHtu7.s:10029  .text.HAL_I2C_AddrCallback:00000000 $t
+     /tmp/ccbUHtu7.s:10035  .text.HAL_I2C_AddrCallback:00000000 HAL_I2C_AddrCallback
+     /tmp/ccbUHtu7.s:10052  .text.I2C_ITAddrCplt:00000000 $t
+     /tmp/ccbUHtu7.s:10057  .text.I2C_ITAddrCplt:00000000 I2C_ITAddrCplt
+     /tmp/ccbUHtu7.s:10217  .text.HAL_I2C_ListenCpltCallback:00000000 $t
+     /tmp/ccbUHtu7.s:10223  .text.HAL_I2C_ListenCpltCallback:00000000 HAL_I2C_ListenCpltCallback
+     /tmp/ccbUHtu7.s:10238  .text.I2C_ITListenCplt:00000000 $t
+     /tmp/ccbUHtu7.s:10243  .text.I2C_ITListenCplt:00000000 I2C_ITListenCplt
+     /tmp/ccbUHtu7.s:10347  .text.I2C_ITListenCplt:00000064 $d
+     /tmp/ccbUHtu7.s:10352  .text.HAL_I2C_MemTxCpltCallback:00000000 $t
+     /tmp/ccbUHtu7.s:10358  .text.HAL_I2C_MemTxCpltCallback:00000000 HAL_I2C_MemTxCpltCallback
+     /tmp/ccbUHtu7.s:10373  .text.HAL_I2C_MemRxCpltCallback:00000000 $t
+     /tmp/ccbUHtu7.s:10379  .text.HAL_I2C_MemRxCpltCallback:00000000 HAL_I2C_MemRxCpltCallback
+     /tmp/ccbUHtu7.s:10394  .text.HAL_I2C_ErrorCallback:00000000 $t
+     /tmp/ccbUHtu7.s:10400  .text.HAL_I2C_ErrorCallback:00000000 HAL_I2C_ErrorCallback
+     /tmp/ccbUHtu7.s:10415  .text.HAL_I2C_AbortCpltCallback:00000000 $t
+     /tmp/ccbUHtu7.s:10421  .text.HAL_I2C_AbortCpltCallback:00000000 HAL_I2C_AbortCpltCallback
+     /tmp/ccbUHtu7.s:10436  .text.I2C_TreatErrorCallback:00000000 $t
+     /tmp/ccbUHtu7.s:10441  .text.I2C_TreatErrorCallback:00000000 I2C_TreatErrorCallback
+     /tmp/ccbUHtu7.s:10498  .text.I2C_ITError:00000000 $t
+     /tmp/ccbUHtu7.s:10503  .text.I2C_ITError:00000000 I2C_ITError
+     /tmp/ccbUHtu7.s:10750  .text.I2C_ITError:000000fc $d
+     /tmp/ccbUHtu7.s:10757  .text.I2C_ITSlaveCplt:00000000 $t
+ARM GAS  /tmp/ccbUHtu7.s 			page 431
+
+
+     /tmp/ccbUHtu7.s:10762  .text.I2C_ITSlaveCplt:00000000 I2C_ITSlaveCplt
+     /tmp/ccbUHtu7.s:11082  .text.I2C_ITSlaveCplt:00000164 $d
+     /tmp/ccbUHtu7.s:11087  .text.I2C_Slave_ISR_IT:00000000 $t
+     /tmp/ccbUHtu7.s:11383  .text.I2C_ITMasterCplt:00000000 $t
+     /tmp/ccbUHtu7.s:11388  .text.I2C_ITMasterCplt:00000000 I2C_ITMasterCplt
+     /tmp/ccbUHtu7.s:11660  .text.I2C_Master_ISR_IT:00000000 $t
+     /tmp/ccbUHtu7.s:12040  .text.I2C_Slave_ISR_DMA:00000000 $t
+     /tmp/ccbUHtu7.s:12182  .text.I2C_Slave_ISR_DMA:0000008e $d
+     /tmp/ccbUHtu7.s:12193  .text.I2C_Slave_ISR_DMA:00000098 $t
+     /tmp/ccbUHtu7.s:12321  .text.I2C_Master_ISR_DMA:00000000 $t
+     /tmp/ccbUHtu7.s:12639  .text.I2C_DMAError:00000000 $t
+     /tmp/ccbUHtu7.s:12679  .text.I2C_DMAMasterTransmitCplt:00000000 $t
+     /tmp/ccbUHtu7.s:12787  .text.I2C_DMAMasterReceiveCplt:00000000 $t
+     /tmp/ccbUHtu7.s:12895  .text.HAL_I2C_ER_IRQHandler:00000000 $t
+     /tmp/ccbUHtu7.s:12901  .text.HAL_I2C_ER_IRQHandler:00000000 HAL_I2C_ER_IRQHandler
+     /tmp/ccbUHtu7.s:13002  .text.I2C_DMAAbort:00000000 $t
+     /tmp/ccbUHtu7.s:13053  .text.HAL_I2C_GetState:00000000 $t
+     /tmp/ccbUHtu7.s:13059  .text.HAL_I2C_GetState:00000000 HAL_I2C_GetState
+     /tmp/ccbUHtu7.s:13077  .text.HAL_I2C_GetMode:00000000 $t
+     /tmp/ccbUHtu7.s:13083  .text.HAL_I2C_GetMode:00000000 HAL_I2C_GetMode
+     /tmp/ccbUHtu7.s:13101  .text.HAL_I2C_GetError:00000000 $t
+     /tmp/ccbUHtu7.s:13107  .text.HAL_I2C_GetError:00000000 HAL_I2C_GetError
+
+UNDEFINED SYMBOLS
+HAL_GetTick
+HAL_DMA_Start_IT
+HAL_DMA_Abort_IT
+HAL_DMA_GetState
diff --git a/squeow_sw/build/stm32g4xx_hal_i2c.o b/squeow_sw/build/stm32g4xx_hal_i2c.o
new file mode 100644
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diff --git a/squeow_sw/build/stm32g4xx_hal_i2c_ex.d b/squeow_sw/build/stm32g4xx_hal_i2c_ex.d
new file mode 100644
index 0000000..d70e59c
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_i2c_ex.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_i2c_ex.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_i2c_ex.lst b/squeow_sw/build/stm32g4xx_hal_i2c_ex.lst
new file mode 100644
index 0000000..98763b7
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_i2c_ex.lst
@@ -0,0 +1,925 @@
+ARM GAS  /tmp/cc3umPGo.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_i2c_ex.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c"
+  20              		.section	.text.HAL_I2CEx_ConfigAnalogFilter,"ax",%progbits
+  21              		.align	1
+  22              		.global	HAL_I2CEx_ConfigAnalogFilter
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	HAL_I2CEx_ConfigAnalogFilter:
+  28              	.LVL0:
+  29              	.LFB329:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @file    stm32g4xx_hal_i2c_ex.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @brief   I2C Extended HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *          functionalities of I2C Extended peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *           + Filter Mode Functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *           + WakeUp Mode Functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *           + FastModePlus Functions
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   ******************************************************************************
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @attention
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * Copyright (c) 2019 STMicroelectronics.
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * All rights reserved.
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * in the root directory of this software component.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   ******************************************************************************
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   @verbatim
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   ==============================================================================
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****                ##### I2C peripheral Extended features  #####
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   ==============================================================================
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   [..] Comparing to other previous devices, the I2C interface for STM32G4xx
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****        devices contains the following additional features
+ARM GAS  /tmp/cc3umPGo.s 			page 2
+
+
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****        (+) Possibility to disable or enable Analog Noise Filter
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****        (+) Use of a configured Digital Noise Filter
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****        (+) Disable or enable wakeup from Stop mode(s)
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****        (+) Disable or enable Fast Mode Plus
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****                      ##### How to use this driver #####
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   ==============================================================================
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****           (++) HAL_I2CEx_EnableWakeUp()
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****           (++) HAL_I2CEx_DisableWakeUp()
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****           (++) HAL_I2CEx_EnableFastModePlus()
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****           (++) HAL_I2CEx_DisableFastModePlus()
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   @endverbatim
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /* Includes ------------------------------------------------------------------*/
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** #include "stm32g4xx_hal.h"
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @{
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /** @defgroup I2CEx I2CEx
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @brief I2C Extended HAL module driver
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @{
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** #ifdef HAL_I2C_MODULE_ENABLED
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /* Private typedef -----------------------------------------------------------*/
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /* Private define ------------------------------------------------------------*/
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /* Private macro -------------------------------------------------------------*/
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /* Private variables ---------------------------------------------------------*/
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /* Private function prototypes -----------------------------------------------*/
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /* Private functions ---------------------------------------------------------*/
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @{
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @brief    Filter Mode Functions
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** @verbatim
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****  ===============================================================================
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****                       ##### Filter Mode Functions #####
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****  ===============================================================================
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     [..] This section provides functions allowing to:
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****       (+) Configure Noise Filters
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** @endverbatim
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @{
+ARM GAS  /tmp/cc3umPGo.s 			page 3
+
+
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /**
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @brief  Configure I2C Analog noise filter.
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *                the configuration information for the specified I2Cx peripheral.
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @param  AnalogFilter New state of the Analog filter.
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @retval HAL status
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** {
+  30              		.loc 1 97 1 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		@ link register save eliminated.
+  35              		.loc 1 97 1 is_stmt 0 view .LVU1
+  36 0000 0346     		mov	r3, r0
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   /* Check the parameters */
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  37              		.loc 1 99 3 is_stmt 1 view .LVU2
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+  38              		.loc 1 100 3 view .LVU3
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+  39              		.loc 1 102 3 view .LVU4
+  40              		.loc 1 102 11 is_stmt 0 view .LVU5
+  41 0002 90F84120 		ldrb	r2, [r0, #65]	@ zero_extendqisi2
+  42 0006 D2B2     		uxtb	r2, r2
+  43              		.loc 1 102 6 view .LVU6
+  44 0008 202A     		cmp	r2, #32
+  45 000a 23D1     		bne	.L3
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   {
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Process Locked */
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_LOCK(hi2c);
+  46              		.loc 1 105 5 is_stmt 1 view .LVU7
+  47              		.loc 1 105 5 view .LVU8
+  48 000c 90F84020 		ldrb	r2, [r0, #64]	@ zero_extendqisi2
+  49 0010 012A     		cmp	r2, #1
+  50 0012 21D0     		beq	.L4
+  51              		.loc 1 105 5 discriminator 2 view .LVU9
+  52 0014 0122     		movs	r2, #1
+  53 0016 80F84020 		strb	r2, [r0, #64]
+  54              		.loc 1 105 5 discriminator 2 view .LVU10
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->State = HAL_I2C_STATE_BUSY;
+  55              		.loc 1 107 5 discriminator 2 view .LVU11
+  56              		.loc 1 107 17 is_stmt 0 discriminator 2 view .LVU12
+  57 001a 2422     		movs	r2, #36
+  58 001c 80F84120 		strb	r2, [r0, #65]
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Disable the selected I2C peripheral */
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_I2C_DISABLE(hi2c);
+  59              		.loc 1 110 5 is_stmt 1 discriminator 2 view .LVU13
+  60 0020 0068     		ldr	r0, [r0]
+  61              	.LVL1:
+  62              		.loc 1 110 5 is_stmt 0 discriminator 2 view .LVU14
+ARM GAS  /tmp/cc3umPGo.s 			page 4
+
+
+  63 0022 0268     		ldr	r2, [r0]
+  64 0024 22F00102 		bic	r2, r2, #1
+  65 0028 0260     		str	r2, [r0]
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Reset I2Cx ANOFF bit */
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+  66              		.loc 1 113 5 is_stmt 1 discriminator 2 view .LVU15
+  67              		.loc 1 113 9 is_stmt 0 discriminator 2 view .LVU16
+  68 002a 1868     		ldr	r0, [r3]
+  69              		.loc 1 113 19 discriminator 2 view .LVU17
+  70 002c 0268     		ldr	r2, [r0]
+  71              		.loc 1 113 25 discriminator 2 view .LVU18
+  72 002e 22F48052 		bic	r2, r2, #4096
+  73 0032 0260     		str	r2, [r0]
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Set analog filter bit*/
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->Instance->CR1 |= AnalogFilter;
+  74              		.loc 1 116 5 is_stmt 1 discriminator 2 view .LVU19
+  75              		.loc 1 116 9 is_stmt 0 discriminator 2 view .LVU20
+  76 0034 1868     		ldr	r0, [r3]
+  77              		.loc 1 116 19 discriminator 2 view .LVU21
+  78 0036 0268     		ldr	r2, [r0]
+  79              		.loc 1 116 25 discriminator 2 view .LVU22
+  80 0038 1143     		orrs	r1, r1, r2
+  81              	.LVL2:
+  82              		.loc 1 116 25 discriminator 2 view .LVU23
+  83 003a 0160     		str	r1, [r0]
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_I2C_ENABLE(hi2c);
+  84              		.loc 1 118 5 is_stmt 1 discriminator 2 view .LVU24
+  85 003c 1968     		ldr	r1, [r3]
+  86 003e 0A68     		ldr	r2, [r1]
+  87 0040 42F00102 		orr	r2, r2, #1
+  88 0044 0A60     		str	r2, [r1]
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->State = HAL_I2C_STATE_READY;
+  89              		.loc 1 120 5 discriminator 2 view .LVU25
+  90              		.loc 1 120 17 is_stmt 0 discriminator 2 view .LVU26
+  91 0046 2022     		movs	r2, #32
+  92 0048 83F84120 		strb	r2, [r3, #65]
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Process Unlocked */
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_UNLOCK(hi2c);
+  93              		.loc 1 123 5 is_stmt 1 discriminator 2 view .LVU27
+  94              		.loc 1 123 5 discriminator 2 view .LVU28
+  95 004c 0020     		movs	r0, #0
+  96 004e 83F84000 		strb	r0, [r3, #64]
+  97              		.loc 1 123 5 discriminator 2 view .LVU29
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     return HAL_OK;
+  98              		.loc 1 125 5 discriminator 2 view .LVU30
+  99              		.loc 1 125 12 is_stmt 0 discriminator 2 view .LVU31
+ 100 0052 7047     		bx	lr
+ 101              	.LVL3:
+ 102              	.L3:
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   }
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   else
+ARM GAS  /tmp/cc3umPGo.s 			page 5
+
+
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   {
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     return HAL_BUSY;
+ 103              		.loc 1 129 12 view .LVU32
+ 104 0054 0220     		movs	r0, #2
+ 105              	.LVL4:
+ 106              		.loc 1 129 12 view .LVU33
+ 107 0056 7047     		bx	lr
+ 108              	.LVL5:
+ 109              	.L4:
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 110              		.loc 1 105 5 view .LVU34
+ 111 0058 0220     		movs	r0, #2
+ 112              	.LVL6:
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   }
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** }
+ 113              		.loc 1 131 1 view .LVU35
+ 114 005a 7047     		bx	lr
+ 115              		.cfi_endproc
+ 116              	.LFE329:
+ 118              		.section	.text.HAL_I2CEx_ConfigDigitalFilter,"ax",%progbits
+ 119              		.align	1
+ 120              		.global	HAL_I2CEx_ConfigDigitalFilter
+ 121              		.syntax unified
+ 122              		.thumb
+ 123              		.thumb_func
+ 125              	HAL_I2CEx_ConfigDigitalFilter:
+ 126              	.LVL7:
+ 127              	.LFB330:
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /**
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @brief  Configure I2C Digital noise filter.
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *                the configuration information for the specified I2Cx peripheral.
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @retval HAL status
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** {
+ 128              		.loc 1 141 1 is_stmt 1 view -0
+ 129              		.cfi_startproc
+ 130              		@ args = 0, pretend = 0, frame = 0
+ 131              		@ frame_needed = 0, uses_anonymous_args = 0
+ 132              		@ link register save eliminated.
+ 133              		.loc 1 141 1 is_stmt 0 view .LVU37
+ 134 0000 0346     		mov	r3, r0
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   uint32_t tmpreg;
+ 135              		.loc 1 142 3 is_stmt 1 view .LVU38
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   /* Check the parameters */
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ 136              		.loc 1 145 3 view .LVU39
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+ 137              		.loc 1 146 3 view .LVU40
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 138              		.loc 1 148 3 view .LVU41
+ 139              		.loc 1 148 11 is_stmt 0 view .LVU42
+ARM GAS  /tmp/cc3umPGo.s 			page 6
+
+
+ 140 0002 90F84120 		ldrb	r2, [r0, #65]	@ zero_extendqisi2
+ 141 0006 D2B2     		uxtb	r2, r2
+ 142              		.loc 1 148 6 view .LVU43
+ 143 0008 202A     		cmp	r2, #32
+ 144 000a 21D1     		bne	.L7
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   {
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Process Locked */
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_LOCK(hi2c);
+ 145              		.loc 1 151 5 is_stmt 1 view .LVU44
+ 146              		.loc 1 151 5 view .LVU45
+ 147 000c 90F84020 		ldrb	r2, [r0, #64]	@ zero_extendqisi2
+ 148 0010 012A     		cmp	r2, #1
+ 149 0012 1FD0     		beq	.L8
+ 150              		.loc 1 151 5 discriminator 2 view .LVU46
+ 151 0014 0122     		movs	r2, #1
+ 152 0016 80F84020 		strb	r2, [r0, #64]
+ 153              		.loc 1 151 5 discriminator 2 view .LVU47
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->State = HAL_I2C_STATE_BUSY;
+ 154              		.loc 1 153 5 discriminator 2 view .LVU48
+ 155              		.loc 1 153 17 is_stmt 0 discriminator 2 view .LVU49
+ 156 001a 2422     		movs	r2, #36
+ 157 001c 80F84120 		strb	r2, [r0, #65]
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Disable the selected I2C peripheral */
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_I2C_DISABLE(hi2c);
+ 158              		.loc 1 156 5 is_stmt 1 discriminator 2 view .LVU50
+ 159 0020 0068     		ldr	r0, [r0]
+ 160              	.LVL8:
+ 161              		.loc 1 156 5 is_stmt 0 discriminator 2 view .LVU51
+ 162 0022 0268     		ldr	r2, [r0]
+ 163 0024 22F00102 		bic	r2, r2, #1
+ 164 0028 0260     		str	r2, [r0]
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Get the old register value */
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     tmpreg = hi2c->Instance->CR1;
+ 165              		.loc 1 159 5 is_stmt 1 discriminator 2 view .LVU52
+ 166              		.loc 1 159 18 is_stmt 0 discriminator 2 view .LVU53
+ 167 002a 1868     		ldr	r0, [r3]
+ 168              		.loc 1 159 12 discriminator 2 view .LVU54
+ 169 002c 0268     		ldr	r2, [r0]
+ 170              	.LVL9:
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Reset I2Cx DNF bits [11:8] */
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     tmpreg &= ~(I2C_CR1_DNF);
+ 171              		.loc 1 162 5 is_stmt 1 discriminator 2 view .LVU55
+ 172              		.loc 1 162 12 is_stmt 0 discriminator 2 view .LVU56
+ 173 002e 22F47062 		bic	r2, r2, #3840
+ 174              	.LVL10:
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Set I2Cx DNF coefficient */
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     tmpreg |= DigitalFilter << 8U;
+ 175              		.loc 1 165 5 is_stmt 1 discriminator 2 view .LVU57
+ 176              		.loc 1 165 12 is_stmt 0 discriminator 2 view .LVU58
+ 177 0032 42EA0122 		orr	r2, r2, r1, lsl #8
+ 178              	.LVL11:
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ARM GAS  /tmp/cc3umPGo.s 			page 7
+
+
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Store the new register value */
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->Instance->CR1 = tmpreg;
+ 179              		.loc 1 168 5 is_stmt 1 discriminator 2 view .LVU59
+ 180              		.loc 1 168 25 is_stmt 0 discriminator 2 view .LVU60
+ 181 0036 0260     		str	r2, [r0]
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_I2C_ENABLE(hi2c);
+ 182              		.loc 1 170 5 is_stmt 1 discriminator 2 view .LVU61
+ 183 0038 1968     		ldr	r1, [r3]
+ 184              	.LVL12:
+ 185              		.loc 1 170 5 is_stmt 0 discriminator 2 view .LVU62
+ 186 003a 0A68     		ldr	r2, [r1]
+ 187              	.LVL13:
+ 188              		.loc 1 170 5 discriminator 2 view .LVU63
+ 189 003c 42F00102 		orr	r2, r2, #1
+ 190 0040 0A60     		str	r2, [r1]
+ 191              	.LVL14:
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 192              		.loc 1 172 5 is_stmt 1 discriminator 2 view .LVU64
+ 193              		.loc 1 172 17 is_stmt 0 discriminator 2 view .LVU65
+ 194 0042 2022     		movs	r2, #32
+ 195 0044 83F84120 		strb	r2, [r3, #65]
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Process Unlocked */
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_UNLOCK(hi2c);
+ 196              		.loc 1 175 5 is_stmt 1 discriminator 2 view .LVU66
+ 197              		.loc 1 175 5 discriminator 2 view .LVU67
+ 198 0048 0020     		movs	r0, #0
+ 199 004a 83F84000 		strb	r0, [r3, #64]
+ 200              		.loc 1 175 5 discriminator 2 view .LVU68
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     return HAL_OK;
+ 201              		.loc 1 177 5 discriminator 2 view .LVU69
+ 202              		.loc 1 177 12 is_stmt 0 discriminator 2 view .LVU70
+ 203 004e 7047     		bx	lr
+ 204              	.LVL15:
+ 205              	.L7:
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   }
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   else
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   {
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     return HAL_BUSY;
+ 206              		.loc 1 181 12 view .LVU71
+ 207 0050 0220     		movs	r0, #2
+ 208              	.LVL16:
+ 209              		.loc 1 181 12 view .LVU72
+ 210 0052 7047     		bx	lr
+ 211              	.LVL17:
+ 212              	.L8:
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 213              		.loc 1 151 5 view .LVU73
+ 214 0054 0220     		movs	r0, #2
+ 215              	.LVL18:
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   }
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** }
+ 216              		.loc 1 183 1 view .LVU74
+ 217 0056 7047     		bx	lr
+ARM GAS  /tmp/cc3umPGo.s 			page 8
+
+
+ 218              		.cfi_endproc
+ 219              	.LFE330:
+ 221              		.section	.text.HAL_I2CEx_EnableWakeUp,"ax",%progbits
+ 222              		.align	1
+ 223              		.global	HAL_I2CEx_EnableWakeUp
+ 224              		.syntax unified
+ 225              		.thumb
+ 226              		.thumb_func
+ 228              	HAL_I2CEx_EnableWakeUp:
+ 229              	.LVL19:
+ 230              	.LFB331:
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /**
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @}
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @brief    WakeUp Mode Functions
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** @verbatim
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****  ===============================================================================
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****                       ##### WakeUp Mode Functions #####
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****  ===============================================================================
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     [..] This section provides functions allowing to:
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****       (+) Configure Wake Up Feature
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** @endverbatim
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @{
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /**
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @brief  Enable I2C wakeup from Stop mode(s).
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *                the configuration information for the specified I2Cx peripheral.
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @retval HAL status
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** {
+ 231              		.loc 1 209 1 is_stmt 1 view -0
+ 232              		.cfi_startproc
+ 233              		@ args = 0, pretend = 0, frame = 0
+ 234              		@ frame_needed = 0, uses_anonymous_args = 0
+ 235              		@ link register save eliminated.
+ 236              		.loc 1 209 1 is_stmt 0 view .LVU76
+ 237 0000 0346     		mov	r3, r0
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   /* Check the parameters */
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+ 238              		.loc 1 211 3 is_stmt 1 view .LVU77
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 239              		.loc 1 213 3 view .LVU78
+ 240              		.loc 1 213 11 is_stmt 0 view .LVU79
+ 241 0002 90F84120 		ldrb	r2, [r0, #65]	@ zero_extendqisi2
+ 242 0006 D2B2     		uxtb	r2, r2
+ 243              		.loc 1 213 6 view .LVU80
+ 244 0008 202A     		cmp	r2, #32
+ 245 000a 1FD1     		bne	.L11
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   {
+ARM GAS  /tmp/cc3umPGo.s 			page 9
+
+
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Process Locked */
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_LOCK(hi2c);
+ 246              		.loc 1 216 5 is_stmt 1 view .LVU81
+ 247              		.loc 1 216 5 view .LVU82
+ 248 000c 90F84020 		ldrb	r2, [r0, #64]	@ zero_extendqisi2
+ 249 0010 012A     		cmp	r2, #1
+ 250 0012 1DD0     		beq	.L12
+ 251              		.loc 1 216 5 discriminator 2 view .LVU83
+ 252 0014 0122     		movs	r2, #1
+ 253 0016 80F84020 		strb	r2, [r0, #64]
+ 254              		.loc 1 216 5 discriminator 2 view .LVU84
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->State = HAL_I2C_STATE_BUSY;
+ 255              		.loc 1 218 5 discriminator 2 view .LVU85
+ 256              		.loc 1 218 17 is_stmt 0 discriminator 2 view .LVU86
+ 257 001a 2422     		movs	r2, #36
+ 258 001c 80F84120 		strb	r2, [r0, #65]
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Disable the selected I2C peripheral */
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_I2C_DISABLE(hi2c);
+ 259              		.loc 1 221 5 is_stmt 1 discriminator 2 view .LVU87
+ 260 0020 0168     		ldr	r1, [r0]
+ 261 0022 0A68     		ldr	r2, [r1]
+ 262 0024 22F00102 		bic	r2, r2, #1
+ 263 0028 0A60     		str	r2, [r1]
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Enable wakeup from stop mode */
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+ 264              		.loc 1 224 5 discriminator 2 view .LVU88
+ 265              		.loc 1 224 9 is_stmt 0 discriminator 2 view .LVU89
+ 266 002a 0168     		ldr	r1, [r0]
+ 267              		.loc 1 224 19 discriminator 2 view .LVU90
+ 268 002c 0A68     		ldr	r2, [r1]
+ 269              		.loc 1 224 25 discriminator 2 view .LVU91
+ 270 002e 42F48022 		orr	r2, r2, #262144
+ 271 0032 0A60     		str	r2, [r1]
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_I2C_ENABLE(hi2c);
+ 272              		.loc 1 226 5 is_stmt 1 discriminator 2 view .LVU92
+ 273 0034 0168     		ldr	r1, [r0]
+ 274 0036 0A68     		ldr	r2, [r1]
+ 275 0038 42F00102 		orr	r2, r2, #1
+ 276 003c 0A60     		str	r2, [r1]
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 277              		.loc 1 228 5 discriminator 2 view .LVU93
+ 278              		.loc 1 228 17 is_stmt 0 discriminator 2 view .LVU94
+ 279 003e 2022     		movs	r2, #32
+ 280 0040 80F84120 		strb	r2, [r0, #65]
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Process Unlocked */
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_UNLOCK(hi2c);
+ 281              		.loc 1 231 5 is_stmt 1 discriminator 2 view .LVU95
+ 282              		.loc 1 231 5 discriminator 2 view .LVU96
+ 283 0044 0020     		movs	r0, #0
+ 284              	.LVL20:
+ 285              		.loc 1 231 5 is_stmt 0 discriminator 2 view .LVU97
+ARM GAS  /tmp/cc3umPGo.s 			page 10
+
+
+ 286 0046 83F84000 		strb	r0, [r3, #64]
+ 287              		.loc 1 231 5 is_stmt 1 discriminator 2 view .LVU98
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     return HAL_OK;
+ 288              		.loc 1 233 5 discriminator 2 view .LVU99
+ 289              		.loc 1 233 12 is_stmt 0 discriminator 2 view .LVU100
+ 290 004a 7047     		bx	lr
+ 291              	.LVL21:
+ 292              	.L11:
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   }
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   else
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   {
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     return HAL_BUSY;
+ 293              		.loc 1 237 12 view .LVU101
+ 294 004c 0220     		movs	r0, #2
+ 295              	.LVL22:
+ 296              		.loc 1 237 12 view .LVU102
+ 297 004e 7047     		bx	lr
+ 298              	.LVL23:
+ 299              	.L12:
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 300              		.loc 1 216 5 view .LVU103
+ 301 0050 0220     		movs	r0, #2
+ 302              	.LVL24:
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   }
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** }
+ 303              		.loc 1 239 1 view .LVU104
+ 304 0052 7047     		bx	lr
+ 305              		.cfi_endproc
+ 306              	.LFE331:
+ 308              		.section	.text.HAL_I2CEx_DisableWakeUp,"ax",%progbits
+ 309              		.align	1
+ 310              		.global	HAL_I2CEx_DisableWakeUp
+ 311              		.syntax unified
+ 312              		.thumb
+ 313              		.thumb_func
+ 315              	HAL_I2CEx_DisableWakeUp:
+ 316              	.LVL25:
+ 317              	.LFB332:
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /**
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @brief  Disable I2C wakeup from Stop mode(s).
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *                the configuration information for the specified I2Cx peripheral.
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @retval HAL status
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** {
+ 318              		.loc 1 248 1 is_stmt 1 view -0
+ 319              		.cfi_startproc
+ 320              		@ args = 0, pretend = 0, frame = 0
+ 321              		@ frame_needed = 0, uses_anonymous_args = 0
+ 322              		@ link register save eliminated.
+ 323              		.loc 1 248 1 is_stmt 0 view .LVU106
+ 324 0000 0346     		mov	r3, r0
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   /* Check the parameters */
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+ARM GAS  /tmp/cc3umPGo.s 			page 11
+
+
+ 325              		.loc 1 250 3 is_stmt 1 view .LVU107
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 326              		.loc 1 252 3 view .LVU108
+ 327              		.loc 1 252 11 is_stmt 0 view .LVU109
+ 328 0002 90F84120 		ldrb	r2, [r0, #65]	@ zero_extendqisi2
+ 329 0006 D2B2     		uxtb	r2, r2
+ 330              		.loc 1 252 6 view .LVU110
+ 331 0008 202A     		cmp	r2, #32
+ 332 000a 1FD1     		bne	.L15
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   {
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Process Locked */
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_LOCK(hi2c);
+ 333              		.loc 1 255 5 is_stmt 1 view .LVU111
+ 334              		.loc 1 255 5 view .LVU112
+ 335 000c 90F84020 		ldrb	r2, [r0, #64]	@ zero_extendqisi2
+ 336 0010 012A     		cmp	r2, #1
+ 337 0012 1DD0     		beq	.L16
+ 338              		.loc 1 255 5 discriminator 2 view .LVU113
+ 339 0014 0122     		movs	r2, #1
+ 340 0016 80F84020 		strb	r2, [r0, #64]
+ 341              		.loc 1 255 5 discriminator 2 view .LVU114
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->State = HAL_I2C_STATE_BUSY;
+ 342              		.loc 1 257 5 discriminator 2 view .LVU115
+ 343              		.loc 1 257 17 is_stmt 0 discriminator 2 view .LVU116
+ 344 001a 2422     		movs	r2, #36
+ 345 001c 80F84120 		strb	r2, [r0, #65]
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Disable the selected I2C peripheral */
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_I2C_DISABLE(hi2c);
+ 346              		.loc 1 260 5 is_stmt 1 discriminator 2 view .LVU117
+ 347 0020 0168     		ldr	r1, [r0]
+ 348 0022 0A68     		ldr	r2, [r1]
+ 349 0024 22F00102 		bic	r2, r2, #1
+ 350 0028 0A60     		str	r2, [r1]
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Enable wakeup from stop mode */
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+ 351              		.loc 1 263 5 discriminator 2 view .LVU118
+ 352              		.loc 1 263 9 is_stmt 0 discriminator 2 view .LVU119
+ 353 002a 0168     		ldr	r1, [r0]
+ 354              		.loc 1 263 19 discriminator 2 view .LVU120
+ 355 002c 0A68     		ldr	r2, [r1]
+ 356              		.loc 1 263 25 discriminator 2 view .LVU121
+ 357 002e 22F48022 		bic	r2, r2, #262144
+ 358 0032 0A60     		str	r2, [r1]
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_I2C_ENABLE(hi2c);
+ 359              		.loc 1 265 5 is_stmt 1 discriminator 2 view .LVU122
+ 360 0034 0168     		ldr	r1, [r0]
+ 361 0036 0A68     		ldr	r2, [r1]
+ 362 0038 42F00102 		orr	r2, r2, #1
+ 363 003c 0A60     		str	r2, [r1]
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 364              		.loc 1 267 5 discriminator 2 view .LVU123
+ARM GAS  /tmp/cc3umPGo.s 			page 12
+
+
+ 365              		.loc 1 267 17 is_stmt 0 discriminator 2 view .LVU124
+ 366 003e 2022     		movs	r2, #32
+ 367 0040 80F84120 		strb	r2, [r0, #65]
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     /* Process Unlocked */
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     __HAL_UNLOCK(hi2c);
+ 368              		.loc 1 270 5 is_stmt 1 discriminator 2 view .LVU125
+ 369              		.loc 1 270 5 discriminator 2 view .LVU126
+ 370 0044 0020     		movs	r0, #0
+ 371              	.LVL26:
+ 372              		.loc 1 270 5 is_stmt 0 discriminator 2 view .LVU127
+ 373 0046 83F84000 		strb	r0, [r3, #64]
+ 374              		.loc 1 270 5 is_stmt 1 discriminator 2 view .LVU128
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     return HAL_OK;
+ 375              		.loc 1 272 5 discriminator 2 view .LVU129
+ 376              		.loc 1 272 12 is_stmt 0 discriminator 2 view .LVU130
+ 377 004a 7047     		bx	lr
+ 378              	.LVL27:
+ 379              	.L15:
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   }
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   else
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   {
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     return HAL_BUSY;
+ 380              		.loc 1 276 12 view .LVU131
+ 381 004c 0220     		movs	r0, #2
+ 382              	.LVL28:
+ 383              		.loc 1 276 12 view .LVU132
+ 384 004e 7047     		bx	lr
+ 385              	.LVL29:
+ 386              	.L16:
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 387              		.loc 1 255 5 view .LVU133
+ 388 0050 0220     		movs	r0, #2
+ 389              	.LVL30:
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   }
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** }
+ 390              		.loc 1 278 1 view .LVU134
+ 391 0052 7047     		bx	lr
+ 392              		.cfi_endproc
+ 393              	.LFE332:
+ 395              		.section	.text.HAL_I2CEx_EnableFastModePlus,"ax",%progbits
+ 396              		.align	1
+ 397              		.global	HAL_I2CEx_EnableFastModePlus
+ 398              		.syntax unified
+ 399              		.thumb
+ 400              		.thumb_func
+ 402              	HAL_I2CEx_EnableFastModePlus:
+ 403              	.LVL31:
+ 404              	.LFB333:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /**
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @}
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @brief    Fast Mode Plus Functions
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *
+ARM GAS  /tmp/cc3umPGo.s 			page 13
+
+
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** @verbatim
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****  ===============================================================================
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****                       ##### Fast Mode Plus Functions #####
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****  ===============================================================================
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****     [..] This section provides functions allowing to:
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****       (+) Configure Fast Mode Plus
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** @endverbatim
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @{
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /**
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @brief Enable the I2C fast mode plus driving capability.
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @param ConfigFastModePlus Selects the pin.
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *   This parameter can be one of the @ref I2CEx_FastModePlus values
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *        on each one of the following pins PB6, PB7, PB8 and PB9.
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @note  For all I2C4 pins fast mode plus driving capability can be enabled
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @retval None
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** {
+ 405              		.loc 1 315 1 is_stmt 1 view -0
+ 406              		.cfi_startproc
+ 407              		@ args = 0, pretend = 0, frame = 8
+ 408              		@ frame_needed = 0, uses_anonymous_args = 0
+ 409              		@ link register save eliminated.
+ 410              		.loc 1 315 1 is_stmt 0 view .LVU136
+ 411 0000 82B0     		sub	sp, sp, #8
+ 412              	.LCFI0:
+ 413              		.cfi_def_cfa_offset 8
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   /* Check the parameter */
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+ 414              		.loc 1 317 3 is_stmt 1 view .LVU137
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   /* Enable SYSCFG clock */
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 415              		.loc 1 320 3 view .LVU138
+ 416              	.LBB2:
+ 417              		.loc 1 320 3 view .LVU139
+ 418              		.loc 1 320 3 view .LVU140
+ 419 0002 084B     		ldr	r3, .L19
+ 420 0004 1A6E     		ldr	r2, [r3, #96]
+ 421 0006 42F00102 		orr	r2, r2, #1
+ 422 000a 1A66     		str	r2, [r3, #96]
+ 423              		.loc 1 320 3 view .LVU141
+ 424 000c 1B6E     		ldr	r3, [r3, #96]
+ 425 000e 03F00103 		and	r3, r3, #1
+ 426 0012 0193     		str	r3, [sp, #4]
+ARM GAS  /tmp/cc3umPGo.s 			page 14
+
+
+ 427              		.loc 1 320 3 view .LVU142
+ 428 0014 019B     		ldr	r3, [sp, #4]
+ 429              	.LBE2:
+ 430              		.loc 1 320 3 view .LVU143
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   /* Enable fast mode plus driving capability for selected pin */
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+ 431              		.loc 1 323 3 view .LVU144
+ 432 0016 044A     		ldr	r2, .L19+4
+ 433 0018 5368     		ldr	r3, [r2, #4]
+ 434 001a 0343     		orrs	r3, r3, r0
+ 435 001c 5360     		str	r3, [r2, #4]
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** }
+ 436              		.loc 1 324 1 is_stmt 0 view .LVU145
+ 437 001e 02B0     		add	sp, sp, #8
+ 438              	.LCFI1:
+ 439              		.cfi_def_cfa_offset 0
+ 440              		@ sp needed
+ 441 0020 7047     		bx	lr
+ 442              	.L20:
+ 443 0022 00BF     		.align	2
+ 444              	.L19:
+ 445 0024 00100240 		.word	1073876992
+ 446 0028 00000140 		.word	1073807360
+ 447              		.cfi_endproc
+ 448              	.LFE333:
+ 450              		.section	.text.HAL_I2CEx_DisableFastModePlus,"ax",%progbits
+ 451              		.align	1
+ 452              		.global	HAL_I2CEx_DisableFastModePlus
+ 453              		.syntax unified
+ 454              		.thumb
+ 455              		.thumb_func
+ 457              	HAL_I2CEx_DisableFastModePlus:
+ 458              	.LVL32:
+ 459              	.LFB334:
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** /**
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @brief Disable the I2C fast mode plus driving capability.
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @param ConfigFastModePlus Selects the pin.
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *   This parameter can be one of the @ref I2CEx_FastModePlus values
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *        on each one of the following pins PB6, PB7, PB8 and PB9.
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @note  For all I2C4 pins fast mode plus driving capability can be disabled
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   * @retval None
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   */
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** {
+ 460              		.loc 1 344 1 is_stmt 1 view -0
+ 461              		.cfi_startproc
+ARM GAS  /tmp/cc3umPGo.s 			page 15
+
+
+ 462              		@ args = 0, pretend = 0, frame = 8
+ 463              		@ frame_needed = 0, uses_anonymous_args = 0
+ 464              		@ link register save eliminated.
+ 465              		.loc 1 344 1 is_stmt 0 view .LVU147
+ 466 0000 82B0     		sub	sp, sp, #8
+ 467              	.LCFI2:
+ 468              		.cfi_def_cfa_offset 8
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   /* Check the parameter */
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+ 469              		.loc 1 346 3 is_stmt 1 view .LVU148
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   /* Enable SYSCFG clock */
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 470              		.loc 1 349 3 view .LVU149
+ 471              	.LBB3:
+ 472              		.loc 1 349 3 view .LVU150
+ 473              		.loc 1 349 3 view .LVU151
+ 474 0002 084B     		ldr	r3, .L23
+ 475 0004 1A6E     		ldr	r2, [r3, #96]
+ 476 0006 42F00102 		orr	r2, r2, #1
+ 477 000a 1A66     		str	r2, [r3, #96]
+ 478              		.loc 1 349 3 view .LVU152
+ 479 000c 1B6E     		ldr	r3, [r3, #96]
+ 480 000e 03F00103 		and	r3, r3, #1
+ 481 0012 0193     		str	r3, [sp, #4]
+ 482              		.loc 1 349 3 view .LVU153
+ 483 0014 019B     		ldr	r3, [sp, #4]
+ 484              	.LBE3:
+ 485              		.loc 1 349 3 view .LVU154
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** 
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   /* Disable fast mode plus driving capability for selected pin */
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c ****   CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+ 486              		.loc 1 352 3 view .LVU155
+ 487 0016 044A     		ldr	r2, .L23+4
+ 488 0018 5368     		ldr	r3, [r2, #4]
+ 489 001a 23EA0003 		bic	r3, r3, r0
+ 490 001e 5360     		str	r3, [r2, #4]
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c **** }
+ 491              		.loc 1 353 1 is_stmt 0 view .LVU156
+ 492 0020 02B0     		add	sp, sp, #8
+ 493              	.LCFI3:
+ 494              		.cfi_def_cfa_offset 0
+ 495              		@ sp needed
+ 496 0022 7047     		bx	lr
+ 497              	.L24:
+ 498              		.align	2
+ 499              	.L23:
+ 500 0024 00100240 		.word	1073876992
+ 501 0028 00000140 		.word	1073807360
+ 502              		.cfi_endproc
+ 503              	.LFE334:
+ 505              		.text
+ 506              	.Letext0:
+ 507              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 508              		.file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 509              		.file 4 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 510              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ARM GAS  /tmp/cc3umPGo.s 			page 16
+
+
+ 511              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h"
+ARM GAS  /tmp/cc3umPGo.s 			page 17
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_i2c_ex.c
+     /tmp/cc3umPGo.s:21     .text.HAL_I2CEx_ConfigAnalogFilter:00000000 $t
+     /tmp/cc3umPGo.s:27     .text.HAL_I2CEx_ConfigAnalogFilter:00000000 HAL_I2CEx_ConfigAnalogFilter
+     /tmp/cc3umPGo.s:119    .text.HAL_I2CEx_ConfigDigitalFilter:00000000 $t
+     /tmp/cc3umPGo.s:125    .text.HAL_I2CEx_ConfigDigitalFilter:00000000 HAL_I2CEx_ConfigDigitalFilter
+     /tmp/cc3umPGo.s:222    .text.HAL_I2CEx_EnableWakeUp:00000000 $t
+     /tmp/cc3umPGo.s:228    .text.HAL_I2CEx_EnableWakeUp:00000000 HAL_I2CEx_EnableWakeUp
+     /tmp/cc3umPGo.s:309    .text.HAL_I2CEx_DisableWakeUp:00000000 $t
+     /tmp/cc3umPGo.s:315    .text.HAL_I2CEx_DisableWakeUp:00000000 HAL_I2CEx_DisableWakeUp
+     /tmp/cc3umPGo.s:396    .text.HAL_I2CEx_EnableFastModePlus:00000000 $t
+     /tmp/cc3umPGo.s:402    .text.HAL_I2CEx_EnableFastModePlus:00000000 HAL_I2CEx_EnableFastModePlus
+     /tmp/cc3umPGo.s:445    .text.HAL_I2CEx_EnableFastModePlus:00000024 $d
+     /tmp/cc3umPGo.s:451    .text.HAL_I2CEx_DisableFastModePlus:00000000 $t
+     /tmp/cc3umPGo.s:457    .text.HAL_I2CEx_DisableFastModePlus:00000000 HAL_I2CEx_DisableFastModePlus
+     /tmp/cc3umPGo.s:500    .text.HAL_I2CEx_DisableFastModePlus:00000024 $d
+
+NO UNDEFINED SYMBOLS
diff --git a/squeow_sw/build/stm32g4xx_hal_i2c_ex.o b/squeow_sw/build/stm32g4xx_hal_i2c_ex.o
new file mode 100644
index 0000000000000000000000000000000000000000..4a85507bf39eedd27fcb528ab53b85398396c80e
GIT binary patch
literal 13644
zcmdT~dvu#em7h<aB!7;r$c~+NnkcbDLL1w$leB3_)7X+@JF#O|a+;(RY}uA=5m|C2
zIZaC+DJ@I81d=YVuz?Mnv(UmRwEKYNlt+0l1(v2fN*6e%<=He88dypT-Lu`_Z@xRS
zq_{viXaCqa*7uux=gysb@7$UBH1e&Ty}K;SQl?mHy_%(z`tnBI;@hlYy}C%PQ1-49
zFSLig{m-F`8y-FJ!p@L&@#-_ynxm*S;@KWjlb*>n=Pi$CcnNF2I~sLswP9;`>Eyi0
z4z$f14z0PJvZ32w*r}$wJR$cpt9!NRUiBw+Pmgq*v(|WCf!<Z3_o5QL7VM(U^M+aL
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diff --git a/squeow_sw/build/stm32g4xx_hal_msp.d b/squeow_sw/build/stm32g4xx_hal_msp.d
new file mode 100644
index 0000000..04a81c8
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_msp.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_msp.o: Src/stm32g4xx_hal_msp.c Inc/main.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Inc/main.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_msp.lst b/squeow_sw/build/stm32g4xx_hal_msp.lst
new file mode 100644
index 0000000..bc51309
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_msp.lst
@@ -0,0 +1,1953 @@
+ARM GAS  /tmp/ccN6WdXz.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_msp.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Src/stm32g4xx_hal_msp.c"
+  20              		.section	.text.HAL_MspInit,"ax",%progbits
+  21              		.align	1
+  22              		.global	HAL_MspInit
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	HAL_MspInit:
+  28              	.LFB329:
+   1:Src/stm32g4xx_hal_msp.c **** /* USER CODE BEGIN Header */
+   2:Src/stm32g4xx_hal_msp.c **** /**
+   3:Src/stm32g4xx_hal_msp.c ****   ******************************************************************************
+   4:Src/stm32g4xx_hal_msp.c ****   * @file         stm32g4xx_hal_msp.c
+   5:Src/stm32g4xx_hal_msp.c ****   * @brief        This file provides code for the MSP Initialization
+   6:Src/stm32g4xx_hal_msp.c ****   *               and de-Initialization codes.
+   7:Src/stm32g4xx_hal_msp.c ****   ******************************************************************************
+   8:Src/stm32g4xx_hal_msp.c ****   * @attention
+   9:Src/stm32g4xx_hal_msp.c ****   *
+  10:Src/stm32g4xx_hal_msp.c ****   * Copyright (c) 2022 STMicroelectronics.
+  11:Src/stm32g4xx_hal_msp.c ****   * All rights reserved.
+  12:Src/stm32g4xx_hal_msp.c ****   *
+  13:Src/stm32g4xx_hal_msp.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  14:Src/stm32g4xx_hal_msp.c ****   * in the root directory of this software component.
+  15:Src/stm32g4xx_hal_msp.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  16:Src/stm32g4xx_hal_msp.c ****   *
+  17:Src/stm32g4xx_hal_msp.c ****   ******************************************************************************
+  18:Src/stm32g4xx_hal_msp.c ****   */
+  19:Src/stm32g4xx_hal_msp.c **** /* USER CODE END Header */
+  20:Src/stm32g4xx_hal_msp.c **** 
+  21:Src/stm32g4xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
+  22:Src/stm32g4xx_hal_msp.c **** #include "main.h"
+  23:Src/stm32g4xx_hal_msp.c **** /* USER CODE BEGIN Includes */
+  24:Src/stm32g4xx_hal_msp.c **** 
+  25:Src/stm32g4xx_hal_msp.c **** /* USER CODE END Includes */
+  26:Src/stm32g4xx_hal_msp.c **** 
+  27:Src/stm32g4xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
+  28:Src/stm32g4xx_hal_msp.c **** /* USER CODE BEGIN TD */
+  29:Src/stm32g4xx_hal_msp.c **** 
+  30:Src/stm32g4xx_hal_msp.c **** /* USER CODE END TD */
+ARM GAS  /tmp/ccN6WdXz.s 			page 2
+
+
+  31:Src/stm32g4xx_hal_msp.c **** 
+  32:Src/stm32g4xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
+  33:Src/stm32g4xx_hal_msp.c **** /* USER CODE BEGIN Define */
+  34:Src/stm32g4xx_hal_msp.c **** 
+  35:Src/stm32g4xx_hal_msp.c **** /* USER CODE END Define */
+  36:Src/stm32g4xx_hal_msp.c **** 
+  37:Src/stm32g4xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
+  38:Src/stm32g4xx_hal_msp.c **** /* USER CODE BEGIN Macro */
+  39:Src/stm32g4xx_hal_msp.c **** 
+  40:Src/stm32g4xx_hal_msp.c **** /* USER CODE END Macro */
+  41:Src/stm32g4xx_hal_msp.c **** 
+  42:Src/stm32g4xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
+  43:Src/stm32g4xx_hal_msp.c **** /* USER CODE BEGIN PV */
+  44:Src/stm32g4xx_hal_msp.c **** 
+  45:Src/stm32g4xx_hal_msp.c **** /* USER CODE END PV */
+  46:Src/stm32g4xx_hal_msp.c **** 
+  47:Src/stm32g4xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
+  48:Src/stm32g4xx_hal_msp.c **** /* USER CODE BEGIN PFP */
+  49:Src/stm32g4xx_hal_msp.c **** 
+  50:Src/stm32g4xx_hal_msp.c **** /* USER CODE END PFP */
+  51:Src/stm32g4xx_hal_msp.c **** 
+  52:Src/stm32g4xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
+  53:Src/stm32g4xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
+  54:Src/stm32g4xx_hal_msp.c **** 
+  55:Src/stm32g4xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
+  56:Src/stm32g4xx_hal_msp.c **** 
+  57:Src/stm32g4xx_hal_msp.c **** /* USER CODE BEGIN 0 */
+  58:Src/stm32g4xx_hal_msp.c **** 
+  59:Src/stm32g4xx_hal_msp.c **** /* USER CODE END 0 */
+  60:Src/stm32g4xx_hal_msp.c **** 
+  61:Src/stm32g4xx_hal_msp.c **** void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+  62:Src/stm32g4xx_hal_msp.c ****                     /**
+  63:Src/stm32g4xx_hal_msp.c ****   * Initializes the Global MSP.
+  64:Src/stm32g4xx_hal_msp.c ****   */
+  65:Src/stm32g4xx_hal_msp.c **** void HAL_MspInit(void)
+  66:Src/stm32g4xx_hal_msp.c **** {
+  29              		.loc 1 66 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 8
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33 0000 00B5     		push	{lr}
+  34              	.LCFI0:
+  35              		.cfi_def_cfa_offset 4
+  36              		.cfi_offset 14, -4
+  37 0002 83B0     		sub	sp, sp, #12
+  38              	.LCFI1:
+  39              		.cfi_def_cfa_offset 16
+  67:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN MspInit 0 */
+  68:Src/stm32g4xx_hal_msp.c **** 
+  69:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END MspInit 0 */
+  70:Src/stm32g4xx_hal_msp.c **** 
+  71:Src/stm32g4xx_hal_msp.c ****   __HAL_RCC_SYSCFG_CLK_ENABLE();
+  40              		.loc 1 71 3 view .LVU1
+  41              	.LBB2:
+  42              		.loc 1 71 3 view .LVU2
+  43              		.loc 1 71 3 view .LVU3
+  44 0004 0B4B     		ldr	r3, .L3
+ARM GAS  /tmp/ccN6WdXz.s 			page 3
+
+
+  45 0006 1A6E     		ldr	r2, [r3, #96]
+  46 0008 42F00102 		orr	r2, r2, #1
+  47 000c 1A66     		str	r2, [r3, #96]
+  48              		.loc 1 71 3 view .LVU4
+  49 000e 1A6E     		ldr	r2, [r3, #96]
+  50 0010 02F00102 		and	r2, r2, #1
+  51 0014 0092     		str	r2, [sp]
+  52              		.loc 1 71 3 view .LVU5
+  53 0016 009A     		ldr	r2, [sp]
+  54              	.LBE2:
+  55              		.loc 1 71 3 view .LVU6
+  72:Src/stm32g4xx_hal_msp.c ****   __HAL_RCC_PWR_CLK_ENABLE();
+  56              		.loc 1 72 3 view .LVU7
+  57              	.LBB3:
+  58              		.loc 1 72 3 view .LVU8
+  59              		.loc 1 72 3 view .LVU9
+  60 0018 9A6D     		ldr	r2, [r3, #88]
+  61 001a 42F08052 		orr	r2, r2, #268435456
+  62 001e 9A65     		str	r2, [r3, #88]
+  63              		.loc 1 72 3 view .LVU10
+  64 0020 9B6D     		ldr	r3, [r3, #88]
+  65 0022 03F08053 		and	r3, r3, #268435456
+  66 0026 0193     		str	r3, [sp, #4]
+  67              		.loc 1 72 3 view .LVU11
+  68 0028 019B     		ldr	r3, [sp, #4]
+  69              	.LBE3:
+  70              		.loc 1 72 3 view .LVU12
+  73:Src/stm32g4xx_hal_msp.c **** 
+  74:Src/stm32g4xx_hal_msp.c ****   /* System interrupt init*/
+  75:Src/stm32g4xx_hal_msp.c **** 
+  76:Src/stm32g4xx_hal_msp.c ****   /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
+  77:Src/stm32g4xx_hal_msp.c ****   */
+  78:Src/stm32g4xx_hal_msp.c ****   HAL_PWREx_DisableUCPDDeadBattery();
+  71              		.loc 1 78 3 view .LVU13
+  72 002a FFF7FEFF 		bl	HAL_PWREx_DisableUCPDDeadBattery
+  73              	.LVL0:
+  79:Src/stm32g4xx_hal_msp.c **** 
+  80:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN MspInit 1 */
+  81:Src/stm32g4xx_hal_msp.c **** 
+  82:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END MspInit 1 */
+  83:Src/stm32g4xx_hal_msp.c **** }
+  74              		.loc 1 83 1 is_stmt 0 view .LVU14
+  75 002e 03B0     		add	sp, sp, #12
+  76              	.LCFI2:
+  77              		.cfi_def_cfa_offset 4
+  78              		@ sp needed
+  79 0030 5DF804FB 		ldr	pc, [sp], #4
+  80              	.L4:
+  81              		.align	2
+  82              	.L3:
+  83 0034 00100240 		.word	1073876992
+  84              		.cfi_endproc
+  85              	.LFE329:
+  87              		.section	.text.HAL_ADC_MspInit,"ax",%progbits
+  88              		.align	1
+  89              		.global	HAL_ADC_MspInit
+  90              		.syntax unified
+ARM GAS  /tmp/ccN6WdXz.s 			page 4
+
+
+  91              		.thumb
+  92              		.thumb_func
+  94              	HAL_ADC_MspInit:
+  95              	.LVL1:
+  96              	.LFB330:
+  84:Src/stm32g4xx_hal_msp.c **** 
+  85:Src/stm32g4xx_hal_msp.c **** static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0;
+  86:Src/stm32g4xx_hal_msp.c **** 
+  87:Src/stm32g4xx_hal_msp.c **** /**
+  88:Src/stm32g4xx_hal_msp.c **** * @brief ADC MSP Initialization
+  89:Src/stm32g4xx_hal_msp.c **** * This function configures the hardware resources used in this example
+  90:Src/stm32g4xx_hal_msp.c **** * @param hadc: ADC handle pointer
+  91:Src/stm32g4xx_hal_msp.c **** * @retval None
+  92:Src/stm32g4xx_hal_msp.c **** */
+  93:Src/stm32g4xx_hal_msp.c **** void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+  94:Src/stm32g4xx_hal_msp.c **** {
+  97              		.loc 1 94 1 is_stmt 1 view -0
+  98              		.cfi_startproc
+  99              		@ args = 0, pretend = 0, frame = 104
+ 100              		@ frame_needed = 0, uses_anonymous_args = 0
+ 101              		.loc 1 94 1 is_stmt 0 view .LVU16
+ 102 0000 10B5     		push	{r4, lr}
+ 103              	.LCFI3:
+ 104              		.cfi_def_cfa_offset 8
+ 105              		.cfi_offset 4, -8
+ 106              		.cfi_offset 14, -4
+ 107 0002 9AB0     		sub	sp, sp, #104
+ 108              	.LCFI4:
+ 109              		.cfi_def_cfa_offset 112
+ 110 0004 0446     		mov	r4, r0
+  95:Src/stm32g4xx_hal_msp.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 111              		.loc 1 95 3 is_stmt 1 view .LVU17
+ 112              		.loc 1 95 20 is_stmt 0 view .LVU18
+ 113 0006 0021     		movs	r1, #0
+ 114 0008 1591     		str	r1, [sp, #84]
+ 115 000a 1691     		str	r1, [sp, #88]
+ 116 000c 1791     		str	r1, [sp, #92]
+ 117 000e 1891     		str	r1, [sp, #96]
+ 118 0010 1991     		str	r1, [sp, #100]
+  96:Src/stm32g4xx_hal_msp.c ****   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ 119              		.loc 1 96 3 is_stmt 1 view .LVU19
+ 120              		.loc 1 96 28 is_stmt 0 view .LVU20
+ 121 0012 4422     		movs	r2, #68
+ 122 0014 04A8     		add	r0, sp, #16
+ 123              	.LVL2:
+ 124              		.loc 1 96 28 view .LVU21
+ 125 0016 FFF7FEFF 		bl	memset
+ 126              	.LVL3:
+  97:Src/stm32g4xx_hal_msp.c ****   if(hadc->Instance==ADC1)
+ 127              		.loc 1 97 3 is_stmt 1 view .LVU22
+ 128              		.loc 1 97 10 is_stmt 0 view .LVU23
+ 129 001a 2368     		ldr	r3, [r4]
+ 130              		.loc 1 97 5 view .LVU24
+ 131 001c B3F1A04F 		cmp	r3, #1342177280
+ 132 0020 04D0     		beq	.L13
+  98:Src/stm32g4xx_hal_msp.c ****   {
+  99:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN ADC1_MspInit 0 */
+ARM GAS  /tmp/ccN6WdXz.s 			page 5
+
+
+ 100:Src/stm32g4xx_hal_msp.c **** 
+ 101:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END ADC1_MspInit 0 */
+ 102:Src/stm32g4xx_hal_msp.c **** 
+ 103:Src/stm32g4xx_hal_msp.c ****   /** Initializes the peripherals clocks
+ 104:Src/stm32g4xx_hal_msp.c ****   */
+ 105:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
+ 106:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
+ 107:Src/stm32g4xx_hal_msp.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 108:Src/stm32g4xx_hal_msp.c ****     {
+ 109:Src/stm32g4xx_hal_msp.c ****       Error_Handler();
+ 110:Src/stm32g4xx_hal_msp.c ****     }
+ 111:Src/stm32g4xx_hal_msp.c **** 
+ 112:Src/stm32g4xx_hal_msp.c ****     /* Peripheral clock enable */
+ 113:Src/stm32g4xx_hal_msp.c ****     HAL_RCC_ADC12_CLK_ENABLED++;
+ 114:Src/stm32g4xx_hal_msp.c ****     if(HAL_RCC_ADC12_CLK_ENABLED==1){
+ 115:Src/stm32g4xx_hal_msp.c ****       __HAL_RCC_ADC12_CLK_ENABLE();
+ 116:Src/stm32g4xx_hal_msp.c ****     }
+ 117:Src/stm32g4xx_hal_msp.c **** 
+ 118:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 119:Src/stm32g4xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 120:Src/stm32g4xx_hal_msp.c ****     PB0     ------> ADC1_IN15
+ 121:Src/stm32g4xx_hal_msp.c ****     */
+ 122:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pin = AUDIO_IN_Pin;
+ 123:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 124:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 125:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(AUDIO_IN_GPIO_Port, &GPIO_InitStruct);
+ 126:Src/stm32g4xx_hal_msp.c **** 
+ 127:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN ADC1_MspInit 1 */
+ 128:Src/stm32g4xx_hal_msp.c **** 
+ 129:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END ADC1_MspInit 1 */
+ 130:Src/stm32g4xx_hal_msp.c ****   }
+ 131:Src/stm32g4xx_hal_msp.c ****   else if(hadc->Instance==ADC2)
+ 133              		.loc 1 131 8 is_stmt 1 view .LVU25
+ 134              		.loc 1 131 10 is_stmt 0 view .LVU26
+ 135 0022 364A     		ldr	r2, .L19
+ 136 0024 9342     		cmp	r3, r2
+ 137 0026 34D0     		beq	.L14
+ 138              	.L5:
+ 132:Src/stm32g4xx_hal_msp.c ****   {
+ 133:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN ADC2_MspInit 0 */
+ 134:Src/stm32g4xx_hal_msp.c **** 
+ 135:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END ADC2_MspInit 0 */
+ 136:Src/stm32g4xx_hal_msp.c **** 
+ 137:Src/stm32g4xx_hal_msp.c ****   /** Initializes the peripherals clocks
+ 138:Src/stm32g4xx_hal_msp.c ****   */
+ 139:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
+ 140:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
+ 141:Src/stm32g4xx_hal_msp.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 142:Src/stm32g4xx_hal_msp.c ****     {
+ 143:Src/stm32g4xx_hal_msp.c ****       Error_Handler();
+ 144:Src/stm32g4xx_hal_msp.c ****     }
+ 145:Src/stm32g4xx_hal_msp.c **** 
+ 146:Src/stm32g4xx_hal_msp.c ****     /* Peripheral clock enable */
+ 147:Src/stm32g4xx_hal_msp.c ****     HAL_RCC_ADC12_CLK_ENABLED++;
+ 148:Src/stm32g4xx_hal_msp.c ****     if(HAL_RCC_ADC12_CLK_ENABLED==1){
+ 149:Src/stm32g4xx_hal_msp.c ****       __HAL_RCC_ADC12_CLK_ENABLE();
+ 150:Src/stm32g4xx_hal_msp.c ****     }
+ARM GAS  /tmp/ccN6WdXz.s 			page 6
+
+
+ 151:Src/stm32g4xx_hal_msp.c **** 
+ 152:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
+ 153:Src/stm32g4xx_hal_msp.c ****     /**ADC2 GPIO Configuration
+ 154:Src/stm32g4xx_hal_msp.c ****     PA4     ------> ADC2_IN17
+ 155:Src/stm32g4xx_hal_msp.c ****     PA5     ------> ADC2_IN13
+ 156:Src/stm32g4xx_hal_msp.c ****     PA6     ------> ADC2_IN3
+ 157:Src/stm32g4xx_hal_msp.c ****     PA7     ------> ADC2_IN4
+ 158:Src/stm32g4xx_hal_msp.c ****     */
+ 159:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pin = TEMPERATURA_Pin|CORRENTE_Pin|DIRETTA_Pin|RIFLESSA_Pin;
+ 160:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 161:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 162:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 163:Src/stm32g4xx_hal_msp.c **** 
+ 164:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN ADC2_MspInit 1 */
+ 165:Src/stm32g4xx_hal_msp.c **** 
+ 166:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END ADC2_MspInit 1 */
+ 167:Src/stm32g4xx_hal_msp.c ****   }
+ 168:Src/stm32g4xx_hal_msp.c **** 
+ 169:Src/stm32g4xx_hal_msp.c **** }
+ 139              		.loc 1 169 1 view .LVU27
+ 140 0028 1AB0     		add	sp, sp, #104
+ 141              	.LCFI5:
+ 142              		.cfi_remember_state
+ 143              		.cfi_def_cfa_offset 8
+ 144              		@ sp needed
+ 145 002a 10BD     		pop	{r4, pc}
+ 146              	.LVL4:
+ 147              	.L13:
+ 148              	.LCFI6:
+ 149              		.cfi_restore_state
+ 105:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
+ 150              		.loc 1 105 5 is_stmt 1 view .LVU28
+ 105:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
+ 151              		.loc 1 105 40 is_stmt 0 view .LVU29
+ 152 002c 4FF40043 		mov	r3, #32768
+ 153 0030 0493     		str	r3, [sp, #16]
+ 106:Src/stm32g4xx_hal_msp.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 154              		.loc 1 106 5 is_stmt 1 view .LVU30
+ 106:Src/stm32g4xx_hal_msp.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 155              		.loc 1 106 39 is_stmt 0 view .LVU31
+ 156 0032 4FF00053 		mov	r3, #536870912
+ 157 0036 1393     		str	r3, [sp, #76]
+ 107:Src/stm32g4xx_hal_msp.c ****     {
+ 158              		.loc 1 107 5 is_stmt 1 view .LVU32
+ 107:Src/stm32g4xx_hal_msp.c ****     {
+ 159              		.loc 1 107 9 is_stmt 0 view .LVU33
+ 160 0038 04A8     		add	r0, sp, #16
+ 161 003a FFF7FEFF 		bl	HAL_RCCEx_PeriphCLKConfig
+ 162              	.LVL5:
+ 107:Src/stm32g4xx_hal_msp.c ****     {
+ 163              		.loc 1 107 8 view .LVU34
+ 164 003e D0B9     		cbnz	r0, .L15
+ 165              	.L7:
+ 113:Src/stm32g4xx_hal_msp.c ****     if(HAL_RCC_ADC12_CLK_ENABLED==1){
+ 166              		.loc 1 113 5 is_stmt 1 view .LVU35
+ 113:Src/stm32g4xx_hal_msp.c ****     if(HAL_RCC_ADC12_CLK_ENABLED==1){
+ 167              		.loc 1 113 30 is_stmt 0 view .LVU36
+ARM GAS  /tmp/ccN6WdXz.s 			page 7
+
+
+ 168 0040 2F4A     		ldr	r2, .L19+4
+ 169 0042 1368     		ldr	r3, [r2]
+ 170 0044 0133     		adds	r3, r3, #1
+ 171 0046 1360     		str	r3, [r2]
+ 114:Src/stm32g4xx_hal_msp.c ****       __HAL_RCC_ADC12_CLK_ENABLE();
+ 172              		.loc 1 114 5 is_stmt 1 view .LVU37
+ 114:Src/stm32g4xx_hal_msp.c ****       __HAL_RCC_ADC12_CLK_ENABLE();
+ 173              		.loc 1 114 7 is_stmt 0 view .LVU38
+ 174 0048 012B     		cmp	r3, #1
+ 175 004a 17D0     		beq	.L16
+ 176              	.L8:
+ 115:Src/stm32g4xx_hal_msp.c ****     }
+ 177              		.loc 1 115 7 is_stmt 1 discriminator 1 view .LVU39
+ 118:Src/stm32g4xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 178              		.loc 1 118 5 discriminator 1 view .LVU40
+ 179              	.LBB4:
+ 118:Src/stm32g4xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 180              		.loc 1 118 5 discriminator 1 view .LVU41
+ 118:Src/stm32g4xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 181              		.loc 1 118 5 discriminator 1 view .LVU42
+ 182 004c 2D4B     		ldr	r3, .L19+8
+ 183 004e DA6C     		ldr	r2, [r3, #76]
+ 184 0050 42F00202 		orr	r2, r2, #2
+ 185 0054 DA64     		str	r2, [r3, #76]
+ 118:Src/stm32g4xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 186              		.loc 1 118 5 discriminator 1 view .LVU43
+ 187 0056 DB6C     		ldr	r3, [r3, #76]
+ 188 0058 03F00203 		and	r3, r3, #2
+ 189 005c 0193     		str	r3, [sp, #4]
+ 118:Src/stm32g4xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 190              		.loc 1 118 5 discriminator 1 view .LVU44
+ 191 005e 019B     		ldr	r3, [sp, #4]
+ 192              	.LBE4:
+ 118:Src/stm32g4xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 193              		.loc 1 118 5 discriminator 1 view .LVU45
+ 122:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 194              		.loc 1 122 5 discriminator 1 view .LVU46
+ 122:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 195              		.loc 1 122 25 is_stmt 0 discriminator 1 view .LVU47
+ 196 0060 0123     		movs	r3, #1
+ 197 0062 1593     		str	r3, [sp, #84]
+ 123:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 198              		.loc 1 123 5 is_stmt 1 discriminator 1 view .LVU48
+ 123:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 199              		.loc 1 123 26 is_stmt 0 discriminator 1 view .LVU49
+ 200 0064 0323     		movs	r3, #3
+ 201 0066 1693     		str	r3, [sp, #88]
+ 124:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(AUDIO_IN_GPIO_Port, &GPIO_InitStruct);
+ 202              		.loc 1 124 5 is_stmt 1 discriminator 1 view .LVU50
+ 124:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(AUDIO_IN_GPIO_Port, &GPIO_InitStruct);
+ 203              		.loc 1 124 26 is_stmt 0 discriminator 1 view .LVU51
+ 204 0068 0023     		movs	r3, #0
+ 205 006a 1793     		str	r3, [sp, #92]
+ 125:Src/stm32g4xx_hal_msp.c **** 
+ 206              		.loc 1 125 5 is_stmt 1 discriminator 1 view .LVU52
+ 207 006c 15A9     		add	r1, sp, #84
+ 208 006e 2648     		ldr	r0, .L19+12
+ARM GAS  /tmp/ccN6WdXz.s 			page 8
+
+
+ 209 0070 FFF7FEFF 		bl	HAL_GPIO_Init
+ 210              	.LVL6:
+ 211 0074 D8E7     		b	.L5
+ 212              	.L15:
+ 109:Src/stm32g4xx_hal_msp.c ****     }
+ 213              		.loc 1 109 7 view .LVU53
+ 214 0076 FFF7FEFF 		bl	Error_Handler
+ 215              	.LVL7:
+ 216 007a E1E7     		b	.L7
+ 217              	.L16:
+ 115:Src/stm32g4xx_hal_msp.c ****     }
+ 218              		.loc 1 115 7 view .LVU54
+ 219              	.LBB5:
+ 115:Src/stm32g4xx_hal_msp.c ****     }
+ 220              		.loc 1 115 7 view .LVU55
+ 115:Src/stm32g4xx_hal_msp.c ****     }
+ 221              		.loc 1 115 7 view .LVU56
+ 222 007c 214B     		ldr	r3, .L19+8
+ 223 007e DA6C     		ldr	r2, [r3, #76]
+ 224 0080 42F40052 		orr	r2, r2, #8192
+ 225 0084 DA64     		str	r2, [r3, #76]
+ 115:Src/stm32g4xx_hal_msp.c ****     }
+ 226              		.loc 1 115 7 view .LVU57
+ 227 0086 DB6C     		ldr	r3, [r3, #76]
+ 228 0088 03F40053 		and	r3, r3, #8192
+ 229 008c 0093     		str	r3, [sp]
+ 115:Src/stm32g4xx_hal_msp.c ****     }
+ 230              		.loc 1 115 7 view .LVU58
+ 231 008e 009B     		ldr	r3, [sp]
+ 232 0090 DCE7     		b	.L8
+ 233              	.L14:
+ 234              	.LBE5:
+ 139:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
+ 235              		.loc 1 139 5 view .LVU59
+ 139:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
+ 236              		.loc 1 139 40 is_stmt 0 view .LVU60
+ 237 0092 4FF40043 		mov	r3, #32768
+ 238 0096 0493     		str	r3, [sp, #16]
+ 140:Src/stm32g4xx_hal_msp.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 239              		.loc 1 140 5 is_stmt 1 view .LVU61
+ 140:Src/stm32g4xx_hal_msp.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 240              		.loc 1 140 39 is_stmt 0 view .LVU62
+ 241 0098 4FF00053 		mov	r3, #536870912
+ 242 009c 1393     		str	r3, [sp, #76]
+ 141:Src/stm32g4xx_hal_msp.c ****     {
+ 243              		.loc 1 141 5 is_stmt 1 view .LVU63
+ 141:Src/stm32g4xx_hal_msp.c ****     {
+ 244              		.loc 1 141 9 is_stmt 0 view .LVU64
+ 245 009e 04A8     		add	r0, sp, #16
+ 246 00a0 FFF7FEFF 		bl	HAL_RCCEx_PeriphCLKConfig
+ 247              	.LVL8:
+ 141:Src/stm32g4xx_hal_msp.c ****     {
+ 248              		.loc 1 141 8 view .LVU65
+ 249 00a4 D8B9     		cbnz	r0, .L17
+ 250              	.L10:
+ 147:Src/stm32g4xx_hal_msp.c ****     if(HAL_RCC_ADC12_CLK_ENABLED==1){
+ 251              		.loc 1 147 5 is_stmt 1 view .LVU66
+ARM GAS  /tmp/ccN6WdXz.s 			page 9
+
+
+ 147:Src/stm32g4xx_hal_msp.c ****     if(HAL_RCC_ADC12_CLK_ENABLED==1){
+ 252              		.loc 1 147 30 is_stmt 0 view .LVU67
+ 253 00a6 164A     		ldr	r2, .L19+4
+ 254 00a8 1368     		ldr	r3, [r2]
+ 255 00aa 0133     		adds	r3, r3, #1
+ 256 00ac 1360     		str	r3, [r2]
+ 148:Src/stm32g4xx_hal_msp.c ****       __HAL_RCC_ADC12_CLK_ENABLE();
+ 257              		.loc 1 148 5 is_stmt 1 view .LVU68
+ 148:Src/stm32g4xx_hal_msp.c ****       __HAL_RCC_ADC12_CLK_ENABLE();
+ 258              		.loc 1 148 7 is_stmt 0 view .LVU69
+ 259 00ae 012B     		cmp	r3, #1
+ 260 00b0 18D0     		beq	.L18
+ 261              	.L11:
+ 149:Src/stm32g4xx_hal_msp.c ****     }
+ 262              		.loc 1 149 7 is_stmt 1 discriminator 1 view .LVU70
+ 152:Src/stm32g4xx_hal_msp.c ****     /**ADC2 GPIO Configuration
+ 263              		.loc 1 152 5 discriminator 1 view .LVU71
+ 264              	.LBB6:
+ 152:Src/stm32g4xx_hal_msp.c ****     /**ADC2 GPIO Configuration
+ 265              		.loc 1 152 5 discriminator 1 view .LVU72
+ 152:Src/stm32g4xx_hal_msp.c ****     /**ADC2 GPIO Configuration
+ 266              		.loc 1 152 5 discriminator 1 view .LVU73
+ 267 00b2 144B     		ldr	r3, .L19+8
+ 268 00b4 DA6C     		ldr	r2, [r3, #76]
+ 269 00b6 42F00102 		orr	r2, r2, #1
+ 270 00ba DA64     		str	r2, [r3, #76]
+ 152:Src/stm32g4xx_hal_msp.c ****     /**ADC2 GPIO Configuration
+ 271              		.loc 1 152 5 discriminator 1 view .LVU74
+ 272 00bc DB6C     		ldr	r3, [r3, #76]
+ 273 00be 03F00103 		and	r3, r3, #1
+ 274 00c2 0393     		str	r3, [sp, #12]
+ 152:Src/stm32g4xx_hal_msp.c ****     /**ADC2 GPIO Configuration
+ 275              		.loc 1 152 5 discriminator 1 view .LVU75
+ 276 00c4 039B     		ldr	r3, [sp, #12]
+ 277              	.LBE6:
+ 152:Src/stm32g4xx_hal_msp.c ****     /**ADC2 GPIO Configuration
+ 278              		.loc 1 152 5 discriminator 1 view .LVU76
+ 159:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 279              		.loc 1 159 5 discriminator 1 view .LVU77
+ 159:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 280              		.loc 1 159 25 is_stmt 0 discriminator 1 view .LVU78
+ 281 00c6 F023     		movs	r3, #240
+ 282 00c8 1593     		str	r3, [sp, #84]
+ 160:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 283              		.loc 1 160 5 is_stmt 1 discriminator 1 view .LVU79
+ 160:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 284              		.loc 1 160 26 is_stmt 0 discriminator 1 view .LVU80
+ 285 00ca 0323     		movs	r3, #3
+ 286 00cc 1693     		str	r3, [sp, #88]
+ 161:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 287              		.loc 1 161 5 is_stmt 1 discriminator 1 view .LVU81
+ 161:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 288              		.loc 1 161 26 is_stmt 0 discriminator 1 view .LVU82
+ 289 00ce 0023     		movs	r3, #0
+ 290 00d0 1793     		str	r3, [sp, #92]
+ 162:Src/stm32g4xx_hal_msp.c **** 
+ 291              		.loc 1 162 5 is_stmt 1 discriminator 1 view .LVU83
+ARM GAS  /tmp/ccN6WdXz.s 			page 10
+
+
+ 292 00d2 15A9     		add	r1, sp, #84
+ 293 00d4 4FF09040 		mov	r0, #1207959552
+ 294 00d8 FFF7FEFF 		bl	HAL_GPIO_Init
+ 295              	.LVL9:
+ 296              		.loc 1 169 1 is_stmt 0 discriminator 1 view .LVU84
+ 297 00dc A4E7     		b	.L5
+ 298              	.L17:
+ 143:Src/stm32g4xx_hal_msp.c ****     }
+ 299              		.loc 1 143 7 is_stmt 1 view .LVU85
+ 300 00de FFF7FEFF 		bl	Error_Handler
+ 301              	.LVL10:
+ 302 00e2 E0E7     		b	.L10
+ 303              	.L18:
+ 149:Src/stm32g4xx_hal_msp.c ****     }
+ 304              		.loc 1 149 7 view .LVU86
+ 305              	.LBB7:
+ 149:Src/stm32g4xx_hal_msp.c ****     }
+ 306              		.loc 1 149 7 view .LVU87
+ 149:Src/stm32g4xx_hal_msp.c ****     }
+ 307              		.loc 1 149 7 view .LVU88
+ 308 00e4 074B     		ldr	r3, .L19+8
+ 309 00e6 DA6C     		ldr	r2, [r3, #76]
+ 310 00e8 42F40052 		orr	r2, r2, #8192
+ 311 00ec DA64     		str	r2, [r3, #76]
+ 149:Src/stm32g4xx_hal_msp.c ****     }
+ 312              		.loc 1 149 7 view .LVU89
+ 313 00ee DB6C     		ldr	r3, [r3, #76]
+ 314 00f0 03F40053 		and	r3, r3, #8192
+ 315 00f4 0293     		str	r3, [sp, #8]
+ 149:Src/stm32g4xx_hal_msp.c ****     }
+ 316              		.loc 1 149 7 view .LVU90
+ 317 00f6 029B     		ldr	r3, [sp, #8]
+ 318 00f8 DBE7     		b	.L11
+ 319              	.L20:
+ 320 00fa 00BF     		.align	2
+ 321              	.L19:
+ 322 00fc 00010050 		.word	1342177536
+ 323 0100 00000000 		.word	HAL_RCC_ADC12_CLK_ENABLED
+ 324 0104 00100240 		.word	1073876992
+ 325 0108 00040048 		.word	1207960576
+ 326              	.LBE7:
+ 327              		.cfi_endproc
+ 328              	.LFE330:
+ 330              		.section	.text.HAL_ADC_MspDeInit,"ax",%progbits
+ 331              		.align	1
+ 332              		.global	HAL_ADC_MspDeInit
+ 333              		.syntax unified
+ 334              		.thumb
+ 335              		.thumb_func
+ 337              	HAL_ADC_MspDeInit:
+ 338              	.LVL11:
+ 339              	.LFB331:
+ 170:Src/stm32g4xx_hal_msp.c **** 
+ 171:Src/stm32g4xx_hal_msp.c **** /**
+ 172:Src/stm32g4xx_hal_msp.c **** * @brief ADC MSP De-Initialization
+ 173:Src/stm32g4xx_hal_msp.c **** * This function freeze the hardware resources used in this example
+ 174:Src/stm32g4xx_hal_msp.c **** * @param hadc: ADC handle pointer
+ARM GAS  /tmp/ccN6WdXz.s 			page 11
+
+
+ 175:Src/stm32g4xx_hal_msp.c **** * @retval None
+ 176:Src/stm32g4xx_hal_msp.c **** */
+ 177:Src/stm32g4xx_hal_msp.c **** void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+ 178:Src/stm32g4xx_hal_msp.c **** {
+ 340              		.loc 1 178 1 view -0
+ 341              		.cfi_startproc
+ 342              		@ args = 0, pretend = 0, frame = 0
+ 343              		@ frame_needed = 0, uses_anonymous_args = 0
+ 344              		.loc 1 178 1 is_stmt 0 view .LVU92
+ 345 0000 08B5     		push	{r3, lr}
+ 346              	.LCFI7:
+ 347              		.cfi_def_cfa_offset 8
+ 348              		.cfi_offset 3, -8
+ 349              		.cfi_offset 14, -4
+ 179:Src/stm32g4xx_hal_msp.c ****   if(hadc->Instance==ADC1)
+ 350              		.loc 1 179 3 is_stmt 1 view .LVU93
+ 351              		.loc 1 179 10 is_stmt 0 view .LVU94
+ 352 0002 0368     		ldr	r3, [r0]
+ 353              		.loc 1 179 5 view .LVU95
+ 354 0004 B3F1A04F 		cmp	r3, #1342177280
+ 355 0008 03D0     		beq	.L27
+ 180:Src/stm32g4xx_hal_msp.c ****   {
+ 181:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN ADC1_MspDeInit 0 */
+ 182:Src/stm32g4xx_hal_msp.c **** 
+ 183:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END ADC1_MspDeInit 0 */
+ 184:Src/stm32g4xx_hal_msp.c ****     /* Peripheral clock disable */
+ 185:Src/stm32g4xx_hal_msp.c ****     HAL_RCC_ADC12_CLK_ENABLED--;
+ 186:Src/stm32g4xx_hal_msp.c ****     if(HAL_RCC_ADC12_CLK_ENABLED==0){
+ 187:Src/stm32g4xx_hal_msp.c ****       __HAL_RCC_ADC12_CLK_DISABLE();
+ 188:Src/stm32g4xx_hal_msp.c ****     }
+ 189:Src/stm32g4xx_hal_msp.c **** 
+ 190:Src/stm32g4xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 191:Src/stm32g4xx_hal_msp.c ****     PB0     ------> ADC1_IN15
+ 192:Src/stm32g4xx_hal_msp.c ****     */
+ 193:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_DeInit(AUDIO_IN_GPIO_Port, AUDIO_IN_Pin);
+ 194:Src/stm32g4xx_hal_msp.c **** 
+ 195:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN ADC1_MspDeInit 1 */
+ 196:Src/stm32g4xx_hal_msp.c **** 
+ 197:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END ADC1_MspDeInit 1 */
+ 198:Src/stm32g4xx_hal_msp.c ****   }
+ 199:Src/stm32g4xx_hal_msp.c ****   else if(hadc->Instance==ADC2)
+ 356              		.loc 1 199 8 is_stmt 1 view .LVU96
+ 357              		.loc 1 199 10 is_stmt 0 view .LVU97
+ 358 000a 114A     		ldr	r2, .L29
+ 359 000c 9342     		cmp	r3, r2
+ 360 000e 0FD0     		beq	.L28
+ 361              	.LVL12:
+ 362              	.L21:
+ 200:Src/stm32g4xx_hal_msp.c ****   {
+ 201:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN ADC2_MspDeInit 0 */
+ 202:Src/stm32g4xx_hal_msp.c **** 
+ 203:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END ADC2_MspDeInit 0 */
+ 204:Src/stm32g4xx_hal_msp.c ****     /* Peripheral clock disable */
+ 205:Src/stm32g4xx_hal_msp.c ****     HAL_RCC_ADC12_CLK_ENABLED--;
+ 206:Src/stm32g4xx_hal_msp.c ****     if(HAL_RCC_ADC12_CLK_ENABLED==0){
+ 207:Src/stm32g4xx_hal_msp.c ****       __HAL_RCC_ADC12_CLK_DISABLE();
+ 208:Src/stm32g4xx_hal_msp.c ****     }
+ARM GAS  /tmp/ccN6WdXz.s 			page 12
+
+
+ 209:Src/stm32g4xx_hal_msp.c **** 
+ 210:Src/stm32g4xx_hal_msp.c ****     /**ADC2 GPIO Configuration
+ 211:Src/stm32g4xx_hal_msp.c ****     PA4     ------> ADC2_IN17
+ 212:Src/stm32g4xx_hal_msp.c ****     PA5     ------> ADC2_IN13
+ 213:Src/stm32g4xx_hal_msp.c ****     PA6     ------> ADC2_IN3
+ 214:Src/stm32g4xx_hal_msp.c ****     PA7     ------> ADC2_IN4
+ 215:Src/stm32g4xx_hal_msp.c ****     */
+ 216:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOA, TEMPERATURA_Pin|CORRENTE_Pin|DIRETTA_Pin|RIFLESSA_Pin);
+ 217:Src/stm32g4xx_hal_msp.c **** 
+ 218:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN ADC2_MspDeInit 1 */
+ 219:Src/stm32g4xx_hal_msp.c **** 
+ 220:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END ADC2_MspDeInit 1 */
+ 221:Src/stm32g4xx_hal_msp.c ****   }
+ 222:Src/stm32g4xx_hal_msp.c **** 
+ 223:Src/stm32g4xx_hal_msp.c **** }
+ 363              		.loc 1 223 1 view .LVU98
+ 364 0010 08BD     		pop	{r3, pc}
+ 365              	.LVL13:
+ 366              	.L27:
+ 185:Src/stm32g4xx_hal_msp.c ****     if(HAL_RCC_ADC12_CLK_ENABLED==0){
+ 367              		.loc 1 185 5 is_stmt 1 view .LVU99
+ 185:Src/stm32g4xx_hal_msp.c ****     if(HAL_RCC_ADC12_CLK_ENABLED==0){
+ 368              		.loc 1 185 30 is_stmt 0 view .LVU100
+ 369 0012 104A     		ldr	r2, .L29+4
+ 370 0014 1368     		ldr	r3, [r2]
+ 371 0016 013B     		subs	r3, r3, #1
+ 372 0018 1360     		str	r3, [r2]
+ 186:Src/stm32g4xx_hal_msp.c ****       __HAL_RCC_ADC12_CLK_DISABLE();
+ 373              		.loc 1 186 5 is_stmt 1 view .LVU101
+ 186:Src/stm32g4xx_hal_msp.c ****       __HAL_RCC_ADC12_CLK_DISABLE();
+ 374              		.loc 1 186 7 is_stmt 0 view .LVU102
+ 375 001a 23B9     		cbnz	r3, .L23
+ 187:Src/stm32g4xx_hal_msp.c ****     }
+ 376              		.loc 1 187 7 is_stmt 1 view .LVU103
+ 377 001c 0E4A     		ldr	r2, .L29+8
+ 378 001e D36C     		ldr	r3, [r2, #76]
+ 379 0020 23F40053 		bic	r3, r3, #8192
+ 380 0024 D364     		str	r3, [r2, #76]
+ 381              	.L23:
+ 193:Src/stm32g4xx_hal_msp.c **** 
+ 382              		.loc 1 193 5 view .LVU104
+ 383 0026 0121     		movs	r1, #1
+ 384 0028 0C48     		ldr	r0, .L29+12
+ 385              	.LVL14:
+ 193:Src/stm32g4xx_hal_msp.c **** 
+ 386              		.loc 1 193 5 is_stmt 0 view .LVU105
+ 387 002a FFF7FEFF 		bl	HAL_GPIO_DeInit
+ 388              	.LVL15:
+ 389 002e EFE7     		b	.L21
+ 390              	.LVL16:
+ 391              	.L28:
+ 205:Src/stm32g4xx_hal_msp.c ****     if(HAL_RCC_ADC12_CLK_ENABLED==0){
+ 392              		.loc 1 205 5 is_stmt 1 view .LVU106
+ 205:Src/stm32g4xx_hal_msp.c ****     if(HAL_RCC_ADC12_CLK_ENABLED==0){
+ 393              		.loc 1 205 30 is_stmt 0 view .LVU107
+ 394 0030 084A     		ldr	r2, .L29+4
+ 395 0032 1368     		ldr	r3, [r2]
+ARM GAS  /tmp/ccN6WdXz.s 			page 13
+
+
+ 396 0034 013B     		subs	r3, r3, #1
+ 397 0036 1360     		str	r3, [r2]
+ 206:Src/stm32g4xx_hal_msp.c ****       __HAL_RCC_ADC12_CLK_DISABLE();
+ 398              		.loc 1 206 5 is_stmt 1 view .LVU108
+ 206:Src/stm32g4xx_hal_msp.c ****       __HAL_RCC_ADC12_CLK_DISABLE();
+ 399              		.loc 1 206 7 is_stmt 0 view .LVU109
+ 400 0038 23B9     		cbnz	r3, .L25
+ 207:Src/stm32g4xx_hal_msp.c ****     }
+ 401              		.loc 1 207 7 is_stmt 1 view .LVU110
+ 402 003a 074A     		ldr	r2, .L29+8
+ 403 003c D36C     		ldr	r3, [r2, #76]
+ 404 003e 23F40053 		bic	r3, r3, #8192
+ 405 0042 D364     		str	r3, [r2, #76]
+ 406              	.L25:
+ 216:Src/stm32g4xx_hal_msp.c **** 
+ 407              		.loc 1 216 5 view .LVU111
+ 408 0044 F021     		movs	r1, #240
+ 409 0046 4FF09040 		mov	r0, #1207959552
+ 410              	.LVL17:
+ 216:Src/stm32g4xx_hal_msp.c **** 
+ 411              		.loc 1 216 5 is_stmt 0 view .LVU112
+ 412 004a FFF7FEFF 		bl	HAL_GPIO_DeInit
+ 413              	.LVL18:
+ 414              		.loc 1 223 1 view .LVU113
+ 415 004e DFE7     		b	.L21
+ 416              	.L30:
+ 417              		.align	2
+ 418              	.L29:
+ 419 0050 00010050 		.word	1342177536
+ 420 0054 00000000 		.word	HAL_RCC_ADC12_CLK_ENABLED
+ 421 0058 00100240 		.word	1073876992
+ 422 005c 00040048 		.word	1207960576
+ 423              		.cfi_endproc
+ 424              	.LFE331:
+ 426              		.section	.text.HAL_I2C_MspInit,"ax",%progbits
+ 427              		.align	1
+ 428              		.global	HAL_I2C_MspInit
+ 429              		.syntax unified
+ 430              		.thumb
+ 431              		.thumb_func
+ 433              	HAL_I2C_MspInit:
+ 434              	.LVL19:
+ 435              	.LFB332:
+ 224:Src/stm32g4xx_hal_msp.c **** 
+ 225:Src/stm32g4xx_hal_msp.c **** /**
+ 226:Src/stm32g4xx_hal_msp.c **** * @brief I2C MSP Initialization
+ 227:Src/stm32g4xx_hal_msp.c **** * This function configures the hardware resources used in this example
+ 228:Src/stm32g4xx_hal_msp.c **** * @param hi2c: I2C handle pointer
+ 229:Src/stm32g4xx_hal_msp.c **** * @retval None
+ 230:Src/stm32g4xx_hal_msp.c **** */
+ 231:Src/stm32g4xx_hal_msp.c **** void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
+ 232:Src/stm32g4xx_hal_msp.c **** {
+ 436              		.loc 1 232 1 is_stmt 1 view -0
+ 437              		.cfi_startproc
+ 438              		@ args = 0, pretend = 0, frame = 104
+ 439              		@ frame_needed = 0, uses_anonymous_args = 0
+ 440              		.loc 1 232 1 is_stmt 0 view .LVU115
+ARM GAS  /tmp/ccN6WdXz.s 			page 14
+
+
+ 441 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 442              	.LCFI8:
+ 443              		.cfi_def_cfa_offset 20
+ 444              		.cfi_offset 4, -20
+ 445              		.cfi_offset 5, -16
+ 446              		.cfi_offset 6, -12
+ 447              		.cfi_offset 7, -8
+ 448              		.cfi_offset 14, -4
+ 449 0002 9BB0     		sub	sp, sp, #108
+ 450              	.LCFI9:
+ 451              		.cfi_def_cfa_offset 128
+ 452 0004 0446     		mov	r4, r0
+ 233:Src/stm32g4xx_hal_msp.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 453              		.loc 1 233 3 is_stmt 1 view .LVU116
+ 454              		.loc 1 233 20 is_stmt 0 view .LVU117
+ 455 0006 0021     		movs	r1, #0
+ 456 0008 1591     		str	r1, [sp, #84]
+ 457 000a 1691     		str	r1, [sp, #88]
+ 458 000c 1791     		str	r1, [sp, #92]
+ 459 000e 1891     		str	r1, [sp, #96]
+ 460 0010 1991     		str	r1, [sp, #100]
+ 234:Src/stm32g4xx_hal_msp.c ****   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ 461              		.loc 1 234 3 is_stmt 1 view .LVU118
+ 462              		.loc 1 234 28 is_stmt 0 view .LVU119
+ 463 0012 4422     		movs	r2, #68
+ 464 0014 04A8     		add	r0, sp, #16
+ 465              	.LVL20:
+ 466              		.loc 1 234 28 view .LVU120
+ 467 0016 FFF7FEFF 		bl	memset
+ 468              	.LVL21:
+ 235:Src/stm32g4xx_hal_msp.c ****   if(hi2c->Instance==I2C1)
+ 469              		.loc 1 235 3 is_stmt 1 view .LVU121
+ 470              		.loc 1 235 10 is_stmt 0 view .LVU122
+ 471 001a 2268     		ldr	r2, [r4]
+ 472              		.loc 1 235 5 view .LVU123
+ 473 001c 224B     		ldr	r3, .L37
+ 474 001e 9A42     		cmp	r2, r3
+ 475 0020 01D0     		beq	.L35
+ 476              	.LVL22:
+ 477              	.L31:
+ 236:Src/stm32g4xx_hal_msp.c ****   {
+ 237:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN I2C1_MspInit 0 */
+ 238:Src/stm32g4xx_hal_msp.c **** 
+ 239:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END I2C1_MspInit 0 */
+ 240:Src/stm32g4xx_hal_msp.c **** 
+ 241:Src/stm32g4xx_hal_msp.c ****   /** Initializes the peripherals clocks
+ 242:Src/stm32g4xx_hal_msp.c ****   */
+ 243:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
+ 244:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
+ 245:Src/stm32g4xx_hal_msp.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 246:Src/stm32g4xx_hal_msp.c ****     {
+ 247:Src/stm32g4xx_hal_msp.c ****       Error_Handler();
+ 248:Src/stm32g4xx_hal_msp.c ****     }
+ 249:Src/stm32g4xx_hal_msp.c **** 
+ 250:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
+ 251:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 252:Src/stm32g4xx_hal_msp.c ****     /**I2C1 GPIO Configuration
+ARM GAS  /tmp/ccN6WdXz.s 			page 15
+
+
+ 253:Src/stm32g4xx_hal_msp.c ****     PA15     ------> I2C1_SCL
+ 254:Src/stm32g4xx_hal_msp.c ****     PB7     ------> I2C1_SDA
+ 255:Src/stm32g4xx_hal_msp.c ****     */
+ 256:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_15;
+ 257:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+ 258:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 259:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 260:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+ 261:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 262:Src/stm32g4xx_hal_msp.c **** 
+ 263:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_7;
+ 264:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+ 265:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 266:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 267:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+ 268:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 269:Src/stm32g4xx_hal_msp.c **** 
+ 270:Src/stm32g4xx_hal_msp.c ****     /* Peripheral clock enable */
+ 271:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_I2C1_CLK_ENABLE();
+ 272:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN I2C1_MspInit 1 */
+ 273:Src/stm32g4xx_hal_msp.c **** 
+ 274:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END I2C1_MspInit 1 */
+ 275:Src/stm32g4xx_hal_msp.c ****   }
+ 276:Src/stm32g4xx_hal_msp.c **** 
+ 277:Src/stm32g4xx_hal_msp.c **** }
+ 478              		.loc 1 277 1 view .LVU124
+ 479 0022 1BB0     		add	sp, sp, #108
+ 480              	.LCFI10:
+ 481              		.cfi_remember_state
+ 482              		.cfi_def_cfa_offset 20
+ 483              		@ sp needed
+ 484 0024 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 485              	.LVL23:
+ 486              	.L35:
+ 487              	.LCFI11:
+ 488              		.cfi_restore_state
+ 243:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
+ 489              		.loc 1 243 5 is_stmt 1 view .LVU125
+ 243:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
+ 490              		.loc 1 243 40 is_stmt 0 view .LVU126
+ 491 0026 4023     		movs	r3, #64
+ 492 0028 0493     		str	r3, [sp, #16]
+ 244:Src/stm32g4xx_hal_msp.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 493              		.loc 1 244 5 is_stmt 1 view .LVU127
+ 245:Src/stm32g4xx_hal_msp.c ****     {
+ 494              		.loc 1 245 5 view .LVU128
+ 245:Src/stm32g4xx_hal_msp.c ****     {
+ 495              		.loc 1 245 9 is_stmt 0 view .LVU129
+ 496 002a 04A8     		add	r0, sp, #16
+ 497 002c FFF7FEFF 		bl	HAL_RCCEx_PeriphCLKConfig
+ 498              	.LVL24:
+ 245:Src/stm32g4xx_hal_msp.c ****     {
+ 499              		.loc 1 245 8 view .LVU130
+ 500 0030 0028     		cmp	r0, #0
+ 501 0032 35D1     		bne	.L36
+ 502              	.L33:
+ 250:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ARM GAS  /tmp/ccN6WdXz.s 			page 16
+
+
+ 503              		.loc 1 250 5 is_stmt 1 view .LVU131
+ 504              	.LBB8:
+ 250:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 505              		.loc 1 250 5 view .LVU132
+ 250:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 506              		.loc 1 250 5 view .LVU133
+ 507 0034 1D4C     		ldr	r4, .L37+4
+ 508              	.LVL25:
+ 250:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 509              		.loc 1 250 5 is_stmt 0 view .LVU134
+ 510 0036 E36C     		ldr	r3, [r4, #76]
+ 511 0038 43F00103 		orr	r3, r3, #1
+ 512 003c E364     		str	r3, [r4, #76]
+ 250:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 513              		.loc 1 250 5 is_stmt 1 view .LVU135
+ 514 003e E36C     		ldr	r3, [r4, #76]
+ 515 0040 03F00103 		and	r3, r3, #1
+ 516 0044 0193     		str	r3, [sp, #4]
+ 250:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 517              		.loc 1 250 5 view .LVU136
+ 518 0046 019B     		ldr	r3, [sp, #4]
+ 519              	.LBE8:
+ 250:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 520              		.loc 1 250 5 view .LVU137
+ 251:Src/stm32g4xx_hal_msp.c ****     /**I2C1 GPIO Configuration
+ 521              		.loc 1 251 5 view .LVU138
+ 522              	.LBB9:
+ 251:Src/stm32g4xx_hal_msp.c ****     /**I2C1 GPIO Configuration
+ 523              		.loc 1 251 5 view .LVU139
+ 251:Src/stm32g4xx_hal_msp.c ****     /**I2C1 GPIO Configuration
+ 524              		.loc 1 251 5 view .LVU140
+ 525 0048 E36C     		ldr	r3, [r4, #76]
+ 526 004a 43F00203 		orr	r3, r3, #2
+ 527 004e E364     		str	r3, [r4, #76]
+ 251:Src/stm32g4xx_hal_msp.c ****     /**I2C1 GPIO Configuration
+ 528              		.loc 1 251 5 view .LVU141
+ 529 0050 E36C     		ldr	r3, [r4, #76]
+ 530 0052 03F00203 		and	r3, r3, #2
+ 531 0056 0293     		str	r3, [sp, #8]
+ 251:Src/stm32g4xx_hal_msp.c ****     /**I2C1 GPIO Configuration
+ 532              		.loc 1 251 5 view .LVU142
+ 533 0058 029B     		ldr	r3, [sp, #8]
+ 534              	.LBE9:
+ 251:Src/stm32g4xx_hal_msp.c ****     /**I2C1 GPIO Configuration
+ 535              		.loc 1 251 5 view .LVU143
+ 256:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+ 536              		.loc 1 256 5 view .LVU144
+ 256:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+ 537              		.loc 1 256 25 is_stmt 0 view .LVU145
+ 538 005a 4FF40043 		mov	r3, #32768
+ 539 005e 1593     		str	r3, [sp, #84]
+ 257:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 540              		.loc 1 257 5 is_stmt 1 view .LVU146
+ 257:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 541              		.loc 1 257 26 is_stmt 0 view .LVU147
+ 542 0060 1227     		movs	r7, #18
+ 543 0062 1697     		str	r7, [sp, #88]
+ARM GAS  /tmp/ccN6WdXz.s 			page 17
+
+
+ 258:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 544              		.loc 1 258 5 is_stmt 1 view .LVU148
+ 258:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 545              		.loc 1 258 26 is_stmt 0 view .LVU149
+ 546 0064 0025     		movs	r5, #0
+ 547 0066 1795     		str	r5, [sp, #92]
+ 259:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+ 548              		.loc 1 259 5 is_stmt 1 view .LVU150
+ 259:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+ 549              		.loc 1 259 27 is_stmt 0 view .LVU151
+ 550 0068 1895     		str	r5, [sp, #96]
+ 260:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 551              		.loc 1 260 5 is_stmt 1 view .LVU152
+ 260:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 552              		.loc 1 260 31 is_stmt 0 view .LVU153
+ 553 006a 0426     		movs	r6, #4
+ 554 006c 1996     		str	r6, [sp, #100]
+ 261:Src/stm32g4xx_hal_msp.c **** 
+ 555              		.loc 1 261 5 is_stmt 1 view .LVU154
+ 556 006e 15A9     		add	r1, sp, #84
+ 557 0070 4FF09040 		mov	r0, #1207959552
+ 558 0074 FFF7FEFF 		bl	HAL_GPIO_Init
+ 559              	.LVL26:
+ 263:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+ 560              		.loc 1 263 5 view .LVU155
+ 263:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+ 561              		.loc 1 263 25 is_stmt 0 view .LVU156
+ 562 0078 8023     		movs	r3, #128
+ 563 007a 1593     		str	r3, [sp, #84]
+ 264:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 564              		.loc 1 264 5 is_stmt 1 view .LVU157
+ 264:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 565              		.loc 1 264 26 is_stmt 0 view .LVU158
+ 566 007c 1697     		str	r7, [sp, #88]
+ 265:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 567              		.loc 1 265 5 is_stmt 1 view .LVU159
+ 265:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 568              		.loc 1 265 26 is_stmt 0 view .LVU160
+ 569 007e 1795     		str	r5, [sp, #92]
+ 266:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+ 570              		.loc 1 266 5 is_stmt 1 view .LVU161
+ 266:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+ 571              		.loc 1 266 27 is_stmt 0 view .LVU162
+ 572 0080 1895     		str	r5, [sp, #96]
+ 267:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 573              		.loc 1 267 5 is_stmt 1 view .LVU163
+ 267:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 574              		.loc 1 267 31 is_stmt 0 view .LVU164
+ 575 0082 1996     		str	r6, [sp, #100]
+ 268:Src/stm32g4xx_hal_msp.c **** 
+ 576              		.loc 1 268 5 is_stmt 1 view .LVU165
+ 577 0084 15A9     		add	r1, sp, #84
+ 578 0086 0A48     		ldr	r0, .L37+8
+ 579 0088 FFF7FEFF 		bl	HAL_GPIO_Init
+ 580              	.LVL27:
+ 271:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN I2C1_MspInit 1 */
+ 581              		.loc 1 271 5 view .LVU166
+ARM GAS  /tmp/ccN6WdXz.s 			page 18
+
+
+ 582              	.LBB10:
+ 271:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN I2C1_MspInit 1 */
+ 583              		.loc 1 271 5 view .LVU167
+ 271:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN I2C1_MspInit 1 */
+ 584              		.loc 1 271 5 view .LVU168
+ 585 008c A36D     		ldr	r3, [r4, #88]
+ 586 008e 43F40013 		orr	r3, r3, #2097152
+ 587 0092 A365     		str	r3, [r4, #88]
+ 271:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN I2C1_MspInit 1 */
+ 588              		.loc 1 271 5 view .LVU169
+ 589 0094 A36D     		ldr	r3, [r4, #88]
+ 590 0096 03F40013 		and	r3, r3, #2097152
+ 591 009a 0393     		str	r3, [sp, #12]
+ 271:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN I2C1_MspInit 1 */
+ 592              		.loc 1 271 5 view .LVU170
+ 593 009c 039B     		ldr	r3, [sp, #12]
+ 594              	.LBE10:
+ 271:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN I2C1_MspInit 1 */
+ 595              		.loc 1 271 5 view .LVU171
+ 596              		.loc 1 277 1 is_stmt 0 view .LVU172
+ 597 009e C0E7     		b	.L31
+ 598              	.LVL28:
+ 599              	.L36:
+ 247:Src/stm32g4xx_hal_msp.c ****     }
+ 600              		.loc 1 247 7 is_stmt 1 view .LVU173
+ 601 00a0 FFF7FEFF 		bl	Error_Handler
+ 602              	.LVL29:
+ 603 00a4 C6E7     		b	.L33
+ 604              	.L38:
+ 605 00a6 00BF     		.align	2
+ 606              	.L37:
+ 607 00a8 00540040 		.word	1073763328
+ 608 00ac 00100240 		.word	1073876992
+ 609 00b0 00040048 		.word	1207960576
+ 610              		.cfi_endproc
+ 611              	.LFE332:
+ 613              		.section	.text.HAL_I2C_MspDeInit,"ax",%progbits
+ 614              		.align	1
+ 615              		.global	HAL_I2C_MspDeInit
+ 616              		.syntax unified
+ 617              		.thumb
+ 618              		.thumb_func
+ 620              	HAL_I2C_MspDeInit:
+ 621              	.LVL30:
+ 622              	.LFB333:
+ 278:Src/stm32g4xx_hal_msp.c **** 
+ 279:Src/stm32g4xx_hal_msp.c **** /**
+ 280:Src/stm32g4xx_hal_msp.c **** * @brief I2C MSP De-Initialization
+ 281:Src/stm32g4xx_hal_msp.c **** * This function freeze the hardware resources used in this example
+ 282:Src/stm32g4xx_hal_msp.c **** * @param hi2c: I2C handle pointer
+ 283:Src/stm32g4xx_hal_msp.c **** * @retval None
+ 284:Src/stm32g4xx_hal_msp.c **** */
+ 285:Src/stm32g4xx_hal_msp.c **** void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
+ 286:Src/stm32g4xx_hal_msp.c **** {
+ 623              		.loc 1 286 1 view -0
+ 624              		.cfi_startproc
+ 625              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/ccN6WdXz.s 			page 19
+
+
+ 626              		@ frame_needed = 0, uses_anonymous_args = 0
+ 627              		.loc 1 286 1 is_stmt 0 view .LVU175
+ 628 0000 08B5     		push	{r3, lr}
+ 629              	.LCFI12:
+ 630              		.cfi_def_cfa_offset 8
+ 631              		.cfi_offset 3, -8
+ 632              		.cfi_offset 14, -4
+ 287:Src/stm32g4xx_hal_msp.c ****   if(hi2c->Instance==I2C1)
+ 633              		.loc 1 287 3 is_stmt 1 view .LVU176
+ 634              		.loc 1 287 10 is_stmt 0 view .LVU177
+ 635 0002 0268     		ldr	r2, [r0]
+ 636              		.loc 1 287 5 view .LVU178
+ 637 0004 094B     		ldr	r3, .L43
+ 638 0006 9A42     		cmp	r2, r3
+ 639 0008 00D0     		beq	.L42
+ 640              	.LVL31:
+ 641              	.L39:
+ 288:Src/stm32g4xx_hal_msp.c ****   {
+ 289:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN I2C1_MspDeInit 0 */
+ 290:Src/stm32g4xx_hal_msp.c **** 
+ 291:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END I2C1_MspDeInit 0 */
+ 292:Src/stm32g4xx_hal_msp.c ****     /* Peripheral clock disable */
+ 293:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_I2C1_CLK_DISABLE();
+ 294:Src/stm32g4xx_hal_msp.c **** 
+ 295:Src/stm32g4xx_hal_msp.c ****     /**I2C1 GPIO Configuration
+ 296:Src/stm32g4xx_hal_msp.c ****     PA15     ------> I2C1_SCL
+ 297:Src/stm32g4xx_hal_msp.c ****     PB7     ------> I2C1_SDA
+ 298:Src/stm32g4xx_hal_msp.c ****     */
+ 299:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOA, GPIO_PIN_15);
+ 300:Src/stm32g4xx_hal_msp.c **** 
+ 301:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7);
+ 302:Src/stm32g4xx_hal_msp.c **** 
+ 303:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN I2C1_MspDeInit 1 */
+ 304:Src/stm32g4xx_hal_msp.c **** 
+ 305:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END I2C1_MspDeInit 1 */
+ 306:Src/stm32g4xx_hal_msp.c ****   }
+ 307:Src/stm32g4xx_hal_msp.c **** 
+ 308:Src/stm32g4xx_hal_msp.c **** }
+ 642              		.loc 1 308 1 view .LVU179
+ 643 000a 08BD     		pop	{r3, pc}
+ 644              	.LVL32:
+ 645              	.L42:
+ 293:Src/stm32g4xx_hal_msp.c **** 
+ 646              		.loc 1 293 5 is_stmt 1 view .LVU180
+ 647 000c 084A     		ldr	r2, .L43+4
+ 648 000e 936D     		ldr	r3, [r2, #88]
+ 649 0010 23F40013 		bic	r3, r3, #2097152
+ 650 0014 9365     		str	r3, [r2, #88]
+ 299:Src/stm32g4xx_hal_msp.c **** 
+ 651              		.loc 1 299 5 view .LVU181
+ 652 0016 4FF40041 		mov	r1, #32768
+ 653 001a 4FF09040 		mov	r0, #1207959552
+ 654              	.LVL33:
+ 299:Src/stm32g4xx_hal_msp.c **** 
+ 655              		.loc 1 299 5 is_stmt 0 view .LVU182
+ 656 001e FFF7FEFF 		bl	HAL_GPIO_DeInit
+ 657              	.LVL34:
+ARM GAS  /tmp/ccN6WdXz.s 			page 20
+
+
+ 301:Src/stm32g4xx_hal_msp.c **** 
+ 658              		.loc 1 301 5 is_stmt 1 view .LVU183
+ 659 0022 8021     		movs	r1, #128
+ 660 0024 0348     		ldr	r0, .L43+8
+ 661 0026 FFF7FEFF 		bl	HAL_GPIO_DeInit
+ 662              	.LVL35:
+ 663              		.loc 1 308 1 is_stmt 0 view .LVU184
+ 664 002a EEE7     		b	.L39
+ 665              	.L44:
+ 666              		.align	2
+ 667              	.L43:
+ 668 002c 00540040 		.word	1073763328
+ 669 0030 00100240 		.word	1073876992
+ 670 0034 00040048 		.word	1207960576
+ 671              		.cfi_endproc
+ 672              	.LFE333:
+ 674              		.section	.text.HAL_TIM_Base_MspInit,"ax",%progbits
+ 675              		.align	1
+ 676              		.global	HAL_TIM_Base_MspInit
+ 677              		.syntax unified
+ 678              		.thumb
+ 679              		.thumb_func
+ 681              	HAL_TIM_Base_MspInit:
+ 682              	.LVL36:
+ 683              	.LFB334:
+ 309:Src/stm32g4xx_hal_msp.c **** 
+ 310:Src/stm32g4xx_hal_msp.c **** /**
+ 311:Src/stm32g4xx_hal_msp.c **** * @brief TIM_Base MSP Initialization
+ 312:Src/stm32g4xx_hal_msp.c **** * This function configures the hardware resources used in this example
+ 313:Src/stm32g4xx_hal_msp.c **** * @param htim_base: TIM_Base handle pointer
+ 314:Src/stm32g4xx_hal_msp.c **** * @retval None
+ 315:Src/stm32g4xx_hal_msp.c **** */
+ 316:Src/stm32g4xx_hal_msp.c **** void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+ 317:Src/stm32g4xx_hal_msp.c **** {
+ 684              		.loc 1 317 1 is_stmt 1 view -0
+ 685              		.cfi_startproc
+ 686              		@ args = 0, pretend = 0, frame = 8
+ 687              		@ frame_needed = 0, uses_anonymous_args = 0
+ 688              		.loc 1 317 1 is_stmt 0 view .LVU186
+ 689 0000 00B5     		push	{lr}
+ 690              	.LCFI13:
+ 691              		.cfi_def_cfa_offset 4
+ 692              		.cfi_offset 14, -4
+ 693 0002 83B0     		sub	sp, sp, #12
+ 694              	.LCFI14:
+ 695              		.cfi_def_cfa_offset 16
+ 318:Src/stm32g4xx_hal_msp.c ****   if(htim_base->Instance==TIM2)
+ 696              		.loc 1 318 3 is_stmt 1 view .LVU187
+ 697              		.loc 1 318 15 is_stmt 0 view .LVU188
+ 698 0004 0368     		ldr	r3, [r0]
+ 699              		.loc 1 318 5 view .LVU189
+ 700 0006 B3F1804F 		cmp	r3, #1073741824
+ 701 000a 05D0     		beq	.L49
+ 319:Src/stm32g4xx_hal_msp.c ****   {
+ 320:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspInit 0 */
+ 321:Src/stm32g4xx_hal_msp.c **** 
+ 322:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END TIM2_MspInit 0 */
+ARM GAS  /tmp/ccN6WdXz.s 			page 21
+
+
+ 323:Src/stm32g4xx_hal_msp.c ****     /* Peripheral clock enable */
+ 324:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_TIM2_CLK_ENABLE();
+ 325:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspInit 1 */
+ 326:Src/stm32g4xx_hal_msp.c **** 
+ 327:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END TIM2_MspInit 1 */
+ 328:Src/stm32g4xx_hal_msp.c ****   }
+ 329:Src/stm32g4xx_hal_msp.c ****   else if(htim_base->Instance==TIM3)
+ 702              		.loc 1 329 8 is_stmt 1 view .LVU190
+ 703              		.loc 1 329 10 is_stmt 0 view .LVU191
+ 704 000c 124A     		ldr	r2, .L51
+ 705 000e 9342     		cmp	r3, r2
+ 706 0010 0ED0     		beq	.L50
+ 707              	.LVL37:
+ 708              	.L45:
+ 330:Src/stm32g4xx_hal_msp.c ****   {
+ 331:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM3_MspInit 0 */
+ 332:Src/stm32g4xx_hal_msp.c **** 
+ 333:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END TIM3_MspInit 0 */
+ 334:Src/stm32g4xx_hal_msp.c ****     /* Peripheral clock enable */
+ 335:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_TIM3_CLK_ENABLE();
+ 336:Src/stm32g4xx_hal_msp.c ****     /* TIM3 interrupt Init */
+ 337:Src/stm32g4xx_hal_msp.c ****     HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
+ 338:Src/stm32g4xx_hal_msp.c ****     HAL_NVIC_EnableIRQ(TIM3_IRQn);
+ 339:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM3_MspInit 1 */
+ 340:Src/stm32g4xx_hal_msp.c **** 
+ 341:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END TIM3_MspInit 1 */
+ 342:Src/stm32g4xx_hal_msp.c ****   }
+ 343:Src/stm32g4xx_hal_msp.c **** 
+ 344:Src/stm32g4xx_hal_msp.c **** }
+ 709              		.loc 1 344 1 view .LVU192
+ 710 0012 03B0     		add	sp, sp, #12
+ 711              	.LCFI15:
+ 712              		.cfi_remember_state
+ 713              		.cfi_def_cfa_offset 4
+ 714              		@ sp needed
+ 715 0014 5DF804FB 		ldr	pc, [sp], #4
+ 716              	.LVL38:
+ 717              	.L49:
+ 718              	.LCFI16:
+ 719              		.cfi_restore_state
+ 324:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspInit 1 */
+ 720              		.loc 1 324 5 is_stmt 1 view .LVU193
+ 721              	.LBB11:
+ 324:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspInit 1 */
+ 722              		.loc 1 324 5 view .LVU194
+ 324:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspInit 1 */
+ 723              		.loc 1 324 5 view .LVU195
+ 724 0018 03F50433 		add	r3, r3, #135168
+ 725 001c 9A6D     		ldr	r2, [r3, #88]
+ 726 001e 42F00102 		orr	r2, r2, #1
+ 727 0022 9A65     		str	r2, [r3, #88]
+ 324:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspInit 1 */
+ 728              		.loc 1 324 5 view .LVU196
+ 729 0024 9B6D     		ldr	r3, [r3, #88]
+ 730 0026 03F00103 		and	r3, r3, #1
+ 731 002a 0093     		str	r3, [sp]
+ 324:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspInit 1 */
+ARM GAS  /tmp/ccN6WdXz.s 			page 22
+
+
+ 732              		.loc 1 324 5 view .LVU197
+ 733 002c 009B     		ldr	r3, [sp]
+ 734              	.LBE11:
+ 324:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspInit 1 */
+ 735              		.loc 1 324 5 view .LVU198
+ 736 002e F0E7     		b	.L45
+ 737              	.L50:
+ 335:Src/stm32g4xx_hal_msp.c ****     /* TIM3 interrupt Init */
+ 738              		.loc 1 335 5 view .LVU199
+ 739              	.LBB12:
+ 335:Src/stm32g4xx_hal_msp.c ****     /* TIM3 interrupt Init */
+ 740              		.loc 1 335 5 view .LVU200
+ 335:Src/stm32g4xx_hal_msp.c ****     /* TIM3 interrupt Init */
+ 741              		.loc 1 335 5 view .LVU201
+ 742 0030 0A4B     		ldr	r3, .L51+4
+ 743 0032 9A6D     		ldr	r2, [r3, #88]
+ 744 0034 42F00202 		orr	r2, r2, #2
+ 745 0038 9A65     		str	r2, [r3, #88]
+ 335:Src/stm32g4xx_hal_msp.c ****     /* TIM3 interrupt Init */
+ 746              		.loc 1 335 5 view .LVU202
+ 747 003a 9B6D     		ldr	r3, [r3, #88]
+ 748 003c 03F00203 		and	r3, r3, #2
+ 749 0040 0193     		str	r3, [sp, #4]
+ 335:Src/stm32g4xx_hal_msp.c ****     /* TIM3 interrupt Init */
+ 750              		.loc 1 335 5 view .LVU203
+ 751 0042 019B     		ldr	r3, [sp, #4]
+ 752              	.LBE12:
+ 335:Src/stm32g4xx_hal_msp.c ****     /* TIM3 interrupt Init */
+ 753              		.loc 1 335 5 view .LVU204
+ 337:Src/stm32g4xx_hal_msp.c ****     HAL_NVIC_EnableIRQ(TIM3_IRQn);
+ 754              		.loc 1 337 5 view .LVU205
+ 755 0044 0022     		movs	r2, #0
+ 756 0046 1146     		mov	r1, r2
+ 757 0048 1D20     		movs	r0, #29
+ 758              	.LVL39:
+ 337:Src/stm32g4xx_hal_msp.c ****     HAL_NVIC_EnableIRQ(TIM3_IRQn);
+ 759              		.loc 1 337 5 is_stmt 0 view .LVU206
+ 760 004a FFF7FEFF 		bl	HAL_NVIC_SetPriority
+ 761              	.LVL40:
+ 338:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM3_MspInit 1 */
+ 762              		.loc 1 338 5 is_stmt 1 view .LVU207
+ 763 004e 1D20     		movs	r0, #29
+ 764 0050 FFF7FEFF 		bl	HAL_NVIC_EnableIRQ
+ 765              	.LVL41:
+ 766              		.loc 1 344 1 is_stmt 0 view .LVU208
+ 767 0054 DDE7     		b	.L45
+ 768              	.L52:
+ 769 0056 00BF     		.align	2
+ 770              	.L51:
+ 771 0058 00040040 		.word	1073742848
+ 772 005c 00100240 		.word	1073876992
+ 773              		.cfi_endproc
+ 774              	.LFE334:
+ 776              		.section	.text.HAL_TIM_MspPostInit,"ax",%progbits
+ 777              		.align	1
+ 778              		.global	HAL_TIM_MspPostInit
+ 779              		.syntax unified
+ARM GAS  /tmp/ccN6WdXz.s 			page 23
+
+
+ 780              		.thumb
+ 781              		.thumb_func
+ 783              	HAL_TIM_MspPostInit:
+ 784              	.LVL42:
+ 785              	.LFB335:
+ 345:Src/stm32g4xx_hal_msp.c **** 
+ 346:Src/stm32g4xx_hal_msp.c **** void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+ 347:Src/stm32g4xx_hal_msp.c **** {
+ 786              		.loc 1 347 1 is_stmt 1 view -0
+ 787              		.cfi_startproc
+ 788              		@ args = 0, pretend = 0, frame = 24
+ 789              		@ frame_needed = 0, uses_anonymous_args = 0
+ 790              		.loc 1 347 1 is_stmt 0 view .LVU210
+ 791 0000 00B5     		push	{lr}
+ 792              	.LCFI17:
+ 793              		.cfi_def_cfa_offset 4
+ 794              		.cfi_offset 14, -4
+ 795 0002 87B0     		sub	sp, sp, #28
+ 796              	.LCFI18:
+ 797              		.cfi_def_cfa_offset 32
+ 348:Src/stm32g4xx_hal_msp.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 798              		.loc 1 348 3 is_stmt 1 view .LVU211
+ 799              		.loc 1 348 20 is_stmt 0 view .LVU212
+ 800 0004 0023     		movs	r3, #0
+ 801 0006 0193     		str	r3, [sp, #4]
+ 802 0008 0293     		str	r3, [sp, #8]
+ 803 000a 0393     		str	r3, [sp, #12]
+ 804 000c 0493     		str	r3, [sp, #16]
+ 805 000e 0593     		str	r3, [sp, #20]
+ 349:Src/stm32g4xx_hal_msp.c ****   if(htim->Instance==TIM2)
+ 806              		.loc 1 349 3 is_stmt 1 view .LVU213
+ 807              		.loc 1 349 10 is_stmt 0 view .LVU214
+ 808 0010 0368     		ldr	r3, [r0]
+ 809              		.loc 1 349 5 view .LVU215
+ 810 0012 B3F1804F 		cmp	r3, #1073741824
+ 811 0016 02D0     		beq	.L56
+ 812              	.LVL43:
+ 813              	.L53:
+ 350:Src/stm32g4xx_hal_msp.c ****   {
+ 351:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspPostInit 0 */
+ 352:Src/stm32g4xx_hal_msp.c **** 
+ 353:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END TIM2_MspPostInit 0 */
+ 354:Src/stm32g4xx_hal_msp.c **** 
+ 355:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
+ 356:Src/stm32g4xx_hal_msp.c ****     /**TIM2 GPIO Configuration
+ 357:Src/stm32g4xx_hal_msp.c ****     PA0     ------> TIM2_CH1
+ 358:Src/stm32g4xx_hal_msp.c ****     PA1     ------> TIM2_CH2
+ 359:Src/stm32g4xx_hal_msp.c ****     PA2     ------> TIM2_CH3
+ 360:Src/stm32g4xx_hal_msp.c ****     PA3     ------> TIM2_CH4
+ 361:Src/stm32g4xx_hal_msp.c ****     */
+ 362:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
+ 363:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 364:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 365:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 366:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+ 367:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 368:Src/stm32g4xx_hal_msp.c **** 
+ARM GAS  /tmp/ccN6WdXz.s 			page 24
+
+
+ 369:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspPostInit 1 */
+ 370:Src/stm32g4xx_hal_msp.c **** 
+ 371:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END TIM2_MspPostInit 1 */
+ 372:Src/stm32g4xx_hal_msp.c ****   }
+ 373:Src/stm32g4xx_hal_msp.c **** 
+ 374:Src/stm32g4xx_hal_msp.c **** }
+ 814              		.loc 1 374 1 view .LVU216
+ 815 0018 07B0     		add	sp, sp, #28
+ 816              	.LCFI19:
+ 817              		.cfi_remember_state
+ 818              		.cfi_def_cfa_offset 4
+ 819              		@ sp needed
+ 820 001a 5DF804FB 		ldr	pc, [sp], #4
+ 821              	.LVL44:
+ 822              	.L56:
+ 823              	.LCFI20:
+ 824              		.cfi_restore_state
+ 355:Src/stm32g4xx_hal_msp.c ****     /**TIM2 GPIO Configuration
+ 825              		.loc 1 355 5 is_stmt 1 view .LVU217
+ 826              	.LBB13:
+ 355:Src/stm32g4xx_hal_msp.c ****     /**TIM2 GPIO Configuration
+ 827              		.loc 1 355 5 view .LVU218
+ 355:Src/stm32g4xx_hal_msp.c ****     /**TIM2 GPIO Configuration
+ 828              		.loc 1 355 5 view .LVU219
+ 829 001e 03F50433 		add	r3, r3, #135168
+ 830 0022 DA6C     		ldr	r2, [r3, #76]
+ 831 0024 42F00102 		orr	r2, r2, #1
+ 832 0028 DA64     		str	r2, [r3, #76]
+ 355:Src/stm32g4xx_hal_msp.c ****     /**TIM2 GPIO Configuration
+ 833              		.loc 1 355 5 view .LVU220
+ 834 002a DB6C     		ldr	r3, [r3, #76]
+ 835 002c 03F00103 		and	r3, r3, #1
+ 836 0030 0093     		str	r3, [sp]
+ 355:Src/stm32g4xx_hal_msp.c ****     /**TIM2 GPIO Configuration
+ 837              		.loc 1 355 5 view .LVU221
+ 838 0032 009B     		ldr	r3, [sp]
+ 839              	.LBE13:
+ 355:Src/stm32g4xx_hal_msp.c ****     /**TIM2 GPIO Configuration
+ 840              		.loc 1 355 5 view .LVU222
+ 362:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 841              		.loc 1 362 5 view .LVU223
+ 362:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 842              		.loc 1 362 25 is_stmt 0 view .LVU224
+ 843 0034 0F23     		movs	r3, #15
+ 844 0036 0193     		str	r3, [sp, #4]
+ 363:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 845              		.loc 1 363 5 is_stmt 1 view .LVU225
+ 363:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 846              		.loc 1 363 26 is_stmt 0 view .LVU226
+ 847 0038 0223     		movs	r3, #2
+ 848 003a 0293     		str	r3, [sp, #8]
+ 364:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 849              		.loc 1 364 5 is_stmt 1 view .LVU227
+ 365:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+ 850              		.loc 1 365 5 view .LVU228
+ 366:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 851              		.loc 1 366 5 view .LVU229
+ARM GAS  /tmp/ccN6WdXz.s 			page 25
+
+
+ 366:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 852              		.loc 1 366 31 is_stmt 0 view .LVU230
+ 853 003c 0123     		movs	r3, #1
+ 854 003e 0593     		str	r3, [sp, #20]
+ 367:Src/stm32g4xx_hal_msp.c **** 
+ 855              		.loc 1 367 5 is_stmt 1 view .LVU231
+ 856 0040 01A9     		add	r1, sp, #4
+ 857 0042 4FF09040 		mov	r0, #1207959552
+ 858              	.LVL45:
+ 367:Src/stm32g4xx_hal_msp.c **** 
+ 859              		.loc 1 367 5 is_stmt 0 view .LVU232
+ 860 0046 FFF7FEFF 		bl	HAL_GPIO_Init
+ 861              	.LVL46:
+ 862              		.loc 1 374 1 view .LVU233
+ 863 004a E5E7     		b	.L53
+ 864              		.cfi_endproc
+ 865              	.LFE335:
+ 867              		.section	.text.HAL_TIM_Base_MspDeInit,"ax",%progbits
+ 868              		.align	1
+ 869              		.global	HAL_TIM_Base_MspDeInit
+ 870              		.syntax unified
+ 871              		.thumb
+ 872              		.thumb_func
+ 874              	HAL_TIM_Base_MspDeInit:
+ 875              	.LVL47:
+ 876              	.LFB336:
+ 375:Src/stm32g4xx_hal_msp.c **** /**
+ 376:Src/stm32g4xx_hal_msp.c **** * @brief TIM_Base MSP De-Initialization
+ 377:Src/stm32g4xx_hal_msp.c **** * This function freeze the hardware resources used in this example
+ 378:Src/stm32g4xx_hal_msp.c **** * @param htim_base: TIM_Base handle pointer
+ 379:Src/stm32g4xx_hal_msp.c **** * @retval None
+ 380:Src/stm32g4xx_hal_msp.c **** */
+ 381:Src/stm32g4xx_hal_msp.c **** void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+ 382:Src/stm32g4xx_hal_msp.c **** {
+ 877              		.loc 1 382 1 is_stmt 1 view -0
+ 878              		.cfi_startproc
+ 879              		@ args = 0, pretend = 0, frame = 0
+ 880              		@ frame_needed = 0, uses_anonymous_args = 0
+ 881              		.loc 1 382 1 is_stmt 0 view .LVU235
+ 882 0000 08B5     		push	{r3, lr}
+ 883              	.LCFI21:
+ 884              		.cfi_def_cfa_offset 8
+ 885              		.cfi_offset 3, -8
+ 886              		.cfi_offset 14, -4
+ 383:Src/stm32g4xx_hal_msp.c ****   if(htim_base->Instance==TIM2)
+ 887              		.loc 1 383 3 is_stmt 1 view .LVU236
+ 888              		.loc 1 383 15 is_stmt 0 view .LVU237
+ 889 0002 0368     		ldr	r3, [r0]
+ 890              		.loc 1 383 5 view .LVU238
+ 891 0004 B3F1804F 		cmp	r3, #1073741824
+ 892 0008 03D0     		beq	.L61
+ 384:Src/stm32g4xx_hal_msp.c ****   {
+ 385:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspDeInit 0 */
+ 386:Src/stm32g4xx_hal_msp.c **** 
+ 387:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END TIM2_MspDeInit 0 */
+ 388:Src/stm32g4xx_hal_msp.c ****     /* Peripheral clock disable */
+ 389:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_TIM2_CLK_DISABLE();
+ARM GAS  /tmp/ccN6WdXz.s 			page 26
+
+
+ 390:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspDeInit 1 */
+ 391:Src/stm32g4xx_hal_msp.c **** 
+ 392:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END TIM2_MspDeInit 1 */
+ 393:Src/stm32g4xx_hal_msp.c ****   }
+ 394:Src/stm32g4xx_hal_msp.c ****   else if(htim_base->Instance==TIM3)
+ 893              		.loc 1 394 8 is_stmt 1 view .LVU239
+ 894              		.loc 1 394 10 is_stmt 0 view .LVU240
+ 895 000a 0A4A     		ldr	r2, .L63
+ 896 000c 9342     		cmp	r3, r2
+ 897 000e 06D0     		beq	.L62
+ 898              	.LVL48:
+ 899              	.L57:
+ 395:Src/stm32g4xx_hal_msp.c ****   {
+ 396:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM3_MspDeInit 0 */
+ 397:Src/stm32g4xx_hal_msp.c **** 
+ 398:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END TIM3_MspDeInit 0 */
+ 399:Src/stm32g4xx_hal_msp.c ****     /* Peripheral clock disable */
+ 400:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_TIM3_CLK_DISABLE();
+ 401:Src/stm32g4xx_hal_msp.c **** 
+ 402:Src/stm32g4xx_hal_msp.c ****     /* TIM3 interrupt DeInit */
+ 403:Src/stm32g4xx_hal_msp.c ****     HAL_NVIC_DisableIRQ(TIM3_IRQn);
+ 404:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM3_MspDeInit 1 */
+ 405:Src/stm32g4xx_hal_msp.c **** 
+ 406:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END TIM3_MspDeInit 1 */
+ 407:Src/stm32g4xx_hal_msp.c ****   }
+ 408:Src/stm32g4xx_hal_msp.c **** 
+ 409:Src/stm32g4xx_hal_msp.c **** }
+ 900              		.loc 1 409 1 view .LVU241
+ 901 0010 08BD     		pop	{r3, pc}
+ 902              	.LVL49:
+ 903              	.L61:
+ 389:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM2_MspDeInit 1 */
+ 904              		.loc 1 389 5 is_stmt 1 view .LVU242
+ 905 0012 094A     		ldr	r2, .L63+4
+ 906 0014 936D     		ldr	r3, [r2, #88]
+ 907 0016 23F00103 		bic	r3, r3, #1
+ 908 001a 9365     		str	r3, [r2, #88]
+ 909 001c F8E7     		b	.L57
+ 910              	.L62:
+ 400:Src/stm32g4xx_hal_msp.c **** 
+ 911              		.loc 1 400 5 view .LVU243
+ 912 001e 02F50332 		add	r2, r2, #134144
+ 913 0022 936D     		ldr	r3, [r2, #88]
+ 914 0024 23F00203 		bic	r3, r3, #2
+ 915 0028 9365     		str	r3, [r2, #88]
+ 403:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM3_MspDeInit 1 */
+ 916              		.loc 1 403 5 view .LVU244
+ 917 002a 1D20     		movs	r0, #29
+ 918              	.LVL50:
+ 403:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN TIM3_MspDeInit 1 */
+ 919              		.loc 1 403 5 is_stmt 0 view .LVU245
+ 920 002c FFF7FEFF 		bl	HAL_NVIC_DisableIRQ
+ 921              	.LVL51:
+ 922              		.loc 1 409 1 view .LVU246
+ 923 0030 EEE7     		b	.L57
+ 924              	.L64:
+ 925 0032 00BF     		.align	2
+ARM GAS  /tmp/ccN6WdXz.s 			page 27
+
+
+ 926              	.L63:
+ 927 0034 00040040 		.word	1073742848
+ 928 0038 00100240 		.word	1073876992
+ 929              		.cfi_endproc
+ 930              	.LFE336:
+ 932              		.section	.text.HAL_UART_MspInit,"ax",%progbits
+ 933              		.align	1
+ 934              		.global	HAL_UART_MspInit
+ 935              		.syntax unified
+ 936              		.thumb
+ 937              		.thumb_func
+ 939              	HAL_UART_MspInit:
+ 940              	.LVL52:
+ 941              	.LFB337:
+ 410:Src/stm32g4xx_hal_msp.c **** 
+ 411:Src/stm32g4xx_hal_msp.c **** /**
+ 412:Src/stm32g4xx_hal_msp.c **** * @brief UART MSP Initialization
+ 413:Src/stm32g4xx_hal_msp.c **** * This function configures the hardware resources used in this example
+ 414:Src/stm32g4xx_hal_msp.c **** * @param huart: UART handle pointer
+ 415:Src/stm32g4xx_hal_msp.c **** * @retval None
+ 416:Src/stm32g4xx_hal_msp.c **** */
+ 417:Src/stm32g4xx_hal_msp.c **** void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+ 418:Src/stm32g4xx_hal_msp.c **** {
+ 942              		.loc 1 418 1 is_stmt 1 view -0
+ 943              		.cfi_startproc
+ 944              		@ args = 0, pretend = 0, frame = 96
+ 945              		@ frame_needed = 0, uses_anonymous_args = 0
+ 946              		.loc 1 418 1 is_stmt 0 view .LVU248
+ 947 0000 10B5     		push	{r4, lr}
+ 948              	.LCFI22:
+ 949              		.cfi_def_cfa_offset 8
+ 950              		.cfi_offset 4, -8
+ 951              		.cfi_offset 14, -4
+ 952 0002 98B0     		sub	sp, sp, #96
+ 953              	.LCFI23:
+ 954              		.cfi_def_cfa_offset 104
+ 955 0004 0446     		mov	r4, r0
+ 419:Src/stm32g4xx_hal_msp.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 956              		.loc 1 419 3 is_stmt 1 view .LVU249
+ 957              		.loc 1 419 20 is_stmt 0 view .LVU250
+ 958 0006 0021     		movs	r1, #0
+ 959 0008 1391     		str	r1, [sp, #76]
+ 960 000a 1491     		str	r1, [sp, #80]
+ 961 000c 1591     		str	r1, [sp, #84]
+ 962 000e 1691     		str	r1, [sp, #88]
+ 963 0010 1791     		str	r1, [sp, #92]
+ 420:Src/stm32g4xx_hal_msp.c ****   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ 964              		.loc 1 420 3 is_stmt 1 view .LVU251
+ 965              		.loc 1 420 28 is_stmt 0 view .LVU252
+ 966 0012 4422     		movs	r2, #68
+ 967 0014 02A8     		add	r0, sp, #8
+ 968              	.LVL53:
+ 969              		.loc 1 420 28 view .LVU253
+ 970 0016 FFF7FEFF 		bl	memset
+ 971              	.LVL54:
+ 421:Src/stm32g4xx_hal_msp.c ****   if(huart->Instance==USART1)
+ 972              		.loc 1 421 3 is_stmt 1 view .LVU254
+ARM GAS  /tmp/ccN6WdXz.s 			page 28
+
+
+ 973              		.loc 1 421 11 is_stmt 0 view .LVU255
+ 974 001a 2268     		ldr	r2, [r4]
+ 975              		.loc 1 421 5 view .LVU256
+ 976 001c 184B     		ldr	r3, .L71
+ 977 001e 9A42     		cmp	r2, r3
+ 978 0020 01D0     		beq	.L69
+ 979              	.L65:
+ 422:Src/stm32g4xx_hal_msp.c ****   {
+ 423:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN USART1_MspInit 0 */
+ 424:Src/stm32g4xx_hal_msp.c **** 
+ 425:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END USART1_MspInit 0 */
+ 426:Src/stm32g4xx_hal_msp.c **** 
+ 427:Src/stm32g4xx_hal_msp.c ****   /** Initializes the peripherals clocks
+ 428:Src/stm32g4xx_hal_msp.c ****   */
+ 429:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+ 430:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+ 431:Src/stm32g4xx_hal_msp.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 432:Src/stm32g4xx_hal_msp.c ****     {
+ 433:Src/stm32g4xx_hal_msp.c ****       Error_Handler();
+ 434:Src/stm32g4xx_hal_msp.c ****     }
+ 435:Src/stm32g4xx_hal_msp.c **** 
+ 436:Src/stm32g4xx_hal_msp.c ****     /* Peripheral clock enable */
+ 437:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_USART1_CLK_ENABLE();
+ 438:Src/stm32g4xx_hal_msp.c **** 
+ 439:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
+ 440:Src/stm32g4xx_hal_msp.c ****     /**USART1 GPIO Configuration
+ 441:Src/stm32g4xx_hal_msp.c ****     PA9     ------> USART1_TX
+ 442:Src/stm32g4xx_hal_msp.c ****     PA10     ------> USART1_RX
+ 443:Src/stm32g4xx_hal_msp.c ****     */
+ 444:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
+ 445:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 446:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 447:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 448:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+ 449:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 450:Src/stm32g4xx_hal_msp.c **** 
+ 451:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN USART1_MspInit 1 */
+ 452:Src/stm32g4xx_hal_msp.c **** 
+ 453:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END USART1_MspInit 1 */
+ 454:Src/stm32g4xx_hal_msp.c ****   }
+ 455:Src/stm32g4xx_hal_msp.c **** 
+ 456:Src/stm32g4xx_hal_msp.c **** }
+ 980              		.loc 1 456 1 view .LVU257
+ 981 0022 18B0     		add	sp, sp, #96
+ 982              	.LCFI24:
+ 983              		.cfi_remember_state
+ 984              		.cfi_def_cfa_offset 8
+ 985              		@ sp needed
+ 986 0024 10BD     		pop	{r4, pc}
+ 987              	.LVL55:
+ 988              	.L69:
+ 989              	.LCFI25:
+ 990              		.cfi_restore_state
+ 429:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+ 991              		.loc 1 429 5 is_stmt 1 view .LVU258
+ 429:Src/stm32g4xx_hal_msp.c ****     PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+ 992              		.loc 1 429 40 is_stmt 0 view .LVU259
+ARM GAS  /tmp/ccN6WdXz.s 			page 29
+
+
+ 993 0026 0123     		movs	r3, #1
+ 994 0028 0293     		str	r3, [sp, #8]
+ 430:Src/stm32g4xx_hal_msp.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 995              		.loc 1 430 5 is_stmt 1 view .LVU260
+ 431:Src/stm32g4xx_hal_msp.c ****     {
+ 996              		.loc 1 431 5 view .LVU261
+ 431:Src/stm32g4xx_hal_msp.c ****     {
+ 997              		.loc 1 431 9 is_stmt 0 view .LVU262
+ 998 002a 02A8     		add	r0, sp, #8
+ 999 002c FFF7FEFF 		bl	HAL_RCCEx_PeriphCLKConfig
+ 1000              	.LVL56:
+ 431:Src/stm32g4xx_hal_msp.c ****     {
+ 1001              		.loc 1 431 8 view .LVU263
+ 1002 0030 10BB     		cbnz	r0, .L70
+ 1003              	.L67:
+ 437:Src/stm32g4xx_hal_msp.c **** 
+ 1004              		.loc 1 437 5 is_stmt 1 view .LVU264
+ 1005              	.LBB14:
+ 437:Src/stm32g4xx_hal_msp.c **** 
+ 1006              		.loc 1 437 5 view .LVU265
+ 437:Src/stm32g4xx_hal_msp.c **** 
+ 1007              		.loc 1 437 5 view .LVU266
+ 1008 0032 144B     		ldr	r3, .L71+4
+ 1009 0034 1A6E     		ldr	r2, [r3, #96]
+ 1010 0036 42F48042 		orr	r2, r2, #16384
+ 1011 003a 1A66     		str	r2, [r3, #96]
+ 437:Src/stm32g4xx_hal_msp.c **** 
+ 1012              		.loc 1 437 5 view .LVU267
+ 1013 003c 1A6E     		ldr	r2, [r3, #96]
+ 1014 003e 02F48042 		and	r2, r2, #16384
+ 1015 0042 0092     		str	r2, [sp]
+ 437:Src/stm32g4xx_hal_msp.c **** 
+ 1016              		.loc 1 437 5 view .LVU268
+ 1017 0044 009A     		ldr	r2, [sp]
+ 1018              	.LBE14:
+ 437:Src/stm32g4xx_hal_msp.c **** 
+ 1019              		.loc 1 437 5 view .LVU269
+ 439:Src/stm32g4xx_hal_msp.c ****     /**USART1 GPIO Configuration
+ 1020              		.loc 1 439 5 view .LVU270
+ 1021              	.LBB15:
+ 439:Src/stm32g4xx_hal_msp.c ****     /**USART1 GPIO Configuration
+ 1022              		.loc 1 439 5 view .LVU271
+ 439:Src/stm32g4xx_hal_msp.c ****     /**USART1 GPIO Configuration
+ 1023              		.loc 1 439 5 view .LVU272
+ 1024 0046 DA6C     		ldr	r2, [r3, #76]
+ 1025 0048 42F00102 		orr	r2, r2, #1
+ 1026 004c DA64     		str	r2, [r3, #76]
+ 439:Src/stm32g4xx_hal_msp.c ****     /**USART1 GPIO Configuration
+ 1027              		.loc 1 439 5 view .LVU273
+ 1028 004e DB6C     		ldr	r3, [r3, #76]
+ 1029 0050 03F00103 		and	r3, r3, #1
+ 1030 0054 0193     		str	r3, [sp, #4]
+ 439:Src/stm32g4xx_hal_msp.c ****     /**USART1 GPIO Configuration
+ 1031              		.loc 1 439 5 view .LVU274
+ 1032 0056 019B     		ldr	r3, [sp, #4]
+ 1033              	.LBE15:
+ 439:Src/stm32g4xx_hal_msp.c ****     /**USART1 GPIO Configuration
+ARM GAS  /tmp/ccN6WdXz.s 			page 30
+
+
+ 1034              		.loc 1 439 5 view .LVU275
+ 444:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 1035              		.loc 1 444 5 view .LVU276
+ 444:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 1036              		.loc 1 444 25 is_stmt 0 view .LVU277
+ 1037 0058 4FF4C063 		mov	r3, #1536
+ 1038 005c 1393     		str	r3, [sp, #76]
+ 445:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 1039              		.loc 1 445 5 is_stmt 1 view .LVU278
+ 445:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 1040              		.loc 1 445 26 is_stmt 0 view .LVU279
+ 1041 005e 0223     		movs	r3, #2
+ 1042 0060 1493     		str	r3, [sp, #80]
+ 446:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 1043              		.loc 1 446 5 is_stmt 1 view .LVU280
+ 446:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 1044              		.loc 1 446 26 is_stmt 0 view .LVU281
+ 1045 0062 0023     		movs	r3, #0
+ 1046 0064 1593     		str	r3, [sp, #84]
+ 447:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+ 1047              		.loc 1 447 5 is_stmt 1 view .LVU282
+ 447:Src/stm32g4xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+ 1048              		.loc 1 447 27 is_stmt 0 view .LVU283
+ 1049 0066 1693     		str	r3, [sp, #88]
+ 448:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 1050              		.loc 1 448 5 is_stmt 1 view .LVU284
+ 448:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 1051              		.loc 1 448 31 is_stmt 0 view .LVU285
+ 1052 0068 0723     		movs	r3, #7
+ 1053 006a 1793     		str	r3, [sp, #92]
+ 449:Src/stm32g4xx_hal_msp.c **** 
+ 1054              		.loc 1 449 5 is_stmt 1 view .LVU286
+ 1055 006c 13A9     		add	r1, sp, #76
+ 1056 006e 4FF09040 		mov	r0, #1207959552
+ 1057 0072 FFF7FEFF 		bl	HAL_GPIO_Init
+ 1058              	.LVL57:
+ 1059              		.loc 1 456 1 is_stmt 0 view .LVU287
+ 1060 0076 D4E7     		b	.L65
+ 1061              	.L70:
+ 433:Src/stm32g4xx_hal_msp.c ****     }
+ 1062              		.loc 1 433 7 is_stmt 1 view .LVU288
+ 1063 0078 FFF7FEFF 		bl	Error_Handler
+ 1064              	.LVL58:
+ 1065 007c D9E7     		b	.L67
+ 1066              	.L72:
+ 1067 007e 00BF     		.align	2
+ 1068              	.L71:
+ 1069 0080 00380140 		.word	1073821696
+ 1070 0084 00100240 		.word	1073876992
+ 1071              		.cfi_endproc
+ 1072              	.LFE337:
+ 1074              		.section	.text.HAL_UART_MspDeInit,"ax",%progbits
+ 1075              		.align	1
+ 1076              		.global	HAL_UART_MspDeInit
+ 1077              		.syntax unified
+ 1078              		.thumb
+ 1079              		.thumb_func
+ARM GAS  /tmp/ccN6WdXz.s 			page 31
+
+
+ 1081              	HAL_UART_MspDeInit:
+ 1082              	.LVL59:
+ 1083              	.LFB338:
+ 457:Src/stm32g4xx_hal_msp.c **** 
+ 458:Src/stm32g4xx_hal_msp.c **** /**
+ 459:Src/stm32g4xx_hal_msp.c **** * @brief UART MSP De-Initialization
+ 460:Src/stm32g4xx_hal_msp.c **** * This function freeze the hardware resources used in this example
+ 461:Src/stm32g4xx_hal_msp.c **** * @param huart: UART handle pointer
+ 462:Src/stm32g4xx_hal_msp.c **** * @retval None
+ 463:Src/stm32g4xx_hal_msp.c **** */
+ 464:Src/stm32g4xx_hal_msp.c **** void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+ 465:Src/stm32g4xx_hal_msp.c **** {
+ 1084              		.loc 1 465 1 view -0
+ 1085              		.cfi_startproc
+ 1086              		@ args = 0, pretend = 0, frame = 0
+ 1087              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1088              		.loc 1 465 1 is_stmt 0 view .LVU290
+ 1089 0000 08B5     		push	{r3, lr}
+ 1090              	.LCFI26:
+ 1091              		.cfi_def_cfa_offset 8
+ 1092              		.cfi_offset 3, -8
+ 1093              		.cfi_offset 14, -4
+ 466:Src/stm32g4xx_hal_msp.c ****   if(huart->Instance==USART1)
+ 1094              		.loc 1 466 3 is_stmt 1 view .LVU291
+ 1095              		.loc 1 466 11 is_stmt 0 view .LVU292
+ 1096 0002 0268     		ldr	r2, [r0]
+ 1097              		.loc 1 466 5 view .LVU293
+ 1098 0004 074B     		ldr	r3, .L77
+ 1099 0006 9A42     		cmp	r2, r3
+ 1100 0008 00D0     		beq	.L76
+ 1101              	.LVL60:
+ 1102              	.L73:
+ 467:Src/stm32g4xx_hal_msp.c ****   {
+ 468:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN USART1_MspDeInit 0 */
+ 469:Src/stm32g4xx_hal_msp.c **** 
+ 470:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END USART1_MspDeInit 0 */
+ 471:Src/stm32g4xx_hal_msp.c ****     /* Peripheral clock disable */
+ 472:Src/stm32g4xx_hal_msp.c ****     __HAL_RCC_USART1_CLK_DISABLE();
+ 473:Src/stm32g4xx_hal_msp.c **** 
+ 474:Src/stm32g4xx_hal_msp.c ****     /**USART1 GPIO Configuration
+ 475:Src/stm32g4xx_hal_msp.c ****     PA9     ------> USART1_TX
+ 476:Src/stm32g4xx_hal_msp.c ****     PA10     ------> USART1_RX
+ 477:Src/stm32g4xx_hal_msp.c ****     */
+ 478:Src/stm32g4xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
+ 479:Src/stm32g4xx_hal_msp.c **** 
+ 480:Src/stm32g4xx_hal_msp.c ****   /* USER CODE BEGIN USART1_MspDeInit 1 */
+ 481:Src/stm32g4xx_hal_msp.c **** 
+ 482:Src/stm32g4xx_hal_msp.c ****   /* USER CODE END USART1_MspDeInit 1 */
+ 483:Src/stm32g4xx_hal_msp.c ****   }
+ 484:Src/stm32g4xx_hal_msp.c **** 
+ 485:Src/stm32g4xx_hal_msp.c **** }
+ 1103              		.loc 1 485 1 view .LVU294
+ 1104 000a 08BD     		pop	{r3, pc}
+ 1105              	.LVL61:
+ 1106              	.L76:
+ 472:Src/stm32g4xx_hal_msp.c **** 
+ 1107              		.loc 1 472 5 is_stmt 1 view .LVU295
+ARM GAS  /tmp/ccN6WdXz.s 			page 32
+
+
+ 1108 000c 064A     		ldr	r2, .L77+4
+ 1109 000e 136E     		ldr	r3, [r2, #96]
+ 1110 0010 23F48043 		bic	r3, r3, #16384
+ 1111 0014 1366     		str	r3, [r2, #96]
+ 478:Src/stm32g4xx_hal_msp.c **** 
+ 1112              		.loc 1 478 5 view .LVU296
+ 1113 0016 4FF4C061 		mov	r1, #1536
+ 1114 001a 4FF09040 		mov	r0, #1207959552
+ 1115              	.LVL62:
+ 478:Src/stm32g4xx_hal_msp.c **** 
+ 1116              		.loc 1 478 5 is_stmt 0 view .LVU297
+ 1117 001e FFF7FEFF 		bl	HAL_GPIO_DeInit
+ 1118              	.LVL63:
+ 1119              		.loc 1 485 1 view .LVU298
+ 1120 0022 F2E7     		b	.L73
+ 1121              	.L78:
+ 1122              		.align	2
+ 1123              	.L77:
+ 1124 0024 00380140 		.word	1073821696
+ 1125 0028 00100240 		.word	1073876992
+ 1126              		.cfi_endproc
+ 1127              	.LFE338:
+ 1129              		.section	.bss.HAL_RCC_ADC12_CLK_ENABLED,"aw",%nobits
+ 1130              		.align	2
+ 1133              	HAL_RCC_ADC12_CLK_ENABLED:
+ 1134 0000 00000000 		.space	4
+ 1135              		.text
+ 1136              	.Letext0:
+ 1137              		.file 2 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 1138              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 1139              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 1140              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 1141              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"
+ 1142              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"
+ 1143              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 1144              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h"
+ 1145              		.file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h"
+ 1146              		.file 11 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"
+ 1147              		.file 12 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h"
+ 1148              		.file 13 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"
+ 1149              		.file 14 "Inc/main.h"
+ 1150              		.file 15 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"
+ 1151              		.file 16 "<built-in>"
+ARM GAS  /tmp/ccN6WdXz.s 			page 33
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_msp.c
+     /tmp/ccN6WdXz.s:21     .text.HAL_MspInit:00000000 $t
+     /tmp/ccN6WdXz.s:27     .text.HAL_MspInit:00000000 HAL_MspInit
+     /tmp/ccN6WdXz.s:83     .text.HAL_MspInit:00000034 $d
+     /tmp/ccN6WdXz.s:88     .text.HAL_ADC_MspInit:00000000 $t
+     /tmp/ccN6WdXz.s:94     .text.HAL_ADC_MspInit:00000000 HAL_ADC_MspInit
+     /tmp/ccN6WdXz.s:322    .text.HAL_ADC_MspInit:000000fc $d
+     /tmp/ccN6WdXz.s:1133   .bss.HAL_RCC_ADC12_CLK_ENABLED:00000000 HAL_RCC_ADC12_CLK_ENABLED
+     /tmp/ccN6WdXz.s:331    .text.HAL_ADC_MspDeInit:00000000 $t
+     /tmp/ccN6WdXz.s:337    .text.HAL_ADC_MspDeInit:00000000 HAL_ADC_MspDeInit
+     /tmp/ccN6WdXz.s:419    .text.HAL_ADC_MspDeInit:00000050 $d
+     /tmp/ccN6WdXz.s:427    .text.HAL_I2C_MspInit:00000000 $t
+     /tmp/ccN6WdXz.s:433    .text.HAL_I2C_MspInit:00000000 HAL_I2C_MspInit
+     /tmp/ccN6WdXz.s:607    .text.HAL_I2C_MspInit:000000a8 $d
+     /tmp/ccN6WdXz.s:614    .text.HAL_I2C_MspDeInit:00000000 $t
+     /tmp/ccN6WdXz.s:620    .text.HAL_I2C_MspDeInit:00000000 HAL_I2C_MspDeInit
+     /tmp/ccN6WdXz.s:668    .text.HAL_I2C_MspDeInit:0000002c $d
+     /tmp/ccN6WdXz.s:675    .text.HAL_TIM_Base_MspInit:00000000 $t
+     /tmp/ccN6WdXz.s:681    .text.HAL_TIM_Base_MspInit:00000000 HAL_TIM_Base_MspInit
+     /tmp/ccN6WdXz.s:771    .text.HAL_TIM_Base_MspInit:00000058 $d
+     /tmp/ccN6WdXz.s:777    .text.HAL_TIM_MspPostInit:00000000 $t
+     /tmp/ccN6WdXz.s:783    .text.HAL_TIM_MspPostInit:00000000 HAL_TIM_MspPostInit
+     /tmp/ccN6WdXz.s:868    .text.HAL_TIM_Base_MspDeInit:00000000 $t
+     /tmp/ccN6WdXz.s:874    .text.HAL_TIM_Base_MspDeInit:00000000 HAL_TIM_Base_MspDeInit
+     /tmp/ccN6WdXz.s:927    .text.HAL_TIM_Base_MspDeInit:00000034 $d
+     /tmp/ccN6WdXz.s:933    .text.HAL_UART_MspInit:00000000 $t
+     /tmp/ccN6WdXz.s:939    .text.HAL_UART_MspInit:00000000 HAL_UART_MspInit
+     /tmp/ccN6WdXz.s:1069   .text.HAL_UART_MspInit:00000080 $d
+     /tmp/ccN6WdXz.s:1075   .text.HAL_UART_MspDeInit:00000000 $t
+     /tmp/ccN6WdXz.s:1081   .text.HAL_UART_MspDeInit:00000000 HAL_UART_MspDeInit
+     /tmp/ccN6WdXz.s:1124   .text.HAL_UART_MspDeInit:00000024 $d
+     /tmp/ccN6WdXz.s:1130   .bss.HAL_RCC_ADC12_CLK_ENABLED:00000000 $d
+
+UNDEFINED SYMBOLS
+HAL_PWREx_DisableUCPDDeadBattery
+memset
+HAL_RCCEx_PeriphCLKConfig
+HAL_GPIO_Init
+Error_Handler
+HAL_GPIO_DeInit
+HAL_NVIC_SetPriority
+HAL_NVIC_EnableIRQ
+HAL_NVIC_DisableIRQ
diff --git a/squeow_sw/build/stm32g4xx_hal_msp.o b/squeow_sw/build/stm32g4xx_hal_msp.o
new file mode 100644
index 0000000000000000000000000000000000000000..4f9cea57eebc6d6d09546fb577bf3f769f5096e9
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diff --git a/squeow_sw/build/stm32g4xx_hal_pcd.d b/squeow_sw/build/stm32g4xx_hal_pcd.d
new file mode 100644
index 0000000..cca8447
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_pcd.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_pcd.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_pcd.lst b/squeow_sw/build/stm32g4xx_hal_pcd.lst
new file mode 100644
index 0000000..ab4f021
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_pcd.lst
@@ -0,0 +1,7846 @@
+ARM GAS  /tmp/ccJPteqL.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_pcd.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c"
+  20              		.section	.text.HAL_PCD_EP_DB_Receive,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	HAL_PCD_EP_DB_Receive:
+  27              	.LVL0:
+  28              	.LFB362:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @file    stm32g4xx_hal_pcd.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief   PCD HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          functionalities of the USB Peripheral Controller:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *           + IO operation functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *           + Peripheral Control functions
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *           + Peripheral State functions
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ******************************************************************************
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @attention
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * Copyright (c) 2019 STMicroelectronics.
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * All rights reserved.
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * in the root directory of this software component.
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ******************************************************************************
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   @verbatim
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ==============================================================================
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                     ##### How to use this driver #####
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ==============================================================================
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     [..]
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       The PCD HAL driver can be used as follows:
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 2
+
+
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****      (#) Declare a PCD_HandleTypeDef handle structure, for example:
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****          PCD_HandleTypeDef  hpcd;
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****      (#) Fill parameters of Init structure in HCD handle
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****      (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****          (##) Enable the PCD/USB Low Level interface clock using
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****          (##) Initialize the related GPIO clocks
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****          (##) Configure PCD pin-out
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****          (##) Configure PCD NVIC interrupt
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****      (#)Associate the Upper USB device stack to the HAL PCD Driver:
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****          (##) hpcd.pData = pdev;
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****      (#)Enable PCD transmission and reception:
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****          (##) HAL_PCD_Start();
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   @endverbatim
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ******************************************************************************
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /* Includes ------------------------------------------------------------------*/
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #include "stm32g4xx_hal.h"
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @{
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /** @defgroup PCD PCD
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief PCD HAL module driver
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @{
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #ifdef HAL_PCD_MODULE_ENABLED
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if defined (USB)
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /* Private types -------------------------------------------------------------*/
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /* Private variables ---------------------------------------------------------*/
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /* Private constants ---------------------------------------------------------*/
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /* Private macros ------------------------------------------------------------*/
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /** @defgroup PCD_Private_Macros PCD Private Macros
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @{
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @}
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /* Private functions prototypes ----------------------------------------------*/
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /** @defgroup PCD_Private_Functions PCD Private Functions
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @{
+ARM GAS  /tmp/ccJPteqL.s 			page 3
+
+
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_USB_DOUBLE_BUFFER == 1U)
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @}
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /* Exported functions --------------------------------------------------------*/
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /** @defgroup PCD_Exported_Functions PCD Exported Functions
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @{
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *  @brief    Initialization and Configuration functions
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** @verbatim
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****  ===============================================================================
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             ##### Initialization and de-initialization functions #####
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****  ===============================================================================
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     [..]  This section provides functions allowing to:
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** @endverbatim
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @{
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Initializes the PCD according to the specified
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         parameters in the PCD_InitTypeDef and initialize the associated handle.
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint8_t i;
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Check the PCD handle allocation */
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd == NULL)
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return HAL_ERROR;
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Check the parameters */
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_RESET)
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Allocate lock resource and initialize it */
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->Lock = HAL_UNLOCKED;
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->SOFCallback = HAL_PCD_SOFCallback;
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+ARM GAS  /tmp/ccJPteqL.s 			page 4
+
+
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ResetCallback = HAL_PCD_ResetCallback;
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (hpcd->MspInitCallback == NULL)
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->MspInitCallback = HAL_PCD_MspInit;
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Init the low level hardware */
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->MspInitCallback(hpcd);
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     HAL_PCD_MspInit(hpcd);
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->State = HAL_PCD_STATE_BUSY;
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Disable the Interrupts */
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_DISABLE(hpcd);
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Init endpoints structures */
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Init ep structure */
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].is_in = 1U;
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].num = i;
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].tx_fifo_num = i;
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Control until ep is activated */
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].type = EP_TYPE_CTRL;
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].maxpacket = 0U;
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].xfer_buff = 0U;
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].xfer_len = 0U;
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].is_in = 0U;
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].num = i;
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Control until ep is activated */
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].maxpacket = 0U;
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].xfer_buff = 0U;
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].xfer_len = 0U;
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Init Device */
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevInit(hpcd->Instance, hpcd->Init);
+ARM GAS  /tmp/ccJPteqL.s 			page 5
+
+
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->USB_Address = 0U;
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->State = HAL_PCD_STATE_READY;
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Activate LPM */
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->Init.lpm_enable == 1U)
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     (void)HAL_PCDEx_ActivateLPM(hpcd);
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  DeInitializes the PCD peripheral.
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Check the PCD handle allocation */
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd == NULL)
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return HAL_ERROR;
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->State = HAL_PCD_STATE_BUSY;
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Stop Device */
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (USB_StopDevice(hpcd->Instance) != HAL_OK)
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return HAL_ERROR;
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->MspDeInitCallback == NULL)
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* DeInit the low level hardware */
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->MspDeInitCallback(hpcd);
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* DeInit the low level hardware: CLOCK, NVIC.*/
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_PCD_MspDeInit(hpcd);
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->State = HAL_PCD_STATE_RESET;
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Initializes the PCD MSP.
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ARM GAS  /tmp/ccJPteqL.s 			page 6
+
+
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_MspInit could be implemented in the user file
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  DeInitializes PCD MSP.
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_MspDeInit could be implemented in the user file
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Register a User USB PCD Callback
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         To be used instead of the weak predefined callback
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd USB PCD handle
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  CallbackID ID of the callback to be registered
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         This parameter can be one of the following values:
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  pCallback pointer to the Callback function
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                                            HAL_PCD_CallbackIDTypeDef CallbackID,
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                                            pPCD_CallbackTypeDef pCallback)
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (pCallback == NULL)
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return HAL_ERROR;
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ARM GAS  /tmp/ccJPteqL.s 			page 7
+
+
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     switch (CallbackID)
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_SOF_CB_ID :
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->SOFCallback = pCallback;
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_SETUPSTAGE_CB_ID :
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->SetupStageCallback = pCallback;
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_RESET_CB_ID :
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->ResetCallback = pCallback;
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_SUSPEND_CB_ID :
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->SuspendCallback = pCallback;
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_RESUME_CB_ID :
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->ResumeCallback = pCallback;
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_CONNECT_CB_ID :
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->ConnectCallback = pCallback;
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_DISCONNECT_CB_ID :
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->DisconnectCallback = pCallback;
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_MSPINIT_CB_ID :
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->MspInitCallback = pCallback;
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_MSPDEINIT_CB_ID :
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->MspDeInitCallback = pCallback;
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       default :
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Update the error code */
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Return error status */
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         status =  HAL_ERROR;
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else if (hpcd->State == HAL_PCD_STATE_RESET)
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     switch (CallbackID)
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_MSPINIT_CB_ID :
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->MspInitCallback = pCallback;
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ARM GAS  /tmp/ccJPteqL.s 			page 8
+
+
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_MSPDEINIT_CB_ID :
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->MspDeInitCallback = pCallback;
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       default :
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Update the error code */
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Return error status */
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         status =  HAL_ERROR;
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Unregister an USB PCD Callback
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         USB PCD callabck is redirected to the weak predefined callback
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd USB PCD handle
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  CallbackID ID of the callback to be unregistered
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         This parameter can be one of the following values:
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef Cal
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Setup Legacy weak Callbacks  */
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     switch (CallbackID)
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_SOF_CB_ID :
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->SOFCallback = HAL_PCD_SOFCallback;
+ARM GAS  /tmp/ccJPteqL.s 			page 9
+
+
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_SETUPSTAGE_CB_ID :
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_RESET_CB_ID :
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->ResetCallback = HAL_PCD_ResetCallback;
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_SUSPEND_CB_ID :
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_RESUME_CB_ID :
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_CONNECT_CB_ID :
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_DISCONNECT_CB_ID :
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_MSPINIT_CB_ID :
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->MspInitCallback = HAL_PCD_MspInit;
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_MSPDEINIT_CB_ID :
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       default :
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Update the error code */
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Return error status */
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         status =  HAL_ERROR;
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else if (hpcd->State == HAL_PCD_STATE_RESET)
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     switch (CallbackID)
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_MSPINIT_CB_ID :
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->MspInitCallback = HAL_PCD_MspInit;
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       case HAL_PCD_MSPDEINIT_CB_ID :
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       default :
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Update the error code */
+ARM GAS  /tmp/ccJPteqL.s 			page 10
+
+
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Return error status */
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         status =  HAL_ERROR;
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         break;
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Register USB PCD Data OUT Stage Callback
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                                                        pPCD_DataOutStageCallbackTypeDef pCallback)
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (pCallback == NULL)
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return HAL_ERROR;
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->DataOutStageCallback = pCallback;
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 11
+
+
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Unregister the USB PCD Data OUT Stage Callback
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback(
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback 
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Register USB PCD Data IN Stage Callback
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  pCallback pointer to the USB PCD Data IN Stage Callback function
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                                                       pPCD_DataInStageCallbackTypeDef pCallback)
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (pCallback == NULL)
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return HAL_ERROR;
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ARM GAS  /tmp/ccJPteqL.s 			page 12
+
+
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->DataInStageCallback = pCallback;
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Unregister the USB PCD Data IN Stage Callback
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback()
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Register USB PCD Iso OUT incomplete Callback
+ARM GAS  /tmp/ccJPteqL.s 			page 13
+
+
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                                                        pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (pCallback == NULL)
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return HAL_ERROR;
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ISOOUTIncompleteCallback = pCallback;
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Unregister the USB PCD Iso OUT incomplete Callback
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         USB PCD Iso OUT incomplete Callback is redirected
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompl
+ARM GAS  /tmp/ccJPteqL.s 			page 14
+
+
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Register USB PCD Iso IN incomplete Callback
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                                                       pPCD_IsoInIncpltCallbackTypeDef pCallback)
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (pCallback == NULL)
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return HAL_ERROR;
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ISOINIncompleteCallback = pCallback;
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ARM GAS  /tmp/ccJPteqL.s 			page 15
+
+
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Unregister the USB PCD Iso IN incomplete Callback
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         USB PCD Iso IN incomplete Callback is redirected
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncomplete
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Register USB PCD BCD Callback
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  pCallback pointer to the USB PCD BCD Callback function
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCal
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (pCallback == NULL)
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return HAL_ERROR;
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ARM GAS  /tmp/ccJPteqL.s 			page 16
+
+
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->BCDCallback = pCallback;
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Unregister the USB PCD BCD Callback
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Register USB PCD LPM Callback
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  pCallback pointer to the USB PCD LPM Callback function
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ARM GAS  /tmp/ccJPteqL.s 			page 17
+
+
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCal
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (pCallback == NULL)
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return HAL_ERROR;
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->LPMCallback = pCallback;
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Unregister the USB PCD LPM Callback
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Process locked */
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (hpcd->State == HAL_PCD_STATE_READY)
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Update the error code */
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Return error status */
+ARM GAS  /tmp/ccJPteqL.s 			page 18
+
+
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     status =  HAL_ERROR;
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Release Lock */
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return status;
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @}
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *  @brief   Data transfers functions
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** @verbatim
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****  ===============================================================================
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                       ##### IO operation functions #####
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****  ===============================================================================
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     [..]
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     This subsection provides a set of functions allowing to manage the PCD data
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     transfers.
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** @endverbatim
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @{
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Start the USB device
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_ENABLE(hpcd);
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevConnect(hpcd->Instance);
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Stop the USB device.
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_DISABLE(hpcd);
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevDisconnect(hpcd->Instance);
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+ARM GAS  /tmp/ccJPteqL.s 			page 19
+
+
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  This function handles PCD interrupt request.
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
+1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* servicing of the endpoint correct transfer interrupt */
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* clear of the CTR flag into the sub */
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     (void)PCD_EP_ISR_Handler(hpcd);
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return;
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ResetCallback(hpcd);
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     HAL_PCD_ResetCallback(hpcd);
+1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     (void)HAL_PCD_SetAddress(hpcd, 0U);
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return;
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return;
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return;
+1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (hpcd->LPM_State == LPM_L1)
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ARM GAS  /tmp/ccJPteqL.s 			page 20
+
+
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->LPM_State = LPM_L0;
+1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->ResumeCallback(hpcd);
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     HAL_PCD_ResumeCallback(hpcd);
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return;
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Force low-power mode in the macrocell */
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->SuspendCallback(hpcd);
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     HAL_PCD_SuspendCallback(hpcd);
+1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return;
+1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Handle LPM Interrupt */
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ)
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (hpcd->LPM_State == LPM_L0)
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* Force suspend and low-power mode before going to L1 state*/
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->LPM_State = LPM_L1;
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
+1107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+1111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+1113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     else
+ARM GAS  /tmp/ccJPteqL.s 			page 21
+
+
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->SuspendCallback(hpcd);
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       HAL_PCD_SuspendCallback(hpcd);
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return;
+1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
+1126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->SOFCallback(hpcd);
+1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     HAL_PCD_SOFCallback(hpcd);
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return;
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
+1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* clear ESOF flag in ISTR */
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return;
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Data OUT stage callback.
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  epnum endpoint number
+1152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+1153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(epnum);
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_DataOutStageCallback could be implemented in the user file
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Data IN stage callback
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  epnum endpoint number
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+ARM GAS  /tmp/ccJPteqL.s 			page 22
+
+
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(epnum);
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_DataInStageCallback could be implemented in the user file
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Setup stage callback
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+1189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_SetupStageCallback could be implemented in the user file
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+1194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  USB Start Of Frame callback.
+1198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_SOFCallback could be implemented in the user file
+1208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  USB Reset callback.
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+1219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_ResetCallback could be implemented in the user file
+1223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Suspend event callback.
+ARM GAS  /tmp/ccJPteqL.s 			page 23
+
+
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_SuspendCallback could be implemented in the user file
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Resume event callback.
+1243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_ResumeCallback could be implemented in the user file
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Incomplete ISO OUT callback.
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  epnum endpoint number
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(epnum);
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
+1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Incomplete ISO IN callback.
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  epnum endpoint number
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+1280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(epnum);
+1284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 24
+
+
+1285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+1288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Connection event callback.
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_ConnectCallback could be implemented in the user file
+1302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Disconnection event callback.
+1307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval None
+1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             the HAL_PCD_DisconnectCallback could be implemented in the user file
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****    */
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @}
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+1325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *  @brief   management functions
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** @verbatim
+1328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****  ===============================================================================
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                       ##### Peripheral Control functions #####
+1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****  ===============================================================================
+1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     [..]
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     This subsection provides a set of functions allowing to control the PCD data
+1333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     transfers.
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** @endverbatim
+1336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @{
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Connect the USB device
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+ARM GAS  /tmp/ccJPteqL.s 			page 25
+
+
+1342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevConnect(hpcd->Instance);
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Disconnect the USB device.
+1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevDisconnect(hpcd->Instance);
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Set the USB Device address.
+1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  address new device address
+1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->USB_Address = address;
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_SetDevAddress(hpcd->Instance, address);
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Open and configure an endpoint.
+1384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  ep_addr endpoint address
+1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  ep_mps endpoint max packet size
+1387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  ep_type endpoint type
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                                   uint16_t ep_mps, uint8_t ep_type)
+1392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef  ret = HAL_OK;
+1394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((ep_addr & 0x80U) == 0x80U)
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ARM GAS  /tmp/ccJPteqL.s 			page 26
+
+
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+1400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+1405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->maxpacket = ep_mps;
+1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->type = ep_type;
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (ep->is_in != 0U)
+1412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Assign a Tx FIFO */
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->tx_fifo_num = ep->num;
+1415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Set initial data PID. */
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (ep_type == EP_TYPE_BULK)
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->data_pid_start = 0U;
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return ret;
+1427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Deactivate an endpoint.
+1431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  ep_addr endpoint address
+1433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+1436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((ep_addr & 0x80U) == 0x80U)
+1440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+1445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+1448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num   = ep_addr & EP_ADDR_MSK;
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+1453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+1454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ARM GAS  /tmp/ccJPteqL.s 			page 27
+
+
+1456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Receive an amount of data.
+1460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  ep_addr endpoint address
+1462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  pBuf pointer to the reception buffer
+1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  len amount of data to be received
+1464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint3
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+1469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /*setup and start the Xfer */
+1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_buff = pBuf;
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_len = len;
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_count = 0U;
+1476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->is_in = 0U;
+1477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((ep_addr & EP_ADDR_MSK) == 0U)
+1480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     (void)USB_EP0StartXfer(hpcd->Instance, ep);
+1482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+1484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     (void)USB_EPStartXfer(hpcd->Instance, ep);
+1486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+1489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Get Received Data Size
+1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  ep_addr endpoint address
+1495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval Data Size
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+1498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Send an amount of data
+1503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  ep_addr endpoint address
+1505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  pBuf pointer to the transmission buffer
+1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  len amount of data to be sent
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+1512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 28
+
+
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /*setup and start the Xfer */
+1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_buff = pBuf;
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_len = len;
+1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_fill_db = 1U;
+1519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_len_db = len;
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_count = 0U;
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->is_in = 1U;
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+1523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((ep_addr & EP_ADDR_MSK) == 0U)
+1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     (void)USB_EP0StartXfer(hpcd->Instance, ep);
+1527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     (void)USB_EPStartXfer(hpcd->Instance, ep);
+1531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Set a STALL condition over an endpoint
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  ep_addr endpoint address
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
+1547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return HAL_ERROR;
+1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((0x80U & ep_addr) == 0x80U)
+1552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+1555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep = &hpcd->OUT_ep[ep_addr];
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+1560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->is_stall = 1U;
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_EPSetStall(hpcd->Instance, ep);
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ARM GAS  /tmp/ccJPteqL.s 			page 29
+
+
+1570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Clear a STALL condition over in an endpoint
+1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  ep_addr endpoint address
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+1581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     return HAL_ERROR;
+1587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((0x80U & ep_addr) == 0x80U)
+1590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+1593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+1595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+1598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->is_stall = 0U;
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+1602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_EPClearStall(hpcd->Instance, ep);
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+1606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+1608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Flush an endpoint
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  ep_addr endpoint address
+1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(hpcd);
+1620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(ep_addr);
+1621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Activate remote wakeup signalling
+ARM GAS  /tmp/ccJPteqL.s 			page 30
+
+
+1627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return (USB_ActivateRemoteWakeup(hpcd->Instance));
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  De-activate remote wakeup signalling.
+1637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return (USB_DeActivateRemoteWakeup(hpcd->Instance));
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @}
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *  @brief   Peripheral State functions
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   *
+1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** @verbatim
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****  ===============================================================================
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                       ##### Peripheral State functions #####
+1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****  ===============================================================================
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     [..]
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     This subsection permits to get in run-time the status of the peripheral
+1658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     and the data flow.
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** @endverbatim
+1661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @{
+1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Return the PCD handle state.
+1666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL state
+1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+1670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return hpcd->State;
+1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @}
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @}
+1680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /* Private functions ---------------------------------------------------------*/
+1683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /** @addtogroup PCD_Private_Functions
+ARM GAS  /tmp/ccJPteqL.s 			page 31
+
+
+1684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @{
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  This function handles PCD Endpoint interrupt request.
+1690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
+1694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint16_t count;
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint16_t wIstr;
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint16_t wEPVal;
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint16_t TxPctSize;
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint8_t epindex;
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* stay in loop while pending interrupts */
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
+1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     wIstr = hpcd->Instance->ISTR;
+1706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* extract highest priority endpoint number */
+1708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (epindex == 0U)
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* Decode and service control endpoint interrupt */
+1713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* DIR bit = origin of the interrupt */
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       if ((wIstr & USB_ISTR_DIR) == 0U)
+1716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* DIR = 0 */
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* DIR = 0 => IN  int */
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* DIR = 0 implies that (EP_CTR_TX = 1) always */
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->IN_ep[0];
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_buff += ep->xfer_count;
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* TX COMPLETE */
+1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         hpcd->DataInStageCallback(hpcd, 0U);
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         HAL_PCD_DataInStageCallback(hpcd, 0U);
+1732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
+1735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           hpcd->USB_Address = 0U;
+1738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+1740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       else
+ARM GAS  /tmp/ccJPteqL.s 			page 32
+
+
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* DIR = 1 */
+1743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* DIR = 1 & CTR_RX => SETUP or OUT int */
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->OUT_ep[0];
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+1748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         if ((wEPVal & USB_EP_SETUP) != 0U)
+1750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+1751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           /* Get SETUP Packet */
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                       ep->pmaadress, (uint16_t)ep->xfer_count);
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           /* SETUP bit kept frozen while CTR_RX = 1 */
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           /* Process SETUP Packet*/
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           hpcd->SetupStageCallback(hpcd);
+1763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           HAL_PCD_SetupStageCallback(hpcd);
+1765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         else if ((wEPVal & USB_EP_CTR_RX) != 0U)
+1768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+1770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           /* Get Control Data OUT Packet */
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                         ep->pmaadress, (uint16_t)ep->xfer_count);
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             ep->xfer_buff += ep->xfer_count;
+1780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             /* Process Control Data OUT Packet */
+1782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             hpcd->DataOutStageCallback(hpcd, 0U);
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             HAL_PCD_DataOutStageCallback(hpcd, 0U);
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U)
+1790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+1794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+1796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+1797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     else
+ARM GAS  /tmp/ccJPteqL.s 			page 33
+
+
+1798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+1799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* Decode and service non control endpoints interrupt */
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* process related endpoint register */
+1801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
+1802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       if ((wEPVal & USB_EP_CTR_RX) != 0U)
+1804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+1805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* clear int flag */
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->OUT_ep[epindex];
+1808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* OUT Single Buffering */
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         if (ep->doublebuffer == 0U)
+1811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+1812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+1813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           if (count != 0U)
+1815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
+1817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+1818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+1819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_USB_DOUBLE_BUFFER == 1U)
+1820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         else
+1821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           /* manage double buffer bulk out */
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           if (ep->type == EP_TYPE_BULK)
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
+1826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+1827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           else /* manage double buffer iso out */
+1828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+1829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             /* free EP OUT Buffer */
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
+1831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
+1833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               /* read from endpoint BUF0Addr buffer */
+1835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               if (count != 0U)
+1838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               {
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                 USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               }
+1841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             else
+1843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+1844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               /* read from endpoint BUF1Addr buffer */
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+1846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               if (count != 0U)
+1848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               {
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                 USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+1850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               }
+1851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+1852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+1854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+ARM GAS  /tmp/ccJPteqL.s 			page 34
+
+
+1855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* multi-packet on the NON control OUT endpoint */
+1857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_count += count;
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_buff += count;
+1859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
+1861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+1862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           /* RX COMPLETE */
+1863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           hpcd->DataOutStageCallback(hpcd, ep->num);
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           HAL_PCD_DataOutStageCallback(hpcd, ep->num);
+1867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+1869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         else
+1870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+1871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           (void) USB_EPStartXfer(hpcd->Instance, ep);
+1872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+1873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+1874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       if ((wEPVal & USB_EP_CTR_TX) != 0U)
+1876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->IN_ep[epindex];
+1878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* clear int flag */
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
+1881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         if (ep->type != EP_TYPE_BULK)
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+1884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_len = 0U;
+1885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_USB_DOUBLE_BUFFER == 1U)
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           if (ep->doublebuffer != 0U)
+1888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+1889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+1890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+1892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+1893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             else
+1894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+1896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+1897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+1898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+1899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           /* TX COMPLETE */
+1901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           hpcd->DataInStageCallback(hpcd, ep->num);
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           HAL_PCD_DataInStageCallback(hpcd, ep->num);
+1905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+1907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         else
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+1909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           /* Manage Bulk Single Buffer Transaction */
+1910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           if ((wEPVal & USB_EP_KIND) == 0U)
+1911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ARM GAS  /tmp/ccJPteqL.s 			page 35
+
+
+1912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             /* multi-packet on the NON control IN endpoint */
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+1914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             if (ep->xfer_len > TxPctSize)
+1916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+1917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               ep->xfer_len -= TxPctSize;
+1918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+1919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             else
+1920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+1921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               ep->xfer_len = 0U;
+1922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             /* Zero Length Packet? */
+1925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             if (ep->xfer_len == 0U)
+1926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+1927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               /* TX COMPLETE */
+1928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+1929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               hpcd->DataInStageCallback(hpcd, ep->num);
+1930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               HAL_PCD_DataInStageCallback(hpcd, ep->num);
+1932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+1933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             else
+1935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+1936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               /* Transfer is not yet Done */
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               ep->xfer_buff += TxPctSize;
+1938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               ep->xfer_count += TxPctSize;
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               (void)USB_EPStartXfer(hpcd->Instance, ep);
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+1941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+1942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_USB_DOUBLE_BUFFER == 1U)
+1943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
+1944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           else
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
+1947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+1949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+1950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+1952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+1953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+1956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_USB_DOUBLE_BUFFER == 1U)
+1959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+1960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Manage double buffer bulk out transaction from ISR
+1961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+1962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  ep current endpoint handle
+1963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  wEPVal Last snapshot of EPRx register value taken in ISR
+1964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+1965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+1966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
+1967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                                       PCD_EPTypeDef *ep, uint16_t wEPVal)
+1968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ARM GAS  /tmp/ccJPteqL.s 			page 36
+
+
+  29              		.loc 1 1968 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		.loc 1 1968 1 is_stmt 0 view .LVU1
+  34 0000 38B5     		push	{r3, r4, r5, lr}
+  35              	.LCFI0:
+  36              		.cfi_def_cfa_offset 16
+  37              		.cfi_offset 3, -16
+  38              		.cfi_offset 4, -12
+  39              		.cfi_offset 5, -8
+  40              		.cfi_offset 14, -4
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint16_t count;
+  41              		.loc 1 1969 3 is_stmt 1 view .LVU2
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Manage Buffer0 OUT */
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((wEPVal & USB_EP_DTOG_RX) != 0U)
+  42              		.loc 1 1972 3 view .LVU3
+  43              		.loc 1 1972 6 is_stmt 0 view .LVU4
+  44 0002 12F4804F 		tst	r2, #16384
+  45 0006 43D0     		beq	.L2
+1973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+1974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Get count of received Data on buffer0 */
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+  46              		.loc 1 1975 5 is_stmt 1 view .LVU5
+  47              		.loc 1 1975 23 is_stmt 0 view .LVU6
+  48 0008 0468     		ldr	r4, [r0]
+  49 000a B4F85030 		ldrh	r3, [r4, #80]
+  50 000e 91F800C0 		ldrb	ip, [r1]	@ zero_extendqisi2
+  51 0012 4FEACC0E 		lsl	lr, ip, #3
+  52 0016 1EFA83F3 		uxtah	r3, lr, r3
+  53 001a 2344     		add	r3, r3, r4
+  54 001c B3F80244 		ldrh	r4, [r3, #1026]
+  55              		.loc 1 1975 11 view .LVU7
+  56 0020 C4F30904 		ubfx	r4, r4, #0, #10
+  57              	.LVL1:
+1976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (ep->xfer_len >= count)
+  58              		.loc 1 1977 5 is_stmt 1 view .LVU8
+  59              		.loc 1 1977 11 is_stmt 0 view .LVU9
+  60 0024 8B69     		ldr	r3, [r1, #24]
+  61              		.loc 1 1977 8 view .LVU10
+  62 0026 A342     		cmp	r3, r4
+  63 0028 28D3     		bcc	.L3
+1978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+1979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       ep->xfer_len -= count;
+  64              		.loc 1 1979 7 is_stmt 1 view .LVU11
+  65              		.loc 1 1979 20 is_stmt 0 view .LVU12
+  66 002a 1B1B     		subs	r3, r3, r4
+  67 002c 8B61     		str	r3, [r1, #24]
+  68              	.L4:
+1980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+1981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     else
+1982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+1983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       ep->xfer_len = 0U;
+1984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+1985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 37
+
+
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (ep->xfer_len == 0U)
+  69              		.loc 1 1986 5 is_stmt 1 view .LVU13
+  70              		.loc 1 1986 11 is_stmt 0 view .LVU14
+  71 002e 8B69     		ldr	r3, [r1, #24]
+  72              		.loc 1 1986 8 view .LVU15
+  73 0030 7BB9     		cbnz	r3, .L5
+1987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+1988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* set NAK to OUT endpoint since double buffer is enabled */
+1989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
+  74              		.loc 1 1989 7 is_stmt 1 view .LVU16
+  75              	.LBB2:
+  76              		.loc 1 1989 7 view .LVU17
+  77              		.loc 1 1989 7 view .LVU18
+  78 0032 0568     		ldr	r5, [r0]
+  79 0034 35F82C30 		ldrh	r3, [r5, ip, lsl #2]
+  80 0038 9BB2     		uxth	r3, r3
+  81 003a 23F48043 		bic	r3, r3, #16384
+  82 003e 23F07003 		bic	r3, r3, #112
+  83              	.LVL2:
+  84              		.loc 1 1989 7 view .LVU19
+  85              		.loc 1 1989 7 view .LVU20
+  86              		.loc 1 1989 7 view .LVU21
+  87 0042 83F40053 		eor	r3, r3, #8192
+  88              	.LVL3:
+  89              		.loc 1 1989 7 view .LVU22
+  90 0046 43F40043 		orr	r3, r3, #32768
+  91              	.LVL4:
+  92              		.loc 1 1989 7 is_stmt 0 view .LVU23
+  93 004a 43F08003 		orr	r3, r3, #128
+  94 004e 25F82C30 		strh	r3, [r5, ip, lsl #2]	@ movhi
+  95              	.LVL5:
+  96              	.L5:
+  97              		.loc 1 1989 7 view .LVU24
+  98              	.LBE2:
+  99              		.loc 1 1989 7 is_stmt 1 discriminator 7 view .LVU25
+1990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+1991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Check if Buffer1 is in blocked state which requires to toggle */
+1993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+ 100              		.loc 1 1993 5 discriminator 7 view .LVU26
+ 101              		.loc 1 1993 8 is_stmt 0 discriminator 7 view .LVU27
+ 102 0052 12F0400F 		tst	r2, #64
+ 103 0056 0ED0     		beq	.L6
+1994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+1995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
+ 104              		.loc 1 1995 7 is_stmt 1 discriminator 1 view .LVU28
+ 105              		.loc 1 1995 7 discriminator 1 view .LVU29
+ 106              		.loc 1 1995 7 discriminator 1 view .LVU30
+ 107              	.LBB3:
+ 108              		.loc 1 1995 7 discriminator 1 view .LVU31
+ 109              		.loc 1 1995 7 discriminator 1 view .LVU32
+ 110 0058 0268     		ldr	r2, [r0]
+ 111              	.LVL6:
+ 112              		.loc 1 1995 7 is_stmt 0 discriminator 1 view .LVU33
+ 113 005a 0D78     		ldrb	r5, [r1]	@ zero_extendqisi2
+ 114 005c 32F82530 		ldrh	r3, [r2, r5, lsl #2]
+ 115 0060 9BB2     		uxth	r3, r3
+ARM GAS  /tmp/ccJPteqL.s 			page 38
+
+
+ 116 0062 23F4E043 		bic	r3, r3, #28672
+ 117 0066 23F07003 		bic	r3, r3, #112
+ 118              	.LVL7:
+ 119              		.loc 1 1995 7 is_stmt 1 discriminator 1 view .LVU34
+ 120 006a 43F40043 		orr	r3, r3, #32768
+ 121              	.LVL8:
+ 122              		.loc 1 1995 7 is_stmt 0 discriminator 1 view .LVU35
+ 123 006e 43F0C003 		orr	r3, r3, #192
+ 124 0072 22F82530 		strh	r3, [r2, r5, lsl #2]	@ movhi
+ 125              	.LBE3:
+ 126              		.loc 1 1995 7 is_stmt 1 discriminator 1 view .LVU36
+ 127              	.LVL9:
+ 128              	.L6:
+ 129              		.loc 1 1995 7 discriminator 6 view .LVU37
+ 130              		.loc 1 1995 7 discriminator 6 view .LVU38
+1996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+1997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+1998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (count != 0U)
+ 131              		.loc 1 1998 5 discriminator 6 view .LVU39
+ 132              		.loc 1 1998 8 is_stmt 0 discriminator 6 view .LVU40
+ 133 0076 24B9     		cbnz	r4, .L13
+ 134              	.LVL10:
+ 135              	.L7:
+1999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+2001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+2003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Manage Buffer 1 DTOG_RX=0 */
+2004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else
+2005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+2006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Get count of received data */
+2007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+2008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (ep->xfer_len >= count)
+2010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       ep->xfer_len -= count;
+2012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     else
+2014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       ep->xfer_len = 0U;
+2016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (ep->xfer_len == 0U)
+2019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* set NAK on the current endpoint */
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
+2022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /*Need to FreeUser Buffer*/
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if ((wEPVal & USB_EP_DTOG_TX) == 0U)
+2026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
+2028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (count != 0U)
+2031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+ARM GAS  /tmp/ccJPteqL.s 			page 39
+
+
+2033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+2035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return count;
+ 136              		.loc 1 2036 3 is_stmt 1 view .LVU41
+2037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 137              		.loc 1 2037 1 is_stmt 0 view .LVU42
+ 138 0078 2046     		mov	r0, r4
+ 139 007a 38BD     		pop	{r3, r4, r5, pc}
+ 140              	.LVL11:
+ 141              	.L3:
+1983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 142              		.loc 1 1983 7 is_stmt 1 view .LVU43
+1983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 143              		.loc 1 1983 20 is_stmt 0 view .LVU44
+ 144 007c 0023     		movs	r3, #0
+ 145 007e 8B61     		str	r3, [r1, #24]
+ 146 0080 D5E7     		b	.L4
+ 147              	.LVL12:
+ 148              	.L13:
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 149              		.loc 1 2000 7 is_stmt 1 view .LVU45
+ 150 0082 2346     		mov	r3, r4
+ 151 0084 0A89     		ldrh	r2, [r1, #8]
+ 152 0086 4969     		ldr	r1, [r1, #20]
+ 153              	.LVL13:
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 154              		.loc 1 2000 7 is_stmt 0 view .LVU46
+ 155 0088 0068     		ldr	r0, [r0]
+ 156              	.LVL14:
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 157              		.loc 1 2000 7 view .LVU47
+ 158 008a FFF7FEFF 		bl	USB_ReadPMA
+ 159              	.LVL15:
+ 160 008e F3E7     		b	.L7
+ 161              	.LVL16:
+ 162              	.L2:
+2007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 163              		.loc 1 2007 5 is_stmt 1 view .LVU48
+2007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 164              		.loc 1 2007 23 is_stmt 0 view .LVU49
+ 165 0090 0468     		ldr	r4, [r0]
+ 166 0092 B4F85030 		ldrh	r3, [r4, #80]
+ 167 0096 91F800C0 		ldrb	ip, [r1]	@ zero_extendqisi2
+ 168 009a 4FEACC0E 		lsl	lr, ip, #3
+ 169 009e 1EFA83F3 		uxtah	r3, lr, r3
+ 170 00a2 2344     		add	r3, r3, r4
+ 171 00a4 B3F80644 		ldrh	r4, [r3, #1030]
+2007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 172              		.loc 1 2007 11 view .LVU50
+ 173 00a8 C4F30904 		ubfx	r4, r4, #0, #10
+ 174              	.LVL17:
+2009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 175              		.loc 1 2009 5 is_stmt 1 view .LVU51
+2009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 176              		.loc 1 2009 11 is_stmt 0 view .LVU52
+ 177 00ac 8B69     		ldr	r3, [r1, #24]
+ARM GAS  /tmp/ccJPteqL.s 			page 40
+
+
+2009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 178              		.loc 1 2009 8 view .LVU53
+ 179 00ae A342     		cmp	r3, r4
+ 180 00b0 2FD3     		bcc	.L8
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 181              		.loc 1 2011 7 is_stmt 1 view .LVU54
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 182              		.loc 1 2011 20 is_stmt 0 view .LVU55
+ 183 00b2 1B1B     		subs	r3, r3, r4
+ 184 00b4 8B61     		str	r3, [r1, #24]
+ 185              	.L9:
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 186              		.loc 1 2018 5 is_stmt 1 view .LVU56
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 187              		.loc 1 2018 11 is_stmt 0 view .LVU57
+ 188 00b6 8B69     		ldr	r3, [r1, #24]
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 189              		.loc 1 2018 8 view .LVU58
+ 190 00b8 7BB9     		cbnz	r3, .L10
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 191              		.loc 1 2021 7 is_stmt 1 view .LVU59
+ 192              	.LBB4:
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 193              		.loc 1 2021 7 view .LVU60
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 194              		.loc 1 2021 7 view .LVU61
+ 195 00ba 0568     		ldr	r5, [r0]
+ 196 00bc 35F82C30 		ldrh	r3, [r5, ip, lsl #2]
+ 197 00c0 9BB2     		uxth	r3, r3
+ 198 00c2 23F48043 		bic	r3, r3, #16384
+ 199 00c6 23F07003 		bic	r3, r3, #112
+ 200              	.LVL18:
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 201              		.loc 1 2021 7 view .LVU62
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 202              		.loc 1 2021 7 view .LVU63
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 203              		.loc 1 2021 7 view .LVU64
+ 204 00ca 83F40053 		eor	r3, r3, #8192
+ 205              	.LVL19:
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 206              		.loc 1 2021 7 view .LVU65
+ 207 00ce 43F40043 		orr	r3, r3, #32768
+ 208              	.LVL20:
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 209              		.loc 1 2021 7 is_stmt 0 view .LVU66
+ 210 00d2 43F08003 		orr	r3, r3, #128
+ 211 00d6 25F82C30 		strh	r3, [r5, ip, lsl #2]	@ movhi
+ 212              	.LVL21:
+ 213              	.L10:
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 214              		.loc 1 2021 7 view .LVU67
+ 215              	.LBE4:
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 216              		.loc 1 2021 7 is_stmt 1 discriminator 7 view .LVU68
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 217              		.loc 1 2025 5 discriminator 7 view .LVU69
+ARM GAS  /tmp/ccJPteqL.s 			page 41
+
+
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 218              		.loc 1 2025 8 is_stmt 0 discriminator 7 view .LVU70
+ 219 00da 12F0400F 		tst	r2, #64
+ 220 00de 0FD1     		bne	.L11
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 221              		.loc 1 2027 7 is_stmt 1 discriminator 1 view .LVU71
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 222              		.loc 1 2027 7 discriminator 1 view .LVU72
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 223              		.loc 1 2027 7 discriminator 1 view .LVU73
+ 224              	.LBB5:
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 225              		.loc 1 2027 7 discriminator 1 view .LVU74
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 226              		.loc 1 2027 7 discriminator 1 view .LVU75
+ 227 00e0 0268     		ldr	r2, [r0]
+ 228              	.LVL22:
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 229              		.loc 1 2027 7 is_stmt 0 discriminator 1 view .LVU76
+ 230 00e2 91F800C0 		ldrb	ip, [r1]	@ zero_extendqisi2
+ 231 00e6 32F82C30 		ldrh	r3, [r2, ip, lsl #2]
+ 232 00ea 9BB2     		uxth	r3, r3
+ 233 00ec 23F4E043 		bic	r3, r3, #28672
+ 234 00f0 23F07003 		bic	r3, r3, #112
+ 235              	.LVL23:
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 236              		.loc 1 2027 7 is_stmt 1 discriminator 1 view .LVU77
+ 237 00f4 43F40043 		orr	r3, r3, #32768
+ 238              	.LVL24:
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 239              		.loc 1 2027 7 is_stmt 0 discriminator 1 view .LVU78
+ 240 00f8 43F0C003 		orr	r3, r3, #192
+ 241 00fc 22F82C30 		strh	r3, [r2, ip, lsl #2]	@ movhi
+ 242              	.LBE5:
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 243              		.loc 1 2027 7 is_stmt 1 discriminator 1 view .LVU79
+ 244              	.LVL25:
+ 245              	.L11:
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 246              		.loc 1 2027 7 discriminator 6 view .LVU80
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 247              		.loc 1 2027 7 discriminator 6 view .LVU81
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 248              		.loc 1 2030 5 discriminator 6 view .LVU82
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 249              		.loc 1 2030 8 is_stmt 0 discriminator 6 view .LVU83
+ 250 0100 002C     		cmp	r4, #0
+ 251 0102 B9D0     		beq	.L7
+2032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 252              		.loc 1 2032 7 is_stmt 1 view .LVU84
+ 253 0104 2346     		mov	r3, r4
+ 254 0106 4A89     		ldrh	r2, [r1, #10]
+ 255 0108 4969     		ldr	r1, [r1, #20]
+ 256              	.LVL26:
+2032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 257              		.loc 1 2032 7 is_stmt 0 view .LVU85
+ 258 010a 0068     		ldr	r0, [r0]
+ARM GAS  /tmp/ccJPteqL.s 			page 42
+
+
+ 259              	.LVL27:
+2032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 260              		.loc 1 2032 7 view .LVU86
+ 261 010c FFF7FEFF 		bl	USB_ReadPMA
+ 262              	.LVL28:
+ 263 0110 B2E7     		b	.L7
+ 264              	.LVL29:
+ 265              	.L8:
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 266              		.loc 1 2015 7 is_stmt 1 view .LVU87
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 267              		.loc 1 2015 20 is_stmt 0 view .LVU88
+ 268 0112 0023     		movs	r3, #0
+ 269 0114 8B61     		str	r3, [r1, #24]
+ 270 0116 CEE7     		b	.L9
+ 271              		.cfi_endproc
+ 272              	.LFE362:
+ 274              		.section	.text.HAL_PCD_MspInit,"ax",%progbits
+ 275              		.align	1
+ 276              		.weak	HAL_PCD_MspInit
+ 277              		.syntax unified
+ 278              		.thumb
+ 279              		.thumb_func
+ 281              	HAL_PCD_MspInit:
+ 282              	.LVL30:
+ 283              	.LFB331:
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 284              		.loc 1 260 1 is_stmt 1 view -0
+ 285              		.cfi_startproc
+ 286              		@ args = 0, pretend = 0, frame = 0
+ 287              		@ frame_needed = 0, uses_anonymous_args = 0
+ 288              		@ link register save eliminated.
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 289              		.loc 1 262 3 view .LVU90
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 290              		.loc 1 267 1 is_stmt 0 view .LVU91
+ 291 0000 7047     		bx	lr
+ 292              		.cfi_endproc
+ 293              	.LFE331:
+ 295              		.section	.text.HAL_PCD_Init,"ax",%progbits
+ 296              		.align	1
+ 297              		.global	HAL_PCD_Init
+ 298              		.syntax unified
+ 299              		.thumb
+ 300              		.thumb_func
+ 302              	HAL_PCD_Init:
+ 303              	.LVL31:
+ 304              	.LFB329:
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint8_t i;
+ 305              		.loc 1 125 1 is_stmt 1 view -0
+ 306              		.cfi_startproc
+ 307              		@ args = 0, pretend = 0, frame = 0
+ 308              		@ frame_needed = 0, uses_anonymous_args = 0
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 309              		.loc 1 126 3 view .LVU93
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 310              		.loc 1 129 3 view .LVU94
+ARM GAS  /tmp/ccJPteqL.s 			page 43
+
+
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 311              		.loc 1 129 6 is_stmt 0 view .LVU95
+ 312 0000 0028     		cmp	r0, #0
+ 313 0002 6DD0     		beq	.L22
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint8_t i;
+ 314              		.loc 1 125 1 view .LVU96
+ 315 0004 30B5     		push	{r4, r5, lr}
+ 316              	.LCFI1:
+ 317              		.cfi_def_cfa_offset 12
+ 318              		.cfi_offset 4, -12
+ 319              		.cfi_offset 5, -8
+ 320              		.cfi_offset 14, -4
+ 321 0006 87B0     		sub	sp, sp, #28
+ 322              	.LCFI2:
+ 323              		.cfi_def_cfa_offset 40
+ 324 0008 0446     		mov	r4, r0
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 325              		.loc 1 135 3 is_stmt 1 view .LVU97
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 326              		.loc 1 137 3 view .LVU98
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 327              		.loc 1 137 11 is_stmt 0 view .LVU99
+ 328 000a 90F8A932 		ldrb	r3, [r0, #681]	@ zero_extendqisi2
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 329              		.loc 1 137 6 view .LVU100
+ 330 000e 3BB1     		cbz	r3, .L28
+ 331              	.LVL32:
+ 332              	.L17:
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 333              		.loc 1 170 3 is_stmt 1 view .LVU101
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 334              		.loc 1 170 15 is_stmt 0 view .LVU102
+ 335 0010 0323     		movs	r3, #3
+ 336 0012 84F8A932 		strb	r3, [r4, #681]
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 337              		.loc 1 173 3 is_stmt 1 view .LVU103
+ 338 0016 2068     		ldr	r0, [r4]
+ 339 0018 FFF7FEFF 		bl	USB_DisableGlobalInt
+ 340              	.LVL33:
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 341              		.loc 1 176 3 view .LVU104
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 342              		.loc 1 176 10 is_stmt 0 view .LVU105
+ 343 001c 0023     		movs	r3, #0
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 344              		.loc 1 176 3 view .LVU106
+ 345 001e 1FE0     		b	.L18
+ 346              	.LVL34:
+ 347              	.L28:
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 348              		.loc 1 140 5 is_stmt 1 view .LVU107
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 349              		.loc 1 140 16 is_stmt 0 view .LVU108
+ 350 0020 80F8A832 		strb	r3, [r0, #680]
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
+ 351              		.loc 1 166 5 is_stmt 1 view .LVU109
+ 352 0024 FFF7FEFF 		bl	HAL_PCD_MspInit
+ARM GAS  /tmp/ccJPteqL.s 			page 44
+
+
+ 353              	.LVL35:
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
+ 354              		.loc 1 166 5 is_stmt 0 view .LVU110
+ 355 0028 F2E7     		b	.L17
+ 356              	.LVL36:
+ 357              	.L19:
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].num = i;
+ 358              		.loc 1 179 5 is_stmt 1 discriminator 3 view .LVU111
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].num = i;
+ 359              		.loc 1 179 26 is_stmt 0 discriminator 3 view .LVU112
+ 360 002a 5A1C     		adds	r2, r3, #1
+ 361 002c 02EB8201 		add	r1, r2, r2, lsl #2
+ 362 0030 04EBC101 		add	r1, r4, r1, lsl #3
+ 363 0034 0120     		movs	r0, #1
+ 364 0036 4870     		strb	r0, [r1, #1]
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].tx_fifo_num = i;
+ 365              		.loc 1 180 5 is_stmt 1 discriminator 3 view .LVU113
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].tx_fifo_num = i;
+ 366              		.loc 1 180 24 is_stmt 0 discriminator 3 view .LVU114
+ 367 0038 02EB8201 		add	r1, r2, r2, lsl #2
+ 368 003c 04F83130 		strb	r3, [r4, r1, lsl #3]
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Control until ep is activated */
+ 369              		.loc 1 181 5 is_stmt 1 discriminator 3 view .LVU115
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Control until ep is activated */
+ 370              		.loc 1 181 32 is_stmt 0 discriminator 3 view .LVU116
+ 371 0040 03EB8301 		add	r1, r3, r3, lsl #2
+ 372 0044 04EBC101 		add	r1, r4, r1, lsl #3
+ 373 0048 CB86     		strh	r3, [r1, #54]	@ movhi
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].maxpacket = 0U;
+ 374              		.loc 1 183 5 is_stmt 1 discriminator 3 view .LVU117
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].maxpacket = 0U;
+ 375              		.loc 1 183 25 is_stmt 0 discriminator 3 view .LVU118
+ 376 004a 02EB820C 		add	ip, r2, r2, lsl #2
+ 377 004e 04EBCC0C 		add	ip, r4, ip, lsl #3
+ 378 0052 0020     		movs	r0, #0
+ 379 0054 8CF80300 		strb	r0, [ip, #3]
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].xfer_buff = 0U;
+ 380              		.loc 1 184 5 is_stmt 1 discriminator 3 view .LVU119
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].xfer_buff = 0U;
+ 381              		.loc 1 184 30 is_stmt 0 discriminator 3 view .LVU120
+ 382 0058 8863     		str	r0, [r1, #56]
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].xfer_len = 0U;
+ 383              		.loc 1 185 5 is_stmt 1 discriminator 3 view .LVU121
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->IN_ep[i].xfer_len = 0U;
+ 384              		.loc 1 185 30 is_stmt 0 discriminator 3 view .LVU122
+ 385 005a C863     		str	r0, [r1, #60]
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 386              		.loc 1 186 5 is_stmt 1 discriminator 3 view .LVU123
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 387              		.loc 1 186 29 is_stmt 0 discriminator 3 view .LVU124
+ 388 005c 0864     		str	r0, [r1, #64]
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 389              		.loc 1 176 47 is_stmt 1 discriminator 3 view .LVU125
+ 390 005e D3B2     		uxtb	r3, r2
+ 391              	.LVL37:
+ 392              	.L18:
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ARM GAS  /tmp/ccJPteqL.s 			page 45
+
+
+ 393              		.loc 1 176 18 discriminator 1 view .LVU126
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 394              		.loc 1 176 30 is_stmt 0 discriminator 1 view .LVU127
+ 395 0060 6068     		ldr	r0, [r4, #4]
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 396              		.loc 1 176 18 discriminator 1 view .LVU128
+ 397 0062 8342     		cmp	r3, r0
+ 398 0064 E1D3     		bcc	.L19
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 399              		.loc 1 189 10 view .LVU129
+ 400 0066 0023     		movs	r3, #0
+ 401              	.LVL38:
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 402              		.loc 1 189 10 view .LVU130
+ 403 0068 16E0     		b	.L20
+ 404              	.LVL39:
+ 405              	.L21:
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].num = i;
+ 406              		.loc 1 191 5 is_stmt 1 discriminator 3 view .LVU131
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].num = i;
+ 407              		.loc 1 191 27 is_stmt 0 discriminator 3 view .LVU132
+ 408 006a 03EB8302 		add	r2, r3, r3, lsl #2
+ 409 006e 04EBC202 		add	r2, r4, r2, lsl #3
+ 410 0072 0021     		movs	r1, #0
+ 411 0074 82F86911 		strb	r1, [r2, #361]
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Control until ep is activated */
+ 412              		.loc 1 192 5 is_stmt 1 discriminator 3 view .LVU133
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Control until ep is activated */
+ 413              		.loc 1 192 25 is_stmt 0 discriminator 3 view .LVU134
+ 414 0078 82F86831 		strb	r3, [r2, #360]
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].maxpacket = 0U;
+ 415              		.loc 1 194 5 is_stmt 1 discriminator 3 view .LVU135
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].maxpacket = 0U;
+ 416              		.loc 1 194 26 is_stmt 0 discriminator 3 view .LVU136
+ 417 007c 82F86B11 		strb	r1, [r2, #363]
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].xfer_buff = 0U;
+ 418              		.loc 1 195 5 is_stmt 1 discriminator 3 view .LVU137
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].xfer_buff = 0U;
+ 419              		.loc 1 195 31 is_stmt 0 discriminator 3 view .LVU138
+ 420 0080 C2F87811 		str	r1, [r2, #376]
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].xfer_len = 0U;
+ 421              		.loc 1 196 5 is_stmt 1 discriminator 3 view .LVU139
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->OUT_ep[i].xfer_len = 0U;
+ 422              		.loc 1 196 31 is_stmt 0 discriminator 3 view .LVU140
+ 423 0084 C2F87C11 		str	r1, [r2, #380]
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 424              		.loc 1 197 5 is_stmt 1 discriminator 3 view .LVU141
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 425              		.loc 1 197 30 is_stmt 0 discriminator 3 view .LVU142
+ 426 0088 03EB8302 		add	r2, r3, r3, lsl #2
+ 427 008c 04EBC202 		add	r2, r4, r2, lsl #3
+ 428 0090 C2F88011 		str	r1, [r2, #384]
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 429              		.loc 1 189 47 is_stmt 1 discriminator 3 view .LVU143
+ 430 0094 0133     		adds	r3, r3, #1
+ 431              	.LVL40:
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ARM GAS  /tmp/ccJPteqL.s 			page 46
+
+
+ 432              		.loc 1 189 47 is_stmt 0 discriminator 3 view .LVU144
+ 433 0096 DBB2     		uxtb	r3, r3
+ 434              	.LVL41:
+ 435              	.L20:
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 436              		.loc 1 189 18 is_stmt 1 discriminator 1 view .LVU145
+ 437 0098 9842     		cmp	r0, r3
+ 438 009a E6D8     		bhi	.L21
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 439              		.loc 1 201 3 view .LVU146
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 440              		.loc 1 201 25 is_stmt 0 view .LVU147
+ 441 009c A446     		mov	ip, r4
+ 442 009e 5CF8105B 		ldr	r5, [ip], #16
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 443              		.loc 1 201 9 view .LVU148
+ 444 00a2 EE46     		mov	lr, sp
+ 445 00a4 BCE80F00 		ldmia	ip!, {r0, r1, r2, r3}
+ 446              	.LVL42:
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 447              		.loc 1 201 9 view .LVU149
+ 448 00a8 AEE80F00 		stmia	lr!, {r0, r1, r2, r3}
+ 449 00ac DCF80030 		ldr	r3, [ip]
+ 450 00b0 CEF80030 		str	r3, [lr]
+ 451 00b4 231D     		adds	r3, r4, #4
+ 452 00b6 0ECB     		ldm	r3, {r1, r2, r3}
+ 453 00b8 2846     		mov	r0, r5
+ 454 00ba FFF7FEFF 		bl	USB_DevInit
+ 455              	.LVL43:
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->State = HAL_PCD_STATE_READY;
+ 456              		.loc 1 203 3 is_stmt 1 view .LVU150
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->State = HAL_PCD_STATE_READY;
+ 457              		.loc 1 203 21 is_stmt 0 view .LVU151
+ 458 00be 0023     		movs	r3, #0
+ 459 00c0 84F82430 		strb	r3, [r4, #36]
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 460              		.loc 1 204 3 is_stmt 1 view .LVU152
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 461              		.loc 1 204 15 is_stmt 0 view .LVU153
+ 462 00c4 0123     		movs	r3, #1
+ 463 00c6 84F8A932 		strb	r3, [r4, #681]
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 464              		.loc 1 207 3 is_stmt 1 view .LVU154
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 465              		.loc 1 207 17 is_stmt 0 view .LVU155
+ 466 00ca E369     		ldr	r3, [r4, #28]
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 467              		.loc 1 207 6 view .LVU156
+ 468 00cc 012B     		cmp	r3, #1
+ 469 00ce 02D0     		beq	.L29
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 470              		.loc 1 212 10 view .LVU157
+ 471 00d0 0020     		movs	r0, #0
+ 472              	.L16:
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 473              		.loc 1 213 1 view .LVU158
+ 474 00d2 07B0     		add	sp, sp, #28
+ARM GAS  /tmp/ccJPteqL.s 			page 47
+
+
+ 475              	.LCFI3:
+ 476              		.cfi_remember_state
+ 477              		.cfi_def_cfa_offset 12
+ 478              		@ sp needed
+ 479 00d4 30BD     		pop	{r4, r5, pc}
+ 480              	.LVL44:
+ 481              	.L29:
+ 482              	.LCFI4:
+ 483              		.cfi_restore_state
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 484              		.loc 1 209 5 is_stmt 1 view .LVU159
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 485              		.loc 1 209 11 is_stmt 0 view .LVU160
+ 486 00d6 2046     		mov	r0, r4
+ 487 00d8 FFF7FEFF 		bl	HAL_PCDEx_ActivateLPM
+ 488              	.LVL45:
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 489              		.loc 1 212 10 view .LVU161
+ 490 00dc 0020     		movs	r0, #0
+ 491 00de F8E7     		b	.L16
+ 492              	.LVL46:
+ 493              	.L22:
+ 494              	.LCFI5:
+ 495              		.cfi_def_cfa_offset 0
+ 496              		.cfi_restore 4
+ 497              		.cfi_restore 5
+ 498              		.cfi_restore 14
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 499              		.loc 1 131 12 view .LVU162
+ 500 00e0 0120     		movs	r0, #1
+ 501              	.LVL47:
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 502              		.loc 1 213 1 view .LVU163
+ 503 00e2 7047     		bx	lr
+ 504              		.cfi_endproc
+ 505              	.LFE329:
+ 507              		.section	.text.HAL_PCD_MspDeInit,"ax",%progbits
+ 508              		.align	1
+ 509              		.weak	HAL_PCD_MspDeInit
+ 510              		.syntax unified
+ 511              		.thumb
+ 512              		.thumb_func
+ 514              	HAL_PCD_MspDeInit:
+ 515              	.LVL48:
+ 516              	.LFB332:
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 517              		.loc 1 275 1 is_stmt 1 view -0
+ 518              		.cfi_startproc
+ 519              		@ args = 0, pretend = 0, frame = 0
+ 520              		@ frame_needed = 0, uses_anonymous_args = 0
+ 521              		@ link register save eliminated.
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 522              		.loc 1 277 3 view .LVU165
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 523              		.loc 1 282 1 is_stmt 0 view .LVU166
+ 524 0000 7047     		bx	lr
+ 525              		.cfi_endproc
+ARM GAS  /tmp/ccJPteqL.s 			page 48
+
+
+ 526              	.LFE332:
+ 528              		.section	.text.HAL_PCD_DeInit,"ax",%progbits
+ 529              		.align	1
+ 530              		.global	HAL_PCD_DeInit
+ 531              		.syntax unified
+ 532              		.thumb
+ 533              		.thumb_func
+ 535              	HAL_PCD_DeInit:
+ 536              	.LVL49:
+ 537              	.LFB330:
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Check the PCD handle allocation */
+ 538              		.loc 1 221 1 is_stmt 1 view -0
+ 539              		.cfi_startproc
+ 540              		@ args = 0, pretend = 0, frame = 0
+ 541              		@ frame_needed = 0, uses_anonymous_args = 0
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Check the PCD handle allocation */
+ 542              		.loc 1 221 1 is_stmt 0 view .LVU168
+ 543 0000 38B5     		push	{r3, r4, r5, lr}
+ 544              	.LCFI6:
+ 545              		.cfi_def_cfa_offset 16
+ 546              		.cfi_offset 3, -16
+ 547              		.cfi_offset 4, -12
+ 548              		.cfi_offset 5, -8
+ 549              		.cfi_offset 14, -4
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 550              		.loc 1 223 3 is_stmt 1 view .LVU169
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 551              		.loc 1 223 6 is_stmt 0 view .LVU170
+ 552 0002 90B1     		cbz	r0, .L33
+ 553 0004 0446     		mov	r4, r0
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 554              		.loc 1 228 3 is_stmt 1 view .LVU171
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 555              		.loc 1 228 15 is_stmt 0 view .LVU172
+ 556 0006 0323     		movs	r3, #3
+ 557 0008 80F8A932 		strb	r3, [r0, #681]
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 558              		.loc 1 231 3 is_stmt 1 view .LVU173
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 559              		.loc 1 231 7 is_stmt 0 view .LVU174
+ 560 000c 0068     		ldr	r0, [r0]
+ 561              	.LVL50:
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 562              		.loc 1 231 7 view .LVU175
+ 563 000e FFF7FEFF 		bl	USB_StopDevice
+ 564              	.LVL51:
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 565              		.loc 1 231 6 view .LVU176
+ 566 0012 0546     		mov	r5, r0
+ 567 0014 10B1     		cbz	r0, .L36
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 568              		.loc 1 233 12 view .LVU177
+ 569 0016 0125     		movs	r5, #1
+ 570              	.LVL52:
+ 571              	.L32:
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 572              		.loc 1 252 1 view .LVU178
+ARM GAS  /tmp/ccJPteqL.s 			page 49
+
+
+ 573 0018 2846     		mov	r0, r5
+ 574 001a 38BD     		pop	{r3, r4, r5, pc}
+ 575              	.LVL53:
+ 576              	.L36:
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 577              		.loc 1 246 3 is_stmt 1 view .LVU179
+ 578 001c 2046     		mov	r0, r4
+ 579 001e FFF7FEFF 		bl	HAL_PCD_MspDeInit
+ 580              	.LVL54:
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 581              		.loc 1 249 3 view .LVU180
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 582              		.loc 1 249 15 is_stmt 0 view .LVU181
+ 583 0022 0023     		movs	r3, #0
+ 584 0024 84F8A932 		strb	r3, [r4, #681]
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 585              		.loc 1 251 3 is_stmt 1 view .LVU182
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 586              		.loc 1 251 10 is_stmt 0 view .LVU183
+ 587 0028 F6E7     		b	.L32
+ 588              	.LVL55:
+ 589              	.L33:
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 590              		.loc 1 225 12 view .LVU184
+ 591 002a 0125     		movs	r5, #1
+ 592 002c F4E7     		b	.L32
+ 593              		.cfi_endproc
+ 594              	.LFE330:
+ 596              		.section	.text.HAL_PCD_Start,"ax",%progbits
+ 597              		.align	1
+ 598              		.global	HAL_PCD_Start
+ 599              		.syntax unified
+ 600              		.thumb
+ 601              		.thumb_func
+ 603              	HAL_PCD_Start:
+ 604              	.LVL56:
+ 605              	.LFB333:
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 606              		.loc 1 978 1 is_stmt 1 view -0
+ 607              		.cfi_startproc
+ 608              		@ args = 0, pretend = 0, frame = 0
+ 609              		@ frame_needed = 0, uses_anonymous_args = 0
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_ENABLE(hpcd);
+ 610              		.loc 1 979 3 view .LVU186
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_ENABLE(hpcd);
+ 611              		.loc 1 979 3 view .LVU187
+ 612 0000 90F8A832 		ldrb	r3, [r0, #680]	@ zero_extendqisi2
+ 613 0004 012B     		cmp	r3, #1
+ 614 0006 0ED0     		beq	.L39
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 615              		.loc 1 978 1 is_stmt 0 discriminator 2 view .LVU188
+ 616 0008 10B5     		push	{r4, lr}
+ 617              	.LCFI7:
+ 618              		.cfi_def_cfa_offset 8
+ 619              		.cfi_offset 4, -8
+ 620              		.cfi_offset 14, -4
+ 621 000a 0446     		mov	r4, r0
+ARM GAS  /tmp/ccJPteqL.s 			page 50
+
+
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_ENABLE(hpcd);
+ 622              		.loc 1 979 3 is_stmt 1 discriminator 2 view .LVU189
+ 623 000c 0123     		movs	r3, #1
+ 624 000e 80F8A832 		strb	r3, [r0, #680]
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_ENABLE(hpcd);
+ 625              		.loc 1 979 3 discriminator 2 view .LVU190
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevConnect(hpcd->Instance);
+ 626              		.loc 1 980 3 discriminator 2 view .LVU191
+ 627 0012 0068     		ldr	r0, [r0]
+ 628              	.LVL57:
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevConnect(hpcd->Instance);
+ 629              		.loc 1 980 3 is_stmt 0 discriminator 2 view .LVU192
+ 630 0014 FFF7FEFF 		bl	USB_EnableGlobalInt
+ 631              	.LVL58:
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 632              		.loc 1 981 3 is_stmt 1 discriminator 2 view .LVU193
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 633              		.loc 1 981 9 is_stmt 0 discriminator 2 view .LVU194
+ 634 0018 2068     		ldr	r0, [r4]
+ 635 001a FFF7FEFF 		bl	USB_DevConnect
+ 636              	.LVL59:
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 637              		.loc 1 982 3 is_stmt 1 discriminator 2 view .LVU195
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 638              		.loc 1 982 3 discriminator 2 view .LVU196
+ 639 001e 0020     		movs	r0, #0
+ 640 0020 84F8A802 		strb	r0, [r4, #680]
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 641              		.loc 1 982 3 discriminator 2 view .LVU197
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 642              		.loc 1 984 3 discriminator 2 view .LVU198
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 643              		.loc 1 985 1 is_stmt 0 discriminator 2 view .LVU199
+ 644 0024 10BD     		pop	{r4, pc}
+ 645              	.LVL60:
+ 646              	.L39:
+ 647              	.LCFI8:
+ 648              		.cfi_def_cfa_offset 0
+ 649              		.cfi_restore 4
+ 650              		.cfi_restore 14
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_ENABLE(hpcd);
+ 651              		.loc 1 979 3 view .LVU200
+ 652 0026 0220     		movs	r0, #2
+ 653              	.LVL61:
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 654              		.loc 1 985 1 view .LVU201
+ 655 0028 7047     		bx	lr
+ 656              		.cfi_endproc
+ 657              	.LFE333:
+ 659              		.section	.text.HAL_PCD_Stop,"ax",%progbits
+ 660              		.align	1
+ 661              		.global	HAL_PCD_Stop
+ 662              		.syntax unified
+ 663              		.thumb
+ 664              		.thumb_func
+ 666              	HAL_PCD_Stop:
+ 667              	.LVL62:
+ARM GAS  /tmp/ccJPteqL.s 			page 51
+
+
+ 668              	.LFB334:
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 669              		.loc 1 993 1 is_stmt 1 view -0
+ 670              		.cfi_startproc
+ 671              		@ args = 0, pretend = 0, frame = 0
+ 672              		@ frame_needed = 0, uses_anonymous_args = 0
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_DISABLE(hpcd);
+ 673              		.loc 1 994 3 view .LVU203
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_DISABLE(hpcd);
+ 674              		.loc 1 994 3 view .LVU204
+ 675 0000 90F8A832 		ldrb	r3, [r0, #680]	@ zero_extendqisi2
+ 676 0004 012B     		cmp	r3, #1
+ 677 0006 0ED0     		beq	.L46
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 678              		.loc 1 993 1 is_stmt 0 discriminator 2 view .LVU205
+ 679 0008 10B5     		push	{r4, lr}
+ 680              	.LCFI9:
+ 681              		.cfi_def_cfa_offset 8
+ 682              		.cfi_offset 4, -8
+ 683              		.cfi_offset 14, -4
+ 684 000a 0446     		mov	r4, r0
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_DISABLE(hpcd);
+ 685              		.loc 1 994 3 is_stmt 1 discriminator 2 view .LVU206
+ 686 000c 0123     		movs	r3, #1
+ 687 000e 80F8A832 		strb	r3, [r0, #680]
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_DISABLE(hpcd);
+ 688              		.loc 1 994 3 discriminator 2 view .LVU207
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevDisconnect(hpcd->Instance);
+ 689              		.loc 1 995 3 discriminator 2 view .LVU208
+ 690 0012 0068     		ldr	r0, [r0]
+ 691              	.LVL63:
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevDisconnect(hpcd->Instance);
+ 692              		.loc 1 995 3 is_stmt 0 discriminator 2 view .LVU209
+ 693 0014 FFF7FEFF 		bl	USB_DisableGlobalInt
+ 694              	.LVL64:
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 695              		.loc 1 996 3 is_stmt 1 discriminator 2 view .LVU210
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 696              		.loc 1 996 9 is_stmt 0 discriminator 2 view .LVU211
+ 697 0018 2068     		ldr	r0, [r4]
+ 698 001a FFF7FEFF 		bl	USB_DevDisconnect
+ 699              	.LVL65:
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 700              		.loc 1 997 3 is_stmt 1 discriminator 2 view .LVU212
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 701              		.loc 1 997 3 discriminator 2 view .LVU213
+ 702 001e 0020     		movs	r0, #0
+ 703 0020 84F8A802 		strb	r0, [r4, #680]
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 704              		.loc 1 997 3 discriminator 2 view .LVU214
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 705              		.loc 1 999 3 discriminator 2 view .LVU215
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 706              		.loc 1 1000 1 is_stmt 0 discriminator 2 view .LVU216
+ 707 0024 10BD     		pop	{r4, pc}
+ 708              	.LVL66:
+ 709              	.L46:
+ARM GAS  /tmp/ccJPteqL.s 			page 52
+
+
+ 710              	.LCFI10:
+ 711              		.cfi_def_cfa_offset 0
+ 712              		.cfi_restore 4
+ 713              		.cfi_restore 14
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_PCD_DISABLE(hpcd);
+ 714              		.loc 1 994 3 view .LVU217
+ 715 0026 0220     		movs	r0, #2
+ 716              	.LVL67:
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 717              		.loc 1 1000 1 view .LVU218
+ 718 0028 7047     		bx	lr
+ 719              		.cfi_endproc
+ 720              	.LFE334:
+ 722              		.section	.text.HAL_PCD_DataOutStageCallback,"ax",%progbits
+ 723              		.align	1
+ 724              		.weak	HAL_PCD_DataOutStageCallback
+ 725              		.syntax unified
+ 726              		.thumb
+ 727              		.thumb_func
+ 729              	HAL_PCD_DataOutStageCallback:
+ 730              	.LVL68:
+ 731              	.LFB336:
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 732              		.loc 1 1155 1 is_stmt 1 view -0
+ 733              		.cfi_startproc
+ 734              		@ args = 0, pretend = 0, frame = 0
+ 735              		@ frame_needed = 0, uses_anonymous_args = 0
+ 736              		@ link register save eliminated.
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(epnum);
+ 737              		.loc 1 1157 3 view .LVU220
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 738              		.loc 1 1158 3 view .LVU221
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 739              		.loc 1 1163 1 is_stmt 0 view .LVU222
+ 740 0000 7047     		bx	lr
+ 741              		.cfi_endproc
+ 742              	.LFE336:
+ 744              		.section	.text.HAL_PCD_DataInStageCallback,"ax",%progbits
+ 745              		.align	1
+ 746              		.weak	HAL_PCD_DataInStageCallback
+ 747              		.syntax unified
+ 748              		.thumb
+ 749              		.thumb_func
+ 751              	HAL_PCD_DataInStageCallback:
+ 752              	.LVL69:
+ 753              	.LFB337:
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 754              		.loc 1 1172 1 is_stmt 1 view -0
+ 755              		.cfi_startproc
+ 756              		@ args = 0, pretend = 0, frame = 0
+ 757              		@ frame_needed = 0, uses_anonymous_args = 0
+ 758              		@ link register save eliminated.
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(epnum);
+ 759              		.loc 1 1174 3 view .LVU224
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 760              		.loc 1 1175 3 view .LVU225
+1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ARM GAS  /tmp/ccJPteqL.s 			page 53
+
+
+ 761              		.loc 1 1180 1 is_stmt 0 view .LVU226
+ 762 0000 7047     		bx	lr
+ 763              		.cfi_endproc
+ 764              	.LFE337:
+ 766              		.section	.text.HAL_PCD_EP_DB_Transmit,"ax",%progbits
+ 767              		.align	1
+ 768              		.syntax unified
+ 769              		.thumb
+ 770              		.thumb_func
+ 772              	HAL_PCD_EP_DB_Transmit:
+ 773              	.LVL70:
+ 774              	.LFB363:
+2038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+2041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @brief  Manage double buffer bulk IN transaction from ISR
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  hpcd PCD handle
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  ep current endpoint handle
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @param  wEPVal Last snapshot of EPRx register value taken in ISR
+2045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   * @retval HAL status
+2046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   */
+2047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
+2048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                                                 PCD_EPTypeDef *ep, uint16_t wEPVal)
+2049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** {
+ 775              		.loc 1 2049 1 is_stmt 1 view -0
+ 776              		.cfi_startproc
+ 777              		@ args = 0, pretend = 0, frame = 0
+ 778              		@ frame_needed = 0, uses_anonymous_args = 0
+ 779              		.loc 1 2049 1 is_stmt 0 view .LVU228
+ 780 0000 70B5     		push	{r4, r5, r6, lr}
+ 781              	.LCFI11:
+ 782              		.cfi_def_cfa_offset 16
+ 783              		.cfi_offset 4, -16
+ 784              		.cfi_offset 5, -12
+ 785              		.cfi_offset 6, -8
+ 786              		.cfi_offset 14, -4
+ 787 0002 0546     		mov	r5, r0
+ 788 0004 0C46     		mov	r4, r1
+ 789 0006 1646     		mov	r6, r2
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint32_t len;
+ 790              		.loc 1 2050 3 is_stmt 1 view .LVU229
+2051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint16_t TxPctSize;
+ 791              		.loc 1 2051 3 view .LVU230
+2052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Data Buffer0 ACK received */
+2054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+ 792              		.loc 1 2054 3 view .LVU231
+ 793              		.loc 1 2054 6 is_stmt 0 view .LVU232
+ 794 0008 12F0400F 		tst	r2, #64
+ 795 000c 00F00981 		beq	.L54
+2055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+2056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* multi-packet on the NON control IN endpoint */
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ 796              		.loc 1 2057 5 is_stmt 1 view .LVU233
+ 797              		.loc 1 2057 27 is_stmt 0 view .LVU234
+ 798 0010 0268     		ldr	r2, [r0]
+ 799              	.LVL71:
+ARM GAS  /tmp/ccJPteqL.s 			page 54
+
+
+ 800              		.loc 1 2057 27 view .LVU235
+ 801 0012 B2F85030 		ldrh	r3, [r2, #80]
+ 802 0016 0978     		ldrb	r1, [r1]	@ zero_extendqisi2
+ 803              	.LVL72:
+ 804              		.loc 1 2057 27 view .LVU236
+ 805 0018 C800     		lsls	r0, r1, #3
+ 806              	.LVL73:
+ 807              		.loc 1 2057 27 view .LVU237
+ 808 001a 10FA83F3 		uxtah	r3, r0, r3
+ 809 001e 1344     		add	r3, r3, r2
+ 810 0020 B3F80224 		ldrh	r2, [r3, #1026]
+ 811              		.loc 1 2057 15 view .LVU238
+ 812 0024 C2F30902 		ubfx	r2, r2, #0, #10
+ 813              	.LVL74:
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (ep->xfer_len > TxPctSize)
+ 814              		.loc 1 2059 5 is_stmt 1 view .LVU239
+ 815              		.loc 1 2059 11 is_stmt 0 view .LVU240
+ 816 0028 A369     		ldr	r3, [r4, #24]
+ 817              		.loc 1 2059 8 view .LVU241
+ 818 002a 9342     		cmp	r3, r2
+ 819 002c 51D9     		bls	.L55
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       ep->xfer_len -= TxPctSize;
+ 820              		.loc 1 2061 7 is_stmt 1 view .LVU242
+ 821              		.loc 1 2061 20 is_stmt 0 view .LVU243
+ 822 002e 9B1A     		subs	r3, r3, r2
+ 823 0030 A361     		str	r3, [r4, #24]
+ 824              	.L56:
+2062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     else
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       ep->xfer_len = 0U;
+2066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Transfer is completed */
+2069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (ep->xfer_len == 0U)
+ 825              		.loc 1 2069 5 is_stmt 1 view .LVU244
+ 826              		.loc 1 2069 11 is_stmt 0 view .LVU245
+ 827 0032 A369     		ldr	r3, [r4, #24]
+ 828              		.loc 1 2069 8 view .LVU246
+ 829 0034 002B     		cmp	r3, #0
+ 830 0036 68D1     		bne	.L57
+2070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 831              		.loc 1 2071 7 is_stmt 1 view .LVU247
+ 832              		.loc 1 2071 7 view .LVU248
+ 833 0038 6378     		ldrb	r3, [r4, #1]	@ zero_extendqisi2
+ 834 003a 002B     		cmp	r3, #0
+ 835 003c 4CD1     		bne	.L58
+ 836              		.loc 1 2071 7 discriminator 1 view .LVU249
+ 837              	.LBB6:
+ 838              		.loc 1 2071 7 discriminator 1 view .LVU250
+ 839 003e 2A68     		ldr	r2, [r5]
+ 840              	.LVL75:
+ 841              		.loc 1 2071 7 discriminator 1 view .LVU251
+ 842              		.loc 1 2071 7 discriminator 1 view .LVU252
+ARM GAS  /tmp/ccJPteqL.s 			page 55
+
+
+ 843 0040 B2F85030 		ldrh	r3, [r2, #80]
+ 844 0044 12FA83F3 		uxtah	r3, r2, r3
+ 845              	.LVL76:
+ 846              		.loc 1 2071 7 discriminator 1 view .LVU253
+ 847 0048 0344     		add	r3, r3, r0
+ 848              	.LVL77:
+ 849              		.loc 1 2071 7 discriminator 1 view .LVU254
+ 850              	.LBB7:
+ 851              		.loc 1 2071 7 discriminator 1 view .LVU255
+ 852              		.loc 1 2071 7 discriminator 1 view .LVU256
+ 853              		.loc 1 2071 7 discriminator 1 view .LVU257
+ 854              		.loc 1 2071 7 discriminator 1 view .LVU258
+ 855 004a B3F80224 		ldrh	r2, [r3, #1026]
+ 856 004e 92B2     		uxth	r2, r2
+ 857 0050 22F4F842 		bic	r2, r2, #31744
+ 858 0054 92B2     		uxth	r2, r2
+ 859 0056 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 860              		.loc 1 2071 7 discriminator 1 view .LVU259
+ 861 005a B3F80224 		ldrh	r2, [r3, #1026]
+ 862 005e 6FEA4242 		mvn	r2, r2, lsl #17
+ 863 0062 6FEA5242 		mvn	r2, r2, lsr #17
+ 864 0066 92B2     		uxth	r2, r2
+ 865 0068 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 866              	.LVL78:
+ 867              	.L59:
+ 868              		.loc 1 2071 7 is_stmt 0 discriminator 1 view .LVU260
+ 869              	.LBE7:
+ 870              	.LBE6:
+ 871              		.loc 1 2071 7 is_stmt 1 discriminator 18 view .LVU261
+ 872              		.loc 1 2071 7 discriminator 18 view .LVU262
+2072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 873              		.loc 1 2072 7 discriminator 18 view .LVU263
+ 874              	.LBB8:
+ 875              		.loc 1 2072 7 discriminator 18 view .LVU264
+ 876 006c 2A68     		ldr	r2, [r5]
+ 877              	.LVL79:
+ 878              		.loc 1 2072 7 discriminator 18 view .LVU265
+ 879              		.loc 1 2072 7 discriminator 18 view .LVU266
+ 880 006e 6378     		ldrb	r3, [r4, #1]	@ zero_extendqisi2
+ 881 0070 002B     		cmp	r3, #0
+ 882 0072 3DD1     		bne	.L60
+ 883              		.loc 1 2072 7 discriminator 1 view .LVU267
+ 884              	.LBB9:
+ 885              		.loc 1 2072 7 discriminator 1 view .LVU268
+ 886              	.LVL80:
+ 887              		.loc 1 2072 7 discriminator 1 view .LVU269
+ 888              		.loc 1 2072 7 discriminator 1 view .LVU270
+ 889 0074 B2F85030 		ldrh	r3, [r2, #80]
+ 890 0078 12FA83F3 		uxtah	r3, r2, r3
+ 891              	.LVL81:
+ 892              		.loc 1 2072 7 discriminator 1 view .LVU271
+ 893 007c 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 894              	.LVL82:
+ 895              		.loc 1 2072 7 is_stmt 0 discriminator 1 view .LVU272
+ 896 007e 03EBC203 		add	r3, r3, r2, lsl #3
+ 897              	.LVL83:
+ 898              		.loc 1 2072 7 is_stmt 1 discriminator 1 view .LVU273
+ARM GAS  /tmp/ccJPteqL.s 			page 56
+
+
+ 899              	.LBB10:
+ 900              		.loc 1 2072 7 discriminator 1 view .LVU274
+ 901              		.loc 1 2072 7 discriminator 1 view .LVU275
+ 902              		.loc 1 2072 7 discriminator 1 view .LVU276
+ 903              		.loc 1 2072 7 discriminator 1 view .LVU277
+ 904 0082 B3F80624 		ldrh	r2, [r3, #1030]
+ 905 0086 92B2     		uxth	r2, r2
+ 906 0088 22F4F842 		bic	r2, r2, #31744
+ 907 008c 92B2     		uxth	r2, r2
+ 908 008e A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 909              	.LVL84:
+ 910              		.loc 1 2072 7 discriminator 1 view .LVU278
+ 911 0092 B3F80624 		ldrh	r2, [r3, #1030]
+ 912 0096 6FEA4242 		mvn	r2, r2, lsl #17
+ 913 009a 6FEA5242 		mvn	r2, r2, lsr #17
+ 914 009e 92B2     		uxth	r2, r2
+ 915 00a0 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 916              	.LVL85:
+ 917              	.L61:
+ 918              		.loc 1 2072 7 is_stmt 0 discriminator 1 view .LVU279
+ 919              	.LBE10:
+ 920              	.LBE9:
+ 921              	.LBE8:
+ 922              		.loc 1 2072 7 is_stmt 1 discriminator 18 view .LVU280
+2073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* TX COMPLETE */
+2075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+2076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->DataInStageCallback(hpcd, ep->num);
+2077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+2078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       HAL_PCD_DataInStageCallback(hpcd, ep->num);
+ 923              		.loc 1 2078 7 discriminator 18 view .LVU281
+ 924 00a4 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 925 00a6 2846     		mov	r0, r5
+ 926 00a8 FFF7FEFF 		bl	HAL_PCD_DataInStageCallback
+ 927              	.LVL86:
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+2080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       if ((wEPVal & USB_EP_DTOG_RX) != 0U)
+ 928              		.loc 1 2081 7 discriminator 18 view .LVU282
+ 929              		.loc 1 2081 10 is_stmt 0 discriminator 18 view .LVU283
+ 930 00ac 16F4804F 		tst	r6, #16384
+ 931 00b0 40D0     		beq	.L62
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
+ 932              		.loc 1 2083 9 is_stmt 1 discriminator 4 view .LVU284
+ 933              		.loc 1 2083 9 discriminator 4 view .LVU285
+ 934              		.loc 1 2083 9 discriminator 4 view .LVU286
+ 935              		.loc 1 2083 9 discriminator 4 view .LVU287
+ 936              	.LBB11:
+ 937              		.loc 1 2083 9 discriminator 4 view .LVU288
+ 938              		.loc 1 2083 9 discriminator 4 view .LVU289
+ 939 00b2 2A68     		ldr	r2, [r5]
+ 940 00b4 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 941 00b6 32F82130 		ldrh	r3, [r2, r1, lsl #2]
+ 942 00ba 9BB2     		uxth	r3, r3
+ 943 00bc 23F4E043 		bic	r3, r3, #28672
+ 944 00c0 23F07003 		bic	r3, r3, #112
+ARM GAS  /tmp/ccJPteqL.s 			page 57
+
+
+ 945              	.LVL87:
+ 946              		.loc 1 2083 9 discriminator 4 view .LVU290
+ 947 00c4 43F44043 		orr	r3, r3, #49152
+ 948              	.LVL88:
+ 949              		.loc 1 2083 9 is_stmt 0 discriminator 4 view .LVU291
+ 950 00c8 43F08003 		orr	r3, r3, #128
+ 951 00cc 22F82130 		strh	r3, [r2, r1, lsl #2]	@ movhi
+ 952 00d0 30E0     		b	.L62
+ 953              	.LVL89:
+ 954              	.L55:
+ 955              		.loc 1 2083 9 discriminator 4 view .LVU292
+ 956              	.LBE11:
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 957              		.loc 1 2065 7 is_stmt 1 view .LVU293
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 958              		.loc 1 2065 20 is_stmt 0 view .LVU294
+ 959 00d2 0023     		movs	r3, #0
+ 960 00d4 A361     		str	r3, [r4, #24]
+ 961 00d6 ACE7     		b	.L56
+ 962              	.L58:
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 963              		.loc 1 2071 7 is_stmt 1 discriminator 2 view .LVU295
+ 964 00d8 012B     		cmp	r3, #1
+ 965 00da C7D1     		bne	.L59
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 966              		.loc 1 2071 7 discriminator 16 view .LVU296
+ 967              	.LBB12:
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 968              		.loc 1 2071 7 discriminator 16 view .LVU297
+ 969 00dc 2A68     		ldr	r2, [r5]
+ 970              	.LVL90:
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 971              		.loc 1 2071 7 discriminator 16 view .LVU298
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 972              		.loc 1 2071 7 discriminator 16 view .LVU299
+ 973 00de B2F85030 		ldrh	r3, [r2, #80]
+ 974 00e2 12FA83F3 		uxtah	r3, r2, r3
+ 975              	.LVL91:
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 976              		.loc 1 2071 7 discriminator 16 view .LVU300
+ 977 00e6 0344     		add	r3, r3, r0
+ 978              	.LVL92:
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 979              		.loc 1 2071 7 discriminator 16 view .LVU301
+ 980 00e8 0022     		movs	r2, #0
+ 981 00ea A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 982 00ee BDE7     		b	.L59
+ 983              	.LVL93:
+ 984              	.L60:
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 985              		.loc 1 2071 7 is_stmt 0 discriminator 16 view .LVU302
+ 986              	.LBE12:
+ 987              	.LBB13:
+2072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 988              		.loc 1 2072 7 is_stmt 1 discriminator 2 view .LVU303
+ 989 00f0 012B     		cmp	r3, #1
+ 990 00f2 D7D1     		bne	.L61
+ARM GAS  /tmp/ccJPteqL.s 			page 58
+
+
+2072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 991              		.loc 1 2072 7 discriminator 16 view .LVU304
+ 992 00f4 B2F85030 		ldrh	r3, [r2, #80]
+ 993 00f8 12FA83F3 		uxtah	r3, r2, r3
+ 994              	.LVL94:
+2072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 995              		.loc 1 2072 7 discriminator 16 view .LVU305
+ 996 00fc 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 997 00fe 03EBC203 		add	r3, r3, r2, lsl #3
+ 998              	.LVL95:
+2072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 999              		.loc 1 2072 7 discriminator 16 view .LVU306
+ 1000 0102 0022     		movs	r2, #0
+ 1001 0104 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 1002 0108 CCE7     		b	.L61
+ 1003              	.LVL96:
+ 1004              	.L57:
+2072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1005              		.loc 1 2072 7 is_stmt 0 discriminator 16 view .LVU307
+ 1006              	.LBE13:
+2084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+2085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     else /* Transfer is not yet Done */
+2087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* need to Free USB Buff */
+2089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       if ((wEPVal & USB_EP_DTOG_RX) != 0U)
+ 1007              		.loc 1 2089 7 is_stmt 1 view .LVU308
+ 1008              		.loc 1 2089 10 is_stmt 0 view .LVU309
+ 1009 010a 16F4804F 		tst	r6, #16384
+ 1010 010e 0DD0     		beq	.L63
+2090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+2091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
+ 1011              		.loc 1 2091 9 is_stmt 1 discriminator 4 view .LVU310
+ 1012              		.loc 1 2091 9 discriminator 4 view .LVU311
+ 1013              		.loc 1 2091 9 discriminator 4 view .LVU312
+ 1014              		.loc 1 2091 9 discriminator 4 view .LVU313
+ 1015              	.LBB14:
+ 1016              		.loc 1 2091 9 discriminator 4 view .LVU314
+ 1017              		.loc 1 2091 9 discriminator 4 view .LVU315
+ 1018 0110 2868     		ldr	r0, [r5]
+ 1019 0112 30F82130 		ldrh	r3, [r0, r1, lsl #2]
+ 1020 0116 9BB2     		uxth	r3, r3
+ 1021 0118 23F4E043 		bic	r3, r3, #28672
+ 1022 011c 23F07003 		bic	r3, r3, #112
+ 1023              	.LVL97:
+ 1024              		.loc 1 2091 9 discriminator 4 view .LVU316
+ 1025 0120 43F44043 		orr	r3, r3, #49152
+ 1026              	.LVL98:
+ 1027              		.loc 1 2091 9 is_stmt 0 discriminator 4 view .LVU317
+ 1028 0124 43F08003 		orr	r3, r3, #128
+ 1029 0128 20F82130 		strh	r3, [r0, r1, lsl #2]	@ movhi
+ 1030              	.LVL99:
+ 1031              	.L63:
+ 1032              		.loc 1 2091 9 discriminator 4 view .LVU318
+ 1033              	.LBE14:
+ 1034              		.loc 1 2091 9 is_stmt 1 discriminator 6 view .LVU319
+ 1035              		.loc 1 2091 9 discriminator 6 view .LVU320
+ARM GAS  /tmp/ccJPteqL.s 			page 59
+
+
+2092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+2093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* Still there is data to Fill in the next Buffer */
+2095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       if (ep->xfer_fill_db == 1U)
+ 1036              		.loc 1 2095 7 discriminator 6 view .LVU321
+ 1037              		.loc 1 2095 13 is_stmt 0 discriminator 6 view .LVU322
+ 1038 012c 94F82430 		ldrb	r3, [r4, #36]	@ zero_extendqisi2
+ 1039              		.loc 1 2095 10 discriminator 6 view .LVU323
+ 1040 0130 012B     		cmp	r3, #1
+ 1041 0132 12D0     		beq	.L91
+ 1042              	.LVL100:
+ 1043              	.L62:
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+2097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_buff += TxPctSize;
+2098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_count += TxPctSize;
+2099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Calculate the len of the new buffer to fill */
+2101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         if (ep->xfer_len_db >= ep->maxpacket)
+2102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+2103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           len = ep->maxpacket;
+2104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_len_db -= len;
+2105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+2106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         else if (ep->xfer_len_db == 0U)
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+2108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           len = TxPctSize;
+2109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_fill_db = 0U;
+2110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+2111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         else
+2112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+2113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_fill_db = 0U;
+2114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           len = ep->xfer_len_db;
+2115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_len_db = 0U;
+2116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Write remaining Data to Buffer */
+2119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Set the Double buffer counter for pma buffer1 */
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+2121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Copy user buffer to USB PMA */
+2123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         USB_WritePMA(hpcd->Instance, ep->xfer_buff,  ep->pmaaddr0, (uint16_t)len);
+2124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+2125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+2127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   else /* Data Buffer1 ACK received */
+2128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+2129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* multi-packet on the NON control IN endpoint */
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+2131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (ep->xfer_len >= TxPctSize)
+2133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       ep->xfer_len -= TxPctSize;
+2135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     else
+2137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       ep->xfer_len = 0U;
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 60
+
+
+2141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     /* Transfer is completed */
+2142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (ep->xfer_len == 0U)
+2143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+2146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* TX COMPLETE */
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->DataInStageCallback(hpcd, ep->num);
+2150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #else
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       HAL_PCD_DataInStageCallback(hpcd, ep->num);
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* need to Free USB Buff */
+2155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       if ((wEPVal & USB_EP_DTOG_RX) == 0U)
+2156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
+2158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     else /* Transfer is not yet Done */
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+2162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* need to Free USB Buff */
+2163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       if ((wEPVal & USB_EP_DTOG_RX) == 0U)
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
+2166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       /* Still there is data to Fill in the next Buffer */
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       if (ep->xfer_fill_db == 1U)
+2170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_buff += TxPctSize;
+2172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_count += TxPctSize;
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Calculate the len of the new buffer to fill */
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         if (ep->xfer_len_db >= ep->maxpacket)
+2176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+2177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           len = ep->maxpacket;
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_len_db -= len;
+2179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         else if (ep->xfer_len_db == 0U)
+2181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           len = TxPctSize;
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_fill_db = 0U;
+2184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+2185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         else
+2186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+2187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           len = ep->xfer_len_db;
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_len_db = 0U;
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_fill_db = 0;
+2190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+2191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Set the Double buffer counter for pmabuffer1 */
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+2194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         /* Copy the user buffer to USB PMA */
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         USB_WritePMA(hpcd->Instance, ep->xfer_buff,  ep->pmaaddr1, (uint16_t)len);
+2197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ARM GAS  /tmp/ccJPteqL.s 			page 61
+
+
+2198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /*enable endpoint IN*/
+2202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+ 1044              		.loc 1 2202 3 is_stmt 1 view .LVU324
+ 1045              	.LBB15:
+ 1046              		.loc 1 2202 3 view .LVU325
+ 1047              		.loc 1 2202 3 view .LVU326
+ 1048 0134 2A68     		ldr	r2, [r5]
+ 1049 0136 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 1050 0138 32F82130 		ldrh	r3, [r2, r1, lsl #2]
+ 1051 013c 9BB2     		uxth	r3, r3
+ 1052 013e 23F4E043 		bic	r3, r3, #28672
+ 1053 0142 23F04003 		bic	r3, r3, #64
+ 1054              	.LVL101:
+ 1055              		.loc 1 2202 3 view .LVU327
+ 1056              		.loc 1 2202 3 view .LVU328
+ 1057              		.loc 1 2202 3 view .LVU329
+ 1058              		.loc 1 2202 3 view .LVU330
+ 1059 0146 83F03003 		eor	r3, r3, #48
+ 1060              	.LVL102:
+ 1061              		.loc 1 2202 3 view .LVU331
+ 1062 014a 43F40043 		orr	r3, r3, #32768
+ 1063              	.LVL103:
+ 1064              		.loc 1 2202 3 is_stmt 0 view .LVU332
+ 1065 014e 43F08003 		orr	r3, r3, #128
+ 1066 0152 22F82130 		strh	r3, [r2, r1, lsl #2]	@ movhi
+ 1067              	.LBE15:
+ 1068              		.loc 1 2202 3 is_stmt 1 view .LVU333
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+2204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+ 1069              		.loc 1 2204 3 view .LVU334
+2205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 1070              		.loc 1 2205 1 is_stmt 0 view .LVU335
+ 1071 0156 0020     		movs	r0, #0
+ 1072 0158 70BD     		pop	{r4, r5, r6, pc}
+ 1073              	.LVL104:
+ 1074              	.L91:
+2097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_count += TxPctSize;
+ 1075              		.loc 1 2097 9 is_stmt 1 view .LVU336
+2097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_count += TxPctSize;
+ 1076              		.loc 1 2097 11 is_stmt 0 view .LVU337
+ 1077 015a 6369     		ldr	r3, [r4, #20]
+2097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_count += TxPctSize;
+ 1078              		.loc 1 2097 23 view .LVU338
+ 1079 015c 1344     		add	r3, r3, r2
+ 1080 015e 6361     		str	r3, [r4, #20]
+2098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1081              		.loc 1 2098 9 is_stmt 1 view .LVU339
+2098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1082              		.loc 1 2098 11 is_stmt 0 view .LVU340
+ 1083 0160 E369     		ldr	r3, [r4, #28]
+2098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1084              		.loc 1 2098 24 view .LVU341
+ 1085 0162 1344     		add	r3, r3, r2
+ 1086 0164 E361     		str	r3, [r4, #28]
+ARM GAS  /tmp/ccJPteqL.s 			page 62
+
+
+2101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1087              		.loc 1 2101 9 is_stmt 1 view .LVU342
+2101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1088              		.loc 1 2101 15 is_stmt 0 view .LVU343
+ 1089 0166 216A     		ldr	r1, [r4, #32]
+2101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1090              		.loc 1 2101 34 view .LVU344
+ 1091 0168 2369     		ldr	r3, [r4, #16]
+2101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1092              		.loc 1 2101 12 view .LVU345
+ 1093 016a 9942     		cmp	r1, r3
+ 1094 016c 1BD3     		bcc	.L64
+2103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_len_db -= len;
+ 1095              		.loc 1 2103 11 is_stmt 1 view .LVU346
+ 1096              	.LVL105:
+2104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1097              		.loc 1 2104 11 view .LVU347
+2104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1098              		.loc 1 2104 27 is_stmt 0 view .LVU348
+ 1099 016e C91A     		subs	r1, r1, r3
+ 1100 0170 2162     		str	r1, [r4, #32]
+ 1101              	.L65:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1102              		.loc 1 2120 9 is_stmt 1 view .LVU349
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1103              		.loc 1 2120 9 view .LVU350
+ 1104 0172 6278     		ldrb	r2, [r4, #1]	@ zero_extendqisi2
+ 1105              	.LVL106:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1106              		.loc 1 2120 9 is_stmt 0 view .LVU351
+ 1107 0174 002A     		cmp	r2, #0
+ 1108 0176 3FD1     		bne	.L67
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1109              		.loc 1 2120 9 is_stmt 1 discriminator 1 view .LVU352
+ 1110              	.LBB16:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1111              		.loc 1 2120 9 discriminator 1 view .LVU353
+ 1112 0178 2968     		ldr	r1, [r5]
+ 1113              	.LVL107:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1114              		.loc 1 2120 9 discriminator 1 view .LVU354
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1115              		.loc 1 2120 9 discriminator 1 view .LVU355
+ 1116 017a B1F85020 		ldrh	r2, [r1, #80]
+ 1117 017e 11FA82F2 		uxtah	r2, r1, r2
+ 1118              	.LVL108:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1119              		.loc 1 2120 9 discriminator 1 view .LVU356
+ 1120 0182 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 1121 0184 02EBC102 		add	r2, r2, r1, lsl #3
+ 1122              	.LVL109:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1123              		.loc 1 2120 9 discriminator 1 view .LVU357
+ 1124              	.LBB17:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1125              		.loc 1 2120 9 discriminator 1 view .LVU358
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 63
+
+
+ 1126              		.loc 1 2120 9 discriminator 1 view .LVU359
+ 1127 0188 3E2B     		cmp	r3, #62
+ 1128 018a 18D9     		bls	.L68
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1129              		.loc 1 2120 9 discriminator 3 view .LVU360
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1130              		.loc 1 2120 9 discriminator 3 view .LVU361
+ 1131 018c 5909     		lsrs	r1, r3, #5
+ 1132              	.LVL110:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1133              		.loc 1 2120 9 discriminator 3 view .LVU362
+ 1134 018e 13F01F0F 		tst	r3, #31
+ 1135 0192 00D1     		bne	.L69
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1136              		.loc 1 2120 9 discriminator 5 view .LVU363
+ 1137 0194 0139     		subs	r1, r1, #1
+ 1138              	.LVL111:
+ 1139              	.L69:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1140              		.loc 1 2120 9 discriminator 7 view .LVU364
+ 1141 0196 6FEAC161 		mvn	r1, r1, lsl #27
+ 1142              	.LVL112:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1143              		.loc 1 2120 9 is_stmt 0 discriminator 7 view .LVU365
+ 1144 019a 6FEA5141 		mvn	r1, r1, lsr #17
+ 1145 019e 89B2     		uxth	r1, r1
+ 1146 01a0 A2F80214 		strh	r1, [r2, #1026]	@ movhi
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1147              		.loc 1 2120 9 is_stmt 1 discriminator 7 view .LVU366
+ 1148 01a4 2AE0     		b	.L70
+ 1149              	.LVL113:
+ 1150              	.L64:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1151              		.loc 1 2120 9 is_stmt 0 discriminator 7 view .LVU367
+ 1152              	.LBE17:
+ 1153              	.LBE16:
+2106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1154              		.loc 1 2106 14 is_stmt 1 view .LVU368
+2106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1155              		.loc 1 2106 17 is_stmt 0 view .LVU369
+ 1156 01a6 21B9     		cbnz	r1, .L66
+2108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_fill_db = 0U;
+ 1157              		.loc 1 2108 11 is_stmt 1 view .LVU370
+ 1158              	.LVL114:
+2109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1159              		.loc 1 2109 11 view .LVU371
+2109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1160              		.loc 1 2109 28 is_stmt 0 view .LVU372
+ 1161 01a8 0023     		movs	r3, #0
+ 1162 01aa 84F82430 		strb	r3, [r4, #36]
+2108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_fill_db = 0U;
+ 1163              		.loc 1 2108 15 view .LVU373
+ 1164 01ae 1346     		mov	r3, r2
+ 1165 01b0 DFE7     		b	.L65
+ 1166              	.LVL115:
+ 1167              	.L66:
+2113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           len = ep->xfer_len_db;
+ARM GAS  /tmp/ccJPteqL.s 			page 64
+
+
+ 1168              		.loc 1 2113 11 is_stmt 1 view .LVU374
+2113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           len = ep->xfer_len_db;
+ 1169              		.loc 1 2113 28 is_stmt 0 view .LVU375
+ 1170 01b2 0023     		movs	r3, #0
+ 1171 01b4 84F82430 		strb	r3, [r4, #36]
+2114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_len_db = 0U;
+ 1172              		.loc 1 2114 11 is_stmt 1 view .LVU376
+ 1173              	.LVL116:
+2115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1174              		.loc 1 2115 11 view .LVU377
+2115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1175              		.loc 1 2115 27 is_stmt 0 view .LVU378
+ 1176 01b8 2362     		str	r3, [r4, #32]
+2114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_len_db = 0U;
+ 1177              		.loc 1 2114 15 view .LVU379
+ 1178 01ba 0B46     		mov	r3, r1
+ 1179 01bc D9E7     		b	.L65
+ 1180              	.LVL117:
+ 1181              	.L68:
+ 1182              	.LBB19:
+ 1183              	.LBB18:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1184              		.loc 1 2120 9 is_stmt 1 discriminator 4 view .LVU380
+ 1185 01be 8BB9     		cbnz	r3, .L71
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1186              		.loc 1 2120 9 discriminator 9 view .LVU381
+ 1187 01c0 B2F80214 		ldrh	r1, [r2, #1026]
+ 1188 01c4 89B2     		uxth	r1, r1
+ 1189 01c6 21F4F841 		bic	r1, r1, #31744
+ 1190 01ca 89B2     		uxth	r1, r1
+ 1191 01cc A2F80214 		strh	r1, [r2, #1026]	@ movhi
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1192              		.loc 1 2120 9 discriminator 9 view .LVU382
+ 1193 01d0 B2F80214 		ldrh	r1, [r2, #1026]
+ 1194 01d4 6FEA4141 		mvn	r1, r1, lsl #17
+ 1195 01d8 6FEA5141 		mvn	r1, r1, lsr #17
+ 1196 01dc 89B2     		uxth	r1, r1
+ 1197 01de A2F80214 		strh	r1, [r2, #1026]	@ movhi
+ 1198 01e2 0BE0     		b	.L70
+ 1199              	.L71:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1200              		.loc 1 2120 9 discriminator 10 view .LVU383
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1201              		.loc 1 2120 9 discriminator 10 view .LVU384
+ 1202 01e4 5908     		lsrs	r1, r3, #1
+ 1203              	.LVL118:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1204              		.loc 1 2120 9 discriminator 10 view .LVU385
+ 1205 01e6 13F0010F 		tst	r3, #1
+ 1206 01ea 00D0     		beq	.L72
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1207              		.loc 1 2120 9 discriminator 12 view .LVU386
+ 1208 01ec 0131     		adds	r1, r1, #1
+ 1209              	.LVL119:
+ 1210              	.L72:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1211              		.loc 1 2120 9 discriminator 14 view .LVU387
+ARM GAS  /tmp/ccJPteqL.s 			page 65
+
+
+ 1212 01ee 8902     		lsls	r1, r1, #10
+ 1213              	.LVL120:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1214              		.loc 1 2120 9 is_stmt 0 discriminator 14 view .LVU388
+ 1215 01f0 89B2     		uxth	r1, r1
+ 1216 01f2 A2F80214 		strh	r1, [r2, #1026]	@ movhi
+ 1217 01f6 01E0     		b	.L70
+ 1218              	.LVL121:
+ 1219              	.L67:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1220              		.loc 1 2120 9 discriminator 14 view .LVU389
+ 1221              	.LBE18:
+ 1222              	.LBE19:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1223              		.loc 1 2120 9 is_stmt 1 discriminator 2 view .LVU390
+ 1224 01f8 012A     		cmp	r2, #1
+ 1225 01fa 06D0     		beq	.L92
+ 1226              	.L70:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1227              		.loc 1 2120 9 discriminator 18 view .LVU391
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1228              		.loc 1 2120 9 discriminator 18 view .LVU392
+2123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1229              		.loc 1 2123 9 discriminator 18 view .LVU393
+ 1230 01fc 9BB2     		uxth	r3, r3
+ 1231              	.LVL122:
+2123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1232              		.loc 1 2123 9 is_stmt 0 discriminator 18 view .LVU394
+ 1233 01fe 2289     		ldrh	r2, [r4, #8]
+ 1234 0200 6169     		ldr	r1, [r4, #20]
+ 1235 0202 2868     		ldr	r0, [r5]
+ 1236 0204 FFF7FEFF 		bl	USB_WritePMA
+ 1237              	.LVL123:
+ 1238 0208 94E7     		b	.L62
+ 1239              	.LVL124:
+ 1240              	.L92:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1241              		.loc 1 2120 9 is_stmt 1 discriminator 16 view .LVU395
+ 1242              	.LBB20:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1243              		.loc 1 2120 9 discriminator 16 view .LVU396
+ 1244 020a 2968     		ldr	r1, [r5]
+ 1245              	.LVL125:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1246              		.loc 1 2120 9 discriminator 16 view .LVU397
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1247              		.loc 1 2120 9 discriminator 16 view .LVU398
+ 1248 020c B1F85020 		ldrh	r2, [r1, #80]
+ 1249 0210 11FA82F2 		uxtah	r2, r1, r2
+ 1250              	.LVL126:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1251              		.loc 1 2120 9 discriminator 16 view .LVU399
+ 1252 0214 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 1253 0216 02EBC102 		add	r2, r2, r1, lsl #3
+ 1254              	.LVL127:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1255              		.loc 1 2120 9 discriminator 16 view .LVU400
+ARM GAS  /tmp/ccJPteqL.s 			page 66
+
+
+ 1256 021a 99B2     		uxth	r1, r3
+ 1257 021c A2F80214 		strh	r1, [r2, #1026]	@ movhi
+ 1258 0220 ECE7     		b	.L70
+ 1259              	.LVL128:
+ 1260              	.L54:
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1261              		.loc 1 2120 9 is_stmt 0 discriminator 16 view .LVU401
+ 1262              	.LBE20:
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1263              		.loc 1 2130 5 is_stmt 1 view .LVU402
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1264              		.loc 1 2130 27 is_stmt 0 view .LVU403
+ 1265 0222 0268     		ldr	r2, [r0]
+ 1266              	.LVL129:
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1267              		.loc 1 2130 27 view .LVU404
+ 1268 0224 B2F85030 		ldrh	r3, [r2, #80]
+ 1269 0228 0978     		ldrb	r1, [r1]	@ zero_extendqisi2
+ 1270              	.LVL130:
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1271              		.loc 1 2130 27 view .LVU405
+ 1272 022a C800     		lsls	r0, r1, #3
+ 1273              	.LVL131:
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1274              		.loc 1 2130 27 view .LVU406
+ 1275 022c 10FA83F3 		uxtah	r3, r0, r3
+ 1276 0230 1344     		add	r3, r3, r2
+ 1277 0232 B3F80624 		ldrh	r2, [r3, #1030]
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1278              		.loc 1 2130 15 view .LVU407
+ 1279 0236 C2F30902 		ubfx	r2, r2, #0, #10
+ 1280              	.LVL132:
+2132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 1281              		.loc 1 2132 5 is_stmt 1 view .LVU408
+2132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 1282              		.loc 1 2132 11 is_stmt 0 view .LVU409
+ 1283 023a A369     		ldr	r3, [r4, #24]
+2132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 1284              		.loc 1 2132 8 view .LVU410
+ 1285 023c 9342     		cmp	r3, r2
+ 1286 023e 52D3     		bcc	.L73
+2134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 1287              		.loc 1 2134 7 is_stmt 1 view .LVU411
+2134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 1288              		.loc 1 2134 20 is_stmt 0 view .LVU412
+ 1289 0240 9B1A     		subs	r3, r3, r2
+ 1290 0242 A361     		str	r3, [r4, #24]
+ 1291              	.L74:
+2142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 1292              		.loc 1 2142 5 is_stmt 1 view .LVU413
+2142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 1293              		.loc 1 2142 11 is_stmt 0 view .LVU414
+ 1294 0244 A369     		ldr	r3, [r4, #24]
+2142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 1295              		.loc 1 2142 8 view .LVU415
+ 1296 0246 002B     		cmp	r3, #0
+ 1297 0248 69D1     		bne	.L75
+ARM GAS  /tmp/ccJPteqL.s 			page 67
+
+
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1298              		.loc 1 2144 7 is_stmt 1 view .LVU416
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1299              		.loc 1 2144 7 view .LVU417
+ 1300 024a 6378     		ldrb	r3, [r4, #1]	@ zero_extendqisi2
+ 1301 024c 002B     		cmp	r3, #0
+ 1302 024e 4DD1     		bne	.L76
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1303              		.loc 1 2144 7 discriminator 1 view .LVU418
+ 1304              	.LBB21:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1305              		.loc 1 2144 7 discriminator 1 view .LVU419
+ 1306 0250 2A68     		ldr	r2, [r5]
+ 1307              	.LVL133:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1308              		.loc 1 2144 7 discriminator 1 view .LVU420
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1309              		.loc 1 2144 7 discriminator 1 view .LVU421
+ 1310 0252 B2F85030 		ldrh	r3, [r2, #80]
+ 1311 0256 12FA83F3 		uxtah	r3, r2, r3
+ 1312              	.LVL134:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1313              		.loc 1 2144 7 discriminator 1 view .LVU422
+ 1314 025a 0344     		add	r3, r3, r0
+ 1315              	.LVL135:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1316              		.loc 1 2144 7 discriminator 1 view .LVU423
+ 1317              	.LBB22:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1318              		.loc 1 2144 7 discriminator 1 view .LVU424
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1319              		.loc 1 2144 7 discriminator 1 view .LVU425
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1320              		.loc 1 2144 7 discriminator 1 view .LVU426
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1321              		.loc 1 2144 7 discriminator 1 view .LVU427
+ 1322 025c B3F80224 		ldrh	r2, [r3, #1026]
+ 1323 0260 92B2     		uxth	r2, r2
+ 1324 0262 22F4F842 		bic	r2, r2, #31744
+ 1325 0266 92B2     		uxth	r2, r2
+ 1326 0268 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1327              		.loc 1 2144 7 discriminator 1 view .LVU428
+ 1328 026c B3F80224 		ldrh	r2, [r3, #1026]
+ 1329 0270 6FEA4242 		mvn	r2, r2, lsl #17
+ 1330 0274 6FEA5242 		mvn	r2, r2, lsr #17
+ 1331 0278 92B2     		uxth	r2, r2
+ 1332 027a A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 1333              	.LVL136:
+ 1334              	.L77:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1335              		.loc 1 2144 7 is_stmt 0 discriminator 1 view .LVU429
+ 1336              	.LBE22:
+ 1337              	.LBE21:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1338              		.loc 1 2144 7 is_stmt 1 discriminator 18 view .LVU430
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ARM GAS  /tmp/ccJPteqL.s 			page 68
+
+
+ 1339              		.loc 1 2144 7 discriminator 18 view .LVU431
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1340              		.loc 1 2145 7 discriminator 18 view .LVU432
+ 1341              	.LBB23:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1342              		.loc 1 2145 7 discriminator 18 view .LVU433
+ 1343 027e 2A68     		ldr	r2, [r5]
+ 1344              	.LVL137:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1345              		.loc 1 2145 7 discriminator 18 view .LVU434
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1346              		.loc 1 2145 7 discriminator 18 view .LVU435
+ 1347 0280 6378     		ldrb	r3, [r4, #1]	@ zero_extendqisi2
+ 1348 0282 002B     		cmp	r3, #0
+ 1349 0284 3ED1     		bne	.L78
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1350              		.loc 1 2145 7 discriminator 1 view .LVU436
+ 1351              	.LBB24:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1352              		.loc 1 2145 7 discriminator 1 view .LVU437
+ 1353              	.LVL138:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1354              		.loc 1 2145 7 discriminator 1 view .LVU438
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1355              		.loc 1 2145 7 discriminator 1 view .LVU439
+ 1356 0286 B2F85030 		ldrh	r3, [r2, #80]
+ 1357 028a 12FA83F3 		uxtah	r3, r2, r3
+ 1358              	.LVL139:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1359              		.loc 1 2145 7 discriminator 1 view .LVU440
+ 1360 028e 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 1361              	.LVL140:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1362              		.loc 1 2145 7 is_stmt 0 discriminator 1 view .LVU441
+ 1363 0290 03EBC203 		add	r3, r3, r2, lsl #3
+ 1364              	.LVL141:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1365              		.loc 1 2145 7 is_stmt 1 discriminator 1 view .LVU442
+ 1366              	.LBB25:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1367              		.loc 1 2145 7 discriminator 1 view .LVU443
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1368              		.loc 1 2145 7 discriminator 1 view .LVU444
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1369              		.loc 1 2145 7 discriminator 1 view .LVU445
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1370              		.loc 1 2145 7 discriminator 1 view .LVU446
+ 1371 0294 B3F80624 		ldrh	r2, [r3, #1030]
+ 1372 0298 92B2     		uxth	r2, r2
+ 1373 029a 22F4F842 		bic	r2, r2, #31744
+ 1374 029e 92B2     		uxth	r2, r2
+ 1375 02a0 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 1376              	.LVL142:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1377              		.loc 1 2145 7 discriminator 1 view .LVU447
+ 1378 02a4 B3F80624 		ldrh	r2, [r3, #1030]
+ 1379 02a8 6FEA4242 		mvn	r2, r2, lsl #17
+ARM GAS  /tmp/ccJPteqL.s 			page 69
+
+
+ 1380 02ac 6FEA5242 		mvn	r2, r2, lsr #17
+ 1381 02b0 92B2     		uxth	r2, r2
+ 1382 02b2 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 1383              	.LVL143:
+ 1384              	.L79:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1385              		.loc 1 2145 7 is_stmt 0 discriminator 1 view .LVU448
+ 1386              	.LBE25:
+ 1387              	.LBE24:
+ 1388              	.LBE23:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1389              		.loc 1 2145 7 is_stmt 1 discriminator 18 view .LVU449
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 1390              		.loc 1 2151 7 discriminator 18 view .LVU450
+ 1391 02b6 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 1392 02b8 2846     		mov	r0, r5
+ 1393 02ba FFF7FEFF 		bl	HAL_PCD_DataInStageCallback
+ 1394              	.LVL144:
+2155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ 1395              		.loc 1 2155 7 discriminator 18 view .LVU451
+2155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ 1396              		.loc 1 2155 10 is_stmt 0 discriminator 18 view .LVU452
+ 1397 02be 16F4804F 		tst	r6, #16384
+ 1398 02c2 7FF437AF 		bne	.L62
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1399              		.loc 1 2157 9 is_stmt 1 discriminator 4 view .LVU453
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1400              		.loc 1 2157 9 discriminator 4 view .LVU454
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1401              		.loc 1 2157 9 discriminator 4 view .LVU455
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1402              		.loc 1 2157 9 discriminator 4 view .LVU456
+ 1403              	.LBB26:
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1404              		.loc 1 2157 9 discriminator 4 view .LVU457
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1405              		.loc 1 2157 9 discriminator 4 view .LVU458
+ 1406 02c6 2A68     		ldr	r2, [r5]
+ 1407 02c8 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 1408 02ca 32F82130 		ldrh	r3, [r2, r1, lsl #2]
+ 1409 02ce 9BB2     		uxth	r3, r3
+ 1410 02d0 23F4E043 		bic	r3, r3, #28672
+ 1411 02d4 23F07003 		bic	r3, r3, #112
+ 1412              	.LVL145:
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1413              		.loc 1 2157 9 discriminator 4 view .LVU459
+ 1414 02d8 43F44043 		orr	r3, r3, #49152
+ 1415              	.LVL146:
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1416              		.loc 1 2157 9 is_stmt 0 discriminator 4 view .LVU460
+ 1417 02dc 43F08003 		orr	r3, r3, #128
+ 1418 02e0 22F82130 		strh	r3, [r2, r1, lsl #2]	@ movhi
+ 1419 02e4 26E7     		b	.L62
+ 1420              	.LVL147:
+ 1421              	.L73:
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1422              		.loc 1 2157 9 discriminator 4 view .LVU461
+ARM GAS  /tmp/ccJPteqL.s 			page 70
+
+
+ 1423              	.LBE26:
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 1424              		.loc 1 2138 7 is_stmt 1 view .LVU462
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     }
+ 1425              		.loc 1 2138 20 is_stmt 0 view .LVU463
+ 1426 02e6 0023     		movs	r3, #0
+ 1427 02e8 A361     		str	r3, [r4, #24]
+ 1428 02ea ABE7     		b	.L74
+ 1429              	.L76:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1430              		.loc 1 2144 7 is_stmt 1 discriminator 2 view .LVU464
+ 1431 02ec 012B     		cmp	r3, #1
+ 1432 02ee C6D1     		bne	.L77
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1433              		.loc 1 2144 7 discriminator 16 view .LVU465
+ 1434              	.LBB27:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1435              		.loc 1 2144 7 discriminator 16 view .LVU466
+ 1436 02f0 2A68     		ldr	r2, [r5]
+ 1437              	.LVL148:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1438              		.loc 1 2144 7 discriminator 16 view .LVU467
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1439              		.loc 1 2144 7 discriminator 16 view .LVU468
+ 1440 02f2 B2F85030 		ldrh	r3, [r2, #80]
+ 1441 02f6 12FA83F3 		uxtah	r3, r2, r3
+ 1442              	.LVL149:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1443              		.loc 1 2144 7 discriminator 16 view .LVU469
+ 1444 02fa 0344     		add	r3, r3, r0
+ 1445              	.LVL150:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1446              		.loc 1 2144 7 discriminator 16 view .LVU470
+ 1447 02fc 0022     		movs	r2, #0
+ 1448 02fe A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 1449 0302 BCE7     		b	.L77
+ 1450              	.LVL151:
+ 1451              	.L78:
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ 1452              		.loc 1 2144 7 is_stmt 0 discriminator 16 view .LVU471
+ 1453              	.LBE27:
+ 1454              	.LBB28:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1455              		.loc 1 2145 7 is_stmt 1 discriminator 2 view .LVU472
+ 1456 0304 012B     		cmp	r3, #1
+ 1457 0306 D6D1     		bne	.L79
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1458              		.loc 1 2145 7 discriminator 16 view .LVU473
+ 1459 0308 B2F85030 		ldrh	r3, [r2, #80]
+ 1460 030c 12FA83F3 		uxtah	r3, r2, r3
+ 1461              	.LVL152:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1462              		.loc 1 2145 7 discriminator 16 view .LVU474
+ 1463 0310 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 1464 0312 03EBC203 		add	r3, r3, r2, lsl #3
+ 1465              	.LVL153:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 71
+
+
+ 1466              		.loc 1 2145 7 discriminator 16 view .LVU475
+ 1467 0316 0022     		movs	r2, #0
+ 1468 0318 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 1469 031c CBE7     		b	.L79
+ 1470              	.LVL154:
+ 1471              	.L75:
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1472              		.loc 1 2145 7 is_stmt 0 discriminator 16 view .LVU476
+ 1473              	.LBE28:
+2163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ 1474              		.loc 1 2163 7 is_stmt 1 view .LVU477
+2163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ 1475              		.loc 1 2163 10 is_stmt 0 view .LVU478
+ 1476 031e 16F4804F 		tst	r6, #16384
+ 1477 0322 0DD1     		bne	.L80
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1478              		.loc 1 2165 9 is_stmt 1 discriminator 4 view .LVU479
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1479              		.loc 1 2165 9 discriminator 4 view .LVU480
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1480              		.loc 1 2165 9 discriminator 4 view .LVU481
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1481              		.loc 1 2165 9 discriminator 4 view .LVU482
+ 1482              	.LBB29:
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1483              		.loc 1 2165 9 discriminator 4 view .LVU483
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1484              		.loc 1 2165 9 discriminator 4 view .LVU484
+ 1485 0324 2868     		ldr	r0, [r5]
+ 1486 0326 30F82130 		ldrh	r3, [r0, r1, lsl #2]
+ 1487 032a 9BB2     		uxth	r3, r3
+ 1488 032c 23F4E043 		bic	r3, r3, #28672
+ 1489 0330 23F07003 		bic	r3, r3, #112
+ 1490              	.LVL155:
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1491              		.loc 1 2165 9 discriminator 4 view .LVU485
+ 1492 0334 43F44043 		orr	r3, r3, #49152
+ 1493              	.LVL156:
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1494              		.loc 1 2165 9 is_stmt 0 discriminator 4 view .LVU486
+ 1495 0338 43F08003 		orr	r3, r3, #128
+ 1496 033c 20F82130 		strh	r3, [r0, r1, lsl #2]	@ movhi
+ 1497              	.LVL157:
+ 1498              	.L80:
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1499              		.loc 1 2165 9 discriminator 4 view .LVU487
+ 1500              	.LBE29:
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1501              		.loc 1 2165 9 is_stmt 1 discriminator 6 view .LVU488
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1502              		.loc 1 2165 9 discriminator 6 view .LVU489
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ 1503              		.loc 1 2169 7 discriminator 6 view .LVU490
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ 1504              		.loc 1 2169 13 is_stmt 0 discriminator 6 view .LVU491
+ 1505 0340 94F82430 		ldrb	r3, [r4, #36]	@ zero_extendqisi2
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ARM GAS  /tmp/ccJPteqL.s 			page 72
+
+
+ 1506              		.loc 1 2169 10 discriminator 6 view .LVU492
+ 1507 0344 012B     		cmp	r3, #1
+ 1508 0346 7FF4F5AE 		bne	.L62
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_count += TxPctSize;
+ 1509              		.loc 1 2171 9 is_stmt 1 view .LVU493
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_count += TxPctSize;
+ 1510              		.loc 1 2171 11 is_stmt 0 view .LVU494
+ 1511 034a 6369     		ldr	r3, [r4, #20]
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_count += TxPctSize;
+ 1512              		.loc 1 2171 23 view .LVU495
+ 1513 034c 1344     		add	r3, r3, r2
+ 1514 034e 6361     		str	r3, [r4, #20]
+2172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1515              		.loc 1 2172 9 is_stmt 1 view .LVU496
+2172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1516              		.loc 1 2172 11 is_stmt 0 view .LVU497
+ 1517 0350 E369     		ldr	r3, [r4, #28]
+2172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1518              		.loc 1 2172 24 view .LVU498
+ 1519 0352 1344     		add	r3, r3, r2
+ 1520 0354 E361     		str	r3, [r4, #28]
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1521              		.loc 1 2175 9 is_stmt 1 view .LVU499
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1522              		.loc 1 2175 15 is_stmt 0 view .LVU500
+ 1523 0356 216A     		ldr	r1, [r4, #32]
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1524              		.loc 1 2175 34 view .LVU501
+ 1525 0358 2369     		ldr	r3, [r4, #16]
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1526              		.loc 1 2175 12 view .LVU502
+ 1527 035a 9942     		cmp	r1, r3
+ 1528 035c 1BD3     		bcc	.L81
+2177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_len_db -= len;
+ 1529              		.loc 1 2177 11 is_stmt 1 view .LVU503
+ 1530              	.LVL158:
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1531              		.loc 1 2178 11 view .LVU504
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1532              		.loc 1 2178 27 is_stmt 0 view .LVU505
+ 1533 035e C91A     		subs	r1, r1, r3
+ 1534 0360 2162     		str	r1, [r4, #32]
+ 1535              	.L82:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1536              		.loc 1 2193 9 is_stmt 1 view .LVU506
+ 1537              	.LBB30:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1538              		.loc 1 2193 9 view .LVU507
+ 1539 0362 2968     		ldr	r1, [r5]
+ 1540              	.LVL159:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1541              		.loc 1 2193 9 view .LVU508
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1542              		.loc 1 2193 9 view .LVU509
+ 1543 0364 6278     		ldrb	r2, [r4, #1]	@ zero_extendqisi2
+ 1544              	.LVL160:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 73
+
+
+ 1545              		.loc 1 2193 9 is_stmt 0 view .LVU510
+ 1546 0366 002A     		cmp	r2, #0
+ 1547 0368 3ED1     		bne	.L84
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1548              		.loc 1 2193 9 is_stmt 1 discriminator 1 view .LVU511
+ 1549              	.LBB31:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1550              		.loc 1 2193 9 discriminator 1 view .LVU512
+ 1551              	.LVL161:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1552              		.loc 1 2193 9 discriminator 1 view .LVU513
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1553              		.loc 1 2193 9 discriminator 1 view .LVU514
+ 1554 036a B1F85020 		ldrh	r2, [r1, #80]
+ 1555 036e 11FA82F2 		uxtah	r2, r1, r2
+ 1556              	.LVL162:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1557              		.loc 1 2193 9 discriminator 1 view .LVU515
+ 1558 0372 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 1559              	.LVL163:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1560              		.loc 1 2193 9 is_stmt 0 discriminator 1 view .LVU516
+ 1561 0374 02EBC102 		add	r2, r2, r1, lsl #3
+ 1562              	.LVL164:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1563              		.loc 1 2193 9 is_stmt 1 discriminator 1 view .LVU517
+ 1564              	.LBB32:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1565              		.loc 1 2193 9 discriminator 1 view .LVU518
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1566              		.loc 1 2193 9 discriminator 1 view .LVU519
+ 1567 0378 3E2B     		cmp	r3, #62
+ 1568 037a 18D9     		bls	.L85
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1569              		.loc 1 2193 9 discriminator 3 view .LVU520
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1570              		.loc 1 2193 9 discriminator 3 view .LVU521
+ 1571 037c 5909     		lsrs	r1, r3, #5
+ 1572              	.LVL165:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1573              		.loc 1 2193 9 discriminator 3 view .LVU522
+ 1574 037e 13F01F0F 		tst	r3, #31
+ 1575 0382 00D1     		bne	.L86
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1576              		.loc 1 2193 9 discriminator 5 view .LVU523
+ 1577 0384 0139     		subs	r1, r1, #1
+ 1578              	.LVL166:
+ 1579              	.L86:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1580              		.loc 1 2193 9 discriminator 7 view .LVU524
+ 1581 0386 6FEAC161 		mvn	r1, r1, lsl #27
+ 1582              	.LVL167:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1583              		.loc 1 2193 9 is_stmt 0 discriminator 7 view .LVU525
+ 1584 038a 6FEA5141 		mvn	r1, r1, lsr #17
+ 1585 038e 89B2     		uxth	r1, r1
+ 1586 0390 A2F80614 		strh	r1, [r2, #1030]	@ movhi
+ARM GAS  /tmp/ccJPteqL.s 			page 74
+
+
+ 1587              	.LVL168:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1588              		.loc 1 2193 9 is_stmt 1 discriminator 7 view .LVU526
+ 1589 0394 2AE0     		b	.L87
+ 1590              	.LVL169:
+ 1591              	.L81:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1592              		.loc 1 2193 9 is_stmt 0 discriminator 7 view .LVU527
+ 1593              	.LBE32:
+ 1594              	.LBE31:
+ 1595              	.LBE30:
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1596              		.loc 1 2180 14 is_stmt 1 view .LVU528
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1597              		.loc 1 2180 17 is_stmt 0 view .LVU529
+ 1598 0396 21B9     		cbnz	r1, .L83
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_fill_db = 0U;
+ 1599              		.loc 1 2182 11 is_stmt 1 view .LVU530
+ 1600              	.LVL170:
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1601              		.loc 1 2183 11 view .LVU531
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1602              		.loc 1 2183 28 is_stmt 0 view .LVU532
+ 1603 0398 0023     		movs	r3, #0
+ 1604 039a 84F82430 		strb	r3, [r4, #36]
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_fill_db = 0U;
+ 1605              		.loc 1 2182 15 view .LVU533
+ 1606 039e 1346     		mov	r3, r2
+ 1607 03a0 DFE7     		b	.L82
+ 1608              	.LVL171:
+ 1609              	.L83:
+2187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_len_db = 0U;
+ 1610              		.loc 1 2187 11 is_stmt 1 view .LVU534
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_fill_db = 0;
+ 1611              		.loc 1 2188 11 view .LVU535
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_fill_db = 0;
+ 1612              		.loc 1 2188 27 is_stmt 0 view .LVU536
+ 1613 03a2 0023     		movs	r3, #0
+ 1614 03a4 2362     		str	r3, [r4, #32]
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1615              		.loc 1 2189 11 is_stmt 1 view .LVU537
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1616              		.loc 1 2189 28 is_stmt 0 view .LVU538
+ 1617 03a6 84F82430 		strb	r3, [r4, #36]
+2187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           ep->xfer_len_db = 0U;
+ 1618              		.loc 1 2187 15 view .LVU539
+ 1619 03aa 0B46     		mov	r3, r1
+ 1620 03ac D9E7     		b	.L82
+ 1621              	.LVL172:
+ 1622              	.L85:
+ 1623              	.LBB35:
+ 1624              	.LBB34:
+ 1625              	.LBB33:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1626              		.loc 1 2193 9 is_stmt 1 discriminator 4 view .LVU540
+ 1627 03ae 8BB9     		cbnz	r3, .L88
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 75
+
+
+ 1628              		.loc 1 2193 9 discriminator 9 view .LVU541
+ 1629 03b0 B2F80614 		ldrh	r1, [r2, #1030]
+ 1630 03b4 89B2     		uxth	r1, r1
+ 1631 03b6 21F4F841 		bic	r1, r1, #31744
+ 1632 03ba 89B2     		uxth	r1, r1
+ 1633 03bc A2F80614 		strh	r1, [r2, #1030]	@ movhi
+ 1634              	.LVL173:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1635              		.loc 1 2193 9 discriminator 9 view .LVU542
+ 1636 03c0 B2F80614 		ldrh	r1, [r2, #1030]
+ 1637 03c4 6FEA4141 		mvn	r1, r1, lsl #17
+ 1638 03c8 6FEA5141 		mvn	r1, r1, lsr #17
+ 1639 03cc 89B2     		uxth	r1, r1
+ 1640 03ce A2F80614 		strh	r1, [r2, #1030]	@ movhi
+ 1641 03d2 0BE0     		b	.L87
+ 1642              	.LVL174:
+ 1643              	.L88:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1644              		.loc 1 2193 9 discriminator 10 view .LVU543
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1645              		.loc 1 2193 9 discriminator 10 view .LVU544
+ 1646 03d4 5908     		lsrs	r1, r3, #1
+ 1647              	.LVL175:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1648              		.loc 1 2193 9 discriminator 10 view .LVU545
+ 1649 03d6 13F0010F 		tst	r3, #1
+ 1650 03da 00D0     		beq	.L89
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1651              		.loc 1 2193 9 discriminator 12 view .LVU546
+ 1652 03dc 0131     		adds	r1, r1, #1
+ 1653              	.LVL176:
+ 1654              	.L89:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1655              		.loc 1 2193 9 discriminator 14 view .LVU547
+ 1656 03de 8902     		lsls	r1, r1, #10
+ 1657              	.LVL177:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1658              		.loc 1 2193 9 is_stmt 0 discriminator 14 view .LVU548
+ 1659 03e0 89B2     		uxth	r1, r1
+ 1660 03e2 A2F80614 		strh	r1, [r2, #1030]	@ movhi
+ 1661              	.LVL178:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1662              		.loc 1 2193 9 discriminator 14 view .LVU549
+ 1663 03e6 01E0     		b	.L87
+ 1664              	.LVL179:
+ 1665              	.L84:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1666              		.loc 1 2193 9 discriminator 14 view .LVU550
+ 1667              	.LBE33:
+ 1668              	.LBE34:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1669              		.loc 1 2193 9 is_stmt 1 discriminator 2 view .LVU551
+ 1670 03e8 012A     		cmp	r2, #1
+ 1671 03ea 06D0     		beq	.L93
+ 1672              	.LVL180:
+ 1673              	.L87:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 76
+
+
+ 1674              		.loc 1 2193 9 is_stmt 0 discriminator 2 view .LVU552
+ 1675              	.LBE35:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1676              		.loc 1 2193 9 is_stmt 1 discriminator 18 view .LVU553
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1677              		.loc 1 2196 9 discriminator 18 view .LVU554
+ 1678 03ec 9BB2     		uxth	r3, r3
+ 1679              	.LVL181:
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       }
+ 1680              		.loc 1 2196 9 is_stmt 0 discriminator 18 view .LVU555
+ 1681 03ee 6289     		ldrh	r2, [r4, #10]
+ 1682 03f0 6169     		ldr	r1, [r4, #20]
+ 1683 03f2 2868     		ldr	r0, [r5]
+ 1684 03f4 FFF7FEFF 		bl	USB_WritePMA
+ 1685              	.LVL182:
+ 1686 03f8 9CE6     		b	.L62
+ 1687              	.LVL183:
+ 1688              	.L93:
+ 1689              	.LBB36:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1690              		.loc 1 2193 9 is_stmt 1 discriminator 16 view .LVU556
+ 1691 03fa B1F85020 		ldrh	r2, [r1, #80]
+ 1692 03fe 11FA82F2 		uxtah	r2, r1, r2
+ 1693              	.LVL184:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1694              		.loc 1 2193 9 discriminator 16 view .LVU557
+ 1695 0402 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 1696 0404 02EBC102 		add	r2, r2, r1, lsl #3
+ 1697              	.LVL185:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1698              		.loc 1 2193 9 discriminator 16 view .LVU558
+ 1699 0408 99B2     		uxth	r1, r3
+ 1700 040a A2F80614 		strh	r1, [r2, #1030]	@ movhi
+ 1701 040e EDE7     		b	.L87
+ 1702              	.LBE36:
+ 1703              		.cfi_endproc
+ 1704              	.LFE363:
+ 1706              		.section	.text.HAL_PCD_SetupStageCallback,"ax",%progbits
+ 1707              		.align	1
+ 1708              		.weak	HAL_PCD_SetupStageCallback
+ 1709              		.syntax unified
+ 1710              		.thumb
+ 1711              		.thumb_func
+ 1713              	HAL_PCD_SetupStageCallback:
+ 1714              	.LVL186:
+ 1715              	.LFB338:
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 1716              		.loc 1 1187 1 view -0
+ 1717              		.cfi_startproc
+ 1718              		@ args = 0, pretend = 0, frame = 0
+ 1719              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1720              		@ link register save eliminated.
+1189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1721              		.loc 1 1189 3 view .LVU560
+1194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1722              		.loc 1 1194 1 is_stmt 0 view .LVU561
+ 1723 0000 7047     		bx	lr
+ARM GAS  /tmp/ccJPteqL.s 			page 77
+
+
+ 1724              		.cfi_endproc
+ 1725              	.LFE338:
+ 1727              		.section	.text.PCD_EP_ISR_Handler,"ax",%progbits
+ 1728              		.align	1
+ 1729              		.syntax unified
+ 1730              		.thumb
+ 1731              		.thumb_func
+ 1733              	PCD_EP_ISR_Handler:
+ 1734              	.LVL187:
+ 1735              	.LFB361:
+1694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 1736              		.loc 1 1694 1 is_stmt 1 view -0
+ 1737              		.cfi_startproc
+ 1738              		@ args = 0, pretend = 0, frame = 0
+ 1739              		@ frame_needed = 0, uses_anonymous_args = 0
+1694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 1740              		.loc 1 1694 1 is_stmt 0 view .LVU563
+ 1741 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 1742              	.LCFI12:
+ 1743              		.cfi_def_cfa_offset 24
+ 1744              		.cfi_offset 4, -24
+ 1745              		.cfi_offset 5, -20
+ 1746              		.cfi_offset 6, -16
+ 1747              		.cfi_offset 7, -12
+ 1748              		.cfi_offset 8, -8
+ 1749              		.cfi_offset 14, -4
+ 1750 0004 0546     		mov	r5, r0
+1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint16_t count;
+ 1751              		.loc 1 1695 3 is_stmt 1 view .LVU564
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint16_t wIstr;
+ 1752              		.loc 1 1696 3 view .LVU565
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint16_t wEPVal;
+ 1753              		.loc 1 1697 3 view .LVU566
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint16_t TxPctSize;
+ 1754              		.loc 1 1698 3 view .LVU567
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint8_t epindex;
+ 1755              		.loc 1 1699 3 view .LVU568
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1756              		.loc 1 1700 3 view .LVU569
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 1757              		.loc 1 1703 3 view .LVU570
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 1758              		.loc 1 1703 9 is_stmt 0 view .LVU571
+ 1759 0006 CAE0     		b	.L96
+ 1760              	.LVL188:
+ 1761              	.L127:
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->IN_ep[0];
+ 1762              		.loc 1 1721 9 is_stmt 1 view .LVU572
+ 1763              	.LBB37:
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->IN_ep[0];
+ 1764              		.loc 1 1721 9 view .LVU573
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->IN_ep[0];
+ 1765              		.loc 1 1721 9 view .LVU574
+ 1766 0008 0388     		ldrh	r3, [r0]
+ 1767              	.LVL189:
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->IN_ep[0];
+ 1768              		.loc 1 1721 9 is_stmt 0 view .LVU575
+ARM GAS  /tmp/ccJPteqL.s 			page 78
+
+
+ 1769 000a 9BB2     		uxth	r3, r3
+ 1770 000c 23F4E143 		bic	r3, r3, #28800
+ 1771 0010 23F07003 		bic	r3, r3, #112
+ 1772              	.LVL190:
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->IN_ep[0];
+ 1773              		.loc 1 1721 9 is_stmt 1 view .LVU576
+ 1774 0014 6FEA4343 		mvn	r3, r3, lsl #17
+ 1775              	.LVL191:
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->IN_ep[0];
+ 1776              		.loc 1 1721 9 is_stmt 0 view .LVU577
+ 1777 0018 6FEA5343 		mvn	r3, r3, lsr #17
+ 1778 001c 9BB2     		uxth	r3, r3
+ 1779 001e 0380     		strh	r3, [r0]	@ movhi
+ 1780              	.LBE37:
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->IN_ep[0];
+ 1781              		.loc 1 1721 9 is_stmt 1 view .LVU578
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1782              		.loc 1 1722 9 view .LVU579
+ 1783              	.LVL192:
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_buff += ep->xfer_count;
+ 1784              		.loc 1 1724 9 view .LVU580
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_buff += ep->xfer_count;
+ 1785              		.loc 1 1724 26 is_stmt 0 view .LVU581
+ 1786 0020 2968     		ldr	r1, [r5]
+ 1787 0022 B1F85030 		ldrh	r3, [r1, #80]
+ 1788 0026 95F82820 		ldrb	r2, [r5, #40]	@ zero_extendqisi2
+ 1789 002a D200     		lsls	r2, r2, #3
+ 1790 002c 12FA83F3 		uxtah	r3, r2, r3
+ 1791 0030 0B44     		add	r3, r3, r1
+ 1792 0032 B3F80234 		ldrh	r3, [r3, #1026]
+ 1793 0036 C3F30903 		ubfx	r3, r3, #0, #10
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_buff += ep->xfer_count;
+ 1794              		.loc 1 1724 24 view .LVU582
+ 1795 003a 6B64     		str	r3, [r5, #68]
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1796              		.loc 1 1725 9 is_stmt 1 view .LVU583
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1797              		.loc 1 1725 11 is_stmt 0 view .LVU584
+ 1798 003c EA6B     		ldr	r2, [r5, #60]
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1799              		.loc 1 1725 23 view .LVU585
+ 1800 003e 1A44     		add	r2, r2, r3
+ 1801 0040 EA63     		str	r2, [r5, #60]
+1731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 1802              		.loc 1 1731 9 is_stmt 1 view .LVU586
+ 1803 0042 0021     		movs	r1, #0
+ 1804 0044 2846     		mov	r0, r5
+ 1805 0046 FFF7FEFF 		bl	HAL_PCD_DataInStageCallback
+ 1806              	.LVL193:
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1807              		.loc 1 1734 9 view .LVU587
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1808              		.loc 1 1734 18 is_stmt 0 view .LVU588
+ 1809 004a 95F82430 		ldrb	r3, [r5, #36]	@ zero_extendqisi2
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1810              		.loc 1 1734 12 view .LVU589
+ 1811 004e 002B     		cmp	r3, #0
+ARM GAS  /tmp/ccJPteqL.s 			page 79
+
+
+ 1812 0050 00F0A580 		beq	.L96
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1813              		.loc 1 1734 44 discriminator 1 view .LVU590
+ 1814 0054 2B6C     		ldr	r3, [r5, #64]
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1815              		.loc 1 1734 38 discriminator 1 view .LVU591
+ 1816 0056 002B     		cmp	r3, #0
+ 1817 0058 40F0A180 		bne	.L96
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           hpcd->USB_Address = 0U;
+ 1818              		.loc 1 1736 11 is_stmt 1 view .LVU592
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           hpcd->USB_Address = 0U;
+ 1819              		.loc 1 1736 50 is_stmt 0 view .LVU593
+ 1820 005c 95F82430 		ldrb	r3, [r5, #36]	@ zero_extendqisi2
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           hpcd->USB_Address = 0U;
+ 1821              		.loc 1 1736 15 view .LVU594
+ 1822 0060 2A68     		ldr	r2, [r5]
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           hpcd->USB_Address = 0U;
+ 1823              		.loc 1 1736 33 view .LVU595
+ 1824 0062 43F08003 		orr	r3, r3, #128
+ 1825 0066 A2F84C30 		strh	r3, [r2, #76]	@ movhi
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1826              		.loc 1 1737 11 is_stmt 1 view .LVU596
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 1827              		.loc 1 1737 29 is_stmt 0 view .LVU597
+ 1828 006a 0023     		movs	r3, #0
+ 1829 006c 85F82430 		strb	r3, [r5, #36]
+ 1830 0070 95E0     		b	.L96
+ 1831              	.LVL194:
+ 1832              	.L128:
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1833              		.loc 1 1752 11 is_stmt 1 view .LVU598
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1834              		.loc 1 1752 28 is_stmt 0 view .LVU599
+ 1835 0072 B0F85030 		ldrh	r3, [r0, #80]
+ 1836 0076 95F86821 		ldrb	r2, [r5, #360]	@ zero_extendqisi2
+ 1837              	.LVL195:
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1838              		.loc 1 1752 28 view .LVU600
+ 1839 007a D200     		lsls	r2, r2, #3
+ 1840 007c 12FA83F3 		uxtah	r3, r2, r3
+ 1841 0080 0344     		add	r3, r3, r0
+ 1842 0082 B3F80634 		ldrh	r3, [r3, #1030]
+ 1843 0086 C3F30903 		ubfx	r3, r3, #0, #10
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1844              		.loc 1 1752 26 view .LVU601
+ 1845 008a C5F88431 		str	r3, [r5, #388]
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                       ep->pmaadress, (uint16_t)ep->xfer_count);
+ 1846              		.loc 1 1754 11 is_stmt 1 view .LVU602
+ 1847 008e B5F86E21 		ldrh	r2, [r5, #366]
+ 1848 0092 05F52C71 		add	r1, r5, #688
+ 1849 0096 FFF7FEFF 		bl	USB_ReadPMA
+ 1850              	.LVL196:
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1851              		.loc 1 1758 11 view .LVU603
+ 1852              	.LBB38:
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1853              		.loc 1 1758 11 view .LVU604
+ARM GAS  /tmp/ccJPteqL.s 			page 80
+
+
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1854              		.loc 1 1758 11 view .LVU605
+ 1855 009a 2A68     		ldr	r2, [r5]
+ 1856 009c 1388     		ldrh	r3, [r2]
+ 1857 009e 23F07003 		bic	r3, r3, #112
+ 1858 00a2 1B05     		lsls	r3, r3, #20
+ 1859 00a4 1B0D     		lsrs	r3, r3, #20
+ 1860              	.LVL197:
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1861              		.loc 1 1758 11 view .LVU606
+ 1862 00a6 43F08003 		orr	r3, r3, #128
+ 1863              	.LVL198:
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1864              		.loc 1 1758 11 is_stmt 0 view .LVU607
+ 1865 00aa 1380     		strh	r3, [r2]	@ movhi
+ 1866              	.LBE38:
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1867              		.loc 1 1758 11 is_stmt 1 view .LVU608
+1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 1868              		.loc 1 1764 11 view .LVU609
+ 1869 00ac 2846     		mov	r0, r5
+ 1870 00ae FFF7FEFF 		bl	HAL_PCD_SetupStageCallback
+ 1871              	.LVL199:
+ 1872 00b2 74E0     		b	.L96
+ 1873              	.LVL200:
+ 1874              	.L102:
+ 1875              	.LBB39:
+ 1876              	.LBB40:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 1877              		.loc 1 1791 13 discriminator 2 view .LVU610
+ 1878 00b4 89B9     		cbnz	r1, .L105
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 1879              		.loc 1 1791 13 discriminator 7 view .LVU611
+ 1880 00b6 B3F80624 		ldrh	r2, [r3, #1030]
+ 1881 00ba 92B2     		uxth	r2, r2
+ 1882 00bc 22F4F842 		bic	r2, r2, #31744
+ 1883 00c0 92B2     		uxth	r2, r2
+ 1884 00c2 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 1885              		.loc 1 1791 13 discriminator 7 view .LVU612
+ 1886 00c6 B3F80624 		ldrh	r2, [r3, #1030]
+ 1887 00ca 6FEA4242 		mvn	r2, r2, lsl #17
+ 1888 00ce 6FEA5242 		mvn	r2, r2, lsr #17
+ 1889 00d2 92B2     		uxth	r2, r2
+ 1890 00d4 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 1891 00d8 BFE0     		b	.L104
+ 1892              	.L105:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 1893              		.loc 1 1791 13 discriminator 8 view .LVU613
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 1894              		.loc 1 1791 13 discriminator 8 view .LVU614
+ 1895 00da 4A08     		lsrs	r2, r1, #1
+ 1896              	.LVL201:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 1897              		.loc 1 1791 13 discriminator 8 view .LVU615
+ 1898 00dc 11F0010F 		tst	r1, #1
+ 1899 00e0 00D0     		beq	.L106
+ARM GAS  /tmp/ccJPteqL.s 			page 81
+
+
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 1900              		.loc 1 1791 13 discriminator 10 view .LVU616
+ 1901 00e2 0132     		adds	r2, r2, #1
+ 1902              	.LVL202:
+ 1903              	.L106:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 1904              		.loc 1 1791 13 discriminator 12 view .LVU617
+ 1905 00e4 9202     		lsls	r2, r2, #10
+ 1906              	.LVL203:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 1907              		.loc 1 1791 13 is_stmt 0 discriminator 12 view .LVU618
+ 1908 00e6 92B2     		uxth	r2, r2
+ 1909 00e8 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 1910 00ec B5E0     		b	.L104
+ 1911              	.LVL204:
+ 1912              	.L97:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 1913              		.loc 1 1791 13 discriminator 12 view .LVU619
+ 1914              	.LBE40:
+ 1915              	.LBE39:
+1801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1916              		.loc 1 1801 7 is_stmt 1 view .LVU620
+1801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1917              		.loc 1 1801 14 is_stmt 0 view .LVU621
+ 1918 00ee 30F82430 		ldrh	r3, [r0, r4, lsl #2]
+ 1919              	.LVL205:
+1801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1920              		.loc 1 1801 14 view .LVU622
+ 1921 00f2 9EB2     		uxth	r6, r3
+ 1922              	.LVL206:
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ 1923              		.loc 1 1803 7 is_stmt 1 view .LVU623
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ 1924              		.loc 1 1803 10 is_stmt 0 view .LVU624
+ 1925 00f4 13F4004F 		tst	r3, #32768
+ 1926 00f8 40F0BE80 		bne	.L125
+ 1927              	.L107:
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ 1928              		.loc 1 1875 7 is_stmt 1 view .LVU625
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ 1929              		.loc 1 1875 10 is_stmt 0 view .LVU626
+ 1930 00fc 16F0800F 		tst	r6, #128
+ 1931 0100 4DD0     		beq	.L96
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1932              		.loc 1 1877 9 is_stmt 1 view .LVU627
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1933              		.loc 1 1877 12 is_stmt 0 view .LVU628
+ 1934 0102 621C     		adds	r2, r4, #1
+ 1935 0104 02EB8201 		add	r1, r2, r2, lsl #2
+ 1936 0108 05EBC101 		add	r1, r5, r1, lsl #3
+ 1937              	.LVL207:
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1938              		.loc 1 1880 9 is_stmt 1 view .LVU629
+ 1939              	.LBB42:
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1940              		.loc 1 1880 9 view .LVU630
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 82
+
+
+ 1941              		.loc 1 1880 9 view .LVU631
+ 1942 010c 2868     		ldr	r0, [r5]
+ 1943 010e 30F82430 		ldrh	r3, [r0, r4, lsl #2]
+ 1944 0112 9BB2     		uxth	r3, r3
+ 1945 0114 23F4E143 		bic	r3, r3, #28800
+ 1946 0118 23F07003 		bic	r3, r3, #112
+ 1947              	.LVL208:
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1948              		.loc 1 1880 9 view .LVU632
+ 1949 011c 6FEA4343 		mvn	r3, r3, lsl #17
+ 1950              	.LVL209:
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1951              		.loc 1 1880 9 is_stmt 0 view .LVU633
+ 1952 0120 6FEA5343 		mvn	r3, r3, lsr #17
+ 1953 0124 9BB2     		uxth	r3, r3
+ 1954 0126 20F82430 		strh	r3, [r0, r4, lsl #2]	@ movhi
+ 1955              	.LBE42:
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1956              		.loc 1 1880 9 is_stmt 1 view .LVU634
+1882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1957              		.loc 1 1882 9 view .LVU635
+1882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1958              		.loc 1 1882 15 is_stmt 0 view .LVU636
+ 1959 012a CB78     		ldrb	r3, [r1, #3]	@ zero_extendqisi2
+1882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 1960              		.loc 1 1882 12 view .LVU637
+ 1961 012c 022B     		cmp	r3, #2
+ 1962 012e 00F0A781 		beq	.L114
+1884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1963              		.loc 1 1884 11 is_stmt 1 view .LVU638
+1884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 1964              		.loc 1 1884 24 is_stmt 0 view .LVU639
+ 1965 0132 04EB8403 		add	r3, r4, r4, lsl #2
+ 1966 0136 05EBC303 		add	r3, r5, r3, lsl #3
+ 1967 013a 0022     		movs	r2, #0
+ 1968 013c 1A64     		str	r2, [r3, #64]
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 1969              		.loc 1 1887 11 is_stmt 1 view .LVU640
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 1970              		.loc 1 1887 17 is_stmt 0 view .LVU641
+ 1971 013e 93F83430 		ldrb	r3, [r3, #52]	@ zero_extendqisi2
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 1972              		.loc 1 1887 14 view .LVU642
+ 1973 0142 23B3     		cbz	r3, .L115
+1889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+ 1974              		.loc 1 1889 13 is_stmt 1 view .LVU643
+1889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+ 1975              		.loc 1 1889 16 is_stmt 0 view .LVU644
+ 1976 0144 16F0400F 		tst	r6, #64
+ 1977 0148 00F06381 		beq	.L116
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 1978              		.loc 1 1891 15 is_stmt 1 view .LVU645
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 1979              		.loc 1 1891 15 view .LVU646
+ 1980 014c 4B78     		ldrb	r3, [r1, #1]	@ zero_extendqisi2
+ 1981 014e 002B     		cmp	r3, #0
+ 1982 0150 40F04C81 		bne	.L117
+ARM GAS  /tmp/ccJPteqL.s 			page 83
+
+
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 1983              		.loc 1 1891 15 discriminator 1 view .LVU647
+ 1984              	.LBB43:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 1985              		.loc 1 1891 15 discriminator 1 view .LVU648
+ 1986 0154 2A68     		ldr	r2, [r5]
+ 1987              	.LVL210:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 1988              		.loc 1 1891 15 discriminator 1 view .LVU649
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 1989              		.loc 1 1891 15 discriminator 1 view .LVU650
+ 1990 0156 B2F85030 		ldrh	r3, [r2, #80]
+ 1991 015a 12FA83F3 		uxtah	r3, r2, r3
+ 1992              	.LVL211:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 1993              		.loc 1 1891 15 discriminator 1 view .LVU651
+ 1994 015e 621C     		adds	r2, r4, #1
+ 1995 0160 02EB8202 		add	r2, r2, r2, lsl #2
+ 1996 0164 15F83220 		ldrb	r2, [r5, r2, lsl #3]	@ zero_extendqisi2
+ 1997 0168 03EBC203 		add	r3, r3, r2, lsl #3
+ 1998              	.LVL212:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 1999              		.loc 1 1891 15 discriminator 1 view .LVU652
+ 2000              	.LBB44:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2001              		.loc 1 1891 15 discriminator 1 view .LVU653
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2002              		.loc 1 1891 15 discriminator 1 view .LVU654
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2003              		.loc 1 1891 15 discriminator 1 view .LVU655
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2004              		.loc 1 1891 15 discriminator 1 view .LVU656
+ 2005 016c B3F80224 		ldrh	r2, [r3, #1026]
+ 2006 0170 92B2     		uxth	r2, r2
+ 2007 0172 22F4F842 		bic	r2, r2, #31744
+ 2008 0176 92B2     		uxth	r2, r2
+ 2009 0178 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2010              		.loc 1 1891 15 discriminator 1 view .LVU657
+ 2011 017c B3F80224 		ldrh	r2, [r3, #1026]
+ 2012 0180 6FEA4242 		mvn	r2, r2, lsl #17
+ 2013 0184 6FEA5242 		mvn	r2, r2, lsr #17
+ 2014 0188 92B2     		uxth	r2, r2
+ 2015 018a A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 2016              	.LVL213:
+ 2017              	.L115:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2018              		.loc 1 1891 15 is_stmt 0 discriminator 1 view .LVU658
+ 2019              	.LBE44:
+ 2020              	.LBE43:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2021              		.loc 1 1895 15 is_stmt 1 discriminator 18 view .LVU659
+1904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 2022              		.loc 1 1904 11 discriminator 18 view .LVU660
+ 2023 018e 0134     		adds	r4, r4, #1
+ 2024 0190 04EB8404 		add	r4, r4, r4, lsl #2
+ 2025 0194 15F83410 		ldrb	r1, [r5, r4, lsl #3]	@ zero_extendqisi2
+ARM GAS  /tmp/ccJPteqL.s 			page 84
+
+
+ 2026              	.LVL214:
+1904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 2027              		.loc 1 1904 11 is_stmt 0 discriminator 18 view .LVU661
+ 2028 0198 2846     		mov	r0, r5
+ 2029 019a FFF7FEFF 		bl	HAL_PCD_DataInStageCallback
+ 2030              	.LVL215:
+ 2031              	.L96:
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 2032              		.loc 1 1703 48 is_stmt 1 view .LVU662
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 2033              		.loc 1 1703 15 is_stmt 0 view .LVU663
+ 2034 019e 2868     		ldr	r0, [r5]
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 2035              		.loc 1 1703 25 view .LVU664
+ 2036 01a0 B0F84430 		ldrh	r3, [r0, #68]
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 2037              		.loc 1 1703 48 view .LVU665
+ 2038 01a4 13F4004F 		tst	r3, #32768
+ 2039 01a8 00F0B281 		beq	.L126
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2040              		.loc 1 1705 5 is_stmt 1 view .LVU666
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2041              		.loc 1 1705 11 is_stmt 0 view .LVU667
+ 2042 01ac B0F84440 		ldrh	r4, [r0, #68]
+ 2043 01b0 A3B2     		uxth	r3, r4
+ 2044              	.LVL216:
+1708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2045              		.loc 1 1708 5 is_stmt 1 view .LVU668
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 2046              		.loc 1 1710 5 view .LVU669
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 2047              		.loc 1 1710 8 is_stmt 0 view .LVU670
+ 2048 01b2 14F00F04 		ands	r4, r4, #15
+ 2049              	.LVL217:
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 2050              		.loc 1 1710 8 view .LVU671
+ 2051 01b6 9AD1     		bne	.L97
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ 2052              		.loc 1 1715 7 is_stmt 1 view .LVU672
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       {
+ 2053              		.loc 1 1715 10 is_stmt 0 view .LVU673
+ 2054 01b8 13F0100F 		tst	r3, #16
+ 2055 01bc 3FF424AF 		beq	.L127
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+ 2056              		.loc 1 1746 9 is_stmt 1 view .LVU674
+ 2057              	.LVL218:
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2058              		.loc 1 1747 9 view .LVU675
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2059              		.loc 1 1747 16 is_stmt 0 view .LVU676
+ 2060 01c0 0388     		ldrh	r3, [r0]
+ 2061              	.LVL219:
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2062              		.loc 1 1747 16 view .LVU677
+ 2063 01c2 9AB2     		uxth	r2, r3
+ 2064              	.LVL220:
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ARM GAS  /tmp/ccJPteqL.s 			page 85
+
+
+ 2065              		.loc 1 1749 9 is_stmt 1 view .LVU678
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 2066              		.loc 1 1749 12 is_stmt 0 view .LVU679
+ 2067 01c4 13F4006F 		tst	r3, #2048
+ 2068 01c8 7FF453AF 		bne	.L128
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 2069              		.loc 1 1767 14 is_stmt 1 view .LVU680
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 2070              		.loc 1 1767 17 is_stmt 0 view .LVU681
+ 2071 01cc 12F4004F 		tst	r2, #32768
+ 2072 01d0 E5D0     		beq	.L96
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2073              		.loc 1 1769 11 is_stmt 1 view .LVU682
+ 2074              	.LBB45:
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2075              		.loc 1 1769 11 view .LVU683
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2076              		.loc 1 1769 11 view .LVU684
+ 2077 01d2 0388     		ldrh	r3, [r0]
+ 2078 01d4 23F07003 		bic	r3, r3, #112
+ 2079 01d8 1B05     		lsls	r3, r3, #20
+ 2080 01da 1B0D     		lsrs	r3, r3, #20
+ 2081              	.LVL221:
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2082              		.loc 1 1769 11 view .LVU685
+ 2083 01dc 43F08003 		orr	r3, r3, #128
+ 2084              	.LVL222:
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2085              		.loc 1 1769 11 is_stmt 0 view .LVU686
+ 2086 01e0 0380     		strh	r3, [r0]	@ movhi
+ 2087              	.LBE45:
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2088              		.loc 1 1769 11 is_stmt 1 view .LVU687
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2089              		.loc 1 1772 11 view .LVU688
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2090              		.loc 1 1772 28 is_stmt 0 view .LVU689
+ 2091 01e2 2868     		ldr	r0, [r5]
+ 2092 01e4 B0F85030 		ldrh	r3, [r0, #80]
+ 2093 01e8 95F86821 		ldrb	r2, [r5, #360]	@ zero_extendqisi2
+ 2094              	.LVL223:
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2095              		.loc 1 1772 28 view .LVU690
+ 2096 01ec D200     		lsls	r2, r2, #3
+ 2097 01ee 12FA83F3 		uxtah	r3, r2, r3
+ 2098 01f2 0344     		add	r3, r3, r0
+ 2099 01f4 B3F80634 		ldrh	r3, [r3, #1030]
+ 2100 01f8 C3F30903 		ubfx	r3, r3, #0, #10
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2101              		.loc 1 1772 26 view .LVU691
+ 2102 01fc C5F88431 		str	r3, [r5, #388]
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2103              		.loc 1 1774 11 is_stmt 1 view .LVU692
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2104              		.loc 1 1774 14 is_stmt 0 view .LVU693
+ 2105 0200 8BB1     		cbz	r3, .L101
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ARM GAS  /tmp/ccJPteqL.s 			page 86
+
+
+ 2106              		.loc 1 1774 44 discriminator 1 view .LVU694
+ 2107 0202 D5F87C11 		ldr	r1, [r5, #380]
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2108              		.loc 1 1774 38 discriminator 1 view .LVU695
+ 2109 0206 71B1     		cbz	r1, .L101
+1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****                         ep->pmaadress, (uint16_t)ep->xfer_count);
+ 2110              		.loc 1 1776 13 is_stmt 1 view .LVU696
+ 2111 0208 B5F86E21 		ldrh	r2, [r5, #366]
+ 2112 020c FFF7FEFF 		bl	USB_ReadPMA
+ 2113              	.LVL224:
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2114              		.loc 1 1779 13 view .LVU697
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2115              		.loc 1 1779 15 is_stmt 0 view .LVU698
+ 2116 0210 D5F87C31 		ldr	r3, [r5, #380]
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2117              		.loc 1 1779 32 view .LVU699
+ 2118 0214 D5F88421 		ldr	r2, [r5, #388]
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2119              		.loc 1 1779 27 view .LVU700
+ 2120 0218 1344     		add	r3, r3, r2
+ 2121 021a C5F87C31 		str	r3, [r5, #380]
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 2122              		.loc 1 1785 13 is_stmt 1 view .LVU701
+ 2123 021e 0021     		movs	r1, #0
+ 2124 0220 2846     		mov	r0, r5
+ 2125 0222 FFF7FEFF 		bl	HAL_PCD_DataOutStageCallback
+ 2126              	.LVL225:
+ 2127              	.L101:
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2128              		.loc 1 1789 11 view .LVU702
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2129              		.loc 1 1789 16 is_stmt 0 view .LVU703
+ 2130 0226 2B68     		ldr	r3, [r5]
+ 2131 0228 1A88     		ldrh	r2, [r3]
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2132              		.loc 1 1789 14 view .LVU704
+ 2133 022a 12F4006F 		tst	r2, #2048
+ 2134 022e B6D1     		bne	.L96
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2135              		.loc 1 1791 13 is_stmt 1 view .LVU705
+ 2136              	.LBB46:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2137              		.loc 1 1791 13 view .LVU706
+ 2138              	.LVL226:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2139              		.loc 1 1791 13 view .LVU707
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2140              		.loc 1 1791 13 view .LVU708
+ 2141 0230 B3F85020 		ldrh	r2, [r3, #80]
+ 2142 0234 13FA82F3 		uxtah	r3, r3, r2
+ 2143              	.LVL227:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2144              		.loc 1 1791 13 view .LVU709
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2145              		.loc 1 1791 13 view .LVU710
+ 2146              	.LBB41:
+ARM GAS  /tmp/ccJPteqL.s 			page 87
+
+
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2147              		.loc 1 1791 13 view .LVU711
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2148              		.loc 1 1791 13 view .LVU712
+ 2149 0238 D5F87811 		ldr	r1, [r5, #376]
+ 2150 023c 3E29     		cmp	r1, #62
+ 2151 023e 7FF639AF 		bls	.L102
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2152              		.loc 1 1791 13 discriminator 1 view .LVU713
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2153              		.loc 1 1791 13 discriminator 1 view .LVU714
+ 2154 0242 4A09     		lsrs	r2, r1, #5
+ 2155              	.LVL228:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2156              		.loc 1 1791 13 discriminator 1 view .LVU715
+ 2157 0244 11F01F0F 		tst	r1, #31
+ 2158 0248 00D1     		bne	.L103
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2159              		.loc 1 1791 13 discriminator 3 view .LVU716
+ 2160 024a 013A     		subs	r2, r2, #1
+ 2161              	.LVL229:
+ 2162              	.L103:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2163              		.loc 1 1791 13 discriminator 5 view .LVU717
+ 2164 024c 6FEAC262 		mvn	r2, r2, lsl #27
+ 2165              	.LVL230:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2166              		.loc 1 1791 13 is_stmt 0 discriminator 5 view .LVU718
+ 2167 0250 6FEA5242 		mvn	r2, r2, lsr #17
+ 2168 0254 92B2     		uxth	r2, r2
+ 2169 0256 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2170              		.loc 1 1791 13 is_stmt 1 discriminator 5 view .LVU719
+ 2171              	.LVL231:
+ 2172              	.L104:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2173              		.loc 1 1791 13 discriminator 13 view .LVU720
+ 2174              	.LBE41:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2175              		.loc 1 1791 13 discriminator 13 view .LVU721
+ 2176              	.LBE46:
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ 2177              		.loc 1 1791 13 discriminator 13 view .LVU722
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2178              		.loc 1 1792 13 discriminator 13 view .LVU723
+ 2179              	.LBB47:
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2180              		.loc 1 1792 13 discriminator 13 view .LVU724
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2181              		.loc 1 1792 13 discriminator 13 view .LVU725
+ 2182 025a 2A68     		ldr	r2, [r5]
+ 2183 025c 1388     		ldrh	r3, [r2]
+ 2184              	.LVL232:
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2185              		.loc 1 1792 13 is_stmt 0 discriminator 13 view .LVU726
+ 2186 025e 9BB2     		uxth	r3, r3
+ 2187 0260 23F48043 		bic	r3, r3, #16384
+ARM GAS  /tmp/ccJPteqL.s 			page 88
+
+
+ 2188 0264 23F07003 		bic	r3, r3, #112
+ 2189              	.LVL233:
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2190              		.loc 1 1792 13 is_stmt 1 discriminator 13 view .LVU727
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2191              		.loc 1 1792 13 discriminator 13 view .LVU728
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2192              		.loc 1 1792 13 discriminator 13 view .LVU729
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2193              		.loc 1 1792 13 discriminator 13 view .LVU730
+ 2194 0268 83F44053 		eor	r3, r3, #12288
+ 2195              	.LVL234:
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2196              		.loc 1 1792 13 discriminator 13 view .LVU731
+ 2197 026c 43F40043 		orr	r3, r3, #32768
+ 2198              	.LVL235:
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2199              		.loc 1 1792 13 is_stmt 0 discriminator 13 view .LVU732
+ 2200 0270 43F08003 		orr	r3, r3, #128
+ 2201 0274 1380     		strh	r3, [r2]	@ movhi
+ 2202 0276 92E7     		b	.L96
+ 2203              	.LVL236:
+ 2204              	.L125:
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2205              		.loc 1 1792 13 discriminator 13 view .LVU733
+ 2206              	.LBE47:
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->OUT_ep[epindex];
+ 2207              		.loc 1 1806 9 is_stmt 1 view .LVU734
+ 2208              	.LBB48:
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->OUT_ep[epindex];
+ 2209              		.loc 1 1806 9 view .LVU735
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->OUT_ep[epindex];
+ 2210              		.loc 1 1806 9 view .LVU736
+ 2211 0278 30F82430 		ldrh	r3, [r0, r4, lsl #2]
+ 2212 027c 23F07003 		bic	r3, r3, #112
+ 2213 0280 1B05     		lsls	r3, r3, #20
+ 2214 0282 1B0D     		lsrs	r3, r3, #20
+ 2215              	.LVL237:
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->OUT_ep[epindex];
+ 2216              		.loc 1 1806 9 view .LVU737
+ 2217 0284 43F08003 		orr	r3, r3, #128
+ 2218              	.LVL238:
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->OUT_ep[epindex];
+ 2219              		.loc 1 1806 9 is_stmt 0 view .LVU738
+ 2220 0288 20F82430 		strh	r3, [r0, r4, lsl #2]	@ movhi
+ 2221              	.LBE48:
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep = &hpcd->OUT_ep[epindex];
+ 2222              		.loc 1 1806 9 is_stmt 1 view .LVU739
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2223              		.loc 1 1807 9 view .LVU740
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2224              		.loc 1 1807 12 is_stmt 0 view .LVU741
+ 2225 028c 04EB8401 		add	r1, r4, r4, lsl #2
+ 2226 0290 C900     		lsls	r1, r1, #3
+ 2227 0292 01F5B471 		add	r1, r1, #360
+ 2228 0296 05EB0108 		add	r8, r5, r1
+ 2229              	.LVL239:
+ARM GAS  /tmp/ccJPteqL.s 			page 89
+
+
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 2230              		.loc 1 1810 9 is_stmt 1 view .LVU742
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 2231              		.loc 1 1810 15 is_stmt 0 view .LVU743
+ 2232 029a 04EB8403 		add	r3, r4, r4, lsl #2
+ 2233 029e 05EBC303 		add	r3, r5, r3, lsl #3
+ 2234 02a2 93F87431 		ldrb	r3, [r3, #372]	@ zero_extendqisi2
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 2235              		.loc 1 1810 12 view .LVU744
+ 2236 02a6 002B     		cmp	r3, #0
+ 2237 02a8 40D1     		bne	.L108
+1812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2238              		.loc 1 1812 11 is_stmt 1 view .LVU745
+1812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2239              		.loc 1 1812 29 is_stmt 0 view .LVU746
+ 2240 02aa 2868     		ldr	r0, [r5]
+ 2241 02ac B0F85030 		ldrh	r3, [r0, #80]
+ 2242 02b0 04EB8402 		add	r2, r4, r4, lsl #2
+ 2243 02b4 05EBC202 		add	r2, r5, r2, lsl #3
+ 2244 02b8 92F86821 		ldrb	r2, [r2, #360]	@ zero_extendqisi2
+ 2245 02bc D200     		lsls	r2, r2, #3
+ 2246 02be 12FA83F3 		uxtah	r3, r2, r3
+ 2247 02c2 0344     		add	r3, r3, r0
+ 2248 02c4 B3F80674 		ldrh	r7, [r3, #1030]
+1812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2249              		.loc 1 1812 17 view .LVU747
+ 2250 02c8 C7F30907 		ubfx	r7, r7, #0, #10
+ 2251              	.LVL240:
+1814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2252              		.loc 1 1814 11 is_stmt 1 view .LVU748
+1814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2253              		.loc 1 1814 14 is_stmt 0 view .LVU749
+ 2254 02cc 17BB     		cbnz	r7, .L129
+ 2255              	.L109:
+1857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_buff += count;
+ 2256              		.loc 1 1857 9 is_stmt 1 view .LVU750
+1857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_buff += count;
+ 2257              		.loc 1 1857 11 is_stmt 0 view .LVU751
+ 2258 02ce 04EB8403 		add	r3, r4, r4, lsl #2
+ 2259 02d2 05EBC303 		add	r3, r5, r3, lsl #3
+ 2260 02d6 D3F88421 		ldr	r2, [r3, #388]
+1857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         ep->xfer_buff += count;
+ 2261              		.loc 1 1857 24 view .LVU752
+ 2262 02da 3A44     		add	r2, r2, r7
+ 2263 02dc C3F88421 		str	r2, [r3, #388]
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2264              		.loc 1 1858 9 is_stmt 1 view .LVU753
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2265              		.loc 1 1858 11 is_stmt 0 view .LVU754
+ 2266 02e0 D3F87C21 		ldr	r2, [r3, #380]
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2267              		.loc 1 1858 23 view .LVU755
+ 2268 02e4 3A44     		add	r2, r2, r7
+ 2269 02e6 C3F87C21 		str	r2, [r3, #380]
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 2270              		.loc 1 1860 9 is_stmt 1 view .LVU756
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ARM GAS  /tmp/ccJPteqL.s 			page 90
+
+
+ 2271              		.loc 1 1860 16 is_stmt 0 view .LVU757
+ 2272 02ea D3F88031 		ldr	r3, [r3, #384]
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 2273              		.loc 1 1860 12 view .LVU758
+ 2274 02ee 3BB1     		cbz	r3, .L112
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 2275              		.loc 1 1860 48 discriminator 1 view .LVU759
+ 2276 02f0 04EB8403 		add	r3, r4, r4, lsl #2
+ 2277 02f4 05EBC303 		add	r3, r5, r3, lsl #3
+ 2278 02f8 D3F87831 		ldr	r3, [r3, #376]
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         {
+ 2279              		.loc 1 1860 34 discriminator 1 view .LVU760
+ 2280 02fc 9F42     		cmp	r7, r3
+ 2281 02fe 70D2     		bcs	.L113
+ 2282              	.L112:
+1866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 2283              		.loc 1 1866 11 is_stmt 1 view .LVU761
+ 2284 0300 04EB8403 		add	r3, r4, r4, lsl #2
+ 2285 0304 05EBC303 		add	r3, r5, r3, lsl #3
+ 2286 0308 93F86811 		ldrb	r1, [r3, #360]	@ zero_extendqisi2
+ 2287 030c 2846     		mov	r0, r5
+ 2288 030e FFF7FEFF 		bl	HAL_PCD_DataOutStageCallback
+ 2289              	.LVL241:
+ 2290 0312 F3E6     		b	.L107
+ 2291              	.L129:
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2292              		.loc 1 1816 13 view .LVU762
+ 2293 0314 04EB8401 		add	r1, r4, r4, lsl #2
+ 2294 0318 05EBC101 		add	r1, r5, r1, lsl #3
+ 2295 031c 3B46     		mov	r3, r7
+ 2296 031e B1F86E21 		ldrh	r2, [r1, #366]
+ 2297 0322 D1F87C11 		ldr	r1, [r1, #380]
+ 2298 0326 FFF7FEFF 		bl	USB_ReadPMA
+ 2299              	.LVL242:
+ 2300 032a D0E7     		b	.L109
+ 2301              	.LVL243:
+ 2302              	.L108:
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2303              		.loc 1 1823 11 view .LVU763
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2304              		.loc 1 1823 17 is_stmt 0 view .LVU764
+ 2305 032c 04EB8403 		add	r3, r4, r4, lsl #2
+ 2306 0330 05EBC303 		add	r3, r5, r3, lsl #3
+ 2307 0334 93F86B31 		ldrb	r3, [r3, #363]	@ zero_extendqisi2
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2308              		.loc 1 1823 14 view .LVU765
+ 2309 0338 022B     		cmp	r3, #2
+ 2310 033a 33D0     		beq	.L130
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2311              		.loc 1 1830 13 is_stmt 1 discriminator 1 view .LVU766
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2312              		.loc 1 1830 13 discriminator 1 view .LVU767
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2313              		.loc 1 1830 13 discriminator 1 view .LVU768
+ 2314              	.LBB49:
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2315              		.loc 1 1830 13 discriminator 1 view .LVU769
+ARM GAS  /tmp/ccJPteqL.s 			page 91
+
+
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2316              		.loc 1 1830 13 discriminator 1 view .LVU770
+ 2317 033c 2968     		ldr	r1, [r5]
+ 2318 033e 04EB8402 		add	r2, r4, r4, lsl #2
+ 2319 0342 05EBC202 		add	r2, r5, r2, lsl #3
+ 2320 0346 92F86801 		ldrb	r0, [r2, #360]	@ zero_extendqisi2
+ 2321 034a 31F82030 		ldrh	r3, [r1, r0, lsl #2]
+ 2322 034e 9BB2     		uxth	r3, r3
+ 2323 0350 23F4E043 		bic	r3, r3, #28672
+ 2324 0354 23F07003 		bic	r3, r3, #112
+ 2325              	.LVL244:
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2326              		.loc 1 1830 13 discriminator 1 view .LVU771
+ 2327 0358 43F40043 		orr	r3, r3, #32768
+ 2328              	.LVL245:
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2329              		.loc 1 1830 13 is_stmt 0 discriminator 1 view .LVU772
+ 2330 035c 43F0C003 		orr	r3, r3, #192
+ 2331 0360 21F82030 		strh	r3, [r1, r0, lsl #2]	@ movhi
+ 2332              	.LBE49:
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2333              		.loc 1 1830 13 is_stmt 1 discriminator 1 view .LVU773
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2334              		.loc 1 1830 13 discriminator 1 view .LVU774
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2335              		.loc 1 1830 13 discriminator 1 view .LVU775
+1832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+ 2336              		.loc 1 1832 13 discriminator 1 view .LVU776
+1832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+ 2337              		.loc 1 1832 18 is_stmt 0 discriminator 1 view .LVU777
+ 2338 0364 2868     		ldr	r0, [r5]
+ 2339 0366 92F86831 		ldrb	r3, [r2, #360]	@ zero_extendqisi2
+ 2340 036a 30F82320 		ldrh	r2, [r0, r3, lsl #2]
+1832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+ 2341              		.loc 1 1832 16 discriminator 1 view .LVU778
+ 2342 036e 12F4804F 		tst	r2, #16384
+ 2343 0372 1ED0     		beq	.L111
+1835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2344              		.loc 1 1835 15 is_stmt 1 view .LVU779
+1835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2345              		.loc 1 1835 33 is_stmt 0 view .LVU780
+ 2346 0374 B0F85020 		ldrh	r2, [r0, #80]
+ 2347 0378 DB00     		lsls	r3, r3, #3
+ 2348 037a 13FA82F3 		uxtah	r3, r3, r2
+ 2349 037e 0344     		add	r3, r3, r0
+ 2350 0380 B3F80274 		ldrh	r7, [r3, #1026]
+1835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2351              		.loc 1 1835 21 view .LVU781
+ 2352 0384 C7F30907 		ubfx	r7, r7, #0, #10
+ 2353              	.LVL246:
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               {
+ 2354              		.loc 1 1837 15 is_stmt 1 view .LVU782
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               {
+ 2355              		.loc 1 1837 18 is_stmt 0 view .LVU783
+ 2356 0388 002F     		cmp	r7, #0
+ 2357 038a A0D0     		beq	.L109
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               }
+ARM GAS  /tmp/ccJPteqL.s 			page 92
+
+
+ 2358              		.loc 1 1839 17 is_stmt 1 view .LVU784
+ 2359 038c 04EB8401 		add	r1, r4, r4, lsl #2
+ 2360 0390 05EBC101 		add	r1, r5, r1, lsl #3
+ 2361 0394 3B46     		mov	r3, r7
+ 2362 0396 B1F87021 		ldrh	r2, [r1, #368]
+ 2363 039a D1F87C11 		ldr	r1, [r1, #380]
+ 2364 039e FFF7FEFF 		bl	USB_ReadPMA
+ 2365              	.LVL247:
+ 2366 03a2 94E7     		b	.L109
+ 2367              	.LVL248:
+ 2368              	.L130:
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2369              		.loc 1 1825 13 view .LVU785
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2370              		.loc 1 1825 21 is_stmt 0 view .LVU786
+ 2371 03a4 3246     		mov	r2, r6
+ 2372 03a6 4146     		mov	r1, r8
+ 2373 03a8 2846     		mov	r0, r5
+ 2374 03aa FFF7FEFF 		bl	HAL_PCD_EP_DB_Receive
+ 2375              	.LVL249:
+ 2376 03ae 0746     		mov	r7, r0
+ 2377              	.LVL250:
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2378              		.loc 1 1825 21 view .LVU787
+ 2379 03b0 8DE7     		b	.L109
+ 2380              	.LVL251:
+ 2381              	.L111:
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2382              		.loc 1 1845 15 is_stmt 1 view .LVU788
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2383              		.loc 1 1845 33 is_stmt 0 view .LVU789
+ 2384 03b2 B0F85020 		ldrh	r2, [r0, #80]
+ 2385 03b6 DB00     		lsls	r3, r3, #3
+ 2386 03b8 13FA82F3 		uxtah	r3, r3, r2
+ 2387 03bc 0344     		add	r3, r3, r0
+ 2388 03be B3F80674 		ldrh	r7, [r3, #1030]
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2389              		.loc 1 1845 21 view .LVU790
+ 2390 03c2 C7F30907 		ubfx	r7, r7, #0, #10
+ 2391              	.LVL252:
+1847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               {
+ 2392              		.loc 1 1847 15 is_stmt 1 view .LVU791
+1847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               {
+ 2393              		.loc 1 1847 18 is_stmt 0 view .LVU792
+ 2394 03c6 002F     		cmp	r7, #0
+ 2395 03c8 81D0     		beq	.L109
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               }
+ 2396              		.loc 1 1849 17 is_stmt 1 view .LVU793
+ 2397 03ca 04EB8401 		add	r1, r4, r4, lsl #2
+ 2398 03ce 05EBC101 		add	r1, r5, r1, lsl #3
+ 2399 03d2 3B46     		mov	r3, r7
+ 2400 03d4 B1F87221 		ldrh	r2, [r1, #370]
+ 2401 03d8 D1F87C11 		ldr	r1, [r1, #380]
+ 2402 03dc FFF7FEFF 		bl	USB_ReadPMA
+ 2403              	.LVL253:
+ 2404 03e0 75E7     		b	.L109
+ 2405              	.LVL254:
+ARM GAS  /tmp/ccJPteqL.s 			page 93
+
+
+ 2406              	.L113:
+1871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 2407              		.loc 1 1871 11 view .LVU794
+1871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****         }
+ 2408              		.loc 1 1871 18 is_stmt 0 view .LVU795
+ 2409 03e2 4146     		mov	r1, r8
+ 2410 03e4 2868     		ldr	r0, [r5]
+ 2411 03e6 FFF7FEFF 		bl	USB_EPStartXfer
+ 2412              	.LVL255:
+ 2413 03ea 87E6     		b	.L107
+ 2414              	.LVL256:
+ 2415              	.L117:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2416              		.loc 1 1891 15 is_stmt 1 discriminator 2 view .LVU796
+ 2417 03ec 012B     		cmp	r3, #1
+ 2418 03ee 7FF4CEAE 		bne	.L115
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2419              		.loc 1 1891 15 discriminator 16 view .LVU797
+ 2420              	.LBB50:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2421              		.loc 1 1891 15 discriminator 16 view .LVU798
+ 2422 03f2 2A68     		ldr	r2, [r5]
+ 2423              	.LVL257:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2424              		.loc 1 1891 15 discriminator 16 view .LVU799
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2425              		.loc 1 1891 15 discriminator 16 view .LVU800
+ 2426 03f4 B2F85030 		ldrh	r3, [r2, #80]
+ 2427 03f8 12FA83F3 		uxtah	r3, r2, r3
+ 2428              	.LVL258:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2429              		.loc 1 1891 15 discriminator 16 view .LVU801
+ 2430 03fc 621C     		adds	r2, r4, #1
+ 2431 03fe 02EB8202 		add	r2, r2, r2, lsl #2
+ 2432 0402 15F83220 		ldrb	r2, [r5, r2, lsl #3]	@ zero_extendqisi2
+ 2433 0406 03EBC203 		add	r3, r3, r2, lsl #3
+ 2434              	.LVL259:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2435              		.loc 1 1891 15 discriminator 16 view .LVU802
+ 2436 040a 0022     		movs	r2, #0
+ 2437 040c A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 2438 0410 BDE6     		b	.L115
+ 2439              	.LVL260:
+ 2440              	.L116:
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2441              		.loc 1 1891 15 is_stmt 0 discriminator 16 view .LVU803
+ 2442              	.LBE50:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2443              		.loc 1 1895 15 is_stmt 1 view .LVU804
+ 2444              	.LBB51:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2445              		.loc 1 1895 15 view .LVU805
+ 2446 0412 2A68     		ldr	r2, [r5]
+ 2447              	.LVL261:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2448              		.loc 1 1895 15 view .LVU806
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ARM GAS  /tmp/ccJPteqL.s 			page 94
+
+
+ 2449              		.loc 1 1895 15 view .LVU807
+ 2450 0414 631C     		adds	r3, r4, #1
+ 2451 0416 03EB8303 		add	r3, r3, r3, lsl #2
+ 2452 041a 05EBC303 		add	r3, r5, r3, lsl #3
+ 2453 041e 5B78     		ldrb	r3, [r3, #1]	@ zero_extendqisi2
+ 2454 0420 E3B9     		cbnz	r3, .L118
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2455              		.loc 1 1895 15 discriminator 1 view .LVU808
+ 2456              	.LBB52:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2457              		.loc 1 1895 15 discriminator 1 view .LVU809
+ 2458              	.LVL262:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2459              		.loc 1 1895 15 discriminator 1 view .LVU810
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2460              		.loc 1 1895 15 discriminator 1 view .LVU811
+ 2461 0422 B2F85030 		ldrh	r3, [r2, #80]
+ 2462 0426 12FA83F3 		uxtah	r3, r2, r3
+ 2463              	.LVL263:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2464              		.loc 1 1895 15 discriminator 1 view .LVU812
+ 2465 042a 621C     		adds	r2, r4, #1
+ 2466              	.LVL264:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2467              		.loc 1 1895 15 is_stmt 0 discriminator 1 view .LVU813
+ 2468 042c 02EB8202 		add	r2, r2, r2, lsl #2
+ 2469 0430 15F83220 		ldrb	r2, [r5, r2, lsl #3]	@ zero_extendqisi2
+ 2470 0434 03EBC203 		add	r3, r3, r2, lsl #3
+ 2471              	.LVL265:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2472              		.loc 1 1895 15 is_stmt 1 discriminator 1 view .LVU814
+ 2473              	.LBB53:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2474              		.loc 1 1895 15 discriminator 1 view .LVU815
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2475              		.loc 1 1895 15 discriminator 1 view .LVU816
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2476              		.loc 1 1895 15 discriminator 1 view .LVU817
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2477              		.loc 1 1895 15 discriminator 1 view .LVU818
+ 2478 0438 B3F80624 		ldrh	r2, [r3, #1030]
+ 2479 043c 92B2     		uxth	r2, r2
+ 2480 043e 22F4F842 		bic	r2, r2, #31744
+ 2481 0442 92B2     		uxth	r2, r2
+ 2482 0444 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 2483              	.LVL266:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2484              		.loc 1 1895 15 discriminator 1 view .LVU819
+ 2485 0448 B3F80624 		ldrh	r2, [r3, #1030]
+ 2486 044c 6FEA4242 		mvn	r2, r2, lsl #17
+ 2487 0450 6FEA5242 		mvn	r2, r2, lsr #17
+ 2488 0454 92B2     		uxth	r2, r2
+ 2489 0456 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 2490 045a 98E6     		b	.L115
+ 2491              	.LVL267:
+ 2492              	.L118:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ARM GAS  /tmp/ccJPteqL.s 			page 95
+
+
+ 2493              		.loc 1 1895 15 is_stmt 0 discriminator 1 view .LVU820
+ 2494              	.LBE53:
+ 2495              	.LBE52:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2496              		.loc 1 1895 15 is_stmt 1 discriminator 2 view .LVU821
+ 2497 045c 012B     		cmp	r3, #1
+ 2498 045e 7FF496AE 		bne	.L115
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2499              		.loc 1 1895 15 discriminator 16 view .LVU822
+ 2500 0462 B2F85030 		ldrh	r3, [r2, #80]
+ 2501 0466 12FA83F3 		uxtah	r3, r2, r3
+ 2502              	.LVL268:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2503              		.loc 1 1895 15 discriminator 16 view .LVU823
+ 2504 046a 621C     		adds	r2, r4, #1
+ 2505 046c 02EB8202 		add	r2, r2, r2, lsl #2
+ 2506 0470 15F83220 		ldrb	r2, [r5, r2, lsl #3]	@ zero_extendqisi2
+ 2507 0474 03EBC203 		add	r3, r3, r2, lsl #3
+ 2508              	.LVL269:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2509              		.loc 1 1895 15 discriminator 16 view .LVU824
+ 2510 0478 0022     		movs	r2, #0
+ 2511 047a A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 2512 047e 86E6     		b	.L115
+ 2513              	.LVL270:
+ 2514              	.L114:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2515              		.loc 1 1895 15 is_stmt 0 discriminator 16 view .LVU825
+ 2516              	.LBE51:
+1910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2517              		.loc 1 1910 11 is_stmt 1 view .LVU826
+1910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           {
+ 2518              		.loc 1 1910 14 is_stmt 0 view .LVU827
+ 2519 0480 16F4807F 		tst	r6, #256
+ 2520 0484 3FD1     		bne	.L119
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2521              		.loc 1 1913 13 is_stmt 1 view .LVU828
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2522              		.loc 1 1913 35 is_stmt 0 view .LVU829
+ 2523 0486 2868     		ldr	r0, [r5]
+ 2524 0488 B0F85030 		ldrh	r3, [r0, #80]
+ 2525 048c 621C     		adds	r2, r4, #1
+ 2526 048e 02EB8202 		add	r2, r2, r2, lsl #2
+ 2527 0492 15F83260 		ldrb	r6, [r5, r2, lsl #3]	@ zero_extendqisi2
+ 2528              	.LVL271:
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2529              		.loc 1 1913 35 view .LVU830
+ 2530 0496 F200     		lsls	r2, r6, #3
+ 2531 0498 12FA83F3 		uxtah	r3, r2, r3
+ 2532 049c 0344     		add	r3, r3, r0
+ 2533 049e B3F80234 		ldrh	r3, [r3, #1026]
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2534              		.loc 1 1913 23 view .LVU831
+ 2535 04a2 C3F30903 		ubfx	r3, r3, #0, #10
+ 2536              	.LVL272:
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+ 2537              		.loc 1 1915 13 is_stmt 1 view .LVU832
+ARM GAS  /tmp/ccJPteqL.s 			page 96
+
+
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+ 2538              		.loc 1 1915 19 is_stmt 0 view .LVU833
+ 2539 04a6 04EB8402 		add	r2, r4, r4, lsl #2
+ 2540 04aa 05EBC202 		add	r2, r5, r2, lsl #3
+ 2541 04ae 126C     		ldr	r2, [r2, #64]
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+ 2542              		.loc 1 1915 16 view .LVU834
+ 2543 04b0 9A42     		cmp	r2, r3
+ 2544 04b2 10D9     		bls	.L120
+1917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2545              		.loc 1 1917 15 is_stmt 1 view .LVU835
+1917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2546              		.loc 1 1917 28 is_stmt 0 view .LVU836
+ 2547 04b4 04EB8407 		add	r7, r4, r4, lsl #2
+ 2548 04b8 05EBC707 		add	r7, r5, r7, lsl #3
+ 2549 04bc D21A     		subs	r2, r2, r3
+ 2550 04be 3A64     		str	r2, [r7, #64]
+ 2551              	.L121:
+1925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+ 2552              		.loc 1 1925 13 is_stmt 1 view .LVU837
+1925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+ 2553              		.loc 1 1925 19 is_stmt 0 view .LVU838
+ 2554 04c0 04EB8402 		add	r2, r4, r4, lsl #2
+ 2555 04c4 05EBC202 		add	r2, r5, r2, lsl #3
+ 2556 04c8 126C     		ldr	r2, [r2, #64]
+1925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             {
+ 2557              		.loc 1 1925 16 view .LVU839
+ 2558 04ca 5AB9     		cbnz	r2, .L122
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 2559              		.loc 1 1931 15 is_stmt 1 view .LVU840
+ 2560 04cc 3146     		mov	r1, r6
+ 2561              	.LVL273:
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 2562              		.loc 1 1931 15 is_stmt 0 view .LVU841
+ 2563 04ce 2846     		mov	r0, r5
+ 2564 04d0 FFF7FEFF 		bl	HAL_PCD_DataInStageCallback
+ 2565              	.LVL274:
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 2566              		.loc 1 1931 15 view .LVU842
+ 2567 04d4 63E6     		b	.L96
+ 2568              	.LVL275:
+ 2569              	.L120:
+1921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2570              		.loc 1 1921 15 is_stmt 1 view .LVU843
+1921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2571              		.loc 1 1921 28 is_stmt 0 view .LVU844
+ 2572 04d6 04EB8402 		add	r2, r4, r4, lsl #2
+ 2573 04da 05EBC202 		add	r2, r5, r2, lsl #3
+ 2574 04de 0027     		movs	r7, #0
+ 2575 04e0 1764     		str	r7, [r2, #64]
+ 2576 04e2 EDE7     		b	.L121
+ 2577              	.L122:
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               ep->xfer_count += TxPctSize;
+ 2578              		.loc 1 1937 15 is_stmt 1 view .LVU845
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               ep->xfer_count += TxPctSize;
+ 2579              		.loc 1 1937 17 is_stmt 0 view .LVU846
+ 2580 04e4 04EB8402 		add	r2, r4, r4, lsl #2
+ARM GAS  /tmp/ccJPteqL.s 			page 97
+
+
+ 2581 04e8 05EBC202 		add	r2, r5, r2, lsl #3
+ 2582 04ec D66B     		ldr	r6, [r2, #60]
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               ep->xfer_count += TxPctSize;
+ 2583              		.loc 1 1937 29 view .LVU847
+ 2584 04ee 1E44     		add	r6, r6, r3
+ 2585 04f0 D663     		str	r6, [r2, #60]
+1938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               (void)USB_EPStartXfer(hpcd->Instance, ep);
+ 2586              		.loc 1 1938 15 is_stmt 1 view .LVU848
+1938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               (void)USB_EPStartXfer(hpcd->Instance, ep);
+ 2587              		.loc 1 1938 17 is_stmt 0 view .LVU849
+ 2588 04f2 526C     		ldr	r2, [r2, #68]
+1938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               (void)USB_EPStartXfer(hpcd->Instance, ep);
+ 2589              		.loc 1 1938 30 view .LVU850
+ 2590 04f4 04EB8404 		add	r4, r4, r4, lsl #2
+ 2591 04f8 05EBC404 		add	r4, r5, r4, lsl #3
+ 2592 04fc 1344     		add	r3, r3, r2
+ 2593              	.LVL276:
+1938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****               (void)USB_EPStartXfer(hpcd->Instance, ep);
+ 2594              		.loc 1 1938 30 view .LVU851
+ 2595 04fe 6364     		str	r3, [r4, #68]
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2596              		.loc 1 1939 15 is_stmt 1 view .LVU852
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2597              		.loc 1 1939 21 is_stmt 0 view .LVU853
+ 2598 0500 FFF7FEFF 		bl	USB_EPStartXfer
+ 2599              	.LVL277:
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****             }
+ 2600              		.loc 1 1939 21 view .LVU854
+ 2601 0504 4BE6     		b	.L96
+ 2602              	.LVL278:
+ 2603              	.L119:
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2604              		.loc 1 1946 13 is_stmt 1 view .LVU855
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2605              		.loc 1 1946 19 is_stmt 0 view .LVU856
+ 2606 0506 3246     		mov	r2, r6
+ 2607 0508 2846     		mov	r0, r5
+ 2608 050a FFF7FEFF 		bl	HAL_PCD_EP_DB_Transmit
+ 2609              	.LVL279:
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****           }
+ 2610              		.loc 1 1946 19 view .LVU857
+ 2611 050e 46E6     		b	.L96
+ 2612              	.LVL280:
+ 2613              	.L126:
+1954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 2614              		.loc 1 1954 3 is_stmt 1 view .LVU858
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2615              		.loc 1 1955 1 is_stmt 0 view .LVU859
+ 2616 0510 0020     		movs	r0, #0
+ 2617 0512 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2618              		.loc 1 1955 1 view .LVU860
+ 2619              		.cfi_endproc
+ 2620              	.LFE361:
+ 2622              		.section	.text.HAL_PCD_SOFCallback,"ax",%progbits
+ 2623              		.align	1
+ 2624              		.weak	HAL_PCD_SOFCallback
+ARM GAS  /tmp/ccJPteqL.s 			page 98
+
+
+ 2625              		.syntax unified
+ 2626              		.thumb
+ 2627              		.thumb_func
+ 2629              	HAL_PCD_SOFCallback:
+ 2630              	.LVL281:
+ 2631              	.LFB339:
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 2632              		.loc 1 1202 1 is_stmt 1 view -0
+ 2633              		.cfi_startproc
+ 2634              		@ args = 0, pretend = 0, frame = 0
+ 2635              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2636              		@ link register save eliminated.
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2637              		.loc 1 1204 3 view .LVU862
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2638              		.loc 1 1209 1 is_stmt 0 view .LVU863
+ 2639 0000 7047     		bx	lr
+ 2640              		.cfi_endproc
+ 2641              	.LFE339:
+ 2643              		.section	.text.HAL_PCD_ResetCallback,"ax",%progbits
+ 2644              		.align	1
+ 2645              		.weak	HAL_PCD_ResetCallback
+ 2646              		.syntax unified
+ 2647              		.thumb
+ 2648              		.thumb_func
+ 2650              	HAL_PCD_ResetCallback:
+ 2651              	.LVL282:
+ 2652              	.LFB340:
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 2653              		.loc 1 1217 1 is_stmt 1 view -0
+ 2654              		.cfi_startproc
+ 2655              		@ args = 0, pretend = 0, frame = 0
+ 2656              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2657              		@ link register save eliminated.
+1219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2658              		.loc 1 1219 3 view .LVU865
+1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2659              		.loc 1 1224 1 is_stmt 0 view .LVU866
+ 2660 0000 7047     		bx	lr
+ 2661              		.cfi_endproc
+ 2662              	.LFE340:
+ 2664              		.section	.text.HAL_PCD_SuspendCallback,"ax",%progbits
+ 2665              		.align	1
+ 2666              		.weak	HAL_PCD_SuspendCallback
+ 2667              		.syntax unified
+ 2668              		.thumb
+ 2669              		.thumb_func
+ 2671              	HAL_PCD_SuspendCallback:
+ 2672              	.LVL283:
+ 2673              	.LFB341:
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 2674              		.loc 1 1232 1 is_stmt 1 view -0
+ 2675              		.cfi_startproc
+ 2676              		@ args = 0, pretend = 0, frame = 0
+ 2677              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2678              		@ link register save eliminated.
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 99
+
+
+ 2679              		.loc 1 1234 3 view .LVU868
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2680              		.loc 1 1239 1 is_stmt 0 view .LVU869
+ 2681 0000 7047     		bx	lr
+ 2682              		.cfi_endproc
+ 2683              	.LFE341:
+ 2685              		.section	.text.HAL_PCD_ResumeCallback,"ax",%progbits
+ 2686              		.align	1
+ 2687              		.weak	HAL_PCD_ResumeCallback
+ 2688              		.syntax unified
+ 2689              		.thumb
+ 2690              		.thumb_func
+ 2692              	HAL_PCD_ResumeCallback:
+ 2693              	.LVL284:
+ 2694              	.LFB342:
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 2695              		.loc 1 1247 1 is_stmt 1 view -0
+ 2696              		.cfi_startproc
+ 2697              		@ args = 0, pretend = 0, frame = 0
+ 2698              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2699              		@ link register save eliminated.
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2700              		.loc 1 1249 3 view .LVU871
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2701              		.loc 1 1254 1 is_stmt 0 view .LVU872
+ 2702 0000 7047     		bx	lr
+ 2703              		.cfi_endproc
+ 2704              	.LFE342:
+ 2706              		.section	.text.HAL_PCD_ISOOUTIncompleteCallback,"ax",%progbits
+ 2707              		.align	1
+ 2708              		.weak	HAL_PCD_ISOOUTIncompleteCallback
+ 2709              		.syntax unified
+ 2710              		.thumb
+ 2711              		.thumb_func
+ 2713              	HAL_PCD_ISOOUTIncompleteCallback:
+ 2714              	.LVL285:
+ 2715              	.LFB343:
+1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 2716              		.loc 1 1263 1 is_stmt 1 view -0
+ 2717              		.cfi_startproc
+ 2718              		@ args = 0, pretend = 0, frame = 0
+ 2719              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2720              		@ link register save eliminated.
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(epnum);
+ 2721              		.loc 1 1265 3 view .LVU874
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2722              		.loc 1 1266 3 view .LVU875
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2723              		.loc 1 1271 1 is_stmt 0 view .LVU876
+ 2724 0000 7047     		bx	lr
+ 2725              		.cfi_endproc
+ 2726              	.LFE343:
+ 2728              		.section	.text.HAL_PCD_ISOINIncompleteCallback,"ax",%progbits
+ 2729              		.align	1
+ 2730              		.weak	HAL_PCD_ISOINIncompleteCallback
+ 2731              		.syntax unified
+ 2732              		.thumb
+ARM GAS  /tmp/ccJPteqL.s 			page 100
+
+
+ 2733              		.thumb_func
+ 2735              	HAL_PCD_ISOINIncompleteCallback:
+ 2736              	.LVL286:
+ 2737              	.LFB344:
+1280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 2738              		.loc 1 1280 1 is_stmt 1 view -0
+ 2739              		.cfi_startproc
+ 2740              		@ args = 0, pretend = 0, frame = 0
+ 2741              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2742              		@ link register save eliminated.
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(epnum);
+ 2743              		.loc 1 1282 3 view .LVU878
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2744              		.loc 1 1283 3 view .LVU879
+1288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2745              		.loc 1 1288 1 is_stmt 0 view .LVU880
+ 2746 0000 7047     		bx	lr
+ 2747              		.cfi_endproc
+ 2748              	.LFE344:
+ 2750              		.section	.text.HAL_PCD_ConnectCallback,"ax",%progbits
+ 2751              		.align	1
+ 2752              		.weak	HAL_PCD_ConnectCallback
+ 2753              		.syntax unified
+ 2754              		.thumb
+ 2755              		.thumb_func
+ 2757              	HAL_PCD_ConnectCallback:
+ 2758              	.LVL287:
+ 2759              	.LFB345:
+1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 2760              		.loc 1 1296 1 is_stmt 1 view -0
+ 2761              		.cfi_startproc
+ 2762              		@ args = 0, pretend = 0, frame = 0
+ 2763              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2764              		@ link register save eliminated.
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2765              		.loc 1 1298 3 view .LVU882
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2766              		.loc 1 1303 1 is_stmt 0 view .LVU883
+ 2767 0000 7047     		bx	lr
+ 2768              		.cfi_endproc
+ 2769              	.LFE345:
+ 2771              		.section	.text.HAL_PCD_DisconnectCallback,"ax",%progbits
+ 2772              		.align	1
+ 2773              		.weak	HAL_PCD_DisconnectCallback
+ 2774              		.syntax unified
+ 2775              		.thumb
+ 2776              		.thumb_func
+ 2778              	HAL_PCD_DisconnectCallback:
+ 2779              	.LVL288:
+ 2780              	.LFB346:
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 2781              		.loc 1 1311 1 is_stmt 1 view -0
+ 2782              		.cfi_startproc
+ 2783              		@ args = 0, pretend = 0, frame = 0
+ 2784              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2785              		@ link register save eliminated.
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 101
+
+
+ 2786              		.loc 1 1313 3 view .LVU885
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2787              		.loc 1 1318 1 is_stmt 0 view .LVU886
+ 2788 0000 7047     		bx	lr
+ 2789              		.cfi_endproc
+ 2790              	.LFE346:
+ 2792              		.section	.text.HAL_PCD_DevConnect,"ax",%progbits
+ 2793              		.align	1
+ 2794              		.global	HAL_PCD_DevConnect
+ 2795              		.syntax unified
+ 2796              		.thumb
+ 2797              		.thumb_func
+ 2799              	HAL_PCD_DevConnect:
+ 2800              	.LVL289:
+ 2801              	.LFB347:
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 2802              		.loc 1 1345 1 is_stmt 1 view -0
+ 2803              		.cfi_startproc
+ 2804              		@ args = 0, pretend = 0, frame = 0
+ 2805              		@ frame_needed = 0, uses_anonymous_args = 0
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevConnect(hpcd->Instance);
+ 2806              		.loc 1 1346 3 view .LVU888
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevConnect(hpcd->Instance);
+ 2807              		.loc 1 1346 3 view .LVU889
+ 2808 0000 90F8A832 		ldrb	r3, [r0, #680]	@ zero_extendqisi2
+ 2809 0004 012B     		cmp	r3, #1
+ 2810 0006 0BD0     		beq	.L141
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 2811              		.loc 1 1345 1 is_stmt 0 discriminator 2 view .LVU890
+ 2812 0008 10B5     		push	{r4, lr}
+ 2813              	.LCFI13:
+ 2814              		.cfi_def_cfa_offset 8
+ 2815              		.cfi_offset 4, -8
+ 2816              		.cfi_offset 14, -4
+ 2817 000a 0446     		mov	r4, r0
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevConnect(hpcd->Instance);
+ 2818              		.loc 1 1346 3 is_stmt 1 discriminator 2 view .LVU891
+ 2819 000c 0123     		movs	r3, #1
+ 2820 000e 80F8A832 		strb	r3, [r0, #680]
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevConnect(hpcd->Instance);
+ 2821              		.loc 1 1346 3 discriminator 2 view .LVU892
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 2822              		.loc 1 1347 3 discriminator 2 view .LVU893
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 2823              		.loc 1 1347 9 is_stmt 0 discriminator 2 view .LVU894
+ 2824 0012 0068     		ldr	r0, [r0]
+ 2825              	.LVL290:
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 2826              		.loc 1 1347 9 discriminator 2 view .LVU895
+ 2827 0014 FFF7FEFF 		bl	USB_DevConnect
+ 2828              	.LVL291:
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2829              		.loc 1 1348 3 is_stmt 1 discriminator 2 view .LVU896
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2830              		.loc 1 1348 3 discriminator 2 view .LVU897
+ 2831 0018 0020     		movs	r0, #0
+ 2832 001a 84F8A802 		strb	r0, [r4, #680]
+ARM GAS  /tmp/ccJPteqL.s 			page 102
+
+
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2833              		.loc 1 1348 3 discriminator 2 view .LVU898
+1350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 2834              		.loc 1 1350 3 discriminator 2 view .LVU899
+1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2835              		.loc 1 1351 1 is_stmt 0 discriminator 2 view .LVU900
+ 2836 001e 10BD     		pop	{r4, pc}
+ 2837              	.LVL292:
+ 2838              	.L141:
+ 2839              	.LCFI14:
+ 2840              		.cfi_def_cfa_offset 0
+ 2841              		.cfi_restore 4
+ 2842              		.cfi_restore 14
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevConnect(hpcd->Instance);
+ 2843              		.loc 1 1346 3 view .LVU901
+ 2844 0020 0220     		movs	r0, #2
+ 2845              	.LVL293:
+1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2846              		.loc 1 1351 1 view .LVU902
+ 2847 0022 7047     		bx	lr
+ 2848              		.cfi_endproc
+ 2849              	.LFE347:
+ 2851              		.section	.text.HAL_PCD_DevDisconnect,"ax",%progbits
+ 2852              		.align	1
+ 2853              		.global	HAL_PCD_DevDisconnect
+ 2854              		.syntax unified
+ 2855              		.thumb
+ 2856              		.thumb_func
+ 2858              	HAL_PCD_DevDisconnect:
+ 2859              	.LVL294:
+ 2860              	.LFB348:
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 2861              		.loc 1 1359 1 is_stmt 1 view -0
+ 2862              		.cfi_startproc
+ 2863              		@ args = 0, pretend = 0, frame = 0
+ 2864              		@ frame_needed = 0, uses_anonymous_args = 0
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevDisconnect(hpcd->Instance);
+ 2865              		.loc 1 1360 3 view .LVU904
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevDisconnect(hpcd->Instance);
+ 2866              		.loc 1 1360 3 view .LVU905
+ 2867 0000 90F8A832 		ldrb	r3, [r0, #680]	@ zero_extendqisi2
+ 2868 0004 012B     		cmp	r3, #1
+ 2869 0006 0BD0     		beq	.L148
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 2870              		.loc 1 1359 1 is_stmt 0 discriminator 2 view .LVU906
+ 2871 0008 10B5     		push	{r4, lr}
+ 2872              	.LCFI15:
+ 2873              		.cfi_def_cfa_offset 8
+ 2874              		.cfi_offset 4, -8
+ 2875              		.cfi_offset 14, -4
+ 2876 000a 0446     		mov	r4, r0
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevDisconnect(hpcd->Instance);
+ 2877              		.loc 1 1360 3 is_stmt 1 discriminator 2 view .LVU907
+ 2878 000c 0123     		movs	r3, #1
+ 2879 000e 80F8A832 		strb	r3, [r0, #680]
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevDisconnect(hpcd->Instance);
+ 2880              		.loc 1 1360 3 discriminator 2 view .LVU908
+ARM GAS  /tmp/ccJPteqL.s 			page 103
+
+
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 2881              		.loc 1 1361 3 discriminator 2 view .LVU909
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 2882              		.loc 1 1361 9 is_stmt 0 discriminator 2 view .LVU910
+ 2883 0012 0068     		ldr	r0, [r0]
+ 2884              	.LVL295:
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 2885              		.loc 1 1361 9 discriminator 2 view .LVU911
+ 2886 0014 FFF7FEFF 		bl	USB_DevDisconnect
+ 2887              	.LVL296:
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2888              		.loc 1 1362 3 is_stmt 1 discriminator 2 view .LVU912
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2889              		.loc 1 1362 3 discriminator 2 view .LVU913
+ 2890 0018 0020     		movs	r0, #0
+ 2891 001a 84F8A802 		strb	r0, [r4, #680]
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2892              		.loc 1 1362 3 discriminator 2 view .LVU914
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 2893              		.loc 1 1364 3 discriminator 2 view .LVU915
+1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2894              		.loc 1 1365 1 is_stmt 0 discriminator 2 view .LVU916
+ 2895 001e 10BD     		pop	{r4, pc}
+ 2896              	.LVL297:
+ 2897              	.L148:
+ 2898              	.LCFI16:
+ 2899              		.cfi_def_cfa_offset 0
+ 2900              		.cfi_restore 4
+ 2901              		.cfi_restore 14
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DevDisconnect(hpcd->Instance);
+ 2902              		.loc 1 1360 3 view .LVU917
+ 2903 0020 0220     		movs	r0, #2
+ 2904              	.LVL298:
+1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2905              		.loc 1 1365 1 view .LVU918
+ 2906 0022 7047     		bx	lr
+ 2907              		.cfi_endproc
+ 2908              	.LFE348:
+ 2910              		.section	.text.HAL_PCD_SetAddress,"ax",%progbits
+ 2911              		.align	1
+ 2912              		.global	HAL_PCD_SetAddress
+ 2913              		.syntax unified
+ 2914              		.thumb
+ 2915              		.thumb_func
+ 2917              	HAL_PCD_SetAddress:
+ 2918              	.LVL299:
+ 2919              	.LFB349:
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 2920              		.loc 1 1374 1 is_stmt 1 view -0
+ 2921              		.cfi_startproc
+ 2922              		@ args = 0, pretend = 0, frame = 0
+ 2923              		@ frame_needed = 0, uses_anonymous_args = 0
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->USB_Address = address;
+ 2924              		.loc 1 1375 3 view .LVU920
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->USB_Address = address;
+ 2925              		.loc 1 1375 3 view .LVU921
+ 2926 0000 90F8A832 		ldrb	r3, [r0, #680]	@ zero_extendqisi2
+ARM GAS  /tmp/ccJPteqL.s 			page 104
+
+
+ 2927 0004 012B     		cmp	r3, #1
+ 2928 0006 0DD0     		beq	.L155
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_LOCK(hpcd);
+ 2929              		.loc 1 1374 1 is_stmt 0 discriminator 2 view .LVU922
+ 2930 0008 10B5     		push	{r4, lr}
+ 2931              	.LCFI17:
+ 2932              		.cfi_def_cfa_offset 8
+ 2933              		.cfi_offset 4, -8
+ 2934              		.cfi_offset 14, -4
+ 2935 000a 0446     		mov	r4, r0
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->USB_Address = address;
+ 2936              		.loc 1 1375 3 is_stmt 1 discriminator 2 view .LVU923
+ 2937 000c 0123     		movs	r3, #1
+ 2938 000e 80F8A832 		strb	r3, [r0, #680]
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->USB_Address = address;
+ 2939              		.loc 1 1375 3 discriminator 2 view .LVU924
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_SetDevAddress(hpcd->Instance, address);
+ 2940              		.loc 1 1376 3 discriminator 2 view .LVU925
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_SetDevAddress(hpcd->Instance, address);
+ 2941              		.loc 1 1376 21 is_stmt 0 discriminator 2 view .LVU926
+ 2942 0012 80F82410 		strb	r1, [r0, #36]
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 2943              		.loc 1 1377 3 is_stmt 1 discriminator 2 view .LVU927
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 2944              		.loc 1 1377 9 is_stmt 0 discriminator 2 view .LVU928
+ 2945 0016 0068     		ldr	r0, [r0]
+ 2946              	.LVL300:
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 2947              		.loc 1 1377 9 discriminator 2 view .LVU929
+ 2948 0018 FFF7FEFF 		bl	USB_SetDevAddress
+ 2949              	.LVL301:
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2950              		.loc 1 1378 3 is_stmt 1 discriminator 2 view .LVU930
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2951              		.loc 1 1378 3 discriminator 2 view .LVU931
+ 2952 001c 0020     		movs	r0, #0
+ 2953 001e 84F8A802 		strb	r0, [r4, #680]
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2954              		.loc 1 1378 3 discriminator 2 view .LVU932
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 2955              		.loc 1 1380 3 discriminator 2 view .LVU933
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 2956              		.loc 1 1381 1 is_stmt 0 discriminator 2 view .LVU934
+ 2957 0022 10BD     		pop	{r4, pc}
+ 2958              	.LVL302:
+ 2959              	.L155:
+ 2960              	.LCFI18:
+ 2961              		.cfi_def_cfa_offset 0
+ 2962              		.cfi_restore 4
+ 2963              		.cfi_restore 14
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   hpcd->USB_Address = address;
+ 2964              		.loc 1 1375 3 view .LVU935
+ 2965 0024 0220     		movs	r0, #2
+ 2966              	.LVL303:
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 2967              		.loc 1 1381 1 view .LVU936
+ 2968 0026 7047     		bx	lr
+ARM GAS  /tmp/ccJPteqL.s 			page 105
+
+
+ 2969              		.cfi_endproc
+ 2970              	.LFE349:
+ 2972              		.section	.text.HAL_PCD_IRQHandler,"ax",%progbits
+ 2973              		.align	1
+ 2974              		.global	HAL_PCD_IRQHandler
+ 2975              		.syntax unified
+ 2976              		.thumb
+ 2977              		.thumb_func
+ 2979              	HAL_PCD_IRQHandler:
+ 2980              	.LVL304:
+ 2981              	.LFB335:
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
+ 2982              		.loc 1 1009 1 is_stmt 1 view -0
+ 2983              		.cfi_startproc
+ 2984              		@ args = 0, pretend = 0, frame = 0
+ 2985              		@ frame_needed = 0, uses_anonymous_args = 0
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
+ 2986              		.loc 1 1009 1 is_stmt 0 view .LVU938
+ 2987 0000 10B5     		push	{r4, lr}
+ 2988              	.LCFI19:
+ 2989              		.cfi_def_cfa_offset 8
+ 2990              		.cfi_offset 4, -8
+ 2991              		.cfi_offset 14, -4
+ 2992 0002 0446     		mov	r4, r0
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2993              		.loc 1 1010 3 is_stmt 1 view .LVU939
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2994              		.loc 1 1010 20 is_stmt 0 view .LVU940
+ 2995 0004 0068     		ldr	r0, [r0]
+ 2996              	.LVL305:
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 2997              		.loc 1 1010 20 view .LVU941
+ 2998 0006 FFF7FEFF 		bl	USB_ReadInterrupts
+ 2999              	.LVL306:
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3000              		.loc 1 1012 3 is_stmt 1 view .LVU942
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3001              		.loc 1 1012 6 is_stmt 0 view .LVU943
+ 3002 000a 10F4004F 		tst	r0, #32768
+ 3003 000e 23D1     		bne	.L174
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3004              		.loc 1 1021 3 is_stmt 1 view .LVU944
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3005              		.loc 1 1021 6 is_stmt 0 view .LVU945
+ 3006 0010 10F4806F 		tst	r0, #1024
+ 3007 0014 24D1     		bne	.L175
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3008              		.loc 1 1036 3 is_stmt 1 view .LVU946
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3009              		.loc 1 1036 6 is_stmt 0 view .LVU947
+ 3010 0016 10F4804F 		tst	r0, #16384
+ 3011 001a 32D1     		bne	.L176
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3012              		.loc 1 1043 3 is_stmt 1 view .LVU948
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3013              		.loc 1 1043 6 is_stmt 0 view .LVU949
+ 3014 001c 10F4005F 		tst	r0, #8192
+ARM GAS  /tmp/ccJPteqL.s 			page 106
+
+
+ 3015 0020 39D1     		bne	.L177
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3016              		.loc 1 1050 3 is_stmt 1 view .LVU950
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3017              		.loc 1 1050 6 is_stmt 0 view .LVU951
+ 3018 0022 10F4805F 		tst	r0, #4096
+ 3019 0026 40D1     		bne	.L178
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3020              		.loc 1 1076 3 is_stmt 1 view .LVU952
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3021              		.loc 1 1076 6 is_stmt 0 view .LVU953
+ 3022 0028 10F4006F 		tst	r0, #2048
+ 3023 002c 67D1     		bne	.L179
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3024              		.loc 1 1096 3 is_stmt 1 view .LVU954
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3025              		.loc 1 1096 6 is_stmt 0 view .LVU955
+ 3026 002e 10F0800F 		tst	r0, #128
+ 3027 0032 40F08180 		bne	.L180
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3028              		.loc 1 1125 3 is_stmt 1 view .LVU956
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3029              		.loc 1 1125 6 is_stmt 0 view .LVU957
+ 3030 0036 10F4007F 		tst	r0, #512
+ 3031 003a 40F0AD80 		bne	.L181
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3032              		.loc 1 1138 3 is_stmt 1 view .LVU958
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3033              		.loc 1 1138 6 is_stmt 0 view .LVU959
+ 3034 003e 10F4807F 		tst	r0, #256
+ 3035 0042 27D0     		beq	.L160
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3036              		.loc 1 1141 5 is_stmt 1 view .LVU960
+ 3037 0044 2268     		ldr	r2, [r4]
+ 3038 0046 B2F84430 		ldrh	r3, [r2, #68]
+ 3039 004a 9BB2     		uxth	r3, r3
+ 3040 004c 23F48073 		bic	r3, r3, #256
+ 3041 0050 9BB2     		uxth	r3, r3
+ 3042 0052 A2F84430 		strh	r3, [r2, #68]	@ movhi
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3043              		.loc 1 1143 5 view .LVU961
+ 3044 0056 1DE0     		b	.L160
+ 3045              	.L174:
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3046              		.loc 1 1016 5 view .LVU962
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3047              		.loc 1 1016 11 is_stmt 0 view .LVU963
+ 3048 0058 2046     		mov	r0, r4
+ 3049              	.LVL307:
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3050              		.loc 1 1016 11 view .LVU964
+ 3051 005a FFF7FEFF 		bl	PCD_EP_ISR_Handler
+ 3052              	.LVL308:
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3053              		.loc 1 1018 5 is_stmt 1 view .LVU965
+ 3054 005e 19E0     		b	.L160
+ 3055              	.LVL309:
+ARM GAS  /tmp/ccJPteqL.s 			page 107
+
+
+ 3056              	.L175:
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3057              		.loc 1 1023 5 view .LVU966
+ 3058 0060 2268     		ldr	r2, [r4]
+ 3059 0062 B2F84430 		ldrh	r3, [r2, #68]
+ 3060 0066 9BB2     		uxth	r3, r3
+ 3061 0068 23F48063 		bic	r3, r3, #1024
+ 3062 006c 9BB2     		uxth	r3, r3
+ 3063 006e A2F84430 		strh	r3, [r2, #68]	@ movhi
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3064              		.loc 1 1028 5 view .LVU967
+ 3065 0072 2046     		mov	r0, r4
+ 3066              	.LVL310:
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3067              		.loc 1 1028 5 is_stmt 0 view .LVU968
+ 3068 0074 FFF7FEFF 		bl	HAL_PCD_ResetCallback
+ 3069              	.LVL311:
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3070              		.loc 1 1031 5 is_stmt 1 view .LVU969
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3071              		.loc 1 1031 11 is_stmt 0 view .LVU970
+ 3072 0078 0021     		movs	r1, #0
+ 3073 007a 2046     		mov	r0, r4
+ 3074 007c FFF7FEFF 		bl	HAL_PCD_SetAddress
+ 3075              	.LVL312:
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3076              		.loc 1 1033 5 is_stmt 1 view .LVU971
+ 3077 0080 08E0     		b	.L160
+ 3078              	.LVL313:
+ 3079              	.L176:
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3080              		.loc 1 1038 5 view .LVU972
+ 3081 0082 2268     		ldr	r2, [r4]
+ 3082 0084 B2F84430 		ldrh	r3, [r2, #68]
+ 3083 0088 9BB2     		uxth	r3, r3
+ 3084 008a 23F48043 		bic	r3, r3, #16384
+ 3085 008e 9BB2     		uxth	r3, r3
+ 3086 0090 A2F84430 		strh	r3, [r2, #68]	@ movhi
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3087              		.loc 1 1040 5 view .LVU973
+ 3088              	.LVL314:
+ 3089              	.L160:
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3090              		.loc 1 1145 1 is_stmt 0 view .LVU974
+ 3091 0094 10BD     		pop	{r4, pc}
+ 3092              	.LVL315:
+ 3093              	.L177:
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3094              		.loc 1 1045 5 is_stmt 1 view .LVU975
+ 3095 0096 2268     		ldr	r2, [r4]
+ 3096 0098 B2F84430 		ldrh	r3, [r2, #68]
+ 3097 009c 9BB2     		uxth	r3, r3
+ 3098 009e 23F40053 		bic	r3, r3, #8192
+ 3099 00a2 9BB2     		uxth	r3, r3
+ 3100 00a4 A2F84430 		strh	r3, [r2, #68]	@ movhi
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3101              		.loc 1 1047 5 view .LVU976
+ARM GAS  /tmp/ccJPteqL.s 			page 108
+
+
+ 3102 00a8 F4E7     		b	.L160
+ 3103              	.L178:
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
+ 3104              		.loc 1 1052 5 view .LVU977
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
+ 3105              		.loc 1 1052 9 is_stmt 0 view .LVU978
+ 3106 00aa 2268     		ldr	r2, [r4]
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
+ 3107              		.loc 1 1052 19 view .LVU979
+ 3108 00ac B2F84030 		ldrh	r3, [r2, #64]
+ 3109 00b0 9BB2     		uxth	r3, r3
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
+ 3110              		.loc 1 1052 26 view .LVU980
+ 3111 00b2 23F00403 		bic	r3, r3, #4
+ 3112 00b6 9BB2     		uxth	r3, r3
+ 3113 00b8 A2F84030 		strh	r3, [r2, #64]	@ movhi
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3114              		.loc 1 1053 5 is_stmt 1 view .LVU981
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3115              		.loc 1 1053 9 is_stmt 0 view .LVU982
+ 3116 00bc 2268     		ldr	r2, [r4]
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3117              		.loc 1 1053 19 view .LVU983
+ 3118 00be B2F84030 		ldrh	r3, [r2, #64]
+ 3119 00c2 9BB2     		uxth	r3, r3
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3120              		.loc 1 1053 26 view .LVU984
+ 3121 00c4 23F00803 		bic	r3, r3, #8
+ 3122 00c8 9BB2     		uxth	r3, r3
+ 3123 00ca A2F84030 		strh	r3, [r2, #64]	@ movhi
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 3124              		.loc 1 1055 5 is_stmt 1 view .LVU985
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 3125              		.loc 1 1055 13 is_stmt 0 view .LVU986
+ 3126 00ce 94F8E032 		ldrb	r3, [r4, #736]	@ zero_extendqisi2
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 3127              		.loc 1 1055 8 view .LVU987
+ 3128 00d2 012B     		cmp	r3, #1
+ 3129 00d4 0CD0     		beq	.L182
+ 3130              	.LVL316:
+ 3131              	.L167:
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3132              		.loc 1 1068 5 is_stmt 1 view .LVU988
+ 3133 00d6 2046     		mov	r0, r4
+ 3134 00d8 FFF7FEFF 		bl	HAL_PCD_ResumeCallback
+ 3135              	.LVL317:
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3136              		.loc 1 1071 5 view .LVU989
+ 3137 00dc 2268     		ldr	r2, [r4]
+ 3138 00de B2F84430 		ldrh	r3, [r2, #68]
+ 3139 00e2 9BB2     		uxth	r3, r3
+ 3140 00e4 23F48053 		bic	r3, r3, #4096
+ 3141 00e8 9BB2     		uxth	r3, r3
+ 3142 00ea A2F84430 		strh	r3, [r2, #68]	@ movhi
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3143              		.loc 1 1073 5 view .LVU990
+ 3144 00ee D1E7     		b	.L160
+ARM GAS  /tmp/ccJPteqL.s 			page 109
+
+
+ 3145              	.LVL318:
+ 3146              	.L182:
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 3147              		.loc 1 1057 7 view .LVU991
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 3148              		.loc 1 1057 23 is_stmt 0 view .LVU992
+ 3149 00f0 0021     		movs	r1, #0
+ 3150 00f2 84F8E012 		strb	r1, [r4, #736]
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3151              		.loc 1 1061 7 is_stmt 1 view .LVU993
+ 3152 00f6 2046     		mov	r0, r4
+ 3153              	.LVL319:
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3154              		.loc 1 1061 7 is_stmt 0 view .LVU994
+ 3155 00f8 FFF7FEFF 		bl	HAL_PCDEx_LPM_Callback
+ 3156              	.LVL320:
+ 3157 00fc EBE7     		b	.L167
+ 3158              	.LVL321:
+ 3159              	.L179:
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3160              		.loc 1 1079 5 is_stmt 1 view .LVU995
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3161              		.loc 1 1079 9 is_stmt 0 view .LVU996
+ 3162 00fe 2268     		ldr	r2, [r4]
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3163              		.loc 1 1079 19 view .LVU997
+ 3164 0100 B2F84030 		ldrh	r3, [r2, #64]
+ 3165 0104 9BB2     		uxth	r3, r3
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3166              		.loc 1 1079 26 view .LVU998
+ 3167 0106 43F00803 		orr	r3, r3, #8
+ 3168 010a A2F84030 		strh	r3, [r2, #64]	@ movhi
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3169              		.loc 1 1082 5 is_stmt 1 view .LVU999
+ 3170 010e 2268     		ldr	r2, [r4]
+ 3171 0110 B2F84430 		ldrh	r3, [r2, #68]
+ 3172 0114 9BB2     		uxth	r3, r3
+ 3173 0116 23F40063 		bic	r3, r3, #2048
+ 3174 011a 9BB2     		uxth	r3, r3
+ 3175 011c A2F84430 		strh	r3, [r2, #68]	@ movhi
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3176              		.loc 1 1084 5 view .LVU1000
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3177              		.loc 1 1084 9 is_stmt 0 view .LVU1001
+ 3178 0120 2268     		ldr	r2, [r4]
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3179              		.loc 1 1084 19 view .LVU1002
+ 3180 0122 B2F84030 		ldrh	r3, [r2, #64]
+ 3181 0126 9BB2     		uxth	r3, r3
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3182              		.loc 1 1084 26 view .LVU1003
+ 3183 0128 43F00403 		orr	r3, r3, #4
+ 3184 012c A2F84030 		strh	r3, [r2, #64]	@ movhi
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3185              		.loc 1 1089 5 is_stmt 1 view .LVU1004
+ 3186 0130 2046     		mov	r0, r4
+ 3187              	.LVL322:
+ARM GAS  /tmp/ccJPteqL.s 			page 110
+
+
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3188              		.loc 1 1089 5 is_stmt 0 view .LVU1005
+ 3189 0132 FFF7FEFF 		bl	HAL_PCD_SuspendCallback
+ 3190              	.LVL323:
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3191              		.loc 1 1092 5 is_stmt 1 view .LVU1006
+ 3192 0136 ADE7     		b	.L160
+ 3193              	.LVL324:
+ 3194              	.L180:
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     if (hpcd->LPM_State == LPM_L0)
+ 3195              		.loc 1 1098 5 view .LVU1007
+ 3196 0138 2268     		ldr	r2, [r4]
+ 3197 013a B2F84430 		ldrh	r3, [r2, #68]
+ 3198 013e 9BB2     		uxth	r3, r3
+ 3199 0140 23F08003 		bic	r3, r3, #128
+ 3200 0144 9BB2     		uxth	r3, r3
+ 3201 0146 A2F84430 		strh	r3, [r2, #68]	@ movhi
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 3202              		.loc 1 1099 5 view .LVU1008
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 3203              		.loc 1 1099 13 is_stmt 0 view .LVU1009
+ 3204 014a 94F8E032 		ldrb	r3, [r4, #736]	@ zero_extendqisi2
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     {
+ 3205              		.loc 1 1099 8 view .LVU1010
+ 3206 014e FBB9     		cbnz	r3, .L170
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
+ 3207              		.loc 1 1102 7 is_stmt 1 view .LVU1011
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
+ 3208              		.loc 1 1102 11 is_stmt 0 view .LVU1012
+ 3209 0150 2268     		ldr	r2, [r4]
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
+ 3210              		.loc 1 1102 21 view .LVU1013
+ 3211 0152 B2F84030 		ldrh	r3, [r2, #64]
+ 3212 0156 9BB2     		uxth	r3, r3
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
+ 3213              		.loc 1 1102 28 view .LVU1014
+ 3214 0158 43F00403 		orr	r3, r3, #4
+ 3215 015c A2F84030 		strh	r3, [r2, #64]	@ movhi
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3216              		.loc 1 1103 7 is_stmt 1 view .LVU1015
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3217              		.loc 1 1103 11 is_stmt 0 view .LVU1016
+ 3218 0160 2268     		ldr	r2, [r4]
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3219              		.loc 1 1103 21 view .LVU1017
+ 3220 0162 B2F84030 		ldrh	r3, [r2, #64]
+ 3221 0166 9BB2     		uxth	r3, r3
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3222              		.loc 1 1103 28 view .LVU1018
+ 3223 0168 43F00803 		orr	r3, r3, #8
+ 3224 016c A2F84030 		strh	r3, [r2, #64]	@ movhi
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
+ 3225              		.loc 1 1105 7 is_stmt 1 view .LVU1019
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****       hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
+ 3226              		.loc 1 1105 23 is_stmt 0 view .LVU1020
+ 3227 0170 0121     		movs	r1, #1
+ 3228 0172 84F8E012 		strb	r1, [r4, #736]
+ARM GAS  /tmp/ccJPteqL.s 			page 111
+
+
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 3229              		.loc 1 1106 7 is_stmt 1 view .LVU1021
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 3230              		.loc 1 1106 35 is_stmt 0 view .LVU1022
+ 3231 0176 2368     		ldr	r3, [r4]
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 3232              		.loc 1 1106 45 view .LVU1023
+ 3233 0178 B3F85430 		ldrh	r3, [r3, #84]
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 3234              		.loc 1 1106 73 view .LVU1024
+ 3235 017c C3F38D03 		ubfx	r3, r3, #2, #14
+ 3236 0180 03F03C03 		and	r3, r3, #60
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 3237              		.loc 1 1106 18 view .LVU1025
+ 3238 0184 C4F8E432 		str	r3, [r4, #740]
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3239              		.loc 1 1110 7 is_stmt 1 view .LVU1026
+ 3240 0188 2046     		mov	r0, r4
+ 3241              	.LVL325:
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3242              		.loc 1 1110 7 is_stmt 0 view .LVU1027
+ 3243 018a FFF7FEFF 		bl	HAL_PCDEx_LPM_Callback
+ 3244              	.LVL326:
+ 3245 018e 81E7     		b	.L160
+ 3246              	.LVL327:
+ 3247              	.L170:
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3248              		.loc 1 1118 7 is_stmt 1 view .LVU1028
+ 3249 0190 2046     		mov	r0, r4
+ 3250              	.LVL328:
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3251              		.loc 1 1118 7 is_stmt 0 view .LVU1029
+ 3252 0192 FFF7FEFF 		bl	HAL_PCD_SuspendCallback
+ 3253              	.LVL329:
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3254              		.loc 1 1122 5 is_stmt 1 view .LVU1030
+ 3255 0196 7DE7     		b	.L160
+ 3256              	.LVL330:
+ 3257              	.L181:
+1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3258              		.loc 1 1127 5 view .LVU1031
+ 3259 0198 2268     		ldr	r2, [r4]
+ 3260 019a B2F84430 		ldrh	r3, [r2, #68]
+ 3261 019e 9BB2     		uxth	r3, r3
+ 3262 01a0 23F40073 		bic	r3, r3, #512
+ 3263 01a4 9BB2     		uxth	r3, r3
+ 3264 01a6 A2F84430 		strh	r3, [r2, #68]	@ movhi
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3265              		.loc 1 1132 5 view .LVU1032
+ 3266 01aa 2046     		mov	r0, r4
+ 3267              	.LVL331:
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 3268              		.loc 1 1132 5 is_stmt 0 view .LVU1033
+ 3269 01ac FFF7FEFF 		bl	HAL_PCD_SOFCallback
+ 3270              	.LVL332:
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3271              		.loc 1 1135 5 is_stmt 1 view .LVU1034
+ARM GAS  /tmp/ccJPteqL.s 			page 112
+
+
+ 3272 01b0 70E7     		b	.L160
+ 3273              		.cfi_endproc
+ 3274              	.LFE335:
+ 3276              		.section	.text.HAL_PCD_EP_Open,"ax",%progbits
+ 3277              		.align	1
+ 3278              		.global	HAL_PCD_EP_Open
+ 3279              		.syntax unified
+ 3280              		.thumb
+ 3281              		.thumb_func
+ 3283              	HAL_PCD_EP_Open:
+ 3284              	.LVL333:
+ 3285              	.LFB350:
+1392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef  ret = HAL_OK;
+ 3286              		.loc 1 1392 1 view -0
+ 3287              		.cfi_startproc
+ 3288              		@ args = 0, pretend = 0, frame = 0
+ 3289              		@ frame_needed = 0, uses_anonymous_args = 0
+1392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   HAL_StatusTypeDef  ret = HAL_OK;
+ 3290              		.loc 1 1392 1 is_stmt 0 view .LVU1036
+ 3291 0000 10B5     		push	{r4, lr}
+ 3292              	.LCFI20:
+ 3293              		.cfi_def_cfa_offset 8
+ 3294              		.cfi_offset 4, -8
+ 3295              		.cfi_offset 14, -4
+ 3296 0002 0446     		mov	r4, r0
+ 3297 0004 8C46     		mov	ip, r1
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3298              		.loc 1 1393 3 is_stmt 1 view .LVU1037
+ 3299              	.LVL334:
+1394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3300              		.loc 1 1394 3 view .LVU1038
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3301              		.loc 1 1396 3 view .LVU1039
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3302              		.loc 1 1396 6 is_stmt 0 view .LVU1040
+ 3303 0006 11F0800F 		tst	r1, #128
+ 3304 000a 2AD1     		bne	.L191
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3305              		.loc 1 1403 5 is_stmt 1 view .LVU1041
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3306              		.loc 1 1403 32 is_stmt 0 view .LVU1042
+ 3307 000c 01F00700 		and	r0, r1, #7
+ 3308              	.LVL335:
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3309              		.loc 1 1403 8 view .LVU1043
+ 3310 0010 00EB8001 		add	r1, r0, r0, lsl #2
+ 3311              	.LVL336:
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3312              		.loc 1 1403 8 view .LVU1044
+ 3313 0014 C900     		lsls	r1, r1, #3
+ 3314 0016 01F5B47E 		add	lr, r1, #360
+ 3315 001a 04EB0E01 		add	r1, r4, lr
+ 3316              	.LVL337:
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3317              		.loc 1 1404 5 is_stmt 1 view .LVU1045
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3318              		.loc 1 1404 15 is_stmt 0 view .LVU1046
+ARM GAS  /tmp/ccJPteqL.s 			page 113
+
+
+ 3319 001e 00EB8000 		add	r0, r0, r0, lsl #2
+ 3320 0022 04EBC000 		add	r0, r4, r0, lsl #3
+ 3321 0026 4FF0000E 		mov	lr, #0
+ 3322 002a 80F869E1 		strb	lr, [r0, #361]
+ 3323              	.L185:
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->maxpacket = ep_mps;
+ 3324              		.loc 1 1407 3 is_stmt 1 view .LVU1047
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->maxpacket = ep_mps;
+ 3325              		.loc 1 1407 21 is_stmt 0 view .LVU1048
+ 3326 002e 0CF0070C 		and	ip, ip, #7
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->maxpacket = ep_mps;
+ 3327              		.loc 1 1407 11 view .LVU1049
+ 3328 0032 81F800C0 		strb	ip, [r1]
+1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->type = ep_type;
+ 3329              		.loc 1 1408 3 is_stmt 1 view .LVU1050
+1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->type = ep_type;
+ 3330              		.loc 1 1408 17 is_stmt 0 view .LVU1051
+ 3331 0036 0A61     		str	r2, [r1, #16]
+1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3332              		.loc 1 1409 3 is_stmt 1 view .LVU1052
+1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3333              		.loc 1 1409 12 is_stmt 0 view .LVU1053
+ 3334 0038 CB70     		strb	r3, [r1, #3]
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3335              		.loc 1 1411 3 is_stmt 1 view .LVU1054
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3336              		.loc 1 1411 9 is_stmt 0 view .LVU1055
+ 3337 003a 4A78     		ldrb	r2, [r1, #1]	@ zero_extendqisi2
+ 3338              	.LVL338:
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3339              		.loc 1 1411 6 view .LVU1056
+ 3340 003c 0AB1     		cbz	r2, .L186
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3341              		.loc 1 1414 5 is_stmt 1 view .LVU1057
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3342              		.loc 1 1414 21 is_stmt 0 view .LVU1058
+ 3343 003e A1F80EC0 		strh	ip, [r1, #14]	@ movhi
+ 3344              	.L186:
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3345              		.loc 1 1417 3 is_stmt 1 view .LVU1059
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3346              		.loc 1 1417 6 is_stmt 0 view .LVU1060
+ 3347 0042 022B     		cmp	r3, #2
+ 3348 0044 19D0     		beq	.L192
+ 3349              	.LVL339:
+ 3350              	.L187:
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+ 3351              		.loc 1 1422 3 is_stmt 1 view .LVU1061
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+ 3352              		.loc 1 1422 3 view .LVU1062
+ 3353 0046 94F8A832 		ldrb	r3, [r4, #680]	@ zero_extendqisi2
+ 3354 004a 012B     		cmp	r3, #1
+ 3355 004c 18D0     		beq	.L189
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+ 3356              		.loc 1 1422 3 discriminator 2 view .LVU1063
+ 3357 004e 0123     		movs	r3, #1
+ 3358 0050 84F8A832 		strb	r3, [r4, #680]
+ARM GAS  /tmp/ccJPteqL.s 			page 114
+
+
+ 3359              	.LVL340:
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+ 3360              		.loc 1 1422 3 discriminator 2 view .LVU1064
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 3361              		.loc 1 1423 3 discriminator 2 view .LVU1065
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 3362              		.loc 1 1423 9 is_stmt 0 discriminator 2 view .LVU1066
+ 3363 0054 2068     		ldr	r0, [r4]
+ 3364 0056 FFF7FEFF 		bl	USB_ActivateEndpoint
+ 3365              	.LVL341:
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3366              		.loc 1 1424 3 is_stmt 1 discriminator 2 view .LVU1067
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3367              		.loc 1 1424 3 discriminator 2 view .LVU1068
+ 3368 005a 0020     		movs	r0, #0
+ 3369 005c 84F8A802 		strb	r0, [r4, #680]
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3370              		.loc 1 1424 3 discriminator 2 view .LVU1069
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 3371              		.loc 1 1426 3 discriminator 2 view .LVU1070
+ 3372              	.L188:
+1427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3373              		.loc 1 1427 1 is_stmt 0 view .LVU1071
+ 3374 0060 10BD     		pop	{r4, pc}
+ 3375              	.LVL342:
+ 3376              	.L191:
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3377              		.loc 1 1398 5 is_stmt 1 view .LVU1072
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3378              		.loc 1 1398 31 is_stmt 0 view .LVU1073
+ 3379 0062 01F00700 		and	r0, r1, #7
+ 3380              	.LVL343:
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3381              		.loc 1 1398 8 view .LVU1074
+ 3382 0066 0130     		adds	r0, r0, #1
+ 3383 0068 00EB8001 		add	r1, r0, r0, lsl #2
+ 3384              	.LVL344:
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3385              		.loc 1 1398 8 view .LVU1075
+ 3386 006c 04EBC101 		add	r1, r4, r1, lsl #3
+ 3387              	.LVL345:
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3388              		.loc 1 1399 5 is_stmt 1 view .LVU1076
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3389              		.loc 1 1399 15 is_stmt 0 view .LVU1077
+ 3390 0070 4FF0010E 		mov	lr, #1
+ 3391 0074 81F801E0 		strb	lr, [r1, #1]
+ 3392 0078 D9E7     		b	.L185
+ 3393              	.LVL346:
+ 3394              	.L192:
+1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3395              		.loc 1 1419 5 is_stmt 1 view .LVU1078
+1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3396              		.loc 1 1419 24 is_stmt 0 view .LVU1079
+ 3397 007a 0023     		movs	r3, #0
+ 3398              	.LVL347:
+1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ARM GAS  /tmp/ccJPteqL.s 			page 115
+
+
+ 3399              		.loc 1 1419 24 view .LVU1080
+ 3400 007c 0B71     		strb	r3, [r1, #4]
+ 3401 007e E2E7     		b	.L187
+ 3402              	.L189:
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+ 3403              		.loc 1 1422 3 view .LVU1081
+ 3404 0080 0220     		movs	r0, #2
+ 3405 0082 EDE7     		b	.L188
+ 3406              		.cfi_endproc
+ 3407              	.LFE350:
+ 3409              		.section	.text.HAL_PCD_EP_Close,"ax",%progbits
+ 3410              		.align	1
+ 3411              		.global	HAL_PCD_EP_Close
+ 3412              		.syntax unified
+ 3413              		.thumb
+ 3414              		.thumb_func
+ 3416              	HAL_PCD_EP_Close:
+ 3417              	.LVL348:
+ 3418              	.LFB351:
+1436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3419              		.loc 1 1436 1 is_stmt 1 view -0
+ 3420              		.cfi_startproc
+ 3421              		@ args = 0, pretend = 0, frame = 0
+ 3422              		@ frame_needed = 0, uses_anonymous_args = 0
+1436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3423              		.loc 1 1436 1 is_stmt 0 view .LVU1083
+ 3424 0000 10B5     		push	{r4, lr}
+ 3425              	.LCFI21:
+ 3426              		.cfi_def_cfa_offset 8
+ 3427              		.cfi_offset 4, -8
+ 3428              		.cfi_offset 14, -4
+ 3429 0002 0446     		mov	r4, r0
+ 3430 0004 0B46     		mov	r3, r1
+1437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3431              		.loc 1 1437 3 is_stmt 1 view .LVU1084
+1439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3432              		.loc 1 1439 3 view .LVU1085
+1439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3433              		.loc 1 1439 6 is_stmt 0 view .LVU1086
+ 3434 0006 11F0800F 		tst	r1, #128
+ 3435 000a 1FD1     		bne	.L199
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3436              		.loc 1 1446 5 is_stmt 1 view .LVU1087
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3437              		.loc 1 1446 32 is_stmt 0 view .LVU1088
+ 3438 000c 01F00702 		and	r2, r1, #7
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3439              		.loc 1 1446 8 view .LVU1089
+ 3440 0010 02EB8201 		add	r1, r2, r2, lsl #2
+ 3441              	.LVL349:
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3442              		.loc 1 1446 8 view .LVU1090
+ 3443 0014 C900     		lsls	r1, r1, #3
+ 3444 0016 01F5B471 		add	r1, r1, #360
+ 3445 001a 0144     		add	r1, r1, r0
+ 3446              	.LVL350:
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ARM GAS  /tmp/ccJPteqL.s 			page 116
+
+
+ 3447              		.loc 1 1447 5 is_stmt 1 view .LVU1091
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3448              		.loc 1 1447 15 is_stmt 0 view .LVU1092
+ 3449 001c 02EB8202 		add	r2, r2, r2, lsl #2
+ 3450 0020 00EBC202 		add	r2, r0, r2, lsl #3
+ 3451 0024 0020     		movs	r0, #0
+ 3452              	.LVL351:
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3453              		.loc 1 1447 15 view .LVU1093
+ 3454 0026 82F86901 		strb	r0, [r2, #361]
+ 3455              	.L195:
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3456              		.loc 1 1449 3 is_stmt 1 view .LVU1094
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3457              		.loc 1 1449 23 is_stmt 0 view .LVU1095
+ 3458 002a 03F00703 		and	r3, r3, #7
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3459              		.loc 1 1449 13 view .LVU1096
+ 3460 002e 0B70     		strb	r3, [r1]
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+ 3461              		.loc 1 1451 3 is_stmt 1 view .LVU1097
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+ 3462              		.loc 1 1451 3 view .LVU1098
+ 3463 0030 94F8A832 		ldrb	r3, [r4, #680]	@ zero_extendqisi2
+ 3464 0034 012B     		cmp	r3, #1
+ 3465 0036 13D0     		beq	.L197
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+ 3466              		.loc 1 1451 3 discriminator 2 view .LVU1099
+ 3467 0038 0123     		movs	r3, #1
+ 3468 003a 84F8A832 		strb	r3, [r4, #680]
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+ 3469              		.loc 1 1451 3 discriminator 2 view .LVU1100
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 3470              		.loc 1 1452 3 discriminator 2 view .LVU1101
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 3471              		.loc 1 1452 9 is_stmt 0 discriminator 2 view .LVU1102
+ 3472 003e 2068     		ldr	r0, [r4]
+ 3473 0040 FFF7FEFF 		bl	USB_DeactivateEndpoint
+ 3474              	.LVL352:
+1453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+ 3475              		.loc 1 1453 3 is_stmt 1 discriminator 2 view .LVU1103
+1453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+ 3476              		.loc 1 1453 3 discriminator 2 view .LVU1104
+ 3477 0044 0020     		movs	r0, #0
+ 3478 0046 84F8A802 		strb	r0, [r4, #680]
+1453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return HAL_OK;
+ 3479              		.loc 1 1453 3 discriminator 2 view .LVU1105
+1454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 3480              		.loc 1 1454 3 discriminator 2 view .LVU1106
+ 3481              	.L196:
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3482              		.loc 1 1455 1 is_stmt 0 view .LVU1107
+ 3483 004a 10BD     		pop	{r4, pc}
+ 3484              	.LVL353:
+ 3485              	.L199:
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3486              		.loc 1 1441 5 is_stmt 1 view .LVU1108
+ARM GAS  /tmp/ccJPteqL.s 			page 117
+
+
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3487              		.loc 1 1441 31 is_stmt 0 view .LVU1109
+ 3488 004c 01F00702 		and	r2, r1, #7
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3489              		.loc 1 1441 8 view .LVU1110
+ 3490 0050 0132     		adds	r2, r2, #1
+ 3491 0052 02EB8201 		add	r1, r2, r2, lsl #2
+ 3492              	.LVL354:
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3493              		.loc 1 1441 8 view .LVU1111
+ 3494 0056 00EBC101 		add	r1, r0, r1, lsl #3
+ 3495              	.LVL355:
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3496              		.loc 1 1442 5 is_stmt 1 view .LVU1112
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3497              		.loc 1 1442 15 is_stmt 0 view .LVU1113
+ 3498 005a 0120     		movs	r0, #1
+ 3499              	.LVL356:
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3500              		.loc 1 1442 15 view .LVU1114
+ 3501 005c 4870     		strb	r0, [r1, #1]
+ 3502 005e E4E7     		b	.L195
+ 3503              	.L197:
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+ 3504              		.loc 1 1451 3 view .LVU1115
+ 3505 0060 0220     		movs	r0, #2
+ 3506 0062 F2E7     		b	.L196
+ 3507              		.cfi_endproc
+ 3508              	.LFE351:
+ 3510              		.section	.text.HAL_PCD_EP_Receive,"ax",%progbits
+ 3511              		.align	1
+ 3512              		.global	HAL_PCD_EP_Receive
+ 3513              		.syntax unified
+ 3514              		.thumb
+ 3515              		.thumb_func
+ 3517              	HAL_PCD_EP_Receive:
+ 3518              	.LVL357:
+ 3519              	.LFB352:
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3520              		.loc 1 1467 1 is_stmt 1 view -0
+ 3521              		.cfi_startproc
+ 3522              		@ args = 0, pretend = 0, frame = 0
+ 3523              		@ frame_needed = 0, uses_anonymous_args = 0
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3524              		.loc 1 1467 1 is_stmt 0 view .LVU1117
+ 3525 0000 10B5     		push	{r4, lr}
+ 3526              	.LCFI22:
+ 3527              		.cfi_def_cfa_offset 8
+ 3528              		.cfi_offset 4, -8
+ 3529              		.cfi_offset 14, -4
+1468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3530              		.loc 1 1468 3 is_stmt 1 view .LVU1118
+1470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3531              		.loc 1 1470 3 view .LVU1119
+ 3532 0002 01F00704 		and	r4, r1, #7
+1470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3533              		.loc 1 1470 6 is_stmt 0 view .LVU1120
+ARM GAS  /tmp/ccJPteqL.s 			page 118
+
+
+ 3534 0006 04EB8401 		add	r1, r4, r4, lsl #2
+ 3535              	.LVL358:
+1470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3536              		.loc 1 1470 6 view .LVU1121
+ 3537 000a C900     		lsls	r1, r1, #3
+ 3538 000c 01F5B471 		add	r1, r1, #360
+ 3539 0010 0144     		add	r1, r1, r0
+ 3540              	.LVL359:
+1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_len = len;
+ 3541              		.loc 1 1473 3 is_stmt 1 view .LVU1122
+1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_len = len;
+ 3542              		.loc 1 1473 17 is_stmt 0 view .LVU1123
+ 3543 0012 04EB840C 		add	ip, r4, r4, lsl #2
+ 3544 0016 00EBCC0C 		add	ip, r0, ip, lsl #3
+ 3545 001a CCF87C21 		str	r2, [ip, #380]
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_count = 0U;
+ 3546              		.loc 1 1474 3 is_stmt 1 view .LVU1124
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_count = 0U;
+ 3547              		.loc 1 1474 16 is_stmt 0 view .LVU1125
+ 3548 001e CCF88031 		str	r3, [ip, #384]
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->is_in = 0U;
+ 3549              		.loc 1 1475 3 is_stmt 1 view .LVU1126
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->is_in = 0U;
+ 3550              		.loc 1 1475 18 is_stmt 0 view .LVU1127
+ 3551 0022 0023     		movs	r3, #0
+ 3552              	.LVL360:
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->is_in = 0U;
+ 3553              		.loc 1 1475 18 view .LVU1128
+ 3554 0024 CCF88431 		str	r3, [ip, #388]
+1476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+ 3555              		.loc 1 1476 3 is_stmt 1 view .LVU1129
+1476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+ 3556              		.loc 1 1476 13 is_stmt 0 view .LVU1130
+ 3557 0028 8CF86931 		strb	r3, [ip, #361]
+1477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3558              		.loc 1 1477 3 is_stmt 1 view .LVU1131
+1477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3559              		.loc 1 1477 11 is_stmt 0 view .LVU1132
+ 3560 002c 8CF86841 		strb	r4, [ip, #360]
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3561              		.loc 1 1479 3 is_stmt 1 view .LVU1133
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3562              		.loc 1 1479 6 is_stmt 0 view .LVU1134
+ 3563 0030 24B9     		cbnz	r4, .L201
+1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3564              		.loc 1 1481 5 is_stmt 1 view .LVU1135
+1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3565              		.loc 1 1481 11 is_stmt 0 view .LVU1136
+ 3566 0032 0068     		ldr	r0, [r0]
+ 3567              	.LVL361:
+1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3568              		.loc 1 1481 11 view .LVU1137
+ 3569 0034 FFF7FEFF 		bl	USB_EPStartXfer
+ 3570              	.LVL362:
+ 3571              	.L202:
+1488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 3572              		.loc 1 1488 3 is_stmt 1 view .LVU1138
+ARM GAS  /tmp/ccJPteqL.s 			page 119
+
+
+1489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3573              		.loc 1 1489 1 is_stmt 0 view .LVU1139
+ 3574 0038 0020     		movs	r0, #0
+ 3575 003a 10BD     		pop	{r4, pc}
+ 3576              	.LVL363:
+ 3577              	.L201:
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3578              		.loc 1 1485 5 is_stmt 1 view .LVU1140
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3579              		.loc 1 1485 11 is_stmt 0 view .LVU1141
+ 3580 003c 0068     		ldr	r0, [r0]
+ 3581              	.LVL364:
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3582              		.loc 1 1485 11 view .LVU1142
+ 3583 003e FFF7FEFF 		bl	USB_EPStartXfer
+ 3584              	.LVL365:
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3585              		.loc 1 1485 11 view .LVU1143
+ 3586 0042 F9E7     		b	.L202
+ 3587              		.cfi_endproc
+ 3588              	.LFE352:
+ 3590              		.section	.text.HAL_PCD_EP_GetRxCount,"ax",%progbits
+ 3591              		.align	1
+ 3592              		.global	HAL_PCD_EP_GetRxCount
+ 3593              		.syntax unified
+ 3594              		.thumb
+ 3595              		.thumb_func
+ 3597              	HAL_PCD_EP_GetRxCount:
+ 3598              	.LVL366:
+ 3599              	.LFB353:
+1498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
+ 3600              		.loc 1 1498 1 is_stmt 1 view -0
+ 3601              		.cfi_startproc
+ 3602              		@ args = 0, pretend = 0, frame = 0
+ 3603              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3604              		@ link register save eliminated.
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 3605              		.loc 1 1499 3 view .LVU1145
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 3606              		.loc 1 1499 31 is_stmt 0 view .LVU1146
+ 3607 0000 01F00701 		and	r1, r1, #7
+ 3608              	.LVL367:
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 3609              		.loc 1 1499 45 view .LVU1147
+ 3610 0004 01EB8101 		add	r1, r1, r1, lsl #2
+ 3611 0008 00EBC100 		add	r0, r0, r1, lsl #3
+ 3612              	.LVL368:
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** /**
+ 3613              		.loc 1 1500 1 view .LVU1148
+ 3614 000c D0F88401 		ldr	r0, [r0, #388]
+ 3615 0010 7047     		bx	lr
+ 3616              		.cfi_endproc
+ 3617              	.LFE353:
+ 3619              		.section	.text.HAL_PCD_EP_Transmit,"ax",%progbits
+ 3620              		.align	1
+ 3621              		.global	HAL_PCD_EP_Transmit
+ 3622              		.syntax unified
+ARM GAS  /tmp/ccJPteqL.s 			page 120
+
+
+ 3623              		.thumb
+ 3624              		.thumb_func
+ 3626              	HAL_PCD_EP_Transmit:
+ 3627              	.LVL369:
+ 3628              	.LFB354:
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3629              		.loc 1 1510 1 is_stmt 1 view -0
+ 3630              		.cfi_startproc
+ 3631              		@ args = 0, pretend = 0, frame = 0
+ 3632              		@ frame_needed = 0, uses_anonymous_args = 0
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3633              		.loc 1 1510 1 is_stmt 0 view .LVU1150
+ 3634 0000 10B5     		push	{r4, lr}
+ 3635              	.LCFI23:
+ 3636              		.cfi_def_cfa_offset 8
+ 3637              		.cfi_offset 4, -8
+ 3638              		.cfi_offset 14, -4
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3639              		.loc 1 1511 3 is_stmt 1 view .LVU1151
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3640              		.loc 1 1513 3 view .LVU1152
+ 3641 0002 01F00704 		and	r4, r1, #7
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3642              		.loc 1 1513 6 is_stmt 0 view .LVU1153
+ 3643 0006 04F1010C 		add	ip, r4, #1
+ 3644 000a 0CEB8C01 		add	r1, ip, ip, lsl #2
+ 3645              	.LVL370:
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3646              		.loc 1 1513 6 view .LVU1154
+ 3647 000e 00EBC101 		add	r1, r0, r1, lsl #3
+ 3648              	.LVL371:
+1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_len = len;
+ 3649              		.loc 1 1516 3 is_stmt 1 view .LVU1155
+1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_len = len;
+ 3650              		.loc 1 1516 17 is_stmt 0 view .LVU1156
+ 3651 0012 04EB840E 		add	lr, r4, r4, lsl #2
+ 3652 0016 00EBCE0E 		add	lr, r0, lr, lsl #3
+ 3653 001a CEF83C20 		str	r2, [lr, #60]
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_fill_db = 1U;
+ 3654              		.loc 1 1517 3 is_stmt 1 view .LVU1157
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_fill_db = 1U;
+ 3655              		.loc 1 1517 16 is_stmt 0 view .LVU1158
+ 3656 001e CEF84030 		str	r3, [lr, #64]
+1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_len_db = len;
+ 3657              		.loc 1 1518 3 is_stmt 1 view .LVU1159
+1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_len_db = len;
+ 3658              		.loc 1 1518 20 is_stmt 0 view .LVU1160
+ 3659 0022 0122     		movs	r2, #1
+ 3660              	.LVL372:
+1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_len_db = len;
+ 3661              		.loc 1 1518 20 view .LVU1161
+ 3662 0024 8EF84C20 		strb	r2, [lr, #76]
+1519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_count = 0U;
+ 3663              		.loc 1 1519 3 is_stmt 1 view .LVU1162
+1519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->xfer_count = 0U;
+ 3664              		.loc 1 1519 19 is_stmt 0 view .LVU1163
+ 3665 0028 CEF84830 		str	r3, [lr, #72]
+ARM GAS  /tmp/ccJPteqL.s 			page 121
+
+
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->is_in = 1U;
+ 3666              		.loc 1 1520 3 is_stmt 1 view .LVU1164
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->is_in = 1U;
+ 3667              		.loc 1 1520 18 is_stmt 0 view .LVU1165
+ 3668 002c 0023     		movs	r3, #0
+ 3669              	.LVL373:
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->is_in = 1U;
+ 3670              		.loc 1 1520 18 view .LVU1166
+ 3671 002e CEF84430 		str	r3, [lr, #68]
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+ 3672              		.loc 1 1521 3 is_stmt 1 view .LVU1167
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+ 3673              		.loc 1 1521 13 is_stmt 0 view .LVU1168
+ 3674 0032 4A70     		strb	r2, [r1, #1]
+ 3675              	.LVL374:
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3676              		.loc 1 1522 3 is_stmt 1 view .LVU1169
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3677              		.loc 1 1522 11 is_stmt 0 view .LVU1170
+ 3678 0034 0CEB8C0C 		add	ip, ip, ip, lsl #2
+ 3679 0038 00F83C40 		strb	r4, [r0, ip, lsl #3]
+1524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3680              		.loc 1 1524 3 is_stmt 1 view .LVU1171
+1524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3681              		.loc 1 1524 6 is_stmt 0 view .LVU1172
+ 3682 003c 24B9     		cbnz	r4, .L206
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3683              		.loc 1 1526 5 is_stmt 1 view .LVU1173
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3684              		.loc 1 1526 11 is_stmt 0 view .LVU1174
+ 3685 003e 0068     		ldr	r0, [r0]
+ 3686              	.LVL375:
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3687              		.loc 1 1526 11 view .LVU1175
+ 3688 0040 FFF7FEFF 		bl	USB_EPStartXfer
+ 3689              	.LVL376:
+ 3690              	.L207:
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 3691              		.loc 1 1533 3 is_stmt 1 view .LVU1176
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3692              		.loc 1 1534 1 is_stmt 0 view .LVU1177
+ 3693 0044 0020     		movs	r0, #0
+ 3694 0046 10BD     		pop	{r4, pc}
+ 3695              	.LVL377:
+ 3696              	.L206:
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3697              		.loc 1 1530 5 is_stmt 1 view .LVU1178
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3698              		.loc 1 1530 11 is_stmt 0 view .LVU1179
+ 3699 0048 0068     		ldr	r0, [r0]
+ 3700              	.LVL378:
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3701              		.loc 1 1530 11 view .LVU1180
+ 3702 004a FFF7FEFF 		bl	USB_EPStartXfer
+ 3703              	.LVL379:
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3704              		.loc 1 1530 11 view .LVU1181
+ARM GAS  /tmp/ccJPteqL.s 			page 122
+
+
+ 3705 004e F9E7     		b	.L207
+ 3706              		.cfi_endproc
+ 3707              	.LFE354:
+ 3709              		.section	.text.HAL_PCD_EP_SetStall,"ax",%progbits
+ 3710              		.align	1
+ 3711              		.global	HAL_PCD_EP_SetStall
+ 3712              		.syntax unified
+ 3713              		.thumb
+ 3714              		.thumb_func
+ 3716              	HAL_PCD_EP_SetStall:
+ 3717              	.LVL380:
+ 3718              	.LFB355:
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3719              		.loc 1 1543 1 is_stmt 1 view -0
+ 3720              		.cfi_startproc
+ 3721              		@ args = 0, pretend = 0, frame = 0
+ 3722              		@ frame_needed = 0, uses_anonymous_args = 0
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3723              		.loc 1 1543 1 is_stmt 0 view .LVU1183
+ 3724 0000 0B46     		mov	r3, r1
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3725              		.loc 1 1544 3 is_stmt 1 view .LVU1184
+1546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3726              		.loc 1 1546 3 view .LVU1185
+ 3727 0002 01F00702 		and	r2, r1, #7
+1546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3728              		.loc 1 1546 53 is_stmt 0 view .LVU1186
+ 3729 0006 4168     		ldr	r1, [r0, #4]
+ 3730              	.LVL381:
+1546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3731              		.loc 1 1546 6 view .LVU1187
+ 3732 0008 8A42     		cmp	r2, r1
+ 3733 000a 2AD8     		bhi	.L213
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3734              		.loc 1 1543 1 view .LVU1188
+ 3735 000c 10B5     		push	{r4, lr}
+ 3736              	.LCFI24:
+ 3737              		.cfi_def_cfa_offset 8
+ 3738              		.cfi_offset 4, -8
+ 3739              		.cfi_offset 14, -4
+ 3740 000e 0446     		mov	r4, r0
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3741              		.loc 1 1551 3 is_stmt 1 view .LVU1189
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3742              		.loc 1 1551 6 is_stmt 0 view .LVU1190
+ 3743 0010 13F0800F 		tst	r3, #128
+ 3744 0014 1DD1     		bne	.L219
+1558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3745              		.loc 1 1558 5 is_stmt 1 view .LVU1191
+1558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3746              		.loc 1 1558 8 is_stmt 0 view .LVU1192
+ 3747 0016 03EB8301 		add	r1, r3, r3, lsl #2
+ 3748 001a C900     		lsls	r1, r1, #3
+ 3749 001c 01F5B471 		add	r1, r1, #360
+ 3750 0020 0144     		add	r1, r1, r0
+ 3751              	.LVL382:
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ARM GAS  /tmp/ccJPteqL.s 			page 123
+
+
+ 3752              		.loc 1 1559 5 is_stmt 1 view .LVU1193
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3753              		.loc 1 1559 15 is_stmt 0 view .LVU1194
+ 3754 0022 03EB8303 		add	r3, r3, r3, lsl #2
+ 3755 0026 00EBC303 		add	r3, r0, r3, lsl #3
+ 3756 002a 0020     		movs	r0, #0
+ 3757              	.LVL383:
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3758              		.loc 1 1559 15 view .LVU1195
+ 3759 002c 83F86901 		strb	r0, [r3, #361]
+ 3760              	.L212:
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+ 3761              		.loc 1 1562 3 is_stmt 1 view .LVU1196
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+ 3762              		.loc 1 1562 16 is_stmt 0 view .LVU1197
+ 3763 0030 0123     		movs	r3, #1
+ 3764 0032 8B70     		strb	r3, [r1, #2]
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3765              		.loc 1 1563 3 is_stmt 1 view .LVU1198
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3766              		.loc 1 1563 11 is_stmt 0 view .LVU1199
+ 3767 0034 0A70     		strb	r2, [r1]
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3768              		.loc 1 1565 3 is_stmt 1 view .LVU1200
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3769              		.loc 1 1565 3 view .LVU1201
+ 3770 0036 94F8A832 		ldrb	r3, [r4, #680]	@ zero_extendqisi2
+ 3771 003a 012B     		cmp	r3, #1
+ 3772 003c 13D0     		beq	.L214
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3773              		.loc 1 1565 3 discriminator 2 view .LVU1202
+ 3774 003e 0123     		movs	r3, #1
+ 3775 0040 84F8A832 		strb	r3, [r4, #680]
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3776              		.loc 1 1565 3 discriminator 2 view .LVU1203
+1567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3777              		.loc 1 1567 3 discriminator 2 view .LVU1204
+1567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3778              		.loc 1 1567 9 is_stmt 0 discriminator 2 view .LVU1205
+ 3779 0044 2068     		ldr	r0, [r4]
+ 3780 0046 FFF7FEFF 		bl	USB_EPSetStall
+ 3781              	.LVL384:
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3782              		.loc 1 1569 3 is_stmt 1 discriminator 2 view .LVU1206
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3783              		.loc 1 1569 3 discriminator 2 view .LVU1207
+ 3784 004a 0020     		movs	r0, #0
+ 3785 004c 84F8A802 		strb	r0, [r4, #680]
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3786              		.loc 1 1569 3 discriminator 2 view .LVU1208
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 3787              		.loc 1 1571 3 discriminator 2 view .LVU1209
+ 3788              	.L210:
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3789              		.loc 1 1572 1 is_stmt 0 view .LVU1210
+ 3790 0050 10BD     		pop	{r4, pc}
+ 3791              	.LVL385:
+ARM GAS  /tmp/ccJPteqL.s 			page 124
+
+
+ 3792              	.L219:
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3793              		.loc 1 1553 5 is_stmt 1 view .LVU1211
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3794              		.loc 1 1553 8 is_stmt 0 view .LVU1212
+ 3795 0052 531C     		adds	r3, r2, #1
+ 3796 0054 03EB8301 		add	r1, r3, r3, lsl #2
+ 3797 0058 00EBC101 		add	r1, r0, r1, lsl #3
+ 3798              	.LVL386:
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3799              		.loc 1 1554 5 is_stmt 1 view .LVU1213
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3800              		.loc 1 1554 15 is_stmt 0 view .LVU1214
+ 3801 005c 0120     		movs	r0, #1
+ 3802              	.LVL387:
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3803              		.loc 1 1554 15 view .LVU1215
+ 3804 005e 4870     		strb	r0, [r1, #1]
+ 3805 0060 E6E7     		b	.L212
+ 3806              	.LVL388:
+ 3807              	.L213:
+ 3808              	.LCFI25:
+ 3809              		.cfi_def_cfa_offset 0
+ 3810              		.cfi_restore 4
+ 3811              		.cfi_restore 14
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3812              		.loc 1 1548 12 view .LVU1216
+ 3813 0062 0120     		movs	r0, #1
+ 3814              	.LVL389:
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3815              		.loc 1 1572 1 view .LVU1217
+ 3816 0064 7047     		bx	lr
+ 3817              	.LVL390:
+ 3818              	.L214:
+ 3819              	.LCFI26:
+ 3820              		.cfi_def_cfa_offset 8
+ 3821              		.cfi_offset 4, -8
+ 3822              		.cfi_offset 14, -4
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3823              		.loc 1 1565 3 view .LVU1218
+ 3824 0066 0220     		movs	r0, #2
+ 3825 0068 F2E7     		b	.L210
+ 3826              		.cfi_endproc
+ 3827              	.LFE355:
+ 3829              		.section	.text.HAL_PCD_EP_ClrStall,"ax",%progbits
+ 3830              		.align	1
+ 3831              		.global	HAL_PCD_EP_ClrStall
+ 3832              		.syntax unified
+ 3833              		.thumb
+ 3834              		.thumb_func
+ 3836              	HAL_PCD_EP_ClrStall:
+ 3837              	.LVL391:
+ 3838              	.LFB356:
+1581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3839              		.loc 1 1581 1 is_stmt 1 view -0
+ 3840              		.cfi_startproc
+ 3841              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/ccJPteqL.s 			page 125
+
+
+ 3842              		@ frame_needed = 0, uses_anonymous_args = 0
+1581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3843              		.loc 1 1581 1 is_stmt 0 view .LVU1220
+ 3844 0000 0B46     		mov	r3, r1
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3845              		.loc 1 1582 3 is_stmt 1 view .LVU1221
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3846              		.loc 1 1584 3 view .LVU1222
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3847              		.loc 1 1584 26 is_stmt 0 view .LVU1223
+ 3848 0002 01F00F01 		and	r1, r1, #15
+ 3849              	.LVL392:
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3850              		.loc 1 1584 47 view .LVU1224
+ 3851 0006 4268     		ldr	r2, [r0, #4]
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3852              		.loc 1 1584 6 view .LVU1225
+ 3853 0008 9142     		cmp	r1, r2
+ 3854 000a 30D8     		bhi	.L224
+1581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   PCD_EPTypeDef *ep;
+ 3855              		.loc 1 1581 1 view .LVU1226
+ 3856 000c 10B5     		push	{r4, lr}
+ 3857              	.LCFI27:
+ 3858              		.cfi_def_cfa_offset 8
+ 3859              		.cfi_offset 4, -8
+ 3860              		.cfi_offset 14, -4
+ 3861 000e 0446     		mov	r4, r0
+1589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3862              		.loc 1 1589 3 is_stmt 1 view .LVU1227
+1589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   {
+ 3863              		.loc 1 1589 6 is_stmt 0 view .LVU1228
+ 3864 0010 13F0800F 		tst	r3, #128
+ 3865 0014 21D1     		bne	.L230
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3866              		.loc 1 1596 5 is_stmt 1 view .LVU1229
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3867              		.loc 1 1596 32 is_stmt 0 view .LVU1230
+ 3868 0016 03F00702 		and	r2, r3, #7
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 0U;
+ 3869              		.loc 1 1596 8 view .LVU1231
+ 3870 001a 02EB8201 		add	r1, r2, r2, lsl #2
+ 3871 001e C900     		lsls	r1, r1, #3
+ 3872 0020 01F5B471 		add	r1, r1, #360
+ 3873 0024 0144     		add	r1, r1, r0
+ 3874              	.LVL393:
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3875              		.loc 1 1597 5 is_stmt 1 view .LVU1232
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3876              		.loc 1 1597 15 is_stmt 0 view .LVU1233
+ 3877 0026 02EB8202 		add	r2, r2, r2, lsl #2
+ 3878 002a 00EBC202 		add	r2, r0, r2, lsl #3
+ 3879 002e 0020     		movs	r0, #0
+ 3880              	.LVL394:
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3881              		.loc 1 1597 15 view .LVU1234
+ 3882 0030 82F86901 		strb	r0, [r2, #361]
+ 3883              	.L223:
+ARM GAS  /tmp/ccJPteqL.s 			page 126
+
+
+1600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+ 3884              		.loc 1 1600 3 is_stmt 1 view .LVU1235
+1600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   ep->num = ep_addr & EP_ADDR_MSK;
+ 3885              		.loc 1 1600 16 is_stmt 0 view .LVU1236
+ 3886 0034 0022     		movs	r2, #0
+ 3887 0036 8A70     		strb	r2, [r1, #2]
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3888              		.loc 1 1601 3 is_stmt 1 view .LVU1237
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3889              		.loc 1 1601 21 is_stmt 0 view .LVU1238
+ 3890 0038 03F00703 		and	r3, r3, #7
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3891              		.loc 1 1601 11 view .LVU1239
+ 3892 003c 0B70     		strb	r3, [r1]
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_EPClearStall(hpcd->Instance, ep);
+ 3893              		.loc 1 1603 3 is_stmt 1 view .LVU1240
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_EPClearStall(hpcd->Instance, ep);
+ 3894              		.loc 1 1603 3 view .LVU1241
+ 3895 003e 94F8A832 		ldrb	r3, [r4, #680]	@ zero_extendqisi2
+ 3896 0042 012B     		cmp	r3, #1
+ 3897 0044 15D0     		beq	.L225
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_EPClearStall(hpcd->Instance, ep);
+ 3898              		.loc 1 1603 3 discriminator 2 view .LVU1242
+ 3899 0046 0123     		movs	r3, #1
+ 3900 0048 84F8A832 		strb	r3, [r4, #680]
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_EPClearStall(hpcd->Instance, ep);
+ 3901              		.loc 1 1603 3 discriminator 2 view .LVU1243
+1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 3902              		.loc 1 1604 3 discriminator 2 view .LVU1244
+1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   __HAL_UNLOCK(hpcd);
+ 3903              		.loc 1 1604 9 is_stmt 0 discriminator 2 view .LVU1245
+ 3904 004c 2068     		ldr	r0, [r4]
+ 3905 004e FFF7FEFF 		bl	USB_EPClearStall
+ 3906              	.LVL395:
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3907              		.loc 1 1605 3 is_stmt 1 discriminator 2 view .LVU1246
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3908              		.loc 1 1605 3 discriminator 2 view .LVU1247
+ 3909 0052 0020     		movs	r0, #0
+ 3910 0054 84F8A802 		strb	r0, [r4, #680]
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3911              		.loc 1 1605 3 discriminator 2 view .LVU1248
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 3912              		.loc 1 1607 3 discriminator 2 view .LVU1249
+ 3913              	.L221:
+1608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3914              		.loc 1 1608 1 is_stmt 0 view .LVU1250
+ 3915 0058 10BD     		pop	{r4, pc}
+ 3916              	.LVL396:
+ 3917              	.L230:
+1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3918              		.loc 1 1591 5 is_stmt 1 view .LVU1251
+1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3919              		.loc 1 1591 31 is_stmt 0 view .LVU1252
+ 3920 005a 03F00702 		and	r2, r3, #7
+1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****     ep->is_in = 1U;
+ 3921              		.loc 1 1591 8 view .LVU1253
+ARM GAS  /tmp/ccJPteqL.s 			page 127
+
+
+ 3922 005e 0132     		adds	r2, r2, #1
+ 3923 0060 02EB8201 		add	r1, r2, r2, lsl #2
+ 3924 0064 00EBC101 		add	r1, r0, r1, lsl #3
+ 3925              	.LVL397:
+1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3926              		.loc 1 1592 5 is_stmt 1 view .LVU1254
+1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3927              		.loc 1 1592 15 is_stmt 0 view .LVU1255
+ 3928 0068 0120     		movs	r0, #1
+ 3929              	.LVL398:
+1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3930              		.loc 1 1592 15 view .LVU1256
+ 3931 006a 4870     		strb	r0, [r1, #1]
+ 3932 006c E2E7     		b	.L223
+ 3933              	.LVL399:
+ 3934              	.L224:
+ 3935              	.LCFI28:
+ 3936              		.cfi_def_cfa_offset 0
+ 3937              		.cfi_restore 4
+ 3938              		.cfi_restore 14
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   }
+ 3939              		.loc 1 1586 12 view .LVU1257
+ 3940 006e 0120     		movs	r0, #1
+ 3941              	.LVL400:
+1608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3942              		.loc 1 1608 1 view .LVU1258
+ 3943 0070 7047     		bx	lr
+ 3944              	.LVL401:
+ 3945              	.L225:
+ 3946              	.LCFI29:
+ 3947              		.cfi_def_cfa_offset 8
+ 3948              		.cfi_offset 4, -8
+ 3949              		.cfi_offset 14, -4
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   (void)USB_EPClearStall(hpcd->Instance, ep);
+ 3950              		.loc 1 1603 3 view .LVU1259
+ 3951 0072 0220     		movs	r0, #2
+ 3952 0074 F0E7     		b	.L221
+ 3953              		.cfi_endproc
+ 3954              	.LFE356:
+ 3956              		.section	.text.HAL_PCD_EP_Flush,"ax",%progbits
+ 3957              		.align	1
+ 3958              		.global	HAL_PCD_EP_Flush
+ 3959              		.syntax unified
+ 3960              		.thumb
+ 3961              		.thumb_func
+ 3963              	HAL_PCD_EP_Flush:
+ 3964              	.LVL402:
+ 3965              	.LFB357:
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   /* Prevent unused argument(s) compilation warning */
+ 3966              		.loc 1 1617 1 is_stmt 1 view -0
+ 3967              		.cfi_startproc
+ 3968              		@ args = 0, pretend = 0, frame = 0
+ 3969              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3970              		@ link register save eliminated.
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   UNUSED(ep_addr);
+ 3971              		.loc 1 1619 3 view .LVU1261
+1620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ARM GAS  /tmp/ccJPteqL.s 			page 128
+
+
+ 3972              		.loc 1 1620 3 view .LVU1262
+1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 3973              		.loc 1 1622 3 view .LVU1263
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3974              		.loc 1 1623 1 is_stmt 0 view .LVU1264
+ 3975 0000 0020     		movs	r0, #0
+ 3976              	.LVL403:
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 3977              		.loc 1 1623 1 view .LVU1265
+ 3978 0002 7047     		bx	lr
+ 3979              		.cfi_endproc
+ 3980              	.LFE357:
+ 3982              		.section	.text.HAL_PCD_ActivateRemoteWakeup,"ax",%progbits
+ 3983              		.align	1
+ 3984              		.global	HAL_PCD_ActivateRemoteWakeup
+ 3985              		.syntax unified
+ 3986              		.thumb
+ 3987              		.thumb_func
+ 3989              	HAL_PCD_ActivateRemoteWakeup:
+ 3990              	.LVL404:
+ 3991              	.LFB358:
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return (USB_ActivateRemoteWakeup(hpcd->Instance));
+ 3992              		.loc 1 1631 1 is_stmt 1 view -0
+ 3993              		.cfi_startproc
+ 3994              		@ args = 0, pretend = 0, frame = 0
+ 3995              		@ frame_needed = 0, uses_anonymous_args = 0
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return (USB_ActivateRemoteWakeup(hpcd->Instance));
+ 3996              		.loc 1 1631 1 is_stmt 0 view .LVU1267
+ 3997 0000 08B5     		push	{r3, lr}
+ 3998              	.LCFI30:
+ 3999              		.cfi_def_cfa_offset 8
+ 4000              		.cfi_offset 3, -8
+ 4001              		.cfi_offset 14, -4
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 4002              		.loc 1 1632 3 is_stmt 1 view .LVU1268
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 4003              		.loc 1 1632 11 is_stmt 0 view .LVU1269
+ 4004 0002 0068     		ldr	r0, [r0]
+ 4005              	.LVL405:
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 4006              		.loc 1 1632 11 view .LVU1270
+ 4007 0004 FFF7FEFF 		bl	USB_ActivateRemoteWakeup
+ 4008              	.LVL406:
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 4009              		.loc 1 1633 1 view .LVU1271
+ 4010 0008 08BD     		pop	{r3, pc}
+ 4011              		.cfi_endproc
+ 4012              	.LFE358:
+ 4014              		.section	.text.HAL_PCD_DeActivateRemoteWakeup,"ax",%progbits
+ 4015              		.align	1
+ 4016              		.global	HAL_PCD_DeActivateRemoteWakeup
+ 4017              		.syntax unified
+ 4018              		.thumb
+ 4019              		.thumb_func
+ 4021              	HAL_PCD_DeActivateRemoteWakeup:
+ 4022              	.LVL407:
+ 4023              	.LFB359:
+ARM GAS  /tmp/ccJPteqL.s 			page 129
+
+
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return (USB_DeActivateRemoteWakeup(hpcd->Instance));
+ 4024              		.loc 1 1641 1 is_stmt 1 view -0
+ 4025              		.cfi_startproc
+ 4026              		@ args = 0, pretend = 0, frame = 0
+ 4027              		@ frame_needed = 0, uses_anonymous_args = 0
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return (USB_DeActivateRemoteWakeup(hpcd->Instance));
+ 4028              		.loc 1 1641 1 is_stmt 0 view .LVU1273
+ 4029 0000 08B5     		push	{r3, lr}
+ 4030              	.LCFI31:
+ 4031              		.cfi_def_cfa_offset 8
+ 4032              		.cfi_offset 3, -8
+ 4033              		.cfi_offset 14, -4
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 4034              		.loc 1 1642 3 is_stmt 1 view .LVU1274
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 4035              		.loc 1 1642 11 is_stmt 0 view .LVU1275
+ 4036 0002 0068     		ldr	r0, [r0]
+ 4037              	.LVL408:
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 4038              		.loc 1 1642 11 view .LVU1276
+ 4039 0004 FFF7FEFF 		bl	USB_DeActivateRemoteWakeup
+ 4040              	.LVL409:
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 4041              		.loc 1 1643 1 view .LVU1277
+ 4042 0008 08BD     		pop	{r3, pc}
+ 4043              		.cfi_endproc
+ 4044              	.LFE359:
+ 4046              		.section	.text.HAL_PCD_GetState,"ax",%progbits
+ 4047              		.align	1
+ 4048              		.global	HAL_PCD_GetState
+ 4049              		.syntax unified
+ 4050              		.thumb
+ 4051              		.thumb_func
+ 4053              	HAL_PCD_GetState:
+ 4054              	.LVL410:
+ 4055              	.LFB360:
+1670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c ****   return hpcd->State;
+ 4056              		.loc 1 1670 1 is_stmt 1 view -0
+ 4057              		.cfi_startproc
+ 4058              		@ args = 0, pretend = 0, frame = 0
+ 4059              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4060              		@ link register save eliminated.
+1671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 4061              		.loc 1 1671 3 view .LVU1279
+1671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** }
+ 4062              		.loc 1 1671 14 is_stmt 0 view .LVU1280
+ 4063 0000 90F8A902 		ldrb	r0, [r0, #681]	@ zero_extendqisi2
+ 4064              	.LVL411:
+1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c **** 
+ 4065              		.loc 1 1672 1 view .LVU1281
+ 4066 0004 7047     		bx	lr
+ 4067              		.cfi_endproc
+ 4068              	.LFE360:
+ 4070              		.text
+ 4071              	.Letext0:
+ 4072              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 4073              		.file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ARM GAS  /tmp/ccJPteqL.s 			page 130
+
+
+ 4074              		.file 4 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 4075              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h"
+ 4076              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h"
+ 4077              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h"
+ARM GAS  /tmp/ccJPteqL.s 			page 131
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_pcd.c
+     /tmp/ccJPteqL.s:21     .text.HAL_PCD_EP_DB_Receive:00000000 $t
+     /tmp/ccJPteqL.s:26     .text.HAL_PCD_EP_DB_Receive:00000000 HAL_PCD_EP_DB_Receive
+     /tmp/ccJPteqL.s:275    .text.HAL_PCD_MspInit:00000000 $t
+     /tmp/ccJPteqL.s:281    .text.HAL_PCD_MspInit:00000000 HAL_PCD_MspInit
+     /tmp/ccJPteqL.s:296    .text.HAL_PCD_Init:00000000 $t
+     /tmp/ccJPteqL.s:302    .text.HAL_PCD_Init:00000000 HAL_PCD_Init
+     /tmp/ccJPteqL.s:508    .text.HAL_PCD_MspDeInit:00000000 $t
+     /tmp/ccJPteqL.s:514    .text.HAL_PCD_MspDeInit:00000000 HAL_PCD_MspDeInit
+     /tmp/ccJPteqL.s:529    .text.HAL_PCD_DeInit:00000000 $t
+     /tmp/ccJPteqL.s:535    .text.HAL_PCD_DeInit:00000000 HAL_PCD_DeInit
+     /tmp/ccJPteqL.s:597    .text.HAL_PCD_Start:00000000 $t
+     /tmp/ccJPteqL.s:603    .text.HAL_PCD_Start:00000000 HAL_PCD_Start
+     /tmp/ccJPteqL.s:660    .text.HAL_PCD_Stop:00000000 $t
+     /tmp/ccJPteqL.s:666    .text.HAL_PCD_Stop:00000000 HAL_PCD_Stop
+     /tmp/ccJPteqL.s:723    .text.HAL_PCD_DataOutStageCallback:00000000 $t
+     /tmp/ccJPteqL.s:729    .text.HAL_PCD_DataOutStageCallback:00000000 HAL_PCD_DataOutStageCallback
+     /tmp/ccJPteqL.s:745    .text.HAL_PCD_DataInStageCallback:00000000 $t
+     /tmp/ccJPteqL.s:751    .text.HAL_PCD_DataInStageCallback:00000000 HAL_PCD_DataInStageCallback
+     /tmp/ccJPteqL.s:767    .text.HAL_PCD_EP_DB_Transmit:00000000 $t
+     /tmp/ccJPteqL.s:772    .text.HAL_PCD_EP_DB_Transmit:00000000 HAL_PCD_EP_DB_Transmit
+     /tmp/ccJPteqL.s:1707   .text.HAL_PCD_SetupStageCallback:00000000 $t
+     /tmp/ccJPteqL.s:1713   .text.HAL_PCD_SetupStageCallback:00000000 HAL_PCD_SetupStageCallback
+     /tmp/ccJPteqL.s:1728   .text.PCD_EP_ISR_Handler:00000000 $t
+     /tmp/ccJPteqL.s:1733   .text.PCD_EP_ISR_Handler:00000000 PCD_EP_ISR_Handler
+     /tmp/ccJPteqL.s:2623   .text.HAL_PCD_SOFCallback:00000000 $t
+     /tmp/ccJPteqL.s:2629   .text.HAL_PCD_SOFCallback:00000000 HAL_PCD_SOFCallback
+     /tmp/ccJPteqL.s:2644   .text.HAL_PCD_ResetCallback:00000000 $t
+     /tmp/ccJPteqL.s:2650   .text.HAL_PCD_ResetCallback:00000000 HAL_PCD_ResetCallback
+     /tmp/ccJPteqL.s:2665   .text.HAL_PCD_SuspendCallback:00000000 $t
+     /tmp/ccJPteqL.s:2671   .text.HAL_PCD_SuspendCallback:00000000 HAL_PCD_SuspendCallback
+     /tmp/ccJPteqL.s:2686   .text.HAL_PCD_ResumeCallback:00000000 $t
+     /tmp/ccJPteqL.s:2692   .text.HAL_PCD_ResumeCallback:00000000 HAL_PCD_ResumeCallback
+     /tmp/ccJPteqL.s:2707   .text.HAL_PCD_ISOOUTIncompleteCallback:00000000 $t
+     /tmp/ccJPteqL.s:2713   .text.HAL_PCD_ISOOUTIncompleteCallback:00000000 HAL_PCD_ISOOUTIncompleteCallback
+     /tmp/ccJPteqL.s:2729   .text.HAL_PCD_ISOINIncompleteCallback:00000000 $t
+     /tmp/ccJPteqL.s:2735   .text.HAL_PCD_ISOINIncompleteCallback:00000000 HAL_PCD_ISOINIncompleteCallback
+     /tmp/ccJPteqL.s:2751   .text.HAL_PCD_ConnectCallback:00000000 $t
+     /tmp/ccJPteqL.s:2757   .text.HAL_PCD_ConnectCallback:00000000 HAL_PCD_ConnectCallback
+     /tmp/ccJPteqL.s:2772   .text.HAL_PCD_DisconnectCallback:00000000 $t
+     /tmp/ccJPteqL.s:2778   .text.HAL_PCD_DisconnectCallback:00000000 HAL_PCD_DisconnectCallback
+     /tmp/ccJPteqL.s:2793   .text.HAL_PCD_DevConnect:00000000 $t
+     /tmp/ccJPteqL.s:2799   .text.HAL_PCD_DevConnect:00000000 HAL_PCD_DevConnect
+     /tmp/ccJPteqL.s:2852   .text.HAL_PCD_DevDisconnect:00000000 $t
+     /tmp/ccJPteqL.s:2858   .text.HAL_PCD_DevDisconnect:00000000 HAL_PCD_DevDisconnect
+     /tmp/ccJPteqL.s:2911   .text.HAL_PCD_SetAddress:00000000 $t
+     /tmp/ccJPteqL.s:2917   .text.HAL_PCD_SetAddress:00000000 HAL_PCD_SetAddress
+     /tmp/ccJPteqL.s:2973   .text.HAL_PCD_IRQHandler:00000000 $t
+     /tmp/ccJPteqL.s:2979   .text.HAL_PCD_IRQHandler:00000000 HAL_PCD_IRQHandler
+     /tmp/ccJPteqL.s:3277   .text.HAL_PCD_EP_Open:00000000 $t
+     /tmp/ccJPteqL.s:3283   .text.HAL_PCD_EP_Open:00000000 HAL_PCD_EP_Open
+     /tmp/ccJPteqL.s:3410   .text.HAL_PCD_EP_Close:00000000 $t
+     /tmp/ccJPteqL.s:3416   .text.HAL_PCD_EP_Close:00000000 HAL_PCD_EP_Close
+     /tmp/ccJPteqL.s:3511   .text.HAL_PCD_EP_Receive:00000000 $t
+     /tmp/ccJPteqL.s:3517   .text.HAL_PCD_EP_Receive:00000000 HAL_PCD_EP_Receive
+     /tmp/ccJPteqL.s:3591   .text.HAL_PCD_EP_GetRxCount:00000000 $t
+ARM GAS  /tmp/ccJPteqL.s 			page 132
+
+
+     /tmp/ccJPteqL.s:3597   .text.HAL_PCD_EP_GetRxCount:00000000 HAL_PCD_EP_GetRxCount
+     /tmp/ccJPteqL.s:3620   .text.HAL_PCD_EP_Transmit:00000000 $t
+     /tmp/ccJPteqL.s:3626   .text.HAL_PCD_EP_Transmit:00000000 HAL_PCD_EP_Transmit
+     /tmp/ccJPteqL.s:3710   .text.HAL_PCD_EP_SetStall:00000000 $t
+     /tmp/ccJPteqL.s:3716   .text.HAL_PCD_EP_SetStall:00000000 HAL_PCD_EP_SetStall
+     /tmp/ccJPteqL.s:3830   .text.HAL_PCD_EP_ClrStall:00000000 $t
+     /tmp/ccJPteqL.s:3836   .text.HAL_PCD_EP_ClrStall:00000000 HAL_PCD_EP_ClrStall
+     /tmp/ccJPteqL.s:3957   .text.HAL_PCD_EP_Flush:00000000 $t
+     /tmp/ccJPteqL.s:3963   .text.HAL_PCD_EP_Flush:00000000 HAL_PCD_EP_Flush
+     /tmp/ccJPteqL.s:3983   .text.HAL_PCD_ActivateRemoteWakeup:00000000 $t
+     /tmp/ccJPteqL.s:3989   .text.HAL_PCD_ActivateRemoteWakeup:00000000 HAL_PCD_ActivateRemoteWakeup
+     /tmp/ccJPteqL.s:4015   .text.HAL_PCD_DeActivateRemoteWakeup:00000000 $t
+     /tmp/ccJPteqL.s:4021   .text.HAL_PCD_DeActivateRemoteWakeup:00000000 HAL_PCD_DeActivateRemoteWakeup
+     /tmp/ccJPteqL.s:4047   .text.HAL_PCD_GetState:00000000 $t
+     /tmp/ccJPteqL.s:4053   .text.HAL_PCD_GetState:00000000 HAL_PCD_GetState
+
+UNDEFINED SYMBOLS
+USB_ReadPMA
+USB_DisableGlobalInt
+USB_DevInit
+HAL_PCDEx_ActivateLPM
+USB_StopDevice
+USB_EnableGlobalInt
+USB_DevConnect
+USB_DevDisconnect
+USB_WritePMA
+USB_EPStartXfer
+USB_SetDevAddress
+USB_ReadInterrupts
+HAL_PCDEx_LPM_Callback
+USB_ActivateEndpoint
+USB_DeactivateEndpoint
+USB_EPSetStall
+USB_EPClearStall
+USB_ActivateRemoteWakeup
+USB_DeActivateRemoteWakeup
diff --git a/squeow_sw/build/stm32g4xx_hal_pcd.o b/squeow_sw/build/stm32g4xx_hal_pcd.o
new file mode 100644
index 0000000000000000000000000000000000000000..2768787d5b95db2e7c0c03db4eefde89e3b7f9bb
GIT binary patch
literal 51184
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HcmV?d00001

diff --git a/squeow_sw/build/stm32g4xx_hal_pcd_ex.d b/squeow_sw/build/stm32g4xx_hal_pcd_ex.d
new file mode 100644
index 0000000..bad7882
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_pcd_ex.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_pcd_ex.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_pcd_ex.lst b/squeow_sw/build/stm32g4xx_hal_pcd_ex.lst
new file mode 100644
index 0000000..e6f6dc4
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_pcd_ex.lst
@@ -0,0 +1,970 @@
+ARM GAS  /tmp/ccXnw0bT.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_pcd_ex.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c"
+  20              		.section	.text.HAL_PCDEx_PMAConfig,"ax",%progbits
+  21              		.align	1
+  22              		.global	HAL_PCDEx_PMAConfig
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	HAL_PCDEx_PMAConfig:
+  28              	.LVL0:
+  29              	.LFB329:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @file    stm32g4xx_hal_pcd_ex.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @brief   PCD Extended HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *          functionalities of the USB Peripheral Controller:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *           + Extended features functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   ******************************************************************************
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @attention
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * Copyright (c) 2019 STMicroelectronics.
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * All rights reserved.
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * in the root directory of this software component.
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   ******************************************************************************
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /* Includes ------------------------------------------------------------------*/
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #include "stm32g4xx_hal.h"
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @{
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ARM GAS  /tmp/ccXnw0bT.s 			page 2
+
+
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /** @defgroup PCDEx PCDEx
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @brief PCD Extended HAL module driver
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @{
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #ifdef HAL_PCD_MODULE_ENABLED
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #if defined (USB)
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /* Private types -------------------------------------------------------------*/
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /* Private variables ---------------------------------------------------------*/
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /* Private constants ---------------------------------------------------------*/
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /* Private macros ------------------------------------------------------------*/
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /* Private functions ---------------------------------------------------------*/
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /* Exported functions --------------------------------------------------------*/
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @{
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @brief    PCDEx control functions
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** @verbatim
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****  ===============================================================================
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****                  ##### Extended features functions #####
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****  ===============================================================================
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     [..]  This section provides functions allowing to:
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****       (+) Update FIFO configuration
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** @endverbatim
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @{
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /**
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @brief  Configure PMA for EP
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  hpcd  Device instance
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  ep_addr endpoint address
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  ep_kind endpoint Kind
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *                  USB_SNG_BUF: Single Buffer used
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *                  USB_DBL_BUF: Double Buffer used
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *                   this parameter is 16-bit value providing the address
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *                   in PMA allocated to endpoint.
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *                   In case of double buffer endpoint this parameter
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *                   is a 32-bit value providing the endpoint buffer 0 address
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *                   in the LSB part of 32-bit value and endpoint buffer 1 address
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   *                   in the MSB part of 32-bit value.
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @retval HAL status
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****                                        uint16_t ep_kind, uint32_t pmaadress)
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** {
+  30              		.loc 1 82 1 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccXnw0bT.s 			page 3
+
+
+  34              		@ link register save eliminated.
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   PCD_EPTypeDef *ep;
+  35              		.loc 1 83 3 view .LVU1
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* initialize ep structure*/
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   if ((0x80U & ep_addr) == 0x80U)
+  36              		.loc 1 86 3 view .LVU2
+  37              		.loc 1 86 6 is_stmt 0 view .LVU3
+  38 0000 11F0800F 		tst	r1, #128
+  39 0004 0BD0     		beq	.L2
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+  40              		.loc 1 88 5 is_stmt 1 view .LVU4
+  41              		.loc 1 88 31 is_stmt 0 view .LVU5
+  42 0006 01F00701 		and	r1, r1, #7
+  43              	.LVL1:
+  44              		.loc 1 88 8 view .LVU6
+  45 000a 0131     		adds	r1, r1, #1
+  46 000c 01EB8101 		add	r1, r1, r1, lsl #2
+  47 0010 00EBC100 		add	r0, r0, r1, lsl #3
+  48              	.LVL2:
+  49              	.L3:
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   else
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     ep = &hpcd->OUT_ep[ep_addr];
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* Here we check if the endpoint is single or double Buffer*/
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   if (ep_kind == PCD_SNG_BUF)
+  50              		.loc 1 96 3 is_stmt 1 view .LVU7
+  51              		.loc 1 96 6 is_stmt 0 view .LVU8
+  52 0014 52B9     		cbnz	r2, .L4
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     /* Single Buffer */
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     ep->doublebuffer = 0U;
+  53              		.loc 1 99 5 is_stmt 1 view .LVU9
+  54              		.loc 1 99 22 is_stmt 0 view .LVU10
+  55 0016 0273     		strb	r2, [r0, #12]
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     /* Configure the PMA */
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     ep->pmaadress = (uint16_t)pmaadress;
+  56              		.loc 1 101 5 is_stmt 1 view .LVU11
+  57              		.loc 1 101 19 is_stmt 0 view .LVU12
+  58 0018 C380     		strh	r3, [r0, #6]	@ movhi
+  59              	.LVL3:
+  60              	.L5:
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #if (USE_USB_DOUBLE_BUFFER == 1U)
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   else /* USB_DBL_BUF */
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     /* Double Buffer Endpoint */
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     ep->doublebuffer = 1U;
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     /* Configure the PMA */
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+ARM GAS  /tmp/ccXnw0bT.s 			page 4
+
+
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   return HAL_OK;
+  61              		.loc 1 114 3 is_stmt 1 view .LVU13
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** }
+  62              		.loc 1 115 1 is_stmt 0 view .LVU14
+  63 001a 0020     		movs	r0, #0
+  64              	.LVL4:
+  65              		.loc 1 115 1 view .LVU15
+  66 001c 7047     		bx	lr
+  67              	.LVL5:
+  68              	.L2:
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+  69              		.loc 1 92 5 is_stmt 1 view .LVU16
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+  70              		.loc 1 92 8 is_stmt 0 view .LVU17
+  71 001e 01EB8101 		add	r1, r1, r1, lsl #2
+  72              	.LVL6:
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+  73              		.loc 1 92 8 view .LVU18
+  74 0022 C900     		lsls	r1, r1, #3
+  75 0024 01F5B471 		add	r1, r1, #360
+  76 0028 0844     		add	r0, r0, r1
+  77              	.LVL7:
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+  78              		.loc 1 92 8 view .LVU19
+  79 002a F3E7     		b	.L3
+  80              	.L4:
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     /* Configure the PMA */
+  81              		.loc 1 107 5 is_stmt 1 view .LVU20
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     /* Configure the PMA */
+  82              		.loc 1 107 22 is_stmt 0 view .LVU21
+  83 002c 0122     		movs	r2, #1
+  84              	.LVL8:
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     /* Configure the PMA */
+  85              		.loc 1 107 22 view .LVU22
+  86 002e 0273     		strb	r2, [r0, #12]
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
+  87              		.loc 1 109 5 is_stmt 1 view .LVU23
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
+  88              		.loc 1 109 18 is_stmt 0 view .LVU24
+  89 0030 0381     		strh	r3, [r0, #8]	@ movhi
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+  90              		.loc 1 110 5 is_stmt 1 view .LVU25
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+  91              		.loc 1 110 20 is_stmt 0 view .LVU26
+  92 0032 1B0C     		lsrs	r3, r3, #16
+  93              	.LVL9:
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+  94              		.loc 1 110 18 view .LVU27
+  95 0034 4381     		strh	r3, [r0, #10]	@ movhi
+  96 0036 F0E7     		b	.L5
+  97              		.cfi_endproc
+  98              	.LFE329:
+ 100              		.section	.text.HAL_PCDEx_ActivateBCD,"ax",%progbits
+ 101              		.align	1
+ 102              		.global	HAL_PCDEx_ActivateBCD
+ 103              		.syntax unified
+ARM GAS  /tmp/ccXnw0bT.s 			page 5
+
+
+ 104              		.thumb
+ 105              		.thumb_func
+ 107              	HAL_PCDEx_ActivateBCD:
+ 108              	.LVL10:
+ 109              	.LFB330:
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /**
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @brief  Activate BatteryCharging feature.
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  hpcd PCD handle
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @retval HAL status
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** {
+ 110              		.loc 1 123 1 is_stmt 1 view -0
+ 111              		.cfi_startproc
+ 112              		@ args = 0, pretend = 0, frame = 0
+ 113              		@ frame_needed = 0, uses_anonymous_args = 0
+ 114              		@ link register save eliminated.
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USB_TypeDef *USBx = hpcd->Instance;
+ 115              		.loc 1 124 3 view .LVU29
+ 116              		.loc 1 124 16 is_stmt 0 view .LVU30
+ 117 0000 0368     		ldr	r3, [r0]
+ 118              	.LVL11:
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   hpcd->battery_charging_active = 1U;
+ 119              		.loc 1 125 3 is_stmt 1 view .LVU31
+ 120              		.loc 1 125 33 is_stmt 0 view .LVU32
+ 121 0002 0122     		movs	r2, #1
+ 122 0004 C0F8EC22 		str	r2, [r0, #748]
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* Enable BCD feature */
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USBx->BCDR |= USB_BCDR_BCDEN;
+ 123              		.loc 1 128 3 is_stmt 1 view .LVU33
+ 124              		.loc 1 128 7 is_stmt 0 view .LVU34
+ 125 0008 B3F85820 		ldrh	r2, [r3, #88]
+ 126 000c 92B2     		uxth	r2, r2
+ 127              		.loc 1 128 14 view .LVU35
+ 128 000e 42F00102 		orr	r2, r2, #1
+ 129 0012 A3F85820 		strh	r2, [r3, #88]	@ movhi
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* Enable DCD : Data Contact Detect */
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USBx->BCDR &= ~(USB_BCDR_PDEN);
+ 130              		.loc 1 131 3 is_stmt 1 view .LVU36
+ 131              		.loc 1 131 7 is_stmt 0 view .LVU37
+ 132 0016 B3F85820 		ldrh	r2, [r3, #88]
+ 133 001a 92B2     		uxth	r2, r2
+ 134              		.loc 1 131 14 view .LVU38
+ 135 001c 22F00402 		bic	r2, r2, #4
+ 136 0020 92B2     		uxth	r2, r2
+ 137 0022 A3F85820 		strh	r2, [r3, #88]	@ movhi
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USBx->BCDR &= ~(USB_BCDR_SDEN);
+ 138              		.loc 1 132 3 is_stmt 1 view .LVU39
+ 139              		.loc 1 132 7 is_stmt 0 view .LVU40
+ 140 0026 B3F85820 		ldrh	r2, [r3, #88]
+ 141 002a 92B2     		uxth	r2, r2
+ 142              		.loc 1 132 14 view .LVU41
+ 143 002c 22F00802 		bic	r2, r2, #8
+ 144 0030 92B2     		uxth	r2, r2
+ARM GAS  /tmp/ccXnw0bT.s 			page 6
+
+
+ 145 0032 A3F85820 		strh	r2, [r3, #88]	@ movhi
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USBx->BCDR |= USB_BCDR_DCDEN;
+ 146              		.loc 1 133 3 is_stmt 1 view .LVU42
+ 147              		.loc 1 133 7 is_stmt 0 view .LVU43
+ 148 0036 B3F85820 		ldrh	r2, [r3, #88]
+ 149 003a 92B2     		uxth	r2, r2
+ 150              		.loc 1 133 14 view .LVU44
+ 151 003c 42F00202 		orr	r2, r2, #2
+ 152 0040 A3F85820 		strh	r2, [r3, #88]	@ movhi
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   return HAL_OK;
+ 153              		.loc 1 135 3 is_stmt 1 view .LVU45
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** }
+ 154              		.loc 1 136 1 is_stmt 0 view .LVU46
+ 155 0044 0020     		movs	r0, #0
+ 156              	.LVL12:
+ 157              		.loc 1 136 1 view .LVU47
+ 158 0046 7047     		bx	lr
+ 159              		.cfi_endproc
+ 160              	.LFE330:
+ 162              		.section	.text.HAL_PCDEx_DeActivateBCD,"ax",%progbits
+ 163              		.align	1
+ 164              		.global	HAL_PCDEx_DeActivateBCD
+ 165              		.syntax unified
+ 166              		.thumb
+ 167              		.thumb_func
+ 169              	HAL_PCDEx_DeActivateBCD:
+ 170              	.LVL13:
+ 171              	.LFB331:
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /**
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @brief  Deactivate BatteryCharging feature.
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  hpcd PCD handle
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @retval HAL status
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** {
+ 172              		.loc 1 144 1 is_stmt 1 view -0
+ 173              		.cfi_startproc
+ 174              		@ args = 0, pretend = 0, frame = 0
+ 175              		@ frame_needed = 0, uses_anonymous_args = 0
+ 176              		@ link register save eliminated.
+ 177              		.loc 1 144 1 is_stmt 0 view .LVU49
+ 178 0000 0346     		mov	r3, r0
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USB_TypeDef *USBx = hpcd->Instance;
+ 179              		.loc 1 145 3 is_stmt 1 view .LVU50
+ 180              		.loc 1 145 16 is_stmt 0 view .LVU51
+ 181 0002 0268     		ldr	r2, [r0]
+ 182              	.LVL14:
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   hpcd->battery_charging_active = 0U;
+ 183              		.loc 1 146 3 is_stmt 1 view .LVU52
+ 184              		.loc 1 146 33 is_stmt 0 view .LVU53
+ 185 0004 0020     		movs	r0, #0
+ 186              	.LVL15:
+ 187              		.loc 1 146 33 view .LVU54
+ 188 0006 C3F8EC02 		str	r0, [r3, #748]
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ARM GAS  /tmp/ccXnw0bT.s 			page 7
+
+
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* Disable BCD feature */
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USBx->BCDR &= ~(USB_BCDR_BCDEN);
+ 189              		.loc 1 149 3 is_stmt 1 view .LVU55
+ 190              		.loc 1 149 7 is_stmt 0 view .LVU56
+ 191 000a B2F85830 		ldrh	r3, [r2, #88]
+ 192              	.LVL16:
+ 193              		.loc 1 149 7 view .LVU57
+ 194 000e 9BB2     		uxth	r3, r3
+ 195              		.loc 1 149 14 view .LVU58
+ 196 0010 23F00103 		bic	r3, r3, #1
+ 197 0014 9BB2     		uxth	r3, r3
+ 198 0016 A2F85830 		strh	r3, [r2, #88]	@ movhi
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   return HAL_OK;
+ 199              		.loc 1 151 3 is_stmt 1 view .LVU59
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** }
+ 200              		.loc 1 152 1 is_stmt 0 view .LVU60
+ 201 001a 7047     		bx	lr
+ 202              		.cfi_endproc
+ 203              	.LFE331:
+ 205              		.section	.text.HAL_PCDEx_ActivateLPM,"ax",%progbits
+ 206              		.align	1
+ 207              		.global	HAL_PCDEx_ActivateLPM
+ 208              		.syntax unified
+ 209              		.thumb
+ 210              		.thumb_func
+ 212              	HAL_PCDEx_ActivateLPM:
+ 213              	.LVL17:
+ 214              	.LFB333:
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /**
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @brief  Handle BatteryCharging Process.
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  hpcd PCD handle
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @retval HAL status
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** {
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USB_TypeDef *USBx = hpcd->Instance;
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   uint32_t tickstart = HAL_GetTick();
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* Wait Detect flag or a timeout is happen */
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   while ((USBx->BCDR & USB_BCDR_DCDET) == 0U)
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     /* Check for the Timeout */
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     if ((HAL_GetTick() - tickstart) > 1000U)
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     {
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****       hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #else
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****       return;
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     }
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   HAL_Delay(200U);
+ARM GAS  /tmp/ccXnw0bT.s 			page 8
+
+
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* Data Pin Contact ? Check Detect flag */
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #else
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* Primary detection: checks if connected to Standard Downstream Port
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   (without charging capability) */
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USBx->BCDR &= ~(USB_BCDR_DCDEN);
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   HAL_Delay(50U);
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USBx->BCDR |= (USB_BCDR_PDEN);
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   HAL_Delay(50U);
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* If Charger detect ? */
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     /* Start secondary detection to check connection to Charging Downstream
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     Port or Dedicated Charging Port */
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     USBx->BCDR &= ~(USB_BCDR_PDEN);
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     HAL_Delay(50U);
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     USBx->BCDR |= (USB_BCDR_SDEN);
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     HAL_Delay(50U);
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     /* If CDP ? */
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     {
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****       /* Dedicated Downstream Port DCP */
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****       hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #else
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     }
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     else
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     {
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****       /* Charging Downstream Port CDP */
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****       hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #else
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     }
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   else /* NO */
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     /* Standard Downstream Port */
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #else
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   }
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ARM GAS  /tmp/ccXnw0bT.s 			page 9
+
+
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* Battery Charging capability discovery finished Start Enumeration */
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   (void)HAL_PCDEx_DeActivateBCD(hpcd);
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #else
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** }
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /**
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @brief  Activate LPM feature.
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  hpcd PCD handle
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @retval HAL status
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** {
+ 215              		.loc 1 254 1 is_stmt 1 view -0
+ 216              		.cfi_startproc
+ 217              		@ args = 0, pretend = 0, frame = 0
+ 218              		@ frame_needed = 0, uses_anonymous_args = 0
+ 219              		@ link register save eliminated.
+ 220              		.loc 1 254 1 is_stmt 0 view .LVU62
+ 221 0000 0346     		mov	r3, r0
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USB_TypeDef *USBx = hpcd->Instance;
+ 222              		.loc 1 256 3 is_stmt 1 view .LVU63
+ 223              		.loc 1 256 16 is_stmt 0 view .LVU64
+ 224 0002 0268     		ldr	r2, [r0]
+ 225              	.LVL18:
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   hpcd->lpm_active = 1U;
+ 226              		.loc 1 257 3 is_stmt 1 view .LVU65
+ 227              		.loc 1 257 20 is_stmt 0 view .LVU66
+ 228 0004 0121     		movs	r1, #1
+ 229 0006 C0F8E812 		str	r1, [r0, #744]
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   hpcd->LPM_State = LPM_L0;
+ 230              		.loc 1 258 3 is_stmt 1 view .LVU67
+ 231              		.loc 1 258 19 is_stmt 0 view .LVU68
+ 232 000a 0020     		movs	r0, #0
+ 233              	.LVL19:
+ 234              		.loc 1 258 19 view .LVU69
+ 235 000c 83F8E002 		strb	r0, [r3, #736]
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USBx->LPMCSR |= USB_LPMCSR_LMPEN;
+ 236              		.loc 1 260 3 is_stmt 1 view .LVU70
+ 237              		.loc 1 260 7 is_stmt 0 view .LVU71
+ 238 0010 B2F85430 		ldrh	r3, [r2, #84]
+ 239              	.LVL20:
+ 240              		.loc 1 260 7 view .LVU72
+ 241 0014 9BB2     		uxth	r3, r3
+ 242              		.loc 1 260 16 view .LVU73
+ 243 0016 0B43     		orrs	r3, r3, r1
+ 244 0018 A2F85430 		strh	r3, [r2, #84]	@ movhi
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USBx->LPMCSR |= USB_LPMCSR_LPMACK;
+ 245              		.loc 1 261 3 is_stmt 1 view .LVU74
+ 246              		.loc 1 261 7 is_stmt 0 view .LVU75
+ 247 001c B2F85430 		ldrh	r3, [r2, #84]
+ARM GAS  /tmp/ccXnw0bT.s 			page 10
+
+
+ 248 0020 9BB2     		uxth	r3, r3
+ 249              		.loc 1 261 16 view .LVU76
+ 250 0022 43F00203 		orr	r3, r3, #2
+ 251 0026 A2F85430 		strh	r3, [r2, #84]	@ movhi
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   return HAL_OK;
+ 252              		.loc 1 263 3 is_stmt 1 view .LVU77
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** }
+ 253              		.loc 1 264 1 is_stmt 0 view .LVU78
+ 254 002a 7047     		bx	lr
+ 255              		.cfi_endproc
+ 256              	.LFE333:
+ 258              		.section	.text.HAL_PCDEx_DeActivateLPM,"ax",%progbits
+ 259              		.align	1
+ 260              		.global	HAL_PCDEx_DeActivateLPM
+ 261              		.syntax unified
+ 262              		.thumb
+ 263              		.thumb_func
+ 265              	HAL_PCDEx_DeActivateLPM:
+ 266              	.LVL21:
+ 267              	.LFB334:
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /**
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @brief  Deactivate LPM feature.
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  hpcd PCD handle
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @retval HAL status
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** {
+ 268              		.loc 1 272 1 is_stmt 1 view -0
+ 269              		.cfi_startproc
+ 270              		@ args = 0, pretend = 0, frame = 0
+ 271              		@ frame_needed = 0, uses_anonymous_args = 0
+ 272              		@ link register save eliminated.
+ 273              		.loc 1 272 1 is_stmt 0 view .LVU80
+ 274 0000 0346     		mov	r3, r0
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USB_TypeDef *USBx = hpcd->Instance;
+ 275              		.loc 1 273 3 is_stmt 1 view .LVU81
+ 276              		.loc 1 273 16 is_stmt 0 view .LVU82
+ 277 0002 0268     		ldr	r2, [r0]
+ 278              	.LVL22:
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   hpcd->lpm_active = 0U;
+ 279              		.loc 1 275 3 is_stmt 1 view .LVU83
+ 280              		.loc 1 275 20 is_stmt 0 view .LVU84
+ 281 0004 0020     		movs	r0, #0
+ 282              	.LVL23:
+ 283              		.loc 1 275 20 view .LVU85
+ 284 0006 C3F8E802 		str	r0, [r3, #744]
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
+ 285              		.loc 1 277 3 is_stmt 1 view .LVU86
+ 286              		.loc 1 277 7 is_stmt 0 view .LVU87
+ 287 000a B2F85430 		ldrh	r3, [r2, #84]
+ 288              	.LVL24:
+ 289              		.loc 1 277 7 view .LVU88
+ 290 000e 9BB2     		uxth	r3, r3
+ARM GAS  /tmp/ccXnw0bT.s 			page 11
+
+
+ 291              		.loc 1 277 16 view .LVU89
+ 292 0010 23F00103 		bic	r3, r3, #1
+ 293 0014 9BB2     		uxth	r3, r3
+ 294 0016 A2F85430 		strh	r3, [r2, #84]	@ movhi
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
+ 295              		.loc 1 278 3 is_stmt 1 view .LVU90
+ 296              		.loc 1 278 7 is_stmt 0 view .LVU91
+ 297 001a B2F85430 		ldrh	r3, [r2, #84]
+ 298 001e 9BB2     		uxth	r3, r3
+ 299              		.loc 1 278 16 view .LVU92
+ 300 0020 23F00203 		bic	r3, r3, #2
+ 301 0024 9BB2     		uxth	r3, r3
+ 302 0026 A2F85430 		strh	r3, [r2, #84]	@ movhi
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   return HAL_OK;
+ 303              		.loc 1 280 3 is_stmt 1 view .LVU93
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** }
+ 304              		.loc 1 281 1 is_stmt 0 view .LVU94
+ 305 002a 7047     		bx	lr
+ 306              		.cfi_endproc
+ 307              	.LFE334:
+ 309              		.section	.text.HAL_PCDEx_LPM_Callback,"ax",%progbits
+ 310              		.align	1
+ 311              		.weak	HAL_PCDEx_LPM_Callback
+ 312              		.syntax unified
+ 313              		.thumb
+ 314              		.thumb_func
+ 316              	HAL_PCDEx_LPM_Callback:
+ 317              	.LVL25:
+ 318              	.LFB335:
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /**
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @brief  Send LPM message to user layer callback.
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  hpcd PCD handle
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  msg LPM message
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @retval HAL status
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** {
+ 319              		.loc 1 292 1 is_stmt 1 view -0
+ 320              		.cfi_startproc
+ 321              		@ args = 0, pretend = 0, frame = 0
+ 322              		@ frame_needed = 0, uses_anonymous_args = 0
+ 323              		@ link register save eliminated.
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   UNUSED(hpcd);
+ 324              		.loc 1 294 3 view .LVU96
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   UNUSED(msg);
+ 325              		.loc 1 295 3 view .LVU97
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****             the HAL_PCDEx_LPM_Callback could be implemented in the user file
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****    */
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** }
+ 326              		.loc 1 300 1 is_stmt 0 view .LVU98
+ARM GAS  /tmp/ccXnw0bT.s 			page 12
+
+
+ 327 0000 7047     		bx	lr
+ 328              		.cfi_endproc
+ 329              	.LFE335:
+ 331              		.section	.text.HAL_PCDEx_BCD_Callback,"ax",%progbits
+ 332              		.align	1
+ 333              		.weak	HAL_PCDEx_BCD_Callback
+ 334              		.syntax unified
+ 335              		.thumb
+ 336              		.thumb_func
+ 338              	HAL_PCDEx_BCD_Callback:
+ 339              	.LVL26:
+ 340              	.LFB336:
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** /**
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @brief  Send BatteryCharging message to user layer callback.
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  hpcd PCD handle
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @param  msg LPM message
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   * @retval HAL status
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   */
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** {
+ 341              		.loc 1 309 1 is_stmt 1 view -0
+ 342              		.cfi_startproc
+ 343              		@ args = 0, pretend = 0, frame = 0
+ 344              		@ frame_needed = 0, uses_anonymous_args = 0
+ 345              		@ link register save eliminated.
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   UNUSED(hpcd);
+ 346              		.loc 1 311 3 view .LVU100
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   UNUSED(msg);
+ 347              		.loc 1 312 3 view .LVU101
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****             the HAL_PCDEx_BCD_Callback could be implemented in the user file
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****    */
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** }
+ 348              		.loc 1 317 1 is_stmt 0 view .LVU102
+ 349 0000 7047     		bx	lr
+ 350              		.cfi_endproc
+ 351              	.LFE336:
+ 353              		.section	.text.HAL_PCDEx_BCD_VBUSDetect,"ax",%progbits
+ 354              		.align	1
+ 355              		.global	HAL_PCDEx_BCD_VBUSDetect
+ 356              		.syntax unified
+ 357              		.thumb
+ 358              		.thumb_func
+ 360              	HAL_PCDEx_BCD_VBUSDetect:
+ 361              	.LVL27:
+ 362              	.LFB332:
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USB_TypeDef *USBx = hpcd->Instance;
+ 363              		.loc 1 160 1 is_stmt 1 view -0
+ 364              		.cfi_startproc
+ 365              		@ args = 0, pretend = 0, frame = 0
+ 366              		@ frame_needed = 0, uses_anonymous_args = 0
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USB_TypeDef *USBx = hpcd->Instance;
+ 367              		.loc 1 160 1 is_stmt 0 view .LVU104
+ 368 0000 70B5     		push	{r4, r5, r6, lr}
+ARM GAS  /tmp/ccXnw0bT.s 			page 13
+
+
+ 369              	.LCFI0:
+ 370              		.cfi_def_cfa_offset 16
+ 371              		.cfi_offset 4, -16
+ 372              		.cfi_offset 5, -12
+ 373              		.cfi_offset 6, -8
+ 374              		.cfi_offset 14, -4
+ 375 0002 0646     		mov	r6, r0
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   uint32_t tickstart = HAL_GetTick();
+ 376              		.loc 1 161 3 is_stmt 1 view .LVU105
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   uint32_t tickstart = HAL_GetTick();
+ 377              		.loc 1 161 16 is_stmt 0 view .LVU106
+ 378 0004 0468     		ldr	r4, [r0]
+ 379              	.LVL28:
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 380              		.loc 1 162 3 is_stmt 1 view .LVU107
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 381              		.loc 1 162 24 is_stmt 0 view .LVU108
+ 382 0006 FFF7FEFF 		bl	HAL_GetTick
+ 383              	.LVL29:
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 384              		.loc 1 162 24 view .LVU109
+ 385 000a 0546     		mov	r5, r0
+ 386              	.LVL30:
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 387              		.loc 1 165 3 is_stmt 1 view .LVU110
+ 388              	.L13:
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 389              		.loc 1 165 40 view .LVU111
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 390              		.loc 1 165 15 is_stmt 0 view .LVU112
+ 391 000c B4F85830 		ldrh	r3, [r4, #88]
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 392              		.loc 1 165 40 view .LVU113
+ 393 0010 13F0100F 		tst	r3, #16
+ 394 0014 0AD1     		bne	.L21
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     {
+ 395              		.loc 1 168 5 is_stmt 1 view .LVU114
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     {
+ 396              		.loc 1 168 10 is_stmt 0 view .LVU115
+ 397 0016 FFF7FEFF 		bl	HAL_GetTick
+ 398              	.LVL31:
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     {
+ 399              		.loc 1 168 24 view .LVU116
+ 400 001a 401B     		subs	r0, r0, r5
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     {
+ 401              		.loc 1 168 8 view .LVU117
+ 402 001c B0F57A7F 		cmp	r0, #1000
+ 403 0020 F4D9     		bls	.L13
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 404              		.loc 1 173 7 is_stmt 1 view .LVU118
+ 405 0022 FF21     		movs	r1, #255
+ 406 0024 3046     		mov	r0, r6
+ 407 0026 FFF7FEFF 		bl	HAL_PCDEx_BCD_Callback
+ 408              	.LVL32:
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     }
+ 409              		.loc 1 176 7 view .LVU119
+ 410 002a 55E0     		b	.L12
+ARM GAS  /tmp/ccXnw0bT.s 			page 14
+
+
+ 411              	.L21:
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 412              		.loc 1 180 3 view .LVU120
+ 413 002c C820     		movs	r0, #200
+ 414 002e FFF7FEFF 		bl	HAL_Delay
+ 415              	.LVL33:
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 416              		.loc 1 183 3 view .LVU121
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 417              		.loc 1 183 12 is_stmt 0 view .LVU122
+ 418 0032 B4F85830 		ldrh	r3, [r4, #88]
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 419              		.loc 1 183 6 view .LVU123
+ 420 0036 13F0100F 		tst	r3, #16
+ 421 003a 38D1     		bne	.L22
+ 422              	.L16:
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   HAL_Delay(50U);
+ 423              		.loc 1 193 3 is_stmt 1 view .LVU124
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   HAL_Delay(50U);
+ 424              		.loc 1 193 7 is_stmt 0 view .LVU125
+ 425 003c B4F85830 		ldrh	r3, [r4, #88]
+ 426 0040 9BB2     		uxth	r3, r3
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   HAL_Delay(50U);
+ 427              		.loc 1 193 14 view .LVU126
+ 428 0042 23F00203 		bic	r3, r3, #2
+ 429 0046 9BB2     		uxth	r3, r3
+ 430 0048 A4F85830 		strh	r3, [r4, #88]	@ movhi
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   USBx->BCDR |= (USB_BCDR_PDEN);
+ 431              		.loc 1 194 3 is_stmt 1 view .LVU127
+ 432 004c 3220     		movs	r0, #50
+ 433 004e FFF7FEFF 		bl	HAL_Delay
+ 434              	.LVL34:
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   HAL_Delay(50U);
+ 435              		.loc 1 195 3 view .LVU128
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   HAL_Delay(50U);
+ 436              		.loc 1 195 7 is_stmt 0 view .LVU129
+ 437 0052 B4F85830 		ldrh	r3, [r4, #88]
+ 438 0056 9BB2     		uxth	r3, r3
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   HAL_Delay(50U);
+ 439              		.loc 1 195 14 view .LVU130
+ 440 0058 43F00403 		orr	r3, r3, #4
+ 441 005c A4F85830 		strh	r3, [r4, #88]	@ movhi
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 442              		.loc 1 196 3 is_stmt 1 view .LVU131
+ 443 0060 3220     		movs	r0, #50
+ 444 0062 FFF7FEFF 		bl	HAL_Delay
+ 445              	.LVL35:
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 446              		.loc 1 199 3 view .LVU132
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 447              		.loc 1 199 12 is_stmt 0 view .LVU133
+ 448 0066 B4F85830 		ldrh	r3, [r4, #88]
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****   {
+ 449              		.loc 1 199 6 view .LVU134
+ 450 006a 13F0200F 		tst	r3, #32
+ 451 006e 28D0     		beq	.L17
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     HAL_Delay(50U);
+ARM GAS  /tmp/ccXnw0bT.s 			page 15
+
+
+ 452              		.loc 1 203 5 is_stmt 1 view .LVU135
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     HAL_Delay(50U);
+ 453              		.loc 1 203 9 is_stmt 0 view .LVU136
+ 454 0070 B4F85830 		ldrh	r3, [r4, #88]
+ 455 0074 9BB2     		uxth	r3, r3
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     HAL_Delay(50U);
+ 456              		.loc 1 203 16 view .LVU137
+ 457 0076 23F00403 		bic	r3, r3, #4
+ 458 007a 9BB2     		uxth	r3, r3
+ 459 007c A4F85830 		strh	r3, [r4, #88]	@ movhi
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     USBx->BCDR |= (USB_BCDR_SDEN);
+ 460              		.loc 1 204 5 is_stmt 1 view .LVU138
+ 461 0080 3220     		movs	r0, #50
+ 462 0082 FFF7FEFF 		bl	HAL_Delay
+ 463              	.LVL36:
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     HAL_Delay(50U);
+ 464              		.loc 1 205 5 view .LVU139
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     HAL_Delay(50U);
+ 465              		.loc 1 205 9 is_stmt 0 view .LVU140
+ 466 0086 B4F85830 		ldrh	r3, [r4, #88]
+ 467 008a 9BB2     		uxth	r3, r3
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     HAL_Delay(50U);
+ 468              		.loc 1 205 16 view .LVU141
+ 469 008c 43F00803 		orr	r3, r3, #8
+ 470 0090 A4F85830 		strh	r3, [r4, #88]	@ movhi
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 471              		.loc 1 206 5 is_stmt 1 view .LVU142
+ 472 0094 3220     		movs	r0, #50
+ 473 0096 FFF7FEFF 		bl	HAL_Delay
+ 474              	.LVL37:
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     {
+ 475              		.loc 1 209 5 view .LVU143
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     {
+ 476              		.loc 1 209 14 is_stmt 0 view .LVU144
+ 477 009a B4F85830 		ldrh	r3, [r4, #88]
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c ****     {
+ 478              		.loc 1 209 8 view .LVU145
+ 479 009e 13F0400F 		tst	r3, #64
+ 480 00a2 09D0     		beq	.L18
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 481              		.loc 1 215 7 is_stmt 1 view .LVU146
+ 482 00a4 FB21     		movs	r1, #251
+ 483 00a6 3046     		mov	r0, r6
+ 484 00a8 FFF7FEFF 		bl	HAL_PCDEx_BCD_Callback
+ 485              	.LVL38:
+ 486 00ac 0DE0     		b	.L19
+ 487              	.L22:
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 488              		.loc 1 188 5 view .LVU147
+ 489 00ae FE21     		movs	r1, #254
+ 490 00b0 3046     		mov	r0, r6
+ 491 00b2 FFF7FEFF 		bl	HAL_PCDEx_BCD_Callback
+ 492              	.LVL39:
+ 493 00b6 C1E7     		b	.L16
+ 494              	.L18:
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 495              		.loc 1 224 7 view .LVU148
+ARM GAS  /tmp/ccXnw0bT.s 			page 16
+
+
+ 496 00b8 FC21     		movs	r1, #252
+ 497 00ba 3046     		mov	r0, r6
+ 498 00bc FFF7FEFF 		bl	HAL_PCDEx_BCD_Callback
+ 499              	.LVL40:
+ 500 00c0 03E0     		b	.L19
+ 501              	.L17:
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 502              		.loc 1 234 5 view .LVU149
+ 503 00c2 FD21     		movs	r1, #253
+ 504 00c4 3046     		mov	r0, r6
+ 505 00c6 FFF7FEFF 		bl	HAL_PCDEx_BCD_Callback
+ 506              	.LVL41:
+ 507              	.L19:
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 508              		.loc 1 239 3 view .LVU150
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 509              		.loc 1 239 9 is_stmt 0 view .LVU151
+ 510 00ca 3046     		mov	r0, r6
+ 511 00cc FFF7FEFF 		bl	HAL_PCDEx_DeActivateBCD
+ 512              	.LVL42:
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 513              		.loc 1 243 3 is_stmt 1 view .LVU152
+ 514 00d0 0021     		movs	r1, #0
+ 515 00d2 3046     		mov	r0, r6
+ 516 00d4 FFF7FEFF 		bl	HAL_PCDEx_BCD_Callback
+ 517              	.LVL43:
+ 518              	.L12:
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 519              		.loc 1 245 1 is_stmt 0 view .LVU153
+ 520 00d8 70BD     		pop	{r4, r5, r6, pc}
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c **** 
+ 521              		.loc 1 245 1 view .LVU154
+ 522              		.cfi_endproc
+ 523              	.LFE332:
+ 525              		.text
+ 526              	.Letext0:
+ 527              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 528              		.file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 529              		.file 4 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 530              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h"
+ 531              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h"
+ 532              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ARM GAS  /tmp/ccXnw0bT.s 			page 17
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_pcd_ex.c
+     /tmp/ccXnw0bT.s:21     .text.HAL_PCDEx_PMAConfig:00000000 $t
+     /tmp/ccXnw0bT.s:27     .text.HAL_PCDEx_PMAConfig:00000000 HAL_PCDEx_PMAConfig
+     /tmp/ccXnw0bT.s:101    .text.HAL_PCDEx_ActivateBCD:00000000 $t
+     /tmp/ccXnw0bT.s:107    .text.HAL_PCDEx_ActivateBCD:00000000 HAL_PCDEx_ActivateBCD
+     /tmp/ccXnw0bT.s:163    .text.HAL_PCDEx_DeActivateBCD:00000000 $t
+     /tmp/ccXnw0bT.s:169    .text.HAL_PCDEx_DeActivateBCD:00000000 HAL_PCDEx_DeActivateBCD
+     /tmp/ccXnw0bT.s:206    .text.HAL_PCDEx_ActivateLPM:00000000 $t
+     /tmp/ccXnw0bT.s:212    .text.HAL_PCDEx_ActivateLPM:00000000 HAL_PCDEx_ActivateLPM
+     /tmp/ccXnw0bT.s:259    .text.HAL_PCDEx_DeActivateLPM:00000000 $t
+     /tmp/ccXnw0bT.s:265    .text.HAL_PCDEx_DeActivateLPM:00000000 HAL_PCDEx_DeActivateLPM
+     /tmp/ccXnw0bT.s:310    .text.HAL_PCDEx_LPM_Callback:00000000 $t
+     /tmp/ccXnw0bT.s:316    .text.HAL_PCDEx_LPM_Callback:00000000 HAL_PCDEx_LPM_Callback
+     /tmp/ccXnw0bT.s:332    .text.HAL_PCDEx_BCD_Callback:00000000 $t
+     /tmp/ccXnw0bT.s:338    .text.HAL_PCDEx_BCD_Callback:00000000 HAL_PCDEx_BCD_Callback
+     /tmp/ccXnw0bT.s:354    .text.HAL_PCDEx_BCD_VBUSDetect:00000000 $t
+     /tmp/ccXnw0bT.s:360    .text.HAL_PCDEx_BCD_VBUSDetect:00000000 HAL_PCDEx_BCD_VBUSDetect
+
+UNDEFINED SYMBOLS
+HAL_GetTick
+HAL_Delay
diff --git a/squeow_sw/build/stm32g4xx_hal_pcd_ex.o b/squeow_sw/build/stm32g4xx_hal_pcd_ex.o
new file mode 100644
index 0000000000000000000000000000000000000000..bee0fab1fccdb40fd2f21eae18cb908e329c2a00
GIT binary patch
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z+<9f}U0r1FL$G%cc4)8GWpAd)-bOfk+&l!(Gxm~2_CiRit&r0mUjK9P@qEBG+*epm
zVGkU~I&TVPyzVU0yAFo<44Pu}?h`%3zYBWIaZ@-hEO$fCJs;O2zJuU1zGb+~_<az1
z=pIu}mzB#4*ADt+A-bkr?SUTuQVoFr114*a^Gu(v;Zo0skTc+!V(ej>3iOU6zK<Ir
HWTyJx6<u4c

literal 0
HcmV?d00001

diff --git a/squeow_sw/build/stm32g4xx_hal_pwr.d b/squeow_sw/build/stm32g4xx_hal_pwr.d
new file mode 100644
index 0000000..b924eb8
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_pwr.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_pwr.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_pwr.lst b/squeow_sw/build/stm32g4xx_hal_pwr.lst
new file mode 100644
index 0000000..97cd986
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_pwr.lst
@@ -0,0 +1,1406 @@
+ARM GAS  /tmp/cchsYltI.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_pwr.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c"
+  20              		.section	.text.HAL_PWR_DeInit,"ax",%progbits
+  21              		.align	1
+  22              		.global	HAL_PWR_DeInit
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	HAL_PWR_DeInit:
+  28              	.LFB329:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @file    stm32g4xx_hal_pwr.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief   PWR HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *          functionalities of the Power Controller (PWR) peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *           + Initialization/de-initialization functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *           + Peripheral Control functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   ******************************************************************************
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @attention
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * Copyright (c) 2019 STMicroelectronics.
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * All rights reserved.
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * in the root directory of this software component.
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   ******************************************************************************
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #include "stm32g4xx_hal.h"
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @{
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ARM GAS  /tmp/cchsYltI.s 			page 2
+
+
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR PWR
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief PWR HAL module driver
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @{
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_Private_Defines PWR Private Defines
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @{
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @{
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #define PVD_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVD
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #define PVD_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVD thresh
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #define PVD_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVD trig
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #define PVD_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVD tri
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @}
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @}
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Exported functions --------------------------------------------------------*/
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @{
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *  @brief    Initialization and de-initialization functions
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** @verbatim
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****  ===============================================================================
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****               ##### Initialization and de-initialization functions #####
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****  ===============================================================================
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     [..]
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** @endverbatim
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @{
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ARM GAS  /tmp/cchsYltI.s 			page 3
+
+
+  29              		.loc 1 87 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   __HAL_RCC_PWR_FORCE_RESET();
+  34              		.loc 1 88 3 view .LVU1
+  35 0000 044B     		ldr	r3, .L2
+  36 0002 9A6B     		ldr	r2, [r3, #56]
+  37 0004 42F08052 		orr	r2, r2, #268435456
+  38 0008 9A63     		str	r2, [r3, #56]
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   __HAL_RCC_PWR_RELEASE_RESET();
+  39              		.loc 1 89 3 view .LVU2
+  40 000a 9A6B     		ldr	r2, [r3, #56]
+  41 000c 22F08052 		bic	r2, r2, #268435456
+  42 0010 9A63     		str	r2, [r3, #56]
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+  43              		.loc 1 90 1 is_stmt 0 view .LVU3
+  44 0012 7047     		bx	lr
+  45              	.L3:
+  46              		.align	2
+  47              	.L2:
+  48 0014 00100240 		.word	1073876992
+  49              		.cfi_endproc
+  50              	.LFE329:
+  52              		.section	.text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
+  53              		.align	1
+  54              		.global	HAL_PWR_EnableBkUpAccess
+  55              		.syntax unified
+  56              		.thumb
+  57              		.thumb_func
+  59              	HAL_PWR_EnableBkUpAccess:
+  60              	.LFB330:
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Enable access to the backup domain
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        (RTC registers, RTC backup data registers).
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  After reset, the backup domain is protected against
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        possible unwanted write accesses.
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        In order to set or modify the RTC clock, the backup domain access must be
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        disabled.
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        back-up domain.
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+  61              		.loc 1 105 1 is_stmt 1 view -0
+  62              		.cfi_startproc
+  63              		@ args = 0, pretend = 0, frame = 0
+  64              		@ frame_needed = 0, uses_anonymous_args = 0
+  65              		@ link register save eliminated.
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   SET_BIT(PWR->CR1, PWR_CR1_DBP);
+  66              		.loc 1 106 3 view .LVU5
+  67 0000 024A     		ldr	r2, .L5
+  68 0002 1368     		ldr	r3, [r2]
+ARM GAS  /tmp/cchsYltI.s 			page 4
+
+
+  69 0004 43F48073 		orr	r3, r3, #256
+  70 0008 1360     		str	r3, [r2]
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+  71              		.loc 1 107 1 is_stmt 0 view .LVU6
+  72 000a 7047     		bx	lr
+  73              	.L6:
+  74              		.align	2
+  75              	.L5:
+  76 000c 00700040 		.word	1073770496
+  77              		.cfi_endproc
+  78              	.LFE330:
+  80              		.section	.text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
+  81              		.align	1
+  82              		.global	HAL_PWR_DisableBkUpAccess
+  83              		.syntax unified
+  84              		.thumb
+  85              		.thumb_func
+  87              	HAL_PWR_DisableBkUpAccess:
+  88              	.LFB331:
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Disable access to the backup domain
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        (RTC registers, RTC backup data registers).
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+  89              		.loc 1 115 1 is_stmt 1 view -0
+  90              		.cfi_startproc
+  91              		@ args = 0, pretend = 0, frame = 0
+  92              		@ frame_needed = 0, uses_anonymous_args = 0
+  93              		@ link register save eliminated.
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+  94              		.loc 1 116 3 view .LVU8
+  95 0000 024A     		ldr	r2, .L8
+  96 0002 1368     		ldr	r3, [r2]
+  97 0004 23F48073 		bic	r3, r3, #256
+  98 0008 1360     		str	r3, [r2]
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+  99              		.loc 1 117 1 is_stmt 0 view .LVU9
+ 100 000a 7047     		bx	lr
+ 101              	.L9:
+ 102              		.align	2
+ 103              	.L8:
+ 104 000c 00700040 		.word	1073770496
+ 105              		.cfi_endproc
+ 106              	.LFE331:
+ 108              		.section	.text.HAL_PWR_ConfigPVD,"ax",%progbits
+ 109              		.align	1
+ 110              		.global	HAL_PWR_ConfigPVD
+ 111              		.syntax unified
+ 112              		.thumb
+ 113              		.thumb_func
+ 115              	HAL_PWR_ConfigPVD:
+ 116              	.LVL0:
+ 117              	.LFB332:
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ARM GAS  /tmp/cchsYltI.s 			page 5
+
+
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @}
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *  @brief Low Power modes configuration functions
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** @verbatim
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****  ===============================================================================
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****                  ##### Peripheral Control functions #####
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****  ===============================================================================
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****      [..]
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****      *** PVD configuration ***
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     =========================
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     [..]
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) The PVD is used to monitor the VDD power supply by comparing it to a
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           than the PVD threshold. This event is internally connected to the EXTI
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           line16 and can generate an interrupt if enabled. This is done through
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           __HAL_PVD_EXTI_ENABLE_IT() macro.
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) The PVD is stopped in Standby mode.
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     *** WakeUp pin configuration ***
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     ================================
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     [..]
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           The polarity of these pins can be set to configure event detection on high
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           level (rising edge) or low level (falling edge).
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     *** Low Power modes configuration ***
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     =====================================
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     [..]
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       The devices feature 8 low-power modes:
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regul
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulato
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator of
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power reg
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserv
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****    *** Low-power run mode ***
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****    ==========================
+ARM GAS  /tmp/cchsYltI.s 			page 6
+
+
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     [..]
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Entry: (from main run mode)
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the syst
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Exit:
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMod
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****              then can the system clock frequency be increased above 2 MHz.
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****    *** Sleep mode / Low-power sleep mode ***
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****    =========================================
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     [..]
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Entry:
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           in specifying whether or not the regulator is forced to low-power mode and if exit is int
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           In the latter case, the system clock frequency must have been decreased below 2 MHz befor
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) WFI Exit:
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****              controller (NVIC) or any wake-up event.
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) WFE Exit:
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         (++) Any wake-up event such as an EXTI line configured in event mode.
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****          [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****              the MCU is in Low-power Run mode.
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****    *** Stop 0, Stop 1 modes ***
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****    ===============================
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     [..]
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Entry:
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           The Stop 0, Stop 1 modes are entered through the following API's:
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or fo
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) PWR_MAINREGULATOR_ON
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) PWR_LOWPOWERREGULATOR_ON
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) WFI Exit:
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****                when programmed in wakeup mode.
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) WFE Exit:
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) Any EXTI Line (Internal or External) configured in Event mode.
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****        [..]
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run m
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           depending on the LPR bit setting.
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****    *** Standby mode ***
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****    ====================
+ARM GAS  /tmp/cchsYltI.s 			page 7
+
+
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****      [..]
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       The Standby mode offers two options:
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low 
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC b
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         and Standby circuitry.
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disa
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         SRAM and register contents are lost except for the RTC registers, RTC backup registers
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         and Standby circuitry.
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (++) Entry:
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****                 SRAM1 and register contents are lost except for registers in the Backup domain and
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****                 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****                 To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetentio
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****                 to set RRS bit.
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (++) Exit:
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****                 external reset in NRST pin, IWDG reset.
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       [..]    After waking up from Standby mode, program execution restarts in the same way as afte
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     *** Shutdown mode ***
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****    ======================
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****      [..]
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       In Shutdown mode,
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         SRAM and registers contents are lost except for backup domain registers.
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Entry:
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) Exit:
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****           (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****                external reset in NRST pin.
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****          [..] After waking up from Shutdown mode, program execution restarts in the same way as aft
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****    *** Auto-wakeup (AWU) from low-power mode ***
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****    =============================================
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     [..]
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       Wakeup event, a tamper event or a time-stamp event, without depending on
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       an external interrupt (Auto-wakeup mode).
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****              is necessary to configure the RTC to detect the tamper or time stamp event using the
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****              HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ARM GAS  /tmp/cchsYltI.s 			page 8
+
+
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****         (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****               configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** @endverbatim
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @{
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        configuration information.
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note Refer to the electrical characteristics of your device datasheet for
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *         more details about the voltage thresholds corresponding to each
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *         detection level.
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ 118              		.loc 1 309 1 is_stmt 1 view -0
+ 119              		.cfi_startproc
+ 120              		@ args = 0, pretend = 0, frame = 0
+ 121              		@ frame_needed = 0, uses_anonymous_args = 0
+ 122              		@ link register save eliminated.
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Check the parameters */
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+ 123              		.loc 1 311 3 view .LVU11
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+ 124              		.loc 1 312 3 view .LVU12
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Set PLS bits according to PVDLevel value */
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
+ 125              		.loc 1 315 3 view .LVU13
+ 126 0000 1E4A     		ldr	r2, .L15
+ 127 0002 5368     		ldr	r3, [r2, #4]
+ 128 0004 23F00E03 		bic	r3, r3, #14
+ 129 0008 0168     		ldr	r1, [r0]
+ 130 000a 0B43     		orrs	r3, r3, r1
+ 131 000c 5360     		str	r3, [r2, #4]
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+ 132              		.loc 1 318 3 view .LVU14
+ 133 000e 1C4B     		ldr	r3, .L15+4
+ 134 0010 5A68     		ldr	r2, [r3, #4]
+ 135 0012 22F48032 		bic	r2, r2, #65536
+ 136 0016 5A60     		str	r2, [r3, #4]
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   __HAL_PWR_PVD_EXTI_DISABLE_IT();
+ 137              		.loc 1 319 3 view .LVU15
+ 138 0018 1A68     		ldr	r2, [r3]
+ 139 001a 22F48032 		bic	r2, r2, #65536
+ 140 001e 1A60     		str	r2, [r3]
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+ 141              		.loc 1 320 3 view .LVU16
+ 142 0020 DA68     		ldr	r2, [r3, #12]
+ 143 0022 22F48032 		bic	r2, r2, #65536
+ARM GAS  /tmp/cchsYltI.s 			page 9
+
+
+ 144 0026 DA60     		str	r2, [r3, #12]
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+ 145              		.loc 1 321 3 view .LVU17
+ 146 0028 9A68     		ldr	r2, [r3, #8]
+ 147 002a 22F48032 		bic	r2, r2, #65536
+ 148 002e 9A60     		str	r2, [r3, #8]
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Configure interrupt mode */
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+ 149              		.loc 1 324 3 view .LVU18
+ 150              		.loc 1 324 17 is_stmt 0 view .LVU19
+ 151 0030 4368     		ldr	r3, [r0, #4]
+ 152              		.loc 1 324 5 view .LVU20
+ 153 0032 13F4803F 		tst	r3, #65536
+ 154 0036 04D0     		beq	.L11
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   {
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     __HAL_PWR_PVD_EXTI_ENABLE_IT();
+ 155              		.loc 1 326 5 is_stmt 1 view .LVU21
+ 156 0038 114A     		ldr	r2, .L15+4
+ 157 003a 1368     		ldr	r3, [r2]
+ 158 003c 43F48033 		orr	r3, r3, #65536
+ 159 0040 1360     		str	r3, [r2]
+ 160              	.L11:
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Configure event mode */
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+ 161              		.loc 1 330 3 view .LVU22
+ 162              		.loc 1 330 17 is_stmt 0 view .LVU23
+ 163 0042 4368     		ldr	r3, [r0, #4]
+ 164              		.loc 1 330 5 view .LVU24
+ 165 0044 13F4003F 		tst	r3, #131072
+ 166 0048 04D0     		beq	.L12
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   {
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+ 167              		.loc 1 332 5 is_stmt 1 view .LVU25
+ 168 004a 0D4A     		ldr	r2, .L15+4
+ 169 004c 5368     		ldr	r3, [r2, #4]
+ 170 004e 43F48033 		orr	r3, r3, #65536
+ 171 0052 5360     		str	r3, [r2, #4]
+ 172              	.L12:
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Configure the edge */
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+ 173              		.loc 1 336 3 view .LVU26
+ 174              		.loc 1 336 17 is_stmt 0 view .LVU27
+ 175 0054 4368     		ldr	r3, [r0, #4]
+ 176              		.loc 1 336 5 view .LVU28
+ 177 0056 13F0010F 		tst	r3, #1
+ 178 005a 04D0     		beq	.L13
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   {
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+ 179              		.loc 1 338 5 is_stmt 1 view .LVU29
+ 180 005c 084A     		ldr	r2, .L15+4
+ 181 005e 9368     		ldr	r3, [r2, #8]
+ 182 0060 43F48033 		orr	r3, r3, #65536
+ARM GAS  /tmp/cchsYltI.s 			page 10
+
+
+ 183 0064 9360     		str	r3, [r2, #8]
+ 184              	.L13:
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+ 185              		.loc 1 341 3 view .LVU30
+ 186              		.loc 1 341 17 is_stmt 0 view .LVU31
+ 187 0066 4368     		ldr	r3, [r0, #4]
+ 188              		.loc 1 341 5 view .LVU32
+ 189 0068 13F0020F 		tst	r3, #2
+ 190 006c 04D0     		beq	.L14
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   {
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+ 191              		.loc 1 343 5 is_stmt 1 view .LVU33
+ 192 006e 044A     		ldr	r2, .L15+4
+ 193 0070 D368     		ldr	r3, [r2, #12]
+ 194 0072 43F48033 		orr	r3, r3, #65536
+ 195 0076 D360     		str	r3, [r2, #12]
+ 196              	.L14:
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   return HAL_OK;
+ 197              		.loc 1 346 3 view .LVU34
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 198              		.loc 1 347 1 is_stmt 0 view .LVU35
+ 199 0078 0020     		movs	r0, #0
+ 200              	.LVL1:
+ 201              		.loc 1 347 1 view .LVU36
+ 202 007a 7047     		bx	lr
+ 203              	.L16:
+ 204              		.align	2
+ 205              	.L15:
+ 206 007c 00700040 		.word	1073770496
+ 207 0080 00040140 		.word	1073808384
+ 208              		.cfi_endproc
+ 209              	.LFE332:
+ 211              		.section	.text.HAL_PWR_EnablePVD,"ax",%progbits
+ 212              		.align	1
+ 213              		.global	HAL_PWR_EnablePVD
+ 214              		.syntax unified
+ 215              		.thumb
+ 216              		.thumb_func
+ 218              	HAL_PWR_EnablePVD:
+ 219              	.LFB333:
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Enable the Power Voltage Detector (PVD).
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void)
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ 220              		.loc 1 355 1 is_stmt 1 view -0
+ 221              		.cfi_startproc
+ 222              		@ args = 0, pretend = 0, frame = 0
+ 223              		@ frame_needed = 0, uses_anonymous_args = 0
+ 224              		@ link register save eliminated.
+ARM GAS  /tmp/cchsYltI.s 			page 11
+
+
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   SET_BIT(PWR->CR2, PWR_CR2_PVDE);
+ 225              		.loc 1 356 3 view .LVU38
+ 226 0000 024A     		ldr	r2, .L18
+ 227 0002 5368     		ldr	r3, [r2, #4]
+ 228 0004 43F00103 		orr	r3, r3, #1
+ 229 0008 5360     		str	r3, [r2, #4]
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 230              		.loc 1 357 1 is_stmt 0 view .LVU39
+ 231 000a 7047     		bx	lr
+ 232              	.L19:
+ 233              		.align	2
+ 234              	.L18:
+ 235 000c 00700040 		.word	1073770496
+ 236              		.cfi_endproc
+ 237              	.LFE333:
+ 239              		.section	.text.HAL_PWR_DisablePVD,"ax",%progbits
+ 240              		.align	1
+ 241              		.global	HAL_PWR_DisablePVD
+ 242              		.syntax unified
+ 243              		.thumb
+ 244              		.thumb_func
+ 246              	HAL_PWR_DisablePVD:
+ 247              	.LFB334:
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Disable the Power Voltage Detector (PVD).
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void)
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ 248              		.loc 1 364 1 is_stmt 1 view -0
+ 249              		.cfi_startproc
+ 250              		@ args = 0, pretend = 0, frame = 0
+ 251              		@ frame_needed = 0, uses_anonymous_args = 0
+ 252              		@ link register save eliminated.
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
+ 253              		.loc 1 365 3 view .LVU41
+ 254 0000 024A     		ldr	r2, .L21
+ 255 0002 5368     		ldr	r3, [r2, #4]
+ 256 0004 23F00103 		bic	r3, r3, #1
+ 257 0008 5360     		str	r3, [r2, #4]
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 258              		.loc 1 366 1 is_stmt 0 view .LVU42
+ 259 000a 7047     		bx	lr
+ 260              	.L22:
+ 261              		.align	2
+ 262              	.L21:
+ 263 000c 00700040 		.word	1073770496
+ 264              		.cfi_endproc
+ 265              	.LFE334:
+ 267              		.section	.text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
+ 268              		.align	1
+ 269              		.global	HAL_PWR_EnableWakeUpPin
+ 270              		.syntax unified
+ 271              		.thumb
+ 272              		.thumb_func
+ 274              	HAL_PWR_EnableWakeUpPin:
+ARM GAS  /tmp/cchsYltI.s 			page 12
+
+
+ 275              	.LVL2:
+ 276              	.LFB335:
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Enable the WakeUp PINx functionality.
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *         This parameter can be one of the following legacy values which set the default polarity
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *         i.e. detection on high level (rising edge):
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAK
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *         or one of the following value where the user can explicitly specify the enabled pin and
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *         the chosen polarity:
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ 277              		.loc 1 389 1 is_stmt 1 view -0
+ 278              		.cfi_startproc
+ 279              		@ args = 0, pretend = 0, frame = 0
+ 280              		@ frame_needed = 0, uses_anonymous_args = 0
+ 281              		@ link register save eliminated.
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
+ 282              		.loc 1 390 3 view .LVU44
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Specifies the Wake-Up pin polarity for the event detection
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     (rising or falling edge) */
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_S
+ 283              		.loc 1 394 3 view .LVU45
+ 284 0000 064A     		ldr	r2, .L24
+ 285 0002 D368     		ldr	r3, [r2, #12]
+ 286 0004 00F01F01 		and	r1, r0, #31
+ 287 0008 23EA0103 		bic	r3, r3, r1
+ 288 000c 43EA5010 		orr	r0, r3, r0, lsr #5
+ 289              	.LVL3:
+ 290              		.loc 1 394 3 is_stmt 0 view .LVU46
+ 291 0010 D060     		str	r0, [r2, #12]
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Enable wake-up pin */
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
+ 292              		.loc 1 397 3 is_stmt 1 view .LVU47
+ 293 0012 9368     		ldr	r3, [r2, #8]
+ 294 0014 1943     		orrs	r1, r1, r3
+ 295 0016 9160     		str	r1, [r2, #8]
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 296              		.loc 1 400 1 is_stmt 0 view .LVU48
+ 297 0018 7047     		bx	lr
+ARM GAS  /tmp/cchsYltI.s 			page 13
+
+
+ 298              	.L25:
+ 299 001a 00BF     		.align	2
+ 300              	.L24:
+ 301 001c 00700040 		.word	1073770496
+ 302              		.cfi_endproc
+ 303              	.LFE335:
+ 305              		.section	.text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
+ 306              		.align	1
+ 307              		.global	HAL_PWR_DisableWakeUpPin
+ 308              		.syntax unified
+ 309              		.thumb
+ 310              		.thumb_func
+ 312              	HAL_PWR_DisableWakeUpPin:
+ 313              	.LVL4:
+ 314              	.LFB336:
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Disable the WakeUp PINx functionality.
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *         This parameter can be one of the following values:
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAK
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ 315              		.loc 1 410 1 is_stmt 1 view -0
+ 316              		.cfi_startproc
+ 317              		@ args = 0, pretend = 0, frame = 0
+ 318              		@ frame_needed = 0, uses_anonymous_args = 0
+ 319              		@ link register save eliminated.
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+ 320              		.loc 1 411 3 view .LVU50
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
+ 321              		.loc 1 413 3 view .LVU51
+ 322 0000 034A     		ldr	r2, .L27
+ 323 0002 9368     		ldr	r3, [r2, #8]
+ 324 0004 00F01F00 		and	r0, r0, #31
+ 325              	.LVL5:
+ 326              		.loc 1 413 3 is_stmt 0 view .LVU52
+ 327 0008 23EA0003 		bic	r3, r3, r0
+ 328 000c 9360     		str	r3, [r2, #8]
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 329              		.loc 1 414 1 view .LVU53
+ 330 000e 7047     		bx	lr
+ 331              	.L28:
+ 332              		.align	2
+ 333              	.L27:
+ 334 0010 00700040 		.word	1073770496
+ 335              		.cfi_endproc
+ 336              	.LFE336:
+ 338              		.section	.text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
+ 339              		.align	1
+ 340              		.global	HAL_PWR_EnterSLEEPMode
+ 341              		.syntax unified
+ 342              		.thumb
+ 343              		.thumb_func
+ARM GAS  /tmp/cchsYltI.s 			page 14
+
+
+ 345              	HAL_PWR_EnterSLEEPMode:
+ 346              	.LVL6:
+ 347              	.LFB337:
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Enter Sleep or Low-power Sleep mode.
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *          This parameter can be one of the following values:
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *            @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *            @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        Additionally, the clock frequency must be reduced below 2 MHz.
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        be done before calling HAL_PWR_EnterSLEEPMode() API.
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *           This parameter can be one of the following values:
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *            @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instructio
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *            @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instructio
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  When WFI entry is used, tick interrupt have to be disabled if not desired as
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        the interrupt wake up source.
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ 348              		.loc 1 442 1 is_stmt 1 view -0
+ 349              		.cfi_startproc
+ 350              		@ args = 0, pretend = 0, frame = 0
+ 351              		@ frame_needed = 0, uses_anonymous_args = 0
+ 352              		.loc 1 442 1 is_stmt 0 view .LVU55
+ 353 0000 10B5     		push	{r4, lr}
+ 354              	.LCFI0:
+ 355              		.cfi_def_cfa_offset 8
+ 356              		.cfi_offset 4, -8
+ 357              		.cfi_offset 14, -4
+ 358 0002 0C46     		mov	r4, r1
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Check the parameters */
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   assert_param(IS_PWR_REGULATOR(Regulator));
+ 359              		.loc 1 444 3 is_stmt 1 view .LVU56
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+ 360              		.loc 1 445 3 view .LVU57
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Set Regulator parameter */
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   if (Regulator == PWR_MAINREGULATOR_ON)
+ 361              		.loc 1 448 3 view .LVU58
+ 362              		.loc 1 448 6 is_stmt 0 view .LVU59
+ 363 0004 90B9     		cbnz	r0, .L30
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   {
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     /* If in low-power run mode at this point, exit it */
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
+ 364              		.loc 1 451 5 is_stmt 1 view .LVU60
+ARM GAS  /tmp/cchsYltI.s 			page 15
+
+
+ 365              		.loc 1 451 9 is_stmt 0 view .LVU61
+ 366 0006 0E4B     		ldr	r3, .L37
+ 367 0008 5B69     		ldr	r3, [r3, #20]
+ 368              		.loc 1 451 8 view .LVU62
+ 369 000a 13F4007F 		tst	r3, #512
+ 370 000e 0AD1     		bne	.L35
+ 371              	.LVL7:
+ 372              	.L31:
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     {
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       (void)HAL_PWREx_DisableLowPowerRunMode();
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     }
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     /* Regulator now in main mode. */
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   else
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   {
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     /* If in run mode, first move to low-power run mode.
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****        The system clock frequency must be below 2 MHz at this point. */
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == 0U)
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     {
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****       HAL_PWREx_EnableLowPowerRunMode();
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     }
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+ 373              		.loc 1 468 3 is_stmt 1 view .LVU63
+ 374 0010 0C4A     		ldr	r2, .L37+4
+ 375 0012 1369     		ldr	r3, [r2, #16]
+ 376 0014 23F00403 		bic	r3, r3, #4
+ 377 0018 1361     		str	r3, [r2, #16]
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Select SLEEP mode entry -------------------------------------------------*/
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+ 378              		.loc 1 471 3 view .LVU64
+ 379              		.loc 1 471 5 is_stmt 0 view .LVU65
+ 380 001a 012C     		cmp	r4, #1
+ 381 001c 0ED0     		beq	.L36
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   {
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     /* Request Wait For Interrupt */
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     __WFI();
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   else
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   {
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     /* Request Wait For Event */
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     __SEV();
+ 382              		.loc 1 479 5 is_stmt 1 view .LVU66
+ 383              		.syntax unified
+ 384              	@ 479 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1
+ 385 001e 40BF     		sev
+ 386              	@ 0 "" 2
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     __WFE();
+ 387              		.loc 1 480 5 view .LVU67
+ 388              	@ 480 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1
+ 389 0020 20BF     		wfe
+ 390              	@ 0 "" 2
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     __WFE();
+ 391              		.loc 1 481 5 view .LVU68
+ARM GAS  /tmp/cchsYltI.s 			page 16
+
+
+ 392              	@ 481 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1
+ 393 0022 20BF     		wfe
+ 394              	@ 0 "" 2
+ 395              		.thumb
+ 396              		.syntax unified
+ 397              	.L29:
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 398              		.loc 1 484 1 is_stmt 0 view .LVU69
+ 399 0024 10BD     		pop	{r4, pc}
+ 400              	.LVL8:
+ 401              	.L35:
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     }
+ 402              		.loc 1 453 7 is_stmt 1 view .LVU70
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     }
+ 403              		.loc 1 453 13 is_stmt 0 view .LVU71
+ 404 0026 FFF7FEFF 		bl	HAL_PWREx_DisableLowPowerRunMode
+ 405              	.LVL9:
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     }
+ 406              		.loc 1 453 13 view .LVU72
+ 407 002a F1E7     		b	.L31
+ 408              	.LVL10:
+ 409              	.L30:
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     {
+ 410              		.loc 1 461 5 is_stmt 1 view .LVU73
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     {
+ 411              		.loc 1 461 9 is_stmt 0 view .LVU74
+ 412 002c 044B     		ldr	r3, .L37
+ 413 002e 5B69     		ldr	r3, [r3, #20]
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     {
+ 414              		.loc 1 461 8 view .LVU75
+ 415 0030 13F4007F 		tst	r3, #512
+ 416 0034 ECD1     		bne	.L31
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     }
+ 417              		.loc 1 463 7 is_stmt 1 view .LVU76
+ 418 0036 FFF7FEFF 		bl	HAL_PWREx_EnableLowPowerRunMode
+ 419              	.LVL11:
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     }
+ 420              		.loc 1 463 7 is_stmt 0 view .LVU77
+ 421 003a E9E7     		b	.L31
+ 422              	.L36:
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 423              		.loc 1 474 5 is_stmt 1 view .LVU78
+ 424              		.syntax unified
+ 425              	@ 474 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1
+ 426 003c 30BF     		wfi
+ 427              	@ 0 "" 2
+ 428              		.thumb
+ 429              		.syntax unified
+ 430 003e F1E7     		b	.L29
+ 431              	.L38:
+ 432              		.align	2
+ 433              	.L37:
+ 434 0040 00700040 		.word	1073770496
+ 435 0044 00ED00E0 		.word	-536810240
+ 436              		.cfi_endproc
+ARM GAS  /tmp/cchsYltI.s 			page 17
+
+
+ 437              	.LFE337:
+ 439              		.section	.text.HAL_PWR_EnterSTOPMode,"ax",%progbits
+ 440              		.align	1
+ 441              		.global	HAL_PWR_EnterSTOPMode
+ 442              		.syntax unified
+ 443              		.thumb
+ 444              		.thumb_func
+ 446              	HAL_PWR_EnterSTOPMode:
+ 447              	.LVL12:
+ 448              	.LFB338:
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Enter Stop mode
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        on devices where only "Stop mode" is mentioned with main or low power regulator ON.
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  All clocks in the VCORE domain are stopped; the PLL,
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capabilit
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the H
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is pr
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        only to the peripheral requesting it.
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        SRAM1, SRAM2 and register contents are preserved.
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        The BOR is available.
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Sto
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *         the HSI RC oscillator is selected as system clock.
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  When the voltage regulator operates in low power mode (Stop 1), an additional
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *         startup delay is incurred when waking up.
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *         By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *         is higher although the startup time is reduced.
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @param Regulator: Specifies the regulator state in Stop mode.
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *          This parameter can be one of the following values:
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power regulator ON)
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *          This parameter can be one of the following values:
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI instruction.
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE instruction.
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ 449              		.loc 1 517 1 view -0
+ 450              		.cfi_startproc
+ 451              		@ args = 0, pretend = 0, frame = 0
+ 452              		@ frame_needed = 0, uses_anonymous_args = 0
+ 453              		.loc 1 517 1 is_stmt 0 view .LVU80
+ 454 0000 08B5     		push	{r3, lr}
+ 455              	.LCFI1:
+ 456              		.cfi_def_cfa_offset 8
+ 457              		.cfi_offset 3, -8
+ 458              		.cfi_offset 14, -4
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Check the parameters */
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   assert_param(IS_PWR_REGULATOR(Regulator));
+ 459              		.loc 1 519 3 is_stmt 1 view .LVU81
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ARM GAS  /tmp/cchsYltI.s 			page 18
+
+
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   if(Regulator == PWR_LOWPOWERREGULATOR_ON)
+ 460              		.loc 1 521 3 view .LVU82
+ 461              		.loc 1 521 5 is_stmt 0 view .LVU83
+ 462 0002 B0F5804F 		cmp	r0, #16384
+ 463 0006 03D0     		beq	.L43
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   {
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     HAL_PWREx_EnterSTOP1Mode(STOPEntry);
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   else
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   {
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****     HAL_PWREx_EnterSTOP0Mode(STOPEntry);
+ 464              		.loc 1 527 5 is_stmt 1 view .LVU84
+ 465 0008 0846     		mov	r0, r1
+ 466              	.LVL13:
+ 467              		.loc 1 527 5 is_stmt 0 view .LVU85
+ 468 000a FFF7FEFF 		bl	HAL_PWREx_EnterSTOP0Mode
+ 469              	.LVL14:
+ 470              	.L39:
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 471              		.loc 1 529 1 view .LVU86
+ 472 000e 08BD     		pop	{r3, pc}
+ 473              	.LVL15:
+ 474              	.L43:
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 475              		.loc 1 523 5 is_stmt 1 view .LVU87
+ 476 0010 0846     		mov	r0, r1
+ 477              	.LVL16:
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 478              		.loc 1 523 5 is_stmt 0 view .LVU88
+ 479 0012 FFF7FEFF 		bl	HAL_PWREx_EnterSTOP1Mode
+ 480              	.LVL17:
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   }
+ 481              		.loc 1 523 5 view .LVU89
+ 482 0016 FAE7     		b	.L39
+ 483              		.cfi_endproc
+ 484              	.LFE338:
+ 486              		.section	.text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
+ 487              		.align	1
+ 488              		.global	HAL_PWR_EnterSTANDBYMode
+ 489              		.syntax unified
+ 490              		.thumb
+ 491              		.thumb_func
+ 493              	HAL_PWR_EnterSTANDBYMode:
+ 494              	.LFB339:
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Enter Standby mode.
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  In Standby mode, the PLL, the HSI and the HSE oscillators are switched
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        off. The voltage regulator is disabled, except when SRAM2 content is preserved
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        in which case the regulator is in low-power mode.
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        SRAM1 and register contents are lost except for registers in the Backup domain and
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 regis
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() A
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        to set RRS bit.
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        The BOR is available.
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog s
+ARM GAS  /tmp/cchsYltI.s 			page 19
+
+
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disab
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        same.
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        These states are effective in Standby mode only if APC bit is set through
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *        HAL_PWREx_EnablePullUpPullDownConfig() API.
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ 495              		.loc 1 550 1 is_stmt 1 view -0
+ 496              		.cfi_startproc
+ 497              		@ args = 0, pretend = 0, frame = 0
+ 498              		@ frame_needed = 0, uses_anonymous_args = 0
+ 499              		@ link register save eliminated.
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Set Stand-by mode */
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
+ 500              		.loc 1 552 3 view .LVU91
+ 501 0000 064A     		ldr	r2, .L45
+ 502 0002 1368     		ldr	r3, [r2]
+ 503 0004 23F00703 		bic	r3, r3, #7
+ 504 0008 43F00303 		orr	r3, r3, #3
+ 505 000c 1360     		str	r3, [r2]
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Set SLEEPDEEP bit of Cortex System Control Register */
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+ 506              		.loc 1 555 3 view .LVU92
+ 507 000e 044A     		ldr	r2, .L45+4
+ 508 0010 1369     		ldr	r3, [r2, #16]
+ 509 0012 43F00403 		orr	r3, r3, #4
+ 510 0016 1361     		str	r3, [r2, #16]
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #if defined ( __CC_ARM)
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   __force_stores();
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #endif
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Request Wait For Interrupt */
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   __WFI();
+ 511              		.loc 1 562 3 view .LVU93
+ 512              		.syntax unified
+ 513              	@ 562 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1
+ 514 0018 30BF     		wfi
+ 515              	@ 0 "" 2
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 516              		.loc 1 563 1 is_stmt 0 view .LVU94
+ 517              		.thumb
+ 518              		.syntax unified
+ 519 001a 7047     		bx	lr
+ 520              	.L46:
+ 521              		.align	2
+ 522              	.L45:
+ 523 001c 00700040 		.word	1073770496
+ 524 0020 00ED00E0 		.word	-536810240
+ 525              		.cfi_endproc
+ 526              	.LFE339:
+ 528              		.section	.text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
+ 529              		.align	1
+ 530              		.global	HAL_PWR_EnableSleepOnExit
+ARM GAS  /tmp/cchsYltI.s 			page 20
+
+
+ 531              		.syntax unified
+ 532              		.thumb
+ 533              		.thumb_func
+ 535              	HAL_PWR_EnableSleepOnExit:
+ 536              	.LFB340:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *       re-enters SLEEP mode when an interruption handling is over.
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *       Setting this bit is useful when the processor is expected to run only on
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *       interruptions handling.
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ 537              		.loc 1 576 1 is_stmt 1 view -0
+ 538              		.cfi_startproc
+ 539              		@ args = 0, pretend = 0, frame = 0
+ 540              		@ frame_needed = 0, uses_anonymous_args = 0
+ 541              		@ link register save eliminated.
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+ 542              		.loc 1 578 3 view .LVU96
+ 543 0000 024A     		ldr	r2, .L48
+ 544 0002 1369     		ldr	r3, [r2, #16]
+ 545 0004 43F00203 		orr	r3, r3, #2
+ 546 0008 1361     		str	r3, [r2, #16]
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 547              		.loc 1 579 1 is_stmt 0 view .LVU97
+ 548 000a 7047     		bx	lr
+ 549              	.L49:
+ 550              		.align	2
+ 551              	.L48:
+ 552 000c 00ED00E0 		.word	-536810240
+ 553              		.cfi_endproc
+ 554              	.LFE340:
+ 556              		.section	.text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
+ 557              		.align	1
+ 558              		.global	HAL_PWR_DisableSleepOnExit
+ 559              		.syntax unified
+ 560              		.thumb
+ 561              		.thumb_func
+ 563              	HAL_PWR_DisableSleepOnExit:
+ 564              	.LFB341:
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *       re-enters SLEEP mode when an interruption handling is over.
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ARM GAS  /tmp/cchsYltI.s 			page 21
+
+
+ 565              		.loc 1 589 1 is_stmt 1 view -0
+ 566              		.cfi_startproc
+ 567              		@ args = 0, pretend = 0, frame = 0
+ 568              		@ frame_needed = 0, uses_anonymous_args = 0
+ 569              		@ link register save eliminated.
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+ 570              		.loc 1 591 3 view .LVU99
+ 571 0000 024A     		ldr	r2, .L51
+ 572 0002 1369     		ldr	r3, [r2, #16]
+ 573 0004 23F00203 		bic	r3, r3, #2
+ 574 0008 1361     		str	r3, [r2, #16]
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 575              		.loc 1 592 1 is_stmt 0 view .LVU100
+ 576 000a 7047     		bx	lr
+ 577              	.L52:
+ 578              		.align	2
+ 579              	.L51:
+ 580 000c 00ED00E0 		.word	-536810240
+ 581              		.cfi_endproc
+ 582              	.LFE341:
+ 584              		.section	.text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
+ 585              		.align	1
+ 586              		.global	HAL_PWR_EnableSEVOnPend
+ 587              		.syntax unified
+ 588              		.thumb
+ 589              		.thumb_func
+ 591              	HAL_PWR_EnableSEVOnPend:
+ 592              	.LFB342:
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Enable CORTEX M4 SEVONPEND bit.
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *       WFE to wake up when an interrupt moves from inactive to pended.
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ 593              		.loc 1 603 1 is_stmt 1 view -0
+ 594              		.cfi_startproc
+ 595              		@ args = 0, pretend = 0, frame = 0
+ 596              		@ frame_needed = 0, uses_anonymous_args = 0
+ 597              		@ link register save eliminated.
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Set SEVONPEND bit of Cortex System Control Register */
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+ 598              		.loc 1 605 3 view .LVU102
+ 599 0000 024A     		ldr	r2, .L54
+ 600 0002 1369     		ldr	r3, [r2, #16]
+ 601 0004 43F01003 		orr	r3, r3, #16
+ 602 0008 1361     		str	r3, [r2, #16]
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 603              		.loc 1 606 1 is_stmt 0 view .LVU103
+ 604 000a 7047     		bx	lr
+ 605              	.L55:
+ 606              		.align	2
+ARM GAS  /tmp/cchsYltI.s 			page 22
+
+
+ 607              	.L54:
+ 608 000c 00ED00E0 		.word	-536810240
+ 609              		.cfi_endproc
+ 610              	.LFE342:
+ 612              		.section	.text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
+ 613              		.align	1
+ 614              		.global	HAL_PWR_DisableSEVOnPend
+ 615              		.syntax unified
+ 616              		.thumb
+ 617              		.thumb_func
+ 619              	HAL_PWR_DisableSEVOnPend:
+ 620              	.LFB343:
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief Disable CORTEX M4 SEVONPEND bit.
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   *       WFE to wake up when an interrupt moves from inactive to pended.
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ 621              		.loc 1 616 1 is_stmt 1 view -0
+ 622              		.cfi_startproc
+ 623              		@ args = 0, pretend = 0, frame = 0
+ 624              		@ frame_needed = 0, uses_anonymous_args = 0
+ 625              		@ link register save eliminated.
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* Clear SEVONPEND bit of Cortex System Control Register */
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+ 626              		.loc 1 618 3 view .LVU105
+ 627 0000 024A     		ldr	r2, .L57
+ 628 0002 1369     		ldr	r3, [r2, #16]
+ 629 0004 23F01003 		bic	r3, r3, #16
+ 630 0008 1361     		str	r3, [r2, #16]
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 631              		.loc 1 619 1 is_stmt 0 view .LVU106
+ 632 000a 7047     		bx	lr
+ 633              	.L58:
+ 634              		.align	2
+ 635              	.L57:
+ 636 000c 00ED00E0 		.word	-536810240
+ 637              		.cfi_endproc
+ 638              	.LFE343:
+ 640              		.section	.text.HAL_PWR_PVDCallback,"ax",%progbits
+ 641              		.align	1
+ 642              		.weak	HAL_PWR_PVDCallback
+ 643              		.syntax unified
+ 644              		.thumb
+ 645              		.thumb_func
+ 647              	HAL_PWR_PVDCallback:
+ 648              	.LFB344:
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
+ARM GAS  /tmp/cchsYltI.s 			page 23
+
+
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @brief PWR PVD interrupt callback
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   * @retval None
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   */
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void)
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
+ 649              		.loc 1 630 1 is_stmt 1 view -0
+ 650              		.cfi_startproc
+ 651              		@ args = 0, pretend = 0, frame = 0
+ 652              		@ frame_needed = 0, uses_anonymous_args = 0
+ 653              		@ link register save eliminated.
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****   /* NOTE : This function should not be modified; when the callback is needed,
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****             the HAL_PWR_PVDCallback can be implemented in the user file
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****    */
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
+ 654              		.loc 1 634 1 view .LVU108
+ 655 0000 7047     		bx	lr
+ 656              		.cfi_endproc
+ 657              	.LFE344:
+ 659              		.text
+ 660              	.Letext0:
+ 661              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 662              		.file 3 "Drivers/CMSIS/Include/core_cm4.h"
+ 663              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 664              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 665              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h"
+ 666              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"
+ARM GAS  /tmp/cchsYltI.s 			page 24
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_pwr.c
+     /tmp/cchsYltI.s:21     .text.HAL_PWR_DeInit:00000000 $t
+     /tmp/cchsYltI.s:27     .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit
+     /tmp/cchsYltI.s:48     .text.HAL_PWR_DeInit:00000014 $d
+     /tmp/cchsYltI.s:53     .text.HAL_PWR_EnableBkUpAccess:00000000 $t
+     /tmp/cchsYltI.s:59     .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess
+     /tmp/cchsYltI.s:76     .text.HAL_PWR_EnableBkUpAccess:0000000c $d
+     /tmp/cchsYltI.s:81     .text.HAL_PWR_DisableBkUpAccess:00000000 $t
+     /tmp/cchsYltI.s:87     .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess
+     /tmp/cchsYltI.s:104    .text.HAL_PWR_DisableBkUpAccess:0000000c $d
+     /tmp/cchsYltI.s:109    .text.HAL_PWR_ConfigPVD:00000000 $t
+     /tmp/cchsYltI.s:115    .text.HAL_PWR_ConfigPVD:00000000 HAL_PWR_ConfigPVD
+     /tmp/cchsYltI.s:206    .text.HAL_PWR_ConfigPVD:0000007c $d
+     /tmp/cchsYltI.s:212    .text.HAL_PWR_EnablePVD:00000000 $t
+     /tmp/cchsYltI.s:218    .text.HAL_PWR_EnablePVD:00000000 HAL_PWR_EnablePVD
+     /tmp/cchsYltI.s:235    .text.HAL_PWR_EnablePVD:0000000c $d
+     /tmp/cchsYltI.s:240    .text.HAL_PWR_DisablePVD:00000000 $t
+     /tmp/cchsYltI.s:246    .text.HAL_PWR_DisablePVD:00000000 HAL_PWR_DisablePVD
+     /tmp/cchsYltI.s:263    .text.HAL_PWR_DisablePVD:0000000c $d
+     /tmp/cchsYltI.s:268    .text.HAL_PWR_EnableWakeUpPin:00000000 $t
+     /tmp/cchsYltI.s:274    .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin
+     /tmp/cchsYltI.s:301    .text.HAL_PWR_EnableWakeUpPin:0000001c $d
+     /tmp/cchsYltI.s:306    .text.HAL_PWR_DisableWakeUpPin:00000000 $t
+     /tmp/cchsYltI.s:312    .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin
+     /tmp/cchsYltI.s:334    .text.HAL_PWR_DisableWakeUpPin:00000010 $d
+     /tmp/cchsYltI.s:339    .text.HAL_PWR_EnterSLEEPMode:00000000 $t
+     /tmp/cchsYltI.s:345    .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode
+     /tmp/cchsYltI.s:434    .text.HAL_PWR_EnterSLEEPMode:00000040 $d
+     /tmp/cchsYltI.s:440    .text.HAL_PWR_EnterSTOPMode:00000000 $t
+     /tmp/cchsYltI.s:446    .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode
+     /tmp/cchsYltI.s:487    .text.HAL_PWR_EnterSTANDBYMode:00000000 $t
+     /tmp/cchsYltI.s:493    .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode
+     /tmp/cchsYltI.s:523    .text.HAL_PWR_EnterSTANDBYMode:0000001c $d
+     /tmp/cchsYltI.s:529    .text.HAL_PWR_EnableSleepOnExit:00000000 $t
+     /tmp/cchsYltI.s:535    .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit
+     /tmp/cchsYltI.s:552    .text.HAL_PWR_EnableSleepOnExit:0000000c $d
+     /tmp/cchsYltI.s:557    .text.HAL_PWR_DisableSleepOnExit:00000000 $t
+     /tmp/cchsYltI.s:563    .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit
+     /tmp/cchsYltI.s:580    .text.HAL_PWR_DisableSleepOnExit:0000000c $d
+     /tmp/cchsYltI.s:585    .text.HAL_PWR_EnableSEVOnPend:00000000 $t
+     /tmp/cchsYltI.s:591    .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend
+     /tmp/cchsYltI.s:608    .text.HAL_PWR_EnableSEVOnPend:0000000c $d
+     /tmp/cchsYltI.s:613    .text.HAL_PWR_DisableSEVOnPend:00000000 $t
+     /tmp/cchsYltI.s:619    .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend
+     /tmp/cchsYltI.s:636    .text.HAL_PWR_DisableSEVOnPend:0000000c $d
+     /tmp/cchsYltI.s:641    .text.HAL_PWR_PVDCallback:00000000 $t
+     /tmp/cchsYltI.s:647    .text.HAL_PWR_PVDCallback:00000000 HAL_PWR_PVDCallback
+
+UNDEFINED SYMBOLS
+HAL_PWREx_DisableLowPowerRunMode
+HAL_PWREx_EnableLowPowerRunMode
+HAL_PWREx_EnterSTOP0Mode
+HAL_PWREx_EnterSTOP1Mode
diff --git a/squeow_sw/build/stm32g4xx_hal_pwr.o b/squeow_sw/build/stm32g4xx_hal_pwr.o
new file mode 100644
index 0000000000000000000000000000000000000000..cb264221889990859ee76fd369aae86d0e929277
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diff --git a/squeow_sw/build/stm32g4xx_hal_pwr_ex.d b/squeow_sw/build/stm32g4xx_hal_pwr_ex.d
new file mode 100644
index 0000000..6735abd
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_pwr_ex.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_pwr_ex.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_pwr_ex.lst b/squeow_sw/build/stm32g4xx_hal_pwr_ex.lst
new file mode 100644
index 0000000..134fdaf
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_pwr_ex.lst
@@ -0,0 +1,3933 @@
+ARM GAS  /tmp/cchjGo05.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_pwr_ex.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c"
+  20              		.section	.text.HAL_PWREx_GetVoltageRange,"ax",%progbits
+  21              		.align	1
+  22              		.global	HAL_PWREx_GetVoltageRange
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	HAL_PWREx_GetVoltageRange:
+  28              	.LFB329:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @file    stm32g4xx_hal_pwr_ex.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief   Extended PWR HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *          functionalities of the Power Controller (PWR) peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *           + Extended Initialization and de-initialization functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *           + Extended Peripheral Control functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   ******************************************************************************
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @attention
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * Copyright (c) 2019 STMicroelectronics.
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * All rights reserved.
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * in the root directory of this software component.
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   ******************************************************************************
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /* Includes ------------------------------------------------------------------*/
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #include "stm32g4xx_hal.h"
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @{
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ARM GAS  /tmp/cchjGo05.s 			page 2
+
+
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /** @defgroup PWREx PWREx
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief PWR Extended HAL module driver
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @{
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #ifdef HAL_PWR_MODULE_ENABLED
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /* Private typedef -----------------------------------------------------------*/
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /* Private define ------------------------------------------------------------*/
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #define PWR_PORTF_AVAILABLE_PINS   0x0000FFFFU /* PF0..PF15 */
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #define PWR_PORTG_AVAILABLE_PINS   0x000007FFU /* PG0..PG10 */
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) || defined (STM32G491
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #define PWR_PORTF_AVAILABLE_PINS   0x00000607U /* PF0..PF2 and PF9 and PF10 */
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #define PWR_PORTG_AVAILABLE_PINS   0x00000400U /* PG10 */
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #endif
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @{
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @{
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #define PVM_MODE_IT               0x00010000U    /*!< Mask for interruption yielded by PVM threshol
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #define PVM_MODE_EVT              0x00020000U    /*!< Mask for event yielded by PVM threshold cross
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #define PVM_RISING_EDGE           0x00000001U    /*!< Mask for rising edge set as PVM trigger      
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #define PVM_FALLING_EDGE          0x00000002U    /*!< Mask for falling edge set as PVM trigger     
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @}
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @{
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #define PWR_FLAG_SETTING_DELAY_US                      50UL   /*!< Time out value for REGLPF and VO
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @}
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @}
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /* Private macro -------------------------------------------------------------*/
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /* Private variables ---------------------------------------------------------*/
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /* Private function prototypes -----------------------------------------------*/
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /* Exported functions --------------------------------------------------------*/
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @{
+ARM GAS  /tmp/cchjGo05.s 			page 3
+
+
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *  @brief   Extended Peripheral Control functions
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** @verbatim
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****  ===============================================================================
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****               ##### Extended Peripheral Initialization and de-initialization functions #####
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****  ===============================================================================
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     [..]
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** @endverbatim
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @{
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Return Voltage Scaling Range.
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetVoltageRange(void)
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+  29              		.loc 1 110 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
+  34              		.loc 1 111 3 view .LVU1
+  35              		.loc 1 111 7 is_stmt 0 view .LVU2
+  36 0000 074B     		ldr	r3, .L4
+  37 0002 1868     		ldr	r0, [r3]
+  38 0004 00F4C060 		and	r0, r0, #1536
+  39              		.loc 1 111 6 view .LVU3
+  40 0008 B0F5806F 		cmp	r0, #1024
+  41 000c 04D0     		beq	.L1
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     return PWR_REGULATOR_VOLTAGE_SCALE2;
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE)
+  42              		.loc 1 115 8 is_stmt 1 view .LVU4
+  43              		.loc 1 115 12 is_stmt 0 view .LVU5
+  44 000e D3F88000 		ldr	r0, [r3, #128]
+  45              		.loc 1 115 11 view .LVU6
+  46 0012 10F48070 		ands	r0, r0, #256
+  47 0016 00D1     		bne	.L3
+  48              	.L1:
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     return PWR_REGULATOR_VOLTAGE_SCALE1;
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   else
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ARM GAS  /tmp/cchjGo05.s 			page 4
+
+
+  49              		.loc 1 124 1 view .LVU7
+  50 0018 7047     		bx	lr
+  51              	.L3:
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+  52              		.loc 1 118 12 view .LVU8
+  53 001a 4FF40070 		mov	r0, #512
+  54 001e FBE7     		b	.L1
+  55              	.L5:
+  56              		.align	2
+  57              	.L4:
+  58 0020 00700040 		.word	1073770496
+  59              		.cfi_endproc
+  60              	.LFE329:
+  62              		.section	.text.HAL_PWREx_ControlVoltageScaling,"ax",%progbits
+  63              		.align	1
+  64              		.global	HAL_PWREx_ControlVoltageScaling
+  65              		.syntax unified
+  66              		.thumb
+  67              		.thumb_func
+  69              	HAL_PWREx_ControlVoltageScaling:
+  70              	.LVL0:
+  71              	.LFB330:
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Configure the main internal regulator output voltage.
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param  VoltageScaling: specifies the regulator output voltage to achieve
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         a tradeoff between performance and power consumption.
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage outpu
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *                                                typical output voltage at 1.28 V,
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *                                                system frequency up to 170 MHz.
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *                                                typical output voltage at 1.2 V,
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *                                                system frequency up to 150 MHz.
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *                                                typical output voltage at 1.0 V,
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *                                                system frequency up to 26 MHz.
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        When moving from Range 2 to Range 1, the system frequency can be increased to
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        a value up to 150 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        When moving from Range 1 to Boost Mode Range 1, the system frequency can be increased to
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        a value up to 170 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  When moving from Range 2 to Range 1, the API waits for VOSF flag to be
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        cleared before returning the status. If the flag is not cleared within
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        50 microseconds, HAL_TIMEOUT status is reported.
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval HAL Status
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+  72              		.loc 1 154 1 is_stmt 1 view -0
+  73              		.cfi_startproc
+  74              		@ args = 0, pretend = 0, frame = 0
+  75              		@ frame_needed = 0, uses_anonymous_args = 0
+  76              		@ link register save eliminated.
+ARM GAS  /tmp/cchjGo05.s 			page 5
+
+
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   uint32_t wait_loop_index;
+  77              		.loc 1 155 3 view .LVU10
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+  78              		.loc 1 157 3 view .LVU11
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
+  79              		.loc 1 159 3 view .LVU12
+  80              		.loc 1 159 6 is_stmt 0 view .LVU13
+  81 0000 0028     		cmp	r0, #0
+  82 0002 36D1     		bne	.L7
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* If current range is range 2 */
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
+  83              		.loc 1 162 5 is_stmt 1 view .LVU14
+  84              		.loc 1 162 9 is_stmt 0 view .LVU15
+  85 0004 3E4B     		ldr	r3, .L23
+  86 0006 1B68     		ldr	r3, [r3]
+  87 0008 03F4C063 		and	r3, r3, #1536
+  88              		.loc 1 162 8 view .LVU16
+  89 000c B3F5806F 		cmp	r3, #1024
+  90 0010 08D0     		beq	.L20
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     {
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Make sure Range 1 Boost is enabled */
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Set Range 1 */
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Wait until VOSF is cleared */
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         wait_loop_index--;
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         return HAL_TIMEOUT;
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     }
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* If current range is range 1 normal or boost mode */
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     else
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     {
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Enable Range 1 Boost (no issue if bit already reset) */
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
+  91              		.loc 1 185 7 is_stmt 1 view .LVU17
+  92 0012 3B4A     		ldr	r2, .L23
+  93 0014 D2F88030 		ldr	r3, [r2, #128]
+  94 0018 23F48073 		bic	r3, r3, #256
+  95 001c C2F88030 		str	r3, [r2, #128]
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     }
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* If current range is range 2 */
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     {
+ARM GAS  /tmp/cchjGo05.s 			page 6
+
+
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Make sure Range 1 Boost is disabled */
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Set Range 1 */
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Wait until VOSF is cleared */
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         wait_loop_index--;
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         return HAL_TIMEOUT;
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     }
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****      /* If current range is range 1 normal or boost mode */
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     else
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     {
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Disable Range 1 Boost (no issue if bit already set) */
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     }
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   else
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* Set Range 2 */
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* No need to wait for VOSF to be cleared for this transition */
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* PWR_CR5_R1MODE bit setting has no effect in Range 2        */
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   return HAL_OK;
+  96              		.loc 1 225 10 is_stmt 0 view .LVU18
+  97 0020 0020     		movs	r0, #0
+  98              	.LVL1:
+  99              		.loc 1 225 10 view .LVU19
+ 100 0022 7047     		bx	lr
+ 101              	.LVL2:
+ 102              	.L20:
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 103              		.loc 1 165 7 is_stmt 1 view .LVU20
+ 104 0024 364A     		ldr	r2, .L23
+ 105 0026 D2F88030 		ldr	r3, [r2, #128]
+ 106 002a 23F48073 		bic	r3, r3, #256
+ 107 002e C2F88030 		str	r3, [r2, #128]
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 108              		.loc 1 168 7 view .LVU21
+ 109 0032 1368     		ldr	r3, [r2]
+ 110 0034 23F4C063 		bic	r3, r3, #1536
+ 111 0038 43F40073 		orr	r3, r3, #512
+ 112 003c 1360     		str	r3, [r2]
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
+ 113              		.loc 1 171 7 view .LVU22
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
+ 114              		.loc 1 171 53 is_stmt 0 view .LVU23
+ 115 003e 314B     		ldr	r3, .L23+4
+ARM GAS  /tmp/cchjGo05.s 			page 7
+
+
+ 116 0040 1B68     		ldr	r3, [r3]
+ 117 0042 3222     		movs	r2, #50
+ 118 0044 02FB03F3 		mul	r3, r2, r3
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
+ 119              		.loc 1 171 72 view .LVU24
+ 120 0048 2F4A     		ldr	r2, .L23+8
+ 121 004a A2FB0323 		umull	r2, r3, r2, r3
+ 122 004e 9B0C     		lsrs	r3, r3, #18
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
+ 123              		.loc 1 171 23 view .LVU25
+ 124 0050 0133     		adds	r3, r3, #1
+ 125              	.LVL3:
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 126              		.loc 1 172 7 is_stmt 1 view .LVU26
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 127              		.loc 1 172 13 is_stmt 0 view .LVU27
+ 128 0052 00E0     		b	.L9
+ 129              	.L11:
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 130              		.loc 1 174 9 is_stmt 1 view .LVU28
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 131              		.loc 1 174 24 is_stmt 0 view .LVU29
+ 132 0054 013B     		subs	r3, r3, #1
+ 133              	.LVL4:
+ 134              	.L9:
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 135              		.loc 1 172 55 is_stmt 1 view .LVU30
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 136              		.loc 1 172 15 is_stmt 0 view .LVU31
+ 137 0056 2A4A     		ldr	r2, .L23
+ 138 0058 5269     		ldr	r2, [r2, #20]
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 139              		.loc 1 172 55 view .LVU32
+ 140 005a 12F4806F 		tst	r2, #1024
+ 141 005e 01D0     		beq	.L10
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 142              		.loc 1 172 55 discriminator 1 view .LVU33
+ 143 0060 002B     		cmp	r3, #0
+ 144 0062 F7D1     		bne	.L11
+ 145              	.L10:
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 146              		.loc 1 176 7 is_stmt 1 view .LVU34
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 147              		.loc 1 176 11 is_stmt 0 view .LVU35
+ 148 0064 264B     		ldr	r3, .L23
+ 149              	.LVL5:
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 150              		.loc 1 176 11 view .LVU36
+ 151 0066 5B69     		ldr	r3, [r3, #20]
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 152              		.loc 1 176 10 view .LVU37
+ 153 0068 13F4806F 		tst	r3, #1024
+ 154 006c 44D1     		bne	.L18
+ 155              		.loc 1 225 10 view .LVU38
+ 156 006e 0020     		movs	r0, #0
+ 157              	.LVL6:
+ 158              		.loc 1 225 10 view .LVU39
+ARM GAS  /tmp/cchjGo05.s 			page 8
+
+
+ 159 0070 7047     		bx	lr
+ 160              	.LVL7:
+ 161              	.L7:
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 162              		.loc 1 188 8 is_stmt 1 view .LVU40
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 163              		.loc 1 188 11 is_stmt 0 view .LVU41
+ 164 0072 B0F5007F 		cmp	r0, #512
+ 165 0076 08D0     		beq	.L21
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* No need to wait for VOSF to be cleared for this transition */
+ 166              		.loc 1 220 5 is_stmt 1 view .LVU42
+ 167 0078 214A     		ldr	r2, .L23
+ 168 007a 1368     		ldr	r3, [r2]
+ 169 007c 23F4C063 		bic	r3, r3, #1536
+ 170 0080 43F48063 		orr	r3, r3, #1024
+ 171 0084 1360     		str	r3, [r2]
+ 172              		.loc 1 225 10 is_stmt 0 view .LVU43
+ 173 0086 0020     		movs	r0, #0
+ 174              	.LVL8:
+ 175              		.loc 1 225 10 view .LVU44
+ 176 0088 7047     		bx	lr
+ 177              	.LVL9:
+ 178              	.L21:
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     {
+ 179              		.loc 1 191 5 is_stmt 1 view .LVU45
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     {
+ 180              		.loc 1 191 9 is_stmt 0 view .LVU46
+ 181 008a 1D4B     		ldr	r3, .L23
+ 182 008c 1B68     		ldr	r3, [r3]
+ 183 008e 03F4C063 		and	r3, r3, #1536
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     {
+ 184              		.loc 1 191 8 view .LVU47
+ 185 0092 B3F5806F 		cmp	r3, #1024
+ 186 0096 08D0     		beq	.L22
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     }
+ 187              		.loc 1 214 7 is_stmt 1 view .LVU48
+ 188 0098 194A     		ldr	r2, .L23
+ 189 009a D2F88030 		ldr	r3, [r2, #128]
+ 190 009e 43F48073 		orr	r3, r3, #256
+ 191 00a2 C2F88030 		str	r3, [r2, #128]
+ 192              		.loc 1 225 10 is_stmt 0 view .LVU49
+ 193 00a6 0020     		movs	r0, #0
+ 194              	.LVL10:
+ 195              		.loc 1 225 10 view .LVU50
+ 196 00a8 7047     		bx	lr
+ 197              	.LVL11:
+ 198              	.L22:
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 199              		.loc 1 194 7 is_stmt 1 view .LVU51
+ 200 00aa 154A     		ldr	r2, .L23
+ 201 00ac D2F88030 		ldr	r3, [r2, #128]
+ 202 00b0 43F48073 		orr	r3, r3, #256
+ 203 00b4 C2F88030 		str	r3, [r2, #128]
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 204              		.loc 1 197 7 view .LVU52
+ 205 00b8 1368     		ldr	r3, [r2]
+ 206 00ba 23F4C063 		bic	r3, r3, #1536
+ARM GAS  /tmp/cchjGo05.s 			page 9
+
+
+ 207 00be 43F40073 		orr	r3, r3, #512
+ 208 00c2 1360     		str	r3, [r2]
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
+ 209              		.loc 1 200 7 view .LVU53
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
+ 210              		.loc 1 200 53 is_stmt 0 view .LVU54
+ 211 00c4 0F4B     		ldr	r3, .L23+4
+ 212 00c6 1B68     		ldr	r3, [r3]
+ 213 00c8 3222     		movs	r2, #50
+ 214 00ca 02FB03F3 		mul	r3, r2, r3
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
+ 215              		.loc 1 200 72 view .LVU55
+ 216 00ce 0E4A     		ldr	r2, .L23+8
+ 217 00d0 A2FB0323 		umull	r2, r3, r2, r3
+ 218 00d4 9B0C     		lsrs	r3, r3, #18
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
+ 219              		.loc 1 200 23 view .LVU56
+ 220 00d6 0133     		adds	r3, r3, #1
+ 221              	.LVL12:
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 222              		.loc 1 201 7 is_stmt 1 view .LVU57
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 223              		.loc 1 201 13 is_stmt 0 view .LVU58
+ 224 00d8 00E0     		b	.L15
+ 225              	.L17:
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 226              		.loc 1 203 9 is_stmt 1 view .LVU59
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 227              		.loc 1 203 24 is_stmt 0 view .LVU60
+ 228 00da 013B     		subs	r3, r3, #1
+ 229              	.LVL13:
+ 230              	.L15:
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 231              		.loc 1 201 55 is_stmt 1 view .LVU61
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 232              		.loc 1 201 15 is_stmt 0 view .LVU62
+ 233 00dc 084A     		ldr	r2, .L23
+ 234 00de 5269     		ldr	r2, [r2, #20]
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 235              		.loc 1 201 55 view .LVU63
+ 236 00e0 12F4806F 		tst	r2, #1024
+ 237 00e4 01D0     		beq	.L16
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 238              		.loc 1 201 55 discriminator 1 view .LVU64
+ 239 00e6 002B     		cmp	r3, #0
+ 240 00e8 F7D1     		bne	.L17
+ 241              	.L16:
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 242              		.loc 1 205 7 is_stmt 1 view .LVU65
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 243              		.loc 1 205 11 is_stmt 0 view .LVU66
+ 244 00ea 054B     		ldr	r3, .L23
+ 245              	.LVL14:
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 246              		.loc 1 205 11 view .LVU67
+ 247 00ec 5B69     		ldr	r3, [r3, #20]
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ARM GAS  /tmp/cchjGo05.s 			page 10
+
+
+ 248              		.loc 1 205 10 view .LVU68
+ 249 00ee 13F4806F 		tst	r3, #1024
+ 250 00f2 03D1     		bne	.L19
+ 251              		.loc 1 225 10 view .LVU69
+ 252 00f4 0020     		movs	r0, #0
+ 253              	.LVL15:
+ 254              		.loc 1 225 10 view .LVU70
+ 255 00f6 7047     		bx	lr
+ 256              	.LVL16:
+ 257              	.L18:
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 258              		.loc 1 178 16 view .LVU71
+ 259 00f8 0320     		movs	r0, #3
+ 260              	.LVL17:
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 261              		.loc 1 178 16 view .LVU72
+ 262 00fa 7047     		bx	lr
+ 263              	.LVL18:
+ 264              	.L19:
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 265              		.loc 1 207 16 view .LVU73
+ 266 00fc 0320     		movs	r0, #3
+ 267              	.LVL19:
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 268              		.loc 1 226 1 view .LVU74
+ 269 00fe 7047     		bx	lr
+ 270              	.L24:
+ 271              		.align	2
+ 272              	.L23:
+ 273 0100 00700040 		.word	1073770496
+ 274 0104 00000000 		.word	SystemCoreClock
+ 275 0108 83DE1B43 		.word	1125899907
+ 276              		.cfi_endproc
+ 277              	.LFE330:
+ 279              		.section	.text.HAL_PWREx_EnableBatteryCharging,"ax",%progbits
+ 280              		.align	1
+ 281              		.global	HAL_PWREx_EnableBatteryCharging
+ 282              		.syntax unified
+ 283              		.thumb
+ 284              		.thumb_func
+ 286              	HAL_PWREx_EnableBatteryCharging:
+ 287              	.LVL20:
+ 288              	.LFB331:
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enable battery charging.
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        When VDD is present, charge the external battery on VBAT through an internal resistor.
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param  ResistorSelection: specifies the resistor impedance.
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5     5 kOhms resistor
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 289              		.loc 1 239 1 is_stmt 1 view -0
+ARM GAS  /tmp/cchjGo05.s 			page 11
+
+
+ 290              		.cfi_startproc
+ 291              		@ args = 0, pretend = 0, frame = 0
+ 292              		@ frame_needed = 0, uses_anonymous_args = 0
+ 293              		@ link register save eliminated.
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
+ 294              		.loc 1 240 3 view .LVU76
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Specify resistor selection */
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
+ 295              		.loc 1 243 3 view .LVU77
+ 296 0000 054A     		ldr	r2, .L26
+ 297 0002 D368     		ldr	r3, [r2, #12]
+ 298 0004 23F40073 		bic	r3, r3, #512
+ 299 0008 0343     		orrs	r3, r3, r0
+ 300 000a D360     		str	r3, [r2, #12]
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Enable battery charging */
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(PWR->CR4, PWR_CR4_VBE);
+ 301              		.loc 1 246 3 view .LVU78
+ 302 000c D368     		ldr	r3, [r2, #12]
+ 303 000e 43F48073 		orr	r3, r3, #256
+ 304 0012 D360     		str	r3, [r2, #12]
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 305              		.loc 1 247 1 is_stmt 0 view .LVU79
+ 306 0014 7047     		bx	lr
+ 307              	.L27:
+ 308 0016 00BF     		.align	2
+ 309              	.L26:
+ 310 0018 00700040 		.word	1073770496
+ 311              		.cfi_endproc
+ 312              	.LFE331:
+ 314              		.section	.text.HAL_PWREx_DisableBatteryCharging,"ax",%progbits
+ 315              		.align	1
+ 316              		.global	HAL_PWREx_DisableBatteryCharging
+ 317              		.syntax unified
+ 318              		.thumb
+ 319              		.thumb_func
+ 321              	HAL_PWREx_DisableBatteryCharging:
+ 322              	.LFB332:
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Disable battery charging.
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_DisableBatteryCharging(void)
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 323              		.loc 1 255 1 is_stmt 1 view -0
+ 324              		.cfi_startproc
+ 325              		@ args = 0, pretend = 0, frame = 0
+ 326              		@ frame_needed = 0, uses_anonymous_args = 0
+ 327              		@ link register save eliminated.
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
+ 328              		.loc 1 256 3 view .LVU81
+ 329 0000 024A     		ldr	r2, .L29
+ 330 0002 D368     		ldr	r3, [r2, #12]
+ 331 0004 23F48073 		bic	r3, r3, #256
+ARM GAS  /tmp/cchjGo05.s 			page 12
+
+
+ 332 0008 D360     		str	r3, [r2, #12]
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 333              		.loc 1 257 1 is_stmt 0 view .LVU82
+ 334 000a 7047     		bx	lr
+ 335              	.L30:
+ 336              		.align	2
+ 337              	.L29:
+ 338 000c 00700040 		.word	1073770496
+ 339              		.cfi_endproc
+ 340              	.LFE332:
+ 342              		.section	.text.HAL_PWREx_EnableInternalWakeUpLine,"ax",%progbits
+ 343              		.align	1
+ 344              		.global	HAL_PWREx_EnableInternalWakeUpLine
+ 345              		.syntax unified
+ 346              		.thumb
+ 347              		.thumb_func
+ 349              	HAL_PWREx_EnableInternalWakeUpLine:
+ 350              	.LFB333:
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enable Internal Wake-up Line.
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnableInternalWakeUpLine(void)
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 351              		.loc 1 265 1 is_stmt 1 view -0
+ 352              		.cfi_startproc
+ 353              		@ args = 0, pretend = 0, frame = 0
+ 354              		@ frame_needed = 0, uses_anonymous_args = 0
+ 355              		@ link register save eliminated.
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(PWR->CR3, PWR_CR3_EIWF);
+ 356              		.loc 1 266 3 view .LVU84
+ 357 0000 024A     		ldr	r2, .L32
+ 358 0002 9368     		ldr	r3, [r2, #8]
+ 359 0004 43F40043 		orr	r3, r3, #32768
+ 360 0008 9360     		str	r3, [r2, #8]
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 361              		.loc 1 267 1 is_stmt 0 view .LVU85
+ 362 000a 7047     		bx	lr
+ 363              	.L33:
+ 364              		.align	2
+ 365              	.L32:
+ 366 000c 00700040 		.word	1073770496
+ 367              		.cfi_endproc
+ 368              	.LFE333:
+ 370              		.section	.text.HAL_PWREx_DisableInternalWakeUpLine,"ax",%progbits
+ 371              		.align	1
+ 372              		.global	HAL_PWREx_DisableInternalWakeUpLine
+ 373              		.syntax unified
+ 374              		.thumb
+ 375              		.thumb_func
+ 377              	HAL_PWREx_DisableInternalWakeUpLine:
+ 378              	.LFB334:
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ARM GAS  /tmp/cchjGo05.s 			page 13
+
+
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Disable Internal Wake-up Line.
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_DisableInternalWakeUpLine(void)
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 379              		.loc 1 275 1 is_stmt 1 view -0
+ 380              		.cfi_startproc
+ 381              		@ args = 0, pretend = 0, frame = 0
+ 382              		@ frame_needed = 0, uses_anonymous_args = 0
+ 383              		@ link register save eliminated.
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
+ 384              		.loc 1 276 3 view .LVU87
+ 385 0000 024A     		ldr	r2, .L35
+ 386 0002 9368     		ldr	r3, [r2, #8]
+ 387 0004 23F40043 		bic	r3, r3, #32768
+ 388 0008 9360     		str	r3, [r2, #8]
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 389              		.loc 1 277 1 is_stmt 0 view .LVU88
+ 390 000a 7047     		bx	lr
+ 391              	.L36:
+ 392              		.align	2
+ 393              	.L35:
+ 394 000c 00700040 		.word	1073770496
+ 395              		.cfi_endproc
+ 396              	.LFE334:
+ 398              		.section	.text.HAL_PWREx_EnableGPIOPullUp,"ax",%progbits
+ 399              		.align	1
+ 400              		.global	HAL_PWREx_EnableGPIOPullUp
+ 401              		.syntax unified
+ 402              		.thumb
+ 403              		.thumb_func
+ 405              	HAL_PWREx_EnableGPIOPullUp:
+ 406              	.LVL21:
+ 407              	.LFB335:
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        pull-up state in Standby and Shutdown modes.
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  This state is effective in Standby and Shutdown modes only if APC bit
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  The configuration is lost when exiting the Shutdown mode due to the
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        power-on reset, maintained when exiting the Standby mode.
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        PDy bit of PWR_PDCRx register is cleared unless it is reserved.
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  Even if a PUy bit to set is reserved, the other PUy bits entered as input
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        parameter at the same time are set.
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param  GPIONumber: Specify the I/O pins numbers.
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         This parameter can be one of the following values:
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         I/O pins are available) or the logical OR of several of them to set
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         several bits for a given port in a single API call.
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval HAL Status
+ARM GAS  /tmp/cchjGo05.s 			page 14
+
+
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 408              		.loc 1 303 1 is_stmt 1 view -0
+ 409              		.cfi_startproc
+ 410              		@ args = 0, pretend = 0, frame = 0
+ 411              		@ frame_needed = 0, uses_anonymous_args = 0
+ 412              		@ link register save eliminated.
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 413              		.loc 1 304 3 view .LVU90
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_GPIO(GPIO));
+ 414              		.loc 1 306 3 view .LVU91
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+ 415              		.loc 1 307 3 view .LVU92
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   switch (GPIO)
+ 416              		.loc 1 309 3 view .LVU93
+ 417 0000 0628     		cmp	r0, #6
+ 418 0002 55D8     		bhi	.L47
+ 419 0004 DFE800F0 		tbb	[pc, r0]
+ 420              	.L40:
+ 421 0008 04       		.byte	(.L46-.L40)/2
+ 422 0009 12       		.byte	(.L45-.L40)/2
+ 423 000a 1E       		.byte	(.L44-.L40)/2
+ 424 000b 28       		.byte	(.L43-.L40)/2
+ 425 000c 32       		.byte	(.L42-.L40)/2
+ 426 000d 3C       		.byte	(.L41-.L40)/2
+ 427 000e 4A       		.byte	(.L39-.L40)/2
+ 428 000f 00       		.p2align 1
+ 429              	.L46:
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_A:
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
+ 430              		.loc 1 312 8 view .LVU94
+ 431 0010 284B     		ldr	r3, .L48
+ 432 0012 1A6A     		ldr	r2, [r3, #32]
+ 433 0014 21F48040 		bic	r0, r1, #16384
+ 434              	.LVL22:
+ 435              		.loc 1 312 8 is_stmt 0 view .LVU95
+ 436 0018 0243     		orrs	r2, r2, r0
+ 437 001a 1A62     		str	r2, [r3, #32]
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
+ 438              		.loc 1 313 8 is_stmt 1 view .LVU96
+ 439 001c 5A6A     		ldr	r2, [r3, #36]
+ 440 001e 21F42041 		bic	r1, r1, #40960
+ 441              	.LVL23:
+ 442              		.loc 1 313 8 is_stmt 0 view .LVU97
+ 443 0022 22EA0102 		bic	r2, r2, r1
+ 444 0026 5A62     		str	r2, [r3, #36]
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 445              		.loc 1 314 8 is_stmt 1 view .LVU98
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 446              		.loc 1 304 21 is_stmt 0 view .LVU99
+ 447 0028 0020     		movs	r0, #0
+ 448              		.loc 1 314 8 view .LVU100
+ 449 002a 7047     		bx	lr
+ARM GAS  /tmp/cchjGo05.s 			page 15
+
+
+ 450              	.LVL24:
+ 451              	.L45:
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_B:
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PUCRB, GPIONumber);
+ 452              		.loc 1 316 8 is_stmt 1 view .LVU101
+ 453 002c 214B     		ldr	r3, .L48
+ 454 002e 9A6A     		ldr	r2, [r3, #40]
+ 455 0030 0A43     		orrs	r2, r2, r1
+ 456 0032 9A62     		str	r2, [r3, #40]
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
+ 457              		.loc 1 317 8 view .LVU102
+ 458 0034 DA6A     		ldr	r2, [r3, #44]
+ 459 0036 21F01001 		bic	r1, r1, #16
+ 460              	.LVL25:
+ 461              		.loc 1 317 8 is_stmt 0 view .LVU103
+ 462 003a 22EA0102 		bic	r2, r2, r1
+ 463 003e DA62     		str	r2, [r3, #44]
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 464              		.loc 1 318 8 is_stmt 1 view .LVU104
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 465              		.loc 1 304 21 is_stmt 0 view .LVU105
+ 466 0040 0020     		movs	r0, #0
+ 467              	.LVL26:
+ 468              		.loc 1 318 8 view .LVU106
+ 469 0042 7047     		bx	lr
+ 470              	.LVL27:
+ 471              	.L44:
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_C:
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PUCRC, GPIONumber);
+ 472              		.loc 1 320 8 is_stmt 1 view .LVU107
+ 473 0044 1B4B     		ldr	r3, .L48
+ 474 0046 1A6B     		ldr	r2, [r3, #48]
+ 475 0048 0A43     		orrs	r2, r2, r1
+ 476 004a 1A63     		str	r2, [r3, #48]
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRC, GPIONumber);
+ 477              		.loc 1 321 8 view .LVU108
+ 478 004c 5A6B     		ldr	r2, [r3, #52]
+ 479 004e 22EA0102 		bic	r2, r2, r1
+ 480 0052 5A63     		str	r2, [r3, #52]
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 481              		.loc 1 322 8 view .LVU109
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 482              		.loc 1 304 21 is_stmt 0 view .LVU110
+ 483 0054 0020     		movs	r0, #0
+ 484              	.LVL28:
+ 485              		.loc 1 322 8 view .LVU111
+ 486 0056 7047     		bx	lr
+ 487              	.LVL29:
+ 488              	.L43:
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_D:
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PUCRD, GPIONumber);
+ 489              		.loc 1 324 8 is_stmt 1 view .LVU112
+ 490 0058 164B     		ldr	r3, .L48
+ 491 005a 9A6B     		ldr	r2, [r3, #56]
+ 492 005c 0A43     		orrs	r2, r2, r1
+ 493 005e 9A63     		str	r2, [r3, #56]
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRD, GPIONumber);
+ARM GAS  /tmp/cchjGo05.s 			page 16
+
+
+ 494              		.loc 1 325 8 view .LVU113
+ 495 0060 DA6B     		ldr	r2, [r3, #60]
+ 496 0062 22EA0102 		bic	r2, r2, r1
+ 497 0066 DA63     		str	r2, [r3, #60]
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 498              		.loc 1 326 8 view .LVU114
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 499              		.loc 1 304 21 is_stmt 0 view .LVU115
+ 500 0068 0020     		movs	r0, #0
+ 501              	.LVL30:
+ 502              		.loc 1 326 8 view .LVU116
+ 503 006a 7047     		bx	lr
+ 504              	.LVL31:
+ 505              	.L42:
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_E:
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PUCRE, GPIONumber);
+ 506              		.loc 1 328 8 is_stmt 1 view .LVU117
+ 507 006c 114B     		ldr	r3, .L48
+ 508 006e 1A6C     		ldr	r2, [r3, #64]
+ 509 0070 0A43     		orrs	r2, r2, r1
+ 510 0072 1A64     		str	r2, [r3, #64]
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRE, GPIONumber);
+ 511              		.loc 1 329 8 view .LVU118
+ 512 0074 5A6C     		ldr	r2, [r3, #68]
+ 513 0076 22EA0102 		bic	r2, r2, r1
+ 514 007a 5A64     		str	r2, [r3, #68]
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 515              		.loc 1 330 8 view .LVU119
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 516              		.loc 1 304 21 is_stmt 0 view .LVU120
+ 517 007c 0020     		movs	r0, #0
+ 518              	.LVL32:
+ 519              		.loc 1 330 8 view .LVU121
+ 520 007e 7047     		bx	lr
+ 521              	.LVL33:
+ 522              	.L41:
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_F:
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+ 523              		.loc 1 332 8 is_stmt 1 view .LVU122
+ 524 0080 0C4B     		ldr	r3, .L48
+ 525 0082 9A6C     		ldr	r2, [r3, #72]
+ 526 0084 21F4FC71 		bic	r1, r1, #504
+ 527              	.LVL34:
+ 528              		.loc 1 332 8 is_stmt 0 view .LVU123
+ 529 0088 4905     		lsls	r1, r1, #21
+ 530 008a 490D     		lsrs	r1, r1, #21
+ 531 008c 0A43     		orrs	r2, r2, r1
+ 532 008e 9A64     		str	r2, [r3, #72]
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+ 533              		.loc 1 333 8 is_stmt 1 view .LVU124
+ 534 0090 DA6C     		ldr	r2, [r3, #76]
+ 535 0092 22EA0102 		bic	r2, r2, r1
+ 536 0096 DA64     		str	r2, [r3, #76]
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 537              		.loc 1 334 8 view .LVU125
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 538              		.loc 1 304 21 is_stmt 0 view .LVU126
+ARM GAS  /tmp/cchjGo05.s 			page 17
+
+
+ 539 0098 0020     		movs	r0, #0
+ 540              	.LVL35:
+ 541              		.loc 1 334 8 view .LVU127
+ 542 009a 7047     		bx	lr
+ 543              	.LVL36:
+ 544              	.L39:
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_G:
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
+ 545              		.loc 1 336 8 is_stmt 1 view .LVU128
+ 546 009c 054B     		ldr	r3, .L48
+ 547 009e 1A6D     		ldr	r2, [r3, #80]
+ 548 00a0 01F48061 		and	r1, r1, #1024
+ 549              	.LVL37:
+ 550              		.loc 1 336 8 is_stmt 0 view .LVU129
+ 551 00a4 0A43     		orrs	r2, r2, r1
+ 552 00a6 1A65     		str	r2, [r3, #80]
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
+ 553              		.loc 1 337 8 is_stmt 1 view .LVU130
+ 554 00a8 5A6D     		ldr	r2, [r3, #84]
+ 555 00aa 5A65     		str	r2, [r3, #84]
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 556              		.loc 1 338 8 view .LVU131
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 557              		.loc 1 304 21 is_stmt 0 view .LVU132
+ 558 00ac 0020     		movs	r0, #0
+ 559              	.LVL38:
+ 560              		.loc 1 338 8 view .LVU133
+ 561 00ae 7047     		bx	lr
+ 562              	.LVL39:
+ 563              	.L47:
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 564              		.loc 1 309 3 view .LVU134
+ 565 00b0 0120     		movs	r0, #1
+ 566              	.LVL40:
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     default:
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       status = HAL_ERROR;
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       break;
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   return status;
+ 567              		.loc 1 344 3 is_stmt 1 view .LVU135
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 568              		.loc 1 345 1 is_stmt 0 view .LVU136
+ 569 00b2 7047     		bx	lr
+ 570              	.L49:
+ 571              		.align	2
+ 572              	.L48:
+ 573 00b4 00700040 		.word	1073770496
+ 574              		.cfi_endproc
+ 575              	.LFE335:
+ 577              		.section	.text.HAL_PWREx_DisableGPIOPullUp,"ax",%progbits
+ 578              		.align	1
+ 579              		.global	HAL_PWREx_DisableGPIOPullUp
+ 580              		.syntax unified
+ 581              		.thumb
+ 582              		.thumb_func
+ 584              	HAL_PWREx_DisableGPIOPullUp:
+ARM GAS  /tmp/cchjGo05.s 			page 18
+
+
+ 585              	.LVL41:
+ 586              	.LFB336:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        in pull-up state in Standby and Shutdown modes.
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  Even if a PUy bit to reset is reserved, the other PUy bits entered as input
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        parameter at the same time are reset.
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *          (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param  GPIONumber: Specify the I/O pins numbers.
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         This parameter can be one of the following values:
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         I/O pins are available) or the logical OR of several of them to reset
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         several bits for a given port in a single API call.
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval HAL Status
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 587              		.loc 1 364 1 is_stmt 1 view -0
+ 588              		.cfi_startproc
+ 589              		@ args = 0, pretend = 0, frame = 0
+ 590              		@ frame_needed = 0, uses_anonymous_args = 0
+ 591              		@ link register save eliminated.
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 592              		.loc 1 365 3 view .LVU138
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_GPIO(GPIO));
+ 593              		.loc 1 367 3 view .LVU139
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+ 594              		.loc 1 368 3 view .LVU140
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   switch (GPIO)
+ 595              		.loc 1 370 3 view .LVU141
+ 596 0000 0628     		cmp	r0, #6
+ 597 0002 3ED8     		bhi	.L60
+ 598 0004 DFE800F0 		tbb	[pc, r0]
+ 599              	.L53:
+ 600 0008 04       		.byte	(.L59-.L53)/2
+ 601 0009 0D       		.byte	(.L58-.L53)/2
+ 602 000a 14       		.byte	(.L57-.L53)/2
+ 603 000b 1B       		.byte	(.L56-.L53)/2
+ 604 000c 22       		.byte	(.L55-.L53)/2
+ 605 000d 29       		.byte	(.L54-.L53)/2
+ 606 000e 34       		.byte	(.L52-.L53)/2
+ 607 000f 00       		.p2align 1
+ 608              	.L59:
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_A:
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
+ 609              		.loc 1 373 8 view .LVU142
+ 610 0010 1D4A     		ldr	r2, .L61
+ 611 0012 136A     		ldr	r3, [r2, #32]
+ 612 0014 21F48041 		bic	r1, r1, #16384
+ 613              	.LVL42:
+ARM GAS  /tmp/cchjGo05.s 			page 19
+
+
+ 614              		.loc 1 373 8 is_stmt 0 view .LVU143
+ 615 0018 23EA0101 		bic	r1, r3, r1
+ 616 001c 1162     		str	r1, [r2, #32]
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 617              		.loc 1 374 8 is_stmt 1 view .LVU144
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 618              		.loc 1 365 21 is_stmt 0 view .LVU145
+ 619 001e 0020     		movs	r0, #0
+ 620              	.LVL43:
+ 621              		.loc 1 374 8 view .LVU146
+ 622 0020 7047     		bx	lr
+ 623              	.LVL44:
+ 624              	.L58:
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_B:
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRB, GPIONumber);
+ 625              		.loc 1 376 8 is_stmt 1 view .LVU147
+ 626 0022 194A     		ldr	r2, .L61
+ 627 0024 936A     		ldr	r3, [r2, #40]
+ 628 0026 23EA0103 		bic	r3, r3, r1
+ 629 002a 9362     		str	r3, [r2, #40]
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 630              		.loc 1 377 8 view .LVU148
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 631              		.loc 1 365 21 is_stmt 0 view .LVU149
+ 632 002c 0020     		movs	r0, #0
+ 633              	.LVL45:
+ 634              		.loc 1 377 8 view .LVU150
+ 635 002e 7047     		bx	lr
+ 636              	.LVL46:
+ 637              	.L57:
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_C:
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRC, GPIONumber);
+ 638              		.loc 1 379 8 is_stmt 1 view .LVU151
+ 639 0030 154A     		ldr	r2, .L61
+ 640 0032 136B     		ldr	r3, [r2, #48]
+ 641 0034 23EA0103 		bic	r3, r3, r1
+ 642 0038 1363     		str	r3, [r2, #48]
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 643              		.loc 1 380 8 view .LVU152
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 644              		.loc 1 365 21 is_stmt 0 view .LVU153
+ 645 003a 0020     		movs	r0, #0
+ 646              	.LVL47:
+ 647              		.loc 1 380 8 view .LVU154
+ 648 003c 7047     		bx	lr
+ 649              	.LVL48:
+ 650              	.L56:
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_D:
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRD, GPIONumber);
+ 651              		.loc 1 382 8 is_stmt 1 view .LVU155
+ 652 003e 124A     		ldr	r2, .L61
+ 653 0040 936B     		ldr	r3, [r2, #56]
+ 654 0042 23EA0103 		bic	r3, r3, r1
+ 655 0046 9363     		str	r3, [r2, #56]
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 656              		.loc 1 383 8 view .LVU156
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ARM GAS  /tmp/cchjGo05.s 			page 20
+
+
+ 657              		.loc 1 365 21 is_stmt 0 view .LVU157
+ 658 0048 0020     		movs	r0, #0
+ 659              	.LVL49:
+ 660              		.loc 1 383 8 view .LVU158
+ 661 004a 7047     		bx	lr
+ 662              	.LVL50:
+ 663              	.L55:
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_E:
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRE, GPIONumber);
+ 664              		.loc 1 385 8 is_stmt 1 view .LVU159
+ 665 004c 0E4A     		ldr	r2, .L61
+ 666 004e 136C     		ldr	r3, [r2, #64]
+ 667 0050 23EA0103 		bic	r3, r3, r1
+ 668 0054 1364     		str	r3, [r2, #64]
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 669              		.loc 1 386 8 view .LVU160
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 670              		.loc 1 365 21 is_stmt 0 view .LVU161
+ 671 0056 0020     		movs	r0, #0
+ 672              	.LVL51:
+ 673              		.loc 1 386 8 view .LVU162
+ 674 0058 7047     		bx	lr
+ 675              	.LVL52:
+ 676              	.L54:
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_F:
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+ 677              		.loc 1 388 8 is_stmt 1 view .LVU163
+ 678 005a 0B4A     		ldr	r2, .L61
+ 679 005c 936C     		ldr	r3, [r2, #72]
+ 680 005e 21F4FC71 		bic	r1, r1, #504
+ 681              	.LVL53:
+ 682              		.loc 1 388 8 is_stmt 0 view .LVU164
+ 683 0062 4905     		lsls	r1, r1, #21
+ 684 0064 490D     		lsrs	r1, r1, #21
+ 685 0066 23EA0101 		bic	r1, r3, r1
+ 686 006a 9164     		str	r1, [r2, #72]
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 687              		.loc 1 389 8 is_stmt 1 view .LVU165
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 688              		.loc 1 365 21 is_stmt 0 view .LVU166
+ 689 006c 0020     		movs	r0, #0
+ 690              	.LVL54:
+ 691              		.loc 1 389 8 view .LVU167
+ 692 006e 7047     		bx	lr
+ 693              	.LVL55:
+ 694              	.L52:
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_G:
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
+ 695              		.loc 1 391 8 is_stmt 1 view .LVU168
+ 696 0070 054A     		ldr	r2, .L61
+ 697 0072 136D     		ldr	r3, [r2, #80]
+ 698 0074 01F48061 		and	r1, r1, #1024
+ 699              	.LVL56:
+ 700              		.loc 1 391 8 is_stmt 0 view .LVU169
+ 701 0078 23EA0103 		bic	r3, r3, r1
+ 702 007c 1365     		str	r3, [r2, #80]
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ARM GAS  /tmp/cchjGo05.s 			page 21
+
+
+ 703              		.loc 1 392 8 is_stmt 1 view .LVU170
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 704              		.loc 1 365 21 is_stmt 0 view .LVU171
+ 705 007e 0020     		movs	r0, #0
+ 706              	.LVL57:
+ 707              		.loc 1 392 8 view .LVU172
+ 708 0080 7047     		bx	lr
+ 709              	.LVL58:
+ 710              	.L60:
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 711              		.loc 1 370 3 view .LVU173
+ 712 0082 0120     		movs	r0, #1
+ 713              	.LVL59:
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     default:
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        status = HAL_ERROR;
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   return status;
+ 714              		.loc 1 398 3 is_stmt 1 view .LVU174
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 715              		.loc 1 399 1 is_stmt 0 view .LVU175
+ 716 0084 7047     		bx	lr
+ 717              	.L62:
+ 718 0086 00BF     		.align	2
+ 719              	.L61:
+ 720 0088 00700040 		.word	1073770496
+ 721              		.cfi_endproc
+ 722              	.LFE336:
+ 724              		.section	.text.HAL_PWREx_EnableGPIOPullDown,"ax",%progbits
+ 725              		.align	1
+ 726              		.global	HAL_PWREx_EnableGPIOPullDown
+ 727              		.syntax unified
+ 728              		.thumb
+ 729              		.thumb_func
+ 731              	HAL_PWREx_EnableGPIOPullDown:
+ 732              	.LVL60:
+ 733              	.LFB337:
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        pull-down state in Standby and Shutdown modes.
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  This state is effective in Standby and Shutdown modes only if APC bit
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  The configuration is lost when exiting the Shutdown mode due to the
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        power-on reset, maintained when exiting the Standby mode.
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        PUy bit of PWR_PUCRx register is cleared unless it is reserved.
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  Even if a PDy bit to set is reserved, the other PDy bits entered as input
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        parameter at the same time are set.
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param  GPIONumber: Specify the I/O pins numbers.
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         This parameter can be one of the following values:
+ARM GAS  /tmp/cchjGo05.s 			page 22
+
+
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         I/O pins are available) or the logical OR of several of them to set
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         several bits for a given port in a single API call.
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval HAL Status
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 734              		.loc 1 425 1 is_stmt 1 view -0
+ 735              		.cfi_startproc
+ 736              		@ args = 0, pretend = 0, frame = 0
+ 737              		@ frame_needed = 0, uses_anonymous_args = 0
+ 738              		@ link register save eliminated.
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 739              		.loc 1 426 3 view .LVU177
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_GPIO(GPIO));
+ 740              		.loc 1 428 3 view .LVU178
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+ 741              		.loc 1 429 3 view .LVU179
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   switch (GPIO)
+ 742              		.loc 1 431 3 view .LVU180
+ 743 0000 0628     		cmp	r0, #6
+ 744 0002 56D8     		bhi	.L73
+ 745 0004 DFE800F0 		tbb	[pc, r0]
+ 746              	.L66:
+ 747 0008 04       		.byte	(.L72-.L66)/2
+ 748 0009 12       		.byte	(.L71-.L66)/2
+ 749 000a 1E       		.byte	(.L70-.L66)/2
+ 750 000b 28       		.byte	(.L69-.L66)/2
+ 751 000c 32       		.byte	(.L68-.L66)/2
+ 752 000d 3C       		.byte	(.L67-.L66)/2
+ 753 000e 4A       		.byte	(.L65-.L66)/2
+ 754 000f 00       		.p2align 1
+ 755              	.L72:
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_A:
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
+ 756              		.loc 1 434 8 view .LVU181
+ 757 0010 294B     		ldr	r3, .L74
+ 758 0012 5A6A     		ldr	r2, [r3, #36]
+ 759 0014 21F42040 		bic	r0, r1, #40960
+ 760              	.LVL61:
+ 761              		.loc 1 434 8 is_stmt 0 view .LVU182
+ 762 0018 0243     		orrs	r2, r2, r0
+ 763 001a 5A62     		str	r2, [r3, #36]
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
+ 764              		.loc 1 435 8 is_stmt 1 view .LVU183
+ 765 001c 1A6A     		ldr	r2, [r3, #32]
+ 766 001e 21F48041 		bic	r1, r1, #16384
+ 767              	.LVL62:
+ 768              		.loc 1 435 8 is_stmt 0 view .LVU184
+ 769 0022 22EA0102 		bic	r2, r2, r1
+ 770 0026 1A62     		str	r2, [r3, #32]
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 771              		.loc 1 436 8 is_stmt 1 view .LVU185
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ARM GAS  /tmp/cchjGo05.s 			page 23
+
+
+ 772              		.loc 1 426 21 is_stmt 0 view .LVU186
+ 773 0028 0020     		movs	r0, #0
+ 774              		.loc 1 436 8 view .LVU187
+ 775 002a 7047     		bx	lr
+ 776              	.LVL63:
+ 777              	.L71:
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_B:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
+ 778              		.loc 1 438 8 is_stmt 1 view .LVU188
+ 779 002c 224B     		ldr	r3, .L74
+ 780 002e DA6A     		ldr	r2, [r3, #44]
+ 781 0030 21F01000 		bic	r0, r1, #16
+ 782              	.LVL64:
+ 783              		.loc 1 438 8 is_stmt 0 view .LVU189
+ 784 0034 0243     		orrs	r2, r2, r0
+ 785 0036 DA62     		str	r2, [r3, #44]
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRB, GPIONumber);
+ 786              		.loc 1 439 8 is_stmt 1 view .LVU190
+ 787 0038 9A6A     		ldr	r2, [r3, #40]
+ 788 003a 22EA0102 		bic	r2, r2, r1
+ 789 003e 9A62     		str	r2, [r3, #40]
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 790              		.loc 1 440 8 view .LVU191
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 791              		.loc 1 426 21 is_stmt 0 view .LVU192
+ 792 0040 0020     		movs	r0, #0
+ 793              		.loc 1 440 8 view .LVU193
+ 794 0042 7047     		bx	lr
+ 795              	.LVL65:
+ 796              	.L70:
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_C:
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PDCRC, GPIONumber);
+ 797              		.loc 1 442 8 is_stmt 1 view .LVU194
+ 798 0044 1C4B     		ldr	r3, .L74
+ 799 0046 5A6B     		ldr	r2, [r3, #52]
+ 800 0048 0A43     		orrs	r2, r2, r1
+ 801 004a 5A63     		str	r2, [r3, #52]
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRC, GPIONumber);
+ 802              		.loc 1 443 8 view .LVU195
+ 803 004c 1A6B     		ldr	r2, [r3, #48]
+ 804 004e 22EA0102 		bic	r2, r2, r1
+ 805 0052 1A63     		str	r2, [r3, #48]
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 806              		.loc 1 444 8 view .LVU196
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 807              		.loc 1 426 21 is_stmt 0 view .LVU197
+ 808 0054 0020     		movs	r0, #0
+ 809              	.LVL66:
+ 810              		.loc 1 444 8 view .LVU198
+ 811 0056 7047     		bx	lr
+ 812              	.LVL67:
+ 813              	.L69:
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_D:
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PDCRD, GPIONumber);
+ 814              		.loc 1 446 8 is_stmt 1 view .LVU199
+ 815 0058 174B     		ldr	r3, .L74
+ 816 005a DA6B     		ldr	r2, [r3, #60]
+ARM GAS  /tmp/cchjGo05.s 			page 24
+
+
+ 817 005c 0A43     		orrs	r2, r2, r1
+ 818 005e DA63     		str	r2, [r3, #60]
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRD, GPIONumber);
+ 819              		.loc 1 447 8 view .LVU200
+ 820 0060 9A6B     		ldr	r2, [r3, #56]
+ 821 0062 22EA0102 		bic	r2, r2, r1
+ 822 0066 9A63     		str	r2, [r3, #56]
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 823              		.loc 1 448 8 view .LVU201
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 824              		.loc 1 426 21 is_stmt 0 view .LVU202
+ 825 0068 0020     		movs	r0, #0
+ 826              	.LVL68:
+ 827              		.loc 1 448 8 view .LVU203
+ 828 006a 7047     		bx	lr
+ 829              	.LVL69:
+ 830              	.L68:
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_E:
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PDCRE, GPIONumber);
+ 831              		.loc 1 450 8 is_stmt 1 view .LVU204
+ 832 006c 124B     		ldr	r3, .L74
+ 833 006e 5A6C     		ldr	r2, [r3, #68]
+ 834 0070 0A43     		orrs	r2, r2, r1
+ 835 0072 5A64     		str	r2, [r3, #68]
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRE, GPIONumber);
+ 836              		.loc 1 451 8 view .LVU205
+ 837 0074 1A6C     		ldr	r2, [r3, #64]
+ 838 0076 22EA0102 		bic	r2, r2, r1
+ 839 007a 1A64     		str	r2, [r3, #64]
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 840              		.loc 1 452 8 view .LVU206
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 841              		.loc 1 426 21 is_stmt 0 view .LVU207
+ 842 007c 0020     		movs	r0, #0
+ 843              	.LVL70:
+ 844              		.loc 1 452 8 view .LVU208
+ 845 007e 7047     		bx	lr
+ 846              	.LVL71:
+ 847              	.L67:
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_F:
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+ 848              		.loc 1 454 8 is_stmt 1 view .LVU209
+ 849 0080 0D4B     		ldr	r3, .L74
+ 850 0082 DA6C     		ldr	r2, [r3, #76]
+ 851 0084 21F4FC71 		bic	r1, r1, #504
+ 852              	.LVL72:
+ 853              		.loc 1 454 8 is_stmt 0 view .LVU210
+ 854 0088 4905     		lsls	r1, r1, #21
+ 855 008a 490D     		lsrs	r1, r1, #21
+ 856 008c 0A43     		orrs	r2, r2, r1
+ 857 008e DA64     		str	r2, [r3, #76]
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+ 858              		.loc 1 455 8 is_stmt 1 view .LVU211
+ 859 0090 9A6C     		ldr	r2, [r3, #72]
+ 860 0092 22EA0102 		bic	r2, r2, r1
+ 861 0096 9A64     		str	r2, [r3, #72]
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ARM GAS  /tmp/cchjGo05.s 			page 25
+
+
+ 862              		.loc 1 456 8 view .LVU212
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 863              		.loc 1 426 21 is_stmt 0 view .LVU213
+ 864 0098 0020     		movs	r0, #0
+ 865              	.LVL73:
+ 866              		.loc 1 456 8 view .LVU214
+ 867 009a 7047     		bx	lr
+ 868              	.LVL74:
+ 869              	.L65:
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_G:
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        SET_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
+ 870              		.loc 1 458 8 is_stmt 1 view .LVU215
+ 871 009c 064B     		ldr	r3, .L74
+ 872 009e 5A6D     		ldr	r2, [r3, #84]
+ 873 00a0 5A65     		str	r2, [r3, #84]
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
+ 874              		.loc 1 459 8 view .LVU216
+ 875 00a2 1A6D     		ldr	r2, [r3, #80]
+ 876 00a4 01F48061 		and	r1, r1, #1024
+ 877              	.LVL75:
+ 878              		.loc 1 459 8 is_stmt 0 view .LVU217
+ 879 00a8 22EA0102 		bic	r2, r2, r1
+ 880 00ac 1A65     		str	r2, [r3, #80]
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 881              		.loc 1 460 8 is_stmt 1 view .LVU218
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 882              		.loc 1 426 21 is_stmt 0 view .LVU219
+ 883 00ae 0020     		movs	r0, #0
+ 884              	.LVL76:
+ 885              		.loc 1 460 8 view .LVU220
+ 886 00b0 7047     		bx	lr
+ 887              	.LVL77:
+ 888              	.L73:
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 889              		.loc 1 431 3 view .LVU221
+ 890 00b2 0120     		movs	r0, #1
+ 891              	.LVL78:
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     default:
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       status = HAL_ERROR;
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       break;
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   return status;
+ 892              		.loc 1 466 3 is_stmt 1 view .LVU222
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 893              		.loc 1 467 1 is_stmt 0 view .LVU223
+ 894 00b4 7047     		bx	lr
+ 895              	.L75:
+ 896 00b6 00BF     		.align	2
+ 897              	.L74:
+ 898 00b8 00700040 		.word	1073770496
+ 899              		.cfi_endproc
+ 900              	.LFE337:
+ 902              		.section	.text.HAL_PWREx_DisableGPIOPullDown,"ax",%progbits
+ 903              		.align	1
+ 904              		.global	HAL_PWREx_DisableGPIOPullDown
+ 905              		.syntax unified
+ARM GAS  /tmp/cchjGo05.s 			page 26
+
+
+ 906              		.thumb
+ 907              		.thumb_func
+ 909              	HAL_PWREx_DisableGPIOPullDown:
+ 910              	.LVL79:
+ 911              	.LFB338:
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        in pull-down state in Standby and Shutdown modes.
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  Even if a PDy bit to reset is reserved, the other PDy bits entered as input
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        parameter at the same time are reset.
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param  GPIONumber: Specify the I/O pins numbers.
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         This parameter can be one of the following values:
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         I/O pins are available) or the logical OR of several of them to reset
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         several bits for a given port in a single API call.
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval HAL Status
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 912              		.loc 1 486 1 is_stmt 1 view -0
+ 913              		.cfi_startproc
+ 914              		@ args = 0, pretend = 0, frame = 0
+ 915              		@ frame_needed = 0, uses_anonymous_args = 0
+ 916              		@ link register save eliminated.
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 917              		.loc 1 487 3 view .LVU225
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_GPIO(GPIO));
+ 918              		.loc 1 489 3 view .LVU226
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+ 919              		.loc 1 490 3 view .LVU227
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   switch (GPIO)
+ 920              		.loc 1 492 3 view .LVU228
+ 921 0000 0628     		cmp	r0, #6
+ 922 0002 3CD8     		bhi	.L86
+ 923 0004 DFE800F0 		tbb	[pc, r0]
+ 924              	.L79:
+ 925 0008 04       		.byte	(.L85-.L79)/2
+ 926 0009 0D       		.byte	(.L84-.L79)/2
+ 927 000a 16       		.byte	(.L83-.L79)/2
+ 928 000b 1D       		.byte	(.L82-.L79)/2
+ 929 000c 24       		.byte	(.L81-.L79)/2
+ 930 000d 2B       		.byte	(.L80-.L79)/2
+ 931 000e 36       		.byte	(.L78-.L79)/2
+ 932 000f 00       		.p2align 1
+ 933              	.L85:
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_A:
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
+ 934              		.loc 1 495 8 view .LVU229
+ 935 0010 1C4A     		ldr	r2, .L87
+ARM GAS  /tmp/cchjGo05.s 			page 27
+
+
+ 936 0012 536A     		ldr	r3, [r2, #36]
+ 937 0014 21F42041 		bic	r1, r1, #40960
+ 938              	.LVL80:
+ 939              		.loc 1 495 8 is_stmt 0 view .LVU230
+ 940 0018 23EA0101 		bic	r1, r3, r1
+ 941 001c 5162     		str	r1, [r2, #36]
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 942              		.loc 1 496 8 is_stmt 1 view .LVU231
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 943              		.loc 1 487 21 is_stmt 0 view .LVU232
+ 944 001e 0020     		movs	r0, #0
+ 945              	.LVL81:
+ 946              		.loc 1 496 8 view .LVU233
+ 947 0020 7047     		bx	lr
+ 948              	.LVL82:
+ 949              	.L84:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_B:
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
+ 950              		.loc 1 498 8 is_stmt 1 view .LVU234
+ 951 0022 184A     		ldr	r2, .L87
+ 952 0024 D36A     		ldr	r3, [r2, #44]
+ 953 0026 21F01001 		bic	r1, r1, #16
+ 954              	.LVL83:
+ 955              		.loc 1 498 8 is_stmt 0 view .LVU235
+ 956 002a 23EA0101 		bic	r1, r3, r1
+ 957 002e D162     		str	r1, [r2, #44]
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 958              		.loc 1 499 8 is_stmt 1 view .LVU236
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 959              		.loc 1 487 21 is_stmt 0 view .LVU237
+ 960 0030 0020     		movs	r0, #0
+ 961              	.LVL84:
+ 962              		.loc 1 499 8 view .LVU238
+ 963 0032 7047     		bx	lr
+ 964              	.LVL85:
+ 965              	.L83:
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_C:
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRC, GPIONumber);
+ 966              		.loc 1 501 8 is_stmt 1 view .LVU239
+ 967 0034 134A     		ldr	r2, .L87
+ 968 0036 536B     		ldr	r3, [r2, #52]
+ 969 0038 23EA0103 		bic	r3, r3, r1
+ 970 003c 5363     		str	r3, [r2, #52]
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 971              		.loc 1 502 8 view .LVU240
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 972              		.loc 1 487 21 is_stmt 0 view .LVU241
+ 973 003e 0020     		movs	r0, #0
+ 974              	.LVL86:
+ 975              		.loc 1 502 8 view .LVU242
+ 976 0040 7047     		bx	lr
+ 977              	.LVL87:
+ 978              	.L82:
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_D:
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRD, GPIONumber);
+ 979              		.loc 1 504 8 is_stmt 1 view .LVU243
+ 980 0042 104A     		ldr	r2, .L87
+ARM GAS  /tmp/cchjGo05.s 			page 28
+
+
+ 981 0044 D36B     		ldr	r3, [r2, #60]
+ 982 0046 23EA0103 		bic	r3, r3, r1
+ 983 004a D363     		str	r3, [r2, #60]
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 984              		.loc 1 505 8 view .LVU244
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 985              		.loc 1 487 21 is_stmt 0 view .LVU245
+ 986 004c 0020     		movs	r0, #0
+ 987              	.LVL88:
+ 988              		.loc 1 505 8 view .LVU246
+ 989 004e 7047     		bx	lr
+ 990              	.LVL89:
+ 991              	.L81:
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_E:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRE, GPIONumber);
+ 992              		.loc 1 507 8 is_stmt 1 view .LVU247
+ 993 0050 0C4A     		ldr	r2, .L87
+ 994 0052 536C     		ldr	r3, [r2, #68]
+ 995 0054 23EA0103 		bic	r3, r3, r1
+ 996 0058 5364     		str	r3, [r2, #68]
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 997              		.loc 1 508 8 view .LVU248
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 998              		.loc 1 487 21 is_stmt 0 view .LVU249
+ 999 005a 0020     		movs	r0, #0
+ 1000              	.LVL90:
+ 1001              		.loc 1 508 8 view .LVU250
+ 1002 005c 7047     		bx	lr
+ 1003              	.LVL91:
+ 1004              	.L80:
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_F:
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
+ 1005              		.loc 1 510 8 is_stmt 1 view .LVU251
+ 1006 005e 094A     		ldr	r2, .L87
+ 1007 0060 D36C     		ldr	r3, [r2, #76]
+ 1008 0062 21F4FC71 		bic	r1, r1, #504
+ 1009              	.LVL92:
+ 1010              		.loc 1 510 8 is_stmt 0 view .LVU252
+ 1011 0066 4905     		lsls	r1, r1, #21
+ 1012 0068 490D     		lsrs	r1, r1, #21
+ 1013 006a 23EA0103 		bic	r3, r3, r1
+ 1014 006e D364     		str	r3, [r2, #76]
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 1015              		.loc 1 511 8 is_stmt 1 view .LVU253
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1016              		.loc 1 487 21 is_stmt 0 view .LVU254
+ 1017 0070 0020     		movs	r0, #0
+ 1018              	.LVL93:
+ 1019              		.loc 1 511 8 view .LVU255
+ 1020 0072 7047     		bx	lr
+ 1021              	.LVL94:
+ 1022              	.L78:
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_GPIO_G:
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
+ 1023              		.loc 1 513 8 is_stmt 1 view .LVU256
+ 1024 0074 034B     		ldr	r3, .L87
+ 1025 0076 5A6D     		ldr	r2, [r3, #84]
+ARM GAS  /tmp/cchjGo05.s 			page 29
+
+
+ 1026 0078 5A65     		str	r2, [r3, #84]
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****        break;
+ 1027              		.loc 1 514 8 view .LVU257
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1028              		.loc 1 487 21 is_stmt 0 view .LVU258
+ 1029 007a 0020     		movs	r0, #0
+ 1030              	.LVL95:
+ 1031              		.loc 1 514 8 view .LVU259
+ 1032 007c 7047     		bx	lr
+ 1033              	.LVL96:
+ 1034              	.L86:
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 1035              		.loc 1 492 3 view .LVU260
+ 1036 007e 0120     		movs	r0, #1
+ 1037              	.LVL97:
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     default:
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       status = HAL_ERROR;
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       break;
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   return status;
+ 1038              		.loc 1 520 3 is_stmt 1 view .LVU261
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1039              		.loc 1 521 1 is_stmt 0 view .LVU262
+ 1040 0080 7047     		bx	lr
+ 1041              	.L88:
+ 1042 0082 00BF     		.align	2
+ 1043              	.L87:
+ 1044 0084 00700040 		.word	1073770496
+ 1045              		.cfi_endproc
+ 1046              	.LFE338:
+ 1048              		.section	.text.HAL_PWREx_EnablePullUpPullDownConfig,"ax",%progbits
+ 1049              		.align	1
+ 1050              		.global	HAL_PWREx_EnablePullUpPullDownConfig
+ 1051              		.syntax unified
+ 1052              		.thumb
+ 1053              		.thumb_func
+ 1055              	HAL_PWREx_EnablePullUpPullDownConfig:
+ 1056              	.LFB339:
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enable pull-up and pull-down configuration.
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  When APC bit is set, the I/O pull-up and pull-down configurations defined in
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        is no conflict when setting PUy or PDy bit.
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnablePullUpPullDownConfig(void)
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1057              		.loc 1 536 1 is_stmt 1 view -0
+ 1058              		.cfi_startproc
+ 1059              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/cchjGo05.s 			page 30
+
+
+ 1060              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1061              		@ link register save eliminated.
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(PWR->CR3, PWR_CR3_APC);
+ 1062              		.loc 1 537 3 view .LVU264
+ 1063 0000 024A     		ldr	r2, .L90
+ 1064 0002 9368     		ldr	r3, [r2, #8]
+ 1065 0004 43F48063 		orr	r3, r3, #1024
+ 1066 0008 9360     		str	r3, [r2, #8]
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1067              		.loc 1 538 1 is_stmt 0 view .LVU265
+ 1068 000a 7047     		bx	lr
+ 1069              	.L91:
+ 1070              		.align	2
+ 1071              	.L90:
+ 1072 000c 00700040 		.word	1073770496
+ 1073              		.cfi_endproc
+ 1074              	.LFE339:
+ 1076              		.section	.text.HAL_PWREx_DisablePullUpPullDownConfig,"ax",%progbits
+ 1077              		.align	1
+ 1078              		.global	HAL_PWREx_DisablePullUpPullDownConfig
+ 1079              		.syntax unified
+ 1080              		.thumb
+ 1081              		.thumb_func
+ 1083              	HAL_PWREx_DisablePullUpPullDownConfig:
+ 1084              	.LFB340:
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Disable pull-up and pull-down configuration.
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_DisablePullUpPullDownConfig(void)
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1085              		.loc 1 548 1 is_stmt 1 view -0
+ 1086              		.cfi_startproc
+ 1087              		@ args = 0, pretend = 0, frame = 0
+ 1088              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1089              		@ link register save eliminated.
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
+ 1090              		.loc 1 549 3 view .LVU267
+ 1091 0000 024A     		ldr	r2, .L93
+ 1092 0002 9368     		ldr	r3, [r2, #8]
+ 1093 0004 23F48063 		bic	r3, r3, #1024
+ 1094 0008 9360     		str	r3, [r2, #8]
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1095              		.loc 1 550 1 is_stmt 0 view .LVU268
+ 1096 000a 7047     		bx	lr
+ 1097              	.L94:
+ 1098              		.align	2
+ 1099              	.L93:
+ 1100 000c 00700040 		.word	1073770496
+ 1101              		.cfi_endproc
+ 1102              	.LFE340:
+ 1104              		.section	.text.HAL_PWREx_EnableSRAM2ContentRetention,"ax",%progbits
+ 1105              		.align	1
+ARM GAS  /tmp/cchjGo05.s 			page 31
+
+
+ 1106              		.global	HAL_PWREx_EnableSRAM2ContentRetention
+ 1107              		.syntax unified
+ 1108              		.thumb
+ 1109              		.thumb_func
+ 1111              	HAL_PWREx_EnableSRAM2ContentRetention:
+ 1112              	.LFB341:
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enable SRAM2 content retention in Standby mode.
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  When RRS bit is set, SRAM2 is powered by the low-power regulator in
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         Standby mode and its content is kept.
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnableSRAM2ContentRetention(void)
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1113              		.loc 1 561 1 is_stmt 1 view -0
+ 1114              		.cfi_startproc
+ 1115              		@ args = 0, pretend = 0, frame = 0
+ 1116              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1117              		@ link register save eliminated.
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(PWR->CR3, PWR_CR3_RRS);
+ 1118              		.loc 1 562 3 view .LVU270
+ 1119 0000 024A     		ldr	r2, .L96
+ 1120 0002 9368     		ldr	r3, [r2, #8]
+ 1121 0004 43F48073 		orr	r3, r3, #256
+ 1122 0008 9360     		str	r3, [r2, #8]
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1123              		.loc 1 563 1 is_stmt 0 view .LVU271
+ 1124 000a 7047     		bx	lr
+ 1125              	.L97:
+ 1126              		.align	2
+ 1127              	.L96:
+ 1128 000c 00700040 		.word	1073770496
+ 1129              		.cfi_endproc
+ 1130              	.LFE341:
+ 1132              		.section	.text.HAL_PWREx_DisableSRAM2ContentRetention,"ax",%progbits
+ 1133              		.align	1
+ 1134              		.global	HAL_PWREx_DisableSRAM2ContentRetention
+ 1135              		.syntax unified
+ 1136              		.thumb
+ 1137              		.thumb_func
+ 1139              	HAL_PWREx_DisableSRAM2ContentRetention:
+ 1140              	.LFB342:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Disable SRAM2 content retention in Standby mode.
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  When RRS bit is reset, SRAM2 is powered off in Standby mode
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        and its content is lost.
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_DisableSRAM2ContentRetention(void)
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1141              		.loc 1 573 1 is_stmt 1 view -0
+ 1142              		.cfi_startproc
+ARM GAS  /tmp/cchjGo05.s 			page 32
+
+
+ 1143              		@ args = 0, pretend = 0, frame = 0
+ 1144              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1145              		@ link register save eliminated.
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
+ 1146              		.loc 1 574 3 view .LVU273
+ 1147 0000 024A     		ldr	r2, .L99
+ 1148 0002 9368     		ldr	r3, [r2, #8]
+ 1149 0004 23F48073 		bic	r3, r3, #256
+ 1150 0008 9360     		str	r3, [r2, #8]
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1151              		.loc 1 575 1 is_stmt 0 view .LVU274
+ 1152 000a 7047     		bx	lr
+ 1153              	.L100:
+ 1154              		.align	2
+ 1155              	.L99:
+ 1156 000c 00700040 		.word	1073770496
+ 1157              		.cfi_endproc
+ 1158              	.LFE342:
+ 1160              		.section	.text.HAL_PWREx_EnablePVM1,"ax",%progbits
+ 1161              		.align	1
+ 1162              		.global	HAL_PWREx_EnablePVM1
+ 1163              		.syntax unified
+ 1164              		.thumb
+ 1165              		.thumb_func
+ 1167              	HAL_PWREx_EnablePVM1:
+ 1168              	.LFB343:
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #if defined(PWR_CR2_PVME1)
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnablePVM1(void)
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1169              		.loc 1 586 1 is_stmt 1 view -0
+ 1170              		.cfi_startproc
+ 1171              		@ args = 0, pretend = 0, frame = 0
+ 1172              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1173              		@ link register save eliminated.
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(PWR->CR2, PWR_PVM_1);
+ 1174              		.loc 1 587 3 view .LVU276
+ 1175 0000 024A     		ldr	r2, .L102
+ 1176 0002 5368     		ldr	r3, [r2, #4]
+ 1177 0004 43F01003 		orr	r3, r3, #16
+ 1178 0008 5360     		str	r3, [r2, #4]
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1179              		.loc 1 588 1 is_stmt 0 view .LVU277
+ 1180 000a 7047     		bx	lr
+ 1181              	.L103:
+ 1182              		.align	2
+ 1183              	.L102:
+ 1184 000c 00700040 		.word	1073770496
+ 1185              		.cfi_endproc
+ 1186              	.LFE343:
+ARM GAS  /tmp/cchjGo05.s 			page 33
+
+
+ 1188              		.section	.text.HAL_PWREx_DisablePVM1,"ax",%progbits
+ 1189              		.align	1
+ 1190              		.global	HAL_PWREx_DisablePVM1
+ 1191              		.syntax unified
+ 1192              		.thumb
+ 1193              		.thumb_func
+ 1195              	HAL_PWREx_DisablePVM1:
+ 1196              	.LFB344:
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_DisablePVM1(void)
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1197              		.loc 1 595 1 is_stmt 1 view -0
+ 1198              		.cfi_startproc
+ 1199              		@ args = 0, pretend = 0, frame = 0
+ 1200              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1201              		@ link register save eliminated.
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(PWR->CR2, PWR_PVM_1);
+ 1202              		.loc 1 596 3 view .LVU279
+ 1203 0000 024A     		ldr	r2, .L105
+ 1204 0002 5368     		ldr	r3, [r2, #4]
+ 1205 0004 23F01003 		bic	r3, r3, #16
+ 1206 0008 5360     		str	r3, [r2, #4]
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1207              		.loc 1 597 1 is_stmt 0 view .LVU280
+ 1208 000a 7047     		bx	lr
+ 1209              	.L106:
+ 1210              		.align	2
+ 1211              	.L105:
+ 1212 000c 00700040 		.word	1073770496
+ 1213              		.cfi_endproc
+ 1214              	.LFE344:
+ 1216              		.section	.text.HAL_PWREx_EnablePVM2,"ax",%progbits
+ 1217              		.align	1
+ 1218              		.global	HAL_PWREx_EnablePVM2
+ 1219              		.syntax unified
+ 1220              		.thumb
+ 1221              		.thumb_func
+ 1223              	HAL_PWREx_EnablePVM2:
+ 1224              	.LFB345:
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #endif /* PWR_CR2_PVME1 */
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #if defined(PWR_CR2_PVME2)
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnablePVM2(void)
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1225              		.loc 1 607 1 is_stmt 1 view -0
+ 1226              		.cfi_startproc
+ 1227              		@ args = 0, pretend = 0, frame = 0
+ 1228              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cchjGo05.s 			page 34
+
+
+ 1229              		@ link register save eliminated.
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(PWR->CR2, PWR_PVM_2);
+ 1230              		.loc 1 608 3 view .LVU282
+ 1231 0000 024A     		ldr	r2, .L108
+ 1232 0002 5368     		ldr	r3, [r2, #4]
+ 1233 0004 43F02003 		orr	r3, r3, #32
+ 1234 0008 5360     		str	r3, [r2, #4]
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1235              		.loc 1 609 1 is_stmt 0 view .LVU283
+ 1236 000a 7047     		bx	lr
+ 1237              	.L109:
+ 1238              		.align	2
+ 1239              	.L108:
+ 1240 000c 00700040 		.word	1073770496
+ 1241              		.cfi_endproc
+ 1242              	.LFE345:
+ 1244              		.section	.text.HAL_PWREx_DisablePVM2,"ax",%progbits
+ 1245              		.align	1
+ 1246              		.global	HAL_PWREx_DisablePVM2
+ 1247              		.syntax unified
+ 1248              		.thumb
+ 1249              		.thumb_func
+ 1251              	HAL_PWREx_DisablePVM2:
+ 1252              	.LFB346:
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_DisablePVM2(void)
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1253              		.loc 1 616 1 is_stmt 1 view -0
+ 1254              		.cfi_startproc
+ 1255              		@ args = 0, pretend = 0, frame = 0
+ 1256              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1257              		@ link register save eliminated.
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(PWR->CR2, PWR_PVM_2);
+ 1258              		.loc 1 617 3 view .LVU285
+ 1259 0000 024A     		ldr	r2, .L111
+ 1260 0002 5368     		ldr	r3, [r2, #4]
+ 1261 0004 23F02003 		bic	r3, r3, #32
+ 1262 0008 5360     		str	r3, [r2, #4]
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1263              		.loc 1 618 1 is_stmt 0 view .LVU286
+ 1264 000a 7047     		bx	lr
+ 1265              	.L112:
+ 1266              		.align	2
+ 1267              	.L111:
+ 1268 000c 00700040 		.word	1073770496
+ 1269              		.cfi_endproc
+ 1270              	.LFE346:
+ 1272              		.section	.text.HAL_PWREx_EnablePVM3,"ax",%progbits
+ 1273              		.align	1
+ 1274              		.global	HAL_PWREx_EnablePVM3
+ 1275              		.syntax unified
+ 1276              		.thumb
+ 1277              		.thumb_func
+ARM GAS  /tmp/cchjGo05.s 			page 35
+
+
+ 1279              	HAL_PWREx_EnablePVM3:
+ 1280              	.LFB347:
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #endif /* PWR_CR2_PVME2 */
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnablePVM3(void)
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1281              		.loc 1 627 1 is_stmt 1 view -0
+ 1282              		.cfi_startproc
+ 1283              		@ args = 0, pretend = 0, frame = 0
+ 1284              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1285              		@ link register save eliminated.
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(PWR->CR2, PWR_PVM_3);
+ 1286              		.loc 1 628 3 view .LVU288
+ 1287 0000 024A     		ldr	r2, .L114
+ 1288 0002 5368     		ldr	r3, [r2, #4]
+ 1289 0004 43F04003 		orr	r3, r3, #64
+ 1290 0008 5360     		str	r3, [r2, #4]
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1291              		.loc 1 629 1 is_stmt 0 view .LVU289
+ 1292 000a 7047     		bx	lr
+ 1293              	.L115:
+ 1294              		.align	2
+ 1295              	.L114:
+ 1296 000c 00700040 		.word	1073770496
+ 1297              		.cfi_endproc
+ 1298              	.LFE347:
+ 1300              		.section	.text.HAL_PWREx_DisablePVM3,"ax",%progbits
+ 1301              		.align	1
+ 1302              		.global	HAL_PWREx_DisablePVM3
+ 1303              		.syntax unified
+ 1304              		.thumb
+ 1305              		.thumb_func
+ 1307              	HAL_PWREx_DisablePVM3:
+ 1308              	.LFB348:
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_DisablePVM3(void)
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1309              		.loc 1 636 1 is_stmt 1 view -0
+ 1310              		.cfi_startproc
+ 1311              		@ args = 0, pretend = 0, frame = 0
+ 1312              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1313              		@ link register save eliminated.
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(PWR->CR2, PWR_PVM_3);
+ 1314              		.loc 1 637 3 view .LVU291
+ 1315 0000 024A     		ldr	r2, .L117
+ 1316 0002 5368     		ldr	r3, [r2, #4]
+ 1317 0004 23F04003 		bic	r3, r3, #64
+ 1318 0008 5360     		str	r3, [r2, #4]
+ARM GAS  /tmp/cchjGo05.s 			page 36
+
+
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1319              		.loc 1 638 1 is_stmt 0 view .LVU292
+ 1320 000a 7047     		bx	lr
+ 1321              	.L118:
+ 1322              		.align	2
+ 1323              	.L117:
+ 1324 000c 00700040 		.word	1073770496
+ 1325              		.cfi_endproc
+ 1326              	.LFE348:
+ 1328              		.section	.text.HAL_PWREx_EnablePVM4,"ax",%progbits
+ 1329              		.align	1
+ 1330              		.global	HAL_PWREx_EnablePVM4
+ 1331              		.syntax unified
+ 1332              		.thumb
+ 1333              		.thumb_func
+ 1335              	HAL_PWREx_EnablePVM4:
+ 1336              	.LFB349:
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnablePVM4(void)
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1337              		.loc 1 646 1 is_stmt 1 view -0
+ 1338              		.cfi_startproc
+ 1339              		@ args = 0, pretend = 0, frame = 0
+ 1340              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1341              		@ link register save eliminated.
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(PWR->CR2, PWR_PVM_4);
+ 1342              		.loc 1 647 3 view .LVU294
+ 1343 0000 024A     		ldr	r2, .L120
+ 1344 0002 5368     		ldr	r3, [r2, #4]
+ 1345 0004 43F08003 		orr	r3, r3, #128
+ 1346 0008 5360     		str	r3, [r2, #4]
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1347              		.loc 1 648 1 is_stmt 0 view .LVU295
+ 1348 000a 7047     		bx	lr
+ 1349              	.L121:
+ 1350              		.align	2
+ 1351              	.L120:
+ 1352 000c 00700040 		.word	1073770496
+ 1353              		.cfi_endproc
+ 1354              	.LFE349:
+ 1356              		.section	.text.HAL_PWREx_DisablePVM4,"ax",%progbits
+ 1357              		.align	1
+ 1358              		.global	HAL_PWREx_DisablePVM4
+ 1359              		.syntax unified
+ 1360              		.thumb
+ 1361              		.thumb_func
+ 1363              	HAL_PWREx_DisablePVM4:
+ 1364              	.LFB350:
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ARM GAS  /tmp/cchjGo05.s 			page 37
+
+
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_DisablePVM4(void)
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1365              		.loc 1 655 1 is_stmt 1 view -0
+ 1366              		.cfi_startproc
+ 1367              		@ args = 0, pretend = 0, frame = 0
+ 1368              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1369              		@ link register save eliminated.
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(PWR->CR2, PWR_PVM_4);
+ 1370              		.loc 1 656 3 view .LVU297
+ 1371 0000 024A     		ldr	r2, .L123
+ 1372 0002 5368     		ldr	r3, [r2, #4]
+ 1373 0004 23F08003 		bic	r3, r3, #128
+ 1374 0008 5360     		str	r3, [r2, #4]
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1375              		.loc 1 657 1 is_stmt 0 view .LVU298
+ 1376 000a 7047     		bx	lr
+ 1377              	.L124:
+ 1378              		.align	2
+ 1379              	.L123:
+ 1380 000c 00700040 		.word	1073770496
+ 1381              		.cfi_endproc
+ 1382              	.LFE350:
+ 1384              		.section	.text.HAL_PWREx_ConfigPVM,"ax",%progbits
+ 1385              		.align	1
+ 1386              		.global	HAL_PWREx_ConfigPVM
+ 1387              		.syntax unified
+ 1388              		.thumb
+ 1389              		.thumb_func
+ 1391              	HAL_PWREx_ConfigPVM:
+ 1392              	.LVL98:
+ 1393              	.LFB351:
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Configure the Peripheral Voltage Monitoring (PVM).
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        PVM configuration information.
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note The API configures a single PVM according to the information contained
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *       in the input structure. To configure several PVMs, the API must be singly
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *       called for each PVM used.
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note Refer to the electrical characteristics of your device datasheet for
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         more details about the voltage thresholds corresponding to each
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         detection level and to each monitored supply.
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval HAL status
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1394              		.loc 1 675 1 is_stmt 1 view -0
+ 1395              		.cfi_startproc
+ 1396              		@ args = 0, pretend = 0, frame = 0
+ 1397              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1398              		@ link register save eliminated.
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1399              		.loc 1 676 3 view .LVU300
+ARM GAS  /tmp/cchjGo05.s 			page 38
+
+
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Check the parameters */
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
+ 1400              		.loc 1 679 3 view .LVU301
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
+ 1401              		.loc 1 680 3 view .LVU302
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Configure EXTI 35 to 38 interrupts if so required:
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****      scan through PVMType to detect which PVMx is set and
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****      configure the corresponding EXTI line accordingly. */
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   switch (sConfigPVM->PVMType)
+ 1402              		.loc 1 686 3 view .LVU303
+ 1403              		.loc 1 686 21 is_stmt 0 view .LVU304
+ 1404 0000 0368     		ldr	r3, [r0]
+ 1405              		.loc 1 686 3 view .LVU305
+ 1406 0002 402B     		cmp	r3, #64
+ 1407 0004 00F0B180 		beq	.L126
+ 1408 0008 3DD8     		bhi	.L127
+ 1409 000a 102B     		cmp	r3, #16
+ 1410 000c 76D0     		beq	.L128
+ 1411 000e 202B     		cmp	r3, #32
+ 1412 0010 37D1     		bne	.L148
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #if defined(PWR_CR2_PVME1)
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_PVM_1:
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM1_EXTI_DISABLE_IT();
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Configure interrupt mode */
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM1_EXTI_ENABLE_IT();
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Configure event mode */
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Configure the edge */
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       break;
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #endif /* PWR_CR2_PVME1 */
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ARM GAS  /tmp/cchjGo05.s 			page 39
+
+
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #if defined(PWR_CR2_PVME2)
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_PVM_2:
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
+ 1413              		.loc 1 724 7 is_stmt 1 view .LVU306
+ 1414 0012 754B     		ldr	r3, .L150
+ 1415 0014 5A6A     		ldr	r2, [r3, #36]
+ 1416 0016 22F01002 		bic	r2, r2, #16
+ 1417 001a 5A62     		str	r2, [r3, #36]
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM2_EXTI_DISABLE_IT();
+ 1418              		.loc 1 725 7 view .LVU307
+ 1419 001c 1A6A     		ldr	r2, [r3, #32]
+ 1420 001e 22F01002 		bic	r2, r2, #16
+ 1421 0022 1A62     		str	r2, [r3, #32]
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
+ 1422              		.loc 1 726 7 view .LVU308
+ 1423 0024 DA6A     		ldr	r2, [r3, #44]
+ 1424 0026 22F01002 		bic	r2, r2, #16
+ 1425 002a DA62     		str	r2, [r3, #44]
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
+ 1426              		.loc 1 727 7 view .LVU309
+ 1427 002c 9A6A     		ldr	r2, [r3, #40]
+ 1428 002e 22F01002 		bic	r2, r2, #16
+ 1429 0032 9A62     		str	r2, [r3, #40]
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Configure interrupt mode */
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+ 1430              		.loc 1 730 7 view .LVU310
+ 1431              		.loc 1 730 21 is_stmt 0 view .LVU311
+ 1432 0034 4368     		ldr	r3, [r0, #4]
+ 1433              		.loc 1 730 9 view .LVU312
+ 1434 0036 13F4803F 		tst	r3, #65536
+ 1435 003a 04D0     		beq	.L135
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM2_EXTI_ENABLE_IT();
+ 1436              		.loc 1 732 9 is_stmt 1 view .LVU313
+ 1437 003c 6A4A     		ldr	r2, .L150
+ 1438 003e 136A     		ldr	r3, [r2, #32]
+ 1439 0040 43F01003 		orr	r3, r3, #16
+ 1440 0044 1362     		str	r3, [r2, #32]
+ 1441              	.L135:
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Configure event mode */
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+ 1442              		.loc 1 736 7 view .LVU314
+ 1443              		.loc 1 736 21 is_stmt 0 view .LVU315
+ 1444 0046 4368     		ldr	r3, [r0, #4]
+ 1445              		.loc 1 736 9 view .LVU316
+ 1446 0048 13F4003F 		tst	r3, #131072
+ 1447 004c 04D0     		beq	.L136
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
+ 1448              		.loc 1 738 9 is_stmt 1 view .LVU317
+ 1449 004e 664A     		ldr	r2, .L150
+ 1450 0050 536A     		ldr	r3, [r2, #36]
+ 1451 0052 43F01003 		orr	r3, r3, #16
+ARM GAS  /tmp/cchjGo05.s 			page 40
+
+
+ 1452 0056 5362     		str	r3, [r2, #36]
+ 1453              	.L136:
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Configure the edge */
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+ 1454              		.loc 1 742 7 view .LVU318
+ 1455              		.loc 1 742 21 is_stmt 0 view .LVU319
+ 1456 0058 4368     		ldr	r3, [r0, #4]
+ 1457              		.loc 1 742 9 view .LVU320
+ 1458 005a 13F0010F 		tst	r3, #1
+ 1459 005e 04D0     		beq	.L137
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
+ 1460              		.loc 1 744 9 is_stmt 1 view .LVU321
+ 1461 0060 614A     		ldr	r2, .L150
+ 1462 0062 936A     		ldr	r3, [r2, #40]
+ 1463 0064 43F01003 		orr	r3, r3, #16
+ 1464 0068 9362     		str	r3, [r2, #40]
+ 1465              	.L137:
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+ 1466              		.loc 1 747 7 view .LVU322
+ 1467              		.loc 1 747 21 is_stmt 0 view .LVU323
+ 1468 006a 4368     		ldr	r3, [r0, #4]
+ 1469              		.loc 1 747 9 view .LVU324
+ 1470 006c 13F0020F 		tst	r3, #2
+ 1471 0070 00F0B480 		beq	.L145
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
+ 1472              		.loc 1 749 9 is_stmt 1 view .LVU325
+ 1473 0074 5C4A     		ldr	r2, .L150
+ 1474 0076 D36A     		ldr	r3, [r2, #44]
+ 1475 0078 43F01003 		orr	r3, r3, #16
+ 1476 007c D362     		str	r3, [r2, #44]
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1477              		.loc 1 676 21 is_stmt 0 view .LVU326
+ 1478 007e 0020     		movs	r0, #0
+ 1479              	.LVL99:
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1480              		.loc 1 676 21 view .LVU327
+ 1481 0080 7047     		bx	lr
+ 1482              	.LVL100:
+ 1483              	.L148:
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 1484              		.loc 1 686 3 view .LVU328
+ 1485 0082 0120     		movs	r0, #1
+ 1486              	.LVL101:
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 1487              		.loc 1 686 3 view .LVU329
+ 1488 0084 7047     		bx	lr
+ 1489              	.LVL102:
+ 1490              	.L127:
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 1491              		.loc 1 686 3 view .LVU330
+ 1492 0086 802B     		cmp	r3, #128
+ARM GAS  /tmp/cchjGo05.s 			page 41
+
+
+ 1493 0088 36D1     		bne	.L149
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       break;
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #endif /* PWR_CR2_PVME2 */
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_PVM_3:
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM3_EXTI_DISABLE_IT();
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Configure interrupt mode */
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM3_EXTI_ENABLE_IT();
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Configure event mode */
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Configure the edge */
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       break;
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     case PWR_PVM_4:
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
+ 1494              		.loc 1 787 7 is_stmt 1 view .LVU331
+ 1495 008a 574B     		ldr	r3, .L150
+ 1496 008c 5A6A     		ldr	r2, [r3, #36]
+ 1497 008e 22F04002 		bic	r2, r2, #64
+ 1498 0092 5A62     		str	r2, [r3, #36]
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM4_EXTI_DISABLE_IT();
+ 1499              		.loc 1 788 7 view .LVU332
+ 1500 0094 1A6A     		ldr	r2, [r3, #32]
+ 1501 0096 22F04002 		bic	r2, r2, #64
+ 1502 009a 1A62     		str	r2, [r3, #32]
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
+ 1503              		.loc 1 789 7 view .LVU333
+ 1504 009c DA6A     		ldr	r2, [r3, #44]
+ 1505 009e 22F04002 		bic	r2, r2, #64
+ 1506 00a2 DA62     		str	r2, [r3, #44]
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
+ 1507              		.loc 1 790 7 view .LVU334
+ 1508 00a4 9A6A     		ldr	r2, [r3, #40]
+ARM GAS  /tmp/cchjGo05.s 			page 42
+
+
+ 1509 00a6 22F04002 		bic	r2, r2, #64
+ 1510 00aa 9A62     		str	r2, [r3, #40]
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Configure interrupt mode */
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+ 1511              		.loc 1 793 7 view .LVU335
+ 1512              		.loc 1 793 21 is_stmt 0 view .LVU336
+ 1513 00ac 4368     		ldr	r3, [r0, #4]
+ 1514              		.loc 1 793 9 view .LVU337
+ 1515 00ae 13F4803F 		tst	r3, #65536
+ 1516 00b2 04D0     		beq	.L141
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM4_EXTI_ENABLE_IT();
+ 1517              		.loc 1 795 9 is_stmt 1 view .LVU338
+ 1518 00b4 4C4A     		ldr	r2, .L150
+ 1519 00b6 136A     		ldr	r3, [r2, #32]
+ 1520 00b8 43F04003 		orr	r3, r3, #64
+ 1521 00bc 1362     		str	r3, [r2, #32]
+ 1522              	.L141:
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Configure event mode */
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+ 1523              		.loc 1 799 7 view .LVU339
+ 1524              		.loc 1 799 21 is_stmt 0 view .LVU340
+ 1525 00be 4368     		ldr	r3, [r0, #4]
+ 1526              		.loc 1 799 9 view .LVU341
+ 1527 00c0 13F4003F 		tst	r3, #131072
+ 1528 00c4 04D0     		beq	.L142
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
+ 1529              		.loc 1 801 9 is_stmt 1 view .LVU342
+ 1530 00c6 484A     		ldr	r2, .L150
+ 1531 00c8 536A     		ldr	r3, [r2, #36]
+ 1532 00ca 43F04003 		orr	r3, r3, #64
+ 1533 00ce 5362     		str	r3, [r2, #36]
+ 1534              	.L142:
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       /* Configure the edge */
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+ 1535              		.loc 1 805 7 view .LVU343
+ 1536              		.loc 1 805 21 is_stmt 0 view .LVU344
+ 1537 00d0 4368     		ldr	r3, [r0, #4]
+ 1538              		.loc 1 805 9 view .LVU345
+ 1539 00d2 13F0010F 		tst	r3, #1
+ 1540 00d6 04D0     		beq	.L143
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
+ 1541              		.loc 1 807 9 is_stmt 1 view .LVU346
+ 1542 00d8 434A     		ldr	r2, .L150
+ 1543 00da 936A     		ldr	r3, [r2, #40]
+ 1544 00dc 43F04003 		orr	r3, r3, #64
+ 1545 00e0 9362     		str	r3, [r2, #40]
+ 1546              	.L143:
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ARM GAS  /tmp/cchjGo05.s 			page 43
+
+
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+ 1547              		.loc 1 810 7 view .LVU347
+ 1548              		.loc 1 810 21 is_stmt 0 view .LVU348
+ 1549 00e2 4368     		ldr	r3, [r0, #4]
+ 1550              		.loc 1 810 9 view .LVU349
+ 1551 00e4 13F0020F 		tst	r3, #2
+ 1552 00e8 7CD0     		beq	.L147
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****         __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
+ 1553              		.loc 1 812 9 is_stmt 1 view .LVU350
+ 1554 00ea 3F4A     		ldr	r2, .L150
+ 1555 00ec D36A     		ldr	r3, [r2, #44]
+ 1556 00ee 43F04003 		orr	r3, r3, #64
+ 1557 00f2 D362     		str	r3, [r2, #44]
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1558              		.loc 1 676 21 is_stmt 0 view .LVU351
+ 1559 00f4 0020     		movs	r0, #0
+ 1560              	.LVL103:
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1561              		.loc 1 676 21 view .LVU352
+ 1562 00f6 7047     		bx	lr
+ 1563              	.LVL104:
+ 1564              	.L149:
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 1565              		.loc 1 686 3 view .LVU353
+ 1566 00f8 0120     		movs	r0, #1
+ 1567              	.LVL105:
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 1568              		.loc 1 686 3 view .LVU354
+ 1569 00fa 7047     		bx	lr
+ 1570              	.LVL106:
+ 1571              	.L128:
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM1_EXTI_DISABLE_IT();
+ 1572              		.loc 1 691 7 is_stmt 1 view .LVU355
+ 1573 00fc 3A4B     		ldr	r3, .L150
+ 1574 00fe 5A6A     		ldr	r2, [r3, #36]
+ 1575 0100 22F00802 		bic	r2, r2, #8
+ 1576 0104 5A62     		str	r2, [r3, #36]
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
+ 1577              		.loc 1 692 7 view .LVU356
+ 1578 0106 1A6A     		ldr	r2, [r3, #32]
+ 1579 0108 22F00802 		bic	r2, r2, #8
+ 1580 010c 1A62     		str	r2, [r3, #32]
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
+ 1581              		.loc 1 693 7 view .LVU357
+ 1582 010e DA6A     		ldr	r2, [r3, #44]
+ 1583 0110 22F00802 		bic	r2, r2, #8
+ 1584 0114 DA62     		str	r2, [r3, #44]
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1585              		.loc 1 694 7 view .LVU358
+ 1586 0116 9A6A     		ldr	r2, [r3, #40]
+ 1587 0118 22F00802 		bic	r2, r2, #8
+ 1588 011c 9A62     		str	r2, [r3, #40]
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1589              		.loc 1 697 7 view .LVU359
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1590              		.loc 1 697 21 is_stmt 0 view .LVU360
+ARM GAS  /tmp/cchjGo05.s 			page 44
+
+
+ 1591 011e 4368     		ldr	r3, [r0, #4]
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1592              		.loc 1 697 9 view .LVU361
+ 1593 0120 13F4803F 		tst	r3, #65536
+ 1594 0124 04D0     		beq	.L132
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 1595              		.loc 1 699 9 is_stmt 1 view .LVU362
+ 1596 0126 304A     		ldr	r2, .L150
+ 1597 0128 136A     		ldr	r3, [r2, #32]
+ 1598 012a 43F00803 		orr	r3, r3, #8
+ 1599 012e 1362     		str	r3, [r2, #32]
+ 1600              	.L132:
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1601              		.loc 1 703 7 view .LVU363
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1602              		.loc 1 703 21 is_stmt 0 view .LVU364
+ 1603 0130 4368     		ldr	r3, [r0, #4]
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1604              		.loc 1 703 9 view .LVU365
+ 1605 0132 13F4003F 		tst	r3, #131072
+ 1606 0136 04D0     		beq	.L133
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 1607              		.loc 1 705 9 is_stmt 1 view .LVU366
+ 1608 0138 2B4A     		ldr	r2, .L150
+ 1609 013a 536A     		ldr	r3, [r2, #36]
+ 1610 013c 43F00803 		orr	r3, r3, #8
+ 1611 0140 5362     		str	r3, [r2, #36]
+ 1612              	.L133:
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1613              		.loc 1 709 7 view .LVU367
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1614              		.loc 1 709 21 is_stmt 0 view .LVU368
+ 1615 0142 4368     		ldr	r3, [r0, #4]
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1616              		.loc 1 709 9 view .LVU369
+ 1617 0144 13F0010F 		tst	r3, #1
+ 1618 0148 04D0     		beq	.L134
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 1619              		.loc 1 711 9 is_stmt 1 view .LVU370
+ 1620 014a 274A     		ldr	r2, .L150
+ 1621 014c 936A     		ldr	r3, [r2, #40]
+ 1622 014e 43F00803 		orr	r3, r3, #8
+ 1623 0152 9362     		str	r3, [r2, #40]
+ 1624              	.L134:
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1625              		.loc 1 714 7 view .LVU371
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1626              		.loc 1 714 21 is_stmt 0 view .LVU372
+ 1627 0154 4368     		ldr	r3, [r0, #4]
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1628              		.loc 1 714 9 view .LVU373
+ 1629 0156 13F0020F 		tst	r3, #2
+ 1630 015a 3DD0     		beq	.L144
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 1631              		.loc 1 716 9 is_stmt 1 view .LVU374
+ 1632 015c 224A     		ldr	r2, .L150
+ 1633 015e D36A     		ldr	r3, [r2, #44]
+ARM GAS  /tmp/cchjGo05.s 			page 45
+
+
+ 1634 0160 43F00803 		orr	r3, r3, #8
+ 1635 0164 D362     		str	r3, [r2, #44]
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1636              		.loc 1 676 21 is_stmt 0 view .LVU375
+ 1637 0166 0020     		movs	r0, #0
+ 1638              	.LVL107:
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1639              		.loc 1 676 21 view .LVU376
+ 1640 0168 7047     		bx	lr
+ 1641              	.LVL108:
+ 1642              	.L126:
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM3_EXTI_DISABLE_IT();
+ 1643              		.loc 1 756 7 is_stmt 1 view .LVU377
+ 1644 016a 1F4B     		ldr	r3, .L150
+ 1645 016c 5A6A     		ldr	r2, [r3, #36]
+ 1646 016e 22F02002 		bic	r2, r2, #32
+ 1647 0172 5A62     		str	r2, [r3, #36]
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
+ 1648              		.loc 1 757 7 view .LVU378
+ 1649 0174 1A6A     		ldr	r2, [r3, #32]
+ 1650 0176 22F02002 		bic	r2, r2, #32
+ 1651 017a 1A62     		str	r2, [r3, #32]
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
+ 1652              		.loc 1 758 7 view .LVU379
+ 1653 017c DA6A     		ldr	r2, [r3, #44]
+ 1654 017e 22F02002 		bic	r2, r2, #32
+ 1655 0182 DA62     		str	r2, [r3, #44]
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1656              		.loc 1 759 7 view .LVU380
+ 1657 0184 9A6A     		ldr	r2, [r3, #40]
+ 1658 0186 22F02002 		bic	r2, r2, #32
+ 1659 018a 9A62     		str	r2, [r3, #40]
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1660              		.loc 1 762 7 view .LVU381
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1661              		.loc 1 762 21 is_stmt 0 view .LVU382
+ 1662 018c 4368     		ldr	r3, [r0, #4]
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1663              		.loc 1 762 9 view .LVU383
+ 1664 018e 13F4803F 		tst	r3, #65536
+ 1665 0192 04D0     		beq	.L138
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 1666              		.loc 1 764 9 is_stmt 1 view .LVU384
+ 1667 0194 144A     		ldr	r2, .L150
+ 1668 0196 136A     		ldr	r3, [r2, #32]
+ 1669 0198 43F02003 		orr	r3, r3, #32
+ 1670 019c 1362     		str	r3, [r2, #32]
+ 1671              	.L138:
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1672              		.loc 1 768 7 view .LVU385
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1673              		.loc 1 768 21 is_stmt 0 view .LVU386
+ 1674 019e 4368     		ldr	r3, [r0, #4]
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1675              		.loc 1 768 9 view .LVU387
+ 1676 01a0 13F4003F 		tst	r3, #131072
+ 1677 01a4 04D0     		beq	.L139
+ARM GAS  /tmp/cchjGo05.s 			page 46
+
+
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 1678              		.loc 1 770 9 is_stmt 1 view .LVU388
+ 1679 01a6 104A     		ldr	r2, .L150
+ 1680 01a8 536A     		ldr	r3, [r2, #36]
+ 1681 01aa 43F02003 		orr	r3, r3, #32
+ 1682 01ae 5362     		str	r3, [r2, #36]
+ 1683              	.L139:
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1684              		.loc 1 774 7 view .LVU389
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1685              		.loc 1 774 21 is_stmt 0 view .LVU390
+ 1686 01b0 4368     		ldr	r3, [r0, #4]
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1687              		.loc 1 774 9 view .LVU391
+ 1688 01b2 13F0010F 		tst	r3, #1
+ 1689 01b6 04D0     		beq	.L140
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 1690              		.loc 1 776 9 is_stmt 1 view .LVU392
+ 1691 01b8 0B4A     		ldr	r2, .L150
+ 1692 01ba 936A     		ldr	r3, [r2, #40]
+ 1693 01bc 43F02003 		orr	r3, r3, #32
+ 1694 01c0 9362     		str	r3, [r2, #40]
+ 1695              	.L140:
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1696              		.loc 1 779 7 view .LVU393
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1697              		.loc 1 779 21 is_stmt 0 view .LVU394
+ 1698 01c2 4368     		ldr	r3, [r0, #4]
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       {
+ 1699              		.loc 1 779 9 view .LVU395
+ 1700 01c4 13F0020F 		tst	r3, #2
+ 1701 01c8 0AD0     		beq	.L146
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 1702              		.loc 1 781 9 is_stmt 1 view .LVU396
+ 1703 01ca 074A     		ldr	r2, .L150
+ 1704 01cc D36A     		ldr	r3, [r2, #44]
+ 1705 01ce 43F02003 		orr	r3, r3, #32
+ 1706 01d2 D362     		str	r3, [r2, #44]
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1707              		.loc 1 676 21 is_stmt 0 view .LVU397
+ 1708 01d4 0020     		movs	r0, #0
+ 1709              	.LVL109:
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1710              		.loc 1 676 21 view .LVU398
+ 1711 01d6 7047     		bx	lr
+ 1712              	.LVL110:
+ 1713              	.L144:
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1714              		.loc 1 676 21 view .LVU399
+ 1715 01d8 0020     		movs	r0, #0
+ 1716              	.LVL111:
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1717              		.loc 1 676 21 view .LVU400
+ 1718 01da 7047     		bx	lr
+ 1719              	.LVL112:
+ 1720              	.L145:
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ARM GAS  /tmp/cchjGo05.s 			page 47
+
+
+ 1721              		.loc 1 676 21 view .LVU401
+ 1722 01dc 0020     		movs	r0, #0
+ 1723              	.LVL113:
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1724              		.loc 1 676 21 view .LVU402
+ 1725 01de 7047     		bx	lr
+ 1726              	.LVL114:
+ 1727              	.L146:
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1728              		.loc 1 676 21 view .LVU403
+ 1729 01e0 0020     		movs	r0, #0
+ 1730              	.LVL115:
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1731              		.loc 1 676 21 view .LVU404
+ 1732 01e2 7047     		bx	lr
+ 1733              	.LVL116:
+ 1734              	.L147:
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 1735              		.loc 1 676 21 view .LVU405
+ 1736 01e4 0020     		movs	r0, #0
+ 1737              	.LVL117:
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       }
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       break;
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     default:
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       status = HAL_ERROR;
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****       break;
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   return status;
+ 1738              		.loc 1 821 3 is_stmt 1 view .LVU406
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1739              		.loc 1 822 1 is_stmt 0 view .LVU407
+ 1740 01e6 7047     		bx	lr
+ 1741              	.L151:
+ 1742              		.align	2
+ 1743              	.L150:
+ 1744 01e8 00040140 		.word	1073808384
+ 1745              		.cfi_endproc
+ 1746              	.LFE351:
+ 1748              		.section	.text.HAL_PWREx_EnableLowPowerRunMode,"ax",%progbits
+ 1749              		.align	1
+ 1750              		.global	HAL_PWREx_EnableLowPowerRunMode
+ 1751              		.syntax unified
+ 1752              		.thumb
+ 1753              		.thumb_func
+ 1755              	HAL_PWREx_EnableLowPowerRunMode:
+ 1756              	.LFB352:
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enter Low-power Run mode
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  In Low-power Run mode, all I/O pins keep the same state as in Run mode.
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        Additionally, the clock frequency must be reduced below 2 MHz.
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
+ARM GAS  /tmp/cchjGo05.s 			page 48
+
+
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnableLowPowerRunMode(void)
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1757              		.loc 1 836 1 is_stmt 1 view -0
+ 1758              		.cfi_startproc
+ 1759              		@ args = 0, pretend = 0, frame = 0
+ 1760              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1761              		@ link register save eliminated.
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Set Regulator parameter */
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(PWR->CR1, PWR_CR1_LPR);
+ 1762              		.loc 1 838 3 view .LVU409
+ 1763 0000 024A     		ldr	r2, .L153
+ 1764 0002 1368     		ldr	r3, [r2]
+ 1765 0004 43F48043 		orr	r3, r3, #16384
+ 1766 0008 1360     		str	r3, [r2]
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1767              		.loc 1 839 1 is_stmt 0 view .LVU410
+ 1768 000a 7047     		bx	lr
+ 1769              	.L154:
+ 1770              		.align	2
+ 1771              	.L153:
+ 1772 000c 00700040 		.word	1073770496
+ 1773              		.cfi_endproc
+ 1774              	.LFE352:
+ 1776              		.section	.text.HAL_PWREx_DisableLowPowerRunMode,"ax",%progbits
+ 1777              		.align	1
+ 1778              		.global	HAL_PWREx_DisableLowPowerRunMode
+ 1779              		.syntax unified
+ 1780              		.thumb
+ 1781              		.thumb_func
+ 1783              	HAL_PWREx_DisableLowPowerRunMode:
+ 1784              	.LFB353:
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Exit Low-power Run mode.
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        returns HAL_TIMEOUT status). The system clock frequency can then be
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        increased above 2 MHz.
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval HAL Status
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1785              		.loc 1 851 1 is_stmt 1 view -0
+ 1786              		.cfi_startproc
+ 1787              		@ args = 0, pretend = 0, frame = 0
+ 1788              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1789              		@ link register save eliminated.
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   uint32_t wait_loop_index;
+ 1790              		.loc 1 852 3 view .LVU412
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Clear LPR bit */
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
+ 1791              		.loc 1 855 3 view .LVU413
+ARM GAS  /tmp/cchjGo05.s 			page 49
+
+
+ 1792 0000 124A     		ldr	r2, .L161
+ 1793 0002 1368     		ldr	r3, [r2]
+ 1794 0004 23F48043 		bic	r3, r3, #16384
+ 1795 0008 1360     		str	r3, [r2]
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Wait until REGLPF is reset */
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U));
+ 1796              		.loc 1 858 3 view .LVU414
+ 1797              		.loc 1 858 67 is_stmt 0 view .LVU415
+ 1798 000a 114B     		ldr	r3, .L161+4
+ 1799 000c 1B68     		ldr	r3, [r3]
+ 1800 000e 02F14672 		add	r2, r2, #51904512
+ 1801 0012 02F55B32 		add	r2, r2, #224256
+ 1802 0016 02F28322 		addw	r2, r2, #643
+ 1803 001a A2FB0323 		umull	r2, r3, r2, r3
+ 1804 001e 9B0C     		lsrs	r3, r3, #18
+ 1805              		.loc 1 858 19 view .LVU416
+ 1806 0020 3222     		movs	r2, #50
+ 1807 0022 02FB03F3 		mul	r3, r2, r3
+ 1808              	.LVL118:
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
+ 1809              		.loc 1 859 3 is_stmt 1 view .LVU417
+ 1810              		.loc 1 859 9 is_stmt 0 view .LVU418
+ 1811 0026 00E0     		b	.L156
+ 1812              	.L158:
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     wait_loop_index--;
+ 1813              		.loc 1 861 5 is_stmt 1 view .LVU419
+ 1814              		.loc 1 861 20 is_stmt 0 view .LVU420
+ 1815 0028 013B     		subs	r3, r3, #1
+ 1816              	.LVL119:
+ 1817              	.L156:
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
+ 1818              		.loc 1 859 53 is_stmt 1 view .LVU421
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
+ 1819              		.loc 1 859 11 is_stmt 0 view .LVU422
+ 1820 002a 084A     		ldr	r2, .L161
+ 1821 002c 5269     		ldr	r2, [r2, #20]
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
+ 1822              		.loc 1 859 53 view .LVU423
+ 1823 002e 12F4007F 		tst	r2, #512
+ 1824 0032 01D0     		beq	.L157
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
+ 1825              		.loc 1 859 53 discriminator 1 view .LVU424
+ 1826 0034 002B     		cmp	r3, #0
+ 1827 0036 F7D1     		bne	.L158
+ 1828              	.L157:
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
+ 1829              		.loc 1 863 3 is_stmt 1 view .LVU425
+ 1830              		.loc 1 863 7 is_stmt 0 view .LVU426
+ 1831 0038 044B     		ldr	r3, .L161
+ 1832              	.LVL120:
+ 1833              		.loc 1 863 7 view .LVU427
+ 1834 003a 5B69     		ldr	r3, [r3, #20]
+ 1835              		.loc 1 863 6 view .LVU428
+ 1836 003c 13F4007F 		tst	r3, #512
+ARM GAS  /tmp/cchjGo05.s 			page 50
+
+
+ 1837 0040 01D1     		bne	.L160
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     return HAL_TIMEOUT;
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   return HAL_OK;
+ 1838              		.loc 1 868 10 view .LVU429
+ 1839 0042 0020     		movs	r0, #0
+ 1840 0044 7047     		bx	lr
+ 1841              	.L160:
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 1842              		.loc 1 865 12 view .LVU430
+ 1843 0046 0320     		movs	r0, #3
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1844              		.loc 1 869 1 view .LVU431
+ 1845 0048 7047     		bx	lr
+ 1846              	.L162:
+ 1847 004a 00BF     		.align	2
+ 1848              	.L161:
+ 1849 004c 00700040 		.word	1073770496
+ 1850 0050 00000000 		.word	SystemCoreClock
+ 1851              		.cfi_endproc
+ 1852              	.LFE353:
+ 1854              		.section	.text.HAL_PWREx_EnterSTOP0Mode,"ax",%progbits
+ 1855              		.align	1
+ 1856              		.global	HAL_PWREx_EnterSTOP0Mode
+ 1857              		.syntax unified
+ 1858              		.thumb
+ 1859              		.thumb_func
+ 1861              	HAL_PWREx_EnterSTOP0Mode:
+ 1862              	.LVL121:
+ 1863              	.LFB354:
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enter Stop 0 mode.
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  In Stop 0 mode, main and low voltage regulators are ON.
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  In Stop 0 mode, all I/O pins keep the same state as in Run mode.
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  All clocks in the VCORE domain are stopped; the PLL, the HSI
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        and the HSE oscillators are disabled. Some peripherals with the wakeup capability
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the H
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is pr
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        only to the peripheral requesting it.
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        SRAM1, SRAM2 and register contents are preserved.
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        The BOR is available.
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         is set; the HSI oscillator is selected if STOPWUCK is cleared.
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  By keeping the internal regulator ON during Stop 0 mode, the consumption
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         is higher although the startup time is reduced.
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
+ARM GAS  /tmp/cchjGo05.s 			page 51
+
+
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1864              		.loc 1 895 1 is_stmt 1 view -0
+ 1865              		.cfi_startproc
+ 1866              		@ args = 0, pretend = 0, frame = 0
+ 1867              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1868              		@ link register save eliminated.
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Check the parameters */
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+ 1869              		.loc 1 897 3 view .LVU433
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Stop 0 mode with Main Regulator */
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
+ 1870              		.loc 1 900 3 view .LVU434
+ 1871 0000 0B4A     		ldr	r2, .L167
+ 1872 0002 1368     		ldr	r3, [r2]
+ 1873 0004 23F00703 		bic	r3, r3, #7
+ 1874 0008 1360     		str	r3, [r2]
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Set SLEEPDEEP bit of Cortex System Control Register */
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+ 1875              		.loc 1 903 3 view .LVU435
+ 1876 000a 0A4A     		ldr	r2, .L167+4
+ 1877 000c 1369     		ldr	r3, [r2, #16]
+ 1878 000e 43F00403 		orr	r3, r3, #4
+ 1879 0012 1361     		str	r3, [r2, #16]
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Select Stop mode entry --------------------------------------------------*/
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   if(STOPEntry == PWR_STOPENTRY_WFI)
+ 1880              		.loc 1 906 3 view .LVU436
+ 1881              		.loc 1 906 5 is_stmt 0 view .LVU437
+ 1882 0014 0128     		cmp	r0, #1
+ 1883 0016 08D0     		beq	.L166
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* Request Wait For Interrupt */
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __WFI();
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   else
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* Request Wait For Event */
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __SEV();
+ 1884              		.loc 1 914 5 is_stmt 1 view .LVU438
+ 1885              		.syntax unified
+ 1886              	@ 914 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c" 1
+ 1887 0018 40BF     		sev
+ 1888              	@ 0 "" 2
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __WFE();
+ 1889              		.loc 1 915 5 view .LVU439
+ 1890              	@ 915 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c" 1
+ 1891 001a 20BF     		wfe
+ 1892              	@ 0 "" 2
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __WFE();
+ 1893              		.loc 1 916 5 view .LVU440
+ 1894              	@ 916 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c" 1
+ 1895 001c 20BF     		wfe
+ 1896              	@ 0 "" 2
+ 1897              		.thumb
+ 1898              		.syntax unified
+ARM GAS  /tmp/cchjGo05.s 			page 52
+
+
+ 1899              	.L165:
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+ 1900              		.loc 1 920 3 view .LVU441
+ 1901 001e 054A     		ldr	r2, .L167+4
+ 1902 0020 1369     		ldr	r3, [r2, #16]
+ 1903 0022 23F00403 		bic	r3, r3, #4
+ 1904 0026 1361     		str	r3, [r2, #16]
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1905              		.loc 1 921 1 is_stmt 0 view .LVU442
+ 1906 0028 7047     		bx	lr
+ 1907              	.L166:
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 1908              		.loc 1 909 5 is_stmt 1 view .LVU443
+ 1909              		.syntax unified
+ 1910              	@ 909 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c" 1
+ 1911 002a 30BF     		wfi
+ 1912              	@ 0 "" 2
+ 1913              		.thumb
+ 1914              		.syntax unified
+ 1915 002c F7E7     		b	.L165
+ 1916              	.L168:
+ 1917 002e 00BF     		.align	2
+ 1918              	.L167:
+ 1919 0030 00700040 		.word	1073770496
+ 1920 0034 00ED00E0 		.word	-536810240
+ 1921              		.cfi_endproc
+ 1922              	.LFE354:
+ 1924              		.section	.text.HAL_PWREx_EnterSTOP1Mode,"ax",%progbits
+ 1925              		.align	1
+ 1926              		.global	HAL_PWREx_EnterSTOP1Mode
+ 1927              		.syntax unified
+ 1928              		.thumb
+ 1929              		.thumb_func
+ 1931              	HAL_PWREx_EnterSTOP1Mode:
+ 1932              	.LVL122:
+ 1933              	.LFB355:
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enter Stop 1 mode.
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  In Stop 1 mode, only low power voltage regulator is ON.
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  In Stop 1 mode, all I/O pins keep the same state as in Run mode.
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  All clocks in the VCORE domain are stopped; the PLL, the HSI
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        and the HSE oscillators are disabled. Some peripherals with the wakeup capability
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the H
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is pr
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        only to the peripheral requesting it.
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        SRAM1, SRAM2 and register contents are preserved.
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        The BOR is available.
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *         is set.
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  Due to low power mode, an additional startup delay is incurred when waking up from Stop 
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
+ARM GAS  /tmp/cchjGo05.s 			page 53
+
+
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 1934              		.loc 1 946 1 view -0
+ 1935              		.cfi_startproc
+ 1936              		@ args = 0, pretend = 0, frame = 0
+ 1937              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1938              		@ link register save eliminated.
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Check the parameters */
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+ 1939              		.loc 1 948 3 view .LVU445
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Stop 1 mode with Low-Power Regulator */
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
+ 1940              		.loc 1 951 3 view .LVU446
+ 1941 0000 0C4A     		ldr	r2, .L173
+ 1942 0002 1368     		ldr	r3, [r2]
+ 1943 0004 23F00703 		bic	r3, r3, #7
+ 1944 0008 43F00103 		orr	r3, r3, #1
+ 1945 000c 1360     		str	r3, [r2]
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Set SLEEPDEEP bit of Cortex System Control Register */
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+ 1946              		.loc 1 954 3 view .LVU447
+ 1947 000e 0A4A     		ldr	r2, .L173+4
+ 1948 0010 1369     		ldr	r3, [r2, #16]
+ 1949 0012 43F00403 		orr	r3, r3, #4
+ 1950 0016 1361     		str	r3, [r2, #16]
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Select Stop mode entry --------------------------------------------------*/
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   if(STOPEntry == PWR_STOPENTRY_WFI)
+ 1951              		.loc 1 957 3 view .LVU448
+ 1952              		.loc 1 957 5 is_stmt 0 view .LVU449
+ 1953 0018 0128     		cmp	r0, #1
+ 1954 001a 08D0     		beq	.L172
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* Request Wait For Interrupt */
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __WFI();
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   else
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* Request Wait For Event */
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __SEV();
+ 1955              		.loc 1 965 5 is_stmt 1 view .LVU450
+ 1956              		.syntax unified
+ 1957              	@ 965 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c" 1
+ 1958 001c 40BF     		sev
+ 1959              	@ 0 "" 2
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __WFE();
+ 1960              		.loc 1 966 5 view .LVU451
+ 1961              	@ 966 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c" 1
+ 1962 001e 20BF     		wfe
+ 1963              	@ 0 "" 2
+ARM GAS  /tmp/cchjGo05.s 			page 54
+
+
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __WFE();
+ 1964              		.loc 1 967 5 view .LVU452
+ 1965              	@ 967 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c" 1
+ 1966 0020 20BF     		wfe
+ 1967              	@ 0 "" 2
+ 1968              		.thumb
+ 1969              		.syntax unified
+ 1970              	.L171:
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+ 1971              		.loc 1 971 3 view .LVU453
+ 1972 0022 054A     		ldr	r2, .L173+4
+ 1973 0024 1369     		ldr	r3, [r2, #16]
+ 1974 0026 23F00403 		bic	r3, r3, #4
+ 1975 002a 1361     		str	r3, [r2, #16]
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 1976              		.loc 1 972 1 is_stmt 0 view .LVU454
+ 1977 002c 7047     		bx	lr
+ 1978              	.L172:
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 1979              		.loc 1 960 5 is_stmt 1 view .LVU455
+ 1980              		.syntax unified
+ 1981              	@ 960 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c" 1
+ 1982 002e 30BF     		wfi
+ 1983              	@ 0 "" 2
+ 1984              		.thumb
+ 1985              		.syntax unified
+ 1986 0030 F7E7     		b	.L171
+ 1987              	.L174:
+ 1988 0032 00BF     		.align	2
+ 1989              	.L173:
+ 1990 0034 00700040 		.word	1073770496
+ 1991 0038 00ED00E0 		.word	-536810240
+ 1992              		.cfi_endproc
+ 1993              	.LFE355:
+ 1995              		.section	.text.HAL_PWREx_EnterSHUTDOWNMode,"ax",%progbits
+ 1996              		.align	1
+ 1997              		.global	HAL_PWREx_EnterSHUTDOWNMode
+ 1998              		.syntax unified
+ 1999              		.thumb
+ 2000              		.thumb_func
+ 2002              	HAL_PWREx_EnterSHUTDOWNMode:
+ 2003              	.LFB356:
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enter Shutdown mode.
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        off. The voltage regulator is disabled and Vcore domain is powered off.
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        The BOR is not available.
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog s
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+ARM GAS  /tmp/cchjGo05.s 			page 55
+
+
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSHUTDOWNMode(void)
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 2004              		.loc 1 987 1 view -0
+ 2005              		.cfi_startproc
+ 2006              		@ args = 0, pretend = 0, frame = 0
+ 2007              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2008              		@ link register save eliminated.
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Set Shutdown mode */
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
+ 2009              		.loc 1 990 3 view .LVU457
+ 2010 0000 064A     		ldr	r2, .L176
+ 2011 0002 1368     		ldr	r3, [r2]
+ 2012 0004 23F00703 		bic	r3, r3, #7
+ 2013 0008 43F00403 		orr	r3, r3, #4
+ 2014 000c 1360     		str	r3, [r2]
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Set SLEEPDEEP bit of Cortex System Control Register */
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+ 2015              		.loc 1 993 3 view .LVU458
+ 2016 000e 044A     		ldr	r2, .L176+4
+ 2017 0010 1369     		ldr	r3, [r2, #16]
+ 2018 0012 43F00403 		orr	r3, r3, #4
+ 2019 0016 1361     		str	r3, [r2, #16]
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /* This option is used to ensure that store operations are completed */
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #if defined ( __CC_ARM)
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   __force_stores();
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #endif
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Request Wait For Interrupt */
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   __WFI();
+ 2020              		.loc 1 1000 3 view .LVU459
+ 2021              		.syntax unified
+ 2022              	@ 1000 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c" 1
+ 2023 0018 30BF     		wfi
+ 2024              	@ 0 "" 2
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 2025              		.loc 1 1001 1 is_stmt 0 view .LVU460
+ 2026              		.thumb
+ 2027              		.syntax unified
+ 2028 001a 7047     		bx	lr
+ 2029              	.L177:
+ 2030              		.align	2
+ 2031              	.L176:
+ 2032 001c 00700040 		.word	1073770496
+ 2033 0020 00ED00E0 		.word	-536810240
+ 2034              		.cfi_endproc
+ 2035              	.LFE356:
+ 2037              		.section	.text.HAL_PWREx_PVM1Callback,"ax",%progbits
+ 2038              		.align	1
+ 2039              		.weak	HAL_PWREx_PVM1Callback
+ 2040              		.syntax unified
+ 2041              		.thumb
+ 2042              		.thumb_func
+ 2044              	HAL_PWREx_PVM1Callback:
+ 2045              	.LFB358:
+ARM GAS  /tmp/cchjGo05.s 			page 56
+
+
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief This function handles the PWR PVD/PVMx interrupt request.
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note This API should be called under the PVD_PVM_IRQHandler().
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_PVD_PVM_IRQHandler(void)
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Check PWR exti flag */
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0U)
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* PWR PVD interrupt user callback */
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     HAL_PWR_PVDCallback();
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* Clear PVD exti pending bit */
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Next, successively check PVMx exti flags */
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #if defined(PWR_CR2_PVME1)
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U)
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* PWR PVM1 interrupt user callback */
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     HAL_PWREx_PVM1Callback();
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* Clear PVM1 exti pending bit */
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #endif /* PWR_CR2_PVME1 */
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #if defined(PWR_CR2_PVME2)
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0U)
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* PWR PVM2 interrupt user callback */
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     HAL_PWREx_PVM2Callback();
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* Clear PVM2 exti pending bit */
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #endif /* PWR_CR2_PVME2 */
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U)
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* PWR PVM3 interrupt user callback */
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     HAL_PWREx_PVM3Callback();
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* Clear PVM3 exti pending bit */
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0U)
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* PWR PVM4 interrupt user callback */
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     HAL_PWREx_PVM4Callback();
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     /* Clear PVM4 exti pending bit */
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****     __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
+1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ARM GAS  /tmp/cchjGo05.s 			page 57
+
+
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #if defined(PWR_CR2_PVME1)
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief PWR PVM1 interrupt callback
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** __weak void HAL_PWREx_PVM1Callback(void)
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 2046              		.loc 1 1068 1 is_stmt 1 view -0
+ 2047              		.cfi_startproc
+ 2048              		@ args = 0, pretend = 0, frame = 0
+ 2049              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2050              		@ link register save eliminated.
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* NOTE : This function should not be modified; when the callback is needed,
+1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****             HAL_PWREx_PVM1Callback() API can be implemented in the user file
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****    */
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 2051              		.loc 1 1072 1 view .LVU462
+ 2052 0000 7047     		bx	lr
+ 2053              		.cfi_endproc
+ 2054              	.LFE358:
+ 2056              		.section	.text.HAL_PWREx_PVM2Callback,"ax",%progbits
+ 2057              		.align	1
+ 2058              		.weak	HAL_PWREx_PVM2Callback
+ 2059              		.syntax unified
+ 2060              		.thumb
+ 2061              		.thumb_func
+ 2063              	HAL_PWREx_PVM2Callback:
+ 2064              	.LFB359:
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #endif /* PWR_CR2_PVME1 */
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #if defined(PWR_CR2_PVME2)
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief PWR PVM2 interrupt callback
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** __weak void HAL_PWREx_PVM2Callback(void)
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 2065              		.loc 1 1081 1 view -0
+ 2066              		.cfi_startproc
+ 2067              		@ args = 0, pretend = 0, frame = 0
+ 2068              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2069              		@ link register save eliminated.
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* NOTE : This function should not be modified; when the callback is needed,
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****             HAL_PWREx_PVM2Callback() API can be implemented in the user file
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****    */
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 2070              		.loc 1 1085 1 view .LVU464
+ 2071 0000 7047     		bx	lr
+ 2072              		.cfi_endproc
+ 2073              	.LFE359:
+ 2075              		.section	.text.HAL_PWREx_PVM3Callback,"ax",%progbits
+ 2076              		.align	1
+ 2077              		.weak	HAL_PWREx_PVM3Callback
+ 2078              		.syntax unified
+ARM GAS  /tmp/cchjGo05.s 			page 58
+
+
+ 2079              		.thumb
+ 2080              		.thumb_func
+ 2082              	HAL_PWREx_PVM3Callback:
+ 2083              	.LFB360:
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #endif /* PWR_CR2_PVME2 */
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief PWR PVM3 interrupt callback
+1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** __weak void HAL_PWREx_PVM3Callback(void)
+1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 2084              		.loc 1 1093 1 view -0
+ 2085              		.cfi_startproc
+ 2086              		@ args = 0, pretend = 0, frame = 0
+ 2087              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2088              		@ link register save eliminated.
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* NOTE : This function should not be modified; when the callback is needed,
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****             HAL_PWREx_PVM3Callback() API can be implemented in the user file
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****    */
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 2089              		.loc 1 1097 1 view .LVU466
+ 2090 0000 7047     		bx	lr
+ 2091              		.cfi_endproc
+ 2092              	.LFE360:
+ 2094              		.section	.text.HAL_PWREx_PVM4Callback,"ax",%progbits
+ 2095              		.align	1
+ 2096              		.weak	HAL_PWREx_PVM4Callback
+ 2097              		.syntax unified
+ 2098              		.thumb
+ 2099              		.thumb_func
+ 2101              	HAL_PWREx_PVM4Callback:
+ 2102              	.LFB361:
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief PWR PVM4 interrupt callback
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** __weak void HAL_PWREx_PVM4Callback(void)
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 2103              		.loc 1 1104 1 view -0
+ 2104              		.cfi_startproc
+ 2105              		@ args = 0, pretend = 0, frame = 0
+ 2106              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2107              		@ link register save eliminated.
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* NOTE : This function should not be modified; when the callback is needed,
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****             HAL_PWREx_PVM4Callback() API can be implemented in the user file
+1107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****    */
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 2108              		.loc 1 1108 1 view .LVU468
+ 2109 0000 7047     		bx	lr
+ 2110              		.cfi_endproc
+ 2111              	.LFE361:
+ 2113              		.section	.text.HAL_PWREx_PVD_PVM_IRQHandler,"ax",%progbits
+ 2114              		.align	1
+ 2115              		.global	HAL_PWREx_PVD_PVM_IRQHandler
+ 2116              		.syntax unified
+ARM GAS  /tmp/cchjGo05.s 			page 59
+
+
+ 2117              		.thumb
+ 2118              		.thumb_func
+ 2120              	HAL_PWREx_PVD_PVM_IRQHandler:
+ 2121              	.LFB357:
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Check PWR exti flag */
+ 2122              		.loc 1 1012 1 view -0
+ 2123              		.cfi_startproc
+ 2124              		@ args = 0, pretend = 0, frame = 0
+ 2125              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2126 0000 08B5     		push	{r3, lr}
+ 2127              	.LCFI0:
+ 2128              		.cfi_def_cfa_offset 8
+ 2129              		.cfi_offset 3, -8
+ 2130              		.cfi_offset 14, -4
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2131              		.loc 1 1014 3 view .LVU470
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2132              		.loc 1 1014 6 is_stmt 0 view .LVU471
+ 2133 0002 1C4B     		ldr	r3, .L194
+ 2134 0004 5B69     		ldr	r3, [r3, #20]
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2135              		.loc 1 1014 5 view .LVU472
+ 2136 0006 13F4803F 		tst	r3, #65536
+ 2137 000a 14D1     		bne	.L189
+ 2138              	.L183:
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2139              		.loc 1 1024 3 is_stmt 1 view .LVU473
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2140              		.loc 1 1024 6 is_stmt 0 view .LVU474
+ 2141 000c 194B     		ldr	r3, .L194
+ 2142 000e 5B6B     		ldr	r3, [r3, #52]
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2143              		.loc 1 1024 5 view .LVU475
+ 2144 0010 13F0080F 		tst	r3, #8
+ 2145 0014 16D1     		bne	.L190
+ 2146              	.L184:
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2147              		.loc 1 1034 3 is_stmt 1 view .LVU476
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2148              		.loc 1 1034 6 is_stmt 0 view .LVU477
+ 2149 0016 174B     		ldr	r3, .L194
+ 2150 0018 5B6B     		ldr	r3, [r3, #52]
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2151              		.loc 1 1034 5 view .LVU478
+ 2152 001a 13F0100F 		tst	r3, #16
+ 2153 001e 17D1     		bne	.L191
+ 2154              	.L185:
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2155              		.loc 1 1043 3 is_stmt 1 view .LVU479
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2156              		.loc 1 1043 6 is_stmt 0 view .LVU480
+ 2157 0020 144B     		ldr	r3, .L194
+ 2158 0022 5B6B     		ldr	r3, [r3, #52]
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2159              		.loc 1 1043 5 view .LVU481
+ 2160 0024 13F0200F 		tst	r3, #32
+ 2161 0028 18D1     		bne	.L192
+ARM GAS  /tmp/cchjGo05.s 			page 60
+
+
+ 2162              	.L186:
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2163              		.loc 1 1051 3 is_stmt 1 view .LVU482
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2164              		.loc 1 1051 6 is_stmt 0 view .LVU483
+ 2165 002a 124B     		ldr	r3, .L194
+ 2166 002c 5B6B     		ldr	r3, [r3, #52]
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   {
+ 2167              		.loc 1 1051 5 view .LVU484
+ 2168 002e 13F0400F 		tst	r3, #64
+ 2169 0032 19D1     		bne	.L193
+ 2170              	.L182:
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 2171              		.loc 1 1059 1 view .LVU485
+ 2172 0034 08BD     		pop	{r3, pc}
+ 2173              	.L189:
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 2174              		.loc 1 1017 5 is_stmt 1 view .LVU486
+ 2175 0036 FFF7FEFF 		bl	HAL_PWR_PVDCallback
+ 2176              	.LVL123:
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 2177              		.loc 1 1020 5 view .LVU487
+ 2178 003a 0E4B     		ldr	r3, .L194
+ 2179 003c 4FF48032 		mov	r2, #65536
+ 2180 0040 5A61     		str	r2, [r3, #20]
+ 2181 0042 E3E7     		b	.L183
+ 2182              	.L190:
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 2183              		.loc 1 1027 5 view .LVU488
+ 2184 0044 FFF7FEFF 		bl	HAL_PWREx_PVM1Callback
+ 2185              	.LVL124:
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 2186              		.loc 1 1030 5 view .LVU489
+ 2187 0048 0A4B     		ldr	r3, .L194
+ 2188 004a 0822     		movs	r2, #8
+ 2189 004c 5A63     		str	r2, [r3, #52]
+ 2190 004e E2E7     		b	.L184
+ 2191              	.L191:
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 2192              		.loc 1 1037 5 view .LVU490
+ 2193 0050 FFF7FEFF 		bl	HAL_PWREx_PVM2Callback
+ 2194              	.LVL125:
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 2195              		.loc 1 1040 5 view .LVU491
+ 2196 0054 074B     		ldr	r3, .L194
+ 2197 0056 1022     		movs	r2, #16
+ 2198 0058 5A63     		str	r2, [r3, #52]
+ 2199 005a E1E7     		b	.L185
+ 2200              	.L192:
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 2201              		.loc 1 1046 5 view .LVU492
+ 2202 005c FFF7FEFF 		bl	HAL_PWREx_PVM3Callback
+ 2203              	.LVL126:
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 2204              		.loc 1 1049 5 view .LVU493
+ 2205 0060 044B     		ldr	r3, .L194
+ 2206 0062 2022     		movs	r2, #32
+ARM GAS  /tmp/cchjGo05.s 			page 61
+
+
+ 2207 0064 5A63     		str	r2, [r3, #52]
+ 2208 0066 E0E7     		b	.L186
+ 2209              	.L193:
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 2210              		.loc 1 1054 5 view .LVU494
+ 2211 0068 FFF7FEFF 		bl	HAL_PWREx_PVM4Callback
+ 2212              	.LVL127:
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   }
+ 2213              		.loc 1 1057 5 view .LVU495
+ 2214 006c 014B     		ldr	r3, .L194
+ 2215 006e 4022     		movs	r2, #64
+ 2216 0070 5A63     		str	r2, [r3, #52]
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+ 2217              		.loc 1 1059 1 is_stmt 0 view .LVU496
+ 2218 0072 DFE7     		b	.L182
+ 2219              	.L195:
+ 2220              		.align	2
+ 2221              	.L194:
+ 2222 0074 00040140 		.word	1073808384
+ 2223              		.cfi_endproc
+ 2224              	.LFE357:
+ 2226              		.section	.text.HAL_PWREx_EnableUCPDStandbyMode,"ax",%progbits
+ 2227              		.align	1
+ 2228              		.global	HAL_PWREx_EnableUCPDStandbyMode
+ 2229              		.syntax unified
+ 2230              		.thumb
+ 2231              		.thumb_func
+ 2233              	HAL_PWREx_EnableUCPDStandbyMode:
+ 2234              	.LFB362:
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #if defined(PWR_CR3_UCPD_STDBY)
+1111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enable UCPD configuration memorization in Standby.
+1113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnableUCPDStandbyMode(void)
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 2235              		.loc 1 1116 1 is_stmt 1 view -0
+ 2236              		.cfi_startproc
+ 2237              		@ args = 0, pretend = 0, frame = 0
+ 2238              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2239              		@ link register save eliminated.
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Memorize UCPD configuration when entering standby mode */
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
+ 2240              		.loc 1 1118 3 view .LVU498
+ 2241 0000 024A     		ldr	r2, .L197
+ 2242 0002 9368     		ldr	r3, [r2, #8]
+ 2243 0004 43F40053 		orr	r3, r3, #8192
+ 2244 0008 9360     		str	r3, [r2, #8]
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 2245              		.loc 1 1119 1 is_stmt 0 view .LVU499
+ 2246 000a 7047     		bx	lr
+ 2247              	.L198:
+ 2248              		.align	2
+ 2249              	.L197:
+ 2250 000c 00700040 		.word	1073770496
+ 2251              		.cfi_endproc
+ARM GAS  /tmp/cchjGo05.s 			page 62
+
+
+ 2252              	.LFE362:
+ 2254              		.section	.text.HAL_PWREx_DisableUCPDStandbyMode,"ax",%progbits
+ 2255              		.align	1
+ 2256              		.global	HAL_PWREx_DisableUCPDStandbyMode
+ 2257              		.syntax unified
+ 2258              		.thumb
+ 2259              		.thumb_func
+ 2261              	HAL_PWREx_DisableUCPDStandbyMode:
+ 2262              	.LFB363:
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Disable UCPD configuration memorization in Standby.
+1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note  This function must be called on exiting the Standby mode and before any UCPD
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        configuration update.
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+1126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_DisableUCPDStandbyMode(void)
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 2263              		.loc 1 1128 1 is_stmt 1 view -0
+ 2264              		.cfi_startproc
+ 2265              		@ args = 0, pretend = 0, frame = 0
+ 2266              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2267              		@ link register save eliminated.
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Write 0 immediately after Standby exit when using UCPD,
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****      and before writing any UCPD registers */
+1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
+ 2268              		.loc 1 1131 3 view .LVU501
+ 2269 0000 024A     		ldr	r2, .L200
+ 2270 0002 9368     		ldr	r3, [r2, #8]
+ 2271 0004 23F40053 		bic	r3, r3, #8192
+ 2272 0008 9360     		str	r3, [r2, #8]
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 2273              		.loc 1 1132 1 is_stmt 0 view .LVU502
+ 2274 000a 7047     		bx	lr
+ 2275              	.L201:
+ 2276              		.align	2
+ 2277              	.L200:
+ 2278 000c 00700040 		.word	1073770496
+ 2279              		.cfi_endproc
+ 2280              	.LFE363:
+ 2282              		.section	.text.HAL_PWREx_EnableUCPDDeadBattery,"ax",%progbits
+ 2283              		.align	1
+ 2284              		.global	HAL_PWREx_EnableUCPDDeadBattery
+ 2285              		.syntax unified
+ 2286              		.thumb
+ 2287              		.thumb_func
+ 2289              	HAL_PWREx_EnableUCPDDeadBattery:
+ 2290              	.LFB364:
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #endif /* PWR_CR3_UCPD_STDBY */
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** #if defined(PWR_CR3_UCPD_DBDIS)
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Enable the USB Type-C dead battery pull-down behavior
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        on UCPDx_CC1 and UCPDx_CC2 pins
+1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_EnableUCPDDeadBattery(void)
+ARM GAS  /tmp/cchjGo05.s 			page 63
+
+
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 2291              		.loc 1 1142 1 is_stmt 1 view -0
+ 2292              		.cfi_startproc
+ 2293              		@ args = 0, pretend = 0, frame = 0
+ 2294              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2295              		@ link register save eliminated.
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Write 0 to enable the USB Type-C dead battery pull-down behavior */
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
+ 2296              		.loc 1 1144 3 view .LVU504
+ 2297 0000 024A     		ldr	r2, .L203
+ 2298 0002 9368     		ldr	r3, [r2, #8]
+ 2299 0004 23F48043 		bic	r3, r3, #16384
+ 2300 0008 9360     		str	r3, [r2, #8]
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 2301              		.loc 1 1145 1 is_stmt 0 view .LVU505
+ 2302 000a 7047     		bx	lr
+ 2303              	.L204:
+ 2304              		.align	2
+ 2305              	.L203:
+ 2306 000c 00700040 		.word	1073770496
+ 2307              		.cfi_endproc
+ 2308              	.LFE364:
+ 2310              		.section	.text.HAL_PWREx_DisableUCPDDeadBattery,"ax",%progbits
+ 2311              		.align	1
+ 2312              		.global	HAL_PWREx_DisableUCPDDeadBattery
+ 2313              		.syntax unified
+ 2314              		.thumb
+ 2315              		.thumb_func
+ 2317              	HAL_PWREx_DisableUCPDDeadBattery:
+ 2318              	.LFB365:
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** 
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** /**
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @brief Disable the USB Type-C dead battery pull-down behavior
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *        on UCPDx_CC1 and UCPDx_CC2 pins
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @note After exiting reset, the USB Type-C dead battery behavior will be enabled,
+1151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *       which may have a pull-down effect on CC1 and CC2 pins.
+1152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *       It is recommended to disable it in all cases, either to stop this pull-down
+1153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *       or to hand over control to the UCPD (which should therefore be
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   *       initialized before doing the disable).
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   * @retval None
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   */
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** void HAL_PWREx_DisableUCPDDeadBattery(void)
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** {
+ 2319              		.loc 1 1158 1 is_stmt 1 view -0
+ 2320              		.cfi_startproc
+ 2321              		@ args = 0, pretend = 0, frame = 0
+ 2322              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2323              		@ link register save eliminated.
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   /* Write 1 to disable the USB Type-C dead battery pull-down behavior */
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ****   SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
+ 2324              		.loc 1 1160 3 view .LVU507
+ 2325 0000 024A     		ldr	r2, .L206
+ 2326 0002 9368     		ldr	r3, [r2, #8]
+ 2327 0004 43F48043 		orr	r3, r3, #16384
+ 2328 0008 9360     		str	r3, [r2, #8]
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c **** }
+ 2329              		.loc 1 1161 1 is_stmt 0 view .LVU508
+ARM GAS  /tmp/cchjGo05.s 			page 64
+
+
+ 2330 000a 7047     		bx	lr
+ 2331              	.L207:
+ 2332              		.align	2
+ 2333              	.L206:
+ 2334 000c 00700040 		.word	1073770496
+ 2335              		.cfi_endproc
+ 2336              	.LFE365:
+ 2338              		.text
+ 2339              	.Letext0:
+ 2340              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 2341              		.file 3 "Drivers/CMSIS/Include/core_cm4.h"
+ 2342              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 2343              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 2344              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"
+ 2345              		.file 7 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
+ 2346              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h"
+ARM GAS  /tmp/cchjGo05.s 			page 65
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_pwr_ex.c
+     /tmp/cchjGo05.s:21     .text.HAL_PWREx_GetVoltageRange:00000000 $t
+     /tmp/cchjGo05.s:27     .text.HAL_PWREx_GetVoltageRange:00000000 HAL_PWREx_GetVoltageRange
+     /tmp/cchjGo05.s:58     .text.HAL_PWREx_GetVoltageRange:00000020 $d
+     /tmp/cchjGo05.s:63     .text.HAL_PWREx_ControlVoltageScaling:00000000 $t
+     /tmp/cchjGo05.s:69     .text.HAL_PWREx_ControlVoltageScaling:00000000 HAL_PWREx_ControlVoltageScaling
+     /tmp/cchjGo05.s:273    .text.HAL_PWREx_ControlVoltageScaling:00000100 $d
+     /tmp/cchjGo05.s:280    .text.HAL_PWREx_EnableBatteryCharging:00000000 $t
+     /tmp/cchjGo05.s:286    .text.HAL_PWREx_EnableBatteryCharging:00000000 HAL_PWREx_EnableBatteryCharging
+     /tmp/cchjGo05.s:310    .text.HAL_PWREx_EnableBatteryCharging:00000018 $d
+     /tmp/cchjGo05.s:315    .text.HAL_PWREx_DisableBatteryCharging:00000000 $t
+     /tmp/cchjGo05.s:321    .text.HAL_PWREx_DisableBatteryCharging:00000000 HAL_PWREx_DisableBatteryCharging
+     /tmp/cchjGo05.s:338    .text.HAL_PWREx_DisableBatteryCharging:0000000c $d
+     /tmp/cchjGo05.s:343    .text.HAL_PWREx_EnableInternalWakeUpLine:00000000 $t
+     /tmp/cchjGo05.s:349    .text.HAL_PWREx_EnableInternalWakeUpLine:00000000 HAL_PWREx_EnableInternalWakeUpLine
+     /tmp/cchjGo05.s:366    .text.HAL_PWREx_EnableInternalWakeUpLine:0000000c $d
+     /tmp/cchjGo05.s:371    .text.HAL_PWREx_DisableInternalWakeUpLine:00000000 $t
+     /tmp/cchjGo05.s:377    .text.HAL_PWREx_DisableInternalWakeUpLine:00000000 HAL_PWREx_DisableInternalWakeUpLine
+     /tmp/cchjGo05.s:394    .text.HAL_PWREx_DisableInternalWakeUpLine:0000000c $d
+     /tmp/cchjGo05.s:399    .text.HAL_PWREx_EnableGPIOPullUp:00000000 $t
+     /tmp/cchjGo05.s:405    .text.HAL_PWREx_EnableGPIOPullUp:00000000 HAL_PWREx_EnableGPIOPullUp
+     /tmp/cchjGo05.s:421    .text.HAL_PWREx_EnableGPIOPullUp:00000008 $d
+     /tmp/cchjGo05.s:573    .text.HAL_PWREx_EnableGPIOPullUp:000000b4 $d
+     /tmp/cchjGo05.s:578    .text.HAL_PWREx_DisableGPIOPullUp:00000000 $t
+     /tmp/cchjGo05.s:584    .text.HAL_PWREx_DisableGPIOPullUp:00000000 HAL_PWREx_DisableGPIOPullUp
+     /tmp/cchjGo05.s:600    .text.HAL_PWREx_DisableGPIOPullUp:00000008 $d
+     /tmp/cchjGo05.s:720    .text.HAL_PWREx_DisableGPIOPullUp:00000088 $d
+     /tmp/cchjGo05.s:725    .text.HAL_PWREx_EnableGPIOPullDown:00000000 $t
+     /tmp/cchjGo05.s:731    .text.HAL_PWREx_EnableGPIOPullDown:00000000 HAL_PWREx_EnableGPIOPullDown
+     /tmp/cchjGo05.s:747    .text.HAL_PWREx_EnableGPIOPullDown:00000008 $d
+     /tmp/cchjGo05.s:898    .text.HAL_PWREx_EnableGPIOPullDown:000000b8 $d
+     /tmp/cchjGo05.s:903    .text.HAL_PWREx_DisableGPIOPullDown:00000000 $t
+     /tmp/cchjGo05.s:909    .text.HAL_PWREx_DisableGPIOPullDown:00000000 HAL_PWREx_DisableGPIOPullDown
+     /tmp/cchjGo05.s:925    .text.HAL_PWREx_DisableGPIOPullDown:00000008 $d
+     /tmp/cchjGo05.s:1044   .text.HAL_PWREx_DisableGPIOPullDown:00000084 $d
+     /tmp/cchjGo05.s:1049   .text.HAL_PWREx_EnablePullUpPullDownConfig:00000000 $t
+     /tmp/cchjGo05.s:1055   .text.HAL_PWREx_EnablePullUpPullDownConfig:00000000 HAL_PWREx_EnablePullUpPullDownConfig
+     /tmp/cchjGo05.s:1072   .text.HAL_PWREx_EnablePullUpPullDownConfig:0000000c $d
+     /tmp/cchjGo05.s:1077   .text.HAL_PWREx_DisablePullUpPullDownConfig:00000000 $t
+     /tmp/cchjGo05.s:1083   .text.HAL_PWREx_DisablePullUpPullDownConfig:00000000 HAL_PWREx_DisablePullUpPullDownConfig
+     /tmp/cchjGo05.s:1100   .text.HAL_PWREx_DisablePullUpPullDownConfig:0000000c $d
+     /tmp/cchjGo05.s:1105   .text.HAL_PWREx_EnableSRAM2ContentRetention:00000000 $t
+     /tmp/cchjGo05.s:1111   .text.HAL_PWREx_EnableSRAM2ContentRetention:00000000 HAL_PWREx_EnableSRAM2ContentRetention
+     /tmp/cchjGo05.s:1128   .text.HAL_PWREx_EnableSRAM2ContentRetention:0000000c $d
+     /tmp/cchjGo05.s:1133   .text.HAL_PWREx_DisableSRAM2ContentRetention:00000000 $t
+     /tmp/cchjGo05.s:1139   .text.HAL_PWREx_DisableSRAM2ContentRetention:00000000 HAL_PWREx_DisableSRAM2ContentRetention
+     /tmp/cchjGo05.s:1156   .text.HAL_PWREx_DisableSRAM2ContentRetention:0000000c $d
+     /tmp/cchjGo05.s:1161   .text.HAL_PWREx_EnablePVM1:00000000 $t
+     /tmp/cchjGo05.s:1167   .text.HAL_PWREx_EnablePVM1:00000000 HAL_PWREx_EnablePVM1
+     /tmp/cchjGo05.s:1184   .text.HAL_PWREx_EnablePVM1:0000000c $d
+     /tmp/cchjGo05.s:1189   .text.HAL_PWREx_DisablePVM1:00000000 $t
+     /tmp/cchjGo05.s:1195   .text.HAL_PWREx_DisablePVM1:00000000 HAL_PWREx_DisablePVM1
+     /tmp/cchjGo05.s:1212   .text.HAL_PWREx_DisablePVM1:0000000c $d
+     /tmp/cchjGo05.s:1217   .text.HAL_PWREx_EnablePVM2:00000000 $t
+     /tmp/cchjGo05.s:1223   .text.HAL_PWREx_EnablePVM2:00000000 HAL_PWREx_EnablePVM2
+     /tmp/cchjGo05.s:1240   .text.HAL_PWREx_EnablePVM2:0000000c $d
+ARM GAS  /tmp/cchjGo05.s 			page 66
+
+
+     /tmp/cchjGo05.s:1245   .text.HAL_PWREx_DisablePVM2:00000000 $t
+     /tmp/cchjGo05.s:1251   .text.HAL_PWREx_DisablePVM2:00000000 HAL_PWREx_DisablePVM2
+     /tmp/cchjGo05.s:1268   .text.HAL_PWREx_DisablePVM2:0000000c $d
+     /tmp/cchjGo05.s:1273   .text.HAL_PWREx_EnablePVM3:00000000 $t
+     /tmp/cchjGo05.s:1279   .text.HAL_PWREx_EnablePVM3:00000000 HAL_PWREx_EnablePVM3
+     /tmp/cchjGo05.s:1296   .text.HAL_PWREx_EnablePVM3:0000000c $d
+     /tmp/cchjGo05.s:1301   .text.HAL_PWREx_DisablePVM3:00000000 $t
+     /tmp/cchjGo05.s:1307   .text.HAL_PWREx_DisablePVM3:00000000 HAL_PWREx_DisablePVM3
+     /tmp/cchjGo05.s:1324   .text.HAL_PWREx_DisablePVM3:0000000c $d
+     /tmp/cchjGo05.s:1329   .text.HAL_PWREx_EnablePVM4:00000000 $t
+     /tmp/cchjGo05.s:1335   .text.HAL_PWREx_EnablePVM4:00000000 HAL_PWREx_EnablePVM4
+     /tmp/cchjGo05.s:1352   .text.HAL_PWREx_EnablePVM4:0000000c $d
+     /tmp/cchjGo05.s:1357   .text.HAL_PWREx_DisablePVM4:00000000 $t
+     /tmp/cchjGo05.s:1363   .text.HAL_PWREx_DisablePVM4:00000000 HAL_PWREx_DisablePVM4
+     /tmp/cchjGo05.s:1380   .text.HAL_PWREx_DisablePVM4:0000000c $d
+     /tmp/cchjGo05.s:1385   .text.HAL_PWREx_ConfigPVM:00000000 $t
+     /tmp/cchjGo05.s:1391   .text.HAL_PWREx_ConfigPVM:00000000 HAL_PWREx_ConfigPVM
+     /tmp/cchjGo05.s:1744   .text.HAL_PWREx_ConfigPVM:000001e8 $d
+     /tmp/cchjGo05.s:1749   .text.HAL_PWREx_EnableLowPowerRunMode:00000000 $t
+     /tmp/cchjGo05.s:1755   .text.HAL_PWREx_EnableLowPowerRunMode:00000000 HAL_PWREx_EnableLowPowerRunMode
+     /tmp/cchjGo05.s:1772   .text.HAL_PWREx_EnableLowPowerRunMode:0000000c $d
+     /tmp/cchjGo05.s:1777   .text.HAL_PWREx_DisableLowPowerRunMode:00000000 $t
+     /tmp/cchjGo05.s:1783   .text.HAL_PWREx_DisableLowPowerRunMode:00000000 HAL_PWREx_DisableLowPowerRunMode
+     /tmp/cchjGo05.s:1849   .text.HAL_PWREx_DisableLowPowerRunMode:0000004c $d
+     /tmp/cchjGo05.s:1855   .text.HAL_PWREx_EnterSTOP0Mode:00000000 $t
+     /tmp/cchjGo05.s:1861   .text.HAL_PWREx_EnterSTOP0Mode:00000000 HAL_PWREx_EnterSTOP0Mode
+     /tmp/cchjGo05.s:1919   .text.HAL_PWREx_EnterSTOP0Mode:00000030 $d
+     /tmp/cchjGo05.s:1925   .text.HAL_PWREx_EnterSTOP1Mode:00000000 $t
+     /tmp/cchjGo05.s:1931   .text.HAL_PWREx_EnterSTOP1Mode:00000000 HAL_PWREx_EnterSTOP1Mode
+     /tmp/cchjGo05.s:1990   .text.HAL_PWREx_EnterSTOP1Mode:00000034 $d
+     /tmp/cchjGo05.s:1996   .text.HAL_PWREx_EnterSHUTDOWNMode:00000000 $t
+     /tmp/cchjGo05.s:2002   .text.HAL_PWREx_EnterSHUTDOWNMode:00000000 HAL_PWREx_EnterSHUTDOWNMode
+     /tmp/cchjGo05.s:2032   .text.HAL_PWREx_EnterSHUTDOWNMode:0000001c $d
+     /tmp/cchjGo05.s:2038   .text.HAL_PWREx_PVM1Callback:00000000 $t
+     /tmp/cchjGo05.s:2044   .text.HAL_PWREx_PVM1Callback:00000000 HAL_PWREx_PVM1Callback
+     /tmp/cchjGo05.s:2057   .text.HAL_PWREx_PVM2Callback:00000000 $t
+     /tmp/cchjGo05.s:2063   .text.HAL_PWREx_PVM2Callback:00000000 HAL_PWREx_PVM2Callback
+     /tmp/cchjGo05.s:2076   .text.HAL_PWREx_PVM3Callback:00000000 $t
+     /tmp/cchjGo05.s:2082   .text.HAL_PWREx_PVM3Callback:00000000 HAL_PWREx_PVM3Callback
+     /tmp/cchjGo05.s:2095   .text.HAL_PWREx_PVM4Callback:00000000 $t
+     /tmp/cchjGo05.s:2101   .text.HAL_PWREx_PVM4Callback:00000000 HAL_PWREx_PVM4Callback
+     /tmp/cchjGo05.s:2114   .text.HAL_PWREx_PVD_PVM_IRQHandler:00000000 $t
+     /tmp/cchjGo05.s:2120   .text.HAL_PWREx_PVD_PVM_IRQHandler:00000000 HAL_PWREx_PVD_PVM_IRQHandler
+     /tmp/cchjGo05.s:2222   .text.HAL_PWREx_PVD_PVM_IRQHandler:00000074 $d
+     /tmp/cchjGo05.s:2227   .text.HAL_PWREx_EnableUCPDStandbyMode:00000000 $t
+     /tmp/cchjGo05.s:2233   .text.HAL_PWREx_EnableUCPDStandbyMode:00000000 HAL_PWREx_EnableUCPDStandbyMode
+     /tmp/cchjGo05.s:2250   .text.HAL_PWREx_EnableUCPDStandbyMode:0000000c $d
+     /tmp/cchjGo05.s:2255   .text.HAL_PWREx_DisableUCPDStandbyMode:00000000 $t
+     /tmp/cchjGo05.s:2261   .text.HAL_PWREx_DisableUCPDStandbyMode:00000000 HAL_PWREx_DisableUCPDStandbyMode
+     /tmp/cchjGo05.s:2278   .text.HAL_PWREx_DisableUCPDStandbyMode:0000000c $d
+     /tmp/cchjGo05.s:2283   .text.HAL_PWREx_EnableUCPDDeadBattery:00000000 $t
+     /tmp/cchjGo05.s:2289   .text.HAL_PWREx_EnableUCPDDeadBattery:00000000 HAL_PWREx_EnableUCPDDeadBattery
+     /tmp/cchjGo05.s:2306   .text.HAL_PWREx_EnableUCPDDeadBattery:0000000c $d
+     /tmp/cchjGo05.s:2311   .text.HAL_PWREx_DisableUCPDDeadBattery:00000000 $t
+     /tmp/cchjGo05.s:2317   .text.HAL_PWREx_DisableUCPDDeadBattery:00000000 HAL_PWREx_DisableUCPDDeadBattery
+     /tmp/cchjGo05.s:2334   .text.HAL_PWREx_DisableUCPDDeadBattery:0000000c $d
+     /tmp/cchjGo05.s:428    .text.HAL_PWREx_EnableGPIOPullUp:0000000f $d
+ARM GAS  /tmp/cchjGo05.s 			page 67
+
+
+     /tmp/cchjGo05.s:428    .text.HAL_PWREx_EnableGPIOPullUp:00000010 $t
+     /tmp/cchjGo05.s:607    .text.HAL_PWREx_DisableGPIOPullUp:0000000f $d
+     /tmp/cchjGo05.s:607    .text.HAL_PWREx_DisableGPIOPullUp:00000010 $t
+     /tmp/cchjGo05.s:754    .text.HAL_PWREx_EnableGPIOPullDown:0000000f $d
+     /tmp/cchjGo05.s:754    .text.HAL_PWREx_EnableGPIOPullDown:00000010 $t
+     /tmp/cchjGo05.s:932    .text.HAL_PWREx_DisableGPIOPullDown:0000000f $d
+     /tmp/cchjGo05.s:932    .text.HAL_PWREx_DisableGPIOPullDown:00000010 $t
+
+UNDEFINED SYMBOLS
+SystemCoreClock
+HAL_PWR_PVDCallback
diff --git a/squeow_sw/build/stm32g4xx_hal_pwr_ex.o b/squeow_sw/build/stm32g4xx_hal_pwr_ex.o
new file mode 100644
index 0000000000000000000000000000000000000000..792c3b8d1b48994b23d7c98245239fef88152d29
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HcmV?d00001

diff --git a/squeow_sw/build/stm32g4xx_hal_rcc.d b/squeow_sw/build/stm32g4xx_hal_rcc.d
new file mode 100644
index 0000000..19bcda0
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_rcc.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_rcc.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_rcc.lst b/squeow_sw/build/stm32g4xx_hal_rcc.lst
new file mode 100644
index 0000000..eb24aee
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_rcc.lst
@@ -0,0 +1,5028 @@
+ARM GAS  /tmp/ccu53ZgF.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_rcc.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c"
+  20              		.section	.text.RCC_GetSysClockFreqFromPLLSource,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	RCC_GetSysClockFreqFromPLLSource:
+  27              	.LFB344:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @file    stm32g4xx_hal_rcc.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief   RCC HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *          functionalities of the Reset and Clock Control (RCC) peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *           + Peripheral Control functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   @verbatim
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   ==============================================================================
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                       ##### RCC specific features #####
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   ==============================================================================
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     [..]
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       After reset the device is running from High Speed Internal oscillator
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       (16 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       and I-Cache are disabled, and all peripherals are off except internal
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       SRAM, Flash and JTAG.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses:
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           all peripherals mapped on these buses are running at HSI speed.
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       (+) All GPIOs are in analog mode, except the JTAG pins which
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           are assigned to be used for debug purpose.
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     [..]
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       Once the device started from reset, the user application has to:
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       (+) Configure the clock source to be used to drive the System clock
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           (if the application needs higher frequency/performance)
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       (+) Configure the System clock frequency and Flash settings
+ARM GAS  /tmp/ccu53ZgF.s 			page 2
+
+
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       (+) Configure the AHB and APB buses prescalers
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       (+) Enable the clock for the peripheral(s) to be used
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       (+) Configure the clock source(s) for peripherals which clocks are not
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           derived from the System clock (USB, RNG, USART, LPUART, FDCAN, some TIMERs,
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           UCPD, I2S, I2C, LPTIM, ADC, QSPI)
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   @endverbatim
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   ******************************************************************************
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @attention
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * Copyright (c) 2019 STMicroelectronics.
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * All rights reserved.
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * the root directory of this software component.
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   ******************************************************************************
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /* Includes ------------------------------------------------------------------*/
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #include "stm32g4xx_hal.h"
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @{
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /** @defgroup RCC RCC
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief RCC HAL module driver
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @{
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #ifdef HAL_RCC_MODULE_ENABLED
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /* Private typedef -----------------------------------------------------------*/
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /* Private define ------------------------------------------------------------*/
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /** @defgroup RCC_Private_Constants RCC Private Constants
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****  * @{
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****  */
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #define HSI_TIMEOUT_VALUE          2U                /* 2 ms (minimum Tick + 1) */
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #define LSI_TIMEOUT_VALUE          2U                /* 2 ms (minimum Tick + 1) */
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #define HSI48_TIMEOUT_VALUE        2U                /* 2 ms (minimum Tick + 1) */
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #define PLL_TIMEOUT_VALUE          2U                /* 2 ms (minimum Tick + 1) */
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #define CLOCKSWITCH_TIMEOUT_VALUE  5000U             /* 5 s    */
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @}
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /* Private macro -------------------------------------------------------------*/
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /** @defgroup RCC_Private_Macros RCC Private Macros
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @{
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__)   ((__RCC_MCOx__) & GPIO_PIN_MASK)
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__)    (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPI
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_G
+ARM GAS  /tmp/ccu53ZgF.s 			page 3
+
+
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__)  (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @}
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /* Private variables ---------------------------------------------------------*/
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /* Private function prototypes -----------------------------------------------*/
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /** @defgroup RCC_Private_Functions RCC Private Functions
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @{
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** static uint32_t          RCC_GetSysClockFreqFromPLLSource(void);
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @}
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /* Exported functions --------------------------------------------------------*/
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions RCC Exported Functions
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @{
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *  @brief    Initialization and Configuration functions
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   @verbatim
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****  ===============================================================================
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            ##### Initialization and de-initialization functions #####
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****  ===============================================================================
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     [..]
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       This section provides functions allowing to configure the internal and external oscillators
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****        and APB2).
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     [..] Internal/external clock and PLL configuration
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              the PLL as System clock source.
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              clock source.
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              through the PLL as System clock source. Can be used also optionally as RTC clock sourc
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (+) PLL (clocked by HSI, HSE) providing up to three independent output clocks:
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            (++) The first output is used to generate the high speed system clock (up to 170 MHz).
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            (++) The second output is used to generate the clock for the USB (48 MHz),
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                 the QSPI (<= 48 MHz), the FDCAN, the SAI and the I2S.
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            (++) The third output is used to generate a clock for ADC
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
+ARM GAS  /tmp/ccu53ZgF.s 			page 4
+
+
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             (HSE used directly or through PLL as System clock source), the System clock
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              is automatically switched to HSI and an interrupt is generated if enabled.
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              exception vector.
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (+) MCO (microcontroller clock output): used to output LSI, HSI, LSE, HSE,
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              main PLL clock, system clock or RC48 clock (through a configurable prescaler) on PA8 p
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     [..] System, AHB and APB buses clocks configuration
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              HSE and main PLL.
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              The AHB clock (HCLK) is derived from System clock through configurable
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              prescaler and used to clock the CPU, memory and peripherals mapped
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              from AHB clock through configurable prescalers and used to clock
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              the peripherals mapped on these buses. You can use
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                 divided by 2 to 31.
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                 You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                 to configure this clock.
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            (+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                 to work correctly, while the RNG peripheral requires a frequency
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                 equal or lower than to 48 MHz. This clock is derived of the main PLL
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                 through PLLQ divider. You have to enable the peripheral clock and use
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                 HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            (+@) IWDG clock which is always the LSI clock.
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 170 MHz.
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              The clock source frequency should be adapted depending on the device voltage range
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****              as listed in the Reference Manual "Clock source frequency versus voltage scaling" chap
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   @endverbatim
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            Table 1. HCLK clock frequency for STM32G4xx devices
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            +----------------------------------------------------------------------------+
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            | Latency         |            HCLK clock frequency (MHz)                    |
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |                 |----------------------------------------------------------|
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |                 |  voltage range 1  |  voltage range 1  | voltage range 2  |
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |                 | boost mode 1.28 V | normal mode 1.2 V |     1.0 V        |
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |-----------------|-------------------|-------------------|------------------|
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |0WS(1 CPU cycles)|    HCLK <= 34     |    HCLK <= 30     |    HCLK <= 13    |
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |-----------------|-------------------|-------------------|------------------|
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |1WS(2 CPU cycles)|    HCLK <= 68     |    HCLK <= 60     |    HCLK <= 26    |
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |-----------------|-------------------|-------------------|------------------|
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |2WS(3 CPU cycles)|    HCLK <= 102    |    HCLK <= 90     |        -         |
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |-----------------|-------------------|-------------------|------------------|
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |3WS(4 CPU cycles)|    HCLK <= 136    |    HCLK <= 120    |        -         |
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |-----------------|-------------------|-------------------|------------------|
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            |4WS(5 CPU cycles)|    HCLK <= 170    |    HCLK <= 150    |        -         |
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****            +----------------------------------------------------------------------------+
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @{
+ARM GAS  /tmp/ccu53ZgF.s 			page 5
+
+
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Reset the RCC clock configuration to the default reset state.
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   The default reset state of the clock configuration is given below:
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            - HSI ON and used as system clock source
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            - HSE, PLL OFF
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            - AHB, APB1 and APB2 prescaler set to 1.
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            - CSS, MCO1 OFF
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            - All interrupts disabled
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            - All interrupt and reset flags cleared
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   This function doesn't modify the configuration of the
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            - Peripheral clocks
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            - LSI, LSE and RTC clocks
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval HAL status
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_DeInit(void)
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t tickstart;
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get Start Tick*/
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   tickstart = HAL_GetTick();
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Set HSION bit to the reset value */
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   SET_BIT(RCC->CR, RCC_CR_HSION);
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Wait till HSI is ready */
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       return HAL_TIMEOUT;
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****  /* Set HSITRIM[6:0] bits to the reset value */
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   SET_BIT(RCC->ICSCR, RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos);
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get Start Tick*/
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   tickstart = HAL_GetTick();
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Reset CFGR register (HSI is selected as system clock source) */
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC->CFGR = 0x00000001u;
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Wait till HSI is ready */
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       return HAL_TIMEOUT;
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Update the SystemCoreClock global variable */
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   SystemCoreClock = HSI_VALUE;
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Adapt Systick interrupt period */
+ARM GAS  /tmp/ccu53ZgF.s 			page 6
+
+
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (HAL_InitTick(uwTickPrio) != HAL_OK)
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     return HAL_ERROR;
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC->CR = RCC_CR_HSION;
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Then again to HSEBYP in case bypass was enabled */
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC->CR = RCC_CR_HSION;
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get Start Tick*/
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   tickstart = HAL_GetTick();
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Wait till PLL is OFF */
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       return HAL_TIMEOUT;
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* once PLL is OFF, reset PLLCFGR register to default value */
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC->PLLCFGR = RCC_PLLCFGR_PLLN_4;
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Disable all interrupts */
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   CLEAR_REG(RCC->CIER);
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Clear all interrupt flags */
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Clear all reset flags */
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   return HAL_OK;
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Initialize the RCC Oscillators according to the specified parameters in the
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         RCC_OscInitTypeDef.
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         contains the configuration information for the RCC Oscillators.
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   The PLL is not disabled when used as system clock.
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         supported by this macro. User should request a transition to LSE Off
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         first and then LSE On or LSE Bypass.
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         supported by this macro. User should request a transition to HSE Off
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         first and then HSE On or HSE Bypass.
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval HAL status
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t tickstart;
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t temp_sysclksrc;
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t temp_pllckcfg;
+ARM GAS  /tmp/ccu53ZgF.s 			page 7
+
+
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Check Null pointer */
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (RCC_OscInitStruct == NULL)
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     return HAL_ERROR;
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Check the parameters */
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /*------------------------------- HSE Configuration ------------------------*/
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Check the parameters */
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowe
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sys
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         return HAL_ERROR;
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     else
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Set the new HSE configuration ---------------------------------------*/
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Check the HSE State */
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Get Start Tick*/
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Wait till HSE is ready */
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       else
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Get Start Tick*/
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Wait till HSE is disabled */
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ARM GAS  /tmp/ccu53ZgF.s 			page 8
+
+
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /*----------------------------- HSI Configuration --------------------------*/
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Check the parameters */
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock *
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sys
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* When HSI is used as system clock it will not be disabled */
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         return HAL_ERROR;
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Otherwise, just the calibration is allowed */
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       else
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Adapt Systick interrupt period */
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         if (HAL_InitTick(uwTickPrio) != HAL_OK)
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           return HAL_ERROR;
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     else
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Check the HSI State */
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Enable the Internal High Speed oscillator (HSI). */
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         __HAL_RCC_HSI_ENABLE();
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Get Start Tick*/
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Wait till HSI is ready */
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ARM GAS  /tmp/ccu53ZgF.s 			page 9
+
+
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       else
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Disable the Internal High Speed oscillator (HSI). */
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         __HAL_RCC_HSI_DISABLE();
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Get Start Tick*/
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Wait till HSI is disabled */
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /*------------------------------ LSI Configuration -------------------------*/
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Check the parameters */
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Check the LSI State */
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Enable the Internal Low Speed oscillator (LSI). */
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       __HAL_RCC_LSI_ENABLE();
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Get Start Tick*/
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       tickstart = HAL_GetTick();
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Wait till LSI is ready */
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           return HAL_TIMEOUT;
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     else
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Disable the Internal Low Speed oscillator (LSI). */
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       __HAL_RCC_LSI_DISABLE();
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Get Start Tick*/
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       tickstart = HAL_GetTick();
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Wait till LSI is disabled */
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ARM GAS  /tmp/ccu53ZgF.s 			page 10
+
+
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           return HAL_TIMEOUT;
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /*------------------------------ LSE Configuration -------------------------*/
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     FlagStatus       pwrclkchanged = RESET;
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Check the parameters */
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Update LSE configuration in Backup Domain control register    */
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Requires to enable write access to Backup Domain if necessary */
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       __HAL_RCC_PWR_CLK_ENABLE();
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       pwrclkchanged = SET;
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Enable write access to Backup domain */
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       SET_BIT(PWR->CR1, PWR_CR1_DBP);
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Wait for Backup domain Write protection disable */
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       tickstart = HAL_GetTick();
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           return HAL_TIMEOUT;
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Set the new LSE configuration -----------------------------------------*/
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Check the LSE State */
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Get Start Tick*/
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       tickstart = HAL_GetTick();
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Wait till LSE is ready */
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           return HAL_TIMEOUT;
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ARM GAS  /tmp/ccu53ZgF.s 			page 11
+
+
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     else
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Get Start Tick*/
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       tickstart = HAL_GetTick();
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Wait till LSE is disabled */
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           return HAL_TIMEOUT;
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Restore clock configuration if changed */
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (pwrclkchanged == SET)
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       __HAL_RCC_PWR_CLK_DISABLE();
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /*------------------------------ HSI48 Configuration -----------------------*/
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Check the parameters */
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Check the HSI48 State */
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Enable the Internal Low Speed oscillator (HSI48). */
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       __HAL_RCC_HSI48_ENABLE();
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Get Start Tick*/
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       tickstart = HAL_GetTick();
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Wait till HSI48 is ready */
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           return HAL_TIMEOUT;
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     else
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Disable the Internal Low Speed oscillator (HSI48). */
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       __HAL_RCC_HSI48_DISABLE();
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Get Start Tick*/
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       tickstart = HAL_GetTick();
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Wait till HSI48 is disabled */
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ARM GAS  /tmp/ccu53ZgF.s 			page 12
+
+
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           return HAL_TIMEOUT;
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /*-------------------------------- PLL Configuration -----------------------*/
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Check the parameters */
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Check if the PLL is used as system clock or not */
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Check the parameters */
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Disable the main PLL. */
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         __HAL_RCC_PLL_DISABLE();
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Get Start Tick*/
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Wait till PLL is ready */
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Configure the main PLL clock source, multiplication and division factors. */
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLM,
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLN,
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLP,
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLQ,
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLR);
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Enable the main PLL. */
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         __HAL_RCC_PLL_ENABLE();
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Enable PLL System Clock output. */
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Get Start Tick*/
+ARM GAS  /tmp/ccu53ZgF.s 			page 13
+
+
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Wait till PLL is ready */
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       else
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Disable the main PLL. */
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         __HAL_RCC_PLL_DISABLE();
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Disable all PLL outputs to save power if no PLLs on */
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Get Start Tick*/
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Wait till PLL is disabled */
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     else
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Check if there is a request to disable the PLL used as System clock source */
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         return HAL_ERROR;
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       else
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Do not return HAL_ERROR if request repeats the current configuration */
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       temp_pllckcfg = RCC->PLLCFGR;
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFG
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLL
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         return HAL_ERROR;
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ARM GAS  /tmp/ccu53ZgF.s 			page 14
+
+
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   return HAL_OK;
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Initialize the CPU, AHB and APB buses clocks according to the specified
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         parameters in the RCC_ClkInitStruct.
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @param  RCC_ClkInitStruct  pointer to an RCC_OscInitTypeDef structure that
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         contains the configuration information for the RCC peripheral.
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @param  FLatency  FLASH Latency
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *          This parameter can be one of the following values:
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_0   FLASH 0 Latency cycle
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_1   FLASH 1 Latency cycle
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_2   FLASH 2 Latency cycles
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_3   FLASH 3 Latency cycles
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_4   FLASH 4 Latency cycles
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_5   FLASH 5 Latency cycles
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_6   FLASH 6 Latency cycles
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_7   FLASH 7 Latency cycles
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_8   FLASH 8 Latency cycles
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_9   FLASH 9 Latency cycles
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_10  FLASH 10 Latency cycles
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_11  FLASH 11 Latency cycles
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_12  FLASH 12 Latency cycles
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_13  FLASH 13 Latency cycles
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_14  FLASH 14 Latency cycles
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg FLASH_LATENCY_15  FLASH 15 Latency cycles
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   The HSI is used by default as system clock source after
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         startup from Reset, wake-up from STANDBY mode. After restart from Reset,
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         the HSI frequency is set to its default value 16 MHz.
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   The HSI can be selected as system clock source after
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         from STOP modes or in case of failure of the HSE used directly or indirectly
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         as system clock (if the Clock Security System CSS is enabled).
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   A switch from one clock source to another occurs only if the target
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         clock source is ready (clock stable after startup delay or PLL locked).
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         If a clock source which is not yet ready is selected, the switch will
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         occur when the clock source is ready.
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   You can use HAL_RCC_GetClockConfig() function to know which clock is
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         currently used as system clock source.
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   Depending on the device voltage range, the software has to set correctly
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         (for more details refer to section above "Initialization/de-initialization functions")
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval None
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t tickstart;
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t pllfreq;
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t hpre = RCC_SYSCLK_DIV1;
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ARM GAS  /tmp/ccu53ZgF.s 			page 15
+
+
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Check Null pointer */
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (RCC_ClkInitStruct == NULL)
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     return HAL_ERROR;
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Check the parameters */
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   assert_param(IS_FLASH_LATENCY(FLatency));
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     must be correctly programmed according to the frequency of the CPU clock
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     (HCLK) and the supply voltage of the device. */
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Increasing the number of wait states because of higher CPU frequency */
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (FLatency > __HAL_FLASH_GET_LATENCY())
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     __HAL_FLASH_SET_LATENCY(FLatency);
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Check that the new number of wait states is taken into account to access the Flash
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     memory by reading the FLASH_ACR register */
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (__HAL_FLASH_GET_LATENCY() != FLatency)
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       return HAL_ERROR;
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /*------------------------- SYSCLK Configuration ---------------------------*/
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* PLL is selected as System Clock Source */
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Check the PLL ready flag */
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         return HAL_ERROR;
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Compute target PLL output frequency */
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       pllfreq = RCC_GetSysClockFreqFromPLLSource();
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if(pllfreq > 80000000U)
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****               (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           hpre = RCC_SYSCLK_DIV2;
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ARM GAS  /tmp/ccu53ZgF.s 			page 16
+
+
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     else
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* HSE is selected as System Clock Source */
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Check the HSE ready flag */
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           return HAL_ERROR;
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* HSI is selected as System Clock Source */
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       else
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         /* Check the HSI ready flag */
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           return HAL_ERROR;
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz *
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       pllfreq = HAL_RCC_GetSysClockFreq();
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if(pllfreq > 80000000U)
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         hpre = RCC_SYSCLK_DIV2;
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Get Start Tick*/
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     tickstart = HAL_GetTick();
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         return HAL_TIMEOUT;
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /*-------------------------- HCLK Configuration --------------------------*/
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Set the highest APB divider in order to ensure that we do not go through
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****        a non-spec phase whatever we decrease or increase HCLK. */
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ARM GAS  /tmp/ccu53ZgF.s 			page 17
+
+
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Set the new HCLK clock divider */
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   else
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if(hpre == RCC_SYSCLK_DIV2)
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Decreasing the number of wait states because of lower CPU frequency */
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (FLatency < __HAL_FLASH_GET_LATENCY())
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     __HAL_FLASH_SET_LATENCY(FLatency);
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Check that the new number of wait states is taken into account to access the Flash
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     memory by polling the FLASH_ACR register */
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     tickstart = HAL_GetTick();
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     while (__HAL_FLASH_GET_LATENCY() != FLatency)
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         return HAL_TIMEOUT;
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /*-------------------------- PCLK1 Configuration ---------------------------*/
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /*-------------------------- PCLK2 Configuration ---------------------------*/
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Update the SystemCoreClock global variable */
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) 
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Configure the source of time base considering new system clocks settings*/
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   return HAL_InitTick(uwTickPrio);
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+ARM GAS  /tmp/ccu53ZgF.s 			page 18
+
+
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @}
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****  *  @brief   RCC clocks control functions
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****  *
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** @verbatim
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****  ===============================================================================
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                       ##### Peripheral Control functions #####
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****  ===============================================================================
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     [..]
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     This subsection provides a set of functions allowing to:
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     (+) Output clock to MCO pin.
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     (+) Retrieve current clock frequencies.
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     (+) Enable the Clock Security System.
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** @endverbatim
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @{
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Select the clock source to output on MCO pin(PA8/PG10).
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   PA8/PG10 should be configured in alternate function mode.
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   The default configuration of the GPIOG pin 10 (PG10) is set to reset mode (NRST pin)
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         and user shall set the NRST_MODE Bit in the FLASH OPTR register to be able to use it 
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         as an MCO pin.
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         The @ref HAL_FLASHEx_OBProgram() API can be used to configure the NRST_MODE Bit value.
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @param  RCC_MCOx  specifies the output direction for the clock source.
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *          For STM32G4xx family this parameter can have only one value:
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCO_PA8  Clock source to output on MCO1 pin(PA8).
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCO_PG10  Clock source to output on MCO1 pin(PG10).
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @param  RCC_MCOSource  specifies the clock source to output.
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *          This parameter can be one of the following values:
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled, no clock on MCO
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCO1SOURCE_SYSCLK  system  clock selected as MCO source
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCO1SOURCE_PLLCLK  main PLL clock selected as MCO source
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with 
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @param  RCC_MCODiv  specifies the MCO prescaler.
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *          This parameter can be one of the following values:
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCODIV_1  no division applied to MCO clock
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCODIV_2  division by 2 applied to MCO clock
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCODIV_4  division by 4 applied to MCO clock
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCODIV_8  division by 8 applied to MCO clock
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *            @arg @ref RCC_MCODIV_16  division by 16 applied to MCO clock
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval None
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   GPIO_InitTypeDef gpio_initstruct;
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t mcoindex;
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t mco_gpio_index;
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   GPIO_TypeDef * mco_gpio_port;
+ARM GAS  /tmp/ccu53ZgF.s 			page 19
+
+
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Check the parameters */
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   assert_param(IS_RCC_MCO(RCC_MCOx));
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Common GPIO init parameters */
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   gpio_initstruct.Mode      = GPIO_MODE_AF_PP;
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   gpio_initstruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   gpio_initstruct.Pull      = GPIO_NOPULL;
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get MCOx selection */
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK;
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get MCOx GPIO Port */
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx);
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* MCOx Clock Enable */
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx);
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index ));
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Configure the MCOx pin in alternate function mode */
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx);
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx);
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct);
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****    if (mcoindex == RCC_MCO1_INDEX)
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv));
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Return the SYSCLK frequency.
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   The system frequency computed by this function is not the real
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         frequency in the chip. It is calculated based on the predefined
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         constant and the selected clock source:
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *           HSI_VALUE(*) Value multiplied/divided by the PLL factors.
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note     (*) HSI_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *               16 MHz) but the real value may vary depending on the variations
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *               in voltage and temperature.
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note     (**) HSE_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value
+1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *                8 MHz), user has to ensure that HSE_VALUE is same as the real
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *                frequency of the crystal used. Otherwise, this function may
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *                have wrong result.
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   The result of this function could be not correct when using fractional
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         value for HSE crystal.
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   This function can be used by the user application to compute the
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         baudrate for the communication peripherals or configure other parameters.
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+ARM GAS  /tmp/ccu53ZgF.s 			page 20
+
+
+1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   Each time SYSCLK changes, this function must be called to update the
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorre
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval SYSCLK frequency
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** uint32_t HAL_RCC_GetSysClockFreq(void)
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t pllvco, pllsource, pllr, pllm;
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t sysclockfreq;
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
+1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* HSI used as system clock source */
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     sysclockfreq = HSI_VALUE;
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
+1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* HSE used as system clock source */
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     sysclockfreq = HSE_VALUE;
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* PLL used as system clock  source */
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     SYSCLK = PLL_VCO / PLLR
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     */
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     switch (pllsource)
+1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_P
+1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     default:
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_P
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     sysclockfreq = pllvco/pllr;
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   else
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     sysclockfreq = 0U;
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   return sysclockfreq;
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Return the HCLK frequency.
+1113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   Each time HCLK changes, this function must be called to update the
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect
+ARM GAS  /tmp/ccu53ZgF.s 			page 21
+
+
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval HCLK frequency in Hz
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** uint32_t HAL_RCC_GetHCLKFreq(void)
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   return SystemCoreClock;
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Return the PCLK1 frequency.
+1126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   Each time PCLK1 changes, this function must be called to update the
+1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrec
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval PCLK1 frequency in Hz
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK1Freq(void)
+1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_P
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Return the PCLK2 frequency.
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   Each time PCLK2 changes, this function must be called to update the
+1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrec
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval PCLK2 frequency in Hz
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK2Freq(void)
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PP
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Configure the RCC_OscInitStruct according to the internal
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         RCC configuration registers.
+1151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
+1152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         will be configured.
+1153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval None
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Check the parameters */
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   assert_param(RCC_OscInitStruct != (void *)NULL);
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Set all possible values for the Oscillator type parameter ---------------*/
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLA
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get the HSE configuration -----------------------------------------------*/
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON)
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ARM GAS  /tmp/ccu53ZgF.s 			page 22
+
+
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   else
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get the HSI configuration -----------------------------------------------*/
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION)
+1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+1182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   else
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSI
+1189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get the LSE configuration -----------------------------------------------*/
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+1194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+1198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   else
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get the LSI configuration -----------------------------------------------*/
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION)
+1206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+1208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   else
+1210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get the HSI48 configuration ---------------------------------------------*/
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
+1216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   else
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get the PLL configuration -----------------------------------------------*/
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON)
+1226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ARM GAS  /tmp/ccu53ZgF.s 			page 23
+
+
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   else
+1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) 
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+1240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Configure the RCC_ClkInitStruct according to the internal
+1243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         RCC configuration registers.
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @param  RCC_ClkInitStruct  pointer to an RCC_ClkInitTypeDef structure that
+1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         will be configured.
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @param  pFLatency  Pointer on the Flash Latency.
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval None
+1248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+1251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Check the parameters */
+1252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   assert_param(RCC_ClkInitStruct != (void  *)NULL);
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   assert_param(pFLatency != (void *)NULL);
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Set all possible values for the Clock type parameter --------------------*/
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | 
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get the SYSCLK configuration --------------------------------------------*/
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get the HCLK configuration ----------------------------------------------*/
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);
+1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get the APB1 configuration ----------------------------------------------*/
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get the APB2 configuration ----------------------------------------------*/
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get the Flash Wait State (Latency) configuration ------------------------*/
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *pFLatency = __HAL_FLASH_GET_LATENCY();
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Enable the Clock Security System.
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         is automatically disabled and an interrupt is generated to inform the
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         software about the failure (Clock Security System Interrupt, CSSI),
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         allowing the MCU to perform rescue operations. The CSSI is linked to
+1280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   The Clock Security System can only be cleared by reset.
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval None
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** void HAL_RCC_EnableCSS(void)
+1285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+ARM GAS  /tmp/ccu53ZgF.s 			page 24
+
+
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   SET_BIT(RCC->CR, RCC_CR_CSSON) ;
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+1288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Enable the LSE Clock Security System.
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   If a failure is detected on the external 32 kHz oscillator,
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         the LSE clock is no longer supplied to the RTC but no hardware action
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         is made to the registers. If enabled, an interrupt will be generated
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   *         and handle through @ref RCCEx_EXTI_LINE_LSECSS
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   The Clock Security System can only be cleared by reset or after a LSE failure detection
+1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval None
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** void HAL_RCC_EnableLSECSS(void)
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+1302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Disable the LSE Clock Security System.
+1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   After LSE failure detection, the software must disable LSECSSON
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note   The Clock Security System can only be cleared by reset otherwise.
+1307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval None
+1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** void HAL_RCC_DisableLSECSS(void)
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief Handle the RCC Clock Security System interrupt request.
+1316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @note This API should be called under the NMI_Handler().
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval None
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** void HAL_RCC_NMI_IRQHandler(void)
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+1321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Check RCC CSSF interrupt flag  */
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+1323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* RCC Clock Security System interrupt user callback */
+1325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     HAL_RCC_CSSCallback();
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Clear RCC CSS pending bit */
+1328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  RCC Clock Security System interrupt callback.
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval none
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** __weak void HAL_RCC_CSSCallback(void)
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+1338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             the HAL_RCC_CSSCallback should be implemented in the user file
+1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****    */
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+1342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ARM GAS  /tmp/ccu53ZgF.s 			page 25
+
+
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @}
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @}
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /* Private function prototypes -----------------------------------------------*/
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /** @addtogroup RCC_Private_Functions
+1353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @{
+1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** /**
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @brief  Compute SYSCLK frequency based on PLL SYSCLK source.
+1358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   * @retval SYSCLK frequency
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   */
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** {
+  28              		.loc 1 1361 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t pllvco, pllsource, pllr, pllm;
+  33              		.loc 1 1362 3 view .LVU1
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t sysclockfreq;
+  34              		.loc 1 1363 3 view .LVU2
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
+1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****      SYSCLK = PLL_VCO / PLLR
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****    */
+1368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+  35              		.loc 1 1368 3 view .LVU3
+  36              		.loc 1 1368 15 is_stmt 0 view .LVU4
+  37 0000 124B     		ldr	r3, .L5
+  38 0002 DA68     		ldr	r2, [r3, #12]
+  39              		.loc 1 1368 13 view .LVU5
+  40 0004 02F00302 		and	r2, r2, #3
+  41              	.LVL0:
+1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
+  42              		.loc 1 1369 3 is_stmt 1 view .LVU6
+  43              		.loc 1 1369 11 is_stmt 0 view .LVU7
+  44 0008 DB68     		ldr	r3, [r3, #12]
+  45              		.loc 1 1369 52 view .LVU8
+  46 000a C3F30313 		ubfx	r3, r3, #4, #4
+  47              		.loc 1 1369 8 view .LVU9
+  48 000e 0133     		adds	r3, r3, #1
+  49              	.LVL1:
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   switch (pllsource)
+  50              		.loc 1 1371 3 is_stmt 1 view .LVU10
+  51 0010 032A     		cmp	r2, #3
+  52 0012 11D0     		beq	.L4
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos
+ARM GAS  /tmp/ccu53ZgF.s 			page 26
+
+
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     break;
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   default:
+1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos
+  53              		.loc 1 1379 5 view .LVU11
+  54              		.loc 1 1379 25 is_stmt 0 view .LVU12
+  55 0014 0E48     		ldr	r0, .L5+4
+  56 0016 B0FBF3F0 		udiv	r0, r0, r3
+  57              		.loc 1 1379 36 view .LVU13
+  58 001a 0C4B     		ldr	r3, .L5
+  59              	.LVL2:
+  60              		.loc 1 1379 36 view .LVU14
+  61 001c DB68     		ldr	r3, [r3, #12]
+  62              		.loc 1 1379 77 view .LVU15
+  63 001e C3F30623 		ubfx	r3, r3, #8, #7
+  64              		.loc 1 1379 12 view .LVU16
+  65 0022 03FB00F0 		mul	r0, r3, r0
+  66              	.LVL3:
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     break;
+  67              		.loc 1 1380 5 is_stmt 1 view .LVU17
+  68              	.L3:
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
+  69              		.loc 1 1383 3 view .LVU18
+  70              		.loc 1 1383 12 is_stmt 0 view .LVU19
+  71 0026 094B     		ldr	r3, .L5
+  72 0028 DB68     		ldr	r3, [r3, #12]
+  73              		.loc 1 1383 53 view .LVU20
+  74 002a C3F34163 		ubfx	r3, r3, #25, #2
+  75              		.loc 1 1383 78 view .LVU21
+  76 002e 0133     		adds	r3, r3, #1
+  77              		.loc 1 1383 8 view .LVU22
+  78 0030 5B00     		lsls	r3, r3, #1
+  79              	.LVL4:
+1384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   sysclockfreq = pllvco/pllr;
+  80              		.loc 1 1384 3 is_stmt 1 view .LVU23
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   return sysclockfreq;
+  81              		.loc 1 1386 3 view .LVU24
+1387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+  82              		.loc 1 1387 1 is_stmt 0 view .LVU25
+  83 0032 B0FBF3F0 		udiv	r0, r0, r3
+  84              	.LVL5:
+  85              		.loc 1 1387 1 view .LVU26
+  86 0036 7047     		bx	lr
+  87              	.LVL6:
+  88              	.L4:
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     break;
+  89              		.loc 1 1374 5 is_stmt 1 view .LVU27
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     break;
+  90              		.loc 1 1374 25 is_stmt 0 view .LVU28
+  91 0038 0648     		ldr	r0, .L5+8
+  92 003a B0FBF3F0 		udiv	r0, r0, r3
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     break;
+  93              		.loc 1 1374 36 view .LVU29
+ARM GAS  /tmp/ccu53ZgF.s 			page 27
+
+
+  94 003e 034B     		ldr	r3, .L5
+  95              	.LVL7:
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     break;
+  96              		.loc 1 1374 36 view .LVU30
+  97 0040 DB68     		ldr	r3, [r3, #12]
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     break;
+  98              		.loc 1 1374 77 view .LVU31
+  99 0042 C3F30623 		ubfx	r3, r3, #8, #7
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     break;
+ 100              		.loc 1 1374 12 view .LVU32
+ 101 0046 03FB00F0 		mul	r0, r3, r0
+ 102              	.LVL8:
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 103              		.loc 1 1375 5 is_stmt 1 view .LVU33
+ 104 004a ECE7     		b	.L3
+ 105              	.L6:
+ 106              		.align	2
+ 107              	.L5:
+ 108 004c 00100240 		.word	1073876992
+ 109 0050 0024F400 		.word	16000000
+ 110 0054 0080BB00 		.word	12288000
+ 111              		.cfi_endproc
+ 112              	.LFE344:
+ 114              		.section	.text.HAL_RCC_DeInit,"ax",%progbits
+ 115              		.align	1
+ 116              		.global	HAL_RCC_DeInit
+ 117              		.syntax unified
+ 118              		.thumb
+ 119              		.thumb_func
+ 121              	HAL_RCC_DeInit:
+ 122              	.LFB329:
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t tickstart;
+ 123              		.loc 1 220 1 view -0
+ 124              		.cfi_startproc
+ 125              		@ args = 0, pretend = 0, frame = 0
+ 126              		@ frame_needed = 0, uses_anonymous_args = 0
+ 127 0000 38B5     		push	{r3, r4, r5, lr}
+ 128              	.LCFI0:
+ 129              		.cfi_def_cfa_offset 16
+ 130              		.cfi_offset 3, -16
+ 131              		.cfi_offset 4, -12
+ 132              		.cfi_offset 5, -8
+ 133              		.cfi_offset 14, -4
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 134              		.loc 1 221 3 view .LVU35
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 135              		.loc 1 224 3 view .LVU36
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 136              		.loc 1 224 15 is_stmt 0 view .LVU37
+ 137 0002 FFF7FEFF 		bl	HAL_GetTick
+ 138              	.LVL9:
+ 139 0006 0446     		mov	r4, r0
+ 140              	.LVL10:
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 141              		.loc 1 227 3 is_stmt 1 view .LVU38
+ 142 0008 2C4A     		ldr	r2, .L24
+ 143 000a 1368     		ldr	r3, [r2]
+ARM GAS  /tmp/ccu53ZgF.s 			page 28
+
+
+ 144 000c 43F48073 		orr	r3, r3, #256
+ 145 0010 1360     		str	r3, [r2]
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 146              		.loc 1 230 3 view .LVU39
+ 147              	.LVL11:
+ 148              	.L8:
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 149              		.loc 1 230 43 view .LVU40
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 150              		.loc 1 230 10 is_stmt 0 view .LVU41
+ 151 0012 2A4B     		ldr	r3, .L24
+ 152 0014 1B68     		ldr	r3, [r3]
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 153              		.loc 1 230 43 view .LVU42
+ 154 0016 13F4806F 		tst	r3, #1024
+ 155 001a 07D1     		bne	.L20
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 156              		.loc 1 232 5 is_stmt 1 view .LVU43
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 157              		.loc 1 232 10 is_stmt 0 view .LVU44
+ 158 001c FFF7FEFF 		bl	HAL_GetTick
+ 159              	.LVL12:
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 160              		.loc 1 232 24 view .LVU45
+ 161 0020 001B     		subs	r0, r0, r4
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 162              		.loc 1 232 8 view .LVU46
+ 163 0022 0228     		cmp	r0, #2
+ 164 0024 F5D9     		bls	.L8
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 165              		.loc 1 234 14 view .LVU47
+ 166 0026 0324     		movs	r4, #3
+ 167              	.LVL13:
+ 168              	.L9:
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 169              		.loc 1 296 1 view .LVU48
+ 170 0028 2046     		mov	r0, r4
+ 171 002a 38BD     		pop	{r3, r4, r5, pc}
+ 172              	.LVL14:
+ 173              	.L20:
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 174              		.loc 1 239 3 is_stmt 1 view .LVU49
+ 175 002c 234D     		ldr	r5, .L24
+ 176 002e 6B68     		ldr	r3, [r5, #4]
+ 177 0030 43F08043 		orr	r3, r3, #1073741824
+ 178 0034 6B60     		str	r3, [r5, #4]
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 179              		.loc 1 242 3 view .LVU50
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 180              		.loc 1 242 15 is_stmt 0 view .LVU51
+ 181 0036 FFF7FEFF 		bl	HAL_GetTick
+ 182              	.LVL15:
+ 183 003a 0446     		mov	r4, r0
+ 184              	.LVL16:
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 185              		.loc 1 245 3 is_stmt 1 view .LVU52
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ARM GAS  /tmp/ccu53ZgF.s 			page 29
+
+
+ 186              		.loc 1 245 13 is_stmt 0 view .LVU53
+ 187 003c 0123     		movs	r3, #1
+ 188 003e AB60     		str	r3, [r5, #8]
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 189              		.loc 1 248 3 is_stmt 1 view .LVU54
+ 190              	.LVL17:
+ 191              	.L11:
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 192              		.loc 1 248 44 view .LVU55
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 193              		.loc 1 248 10 is_stmt 0 view .LVU56
+ 194 0040 1E4B     		ldr	r3, .L24
+ 195 0042 9B68     		ldr	r3, [r3, #8]
+ 196 0044 03F00C03 		and	r3, r3, #12
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 197              		.loc 1 248 44 view .LVU57
+ 198 0048 042B     		cmp	r3, #4
+ 199 004a 08D0     		beq	.L21
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 200              		.loc 1 250 5 is_stmt 1 view .LVU58
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 201              		.loc 1 250 10 is_stmt 0 view .LVU59
+ 202 004c FFF7FEFF 		bl	HAL_GetTick
+ 203              	.LVL18:
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 204              		.loc 1 250 24 view .LVU60
+ 205 0050 001B     		subs	r0, r0, r4
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 206              		.loc 1 250 8 view .LVU61
+ 207 0052 41F28833 		movw	r3, #5000
+ 208 0056 9842     		cmp	r0, r3
+ 209 0058 F2D9     		bls	.L11
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 210              		.loc 1 252 14 view .LVU62
+ 211 005a 0324     		movs	r4, #3
+ 212              	.LVL19:
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 213              		.loc 1 252 14 view .LVU63
+ 214 005c E4E7     		b	.L9
+ 215              	.LVL20:
+ 216              	.L21:
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 217              		.loc 1 257 3 is_stmt 1 view .LVU64
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 218              		.loc 1 257 19 is_stmt 0 view .LVU65
+ 219 005e 184B     		ldr	r3, .L24+4
+ 220 0060 184A     		ldr	r2, .L24+8
+ 221 0062 1A60     		str	r2, [r3]
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 222              		.loc 1 260 3 is_stmt 1 view .LVU66
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 223              		.loc 1 260 7 is_stmt 0 view .LVU67
+ 224 0064 184B     		ldr	r3, .L24+12
+ 225 0066 1868     		ldr	r0, [r3]
+ 226 0068 FFF7FEFF 		bl	HAL_InitTick
+ 227              	.LVL21:
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ARM GAS  /tmp/ccu53ZgF.s 			page 30
+
+
+ 228              		.loc 1 260 6 view .LVU68
+ 229 006c 0446     		mov	r4, r0
+ 230              	.LVL22:
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 231              		.loc 1 260 6 view .LVU69
+ 232 006e 08B1     		cbz	r0, .L22
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 233              		.loc 1 262 12 view .LVU70
+ 234 0070 0124     		movs	r4, #1
+ 235 0072 D9E7     		b	.L9
+ 236              	.L22:
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 237              		.loc 1 266 3 is_stmt 1 view .LVU71
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 238              		.loc 1 266 11 is_stmt 0 view .LVU72
+ 239 0074 114B     		ldr	r3, .L24
+ 240 0076 4FF48072 		mov	r2, #256
+ 241 007a 1A60     		str	r2, [r3]
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 242              		.loc 1 269 3 is_stmt 1 view .LVU73
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 243              		.loc 1 269 11 is_stmt 0 view .LVU74
+ 244 007c 1A60     		str	r2, [r3]
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 245              		.loc 1 272 3 is_stmt 1 view .LVU75
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 246              		.loc 1 272 15 is_stmt 0 view .LVU76
+ 247 007e FFF7FEFF 		bl	HAL_GetTick
+ 248              	.LVL23:
+ 249 0082 0546     		mov	r5, r0
+ 250              	.LVL24:
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 251              		.loc 1 275 3 is_stmt 1 view .LVU77
+ 252              	.L13:
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 253              		.loc 1 275 43 view .LVU78
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 254              		.loc 1 275 10 is_stmt 0 view .LVU79
+ 255 0084 0D4B     		ldr	r3, .L24
+ 256 0086 1B68     		ldr	r3, [r3]
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 257              		.loc 1 275 43 view .LVU80
+ 258 0088 13F0007F 		tst	r3, #33554432
+ 259 008c 06D0     		beq	.L23
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 260              		.loc 1 277 5 is_stmt 1 view .LVU81
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 261              		.loc 1 277 10 is_stmt 0 view .LVU82
+ 262 008e FFF7FEFF 		bl	HAL_GetTick
+ 263              	.LVL25:
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 264              		.loc 1 277 24 view .LVU83
+ 265 0092 401B     		subs	r0, r0, r5
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 266              		.loc 1 277 8 view .LVU84
+ 267 0094 0228     		cmp	r0, #2
+ 268 0096 F5D9     		bls	.L13
+ARM GAS  /tmp/ccu53ZgF.s 			page 31
+
+
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 269              		.loc 1 279 14 view .LVU85
+ 270 0098 0324     		movs	r4, #3
+ 271 009a C5E7     		b	.L9
+ 272              	.L23:
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 273              		.loc 1 284 3 is_stmt 1 view .LVU86
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 274              		.loc 1 284 16 is_stmt 0 view .LVU87
+ 275 009c 074B     		ldr	r3, .L24
+ 276 009e 4FF48052 		mov	r2, #4096
+ 277 00a2 DA60     		str	r2, [r3, #12]
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 278              		.loc 1 287 3 is_stmt 1 view .LVU88
+ 279 00a4 0022     		movs	r2, #0
+ 280 00a6 9A61     		str	r2, [r3, #24]
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 281              		.loc 1 290 3 view .LVU89
+ 282 00a8 4FF0FF32 		mov	r2, #-1
+ 283 00ac 1A62     		str	r2, [r3, #32]
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 284              		.loc 1 293 3 view .LVU90
+ 285 00ae D3F89420 		ldr	r2, [r3, #148]
+ 286 00b2 42F40002 		orr	r2, r2, #8388608
+ 287 00b6 C3F89420 		str	r2, [r3, #148]
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 288              		.loc 1 295 3 view .LVU91
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 289              		.loc 1 295 10 is_stmt 0 view .LVU92
+ 290 00ba B5E7     		b	.L9
+ 291              	.L25:
+ 292              		.align	2
+ 293              	.L24:
+ 294 00bc 00100240 		.word	1073876992
+ 295 00c0 00000000 		.word	SystemCoreClock
+ 296 00c4 0024F400 		.word	16000000
+ 297 00c8 00000000 		.word	uwTickPrio
+ 298              		.cfi_endproc
+ 299              	.LFE329:
+ 301              		.section	.text.HAL_RCC_OscConfig,"ax",%progbits
+ 302              		.align	1
+ 303              		.global	HAL_RCC_OscConfig
+ 304              		.syntax unified
+ 305              		.thumb
+ 306              		.thumb_func
+ 308              	HAL_RCC_OscConfig:
+ 309              	.LVL26:
+ 310              	.LFB330:
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t tickstart;
+ 311              		.loc 1 313 1 is_stmt 1 view -0
+ 312              		.cfi_startproc
+ 313              		@ args = 0, pretend = 0, frame = 8
+ 314              		@ frame_needed = 0, uses_anonymous_args = 0
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t temp_sysclksrc;
+ 315              		.loc 1 314 3 view .LVU94
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t temp_pllckcfg;
+ 316              		.loc 1 315 3 view .LVU95
+ARM GAS  /tmp/ccu53ZgF.s 			page 32
+
+
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 317              		.loc 1 316 3 view .LVU96
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 318              		.loc 1 319 3 view .LVU97
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 319              		.loc 1 319 6 is_stmt 0 view .LVU98
+ 320 0000 0028     		cmp	r0, #0
+ 321 0002 00F05482 		beq	.L84
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t tickstart;
+ 322              		.loc 1 313 1 view .LVU99
+ 323 0006 70B5     		push	{r4, r5, r6, lr}
+ 324              	.LCFI1:
+ 325              		.cfi_def_cfa_offset 16
+ 326              		.cfi_offset 4, -16
+ 327              		.cfi_offset 5, -12
+ 328              		.cfi_offset 6, -8
+ 329              		.cfi_offset 14, -4
+ 330 0008 82B0     		sub	sp, sp, #8
+ 331              	.LCFI2:
+ 332              		.cfi_def_cfa_offset 24
+ 333 000a 0446     		mov	r4, r0
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 334              		.loc 1 325 3 is_stmt 1 view .LVU100
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 335              		.loc 1 328 3 view .LVU101
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 336              		.loc 1 328 26 is_stmt 0 view .LVU102
+ 337 000c 0368     		ldr	r3, [r0]
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 338              		.loc 1 328 6 view .LVU103
+ 339 000e 13F0010F 		tst	r3, #1
+ 340 0012 37D0     		beq	.L28
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 341              		.loc 1 331 5 is_stmt 1 view .LVU104
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
+ 342              		.loc 1 333 5 view .LVU105
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
+ 343              		.loc 1 333 22 is_stmt 0 view .LVU106
+ 344 0014 A44A     		ldr	r2, .L130
+ 345 0016 9368     		ldr	r3, [r2, #8]
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
+ 346              		.loc 1 333 20 view .LVU107
+ 347 0018 03F00C03 		and	r3, r3, #12
+ 348              	.LVL27:
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 349              		.loc 1 334 5 is_stmt 1 view .LVU108
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 350              		.loc 1 334 21 is_stmt 0 view .LVU109
+ 351 001c D268     		ldr	r2, [r2, #12]
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 352              		.loc 1 334 19 view .LVU110
+ 353 001e 02F00302 		and	r2, r2, #3
+ 354              	.LVL28:
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 355              		.loc 1 337 5 is_stmt 1 view .LVU111
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 356              		.loc 1 337 8 is_stmt 0 view .LVU112
+ARM GAS  /tmp/ccu53ZgF.s 			page 33
+
+
+ 357 0022 0C2B     		cmp	r3, #12
+ 358 0024 23D0     		beq	.L115
+ 359              	.L29:
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 360              		.loc 1 337 88 discriminator 3 view .LVU113
+ 361 0026 082B     		cmp	r3, #8
+ 362 0028 23D0     		beq	.L30
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 363              		.loc 1 347 7 is_stmt 1 view .LVU114
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 364              		.loc 1 347 7 view .LVU115
+ 365 002a 6368     		ldr	r3, [r4, #4]
+ 366              	.LVL29:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 367              		.loc 1 347 7 is_stmt 0 view .LVU116
+ 368 002c B3F5803F 		cmp	r3, #65536
+ 369 0030 4ED0     		beq	.L116
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 370              		.loc 1 347 7 is_stmt 1 discriminator 2 view .LVU117
+ 371 0032 B3F5A02F 		cmp	r3, #327680
+ 372 0036 51D0     		beq	.L117
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 373              		.loc 1 347 7 discriminator 5 view .LVU118
+ 374 0038 9B4B     		ldr	r3, .L130
+ 375 003a 1A68     		ldr	r2, [r3]
+ 376              	.LVL30:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 377              		.loc 1 347 7 is_stmt 0 discriminator 5 view .LVU119
+ 378 003c 22F48032 		bic	r2, r2, #65536
+ 379 0040 1A60     		str	r2, [r3]
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 380              		.loc 1 347 7 is_stmt 1 discriminator 5 view .LVU120
+ 381 0042 1A68     		ldr	r2, [r3]
+ 382 0044 22F48022 		bic	r2, r2, #262144
+ 383 0048 1A60     		str	r2, [r3]
+ 384              	.L33:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 385              		.loc 1 347 7 discriminator 7 view .LVU121
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 386              		.loc 1 350 7 discriminator 7 view .LVU122
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 387              		.loc 1 350 28 is_stmt 0 discriminator 7 view .LVU123
+ 388 004a 6368     		ldr	r3, [r4, #4]
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 389              		.loc 1 350 10 discriminator 7 view .LVU124
+ 390 004c 002B     		cmp	r3, #0
+ 391 004e 52D0     		beq	.L35
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 392              		.loc 1 353 9 is_stmt 1 view .LVU125
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 393              		.loc 1 353 21 is_stmt 0 view .LVU126
+ 394 0050 FFF7FEFF 		bl	HAL_GetTick
+ 395              	.LVL31:
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 396              		.loc 1 353 21 view .LVU127
+ 397 0054 0546     		mov	r5, r0
+ 398              	.LVL32:
+ARM GAS  /tmp/ccu53ZgF.s 			page 34
+
+
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 399              		.loc 1 356 9 is_stmt 1 view .LVU128
+ 400              	.L36:
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 401              		.loc 1 356 49 view .LVU129
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 402              		.loc 1 356 16 is_stmt 0 view .LVU130
+ 403 0056 944B     		ldr	r3, .L130
+ 404 0058 1B68     		ldr	r3, [r3]
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 405              		.loc 1 356 49 view .LVU131
+ 406 005a 13F4003F 		tst	r3, #131072
+ 407 005e 11D1     		bne	.L28
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 408              		.loc 1 358 11 is_stmt 1 view .LVU132
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 409              		.loc 1 358 16 is_stmt 0 view .LVU133
+ 410 0060 FFF7FEFF 		bl	HAL_GetTick
+ 411              	.LVL33:
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 412              		.loc 1 358 30 view .LVU134
+ 413 0064 401B     		subs	r0, r0, r5
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 414              		.loc 1 358 14 view .LVU135
+ 415 0066 6428     		cmp	r0, #100
+ 416 0068 F5D9     		bls	.L36
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 417              		.loc 1 360 20 view .LVU136
+ 418 006a 0320     		movs	r0, #3
+ 419 006c 28E2     		b	.L27
+ 420              	.LVL34:
+ 421              	.L115:
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 422              		.loc 1 337 47 discriminator 1 view .LVU137
+ 423 006e 032A     		cmp	r2, #3
+ 424 0070 D9D1     		bne	.L29
+ 425              	.L30:
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 426              		.loc 1 339 7 is_stmt 1 view .LVU138
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 427              		.loc 1 339 12 is_stmt 0 view .LVU139
+ 428 0072 8D4B     		ldr	r3, .L130
+ 429              	.LVL35:
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 430              		.loc 1 339 12 view .LVU140
+ 431 0074 1B68     		ldr	r3, [r3]
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 432              		.loc 1 339 10 view .LVU141
+ 433 0076 13F4003F 		tst	r3, #131072
+ 434 007a 03D0     		beq	.L28
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 435              		.loc 1 339 73 discriminator 1 view .LVU142
+ 436 007c 6368     		ldr	r3, [r4, #4]
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 437              		.loc 1 339 52 discriminator 1 view .LVU143
+ 438 007e 002B     		cmp	r3, #0
+ 439 0080 00F01782 		beq	.L118
+ARM GAS  /tmp/ccu53ZgF.s 			page 35
+
+
+ 440              	.LVL36:
+ 441              	.L28:
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 442              		.loc 1 381 3 is_stmt 1 view .LVU144
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 443              		.loc 1 381 26 is_stmt 0 view .LVU145
+ 444 0084 2368     		ldr	r3, [r4]
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 445              		.loc 1 381 6 view .LVU146
+ 446 0086 13F0020F 		tst	r3, #2
+ 447 008a 5DD0     		beq	.L40
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+ 448              		.loc 1 384 5 is_stmt 1 view .LVU147
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 449              		.loc 1 385 5 view .LVU148
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
+ 450              		.loc 1 388 5 view .LVU149
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
+ 451              		.loc 1 388 22 is_stmt 0 view .LVU150
+ 452 008c 864A     		ldr	r2, .L130
+ 453 008e 9368     		ldr	r3, [r2, #8]
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
+ 454              		.loc 1 388 20 view .LVU151
+ 455 0090 03F00C03 		and	r3, r3, #12
+ 456              	.LVL37:
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sys
+ 457              		.loc 1 389 5 is_stmt 1 view .LVU152
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sys
+ 458              		.loc 1 389 21 is_stmt 0 view .LVU153
+ 459 0094 D268     		ldr	r2, [r2, #12]
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sys
+ 460              		.loc 1 389 19 view .LVU154
+ 461 0096 02F00302 		and	r2, r2, #3
+ 462              	.LVL38:
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 463              		.loc 1 390 5 is_stmt 1 view .LVU155
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 464              		.loc 1 390 8 is_stmt 0 view .LVU156
+ 465 009a 0C2B     		cmp	r3, #12
+ 466 009c 3AD0     		beq	.L119
+ 467              	.L41:
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 468              		.loc 1 390 88 discriminator 3 view .LVU157
+ 469 009e 042B     		cmp	r3, #4
+ 470 00a0 3AD0     		beq	.L42
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 471              		.loc 1 413 7 is_stmt 1 view .LVU158
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 472              		.loc 1 413 28 is_stmt 0 view .LVU159
+ 473 00a2 E368     		ldr	r3, [r4, #12]
+ 474              	.LVL39:
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 475              		.loc 1 413 10 view .LVU160
+ 476 00a4 002B     		cmp	r3, #0
+ 477 00a6 75D0     		beq	.L45
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 478              		.loc 1 416 9 is_stmt 1 view .LVU161
+ARM GAS  /tmp/ccu53ZgF.s 			page 36
+
+
+ 479 00a8 7F4A     		ldr	r2, .L130
+ 480              	.LVL40:
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 481              		.loc 1 416 9 is_stmt 0 view .LVU162
+ 482 00aa 1368     		ldr	r3, [r2]
+ 483 00ac 43F48073 		orr	r3, r3, #256
+ 484 00b0 1360     		str	r3, [r2]
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 485              		.loc 1 419 9 is_stmt 1 view .LVU163
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 486              		.loc 1 419 21 is_stmt 0 view .LVU164
+ 487 00b2 FFF7FEFF 		bl	HAL_GetTick
+ 488              	.LVL41:
+ 489 00b6 0546     		mov	r5, r0
+ 490              	.LVL42:
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 491              		.loc 1 422 9 is_stmt 1 view .LVU165
+ 492              	.L46:
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 493              		.loc 1 422 49 view .LVU166
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 494              		.loc 1 422 16 is_stmt 0 view .LVU167
+ 495 00b8 7B4B     		ldr	r3, .L130
+ 496 00ba 1B68     		ldr	r3, [r3]
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 497              		.loc 1 422 49 view .LVU168
+ 498 00bc 13F4806F 		tst	r3, #1024
+ 499 00c0 5FD1     		bne	.L120
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 500              		.loc 1 424 11 is_stmt 1 view .LVU169
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 501              		.loc 1 424 16 is_stmt 0 view .LVU170
+ 502 00c2 FFF7FEFF 		bl	HAL_GetTick
+ 503              	.LVL43:
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 504              		.loc 1 424 30 view .LVU171
+ 505 00c6 401B     		subs	r0, r0, r5
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 506              		.loc 1 424 14 view .LVU172
+ 507 00c8 0228     		cmp	r0, #2
+ 508 00ca F5D9     		bls	.L46
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 509              		.loc 1 426 20 view .LVU173
+ 510 00cc 0320     		movs	r0, #3
+ 511 00ce F7E1     		b	.L27
+ 512              	.LVL44:
+ 513              	.L116:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 514              		.loc 1 347 7 is_stmt 1 discriminator 1 view .LVU174
+ 515 00d0 754A     		ldr	r2, .L130
+ 516              	.LVL45:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 517              		.loc 1 347 7 is_stmt 0 discriminator 1 view .LVU175
+ 518 00d2 1368     		ldr	r3, [r2]
+ 519 00d4 43F48033 		orr	r3, r3, #65536
+ 520 00d8 1360     		str	r3, [r2]
+ 521 00da B6E7     		b	.L33
+ARM GAS  /tmp/ccu53ZgF.s 			page 37
+
+
+ 522              	.LVL46:
+ 523              	.L117:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 524              		.loc 1 347 7 is_stmt 1 discriminator 4 view .LVU176
+ 525 00dc 03F18043 		add	r3, r3, #1073741824
+ 526 00e0 A3F53C33 		sub	r3, r3, #192512
+ 527 00e4 1A68     		ldr	r2, [r3]
+ 528              	.LVL47:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 529              		.loc 1 347 7 is_stmt 0 discriminator 4 view .LVU177
+ 530 00e6 42F48022 		orr	r2, r2, #262144
+ 531 00ea 1A60     		str	r2, [r3]
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 532              		.loc 1 347 7 is_stmt 1 discriminator 4 view .LVU178
+ 533 00ec 1A68     		ldr	r2, [r3]
+ 534 00ee 42F48032 		orr	r2, r2, #65536
+ 535 00f2 1A60     		str	r2, [r3]
+ 536 00f4 A9E7     		b	.L33
+ 537              	.L35:
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 538              		.loc 1 367 9 view .LVU179
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 539              		.loc 1 367 21 is_stmt 0 view .LVU180
+ 540 00f6 FFF7FEFF 		bl	HAL_GetTick
+ 541              	.LVL48:
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 542              		.loc 1 367 21 view .LVU181
+ 543 00fa 0546     		mov	r5, r0
+ 544              	.LVL49:
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 545              		.loc 1 370 9 is_stmt 1 view .LVU182
+ 546              	.L38:
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 547              		.loc 1 370 49 view .LVU183
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 548              		.loc 1 370 16 is_stmt 0 view .LVU184
+ 549 00fc 6A4B     		ldr	r3, .L130
+ 550 00fe 1B68     		ldr	r3, [r3]
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 551              		.loc 1 370 49 view .LVU185
+ 552 0100 13F4003F 		tst	r3, #131072
+ 553 0104 BED0     		beq	.L28
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 554              		.loc 1 372 11 is_stmt 1 view .LVU186
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 555              		.loc 1 372 16 is_stmt 0 view .LVU187
+ 556 0106 FFF7FEFF 		bl	HAL_GetTick
+ 557              	.LVL50:
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 558              		.loc 1 372 30 view .LVU188
+ 559 010a 401B     		subs	r0, r0, r5
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 560              		.loc 1 372 14 view .LVU189
+ 561 010c 6428     		cmp	r0, #100
+ 562 010e F5D9     		bls	.L38
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 563              		.loc 1 374 20 view .LVU190
+ARM GAS  /tmp/ccu53ZgF.s 			page 38
+
+
+ 564 0110 0320     		movs	r0, #3
+ 565 0112 D5E1     		b	.L27
+ 566              	.LVL51:
+ 567              	.L119:
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 568              		.loc 1 390 47 discriminator 1 view .LVU191
+ 569 0114 022A     		cmp	r2, #2
+ 570 0116 C2D1     		bne	.L41
+ 571              	.L42:
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 572              		.loc 1 393 7 is_stmt 1 view .LVU192
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 573              		.loc 1 393 12 is_stmt 0 view .LVU193
+ 574 0118 634B     		ldr	r3, .L130
+ 575              	.LVL52:
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 576              		.loc 1 393 12 view .LVU194
+ 577 011a 1B68     		ldr	r3, [r3]
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 578              		.loc 1 393 10 view .LVU195
+ 579 011c 13F4806F 		tst	r3, #1024
+ 580 0120 03D0     		beq	.L44
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 581              		.loc 1 393 73 discriminator 1 view .LVU196
+ 582 0122 E368     		ldr	r3, [r4, #12]
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 583              		.loc 1 393 52 discriminator 1 view .LVU197
+ 584 0124 002B     		cmp	r3, #0
+ 585 0126 00F0C681 		beq	.L88
+ 586              	.L44:
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 587              		.loc 1 401 9 is_stmt 1 view .LVU198
+ 588 012a 5F4A     		ldr	r2, .L130
+ 589              	.LVL53:
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 590              		.loc 1 401 9 is_stmt 0 view .LVU199
+ 591 012c 5368     		ldr	r3, [r2, #4]
+ 592 012e 23F0FE43 		bic	r3, r3, #2130706432
+ 593 0132 2169     		ldr	r1, [r4, #16]
+ 594 0134 43EA0163 		orr	r3, r3, r1, lsl #24
+ 595 0138 5360     		str	r3, [r2, #4]
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 596              		.loc 1 404 9 is_stmt 1 view .LVU200
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 597              		.loc 1 404 13 is_stmt 0 view .LVU201
+ 598 013a 5C4B     		ldr	r3, .L130+4
+ 599 013c 1868     		ldr	r0, [r3]
+ 600 013e FFF7FEFF 		bl	HAL_InitTick
+ 601              	.LVL54:
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 602              		.loc 1 404 12 view .LVU202
+ 603 0142 0028     		cmp	r0, #0
+ 604 0144 40F0B981 		bne	.L121
+ 605              	.LVL55:
+ 606              	.L40:
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 607              		.loc 1 453 3 is_stmt 1 view .LVU203
+ARM GAS  /tmp/ccu53ZgF.s 			page 39
+
+
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 608              		.loc 1 453 26 is_stmt 0 view .LVU204
+ 609 0148 2368     		ldr	r3, [r4]
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 610              		.loc 1 453 6 view .LVU205
+ 611 014a 13F0080F 		tst	r3, #8
+ 612 014e 4CD0     		beq	.L50
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 613              		.loc 1 456 5 is_stmt 1 view .LVU206
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 614              		.loc 1 459 5 view .LVU207
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 615              		.loc 1 459 25 is_stmt 0 view .LVU208
+ 616 0150 6369     		ldr	r3, [r4, #20]
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 617              		.loc 1 459 7 view .LVU209
+ 618 0152 9BB3     		cbz	r3, .L51
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 619              		.loc 1 462 7 is_stmt 1 view .LVU210
+ 620 0154 544A     		ldr	r2, .L130
+ 621 0156 D2F89430 		ldr	r3, [r2, #148]
+ 622 015a 43F00103 		orr	r3, r3, #1
+ 623 015e C2F89430 		str	r3, [r2, #148]
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 624              		.loc 1 465 7 view .LVU211
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 625              		.loc 1 465 19 is_stmt 0 view .LVU212
+ 626 0162 FFF7FEFF 		bl	HAL_GetTick
+ 627              	.LVL56:
+ 628 0166 0546     		mov	r5, r0
+ 629              	.LVL57:
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 630              		.loc 1 468 7 is_stmt 1 view .LVU213
+ 631              	.L52:
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 632              		.loc 1 468 49 view .LVU214
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 633              		.loc 1 468 14 is_stmt 0 view .LVU215
+ 634 0168 4F4B     		ldr	r3, .L130
+ 635 016a D3F89430 		ldr	r3, [r3, #148]
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 636              		.loc 1 468 49 view .LVU216
+ 637 016e 13F0020F 		tst	r3, #2
+ 638 0172 3AD1     		bne	.L50
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 639              		.loc 1 470 9 is_stmt 1 view .LVU217
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 640              		.loc 1 470 14 is_stmt 0 view .LVU218
+ 641 0174 FFF7FEFF 		bl	HAL_GetTick
+ 642              	.LVL58:
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 643              		.loc 1 470 28 view .LVU219
+ 644 0178 401B     		subs	r0, r0, r5
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 645              		.loc 1 470 12 view .LVU220
+ 646 017a 0228     		cmp	r0, #2
+ 647 017c F4D9     		bls	.L52
+ARM GAS  /tmp/ccu53ZgF.s 			page 40
+
+
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 648              		.loc 1 472 18 view .LVU221
+ 649 017e 0320     		movs	r0, #3
+ 650 0180 9EE1     		b	.L27
+ 651              	.LVL59:
+ 652              	.L120:
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 653              		.loc 1 431 9 is_stmt 1 view .LVU222
+ 654 0182 494A     		ldr	r2, .L130
+ 655 0184 5368     		ldr	r3, [r2, #4]
+ 656 0186 23F0FE43 		bic	r3, r3, #2130706432
+ 657 018a 2169     		ldr	r1, [r4, #16]
+ 658 018c 43EA0163 		orr	r3, r3, r1, lsl #24
+ 659 0190 5360     		str	r3, [r2, #4]
+ 660 0192 D9E7     		b	.L40
+ 661              	.LVL60:
+ 662              	.L45:
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 663              		.loc 1 436 9 view .LVU223
+ 664 0194 444A     		ldr	r2, .L130
+ 665              	.LVL61:
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 666              		.loc 1 436 9 is_stmt 0 view .LVU224
+ 667 0196 1368     		ldr	r3, [r2]
+ 668 0198 23F48073 		bic	r3, r3, #256
+ 669 019c 1360     		str	r3, [r2]
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 670              		.loc 1 439 9 is_stmt 1 view .LVU225
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 671              		.loc 1 439 21 is_stmt 0 view .LVU226
+ 672 019e FFF7FEFF 		bl	HAL_GetTick
+ 673              	.LVL62:
+ 674 01a2 0546     		mov	r5, r0
+ 675              	.LVL63:
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 676              		.loc 1 442 9 is_stmt 1 view .LVU227
+ 677              	.L48:
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 678              		.loc 1 442 49 view .LVU228
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 679              		.loc 1 442 16 is_stmt 0 view .LVU229
+ 680 01a4 404B     		ldr	r3, .L130
+ 681 01a6 1B68     		ldr	r3, [r3]
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 682              		.loc 1 442 49 view .LVU230
+ 683 01a8 13F4806F 		tst	r3, #1024
+ 684 01ac CCD0     		beq	.L40
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 685              		.loc 1 444 11 is_stmt 1 view .LVU231
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 686              		.loc 1 444 16 is_stmt 0 view .LVU232
+ 687 01ae FFF7FEFF 		bl	HAL_GetTick
+ 688              	.LVL64:
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 689              		.loc 1 444 30 view .LVU233
+ 690 01b2 401B     		subs	r0, r0, r5
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ARM GAS  /tmp/ccu53ZgF.s 			page 41
+
+
+ 691              		.loc 1 444 14 view .LVU234
+ 692 01b4 0228     		cmp	r0, #2
+ 693 01b6 F5D9     		bls	.L48
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 694              		.loc 1 446 20 view .LVU235
+ 695 01b8 0320     		movs	r0, #3
+ 696 01ba 81E1     		b	.L27
+ 697              	.LVL65:
+ 698              	.L51:
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 699              		.loc 1 479 7 is_stmt 1 view .LVU236
+ 700 01bc 3A4A     		ldr	r2, .L130
+ 701 01be D2F89430 		ldr	r3, [r2, #148]
+ 702 01c2 23F00103 		bic	r3, r3, #1
+ 703 01c6 C2F89430 		str	r3, [r2, #148]
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 704              		.loc 1 482 7 view .LVU237
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 705              		.loc 1 482 19 is_stmt 0 view .LVU238
+ 706 01ca FFF7FEFF 		bl	HAL_GetTick
+ 707              	.LVL66:
+ 708 01ce 0546     		mov	r5, r0
+ 709              	.LVL67:
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 710              		.loc 1 485 7 is_stmt 1 view .LVU239
+ 711              	.L54:
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 712              		.loc 1 485 48 view .LVU240
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 713              		.loc 1 485 13 is_stmt 0 view .LVU241
+ 714 01d0 354B     		ldr	r3, .L130
+ 715 01d2 D3F89430 		ldr	r3, [r3, #148]
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 716              		.loc 1 485 48 view .LVU242
+ 717 01d6 13F0020F 		tst	r3, #2
+ 718 01da 06D0     		beq	.L50
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 719              		.loc 1 487 9 is_stmt 1 view .LVU243
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 720              		.loc 1 487 13 is_stmt 0 view .LVU244
+ 721 01dc FFF7FEFF 		bl	HAL_GetTick
+ 722              	.LVL68:
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 723              		.loc 1 487 27 view .LVU245
+ 724 01e0 401B     		subs	r0, r0, r5
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 725              		.loc 1 487 11 view .LVU246
+ 726 01e2 0228     		cmp	r0, #2
+ 727 01e4 F4D9     		bls	.L54
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 728              		.loc 1 489 18 view .LVU247
+ 729 01e6 0320     		movs	r0, #3
+ 730 01e8 6AE1     		b	.L27
+ 731              	.LVL69:
+ 732              	.L50:
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 733              		.loc 1 495 3 is_stmt 1 view .LVU248
+ARM GAS  /tmp/ccu53ZgF.s 			page 42
+
+
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 734              		.loc 1 495 26 is_stmt 0 view .LVU249
+ 735 01ea 2368     		ldr	r3, [r4]
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 736              		.loc 1 495 6 view .LVU250
+ 737 01ec 13F0040F 		tst	r3, #4
+ 738 01f0 00F08180 		beq	.L56
+ 739              	.LBB2:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 740              		.loc 1 497 5 is_stmt 1 view .LVU251
+ 741              	.LVL70:
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 742              		.loc 1 500 5 view .LVU252
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 743              		.loc 1 504 5 view .LVU253
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 744              		.loc 1 504 9 is_stmt 0 view .LVU254
+ 745 01f4 2C4B     		ldr	r3, .L130
+ 746 01f6 9B6D     		ldr	r3, [r3, #88]
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 747              		.loc 1 504 41 view .LVU255
+ 748 01f8 13F0805F 		tst	r3, #268435456
+ 749 01fc 36D1     		bne	.L94
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       pwrclkchanged = SET;
+ 750              		.loc 1 506 7 is_stmt 1 view .LVU256
+ 751              	.LBB3:
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       pwrclkchanged = SET;
+ 752              		.loc 1 506 7 view .LVU257
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       pwrclkchanged = SET;
+ 753              		.loc 1 506 7 view .LVU258
+ 754 01fe 2A4B     		ldr	r3, .L130
+ 755 0200 9A6D     		ldr	r2, [r3, #88]
+ 756 0202 42F08052 		orr	r2, r2, #268435456
+ 757 0206 9A65     		str	r2, [r3, #88]
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       pwrclkchanged = SET;
+ 758              		.loc 1 506 7 view .LVU259
+ 759 0208 9B6D     		ldr	r3, [r3, #88]
+ 760 020a 03F08053 		and	r3, r3, #268435456
+ 761 020e 0193     		str	r3, [sp, #4]
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       pwrclkchanged = SET;
+ 762              		.loc 1 506 7 view .LVU260
+ 763 0210 019B     		ldr	r3, [sp, #4]
+ 764              	.LBE3:
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       pwrclkchanged = SET;
+ 765              		.loc 1 506 7 view .LVU261
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 766              		.loc 1 507 7 view .LVU262
+ 767              	.LVL71:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 768              		.loc 1 507 21 is_stmt 0 view .LVU263
+ 769 0212 0125     		movs	r5, #1
+ 770              	.LVL72:
+ 771              	.L57:
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 772              		.loc 1 510 5 is_stmt 1 view .LVU264
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 773              		.loc 1 510 9 is_stmt 0 view .LVU265
+ARM GAS  /tmp/ccu53ZgF.s 			page 43
+
+
+ 774 0214 264B     		ldr	r3, .L130+8
+ 775 0216 1B68     		ldr	r3, [r3]
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 776              		.loc 1 510 8 view .LVU266
+ 777 0218 13F4807F 		tst	r3, #256
+ 778 021c 28D0     		beq	.L122
+ 779              	.L58:
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 780              		.loc 1 528 5 is_stmt 1 view .LVU267
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 781              		.loc 1 528 5 view .LVU268
+ 782 021e A368     		ldr	r3, [r4, #8]
+ 783 0220 012B     		cmp	r3, #1
+ 784 0222 39D0     		beq	.L123
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 785              		.loc 1 528 5 discriminator 2 view .LVU269
+ 786 0224 052B     		cmp	r3, #5
+ 787 0226 45D0     		beq	.L124
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 788              		.loc 1 528 5 discriminator 5 view .LVU270
+ 789 0228 1F4B     		ldr	r3, .L130
+ 790 022a D3F89020 		ldr	r2, [r3, #144]
+ 791 022e 22F00102 		bic	r2, r2, #1
+ 792 0232 C3F89020 		str	r2, [r3, #144]
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 793              		.loc 1 528 5 discriminator 5 view .LVU271
+ 794 0236 D3F89020 		ldr	r2, [r3, #144]
+ 795 023a 22F00402 		bic	r2, r2, #4
+ 796 023e C3F89020 		str	r2, [r3, #144]
+ 797              	.L62:
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 798              		.loc 1 528 5 discriminator 7 view .LVU272
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 799              		.loc 1 531 5 discriminator 7 view .LVU273
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 800              		.loc 1 531 26 is_stmt 0 discriminator 7 view .LVU274
+ 801 0242 A368     		ldr	r3, [r4, #8]
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 802              		.loc 1 531 8 discriminator 7 view .LVU275
+ 803 0244 002B     		cmp	r3, #0
+ 804 0246 43D0     		beq	.L64
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 805              		.loc 1 534 7 is_stmt 1 view .LVU276
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 806              		.loc 1 534 19 is_stmt 0 view .LVU277
+ 807 0248 FFF7FEFF 		bl	HAL_GetTick
+ 808              	.LVL73:
+ 809 024c 0646     		mov	r6, r0
+ 810              	.LVL74:
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 811              		.loc 1 537 7 is_stmt 1 view .LVU278
+ 812              	.L65:
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 813              		.loc 1 537 51 view .LVU279
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 814              		.loc 1 537 14 is_stmt 0 view .LVU280
+ 815 024e 164B     		ldr	r3, .L130
+ARM GAS  /tmp/ccu53ZgF.s 			page 44
+
+
+ 816 0250 D3F89030 		ldr	r3, [r3, #144]
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 817              		.loc 1 537 51 view .LVU281
+ 818 0254 13F0020F 		tst	r3, #2
+ 819 0258 4CD1     		bne	.L67
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 820              		.loc 1 539 9 is_stmt 1 view .LVU282
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 821              		.loc 1 539 13 is_stmt 0 view .LVU283
+ 822 025a FFF7FEFF 		bl	HAL_GetTick
+ 823              	.LVL75:
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 824              		.loc 1 539 27 view .LVU284
+ 825 025e 801B     		subs	r0, r0, r6
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 826              		.loc 1 539 11 view .LVU285
+ 827 0260 41F28833 		movw	r3, #5000
+ 828 0264 9842     		cmp	r0, r3
+ 829 0266 F2D9     		bls	.L65
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 830              		.loc 1 541 18 view .LVU286
+ 831 0268 0320     		movs	r0, #3
+ 832 026a 29E1     		b	.L27
+ 833              	.LVL76:
+ 834              	.L94:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 835              		.loc 1 497 22 view .LVU287
+ 836 026c 0025     		movs	r5, #0
+ 837 026e D1E7     		b	.L57
+ 838              	.LVL77:
+ 839              	.L122:
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 840              		.loc 1 513 7 is_stmt 1 view .LVU288
+ 841 0270 0F4A     		ldr	r2, .L130+8
+ 842 0272 1368     		ldr	r3, [r2]
+ 843 0274 43F48073 		orr	r3, r3, #256
+ 844 0278 1360     		str	r3, [r2]
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 845              		.loc 1 516 7 view .LVU289
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 846              		.loc 1 516 19 is_stmt 0 view .LVU290
+ 847 027a FFF7FEFF 		bl	HAL_GetTick
+ 848              	.LVL78:
+ 849 027e 0646     		mov	r6, r0
+ 850              	.LVL79:
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 851              		.loc 1 518 7 is_stmt 1 view .LVU291
+ 852              	.L59:
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 853              		.loc 1 518 14 view .LVU292
+ 854 0280 0B4B     		ldr	r3, .L130+8
+ 855 0282 1B68     		ldr	r3, [r3]
+ 856 0284 13F4807F 		tst	r3, #256
+ 857 0288 C9D1     		bne	.L58
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 858              		.loc 1 520 9 view .LVU293
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ARM GAS  /tmp/ccu53ZgF.s 			page 45
+
+
+ 859              		.loc 1 520 14 is_stmt 0 view .LVU294
+ 860 028a FFF7FEFF 		bl	HAL_GetTick
+ 861              	.LVL80:
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 862              		.loc 1 520 28 view .LVU295
+ 863 028e 801B     		subs	r0, r0, r6
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 864              		.loc 1 520 12 view .LVU296
+ 865 0290 0228     		cmp	r0, #2
+ 866 0292 F5D9     		bls	.L59
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 867              		.loc 1 522 18 view .LVU297
+ 868 0294 0320     		movs	r0, #3
+ 869 0296 13E1     		b	.L27
+ 870              	.LVL81:
+ 871              	.L123:
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 872              		.loc 1 528 5 is_stmt 1 discriminator 1 view .LVU298
+ 873 0298 034A     		ldr	r2, .L130
+ 874 029a D2F89030 		ldr	r3, [r2, #144]
+ 875 029e 43F00103 		orr	r3, r3, #1
+ 876 02a2 C2F89030 		str	r3, [r2, #144]
+ 877 02a6 CCE7     		b	.L62
+ 878              	.L131:
+ 879              		.align	2
+ 880              	.L130:
+ 881 02a8 00100240 		.word	1073876992
+ 882 02ac 00000000 		.word	uwTickPrio
+ 883 02b0 00700040 		.word	1073770496
+ 884              	.L124:
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 885              		.loc 1 528 5 discriminator 4 view .LVU299
+ 886 02b4 8A4B     		ldr	r3, .L132
+ 887 02b6 D3F89020 		ldr	r2, [r3, #144]
+ 888 02ba 42F00402 		orr	r2, r2, #4
+ 889 02be C3F89020 		str	r2, [r3, #144]
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 890              		.loc 1 528 5 discriminator 4 view .LVU300
+ 891 02c2 D3F89020 		ldr	r2, [r3, #144]
+ 892 02c6 42F00102 		orr	r2, r2, #1
+ 893 02ca C3F89020 		str	r2, [r3, #144]
+ 894 02ce B8E7     		b	.L62
+ 895              	.L64:
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 896              		.loc 1 548 7 view .LVU301
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 897              		.loc 1 548 19 is_stmt 0 view .LVU302
+ 898 02d0 FFF7FEFF 		bl	HAL_GetTick
+ 899              	.LVL82:
+ 900 02d4 0646     		mov	r6, r0
+ 901              	.LVL83:
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 902              		.loc 1 551 7 is_stmt 1 view .LVU303
+ 903              	.L68:
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 904              		.loc 1 551 51 view .LVU304
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ARM GAS  /tmp/ccu53ZgF.s 			page 46
+
+
+ 905              		.loc 1 551 14 is_stmt 0 view .LVU305
+ 906 02d6 824B     		ldr	r3, .L132
+ 907 02d8 D3F89030 		ldr	r3, [r3, #144]
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 908              		.loc 1 551 51 view .LVU306
+ 909 02dc 13F0020F 		tst	r3, #2
+ 910 02e0 08D0     		beq	.L67
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 911              		.loc 1 553 9 is_stmt 1 view .LVU307
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 912              		.loc 1 553 13 is_stmt 0 view .LVU308
+ 913 02e2 FFF7FEFF 		bl	HAL_GetTick
+ 914              	.LVL84:
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 915              		.loc 1 553 27 view .LVU309
+ 916 02e6 801B     		subs	r0, r0, r6
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 917              		.loc 1 553 11 view .LVU310
+ 918 02e8 41F28833 		movw	r3, #5000
+ 919 02ec 9842     		cmp	r0, r3
+ 920 02ee F2D9     		bls	.L68
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 921              		.loc 1 555 18 view .LVU311
+ 922 02f0 0320     		movs	r0, #3
+ 923 02f2 E5E0     		b	.L27
+ 924              	.L67:
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 925              		.loc 1 561 5 is_stmt 1 view .LVU312
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 926              		.loc 1 561 8 is_stmt 0 view .LVU313
+ 927 02f4 E5B9     		cbnz	r5, .L125
+ 928              	.LVL85:
+ 929              	.L56:
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 930              		.loc 1 561 8 view .LVU314
+ 931              	.LBE2:
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 932              		.loc 1 568 3 is_stmt 1 view .LVU315
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 933              		.loc 1 568 25 is_stmt 0 view .LVU316
+ 934 02f6 2368     		ldr	r3, [r4]
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 935              		.loc 1 568 5 view .LVU317
+ 936 02f8 13F0200F 		tst	r3, #32
+ 937 02fc 35D0     		beq	.L70
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 938              		.loc 1 571 5 is_stmt 1 view .LVU318
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 939              		.loc 1 574 5 view .LVU319
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 940              		.loc 1 574 25 is_stmt 0 view .LVU320
+ 941 02fe A369     		ldr	r3, [r4, #24]
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 942              		.loc 1 574 7 view .LVU321
+ 943 0300 E3B1     		cbz	r3, .L71
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 944              		.loc 1 577 7 is_stmt 1 view .LVU322
+ARM GAS  /tmp/ccu53ZgF.s 			page 47
+
+
+ 945 0302 774A     		ldr	r2, .L132
+ 946 0304 D2F89830 		ldr	r3, [r2, #152]
+ 947 0308 43F00103 		orr	r3, r3, #1
+ 948 030c C2F89830 		str	r3, [r2, #152]
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 949              		.loc 1 580 7 view .LVU323
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 950              		.loc 1 580 19 is_stmt 0 view .LVU324
+ 951 0310 FFF7FEFF 		bl	HAL_GetTick
+ 952              	.LVL86:
+ 953 0314 0546     		mov	r5, r0
+ 954              	.LVL87:
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 955              		.loc 1 583 7 is_stmt 1 view .LVU325
+ 956              	.L72:
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 957              		.loc 1 583 54 view .LVU326
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 958              		.loc 1 583 13 is_stmt 0 view .LVU327
+ 959 0316 724B     		ldr	r3, .L132
+ 960 0318 D3F89830 		ldr	r3, [r3, #152]
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 961              		.loc 1 583 54 view .LVU328
+ 962 031c 13F0020F 		tst	r3, #2
+ 963 0320 23D1     		bne	.L70
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 964              		.loc 1 585 9 is_stmt 1 view .LVU329
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 965              		.loc 1 585 13 is_stmt 0 view .LVU330
+ 966 0322 FFF7FEFF 		bl	HAL_GetTick
+ 967              	.LVL88:
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 968              		.loc 1 585 27 view .LVU331
+ 969 0326 401B     		subs	r0, r0, r5
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 970              		.loc 1 585 11 view .LVU332
+ 971 0328 0228     		cmp	r0, #2
+ 972 032a F4D9     		bls	.L72
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 973              		.loc 1 587 18 view .LVU333
+ 974 032c 0320     		movs	r0, #3
+ 975 032e C7E0     		b	.L27
+ 976              	.LVL89:
+ 977              	.L125:
+ 978              	.LBB4:
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 979              		.loc 1 563 7 is_stmt 1 view .LVU334
+ 980 0330 6B4A     		ldr	r2, .L132
+ 981 0332 936D     		ldr	r3, [r2, #88]
+ 982 0334 23F08053 		bic	r3, r3, #268435456
+ 983 0338 9365     		str	r3, [r2, #88]
+ 984 033a DCE7     		b	.L56
+ 985              	.LVL90:
+ 986              	.L71:
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 987              		.loc 1 563 7 is_stmt 0 view .LVU335
+ 988              	.LBE4:
+ARM GAS  /tmp/ccu53ZgF.s 			page 48
+
+
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 989              		.loc 1 594 7 is_stmt 1 view .LVU336
+ 990 033c 684A     		ldr	r2, .L132
+ 991 033e D2F89830 		ldr	r3, [r2, #152]
+ 992 0342 23F00103 		bic	r3, r3, #1
+ 993 0346 C2F89830 		str	r3, [r2, #152]
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 994              		.loc 1 597 7 view .LVU337
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 995              		.loc 1 597 19 is_stmt 0 view .LVU338
+ 996 034a FFF7FEFF 		bl	HAL_GetTick
+ 997              	.LVL91:
+ 998 034e 0546     		mov	r5, r0
+ 999              	.LVL92:
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1000              		.loc 1 600 7 is_stmt 1 view .LVU339
+ 1001              	.L74:
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1002              		.loc 1 600 54 view .LVU340
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1003              		.loc 1 600 13 is_stmt 0 view .LVU341
+ 1004 0350 634B     		ldr	r3, .L132
+ 1005 0352 D3F89830 		ldr	r3, [r3, #152]
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1006              		.loc 1 600 54 view .LVU342
+ 1007 0356 13F0020F 		tst	r3, #2
+ 1008 035a 06D0     		beq	.L70
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1009              		.loc 1 602 9 is_stmt 1 view .LVU343
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1010              		.loc 1 602 13 is_stmt 0 view .LVU344
+ 1011 035c FFF7FEFF 		bl	HAL_GetTick
+ 1012              	.LVL93:
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1013              		.loc 1 602 27 view .LVU345
+ 1014 0360 401B     		subs	r0, r0, r5
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1015              		.loc 1 602 11 view .LVU346
+ 1016 0362 0228     		cmp	r0, #2
+ 1017 0364 F4D9     		bls	.L74
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 1018              		.loc 1 604 18 view .LVU347
+ 1019 0366 0320     		movs	r0, #3
+ 1020 0368 AAE0     		b	.L27
+ 1021              	.LVL94:
+ 1022              	.L70:
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1023              		.loc 1 612 3 is_stmt 1 view .LVU348
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1024              		.loc 1 614 3 view .LVU349
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1025              		.loc 1 614 29 is_stmt 0 view .LVU350
+ 1026 036a E369     		ldr	r3, [r4, #28]
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1027              		.loc 1 614 6 view .LVU351
+ 1028 036c 002B     		cmp	r3, #0
+ 1029 036e 00F0A680 		beq	.L100
+ARM GAS  /tmp/ccu53ZgF.s 			page 49
+
+
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1030              		.loc 1 617 5 is_stmt 1 view .LVU352
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1031              		.loc 1 617 9 is_stmt 0 view .LVU353
+ 1032 0372 5B4A     		ldr	r2, .L132
+ 1033 0374 9268     		ldr	r2, [r2, #8]
+ 1034 0376 02F00C02 		and	r2, r2, #12
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1035              		.loc 1 617 8 view .LVU354
+ 1036 037a 0C2A     		cmp	r2, #12
+ 1037 037c 69D0     		beq	.L76
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1038              		.loc 1 619 7 is_stmt 1 view .LVU355
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1039              		.loc 1 619 10 is_stmt 0 view .LVU356
+ 1040 037e 022B     		cmp	r3, #2
+ 1041 0380 1DD0     		beq	.L126
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1042              		.loc 1 673 9 is_stmt 1 view .LVU357
+ 1043 0382 574B     		ldr	r3, .L132
+ 1044 0384 1A68     		ldr	r2, [r3]
+ 1045 0386 22F08072 		bic	r2, r2, #16777216
+ 1046 038a 1A60     		str	r2, [r3]
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
+ 1047              		.loc 1 676 11 view .LVU358
+ 1048 038c DA68     		ldr	r2, [r3, #12]
+ 1049 038e 22F00302 		bic	r2, r2, #3
+ 1050 0392 DA60     		str	r2, [r3, #12]
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1051              		.loc 1 677 9 view .LVU359
+ 1052 0394 DA68     		ldr	r2, [r3, #12]
+ 1053 0396 22F08872 		bic	r2, r2, #17825792
+ 1054 039a 22F48032 		bic	r2, r2, #65536
+ 1055 039e DA60     		str	r2, [r3, #12]
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1056              		.loc 1 680 9 view .LVU360
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1057              		.loc 1 680 21 is_stmt 0 view .LVU361
+ 1058 03a0 FFF7FEFF 		bl	HAL_GetTick
+ 1059              	.LVL95:
+ 1060 03a4 0446     		mov	r4, r0
+ 1061              	.LVL96:
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1062              		.loc 1 683 9 is_stmt 1 view .LVU362
+ 1063              	.L82:
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1064              		.loc 1 683 49 view .LVU363
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1065              		.loc 1 683 16 is_stmt 0 view .LVU364
+ 1066 03a6 4E4B     		ldr	r3, .L132
+ 1067 03a8 1B68     		ldr	r3, [r3]
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1068              		.loc 1 683 49 view .LVU365
+ 1069 03aa 13F0007F 		tst	r3, #33554432
+ 1070 03ae 4ED0     		beq	.L127
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 1071              		.loc 1 685 11 is_stmt 1 view .LVU366
+ARM GAS  /tmp/ccu53ZgF.s 			page 50
+
+
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 1072              		.loc 1 685 16 is_stmt 0 view .LVU367
+ 1073 03b0 FFF7FEFF 		bl	HAL_GetTick
+ 1074              	.LVL97:
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 1075              		.loc 1 685 30 view .LVU368
+ 1076 03b4 001B     		subs	r0, r0, r4
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 1077              		.loc 1 685 14 view .LVU369
+ 1078 03b6 0228     		cmp	r0, #2
+ 1079 03b8 F5D9     		bls	.L82
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 1080              		.loc 1 687 20 view .LVU370
+ 1081 03ba 0320     		movs	r0, #3
+ 1082 03bc 80E0     		b	.L27
+ 1083              	.LVL98:
+ 1084              	.L126:
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+ 1085              		.loc 1 622 9 is_stmt 1 view .LVU371
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+ 1086              		.loc 1 623 9 view .LVU372
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+ 1087              		.loc 1 624 9 view .LVU373
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+ 1088              		.loc 1 625 9 view .LVU374
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+ 1089              		.loc 1 626 9 view .LVU375
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1090              		.loc 1 627 9 view .LVU376
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1091              		.loc 1 630 9 view .LVU377
+ 1092 03be 484A     		ldr	r2, .L132
+ 1093 03c0 1368     		ldr	r3, [r2]
+ 1094 03c2 23F08073 		bic	r3, r3, #16777216
+ 1095 03c6 1360     		str	r3, [r2]
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1096              		.loc 1 633 9 view .LVU378
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1097              		.loc 1 633 21 is_stmt 0 view .LVU379
+ 1098 03c8 FFF7FEFF 		bl	HAL_GetTick
+ 1099              	.LVL99:
+ 1100 03cc 0546     		mov	r5, r0
+ 1101              	.LVL100:
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1102              		.loc 1 636 9 is_stmt 1 view .LVU380
+ 1103              	.L78:
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1104              		.loc 1 636 49 view .LVU381
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1105              		.loc 1 636 16 is_stmt 0 view .LVU382
+ 1106 03ce 444B     		ldr	r3, .L132
+ 1107 03d0 1B68     		ldr	r3, [r3]
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1108              		.loc 1 636 49 view .LVU383
+ 1109 03d2 13F0007F 		tst	r3, #33554432
+ 1110 03d6 06D0     		beq	.L128
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ARM GAS  /tmp/ccu53ZgF.s 			page 51
+
+
+ 1111              		.loc 1 638 11 is_stmt 1 view .LVU384
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 1112              		.loc 1 638 16 is_stmt 0 view .LVU385
+ 1113 03d8 FFF7FEFF 		bl	HAL_GetTick
+ 1114              	.LVL101:
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 1115              		.loc 1 638 30 view .LVU386
+ 1116 03dc 401B     		subs	r0, r0, r5
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 1117              		.loc 1 638 14 view .LVU387
+ 1118 03de 0228     		cmp	r0, #2
+ 1119 03e0 F5D9     		bls	.L78
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 1120              		.loc 1 640 20 view .LVU388
+ 1121 03e2 0320     		movs	r0, #3
+ 1122 03e4 6CE0     		b	.L27
+ 1123              	.L128:
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLM,
+ 1124              		.loc 1 645 9 is_stmt 1 view .LVU389
+ 1125 03e6 3E4A     		ldr	r2, .L132
+ 1126 03e8 D368     		ldr	r3, [r2, #12]
+ 1127 03ea 3E49     		ldr	r1, .L132+4
+ 1128 03ec 1940     		ands	r1, r1, r3
+ 1129 03ee 236A     		ldr	r3, [r4, #32]
+ 1130 03f0 606A     		ldr	r0, [r4, #36]
+ 1131 03f2 0138     		subs	r0, r0, #1
+ 1132 03f4 43EA0013 		orr	r3, r3, r0, lsl #4
+ 1133 03f8 A06A     		ldr	r0, [r4, #40]
+ 1134 03fa 43EA0023 		orr	r3, r3, r0, lsl #8
+ 1135 03fe 206B     		ldr	r0, [r4, #48]
+ 1136 0400 4008     		lsrs	r0, r0, #1
+ 1137 0402 0138     		subs	r0, r0, #1
+ 1138 0404 43EA4053 		orr	r3, r3, r0, lsl #21
+ 1139 0408 606B     		ldr	r0, [r4, #52]
+ 1140 040a 4008     		lsrs	r0, r0, #1
+ 1141 040c 0138     		subs	r0, r0, #1
+ 1142 040e 43EA4063 		orr	r3, r3, r0, lsl #25
+ 1143 0412 E06A     		ldr	r0, [r4, #44]
+ 1144 0414 43EAC063 		orr	r3, r3, r0, lsl #27
+ 1145 0418 1943     		orrs	r1, r1, r3
+ 1146 041a D160     		str	r1, [r2, #12]
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1147              		.loc 1 653 9 view .LVU390
+ 1148 041c 1368     		ldr	r3, [r2]
+ 1149 041e 43F08073 		orr	r3, r3, #16777216
+ 1150 0422 1360     		str	r3, [r2]
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1151              		.loc 1 656 10 view .LVU391
+ 1152 0424 D368     		ldr	r3, [r2, #12]
+ 1153 0426 43F08073 		orr	r3, r3, #16777216
+ 1154 042a D360     		str	r3, [r2, #12]
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1155              		.loc 1 659 9 view .LVU392
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1156              		.loc 1 659 21 is_stmt 0 view .LVU393
+ 1157 042c FFF7FEFF 		bl	HAL_GetTick
+ 1158              	.LVL102:
+ARM GAS  /tmp/ccu53ZgF.s 			page 52
+
+
+ 1159 0430 0446     		mov	r4, r0
+ 1160              	.LVL103:
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1161              		.loc 1 662 9 is_stmt 1 view .LVU394
+ 1162              	.L80:
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1163              		.loc 1 662 49 view .LVU395
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1164              		.loc 1 662 16 is_stmt 0 view .LVU396
+ 1165 0432 2B4B     		ldr	r3, .L132
+ 1166 0434 1B68     		ldr	r3, [r3]
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1167              		.loc 1 662 49 view .LVU397
+ 1168 0436 13F0007F 		tst	r3, #33554432
+ 1169 043a 06D1     		bne	.L129
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 1170              		.loc 1 664 11 is_stmt 1 view .LVU398
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 1171              		.loc 1 664 16 is_stmt 0 view .LVU399
+ 1172 043c FFF7FEFF 		bl	HAL_GetTick
+ 1173              	.LVL104:
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 1174              		.loc 1 664 30 view .LVU400
+ 1175 0440 001B     		subs	r0, r0, r4
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           {
+ 1176              		.loc 1 664 14 view .LVU401
+ 1177 0442 0228     		cmp	r0, #2
+ 1178 0444 F5D9     		bls	.L80
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           }
+ 1179              		.loc 1 666 20 view .LVU402
+ 1180 0446 0320     		movs	r0, #3
+ 1181 0448 3AE0     		b	.L27
+ 1182              	.L129:
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 1183              		.loc 1 716 10 view .LVU403
+ 1184 044a 0020     		movs	r0, #0
+ 1185 044c 38E0     		b	.L27
+ 1186              	.L127:
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 1187              		.loc 1 716 10 view .LVU404
+ 1188 044e 0020     		movs	r0, #0
+ 1189 0450 36E0     		b	.L27
+ 1190              	.LVL105:
+ 1191              	.L76:
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1192              		.loc 1 695 7 is_stmt 1 view .LVU405
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1193              		.loc 1 695 9 is_stmt 0 view .LVU406
+ 1194 0452 012B     		cmp	r3, #1
+ 1195 0454 36D0     		beq	.L104
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 1196              		.loc 1 702 7 is_stmt 1 view .LVU407
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 1197              		.loc 1 702 21 is_stmt 0 view .LVU408
+ 1198 0456 224B     		ldr	r3, .L132
+ 1199 0458 DB68     		ldr	r3, [r3, #12]
+ 1200              	.LVL106:
+ARM GAS  /tmp/ccu53ZgF.s 			page 53
+
+
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC
+ 1201              		.loc 1 703 7 is_stmt 1 view .LVU409
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC
+ 1202              		.loc 1 703 11 is_stmt 0 view .LVU410
+ 1203 045a 03F00301 		and	r1, r3, #3
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC
+ 1204              		.loc 1 703 80 view .LVU411
+ 1205 045e 226A     		ldr	r2, [r4, #32]
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC
+ 1206              		.loc 1 703 9 view .LVU412
+ 1207 0460 9142     		cmp	r1, r2
+ 1208 0462 31D1     		bne	.L105
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFG
+ 1209              		.loc 1 704 11 discriminator 1 view .LVU413
+ 1210 0464 03F0F002 		and	r2, r3, #240
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFG
+ 1211              		.loc 1 704 81 discriminator 1 view .LVU414
+ 1212 0468 616A     		ldr	r1, [r4, #36]
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFG
+ 1213              		.loc 1 704 88 discriminator 1 view .LVU415
+ 1214 046a 0139     		subs	r1, r1, #1
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC
+ 1215              		.loc 1 703 92 discriminator 1 view .LVU416
+ 1216 046c B2EB011F 		cmp	r2, r1, lsl #4
+ 1217 0470 2CD1     		bne	.L106
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLL
+ 1218              		.loc 1 705 11 view .LVU417
+ 1219 0472 03F4FE42 		and	r2, r3, #32512
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLL
+ 1220              		.loc 1 705 80 view .LVU418
+ 1221 0476 A16A     		ldr	r1, [r4, #40]
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFG
+ 1222              		.loc 1 704 120 view .LVU419
+ 1223 0478 B2EB012F 		cmp	r2, r1, lsl #8
+ 1224 047c 28D1     		bne	.L107
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U
+ 1225              		.loc 1 706 11 view .LVU420
+ 1226 047e 03F07842 		and	r2, r3, #-134217728
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U
+ 1227              		.loc 1 706 83 view .LVU421
+ 1228 0482 E16A     		ldr	r1, [r4, #44]
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLL
+ 1229              		.loc 1 705 113 view .LVU422
+ 1230 0484 B2EBC16F 		cmp	r2, r1, lsl #27
+ 1231 0488 24D1     		bne	.L108
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U
+ 1232              		.loc 1 707 11 view .LVU423
+ 1233 048a 03F4C001 		and	r1, r3, #6291456
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U
+ 1234              		.loc 1 707 82 view .LVU424
+ 1235 048e 226B     		ldr	r2, [r4, #48]
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U
+ 1236              		.loc 1 707 89 view .LVU425
+ 1237 0490 5208     		lsrs	r2, r2, #1
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U
+ 1238              		.loc 1 707 96 view .LVU426
+ 1239 0492 013A     		subs	r2, r2, #1
+ARM GAS  /tmp/ccu53ZgF.s 			page 54
+
+
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U
+ 1240              		.loc 1 706 119 view .LVU427
+ 1241 0494 B1EB425F 		cmp	r1, r2, lsl #21
+ 1242 0498 1ED1     		bne	.L109
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1243              		.loc 1 708 11 view .LVU428
+ 1244 049a 03F0C063 		and	r3, r3, #100663296
+ 1245              	.LVL107:
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1246              		.loc 1 708 82 view .LVU429
+ 1247 049e 626B     		ldr	r2, [r4, #52]
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1248              		.loc 1 708 89 view .LVU430
+ 1249 04a0 5208     		lsrs	r2, r2, #1
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1250              		.loc 1 708 96 view .LVU431
+ 1251 04a2 013A     		subs	r2, r2, #1
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U
+ 1252              		.loc 1 707 128 view .LVU432
+ 1253 04a4 B3EB426F 		cmp	r3, r2, lsl #25
+ 1254 04a8 18D1     		bne	.L110
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 1255              		.loc 1 716 10 view .LVU433
+ 1256 04aa 0020     		movs	r0, #0
+ 1257 04ac 08E0     		b	.L27
+ 1258              	.LVL108:
+ 1259              	.L84:
+ 1260              	.LCFI3:
+ 1261              		.cfi_def_cfa_offset 0
+ 1262              		.cfi_restore 4
+ 1263              		.cfi_restore 5
+ 1264              		.cfi_restore 6
+ 1265              		.cfi_restore 14
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1266              		.loc 1 321 12 view .LVU434
+ 1267 04ae 0120     		movs	r0, #1
+ 1268              	.LVL109:
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1269              		.loc 1 717 1 view .LVU435
+ 1270 04b0 7047     		bx	lr
+ 1271              	.LVL110:
+ 1272              	.L118:
+ 1273              	.LCFI4:
+ 1274              		.cfi_def_cfa_offset 24
+ 1275              		.cfi_offset 4, -16
+ 1276              		.cfi_offset 5, -12
+ 1277              		.cfi_offset 6, -8
+ 1278              		.cfi_offset 14, -4
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 1279              		.loc 1 341 16 view .LVU436
+ 1280 04b2 0120     		movs	r0, #1
+ 1281              	.LVL111:
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 1282              		.loc 1 341 16 view .LVU437
+ 1283 04b4 04E0     		b	.L27
+ 1284              	.L88:
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ARM GAS  /tmp/ccu53ZgF.s 			page 55
+
+
+ 1285              		.loc 1 395 16 view .LVU438
+ 1286 04b6 0120     		movs	r0, #1
+ 1287 04b8 02E0     		b	.L27
+ 1288              	.LVL112:
+ 1289              	.L121:
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 1290              		.loc 1 406 18 view .LVU439
+ 1291 04ba 0120     		movs	r0, #1
+ 1292 04bc 00E0     		b	.L27
+ 1293              	.LVL113:
+ 1294              	.L100:
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 1295              		.loc 1 716 10 view .LVU440
+ 1296 04be 0020     		movs	r0, #0
+ 1297              	.LVL114:
+ 1298              	.L27:
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1299              		.loc 1 717 1 view .LVU441
+ 1300 04c0 02B0     		add	sp, sp, #8
+ 1301              	.LCFI5:
+ 1302              		.cfi_remember_state
+ 1303              		.cfi_def_cfa_offset 16
+ 1304              		@ sp needed
+ 1305 04c2 70BD     		pop	{r4, r5, r6, pc}
+ 1306              	.LVL115:
+ 1307              	.L104:
+ 1308              	.LCFI6:
+ 1309              		.cfi_restore_state
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 1310              		.loc 1 697 16 view .LVU442
+ 1311 04c4 0120     		movs	r0, #1
+ 1312 04c6 FBE7     		b	.L27
+ 1313              	.LVL116:
+ 1314              	.L105:
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 1315              		.loc 1 710 16 view .LVU443
+ 1316 04c8 0120     		movs	r0, #1
+ 1317 04ca F9E7     		b	.L27
+ 1318              	.L106:
+ 1319 04cc 0120     		movs	r0, #1
+ 1320 04ce F7E7     		b	.L27
+ 1321              	.L107:
+ 1322 04d0 0120     		movs	r0, #1
+ 1323 04d2 F5E7     		b	.L27
+ 1324              	.L108:
+ 1325 04d4 0120     		movs	r0, #1
+ 1326 04d6 F3E7     		b	.L27
+ 1327              	.L109:
+ 1328 04d8 0120     		movs	r0, #1
+ 1329 04da F1E7     		b	.L27
+ 1330              	.LVL117:
+ 1331              	.L110:
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 1332              		.loc 1 710 16 view .LVU444
+ 1333 04dc 0120     		movs	r0, #1
+ 1334 04de EFE7     		b	.L27
+ 1335              	.L133:
+ARM GAS  /tmp/ccu53ZgF.s 			page 56
+
+
+ 1336              		.align	2
+ 1337              	.L132:
+ 1338 04e0 00100240 		.word	1073876992
+ 1339 04e4 0C809F01 		.word	27230220
+ 1340              		.cfi_endproc
+ 1341              	.LFE330:
+ 1343              		.section	.text.HAL_RCC_MCOConfig,"ax",%progbits
+ 1344              		.align	1
+ 1345              		.global	HAL_RCC_MCOConfig
+ 1346              		.syntax unified
+ 1347              		.thumb
+ 1348              		.thumb_func
+ 1350              	HAL_RCC_MCOConfig:
+ 1351              	.LVL118:
+ 1352              	.LFB332:
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   GPIO_InitTypeDef gpio_initstruct;
+ 1353              		.loc 1 996 1 is_stmt 1 view -0
+ 1354              		.cfi_startproc
+ 1355              		@ args = 0, pretend = 0, frame = 24
+ 1356              		@ frame_needed = 0, uses_anonymous_args = 0
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   GPIO_InitTypeDef gpio_initstruct;
+ 1357              		.loc 1 996 1 is_stmt 0 view .LVU446
+ 1358 0000 70B5     		push	{r4, r5, r6, lr}
+ 1359              	.LCFI7:
+ 1360              		.cfi_def_cfa_offset 16
+ 1361              		.cfi_offset 4, -16
+ 1362              		.cfi_offset 5, -12
+ 1363              		.cfi_offset 6, -8
+ 1364              		.cfi_offset 14, -4
+ 1365 0002 86B0     		sub	sp, sp, #24
+ 1366              	.LCFI8:
+ 1367              		.cfi_def_cfa_offset 40
+ 1368 0004 0C46     		mov	r4, r1
+ 1369 0006 1546     		mov	r5, r2
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t mcoindex;
+ 1370              		.loc 1 997 3 is_stmt 1 view .LVU447
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t mco_gpio_index;
+ 1371              		.loc 1 998 3 view .LVU448
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   GPIO_TypeDef * mco_gpio_port;
+ 1372              		.loc 1 999 3 view .LVU449
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1373              		.loc 1 1000 3 view .LVU450
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1374              		.loc 1 1003 3 view .LVU451
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   gpio_initstruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
+ 1375              		.loc 1 1006 3 view .LVU452
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   gpio_initstruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
+ 1376              		.loc 1 1006 29 is_stmt 0 view .LVU453
+ 1377 0008 0223     		movs	r3, #2
+ 1378 000a 0293     		str	r3, [sp, #8]
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   gpio_initstruct.Pull      = GPIO_NOPULL;
+ 1379              		.loc 1 1007 3 is_stmt 1 view .LVU454
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   gpio_initstruct.Pull      = GPIO_NOPULL;
+ 1380              		.loc 1 1007 29 is_stmt 0 view .LVU455
+ 1381 000c 0323     		movs	r3, #3
+ 1382 000e 0493     		str	r3, [sp, #16]
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ARM GAS  /tmp/ccu53ZgF.s 			page 57
+
+
+ 1383              		.loc 1 1008 3 is_stmt 1 view .LVU456
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1384              		.loc 1 1008 29 is_stmt 0 view .LVU457
+ 1385 0010 0023     		movs	r3, #0
+ 1386 0012 0393     		str	r3, [sp, #12]
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1387              		.loc 1 1011 3 is_stmt 1 view .LVU458
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1388              		.loc 1 1011 12 is_stmt 0 view .LVU459
+ 1389 0014 00F08056 		and	r6, r0, #268435456
+ 1390              	.LVL119:
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1391              		.loc 1 1014 3 is_stmt 1 view .LVU460
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1392              		.loc 1 1014 36 is_stmt 0 view .LVU461
+ 1393 0018 C0F3034C 		ubfx	ip, r0, #16, #4
+ 1394 001c 0CF5901E 		add	lr, ip, #1179648
+ 1395              	.LVL120:
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index ));
+ 1396              		.loc 1 1017 3 is_stmt 1 view .LVU462
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1397              		.loc 1 1018 3 view .LVU463
+ 1398 0020 0D4A     		ldr	r2, .L137
+ 1399              	.LVL121:
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1400              		.loc 1 1018 3 is_stmt 0 view .LVU464
+ 1401 0022 D36C     		ldr	r3, [r2, #76]
+ 1402 0024 0121     		movs	r1, #1
+ 1403              	.LVL122:
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1404              		.loc 1 1018 3 view .LVU465
+ 1405 0026 01FA0CF1 		lsl	r1, r1, ip
+ 1406 002a 0B43     		orrs	r3, r3, r1
+ 1407 002c D364     		str	r3, [r2, #76]
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx);
+ 1408              		.loc 1 1021 3 is_stmt 1 view .LVU466
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx);
+ 1409              		.loc 1 1021 25 is_stmt 0 view .LVU467
+ 1410 002e 83B2     		uxth	r3, r0
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx);
+ 1411              		.loc 1 1021 23 view .LVU468
+ 1412 0030 0193     		str	r3, [sp, #4]
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct);
+ 1413              		.loc 1 1022 3 is_stmt 1 view .LVU469
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct);
+ 1414              		.loc 1 1022 31 is_stmt 0 view .LVU470
+ 1415 0032 C0F30750 		ubfx	r0, r0, #20, #8
+ 1416              	.LVL123:
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct);
+ 1417              		.loc 1 1022 29 view .LVU471
+ 1418 0036 0590     		str	r0, [sp, #20]
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1419              		.loc 1 1023 3 is_stmt 1 view .LVU472
+ 1420 0038 01A9     		add	r1, sp, #4
+ 1421 003a 4FEA8E20 		lsl	r0, lr, #10
+ 1422              	.LVL124:
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ARM GAS  /tmp/ccu53ZgF.s 			page 58
+
+
+ 1423              		.loc 1 1023 3 is_stmt 0 view .LVU473
+ 1424 003e FFF7FEFF 		bl	HAL_GPIO_Init
+ 1425              	.LVL125:
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1426              		.loc 1 1025 4 is_stmt 1 view .LVU474
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1427              		.loc 1 1025 7 is_stmt 0 view .LVU475
+ 1428 0042 36B9     		cbnz	r6, .L134
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+ 1429              		.loc 1 1027 5 is_stmt 1 view .LVU476
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */
+ 1430              		.loc 1 1028 5 view .LVU477
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1431              		.loc 1 1030 5 view .LVU478
+ 1432 0044 044A     		ldr	r2, .L137
+ 1433 0046 9368     		ldr	r3, [r2, #8]
+ 1434 0048 23F0FE43 		bic	r3, r3, #2130706432
+ 1435 004c 2C43     		orrs	r4, r4, r5
+ 1436              	.LVL126:
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1437              		.loc 1 1030 5 is_stmt 0 view .LVU479
+ 1438 004e 1C43     		orrs	r4, r4, r3
+ 1439 0050 9460     		str	r4, [r2, #8]
+ 1440              	.L134:
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1441              		.loc 1 1032 1 view .LVU480
+ 1442 0052 06B0     		add	sp, sp, #24
+ 1443              	.LCFI9:
+ 1444              		.cfi_def_cfa_offset 16
+ 1445              		@ sp needed
+ 1446 0054 70BD     		pop	{r4, r5, r6, pc}
+ 1447              	.LVL127:
+ 1448              	.L138:
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1449              		.loc 1 1032 1 view .LVU481
+ 1450 0056 00BF     		.align	2
+ 1451              	.L137:
+ 1452 0058 00100240 		.word	1073876992
+ 1453              		.cfi_endproc
+ 1454              	.LFE332:
+ 1456              		.section	.text.HAL_RCC_GetSysClockFreq,"ax",%progbits
+ 1457              		.align	1
+ 1458              		.global	HAL_RCC_GetSysClockFreq
+ 1459              		.syntax unified
+ 1460              		.thumb
+ 1461              		.thumb_func
+ 1463              	HAL_RCC_GetSysClockFreq:
+ 1464              	.LFB333:
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t pllvco, pllsource, pllr, pllm;
+ 1465              		.loc 1 1065 1 is_stmt 1 view -0
+ 1466              		.cfi_startproc
+ 1467              		@ args = 0, pretend = 0, frame = 0
+ 1468              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1469              		@ link register save eliminated.
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t sysclockfreq;
+ 1470              		.loc 1 1066 3 view .LVU483
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ARM GAS  /tmp/ccu53ZgF.s 			page 59
+
+
+ 1471              		.loc 1 1067 3 view .LVU484
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1472              		.loc 1 1069 3 view .LVU485
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1473              		.loc 1 1069 7 is_stmt 0 view .LVU486
+ 1474 0000 1E4B     		ldr	r3, .L148
+ 1475 0002 9B68     		ldr	r3, [r3, #8]
+ 1476 0004 03F00C03 		and	r3, r3, #12
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1477              		.loc 1 1069 6 view .LVU487
+ 1478 0008 042B     		cmp	r3, #4
+ 1479 000a 33D0     		beq	.L143
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1480              		.loc 1 1074 8 is_stmt 1 view .LVU488
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1481              		.loc 1 1074 12 is_stmt 0 view .LVU489
+ 1482 000c 1B4B     		ldr	r3, .L148
+ 1483 000e 9B68     		ldr	r3, [r3, #8]
+ 1484 0010 03F00C03 		and	r3, r3, #12
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1485              		.loc 1 1074 11 view .LVU490
+ 1486 0014 082B     		cmp	r3, #8
+ 1487 0016 2FD0     		beq	.L144
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1488              		.loc 1 1079 8 is_stmt 1 view .LVU491
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1489              		.loc 1 1079 12 is_stmt 0 view .LVU492
+ 1490 0018 184B     		ldr	r3, .L148
+ 1491 001a 9B68     		ldr	r3, [r3, #8]
+ 1492 001c 03F00C03 		and	r3, r3, #12
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1493              		.loc 1 1079 11 view .LVU493
+ 1494 0020 0C2B     		cmp	r3, #12
+ 1495 0022 01D0     		beq	.L146
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1496              		.loc 1 1105 18 view .LVU494
+ 1497 0024 0020     		movs	r0, #0
+ 1498              	.LVL128:
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 1499              		.loc 1 1108 3 is_stmt 1 view .LVU495
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1500              		.loc 1 1109 1 is_stmt 0 view .LVU496
+ 1501 0026 7047     		bx	lr
+ 1502              	.LVL129:
+ 1503              	.L146:
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
+ 1504              		.loc 1 1086 5 is_stmt 1 view .LVU497
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
+ 1505              		.loc 1 1086 17 is_stmt 0 view .LVU498
+ 1506 0028 144B     		ldr	r3, .L148
+ 1507 002a DA68     		ldr	r2, [r3, #12]
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
+ 1508              		.loc 1 1086 15 view .LVU499
+ 1509 002c 02F00302 		and	r2, r2, #3
+ 1510              	.LVL130:
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1511              		.loc 1 1087 5 is_stmt 1 view .LVU500
+ARM GAS  /tmp/ccu53ZgF.s 			page 60
+
+
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1512              		.loc 1 1087 13 is_stmt 0 view .LVU501
+ 1513 0030 DB68     		ldr	r3, [r3, #12]
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1514              		.loc 1 1087 54 view .LVU502
+ 1515 0032 C3F30313 		ubfx	r3, r3, #4, #4
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1516              		.loc 1 1087 10 view .LVU503
+ 1517 0036 0133     		adds	r3, r3, #1
+ 1518              	.LVL131:
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1519              		.loc 1 1089 5 is_stmt 1 view .LVU504
+ 1520 0038 032A     		cmp	r2, #3
+ 1521 003a 11D0     		beq	.L147
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+ 1522              		.loc 1 1097 7 view .LVU505
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+ 1523              		.loc 1 1097 27 is_stmt 0 view .LVU506
+ 1524 003c 1048     		ldr	r0, .L148+4
+ 1525 003e B0FBF3F0 		udiv	r0, r0, r3
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+ 1526              		.loc 1 1097 38 view .LVU507
+ 1527 0042 0E4B     		ldr	r3, .L148
+ 1528              	.LVL132:
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+ 1529              		.loc 1 1097 38 view .LVU508
+ 1530 0044 DB68     		ldr	r3, [r3, #12]
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+ 1531              		.loc 1 1097 79 view .LVU509
+ 1532 0046 C3F30623 		ubfx	r3, r3, #8, #7
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+ 1533              		.loc 1 1097 14 view .LVU510
+ 1534 004a 03FB00F0 		mul	r0, r3, r0
+ 1535              	.LVL133:
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 1536              		.loc 1 1098 7 is_stmt 1 view .LVU511
+ 1537              	.L142:
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     sysclockfreq = pllvco/pllr;
+ 1538              		.loc 1 1100 5 view .LVU512
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     sysclockfreq = pllvco/pllr;
+ 1539              		.loc 1 1100 14 is_stmt 0 view .LVU513
+ 1540 004e 0B4B     		ldr	r3, .L148
+ 1541 0050 DB68     		ldr	r3, [r3, #12]
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     sysclockfreq = pllvco/pllr;
+ 1542              		.loc 1 1100 55 view .LVU514
+ 1543 0052 C3F34163 		ubfx	r3, r3, #25, #2
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     sysclockfreq = pllvco/pllr;
+ 1544              		.loc 1 1100 80 view .LVU515
+ 1545 0056 0133     		adds	r3, r3, #1
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     sysclockfreq = pllvco/pllr;
+ 1546              		.loc 1 1100 10 view .LVU516
+ 1547 0058 5B00     		lsls	r3, r3, #1
+ 1548              	.LVL134:
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1549              		.loc 1 1101 5 is_stmt 1 view .LVU517
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1550              		.loc 1 1101 18 is_stmt 0 view .LVU518
+ARM GAS  /tmp/ccu53ZgF.s 			page 61
+
+
+ 1551 005a B0FBF3F0 		udiv	r0, r0, r3
+ 1552              	.LVL135:
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1553              		.loc 1 1101 18 view .LVU519
+ 1554 005e 7047     		bx	lr
+ 1555              	.LVL136:
+ 1556              	.L147:
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+ 1557              		.loc 1 1092 7 is_stmt 1 view .LVU520
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+ 1558              		.loc 1 1092 27 is_stmt 0 view .LVU521
+ 1559 0060 0848     		ldr	r0, .L148+8
+ 1560 0062 B0FBF3F0 		udiv	r0, r0, r3
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+ 1561              		.loc 1 1092 38 view .LVU522
+ 1562 0066 054B     		ldr	r3, .L148
+ 1563              	.LVL137:
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+ 1564              		.loc 1 1092 38 view .LVU523
+ 1565 0068 DB68     		ldr	r3, [r3, #12]
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+ 1566              		.loc 1 1092 79 view .LVU524
+ 1567 006a C3F30623 		ubfx	r3, r3, #8, #7
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       break;
+ 1568              		.loc 1 1092 14 view .LVU525
+ 1569 006e 03FB00F0 		mul	r0, r3, r0
+ 1570              	.LVL138:
+1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1571              		.loc 1 1093 7 is_stmt 1 view .LVU526
+ 1572 0072 ECE7     		b	.L142
+ 1573              	.LVL139:
+ 1574              	.L143:
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1575              		.loc 1 1072 18 is_stmt 0 view .LVU527
+ 1576 0074 0248     		ldr	r0, .L148+4
+ 1577 0076 7047     		bx	lr
+ 1578              	.L144:
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1579              		.loc 1 1077 18 view .LVU528
+ 1580 0078 0248     		ldr	r0, .L148+8
+ 1581 007a 7047     		bx	lr
+ 1582              	.L149:
+ 1583              		.align	2
+ 1584              	.L148:
+ 1585 007c 00100240 		.word	1073876992
+ 1586 0080 0024F400 		.word	16000000
+ 1587 0084 0080BB00 		.word	12288000
+ 1588              		.cfi_endproc
+ 1589              	.LFE333:
+ 1591              		.section	.text.HAL_RCC_ClockConfig,"ax",%progbits
+ 1592              		.align	1
+ 1593              		.global	HAL_RCC_ClockConfig
+ 1594              		.syntax unified
+ 1595              		.thumb
+ 1596              		.thumb_func
+ 1598              	HAL_RCC_ClockConfig:
+ 1599              	.LVL140:
+ARM GAS  /tmp/ccu53ZgF.s 			page 62
+
+
+ 1600              	.LFB331:
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t tickstart;
+ 1601              		.loc 1 768 1 is_stmt 1 view -0
+ 1602              		.cfi_startproc
+ 1603              		@ args = 0, pretend = 0, frame = 0
+ 1604              		@ frame_needed = 0, uses_anonymous_args = 0
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t pllfreq;
+ 1605              		.loc 1 769 3 view .LVU530
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t hpre = RCC_SYSCLK_DIV1;
+ 1606              		.loc 1 770 3 view .LVU531
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1607              		.loc 1 771 3 view .LVU532
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1608              		.loc 1 774 3 view .LVU533
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1609              		.loc 1 774 6 is_stmt 0 view .LVU534
+ 1610 0000 0028     		cmp	r0, #0
+ 1611 0002 00F0E680 		beq	.L170
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   uint32_t tickstart;
+ 1612              		.loc 1 768 1 view .LVU535
+ 1613 0006 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 1614              	.LCFI10:
+ 1615              		.cfi_def_cfa_offset 24
+ 1616              		.cfi_offset 3, -24
+ 1617              		.cfi_offset 4, -20
+ 1618              		.cfi_offset 5, -16
+ 1619              		.cfi_offset 6, -12
+ 1620              		.cfi_offset 7, -8
+ 1621              		.cfi_offset 14, -4
+ 1622 0008 0C46     		mov	r4, r1
+ 1623 000a 0546     		mov	r5, r0
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   assert_param(IS_FLASH_LATENCY(FLatency));
+ 1624              		.loc 1 780 3 is_stmt 1 view .LVU536
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1625              		.loc 1 781 3 view .LVU537
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1626              		.loc 1 788 3 view .LVU538
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1627              		.loc 1 788 18 is_stmt 0 view .LVU539
+ 1628 000c 744B     		ldr	r3, .L188
+ 1629 000e 1B68     		ldr	r3, [r3]
+ 1630 0010 03F00F03 		and	r3, r3, #15
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1631              		.loc 1 788 6 view .LVU540
+ 1632 0014 8B42     		cmp	r3, r1
+ 1633 0016 0BD2     		bcs	.L152
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1634              		.loc 1 791 5 is_stmt 1 view .LVU541
+ 1635 0018 714A     		ldr	r2, .L188
+ 1636 001a 1368     		ldr	r3, [r2]
+ 1637 001c 23F00F03 		bic	r3, r3, #15
+ 1638 0020 0B43     		orrs	r3, r3, r1
+ 1639 0022 1360     		str	r3, [r2]
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1640              		.loc 1 795 5 view .LVU542
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1641              		.loc 1 795 9 is_stmt 0 view .LVU543
+ARM GAS  /tmp/ccu53ZgF.s 			page 63
+
+
+ 1642 0024 1368     		ldr	r3, [r2]
+ 1643 0026 03F00F03 		and	r3, r3, #15
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1644              		.loc 1 795 8 view .LVU544
+ 1645 002a 8B42     		cmp	r3, r1
+ 1646 002c 40F0D380 		bne	.L171
+ 1647              	.L152:
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1648              		.loc 1 802 3 is_stmt 1 view .LVU545
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1649              		.loc 1 802 25 is_stmt 0 view .LVU546
+ 1650 0030 2E68     		ldr	r6, [r5]
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1651              		.loc 1 802 5 view .LVU547
+ 1652 0032 16F00106 		ands	r6, r6, #1
+ 1653 0036 5FD0     		beq	.L153
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1654              		.loc 1 804 5 is_stmt 1 view .LVU548
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1655              		.loc 1 807 5 view .LVU549
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1656              		.loc 1 807 26 is_stmt 0 view .LVU550
+ 1657 0038 6B68     		ldr	r3, [r5, #4]
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1658              		.loc 1 807 8 view .LVU551
+ 1659 003a 032B     		cmp	r3, #3
+ 1660 003c 2FD0     		beq	.L184
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1661              		.loc 1 833 7 is_stmt 1 view .LVU552
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1662              		.loc 1 833 10 is_stmt 0 view .LVU553
+ 1663 003e 022B     		cmp	r3, #2
+ 1664 0040 4DD0     		beq	.L185
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1665              		.loc 1 845 9 is_stmt 1 view .LVU554
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1666              		.loc 1 845 12 is_stmt 0 view .LVU555
+ 1667 0042 684B     		ldr	r3, .L188+4
+ 1668 0044 1B68     		ldr	r3, [r3]
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1669              		.loc 1 845 11 view .LVU556
+ 1670 0046 13F4806F 		tst	r3, #1024
+ 1671 004a 00F0C680 		beq	.L176
+ 1672              	.L158:
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1673              		.loc 1 851 7 is_stmt 1 view .LVU557
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1674              		.loc 1 851 17 is_stmt 0 view .LVU558
+ 1675 004e FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1676              	.LVL141:
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1677              		.loc 1 854 7 is_stmt 1 view .LVU559
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1678              		.loc 1 854 9 is_stmt 0 view .LVU560
+ 1679 0052 654B     		ldr	r3, .L188+8
+ 1680 0054 9842     		cmp	r0, r3
+ 1681 0056 4DD9     		bls	.L177
+ARM GAS  /tmp/ccu53ZgF.s 			page 64
+
+
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         hpre = RCC_SYSCLK_DIV2;
+ 1682              		.loc 1 856 9 is_stmt 1 view .LVU561
+ 1683 0058 624A     		ldr	r2, .L188+4
+ 1684 005a 9368     		ldr	r3, [r2, #8]
+ 1685 005c 23F0F003 		bic	r3, r3, #240
+ 1686 0060 43F08003 		orr	r3, r3, #128
+ 1687 0064 9360     		str	r3, [r2, #8]
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 1688              		.loc 1 857 9 view .LVU562
+ 1689              	.LVL142:
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 1690              		.loc 1 857 14 is_stmt 0 view .LVU563
+ 1691 0066 8026     		movs	r6, #128
+ 1692              	.LVL143:
+ 1693              	.L155:
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1694              		.loc 1 862 5 is_stmt 1 view .LVU564
+ 1695 0068 5E4A     		ldr	r2, .L188+4
+ 1696 006a 9368     		ldr	r3, [r2, #8]
+ 1697 006c 23F00303 		bic	r3, r3, #3
+ 1698 0070 6968     		ldr	r1, [r5, #4]
+ 1699 0072 0B43     		orrs	r3, r3, r1
+ 1700 0074 9360     		str	r3, [r2, #8]
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1701              		.loc 1 865 5 view .LVU565
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1702              		.loc 1 865 17 is_stmt 0 view .LVU566
+ 1703 0076 FFF7FEFF 		bl	HAL_GetTick
+ 1704              	.LVL144:
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1705              		.loc 1 865 17 view .LVU567
+ 1706 007a 0746     		mov	r7, r0
+ 1707              	.LVL145:
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1708              		.loc 1 867 5 is_stmt 1 view .LVU568
+ 1709              	.L159:
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1710              		.loc 1 867 42 view .LVU569
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1711              		.loc 1 867 12 is_stmt 0 view .LVU570
+ 1712 007c 594B     		ldr	r3, .L188+4
+ 1713 007e 9B68     		ldr	r3, [r3, #8]
+ 1714 0080 03F00C03 		and	r3, r3, #12
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1715              		.loc 1 867 63 view .LVU571
+ 1716 0084 6A68     		ldr	r2, [r5, #4]
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1717              		.loc 1 867 42 view .LVU572
+ 1718 0086 B3EB820F 		cmp	r3, r2, lsl #2
+ 1719 008a 35D0     		beq	.L153
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1720              		.loc 1 869 7 is_stmt 1 view .LVU573
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1721              		.loc 1 869 12 is_stmt 0 view .LVU574
+ 1722 008c FFF7FEFF 		bl	HAL_GetTick
+ 1723              	.LVL146:
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ARM GAS  /tmp/ccu53ZgF.s 			page 65
+
+
+ 1724              		.loc 1 869 26 view .LVU575
+ 1725 0090 C01B     		subs	r0, r0, r7
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1726              		.loc 1 869 10 view .LVU576
+ 1727 0092 41F28833 		movw	r3, #5000
+ 1728 0096 9842     		cmp	r0, r3
+ 1729 0098 F0D9     		bls	.L159
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 1730              		.loc 1 871 16 view .LVU577
+ 1731 009a 0320     		movs	r0, #3
+ 1732 009c 78E0     		b	.L151
+ 1733              	.LVL147:
+ 1734              	.L184:
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1735              		.loc 1 810 7 is_stmt 1 view .LVU578
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1736              		.loc 1 810 11 is_stmt 0 view .LVU579
+ 1737 009e 514B     		ldr	r3, .L188+4
+ 1738 00a0 1B68     		ldr	r3, [r3]
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1739              		.loc 1 810 10 view .LVU580
+ 1740 00a2 13F0007F 		tst	r3, #33554432
+ 1741 00a6 01D1     		bne	.L186
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 1742              		.loc 1 812 16 view .LVU581
+ 1743 00a8 0120     		movs	r0, #1
+ 1744              	.LVL148:
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 1745              		.loc 1 812 16 view .LVU582
+ 1746 00aa 71E0     		b	.L151
+ 1747              	.LVL149:
+ 1748              	.L186:
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1749              		.loc 1 816 7 is_stmt 1 view .LVU583
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1750              		.loc 1 816 17 is_stmt 0 view .LVU584
+ 1751 00ac FFF7FEFF 		bl	RCC_GetSysClockFreqFromPLLSource
+ 1752              	.LVL150:
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1753              		.loc 1 819 7 is_stmt 1 view .LVU585
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1754              		.loc 1 819 9 is_stmt 0 view .LVU586
+ 1755 00b0 4D4B     		ldr	r3, .L188+8
+ 1756 00b2 9842     		cmp	r0, r3
+ 1757 00b4 1AD9     		bls	.L173
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
+ 1758              		.loc 1 821 9 is_stmt 1 view .LVU587
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
+ 1759              		.loc 1 821 15 is_stmt 0 view .LVU588
+ 1760 00b6 4B4B     		ldr	r3, .L188+4
+ 1761 00b8 9B68     		ldr	r3, [r3, #8]
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
+ 1762              		.loc 1 821 12 view .LVU589
+ 1763 00ba 13F0F00F 		tst	r3, #240
+ 1764 00be 05D0     		beq	.L156
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****               (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
+ 1765              		.loc 1 822 35 discriminator 1 view .LVU590
+ARM GAS  /tmp/ccu53ZgF.s 			page 66
+
+
+ 1766 00c0 2E68     		ldr	r6, [r5]
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****             (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
+ 1767              		.loc 1 821 71 discriminator 1 view .LVU591
+ 1768 00c2 16F00206 		ands	r6, r6, #2
+ 1769 00c6 CFD0     		beq	.L155
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1770              		.loc 1 823 33 view .LVU592
+ 1771 00c8 AB68     		ldr	r3, [r5, #8]
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****               (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
+ 1772              		.loc 1 822 93 view .LVU593
+ 1773 00ca 8BB9     		cbnz	r3, .L174
+ 1774              	.L156:
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****           hpre = RCC_SYSCLK_DIV2;
+ 1775              		.loc 1 825 11 is_stmt 1 view .LVU594
+ 1776 00cc 454A     		ldr	r2, .L188+4
+ 1777 00ce 9368     		ldr	r3, [r2, #8]
+ 1778 00d0 23F0F003 		bic	r3, r3, #240
+ 1779 00d4 43F08003 		orr	r3, r3, #128
+ 1780 00d8 9360     		str	r3, [r2, #8]
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 1781              		.loc 1 826 11 view .LVU595
+ 1782              	.LVL151:
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 1783              		.loc 1 826 16 is_stmt 0 view .LVU596
+ 1784 00da 8026     		movs	r6, #128
+ 1785 00dc C4E7     		b	.L155
+ 1786              	.LVL152:
+ 1787              	.L185:
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1788              		.loc 1 836 9 is_stmt 1 view .LVU597
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1789              		.loc 1 836 12 is_stmt 0 view .LVU598
+ 1790 00de 414B     		ldr	r3, .L188+4
+ 1791 00e0 1B68     		ldr	r3, [r3]
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         {
+ 1792              		.loc 1 836 11 view .LVU599
+ 1793 00e2 13F4003F 		tst	r3, #131072
+ 1794 00e6 B2D1     		bne	.L158
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 1795              		.loc 1 838 18 view .LVU600
+ 1796 00e8 0120     		movs	r0, #1
+ 1797              	.LVL153:
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 1798              		.loc 1 838 18 view .LVU601
+ 1799 00ea 51E0     		b	.L151
+ 1800              	.LVL154:
+ 1801              	.L173:
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1802              		.loc 1 771 12 view .LVU602
+ 1803 00ec 0026     		movs	r6, #0
+ 1804 00ee BBE7     		b	.L155
+ 1805              	.L174:
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1806              		.loc 1 771 12 view .LVU603
+ 1807 00f0 0026     		movs	r6, #0
+ 1808 00f2 B9E7     		b	.L155
+ 1809              	.L177:
+ARM GAS  /tmp/ccu53ZgF.s 			page 67
+
+
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1810              		.loc 1 771 12 view .LVU604
+ 1811 00f4 0026     		movs	r6, #0
+ 1812 00f6 B7E7     		b	.L155
+ 1813              	.LVL155:
+ 1814              	.L153:
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1815              		.loc 1 877 3 is_stmt 1 view .LVU605
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1816              		.loc 1 877 26 is_stmt 0 view .LVU606
+ 1817 00f8 2B68     		ldr	r3, [r5]
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1818              		.loc 1 877 6 view .LVU607
+ 1819 00fa 13F0020F 		tst	r3, #2
+ 1820 00fe 48D0     		beq	.L161
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1821              		.loc 1 881 5 is_stmt 1 view .LVU608
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1822              		.loc 1 881 8 is_stmt 0 view .LVU609
+ 1823 0100 13F0040F 		tst	r3, #4
+ 1824 0104 04D0     		beq	.L162
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 1825              		.loc 1 883 7 is_stmt 1 view .LVU610
+ 1826 0106 374A     		ldr	r2, .L188+4
+ 1827 0108 9368     		ldr	r3, [r2, #8]
+ 1828 010a 43F4E063 		orr	r3, r3, #1792
+ 1829 010e 9360     		str	r3, [r2, #8]
+ 1830              	.L162:
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1831              		.loc 1 885 5 view .LVU611
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1832              		.loc 1 885 28 is_stmt 0 view .LVU612
+ 1833 0110 2B68     		ldr	r3, [r5]
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1834              		.loc 1 885 8 view .LVU613
+ 1835 0112 13F0080F 		tst	r3, #8
+ 1836 0116 06D0     		beq	.L163
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 1837              		.loc 1 887 7 is_stmt 1 view .LVU614
+ 1838 0118 324A     		ldr	r2, .L188+4
+ 1839 011a 9368     		ldr	r3, [r2, #8]
+ 1840 011c 23F47C53 		bic	r3, r3, #16128
+ 1841 0120 43F4E063 		orr	r3, r3, #1792
+ 1842 0124 9360     		str	r3, [r2, #8]
+ 1843              	.L163:
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 1844              		.loc 1 891 5 view .LVU615
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1845              		.loc 1 892 5 view .LVU616
+ 1846 0126 2F4A     		ldr	r2, .L188+4
+ 1847 0128 9368     		ldr	r3, [r2, #8]
+ 1848 012a 23F0F003 		bic	r3, r3, #240
+ 1849 012e A968     		ldr	r1, [r5, #8]
+ 1850 0130 0B43     		orrs	r3, r3, r1
+ 1851 0132 9360     		str	r3, [r2, #8]
+ 1852              	.L164:
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ARM GAS  /tmp/ccu53ZgF.s 			page 68
+
+
+ 1853              		.loc 1 904 3 view .LVU617
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1854              		.loc 1 904 18 is_stmt 0 view .LVU618
+ 1855 0134 2A4B     		ldr	r3, .L188
+ 1856 0136 1B68     		ldr	r3, [r3]
+ 1857 0138 03F00F03 		and	r3, r3, #15
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1858              		.loc 1 904 6 view .LVU619
+ 1859 013c A342     		cmp	r3, r4
+ 1860 013e 30D8     		bhi	.L187
+ 1861              	.LVL156:
+ 1862              	.L165:
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1863              		.loc 1 923 3 is_stmt 1 view .LVU620
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1864              		.loc 1 923 26 is_stmt 0 view .LVU621
+ 1865 0140 2B68     		ldr	r3, [r5]
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1866              		.loc 1 923 6 view .LVU622
+ 1867 0142 13F0040F 		tst	r3, #4
+ 1868 0146 06D0     		beq	.L168
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ 1869              		.loc 1 925 5 is_stmt 1 view .LVU623
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1870              		.loc 1 926 5 view .LVU624
+ 1871 0148 264A     		ldr	r2, .L188+4
+ 1872 014a 9368     		ldr	r3, [r2, #8]
+ 1873 014c 23F4E063 		bic	r3, r3, #1792
+ 1874 0150 E968     		ldr	r1, [r5, #12]
+ 1875 0152 0B43     		orrs	r3, r3, r1
+ 1876 0154 9360     		str	r3, [r2, #8]
+ 1877              	.L168:
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1878              		.loc 1 930 3 view .LVU625
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1879              		.loc 1 930 25 is_stmt 0 view .LVU626
+ 1880 0156 2B68     		ldr	r3, [r5]
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 1881              		.loc 1 930 5 view .LVU627
+ 1882 0158 13F0080F 		tst	r3, #8
+ 1883 015c 07D0     		beq	.L169
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
+ 1884              		.loc 1 932 5 is_stmt 1 view .LVU628
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1885              		.loc 1 933 5 view .LVU629
+ 1886 015e 214A     		ldr	r2, .L188+4
+ 1887 0160 9368     		ldr	r3, [r2, #8]
+ 1888 0162 23F46053 		bic	r3, r3, #14336
+ 1889 0166 2969     		ldr	r1, [r5, #16]
+ 1890 0168 43EAC103 		orr	r3, r3, r1, lsl #3
+ 1891 016c 9360     		str	r3, [r2, #8]
+ 1892              	.L169:
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1893              		.loc 1 937 3 view .LVU630
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1894              		.loc 1 937 21 is_stmt 0 view .LVU631
+ 1895 016e FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ARM GAS  /tmp/ccu53ZgF.s 			page 69
+
+
+ 1896              	.LVL157:
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1897              		.loc 1 937 65 view .LVU632
+ 1898 0172 1C4B     		ldr	r3, .L188+4
+ 1899 0174 9B68     		ldr	r3, [r3, #8]
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1900              		.loc 1 937 100 view .LVU633
+ 1901 0176 C3F30313 		ubfx	r3, r3, #4, #4
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1902              		.loc 1 937 64 view .LVU634
+ 1903 017a 1C4A     		ldr	r2, .L188+12
+ 1904 017c D35C     		ldrb	r3, [r2, r3]	@ zero_extendqisi2
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1905              		.loc 1 937 122 view .LVU635
+ 1906 017e 03F01F03 		and	r3, r3, #31
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1907              		.loc 1 937 47 view .LVU636
+ 1908 0182 D840     		lsrs	r0, r0, r3
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1909              		.loc 1 937 19 view .LVU637
+ 1910 0184 1A4B     		ldr	r3, .L188+16
+ 1911 0186 1860     		str	r0, [r3]
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 1912              		.loc 1 940 3 is_stmt 1 view .LVU638
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 1913              		.loc 1 940 10 is_stmt 0 view .LVU639
+ 1914 0188 1A4B     		ldr	r3, .L188+20
+ 1915 018a 1868     		ldr	r0, [r3]
+ 1916 018c FFF7FEFF 		bl	HAL_InitTick
+ 1917              	.LVL158:
+ 1918              	.L151:
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1919              		.loc 1 941 1 view .LVU640
+ 1920 0190 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 1921              	.LVL159:
+ 1922              	.L161:
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1923              		.loc 1 897 5 is_stmt 1 view .LVU641
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1924              		.loc 1 897 7 is_stmt 0 view .LVU642
+ 1925 0192 802E     		cmp	r6, #128
+ 1926 0194 CED1     		bne	.L164
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 1927              		.loc 1 899 7 is_stmt 1 view .LVU643
+ 1928 0196 134A     		ldr	r2, .L188+4
+ 1929 0198 9368     		ldr	r3, [r2, #8]
+ 1930 019a 23F0F003 		bic	r3, r3, #240
+ 1931 019e 9360     		str	r3, [r2, #8]
+ 1932 01a0 C8E7     		b	.L164
+ 1933              	.L187:
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1934              		.loc 1 907 5 view .LVU644
+ 1935 01a2 0F4A     		ldr	r2, .L188
+ 1936 01a4 1368     		ldr	r3, [r2]
+ 1937 01a6 23F00F03 		bic	r3, r3, #15
+ 1938 01aa 2343     		orrs	r3, r3, r4
+ 1939 01ac 1360     		str	r3, [r2]
+ARM GAS  /tmp/ccu53ZgF.s 			page 70
+
+
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1940              		.loc 1 911 5 view .LVU645
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1941              		.loc 1 911 17 is_stmt 0 view .LVU646
+ 1942 01ae FFF7FEFF 		bl	HAL_GetTick
+ 1943              	.LVL160:
+ 1944 01b2 0646     		mov	r6, r0
+ 1945              	.LVL161:
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1946              		.loc 1 913 5 is_stmt 1 view .LVU647
+ 1947              	.L166:
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1948              		.loc 1 913 38 view .LVU648
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1949              		.loc 1 913 12 is_stmt 0 view .LVU649
+ 1950 01b4 0A4B     		ldr	r3, .L188
+ 1951 01b6 1B68     		ldr	r3, [r3]
+ 1952 01b8 03F00F03 		and	r3, r3, #15
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     {
+ 1953              		.loc 1 913 38 view .LVU650
+ 1954 01bc A342     		cmp	r3, r4
+ 1955 01be BFD0     		beq	.L165
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1956              		.loc 1 915 7 is_stmt 1 view .LVU651
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1957              		.loc 1 915 12 is_stmt 0 view .LVU652
+ 1958 01c0 FFF7FEFF 		bl	HAL_GetTick
+ 1959              	.LVL162:
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1960              		.loc 1 915 26 view .LVU653
+ 1961 01c4 801B     		subs	r0, r0, r6
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       {
+ 1962              		.loc 1 915 10 view .LVU654
+ 1963 01c6 41F28833 		movw	r3, #5000
+ 1964 01ca 9842     		cmp	r0, r3
+ 1965 01cc F2D9     		bls	.L166
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****       }
+ 1966              		.loc 1 917 16 view .LVU655
+ 1967 01ce 0320     		movs	r0, #3
+ 1968 01d0 DEE7     		b	.L151
+ 1969              	.LVL163:
+ 1970              	.L170:
+ 1971              	.LCFI11:
+ 1972              		.cfi_def_cfa_offset 0
+ 1973              		.cfi_restore 3
+ 1974              		.cfi_restore 4
+ 1975              		.cfi_restore 5
+ 1976              		.cfi_restore 6
+ 1977              		.cfi_restore 7
+ 1978              		.cfi_restore 14
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 1979              		.loc 1 776 12 view .LVU656
+ 1980 01d2 0120     		movs	r0, #1
+ 1981              	.LVL164:
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 1982              		.loc 1 941 1 view .LVU657
+ 1983 01d4 7047     		bx	lr
+ARM GAS  /tmp/ccu53ZgF.s 			page 71
+
+
+ 1984              	.LVL165:
+ 1985              	.L171:
+ 1986              	.LCFI12:
+ 1987              		.cfi_def_cfa_offset 24
+ 1988              		.cfi_offset 3, -24
+ 1989              		.cfi_offset 4, -20
+ 1990              		.cfi_offset 5, -16
+ 1991              		.cfi_offset 6, -12
+ 1992              		.cfi_offset 7, -8
+ 1993              		.cfi_offset 14, -4
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 1994              		.loc 1 797 14 view .LVU658
+ 1995 01d6 0120     		movs	r0, #1
+ 1996              	.LVL166:
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****     }
+ 1997              		.loc 1 797 14 view .LVU659
+ 1998 01d8 DAE7     		b	.L151
+ 1999              	.LVL167:
+ 2000              	.L176:
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 2001              		.loc 1 847 18 view .LVU660
+ 2002 01da 0120     		movs	r0, #1
+ 2003              	.LVL168:
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****         }
+ 2004              		.loc 1 847 18 view .LVU661
+ 2005 01dc D8E7     		b	.L151
+ 2006              	.L189:
+ 2007 01de 00BF     		.align	2
+ 2008              	.L188:
+ 2009 01e0 00200240 		.word	1073881088
+ 2010 01e4 00100240 		.word	1073876992
+ 2011 01e8 00B4C404 		.word	80000000
+ 2012 01ec 00000000 		.word	AHBPrescTable
+ 2013 01f0 00000000 		.word	SystemCoreClock
+ 2014 01f4 00000000 		.word	uwTickPrio
+ 2015              		.cfi_endproc
+ 2016              	.LFE331:
+ 2018              		.section	.text.HAL_RCC_GetHCLKFreq,"ax",%progbits
+ 2019              		.align	1
+ 2020              		.global	HAL_RCC_GetHCLKFreq
+ 2021              		.syntax unified
+ 2022              		.thumb
+ 2023              		.thumb_func
+ 2025              	HAL_RCC_GetHCLKFreq:
+ 2026              	.LFB334:
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   return SystemCoreClock;
+ 2027              		.loc 1 1120 1 is_stmt 1 view -0
+ 2028              		.cfi_startproc
+ 2029              		@ args = 0, pretend = 0, frame = 0
+ 2030              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2031              		@ link register save eliminated.
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2032              		.loc 1 1121 3 view .LVU663
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2033              		.loc 1 1122 1 is_stmt 0 view .LVU664
+ 2034 0000 014B     		ldr	r3, .L191
+ 2035 0002 1868     		ldr	r0, [r3]
+ARM GAS  /tmp/ccu53ZgF.s 			page 72
+
+
+ 2036 0004 7047     		bx	lr
+ 2037              	.L192:
+ 2038 0006 00BF     		.align	2
+ 2039              	.L191:
+ 2040 0008 00000000 		.word	SystemCoreClock
+ 2041              		.cfi_endproc
+ 2042              	.LFE334:
+ 2044              		.section	.text.HAL_RCC_GetPCLK1Freq,"ax",%progbits
+ 2045              		.align	1
+ 2046              		.global	HAL_RCC_GetPCLK1Freq
+ 2047              		.syntax unified
+ 2048              		.thumb
+ 2049              		.thumb_func
+ 2051              	HAL_RCC_GetPCLK1Freq:
+ 2052              	.LFB335:
+1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+ 2053              		.loc 1 1131 1 is_stmt 1 view -0
+ 2054              		.cfi_startproc
+ 2055              		@ args = 0, pretend = 0, frame = 0
+ 2056              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2057 0000 08B5     		push	{r3, lr}
+ 2058              	.LCFI13:
+ 2059              		.cfi_def_cfa_offset 8
+ 2060              		.cfi_offset 3, -8
+ 2061              		.cfi_offset 14, -4
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2062              		.loc 1 1133 3 view .LVU666
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2063              		.loc 1 1133 11 is_stmt 0 view .LVU667
+ 2064 0002 FFF7FEFF 		bl	HAL_RCC_GetHCLKFreq
+ 2065              	.LVL169:
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2066              		.loc 1 1133 51 view .LVU668
+ 2067 0006 054B     		ldr	r3, .L195
+ 2068 0008 9B68     		ldr	r3, [r3, #8]
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2069              		.loc 1 1133 87 view .LVU669
+ 2070 000a C3F30223 		ubfx	r3, r3, #8, #3
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2071              		.loc 1 1133 50 view .LVU670
+ 2072 000e 044A     		ldr	r2, .L195+4
+ 2073 0010 D35C     		ldrb	r3, [r2, r3]	@ zero_extendqisi2
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2074              		.loc 1 1133 110 view .LVU671
+ 2075 0012 03F01F03 		and	r3, r3, #31
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2076              		.loc 1 1134 1 view .LVU672
+ 2077 0016 D840     		lsrs	r0, r0, r3
+ 2078 0018 08BD     		pop	{r3, pc}
+ 2079              	.L196:
+ 2080 001a 00BF     		.align	2
+ 2081              	.L195:
+ 2082 001c 00100240 		.word	1073876992
+ 2083 0020 00000000 		.word	APBPrescTable
+ 2084              		.cfi_endproc
+ 2085              	.LFE335:
+ 2087              		.section	.text.HAL_RCC_GetPCLK2Freq,"ax",%progbits
+ARM GAS  /tmp/ccu53ZgF.s 			page 73
+
+
+ 2088              		.align	1
+ 2089              		.global	HAL_RCC_GetPCLK2Freq
+ 2090              		.syntax unified
+ 2091              		.thumb
+ 2092              		.thumb_func
+ 2094              	HAL_RCC_GetPCLK2Freq:
+ 2095              	.LFB336:
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+ 2096              		.loc 1 1143 1 is_stmt 1 view -0
+ 2097              		.cfi_startproc
+ 2098              		@ args = 0, pretend = 0, frame = 0
+ 2099              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2100 0000 08B5     		push	{r3, lr}
+ 2101              	.LCFI14:
+ 2102              		.cfi_def_cfa_offset 8
+ 2103              		.cfi_offset 3, -8
+ 2104              		.cfi_offset 14, -4
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2105              		.loc 1 1145 3 view .LVU674
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2106              		.loc 1 1145 11 is_stmt 0 view .LVU675
+ 2107 0002 FFF7FEFF 		bl	HAL_RCC_GetHCLKFreq
+ 2108              	.LVL170:
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2109              		.loc 1 1145 50 view .LVU676
+ 2110 0006 054B     		ldr	r3, .L199
+ 2111 0008 9B68     		ldr	r3, [r3, #8]
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2112              		.loc 1 1145 86 view .LVU677
+ 2113 000a C3F3C223 		ubfx	r3, r3, #11, #3
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2114              		.loc 1 1145 49 view .LVU678
+ 2115 000e 044A     		ldr	r2, .L199+4
+ 2116 0010 D35C     		ldrb	r3, [r2, r3]	@ zero_extendqisi2
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2117              		.loc 1 1145 109 view .LVU679
+ 2118 0012 03F01F03 		and	r3, r3, #31
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2119              		.loc 1 1146 1 view .LVU680
+ 2120 0016 D840     		lsrs	r0, r0, r3
+ 2121 0018 08BD     		pop	{r3, pc}
+ 2122              	.L200:
+ 2123 001a 00BF     		.align	2
+ 2124              	.L199:
+ 2125 001c 00100240 		.word	1073876992
+ 2126 0020 00000000 		.word	APBPrescTable
+ 2127              		.cfi_endproc
+ 2128              	.LFE336:
+ 2130              		.section	.text.HAL_RCC_GetOscConfig,"ax",%progbits
+ 2131              		.align	1
+ 2132              		.global	HAL_RCC_GetOscConfig
+ 2133              		.syntax unified
+ 2134              		.thumb
+ 2135              		.thumb_func
+ 2137              	HAL_RCC_GetOscConfig:
+ 2138              	.LVL171:
+ 2139              	.LFB337:
+ARM GAS  /tmp/ccu53ZgF.s 			page 74
+
+
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Check the parameters */
+ 2140              		.loc 1 1156 1 is_stmt 1 view -0
+ 2141              		.cfi_startproc
+ 2142              		@ args = 0, pretend = 0, frame = 0
+ 2143              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2144              		@ link register save eliminated.
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2145              		.loc 1 1158 3 view .LVU682
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLA
+ 2146              		.loc 1 1161 3 view .LVU683
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLA
+ 2147              		.loc 1 1161 37 is_stmt 0 view .LVU684
+ 2148 0000 2F23     		movs	r3, #47
+ 2149 0002 0360     		str	r3, [r0]
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2150              		.loc 1 1165 3 is_stmt 1 view .LVU685
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2151              		.loc 1 1165 6 is_stmt 0 view .LVU686
+ 2152 0004 3A4B     		ldr	r3, .L216
+ 2153 0006 1B68     		ldr	r3, [r3]
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2154              		.loc 1 1165 5 view .LVU687
+ 2155 0008 13F4802F 		tst	r3, #262144
+ 2156 000c 4BD0     		beq	.L202
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2157              		.loc 1 1167 5 is_stmt 1 view .LVU688
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2158              		.loc 1 1167 33 is_stmt 0 view .LVU689
+ 2159 000e 4FF4A023 		mov	r3, #327680
+ 2160 0012 4360     		str	r3, [r0, #4]
+ 2161              	.L203:
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2162              		.loc 1 1179 3 is_stmt 1 view .LVU690
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2163              		.loc 1 1179 6 is_stmt 0 view .LVU691
+ 2164 0014 364B     		ldr	r3, .L216
+ 2165 0016 1B68     		ldr	r3, [r3]
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2166              		.loc 1 1179 5 view .LVU692
+ 2167 0018 13F4807F 		tst	r3, #256
+ 2168 001c 4FD0     		beq	.L205
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2169              		.loc 1 1181 5 is_stmt 1 view .LVU693
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2170              		.loc 1 1181 33 is_stmt 0 view .LVU694
+ 2171 001e 4FF48073 		mov	r3, #256
+ 2172 0022 C360     		str	r3, [r0, #12]
+ 2173              	.L206:
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2174              		.loc 1 1188 3 is_stmt 1 view .LVU695
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2175              		.loc 1 1188 44 is_stmt 0 view .LVU696
+ 2176 0024 324A     		ldr	r2, .L216
+ 2177 0026 5368     		ldr	r3, [r2, #4]
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2178              		.loc 1 1188 84 view .LVU697
+ 2179 0028 C3F30663 		ubfx	r3, r3, #24, #7
+ARM GAS  /tmp/ccu53ZgF.s 			page 75
+
+
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2180              		.loc 1 1188 42 view .LVU698
+ 2181 002c 0361     		str	r3, [r0, #16]
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2182              		.loc 1 1191 3 is_stmt 1 view .LVU699
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2183              		.loc 1 1191 6 is_stmt 0 view .LVU700
+ 2184 002e D2F89030 		ldr	r3, [r2, #144]
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2185              		.loc 1 1191 5 view .LVU701
+ 2186 0032 13F0040F 		tst	r3, #4
+ 2187 0036 45D0     		beq	.L207
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2188              		.loc 1 1193 5 is_stmt 1 view .LVU702
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2189              		.loc 1 1193 33 is_stmt 0 view .LVU703
+ 2190 0038 0523     		movs	r3, #5
+ 2191 003a 8360     		str	r3, [r0, #8]
+ 2192              	.L208:
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2193              		.loc 1 1205 3 is_stmt 1 view .LVU704
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2194              		.loc 1 1205 6 is_stmt 0 view .LVU705
+ 2195 003c 2C4B     		ldr	r3, .L216
+ 2196 003e D3F89430 		ldr	r3, [r3, #148]
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2197              		.loc 1 1205 5 view .LVU706
+ 2198 0042 13F0010F 		tst	r3, #1
+ 2199 0046 49D0     		beq	.L210
+1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2200              		.loc 1 1207 5 is_stmt 1 view .LVU707
+1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2201              		.loc 1 1207 33 is_stmt 0 view .LVU708
+ 2202 0048 0123     		movs	r3, #1
+ 2203 004a 4361     		str	r3, [r0, #20]
+ 2204              	.L211:
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2205              		.loc 1 1215 3 is_stmt 1 view .LVU709
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2206              		.loc 1 1215 6 is_stmt 0 view .LVU710
+ 2207 004c 284B     		ldr	r3, .L216
+ 2208 004e D3F89830 		ldr	r3, [r3, #152]
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2209              		.loc 1 1215 5 view .LVU711
+ 2210 0052 13F0010F 		tst	r3, #1
+ 2211 0056 44D0     		beq	.L212
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2212              		.loc 1 1217 5 is_stmt 1 view .LVU712
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2213              		.loc 1 1217 35 is_stmt 0 view .LVU713
+ 2214 0058 0123     		movs	r3, #1
+ 2215 005a 8361     		str	r3, [r0, #24]
+ 2216              	.L213:
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2217              		.loc 1 1225 3 is_stmt 1 view .LVU714
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2218              		.loc 1 1225 6 is_stmt 0 view .LVU715
+ARM GAS  /tmp/ccu53ZgF.s 			page 76
+
+
+ 2219 005c 244B     		ldr	r3, .L216
+ 2220 005e 1B68     		ldr	r3, [r3]
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2221              		.loc 1 1225 5 view .LVU716
+ 2222 0060 13F0807F 		tst	r3, #16777216
+ 2223 0064 40D0     		beq	.L214
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2224              		.loc 1 1227 5 is_stmt 1 view .LVU717
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2225              		.loc 1 1227 37 is_stmt 0 view .LVU718
+ 2226 0066 0223     		movs	r3, #2
+ 2227 0068 C361     		str	r3, [r0, #28]
+ 2228              	.L215:
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) 
+ 2229              		.loc 1 1233 3 is_stmt 1 view .LVU719
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) 
+ 2230              		.loc 1 1233 38 is_stmt 0 view .LVU720
+ 2231 006a 214A     		ldr	r2, .L216
+ 2232 006c D368     		ldr	r3, [r2, #12]
+ 2233 006e 03F00303 		and	r3, r3, #3
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) 
+ 2234              		.loc 1 1233 36 view .LVU721
+ 2235 0072 0362     		str	r3, [r0, #32]
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+ 2236              		.loc 1 1234 3 is_stmt 1 view .LVU722
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+ 2237              		.loc 1 1234 34 is_stmt 0 view .LVU723
+ 2238 0074 D368     		ldr	r3, [r2, #12]
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+ 2239              		.loc 1 1234 75 view .LVU724
+ 2240 0076 C3F30313 		ubfx	r3, r3, #4, #4
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+ 2241              		.loc 1 1234 100 view .LVU725
+ 2242 007a 0133     		adds	r3, r3, #1
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+ 2243              		.loc 1 1234 31 view .LVU726
+ 2244 007c 4362     		str	r3, [r0, #36]
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos
+ 2245              		.loc 1 1235 3 is_stmt 1 view .LVU727
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos
+ 2246              		.loc 1 1235 33 is_stmt 0 view .LVU728
+ 2247 007e D368     		ldr	r3, [r2, #12]
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos
+ 2248              		.loc 1 1235 74 view .LVU729
+ 2249 0080 C3F30623 		ubfx	r3, r3, #8, #7
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos
+ 2250              		.loc 1 1235 31 view .LVU730
+ 2251 0084 8362     		str	r3, [r0, #40]
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos
+ 2252              		.loc 1 1236 3 is_stmt 1 view .LVU731
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos
+ 2253              		.loc 1 1236 36 is_stmt 0 view .LVU732
+ 2254 0086 D368     		ldr	r3, [r2, #12]
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos
+ 2255              		.loc 1 1236 77 view .LVU733
+ 2256 0088 C3F34153 		ubfx	r3, r3, #21, #2
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos
+ARM GAS  /tmp/ccu53ZgF.s 			page 77
+
+
+ 2257              		.loc 1 1236 102 view .LVU734
+ 2258 008c 0133     		adds	r3, r3, #1
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos
+ 2259              		.loc 1 1236 108 view .LVU735
+ 2260 008e 5B00     		lsls	r3, r3, #1
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos
+ 2261              		.loc 1 1236 31 view .LVU736
+ 2262 0090 0363     		str	r3, [r0, #48]
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_
+ 2263              		.loc 1 1237 3 is_stmt 1 view .LVU737
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_
+ 2264              		.loc 1 1237 36 is_stmt 0 view .LVU738
+ 2265 0092 D368     		ldr	r3, [r2, #12]
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_
+ 2266              		.loc 1 1237 77 view .LVU739
+ 2267 0094 C3F34163 		ubfx	r3, r3, #25, #2
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_
+ 2268              		.loc 1 1237 102 view .LVU740
+ 2269 0098 0133     		adds	r3, r3, #1
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_
+ 2270              		.loc 1 1237 108 view .LVU741
+ 2271 009a 5B00     		lsls	r3, r3, #1
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_
+ 2272              		.loc 1 1237 31 view .LVU742
+ 2273 009c 4363     		str	r3, [r0, #52]
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2274              		.loc 1 1238 3 is_stmt 1 view .LVU743
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2275              		.loc 1 1238 33 is_stmt 0 view .LVU744
+ 2276 009e D368     		ldr	r3, [r2, #12]
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2277              		.loc 1 1238 77 view .LVU745
+ 2278 00a0 DB0E     		lsrs	r3, r3, #27
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2279              		.loc 1 1238 31 view .LVU746
+ 2280 00a2 C362     		str	r3, [r0, #44]
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2281              		.loc 1 1239 1 view .LVU747
+ 2282 00a4 7047     		bx	lr
+ 2283              	.L202:
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2284              		.loc 1 1169 8 is_stmt 1 view .LVU748
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2285              		.loc 1 1169 11 is_stmt 0 view .LVU749
+ 2286 00a6 124B     		ldr	r3, .L216
+ 2287 00a8 1B68     		ldr	r3, [r3]
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2288              		.loc 1 1169 10 view .LVU750
+ 2289 00aa 13F4803F 		tst	r3, #65536
+ 2290 00ae 03D0     		beq	.L204
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2291              		.loc 1 1171 5 is_stmt 1 view .LVU751
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2292              		.loc 1 1171 33 is_stmt 0 view .LVU752
+ 2293 00b0 4FF48033 		mov	r3, #65536
+ 2294 00b4 4360     		str	r3, [r0, #4]
+ 2295 00b6 ADE7     		b	.L203
+ARM GAS  /tmp/ccu53ZgF.s 			page 78
+
+
+ 2296              	.L204:
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2297              		.loc 1 1175 5 is_stmt 1 view .LVU753
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2298              		.loc 1 1175 33 is_stmt 0 view .LVU754
+ 2299 00b8 0023     		movs	r3, #0
+ 2300 00ba 4360     		str	r3, [r0, #4]
+ 2301 00bc AAE7     		b	.L203
+ 2302              	.L205:
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2303              		.loc 1 1185 5 is_stmt 1 view .LVU755
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2304              		.loc 1 1185 33 is_stmt 0 view .LVU756
+ 2305 00be 0023     		movs	r3, #0
+ 2306 00c0 C360     		str	r3, [r0, #12]
+ 2307 00c2 AFE7     		b	.L206
+ 2308              	.L207:
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2309              		.loc 1 1195 8 is_stmt 1 view .LVU757
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2310              		.loc 1 1195 11 is_stmt 0 view .LVU758
+ 2311 00c4 0A4B     		ldr	r3, .L216
+ 2312 00c6 D3F89030 		ldr	r3, [r3, #144]
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2313              		.loc 1 1195 10 view .LVU759
+ 2314 00ca 13F0010F 		tst	r3, #1
+ 2315 00ce 02D0     		beq	.L209
+1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2316              		.loc 1 1197 5 is_stmt 1 view .LVU760
+1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2317              		.loc 1 1197 33 is_stmt 0 view .LVU761
+ 2318 00d0 0123     		movs	r3, #1
+ 2319 00d2 8360     		str	r3, [r0, #8]
+ 2320 00d4 B2E7     		b	.L208
+ 2321              	.L209:
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2322              		.loc 1 1201 5 is_stmt 1 view .LVU762
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2323              		.loc 1 1201 33 is_stmt 0 view .LVU763
+ 2324 00d6 0023     		movs	r3, #0
+ 2325 00d8 8360     		str	r3, [r0, #8]
+ 2326 00da AFE7     		b	.L208
+ 2327              	.L210:
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2328              		.loc 1 1211 5 is_stmt 1 view .LVU764
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2329              		.loc 1 1211 33 is_stmt 0 view .LVU765
+ 2330 00dc 0023     		movs	r3, #0
+ 2331 00de 4361     		str	r3, [r0, #20]
+ 2332 00e0 B4E7     		b	.L211
+ 2333              	.L212:
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2334              		.loc 1 1221 5 is_stmt 1 view .LVU766
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2335              		.loc 1 1221 35 is_stmt 0 view .LVU767
+ 2336 00e2 0023     		movs	r3, #0
+ 2337 00e4 8361     		str	r3, [r0, #24]
+ARM GAS  /tmp/ccu53ZgF.s 			page 79
+
+
+ 2338 00e6 B9E7     		b	.L213
+ 2339              	.L214:
+1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2340              		.loc 1 1231 5 is_stmt 1 view .LVU768
+1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2341              		.loc 1 1231 37 is_stmt 0 view .LVU769
+ 2342 00e8 0123     		movs	r3, #1
+ 2343 00ea C361     		str	r3, [r0, #28]
+ 2344 00ec BDE7     		b	.L215
+ 2345              	.L217:
+ 2346 00ee 00BF     		.align	2
+ 2347              	.L216:
+ 2348 00f0 00100240 		.word	1073876992
+ 2349              		.cfi_endproc
+ 2350              	.LFE337:
+ 2352              		.section	.text.HAL_RCC_GetClockConfig,"ax",%progbits
+ 2353              		.align	1
+ 2354              		.global	HAL_RCC_GetClockConfig
+ 2355              		.syntax unified
+ 2356              		.thumb
+ 2357              		.thumb_func
+ 2359              	HAL_RCC_GetClockConfig:
+ 2360              	.LVL172:
+ 2361              	.LFB338:
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Check the parameters */
+ 2362              		.loc 1 1250 1 is_stmt 1 view -0
+ 2363              		.cfi_startproc
+ 2364              		@ args = 0, pretend = 0, frame = 0
+ 2365              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2366              		@ link register save eliminated.
+1252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   assert_param(pFLatency != (void *)NULL);
+ 2367              		.loc 1 1252 3 view .LVU771
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2368              		.loc 1 1253 3 view .LVU772
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2369              		.loc 1 1256 3 view .LVU773
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2370              		.loc 1 1256 32 is_stmt 0 view .LVU774
+ 2371 0000 0F23     		movs	r3, #15
+ 2372 0002 0360     		str	r3, [r0]
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2373              		.loc 1 1259 3 is_stmt 1 view .LVU775
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2374              		.loc 1 1259 37 is_stmt 0 view .LVU776
+ 2375 0004 0B4B     		ldr	r3, .L219
+ 2376 0006 9A68     		ldr	r2, [r3, #8]
+ 2377 0008 02F00302 		and	r2, r2, #3
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2378              		.loc 1 1259 35 view .LVU777
+ 2379 000c 4260     		str	r2, [r0, #4]
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2380              		.loc 1 1262 3 is_stmt 1 view .LVU778
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2381              		.loc 1 1262 38 is_stmt 0 view .LVU779
+ 2382 000e 9A68     		ldr	r2, [r3, #8]
+ 2383 0010 02F0F002 		and	r2, r2, #240
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ARM GAS  /tmp/ccu53ZgF.s 			page 80
+
+
+ 2384              		.loc 1 1262 36 view .LVU780
+ 2385 0014 8260     		str	r2, [r0, #8]
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2386              		.loc 1 1265 3 is_stmt 1 view .LVU781
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2387              		.loc 1 1265 39 is_stmt 0 view .LVU782
+ 2388 0016 9A68     		ldr	r2, [r3, #8]
+ 2389 0018 02F4E062 		and	r2, r2, #1792
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2390              		.loc 1 1265 37 view .LVU783
+ 2391 001c C260     		str	r2, [r0, #12]
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2392              		.loc 1 1268 3 is_stmt 1 view .LVU784
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2393              		.loc 1 1268 40 is_stmt 0 view .LVU785
+ 2394 001e 9B68     		ldr	r3, [r3, #8]
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2395              		.loc 1 1268 76 view .LVU786
+ 2396 0020 DB08     		lsrs	r3, r3, #3
+ 2397 0022 03F4E063 		and	r3, r3, #1792
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2398              		.loc 1 1268 37 view .LVU787
+ 2399 0026 0361     		str	r3, [r0, #16]
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2400              		.loc 1 1271 3 is_stmt 1 view .LVU788
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2401              		.loc 1 1271 16 is_stmt 0 view .LVU789
+ 2402 0028 034B     		ldr	r3, .L219+4
+ 2403 002a 1B68     		ldr	r3, [r3]
+ 2404 002c 03F00F03 		and	r3, r3, #15
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2405              		.loc 1 1271 14 view .LVU790
+ 2406 0030 0B60     		str	r3, [r1]
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2407              		.loc 1 1272 1 view .LVU791
+ 2408 0032 7047     		bx	lr
+ 2409              	.L220:
+ 2410              		.align	2
+ 2411              	.L219:
+ 2412 0034 00100240 		.word	1073876992
+ 2413 0038 00200240 		.word	1073881088
+ 2414              		.cfi_endproc
+ 2415              	.LFE338:
+ 2417              		.section	.text.HAL_RCC_EnableCSS,"ax",%progbits
+ 2418              		.align	1
+ 2419              		.global	HAL_RCC_EnableCSS
+ 2420              		.syntax unified
+ 2421              		.thumb
+ 2422              		.thumb_func
+ 2424              	HAL_RCC_EnableCSS:
+ 2425              	.LFB339:
+1285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   SET_BIT(RCC->CR, RCC_CR_CSSON) ;
+ 2426              		.loc 1 1285 1 is_stmt 1 view -0
+ 2427              		.cfi_startproc
+ 2428              		@ args = 0, pretend = 0, frame = 0
+ 2429              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2430              		@ link register save eliminated.
+ARM GAS  /tmp/ccu53ZgF.s 			page 81
+
+
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2431              		.loc 1 1286 3 view .LVU793
+ 2432 0000 024A     		ldr	r2, .L222
+ 2433 0002 1368     		ldr	r3, [r2]
+ 2434 0004 43F40023 		orr	r3, r3, #524288
+ 2435 0008 1360     		str	r3, [r2]
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2436              		.loc 1 1287 1 is_stmt 0 view .LVU794
+ 2437 000a 7047     		bx	lr
+ 2438              	.L223:
+ 2439              		.align	2
+ 2440              	.L222:
+ 2441 000c 00100240 		.word	1073876992
+ 2442              		.cfi_endproc
+ 2443              	.LFE339:
+ 2445              		.section	.text.HAL_RCC_EnableLSECSS,"ax",%progbits
+ 2446              		.align	1
+ 2447              		.global	HAL_RCC_EnableLSECSS
+ 2448              		.syntax unified
+ 2449              		.thumb
+ 2450              		.thumb_func
+ 2452              	HAL_RCC_EnableLSECSS:
+ 2453              	.LFB340:
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+ 2454              		.loc 1 1299 1 is_stmt 1 view -0
+ 2455              		.cfi_startproc
+ 2456              		@ args = 0, pretend = 0, frame = 0
+ 2457              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2458              		@ link register save eliminated.
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2459              		.loc 1 1300 3 view .LVU796
+ 2460 0000 034A     		ldr	r2, .L225
+ 2461 0002 D2F89030 		ldr	r3, [r2, #144]
+ 2462 0006 43F02003 		orr	r3, r3, #32
+ 2463 000a C2F89030 		str	r3, [r2, #144]
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2464              		.loc 1 1301 1 is_stmt 0 view .LVU797
+ 2465 000e 7047     		bx	lr
+ 2466              	.L226:
+ 2467              		.align	2
+ 2468              	.L225:
+ 2469 0010 00100240 		.word	1073876992
+ 2470              		.cfi_endproc
+ 2471              	.LFE340:
+ 2473              		.section	.text.HAL_RCC_DisableLSECSS,"ax",%progbits
+ 2474              		.align	1
+ 2475              		.global	HAL_RCC_DisableLSECSS
+ 2476              		.syntax unified
+ 2477              		.thumb
+ 2478              		.thumb_func
+ 2480              	HAL_RCC_DisableLSECSS:
+ 2481              	.LFB341:
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+ 2482              		.loc 1 1310 1 is_stmt 1 view -0
+ 2483              		.cfi_startproc
+ 2484              		@ args = 0, pretend = 0, frame = 0
+ 2485              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccu53ZgF.s 			page 82
+
+
+ 2486              		@ link register save eliminated.
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** }
+ 2487              		.loc 1 1311 3 view .LVU799
+ 2488 0000 034A     		ldr	r2, .L228
+ 2489 0002 D2F89030 		ldr	r3, [r2, #144]
+ 2490 0006 23F02003 		bic	r3, r3, #32
+ 2491 000a C2F89030 		str	r3, [r2, #144]
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2492              		.loc 1 1312 1 is_stmt 0 view .LVU800
+ 2493 000e 7047     		bx	lr
+ 2494              	.L229:
+ 2495              		.align	2
+ 2496              	.L228:
+ 2497 0010 00100240 		.word	1073876992
+ 2498              		.cfi_endproc
+ 2499              	.LFE341:
+ 2501              		.section	.text.HAL_RCC_CSSCallback,"ax",%progbits
+ 2502              		.align	1
+ 2503              		.weak	HAL_RCC_CSSCallback
+ 2504              		.syntax unified
+ 2505              		.thumb
+ 2506              		.thumb_func
+ 2508              	HAL_RCC_CSSCallback:
+ 2509              	.LFB343:
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 2510              		.loc 1 1337 1 is_stmt 1 view -0
+ 2511              		.cfi_startproc
+ 2512              		@ args = 0, pretend = 0, frame = 0
+ 2513              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2514              		@ link register save eliminated.
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2515              		.loc 1 1341 1 view .LVU802
+ 2516 0000 7047     		bx	lr
+ 2517              		.cfi_endproc
+ 2518              	.LFE343:
+ 2520              		.section	.text.HAL_RCC_NMI_IRQHandler,"ax",%progbits
+ 2521              		.align	1
+ 2522              		.global	HAL_RCC_NMI_IRQHandler
+ 2523              		.syntax unified
+ 2524              		.thumb
+ 2525              		.thumb_func
+ 2527              	HAL_RCC_NMI_IRQHandler:
+ 2528              	.LFB342:
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   /* Check RCC CSSF interrupt flag  */
+ 2529              		.loc 1 1320 1 view -0
+ 2530              		.cfi_startproc
+ 2531              		@ args = 0, pretend = 0, frame = 0
+ 2532              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2533 0000 08B5     		push	{r3, lr}
+ 2534              	.LCFI15:
+ 2535              		.cfi_def_cfa_offset 8
+ 2536              		.cfi_offset 3, -8
+ 2537              		.cfi_offset 14, -4
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2538              		.loc 1 1322 3 view .LVU804
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2539              		.loc 1 1322 6 is_stmt 0 view .LVU805
+ARM GAS  /tmp/ccu53ZgF.s 			page 83
+
+
+ 2540 0002 064B     		ldr	r3, .L235
+ 2541 0004 DB69     		ldr	r3, [r3, #28]
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   {
+ 2542              		.loc 1 1322 5 view .LVU806
+ 2543 0006 13F4807F 		tst	r3, #256
+ 2544 000a 00D1     		bne	.L234
+ 2545              	.L231:
+1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2546              		.loc 1 1330 1 view .LVU807
+ 2547 000c 08BD     		pop	{r3, pc}
+ 2548              	.L234:
+1325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2549              		.loc 1 1325 5 is_stmt 1 view .LVU808
+ 2550 000e FFF7FEFF 		bl	HAL_RCC_CSSCallback
+ 2551              	.LVL173:
+1328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ****   }
+ 2552              		.loc 1 1328 5 view .LVU809
+ 2553 0012 024B     		ldr	r3, .L235
+ 2554 0014 4FF48072 		mov	r2, #256
+ 2555 0018 1A62     		str	r2, [r3, #32]
+1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c **** 
+ 2556              		.loc 1 1330 1 is_stmt 0 view .LVU810
+ 2557 001a F7E7     		b	.L231
+ 2558              	.L236:
+ 2559              		.align	2
+ 2560              	.L235:
+ 2561 001c 00100240 		.word	1073876992
+ 2562              		.cfi_endproc
+ 2563              	.LFE342:
+ 2565              		.text
+ 2566              	.Letext0:
+ 2567              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 2568              		.file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
+ 2569              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 2570              		.file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 2571              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 2572              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"
+ 2573              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"
+ 2574              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ARM GAS  /tmp/ccu53ZgF.s 			page 84
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_rcc.c
+     /tmp/ccu53ZgF.s:21     .text.RCC_GetSysClockFreqFromPLLSource:00000000 $t
+     /tmp/ccu53ZgF.s:26     .text.RCC_GetSysClockFreqFromPLLSource:00000000 RCC_GetSysClockFreqFromPLLSource
+     /tmp/ccu53ZgF.s:108    .text.RCC_GetSysClockFreqFromPLLSource:0000004c $d
+     /tmp/ccu53ZgF.s:115    .text.HAL_RCC_DeInit:00000000 $t
+     /tmp/ccu53ZgF.s:121    .text.HAL_RCC_DeInit:00000000 HAL_RCC_DeInit
+     /tmp/ccu53ZgF.s:294    .text.HAL_RCC_DeInit:000000bc $d
+     /tmp/ccu53ZgF.s:302    .text.HAL_RCC_OscConfig:00000000 $t
+     /tmp/ccu53ZgF.s:308    .text.HAL_RCC_OscConfig:00000000 HAL_RCC_OscConfig
+     /tmp/ccu53ZgF.s:881    .text.HAL_RCC_OscConfig:000002a8 $d
+     /tmp/ccu53ZgF.s:886    .text.HAL_RCC_OscConfig:000002b4 $t
+     /tmp/ccu53ZgF.s:1338   .text.HAL_RCC_OscConfig:000004e0 $d
+     /tmp/ccu53ZgF.s:1344   .text.HAL_RCC_MCOConfig:00000000 $t
+     /tmp/ccu53ZgF.s:1350   .text.HAL_RCC_MCOConfig:00000000 HAL_RCC_MCOConfig
+     /tmp/ccu53ZgF.s:1452   .text.HAL_RCC_MCOConfig:00000058 $d
+     /tmp/ccu53ZgF.s:1457   .text.HAL_RCC_GetSysClockFreq:00000000 $t
+     /tmp/ccu53ZgF.s:1463   .text.HAL_RCC_GetSysClockFreq:00000000 HAL_RCC_GetSysClockFreq
+     /tmp/ccu53ZgF.s:1585   .text.HAL_RCC_GetSysClockFreq:0000007c $d
+     /tmp/ccu53ZgF.s:1592   .text.HAL_RCC_ClockConfig:00000000 $t
+     /tmp/ccu53ZgF.s:1598   .text.HAL_RCC_ClockConfig:00000000 HAL_RCC_ClockConfig
+     /tmp/ccu53ZgF.s:2009   .text.HAL_RCC_ClockConfig:000001e0 $d
+     /tmp/ccu53ZgF.s:2019   .text.HAL_RCC_GetHCLKFreq:00000000 $t
+     /tmp/ccu53ZgF.s:2025   .text.HAL_RCC_GetHCLKFreq:00000000 HAL_RCC_GetHCLKFreq
+     /tmp/ccu53ZgF.s:2040   .text.HAL_RCC_GetHCLKFreq:00000008 $d
+     /tmp/ccu53ZgF.s:2045   .text.HAL_RCC_GetPCLK1Freq:00000000 $t
+     /tmp/ccu53ZgF.s:2051   .text.HAL_RCC_GetPCLK1Freq:00000000 HAL_RCC_GetPCLK1Freq
+     /tmp/ccu53ZgF.s:2082   .text.HAL_RCC_GetPCLK1Freq:0000001c $d
+     /tmp/ccu53ZgF.s:2088   .text.HAL_RCC_GetPCLK2Freq:00000000 $t
+     /tmp/ccu53ZgF.s:2094   .text.HAL_RCC_GetPCLK2Freq:00000000 HAL_RCC_GetPCLK2Freq
+     /tmp/ccu53ZgF.s:2125   .text.HAL_RCC_GetPCLK2Freq:0000001c $d
+     /tmp/ccu53ZgF.s:2131   .text.HAL_RCC_GetOscConfig:00000000 $t
+     /tmp/ccu53ZgF.s:2137   .text.HAL_RCC_GetOscConfig:00000000 HAL_RCC_GetOscConfig
+     /tmp/ccu53ZgF.s:2348   .text.HAL_RCC_GetOscConfig:000000f0 $d
+     /tmp/ccu53ZgF.s:2353   .text.HAL_RCC_GetClockConfig:00000000 $t
+     /tmp/ccu53ZgF.s:2359   .text.HAL_RCC_GetClockConfig:00000000 HAL_RCC_GetClockConfig
+     /tmp/ccu53ZgF.s:2412   .text.HAL_RCC_GetClockConfig:00000034 $d
+     /tmp/ccu53ZgF.s:2418   .text.HAL_RCC_EnableCSS:00000000 $t
+     /tmp/ccu53ZgF.s:2424   .text.HAL_RCC_EnableCSS:00000000 HAL_RCC_EnableCSS
+     /tmp/ccu53ZgF.s:2441   .text.HAL_RCC_EnableCSS:0000000c $d
+     /tmp/ccu53ZgF.s:2446   .text.HAL_RCC_EnableLSECSS:00000000 $t
+     /tmp/ccu53ZgF.s:2452   .text.HAL_RCC_EnableLSECSS:00000000 HAL_RCC_EnableLSECSS
+     /tmp/ccu53ZgF.s:2469   .text.HAL_RCC_EnableLSECSS:00000010 $d
+     /tmp/ccu53ZgF.s:2474   .text.HAL_RCC_DisableLSECSS:00000000 $t
+     /tmp/ccu53ZgF.s:2480   .text.HAL_RCC_DisableLSECSS:00000000 HAL_RCC_DisableLSECSS
+     /tmp/ccu53ZgF.s:2497   .text.HAL_RCC_DisableLSECSS:00000010 $d
+     /tmp/ccu53ZgF.s:2502   .text.HAL_RCC_CSSCallback:00000000 $t
+     /tmp/ccu53ZgF.s:2508   .text.HAL_RCC_CSSCallback:00000000 HAL_RCC_CSSCallback
+     /tmp/ccu53ZgF.s:2521   .text.HAL_RCC_NMI_IRQHandler:00000000 $t
+     /tmp/ccu53ZgF.s:2527   .text.HAL_RCC_NMI_IRQHandler:00000000 HAL_RCC_NMI_IRQHandler
+     /tmp/ccu53ZgF.s:2561   .text.HAL_RCC_NMI_IRQHandler:0000001c $d
+
+UNDEFINED SYMBOLS
+HAL_GetTick
+HAL_InitTick
+SystemCoreClock
+uwTickPrio
+ARM GAS  /tmp/ccu53ZgF.s 			page 85
+
+
+HAL_GPIO_Init
+AHBPrescTable
+APBPrescTable
diff --git a/squeow_sw/build/stm32g4xx_hal_rcc.o b/squeow_sw/build/stm32g4xx_hal_rcc.o
new file mode 100644
index 0000000000000000000000000000000000000000..58fc026959930478e1e32bf942858f5fa779a902
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diff --git a/squeow_sw/build/stm32g4xx_hal_rcc_ex.d b/squeow_sw/build/stm32g4xx_hal_rcc_ex.d
new file mode 100644
index 0000000..e4eb9c9
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_rcc_ex.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_rcc_ex.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_rcc_ex.lst b/squeow_sw/build/stm32g4xx_hal_rcc_ex.lst
new file mode 100644
index 0000000..7b87dcb
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_rcc_ex.lst
@@ -0,0 +1,5781 @@
+ARM GAS  /tmp/ccXzHHIc.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_rcc_ex.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c"
+  20              		.section	.text.HAL_RCCEx_PeriphCLKConfig,"ax",%progbits
+  21              		.align	1
+  22              		.global	HAL_RCCEx_PeriphCLKConfig
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	HAL_RCCEx_PeriphCLKConfig:
+  28              	.LVL0:
+  29              	.LFB329:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @file    stm32g4xx_hal_rcc_ex.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief   Extended RCC HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *          functionalities RCC extended peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *           + Extended Peripheral Control functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *           + Extended Clock management functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *           + Extended Clock Recovery System Control functions
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   ******************************************************************************
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @attention
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * Copyright (c) 2019 STMicroelectronics.
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * All rights reserved.
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * the root directory of this software component.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   ******************************************************************************
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Includes ------------------------------------------------------------------*/
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #include "stm32g4xx_hal.h"
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @{
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+ARM GAS  /tmp/ccXzHHIc.s 			page 2
+
+
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx RCCEx
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief RCC Extended HAL module driver
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @{
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #ifdef HAL_RCC_MODULE_ENABLED
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Private typedef -----------------------------------------------------------*/
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Private defines -----------------------------------------------------------*/
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  * @{
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  */
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define PLL_TIMEOUT_VALUE        2U                /* 2 ms (minimum Tick + 1) */
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define DIVIDER_P_UPDATE          0U
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define DIVIDER_Q_UPDATE          1U
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define DIVIDER_R_UPDATE          2U
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define __LSCO_CLK_ENABLE()       __HAL_RCC_GPIOA_CLK_ENABLE()
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define LSCO_GPIO_PORT            GPIOA
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define LSCO_PIN                  GPIO_PIN_2
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @}
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Private macros ------------------------------------------------------------*/
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Private variables ---------------------------------------------------------*/
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Private function prototypes -----------------------------------------------*/
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  * @{
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  */
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @}
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Exported functions --------------------------------------------------------*/
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @{
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  *  @brief  Extended Peripheral Control functions
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  *
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** @verbatim
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  ===============================================================================
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                 ##### Extended Peripheral Control functions  #####
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  ===============================================================================
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     [..]
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     This subsection provides a set of functions allowing to control the RCC Clocks
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     frequencies.
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     [..]
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         select the RTC clock source; in this case the Backup domain will be reset in
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         order to modify the RTC Clock source, as consequence RTC registers (including
+ARM GAS  /tmp/ccXzHHIc.s 			page 3
+
+
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         the backup registers) are set to their reset values.
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** @endverbatim
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @{
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  Initialize the RCC extended peripherals clocks according to the specified
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *         parameters in the RCC_PeriphCLKInitTypeDef.
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *         contains a field PeriphClockSelection which can be a combination of the following value
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_I2S  I2S peripheral clock
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_FDCAN  FDCAN peripheral clock (only for devices with FDCAN)
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_ADC12  ADC1 and ADC2 peripheral clock
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_ADC345  ADC3, ADC4 and ADC5 peripheral clock (only for devic
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_QSPI  QuadSPI peripheral clock (only for devices with QuadSP
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *         the RTC clock source: in this case the access to Backup domain is enabled.
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval HAL status
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+  30              		.loc 1 124 1 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 8
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		.loc 1 124 1 is_stmt 0 view .LVU1
+  35 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+  36              	.LCFI0:
+  37              		.cfi_def_cfa_offset 20
+  38              		.cfi_offset 4, -20
+  39              		.cfi_offset 5, -16
+  40              		.cfi_offset 6, -12
+  41              		.cfi_offset 7, -8
+  42              		.cfi_offset 14, -4
+  43 0002 83B0     		sub	sp, sp, #12
+  44              	.LCFI1:
+  45              		.cfi_def_cfa_offset 32
+  46 0004 0446     		mov	r4, r0
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t tmpregister;
+  47              		.loc 1 125 3 is_stmt 1 view .LVU2
+ARM GAS  /tmp/ccXzHHIc.s 			page 4
+
+
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t tickstart;
+  48              		.loc 1 126 3 view .LVU3
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
+  49              		.loc 1 127 3 view .LVU4
+  50              	.LVL1:
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+  51              		.loc 1 128 3 view .LVU5
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Check the parameters */
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+  52              		.loc 1 131 3 view .LVU6
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- RTC clock source configuration ----------------------*/
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+  53              		.loc 1 134 3 view .LVU7
+  54              		.loc 1 134 20 is_stmt 0 view .LVU8
+  55 0006 0368     		ldr	r3, [r0]
+  56              		.loc 1 134 5 view .LVU9
+  57 0008 13F4002F 		tst	r3, #524288
+  58 000c 69D0     		beq	.L27
+  59              	.LBB2:
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     FlagStatus       pwrclkchanged = RESET;
+  60              		.loc 1 136 5 is_stmt 1 view .LVU10
+  61              	.LVL2:
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check for RTC Parameters used to output RTCCLK */
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+  62              		.loc 1 139 5 view .LVU11
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Enable Power Clock */
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+  63              		.loc 1 142 5 view .LVU12
+  64              		.loc 1 142 8 is_stmt 0 view .LVU13
+  65 000e AE4B     		ldr	r3, .L40
+  66 0010 9B6D     		ldr	r3, [r3, #88]
+  67              		.loc 1 142 7 view .LVU14
+  68 0012 13F0805F 		tst	r3, #268435456
+  69 0016 1ED1     		bne	.L28
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_PWR_CLK_ENABLE();
+  70              		.loc 1 144 7 is_stmt 1 view .LVU15
+  71              	.LBB3:
+  72              		.loc 1 144 7 view .LVU16
+  73              		.loc 1 144 7 view .LVU17
+  74 0018 AB4B     		ldr	r3, .L40
+  75 001a 9A6D     		ldr	r2, [r3, #88]
+  76 001c 42F08052 		orr	r2, r2, #268435456
+  77 0020 9A65     		str	r2, [r3, #88]
+  78              		.loc 1 144 7 view .LVU18
+  79 0022 9B6D     		ldr	r3, [r3, #88]
+  80 0024 03F08053 		and	r3, r3, #268435456
+  81 0028 0193     		str	r3, [sp, #4]
+  82              		.loc 1 144 7 view .LVU19
+  83 002a 019B     		ldr	r3, [sp, #4]
+  84              	.LBE3:
+  85              		.loc 1 144 7 view .LVU20
+ARM GAS  /tmp/ccXzHHIc.s 			page 5
+
+
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       pwrclkchanged = SET;
+  86              		.loc 1 145 7 view .LVU21
+  87              	.LVL3:
+  88              		.loc 1 145 21 is_stmt 0 view .LVU22
+  89 002c 0126     		movs	r6, #1
+  90              	.LVL4:
+  91              	.L3:
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Enable write access to Backup domain */
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     SET_BIT(PWR->CR1, PWR_CR1_DBP);
+  92              		.loc 1 149 5 is_stmt 1 view .LVU23
+  93 002e A74A     		ldr	r2, .L40+4
+  94 0030 1368     		ldr	r3, [r2]
+  95 0032 43F48073 		orr	r3, r3, #256
+  96 0036 1360     		str	r3, [r2]
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Wait for Backup domain Write protection disable */
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     tickstart = HAL_GetTick();
+  97              		.loc 1 152 5 view .LVU24
+  98              		.loc 1 152 17 is_stmt 0 view .LVU25
+  99 0038 FFF7FEFF 		bl	HAL_GetTick
+ 100              	.LVL5:
+ 101              		.loc 1 152 17 view .LVU26
+ 102 003c 0546     		mov	r5, r0
+ 103              	.LVL6:
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     while((PWR->CR1 & PWR_CR1_DBP) == 0U)
+ 104              		.loc 1 154 5 is_stmt 1 view .LVU27
+ 105              	.L4:
+ 106              		.loc 1 154 36 view .LVU28
+ 107              		.loc 1 154 15 is_stmt 0 view .LVU29
+ 108 003e A34B     		ldr	r3, .L40+4
+ 109 0040 1B68     		ldr	r3, [r3]
+ 110              		.loc 1 154 36 view .LVU30
+ 111 0042 13F4807F 		tst	r3, #256
+ 112 0046 08D1     		bne	.L32
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 113              		.loc 1 156 7 is_stmt 1 view .LVU31
+ 114              		.loc 1 156 11 is_stmt 0 view .LVU32
+ 115 0048 FFF7FEFF 		bl	HAL_GetTick
+ 116              	.LVL7:
+ 117              		.loc 1 156 25 view .LVU33
+ 118 004c 401B     		subs	r0, r0, r5
+ 119              		.loc 1 156 9 view .LVU34
+ 120 004e 0228     		cmp	r0, #2
+ 121 0050 F5D9     		bls	.L4
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         ret = HAL_TIMEOUT;
+ 122              		.loc 1 158 13 view .LVU35
+ 123 0052 0325     		movs	r5, #3
+ 124              	.LVL8:
+ 125              		.loc 1 158 13 view .LVU36
+ 126 0054 02E0     		b	.L5
+ 127              	.LVL9:
+ 128              	.L28:
+ARM GAS  /tmp/ccXzHHIc.s 			page 6
+
+
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     
+ 129              		.loc 1 136 22 view .LVU37
+ 130 0056 0026     		movs	r6, #0
+ 131 0058 E9E7     		b	.L3
+ 132              	.LVL10:
+ 133              	.L32:
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     
+ 134              		.loc 1 136 22 view .LVU38
+ 135              	.LBE2:
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+ 136              		.loc 1 127 21 view .LVU39
+ 137 005a 0025     		movs	r5, #0
+ 138              	.LVL11:
+ 139              	.L5:
+ 140              	.LBB4:
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         break;
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(ret == HAL_OK)
+ 141              		.loc 1 163 5 is_stmt 1 view .LVU40
+ 142              		.loc 1 163 7 is_stmt 0 view .LVU41
+ 143 005c 45BB     		cbnz	r5, .L7
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     { 
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
+ 144              		.loc 1 166 7 is_stmt 1 view .LVU42
+ 145              		.loc 1 166 21 is_stmt 0 view .LVU43
+ 146 005e 9A4B     		ldr	r3, .L40
+ 147 0060 D3F89030 		ldr	r3, [r3, #144]
+ 148              	.LVL12:
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection
+ 149              		.loc 1 168 7 is_stmt 1 view .LVU44
+ 150              		.loc 1 168 9 is_stmt 0 view .LVU45
+ 151 0064 13F44073 		ands	r3, r3, #768
+ 152              	.LVL13:
+ 153              		.loc 1 168 9 view .LVU46
+ 154 0068 15D0     		beq	.L8
+ 155              		.loc 1 168 81 discriminator 1 view .LVU47
+ 156 006a 226C     		ldr	r2, [r4, #64]
+ 157              		.loc 1 168 49 discriminator 1 view .LVU48
+ 158 006c 9A42     		cmp	r2, r3
+ 159 006e 12D0     		beq	.L8
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* Store the content of BDCR register before the reset of Backup Domain */
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
+ 160              		.loc 1 171 9 is_stmt 1 view .LVU49
+ 161              		.loc 1 171 23 is_stmt 0 view .LVU50
+ 162 0070 954A     		ldr	r2, .L40
+ 163 0072 D2F89030 		ldr	r3, [r2, #144]
+ 164              	.LVL14:
+ 165              		.loc 1 171 21 view .LVU51
+ 166 0076 23F44073 		bic	r3, r3, #768
+ 167              	.LVL15:
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         __HAL_RCC_BACKUPRESET_FORCE();
+ARM GAS  /tmp/ccXzHHIc.s 			page 7
+
+
+ 168              		.loc 1 173 9 is_stmt 1 view .LVU52
+ 169 007a D2F89010 		ldr	r1, [r2, #144]
+ 170 007e 41F48031 		orr	r1, r1, #65536
+ 171 0082 C2F89010 		str	r1, [r2, #144]
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         __HAL_RCC_BACKUPRESET_RELEASE();
+ 172              		.loc 1 174 9 view .LVU53
+ 173 0086 D2F89010 		ldr	r1, [r2, #144]
+ 174 008a 21F48031 		bic	r1, r1, #65536
+ 175 008e C2F89010 		str	r1, [r2, #144]
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* Restore the Content of BDCR register */
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         RCC->BDCR = tmpregister;
+ 176              		.loc 1 176 9 view .LVU54
+ 177              		.loc 1 176 19 is_stmt 0 view .LVU55
+ 178 0092 C2F89030 		str	r3, [r2, #144]
+ 179              	.L8:
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
+ 180              		.loc 1 180 7 is_stmt 1 view .LVU56
+ 181              		.loc 1 180 10 is_stmt 0 view .LVU57
+ 182 0096 13F0010F 		tst	r3, #1
+ 183 009a 10D1     		bne	.L33
+ 184              	.LVL16:
+ 185              	.L9:
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* Get Start Tick*/
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         tickstart = HAL_GetTick();
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* Wait till LSE is ready */
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           {
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             ret = HAL_TIMEOUT;
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             break;
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           }
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(ret == HAL_OK)
+ 186              		.loc 1 196 7 is_stmt 1 view .LVU58
+ 187              		.loc 1 196 9 is_stmt 0 view .LVU59
+ 188 009c 45B9     		cbnz	r5, .L7
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* Apply new RTC clock source selection */
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ 189              		.loc 1 199 9 is_stmt 1 view .LVU60
+ 190 009e 8A4A     		ldr	r2, .L40
+ 191 00a0 D2F89030 		ldr	r3, [r2, #144]
+ 192 00a4 23F44073 		bic	r3, r3, #768
+ 193 00a8 216C     		ldr	r1, [r4, #64]
+ 194 00aa 0B43     		orrs	r3, r3, r1
+ 195 00ac C2F89030 		str	r3, [r2, #144]
+ 196              	.LVL17:
+ 197              	.L7:
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ARM GAS  /tmp/ccXzHHIc.s 			page 8
+
+
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* set overall return value */
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         status = ret;
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     else
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* set overall return value */
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       status = ret;
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Restore clock configuration if changed */
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(pwrclkchanged == SET)
+ 198              		.loc 1 214 5 view .LVU61
+ 199              		.loc 1 214 7 is_stmt 0 view .LVU62
+ 200 00b0 C6B1     		cbz	r6, .L2
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_PWR_CLK_DISABLE();
+ 201              		.loc 1 216 7 is_stmt 1 view .LVU63
+ 202 00b2 854A     		ldr	r2, .L40
+ 203 00b4 936D     		ldr	r3, [r2, #88]
+ 204 00b6 23F08053 		bic	r3, r3, #268435456
+ 205 00ba 9365     		str	r3, [r2, #88]
+ 206 00bc 12E0     		b	.L2
+ 207              	.LVL18:
+ 208              	.L33:
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 209              		.loc 1 183 9 view .LVU64
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 210              		.loc 1 183 21 is_stmt 0 view .LVU65
+ 211 00be FFF7FEFF 		bl	HAL_GetTick
+ 212              	.LVL19:
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 213              		.loc 1 183 21 view .LVU66
+ 214 00c2 0746     		mov	r7, r0
+ 215              	.LVL20:
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 216              		.loc 1 186 9 is_stmt 1 view .LVU67
+ 217              	.L10:
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 218              		.loc 1 186 52 view .LVU68
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 219              		.loc 1 186 15 is_stmt 0 view .LVU69
+ 220 00c4 804B     		ldr	r3, .L40
+ 221 00c6 D3F89030 		ldr	r3, [r3, #144]
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 222              		.loc 1 186 52 view .LVU70
+ 223 00ca 13F0020F 		tst	r3, #2
+ 224 00ce E5D1     		bne	.L9
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           {
+ 225              		.loc 1 188 11 is_stmt 1 view .LVU71
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           {
+ 226              		.loc 1 188 15 is_stmt 0 view .LVU72
+ 227 00d0 FFF7FEFF 		bl	HAL_GetTick
+ 228              	.LVL21:
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           {
+ARM GAS  /tmp/ccXzHHIc.s 			page 9
+
+
+ 229              		.loc 1 188 29 view .LVU73
+ 230 00d4 C01B     		subs	r0, r0, r7
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           {
+ 231              		.loc 1 188 13 view .LVU74
+ 232 00d6 41F28833 		movw	r3, #5000
+ 233 00da 9842     		cmp	r0, r3
+ 234 00dc F2D9     		bls	.L10
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             break;
+ 235              		.loc 1 190 17 view .LVU75
+ 236 00de 0325     		movs	r5, #3
+ 237              	.LVL22:
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             break;
+ 238              		.loc 1 190 17 view .LVU76
+ 239 00e0 DCE7     		b	.L9
+ 240              	.LVL23:
+ 241              	.L27:
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             break;
+ 242              		.loc 1 190 17 view .LVU77
+ 243              	.LBE4:
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 244              		.loc 1 128 21 view .LVU78
+ 245 00e2 0025     		movs	r5, #0
+ 246              	.LVL24:
+ 247              	.L2:
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- USART1 clock source configuration -------------------*/
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+ 248              		.loc 1 221 3 is_stmt 1 view .LVU79
+ 249              		.loc 1 221 21 is_stmt 0 view .LVU80
+ 250 00e4 2368     		ldr	r3, [r4]
+ 251              		.loc 1 221 5 view .LVU81
+ 252 00e6 13F0010F 		tst	r3, #1
+ 253 00ea 08D0     		beq	.L12
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+ 254              		.loc 1 224 5 is_stmt 1 view .LVU82
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the USART1 clock source */
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+ 255              		.loc 1 227 5 view .LVU83
+ 256 00ec 764A     		ldr	r2, .L40
+ 257 00ee D2F88830 		ldr	r3, [r2, #136]
+ 258 00f2 23F00303 		bic	r3, r3, #3
+ 259 00f6 6168     		ldr	r1, [r4, #4]
+ 260 00f8 0B43     		orrs	r3, r3, r1
+ 261 00fa C2F88830 		str	r3, [r2, #136]
+ 262              	.L12:
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- USART2 clock source configuration -------------------*/
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+ 263              		.loc 1 231 3 view .LVU84
+ 264              		.loc 1 231 21 is_stmt 0 view .LVU85
+ 265 00fe 2368     		ldr	r3, [r4]
+ARM GAS  /tmp/ccXzHHIc.s 			page 10
+
+
+ 266              		.loc 1 231 5 view .LVU86
+ 267 0100 13F0020F 		tst	r3, #2
+ 268 0104 08D0     		beq	.L13
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+ 269              		.loc 1 234 5 is_stmt 1 view .LVU87
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the USART2 clock source */
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+ 270              		.loc 1 237 5 view .LVU88
+ 271 0106 704A     		ldr	r2, .L40
+ 272 0108 D2F88830 		ldr	r3, [r2, #136]
+ 273 010c 23F00C03 		bic	r3, r3, #12
+ 274 0110 A168     		ldr	r1, [r4, #8]
+ 275 0112 0B43     		orrs	r3, r3, r1
+ 276 0114 C2F88830 		str	r3, [r2, #136]
+ 277              	.L13:
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- USART3 clock source configuration -------------------*/
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+ 278              		.loc 1 241 3 view .LVU89
+ 279              		.loc 1 241 21 is_stmt 0 view .LVU90
+ 280 0118 2368     		ldr	r3, [r4]
+ 281              		.loc 1 241 5 view .LVU91
+ 282 011a 13F0040F 		tst	r3, #4
+ 283 011e 08D0     		beq	.L14
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+ 284              		.loc 1 244 5 is_stmt 1 view .LVU92
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the USART3 clock source */
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+ 285              		.loc 1 247 5 view .LVU93
+ 286 0120 694A     		ldr	r2, .L40
+ 287 0122 D2F88830 		ldr	r3, [r2, #136]
+ 288 0126 23F03003 		bic	r3, r3, #48
+ 289 012a E168     		ldr	r1, [r4, #12]
+ 290 012c 0B43     		orrs	r3, r3, r1
+ 291 012e C2F88830 		str	r3, [r2, #136]
+ 292              	.L14:
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(UART4)
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- UART4 clock source configuration --------------------*/
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
+ 293              		.loc 1 252 3 view .LVU94
+ 294              		.loc 1 252 21 is_stmt 0 view .LVU95
+ 295 0132 2368     		ldr	r3, [r4]
+ 296              		.loc 1 252 5 view .LVU96
+ 297 0134 13F0080F 		tst	r3, #8
+ 298 0138 08D0     		beq	.L15
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
+ARM GAS  /tmp/ccXzHHIc.s 			page 11
+
+
+ 299              		.loc 1 255 5 is_stmt 1 view .LVU97
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the UART4 clock source */
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
+ 300              		.loc 1 258 5 view .LVU98
+ 301 013a 634A     		ldr	r2, .L40
+ 302 013c D2F88830 		ldr	r3, [r2, #136]
+ 303 0140 23F0C003 		bic	r3, r3, #192
+ 304 0144 2169     		ldr	r1, [r4, #16]
+ 305 0146 0B43     		orrs	r3, r3, r1
+ 306 0148 C2F88830 		str	r3, [r2, #136]
+ 307              	.L15:
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* UART4 */
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(UART5)
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- UART5 clock source configuration --------------------*/
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the UART5 clock source */
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* UART5 */
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- LPUART1 clock source configuration ------------------*/
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+ 308              		.loc 1 277 3 view .LVU99
+ 309              		.loc 1 277 21 is_stmt 0 view .LVU100
+ 310 014c 2368     		ldr	r3, [r4]
+ 311              		.loc 1 277 5 view .LVU101
+ 312 014e 13F0200F 		tst	r3, #32
+ 313 0152 08D0     		beq	.L16
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
+ 314              		.loc 1 280 5 is_stmt 1 view .LVU102
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the LPUAR1 clock source */
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+ 315              		.loc 1 283 5 view .LVU103
+ 316 0154 5C4A     		ldr	r2, .L40
+ 317 0156 D2F88830 		ldr	r3, [r2, #136]
+ 318 015a 23F44063 		bic	r3, r3, #3072
+ 319 015e 6169     		ldr	r1, [r4, #20]
+ 320 0160 0B43     		orrs	r3, r3, r1
+ 321 0162 C2F88830 		str	r3, [r2, #136]
+ 322              	.L16:
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- I2C1 clock source configuration ---------------------*/
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+ 323              		.loc 1 287 3 view .LVU104
+ARM GAS  /tmp/ccXzHHIc.s 			page 12
+
+
+ 324              		.loc 1 287 21 is_stmt 0 view .LVU105
+ 325 0166 2368     		ldr	r3, [r4]
+ 326              		.loc 1 287 5 view .LVU106
+ 327 0168 13F0400F 		tst	r3, #64
+ 328 016c 08D0     		beq	.L17
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+ 329              		.loc 1 290 5 is_stmt 1 view .LVU107
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the I2C1 clock source */
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+ 330              		.loc 1 293 5 view .LVU108
+ 331 016e 564A     		ldr	r2, .L40
+ 332 0170 D2F88830 		ldr	r3, [r2, #136]
+ 333 0174 23F44053 		bic	r3, r3, #12288
+ 334 0178 A169     		ldr	r1, [r4, #24]
+ 335 017a 0B43     		orrs	r3, r3, r1
+ 336 017c C2F88830 		str	r3, [r2, #136]
+ 337              	.L17:
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- I2C2 clock source configuration ---------------------*/
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
+ 338              		.loc 1 297 3 view .LVU109
+ 339              		.loc 1 297 21 is_stmt 0 view .LVU110
+ 340 0180 2368     		ldr	r3, [r4]
+ 341              		.loc 1 297 5 view .LVU111
+ 342 0182 13F0800F 		tst	r3, #128
+ 343 0186 08D0     		beq	.L18
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
+ 344              		.loc 1 300 5 is_stmt 1 view .LVU112
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the I2C2 clock source */
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
+ 345              		.loc 1 303 5 view .LVU113
+ 346 0188 4F4A     		ldr	r2, .L40
+ 347 018a D2F88830 		ldr	r3, [r2, #136]
+ 348 018e 23F44043 		bic	r3, r3, #49152
+ 349 0192 E169     		ldr	r1, [r4, #28]
+ 350 0194 0B43     		orrs	r3, r3, r1
+ 351 0196 C2F88830 		str	r3, [r2, #136]
+ 352              	.L18:
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- I2C3 clock source configuration ---------------------*/
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
+ 353              		.loc 1 307 3 view .LVU114
+ 354              		.loc 1 307 21 is_stmt 0 view .LVU115
+ 355 019a 2368     		ldr	r3, [r4]
+ 356              		.loc 1 307 5 view .LVU116
+ 357 019c 13F4807F 		tst	r3, #256
+ 358 01a0 08D0     		beq	.L19
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ARM GAS  /tmp/ccXzHHIc.s 			page 13
+
+
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
+ 359              		.loc 1 310 5 is_stmt 1 view .LVU117
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the I2C3 clock source */
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
+ 360              		.loc 1 313 5 view .LVU118
+ 361 01a2 494A     		ldr	r2, .L40
+ 362 01a4 D2F88830 		ldr	r3, [r2, #136]
+ 363 01a8 23F44033 		bic	r3, r3, #196608
+ 364 01ac 216A     		ldr	r1, [r4, #32]
+ 365 01ae 0B43     		orrs	r3, r3, r1
+ 366 01b0 C2F88830 		str	r3, [r2, #136]
+ 367              	.L19:
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(I2C4)  
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- I2C4 clock source configuration ---------------------*/
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the I2C4 clock source */
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* I2C4 */
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- LPTIM1 clock source configuration ---------------------*/
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+ 368              		.loc 1 331 3 view .LVU119
+ 369              		.loc 1 331 21 is_stmt 0 view .LVU120
+ 370 01b4 2368     		ldr	r3, [r4]
+ 371              		.loc 1 331 5 view .LVU121
+ 372 01b6 13F4007F 		tst	r3, #512
+ 373 01ba 08D0     		beq	.L20
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
+ 374              		.loc 1 334 5 is_stmt 1 view .LVU122
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the LPTIM1 clock source */
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+ 375              		.loc 1 337 5 view .LVU123
+ 376 01bc 424A     		ldr	r2, .L40
+ 377 01be D2F88830 		ldr	r3, [r2, #136]
+ 378 01c2 23F44023 		bic	r3, r3, #786432
+ 379 01c6 616A     		ldr	r1, [r4, #36]
+ 380 01c8 0B43     		orrs	r3, r3, r1
+ 381 01ca C2F88830 		str	r3, [r2, #136]
+ 382              	.L20:
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- SAI1 clock source configuration ---------------------*/
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
+ 383              		.loc 1 341 3 view .LVU124
+ARM GAS  /tmp/ccXzHHIc.s 			page 14
+
+
+ 384              		.loc 1 341 21 is_stmt 0 view .LVU125
+ 385 01ce 2368     		ldr	r3, [r4]
+ 386              		.loc 1 341 5 view .LVU126
+ 387 01d0 13F4806F 		tst	r3, #1024
+ 388 01d4 0CD0     		beq	.L21
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+ 389              		.loc 1 344 5 is_stmt 1 view .LVU127
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the SAI1 interface clock source */
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+ 390              		.loc 1 347 5 view .LVU128
+ 391 01d6 3C4A     		ldr	r2, .L40
+ 392 01d8 D2F88830 		ldr	r3, [r2, #136]
+ 393 01dc 23F44013 		bic	r3, r3, #3145728
+ 394 01e0 A16A     		ldr	r1, [r4, #40]
+ 395 01e2 0B43     		orrs	r3, r3, r1
+ 396 01e4 C2F88830 		str	r3, [r2, #136]
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
+ 397              		.loc 1 349 5 view .LVU129
+ 398              		.loc 1 349 21 is_stmt 0 view .LVU130
+ 399 01e8 A36A     		ldr	r3, [r4, #40]
+ 400              		.loc 1 349 7 view .LVU131
+ 401 01ea B3F5801F 		cmp	r3, #1048576
+ 402 01ee 57D0     		beq	.L34
+ 403              	.L21:
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Enable PLL48M1CLK output */
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- I2S clock source configuration ---------------------*/
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
+ 404              		.loc 1 357 3 is_stmt 1 view .LVU132
+ 405              		.loc 1 357 21 is_stmt 0 view .LVU133
+ 406 01f0 2368     		ldr	r3, [r4]
+ 407              		.loc 1 357 5 view .LVU134
+ 408 01f2 13F4006F 		tst	r3, #2048
+ 409 01f6 0CD0     		beq	.L22
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
+ 410              		.loc 1 360 5 is_stmt 1 view .LVU135
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the I2S interface clock source */
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
+ 411              		.loc 1 363 5 view .LVU136
+ 412 01f8 334A     		ldr	r2, .L40
+ 413 01fa D2F88830 		ldr	r3, [r2, #136]
+ 414 01fe 23F44003 		bic	r3, r3, #12582912
+ 415 0202 E16A     		ldr	r1, [r4, #44]
+ 416 0204 0B43     		orrs	r3, r3, r1
+ 417 0206 C2F88830 		str	r3, [r2, #136]
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     
+ARM GAS  /tmp/ccXzHHIc.s 			page 15
+
+
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
+ 418              		.loc 1 365 5 view .LVU137
+ 419              		.loc 1 365 21 is_stmt 0 view .LVU138
+ 420 020a E36A     		ldr	r3, [r4, #44]
+ 421              		.loc 1 365 7 view .LVU139
+ 422 020c B3F5800F 		cmp	r3, #4194304
+ 423 0210 4BD0     		beq	.L35
+ 424              	.L22:
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Enable PLL48M1CLK output */
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(FDCAN1)
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- FDCAN clock source configuration ---------------------*/
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
+ 425              		.loc 1 374 3 is_stmt 1 view .LVU140
+ 426              		.loc 1 374 21 is_stmt 0 view .LVU141
+ 427 0212 2368     		ldr	r3, [r4]
+ 428              		.loc 1 374 5 view .LVU142
+ 429 0214 13F4805F 		tst	r3, #4096
+ 430 0218 0CD0     		beq	.L23
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
+ 431              		.loc 1 377 5 is_stmt 1 view .LVU143
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the FDCAN interface clock source */
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
+ 432              		.loc 1 380 5 view .LVU144
+ 433 021a 2B4A     		ldr	r2, .L40
+ 434 021c D2F88830 		ldr	r3, [r2, #136]
+ 435 0220 23F04073 		bic	r3, r3, #50331648
+ 436 0224 216B     		ldr	r1, [r4, #48]
+ 437 0226 0B43     		orrs	r3, r3, r1
+ 438 0228 C2F88830 		str	r3, [r2, #136]
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
+ 439              		.loc 1 382 5 view .LVU145
+ 440              		.loc 1 382 21 is_stmt 0 view .LVU146
+ 441 022c 236B     		ldr	r3, [r4, #48]
+ 442              		.loc 1 382 7 view .LVU147
+ 443 022e B3F1807F 		cmp	r3, #16777216
+ 444 0232 3FD0     		beq	.L36
+ 445              	.L23:
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Enable PLL48M1CLK output */
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* FDCAN1 */
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(USB)
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- USB clock source configuration ----------------------*/
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
+ARM GAS  /tmp/ccXzHHIc.s 			page 16
+
+
+ 446              		.loc 1 393 3 is_stmt 1 view .LVU148
+ 447              		.loc 1 393 21 is_stmt 0 view .LVU149
+ 448 0234 2368     		ldr	r3, [r4]
+ 449              		.loc 1 393 5 view .LVU150
+ 450 0236 13F4005F 		tst	r3, #8192
+ 451 023a 0CD0     		beq	.L24
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
+ 452              		.loc 1 395 5 is_stmt 1 view .LVU151
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+ 453              		.loc 1 396 5 view .LVU152
+ 454 023c 224A     		ldr	r2, .L40
+ 455 023e D2F88830 		ldr	r3, [r2, #136]
+ 456 0242 23F04063 		bic	r3, r3, #201326592
+ 457 0246 616B     		ldr	r1, [r4, #52]
+ 458 0248 0B43     		orrs	r3, r3, r1
+ 459 024a C2F88830 		str	r3, [r2, #136]
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
+ 460              		.loc 1 398 5 view .LVU153
+ 461              		.loc 1 398 21 is_stmt 0 view .LVU154
+ 462 024e 636B     		ldr	r3, [r4, #52]
+ 463              		.loc 1 398 7 view .LVU155
+ 464 0250 B3F1006F 		cmp	r3, #134217728
+ 465 0254 33D0     		beq	.L37
+ 466              	.L24:
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Enable PLL48M1CLK output */
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* USB */
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- RNG clock source configuration ----------------------*/
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
+ 467              		.loc 1 408 3 is_stmt 1 view .LVU156
+ 468              		.loc 1 408 21 is_stmt 0 view .LVU157
+ 469 0256 2368     		ldr	r3, [r4]
+ 470              		.loc 1 408 5 view .LVU158
+ 471 0258 13F4804F 		tst	r3, #16384
+ 472 025c 0CD0     		beq	.L25
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
+ 473              		.loc 1 410 5 is_stmt 1 view .LVU159
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
+ 474              		.loc 1 411 5 view .LVU160
+ 475 025e 1A4A     		ldr	r2, .L40
+ 476 0260 D2F88830 		ldr	r3, [r2, #136]
+ 477 0264 23F04063 		bic	r3, r3, #201326592
+ 478 0268 A16B     		ldr	r1, [r4, #56]
+ 479 026a 0B43     		orrs	r3, r3, r1
+ 480 026c C2F88830 		str	r3, [r2, #136]
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
+ 481              		.loc 1 413 5 view .LVU161
+ 482              		.loc 1 413 21 is_stmt 0 view .LVU162
+ARM GAS  /tmp/ccXzHHIc.s 			page 17
+
+
+ 483 0270 A36B     		ldr	r3, [r4, #56]
+ 484              		.loc 1 413 7 view .LVU163
+ 485 0272 B3F1006F 		cmp	r3, #134217728
+ 486 0276 2BD0     		beq	.L38
+ 487              	.L25:
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Enable PLL48M1CLK output */
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- ADC12 clock source configuration ----------------------*/
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
+ 488              		.loc 1 421 3 is_stmt 1 view .LVU164
+ 489              		.loc 1 421 21 is_stmt 0 view .LVU165
+ 490 0278 2368     		ldr	r3, [r4]
+ 491              		.loc 1 421 5 view .LVU166
+ 492 027a 13F4004F 		tst	r3, #32768
+ 493 027e 0CD0     		beq	.L26
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
+ 494              		.loc 1 424 5 is_stmt 1 view .LVU167
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the ADC12 interface clock source */
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
+ 495              		.loc 1 427 5 view .LVU168
+ 496 0280 114A     		ldr	r2, .L40
+ 497 0282 D2F88830 		ldr	r3, [r2, #136]
+ 498 0286 23F04053 		bic	r3, r3, #805306368
+ 499 028a E16B     		ldr	r1, [r4, #60]
+ 500 028c 0B43     		orrs	r3, r3, r1
+ 501 028e C2F88830 		str	r3, [r2, #136]
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
+ 502              		.loc 1 429 5 view .LVU169
+ 503              		.loc 1 429 21 is_stmt 0 view .LVU170
+ 504 0292 E36B     		ldr	r3, [r4, #60]
+ 505              		.loc 1 429 7 view .LVU171
+ 506 0294 B3F1805F 		cmp	r3, #268435456
+ 507 0298 1FD0     		beq	.L39
+ 508              	.L26:
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Enable PLLADCCLK output */
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(ADC345_COMMON)
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- ADC345 clock source configuration ----------------------*/
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345)
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_ADC345CLKSOURCE(PeriphClkInit->Adc345ClockSelection));
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the ADC345 interface clock source */
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_ADC345_CONFIG(PeriphClkInit->Adc345ClockSelection);
+ARM GAS  /tmp/ccXzHHIc.s 			page 18
+
+
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(PeriphClkInit->Adc345ClockSelection == RCC_ADC345CLKSOURCE_PLL)
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Enable PLLADCCLK output */
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* ADC345_COMMON */
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(QUADSPI)
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /*-------------------------- QuadSPIx clock source configuration ----------------*/
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection));
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Configure the QuadSPI clock source */
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(PeriphClkInit->QspiClockSelection == RCC_QSPICLKSOURCE_PLL)
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Enable PLL48M1CLK output */
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* QUADSPI */
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   return status;
+ 509              		.loc 1 474 3 is_stmt 1 view .LVU172
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 510              		.loc 1 475 1 is_stmt 0 view .LVU173
+ 511 029a 2846     		mov	r0, r5
+ 512 029c 03B0     		add	sp, sp, #12
+ 513              	.LCFI2:
+ 514              		.cfi_remember_state
+ 515              		.cfi_def_cfa_offset 20
+ 516              		@ sp needed
+ 517 029e F0BD     		pop	{r4, r5, r6, r7, pc}
+ 518              	.LVL25:
+ 519              	.L34:
+ 520              	.LCFI3:
+ 521              		.cfi_restore_state
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 522              		.loc 1 352 7 is_stmt 1 view .LVU174
+ 523 02a0 D368     		ldr	r3, [r2, #12]
+ 524 02a2 43F48013 		orr	r3, r3, #1048576
+ 525 02a6 D360     		str	r3, [r2, #12]
+ 526 02a8 A2E7     		b	.L21
+ 527              	.L35:
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 528              		.loc 1 368 7 view .LVU175
+ 529 02aa D368     		ldr	r3, [r2, #12]
+ 530 02ac 43F48013 		orr	r3, r3, #1048576
+ 531 02b0 D360     		str	r3, [r2, #12]
+ 532 02b2 AEE7     		b	.L22
+ARM GAS  /tmp/ccXzHHIc.s 			page 19
+
+
+ 533              	.L36:
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 534              		.loc 1 385 7 view .LVU176
+ 535 02b4 D368     		ldr	r3, [r2, #12]
+ 536 02b6 43F48013 		orr	r3, r3, #1048576
+ 537 02ba D360     		str	r3, [r2, #12]
+ 538 02bc BAE7     		b	.L23
+ 539              	.L37:
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 540              		.loc 1 401 7 view .LVU177
+ 541 02be D368     		ldr	r3, [r2, #12]
+ 542 02c0 43F48013 		orr	r3, r3, #1048576
+ 543 02c4 D360     		str	r3, [r2, #12]
+ 544 02c6 C6E7     		b	.L24
+ 545              	.L41:
+ 546              		.align	2
+ 547              	.L40:
+ 548 02c8 00100240 		.word	1073876992
+ 549 02cc 00700040 		.word	1073770496
+ 550              	.L38:
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 551              		.loc 1 416 7 view .LVU178
+ 552 02d0 D368     		ldr	r3, [r2, #12]
+ 553 02d2 43F48013 		orr	r3, r3, #1048576
+ 554 02d6 D360     		str	r3, [r2, #12]
+ 555 02d8 CEE7     		b	.L25
+ 556              	.L39:
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 557              		.loc 1 432 7 view .LVU179
+ 558 02da D368     		ldr	r3, [r2, #12]
+ 559 02dc 43F48033 		orr	r3, r3, #65536
+ 560 02e0 D360     		str	r3, [r2, #12]
+ 561 02e2 DAE7     		b	.L26
+ 562              		.cfi_endproc
+ 563              	.LFE329:
+ 565              		.section	.text.HAL_RCCEx_GetPeriphCLKConfig,"ax",%progbits
+ 566              		.align	1
+ 567              		.global	HAL_RCCEx_GetPeriphCLKConfig
+ 568              		.syntax unified
+ 569              		.thumb
+ 570              		.thumb_func
+ 572              	HAL_RCCEx_GetPeriphCLKConfig:
+ 573              	.LVL26:
+ 574              	.LFB330:
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *         returns the configuration information for the Extended Peripherals
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *         clocks(USART1, USART2, USART3, UART4, UART5, LPUART1, I2C1, I2C2, I2C3, I2C4,
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *         LPTIM1, SAI1, I2Sx, FDCANx, USB, RNG, ADCx, RTC, QSPI).
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval None
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 575              		.loc 1 486 1 view -0
+ 576              		.cfi_startproc
+ARM GAS  /tmp/ccXzHHIc.s 			page 20
+
+
+ 577              		@ args = 0, pretend = 0, frame = 0
+ 578              		@ frame_needed = 0, uses_anonymous_args = 0
+ 579              		@ link register save eliminated.
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Set all possible values for the extended clock type parameter------------*/
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(STM32G474xx) || defined(STM32G484xx)
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCL
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_UART5   | \
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCL
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_I2C4    | \
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCL
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCL
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_QSPI    | \
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_RTC;
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #elif defined(STM32G491xx) || defined(STM32G4A1xx)
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCL
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_UART5   | \
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCL
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCL
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCL
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_QSPI    | \
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_RTC;
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #elif defined(STM32G473xx) || defined(STM32G483xx)
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCL
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_UART5   | \
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCL
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_I2C4    | \
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCL
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCL
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_QSPI    | \
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_RTC;
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #elif defined(STM32G471xx)
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCL
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_UART5   | \
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCL
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_I2C4    | \
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCL
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCL
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_RTC;
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #elif defined(STM32G431xx) || defined(STM32G441xx)
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCL
+ 580              		.loc 1 531 3 view .LVU181
+ 581              		.loc 1 531 39 is_stmt 0 view .LVU182
+ 582 0000 294B     		ldr	r3, .L43
+ 583 0002 0360     		str	r3, [r0]
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCL
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCL
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCL
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_RTC;
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #elif defined(STM32GBK1CB)
+ARM GAS  /tmp/ccXzHHIc.s 			page 21
+
+
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCL
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCL
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCL
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCL
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_RTC;
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* STM32G431xx */
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the USART1 clock source ---------------------------------------------*/
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->Usart1ClockSelection  = __HAL_RCC_GET_USART1_SOURCE();
+ 584              		.loc 1 548 3 is_stmt 1 view .LVU183
+ 585              		.loc 1 548 42 is_stmt 0 view .LVU184
+ 586 0004 294B     		ldr	r3, .L43+4
+ 587 0006 D3F88820 		ldr	r2, [r3, #136]
+ 588 000a 02F00302 		and	r2, r2, #3
+ 589              		.loc 1 548 40 view .LVU185
+ 590 000e 4260     		str	r2, [r0, #4]
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the USART2 clock source ---------------------------------------------*/
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->Usart2ClockSelection  = __HAL_RCC_GET_USART2_SOURCE();
+ 591              		.loc 1 550 3 is_stmt 1 view .LVU186
+ 592              		.loc 1 550 42 is_stmt 0 view .LVU187
+ 593 0010 D3F88820 		ldr	r2, [r3, #136]
+ 594 0014 02F00C02 		and	r2, r2, #12
+ 595              		.loc 1 550 40 view .LVU188
+ 596 0018 8260     		str	r2, [r0, #8]
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the USART3 clock source ---------------------------------------------*/
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->Usart3ClockSelection  = __HAL_RCC_GET_USART3_SOURCE();
+ 597              		.loc 1 552 3 is_stmt 1 view .LVU189
+ 598              		.loc 1 552 42 is_stmt 0 view .LVU190
+ 599 001a D3F88820 		ldr	r2, [r3, #136]
+ 600 001e 02F03002 		and	r2, r2, #48
+ 601              		.loc 1 552 40 view .LVU191
+ 602 0022 C260     		str	r2, [r0, #12]
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(UART4)
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the UART4 clock source ----------------------------------------------*/
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->Uart4ClockSelection   = __HAL_RCC_GET_UART4_SOURCE();
+ 603              		.loc 1 556 3 is_stmt 1 view .LVU192
+ 604              		.loc 1 556 42 is_stmt 0 view .LVU193
+ 605 0024 D3F88820 		ldr	r2, [r3, #136]
+ 606 0028 02F0C002 		and	r2, r2, #192
+ 607              		.loc 1 556 40 view .LVU194
+ 608 002c 0261     		str	r2, [r0, #16]
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* UART4 */
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(UART5)
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the UART5 clock source ----------------------------------------------*/
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->Uart5ClockSelection   = __HAL_RCC_GET_UART5_SOURCE();
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* UART5 */
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the LPUART1 clock source --------------------------------------------*/
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
+ 609              		.loc 1 565 3 is_stmt 1 view .LVU195
+ 610              		.loc 1 565 42 is_stmt 0 view .LVU196
+ 611 002e D3F88820 		ldr	r2, [r3, #136]
+ARM GAS  /tmp/ccXzHHIc.s 			page 22
+
+
+ 612 0032 02F44062 		and	r2, r2, #3072
+ 613              		.loc 1 565 40 view .LVU197
+ 614 0036 4261     		str	r2, [r0, #20]
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the I2C1 clock source -----------------------------------------------*/
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->I2c1ClockSelection    = __HAL_RCC_GET_I2C1_SOURCE();
+ 615              		.loc 1 568 3 is_stmt 1 view .LVU198
+ 616              		.loc 1 568 42 is_stmt 0 view .LVU199
+ 617 0038 D3F88820 		ldr	r2, [r3, #136]
+ 618 003c 02F44052 		and	r2, r2, #12288
+ 619              		.loc 1 568 40 view .LVU200
+ 620 0040 8261     		str	r2, [r0, #24]
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the I2C2 clock source ----------------------------------------------*/
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->I2c2ClockSelection    = __HAL_RCC_GET_I2C2_SOURCE();
+ 621              		.loc 1 571 3 is_stmt 1 view .LVU201
+ 622              		.loc 1 571 42 is_stmt 0 view .LVU202
+ 623 0042 D3F88820 		ldr	r2, [r3, #136]
+ 624 0046 02F44042 		and	r2, r2, #49152
+ 625              		.loc 1 571 40 view .LVU203
+ 626 004a C261     		str	r2, [r0, #28]
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the I2C3 clock source -----------------------------------------------*/
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->I2c3ClockSelection    = __HAL_RCC_GET_I2C3_SOURCE();
+ 627              		.loc 1 574 3 is_stmt 1 view .LVU204
+ 628              		.loc 1 574 42 is_stmt 0 view .LVU205
+ 629 004c D3F88820 		ldr	r2, [r3, #136]
+ 630 0050 02F44032 		and	r2, r2, #196608
+ 631              		.loc 1 574 40 view .LVU206
+ 632 0054 0262     		str	r2, [r0, #32]
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(I2C4)
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the I2C4 clock source -----------------------------------------------*/
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->I2c4ClockSelection    = __HAL_RCC_GET_I2C4_SOURCE();
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* I2C4 */
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the LPTIM1 clock source ---------------------------------------------*/
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->Lptim1ClockSelection  = __HAL_RCC_GET_LPTIM1_SOURCE();
+ 633              		.loc 1 582 3 is_stmt 1 view .LVU207
+ 634              		.loc 1 582 42 is_stmt 0 view .LVU208
+ 635 0056 D3F88820 		ldr	r2, [r3, #136]
+ 636 005a 02F44022 		and	r2, r2, #786432
+ 637              		.loc 1 582 40 view .LVU209
+ 638 005e 4262     		str	r2, [r0, #36]
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the SAI1 clock source -----------------------------------------------*/
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->Sai1ClockSelection    = __HAL_RCC_GET_SAI1_SOURCE();
+ 639              		.loc 1 585 3 is_stmt 1 view .LVU210
+ 640              		.loc 1 585 42 is_stmt 0 view .LVU211
+ 641 0060 D3F88820 		ldr	r2, [r3, #136]
+ 642 0064 02F44012 		and	r2, r2, #3145728
+ 643              		.loc 1 585 40 view .LVU212
+ 644 0068 8262     		str	r2, [r0, #40]
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the I2S clock source -----------------------------------------------*/
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->I2sClockSelection    = __HAL_RCC_GET_I2S_SOURCE();
+ 645              		.loc 1 588 3 is_stmt 1 view .LVU213
+ARM GAS  /tmp/ccXzHHIc.s 			page 23
+
+
+ 646              		.loc 1 588 41 is_stmt 0 view .LVU214
+ 647 006a D3F88820 		ldr	r2, [r3, #136]
+ 648 006e 02F44002 		and	r2, r2, #12582912
+ 649              		.loc 1 588 39 view .LVU215
+ 650 0072 C262     		str	r2, [r0, #44]
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(FDCAN1)
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the FDCAN clock source -----------------------------------------------*/
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->FdcanClockSelection    = __HAL_RCC_GET_FDCAN_SOURCE();
+ 651              		.loc 1 592 3 is_stmt 1 view .LVU216
+ 652              		.loc 1 592 43 is_stmt 0 view .LVU217
+ 653 0074 D3F88820 		ldr	r2, [r3, #136]
+ 654 0078 02F04072 		and	r2, r2, #50331648
+ 655              		.loc 1 592 41 view .LVU218
+ 656 007c 0263     		str	r2, [r0, #48]
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* FDCAN1 */
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(USB)
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the USB clock source ------------------------------------------------*/
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->UsbClockSelection   = __HAL_RCC_GET_USB_SOURCE();
+ 657              		.loc 1 597 3 is_stmt 1 view .LVU219
+ 658              		.loc 1 597 40 is_stmt 0 view .LVU220
+ 659 007e D3F88820 		ldr	r2, [r3, #136]
+ 660 0082 02F04062 		and	r2, r2, #201326592
+ 661              		.loc 1 597 38 view .LVU221
+ 662 0086 4263     		str	r2, [r0, #52]
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* USB */
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the RNG clock source ------------------------------------------------*/
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->RngClockSelection   = __HAL_RCC_GET_RNG_SOURCE();
+ 663              		.loc 1 601 3 is_stmt 1 view .LVU222
+ 664              		.loc 1 601 40 is_stmt 0 view .LVU223
+ 665 0088 D3F88820 		ldr	r2, [r3, #136]
+ 666 008c 02F04062 		and	r2, r2, #201326592
+ 667              		.loc 1 601 38 view .LVU224
+ 668 0090 8263     		str	r2, [r0, #56]
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the ADC12 clock source -----------------------------------------------*/
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->Adc12ClockSelection     = __HAL_RCC_GET_ADC12_SOURCE();
+ 669              		.loc 1 604 3 is_stmt 1 view .LVU225
+ 670              		.loc 1 604 44 is_stmt 0 view .LVU226
+ 671 0092 D3F88820 		ldr	r2, [r3, #136]
+ 672 0096 02F04052 		and	r2, r2, #805306368
+ 673              		.loc 1 604 42 view .LVU227
+ 674 009a C263     		str	r2, [r0, #60]
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(ADC345_COMMON)
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the ADC345 clock source ----------------------------------------------*/
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->Adc345ClockSelection     = __HAL_RCC_GET_ADC345_SOURCE();
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* ADC345_COMMON */
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(QUADSPI)
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the QuadSPIclock source --------------------------------------------*/
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* QUADSPI */
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the RTC clock source ------------------------------------------------*/
+ARM GAS  /tmp/ccXzHHIc.s 			page 24
+
+
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   PeriphClkInit->RTCClockSelection     = __HAL_RCC_GET_RTC_SOURCE();
+ 675              		.loc 1 617 3 is_stmt 1 view .LVU228
+ 676              		.loc 1 617 42 is_stmt 0 view .LVU229
+ 677 009c D3F89030 		ldr	r3, [r3, #144]
+ 678 00a0 03F44073 		and	r3, r3, #768
+ 679              		.loc 1 617 40 view .LVU230
+ 680 00a4 0364     		str	r3, [r0, #64]
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 681              		.loc 1 619 1 view .LVU231
+ 682 00a6 7047     		bx	lr
+ 683              	.L44:
+ 684              		.align	2
+ 685              	.L43:
+ 686 00a8 EFFF0800 		.word	589807
+ 687 00ac 00100240 		.word	1073876992
+ 688              		.cfi_endproc
+ 689              	.LFE330:
+ 691              		.section	.text.HAL_RCCEx_GetPeriphCLKFreq,"ax",%progbits
+ 692              		.align	1
+ 693              		.global	HAL_RCCEx_GetPeriphCLKFreq
+ 694              		.syntax unified
+ 695              		.thumb
+ 696              		.thumb_func
+ 698              	HAL_RCCEx_GetPeriphCLKFreq:
+ 699              	.LVL27:
+ 700              	.LFB331:
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  Return the peripheral clock frequency for peripherals with clock source from PLL
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @note   Return 0 if peripheral clock identifier not managed by this API
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @param  PeriphClk  Peripheral clock identifier
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *         This parameter can be one of the following values:
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_I2S  SPI peripheral clock
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_FDCAN  FDCAN peripheral clock (only for devices with FDCAN)
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_ADC12  ADC1 and ADC2 peripheral clock
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_ADC345  ADC3, ADC4 and ADC5 peripheral clock (only for devic
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_QSPI  QSPI peripheral clock (only for devices with QSPI)
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval Frequency in Hz
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ARM GAS  /tmp/ccXzHHIc.s 			page 25
+
+
+ 701              		.loc 1 649 1 is_stmt 1 view -0
+ 702              		.cfi_startproc
+ 703              		@ args = 0, pretend = 0, frame = 0
+ 704              		@ frame_needed = 0, uses_anonymous_args = 0
+ 705              		.loc 1 649 1 is_stmt 0 view .LVU233
+ 706 0000 08B5     		push	{r3, lr}
+ 707              	.LCFI4:
+ 708              		.cfi_def_cfa_offset 8
+ 709              		.cfi_offset 3, -8
+ 710              		.cfi_offset 14, -4
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t frequency = 0U;
+ 711              		.loc 1 650 3 is_stmt 1 view .LVU234
+ 712              	.LVL28:
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 713              		.loc 1 651 3 view .LVU235
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t pllvco, plln, pllp;
+ 714              		.loc 1 652 3 view .LVU236
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Check the parameters */
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+ 715              		.loc 1 655 3 view .LVU237
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(PeriphClk == RCC_PERIPHCLK_RTC)
+ 716              		.loc 1 657 3 view .LVU238
+ 717              		.loc 1 657 5 is_stmt 0 view .LVU239
+ 718 0002 B0F5002F 		cmp	r0, #524288
+ 719 0006 43D0     		beq	.L137
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Get the current RTC source */
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     srcclk = __HAL_RCC_GET_RTC_SOURCE();
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check if LSE is ready and if RTC clock selection is LSE */
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       frequency = LSE_VALUE;
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check if LSI is ready and if RTC clock selection is LSI */
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       frequency = LSI_VALUE;
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check if HSE is ready  and if RTC clock selection is HSI_DIV32*/
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32))
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       frequency = HSE_VALUE / 32U;
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Clock not enabled for RTC*/
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     else
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* nothing to do: frequency already initialized to 0 */
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   else
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Other external peripheral clock source than RTC */
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Compute PLL clock input */
+ARM GAS  /tmp/ccXzHHIc.s 			page 26
+
+
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)   /* HSI ? */
+ 720              		.loc 1 688 5 is_stmt 1 view .LVU240
+ 721              		.loc 1 688 8 is_stmt 0 view .LVU241
+ 722 0008 9C4B     		ldr	r3, .L173
+ 723 000a DB68     		ldr	r3, [r3, #12]
+ 724 000c 03F00303 		and	r3, r3, #3
+ 725              		.loc 1 688 7 view .LVU242
+ 726 0010 022B     		cmp	r3, #2
+ 727 0012 61D0     		beq	.L138
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         pllvco = HSI_VALUE;
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         pllvco = 0U;
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)   /* HSE ? */
+ 728              		.loc 1 699 10 is_stmt 1 view .LVU243
+ 729              		.loc 1 699 13 is_stmt 0 view .LVU244
+ 730 0014 994B     		ldr	r3, .L173
+ 731 0016 DB68     		ldr	r3, [r3, #12]
+ 732 0018 03F00303 		and	r3, r3, #3
+ 733              		.loc 1 699 12 view .LVU245
+ 734 001c 032B     		cmp	r3, #3
+ 735 001e 62D0     		beq	.L139
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         pllvco = HSE_VALUE;
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         pllvco = 0U;
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     else /* No source */
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       pllvco = 0U;
+ 736              		.loc 1 712 14 view .LVU246
+ 737 0020 0022     		movs	r2, #0
+ 738              	.L51:
+ 739              	.LVL29:
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* f(PLL Source) / PLLM */
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
+ 740              		.loc 1 716 5 is_stmt 1 view .LVU247
+ 741              		.loc 1 716 26 is_stmt 0 view .LVU248
+ 742 0022 964B     		ldr	r3, .L173
+ 743 0024 DB68     		ldr	r3, [r3, #12]
+ 744              		.loc 1 716 67 view .LVU249
+ 745 0026 C3F30313 		ubfx	r3, r3, #4, #4
+ 746              		.loc 1 716 92 view .LVU250
+ 747 002a 0133     		adds	r3, r3, #1
+ARM GAS  /tmp/ccXzHHIc.s 			page 27
+
+
+ 748              		.loc 1 716 12 view .LVU251
+ 749 002c B2FBF3F2 		udiv	r2, r2, r3
+ 750              	.LVL30:
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     switch(PeriphClk)
+ 751              		.loc 1 718 5 is_stmt 1 view .LVU252
+ 752 0030 B0F5807F 		cmp	r0, #256
+ 753 0034 00F0D481 		beq	.L52
+ 754 0038 7AD8     		bhi	.L53
+ 755 003a 2028     		cmp	r0, #32
+ 756 003c 5AD8     		bhi	.L54
+ 757 003e 0028     		cmp	r0, #0
+ 758 0040 00F0BB82 		beq	.L108
+ 759 0044 0138     		subs	r0, r0, #1
+ 760              	.LVL31:
+ 761              		.loc 1 718 5 is_stmt 0 view .LVU253
+ 762 0046 1F28     		cmp	r0, #31
+ 763 0048 00F2B982 		bhi	.L109
+ 764 004c DFE810F0 		tbh	[pc, r0, lsl #1]
+ 765              	.L56:
+ 766 0050 F300     		.2byte	(.L60-.L56)/2
+ 767 0052 1C01     		.2byte	(.L59-.L56)/2
+ 768 0054 B702     		.2byte	(.L109-.L56)/2
+ 769 0056 3E01     		.2byte	(.L58-.L56)/2
+ 770 0058 B702     		.2byte	(.L109-.L56)/2
+ 771 005a B702     		.2byte	(.L109-.L56)/2
+ 772 005c B702     		.2byte	(.L109-.L56)/2
+ 773 005e 6001     		.2byte	(.L57-.L56)/2
+ 774 0060 B702     		.2byte	(.L109-.L56)/2
+ 775 0062 B702     		.2byte	(.L109-.L56)/2
+ 776 0064 B702     		.2byte	(.L109-.L56)/2
+ 777 0066 B702     		.2byte	(.L109-.L56)/2
+ 778 0068 B702     		.2byte	(.L109-.L56)/2
+ 779 006a B702     		.2byte	(.L109-.L56)/2
+ 780 006c B702     		.2byte	(.L109-.L56)/2
+ 781 006e B702     		.2byte	(.L109-.L56)/2
+ 782 0070 B702     		.2byte	(.L109-.L56)/2
+ 783 0072 B702     		.2byte	(.L109-.L56)/2
+ 784 0074 B702     		.2byte	(.L109-.L56)/2
+ 785 0076 B702     		.2byte	(.L109-.L56)/2
+ 786 0078 B702     		.2byte	(.L109-.L56)/2
+ 787 007a B702     		.2byte	(.L109-.L56)/2
+ 788 007c B702     		.2byte	(.L109-.L56)/2
+ 789 007e B702     		.2byte	(.L109-.L56)/2
+ 790 0080 B702     		.2byte	(.L109-.L56)/2
+ 791 0082 B702     		.2byte	(.L109-.L56)/2
+ 792 0084 B702     		.2byte	(.L109-.L56)/2
+ 793 0086 B702     		.2byte	(.L109-.L56)/2
+ 794 0088 B702     		.2byte	(.L109-.L56)/2
+ 795 008a B702     		.2byte	(.L109-.L56)/2
+ 796 008c B702     		.2byte	(.L109-.L56)/2
+ 797 008e 8201     		.2byte	(.L55-.L56)/2
+ 798              	.LVL32:
+ 799              		.p2align 1
+ 800              	.L137:
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 801              		.loc 1 660 5 is_stmt 1 view .LVU254
+ARM GAS  /tmp/ccXzHHIc.s 			page 28
+
+
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 802              		.loc 1 660 14 is_stmt 0 view .LVU255
+ 803 0090 7A4A     		ldr	r2, .L173
+ 804 0092 D2F89030 		ldr	r3, [r2, #144]
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 805              		.loc 1 660 12 view .LVU256
+ 806 0096 03F44073 		and	r3, r3, #768
+ 807              	.LVL33:
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 808              		.loc 1 663 5 is_stmt 1 view .LVU257
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 809              		.loc 1 663 10 is_stmt 0 view .LVU258
+ 810 009a D2F89020 		ldr	r2, [r2, #144]
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 811              		.loc 1 663 8 view .LVU259
+ 812 009e 12F0020F 		tst	r2, #2
+ 813 00a2 03D0     		beq	.L47
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 814              		.loc 1 663 54 discriminator 1 view .LVU260
+ 815 00a4 B3F5807F 		cmp	r3, #256
+ 816 00a8 00F07F82 		beq	.L104
+ 817              	.L47:
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 818              		.loc 1 668 10 is_stmt 1 view .LVU261
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 819              		.loc 1 668 15 is_stmt 0 view .LVU262
+ 820 00ac 734A     		ldr	r2, .L173
+ 821 00ae D2F89420 		ldr	r2, [r2, #148]
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 822              		.loc 1 668 13 view .LVU263
+ 823 00b2 12F0020F 		tst	r2, #2
+ 824 00b6 03D0     		beq	.L49
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 825              		.loc 1 668 57 discriminator 1 view .LVU264
+ 826 00b8 B3F5007F 		cmp	r3, #512
+ 827 00bc 00F07882 		beq	.L105
+ 828              	.L49:
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 829              		.loc 1 673 10 is_stmt 1 view .LVU265
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 830              		.loc 1 673 15 is_stmt 0 view .LVU266
+ 831 00c0 6E4A     		ldr	r2, .L173
+ 832 00c2 1068     		ldr	r0, [r2]
+ 833              	.LVL34:
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 834              		.loc 1 673 13 view .LVU267
+ 835 00c4 10F40030 		ands	r0, r0, #131072
+ 836 00c8 00F07A82 		beq	.L45
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 837              		.loc 1 673 55 discriminator 1 view .LVU268
+ 838 00cc B3F5407F 		cmp	r3, #768
+ 839 00d0 00F07182 		beq	.L106
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 840              		.loc 1 650 12 view .LVU269
+ 841 00d4 0020     		movs	r0, #0
+ 842 00d6 73E2     		b	.L45
+ 843              	.LVL35:
+ARM GAS  /tmp/ccXzHHIc.s 			page 29
+
+
+ 844              	.L138:
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 845              		.loc 1 690 7 is_stmt 1 view .LVU270
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 846              		.loc 1 690 10 is_stmt 0 view .LVU271
+ 847 00d8 684B     		ldr	r3, .L173
+ 848 00da 1A68     		ldr	r2, [r3]
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 849              		.loc 1 690 9 view .LVU272
+ 850 00dc 12F48062 		ands	r2, r2, #1024
+ 851 00e0 9FD0     		beq	.L51
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 852              		.loc 1 692 16 view .LVU273
+ 853 00e2 674A     		ldr	r2, .L173+4
+ 854 00e4 9DE7     		b	.L51
+ 855              	.L139:
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 856              		.loc 1 701 7 is_stmt 1 view .LVU274
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 857              		.loc 1 701 10 is_stmt 0 view .LVU275
+ 858 00e6 654B     		ldr	r3, .L173
+ 859 00e8 1A68     		ldr	r2, [r3]
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 860              		.loc 1 701 9 view .LVU276
+ 861 00ea 12F40032 		ands	r2, r2, #131072
+ 862 00ee 98D0     		beq	.L51
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 863              		.loc 1 703 16 view .LVU277
+ 864 00f0 644A     		ldr	r2, .L173+8
+ 865 00f2 96E7     		b	.L51
+ 866              	.LVL36:
+ 867              	.L54:
+ 868              		.loc 1 718 5 view .LVU278
+ 869 00f4 4028     		cmp	r0, #64
+ 870 00f6 00F05281 		beq	.L61
+ 871 00fa 8028     		cmp	r0, #128
+ 872 00fc 16D1     		bne	.L140
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_USART1:
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current USART1 source */
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_USART1_SOURCE();
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_USART1CLKSOURCE_PCLK2)
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetPCLK2Freq();
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK)
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI) )
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ARM GAS  /tmp/ccXzHHIc.s 			page 30
+
+
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = LSE_VALUE;
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for USART1 */
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_USART2:
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current USART2 source */
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_USART2_SOURCE();
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_USART2CLKSOURCE_PCLK1)
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetPCLK1Freq();
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK)
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))  && (srcclk == RCC_USART2CLKSOURCE_LSE))
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = LSE_VALUE;
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for USART2 */
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_USART3:
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current USART3 source */
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_USART3_SOURCE();
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_USART3CLKSOURCE_PCLK1)
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetPCLK1Freq();
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK)
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = LSE_VALUE;
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for USART3 */
+ARM GAS  /tmp/ccXzHHIc.s 			page 31
+
+
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(UART4)
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_UART4:
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current UART4 source */
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_UART4_SOURCE();
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_UART4CLKSOURCE_PCLK1)
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetPCLK1Freq();
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK)
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = LSE_VALUE;
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for UART4 */
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* UART4 */
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(UART5)
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_UART5:
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current UART5 source */
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_UART5_SOURCE();
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_UART5CLKSOURCE_PCLK1)
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetPCLK1Freq();
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK)
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = LSE_VALUE;
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for UART5 */
+ARM GAS  /tmp/ccXzHHIc.s 			page 32
+
+
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* UART5 */
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_LPUART1:
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current LPUART1 source */
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetPCLK1Freq();
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = LSE_VALUE;
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for LPUART1 */
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_I2C1:
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current I2C1 source */
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_I2C1_SOURCE();
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_I2C1CLKSOURCE_PCLK1)
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetPCLK1Freq();
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for I2C1 */
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ARM GAS  /tmp/ccXzHHIc.s 			page 33
+
+
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_I2C2:
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current I2C2 source */
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_I2C2_SOURCE();
+ 873              		.loc 1 912 7 is_stmt 1 view .LVU279
+ 874              		.loc 1 912 16 is_stmt 0 view .LVU280
+ 875 00fe 5F4B     		ldr	r3, .L173
+ 876 0100 D3F88830 		ldr	r3, [r3, #136]
+ 877              	.LVL37:
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_I2C2CLKSOURCE_PCLK1)
+ 878              		.loc 1 914 7 is_stmt 1 view .LVU281
+ 879              		.loc 1 914 9 is_stmt 0 view .LVU282
+ 880 0104 13F44043 		ands	r3, r3, #49152
+ 881              	.LVL38:
+ 882              		.loc 1 914 9 view .LVU283
+ 883 0108 00F06481 		beq	.L141
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetPCLK1Freq();
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
+ 884              		.loc 1 918 12 is_stmt 1 view .LVU284
+ 885              		.loc 1 918 14 is_stmt 0 view .LVU285
+ 886 010c B3F5804F 		cmp	r3, #16384
+ 887 0110 00F06381 		beq	.L142
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
+ 888              		.loc 1 922 12 is_stmt 1 view .LVU286
+ 889              		.loc 1 922 16 is_stmt 0 view .LVU287
+ 890 0114 594A     		ldr	r2, .L173
+ 891              	.LVL39:
+ 892              		.loc 1 922 16 view .LVU288
+ 893 0116 1068     		ldr	r0, [r2]
+ 894              	.LVL40:
+ 895              		.loc 1 922 14 view .LVU289
+ 896 0118 10F48060 		ands	r0, r0, #1024
+ 897 011c 00F05082 		beq	.L45
+ 898              		.loc 1 922 56 discriminator 1 view .LVU290
+ 899 0120 B3F5004F 		cmp	r3, #32768
+ 900 0124 00F06882 		beq	.L121
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 901              		.loc 1 650 12 view .LVU291
+ 902 0128 0020     		movs	r0, #0
+ 903 012a 49E2     		b	.L45
+ 904              	.LVL41:
+ 905              	.L140:
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 906              		.loc 1 718 5 view .LVU292
+ 907 012c 0020     		movs	r0, #0
+ 908              	.LVL42:
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 909              		.loc 1 718 5 view .LVU293
+ 910 012e 47E2     		b	.L45
+ 911              	.LVL43:
+ 912              	.L53:
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ARM GAS  /tmp/ccXzHHIc.s 			page 34
+
+
+ 913              		.loc 1 718 5 view .LVU294
+ 914 0130 B0F5805F 		cmp	r0, #4096
+ 915 0134 00F0BD81 		beq	.L63
+ 916 0138 15D9     		bls	.L143
+ 917 013a B0F5804F 		cmp	r0, #16384
+ 918 013e 00F0F181 		beq	.L68
+ 919 0142 B0F5004F 		cmp	r0, #32768
+ 920 0146 5CD1     		bne	.L144
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for I2C2 */
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_I2C3:
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current I2C3 source */
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_I2C3_SOURCE();
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_I2C3CLKSOURCE_PCLK1)
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetPCLK1Freq();
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_HSI))
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for I2C3 */
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(I2C4)
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_I2C4:
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current I2C4 source */
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_I2C4_SOURCE();
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_I2C4CLKSOURCE_PCLK1)
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetPCLK1Freq();
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK)
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ARM GAS  /tmp/ccXzHHIc.s 			page 35
+
+
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for I2C4 */
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* I2C4 */
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_LPTIM1:
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current LPTIM1 source */
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1)
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetPCLK1Freq();
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI))
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = LSI_VALUE;
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI))
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE))
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = LSE_VALUE;
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for LPTIM1 */
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_SAI1:
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current SAI1 source */
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_SAI1_SOURCE();
+1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_SAI1CLKSOURCE_SYSCLK)
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_SAI1CLKSOURCE_PLL)
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U)
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_SAI1CLKSOURCE_EXT)
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ARM GAS  /tmp/ccXzHHIc.s 			page 36
+
+
+1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* External clock used.*/
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = EXTERNAL_CLOCK_VALUE;
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SAI1CLKSOURCE_HSI))
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for SAI1 */
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_I2S:
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current I2Sx source */
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_I2S_SOURCE();
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_I2SCLKSOURCE_SYSCLK)
+1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_I2SCLKSOURCE_PLL)
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U)
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
+1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_I2SCLKSOURCE_EXT)
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* External clock used.*/
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = EXTERNAL_CLOCK_VALUE;
+1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }      
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2SCLKSOURCE_HSI))
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for I2S */
+1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(FDCAN1)
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_FDCAN:
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current FDCANx source */
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_FDCANCLKSOURCE_PCLK1)
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetPCLK1Freq();
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_FDCANCLKSOURCE_HSE)
+ARM GAS  /tmp/ccXzHHIc.s 			page 37
+
+
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSE_VALUE;
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_FDCANCLKSOURCE_PLL)
+1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U)
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for FDCAN */
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* FDCAN1 */
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(USB)
+1107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_USB:
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current USB source */
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_USB_SOURCE();
+1111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_USBCLKSOURCE_PLL)  /* PLL ? */
+1113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if((HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI48_VALUE;
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else /* No clock source */
+1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* USB */
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_RNG:
+1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current RNG source */
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_RNG_SOURCE();
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_RNGCLKSOURCE_PLL)  /* PLL ? */
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if( (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI4
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI48_VALUE;
+ARM GAS  /tmp/ccXzHHIc.s 			page 38
+
+
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else /* No clock source */
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_ADC12:
+1151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current ADC12 source */
+1152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_ADC12_SOURCE();
+ 921              		.loc 1 1152 7 is_stmt 1 view .LVU295
+ 922              		.loc 1 1152 16 is_stmt 0 view .LVU296
+ 923 0148 4C4B     		ldr	r3, .L173
+ 924 014a D3F88830 		ldr	r3, [r3, #136]
+ 925              		.loc 1 1152 14 view .LVU297
+ 926 014e 03F04053 		and	r3, r3, #805306368
+ 927              	.LVL44:
+1153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_ADC12CLKSOURCE_PLL)
+ 928              		.loc 1 1154 7 is_stmt 1 view .LVU298
+ 929              		.loc 1 1154 9 is_stmt 0 view .LVU299
+ 930 0152 B3F1805F 		cmp	r3, #268435456
+ 931 0156 00F00A82 		beq	.L145
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U)
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           /* f(PLLP) = f(VCO input) * PLLN / PLLP */
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           if(pllp == 0U)
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           {
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             {
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               pllp = 17U;
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             }
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             else
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             {
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               pllp = 7U;
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             }
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           }
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / pllp;
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_ADC12CLKSOURCE_SYSCLK)
+ 932              		.loc 1 1175 12 is_stmt 1 view .LVU300
+ 933              		.loc 1 1175 14 is_stmt 0 view .LVU301
+ 934 015a B3F1005F 		cmp	r3, #536870912
+ 935 015e 00F02182 		beq	.L146
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 936              		.loc 1 650 12 view .LVU302
+ 937 0162 0020     		movs	r0, #0
+ 938              	.LVL45:
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for ADC12 */
+1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+ARM GAS  /tmp/ccXzHHIc.s 			page 39
+
+
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(ADC345_COMMON)
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_ADC345:
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current ADC345 source */
+1189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_ADC345_SOURCE();
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_ADC345CLKSOURCE_PLL)
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U)
+1194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           /* f(PLLP) = f(VCO input) * PLLN / PLLP */
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
+1198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           if(pllp == 0U)
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           {
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             {
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               pllp = 17U;
+1203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             }
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             else
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             {
+1206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               pllp = 7U;
+1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             }
+1208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           }
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / pllp;
+1210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_ADC345CLKSOURCE_SYSCLK)
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clock not enabled for ADC345 */
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* ADC345_COMMON */
+1223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(QUADSPI)
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     case RCC_PERIPHCLK_QSPI:
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Get the current QSPI source */
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       srcclk = __HAL_RCC_GET_QSPI_SOURCE();
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       
+1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(srcclk == RCC_QSPICLKSOURCE_PLL)  /* PLL ? */
+1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_QSPICLKSOURCE_HSI)
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ARM GAS  /tmp/ccXzHHIc.s 			page 40
+
+
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HSI_VALUE;
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }      
+1240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else if(srcclk == RCC_QSPICLKSOURCE_SYSCLK)
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = HAL_RCC_GetSysClockFreq();
+1243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       else /* No clock source */
+1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         /* nothing to do: frequency already initialized to 0 */
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* QUADSPI */
+1251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     default:
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       break;
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   return(frequency);
+ 939              		.loc 1 1257 3 is_stmt 1 view .LVU303
+ 940              		.loc 1 1257 9 is_stmt 0 view .LVU304
+ 941 0164 2CE2     		b	.L45
+ 942              	.LVL46:
+ 943              	.L143:
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 944              		.loc 1 718 5 view .LVU305
+ 945 0166 B0F5806F 		cmp	r0, #1024
+ 946 016a 00F05781 		beq	.L65
+ 947 016e B0F5006F 		cmp	r0, #2048
+ 948 0172 1AD1     		bne	.L147
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 949              		.loc 1 1045 7 is_stmt 1 view .LVU306
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 950              		.loc 1 1045 16 is_stmt 0 view .LVU307
+ 951 0174 414B     		ldr	r3, .L173
+ 952 0176 D3F88830 		ldr	r3, [r3, #136]
+ 953              	.LVL47:
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 954              		.loc 1 1047 7 is_stmt 1 view .LVU308
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 955              		.loc 1 1047 9 is_stmt 0 view .LVU309
+ 956 017a 13F44003 		ands	r3, r3, #12582912
+ 957              	.LVL48:
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 958              		.loc 1 1047 9 view .LVU310
+ 959 017e 00F07F81 		beq	.L148
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 960              		.loc 1 1051 12 is_stmt 1 view .LVU311
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 961              		.loc 1 1051 14 is_stmt 0 view .LVU312
+ 962 0182 B3F5800F 		cmp	r3, #4194304
+ 963 0186 00F07E81 		beq	.L149
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 964              		.loc 1 1060 12 is_stmt 1 view .LVU313
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 965              		.loc 1 1060 14 is_stmt 0 view .LVU314
+ARM GAS  /tmp/ccXzHHIc.s 			page 41
+
+
+ 966 018a B3F5000F 		cmp	r3, #8388608
+ 967 018e 00F04382 		beq	.L128
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 968              		.loc 1 1065 12 is_stmt 1 view .LVU315
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 969              		.loc 1 1065 16 is_stmt 0 view .LVU316
+ 970 0192 3A4A     		ldr	r2, .L173
+ 971              	.LVL49:
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 972              		.loc 1 1065 16 view .LVU317
+ 973 0194 1068     		ldr	r0, [r2]
+ 974              	.LVL50:
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 975              		.loc 1 1065 14 view .LVU318
+ 976 0196 10F48060 		ands	r0, r0, #1024
+ 977 019a 00F01182 		beq	.L45
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 978              		.loc 1 1065 56 discriminator 1 view .LVU319
+ 979 019e B3F5400F 		cmp	r3, #12582912
+ 980 01a2 00F03B82 		beq	.L129
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 981              		.loc 1 650 12 view .LVU320
+ 982 01a6 0020     		movs	r0, #0
+ 983 01a8 0AE2     		b	.L45
+ 984              	.LVL51:
+ 985              	.L147:
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 986              		.loc 1 718 5 view .LVU321
+ 987 01aa B0F5007F 		cmp	r0, #512
+ 988 01ae 26D1     		bne	.L150
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 989              		.loc 1 985 7 is_stmt 1 view .LVU322
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 990              		.loc 1 985 16 is_stmt 0 view .LVU323
+ 991 01b0 324B     		ldr	r3, .L173
+ 992 01b2 D3F88830 		ldr	r3, [r3, #136]
+ 993              	.LVL52:
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 994              		.loc 1 987 7 is_stmt 1 view .LVU324
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 995              		.loc 1 987 9 is_stmt 0 view .LVU325
+ 996 01b6 13F44023 		ands	r3, r3, #786432
+ 997              	.LVL53:
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 998              		.loc 1 987 9 view .LVU326
+ 999 01ba 00F02C81 		beq	.L151
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1000              		.loc 1 991 12 is_stmt 1 view .LVU327
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1001              		.loc 1 991 16 is_stmt 0 view .LVU328
+ 1002 01be 2F4A     		ldr	r2, .L173
+ 1003              	.LVL54:
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1004              		.loc 1 991 16 view .LVU329
+ 1005 01c0 D2F89420 		ldr	r2, [r2, #148]
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1006              		.loc 1 991 14 view .LVU330
+ARM GAS  /tmp/ccXzHHIc.s 			page 42
+
+
+ 1007 01c4 12F0020F 		tst	r2, #2
+ 1008 01c8 03D0     		beq	.L93
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1009              		.loc 1 991 58 discriminator 1 view .LVU331
+ 1010 01ca B3F5802F 		cmp	r3, #262144
+ 1011 01ce 00F01782 		beq	.L123
+ 1012              	.L93:
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1013              		.loc 1 995 12 is_stmt 1 view .LVU332
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1014              		.loc 1 995 16 is_stmt 0 view .LVU333
+ 1015 01d2 2A4A     		ldr	r2, .L173
+ 1016 01d4 1268     		ldr	r2, [r2]
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1017              		.loc 1 995 14 view .LVU334
+ 1018 01d6 12F4806F 		tst	r2, #1024
+ 1019 01da 03D0     		beq	.L94
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1020              		.loc 1 995 56 discriminator 1 view .LVU335
+ 1021 01dc B3F5002F 		cmp	r3, #524288
+ 1022 01e0 00F01182 		beq	.L124
+ 1023              	.L94:
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1024              		.loc 1 999 12 is_stmt 1 view .LVU336
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1025              		.loc 1 999 17 is_stmt 0 view .LVU337
+ 1026 01e4 254A     		ldr	r2, .L173
+ 1027 01e6 D2F89000 		ldr	r0, [r2, #144]
+ 1028              	.LVL55:
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1029              		.loc 1 999 15 view .LVU338
+ 1030 01ea 10F00200 		ands	r0, r0, #2
+ 1031 01ee 00F0E781 		beq	.L45
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1032              		.loc 1 999 61 discriminator 1 view .LVU339
+ 1033 01f2 B3F5402F 		cmp	r3, #786432
+ 1034 01f6 00F00882 		beq	.L125
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1035              		.loc 1 650 12 view .LVU340
+ 1036 01fa 0020     		movs	r0, #0
+ 1037 01fc E0E1     		b	.L45
+ 1038              	.LVL56:
+ 1039              	.L150:
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 1040              		.loc 1 718 5 view .LVU341
+ 1041 01fe 0020     		movs	r0, #0
+ 1042              	.LVL57:
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 1043              		.loc 1 718 5 view .LVU342
+ 1044 0200 DEE1     		b	.L45
+ 1045              	.LVL58:
+ 1046              	.L144:
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 1047              		.loc 1 718 5 view .LVU343
+ 1048 0202 B0F5005F 		cmp	r0, #8192
+ 1049 0206 14D1     		bne	.L152
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       
+ARM GAS  /tmp/ccXzHHIc.s 			page 43
+
+
+ 1050              		.loc 1 1110 7 is_stmt 1 view .LVU344
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       
+ 1051              		.loc 1 1110 16 is_stmt 0 view .LVU345
+ 1052 0208 1C4B     		ldr	r3, .L173
+ 1053 020a D3F88830 		ldr	r3, [r3, #136]
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       
+ 1054              		.loc 1 1110 14 view .LVU346
+ 1055 020e 03F04063 		and	r3, r3, #201326592
+ 1056              	.LVL59:
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1057              		.loc 1 1112 7 is_stmt 1 view .LVU347
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1058              		.loc 1 1112 9 is_stmt 0 view .LVU348
+ 1059 0212 B3F1006F 		cmp	r3, #134217728
+ 1060 0216 00F07481 		beq	.L153
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1061              		.loc 1 1118 12 is_stmt 1 view .LVU349
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1062              		.loc 1 1118 16 is_stmt 0 view .LVU350
+ 1063 021a 184A     		ldr	r2, .L173
+ 1064              	.LVL60:
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1065              		.loc 1 1118 16 view .LVU351
+ 1066 021c D2F89800 		ldr	r0, [r2, #152]
+ 1067              	.LVL61:
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1068              		.loc 1 1118 14 view .LVU352
+ 1069 0220 10F00200 		ands	r0, r0, #2
+ 1070 0224 00F0CC81 		beq	.L45
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1071              		.loc 1 1118 64 discriminator 1 view .LVU353
+ 1072 0228 002B     		cmp	r3, #0
+ 1073 022a 00F0FB81 		beq	.L132
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1074              		.loc 1 650 12 view .LVU354
+ 1075 022e 0020     		movs	r0, #0
+ 1076 0230 C6E1     		b	.L45
+ 1077              	.LVL62:
+ 1078              	.L152:
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 1079              		.loc 1 718 5 view .LVU355
+ 1080 0232 0020     		movs	r0, #0
+ 1081              	.LVL63:
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 1082              		.loc 1 718 5 view .LVU356
+ 1083 0234 C4E1     		b	.L45
+ 1084              	.LVL64:
+ 1085              	.L60:
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1086              		.loc 1 723 7 is_stmt 1 view .LVU357
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1087              		.loc 1 723 16 is_stmt 0 view .LVU358
+ 1088 0236 114B     		ldr	r3, .L173
+ 1089 0238 D3F88830 		ldr	r3, [r3, #136]
+ 1090              	.LVL65:
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1091              		.loc 1 725 7 is_stmt 1 view .LVU359
+ARM GAS  /tmp/ccXzHHIc.s 			page 44
+
+
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1092              		.loc 1 725 9 is_stmt 0 view .LVU360
+ 1093 023c 13F00303 		ands	r3, r3, #3
+ 1094              	.LVL66:
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1095              		.loc 1 725 9 view .LVU361
+ 1096 0240 15D0     		beq	.L154
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1097              		.loc 1 729 12 is_stmt 1 view .LVU362
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1098              		.loc 1 729 14 is_stmt 0 view .LVU363
+ 1099 0242 012B     		cmp	r3, #1
+ 1100 0244 16D0     		beq	.L155
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1101              		.loc 1 733 12 is_stmt 1 view .LVU364
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1102              		.loc 1 733 16 is_stmt 0 view .LVU365
+ 1103 0246 0D4A     		ldr	r2, .L173
+ 1104              	.LVL67:
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1105              		.loc 1 733 16 view .LVU366
+ 1106 0248 1268     		ldr	r2, [r2]
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1107              		.loc 1 733 14 view .LVU367
+ 1108 024a 12F4806F 		tst	r2, #1024
+ 1109 024e 02D0     		beq	.L73
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1110              		.loc 1 733 56 discriminator 1 view .LVU368
+ 1111 0250 022B     		cmp	r3, #2
+ 1112 0252 00F0B681 		beq	.L110
+ 1113              	.L73:
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1114              		.loc 1 737 12 is_stmt 1 view .LVU369
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1115              		.loc 1 737 16 is_stmt 0 view .LVU370
+ 1116 0256 094A     		ldr	r2, .L173
+ 1117 0258 D2F89000 		ldr	r0, [r2, #144]
+ 1118              	.LVL68:
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1119              		.loc 1 737 14 view .LVU371
+ 1120 025c 10F00200 		ands	r0, r0, #2
+ 1121 0260 00F0AE81 		beq	.L45
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1122              		.loc 1 737 60 discriminator 1 view .LVU372
+ 1123 0264 032B     		cmp	r3, #3
+ 1124 0266 00F0AE81 		beq	.L111
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1125              		.loc 1 650 12 view .LVU373
+ 1126 026a 0020     		movs	r0, #0
+ 1127 026c A8E1     		b	.L45
+ 1128              	.LVL69:
+ 1129              	.L154:
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1130              		.loc 1 727 9 is_stmt 1 view .LVU374
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1131              		.loc 1 727 21 is_stmt 0 view .LVU375
+ 1132 026e FFF7FEFF 		bl	HAL_RCC_GetPCLK2Freq
+ARM GAS  /tmp/ccXzHHIc.s 			page 45
+
+
+ 1133              	.LVL70:
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1134              		.loc 1 727 21 view .LVU376
+ 1135 0272 A5E1     		b	.L45
+ 1136              	.LVL71:
+ 1137              	.L155:
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1138              		.loc 1 731 9 is_stmt 1 view .LVU377
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1139              		.loc 1 731 21 is_stmt 0 view .LVU378
+ 1140 0274 FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1141              	.LVL72:
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1142              		.loc 1 731 21 view .LVU379
+ 1143 0278 A2E1     		b	.L45
+ 1144              	.L174:
+ 1145 027a 00BF     		.align	2
+ 1146              	.L173:
+ 1147 027c 00100240 		.word	1073876992
+ 1148 0280 0024F400 		.word	16000000
+ 1149 0284 0080BB00 		.word	12288000
+ 1150              	.LVL73:
+ 1151              	.L59:
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1152              		.loc 1 750 7 is_stmt 1 view .LVU380
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1153              		.loc 1 750 16 is_stmt 0 view .LVU381
+ 1154 0288 AF4B     		ldr	r3, .L175
+ 1155 028a D3F88830 		ldr	r3, [r3, #136]
+ 1156              	.LVL74:
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1157              		.loc 1 752 7 is_stmt 1 view .LVU382
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1158              		.loc 1 752 9 is_stmt 0 view .LVU383
+ 1159 028e 13F00C03 		ands	r3, r3, #12
+ 1160              	.LVL75:
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1161              		.loc 1 752 9 view .LVU384
+ 1162 0292 15D0     		beq	.L156
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1163              		.loc 1 756 12 is_stmt 1 view .LVU385
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1164              		.loc 1 756 14 is_stmt 0 view .LVU386
+ 1165 0294 042B     		cmp	r3, #4
+ 1166 0296 16D0     		beq	.L157
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1167              		.loc 1 760 12 is_stmt 1 view .LVU387
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1168              		.loc 1 760 16 is_stmt 0 view .LVU388
+ 1169 0298 AB4A     		ldr	r2, .L175
+ 1170              	.LVL76:
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1171              		.loc 1 760 16 view .LVU389
+ 1172 029a 1268     		ldr	r2, [r2]
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1173              		.loc 1 760 14 view .LVU390
+ 1174 029c 12F4806F 		tst	r2, #1024
+ARM GAS  /tmp/ccXzHHIc.s 			page 46
+
+
+ 1175 02a0 02D0     		beq	.L76
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1176              		.loc 1 760 56 discriminator 1 view .LVU391
+ 1177 02a2 082B     		cmp	r3, #8
+ 1178 02a4 00F09281 		beq	.L112
+ 1179              	.L76:
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1180              		.loc 1 764 12 is_stmt 1 view .LVU392
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1181              		.loc 1 764 16 is_stmt 0 view .LVU393
+ 1182 02a8 A74A     		ldr	r2, .L175
+ 1183 02aa D2F89000 		ldr	r0, [r2, #144]
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1184              		.loc 1 764 14 view .LVU394
+ 1185 02ae 10F00200 		ands	r0, r0, #2
+ 1186 02b2 00F08581 		beq	.L45
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1187              		.loc 1 764 61 discriminator 1 view .LVU395
+ 1188 02b6 0C2B     		cmp	r3, #12
+ 1189 02b8 00F08A81 		beq	.L113
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1190              		.loc 1 650 12 view .LVU396
+ 1191 02bc 0020     		movs	r0, #0
+ 1192 02be 7FE1     		b	.L45
+ 1193              	.LVL77:
+ 1194              	.L156:
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1195              		.loc 1 754 9 is_stmt 1 view .LVU397
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1196              		.loc 1 754 21 is_stmt 0 view .LVU398
+ 1197 02c0 FFF7FEFF 		bl	HAL_RCC_GetPCLK1Freq
+ 1198              	.LVL78:
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1199              		.loc 1 754 21 view .LVU399
+ 1200 02c4 7CE1     		b	.L45
+ 1201              	.LVL79:
+ 1202              	.L157:
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1203              		.loc 1 758 9 is_stmt 1 view .LVU400
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1204              		.loc 1 758 21 is_stmt 0 view .LVU401
+ 1205 02c6 FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1206              	.LVL80:
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1207              		.loc 1 758 21 view .LVU402
+ 1208 02ca 79E1     		b	.L45
+ 1209              	.LVL81:
+ 1210              	.L58:
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1211              		.loc 1 777 7 is_stmt 1 view .LVU403
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1212              		.loc 1 777 16 is_stmt 0 view .LVU404
+ 1213 02cc 9E4B     		ldr	r3, .L175
+ 1214 02ce D3F88830 		ldr	r3, [r3, #136]
+ 1215              	.LVL82:
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1216              		.loc 1 779 7 is_stmt 1 view .LVU405
+ARM GAS  /tmp/ccXzHHIc.s 			page 47
+
+
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1217              		.loc 1 779 9 is_stmt 0 view .LVU406
+ 1218 02d2 13F03003 		ands	r3, r3, #48
+ 1219              	.LVL83:
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1220              		.loc 1 779 9 view .LVU407
+ 1221 02d6 15D0     		beq	.L158
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1222              		.loc 1 783 12 is_stmt 1 view .LVU408
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1223              		.loc 1 783 14 is_stmt 0 view .LVU409
+ 1224 02d8 102B     		cmp	r3, #16
+ 1225 02da 16D0     		beq	.L159
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1226              		.loc 1 787 12 is_stmt 1 view .LVU410
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1227              		.loc 1 787 16 is_stmt 0 view .LVU411
+ 1228 02dc 9A4A     		ldr	r2, .L175
+ 1229              	.LVL84:
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1230              		.loc 1 787 16 view .LVU412
+ 1231 02de 1268     		ldr	r2, [r2]
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1232              		.loc 1 787 14 view .LVU413
+ 1233 02e0 12F4806F 		tst	r2, #1024
+ 1234 02e4 02D0     		beq	.L79
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1235              		.loc 1 787 56 discriminator 1 view .LVU414
+ 1236 02e6 202B     		cmp	r3, #32
+ 1237 02e8 00F07581 		beq	.L114
+ 1238              	.L79:
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1239              		.loc 1 791 12 is_stmt 1 view .LVU415
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1240              		.loc 1 791 16 is_stmt 0 view .LVU416
+ 1241 02ec 964A     		ldr	r2, .L175
+ 1242 02ee D2F89000 		ldr	r0, [r2, #144]
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1243              		.loc 1 791 14 view .LVU417
+ 1244 02f2 10F00200 		ands	r0, r0, #2
+ 1245 02f6 00F06381 		beq	.L45
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1246              		.loc 1 791 60 discriminator 1 view .LVU418
+ 1247 02fa 302B     		cmp	r3, #48
+ 1248 02fc 00F06D81 		beq	.L115
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1249              		.loc 1 650 12 view .LVU419
+ 1250 0300 0020     		movs	r0, #0
+ 1251 0302 5DE1     		b	.L45
+ 1252              	.LVL85:
+ 1253              	.L158:
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1254              		.loc 1 781 9 is_stmt 1 view .LVU420
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1255              		.loc 1 781 21 is_stmt 0 view .LVU421
+ 1256 0304 FFF7FEFF 		bl	HAL_RCC_GetPCLK1Freq
+ 1257              	.LVL86:
+ARM GAS  /tmp/ccXzHHIc.s 			page 48
+
+
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1258              		.loc 1 781 21 view .LVU422
+ 1259 0308 5AE1     		b	.L45
+ 1260              	.LVL87:
+ 1261              	.L159:
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1262              		.loc 1 785 9 is_stmt 1 view .LVU423
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1263              		.loc 1 785 21 is_stmt 0 view .LVU424
+ 1264 030a FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1265              	.LVL88:
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1266              		.loc 1 785 21 view .LVU425
+ 1267 030e 57E1     		b	.L45
+ 1268              	.LVL89:
+ 1269              	.L57:
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1270              		.loc 1 805 7 is_stmt 1 view .LVU426
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1271              		.loc 1 805 16 is_stmt 0 view .LVU427
+ 1272 0310 8D4B     		ldr	r3, .L175
+ 1273 0312 D3F88830 		ldr	r3, [r3, #136]
+ 1274              	.LVL90:
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1275              		.loc 1 807 7 is_stmt 1 view .LVU428
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1276              		.loc 1 807 9 is_stmt 0 view .LVU429
+ 1277 0316 13F0C003 		ands	r3, r3, #192
+ 1278              	.LVL91:
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1279              		.loc 1 807 9 view .LVU430
+ 1280 031a 15D0     		beq	.L160
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1281              		.loc 1 811 12 is_stmt 1 view .LVU431
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1282              		.loc 1 811 14 is_stmt 0 view .LVU432
+ 1283 031c 402B     		cmp	r3, #64
+ 1284 031e 16D0     		beq	.L161
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1285              		.loc 1 815 12 is_stmt 1 view .LVU433
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1286              		.loc 1 815 16 is_stmt 0 view .LVU434
+ 1287 0320 894A     		ldr	r2, .L175
+ 1288              	.LVL92:
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1289              		.loc 1 815 16 view .LVU435
+ 1290 0322 1268     		ldr	r2, [r2]
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1291              		.loc 1 815 14 view .LVU436
+ 1292 0324 12F4806F 		tst	r2, #1024
+ 1293 0328 02D0     		beq	.L82
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1294              		.loc 1 815 56 discriminator 1 view .LVU437
+ 1295 032a 802B     		cmp	r3, #128
+ 1296 032c 00F05881 		beq	.L116
+ 1297              	.L82:
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ARM GAS  /tmp/ccXzHHIc.s 			page 49
+
+
+ 1298              		.loc 1 819 12 is_stmt 1 view .LVU438
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1299              		.loc 1 819 16 is_stmt 0 view .LVU439
+ 1300 0330 854A     		ldr	r2, .L175
+ 1301 0332 D2F89000 		ldr	r0, [r2, #144]
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1302              		.loc 1 819 14 view .LVU440
+ 1303 0336 10F00200 		ands	r0, r0, #2
+ 1304 033a 00F04181 		beq	.L45
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1305              		.loc 1 819 60 discriminator 1 view .LVU441
+ 1306 033e C02B     		cmp	r3, #192
+ 1307 0340 00F05081 		beq	.L117
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1308              		.loc 1 650 12 view .LVU442
+ 1309 0344 0020     		movs	r0, #0
+ 1310 0346 3BE1     		b	.L45
+ 1311              	.LVL93:
+ 1312              	.L160:
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1313              		.loc 1 809 9 is_stmt 1 view .LVU443
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1314              		.loc 1 809 21 is_stmt 0 view .LVU444
+ 1315 0348 FFF7FEFF 		bl	HAL_RCC_GetPCLK1Freq
+ 1316              	.LVL94:
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1317              		.loc 1 809 21 view .LVU445
+ 1318 034c 38E1     		b	.L45
+ 1319              	.LVL95:
+ 1320              	.L161:
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1321              		.loc 1 813 9 is_stmt 1 view .LVU446
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1322              		.loc 1 813 21 is_stmt 0 view .LVU447
+ 1323 034e FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1324              	.LVL96:
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1325              		.loc 1 813 21 view .LVU448
+ 1326 0352 35E1     		b	.L45
+ 1327              	.LVL97:
+ 1328              	.L55:
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1329              		.loc 1 862 7 is_stmt 1 view .LVU449
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1330              		.loc 1 862 16 is_stmt 0 view .LVU450
+ 1331 0354 7C4B     		ldr	r3, .L175
+ 1332 0356 D3F88830 		ldr	r3, [r3, #136]
+ 1333              	.LVL98:
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1334              		.loc 1 864 7 is_stmt 1 view .LVU451
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1335              		.loc 1 864 9 is_stmt 0 view .LVU452
+ 1336 035a 13F44063 		ands	r3, r3, #3072
+ 1337              	.LVL99:
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1338              		.loc 1 864 9 view .LVU453
+ 1339 035e 18D0     		beq	.L162
+ARM GAS  /tmp/ccXzHHIc.s 			page 50
+
+
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1340              		.loc 1 868 12 is_stmt 1 view .LVU454
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1341              		.loc 1 868 14 is_stmt 0 view .LVU455
+ 1342 0360 B3F5806F 		cmp	r3, #1024
+ 1343 0364 18D0     		beq	.L163
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1344              		.loc 1 872 12 is_stmt 1 view .LVU456
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1345              		.loc 1 872 16 is_stmt 0 view .LVU457
+ 1346 0366 784A     		ldr	r2, .L175
+ 1347              	.LVL100:
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1348              		.loc 1 872 16 view .LVU458
+ 1349 0368 1268     		ldr	r2, [r2]
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1350              		.loc 1 872 14 view .LVU459
+ 1351 036a 12F4806F 		tst	r2, #1024
+ 1352 036e 03D0     		beq	.L85
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1353              		.loc 1 872 56 discriminator 1 view .LVU460
+ 1354 0370 B3F5006F 		cmp	r3, #2048
+ 1355 0374 00F03981 		beq	.L118
+ 1356              	.L85:
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1357              		.loc 1 876 12 is_stmt 1 view .LVU461
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1358              		.loc 1 876 16 is_stmt 0 view .LVU462
+ 1359 0378 734A     		ldr	r2, .L175
+ 1360 037a D2F89000 		ldr	r0, [r2, #144]
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1361              		.loc 1 876 14 view .LVU463
+ 1362 037e 10F00200 		ands	r0, r0, #2
+ 1363 0382 00F01D81 		beq	.L45
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1364              		.loc 1 876 60 discriminator 1 view .LVU464
+ 1365 0386 B3F5406F 		cmp	r3, #3072
+ 1366 038a 00F03081 		beq	.L119
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1367              		.loc 1 650 12 view .LVU465
+ 1368 038e 0020     		movs	r0, #0
+ 1369 0390 16E1     		b	.L45
+ 1370              	.LVL101:
+ 1371              	.L162:
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1372              		.loc 1 866 9 is_stmt 1 view .LVU466
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1373              		.loc 1 866 21 is_stmt 0 view .LVU467
+ 1374 0392 FFF7FEFF 		bl	HAL_RCC_GetPCLK1Freq
+ 1375              	.LVL102:
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1376              		.loc 1 866 21 view .LVU468
+ 1377 0396 13E1     		b	.L45
+ 1378              	.LVL103:
+ 1379              	.L163:
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1380              		.loc 1 870 9 is_stmt 1 view .LVU469
+ARM GAS  /tmp/ccXzHHIc.s 			page 51
+
+
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1381              		.loc 1 870 21 is_stmt 0 view .LVU470
+ 1382 0398 FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1383              	.LVL104:
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1384              		.loc 1 870 21 view .LVU471
+ 1385 039c 10E1     		b	.L45
+ 1386              	.LVL105:
+ 1387              	.L61:
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1388              		.loc 1 889 7 is_stmt 1 view .LVU472
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1389              		.loc 1 889 16 is_stmt 0 view .LVU473
+ 1390 039e 6A4B     		ldr	r3, .L175
+ 1391 03a0 D3F88830 		ldr	r3, [r3, #136]
+ 1392              	.LVL106:
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1393              		.loc 1 891 7 is_stmt 1 view .LVU474
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1394              		.loc 1 891 9 is_stmt 0 view .LVU475
+ 1395 03a4 13F44053 		ands	r3, r3, #12288
+ 1396              	.LVL107:
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1397              		.loc 1 891 9 view .LVU476
+ 1398 03a8 0ED0     		beq	.L164
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1399              		.loc 1 895 12 is_stmt 1 view .LVU477
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1400              		.loc 1 895 14 is_stmt 0 view .LVU478
+ 1401 03aa B3F5805F 		cmp	r3, #4096
+ 1402 03ae 0ED0     		beq	.L165
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1403              		.loc 1 899 12 is_stmt 1 view .LVU479
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1404              		.loc 1 899 16 is_stmt 0 view .LVU480
+ 1405 03b0 654A     		ldr	r2, .L175
+ 1406              	.LVL108:
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1407              		.loc 1 899 16 view .LVU481
+ 1408 03b2 1068     		ldr	r0, [r2]
+ 1409              	.LVL109:
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1410              		.loc 1 899 14 view .LVU482
+ 1411 03b4 10F48060 		ands	r0, r0, #1024
+ 1412 03b8 00F00281 		beq	.L45
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1413              		.loc 1 899 56 discriminator 1 view .LVU483
+ 1414 03bc B3F5005F 		cmp	r3, #8192
+ 1415 03c0 00F01881 		beq	.L120
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1416              		.loc 1 650 12 view .LVU484
+ 1417 03c4 0020     		movs	r0, #0
+ 1418 03c6 FBE0     		b	.L45
+ 1419              	.LVL110:
+ 1420              	.L164:
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1421              		.loc 1 893 9 is_stmt 1 view .LVU485
+ARM GAS  /tmp/ccXzHHIc.s 			page 52
+
+
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1422              		.loc 1 893 21 is_stmt 0 view .LVU486
+ 1423 03c8 FFF7FEFF 		bl	HAL_RCC_GetPCLK1Freq
+ 1424              	.LVL111:
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1425              		.loc 1 893 21 view .LVU487
+ 1426 03cc F8E0     		b	.L45
+ 1427              	.LVL112:
+ 1428              	.L165:
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1429              		.loc 1 897 9 is_stmt 1 view .LVU488
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1430              		.loc 1 897 21 is_stmt 0 view .LVU489
+ 1431 03ce FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1432              	.LVL113:
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1433              		.loc 1 897 21 view .LVU490
+ 1434 03d2 F5E0     		b	.L45
+ 1435              	.LVL114:
+ 1436              	.L141:
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1437              		.loc 1 916 9 is_stmt 1 view .LVU491
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1438              		.loc 1 916 21 is_stmt 0 view .LVU492
+ 1439 03d4 FFF7FEFF 		bl	HAL_RCC_GetPCLK1Freq
+ 1440              	.LVL115:
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1441              		.loc 1 916 21 view .LVU493
+ 1442 03d8 F2E0     		b	.L45
+ 1443              	.LVL116:
+ 1444              	.L142:
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1445              		.loc 1 920 9 is_stmt 1 view .LVU494
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1446              		.loc 1 920 21 is_stmt 0 view .LVU495
+ 1447 03da FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1448              	.LVL117:
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1449              		.loc 1 920 21 view .LVU496
+ 1450 03de EFE0     		b	.L45
+ 1451              	.LVL118:
+ 1452              	.L52:
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1453              		.loc 1 935 7 is_stmt 1 view .LVU497
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1454              		.loc 1 935 16 is_stmt 0 view .LVU498
+ 1455 03e0 594B     		ldr	r3, .L175
+ 1456 03e2 D3F88830 		ldr	r3, [r3, #136]
+ 1457              	.LVL119:
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1458              		.loc 1 937 7 is_stmt 1 view .LVU499
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1459              		.loc 1 937 9 is_stmt 0 view .LVU500
+ 1460 03e6 13F44033 		ands	r3, r3, #196608
+ 1461              	.LVL120:
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1462              		.loc 1 937 9 view .LVU501
+ARM GAS  /tmp/ccXzHHIc.s 			page 53
+
+
+ 1463 03ea 0ED0     		beq	.L166
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1464              		.loc 1 941 12 is_stmt 1 view .LVU502
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1465              		.loc 1 941 14 is_stmt 0 view .LVU503
+ 1466 03ec B3F5803F 		cmp	r3, #65536
+ 1467 03f0 0ED0     		beq	.L167
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1468              		.loc 1 945 12 is_stmt 1 view .LVU504
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1469              		.loc 1 945 16 is_stmt 0 view .LVU505
+ 1470 03f2 554A     		ldr	r2, .L175
+ 1471              	.LVL121:
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1472              		.loc 1 945 16 view .LVU506
+ 1473 03f4 1068     		ldr	r0, [r2]
+ 1474              	.LVL122:
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1475              		.loc 1 945 14 view .LVU507
+ 1476 03f6 10F48060 		ands	r0, r0, #1024
+ 1477 03fa 00F0E180 		beq	.L45
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1478              		.loc 1 945 56 discriminator 1 view .LVU508
+ 1479 03fe B3F5003F 		cmp	r3, #131072
+ 1480 0402 00F0FB80 		beq	.L122
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1481              		.loc 1 650 12 view .LVU509
+ 1482 0406 0020     		movs	r0, #0
+ 1483 0408 DAE0     		b	.L45
+ 1484              	.LVL123:
+ 1485              	.L166:
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1486              		.loc 1 939 9 is_stmt 1 view .LVU510
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1487              		.loc 1 939 21 is_stmt 0 view .LVU511
+ 1488 040a FFF7FEFF 		bl	HAL_RCC_GetPCLK1Freq
+ 1489              	.LVL124:
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1490              		.loc 1 939 21 view .LVU512
+ 1491 040e D7E0     		b	.L45
+ 1492              	.LVL125:
+ 1493              	.L167:
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1494              		.loc 1 943 9 is_stmt 1 view .LVU513
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1495              		.loc 1 943 21 is_stmt 0 view .LVU514
+ 1496 0410 FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1497              	.LVL126:
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1498              		.loc 1 943 21 view .LVU515
+ 1499 0414 D4E0     		b	.L45
+ 1500              	.LVL127:
+ 1501              	.L151:
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1502              		.loc 1 989 9 is_stmt 1 view .LVU516
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1503              		.loc 1 989 21 is_stmt 0 view .LVU517
+ARM GAS  /tmp/ccXzHHIc.s 			page 54
+
+
+ 1504 0416 FFF7FEFF 		bl	HAL_RCC_GetPCLK1Freq
+ 1505              	.LVL128:
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1506              		.loc 1 989 21 view .LVU518
+ 1507 041a D1E0     		b	.L45
+ 1508              	.LVL129:
+ 1509              	.L65:
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1510              		.loc 1 1012 7 is_stmt 1 view .LVU519
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1511              		.loc 1 1012 16 is_stmt 0 view .LVU520
+ 1512 041c 4A4B     		ldr	r3, .L175
+ 1513 041e D3F88830 		ldr	r3, [r3, #136]
+ 1514              	.LVL130:
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1515              		.loc 1 1014 7 is_stmt 1 view .LVU521
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1516              		.loc 1 1014 9 is_stmt 0 view .LVU522
+ 1517 0422 13F44013 		ands	r3, r3, #3145728
+ 1518              	.LVL131:
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1519              		.loc 1 1014 9 view .LVU523
+ 1520 0426 12D0     		beq	.L168
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1521              		.loc 1 1018 12 is_stmt 1 view .LVU524
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1522              		.loc 1 1018 14 is_stmt 0 view .LVU525
+ 1523 0428 B3F5801F 		cmp	r3, #1048576
+ 1524 042c 12D0     		beq	.L169
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1525              		.loc 1 1027 12 is_stmt 1 view .LVU526
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1526              		.loc 1 1027 14 is_stmt 0 view .LVU527
+ 1527 042e B3F5001F 		cmp	r3, #2097152
+ 1528 0432 00F0ED80 		beq	.L126
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1529              		.loc 1 1032 12 is_stmt 1 view .LVU528
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1530              		.loc 1 1032 16 is_stmt 0 view .LVU529
+ 1531 0436 444A     		ldr	r2, .L175
+ 1532              	.LVL132:
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1533              		.loc 1 1032 16 view .LVU530
+ 1534 0438 1068     		ldr	r0, [r2]
+ 1535              	.LVL133:
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1536              		.loc 1 1032 14 view .LVU531
+ 1537 043a 10F48060 		ands	r0, r0, #1024
+ 1538 043e 00F0BF80 		beq	.L45
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1539              		.loc 1 1032 56 discriminator 1 view .LVU532
+ 1540 0442 B3F5401F 		cmp	r3, #3145728
+ 1541 0446 00F0E580 		beq	.L127
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1542              		.loc 1 650 12 view .LVU533
+ 1543 044a 0020     		movs	r0, #0
+ 1544 044c B8E0     		b	.L45
+ARM GAS  /tmp/ccXzHHIc.s 			page 55
+
+
+ 1545              	.LVL134:
+ 1546              	.L168:
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1547              		.loc 1 1016 9 is_stmt 1 view .LVU534
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1548              		.loc 1 1016 21 is_stmt 0 view .LVU535
+ 1549 044e FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1550              	.LVL135:
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1551              		.loc 1 1016 21 view .LVU536
+ 1552 0452 B5E0     		b	.L45
+ 1553              	.LVL136:
+ 1554              	.L169:
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1555              		.loc 1 1020 9 is_stmt 1 view .LVU537
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1556              		.loc 1 1020 12 is_stmt 0 view .LVU538
+ 1557 0454 03F18043 		add	r3, r3, #1073741824
+ 1558              	.LVL137:
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1559              		.loc 1 1020 12 view .LVU539
+ 1560 0458 A3F55F23 		sub	r3, r3, #913408
+ 1561              	.LVL138:
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1562              		.loc 1 1020 12 view .LVU540
+ 1563 045c D868     		ldr	r0, [r3, #12]
+ 1564              	.LVL139:
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1565              		.loc 1 1020 11 view .LVU541
+ 1566 045e 10F48010 		ands	r0, r0, #1048576
+ 1567 0462 00F0AD80 		beq	.L45
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
+ 1568              		.loc 1 1023 11 is_stmt 1 view .LVU542
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
+ 1569              		.loc 1 1023 18 is_stmt 0 view .LVU543
+ 1570 0466 D868     		ldr	r0, [r3, #12]
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
+ 1571              		.loc 1 1023 16 view .LVU544
+ 1572 0468 C0F30620 		ubfx	r0, r0, #8, #7
+ 1573              	.LVL140:
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1574              		.loc 1 1024 11 is_stmt 1 view .LVU545
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1575              		.loc 1 1024 31 is_stmt 0 view .LVU546
+ 1576 046c 02FB00F0 		mul	r0, r2, r0
+ 1577              	.LVL141:
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1578              		.loc 1 1024 44 view .LVU547
+ 1579 0470 DB68     		ldr	r3, [r3, #12]
+ 1580              	.LVL142:
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1581              		.loc 1 1024 85 view .LVU548
+ 1582 0472 C3F34153 		ubfx	r3, r3, #21, #2
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1583              		.loc 1 1024 110 view .LVU549
+ 1584 0476 0133     		adds	r3, r3, #1
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ARM GAS  /tmp/ccXzHHIc.s 			page 56
+
+
+ 1585              		.loc 1 1024 116 view .LVU550
+ 1586 0478 5B00     		lsls	r3, r3, #1
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1587              		.loc 1 1024 21 view .LVU551
+ 1588 047a B0FBF3F0 		udiv	r0, r0, r3
+ 1589              	.LVL143:
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1590              		.loc 1 1024 21 view .LVU552
+ 1591 047e 9FE0     		b	.L45
+ 1592              	.LVL144:
+ 1593              	.L148:
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1594              		.loc 1 1049 9 is_stmt 1 view .LVU553
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1595              		.loc 1 1049 21 is_stmt 0 view .LVU554
+ 1596 0480 FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1597              	.LVL145:
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1598              		.loc 1 1049 21 view .LVU555
+ 1599 0484 9CE0     		b	.L45
+ 1600              	.LVL146:
+ 1601              	.L149:
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1602              		.loc 1 1053 9 is_stmt 1 view .LVU556
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1603              		.loc 1 1053 12 is_stmt 0 view .LVU557
+ 1604 0486 03F17F53 		add	r3, r3, #1069547520
+ 1605              	.LVL147:
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1606              		.loc 1 1053 12 view .LVU558
+ 1607 048a 03F50433 		add	r3, r3, #135168
+ 1608              	.LVL148:
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1609              		.loc 1 1053 12 view .LVU559
+ 1610 048e D868     		ldr	r0, [r3, #12]
+ 1611              	.LVL149:
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1612              		.loc 1 1053 11 view .LVU560
+ 1613 0490 10F48010 		ands	r0, r0, #1048576
+ 1614 0494 00F09480 		beq	.L45
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
+ 1615              		.loc 1 1056 11 is_stmt 1 view .LVU561
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
+ 1616              		.loc 1 1056 18 is_stmt 0 view .LVU562
+ 1617 0498 D868     		ldr	r0, [r3, #12]
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
+ 1618              		.loc 1 1056 16 view .LVU563
+ 1619 049a C0F30620 		ubfx	r0, r0, #8, #7
+ 1620              	.LVL150:
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1621              		.loc 1 1057 11 is_stmt 1 view .LVU564
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1622              		.loc 1 1057 31 is_stmt 0 view .LVU565
+ 1623 049e 02FB00F0 		mul	r0, r2, r0
+ 1624              	.LVL151:
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1625              		.loc 1 1057 44 view .LVU566
+ARM GAS  /tmp/ccXzHHIc.s 			page 57
+
+
+ 1626 04a2 DB68     		ldr	r3, [r3, #12]
+ 1627              	.LVL152:
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1628              		.loc 1 1057 85 view .LVU567
+ 1629 04a4 C3F34153 		ubfx	r3, r3, #21, #2
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1630              		.loc 1 1057 110 view .LVU568
+ 1631 04a8 0133     		adds	r3, r3, #1
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1632              		.loc 1 1057 116 view .LVU569
+ 1633 04aa 5B00     		lsls	r3, r3, #1
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1634              		.loc 1 1057 21 view .LVU570
+ 1635 04ac B0FBF3F0 		udiv	r0, r0, r3
+ 1636              	.LVL153:
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1637              		.loc 1 1057 21 view .LVU571
+ 1638 04b0 86E0     		b	.L45
+ 1639              	.LVL154:
+ 1640              	.L63:
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1641              		.loc 1 1079 7 is_stmt 1 view .LVU572
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1642              		.loc 1 1079 16 is_stmt 0 view .LVU573
+ 1643 04b2 254B     		ldr	r3, .L175
+ 1644 04b4 D3F88830 		ldr	r3, [r3, #136]
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1645              		.loc 1 1079 14 view .LVU574
+ 1646 04b8 03F04073 		and	r3, r3, #50331648
+ 1647              	.LVL155:
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1648              		.loc 1 1081 7 is_stmt 1 view .LVU575
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1649              		.loc 1 1081 9 is_stmt 0 view .LVU576
+ 1650 04bc B3F1007F 		cmp	r3, #33554432
+ 1651 04c0 07D0     		beq	.L170
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1652              		.loc 1 1085 12 is_stmt 1 view .LVU577
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1653              		.loc 1 1085 14 is_stmt 0 view .LVU578
+ 1654 04c2 002B     		cmp	r3, #0
+ 1655 04c4 00F0AC80 		beq	.L130
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1656              		.loc 1 1089 12 is_stmt 1 view .LVU579
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1657              		.loc 1 1089 14 is_stmt 0 view .LVU580
+ 1658 04c8 B3F1807F 		cmp	r3, #16777216
+ 1659 04cc 04D0     		beq	.L171
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1660              		.loc 1 650 12 view .LVU581
+ 1661 04ce 0020     		movs	r0, #0
+ 1662              	.LVL156:
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1663              		.loc 1 650 12 view .LVU582
+ 1664 04d0 76E0     		b	.L45
+ 1665              	.LVL157:
+ 1666              	.L170:
+ARM GAS  /tmp/ccXzHHIc.s 			page 58
+
+
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1667              		.loc 1 1083 9 is_stmt 1 view .LVU583
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1668              		.loc 1 1083 21 is_stmt 0 view .LVU584
+ 1669 04d2 FFF7FEFF 		bl	HAL_RCC_GetPCLK1Freq
+ 1670              	.LVL158:
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1671              		.loc 1 1083 21 view .LVU585
+ 1672 04d6 73E0     		b	.L45
+ 1673              	.LVL159:
+ 1674              	.L171:
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1675              		.loc 1 1091 9 is_stmt 1 view .LVU586
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1676              		.loc 1 1091 12 is_stmt 0 view .LVU587
+ 1677 04d8 03F17C53 		add	r3, r3, #1056964608
+ 1678              	.LVL160:
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1679              		.loc 1 1091 12 view .LVU588
+ 1680 04dc 03F50433 		add	r3, r3, #135168
+ 1681              	.LVL161:
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1682              		.loc 1 1091 12 view .LVU589
+ 1683 04e0 D868     		ldr	r0, [r3, #12]
+ 1684              	.LVL162:
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1685              		.loc 1 1091 11 view .LVU590
+ 1686 04e2 10F48010 		ands	r0, r0, #1048576
+ 1687 04e6 6BD0     		beq	.L45
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
+ 1688              		.loc 1 1094 11 is_stmt 1 view .LVU591
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
+ 1689              		.loc 1 1094 18 is_stmt 0 view .LVU592
+ 1690 04e8 D868     		ldr	r0, [r3, #12]
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
+ 1691              		.loc 1 1094 16 view .LVU593
+ 1692 04ea C0F30620 		ubfx	r0, r0, #8, #7
+ 1693              	.LVL163:
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1694              		.loc 1 1095 11 is_stmt 1 view .LVU594
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1695              		.loc 1 1095 31 is_stmt 0 view .LVU595
+ 1696 04ee 02FB00F0 		mul	r0, r2, r0
+ 1697              	.LVL164:
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1698              		.loc 1 1095 44 view .LVU596
+ 1699 04f2 DB68     		ldr	r3, [r3, #12]
+ 1700              	.LVL165:
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1701              		.loc 1 1095 85 view .LVU597
+ 1702 04f4 C3F34153 		ubfx	r3, r3, #21, #2
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1703              		.loc 1 1095 110 view .LVU598
+ 1704 04f8 0133     		adds	r3, r3, #1
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1705              		.loc 1 1095 116 view .LVU599
+ 1706 04fa 5B00     		lsls	r3, r3, #1
+ARM GAS  /tmp/ccXzHHIc.s 			page 59
+
+
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1707              		.loc 1 1095 21 view .LVU600
+ 1708 04fc B0FBF3F0 		udiv	r0, r0, r3
+ 1709              	.LVL166:
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1710              		.loc 1 1095 21 view .LVU601
+ 1711 0500 5EE0     		b	.L45
+ 1712              	.LVL167:
+ 1713              	.L153:
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+ 1714              		.loc 1 1115 9 is_stmt 1 view .LVU602
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+ 1715              		.loc 1 1115 16 is_stmt 0 view .LVU603
+ 1716 0502 03F16053 		add	r3, r3, #939524096
+ 1717              	.LVL168:
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+ 1718              		.loc 1 1115 16 view .LVU604
+ 1719 0506 03F50433 		add	r3, r3, #135168
+ 1720              	.LVL169:
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+ 1721              		.loc 1 1115 16 view .LVU605
+ 1722 050a D868     		ldr	r0, [r3, #12]
+ 1723              	.LVL170:
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+ 1724              		.loc 1 1115 14 view .LVU606
+ 1725 050c C0F30620 		ubfx	r0, r0, #8, #7
+ 1726              	.LVL171:
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1727              		.loc 1 1116 9 is_stmt 1 view .LVU607
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1728              		.loc 1 1116 29 is_stmt 0 view .LVU608
+ 1729 0510 02FB00F0 		mul	r0, r2, r0
+ 1730              	.LVL172:
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1731              		.loc 1 1116 42 view .LVU609
+ 1732 0514 DB68     		ldr	r3, [r3, #12]
+ 1733              	.LVL173:
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1734              		.loc 1 1116 83 view .LVU610
+ 1735 0516 C3F34153 		ubfx	r3, r3, #21, #2
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1736              		.loc 1 1116 108 view .LVU611
+ 1737 051a 0133     		adds	r3, r3, #1
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1738              		.loc 1 1116 114 view .LVU612
+ 1739 051c 5B00     		lsls	r3, r3, #1
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1740              		.loc 1 1116 19 view .LVU613
+ 1741 051e B0FBF3F0 		udiv	r0, r0, r3
+ 1742              	.LVL174:
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1743              		.loc 1 1116 19 view .LVU614
+ 1744 0522 4DE0     		b	.L45
+ 1745              	.LVL175:
+ 1746              	.L68:
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1747              		.loc 1 1132 7 is_stmt 1 view .LVU615
+ARM GAS  /tmp/ccXzHHIc.s 			page 60
+
+
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1748              		.loc 1 1132 16 is_stmt 0 view .LVU616
+ 1749 0524 084B     		ldr	r3, .L175
+ 1750 0526 D3F88830 		ldr	r3, [r3, #136]
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 1751              		.loc 1 1132 14 view .LVU617
+ 1752 052a 03F04063 		and	r3, r3, #201326592
+ 1753              	.LVL176:
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1754              		.loc 1 1134 7 is_stmt 1 view .LVU618
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1755              		.loc 1 1134 9 is_stmt 0 view .LVU619
+ 1756 052e B3F1006F 		cmp	r3, #134217728
+ 1757 0532 0BD0     		beq	.L172
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1758              		.loc 1 1140 12 is_stmt 1 view .LVU620
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1759              		.loc 1 1140 17 is_stmt 0 view .LVU621
+ 1760 0534 044A     		ldr	r2, .L175
+ 1761              	.LVL177:
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1762              		.loc 1 1140 17 view .LVU622
+ 1763 0536 D2F89800 		ldr	r0, [r2, #152]
+ 1764              	.LVL178:
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1765              		.loc 1 1140 14 view .LVU623
+ 1766 053a 10F00200 		ands	r0, r0, #2
+ 1767 053e 3FD0     		beq	.L45
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 1768              		.loc 1 1140 65 discriminator 1 view .LVU624
+ 1769 0540 002B     		cmp	r3, #0
+ 1770 0542 71D0     		beq	.L133
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t srcclk;
+ 1771              		.loc 1 650 12 view .LVU625
+ 1772 0544 0020     		movs	r0, #0
+ 1773 0546 3BE0     		b	.L45
+ 1774              	.L176:
+ 1775              		.align	2
+ 1776              	.L175:
+ 1777 0548 00100240 		.word	1073876992
+ 1778              	.LVL179:
+ 1779              	.L172:
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+ 1780              		.loc 1 1137 9 is_stmt 1 view .LVU626
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+ 1781              		.loc 1 1137 16 is_stmt 0 view .LVU627
+ 1782 054c 03F16053 		add	r3, r3, #939524096
+ 1783              	.LVL180:
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+ 1784              		.loc 1 1137 16 view .LVU628
+ 1785 0550 03F50433 		add	r3, r3, #135168
+ 1786              	.LVL181:
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+ 1787              		.loc 1 1137 16 view .LVU629
+ 1788 0554 D868     		ldr	r0, [r3, #12]
+ 1789              	.LVL182:
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
+ARM GAS  /tmp/ccXzHHIc.s 			page 61
+
+
+ 1790              		.loc 1 1137 14 view .LVU630
+ 1791 0556 C0F30620 		ubfx	r0, r0, #8, #7
+ 1792              	.LVL183:
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1793              		.loc 1 1138 9 is_stmt 1 view .LVU631
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1794              		.loc 1 1138 29 is_stmt 0 view .LVU632
+ 1795 055a 02FB00F0 		mul	r0, r2, r0
+ 1796              	.LVL184:
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1797              		.loc 1 1138 42 view .LVU633
+ 1798 055e DB68     		ldr	r3, [r3, #12]
+ 1799              	.LVL185:
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1800              		.loc 1 1138 83 view .LVU634
+ 1801 0560 C3F34153 		ubfx	r3, r3, #21, #2
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1802              		.loc 1 1138 108 view .LVU635
+ 1803 0564 0133     		adds	r3, r3, #1
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1804              		.loc 1 1138 114 view .LVU636
+ 1805 0566 5B00     		lsls	r3, r3, #1
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1806              		.loc 1 1138 19 view .LVU637
+ 1807 0568 B0FBF3F0 		udiv	r0, r0, r3
+ 1808              	.LVL186:
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1809              		.loc 1 1138 19 view .LVU638
+ 1810 056c 28E0     		b	.L45
+ 1811              	.LVL187:
+ 1812              	.L145:
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1813              		.loc 1 1156 9 is_stmt 1 view .LVU639
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1814              		.loc 1 1156 12 is_stmt 0 view .LVU640
+ 1815 056e 03F14053 		add	r3, r3, #805306368
+ 1816              	.LVL188:
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1817              		.loc 1 1156 12 view .LVU641
+ 1818 0572 03F50433 		add	r3, r3, #135168
+ 1819              	.LVL189:
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1820              		.loc 1 1156 12 view .LVU642
+ 1821 0576 D868     		ldr	r0, [r3, #12]
+ 1822              	.LVL190:
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         {
+ 1823              		.loc 1 1156 11 view .LVU643
+ 1824 0578 10F48030 		ands	r0, r0, #65536
+ 1825 057c 20D0     		beq	.L45
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
+ 1826              		.loc 1 1159 11 is_stmt 1 view .LVU644
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
+ 1827              		.loc 1 1159 18 is_stmt 0 view .LVU645
+ 1828 057e D968     		ldr	r1, [r3, #12]
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
+ 1829              		.loc 1 1159 16 view .LVU646
+ 1830 0580 C1F30621 		ubfx	r1, r1, #8, #7
+ARM GAS  /tmp/ccXzHHIc.s 			page 62
+
+
+ 1831              	.LVL191:
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           if(pllp == 0U)
+ 1832              		.loc 1 1160 11 is_stmt 1 view .LVU647
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           if(pllp == 0U)
+ 1833              		.loc 1 1160 18 is_stmt 0 view .LVU648
+ 1834 0584 DB68     		ldr	r3, [r3, #12]
+ 1835              	.LVL192:
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           {
+ 1836              		.loc 1 1161 11 is_stmt 1 view .LVU649
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           {
+ 1837              		.loc 1 1161 13 is_stmt 0 view .LVU650
+ 1838 0586 DB0E     		lsrs	r3, r3, #27
+ 1839              	.LVL193:
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           {
+ 1840              		.loc 1 1161 13 view .LVU651
+ 1841 0588 05D1     		bne	.L103
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             {
+ 1842              		.loc 1 1163 13 is_stmt 1 view .LVU652
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             {
+ 1843              		.loc 1 1163 16 is_stmt 0 view .LVU653
+ 1844 058a 284B     		ldr	r3, .L177
+ 1845              	.LVL194:
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             {
+ 1846              		.loc 1 1163 16 view .LVU654
+ 1847 058c DB68     		ldr	r3, [r3, #12]
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             {
+ 1848              		.loc 1 1163 15 view .LVU655
+ 1849 058e 13F4003F 		tst	r3, #131072
+ 1850 0592 05D0     		beq	.L134
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             }
+ 1851              		.loc 1 1165 20 view .LVU656
+ 1852 0594 1123     		movs	r3, #17
+ 1853              	.L103:
+ 1854              	.LVL195:
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1855              		.loc 1 1172 11 is_stmt 1 view .LVU657
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1856              		.loc 1 1172 31 is_stmt 0 view .LVU658
+ 1857 0596 01FB02F2 		mul	r2, r1, r2
+ 1858              	.LVL196:
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1859              		.loc 1 1172 21 view .LVU659
+ 1860 059a B2FBF3F0 		udiv	r0, r2, r3
+ 1861              	.LVL197:
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         }
+ 1862              		.loc 1 1172 21 view .LVU660
+ 1863 059e 0FE0     		b	.L45
+ 1864              	.LVL198:
+ 1865              	.L134:
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             }
+ 1866              		.loc 1 1169 20 view .LVU661
+ 1867 05a0 0723     		movs	r3, #7
+ 1868 05a2 F8E7     		b	.L103
+ 1869              	.LVL199:
+ 1870              	.L146:
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1871              		.loc 1 1177 9 is_stmt 1 view .LVU662
+ARM GAS  /tmp/ccXzHHIc.s 			page 63
+
+
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1872              		.loc 1 1177 21 is_stmt 0 view .LVU663
+ 1873 05a4 FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1874              	.LVL200:
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1875              		.loc 1 1177 21 view .LVU664
+ 1876 05a8 0AE0     		b	.L45
+ 1877              	.LVL201:
+ 1878              	.L104:
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 1879              		.loc 1 665 17 view .LVU665
+ 1880 05aa 4FF40040 		mov	r0, #32768
+ 1881              	.LVL202:
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 1882              		.loc 1 665 17 view .LVU666
+ 1883 05ae 07E0     		b	.L45
+ 1884              	.LVL203:
+ 1885              	.L105:
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 1886              		.loc 1 670 17 view .LVU667
+ 1887 05b0 4FF4FA40 		mov	r0, #32000
+ 1888              	.LVL204:
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 1889              		.loc 1 670 17 view .LVU668
+ 1890 05b4 04E0     		b	.L45
+ 1891              	.L106:
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 1892              		.loc 1 675 17 view .LVU669
+ 1893 05b6 1E48     		ldr	r0, .L177+4
+ 1894 05b8 02E0     		b	.L45
+ 1895              	.LVL205:
+ 1896              	.L108:
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 1897              		.loc 1 718 5 view .LVU670
+ 1898 05ba 0020     		movs	r0, #0
+ 1899              	.LVL206:
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 1900              		.loc 1 718 5 view .LVU671
+ 1901 05bc 00E0     		b	.L45
+ 1902              	.L109:
+ 1903 05be 0020     		movs	r0, #0
+ 1904              	.LVL207:
+ 1905              	.L45:
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 1906              		.loc 1 1258 1 view .LVU672
+ 1907 05c0 08BD     		pop	{r3, pc}
+ 1908              	.LVL208:
+ 1909              	.L110:
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1910              		.loc 1 735 19 view .LVU673
+ 1911 05c2 1C48     		ldr	r0, .L177+8
+ 1912              	.LVL209:
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1913              		.loc 1 735 19 view .LVU674
+ 1914 05c4 FCE7     		b	.L45
+ 1915              	.L111:
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ARM GAS  /tmp/ccXzHHIc.s 			page 64
+
+
+ 1916              		.loc 1 739 19 view .LVU675
+ 1917 05c6 4FF40040 		mov	r0, #32768
+ 1918 05ca F9E7     		b	.L45
+ 1919              	.L112:
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1920              		.loc 1 762 19 view .LVU676
+ 1921 05cc 1948     		ldr	r0, .L177+8
+ 1922 05ce F7E7     		b	.L45
+ 1923              	.L113:
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1924              		.loc 1 766 19 view .LVU677
+ 1925 05d0 4FF40040 		mov	r0, #32768
+ 1926 05d4 F4E7     		b	.L45
+ 1927              	.L114:
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1928              		.loc 1 789 19 view .LVU678
+ 1929 05d6 1748     		ldr	r0, .L177+8
+ 1930 05d8 F2E7     		b	.L45
+ 1931              	.L115:
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1932              		.loc 1 793 19 view .LVU679
+ 1933 05da 4FF40040 		mov	r0, #32768
+ 1934 05de EFE7     		b	.L45
+ 1935              	.L116:
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1936              		.loc 1 817 19 view .LVU680
+ 1937 05e0 1448     		ldr	r0, .L177+8
+ 1938 05e2 EDE7     		b	.L45
+ 1939              	.L117:
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1940              		.loc 1 821 19 view .LVU681
+ 1941 05e4 4FF40040 		mov	r0, #32768
+ 1942 05e8 EAE7     		b	.L45
+ 1943              	.L118:
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1944              		.loc 1 874 19 view .LVU682
+ 1945 05ea 1248     		ldr	r0, .L177+8
+ 1946 05ec E8E7     		b	.L45
+ 1947              	.L119:
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1948              		.loc 1 878 19 view .LVU683
+ 1949 05ee 4FF40040 		mov	r0, #32768
+ 1950 05f2 E5E7     		b	.L45
+ 1951              	.L120:
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1952              		.loc 1 901 19 view .LVU684
+ 1953 05f4 0F48     		ldr	r0, .L177+8
+ 1954 05f6 E3E7     		b	.L45
+ 1955              	.L121:
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1956              		.loc 1 924 19 view .LVU685
+ 1957 05f8 0E48     		ldr	r0, .L177+8
+ 1958 05fa E1E7     		b	.L45
+ 1959              	.L122:
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1960              		.loc 1 947 19 view .LVU686
+ 1961 05fc 0D48     		ldr	r0, .L177+8
+ARM GAS  /tmp/ccXzHHIc.s 			page 65
+
+
+ 1962 05fe DFE7     		b	.L45
+ 1963              	.LVL210:
+ 1964              	.L123:
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1965              		.loc 1 993 19 view .LVU687
+ 1966 0600 4FF4FA40 		mov	r0, #32000
+ 1967              	.LVL211:
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1968              		.loc 1 993 19 view .LVU688
+ 1969 0604 DCE7     		b	.L45
+ 1970              	.LVL212:
+ 1971              	.L124:
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1972              		.loc 1 997 19 view .LVU689
+ 1973 0606 0B48     		ldr	r0, .L177+8
+ 1974              	.LVL213:
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1975              		.loc 1 997 19 view .LVU690
+ 1976 0608 DAE7     		b	.L45
+ 1977              	.L125:
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1978              		.loc 1 1001 19 view .LVU691
+ 1979 060a 4FF40040 		mov	r0, #32768
+ 1980 060e D7E7     		b	.L45
+ 1981              	.LVL214:
+ 1982              	.L126:
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1983              		.loc 1 1030 19 view .LVU692
+ 1984 0610 0948     		ldr	r0, .L177+12
+ 1985              	.LVL215:
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1986              		.loc 1 1030 19 view .LVU693
+ 1987 0612 D5E7     		b	.L45
+ 1988              	.LVL216:
+ 1989              	.L127:
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 1990              		.loc 1 1034 19 view .LVU694
+ 1991 0614 0748     		ldr	r0, .L177+8
+ 1992 0616 D3E7     		b	.L45
+ 1993              	.LVL217:
+ 1994              	.L128:
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }      
+ 1995              		.loc 1 1063 19 view .LVU695
+ 1996 0618 0748     		ldr	r0, .L177+12
+ 1997              	.LVL218:
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }      
+ 1998              		.loc 1 1063 19 view .LVU696
+ 1999 061a D1E7     		b	.L45
+ 2000              	.LVL219:
+ 2001              	.L129:
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 2002              		.loc 1 1067 19 view .LVU697
+ 2003 061c 0548     		ldr	r0, .L177+8
+ 2004 061e CFE7     		b	.L45
+ 2005              	.LVL220:
+ 2006              	.L130:
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ARM GAS  /tmp/ccXzHHIc.s 			page 66
+
+
+ 2007              		.loc 1 1087 19 view .LVU698
+ 2008 0620 0548     		ldr	r0, .L177+12
+ 2009              	.LVL221:
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 2010              		.loc 1 1087 19 view .LVU699
+ 2011 0622 CDE7     		b	.L45
+ 2012              	.LVL222:
+ 2013              	.L132:
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 2014              		.loc 1 1120 19 view .LVU700
+ 2015 0624 0548     		ldr	r0, .L177+16
+ 2016 0626 CBE7     		b	.L45
+ 2017              	.L133:
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 2018              		.loc 1 1142 19 view .LVU701
+ 2019 0628 0448     		ldr	r0, .L177+16
+ 2020 062a C9E7     		b	.L45
+ 2021              	.L178:
+ 2022              		.align	2
+ 2023              	.L177:
+ 2024 062c 00100240 		.word	1073876992
+ 2025 0630 00DC0500 		.word	384000
+ 2026 0634 0024F400 		.word	16000000
+ 2027 0638 0080BB00 		.word	12288000
+ 2028 063c 006CDC02 		.word	48000000
+ 2029              		.cfi_endproc
+ 2030              	.LFE331:
+ 2032              		.section	.text.HAL_RCCEx_EnableLSECSS,"ax",%progbits
+ 2033              		.align	1
+ 2034              		.global	HAL_RCCEx_EnableLSECSS
+ 2035              		.syntax unified
+ 2036              		.thumb
+ 2037              		.thumb_func
+ 2039              	HAL_RCCEx_EnableLSECSS:
+ 2040              	.LFB332:
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @}
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  *  @brief  Extended Clock management functions
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  *
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** @verbatim
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  ===============================================================================
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                 ##### Extended clock management functions  #####
+1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  ===============================================================================
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     [..]
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     This subsection provides a set of functions allowing to control the
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     activation or deactivation of LSE CSS,
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     Low speed clock output and clock after wake-up from STOP mode.
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** @endverbatim
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @{
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  Enable the LSE Clock Security System.
+ARM GAS  /tmp/ccXzHHIc.s 			page 67
+
+
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *         clock with HAL_RCCEx_PeriphCLKConfig().
+1284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval None
+1285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableLSECSS(void)
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2041              		.loc 1 1287 1 is_stmt 1 view -0
+ 2042              		.cfi_startproc
+ 2043              		@ args = 0, pretend = 0, frame = 0
+ 2044              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2045              		@ link register save eliminated.
+1288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+ 2046              		.loc 1 1288 3 view .LVU703
+ 2047 0000 034A     		ldr	r2, .L180
+ 2048 0002 D2F89030 		ldr	r3, [r2, #144]
+ 2049 0006 43F02003 		orr	r3, r3, #32
+ 2050 000a C2F89030 		str	r3, [r2, #144]
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2051              		.loc 1 1289 1 is_stmt 0 view .LVU704
+ 2052 000e 7047     		bx	lr
+ 2053              	.L181:
+ 2054              		.align	2
+ 2055              	.L180:
+ 2056 0010 00100240 		.word	1073876992
+ 2057              		.cfi_endproc
+ 2058              	.LFE332:
+ 2060              		.section	.text.HAL_RCCEx_DisableLSECSS,"ax",%progbits
+ 2061              		.align	1
+ 2062              		.global	HAL_RCCEx_DisableLSECSS
+ 2063              		.syntax unified
+ 2064              		.thumb
+ 2065              		.thumb_func
+ 2067              	HAL_RCCEx_DisableLSECSS:
+ 2068              	.LFB333:
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  Disable the LSE Clock Security System.
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval None
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_DisableLSECSS(void)
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2069              		.loc 1 1297 1 is_stmt 1 view -0
+ 2070              		.cfi_startproc
+ 2071              		@ args = 0, pretend = 0, frame = 0
+ 2072              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2073              		@ link register save eliminated.
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+ 2074              		.loc 1 1298 3 view .LVU706
+ 2075 0000 054B     		ldr	r3, .L183
+ 2076 0002 D3F89020 		ldr	r2, [r3, #144]
+ 2077 0006 22F02002 		bic	r2, r2, #32
+ 2078 000a C3F89020 		str	r2, [r3, #144]
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Disable LSE CSS IT if any */
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
+ARM GAS  /tmp/ccXzHHIc.s 			page 68
+
+
+ 2079              		.loc 1 1301 3 view .LVU707
+ 2080 000e 9A69     		ldr	r2, [r3, #24]
+ 2081 0010 22F40072 		bic	r2, r2, #512
+ 2082 0014 9A61     		str	r2, [r3, #24]
+1302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2083              		.loc 1 1302 1 is_stmt 0 view .LVU708
+ 2084 0016 7047     		bx	lr
+ 2085              	.L184:
+ 2086              		.align	2
+ 2087              	.L183:
+ 2088 0018 00100240 		.word	1073876992
+ 2089              		.cfi_endproc
+ 2090              	.LFE333:
+ 2092              		.section	.text.HAL_RCCEx_EnableLSECSS_IT,"ax",%progbits
+ 2093              		.align	1
+ 2094              		.global	HAL_RCCEx_EnableLSECSS_IT
+ 2095              		.syntax unified
+ 2096              		.thumb
+ 2097              		.thumb_func
+ 2099              	HAL_RCCEx_EnableLSECSS_IT:
+ 2100              	.LFB334:
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @note   LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
+1307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval None
+1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableLSECSS_IT(void)
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2101              		.loc 1 1310 1 is_stmt 1 view -0
+ 2102              		.cfi_startproc
+ 2103              		@ args = 0, pretend = 0, frame = 0
+ 2104              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2105              		@ link register save eliminated.
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Enable LSE CSS */
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+ 2106              		.loc 1 1312 3 view .LVU710
+ 2107 0000 0A4B     		ldr	r3, .L186
+ 2108 0002 D3F89020 		ldr	r2, [r3, #144]
+ 2109 0006 42F02002 		orr	r2, r2, #32
+ 2110 000a C3F89020 		str	r2, [r3, #144]
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Enable LSE CSS IT */
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
+ 2111              		.loc 1 1315 3 view .LVU711
+ 2112 000e 9A69     		ldr	r2, [r3, #24]
+ 2113 0010 42F40072 		orr	r2, r2, #512
+ 2114 0014 9A61     		str	r2, [r3, #24]
+1316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Enable IT on EXTI Line 19 */
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
+ 2115              		.loc 1 1318 3 view .LVU712
+ 2116 0016 A3F58633 		sub	r3, r3, #68608
+ 2117 001a 1A68     		ldr	r2, [r3]
+ 2118 001c 42F40022 		orr	r2, r2, #524288
+ 2119 0020 1A60     		str	r2, [r3]
+1319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
+ARM GAS  /tmp/ccXzHHIc.s 			page 69
+
+
+ 2120              		.loc 1 1319 3 view .LVU713
+ 2121 0022 9A68     		ldr	r2, [r3, #8]
+ 2122 0024 42F40022 		orr	r2, r2, #524288
+ 2123 0028 9A60     		str	r2, [r3, #8]
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2124              		.loc 1 1320 1 is_stmt 0 view .LVU714
+ 2125 002a 7047     		bx	lr
+ 2126              	.L187:
+ 2127              		.align	2
+ 2128              	.L186:
+ 2129 002c 00100240 		.word	1073876992
+ 2130              		.cfi_endproc
+ 2131              	.LFE334:
+ 2133              		.section	.text.HAL_RCCEx_LSECSS_Callback,"ax",%progbits
+ 2134              		.align	1
+ 2135              		.weak	HAL_RCCEx_LSECSS_Callback
+ 2136              		.syntax unified
+ 2137              		.thumb
+ 2138              		.thumb_func
+ 2140              	HAL_RCCEx_LSECSS_Callback:
+ 2141              	.LFB336:
+1321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief Handle the RCC LSE Clock Security System interrupt request.
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval None
+1325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_LSECSS_IRQHandler(void)
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+1328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Check RCC LSE CSSF flag  */
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
+1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* RCC LSE Clock Security System interrupt user callback */
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     HAL_RCCEx_LSECSS_Callback();
+1333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Clear RCC LSE CSS pending bit */
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
+1336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+1338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  RCCEx LSE Clock Security System interrupt callback.
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval none
+1342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_LSECSS_Callback(void)
+1344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2142              		.loc 1 1344 1 is_stmt 1 view -0
+ 2143              		.cfi_startproc
+ 2144              		@ args = 0, pretend = 0, frame = 0
+ 2145              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2146              		@ link register save eliminated.
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****    */
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2147              		.loc 1 1348 1 view .LVU716
+ 2148 0000 7047     		bx	lr
+ 2149              		.cfi_endproc
+ARM GAS  /tmp/ccXzHHIc.s 			page 70
+
+
+ 2150              	.LFE336:
+ 2152              		.section	.text.HAL_RCCEx_LSECSS_IRQHandler,"ax",%progbits
+ 2153              		.align	1
+ 2154              		.global	HAL_RCCEx_LSECSS_IRQHandler
+ 2155              		.syntax unified
+ 2156              		.thumb
+ 2157              		.thumb_func
+ 2159              	HAL_RCCEx_LSECSS_IRQHandler:
+ 2160              	.LFB335:
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Check RCC LSE CSSF flag  */
+ 2161              		.loc 1 1327 1 view -0
+ 2162              		.cfi_startproc
+ 2163              		@ args = 0, pretend = 0, frame = 0
+ 2164              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2165 0000 08B5     		push	{r3, lr}
+ 2166              	.LCFI5:
+ 2167              		.cfi_def_cfa_offset 8
+ 2168              		.cfi_offset 3, -8
+ 2169              		.cfi_offset 14, -4
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2170              		.loc 1 1329 3 view .LVU718
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2171              		.loc 1 1329 6 is_stmt 0 view .LVU719
+ 2172 0002 064B     		ldr	r3, .L193
+ 2173 0004 DB69     		ldr	r3, [r3, #28]
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2174              		.loc 1 1329 5 view .LVU720
+ 2175 0006 13F4007F 		tst	r3, #512
+ 2176 000a 00D1     		bne	.L192
+ 2177              	.L189:
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2178              		.loc 1 1337 1 view .LVU721
+ 2179 000c 08BD     		pop	{r3, pc}
+ 2180              	.L192:
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2181              		.loc 1 1332 5 is_stmt 1 view .LVU722
+ 2182 000e FFF7FEFF 		bl	HAL_RCCEx_LSECSS_Callback
+ 2183              	.LVL223:
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 2184              		.loc 1 1335 5 view .LVU723
+ 2185 0012 024B     		ldr	r3, .L193
+ 2186 0014 4FF40072 		mov	r2, #512
+ 2187 0018 1A62     		str	r2, [r3, #32]
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2188              		.loc 1 1337 1 is_stmt 0 view .LVU724
+ 2189 001a F7E7     		b	.L189
+ 2190              	.L194:
+ 2191              		.align	2
+ 2192              	.L193:
+ 2193 001c 00100240 		.word	1073876992
+ 2194              		.cfi_endproc
+ 2195              	.LFE335:
+ 2197              		.section	.text.HAL_RCCEx_EnableLSCO,"ax",%progbits
+ 2198              		.align	1
+ 2199              		.global	HAL_RCCEx_EnableLSCO
+ 2200              		.syntax unified
+ 2201              		.thumb
+ARM GAS  /tmp/ccXzHHIc.s 			page 71
+
+
+ 2202              		.thumb_func
+ 2204              	HAL_RCCEx_EnableLSCO:
+ 2205              	.LVL224:
+ 2206              	.LFB337:
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  Select the Low Speed clock source to output on LSCO pin (PA2).
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @param  LSCOSource  specifies the Low Speed clock source to output.
+1353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *          This parameter can be one of the following values:
+1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_LSCOSOURCE_LSI  LSI clock selected as LSCO source
+1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *            @arg @ref RCC_LSCOSOURCE_LSE  LSE clock selected as LSCO source
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval None
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2207              		.loc 1 1359 1 is_stmt 1 view -0
+ 2208              		.cfi_startproc
+ 2209              		@ args = 0, pretend = 0, frame = 32
+ 2210              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2211              		.loc 1 1359 1 is_stmt 0 view .LVU726
+ 2212 0000 30B5     		push	{r4, r5, lr}
+ 2213              	.LCFI6:
+ 2214              		.cfi_def_cfa_offset 12
+ 2215              		.cfi_offset 4, -12
+ 2216              		.cfi_offset 5, -8
+ 2217              		.cfi_offset 14, -4
+ 2218 0002 89B0     		sub	sp, sp, #36
+ 2219              	.LCFI7:
+ 2220              		.cfi_def_cfa_offset 48
+ 2221 0004 0546     		mov	r5, r0
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   GPIO_InitTypeDef GPIO_InitStruct;
+ 2222              		.loc 1 1360 3 is_stmt 1 view .LVU727
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   FlagStatus       pwrclkchanged = RESET;
+ 2223              		.loc 1 1361 3 view .LVU728
+ 2224              	.LVL225:
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   FlagStatus       backupchanged = RESET;
+ 2225              		.loc 1 1362 3 view .LVU729
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Check the parameters */
+1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
+ 2226              		.loc 1 1365 3 view .LVU730
+1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* LSCO Pin Clock Enable */
+1368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   __LSCO_CLK_ENABLE();
+ 2227              		.loc 1 1368 3 view .LVU731
+ 2228              	.LBB5:
+ 2229              		.loc 1 1368 3 view .LVU732
+ 2230              		.loc 1 1368 3 view .LVU733
+ 2231 0006 244C     		ldr	r4, .L206
+ 2232 0008 E36C     		ldr	r3, [r4, #76]
+ 2233 000a 43F00103 		orr	r3, r3, #1
+ 2234 000e E364     		str	r3, [r4, #76]
+ 2235              		.loc 1 1368 3 view .LVU734
+ 2236 0010 E36C     		ldr	r3, [r4, #76]
+ 2237 0012 03F00103 		and	r3, r3, #1
+ 2238 0016 0193     		str	r3, [sp, #4]
+ 2239              		.loc 1 1368 3 view .LVU735
+ARM GAS  /tmp/ccXzHHIc.s 			page 72
+
+
+ 2240 0018 019B     		ldr	r3, [sp, #4]
+ 2241              	.LBE5:
+ 2242              		.loc 1 1368 3 view .LVU736
+1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Configure the LSCO pin in analog mode */
+1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   GPIO_InitStruct.Pin = LSCO_PIN;
+ 2243              		.loc 1 1371 3 view .LVU737
+ 2244              		.loc 1 1371 23 is_stmt 0 view .LVU738
+ 2245 001a 0423     		movs	r3, #4
+ 2246 001c 0393     		str	r3, [sp, #12]
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 2247              		.loc 1 1372 3 is_stmt 1 view .LVU739
+ 2248              		.loc 1 1372 24 is_stmt 0 view .LVU740
+ 2249 001e 0323     		movs	r3, #3
+ 2250 0020 0493     		str	r3, [sp, #16]
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ 2251              		.loc 1 1373 3 is_stmt 1 view .LVU741
+ 2252              		.loc 1 1373 25 is_stmt 0 view .LVU742
+ 2253 0022 0223     		movs	r3, #2
+ 2254 0024 0693     		str	r3, [sp, #24]
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2255              		.loc 1 1374 3 is_stmt 1 view .LVU743
+ 2256              		.loc 1 1374 24 is_stmt 0 view .LVU744
+ 2257 0026 0023     		movs	r3, #0
+ 2258 0028 0593     		str	r3, [sp, #20]
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
+ 2259              		.loc 1 1375 3 is_stmt 1 view .LVU745
+ 2260 002a 03A9     		add	r1, sp, #12
+ 2261 002c 4FF09040 		mov	r0, #1207959552
+ 2262              	.LVL226:
+ 2263              		.loc 1 1375 3 is_stmt 0 view .LVU746
+ 2264 0030 FFF7FEFF 		bl	HAL_GPIO_Init
+ 2265              	.LVL227:
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Update LSCOSEL clock source in Backup Domain control register */
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ 2266              		.loc 1 1378 3 is_stmt 1 view .LVU747
+ 2267              		.loc 1 1378 6 is_stmt 0 view .LVU748
+ 2268 0034 A36D     		ldr	r3, [r4, #88]
+ 2269              		.loc 1 1378 5 view .LVU749
+ 2270 0036 13F0805F 		tst	r3, #268435456
+ 2271 003a 1DD1     		bne	.L200
+1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_PWR_CLK_ENABLE();
+ 2272              		.loc 1 1380 5 is_stmt 1 view .LVU750
+ 2273              	.LBB6:
+ 2274              		.loc 1 1380 5 view .LVU751
+ 2275              		.loc 1 1380 5 view .LVU752
+ 2276 003c A26D     		ldr	r2, [r4, #88]
+ 2277 003e 42F08052 		orr	r2, r2, #268435456
+ 2278 0042 A265     		str	r2, [r4, #88]
+ 2279              		.loc 1 1380 5 view .LVU753
+ 2280 0044 A36D     		ldr	r3, [r4, #88]
+ 2281 0046 03F08053 		and	r3, r3, #268435456
+ 2282 004a 0293     		str	r3, [sp, #8]
+ 2283              		.loc 1 1380 5 view .LVU754
+ 2284 004c 029B     		ldr	r3, [sp, #8]
+ARM GAS  /tmp/ccXzHHIc.s 			page 73
+
+
+ 2285              	.LBE6:
+ 2286              		.loc 1 1380 5 view .LVU755
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     pwrclkchanged = SET;
+ 2287              		.loc 1 1381 5 view .LVU756
+ 2288              	.LVL228:
+ 2289              		.loc 1 1381 19 is_stmt 0 view .LVU757
+ 2290 004e 0124     		movs	r4, #1
+ 2291              	.LVL229:
+ 2292              	.L196:
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ 2293              		.loc 1 1383 3 is_stmt 1 view .LVU758
+ 2294              		.loc 1 1383 6 is_stmt 0 view .LVU759
+ 2295 0050 124B     		ldr	r3, .L206+4
+ 2296 0052 1B68     		ldr	r3, [r3]
+ 2297              		.loc 1 1383 5 view .LVU760
+ 2298 0054 13F4807F 		tst	r3, #256
+ 2299 0058 10D0     		beq	.L203
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2300              		.loc 1 1362 20 view .LVU761
+ 2301 005a 0022     		movs	r2, #0
+ 2302              	.LVL230:
+ 2303              	.L197:
+1384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     HAL_PWR_EnableBkUpAccess();
+1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     backupchanged = SET;
+1387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
+ 2304              		.loc 1 1389 3 is_stmt 1 view .LVU762
+ 2305 005c 0E4B     		ldr	r3, .L206
+ 2306 005e D3F89000 		ldr	r0, [r3, #144]
+ 2307 0062 20F04070 		bic	r0, r0, #50331648
+ 2308 0066 2843     		orrs	r0, r0, r5
+ 2309 0068 40F08070 		orr	r0, r0, #16777216
+ 2310 006c C3F89000 		str	r0, [r3, #144]
+1390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(backupchanged == SET)
+ 2311              		.loc 1 1391 3 view .LVU763
+ 2312              		.loc 1 1391 5 is_stmt 0 view .LVU764
+ 2313 0070 42B9     		cbnz	r2, .L204
+ 2314              	.LVL231:
+ 2315              	.L198:
+1392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     HAL_PWR_DisableBkUpAccess();
+1394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(pwrclkchanged == SET)
+ 2316              		.loc 1 1395 3 is_stmt 1 view .LVU765
+ 2317              		.loc 1 1395 5 is_stmt 0 view .LVU766
+ 2318 0072 54B9     		cbnz	r4, .L205
+ 2319              	.L195:
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_PWR_CLK_DISABLE();
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2320              		.loc 1 1399 1 view .LVU767
+ 2321 0074 09B0     		add	sp, sp, #36
+ARM GAS  /tmp/ccXzHHIc.s 			page 74
+
+
+ 2322              	.LCFI8:
+ 2323              		.cfi_remember_state
+ 2324              		.cfi_def_cfa_offset 12
+ 2325              		@ sp needed
+ 2326 0076 30BD     		pop	{r4, r5, pc}
+ 2327              	.LVL232:
+ 2328              	.L200:
+ 2329              	.LCFI9:
+ 2330              		.cfi_restore_state
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   FlagStatus       backupchanged = RESET;
+ 2331              		.loc 1 1361 20 view .LVU768
+ 2332 0078 0024     		movs	r4, #0
+ 2333 007a E9E7     		b	.L196
+ 2334              	.LVL233:
+ 2335              	.L203:
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     backupchanged = SET;
+ 2336              		.loc 1 1385 5 is_stmt 1 view .LVU769
+ 2337 007c FFF7FEFF 		bl	HAL_PWR_EnableBkUpAccess
+ 2338              	.LVL234:
+1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 2339              		.loc 1 1386 5 view .LVU770
+1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 2340              		.loc 1 1386 19 is_stmt 0 view .LVU771
+ 2341 0080 0122     		movs	r2, #1
+ 2342 0082 EBE7     		b	.L197
+ 2343              	.LVL235:
+ 2344              	.L204:
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 2345              		.loc 1 1393 5 is_stmt 1 view .LVU772
+ 2346 0084 FFF7FEFF 		bl	HAL_PWR_DisableBkUpAccess
+ 2347              	.LVL236:
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 2348              		.loc 1 1393 5 is_stmt 0 view .LVU773
+ 2349 0088 F3E7     		b	.L198
+ 2350              	.L205:
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 2351              		.loc 1 1397 5 is_stmt 1 view .LVU774
+ 2352 008a 034A     		ldr	r2, .L206
+ 2353 008c 936D     		ldr	r3, [r2, #88]
+ 2354 008e 23F08053 		bic	r3, r3, #268435456
+ 2355 0092 9365     		str	r3, [r2, #88]
+ 2356              		.loc 1 1399 1 is_stmt 0 view .LVU775
+ 2357 0094 EEE7     		b	.L195
+ 2358              	.L207:
+ 2359 0096 00BF     		.align	2
+ 2360              	.L206:
+ 2361 0098 00100240 		.word	1073876992
+ 2362 009c 00700040 		.word	1073770496
+ 2363              		.cfi_endproc
+ 2364              	.LFE337:
+ 2366              		.section	.text.HAL_RCCEx_DisableLSCO,"ax",%progbits
+ 2367              		.align	1
+ 2368              		.global	HAL_RCCEx_DisableLSCO
+ 2369              		.syntax unified
+ 2370              		.thumb
+ 2371              		.thumb_func
+ 2373              	HAL_RCCEx_DisableLSCO:
+ARM GAS  /tmp/ccXzHHIc.s 			page 75
+
+
+ 2374              	.LFB338:
+1400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  Disable the Low Speed clock output.
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval None
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_DisableLSCO(void)
+1406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2375              		.loc 1 1406 1 is_stmt 1 view -0
+ 2376              		.cfi_startproc
+ 2377              		@ args = 0, pretend = 0, frame = 8
+ 2378              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2379 0000 10B5     		push	{r4, lr}
+ 2380              	.LCFI10:
+ 2381              		.cfi_def_cfa_offset 8
+ 2382              		.cfi_offset 4, -8
+ 2383              		.cfi_offset 14, -4
+ 2384 0002 82B0     		sub	sp, sp, #8
+ 2385              	.LCFI11:
+ 2386              		.cfi_def_cfa_offset 16
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   FlagStatus       pwrclkchanged = RESET;
+ 2387              		.loc 1 1407 3 view .LVU777
+ 2388              	.LVL237:
+1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   FlagStatus       backupchanged = RESET;
+ 2389              		.loc 1 1408 3 view .LVU778
+1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Update LSCOEN bit in Backup Domain control register */
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ 2390              		.loc 1 1411 3 view .LVU779
+ 2391              		.loc 1 1411 6 is_stmt 0 view .LVU780
+ 2392 0004 174B     		ldr	r3, .L219
+ 2393 0006 9B6D     		ldr	r3, [r3, #88]
+ 2394              		.loc 1 1411 5 view .LVU781
+ 2395 0008 13F0805F 		tst	r3, #268435456
+ 2396 000c 1BD1     		bne	.L213
+1412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_PWR_CLK_ENABLE();
+ 2397              		.loc 1 1413 5 is_stmt 1 view .LVU782
+ 2398              	.LBB7:
+ 2399              		.loc 1 1413 5 view .LVU783
+ 2400              		.loc 1 1413 5 view .LVU784
+ 2401 000e 154B     		ldr	r3, .L219
+ 2402 0010 9A6D     		ldr	r2, [r3, #88]
+ 2403 0012 42F08052 		orr	r2, r2, #268435456
+ 2404 0016 9A65     		str	r2, [r3, #88]
+ 2405              		.loc 1 1413 5 view .LVU785
+ 2406 0018 9B6D     		ldr	r3, [r3, #88]
+ 2407 001a 03F08053 		and	r3, r3, #268435456
+ 2408 001e 0193     		str	r3, [sp, #4]
+ 2409              		.loc 1 1413 5 view .LVU786
+ 2410 0020 019B     		ldr	r3, [sp, #4]
+ 2411              	.LBE7:
+ 2412              		.loc 1 1413 5 view .LVU787
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     pwrclkchanged = SET;
+ 2413              		.loc 1 1414 5 view .LVU788
+ 2414              	.LVL238:
+ 2415              		.loc 1 1414 19 is_stmt 0 view .LVU789
+ARM GAS  /tmp/ccXzHHIc.s 			page 76
+
+
+ 2416 0022 0124     		movs	r4, #1
+ 2417              	.LVL239:
+ 2418              	.L209:
+1415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ 2419              		.loc 1 1416 3 is_stmt 1 view .LVU790
+ 2420              		.loc 1 1416 6 is_stmt 0 view .LVU791
+ 2421 0024 104B     		ldr	r3, .L219+4
+ 2422 0026 1B68     		ldr	r3, [r3]
+ 2423              		.loc 1 1416 5 view .LVU792
+ 2424 0028 13F4807F 		tst	r3, #256
+ 2425 002c 0DD0     		beq	.L216
+1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2426              		.loc 1 1408 20 view .LVU793
+ 2427 002e 0021     		movs	r1, #0
+ 2428              	.LVL240:
+ 2429              	.L210:
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Enable access to the backup domain */
+1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     HAL_PWR_EnableBkUpAccess();
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     backupchanged = SET;
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+ 2430              		.loc 1 1423 3 is_stmt 1 view .LVU794
+ 2431 0030 0C4A     		ldr	r2, .L219
+ 2432 0032 D2F89030 		ldr	r3, [r2, #144]
+ 2433 0036 23F08073 		bic	r3, r3, #16777216
+ 2434 003a C2F89030 		str	r3, [r2, #144]
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Restore previous configuration */
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(backupchanged == SET)
+ 2435              		.loc 1 1426 3 view .LVU795
+ 2436              		.loc 1 1426 5 is_stmt 0 view .LVU796
+ 2437 003e 41B9     		cbnz	r1, .L217
+ 2438              	.LVL241:
+ 2439              	.L211:
+1427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Disable access to the backup domain */
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     HAL_PWR_DisableBkUpAccess();
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(pwrclkchanged == SET)
+ 2440              		.loc 1 1431 3 is_stmt 1 view .LVU797
+ 2441              		.loc 1 1431 5 is_stmt 0 view .LVU798
+ 2442 0040 54B9     		cbnz	r4, .L218
+ 2443              	.L208:
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     __HAL_RCC_PWR_CLK_DISABLE();
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2444              		.loc 1 1435 1 view .LVU799
+ 2445 0042 02B0     		add	sp, sp, #8
+ 2446              	.LCFI12:
+ 2447              		.cfi_remember_state
+ 2448              		.cfi_def_cfa_offset 8
+ 2449              		@ sp needed
+ 2450 0044 10BD     		pop	{r4, pc}
+ARM GAS  /tmp/ccXzHHIc.s 			page 77
+
+
+ 2451              	.LVL242:
+ 2452              	.L213:
+ 2453              	.LCFI13:
+ 2454              		.cfi_restore_state
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   FlagStatus       backupchanged = RESET;
+ 2455              		.loc 1 1407 20 view .LVU800
+ 2456 0046 0024     		movs	r4, #0
+ 2457 0048 ECE7     		b	.L209
+ 2458              	.LVL243:
+ 2459              	.L216:
+1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     backupchanged = SET;
+ 2460              		.loc 1 1419 5 is_stmt 1 view .LVU801
+ 2461 004a FFF7FEFF 		bl	HAL_PWR_EnableBkUpAccess
+ 2462              	.LVL244:
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 2463              		.loc 1 1420 5 view .LVU802
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 2464              		.loc 1 1420 19 is_stmt 0 view .LVU803
+ 2465 004e 0121     		movs	r1, #1
+ 2466 0050 EEE7     		b	.L210
+ 2467              	.LVL245:
+ 2468              	.L217:
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 2469              		.loc 1 1429 5 is_stmt 1 view .LVU804
+ 2470 0052 FFF7FEFF 		bl	HAL_PWR_DisableBkUpAccess
+ 2471              	.LVL246:
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 2472              		.loc 1 1429 5 is_stmt 0 view .LVU805
+ 2473 0056 F3E7     		b	.L211
+ 2474              	.L218:
+1433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 2475              		.loc 1 1433 5 is_stmt 1 view .LVU806
+ 2476 0058 024A     		ldr	r2, .L219
+ 2477 005a 936D     		ldr	r3, [r2, #88]
+ 2478 005c 23F08053 		bic	r3, r3, #268435456
+ 2479 0060 9365     		str	r3, [r2, #88]
+ 2480              		.loc 1 1435 1 is_stmt 0 view .LVU807
+ 2481 0062 EEE7     		b	.L208
+ 2482              	.L220:
+ 2483              		.align	2
+ 2484              	.L219:
+ 2485 0064 00100240 		.word	1073876992
+ 2486 0068 00700040 		.word	1073770496
+ 2487              		.cfi_endproc
+ 2488              	.LFE338:
+ 2490              		.section	.text.HAL_RCCEx_CRSConfig,"ax",%progbits
+ 2491              		.align	1
+ 2492              		.global	HAL_RCCEx_CRSConfig
+ 2493              		.syntax unified
+ 2494              		.thumb
+ 2495              		.thumb_func
+ 2497              	HAL_RCCEx_CRSConfig:
+ 2498              	.LVL247:
+ 2499              	.LFB339:
+1436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+ARM GAS  /tmp/ccXzHHIc.s 			page 78
+
+
+1439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @}
+1440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(CRS)
+1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
+1445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  *  @brief  Extended Clock Recovery System Control functions
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  *
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** @verbatim
+1448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  ===============================================================================
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                 ##### Extended Clock Recovery System Control functions  #####
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  ===============================================================================
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     [..]
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as
+1453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       (#) In System clock config, HSI48 needs to be enabled
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       (#) Enable CRS clock in IP MSP init which will use CRS functions
+1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       (#) Call CRS functions as follows:
+1459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           (##) Prepare synchronization configuration necessary for HSI48 calibration
+1460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               (+++) Default values can be set for frequency Error Measurement (reload and error lim
+1461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                         and also HSI48 oscillator smooth trimming.
+1462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
+1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                         directly reload value with target and sychronization frequencies values
+1464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           (##) Call function HAL_RCCEx_CRSConfig which
+1465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               (+++) Resets CRS registers to their default values.
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               (+++) Configures CRS registers with synchronization configuration
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               (+++) Enables automatic calibration and frequency error counter feature
+1468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****            Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
+1469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****            periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
+1470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****            provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
+1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****            precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****            should be used as SYNC signal.
+1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           (##) A polling function is provided to wait for complete synchronization
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
+1476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               (+++) According to CRS status, user can decide to adjust again the calibration or con
+1477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                         application if synchronization is OK
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       (#) User can retrieve information related to synchronization in calling function
+1480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             HAL_RCCEx_CRSGetSynchronizationInfo()
+1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       (#) Regarding synchronization status and synchronization information, user can try a new cali
+1483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****            in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
+1484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****            Note: When the SYNC event is detected during the downcounting phase (before reaching the
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****            it means that the actual frequency is lower than the target (and so, that the TRIM value
+1486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****            incremented), while when it is detected during the upcounting phase it means that the ac
+1487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****            is higher (and that the TRIM value should be decremented).
+1488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interr
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           through CRS Handler (CRS_IRQn/CRS_IRQHandler)
+1491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               (++) Call function HAL_RCCEx_CRSConfig()
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               (++) Enable CRS_IRQn (thanks to NVIC functions)
+1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
+1494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****               (++) Implement CRS status management in the following user callbacks called from
+1495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                    HAL_RCCEx_CRS_IRQHandler():
+ARM GAS  /tmp/ccXzHHIc.s 			page 79
+
+
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                    (+++) HAL_RCCEx_CRS_SyncOkCallback()
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                    (+++) HAL_RCCEx_CRS_SyncWarnCallback()
+1498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                    (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****                    (+++) HAL_RCCEx_CRS_ErrorCallback()
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGene
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****           This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick h
+1503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** @endverbatim
+1505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  * @{
+1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****  */
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  Start automatic synchronization for polling mode
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @param  pInit Pointer on RCC_CRSInitTypeDef structure
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval None
+1512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2500              		.loc 1 1514 1 is_stmt 1 view -0
+ 2501              		.cfi_startproc
+ 2502              		@ args = 0, pretend = 0, frame = 0
+ 2503              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2504              		@ link register save eliminated.
+1515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t value;
+ 2505              		.loc 1 1515 3 view .LVU809
+1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Check the parameters */
+1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
+ 2506              		.loc 1 1518 3 view .LVU810
+1519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
+ 2507              		.loc 1 1519 3 view .LVU811
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
+ 2508              		.loc 1 1520 3 view .LVU812
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
+ 2509              		.loc 1 1521 3 view .LVU813
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
+ 2510              		.loc 1 1522 3 view .LVU814
+1523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
+ 2511              		.loc 1 1523 3 view .LVU815
+1524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* CONFIGURATION */
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Before configuration, reset CRS registers to their default values*/
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   __HAL_RCC_CRS_FORCE_RESET();
+ 2512              		.loc 1 1528 3 view .LVU816
+ 2513 0000 104B     		ldr	r3, .L222
+ 2514 0002 9A6B     		ldr	r2, [r3, #56]
+ 2515 0004 42F48072 		orr	r2, r2, #256
+ 2516 0008 9A63     		str	r2, [r3, #56]
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   __HAL_RCC_CRS_RELEASE_RESET();
+ 2517              		.loc 1 1529 3 view .LVU817
+ 2518 000a 9A6B     		ldr	r2, [r3, #56]
+ 2519 000c 22F48072 		bic	r2, r2, #256
+ 2520 0010 9A63     		str	r2, [r3, #56]
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Set the SYNCDIV[2:0] bits according to Prescaler value */
+ARM GAS  /tmp/ccXzHHIc.s 			page 80
+
+
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Set the SYNCSRC[1:0] bits according to Source value */
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Set the SYNCSPOL bit according to Polarity value */
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
+ 2521              		.loc 1 1534 3 view .LVU818
+ 2522              		.loc 1 1534 17 is_stmt 0 view .LVU819
+ 2523 0012 0368     		ldr	r3, [r0]
+ 2524              		.loc 1 1534 36 view .LVU820
+ 2525 0014 4268     		ldr	r2, [r0, #4]
+ 2526              		.loc 1 1534 29 view .LVU821
+ 2527 0016 1343     		orrs	r3, r3, r2
+ 2528              		.loc 1 1534 52 view .LVU822
+ 2529 0018 8268     		ldr	r2, [r0, #8]
+ 2530              		.loc 1 1534 9 view .LVU823
+ 2531 001a 1A43     		orrs	r2, r2, r3
+ 2532              	.LVL248:
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Set the RELOAD[15:0] bits according to ReloadValue value */
+1536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   value |= pInit->ReloadValue;
+ 2533              		.loc 1 1536 3 is_stmt 1 view .LVU824
+ 2534              		.loc 1 1536 17 is_stmt 0 view .LVU825
+ 2535 001c C368     		ldr	r3, [r0, #12]
+ 2536              		.loc 1 1536 9 view .LVU826
+ 2537 001e 1343     		orrs	r3, r3, r2
+ 2538              	.LVL249:
+1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
+ 2539              		.loc 1 1538 3 is_stmt 1 view .LVU827
+ 2540              		.loc 1 1538 18 is_stmt 0 view .LVU828
+ 2541 0020 0269     		ldr	r2, [r0, #16]
+ 2542              		.loc 1 1538 9 view .LVU829
+ 2543 0022 43EA0242 		orr	r2, r3, r2, lsl #16
+ 2544              	.LVL250:
+1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   WRITE_REG(CRS->CFGR, value);
+ 2545              		.loc 1 1539 3 is_stmt 1 view .LVU830
+ 2546 0026 084B     		ldr	r3, .L222+4
+ 2547 0028 5A60     		str	r2, [r3, #4]
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Adjust HSI48 oscillator smooth trimming */
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
+ 2548              		.loc 1 1543 3 view .LVU831
+ 2549 002a 1A68     		ldr	r2, [r3]
+ 2550              	.LVL251:
+ 2551              		.loc 1 1543 3 is_stmt 0 view .LVU832
+ 2552 002c 22F4FE42 		bic	r2, r2, #32512
+ 2553 0030 4169     		ldr	r1, [r0, #20]
+ 2554 0032 42EA0122 		orr	r2, r2, r1, lsl #8
+ 2555 0036 1A60     		str	r2, [r3]
+ 2556              	.LVL252:
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* START AUTOMATIC SYNCHRONIZATION*/
+1546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Enable Automatic trimming & Frequency error counter */
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
+ 2557              		.loc 1 1548 3 is_stmt 1 view .LVU833
+ 2558 0038 1A68     		ldr	r2, [r3]
+ 2559 003a 42F06002 		orr	r2, r2, #96
+ 2560 003e 1A60     		str	r2, [r3]
+ARM GAS  /tmp/ccXzHHIc.s 			page 81
+
+
+1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2561              		.loc 1 1549 1 is_stmt 0 view .LVU834
+ 2562 0040 7047     		bx	lr
+ 2563              	.L223:
+ 2564 0042 00BF     		.align	2
+ 2565              	.L222:
+ 2566 0044 00100240 		.word	1073876992
+ 2567 0048 00200040 		.word	1073750016
+ 2568              		.cfi_endproc
+ 2569              	.LFE339:
+ 2571              		.section	.text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate,"ax",%progbits
+ 2572              		.align	1
+ 2573              		.global	HAL_RCCEx_CRSSoftwareSynchronizationGenerate
+ 2574              		.syntax unified
+ 2575              		.thumb
+ 2576              		.thumb_func
+ 2578              	HAL_RCCEx_CRSSoftwareSynchronizationGenerate:
+ 2579              	.LFB340:
+1550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  Generate the software synchronization event
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval None
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
+1556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2580              		.loc 1 1556 1 is_stmt 1 view -0
+ 2581              		.cfi_startproc
+ 2582              		@ args = 0, pretend = 0, frame = 0
+ 2583              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2584              		@ link register save eliminated.
+1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+ 2585              		.loc 1 1557 3 view .LVU836
+ 2586 0000 024A     		ldr	r2, .L225
+ 2587 0002 1368     		ldr	r3, [r2]
+ 2588 0004 43F08003 		orr	r3, r3, #128
+ 2589 0008 1360     		str	r3, [r2]
+1558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2590              		.loc 1 1558 1 is_stmt 0 view .LVU837
+ 2591 000a 7047     		bx	lr
+ 2592              	.L226:
+ 2593              		.align	2
+ 2594              	.L225:
+ 2595 000c 00200040 		.word	1073750016
+ 2596              		.cfi_endproc
+ 2597              	.LFE340:
+ 2599              		.section	.text.HAL_RCCEx_CRSGetSynchronizationInfo,"ax",%progbits
+ 2600              		.align	1
+ 2601              		.global	HAL_RCCEx_CRSGetSynchronizationInfo
+ 2602              		.syntax unified
+ 2603              		.thumb
+ 2604              		.thumb_func
+ 2606              	HAL_RCCEx_CRSGetSynchronizationInfo:
+ 2607              	.LVL253:
+ 2608              	.LFB341:
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  Return synchronization info
+ARM GAS  /tmp/ccXzHHIc.s 			page 82
+
+
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval None
+1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2609              		.loc 1 1566 1 is_stmt 1 view -0
+ 2610              		.cfi_startproc
+ 2611              		@ args = 0, pretend = 0, frame = 0
+ 2612              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2613              		@ link register save eliminated.
+1567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Check the parameter */
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   assert_param(pSynchroInfo != (void *)NULL);
+ 2614              		.loc 1 1568 3 view .LVU839
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get the reload value */
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+ 2615              		.loc 1 1571 3 view .LVU840
+ 2616              		.loc 1 1571 32 is_stmt 0 view .LVU841
+ 2617 0000 074B     		ldr	r3, .L228
+ 2618 0002 5A68     		ldr	r2, [r3, #4]
+ 2619 0004 92B2     		uxth	r2, r2
+ 2620              		.loc 1 1571 29 view .LVU842
+ 2621 0006 0260     		str	r2, [r0]
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get HSI48 oscillator smooth trimming */
+1574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+ 2622              		.loc 1 1574 3 is_stmt 1 view .LVU843
+ 2623              		.loc 1 1574 42 is_stmt 0 view .LVU844
+ 2624 0008 1A68     		ldr	r2, [r3]
+ 2625              		.loc 1 1574 73 view .LVU845
+ 2626 000a C2F30622 		ubfx	r2, r2, #8, #7
+ 2627              		.loc 1 1574 39 view .LVU846
+ 2628 000e 4260     		str	r2, [r0, #4]
+1575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get Frequency error capture */
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+ 2629              		.loc 1 1577 3 is_stmt 1 view .LVU847
+ 2630              		.loc 1 1577 37 is_stmt 0 view .LVU848
+ 2631 0010 9A68     		ldr	r2, [r3, #8]
+ 2632              		.loc 1 1577 71 view .LVU849
+ 2633 0012 120C     		lsrs	r2, r2, #16
+ 2634              		.loc 1 1577 34 view .LVU850
+ 2635 0014 8260     		str	r2, [r0, #8]
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get Frequency error direction */
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+ 2636              		.loc 1 1580 3 is_stmt 1 view .LVU851
+ 2637              		.loc 1 1580 39 is_stmt 0 view .LVU852
+ 2638 0016 9B68     		ldr	r3, [r3, #8]
+ 2639 0018 03F40043 		and	r3, r3, #32768
+ 2640              		.loc 1 1580 36 view .LVU853
+ 2641 001c C360     		str	r3, [r0, #12]
+1581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2642              		.loc 1 1581 1 view .LVU854
+ 2643 001e 7047     		bx	lr
+ 2644              	.L229:
+ 2645              		.align	2
+ARM GAS  /tmp/ccXzHHIc.s 			page 83
+
+
+ 2646              	.L228:
+ 2647 0020 00200040 		.word	1073750016
+ 2648              		.cfi_endproc
+ 2649              	.LFE341:
+ 2651              		.section	.text.HAL_RCCEx_CRSWaitSynchronization,"ax",%progbits
+ 2652              		.align	1
+ 2653              		.global	HAL_RCCEx_CRSWaitSynchronization
+ 2654              		.syntax unified
+ 2655              		.thumb
+ 2656              		.thumb_func
+ 2658              	HAL_RCCEx_CRSWaitSynchronization:
+ 2659              	.LVL254:
+ 2660              	.LFB342:
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Wait for CRS Synchronization status.
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @param Timeout  Duration of the timeout
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
+1587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *        frequency.
+1588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @note    If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
+1589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval Combination of Synchronization status
+1590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *          This parameter can be a combination of the following values:
+1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *            @arg @ref RCC_CRS_TIMEOUT
+1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *            @arg @ref RCC_CRS_SYNCOK
+1593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *            @arg @ref RCC_CRS_SYNCWARN
+1594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *            @arg @ref RCC_CRS_SYNCERR
+1595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *            @arg @ref RCC_CRS_SYNCMISS
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *            @arg @ref RCC_CRS_TRIMOVF
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
+1598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
+1599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2661              		.loc 1 1599 1 is_stmt 1 view -0
+ 2662              		.cfi_startproc
+ 2663              		@ args = 0, pretend = 0, frame = 0
+ 2664              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2665              		.loc 1 1599 1 is_stmt 0 view .LVU856
+ 2666 0000 70B5     		push	{r4, r5, r6, lr}
+ 2667              	.LCFI14:
+ 2668              		.cfi_def_cfa_offset 16
+ 2669              		.cfi_offset 4, -16
+ 2670              		.cfi_offset 5, -12
+ 2671              		.cfi_offset 6, -8
+ 2672              		.cfi_offset 14, -4
+ 2673 0002 0546     		mov	r5, r0
+1600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t crsstatus = RCC_CRS_NONE;
+ 2674              		.loc 1 1600 3 is_stmt 1 view .LVU857
+ 2675              	.LVL255:
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t tickstart;
+ 2676              		.loc 1 1601 3 view .LVU858
+1602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get timeout */
+1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   tickstart = HAL_GetTick();
+ 2677              		.loc 1 1604 3 view .LVU859
+ 2678              		.loc 1 1604 15 is_stmt 0 view .LVU860
+ 2679 0004 FFF7FEFF 		bl	HAL_GetTick
+ 2680              	.LVL256:
+ 2681              		.loc 1 1604 15 view .LVU861
+ARM GAS  /tmp/ccXzHHIc.s 			page 84
+
+
+ 2682 0008 0646     		mov	r6, r0
+ 2683              	.LVL257:
+1600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t tickstart;
+ 2684              		.loc 1 1600 12 view .LVU862
+ 2685 000a 0024     		movs	r4, #0
+ 2686 000c 0EE0     		b	.L238
+ 2687              	.LVL258:
+ 2688              	.L243:
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Wait for CRS flag or timeout detection */
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   do
+1608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(Timeout != HAL_MAX_DELAY)
+1610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+1611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ 2689              		.loc 1 1611 7 is_stmt 1 view .LVU863
+ 2690              		.loc 1 1611 12 is_stmt 0 view .LVU864
+ 2691 000e FFF7FEFF 		bl	HAL_GetTick
+ 2692              	.LVL259:
+ 2693              		.loc 1 1611 26 view .LVU865
+ 2694 0012 801B     		subs	r0, r0, r6
+ 2695              		.loc 1 1611 9 view .LVU866
+ 2696 0014 A842     		cmp	r0, r5
+ 2697 0016 02D8     		bhi	.L239
+ 2698              		.loc 1 1611 50 discriminator 1 view .LVU867
+ 2699 0018 5DB9     		cbnz	r5, .L231
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         crsstatus = RCC_CRS_TIMEOUT;
+ 2700              		.loc 1 1613 19 view .LVU868
+ 2701 001a 0124     		movs	r4, #1
+ 2702              	.LVL260:
+ 2703              		.loc 1 1613 19 view .LVU869
+ 2704 001c 09E0     		b	.L231
+ 2705              	.LVL261:
+ 2706              	.L239:
+ 2707              		.loc 1 1613 19 view .LVU870
+ 2708 001e 0124     		movs	r4, #1
+ 2709              	.LVL262:
+ 2710              		.loc 1 1613 19 view .LVU871
+ 2711 0020 07E0     		b	.L231
+ 2712              	.LVL263:
+ 2713              	.L244:
+1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+1616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check CRS SYNCOK flag  */
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
+1618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* CRS SYNC event OK */
+1620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       crsstatus |= RCC_CRS_SYNCOK;
+1621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clear CRS SYNC event OK bit */
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
+1624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check CRS SYNCWARN flag  */
+1627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
+1628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ARM GAS  /tmp/ccXzHHIc.s 			page 85
+
+
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* CRS SYNC warning */
+1630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       crsstatus |= RCC_CRS_SYNCWARN;
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clear CRS SYNCWARN bit */
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check CRS TRIM overflow flag  */
+1637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
+1638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* CRS SYNC Error */
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       crsstatus |= RCC_CRS_TRIMOVF;
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clear CRS Error bit */
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
+1644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check CRS Error flag  */
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* CRS SYNC Error */
+1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       crsstatus |= RCC_CRS_SYNCERR;
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clear CRS Error bit */
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check CRS SYNC Missed flag  */
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
+1658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* CRS SYNC Missed */
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       crsstatus |= RCC_CRS_SYNCMISS;
+1661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clear CRS SYNC Missed bit */
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
+1664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Check CRS Expected SYNC flag  */
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
+1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* frequency error counter reached a zero value */
+1670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
+ 2714              		.loc 1 1670 7 is_stmt 1 discriminator 2 view .LVU872
+ 2715              		.loc 1 1670 7 discriminator 2 view .LVU873
+ 2716              		.loc 1 1670 7 discriminator 2 view .LVU874
+ 2717 0022 214B     		ldr	r3, .L245
+ 2718 0024 0822     		movs	r2, #8
+ 2719 0026 DA60     		str	r2, [r3, #12]
+ 2720              	.L237:
+ 2721              		.loc 1 1670 7 discriminator 4 view .LVU875
+1671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   } while(RCC_CRS_NONE == crsstatus);
+ 2722              		.loc 1 1672 24 discriminator 4 view .LVU876
+ 2723 0028 002C     		cmp	r4, #0
+ 2724 002a 3AD1     		bne	.L242
+ 2725              	.LVL264:
+ 2726              	.L238:
+ARM GAS  /tmp/ccXzHHIc.s 			page 86
+
+
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2727              		.loc 1 1607 3 view .LVU877
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2728              		.loc 1 1609 5 view .LVU878
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2729              		.loc 1 1609 7 is_stmt 0 view .LVU879
+ 2730 002c B5F1FF3F 		cmp	r5, #-1
+ 2731 0030 EDD1     		bne	.L243
+ 2732              	.LVL265:
+ 2733              	.L231:
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2734              		.loc 1 1617 5 is_stmt 1 view .LVU880
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2735              		.loc 1 1617 8 is_stmt 0 view .LVU881
+ 2736 0032 1D4B     		ldr	r3, .L245
+ 2737 0034 9B68     		ldr	r3, [r3, #8]
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2738              		.loc 1 1617 7 view .LVU882
+ 2739 0036 13F0010F 		tst	r3, #1
+ 2740 003a 04D0     		beq	.L232
+1620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2741              		.loc 1 1620 7 is_stmt 1 view .LVU883
+1620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2742              		.loc 1 1620 17 is_stmt 0 view .LVU884
+ 2743 003c 44F00204 		orr	r4, r4, #2
+ 2744              	.LVL266:
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2745              		.loc 1 1623 7 is_stmt 1 view .LVU885
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2746              		.loc 1 1623 7 view .LVU886
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2747              		.loc 1 1623 7 view .LVU887
+ 2748 0040 194B     		ldr	r3, .L245
+ 2749 0042 0122     		movs	r2, #1
+ 2750 0044 DA60     		str	r2, [r3, #12]
+ 2751              	.L232:
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2752              		.loc 1 1623 7 discriminator 4 view .LVU888
+1627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2753              		.loc 1 1627 5 discriminator 4 view .LVU889
+1627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2754              		.loc 1 1627 8 is_stmt 0 discriminator 4 view .LVU890
+ 2755 0046 184B     		ldr	r3, .L245
+ 2756 0048 9B68     		ldr	r3, [r3, #8]
+1627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2757              		.loc 1 1627 7 discriminator 4 view .LVU891
+ 2758 004a 13F0020F 		tst	r3, #2
+ 2759 004e 04D0     		beq	.L233
+1630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2760              		.loc 1 1630 7 is_stmt 1 view .LVU892
+1630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2761              		.loc 1 1630 17 is_stmt 0 view .LVU893
+ 2762 0050 44F00404 		orr	r4, r4, #4
+ 2763              	.LVL267:
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2764              		.loc 1 1633 7 is_stmt 1 view .LVU894
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ARM GAS  /tmp/ccXzHHIc.s 			page 87
+
+
+ 2765              		.loc 1 1633 7 view .LVU895
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2766              		.loc 1 1633 7 view .LVU896
+ 2767 0054 144B     		ldr	r3, .L245
+ 2768 0056 0222     		movs	r2, #2
+ 2769 0058 DA60     		str	r2, [r3, #12]
+ 2770              	.L233:
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2771              		.loc 1 1633 7 discriminator 4 view .LVU897
+1637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2772              		.loc 1 1637 5 discriminator 4 view .LVU898
+1637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2773              		.loc 1 1637 8 is_stmt 0 discriminator 4 view .LVU899
+ 2774 005a 134B     		ldr	r3, .L245
+ 2775 005c 9B68     		ldr	r3, [r3, #8]
+1637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2776              		.loc 1 1637 7 discriminator 4 view .LVU900
+ 2777 005e 13F4806F 		tst	r3, #1024
+ 2778 0062 04D0     		beq	.L234
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2779              		.loc 1 1640 7 is_stmt 1 view .LVU901
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2780              		.loc 1 1640 17 is_stmt 0 view .LVU902
+ 2781 0064 44F02004 		orr	r4, r4, #32
+ 2782              	.LVL268:
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2783              		.loc 1 1643 7 is_stmt 1 view .LVU903
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2784              		.loc 1 1643 7 view .LVU904
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2785              		.loc 1 1643 7 view .LVU905
+ 2786 0068 0F4B     		ldr	r3, .L245
+ 2787 006a 0422     		movs	r2, #4
+ 2788 006c DA60     		str	r2, [r3, #12]
+ 2789              	.L234:
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2790              		.loc 1 1643 7 discriminator 4 view .LVU906
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2791              		.loc 1 1647 5 discriminator 4 view .LVU907
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2792              		.loc 1 1647 8 is_stmt 0 discriminator 4 view .LVU908
+ 2793 006e 0E4B     		ldr	r3, .L245
+ 2794 0070 9B68     		ldr	r3, [r3, #8]
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2795              		.loc 1 1647 7 discriminator 4 view .LVU909
+ 2796 0072 13F4807F 		tst	r3, #256
+ 2797 0076 04D0     		beq	.L235
+1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2798              		.loc 1 1650 7 is_stmt 1 view .LVU910
+1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2799              		.loc 1 1650 17 is_stmt 0 view .LVU911
+ 2800 0078 44F00804 		orr	r4, r4, #8
+ 2801              	.LVL269:
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2802              		.loc 1 1653 7 is_stmt 1 view .LVU912
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2803              		.loc 1 1653 7 view .LVU913
+ARM GAS  /tmp/ccXzHHIc.s 			page 88
+
+
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2804              		.loc 1 1653 7 view .LVU914
+ 2805 007c 0A4B     		ldr	r3, .L245
+ 2806 007e 0422     		movs	r2, #4
+ 2807 0080 DA60     		str	r2, [r3, #12]
+ 2808              	.L235:
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2809              		.loc 1 1653 7 discriminator 4 view .LVU915
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2810              		.loc 1 1657 5 discriminator 4 view .LVU916
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2811              		.loc 1 1657 8 is_stmt 0 discriminator 4 view .LVU917
+ 2812 0082 094B     		ldr	r3, .L245
+ 2813 0084 9B68     		ldr	r3, [r3, #8]
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2814              		.loc 1 1657 7 discriminator 4 view .LVU918
+ 2815 0086 13F4007F 		tst	r3, #512
+ 2816 008a 04D0     		beq	.L236
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2817              		.loc 1 1660 7 is_stmt 1 view .LVU919
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2818              		.loc 1 1660 17 is_stmt 0 view .LVU920
+ 2819 008c 44F01004 		orr	r4, r4, #16
+ 2820              	.LVL270:
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2821              		.loc 1 1663 7 is_stmt 1 view .LVU921
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2822              		.loc 1 1663 7 view .LVU922
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2823              		.loc 1 1663 7 view .LVU923
+ 2824 0090 054B     		ldr	r3, .L245
+ 2825 0092 0422     		movs	r2, #4
+ 2826 0094 DA60     		str	r2, [r3, #12]
+ 2827              	.L236:
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 2828              		.loc 1 1663 7 discriminator 4 view .LVU924
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2829              		.loc 1 1667 5 discriminator 4 view .LVU925
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2830              		.loc 1 1667 8 is_stmt 0 discriminator 4 view .LVU926
+ 2831 0096 044B     		ldr	r3, .L245
+ 2832 0098 9B68     		ldr	r3, [r3, #8]
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2833              		.loc 1 1667 7 discriminator 4 view .LVU927
+ 2834 009a 13F0080F 		tst	r3, #8
+ 2835 009e C3D0     		beq	.L237
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2836              		.loc 1 1667 7 discriminator 4 view .LVU928
+ 2837 00a0 BFE7     		b	.L244
+ 2838              	.L242:
+1673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   return crsstatus;
+ 2839              		.loc 1 1674 3 is_stmt 1 view .LVU929
+1675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2840              		.loc 1 1675 1 is_stmt 0 view .LVU930
+ 2841 00a2 2046     		mov	r0, r4
+ 2842 00a4 70BD     		pop	{r4, r5, r6, pc}
+ARM GAS  /tmp/ccXzHHIc.s 			page 89
+
+
+ 2843              	.LVL271:
+ 2844              	.L246:
+ 2845              		.loc 1 1675 1 view .LVU931
+ 2846 00a6 00BF     		.align	2
+ 2847              	.L245:
+ 2848 00a8 00200040 		.word	1073750016
+ 2849              		.cfi_endproc
+ 2850              	.LFE342:
+ 2852              		.section	.text.HAL_RCCEx_CRS_SyncOkCallback,"ax",%progbits
+ 2853              		.align	1
+ 2854              		.weak	HAL_RCCEx_CRS_SyncOkCallback
+ 2855              		.syntax unified
+ 2856              		.thumb
+ 2857              		.thumb_func
+ 2859              	HAL_RCCEx_CRS_SyncOkCallback:
+ 2860              	.LFB344:
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief Handle the Clock Recovery System interrupt request.
+1679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval None
+1680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_CRS_IRQHandler(void)
+1682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+1683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t crserror = RCC_CRS_NONE;
+1684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get current IT flags and IT sources values */
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t itflags = READ_REG(CRS->ISR);
+1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t itsources = READ_REG(CRS->CR);
+1687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Check CRS SYNCOK flag  */
+1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
+1690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Clear CRS SYNC event OK flag */
+1692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+1693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* user callback */
+1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     HAL_RCCEx_CRS_SyncOkCallback();
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Check CRS SYNCWARN flag  */
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* Clear CRS SYNCWARN flag */
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* user callback */
+1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     HAL_RCCEx_CRS_SyncWarnCallback();
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Check CRS Expected SYNC flag  */
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
+1708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* frequency error counter reached a zero value */
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     /* user callback */
+1713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     HAL_RCCEx_CRS_ExpectedSyncCallback();
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Check CRS Error flags  */
+1716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   else
+ARM GAS  /tmp/ccXzHHIc.s 			page 90
+
+
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
+1719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         crserror |= RCC_CRS_SYNCERR;
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         crserror |= RCC_CRS_SYNCMISS;
+1727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
+1729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****         crserror |= RCC_CRS_TRIMOVF;
+1731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+1732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* Clear CRS Error flags */
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+1735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       /* user error callback */
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       HAL_RCCEx_CRS_ErrorCallback(crserror);
+1738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+1740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
+1744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval none
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2861              		.loc 1 1747 1 is_stmt 1 view -0
+ 2862              		.cfi_startproc
+ 2863              		@ args = 0, pretend = 0, frame = 0
+ 2864              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2865              		@ link register save eliminated.
+1748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
+1750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****    */
+1751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2866              		.loc 1 1751 1 view .LVU933
+ 2867 0000 7047     		bx	lr
+ 2868              		.cfi_endproc
+ 2869              	.LFE344:
+ 2871              		.section	.text.HAL_RCCEx_CRS_SyncWarnCallback,"ax",%progbits
+ 2872              		.align	1
+ 2873              		.weak	HAL_RCCEx_CRS_SyncWarnCallback
+ 2874              		.syntax unified
+ 2875              		.thumb
+ 2876              		.thumb_func
+ 2878              	HAL_RCCEx_CRS_SyncWarnCallback:
+ 2879              	.LFB345:
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval none
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+ARM GAS  /tmp/ccXzHHIc.s 			page 91
+
+
+1757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2880              		.loc 1 1758 1 view -0
+ 2881              		.cfi_startproc
+ 2882              		@ args = 0, pretend = 0, frame = 0
+ 2883              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2884              		@ link register save eliminated.
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****    */
+1762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2885              		.loc 1 1762 1 view .LVU935
+ 2886 0000 7047     		bx	lr
+ 2887              		.cfi_endproc
+ 2888              	.LFE345:
+ 2890              		.section	.text.HAL_RCCEx_CRS_ExpectedSyncCallback,"ax",%progbits
+ 2891              		.align	1
+ 2892              		.weak	HAL_RCCEx_CRS_ExpectedSyncCallback
+ 2893              		.syntax unified
+ 2894              		.thumb
+ 2895              		.thumb_func
+ 2897              	HAL_RCCEx_CRS_ExpectedSyncCallback:
+ 2898              	.LFB346:
+1763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval none
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2899              		.loc 1 1769 1 view -0
+ 2900              		.cfi_startproc
+ 2901              		@ args = 0, pretend = 0, frame = 0
+ 2902              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2903              		@ link register save eliminated.
+1770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****    */
+1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2904              		.loc 1 1773 1 view .LVU937
+ 2905 0000 7047     		bx	lr
+ 2906              		.cfi_endproc
+ 2907              	.LFE346:
+ 2909              		.section	.text.HAL_RCCEx_CRS_ErrorCallback,"ax",%progbits
+ 2910              		.align	1
+ 2911              		.weak	HAL_RCCEx_CRS_ErrorCallback
+ 2912              		.syntax unified
+ 2913              		.thumb
+ 2914              		.thumb_func
+ 2916              	HAL_RCCEx_CRS_ErrorCallback:
+ 2917              	.LVL272:
+ 2918              	.LFB347:
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
+1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @brief  RCCEx Clock Recovery System Error interrupt callback.
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @param  Error Combination of Error status.
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *         This parameter can be a combination of the following values:
+ARM GAS  /tmp/ccXzHHIc.s 			page 92
+
+
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *           @arg @ref RCC_CRS_SYNCERR
+1780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *           @arg @ref RCC_CRS_SYNCMISS
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   *           @arg @ref RCC_CRS_TRIMOVF
+1782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   * @retval none
+1783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   */
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
+ 2919              		.loc 1 1785 1 view -0
+ 2920              		.cfi_startproc
+ 2921              		@ args = 0, pretend = 0, frame = 0
+ 2922              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2923              		@ link register save eliminated.
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Prevent unused argument(s) compilation warning */
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   UNUSED(Error);
+ 2924              		.loc 1 1787 3 view .LVU939
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****             the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****    */
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
+ 2925              		.loc 1 1792 1 is_stmt 0 view .LVU940
+ 2926 0000 7047     		bx	lr
+ 2927              		.cfi_endproc
+ 2928              	.LFE347:
+ 2930              		.section	.text.HAL_RCCEx_CRS_IRQHandler,"ax",%progbits
+ 2931              		.align	1
+ 2932              		.global	HAL_RCCEx_CRS_IRQHandler
+ 2933              		.syntax unified
+ 2934              		.thumb
+ 2935              		.thumb_func
+ 2937              	HAL_RCCEx_CRS_IRQHandler:
+ 2938              	.LFB343:
+1682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t crserror = RCC_CRS_NONE;
+ 2939              		.loc 1 1682 1 is_stmt 1 view -0
+ 2940              		.cfi_startproc
+ 2941              		@ args = 0, pretend = 0, frame = 0
+ 2942              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2943 0000 08B5     		push	{r3, lr}
+ 2944              	.LCFI15:
+ 2945              		.cfi_def_cfa_offset 8
+ 2946              		.cfi_offset 3, -8
+ 2947              		.cfi_offset 14, -4
+1683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   /* Get current IT flags and IT sources values */
+ 2948              		.loc 1 1683 3 view .LVU942
+ 2949              	.LVL273:
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t itsources = READ_REG(CRS->CR);
+ 2950              		.loc 1 1685 3 view .LVU943
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   uint32_t itsources = READ_REG(CRS->CR);
+ 2951              		.loc 1 1685 12 is_stmt 0 view .LVU944
+ 2952 0002 204A     		ldr	r2, .L264
+ 2953 0004 9368     		ldr	r3, [r2, #8]
+ 2954              	.LVL274:
+1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2955              		.loc 1 1686 3 is_stmt 1 view .LVU945
+1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 2956              		.loc 1 1686 12 is_stmt 0 view .LVU946
+ 2957 0006 1268     		ldr	r2, [r2]
+ARM GAS  /tmp/ccXzHHIc.s 			page 93
+
+
+ 2958              	.LVL275:
+1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2959              		.loc 1 1689 3 is_stmt 1 view .LVU947
+1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2960              		.loc 1 1689 5 is_stmt 0 view .LVU948
+ 2961 0008 13F0010F 		tst	r3, #1
+ 2962 000c 02D0     		beq	.L252
+1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2963              		.loc 1 1689 46 discriminator 1 view .LVU949
+ 2964 000e 12F0010F 		tst	r2, #1
+ 2965 0012 25D1     		bne	.L261
+ 2966              	.L252:
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2967              		.loc 1 1698 8 is_stmt 1 view .LVU950
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2968              		.loc 1 1698 10 is_stmt 0 view .LVU951
+ 2969 0014 13F0020F 		tst	r3, #2
+ 2970 0018 02D0     		beq	.L254
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2971              		.loc 1 1698 53 discriminator 1 view .LVU952
+ 2972 001a 12F0020F 		tst	r2, #2
+ 2973 001e 25D1     		bne	.L262
+ 2974              	.L254:
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2975              		.loc 1 1707 8 is_stmt 1 view .LVU953
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2976              		.loc 1 1707 10 is_stmt 0 view .LVU954
+ 2977 0020 13F0080F 		tst	r3, #8
+ 2978 0024 02D0     		beq	.L255
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   {
+ 2979              		.loc 1 1707 50 discriminator 1 view .LVU955
+ 2980 0026 12F0080F 		tst	r2, #8
+ 2981 002a 25D1     		bne	.L263
+ 2982              	.L255:
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2983              		.loc 1 1718 5 is_stmt 1 view .LVU956
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2984              		.loc 1 1718 7 is_stmt 0 view .LVU957
+ 2985 002c 13F0040F 		tst	r3, #4
+ 2986 0030 1BD0     		beq	.L251
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     {
+ 2987              		.loc 1 1718 45 discriminator 1 view .LVU958
+ 2988 0032 12F0040F 		tst	r2, #4
+ 2989 0036 18D0     		beq	.L251
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 2990              		.loc 1 1720 7 is_stmt 1 view .LVU959
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 2991              		.loc 1 1720 9 is_stmt 0 view .LVU960
+ 2992 0038 13F48070 		ands	r0, r3, #256
+ 2993 003c 00D0     		beq	.L256
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 2994              		.loc 1 1722 18 view .LVU961
+ 2995 003e 0820     		movs	r0, #8
+ 2996              	.L256:
+ 2997              	.LVL276:
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 2998              		.loc 1 1724 7 is_stmt 1 view .LVU962
+ARM GAS  /tmp/ccXzHHIc.s 			page 94
+
+
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 2999              		.loc 1 1724 9 is_stmt 0 view .LVU963
+ 3000 0040 13F4007F 		tst	r3, #512
+ 3001 0044 01D0     		beq	.L257
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 3002              		.loc 1 1726 9 is_stmt 1 view .LVU964
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 3003              		.loc 1 1726 18 is_stmt 0 view .LVU965
+ 3004 0046 40F01000 		orr	r0, r0, #16
+ 3005              	.LVL277:
+ 3006              	.L257:
+1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 3007              		.loc 1 1728 7 is_stmt 1 view .LVU966
+1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       {
+ 3008              		.loc 1 1728 9 is_stmt 0 view .LVU967
+ 3009 004a 13F4806F 		tst	r3, #1024
+ 3010 004e 01D0     		beq	.L258
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 3011              		.loc 1 1730 9 is_stmt 1 view .LVU968
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****       }
+ 3012              		.loc 1 1730 18 is_stmt 0 view .LVU969
+ 3013 0050 40F02000 		orr	r0, r0, #32
+ 3014              	.LVL278:
+ 3015              	.L258:
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3016              		.loc 1 1734 7 is_stmt 1 view .LVU970
+ 3017 0054 0B4B     		ldr	r3, .L264
+ 3018              	.LVL279:
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3019              		.loc 1 1734 7 is_stmt 0 view .LVU971
+ 3020 0056 0422     		movs	r2, #4
+ 3021              	.LVL280:
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3022              		.loc 1 1734 7 view .LVU972
+ 3023 0058 DA60     		str	r2, [r3, #12]
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****     }
+ 3024              		.loc 1 1737 7 is_stmt 1 view .LVU973
+ 3025 005a FFF7FEFF 		bl	HAL_RCCEx_CRS_ErrorCallback
+ 3026              	.LVL281:
+1740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3027              		.loc 1 1740 1 is_stmt 0 view .LVU974
+ 3028 005e 04E0     		b	.L251
+ 3029              	.LVL282:
+ 3030              	.L261:
+1692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3031              		.loc 1 1692 5 is_stmt 1 view .LVU975
+ 3032 0060 084B     		ldr	r3, .L264
+ 3033              	.LVL283:
+1692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3034              		.loc 1 1692 5 is_stmt 0 view .LVU976
+ 3035 0062 0122     		movs	r2, #1
+ 3036              	.LVL284:
+1692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3037              		.loc 1 1692 5 view .LVU977
+ 3038 0064 DA60     		str	r2, [r3, #12]
+1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 3039              		.loc 1 1695 5 is_stmt 1 view .LVU978
+ARM GAS  /tmp/ccXzHHIc.s 			page 95
+
+
+ 3040 0066 FFF7FEFF 		bl	HAL_RCCEx_CRS_SyncOkCallback
+ 3041              	.LVL285:
+ 3042              	.L251:
+1740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3043              		.loc 1 1740 1 is_stmt 0 view .LVU979
+ 3044 006a 08BD     		pop	{r3, pc}
+ 3045              	.LVL286:
+ 3046              	.L262:
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3047              		.loc 1 1701 5 is_stmt 1 view .LVU980
+ 3048 006c 054B     		ldr	r3, .L264
+ 3049              	.LVL287:
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3050              		.loc 1 1701 5 is_stmt 0 view .LVU981
+ 3051 006e 0222     		movs	r2, #2
+ 3052              	.LVL288:
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3053              		.loc 1 1701 5 view .LVU982
+ 3054 0070 DA60     		str	r2, [r3, #12]
+1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 3055              		.loc 1 1704 5 is_stmt 1 view .LVU983
+ 3056 0072 FFF7FEFF 		bl	HAL_RCCEx_CRS_SyncWarnCallback
+ 3057              	.LVL289:
+ 3058 0076 F8E7     		b	.L251
+ 3059              	.LVL290:
+ 3060              	.L263:
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3061              		.loc 1 1710 5 view .LVU984
+ 3062 0078 024B     		ldr	r3, .L264
+ 3063              	.LVL291:
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3064              		.loc 1 1710 5 is_stmt 0 view .LVU985
+ 3065 007a 0822     		movs	r2, #8
+ 3066              	.LVL292:
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** 
+ 3067              		.loc 1 1710 5 view .LVU986
+ 3068 007c DA60     		str	r2, [r3, #12]
+1713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****   }
+ 3069              		.loc 1 1713 5 is_stmt 1 view .LVU987
+ 3070 007e FFF7FEFF 		bl	HAL_RCCEx_CRS_ExpectedSyncCallback
+ 3071              	.LVL293:
+ 3072 0082 F2E7     		b	.L251
+ 3073              	.L265:
+ 3074              		.align	2
+ 3075              	.L264:
+ 3076 0084 00200040 		.word	1073750016
+ 3077              		.cfi_endproc
+ 3078              	.LFE343:
+ 3080              		.text
+ 3081              	.Letext0:
+ 3082              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 3083              		.file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 3084              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 3085              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 3086              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"
+ 3087              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"
+ 3088              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h"
+ARM GAS  /tmp/ccXzHHIc.s 			page 96
+
+
+ 3089              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"
+ 3090              		.file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ARM GAS  /tmp/ccXzHHIc.s 			page 97
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_rcc_ex.c
+     /tmp/ccXzHHIc.s:21     .text.HAL_RCCEx_PeriphCLKConfig:00000000 $t
+     /tmp/ccXzHHIc.s:27     .text.HAL_RCCEx_PeriphCLKConfig:00000000 HAL_RCCEx_PeriphCLKConfig
+     /tmp/ccXzHHIc.s:548    .text.HAL_RCCEx_PeriphCLKConfig:000002c8 $d
+     /tmp/ccXzHHIc.s:552    .text.HAL_RCCEx_PeriphCLKConfig:000002d0 $t
+     /tmp/ccXzHHIc.s:566    .text.HAL_RCCEx_GetPeriphCLKConfig:00000000 $t
+     /tmp/ccXzHHIc.s:572    .text.HAL_RCCEx_GetPeriphCLKConfig:00000000 HAL_RCCEx_GetPeriphCLKConfig
+     /tmp/ccXzHHIc.s:686    .text.HAL_RCCEx_GetPeriphCLKConfig:000000a8 $d
+     /tmp/ccXzHHIc.s:692    .text.HAL_RCCEx_GetPeriphCLKFreq:00000000 $t
+     /tmp/ccXzHHIc.s:698    .text.HAL_RCCEx_GetPeriphCLKFreq:00000000 HAL_RCCEx_GetPeriphCLKFreq
+     /tmp/ccXzHHIc.s:766    .text.HAL_RCCEx_GetPeriphCLKFreq:00000050 $d
+     /tmp/ccXzHHIc.s:799    .text.HAL_RCCEx_GetPeriphCLKFreq:00000090 $t
+     /tmp/ccXzHHIc.s:1147   .text.HAL_RCCEx_GetPeriphCLKFreq:0000027c $d
+     /tmp/ccXzHHIc.s:1154   .text.HAL_RCCEx_GetPeriphCLKFreq:00000288 $t
+     /tmp/ccXzHHIc.s:1777   .text.HAL_RCCEx_GetPeriphCLKFreq:00000548 $d
+     /tmp/ccXzHHIc.s:1782   .text.HAL_RCCEx_GetPeriphCLKFreq:0000054c $t
+     /tmp/ccXzHHIc.s:2024   .text.HAL_RCCEx_GetPeriphCLKFreq:0000062c $d
+     /tmp/ccXzHHIc.s:2033   .text.HAL_RCCEx_EnableLSECSS:00000000 $t
+     /tmp/ccXzHHIc.s:2039   .text.HAL_RCCEx_EnableLSECSS:00000000 HAL_RCCEx_EnableLSECSS
+     /tmp/ccXzHHIc.s:2056   .text.HAL_RCCEx_EnableLSECSS:00000010 $d
+     /tmp/ccXzHHIc.s:2061   .text.HAL_RCCEx_DisableLSECSS:00000000 $t
+     /tmp/ccXzHHIc.s:2067   .text.HAL_RCCEx_DisableLSECSS:00000000 HAL_RCCEx_DisableLSECSS
+     /tmp/ccXzHHIc.s:2088   .text.HAL_RCCEx_DisableLSECSS:00000018 $d
+     /tmp/ccXzHHIc.s:2093   .text.HAL_RCCEx_EnableLSECSS_IT:00000000 $t
+     /tmp/ccXzHHIc.s:2099   .text.HAL_RCCEx_EnableLSECSS_IT:00000000 HAL_RCCEx_EnableLSECSS_IT
+     /tmp/ccXzHHIc.s:2129   .text.HAL_RCCEx_EnableLSECSS_IT:0000002c $d
+     /tmp/ccXzHHIc.s:2134   .text.HAL_RCCEx_LSECSS_Callback:00000000 $t
+     /tmp/ccXzHHIc.s:2140   .text.HAL_RCCEx_LSECSS_Callback:00000000 HAL_RCCEx_LSECSS_Callback
+     /tmp/ccXzHHIc.s:2153   .text.HAL_RCCEx_LSECSS_IRQHandler:00000000 $t
+     /tmp/ccXzHHIc.s:2159   .text.HAL_RCCEx_LSECSS_IRQHandler:00000000 HAL_RCCEx_LSECSS_IRQHandler
+     /tmp/ccXzHHIc.s:2193   .text.HAL_RCCEx_LSECSS_IRQHandler:0000001c $d
+     /tmp/ccXzHHIc.s:2198   .text.HAL_RCCEx_EnableLSCO:00000000 $t
+     /tmp/ccXzHHIc.s:2204   .text.HAL_RCCEx_EnableLSCO:00000000 HAL_RCCEx_EnableLSCO
+     /tmp/ccXzHHIc.s:2361   .text.HAL_RCCEx_EnableLSCO:00000098 $d
+     /tmp/ccXzHHIc.s:2367   .text.HAL_RCCEx_DisableLSCO:00000000 $t
+     /tmp/ccXzHHIc.s:2373   .text.HAL_RCCEx_DisableLSCO:00000000 HAL_RCCEx_DisableLSCO
+     /tmp/ccXzHHIc.s:2485   .text.HAL_RCCEx_DisableLSCO:00000064 $d
+     /tmp/ccXzHHIc.s:2491   .text.HAL_RCCEx_CRSConfig:00000000 $t
+     /tmp/ccXzHHIc.s:2497   .text.HAL_RCCEx_CRSConfig:00000000 HAL_RCCEx_CRSConfig
+     /tmp/ccXzHHIc.s:2566   .text.HAL_RCCEx_CRSConfig:00000044 $d
+     /tmp/ccXzHHIc.s:2572   .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate:00000000 $t
+     /tmp/ccXzHHIc.s:2578   .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate:00000000 HAL_RCCEx_CRSSoftwareSynchronizationGenerate
+     /tmp/ccXzHHIc.s:2595   .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate:0000000c $d
+     /tmp/ccXzHHIc.s:2600   .text.HAL_RCCEx_CRSGetSynchronizationInfo:00000000 $t
+     /tmp/ccXzHHIc.s:2606   .text.HAL_RCCEx_CRSGetSynchronizationInfo:00000000 HAL_RCCEx_CRSGetSynchronizationInfo
+     /tmp/ccXzHHIc.s:2647   .text.HAL_RCCEx_CRSGetSynchronizationInfo:00000020 $d
+     /tmp/ccXzHHIc.s:2652   .text.HAL_RCCEx_CRSWaitSynchronization:00000000 $t
+     /tmp/ccXzHHIc.s:2658   .text.HAL_RCCEx_CRSWaitSynchronization:00000000 HAL_RCCEx_CRSWaitSynchronization
+     /tmp/ccXzHHIc.s:2848   .text.HAL_RCCEx_CRSWaitSynchronization:000000a8 $d
+     /tmp/ccXzHHIc.s:2853   .text.HAL_RCCEx_CRS_SyncOkCallback:00000000 $t
+     /tmp/ccXzHHIc.s:2859   .text.HAL_RCCEx_CRS_SyncOkCallback:00000000 HAL_RCCEx_CRS_SyncOkCallback
+     /tmp/ccXzHHIc.s:2872   .text.HAL_RCCEx_CRS_SyncWarnCallback:00000000 $t
+     /tmp/ccXzHHIc.s:2878   .text.HAL_RCCEx_CRS_SyncWarnCallback:00000000 HAL_RCCEx_CRS_SyncWarnCallback
+     /tmp/ccXzHHIc.s:2891   .text.HAL_RCCEx_CRS_ExpectedSyncCallback:00000000 $t
+     /tmp/ccXzHHIc.s:2897   .text.HAL_RCCEx_CRS_ExpectedSyncCallback:00000000 HAL_RCCEx_CRS_ExpectedSyncCallback
+     /tmp/ccXzHHIc.s:2910   .text.HAL_RCCEx_CRS_ErrorCallback:00000000 $t
+ARM GAS  /tmp/ccXzHHIc.s 			page 98
+
+
+     /tmp/ccXzHHIc.s:2916   .text.HAL_RCCEx_CRS_ErrorCallback:00000000 HAL_RCCEx_CRS_ErrorCallback
+     /tmp/ccXzHHIc.s:2931   .text.HAL_RCCEx_CRS_IRQHandler:00000000 $t
+     /tmp/ccXzHHIc.s:2937   .text.HAL_RCCEx_CRS_IRQHandler:00000000 HAL_RCCEx_CRS_IRQHandler
+     /tmp/ccXzHHIc.s:3076   .text.HAL_RCCEx_CRS_IRQHandler:00000084 $d
+
+UNDEFINED SYMBOLS
+HAL_GetTick
+HAL_RCC_GetPCLK2Freq
+HAL_RCC_GetSysClockFreq
+HAL_RCC_GetPCLK1Freq
+HAL_GPIO_Init
+HAL_PWR_EnableBkUpAccess
+HAL_PWR_DisableBkUpAccess
diff --git a/squeow_sw/build/stm32g4xx_hal_rcc_ex.o b/squeow_sw/build/stm32g4xx_hal_rcc_ex.o
new file mode 100644
index 0000000000000000000000000000000000000000..a87cc26da24f5a3e82b7ba4ad323838e0a454ecd
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diff --git a/squeow_sw/build/stm32g4xx_hal_tim.d b/squeow_sw/build/stm32g4xx_hal_tim.d
new file mode 100644
index 0000000..4f8e955
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_tim.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_tim.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_tim.lst b/squeow_sw/build/stm32g4xx_hal_tim.lst
new file mode 100644
index 0000000..138ef5f
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_tim.lst
@@ -0,0 +1,31027 @@
+ARM GAS  /tmp/cc0wMqvE.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_tim.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c"
+  20              		.section	.text.TIM_OC1_SetConfig,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	TIM_OC1_SetConfig:
+  27              	.LVL0:
+  28              	.LFB434:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @file    stm32g4xx_hal_tim.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief   TIM HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          functionalities of the Timer (TIM) peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Time Base Initialization
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Time Base Start
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Time Base Start Interruption
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Time Base Start DMA
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Output Compare/PWM Initialization
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Output Compare/PWM Channel Configuration
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Output Compare/PWM  Start
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Output Compare/PWM  Start Interruption
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Output Compare/PWM Start DMA
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Input Capture Initialization
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Input Capture Channel Configuration
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Input Capture Start
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Input Capture Start Interruption
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Input Capture Start DMA
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM One Pulse Initialization
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM One Pulse Channel Configuration
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM One Pulse Start
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Encoder Interface Initialization
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Encoder Interface Start
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Encoder Interface Start Interruption
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM Encoder Interface Start DMA
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + Commutation Event configuration with Interruption and DMA
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM OCRef clear configuration
+ARM GAS  /tmp/cc0wMqvE.s 			page 2
+
+
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *           + TIM External Clock configuration
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ******************************************************************************
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @attention
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * Copyright (c) 2019 STMicroelectronics.
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * All rights reserved.
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * in the root directory of this software component.
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ******************************************************************************
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   @verbatim
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       ##### TIMER Generic features #####
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..] The Timer features include:
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****        (#) 16-bit up, down, up/down auto-reload counter.
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            counter clock frequency either by any factor between 1 and 65536.
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****        (#) Up to 4 independent channels for:
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) Input Capture
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) Output Compare
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) PWM generation (Edge and Center-aligned Mode)
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) One-pulse mode output
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****        (#) Synchronization circuit to control the timer with external signals and to interconnect
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             several timers together.
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****        (#) Supports incremental encoder for positioning purposes
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             ##### How to use this driver #####
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     [..]
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****      (#) Initialize the TIM low level resources by implementing the following functions
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****          depending on the selected feature:
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) Time Base : HAL_TIM_Base_MspInit()
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) Input Capture : HAL_TIM_IC_MspInit()
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) Output Compare : HAL_TIM_OC_MspInit()
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) PWM generation : HAL_TIM_PWM_MspInit()
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****      (#) Initialize the TIM low level resources :
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         (##) TIM pins configuration
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             (+++) Enable the clock for the TIM GPIOs using the following function:
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              __HAL_RCC_GPIOx_CLK_ENABLE();
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****      (#) The external Clock can be configured, if needed (the default clock is the
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****          internal clock from the APBx), using the following function:
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****          HAL_TIM_ConfigClockSource, the clock configuration should be done before
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****          any start function.
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****      (#) Configure the TIM in the desired functioning mode using one of the
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****        Initialization function of this driver:
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****        (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnComp
+ARM GAS  /tmp/cc0wMqvE.s 			page 3
+
+
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             to use the Timer to generate an Output Compare signal.
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             PWM signal.
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             external signal.
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             in One Pulse Mode.
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****      (#) Activate the TIM peripheral using one of the start functions depending from the feature us
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****      (#) The DMA Burst is managed with the two following functions:
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****          HAL_TIM_DMABurst_WriteStart()
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****          HAL_TIM_DMABurst_ReadStart()
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     *** Callback registration ***
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   =============================================
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   allows the user to configure dynamically the driver callbacks.
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   Use Function HAL_TIM_RegisterCallback() to register a callback.
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   the Callback ID and a pointer to the user callback function.
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   weak function.
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   and the Callback ID.
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   These functions allow to register/unregister following callbacks:
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+ARM GAS  /tmp/cc0wMqvE.s 			page 4
+
+
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) TriggerCallback                   : TIM Trigger Callback.
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) IC_CaptureCallback                : TIM Input Capture Callback.
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) ErrorCallback                     : TIM Error Callback.
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) CommutationCallback               : TIM Commutation Callback.
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) BreakCallback                     : TIM Break Callback.
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Break2Callback                    : TIM Break2 Callback.
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) EncoderIndexCallback              : TIM Encoder Index Callback.
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) DirectionChangeCallback           : TIM Direction Change Callback
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) IndexErrorCallback                : TIM Index Error Callback.
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) TransitionErrorCallback           : TIM Transition Error Callback
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** By default, after the Init and when the state is HAL_TIM_STATE_RESET
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** all interrupt callbacks are set to the corresponding weak functions:
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   functionalities in the Init / DeInit only when these callbacks are null
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     Exception done MspInit / MspDeInit that can be registered / unregistered
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   In that case first register the MspInit/MspDeInit user callbacks
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       not defined, the callback registration feature is not available and all callbacks
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       are set to the corresponding weak functions.
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   @endverbatim
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ******************************************************************************
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /* Includes ------------------------------------------------------------------*/
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #include "stm32g4xx_hal.h"
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @addtogroup STM32G4xx_HAL_Driver
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM TIM
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief TIM HAL module driver
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 5
+
+
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #ifdef HAL_TIM_MODULE_ENABLED
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /* Private typedef -----------------------------------------------------------*/
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /* Private define ------------------------------------------------------------*/
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @addtogroup TIM_Private_Constants
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /* Private macros ------------------------------------------------------------*/
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /* Private variables ---------------------------------------------------------*/
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /* Private function prototypes -----------------------------------------------*/
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @addtogroup TIM_Private_Functions
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                               uint32_t TIM_ICFilter);
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                               uint32_t TIM_ICFilter);
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                               uint32_t TIM_ICFilter);
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                                   TIM_SlaveConfigTypeDef *sSlaveConfig);
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /* Exported functions --------------------------------------------------------*/
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions TIM Exported Functions
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *  @brief    Time Base functions
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @verbatim
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****               ##### Time Base functions #####
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     This section provides functions allowing to:
+ARM GAS  /tmp/cc0wMqvE.s 			page 6
+
+
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Initialize and configure the TIM base.
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) De-initialize the TIM base.
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the Time Base.
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the Time Base.
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the Time Base and enable interrupt.
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the Time Base and disable interrupt.
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the Time Base and enable DMA transfer.
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the Time Base and disable DMA transfer.
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @endverbatim
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM Time base Unit according to the specified
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         requires a timer reset to avoid unexpected direction
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         due to DIR bit readonly in center aligned mode.
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim == NULL)
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Allocate lock resource and initialize it */
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Lock = HAL_UNLOCKED;
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset interrupt callbacks to legacy weak callbacks */
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_ResetCallback(htim);
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (htim->Base_MspInitCallback == NULL)
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Base_MspInitCallback(htim);
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     HAL_TIM_Base_MspInit(htim);
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 7
+
+
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM state */
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Time Base configuration */
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the DMA burst operation state */
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the TIM channels state */
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the TIM state*/
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  DeInitializes the TIM Base peripheral
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the TIM Peripheral Clock */
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->Base_MspDeInitCallback == NULL)
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* DeInit the low level hardware */
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Base_MspDeInitCallback(htim);
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_Base_MspDeInit(htim);
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change the DMA burst operation state */
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change the TIM channels state */
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change TIM state */
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_RESET;
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Release Lock */
+ARM GAS  /tmp/cc0wMqvE.s 			page 8
+
+
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM Base MSP.
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_Base_MspInit could be implemented in the user file
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  DeInitializes TIM Base MSP.
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_Base_MspDeInit could be implemented in the user file
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM Base generation.
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM state */
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->State != HAL_TIM_STATE_READY)
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM state */
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 9
+
+
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM Base generation.
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Peripheral */
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM state */
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM Base generation in interrupt mode.
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM state */
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->State != HAL_TIM_STATE_READY)
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM state */
+ARM GAS  /tmp/cc0wMqvE.s 			page 10
+
+
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the TIM Update interrupt */
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM Base generation in interrupt mode.
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the TIM Update interrupt */
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Peripheral */
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM state */
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM Base generation in DMA mode.
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  pData The source Buffer address.
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Length The length of data to be transferred from memory to peripheral.
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 11
+
+
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM state */
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_BUSY)
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_BUSY;
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (htim->State == HAL_TIM_STATE_READY)
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((pData == NULL) && (Length > 0U))
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->State = HAL_TIM_STATE_BUSY;
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the DMA Period elapsed callbacks */
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the DMA error callback */
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the DMA channel */
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->A
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                        Length) != HAL_OK)
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Return error status */
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the TIM Update DMA request */
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+ARM GAS  /tmp/cc0wMqvE.s 			page 12
+
+
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM Base generation in DMA mode.
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the TIM Update DMA request */
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Peripheral */
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM state */
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *  @brief    TIM Output Compare functions
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @verbatim
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                   ##### TIM Output Compare functions #####
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     This section provides functions allowing to:
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Initialize and configure the TIM Output Compare.
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) De-initialize the TIM Output Compare.
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the TIM Output Compare.
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the TIM Output Compare.
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the TIM Output Compare and enable interrupt.
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the TIM Output Compare and disable interrupt.
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the TIM Output Compare and enable DMA transfer.
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the TIM Output Compare and disable DMA transfer.
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @endverbatim
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM Output Compare according to the specified
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ARM GAS  /tmp/cc0wMqvE.s 			page 13
+
+
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         requires a timer reset to avoid unexpected direction
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         due to DIR bit readonly in center aligned mode.
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim == NULL)
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Allocate lock resource and initialize it */
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Lock = HAL_UNLOCKED;
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset interrupt callbacks to legacy weak callbacks */
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_ResetCallback(htim);
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (htim->OC_MspInitCallback == NULL)
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->OC_MspInitCallback(htim);
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     HAL_TIM_OC_MspInit(htim);
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM state */
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Init the base time for the Output Compare */
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the DMA burst operation state */
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the TIM channels state */
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the TIM state*/
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 14
+
+
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  DeInitializes the TIM peripheral
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the TIM Peripheral Clock */
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->OC_MspDeInitCallback == NULL)
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* DeInit the low level hardware */
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->OC_MspDeInitCallback(htim);
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_OC_MspDeInit(htim);
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change the DMA burst operation state */
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change the TIM channels state */
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change TIM state */
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_RESET;
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Release Lock */
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM Output Compare MSP.
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ARM GAS  /tmp/cc0wMqvE.s 			page 15
+
+
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_OC_MspInit could be implemented in the user file
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  DeInitializes TIM Output Compare MSP.
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_OC_MspDeInit could be implemented in the user file
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM Output Compare signal generation.
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channel to be enabled
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM channel state */
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Output compare channel */
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the main output */
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_MOE_ENABLE(htim);
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 16
+
+
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM Output Compare signal generation.
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channel to be disabled
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Output compare channel */
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Main Output */
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_MOE_DISABLE(htim);
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Peripheral */
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+ARM GAS  /tmp/cc0wMqvE.s 			page 17
+
+
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channel to be enabled
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM channel state */
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 1 interrupt */
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 2 interrupt */
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 3 interrupt */
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 4 interrupt */
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+ARM GAS  /tmp/cc0wMqvE.s 			page 18
+
+
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the Output compare channel */
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the main output */
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_MOE_ENABLE(htim);
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         __HAL_TIM_ENABLE(htim);
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channel to be disabled
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 1 interrupt */
+ARM GAS  /tmp/cc0wMqvE.s 			page 19
+
+
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 2 interrupt */
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 3 interrupt */
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 4 interrupt */
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Output compare channel */
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the Main Output */
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_MOE_DISABLE(htim);
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Peripheral */
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE(htim);
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the TIM channel state */
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channel to be enabled
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+ARM GAS  /tmp/cc0wMqvE.s 			page 20
+
+
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  pData The source Buffer address.
+1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Length The length of data to be transferred from memory to TIM peripheral
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, 
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_BUSY;
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((pData == NULL) && (Length > 0U))
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->
+1107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+1111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 1 DMA request */
+ARM GAS  /tmp/cc0wMqvE.s 			page 21
+
+
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+1126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 2 DMA request */
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->
+1151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+1152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+1153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 3 DMA request */
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+ARM GAS  /tmp/cc0wMqvE.s 			page 22
+
+
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 4 DMA request */
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the Output compare channel */
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the main output */
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_MOE_ENABLE(htim);
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         __HAL_TIM_ENABLE(htim);
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+1206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+1208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+1210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+1216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+1219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channel to be disabled
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+ARM GAS  /tmp/cc0wMqvE.s 			page 23
+
+
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 1 DMA request */
+1240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 2 DMA request */
+1248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 3 DMA request */
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 4 interrupt */
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Output compare channel */
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the Main Output */
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_MOE_DISABLE(htim);
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 24
+
+
+1285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Peripheral */
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE(htim);
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the TIM channel state */
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *  @brief    TIM PWM functions
+1302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @verbatim
+1304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                           ##### TIM PWM functions #####
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+1307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     This section provides functions allowing to:
+1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Initialize and configure the TIM PWM.
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) De-initialize the TIM PWM.
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the TIM PWM.
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the TIM PWM.
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the TIM PWM and enable interrupt.
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the TIM PWM and disable interrupt.
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the TIM PWM and enable DMA transfer.
+1316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the TIM PWM and disable DMA transfer.
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @endverbatim
+1319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM PWM Time Base according to the specified
+1323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+1325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         requires a timer reset to avoid unexpected direction
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         due to DIR bit readonly in center aligned mode.
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+1328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim == NULL)
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ARM GAS  /tmp/cc0wMqvE.s 			page 25
+
+
+1342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+1344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Allocate lock resource and initialize it */
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Lock = HAL_UNLOCKED;
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset interrupt callbacks to legacy weak callbacks */
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_ResetCallback(htim);
+1353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (htim->PWM_MspInitCallback == NULL)
+1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->PWM_MspInitCallback(htim);
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     HAL_TIM_PWM_MspInit(htim);
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM state */
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+1368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Init the base time for the PWM */
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_Base_SetConfig(htim->Instance, &htim->Init);
+1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the DMA burst operation state */
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the TIM channels state */
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the TIM state*/
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+1384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  DeInitializes the TIM peripheral
+1387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+1394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the TIM Peripheral Clock */
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ARM GAS  /tmp/cc0wMqvE.s 			page 26
+
+
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+1401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->PWM_MspDeInitCallback == NULL)
+1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* DeInit the low level hardware */
+1406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->PWM_MspDeInitCallback(htim);
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_PWM_MspDeInit(htim);
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change the DMA burst operation state */
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change the TIM channels state */
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change TIM state */
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_RESET;
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Release Lock */
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+1427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM PWM MSP.
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+1436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+1437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_PWM_MspInit could be implemented in the user file
+1440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  DeInitializes TIM PWM MSP.
+1445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+ARM GAS  /tmp/cc0wMqvE.s 			page 27
+
+
+1456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the PWM signal generation.
+1460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+1461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+1462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+1468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+1469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+1470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+1476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+1477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM channel state */
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+1480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+1482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Capture compare channel */
+1488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+1489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the main output */
+1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_MOE_ENABLE(htim);
+1494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+1503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+1508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+1512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ARM GAS  /tmp/cc0wMqvE.s 			page 28
+
+
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the PWM signal generation.
+1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+1524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+1531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Capture compare channel */
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Main Output */
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_MOE_DISABLE(htim);
+1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Peripheral */
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+1550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the PWM signal generation in interrupt mode.
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channel to be enabled
+1555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+1561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 29
+
+
+1570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM channel state */
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+1574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 1 interrupt */
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+1589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 2 interrupt */
+1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 3 interrupt */
+1598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+1599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 4 interrupt */
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+1606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+1610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+1611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the Capture compare channel */
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+1618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the main output */
+1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_MOE_ENABLE(htim);
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ARM GAS  /tmp/cc0wMqvE.s 			page 30
+
+
+1627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         __HAL_TIM_ENABLE(htim);
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+1637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the PWM signal generation in interrupt mode.
+1646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+1658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+1661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 1 interrupt */
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 2 interrupt */
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+1675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 3 interrupt */
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+1682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ARM GAS  /tmp/cc0wMqvE.s 			page 31
+
+
+1684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 4 interrupt */
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+1693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+1694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Capture compare channel */
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the Main Output */
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_MOE_DISABLE(htim);
+1706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Peripheral */
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE(htim);
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the TIM channel state */
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+1716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM PWM signal generation in DMA mode.
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  pData The source Buffer address.
+1729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Length The length of data to be transferred from memory to TIM peripheral
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+1731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData,
+1733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+1735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+1738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+ARM GAS  /tmp/cc0wMqvE.s 			page 32
+
+
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_BUSY;
+1744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((pData == NULL) && (Length > 0U))
+1748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+1750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+1757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+1762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+1770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+1771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 1 DMA request */
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+1782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->
+1796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+1797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ARM GAS  /tmp/cc0wMqvE.s 			page 33
+
+
+1798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+1799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+1801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 2 DMA request */
+1802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+1813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+1814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->
+1817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+1818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+1819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+1820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+1821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Output Capture/Compare 3 request */
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+1835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->
+1838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+1841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+1843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 4 DMA request */
+1844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+1850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+1854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 34
+
+
+1855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the Capture compare channel */
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+1857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the main output */
+1861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_MOE_ENABLE(htim);
+1862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+1870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         __HAL_TIM_ENABLE(htim);
+1871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+1872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+1874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+1876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+1881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+1882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM PWM signal generation in DMA mode.
+1885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+1893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+1897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+1899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+1900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+1902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+1904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 1 DMA request */
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+1907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+ARM GAS  /tmp/cc0wMqvE.s 			page 35
+
+
+1912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 2 DMA request */
+1914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+1916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 3 DMA request */
+1922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+1924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 4 interrupt */
+1930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+1932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+1936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+1938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+1941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+1942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Capture compare channel */
+1943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+1944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+1947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the Main Output */
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_MOE_DISABLE(htim);
+1949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+1950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Peripheral */
+1952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE(htim);
+1953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the TIM channel state */
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+1957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+1959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+1960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+1961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+1964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+1967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *  @brief    TIM Input Capture functions
+1968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+ARM GAS  /tmp/cc0wMqvE.s 			page 36
+
+
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @verbatim
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+1971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****               ##### TIM Input Capture functions #####
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+1973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****  [..]
+1974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    This section provides functions allowing to:
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) Initialize and configure the TIM Input Capture.
+1976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) De-initialize the TIM Input Capture.
+1977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) Start the TIM Input Capture.
+1978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) Stop the TIM Input Capture.
+1979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) Start the TIM Input Capture and enable interrupt.
+1980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) Stop the TIM Input Capture and disable interrupt.
+1981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) Start the TIM Input Capture and enable DMA transfer.
+1982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) Stop the TIM Input Capture and disable DMA transfer.
+1983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+1984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @endverbatim
+1985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+1988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM Input Capture Time base according to the specified
+1989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+1990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+1991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         requires a timer reset to avoid unexpected direction
+1992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         due to DIR bit readonly in center aligned mode.
+1993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+1994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+1995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+1996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+1997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+1998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+1999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim == NULL)
+2001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+2003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+2006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+2007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+2008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+2009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+2010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+2012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Allocate lock resource and initialize it */
+2014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Lock = HAL_UNLOCKED;
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+2017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset interrupt callbacks to legacy weak callbacks */
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_ResetCallback(htim);
+2019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (htim->IC_MspInitCallback == NULL)
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+2023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->IC_MspInitCallback(htim);
+ARM GAS  /tmp/cc0wMqvE.s 			page 37
+
+
+2026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+2028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     HAL_TIM_IC_MspInit(htim);
+2029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM state */
+2033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+2034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Init the base time for the input capture */
+2036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_Base_SetConfig(htim->Instance, &htim->Init);
+2037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the DMA burst operation state */
+2039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+2040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the TIM channels state */
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the TIM state*/
+2046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+2047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+2049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  DeInitializes the TIM peripheral
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+2055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+2059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+2062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the TIM Peripheral Clock */
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->IC_MspDeInitCallback == NULL)
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+2070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* DeInit the low level hardware */
+2072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->IC_MspDeInitCallback(htim);
+2073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+2075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_IC_MspDeInit(htim);
+2076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+2077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change the DMA burst operation state */
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+2080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change the TIM channels state */
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ARM GAS  /tmp/cc0wMqvE.s 			page 38
+
+
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+2084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change TIM state */
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_RESET;
+2087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Release Lock */
+2089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+2090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+2092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM Input Capture MSP.
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+2098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+2100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+2103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_IC_MspInit could be implemented in the user file
+2106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  DeInitializes TIM Input Capture MSP.
+2111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+2112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+2113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+2115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+2118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_IC_MspDeInit could be implemented in the user file
+2121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM Input Capture measurement.
+2126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+2128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+2129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+2131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+2132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+2133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+2134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+2136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ARM GAS  /tmp/cc0wMqvE.s 			page 39
+
+
+2140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+2142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+2143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM channel state */
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+2146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+2147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Input Capture channel */
+2156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+2162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+2163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+2168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+2170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+2174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM Input Capture measurement.
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+2181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+2184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+2185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+2186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+2190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+2191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Input Capture channel */
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+2194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Peripheral */
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ARM GAS  /tmp/cc0wMqvE.s 			page 40
+
+
+2197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+2201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+2204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+2208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+2210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+2211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+2212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+2213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+2214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+2215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+2216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+2218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+2221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+2224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+2226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+2227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM channel state */
+2229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+2230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+2233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+2238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+2240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+2242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 1 interrupt */
+2244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+2245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+2249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 2 interrupt */
+2251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+2252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ARM GAS  /tmp/cc0wMqvE.s 			page 41
+
+
+2254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+2256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 3 interrupt */
+2258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+2259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+2263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 4 interrupt */
+2265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+2266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+2270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+2271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+2275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the Input Capture channel */
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+2278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+2281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+2283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+2284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+2285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         __HAL_TIM_ENABLE(htim);
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+2287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+2289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+2291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+2295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+2296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+2302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+2304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+2305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+2306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+2307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+2308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+2310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ARM GAS  /tmp/cc0wMqvE.s 			page 42
+
+
+2311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+2314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+2315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+2317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+2319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 1 interrupt */
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+2322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+2326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 2 interrupt */
+2328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+2329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+2333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 3 interrupt */
+2335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+2336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+2340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 4 interrupt */
+2342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+2347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+2348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+2352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Input Capture channel */
+2354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+2355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Peripheral */
+2357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE(htim);
+2358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the TIM channel state */
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+2362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+2365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+2366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 43
+
+
+2368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM Input Capture measurement in DMA mode.
+2370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+2372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+2373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+2374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+2375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+2376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+2377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  pData The destination Buffer address.
+2378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Length The length of data to be transferred from TIM peripheral to memory.
+2379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+2380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, 
+2382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+2384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+2385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+2388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+2390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+2391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+2392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+2394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+2396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_BUSY;
+2398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
+2400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+2401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((pData == NULL) && (Length > 0U))
+2403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+2405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+2407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+2410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+2413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+2415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Input Capture channel */
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+2419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+2421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+2423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+ARM GAS  /tmp/cc0wMqvE.s 			page 44
+
+
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+2426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+2427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+2430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)p
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+2434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+2435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+2436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+2437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 1 DMA request */
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+2440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+2444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+2447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+2448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+2450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+2451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+2453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)p
+2454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+2455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+2456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+2457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+2458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+2459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 2  DMA request */
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+2461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+2465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+2469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+2471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+2472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+2474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)p
+2475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+2477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+2478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+2479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+2480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 3  DMA request */
+2481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ARM GAS  /tmp/cc0wMqvE.s 			page 45
+
+
+2482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+2486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+2488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+2489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+2490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+2493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)p
+2496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+2497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+2498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+2499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+2500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+2501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 4  DMA request */
+2502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+2503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+2507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+2508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+2513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+2515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+2516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+2518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+2521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+2523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+2526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM Input Capture measurement in DMA mode.
+2531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+2533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+2534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+2535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+2536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+2537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+2538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ARM GAS  /tmp/cc0wMqvE.s 			page 46
+
+
+2539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+2541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+2543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+2545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+2546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+2547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Input Capture channel */
+2549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+2550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+2552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+2554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 1 DMA request */
+2556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+2557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+2558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+2562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 2 DMA request */
+2564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+2565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+2566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+2570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 3  DMA request */
+2572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+2573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+2574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+2578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 4  DMA request */
+2580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+2582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+2586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+2587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+2588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+2591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Peripheral */
+2593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE(htim);
+2594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the TIM channel state */
+ARM GAS  /tmp/cc0wMqvE.s 			page 47
+
+
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+2598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+2601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+2605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+2608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *  @brief    TIM One Pulse functions
+2609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+2610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @verbatim
+2611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+2612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         ##### TIM One Pulse functions #####
+2613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+2614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+2615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     This section provides functions allowing to:
+2616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Initialize and configure the TIM One Pulse.
+2617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) De-initialize the TIM One Pulse.
+2618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the TIM One Pulse.
+2619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the TIM One Pulse.
+2620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the TIM One Pulse and enable interrupt.
+2621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the TIM One Pulse and disable interrupt.
+2622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the TIM One Pulse and enable DMA transfer.
+2623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the TIM One Pulse and disable DMA transfer.
+2624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @endverbatim
+2626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+2627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM One Pulse Time Base according to the specified
+2630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+2631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+2632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         requires a timer reset to avoid unexpected direction
+2633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         due to DIR bit readonly in center aligned mode.
+2634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+2635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   When the timer instance is initialized in One Pulse mode, timer
+2636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         channels 1 and channel 2 are reserved and cannot be used for other
+2637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         purpose.
+2638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  OnePulseMode Select the One pulse mode.
+2640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         This parameter can be one of the following values:
+2641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+2642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+2643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+2644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+2646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+2648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim == NULL)
+2649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+2651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 48
+
+
+2653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+2654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+2655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+2656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+2657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+2658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+2659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+2661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Allocate lock resource and initialize it */
+2663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Lock = HAL_UNLOCKED;
+2664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+2666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset interrupt callbacks to legacy weak callbacks */
+2667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_ResetCallback(htim);
+2668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (htim->OnePulse_MspInitCallback == NULL)
+2670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+2671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+2672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+2673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+2674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->OnePulse_MspInitCallback(htim);
+2675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+2676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+2677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     HAL_TIM_OnePulse_MspInit(htim);
+2678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+2679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM state */
+2682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+2683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Configure the Time base in the One Pulse Mode */
+2685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_Base_SetConfig(htim->Instance, &htim->Init);
+2686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the OPM Bit */
+2688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Instance->CR1 &= ~TIM_CR1_OPM;
+2689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Configure the OPM Mode */
+2691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Instance->CR1 |= OnePulseMode;
+2692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the DMA burst operation state */
+2694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+2695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the TIM channels state */
+2697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the TIM state*/
+2703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+2704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+2706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  DeInitializes the TIM One Pulse
+ARM GAS  /tmp/cc0wMqvE.s 			page 49
+
+
+2710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+2712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+2714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+2716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+2717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+2719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the TIM Peripheral Clock */
+2721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+2722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+2724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->OnePulse_MspDeInitCallback == NULL)
+2725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+2727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* DeInit the low level hardware */
+2729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->OnePulse_MspDeInitCallback(htim);
+2730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+2731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+2732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_OnePulse_MspDeInit(htim);
+2733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+2734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change the DMA burst operation state */
+2736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+2737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel state */
+2739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+2740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+2741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+2742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+2743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change TIM state */
+2745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_RESET;
+2746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Release Lock */
+2748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+2749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+2751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM One Pulse MSP.
+2755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+2757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+2759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+2762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+2765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+2766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ARM GAS  /tmp/cc0wMqvE.s 			page 50
+
+
+2767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  DeInitializes TIM One Pulse MSP.
+2770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+2772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+2774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+2777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+2780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+2781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM One Pulse signal generation.
+2785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note Though OutputChannel parameter is deprecated and ignored by the function
+2786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        it has been kept to avoid HAL_TIM API compatibility break.
+2787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note The pulse output channel is determined when calling
+2788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+2789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  OutputChannel See note above
+2791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+2792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+2794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+2796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+2798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+2799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(OutputChannel);
+2802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM channels state */
+2804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+2805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+2806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+2807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+2808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+2810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channels state */
+2813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+2815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+2816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+2817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Capture compare and the Input Capture channels
+2819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2
+2820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+2821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+2822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+2823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 51
+
+
+2824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     No need to enable the counter, it's enabled automatically by hardware
+2825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (the counter starts in response to a stimulus and generate a pulse */
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+2828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+2829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+2831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the main output */
+2833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_MOE_ENABLE(htim);
+2834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+2838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM One Pulse signal generation.
+2842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note Though OutputChannel parameter is deprecated and ignored by the function
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        it has been kept to avoid HAL_TIM API compatibility break.
+2844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note The pulse output channel is determined when calling
+2845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  OutputChannel See note above
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+2849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(OutputChannel);
+2854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Capture compare and the Input Capture channels
+2856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+2858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+2859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+2860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+2863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+2865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Main Output */
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_MOE_DISABLE(htim);
+2868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Peripheral */
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+2872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channels state */
+2874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+2880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+ARM GAS  /tmp/cc0wMqvE.s 			page 52
+
+
+2881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+2885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note Though OutputChannel parameter is deprecated and ignored by the function
+2886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        it has been kept to avoid HAL_TIM API compatibility break.
+2887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note The pulse output channel is determined when calling
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  OutputChannel See note above
+2891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+2892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+2894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+2896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+2897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+2899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(OutputChannel);
+2902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM channels state */
+2904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+2905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+2906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+2907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+2908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+2910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channels state */
+2913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+2914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+2915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+2916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+2917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Capture compare and the Input Capture channels
+2919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2
+2920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+2922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+2923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     No need to enable the counter, it's enabled automatically by hardware
+2925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (the counter starts in response to a stimulus and generate a pulse */
+2926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the TIM Capture/Compare 1 interrupt */
+2928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+2929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the TIM Capture/Compare 2 interrupt */
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+2932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+2934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+2935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+2937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 53
+
+
+2938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the main output */
+2939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_MOE_ENABLE(htim);
+2940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+2944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+2947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+2948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note Though OutputChannel parameter is deprecated and ignored by the function
+2949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        it has been kept to avoid HAL_TIM API compatibility break.
+2950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note The pulse output channel is determined when calling
+2951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+2952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  OutputChannel See note above
+2954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+2955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+2957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+2958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(OutputChannel);
+2960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the TIM Capture/Compare 1 interrupt */
+2962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+2963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the TIM Capture/Compare 2 interrupt */
+2965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+2966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Capture compare and the Input Capture channels
+2968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+2969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+2970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+2971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+2972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+2973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+2974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+2976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+2977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the Main Output */
+2978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_MOE_DISABLE(htim);
+2979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+2980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Peripheral */
+2982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+2983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channels state */
+2985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+2991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+2993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ARM GAS  /tmp/cc0wMqvE.s 			page 54
+
+
+2995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+2996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+2997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+2998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+2999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *  @brief    TIM Encoder functions
+3000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+3001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @verbatim
+3002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+3003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                           ##### TIM Encoder functions #####
+3004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+3005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+3006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     This section provides functions allowing to:
+3007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Initialize and configure the TIM Encoder.
+3008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) De-initialize the TIM Encoder.
+3009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the TIM Encoder.
+3010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the TIM Encoder.
+3011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the TIM Encoder and enable interrupt.
+3012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the TIM Encoder and disable interrupt.
+3013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Start the TIM Encoder and enable DMA transfer.
+3014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (+) Stop the TIM Encoder and disable DMA transfer.
+3015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @endverbatim
+3017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+3018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+3020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+3021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+3022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         requires a timer reset to avoid unexpected direction
+3023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         due to DIR bit readonly in center aligned mode.
+3024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+3025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected toge
+3026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_Config
+3027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+3028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   When the timer instance is initialized in Encoder mode, timer
+3029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         channels 1 and channel 2 are reserved and cannot be used for other
+3030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         purpose.
+3031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  sConfig TIM Encoder Interface configuration structure
+3033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+3034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
+3036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+3037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+3038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmr1;
+3039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+3040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+3042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim == NULL)
+3043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+3045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+3050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+3051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ARM GAS  /tmp/cc0wMqvE.s 			page 55
+
+
+3052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+3053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+3054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+3055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+3056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+3057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+3058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+3060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+3061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+3063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Allocate lock resource and initialize it */
+3065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Lock = HAL_UNLOCKED;
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset interrupt callbacks to legacy weak callbacks */
+3069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_ResetCallback(htim);
+3070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (htim->Encoder_MspInitCallback == NULL)
+3072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+3074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+3076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Encoder_MspInitCallback(htim);
+3077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+3079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     HAL_TIM_Encoder_MspInit(htim);
+3080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM state */
+3084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+3085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the SMS and ECE bits */
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+3088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Configure the Time base in the Encoder Mode */
+3090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_Base_SetConfig(htim->Instance, &htim->Init);
+3091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx SMCR register value */
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr = htim->Instance->SMCR;
+3094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCMR1 register value */
+3096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 = htim->Instance->CCMR1;
+3097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+3099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = htim->Instance->CCER;
+3100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the encoder Mode */
+3102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr |= sConfig->EncoderMode;
+3103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+3105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+3106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+3107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ARM GAS  /tmp/cc0wMqvE.s 			page 56
+
+
+3109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+3110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+3111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+3112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+3113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TI1 and the TI2 Polarities */
+3115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+3116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+3118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx SMCR */
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Instance->SMCR = tmpsmcr;
+3121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR1 */
+3123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Instance->CCMR1 = tmpccmr1;
+3124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCER */
+3126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Instance->CCER = tmpccer;
+3127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the DMA burst operation state */
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+3130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channels state */
+3132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Initialize the TIM state*/
+3138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+3139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+3142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+3145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  DeInitializes the TIM Encoder interface
+3146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+3148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+3150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+3151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+3152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+3153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+3155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the TIM Peripheral Clock */
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+3158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->Encoder_MspDeInitCallback == NULL)
+3161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+3163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* DeInit the low level hardware */
+3165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Encoder_MspDeInitCallback(htim);
+ARM GAS  /tmp/cc0wMqvE.s 			page 57
+
+
+3166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+3168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_Encoder_MspDeInit(htim);
+3169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change the DMA burst operation state */
+3172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+3173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channels state */
+3175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+3176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+3177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+3178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+3179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change TIM state */
+3181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_RESET;
+3182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Release Lock */
+3184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+3185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+3187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+3188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+3190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM Encoder Interface MSP.
+3191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+3193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+3195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+3196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+3197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+3198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+3200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_Encoder_MspInit could be implemented in the user file
+3201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+3202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+3203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+3205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  DeInitializes TIM Encoder Interface MSP.
+3206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+3208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+3210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+3211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+3212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+3213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+3215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+3216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+3217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+3218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+3220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM Encoder Interface.
+3221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+ARM GAS  /tmp/cc0wMqvE.s 			page 58
+
+
+3223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+3224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+3225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+3226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+3227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+3228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+3230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+3231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+3232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+3233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+3234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+3235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+3237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel(s) state */
+3240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (Channel == TIM_CHANNEL_1)
+3241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+3243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+3244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+3246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+3248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_2)
+3254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+3256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+3257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+3259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+3261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+3267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+3269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+3270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+3271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+3272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+3274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+3276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ARM GAS  /tmp/cc0wMqvE.s 			page 59
+
+
+3280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the encoder interface channels */
+3285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+3286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+3288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+3290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+3291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+3294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+3296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+3297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default :
+3300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+3302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+3303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+3304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Peripheral */
+3307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_ENABLE(htim);
+3308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+3310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+3311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+3312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+3314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM Encoder Interface.
+3315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+3317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+3318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+3319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+3320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+3321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+3322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+3324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+3325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+3326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Input Capture channels 1 and 2
+3329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C
+3330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+3331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+3333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+3335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+3336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ARM GAS  /tmp/cc0wMqvE.s 			page 60
+
+
+3337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+3339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+3341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+3342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default :
+3345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+3347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+3348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+3349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Peripheral */
+3353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+3354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel(s) state */
+3356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+3357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+3359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+3360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+3362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+3370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+3371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+3372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+3374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM Encoder Interface in interrupt mode.
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+3377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+3378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+3380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+3382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+3384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+3385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+3387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+3388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+3389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel(s) state */
+ARM GAS  /tmp/cc0wMqvE.s 			page 61
+
+
+3394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (Channel == TIM_CHANNEL_1)
+3395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+3397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+3398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_2)
+3408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+3410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+3411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+3413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+3415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+3421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+3423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+3424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+3425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+3426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+3428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+3430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the encoder interface channels */
+3439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the capture compare Interrupts 1 and/or 2 */
+3440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+3441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+3443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+3445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+3446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+3447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+3450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ARM GAS  /tmp/cc0wMqvE.s 			page 62
+
+
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+3452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+3453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+3454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default :
+3457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+3459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+3460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+3461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+3462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+3463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable the Peripheral */
+3467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_ENABLE(htim);
+3468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+3470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+3471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+3472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+3474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM Encoder Interface in interrupt mode.
+3475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+3477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+3478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+3479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+3480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+3481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+3482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+3484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+3486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Input Capture channels 1 and 2
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C
+3490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (Channel == TIM_CHANNEL_1)
+3491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+3493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the capture compare Interrupts 1 */
+3495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+3496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_2)
+3498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+3500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the capture compare Interrupts 2 */
+3502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+3503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+3505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ARM GAS  /tmp/cc0wMqvE.s 			page 63
+
+
+3508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the capture compare Interrupts 1 and 2 */
+3510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+3511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Peripheral */
+3515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+3516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel(s) state */
+3518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+3519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+3521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+3522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+3524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+3533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+3534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+3536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Starts the TIM Encoder Interface in DMA mode.
+3537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+3539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+3540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+3541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+3542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+3543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  pData1 The destination Buffer address for IC1.
+3544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  pData2 The destination Buffer address for IC2.
+3545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Length The length of data to be transferred from TIM peripheral to memory.
+3546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pD
+3549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                             uint32_t *pData2, uint16_t Length)
+3550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+3552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+3553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+3554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+3557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel(s) state */
+3560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (Channel == TIM_CHANNEL_1)
+3561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+3563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+3564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ARM GAS  /tmp/cc0wMqvE.s 			page 64
+
+
+3565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_BUSY;
+3566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+3568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+3569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if ((pData1 == NULL) && (Length > 0U))
+3571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+3573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       else
+3575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+3581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+3583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_2)
+3586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+3588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+3589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_BUSY;
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+3593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+3594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if ((pData2 == NULL) && (Length > 0U))
+3596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+3598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       else
+3600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+3606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+3608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+3611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+3613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+3614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+3615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+3616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_BUSY;
+3618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+3620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+3621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ARM GAS  /tmp/cc0wMqvE.s 			page 65
+
+
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+3623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+3625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+3627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       else
+3629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+3637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+3639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+3643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+3645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+3647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+3648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+3649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+3651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+3652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+3654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)p
+3655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+3656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+3658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+3659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Input Capture DMA request */
+3661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+3662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the Capture compare channel */
+3664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+3665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the Peripheral */
+3667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+3668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+3673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+3676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+3677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+ARM GAS  /tmp/cc0wMqvE.s 			page 66
+
+
+3679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+3680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)p
+3682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+3685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+3686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Input Capture  DMA request */
+3688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+3689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the Capture compare channel */
+3691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+3692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the Peripheral */
+3694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+3695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+3697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+3700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+3702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+3703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+3704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+3706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+3707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+3709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)p
+3710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+3711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+3713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+3714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+3717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+3718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+3719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+3721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+3722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+3724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)p
+3725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+3726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+3728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+3729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Input Capture  DMA request */
+3732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+3733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Input Capture  DMA request */
+3734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+3735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 67
+
+
+3736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the Capture compare channel */
+3737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+3738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+3739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the Peripheral */
+3741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+3742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+3744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+3748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+3749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+3750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+3752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM Encoder Interface in DMA mode.
+3753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+3755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+3756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+3757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+3758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+3759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+3760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+3762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+3763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+3764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Input Capture channels 1 and 2
+3767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C
+3768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (Channel == TIM_CHANNEL_1)
+3769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+3771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the capture compare DMA Request 1 */
+3773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+3774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+3775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_2)
+3777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+3779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the capture compare DMA Request 2 */
+3781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+3782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+3783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+3785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+3787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+3788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the capture compare DMA Request 1 and 2 */
+3790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+3791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+3792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ARM GAS  /tmp/cc0wMqvE.s 			page 68
+
+
+3793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+3794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Peripheral */
+3797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+3798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TIM channel(s) state */
+3800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+3801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+3803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+3804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+3806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+3814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+3815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+3816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+3818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+3819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+3821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *  @brief    TIM IRQ handler management
+3822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+3823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @verbatim
+3824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+3825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         ##### IRQ handler management #####
+3826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+3827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   [..]
+3828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     This section provides Timer IRQ handler function.
+3829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @endverbatim
+3831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+3832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+3834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  This function handles TIM interrupts requests.
+3835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM  handle
+3836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+3837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+3838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+3839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+3840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Capture compare 1 event */
+3841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+3842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+3844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+3847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+3848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+3849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Input capture event */
+ARM GAS  /tmp/cc0wMqvE.s 			page 69
+
+
+3850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+3851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+3852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->IC_CaptureCallback(htim);
+3854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           HAL_TIM_IC_CaptureCallback(htim);
+3856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+3858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Output compare event */
+3859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         else
+3860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+3861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->OC_DelayElapsedCallback(htim);
+3863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->PWM_PulseFinishedCallback(htim);
+3864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           HAL_TIM_OC_DelayElapsedCallback(htim);
+3866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           HAL_TIM_PWM_PulseFinishedCallback(htim);
+3867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+3869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+3870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Capture compare 2 event */
+3874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+3875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+3877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+3879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+3880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Input capture event */
+3881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+3882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_CaptureCallback(htim);
+3885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         HAL_TIM_IC_CaptureCallback(htim);
+3887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Output compare event */
+3890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       else
+3891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_DelayElapsedCallback(htim);
+3894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_PulseFinishedCallback(htim);
+3895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         HAL_TIM_OC_DelayElapsedCallback(htim);
+3897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         HAL_TIM_PWM_PulseFinishedCallback(htim);
+3898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+3901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Capture compare 3 event */
+3904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+3905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+ARM GAS  /tmp/cc0wMqvE.s 			page 70
+
+
+3907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+3909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+3910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Input capture event */
+3911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+3912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_CaptureCallback(htim);
+3915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         HAL_TIM_IC_CaptureCallback(htim);
+3917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Output compare event */
+3920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       else
+3921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_DelayElapsedCallback(htim);
+3924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_PulseFinishedCallback(htim);
+3925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         HAL_TIM_OC_DelayElapsedCallback(htim);
+3927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         HAL_TIM_PWM_PulseFinishedCallback(htim);
+3928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+3931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Capture compare 4 event */
+3934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+3935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+3937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+3939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+3940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Input capture event */
+3941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+3942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_CaptureCallback(htim);
+3945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         HAL_TIM_IC_CaptureCallback(htim);
+3947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Output compare event */
+3950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       else
+3951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+3952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_DelayElapsedCallback(htim);
+3954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_PulseFinishedCallback(htim);
+3955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         HAL_TIM_OC_DelayElapsedCallback(htim);
+3957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         HAL_TIM_PWM_PulseFinishedCallback(htim);
+3958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+3960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+3961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* TIM Update event */
+ARM GAS  /tmp/cc0wMqvE.s 			page 71
+
+
+3964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+3965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+3967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+3969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->PeriodElapsedCallback(htim);
+3971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       HAL_TIM_PeriodElapsedCallback(htim);
+3973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* TIM Break input event */
+3977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+3978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+3980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+3982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->BreakCallback(htim);
+3984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       HAL_TIMEx_BreakCallback(htim);
+3986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+3988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+3989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* TIM Break2 input event */
+3990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+3991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+3992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+3993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+3994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+3995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Break2Callback(htim);
+3997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+3998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       HAL_TIMEx_Break2Callback(htim);
+3999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+4000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* TIM Trigger detection event */
+4003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+4004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+4006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+4008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+4009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->TriggerCallback(htim);
+4010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+4011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       HAL_TIM_TriggerCallback(htim);
+4012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+4013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* TIM commutation event */
+4016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+4017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+4019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ARM GAS  /tmp/cc0wMqvE.s 			page 72
+
+
+4021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+4022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->CommutationCallback(htim);
+4023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+4024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       HAL_TIMEx_CommutCallback(htim);
+4025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+4026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* TIM Encoder index event */
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IDX) != RESET)
+4030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IDX) != RESET)
+4032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX);
+4034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+4035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->EncoderIndexCallback(htim);
+4036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+4037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       HAL_TIMEx_EncoderIndexCallback(htim);
+4038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+4039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* TIM Direction change event */
+4042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_DIR) != RESET)
+4043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_DIR) != RESET)
+4045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR);
+4047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+4048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->DirectionChangeCallback(htim);
+4049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+4050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       HAL_TIMEx_DirectionChangeCallback(htim);
+4051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+4052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* TIM Index error event */
+4055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IERR) != RESET)
+4056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IERR) != RESET)
+4058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR);
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+4061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->IndexErrorCallback(htim);
+4062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+4063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       HAL_TIMEx_IndexErrorCallback(htim);
+4064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+4065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* TIM Transition error event */
+4068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TERR) != RESET)
+4069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TERR) != RESET)
+4071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR);
+4073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+4074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->TransitionErrorCallback(htim);
+4075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+4076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       HAL_TIMEx_TransitionErrorCallback(htim);
+4077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ARM GAS  /tmp/cc0wMqvE.s 			page 73
+
+
+4078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+4081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+4083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+4084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+4085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+4087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *  @brief    TIM Peripheral Control functions
+4088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+4089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @verbatim
+4090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+4091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                    ##### Peripheral Control functions #####
+4092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+4093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****  [..]
+4094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    This section provides functions allowing to:
+4095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+4096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (+) Configure External Clock source.
+4097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (+) Configure Complementary channels, break features and dead time.
+4098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (+) Configure Master and the Slave synchronization.
+4099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (+) Configure the DMA Burst Mode.
+4100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @endverbatim
+4102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+4103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+4104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+4106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM Output Compare Channels according to the specified
+4107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         parameters in the TIM_OC_InitTypeDef.
+4108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+4109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  sConfig TIM Output Compare configuration structure
+4110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to configure
+4111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+4112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+4113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+4114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+4115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+4116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+4117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+4118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+4119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+4120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+4121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                            TIM_OC_InitTypeDef *sConfig,
+4122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                            uint32_t Channel)
+4123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+4124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+4127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CHANNELS(Channel));
+4128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
+4129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+4130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Process Locked */
+4132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_LOCK(htim);
+4133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+ARM GAS  /tmp/cc0wMqvE.s 			page 74
+
+
+4135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+4137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+4139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+4140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the TIM Channel 1 in Output Compare */
+4142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_OC1_SetConfig(htim->Instance, sConfig);
+4143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+4147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+4149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+4150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the TIM Channel 2 in Output Compare */
+4152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_OC2_SetConfig(htim->Instance, sConfig);
+4153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+4157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+4159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+4160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the TIM Channel 3 in Output Compare */
+4162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_OC3_SetConfig(htim->Instance, sConfig);
+4163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+4167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+4169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the TIM Channel 4 in Output Compare */
+4172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_OC4_SetConfig(htim->Instance, sConfig);
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_5:
+4177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+4179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+4180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the TIM Channel 5 in Output Compare */
+4182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_OC5_SetConfig(htim->Instance, sConfig);
+4183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_6:
+4187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+4189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+4190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the TIM Channel 6 in Output Compare */
+ARM GAS  /tmp/cc0wMqvE.s 			page 75
+
+
+4192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_OC6_SetConfig(htim->Instance, sConfig);
+4193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+4197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+4198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+4202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+4204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+4205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+4207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM Input Capture Channels according to the specified
+4208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         parameters in the TIM_IC_InitTypeDef.
+4209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM IC handle
+4210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  sConfig TIM Input Capture configuration structure
+4211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channel to configure
+4212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+4213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+4214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+4215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+4216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+4217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+4218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+4219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, ui
+4220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+4221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+4224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+4225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+4226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+4227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+4228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+4229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Process Locked */
+4231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_LOCK(htim);
+4232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (Channel == TIM_CHANNEL_1)
+4234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* TI1 Configuration */
+4236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_TI1_SetConfig(htim->Instance,
+4237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+4238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICSelection,
+4239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICFilter);
+4240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the IC1PSC Bits */
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+4243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the IC1PSC value */
+4245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+4246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_2)
+4248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 76
+
+
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* TI2 Configuration */
+4250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+4251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_TI2_SetConfig(htim->Instance,
+4253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+4254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICSelection,
+4255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICFilter);
+4256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the IC2PSC Bits */
+4258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+4259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the IC2PSC value */
+4261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+4262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_3)
+4264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* TI3 Configuration */
+4266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+4267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_TI3_SetConfig(htim->Instance,
+4269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+4270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICSelection,
+4271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICFilter);
+4272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the IC3PSC Bits */
+4274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+4275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the IC3PSC value */
+4277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+4278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_4)
+4280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* TI4 Configuration */
+4282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+4283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_TI4_SetConfig(htim->Instance,
+4285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+4286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICSelection,
+4287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICFilter);
+4288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the IC4PSC Bits */
+4290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+4291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the IC4PSC value */
+4293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+4294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+4296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     status = HAL_ERROR;
+4298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+4301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+4303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+4304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ARM GAS  /tmp/cc0wMqvE.s 			page 77
+
+
+4306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM PWM  channels according to the specified
+4307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         parameters in the TIM_OC_InitTypeDef.
+4308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM PWM handle
+4309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  sConfig TIM PWM configuration structure
+4310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be configured
+4311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+4312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+4313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+4314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+4315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+4316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+4317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+4318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+4319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+4320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+4321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                             TIM_OC_InitTypeDef *sConfig,
+4322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                             uint32_t Channel)
+4323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+4327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CHANNELS(Channel));
+4328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+4329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+4330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+4331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Process Locked */
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_LOCK(htim);
+4334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+4336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+4338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+4340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+4341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the Channel 1 in PWM mode */
+4343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_OC1_SetConfig(htim->Instance, sConfig);
+4344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the Preload enable bit for channel1 */
+4346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+4347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the Output Fast mode */
+4349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+4350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode;
+4351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+4355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+4357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+4358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the Channel 2 in PWM mode */
+4360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_OC2_SetConfig(htim->Instance, sConfig);
+4361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the Preload enable bit for channel2 */
+ARM GAS  /tmp/cc0wMqvE.s 			page 78
+
+
+4363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+4364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the Output Fast mode */
+4366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+4367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+4368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+4372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+4374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+4375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the Channel 3 in PWM mode */
+4377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_OC3_SetConfig(htim->Instance, sConfig);
+4378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the Preload enable bit for channel3 */
+4380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+4381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the Output Fast mode */
+4383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+4384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode;
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+4389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+4391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+4392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the Channel 4 in PWM mode */
+4394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_OC4_SetConfig(htim->Instance, sConfig);
+4395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the Preload enable bit for channel4 */
+4397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+4398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the Output Fast mode */
+4400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+4401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+4402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_5:
+4406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+4408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+4409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the Channel 5 in PWM mode */
+4411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_OC5_SetConfig(htim->Instance, sConfig);
+4412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the Preload enable bit for channel5*/
+4414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+4415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the Output Fast mode */
+4417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+4418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode;
+4419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ARM GAS  /tmp/cc0wMqvE.s 			page 79
+
+
+4420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_6:
+4423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+4425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+4426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the Channel 6 in PWM mode */
+4428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_OC6_SetConfig(htim->Instance, sConfig);
+4429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the Preload enable bit for channel6 */
+4431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+4432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the Output Fast mode */
+4434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+4436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+4440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+4441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+4445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+4447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+4448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+4450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Initializes the TIM One Pulse Channels according to the specified
+4451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         parameters in the TIM_OnePulse_InitTypeDef.
+4452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+4453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  sConfig TIM One Pulse configuration structure
+4454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  OutputChannel TIM output channel to configure
+4455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+4456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+4457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+4458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  InputChannel TIM input Channel to configure
+4459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+4460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+4461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+4462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note  To output a waveform with a minimum delay user can enable the fast
+4463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+4464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        output is forced in response to the edge detection on TIx input,
+4465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        without taking in account the comparison.
+4466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+4467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+4468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef
+4469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                                  uint32_t OutputChannel,  uint32_t InputChannel)
+4470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+4471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_OC_InitTypeDef temp1;
+4473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+4475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+4476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+ARM GAS  /tmp/cc0wMqvE.s 			page 80
+
+
+4477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (OutputChannel != InputChannel)
+4479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Process Locked */
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_LOCK(htim);
+4482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_BUSY;
+4484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Extract the Output compare configuration from sConfig structure */
+4486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCMode = sConfig->OCMode;
+4487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.Pulse = sConfig->Pulse;
+4488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCPolarity = sConfig->OCPolarity;
+4489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCNPolarity = sConfig->OCNPolarity;
+4490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCIdleState = sConfig->OCIdleState;
+4491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCNIdleState = sConfig->OCNIdleState;
+4492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     switch (OutputChannel)
+4494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case TIM_CHANNEL_1:
+4496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+4497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+4498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_OC1_SetConfig(htim->Instance, &temp1);
+4500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+4501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+4502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case TIM_CHANNEL_2:
+4504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+4505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+4506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_OC2_SetConfig(htim->Instance, &temp1);
+4508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+4509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+4510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       default:
+4512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         status = HAL_ERROR;
+4513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+4514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (status == HAL_OK)
+4517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       switch (InputChannel)
+4519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+4520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         case TIM_CHANNEL_1:
+4521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+4522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+4523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+4525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                             sConfig->ICSelection, sConfig->ICFilter);
+4526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Reset the IC1PSC Bits */
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+4529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Select the Trigger source */
+4531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR &= ~TIM_SMCR_TS;
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI1FP1;
+4533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 81
+
+
+4534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Select the Slave Mode */
+4535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+4536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+4537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           break;
+4538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+4539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         case TIM_CHANNEL_2:
+4541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+4542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+4543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+4545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                             sConfig->ICSelection, sConfig->ICFilter);
+4546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Reset the IC2PSC Bits */
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+4549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Select the Trigger source */
+4551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR &= ~TIM_SMCR_TS;
+4552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI2FP2;
+4553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Select the Slave Mode */
+4555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+4556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+4557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           break;
+4558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+4559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         default:
+4561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           status = HAL_ERROR;
+4562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           break;
+4563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+4564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_READY;
+4567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+4569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return status;
+4571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+4573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+4575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+4577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+4579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+4580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+4581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+4582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR1
+4584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR2
+4585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_SMCR
+4586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_DIER
+4587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_SR
+4588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_EGR
+4589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR1
+4590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR2
+ARM GAS  /tmp/cc0wMqvE.s 			page 82
+
+
+4591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCER
+4592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CNT
+4593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_PSC
+4594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_ARR
+4595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_RCR
+4596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR1
+4597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR2
+4598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR3
+4599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR4
+4600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_BDTR
+4601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR3
+4602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR5
+4603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR6
+4604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_DTR2
+4605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_ECR
+4606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_TISEL
+4607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF1
+4608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF2
+4609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_OR
+4610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstRequestSrc TIM DMA Request sources
+4611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+4613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+4614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+4615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+4616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+4617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_COM: TIM Commutation DMA source
+4618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+4619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstBuffer The Buffer address.
+4620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstLength DMA Burst length. This parameter can be one value
+4621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+4622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   This function should be used only when BurstLength is equal to DMA data transfer length
+4623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+4624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+4625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+4626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                               uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint
+4627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+4628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status;
+4629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, B
+4631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                             ((BurstLength) >> 8U) + 1U);
+4632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+4636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+4637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+4639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+4640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+4641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+4642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR1
+4644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR2
+4645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_SMCR
+4646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_DIER
+4647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_SR
+ARM GAS  /tmp/cc0wMqvE.s 			page 83
+
+
+4648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_EGR
+4649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR1
+4650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR2
+4651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCER
+4652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CNT
+4653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_PSC
+4654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_ARR
+4655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_RCR
+4656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR1
+4657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR2
+4658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR3
+4659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR4
+4660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_BDTR
+4661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR3
+4662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR5
+4663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR6
+4664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_DTR2
+4665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_ECR
+4666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_TISEL
+4667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF1
+4668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF2
+4669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_OR
+4670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstRequestSrc TIM DMA Request sources
+4671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+4673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+4674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+4675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+4676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+4677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_COM: TIM Commutation DMA source
+4678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+4679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstBuffer The Buffer address.
+4680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstLength DMA Burst length. This parameter can be one value
+4681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+4682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  DataLength Data length. This parameter can be one value
+4683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         between 1 and 0xFFFF.
+4684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+4685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+4686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddre
+4687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                                    uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+4688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                                    uint32_t  BurstLength,  uint32_t  DataLength)
+4689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+4690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+4693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+4694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+4695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+4696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+4697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+4698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+4700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_BUSY;
+4702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+4704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 84
+
+
+4705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((BurstBuffer == NULL) && (BurstLength > 0U))
+4706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+4708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+4710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+4712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+4715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* nothing to do */
+4717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (BurstRequestSrc)
+4720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_UPDATE:
+4722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA Period elapsed callbacks */
+4724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+4725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+4726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+4728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+4729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+4731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+4732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+4734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+4735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+4736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+4737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC1:
+4740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+4742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+4743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+4744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+4746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+4747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+4749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+4750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+4752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+4753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+4754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+4755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC2:
+4758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+4760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+4761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ARM GAS  /tmp/cc0wMqvE.s 			page 85
+
+
+4762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+4764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+4765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+4767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+4768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+4770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+4771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+4772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+4773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC3:
+4776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+4778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+4779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+4780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+4782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+4783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+4785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+4786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+4788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+4789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+4790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+4791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC4:
+4794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+4796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+4797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+4798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+4800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+4801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+4803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+4804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+4806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+4807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+4808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+4809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_COM:
+4812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA commutation callbacks */
+4814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+4815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+4816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+4818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+ARM GAS  /tmp/cc0wMqvE.s 			page 86
+
+
+4819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+4821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+4822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+4824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+4825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+4826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+4827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_TRIGGER:
+4830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA trigger callbacks */
+4832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+4833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+4834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+4836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+4837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+4839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+4840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+4842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+4843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+4844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+4845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+4848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+4849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+4853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Configure the DMA Burst Mode */
+4855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+4856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the TIM DMA Request */
+4857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+4858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+4861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+4862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+4863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+4865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stops the TIM DMA Burst mode
+4866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+4867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstRequestSrc TIM DMA Request sources to disable
+4868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+4869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+4870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+4871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+4872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+4875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ARM GAS  /tmp/cc0wMqvE.s 			page 87
+
+
+4876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Abort the DMA transfer (at least disable the DMA channel) */
+4878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (BurstRequestSrc)
+4879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_UPDATE:
+4881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+4883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC1:
+4886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+4888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC2:
+4891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+4893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC3:
+4896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+4898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC4:
+4901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+4903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_COM:
+4906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+4908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_TRIGGER:
+4911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+4912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+4913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+4915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+4916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+4917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+4918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+4921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+4922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the TIM Update DMA request */
+4923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+4924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Change the DMA burst operation state */
+4926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+4927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+4928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+4930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+4931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+4932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 88
+
+
+4933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+4934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+4935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+4936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+4937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR1
+4939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR2
+4940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_SMCR
+4941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_DIER
+4942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_SR
+4943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_EGR
+4944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR1
+4945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR2
+4946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCER
+4947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CNT
+4948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_PSC
+4949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_ARR
+4950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_RCR
+4951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR1
+4952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR2
+4953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR3
+4954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR4
+4955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_BDTR
+4956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR3
+4957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR5
+4958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR6
+4959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_DTR2
+4960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_ECR
+4961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_TISEL
+4962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF1
+4963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF2
+4964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_OR
+4965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstRequestSrc TIM DMA Request sources
+4966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+4968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+4969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+4970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+4971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+4972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_COM: TIM Commutation DMA source
+4973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+4974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstBuffer The Buffer address.
+4975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstLength DMA Burst length. This parameter can be one value
+4976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+4977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   This function should be used only when BurstLength is equal to DMA data transfer length
+4978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+4979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+4980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+4981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint
+4982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+4983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status;
+4984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bu
+4986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                            ((BurstLength) >> 8U) + 1U);
+4987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+ARM GAS  /tmp/cc0wMqvE.s 			page 89
+
+
+4990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+4991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+4992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+4993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+4994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+4995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+4996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR1
+4998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR2
+4999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_SMCR
+5000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_DIER
+5001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_SR
+5002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_EGR
+5003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR1
+5004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR2
+5005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCER
+5006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CNT
+5007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_PSC
+5008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_ARR
+5009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_RCR
+5010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR1
+5011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR2
+5012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR3
+5013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR4
+5014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_BDTR
+5015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR3
+5016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR5
+5017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR6
+5018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_DTR2
+5019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_ECR
+5020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_TISEL
+5021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF1
+5022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF2
+5023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMABASE_OR
+5024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstRequestSrc TIM DMA Request sources
+5025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         This parameter can be one of the following values:
+5026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+5027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+5028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+5029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+5030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+5031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_COM: TIM Commutation DMA source
+5032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+5033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstBuffer The Buffer address.
+5034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstLength DMA Burst length. This parameter can be one value
+5035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+5036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  DataLength Data length. This parameter can be one value
+5037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         between 1 and 0xFFFF.
+5038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+5039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddres
+5041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+5042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                                   uint32_t  BurstLength, uint32_t  DataLength)
+5043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+5045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ARM GAS  /tmp/cc0wMqvE.s 			page 90
+
+
+5047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+5048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+5049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+5050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+5051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+5052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+5054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_BUSY;
+5056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+5058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if ((BurstBuffer == NULL) && (BurstLength > 0U))
+5060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       return HAL_ERROR;
+5062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     else
+5064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+5066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+5069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* nothing to do */
+5071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (BurstRequestSrc)
+5073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_UPDATE:
+5075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA Period elapsed callbacks */
+5077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+5078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+5079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+5081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+5082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+5084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_
+5085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+5088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+5089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC1:
+5093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+5095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+5096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+5097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+5099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+5100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+5102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)B
+5103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ARM GAS  /tmp/cc0wMqvE.s 			page 91
+
+
+5104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+5106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+5107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC2:
+5111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+5113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+5114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+5115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+5117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+5118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+5120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)B
+5121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+5124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+5125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC3:
+5129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+5131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+5132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+5133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+5135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+5136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+5138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)B
+5139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+5142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+5143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC4:
+5147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+5149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+5150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+5151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+5153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+5154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+5156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)B
+5157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+5160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+ARM GAS  /tmp/cc0wMqvE.s 			page 92
+
+
+5161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_COM:
+5165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA commutation callbacks */
+5167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+5168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+5169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+5171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+5172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+5174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (ui
+5175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+5178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+5179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_TRIGGER:
+5183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA trigger callbacks */
+5185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+5186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+5187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the DMA error callback */
+5189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+5190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+5192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32
+5193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+5196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+5197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+5201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+5202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+5206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Configure the DMA Burst Mode */
+5208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+5209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the TIM DMA Request */
+5211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+5212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+5215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+5216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 93
+
+
+5218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Stop the DMA burst reading
+5220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+5221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  BurstRequestSrc TIM DMA Request sources to disable.
+5222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+5223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+5225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+5227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+5229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+5230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Abort the DMA transfer (at least disable the DMA channel) */
+5232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (BurstRequestSrc)
+5233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_UPDATE:
+5235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+5237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC1:
+5240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+5242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC2:
+5245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+5247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC3:
+5250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+5252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_CC4:
+5255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+5257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_COM:
+5260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+5262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_DMA_TRIGGER:
+5265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+5267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+5270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+5271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+ARM GAS  /tmp/cc0wMqvE.s 			page 94
+
+
+5275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Disable the TIM Update DMA request */
+5277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+5278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Change the DMA burst operation state */
+5280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+5281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+5284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+5285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Generate a software event
+5289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+5290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  EventSource specifies the event source.
+5291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+5292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+5293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+5294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+5295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+5296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+5297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
+5298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+5299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+5300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+5301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   Basic timers can only generate an update event.
+5302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+5303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+5304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         only for timer instances supporting break input(s).
+5305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+5306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+5309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+5311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+5312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+5313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Process Locked */
+5315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_LOCK(htim);
+5316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change the TIM state */
+5318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+5319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the event sources */
+5321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Instance->EGR = EventSource;
+5322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Change the TIM state */
+5324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+5325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+5327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Return function status */
+5329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+5330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 95
+
+
+5332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configures the OCRef clear feature
+5334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+5335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+5336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         contains the OCREF clear feature and parameters for the TIM peripheral.
+5337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel specifies the TIM Channel
+5338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+5339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1
+5340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2
+5341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3
+5342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4
+5343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5
+5344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6
+5345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+5346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+5348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                            TIM_ClearInputConfigTypeDef *sClearInputConfig,
+5349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                            uint32_t Channel)
+5350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+5352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+5354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+5355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+5356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Process Locked */
+5358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_LOCK(htim);
+5359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+5361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (sClearInputConfig->ClearInputSource)
+5363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLEARINPUTSOURCE_NONE:
+5365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Clear the OCREF clear selection bit and the the ETR Bits */
+5367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (IS_TIM_OCCS_INSTANCE(htim->Instance))
+5368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_EC
+5370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Clear TIMx_AF2_OCRSEL (reset value) */
+5372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
+5373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       else
+5375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP
+5377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLEARINPUTSOURCE_COMP1:
+5382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLEARINPUTSOURCE_COMP2:
+5383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLEARINPUTSOURCE_COMP3:
+5384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLEARINPUTSOURCE_COMP4:
+5385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if defined (COMP5)
+5386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLEARINPUTSOURCE_COMP5:
+5387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* COMP5 */
+5388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if defined (COMP6)
+ARM GAS  /tmp/cc0wMqvE.s 			page 96
+
+
+5389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLEARINPUTSOURCE_COMP6:
+5390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* COMP6 */
+5391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if defined (COMP7)
+5392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLEARINPUTSOURCE_COMP7:
+5393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* COMP7 */
+5394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (IS_TIM_OCCS_INSTANCE(htim->Instance))
+5396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Clear the OCREF clear selection bit */
+5398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+5399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Clear TIM1_AF2_OCRSEL (reset value) */
+5401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource);
+5402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLEARINPUTSOURCE_ETR:
+5407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+5409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+5410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+5411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+5412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+5414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+5415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->State = HAL_TIM_STATE_READY;
+5417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         __HAL_UNLOCK(htim);
+5418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+5419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_ETR_SetConfig(htim->Instance,
+5422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClearInputConfig->ClearInputPrescaler,
+5423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClearInputConfig->ClearInputPolarity,
+5424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClearInputConfig->ClearInputFilter);
+5425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (IS_TIM_OCCS_INSTANCE(htim->Instance))
+5427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Set the OCREF clear selection bit */
+5429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+5430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Clear TIMx_AF2_OCRSEL (reset value) */
+5432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
+5433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+5438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+5439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (status == HAL_OK)
+5443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     switch (Channel)
+5445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ARM GAS  /tmp/cc0wMqvE.s 			page 97
+
+
+5446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case TIM_CHANNEL_1:
+5447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+5449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+5450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Enable the OCREF clear feature for Channel 1 */
+5451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+5452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+5453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         else
+5454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+5455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Disable the OCREF clear feature for Channel 1 */
+5456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+5457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+5458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+5459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case TIM_CHANNEL_2:
+5461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+5463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+5464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Enable the OCREF clear feature for Channel 2 */
+5465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+5466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+5467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         else
+5468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+5469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Disable the OCREF clear feature for Channel 2 */
+5470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+5471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+5472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+5473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case TIM_CHANNEL_3:
+5475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+5477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+5478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Enable the OCREF clear feature for Channel 3 */
+5479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+5480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+5481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         else
+5482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+5483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Disable the OCREF clear feature for Channel 3 */
+5484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+5485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+5486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+5487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case TIM_CHANNEL_4:
+5489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+5491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+5492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Enable the OCREF clear feature for Channel 4 */
+5493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+5494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+5495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         else
+5496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+5497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Disable the OCREF clear feature for Channel 4 */
+5498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+5499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+5500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+5501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case TIM_CHANNEL_5:
+ARM GAS  /tmp/cc0wMqvE.s 			page 98
+
+
+5503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+5505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+5506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Enable the OCREF clear feature for Channel 5 */
+5507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+5508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+5509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         else
+5510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+5511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Disable the OCREF clear feature for Channel 5 */
+5512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+5513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+5514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+5515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case TIM_CHANNEL_6:
+5517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+5518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+5519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+5520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Enable the OCREF clear feature for Channel 6 */
+5521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+5522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+5523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         else
+5524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+5525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           /* Disable the OCREF clear feature for Channel 6 */
+5526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+5527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+5528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+5529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+5530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       default:
+5531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+5532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+5536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+5538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+5540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief   Configures the clock source to be used
+5544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+5545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+5546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         contains the clock source information for the TIM peripheral.
+5547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+5548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClock
+5550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+5552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+5553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Process Locked */
+5555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_LOCK(htim);
+5556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+5558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ARM GAS  /tmp/cc0wMqvE.s 			page 99
+
+
+5560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+5561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+5563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr = htim->Instance->SMCR;
+5564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+5565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+5566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Instance->SMCR = tmpsmcr;
+5567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (sClockSourceConfig->ClockSource)
+5569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_INTERNAL:
+5571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_INSTANCE(htim->Instance));
+5573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ETRMODE1:
+5577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+5579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+5580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check ETR input conditioning related parameters */
+5582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+5583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+5584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+5585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the ETR Clock source */
+5587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_ETR_SetConfig(htim->Instance,
+5588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+5589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockPolarity,
+5590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockFilter);
+5591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Select the External clock mode1 and the ETRF trigger */
+5593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpsmcr = htim->Instance->SMCR;
+5594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+5595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Write to TIMx SMCR */
+5596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->SMCR = tmpsmcr;
+5597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ETRMODE2:
+5601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+5603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+5604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check ETR input conditioning related parameters */
+5606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+5607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+5608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+5609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the ETR Clock source */
+5611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_ETR_SetConfig(htim->Instance,
+5612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+5613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockPolarity,
+5614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockFilter);
+5615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the External clock mode2 */
+5616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->SMCR |= TIM_SMCR_ECE;
+ARM GAS  /tmp/cc0wMqvE.s 			page 100
+
+
+5617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_TI1:
+5621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check whether or not the timer instance supports external clock mode 1 */
+5623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+5624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check TI1 input conditioning related parameters */
+5626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+5627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+5628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_TI1_ConfigInputStage(htim->Instance,
+5630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+5631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockFilter);
+5632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+5633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_TI2:
+5637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+5639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+5640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check TI2 input conditioning related parameters */
+5642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+5643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+5644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_TI2_ConfigInputStage(htim->Instance,
+5646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+5647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockFilter);
+5648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+5649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_TI1ED:
+5653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check whether or not the timer instance supports external clock mode 1 */
+5655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+5656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check TI1 input conditioning related parameters */
+5658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+5659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+5660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_TI1_ConfigInputStage(htim->Instance,
+5662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+5663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockFilter);
+5664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+5665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR0:
+5669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR1:
+5670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR2:
+5671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR3:
+5672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if defined (TIM5)
+5673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR4:
+ARM GAS  /tmp/cc0wMqvE.s 			page 101
+
+
+5674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* TIM5 */
+5675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR5:
+5676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR6:
+5677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR7:
+5678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR8:
+5679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if defined (TIM20)
+5680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR9:
+5681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* TIM20 */
+5682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if defined (HRTIM1)
+5683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR10:
+5684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* HRTIM1 */
+5685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR11:
+5686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check whether or not the timer instance supports internal trigger input */
+5688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
+5689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+5691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+5695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+5696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+5699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+5701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+5703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+5707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         or a XOR combination between CH1_input, CH2_input & CH3_input
+5708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle.
+5709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
+5710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         output of a XOR gate.
+5711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+5712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+5713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+5714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            pins are connected to the TI1 input (XOR combination)
+5715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+5716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+5718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpcr2;
+5720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+5722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+5723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+5724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+5726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpcr2 = htim->Instance->CR2;
+5727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the TI1 selection */
+5729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpcr2 &= ~TIM_CR2_TI1S;
+5730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 102
+
+
+5731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the TI1 selection */
+5732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpcr2 |= TI1_Selection;
+5733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMxCR2 */
+5735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Instance->CR2 = tmpcr2;
+5736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+5738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configures the TIM in Slave mode
+5742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle.
+5743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+5744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         contains the selected trigger (internal trigger input, filtered
+5745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         timer input or external trigger input) and the Slave mode
+5746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset)
+5747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+5748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlav
+5750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+5752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+5753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+5754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
+5755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_LOCK(htim);
+5757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+5759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+5761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_READY;
+5763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+5764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+5765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable Trigger Interrupt */
+5768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+5769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable Trigger DMA request */
+5771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+5772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+5774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+5776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+5778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configures the TIM in Slave mode in interrupt mode
+5782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle.
+5783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+5784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         contains the selected trigger (internal trigger input, filtered
+5785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         timer input or external trigger input) and the Slave mode
+5786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset)
+5787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL status
+ARM GAS  /tmp/cc0wMqvE.s 			page 103
+
+
+5788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+5790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                                 TIM_SlaveConfigTypeDef *sSlaveConfig)
+5791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+5793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+5794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+5795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
+5796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_LOCK(htim);
+5798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+5800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+5802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_READY;
+5804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+5805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+5806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Enable Trigger Interrupt */
+5809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+5810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable Trigger DMA request */
+5812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+5813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+5815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+5817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return HAL_OK;
+5819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Read the captured value from Capture Compare unit
+5823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle.
+5824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+5825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+5826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+5827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+5828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+5829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+5830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval Captured value
+5831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+5833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpreg = 0U;
+5835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (Channel)
+5837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+5838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_1:
+5839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+5841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+5842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Return the capture 1 value */
+5844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpreg =  htim->Instance->CCR1;
+ARM GAS  /tmp/cc0wMqvE.s 			page 104
+
+
+5845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_2:
+5849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+5851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+5852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Return the capture 2 value */
+5854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpreg =   htim->Instance->CCR2;
+5855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_3:
+5860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+5862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+5863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Return the capture 3 value */
+5865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpreg =   htim->Instance->CCR3;
+5866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_CHANNEL_4:
+5871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+5872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+5873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+5874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Return the capture 4 value */
+5876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpreg =   htim->Instance->CCR4;
+5877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+5880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+5882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+5883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+5884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return tmpreg;
+5886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+5890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+5893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *  @brief    TIM Callbacks functions
+5894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+5895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @verbatim
+5896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+5897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         ##### TIM Callbacks functions #####
+5898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+5899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****  [..]
+5900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    This section provides TIM callback functions:
+5901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) TIM Period elapsed callback
+ARM GAS  /tmp/cc0wMqvE.s 			page 105
+
+
+5902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) TIM Output Compare callback
+5903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) TIM Input capture callback
+5904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) TIM Trigger callback
+5905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) TIM Error callback
+5906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) TIM Index callback
+5907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) TIM Direction change callback
+5908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) TIM Index error callback
+5909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    (+) TIM Transition error callback
+5910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @endverbatim
+5912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+5913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Period elapsed callback in non-blocking mode
+5917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+5918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+5919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+5921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+5924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+5927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+5928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Period elapsed half complete callback in non-blocking mode
+5932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+5933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+5934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+5936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+5939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+5942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+5943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Output Compare callback in non-blocking mode
+5947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM OC handle
+5948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+5949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+5951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+5954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+5957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+5958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ARM GAS  /tmp/cc0wMqvE.s 			page 106
+
+
+5959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Input Capture callback in non-blocking mode
+5962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM IC handle
+5963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+5964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+5966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+5969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+5972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+5973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Input Capture half complete callback in non-blocking mode
+5977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM IC handle
+5978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+5979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+5981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+5984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+5987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+5988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+5989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+5990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+5991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  PWM Pulse finished callback in non-blocking mode
+5992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+5993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+5994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+5995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+5996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+5997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+5999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+6001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+6002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+6003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  PWM Pulse finished half complete callback in non-blocking mode
+6007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+6008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+6009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+6011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+6013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+6014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ARM GAS  /tmp/cc0wMqvE.s 			page 107
+
+
+6016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+6017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+6018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Hall Trigger detection callback in non-blocking mode
+6022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+6023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+6024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+6026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+6028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+6029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+6031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_TriggerCallback could be implemented in the user file
+6032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+6033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Hall Trigger detection half complete callback in non-blocking mode
+6037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+6038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+6039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+6041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+6043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+6044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+6046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+6047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+6048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Timer error callback in non-blocking mode
+6052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+6053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+6054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+6056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+6058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   UNUSED(htim);
+6059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+6061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****             the HAL_TIM_ErrorCallback could be implemented in the user file
+6062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****    */
+6063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+6068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param htim tim handle
+6069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param CallbackID ID of the callback to be registered
+6070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        This parameter can be one of the following values:
+6071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+6072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ARM GAS  /tmp/cc0wMqvE.s 			page 108
+
+
+6073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+6074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+6075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+6076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+6077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+6078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+6079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+6080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+6081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+6082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+6083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+6084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+6085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+6086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+6087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+6088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+6089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+6090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+6091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+6092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+6093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callb
+6094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+6095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+6096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+6097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+6098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+6099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
+6100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
+6101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
+6102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
+6103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @param pCallback pointer to the callback function
+6104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @retval status
+6105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Callb
+6107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                            pTIM_CallbackTypeDef pCallback)
+6108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+6110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (pCallback == NULL)
+6112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+6114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Process locked */
+6116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_LOCK(htim);
+6117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_READY)
+6119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     switch (CallbackID)
+6121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+6122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_BASE_MSPINIT_CB_ID :
+6123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Base_MspInitCallback                 = pCallback;
+6124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+6127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Base_MspDeInitCallback               = pCallback;
+6128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 109
+
+
+6130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_IC_MSPINIT_CB_ID :
+6131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_MspInitCallback                   = pCallback;
+6132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_IC_MSPDEINIT_CB_ID :
+6135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_MspDeInitCallback                 = pCallback;
+6136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_OC_MSPINIT_CB_ID :
+6139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_MspInitCallback                   = pCallback;
+6140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_OC_MSPDEINIT_CB_ID :
+6143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_MspDeInitCallback                 = pCallback;
+6144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PWM_MSPINIT_CB_ID :
+6147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_MspInitCallback                  = pCallback;
+6148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+6151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_MspDeInitCallback                = pCallback;
+6152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+6155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OnePulse_MspInitCallback             = pCallback;
+6156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+6159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OnePulse_MspDeInitCallback           = pCallback;
+6160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+6163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Encoder_MspInitCallback              = pCallback;
+6164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+6167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Encoder_MspDeInitCallback            = pCallback;
+6168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+6171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->HallSensor_MspInitCallback           = pCallback;
+6172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+6175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->HallSensor_MspDeInitCallback         = pCallback;
+6176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+6179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PeriodElapsedCallback                = pCallback;
+6180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+6183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PeriodElapsedHalfCpltCallback        = pCallback;
+6184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_TRIGGER_CB_ID :
+ARM GAS  /tmp/cc0wMqvE.s 			page 110
+
+
+6187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->TriggerCallback                      = pCallback;
+6188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_TRIGGER_HALF_CB_ID :
+6191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->TriggerHalfCpltCallback              = pCallback;
+6192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_IC_CAPTURE_CB_ID :
+6195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_CaptureCallback                   = pCallback;
+6196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+6199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_CaptureHalfCpltCallback           = pCallback;
+6200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+6203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_DelayElapsedCallback              = pCallback;
+6204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+6207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_PulseFinishedCallback            = pCallback;
+6208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+6211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+6212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ERROR_CB_ID :
+6215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->ErrorCallback                        = pCallback;
+6216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_COMMUTATION_CB_ID :
+6219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->CommutationCallback                  = pCallback;
+6220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_COMMUTATION_HALF_CB_ID :
+6223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->CommutationHalfCpltCallback          = pCallback;
+6224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_BREAK_CB_ID :
+6227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->BreakCallback                        = pCallback;
+6228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_BREAK2_CB_ID :
+6231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Break2Callback                       = pCallback;
+6232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ENCODER_INDEX_CB_ID :
+6235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->EncoderIndexCallback                 = pCallback;
+6236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_DIRECTION_CHANGE_CB_ID :
+6239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->DirectionChangeCallback              = pCallback;
+6240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_INDEX_ERROR_CB_ID :
+6243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IndexErrorCallback                   = pCallback;
+ARM GAS  /tmp/cc0wMqvE.s 			page 111
+
+
+6244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_TRANSITION_ERROR_CB_ID :
+6247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->TransitionErrorCallback              = pCallback;
+6248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       default :
+6251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+6252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         status = HAL_ERROR;
+6253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+6255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (htim->State == HAL_TIM_STATE_RESET)
+6257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     switch (CallbackID)
+6259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+6260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_BASE_MSPINIT_CB_ID :
+6261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Base_MspInitCallback         = pCallback;
+6262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+6265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Base_MspDeInitCallback       = pCallback;
+6266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_IC_MSPINIT_CB_ID :
+6269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_MspInitCallback           = pCallback;
+6270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_IC_MSPDEINIT_CB_ID :
+6273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_MspDeInitCallback         = pCallback;
+6274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_OC_MSPINIT_CB_ID :
+6277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_MspInitCallback           = pCallback;
+6278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_OC_MSPDEINIT_CB_ID :
+6281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_MspDeInitCallback         = pCallback;
+6282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PWM_MSPINIT_CB_ID :
+6285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_MspInitCallback          = pCallback;
+6286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+6289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_MspDeInitCallback        = pCallback;
+6290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+6293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OnePulse_MspInitCallback     = pCallback;
+6294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+6297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OnePulse_MspDeInitCallback   = pCallback;
+6298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ARM GAS  /tmp/cc0wMqvE.s 			page 112
+
+
+6301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Encoder_MspInitCallback      = pCallback;
+6302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+6305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Encoder_MspDeInitCallback    = pCallback;
+6306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+6309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->HallSensor_MspInitCallback   = pCallback;
+6310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+6313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->HallSensor_MspDeInitCallback = pCallback;
+6314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       default :
+6317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+6318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         status = HAL_ERROR;
+6319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+6321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+6323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Return error status */
+6325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     status = HAL_ERROR;
+6326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Release Lock */
+6329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+6330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+6332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Unregister a TIM callback
+6336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *         TIM callback is redirected to the weak predefined callback
+6337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param htim tim handle
+6338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param CallbackID ID of the callback to be unregistered
+6339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        This parameter can be one of the following values:
+6340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+6341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+6342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+6343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+6344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+6345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+6346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+6347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+6348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+6349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+6350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+6351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+6352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+6353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+6354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+6355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+6356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+6357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+ARM GAS  /tmp/cc0wMqvE.s 			page 113
+
+
+6358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+6359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+6360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+6361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+6362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callb
+6363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+6364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+6365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+6366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+6367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+6368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
+6369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
+6370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
+6371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
+6372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          @retval status
+6373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Cal
+6375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+6377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Process locked */
+6379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_LOCK(htim);
+6380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_READY)
+6382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     switch (CallbackID)
+6384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+6385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_BASE_MSPINIT_CB_ID :
+6386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Base MspInit Callback */
+6387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
+6388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+6391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Base Msp DeInit Callback */
+6392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
+6393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_IC_MSPINIT_CB_ID :
+6396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak IC Msp Init Callback */
+6397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
+6398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_IC_MSPDEINIT_CB_ID :
+6401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak IC Msp DeInit Callback */
+6402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
+6403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_OC_MSPINIT_CB_ID :
+6406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak OC Msp Init Callback */
+6407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
+6408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_OC_MSPDEINIT_CB_ID :
+6411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak OC Msp DeInit Callback */
+6412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
+6413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 114
+
+
+6415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PWM_MSPINIT_CB_ID :
+6416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak PWM Msp Init Callback */
+6417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
+6418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+6421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak PWM Msp DeInit Callback */
+6422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
+6423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+6426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak One Pulse Msp Init Callback */
+6427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
+6428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+6431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak One Pulse Msp DeInit Callback */
+6432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
+6433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+6436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Encoder Msp Init Callback */
+6437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
+6438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+6441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Encoder Msp DeInit Callback */
+6442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
+6443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+6446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Hall Sensor Msp Init Callback */
+6447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
+6448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+6451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Hall Sensor Msp DeInit Callback */
+6452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
+6453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+6456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Period Elapsed Callback */
+6457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+6458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+6461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Period Elapsed half complete Callback */
+6462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+6463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_TRIGGER_CB_ID :
+6466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Trigger Callback */
+6467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+6468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_TRIGGER_HALF_CB_ID :
+6471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Trigger half complete Callback */
+ARM GAS  /tmp/cc0wMqvE.s 			page 115
+
+
+6472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+6473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_IC_CAPTURE_CB_ID :
+6476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak IC Capture Callback */
+6477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+6478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+6481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak IC Capture half complete Callback */
+6482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+6483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+6486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak OC Delay Elapsed Callback */
+6487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+6488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+6491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak PWM Pulse Finished Callback */
+6492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+6493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+6496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak PWM Pulse Finished half complete Callback */
+6497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+6498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ERROR_CB_ID :
+6501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Error Callback */
+6502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+6503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_COMMUTATION_CB_ID :
+6506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Commutation Callback */
+6507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+6508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_COMMUTATION_HALF_CB_ID :
+6511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Commutation half complete Callback */
+6512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+6513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_BREAK_CB_ID :
+6516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Break Callback */
+6517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+6518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_BREAK2_CB_ID :
+6521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Break2 Callback */
+6522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
+6523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ENCODER_INDEX_CB_ID :
+6526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Encoder Index Callback */
+6527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->EncoderIndexCallback              = HAL_TIMEx_EncoderIndexCallback;
+6528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+ARM GAS  /tmp/cc0wMqvE.s 			page 116
+
+
+6529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_DIRECTION_CHANGE_CB_ID :
+6531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Direction Change Callback */
+6532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->DirectionChangeCallback           = HAL_TIMEx_DirectionChangeCallback;
+6533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_INDEX_ERROR_CB_ID :
+6536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Index Error Callback */
+6537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IndexErrorCallback                = HAL_TIMEx_IndexErrorCallback;
+6538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_TRANSITION_ERROR_CB_ID :
+6541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Transition Error Callback */
+6542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->TransitionErrorCallback           = HAL_TIMEx_TransitionErrorCallback;
+6543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       default :
+6546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+6547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         status = HAL_ERROR;
+6548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+6550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (htim->State == HAL_TIM_STATE_RESET)
+6552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     switch (CallbackID)
+6554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+6555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_BASE_MSPINIT_CB_ID :
+6556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Base MspInit Callback */
+6557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
+6558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+6561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Base Msp DeInit Callback */
+6562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
+6563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_IC_MSPINIT_CB_ID :
+6566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak IC Msp Init Callback */
+6567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
+6568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_IC_MSPDEINIT_CB_ID :
+6571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak IC Msp DeInit Callback */
+6572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
+6573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_OC_MSPINIT_CB_ID :
+6576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak OC Msp Init Callback */
+6577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
+6578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_OC_MSPDEINIT_CB_ID :
+6581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak OC Msp DeInit Callback */
+6582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
+6583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PWM_MSPINIT_CB_ID :
+ARM GAS  /tmp/cc0wMqvE.s 			page 117
+
+
+6586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak PWM Msp Init Callback */
+6587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
+6588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+6591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak PWM Msp DeInit Callback */
+6592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
+6593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+6596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak One Pulse Msp Init Callback */
+6597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
+6598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+6601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak One Pulse Msp DeInit Callback */
+6602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
+6603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+6606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Encoder Msp Init Callback */
+6607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
+6608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+6611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Encoder Msp DeInit Callback */
+6612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
+6613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+6616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Hall Sensor Msp Init Callback */
+6617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
+6618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+6621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Legacy weak Hall Sensor Msp DeInit Callback */
+6622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+6623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       default :
+6626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         /* Return error status */
+6627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         status = HAL_ERROR;
+6628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+6629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+6630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+6632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Return error status */
+6634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     status = HAL_ERROR;
+6635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Release Lock */
+6638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+6639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+6641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ARM GAS  /tmp/cc0wMqvE.s 			page 118
+
+
+6643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+6646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+6649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *  @brief   TIM Peripheral State functions
+6650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+6651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @verbatim
+6652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+6653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         ##### Peripheral State functions #####
+6654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   ==============================================================================
+6655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     [..]
+6656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     This subsection permits to get in run-time the status of the peripheral
+6657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     and the data flow.
+6658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** @endverbatim
+6660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+6661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Return the TIM Base handle state.
+6665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Base handle
+6666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL state
+6667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+6669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->State;
+6671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Return the TIM OC handle state.
+6675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+6676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL state
+6677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+6679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->State;
+6681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Return the TIM PWM handle state.
+6685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+6686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL state
+6687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+6689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->State;
+6691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Return the TIM Input Capture handle state.
+6695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM IC handle
+6696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL state
+6697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+6699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ARM GAS  /tmp/cc0wMqvE.s 			page 119
+
+
+6700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->State;
+6701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Return the TIM One Pulse Mode handle state.
+6705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM OPM handle
+6706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL state
+6707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+6709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->State;
+6711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Return the TIM Encoder Mode handle state.
+6715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+6716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval HAL state
+6717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+6719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->State;
+6721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Return the TIM Encoder Mode handle state.
+6725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+6726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval Active channel
+6727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
+6729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->Channel;
+6731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Return actual state of the TIM channel.
+6735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+6736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel TIM Channel
+6737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+6738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1
+6739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2
+6740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3
+6741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4
+6742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5
+6743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6
+6744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval TIM Channel state
+6745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel)
+6747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_state;
+6749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+6751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+6752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+6754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return channel_state;
+6756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ARM GAS  /tmp/cc0wMqvE.s 			page 120
+
+
+6757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Return actual state of a DMA burst operation.
+6760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+6761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval DMA burst state
+6762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
+6764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+6766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+6767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->DMABurstState;
+6769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+6773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @}
+6777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /** @defgroup TIM_Private_Functions TIM Private Functions
+6780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @{
+6781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  TIM DMA error callback
+6785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+6787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** void TIM_DMAError(DMA_HandleTypeDef *hdma)
+6789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+6793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+6795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+6796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+6798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+6800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+6801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+6803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+6805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+6806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+6808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+6810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+6811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+6813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 121
+
+
+6814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_READY;
+6815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->ErrorCallback(htim);
+6819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+6820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ErrorCallback(htim);
+6821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+6824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  TIM DMA Delay Pulse complete callback.
+6828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+6830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+6832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+6836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+6838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+6841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+6842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+6843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+6845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+6847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+6850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+6851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+6852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+6854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+6856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+6859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+6860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+6861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+6863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+6865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+6868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+6869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+6870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ARM GAS  /tmp/cc0wMqvE.s 			page 122
+
+
+6871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+6872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* nothing to do */
+6874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->PWM_PulseFinishedCallback(htim);
+6878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+6879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_PWM_PulseFinishedCallback(htim);
+6880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+6883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  TIM DMA Delay Pulse half complete callback.
+6887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+6889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+6891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+6895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+6897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+6899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+6901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+6903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+6905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+6907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+6909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+6911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* nothing to do */
+6913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->PWM_PulseFinishedHalfCpltCallback(htim);
+6917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+6918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+6919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+6922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  TIM DMA Capture complete callback.
+6926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+ARM GAS  /tmp/cc0wMqvE.s 			page 123
+
+
+6928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+6930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+6934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+6936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+6939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+6940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+6941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+6942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+6944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+6946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+6949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+6950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+6951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+6952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+6954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+6956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+6959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+6960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+6961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+6962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+6964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+6966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+6969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+6970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+6971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+6972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+6974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* nothing to do */
+6976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+6977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->IC_CaptureCallback(htim);
+6980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+6981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_IC_CaptureCallback(htim);
+6982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ARM GAS  /tmp/cc0wMqvE.s 			page 124
+
+
+6985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+6986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+6988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  TIM DMA Capture half complete callback.
+6989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+6991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+6992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+6993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+6994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+6996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+6997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+6998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+6999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+7001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+7003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+7005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+7007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+7009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+7011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+7013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* nothing to do */
+7015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+7018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->IC_CaptureHalfCpltCallback(htim);
+7019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+7020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+7021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+7022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+7024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+7025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  TIM DMA Period Elapse complete callback.
+7028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+7029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+7032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+7033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+7034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
+7036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_READY;
+7038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+7041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->PeriodElapsedCallback(htim);
+ARM GAS  /tmp/cc0wMqvE.s 			page 125
+
+
+7042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+7043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_PeriodElapsedCallback(htim);
+7044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+7045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+7046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  TIM DMA Period Elapse half complete callback.
+7049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+7050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+7053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+7054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+7055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+7057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->PeriodElapsedHalfCpltCallback(htim);
+7058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+7059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+7060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+7061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+7062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  TIM DMA Trigger callback.
+7065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+7066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+7069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+7070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+7071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
+7073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_READY;
+7075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+7078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->TriggerCallback(htim);
+7079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+7080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_TriggerCallback(htim);
+7081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+7082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+7083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  TIM DMA Trigger half complete callback.
+7086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+7087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+7090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+7091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+7092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+7094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->TriggerHalfCpltCallback(htim);
+7095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #else
+7096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_TriggerHalfCpltCallback(htim);
+7097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+7098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ARM GAS  /tmp/cc0wMqvE.s 			page 126
+
+
+7099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Time Base configuration
+7102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx TIM peripheral
+7103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Structure TIM Base configuration structure
+7104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+7107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+7108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpcr1;
+7109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpcr1 = TIMx->CR1;
+7110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set TIM Time Base Unit parameters ---------------------------------------*/
+7112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+7113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Select the Counter Mode */
+7115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+7116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr1 |= Structure->CounterMode;
+7117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+7120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the clock division */
+7122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr1 &= ~TIM_CR1_CKD;
+7123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr1 |= (uint32_t)Structure->ClockDivision;
+7124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the auto-reload preload */
+7127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+7128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CR1 = tmpcr1;
+7130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Autoreload value */
+7132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->ARR = (uint32_t)Structure->Period ;
+7133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Prescaler value */
+7135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->PSC = Structure->Prescaler;
+7136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+7138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Repetition Counter value */
+7140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIMx->RCR = Structure->RepetitionCounter;
+7141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Generate an update event to reload the Prescaler
+7144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****      and the repetition counter (only for advanced timer) value immediately */
+7145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->EGR = TIM_EGR_UG;
+7146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+7147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Timer Output Compare 1 configuration
+7150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  OC_Config The output configuration structure
+7152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+7155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ARM GAS  /tmp/cc0wMqvE.s 			page 127
+
+
+  29              		.loc 1 7155 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+  34              		.loc 1 7155 1 is_stmt 0 view .LVU1
+  35 0000 30B4     		push	{r4, r5}
+  36              	.LCFI0:
+  37              		.cfi_def_cfa_offset 8
+  38              		.cfi_offset 4, -8
+  39              		.cfi_offset 5, -4
+7156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmrx;
+  40              		.loc 1 7156 3 is_stmt 1 view .LVU2
+7157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+  41              		.loc 1 7157 3 view .LVU3
+7158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpcr2;
+  42              		.loc 1 7158 3 view .LVU4
+7159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Channel 1: Reset the CC1E Bit */
+7161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC1E;
+  43              		.loc 1 7161 3 view .LVU5
+  44              		.loc 1 7161 7 is_stmt 0 view .LVU6
+  45 0002 036A     		ldr	r3, [r0, #32]
+  46              		.loc 1 7161 14 view .LVU7
+  47 0004 23F00103 		bic	r3, r3, #1
+  48 0008 0362     		str	r3, [r0, #32]
+7162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+7164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+  49              		.loc 1 7164 3 is_stmt 1 view .LVU8
+  50              		.loc 1 7164 11 is_stmt 0 view .LVU9
+  51 000a 026A     		ldr	r2, [r0, #32]
+  52              	.LVL1:
+7165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+7166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpcr2 =  TIMx->CR2;
+  53              		.loc 1 7166 3 is_stmt 1 view .LVU10
+  54              		.loc 1 7166 10 is_stmt 0 view .LVU11
+  55 000c 4468     		ldr	r4, [r0, #4]
+  56              	.LVL2:
+7167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCMR1 register value */
+7169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx = TIMx->CCMR1;
+  57              		.loc 1 7169 3 is_stmt 1 view .LVU12
+  58              		.loc 1 7169 12 is_stmt 0 view .LVU13
+  59 000e 8369     		ldr	r3, [r0, #24]
+  60              	.LVL3:
+7170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Output Compare Mode Bits */
+7172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR1_OC1M;
+  61              		.loc 1 7172 3 is_stmt 1 view .LVU14
+7173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR1_CC1S;
+  62              		.loc 1 7173 3 view .LVU15
+  63              		.loc 1 7173 12 is_stmt 0 view .LVU16
+  64 0010 23F48033 		bic	r3, r3, #65536
+  65              	.LVL4:
+  66              		.loc 1 7173 12 view .LVU17
+  67 0014 23F07303 		bic	r3, r3, #115
+ARM GAS  /tmp/cc0wMqvE.s 			page 128
+
+
+  68              	.LVL5:
+7174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Output Compare Mode */
+7175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx |= OC_Config->OCMode;
+  69              		.loc 1 7175 3 is_stmt 1 view .LVU18
+  70              		.loc 1 7175 24 is_stmt 0 view .LVU19
+  71 0018 0D68     		ldr	r5, [r1]
+  72              		.loc 1 7175 12 view .LVU20
+  73 001a 1D43     		orrs	r5, r5, r3
+  74              	.LVL6:
+7176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Output Polarity level */
+7178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~TIM_CCER_CC1P;
+  75              		.loc 1 7178 3 is_stmt 1 view .LVU21
+  76              		.loc 1 7178 11 is_stmt 0 view .LVU22
+  77 001c 22F00202 		bic	r2, r2, #2
+  78              	.LVL7:
+7179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+7180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= OC_Config->OCPolarity;
+  79              		.loc 1 7180 3 is_stmt 1 view .LVU23
+  80              		.loc 1 7180 23 is_stmt 0 view .LVU24
+  81 0020 8B68     		ldr	r3, [r1, #8]
+  82              		.loc 1 7180 11 view .LVU25
+  83 0022 1343     		orrs	r3, r3, r2
+  84              	.LVL8:
+7181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  85              		.loc 1 7182 3 is_stmt 1 view .LVU26
+  86              		.loc 1 7182 6 is_stmt 0 view .LVU27
+  87 0024 1C4A     		ldr	r2, .L7
+  88 0026 9042     		cmp	r0, r2
+  89 0028 0FD0     		beq	.L2
+  90              		.loc 1 7182 7 discriminator 1 view .LVU28
+  91 002a 02F50062 		add	r2, r2, #2048
+  92 002e 9042     		cmp	r0, r2
+  93 0030 0BD0     		beq	.L2
+  94              		.loc 1 7182 7 discriminator 2 view .LVU29
+  95 0032 02F54062 		add	r2, r2, #3072
+  96 0036 9042     		cmp	r0, r2
+  97 0038 07D0     		beq	.L2
+  98              		.loc 1 7182 7 discriminator 3 view .LVU30
+  99 003a 02F58062 		add	r2, r2, #1024
+ 100 003e 9042     		cmp	r0, r2
+ 101 0040 03D0     		beq	.L2
+ 102              		.loc 1 7182 7 discriminator 4 view .LVU31
+ 103 0042 02F58062 		add	r2, r2, #1024
+ 104 0046 9042     		cmp	r0, r2
+ 105 0048 05D1     		bne	.L3
+ 106              	.L2:
+7183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Check parameters */
+7185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+ 107              		.loc 1 7185 5 is_stmt 1 view .LVU32
+7186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output N Polarity level */
+7188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC1NP;
+ 108              		.loc 1 7188 5 view .LVU33
+ 109              		.loc 1 7188 13 is_stmt 0 view .LVU34
+ARM GAS  /tmp/cc0wMqvE.s 			page 129
+
+
+ 110 004a 23F00803 		bic	r3, r3, #8
+ 111              	.LVL9:
+7189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Polarity */
+7190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccer |= OC_Config->OCNPolarity;
+ 112              		.loc 1 7190 5 is_stmt 1 view .LVU35
+ 113              		.loc 1 7190 25 is_stmt 0 view .LVU36
+ 114 004e CA68     		ldr	r2, [r1, #12]
+ 115              		.loc 1 7190 13 view .LVU37
+ 116 0050 1A43     		orrs	r2, r2, r3
+ 117              	.LVL10:
+7191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output N State */
+7192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC1NE;
+ 118              		.loc 1 7192 5 is_stmt 1 view .LVU38
+ 119              		.loc 1 7192 13 is_stmt 0 view .LVU39
+ 120 0052 22F00403 		bic	r3, r2, #4
+ 121              	.LVL11:
+ 122              	.L3:
+7193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 123              		.loc 1 7195 3 is_stmt 1 view .LVU40
+ 124              		.loc 1 7195 6 is_stmt 0 view .LVU41
+ 125 0056 104A     		ldr	r2, .L7
+ 126 0058 9042     		cmp	r0, r2
+ 127 005a 0FD0     		beq	.L4
+ 128              		.loc 1 7195 7 discriminator 1 view .LVU42
+ 129 005c 02F50062 		add	r2, r2, #2048
+ 130 0060 9042     		cmp	r0, r2
+ 131 0062 0BD0     		beq	.L4
+ 132              		.loc 1 7195 7 discriminator 2 view .LVU43
+ 133 0064 02F54062 		add	r2, r2, #3072
+ 134 0068 9042     		cmp	r0, r2
+ 135 006a 07D0     		beq	.L4
+ 136              		.loc 1 7195 7 discriminator 3 view .LVU44
+ 137 006c 02F58062 		add	r2, r2, #1024
+ 138 0070 9042     		cmp	r0, r2
+ 139 0072 03D0     		beq	.L4
+ 140              		.loc 1 7195 7 discriminator 4 view .LVU45
+ 141 0074 02F58062 		add	r2, r2, #1024
+ 142 0078 9042     		cmp	r0, r2
+ 143 007a 05D1     		bne	.L5
+ 144              	.L4:
+7196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Check parameters */
+7198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ 145              		.loc 1 7198 5 is_stmt 1 view .LVU46
+7199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+ 146              		.loc 1 7199 5 view .LVU47
+7200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output Compare and Output Compare N IDLE State */
+7202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS1;
+ 147              		.loc 1 7202 5 view .LVU48
+ 148              	.LVL12:
+7203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS1N;
+ 149              		.loc 1 7203 5 view .LVU49
+ 150              		.loc 1 7203 12 is_stmt 0 view .LVU50
+ 151 007c 24F44074 		bic	r4, r4, #768
+ARM GAS  /tmp/cc0wMqvE.s 			page 130
+
+
+ 152              	.LVL13:
+7204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output Idle state */
+7205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 |= OC_Config->OCIdleState;
+ 153              		.loc 1 7205 5 is_stmt 1 view .LVU51
+ 154              		.loc 1 7205 24 is_stmt 0 view .LVU52
+ 155 0080 4A69     		ldr	r2, [r1, #20]
+ 156              		.loc 1 7205 12 view .LVU53
+ 157 0082 2243     		orrs	r2, r2, r4
+ 158              	.LVL14:
+7206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Idle state */
+7207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 |= OC_Config->OCNIdleState;
+ 159              		.loc 1 7207 5 is_stmt 1 view .LVU54
+ 160              		.loc 1 7207 24 is_stmt 0 view .LVU55
+ 161 0084 8C69     		ldr	r4, [r1, #24]
+ 162              		.loc 1 7207 12 view .LVU56
+ 163 0086 1443     		orrs	r4, r4, r2
+ 164              	.LVL15:
+ 165              	.L5:
+7208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CR2 */
+7211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CR2 = tmpcr2;
+ 166              		.loc 1 7211 3 is_stmt 1 view .LVU57
+ 167              		.loc 1 7211 13 is_stmt 0 view .LVU58
+ 168 0088 4460     		str	r4, [r0, #4]
+7212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR1 */
+7214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCMR1 = tmpccmrx;
+ 169              		.loc 1 7214 3 is_stmt 1 view .LVU59
+ 170              		.loc 1 7214 15 is_stmt 0 view .LVU60
+ 171 008a 8561     		str	r5, [r0, #24]
+7215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Capture Compare Register value */
+7217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCR1 = OC_Config->Pulse;
+ 172              		.loc 1 7217 3 is_stmt 1 view .LVU61
+ 173              		.loc 1 7217 25 is_stmt 0 view .LVU62
+ 174 008c 4A68     		ldr	r2, [r1, #4]
+ 175              		.loc 1 7217 14 view .LVU63
+ 176 008e 4263     		str	r2, [r0, #52]
+7218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCER */
+7220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 177              		.loc 1 7220 3 is_stmt 1 view .LVU64
+ 178              		.loc 1 7220 14 is_stmt 0 view .LVU65
+ 179 0090 0362     		str	r3, [r0, #32]
+7221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 180              		.loc 1 7221 1 view .LVU66
+ 181 0092 30BC     		pop	{r4, r5}
+ 182              	.LCFI1:
+ 183              		.cfi_restore 5
+ 184              		.cfi_restore 4
+ 185              		.cfi_def_cfa_offset 0
+ 186              	.LVL16:
+ 187              		.loc 1 7221 1 view .LVU67
+ 188 0094 7047     		bx	lr
+ 189              	.L8:
+ 190 0096 00BF     		.align	2
+ARM GAS  /tmp/cc0wMqvE.s 			page 131
+
+
+ 191              	.L7:
+ 192 0098 002C0140 		.word	1073818624
+ 193              		.cfi_endproc
+ 194              	.LFE434:
+ 196              		.section	.text.TIM_OC3_SetConfig,"ax",%progbits
+ 197              		.align	1
+ 198              		.syntax unified
+ 199              		.thumb
+ 200              		.thumb_func
+ 202              	TIM_OC3_SetConfig:
+ 203              	.LVL17:
+ 204              	.LFB436:
+7222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Timer Output Compare 2 configuration
+7225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  OC_Config The output configuration structure
+7227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+7230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+7231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmrx;
+7232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+7233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpcr2;
+7234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Channel 2: Reset the CC2E Bit */
+7236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC2E;
+7237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+7239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+7240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+7241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpcr2 =  TIMx->CR2;
+7242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCMR1 register value */
+7244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx = TIMx->CCMR1;
+7245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Output Compare mode and Capture/Compare selection Bits */
+7247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR1_OC2M;
+7248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR1_CC2S;
+7249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Output Compare Mode */
+7251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx |= (OC_Config->OCMode << 8U);
+7252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Output Polarity level */
+7254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~TIM_CCER_CC2P;
+7255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+7256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= (OC_Config->OCPolarity << 4U);
+7257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+7259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+7261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output N Polarity level */
+7263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC2NP;
+7264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Polarity */
+7265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccer |= (OC_Config->OCNPolarity << 4U);
+7266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output N State */
+ARM GAS  /tmp/cc0wMqvE.s 			page 132
+
+
+7267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC2NE;
+7268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+7272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Check parameters */
+7274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+7275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+7276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output Compare and Output Compare N IDLE State */
+7278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS2;
+7279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS2N;
+7280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output Idle state */
+7281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCIdleState << 2U);
+7282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Idle state */
+7283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+7284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CR2 */
+7287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CR2 = tmpcr2;
+7288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR1 */
+7290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCMR1 = tmpccmrx;
+7291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Capture Compare Register value */
+7293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCR2 = OC_Config->Pulse;
+7294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCER */
+7296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+7297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+7298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Timer Output Compare 3 configuration
+7301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  OC_Config The output configuration structure
+7303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+7306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 205              		.loc 1 7306 1 is_stmt 1 view -0
+ 206              		.cfi_startproc
+ 207              		@ args = 0, pretend = 0, frame = 0
+ 208              		@ frame_needed = 0, uses_anonymous_args = 0
+ 209              		@ link register save eliminated.
+ 210              		.loc 1 7306 1 is_stmt 0 view .LVU69
+ 211 0000 30B4     		push	{r4, r5}
+ 212              	.LCFI2:
+ 213              		.cfi_def_cfa_offset 8
+ 214              		.cfi_offset 4, -8
+ 215              		.cfi_offset 5, -4
+7307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmrx;
+ 216              		.loc 1 7307 3 is_stmt 1 view .LVU70
+7308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ 217              		.loc 1 7308 3 view .LVU71
+7309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpcr2;
+ 218              		.loc 1 7309 3 view .LVU72
+ARM GAS  /tmp/cc0wMqvE.s 			page 133
+
+
+7310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Channel 3: Reset the CC2E Bit */
+7312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC3E;
+ 219              		.loc 1 7312 3 view .LVU73
+ 220              		.loc 1 7312 7 is_stmt 0 view .LVU74
+ 221 0002 036A     		ldr	r3, [r0, #32]
+ 222              		.loc 1 7312 14 view .LVU75
+ 223 0004 23F48073 		bic	r3, r3, #256
+ 224 0008 0362     		str	r3, [r0, #32]
+7313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+7315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 225              		.loc 1 7315 3 is_stmt 1 view .LVU76
+ 226              		.loc 1 7315 11 is_stmt 0 view .LVU77
+ 227 000a 036A     		ldr	r3, [r0, #32]
+ 228              	.LVL18:
+7316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+7317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpcr2 =  TIMx->CR2;
+ 229              		.loc 1 7317 3 is_stmt 1 view .LVU78
+ 230              		.loc 1 7317 10 is_stmt 0 view .LVU79
+ 231 000c 4468     		ldr	r4, [r0, #4]
+ 232              	.LVL19:
+7318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCMR2 register value */
+7320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx = TIMx->CCMR2;
+ 233              		.loc 1 7320 3 is_stmt 1 view .LVU80
+ 234              		.loc 1 7320 12 is_stmt 0 view .LVU81
+ 235 000e C269     		ldr	r2, [r0, #28]
+ 236              	.LVL20:
+7321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Output Compare mode and Capture/Compare selection Bits */
+7323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR2_OC3M;
+ 237              		.loc 1 7323 3 is_stmt 1 view .LVU82
+7324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR2_CC3S;
+ 238              		.loc 1 7324 3 view .LVU83
+ 239              		.loc 1 7324 12 is_stmt 0 view .LVU84
+ 240 0010 22F48032 		bic	r2, r2, #65536
+ 241              	.LVL21:
+ 242              		.loc 1 7324 12 view .LVU85
+ 243 0014 22F07302 		bic	r2, r2, #115
+ 244              	.LVL22:
+7325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Output Compare Mode */
+7326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx |= OC_Config->OCMode;
+ 245              		.loc 1 7326 3 is_stmt 1 view .LVU86
+ 246              		.loc 1 7326 24 is_stmt 0 view .LVU87
+ 247 0018 0D68     		ldr	r5, [r1]
+ 248              		.loc 1 7326 12 view .LVU88
+ 249 001a 1543     		orrs	r5, r5, r2
+ 250              	.LVL23:
+7327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Output Polarity level */
+7329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~TIM_CCER_CC3P;
+ 251              		.loc 1 7329 3 is_stmt 1 view .LVU89
+ 252              		.loc 1 7329 11 is_stmt 0 view .LVU90
+ 253 001c 23F40073 		bic	r3, r3, #512
+ 254              	.LVL24:
+7330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+ARM GAS  /tmp/cc0wMqvE.s 			page 134
+
+
+7331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= (OC_Config->OCPolarity << 8U);
+ 255              		.loc 1 7331 3 is_stmt 1 view .LVU91
+ 256              		.loc 1 7331 24 is_stmt 0 view .LVU92
+ 257 0020 8A68     		ldr	r2, [r1, #8]
+ 258              		.loc 1 7331 11 view .LVU93
+ 259 0022 43EA0223 		orr	r3, r3, r2, lsl #8
+ 260              	.LVL25:
+7332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+ 261              		.loc 1 7333 3 is_stmt 1 view .LVU94
+ 262              		.loc 1 7333 6 is_stmt 0 view .LVU95
+ 263 0026 184A     		ldr	r2, .L15
+ 264 0028 9042     		cmp	r0, r2
+ 265 002a 03D0     		beq	.L10
+ 266              		.loc 1 7333 7 discriminator 1 view .LVU96
+ 267 002c 02F50062 		add	r2, r2, #2048
+ 268 0030 9042     		cmp	r0, r2
+ 269 0032 06D1     		bne	.L11
+ 270              	.L10:
+7334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+ 271              		.loc 1 7335 5 is_stmt 1 view .LVU97
+7336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output N Polarity level */
+7338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC3NP;
+ 272              		.loc 1 7338 5 view .LVU98
+ 273              		.loc 1 7338 13 is_stmt 0 view .LVU99
+ 274 0034 23F40063 		bic	r3, r3, #2048
+ 275              	.LVL26:
+7339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Polarity */
+7340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccer |= (OC_Config->OCNPolarity << 8U);
+ 276              		.loc 1 7340 5 is_stmt 1 view .LVU100
+ 277              		.loc 1 7340 26 is_stmt 0 view .LVU101
+ 278 0038 CA68     		ldr	r2, [r1, #12]
+ 279              		.loc 1 7340 13 view .LVU102
+ 280 003a 43EA0223 		orr	r3, r3, r2, lsl #8
+ 281              	.LVL27:
+7341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output N State */
+7342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC3NE;
+ 282              		.loc 1 7342 5 is_stmt 1 view .LVU103
+ 283              		.loc 1 7342 13 is_stmt 0 view .LVU104
+ 284 003e 23F48063 		bic	r3, r3, #1024
+ 285              	.LVL28:
+ 286              	.L11:
+7343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 287              		.loc 1 7345 3 is_stmt 1 view .LVU105
+ 288              		.loc 1 7345 6 is_stmt 0 view .LVU106
+ 289 0042 114A     		ldr	r2, .L15
+ 290 0044 9042     		cmp	r0, r2
+ 291 0046 0FD0     		beq	.L12
+ 292              		.loc 1 7345 7 discriminator 1 view .LVU107
+ 293 0048 02F50062 		add	r2, r2, #2048
+ 294 004c 9042     		cmp	r0, r2
+ 295 004e 0BD0     		beq	.L12
+ 296              		.loc 1 7345 7 discriminator 2 view .LVU108
+ARM GAS  /tmp/cc0wMqvE.s 			page 135
+
+
+ 297 0050 02F54062 		add	r2, r2, #3072
+ 298 0054 9042     		cmp	r0, r2
+ 299 0056 07D0     		beq	.L12
+ 300              		.loc 1 7345 7 discriminator 3 view .LVU109
+ 301 0058 02F58062 		add	r2, r2, #1024
+ 302 005c 9042     		cmp	r0, r2
+ 303 005e 03D0     		beq	.L12
+ 304              		.loc 1 7345 7 discriminator 4 view .LVU110
+ 305 0060 02F58062 		add	r2, r2, #1024
+ 306 0064 9042     		cmp	r0, r2
+ 307 0066 07D1     		bne	.L13
+ 308              	.L12:
+7346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Check parameters */
+7348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ 309              		.loc 1 7348 5 is_stmt 1 view .LVU111
+7349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+ 310              		.loc 1 7349 5 view .LVU112
+7350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output Compare and Output Compare N IDLE State */
+7352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS3;
+ 311              		.loc 1 7352 5 view .LVU113
+ 312              	.LVL29:
+7353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS3N;
+ 313              		.loc 1 7353 5 view .LVU114
+ 314              		.loc 1 7353 12 is_stmt 0 view .LVU115
+ 315 0068 24F44052 		bic	r2, r4, #12288
+ 316              	.LVL30:
+7354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output Idle state */
+7355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCIdleState << 4U);
+ 317              		.loc 1 7355 5 is_stmt 1 view .LVU116
+ 318              		.loc 1 7355 25 is_stmt 0 view .LVU117
+ 319 006c 4C69     		ldr	r4, [r1, #20]
+ 320              		.loc 1 7355 12 view .LVU118
+ 321 006e 42EA0412 		orr	r2, r2, r4, lsl #4
+ 322              	.LVL31:
+7356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Idle state */
+7357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+ 323              		.loc 1 7357 5 is_stmt 1 view .LVU119
+ 324              		.loc 1 7357 25 is_stmt 0 view .LVU120
+ 325 0072 8C69     		ldr	r4, [r1, #24]
+ 326              		.loc 1 7357 12 view .LVU121
+ 327 0074 42EA0414 		orr	r4, r2, r4, lsl #4
+ 328              	.LVL32:
+ 329              	.L13:
+7358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CR2 */
+7361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CR2 = tmpcr2;
+ 330              		.loc 1 7361 3 is_stmt 1 view .LVU122
+ 331              		.loc 1 7361 13 is_stmt 0 view .LVU123
+ 332 0078 4460     		str	r4, [r0, #4]
+7362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR2 */
+7364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCMR2 = tmpccmrx;
+ 333              		.loc 1 7364 3 is_stmt 1 view .LVU124
+ 334              		.loc 1 7364 15 is_stmt 0 view .LVU125
+ARM GAS  /tmp/cc0wMqvE.s 			page 136
+
+
+ 335 007a C561     		str	r5, [r0, #28]
+7365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Capture Compare Register value */
+7367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCR3 = OC_Config->Pulse;
+ 336              		.loc 1 7367 3 is_stmt 1 view .LVU126
+ 337              		.loc 1 7367 25 is_stmt 0 view .LVU127
+ 338 007c 4A68     		ldr	r2, [r1, #4]
+ 339              		.loc 1 7367 14 view .LVU128
+ 340 007e C263     		str	r2, [r0, #60]
+7368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCER */
+7370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 341              		.loc 1 7370 3 is_stmt 1 view .LVU129
+ 342              		.loc 1 7370 14 is_stmt 0 view .LVU130
+ 343 0080 0362     		str	r3, [r0, #32]
+7371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 344              		.loc 1 7371 1 view .LVU131
+ 345 0082 30BC     		pop	{r4, r5}
+ 346              	.LCFI3:
+ 347              		.cfi_restore 5
+ 348              		.cfi_restore 4
+ 349              		.cfi_def_cfa_offset 0
+ 350              	.LVL33:
+ 351              		.loc 1 7371 1 view .LVU132
+ 352 0084 7047     		bx	lr
+ 353              	.L16:
+ 354 0086 00BF     		.align	2
+ 355              	.L15:
+ 356 0088 002C0140 		.word	1073818624
+ 357              		.cfi_endproc
+ 358              	.LFE436:
+ 360              		.section	.text.TIM_OC4_SetConfig,"ax",%progbits
+ 361              		.align	1
+ 362              		.syntax unified
+ 363              		.thumb
+ 364              		.thumb_func
+ 366              	TIM_OC4_SetConfig:
+ 367              	.LVL34:
+ 368              	.LFB437:
+7372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Timer Output Compare 4 configuration
+7375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  OC_Config The output configuration structure
+7377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+7380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 369              		.loc 1 7380 1 is_stmt 1 view -0
+ 370              		.cfi_startproc
+ 371              		@ args = 0, pretend = 0, frame = 0
+ 372              		@ frame_needed = 0, uses_anonymous_args = 0
+ 373              		@ link register save eliminated.
+ 374              		.loc 1 7380 1 is_stmt 0 view .LVU134
+ 375 0000 30B4     		push	{r4, r5}
+ 376              	.LCFI4:
+ 377              		.cfi_def_cfa_offset 8
+ARM GAS  /tmp/cc0wMqvE.s 			page 137
+
+
+ 378              		.cfi_offset 4, -8
+ 379              		.cfi_offset 5, -4
+7381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmrx;
+ 380              		.loc 1 7381 3 is_stmt 1 view .LVU135
+7382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ 381              		.loc 1 7382 3 view .LVU136
+7383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpcr2;
+ 382              		.loc 1 7383 3 view .LVU137
+7384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Channel 4: Reset the CC4E Bit */
+7386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC4E;
+ 383              		.loc 1 7386 3 view .LVU138
+ 384              		.loc 1 7386 7 is_stmt 0 view .LVU139
+ 385 0002 036A     		ldr	r3, [r0, #32]
+ 386              		.loc 1 7386 14 view .LVU140
+ 387 0004 23F48053 		bic	r3, r3, #4096
+ 388 0008 0362     		str	r3, [r0, #32]
+7387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+7389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 389              		.loc 1 7389 3 is_stmt 1 view .LVU141
+ 390              		.loc 1 7389 11 is_stmt 0 view .LVU142
+ 391 000a 036A     		ldr	r3, [r0, #32]
+ 392              	.LVL35:
+7390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+7391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpcr2 =  TIMx->CR2;
+ 393              		.loc 1 7391 3 is_stmt 1 view .LVU143
+ 394              		.loc 1 7391 10 is_stmt 0 view .LVU144
+ 395 000c 4468     		ldr	r4, [r0, #4]
+ 396              	.LVL36:
+7392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCMR2 register value */
+7394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx = TIMx->CCMR2;
+ 397              		.loc 1 7394 3 is_stmt 1 view .LVU145
+ 398              		.loc 1 7394 12 is_stmt 0 view .LVU146
+ 399 000e C269     		ldr	r2, [r0, #28]
+ 400              	.LVL37:
+7395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Output Compare mode and Capture/Compare selection Bits */
+7397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR2_OC4M;
+ 401              		.loc 1 7397 3 is_stmt 1 view .LVU147
+7398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR2_CC4S;
+ 402              		.loc 1 7398 3 view .LVU148
+ 403              		.loc 1 7398 12 is_stmt 0 view .LVU149
+ 404 0010 22F08072 		bic	r2, r2, #16777216
+ 405              	.LVL38:
+ 406              		.loc 1 7398 12 view .LVU150
+ 407 0014 22F4E642 		bic	r2, r2, #29440
+ 408              	.LVL39:
+7399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Output Compare Mode */
+7401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx |= (OC_Config->OCMode << 8U);
+ 409              		.loc 1 7401 3 is_stmt 1 view .LVU151
+ 410              		.loc 1 7401 25 is_stmt 0 view .LVU152
+ 411 0018 0D68     		ldr	r5, [r1]
+ 412              		.loc 1 7401 12 view .LVU153
+ 413 001a 42EA0522 		orr	r2, r2, r5, lsl #8
+ARM GAS  /tmp/cc0wMqvE.s 			page 138
+
+
+ 414              	.LVL40:
+7402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Output Polarity level */
+7404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~TIM_CCER_CC4P;
+ 415              		.loc 1 7404 3 is_stmt 1 view .LVU154
+ 416              		.loc 1 7404 11 is_stmt 0 view .LVU155
+ 417 001e 23F40053 		bic	r3, r3, #8192
+ 418              	.LVL41:
+7405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+7406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= (OC_Config->OCPolarity << 12U);
+ 419              		.loc 1 7406 3 is_stmt 1 view .LVU156
+ 420              		.loc 1 7406 24 is_stmt 0 view .LVU157
+ 421 0022 8D68     		ldr	r5, [r1, #8]
+ 422              		.loc 1 7406 11 view .LVU158
+ 423 0024 43EA0533 		orr	r3, r3, r5, lsl #12
+ 424              	.LVL42:
+7407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
+ 425              		.loc 1 7408 3 is_stmt 1 view .LVU159
+ 426              		.loc 1 7408 6 is_stmt 0 view .LVU160
+ 427 0028 174D     		ldr	r5, .L23
+ 428 002a A842     		cmp	r0, r5
+ 429 002c 03D0     		beq	.L18
+ 430              		.loc 1 7408 7 discriminator 1 view .LVU161
+ 431 002e 05F50065 		add	r5, r5, #2048
+ 432 0032 A842     		cmp	r0, r5
+ 433 0034 06D1     		bne	.L19
+ 434              	.L18:
+7409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+ 435              		.loc 1 7410 5 is_stmt 1 view .LVU162
+7411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output N Polarity level */
+7413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC4NP;
+ 436              		.loc 1 7413 5 view .LVU163
+ 437              		.loc 1 7413 13 is_stmt 0 view .LVU164
+ 438 0036 23F40043 		bic	r3, r3, #32768
+ 439              	.LVL43:
+7414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Polarity */
+7415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccer |= (OC_Config->OCNPolarity << 12U);
+ 440              		.loc 1 7415 5 is_stmt 1 view .LVU165
+ 441              		.loc 1 7415 26 is_stmt 0 view .LVU166
+ 442 003a CD68     		ldr	r5, [r1, #12]
+ 443              		.loc 1 7415 13 view .LVU167
+ 444 003c 43EA0533 		orr	r3, r3, r5, lsl #12
+ 445              	.LVL44:
+7416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output N State */
+7417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC4NE;
+ 446              		.loc 1 7417 5 is_stmt 1 view .LVU168
+ 447              		.loc 1 7417 13 is_stmt 0 view .LVU169
+ 448 0040 23F48043 		bic	r3, r3, #16384
+ 449              	.LVL45:
+ 450              	.L19:
+7418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 451              		.loc 1 7420 3 is_stmt 1 view .LVU170
+ARM GAS  /tmp/cc0wMqvE.s 			page 139
+
+
+ 452              		.loc 1 7420 6 is_stmt 0 view .LVU171
+ 453 0044 104D     		ldr	r5, .L23
+ 454 0046 A842     		cmp	r0, r5
+ 455 0048 0FD0     		beq	.L20
+ 456              		.loc 1 7420 7 discriminator 1 view .LVU172
+ 457 004a 05F50065 		add	r5, r5, #2048
+ 458 004e A842     		cmp	r0, r5
+ 459 0050 0BD0     		beq	.L20
+ 460              		.loc 1 7420 7 discriminator 2 view .LVU173
+ 461 0052 05F54065 		add	r5, r5, #3072
+ 462 0056 A842     		cmp	r0, r5
+ 463 0058 07D0     		beq	.L20
+ 464              		.loc 1 7420 7 discriminator 3 view .LVU174
+ 465 005a 05F58065 		add	r5, r5, #1024
+ 466 005e A842     		cmp	r0, r5
+ 467 0060 03D0     		beq	.L20
+ 468              		.loc 1 7420 7 discriminator 4 view .LVU175
+ 469 0062 05F58065 		add	r5, r5, #1024
+ 470 0066 A842     		cmp	r0, r5
+ 471 0068 07D1     		bne	.L21
+ 472              	.L20:
+7421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Check parameters */
+7423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ 473              		.loc 1 7423 5 is_stmt 1 view .LVU176
+7424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+ 474              		.loc 1 7424 5 view .LVU177
+7425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output Compare IDLE State */
+7427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS4;
+ 475              		.loc 1 7427 5 view .LVU178
+ 476              	.LVL46:
+7428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output Compare N IDLE State */
+7429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS4N;
+ 477              		.loc 1 7429 5 view .LVU179
+ 478              		.loc 1 7429 12 is_stmt 0 view .LVU180
+ 479 006a 24F4404C 		bic	ip, r4, #49152
+ 480              	.LVL47:
+7430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output Idle state */
+7432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCIdleState << 6U);
+ 481              		.loc 1 7432 5 is_stmt 1 view .LVU181
+ 482              		.loc 1 7432 25 is_stmt 0 view .LVU182
+ 483 006e 4C69     		ldr	r4, [r1, #20]
+ 484              		.loc 1 7432 12 view .LVU183
+ 485 0070 4CEA841C 		orr	ip, ip, r4, lsl #6
+ 486              	.LVL48:
+7433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Idle state */
+7434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCNIdleState << 6U);
+ 487              		.loc 1 7434 5 is_stmt 1 view .LVU184
+ 488              		.loc 1 7434 25 is_stmt 0 view .LVU185
+ 489 0074 8C69     		ldr	r4, [r1, #24]
+ 490              		.loc 1 7434 12 view .LVU186
+ 491 0076 4CEA8414 		orr	r4, ip, r4, lsl #6
+ 492              	.LVL49:
+ 493              	.L21:
+7435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ARM GAS  /tmp/cc0wMqvE.s 			page 140
+
+
+7436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CR2 */
+7438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CR2 = tmpcr2;
+ 494              		.loc 1 7438 3 is_stmt 1 view .LVU187
+ 495              		.loc 1 7438 13 is_stmt 0 view .LVU188
+ 496 007a 4460     		str	r4, [r0, #4]
+7439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR2 */
+7441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCMR2 = tmpccmrx;
+ 497              		.loc 1 7441 3 is_stmt 1 view .LVU189
+ 498              		.loc 1 7441 15 is_stmt 0 view .LVU190
+ 499 007c C261     		str	r2, [r0, #28]
+7442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Capture Compare Register value */
+7444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCR4 = OC_Config->Pulse;
+ 500              		.loc 1 7444 3 is_stmt 1 view .LVU191
+ 501              		.loc 1 7444 25 is_stmt 0 view .LVU192
+ 502 007e 4A68     		ldr	r2, [r1, #4]
+ 503              	.LVL50:
+ 504              		.loc 1 7444 14 view .LVU193
+ 505 0080 0264     		str	r2, [r0, #64]
+ 506              	.LVL51:
+7445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCER */
+7447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 507              		.loc 1 7447 3 is_stmt 1 view .LVU194
+ 508              		.loc 1 7447 14 is_stmt 0 view .LVU195
+ 509 0082 0362     		str	r3, [r0, #32]
+7448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 510              		.loc 1 7448 1 view .LVU196
+ 511 0084 30BC     		pop	{r4, r5}
+ 512              	.LCFI5:
+ 513              		.cfi_restore 5
+ 514              		.cfi_restore 4
+ 515              		.cfi_def_cfa_offset 0
+ 516              	.LVL52:
+ 517              		.loc 1 7448 1 view .LVU197
+ 518 0086 7047     		bx	lr
+ 519              	.L24:
+ 520              		.align	2
+ 521              	.L23:
+ 522 0088 002C0140 		.word	1073818624
+ 523              		.cfi_endproc
+ 524              	.LFE437:
+ 526              		.section	.text.TIM_OC5_SetConfig,"ax",%progbits
+ 527              		.align	1
+ 528              		.syntax unified
+ 529              		.thumb
+ 530              		.thumb_func
+ 532              	TIM_OC5_SetConfig:
+ 533              	.LVL53:
+ 534              	.LFB438:
+7449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Timer Output Compare 5 configuration
+7452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  OC_Config The output configuration structure
+ARM GAS  /tmp/cc0wMqvE.s 			page 141
+
+
+7454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+7457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                               TIM_OC_InitTypeDef *OC_Config)
+7458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 535              		.loc 1 7458 1 is_stmt 1 view -0
+ 536              		.cfi_startproc
+ 537              		@ args = 0, pretend = 0, frame = 0
+ 538              		@ frame_needed = 0, uses_anonymous_args = 0
+ 539              		@ link register save eliminated.
+ 540              		.loc 1 7458 1 is_stmt 0 view .LVU199
+ 541 0000 30B4     		push	{r4, r5}
+ 542              	.LCFI6:
+ 543              		.cfi_def_cfa_offset 8
+ 544              		.cfi_offset 4, -8
+ 545              		.cfi_offset 5, -4
+7459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmrx;
+ 546              		.loc 1 7459 3 is_stmt 1 view .LVU200
+7460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ 547              		.loc 1 7460 3 view .LVU201
+7461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpcr2;
+ 548              		.loc 1 7461 3 view .LVU202
+7462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the output: Reset the CCxE Bit */
+7464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC5E;
+ 549              		.loc 1 7464 3 view .LVU203
+ 550              		.loc 1 7464 7 is_stmt 0 view .LVU204
+ 551 0002 036A     		ldr	r3, [r0, #32]
+ 552              		.loc 1 7464 14 view .LVU205
+ 553 0004 23F48033 		bic	r3, r3, #65536
+ 554 0008 0362     		str	r3, [r0, #32]
+7465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+7467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 555              		.loc 1 7467 3 is_stmt 1 view .LVU206
+ 556              		.loc 1 7467 11 is_stmt 0 view .LVU207
+ 557 000a 036A     		ldr	r3, [r0, #32]
+ 558              	.LVL54:
+7468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+7469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpcr2 =  TIMx->CR2;
+ 559              		.loc 1 7469 3 is_stmt 1 view .LVU208
+ 560              		.loc 1 7469 10 is_stmt 0 view .LVU209
+ 561 000c 4468     		ldr	r4, [r0, #4]
+ 562              	.LVL55:
+7470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCMR1 register value */
+7471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx = TIMx->CCMR3;
+ 563              		.loc 1 7471 3 is_stmt 1 view .LVU210
+ 564              		.loc 1 7471 12 is_stmt 0 view .LVU211
+ 565 000e 026D     		ldr	r2, [r0, #80]
+ 566              	.LVL56:
+7472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Output Compare Mode Bits */
+7474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx &= ~(TIM_CCMR3_OC5M);
+ 567              		.loc 1 7474 3 is_stmt 1 view .LVU212
+ 568              		.loc 1 7474 12 is_stmt 0 view .LVU213
+ 569 0010 22F48032 		bic	r2, r2, #65536
+ 570              	.LVL57:
+ARM GAS  /tmp/cc0wMqvE.s 			page 142
+
+
+ 571              		.loc 1 7474 12 view .LVU214
+ 572 0014 22F07002 		bic	r2, r2, #112
+ 573              	.LVL58:
+7475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Output Compare Mode */
+7476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx |= OC_Config->OCMode;
+ 574              		.loc 1 7476 3 is_stmt 1 view .LVU215
+ 575              		.loc 1 7476 24 is_stmt 0 view .LVU216
+ 576 0018 0D68     		ldr	r5, [r1]
+ 577              		.loc 1 7476 12 view .LVU217
+ 578 001a 1543     		orrs	r5, r5, r2
+ 579              	.LVL59:
+7477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Output Polarity level */
+7479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~TIM_CCER_CC5P;
+ 580              		.loc 1 7479 3 is_stmt 1 view .LVU218
+ 581              		.loc 1 7479 11 is_stmt 0 view .LVU219
+ 582 001c 23F40033 		bic	r3, r3, #131072
+ 583              	.LVL60:
+7480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+7481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= (OC_Config->OCPolarity << 16U);
+ 584              		.loc 1 7481 3 is_stmt 1 view .LVU220
+ 585              		.loc 1 7481 24 is_stmt 0 view .LVU221
+ 586 0020 8A68     		ldr	r2, [r1, #8]
+ 587              		.loc 1 7481 11 view .LVU222
+ 588 0022 43EA0243 		orr	r3, r3, r2, lsl #16
+ 589              	.LVL61:
+7482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 590              		.loc 1 7483 3 is_stmt 1 view .LVU223
+ 591              		.loc 1 7483 6 is_stmt 0 view .LVU224
+ 592 0026 0F4A     		ldr	r2, .L29
+ 593 0028 9042     		cmp	r0, r2
+ 594 002a 0FD0     		beq	.L26
+ 595              		.loc 1 7483 7 discriminator 1 view .LVU225
+ 596 002c 02F50062 		add	r2, r2, #2048
+ 597 0030 9042     		cmp	r0, r2
+ 598 0032 0BD0     		beq	.L26
+ 599              		.loc 1 7483 7 discriminator 2 view .LVU226
+ 600 0034 02F54062 		add	r2, r2, #3072
+ 601 0038 9042     		cmp	r0, r2
+ 602 003a 07D0     		beq	.L26
+ 603              		.loc 1 7483 7 discriminator 3 view .LVU227
+ 604 003c 02F58062 		add	r2, r2, #1024
+ 605 0040 9042     		cmp	r0, r2
+ 606 0042 03D0     		beq	.L26
+ 607              		.loc 1 7483 7 discriminator 4 view .LVU228
+ 608 0044 02F58062 		add	r2, r2, #1024
+ 609 0048 9042     		cmp	r0, r2
+ 610 004a 04D1     		bne	.L27
+ 611              	.L26:
+7484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output Compare IDLE State */
+7486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS5;
+ 612              		.loc 1 7486 5 is_stmt 1 view .LVU229
+ 613              		.loc 1 7486 12 is_stmt 0 view .LVU230
+ 614 004c 24F48034 		bic	r4, r4, #65536
+ 615              	.LVL62:
+ARM GAS  /tmp/cc0wMqvE.s 			page 143
+
+
+7487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output Idle state */
+7488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCIdleState << 8U);
+ 616              		.loc 1 7488 5 is_stmt 1 view .LVU231
+ 617              		.loc 1 7488 25 is_stmt 0 view .LVU232
+ 618 0050 4A69     		ldr	r2, [r1, #20]
+ 619              		.loc 1 7488 12 view .LVU233
+ 620 0052 44EA0224 		orr	r4, r4, r2, lsl #8
+ 621              	.LVL63:
+ 622              	.L27:
+7489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CR2 */
+7491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CR2 = tmpcr2;
+ 623              		.loc 1 7491 3 is_stmt 1 view .LVU234
+ 624              		.loc 1 7491 13 is_stmt 0 view .LVU235
+ 625 0056 4460     		str	r4, [r0, #4]
+7492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR3 */
+7494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCMR3 = tmpccmrx;
+ 626              		.loc 1 7494 3 is_stmt 1 view .LVU236
+ 627              		.loc 1 7494 15 is_stmt 0 view .LVU237
+ 628 0058 0565     		str	r5, [r0, #80]
+7495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Capture Compare Register value */
+7497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCR5 = OC_Config->Pulse;
+ 629              		.loc 1 7497 3 is_stmt 1 view .LVU238
+ 630              		.loc 1 7497 25 is_stmt 0 view .LVU239
+ 631 005a 4A68     		ldr	r2, [r1, #4]
+ 632              		.loc 1 7497 14 view .LVU240
+ 633 005c 8264     		str	r2, [r0, #72]
+7498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCER */
+7500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 634              		.loc 1 7500 3 is_stmt 1 view .LVU241
+ 635              		.loc 1 7500 14 is_stmt 0 view .LVU242
+ 636 005e 0362     		str	r3, [r0, #32]
+7501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 637              		.loc 1 7501 1 view .LVU243
+ 638 0060 30BC     		pop	{r4, r5}
+ 639              	.LCFI7:
+ 640              		.cfi_restore 5
+ 641              		.cfi_restore 4
+ 642              		.cfi_def_cfa_offset 0
+ 643              	.LVL64:
+ 644              		.loc 1 7501 1 view .LVU244
+ 645 0062 7047     		bx	lr
+ 646              	.L30:
+ 647              		.align	2
+ 648              	.L29:
+ 649 0064 002C0140 		.word	1073818624
+ 650              		.cfi_endproc
+ 651              	.LFE438:
+ 653              		.section	.text.TIM_OC6_SetConfig,"ax",%progbits
+ 654              		.align	1
+ 655              		.syntax unified
+ 656              		.thumb
+ 657              		.thumb_func
+ 659              	TIM_OC6_SetConfig:
+ARM GAS  /tmp/cc0wMqvE.s 			page 144
+
+
+ 660              	.LVL65:
+ 661              	.LFB439:
+7502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Timer Output Compare 6 configuration
+7505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  OC_Config The output configuration structure
+7507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+7510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                               TIM_OC_InitTypeDef *OC_Config)
+7511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 662              		.loc 1 7511 1 is_stmt 1 view -0
+ 663              		.cfi_startproc
+ 664              		@ args = 0, pretend = 0, frame = 0
+ 665              		@ frame_needed = 0, uses_anonymous_args = 0
+ 666              		@ link register save eliminated.
+ 667              		.loc 1 7511 1 is_stmt 0 view .LVU246
+ 668 0000 30B4     		push	{r4, r5}
+ 669              	.LCFI8:
+ 670              		.cfi_def_cfa_offset 8
+ 671              		.cfi_offset 4, -8
+ 672              		.cfi_offset 5, -4
+7512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmrx;
+ 673              		.loc 1 7512 3 is_stmt 1 view .LVU247
+7513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ 674              		.loc 1 7513 3 view .LVU248
+7514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpcr2;
+ 675              		.loc 1 7514 3 view .LVU249
+7515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the output: Reset the CCxE Bit */
+7517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC6E;
+ 676              		.loc 1 7517 3 view .LVU250
+ 677              		.loc 1 7517 7 is_stmt 0 view .LVU251
+ 678 0002 036A     		ldr	r3, [r0, #32]
+ 679              		.loc 1 7517 14 view .LVU252
+ 680 0004 23F48013 		bic	r3, r3, #1048576
+ 681 0008 0362     		str	r3, [r0, #32]
+7518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+7520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 682              		.loc 1 7520 3 is_stmt 1 view .LVU253
+ 683              		.loc 1 7520 11 is_stmt 0 view .LVU254
+ 684 000a 036A     		ldr	r3, [r0, #32]
+ 685              	.LVL66:
+7521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+7522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpcr2 =  TIMx->CR2;
+ 686              		.loc 1 7522 3 is_stmt 1 view .LVU255
+ 687              		.loc 1 7522 10 is_stmt 0 view .LVU256
+ 688 000c 4468     		ldr	r4, [r0, #4]
+ 689              	.LVL67:
+7523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CCMR1 register value */
+7524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx = TIMx->CCMR3;
+ 690              		.loc 1 7524 3 is_stmt 1 view .LVU257
+ 691              		.loc 1 7524 12 is_stmt 0 view .LVU258
+ 692 000e 026D     		ldr	r2, [r0, #80]
+ 693              	.LVL68:
+ARM GAS  /tmp/cc0wMqvE.s 			page 145
+
+
+7525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Output Compare Mode Bits */
+7527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx &= ~(TIM_CCMR3_OC6M);
+ 694              		.loc 1 7527 3 is_stmt 1 view .LVU259
+ 695              		.loc 1 7527 12 is_stmt 0 view .LVU260
+ 696 0010 22F08072 		bic	r2, r2, #16777216
+ 697              	.LVL69:
+ 698              		.loc 1 7527 12 view .LVU261
+ 699 0014 22F4E042 		bic	r2, r2, #28672
+ 700              	.LVL70:
+7528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Output Compare Mode */
+7529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx |= (OC_Config->OCMode << 8U);
+ 701              		.loc 1 7529 3 is_stmt 1 view .LVU262
+ 702              		.loc 1 7529 25 is_stmt 0 view .LVU263
+ 703 0018 0D68     		ldr	r5, [r1]
+ 704              		.loc 1 7529 12 view .LVU264
+ 705 001a 42EA0522 		orr	r2, r2, r5, lsl #8
+ 706              	.LVL71:
+7530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Output Polarity level */
+7532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+ 707              		.loc 1 7532 3 is_stmt 1 view .LVU265
+ 708              		.loc 1 7532 11 is_stmt 0 view .LVU266
+ 709 001e 23F40013 		bic	r3, r3, #2097152
+ 710              	.LVL72:
+7533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+7534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= (OC_Config->OCPolarity << 20U);
+ 711              		.loc 1 7534 3 is_stmt 1 view .LVU267
+ 712              		.loc 1 7534 24 is_stmt 0 view .LVU268
+ 713 0022 8D68     		ldr	r5, [r1, #8]
+ 714              		.loc 1 7534 11 view .LVU269
+ 715 0024 43EA0553 		orr	r3, r3, r5, lsl #20
+ 716              	.LVL73:
+7535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 717              		.loc 1 7536 3 is_stmt 1 view .LVU270
+ 718              		.loc 1 7536 6 is_stmt 0 view .LVU271
+ 719 0028 0F4D     		ldr	r5, .L35
+ 720 002a A842     		cmp	r0, r5
+ 721 002c 0FD0     		beq	.L32
+ 722              		.loc 1 7536 7 discriminator 1 view .LVU272
+ 723 002e 05F50065 		add	r5, r5, #2048
+ 724 0032 A842     		cmp	r0, r5
+ 725 0034 0BD0     		beq	.L32
+ 726              		.loc 1 7536 7 discriminator 2 view .LVU273
+ 727 0036 05F54065 		add	r5, r5, #3072
+ 728 003a A842     		cmp	r0, r5
+ 729 003c 07D0     		beq	.L32
+ 730              		.loc 1 7536 7 discriminator 3 view .LVU274
+ 731 003e 05F58065 		add	r5, r5, #1024
+ 732 0042 A842     		cmp	r0, r5
+ 733 0044 03D0     		beq	.L32
+ 734              		.loc 1 7536 7 discriminator 4 view .LVU275
+ 735 0046 05F58065 		add	r5, r5, #1024
+ 736 004a A842     		cmp	r0, r5
+ 737 004c 04D1     		bne	.L33
+ 738              	.L32:
+ARM GAS  /tmp/cc0wMqvE.s 			page 146
+
+
+7537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output Compare IDLE State */
+7539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS6;
+ 739              		.loc 1 7539 5 is_stmt 1 view .LVU276
+ 740              		.loc 1 7539 12 is_stmt 0 view .LVU277
+ 741 004e 24F48024 		bic	r4, r4, #262144
+ 742              	.LVL74:
+7540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output Idle state */
+7541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCIdleState << 10U);
+ 743              		.loc 1 7541 5 is_stmt 1 view .LVU278
+ 744              		.loc 1 7541 25 is_stmt 0 view .LVU279
+ 745 0052 4D69     		ldr	r5, [r1, #20]
+ 746              		.loc 1 7541 12 view .LVU280
+ 747 0054 44EA8524 		orr	r4, r4, r5, lsl #10
+ 748              	.LVL75:
+ 749              	.L33:
+7542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CR2 */
+7545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CR2 = tmpcr2;
+ 750              		.loc 1 7545 3 is_stmt 1 view .LVU281
+ 751              		.loc 1 7545 13 is_stmt 0 view .LVU282
+ 752 0058 4460     		str	r4, [r0, #4]
+7546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR3 */
+7548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCMR3 = tmpccmrx;
+ 753              		.loc 1 7548 3 is_stmt 1 view .LVU283
+ 754              		.loc 1 7548 15 is_stmt 0 view .LVU284
+ 755 005a 0265     		str	r2, [r0, #80]
+7549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Capture Compare Register value */
+7551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCR6 = OC_Config->Pulse;
+ 756              		.loc 1 7551 3 is_stmt 1 view .LVU285
+ 757              		.loc 1 7551 25 is_stmt 0 view .LVU286
+ 758 005c 4A68     		ldr	r2, [r1, #4]
+ 759              	.LVL76:
+ 760              		.loc 1 7551 14 view .LVU287
+ 761 005e C264     		str	r2, [r0, #76]
+ 762              	.LVL77:
+7552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCER */
+7554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 763              		.loc 1 7554 3 is_stmt 1 view .LVU288
+ 764              		.loc 1 7554 14 is_stmt 0 view .LVU289
+ 765 0060 0362     		str	r3, [r0, #32]
+7555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 766              		.loc 1 7555 1 view .LVU290
+ 767 0062 30BC     		pop	{r4, r5}
+ 768              	.LCFI9:
+ 769              		.cfi_restore 5
+ 770              		.cfi_restore 4
+ 771              		.cfi_def_cfa_offset 0
+ 772              	.LVL78:
+ 773              		.loc 1 7555 1 view .LVU291
+ 774 0064 7047     		bx	lr
+ 775              	.L36:
+ 776 0066 00BF     		.align	2
+ARM GAS  /tmp/cc0wMqvE.s 			page 147
+
+
+ 777              	.L35:
+ 778 0068 002C0140 		.word	1073818624
+ 779              		.cfi_endproc
+ 780              	.LFE439:
+ 782              		.section	.text.TIM_TI1_ConfigInputStage,"ax",%progbits
+ 783              		.align	1
+ 784              		.syntax unified
+ 785              		.thumb
+ 786              		.thumb_func
+ 788              	TIM_TI1_ConfigInputStage:
+ 789              	.LVL79:
+ 790              	.LFB442:
+7556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Slave Timer configuration function
+7559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  htim TIM handle
+7560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  sSlaveConfig Slave timer configuration
+7561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+7564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                                   TIM_SlaveConfigTypeDef *sSlaveConfig)
+7565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+7566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+7567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+7568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmr1;
+7569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+7570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx SMCR register value */
+7572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr = htim->Instance->SMCR;
+7573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the Trigger Selection Bits */
+7575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr &= ~TIM_SMCR_TS;
+7576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Input Trigger source */
+7577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr |= sSlaveConfig->InputTrigger;
+7578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the slave mode Bits */
+7580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr &= ~TIM_SMCR_SMS;
+7581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the slave mode */
+7582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr |= sSlaveConfig->SlaveMode;
+7583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx SMCR */
+7585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Instance->SMCR = tmpsmcr;
+7586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Configure the trigger prescaler, filter, and polarity */
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (sSlaveConfig->InputTrigger)
+7589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ETRF:
+7591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+7592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+7593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+7594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+7595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+7596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+7597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the ETR Trigger source */
+7598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_ETR_SetConfig(htim->Instance,
+7599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sSlaveConfig->TriggerPrescaler,
+7600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sSlaveConfig->TriggerPolarity,
+ARM GAS  /tmp/cc0wMqvE.s 			page 148
+
+
+7601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sSlaveConfig->TriggerFilter);
+7602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+7603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+7604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_TI1F_ED:
+7606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+7607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+7608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+7609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+7610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \
+7612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
+7613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+7614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+7615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+7616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Disable the Channel 1: Reset the CC1E Bit */
+7618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpccer = htim->Instance->CCER;
+7619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCER &= ~TIM_CCER_CC1E;
+7620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpccmr1 = htim->Instance->CCMR1;
+7621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Set the filter */
+7623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpccmr1 &= ~TIM_CCMR1_IC1F;
+7624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+7625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Write to TIMx CCMR1 and CCER registers */
+7627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 = tmpccmr1;
+7628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCER = tmpccer;
+7629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+7630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+7631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_TI1FP1:
+7633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+7634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+7635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+7636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+7637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+7638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure TI1 Filter and Polarity */
+7640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_TI1_ConfigInputStage(htim->Instance,
+7641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+7642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sSlaveConfig->TriggerFilter);
+7643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+7644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+7645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_TI2FP2:
+7647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+7648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameters */
+7649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+7650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+7651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+7652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure TI2 Filter and Polarity */
+7654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_TI2_ConfigInputStage(htim->Instance,
+7655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+7656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sSlaveConfig->TriggerFilter);
+7657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ARM GAS  /tmp/cc0wMqvE.s 			page 149
+
+
+7658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+7659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ITR0:
+7661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ITR1:
+7662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ITR2:
+7663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ITR3:
+7664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if defined (TIM5)
+7665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ITR4:
+7666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* TIM5 */
+7667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ITR5:
+7668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ITR6:
+7669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ITR7:
+7670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ITR8:
+7671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if defined (TIM20)
+7672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ITR9:
+7673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* TIM20 */
+7674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if defined (HRTIM1)
+7675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ITR10:
+7676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* HRTIM1 */
+7677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     case TIM_TS_ITR11:
+7678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+7679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Check the parameter */
+7680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigg
+7681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+7682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+7683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     default:
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       status = HAL_ERROR;
+7686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+7687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return status;
+7690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+7691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configure the TI1 as Input.
+7694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral.
+7695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICPolarity The Input Polarity.
+7696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_RISING
+7698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_FALLING
+7699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_BOTHEDGE
+7700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICSelection specifies the input to be used.
+7701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+7703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+7704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+7705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICFilter Specifies the Input Capture Filter.
+7706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F.
+7707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+7709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+7710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        protected against un-initialized filter and polarity values.
+7711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+7713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                        uint32_t TIM_ICFilter)
+7714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ARM GAS  /tmp/cc0wMqvE.s 			page 150
+
+
+7715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmr1;
+7716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+7717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Channel 1: Reset the CC1E Bit */
+7719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC1E;
+7720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+7721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+7722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Input */
+7724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+7725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccmr1 &= ~TIM_CCMR1_CC1S;
+7727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccmr1 |= TIM_ICSelection;
+7728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   else
+7730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+7731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccmr1 |= TIM_CCMR1_CC1S_0;
+7732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+7733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the filter */
+7735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 &= ~TIM_CCMR1_IC1F;
+7736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+7737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Polarity and set the CC1E Bit */
+7739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+7740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+7741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR1 and CCER registers */
+7743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCMR1 = tmpccmr1;
+7744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+7745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+7746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configure the Polarity and Filter for TI1.
+7749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral.
+7750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICPolarity The Input Polarity.
+7751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_RISING
+7753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_FALLING
+7754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_BOTHEDGE
+7755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICFilter Specifies the Input Capture Filter.
+7756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F.
+7757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil
+7760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 791              		.loc 1 7760 1 is_stmt 1 view -0
+ 792              		.cfi_startproc
+ 793              		@ args = 0, pretend = 0, frame = 0
+ 794              		@ frame_needed = 0, uses_anonymous_args = 0
+ 795              		@ link register save eliminated.
+ 796              		.loc 1 7760 1 is_stmt 0 view .LVU293
+ 797 0000 10B4     		push	{r4}
+ 798              	.LCFI10:
+ 799              		.cfi_def_cfa_offset 4
+ 800              		.cfi_offset 4, -4
+7761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmr1;
+ARM GAS  /tmp/cc0wMqvE.s 			page 151
+
+
+ 801              		.loc 1 7761 3 is_stmt 1 view .LVU294
+7762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ 802              		.loc 1 7762 3 view .LVU295
+7763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Channel 1: Reset the CC1E Bit */
+7765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 803              		.loc 1 7765 3 view .LVU296
+ 804              		.loc 1 7765 11 is_stmt 0 view .LVU297
+ 805 0002 036A     		ldr	r3, [r0, #32]
+ 806              	.LVL80:
+7766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC1E;
+ 807              		.loc 1 7766 3 is_stmt 1 view .LVU298
+ 808              		.loc 1 7766 7 is_stmt 0 view .LVU299
+ 809 0004 046A     		ldr	r4, [r0, #32]
+ 810              		.loc 1 7766 14 view .LVU300
+ 811 0006 24F00104 		bic	r4, r4, #1
+ 812 000a 0462     		str	r4, [r0, #32]
+7767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+ 813              		.loc 1 7767 3 is_stmt 1 view .LVU301
+ 814              		.loc 1 7767 12 is_stmt 0 view .LVU302
+ 815 000c 8469     		ldr	r4, [r0, #24]
+ 816              	.LVL81:
+7768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the filter */
+7770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ 817              		.loc 1 7770 3 is_stmt 1 view .LVU303
+ 818              		.loc 1 7770 12 is_stmt 0 view .LVU304
+ 819 000e 24F0F00C 		bic	ip, r4, #240
+ 820              	.LVL82:
+7771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= (TIM_ICFilter << 4U);
+ 821              		.loc 1 7771 3 is_stmt 1 view .LVU305
+ 822              		.loc 1 7771 12 is_stmt 0 view .LVU306
+ 823 0012 4CEA0212 		orr	r2, ip, r2, lsl #4
+ 824              	.LVL83:
+7772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Polarity and set the CC1E Bit */
+7774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ 825              		.loc 1 7774 3 is_stmt 1 view .LVU307
+ 826              		.loc 1 7774 11 is_stmt 0 view .LVU308
+ 827 0016 23F00A03 		bic	r3, r3, #10
+ 828              	.LVL84:
+7775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= TIM_ICPolarity;
+ 829              		.loc 1 7775 3 is_stmt 1 view .LVU309
+ 830              		.loc 1 7775 11 is_stmt 0 view .LVU310
+ 831 001a 0B43     		orrs	r3, r3, r1
+ 832              	.LVL85:
+7776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR1 and CCER registers */
+7778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCMR1 = tmpccmr1;
+ 833              		.loc 1 7778 3 is_stmt 1 view .LVU311
+ 834              		.loc 1 7778 15 is_stmt 0 view .LVU312
+ 835 001c 8261     		str	r2, [r0, #24]
+7779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 836              		.loc 1 7779 3 is_stmt 1 view .LVU313
+ 837              		.loc 1 7779 14 is_stmt 0 view .LVU314
+ 838 001e 0362     		str	r3, [r0, #32]
+7780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ARM GAS  /tmp/cc0wMqvE.s 			page 152
+
+
+ 839              		.loc 1 7780 1 view .LVU315
+ 840 0020 5DF8044B 		ldr	r4, [sp], #4
+ 841              	.LCFI11:
+ 842              		.cfi_restore 4
+ 843              		.cfi_def_cfa_offset 0
+ 844 0024 7047     		bx	lr
+ 845              		.cfi_endproc
+ 846              	.LFE442:
+ 848              		.section	.text.TIM_TI2_SetConfig,"ax",%progbits
+ 849              		.align	1
+ 850              		.syntax unified
+ 851              		.thumb
+ 852              		.thumb_func
+ 854              	TIM_TI2_SetConfig:
+ 855              	.LVL86:
+ 856              	.LFB443:
+7781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configure the TI2 as Input.
+7784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICPolarity The Input Polarity.
+7786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_RISING
+7788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_FALLING
+7789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_BOTHEDGE
+7790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICSelection specifies the input to be used.
+7791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+7793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+7794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+7795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICFilter Specifies the Input Capture Filter.
+7796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F.
+7797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+7799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+7800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        protected against un-initialized filter and polarity values.
+7801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+7803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                               uint32_t TIM_ICFilter)
+7804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 857              		.loc 1 7804 1 is_stmt 1 view -0
+ 858              		.cfi_startproc
+ 859              		@ args = 0, pretend = 0, frame = 0
+ 860              		@ frame_needed = 0, uses_anonymous_args = 0
+ 861              		@ link register save eliminated.
+ 862              		.loc 1 7804 1 is_stmt 0 view .LVU317
+ 863 0000 30B4     		push	{r4, r5}
+ 864              	.LCFI12:
+ 865              		.cfi_def_cfa_offset 8
+ 866              		.cfi_offset 4, -8
+ 867              		.cfi_offset 5, -4
+7805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 868              		.loc 1 7805 3 is_stmt 1 view .LVU318
+7806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ 869              		.loc 1 7806 3 view .LVU319
+7807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Channel 2: Reset the CC2E Bit */
+ARM GAS  /tmp/cc0wMqvE.s 			page 153
+
+
+7809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC2E;
+ 870              		.loc 1 7809 3 view .LVU320
+ 871              		.loc 1 7809 7 is_stmt 0 view .LVU321
+ 872 0002 046A     		ldr	r4, [r0, #32]
+ 873              		.loc 1 7809 14 view .LVU322
+ 874 0004 24F01004 		bic	r4, r4, #16
+ 875 0008 0462     		str	r4, [r0, #32]
+7810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+ 876              		.loc 1 7810 3 is_stmt 1 view .LVU323
+ 877              		.loc 1 7810 12 is_stmt 0 view .LVU324
+ 878 000a 8469     		ldr	r4, [r0, #24]
+ 879              	.LVL87:
+7811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 880              		.loc 1 7811 3 is_stmt 1 view .LVU325
+ 881              		.loc 1 7811 11 is_stmt 0 view .LVU326
+ 882 000c 056A     		ldr	r5, [r0, #32]
+ 883              	.LVL88:
+7812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Input */
+7814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 &= ~TIM_CCMR1_CC2S;
+ 884              		.loc 1 7814 3 is_stmt 1 view .LVU327
+ 885              		.loc 1 7814 12 is_stmt 0 view .LVU328
+ 886 000e 24F4407C 		bic	ip, r4, #768
+ 887              	.LVL89:
+7815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= (TIM_ICSelection << 8U);
+ 888              		.loc 1 7815 3 is_stmt 1 view .LVU329
+ 889              		.loc 1 7815 12 is_stmt 0 view .LVU330
+ 890 0012 4CEA022C 		orr	ip, ip, r2, lsl #8
+ 891              	.LVL90:
+7816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the filter */
+7818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ 892              		.loc 1 7818 3 is_stmt 1 view .LVU331
+ 893              		.loc 1 7818 12 is_stmt 0 view .LVU332
+ 894 0016 2CF4704C 		bic	ip, ip, #61440
+ 895              	.LVL91:
+7819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+ 896              		.loc 1 7819 3 is_stmt 1 view .LVU333
+ 897              		.loc 1 7819 30 is_stmt 0 view .LVU334
+ 898 001a 1B03     		lsls	r3, r3, #12
+ 899              	.LVL92:
+ 900              		.loc 1 7819 38 view .LVU335
+ 901 001c 9BB2     		uxth	r3, r3
+ 902              		.loc 1 7819 12 view .LVU336
+ 903 001e 43EA0C03 		orr	r3, r3, ip
+ 904              	.LVL93:
+7820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Polarity and set the CC2E Bit */
+7822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ 905              		.loc 1 7822 3 is_stmt 1 view .LVU337
+ 906              		.loc 1 7822 11 is_stmt 0 view .LVU338
+ 907 0022 25F0A005 		bic	r5, r5, #160
+ 908              	.LVL94:
+7823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+ 909              		.loc 1 7823 3 is_stmt 1 view .LVU339
+ 910              		.loc 1 7823 31 is_stmt 0 view .LVU340
+ 911 0026 0901     		lsls	r1, r1, #4
+ARM GAS  /tmp/cc0wMqvE.s 			page 154
+
+
+ 912              	.LVL95:
+ 913              		.loc 1 7823 38 view .LVU341
+ 914 0028 01F0A001 		and	r1, r1, #160
+ 915              		.loc 1 7823 11 view .LVU342
+ 916 002c 2943     		orrs	r1, r1, r5
+ 917              	.LVL96:
+7824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR1 and CCER registers */
+7826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCMR1 = tmpccmr1 ;
+ 918              		.loc 1 7826 3 is_stmt 1 view .LVU343
+ 919              		.loc 1 7826 15 is_stmt 0 view .LVU344
+ 920 002e 8361     		str	r3, [r0, #24]
+7827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 921              		.loc 1 7827 3 is_stmt 1 view .LVU345
+ 922              		.loc 1 7827 14 is_stmt 0 view .LVU346
+ 923 0030 0162     		str	r1, [r0, #32]
+7828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 924              		.loc 1 7828 1 view .LVU347
+ 925 0032 30BC     		pop	{r4, r5}
+ 926              	.LCFI13:
+ 927              		.cfi_restore 5
+ 928              		.cfi_restore 4
+ 929              		.cfi_def_cfa_offset 0
+ 930 0034 7047     		bx	lr
+ 931              		.cfi_endproc
+ 932              	.LFE443:
+ 934              		.section	.text.TIM_TI2_ConfigInputStage,"ax",%progbits
+ 935              		.align	1
+ 936              		.syntax unified
+ 937              		.thumb
+ 938              		.thumb_func
+ 940              	TIM_TI2_ConfigInputStage:
+ 941              	.LVL97:
+ 942              	.LFB444:
+7829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configure the Polarity and Filter for TI2.
+7832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral.
+7833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICPolarity The Input Polarity.
+7834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_RISING
+7836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_FALLING
+7837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_BOTHEDGE
+7838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICFilter Specifies the Input Capture Filter.
+7839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F.
+7840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil
+7843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 943              		.loc 1 7843 1 is_stmt 1 view -0
+ 944              		.cfi_startproc
+ 945              		@ args = 0, pretend = 0, frame = 0
+ 946              		@ frame_needed = 0, uses_anonymous_args = 0
+ 947              		@ link register save eliminated.
+ 948              		.loc 1 7843 1 is_stmt 0 view .LVU349
+ 949 0000 10B4     		push	{r4}
+ 950              	.LCFI14:
+ARM GAS  /tmp/cc0wMqvE.s 			page 155
+
+
+ 951              		.cfi_def_cfa_offset 4
+ 952              		.cfi_offset 4, -4
+7844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 953              		.loc 1 7844 3 is_stmt 1 view .LVU350
+7845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ 954              		.loc 1 7845 3 view .LVU351
+7846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Channel 2: Reset the CC2E Bit */
+7848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC2E;
+ 955              		.loc 1 7848 3 view .LVU352
+ 956              		.loc 1 7848 7 is_stmt 0 view .LVU353
+ 957 0002 036A     		ldr	r3, [r0, #32]
+ 958              		.loc 1 7848 14 view .LVU354
+ 959 0004 23F01003 		bic	r3, r3, #16
+ 960 0008 0362     		str	r3, [r0, #32]
+7849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+ 961              		.loc 1 7849 3 is_stmt 1 view .LVU355
+ 962              		.loc 1 7849 12 is_stmt 0 view .LVU356
+ 963 000a 8469     		ldr	r4, [r0, #24]
+ 964              	.LVL98:
+7850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 965              		.loc 1 7850 3 is_stmt 1 view .LVU357
+ 966              		.loc 1 7850 11 is_stmt 0 view .LVU358
+ 967 000c 036A     		ldr	r3, [r0, #32]
+ 968              	.LVL99:
+7851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the filter */
+7853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ 969              		.loc 1 7853 3 is_stmt 1 view .LVU359
+ 970              		.loc 1 7853 12 is_stmt 0 view .LVU360
+ 971 000e 24F4704C 		bic	ip, r4, #61440
+ 972              	.LVL100:
+7854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= (TIM_ICFilter << 12U);
+ 973              		.loc 1 7854 3 is_stmt 1 view .LVU361
+ 974              		.loc 1 7854 12 is_stmt 0 view .LVU362
+ 975 0012 4CEA0232 		orr	r2, ip, r2, lsl #12
+ 976              	.LVL101:
+7855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Polarity and set the CC2E Bit */
+7857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ 977              		.loc 1 7857 3 is_stmt 1 view .LVU363
+ 978              		.loc 1 7857 11 is_stmt 0 view .LVU364
+ 979 0016 23F0A003 		bic	r3, r3, #160
+ 980              	.LVL102:
+7858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= (TIM_ICPolarity << 4U);
+ 981              		.loc 1 7858 3 is_stmt 1 view .LVU365
+ 982              		.loc 1 7858 11 is_stmt 0 view .LVU366
+ 983 001a 43EA0113 		orr	r3, r3, r1, lsl #4
+ 984              	.LVL103:
+7859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR1 and CCER registers */
+7861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCMR1 = tmpccmr1 ;
+ 985              		.loc 1 7861 3 is_stmt 1 view .LVU367
+ 986              		.loc 1 7861 15 is_stmt 0 view .LVU368
+ 987 001e 8261     		str	r2, [r0, #24]
+7862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 988              		.loc 1 7862 3 is_stmt 1 view .LVU369
+ARM GAS  /tmp/cc0wMqvE.s 			page 156
+
+
+ 989              		.loc 1 7862 14 is_stmt 0 view .LVU370
+ 990 0020 0362     		str	r3, [r0, #32]
+7863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 991              		.loc 1 7863 1 view .LVU371
+ 992 0022 5DF8044B 		ldr	r4, [sp], #4
+ 993              	.LCFI15:
+ 994              		.cfi_restore 4
+ 995              		.cfi_def_cfa_offset 0
+ 996 0026 7047     		bx	lr
+ 997              		.cfi_endproc
+ 998              	.LFE444:
+ 1000              		.section	.text.TIM_TI3_SetConfig,"ax",%progbits
+ 1001              		.align	1
+ 1002              		.syntax unified
+ 1003              		.thumb
+ 1004              		.thumb_func
+ 1006              	TIM_TI3_SetConfig:
+ 1007              	.LVL104:
+ 1008              	.LFB445:
+7864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configure the TI3 as Input.
+7867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICPolarity The Input Polarity.
+7869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_RISING
+7871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_FALLING
+7872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_BOTHEDGE
+7873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICSelection specifies the input to be used.
+7874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+7876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+7877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+7878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICFilter Specifies the Input Capture Filter.
+7879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F.
+7880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+7882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+7883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        protected against un-initialized filter and polarity values.
+7884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+7886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                               uint32_t TIM_ICFilter)
+7887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 1009              		.loc 1 7887 1 is_stmt 1 view -0
+ 1010              		.cfi_startproc
+ 1011              		@ args = 0, pretend = 0, frame = 0
+ 1012              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1013              		@ link register save eliminated.
+ 1014              		.loc 1 7887 1 is_stmt 0 view .LVU373
+ 1015 0000 30B4     		push	{r4, r5}
+ 1016              	.LCFI16:
+ 1017              		.cfi_def_cfa_offset 8
+ 1018              		.cfi_offset 4, -8
+ 1019              		.cfi_offset 5, -4
+7888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmr2;
+ 1020              		.loc 1 7888 3 is_stmt 1 view .LVU374
+7889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ARM GAS  /tmp/cc0wMqvE.s 			page 157
+
+
+ 1021              		.loc 1 7889 3 view .LVU375
+7890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Channel 3: Reset the CC3E Bit */
+7892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC3E;
+ 1022              		.loc 1 7892 3 view .LVU376
+ 1023              		.loc 1 7892 7 is_stmt 0 view .LVU377
+ 1024 0002 046A     		ldr	r4, [r0, #32]
+ 1025              		.loc 1 7892 14 view .LVU378
+ 1026 0004 24F48074 		bic	r4, r4, #256
+ 1027 0008 0462     		str	r4, [r0, #32]
+7893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr2 = TIMx->CCMR2;
+ 1028              		.loc 1 7893 3 is_stmt 1 view .LVU379
+ 1029              		.loc 1 7893 12 is_stmt 0 view .LVU380
+ 1030 000a C469     		ldr	r4, [r0, #28]
+ 1031              	.LVL105:
+7894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 1032              		.loc 1 7894 3 is_stmt 1 view .LVU381
+ 1033              		.loc 1 7894 11 is_stmt 0 view .LVU382
+ 1034 000c 056A     		ldr	r5, [r0, #32]
+ 1035              	.LVL106:
+7895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Input */
+7897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr2 &= ~TIM_CCMR2_CC3S;
+ 1036              		.loc 1 7897 3 is_stmt 1 view .LVU383
+ 1037              		.loc 1 7897 12 is_stmt 0 view .LVU384
+ 1038 000e 24F0030C 		bic	ip, r4, #3
+ 1039              	.LVL107:
+7898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr2 |= TIM_ICSelection;
+ 1040              		.loc 1 7898 3 is_stmt 1 view .LVU385
+ 1041              		.loc 1 7898 12 is_stmt 0 view .LVU386
+ 1042 0012 4CEA020C 		orr	ip, ip, r2
+ 1043              	.LVL108:
+7899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the filter */
+7901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr2 &= ~TIM_CCMR2_IC3F;
+ 1044              		.loc 1 7901 3 is_stmt 1 view .LVU387
+ 1045              		.loc 1 7901 12 is_stmt 0 view .LVU388
+ 1046 0016 2CF0F00C 		bic	ip, ip, #240
+ 1047              	.LVL109:
+7902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+ 1048              		.loc 1 7902 3 is_stmt 1 view .LVU389
+ 1049              		.loc 1 7902 30 is_stmt 0 view .LVU390
+ 1050 001a 1B01     		lsls	r3, r3, #4
+ 1051              	.LVL110:
+ 1052              		.loc 1 7902 37 view .LVU391
+ 1053 001c DBB2     		uxtb	r3, r3
+ 1054              		.loc 1 7902 12 view .LVU392
+ 1055 001e 43EA0C03 		orr	r3, r3, ip
+ 1056              	.LVL111:
+7903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Polarity and set the CC3E Bit */
+7905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+ 1057              		.loc 1 7905 3 is_stmt 1 view .LVU393
+ 1058              		.loc 1 7905 11 is_stmt 0 view .LVU394
+ 1059 0022 25F42065 		bic	r5, r5, #2560
+ 1060              	.LVL112:
+7906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+ARM GAS  /tmp/cc0wMqvE.s 			page 158
+
+
+ 1061              		.loc 1 7906 3 is_stmt 1 view .LVU395
+ 1062              		.loc 1 7906 31 is_stmt 0 view .LVU396
+ 1063 0026 0902     		lsls	r1, r1, #8
+ 1064              	.LVL113:
+ 1065              		.loc 1 7906 38 view .LVU397
+ 1066 0028 01F42061 		and	r1, r1, #2560
+ 1067              		.loc 1 7906 11 view .LVU398
+ 1068 002c 2943     		orrs	r1, r1, r5
+ 1069              	.LVL114:
+7907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR2 and CCER registers */
+7909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCMR2 = tmpccmr2;
+ 1070              		.loc 1 7909 3 is_stmt 1 view .LVU399
+ 1071              		.loc 1 7909 15 is_stmt 0 view .LVU400
+ 1072 002e C361     		str	r3, [r0, #28]
+7910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 1073              		.loc 1 7910 3 is_stmt 1 view .LVU401
+ 1074              		.loc 1 7910 14 is_stmt 0 view .LVU402
+ 1075 0030 0162     		str	r1, [r0, #32]
+7911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1076              		.loc 1 7911 1 view .LVU403
+ 1077 0032 30BC     		pop	{r4, r5}
+ 1078              	.LCFI17:
+ 1079              		.cfi_restore 5
+ 1080              		.cfi_restore 4
+ 1081              		.cfi_def_cfa_offset 0
+ 1082 0034 7047     		bx	lr
+ 1083              		.cfi_endproc
+ 1084              	.LFE445:
+ 1086              		.section	.text.TIM_TI4_SetConfig,"ax",%progbits
+ 1087              		.align	1
+ 1088              		.syntax unified
+ 1089              		.thumb
+ 1090              		.thumb_func
+ 1092              	TIM_TI4_SetConfig:
+ 1093              	.LVL115:
+ 1094              	.LFB446:
+7912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+7914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configure the TI4 as Input.
+7915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICPolarity The Input Polarity.
+7917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_RISING
+7919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_FALLING
+7920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_BOTHEDGE
+7921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICSelection specifies the input to be used.
+7922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+7924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+7925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+7926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ICFilter Specifies the Input Capture Filter.
+7927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F.
+7928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+7929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+7930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *        protected against un-initialized filter and polarity values.
+7931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+ARM GAS  /tmp/cc0wMqvE.s 			page 159
+
+
+7932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+7934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                               uint32_t TIM_ICFilter)
+7935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 1095              		.loc 1 7935 1 is_stmt 1 view -0
+ 1096              		.cfi_startproc
+ 1097              		@ args = 0, pretend = 0, frame = 0
+ 1098              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1099              		@ link register save eliminated.
+ 1100              		.loc 1 7935 1 is_stmt 0 view .LVU405
+ 1101 0000 30B4     		push	{r4, r5}
+ 1102              	.LCFI18:
+ 1103              		.cfi_def_cfa_offset 8
+ 1104              		.cfi_offset 4, -8
+ 1105              		.cfi_offset 5, -4
+7936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmr2;
+ 1106              		.loc 1 7936 3 is_stmt 1 view .LVU406
+7937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ 1107              		.loc 1 7937 3 view .LVU407
+7938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Disable the Channel 4: Reset the CC4E Bit */
+7940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC4E;
+ 1108              		.loc 1 7940 3 view .LVU408
+ 1109              		.loc 1 7940 7 is_stmt 0 view .LVU409
+ 1110 0002 046A     		ldr	r4, [r0, #32]
+ 1111              		.loc 1 7940 14 view .LVU410
+ 1112 0004 24F48054 		bic	r4, r4, #4096
+ 1113 0008 0462     		str	r4, [r0, #32]
+7941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr2 = TIMx->CCMR2;
+ 1114              		.loc 1 7941 3 is_stmt 1 view .LVU411
+ 1115              		.loc 1 7941 12 is_stmt 0 view .LVU412
+ 1116 000a C469     		ldr	r4, [r0, #28]
+ 1117              	.LVL116:
+7942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 1118              		.loc 1 7942 3 is_stmt 1 view .LVU413
+ 1119              		.loc 1 7942 11 is_stmt 0 view .LVU414
+ 1120 000c 056A     		ldr	r5, [r0, #32]
+ 1121              	.LVL117:
+7943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Input */
+7945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr2 &= ~TIM_CCMR2_CC4S;
+ 1122              		.loc 1 7945 3 is_stmt 1 view .LVU415
+ 1123              		.loc 1 7945 12 is_stmt 0 view .LVU416
+ 1124 000e 24F4407C 		bic	ip, r4, #768
+ 1125              	.LVL118:
+7946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr2 |= (TIM_ICSelection << 8U);
+ 1126              		.loc 1 7946 3 is_stmt 1 view .LVU417
+ 1127              		.loc 1 7946 12 is_stmt 0 view .LVU418
+ 1128 0012 4CEA022C 		orr	ip, ip, r2, lsl #8
+ 1129              	.LVL119:
+7947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the filter */
+7949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr2 &= ~TIM_CCMR2_IC4F;
+ 1130              		.loc 1 7949 3 is_stmt 1 view .LVU419
+ 1131              		.loc 1 7949 12 is_stmt 0 view .LVU420
+ 1132 0016 2CF4704C 		bic	ip, ip, #61440
+ 1133              	.LVL120:
+ARM GAS  /tmp/cc0wMqvE.s 			page 160
+
+
+7950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+ 1134              		.loc 1 7950 3 is_stmt 1 view .LVU421
+ 1135              		.loc 1 7950 30 is_stmt 0 view .LVU422
+ 1136 001a 1B03     		lsls	r3, r3, #12
+ 1137              	.LVL121:
+ 1138              		.loc 1 7950 38 view .LVU423
+ 1139 001c 9BB2     		uxth	r3, r3
+ 1140              		.loc 1 7950 12 view .LVU424
+ 1141 001e 43EA0C03 		orr	r3, r3, ip
+ 1142              	.LVL122:
+7951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Select the Polarity and set the CC4E Bit */
+7953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+ 1143              		.loc 1 7953 3 is_stmt 1 view .LVU425
+ 1144              		.loc 1 7953 11 is_stmt 0 view .LVU426
+ 1145 0022 25F42045 		bic	r5, r5, #40960
+ 1146              	.LVL123:
+7954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+ 1147              		.loc 1 7954 3 is_stmt 1 view .LVU427
+ 1148              		.loc 1 7954 31 is_stmt 0 view .LVU428
+ 1149 0026 0903     		lsls	r1, r1, #12
+ 1150              	.LVL124:
+ 1151              		.loc 1 7954 39 view .LVU429
+ 1152 0028 01F42041 		and	r1, r1, #40960
+ 1153              		.loc 1 7954 11 view .LVU430
+ 1154 002c 2943     		orrs	r1, r1, r5
+ 1155              	.LVL125:
+7955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx CCMR2 and CCER registers */
+7957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCMR2 = tmpccmr2;
+ 1156              		.loc 1 7957 3 is_stmt 1 view .LVU431
+ 1157              		.loc 1 7957 15 is_stmt 0 view .LVU432
+ 1158 002e C361     		str	r3, [r0, #28]
+7958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer ;
+ 1159              		.loc 1 7958 3 is_stmt 1 view .LVU433
+ 1160              		.loc 1 7958 14 is_stmt 0 view .LVU434
+ 1161 0030 0162     		str	r1, [r0, #32]
+7959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1162              		.loc 1 7959 1 view .LVU435
+ 1163 0032 30BC     		pop	{r4, r5}
+ 1164              	.LCFI19:
+ 1165              		.cfi_restore 5
+ 1166              		.cfi_restore 4
+ 1167              		.cfi_def_cfa_offset 0
+ 1168 0034 7047     		bx	lr
+ 1169              		.cfi_endproc
+ 1170              	.LFE446:
+ 1172              		.section	.text.TIM_ITRx_SetConfig,"ax",%progbits
+ 1173              		.align	1
+ 1174              		.syntax unified
+ 1175              		.thumb
+ 1176              		.thumb_func
+ 1178              	TIM_ITRx_SetConfig:
+ 1179              	.LVL126:
+ 1180              	.LFB447:
+7960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ARM GAS  /tmp/cc0wMqvE.s 			page 161
+
+
+7962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Selects the Input Trigger source
+7963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  InputTriggerSource The Input Trigger source.
+7965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ITR0: Internal Trigger 0
+7967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ITR1: Internal Trigger 1
+7968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ITR2: Internal Trigger 2
+7969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ITR3: Internal Trigger 3
+7970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+7971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+7972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+7973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ETRF: External Trigger input
+7974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ITR4: Internal Trigger 4  (*)
+7975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ITR5: Internal Trigger 5
+7976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ITR6: Internal Trigger 6
+7977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ITR7: Internal Trigger 7
+7978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ITR8: Internal Trigger 8
+7979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ITR9: Internal Trigger 9   (*)
+7980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ITR10: Internal Trigger 10
+7981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_TS_ITR11: Internal Trigger 11
+7982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+7983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *       (*)  Value not defined in all devices.
+7984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *
+7985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+7986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+7987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+7988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 1181              		.loc 1 7988 1 is_stmt 1 view -0
+ 1182              		.cfi_startproc
+ 1183              		@ args = 0, pretend = 0, frame = 0
+ 1184              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1185              		@ link register save eliminated.
+7989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 1186              		.loc 1 7989 3 view .LVU437
+7990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+7991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx SMCR register value */
+7992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr = TIMx->SMCR;
+ 1187              		.loc 1 7992 3 view .LVU438
+ 1188              		.loc 1 7992 11 is_stmt 0 view .LVU439
+ 1189 0000 8368     		ldr	r3, [r0, #8]
+ 1190              	.LVL127:
+7993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the TS Bits */
+7994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr &= ~TIM_SMCR_TS;
+ 1191              		.loc 1 7994 3 is_stmt 1 view .LVU440
+ 1192              		.loc 1 7994 11 is_stmt 0 view .LVU441
+ 1193 0002 23F44013 		bic	r3, r3, #3145728
+ 1194              	.LVL128:
+ 1195              		.loc 1 7994 11 view .LVU442
+ 1196 0006 23F07003 		bic	r3, r3, #112
+ 1197              	.LVL129:
+7995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Input Trigger source and the slave mode*/
+7996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ 1198              		.loc 1 7996 3 is_stmt 1 view .LVU443
+ 1199              		.loc 1 7996 11 is_stmt 0 view .LVU444
+ 1200 000a 0B43     		orrs	r3, r3, r1
+ 1201              	.LVL130:
+ 1202              		.loc 1 7996 11 view .LVU445
+ARM GAS  /tmp/cc0wMqvE.s 			page 162
+
+
+ 1203 000c 43F00703 		orr	r3, r3, #7
+ 1204              	.LVL131:
+7997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx SMCR */
+7998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->SMCR = tmpsmcr;
+ 1205              		.loc 1 7998 3 is_stmt 1 view .LVU446
+ 1206              		.loc 1 7998 14 is_stmt 0 view .LVU447
+ 1207 0010 8360     		str	r3, [r0, #8]
+7999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1208              		.loc 1 7999 1 view .LVU448
+ 1209 0012 7047     		bx	lr
+ 1210              		.cfi_endproc
+ 1211              	.LFE447:
+ 1213              		.section	.text.HAL_TIM_Base_MspInit,"ax",%progbits
+ 1214              		.align	1
+ 1215              		.weak	HAL_TIM_Base_MspInit
+ 1216              		.syntax unified
+ 1217              		.thumb
+ 1218              		.thumb_func
+ 1220              	HAL_TIM_Base_MspInit:
+ 1221              	.LVL132:
+ 1222              	.LFB331:
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 1223              		.loc 1 384 1 is_stmt 1 view -0
+ 1224              		.cfi_startproc
+ 1225              		@ args = 0, pretend = 0, frame = 0
+ 1226              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1227              		@ link register save eliminated.
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1228              		.loc 1 386 3 view .LVU450
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1229              		.loc 1 391 1 is_stmt 0 view .LVU451
+ 1230 0000 7047     		bx	lr
+ 1231              		.cfi_endproc
+ 1232              	.LFE331:
+ 1234              		.section	.text.HAL_TIM_Base_MspDeInit,"ax",%progbits
+ 1235              		.align	1
+ 1236              		.weak	HAL_TIM_Base_MspDeInit
+ 1237              		.syntax unified
+ 1238              		.thumb
+ 1239              		.thumb_func
+ 1241              	HAL_TIM_Base_MspDeInit:
+ 1242              	.LVL133:
+ 1243              	.LFB332:
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 1244              		.loc 1 399 1 is_stmt 1 view -0
+ 1245              		.cfi_startproc
+ 1246              		@ args = 0, pretend = 0, frame = 0
+ 1247              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1248              		@ link register save eliminated.
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1249              		.loc 1 401 3 view .LVU453
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1250              		.loc 1 406 1 is_stmt 0 view .LVU454
+ 1251 0000 7047     		bx	lr
+ 1252              		.cfi_endproc
+ 1253              	.LFE332:
+ 1255              		.section	.text.HAL_TIM_Base_DeInit,"ax",%progbits
+ARM GAS  /tmp/cc0wMqvE.s 			page 163
+
+
+ 1256              		.align	1
+ 1257              		.global	HAL_TIM_Base_DeInit
+ 1258              		.syntax unified
+ 1259              		.thumb
+ 1260              		.thumb_func
+ 1262              	HAL_TIM_Base_DeInit:
+ 1263              	.LVL134:
+ 1264              	.LFB330:
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 1265              		.loc 1 341 1 is_stmt 1 view -0
+ 1266              		.cfi_startproc
+ 1267              		@ args = 0, pretend = 0, frame = 0
+ 1268              		@ frame_needed = 0, uses_anonymous_args = 0
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 1269              		.loc 1 341 1 is_stmt 0 view .LVU456
+ 1270 0000 10B5     		push	{r4, lr}
+ 1271              	.LCFI20:
+ 1272              		.cfi_def_cfa_offset 8
+ 1273              		.cfi_offset 4, -8
+ 1274              		.cfi_offset 14, -4
+ 1275 0002 0446     		mov	r4, r0
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1276              		.loc 1 343 3 is_stmt 1 view .LVU457
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1277              		.loc 1 345 3 view .LVU458
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1278              		.loc 1 345 15 is_stmt 0 view .LVU459
+ 1279 0004 0223     		movs	r3, #2
+ 1280 0006 80F83D30 		strb	r3, [r0, #61]
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1281              		.loc 1 348 3 is_stmt 1 view .LVU460
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1282              		.loc 1 348 3 view .LVU461
+ 1283 000a 0368     		ldr	r3, [r0]
+ 1284 000c 196A     		ldr	r1, [r3, #32]
+ 1285 000e 41F21112 		movw	r2, #4369
+ 1286 0012 1142     		tst	r1, r2
+ 1287 0014 08D1     		bne	.L51
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1288              		.loc 1 348 3 discriminator 1 view .LVU462
+ 1289 0016 196A     		ldr	r1, [r3, #32]
+ 1290 0018 44F24442 		movw	r2, #17476
+ 1291 001c 1142     		tst	r1, r2
+ 1292 001e 03D1     		bne	.L51
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1293              		.loc 1 348 3 discriminator 3 view .LVU463
+ 1294 0020 1A68     		ldr	r2, [r3]
+ 1295 0022 22F00102 		bic	r2, r2, #1
+ 1296 0026 1A60     		str	r2, [r3]
+ 1297              	.L51:
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1298              		.loc 1 348 3 discriminator 5 view .LVU464
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 1299              		.loc 1 359 3 discriminator 5 view .LVU465
+ 1300 0028 2046     		mov	r0, r4
+ 1301              	.LVL135:
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ARM GAS  /tmp/cc0wMqvE.s 			page 164
+
+
+ 1302              		.loc 1 359 3 is_stmt 0 discriminator 5 view .LVU466
+ 1303 002a FFF7FEFF 		bl	HAL_TIM_Base_MspDeInit
+ 1304              	.LVL136:
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1305              		.loc 1 363 3 is_stmt 1 discriminator 5 view .LVU467
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1306              		.loc 1 363 23 is_stmt 0 discriminator 5 view .LVU468
+ 1307 002e 0020     		movs	r0, #0
+ 1308 0030 84F84800 		strb	r0, [r4, #72]
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1309              		.loc 1 366 3 is_stmt 1 discriminator 5 view .LVU469
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1310              		.loc 1 366 3 discriminator 5 view .LVU470
+ 1311 0034 84F83E00 		strb	r0, [r4, #62]
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1312              		.loc 1 366 3 discriminator 5 view .LVU471
+ 1313 0038 84F83F00 		strb	r0, [r4, #63]
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1314              		.loc 1 366 3 discriminator 5 view .LVU472
+ 1315 003c 84F84000 		strb	r0, [r4, #64]
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1316              		.loc 1 366 3 discriminator 5 view .LVU473
+ 1317 0040 84F84100 		strb	r0, [r4, #65]
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1318              		.loc 1 366 3 discriminator 5 view .LVU474
+ 1319 0044 84F84200 		strb	r0, [r4, #66]
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1320              		.loc 1 366 3 discriminator 5 view .LVU475
+ 1321 0048 84F84300 		strb	r0, [r4, #67]
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1322              		.loc 1 366 3 discriminator 5 view .LVU476
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1323              		.loc 1 367 3 discriminator 5 view .LVU477
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1324              		.loc 1 367 3 discriminator 5 view .LVU478
+ 1325 004c 84F84400 		strb	r0, [r4, #68]
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1326              		.loc 1 367 3 discriminator 5 view .LVU479
+ 1327 0050 84F84500 		strb	r0, [r4, #69]
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1328              		.loc 1 367 3 discriminator 5 view .LVU480
+ 1329 0054 84F84600 		strb	r0, [r4, #70]
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1330              		.loc 1 367 3 discriminator 5 view .LVU481
+ 1331 0058 84F84700 		strb	r0, [r4, #71]
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1332              		.loc 1 367 3 discriminator 5 view .LVU482
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1333              		.loc 1 370 3 discriminator 5 view .LVU483
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1334              		.loc 1 370 15 is_stmt 0 discriminator 5 view .LVU484
+ 1335 005c 84F83D00 		strb	r0, [r4, #61]
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1336              		.loc 1 373 3 is_stmt 1 discriminator 5 view .LVU485
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1337              		.loc 1 373 3 discriminator 5 view .LVU486
+ 1338 0060 84F83C00 		strb	r0, [r4, #60]
+ARM GAS  /tmp/cc0wMqvE.s 			page 165
+
+
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1339              		.loc 1 373 3 discriminator 5 view .LVU487
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1340              		.loc 1 375 3 discriminator 5 view .LVU488
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1341              		.loc 1 376 1 is_stmt 0 discriminator 5 view .LVU489
+ 1342 0064 10BD     		pop	{r4, pc}
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1343              		.loc 1 376 1 discriminator 5 view .LVU490
+ 1344              		.cfi_endproc
+ 1345              	.LFE330:
+ 1347              		.section	.text.HAL_TIM_Base_Start,"ax",%progbits
+ 1348              		.align	1
+ 1349              		.global	HAL_TIM_Base_Start
+ 1350              		.syntax unified
+ 1351              		.thumb
+ 1352              		.thumb_func
+ 1354              	HAL_TIM_Base_Start:
+ 1355              	.LVL137:
+ 1356              	.LFB333:
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 1357              		.loc 1 415 1 is_stmt 1 view -0
+ 1358              		.cfi_startproc
+ 1359              		@ args = 0, pretend = 0, frame = 0
+ 1360              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1361              		@ link register save eliminated.
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1362              		.loc 1 416 3 view .LVU492
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1363              		.loc 1 419 3 view .LVU493
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1364              		.loc 1 422 3 view .LVU494
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1365              		.loc 1 422 11 is_stmt 0 view .LVU495
+ 1366 0000 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+ 1367 0004 DBB2     		uxtb	r3, r3
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1368              		.loc 1 422 6 view .LVU496
+ 1369 0006 012B     		cmp	r3, #1
+ 1370 0008 2DD1     		bne	.L57
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1371              		.loc 1 428 3 is_stmt 1 view .LVU497
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1372              		.loc 1 428 15 is_stmt 0 view .LVU498
+ 1373 000a 0223     		movs	r3, #2
+ 1374 000c 80F83D30 		strb	r3, [r0, #61]
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1375              		.loc 1 431 3 is_stmt 1 view .LVU499
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1376              		.loc 1 431 7 is_stmt 0 view .LVU500
+ 1377 0010 0368     		ldr	r3, [r0]
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1378              		.loc 1 431 6 view .LVU501
+ 1379 0012 184A     		ldr	r2, .L60
+ 1380 0014 9342     		cmp	r3, r2
+ 1381 0016 18D0     		beq	.L55
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 166
+
+
+ 1382              		.loc 1 431 7 discriminator 1 view .LVU502
+ 1383 0018 B3F1804F 		cmp	r3, #1073741824
+ 1384 001c 15D0     		beq	.L55
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1385              		.loc 1 431 7 discriminator 2 view .LVU503
+ 1386 001e A2F59432 		sub	r2, r2, #75776
+ 1387 0022 9342     		cmp	r3, r2
+ 1388 0024 11D0     		beq	.L55
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1389              		.loc 1 431 7 discriminator 3 view .LVU504
+ 1390 0026 02F58062 		add	r2, r2, #1024
+ 1391 002a 9342     		cmp	r3, r2
+ 1392 002c 0DD0     		beq	.L55
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1393              		.loc 1 431 7 discriminator 4 view .LVU505
+ 1394 002e 02F59632 		add	r2, r2, #76800
+ 1395 0032 9342     		cmp	r3, r2
+ 1396 0034 09D0     		beq	.L55
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1397              		.loc 1 431 7 discriminator 5 view .LVU506
+ 1398 0036 02F54062 		add	r2, r2, #3072
+ 1399 003a 9342     		cmp	r3, r2
+ 1400 003c 05D0     		beq	.L55
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 1401              		.loc 1 441 5 is_stmt 1 view .LVU507
+ 1402 003e 1A68     		ldr	r2, [r3]
+ 1403 0040 42F00102 		orr	r2, r2, #1
+ 1404 0044 1A60     		str	r2, [r3]
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1405              		.loc 1 445 10 is_stmt 0 view .LVU508
+ 1406 0046 0020     		movs	r0, #0
+ 1407              	.LVL138:
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1408              		.loc 1 445 10 view .LVU509
+ 1409 0048 7047     		bx	lr
+ 1410              	.LVL139:
+ 1411              	.L55:
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1412              		.loc 1 433 5 is_stmt 1 view .LVU510
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1413              		.loc 1 433 29 is_stmt 0 view .LVU511
+ 1414 004a 9968     		ldr	r1, [r3, #8]
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1415              		.loc 1 433 13 view .LVU512
+ 1416 004c 0A4A     		ldr	r2, .L60+4
+ 1417 004e 0A40     		ands	r2, r2, r1
+ 1418              	.LVL140:
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 1419              		.loc 1 434 5 is_stmt 1 view .LVU513
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 1420              		.loc 1 434 8 is_stmt 0 view .LVU514
+ 1421 0050 062A     		cmp	r2, #6
+ 1422 0052 0AD0     		beq	.L58
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 1423              		.loc 1 434 9 discriminator 1 view .LVU515
+ 1424 0054 B2F5803F 		cmp	r2, #65536
+ 1425 0058 09D0     		beq	.L59
+ARM GAS  /tmp/cc0wMqvE.s 			page 167
+
+
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 1426              		.loc 1 436 7 is_stmt 1 view .LVU516
+ 1427 005a 1A68     		ldr	r2, [r3]
+ 1428              	.LVL141:
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 1429              		.loc 1 436 7 is_stmt 0 view .LVU517
+ 1430 005c 42F00102 		orr	r2, r2, #1
+ 1431 0060 1A60     		str	r2, [r3]
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1432              		.loc 1 445 10 view .LVU518
+ 1433 0062 0020     		movs	r0, #0
+ 1434              	.LVL142:
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1435              		.loc 1 445 10 view .LVU519
+ 1436 0064 7047     		bx	lr
+ 1437              	.LVL143:
+ 1438              	.L57:
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 1439              		.loc 1 424 12 view .LVU520
+ 1440 0066 0120     		movs	r0, #1
+ 1441              	.LVL144:
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 1442              		.loc 1 424 12 view .LVU521
+ 1443 0068 7047     		bx	lr
+ 1444              	.LVL145:
+ 1445              	.L58:
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1446              		.loc 1 445 10 view .LVU522
+ 1447 006a 0020     		movs	r0, #0
+ 1448              	.LVL146:
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1449              		.loc 1 445 10 view .LVU523
+ 1450 006c 7047     		bx	lr
+ 1451              	.LVL147:
+ 1452              	.L59:
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1453              		.loc 1 445 10 view .LVU524
+ 1454 006e 0020     		movs	r0, #0
+ 1455              	.LVL148:
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1456              		.loc 1 446 1 view .LVU525
+ 1457 0070 7047     		bx	lr
+ 1458              	.L61:
+ 1459 0072 00BF     		.align	2
+ 1460              	.L60:
+ 1461 0074 002C0140 		.word	1073818624
+ 1462 0078 07000100 		.word	65543
+ 1463              		.cfi_endproc
+ 1464              	.LFE333:
+ 1466              		.section	.text.HAL_TIM_Base_Stop,"ax",%progbits
+ 1467              		.align	1
+ 1468              		.global	HAL_TIM_Base_Stop
+ 1469              		.syntax unified
+ 1470              		.thumb
+ 1471              		.thumb_func
+ 1473              	HAL_TIM_Base_Stop:
+ 1474              	.LVL149:
+ARM GAS  /tmp/cc0wMqvE.s 			page 168
+
+
+ 1475              	.LFB334:
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 1476              		.loc 1 454 1 is_stmt 1 view -0
+ 1477              		.cfi_startproc
+ 1478              		@ args = 0, pretend = 0, frame = 0
+ 1479              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1480              		@ link register save eliminated.
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1481              		.loc 1 456 3 view .LVU527
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1482              		.loc 1 459 3 view .LVU528
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1483              		.loc 1 459 3 view .LVU529
+ 1484 0000 0368     		ldr	r3, [r0]
+ 1485 0002 196A     		ldr	r1, [r3, #32]
+ 1486 0004 41F21112 		movw	r2, #4369
+ 1487 0008 1142     		tst	r1, r2
+ 1488 000a 08D1     		bne	.L63
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1489              		.loc 1 459 3 discriminator 1 view .LVU530
+ 1490 000c 196A     		ldr	r1, [r3, #32]
+ 1491 000e 44F24442 		movw	r2, #17476
+ 1492 0012 1142     		tst	r1, r2
+ 1493 0014 03D1     		bne	.L63
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1494              		.loc 1 459 3 discriminator 3 view .LVU531
+ 1495 0016 1A68     		ldr	r2, [r3]
+ 1496 0018 22F00102 		bic	r2, r2, #1
+ 1497 001c 1A60     		str	r2, [r3]
+ 1498              	.L63:
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1499              		.loc 1 459 3 discriminator 5 view .LVU532
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1500              		.loc 1 462 3 discriminator 5 view .LVU533
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1501              		.loc 1 462 15 is_stmt 0 discriminator 5 view .LVU534
+ 1502 001e 0123     		movs	r3, #1
+ 1503 0020 80F83D30 		strb	r3, [r0, #61]
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1504              		.loc 1 465 3 is_stmt 1 discriminator 5 view .LVU535
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1505              		.loc 1 466 1 is_stmt 0 discriminator 5 view .LVU536
+ 1506 0024 0020     		movs	r0, #0
+ 1507              	.LVL150:
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1508              		.loc 1 466 1 discriminator 5 view .LVU537
+ 1509 0026 7047     		bx	lr
+ 1510              		.cfi_endproc
+ 1511              	.LFE334:
+ 1513              		.section	.text.HAL_TIM_Base_Start_IT,"ax",%progbits
+ 1514              		.align	1
+ 1515              		.global	HAL_TIM_Base_Start_IT
+ 1516              		.syntax unified
+ 1517              		.thumb
+ 1518              		.thumb_func
+ 1520              	HAL_TIM_Base_Start_IT:
+ 1521              	.LVL151:
+ARM GAS  /tmp/cc0wMqvE.s 			page 169
+
+
+ 1522              	.LFB335:
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 1523              		.loc 1 474 1 is_stmt 1 view -0
+ 1524              		.cfi_startproc
+ 1525              		@ args = 0, pretend = 0, frame = 0
+ 1526              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1527              		@ link register save eliminated.
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1528              		.loc 1 475 3 view .LVU539
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1529              		.loc 1 478 3 view .LVU540
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1530              		.loc 1 481 3 view .LVU541
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1531              		.loc 1 481 11 is_stmt 0 view .LVU542
+ 1532 0000 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+ 1533 0004 DBB2     		uxtb	r3, r3
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1534              		.loc 1 481 6 view .LVU543
+ 1535 0006 012B     		cmp	r3, #1
+ 1536 0008 32D1     		bne	.L68
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1537              		.loc 1 487 3 is_stmt 1 view .LVU544
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1538              		.loc 1 487 15 is_stmt 0 view .LVU545
+ 1539 000a 0223     		movs	r3, #2
+ 1540 000c 80F83D30 		strb	r3, [r0, #61]
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1541              		.loc 1 490 3 is_stmt 1 view .LVU546
+ 1542 0010 0268     		ldr	r2, [r0]
+ 1543 0012 D368     		ldr	r3, [r2, #12]
+ 1544 0014 43F00103 		orr	r3, r3, #1
+ 1545 0018 D360     		str	r3, [r2, #12]
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1546              		.loc 1 493 3 view .LVU547
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1547              		.loc 1 493 7 is_stmt 0 view .LVU548
+ 1548 001a 0368     		ldr	r3, [r0]
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1549              		.loc 1 493 6 view .LVU549
+ 1550 001c 174A     		ldr	r2, .L71
+ 1551 001e 9342     		cmp	r3, r2
+ 1552 0020 18D0     		beq	.L66
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1553              		.loc 1 493 7 discriminator 1 view .LVU550
+ 1554 0022 B3F1804F 		cmp	r3, #1073741824
+ 1555 0026 15D0     		beq	.L66
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1556              		.loc 1 493 7 discriminator 2 view .LVU551
+ 1557 0028 A2F59432 		sub	r2, r2, #75776
+ 1558 002c 9342     		cmp	r3, r2
+ 1559 002e 11D0     		beq	.L66
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1560              		.loc 1 493 7 discriminator 3 view .LVU552
+ 1561 0030 02F58062 		add	r2, r2, #1024
+ 1562 0034 9342     		cmp	r3, r2
+ 1563 0036 0DD0     		beq	.L66
+ARM GAS  /tmp/cc0wMqvE.s 			page 170
+
+
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1564              		.loc 1 493 7 discriminator 4 view .LVU553
+ 1565 0038 02F59632 		add	r2, r2, #76800
+ 1566 003c 9342     		cmp	r3, r2
+ 1567 003e 09D0     		beq	.L66
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1568              		.loc 1 493 7 discriminator 5 view .LVU554
+ 1569 0040 02F54062 		add	r2, r2, #3072
+ 1570 0044 9342     		cmp	r3, r2
+ 1571 0046 05D0     		beq	.L66
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 1572              		.loc 1 503 5 is_stmt 1 view .LVU555
+ 1573 0048 1A68     		ldr	r2, [r3]
+ 1574 004a 42F00102 		orr	r2, r2, #1
+ 1575 004e 1A60     		str	r2, [r3]
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1576              		.loc 1 507 10 is_stmt 0 view .LVU556
+ 1577 0050 0020     		movs	r0, #0
+ 1578              	.LVL152:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1579              		.loc 1 507 10 view .LVU557
+ 1580 0052 7047     		bx	lr
+ 1581              	.LVL153:
+ 1582              	.L66:
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1583              		.loc 1 495 5 is_stmt 1 view .LVU558
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1584              		.loc 1 495 29 is_stmt 0 view .LVU559
+ 1585 0054 9968     		ldr	r1, [r3, #8]
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1586              		.loc 1 495 13 view .LVU560
+ 1587 0056 0A4A     		ldr	r2, .L71+4
+ 1588 0058 0A40     		ands	r2, r2, r1
+ 1589              	.LVL154:
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 1590              		.loc 1 496 5 is_stmt 1 view .LVU561
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 1591              		.loc 1 496 8 is_stmt 0 view .LVU562
+ 1592 005a 062A     		cmp	r2, #6
+ 1593 005c 0AD0     		beq	.L69
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 1594              		.loc 1 496 9 discriminator 1 view .LVU563
+ 1595 005e B2F5803F 		cmp	r2, #65536
+ 1596 0062 09D0     		beq	.L70
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 1597              		.loc 1 498 7 is_stmt 1 view .LVU564
+ 1598 0064 1A68     		ldr	r2, [r3]
+ 1599              	.LVL155:
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 1600              		.loc 1 498 7 is_stmt 0 view .LVU565
+ 1601 0066 42F00102 		orr	r2, r2, #1
+ 1602 006a 1A60     		str	r2, [r3]
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1603              		.loc 1 507 10 view .LVU566
+ 1604 006c 0020     		movs	r0, #0
+ 1605              	.LVL156:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ARM GAS  /tmp/cc0wMqvE.s 			page 171
+
+
+ 1606              		.loc 1 507 10 view .LVU567
+ 1607 006e 7047     		bx	lr
+ 1608              	.LVL157:
+ 1609              	.L68:
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 1610              		.loc 1 483 12 view .LVU568
+ 1611 0070 0120     		movs	r0, #1
+ 1612              	.LVL158:
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 1613              		.loc 1 483 12 view .LVU569
+ 1614 0072 7047     		bx	lr
+ 1615              	.LVL159:
+ 1616              	.L69:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1617              		.loc 1 507 10 view .LVU570
+ 1618 0074 0020     		movs	r0, #0
+ 1619              	.LVL160:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1620              		.loc 1 507 10 view .LVU571
+ 1621 0076 7047     		bx	lr
+ 1622              	.LVL161:
+ 1623              	.L70:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1624              		.loc 1 507 10 view .LVU572
+ 1625 0078 0020     		movs	r0, #0
+ 1626              	.LVL162:
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1627              		.loc 1 508 1 view .LVU573
+ 1628 007a 7047     		bx	lr
+ 1629              	.L72:
+ 1630              		.align	2
+ 1631              	.L71:
+ 1632 007c 002C0140 		.word	1073818624
+ 1633 0080 07000100 		.word	65543
+ 1634              		.cfi_endproc
+ 1635              	.LFE335:
+ 1637              		.section	.text.HAL_TIM_Base_Stop_IT,"ax",%progbits
+ 1638              		.align	1
+ 1639              		.global	HAL_TIM_Base_Stop_IT
+ 1640              		.syntax unified
+ 1641              		.thumb
+ 1642              		.thumb_func
+ 1644              	HAL_TIM_Base_Stop_IT:
+ 1645              	.LVL163:
+ 1646              	.LFB336:
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 1647              		.loc 1 516 1 is_stmt 1 view -0
+ 1648              		.cfi_startproc
+ 1649              		@ args = 0, pretend = 0, frame = 0
+ 1650              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1651              		@ link register save eliminated.
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1652              		.loc 1 518 3 view .LVU575
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1653              		.loc 1 521 3 view .LVU576
+ 1654 0000 0268     		ldr	r2, [r0]
+ 1655 0002 D368     		ldr	r3, [r2, #12]
+ARM GAS  /tmp/cc0wMqvE.s 			page 172
+
+
+ 1656 0004 23F00103 		bic	r3, r3, #1
+ 1657 0008 D360     		str	r3, [r2, #12]
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1658              		.loc 1 524 3 view .LVU577
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1659              		.loc 1 524 3 view .LVU578
+ 1660 000a 0368     		ldr	r3, [r0]
+ 1661 000c 196A     		ldr	r1, [r3, #32]
+ 1662 000e 41F21112 		movw	r2, #4369
+ 1663 0012 1142     		tst	r1, r2
+ 1664 0014 08D1     		bne	.L74
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1665              		.loc 1 524 3 discriminator 1 view .LVU579
+ 1666 0016 196A     		ldr	r1, [r3, #32]
+ 1667 0018 44F24442 		movw	r2, #17476
+ 1668 001c 1142     		tst	r1, r2
+ 1669 001e 03D1     		bne	.L74
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1670              		.loc 1 524 3 discriminator 3 view .LVU580
+ 1671 0020 1A68     		ldr	r2, [r3]
+ 1672 0022 22F00102 		bic	r2, r2, #1
+ 1673 0026 1A60     		str	r2, [r3]
+ 1674              	.L74:
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1675              		.loc 1 524 3 discriminator 5 view .LVU581
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1676              		.loc 1 527 3 discriminator 5 view .LVU582
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1677              		.loc 1 527 15 is_stmt 0 discriminator 5 view .LVU583
+ 1678 0028 0123     		movs	r3, #1
+ 1679 002a 80F83D30 		strb	r3, [r0, #61]
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1680              		.loc 1 530 3 is_stmt 1 discriminator 5 view .LVU584
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1681              		.loc 1 531 1 is_stmt 0 discriminator 5 view .LVU585
+ 1682 002e 0020     		movs	r0, #0
+ 1683              	.LVL164:
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1684              		.loc 1 531 1 discriminator 5 view .LVU586
+ 1685 0030 7047     		bx	lr
+ 1686              		.cfi_endproc
+ 1687              	.LFE336:
+ 1689              		.section	.text.HAL_TIM_Base_Start_DMA,"ax",%progbits
+ 1690              		.align	1
+ 1691              		.global	HAL_TIM_Base_Start_DMA
+ 1692              		.syntax unified
+ 1693              		.thumb
+ 1694              		.thumb_func
+ 1696              	HAL_TIM_Base_Start_DMA:
+ 1697              	.LVL165:
+ 1698              	.LFB337:
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 1699              		.loc 1 541 1 is_stmt 1 view -0
+ 1700              		.cfi_startproc
+ 1701              		@ args = 0, pretend = 0, frame = 0
+ 1702              		@ frame_needed = 0, uses_anonymous_args = 0
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ARM GAS  /tmp/cc0wMqvE.s 			page 173
+
+
+ 1703              		.loc 1 541 1 is_stmt 0 view .LVU588
+ 1704 0000 38B5     		push	{r3, r4, r5, lr}
+ 1705              	.LCFI21:
+ 1706              		.cfi_def_cfa_offset 16
+ 1707              		.cfi_offset 3, -16
+ 1708              		.cfi_offset 4, -12
+ 1709              		.cfi_offset 5, -8
+ 1710              		.cfi_offset 14, -4
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1711              		.loc 1 542 3 is_stmt 1 view .LVU589
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1712              		.loc 1 545 3 view .LVU590
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1713              		.loc 1 548 3 view .LVU591
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1714              		.loc 1 548 11 is_stmt 0 view .LVU592
+ 1715 0002 90F83D40 		ldrb	r4, [r0, #61]	@ zero_extendqisi2
+ 1716 0006 E4B2     		uxtb	r4, r4
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1717              		.loc 1 548 6 view .LVU593
+ 1718 0008 022C     		cmp	r4, #2
+ 1719 000a 51D0     		beq	.L76
+ 1720 000c 0546     		mov	r5, r0
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1721              		.loc 1 552 8 is_stmt 1 view .LVU594
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1722              		.loc 1 552 16 is_stmt 0 view .LVU595
+ 1723 000e 90F83D40 		ldrb	r4, [r0, #61]	@ zero_extendqisi2
+ 1724 0012 E4B2     		uxtb	r4, r4
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1725              		.loc 1 552 11 view .LVU596
+ 1726 0014 012C     		cmp	r4, #1
+ 1727 0016 4AD1     		bne	.L80
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 1728              		.loc 1 554 5 is_stmt 1 view .LVU597
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 1729              		.loc 1 554 8 is_stmt 0 view .LVU598
+ 1730 0018 0029     		cmp	r1, #0
+ 1731 001a 37D0     		beq	.L84
+ 1732              	.L77:
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 1733              		.loc 1 560 7 is_stmt 1 view .LVU599
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 1734              		.loc 1 560 19 is_stmt 0 view .LVU600
+ 1735 001c 0223     		movs	r3, #2
+ 1736 001e 85F83D30 		strb	r3, [r5, #61]
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 1737              		.loc 1 569 3 is_stmt 1 view .LVU601
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 1738              		.loc 1 569 13 is_stmt 0 view .LVU602
+ 1739 0022 2B6A     		ldr	r3, [r5, #32]
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 1740              		.loc 1 569 51 view .LVU603
+ 1741 0024 2548     		ldr	r0, .L85
+ 1742              	.LVL166:
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 1743              		.loc 1 569 51 view .LVU604
+ARM GAS  /tmp/cc0wMqvE.s 			page 174
+
+
+ 1744 0026 D862     		str	r0, [r3, #44]
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1745              		.loc 1 570 3 is_stmt 1 view .LVU605
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1746              		.loc 1 570 13 is_stmt 0 view .LVU606
+ 1747 0028 2B6A     		ldr	r3, [r5, #32]
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1748              		.loc 1 570 55 view .LVU607
+ 1749 002a 2548     		ldr	r0, .L85+4
+ 1750 002c 1863     		str	r0, [r3, #48]
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1751              		.loc 1 573 3 is_stmt 1 view .LVU608
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1752              		.loc 1 573 13 is_stmt 0 view .LVU609
+ 1753 002e 2B6A     		ldr	r3, [r5, #32]
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1754              		.loc 1 573 52 view .LVU610
+ 1755 0030 2448     		ldr	r0, .L85+8
+ 1756 0032 5863     		str	r0, [r3, #52]
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                        Length) != HAL_OK)
+ 1757              		.loc 1 576 3 is_stmt 1 view .LVU611
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                        Length) != HAL_OK)
+ 1758              		.loc 1 576 87 is_stmt 0 view .LVU612
+ 1759 0034 2868     		ldr	r0, [r5]
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                        Length) != HAL_OK)
+ 1760              		.loc 1 576 7 view .LVU613
+ 1761 0036 1346     		mov	r3, r2
+ 1762 0038 00F12C02 		add	r2, r0, #44
+ 1763              	.LVL167:
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                        Length) != HAL_OK)
+ 1764              		.loc 1 576 7 view .LVU614
+ 1765 003c 286A     		ldr	r0, [r5, #32]
+ 1766 003e FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 1767              	.LVL168:
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                        Length) != HAL_OK)
+ 1768              		.loc 1 576 6 view .LVU615
+ 1769 0042 0146     		mov	r1, r0
+ 1770 0044 0028     		cmp	r0, #0
+ 1771 0046 33D1     		bne	.L76
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1772              		.loc 1 584 3 is_stmt 1 view .LVU616
+ 1773 0048 2A68     		ldr	r2, [r5]
+ 1774 004a D368     		ldr	r3, [r2, #12]
+ 1775 004c 43F48073 		orr	r3, r3, #256
+ 1776 0050 D360     		str	r3, [r2, #12]
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1777              		.loc 1 587 3 view .LVU617
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1778              		.loc 1 587 7 is_stmt 0 view .LVU618
+ 1779 0052 2B68     		ldr	r3, [r5]
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1780              		.loc 1 587 6 view .LVU619
+ 1781 0054 1C4A     		ldr	r2, .L85+12
+ 1782 0056 9342     		cmp	r3, r2
+ 1783 0058 1BD0     		beq	.L78
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1784              		.loc 1 587 7 discriminator 1 view .LVU620
+ARM GAS  /tmp/cc0wMqvE.s 			page 175
+
+
+ 1785 005a B3F1804F 		cmp	r3, #1073741824
+ 1786 005e 18D0     		beq	.L78
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1787              		.loc 1 587 7 discriminator 2 view .LVU621
+ 1788 0060 A2F59432 		sub	r2, r2, #75776
+ 1789 0064 9342     		cmp	r3, r2
+ 1790 0066 14D0     		beq	.L78
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1791              		.loc 1 587 7 discriminator 3 view .LVU622
+ 1792 0068 02F58062 		add	r2, r2, #1024
+ 1793 006c 9342     		cmp	r3, r2
+ 1794 006e 10D0     		beq	.L78
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1795              		.loc 1 587 7 discriminator 4 view .LVU623
+ 1796 0070 02F59632 		add	r2, r2, #76800
+ 1797 0074 9342     		cmp	r3, r2
+ 1798 0076 0CD0     		beq	.L78
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 1799              		.loc 1 587 7 discriminator 5 view .LVU624
+ 1800 0078 02F54062 		add	r2, r2, #3072
+ 1801 007c 9342     		cmp	r3, r2
+ 1802 007e 08D0     		beq	.L78
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 1803              		.loc 1 597 5 is_stmt 1 view .LVU625
+ 1804 0080 1A68     		ldr	r2, [r3]
+ 1805 0082 42F00102 		orr	r2, r2, #1
+ 1806 0086 1A60     		str	r2, [r3]
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1807              		.loc 1 601 10 is_stmt 0 view .LVU626
+ 1808 0088 0446     		mov	r4, r0
+ 1809 008a 11E0     		b	.L76
+ 1810              	.LVL169:
+ 1811              	.L84:
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 1812              		.loc 1 554 25 discriminator 1 view .LVU627
+ 1813 008c 002A     		cmp	r2, #0
+ 1814 008e C5D0     		beq	.L77
+ 1815 0090 0EE0     		b	.L76
+ 1816              	.LVL170:
+ 1817              	.L78:
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1818              		.loc 1 589 5 is_stmt 1 view .LVU628
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1819              		.loc 1 589 29 is_stmt 0 view .LVU629
+ 1820 0092 9868     		ldr	r0, [r3, #8]
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1821              		.loc 1 589 13 view .LVU630
+ 1822 0094 0D4A     		ldr	r2, .L85+16
+ 1823 0096 0240     		ands	r2, r2, r0
+ 1824              	.LVL171:
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 1825              		.loc 1 590 5 is_stmt 1 view .LVU631
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 1826              		.loc 1 590 8 is_stmt 0 view .LVU632
+ 1827 0098 062A     		cmp	r2, #6
+ 1828 009a 0BD0     		beq	.L81
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ARM GAS  /tmp/cc0wMqvE.s 			page 176
+
+
+ 1829              		.loc 1 590 9 discriminator 1 view .LVU633
+ 1830 009c B2F5803F 		cmp	r2, #65536
+ 1831 00a0 0AD0     		beq	.L82
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 1832              		.loc 1 592 7 is_stmt 1 view .LVU634
+ 1833 00a2 1A68     		ldr	r2, [r3]
+ 1834              	.LVL172:
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 1835              		.loc 1 592 7 is_stmt 0 view .LVU635
+ 1836 00a4 42F00102 		orr	r2, r2, #1
+ 1837 00a8 1A60     		str	r2, [r3]
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1838              		.loc 1 601 10 view .LVU636
+ 1839 00aa 0C46     		mov	r4, r1
+ 1840 00ac 00E0     		b	.L76
+ 1841              	.LVL173:
+ 1842              	.L80:
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 1843              		.loc 1 565 12 view .LVU637
+ 1844 00ae 0124     		movs	r4, #1
+ 1845              	.LVL174:
+ 1846              	.L76:
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1847              		.loc 1 602 1 view .LVU638
+ 1848 00b0 2046     		mov	r0, r4
+ 1849 00b2 38BD     		pop	{r3, r4, r5, pc}
+ 1850              	.LVL175:
+ 1851              	.L81:
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1852              		.loc 1 601 10 view .LVU639
+ 1853 00b4 0C46     		mov	r4, r1
+ 1854 00b6 FBE7     		b	.L76
+ 1855              	.L82:
+ 1856 00b8 0C46     		mov	r4, r1
+ 1857 00ba F9E7     		b	.L76
+ 1858              	.L86:
+ 1859              		.align	2
+ 1860              	.L85:
+ 1861 00bc 00000000 		.word	TIM_DMAPeriodElapsedCplt
+ 1862 00c0 00000000 		.word	TIM_DMAPeriodElapsedHalfCplt
+ 1863 00c4 00000000 		.word	TIM_DMAError
+ 1864 00c8 002C0140 		.word	1073818624
+ 1865 00cc 07000100 		.word	65543
+ 1866              		.cfi_endproc
+ 1867              	.LFE337:
+ 1869              		.section	.text.HAL_TIM_Base_Stop_DMA,"ax",%progbits
+ 1870              		.align	1
+ 1871              		.global	HAL_TIM_Base_Stop_DMA
+ 1872              		.syntax unified
+ 1873              		.thumb
+ 1874              		.thumb_func
+ 1876              	HAL_TIM_Base_Stop_DMA:
+ 1877              	.LVL176:
+ 1878              	.LFB338:
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 1879              		.loc 1 610 1 is_stmt 1 view -0
+ 1880              		.cfi_startproc
+ARM GAS  /tmp/cc0wMqvE.s 			page 177
+
+
+ 1881              		@ args = 0, pretend = 0, frame = 0
+ 1882              		@ frame_needed = 0, uses_anonymous_args = 0
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 1883              		.loc 1 610 1 is_stmt 0 view .LVU641
+ 1884 0000 10B5     		push	{r4, lr}
+ 1885              	.LCFI22:
+ 1886              		.cfi_def_cfa_offset 8
+ 1887              		.cfi_offset 4, -8
+ 1888              		.cfi_offset 14, -4
+ 1889 0002 0446     		mov	r4, r0
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1890              		.loc 1 612 3 is_stmt 1 view .LVU642
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1891              		.loc 1 615 3 view .LVU643
+ 1892 0004 0268     		ldr	r2, [r0]
+ 1893 0006 D368     		ldr	r3, [r2, #12]
+ 1894 0008 23F48073 		bic	r3, r3, #256
+ 1895 000c D360     		str	r3, [r2, #12]
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1896              		.loc 1 617 3 view .LVU644
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1897              		.loc 1 617 9 is_stmt 0 view .LVU645
+ 1898 000e 006A     		ldr	r0, [r0, #32]
+ 1899              	.LVL177:
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1900              		.loc 1 617 9 view .LVU646
+ 1901 0010 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 1902              	.LVL178:
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1903              		.loc 1 620 3 is_stmt 1 view .LVU647
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1904              		.loc 1 620 3 view .LVU648
+ 1905 0014 2368     		ldr	r3, [r4]
+ 1906 0016 196A     		ldr	r1, [r3, #32]
+ 1907 0018 41F21112 		movw	r2, #4369
+ 1908 001c 1142     		tst	r1, r2
+ 1909 001e 08D1     		bne	.L88
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1910              		.loc 1 620 3 discriminator 1 view .LVU649
+ 1911 0020 196A     		ldr	r1, [r3, #32]
+ 1912 0022 44F24442 		movw	r2, #17476
+ 1913 0026 1142     		tst	r1, r2
+ 1914 0028 03D1     		bne	.L88
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1915              		.loc 1 620 3 discriminator 3 view .LVU650
+ 1916 002a 1A68     		ldr	r2, [r3]
+ 1917 002c 22F00102 		bic	r2, r2, #1
+ 1918 0030 1A60     		str	r2, [r3]
+ 1919              	.L88:
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1920              		.loc 1 620 3 discriminator 5 view .LVU651
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1921              		.loc 1 623 3 discriminator 5 view .LVU652
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1922              		.loc 1 623 15 is_stmt 0 discriminator 5 view .LVU653
+ 1923 0032 0123     		movs	r3, #1
+ 1924 0034 84F83D30 		strb	r3, [r4, #61]
+ARM GAS  /tmp/cc0wMqvE.s 			page 178
+
+
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 1925              		.loc 1 626 3 is_stmt 1 discriminator 5 view .LVU654
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1926              		.loc 1 627 1 is_stmt 0 discriminator 5 view .LVU655
+ 1927 0038 0020     		movs	r0, #0
+ 1928 003a 10BD     		pop	{r4, pc}
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1929              		.loc 1 627 1 discriminator 5 view .LVU656
+ 1930              		.cfi_endproc
+ 1931              	.LFE338:
+ 1933              		.section	.text.HAL_TIM_OC_MspInit,"ax",%progbits
+ 1934              		.align	1
+ 1935              		.weak	HAL_TIM_OC_MspInit
+ 1936              		.syntax unified
+ 1937              		.thumb
+ 1938              		.thumb_func
+ 1940              	HAL_TIM_OC_MspInit:
+ 1941              	.LVL179:
+ 1942              	.LFB341:
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 1943              		.loc 1 767 1 is_stmt 1 view -0
+ 1944              		.cfi_startproc
+ 1945              		@ args = 0, pretend = 0, frame = 0
+ 1946              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1947              		@ link register save eliminated.
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1948              		.loc 1 769 3 view .LVU658
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1949              		.loc 1 774 1 is_stmt 0 view .LVU659
+ 1950 0000 7047     		bx	lr
+ 1951              		.cfi_endproc
+ 1952              	.LFE341:
+ 1954              		.section	.text.HAL_TIM_OC_MspDeInit,"ax",%progbits
+ 1955              		.align	1
+ 1956              		.weak	HAL_TIM_OC_MspDeInit
+ 1957              		.syntax unified
+ 1958              		.thumb
+ 1959              		.thumb_func
+ 1961              	HAL_TIM_OC_MspDeInit:
+ 1962              	.LVL180:
+ 1963              	.LFB342:
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 1964              		.loc 1 782 1 is_stmt 1 view -0
+ 1965              		.cfi_startproc
+ 1966              		@ args = 0, pretend = 0, frame = 0
+ 1967              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1968              		@ link register save eliminated.
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1969              		.loc 1 784 3 view .LVU661
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1970              		.loc 1 789 1 is_stmt 0 view .LVU662
+ 1971 0000 7047     		bx	lr
+ 1972              		.cfi_endproc
+ 1973              	.LFE342:
+ 1975              		.section	.text.HAL_TIM_OC_DeInit,"ax",%progbits
+ 1976              		.align	1
+ 1977              		.global	HAL_TIM_OC_DeInit
+ARM GAS  /tmp/cc0wMqvE.s 			page 179
+
+
+ 1978              		.syntax unified
+ 1979              		.thumb
+ 1980              		.thumb_func
+ 1982              	HAL_TIM_OC_DeInit:
+ 1983              	.LVL181:
+ 1984              	.LFB340:
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 1985              		.loc 1 724 1 is_stmt 1 view -0
+ 1986              		.cfi_startproc
+ 1987              		@ args = 0, pretend = 0, frame = 0
+ 1988              		@ frame_needed = 0, uses_anonymous_args = 0
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 1989              		.loc 1 724 1 is_stmt 0 view .LVU664
+ 1990 0000 10B5     		push	{r4, lr}
+ 1991              	.LCFI23:
+ 1992              		.cfi_def_cfa_offset 8
+ 1993              		.cfi_offset 4, -8
+ 1994              		.cfi_offset 14, -4
+ 1995 0002 0446     		mov	r4, r0
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1996              		.loc 1 726 3 is_stmt 1 view .LVU665
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1997              		.loc 1 728 3 view .LVU666
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 1998              		.loc 1 728 15 is_stmt 0 view .LVU667
+ 1999 0004 0223     		movs	r3, #2
+ 2000 0006 80F83D30 		strb	r3, [r0, #61]
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2001              		.loc 1 731 3 is_stmt 1 view .LVU668
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2002              		.loc 1 731 3 view .LVU669
+ 2003 000a 0368     		ldr	r3, [r0]
+ 2004 000c 196A     		ldr	r1, [r3, #32]
+ 2005 000e 41F21112 		movw	r2, #4369
+ 2006 0012 1142     		tst	r1, r2
+ 2007 0014 08D1     		bne	.L93
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2008              		.loc 1 731 3 discriminator 1 view .LVU670
+ 2009 0016 196A     		ldr	r1, [r3, #32]
+ 2010 0018 44F24442 		movw	r2, #17476
+ 2011 001c 1142     		tst	r1, r2
+ 2012 001e 03D1     		bne	.L93
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2013              		.loc 1 731 3 discriminator 3 view .LVU671
+ 2014 0020 1A68     		ldr	r2, [r3]
+ 2015 0022 22F00102 		bic	r2, r2, #1
+ 2016 0026 1A60     		str	r2, [r3]
+ 2017              	.L93:
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2018              		.loc 1 731 3 discriminator 5 view .LVU672
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2019              		.loc 1 742 3 discriminator 5 view .LVU673
+ 2020 0028 2046     		mov	r0, r4
+ 2021              	.LVL182:
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2022              		.loc 1 742 3 is_stmt 0 discriminator 5 view .LVU674
+ 2023 002a FFF7FEFF 		bl	HAL_TIM_OC_MspDeInit
+ARM GAS  /tmp/cc0wMqvE.s 			page 180
+
+
+ 2024              	.LVL183:
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2025              		.loc 1 746 3 is_stmt 1 discriminator 5 view .LVU675
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2026              		.loc 1 746 23 is_stmt 0 discriminator 5 view .LVU676
+ 2027 002e 0020     		movs	r0, #0
+ 2028 0030 84F84800 		strb	r0, [r4, #72]
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2029              		.loc 1 749 3 is_stmt 1 discriminator 5 view .LVU677
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2030              		.loc 1 749 3 discriminator 5 view .LVU678
+ 2031 0034 84F83E00 		strb	r0, [r4, #62]
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2032              		.loc 1 749 3 discriminator 5 view .LVU679
+ 2033 0038 84F83F00 		strb	r0, [r4, #63]
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2034              		.loc 1 749 3 discriminator 5 view .LVU680
+ 2035 003c 84F84000 		strb	r0, [r4, #64]
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2036              		.loc 1 749 3 discriminator 5 view .LVU681
+ 2037 0040 84F84100 		strb	r0, [r4, #65]
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2038              		.loc 1 749 3 discriminator 5 view .LVU682
+ 2039 0044 84F84200 		strb	r0, [r4, #66]
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2040              		.loc 1 749 3 discriminator 5 view .LVU683
+ 2041 0048 84F84300 		strb	r0, [r4, #67]
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2042              		.loc 1 749 3 discriminator 5 view .LVU684
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2043              		.loc 1 750 3 discriminator 5 view .LVU685
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2044              		.loc 1 750 3 discriminator 5 view .LVU686
+ 2045 004c 84F84400 		strb	r0, [r4, #68]
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2046              		.loc 1 750 3 discriminator 5 view .LVU687
+ 2047 0050 84F84500 		strb	r0, [r4, #69]
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2048              		.loc 1 750 3 discriminator 5 view .LVU688
+ 2049 0054 84F84600 		strb	r0, [r4, #70]
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2050              		.loc 1 750 3 discriminator 5 view .LVU689
+ 2051 0058 84F84700 		strb	r0, [r4, #71]
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2052              		.loc 1 750 3 discriminator 5 view .LVU690
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2053              		.loc 1 753 3 discriminator 5 view .LVU691
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2054              		.loc 1 753 15 is_stmt 0 discriminator 5 view .LVU692
+ 2055 005c 84F83D00 		strb	r0, [r4, #61]
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2056              		.loc 1 756 3 is_stmt 1 discriminator 5 view .LVU693
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2057              		.loc 1 756 3 discriminator 5 view .LVU694
+ 2058 0060 84F83C00 		strb	r0, [r4, #60]
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2059              		.loc 1 756 3 discriminator 5 view .LVU695
+ARM GAS  /tmp/cc0wMqvE.s 			page 181
+
+
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 2060              		.loc 1 758 3 discriminator 5 view .LVU696
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2061              		.loc 1 759 1 is_stmt 0 discriminator 5 view .LVU697
+ 2062 0064 10BD     		pop	{r4, pc}
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2063              		.loc 1 759 1 discriminator 5 view .LVU698
+ 2064              		.cfi_endproc
+ 2065              	.LFE340:
+ 2067              		.section	.text.HAL_TIM_PWM_MspInit,"ax",%progbits
+ 2068              		.align	1
+ 2069              		.weak	HAL_TIM_PWM_MspInit
+ 2070              		.syntax unified
+ 2071              		.thumb
+ 2072              		.thumb_func
+ 2074              	HAL_TIM_PWM_MspInit:
+ 2075              	.LVL184:
+ 2076              	.LFB351:
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2077              		.loc 1 1434 1 is_stmt 1 view -0
+ 2078              		.cfi_startproc
+ 2079              		@ args = 0, pretend = 0, frame = 0
+ 2080              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2081              		@ link register save eliminated.
+1436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2082              		.loc 1 1436 3 view .LVU700
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2083              		.loc 1 1441 1 is_stmt 0 view .LVU701
+ 2084 0000 7047     		bx	lr
+ 2085              		.cfi_endproc
+ 2086              	.LFE351:
+ 2088              		.section	.text.HAL_TIM_PWM_MspDeInit,"ax",%progbits
+ 2089              		.align	1
+ 2090              		.weak	HAL_TIM_PWM_MspDeInit
+ 2091              		.syntax unified
+ 2092              		.thumb
+ 2093              		.thumb_func
+ 2095              	HAL_TIM_PWM_MspDeInit:
+ 2096              	.LVL185:
+ 2097              	.LFB352:
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2098              		.loc 1 1449 1 is_stmt 1 view -0
+ 2099              		.cfi_startproc
+ 2100              		@ args = 0, pretend = 0, frame = 0
+ 2101              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2102              		@ link register save eliminated.
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2103              		.loc 1 1451 3 view .LVU703
+1456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2104              		.loc 1 1456 1 is_stmt 0 view .LVU704
+ 2105 0000 7047     		bx	lr
+ 2106              		.cfi_endproc
+ 2107              	.LFE352:
+ 2109              		.section	.text.HAL_TIM_PWM_DeInit,"ax",%progbits
+ 2110              		.align	1
+ 2111              		.global	HAL_TIM_PWM_DeInit
+ 2112              		.syntax unified
+ARM GAS  /tmp/cc0wMqvE.s 			page 182
+
+
+ 2113              		.thumb
+ 2114              		.thumb_func
+ 2116              	HAL_TIM_PWM_DeInit:
+ 2117              	.LVL186:
+ 2118              	.LFB350:
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 2119              		.loc 1 1391 1 is_stmt 1 view -0
+ 2120              		.cfi_startproc
+ 2121              		@ args = 0, pretend = 0, frame = 0
+ 2122              		@ frame_needed = 0, uses_anonymous_args = 0
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 2123              		.loc 1 1391 1 is_stmt 0 view .LVU706
+ 2124 0000 10B5     		push	{r4, lr}
+ 2125              	.LCFI24:
+ 2126              		.cfi_def_cfa_offset 8
+ 2127              		.cfi_offset 4, -8
+ 2128              		.cfi_offset 14, -4
+ 2129 0002 0446     		mov	r4, r0
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2130              		.loc 1 1393 3 is_stmt 1 view .LVU707
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2131              		.loc 1 1395 3 view .LVU708
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2132              		.loc 1 1395 15 is_stmt 0 view .LVU709
+ 2133 0004 0223     		movs	r3, #2
+ 2134 0006 80F83D30 		strb	r3, [r0, #61]
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2135              		.loc 1 1398 3 is_stmt 1 view .LVU710
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2136              		.loc 1 1398 3 view .LVU711
+ 2137 000a 0368     		ldr	r3, [r0]
+ 2138 000c 196A     		ldr	r1, [r3, #32]
+ 2139 000e 41F21112 		movw	r2, #4369
+ 2140 0012 1142     		tst	r1, r2
+ 2141 0014 08D1     		bne	.L98
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2142              		.loc 1 1398 3 discriminator 1 view .LVU712
+ 2143 0016 196A     		ldr	r1, [r3, #32]
+ 2144 0018 44F24442 		movw	r2, #17476
+ 2145 001c 1142     		tst	r1, r2
+ 2146 001e 03D1     		bne	.L98
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2147              		.loc 1 1398 3 discriminator 3 view .LVU713
+ 2148 0020 1A68     		ldr	r2, [r3]
+ 2149 0022 22F00102 		bic	r2, r2, #1
+ 2150 0026 1A60     		str	r2, [r3]
+ 2151              	.L98:
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2152              		.loc 1 1398 3 discriminator 5 view .LVU714
+1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2153              		.loc 1 1409 3 discriminator 5 view .LVU715
+ 2154 0028 2046     		mov	r0, r4
+ 2155              	.LVL187:
+1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2156              		.loc 1 1409 3 is_stmt 0 discriminator 5 view .LVU716
+ 2157 002a FFF7FEFF 		bl	HAL_TIM_PWM_MspDeInit
+ 2158              	.LVL188:
+ARM GAS  /tmp/cc0wMqvE.s 			page 183
+
+
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2159              		.loc 1 1413 3 is_stmt 1 discriminator 5 view .LVU717
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2160              		.loc 1 1413 23 is_stmt 0 discriminator 5 view .LVU718
+ 2161 002e 0020     		movs	r0, #0
+ 2162 0030 84F84800 		strb	r0, [r4, #72]
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2163              		.loc 1 1416 3 is_stmt 1 discriminator 5 view .LVU719
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2164              		.loc 1 1416 3 discriminator 5 view .LVU720
+ 2165 0034 84F83E00 		strb	r0, [r4, #62]
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2166              		.loc 1 1416 3 discriminator 5 view .LVU721
+ 2167 0038 84F83F00 		strb	r0, [r4, #63]
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2168              		.loc 1 1416 3 discriminator 5 view .LVU722
+ 2169 003c 84F84000 		strb	r0, [r4, #64]
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2170              		.loc 1 1416 3 discriminator 5 view .LVU723
+ 2171 0040 84F84100 		strb	r0, [r4, #65]
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2172              		.loc 1 1416 3 discriminator 5 view .LVU724
+ 2173 0044 84F84200 		strb	r0, [r4, #66]
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2174              		.loc 1 1416 3 discriminator 5 view .LVU725
+ 2175 0048 84F84300 		strb	r0, [r4, #67]
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2176              		.loc 1 1416 3 discriminator 5 view .LVU726
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2177              		.loc 1 1417 3 discriminator 5 view .LVU727
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2178              		.loc 1 1417 3 discriminator 5 view .LVU728
+ 2179 004c 84F84400 		strb	r0, [r4, #68]
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2180              		.loc 1 1417 3 discriminator 5 view .LVU729
+ 2181 0050 84F84500 		strb	r0, [r4, #69]
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2182              		.loc 1 1417 3 discriminator 5 view .LVU730
+ 2183 0054 84F84600 		strb	r0, [r4, #70]
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2184              		.loc 1 1417 3 discriminator 5 view .LVU731
+ 2185 0058 84F84700 		strb	r0, [r4, #71]
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2186              		.loc 1 1417 3 discriminator 5 view .LVU732
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2187              		.loc 1 1420 3 discriminator 5 view .LVU733
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2188              		.loc 1 1420 15 is_stmt 0 discriminator 5 view .LVU734
+ 2189 005c 84F83D00 		strb	r0, [r4, #61]
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2190              		.loc 1 1423 3 is_stmt 1 discriminator 5 view .LVU735
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2191              		.loc 1 1423 3 discriminator 5 view .LVU736
+ 2192 0060 84F83C00 		strb	r0, [r4, #60]
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2193              		.loc 1 1423 3 discriminator 5 view .LVU737
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ARM GAS  /tmp/cc0wMqvE.s 			page 184
+
+
+ 2194              		.loc 1 1425 3 discriminator 5 view .LVU738
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2195              		.loc 1 1426 1 is_stmt 0 discriminator 5 view .LVU739
+ 2196 0064 10BD     		pop	{r4, pc}
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2197              		.loc 1 1426 1 discriminator 5 view .LVU740
+ 2198              		.cfi_endproc
+ 2199              	.LFE350:
+ 2201              		.section	.text.HAL_TIM_IC_MspInit,"ax",%progbits
+ 2202              		.align	1
+ 2203              		.weak	HAL_TIM_IC_MspInit
+ 2204              		.syntax unified
+ 2205              		.thumb
+ 2206              		.thumb_func
+ 2208              	HAL_TIM_IC_MspInit:
+ 2209              	.LVL189:
+ 2210              	.LFB361:
+2100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2211              		.loc 1 2100 1 is_stmt 1 view -0
+ 2212              		.cfi_startproc
+ 2213              		@ args = 0, pretend = 0, frame = 0
+ 2214              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2215              		@ link register save eliminated.
+2102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2216              		.loc 1 2102 3 view .LVU742
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2217              		.loc 1 2107 1 is_stmt 0 view .LVU743
+ 2218 0000 7047     		bx	lr
+ 2219              		.cfi_endproc
+ 2220              	.LFE361:
+ 2222              		.section	.text.HAL_TIM_IC_MspDeInit,"ax",%progbits
+ 2223              		.align	1
+ 2224              		.weak	HAL_TIM_IC_MspDeInit
+ 2225              		.syntax unified
+ 2226              		.thumb
+ 2227              		.thumb_func
+ 2229              	HAL_TIM_IC_MspDeInit:
+ 2230              	.LVL190:
+ 2231              	.LFB362:
+2115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2232              		.loc 1 2115 1 is_stmt 1 view -0
+ 2233              		.cfi_startproc
+ 2234              		@ args = 0, pretend = 0, frame = 0
+ 2235              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2236              		@ link register save eliminated.
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2237              		.loc 1 2117 3 view .LVU745
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2238              		.loc 1 2122 1 is_stmt 0 view .LVU746
+ 2239 0000 7047     		bx	lr
+ 2240              		.cfi_endproc
+ 2241              	.LFE362:
+ 2243              		.section	.text.HAL_TIM_IC_DeInit,"ax",%progbits
+ 2244              		.align	1
+ 2245              		.global	HAL_TIM_IC_DeInit
+ 2246              		.syntax unified
+ 2247              		.thumb
+ARM GAS  /tmp/cc0wMqvE.s 			page 185
+
+
+ 2248              		.thumb_func
+ 2250              	HAL_TIM_IC_DeInit:
+ 2251              	.LVL191:
+ 2252              	.LFB360:
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 2253              		.loc 1 2057 1 is_stmt 1 view -0
+ 2254              		.cfi_startproc
+ 2255              		@ args = 0, pretend = 0, frame = 0
+ 2256              		@ frame_needed = 0, uses_anonymous_args = 0
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 2257              		.loc 1 2057 1 is_stmt 0 view .LVU748
+ 2258 0000 10B5     		push	{r4, lr}
+ 2259              	.LCFI25:
+ 2260              		.cfi_def_cfa_offset 8
+ 2261              		.cfi_offset 4, -8
+ 2262              		.cfi_offset 14, -4
+ 2263 0002 0446     		mov	r4, r0
+2059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2264              		.loc 1 2059 3 is_stmt 1 view .LVU749
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2265              		.loc 1 2061 3 view .LVU750
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2266              		.loc 1 2061 15 is_stmt 0 view .LVU751
+ 2267 0004 0223     		movs	r3, #2
+ 2268 0006 80F83D30 		strb	r3, [r0, #61]
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2269              		.loc 1 2064 3 is_stmt 1 view .LVU752
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2270              		.loc 1 2064 3 view .LVU753
+ 2271 000a 0368     		ldr	r3, [r0]
+ 2272 000c 196A     		ldr	r1, [r3, #32]
+ 2273 000e 41F21112 		movw	r2, #4369
+ 2274 0012 1142     		tst	r1, r2
+ 2275 0014 08D1     		bne	.L103
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2276              		.loc 1 2064 3 discriminator 1 view .LVU754
+ 2277 0016 196A     		ldr	r1, [r3, #32]
+ 2278 0018 44F24442 		movw	r2, #17476
+ 2279 001c 1142     		tst	r1, r2
+ 2280 001e 03D1     		bne	.L103
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2281              		.loc 1 2064 3 discriminator 3 view .LVU755
+ 2282 0020 1A68     		ldr	r2, [r3]
+ 2283 0022 22F00102 		bic	r2, r2, #1
+ 2284 0026 1A60     		str	r2, [r3]
+ 2285              	.L103:
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2286              		.loc 1 2064 3 discriminator 5 view .LVU756
+2075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2287              		.loc 1 2075 3 discriminator 5 view .LVU757
+ 2288 0028 2046     		mov	r0, r4
+ 2289              	.LVL192:
+2075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2290              		.loc 1 2075 3 is_stmt 0 discriminator 5 view .LVU758
+ 2291 002a FFF7FEFF 		bl	HAL_TIM_IC_MspDeInit
+ 2292              	.LVL193:
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 186
+
+
+ 2293              		.loc 1 2079 3 is_stmt 1 discriminator 5 view .LVU759
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2294              		.loc 1 2079 23 is_stmt 0 discriminator 5 view .LVU760
+ 2295 002e 0020     		movs	r0, #0
+ 2296 0030 84F84800 		strb	r0, [r4, #72]
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2297              		.loc 1 2082 3 is_stmt 1 discriminator 5 view .LVU761
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2298              		.loc 1 2082 3 discriminator 5 view .LVU762
+ 2299 0034 84F83E00 		strb	r0, [r4, #62]
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2300              		.loc 1 2082 3 discriminator 5 view .LVU763
+ 2301 0038 84F83F00 		strb	r0, [r4, #63]
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2302              		.loc 1 2082 3 discriminator 5 view .LVU764
+ 2303 003c 84F84000 		strb	r0, [r4, #64]
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2304              		.loc 1 2082 3 discriminator 5 view .LVU765
+ 2305 0040 84F84100 		strb	r0, [r4, #65]
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2306              		.loc 1 2082 3 discriminator 5 view .LVU766
+ 2307 0044 84F84200 		strb	r0, [r4, #66]
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2308              		.loc 1 2082 3 discriminator 5 view .LVU767
+ 2309 0048 84F84300 		strb	r0, [r4, #67]
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2310              		.loc 1 2082 3 discriminator 5 view .LVU768
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2311              		.loc 1 2083 3 discriminator 5 view .LVU769
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2312              		.loc 1 2083 3 discriminator 5 view .LVU770
+ 2313 004c 84F84400 		strb	r0, [r4, #68]
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2314              		.loc 1 2083 3 discriminator 5 view .LVU771
+ 2315 0050 84F84500 		strb	r0, [r4, #69]
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2316              		.loc 1 2083 3 discriminator 5 view .LVU772
+ 2317 0054 84F84600 		strb	r0, [r4, #70]
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2318              		.loc 1 2083 3 discriminator 5 view .LVU773
+ 2319 0058 84F84700 		strb	r0, [r4, #71]
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2320              		.loc 1 2083 3 discriminator 5 view .LVU774
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2321              		.loc 1 2086 3 discriminator 5 view .LVU775
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2322              		.loc 1 2086 15 is_stmt 0 discriminator 5 view .LVU776
+ 2323 005c 84F83D00 		strb	r0, [r4, #61]
+2089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2324              		.loc 1 2089 3 is_stmt 1 discriminator 5 view .LVU777
+2089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2325              		.loc 1 2089 3 discriminator 5 view .LVU778
+ 2326 0060 84F83C00 		strb	r0, [r4, #60]
+2089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2327              		.loc 1 2089 3 discriminator 5 view .LVU779
+2091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 2328              		.loc 1 2091 3 discriminator 5 view .LVU780
+ARM GAS  /tmp/cc0wMqvE.s 			page 187
+
+
+2092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2329              		.loc 1 2092 1 is_stmt 0 discriminator 5 view .LVU781
+ 2330 0064 10BD     		pop	{r4, pc}
+2092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2331              		.loc 1 2092 1 discriminator 5 view .LVU782
+ 2332              		.cfi_endproc
+ 2333              	.LFE360:
+ 2335              		.section	.text.HAL_TIM_OnePulse_MspInit,"ax",%progbits
+ 2336              		.align	1
+ 2337              		.weak	HAL_TIM_OnePulse_MspInit
+ 2338              		.syntax unified
+ 2339              		.thumb
+ 2340              		.thumb_func
+ 2342              	HAL_TIM_OnePulse_MspInit:
+ 2343              	.LVL194:
+ 2344              	.LFB371:
+2759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2345              		.loc 1 2759 1 is_stmt 1 view -0
+ 2346              		.cfi_startproc
+ 2347              		@ args = 0, pretend = 0, frame = 0
+ 2348              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2349              		@ link register save eliminated.
+2761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2350              		.loc 1 2761 3 view .LVU784
+2766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2351              		.loc 1 2766 1 is_stmt 0 view .LVU785
+ 2352 0000 7047     		bx	lr
+ 2353              		.cfi_endproc
+ 2354              	.LFE371:
+ 2356              		.section	.text.HAL_TIM_OnePulse_MspDeInit,"ax",%progbits
+ 2357              		.align	1
+ 2358              		.weak	HAL_TIM_OnePulse_MspDeInit
+ 2359              		.syntax unified
+ 2360              		.thumb
+ 2361              		.thumb_func
+ 2363              	HAL_TIM_OnePulse_MspDeInit:
+ 2364              	.LVL195:
+ 2365              	.LFB372:
+2774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2366              		.loc 1 2774 1 is_stmt 1 view -0
+ 2367              		.cfi_startproc
+ 2368              		@ args = 0, pretend = 0, frame = 0
+ 2369              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2370              		@ link register save eliminated.
+2776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2371              		.loc 1 2776 3 view .LVU787
+2781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2372              		.loc 1 2781 1 is_stmt 0 view .LVU788
+ 2373 0000 7047     		bx	lr
+ 2374              		.cfi_endproc
+ 2375              	.LFE372:
+ 2377              		.section	.text.HAL_TIM_OnePulse_DeInit,"ax",%progbits
+ 2378              		.align	1
+ 2379              		.global	HAL_TIM_OnePulse_DeInit
+ 2380              		.syntax unified
+ 2381              		.thumb
+ 2382              		.thumb_func
+ARM GAS  /tmp/cc0wMqvE.s 			page 188
+
+
+ 2384              	HAL_TIM_OnePulse_DeInit:
+ 2385              	.LVL196:
+ 2386              	.LFB370:
+2714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 2387              		.loc 1 2714 1 is_stmt 1 view -0
+ 2388              		.cfi_startproc
+ 2389              		@ args = 0, pretend = 0, frame = 0
+ 2390              		@ frame_needed = 0, uses_anonymous_args = 0
+2714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 2391              		.loc 1 2714 1 is_stmt 0 view .LVU790
+ 2392 0000 10B5     		push	{r4, lr}
+ 2393              	.LCFI26:
+ 2394              		.cfi_def_cfa_offset 8
+ 2395              		.cfi_offset 4, -8
+ 2396              		.cfi_offset 14, -4
+ 2397 0002 0446     		mov	r4, r0
+2716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2398              		.loc 1 2716 3 is_stmt 1 view .LVU791
+2718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2399              		.loc 1 2718 3 view .LVU792
+2718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2400              		.loc 1 2718 15 is_stmt 0 view .LVU793
+ 2401 0004 0223     		movs	r3, #2
+ 2402 0006 80F83D30 		strb	r3, [r0, #61]
+2721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2403              		.loc 1 2721 3 is_stmt 1 view .LVU794
+2721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2404              		.loc 1 2721 3 view .LVU795
+ 2405 000a 0368     		ldr	r3, [r0]
+ 2406 000c 196A     		ldr	r1, [r3, #32]
+ 2407 000e 41F21112 		movw	r2, #4369
+ 2408 0012 1142     		tst	r1, r2
+ 2409 0014 08D1     		bne	.L108
+2721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2410              		.loc 1 2721 3 discriminator 1 view .LVU796
+ 2411 0016 196A     		ldr	r1, [r3, #32]
+ 2412 0018 44F24442 		movw	r2, #17476
+ 2413 001c 1142     		tst	r1, r2
+ 2414 001e 03D1     		bne	.L108
+2721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2415              		.loc 1 2721 3 discriminator 3 view .LVU797
+ 2416 0020 1A68     		ldr	r2, [r3]
+ 2417 0022 22F00102 		bic	r2, r2, #1
+ 2418 0026 1A60     		str	r2, [r3]
+ 2419              	.L108:
+2721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2420              		.loc 1 2721 3 discriminator 5 view .LVU798
+2732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2421              		.loc 1 2732 3 discriminator 5 view .LVU799
+ 2422 0028 2046     		mov	r0, r4
+ 2423              	.LVL197:
+2732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2424              		.loc 1 2732 3 is_stmt 0 discriminator 5 view .LVU800
+ 2425 002a FFF7FEFF 		bl	HAL_TIM_OnePulse_MspDeInit
+ 2426              	.LVL198:
+2736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2427              		.loc 1 2736 3 is_stmt 1 discriminator 5 view .LVU801
+ARM GAS  /tmp/cc0wMqvE.s 			page 189
+
+
+2736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2428              		.loc 1 2736 23 is_stmt 0 discriminator 5 view .LVU802
+ 2429 002e 0020     		movs	r0, #0
+ 2430 0030 84F84800 		strb	r0, [r4, #72]
+2739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 2431              		.loc 1 2739 3 is_stmt 1 discriminator 5 view .LVU803
+ 2432 0034 84F83E00 		strb	r0, [r4, #62]
+2740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ 2433              		.loc 1 2740 3 discriminator 5 view .LVU804
+ 2434 0038 84F83F00 		strb	r0, [r4, #63]
+2741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 2435              		.loc 1 2741 3 discriminator 5 view .LVU805
+ 2436 003c 84F84400 		strb	r0, [r4, #68]
+2742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2437              		.loc 1 2742 3 discriminator 5 view .LVU806
+ 2438 0040 84F84500 		strb	r0, [r4, #69]
+2745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2439              		.loc 1 2745 3 discriminator 5 view .LVU807
+2745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2440              		.loc 1 2745 15 is_stmt 0 discriminator 5 view .LVU808
+ 2441 0044 84F83D00 		strb	r0, [r4, #61]
+2748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2442              		.loc 1 2748 3 is_stmt 1 discriminator 5 view .LVU809
+2748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2443              		.loc 1 2748 3 discriminator 5 view .LVU810
+ 2444 0048 84F83C00 		strb	r0, [r4, #60]
+2748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2445              		.loc 1 2748 3 discriminator 5 view .LVU811
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 2446              		.loc 1 2750 3 discriminator 5 view .LVU812
+2751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2447              		.loc 1 2751 1 is_stmt 0 discriminator 5 view .LVU813
+ 2448 004c 10BD     		pop	{r4, pc}
+2751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2449              		.loc 1 2751 1 discriminator 5 view .LVU814
+ 2450              		.cfi_endproc
+ 2451              	.LFE370:
+ 2453              		.section	.text.HAL_TIM_Encoder_MspInit,"ax",%progbits
+ 2454              		.align	1
+ 2455              		.weak	HAL_TIM_Encoder_MspInit
+ 2456              		.syntax unified
+ 2457              		.thumb
+ 2458              		.thumb_func
+ 2460              	HAL_TIM_Encoder_MspInit:
+ 2461              	.LVL199:
+ 2462              	.LFB379:
+3195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2463              		.loc 1 3195 1 is_stmt 1 view -0
+ 2464              		.cfi_startproc
+ 2465              		@ args = 0, pretend = 0, frame = 0
+ 2466              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2467              		@ link register save eliminated.
+3197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2468              		.loc 1 3197 3 view .LVU816
+3202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2469              		.loc 1 3202 1 is_stmt 0 view .LVU817
+ 2470 0000 7047     		bx	lr
+ARM GAS  /tmp/cc0wMqvE.s 			page 190
+
+
+ 2471              		.cfi_endproc
+ 2472              	.LFE379:
+ 2474              		.section	.text.HAL_TIM_Encoder_MspDeInit,"ax",%progbits
+ 2475              		.align	1
+ 2476              		.weak	HAL_TIM_Encoder_MspDeInit
+ 2477              		.syntax unified
+ 2478              		.thumb
+ 2479              		.thumb_func
+ 2481              	HAL_TIM_Encoder_MspDeInit:
+ 2482              	.LVL200:
+ 2483              	.LFB380:
+3210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2484              		.loc 1 3210 1 is_stmt 1 view -0
+ 2485              		.cfi_startproc
+ 2486              		@ args = 0, pretend = 0, frame = 0
+ 2487              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2488              		@ link register save eliminated.
+3212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2489              		.loc 1 3212 3 view .LVU819
+3217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2490              		.loc 1 3217 1 is_stmt 0 view .LVU820
+ 2491 0000 7047     		bx	lr
+ 2492              		.cfi_endproc
+ 2493              	.LFE380:
+ 2495              		.section	.text.HAL_TIM_Encoder_DeInit,"ax",%progbits
+ 2496              		.align	1
+ 2497              		.global	HAL_TIM_Encoder_DeInit
+ 2498              		.syntax unified
+ 2499              		.thumb
+ 2500              		.thumb_func
+ 2502              	HAL_TIM_Encoder_DeInit:
+ 2503              	.LVL201:
+ 2504              	.LFB378:
+3150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 2505              		.loc 1 3150 1 is_stmt 1 view -0
+ 2506              		.cfi_startproc
+ 2507              		@ args = 0, pretend = 0, frame = 0
+ 2508              		@ frame_needed = 0, uses_anonymous_args = 0
+3150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 2509              		.loc 1 3150 1 is_stmt 0 view .LVU822
+ 2510 0000 10B5     		push	{r4, lr}
+ 2511              	.LCFI27:
+ 2512              		.cfi_def_cfa_offset 8
+ 2513              		.cfi_offset 4, -8
+ 2514              		.cfi_offset 14, -4
+ 2515 0002 0446     		mov	r4, r0
+3152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2516              		.loc 1 3152 3 is_stmt 1 view .LVU823
+3154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2517              		.loc 1 3154 3 view .LVU824
+3154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2518              		.loc 1 3154 15 is_stmt 0 view .LVU825
+ 2519 0004 0223     		movs	r3, #2
+ 2520 0006 80F83D30 		strb	r3, [r0, #61]
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2521              		.loc 1 3157 3 is_stmt 1 view .LVU826
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 191
+
+
+ 2522              		.loc 1 3157 3 view .LVU827
+ 2523 000a 0368     		ldr	r3, [r0]
+ 2524 000c 196A     		ldr	r1, [r3, #32]
+ 2525 000e 41F21112 		movw	r2, #4369
+ 2526 0012 1142     		tst	r1, r2
+ 2527 0014 08D1     		bne	.L113
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2528              		.loc 1 3157 3 discriminator 1 view .LVU828
+ 2529 0016 196A     		ldr	r1, [r3, #32]
+ 2530 0018 44F24442 		movw	r2, #17476
+ 2531 001c 1142     		tst	r1, r2
+ 2532 001e 03D1     		bne	.L113
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2533              		.loc 1 3157 3 discriminator 3 view .LVU829
+ 2534 0020 1A68     		ldr	r2, [r3]
+ 2535 0022 22F00102 		bic	r2, r2, #1
+ 2536 0026 1A60     		str	r2, [r3]
+ 2537              	.L113:
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2538              		.loc 1 3157 3 discriminator 5 view .LVU830
+3168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2539              		.loc 1 3168 3 discriminator 5 view .LVU831
+ 2540 0028 2046     		mov	r0, r4
+ 2541              	.LVL202:
+3168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2542              		.loc 1 3168 3 is_stmt 0 discriminator 5 view .LVU832
+ 2543 002a FFF7FEFF 		bl	HAL_TIM_Encoder_MspDeInit
+ 2544              	.LVL203:
+3172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2545              		.loc 1 3172 3 is_stmt 1 discriminator 5 view .LVU833
+3172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2546              		.loc 1 3172 23 is_stmt 0 discriminator 5 view .LVU834
+ 2547 002e 0020     		movs	r0, #0
+ 2548 0030 84F84800 		strb	r0, [r4, #72]
+3175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 2549              		.loc 1 3175 3 is_stmt 1 discriminator 5 view .LVU835
+ 2550 0034 84F83E00 		strb	r0, [r4, #62]
+3176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ 2551              		.loc 1 3176 3 discriminator 5 view .LVU836
+ 2552 0038 84F83F00 		strb	r0, [r4, #63]
+3177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 2553              		.loc 1 3177 3 discriminator 5 view .LVU837
+ 2554 003c 84F84400 		strb	r0, [r4, #68]
+3178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2555              		.loc 1 3178 3 discriminator 5 view .LVU838
+ 2556 0040 84F84500 		strb	r0, [r4, #69]
+3181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2557              		.loc 1 3181 3 discriminator 5 view .LVU839
+3181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2558              		.loc 1 3181 15 is_stmt 0 discriminator 5 view .LVU840
+ 2559 0044 84F83D00 		strb	r0, [r4, #61]
+3184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2560              		.loc 1 3184 3 is_stmt 1 discriminator 5 view .LVU841
+3184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2561              		.loc 1 3184 3 discriminator 5 view .LVU842
+ 2562 0048 84F83C00 		strb	r0, [r4, #60]
+3184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 192
+
+
+ 2563              		.loc 1 3184 3 discriminator 5 view .LVU843
+3186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 2564              		.loc 1 3186 3 discriminator 5 view .LVU844
+3187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2565              		.loc 1 3187 1 is_stmt 0 discriminator 5 view .LVU845
+ 2566 004c 10BD     		pop	{r4, pc}
+3187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2567              		.loc 1 3187 1 discriminator 5 view .LVU846
+ 2568              		.cfi_endproc
+ 2569              	.LFE378:
+ 2571              		.section	.text.HAL_TIM_DMABurst_MultiWriteStart,"ax",%progbits
+ 2572              		.align	1
+ 2573              		.global	HAL_TIM_DMABurst_MultiWriteStart
+ 2574              		.syntax unified
+ 2575              		.thumb
+ 2576              		.thumb_func
+ 2578              	HAL_TIM_DMABurst_MultiWriteStart:
+ 2579              	.LVL204:
+ 2580              	.LFB393:
+4689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2581              		.loc 1 4689 1 is_stmt 1 view -0
+ 2582              		.cfi_startproc
+ 2583              		@ args = 8, pretend = 0, frame = 0
+ 2584              		@ frame_needed = 0, uses_anonymous_args = 0
+4689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2585              		.loc 1 4689 1 is_stmt 0 view .LVU848
+ 2586 0000 70B5     		push	{r4, r5, r6, lr}
+ 2587              	.LCFI28:
+ 2588              		.cfi_def_cfa_offset 16
+ 2589              		.cfi_offset 4, -16
+ 2590              		.cfi_offset 5, -12
+ 2591              		.cfi_offset 6, -8
+ 2592              		.cfi_offset 14, -4
+ 2593 0002 0546     		mov	r5, r0
+4690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2594              		.loc 1 4690 3 is_stmt 1 view .LVU849
+ 2595              	.LVL205:
+4693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ 2596              		.loc 1 4693 3 view .LVU850
+4694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ 2597              		.loc 1 4694 3 view .LVU851
+4695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ 2598              		.loc 1 4695 3 view .LVU852
+4696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+ 2599              		.loc 1 4696 3 view .LVU853
+4697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2600              		.loc 1 4697 3 view .LVU854
+4699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 2601              		.loc 1 4699 3 view .LVU855
+4699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 2602              		.loc 1 4699 11 is_stmt 0 view .LVU856
+ 2603 0004 90F84800 		ldrb	r0, [r0, #72]	@ zero_extendqisi2
+ 2604              	.LVL206:
+4699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 2605              		.loc 1 4699 11 view .LVU857
+ 2606 0008 C0B2     		uxtb	r0, r0
+4699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 193
+
+
+ 2607              		.loc 1 4699 6 view .LVU858
+ 2608 000a 0228     		cmp	r0, #2
+ 2609 000c 4DD0     		beq	.L116
+ 2610 000e 0E46     		mov	r6, r1
+ 2611 0010 1446     		mov	r4, r2
+ 2612 0012 1946     		mov	r1, r3
+ 2613              	.LVL207:
+4703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 2614              		.loc 1 4703 8 is_stmt 1 view .LVU859
+4703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 2615              		.loc 1 4703 16 is_stmt 0 view .LVU860
+ 2616 0014 95F84800 		ldrb	r0, [r5, #72]	@ zero_extendqisi2
+ 2617 0018 C0B2     		uxtb	r0, r0
+4703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 2618              		.loc 1 4703 11 view .LVU861
+ 2619 001a 0128     		cmp	r0, #1
+ 2620 001c 1DD0     		beq	.L136
+ 2621              	.LVL208:
+ 2622              	.L117:
+4717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2623              		.loc 1 4717 3 is_stmt 1 view .LVU862
+4719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 2624              		.loc 1 4719 3 view .LVU863
+ 2625 001e B4F5006F 		cmp	r4, #2048
+ 2626 0022 00F08C80 		beq	.L119
+ 2627 0026 43D8     		bhi	.L120
+ 2628 0028 B4F5007F 		cmp	r4, #512
+ 2629 002c 73D0     		beq	.L121
+ 2630 002e B4F5806F 		cmp	r4, #1024
+ 2631 0032 1BD1     		bne	.L137
+4760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2632              		.loc 1 4760 7 view .LVU864
+4760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2633              		.loc 1 4760 17 is_stmt 0 view .LVU865
+ 2634 0034 AB6A     		ldr	r3, [r5, #40]
+4760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2635              		.loc 1 4760 52 view .LVU866
+ 2636 0036 574A     		ldr	r2, .L143
+ 2637              	.LVL209:
+4760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2638              		.loc 1 4760 52 view .LVU867
+ 2639 0038 DA62     		str	r2, [r3, #44]
+4761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2640              		.loc 1 4761 7 is_stmt 1 view .LVU868
+4761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2641              		.loc 1 4761 17 is_stmt 0 view .LVU869
+ 2642 003a AB6A     		ldr	r3, [r5, #40]
+4761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2643              		.loc 1 4761 56 view .LVU870
+ 2644 003c 564A     		ldr	r2, .L143+4
+ 2645 003e 1A63     		str	r2, [r3, #48]
+4764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2646              		.loc 1 4764 7 is_stmt 1 view .LVU871
+4764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2647              		.loc 1 4764 17 is_stmt 0 view .LVU872
+ 2648 0040 AB6A     		ldr	r3, [r5, #40]
+4764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 194
+
+
+ 2649              		.loc 1 4764 53 view .LVU873
+ 2650 0042 564A     		ldr	r2, .L143+8
+ 2651 0044 5A63     		str	r2, [r3, #52]
+4767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2652              		.loc 1 4767 7 is_stmt 1 view .LVU874
+4768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 2653              		.loc 1 4768 43 is_stmt 0 view .LVU875
+ 2654 0046 2A68     		ldr	r2, [r5]
+4767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2655              		.loc 1 4767 11 view .LVU876
+ 2656 0048 059B     		ldr	r3, [sp, #20]
+ 2657 004a 02F57872 		add	r2, r2, #992
+ 2658 004e A86A     		ldr	r0, [r5, #40]
+ 2659 0050 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2660              	.LVL210:
+4767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2661              		.loc 1 4767 10 view .LVU877
+ 2662 0054 F8B1     		cbz	r0, .L127
+4771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 2663              		.loc 1 4771 16 view .LVU878
+ 2664 0056 0120     		movs	r0, #1
+ 2665 0058 27E0     		b	.L116
+ 2666              	.LVL211:
+ 2667              	.L136:
+4705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 2668              		.loc 1 4705 5 is_stmt 1 view .LVU879
+4705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 2669              		.loc 1 4705 8 is_stmt 0 view .LVU880
+ 2670 005a 1BB1     		cbz	r3, .L138
+ 2671              	.L118:
+4711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 2672              		.loc 1 4711 7 is_stmt 1 view .LVU881
+4711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 2673              		.loc 1 4711 27 is_stmt 0 view .LVU882
+ 2674 005c 0223     		movs	r3, #2
+ 2675 005e 85F84830 		strb	r3, [r5, #72]
+ 2676 0062 DCE7     		b	.L117
+ 2677              	.L138:
+4705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 2678              		.loc 1 4705 31 discriminator 1 view .LVU883
+ 2679 0064 049B     		ldr	r3, [sp, #16]
+ 2680 0066 002B     		cmp	r3, #0
+ 2681 0068 F8D0     		beq	.L118
+ 2682 006a 1EE0     		b	.L116
+ 2683              	.L137:
+4719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 2684              		.loc 1 4719 3 view .LVU884
+ 2685 006c B4F5807F 		cmp	r4, #256
+ 2686 0070 1CD1     		bne	.L139
+4724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 2687              		.loc 1 4724 7 is_stmt 1 view .LVU885
+4724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 2688              		.loc 1 4724 17 is_stmt 0 view .LVU886
+ 2689 0072 2B6A     		ldr	r3, [r5, #32]
+4724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 2690              		.loc 1 4724 55 view .LVU887
+ 2691 0074 4A4A     		ldr	r2, .L143+12
+ARM GAS  /tmp/cc0wMqvE.s 			page 195
+
+
+ 2692              	.LVL212:
+4724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 2693              		.loc 1 4724 55 view .LVU888
+ 2694 0076 DA62     		str	r2, [r3, #44]
+4725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2695              		.loc 1 4725 7 is_stmt 1 view .LVU889
+4725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2696              		.loc 1 4725 17 is_stmt 0 view .LVU890
+ 2697 0078 2B6A     		ldr	r3, [r5, #32]
+4725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2698              		.loc 1 4725 59 view .LVU891
+ 2699 007a 4A4A     		ldr	r2, .L143+16
+ 2700 007c 1A63     		str	r2, [r3, #48]
+4728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2701              		.loc 1 4728 7 is_stmt 1 view .LVU892
+4728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2702              		.loc 1 4728 17 is_stmt 0 view .LVU893
+ 2703 007e 2B6A     		ldr	r3, [r5, #32]
+4728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2704              		.loc 1 4728 56 view .LVU894
+ 2705 0080 464A     		ldr	r2, .L143+8
+ 2706 0082 5A63     		str	r2, [r3, #52]
+4731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2707              		.loc 1 4731 7 is_stmt 1 view .LVU895
+4732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 2708              		.loc 1 4732 43 is_stmt 0 view .LVU896
+ 2709 0084 2A68     		ldr	r2, [r5]
+4731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2710              		.loc 1 4731 11 view .LVU897
+ 2711 0086 059B     		ldr	r3, [sp, #20]
+ 2712 0088 02F57872 		add	r2, r2, #992
+ 2713 008c 286A     		ldr	r0, [r5, #32]
+ 2714 008e FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2715              	.LVL213:
+4731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2716              		.loc 1 4731 10 view .LVU898
+ 2717 0092 0028     		cmp	r0, #0
+ 2718 0094 7BD1     		bne	.L140
+ 2719              	.L127:
+ 2720              	.LVL214:
+4855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the TIM DMA Request */
+ 2721              		.loc 1 4855 5 is_stmt 1 view .LVU899
+4855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the TIM DMA Request */
+ 2722              		.loc 1 4855 9 is_stmt 0 view .LVU900
+ 2723 0096 2B68     		ldr	r3, [r5]
+4855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the TIM DMA Request */
+ 2724              		.loc 1 4855 45 view .LVU901
+ 2725 0098 049A     		ldr	r2, [sp, #16]
+ 2726 009a 1643     		orrs	r6, r6, r2
+ 2727              	.LVL215:
+4855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Enable the TIM DMA Request */
+ 2728              		.loc 1 4855 25 view .LVU902
+ 2729 009c C3F8DC63 		str	r6, [r3, #988]
+4857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 2730              		.loc 1 4857 5 is_stmt 1 view .LVU903
+ 2731 00a0 2A68     		ldr	r2, [r5]
+ 2732 00a2 D368     		ldr	r3, [r2, #12]
+ARM GAS  /tmp/cc0wMqvE.s 			page 196
+
+
+ 2733 00a4 2343     		orrs	r3, r3, r4
+ 2734 00a6 D360     		str	r3, [r2, #12]
+ 2735 00a8 0020     		movs	r0, #0
+ 2736              	.LVL216:
+ 2737              	.L116:
+4862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2738              		.loc 1 4862 1 is_stmt 0 view .LVU904
+ 2739 00aa 70BD     		pop	{r4, r5, r6, pc}
+ 2740              	.LVL217:
+ 2741              	.L139:
+4719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 2742              		.loc 1 4719 3 view .LVU905
+ 2743 00ac 0120     		movs	r0, #1
+ 2744 00ae FCE7     		b	.L116
+ 2745              	.L120:
+4719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 2746              		.loc 1 4719 3 view .LVU906
+ 2747 00b0 B4F5005F 		cmp	r4, #8192
+ 2748 00b4 57D0     		beq	.L124
+ 2749 00b6 B4F5804F 		cmp	r4, #16384
+ 2750 00ba 13D1     		bne	.L141
+4832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 2751              		.loc 1 4832 7 is_stmt 1 view .LVU907
+4832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 2752              		.loc 1 4832 17 is_stmt 0 view .LVU908
+ 2753 00bc AB6B     		ldr	r3, [r5, #56]
+4832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 2754              		.loc 1 4832 56 view .LVU909
+ 2755 00be 3A4A     		ldr	r2, .L143+20
+ 2756              	.LVL218:
+4832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 2757              		.loc 1 4832 56 view .LVU910
+ 2758 00c0 DA62     		str	r2, [r3, #44]
+4833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2759              		.loc 1 4833 7 is_stmt 1 view .LVU911
+4833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2760              		.loc 1 4833 17 is_stmt 0 view .LVU912
+ 2761 00c2 AB6B     		ldr	r3, [r5, #56]
+4833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2762              		.loc 1 4833 60 view .LVU913
+ 2763 00c4 394A     		ldr	r2, .L143+24
+ 2764 00c6 1A63     		str	r2, [r3, #48]
+4836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2765              		.loc 1 4836 7 is_stmt 1 view .LVU914
+4836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2766              		.loc 1 4836 17 is_stmt 0 view .LVU915
+ 2767 00c8 AB6B     		ldr	r3, [r5, #56]
+4836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2768              		.loc 1 4836 57 view .LVU916
+ 2769 00ca 344A     		ldr	r2, .L143+8
+ 2770 00cc 5A63     		str	r2, [r3, #52]
+4839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2771              		.loc 1 4839 7 is_stmt 1 view .LVU917
+4840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 2772              		.loc 1 4840 43 is_stmt 0 view .LVU918
+ 2773 00ce 2A68     		ldr	r2, [r5]
+4839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ARM GAS  /tmp/cc0wMqvE.s 			page 197
+
+
+ 2774              		.loc 1 4839 11 view .LVU919
+ 2775 00d0 059B     		ldr	r3, [sp, #20]
+ 2776 00d2 02F57872 		add	r2, r2, #992
+ 2777 00d6 A86B     		ldr	r0, [r5, #56]
+ 2778 00d8 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2779              	.LVL219:
+4839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2780              		.loc 1 4839 10 view .LVU920
+ 2781 00dc 0028     		cmp	r0, #0
+ 2782 00de DAD0     		beq	.L127
+4843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 2783              		.loc 1 4843 16 view .LVU921
+ 2784 00e0 0120     		movs	r0, #1
+ 2785 00e2 E2E7     		b	.L116
+ 2786              	.LVL220:
+ 2787              	.L141:
+4719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 2788              		.loc 1 4719 3 view .LVU922
+ 2789 00e4 B4F5805F 		cmp	r4, #4096
+ 2790 00e8 13D1     		bne	.L142
+4796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2791              		.loc 1 4796 7 is_stmt 1 view .LVU923
+4796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2792              		.loc 1 4796 17 is_stmt 0 view .LVU924
+ 2793 00ea 2B6B     		ldr	r3, [r5, #48]
+4796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2794              		.loc 1 4796 52 view .LVU925
+ 2795 00ec 294A     		ldr	r2, .L143
+ 2796              	.LVL221:
+4796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2797              		.loc 1 4796 52 view .LVU926
+ 2798 00ee DA62     		str	r2, [r3, #44]
+4797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2799              		.loc 1 4797 7 is_stmt 1 view .LVU927
+4797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2800              		.loc 1 4797 17 is_stmt 0 view .LVU928
+ 2801 00f0 2B6B     		ldr	r3, [r5, #48]
+4797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2802              		.loc 1 4797 56 view .LVU929
+ 2803 00f2 294A     		ldr	r2, .L143+4
+ 2804 00f4 1A63     		str	r2, [r3, #48]
+4800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2805              		.loc 1 4800 7 is_stmt 1 view .LVU930
+4800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2806              		.loc 1 4800 17 is_stmt 0 view .LVU931
+ 2807 00f6 2B6B     		ldr	r3, [r5, #48]
+4800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2808              		.loc 1 4800 53 view .LVU932
+ 2809 00f8 284A     		ldr	r2, .L143+8
+ 2810 00fa 5A63     		str	r2, [r3, #52]
+4803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2811              		.loc 1 4803 7 is_stmt 1 view .LVU933
+4804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 2812              		.loc 1 4804 43 is_stmt 0 view .LVU934
+ 2813 00fc 2A68     		ldr	r2, [r5]
+4803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2814              		.loc 1 4803 11 view .LVU935
+ARM GAS  /tmp/cc0wMqvE.s 			page 198
+
+
+ 2815 00fe 059B     		ldr	r3, [sp, #20]
+ 2816 0100 02F57872 		add	r2, r2, #992
+ 2817 0104 286B     		ldr	r0, [r5, #48]
+ 2818 0106 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2819              	.LVL222:
+4803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2820              		.loc 1 4803 10 view .LVU936
+ 2821 010a 0028     		cmp	r0, #0
+ 2822 010c C3D0     		beq	.L127
+4807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 2823              		.loc 1 4807 16 view .LVU937
+ 2824 010e 0120     		movs	r0, #1
+ 2825 0110 CBE7     		b	.L116
+ 2826              	.LVL223:
+ 2827              	.L142:
+4719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 2828              		.loc 1 4719 3 view .LVU938
+ 2829 0112 0120     		movs	r0, #1
+ 2830 0114 C9E7     		b	.L116
+ 2831              	.L121:
+4742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2832              		.loc 1 4742 7 is_stmt 1 view .LVU939
+4742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2833              		.loc 1 4742 17 is_stmt 0 view .LVU940
+ 2834 0116 6B6A     		ldr	r3, [r5, #36]
+4742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2835              		.loc 1 4742 52 view .LVU941
+ 2836 0118 1E4A     		ldr	r2, .L143
+ 2837              	.LVL224:
+4742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2838              		.loc 1 4742 52 view .LVU942
+ 2839 011a DA62     		str	r2, [r3, #44]
+4743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2840              		.loc 1 4743 7 is_stmt 1 view .LVU943
+4743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2841              		.loc 1 4743 17 is_stmt 0 view .LVU944
+ 2842 011c 6B6A     		ldr	r3, [r5, #36]
+4743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2843              		.loc 1 4743 56 view .LVU945
+ 2844 011e 1E4A     		ldr	r2, .L143+4
+ 2845 0120 1A63     		str	r2, [r3, #48]
+4746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2846              		.loc 1 4746 7 is_stmt 1 view .LVU946
+4746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2847              		.loc 1 4746 17 is_stmt 0 view .LVU947
+ 2848 0122 6B6A     		ldr	r3, [r5, #36]
+4746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2849              		.loc 1 4746 53 view .LVU948
+ 2850 0124 1D4A     		ldr	r2, .L143+8
+ 2851 0126 5A63     		str	r2, [r3, #52]
+4749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2852              		.loc 1 4749 7 is_stmt 1 view .LVU949
+4750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 2853              		.loc 1 4750 43 is_stmt 0 view .LVU950
+ 2854 0128 2A68     		ldr	r2, [r5]
+4749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2855              		.loc 1 4749 11 view .LVU951
+ARM GAS  /tmp/cc0wMqvE.s 			page 199
+
+
+ 2856 012a 059B     		ldr	r3, [sp, #20]
+ 2857 012c 02F57872 		add	r2, r2, #992
+ 2858 0130 686A     		ldr	r0, [r5, #36]
+ 2859 0132 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2860              	.LVL225:
+4749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2861              		.loc 1 4749 10 view .LVU952
+ 2862 0136 0028     		cmp	r0, #0
+ 2863 0138 ADD0     		beq	.L127
+4753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 2864              		.loc 1 4753 16 view .LVU953
+ 2865 013a 0120     		movs	r0, #1
+ 2866 013c B5E7     		b	.L116
+ 2867              	.LVL226:
+ 2868              	.L119:
+4778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2869              		.loc 1 4778 7 is_stmt 1 view .LVU954
+4778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2870              		.loc 1 4778 17 is_stmt 0 view .LVU955
+ 2871 013e EB6A     		ldr	r3, [r5, #44]
+4778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2872              		.loc 1 4778 52 view .LVU956
+ 2873 0140 144A     		ldr	r2, .L143
+ 2874              	.LVL227:
+4778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2875              		.loc 1 4778 52 view .LVU957
+ 2876 0142 DA62     		str	r2, [r3, #44]
+4779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2877              		.loc 1 4779 7 is_stmt 1 view .LVU958
+4779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2878              		.loc 1 4779 17 is_stmt 0 view .LVU959
+ 2879 0144 EB6A     		ldr	r3, [r5, #44]
+4779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2880              		.loc 1 4779 56 view .LVU960
+ 2881 0146 144A     		ldr	r2, .L143+4
+ 2882 0148 1A63     		str	r2, [r3, #48]
+4782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2883              		.loc 1 4782 7 is_stmt 1 view .LVU961
+4782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2884              		.loc 1 4782 17 is_stmt 0 view .LVU962
+ 2885 014a EB6A     		ldr	r3, [r5, #44]
+4782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2886              		.loc 1 4782 53 view .LVU963
+ 2887 014c 134A     		ldr	r2, .L143+8
+ 2888 014e 5A63     		str	r2, [r3, #52]
+4785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2889              		.loc 1 4785 7 is_stmt 1 view .LVU964
+4786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 2890              		.loc 1 4786 43 is_stmt 0 view .LVU965
+ 2891 0150 2A68     		ldr	r2, [r5]
+4785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2892              		.loc 1 4785 11 view .LVU966
+ 2893 0152 059B     		ldr	r3, [sp, #20]
+ 2894 0154 02F57872 		add	r2, r2, #992
+ 2895 0158 E86A     		ldr	r0, [r5, #44]
+ 2896 015a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2897              	.LVL228:
+ARM GAS  /tmp/cc0wMqvE.s 			page 200
+
+
+4785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2898              		.loc 1 4785 10 view .LVU967
+ 2899 015e 0028     		cmp	r0, #0
+ 2900 0160 99D0     		beq	.L127
+4789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 2901              		.loc 1 4789 16 view .LVU968
+ 2902 0162 0120     		movs	r0, #1
+ 2903 0164 A1E7     		b	.L116
+ 2904              	.LVL229:
+ 2905              	.L124:
+4814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 2906              		.loc 1 4814 7 is_stmt 1 view .LVU969
+4814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 2907              		.loc 1 4814 17 is_stmt 0 view .LVU970
+ 2908 0166 6B6B     		ldr	r3, [r5, #52]
+4814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 2909              		.loc 1 4814 60 view .LVU971
+ 2910 0168 114A     		ldr	r2, .L143+28
+ 2911              	.LVL230:
+4814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 2912              		.loc 1 4814 60 view .LVU972
+ 2913 016a DA62     		str	r2, [r3, #44]
+4815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2914              		.loc 1 4815 7 is_stmt 1 view .LVU973
+4815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2915              		.loc 1 4815 17 is_stmt 0 view .LVU974
+ 2916 016c 6B6B     		ldr	r3, [r5, #52]
+4815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2917              		.loc 1 4815 64 view .LVU975
+ 2918 016e 114A     		ldr	r2, .L143+32
+ 2919 0170 1A63     		str	r2, [r3, #48]
+4818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2920              		.loc 1 4818 7 is_stmt 1 view .LVU976
+4818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2921              		.loc 1 4818 17 is_stmt 0 view .LVU977
+ 2922 0172 6B6B     		ldr	r3, [r5, #52]
+4818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2923              		.loc 1 4818 61 view .LVU978
+ 2924 0174 094A     		ldr	r2, .L143+8
+ 2925 0176 5A63     		str	r2, [r3, #52]
+4821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2926              		.loc 1 4821 7 is_stmt 1 view .LVU979
+4822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 2927              		.loc 1 4822 43 is_stmt 0 view .LVU980
+ 2928 0178 2A68     		ldr	r2, [r5]
+4821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2929              		.loc 1 4821 11 view .LVU981
+ 2930 017a 059B     		ldr	r3, [sp, #20]
+ 2931 017c 02F57872 		add	r2, r2, #992
+ 2932 0180 686B     		ldr	r0, [r5, #52]
+ 2933 0182 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2934              	.LVL231:
+4821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2935              		.loc 1 4821 10 view .LVU982
+ 2936 0186 0028     		cmp	r0, #0
+ 2937 0188 85D0     		beq	.L127
+4825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ARM GAS  /tmp/cc0wMqvE.s 			page 201
+
+
+ 2938              		.loc 1 4825 16 view .LVU983
+ 2939 018a 0120     		movs	r0, #1
+ 2940 018c 8DE7     		b	.L116
+ 2941              	.L140:
+4735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 2942              		.loc 1 4735 16 view .LVU984
+ 2943 018e 0120     		movs	r0, #1
+ 2944 0190 8BE7     		b	.L116
+ 2945              	.L144:
+ 2946 0192 00BF     		.align	2
+ 2947              	.L143:
+ 2948 0194 00000000 		.word	TIM_DMADelayPulseCplt
+ 2949 0198 00000000 		.word	TIM_DMADelayPulseHalfCplt
+ 2950 019c 00000000 		.word	TIM_DMAError
+ 2951 01a0 00000000 		.word	TIM_DMAPeriodElapsedCplt
+ 2952 01a4 00000000 		.word	TIM_DMAPeriodElapsedHalfCplt
+ 2953 01a8 00000000 		.word	TIM_DMATriggerCplt
+ 2954 01ac 00000000 		.word	TIM_DMATriggerHalfCplt
+ 2955 01b0 00000000 		.word	TIMEx_DMACommutationCplt
+ 2956 01b4 00000000 		.word	TIMEx_DMACommutationHalfCplt
+ 2957              		.cfi_endproc
+ 2958              	.LFE393:
+ 2960              		.section	.text.HAL_TIM_DMABurst_WriteStart,"ax",%progbits
+ 2961              		.align	1
+ 2962              		.global	HAL_TIM_DMABurst_WriteStart
+ 2963              		.syntax unified
+ 2964              		.thumb
+ 2965              		.thumb_func
+ 2967              	HAL_TIM_DMABurst_WriteStart:
+ 2968              	.LVL232:
+ 2969              	.LFB392:
+4627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status;
+ 2970              		.loc 1 4627 1 is_stmt 1 view -0
+ 2971              		.cfi_startproc
+ 2972              		@ args = 4, pretend = 0, frame = 0
+ 2973              		@ frame_needed = 0, uses_anonymous_args = 0
+4627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status;
+ 2974              		.loc 1 4627 1 is_stmt 0 view .LVU986
+ 2975 0000 30B5     		push	{r4, r5, lr}
+ 2976              	.LCFI29:
+ 2977              		.cfi_def_cfa_offset 12
+ 2978              		.cfi_offset 4, -12
+ 2979              		.cfi_offset 5, -8
+ 2980              		.cfi_offset 14, -4
+ 2981 0002 83B0     		sub	sp, sp, #12
+ 2982              	.LCFI30:
+ 2983              		.cfi_def_cfa_offset 24
+ 2984 0004 069D     		ldr	r5, [sp, #24]
+4628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2985              		.loc 1 4628 3 is_stmt 1 view .LVU987
+4630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                             ((BurstLength) >> 8U) + 1U);
+ 2986              		.loc 1 4630 3 view .LVU988
+4631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2987              		.loc 1 4631 60 is_stmt 0 view .LVU989
+ 2988 0006 2C0A     		lsrs	r4, r5, #8
+4630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                             ((BurstLength) >> 8U) + 1U);
+ 2989              		.loc 1 4630 12 view .LVU990
+ARM GAS  /tmp/cc0wMqvE.s 			page 202
+
+
+ 2990 0008 0134     		adds	r4, r4, #1
+ 2991 000a 0194     		str	r4, [sp, #4]
+ 2992 000c 0095     		str	r5, [sp]
+ 2993 000e FFF7FEFF 		bl	HAL_TIM_DMABurst_MultiWriteStart
+ 2994              	.LVL233:
+4635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 2995              		.loc 1 4635 3 is_stmt 1 view .LVU991
+4636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 2996              		.loc 1 4636 1 is_stmt 0 view .LVU992
+ 2997 0012 03B0     		add	sp, sp, #12
+ 2998              	.LCFI31:
+ 2999              		.cfi_def_cfa_offset 12
+ 3000              		@ sp needed
+ 3001 0014 30BD     		pop	{r4, r5, pc}
+4636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3002              		.loc 1 4636 1 view .LVU993
+ 3003              		.cfi_endproc
+ 3004              	.LFE392:
+ 3006              		.section	.text.HAL_TIM_DMABurst_WriteStop,"ax",%progbits
+ 3007              		.align	1
+ 3008              		.global	HAL_TIM_DMABurst_WriteStop
+ 3009              		.syntax unified
+ 3010              		.thumb
+ 3011              		.thumb_func
+ 3013              	HAL_TIM_DMABurst_WriteStop:
+ 3014              	.LVL234:
+ 3015              	.LFB394:
+4871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3016              		.loc 1 4871 1 is_stmt 1 view -0
+ 3017              		.cfi_startproc
+ 3018              		@ args = 0, pretend = 0, frame = 0
+ 3019              		@ frame_needed = 0, uses_anonymous_args = 0
+4871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3020              		.loc 1 4871 1 is_stmt 0 view .LVU995
+ 3021 0000 38B5     		push	{r3, r4, r5, lr}
+ 3022              	.LCFI32:
+ 3023              		.cfi_def_cfa_offset 16
+ 3024              		.cfi_offset 3, -16
+ 3025              		.cfi_offset 4, -12
+ 3026              		.cfi_offset 5, -8
+ 3027              		.cfi_offset 14, -4
+ 3028 0002 0546     		mov	r5, r0
+ 3029 0004 0C46     		mov	r4, r1
+4872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3030              		.loc 1 4872 3 is_stmt 1 view .LVU996
+ 3031              	.LVL235:
+4875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3032              		.loc 1 4875 3 view .LVU997
+4878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3033              		.loc 1 4878 3 view .LVU998
+ 3034 0006 B1F5006F 		cmp	r1, #2048
+ 3035 000a 33D0     		beq	.L148
+ 3036 000c 1BD8     		bhi	.L149
+ 3037 000e B1F5007F 		cmp	r1, #512
+ 3038 0012 2BD0     		beq	.L150
+ 3039 0014 B1F5806F 		cmp	r1, #1024
+ 3040 0018 03D1     		bne	.L159
+ARM GAS  /tmp/cc0wMqvE.s 			page 203
+
+
+4892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3041              		.loc 1 4892 7 view .LVU999
+4892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3042              		.loc 1 4892 13 is_stmt 0 view .LVU1000
+ 3043 001a 806A     		ldr	r0, [r0, #40]
+ 3044              	.LVL236:
+4892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3045              		.loc 1 4892 13 view .LVU1001
+ 3046 001c FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3047              	.LVL237:
+4893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3048              		.loc 1 4893 7 is_stmt 1 view .LVU1002
+4920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3049              		.loc 1 4920 3 view .LVU1003
+ 3050 0020 05E0     		b	.L157
+ 3051              	.LVL238:
+ 3052              	.L159:
+4878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3053              		.loc 1 4878 3 is_stmt 0 view .LVU1004
+ 3054 0022 B1F5807F 		cmp	r1, #256
+ 3055 0026 0CD1     		bne	.L160
+4882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3056              		.loc 1 4882 7 is_stmt 1 view .LVU1005
+4882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3057              		.loc 1 4882 13 is_stmt 0 view .LVU1006
+ 3058 0028 006A     		ldr	r0, [r0, #32]
+ 3059              	.LVL239:
+4882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3060              		.loc 1 4882 13 view .LVU1007
+ 3061 002a FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3062              	.LVL240:
+4883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3063              		.loc 1 4883 7 is_stmt 1 view .LVU1008
+4920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3064              		.loc 1 4920 3 view .LVU1009
+ 3065              	.L157:
+4923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3066              		.loc 1 4923 5 view .LVU1010
+ 3067 002e 2A68     		ldr	r2, [r5]
+ 3068 0030 D368     		ldr	r3, [r2, #12]
+ 3069 0032 23EA0403 		bic	r3, r3, r4
+ 3070 0036 D360     		str	r3, [r2, #12]
+4926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 3071              		.loc 1 4926 5 view .LVU1011
+4926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 3072              		.loc 1 4926 25 is_stmt 0 view .LVU1012
+ 3073 0038 0123     		movs	r3, #1
+ 3074 003a 85F84830 		strb	r3, [r5, #72]
+ 3075 003e 0020     		movs	r0, #0
+ 3076              	.L153:
+ 3077              	.LVL241:
+4930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 3078              		.loc 1 4930 3 is_stmt 1 view .LVU1013
+4931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3079              		.loc 1 4931 1 is_stmt 0 view .LVU1014
+ 3080 0040 38BD     		pop	{r3, r4, r5, pc}
+ 3081              	.LVL242:
+ARM GAS  /tmp/cc0wMqvE.s 			page 204
+
+
+ 3082              	.L160:
+4878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3083              		.loc 1 4878 3 view .LVU1015
+ 3084 0042 0120     		movs	r0, #1
+ 3085              	.LVL243:
+4878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3086              		.loc 1 4878 3 view .LVU1016
+ 3087 0044 FCE7     		b	.L153
+ 3088              	.LVL244:
+ 3089              	.L149:
+4878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3090              		.loc 1 4878 3 view .LVU1017
+ 3091 0046 B1F5005F 		cmp	r1, #8192
+ 3092 004a 17D0     		beq	.L154
+ 3093 004c B1F5804F 		cmp	r1, #16384
+ 3094 0050 03D1     		bne	.L161
+4912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3095              		.loc 1 4912 7 is_stmt 1 view .LVU1018
+4912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3096              		.loc 1 4912 13 is_stmt 0 view .LVU1019
+ 3097 0052 806B     		ldr	r0, [r0, #56]
+ 3098              	.LVL245:
+4912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3099              		.loc 1 4912 13 view .LVU1020
+ 3100 0054 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3101              	.LVL246:
+4913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3102              		.loc 1 4913 7 is_stmt 1 view .LVU1021
+4920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3103              		.loc 1 4920 3 view .LVU1022
+ 3104 0058 E9E7     		b	.L157
+ 3105              	.LVL247:
+ 3106              	.L161:
+4878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3107              		.loc 1 4878 3 is_stmt 0 view .LVU1023
+ 3108 005a B1F5805F 		cmp	r1, #4096
+ 3109 005e 03D1     		bne	.L162
+4902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3110              		.loc 1 4902 7 is_stmt 1 view .LVU1024
+4902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3111              		.loc 1 4902 13 is_stmt 0 view .LVU1025
+ 3112 0060 006B     		ldr	r0, [r0, #48]
+ 3113              	.LVL248:
+4902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3114              		.loc 1 4902 13 view .LVU1026
+ 3115 0062 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3116              	.LVL249:
+4903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3117              		.loc 1 4903 7 is_stmt 1 view .LVU1027
+4920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3118              		.loc 1 4920 3 view .LVU1028
+ 3119 0066 E2E7     		b	.L157
+ 3120              	.LVL250:
+ 3121              	.L162:
+4878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3122              		.loc 1 4878 3 is_stmt 0 view .LVU1029
+ 3123 0068 0120     		movs	r0, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 205
+
+
+ 3124              	.LVL251:
+4878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3125              		.loc 1 4878 3 view .LVU1030
+ 3126 006a E9E7     		b	.L153
+ 3127              	.LVL252:
+ 3128              	.L150:
+4887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3129              		.loc 1 4887 7 is_stmt 1 view .LVU1031
+4887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3130              		.loc 1 4887 13 is_stmt 0 view .LVU1032
+ 3131 006c 406A     		ldr	r0, [r0, #36]
+ 3132              	.LVL253:
+4887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3133              		.loc 1 4887 13 view .LVU1033
+ 3134 006e FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3135              	.LVL254:
+4888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3136              		.loc 1 4888 7 is_stmt 1 view .LVU1034
+4920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3137              		.loc 1 4920 3 view .LVU1035
+ 3138 0072 DCE7     		b	.L157
+ 3139              	.LVL255:
+ 3140              	.L148:
+4897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3141              		.loc 1 4897 7 view .LVU1036
+4897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3142              		.loc 1 4897 13 is_stmt 0 view .LVU1037
+ 3143 0074 C06A     		ldr	r0, [r0, #44]
+ 3144              	.LVL256:
+4897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3145              		.loc 1 4897 13 view .LVU1038
+ 3146 0076 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3147              	.LVL257:
+4898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3148              		.loc 1 4898 7 is_stmt 1 view .LVU1039
+4920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3149              		.loc 1 4920 3 view .LVU1040
+ 3150 007a D8E7     		b	.L157
+ 3151              	.LVL258:
+ 3152              	.L154:
+4907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3153              		.loc 1 4907 7 view .LVU1041
+4907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3154              		.loc 1 4907 13 is_stmt 0 view .LVU1042
+ 3155 007c 406B     		ldr	r0, [r0, #52]
+ 3156              	.LVL259:
+4907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3157              		.loc 1 4907 13 view .LVU1043
+ 3158 007e FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3159              	.LVL260:
+4908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3160              		.loc 1 4908 7 is_stmt 1 view .LVU1044
+4920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3161              		.loc 1 4920 3 view .LVU1045
+ 3162 0082 D4E7     		b	.L157
+ 3163              		.cfi_endproc
+ 3164              	.LFE394:
+ARM GAS  /tmp/cc0wMqvE.s 			page 206
+
+
+ 3166              		.section	.text.HAL_TIM_DMABurst_MultiReadStart,"ax",%progbits
+ 3167              		.align	1
+ 3168              		.global	HAL_TIM_DMABurst_MultiReadStart
+ 3169              		.syntax unified
+ 3170              		.thumb
+ 3171              		.thumb_func
+ 3173              	HAL_TIM_DMABurst_MultiReadStart:
+ 3174              	.LVL261:
+ 3175              	.LFB396:
+5043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3176              		.loc 1 5043 1 view -0
+ 3177              		.cfi_startproc
+ 3178              		@ args = 8, pretend = 0, frame = 0
+ 3179              		@ frame_needed = 0, uses_anonymous_args = 0
+5043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3180              		.loc 1 5043 1 is_stmt 0 view .LVU1047
+ 3181 0000 70B5     		push	{r4, r5, r6, lr}
+ 3182              	.LCFI33:
+ 3183              		.cfi_def_cfa_offset 16
+ 3184              		.cfi_offset 4, -16
+ 3185              		.cfi_offset 5, -12
+ 3186              		.cfi_offset 6, -8
+ 3187              		.cfi_offset 14, -4
+ 3188 0002 0546     		mov	r5, r0
+5044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3189              		.loc 1 5044 3 is_stmt 1 view .LVU1048
+ 3190              	.LVL262:
+5047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ 3191              		.loc 1 5047 3 view .LVU1049
+5048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ 3192              		.loc 1 5048 3 view .LVU1050
+5049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ 3193              		.loc 1 5049 3 view .LVU1051
+5050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+ 3194              		.loc 1 5050 3 view .LVU1052
+5051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3195              		.loc 1 5051 3 view .LVU1053
+5053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3196              		.loc 1 5053 3 view .LVU1054
+5053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3197              		.loc 1 5053 11 is_stmt 0 view .LVU1055
+ 3198 0004 90F84800 		ldrb	r0, [r0, #72]	@ zero_extendqisi2
+ 3199              	.LVL263:
+5053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3200              		.loc 1 5053 11 view .LVU1056
+ 3201 0008 C0B2     		uxtb	r0, r0
+5053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3202              		.loc 1 5053 6 view .LVU1057
+ 3203 000a 0228     		cmp	r0, #2
+ 3204 000c 4DD0     		beq	.L164
+ 3205 000e 0E46     		mov	r6, r1
+ 3206 0010 1446     		mov	r4, r2
+ 3207 0012 1A46     		mov	r2, r3
+ 3208              	.LVL264:
+5057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3209              		.loc 1 5057 8 is_stmt 1 view .LVU1058
+5057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 207
+
+
+ 3210              		.loc 1 5057 16 is_stmt 0 view .LVU1059
+ 3211 0014 95F84800 		ldrb	r0, [r5, #72]	@ zero_extendqisi2
+ 3212 0018 C0B2     		uxtb	r0, r0
+5057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3213              		.loc 1 5057 11 view .LVU1060
+ 3214 001a 0128     		cmp	r0, #1
+ 3215 001c 1DD0     		beq	.L184
+ 3216              	.LVL265:
+ 3217              	.L165:
+5071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   switch (BurstRequestSrc)
+ 3218              		.loc 1 5071 3 is_stmt 1 view .LVU1061
+5072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3219              		.loc 1 5072 3 view .LVU1062
+ 3220 001e B4F5006F 		cmp	r4, #2048
+ 3221 0022 00F08C80 		beq	.L167
+ 3222 0026 43D8     		bhi	.L168
+ 3223 0028 B4F5007F 		cmp	r4, #512
+ 3224 002c 73D0     		beq	.L169
+ 3225 002e B4F5806F 		cmp	r4, #1024
+ 3226 0032 1BD1     		bne	.L185
+5113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3227              		.loc 1 5113 7 view .LVU1063
+5113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3228              		.loc 1 5113 17 is_stmt 0 view .LVU1064
+ 3229 0034 AB6A     		ldr	r3, [r5, #40]
+5113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3230              		.loc 1 5113 52 view .LVU1065
+ 3231 0036 5749     		ldr	r1, .L191
+ 3232              	.LVL266:
+5113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3233              		.loc 1 5113 52 view .LVU1066
+ 3234 0038 D962     		str	r1, [r3, #44]
+5114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3235              		.loc 1 5114 7 is_stmt 1 view .LVU1067
+5114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3236              		.loc 1 5114 17 is_stmt 0 view .LVU1068
+ 3237 003a AB6A     		ldr	r3, [r5, #40]
+5114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3238              		.loc 1 5114 56 view .LVU1069
+ 3239 003c 5649     		ldr	r1, .L191+4
+ 3240 003e 1963     		str	r1, [r3, #48]
+5117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3241              		.loc 1 5117 7 is_stmt 1 view .LVU1070
+5117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3242              		.loc 1 5117 17 is_stmt 0 view .LVU1071
+ 3243 0040 AB6A     		ldr	r3, [r5, #40]
+5117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3244              		.loc 1 5117 53 view .LVU1072
+ 3245 0042 5649     		ldr	r1, .L191+8
+ 3246 0044 5963     		str	r1, [r3, #52]
+5120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3247              		.loc 1 5120 7 is_stmt 1 view .LVU1073
+5120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3248              		.loc 1 5120 71 is_stmt 0 view .LVU1074
+ 3249 0046 2968     		ldr	r1, [r5]
+5120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3250              		.loc 1 5120 11 view .LVU1075
+ARM GAS  /tmp/cc0wMqvE.s 			page 208
+
+
+ 3251 0048 059B     		ldr	r3, [sp, #20]
+ 3252 004a 01F57871 		add	r1, r1, #992
+ 3253 004e A86A     		ldr	r0, [r5, #40]
+ 3254 0050 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3255              	.LVL267:
+5120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3256              		.loc 1 5120 10 view .LVU1076
+ 3257 0054 F8B1     		cbz	r0, .L175
+5124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 3258              		.loc 1 5124 16 view .LVU1077
+ 3259 0056 0120     		movs	r0, #1
+ 3260 0058 27E0     		b	.L164
+ 3261              	.LVL268:
+ 3262              	.L184:
+5059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 3263              		.loc 1 5059 5 is_stmt 1 view .LVU1078
+5059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 3264              		.loc 1 5059 8 is_stmt 0 view .LVU1079
+ 3265 005a 1BB1     		cbz	r3, .L186
+ 3266              	.L166:
+5065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3267              		.loc 1 5065 7 is_stmt 1 view .LVU1080
+5065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3268              		.loc 1 5065 27 is_stmt 0 view .LVU1081
+ 3269 005c 0223     		movs	r3, #2
+ 3270 005e 85F84830 		strb	r3, [r5, #72]
+ 3271 0062 DCE7     		b	.L165
+ 3272              	.L186:
+5059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 3273              		.loc 1 5059 31 discriminator 1 view .LVU1082
+ 3274 0064 049B     		ldr	r3, [sp, #16]
+ 3275 0066 002B     		cmp	r3, #0
+ 3276 0068 F8D0     		beq	.L166
+ 3277 006a 1EE0     		b	.L164
+ 3278              	.L185:
+5072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3279              		.loc 1 5072 3 view .LVU1083
+ 3280 006c B4F5807F 		cmp	r4, #256
+ 3281 0070 1CD1     		bne	.L187
+5077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 3282              		.loc 1 5077 7 is_stmt 1 view .LVU1084
+5077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 3283              		.loc 1 5077 17 is_stmt 0 view .LVU1085
+ 3284 0072 2B6A     		ldr	r3, [r5, #32]
+5077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 3285              		.loc 1 5077 55 view .LVU1086
+ 3286 0074 4A49     		ldr	r1, .L191+12
+ 3287              	.LVL269:
+5077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 3288              		.loc 1 5077 55 view .LVU1087
+ 3289 0076 D962     		str	r1, [r3, #44]
+5078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3290              		.loc 1 5078 7 is_stmt 1 view .LVU1088
+5078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3291              		.loc 1 5078 17 is_stmt 0 view .LVU1089
+ 3292 0078 2B6A     		ldr	r3, [r5, #32]
+5078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 209
+
+
+ 3293              		.loc 1 5078 59 view .LVU1090
+ 3294 007a 4A49     		ldr	r1, .L191+16
+ 3295 007c 1963     		str	r1, [r3, #48]
+5081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3296              		.loc 1 5081 7 is_stmt 1 view .LVU1091
+5081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3297              		.loc 1 5081 17 is_stmt 0 view .LVU1092
+ 3298 007e 2B6A     		ldr	r3, [r5, #32]
+5081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3299              		.loc 1 5081 56 view .LVU1093
+ 3300 0080 4649     		ldr	r1, .L191+8
+ 3301 0082 5963     		str	r1, [r3, #52]
+5084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3302              		.loc 1 5084 7 is_stmt 1 view .LVU1094
+5084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3303              		.loc 1 5084 74 is_stmt 0 view .LVU1095
+ 3304 0084 2968     		ldr	r1, [r5]
+5084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3305              		.loc 1 5084 11 view .LVU1096
+ 3306 0086 059B     		ldr	r3, [sp, #20]
+ 3307 0088 01F57871 		add	r1, r1, #992
+ 3308 008c 286A     		ldr	r0, [r5, #32]
+ 3309 008e FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3310              	.LVL270:
+5084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3311              		.loc 1 5084 10 view .LVU1097
+ 3312 0092 0028     		cmp	r0, #0
+ 3313 0094 7BD1     		bne	.L188
+ 3314              	.L175:
+ 3315              	.LVL271:
+5208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3316              		.loc 1 5208 5 is_stmt 1 view .LVU1098
+5208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3317              		.loc 1 5208 9 is_stmt 0 view .LVU1099
+ 3318 0096 2B68     		ldr	r3, [r5]
+5208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3319              		.loc 1 5208 45 view .LVU1100
+ 3320 0098 049A     		ldr	r2, [sp, #16]
+ 3321 009a 1643     		orrs	r6, r6, r2
+ 3322              	.LVL272:
+5208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3323              		.loc 1 5208 25 view .LVU1101
+ 3324 009c C3F8DC63 		str	r6, [r3, #988]
+5211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 3325              		.loc 1 5211 5 is_stmt 1 view .LVU1102
+ 3326 00a0 2A68     		ldr	r2, [r5]
+ 3327 00a2 D368     		ldr	r3, [r2, #12]
+ 3328 00a4 2343     		orrs	r3, r3, r4
+ 3329 00a6 D360     		str	r3, [r2, #12]
+ 3330 00a8 0020     		movs	r0, #0
+ 3331              	.LVL273:
+ 3332              	.L164:
+5216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3333              		.loc 1 5216 1 is_stmt 0 view .LVU1103
+ 3334 00aa 70BD     		pop	{r4, r5, r6, pc}
+ 3335              	.LVL274:
+ 3336              	.L187:
+ARM GAS  /tmp/cc0wMqvE.s 			page 210
+
+
+5072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3337              		.loc 1 5072 3 view .LVU1104
+ 3338 00ac 0120     		movs	r0, #1
+ 3339 00ae FCE7     		b	.L164
+ 3340              	.L168:
+5072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3341              		.loc 1 5072 3 view .LVU1105
+ 3342 00b0 B4F5005F 		cmp	r4, #8192
+ 3343 00b4 57D0     		beq	.L172
+ 3344 00b6 B4F5804F 		cmp	r4, #16384
+ 3345 00ba 13D1     		bne	.L189
+5185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 3346              		.loc 1 5185 7 is_stmt 1 view .LVU1106
+5185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 3347              		.loc 1 5185 17 is_stmt 0 view .LVU1107
+ 3348 00bc AB6B     		ldr	r3, [r5, #56]
+5185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 3349              		.loc 1 5185 56 view .LVU1108
+ 3350 00be 3A49     		ldr	r1, .L191+20
+ 3351              	.LVL275:
+5185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 3352              		.loc 1 5185 56 view .LVU1109
+ 3353 00c0 D962     		str	r1, [r3, #44]
+5186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3354              		.loc 1 5186 7 is_stmt 1 view .LVU1110
+5186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3355              		.loc 1 5186 17 is_stmt 0 view .LVU1111
+ 3356 00c2 AB6B     		ldr	r3, [r5, #56]
+5186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3357              		.loc 1 5186 60 view .LVU1112
+ 3358 00c4 3949     		ldr	r1, .L191+24
+ 3359 00c6 1963     		str	r1, [r3, #48]
+5189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3360              		.loc 1 5189 7 is_stmt 1 view .LVU1113
+5189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3361              		.loc 1 5189 17 is_stmt 0 view .LVU1114
+ 3362 00c8 AB6B     		ldr	r3, [r5, #56]
+5189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3363              		.loc 1 5189 57 view .LVU1115
+ 3364 00ca 3449     		ldr	r1, .L191+8
+ 3365 00cc 5963     		str	r1, [r3, #52]
+5192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3366              		.loc 1 5192 7 is_stmt 1 view .LVU1116
+5192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3367              		.loc 1 5192 75 is_stmt 0 view .LVU1117
+ 3368 00ce 2968     		ldr	r1, [r5]
+5192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3369              		.loc 1 5192 11 view .LVU1118
+ 3370 00d0 059B     		ldr	r3, [sp, #20]
+ 3371 00d2 01F57871 		add	r1, r1, #992
+ 3372 00d6 A86B     		ldr	r0, [r5, #56]
+ 3373 00d8 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3374              	.LVL276:
+5192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3375              		.loc 1 5192 10 view .LVU1119
+ 3376 00dc 0028     		cmp	r0, #0
+ 3377 00de DAD0     		beq	.L175
+ARM GAS  /tmp/cc0wMqvE.s 			page 211
+
+
+5196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 3378              		.loc 1 5196 16 view .LVU1120
+ 3379 00e0 0120     		movs	r0, #1
+ 3380 00e2 E2E7     		b	.L164
+ 3381              	.LVL277:
+ 3382              	.L189:
+5072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3383              		.loc 1 5072 3 view .LVU1121
+ 3384 00e4 B4F5805F 		cmp	r4, #4096
+ 3385 00e8 13D1     		bne	.L190
+5149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3386              		.loc 1 5149 7 is_stmt 1 view .LVU1122
+5149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3387              		.loc 1 5149 17 is_stmt 0 view .LVU1123
+ 3388 00ea 2B6B     		ldr	r3, [r5, #48]
+5149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3389              		.loc 1 5149 52 view .LVU1124
+ 3390 00ec 2949     		ldr	r1, .L191
+ 3391              	.LVL278:
+5149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3392              		.loc 1 5149 52 view .LVU1125
+ 3393 00ee D962     		str	r1, [r3, #44]
+5150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3394              		.loc 1 5150 7 is_stmt 1 view .LVU1126
+5150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3395              		.loc 1 5150 17 is_stmt 0 view .LVU1127
+ 3396 00f0 2B6B     		ldr	r3, [r5, #48]
+5150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3397              		.loc 1 5150 56 view .LVU1128
+ 3398 00f2 2949     		ldr	r1, .L191+4
+ 3399 00f4 1963     		str	r1, [r3, #48]
+5153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3400              		.loc 1 5153 7 is_stmt 1 view .LVU1129
+5153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3401              		.loc 1 5153 17 is_stmt 0 view .LVU1130
+ 3402 00f6 2B6B     		ldr	r3, [r5, #48]
+5153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3403              		.loc 1 5153 53 view .LVU1131
+ 3404 00f8 2849     		ldr	r1, .L191+8
+ 3405 00fa 5963     		str	r1, [r3, #52]
+5156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3406              		.loc 1 5156 7 is_stmt 1 view .LVU1132
+5156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3407              		.loc 1 5156 71 is_stmt 0 view .LVU1133
+ 3408 00fc 2968     		ldr	r1, [r5]
+5156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3409              		.loc 1 5156 11 view .LVU1134
+ 3410 00fe 059B     		ldr	r3, [sp, #20]
+ 3411 0100 01F57871 		add	r1, r1, #992
+ 3412 0104 286B     		ldr	r0, [r5, #48]
+ 3413 0106 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3414              	.LVL279:
+5156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3415              		.loc 1 5156 10 view .LVU1135
+ 3416 010a 0028     		cmp	r0, #0
+ 3417 010c C3D0     		beq	.L175
+5160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ARM GAS  /tmp/cc0wMqvE.s 			page 212
+
+
+ 3418              		.loc 1 5160 16 view .LVU1136
+ 3419 010e 0120     		movs	r0, #1
+ 3420 0110 CBE7     		b	.L164
+ 3421              	.LVL280:
+ 3422              	.L190:
+5072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3423              		.loc 1 5072 3 view .LVU1137
+ 3424 0112 0120     		movs	r0, #1
+ 3425 0114 C9E7     		b	.L164
+ 3426              	.L169:
+5095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3427              		.loc 1 5095 7 is_stmt 1 view .LVU1138
+5095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3428              		.loc 1 5095 17 is_stmt 0 view .LVU1139
+ 3429 0116 6B6A     		ldr	r3, [r5, #36]
+5095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3430              		.loc 1 5095 52 view .LVU1140
+ 3431 0118 1E49     		ldr	r1, .L191
+ 3432              	.LVL281:
+5095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3433              		.loc 1 5095 52 view .LVU1141
+ 3434 011a D962     		str	r1, [r3, #44]
+5096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3435              		.loc 1 5096 7 is_stmt 1 view .LVU1142
+5096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3436              		.loc 1 5096 17 is_stmt 0 view .LVU1143
+ 3437 011c 6B6A     		ldr	r3, [r5, #36]
+5096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3438              		.loc 1 5096 56 view .LVU1144
+ 3439 011e 1E49     		ldr	r1, .L191+4
+ 3440 0120 1963     		str	r1, [r3, #48]
+5099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3441              		.loc 1 5099 7 is_stmt 1 view .LVU1145
+5099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3442              		.loc 1 5099 17 is_stmt 0 view .LVU1146
+ 3443 0122 6B6A     		ldr	r3, [r5, #36]
+5099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3444              		.loc 1 5099 53 view .LVU1147
+ 3445 0124 1D49     		ldr	r1, .L191+8
+ 3446 0126 5963     		str	r1, [r3, #52]
+5102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3447              		.loc 1 5102 7 is_stmt 1 view .LVU1148
+5102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3448              		.loc 1 5102 71 is_stmt 0 view .LVU1149
+ 3449 0128 2968     		ldr	r1, [r5]
+5102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3450              		.loc 1 5102 11 view .LVU1150
+ 3451 012a 059B     		ldr	r3, [sp, #20]
+ 3452 012c 01F57871 		add	r1, r1, #992
+ 3453 0130 686A     		ldr	r0, [r5, #36]
+ 3454 0132 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3455              	.LVL282:
+5102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3456              		.loc 1 5102 10 view .LVU1151
+ 3457 0136 0028     		cmp	r0, #0
+ 3458 0138 ADD0     		beq	.L175
+5106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ARM GAS  /tmp/cc0wMqvE.s 			page 213
+
+
+ 3459              		.loc 1 5106 16 view .LVU1152
+ 3460 013a 0120     		movs	r0, #1
+ 3461 013c B5E7     		b	.L164
+ 3462              	.LVL283:
+ 3463              	.L167:
+5131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3464              		.loc 1 5131 7 is_stmt 1 view .LVU1153
+5131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3465              		.loc 1 5131 17 is_stmt 0 view .LVU1154
+ 3466 013e EB6A     		ldr	r3, [r5, #44]
+5131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3467              		.loc 1 5131 52 view .LVU1155
+ 3468 0140 1449     		ldr	r1, .L191
+ 3469              	.LVL284:
+5131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3470              		.loc 1 5131 52 view .LVU1156
+ 3471 0142 D962     		str	r1, [r3, #44]
+5132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3472              		.loc 1 5132 7 is_stmt 1 view .LVU1157
+5132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3473              		.loc 1 5132 17 is_stmt 0 view .LVU1158
+ 3474 0144 EB6A     		ldr	r3, [r5, #44]
+5132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3475              		.loc 1 5132 56 view .LVU1159
+ 3476 0146 1449     		ldr	r1, .L191+4
+ 3477 0148 1963     		str	r1, [r3, #48]
+5135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3478              		.loc 1 5135 7 is_stmt 1 view .LVU1160
+5135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3479              		.loc 1 5135 17 is_stmt 0 view .LVU1161
+ 3480 014a EB6A     		ldr	r3, [r5, #44]
+5135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3481              		.loc 1 5135 53 view .LVU1162
+ 3482 014c 1349     		ldr	r1, .L191+8
+ 3483 014e 5963     		str	r1, [r3, #52]
+5138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3484              		.loc 1 5138 7 is_stmt 1 view .LVU1163
+5138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3485              		.loc 1 5138 71 is_stmt 0 view .LVU1164
+ 3486 0150 2968     		ldr	r1, [r5]
+5138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3487              		.loc 1 5138 11 view .LVU1165
+ 3488 0152 059B     		ldr	r3, [sp, #20]
+ 3489 0154 01F57871 		add	r1, r1, #992
+ 3490 0158 E86A     		ldr	r0, [r5, #44]
+ 3491 015a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3492              	.LVL285:
+5138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3493              		.loc 1 5138 10 view .LVU1166
+ 3494 015e 0028     		cmp	r0, #0
+ 3495 0160 99D0     		beq	.L175
+5142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 3496              		.loc 1 5142 16 view .LVU1167
+ 3497 0162 0120     		movs	r0, #1
+ 3498 0164 A1E7     		b	.L164
+ 3499              	.LVL286:
+ 3500              	.L172:
+ARM GAS  /tmp/cc0wMqvE.s 			page 214
+
+
+5167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 3501              		.loc 1 5167 7 is_stmt 1 view .LVU1168
+5167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 3502              		.loc 1 5167 17 is_stmt 0 view .LVU1169
+ 3503 0166 6B6B     		ldr	r3, [r5, #52]
+5167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 3504              		.loc 1 5167 60 view .LVU1170
+ 3505 0168 1149     		ldr	r1, .L191+28
+ 3506              	.LVL287:
+5167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 3507              		.loc 1 5167 60 view .LVU1171
+ 3508 016a D962     		str	r1, [r3, #44]
+5168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3509              		.loc 1 5168 7 is_stmt 1 view .LVU1172
+5168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3510              		.loc 1 5168 17 is_stmt 0 view .LVU1173
+ 3511 016c 6B6B     		ldr	r3, [r5, #52]
+5168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3512              		.loc 1 5168 64 view .LVU1174
+ 3513 016e 1149     		ldr	r1, .L191+32
+ 3514 0170 1963     		str	r1, [r3, #48]
+5171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3515              		.loc 1 5171 7 is_stmt 1 view .LVU1175
+5171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3516              		.loc 1 5171 17 is_stmt 0 view .LVU1176
+ 3517 0172 6B6B     		ldr	r3, [r5, #52]
+5171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3518              		.loc 1 5171 61 view .LVU1177
+ 3519 0174 0949     		ldr	r1, .L191+8
+ 3520 0176 5963     		str	r1, [r3, #52]
+5174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3521              		.loc 1 5174 7 is_stmt 1 view .LVU1178
+5174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3522              		.loc 1 5174 79 is_stmt 0 view .LVU1179
+ 3523 0178 2968     		ldr	r1, [r5]
+5174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3524              		.loc 1 5174 11 view .LVU1180
+ 3525 017a 059B     		ldr	r3, [sp, #20]
+ 3526 017c 01F57871 		add	r1, r1, #992
+ 3527 0180 686B     		ldr	r0, [r5, #52]
+ 3528 0182 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3529              	.LVL288:
+5174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3530              		.loc 1 5174 10 view .LVU1181
+ 3531 0186 0028     		cmp	r0, #0
+ 3532 0188 85D0     		beq	.L175
+5178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 3533              		.loc 1 5178 16 view .LVU1182
+ 3534 018a 0120     		movs	r0, #1
+ 3535 018c 8DE7     		b	.L164
+ 3536              	.L188:
+5088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 3537              		.loc 1 5088 16 view .LVU1183
+ 3538 018e 0120     		movs	r0, #1
+ 3539 0190 8BE7     		b	.L164
+ 3540              	.L192:
+ 3541 0192 00BF     		.align	2
+ARM GAS  /tmp/cc0wMqvE.s 			page 215
+
+
+ 3542              	.L191:
+ 3543 0194 00000000 		.word	TIM_DMACaptureCplt
+ 3544 0198 00000000 		.word	TIM_DMACaptureHalfCplt
+ 3545 019c 00000000 		.word	TIM_DMAError
+ 3546 01a0 00000000 		.word	TIM_DMAPeriodElapsedCplt
+ 3547 01a4 00000000 		.word	TIM_DMAPeriodElapsedHalfCplt
+ 3548 01a8 00000000 		.word	TIM_DMATriggerCplt
+ 3549 01ac 00000000 		.word	TIM_DMATriggerHalfCplt
+ 3550 01b0 00000000 		.word	TIMEx_DMACommutationCplt
+ 3551 01b4 00000000 		.word	TIMEx_DMACommutationHalfCplt
+ 3552              		.cfi_endproc
+ 3553              	.LFE396:
+ 3555              		.section	.text.HAL_TIM_DMABurst_ReadStart,"ax",%progbits
+ 3556              		.align	1
+ 3557              		.global	HAL_TIM_DMABurst_ReadStart
+ 3558              		.syntax unified
+ 3559              		.thumb
+ 3560              		.thumb_func
+ 3562              	HAL_TIM_DMABurst_ReadStart:
+ 3563              	.LVL289:
+ 3564              	.LFB395:
+4982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status;
+ 3565              		.loc 1 4982 1 is_stmt 1 view -0
+ 3566              		.cfi_startproc
+ 3567              		@ args = 4, pretend = 0, frame = 0
+ 3568              		@ frame_needed = 0, uses_anonymous_args = 0
+4982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status;
+ 3569              		.loc 1 4982 1 is_stmt 0 view .LVU1185
+ 3570 0000 30B5     		push	{r4, r5, lr}
+ 3571              	.LCFI34:
+ 3572              		.cfi_def_cfa_offset 12
+ 3573              		.cfi_offset 4, -12
+ 3574              		.cfi_offset 5, -8
+ 3575              		.cfi_offset 14, -4
+ 3576 0002 83B0     		sub	sp, sp, #12
+ 3577              	.LCFI35:
+ 3578              		.cfi_def_cfa_offset 24
+ 3579 0004 069D     		ldr	r5, [sp, #24]
+4983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3580              		.loc 1 4983 3 is_stmt 1 view .LVU1186
+4985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                            ((BurstLength) >> 8U) + 1U);
+ 3581              		.loc 1 4985 3 view .LVU1187
+4986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3582              		.loc 1 4986 59 is_stmt 0 view .LVU1188
+ 3583 0006 2C0A     		lsrs	r4, r5, #8
+4985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                            ((BurstLength) >> 8U) + 1U);
+ 3584              		.loc 1 4985 12 view .LVU1189
+ 3585 0008 0134     		adds	r4, r4, #1
+ 3586 000a 0194     		str	r4, [sp, #4]
+ 3587 000c 0095     		str	r5, [sp]
+ 3588 000e FFF7FEFF 		bl	HAL_TIM_DMABurst_MultiReadStart
+ 3589              	.LVL290:
+4989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 3590              		.loc 1 4989 3 is_stmt 1 view .LVU1190
+4990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3591              		.loc 1 4990 1 is_stmt 0 view .LVU1191
+ 3592 0012 03B0     		add	sp, sp, #12
+ARM GAS  /tmp/cc0wMqvE.s 			page 216
+
+
+ 3593              	.LCFI36:
+ 3594              		.cfi_def_cfa_offset 12
+ 3595              		@ sp needed
+ 3596 0014 30BD     		pop	{r4, r5, pc}
+4990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3597              		.loc 1 4990 1 view .LVU1192
+ 3598              		.cfi_endproc
+ 3599              	.LFE395:
+ 3601              		.section	.text.HAL_TIM_DMABurst_ReadStop,"ax",%progbits
+ 3602              		.align	1
+ 3603              		.global	HAL_TIM_DMABurst_ReadStop
+ 3604              		.syntax unified
+ 3605              		.thumb
+ 3606              		.thumb_func
+ 3608              	HAL_TIM_DMABurst_ReadStop:
+ 3609              	.LVL291:
+ 3610              	.LFB397:
+5225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3611              		.loc 1 5225 1 is_stmt 1 view -0
+ 3612              		.cfi_startproc
+ 3613              		@ args = 0, pretend = 0, frame = 0
+ 3614              		@ frame_needed = 0, uses_anonymous_args = 0
+5225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3615              		.loc 1 5225 1 is_stmt 0 view .LVU1194
+ 3616 0000 38B5     		push	{r3, r4, r5, lr}
+ 3617              	.LCFI37:
+ 3618              		.cfi_def_cfa_offset 16
+ 3619              		.cfi_offset 3, -16
+ 3620              		.cfi_offset 4, -12
+ 3621              		.cfi_offset 5, -8
+ 3622              		.cfi_offset 14, -4
+ 3623 0002 0546     		mov	r5, r0
+ 3624 0004 0C46     		mov	r4, r1
+5226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3625              		.loc 1 5226 3 is_stmt 1 view .LVU1195
+ 3626              	.LVL292:
+5229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3627              		.loc 1 5229 3 view .LVU1196
+5232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3628              		.loc 1 5232 3 view .LVU1197
+ 3629 0006 B1F5006F 		cmp	r1, #2048
+ 3630 000a 33D0     		beq	.L196
+ 3631 000c 1BD8     		bhi	.L197
+ 3632 000e B1F5007F 		cmp	r1, #512
+ 3633 0012 2BD0     		beq	.L198
+ 3634 0014 B1F5806F 		cmp	r1, #1024
+ 3635 0018 03D1     		bne	.L207
+5246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3636              		.loc 1 5246 7 view .LVU1198
+5246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3637              		.loc 1 5246 13 is_stmt 0 view .LVU1199
+ 3638 001a 806A     		ldr	r0, [r0, #40]
+ 3639              	.LVL293:
+5246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3640              		.loc 1 5246 13 view .LVU1200
+ 3641 001c FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3642              	.LVL294:
+ARM GAS  /tmp/cc0wMqvE.s 			page 217
+
+
+5247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3643              		.loc 1 5247 7 is_stmt 1 view .LVU1201
+5274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3644              		.loc 1 5274 3 view .LVU1202
+ 3645 0020 05E0     		b	.L205
+ 3646              	.LVL295:
+ 3647              	.L207:
+5232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3648              		.loc 1 5232 3 is_stmt 0 view .LVU1203
+ 3649 0022 B1F5807F 		cmp	r1, #256
+ 3650 0026 0CD1     		bne	.L208
+5236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3651              		.loc 1 5236 7 is_stmt 1 view .LVU1204
+5236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3652              		.loc 1 5236 13 is_stmt 0 view .LVU1205
+ 3653 0028 006A     		ldr	r0, [r0, #32]
+ 3654              	.LVL296:
+5236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3655              		.loc 1 5236 13 view .LVU1206
+ 3656 002a FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3657              	.LVL297:
+5237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3658              		.loc 1 5237 7 is_stmt 1 view .LVU1207
+5274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3659              		.loc 1 5274 3 view .LVU1208
+ 3660              	.L205:
+5277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3661              		.loc 1 5277 5 view .LVU1209
+ 3662 002e 2A68     		ldr	r2, [r5]
+ 3663 0030 D368     		ldr	r3, [r2, #12]
+ 3664 0032 23EA0403 		bic	r3, r3, r4
+ 3665 0036 D360     		str	r3, [r2, #12]
+5280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 3666              		.loc 1 5280 5 view .LVU1210
+5280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 3667              		.loc 1 5280 25 is_stmt 0 view .LVU1211
+ 3668 0038 0123     		movs	r3, #1
+ 3669 003a 85F84830 		strb	r3, [r5, #72]
+ 3670 003e 0020     		movs	r0, #0
+ 3671              	.L201:
+ 3672              	.LVL298:
+5284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 3673              		.loc 1 5284 3 is_stmt 1 view .LVU1212
+5285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3674              		.loc 1 5285 1 is_stmt 0 view .LVU1213
+ 3675 0040 38BD     		pop	{r3, r4, r5, pc}
+ 3676              	.LVL299:
+ 3677              	.L208:
+5232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3678              		.loc 1 5232 3 view .LVU1214
+ 3679 0042 0120     		movs	r0, #1
+ 3680              	.LVL300:
+5232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3681              		.loc 1 5232 3 view .LVU1215
+ 3682 0044 FCE7     		b	.L201
+ 3683              	.LVL301:
+ 3684              	.L197:
+ARM GAS  /tmp/cc0wMqvE.s 			page 218
+
+
+5232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3685              		.loc 1 5232 3 view .LVU1216
+ 3686 0046 B1F5005F 		cmp	r1, #8192
+ 3687 004a 17D0     		beq	.L202
+ 3688 004c B1F5804F 		cmp	r1, #16384
+ 3689 0050 03D1     		bne	.L209
+5266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3690              		.loc 1 5266 7 is_stmt 1 view .LVU1217
+5266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3691              		.loc 1 5266 13 is_stmt 0 view .LVU1218
+ 3692 0052 806B     		ldr	r0, [r0, #56]
+ 3693              	.LVL302:
+5266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3694              		.loc 1 5266 13 view .LVU1219
+ 3695 0054 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3696              	.LVL303:
+5267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3697              		.loc 1 5267 7 is_stmt 1 view .LVU1220
+5274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3698              		.loc 1 5274 3 view .LVU1221
+ 3699 0058 E9E7     		b	.L205
+ 3700              	.LVL304:
+ 3701              	.L209:
+5232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3702              		.loc 1 5232 3 is_stmt 0 view .LVU1222
+ 3703 005a B1F5805F 		cmp	r1, #4096
+ 3704 005e 03D1     		bne	.L210
+5256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3705              		.loc 1 5256 7 is_stmt 1 view .LVU1223
+5256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3706              		.loc 1 5256 13 is_stmt 0 view .LVU1224
+ 3707 0060 006B     		ldr	r0, [r0, #48]
+ 3708              	.LVL305:
+5256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3709              		.loc 1 5256 13 view .LVU1225
+ 3710 0062 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3711              	.LVL306:
+5257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3712              		.loc 1 5257 7 is_stmt 1 view .LVU1226
+5274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3713              		.loc 1 5274 3 view .LVU1227
+ 3714 0066 E2E7     		b	.L205
+ 3715              	.LVL307:
+ 3716              	.L210:
+5232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3717              		.loc 1 5232 3 is_stmt 0 view .LVU1228
+ 3718 0068 0120     		movs	r0, #1
+ 3719              	.LVL308:
+5232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3720              		.loc 1 5232 3 view .LVU1229
+ 3721 006a E9E7     		b	.L201
+ 3722              	.LVL309:
+ 3723              	.L198:
+5241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3724              		.loc 1 5241 7 is_stmt 1 view .LVU1230
+5241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3725              		.loc 1 5241 13 is_stmt 0 view .LVU1231
+ARM GAS  /tmp/cc0wMqvE.s 			page 219
+
+
+ 3726 006c 406A     		ldr	r0, [r0, #36]
+ 3727              	.LVL310:
+5241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3728              		.loc 1 5241 13 view .LVU1232
+ 3729 006e FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3730              	.LVL311:
+5242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3731              		.loc 1 5242 7 is_stmt 1 view .LVU1233
+5274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3732              		.loc 1 5274 3 view .LVU1234
+ 3733 0072 DCE7     		b	.L205
+ 3734              	.LVL312:
+ 3735              	.L196:
+5251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3736              		.loc 1 5251 7 view .LVU1235
+5251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3737              		.loc 1 5251 13 is_stmt 0 view .LVU1236
+ 3738 0074 C06A     		ldr	r0, [r0, #44]
+ 3739              	.LVL313:
+5251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3740              		.loc 1 5251 13 view .LVU1237
+ 3741 0076 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3742              	.LVL314:
+5252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3743              		.loc 1 5252 7 is_stmt 1 view .LVU1238
+5274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3744              		.loc 1 5274 3 view .LVU1239
+ 3745 007a D8E7     		b	.L205
+ 3746              	.LVL315:
+ 3747              	.L202:
+5261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3748              		.loc 1 5261 7 view .LVU1240
+5261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3749              		.loc 1 5261 13 is_stmt 0 view .LVU1241
+ 3750 007c 406B     		ldr	r0, [r0, #52]
+ 3751              	.LVL316:
+5261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 3752              		.loc 1 5261 13 view .LVU1242
+ 3753 007e FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3754              	.LVL317:
+5262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3755              		.loc 1 5262 7 is_stmt 1 view .LVU1243
+5274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3756              		.loc 1 5274 3 view .LVU1244
+ 3757 0082 D4E7     		b	.L205
+ 3758              		.cfi_endproc
+ 3759              	.LFE397:
+ 3761              		.section	.text.HAL_TIM_GenerateEvent,"ax",%progbits
+ 3762              		.align	1
+ 3763              		.global	HAL_TIM_GenerateEvent
+ 3764              		.syntax unified
+ 3765              		.thumb
+ 3766              		.thumb_func
+ 3768              	HAL_TIM_GenerateEvent:
+ 3769              	.LVL318:
+ 3770              	.LFB398:
+5309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ARM GAS  /tmp/cc0wMqvE.s 			page 220
+
+
+ 3771              		.loc 1 5309 1 view -0
+ 3772              		.cfi_startproc
+ 3773              		@ args = 0, pretend = 0, frame = 0
+ 3774              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3775              		@ link register save eliminated.
+5311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+ 3776              		.loc 1 5311 3 view .LVU1246
+5312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3777              		.loc 1 5312 3 view .LVU1247
+5315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3778              		.loc 1 5315 3 view .LVU1248
+5315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3779              		.loc 1 5315 3 view .LVU1249
+ 3780 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 3781 0004 012B     		cmp	r3, #1
+ 3782 0006 0ED0     		beq	.L213
+5315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3783              		.loc 1 5315 3 discriminator 2 view .LVU1250
+ 3784 0008 0123     		movs	r3, #1
+ 3785 000a 80F83C30 		strb	r3, [r0, #60]
+5315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3786              		.loc 1 5315 3 discriminator 2 view .LVU1251
+5318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3787              		.loc 1 5318 3 discriminator 2 view .LVU1252
+5318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3788              		.loc 1 5318 15 is_stmt 0 discriminator 2 view .LVU1253
+ 3789 000e 0222     		movs	r2, #2
+ 3790 0010 80F83D20 		strb	r2, [r0, #61]
+5321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3791              		.loc 1 5321 3 is_stmt 1 discriminator 2 view .LVU1254
+5321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3792              		.loc 1 5321 7 is_stmt 0 discriminator 2 view .LVU1255
+ 3793 0014 0268     		ldr	r2, [r0]
+5321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3794              		.loc 1 5321 23 discriminator 2 view .LVU1256
+ 3795 0016 5161     		str	r1, [r2, #20]
+5324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3796              		.loc 1 5324 3 is_stmt 1 discriminator 2 view .LVU1257
+5324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3797              		.loc 1 5324 15 is_stmt 0 discriminator 2 view .LVU1258
+ 3798 0018 80F83D30 		strb	r3, [r0, #61]
+5326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3799              		.loc 1 5326 3 is_stmt 1 discriminator 2 view .LVU1259
+5326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3800              		.loc 1 5326 3 discriminator 2 view .LVU1260
+ 3801 001c 0023     		movs	r3, #0
+ 3802 001e 80F83C30 		strb	r3, [r0, #60]
+5326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3803              		.loc 1 5326 3 discriminator 2 view .LVU1261
+5329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 3804              		.loc 1 5329 3 discriminator 2 view .LVU1262
+5329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 3805              		.loc 1 5329 10 is_stmt 0 discriminator 2 view .LVU1263
+ 3806 0022 1846     		mov	r0, r3
+ 3807              	.LVL319:
+5329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 3808              		.loc 1 5329 10 discriminator 2 view .LVU1264
+ARM GAS  /tmp/cc0wMqvE.s 			page 221
+
+
+ 3809 0024 7047     		bx	lr
+ 3810              	.LVL320:
+ 3811              	.L213:
+5315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3812              		.loc 1 5315 3 view .LVU1265
+ 3813 0026 0220     		movs	r0, #2
+ 3814              	.LVL321:
+5330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3815              		.loc 1 5330 1 view .LVU1266
+ 3816 0028 7047     		bx	lr
+ 3817              		.cfi_endproc
+ 3818              	.LFE398:
+ 3820              		.section	.text.HAL_TIM_ConfigTI1Input,"ax",%progbits
+ 3821              		.align	1
+ 3822              		.global	HAL_TIM_ConfigTI1Input
+ 3823              		.syntax unified
+ 3824              		.thumb
+ 3825              		.thumb_func
+ 3827              	HAL_TIM_ConfigTI1Input:
+ 3828              	.LVL322:
+ 3829              	.LFB401:
+5718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpcr2;
+ 3830              		.loc 1 5718 1 is_stmt 1 view -0
+ 3831              		.cfi_startproc
+ 3832              		@ args = 0, pretend = 0, frame = 0
+ 3833              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3834              		@ link register save eliminated.
+5719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3835              		.loc 1 5719 3 view .LVU1268
+5722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+ 3836              		.loc 1 5722 3 view .LVU1269
+5723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3837              		.loc 1 5723 3 view .LVU1270
+5726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3838              		.loc 1 5726 3 view .LVU1271
+5726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3839              		.loc 1 5726 16 is_stmt 0 view .LVU1272
+ 3840 0000 0268     		ldr	r2, [r0]
+5726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3841              		.loc 1 5726 10 view .LVU1273
+ 3842 0002 5368     		ldr	r3, [r2, #4]
+ 3843              	.LVL323:
+5729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3844              		.loc 1 5729 3 is_stmt 1 view .LVU1274
+5729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3845              		.loc 1 5729 10 is_stmt 0 view .LVU1275
+ 3846 0004 23F08003 		bic	r3, r3, #128
+ 3847              	.LVL324:
+5732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3848              		.loc 1 5732 3 is_stmt 1 view .LVU1276
+5732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3849              		.loc 1 5732 10 is_stmt 0 view .LVU1277
+ 3850 0008 0B43     		orrs	r3, r3, r1
+ 3851              	.LVL325:
+5735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3852              		.loc 1 5735 3 is_stmt 1 view .LVU1278
+5735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 222
+
+
+ 3853              		.loc 1 5735 23 is_stmt 0 view .LVU1279
+ 3854 000a 5360     		str	r3, [r2, #4]
+5737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 3855              		.loc 1 5737 3 is_stmt 1 view .LVU1280
+5738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3856              		.loc 1 5738 1 is_stmt 0 view .LVU1281
+ 3857 000c 0020     		movs	r0, #0
+ 3858              	.LVL326:
+5738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3859              		.loc 1 5738 1 view .LVU1282
+ 3860 000e 7047     		bx	lr
+ 3861              		.cfi_endproc
+ 3862              	.LFE401:
+ 3864              		.section	.text.HAL_TIM_ReadCapturedValue,"ax",%progbits
+ 3865              		.align	1
+ 3866              		.global	HAL_TIM_ReadCapturedValue
+ 3867              		.syntax unified
+ 3868              		.thumb
+ 3869              		.thumb_func
+ 3871              	HAL_TIM_ReadCapturedValue:
+ 3872              	.LVL327:
+ 3873              	.LFB404:
+5833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpreg = 0U;
+ 3874              		.loc 1 5833 1 is_stmt 1 view -0
+ 3875              		.cfi_startproc
+ 3876              		@ args = 0, pretend = 0, frame = 0
+ 3877              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3878              		@ link register save eliminated.
+5834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3879              		.loc 1 5834 3 view .LVU1284
+5836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3880              		.loc 1 5836 3 view .LVU1285
+ 3881 0000 0C29     		cmp	r1, #12
+ 3882 0002 14D8     		bhi	.L222
+ 3883 0004 DFE801F0 		tbb	[pc, r1]
+ 3884              	.L218:
+ 3885 0008 07       		.byte	(.L221-.L218)/2
+ 3886 0009 13       		.byte	(.L222-.L218)/2
+ 3887 000a 13       		.byte	(.L222-.L218)/2
+ 3888 000b 13       		.byte	(.L222-.L218)/2
+ 3889 000c 0A       		.byte	(.L220-.L218)/2
+ 3890 000d 13       		.byte	(.L222-.L218)/2
+ 3891 000e 13       		.byte	(.L222-.L218)/2
+ 3892 000f 13       		.byte	(.L222-.L218)/2
+ 3893 0010 0D       		.byte	(.L219-.L218)/2
+ 3894 0011 13       		.byte	(.L222-.L218)/2
+ 3895 0012 13       		.byte	(.L222-.L218)/2
+ 3896 0013 13       		.byte	(.L222-.L218)/2
+ 3897 0014 10       		.byte	(.L217-.L218)/2
+ 3898 0015 00       		.p2align 1
+ 3899              	.L221:
+5841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3900              		.loc 1 5841 7 view .LVU1286
+5844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3901              		.loc 1 5844 7 view .LVU1287
+5844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3902              		.loc 1 5844 21 is_stmt 0 view .LVU1288
+ARM GAS  /tmp/cc0wMqvE.s 			page 223
+
+
+ 3903 0016 0368     		ldr	r3, [r0]
+5844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3904              		.loc 1 5844 14 view .LVU1289
+ 3905 0018 586B     		ldr	r0, [r3, #52]
+ 3906              	.LVL328:
+5846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3907              		.loc 1 5846 7 is_stmt 1 view .LVU1290
+ 3908 001a 7047     		bx	lr
+ 3909              	.LVL329:
+ 3910              	.L220:
+5851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3911              		.loc 1 5851 7 view .LVU1291
+5854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3912              		.loc 1 5854 7 view .LVU1292
+5854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3913              		.loc 1 5854 22 is_stmt 0 view .LVU1293
+ 3914 001c 0368     		ldr	r3, [r0]
+5854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3915              		.loc 1 5854 14 view .LVU1294
+ 3916 001e 986B     		ldr	r0, [r3, #56]
+ 3917              	.LVL330:
+5856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3918              		.loc 1 5856 7 is_stmt 1 view .LVU1295
+ 3919 0020 7047     		bx	lr
+ 3920              	.LVL331:
+ 3921              	.L219:
+5862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3922              		.loc 1 5862 7 view .LVU1296
+5865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3923              		.loc 1 5865 7 view .LVU1297
+5865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3924              		.loc 1 5865 22 is_stmt 0 view .LVU1298
+ 3925 0022 0368     		ldr	r3, [r0]
+5865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3926              		.loc 1 5865 14 view .LVU1299
+ 3927 0024 D86B     		ldr	r0, [r3, #60]
+ 3928              	.LVL332:
+5867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3929              		.loc 1 5867 7 is_stmt 1 view .LVU1300
+ 3930 0026 7047     		bx	lr
+ 3931              	.LVL333:
+ 3932              	.L217:
+5873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3933              		.loc 1 5873 7 view .LVU1301
+5876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3934              		.loc 1 5876 7 view .LVU1302
+5876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3935              		.loc 1 5876 22 is_stmt 0 view .LVU1303
+ 3936 0028 0368     		ldr	r3, [r0]
+5876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3937              		.loc 1 5876 14 view .LVU1304
+ 3938 002a 186C     		ldr	r0, [r3, #64]
+ 3939              	.LVL334:
+5878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 3940              		.loc 1 5878 7 is_stmt 1 view .LVU1305
+ 3941 002c 7047     		bx	lr
+ 3942              	.LVL335:
+ARM GAS  /tmp/cc0wMqvE.s 			page 224
+
+
+ 3943              	.L222:
+5836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3944              		.loc 1 5836 3 is_stmt 0 view .LVU1306
+ 3945 002e 0020     		movs	r0, #0
+ 3946              	.LVL336:
+5885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 3947              		.loc 1 5885 3 is_stmt 1 view .LVU1307
+5886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3948              		.loc 1 5886 1 is_stmt 0 view .LVU1308
+ 3949 0030 7047     		bx	lr
+ 3950              		.cfi_endproc
+ 3951              	.LFE404:
+ 3953              		.section	.text.HAL_TIM_PeriodElapsedCallback,"ax",%progbits
+ 3954              		.align	1
+ 3955              		.weak	HAL_TIM_PeriodElapsedCallback
+ 3956              		.syntax unified
+ 3957              		.thumb
+ 3958              		.thumb_func
+ 3960              	HAL_TIM_PeriodElapsedCallback:
+ 3961              	.LVL337:
+ 3962              	.LFB405:
+5921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 3963              		.loc 1 5921 1 is_stmt 1 view -0
+ 3964              		.cfi_startproc
+ 3965              		@ args = 0, pretend = 0, frame = 0
+ 3966              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3967              		@ link register save eliminated.
+5923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3968              		.loc 1 5923 3 view .LVU1310
+5928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3969              		.loc 1 5928 1 is_stmt 0 view .LVU1311
+ 3970 0000 7047     		bx	lr
+ 3971              		.cfi_endproc
+ 3972              	.LFE405:
+ 3974              		.section	.text.TIM_DMAPeriodElapsedCplt,"ax",%progbits
+ 3975              		.align	1
+ 3976              		.syntax unified
+ 3977              		.thumb
+ 3978              		.thumb_func
+ 3980              	TIM_DMAPeriodElapsedCplt:
+ 3981              	.LVL338:
+ 3982              	.LFB429:
+7032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 3983              		.loc 1 7032 1 is_stmt 1 view -0
+ 3984              		.cfi_startproc
+ 3985              		@ args = 0, pretend = 0, frame = 0
+ 3986              		@ frame_needed = 0, uses_anonymous_args = 0
+7032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 3987              		.loc 1 7032 1 is_stmt 0 view .LVU1313
+ 3988 0000 08B5     		push	{r3, lr}
+ 3989              	.LCFI38:
+ 3990              		.cfi_def_cfa_offset 8
+ 3991              		.cfi_offset 3, -8
+ 3992              		.cfi_offset 14, -4
+7033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 3993              		.loc 1 7033 3 is_stmt 1 view .LVU1314
+7033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 225
+
+
+ 3994              		.loc 1 7033 22 is_stmt 0 view .LVU1315
+ 3995 0002 806A     		ldr	r0, [r0, #40]
+ 3996              	.LVL339:
+7035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3997              		.loc 1 7035 3 is_stmt 1 view .LVU1316
+7035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 3998              		.loc 1 7035 17 is_stmt 0 view .LVU1317
+ 3999 0004 036A     		ldr	r3, [r0, #32]
+7035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4000              		.loc 1 7035 42 view .LVU1318
+ 4001 0006 DB69     		ldr	r3, [r3, #28]
+7035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4002              		.loc 1 7035 6 view .LVU1319
+ 4003 0008 13B9     		cbnz	r3, .L225
+7037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4004              		.loc 1 7037 5 is_stmt 1 view .LVU1320
+7037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4005              		.loc 1 7037 17 is_stmt 0 view .LVU1321
+ 4006 000a 0123     		movs	r3, #1
+ 4007 000c 80F83D30 		strb	r3, [r0, #61]
+ 4008              	.L225:
+7043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4009              		.loc 1 7043 3 is_stmt 1 view .LVU1322
+ 4010 0010 FFF7FEFF 		bl	HAL_TIM_PeriodElapsedCallback
+ 4011              	.LVL340:
+7045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4012              		.loc 1 7045 1 is_stmt 0 view .LVU1323
+ 4013 0014 08BD     		pop	{r3, pc}
+ 4014              		.cfi_endproc
+ 4015              	.LFE429:
+ 4017              		.section	.text.HAL_TIM_PeriodElapsedHalfCpltCallback,"ax",%progbits
+ 4018              		.align	1
+ 4019              		.weak	HAL_TIM_PeriodElapsedHalfCpltCallback
+ 4020              		.syntax unified
+ 4021              		.thumb
+ 4022              		.thumb_func
+ 4024              	HAL_TIM_PeriodElapsedHalfCpltCallback:
+ 4025              	.LVL341:
+ 4026              	.LFB406:
+5936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4027              		.loc 1 5936 1 is_stmt 1 view -0
+ 4028              		.cfi_startproc
+ 4029              		@ args = 0, pretend = 0, frame = 0
+ 4030              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4031              		@ link register save eliminated.
+5938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4032              		.loc 1 5938 3 view .LVU1325
+5943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4033              		.loc 1 5943 1 is_stmt 0 view .LVU1326
+ 4034 0000 7047     		bx	lr
+ 4035              		.cfi_endproc
+ 4036              	.LFE406:
+ 4038              		.section	.text.TIM_DMAPeriodElapsedHalfCplt,"ax",%progbits
+ 4039              		.align	1
+ 4040              		.syntax unified
+ 4041              		.thumb
+ 4042              		.thumb_func
+ARM GAS  /tmp/cc0wMqvE.s 			page 226
+
+
+ 4044              	TIM_DMAPeriodElapsedHalfCplt:
+ 4045              	.LVL342:
+ 4046              	.LFB430:
+7053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4047              		.loc 1 7053 1 is_stmt 1 view -0
+ 4048              		.cfi_startproc
+ 4049              		@ args = 0, pretend = 0, frame = 0
+ 4050              		@ frame_needed = 0, uses_anonymous_args = 0
+7053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4051              		.loc 1 7053 1 is_stmt 0 view .LVU1328
+ 4052 0000 08B5     		push	{r3, lr}
+ 4053              	.LCFI39:
+ 4054              		.cfi_def_cfa_offset 8
+ 4055              		.cfi_offset 3, -8
+ 4056              		.cfi_offset 14, -4
+7054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4057              		.loc 1 7054 3 is_stmt 1 view .LVU1329
+ 4058              	.LVL343:
+7059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4059              		.loc 1 7059 3 view .LVU1330
+ 4060 0002 806A     		ldr	r0, [r0, #40]
+ 4061              	.LVL344:
+7059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4062              		.loc 1 7059 3 is_stmt 0 view .LVU1331
+ 4063 0004 FFF7FEFF 		bl	HAL_TIM_PeriodElapsedHalfCpltCallback
+ 4064              	.LVL345:
+7061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4065              		.loc 1 7061 1 view .LVU1332
+ 4066 0008 08BD     		pop	{r3, pc}
+ 4067              		.cfi_endproc
+ 4068              	.LFE430:
+ 4070              		.section	.text.HAL_TIM_OC_DelayElapsedCallback,"ax",%progbits
+ 4071              		.align	1
+ 4072              		.weak	HAL_TIM_OC_DelayElapsedCallback
+ 4073              		.syntax unified
+ 4074              		.thumb
+ 4075              		.thumb_func
+ 4077              	HAL_TIM_OC_DelayElapsedCallback:
+ 4078              	.LVL346:
+ 4079              	.LFB407:
+5951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4080              		.loc 1 5951 1 is_stmt 1 view -0
+ 4081              		.cfi_startproc
+ 4082              		@ args = 0, pretend = 0, frame = 0
+ 4083              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4084              		@ link register save eliminated.
+5953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4085              		.loc 1 5953 3 view .LVU1334
+5958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4086              		.loc 1 5958 1 is_stmt 0 view .LVU1335
+ 4087 0000 7047     		bx	lr
+ 4088              		.cfi_endproc
+ 4089              	.LFE407:
+ 4091              		.section	.text.HAL_TIM_IC_CaptureCallback,"ax",%progbits
+ 4092              		.align	1
+ 4093              		.weak	HAL_TIM_IC_CaptureCallback
+ 4094              		.syntax unified
+ARM GAS  /tmp/cc0wMqvE.s 			page 227
+
+
+ 4095              		.thumb
+ 4096              		.thumb_func
+ 4098              	HAL_TIM_IC_CaptureCallback:
+ 4099              	.LVL347:
+ 4100              	.LFB408:
+5966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4101              		.loc 1 5966 1 is_stmt 1 view -0
+ 4102              		.cfi_startproc
+ 4103              		@ args = 0, pretend = 0, frame = 0
+ 4104              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4105              		@ link register save eliminated.
+5968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4106              		.loc 1 5968 3 view .LVU1337
+5973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4107              		.loc 1 5973 1 is_stmt 0 view .LVU1338
+ 4108 0000 7047     		bx	lr
+ 4109              		.cfi_endproc
+ 4110              	.LFE408:
+ 4112              		.section	.text.TIM_DMACaptureCplt,"ax",%progbits
+ 4113              		.align	1
+ 4114              		.global	TIM_DMACaptureCplt
+ 4115              		.syntax unified
+ 4116              		.thumb
+ 4117              		.thumb_func
+ 4119              	TIM_DMACaptureCplt:
+ 4120              	.LVL348:
+ 4121              	.LFB427:
+6930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4122              		.loc 1 6930 1 is_stmt 1 view -0
+ 4123              		.cfi_startproc
+ 4124              		@ args = 0, pretend = 0, frame = 0
+ 4125              		@ frame_needed = 0, uses_anonymous_args = 0
+6930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4126              		.loc 1 6930 1 is_stmt 0 view .LVU1340
+ 4127 0000 10B5     		push	{r4, lr}
+ 4128              	.LCFI40:
+ 4129              		.cfi_def_cfa_offset 8
+ 4130              		.cfi_offset 4, -8
+ 4131              		.cfi_offset 14, -4
+6931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4132              		.loc 1 6931 3 is_stmt 1 view .LVU1341
+6931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4133              		.loc 1 6931 22 is_stmt 0 view .LVU1342
+ 4134 0002 846A     		ldr	r4, [r0, #40]
+ 4135              	.LVL349:
+6933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4136              		.loc 1 6933 3 is_stmt 1 view .LVU1343
+6933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4137              		.loc 1 6933 25 is_stmt 0 view .LVU1344
+ 4138 0004 636A     		ldr	r3, [r4, #36]
+6933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4139              		.loc 1 6933 6 view .LVU1345
+ 4140 0006 8342     		cmp	r3, r0
+ 4141 0008 0ED0     		beq	.L238
+6943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4142              		.loc 1 6943 8 is_stmt 1 view .LVU1346
+6943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 228
+
+
+ 4143              		.loc 1 6943 30 is_stmt 0 view .LVU1347
+ 4144 000a A36A     		ldr	r3, [r4, #40]
+6943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4145              		.loc 1 6943 11 view .LVU1348
+ 4146 000c 8342     		cmp	r3, r0
+ 4147 000e 16D0     		beq	.L239
+6953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4148              		.loc 1 6953 8 is_stmt 1 view .LVU1349
+6953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4149              		.loc 1 6953 30 is_stmt 0 view .LVU1350
+ 4150 0010 E36A     		ldr	r3, [r4, #44]
+6953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4151              		.loc 1 6953 11 view .LVU1351
+ 4152 0012 8342     		cmp	r3, r0
+ 4153 0014 1ED0     		beq	.L240
+6963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4154              		.loc 1 6963 8 is_stmt 1 view .LVU1352
+6963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4155              		.loc 1 6963 30 is_stmt 0 view .LVU1353
+ 4156 0016 236B     		ldr	r3, [r4, #48]
+6963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4157              		.loc 1 6963 11 view .LVU1354
+ 4158 0018 8342     		cmp	r3, r0
+ 4159 001a 26D0     		beq	.L241
+ 4160              	.L234:
+6976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4161              		.loc 1 6976 3 is_stmt 1 view .LVU1355
+6981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4162              		.loc 1 6981 3 view .LVU1356
+ 4163 001c 2046     		mov	r0, r4
+ 4164              	.LVL350:
+6981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4165              		.loc 1 6981 3 is_stmt 0 view .LVU1357
+ 4166 001e FFF7FEFF 		bl	HAL_TIM_IC_CaptureCallback
+ 4167              	.LVL351:
+6984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 4168              		.loc 1 6984 3 is_stmt 1 view .LVU1358
+6984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 4169              		.loc 1 6984 17 is_stmt 0 view .LVU1359
+ 4170 0022 0023     		movs	r3, #0
+ 4171 0024 2377     		strb	r3, [r4, #28]
+6985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4172              		.loc 1 6985 1 view .LVU1360
+ 4173 0026 10BD     		pop	{r4, pc}
+ 4174              	.LVL352:
+ 4175              	.L238:
+6935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4176              		.loc 1 6935 5 is_stmt 1 view .LVU1361
+6935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4177              		.loc 1 6935 19 is_stmt 0 view .LVU1362
+ 4178 0028 0123     		movs	r3, #1
+ 4179 002a 2377     		strb	r3, [r4, #28]
+6937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4180              		.loc 1 6937 5 is_stmt 1 view .LVU1363
+6937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4181              		.loc 1 6937 19 is_stmt 0 view .LVU1364
+ 4182 002c C369     		ldr	r3, [r0, #28]
+ARM GAS  /tmp/cc0wMqvE.s 			page 229
+
+
+6937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4183              		.loc 1 6937 8 view .LVU1365
+ 4184 002e 002B     		cmp	r3, #0
+ 4185 0030 F4D1     		bne	.L234
+6939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 4186              		.loc 1 6939 7 is_stmt 1 view .LVU1366
+ 4187 0032 0123     		movs	r3, #1
+ 4188 0034 84F83E30 		strb	r3, [r4, #62]
+6940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4189              		.loc 1 6940 7 view .LVU1367
+ 4190 0038 84F84430 		strb	r3, [r4, #68]
+ 4191 003c EEE7     		b	.L234
+ 4192              	.L239:
+6945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4193              		.loc 1 6945 5 view .LVU1368
+6945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4194              		.loc 1 6945 19 is_stmt 0 view .LVU1369
+ 4195 003e 0223     		movs	r3, #2
+ 4196 0040 2377     		strb	r3, [r4, #28]
+6947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4197              		.loc 1 6947 5 is_stmt 1 view .LVU1370
+6947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4198              		.loc 1 6947 19 is_stmt 0 view .LVU1371
+ 4199 0042 C369     		ldr	r3, [r0, #28]
+6947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4200              		.loc 1 6947 8 view .LVU1372
+ 4201 0044 002B     		cmp	r3, #0
+ 4202 0046 E9D1     		bne	.L234
+6949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 4203              		.loc 1 6949 7 is_stmt 1 view .LVU1373
+ 4204 0048 0123     		movs	r3, #1
+ 4205 004a 84F83F30 		strb	r3, [r4, #63]
+6950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4206              		.loc 1 6950 7 view .LVU1374
+ 4207 004e 84F84530 		strb	r3, [r4, #69]
+ 4208 0052 E3E7     		b	.L234
+ 4209              	.L240:
+6955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4210              		.loc 1 6955 5 view .LVU1375
+6955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4211              		.loc 1 6955 19 is_stmt 0 view .LVU1376
+ 4212 0054 0423     		movs	r3, #4
+ 4213 0056 2377     		strb	r3, [r4, #28]
+6957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4214              		.loc 1 6957 5 is_stmt 1 view .LVU1377
+6957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4215              		.loc 1 6957 19 is_stmt 0 view .LVU1378
+ 4216 0058 C369     		ldr	r3, [r0, #28]
+6957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4217              		.loc 1 6957 8 view .LVU1379
+ 4218 005a 002B     		cmp	r3, #0
+ 4219 005c DED1     		bne	.L234
+6959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ 4220              		.loc 1 6959 7 is_stmt 1 view .LVU1380
+ 4221 005e 0123     		movs	r3, #1
+ 4222 0060 84F84030 		strb	r3, [r4, #64]
+6960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ARM GAS  /tmp/cc0wMqvE.s 			page 230
+
+
+ 4223              		.loc 1 6960 7 view .LVU1381
+ 4224 0064 84F84630 		strb	r3, [r4, #70]
+ 4225 0068 D8E7     		b	.L234
+ 4226              	.L241:
+6965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4227              		.loc 1 6965 5 view .LVU1382
+6965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4228              		.loc 1 6965 19 is_stmt 0 view .LVU1383
+ 4229 006a 0823     		movs	r3, #8
+ 4230 006c 2377     		strb	r3, [r4, #28]
+6967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4231              		.loc 1 6967 5 is_stmt 1 view .LVU1384
+6967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4232              		.loc 1 6967 19 is_stmt 0 view .LVU1385
+ 4233 006e C369     		ldr	r3, [r0, #28]
+6967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4234              		.loc 1 6967 8 view .LVU1386
+ 4235 0070 002B     		cmp	r3, #0
+ 4236 0072 D3D1     		bne	.L234
+6969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ 4237              		.loc 1 6969 7 is_stmt 1 view .LVU1387
+ 4238 0074 0123     		movs	r3, #1
+ 4239 0076 84F84130 		strb	r3, [r4, #65]
+6970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4240              		.loc 1 6970 7 view .LVU1388
+ 4241 007a 84F84730 		strb	r3, [r4, #71]
+ 4242 007e CDE7     		b	.L234
+ 4243              		.cfi_endproc
+ 4244              	.LFE427:
+ 4246              		.section	.text.HAL_TIM_IC_CaptureHalfCpltCallback,"ax",%progbits
+ 4247              		.align	1
+ 4248              		.weak	HAL_TIM_IC_CaptureHalfCpltCallback
+ 4249              		.syntax unified
+ 4250              		.thumb
+ 4251              		.thumb_func
+ 4253              	HAL_TIM_IC_CaptureHalfCpltCallback:
+ 4254              	.LVL353:
+ 4255              	.LFB409:
+5981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4256              		.loc 1 5981 1 view -0
+ 4257              		.cfi_startproc
+ 4258              		@ args = 0, pretend = 0, frame = 0
+ 4259              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4260              		@ link register save eliminated.
+5983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4261              		.loc 1 5983 3 view .LVU1390
+5988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4262              		.loc 1 5988 1 is_stmt 0 view .LVU1391
+ 4263 0000 7047     		bx	lr
+ 4264              		.cfi_endproc
+ 4265              	.LFE409:
+ 4267              		.section	.text.TIM_DMACaptureHalfCplt,"ax",%progbits
+ 4268              		.align	1
+ 4269              		.global	TIM_DMACaptureHalfCplt
+ 4270              		.syntax unified
+ 4271              		.thumb
+ 4272              		.thumb_func
+ARM GAS  /tmp/cc0wMqvE.s 			page 231
+
+
+ 4274              	TIM_DMACaptureHalfCplt:
+ 4275              	.LVL354:
+ 4276              	.LFB428:
+6993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4277              		.loc 1 6993 1 is_stmt 1 view -0
+ 4278              		.cfi_startproc
+ 4279              		@ args = 0, pretend = 0, frame = 0
+ 4280              		@ frame_needed = 0, uses_anonymous_args = 0
+6993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4281              		.loc 1 6993 1 is_stmt 0 view .LVU1393
+ 4282 0000 10B5     		push	{r4, lr}
+ 4283              	.LCFI41:
+ 4284              		.cfi_def_cfa_offset 8
+ 4285              		.cfi_offset 4, -8
+ 4286              		.cfi_offset 14, -4
+6994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4287              		.loc 1 6994 3 is_stmt 1 view .LVU1394
+6994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4288              		.loc 1 6994 22 is_stmt 0 view .LVU1395
+ 4289 0002 846A     		ldr	r4, [r0, #40]
+ 4290              	.LVL355:
+6996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4291              		.loc 1 6996 3 is_stmt 1 view .LVU1396
+6996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4292              		.loc 1 6996 25 is_stmt 0 view .LVU1397
+ 4293 0004 636A     		ldr	r3, [r4, #36]
+6996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4294              		.loc 1 6996 6 view .LVU1398
+ 4295 0006 8342     		cmp	r3, r0
+ 4296 0008 0BD0     		beq	.L249
+7000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4297              		.loc 1 7000 8 is_stmt 1 view .LVU1399
+7000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4298              		.loc 1 7000 30 is_stmt 0 view .LVU1400
+ 4299 000a A36A     		ldr	r3, [r4, #40]
+7000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4300              		.loc 1 7000 11 view .LVU1401
+ 4301 000c 8342     		cmp	r3, r0
+ 4302 000e 10D0     		beq	.L250
+7004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4303              		.loc 1 7004 8 is_stmt 1 view .LVU1402
+7004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4304              		.loc 1 7004 30 is_stmt 0 view .LVU1403
+ 4305 0010 E36A     		ldr	r3, [r4, #44]
+7004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4306              		.loc 1 7004 11 view .LVU1404
+ 4307 0012 8342     		cmp	r3, r0
+ 4308 0014 10D0     		beq	.L251
+7008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4309              		.loc 1 7008 8 is_stmt 1 view .LVU1405
+7008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4310              		.loc 1 7008 30 is_stmt 0 view .LVU1406
+ 4311 0016 236B     		ldr	r3, [r4, #48]
+7008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4312              		.loc 1 7008 11 view .LVU1407
+ 4313 0018 8342     		cmp	r3, r0
+ 4314 001a 04D1     		bne	.L245
+ARM GAS  /tmp/cc0wMqvE.s 			page 232
+
+
+7010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4315              		.loc 1 7010 5 is_stmt 1 view .LVU1408
+7010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4316              		.loc 1 7010 19 is_stmt 0 view .LVU1409
+ 4317 001c 0823     		movs	r3, #8
+ 4318 001e 2377     		strb	r3, [r4, #28]
+ 4319 0020 01E0     		b	.L245
+ 4320              	.L249:
+6998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4321              		.loc 1 6998 5 is_stmt 1 view .LVU1410
+6998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4322              		.loc 1 6998 19 is_stmt 0 view .LVU1411
+ 4323 0022 0123     		movs	r3, #1
+ 4324 0024 2377     		strb	r3, [r4, #28]
+ 4325              	.L245:
+7015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4326              		.loc 1 7015 3 is_stmt 1 view .LVU1412
+7020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4327              		.loc 1 7020 3 view .LVU1413
+ 4328 0026 2046     		mov	r0, r4
+ 4329              	.LVL356:
+7020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4330              		.loc 1 7020 3 is_stmt 0 view .LVU1414
+ 4331 0028 FFF7FEFF 		bl	HAL_TIM_IC_CaptureHalfCpltCallback
+ 4332              	.LVL357:
+7023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 4333              		.loc 1 7023 3 is_stmt 1 view .LVU1415
+7023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 4334              		.loc 1 7023 17 is_stmt 0 view .LVU1416
+ 4335 002c 0023     		movs	r3, #0
+ 4336 002e 2377     		strb	r3, [r4, #28]
+7024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4337              		.loc 1 7024 1 view .LVU1417
+ 4338 0030 10BD     		pop	{r4, pc}
+ 4339              	.LVL358:
+ 4340              	.L250:
+7002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4341              		.loc 1 7002 5 is_stmt 1 view .LVU1418
+7002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4342              		.loc 1 7002 19 is_stmt 0 view .LVU1419
+ 4343 0032 0223     		movs	r3, #2
+ 4344 0034 2377     		strb	r3, [r4, #28]
+ 4345 0036 F6E7     		b	.L245
+ 4346              	.L251:
+7006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4347              		.loc 1 7006 5 is_stmt 1 view .LVU1420
+7006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4348              		.loc 1 7006 19 is_stmt 0 view .LVU1421
+ 4349 0038 0423     		movs	r3, #4
+ 4350 003a 2377     		strb	r3, [r4, #28]
+ 4351 003c F3E7     		b	.L245
+ 4352              		.cfi_endproc
+ 4353              	.LFE428:
+ 4355              		.section	.text.HAL_TIM_PWM_PulseFinishedCallback,"ax",%progbits
+ 4356              		.align	1
+ 4357              		.weak	HAL_TIM_PWM_PulseFinishedCallback
+ 4358              		.syntax unified
+ARM GAS  /tmp/cc0wMqvE.s 			page 233
+
+
+ 4359              		.thumb
+ 4360              		.thumb_func
+ 4362              	HAL_TIM_PWM_PulseFinishedCallback:
+ 4363              	.LVL359:
+ 4364              	.LFB410:
+5996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4365              		.loc 1 5996 1 is_stmt 1 view -0
+ 4366              		.cfi_startproc
+ 4367              		@ args = 0, pretend = 0, frame = 0
+ 4368              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4369              		@ link register save eliminated.
+5998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4370              		.loc 1 5998 3 view .LVU1423
+6003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4371              		.loc 1 6003 1 is_stmt 0 view .LVU1424
+ 4372 0000 7047     		bx	lr
+ 4373              		.cfi_endproc
+ 4374              	.LFE410:
+ 4376              		.section	.text.TIM_DMADelayPulseCplt,"ax",%progbits
+ 4377              		.align	1
+ 4378              		.syntax unified
+ 4379              		.thumb
+ 4380              		.thumb_func
+ 4382              	TIM_DMADelayPulseCplt:
+ 4383              	.LVL360:
+ 4384              	.LFB425:
+6832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4385              		.loc 1 6832 1 is_stmt 1 view -0
+ 4386              		.cfi_startproc
+ 4387              		@ args = 0, pretend = 0, frame = 0
+ 4388              		@ frame_needed = 0, uses_anonymous_args = 0
+6832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4389              		.loc 1 6832 1 is_stmt 0 view .LVU1426
+ 4390 0000 10B5     		push	{r4, lr}
+ 4391              	.LCFI42:
+ 4392              		.cfi_def_cfa_offset 8
+ 4393              		.cfi_offset 4, -8
+ 4394              		.cfi_offset 14, -4
+6833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4395              		.loc 1 6833 3 is_stmt 1 view .LVU1427
+6833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4396              		.loc 1 6833 22 is_stmt 0 view .LVU1428
+ 4397 0002 846A     		ldr	r4, [r0, #40]
+ 4398              	.LVL361:
+6835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4399              		.loc 1 6835 3 is_stmt 1 view .LVU1429
+6835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4400              		.loc 1 6835 25 is_stmt 0 view .LVU1430
+ 4401 0004 636A     		ldr	r3, [r4, #36]
+6835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4402              		.loc 1 6835 6 view .LVU1431
+ 4403 0006 8342     		cmp	r3, r0
+ 4404 0008 0ED0     		beq	.L259
+6844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4405              		.loc 1 6844 8 is_stmt 1 view .LVU1432
+6844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4406              		.loc 1 6844 30 is_stmt 0 view .LVU1433
+ARM GAS  /tmp/cc0wMqvE.s 			page 234
+
+
+ 4407 000a A36A     		ldr	r3, [r4, #40]
+6844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4408              		.loc 1 6844 11 view .LVU1434
+ 4409 000c 8342     		cmp	r3, r0
+ 4410 000e 14D0     		beq	.L260
+6853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4411              		.loc 1 6853 8 is_stmt 1 view .LVU1435
+6853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4412              		.loc 1 6853 30 is_stmt 0 view .LVU1436
+ 4413 0010 E36A     		ldr	r3, [r4, #44]
+6853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4414              		.loc 1 6853 11 view .LVU1437
+ 4415 0012 8342     		cmp	r3, r0
+ 4416 0014 1AD0     		beq	.L261
+6862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4417              		.loc 1 6862 8 is_stmt 1 view .LVU1438
+6862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4418              		.loc 1 6862 30 is_stmt 0 view .LVU1439
+ 4419 0016 236B     		ldr	r3, [r4, #48]
+6862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4420              		.loc 1 6862 11 view .LVU1440
+ 4421 0018 8342     		cmp	r3, r0
+ 4422 001a 20D0     		beq	.L262
+ 4423              	.L255:
+6874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4424              		.loc 1 6874 3 is_stmt 1 view .LVU1441
+6879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4425              		.loc 1 6879 3 view .LVU1442
+ 4426 001c 2046     		mov	r0, r4
+ 4427              	.LVL362:
+6879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4428              		.loc 1 6879 3 is_stmt 0 view .LVU1443
+ 4429 001e FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedCallback
+ 4430              	.LVL363:
+6882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 4431              		.loc 1 6882 3 is_stmt 1 view .LVU1444
+6882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 4432              		.loc 1 6882 17 is_stmt 0 view .LVU1445
+ 4433 0022 0023     		movs	r3, #0
+ 4434 0024 2377     		strb	r3, [r4, #28]
+6883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4435              		.loc 1 6883 1 view .LVU1446
+ 4436 0026 10BD     		pop	{r4, pc}
+ 4437              	.LVL364:
+ 4438              	.L259:
+6837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4439              		.loc 1 6837 5 is_stmt 1 view .LVU1447
+6837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4440              		.loc 1 6837 19 is_stmt 0 view .LVU1448
+ 4441 0028 0123     		movs	r3, #1
+ 4442 002a 2377     		strb	r3, [r4, #28]
+6839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4443              		.loc 1 6839 5 is_stmt 1 view .LVU1449
+6839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4444              		.loc 1 6839 19 is_stmt 0 view .LVU1450
+ 4445 002c C369     		ldr	r3, [r0, #28]
+6839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ARM GAS  /tmp/cc0wMqvE.s 			page 235
+
+
+ 4446              		.loc 1 6839 8 view .LVU1451
+ 4447 002e 002B     		cmp	r3, #0
+ 4448 0030 F4D1     		bne	.L255
+6841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4449              		.loc 1 6841 7 is_stmt 1 view .LVU1452
+ 4450 0032 0123     		movs	r3, #1
+ 4451 0034 84F83E30 		strb	r3, [r4, #62]
+ 4452 0038 F0E7     		b	.L255
+ 4453              	.L260:
+6846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4454              		.loc 1 6846 5 view .LVU1453
+6846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4455              		.loc 1 6846 19 is_stmt 0 view .LVU1454
+ 4456 003a 0223     		movs	r3, #2
+ 4457 003c 2377     		strb	r3, [r4, #28]
+6848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4458              		.loc 1 6848 5 is_stmt 1 view .LVU1455
+6848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4459              		.loc 1 6848 19 is_stmt 0 view .LVU1456
+ 4460 003e C369     		ldr	r3, [r0, #28]
+6848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4461              		.loc 1 6848 8 view .LVU1457
+ 4462 0040 002B     		cmp	r3, #0
+ 4463 0042 EBD1     		bne	.L255
+6850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4464              		.loc 1 6850 7 is_stmt 1 view .LVU1458
+ 4465 0044 0123     		movs	r3, #1
+ 4466 0046 84F83F30 		strb	r3, [r4, #63]
+ 4467 004a E7E7     		b	.L255
+ 4468              	.L261:
+6855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4469              		.loc 1 6855 5 view .LVU1459
+6855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4470              		.loc 1 6855 19 is_stmt 0 view .LVU1460
+ 4471 004c 0423     		movs	r3, #4
+ 4472 004e 2377     		strb	r3, [r4, #28]
+6857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4473              		.loc 1 6857 5 is_stmt 1 view .LVU1461
+6857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4474              		.loc 1 6857 19 is_stmt 0 view .LVU1462
+ 4475 0050 C369     		ldr	r3, [r0, #28]
+6857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4476              		.loc 1 6857 8 view .LVU1463
+ 4477 0052 002B     		cmp	r3, #0
+ 4478 0054 E2D1     		bne	.L255
+6859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4479              		.loc 1 6859 7 is_stmt 1 view .LVU1464
+ 4480 0056 0123     		movs	r3, #1
+ 4481 0058 84F84030 		strb	r3, [r4, #64]
+ 4482 005c DEE7     		b	.L255
+ 4483              	.L262:
+6864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4484              		.loc 1 6864 5 view .LVU1465
+6864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4485              		.loc 1 6864 19 is_stmt 0 view .LVU1466
+ 4486 005e 0823     		movs	r3, #8
+ 4487 0060 2377     		strb	r3, [r4, #28]
+ARM GAS  /tmp/cc0wMqvE.s 			page 236
+
+
+6866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4488              		.loc 1 6866 5 is_stmt 1 view .LVU1467
+6866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4489              		.loc 1 6866 19 is_stmt 0 view .LVU1468
+ 4490 0062 C369     		ldr	r3, [r0, #28]
+6866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4491              		.loc 1 6866 8 view .LVU1469
+ 4492 0064 002B     		cmp	r3, #0
+ 4493 0066 D9D1     		bne	.L255
+6868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4494              		.loc 1 6868 7 is_stmt 1 view .LVU1470
+ 4495 0068 0123     		movs	r3, #1
+ 4496 006a 84F84130 		strb	r3, [r4, #65]
+ 4497 006e D5E7     		b	.L255
+ 4498              		.cfi_endproc
+ 4499              	.LFE425:
+ 4501              		.section	.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback,"ax",%progbits
+ 4502              		.align	1
+ 4503              		.weak	HAL_TIM_PWM_PulseFinishedHalfCpltCallback
+ 4504              		.syntax unified
+ 4505              		.thumb
+ 4506              		.thumb_func
+ 4508              	HAL_TIM_PWM_PulseFinishedHalfCpltCallback:
+ 4509              	.LVL365:
+ 4510              	.LFB411:
+6011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4511              		.loc 1 6011 1 view -0
+ 4512              		.cfi_startproc
+ 4513              		@ args = 0, pretend = 0, frame = 0
+ 4514              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4515              		@ link register save eliminated.
+6013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4516              		.loc 1 6013 3 view .LVU1472
+6018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4517              		.loc 1 6018 1 is_stmt 0 view .LVU1473
+ 4518 0000 7047     		bx	lr
+ 4519              		.cfi_endproc
+ 4520              	.LFE411:
+ 4522              		.section	.text.TIM_DMADelayPulseHalfCplt,"ax",%progbits
+ 4523              		.align	1
+ 4524              		.global	TIM_DMADelayPulseHalfCplt
+ 4525              		.syntax unified
+ 4526              		.thumb
+ 4527              		.thumb_func
+ 4529              	TIM_DMADelayPulseHalfCplt:
+ 4530              	.LVL366:
+ 4531              	.LFB426:
+6891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4532              		.loc 1 6891 1 is_stmt 1 view -0
+ 4533              		.cfi_startproc
+ 4534              		@ args = 0, pretend = 0, frame = 0
+ 4535              		@ frame_needed = 0, uses_anonymous_args = 0
+6891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4536              		.loc 1 6891 1 is_stmt 0 view .LVU1475
+ 4537 0000 10B5     		push	{r4, lr}
+ 4538              	.LCFI43:
+ 4539              		.cfi_def_cfa_offset 8
+ARM GAS  /tmp/cc0wMqvE.s 			page 237
+
+
+ 4540              		.cfi_offset 4, -8
+ 4541              		.cfi_offset 14, -4
+6892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4542              		.loc 1 6892 3 is_stmt 1 view .LVU1476
+6892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4543              		.loc 1 6892 22 is_stmt 0 view .LVU1477
+ 4544 0002 846A     		ldr	r4, [r0, #40]
+ 4545              	.LVL367:
+6894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4546              		.loc 1 6894 3 is_stmt 1 view .LVU1478
+6894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4547              		.loc 1 6894 25 is_stmt 0 view .LVU1479
+ 4548 0004 636A     		ldr	r3, [r4, #36]
+6894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4549              		.loc 1 6894 6 view .LVU1480
+ 4550 0006 8342     		cmp	r3, r0
+ 4551 0008 0BD0     		beq	.L270
+6898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4552              		.loc 1 6898 8 is_stmt 1 view .LVU1481
+6898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4553              		.loc 1 6898 30 is_stmt 0 view .LVU1482
+ 4554 000a A36A     		ldr	r3, [r4, #40]
+6898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4555              		.loc 1 6898 11 view .LVU1483
+ 4556 000c 8342     		cmp	r3, r0
+ 4557 000e 10D0     		beq	.L271
+6902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4558              		.loc 1 6902 8 is_stmt 1 view .LVU1484
+6902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4559              		.loc 1 6902 30 is_stmt 0 view .LVU1485
+ 4560 0010 E36A     		ldr	r3, [r4, #44]
+6902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4561              		.loc 1 6902 11 view .LVU1486
+ 4562 0012 8342     		cmp	r3, r0
+ 4563 0014 10D0     		beq	.L272
+6906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4564              		.loc 1 6906 8 is_stmt 1 view .LVU1487
+6906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4565              		.loc 1 6906 30 is_stmt 0 view .LVU1488
+ 4566 0016 236B     		ldr	r3, [r4, #48]
+6906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4567              		.loc 1 6906 11 view .LVU1489
+ 4568 0018 8342     		cmp	r3, r0
+ 4569 001a 04D1     		bne	.L266
+6908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4570              		.loc 1 6908 5 is_stmt 1 view .LVU1490
+6908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4571              		.loc 1 6908 19 is_stmt 0 view .LVU1491
+ 4572 001c 0823     		movs	r3, #8
+ 4573 001e 2377     		strb	r3, [r4, #28]
+ 4574 0020 01E0     		b	.L266
+ 4575              	.L270:
+6896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4576              		.loc 1 6896 5 is_stmt 1 view .LVU1492
+6896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4577              		.loc 1 6896 19 is_stmt 0 view .LVU1493
+ 4578 0022 0123     		movs	r3, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 238
+
+
+ 4579 0024 2377     		strb	r3, [r4, #28]
+ 4580              	.L266:
+6913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4581              		.loc 1 6913 3 is_stmt 1 view .LVU1494
+6918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4582              		.loc 1 6918 3 view .LVU1495
+ 4583 0026 2046     		mov	r0, r4
+ 4584              	.LVL368:
+6918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4585              		.loc 1 6918 3 is_stmt 0 view .LVU1496
+ 4586 0028 FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedHalfCpltCallback
+ 4587              	.LVL369:
+6921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 4588              		.loc 1 6921 3 is_stmt 1 view .LVU1497
+6921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 4589              		.loc 1 6921 17 is_stmt 0 view .LVU1498
+ 4590 002c 0023     		movs	r3, #0
+ 4591 002e 2377     		strb	r3, [r4, #28]
+6922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4592              		.loc 1 6922 1 view .LVU1499
+ 4593 0030 10BD     		pop	{r4, pc}
+ 4594              	.LVL370:
+ 4595              	.L271:
+6900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4596              		.loc 1 6900 5 is_stmt 1 view .LVU1500
+6900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4597              		.loc 1 6900 19 is_stmt 0 view .LVU1501
+ 4598 0032 0223     		movs	r3, #2
+ 4599 0034 2377     		strb	r3, [r4, #28]
+ 4600 0036 F6E7     		b	.L266
+ 4601              	.L272:
+6904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4602              		.loc 1 6904 5 is_stmt 1 view .LVU1502
+6904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 4603              		.loc 1 6904 19 is_stmt 0 view .LVU1503
+ 4604 0038 0423     		movs	r3, #4
+ 4605 003a 2377     		strb	r3, [r4, #28]
+ 4606 003c F3E7     		b	.L266
+ 4607              		.cfi_endproc
+ 4608              	.LFE426:
+ 4610              		.section	.text.HAL_TIM_TriggerCallback,"ax",%progbits
+ 4611              		.align	1
+ 4612              		.weak	HAL_TIM_TriggerCallback
+ 4613              		.syntax unified
+ 4614              		.thumb
+ 4615              		.thumb_func
+ 4617              	HAL_TIM_TriggerCallback:
+ 4618              	.LVL371:
+ 4619              	.LFB412:
+6026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4620              		.loc 1 6026 1 is_stmt 1 view -0
+ 4621              		.cfi_startproc
+ 4622              		@ args = 0, pretend = 0, frame = 0
+ 4623              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4624              		@ link register save eliminated.
+6028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4625              		.loc 1 6028 3 view .LVU1505
+ARM GAS  /tmp/cc0wMqvE.s 			page 239
+
+
+6033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4626              		.loc 1 6033 1 is_stmt 0 view .LVU1506
+ 4627 0000 7047     		bx	lr
+ 4628              		.cfi_endproc
+ 4629              	.LFE412:
+ 4631              		.section	.text.HAL_TIM_IRQHandler,"ax",%progbits
+ 4632              		.align	1
+ 4633              		.global	HAL_TIM_IRQHandler
+ 4634              		.syntax unified
+ 4635              		.thumb
+ 4636              		.thumb_func
+ 4638              	HAL_TIM_IRQHandler:
+ 4639              	.LVL372:
+ 4640              	.LFB387:
+3839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Capture compare 1 event */
+ 4641              		.loc 1 3839 1 is_stmt 1 view -0
+ 4642              		.cfi_startproc
+ 4643              		@ args = 0, pretend = 0, frame = 0
+ 4644              		@ frame_needed = 0, uses_anonymous_args = 0
+3839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Capture compare 1 event */
+ 4645              		.loc 1 3839 1 is_stmt 0 view .LVU1508
+ 4646 0000 10B5     		push	{r4, lr}
+ 4647              	.LCFI44:
+ 4648              		.cfi_def_cfa_offset 8
+ 4649              		.cfi_offset 4, -8
+ 4650              		.cfi_offset 14, -4
+ 4651 0002 0446     		mov	r4, r0
+3841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4652              		.loc 1 3841 3 is_stmt 1 view .LVU1509
+3841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4653              		.loc 1 3841 7 is_stmt 0 view .LVU1510
+ 4654 0004 0368     		ldr	r3, [r0]
+ 4655 0006 1A69     		ldr	r2, [r3, #16]
+3841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4656              		.loc 1 3841 6 view .LVU1511
+ 4657 0008 12F0020F 		tst	r2, #2
+ 4658 000c 12D0     		beq	.L275
+3843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4659              		.loc 1 3843 5 is_stmt 1 view .LVU1512
+3843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4660              		.loc 1 3843 9 is_stmt 0 view .LVU1513
+ 4661 000e DA68     		ldr	r2, [r3, #12]
+3843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4662              		.loc 1 3843 8 view .LVU1514
+ 4663 0010 12F0020F 		tst	r2, #2
+ 4664 0014 0ED0     		beq	.L275
+3846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ 4665              		.loc 1 3846 9 is_stmt 1 view .LVU1515
+ 4666 0016 6FF00202 		mvn	r2, #2
+ 4667 001a 1A61     		str	r2, [r3, #16]
+3847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4668              		.loc 1 3847 9 view .LVU1516
+3847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4669              		.loc 1 3847 23 is_stmt 0 view .LVU1517
+ 4670 001c 0123     		movs	r3, #1
+ 4671 001e 0377     		strb	r3, [r0, #28]
+3850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ARM GAS  /tmp/cc0wMqvE.s 			page 240
+
+
+ 4672              		.loc 1 3850 9 is_stmt 1 view .LVU1518
+3850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 4673              		.loc 1 3850 18 is_stmt 0 view .LVU1519
+ 4674 0020 0368     		ldr	r3, [r0]
+3850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 4675              		.loc 1 3850 28 view .LVU1520
+ 4676 0022 9B69     		ldr	r3, [r3, #24]
+3850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 4677              		.loc 1 3850 12 view .LVU1521
+ 4678 0024 13F0030F 		tst	r3, #3
+ 4679 0028 00F09F80 		beq	.L276
+3855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4680              		.loc 1 3855 11 is_stmt 1 view .LVU1522
+ 4681 002c FFF7FEFF 		bl	HAL_TIM_IC_CaptureCallback
+ 4682              	.LVL373:
+ 4683              	.L277:
+3869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 4684              		.loc 1 3869 9 view .LVU1523
+3869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 4685              		.loc 1 3869 23 is_stmt 0 view .LVU1524
+ 4686 0030 0023     		movs	r3, #0
+ 4687 0032 2377     		strb	r3, [r4, #28]
+ 4688              	.L275:
+3874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4689              		.loc 1 3874 3 is_stmt 1 view .LVU1525
+3874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4690              		.loc 1 3874 7 is_stmt 0 view .LVU1526
+ 4691 0034 2368     		ldr	r3, [r4]
+ 4692 0036 1A69     		ldr	r2, [r3, #16]
+3874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4693              		.loc 1 3874 6 view .LVU1527
+ 4694 0038 12F0040F 		tst	r2, #4
+ 4695 003c 13D0     		beq	.L278
+3876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4696              		.loc 1 3876 5 is_stmt 1 view .LVU1528
+3876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4697              		.loc 1 3876 9 is_stmt 0 view .LVU1529
+ 4698 003e DA68     		ldr	r2, [r3, #12]
+3876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4699              		.loc 1 3876 8 view .LVU1530
+ 4700 0040 12F0040F 		tst	r2, #4
+ 4701 0044 0FD0     		beq	.L278
+3878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ 4702              		.loc 1 3878 7 is_stmt 1 view .LVU1531
+ 4703 0046 6FF00402 		mvn	r2, #4
+ 4704 004a 1A61     		str	r2, [r3, #16]
+3879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Input capture event */
+ 4705              		.loc 1 3879 7 view .LVU1532
+3879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Input capture event */
+ 4706              		.loc 1 3879 21 is_stmt 0 view .LVU1533
+ 4707 004c 0223     		movs	r3, #2
+ 4708 004e 2377     		strb	r3, [r4, #28]
+3881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 4709              		.loc 1 3881 7 is_stmt 1 view .LVU1534
+3881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 4710              		.loc 1 3881 16 is_stmt 0 view .LVU1535
+ 4711 0050 2368     		ldr	r3, [r4]
+ARM GAS  /tmp/cc0wMqvE.s 			page 241
+
+
+3881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 4712              		.loc 1 3881 26 view .LVU1536
+ 4713 0052 9B69     		ldr	r3, [r3, #24]
+3881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 4714              		.loc 1 3881 10 view .LVU1537
+ 4715 0054 13F4407F 		tst	r3, #768
+ 4716 0058 00F08D80 		beq	.L279
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4717              		.loc 1 3886 9 is_stmt 1 view .LVU1538
+ 4718 005c 2046     		mov	r0, r4
+ 4719 005e FFF7FEFF 		bl	HAL_TIM_IC_CaptureCallback
+ 4720              	.LVL374:
+ 4721              	.L280:
+3900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4722              		.loc 1 3900 7 view .LVU1539
+3900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4723              		.loc 1 3900 21 is_stmt 0 view .LVU1540
+ 4724 0062 0023     		movs	r3, #0
+ 4725 0064 2377     		strb	r3, [r4, #28]
+ 4726              	.L278:
+3904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4727              		.loc 1 3904 3 is_stmt 1 view .LVU1541
+3904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4728              		.loc 1 3904 7 is_stmt 0 view .LVU1542
+ 4729 0066 2368     		ldr	r3, [r4]
+ 4730 0068 1A69     		ldr	r2, [r3, #16]
+3904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4731              		.loc 1 3904 6 view .LVU1543
+ 4732 006a 12F0080F 		tst	r2, #8
+ 4733 006e 12D0     		beq	.L281
+3906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4734              		.loc 1 3906 5 is_stmt 1 view .LVU1544
+3906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4735              		.loc 1 3906 9 is_stmt 0 view .LVU1545
+ 4736 0070 DA68     		ldr	r2, [r3, #12]
+3906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4737              		.loc 1 3906 8 view .LVU1546
+ 4738 0072 12F0080F 		tst	r2, #8
+ 4739 0076 0ED0     		beq	.L281
+3908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ 4740              		.loc 1 3908 7 is_stmt 1 view .LVU1547
+ 4741 0078 6FF00802 		mvn	r2, #8
+ 4742 007c 1A61     		str	r2, [r3, #16]
+3909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Input capture event */
+ 4743              		.loc 1 3909 7 view .LVU1548
+3909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Input capture event */
+ 4744              		.loc 1 3909 21 is_stmt 0 view .LVU1549
+ 4745 007e 0423     		movs	r3, #4
+ 4746 0080 2377     		strb	r3, [r4, #28]
+3911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 4747              		.loc 1 3911 7 is_stmt 1 view .LVU1550
+3911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 4748              		.loc 1 3911 16 is_stmt 0 view .LVU1551
+ 4749 0082 2368     		ldr	r3, [r4]
+3911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 4750              		.loc 1 3911 26 view .LVU1552
+ 4751 0084 DB69     		ldr	r3, [r3, #28]
+ARM GAS  /tmp/cc0wMqvE.s 			page 242
+
+
+3911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 4752              		.loc 1 3911 10 view .LVU1553
+ 4753 0086 13F0030F 		tst	r3, #3
+ 4754 008a 7BD0     		beq	.L282
+3916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4755              		.loc 1 3916 9 is_stmt 1 view .LVU1554
+ 4756 008c 2046     		mov	r0, r4
+ 4757 008e FFF7FEFF 		bl	HAL_TIM_IC_CaptureCallback
+ 4758              	.LVL375:
+ 4759              	.L283:
+3930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4760              		.loc 1 3930 7 view .LVU1555
+3930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4761              		.loc 1 3930 21 is_stmt 0 view .LVU1556
+ 4762 0092 0023     		movs	r3, #0
+ 4763 0094 2377     		strb	r3, [r4, #28]
+ 4764              	.L281:
+3934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4765              		.loc 1 3934 3 is_stmt 1 view .LVU1557
+3934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4766              		.loc 1 3934 7 is_stmt 0 view .LVU1558
+ 4767 0096 2368     		ldr	r3, [r4]
+ 4768 0098 1A69     		ldr	r2, [r3, #16]
+3934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4769              		.loc 1 3934 6 view .LVU1559
+ 4770 009a 12F0100F 		tst	r2, #16
+ 4771 009e 12D0     		beq	.L284
+3936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4772              		.loc 1 3936 5 is_stmt 1 view .LVU1560
+3936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4773              		.loc 1 3936 9 is_stmt 0 view .LVU1561
+ 4774 00a0 DA68     		ldr	r2, [r3, #12]
+3936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4775              		.loc 1 3936 8 view .LVU1562
+ 4776 00a2 12F0100F 		tst	r2, #16
+ 4777 00a6 0ED0     		beq	.L284
+3938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ 4778              		.loc 1 3938 7 is_stmt 1 view .LVU1563
+ 4779 00a8 6FF01002 		mvn	r2, #16
+ 4780 00ac 1A61     		str	r2, [r3, #16]
+3939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Input capture event */
+ 4781              		.loc 1 3939 7 view .LVU1564
+3939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Input capture event */
+ 4782              		.loc 1 3939 21 is_stmt 0 view .LVU1565
+ 4783 00ae 0823     		movs	r3, #8
+ 4784 00b0 2377     		strb	r3, [r4, #28]
+3941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 4785              		.loc 1 3941 7 is_stmt 1 view .LVU1566
+3941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 4786              		.loc 1 3941 16 is_stmt 0 view .LVU1567
+ 4787 00b2 2368     		ldr	r3, [r4]
+3941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 4788              		.loc 1 3941 26 view .LVU1568
+ 4789 00b4 DB69     		ldr	r3, [r3, #28]
+3941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 4790              		.loc 1 3941 10 view .LVU1569
+ 4791 00b6 13F4407F 		tst	r3, #768
+ARM GAS  /tmp/cc0wMqvE.s 			page 243
+
+
+ 4792 00ba 6AD0     		beq	.L285
+3946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4793              		.loc 1 3946 9 is_stmt 1 view .LVU1570
+ 4794 00bc 2046     		mov	r0, r4
+ 4795 00be FFF7FEFF 		bl	HAL_TIM_IC_CaptureCallback
+ 4796              	.LVL376:
+ 4797              	.L286:
+3960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4798              		.loc 1 3960 7 view .LVU1571
+3960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 4799              		.loc 1 3960 21 is_stmt 0 view .LVU1572
+ 4800 00c2 0023     		movs	r3, #0
+ 4801 00c4 2377     		strb	r3, [r4, #28]
+ 4802              	.L284:
+3964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4803              		.loc 1 3964 3 is_stmt 1 view .LVU1573
+3964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4804              		.loc 1 3964 7 is_stmt 0 view .LVU1574
+ 4805 00c6 2368     		ldr	r3, [r4]
+ 4806 00c8 1A69     		ldr	r2, [r3, #16]
+3964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4807              		.loc 1 3964 6 view .LVU1575
+ 4808 00ca 12F0010F 		tst	r2, #1
+ 4809 00ce 03D0     		beq	.L287
+3966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4810              		.loc 1 3966 5 is_stmt 1 view .LVU1576
+3966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4811              		.loc 1 3966 9 is_stmt 0 view .LVU1577
+ 4812 00d0 DA68     		ldr	r2, [r3, #12]
+3966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4813              		.loc 1 3966 8 view .LVU1578
+ 4814 00d2 12F0010F 		tst	r2, #1
+ 4815 00d6 63D1     		bne	.L297
+ 4816              	.L287:
+3977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4817              		.loc 1 3977 3 is_stmt 1 view .LVU1579
+3977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4818              		.loc 1 3977 7 is_stmt 0 view .LVU1580
+ 4819 00d8 2368     		ldr	r3, [r4]
+ 4820 00da 1A69     		ldr	r2, [r3, #16]
+3977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4821              		.loc 1 3977 6 view .LVU1581
+ 4822 00dc 12F0800F 		tst	r2, #128
+ 4823 00e0 03D0     		beq	.L288
+3979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4824              		.loc 1 3979 5 is_stmt 1 view .LVU1582
+3979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4825              		.loc 1 3979 9 is_stmt 0 view .LVU1583
+ 4826 00e2 DA68     		ldr	r2, [r3, #12]
+3979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4827              		.loc 1 3979 8 view .LVU1584
+ 4828 00e4 12F0800F 		tst	r2, #128
+ 4829 00e8 61D1     		bne	.L298
+ 4830              	.L288:
+3990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4831              		.loc 1 3990 3 is_stmt 1 view .LVU1585
+3990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 244
+
+
+ 4832              		.loc 1 3990 7 is_stmt 0 view .LVU1586
+ 4833 00ea 2368     		ldr	r3, [r4]
+ 4834 00ec 1A69     		ldr	r2, [r3, #16]
+3990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4835              		.loc 1 3990 6 view .LVU1587
+ 4836 00ee 12F4807F 		tst	r2, #256
+ 4837 00f2 03D0     		beq	.L289
+3992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4838              		.loc 1 3992 5 is_stmt 1 view .LVU1588
+3992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4839              		.loc 1 3992 9 is_stmt 0 view .LVU1589
+ 4840 00f4 DA68     		ldr	r2, [r3, #12]
+3992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4841              		.loc 1 3992 8 view .LVU1590
+ 4842 00f6 12F0800F 		tst	r2, #128
+ 4843 00fa 5FD1     		bne	.L299
+ 4844              	.L289:
+4003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4845              		.loc 1 4003 3 is_stmt 1 view .LVU1591
+4003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4846              		.loc 1 4003 7 is_stmt 0 view .LVU1592
+ 4847 00fc 2368     		ldr	r3, [r4]
+ 4848 00fe 1A69     		ldr	r2, [r3, #16]
+4003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4849              		.loc 1 4003 6 view .LVU1593
+ 4850 0100 12F0400F 		tst	r2, #64
+ 4851 0104 03D0     		beq	.L290
+4005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4852              		.loc 1 4005 5 is_stmt 1 view .LVU1594
+4005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4853              		.loc 1 4005 9 is_stmt 0 view .LVU1595
+ 4854 0106 DA68     		ldr	r2, [r3, #12]
+4005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4855              		.loc 1 4005 8 view .LVU1596
+ 4856 0108 12F0400F 		tst	r2, #64
+ 4857 010c 5DD1     		bne	.L300
+ 4858              	.L290:
+4016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4859              		.loc 1 4016 3 is_stmt 1 view .LVU1597
+4016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4860              		.loc 1 4016 7 is_stmt 0 view .LVU1598
+ 4861 010e 2368     		ldr	r3, [r4]
+ 4862 0110 1A69     		ldr	r2, [r3, #16]
+4016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4863              		.loc 1 4016 6 view .LVU1599
+ 4864 0112 12F0200F 		tst	r2, #32
+ 4865 0116 03D0     		beq	.L291
+4018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4866              		.loc 1 4018 5 is_stmt 1 view .LVU1600
+4018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4867              		.loc 1 4018 9 is_stmt 0 view .LVU1601
+ 4868 0118 DA68     		ldr	r2, [r3, #12]
+4018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4869              		.loc 1 4018 8 view .LVU1602
+ 4870 011a 12F0200F 		tst	r2, #32
+ 4871 011e 5BD1     		bne	.L301
+ 4872              	.L291:
+ARM GAS  /tmp/cc0wMqvE.s 			page 245
+
+
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4873              		.loc 1 4029 3 is_stmt 1 view .LVU1603
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4874              		.loc 1 4029 7 is_stmt 0 view .LVU1604
+ 4875 0120 2368     		ldr	r3, [r4]
+ 4876 0122 1A69     		ldr	r2, [r3, #16]
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4877              		.loc 1 4029 6 view .LVU1605
+ 4878 0124 12F4801F 		tst	r2, #1048576
+ 4879 0128 03D0     		beq	.L292
+4031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4880              		.loc 1 4031 5 is_stmt 1 view .LVU1606
+4031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4881              		.loc 1 4031 9 is_stmt 0 view .LVU1607
+ 4882 012a DA68     		ldr	r2, [r3, #12]
+4031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4883              		.loc 1 4031 8 view .LVU1608
+ 4884 012c 12F4801F 		tst	r2, #1048576
+ 4885 0130 59D1     		bne	.L302
+ 4886              	.L292:
+4042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4887              		.loc 1 4042 3 is_stmt 1 view .LVU1609
+4042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4888              		.loc 1 4042 7 is_stmt 0 view .LVU1610
+ 4889 0132 2368     		ldr	r3, [r4]
+ 4890 0134 1A69     		ldr	r2, [r3, #16]
+4042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4891              		.loc 1 4042 6 view .LVU1611
+ 4892 0136 12F4001F 		tst	r2, #2097152
+ 4893 013a 03D0     		beq	.L293
+4044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4894              		.loc 1 4044 5 is_stmt 1 view .LVU1612
+4044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4895              		.loc 1 4044 9 is_stmt 0 view .LVU1613
+ 4896 013c DA68     		ldr	r2, [r3, #12]
+4044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4897              		.loc 1 4044 8 view .LVU1614
+ 4898 013e 12F4001F 		tst	r2, #2097152
+ 4899 0142 57D1     		bne	.L303
+ 4900              	.L293:
+4055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4901              		.loc 1 4055 3 is_stmt 1 view .LVU1615
+4055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4902              		.loc 1 4055 7 is_stmt 0 view .LVU1616
+ 4903 0144 2368     		ldr	r3, [r4]
+ 4904 0146 1A69     		ldr	r2, [r3, #16]
+4055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4905              		.loc 1 4055 6 view .LVU1617
+ 4906 0148 12F4800F 		tst	r2, #4194304
+ 4907 014c 03D0     		beq	.L294
+4057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4908              		.loc 1 4057 5 is_stmt 1 view .LVU1618
+4057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4909              		.loc 1 4057 9 is_stmt 0 view .LVU1619
+ 4910 014e DA68     		ldr	r2, [r3, #12]
+4057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4911              		.loc 1 4057 8 view .LVU1620
+ARM GAS  /tmp/cc0wMqvE.s 			page 246
+
+
+ 4912 0150 12F4800F 		tst	r2, #4194304
+ 4913 0154 55D1     		bne	.L304
+ 4914              	.L294:
+4068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4915              		.loc 1 4068 3 is_stmt 1 view .LVU1621
+4068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4916              		.loc 1 4068 7 is_stmt 0 view .LVU1622
+ 4917 0156 2368     		ldr	r3, [r4]
+ 4918 0158 1A69     		ldr	r2, [r3, #16]
+4068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 4919              		.loc 1 4068 6 view .LVU1623
+ 4920 015a 12F4000F 		tst	r2, #8388608
+ 4921 015e 03D0     		beq	.L274
+4070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4922              		.loc 1 4070 5 is_stmt 1 view .LVU1624
+4070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4923              		.loc 1 4070 9 is_stmt 0 view .LVU1625
+ 4924 0160 DA68     		ldr	r2, [r3, #12]
+4070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 4925              		.loc 1 4070 8 view .LVU1626
+ 4926 0162 12F4000F 		tst	r2, #8388608
+ 4927 0166 53D1     		bne	.L305
+ 4928              	.L274:
+4080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 4929              		.loc 1 4080 1 view .LVU1627
+ 4930 0168 10BD     		pop	{r4, pc}
+ 4931              	.LVL377:
+ 4932              	.L276:
+3865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 4933              		.loc 1 3865 11 is_stmt 1 view .LVU1628
+ 4934 016a FFF7FEFF 		bl	HAL_TIM_OC_DelayElapsedCallback
+ 4935              	.LVL378:
+3866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4936              		.loc 1 3866 11 view .LVU1629
+ 4937 016e 2046     		mov	r0, r4
+ 4938 0170 FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedCallback
+ 4939              	.LVL379:
+ 4940 0174 5CE7     		b	.L277
+ 4941              	.L279:
+3896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 4942              		.loc 1 3896 9 view .LVU1630
+ 4943 0176 2046     		mov	r0, r4
+ 4944 0178 FFF7FEFF 		bl	HAL_TIM_OC_DelayElapsedCallback
+ 4945              	.LVL380:
+3897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4946              		.loc 1 3897 9 view .LVU1631
+ 4947 017c 2046     		mov	r0, r4
+ 4948 017e FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedCallback
+ 4949              	.LVL381:
+ 4950 0182 6EE7     		b	.L280
+ 4951              	.L282:
+3926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 4952              		.loc 1 3926 9 view .LVU1632
+ 4953 0184 2046     		mov	r0, r4
+ 4954 0186 FFF7FEFF 		bl	HAL_TIM_OC_DelayElapsedCallback
+ 4955              	.LVL382:
+3927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ARM GAS  /tmp/cc0wMqvE.s 			page 247
+
+
+ 4956              		.loc 1 3927 9 view .LVU1633
+ 4957 018a 2046     		mov	r0, r4
+ 4958 018c FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedCallback
+ 4959              	.LVL383:
+ 4960 0190 7FE7     		b	.L283
+ 4961              	.L285:
+3956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 4962              		.loc 1 3956 9 view .LVU1634
+ 4963 0192 2046     		mov	r0, r4
+ 4964 0194 FFF7FEFF 		bl	HAL_TIM_OC_DelayElapsedCallback
+ 4965              	.LVL384:
+3957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4966              		.loc 1 3957 9 view .LVU1635
+ 4967 0198 2046     		mov	r0, r4
+ 4968 019a FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedCallback
+ 4969              	.LVL385:
+ 4970 019e 90E7     		b	.L286
+ 4971              	.L297:
+3968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 4972              		.loc 1 3968 7 view .LVU1636
+ 4973 01a0 6FF00102 		mvn	r2, #1
+ 4974 01a4 1A61     		str	r2, [r3, #16]
+3972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4975              		.loc 1 3972 7 view .LVU1637
+ 4976 01a6 2046     		mov	r0, r4
+ 4977 01a8 FFF7FEFF 		bl	HAL_TIM_PeriodElapsedCallback
+ 4978              	.LVL386:
+ 4979 01ac 94E7     		b	.L287
+ 4980              	.L298:
+3981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 4981              		.loc 1 3981 7 view .LVU1638
+ 4982 01ae 6FF08002 		mvn	r2, #128
+ 4983 01b2 1A61     		str	r2, [r3, #16]
+3985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4984              		.loc 1 3985 7 view .LVU1639
+ 4985 01b4 2046     		mov	r0, r4
+ 4986 01b6 FFF7FEFF 		bl	HAL_TIMEx_BreakCallback
+ 4987              	.LVL387:
+ 4988 01ba 96E7     		b	.L288
+ 4989              	.L299:
+3994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 4990              		.loc 1 3994 7 view .LVU1640
+ 4991 01bc 6FF48072 		mvn	r2, #256
+ 4992 01c0 1A61     		str	r2, [r3, #16]
+3998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4993              		.loc 1 3998 7 view .LVU1641
+ 4994 01c2 2046     		mov	r0, r4
+ 4995 01c4 FFF7FEFF 		bl	HAL_TIMEx_Break2Callback
+ 4996              	.LVL388:
+ 4997 01c8 98E7     		b	.L289
+ 4998              	.L300:
+4007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 4999              		.loc 1 4007 7 view .LVU1642
+ 5000 01ca 6FF04002 		mvn	r2, #64
+ 5001 01ce 1A61     		str	r2, [r3, #16]
+4011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5002              		.loc 1 4011 7 view .LVU1643
+ARM GAS  /tmp/cc0wMqvE.s 			page 248
+
+
+ 5003 01d0 2046     		mov	r0, r4
+ 5004 01d2 FFF7FEFF 		bl	HAL_TIM_TriggerCallback
+ 5005              	.LVL389:
+ 5006 01d6 9AE7     		b	.L290
+ 5007              	.L301:
+4020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 5008              		.loc 1 4020 7 view .LVU1644
+ 5009 01d8 6FF02002 		mvn	r2, #32
+ 5010 01dc 1A61     		str	r2, [r3, #16]
+4024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5011              		.loc 1 4024 7 view .LVU1645
+ 5012 01de 2046     		mov	r0, r4
+ 5013 01e0 FFF7FEFF 		bl	HAL_TIMEx_CommutCallback
+ 5014              	.LVL390:
+ 5015 01e4 9CE7     		b	.L291
+ 5016              	.L302:
+4033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 5017              		.loc 1 4033 7 view .LVU1646
+ 5018 01e6 6FF48012 		mvn	r2, #1048576
+ 5019 01ea 1A61     		str	r2, [r3, #16]
+4037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5020              		.loc 1 4037 7 view .LVU1647
+ 5021 01ec 2046     		mov	r0, r4
+ 5022 01ee FFF7FEFF 		bl	HAL_TIMEx_EncoderIndexCallback
+ 5023              	.LVL391:
+ 5024 01f2 9EE7     		b	.L292
+ 5025              	.L303:
+4046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 5026              		.loc 1 4046 7 view .LVU1648
+ 5027 01f4 6FF40012 		mvn	r2, #2097152
+ 5028 01f8 1A61     		str	r2, [r3, #16]
+4050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5029              		.loc 1 4050 7 view .LVU1649
+ 5030 01fa 2046     		mov	r0, r4
+ 5031 01fc FFF7FEFF 		bl	HAL_TIMEx_DirectionChangeCallback
+ 5032              	.LVL392:
+ 5033 0200 A0E7     		b	.L293
+ 5034              	.L304:
+4059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 5035              		.loc 1 4059 7 view .LVU1650
+ 5036 0202 6FF48002 		mvn	r2, #4194304
+ 5037 0206 1A61     		str	r2, [r3, #16]
+4063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5038              		.loc 1 4063 7 view .LVU1651
+ 5039 0208 2046     		mov	r0, r4
+ 5040 020a FFF7FEFF 		bl	HAL_TIMEx_IndexErrorCallback
+ 5041              	.LVL393:
+ 5042 020e A2E7     		b	.L294
+ 5043              	.L305:
+4072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 5044              		.loc 1 4072 7 view .LVU1652
+ 5045 0210 6FF40002 		mvn	r2, #8388608
+ 5046 0214 1A61     		str	r2, [r3, #16]
+4076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5047              		.loc 1 4076 7 view .LVU1653
+ 5048 0216 2046     		mov	r0, r4
+ 5049 0218 FFF7FEFF 		bl	HAL_TIMEx_TransitionErrorCallback
+ARM GAS  /tmp/cc0wMqvE.s 			page 249
+
+
+ 5050              	.LVL394:
+4080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5051              		.loc 1 4080 1 is_stmt 0 view .LVU1654
+ 5052 021c A4E7     		b	.L274
+ 5053              		.cfi_endproc
+ 5054              	.LFE387:
+ 5056              		.section	.text.TIM_DMATriggerCplt,"ax",%progbits
+ 5057              		.align	1
+ 5058              		.syntax unified
+ 5059              		.thumb
+ 5060              		.thumb_func
+ 5062              	TIM_DMATriggerCplt:
+ 5063              	.LVL395:
+ 5064              	.LFB431:
+7069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 5065              		.loc 1 7069 1 is_stmt 1 view -0
+ 5066              		.cfi_startproc
+ 5067              		@ args = 0, pretend = 0, frame = 0
+ 5068              		@ frame_needed = 0, uses_anonymous_args = 0
+7069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 5069              		.loc 1 7069 1 is_stmt 0 view .LVU1656
+ 5070 0000 08B5     		push	{r3, lr}
+ 5071              	.LCFI45:
+ 5072              		.cfi_def_cfa_offset 8
+ 5073              		.cfi_offset 3, -8
+ 5074              		.cfi_offset 14, -4
+7070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5075              		.loc 1 7070 3 is_stmt 1 view .LVU1657
+7070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5076              		.loc 1 7070 22 is_stmt 0 view .LVU1658
+ 5077 0002 806A     		ldr	r0, [r0, #40]
+ 5078              	.LVL396:
+7072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5079              		.loc 1 7072 3 is_stmt 1 view .LVU1659
+7072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5080              		.loc 1 7072 17 is_stmt 0 view .LVU1660
+ 5081 0004 836B     		ldr	r3, [r0, #56]
+7072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5082              		.loc 1 7072 43 view .LVU1661
+ 5083 0006 DB69     		ldr	r3, [r3, #28]
+7072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5084              		.loc 1 7072 6 view .LVU1662
+ 5085 0008 13B9     		cbnz	r3, .L307
+7074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5086              		.loc 1 7074 5 is_stmt 1 view .LVU1663
+7074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5087              		.loc 1 7074 17 is_stmt 0 view .LVU1664
+ 5088 000a 0123     		movs	r3, #1
+ 5089 000c 80F83D30 		strb	r3, [r0, #61]
+ 5090              	.L307:
+7080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5091              		.loc 1 7080 3 is_stmt 1 view .LVU1665
+ 5092 0010 FFF7FEFF 		bl	HAL_TIM_TriggerCallback
+ 5093              	.LVL397:
+7082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5094              		.loc 1 7082 1 is_stmt 0 view .LVU1666
+ 5095 0014 08BD     		pop	{r3, pc}
+ARM GAS  /tmp/cc0wMqvE.s 			page 250
+
+
+ 5096              		.cfi_endproc
+ 5097              	.LFE431:
+ 5099              		.section	.text.HAL_TIM_TriggerHalfCpltCallback,"ax",%progbits
+ 5100              		.align	1
+ 5101              		.weak	HAL_TIM_TriggerHalfCpltCallback
+ 5102              		.syntax unified
+ 5103              		.thumb
+ 5104              		.thumb_func
+ 5106              	HAL_TIM_TriggerHalfCpltCallback:
+ 5107              	.LVL398:
+ 5108              	.LFB413:
+6041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 5109              		.loc 1 6041 1 is_stmt 1 view -0
+ 5110              		.cfi_startproc
+ 5111              		@ args = 0, pretend = 0, frame = 0
+ 5112              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5113              		@ link register save eliminated.
+6043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5114              		.loc 1 6043 3 view .LVU1668
+6048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5115              		.loc 1 6048 1 is_stmt 0 view .LVU1669
+ 5116 0000 7047     		bx	lr
+ 5117              		.cfi_endproc
+ 5118              	.LFE413:
+ 5120              		.section	.text.TIM_DMATriggerHalfCplt,"ax",%progbits
+ 5121              		.align	1
+ 5122              		.syntax unified
+ 5123              		.thumb
+ 5124              		.thumb_func
+ 5126              	TIM_DMATriggerHalfCplt:
+ 5127              	.LVL399:
+ 5128              	.LFB432:
+7090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 5129              		.loc 1 7090 1 is_stmt 1 view -0
+ 5130              		.cfi_startproc
+ 5131              		@ args = 0, pretend = 0, frame = 0
+ 5132              		@ frame_needed = 0, uses_anonymous_args = 0
+7090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 5133              		.loc 1 7090 1 is_stmt 0 view .LVU1671
+ 5134 0000 08B5     		push	{r3, lr}
+ 5135              	.LCFI46:
+ 5136              		.cfi_def_cfa_offset 8
+ 5137              		.cfi_offset 3, -8
+ 5138              		.cfi_offset 14, -4
+7091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5139              		.loc 1 7091 3 is_stmt 1 view .LVU1672
+ 5140              	.LVL400:
+7096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5141              		.loc 1 7096 3 view .LVU1673
+ 5142 0002 806A     		ldr	r0, [r0, #40]
+ 5143              	.LVL401:
+7096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5144              		.loc 1 7096 3 is_stmt 0 view .LVU1674
+ 5145 0004 FFF7FEFF 		bl	HAL_TIM_TriggerHalfCpltCallback
+ 5146              	.LVL402:
+7098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5147              		.loc 1 7098 1 view .LVU1675
+ARM GAS  /tmp/cc0wMqvE.s 			page 251
+
+
+ 5148 0008 08BD     		pop	{r3, pc}
+ 5149              		.cfi_endproc
+ 5150              	.LFE432:
+ 5152              		.section	.text.HAL_TIM_ErrorCallback,"ax",%progbits
+ 5153              		.align	1
+ 5154              		.weak	HAL_TIM_ErrorCallback
+ 5155              		.syntax unified
+ 5156              		.thumb
+ 5157              		.thumb_func
+ 5159              	HAL_TIM_ErrorCallback:
+ 5160              	.LVL403:
+ 5161              	.LFB414:
+6056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 5162              		.loc 1 6056 1 is_stmt 1 view -0
+ 5163              		.cfi_startproc
+ 5164              		@ args = 0, pretend = 0, frame = 0
+ 5165              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5166              		@ link register save eliminated.
+6058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5167              		.loc 1 6058 3 view .LVU1677
+6063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5168              		.loc 1 6063 1 is_stmt 0 view .LVU1678
+ 5169 0000 7047     		bx	lr
+ 5170              		.cfi_endproc
+ 5171              	.LFE414:
+ 5173              		.section	.text.TIM_DMAError,"ax",%progbits
+ 5174              		.align	1
+ 5175              		.global	TIM_DMAError
+ 5176              		.syntax unified
+ 5177              		.thumb
+ 5178              		.thumb_func
+ 5180              	TIM_DMAError:
+ 5181              	.LVL404:
+ 5182              	.LFB424:
+6789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 5183              		.loc 1 6789 1 is_stmt 1 view -0
+ 5184              		.cfi_startproc
+ 5185              		@ args = 0, pretend = 0, frame = 0
+ 5186              		@ frame_needed = 0, uses_anonymous_args = 0
+6789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 5187              		.loc 1 6789 1 is_stmt 0 view .LVU1680
+ 5188 0000 10B5     		push	{r4, lr}
+ 5189              	.LCFI47:
+ 5190              		.cfi_def_cfa_offset 8
+ 5191              		.cfi_offset 4, -8
+ 5192              		.cfi_offset 14, -4
+6790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5193              		.loc 1 6790 3 is_stmt 1 view .LVU1681
+6790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5194              		.loc 1 6790 22 is_stmt 0 view .LVU1682
+ 5195 0002 846A     		ldr	r4, [r0, #40]
+ 5196              	.LVL405:
+6792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5197              		.loc 1 6792 3 is_stmt 1 view .LVU1683
+6792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5198              		.loc 1 6792 25 is_stmt 0 view .LVU1684
+ 5199 0004 636A     		ldr	r3, [r4, #36]
+ARM GAS  /tmp/cc0wMqvE.s 			page 252
+
+
+6792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5200              		.loc 1 6792 6 view .LVU1685
+ 5201 0006 8342     		cmp	r3, r0
+ 5202 0008 0CD0     		beq	.L320
+6797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5203              		.loc 1 6797 8 is_stmt 1 view .LVU1686
+6797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5204              		.loc 1 6797 30 is_stmt 0 view .LVU1687
+ 5205 000a A36A     		ldr	r3, [r4, #40]
+6797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5206              		.loc 1 6797 11 view .LVU1688
+ 5207 000c 8342     		cmp	r3, r0
+ 5208 000e 13D0     		beq	.L321
+6802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5209              		.loc 1 6802 8 is_stmt 1 view .LVU1689
+6802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5210              		.loc 1 6802 30 is_stmt 0 view .LVU1690
+ 5211 0010 E36A     		ldr	r3, [r4, #44]
+6802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5212              		.loc 1 6802 11 view .LVU1691
+ 5213 0012 8342     		cmp	r3, r0
+ 5214 0014 16D0     		beq	.L322
+6807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5215              		.loc 1 6807 8 is_stmt 1 view .LVU1692
+6807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5216              		.loc 1 6807 30 is_stmt 0 view .LVU1693
+ 5217 0016 236B     		ldr	r3, [r4, #48]
+6807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5218              		.loc 1 6807 11 view .LVU1694
+ 5219 0018 8342     		cmp	r3, r0
+ 5220 001a 19D0     		beq	.L323
+6814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5221              		.loc 1 6814 5 is_stmt 1 view .LVU1695
+6814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5222              		.loc 1 6814 17 is_stmt 0 view .LVU1696
+ 5223 001c 0123     		movs	r3, #1
+ 5224 001e 84F83D30 		strb	r3, [r4, #61]
+ 5225 0022 03E0     		b	.L315
+ 5226              	.L320:
+6794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 5227              		.loc 1 6794 5 is_stmt 1 view .LVU1697
+6794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 5228              		.loc 1 6794 19 is_stmt 0 view .LVU1698
+ 5229 0024 0123     		movs	r3, #1
+ 5230 0026 2377     		strb	r3, [r4, #28]
+6795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5231              		.loc 1 6795 5 is_stmt 1 view .LVU1699
+ 5232 0028 84F83E30 		strb	r3, [r4, #62]
+ 5233              	.L315:
+6820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5234              		.loc 1 6820 3 view .LVU1700
+ 5235 002c 2046     		mov	r0, r4
+ 5236              	.LVL406:
+6820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5237              		.loc 1 6820 3 is_stmt 0 view .LVU1701
+ 5238 002e FFF7FEFF 		bl	HAL_TIM_ErrorCallback
+ 5239              	.LVL407:
+ARM GAS  /tmp/cc0wMqvE.s 			page 253
+
+
+6823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5240              		.loc 1 6823 3 is_stmt 1 view .LVU1702
+6823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5241              		.loc 1 6823 17 is_stmt 0 view .LVU1703
+ 5242 0032 0023     		movs	r3, #0
+ 5243 0034 2377     		strb	r3, [r4, #28]
+6824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5244              		.loc 1 6824 1 view .LVU1704
+ 5245 0036 10BD     		pop	{r4, pc}
+ 5246              	.LVL408:
+ 5247              	.L321:
+6799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 5248              		.loc 1 6799 5 is_stmt 1 view .LVU1705
+6799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 5249              		.loc 1 6799 19 is_stmt 0 view .LVU1706
+ 5250 0038 0223     		movs	r3, #2
+ 5251 003a 2377     		strb	r3, [r4, #28]
+6800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5252              		.loc 1 6800 5 is_stmt 1 view .LVU1707
+ 5253 003c 0123     		movs	r3, #1
+ 5254 003e 84F83F30 		strb	r3, [r4, #63]
+ 5255 0042 F3E7     		b	.L315
+ 5256              	.L322:
+6804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ 5257              		.loc 1 6804 5 view .LVU1708
+6804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ 5258              		.loc 1 6804 19 is_stmt 0 view .LVU1709
+ 5259 0044 0423     		movs	r3, #4
+ 5260 0046 2377     		strb	r3, [r4, #28]
+6805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5261              		.loc 1 6805 5 is_stmt 1 view .LVU1710
+ 5262 0048 0123     		movs	r3, #1
+ 5263 004a 84F84030 		strb	r3, [r4, #64]
+ 5264 004e EDE7     		b	.L315
+ 5265              	.L323:
+6809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ 5266              		.loc 1 6809 5 view .LVU1711
+6809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ 5267              		.loc 1 6809 19 is_stmt 0 view .LVU1712
+ 5268 0050 0823     		movs	r3, #8
+ 5269 0052 2377     		strb	r3, [r4, #28]
+6810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5270              		.loc 1 6810 5 is_stmt 1 view .LVU1713
+ 5271 0054 0123     		movs	r3, #1
+ 5272 0056 84F84130 		strb	r3, [r4, #65]
+ 5273 005a E7E7     		b	.L315
+ 5274              		.cfi_endproc
+ 5275              	.LFE424:
+ 5277              		.section	.text.HAL_TIM_Base_GetState,"ax",%progbits
+ 5278              		.align	1
+ 5279              		.global	HAL_TIM_Base_GetState
+ 5280              		.syntax unified
+ 5281              		.thumb
+ 5282              		.thumb_func
+ 5284              	HAL_TIM_Base_GetState:
+ 5285              	.LVL409:
+ 5286              	.LFB415:
+ARM GAS  /tmp/cc0wMqvE.s 			page 254
+
+
+6669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->State;
+ 5287              		.loc 1 6669 1 view -0
+ 5288              		.cfi_startproc
+ 5289              		@ args = 0, pretend = 0, frame = 0
+ 5290              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5291              		@ link register save eliminated.
+6670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5292              		.loc 1 6670 3 view .LVU1715
+6670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5293              		.loc 1 6670 14 is_stmt 0 view .LVU1716
+ 5294 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5295              	.LVL410:
+6671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5296              		.loc 1 6671 1 view .LVU1717
+ 5297 0004 7047     		bx	lr
+ 5298              		.cfi_endproc
+ 5299              	.LFE415:
+ 5301              		.section	.text.HAL_TIM_OC_GetState,"ax",%progbits
+ 5302              		.align	1
+ 5303              		.global	HAL_TIM_OC_GetState
+ 5304              		.syntax unified
+ 5305              		.thumb
+ 5306              		.thumb_func
+ 5308              	HAL_TIM_OC_GetState:
+ 5309              	.LVL411:
+ 5310              	.LFB416:
+6679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->State;
+ 5311              		.loc 1 6679 1 is_stmt 1 view -0
+ 5312              		.cfi_startproc
+ 5313              		@ args = 0, pretend = 0, frame = 0
+ 5314              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5315              		@ link register save eliminated.
+6680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5316              		.loc 1 6680 3 view .LVU1719
+6680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5317              		.loc 1 6680 14 is_stmt 0 view .LVU1720
+ 5318 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5319              	.LVL412:
+6681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5320              		.loc 1 6681 1 view .LVU1721
+ 5321 0004 7047     		bx	lr
+ 5322              		.cfi_endproc
+ 5323              	.LFE416:
+ 5325              		.section	.text.HAL_TIM_PWM_GetState,"ax",%progbits
+ 5326              		.align	1
+ 5327              		.global	HAL_TIM_PWM_GetState
+ 5328              		.syntax unified
+ 5329              		.thumb
+ 5330              		.thumb_func
+ 5332              	HAL_TIM_PWM_GetState:
+ 5333              	.LVL413:
+ 5334              	.LFB417:
+6689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->State;
+ 5335              		.loc 1 6689 1 is_stmt 1 view -0
+ 5336              		.cfi_startproc
+ 5337              		@ args = 0, pretend = 0, frame = 0
+ 5338              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cc0wMqvE.s 			page 255
+
+
+ 5339              		@ link register save eliminated.
+6690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5340              		.loc 1 6690 3 view .LVU1723
+6690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5341              		.loc 1 6690 14 is_stmt 0 view .LVU1724
+ 5342 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5343              	.LVL414:
+6691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5344              		.loc 1 6691 1 view .LVU1725
+ 5345 0004 7047     		bx	lr
+ 5346              		.cfi_endproc
+ 5347              	.LFE417:
+ 5349              		.section	.text.HAL_TIM_IC_GetState,"ax",%progbits
+ 5350              		.align	1
+ 5351              		.global	HAL_TIM_IC_GetState
+ 5352              		.syntax unified
+ 5353              		.thumb
+ 5354              		.thumb_func
+ 5356              	HAL_TIM_IC_GetState:
+ 5357              	.LVL415:
+ 5358              	.LFB418:
+6699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->State;
+ 5359              		.loc 1 6699 1 is_stmt 1 view -0
+ 5360              		.cfi_startproc
+ 5361              		@ args = 0, pretend = 0, frame = 0
+ 5362              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5363              		@ link register save eliminated.
+6700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5364              		.loc 1 6700 3 view .LVU1727
+6700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5365              		.loc 1 6700 14 is_stmt 0 view .LVU1728
+ 5366 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5367              	.LVL416:
+6701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5368              		.loc 1 6701 1 view .LVU1729
+ 5369 0004 7047     		bx	lr
+ 5370              		.cfi_endproc
+ 5371              	.LFE418:
+ 5373              		.section	.text.HAL_TIM_OnePulse_GetState,"ax",%progbits
+ 5374              		.align	1
+ 5375              		.global	HAL_TIM_OnePulse_GetState
+ 5376              		.syntax unified
+ 5377              		.thumb
+ 5378              		.thumb_func
+ 5380              	HAL_TIM_OnePulse_GetState:
+ 5381              	.LVL417:
+ 5382              	.LFB419:
+6709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->State;
+ 5383              		.loc 1 6709 1 is_stmt 1 view -0
+ 5384              		.cfi_startproc
+ 5385              		@ args = 0, pretend = 0, frame = 0
+ 5386              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5387              		@ link register save eliminated.
+6710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5388              		.loc 1 6710 3 view .LVU1731
+6710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5389              		.loc 1 6710 14 is_stmt 0 view .LVU1732
+ARM GAS  /tmp/cc0wMqvE.s 			page 256
+
+
+ 5390 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5391              	.LVL418:
+6711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5392              		.loc 1 6711 1 view .LVU1733
+ 5393 0004 7047     		bx	lr
+ 5394              		.cfi_endproc
+ 5395              	.LFE419:
+ 5397              		.section	.text.HAL_TIM_Encoder_GetState,"ax",%progbits
+ 5398              		.align	1
+ 5399              		.global	HAL_TIM_Encoder_GetState
+ 5400              		.syntax unified
+ 5401              		.thumb
+ 5402              		.thumb_func
+ 5404              	HAL_TIM_Encoder_GetState:
+ 5405              	.LVL419:
+ 5406              	.LFB420:
+6719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->State;
+ 5407              		.loc 1 6719 1 is_stmt 1 view -0
+ 5408              		.cfi_startproc
+ 5409              		@ args = 0, pretend = 0, frame = 0
+ 5410              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5411              		@ link register save eliminated.
+6720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5412              		.loc 1 6720 3 view .LVU1735
+6720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5413              		.loc 1 6720 14 is_stmt 0 view .LVU1736
+ 5414 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5415              	.LVL420:
+6721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5416              		.loc 1 6721 1 view .LVU1737
+ 5417 0004 7047     		bx	lr
+ 5418              		.cfi_endproc
+ 5419              	.LFE420:
+ 5421              		.section	.text.HAL_TIM_GetActiveChannel,"ax",%progbits
+ 5422              		.align	1
+ 5423              		.global	HAL_TIM_GetActiveChannel
+ 5424              		.syntax unified
+ 5425              		.thumb
+ 5426              		.thumb_func
+ 5428              	HAL_TIM_GetActiveChannel:
+ 5429              	.LVL421:
+ 5430              	.LFB421:
+6729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   return htim->Channel;
+ 5431              		.loc 1 6729 1 is_stmt 1 view -0
+ 5432              		.cfi_startproc
+ 5433              		@ args = 0, pretend = 0, frame = 0
+ 5434              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5435              		@ link register save eliminated.
+6730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5436              		.loc 1 6730 3 view .LVU1739
+6731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5437              		.loc 1 6731 1 is_stmt 0 view .LVU1740
+ 5438 0000 007F     		ldrb	r0, [r0, #28]	@ zero_extendqisi2
+ 5439              	.LVL422:
+6731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5440              		.loc 1 6731 1 view .LVU1741
+ 5441 0002 7047     		bx	lr
+ARM GAS  /tmp/cc0wMqvE.s 			page 257
+
+
+ 5442              		.cfi_endproc
+ 5443              	.LFE421:
+ 5445              		.section	.text.HAL_TIM_GetChannelState,"ax",%progbits
+ 5446              		.align	1
+ 5447              		.global	HAL_TIM_GetChannelState
+ 5448              		.syntax unified
+ 5449              		.thumb
+ 5450              		.thumb_func
+ 5452              	HAL_TIM_GetChannelState:
+ 5453              	.LVL423:
+ 5454              	.LFB422:
+6747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_state;
+ 5455              		.loc 1 6747 1 is_stmt 1 view -0
+ 5456              		.cfi_startproc
+ 5457              		@ args = 0, pretend = 0, frame = 0
+ 5458              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5459              		@ link register save eliminated.
+6748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5460              		.loc 1 6748 3 view .LVU1743
+6751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5461              		.loc 1 6751 3 view .LVU1744
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5462              		.loc 1 6753 3 view .LVU1745
+ 5463 0000 1029     		cmp	r1, #16
+ 5464 0002 1ED8     		bhi	.L332
+ 5465 0004 DFE801F0 		tbb	[pc, r1]
+ 5466              	.L334:
+ 5467 0008 09       		.byte	(.L338-.L334)/2
+ 5468 0009 1D       		.byte	(.L332-.L334)/2
+ 5469 000a 1D       		.byte	(.L332-.L334)/2
+ 5470 000b 1D       		.byte	(.L332-.L334)/2
+ 5471 000c 0D       		.byte	(.L337-.L334)/2
+ 5472 000d 1D       		.byte	(.L332-.L334)/2
+ 5473 000e 1D       		.byte	(.L332-.L334)/2
+ 5474 000f 1D       		.byte	(.L332-.L334)/2
+ 5475 0010 11       		.byte	(.L336-.L334)/2
+ 5476 0011 1D       		.byte	(.L332-.L334)/2
+ 5477 0012 1D       		.byte	(.L332-.L334)/2
+ 5478 0013 1D       		.byte	(.L332-.L334)/2
+ 5479 0014 15       		.byte	(.L335-.L334)/2
+ 5480 0015 1D       		.byte	(.L332-.L334)/2
+ 5481 0016 1D       		.byte	(.L332-.L334)/2
+ 5482 0017 1D       		.byte	(.L332-.L334)/2
+ 5483 0018 19       		.byte	(.L333-.L334)/2
+ 5484 0019 00       		.p2align 1
+ 5485              	.L338:
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5486              		.loc 1 6753 19 is_stmt 0 discriminator 1 view .LVU1746
+ 5487 001a 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 5488              	.LVL424:
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5489              		.loc 1 6753 19 discriminator 1 view .LVU1747
+ 5490 001e C0B2     		uxtb	r0, r0
+ 5491 0020 7047     		bx	lr
+ 5492              	.LVL425:
+ 5493              	.L337:
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 258
+
+
+ 5494              		.loc 1 6753 19 discriminator 4 view .LVU1748
+ 5495 0022 90F83F00 		ldrb	r0, [r0, #63]	@ zero_extendqisi2
+ 5496              	.LVL426:
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5497              		.loc 1 6753 19 discriminator 4 view .LVU1749
+ 5498 0026 C0B2     		uxtb	r0, r0
+ 5499 0028 7047     		bx	lr
+ 5500              	.LVL427:
+ 5501              	.L336:
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5502              		.loc 1 6753 19 discriminator 7 view .LVU1750
+ 5503 002a 90F84000 		ldrb	r0, [r0, #64]	@ zero_extendqisi2
+ 5504              	.LVL428:
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5505              		.loc 1 6753 19 discriminator 7 view .LVU1751
+ 5506 002e C0B2     		uxtb	r0, r0
+ 5507 0030 7047     		bx	lr
+ 5508              	.LVL429:
+ 5509              	.L335:
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5510              		.loc 1 6753 19 discriminator 10 view .LVU1752
+ 5511 0032 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 5512              	.LVL430:
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5513              		.loc 1 6753 19 discriminator 10 view .LVU1753
+ 5514 0036 C0B2     		uxtb	r0, r0
+ 5515 0038 7047     		bx	lr
+ 5516              	.LVL431:
+ 5517              	.L333:
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5518              		.loc 1 6753 19 discriminator 13 view .LVU1754
+ 5519 003a 90F84200 		ldrb	r0, [r0, #66]	@ zero_extendqisi2
+ 5520              	.LVL432:
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5521              		.loc 1 6753 19 discriminator 13 view .LVU1755
+ 5522 003e C0B2     		uxtb	r0, r0
+ 5523 0040 7047     		bx	lr
+ 5524              	.LVL433:
+ 5525              	.L332:
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5526              		.loc 1 6753 19 discriminator 14 view .LVU1756
+ 5527 0042 90F84300 		ldrb	r0, [r0, #67]	@ zero_extendqisi2
+ 5528              	.LVL434:
+6753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5529              		.loc 1 6753 19 discriminator 14 view .LVU1757
+ 5530 0046 C0B2     		uxtb	r0, r0
+ 5531              	.LVL435:
+6755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5532              		.loc 1 6755 3 is_stmt 1 discriminator 14 view .LVU1758
+6756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5533              		.loc 1 6756 1 is_stmt 0 discriminator 14 view .LVU1759
+ 5534 0048 7047     		bx	lr
+ 5535              		.cfi_endproc
+ 5536              	.LFE422:
+ 5538              		.section	.text.HAL_TIM_DMABurstState,"ax",%progbits
+ 5539              		.align	1
+ 5540              		.global	HAL_TIM_DMABurstState
+ARM GAS  /tmp/cc0wMqvE.s 			page 259
+
+
+ 5541              		.syntax unified
+ 5542              		.thumb
+ 5543              		.thumb_func
+ 5545              	HAL_TIM_DMABurstState:
+ 5546              	.LVL436:
+ 5547              	.LFB423:
+6764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 5548              		.loc 1 6764 1 is_stmt 1 view -0
+ 5549              		.cfi_startproc
+ 5550              		@ args = 0, pretend = 0, frame = 0
+ 5551              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5552              		@ link register save eliminated.
+6766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5553              		.loc 1 6766 3 view .LVU1761
+6768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5554              		.loc 1 6768 3 view .LVU1762
+6768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5555              		.loc 1 6768 14 is_stmt 0 view .LVU1763
+ 5556 0000 90F84800 		ldrb	r0, [r0, #72]	@ zero_extendqisi2
+ 5557              	.LVL437:
+6769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5558              		.loc 1 6769 1 view .LVU1764
+ 5559 0004 7047     		bx	lr
+ 5560              		.cfi_endproc
+ 5561              	.LFE423:
+ 5563              		.section	.text.TIM_Base_SetConfig,"ax",%progbits
+ 5564              		.align	1
+ 5565              		.global	TIM_Base_SetConfig
+ 5566              		.syntax unified
+ 5567              		.thumb
+ 5568              		.thumb_func
+ 5570              	TIM_Base_SetConfig:
+ 5571              	.LVL438:
+ 5572              	.LFB433:
+7107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpcr1;
+ 5573              		.loc 1 7107 1 is_stmt 1 view -0
+ 5574              		.cfi_startproc
+ 5575              		@ args = 0, pretend = 0, frame = 0
+ 5576              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5577              		@ link register save eliminated.
+7108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpcr1 = TIMx->CR1;
+ 5578              		.loc 1 7108 3 view .LVU1766
+7109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5579              		.loc 1 7109 3 view .LVU1767
+7109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5580              		.loc 1 7109 10 is_stmt 0 view .LVU1768
+ 5581 0000 0368     		ldr	r3, [r0]
+ 5582              	.LVL439:
+7112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5583              		.loc 1 7112 3 is_stmt 1 view .LVU1769
+7112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5584              		.loc 1 7112 6 is_stmt 0 view .LVU1770
+ 5585 0002 2C4A     		ldr	r2, .L348
+ 5586 0004 9042     		cmp	r0, r2
+ 5587 0006 0ED0     		beq	.L342
+7112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5588              		.loc 1 7112 7 discriminator 1 view .LVU1771
+ARM GAS  /tmp/cc0wMqvE.s 			page 260
+
+
+ 5589 0008 B0F1804F 		cmp	r0, #1073741824
+ 5590 000c 0BD0     		beq	.L342
+7112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5591              		.loc 1 7112 7 discriminator 2 view .LVU1772
+ 5592 000e A2F59432 		sub	r2, r2, #75776
+ 5593 0012 9042     		cmp	r0, r2
+ 5594 0014 07D0     		beq	.L342
+7112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5595              		.loc 1 7112 7 discriminator 3 view .LVU1773
+ 5596 0016 02F58062 		add	r2, r2, #1024
+ 5597 001a 9042     		cmp	r0, r2
+ 5598 001c 03D0     		beq	.L342
+7112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5599              		.loc 1 7112 7 discriminator 4 view .LVU1774
+ 5600 001e 02F59632 		add	r2, r2, #76800
+ 5601 0022 9042     		cmp	r0, r2
+ 5602 0024 03D1     		bne	.L343
+ 5603              	.L342:
+7115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr1 |= Structure->CounterMode;
+ 5604              		.loc 1 7115 5 is_stmt 1 view .LVU1775
+7115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr1 |= Structure->CounterMode;
+ 5605              		.loc 1 7115 12 is_stmt 0 view .LVU1776
+ 5606 0026 23F07003 		bic	r3, r3, #112
+ 5607              	.LVL440:
+7116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5608              		.loc 1 7116 5 is_stmt 1 view .LVU1777
+7116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5609              		.loc 1 7116 24 is_stmt 0 view .LVU1778
+ 5610 002a 4A68     		ldr	r2, [r1, #4]
+7116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5611              		.loc 1 7116 12 view .LVU1779
+ 5612 002c 1343     		orrs	r3, r3, r2
+ 5613              	.LVL441:
+ 5614              	.L343:
+7119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5615              		.loc 1 7119 3 is_stmt 1 view .LVU1780
+7119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5616              		.loc 1 7119 6 is_stmt 0 view .LVU1781
+ 5617 002e 214A     		ldr	r2, .L348
+ 5618 0030 9042     		cmp	r0, r2
+ 5619 0032 1AD0     		beq	.L344
+7119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5620              		.loc 1 7119 7 discriminator 1 view .LVU1782
+ 5621 0034 B0F1804F 		cmp	r0, #1073741824
+ 5622 0038 17D0     		beq	.L344
+7119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5623              		.loc 1 7119 7 discriminator 2 view .LVU1783
+ 5624 003a A2F59432 		sub	r2, r2, #75776
+ 5625 003e 9042     		cmp	r0, r2
+ 5626 0040 13D0     		beq	.L344
+7119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5627              		.loc 1 7119 7 discriminator 3 view .LVU1784
+ 5628 0042 02F58062 		add	r2, r2, #1024
+ 5629 0046 9042     		cmp	r0, r2
+ 5630 0048 0FD0     		beq	.L344
+7119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5631              		.loc 1 7119 7 discriminator 4 view .LVU1785
+ARM GAS  /tmp/cc0wMqvE.s 			page 261
+
+
+ 5632 004a 02F59632 		add	r2, r2, #76800
+ 5633 004e 9042     		cmp	r0, r2
+ 5634 0050 0BD0     		beq	.L344
+7119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5635              		.loc 1 7119 7 discriminator 5 view .LVU1786
+ 5636 0052 02F54062 		add	r2, r2, #3072
+ 5637 0056 9042     		cmp	r0, r2
+ 5638 0058 07D0     		beq	.L344
+7119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5639              		.loc 1 7119 7 discriminator 6 view .LVU1787
+ 5640 005a 02F58062 		add	r2, r2, #1024
+ 5641 005e 9042     		cmp	r0, r2
+ 5642 0060 03D0     		beq	.L344
+7119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5643              		.loc 1 7119 7 discriminator 7 view .LVU1788
+ 5644 0062 02F58062 		add	r2, r2, #1024
+ 5645 0066 9042     		cmp	r0, r2
+ 5646 0068 03D1     		bne	.L345
+ 5647              	.L344:
+7122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ 5648              		.loc 1 7122 5 is_stmt 1 view .LVU1789
+7122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ 5649              		.loc 1 7122 12 is_stmt 0 view .LVU1790
+ 5650 006a 23F44073 		bic	r3, r3, #768
+ 5651              	.LVL442:
+7123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5652              		.loc 1 7123 5 is_stmt 1 view .LVU1791
+7123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5653              		.loc 1 7123 34 is_stmt 0 view .LVU1792
+ 5654 006e CA68     		ldr	r2, [r1, #12]
+7123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5655              		.loc 1 7123 12 view .LVU1793
+ 5656 0070 1343     		orrs	r3, r3, r2
+ 5657              	.LVL443:
+ 5658              	.L345:
+7127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5659              		.loc 1 7127 3 is_stmt 1 view .LVU1794
+ 5660 0072 23F08003 		bic	r3, r3, #128
+ 5661              	.LVL444:
+7127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5662              		.loc 1 7127 3 is_stmt 0 view .LVU1795
+ 5663 0076 4A69     		ldr	r2, [r1, #20]
+ 5664 0078 1343     		orrs	r3, r3, r2
+ 5665              	.LVL445:
+7129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5666              		.loc 1 7129 3 is_stmt 1 view .LVU1796
+7129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5667              		.loc 1 7129 13 is_stmt 0 view .LVU1797
+ 5668 007a 0360     		str	r3, [r0]
+7132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5669              		.loc 1 7132 3 is_stmt 1 view .LVU1798
+7132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5670              		.loc 1 7132 34 is_stmt 0 view .LVU1799
+ 5671 007c 8B68     		ldr	r3, [r1, #8]
+ 5672              	.LVL446:
+7132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5673              		.loc 1 7132 13 view .LVU1800
+ARM GAS  /tmp/cc0wMqvE.s 			page 262
+
+
+ 5674 007e C362     		str	r3, [r0, #44]
+ 5675              	.LVL447:
+7135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5676              		.loc 1 7135 3 is_stmt 1 view .LVU1801
+7135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5677              		.loc 1 7135 24 is_stmt 0 view .LVU1802
+ 5678 0080 0B68     		ldr	r3, [r1]
+7135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5679              		.loc 1 7135 13 view .LVU1803
+ 5680 0082 8362     		str	r3, [r0, #40]
+7137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5681              		.loc 1 7137 3 is_stmt 1 view .LVU1804
+7137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5682              		.loc 1 7137 6 is_stmt 0 view .LVU1805
+ 5683 0084 0B4B     		ldr	r3, .L348
+ 5684 0086 9842     		cmp	r0, r3
+ 5685 0088 0FD0     		beq	.L346
+7137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5686              		.loc 1 7137 7 discriminator 1 view .LVU1806
+ 5687 008a 03F50063 		add	r3, r3, #2048
+ 5688 008e 9842     		cmp	r0, r3
+ 5689 0090 0BD0     		beq	.L346
+7137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5690              		.loc 1 7137 7 discriminator 2 view .LVU1807
+ 5691 0092 03F54063 		add	r3, r3, #3072
+ 5692 0096 9842     		cmp	r0, r3
+ 5693 0098 07D0     		beq	.L346
+7137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5694              		.loc 1 7137 7 discriminator 3 view .LVU1808
+ 5695 009a 03F58063 		add	r3, r3, #1024
+ 5696 009e 9842     		cmp	r0, r3
+ 5697 00a0 03D0     		beq	.L346
+7137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5698              		.loc 1 7137 7 discriminator 4 view .LVU1809
+ 5699 00a2 03F58063 		add	r3, r3, #1024
+ 5700 00a6 9842     		cmp	r0, r3
+ 5701 00a8 01D1     		bne	.L347
+ 5702              	.L346:
+7140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5703              		.loc 1 7140 5 is_stmt 1 view .LVU1810
+7140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5704              		.loc 1 7140 26 is_stmt 0 view .LVU1811
+ 5705 00aa 0B69     		ldr	r3, [r1, #16]
+7140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5706              		.loc 1 7140 15 view .LVU1812
+ 5707 00ac 0363     		str	r3, [r0, #48]
+ 5708              	.L347:
+7145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5709              		.loc 1 7145 3 is_stmt 1 view .LVU1813
+7145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5710              		.loc 1 7145 13 is_stmt 0 view .LVU1814
+ 5711 00ae 0123     		movs	r3, #1
+ 5712 00b0 4361     		str	r3, [r0, #20]
+7146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5713              		.loc 1 7146 1 view .LVU1815
+ 5714 00b2 7047     		bx	lr
+ 5715              	.L349:
+ARM GAS  /tmp/cc0wMqvE.s 			page 263
+
+
+ 5716              		.align	2
+ 5717              	.L348:
+ 5718 00b4 002C0140 		.word	1073818624
+ 5719              		.cfi_endproc
+ 5720              	.LFE433:
+ 5722              		.section	.text.HAL_TIM_Base_Init,"ax",%progbits
+ 5723              		.align	1
+ 5724              		.global	HAL_TIM_Base_Init
+ 5725              		.syntax unified
+ 5726              		.thumb
+ 5727              		.thumb_func
+ 5729              	HAL_TIM_Base_Init:
+ 5730              	.LVL448:
+ 5731              	.LFB329:
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5732              		.loc 1 282 1 is_stmt 1 view -0
+ 5733              		.cfi_startproc
+ 5734              		@ args = 0, pretend = 0, frame = 0
+ 5735              		@ frame_needed = 0, uses_anonymous_args = 0
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5736              		.loc 1 284 3 view .LVU1817
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5737              		.loc 1 284 6 is_stmt 0 view .LVU1818
+ 5738 0000 60B3     		cbz	r0, .L353
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5739              		.loc 1 282 1 view .LVU1819
+ 5740 0002 10B5     		push	{r4, lr}
+ 5741              	.LCFI48:
+ 5742              		.cfi_def_cfa_offset 8
+ 5743              		.cfi_offset 4, -8
+ 5744              		.cfi_offset 14, -4
+ 5745 0004 0446     		mov	r4, r0
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 5746              		.loc 1 290 3 is_stmt 1 view .LVU1820
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 5747              		.loc 1 291 3 view .LVU1821
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 5748              		.loc 1 292 3 view .LVU1822
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5749              		.loc 1 293 3 view .LVU1823
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5750              		.loc 1 295 3 view .LVU1824
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5751              		.loc 1 295 11 is_stmt 0 view .LVU1825
+ 5752 0006 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5753              		.loc 1 295 6 view .LVU1826
+ 5754 000a 13B3     		cbz	r3, .L358
+ 5755              	.LVL449:
+ 5756              	.L352:
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5757              		.loc 1 317 3 is_stmt 1 view .LVU1827
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5758              		.loc 1 317 15 is_stmt 0 view .LVU1828
+ 5759 000c 0223     		movs	r3, #2
+ 5760 000e 84F83D30 		strb	r3, [r4, #61]
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 264
+
+
+ 5761              		.loc 1 320 3 is_stmt 1 view .LVU1829
+ 5762 0012 2146     		mov	r1, r4
+ 5763 0014 51F8040B 		ldr	r0, [r1], #4
+ 5764 0018 FFF7FEFF 		bl	TIM_Base_SetConfig
+ 5765              	.LVL450:
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5766              		.loc 1 323 3 view .LVU1830
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5767              		.loc 1 323 23 is_stmt 0 view .LVU1831
+ 5768 001c 0123     		movs	r3, #1
+ 5769 001e 84F84830 		strb	r3, [r4, #72]
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5770              		.loc 1 326 3 is_stmt 1 view .LVU1832
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5771              		.loc 1 326 3 view .LVU1833
+ 5772 0022 84F83E30 		strb	r3, [r4, #62]
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5773              		.loc 1 326 3 view .LVU1834
+ 5774 0026 84F83F30 		strb	r3, [r4, #63]
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5775              		.loc 1 326 3 view .LVU1835
+ 5776 002a 84F84030 		strb	r3, [r4, #64]
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5777              		.loc 1 326 3 view .LVU1836
+ 5778 002e 84F84130 		strb	r3, [r4, #65]
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5779              		.loc 1 326 3 view .LVU1837
+ 5780 0032 84F84230 		strb	r3, [r4, #66]
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5781              		.loc 1 326 3 view .LVU1838
+ 5782 0036 84F84330 		strb	r3, [r4, #67]
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5783              		.loc 1 326 3 view .LVU1839
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5784              		.loc 1 327 3 view .LVU1840
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5785              		.loc 1 327 3 view .LVU1841
+ 5786 003a 84F84430 		strb	r3, [r4, #68]
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5787              		.loc 1 327 3 view .LVU1842
+ 5788 003e 84F84530 		strb	r3, [r4, #69]
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5789              		.loc 1 327 3 view .LVU1843
+ 5790 0042 84F84630 		strb	r3, [r4, #70]
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5791              		.loc 1 327 3 view .LVU1844
+ 5792 0046 84F84730 		strb	r3, [r4, #71]
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5793              		.loc 1 327 3 view .LVU1845
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5794              		.loc 1 330 3 view .LVU1846
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5795              		.loc 1 330 15 is_stmt 0 view .LVU1847
+ 5796 004a 84F83D30 		strb	r3, [r4, #61]
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5797              		.loc 1 332 3 is_stmt 1 view .LVU1848
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ARM GAS  /tmp/cc0wMqvE.s 			page 265
+
+
+ 5798              		.loc 1 332 10 is_stmt 0 view .LVU1849
+ 5799 004e 0020     		movs	r0, #0
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5800              		.loc 1 333 1 view .LVU1850
+ 5801 0050 10BD     		pop	{r4, pc}
+ 5802              	.LVL451:
+ 5803              	.L358:
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5804              		.loc 1 298 5 is_stmt 1 view .LVU1851
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5805              		.loc 1 298 16 is_stmt 0 view .LVU1852
+ 5806 0052 80F83C30 		strb	r3, [r0, #60]
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5807              		.loc 1 312 5 is_stmt 1 view .LVU1853
+ 5808 0056 FFF7FEFF 		bl	HAL_TIM_Base_MspInit
+ 5809              	.LVL452:
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5810              		.loc 1 312 5 is_stmt 0 view .LVU1854
+ 5811 005a D7E7     		b	.L352
+ 5812              	.LVL453:
+ 5813              	.L353:
+ 5814              	.LCFI49:
+ 5815              		.cfi_def_cfa_offset 0
+ 5816              		.cfi_restore 4
+ 5817              		.cfi_restore 14
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5818              		.loc 1 286 12 view .LVU1855
+ 5819 005c 0120     		movs	r0, #1
+ 5820              	.LVL454:
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5821              		.loc 1 333 1 view .LVU1856
+ 5822 005e 7047     		bx	lr
+ 5823              		.cfi_endproc
+ 5824              	.LFE329:
+ 5826              		.section	.text.HAL_TIM_OC_Init,"ax",%progbits
+ 5827              		.align	1
+ 5828              		.global	HAL_TIM_OC_Init
+ 5829              		.syntax unified
+ 5830              		.thumb
+ 5831              		.thumb_func
+ 5833              	HAL_TIM_OC_Init:
+ 5834              	.LVL455:
+ 5835              	.LFB339:
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5836              		.loc 1 665 1 is_stmt 1 view -0
+ 5837              		.cfi_startproc
+ 5838              		@ args = 0, pretend = 0, frame = 0
+ 5839              		@ frame_needed = 0, uses_anonymous_args = 0
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5840              		.loc 1 667 3 view .LVU1858
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5841              		.loc 1 667 6 is_stmt 0 view .LVU1859
+ 5842 0000 60B3     		cbz	r0, .L362
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5843              		.loc 1 665 1 view .LVU1860
+ 5844 0002 10B5     		push	{r4, lr}
+ 5845              	.LCFI50:
+ARM GAS  /tmp/cc0wMqvE.s 			page 266
+
+
+ 5846              		.cfi_def_cfa_offset 8
+ 5847              		.cfi_offset 4, -8
+ 5848              		.cfi_offset 14, -4
+ 5849 0004 0446     		mov	r4, r0
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 5850              		.loc 1 673 3 is_stmt 1 view .LVU1861
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 5851              		.loc 1 674 3 view .LVU1862
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 5852              		.loc 1 675 3 view .LVU1863
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5853              		.loc 1 676 3 view .LVU1864
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5854              		.loc 1 678 3 view .LVU1865
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5855              		.loc 1 678 11 is_stmt 0 view .LVU1866
+ 5856 0006 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5857              		.loc 1 678 6 view .LVU1867
+ 5858 000a 13B3     		cbz	r3, .L367
+ 5859              	.LVL456:
+ 5860              	.L361:
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5861              		.loc 1 700 3 is_stmt 1 view .LVU1868
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5862              		.loc 1 700 15 is_stmt 0 view .LVU1869
+ 5863 000c 0223     		movs	r3, #2
+ 5864 000e 84F83D30 		strb	r3, [r4, #61]
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5865              		.loc 1 703 3 is_stmt 1 view .LVU1870
+ 5866 0012 2146     		mov	r1, r4
+ 5867 0014 51F8040B 		ldr	r0, [r1], #4
+ 5868 0018 FFF7FEFF 		bl	TIM_Base_SetConfig
+ 5869              	.LVL457:
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5870              		.loc 1 706 3 view .LVU1871
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5871              		.loc 1 706 23 is_stmt 0 view .LVU1872
+ 5872 001c 0123     		movs	r3, #1
+ 5873 001e 84F84830 		strb	r3, [r4, #72]
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5874              		.loc 1 709 3 is_stmt 1 view .LVU1873
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5875              		.loc 1 709 3 view .LVU1874
+ 5876 0022 84F83E30 		strb	r3, [r4, #62]
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5877              		.loc 1 709 3 view .LVU1875
+ 5878 0026 84F83F30 		strb	r3, [r4, #63]
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5879              		.loc 1 709 3 view .LVU1876
+ 5880 002a 84F84030 		strb	r3, [r4, #64]
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5881              		.loc 1 709 3 view .LVU1877
+ 5882 002e 84F84130 		strb	r3, [r4, #65]
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5883              		.loc 1 709 3 view .LVU1878
+ 5884 0032 84F84230 		strb	r3, [r4, #66]
+ARM GAS  /tmp/cc0wMqvE.s 			page 267
+
+
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5885              		.loc 1 709 3 view .LVU1879
+ 5886 0036 84F84330 		strb	r3, [r4, #67]
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5887              		.loc 1 709 3 view .LVU1880
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5888              		.loc 1 710 3 view .LVU1881
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5889              		.loc 1 710 3 view .LVU1882
+ 5890 003a 84F84430 		strb	r3, [r4, #68]
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5891              		.loc 1 710 3 view .LVU1883
+ 5892 003e 84F84530 		strb	r3, [r4, #69]
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5893              		.loc 1 710 3 view .LVU1884
+ 5894 0042 84F84630 		strb	r3, [r4, #70]
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5895              		.loc 1 710 3 view .LVU1885
+ 5896 0046 84F84730 		strb	r3, [r4, #71]
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5897              		.loc 1 710 3 view .LVU1886
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5898              		.loc 1 713 3 view .LVU1887
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5899              		.loc 1 713 15 is_stmt 0 view .LVU1888
+ 5900 004a 84F83D30 		strb	r3, [r4, #61]
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5901              		.loc 1 715 3 is_stmt 1 view .LVU1889
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 5902              		.loc 1 715 10 is_stmt 0 view .LVU1890
+ 5903 004e 0020     		movs	r0, #0
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5904              		.loc 1 716 1 view .LVU1891
+ 5905 0050 10BD     		pop	{r4, pc}
+ 5906              	.LVL458:
+ 5907              	.L367:
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5908              		.loc 1 681 5 is_stmt 1 view .LVU1892
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5909              		.loc 1 681 16 is_stmt 0 view .LVU1893
+ 5910 0052 80F83C30 		strb	r3, [r0, #60]
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5911              		.loc 1 695 5 is_stmt 1 view .LVU1894
+ 5912 0056 FFF7FEFF 		bl	HAL_TIM_OC_MspInit
+ 5913              	.LVL459:
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5914              		.loc 1 695 5 is_stmt 0 view .LVU1895
+ 5915 005a D7E7     		b	.L361
+ 5916              	.LVL460:
+ 5917              	.L362:
+ 5918              	.LCFI51:
+ 5919              		.cfi_def_cfa_offset 0
+ 5920              		.cfi_restore 4
+ 5921              		.cfi_restore 14
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 5922              		.loc 1 669 12 view .LVU1896
+ 5923 005c 0120     		movs	r0, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 268
+
+
+ 5924              	.LVL461:
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5925              		.loc 1 716 1 view .LVU1897
+ 5926 005e 7047     		bx	lr
+ 5927              		.cfi_endproc
+ 5928              	.LFE339:
+ 5930              		.section	.text.HAL_TIM_PWM_Init,"ax",%progbits
+ 5931              		.align	1
+ 5932              		.global	HAL_TIM_PWM_Init
+ 5933              		.syntax unified
+ 5934              		.thumb
+ 5935              		.thumb_func
+ 5937              	HAL_TIM_PWM_Init:
+ 5938              	.LVL462:
+ 5939              	.LFB349:
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5940              		.loc 1 1332 1 is_stmt 1 view -0
+ 5941              		.cfi_startproc
+ 5942              		@ args = 0, pretend = 0, frame = 0
+ 5943              		@ frame_needed = 0, uses_anonymous_args = 0
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5944              		.loc 1 1334 3 view .LVU1899
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5945              		.loc 1 1334 6 is_stmt 0 view .LVU1900
+ 5946 0000 60B3     		cbz	r0, .L371
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5947              		.loc 1 1332 1 view .LVU1901
+ 5948 0002 10B5     		push	{r4, lr}
+ 5949              	.LCFI52:
+ 5950              		.cfi_def_cfa_offset 8
+ 5951              		.cfi_offset 4, -8
+ 5952              		.cfi_offset 14, -4
+ 5953 0004 0446     		mov	r4, r0
+1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 5954              		.loc 1 1340 3 is_stmt 1 view .LVU1902
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 5955              		.loc 1 1341 3 view .LVU1903
+1342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 5956              		.loc 1 1342 3 view .LVU1904
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5957              		.loc 1 1343 3 view .LVU1905
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5958              		.loc 1 1345 3 view .LVU1906
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5959              		.loc 1 1345 11 is_stmt 0 view .LVU1907
+ 5960 0006 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 5961              		.loc 1 1345 6 view .LVU1908
+ 5962 000a 13B3     		cbz	r3, .L376
+ 5963              	.LVL463:
+ 5964              	.L370:
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5965              		.loc 1 1367 3 is_stmt 1 view .LVU1909
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5966              		.loc 1 1367 15 is_stmt 0 view .LVU1910
+ 5967 000c 0223     		movs	r3, #2
+ 5968 000e 84F83D30 		strb	r3, [r4, #61]
+ARM GAS  /tmp/cc0wMqvE.s 			page 269
+
+
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5969              		.loc 1 1370 3 is_stmt 1 view .LVU1911
+ 5970 0012 2146     		mov	r1, r4
+ 5971 0014 51F8040B 		ldr	r0, [r1], #4
+ 5972 0018 FFF7FEFF 		bl	TIM_Base_SetConfig
+ 5973              	.LVL464:
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5974              		.loc 1 1373 3 view .LVU1912
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5975              		.loc 1 1373 23 is_stmt 0 view .LVU1913
+ 5976 001c 0123     		movs	r3, #1
+ 5977 001e 84F84830 		strb	r3, [r4, #72]
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5978              		.loc 1 1376 3 is_stmt 1 view .LVU1914
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5979              		.loc 1 1376 3 view .LVU1915
+ 5980 0022 84F83E30 		strb	r3, [r4, #62]
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5981              		.loc 1 1376 3 view .LVU1916
+ 5982 0026 84F83F30 		strb	r3, [r4, #63]
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5983              		.loc 1 1376 3 view .LVU1917
+ 5984 002a 84F84030 		strb	r3, [r4, #64]
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5985              		.loc 1 1376 3 view .LVU1918
+ 5986 002e 84F84130 		strb	r3, [r4, #65]
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5987              		.loc 1 1376 3 view .LVU1919
+ 5988 0032 84F84230 		strb	r3, [r4, #66]
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5989              		.loc 1 1376 3 view .LVU1920
+ 5990 0036 84F84330 		strb	r3, [r4, #67]
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5991              		.loc 1 1376 3 view .LVU1921
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5992              		.loc 1 1377 3 view .LVU1922
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5993              		.loc 1 1377 3 view .LVU1923
+ 5994 003a 84F84430 		strb	r3, [r4, #68]
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5995              		.loc 1 1377 3 view .LVU1924
+ 5996 003e 84F84530 		strb	r3, [r4, #69]
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5997              		.loc 1 1377 3 view .LVU1925
+ 5998 0042 84F84630 		strb	r3, [r4, #70]
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 5999              		.loc 1 1377 3 view .LVU1926
+ 6000 0046 84F84730 		strb	r3, [r4, #71]
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6001              		.loc 1 1377 3 view .LVU1927
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6002              		.loc 1 1380 3 view .LVU1928
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6003              		.loc 1 1380 15 is_stmt 0 view .LVU1929
+ 6004 004a 84F83D30 		strb	r3, [r4, #61]
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 6005              		.loc 1 1382 3 is_stmt 1 view .LVU1930
+ARM GAS  /tmp/cc0wMqvE.s 			page 270
+
+
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 6006              		.loc 1 1382 10 is_stmt 0 view .LVU1931
+ 6007 004e 0020     		movs	r0, #0
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6008              		.loc 1 1383 1 view .LVU1932
+ 6009 0050 10BD     		pop	{r4, pc}
+ 6010              	.LVL465:
+ 6011              	.L376:
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6012              		.loc 1 1348 5 is_stmt 1 view .LVU1933
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6013              		.loc 1 1348 16 is_stmt 0 view .LVU1934
+ 6014 0052 80F83C30 		strb	r3, [r0, #60]
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 6015              		.loc 1 1362 5 is_stmt 1 view .LVU1935
+ 6016 0056 FFF7FEFF 		bl	HAL_TIM_PWM_MspInit
+ 6017              	.LVL466:
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 6018              		.loc 1 1362 5 is_stmt 0 view .LVU1936
+ 6019 005a D7E7     		b	.L370
+ 6020              	.LVL467:
+ 6021              	.L371:
+ 6022              	.LCFI53:
+ 6023              		.cfi_def_cfa_offset 0
+ 6024              		.cfi_restore 4
+ 6025              		.cfi_restore 14
+1336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 6026              		.loc 1 1336 12 view .LVU1937
+ 6027 005c 0120     		movs	r0, #1
+ 6028              	.LVL468:
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6029              		.loc 1 1383 1 view .LVU1938
+ 6030 005e 7047     		bx	lr
+ 6031              		.cfi_endproc
+ 6032              	.LFE349:
+ 6034              		.section	.text.HAL_TIM_IC_Init,"ax",%progbits
+ 6035              		.align	1
+ 6036              		.global	HAL_TIM_IC_Init
+ 6037              		.syntax unified
+ 6038              		.thumb
+ 6039              		.thumb_func
+ 6041              	HAL_TIM_IC_Init:
+ 6042              	.LVL469:
+ 6043              	.LFB359:
+1998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 6044              		.loc 1 1998 1 is_stmt 1 view -0
+ 6045              		.cfi_startproc
+ 6046              		@ args = 0, pretend = 0, frame = 0
+ 6047              		@ frame_needed = 0, uses_anonymous_args = 0
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6048              		.loc 1 2000 3 view .LVU1940
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6049              		.loc 1 2000 6 is_stmt 0 view .LVU1941
+ 6050 0000 60B3     		cbz	r0, .L380
+1998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 6051              		.loc 1 1998 1 view .LVU1942
+ 6052 0002 10B5     		push	{r4, lr}
+ARM GAS  /tmp/cc0wMqvE.s 			page 271
+
+
+ 6053              	.LCFI54:
+ 6054              		.cfi_def_cfa_offset 8
+ 6055              		.cfi_offset 4, -8
+ 6056              		.cfi_offset 14, -4
+ 6057 0004 0446     		mov	r4, r0
+2006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 6058              		.loc 1 2006 3 is_stmt 1 view .LVU1943
+2007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 6059              		.loc 1 2007 3 view .LVU1944
+2008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 6060              		.loc 1 2008 3 view .LVU1945
+2009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6061              		.loc 1 2009 3 view .LVU1946
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6062              		.loc 1 2011 3 view .LVU1947
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6063              		.loc 1 2011 11 is_stmt 0 view .LVU1948
+ 6064 0006 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6065              		.loc 1 2011 6 view .LVU1949
+ 6066 000a 13B3     		cbz	r3, .L385
+ 6067              	.LVL470:
+ 6068              	.L379:
+2033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6069              		.loc 1 2033 3 is_stmt 1 view .LVU1950
+2033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6070              		.loc 1 2033 15 is_stmt 0 view .LVU1951
+ 6071 000c 0223     		movs	r3, #2
+ 6072 000e 84F83D30 		strb	r3, [r4, #61]
+2036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6073              		.loc 1 2036 3 is_stmt 1 view .LVU1952
+ 6074 0012 2146     		mov	r1, r4
+ 6075 0014 51F8040B 		ldr	r0, [r1], #4
+ 6076 0018 FFF7FEFF 		bl	TIM_Base_SetConfig
+ 6077              	.LVL471:
+2039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6078              		.loc 1 2039 3 view .LVU1953
+2039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6079              		.loc 1 2039 23 is_stmt 0 view .LVU1954
+ 6080 001c 0123     		movs	r3, #1
+ 6081 001e 84F84830 		strb	r3, [r4, #72]
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 6082              		.loc 1 2042 3 is_stmt 1 view .LVU1955
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 6083              		.loc 1 2042 3 view .LVU1956
+ 6084 0022 84F83E30 		strb	r3, [r4, #62]
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 6085              		.loc 1 2042 3 view .LVU1957
+ 6086 0026 84F83F30 		strb	r3, [r4, #63]
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 6087              		.loc 1 2042 3 view .LVU1958
+ 6088 002a 84F84030 		strb	r3, [r4, #64]
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 6089              		.loc 1 2042 3 view .LVU1959
+ 6090 002e 84F84130 		strb	r3, [r4, #65]
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 6091              		.loc 1 2042 3 view .LVU1960
+ARM GAS  /tmp/cc0wMqvE.s 			page 272
+
+
+ 6092 0032 84F84230 		strb	r3, [r4, #66]
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 6093              		.loc 1 2042 3 view .LVU1961
+ 6094 0036 84F84330 		strb	r3, [r4, #67]
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 6095              		.loc 1 2042 3 view .LVU1962
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6096              		.loc 1 2043 3 view .LVU1963
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6097              		.loc 1 2043 3 view .LVU1964
+ 6098 003a 84F84430 		strb	r3, [r4, #68]
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6099              		.loc 1 2043 3 view .LVU1965
+ 6100 003e 84F84530 		strb	r3, [r4, #69]
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6101              		.loc 1 2043 3 view .LVU1966
+ 6102 0042 84F84630 		strb	r3, [r4, #70]
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6103              		.loc 1 2043 3 view .LVU1967
+ 6104 0046 84F84730 		strb	r3, [r4, #71]
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6105              		.loc 1 2043 3 view .LVU1968
+2046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6106              		.loc 1 2046 3 view .LVU1969
+2046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6107              		.loc 1 2046 15 is_stmt 0 view .LVU1970
+ 6108 004a 84F83D30 		strb	r3, [r4, #61]
+2048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 6109              		.loc 1 2048 3 is_stmt 1 view .LVU1971
+2048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 6110              		.loc 1 2048 10 is_stmt 0 view .LVU1972
+ 6111 004e 0020     		movs	r0, #0
+2049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6112              		.loc 1 2049 1 view .LVU1973
+ 6113 0050 10BD     		pop	{r4, pc}
+ 6114              	.LVL472:
+ 6115              	.L385:
+2014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6116              		.loc 1 2014 5 is_stmt 1 view .LVU1974
+2014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6117              		.loc 1 2014 16 is_stmt 0 view .LVU1975
+ 6118 0052 80F83C30 		strb	r3, [r0, #60]
+2028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 6119              		.loc 1 2028 5 is_stmt 1 view .LVU1976
+ 6120 0056 FFF7FEFF 		bl	HAL_TIM_IC_MspInit
+ 6121              	.LVL473:
+2028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 6122              		.loc 1 2028 5 is_stmt 0 view .LVU1977
+ 6123 005a D7E7     		b	.L379
+ 6124              	.LVL474:
+ 6125              	.L380:
+ 6126              	.LCFI55:
+ 6127              		.cfi_def_cfa_offset 0
+ 6128              		.cfi_restore 4
+ 6129              		.cfi_restore 14
+2002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 6130              		.loc 1 2002 12 view .LVU1978
+ARM GAS  /tmp/cc0wMqvE.s 			page 273
+
+
+ 6131 005c 0120     		movs	r0, #1
+ 6132              	.LVL475:
+2049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6133              		.loc 1 2049 1 view .LVU1979
+ 6134 005e 7047     		bx	lr
+ 6135              		.cfi_endproc
+ 6136              	.LFE359:
+ 6138              		.section	.text.HAL_TIM_OnePulse_Init,"ax",%progbits
+ 6139              		.align	1
+ 6140              		.global	HAL_TIM_OnePulse_Init
+ 6141              		.syntax unified
+ 6142              		.thumb
+ 6143              		.thumb_func
+ 6145              	HAL_TIM_OnePulse_Init:
+ 6146              	.LVL476:
+ 6147              	.LFB369:
+2646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 6148              		.loc 1 2646 1 is_stmt 1 view -0
+ 6149              		.cfi_startproc
+ 6150              		@ args = 0, pretend = 0, frame = 0
+ 6151              		@ frame_needed = 0, uses_anonymous_args = 0
+2648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6152              		.loc 1 2648 3 view .LVU1981
+2648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6153              		.loc 1 2648 6 is_stmt 0 view .LVU1982
+ 6154 0000 50B3     		cbz	r0, .L389
+2646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 6155              		.loc 1 2646 1 view .LVU1983
+ 6156 0002 38B5     		push	{r3, r4, r5, lr}
+ 6157              	.LCFI56:
+ 6158              		.cfi_def_cfa_offset 16
+ 6159              		.cfi_offset 3, -16
+ 6160              		.cfi_offset 4, -12
+ 6161              		.cfi_offset 5, -8
+ 6162              		.cfi_offset 14, -4
+ 6163 0004 0D46     		mov	r5, r1
+ 6164 0006 0446     		mov	r4, r0
+2654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 6165              		.loc 1 2654 3 is_stmt 1 view .LVU1984
+2655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 6166              		.loc 1 2655 3 view .LVU1985
+2656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+ 6167              		.loc 1 2656 3 view .LVU1986
+2657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 6168              		.loc 1 2657 3 view .LVU1987
+2658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6169              		.loc 1 2658 3 view .LVU1988
+2660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6170              		.loc 1 2660 3 view .LVU1989
+2660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6171              		.loc 1 2660 11 is_stmt 0 view .LVU1990
+ 6172 0008 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+2660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6173              		.loc 1 2660 6 view .LVU1991
+ 6174 000c FBB1     		cbz	r3, .L394
+ 6175              	.LVL477:
+ 6176              	.L388:
+ARM GAS  /tmp/cc0wMqvE.s 			page 274
+
+
+2682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6177              		.loc 1 2682 3 is_stmt 1 view .LVU1992
+2682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6178              		.loc 1 2682 15 is_stmt 0 view .LVU1993
+ 6179 000e 0223     		movs	r3, #2
+ 6180 0010 84F83D30 		strb	r3, [r4, #61]
+2685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6181              		.loc 1 2685 3 is_stmt 1 view .LVU1994
+ 6182 0014 2146     		mov	r1, r4
+ 6183 0016 51F8040B 		ldr	r0, [r1], #4
+ 6184 001a FFF7FEFF 		bl	TIM_Base_SetConfig
+ 6185              	.LVL478:
+2688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6186              		.loc 1 2688 3 view .LVU1995
+2688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6187              		.loc 1 2688 7 is_stmt 0 view .LVU1996
+ 6188 001e 2268     		ldr	r2, [r4]
+2688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6189              		.loc 1 2688 17 view .LVU1997
+ 6190 0020 1368     		ldr	r3, [r2]
+2688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6191              		.loc 1 2688 23 view .LVU1998
+ 6192 0022 23F00803 		bic	r3, r3, #8
+ 6193 0026 1360     		str	r3, [r2]
+2691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6194              		.loc 1 2691 3 is_stmt 1 view .LVU1999
+2691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6195              		.loc 1 2691 7 is_stmt 0 view .LVU2000
+ 6196 0028 2268     		ldr	r2, [r4]
+2691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6197              		.loc 1 2691 17 view .LVU2001
+ 6198 002a 1368     		ldr	r3, [r2]
+2691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6199              		.loc 1 2691 23 view .LVU2002
+ 6200 002c 2B43     		orrs	r3, r3, r5
+ 6201 002e 1360     		str	r3, [r2]
+2694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6202              		.loc 1 2694 3 is_stmt 1 view .LVU2003
+2694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6203              		.loc 1 2694 23 is_stmt 0 view .LVU2004
+ 6204 0030 0123     		movs	r3, #1
+ 6205 0032 84F84830 		strb	r3, [r4, #72]
+2697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 6206              		.loc 1 2697 3 is_stmt 1 view .LVU2005
+ 6207 0036 84F83E30 		strb	r3, [r4, #62]
+2698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 6208              		.loc 1 2698 3 view .LVU2006
+ 6209 003a 84F83F30 		strb	r3, [r4, #63]
+2699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 6210              		.loc 1 2699 3 view .LVU2007
+ 6211 003e 84F84430 		strb	r3, [r4, #68]
+2700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6212              		.loc 1 2700 3 view .LVU2008
+ 6213 0042 84F84530 		strb	r3, [r4, #69]
+2703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6214              		.loc 1 2703 3 view .LVU2009
+2703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 275
+
+
+ 6215              		.loc 1 2703 15 is_stmt 0 view .LVU2010
+ 6216 0046 84F83D30 		strb	r3, [r4, #61]
+2705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 6217              		.loc 1 2705 3 is_stmt 1 view .LVU2011
+2705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 6218              		.loc 1 2705 10 is_stmt 0 view .LVU2012
+ 6219 004a 0020     		movs	r0, #0
+2706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6220              		.loc 1 2706 1 view .LVU2013
+ 6221 004c 38BD     		pop	{r3, r4, r5, pc}
+ 6222              	.LVL479:
+ 6223              	.L394:
+2663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6224              		.loc 1 2663 5 is_stmt 1 view .LVU2014
+2663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6225              		.loc 1 2663 16 is_stmt 0 view .LVU2015
+ 6226 004e 80F83C30 		strb	r3, [r0, #60]
+2677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 6227              		.loc 1 2677 5 is_stmt 1 view .LVU2016
+ 6228 0052 FFF7FEFF 		bl	HAL_TIM_OnePulse_MspInit
+ 6229              	.LVL480:
+2677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 6230              		.loc 1 2677 5 is_stmt 0 view .LVU2017
+ 6231 0056 DAE7     		b	.L388
+ 6232              	.LVL481:
+ 6233              	.L389:
+ 6234              	.LCFI57:
+ 6235              		.cfi_def_cfa_offset 0
+ 6236              		.cfi_restore 3
+ 6237              		.cfi_restore 4
+ 6238              		.cfi_restore 5
+ 6239              		.cfi_restore 14
+2650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 6240              		.loc 1 2650 12 view .LVU2018
+ 6241 0058 0120     		movs	r0, #1
+ 6242              	.LVL482:
+2706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6243              		.loc 1 2706 1 view .LVU2019
+ 6244 005a 7047     		bx	lr
+ 6245              		.cfi_endproc
+ 6246              	.LFE369:
+ 6248              		.section	.text.HAL_TIM_Encoder_Init,"ax",%progbits
+ 6249              		.align	1
+ 6250              		.global	HAL_TIM_Encoder_Init
+ 6251              		.syntax unified
+ 6252              		.thumb
+ 6253              		.thumb_func
+ 6255              	HAL_TIM_Encoder_Init:
+ 6256              	.LVL483:
+ 6257              	.LFB377:
+3036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 6258              		.loc 1 3036 1 is_stmt 1 view -0
+ 6259              		.cfi_startproc
+ 6260              		@ args = 0, pretend = 0, frame = 0
+ 6261              		@ frame_needed = 0, uses_anonymous_args = 0
+3037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 6262              		.loc 1 3037 3 view .LVU2021
+ARM GAS  /tmp/cc0wMqvE.s 			page 276
+
+
+3038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ 6263              		.loc 1 3038 3 view .LVU2022
+3039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6264              		.loc 1 3039 3 view .LVU2023
+3042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6265              		.loc 1 3042 3 view .LVU2024
+3042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6266              		.loc 1 3042 6 is_stmt 0 view .LVU2025
+ 6267 0000 0028     		cmp	r0, #0
+ 6268 0002 53D0     		beq	.L398
+3036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 6269              		.loc 1 3036 1 view .LVU2026
+ 6270 0004 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 6271              	.LCFI58:
+ 6272              		.cfi_def_cfa_offset 24
+ 6273              		.cfi_offset 3, -24
+ 6274              		.cfi_offset 4, -20
+ 6275              		.cfi_offset 5, -16
+ 6276              		.cfi_offset 6, -12
+ 6277              		.cfi_offset 7, -8
+ 6278              		.cfi_offset 14, -4
+ 6279 0006 0D46     		mov	r5, r1
+ 6280 0008 0446     		mov	r4, r0
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 6281              		.loc 1 3048 3 is_stmt 1 view .LVU2027
+3049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 6282              		.loc 1 3049 3 view .LVU2028
+3050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 6283              		.loc 1 3050 3 view .LVU2029
+3051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+ 6284              		.loc 1 3051 3 view .LVU2030
+3052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+ 6285              		.loc 1 3052 3 view .LVU2031
+3053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+ 6286              		.loc 1 3053 3 view .LVU2032
+3054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+ 6287              		.loc 1 3054 3 view .LVU2033
+3055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+ 6288              		.loc 1 3055 3 view .LVU2034
+3056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ 6289              		.loc 1 3056 3 view .LVU2035
+3057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ 6290              		.loc 1 3057 3 view .LVU2036
+3058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ 6291              		.loc 1 3058 3 view .LVU2037
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+ 6292              		.loc 1 3059 3 view .LVU2038
+3060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6293              		.loc 1 3060 3 view .LVU2039
+3062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6294              		.loc 1 3062 3 view .LVU2040
+3062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6295              		.loc 1 3062 11 is_stmt 0 view .LVU2041
+ 6296 000a 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+3062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6297              		.loc 1 3062 6 view .LVU2042
+ 6298 000e 002B     		cmp	r3, #0
+ARM GAS  /tmp/cc0wMqvE.s 			page 277
+
+
+ 6299 0010 47D0     		beq	.L403
+ 6300              	.LVL484:
+ 6301              	.L397:
+3084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6302              		.loc 1 3084 3 is_stmt 1 view .LVU2043
+3084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6303              		.loc 1 3084 15 is_stmt 0 view .LVU2044
+ 6304 0012 0223     		movs	r3, #2
+ 6305 0014 84F83D30 		strb	r3, [r4, #61]
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6306              		.loc 1 3087 3 is_stmt 1 view .LVU2045
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6307              		.loc 1 3087 7 is_stmt 0 view .LVU2046
+ 6308 0018 2268     		ldr	r2, [r4]
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6309              		.loc 1 3087 17 view .LVU2047
+ 6310 001a 9368     		ldr	r3, [r2, #8]
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6311              		.loc 1 3087 24 view .LVU2048
+ 6312 001c 23F4A033 		bic	r3, r3, #81920
+ 6313 0020 23F00703 		bic	r3, r3, #7
+ 6314 0024 9360     		str	r3, [r2, #8]
+3090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6315              		.loc 1 3090 3 is_stmt 1 view .LVU2049
+ 6316 0026 2146     		mov	r1, r4
+ 6317 0028 51F8040B 		ldr	r0, [r1], #4
+ 6318 002c FFF7FEFF 		bl	TIM_Base_SetConfig
+ 6319              	.LVL485:
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6320              		.loc 1 3093 3 view .LVU2050
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6321              		.loc 1 3093 17 is_stmt 0 view .LVU2051
+ 6322 0030 2168     		ldr	r1, [r4]
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6323              		.loc 1 3093 11 view .LVU2052
+ 6324 0032 8B68     		ldr	r3, [r1, #8]
+ 6325              	.LVL486:
+3096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6326              		.loc 1 3096 3 is_stmt 1 view .LVU2053
+3096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6327              		.loc 1 3096 12 is_stmt 0 view .LVU2054
+ 6328 0034 8A69     		ldr	r2, [r1, #24]
+ 6329              	.LVL487:
+3099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6330              		.loc 1 3099 3 is_stmt 1 view .LVU2055
+3099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6331              		.loc 1 3099 11 is_stmt 0 view .LVU2056
+ 6332 0036 0E6A     		ldr	r6, [r1, #32]
+ 6333              	.LVL488:
+3102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6334              		.loc 1 3102 3 is_stmt 1 view .LVU2057
+3102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6335              		.loc 1 3102 21 is_stmt 0 view .LVU2058
+ 6336 0038 2868     		ldr	r0, [r5]
+3102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6337              		.loc 1 3102 11 view .LVU2059
+ 6338 003a 1843     		orrs	r0, r0, r3
+ARM GAS  /tmp/cc0wMqvE.s 			page 278
+
+
+ 6339              	.LVL489:
+3105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+ 6340              		.loc 1 3105 3 is_stmt 1 view .LVU2060
+3105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+ 6341              		.loc 1 3105 12 is_stmt 0 view .LVU2061
+ 6342 003c 22F44072 		bic	r2, r2, #768
+ 6343              	.LVL490:
+3105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+ 6344              		.loc 1 3105 12 view .LVU2062
+ 6345 0040 22F00302 		bic	r2, r2, #3
+ 6346              	.LVL491:
+3106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6347              		.loc 1 3106 3 is_stmt 1 view .LVU2063
+3106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6348              		.loc 1 3106 23 is_stmt 0 view .LVU2064
+ 6349 0044 AB68     		ldr	r3, [r5, #8]
+3106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6350              		.loc 1 3106 38 view .LVU2065
+ 6351 0046 AF69     		ldr	r7, [r5, #24]
+ 6352 0048 43EA0723 		orr	r3, r3, r7, lsl #8
+3106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6353              		.loc 1 3106 12 view .LVU2066
+ 6354 004c 1343     		orrs	r3, r3, r2
+ 6355              	.LVL492:
+3109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ 6356              		.loc 1 3109 3 is_stmt 1 view .LVU2067
+3110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ 6357              		.loc 1 3110 3 view .LVU2068
+3110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ 6358              		.loc 1 3110 12 is_stmt 0 view .LVU2069
+ 6359 004e 23F47C43 		bic	r3, r3, #64512
+ 6360              	.LVL493:
+3110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ 6361              		.loc 1 3110 12 view .LVU2070
+ 6362 0052 23F0FC03 		bic	r3, r3, #252
+ 6363              	.LVL494:
+3111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 6364              		.loc 1 3111 3 is_stmt 1 view .LVU2071
+3111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 6365              		.loc 1 3111 22 is_stmt 0 view .LVU2072
+ 6366 0056 EA68     		ldr	r2, [r5, #12]
+3111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 6367              		.loc 1 3111 37 view .LVU2073
+ 6368 0058 EF69     		ldr	r7, [r5, #28]
+ 6369 005a 42EA0722 		orr	r2, r2, r7, lsl #8
+3111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 6370              		.loc 1 3111 12 view .LVU2074
+ 6371 005e 1A43     		orrs	r2, r2, r3
+ 6372              	.LVL495:
+3112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6373              		.loc 1 3112 3 is_stmt 1 view .LVU2075
+3112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6374              		.loc 1 3112 52 is_stmt 0 view .LVU2076
+ 6375 0060 2B6A     		ldr	r3, [r5, #32]
+3112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6376              		.loc 1 3112 64 view .LVU2077
+ 6377 0062 1B03     		lsls	r3, r3, #12
+ARM GAS  /tmp/cc0wMqvE.s 			page 279
+
+
+3112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6378              		.loc 1 3112 42 view .LVU2078
+ 6379 0064 2F69     		ldr	r7, [r5, #16]
+ 6380 0066 43EA0713 		orr	r3, r3, r7, lsl #4
+3112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6381              		.loc 1 3112 12 view .LVU2079
+ 6382 006a 1343     		orrs	r3, r3, r2
+ 6383              	.LVL496:
+3115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ 6384              		.loc 1 3115 3 is_stmt 1 view .LVU2080
+3116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+ 6385              		.loc 1 3116 3 view .LVU2081
+3116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+ 6386              		.loc 1 3116 11 is_stmt 0 view .LVU2082
+ 6387 006c 26F0AA06 		bic	r6, r6, #170
+ 6388              	.LVL497:
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6389              		.loc 1 3117 3 is_stmt 1 view .LVU2083
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6390              		.loc 1 3117 21 is_stmt 0 view .LVU2084
+ 6391 0070 6A68     		ldr	r2, [r5, #4]
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6392              		.loc 1 3117 45 view .LVU2085
+ 6393 0072 6D69     		ldr	r5, [r5, #20]
+ 6394              	.LVL498:
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6395              		.loc 1 3117 35 view .LVU2086
+ 6396 0074 42EA0512 		orr	r2, r2, r5, lsl #4
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6397              		.loc 1 3117 11 view .LVU2087
+ 6398 0078 3243     		orrs	r2, r2, r6
+ 6399              	.LVL499:
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6400              		.loc 1 3120 3 is_stmt 1 view .LVU2088
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6401              		.loc 1 3120 24 is_stmt 0 view .LVU2089
+ 6402 007a 8860     		str	r0, [r1, #8]
+3123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6403              		.loc 1 3123 3 is_stmt 1 view .LVU2090
+3123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6404              		.loc 1 3123 7 is_stmt 0 view .LVU2091
+ 6405 007c 2168     		ldr	r1, [r4]
+3123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6406              		.loc 1 3123 25 view .LVU2092
+ 6407 007e 8B61     		str	r3, [r1, #24]
+3126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6408              		.loc 1 3126 3 is_stmt 1 view .LVU2093
+3126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6409              		.loc 1 3126 7 is_stmt 0 view .LVU2094
+ 6410 0080 2368     		ldr	r3, [r4]
+ 6411              	.LVL500:
+3126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6412              		.loc 1 3126 24 view .LVU2095
+ 6413 0082 1A62     		str	r2, [r3, #32]
+ 6414              	.LVL501:
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6415              		.loc 1 3129 3 is_stmt 1 view .LVU2096
+ARM GAS  /tmp/cc0wMqvE.s 			page 280
+
+
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6416              		.loc 1 3129 23 is_stmt 0 view .LVU2097
+ 6417 0084 0123     		movs	r3, #1
+ 6418 0086 84F84830 		strb	r3, [r4, #72]
+3132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 6419              		.loc 1 3132 3 is_stmt 1 view .LVU2098
+ 6420 008a 84F83E30 		strb	r3, [r4, #62]
+3133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 6421              		.loc 1 3133 3 view .LVU2099
+ 6422 008e 84F83F30 		strb	r3, [r4, #63]
+3134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 6423              		.loc 1 3134 3 view .LVU2100
+ 6424 0092 84F84430 		strb	r3, [r4, #68]
+3135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6425              		.loc 1 3135 3 view .LVU2101
+ 6426 0096 84F84530 		strb	r3, [r4, #69]
+3138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6427              		.loc 1 3138 3 view .LVU2102
+3138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6428              		.loc 1 3138 15 is_stmt 0 view .LVU2103
+ 6429 009a 84F83D30 		strb	r3, [r4, #61]
+3140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 6430              		.loc 1 3140 3 is_stmt 1 view .LVU2104
+3140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 6431              		.loc 1 3140 10 is_stmt 0 view .LVU2105
+ 6432 009e 0020     		movs	r0, #0
+ 6433              	.LVL502:
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6434              		.loc 1 3141 1 view .LVU2106
+ 6435 00a0 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 6436              	.LVL503:
+ 6437              	.L403:
+3065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6438              		.loc 1 3065 5 is_stmt 1 view .LVU2107
+3065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6439              		.loc 1 3065 16 is_stmt 0 view .LVU2108
+ 6440 00a2 80F83C30 		strb	r3, [r0, #60]
+3079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 6441              		.loc 1 3079 5 is_stmt 1 view .LVU2109
+ 6442 00a6 FFF7FEFF 		bl	HAL_TIM_Encoder_MspInit
+ 6443              	.LVL504:
+3079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 6444              		.loc 1 3079 5 is_stmt 0 view .LVU2110
+ 6445 00aa B2E7     		b	.L397
+ 6446              	.LVL505:
+ 6447              	.L398:
+ 6448              	.LCFI59:
+ 6449              		.cfi_def_cfa_offset 0
+ 6450              		.cfi_restore 3
+ 6451              		.cfi_restore 4
+ 6452              		.cfi_restore 5
+ 6453              		.cfi_restore 6
+ 6454              		.cfi_restore 7
+ 6455              		.cfi_restore 14
+3044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 6456              		.loc 1 3044 12 view .LVU2111
+ 6457 00ac 0120     		movs	r0, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 281
+
+
+ 6458              	.LVL506:
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6459              		.loc 1 3141 1 view .LVU2112
+ 6460 00ae 7047     		bx	lr
+ 6461              		.cfi_endproc
+ 6462              	.LFE377:
+ 6464              		.section	.text.TIM_OC2_SetConfig,"ax",%progbits
+ 6465              		.align	1
+ 6466              		.global	TIM_OC2_SetConfig
+ 6467              		.syntax unified
+ 6468              		.thumb
+ 6469              		.thumb_func
+ 6471              	TIM_OC2_SetConfig:
+ 6472              	.LVL507:
+ 6473              	.LFB435:
+7230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmrx;
+ 6474              		.loc 1 7230 1 is_stmt 1 view -0
+ 6475              		.cfi_startproc
+ 6476              		@ args = 0, pretend = 0, frame = 0
+ 6477              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6478              		@ link register save eliminated.
+7230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmrx;
+ 6479              		.loc 1 7230 1 is_stmt 0 view .LVU2114
+ 6480 0000 30B4     		push	{r4, r5}
+ 6481              	.LCFI60:
+ 6482              		.cfi_def_cfa_offset 8
+ 6483              		.cfi_offset 4, -8
+ 6484              		.cfi_offset 5, -4
+7231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ 6485              		.loc 1 7231 3 is_stmt 1 view .LVU2115
+7232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpcr2;
+ 6486              		.loc 1 7232 3 view .LVU2116
+7233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6487              		.loc 1 7233 3 view .LVU2117
+7236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6488              		.loc 1 7236 3 view .LVU2118
+7236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6489              		.loc 1 7236 7 is_stmt 0 view .LVU2119
+ 6490 0002 036A     		ldr	r3, [r0, #32]
+7236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6491              		.loc 1 7236 14 view .LVU2120
+ 6492 0004 23F01003 		bic	r3, r3, #16
+ 6493 0008 0362     		str	r3, [r0, #32]
+7239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+ 6494              		.loc 1 7239 3 is_stmt 1 view .LVU2121
+7239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+ 6495              		.loc 1 7239 11 is_stmt 0 view .LVU2122
+ 6496 000a 036A     		ldr	r3, [r0, #32]
+ 6497              	.LVL508:
+7241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6498              		.loc 1 7241 3 is_stmt 1 view .LVU2123
+7241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6499              		.loc 1 7241 10 is_stmt 0 view .LVU2124
+ 6500 000c 4468     		ldr	r4, [r0, #4]
+ 6501              	.LVL509:
+7244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6502              		.loc 1 7244 3 is_stmt 1 view .LVU2125
+ARM GAS  /tmp/cc0wMqvE.s 			page 282
+
+
+7244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6503              		.loc 1 7244 12 is_stmt 0 view .LVU2126
+ 6504 000e 8269     		ldr	r2, [r0, #24]
+ 6505              	.LVL510:
+7247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR1_CC2S;
+ 6506              		.loc 1 7247 3 is_stmt 1 view .LVU2127
+7248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6507              		.loc 1 7248 3 view .LVU2128
+7248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6508              		.loc 1 7248 12 is_stmt 0 view .LVU2129
+ 6509 0010 22F08072 		bic	r2, r2, #16777216
+ 6510              	.LVL511:
+7248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6511              		.loc 1 7248 12 view .LVU2130
+ 6512 0014 22F4E642 		bic	r2, r2, #29440
+ 6513              	.LVL512:
+7251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6514              		.loc 1 7251 3 is_stmt 1 view .LVU2131
+7251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6515              		.loc 1 7251 25 is_stmt 0 view .LVU2132
+ 6516 0018 0D68     		ldr	r5, [r1]
+7251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6517              		.loc 1 7251 12 view .LVU2133
+ 6518 001a 42EA0522 		orr	r2, r2, r5, lsl #8
+ 6519              	.LVL513:
+7254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+ 6520              		.loc 1 7254 3 is_stmt 1 view .LVU2134
+7254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+ 6521              		.loc 1 7254 11 is_stmt 0 view .LVU2135
+ 6522 001e 23F02003 		bic	r3, r3, #32
+ 6523              	.LVL514:
+7256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6524              		.loc 1 7256 3 is_stmt 1 view .LVU2136
+7256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6525              		.loc 1 7256 24 is_stmt 0 view .LVU2137
+ 6526 0022 8D68     		ldr	r5, [r1, #8]
+7256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6527              		.loc 1 7256 11 view .LVU2138
+ 6528 0024 43EA0513 		orr	r3, r3, r5, lsl #4
+ 6529              	.LVL515:
+7258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6530              		.loc 1 7258 3 is_stmt 1 view .LVU2139
+7258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6531              		.loc 1 7258 6 is_stmt 0 view .LVU2140
+ 6532 0028 174D     		ldr	r5, .L410
+ 6533 002a A842     		cmp	r0, r5
+ 6534 002c 03D0     		beq	.L405
+7258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6535              		.loc 1 7258 7 discriminator 1 view .LVU2141
+ 6536 002e 05F50065 		add	r5, r5, #2048
+ 6537 0032 A842     		cmp	r0, r5
+ 6538 0034 06D1     		bne	.L406
+ 6539              	.L405:
+7260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6540              		.loc 1 7260 5 is_stmt 1 view .LVU2142
+7263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Polarity */
+ 6541              		.loc 1 7263 5 view .LVU2143
+ARM GAS  /tmp/cc0wMqvE.s 			page 283
+
+
+7263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Polarity */
+ 6542              		.loc 1 7263 13 is_stmt 0 view .LVU2144
+ 6543 0036 23F08003 		bic	r3, r3, #128
+ 6544              	.LVL516:
+7265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output N State */
+ 6545              		.loc 1 7265 5 is_stmt 1 view .LVU2145
+7265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output N State */
+ 6546              		.loc 1 7265 26 is_stmt 0 view .LVU2146
+ 6547 003a CD68     		ldr	r5, [r1, #12]
+7265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Reset the Output N State */
+ 6548              		.loc 1 7265 13 view .LVU2147
+ 6549 003c 43EA0513 		orr	r3, r3, r5, lsl #4
+ 6550              	.LVL517:
+7267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6551              		.loc 1 7267 5 is_stmt 1 view .LVU2148
+7267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6552              		.loc 1 7267 13 is_stmt 0 view .LVU2149
+ 6553 0040 23F04003 		bic	r3, r3, #64
+ 6554              	.LVL518:
+ 6555              	.L406:
+7271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6556              		.loc 1 7271 3 is_stmt 1 view .LVU2150
+7271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6557              		.loc 1 7271 6 is_stmt 0 view .LVU2151
+ 6558 0044 104D     		ldr	r5, .L410
+ 6559 0046 A842     		cmp	r0, r5
+ 6560 0048 0FD0     		beq	.L407
+7271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6561              		.loc 1 7271 7 discriminator 1 view .LVU2152
+ 6562 004a 05F50065 		add	r5, r5, #2048
+ 6563 004e A842     		cmp	r0, r5
+ 6564 0050 0BD0     		beq	.L407
+7271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6565              		.loc 1 7271 7 discriminator 2 view .LVU2153
+ 6566 0052 05F54065 		add	r5, r5, #3072
+ 6567 0056 A842     		cmp	r0, r5
+ 6568 0058 07D0     		beq	.L407
+7271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6569              		.loc 1 7271 7 discriminator 3 view .LVU2154
+ 6570 005a 05F58065 		add	r5, r5, #1024
+ 6571 005e A842     		cmp	r0, r5
+ 6572 0060 03D0     		beq	.L407
+7271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6573              		.loc 1 7271 7 discriminator 4 view .LVU2155
+ 6574 0062 05F58065 		add	r5, r5, #1024
+ 6575 0066 A842     		cmp	r0, r5
+ 6576 0068 07D1     		bne	.L408
+ 6577              	.L407:
+7274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+ 6578              		.loc 1 7274 5 is_stmt 1 view .LVU2156
+7275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6579              		.loc 1 7275 5 view .LVU2157
+7278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS2N;
+ 6580              		.loc 1 7278 5 view .LVU2158
+ 6581              	.LVL519:
+7279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output Idle state */
+ 6582              		.loc 1 7279 5 view .LVU2159
+ARM GAS  /tmp/cc0wMqvE.s 			page 284
+
+
+7279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output Idle state */
+ 6583              		.loc 1 7279 12 is_stmt 0 view .LVU2160
+ 6584 006a 24F4406C 		bic	ip, r4, #3072
+ 6585              	.LVL520:
+7281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Idle state */
+ 6586              		.loc 1 7281 5 is_stmt 1 view .LVU2161
+7281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Idle state */
+ 6587              		.loc 1 7281 25 is_stmt 0 view .LVU2162
+ 6588 006e 4C69     		ldr	r4, [r1, #20]
+7281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     /* Set the Output N Idle state */
+ 6589              		.loc 1 7281 12 view .LVU2163
+ 6590 0070 4CEA840C 		orr	ip, ip, r4, lsl #2
+ 6591              	.LVL521:
+7283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 6592              		.loc 1 7283 5 is_stmt 1 view .LVU2164
+7283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 6593              		.loc 1 7283 25 is_stmt 0 view .LVU2165
+ 6594 0074 8C69     		ldr	r4, [r1, #24]
+7283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 6595              		.loc 1 7283 12 view .LVU2166
+ 6596 0076 4CEA8404 		orr	r4, ip, r4, lsl #2
+ 6597              	.LVL522:
+ 6598              	.L408:
+7287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6599              		.loc 1 7287 3 is_stmt 1 view .LVU2167
+7287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6600              		.loc 1 7287 13 is_stmt 0 view .LVU2168
+ 6601 007a 4460     		str	r4, [r0, #4]
+7290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6602              		.loc 1 7290 3 is_stmt 1 view .LVU2169
+7290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6603              		.loc 1 7290 15 is_stmt 0 view .LVU2170
+ 6604 007c 8261     		str	r2, [r0, #24]
+7293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6605              		.loc 1 7293 3 is_stmt 1 view .LVU2171
+7293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6606              		.loc 1 7293 25 is_stmt 0 view .LVU2172
+ 6607 007e 4A68     		ldr	r2, [r1, #4]
+ 6608              	.LVL523:
+7293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6609              		.loc 1 7293 14 view .LVU2173
+ 6610 0080 8263     		str	r2, [r0, #56]
+ 6611              	.LVL524:
+7296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 6612              		.loc 1 7296 3 is_stmt 1 view .LVU2174
+7296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 6613              		.loc 1 7296 14 is_stmt 0 view .LVU2175
+ 6614 0082 0362     		str	r3, [r0, #32]
+7297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6615              		.loc 1 7297 1 view .LVU2176
+ 6616 0084 30BC     		pop	{r4, r5}
+ 6617              	.LCFI61:
+ 6618              		.cfi_restore 5
+ 6619              		.cfi_restore 4
+ 6620              		.cfi_def_cfa_offset 0
+ 6621              	.LVL525:
+7297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 285
+
+
+ 6622              		.loc 1 7297 1 view .LVU2177
+ 6623 0086 7047     		bx	lr
+ 6624              	.L411:
+ 6625              		.align	2
+ 6626              	.L410:
+ 6627 0088 002C0140 		.word	1073818624
+ 6628              		.cfi_endproc
+ 6629              	.LFE435:
+ 6631              		.section	.text.HAL_TIM_OC_ConfigChannel,"ax",%progbits
+ 6632              		.align	1
+ 6633              		.global	HAL_TIM_OC_ConfigChannel
+ 6634              		.syntax unified
+ 6635              		.thumb
+ 6636              		.thumb_func
+ 6638              	HAL_TIM_OC_ConfigChannel:
+ 6639              	.LVL526:
+ 6640              	.LFB388:
+4123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 6641              		.loc 1 4123 1 is_stmt 1 view -0
+ 6642              		.cfi_startproc
+ 6643              		@ args = 0, pretend = 0, frame = 0
+ 6644              		@ frame_needed = 0, uses_anonymous_args = 0
+4124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6645              		.loc 1 4124 3 view .LVU2179
+4127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
+ 6646              		.loc 1 4127 3 view .LVU2180
+4128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ 6647              		.loc 1 4128 3 view .LVU2181
+4129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6648              		.loc 1 4129 3 view .LVU2182
+4132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6649              		.loc 1 4132 3 view .LVU2183
+4132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6650              		.loc 1 4132 3 view .LVU2184
+ 6651 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 6652 0004 012B     		cmp	r3, #1
+ 6653 0006 36D0     		beq	.L422
+4123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 6654              		.loc 1 4123 1 is_stmt 0 discriminator 2 view .LVU2185
+ 6655 0008 10B5     		push	{r4, lr}
+ 6656              	.LCFI62:
+ 6657              		.cfi_def_cfa_offset 8
+ 6658              		.cfi_offset 4, -8
+ 6659              		.cfi_offset 14, -4
+ 6660 000a 0446     		mov	r4, r0
+4132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6661              		.loc 1 4132 3 is_stmt 1 discriminator 2 view .LVU2186
+ 6662 000c 0123     		movs	r3, #1
+ 6663 000e 80F83C30 		strb	r3, [r0, #60]
+4132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6664              		.loc 1 4132 3 discriminator 2 view .LVU2187
+4134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6665              		.loc 1 4134 3 discriminator 2 view .LVU2188
+ 6666 0012 142A     		cmp	r2, #20
+ 6667 0014 2AD8     		bhi	.L423
+ 6668 0016 DFE802F0 		tbb	[pc, r2]
+ 6669              	.L416:
+ARM GAS  /tmp/cc0wMqvE.s 			page 286
+
+
+ 6670 001a 0B       		.byte	(.L421-.L416)/2
+ 6671 001b 29       		.byte	(.L423-.L416)/2
+ 6672 001c 29       		.byte	(.L423-.L416)/2
+ 6673 001d 29       		.byte	(.L423-.L416)/2
+ 6674 001e 10       		.byte	(.L420-.L416)/2
+ 6675 001f 29       		.byte	(.L423-.L416)/2
+ 6676 0020 29       		.byte	(.L423-.L416)/2
+ 6677 0021 29       		.byte	(.L423-.L416)/2
+ 6678 0022 15       		.byte	(.L419-.L416)/2
+ 6679 0023 29       		.byte	(.L423-.L416)/2
+ 6680 0024 29       		.byte	(.L423-.L416)/2
+ 6681 0025 29       		.byte	(.L423-.L416)/2
+ 6682 0026 1A       		.byte	(.L418-.L416)/2
+ 6683 0027 29       		.byte	(.L423-.L416)/2
+ 6684 0028 29       		.byte	(.L423-.L416)/2
+ 6685 0029 29       		.byte	(.L423-.L416)/2
+ 6686 002a 1F       		.byte	(.L417-.L416)/2
+ 6687 002b 29       		.byte	(.L423-.L416)/2
+ 6688 002c 29       		.byte	(.L423-.L416)/2
+ 6689 002d 29       		.byte	(.L423-.L416)/2
+ 6690 002e 24       		.byte	(.L415-.L416)/2
+ 6691 002f 00       		.p2align 1
+ 6692              	.L421:
+4139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6693              		.loc 1 4139 7 view .LVU2189
+4142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6694              		.loc 1 4142 7 view .LVU2190
+ 6695 0030 0068     		ldr	r0, [r0]
+ 6696              	.LVL527:
+4142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6697              		.loc 1 4142 7 is_stmt 0 view .LVU2191
+ 6698 0032 FFF7FEFF 		bl	TIM_OC1_SetConfig
+ 6699              	.LVL528:
+4143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6700              		.loc 1 4143 7 is_stmt 1 view .LVU2192
+4124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6701              		.loc 1 4124 21 is_stmt 0 view .LVU2193
+ 6702 0036 0020     		movs	r0, #0
+4143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6703              		.loc 1 4143 7 view .LVU2194
+ 6704 0038 19E0     		b	.L414
+ 6705              	.LVL529:
+ 6706              	.L420:
+4149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6707              		.loc 1 4149 7 is_stmt 1 view .LVU2195
+4152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6708              		.loc 1 4152 7 view .LVU2196
+ 6709 003a 0068     		ldr	r0, [r0]
+ 6710              	.LVL530:
+4152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6711              		.loc 1 4152 7 is_stmt 0 view .LVU2197
+ 6712 003c FFF7FEFF 		bl	TIM_OC2_SetConfig
+ 6713              	.LVL531:
+4153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6714              		.loc 1 4153 7 is_stmt 1 view .LVU2198
+4124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6715              		.loc 1 4124 21 is_stmt 0 view .LVU2199
+ARM GAS  /tmp/cc0wMqvE.s 			page 287
+
+
+ 6716 0040 0020     		movs	r0, #0
+4153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6717              		.loc 1 4153 7 view .LVU2200
+ 6718 0042 14E0     		b	.L414
+ 6719              	.LVL532:
+ 6720              	.L419:
+4159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6721              		.loc 1 4159 7 is_stmt 1 view .LVU2201
+4162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6722              		.loc 1 4162 7 view .LVU2202
+ 6723 0044 0068     		ldr	r0, [r0]
+ 6724              	.LVL533:
+4162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6725              		.loc 1 4162 7 is_stmt 0 view .LVU2203
+ 6726 0046 FFF7FEFF 		bl	TIM_OC3_SetConfig
+ 6727              	.LVL534:
+4163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6728              		.loc 1 4163 7 is_stmt 1 view .LVU2204
+4124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6729              		.loc 1 4124 21 is_stmt 0 view .LVU2205
+ 6730 004a 0020     		movs	r0, #0
+4163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6731              		.loc 1 4163 7 view .LVU2206
+ 6732 004c 0FE0     		b	.L414
+ 6733              	.LVL535:
+ 6734              	.L418:
+4169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6735              		.loc 1 4169 7 is_stmt 1 view .LVU2207
+4172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6736              		.loc 1 4172 7 view .LVU2208
+ 6737 004e 0068     		ldr	r0, [r0]
+ 6738              	.LVL536:
+4172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6739              		.loc 1 4172 7 is_stmt 0 view .LVU2209
+ 6740 0050 FFF7FEFF 		bl	TIM_OC4_SetConfig
+ 6741              	.LVL537:
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6742              		.loc 1 4173 7 is_stmt 1 view .LVU2210
+4124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6743              		.loc 1 4124 21 is_stmt 0 view .LVU2211
+ 6744 0054 0020     		movs	r0, #0
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6745              		.loc 1 4173 7 view .LVU2212
+ 6746 0056 0AE0     		b	.L414
+ 6747              	.LVL538:
+ 6748              	.L417:
+4179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6749              		.loc 1 4179 7 is_stmt 1 view .LVU2213
+4182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6750              		.loc 1 4182 7 view .LVU2214
+ 6751 0058 0068     		ldr	r0, [r0]
+ 6752              	.LVL539:
+4182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6753              		.loc 1 4182 7 is_stmt 0 view .LVU2215
+ 6754 005a FFF7FEFF 		bl	TIM_OC5_SetConfig
+ 6755              	.LVL540:
+4183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ARM GAS  /tmp/cc0wMqvE.s 			page 288
+
+
+ 6756              		.loc 1 4183 7 is_stmt 1 view .LVU2216
+4124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6757              		.loc 1 4124 21 is_stmt 0 view .LVU2217
+ 6758 005e 0020     		movs	r0, #0
+4183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6759              		.loc 1 4183 7 view .LVU2218
+ 6760 0060 05E0     		b	.L414
+ 6761              	.LVL541:
+ 6762              	.L415:
+4189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6763              		.loc 1 4189 7 is_stmt 1 view .LVU2219
+4192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6764              		.loc 1 4192 7 view .LVU2220
+ 6765 0062 0068     		ldr	r0, [r0]
+ 6766              	.LVL542:
+4192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6767              		.loc 1 4192 7 is_stmt 0 view .LVU2221
+ 6768 0064 FFF7FEFF 		bl	TIM_OC6_SetConfig
+ 6769              	.LVL543:
+4193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6770              		.loc 1 4193 7 is_stmt 1 view .LVU2222
+4124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6771              		.loc 1 4124 21 is_stmt 0 view .LVU2223
+ 6772 0068 0020     		movs	r0, #0
+4193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6773              		.loc 1 4193 7 view .LVU2224
+ 6774 006a 00E0     		b	.L414
+ 6775              	.LVL544:
+ 6776              	.L423:
+4134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6777              		.loc 1 4134 3 view .LVU2225
+ 6778 006c 0120     		movs	r0, #1
+ 6779              	.LVL545:
+ 6780              	.L414:
+4201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6781              		.loc 1 4201 3 is_stmt 1 view .LVU2226
+4201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6782              		.loc 1 4201 3 view .LVU2227
+ 6783 006e 0023     		movs	r3, #0
+ 6784 0070 84F83C30 		strb	r3, [r4, #60]
+4201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6785              		.loc 1 4201 3 view .LVU2228
+4203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 6786              		.loc 1 4203 3 view .LVU2229
+4204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6787              		.loc 1 4204 1 is_stmt 0 view .LVU2230
+ 6788 0074 10BD     		pop	{r4, pc}
+ 6789              	.LVL546:
+ 6790              	.L422:
+ 6791              	.LCFI63:
+ 6792              		.cfi_def_cfa_offset 0
+ 6793              		.cfi_restore 4
+ 6794              		.cfi_restore 14
+4132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6795              		.loc 1 4132 3 view .LVU2231
+ 6796 0076 0220     		movs	r0, #2
+ 6797              	.LVL547:
+ARM GAS  /tmp/cc0wMqvE.s 			page 289
+
+
+4204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6798              		.loc 1 4204 1 view .LVU2232
+ 6799 0078 7047     		bx	lr
+ 6800              		.cfi_endproc
+ 6801              	.LFE388:
+ 6803              		.section	.text.HAL_TIM_PWM_ConfigChannel,"ax",%progbits
+ 6804              		.align	1
+ 6805              		.global	HAL_TIM_PWM_ConfigChannel
+ 6806              		.syntax unified
+ 6807              		.thumb
+ 6808              		.thumb_func
+ 6810              	HAL_TIM_PWM_ConfigChannel:
+ 6811              	.LVL548:
+ 6812              	.LFB390:
+4323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 6813              		.loc 1 4323 1 is_stmt 1 view -0
+ 6814              		.cfi_startproc
+ 6815              		@ args = 0, pretend = 0, frame = 0
+ 6816              		@ frame_needed = 0, uses_anonymous_args = 0
+4323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 6817              		.loc 1 4323 1 is_stmt 0 view .LVU2234
+ 6818 0000 38B5     		push	{r3, r4, r5, lr}
+ 6819              	.LCFI64:
+ 6820              		.cfi_def_cfa_offset 16
+ 6821              		.cfi_offset 3, -16
+ 6822              		.cfi_offset 4, -12
+ 6823              		.cfi_offset 5, -8
+ 6824              		.cfi_offset 14, -4
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6825              		.loc 1 4324 3 is_stmt 1 view .LVU2235
+ 6826              	.LVL549:
+4327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ 6827              		.loc 1 4327 3 view .LVU2236
+4328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ 6828              		.loc 1 4328 3 view .LVU2237
+4329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+ 6829              		.loc 1 4329 3 view .LVU2238
+4330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6830              		.loc 1 4330 3 view .LVU2239
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6831              		.loc 1 4333 3 view .LVU2240
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6832              		.loc 1 4333 3 view .LVU2241
+ 6833 0002 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 6834 0006 012B     		cmp	r3, #1
+ 6835 0008 00F09580 		beq	.L438
+ 6836 000c 0446     		mov	r4, r0
+ 6837 000e 0D46     		mov	r5, r1
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6838              		.loc 1 4333 3 discriminator 2 view .LVU2242
+ 6839 0010 0123     		movs	r3, #1
+ 6840 0012 80F83C30 		strb	r3, [r0, #60]
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6841              		.loc 1 4333 3 discriminator 2 view .LVU2243
+4335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 6842              		.loc 1 4335 3 discriminator 2 view .LVU2244
+ 6843 0016 142A     		cmp	r2, #20
+ARM GAS  /tmp/cc0wMqvE.s 			page 290
+
+
+ 6844 0018 00F28880 		bhi	.L439
+ 6845 001c DFE802F0 		tbb	[pc, r2]
+ 6846              	.L432:
+ 6847 0020 0B       		.byte	(.L437-.L432)/2
+ 6848 0021 86       		.byte	(.L439-.L432)/2
+ 6849 0022 86       		.byte	(.L439-.L432)/2
+ 6850 0023 86       		.byte	(.L439-.L432)/2
+ 6851 0024 1F       		.byte	(.L436-.L432)/2
+ 6852 0025 86       		.byte	(.L439-.L432)/2
+ 6853 0026 86       		.byte	(.L439-.L432)/2
+ 6854 0027 86       		.byte	(.L439-.L432)/2
+ 6855 0028 34       		.byte	(.L435-.L432)/2
+ 6856 0029 86       		.byte	(.L439-.L432)/2
+ 6857 002a 86       		.byte	(.L439-.L432)/2
+ 6858 002b 86       		.byte	(.L439-.L432)/2
+ 6859 002c 48       		.byte	(.L434-.L432)/2
+ 6860 002d 86       		.byte	(.L439-.L432)/2
+ 6861 002e 86       		.byte	(.L439-.L432)/2
+ 6862 002f 86       		.byte	(.L439-.L432)/2
+ 6863 0030 5D       		.byte	(.L433-.L432)/2
+ 6864 0031 86       		.byte	(.L439-.L432)/2
+ 6865 0032 86       		.byte	(.L439-.L432)/2
+ 6866 0033 86       		.byte	(.L439-.L432)/2
+ 6867 0034 71       		.byte	(.L431-.L432)/2
+ 6868 0035 00       		.p2align 1
+ 6869              	.L437:
+4340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6870              		.loc 1 4340 7 view .LVU2245
+4343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6871              		.loc 1 4343 7 view .LVU2246
+ 6872 0036 0068     		ldr	r0, [r0]
+ 6873              	.LVL550:
+4343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6874              		.loc 1 4343 7 is_stmt 0 view .LVU2247
+ 6875 0038 FFF7FEFF 		bl	TIM_OC1_SetConfig
+ 6876              	.LVL551:
+4346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6877              		.loc 1 4346 7 is_stmt 1 view .LVU2248
+4346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6878              		.loc 1 4346 11 is_stmt 0 view .LVU2249
+ 6879 003c 2268     		ldr	r2, [r4]
+4346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6880              		.loc 1 4346 21 view .LVU2250
+ 6881 003e 9369     		ldr	r3, [r2, #24]
+4346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6882              		.loc 1 4346 29 view .LVU2251
+ 6883 0040 43F00803 		orr	r3, r3, #8
+ 6884 0044 9361     		str	r3, [r2, #24]
+4349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ 6885              		.loc 1 4349 7 is_stmt 1 view .LVU2252
+4349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ 6886              		.loc 1 4349 11 is_stmt 0 view .LVU2253
+ 6887 0046 2268     		ldr	r2, [r4]
+4349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ 6888              		.loc 1 4349 21 view .LVU2254
+ 6889 0048 9369     		ldr	r3, [r2, #24]
+4349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ARM GAS  /tmp/cc0wMqvE.s 			page 291
+
+
+ 6890              		.loc 1 4349 29 view .LVU2255
+ 6891 004a 23F00403 		bic	r3, r3, #4
+ 6892 004e 9361     		str	r3, [r2, #24]
+4350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6893              		.loc 1 4350 7 is_stmt 1 view .LVU2256
+4350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6894              		.loc 1 4350 11 is_stmt 0 view .LVU2257
+ 6895 0050 2268     		ldr	r2, [r4]
+4350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6896              		.loc 1 4350 21 view .LVU2258
+ 6897 0052 9369     		ldr	r3, [r2, #24]
+4350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6898              		.loc 1 4350 39 view .LVU2259
+ 6899 0054 2969     		ldr	r1, [r5, #16]
+4350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6900              		.loc 1 4350 29 view .LVU2260
+ 6901 0056 0B43     		orrs	r3, r3, r1
+ 6902 0058 9361     		str	r3, [r2, #24]
+4351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6903              		.loc 1 4351 7 is_stmt 1 view .LVU2261
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6904              		.loc 1 4324 21 is_stmt 0 view .LVU2262
+ 6905 005a 0020     		movs	r0, #0
+4351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6906              		.loc 1 4351 7 view .LVU2263
+ 6907 005c 67E0     		b	.L430
+ 6908              	.LVL552:
+ 6909              	.L436:
+4357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6910              		.loc 1 4357 7 is_stmt 1 view .LVU2264
+4360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6911              		.loc 1 4360 7 view .LVU2265
+ 6912 005e 0068     		ldr	r0, [r0]
+ 6913              	.LVL553:
+4360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6914              		.loc 1 4360 7 is_stmt 0 view .LVU2266
+ 6915 0060 FFF7FEFF 		bl	TIM_OC2_SetConfig
+ 6916              	.LVL554:
+4363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6917              		.loc 1 4363 7 is_stmt 1 view .LVU2267
+4363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6918              		.loc 1 4363 11 is_stmt 0 view .LVU2268
+ 6919 0064 2268     		ldr	r2, [r4]
+4363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6920              		.loc 1 4363 21 view .LVU2269
+ 6921 0066 9369     		ldr	r3, [r2, #24]
+4363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6922              		.loc 1 4363 29 view .LVU2270
+ 6923 0068 43F40063 		orr	r3, r3, #2048
+ 6924 006c 9361     		str	r3, [r2, #24]
+4366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ 6925              		.loc 1 4366 7 is_stmt 1 view .LVU2271
+4366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ 6926              		.loc 1 4366 11 is_stmt 0 view .LVU2272
+ 6927 006e 2268     		ldr	r2, [r4]
+4366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ 6928              		.loc 1 4366 21 view .LVU2273
+ARM GAS  /tmp/cc0wMqvE.s 			page 292
+
+
+ 6929 0070 9369     		ldr	r3, [r2, #24]
+4366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ 6930              		.loc 1 4366 29 view .LVU2274
+ 6931 0072 23F48063 		bic	r3, r3, #1024
+ 6932 0076 9361     		str	r3, [r2, #24]
+4367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6933              		.loc 1 4367 7 is_stmt 1 view .LVU2275
+4367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6934              		.loc 1 4367 11 is_stmt 0 view .LVU2276
+ 6935 0078 2268     		ldr	r2, [r4]
+4367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6936              		.loc 1 4367 21 view .LVU2277
+ 6937 007a 9369     		ldr	r3, [r2, #24]
+4367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6938              		.loc 1 4367 39 view .LVU2278
+ 6939 007c 2969     		ldr	r1, [r5, #16]
+4367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6940              		.loc 1 4367 29 view .LVU2279
+ 6941 007e 43EA0123 		orr	r3, r3, r1, lsl #8
+ 6942 0082 9361     		str	r3, [r2, #24]
+4368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6943              		.loc 1 4368 7 is_stmt 1 view .LVU2280
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6944              		.loc 1 4324 21 is_stmt 0 view .LVU2281
+ 6945 0084 0020     		movs	r0, #0
+4368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6946              		.loc 1 4368 7 view .LVU2282
+ 6947 0086 52E0     		b	.L430
+ 6948              	.LVL555:
+ 6949              	.L435:
+4374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6950              		.loc 1 4374 7 is_stmt 1 view .LVU2283
+4377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6951              		.loc 1 4377 7 view .LVU2284
+ 6952 0088 0068     		ldr	r0, [r0]
+ 6953              	.LVL556:
+4377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6954              		.loc 1 4377 7 is_stmt 0 view .LVU2285
+ 6955 008a FFF7FEFF 		bl	TIM_OC3_SetConfig
+ 6956              	.LVL557:
+4380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6957              		.loc 1 4380 7 is_stmt 1 view .LVU2286
+4380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6958              		.loc 1 4380 11 is_stmt 0 view .LVU2287
+ 6959 008e 2268     		ldr	r2, [r4]
+4380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6960              		.loc 1 4380 21 view .LVU2288
+ 6961 0090 D369     		ldr	r3, [r2, #28]
+4380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6962              		.loc 1 4380 29 view .LVU2289
+ 6963 0092 43F00803 		orr	r3, r3, #8
+ 6964 0096 D361     		str	r3, [r2, #28]
+4383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ 6965              		.loc 1 4383 7 is_stmt 1 view .LVU2290
+4383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ 6966              		.loc 1 4383 11 is_stmt 0 view .LVU2291
+ 6967 0098 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/cc0wMqvE.s 			page 293
+
+
+4383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ 6968              		.loc 1 4383 21 view .LVU2292
+ 6969 009a D369     		ldr	r3, [r2, #28]
+4383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ 6970              		.loc 1 4383 29 view .LVU2293
+ 6971 009c 23F00403 		bic	r3, r3, #4
+ 6972 00a0 D361     		str	r3, [r2, #28]
+4384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6973              		.loc 1 4384 7 is_stmt 1 view .LVU2294
+4384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6974              		.loc 1 4384 11 is_stmt 0 view .LVU2295
+ 6975 00a2 2268     		ldr	r2, [r4]
+4384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6976              		.loc 1 4384 21 view .LVU2296
+ 6977 00a4 D369     		ldr	r3, [r2, #28]
+4384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6978              		.loc 1 4384 39 view .LVU2297
+ 6979 00a6 2969     		ldr	r1, [r5, #16]
+4384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 6980              		.loc 1 4384 29 view .LVU2298
+ 6981 00a8 0B43     		orrs	r3, r3, r1
+ 6982 00aa D361     		str	r3, [r2, #28]
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6983              		.loc 1 4385 7 is_stmt 1 view .LVU2299
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6984              		.loc 1 4324 21 is_stmt 0 view .LVU2300
+ 6985 00ac 0020     		movs	r0, #0
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 6986              		.loc 1 4385 7 view .LVU2301
+ 6987 00ae 3EE0     		b	.L430
+ 6988              	.LVL558:
+ 6989              	.L434:
+4391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6990              		.loc 1 4391 7 is_stmt 1 view .LVU2302
+4394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6991              		.loc 1 4394 7 view .LVU2303
+ 6992 00b0 0068     		ldr	r0, [r0]
+ 6993              	.LVL559:
+4394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6994              		.loc 1 4394 7 is_stmt 0 view .LVU2304
+ 6995 00b2 FFF7FEFF 		bl	TIM_OC4_SetConfig
+ 6996              	.LVL560:
+4397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6997              		.loc 1 4397 7 is_stmt 1 view .LVU2305
+4397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 6998              		.loc 1 4397 11 is_stmt 0 view .LVU2306
+ 6999 00b6 2268     		ldr	r2, [r4]
+4397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7000              		.loc 1 4397 21 view .LVU2307
+ 7001 00b8 D369     		ldr	r3, [r2, #28]
+4397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7002              		.loc 1 4397 29 view .LVU2308
+ 7003 00ba 43F40063 		orr	r3, r3, #2048
+ 7004 00be D361     		str	r3, [r2, #28]
+4400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ 7005              		.loc 1 4400 7 is_stmt 1 view .LVU2309
+4400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ARM GAS  /tmp/cc0wMqvE.s 			page 294
+
+
+ 7006              		.loc 1 4400 11 is_stmt 0 view .LVU2310
+ 7007 00c0 2268     		ldr	r2, [r4]
+4400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ 7008              		.loc 1 4400 21 view .LVU2311
+ 7009 00c2 D369     		ldr	r3, [r2, #28]
+4400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ 7010              		.loc 1 4400 29 view .LVU2312
+ 7011 00c4 23F48063 		bic	r3, r3, #1024
+ 7012 00c8 D361     		str	r3, [r2, #28]
+4401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7013              		.loc 1 4401 7 is_stmt 1 view .LVU2313
+4401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7014              		.loc 1 4401 11 is_stmt 0 view .LVU2314
+ 7015 00ca 2268     		ldr	r2, [r4]
+4401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7016              		.loc 1 4401 21 view .LVU2315
+ 7017 00cc D369     		ldr	r3, [r2, #28]
+4401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7018              		.loc 1 4401 39 view .LVU2316
+ 7019 00ce 2969     		ldr	r1, [r5, #16]
+4401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7020              		.loc 1 4401 29 view .LVU2317
+ 7021 00d0 43EA0123 		orr	r3, r3, r1, lsl #8
+ 7022 00d4 D361     		str	r3, [r2, #28]
+4402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 7023              		.loc 1 4402 7 is_stmt 1 view .LVU2318
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7024              		.loc 1 4324 21 is_stmt 0 view .LVU2319
+ 7025 00d6 0020     		movs	r0, #0
+4402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 7026              		.loc 1 4402 7 view .LVU2320
+ 7027 00d8 29E0     		b	.L430
+ 7028              	.LVL561:
+ 7029              	.L433:
+4408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7030              		.loc 1 4408 7 is_stmt 1 view .LVU2321
+4411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7031              		.loc 1 4411 7 view .LVU2322
+ 7032 00da 0068     		ldr	r0, [r0]
+ 7033              	.LVL562:
+4411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7034              		.loc 1 4411 7 is_stmt 0 view .LVU2323
+ 7035 00dc FFF7FEFF 		bl	TIM_OC5_SetConfig
+ 7036              	.LVL563:
+4414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7037              		.loc 1 4414 7 is_stmt 1 view .LVU2324
+4414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7038              		.loc 1 4414 11 is_stmt 0 view .LVU2325
+ 7039 00e0 2268     		ldr	r2, [r4]
+4414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7040              		.loc 1 4414 21 view .LVU2326
+ 7041 00e2 136D     		ldr	r3, [r2, #80]
+4414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7042              		.loc 1 4414 29 view .LVU2327
+ 7043 00e4 43F00803 		orr	r3, r3, #8
+ 7044 00e8 1365     		str	r3, [r2, #80]
+4417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ARM GAS  /tmp/cc0wMqvE.s 			page 295
+
+
+ 7045              		.loc 1 4417 7 is_stmt 1 view .LVU2328
+4417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ 7046              		.loc 1 4417 11 is_stmt 0 view .LVU2329
+ 7047 00ea 2268     		ldr	r2, [r4]
+4417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ 7048              		.loc 1 4417 21 view .LVU2330
+ 7049 00ec 136D     		ldr	r3, [r2, #80]
+4417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ 7050              		.loc 1 4417 29 view .LVU2331
+ 7051 00ee 23F00403 		bic	r3, r3, #4
+ 7052 00f2 1365     		str	r3, [r2, #80]
+4418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7053              		.loc 1 4418 7 is_stmt 1 view .LVU2332
+4418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7054              		.loc 1 4418 11 is_stmt 0 view .LVU2333
+ 7055 00f4 2268     		ldr	r2, [r4]
+4418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7056              		.loc 1 4418 21 view .LVU2334
+ 7057 00f6 136D     		ldr	r3, [r2, #80]
+4418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7058              		.loc 1 4418 39 view .LVU2335
+ 7059 00f8 2969     		ldr	r1, [r5, #16]
+4418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7060              		.loc 1 4418 29 view .LVU2336
+ 7061 00fa 0B43     		orrs	r3, r3, r1
+ 7062 00fc 1365     		str	r3, [r2, #80]
+4419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 7063              		.loc 1 4419 7 is_stmt 1 view .LVU2337
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7064              		.loc 1 4324 21 is_stmt 0 view .LVU2338
+ 7065 00fe 0020     		movs	r0, #0
+4419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 7066              		.loc 1 4419 7 view .LVU2339
+ 7067 0100 15E0     		b	.L430
+ 7068              	.LVL564:
+ 7069              	.L431:
+4425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7070              		.loc 1 4425 7 is_stmt 1 view .LVU2340
+4428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7071              		.loc 1 4428 7 view .LVU2341
+ 7072 0102 0068     		ldr	r0, [r0]
+ 7073              	.LVL565:
+4428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7074              		.loc 1 4428 7 is_stmt 0 view .LVU2342
+ 7075 0104 FFF7FEFF 		bl	TIM_OC6_SetConfig
+ 7076              	.LVL566:
+4431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7077              		.loc 1 4431 7 is_stmt 1 view .LVU2343
+4431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7078              		.loc 1 4431 11 is_stmt 0 view .LVU2344
+ 7079 0108 2268     		ldr	r2, [r4]
+4431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7080              		.loc 1 4431 21 view .LVU2345
+ 7081 010a 136D     		ldr	r3, [r2, #80]
+4431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7082              		.loc 1 4431 29 view .LVU2346
+ 7083 010c 43F40063 		orr	r3, r3, #2048
+ARM GAS  /tmp/cc0wMqvE.s 			page 296
+
+
+ 7084 0110 1365     		str	r3, [r2, #80]
+4434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ 7085              		.loc 1 4434 7 is_stmt 1 view .LVU2347
+4434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ 7086              		.loc 1 4434 11 is_stmt 0 view .LVU2348
+ 7087 0112 2268     		ldr	r2, [r4]
+4434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ 7088              		.loc 1 4434 21 view .LVU2349
+ 7089 0114 136D     		ldr	r3, [r2, #80]
+4434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ 7090              		.loc 1 4434 29 view .LVU2350
+ 7091 0116 23F48063 		bic	r3, r3, #1024
+ 7092 011a 1365     		str	r3, [r2, #80]
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7093              		.loc 1 4435 7 is_stmt 1 view .LVU2351
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7094              		.loc 1 4435 11 is_stmt 0 view .LVU2352
+ 7095 011c 2268     		ldr	r2, [r4]
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7096              		.loc 1 4435 21 view .LVU2353
+ 7097 011e 136D     		ldr	r3, [r2, #80]
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7098              		.loc 1 4435 39 view .LVU2354
+ 7099 0120 2969     		ldr	r1, [r5, #16]
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 7100              		.loc 1 4435 29 view .LVU2355
+ 7101 0122 43EA0123 		orr	r3, r3, r1, lsl #8
+ 7102 0126 1365     		str	r3, [r2, #80]
+4436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 7103              		.loc 1 4436 7 is_stmt 1 view .LVU2356
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7104              		.loc 1 4324 21 is_stmt 0 view .LVU2357
+ 7105 0128 0020     		movs	r0, #0
+4436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 7106              		.loc 1 4436 7 view .LVU2358
+ 7107 012a 00E0     		b	.L430
+ 7108              	.LVL567:
+ 7109              	.L439:
+4335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7110              		.loc 1 4335 3 view .LVU2359
+ 7111 012c 0120     		movs	r0, #1
+ 7112              	.LVL568:
+ 7113              	.L430:
+4444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7114              		.loc 1 4444 3 is_stmt 1 view .LVU2360
+4444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7115              		.loc 1 4444 3 view .LVU2361
+ 7116 012e 0023     		movs	r3, #0
+ 7117 0130 84F83C30 		strb	r3, [r4, #60]
+4444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7118              		.loc 1 4444 3 view .LVU2362
+4446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 7119              		.loc 1 4446 3 view .LVU2363
+ 7120              	.LVL569:
+ 7121              	.L429:
+4447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7122              		.loc 1 4447 1 is_stmt 0 view .LVU2364
+ARM GAS  /tmp/cc0wMqvE.s 			page 297
+
+
+ 7123 0134 38BD     		pop	{r3, r4, r5, pc}
+ 7124              	.LVL570:
+ 7125              	.L438:
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7126              		.loc 1 4333 3 view .LVU2365
+ 7127 0136 0220     		movs	r0, #2
+ 7128              	.LVL571:
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7129              		.loc 1 4333 3 view .LVU2366
+ 7130 0138 FCE7     		b	.L429
+ 7131              		.cfi_endproc
+ 7132              	.LFE390:
+ 7134              		.section	.text.TIM_TI1_SetConfig,"ax",%progbits
+ 7135              		.align	1
+ 7136              		.global	TIM_TI1_SetConfig
+ 7137              		.syntax unified
+ 7138              		.thumb
+ 7139              		.thumb_func
+ 7141              	TIM_TI1_SetConfig:
+ 7142              	.LVL572:
+ 7143              	.LFB441:
+7714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 7144              		.loc 1 7714 1 is_stmt 1 view -0
+ 7145              		.cfi_startproc
+ 7146              		@ args = 0, pretend = 0, frame = 0
+ 7147              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7148              		@ link register save eliminated.
+7714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 7149              		.loc 1 7714 1 is_stmt 0 view .LVU2368
+ 7150 0000 70B4     		push	{r4, r5, r6}
+ 7151              	.LCFI65:
+ 7152              		.cfi_def_cfa_offset 12
+ 7153              		.cfi_offset 4, -12
+ 7154              		.cfi_offset 5, -8
+ 7155              		.cfi_offset 6, -4
+ 7156 0002 9446     		mov	ip, r2
+7715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ 7157              		.loc 1 7715 3 is_stmt 1 view .LVU2369
+7716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7158              		.loc 1 7716 3 view .LVU2370
+7719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+ 7159              		.loc 1 7719 3 view .LVU2371
+7719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+ 7160              		.loc 1 7719 7 is_stmt 0 view .LVU2372
+ 7161 0004 046A     		ldr	r4, [r0, #32]
+7719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+ 7162              		.loc 1 7719 14 view .LVU2373
+ 7163 0006 24F00104 		bic	r4, r4, #1
+ 7164 000a 0462     		str	r4, [r0, #32]
+7720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 7165              		.loc 1 7720 3 is_stmt 1 view .LVU2374
+7720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 7166              		.loc 1 7720 12 is_stmt 0 view .LVU2375
+ 7167 000c 8469     		ldr	r4, [r0, #24]
+ 7168              	.LVL573:
+7721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7169              		.loc 1 7721 3 is_stmt 1 view .LVU2376
+ARM GAS  /tmp/cc0wMqvE.s 			page 298
+
+
+7721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7170              		.loc 1 7721 11 is_stmt 0 view .LVU2377
+ 7171 000e 066A     		ldr	r6, [r0, #32]
+ 7172              	.LVL574:
+7724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7173              		.loc 1 7724 3 is_stmt 1 view .LVU2378
+7724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7174              		.loc 1 7724 7 is_stmt 0 view .LVU2379
+ 7175 0010 144D     		ldr	r5, .L445
+ 7176 0012 A842     		cmp	r0, r5
+ 7177 0014 14D0     		beq	.L442
+7724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7178              		.loc 1 7724 7 discriminator 2 view .LVU2380
+ 7179 0016 B0F1804F 		cmp	r0, #1073741824
+ 7180 001a 11D0     		beq	.L442
+7724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7181              		.loc 1 7724 7 discriminator 4 view .LVU2381
+ 7182 001c 124A     		ldr	r2, .L445+4
+ 7183              	.LVL575:
+7724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7184              		.loc 1 7724 7 discriminator 4 view .LVU2382
+ 7185 001e 9042     		cmp	r0, r2
+ 7186 0020 0ED0     		beq	.L442
+7724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7187              		.loc 1 7724 7 discriminator 6 view .LVU2383
+ 7188 0022 02F58062 		add	r2, r2, #1024
+ 7189 0026 9042     		cmp	r0, r2
+ 7190 0028 0AD0     		beq	.L442
+7724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7191              		.loc 1 7724 7 discriminator 8 view .LVU2384
+ 7192 002a 02F59632 		add	r2, r2, #76800
+ 7193 002e 9042     		cmp	r0, r2
+ 7194 0030 06D0     		beq	.L442
+7724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7195              		.loc 1 7724 7 discriminator 10 view .LVU2385
+ 7196 0032 02F54062 		add	r2, r2, #3072
+ 7197 0036 9042     		cmp	r0, r2
+ 7198 0038 02D0     		beq	.L442
+7731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7199              		.loc 1 7731 5 is_stmt 1 view .LVU2386
+7731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7200              		.loc 1 7731 14 is_stmt 0 view .LVU2387
+ 7201 003a 44F00102 		orr	r2, r4, #1
+ 7202              	.LVL576:
+7731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7203              		.loc 1 7731 14 view .LVU2388
+ 7204 003e 03E0     		b	.L443
+ 7205              	.LVL577:
+ 7206              	.L442:
+7726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccmr1 |= TIM_ICSelection;
+ 7207              		.loc 1 7726 5 is_stmt 1 view .LVU2389
+7726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     tmpccmr1 |= TIM_ICSelection;
+ 7208              		.loc 1 7726 14 is_stmt 0 view .LVU2390
+ 7209 0040 24F00302 		bic	r2, r4, #3
+ 7210              	.LVL578:
+7727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7211              		.loc 1 7727 5 is_stmt 1 view .LVU2391
+ARM GAS  /tmp/cc0wMqvE.s 			page 299
+
+
+7727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7212              		.loc 1 7727 14 is_stmt 0 view .LVU2392
+ 7213 0044 42EA0C02 		orr	r2, r2, ip
+ 7214              	.LVL579:
+ 7215              	.L443:
+7735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+ 7216              		.loc 1 7735 3 is_stmt 1 view .LVU2393
+7735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+ 7217              		.loc 1 7735 12 is_stmt 0 view .LVU2394
+ 7218 0048 22F0F002 		bic	r2, r2, #240
+ 7219              	.LVL580:
+7736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7220              		.loc 1 7736 3 is_stmt 1 view .LVU2395
+7736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7221              		.loc 1 7736 30 is_stmt 0 view .LVU2396
+ 7222 004c 1B01     		lsls	r3, r3, #4
+ 7223              	.LVL581:
+7736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7224              		.loc 1 7736 37 view .LVU2397
+ 7225 004e DBB2     		uxtb	r3, r3
+7736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7226              		.loc 1 7736 12 view .LVU2398
+ 7227 0050 1343     		orrs	r3, r3, r2
+ 7228              	.LVL582:
+7739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+ 7229              		.loc 1 7739 3 is_stmt 1 view .LVU2399
+7739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+ 7230              		.loc 1 7739 11 is_stmt 0 view .LVU2400
+ 7231 0052 26F00A02 		bic	r2, r6, #10
+ 7232              	.LVL583:
+7740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7233              		.loc 1 7740 3 is_stmt 1 view .LVU2401
+7740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7234              		.loc 1 7740 30 is_stmt 0 view .LVU2402
+ 7235 0056 01F00A01 		and	r1, r1, #10
+ 7236              	.LVL584:
+7740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7237              		.loc 1 7740 11 view .LVU2403
+ 7238 005a 1143     		orrs	r1, r1, r2
+ 7239              	.LVL585:
+7743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 7240              		.loc 1 7743 3 is_stmt 1 view .LVU2404
+7743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 7241              		.loc 1 7743 15 is_stmt 0 view .LVU2405
+ 7242 005c 8361     		str	r3, [r0, #24]
+7744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 7243              		.loc 1 7744 3 is_stmt 1 view .LVU2406
+7744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 7244              		.loc 1 7744 14 is_stmt 0 view .LVU2407
+ 7245 005e 0162     		str	r1, [r0, #32]
+7745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7246              		.loc 1 7745 1 view .LVU2408
+ 7247 0060 70BC     		pop	{r4, r5, r6}
+ 7248              	.LCFI66:
+ 7249              		.cfi_restore 6
+ 7250              		.cfi_restore 5
+ 7251              		.cfi_restore 4
+ARM GAS  /tmp/cc0wMqvE.s 			page 300
+
+
+ 7252              		.cfi_def_cfa_offset 0
+ 7253 0062 7047     		bx	lr
+ 7254              	.L446:
+ 7255              		.align	2
+ 7256              	.L445:
+ 7257 0064 002C0140 		.word	1073818624
+ 7258 0068 00040040 		.word	1073742848
+ 7259              		.cfi_endproc
+ 7260              	.LFE441:
+ 7262              		.section	.text.HAL_TIM_IC_ConfigChannel,"ax",%progbits
+ 7263              		.align	1
+ 7264              		.global	HAL_TIM_IC_ConfigChannel
+ 7265              		.syntax unified
+ 7266              		.thumb
+ 7267              		.thumb_func
+ 7269              	HAL_TIM_IC_ConfigChannel:
+ 7270              	.LVL586:
+ 7271              	.LFB389:
+4220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7272              		.loc 1 4220 1 is_stmt 1 view -0
+ 7273              		.cfi_startproc
+ 7274              		@ args = 0, pretend = 0, frame = 0
+ 7275              		@ frame_needed = 0, uses_anonymous_args = 0
+4220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7276              		.loc 1 4220 1 is_stmt 0 view .LVU2410
+ 7277 0000 38B5     		push	{r3, r4, r5, lr}
+ 7278              	.LCFI67:
+ 7279              		.cfi_def_cfa_offset 16
+ 7280              		.cfi_offset 3, -16
+ 7281              		.cfi_offset 4, -12
+ 7282              		.cfi_offset 5, -8
+ 7283              		.cfi_offset 14, -4
+4221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7284              		.loc 1 4221 3 is_stmt 1 view .LVU2411
+ 7285              	.LVL587:
+4224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+ 7286              		.loc 1 4224 3 view .LVU2412
+4225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+ 7287              		.loc 1 4225 3 view .LVU2413
+4226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+ 7288              		.loc 1 4226 3 view .LVU2414
+4227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+ 7289              		.loc 1 4227 3 view .LVU2415
+4228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7290              		.loc 1 4228 3 view .LVU2416
+4231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7291              		.loc 1 4231 3 view .LVU2417
+4231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7292              		.loc 1 4231 3 view .LVU2418
+ 7293 0002 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 7294 0006 012B     		cmp	r3, #1
+ 7295 0008 5AD0     		beq	.L453
+ 7296 000a 0446     		mov	r4, r0
+ 7297 000c 0D46     		mov	r5, r1
+4231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7298              		.loc 1 4231 3 discriminator 2 view .LVU2419
+ 7299 000e 0123     		movs	r3, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 301
+
+
+ 7300 0010 80F83C30 		strb	r3, [r0, #60]
+4231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7301              		.loc 1 4231 3 discriminator 2 view .LVU2420
+4233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7302              		.loc 1 4233 3 discriminator 2 view .LVU2421
+4233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7303              		.loc 1 4233 6 is_stmt 0 discriminator 2 view .LVU2422
+ 7304 0014 52B1     		cbz	r2, .L456
+4247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7305              		.loc 1 4247 8 is_stmt 1 view .LVU2423
+4247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7306              		.loc 1 4247 11 is_stmt 0 view .LVU2424
+ 7307 0016 042A     		cmp	r2, #4
+ 7308 0018 1AD0     		beq	.L457
+4263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7309              		.loc 1 4263 8 is_stmt 1 view .LVU2425
+4263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7310              		.loc 1 4263 11 is_stmt 0 view .LVU2426
+ 7311 001a 082A     		cmp	r2, #8
+ 7312 001c 2BD0     		beq	.L458
+4279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7313              		.loc 1 4279 8 is_stmt 1 view .LVU2427
+4279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7314              		.loc 1 4279 11 is_stmt 0 view .LVU2428
+ 7315 001e 0C2A     		cmp	r2, #12
+ 7316 0020 3BD0     		beq	.L459
+4297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7317              		.loc 1 4297 12 view .LVU2429
+ 7318 0022 0120     		movs	r0, #1
+ 7319              	.LVL588:
+ 7320              	.L450:
+4300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7321              		.loc 1 4300 3 is_stmt 1 view .LVU2430
+4300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7322              		.loc 1 4300 3 view .LVU2431
+ 7323 0024 0023     		movs	r3, #0
+ 7324 0026 84F83C30 		strb	r3, [r4, #60]
+4300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7325              		.loc 1 4300 3 view .LVU2432
+4302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 7326              		.loc 1 4302 3 view .LVU2433
+ 7327              	.LVL589:
+ 7328              	.L448:
+4303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7329              		.loc 1 4303 1 is_stmt 0 view .LVU2434
+ 7330 002a 38BD     		pop	{r3, r4, r5, pc}
+ 7331              	.LVL590:
+ 7332              	.L456:
+4236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7333              		.loc 1 4236 5 is_stmt 1 view .LVU2435
+ 7334 002c CB68     		ldr	r3, [r1, #12]
+ 7335 002e 4A68     		ldr	r2, [r1, #4]
+ 7336              	.LVL591:
+4236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7337              		.loc 1 4236 5 is_stmt 0 view .LVU2436
+ 7338 0030 0968     		ldr	r1, [r1]
+ 7339              	.LVL592:
+ARM GAS  /tmp/cc0wMqvE.s 			page 302
+
+
+4236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7340              		.loc 1 4236 5 view .LVU2437
+ 7341 0032 0068     		ldr	r0, [r0]
+ 7342              	.LVL593:
+4236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7343              		.loc 1 4236 5 view .LVU2438
+ 7344 0034 FFF7FEFF 		bl	TIM_TI1_SetConfig
+ 7345              	.LVL594:
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7346              		.loc 1 4242 5 is_stmt 1 view .LVU2439
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7347              		.loc 1 4242 9 is_stmt 0 view .LVU2440
+ 7348 0038 2268     		ldr	r2, [r4]
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7349              		.loc 1 4242 19 view .LVU2441
+ 7350 003a 9369     		ldr	r3, [r2, #24]
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7351              		.loc 1 4242 27 view .LVU2442
+ 7352 003c 23F00C03 		bic	r3, r3, #12
+ 7353 0040 9361     		str	r3, [r2, #24]
+4245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7354              		.loc 1 4245 5 is_stmt 1 view .LVU2443
+4245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7355              		.loc 1 4245 9 is_stmt 0 view .LVU2444
+ 7356 0042 2268     		ldr	r2, [r4]
+4245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7357              		.loc 1 4245 19 view .LVU2445
+ 7358 0044 9369     		ldr	r3, [r2, #24]
+4245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7359              		.loc 1 4245 37 view .LVU2446
+ 7360 0046 A968     		ldr	r1, [r5, #8]
+4245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7361              		.loc 1 4245 27 view .LVU2447
+ 7362 0048 0B43     		orrs	r3, r3, r1
+ 7363 004a 9361     		str	r3, [r2, #24]
+4221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7364              		.loc 1 4221 21 view .LVU2448
+ 7365 004c 0020     		movs	r0, #0
+ 7366 004e E9E7     		b	.L450
+ 7367              	.LVL595:
+ 7368              	.L457:
+4250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7369              		.loc 1 4250 5 is_stmt 1 view .LVU2449
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7370              		.loc 1 4252 5 view .LVU2450
+ 7371 0050 CB68     		ldr	r3, [r1, #12]
+ 7372 0052 4A68     		ldr	r2, [r1, #4]
+ 7373              	.LVL596:
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7374              		.loc 1 4252 5 is_stmt 0 view .LVU2451
+ 7375 0054 0968     		ldr	r1, [r1]
+ 7376              	.LVL597:
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7377              		.loc 1 4252 5 view .LVU2452
+ 7378 0056 0068     		ldr	r0, [r0]
+ 7379              	.LVL598:
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ARM GAS  /tmp/cc0wMqvE.s 			page 303
+
+
+ 7380              		.loc 1 4252 5 view .LVU2453
+ 7381 0058 FFF7FEFF 		bl	TIM_TI2_SetConfig
+ 7382              	.LVL599:
+4258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7383              		.loc 1 4258 5 is_stmt 1 view .LVU2454
+4258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7384              		.loc 1 4258 9 is_stmt 0 view .LVU2455
+ 7385 005c 2268     		ldr	r2, [r4]
+4258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7386              		.loc 1 4258 19 view .LVU2456
+ 7387 005e 9369     		ldr	r3, [r2, #24]
+4258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7388              		.loc 1 4258 27 view .LVU2457
+ 7389 0060 23F44063 		bic	r3, r3, #3072
+ 7390 0064 9361     		str	r3, [r2, #24]
+4261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7391              		.loc 1 4261 5 is_stmt 1 view .LVU2458
+4261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7392              		.loc 1 4261 9 is_stmt 0 view .LVU2459
+ 7393 0066 2268     		ldr	r2, [r4]
+4261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7394              		.loc 1 4261 19 view .LVU2460
+ 7395 0068 9369     		ldr	r3, [r2, #24]
+4261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7396              		.loc 1 4261 38 view .LVU2461
+ 7397 006a A968     		ldr	r1, [r5, #8]
+4261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7398              		.loc 1 4261 27 view .LVU2462
+ 7399 006c 43EA0123 		orr	r3, r3, r1, lsl #8
+ 7400 0070 9361     		str	r3, [r2, #24]
+4221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7401              		.loc 1 4221 21 view .LVU2463
+ 7402 0072 0020     		movs	r0, #0
+ 7403 0074 D6E7     		b	.L450
+ 7404              	.LVL600:
+ 7405              	.L458:
+4266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7406              		.loc 1 4266 5 is_stmt 1 view .LVU2464
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7407              		.loc 1 4268 5 view .LVU2465
+ 7408 0076 CB68     		ldr	r3, [r1, #12]
+ 7409 0078 4A68     		ldr	r2, [r1, #4]
+ 7410              	.LVL601:
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7411              		.loc 1 4268 5 is_stmt 0 view .LVU2466
+ 7412 007a 0968     		ldr	r1, [r1]
+ 7413              	.LVL602:
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7414              		.loc 1 4268 5 view .LVU2467
+ 7415 007c 0068     		ldr	r0, [r0]
+ 7416              	.LVL603:
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7417              		.loc 1 4268 5 view .LVU2468
+ 7418 007e FFF7FEFF 		bl	TIM_TI3_SetConfig
+ 7419              	.LVL604:
+4274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7420              		.loc 1 4274 5 is_stmt 1 view .LVU2469
+ARM GAS  /tmp/cc0wMqvE.s 			page 304
+
+
+4274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7421              		.loc 1 4274 9 is_stmt 0 view .LVU2470
+ 7422 0082 2268     		ldr	r2, [r4]
+4274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7423              		.loc 1 4274 19 view .LVU2471
+ 7424 0084 D369     		ldr	r3, [r2, #28]
+4274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7425              		.loc 1 4274 27 view .LVU2472
+ 7426 0086 23F00C03 		bic	r3, r3, #12
+ 7427 008a D361     		str	r3, [r2, #28]
+4277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7428              		.loc 1 4277 5 is_stmt 1 view .LVU2473
+4277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7429              		.loc 1 4277 9 is_stmt 0 view .LVU2474
+ 7430 008c 2268     		ldr	r2, [r4]
+4277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7431              		.loc 1 4277 19 view .LVU2475
+ 7432 008e D369     		ldr	r3, [r2, #28]
+4277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7433              		.loc 1 4277 37 view .LVU2476
+ 7434 0090 A968     		ldr	r1, [r5, #8]
+4277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7435              		.loc 1 4277 27 view .LVU2477
+ 7436 0092 0B43     		orrs	r3, r3, r1
+ 7437 0094 D361     		str	r3, [r2, #28]
+4221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7438              		.loc 1 4221 21 view .LVU2478
+ 7439 0096 0020     		movs	r0, #0
+ 7440 0098 C4E7     		b	.L450
+ 7441              	.LVL605:
+ 7442              	.L459:
+4282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7443              		.loc 1 4282 5 is_stmt 1 view .LVU2479
+4284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7444              		.loc 1 4284 5 view .LVU2480
+ 7445 009a CB68     		ldr	r3, [r1, #12]
+ 7446 009c 4A68     		ldr	r2, [r1, #4]
+ 7447              	.LVL606:
+4284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7448              		.loc 1 4284 5 is_stmt 0 view .LVU2481
+ 7449 009e 0968     		ldr	r1, [r1]
+ 7450              	.LVL607:
+4284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7451              		.loc 1 4284 5 view .LVU2482
+ 7452 00a0 0068     		ldr	r0, [r0]
+ 7453              	.LVL608:
+4284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7454              		.loc 1 4284 5 view .LVU2483
+ 7455 00a2 FFF7FEFF 		bl	TIM_TI4_SetConfig
+ 7456              	.LVL609:
+4290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7457              		.loc 1 4290 5 is_stmt 1 view .LVU2484
+4290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7458              		.loc 1 4290 9 is_stmt 0 view .LVU2485
+ 7459 00a6 2268     		ldr	r2, [r4]
+4290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7460              		.loc 1 4290 19 view .LVU2486
+ARM GAS  /tmp/cc0wMqvE.s 			page 305
+
+
+ 7461 00a8 D369     		ldr	r3, [r2, #28]
+4290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7462              		.loc 1 4290 27 view .LVU2487
+ 7463 00aa 23F44063 		bic	r3, r3, #3072
+ 7464 00ae D361     		str	r3, [r2, #28]
+4293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7465              		.loc 1 4293 5 is_stmt 1 view .LVU2488
+4293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7466              		.loc 1 4293 9 is_stmt 0 view .LVU2489
+ 7467 00b0 2268     		ldr	r2, [r4]
+4293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7468              		.loc 1 4293 19 view .LVU2490
+ 7469 00b2 D369     		ldr	r3, [r2, #28]
+4293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7470              		.loc 1 4293 38 view .LVU2491
+ 7471 00b4 A968     		ldr	r1, [r5, #8]
+4293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7472              		.loc 1 4293 27 view .LVU2492
+ 7473 00b6 43EA0123 		orr	r3, r3, r1, lsl #8
+ 7474 00ba D361     		str	r3, [r2, #28]
+4221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7475              		.loc 1 4221 21 view .LVU2493
+ 7476 00bc 0020     		movs	r0, #0
+ 7477 00be B1E7     		b	.L450
+ 7478              	.LVL610:
+ 7479              	.L453:
+4231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7480              		.loc 1 4231 3 view .LVU2494
+ 7481 00c0 0220     		movs	r0, #2
+ 7482              	.LVL611:
+4231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7483              		.loc 1 4231 3 view .LVU2495
+ 7484 00c2 B2E7     		b	.L448
+ 7485              		.cfi_endproc
+ 7486              	.LFE389:
+ 7488              		.section	.text.HAL_TIM_OnePulse_ConfigChannel,"ax",%progbits
+ 7489              		.align	1
+ 7490              		.global	HAL_TIM_OnePulse_ConfigChannel
+ 7491              		.syntax unified
+ 7492              		.thumb
+ 7493              		.thumb_func
+ 7495              	HAL_TIM_OnePulse_ConfigChannel:
+ 7496              	.LVL612:
+ 7497              	.LFB391:
+4470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7498              		.loc 1 4470 1 is_stmt 1 view -0
+ 7499              		.cfi_startproc
+ 7500              		@ args = 0, pretend = 0, frame = 32
+ 7501              		@ frame_needed = 0, uses_anonymous_args = 0
+4471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_OC_InitTypeDef temp1;
+ 7502              		.loc 1 4471 3 view .LVU2497
+4472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7503              		.loc 1 4472 3 view .LVU2498
+4475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+ 7504              		.loc 1 4475 3 view .LVU2499
+4476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7505              		.loc 1 4476 3 view .LVU2500
+ARM GAS  /tmp/cc0wMqvE.s 			page 306
+
+
+4478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7506              		.loc 1 4478 3 view .LVU2501
+4478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7507              		.loc 1 4478 6 is_stmt 0 view .LVU2502
+ 7508 0000 9A42     		cmp	r2, r3
+ 7509 0002 7ED0     		beq	.L468
+4470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7510              		.loc 1 4470 1 view .LVU2503
+ 7511 0004 70B5     		push	{r4, r5, r6, lr}
+ 7512              	.LCFI68:
+ 7513              		.cfi_def_cfa_offset 16
+ 7514              		.cfi_offset 4, -16
+ 7515              		.cfi_offset 5, -12
+ 7516              		.cfi_offset 6, -8
+ 7517              		.cfi_offset 14, -4
+ 7518 0006 88B0     		sub	sp, sp, #32
+ 7519              	.LCFI69:
+ 7520              		.cfi_def_cfa_offset 48
+ 7521 0008 0446     		mov	r4, r0
+ 7522 000a 0D46     		mov	r5, r1
+ 7523 000c 1E46     		mov	r6, r3
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7524              		.loc 1 4481 5 is_stmt 1 view .LVU2504
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7525              		.loc 1 4481 5 view .LVU2505
+ 7526 000e 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 7527              	.LVL613:
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7528              		.loc 1 4481 5 is_stmt 0 view .LVU2506
+ 7529 0012 012B     		cmp	r3, #1
+ 7530 0014 77D0     		beq	.L469
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7531              		.loc 1 4481 5 is_stmt 1 discriminator 2 view .LVU2507
+ 7532 0016 0123     		movs	r3, #1
+ 7533 0018 80F83C30 		strb	r3, [r0, #60]
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7534              		.loc 1 4481 5 discriminator 2 view .LVU2508
+4483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7535              		.loc 1 4483 5 discriminator 2 view .LVU2509
+4483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7536              		.loc 1 4483 17 is_stmt 0 discriminator 2 view .LVU2510
+ 7537 001c 0223     		movs	r3, #2
+ 7538 001e 80F83D30 		strb	r3, [r0, #61]
+4486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.Pulse = sConfig->Pulse;
+ 7539              		.loc 1 4486 5 is_stmt 1 discriminator 2 view .LVU2511
+4486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.Pulse = sConfig->Pulse;
+ 7540              		.loc 1 4486 27 is_stmt 0 discriminator 2 view .LVU2512
+ 7541 0022 0B68     		ldr	r3, [r1]
+4486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.Pulse = sConfig->Pulse;
+ 7542              		.loc 1 4486 18 discriminator 2 view .LVU2513
+ 7543 0024 0193     		str	r3, [sp, #4]
+4487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCPolarity = sConfig->OCPolarity;
+ 7544              		.loc 1 4487 5 is_stmt 1 discriminator 2 view .LVU2514
+4487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCPolarity = sConfig->OCPolarity;
+ 7545              		.loc 1 4487 26 is_stmt 0 discriminator 2 view .LVU2515
+ 7546 0026 4B68     		ldr	r3, [r1, #4]
+4487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCPolarity = sConfig->OCPolarity;
+ARM GAS  /tmp/cc0wMqvE.s 			page 307
+
+
+ 7547              		.loc 1 4487 17 discriminator 2 view .LVU2516
+ 7548 0028 0293     		str	r3, [sp, #8]
+4488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCNPolarity = sConfig->OCNPolarity;
+ 7549              		.loc 1 4488 5 is_stmt 1 discriminator 2 view .LVU2517
+4488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCNPolarity = sConfig->OCNPolarity;
+ 7550              		.loc 1 4488 31 is_stmt 0 discriminator 2 view .LVU2518
+ 7551 002a 8B68     		ldr	r3, [r1, #8]
+4488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCNPolarity = sConfig->OCNPolarity;
+ 7552              		.loc 1 4488 22 discriminator 2 view .LVU2519
+ 7553 002c 0393     		str	r3, [sp, #12]
+4489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCIdleState = sConfig->OCIdleState;
+ 7554              		.loc 1 4489 5 is_stmt 1 discriminator 2 view .LVU2520
+4489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCIdleState = sConfig->OCIdleState;
+ 7555              		.loc 1 4489 32 is_stmt 0 discriminator 2 view .LVU2521
+ 7556 002e CB68     		ldr	r3, [r1, #12]
+4489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCIdleState = sConfig->OCIdleState;
+ 7557              		.loc 1 4489 23 discriminator 2 view .LVU2522
+ 7558 0030 0493     		str	r3, [sp, #16]
+4490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCNIdleState = sConfig->OCNIdleState;
+ 7559              		.loc 1 4490 5 is_stmt 1 discriminator 2 view .LVU2523
+4490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCNIdleState = sConfig->OCNIdleState;
+ 7560              		.loc 1 4490 32 is_stmt 0 discriminator 2 view .LVU2524
+ 7561 0032 0B69     		ldr	r3, [r1, #16]
+4490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     temp1.OCNIdleState = sConfig->OCNIdleState;
+ 7562              		.loc 1 4490 23 discriminator 2 view .LVU2525
+ 7563 0034 0693     		str	r3, [sp, #24]
+4491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7564              		.loc 1 4491 5 is_stmt 1 discriminator 2 view .LVU2526
+4491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7565              		.loc 1 4491 33 is_stmt 0 discriminator 2 view .LVU2527
+ 7566 0036 4B69     		ldr	r3, [r1, #20]
+4491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7567              		.loc 1 4491 24 discriminator 2 view .LVU2528
+ 7568 0038 0793     		str	r3, [sp, #28]
+4493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 7569              		.loc 1 4493 5 is_stmt 1 discriminator 2 view .LVU2529
+ 7570 003a 52B1     		cbz	r2, .L462
+4493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 7571              		.loc 1 4493 5 is_stmt 0 view .LVU2530
+ 7572 003c 042A     		cmp	r2, #4
+ 7573 003e 11D0     		beq	.L463
+ 7574 0040 0120     		movs	r0, #1
+ 7575              	.LVL614:
+ 7576              	.L464:
+4566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7577              		.loc 1 4566 5 is_stmt 1 view .LVU2531
+4566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7578              		.loc 1 4566 17 is_stmt 0 view .LVU2532
+ 7579 0042 0123     		movs	r3, #1
+ 7580 0044 84F83D30 		strb	r3, [r4, #61]
+4568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7581              		.loc 1 4568 5 is_stmt 1 view .LVU2533
+4568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7582              		.loc 1 4568 5 view .LVU2534
+ 7583 0048 0023     		movs	r3, #0
+ 7584 004a 84F83C30 		strb	r3, [r4, #60]
+4568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 308
+
+
+ 7585              		.loc 1 4568 5 view .LVU2535
+4570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7586              		.loc 1 4570 5 view .LVU2536
+ 7587              	.LVL615:
+ 7588              	.L461:
+4576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7589              		.loc 1 4576 1 is_stmt 0 view .LVU2537
+ 7590 004e 08B0     		add	sp, sp, #32
+ 7591              	.LCFI70:
+ 7592              		.cfi_remember_state
+ 7593              		.cfi_def_cfa_offset 16
+ 7594              		@ sp needed
+ 7595 0050 70BD     		pop	{r4, r5, r6, pc}
+ 7596              	.LVL616:
+ 7597              	.L462:
+ 7598              	.LCFI71:
+ 7599              		.cfi_restore_state
+4497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7600              		.loc 1 4497 9 is_stmt 1 view .LVU2538
+4499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+ 7601              		.loc 1 4499 9 view .LVU2539
+ 7602 0052 01A9     		add	r1, sp, #4
+ 7603              	.LVL617:
+4499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+ 7604              		.loc 1 4499 9 is_stmt 0 view .LVU2540
+ 7605 0054 0068     		ldr	r0, [r0]
+ 7606              	.LVL618:
+4499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+ 7607              		.loc 1 4499 9 view .LVU2541
+ 7608 0056 FFF7FEFF 		bl	TIM_OC1_SetConfig
+ 7609              	.LVL619:
+4500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 7610              		.loc 1 4500 9 is_stmt 1 view .LVU2542
+4516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 7611              		.loc 1 4516 5 view .LVU2543
+ 7612              	.L465:
+4518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7613              		.loc 1 4518 7 view .LVU2544
+ 7614 005a 46B1     		cbz	r6, .L466
+ 7615 005c 042E     		cmp	r6, #4
+ 7616 005e 2BD0     		beq	.L467
+ 7617 0060 0120     		movs	r0, #1
+ 7618 0062 EEE7     		b	.L464
+ 7619              	.LVL620:
+ 7620              	.L463:
+4505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7621              		.loc 1 4505 9 view .LVU2545
+4507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+ 7622              		.loc 1 4507 9 view .LVU2546
+ 7623 0064 01A9     		add	r1, sp, #4
+ 7624              	.LVL621:
+4507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+ 7625              		.loc 1 4507 9 is_stmt 0 view .LVU2547
+ 7626 0066 0068     		ldr	r0, [r0]
+ 7627              	.LVL622:
+4507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         break;
+ 7628              		.loc 1 4507 9 view .LVU2548
+ARM GAS  /tmp/cc0wMqvE.s 			page 309
+
+
+ 7629 0068 FFF7FEFF 		bl	TIM_OC2_SetConfig
+ 7630              	.LVL623:
+4508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 7631              		.loc 1 4508 9 is_stmt 1 view .LVU2549
+4516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 7632              		.loc 1 4516 5 view .LVU2550
+ 7633 006c F5E7     		b	.L465
+ 7634              	.L466:
+4522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7635              		.loc 1 4522 11 view .LVU2551
+4524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                             sConfig->ICSelection, sConfig->ICFilter);
+ 7636              		.loc 1 4524 11 view .LVU2552
+ 7637 006e 2B6A     		ldr	r3, [r5, #32]
+ 7638 0070 EA69     		ldr	r2, [r5, #28]
+ 7639 0072 A969     		ldr	r1, [r5, #24]
+ 7640 0074 2068     		ldr	r0, [r4]
+ 7641 0076 FFF7FEFF 		bl	TIM_TI1_SetConfig
+ 7642              	.LVL624:
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7643              		.loc 1 4528 11 view .LVU2553
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7644              		.loc 1 4528 15 is_stmt 0 view .LVU2554
+ 7645 007a 2268     		ldr	r2, [r4]
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7646              		.loc 1 4528 25 view .LVU2555
+ 7647 007c 9369     		ldr	r3, [r2, #24]
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7648              		.loc 1 4528 33 view .LVU2556
+ 7649 007e 23F00C03 		bic	r3, r3, #12
+ 7650 0082 9361     		str	r3, [r2, #24]
+4531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI1FP1;
+ 7651              		.loc 1 4531 11 is_stmt 1 view .LVU2557
+4531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI1FP1;
+ 7652              		.loc 1 4531 15 is_stmt 0 view .LVU2558
+ 7653 0084 2268     		ldr	r2, [r4]
+4531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI1FP1;
+ 7654              		.loc 1 4531 25 view .LVU2559
+ 7655 0086 9368     		ldr	r3, [r2, #8]
+4531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI1FP1;
+ 7656              		.loc 1 4531 32 view .LVU2560
+ 7657 0088 23F44013 		bic	r3, r3, #3145728
+ 7658 008c 23F07003 		bic	r3, r3, #112
+ 7659 0090 9360     		str	r3, [r2, #8]
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7660              		.loc 1 4532 11 is_stmt 1 view .LVU2561
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7661              		.loc 1 4532 15 is_stmt 0 view .LVU2562
+ 7662 0092 2268     		ldr	r2, [r4]
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7663              		.loc 1 4532 25 view .LVU2563
+ 7664 0094 9368     		ldr	r3, [r2, #8]
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7665              		.loc 1 4532 32 view .LVU2564
+ 7666 0096 43F05003 		orr	r3, r3, #80
+ 7667 009a 9360     		str	r3, [r2, #8]
+4535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7668              		.loc 1 4535 11 is_stmt 1 view .LVU2565
+ARM GAS  /tmp/cc0wMqvE.s 			page 310
+
+
+4535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7669              		.loc 1 4535 15 is_stmt 0 view .LVU2566
+ 7670 009c 2268     		ldr	r2, [r4]
+4535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7671              		.loc 1 4535 25 view .LVU2567
+ 7672 009e 9368     		ldr	r3, [r2, #8]
+4535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7673              		.loc 1 4535 32 view .LVU2568
+ 7674 00a0 23F48033 		bic	r3, r3, #65536
+ 7675 00a4 23F00703 		bic	r3, r3, #7
+ 7676 00a8 9360     		str	r3, [r2, #8]
+4536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           break;
+ 7677              		.loc 1 4536 11 is_stmt 1 view .LVU2569
+4536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           break;
+ 7678              		.loc 1 4536 15 is_stmt 0 view .LVU2570
+ 7679 00aa 2268     		ldr	r2, [r4]
+4536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           break;
+ 7680              		.loc 1 4536 25 view .LVU2571
+ 7681 00ac 9368     		ldr	r3, [r2, #8]
+4536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           break;
+ 7682              		.loc 1 4536 32 view .LVU2572
+ 7683 00ae 43F00603 		orr	r3, r3, #6
+ 7684 00b2 9360     		str	r3, [r2, #8]
+4537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 7685              		.loc 1 4537 11 is_stmt 1 view .LVU2573
+ 7686 00b4 0020     		movs	r0, #0
+ 7687 00b6 C4E7     		b	.L464
+ 7688              	.L467:
+4542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7689              		.loc 1 4542 11 view .LVU2574
+4544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                             sConfig->ICSelection, sConfig->ICFilter);
+ 7690              		.loc 1 4544 11 view .LVU2575
+ 7691 00b8 2B6A     		ldr	r3, [r5, #32]
+ 7692 00ba EA69     		ldr	r2, [r5, #28]
+ 7693 00bc A969     		ldr	r1, [r5, #24]
+ 7694 00be 2068     		ldr	r0, [r4]
+ 7695 00c0 FFF7FEFF 		bl	TIM_TI2_SetConfig
+ 7696              	.LVL625:
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7697              		.loc 1 4548 11 view .LVU2576
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7698              		.loc 1 4548 15 is_stmt 0 view .LVU2577
+ 7699 00c4 2268     		ldr	r2, [r4]
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7700              		.loc 1 4548 25 view .LVU2578
+ 7701 00c6 9369     		ldr	r3, [r2, #24]
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7702              		.loc 1 4548 33 view .LVU2579
+ 7703 00c8 23F44063 		bic	r3, r3, #3072
+ 7704 00cc 9361     		str	r3, [r2, #24]
+4551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI2FP2;
+ 7705              		.loc 1 4551 11 is_stmt 1 view .LVU2580
+4551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI2FP2;
+ 7706              		.loc 1 4551 15 is_stmt 0 view .LVU2581
+ 7707 00ce 2268     		ldr	r2, [r4]
+4551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI2FP2;
+ 7708              		.loc 1 4551 25 view .LVU2582
+ARM GAS  /tmp/cc0wMqvE.s 			page 311
+
+
+ 7709 00d0 9368     		ldr	r3, [r2, #8]
+4551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI2FP2;
+ 7710              		.loc 1 4551 32 view .LVU2583
+ 7711 00d2 23F44013 		bic	r3, r3, #3145728
+ 7712 00d6 23F07003 		bic	r3, r3, #112
+ 7713 00da 9360     		str	r3, [r2, #8]
+4552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7714              		.loc 1 4552 11 is_stmt 1 view .LVU2584
+4552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7715              		.loc 1 4552 15 is_stmt 0 view .LVU2585
+ 7716 00dc 2268     		ldr	r2, [r4]
+4552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7717              		.loc 1 4552 25 view .LVU2586
+ 7718 00de 9368     		ldr	r3, [r2, #8]
+4552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7719              		.loc 1 4552 32 view .LVU2587
+ 7720 00e0 43F06003 		orr	r3, r3, #96
+ 7721 00e4 9360     		str	r3, [r2, #8]
+4555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7722              		.loc 1 4555 11 is_stmt 1 view .LVU2588
+4555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7723              		.loc 1 4555 15 is_stmt 0 view .LVU2589
+ 7724 00e6 2268     		ldr	r2, [r4]
+4555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7725              		.loc 1 4555 25 view .LVU2590
+ 7726 00e8 9368     		ldr	r3, [r2, #8]
+4555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7727              		.loc 1 4555 32 view .LVU2591
+ 7728 00ea 23F48033 		bic	r3, r3, #65536
+ 7729 00ee 23F00703 		bic	r3, r3, #7
+ 7730 00f2 9360     		str	r3, [r2, #8]
+4556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           break;
+ 7731              		.loc 1 4556 11 is_stmt 1 view .LVU2592
+4556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           break;
+ 7732              		.loc 1 4556 15 is_stmt 0 view .LVU2593
+ 7733 00f4 2268     		ldr	r2, [r4]
+4556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           break;
+ 7734              		.loc 1 4556 25 view .LVU2594
+ 7735 00f6 9368     		ldr	r3, [r2, #8]
+4556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           break;
+ 7736              		.loc 1 4556 32 view .LVU2595
+ 7737 00f8 43F00603 		orr	r3, r3, #6
+ 7738 00fc 9360     		str	r3, [r2, #8]
+4557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 7739              		.loc 1 4557 11 is_stmt 1 view .LVU2596
+ 7740 00fe 0020     		movs	r0, #0
+ 7741 0100 9FE7     		b	.L464
+ 7742              	.LVL626:
+ 7743              	.L468:
+ 7744              	.LCFI72:
+ 7745              		.cfi_def_cfa_offset 0
+ 7746              		.cfi_restore 4
+ 7747              		.cfi_restore 5
+ 7748              		.cfi_restore 6
+ 7749              		.cfi_restore 14
+4574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 7750              		.loc 1 4574 12 is_stmt 0 view .LVU2597
+ARM GAS  /tmp/cc0wMqvE.s 			page 312
+
+
+ 7751 0102 0120     		movs	r0, #1
+ 7752              	.LVL627:
+4576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7753              		.loc 1 4576 1 view .LVU2598
+ 7754 0104 7047     		bx	lr
+ 7755              	.LVL628:
+ 7756              	.L469:
+ 7757              	.LCFI73:
+ 7758              		.cfi_def_cfa_offset 48
+ 7759              		.cfi_offset 4, -16
+ 7760              		.cfi_offset 5, -12
+ 7761              		.cfi_offset 6, -8
+ 7762              		.cfi_offset 14, -4
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7763              		.loc 1 4481 5 view .LVU2599
+ 7764 0106 0220     		movs	r0, #2
+ 7765              	.LVL629:
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7766              		.loc 1 4481 5 view .LVU2600
+ 7767 0108 A1E7     		b	.L461
+ 7768              		.cfi_endproc
+ 7769              	.LFE391:
+ 7771              		.section	.text.TIM_ETR_SetConfig,"ax",%progbits
+ 7772              		.align	1
+ 7773              		.global	TIM_ETR_SetConfig
+ 7774              		.syntax unified
+ 7775              		.thumb
+ 7776              		.thumb_func
+ 7778              	TIM_ETR_SetConfig:
+ 7779              	.LVL630:
+ 7780              	.LFB448:
+8000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+8001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Configures the TIMx External Trigger (ETR).
+8002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+8003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
+8004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+8005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+8006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+8007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+8008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+8009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
+8010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+8011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+8012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+8013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  ExtTRGFilter External Trigger Filter.
+8014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F
+8015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+8016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+8017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+8018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+8019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 7781              		.loc 1 8019 1 is_stmt 1 view -0
+ 7782              		.cfi_startproc
+ 7783              		@ args = 0, pretend = 0, frame = 0
+ 7784              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7785              		@ link register save eliminated.
+ 7786              		.loc 1 8019 1 is_stmt 0 view .LVU2602
+ARM GAS  /tmp/cc0wMqvE.s 			page 313
+
+
+ 7787 0000 10B4     		push	{r4}
+ 7788              	.LCFI74:
+ 7789              		.cfi_def_cfa_offset 4
+ 7790              		.cfi_offset 4, -4
+8020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 7791              		.loc 1 8020 3 is_stmt 1 view .LVU2603
+8021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+8022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr = TIMx->SMCR;
+ 7792              		.loc 1 8022 3 view .LVU2604
+ 7793              		.loc 1 8022 11 is_stmt 0 view .LVU2605
+ 7794 0002 8468     		ldr	r4, [r0, #8]
+ 7795              	.LVL631:
+8023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+8024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the ETR Bits */
+8025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 7796              		.loc 1 8025 3 is_stmt 1 view .LVU2606
+ 7797              		.loc 1 8025 11 is_stmt 0 view .LVU2607
+ 7798 0004 24F47F4C 		bic	ip, r4, #65280
+ 7799              	.LVL632:
+8026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+8027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Prescaler, the Filter value and the Polarity */
+8028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+ 7800              		.loc 1 8028 3 is_stmt 1 view .LVU2608
+ 7801              		.loc 1 8028 67 is_stmt 0 view .LVU2609
+ 7802 0008 42EA0322 		orr	r2, r2, r3, lsl #8
+ 7803              	.LVL633:
+ 7804              		.loc 1 8028 45 view .LVU2610
+ 7805 000c 0A43     		orrs	r2, r2, r1
+ 7806              		.loc 1 8028 11 view .LVU2611
+ 7807 000e 42EA0C02 		orr	r2, r2, ip
+ 7808              	.LVL634:
+8029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+8030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Write to TIMx SMCR */
+8031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->SMCR = tmpsmcr;
+ 7809              		.loc 1 8031 3 is_stmt 1 view .LVU2612
+ 7810              		.loc 1 8031 14 is_stmt 0 view .LVU2613
+ 7811 0012 8260     		str	r2, [r0, #8]
+8032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 7812              		.loc 1 8032 1 view .LVU2614
+ 7813 0014 5DF8044B 		ldr	r4, [sp], #4
+ 7814              	.LCFI75:
+ 7815              		.cfi_restore 4
+ 7816              		.cfi_def_cfa_offset 0
+ 7817 0018 7047     		bx	lr
+ 7818              		.cfi_endproc
+ 7819              	.LFE448:
+ 7821              		.section	.text.HAL_TIM_ConfigOCrefClear,"ax",%progbits
+ 7822              		.align	1
+ 7823              		.global	HAL_TIM_ConfigOCrefClear
+ 7824              		.syntax unified
+ 7825              		.thumb
+ 7826              		.thumb_func
+ 7828              	HAL_TIM_ConfigOCrefClear:
+ 7829              	.LVL635:
+ 7830              	.LFB399:
+5350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7831              		.loc 1 5350 1 is_stmt 1 view -0
+ARM GAS  /tmp/cc0wMqvE.s 			page 314
+
+
+ 7832              		.cfi_startproc
+ 7833              		@ args = 0, pretend = 0, frame = 0
+ 7834              		@ frame_needed = 0, uses_anonymous_args = 0
+5351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7835              		.loc 1 5351 3 view .LVU2616
+5354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+ 7836              		.loc 1 5354 3 view .LVU2617
+5355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7837              		.loc 1 5355 3 view .LVU2618
+5358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7838              		.loc 1 5358 3 view .LVU2619
+5358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7839              		.loc 1 5358 3 view .LVU2620
+ 7840 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 7841 0004 012B     		cmp	r3, #1
+ 7842 0006 00F02881 		beq	.L501
+5350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7843              		.loc 1 5350 1 is_stmt 0 discriminator 2 view .LVU2621
+ 7844 000a 70B5     		push	{r4, r5, r6, lr}
+ 7845              	.LCFI76:
+ 7846              		.cfi_def_cfa_offset 16
+ 7847              		.cfi_offset 4, -16
+ 7848              		.cfi_offset 5, -12
+ 7849              		.cfi_offset 6, -8
+ 7850              		.cfi_offset 14, -4
+ 7851 000c 0446     		mov	r4, r0
+ 7852 000e 0D46     		mov	r5, r1
+ 7853 0010 1646     		mov	r6, r2
+5358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7854              		.loc 1 5358 3 is_stmt 1 discriminator 2 view .LVU2622
+ 7855 0012 0123     		movs	r3, #1
+ 7856 0014 80F83C30 		strb	r3, [r0, #60]
+5358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7857              		.loc 1 5358 3 discriminator 2 view .LVU2623
+5360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7858              		.loc 1 5360 3 discriminator 2 view .LVU2624
+5360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7859              		.loc 1 5360 15 is_stmt 0 discriminator 2 view .LVU2625
+ 7860 0018 0223     		movs	r3, #2
+ 7861 001a 80F83D30 		strb	r3, [r0, #61]
+5362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7862              		.loc 1 5362 3 is_stmt 1 discriminator 2 view .LVU2626
+5362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7863              		.loc 1 5362 28 is_stmt 0 discriminator 2 view .LVU2627
+ 7864 001e 4B68     		ldr	r3, [r1, #4]
+5362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7865              		.loc 1 5362 3 discriminator 2 view .LVU2628
+ 7866 0020 B3F5003F 		cmp	r3, #131072
+ 7867 0024 5BD0     		beq	.L478
+5362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7868              		.loc 1 5362 3 view .LVU2629
+ 7869 0026 0ED8     		bhi	.L479
+ 7870 0028 012B     		cmp	r3, #1
+ 7871 002a 7FD0     		beq	.L480
+ 7872 002c B3F5803F 		cmp	r3, #65536
+ 7873 0030 55D0     		beq	.L478
+ 7874 0032 002B     		cmp	r3, #0
+ARM GAS  /tmp/cc0wMqvE.s 			page 315
+
+
+ 7875 0034 53D0     		beq	.L478
+ 7876 0036 0120     		movs	r0, #1
+ 7877              	.LVL636:
+ 7878              	.L481:
+5535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7879              		.loc 1 5535 3 is_stmt 1 view .LVU2630
+5535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7880              		.loc 1 5535 15 is_stmt 0 view .LVU2631
+ 7881 0038 0123     		movs	r3, #1
+ 7882 003a 84F83D30 		strb	r3, [r4, #61]
+5537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7883              		.loc 1 5537 3 is_stmt 1 view .LVU2632
+5537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7884              		.loc 1 5537 3 view .LVU2633
+ 7885 003e 0023     		movs	r3, #0
+ 7886 0040 84F83C30 		strb	r3, [r4, #60]
+5537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7887              		.loc 1 5537 3 view .LVU2634
+5539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 7888              		.loc 1 5539 3 view .LVU2635
+ 7889              	.L477:
+5540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7890              		.loc 1 5540 1 is_stmt 0 view .LVU2636
+ 7891 0044 70BD     		pop	{r4, r5, r6, pc}
+ 7892              	.LVL637:
+ 7893              	.L479:
+5362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7894              		.loc 1 5362 3 view .LVU2637
+ 7895 0046 B3F5403F 		cmp	r3, #196608
+ 7896 004a 48D0     		beq	.L478
+ 7897 004c B3F1FF3F 		cmp	r3, #-1
+ 7898 0050 40F0FF80 		bne	.L502
+5367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7899              		.loc 1 5367 7 is_stmt 1 view .LVU2638
+5367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7900              		.loc 1 5367 11 is_stmt 0 view .LVU2639
+ 7901 0054 0368     		ldr	r3, [r0]
+5367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7902              		.loc 1 5367 10 view .LVU2640
+ 7903 0056 824A     		ldr	r2, .L508
+ 7904              	.LVL638:
+5367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7905              		.loc 1 5367 10 view .LVU2641
+ 7906 0058 9342     		cmp	r3, r2
+ 7907 005a 1BD0     		beq	.L482
+5367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7908              		.loc 1 5367 11 discriminator 1 view .LVU2642
+ 7909 005c B3F1804F 		cmp	r3, #1073741824
+ 7910 0060 18D0     		beq	.L482
+5367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7911              		.loc 1 5367 11 discriminator 2 view .LVU2643
+ 7912 0062 A2F59432 		sub	r2, r2, #75776
+ 7913 0066 9342     		cmp	r3, r2
+ 7914 0068 14D0     		beq	.L482
+5367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7915              		.loc 1 5367 11 discriminator 3 view .LVU2644
+ 7916 006a 02F59832 		add	r2, r2, #77824
+ARM GAS  /tmp/cc0wMqvE.s 			page 316
+
+
+ 7917 006e 9342     		cmp	r3, r2
+ 7918 0070 10D0     		beq	.L482
+5367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7919              		.loc 1 5367 11 discriminator 4 view .LVU2645
+ 7920 0072 02F54062 		add	r2, r2, #3072
+ 7921 0076 9342     		cmp	r3, r2
+ 7922 0078 0CD0     		beq	.L482
+5367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7923              		.loc 1 5367 11 discriminator 5 view .LVU2646
+ 7924 007a 02F58062 		add	r2, r2, #1024
+ 7925 007e 9342     		cmp	r3, r2
+ 7926 0080 08D0     		beq	.L482
+5367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7927              		.loc 1 5367 11 discriminator 6 view .LVU2647
+ 7928 0082 02F58062 		add	r2, r2, #1024
+ 7929 0086 9342     		cmp	r3, r2
+ 7930 0088 04D0     		beq	.L482
+5376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 7931              		.loc 1 5376 9 is_stmt 1 view .LVU2648
+ 7932 008a 9A68     		ldr	r2, [r3, #8]
+ 7933 008c 22F47F42 		bic	r2, r2, #65280
+ 7934 0090 9A60     		str	r2, [r3, #8]
+5442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7935              		.loc 1 5442 3 view .LVU2649
+ 7936 0092 0AE0     		b	.L484
+ 7937              	.L482:
+5369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 7938              		.loc 1 5369 9 view .LVU2650
+ 7939 0094 9A68     		ldr	r2, [r3, #8]
+ 7940 0096 22F47F42 		bic	r2, r2, #65280
+ 7941 009a 22F00802 		bic	r2, r2, #8
+ 7942 009e 9A60     		str	r2, [r3, #8]
+5372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 7943              		.loc 1 5372 9 view .LVU2651
+ 7944 00a0 2268     		ldr	r2, [r4]
+ 7945 00a2 536E     		ldr	r3, [r2, #100]
+ 7946 00a4 23F4E023 		bic	r3, r3, #458752
+ 7947 00a8 5366     		str	r3, [r2, #100]
+5442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 7948              		.loc 1 5442 3 view .LVU2652
+ 7949              	.LVL639:
+ 7950              	.L484:
+5444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 7951              		.loc 1 5444 5 view .LVU2653
+ 7952 00aa 142E     		cmp	r6, #20
+ 7953 00ac 00F2D380 		bhi	.L503
+ 7954 00b0 DFE816F0 		tbh	[pc, r6, lsl #1]
+ 7955              	.L489:
+ 7956 00b4 6F00     		.2byte	(.L494-.L489)/2
+ 7957 00b6 D100     		.2byte	(.L503-.L489)/2
+ 7958 00b8 D100     		.2byte	(.L503-.L489)/2
+ 7959 00ba D100     		.2byte	(.L503-.L489)/2
+ 7960 00bc 7F00     		.2byte	(.L493-.L489)/2
+ 7961 00be D100     		.2byte	(.L503-.L489)/2
+ 7962 00c0 D100     		.2byte	(.L503-.L489)/2
+ 7963 00c2 D100     		.2byte	(.L503-.L489)/2
+ 7964 00c4 8F00     		.2byte	(.L492-.L489)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 317
+
+
+ 7965 00c6 D100     		.2byte	(.L503-.L489)/2
+ 7966 00c8 D100     		.2byte	(.L503-.L489)/2
+ 7967 00ca D100     		.2byte	(.L503-.L489)/2
+ 7968 00cc 9F00     		.2byte	(.L491-.L489)/2
+ 7969 00ce D100     		.2byte	(.L503-.L489)/2
+ 7970 00d0 D100     		.2byte	(.L503-.L489)/2
+ 7971 00d2 D100     		.2byte	(.L503-.L489)/2
+ 7972 00d4 AF00     		.2byte	(.L490-.L489)/2
+ 7973 00d6 D100     		.2byte	(.L503-.L489)/2
+ 7974 00d8 D100     		.2byte	(.L503-.L489)/2
+ 7975 00da D100     		.2byte	(.L503-.L489)/2
+ 7976 00dc BF00     		.2byte	(.L488-.L489)/2
+ 7977              	.LVL640:
+ 7978              		.p2align 1
+ 7979              	.L478:
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7980              		.loc 1 5395 7 view .LVU2654
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7981              		.loc 1 5395 11 is_stmt 0 view .LVU2655
+ 7982 00de 2368     		ldr	r3, [r4]
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7983              		.loc 1 5395 10 view .LVU2656
+ 7984 00e0 5F4A     		ldr	r2, .L508
+ 7985              	.LVL641:
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7986              		.loc 1 5395 10 view .LVU2657
+ 7987 00e2 9342     		cmp	r3, r2
+ 7988 00e4 16D0     		beq	.L485
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7989              		.loc 1 5395 11 discriminator 1 view .LVU2658
+ 7990 00e6 B3F1804F 		cmp	r3, #1073741824
+ 7991 00ea 13D0     		beq	.L485
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7992              		.loc 1 5395 11 discriminator 2 view .LVU2659
+ 7993 00ec A2F59432 		sub	r2, r2, #75776
+ 7994 00f0 9342     		cmp	r3, r2
+ 7995 00f2 0FD0     		beq	.L485
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 7996              		.loc 1 5395 11 discriminator 3 view .LVU2660
+ 7997 00f4 02F59832 		add	r2, r2, #77824
+ 7998 00f8 9342     		cmp	r3, r2
+ 7999 00fa 0BD0     		beq	.L485
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8000              		.loc 1 5395 11 discriminator 4 view .LVU2661
+ 8001 00fc 02F54062 		add	r2, r2, #3072
+ 8002 0100 9342     		cmp	r3, r2
+ 8003 0102 07D0     		beq	.L485
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8004              		.loc 1 5395 11 discriminator 5 view .LVU2662
+ 8005 0104 02F58062 		add	r2, r2, #1024
+ 8006 0108 9342     		cmp	r3, r2
+ 8007 010a 03D0     		beq	.L485
+5395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8008              		.loc 1 5395 11 discriminator 6 view .LVU2663
+ 8009 010c 02F58062 		add	r2, r2, #1024
+ 8010 0110 9342     		cmp	r3, r2
+ 8011 0112 CAD1     		bne	.L484
+ARM GAS  /tmp/cc0wMqvE.s 			page 318
+
+
+ 8012              	.L485:
+5398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8013              		.loc 1 5398 9 is_stmt 1 view .LVU2664
+ 8014 0114 9A68     		ldr	r2, [r3, #8]
+ 8015 0116 22F00802 		bic	r2, r2, #8
+ 8016 011a 9A60     		str	r2, [r3, #8]
+5401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 8017              		.loc 1 5401 9 view .LVU2665
+ 8018 011c 2268     		ldr	r2, [r4]
+ 8019 011e 536E     		ldr	r3, [r2, #100]
+ 8020 0120 23F4E023 		bic	r3, r3, #458752
+ 8021 0124 6968     		ldr	r1, [r5, #4]
+ 8022              	.LVL642:
+5401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 8023              		.loc 1 5401 9 is_stmt 0 view .LVU2666
+ 8024 0126 0B43     		orrs	r3, r3, r1
+ 8025 0128 5366     		str	r3, [r2, #100]
+5442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8026              		.loc 1 5442 3 is_stmt 1 view .LVU2667
+ 8027 012a BEE7     		b	.L484
+ 8028              	.LVL643:
+ 8029              	.L480:
+5409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ 8030              		.loc 1 5409 7 view .LVU2668
+5410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+ 8031              		.loc 1 5410 7 view .LVU2669
+5411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8032              		.loc 1 5411 7 view .LVU2670
+5414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8033              		.loc 1 5414 7 view .LVU2671
+5414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8034              		.loc 1 5414 28 is_stmt 0 view .LVU2672
+ 8035 012c C968     		ldr	r1, [r1, #12]
+ 8036              	.LVL644:
+5414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8037              		.loc 1 5414 10 view .LVU2673
+ 8038 012e 31B1     		cbz	r1, .L486
+5416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         __HAL_UNLOCK(htim);
+ 8039              		.loc 1 5416 9 is_stmt 1 view .LVU2674
+5416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         __HAL_UNLOCK(htim);
+ 8040              		.loc 1 5416 21 is_stmt 0 view .LVU2675
+ 8041 0130 0120     		movs	r0, #1
+ 8042              	.LVL645:
+5416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         __HAL_UNLOCK(htim);
+ 8043              		.loc 1 5416 21 view .LVU2676
+ 8044 0132 84F83D00 		strb	r0, [r4, #61]
+5417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+ 8045              		.loc 1 5417 9 is_stmt 1 view .LVU2677
+5417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+ 8046              		.loc 1 5417 9 view .LVU2678
+ 8047 0136 0023     		movs	r3, #0
+ 8048 0138 84F83C30 		strb	r3, [r4, #60]
+5417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         return HAL_ERROR;
+ 8049              		.loc 1 5417 9 view .LVU2679
+5418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 8050              		.loc 1 5418 9 view .LVU2680
+5418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ARM GAS  /tmp/cc0wMqvE.s 			page 319
+
+
+ 8051              		.loc 1 5418 16 is_stmt 0 view .LVU2681
+ 8052 013c 82E7     		b	.L477
+ 8053              	.LVL646:
+ 8054              	.L486:
+5421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClearInputConfig->ClearInputPrescaler,
+ 8055              		.loc 1 5421 7 is_stmt 1 view .LVU2682
+ 8056 013e 2B69     		ldr	r3, [r5, #16]
+ 8057 0140 AA68     		ldr	r2, [r5, #8]
+ 8058              	.LVL647:
+5421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClearInputConfig->ClearInputPrescaler,
+ 8059              		.loc 1 5421 7 is_stmt 0 view .LVU2683
+ 8060 0142 0068     		ldr	r0, [r0]
+ 8061              	.LVL648:
+5421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClearInputConfig->ClearInputPrescaler,
+ 8062              		.loc 1 5421 7 view .LVU2684
+ 8063 0144 FFF7FEFF 		bl	TIM_ETR_SetConfig
+ 8064              	.LVL649:
+5426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8065              		.loc 1 5426 7 is_stmt 1 view .LVU2685
+5426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8066              		.loc 1 5426 11 is_stmt 0 view .LVU2686
+ 8067 0148 2368     		ldr	r3, [r4]
+5426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8068              		.loc 1 5426 10 view .LVU2687
+ 8069 014a 454A     		ldr	r2, .L508
+ 8070 014c 9342     		cmp	r3, r2
+ 8071 014e 16D0     		beq	.L487
+5426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8072              		.loc 1 5426 11 discriminator 1 view .LVU2688
+ 8073 0150 B3F1804F 		cmp	r3, #1073741824
+ 8074 0154 13D0     		beq	.L487
+5426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8075              		.loc 1 5426 11 discriminator 2 view .LVU2689
+ 8076 0156 A2F59432 		sub	r2, r2, #75776
+ 8077 015a 9342     		cmp	r3, r2
+ 8078 015c 0FD0     		beq	.L487
+5426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8079              		.loc 1 5426 11 discriminator 3 view .LVU2690
+ 8080 015e 02F59832 		add	r2, r2, #77824
+ 8081 0162 9342     		cmp	r3, r2
+ 8082 0164 0BD0     		beq	.L487
+5426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8083              		.loc 1 5426 11 discriminator 4 view .LVU2691
+ 8084 0166 02F54062 		add	r2, r2, #3072
+ 8085 016a 9342     		cmp	r3, r2
+ 8086 016c 07D0     		beq	.L487
+5426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8087              		.loc 1 5426 11 discriminator 5 view .LVU2692
+ 8088 016e 02F58062 		add	r2, r2, #1024
+ 8089 0172 9342     		cmp	r3, r2
+ 8090 0174 03D0     		beq	.L487
+5426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 8091              		.loc 1 5426 11 discriminator 6 view .LVU2693
+ 8092 0176 02F58062 		add	r2, r2, #1024
+ 8093 017a 9342     		cmp	r3, r2
+ 8094 017c 95D1     		bne	.L484
+ 8095              	.L487:
+ARM GAS  /tmp/cc0wMqvE.s 			page 320
+
+
+5429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8096              		.loc 1 5429 9 is_stmt 1 view .LVU2694
+ 8097 017e 9A68     		ldr	r2, [r3, #8]
+ 8098 0180 42F00802 		orr	r2, r2, #8
+ 8099 0184 9A60     		str	r2, [r3, #8]
+5432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 8100              		.loc 1 5432 9 view .LVU2695
+ 8101 0186 2268     		ldr	r2, [r4]
+ 8102 0188 536E     		ldr	r3, [r2, #100]
+ 8103 018a 23F4E023 		bic	r3, r3, #458752
+ 8104 018e 5366     		str	r3, [r2, #100]
+5442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8105              		.loc 1 5442 3 view .LVU2696
+ 8106 0190 8BE7     		b	.L484
+ 8107              	.LVL650:
+ 8108              	.L494:
+5448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8109              		.loc 1 5448 9 view .LVU2697
+5448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8110              		.loc 1 5448 30 is_stmt 0 view .LVU2698
+ 8111 0192 2B68     		ldr	r3, [r5]
+5448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8112              		.loc 1 5448 12 view .LVU2699
+ 8113 0194 33B1     		cbz	r3, .L495
+5451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 8114              		.loc 1 5451 11 is_stmt 1 view .LVU2700
+ 8115 0196 2268     		ldr	r2, [r4]
+ 8116 0198 9369     		ldr	r3, [r2, #24]
+ 8117 019a 43F08003 		orr	r3, r3, #128
+ 8118 019e 9361     		str	r3, [r2, #24]
+ 8119 01a0 0020     		movs	r0, #0
+ 8120 01a2 49E7     		b	.L481
+ 8121              	.L495:
+5456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 8122              		.loc 1 5456 11 view .LVU2701
+ 8123 01a4 2268     		ldr	r2, [r4]
+ 8124 01a6 9369     		ldr	r3, [r2, #24]
+ 8125 01a8 23F08003 		bic	r3, r3, #128
+ 8126 01ac 9361     		str	r3, [r2, #24]
+ 8127 01ae 0020     		movs	r0, #0
+ 8128 01b0 42E7     		b	.L481
+ 8129              	.L493:
+5462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8130              		.loc 1 5462 9 view .LVU2702
+5462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8131              		.loc 1 5462 30 is_stmt 0 view .LVU2703
+ 8132 01b2 2B68     		ldr	r3, [r5]
+5462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8133              		.loc 1 5462 12 view .LVU2704
+ 8134 01b4 33B1     		cbz	r3, .L496
+5465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 8135              		.loc 1 5465 11 is_stmt 1 view .LVU2705
+ 8136 01b6 2268     		ldr	r2, [r4]
+ 8137 01b8 9369     		ldr	r3, [r2, #24]
+ 8138 01ba 43F40043 		orr	r3, r3, #32768
+ 8139 01be 9361     		str	r3, [r2, #24]
+ 8140 01c0 0020     		movs	r0, #0
+ARM GAS  /tmp/cc0wMqvE.s 			page 321
+
+
+ 8141 01c2 39E7     		b	.L481
+ 8142              	.L496:
+5470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 8143              		.loc 1 5470 11 view .LVU2706
+ 8144 01c4 2268     		ldr	r2, [r4]
+ 8145 01c6 9369     		ldr	r3, [r2, #24]
+ 8146 01c8 23F40043 		bic	r3, r3, #32768
+ 8147 01cc 9361     		str	r3, [r2, #24]
+ 8148 01ce 0020     		movs	r0, #0
+ 8149 01d0 32E7     		b	.L481
+ 8150              	.L492:
+5476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8151              		.loc 1 5476 9 view .LVU2707
+5476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8152              		.loc 1 5476 30 is_stmt 0 view .LVU2708
+ 8153 01d2 2B68     		ldr	r3, [r5]
+5476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8154              		.loc 1 5476 12 view .LVU2709
+ 8155 01d4 33B1     		cbz	r3, .L497
+5479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 8156              		.loc 1 5479 11 is_stmt 1 view .LVU2710
+ 8157 01d6 2268     		ldr	r2, [r4]
+ 8158 01d8 D369     		ldr	r3, [r2, #28]
+ 8159 01da 43F08003 		orr	r3, r3, #128
+ 8160 01de D361     		str	r3, [r2, #28]
+ 8161 01e0 0020     		movs	r0, #0
+ 8162 01e2 29E7     		b	.L481
+ 8163              	.L497:
+5484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 8164              		.loc 1 5484 11 view .LVU2711
+ 8165 01e4 2268     		ldr	r2, [r4]
+ 8166 01e6 D369     		ldr	r3, [r2, #28]
+ 8167 01e8 23F08003 		bic	r3, r3, #128
+ 8168 01ec D361     		str	r3, [r2, #28]
+ 8169 01ee 0020     		movs	r0, #0
+ 8170 01f0 22E7     		b	.L481
+ 8171              	.L491:
+5490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8172              		.loc 1 5490 9 view .LVU2712
+5490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8173              		.loc 1 5490 30 is_stmt 0 view .LVU2713
+ 8174 01f2 2B68     		ldr	r3, [r5]
+5490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8175              		.loc 1 5490 12 view .LVU2714
+ 8176 01f4 33B1     		cbz	r3, .L498
+5493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 8177              		.loc 1 5493 11 is_stmt 1 view .LVU2715
+ 8178 01f6 2268     		ldr	r2, [r4]
+ 8179 01f8 D369     		ldr	r3, [r2, #28]
+ 8180 01fa 43F40043 		orr	r3, r3, #32768
+ 8181 01fe D361     		str	r3, [r2, #28]
+ 8182 0200 0020     		movs	r0, #0
+ 8183 0202 19E7     		b	.L481
+ 8184              	.L498:
+5498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 8185              		.loc 1 5498 11 view .LVU2716
+ 8186 0204 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/cc0wMqvE.s 			page 322
+
+
+ 8187 0206 D369     		ldr	r3, [r2, #28]
+ 8188 0208 23F40043 		bic	r3, r3, #32768
+ 8189 020c D361     		str	r3, [r2, #28]
+ 8190 020e 0020     		movs	r0, #0
+ 8191 0210 12E7     		b	.L481
+ 8192              	.L490:
+5504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8193              		.loc 1 5504 9 view .LVU2717
+5504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8194              		.loc 1 5504 30 is_stmt 0 view .LVU2718
+ 8195 0212 2B68     		ldr	r3, [r5]
+5504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8196              		.loc 1 5504 12 view .LVU2719
+ 8197 0214 33B1     		cbz	r3, .L499
+5507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 8198              		.loc 1 5507 11 is_stmt 1 view .LVU2720
+ 8199 0216 2268     		ldr	r2, [r4]
+ 8200 0218 136D     		ldr	r3, [r2, #80]
+ 8201 021a 43F08003 		orr	r3, r3, #128
+ 8202 021e 1365     		str	r3, [r2, #80]
+ 8203 0220 0020     		movs	r0, #0
+ 8204 0222 09E7     		b	.L481
+ 8205              	.L499:
+5512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 8206              		.loc 1 5512 11 view .LVU2721
+ 8207 0224 2268     		ldr	r2, [r4]
+ 8208 0226 136D     		ldr	r3, [r2, #80]
+ 8209 0228 23F08003 		bic	r3, r3, #128
+ 8210 022c 1365     		str	r3, [r2, #80]
+ 8211 022e 0020     		movs	r0, #0
+ 8212 0230 02E7     		b	.L481
+ 8213              	.L488:
+5518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8214              		.loc 1 5518 9 view .LVU2722
+5518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8215              		.loc 1 5518 30 is_stmt 0 view .LVU2723
+ 8216 0232 2B68     		ldr	r3, [r5]
+5518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         {
+ 8217              		.loc 1 5518 12 view .LVU2724
+ 8218 0234 33B1     		cbz	r3, .L500
+5521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 8219              		.loc 1 5521 11 is_stmt 1 view .LVU2725
+ 8220 0236 2268     		ldr	r2, [r4]
+ 8221 0238 136D     		ldr	r3, [r2, #80]
+ 8222 023a 43F40043 		orr	r3, r3, #32768
+ 8223 023e 1365     		str	r3, [r2, #80]
+ 8224 0240 0020     		movs	r0, #0
+ 8225 0242 F9E6     		b	.L481
+ 8226              	.L500:
+5526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         }
+ 8227              		.loc 1 5526 11 view .LVU2726
+ 8228 0244 2268     		ldr	r2, [r4]
+ 8229 0246 136D     		ldr	r3, [r2, #80]
+ 8230 0248 23F40043 		bic	r3, r3, #32768
+ 8231 024c 1365     		str	r3, [r2, #80]
+ 8232 024e 0020     		movs	r0, #0
+ 8233 0250 F2E6     		b	.L481
+ARM GAS  /tmp/cc0wMqvE.s 			page 323
+
+
+ 8234              	.LVL651:
+ 8235              	.L502:
+5362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8236              		.loc 1 5362 3 is_stmt 0 view .LVU2727
+ 8237 0252 0120     		movs	r0, #1
+ 8238              	.LVL652:
+5362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8239              		.loc 1 5362 3 view .LVU2728
+ 8240 0254 F0E6     		b	.L481
+ 8241              	.LVL653:
+ 8242              	.L503:
+5444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 8243              		.loc 1 5444 5 view .LVU2729
+ 8244 0256 0020     		movs	r0, #0
+ 8245 0258 EEE6     		b	.L481
+ 8246              	.LVL654:
+ 8247              	.L501:
+ 8248              	.LCFI77:
+ 8249              		.cfi_def_cfa_offset 0
+ 8250              		.cfi_restore 4
+ 8251              		.cfi_restore 5
+ 8252              		.cfi_restore 6
+ 8253              		.cfi_restore 14
+5358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8254              		.loc 1 5358 3 view .LVU2730
+ 8255 025a 0220     		movs	r0, #2
+ 8256              	.LVL655:
+5540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8257              		.loc 1 5540 1 view .LVU2731
+ 8258 025c 7047     		bx	lr
+ 8259              	.L509:
+ 8260 025e 00BF     		.align	2
+ 8261              	.L508:
+ 8262 0260 002C0140 		.word	1073818624
+ 8263              		.cfi_endproc
+ 8264              	.LFE399:
+ 8266              		.section	.text.HAL_TIM_ConfigClockSource,"ax",%progbits
+ 8267              		.align	1
+ 8268              		.global	HAL_TIM_ConfigClockSource
+ 8269              		.syntax unified
+ 8270              		.thumb
+ 8271              		.thumb_func
+ 8273              	HAL_TIM_ConfigClockSource:
+ 8274              	.LVL656:
+ 8275              	.LFB400:
+5550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 8276              		.loc 1 5550 1 is_stmt 1 view -0
+ 8277              		.cfi_startproc
+ 8278              		@ args = 0, pretend = 0, frame = 0
+ 8279              		@ frame_needed = 0, uses_anonymous_args = 0
+5551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8280              		.loc 1 5551 3 view .LVU2733
+5552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8281              		.loc 1 5552 3 view .LVU2734
+5555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8282              		.loc 1 5555 3 view .LVU2735
+5555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 324
+
+
+ 8283              		.loc 1 5555 3 view .LVU2736
+ 8284 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 8285 0004 012B     		cmp	r3, #1
+ 8286 0006 00F08F80 		beq	.L524
+5550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 8287              		.loc 1 5550 1 is_stmt 0 discriminator 2 view .LVU2737
+ 8288 000a 10B5     		push	{r4, lr}
+ 8289              	.LCFI78:
+ 8290              		.cfi_def_cfa_offset 8
+ 8291              		.cfi_offset 4, -8
+ 8292              		.cfi_offset 14, -4
+ 8293 000c 0446     		mov	r4, r0
+5555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8294              		.loc 1 5555 3 is_stmt 1 discriminator 2 view .LVU2738
+ 8295 000e 0123     		movs	r3, #1
+ 8296 0010 80F83C30 		strb	r3, [r0, #60]
+5555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8297              		.loc 1 5555 3 discriminator 2 view .LVU2739
+5557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8298              		.loc 1 5557 3 discriminator 2 view .LVU2740
+5557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8299              		.loc 1 5557 15 is_stmt 0 discriminator 2 view .LVU2741
+ 8300 0014 0223     		movs	r3, #2
+ 8301 0016 80F83D30 		strb	r3, [r0, #61]
+5560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8302              		.loc 1 5560 3 is_stmt 1 discriminator 2 view .LVU2742
+5563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ 8303              		.loc 1 5563 3 discriminator 2 view .LVU2743
+5563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ 8304              		.loc 1 5563 17 is_stmt 0 discriminator 2 view .LVU2744
+ 8305 001a 0268     		ldr	r2, [r0]
+5563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ 8306              		.loc 1 5563 11 discriminator 2 view .LVU2745
+ 8307 001c 9068     		ldr	r0, [r2, #8]
+ 8308              	.LVL657:
+5564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 8309              		.loc 1 5564 3 is_stmt 1 discriminator 2 view .LVU2746
+5565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Instance->SMCR = tmpsmcr;
+ 8310              		.loc 1 5565 3 discriminator 2 view .LVU2747
+5565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   htim->Instance->SMCR = tmpsmcr;
+ 8311              		.loc 1 5565 11 is_stmt 0 discriminator 2 view .LVU2748
+ 8312 001e 434B     		ldr	r3, .L538
+ 8313 0020 0340     		ands	r3, r3, r0
+ 8314              	.LVL658:
+5566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8315              		.loc 1 5566 3 is_stmt 1 discriminator 2 view .LVU2749
+5566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8316              		.loc 1 5566 24 is_stmt 0 discriminator 2 view .LVU2750
+ 8317 0022 9360     		str	r3, [r2, #8]
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8318              		.loc 1 5568 3 is_stmt 1 discriminator 2 view .LVU2751
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8319              		.loc 1 5568 29 is_stmt 0 discriminator 2 view .LVU2752
+ 8320 0024 0B68     		ldr	r3, [r1]
+ 8321              	.LVL659:
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8322              		.loc 1 5568 3 discriminator 2 view .LVU2753
+ARM GAS  /tmp/cc0wMqvE.s 			page 325
+
+
+ 8323 0026 702B     		cmp	r3, #112
+ 8324 0028 55D0     		beq	.L512
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8325              		.loc 1 5568 3 view .LVU2754
+ 8326 002a 31D8     		bhi	.L513
+ 8327 002c 502B     		cmp	r3, #80
+ 8328 002e 6CD0     		beq	.L514
+ 8329 0030 0CD9     		bls	.L531
+ 8330 0032 602B     		cmp	r3, #96
+ 8331 0034 2AD1     		bne	.L532
+5639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8332              		.loc 1 5639 7 is_stmt 1 view .LVU2755
+5642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+ 8333              		.loc 1 5642 7 view .LVU2756
+5643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8334              		.loc 1 5643 7 view .LVU2757
+5645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8335              		.loc 1 5645 7 view .LVU2758
+ 8336 0036 CA68     		ldr	r2, [r1, #12]
+ 8337              	.LVL660:
+5645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8338              		.loc 1 5645 7 is_stmt 0 view .LVU2759
+ 8339 0038 4968     		ldr	r1, [r1, #4]
+ 8340              	.LVL661:
+5645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8341              		.loc 1 5645 7 view .LVU2760
+ 8342 003a 2068     		ldr	r0, [r4]
+ 8343              	.LVL662:
+5645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8344              		.loc 1 5645 7 view .LVU2761
+ 8345 003c FFF7FEFF 		bl	TIM_TI2_ConfigInputStage
+ 8346              	.LVL663:
+5648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8347              		.loc 1 5648 7 is_stmt 1 view .LVU2762
+ 8348 0040 6021     		movs	r1, #96
+ 8349 0042 2068     		ldr	r0, [r4]
+ 8350 0044 FFF7FEFF 		bl	TIM_ITRx_SetConfig
+ 8351              	.LVL664:
+5649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8352              		.loc 1 5649 7 view .LVU2763
+5551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8353              		.loc 1 5551 21 is_stmt 0 view .LVU2764
+ 8354 0048 0020     		movs	r0, #0
+5649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8355              		.loc 1 5649 7 view .LVU2765
+ 8356 004a 35E0     		b	.L517
+ 8357              	.LVL665:
+ 8358              	.L531:
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8359              		.loc 1 5568 3 view .LVU2766
+ 8360 004c 402B     		cmp	r3, #64
+ 8361 004e 0AD1     		bne	.L533
+5655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8362              		.loc 1 5655 7 is_stmt 1 view .LVU2767
+5658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+ 8363              		.loc 1 5658 7 view .LVU2768
+5659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 326
+
+
+ 8364              		.loc 1 5659 7 view .LVU2769
+5661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8365              		.loc 1 5661 7 view .LVU2770
+ 8366 0050 CA68     		ldr	r2, [r1, #12]
+ 8367              	.LVL666:
+5661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8368              		.loc 1 5661 7 is_stmt 0 view .LVU2771
+ 8369 0052 4968     		ldr	r1, [r1, #4]
+ 8370              	.LVL667:
+5661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8371              		.loc 1 5661 7 view .LVU2772
+ 8372 0054 2068     		ldr	r0, [r4]
+ 8373              	.LVL668:
+5661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8374              		.loc 1 5661 7 view .LVU2773
+ 8375 0056 FFF7FEFF 		bl	TIM_TI1_ConfigInputStage
+ 8376              	.LVL669:
+5664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8377              		.loc 1 5664 7 is_stmt 1 view .LVU2774
+ 8378 005a 4021     		movs	r1, #64
+ 8379 005c 2068     		ldr	r0, [r4]
+ 8380 005e FFF7FEFF 		bl	TIM_ITRx_SetConfig
+ 8381              	.LVL670:
+5665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8382              		.loc 1 5665 7 view .LVU2775
+5551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8383              		.loc 1 5551 21 is_stmt 0 view .LVU2776
+ 8384 0062 0020     		movs	r0, #0
+5665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8385              		.loc 1 5665 7 view .LVU2777
+ 8386 0064 28E0     		b	.L517
+ 8387              	.LVL671:
+ 8388              	.L533:
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8389              		.loc 1 5568 3 view .LVU2778
+ 8390 0066 5BD8     		bhi	.L525
+ 8391 0068 202B     		cmp	r3, #32
+ 8392 006a 07D0     		beq	.L518
+ 8393 006c 03D9     		bls	.L534
+ 8394 006e 302B     		cmp	r3, #48
+ 8395 0070 04D0     		beq	.L518
+5695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8396              		.loc 1 5695 14 view .LVU2779
+ 8397 0072 0120     		movs	r0, #1
+ 8398 0074 20E0     		b	.L517
+ 8399              	.L534:
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8400              		.loc 1 5568 3 view .LVU2780
+ 8401 0076 0BB1     		cbz	r3, .L518
+ 8402 0078 102B     		cmp	r3, #16
+ 8403 007a 05D1     		bne	.L535
+ 8404              	.LVL672:
+ 8405              	.L518:
+5688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8406              		.loc 1 5688 7 is_stmt 1 view .LVU2781
+5690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8407              		.loc 1 5690 7 view .LVU2782
+ARM GAS  /tmp/cc0wMqvE.s 			page 327
+
+
+ 8408 007c 1946     		mov	r1, r3
+ 8409              	.LVL673:
+5690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8410              		.loc 1 5690 7 is_stmt 0 view .LVU2783
+ 8411 007e 2068     		ldr	r0, [r4]
+ 8412              	.LVL674:
+5690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8413              		.loc 1 5690 7 view .LVU2784
+ 8414 0080 FFF7FEFF 		bl	TIM_ITRx_SetConfig
+ 8415              	.LVL675:
+5691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8416              		.loc 1 5691 7 is_stmt 1 view .LVU2785
+5551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8417              		.loc 1 5551 21 is_stmt 0 view .LVU2786
+ 8418 0084 0020     		movs	r0, #0
+5691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8419              		.loc 1 5691 7 view .LVU2787
+ 8420 0086 17E0     		b	.L517
+ 8421              	.LVL676:
+ 8422              	.L535:
+5695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8423              		.loc 1 5695 14 view .LVU2788
+ 8424 0088 0120     		movs	r0, #1
+ 8425 008a 15E0     		b	.L517
+ 8426              	.L532:
+ 8427 008c 0120     		movs	r0, #1
+ 8428 008e 13E0     		b	.L517
+ 8429              	.L513:
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8430              		.loc 1 5568 3 view .LVU2789
+ 8431 0090 B3F5005F 		cmp	r3, #8192
+ 8432 0094 2CD0     		beq	.L521
+ 8433 0096 0BD9     		bls	.L536
+ 8434 0098 254A     		ldr	r2, .L538+4
+ 8435              	.LVL677:
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8436              		.loc 1 5568 3 view .LVU2790
+ 8437 009a 9342     		cmp	r3, r2
+ 8438 009c EED0     		beq	.L518
+ 8439 009e 12D9     		bls	.L537
+ 8440 00a0 244A     		ldr	r2, .L538+8
+ 8441 00a2 9342     		cmp	r3, r2
+ 8442 00a4 EAD0     		beq	.L518
+ 8443 00a6 3032     		adds	r2, r2, #48
+ 8444 00a8 9342     		cmp	r3, r2
+ 8445 00aa E7D0     		beq	.L518
+5695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8446              		.loc 1 5695 14 view .LVU2791
+ 8447 00ac 0120     		movs	r0, #1
+ 8448              	.LVL678:
+5695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8449              		.loc 1 5695 14 view .LVU2792
+ 8450 00ae 03E0     		b	.L517
+ 8451              	.LVL679:
+ 8452              	.L536:
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8453              		.loc 1 5568 3 view .LVU2793
+ARM GAS  /tmp/cc0wMqvE.s 			page 328
+
+
+ 8454 00b0 B3F5805F 		cmp	r3, #4096
+ 8455 00b4 36D1     		bne	.L526
+ 8456 00b6 0020     		movs	r0, #0
+ 8457              	.LVL680:
+ 8458              	.L517:
+5698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8459              		.loc 1 5698 3 is_stmt 1 view .LVU2794
+5698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8460              		.loc 1 5698 15 is_stmt 0 view .LVU2795
+ 8461 00b8 0123     		movs	r3, #1
+ 8462 00ba 84F83D30 		strb	r3, [r4, #61]
+5700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8463              		.loc 1 5700 3 is_stmt 1 view .LVU2796
+5700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8464              		.loc 1 5700 3 view .LVU2797
+ 8465 00be 0023     		movs	r3, #0
+ 8466 00c0 84F83C30 		strb	r3, [r4, #60]
+5700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8467              		.loc 1 5700 3 view .LVU2798
+5702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 8468              		.loc 1 5702 3 view .LVU2799
+5703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8469              		.loc 1 5703 1 is_stmt 0 view .LVU2800
+ 8470 00c4 10BD     		pop	{r4, pc}
+ 8471              	.LVL681:
+ 8472              	.L537:
+5568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8473              		.loc 1 5568 3 view .LVU2801
+ 8474 00c6 B3F1101F 		cmp	r3, #1048592
+ 8475 00ca D7D0     		beq	.L518
+ 8476 00cc 103A     		subs	r2, r2, #16
+ 8477 00ce 9342     		cmp	r3, r2
+ 8478 00d0 D4D0     		beq	.L518
+5695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8479              		.loc 1 5695 14 view .LVU2802
+ 8480 00d2 0120     		movs	r0, #1
+ 8481              	.LVL682:
+5695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8482              		.loc 1 5695 14 view .LVU2803
+ 8483 00d4 F0E7     		b	.L517
+ 8484              	.LVL683:
+ 8485              	.L512:
+5579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8486              		.loc 1 5579 7 is_stmt 1 view .LVU2804
+5582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ 8487              		.loc 1 5582 7 view .LVU2805
+5583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+ 8488              		.loc 1 5583 7 view .LVU2806
+5584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8489              		.loc 1 5584 7 view .LVU2807
+5587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8490              		.loc 1 5587 7 view .LVU2808
+ 8491 00d6 CB68     		ldr	r3, [r1, #12]
+ 8492 00d8 4A68     		ldr	r2, [r1, #4]
+ 8493              	.LVL684:
+5587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8494              		.loc 1 5587 7 is_stmt 0 view .LVU2809
+ARM GAS  /tmp/cc0wMqvE.s 			page 329
+
+
+ 8495 00da 8968     		ldr	r1, [r1, #8]
+ 8496              	.LVL685:
+5587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8497              		.loc 1 5587 7 view .LVU2810
+ 8498 00dc 2068     		ldr	r0, [r4]
+ 8499              	.LVL686:
+5587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8500              		.loc 1 5587 7 view .LVU2811
+ 8501 00de FFF7FEFF 		bl	TIM_ETR_SetConfig
+ 8502              	.LVL687:
+5593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 8503              		.loc 1 5593 7 is_stmt 1 view .LVU2812
+5593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 8504              		.loc 1 5593 21 is_stmt 0 view .LVU2813
+ 8505 00e2 2268     		ldr	r2, [r4]
+5593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 8506              		.loc 1 5593 15 view .LVU2814
+ 8507 00e4 9368     		ldr	r3, [r2, #8]
+ 8508              	.LVL688:
+5594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Write to TIMx SMCR */
+ 8509              		.loc 1 5594 7 is_stmt 1 view .LVU2815
+5594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Write to TIMx SMCR */
+ 8510              		.loc 1 5594 15 is_stmt 0 view .LVU2816
+ 8511 00e6 43F07703 		orr	r3, r3, #119
+ 8512              	.LVL689:
+5596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8513              		.loc 1 5596 7 is_stmt 1 view .LVU2817
+5596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8514              		.loc 1 5596 28 is_stmt 0 view .LVU2818
+ 8515 00ea 9360     		str	r3, [r2, #8]
+5597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8516              		.loc 1 5597 7 is_stmt 1 view .LVU2819
+5551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8517              		.loc 1 5551 21 is_stmt 0 view .LVU2820
+ 8518 00ec 0020     		movs	r0, #0
+5597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8519              		.loc 1 5597 7 view .LVU2821
+ 8520 00ee E3E7     		b	.L517
+ 8521              	.LVL690:
+ 8522              	.L521:
+5603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8523              		.loc 1 5603 7 is_stmt 1 view .LVU2822
+5606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ 8524              		.loc 1 5606 7 view .LVU2823
+5607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+ 8525              		.loc 1 5607 7 view .LVU2824
+5608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8526              		.loc 1 5608 7 view .LVU2825
+5611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8527              		.loc 1 5611 7 view .LVU2826
+ 8528 00f0 CB68     		ldr	r3, [r1, #12]
+ 8529 00f2 4A68     		ldr	r2, [r1, #4]
+ 8530              	.LVL691:
+5611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8531              		.loc 1 5611 7 is_stmt 0 view .LVU2827
+ 8532 00f4 8968     		ldr	r1, [r1, #8]
+ 8533              	.LVL692:
+ARM GAS  /tmp/cc0wMqvE.s 			page 330
+
+
+5611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8534              		.loc 1 5611 7 view .LVU2828
+ 8535 00f6 2068     		ldr	r0, [r4]
+ 8536              	.LVL693:
+5611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8537              		.loc 1 5611 7 view .LVU2829
+ 8538 00f8 FFF7FEFF 		bl	TIM_ETR_SetConfig
+ 8539              	.LVL694:
+5616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8540              		.loc 1 5616 7 is_stmt 1 view .LVU2830
+5616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8541              		.loc 1 5616 11 is_stmt 0 view .LVU2831
+ 8542 00fc 2268     		ldr	r2, [r4]
+5616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8543              		.loc 1 5616 21 view .LVU2832
+ 8544 00fe 9368     		ldr	r3, [r2, #8]
+5616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8545              		.loc 1 5616 28 view .LVU2833
+ 8546 0100 43F48043 		orr	r3, r3, #16384
+ 8547 0104 9360     		str	r3, [r2, #8]
+5617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8548              		.loc 1 5617 7 is_stmt 1 view .LVU2834
+5551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8549              		.loc 1 5551 21 is_stmt 0 view .LVU2835
+ 8550 0106 0020     		movs	r0, #0
+5617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8551              		.loc 1 5617 7 view .LVU2836
+ 8552 0108 D6E7     		b	.L517
+ 8553              	.LVL695:
+ 8554              	.L514:
+5623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8555              		.loc 1 5623 7 is_stmt 1 view .LVU2837
+5626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+ 8556              		.loc 1 5626 7 view .LVU2838
+5627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8557              		.loc 1 5627 7 view .LVU2839
+5629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8558              		.loc 1 5629 7 view .LVU2840
+ 8559 010a CA68     		ldr	r2, [r1, #12]
+ 8560              	.LVL696:
+5629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8561              		.loc 1 5629 7 is_stmt 0 view .LVU2841
+ 8562 010c 4968     		ldr	r1, [r1, #4]
+ 8563              	.LVL697:
+5629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8564              		.loc 1 5629 7 view .LVU2842
+ 8565 010e 2068     		ldr	r0, [r4]
+ 8566              	.LVL698:
+5629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8567              		.loc 1 5629 7 view .LVU2843
+ 8568 0110 FFF7FEFF 		bl	TIM_TI1_ConfigInputStage
+ 8569              	.LVL699:
+5632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8570              		.loc 1 5632 7 is_stmt 1 view .LVU2844
+ 8571 0114 5021     		movs	r1, #80
+ 8572 0116 2068     		ldr	r0, [r4]
+ 8573 0118 FFF7FEFF 		bl	TIM_ITRx_SetConfig
+ARM GAS  /tmp/cc0wMqvE.s 			page 331
+
+
+ 8574              	.LVL700:
+5633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8575              		.loc 1 5633 7 view .LVU2845
+5551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8576              		.loc 1 5551 21 is_stmt 0 view .LVU2846
+ 8577 011c 0020     		movs	r0, #0
+5633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8578              		.loc 1 5633 7 view .LVU2847
+ 8579 011e CBE7     		b	.L517
+ 8580              	.LVL701:
+ 8581              	.L525:
+5695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8582              		.loc 1 5695 14 view .LVU2848
+ 8583 0120 0120     		movs	r0, #1
+ 8584 0122 C9E7     		b	.L517
+ 8585              	.L526:
+ 8586 0124 0120     		movs	r0, #1
+ 8587 0126 C7E7     		b	.L517
+ 8588              	.LVL702:
+ 8589              	.L524:
+ 8590              	.LCFI79:
+ 8591              		.cfi_def_cfa_offset 0
+ 8592              		.cfi_restore 4
+ 8593              		.cfi_restore 14
+5555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8594              		.loc 1 5555 3 view .LVU2849
+ 8595 0128 0220     		movs	r0, #2
+ 8596              	.LVL703:
+5703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8597              		.loc 1 5703 1 view .LVU2850
+ 8598 012a 7047     		bx	lr
+ 8599              	.L539:
+ 8600              		.align	2
+ 8601              	.L538:
+ 8602 012c 8800CEFF 		.word	-3276664
+ 8603 0130 30001000 		.word	1048624
+ 8604 0134 40001000 		.word	1048640
+ 8605              		.cfi_endproc
+ 8606              	.LFE400:
+ 8608              		.section	.text.TIM_SlaveTimer_SetConfig,"ax",%progbits
+ 8609              		.align	1
+ 8610              		.syntax unified
+ 8611              		.thumb
+ 8612              		.thumb_func
+ 8614              	TIM_SlaveTimer_SetConfig:
+ 8615              	.LVL704:
+ 8616              	.LFB440:
+7565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 8617              		.loc 1 7565 1 is_stmt 1 view -0
+ 8618              		.cfi_startproc
+ 8619              		@ args = 0, pretend = 0, frame = 0
+ 8620              		@ frame_needed = 0, uses_anonymous_args = 0
+7565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 8621              		.loc 1 7565 1 is_stmt 0 view .LVU2852
+ 8622 0000 10B5     		push	{r4, lr}
+ 8623              	.LCFI80:
+ 8624              		.cfi_def_cfa_offset 8
+ARM GAS  /tmp/cc0wMqvE.s 			page 332
+
+
+ 8625              		.cfi_offset 4, -8
+ 8626              		.cfi_offset 14, -4
+7566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8627              		.loc 1 7566 3 is_stmt 1 view .LVU2853
+ 8628              	.LVL705:
+7567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 8629              		.loc 1 7567 3 view .LVU2854
+7568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpccer;
+ 8630              		.loc 1 7568 3 view .LVU2855
+7569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8631              		.loc 1 7569 3 view .LVU2856
+7572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8632              		.loc 1 7572 3 view .LVU2857
+7572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8633              		.loc 1 7572 17 is_stmt 0 view .LVU2858
+ 8634 0002 0468     		ldr	r4, [r0]
+7572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8635              		.loc 1 7572 11 view .LVU2859
+ 8636 0004 A268     		ldr	r2, [r4, #8]
+ 8637              	.LVL706:
+7575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Input Trigger source */
+ 8638              		.loc 1 7575 3 is_stmt 1 view .LVU2860
+7575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Input Trigger source */
+ 8639              		.loc 1 7575 11 is_stmt 0 view .LVU2861
+ 8640 0006 22F44012 		bic	r2, r2, #3145728
+ 8641              	.LVL707:
+7575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the Input Trigger source */
+ 8642              		.loc 1 7575 11 view .LVU2862
+ 8643 000a 22F07002 		bic	r2, r2, #112
+ 8644              	.LVL708:
+7577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8645              		.loc 1 7577 3 is_stmt 1 view .LVU2863
+7577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8646              		.loc 1 7577 26 is_stmt 0 view .LVU2864
+ 8647 000e 4B68     		ldr	r3, [r1, #4]
+7577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8648              		.loc 1 7577 11 view .LVU2865
+ 8649 0010 1343     		orrs	r3, r3, r2
+ 8650              	.LVL709:
+7580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the slave mode */
+ 8651              		.loc 1 7580 3 is_stmt 1 view .LVU2866
+7580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the slave mode */
+ 8652              		.loc 1 7580 11 is_stmt 0 view .LVU2867
+ 8653 0012 23F48033 		bic	r3, r3, #65536
+ 8654              	.LVL710:
+7580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set the slave mode */
+ 8655              		.loc 1 7580 11 view .LVU2868
+ 8656 0016 23F00703 		bic	r3, r3, #7
+ 8657              	.LVL711:
+7582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8658              		.loc 1 7582 3 is_stmt 1 view .LVU2869
+7582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8659              		.loc 1 7582 26 is_stmt 0 view .LVU2870
+ 8660 001a 0A68     		ldr	r2, [r1]
+7582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8661              		.loc 1 7582 11 view .LVU2871
+ 8662 001c 1A43     		orrs	r2, r2, r3
+ARM GAS  /tmp/cc0wMqvE.s 			page 333
+
+
+ 8663              	.LVL712:
+7585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8664              		.loc 1 7585 3 is_stmt 1 view .LVU2872
+7585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8665              		.loc 1 7585 24 is_stmt 0 view .LVU2873
+ 8666 001e A260     		str	r2, [r4, #8]
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8667              		.loc 1 7588 3 is_stmt 1 view .LVU2874
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8668              		.loc 1 7588 23 is_stmt 0 view .LVU2875
+ 8669 0020 4B68     		ldr	r3, [r1, #4]
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8670              		.loc 1 7588 3 view .LVU2876
+ 8671 0022 602B     		cmp	r3, #96
+ 8672 0024 56D0     		beq	.L541
+ 8673 0026 1CD8     		bhi	.L542
+ 8674 0028 402B     		cmp	r3, #64
+ 8675 002a 3BD0     		beq	.L543
+ 8676 002c 08D9     		bls	.L563
+ 8677 002e 502B     		cmp	r3, #80
+ 8678 0030 15D1     		bne	.L564
+7635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ 8679              		.loc 1 7635 7 is_stmt 1 view .LVU2877
+7636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ 8680              		.loc 1 7636 7 view .LVU2878
+7637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8681              		.loc 1 7637 7 view .LVU2879
+7640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8682              		.loc 1 7640 7 view .LVU2880
+ 8683 0032 0A69     		ldr	r2, [r1, #16]
+ 8684              	.LVL713:
+7640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8685              		.loc 1 7640 7 is_stmt 0 view .LVU2881
+ 8686 0034 8968     		ldr	r1, [r1, #8]
+ 8687              	.LVL714:
+7640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8688              		.loc 1 7640 7 view .LVU2882
+ 8689 0036 0068     		ldr	r0, [r0]
+ 8690              	.LVL715:
+7640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8691              		.loc 1 7640 7 view .LVU2883
+ 8692 0038 FFF7FEFF 		bl	TIM_TI1_ConfigInputStage
+ 8693              	.LVL716:
+7643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8694              		.loc 1 7643 7 is_stmt 1 view .LVU2884
+7566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8695              		.loc 1 7566 21 is_stmt 0 view .LVU2885
+ 8696 003c 0020     		movs	r0, #0
+7643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8697              		.loc 1 7643 7 view .LVU2886
+ 8698 003e 0BE0     		b	.L545
+ 8699              	.LVL717:
+ 8700              	.L563:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8701              		.loc 1 7588 3 view .LVU2887
+ 8702 0040 202B     		cmp	r3, #32
+ 8703 0042 4ED0     		beq	.L550
+ARM GAS  /tmp/cc0wMqvE.s 			page 334
+
+
+ 8704 0044 03D9     		bls	.L565
+ 8705 0046 302B     		cmp	r3, #48
+ 8706 0048 07D0     		beq	.L566
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8707              		.loc 1 7685 14 view .LVU2888
+ 8708 004a 0120     		movs	r0, #1
+ 8709              	.LVL718:
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8710              		.loc 1 7685 14 view .LVU2889
+ 8711 004c 04E0     		b	.L545
+ 8712              	.LVL719:
+ 8713              	.L565:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8714              		.loc 1 7588 3 view .LVU2890
+ 8715 004e 002B     		cmp	r3, #0
+ 8716 0050 49D0     		beq	.L551
+ 8717 0052 102B     		cmp	r3, #16
+ 8718 0054 49D1     		bne	.L552
+ 8719 0056 0020     		movs	r0, #0
+ 8720              	.LVL720:
+ 8721              	.L545:
+7690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8722              		.loc 1 7690 1 view .LVU2891
+ 8723 0058 10BD     		pop	{r4, pc}
+ 8724              	.LVL721:
+ 8725              	.L566:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8726              		.loc 1 7588 3 view .LVU2892
+ 8727 005a 0020     		movs	r0, #0
+ 8728              	.LVL722:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8729              		.loc 1 7588 3 view .LVU2893
+ 8730 005c FCE7     		b	.L545
+ 8731              	.LVL723:
+ 8732              	.L564:
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8733              		.loc 1 7685 14 view .LVU2894
+ 8734 005e 0120     		movs	r0, #1
+ 8735              	.LVL724:
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8736              		.loc 1 7685 14 view .LVU2895
+ 8737 0060 FAE7     		b	.L545
+ 8738              	.LVL725:
+ 8739              	.L542:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8740              		.loc 1 7588 3 view .LVU2896
+ 8741 0062 702B     		cmp	r3, #112
+ 8742 0064 16D0     		beq	.L548
+ 8743 0066 01D2     		bcs	.L567
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8744              		.loc 1 7685 14 view .LVU2897
+ 8745 0068 0120     		movs	r0, #1
+ 8746              	.LVL726:
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8747              		.loc 1 7685 14 view .LVU2898
+ 8748 006a F5E7     		b	.L545
+ 8749              	.LVL727:
+ARM GAS  /tmp/cc0wMqvE.s 			page 335
+
+
+ 8750              	.L567:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8751              		.loc 1 7588 3 view .LVU2899
+ 8752 006c 274A     		ldr	r2, .L569
+ 8753              	.LVL728:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8754              		.loc 1 7588 3 view .LVU2900
+ 8755 006e 9342     		cmp	r3, r2
+ 8756 0070 3DD0     		beq	.L555
+ 8757 0072 07D9     		bls	.L568
+ 8758 0074 264A     		ldr	r2, .L569+4
+ 8759 0076 9342     		cmp	r3, r2
+ 8760 0078 3FD0     		beq	.L558
+ 8761 007a 3032     		adds	r2, r2, #48
+ 8762 007c 9342     		cmp	r3, r2
+ 8763 007e 3ED1     		bne	.L559
+ 8764 0080 0020     		movs	r0, #0
+ 8765              	.LVL729:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8766              		.loc 1 7588 3 view .LVU2901
+ 8767 0082 E9E7     		b	.L545
+ 8768              	.LVL730:
+ 8769              	.L568:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8770              		.loc 1 7588 3 view .LVU2902
+ 8771 0084 B3F1101F 		cmp	r3, #1048592
+ 8772 0088 33D0     		beq	.L556
+ 8773 008a 103A     		subs	r2, r2, #16
+ 8774 008c 9342     		cmp	r3, r2
+ 8775 008e 32D1     		bne	.L557
+ 8776 0090 0020     		movs	r0, #0
+ 8777              	.LVL731:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8778              		.loc 1 7588 3 view .LVU2903
+ 8779 0092 E1E7     		b	.L545
+ 8780              	.LVL732:
+ 8781              	.L548:
+7593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+ 8782              		.loc 1 7593 7 is_stmt 1 view .LVU2904
+7594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ 8783              		.loc 1 7594 7 view .LVU2905
+7595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ 8784              		.loc 1 7595 7 view .LVU2906
+7596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Configure the ETR Trigger source */
+ 8785              		.loc 1 7596 7 view .LVU2907
+7598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sSlaveConfig->TriggerPrescaler,
+ 8786              		.loc 1 7598 7 view .LVU2908
+ 8787 0094 0B69     		ldr	r3, [r1, #16]
+ 8788 0096 8A68     		ldr	r2, [r1, #8]
+ 8789              	.LVL733:
+7598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sSlaveConfig->TriggerPrescaler,
+ 8790              		.loc 1 7598 7 is_stmt 0 view .LVU2909
+ 8791 0098 C968     		ldr	r1, [r1, #12]
+ 8792              	.LVL734:
+7598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sSlaveConfig->TriggerPrescaler,
+ 8793              		.loc 1 7598 7 view .LVU2910
+ 8794 009a 0068     		ldr	r0, [r0]
+ARM GAS  /tmp/cc0wMqvE.s 			page 336
+
+
+ 8795              	.LVL735:
+7598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                         sSlaveConfig->TriggerPrescaler,
+ 8796              		.loc 1 7598 7 view .LVU2911
+ 8797 009c FFF7FEFF 		bl	TIM_ETR_SetConfig
+ 8798              	.LVL736:
+7602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8799              		.loc 1 7602 7 is_stmt 1 view .LVU2912
+7566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8800              		.loc 1 7566 21 is_stmt 0 view .LVU2913
+ 8801 00a0 0020     		movs	r0, #0
+7602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8802              		.loc 1 7602 7 view .LVU2914
+ 8803 00a2 D9E7     		b	.L545
+ 8804              	.LVL737:
+ 8805              	.L543:
+7608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ 8806              		.loc 1 7608 7 is_stmt 1 view .LVU2915
+7609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8807              		.loc 1 7609 7 view .LVU2916
+7611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
+ 8808              		.loc 1 7611 7 view .LVU2917
+7611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
+ 8809              		.loc 1 7611 24 is_stmt 0 view .LVU2918
+ 8810 00a4 0B68     		ldr	r3, [r1]
+7611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
+ 8811              		.loc 1 7611 10 view .LVU2919
+ 8812 00a6 052B     		cmp	r3, #5
+ 8813 00a8 2BD0     		beq	.L560
+7611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****           (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
+ 8814              		.loc 1 7611 60 discriminator 1 view .LVU2920
+ 8815 00aa B3F1011F 		cmp	r3, #65537
+ 8816 00ae 2AD0     		beq	.L561
+7618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ 8817              		.loc 1 7618 7 is_stmt 1 view .LVU2921
+7618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ 8818              		.loc 1 7618 21 is_stmt 0 view .LVU2922
+ 8819 00b0 0368     		ldr	r3, [r0]
+7618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ 8820              		.loc 1 7618 15 view .LVU2923
+ 8821 00b2 1C6A     		ldr	r4, [r3, #32]
+ 8822              	.LVL738:
+7619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpccmr1 = htim->Instance->CCMR1;
+ 8823              		.loc 1 7619 7 is_stmt 1 view .LVU2924
+7619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpccmr1 = htim->Instance->CCMR1;
+ 8824              		.loc 1 7619 21 is_stmt 0 view .LVU2925
+ 8825 00b4 1A6A     		ldr	r2, [r3, #32]
+ 8826              	.LVL739:
+7619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpccmr1 = htim->Instance->CCMR1;
+ 8827              		.loc 1 7619 28 view .LVU2926
+ 8828 00b6 22F00102 		bic	r2, r2, #1
+ 8829 00ba 1A62     		str	r2, [r3, #32]
+7620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8830              		.loc 1 7620 7 is_stmt 1 view .LVU2927
+7620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8831              		.loc 1 7620 22 is_stmt 0 view .LVU2928
+ 8832 00bc 0268     		ldr	r2, [r0]
+7620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 337
+
+
+ 8833              		.loc 1 7620 16 view .LVU2929
+ 8834 00be 9369     		ldr	r3, [r2, #24]
+ 8835              	.LVL740:
+7623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+ 8836              		.loc 1 7623 7 is_stmt 1 view .LVU2930
+7623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+ 8837              		.loc 1 7623 16 is_stmt 0 view .LVU2931
+ 8838 00c0 23F0F003 		bic	r3, r3, #240
+ 8839              	.LVL741:
+7624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8840              		.loc 1 7624 7 is_stmt 1 view .LVU2932
+7624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8841              		.loc 1 7624 33 is_stmt 0 view .LVU2933
+ 8842 00c4 0969     		ldr	r1, [r1, #16]
+ 8843              	.LVL742:
+7624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8844              		.loc 1 7624 16 view .LVU2934
+ 8845 00c6 43EA0113 		orr	r3, r3, r1, lsl #4
+ 8846              	.LVL743:
+7627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCER = tmpccer;
+ 8847              		.loc 1 7627 7 is_stmt 1 view .LVU2935
+7627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->Instance->CCER = tmpccer;
+ 8848              		.loc 1 7627 29 is_stmt 0 view .LVU2936
+ 8849 00ca 9361     		str	r3, [r2, #24]
+7628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8850              		.loc 1 7628 7 is_stmt 1 view .LVU2937
+7628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8851              		.loc 1 7628 11 is_stmt 0 view .LVU2938
+ 8852 00cc 0368     		ldr	r3, [r0]
+ 8853              	.LVL744:
+7628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8854              		.loc 1 7628 28 view .LVU2939
+ 8855 00ce 1C62     		str	r4, [r3, #32]
+ 8856              	.LVL745:
+7629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8857              		.loc 1 7629 7 is_stmt 1 view .LVU2940
+7566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8858              		.loc 1 7566 21 is_stmt 0 view .LVU2941
+ 8859 00d0 0020     		movs	r0, #0
+ 8860              	.LVL746:
+7629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8861              		.loc 1 7629 7 view .LVU2942
+ 8862 00d2 C1E7     		b	.L545
+ 8863              	.LVL747:
+ 8864              	.L541:
+7649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ 8865              		.loc 1 7649 7 is_stmt 1 view .LVU2943
+7650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ 8866              		.loc 1 7650 7 view .LVU2944
+7651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8867              		.loc 1 7651 7 view .LVU2945
+7654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8868              		.loc 1 7654 7 view .LVU2946
+ 8869 00d4 0A69     		ldr	r2, [r1, #16]
+ 8870              	.LVL748:
+7654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8871              		.loc 1 7654 7 is_stmt 0 view .LVU2947
+ARM GAS  /tmp/cc0wMqvE.s 			page 338
+
+
+ 8872 00d6 8968     		ldr	r1, [r1, #8]
+ 8873              	.LVL749:
+7654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8874              		.loc 1 7654 7 view .LVU2948
+ 8875 00d8 0068     		ldr	r0, [r0]
+ 8876              	.LVL750:
+7654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8877              		.loc 1 7654 7 view .LVU2949
+ 8878 00da FFF7FEFF 		bl	TIM_TI2_ConfigInputStage
+ 8879              	.LVL751:
+7657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8880              		.loc 1 7657 7 is_stmt 1 view .LVU2950
+7566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8881              		.loc 1 7566 21 is_stmt 0 view .LVU2951
+ 8882 00de 0020     		movs	r0, #0
+7657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 8883              		.loc 1 7657 7 view .LVU2952
+ 8884 00e0 BAE7     		b	.L545
+ 8885              	.LVL752:
+ 8886              	.L550:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8887              		.loc 1 7588 3 view .LVU2953
+ 8888 00e2 0020     		movs	r0, #0
+ 8889              	.LVL753:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8890              		.loc 1 7588 3 view .LVU2954
+ 8891 00e4 B8E7     		b	.L545
+ 8892              	.LVL754:
+ 8893              	.L551:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8894              		.loc 1 7588 3 view .LVU2955
+ 8895 00e6 0020     		movs	r0, #0
+ 8896              	.LVL755:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8897              		.loc 1 7588 3 view .LVU2956
+ 8898 00e8 B6E7     		b	.L545
+ 8899              	.LVL756:
+ 8900              	.L552:
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8901              		.loc 1 7685 14 view .LVU2957
+ 8902 00ea 0120     		movs	r0, #1
+ 8903              	.LVL757:
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8904              		.loc 1 7685 14 view .LVU2958
+ 8905 00ec B4E7     		b	.L545
+ 8906              	.LVL758:
+ 8907              	.L555:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8908              		.loc 1 7588 3 view .LVU2959
+ 8909 00ee 0020     		movs	r0, #0
+ 8910              	.LVL759:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8911              		.loc 1 7588 3 view .LVU2960
+ 8912 00f0 B2E7     		b	.L545
+ 8913              	.LVL760:
+ 8914              	.L556:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 339
+
+
+ 8915              		.loc 1 7588 3 view .LVU2961
+ 8916 00f2 0020     		movs	r0, #0
+ 8917              	.LVL761:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8918              		.loc 1 7588 3 view .LVU2962
+ 8919 00f4 B0E7     		b	.L545
+ 8920              	.LVL762:
+ 8921              	.L557:
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8922              		.loc 1 7685 14 view .LVU2963
+ 8923 00f6 0120     		movs	r0, #1
+ 8924              	.LVL763:
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8925              		.loc 1 7685 14 view .LVU2964
+ 8926 00f8 AEE7     		b	.L545
+ 8927              	.LVL764:
+ 8928              	.L558:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8929              		.loc 1 7588 3 view .LVU2965
+ 8930 00fa 0020     		movs	r0, #0
+ 8931              	.LVL765:
+7588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 8932              		.loc 1 7588 3 view .LVU2966
+ 8933 00fc ACE7     		b	.L545
+ 8934              	.LVL766:
+ 8935              	.L559:
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8936              		.loc 1 7685 14 view .LVU2967
+ 8937 00fe 0120     		movs	r0, #1
+ 8938              	.LVL767:
+7685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 8939              		.loc 1 7685 14 view .LVU2968
+ 8940 0100 AAE7     		b	.L545
+ 8941              	.LVL768:
+ 8942              	.L560:
+7614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 8943              		.loc 1 7614 16 view .LVU2969
+ 8944 0102 0120     		movs	r0, #1
+ 8945              	.LVL769:
+7614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 8946              		.loc 1 7614 16 view .LVU2970
+ 8947 0104 A8E7     		b	.L545
+ 8948              	.LVL770:
+ 8949              	.L561:
+7614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 8950              		.loc 1 7614 16 view .LVU2971
+ 8951 0106 0120     		movs	r0, #1
+ 8952              	.LVL771:
+7614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 8953              		.loc 1 7614 16 view .LVU2972
+ 8954 0108 A6E7     		b	.L545
+ 8955              	.L570:
+ 8956 010a 00BF     		.align	2
+ 8957              	.L569:
+ 8958 010c 30001000 		.word	1048624
+ 8959 0110 40001000 		.word	1048640
+ 8960              		.cfi_endproc
+ARM GAS  /tmp/cc0wMqvE.s 			page 340
+
+
+ 8961              	.LFE440:
+ 8963              		.section	.text.HAL_TIM_SlaveConfigSynchro,"ax",%progbits
+ 8964              		.align	1
+ 8965              		.global	HAL_TIM_SlaveConfigSynchro
+ 8966              		.syntax unified
+ 8967              		.thumb
+ 8968              		.thumb_func
+ 8970              	HAL_TIM_SlaveConfigSynchro:
+ 8971              	.LVL772:
+ 8972              	.LFB402:
+5750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 8973              		.loc 1 5750 1 is_stmt 1 view -0
+ 8974              		.cfi_startproc
+ 8975              		@ args = 0, pretend = 0, frame = 0
+ 8976              		@ frame_needed = 0, uses_anonymous_args = 0
+5752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ 8977              		.loc 1 5752 3 view .LVU2974
+5753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
+ 8978              		.loc 1 5753 3 view .LVU2975
+5754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8979              		.loc 1 5754 3 view .LVU2976
+5756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8980              		.loc 1 5756 3 view .LVU2977
+5756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8981              		.loc 1 5756 3 view .LVU2978
+ 8982 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 8983 0004 012B     		cmp	r3, #1
+ 8984 0006 22D0     		beq	.L574
+5750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 8985              		.loc 1 5750 1 is_stmt 0 discriminator 2 view .LVU2979
+ 8986 0008 10B5     		push	{r4, lr}
+ 8987              	.LCFI81:
+ 8988              		.cfi_def_cfa_offset 8
+ 8989              		.cfi_offset 4, -8
+ 8990              		.cfi_offset 14, -4
+ 8991 000a 0446     		mov	r4, r0
+5756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8992              		.loc 1 5756 3 is_stmt 1 discriminator 2 view .LVU2980
+ 8993 000c 0123     		movs	r3, #1
+ 8994 000e 80F83C30 		strb	r3, [r0, #60]
+5756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8995              		.loc 1 5756 3 discriminator 2 view .LVU2981
+5758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8996              		.loc 1 5758 3 discriminator 2 view .LVU2982
+5758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 8997              		.loc 1 5758 15 is_stmt 0 discriminator 2 view .LVU2983
+ 8998 0012 0223     		movs	r3, #2
+ 8999 0014 80F83D30 		strb	r3, [r0, #61]
+5760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9000              		.loc 1 5760 3 is_stmt 1 discriminator 2 view .LVU2984
+5760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9001              		.loc 1 5760 7 is_stmt 0 discriminator 2 view .LVU2985
+ 9002 0018 FFF7FEFF 		bl	TIM_SlaveTimer_SetConfig
+ 9003              	.LVL773:
+5760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9004              		.loc 1 5760 6 discriminator 2 view .LVU2986
+ 9005 001c 80B9     		cbnz	r0, .L579
+ARM GAS  /tmp/cc0wMqvE.s 			page 341
+
+
+5768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9006              		.loc 1 5768 3 is_stmt 1 view .LVU2987
+ 9007 001e 2268     		ldr	r2, [r4]
+ 9008 0020 D368     		ldr	r3, [r2, #12]
+ 9009 0022 23F04003 		bic	r3, r3, #64
+ 9010 0026 D360     		str	r3, [r2, #12]
+5771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9011              		.loc 1 5771 3 view .LVU2988
+ 9012 0028 2268     		ldr	r2, [r4]
+ 9013 002a D368     		ldr	r3, [r2, #12]
+ 9014 002c 23F48043 		bic	r3, r3, #16384
+ 9015 0030 D360     		str	r3, [r2, #12]
+5773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9016              		.loc 1 5773 3 view .LVU2989
+5773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9017              		.loc 1 5773 15 is_stmt 0 view .LVU2990
+ 9018 0032 0123     		movs	r3, #1
+ 9019 0034 84F83D30 		strb	r3, [r4, #61]
+5775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9020              		.loc 1 5775 3 is_stmt 1 view .LVU2991
+5775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9021              		.loc 1 5775 3 view .LVU2992
+ 9022 0038 0023     		movs	r3, #0
+ 9023 003a 84F83C30 		strb	r3, [r4, #60]
+5775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9024              		.loc 1 5775 3 view .LVU2993
+5777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 9025              		.loc 1 5777 3 view .LVU2994
+ 9026              	.L572:
+5778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9027              		.loc 1 5778 1 is_stmt 0 view .LVU2995
+ 9028 003e 10BD     		pop	{r4, pc}
+ 9029              	.LVL774:
+ 9030              	.L579:
+5762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+ 9031              		.loc 1 5762 5 is_stmt 1 view .LVU2996
+5762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+ 9032              		.loc 1 5762 17 is_stmt 0 view .LVU2997
+ 9033 0040 0120     		movs	r0, #1
+ 9034 0042 84F83D00 		strb	r0, [r4, #61]
+5763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 9035              		.loc 1 5763 5 is_stmt 1 view .LVU2998
+5763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 9036              		.loc 1 5763 5 view .LVU2999
+ 9037 0046 0023     		movs	r3, #0
+ 9038 0048 84F83C30 		strb	r3, [r4, #60]
+5763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 9039              		.loc 1 5763 5 view .LVU3000
+5764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9040              		.loc 1 5764 5 view .LVU3001
+5764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9041              		.loc 1 5764 12 is_stmt 0 view .LVU3002
+ 9042 004c F7E7     		b	.L572
+ 9043              	.LVL775:
+ 9044              	.L574:
+ 9045              	.LCFI82:
+ 9046              		.cfi_def_cfa_offset 0
+ARM GAS  /tmp/cc0wMqvE.s 			page 342
+
+
+ 9047              		.cfi_restore 4
+ 9048              		.cfi_restore 14
+5756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9049              		.loc 1 5756 3 view .LVU3003
+ 9050 004e 0220     		movs	r0, #2
+ 9051              	.LVL776:
+5778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9052              		.loc 1 5778 1 view .LVU3004
+ 9053 0050 7047     		bx	lr
+ 9054              		.cfi_endproc
+ 9055              	.LFE402:
+ 9057              		.section	.text.HAL_TIM_SlaveConfigSynchro_IT,"ax",%progbits
+ 9058              		.align	1
+ 9059              		.global	HAL_TIM_SlaveConfigSynchro_IT
+ 9060              		.syntax unified
+ 9061              		.thumb
+ 9062              		.thumb_func
+ 9064              	HAL_TIM_SlaveConfigSynchro_IT:
+ 9065              	.LVL777:
+ 9066              	.LFB403:
+5791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 9067              		.loc 1 5791 1 is_stmt 1 view -0
+ 9068              		.cfi_startproc
+ 9069              		@ args = 0, pretend = 0, frame = 0
+ 9070              		@ frame_needed = 0, uses_anonymous_args = 0
+5793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ 9071              		.loc 1 5793 3 view .LVU3006
+5794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
+ 9072              		.loc 1 5794 3 view .LVU3007
+5795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9073              		.loc 1 5795 3 view .LVU3008
+5797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9074              		.loc 1 5797 3 view .LVU3009
+5797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9075              		.loc 1 5797 3 view .LVU3010
+ 9076 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 9077 0004 012B     		cmp	r3, #1
+ 9078 0006 22D0     		beq	.L583
+5791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 9079              		.loc 1 5791 1 is_stmt 0 discriminator 2 view .LVU3011
+ 9080 0008 10B5     		push	{r4, lr}
+ 9081              	.LCFI83:
+ 9082              		.cfi_def_cfa_offset 8
+ 9083              		.cfi_offset 4, -8
+ 9084              		.cfi_offset 14, -4
+ 9085 000a 0446     		mov	r4, r0
+5797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9086              		.loc 1 5797 3 is_stmt 1 discriminator 2 view .LVU3012
+ 9087 000c 0123     		movs	r3, #1
+ 9088 000e 80F83C30 		strb	r3, [r0, #60]
+5797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9089              		.loc 1 5797 3 discriminator 2 view .LVU3013
+5799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9090              		.loc 1 5799 3 discriminator 2 view .LVU3014
+5799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9091              		.loc 1 5799 15 is_stmt 0 discriminator 2 view .LVU3015
+ 9092 0012 0223     		movs	r3, #2
+ARM GAS  /tmp/cc0wMqvE.s 			page 343
+
+
+ 9093 0014 80F83D30 		strb	r3, [r0, #61]
+5801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9094              		.loc 1 5801 3 is_stmt 1 discriminator 2 view .LVU3016
+5801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9095              		.loc 1 5801 7 is_stmt 0 discriminator 2 view .LVU3017
+ 9096 0018 FFF7FEFF 		bl	TIM_SlaveTimer_SetConfig
+ 9097              	.LVL778:
+5801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9098              		.loc 1 5801 6 discriminator 2 view .LVU3018
+ 9099 001c 80B9     		cbnz	r0, .L588
+5809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9100              		.loc 1 5809 3 is_stmt 1 view .LVU3019
+ 9101 001e 2268     		ldr	r2, [r4]
+ 9102 0020 D368     		ldr	r3, [r2, #12]
+ 9103 0022 43F04003 		orr	r3, r3, #64
+ 9104 0026 D360     		str	r3, [r2, #12]
+5812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9105              		.loc 1 5812 3 view .LVU3020
+ 9106 0028 2268     		ldr	r2, [r4]
+ 9107 002a D368     		ldr	r3, [r2, #12]
+ 9108 002c 23F48043 		bic	r3, r3, #16384
+ 9109 0030 D360     		str	r3, [r2, #12]
+5814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9110              		.loc 1 5814 3 view .LVU3021
+5814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9111              		.loc 1 5814 15 is_stmt 0 view .LVU3022
+ 9112 0032 0123     		movs	r3, #1
+ 9113 0034 84F83D30 		strb	r3, [r4, #61]
+5816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9114              		.loc 1 5816 3 is_stmt 1 view .LVU3023
+5816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9115              		.loc 1 5816 3 view .LVU3024
+ 9116 0038 0023     		movs	r3, #0
+ 9117 003a 84F83C30 		strb	r3, [r4, #60]
+5816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9118              		.loc 1 5816 3 view .LVU3025
+5818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 9119              		.loc 1 5818 3 view .LVU3026
+ 9120              	.L581:
+5819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9121              		.loc 1 5819 1 is_stmt 0 view .LVU3027
+ 9122 003e 10BD     		pop	{r4, pc}
+ 9123              	.LVL779:
+ 9124              	.L588:
+5803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+ 9125              		.loc 1 5803 5 is_stmt 1 view .LVU3028
+5803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+ 9126              		.loc 1 5803 17 is_stmt 0 view .LVU3029
+ 9127 0040 0120     		movs	r0, #1
+ 9128 0042 84F83D00 		strb	r0, [r4, #61]
+5804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 9129              		.loc 1 5804 5 is_stmt 1 view .LVU3030
+5804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ 9130              		.loc 1 5804 5 view .LVU3031
+ 9131 0046 0023     		movs	r3, #0
+ 9132 0048 84F83C30 		strb	r3, [r4, #60]
+5804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     return HAL_ERROR;
+ARM GAS  /tmp/cc0wMqvE.s 			page 344
+
+
+ 9133              		.loc 1 5804 5 view .LVU3032
+5805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9134              		.loc 1 5805 5 view .LVU3033
+5805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9135              		.loc 1 5805 12 is_stmt 0 view .LVU3034
+ 9136 004c F7E7     		b	.L581
+ 9137              	.LVL780:
+ 9138              	.L583:
+ 9139              	.LCFI84:
+ 9140              		.cfi_def_cfa_offset 0
+ 9141              		.cfi_restore 4
+ 9142              		.cfi_restore 14
+5797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9143              		.loc 1 5797 3 view .LVU3035
+ 9144 004e 0220     		movs	r0, #2
+ 9145              	.LVL781:
+5819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9146              		.loc 1 5819 1 view .LVU3036
+ 9147 0050 7047     		bx	lr
+ 9148              		.cfi_endproc
+ 9149              	.LFE403:
+ 9151              		.section	.text.TIM_CCxChannelCmd,"ax",%progbits
+ 9152              		.align	1
+ 9153              		.global	TIM_CCxChannelCmd
+ 9154              		.syntax unified
+ 9155              		.thumb
+ 9156              		.thumb_func
+ 9158              	TIM_CCxChannelCmd:
+ 9159              	.LVL782:
+ 9160              	.LFB449:
+8033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+8034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+8035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @brief  Enables or disables the TIM Capture Compare Channel x.
+8036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+8037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  Channel specifies the TIM Channel
+8038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be one of the following values:
+8039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1
+8040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2
+8041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3
+8042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4
+8043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+8044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+8045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+8046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+8047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   * @retval None
+8048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   */
+8049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+8050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** {
+ 9161              		.loc 1 8050 1 is_stmt 1 view -0
+ 9162              		.cfi_startproc
+ 9163              		@ args = 0, pretend = 0, frame = 0
+ 9164              		@ frame_needed = 0, uses_anonymous_args = 0
+ 9165              		@ link register save eliminated.
+8051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmp;
+ 9166              		.loc 1 8051 3 view .LVU3038
+8052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+8053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ARM GAS  /tmp/cc0wMqvE.s 			page 345
+
+
+8054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ 9167              		.loc 1 8054 3 view .LVU3039
+8055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_CHANNELS(Channel));
+ 9168              		.loc 1 8055 3 view .LVU3040
+8056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+8057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+ 9169              		.loc 1 8057 3 view .LVU3041
+ 9170              		.loc 1 8057 35 is_stmt 0 view .LVU3042
+ 9171 0000 01F01F01 		and	r1, r1, #31
+ 9172              	.LVL783:
+ 9173              		.loc 1 8057 7 view .LVU3043
+ 9174 0004 4FF0010C 		mov	ip, #1
+ 9175 0008 0CFA01FC 		lsl	ip, ip, r1
+ 9176              	.LVL784:
+8058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+8059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Reset the CCxE Bit */
+8060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER &= ~tmp;
+ 9177              		.loc 1 8060 3 is_stmt 1 view .LVU3044
+ 9178              		.loc 1 8060 7 is_stmt 0 view .LVU3045
+ 9179 000c 036A     		ldr	r3, [r0, #32]
+ 9180              		.loc 1 8060 14 view .LVU3046
+ 9181 000e 23EA0C03 		bic	r3, r3, ip
+ 9182 0012 0362     		str	r3, [r0, #32]
+8061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+8062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Set or reset the CCxE Bit */
+8063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ 9183              		.loc 1 8063 3 is_stmt 1 view .LVU3047
+ 9184              		.loc 1 8063 7 is_stmt 0 view .LVU3048
+ 9185 0014 036A     		ldr	r3, [r0, #32]
+ 9186              		.loc 1 8063 41 view .LVU3049
+ 9187 0016 8A40     		lsls	r2, r2, r1
+ 9188              	.LVL785:
+ 9189              		.loc 1 8063 14 view .LVU3050
+ 9190 0018 1343     		orrs	r3, r3, r2
+ 9191 001a 0362     		str	r3, [r0, #32]
+8064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 9192              		.loc 1 8064 1 view .LVU3051
+ 9193 001c 7047     		bx	lr
+ 9194              		.cfi_endproc
+ 9195              	.LFE449:
+ 9197              		.section	.text.HAL_TIM_OC_Start,"ax",%progbits
+ 9198              		.align	1
+ 9199              		.global	HAL_TIM_OC_Start
+ 9200              		.syntax unified
+ 9201              		.thumb
+ 9202              		.thumb_func
+ 9204              	HAL_TIM_OC_Start:
+ 9205              	.LVL786:
+ 9206              	.LFB343:
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 9207              		.loc 1 805 1 is_stmt 1 view -0
+ 9208              		.cfi_startproc
+ 9209              		@ args = 0, pretend = 0, frame = 0
+ 9210              		@ frame_needed = 0, uses_anonymous_args = 0
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 9211              		.loc 1 805 1 is_stmt 0 view .LVU3053
+ 9212 0000 10B5     		push	{r4, lr}
+ARM GAS  /tmp/cc0wMqvE.s 			page 346
+
+
+ 9213              	.LCFI85:
+ 9214              		.cfi_def_cfa_offset 8
+ 9215              		.cfi_offset 4, -8
+ 9216              		.cfi_offset 14, -4
+ 9217 0002 0446     		mov	r4, r0
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9218              		.loc 1 806 3 is_stmt 1 view .LVU3054
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9219              		.loc 1 809 3 view .LVU3055
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9220              		.loc 1 812 3 view .LVU3056
+ 9221 0004 1029     		cmp	r1, #16
+ 9222 0006 3CD8     		bhi	.L591
+ 9223 0008 DFE801F0 		tbb	[pc, r1]
+ 9224              	.L593:
+ 9225 000c 09       		.byte	(.L597-.L593)/2
+ 9226 000d 3B       		.byte	(.L591-.L593)/2
+ 9227 000e 3B       		.byte	(.L591-.L593)/2
+ 9228 000f 3B       		.byte	(.L591-.L593)/2
+ 9229 0010 1F       		.byte	(.L596-.L593)/2
+ 9230 0011 3B       		.byte	(.L591-.L593)/2
+ 9231 0012 3B       		.byte	(.L591-.L593)/2
+ 9232 0013 3B       		.byte	(.L591-.L593)/2
+ 9233 0014 26       		.byte	(.L595-.L593)/2
+ 9234 0015 3B       		.byte	(.L591-.L593)/2
+ 9235 0016 3B       		.byte	(.L591-.L593)/2
+ 9236 0017 3B       		.byte	(.L591-.L593)/2
+ 9237 0018 2D       		.byte	(.L594-.L593)/2
+ 9238 0019 3B       		.byte	(.L591-.L593)/2
+ 9239 001a 3B       		.byte	(.L591-.L593)/2
+ 9240 001b 3B       		.byte	(.L591-.L593)/2
+ 9241 001c 34       		.byte	(.L592-.L593)/2
+ 9242 001d 00       		.p2align 1
+ 9243              	.L597:
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9244              		.loc 1 812 7 is_stmt 0 discriminator 1 view .LVU3057
+ 9245 001e 90F83E30 		ldrb	r3, [r0, #62]	@ zero_extendqisi2
+ 9246 0022 DBB2     		uxtb	r3, r3
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9247              		.loc 1 812 44 discriminator 1 view .LVU3058
+ 9248 0024 013B     		subs	r3, r3, #1
+ 9249 0026 18BF     		it	ne
+ 9250 0028 0123     		movne	r3, #1
+ 9251              	.L598:
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9252              		.loc 1 812 6 discriminator 20 view .LVU3059
+ 9253 002a 002B     		cmp	r3, #0
+ 9254 002c 40F08E80 		bne	.L612
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9255              		.loc 1 818 3 is_stmt 1 view .LVU3060
+ 9256 0030 1029     		cmp	r1, #16
+ 9257 0032 79D8     		bhi	.L600
+ 9258 0034 DFE801F0 		tbb	[pc, r1]
+ 9259              	.L602:
+ 9260 0038 2C       		.byte	(.L606-.L602)/2
+ 9261 0039 78       		.byte	(.L600-.L602)/2
+ 9262 003a 78       		.byte	(.L600-.L602)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 347
+
+
+ 9263 003b 78       		.byte	(.L600-.L602)/2
+ 9264 003c 68       		.byte	(.L605-.L602)/2
+ 9265 003d 78       		.byte	(.L600-.L602)/2
+ 9266 003e 78       		.byte	(.L600-.L602)/2
+ 9267 003f 78       		.byte	(.L600-.L602)/2
+ 9268 0040 6C       		.byte	(.L604-.L602)/2
+ 9269 0041 78       		.byte	(.L600-.L602)/2
+ 9270 0042 78       		.byte	(.L600-.L602)/2
+ 9271 0043 78       		.byte	(.L600-.L602)/2
+ 9272 0044 70       		.byte	(.L603-.L602)/2
+ 9273 0045 78       		.byte	(.L600-.L602)/2
+ 9274 0046 78       		.byte	(.L600-.L602)/2
+ 9275 0047 78       		.byte	(.L600-.L602)/2
+ 9276 0048 74       		.byte	(.L601-.L602)/2
+ 9277 0049 00       		.p2align 1
+ 9278              	.L596:
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9279              		.loc 1 812 7 is_stmt 0 discriminator 4 view .LVU3061
+ 9280 004a 90F83F30 		ldrb	r3, [r0, #63]	@ zero_extendqisi2
+ 9281 004e DBB2     		uxtb	r3, r3
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9282              		.loc 1 812 44 discriminator 4 view .LVU3062
+ 9283 0050 013B     		subs	r3, r3, #1
+ 9284 0052 18BF     		it	ne
+ 9285 0054 0123     		movne	r3, #1
+ 9286 0056 E8E7     		b	.L598
+ 9287              	.L595:
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9288              		.loc 1 812 7 discriminator 7 view .LVU3063
+ 9289 0058 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 9290 005c DBB2     		uxtb	r3, r3
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9291              		.loc 1 812 44 discriminator 7 view .LVU3064
+ 9292 005e 013B     		subs	r3, r3, #1
+ 9293 0060 18BF     		it	ne
+ 9294 0062 0123     		movne	r3, #1
+ 9295 0064 E1E7     		b	.L598
+ 9296              	.L594:
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9297              		.loc 1 812 7 discriminator 10 view .LVU3065
+ 9298 0066 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 9299 006a DBB2     		uxtb	r3, r3
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9300              		.loc 1 812 44 discriminator 10 view .LVU3066
+ 9301 006c 013B     		subs	r3, r3, #1
+ 9302 006e 18BF     		it	ne
+ 9303 0070 0123     		movne	r3, #1
+ 9304 0072 DAE7     		b	.L598
+ 9305              	.L592:
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9306              		.loc 1 812 7 discriminator 13 view .LVU3067
+ 9307 0074 90F84230 		ldrb	r3, [r0, #66]	@ zero_extendqisi2
+ 9308 0078 DBB2     		uxtb	r3, r3
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9309              		.loc 1 812 44 discriminator 13 view .LVU3068
+ 9310 007a 013B     		subs	r3, r3, #1
+ 9311 007c 18BF     		it	ne
+ARM GAS  /tmp/cc0wMqvE.s 			page 348
+
+
+ 9312 007e 0123     		movne	r3, #1
+ 9313 0080 D3E7     		b	.L598
+ 9314              	.L591:
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9315              		.loc 1 812 7 discriminator 14 view .LVU3069
+ 9316 0082 90F84330 		ldrb	r3, [r0, #67]	@ zero_extendqisi2
+ 9317 0086 DBB2     		uxtb	r3, r3
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9318              		.loc 1 812 44 discriminator 14 view .LVU3070
+ 9319 0088 013B     		subs	r3, r3, #1
+ 9320 008a 18BF     		it	ne
+ 9321 008c 0123     		movne	r3, #1
+ 9322 008e CCE7     		b	.L598
+ 9323              	.L606:
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9324              		.loc 1 818 3 discriminator 1 view .LVU3071
+ 9325 0090 0223     		movs	r3, #2
+ 9326 0092 84F83E30 		strb	r3, [r4, #62]
+ 9327              	.L607:
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9328              		.loc 1 821 3 is_stmt 1 view .LVU3072
+ 9329 0096 0122     		movs	r2, #1
+ 9330 0098 2068     		ldr	r0, [r4]
+ 9331              	.LVL787:
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9332              		.loc 1 821 3 is_stmt 0 view .LVU3073
+ 9333 009a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 9334              	.LVL788:
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9335              		.loc 1 823 3 is_stmt 1 view .LVU3074
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9336              		.loc 1 823 7 is_stmt 0 view .LVU3075
+ 9337 009e 2368     		ldr	r3, [r4]
+ 9338 00a0 2D4A     		ldr	r2, .L616
+ 9339 00a2 9342     		cmp	r3, r2
+ 9340 00a4 0FD0     		beq	.L608
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9341              		.loc 1 823 7 discriminator 2 view .LVU3076
+ 9342 00a6 02F50062 		add	r2, r2, #2048
+ 9343 00aa 9342     		cmp	r3, r2
+ 9344 00ac 0BD0     		beq	.L608
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9345              		.loc 1 823 7 discriminator 4 view .LVU3077
+ 9346 00ae 02F54062 		add	r2, r2, #3072
+ 9347 00b2 9342     		cmp	r3, r2
+ 9348 00b4 07D0     		beq	.L608
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9349              		.loc 1 823 7 discriminator 6 view .LVU3078
+ 9350 00b6 02F58062 		add	r2, r2, #1024
+ 9351 00ba 9342     		cmp	r3, r2
+ 9352 00bc 03D0     		beq	.L608
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9353              		.loc 1 823 7 discriminator 8 view .LVU3079
+ 9354 00be 02F58062 		add	r2, r2, #1024
+ 9355 00c2 9342     		cmp	r3, r2
+ 9356 00c4 03D1     		bne	.L609
+ 9357              	.L608:
+ARM GAS  /tmp/cc0wMqvE.s 			page 349
+
+
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9358              		.loc 1 826 5 is_stmt 1 view .LVU3080
+ 9359 00c6 5A6C     		ldr	r2, [r3, #68]
+ 9360 00c8 42F40042 		orr	r2, r2, #32768
+ 9361 00cc 5A64     		str	r2, [r3, #68]
+ 9362              	.L609:
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9363              		.loc 1 830 3 view .LVU3081
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9364              		.loc 1 830 7 is_stmt 0 view .LVU3082
+ 9365 00ce 2368     		ldr	r3, [r4]
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9366              		.loc 1 830 6 view .LVU3083
+ 9367 00d0 214A     		ldr	r2, .L616
+ 9368 00d2 9342     		cmp	r3, r2
+ 9369 00d4 2CD0     		beq	.L610
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9370              		.loc 1 830 7 discriminator 1 view .LVU3084
+ 9371 00d6 B3F1804F 		cmp	r3, #1073741824
+ 9372 00da 29D0     		beq	.L610
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9373              		.loc 1 830 7 discriminator 2 view .LVU3085
+ 9374 00dc A2F59432 		sub	r2, r2, #75776
+ 9375 00e0 9342     		cmp	r3, r2
+ 9376 00e2 25D0     		beq	.L610
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9377              		.loc 1 830 7 discriminator 3 view .LVU3086
+ 9378 00e4 02F58062 		add	r2, r2, #1024
+ 9379 00e8 9342     		cmp	r3, r2
+ 9380 00ea 21D0     		beq	.L610
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9381              		.loc 1 830 7 discriminator 4 view .LVU3087
+ 9382 00ec 02F59632 		add	r2, r2, #76800
+ 9383 00f0 9342     		cmp	r3, r2
+ 9384 00f2 1DD0     		beq	.L610
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9385              		.loc 1 830 7 discriminator 5 view .LVU3088
+ 9386 00f4 02F54062 		add	r2, r2, #3072
+ 9387 00f8 9342     		cmp	r3, r2
+ 9388 00fa 19D0     		beq	.L610
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9389              		.loc 1 840 5 is_stmt 1 view .LVU3089
+ 9390 00fc 1A68     		ldr	r2, [r3]
+ 9391 00fe 42F00102 		orr	r2, r2, #1
+ 9392 0102 1A60     		str	r2, [r3]
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 9393              		.loc 1 844 10 is_stmt 0 view .LVU3090
+ 9394 0104 0020     		movs	r0, #0
+ 9395 0106 22E0     		b	.L599
+ 9396              	.LVL789:
+ 9397              	.L605:
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9398              		.loc 1 818 3 discriminator 3 view .LVU3091
+ 9399 0108 0223     		movs	r3, #2
+ 9400 010a 84F83F30 		strb	r3, [r4, #63]
+ 9401 010e C2E7     		b	.L607
+ 9402              	.L604:
+ARM GAS  /tmp/cc0wMqvE.s 			page 350
+
+
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9403              		.loc 1 818 3 discriminator 6 view .LVU3092
+ 9404 0110 0223     		movs	r3, #2
+ 9405 0112 84F84030 		strb	r3, [r4, #64]
+ 9406 0116 BEE7     		b	.L607
+ 9407              	.L603:
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9408              		.loc 1 818 3 discriminator 9 view .LVU3093
+ 9409 0118 0223     		movs	r3, #2
+ 9410 011a 84F84130 		strb	r3, [r4, #65]
+ 9411 011e BAE7     		b	.L607
+ 9412              	.L601:
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9413              		.loc 1 818 3 discriminator 12 view .LVU3094
+ 9414 0120 0223     		movs	r3, #2
+ 9415 0122 84F84230 		strb	r3, [r4, #66]
+ 9416 0126 B6E7     		b	.L607
+ 9417              	.L600:
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9418              		.loc 1 818 3 discriminator 13 view .LVU3095
+ 9419 0128 0223     		movs	r3, #2
+ 9420 012a 84F84330 		strb	r3, [r4, #67]
+ 9421 012e B2E7     		b	.L607
+ 9422              	.LVL790:
+ 9423              	.L610:
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 9424              		.loc 1 832 5 is_stmt 1 view .LVU3096
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 9425              		.loc 1 832 29 is_stmt 0 view .LVU3097
+ 9426 0130 9968     		ldr	r1, [r3, #8]
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 9427              		.loc 1 832 13 view .LVU3098
+ 9428 0132 0A4A     		ldr	r2, .L616+4
+ 9429 0134 0A40     		ands	r2, r2, r1
+ 9430              	.LVL791:
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9431              		.loc 1 833 5 is_stmt 1 view .LVU3099
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9432              		.loc 1 833 8 is_stmt 0 view .LVU3100
+ 9433 0136 062A     		cmp	r2, #6
+ 9434 0138 0AD0     		beq	.L613
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9435              		.loc 1 833 9 discriminator 1 view .LVU3101
+ 9436 013a B2F5803F 		cmp	r2, #65536
+ 9437 013e 09D0     		beq	.L614
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 9438              		.loc 1 835 7 is_stmt 1 view .LVU3102
+ 9439 0140 1A68     		ldr	r2, [r3]
+ 9440              	.LVL792:
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 9441              		.loc 1 835 7 is_stmt 0 view .LVU3103
+ 9442 0142 42F00102 		orr	r2, r2, #1
+ 9443 0146 1A60     		str	r2, [r3]
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 9444              		.loc 1 844 10 view .LVU3104
+ 9445 0148 0020     		movs	r0, #0
+ 9446 014a 00E0     		b	.L599
+ARM GAS  /tmp/cc0wMqvE.s 			page 351
+
+
+ 9447              	.LVL793:
+ 9448              	.L612:
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9449              		.loc 1 814 12 view .LVU3105
+ 9450 014c 0120     		movs	r0, #1
+ 9451              	.LVL794:
+ 9452              	.L599:
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9453              		.loc 1 845 1 view .LVU3106
+ 9454 014e 10BD     		pop	{r4, pc}
+ 9455              	.LVL795:
+ 9456              	.L613:
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 9457              		.loc 1 844 10 view .LVU3107
+ 9458 0150 0020     		movs	r0, #0
+ 9459 0152 FCE7     		b	.L599
+ 9460              	.L614:
+ 9461 0154 0020     		movs	r0, #0
+ 9462 0156 FAE7     		b	.L599
+ 9463              	.L617:
+ 9464              		.align	2
+ 9465              	.L616:
+ 9466 0158 002C0140 		.word	1073818624
+ 9467 015c 07000100 		.word	65543
+ 9468              		.cfi_endproc
+ 9469              	.LFE343:
+ 9471              		.section	.text.HAL_TIM_OC_Stop,"ax",%progbits
+ 9472              		.align	1
+ 9473              		.global	HAL_TIM_OC_Stop
+ 9474              		.syntax unified
+ 9475              		.thumb
+ 9476              		.thumb_func
+ 9478              	HAL_TIM_OC_Stop:
+ 9479              	.LVL796:
+ 9480              	.LFB344:
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 9481              		.loc 1 861 1 is_stmt 1 view -0
+ 9482              		.cfi_startproc
+ 9483              		@ args = 0, pretend = 0, frame = 0
+ 9484              		@ frame_needed = 0, uses_anonymous_args = 0
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 9485              		.loc 1 861 1 is_stmt 0 view .LVU3109
+ 9486 0000 38B5     		push	{r3, r4, r5, lr}
+ 9487              	.LCFI86:
+ 9488              		.cfi_def_cfa_offset 16
+ 9489              		.cfi_offset 3, -16
+ 9490              		.cfi_offset 4, -12
+ 9491              		.cfi_offset 5, -8
+ 9492              		.cfi_offset 14, -4
+ 9493 0002 0446     		mov	r4, r0
+ 9494 0004 0D46     		mov	r5, r1
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9495              		.loc 1 863 3 is_stmt 1 view .LVU3110
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9496              		.loc 1 866 3 view .LVU3111
+ 9497 0006 0022     		movs	r2, #0
+ 9498 0008 0068     		ldr	r0, [r0]
+ARM GAS  /tmp/cc0wMqvE.s 			page 352
+
+
+ 9499              	.LVL797:
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9500              		.loc 1 866 3 is_stmt 0 view .LVU3112
+ 9501 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 9502              	.LVL798:
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9503              		.loc 1 868 3 is_stmt 1 view .LVU3113
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9504              		.loc 1 868 7 is_stmt 0 view .LVU3114
+ 9505 000e 2368     		ldr	r3, [r4]
+ 9506 0010 2A4A     		ldr	r2, .L631
+ 9507 0012 9342     		cmp	r3, r2
+ 9508 0014 0FD0     		beq	.L619
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9509              		.loc 1 868 7 discriminator 2 view .LVU3115
+ 9510 0016 02F50062 		add	r2, r2, #2048
+ 9511 001a 9342     		cmp	r3, r2
+ 9512 001c 0BD0     		beq	.L619
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9513              		.loc 1 868 7 discriminator 4 view .LVU3116
+ 9514 001e 02F54062 		add	r2, r2, #3072
+ 9515 0022 9342     		cmp	r3, r2
+ 9516 0024 07D0     		beq	.L619
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9517              		.loc 1 868 7 discriminator 6 view .LVU3117
+ 9518 0026 02F58062 		add	r2, r2, #1024
+ 9519 002a 9342     		cmp	r3, r2
+ 9520 002c 03D0     		beq	.L619
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9521              		.loc 1 868 7 discriminator 8 view .LVU3118
+ 9522 002e 02F58062 		add	r2, r2, #1024
+ 9523 0032 9342     		cmp	r3, r2
+ 9524 0034 0DD1     		bne	.L620
+ 9525              	.L619:
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9526              		.loc 1 871 5 is_stmt 1 view .LVU3119
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9527              		.loc 1 871 5 view .LVU3120
+ 9528 0036 196A     		ldr	r1, [r3, #32]
+ 9529 0038 41F21112 		movw	r2, #4369
+ 9530 003c 1142     		tst	r1, r2
+ 9531 003e 08D1     		bne	.L620
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9532              		.loc 1 871 5 discriminator 1 view .LVU3121
+ 9533 0040 196A     		ldr	r1, [r3, #32]
+ 9534 0042 44F24442 		movw	r2, #17476
+ 9535 0046 1142     		tst	r1, r2
+ 9536 0048 03D1     		bne	.L620
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9537              		.loc 1 871 5 discriminator 3 view .LVU3122
+ 9538 004a 5A6C     		ldr	r2, [r3, #68]
+ 9539 004c 22F40042 		bic	r2, r2, #32768
+ 9540 0050 5A64     		str	r2, [r3, #68]
+ 9541              	.L620:
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9542              		.loc 1 871 5 discriminator 5 view .LVU3123
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 353
+
+
+ 9543              		.loc 1 875 3 discriminator 5 view .LVU3124
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9544              		.loc 1 875 3 discriminator 5 view .LVU3125
+ 9545 0052 2368     		ldr	r3, [r4]
+ 9546 0054 196A     		ldr	r1, [r3, #32]
+ 9547 0056 41F21112 		movw	r2, #4369
+ 9548 005a 1142     		tst	r1, r2
+ 9549 005c 08D1     		bne	.L621
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9550              		.loc 1 875 3 discriminator 1 view .LVU3126
+ 9551 005e 196A     		ldr	r1, [r3, #32]
+ 9552 0060 44F24442 		movw	r2, #17476
+ 9553 0064 1142     		tst	r1, r2
+ 9554 0066 03D1     		bne	.L621
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9555              		.loc 1 875 3 discriminator 3 view .LVU3127
+ 9556 0068 1A68     		ldr	r2, [r3]
+ 9557 006a 22F00102 		bic	r2, r2, #1
+ 9558 006e 1A60     		str	r2, [r3]
+ 9559              	.L621:
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9560              		.loc 1 875 3 discriminator 5 view .LVU3128
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9561              		.loc 1 878 3 discriminator 5 view .LVU3129
+ 9562 0070 25B9     		cbnz	r5, .L622
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9563              		.loc 1 878 3 is_stmt 0 discriminator 1 view .LVU3130
+ 9564 0072 0123     		movs	r3, #1
+ 9565 0074 84F83E30 		strb	r3, [r4, #62]
+ 9566              	.LVL799:
+ 9567              	.L623:
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 9568              		.loc 1 881 3 is_stmt 1 view .LVU3131
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9569              		.loc 1 882 1 is_stmt 0 view .LVU3132
+ 9570 0078 0020     		movs	r0, #0
+ 9571 007a 38BD     		pop	{r3, r4, r5, pc}
+ 9572              	.LVL800:
+ 9573              	.L622:
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9574              		.loc 1 882 1 view .LVU3133
+ 9575 007c 043D     		subs	r5, r5, #4
+ 9576              	.LVL801:
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9577              		.loc 1 882 1 view .LVU3134
+ 9578 007e 0C2D     		cmp	r5, #12
+ 9579 0080 18D8     		bhi	.L624
+ 9580 0082 DFE805F0 		tbb	[pc, r5]
+ 9581              	.L626:
+ 9582 0086 07       		.byte	(.L629-.L626)/2
+ 9583 0087 17       		.byte	(.L624-.L626)/2
+ 9584 0088 17       		.byte	(.L624-.L626)/2
+ 9585 0089 17       		.byte	(.L624-.L626)/2
+ 9586 008a 0B       		.byte	(.L628-.L626)/2
+ 9587 008b 17       		.byte	(.L624-.L626)/2
+ 9588 008c 17       		.byte	(.L624-.L626)/2
+ 9589 008d 17       		.byte	(.L624-.L626)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 354
+
+
+ 9590 008e 0F       		.byte	(.L627-.L626)/2
+ 9591 008f 17       		.byte	(.L624-.L626)/2
+ 9592 0090 17       		.byte	(.L624-.L626)/2
+ 9593 0091 17       		.byte	(.L624-.L626)/2
+ 9594 0092 13       		.byte	(.L625-.L626)/2
+ 9595 0093 00       		.p2align 1
+ 9596              	.L629:
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9597              		.loc 1 878 3 discriminator 3 view .LVU3135
+ 9598 0094 0123     		movs	r3, #1
+ 9599 0096 84F83F30 		strb	r3, [r4, #63]
+ 9600 009a EDE7     		b	.L623
+ 9601              	.L628:
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9602              		.loc 1 878 3 discriminator 6 view .LVU3136
+ 9603 009c 0123     		movs	r3, #1
+ 9604 009e 84F84030 		strb	r3, [r4, #64]
+ 9605 00a2 E9E7     		b	.L623
+ 9606              	.L627:
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9607              		.loc 1 878 3 discriminator 9 view .LVU3137
+ 9608 00a4 0123     		movs	r3, #1
+ 9609 00a6 84F84130 		strb	r3, [r4, #65]
+ 9610 00aa E5E7     		b	.L623
+ 9611              	.L625:
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9612              		.loc 1 878 3 discriminator 12 view .LVU3138
+ 9613 00ac 0123     		movs	r3, #1
+ 9614 00ae 84F84230 		strb	r3, [r4, #66]
+ 9615 00b2 E1E7     		b	.L623
+ 9616              	.L624:
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9617              		.loc 1 878 3 discriminator 13 view .LVU3139
+ 9618 00b4 0123     		movs	r3, #1
+ 9619 00b6 84F84330 		strb	r3, [r4, #67]
+ 9620 00ba DDE7     		b	.L623
+ 9621              	.L632:
+ 9622              		.align	2
+ 9623              	.L631:
+ 9624 00bc 002C0140 		.word	1073818624
+ 9625              		.cfi_endproc
+ 9626              	.LFE344:
+ 9628              		.section	.text.HAL_TIM_OC_Start_IT,"ax",%progbits
+ 9629              		.align	1
+ 9630              		.global	HAL_TIM_OC_Start_IT
+ 9631              		.syntax unified
+ 9632              		.thumb
+ 9633              		.thumb_func
+ 9635              	HAL_TIM_OC_Start_IT:
+ 9636              	.LVL802:
+ 9637              	.LFB345:
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 9638              		.loc 1 896 1 is_stmt 1 view -0
+ 9639              		.cfi_startproc
+ 9640              		@ args = 0, pretend = 0, frame = 0
+ 9641              		@ frame_needed = 0, uses_anonymous_args = 0
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ARM GAS  /tmp/cc0wMqvE.s 			page 355
+
+
+ 9642              		.loc 1 896 1 is_stmt 0 view .LVU3141
+ 9643 0000 10B5     		push	{r4, lr}
+ 9644              	.LCFI87:
+ 9645              		.cfi_def_cfa_offset 8
+ 9646              		.cfi_offset 4, -8
+ 9647              		.cfi_offset 14, -4
+ 9648 0002 0446     		mov	r4, r0
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 9649              		.loc 1 897 3 is_stmt 1 view .LVU3142
+ 9650              	.LVL803:
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9651              		.loc 1 898 3 view .LVU3143
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9652              		.loc 1 901 3 view .LVU3144
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9653              		.loc 1 904 3 view .LVU3145
+ 9654 0004 1029     		cmp	r1, #16
+ 9655 0006 3DD8     		bhi	.L634
+ 9656 0008 DFE801F0 		tbb	[pc, r1]
+ 9657              	.L636:
+ 9658 000c 09       		.byte	(.L640-.L636)/2
+ 9659 000d 3C       		.byte	(.L634-.L636)/2
+ 9660 000e 3C       		.byte	(.L634-.L636)/2
+ 9661 000f 3C       		.byte	(.L634-.L636)/2
+ 9662 0010 20       		.byte	(.L639-.L636)/2
+ 9663 0011 3C       		.byte	(.L634-.L636)/2
+ 9664 0012 3C       		.byte	(.L634-.L636)/2
+ 9665 0013 3C       		.byte	(.L634-.L636)/2
+ 9666 0014 27       		.byte	(.L638-.L636)/2
+ 9667 0015 3C       		.byte	(.L634-.L636)/2
+ 9668 0016 3C       		.byte	(.L634-.L636)/2
+ 9669 0017 3C       		.byte	(.L634-.L636)/2
+ 9670 0018 2E       		.byte	(.L637-.L636)/2
+ 9671 0019 3C       		.byte	(.L634-.L636)/2
+ 9672 001a 3C       		.byte	(.L634-.L636)/2
+ 9673 001b 3C       		.byte	(.L634-.L636)/2
+ 9674 001c 35       		.byte	(.L635-.L636)/2
+ 9675 001d 00       		.p2align 1
+ 9676              	.L640:
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9677              		.loc 1 904 7 is_stmt 0 discriminator 1 view .LVU3146
+ 9678 001e 90F83E30 		ldrb	r3, [r0, #62]	@ zero_extendqisi2
+ 9679 0022 DBB2     		uxtb	r3, r3
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9680              		.loc 1 904 44 discriminator 1 view .LVU3147
+ 9681 0024 013B     		subs	r3, r3, #1
+ 9682 0026 18BF     		it	ne
+ 9683 0028 0123     		movne	r3, #1
+ 9684              	.L641:
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9685              		.loc 1 904 6 discriminator 20 view .LVU3148
+ 9686 002a 002B     		cmp	r3, #0
+ 9687 002c 40F0C280 		bne	.L660
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9688              		.loc 1 910 3 is_stmt 1 view .LVU3149
+ 9689 0030 1029     		cmp	r1, #16
+ 9690 0032 00F28F80 		bhi	.L643
+ARM GAS  /tmp/cc0wMqvE.s 			page 356
+
+
+ 9691 0036 DFE801F0 		tbb	[pc, r1]
+ 9692              	.L645:
+ 9693 003a 2C       		.byte	(.L649-.L645)/2
+ 9694 003b 8D       		.byte	(.L643-.L645)/2
+ 9695 003c 8D       		.byte	(.L643-.L645)/2
+ 9696 003d 8D       		.byte	(.L643-.L645)/2
+ 9697 003e 6D       		.byte	(.L648-.L645)/2
+ 9698 003f 8D       		.byte	(.L643-.L645)/2
+ 9699 0040 8D       		.byte	(.L643-.L645)/2
+ 9700 0041 8D       		.byte	(.L643-.L645)/2
+ 9701 0042 76       		.byte	(.L647-.L645)/2
+ 9702 0043 8D       		.byte	(.L643-.L645)/2
+ 9703 0044 8D       		.byte	(.L643-.L645)/2
+ 9704 0045 8D       		.byte	(.L643-.L645)/2
+ 9705 0046 7F       		.byte	(.L646-.L645)/2
+ 9706 0047 8D       		.byte	(.L643-.L645)/2
+ 9707 0048 8D       		.byte	(.L643-.L645)/2
+ 9708 0049 8D       		.byte	(.L643-.L645)/2
+ 9709 004a 88       		.byte	(.L644-.L645)/2
+ 9710 004b 00       		.p2align 1
+ 9711              	.L639:
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9712              		.loc 1 904 7 is_stmt 0 discriminator 4 view .LVU3150
+ 9713 004c 90F83F30 		ldrb	r3, [r0, #63]	@ zero_extendqisi2
+ 9714 0050 DBB2     		uxtb	r3, r3
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9715              		.loc 1 904 44 discriminator 4 view .LVU3151
+ 9716 0052 013B     		subs	r3, r3, #1
+ 9717 0054 18BF     		it	ne
+ 9718 0056 0123     		movne	r3, #1
+ 9719 0058 E7E7     		b	.L641
+ 9720              	.L638:
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9721              		.loc 1 904 7 discriminator 7 view .LVU3152
+ 9722 005a 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 9723 005e DBB2     		uxtb	r3, r3
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9724              		.loc 1 904 44 discriminator 7 view .LVU3153
+ 9725 0060 013B     		subs	r3, r3, #1
+ 9726 0062 18BF     		it	ne
+ 9727 0064 0123     		movne	r3, #1
+ 9728 0066 E0E7     		b	.L641
+ 9729              	.L637:
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9730              		.loc 1 904 7 discriminator 10 view .LVU3154
+ 9731 0068 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 9732 006c DBB2     		uxtb	r3, r3
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9733              		.loc 1 904 44 discriminator 10 view .LVU3155
+ 9734 006e 013B     		subs	r3, r3, #1
+ 9735 0070 18BF     		it	ne
+ 9736 0072 0123     		movne	r3, #1
+ 9737 0074 D9E7     		b	.L641
+ 9738              	.L635:
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9739              		.loc 1 904 7 discriminator 13 view .LVU3156
+ 9740 0076 90F84230 		ldrb	r3, [r0, #66]	@ zero_extendqisi2
+ARM GAS  /tmp/cc0wMqvE.s 			page 357
+
+
+ 9741 007a DBB2     		uxtb	r3, r3
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9742              		.loc 1 904 44 discriminator 13 view .LVU3157
+ 9743 007c 013B     		subs	r3, r3, #1
+ 9744 007e 18BF     		it	ne
+ 9745 0080 0123     		movne	r3, #1
+ 9746 0082 D2E7     		b	.L641
+ 9747              	.L634:
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9748              		.loc 1 904 7 discriminator 14 view .LVU3158
+ 9749 0084 90F84330 		ldrb	r3, [r0, #67]	@ zero_extendqisi2
+ 9750 0088 DBB2     		uxtb	r3, r3
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9751              		.loc 1 904 44 discriminator 14 view .LVU3159
+ 9752 008a 013B     		subs	r3, r3, #1
+ 9753 008c 18BF     		it	ne
+ 9754 008e 0123     		movne	r3, #1
+ 9755 0090 CBE7     		b	.L641
+ 9756              	.L649:
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9757              		.loc 1 910 3 view .LVU3160
+ 9758 0092 0223     		movs	r3, #2
+ 9759 0094 84F83E30 		strb	r3, [r4, #62]
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9760              		.loc 1 912 3 is_stmt 1 view .LVU3161
+ 9761              	.L650:
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 9762              		.loc 1 917 7 view .LVU3162
+ 9763 0098 2268     		ldr	r2, [r4]
+ 9764 009a D368     		ldr	r3, [r2, #12]
+ 9765 009c 43F00203 		orr	r3, r3, #2
+ 9766 00a0 D360     		str	r3, [r2, #12]
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 9767              		.loc 1 918 7 view .LVU3163
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9768              		.loc 1 947 3 view .LVU3164
+ 9769              	.L655:
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9770              		.loc 1 950 5 view .LVU3165
+ 9771 00a2 0122     		movs	r2, #1
+ 9772 00a4 2068     		ldr	r0, [r4]
+ 9773              	.LVL804:
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9774              		.loc 1 950 5 is_stmt 0 view .LVU3166
+ 9775 00a6 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 9776              	.LVL805:
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9777              		.loc 1 952 5 is_stmt 1 view .LVU3167
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9778              		.loc 1 952 9 is_stmt 0 view .LVU3168
+ 9779 00aa 2368     		ldr	r3, [r4]
+ 9780 00ac 454A     		ldr	r2, .L669
+ 9781 00ae 9342     		cmp	r3, r2
+ 9782 00b0 0FD0     		beq	.L656
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9783              		.loc 1 952 9 discriminator 2 view .LVU3169
+ 9784 00b2 02F50062 		add	r2, r2, #2048
+ARM GAS  /tmp/cc0wMqvE.s 			page 358
+
+
+ 9785 00b6 9342     		cmp	r3, r2
+ 9786 00b8 0BD0     		beq	.L656
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9787              		.loc 1 952 9 discriminator 4 view .LVU3170
+ 9788 00ba 02F54062 		add	r2, r2, #3072
+ 9789 00be 9342     		cmp	r3, r2
+ 9790 00c0 07D0     		beq	.L656
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9791              		.loc 1 952 9 discriminator 6 view .LVU3171
+ 9792 00c2 02F58062 		add	r2, r2, #1024
+ 9793 00c6 9342     		cmp	r3, r2
+ 9794 00c8 03D0     		beq	.L656
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9795              		.loc 1 952 9 discriminator 8 view .LVU3172
+ 9796 00ca 02F58062 		add	r2, r2, #1024
+ 9797 00ce 9342     		cmp	r3, r2
+ 9798 00d0 03D1     		bne	.L657
+ 9799              	.L656:
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 9800              		.loc 1 955 7 is_stmt 1 view .LVU3173
+ 9801 00d2 5A6C     		ldr	r2, [r3, #68]
+ 9802 00d4 42F40042 		orr	r2, r2, #32768
+ 9803 00d8 5A64     		str	r2, [r3, #68]
+ 9804              	.L657:
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9805              		.loc 1 959 5 view .LVU3174
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9806              		.loc 1 959 9 is_stmt 0 view .LVU3175
+ 9807 00da 2368     		ldr	r3, [r4]
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9808              		.loc 1 959 8 view .LVU3176
+ 9809 00dc 394A     		ldr	r2, .L669
+ 9810 00de 9342     		cmp	r3, r2
+ 9811 00e0 5AD0     		beq	.L658
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9812              		.loc 1 959 9 discriminator 1 view .LVU3177
+ 9813 00e2 B3F1804F 		cmp	r3, #1073741824
+ 9814 00e6 57D0     		beq	.L658
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9815              		.loc 1 959 9 discriminator 2 view .LVU3178
+ 9816 00e8 A2F59432 		sub	r2, r2, #75776
+ 9817 00ec 9342     		cmp	r3, r2
+ 9818 00ee 53D0     		beq	.L658
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9819              		.loc 1 959 9 discriminator 3 view .LVU3179
+ 9820 00f0 02F58062 		add	r2, r2, #1024
+ 9821 00f4 9342     		cmp	r3, r2
+ 9822 00f6 4FD0     		beq	.L658
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9823              		.loc 1 959 9 discriminator 4 view .LVU3180
+ 9824 00f8 02F59632 		add	r2, r2, #76800
+ 9825 00fc 9342     		cmp	r3, r2
+ 9826 00fe 4BD0     		beq	.L658
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 9827              		.loc 1 959 9 discriminator 5 view .LVU3181
+ 9828 0100 02F54062 		add	r2, r2, #3072
+ 9829 0104 9342     		cmp	r3, r2
+ARM GAS  /tmp/cc0wMqvE.s 			page 359
+
+
+ 9830 0106 47D0     		beq	.L658
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 9831              		.loc 1 969 7 is_stmt 1 view .LVU3182
+ 9832 0108 1A68     		ldr	r2, [r3]
+ 9833 010a 42F00102 		orr	r2, r2, #1
+ 9834 010e 1A60     		str	r2, [r3]
+ 9835 0110 0020     		movs	r0, #0
+ 9836 0112 50E0     		b	.L642
+ 9837              	.LVL806:
+ 9838              	.L648:
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9839              		.loc 1 910 3 is_stmt 0 view .LVU3183
+ 9840 0114 0223     		movs	r3, #2
+ 9841 0116 84F83F30 		strb	r3, [r4, #63]
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9842              		.loc 1 912 3 is_stmt 1 view .LVU3184
+ 9843              	.L651:
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 9844              		.loc 1 924 7 view .LVU3185
+ 9845 011a 2268     		ldr	r2, [r4]
+ 9846 011c D368     		ldr	r3, [r2, #12]
+ 9847 011e 43F00403 		orr	r3, r3, #4
+ 9848 0122 D360     		str	r3, [r2, #12]
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 9849              		.loc 1 925 7 view .LVU3186
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9850              		.loc 1 947 3 view .LVU3187
+ 9851 0124 BDE7     		b	.L655
+ 9852              	.L647:
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9853              		.loc 1 910 3 is_stmt 0 view .LVU3188
+ 9854 0126 0223     		movs	r3, #2
+ 9855 0128 84F84030 		strb	r3, [r4, #64]
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9856              		.loc 1 912 3 is_stmt 1 view .LVU3189
+ 9857              	.L652:
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 9858              		.loc 1 931 7 view .LVU3190
+ 9859 012c 2268     		ldr	r2, [r4]
+ 9860 012e D368     		ldr	r3, [r2, #12]
+ 9861 0130 43F00803 		orr	r3, r3, #8
+ 9862 0134 D360     		str	r3, [r2, #12]
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 9863              		.loc 1 932 7 view .LVU3191
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9864              		.loc 1 947 3 view .LVU3192
+ 9865 0136 B4E7     		b	.L655
+ 9866              	.L646:
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9867              		.loc 1 910 3 is_stmt 0 view .LVU3193
+ 9868 0138 0223     		movs	r3, #2
+ 9869 013a 84F84130 		strb	r3, [r4, #65]
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9870              		.loc 1 912 3 is_stmt 1 view .LVU3194
+ 9871              	.L653:
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 9872              		.loc 1 938 7 view .LVU3195
+ARM GAS  /tmp/cc0wMqvE.s 			page 360
+
+
+ 9873 013e 2268     		ldr	r2, [r4]
+ 9874 0140 D368     		ldr	r3, [r2, #12]
+ 9875 0142 43F01003 		orr	r3, r3, #16
+ 9876 0146 D360     		str	r3, [r2, #12]
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 9877              		.loc 1 939 7 view .LVU3196
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9878              		.loc 1 947 3 view .LVU3197
+ 9879 0148 ABE7     		b	.L655
+ 9880              	.L644:
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9881              		.loc 1 910 3 is_stmt 0 view .LVU3198
+ 9882 014a 0223     		movs	r3, #2
+ 9883 014c 84F84230 		strb	r3, [r4, #66]
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9884              		.loc 1 912 3 is_stmt 1 view .LVU3199
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9885              		.loc 1 910 3 is_stmt 0 view .LVU3200
+ 9886 0150 0120     		movs	r0, #1
+ 9887              	.LVL807:
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9888              		.loc 1 910 3 view .LVU3201
+ 9889 0152 30E0     		b	.L642
+ 9890              	.LVL808:
+ 9891              	.L643:
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9892              		.loc 1 910 3 discriminator 13 view .LVU3202
+ 9893 0154 0223     		movs	r3, #2
+ 9894 0156 84F84330 		strb	r3, [r4, #67]
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9895              		.loc 1 912 3 is_stmt 1 discriminator 13 view .LVU3203
+ 9896 015a 0C29     		cmp	r1, #12
+ 9897 015c 2CD8     		bhi	.L661
+ 9898 015e 01A3     		adr	r3, .L654
+ 9899 0160 53F821F0 		ldr	pc, [r3, r1, lsl #2]
+ 9900              		.p2align 2
+ 9901              	.L654:
+ 9902 0164 99000000 		.word	.L650+1
+ 9903 0168 B9010000 		.word	.L661+1
+ 9904 016c B9010000 		.word	.L661+1
+ 9905 0170 B9010000 		.word	.L661+1
+ 9906 0174 1B010000 		.word	.L651+1
+ 9907 0178 B9010000 		.word	.L661+1
+ 9908 017c B9010000 		.word	.L661+1
+ 9909 0180 B9010000 		.word	.L661+1
+ 9910 0184 2D010000 		.word	.L652+1
+ 9911 0188 B9010000 		.word	.L661+1
+ 9912 018c B9010000 		.word	.L661+1
+ 9913 0190 B9010000 		.word	.L661+1
+ 9914 0194 3F010000 		.word	.L653+1
+ 9915              	.LVL809:
+ 9916              		.p2align 1
+ 9917              	.L658:
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 9918              		.loc 1 961 7 view .LVU3204
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 9919              		.loc 1 961 31 is_stmt 0 view .LVU3205
+ARM GAS  /tmp/cc0wMqvE.s 			page 361
+
+
+ 9920 0198 9968     		ldr	r1, [r3, #8]
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 9921              		.loc 1 961 15 view .LVU3206
+ 9922 019a 0B4A     		ldr	r2, .L669+4
+ 9923 019c 0A40     		ands	r2, r2, r1
+ 9924              	.LVL810:
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 9925              		.loc 1 962 7 is_stmt 1 view .LVU3207
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 9926              		.loc 1 962 10 is_stmt 0 view .LVU3208
+ 9927 019e 062A     		cmp	r2, #6
+ 9928 01a0 0CD0     		beq	.L662
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 9929              		.loc 1 962 11 discriminator 1 view .LVU3209
+ 9930 01a2 B2F5803F 		cmp	r2, #65536
+ 9931 01a6 0BD0     		beq	.L663
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 9932              		.loc 1 964 9 is_stmt 1 view .LVU3210
+ 9933 01a8 1A68     		ldr	r2, [r3]
+ 9934              	.LVL811:
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 9935              		.loc 1 964 9 is_stmt 0 view .LVU3211
+ 9936 01aa 42F00102 		orr	r2, r2, #1
+ 9937 01ae 1A60     		str	r2, [r3]
+ 9938 01b0 0020     		movs	r0, #0
+ 9939 01b2 00E0     		b	.L642
+ 9940              	.LVL812:
+ 9941              	.L660:
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 9942              		.loc 1 906 12 view .LVU3212
+ 9943 01b4 0120     		movs	r0, #1
+ 9944              	.LVL813:
+ 9945              	.L642:
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9946              		.loc 1 975 1 view .LVU3213
+ 9947 01b6 10BD     		pop	{r4, pc}
+ 9948              	.LVL814:
+ 9949              	.L661:
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9950              		.loc 1 912 3 view .LVU3214
+ 9951 01b8 0120     		movs	r0, #1
+ 9952              	.LVL815:
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9953              		.loc 1 912 3 view .LVU3215
+ 9954 01ba FCE7     		b	.L642
+ 9955              	.LVL816:
+ 9956              	.L662:
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9957              		.loc 1 912 3 view .LVU3216
+ 9958 01bc 0020     		movs	r0, #0
+ 9959 01be FAE7     		b	.L642
+ 9960              	.L663:
+ 9961 01c0 0020     		movs	r0, #0
+ 9962 01c2 F8E7     		b	.L642
+ 9963              	.L670:
+ 9964              		.align	2
+ 9965              	.L669:
+ARM GAS  /tmp/cc0wMqvE.s 			page 362
+
+
+ 9966 01c4 002C0140 		.word	1073818624
+ 9967 01c8 07000100 		.word	65543
+ 9968              		.cfi_endproc
+ 9969              	.LFE345:
+ 9971              		.section	.text.HAL_TIM_OC_Stop_IT,"ax",%progbits
+ 9972              		.align	1
+ 9973              		.global	HAL_TIM_OC_Stop_IT
+ 9974              		.syntax unified
+ 9975              		.thumb
+ 9976              		.thumb_func
+ 9978              	HAL_TIM_OC_Stop_IT:
+ 9979              	.LVL817:
+ 9980              	.LFB346:
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 9981              		.loc 1 989 1 is_stmt 1 view -0
+ 9982              		.cfi_startproc
+ 9983              		@ args = 0, pretend = 0, frame = 0
+ 9984              		@ frame_needed = 0, uses_anonymous_args = 0
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 9985              		.loc 1 989 1 is_stmt 0 view .LVU3218
+ 9986 0000 38B5     		push	{r3, r4, r5, lr}
+ 9987              	.LCFI88:
+ 9988              		.cfi_def_cfa_offset 16
+ 9989              		.cfi_offset 3, -16
+ 9990              		.cfi_offset 4, -12
+ 9991              		.cfi_offset 5, -8
+ 9992              		.cfi_offset 14, -4
+ 9993 0002 0546     		mov	r5, r0
+ 9994 0004 0C46     		mov	r4, r1
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9995              		.loc 1 990 3 is_stmt 1 view .LVU3219
+ 9996              	.LVL818:
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 9997              		.loc 1 993 3 view .LVU3220
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 9998              		.loc 1 995 3 view .LVU3221
+ 9999 0006 0C29     		cmp	r1, #12
+ 10000 0008 00F28180 		bhi	.L689
+ 10001 000c DFE801F0 		tbb	[pc, r1]
+ 10002              	.L674:
+ 10003 0010 07       		.byte	(.L677-.L674)/2
+ 10004 0011 7F       		.byte	(.L689-.L674)/2
+ 10005 0012 7F       		.byte	(.L689-.L674)/2
+ 10006 0013 7F       		.byte	(.L689-.L674)/2
+ 10007 0014 48       		.byte	(.L676-.L674)/2
+ 10008 0015 7F       		.byte	(.L689-.L674)/2
+ 10009 0016 7F       		.byte	(.L689-.L674)/2
+ 10010 0017 7F       		.byte	(.L689-.L674)/2
+ 10011 0018 4E       		.byte	(.L675-.L674)/2
+ 10012 0019 7F       		.byte	(.L689-.L674)/2
+ 10013 001a 7F       		.byte	(.L689-.L674)/2
+ 10014 001b 7F       		.byte	(.L689-.L674)/2
+ 10015 001c 54       		.byte	(.L673-.L674)/2
+ 10016 001d 00       		.p2align 1
+ 10017              	.L677:
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10018              		.loc 1 1000 7 view .LVU3222
+ARM GAS  /tmp/cc0wMqvE.s 			page 363
+
+
+ 10019 001e 0268     		ldr	r2, [r0]
+ 10020 0020 D368     		ldr	r3, [r2, #12]
+ 10021 0022 23F00203 		bic	r3, r3, #2
+ 10022 0026 D360     		str	r3, [r2, #12]
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10023              		.loc 1 1001 7 view .LVU3223
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10024              		.loc 1 1030 3 view .LVU3224
+ 10025              	.L678:
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10026              		.loc 1 1033 5 view .LVU3225
+ 10027 0028 0022     		movs	r2, #0
+ 10028 002a 2146     		mov	r1, r4
+ 10029              	.LVL819:
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10030              		.loc 1 1033 5 is_stmt 0 view .LVU3226
+ 10031 002c 2868     		ldr	r0, [r5]
+ 10032              	.LVL820:
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10033              		.loc 1 1033 5 view .LVU3227
+ 10034 002e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 10035              	.LVL821:
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10036              		.loc 1 1035 5 is_stmt 1 view .LVU3228
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10037              		.loc 1 1035 9 is_stmt 0 view .LVU3229
+ 10038 0032 2B68     		ldr	r3, [r5]
+ 10039 0034 374A     		ldr	r2, .L691
+ 10040 0036 9342     		cmp	r3, r2
+ 10041 0038 0FD0     		beq	.L679
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10042              		.loc 1 1035 9 discriminator 2 view .LVU3230
+ 10043 003a 02F50062 		add	r2, r2, #2048
+ 10044 003e 9342     		cmp	r3, r2
+ 10045 0040 0BD0     		beq	.L679
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10046              		.loc 1 1035 9 discriminator 4 view .LVU3231
+ 10047 0042 02F54062 		add	r2, r2, #3072
+ 10048 0046 9342     		cmp	r3, r2
+ 10049 0048 07D0     		beq	.L679
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10050              		.loc 1 1035 9 discriminator 6 view .LVU3232
+ 10051 004a 02F58062 		add	r2, r2, #1024
+ 10052 004e 9342     		cmp	r3, r2
+ 10053 0050 03D0     		beq	.L679
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10054              		.loc 1 1035 9 discriminator 8 view .LVU3233
+ 10055 0052 02F58062 		add	r2, r2, #1024
+ 10056 0056 9342     		cmp	r3, r2
+ 10057 0058 0DD1     		bne	.L680
+ 10058              	.L679:
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10059              		.loc 1 1038 7 is_stmt 1 view .LVU3234
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10060              		.loc 1 1038 7 view .LVU3235
+ 10061 005a 196A     		ldr	r1, [r3, #32]
+ 10062 005c 41F21112 		movw	r2, #4369
+ARM GAS  /tmp/cc0wMqvE.s 			page 364
+
+
+ 10063 0060 1142     		tst	r1, r2
+ 10064 0062 08D1     		bne	.L680
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10065              		.loc 1 1038 7 discriminator 1 view .LVU3236
+ 10066 0064 196A     		ldr	r1, [r3, #32]
+ 10067 0066 44F24442 		movw	r2, #17476
+ 10068 006a 1142     		tst	r1, r2
+ 10069 006c 03D1     		bne	.L680
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10070              		.loc 1 1038 7 discriminator 3 view .LVU3237
+ 10071 006e 5A6C     		ldr	r2, [r3, #68]
+ 10072 0070 22F40042 		bic	r2, r2, #32768
+ 10073 0074 5A64     		str	r2, [r3, #68]
+ 10074              	.L680:
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10075              		.loc 1 1038 7 discriminator 5 view .LVU3238
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10076              		.loc 1 1042 5 discriminator 5 view .LVU3239
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10077              		.loc 1 1042 5 discriminator 5 view .LVU3240
+ 10078 0076 2B68     		ldr	r3, [r5]
+ 10079 0078 196A     		ldr	r1, [r3, #32]
+ 10080 007a 41F21112 		movw	r2, #4369
+ 10081 007e 1142     		tst	r1, r2
+ 10082 0080 08D1     		bne	.L681
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10083              		.loc 1 1042 5 discriminator 1 view .LVU3241
+ 10084 0082 196A     		ldr	r1, [r3, #32]
+ 10085 0084 44F24442 		movw	r2, #17476
+ 10086 0088 1142     		tst	r1, r2
+ 10087 008a 03D1     		bne	.L681
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10088              		.loc 1 1042 5 discriminator 3 view .LVU3242
+ 10089 008c 1A68     		ldr	r2, [r3]
+ 10090 008e 22F00102 		bic	r2, r2, #1
+ 10091 0092 1A60     		str	r2, [r3]
+ 10092              	.L681:
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10093              		.loc 1 1042 5 discriminator 5 view .LVU3243
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 10094              		.loc 1 1045 5 discriminator 5 view .LVU3244
+ 10095 0094 B4B9     		cbnz	r4, .L682
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 10096              		.loc 1 1045 5 is_stmt 0 discriminator 1 view .LVU3245
+ 10097 0096 0123     		movs	r3, #1
+ 10098 0098 85F83E30 		strb	r3, [r5, #62]
+ 10099 009c 0020     		movs	r0, #0
+ 10100 009e 37E0     		b	.L672
+ 10101              	.LVL822:
+ 10102              	.L676:
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10103              		.loc 1 1007 7 is_stmt 1 view .LVU3246
+ 10104 00a0 0268     		ldr	r2, [r0]
+ 10105 00a2 D368     		ldr	r3, [r2, #12]
+ 10106 00a4 23F00403 		bic	r3, r3, #4
+ 10107 00a8 D360     		str	r3, [r2, #12]
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ARM GAS  /tmp/cc0wMqvE.s 			page 365
+
+
+ 10108              		.loc 1 1008 7 view .LVU3247
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10109              		.loc 1 1030 3 view .LVU3248
+ 10110 00aa BDE7     		b	.L678
+ 10111              	.L675:
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10112              		.loc 1 1014 7 view .LVU3249
+ 10113 00ac 0268     		ldr	r2, [r0]
+ 10114 00ae D368     		ldr	r3, [r2, #12]
+ 10115 00b0 23F00803 		bic	r3, r3, #8
+ 10116 00b4 D360     		str	r3, [r2, #12]
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10117              		.loc 1 1015 7 view .LVU3250
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10118              		.loc 1 1030 3 view .LVU3251
+ 10119 00b6 B7E7     		b	.L678
+ 10120              	.L673:
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10121              		.loc 1 1021 7 view .LVU3252
+ 10122 00b8 0268     		ldr	r2, [r0]
+ 10123 00ba D368     		ldr	r3, [r2, #12]
+ 10124 00bc 23F01003 		bic	r3, r3, #16
+ 10125 00c0 D360     		str	r3, [r2, #12]
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10126              		.loc 1 1022 7 view .LVU3253
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10127              		.loc 1 1030 3 view .LVU3254
+ 10128 00c2 B1E7     		b	.L678
+ 10129              	.LVL823:
+ 10130              	.L682:
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10131              		.loc 1 1030 3 is_stmt 0 view .LVU3255
+ 10132 00c4 043C     		subs	r4, r4, #4
+ 10133              	.LVL824:
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10134              		.loc 1 1030 3 view .LVU3256
+ 10135 00c6 0C2C     		cmp	r4, #12
+ 10136 00c8 1CD8     		bhi	.L683
+ 10137 00ca DFE804F0 		tbb	[pc, r4]
+ 10138              	.L685:
+ 10139 00ce 07       		.byte	(.L688-.L685)/2
+ 10140 00cf 1B       		.byte	(.L683-.L685)/2
+ 10141 00d0 1B       		.byte	(.L683-.L685)/2
+ 10142 00d1 1B       		.byte	(.L683-.L685)/2
+ 10143 00d2 0C       		.byte	(.L687-.L685)/2
+ 10144 00d3 1B       		.byte	(.L683-.L685)/2
+ 10145 00d4 1B       		.byte	(.L683-.L685)/2
+ 10146 00d5 1B       		.byte	(.L683-.L685)/2
+ 10147 00d6 11       		.byte	(.L686-.L685)/2
+ 10148 00d7 1B       		.byte	(.L683-.L685)/2
+ 10149 00d8 1B       		.byte	(.L683-.L685)/2
+ 10150 00d9 1B       		.byte	(.L683-.L685)/2
+ 10151 00da 16       		.byte	(.L684-.L685)/2
+ 10152 00db 00       		.p2align 1
+ 10153              	.L688:
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 10154              		.loc 1 1045 5 discriminator 3 view .LVU3257
+ARM GAS  /tmp/cc0wMqvE.s 			page 366
+
+
+ 10155 00dc 0123     		movs	r3, #1
+ 10156 00de 85F83F30 		strb	r3, [r5, #63]
+ 10157 00e2 0020     		movs	r0, #0
+ 10158 00e4 14E0     		b	.L672
+ 10159              	.L687:
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 10160              		.loc 1 1045 5 discriminator 6 view .LVU3258
+ 10161 00e6 0123     		movs	r3, #1
+ 10162 00e8 85F84030 		strb	r3, [r5, #64]
+ 10163 00ec 0020     		movs	r0, #0
+ 10164 00ee 0FE0     		b	.L672
+ 10165              	.L686:
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 10166              		.loc 1 1045 5 discriminator 9 view .LVU3259
+ 10167 00f0 0123     		movs	r3, #1
+ 10168 00f2 85F84130 		strb	r3, [r5, #65]
+ 10169 00f6 0020     		movs	r0, #0
+ 10170 00f8 0AE0     		b	.L672
+ 10171              	.L684:
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 10172              		.loc 1 1045 5 discriminator 12 view .LVU3260
+ 10173 00fa 0123     		movs	r3, #1
+ 10174 00fc 85F84230 		strb	r3, [r5, #66]
+ 10175 0100 0020     		movs	r0, #0
+ 10176 0102 05E0     		b	.L672
+ 10177              	.L683:
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 10178              		.loc 1 1045 5 discriminator 13 view .LVU3261
+ 10179 0104 0123     		movs	r3, #1
+ 10180 0106 85F84330 		strb	r3, [r5, #67]
+ 10181 010a 0020     		movs	r0, #0
+ 10182 010c 00E0     		b	.L672
+ 10183              	.LVL825:
+ 10184              	.L689:
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10185              		.loc 1 995 3 view .LVU3262
+ 10186 010e 0120     		movs	r0, #1
+ 10187              	.LVL826:
+ 10188              	.L672:
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 10189              		.loc 1 1049 3 is_stmt 1 view .LVU3263
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10190              		.loc 1 1050 1 is_stmt 0 view .LVU3264
+ 10191 0110 38BD     		pop	{r3, r4, r5, pc}
+ 10192              	.LVL827:
+ 10193              	.L692:
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10194              		.loc 1 1050 1 view .LVU3265
+ 10195 0112 00BF     		.align	2
+ 10196              	.L691:
+ 10197 0114 002C0140 		.word	1073818624
+ 10198              		.cfi_endproc
+ 10199              	.LFE346:
+ 10201              		.section	.text.HAL_TIM_OC_Start_DMA,"ax",%progbits
+ 10202              		.align	1
+ 10203              		.global	HAL_TIM_OC_Start_DMA
+ 10204              		.syntax unified
+ARM GAS  /tmp/cc0wMqvE.s 			page 367
+
+
+ 10205              		.thumb
+ 10206              		.thumb_func
+ 10208              	HAL_TIM_OC_Start_DMA:
+ 10209              	.LVL828:
+ 10210              	.LFB347:
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 10211              		.loc 1 1066 1 is_stmt 1 view -0
+ 10212              		.cfi_startproc
+ 10213              		@ args = 0, pretend = 0, frame = 0
+ 10214              		@ frame_needed = 0, uses_anonymous_args = 0
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 10215              		.loc 1 1066 1 is_stmt 0 view .LVU3267
+ 10216 0000 38B5     		push	{r3, r4, r5, lr}
+ 10217              	.LCFI89:
+ 10218              		.cfi_def_cfa_offset 16
+ 10219              		.cfi_offset 3, -16
+ 10220              		.cfi_offset 4, -12
+ 10221              		.cfi_offset 5, -8
+ 10222              		.cfi_offset 14, -4
+ 10223 0002 0446     		mov	r4, r0
+ 10224 0004 0D46     		mov	r5, r1
+ 10225 0006 1146     		mov	r1, r2
+ 10226              	.LVL829:
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 10227              		.loc 1 1067 3 is_stmt 1 view .LVU3268
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10228              		.loc 1 1068 3 view .LVU3269
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10229              		.loc 1 1071 3 view .LVU3270
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10230              		.loc 1 1074 3 view .LVU3271
+ 10231 0008 102D     		cmp	r5, #16
+ 10232 000a 41D8     		bhi	.L694
+ 10233 000c DFE805F0 		tbb	[pc, r5]
+ 10234              	.LVL830:
+ 10235              	.L696:
+ 10236 0010 09       		.byte	(.L700-.L696)/2
+ 10237 0011 40       		.byte	(.L694-.L696)/2
+ 10238 0012 40       		.byte	(.L694-.L696)/2
+ 10239 0013 40       		.byte	(.L694-.L696)/2
+ 10240 0014 20       		.byte	(.L699-.L696)/2
+ 10241 0015 40       		.byte	(.L694-.L696)/2
+ 10242 0016 40       		.byte	(.L694-.L696)/2
+ 10243 0017 40       		.byte	(.L694-.L696)/2
+ 10244 0018 28       		.byte	(.L698-.L696)/2
+ 10245 0019 40       		.byte	(.L694-.L696)/2
+ 10246 001a 40       		.byte	(.L694-.L696)/2
+ 10247 001b 40       		.byte	(.L694-.L696)/2
+ 10248 001c 30       		.byte	(.L697-.L696)/2
+ 10249 001d 40       		.byte	(.L694-.L696)/2
+ 10250 001e 40       		.byte	(.L694-.L696)/2
+ 10251 001f 40       		.byte	(.L694-.L696)/2
+ 10252 0020 38       		.byte	(.L695-.L696)/2
+ 10253 0021 00       		.p2align 1
+ 10254              	.L700:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10255              		.loc 1 1074 7 is_stmt 0 discriminator 1 view .LVU3272
+ARM GAS  /tmp/cc0wMqvE.s 			page 368
+
+
+ 10256 0022 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 10257              	.LVL831:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10258              		.loc 1 1074 7 discriminator 1 view .LVU3273
+ 10259 0026 C0B2     		uxtb	r0, r0
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10260              		.loc 1 1074 44 discriminator 1 view .LVU3274
+ 10261 0028 0228     		cmp	r0, #2
+ 10262 002a 14BF     		ite	ne
+ 10263 002c 0020     		movne	r0, #0
+ 10264 002e 0120     		moveq	r0, #1
+ 10265              	.L701:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10266              		.loc 1 1074 6 discriminator 20 view .LVU3275
+ 10267 0030 0028     		cmp	r0, #0
+ 10268 0032 40F05981 		bne	.L729
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10269              		.loc 1 1078 8 is_stmt 1 view .LVU3276
+ 10270 0036 102D     		cmp	r5, #16
+ 10271 0038 74D8     		bhi	.L703
+ 10272 003a DFE805F0 		tbb	[pc, r5]
+ 10273              	.L705:
+ 10274 003e 31       		.byte	(.L709-.L705)/2
+ 10275 003f 73       		.byte	(.L703-.L705)/2
+ 10276 0040 73       		.byte	(.L703-.L705)/2
+ 10277 0041 73       		.byte	(.L703-.L705)/2
+ 10278 0042 53       		.byte	(.L708-.L705)/2
+ 10279 0043 73       		.byte	(.L703-.L705)/2
+ 10280 0044 73       		.byte	(.L703-.L705)/2
+ 10281 0045 73       		.byte	(.L703-.L705)/2
+ 10282 0046 5B       		.byte	(.L707-.L705)/2
+ 10283 0047 73       		.byte	(.L703-.L705)/2
+ 10284 0048 73       		.byte	(.L703-.L705)/2
+ 10285 0049 73       		.byte	(.L703-.L705)/2
+ 10286 004a 63       		.byte	(.L706-.L705)/2
+ 10287 004b 73       		.byte	(.L703-.L705)/2
+ 10288 004c 73       		.byte	(.L703-.L705)/2
+ 10289 004d 73       		.byte	(.L703-.L705)/2
+ 10290 004e 6B       		.byte	(.L704-.L705)/2
+ 10291              	.LVL832:
+ 10292 004f 00       		.p2align 1
+ 10293              	.L699:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10294              		.loc 1 1074 7 is_stmt 0 discriminator 4 view .LVU3277
+ 10295 0050 90F83F00 		ldrb	r0, [r0, #63]	@ zero_extendqisi2
+ 10296              	.LVL833:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10297              		.loc 1 1074 7 discriminator 4 view .LVU3278
+ 10298 0054 C0B2     		uxtb	r0, r0
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10299              		.loc 1 1074 44 discriminator 4 view .LVU3279
+ 10300 0056 0228     		cmp	r0, #2
+ 10301 0058 14BF     		ite	ne
+ 10302 005a 0020     		movne	r0, #0
+ 10303 005c 0120     		moveq	r0, #1
+ 10304 005e E7E7     		b	.L701
+ 10305              	.LVL834:
+ARM GAS  /tmp/cc0wMqvE.s 			page 369
+
+
+ 10306              	.L698:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10307              		.loc 1 1074 7 discriminator 7 view .LVU3280
+ 10308 0060 90F84000 		ldrb	r0, [r0, #64]	@ zero_extendqisi2
+ 10309              	.LVL835:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10310              		.loc 1 1074 7 discriminator 7 view .LVU3281
+ 10311 0064 C0B2     		uxtb	r0, r0
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10312              		.loc 1 1074 44 discriminator 7 view .LVU3282
+ 10313 0066 0228     		cmp	r0, #2
+ 10314 0068 14BF     		ite	ne
+ 10315 006a 0020     		movne	r0, #0
+ 10316 006c 0120     		moveq	r0, #1
+ 10317 006e DFE7     		b	.L701
+ 10318              	.LVL836:
+ 10319              	.L697:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10320              		.loc 1 1074 7 discriminator 10 view .LVU3283
+ 10321 0070 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 10322              	.LVL837:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10323              		.loc 1 1074 7 discriminator 10 view .LVU3284
+ 10324 0074 C0B2     		uxtb	r0, r0
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10325              		.loc 1 1074 44 discriminator 10 view .LVU3285
+ 10326 0076 0228     		cmp	r0, #2
+ 10327 0078 14BF     		ite	ne
+ 10328 007a 0020     		movne	r0, #0
+ 10329 007c 0120     		moveq	r0, #1
+ 10330 007e D7E7     		b	.L701
+ 10331              	.LVL838:
+ 10332              	.L695:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10333              		.loc 1 1074 7 discriminator 13 view .LVU3286
+ 10334 0080 90F84200 		ldrb	r0, [r0, #66]	@ zero_extendqisi2
+ 10335              	.LVL839:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10336              		.loc 1 1074 7 discriminator 13 view .LVU3287
+ 10337 0084 C0B2     		uxtb	r0, r0
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10338              		.loc 1 1074 44 discriminator 13 view .LVU3288
+ 10339 0086 0228     		cmp	r0, #2
+ 10340 0088 14BF     		ite	ne
+ 10341 008a 0020     		movne	r0, #0
+ 10342 008c 0120     		moveq	r0, #1
+ 10343 008e CFE7     		b	.L701
+ 10344              	.LVL840:
+ 10345              	.L694:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10346              		.loc 1 1074 7 discriminator 14 view .LVU3289
+ 10347 0090 90F84300 		ldrb	r0, [r0, #67]	@ zero_extendqisi2
+ 10348              	.LVL841:
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10349              		.loc 1 1074 7 discriminator 14 view .LVU3290
+ 10350 0094 C0B2     		uxtb	r0, r0
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 370
+
+
+ 10351              		.loc 1 1074 44 discriminator 14 view .LVU3291
+ 10352 0096 0228     		cmp	r0, #2
+ 10353 0098 14BF     		ite	ne
+ 10354 009a 0020     		movne	r0, #0
+ 10355 009c 0120     		moveq	r0, #1
+ 10356 009e C7E7     		b	.L701
+ 10357              	.L709:
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10358              		.loc 1 1078 12 discriminator 1 view .LVU3292
+ 10359 00a0 94F83E20 		ldrb	r2, [r4, #62]	@ zero_extendqisi2
+ 10360 00a4 D2B2     		uxtb	r2, r2
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10361              		.loc 1 1078 49 discriminator 1 view .LVU3293
+ 10362 00a6 012A     		cmp	r2, #1
+ 10363 00a8 14BF     		ite	ne
+ 10364 00aa 0022     		movne	r2, #0
+ 10365 00ac 0122     		moveq	r2, #1
+ 10366              	.L710:
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10367              		.loc 1 1078 11 discriminator 20 view .LVU3294
+ 10368 00ae 002A     		cmp	r2, #0
+ 10369 00b0 00F01C81 		beq	.L730
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10370              		.loc 1 1080 5 is_stmt 1 view .LVU3295
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10371              		.loc 1 1080 8 is_stmt 0 view .LVU3296
+ 10372 00b4 0029     		cmp	r1, #0
+ 10373 00b6 3DD0     		beq	.L744
+ 10374              	.L711:
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10375              		.loc 1 1086 7 is_stmt 1 view .LVU3297
+ 10376 00b8 102D     		cmp	r5, #16
+ 10377 00ba 00F2E580 		bhi	.L712
+ 10378 00be DFE815F0 		tbh	[pc, r5, lsl #1]
+ 10379              	.L714:
+ 10380 00c2 3D00     		.2byte	(.L718-.L714)/2
+ 10381 00c4 E300     		.2byte	(.L712-.L714)/2
+ 10382 00c6 E300     		.2byte	(.L712-.L714)/2
+ 10383 00c8 E300     		.2byte	(.L712-.L714)/2
+ 10384 00ca 9300     		.2byte	(.L717-.L714)/2
+ 10385 00cc E300     		.2byte	(.L712-.L714)/2
+ 10386 00ce E300     		.2byte	(.L712-.L714)/2
+ 10387 00d0 E300     		.2byte	(.L712-.L714)/2
+ 10388 00d2 AC00     		.2byte	(.L716-.L714)/2
+ 10389 00d4 E300     		.2byte	(.L712-.L714)/2
+ 10390 00d6 E300     		.2byte	(.L712-.L714)/2
+ 10391 00d8 E300     		.2byte	(.L712-.L714)/2
+ 10392 00da C500     		.2byte	(.L715-.L714)/2
+ 10393 00dc E300     		.2byte	(.L712-.L714)/2
+ 10394 00de E300     		.2byte	(.L712-.L714)/2
+ 10395 00e0 E300     		.2byte	(.L712-.L714)/2
+ 10396 00e2 DE00     		.2byte	(.L713-.L714)/2
+ 10397              		.p2align 1
+ 10398              	.L708:
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10399              		.loc 1 1078 12 is_stmt 0 discriminator 4 view .LVU3298
+ 10400 00e4 94F83F20 		ldrb	r2, [r4, #63]	@ zero_extendqisi2
+ARM GAS  /tmp/cc0wMqvE.s 			page 371
+
+
+ 10401 00e8 D2B2     		uxtb	r2, r2
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10402              		.loc 1 1078 49 discriminator 4 view .LVU3299
+ 10403 00ea 012A     		cmp	r2, #1
+ 10404 00ec 14BF     		ite	ne
+ 10405 00ee 0022     		movne	r2, #0
+ 10406 00f0 0122     		moveq	r2, #1
+ 10407 00f2 DCE7     		b	.L710
+ 10408              	.L707:
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10409              		.loc 1 1078 12 discriminator 7 view .LVU3300
+ 10410 00f4 94F84020 		ldrb	r2, [r4, #64]	@ zero_extendqisi2
+ 10411 00f8 D2B2     		uxtb	r2, r2
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10412              		.loc 1 1078 49 discriminator 7 view .LVU3301
+ 10413 00fa 012A     		cmp	r2, #1
+ 10414 00fc 14BF     		ite	ne
+ 10415 00fe 0022     		movne	r2, #0
+ 10416 0100 0122     		moveq	r2, #1
+ 10417 0102 D4E7     		b	.L710
+ 10418              	.L706:
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10419              		.loc 1 1078 12 discriminator 10 view .LVU3302
+ 10420 0104 94F84120 		ldrb	r2, [r4, #65]	@ zero_extendqisi2
+ 10421 0108 D2B2     		uxtb	r2, r2
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10422              		.loc 1 1078 49 discriminator 10 view .LVU3303
+ 10423 010a 012A     		cmp	r2, #1
+ 10424 010c 14BF     		ite	ne
+ 10425 010e 0022     		movne	r2, #0
+ 10426 0110 0122     		moveq	r2, #1
+ 10427 0112 CCE7     		b	.L710
+ 10428              	.L704:
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10429              		.loc 1 1078 12 discriminator 13 view .LVU3304
+ 10430 0114 94F84220 		ldrb	r2, [r4, #66]	@ zero_extendqisi2
+ 10431 0118 D2B2     		uxtb	r2, r2
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10432              		.loc 1 1078 49 discriminator 13 view .LVU3305
+ 10433 011a 012A     		cmp	r2, #1
+ 10434 011c 14BF     		ite	ne
+ 10435 011e 0022     		movne	r2, #0
+ 10436 0120 0122     		moveq	r2, #1
+ 10437 0122 C4E7     		b	.L710
+ 10438              	.L703:
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10439              		.loc 1 1078 12 discriminator 14 view .LVU3306
+ 10440 0124 94F84320 		ldrb	r2, [r4, #67]	@ zero_extendqisi2
+ 10441 0128 D2B2     		uxtb	r2, r2
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10442              		.loc 1 1078 49 discriminator 14 view .LVU3307
+ 10443 012a 012A     		cmp	r2, #1
+ 10444 012c 14BF     		ite	ne
+ 10445 012e 0022     		movne	r2, #0
+ 10446 0130 0122     		moveq	r2, #1
+ 10447 0132 BCE7     		b	.L710
+ 10448              	.L744:
+ARM GAS  /tmp/cc0wMqvE.s 			page 372
+
+
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10449              		.loc 1 1080 25 discriminator 1 view .LVU3308
+ 10450 0134 002B     		cmp	r3, #0
+ 10451 0136 BFD0     		beq	.L711
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10452              		.loc 1 1082 14 view .LVU3309
+ 10453 0138 0120     		movs	r0, #1
+ 10454 013a D8E0     		b	.L702
+ 10455              	.L718:
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10456              		.loc 1 1086 7 view .LVU3310
+ 10457 013c 0222     		movs	r2, #2
+ 10458 013e 84F83E20 		strb	r2, [r4, #62]
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10459              		.loc 1 1094 3 is_stmt 1 view .LVU3311
+ 10460              	.L719:
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10461              		.loc 1 1099 7 view .LVU3312
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10462              		.loc 1 1099 17 is_stmt 0 view .LVU3313
+ 10463 0142 626A     		ldr	r2, [r4, #36]
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10464              		.loc 1 1099 52 view .LVU3314
+ 10465 0144 7148     		ldr	r0, .L745
+ 10466 0146 D062     		str	r0, [r2, #44]
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10467              		.loc 1 1100 7 is_stmt 1 view .LVU3315
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10468              		.loc 1 1100 17 is_stmt 0 view .LVU3316
+ 10469 0148 626A     		ldr	r2, [r4, #36]
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10470              		.loc 1 1100 56 view .LVU3317
+ 10471 014a 7148     		ldr	r0, .L745+4
+ 10472 014c 1063     		str	r0, [r2, #48]
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10473              		.loc 1 1103 7 is_stmt 1 view .LVU3318
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10474              		.loc 1 1103 17 is_stmt 0 view .LVU3319
+ 10475 014e 626A     		ldr	r2, [r4, #36]
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10476              		.loc 1 1103 53 view .LVU3320
+ 10477 0150 7048     		ldr	r0, .L745+8
+ 10478 0152 5063     		str	r0, [r2, #52]
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10479              		.loc 1 1106 7 is_stmt 1 view .LVU3321
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10480              		.loc 1 1106 88 is_stmt 0 view .LVU3322
+ 10481 0154 2268     		ldr	r2, [r4]
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10482              		.loc 1 1106 11 view .LVU3323
+ 10483 0156 3432     		adds	r2, r2, #52
+ 10484 0158 606A     		ldr	r0, [r4, #36]
+ 10485 015a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 10486              	.LVL842:
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10487              		.loc 1 1106 10 view .LVU3324
+ 10488 015e 0028     		cmp	r0, #0
+ARM GAS  /tmp/cc0wMqvE.s 			page 373
+
+
+ 10489 0160 40F0C880 		bne	.L733
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10490              		.loc 1 1114 7 is_stmt 1 view .LVU3325
+ 10491 0164 2268     		ldr	r2, [r4]
+ 10492 0166 D368     		ldr	r3, [r2, #12]
+ 10493 0168 43F40073 		orr	r3, r3, #512
+ 10494 016c D360     		str	r3, [r2, #12]
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10495              		.loc 1 1115 7 view .LVU3326
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10496              		.loc 1 1187 3 view .LVU3327
+ 10497              	.L724:
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10498              		.loc 1 1190 5 view .LVU3328
+ 10499 016e 0122     		movs	r2, #1
+ 10500 0170 2946     		mov	r1, r5
+ 10501 0172 2068     		ldr	r0, [r4]
+ 10502 0174 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 10503              	.LVL843:
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10504              		.loc 1 1192 5 view .LVU3329
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10505              		.loc 1 1192 9 is_stmt 0 view .LVU3330
+ 10506 0178 2368     		ldr	r3, [r4]
+ 10507 017a 674A     		ldr	r2, .L745+12
+ 10508 017c 9342     		cmp	r3, r2
+ 10509 017e 0FD0     		beq	.L725
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10510              		.loc 1 1192 9 discriminator 2 view .LVU3331
+ 10511 0180 02F50062 		add	r2, r2, #2048
+ 10512 0184 9342     		cmp	r3, r2
+ 10513 0186 0BD0     		beq	.L725
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10514              		.loc 1 1192 9 discriminator 4 view .LVU3332
+ 10515 0188 02F54062 		add	r2, r2, #3072
+ 10516 018c 9342     		cmp	r3, r2
+ 10517 018e 07D0     		beq	.L725
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10518              		.loc 1 1192 9 discriminator 6 view .LVU3333
+ 10519 0190 02F58062 		add	r2, r2, #1024
+ 10520 0194 9342     		cmp	r3, r2
+ 10521 0196 03D0     		beq	.L725
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10522              		.loc 1 1192 9 discriminator 8 view .LVU3334
+ 10523 0198 02F58062 		add	r2, r2, #1024
+ 10524 019c 9342     		cmp	r3, r2
+ 10525 019e 03D1     		bne	.L726
+ 10526              	.L725:
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10527              		.loc 1 1195 7 is_stmt 1 view .LVU3335
+ 10528 01a0 5A6C     		ldr	r2, [r3, #68]
+ 10529 01a2 42F40042 		orr	r2, r2, #32768
+ 10530 01a6 5A64     		str	r2, [r3, #68]
+ 10531              	.L726:
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10532              		.loc 1 1199 5 view .LVU3336
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ARM GAS  /tmp/cc0wMqvE.s 			page 374
+
+
+ 10533              		.loc 1 1199 9 is_stmt 0 view .LVU3337
+ 10534 01a8 2368     		ldr	r3, [r4]
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10535              		.loc 1 1199 8 view .LVU3338
+ 10536 01aa 5B4A     		ldr	r2, .L745+12
+ 10537 01ac 9342     		cmp	r3, r2
+ 10538 01ae 00F08D80 		beq	.L727
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10539              		.loc 1 1199 9 discriminator 1 view .LVU3339
+ 10540 01b2 B3F1804F 		cmp	r3, #1073741824
+ 10541 01b6 00F08980 		beq	.L727
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10542              		.loc 1 1199 9 discriminator 2 view .LVU3340
+ 10543 01ba A2F59432 		sub	r2, r2, #75776
+ 10544 01be 9342     		cmp	r3, r2
+ 10545 01c0 00F08480 		beq	.L727
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10546              		.loc 1 1199 9 discriminator 3 view .LVU3341
+ 10547 01c4 02F58062 		add	r2, r2, #1024
+ 10548 01c8 9342     		cmp	r3, r2
+ 10549 01ca 7FD0     		beq	.L727
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10550              		.loc 1 1199 9 discriminator 4 view .LVU3342
+ 10551 01cc 02F59632 		add	r2, r2, #76800
+ 10552 01d0 9342     		cmp	r3, r2
+ 10553 01d2 7BD0     		beq	.L727
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10554              		.loc 1 1199 9 discriminator 5 view .LVU3343
+ 10555 01d4 02F54062 		add	r2, r2, #3072
+ 10556 01d8 9342     		cmp	r3, r2
+ 10557 01da 77D0     		beq	.L727
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10558              		.loc 1 1209 7 is_stmt 1 view .LVU3344
+ 10559 01dc 1A68     		ldr	r2, [r3]
+ 10560 01de 42F00102 		orr	r2, r2, #1
+ 10561 01e2 1A60     		str	r2, [r3]
+ 10562 01e4 0020     		movs	r0, #0
+ 10563 01e6 82E0     		b	.L702
+ 10564              	.LVL844:
+ 10565              	.L717:
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10566              		.loc 1 1086 7 is_stmt 0 view .LVU3345
+ 10567 01e8 0222     		movs	r2, #2
+ 10568 01ea 84F83F20 		strb	r2, [r4, #63]
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10569              		.loc 1 1094 3 is_stmt 1 view .LVU3346
+ 10570              	.L720:
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10571              		.loc 1 1121 7 view .LVU3347
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10572              		.loc 1 1121 17 is_stmt 0 view .LVU3348
+ 10573 01ee A26A     		ldr	r2, [r4, #40]
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10574              		.loc 1 1121 52 view .LVU3349
+ 10575 01f0 4648     		ldr	r0, .L745
+ 10576 01f2 D062     		str	r0, [r2, #44]
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 375
+
+
+ 10577              		.loc 1 1122 7 is_stmt 1 view .LVU3350
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10578              		.loc 1 1122 17 is_stmt 0 view .LVU3351
+ 10579 01f4 A26A     		ldr	r2, [r4, #40]
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10580              		.loc 1 1122 56 view .LVU3352
+ 10581 01f6 4648     		ldr	r0, .L745+4
+ 10582 01f8 1063     		str	r0, [r2, #48]
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10583              		.loc 1 1125 7 is_stmt 1 view .LVU3353
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10584              		.loc 1 1125 17 is_stmt 0 view .LVU3354
+ 10585 01fa A26A     		ldr	r2, [r4, #40]
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10586              		.loc 1 1125 53 view .LVU3355
+ 10587 01fc 4548     		ldr	r0, .L745+8
+ 10588 01fe 5063     		str	r0, [r2, #52]
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10589              		.loc 1 1128 7 is_stmt 1 view .LVU3356
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10590              		.loc 1 1128 88 is_stmt 0 view .LVU3357
+ 10591 0200 2268     		ldr	r2, [r4]
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10592              		.loc 1 1128 11 view .LVU3358
+ 10593 0202 3832     		adds	r2, r2, #56
+ 10594 0204 A06A     		ldr	r0, [r4, #40]
+ 10595 0206 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 10596              	.LVL845:
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10597              		.loc 1 1128 10 view .LVU3359
+ 10598 020a 0028     		cmp	r0, #0
+ 10599 020c 74D1     		bne	.L734
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10600              		.loc 1 1136 7 is_stmt 1 view .LVU3360
+ 10601 020e 2268     		ldr	r2, [r4]
+ 10602 0210 D368     		ldr	r3, [r2, #12]
+ 10603 0212 43F48063 		orr	r3, r3, #1024
+ 10604 0216 D360     		str	r3, [r2, #12]
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10605              		.loc 1 1137 7 view .LVU3361
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10606              		.loc 1 1187 3 view .LVU3362
+ 10607 0218 A9E7     		b	.L724
+ 10608              	.LVL846:
+ 10609              	.L716:
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10610              		.loc 1 1086 7 is_stmt 0 view .LVU3363
+ 10611 021a 0222     		movs	r2, #2
+ 10612 021c 84F84020 		strb	r2, [r4, #64]
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10613              		.loc 1 1094 3 is_stmt 1 view .LVU3364
+ 10614              	.L721:
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10615              		.loc 1 1143 7 view .LVU3365
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10616              		.loc 1 1143 17 is_stmt 0 view .LVU3366
+ 10617 0220 E26A     		ldr	r2, [r4, #44]
+ARM GAS  /tmp/cc0wMqvE.s 			page 376
+
+
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10618              		.loc 1 1143 52 view .LVU3367
+ 10619 0222 3A48     		ldr	r0, .L745
+ 10620 0224 D062     		str	r0, [r2, #44]
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10621              		.loc 1 1144 7 is_stmt 1 view .LVU3368
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10622              		.loc 1 1144 17 is_stmt 0 view .LVU3369
+ 10623 0226 E26A     		ldr	r2, [r4, #44]
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10624              		.loc 1 1144 56 view .LVU3370
+ 10625 0228 3948     		ldr	r0, .L745+4
+ 10626 022a 1063     		str	r0, [r2, #48]
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10627              		.loc 1 1147 7 is_stmt 1 view .LVU3371
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10628              		.loc 1 1147 17 is_stmt 0 view .LVU3372
+ 10629 022c E26A     		ldr	r2, [r4, #44]
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10630              		.loc 1 1147 53 view .LVU3373
+ 10631 022e 3948     		ldr	r0, .L745+8
+ 10632 0230 5063     		str	r0, [r2, #52]
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10633              		.loc 1 1150 7 is_stmt 1 view .LVU3374
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10634              		.loc 1 1150 88 is_stmt 0 view .LVU3375
+ 10635 0232 2268     		ldr	r2, [r4]
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10636              		.loc 1 1150 11 view .LVU3376
+ 10637 0234 3C32     		adds	r2, r2, #60
+ 10638 0236 E06A     		ldr	r0, [r4, #44]
+ 10639 0238 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 10640              	.LVL847:
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10641              		.loc 1 1150 10 view .LVU3377
+ 10642 023c 0028     		cmp	r0, #0
+ 10643 023e 5DD1     		bne	.L735
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10644              		.loc 1 1157 7 is_stmt 1 view .LVU3378
+ 10645 0240 2268     		ldr	r2, [r4]
+ 10646 0242 D368     		ldr	r3, [r2, #12]
+ 10647 0244 43F40063 		orr	r3, r3, #2048
+ 10648 0248 D360     		str	r3, [r2, #12]
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10649              		.loc 1 1158 7 view .LVU3379
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10650              		.loc 1 1187 3 view .LVU3380
+ 10651 024a 90E7     		b	.L724
+ 10652              	.LVL848:
+ 10653              	.L715:
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10654              		.loc 1 1086 7 is_stmt 0 view .LVU3381
+ 10655 024c 0222     		movs	r2, #2
+ 10656 024e 84F84120 		strb	r2, [r4, #65]
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10657              		.loc 1 1094 3 is_stmt 1 view .LVU3382
+ 10658              	.L722:
+ARM GAS  /tmp/cc0wMqvE.s 			page 377
+
+
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10659              		.loc 1 1164 7 view .LVU3383
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10660              		.loc 1 1164 17 is_stmt 0 view .LVU3384
+ 10661 0252 226B     		ldr	r2, [r4, #48]
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10662              		.loc 1 1164 52 view .LVU3385
+ 10663 0254 2D48     		ldr	r0, .L745
+ 10664 0256 D062     		str	r0, [r2, #44]
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10665              		.loc 1 1165 7 is_stmt 1 view .LVU3386
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10666              		.loc 1 1165 17 is_stmt 0 view .LVU3387
+ 10667 0258 226B     		ldr	r2, [r4, #48]
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10668              		.loc 1 1165 56 view .LVU3388
+ 10669 025a 2D48     		ldr	r0, .L745+4
+ 10670 025c 1063     		str	r0, [r2, #48]
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10671              		.loc 1 1168 7 is_stmt 1 view .LVU3389
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10672              		.loc 1 1168 17 is_stmt 0 view .LVU3390
+ 10673 025e 226B     		ldr	r2, [r4, #48]
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10674              		.loc 1 1168 53 view .LVU3391
+ 10675 0260 2C48     		ldr	r0, .L745+8
+ 10676 0262 5063     		str	r0, [r2, #52]
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10677              		.loc 1 1171 7 is_stmt 1 view .LVU3392
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10678              		.loc 1 1171 88 is_stmt 0 view .LVU3393
+ 10679 0264 2268     		ldr	r2, [r4]
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10680              		.loc 1 1171 11 view .LVU3394
+ 10681 0266 4032     		adds	r2, r2, #64
+ 10682 0268 206B     		ldr	r0, [r4, #48]
+ 10683 026a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 10684              	.LVL849:
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10685              		.loc 1 1171 10 view .LVU3395
+ 10686 026e 0028     		cmp	r0, #0
+ 10687 0270 46D1     		bne	.L736
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10688              		.loc 1 1178 7 is_stmt 1 view .LVU3396
+ 10689 0272 2268     		ldr	r2, [r4]
+ 10690 0274 D368     		ldr	r3, [r2, #12]
+ 10691 0276 43F48053 		orr	r3, r3, #4096
+ 10692 027a D360     		str	r3, [r2, #12]
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10693              		.loc 1 1179 7 view .LVU3397
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10694              		.loc 1 1187 3 view .LVU3398
+ 10695 027c 77E7     		b	.L724
+ 10696              	.LVL850:
+ 10697              	.L713:
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10698              		.loc 1 1086 7 is_stmt 0 view .LVU3399
+ARM GAS  /tmp/cc0wMqvE.s 			page 378
+
+
+ 10699 027e 0223     		movs	r3, #2
+ 10700              	.LVL851:
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10701              		.loc 1 1086 7 view .LVU3400
+ 10702 0280 84F84230 		strb	r3, [r4, #66]
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10703              		.loc 1 1094 3 is_stmt 1 view .LVU3401
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10704              		.loc 1 1086 7 is_stmt 0 view .LVU3402
+ 10705 0284 0120     		movs	r0, #1
+ 10706 0286 32E0     		b	.L702
+ 10707              	.LVL852:
+ 10708              	.L712:
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10709              		.loc 1 1086 7 discriminator 13 view .LVU3403
+ 10710 0288 0222     		movs	r2, #2
+ 10711 028a 84F84320 		strb	r2, [r4, #67]
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10712              		.loc 1 1094 3 is_stmt 1 discriminator 13 view .LVU3404
+ 10713 028e 0C2D     		cmp	r5, #12
+ 10714 0290 2ED8     		bhi	.L732
+ 10715 0292 01A2     		adr	r2, .L723
+ 10716 0294 52F825F0 		ldr	pc, [r2, r5, lsl #2]
+ 10717              		.p2align 2
+ 10718              	.L723:
+ 10719 0298 43010000 		.word	.L719+1
+ 10720 029c F1020000 		.word	.L732+1
+ 10721 02a0 F1020000 		.word	.L732+1
+ 10722 02a4 F1020000 		.word	.L732+1
+ 10723 02a8 EF010000 		.word	.L720+1
+ 10724 02ac F1020000 		.word	.L732+1
+ 10725 02b0 F1020000 		.word	.L732+1
+ 10726 02b4 F1020000 		.word	.L732+1
+ 10727 02b8 21020000 		.word	.L721+1
+ 10728 02bc F1020000 		.word	.L732+1
+ 10729 02c0 F1020000 		.word	.L732+1
+ 10730 02c4 F1020000 		.word	.L732+1
+ 10731 02c8 53020000 		.word	.L722+1
+ 10732              	.LVL853:
+ 10733              		.p2align 1
+ 10734              	.L727:
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 10735              		.loc 1 1201 7 view .LVU3405
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 10736              		.loc 1 1201 31 is_stmt 0 view .LVU3406
+ 10737 02cc 9968     		ldr	r1, [r3, #8]
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 10738              		.loc 1 1201 15 view .LVU3407
+ 10739 02ce 134A     		ldr	r2, .L745+16
+ 10740 02d0 0A40     		ands	r2, r2, r1
+ 10741              	.LVL854:
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 10742              		.loc 1 1202 7 is_stmt 1 view .LVU3408
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 10743              		.loc 1 1202 10 is_stmt 0 view .LVU3409
+ 10744 02d2 062A     		cmp	r2, #6
+ 10745 02d4 16D0     		beq	.L737
+ARM GAS  /tmp/cc0wMqvE.s 			page 379
+
+
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 10746              		.loc 1 1202 11 discriminator 1 view .LVU3410
+ 10747 02d6 B2F5803F 		cmp	r2, #65536
+ 10748 02da 15D0     		beq	.L738
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 10749              		.loc 1 1204 9 is_stmt 1 view .LVU3411
+ 10750 02dc 1A68     		ldr	r2, [r3]
+ 10751              	.LVL855:
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 10752              		.loc 1 1204 9 is_stmt 0 view .LVU3412
+ 10753 02de 42F00102 		orr	r2, r2, #1
+ 10754 02e2 1A60     		str	r2, [r3]
+ 10755 02e4 0020     		movs	r0, #0
+ 10756 02e6 02E0     		b	.L702
+ 10757              	.LVL856:
+ 10758              	.L729:
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 10759              		.loc 1 1076 12 view .LVU3413
+ 10760 02e8 0220     		movs	r0, #2
+ 10761 02ea 00E0     		b	.L702
+ 10762              	.L730:
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 10763              		.loc 1 1091 12 view .LVU3414
+ 10764 02ec 0120     		movs	r0, #1
+ 10765              	.LVL857:
+ 10766              	.L702:
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10767              		.loc 1 1215 1 view .LVU3415
+ 10768 02ee 38BD     		pop	{r3, r4, r5, pc}
+ 10769              	.LVL858:
+ 10770              	.L732:
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10771              		.loc 1 1094 3 view .LVU3416
+ 10772 02f0 0120     		movs	r0, #1
+ 10773 02f2 FCE7     		b	.L702
+ 10774              	.LVL859:
+ 10775              	.L733:
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 10776              		.loc 1 1110 16 view .LVU3417
+ 10777 02f4 0120     		movs	r0, #1
+ 10778 02f6 FAE7     		b	.L702
+ 10779              	.L734:
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 10780              		.loc 1 1132 16 view .LVU3418
+ 10781 02f8 0120     		movs	r0, #1
+ 10782 02fa F8E7     		b	.L702
+ 10783              	.L735:
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 10784              		.loc 1 1154 16 view .LVU3419
+ 10785 02fc 0120     		movs	r0, #1
+ 10786 02fe F6E7     		b	.L702
+ 10787              	.L736:
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 10788              		.loc 1 1175 16 view .LVU3420
+ 10789 0300 0120     		movs	r0, #1
+ 10790 0302 F4E7     		b	.L702
+ 10791              	.LVL860:
+ARM GAS  /tmp/cc0wMqvE.s 			page 380
+
+
+ 10792              	.L737:
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 10793              		.loc 1 1175 16 view .LVU3421
+ 10794 0304 0020     		movs	r0, #0
+ 10795 0306 F2E7     		b	.L702
+ 10796              	.L738:
+ 10797 0308 0020     		movs	r0, #0
+ 10798 030a F0E7     		b	.L702
+ 10799              	.L746:
+ 10800              		.align	2
+ 10801              	.L745:
+ 10802 030c 00000000 		.word	TIM_DMADelayPulseCplt
+ 10803 0310 00000000 		.word	TIM_DMADelayPulseHalfCplt
+ 10804 0314 00000000 		.word	TIM_DMAError
+ 10805 0318 002C0140 		.word	1073818624
+ 10806 031c 07000100 		.word	65543
+ 10807              		.cfi_endproc
+ 10808              	.LFE347:
+ 10810              		.section	.text.HAL_TIM_OC_Stop_DMA,"ax",%progbits
+ 10811              		.align	1
+ 10812              		.global	HAL_TIM_OC_Stop_DMA
+ 10813              		.syntax unified
+ 10814              		.thumb
+ 10815              		.thumb_func
+ 10817              	HAL_TIM_OC_Stop_DMA:
+ 10818              	.LVL861:
+ 10819              	.LFB348:
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 10820              		.loc 1 1229 1 is_stmt 1 view -0
+ 10821              		.cfi_startproc
+ 10822              		@ args = 0, pretend = 0, frame = 0
+ 10823              		@ frame_needed = 0, uses_anonymous_args = 0
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 10824              		.loc 1 1229 1 is_stmt 0 view .LVU3423
+ 10825 0000 38B5     		push	{r3, r4, r5, lr}
+ 10826              	.LCFI90:
+ 10827              		.cfi_def_cfa_offset 16
+ 10828              		.cfi_offset 3, -16
+ 10829              		.cfi_offset 4, -12
+ 10830              		.cfi_offset 5, -8
+ 10831              		.cfi_offset 14, -4
+ 10832 0002 0546     		mov	r5, r0
+ 10833 0004 0C46     		mov	r4, r1
+1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10834              		.loc 1 1230 3 is_stmt 1 view .LVU3424
+ 10835              	.LVL862:
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10836              		.loc 1 1233 3 view .LVU3425
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10837              		.loc 1 1235 3 view .LVU3426
+ 10838 0006 0C29     		cmp	r1, #12
+ 10839 0008 00F28D80 		bhi	.L765
+ 10840 000c DFE801F0 		tbb	[pc, r1]
+ 10841              	.L750:
+ 10842 0010 07       		.byte	(.L753-.L750)/2
+ 10843 0011 8B       		.byte	(.L765-.L750)/2
+ 10844 0012 8B       		.byte	(.L765-.L750)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 381
+
+
+ 10845 0013 8B       		.byte	(.L765-.L750)/2
+ 10846 0014 4B       		.byte	(.L752-.L750)/2
+ 10847 0015 8B       		.byte	(.L765-.L750)/2
+ 10848 0016 8B       		.byte	(.L765-.L750)/2
+ 10849 0017 8B       		.byte	(.L765-.L750)/2
+ 10850 0018 54       		.byte	(.L751-.L750)/2
+ 10851 0019 8B       		.byte	(.L765-.L750)/2
+ 10852 001a 8B       		.byte	(.L765-.L750)/2
+ 10853 001b 8B       		.byte	(.L765-.L750)/2
+ 10854 001c 5D       		.byte	(.L749-.L750)/2
+ 10855 001d 00       		.p2align 1
+ 10856              	.L753:
+1240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 10857              		.loc 1 1240 7 view .LVU3427
+ 10858 001e 0268     		ldr	r2, [r0]
+ 10859 0020 D368     		ldr	r3, [r2, #12]
+ 10860 0022 23F40073 		bic	r3, r3, #512
+ 10861 0026 D360     		str	r3, [r2, #12]
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10862              		.loc 1 1241 7 view .LVU3428
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10863              		.loc 1 1241 13 is_stmt 0 view .LVU3429
+ 10864 0028 406A     		ldr	r0, [r0, #36]
+ 10865              	.LVL863:
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10866              		.loc 1 1241 13 view .LVU3430
+ 10867 002a FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 10868              	.LVL864:
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10869              		.loc 1 1242 7 is_stmt 1 view .LVU3431
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10870              		.loc 1 1274 3 view .LVU3432
+ 10871              	.L754:
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10872              		.loc 1 1277 5 view .LVU3433
+ 10873 002e 0022     		movs	r2, #0
+ 10874 0030 2146     		mov	r1, r4
+ 10875 0032 2868     		ldr	r0, [r5]
+ 10876 0034 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 10877              	.LVL865:
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10878              		.loc 1 1279 5 view .LVU3434
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10879              		.loc 1 1279 9 is_stmt 0 view .LVU3435
+ 10880 0038 2B68     		ldr	r3, [r5]
+ 10881 003a 3C4A     		ldr	r2, .L767
+ 10882 003c 9342     		cmp	r3, r2
+ 10883 003e 0FD0     		beq	.L755
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10884              		.loc 1 1279 9 discriminator 2 view .LVU3436
+ 10885 0040 02F50062 		add	r2, r2, #2048
+ 10886 0044 9342     		cmp	r3, r2
+ 10887 0046 0BD0     		beq	.L755
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10888              		.loc 1 1279 9 discriminator 4 view .LVU3437
+ 10889 0048 02F54062 		add	r2, r2, #3072
+ 10890 004c 9342     		cmp	r3, r2
+ARM GAS  /tmp/cc0wMqvE.s 			page 382
+
+
+ 10891 004e 07D0     		beq	.L755
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10892              		.loc 1 1279 9 discriminator 6 view .LVU3438
+ 10893 0050 02F58062 		add	r2, r2, #1024
+ 10894 0054 9342     		cmp	r3, r2
+ 10895 0056 03D0     		beq	.L755
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 10896              		.loc 1 1279 9 discriminator 8 view .LVU3439
+ 10897 0058 02F58062 		add	r2, r2, #1024
+ 10898 005c 9342     		cmp	r3, r2
+ 10899 005e 0DD1     		bne	.L756
+ 10900              	.L755:
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10901              		.loc 1 1282 7 is_stmt 1 view .LVU3440
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10902              		.loc 1 1282 7 view .LVU3441
+ 10903 0060 196A     		ldr	r1, [r3, #32]
+ 10904 0062 41F21112 		movw	r2, #4369
+ 10905 0066 1142     		tst	r1, r2
+ 10906 0068 08D1     		bne	.L756
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10907              		.loc 1 1282 7 discriminator 1 view .LVU3442
+ 10908 006a 196A     		ldr	r1, [r3, #32]
+ 10909 006c 44F24442 		movw	r2, #17476
+ 10910 0070 1142     		tst	r1, r2
+ 10911 0072 03D1     		bne	.L756
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10912              		.loc 1 1282 7 discriminator 3 view .LVU3443
+ 10913 0074 5A6C     		ldr	r2, [r3, #68]
+ 10914 0076 22F40042 		bic	r2, r2, #32768
+ 10915 007a 5A64     		str	r2, [r3, #68]
+ 10916              	.L756:
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10917              		.loc 1 1282 7 discriminator 5 view .LVU3444
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10918              		.loc 1 1286 5 discriminator 5 view .LVU3445
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10919              		.loc 1 1286 5 discriminator 5 view .LVU3446
+ 10920 007c 2B68     		ldr	r3, [r5]
+ 10921 007e 196A     		ldr	r1, [r3, #32]
+ 10922 0080 41F21112 		movw	r2, #4369
+ 10923 0084 1142     		tst	r1, r2
+ 10924 0086 08D1     		bne	.L757
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10925              		.loc 1 1286 5 discriminator 1 view .LVU3447
+ 10926 0088 196A     		ldr	r1, [r3, #32]
+ 10927 008a 44F24442 		movw	r2, #17476
+ 10928 008e 1142     		tst	r1, r2
+ 10929 0090 03D1     		bne	.L757
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10930              		.loc 1 1286 5 discriminator 3 view .LVU3448
+ 10931 0092 1A68     		ldr	r2, [r3]
+ 10932 0094 22F00102 		bic	r2, r2, #1
+ 10933 0098 1A60     		str	r2, [r3]
+ 10934              	.L757:
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 10935              		.loc 1 1286 5 discriminator 5 view .LVU3449
+ARM GAS  /tmp/cc0wMqvE.s 			page 383
+
+
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 10936              		.loc 1 1289 5 discriminator 5 view .LVU3450
+ 10937 009a FCB9     		cbnz	r4, .L758
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 10938              		.loc 1 1289 5 is_stmt 0 discriminator 1 view .LVU3451
+ 10939 009c 0123     		movs	r3, #1
+ 10940 009e 85F83E30 		strb	r3, [r5, #62]
+ 10941 00a2 0020     		movs	r0, #0
+ 10942 00a4 40E0     		b	.L748
+ 10943              	.LVL866:
+ 10944              	.L752:
+1248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 10945              		.loc 1 1248 7 is_stmt 1 view .LVU3452
+ 10946 00a6 0268     		ldr	r2, [r0]
+ 10947 00a8 D368     		ldr	r3, [r2, #12]
+ 10948 00aa 23F48063 		bic	r3, r3, #1024
+ 10949 00ae D360     		str	r3, [r2, #12]
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10950              		.loc 1 1249 7 view .LVU3453
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10951              		.loc 1 1249 13 is_stmt 0 view .LVU3454
+ 10952 00b0 806A     		ldr	r0, [r0, #40]
+ 10953              	.LVL867:
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10954              		.loc 1 1249 13 view .LVU3455
+ 10955 00b2 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 10956              	.LVL868:
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10957              		.loc 1 1250 7 is_stmt 1 view .LVU3456
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10958              		.loc 1 1274 3 view .LVU3457
+ 10959 00b6 BAE7     		b	.L754
+ 10960              	.LVL869:
+ 10961              	.L751:
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ 10962              		.loc 1 1256 7 view .LVU3458
+ 10963 00b8 0268     		ldr	r2, [r0]
+ 10964 00ba D368     		ldr	r3, [r2, #12]
+ 10965 00bc 23F40063 		bic	r3, r3, #2048
+ 10966 00c0 D360     		str	r3, [r2, #12]
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10967              		.loc 1 1257 7 view .LVU3459
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10968              		.loc 1 1257 13 is_stmt 0 view .LVU3460
+ 10969 00c2 C06A     		ldr	r0, [r0, #44]
+ 10970              	.LVL870:
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10971              		.loc 1 1257 13 view .LVU3461
+ 10972 00c4 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 10973              	.LVL871:
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10974              		.loc 1 1258 7 is_stmt 1 view .LVU3462
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10975              		.loc 1 1274 3 view .LVU3463
+ 10976 00c8 B1E7     		b	.L754
+ 10977              	.LVL872:
+ 10978              	.L749:
+ARM GAS  /tmp/cc0wMqvE.s 			page 384
+
+
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ 10979              		.loc 1 1264 7 view .LVU3464
+ 10980 00ca 0268     		ldr	r2, [r0]
+ 10981 00cc D368     		ldr	r3, [r2, #12]
+ 10982 00ce 23F48053 		bic	r3, r3, #4096
+ 10983 00d2 D360     		str	r3, [r2, #12]
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10984              		.loc 1 1265 7 view .LVU3465
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10985              		.loc 1 1265 13 is_stmt 0 view .LVU3466
+ 10986 00d4 006B     		ldr	r0, [r0, #48]
+ 10987              	.LVL873:
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 10988              		.loc 1 1265 13 view .LVU3467
+ 10989 00d6 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 10990              	.LVL874:
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 10991              		.loc 1 1266 7 is_stmt 1 view .LVU3468
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10992              		.loc 1 1274 3 view .LVU3469
+ 10993 00da A8E7     		b	.L754
+ 10994              	.L758:
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10995              		.loc 1 1274 3 is_stmt 0 view .LVU3470
+ 10996 00dc 043C     		subs	r4, r4, #4
+ 10997              	.LVL875:
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 10998              		.loc 1 1274 3 view .LVU3471
+ 10999 00de 0C2C     		cmp	r4, #12
+ 11000 00e0 1CD8     		bhi	.L759
+ 11001 00e2 DFE804F0 		tbb	[pc, r4]
+ 11002              	.L761:
+ 11003 00e6 07       		.byte	(.L764-.L761)/2
+ 11004 00e7 1B       		.byte	(.L759-.L761)/2
+ 11005 00e8 1B       		.byte	(.L759-.L761)/2
+ 11006 00e9 1B       		.byte	(.L759-.L761)/2
+ 11007 00ea 0C       		.byte	(.L763-.L761)/2
+ 11008 00eb 1B       		.byte	(.L759-.L761)/2
+ 11009 00ec 1B       		.byte	(.L759-.L761)/2
+ 11010 00ed 1B       		.byte	(.L759-.L761)/2
+ 11011 00ee 11       		.byte	(.L762-.L761)/2
+ 11012 00ef 1B       		.byte	(.L759-.L761)/2
+ 11013 00f0 1B       		.byte	(.L759-.L761)/2
+ 11014 00f1 1B       		.byte	(.L759-.L761)/2
+ 11015 00f2 16       		.byte	(.L760-.L761)/2
+ 11016 00f3 00       		.p2align 1
+ 11017              	.L764:
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11018              		.loc 1 1289 5 discriminator 3 view .LVU3472
+ 11019 00f4 0123     		movs	r3, #1
+ 11020 00f6 85F83F30 		strb	r3, [r5, #63]
+ 11021 00fa 0020     		movs	r0, #0
+ 11022 00fc 14E0     		b	.L748
+ 11023              	.L763:
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11024              		.loc 1 1289 5 discriminator 6 view .LVU3473
+ 11025 00fe 0123     		movs	r3, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 385
+
+
+ 11026 0100 85F84030 		strb	r3, [r5, #64]
+ 11027 0104 0020     		movs	r0, #0
+ 11028 0106 0FE0     		b	.L748
+ 11029              	.L762:
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11030              		.loc 1 1289 5 discriminator 9 view .LVU3474
+ 11031 0108 0123     		movs	r3, #1
+ 11032 010a 85F84130 		strb	r3, [r5, #65]
+ 11033 010e 0020     		movs	r0, #0
+ 11034 0110 0AE0     		b	.L748
+ 11035              	.L760:
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11036              		.loc 1 1289 5 discriminator 12 view .LVU3475
+ 11037 0112 0123     		movs	r3, #1
+ 11038 0114 85F84230 		strb	r3, [r5, #66]
+ 11039 0118 0020     		movs	r0, #0
+ 11040 011a 05E0     		b	.L748
+ 11041              	.L759:
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11042              		.loc 1 1289 5 discriminator 13 view .LVU3476
+ 11043 011c 0123     		movs	r3, #1
+ 11044 011e 85F84330 		strb	r3, [r5, #67]
+ 11045 0122 0020     		movs	r0, #0
+ 11046 0124 00E0     		b	.L748
+ 11047              	.LVL876:
+ 11048              	.L765:
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11049              		.loc 1 1235 3 view .LVU3477
+ 11050 0126 0120     		movs	r0, #1
+ 11051              	.LVL877:
+ 11052              	.L748:
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 11053              		.loc 1 1293 3 is_stmt 1 view .LVU3478
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11054              		.loc 1 1294 1 is_stmt 0 view .LVU3479
+ 11055 0128 38BD     		pop	{r3, r4, r5, pc}
+ 11056              	.LVL878:
+ 11057              	.L768:
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11058              		.loc 1 1294 1 view .LVU3480
+ 11059 012a 00BF     		.align	2
+ 11060              	.L767:
+ 11061 012c 002C0140 		.word	1073818624
+ 11062              		.cfi_endproc
+ 11063              	.LFE348:
+ 11065              		.section	.text.HAL_TIM_PWM_Start,"ax",%progbits
+ 11066              		.align	1
+ 11067              		.global	HAL_TIM_PWM_Start
+ 11068              		.syntax unified
+ 11069              		.thumb
+ 11070              		.thumb_func
+ 11072              	HAL_TIM_PWM_Start:
+ 11073              	.LVL879:
+ 11074              	.LFB353:
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 11075              		.loc 1 1472 1 is_stmt 1 view -0
+ 11076              		.cfi_startproc
+ARM GAS  /tmp/cc0wMqvE.s 			page 386
+
+
+ 11077              		@ args = 0, pretend = 0, frame = 0
+ 11078              		@ frame_needed = 0, uses_anonymous_args = 0
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 11079              		.loc 1 1472 1 is_stmt 0 view .LVU3482
+ 11080 0000 10B5     		push	{r4, lr}
+ 11081              	.LCFI91:
+ 11082              		.cfi_def_cfa_offset 8
+ 11083              		.cfi_offset 4, -8
+ 11084              		.cfi_offset 14, -4
+ 11085 0002 0446     		mov	r4, r0
+1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11086              		.loc 1 1473 3 is_stmt 1 view .LVU3483
+1476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11087              		.loc 1 1476 3 view .LVU3484
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11088              		.loc 1 1479 3 view .LVU3485
+ 11089 0004 1029     		cmp	r1, #16
+ 11090 0006 3CD8     		bhi	.L770
+ 11091 0008 DFE801F0 		tbb	[pc, r1]
+ 11092              	.L772:
+ 11093 000c 09       		.byte	(.L776-.L772)/2
+ 11094 000d 3B       		.byte	(.L770-.L772)/2
+ 11095 000e 3B       		.byte	(.L770-.L772)/2
+ 11096 000f 3B       		.byte	(.L770-.L772)/2
+ 11097 0010 1F       		.byte	(.L775-.L772)/2
+ 11098 0011 3B       		.byte	(.L770-.L772)/2
+ 11099 0012 3B       		.byte	(.L770-.L772)/2
+ 11100 0013 3B       		.byte	(.L770-.L772)/2
+ 11101 0014 26       		.byte	(.L774-.L772)/2
+ 11102 0015 3B       		.byte	(.L770-.L772)/2
+ 11103 0016 3B       		.byte	(.L770-.L772)/2
+ 11104 0017 3B       		.byte	(.L770-.L772)/2
+ 11105 0018 2D       		.byte	(.L773-.L772)/2
+ 11106 0019 3B       		.byte	(.L770-.L772)/2
+ 11107 001a 3B       		.byte	(.L770-.L772)/2
+ 11108 001b 3B       		.byte	(.L770-.L772)/2
+ 11109 001c 34       		.byte	(.L771-.L772)/2
+ 11110 001d 00       		.p2align 1
+ 11111              	.L776:
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11112              		.loc 1 1479 7 is_stmt 0 discriminator 1 view .LVU3486
+ 11113 001e 90F83E30 		ldrb	r3, [r0, #62]	@ zero_extendqisi2
+ 11114 0022 DBB2     		uxtb	r3, r3
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11115              		.loc 1 1479 44 discriminator 1 view .LVU3487
+ 11116 0024 013B     		subs	r3, r3, #1
+ 11117 0026 18BF     		it	ne
+ 11118 0028 0123     		movne	r3, #1
+ 11119              	.L777:
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11120              		.loc 1 1479 6 discriminator 20 view .LVU3488
+ 11121 002a 002B     		cmp	r3, #0
+ 11122 002c 40F08E80 		bne	.L791
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11123              		.loc 1 1485 3 is_stmt 1 view .LVU3489
+ 11124 0030 1029     		cmp	r1, #16
+ 11125 0032 79D8     		bhi	.L779
+ARM GAS  /tmp/cc0wMqvE.s 			page 387
+
+
+ 11126 0034 DFE801F0 		tbb	[pc, r1]
+ 11127              	.L781:
+ 11128 0038 2C       		.byte	(.L785-.L781)/2
+ 11129 0039 78       		.byte	(.L779-.L781)/2
+ 11130 003a 78       		.byte	(.L779-.L781)/2
+ 11131 003b 78       		.byte	(.L779-.L781)/2
+ 11132 003c 68       		.byte	(.L784-.L781)/2
+ 11133 003d 78       		.byte	(.L779-.L781)/2
+ 11134 003e 78       		.byte	(.L779-.L781)/2
+ 11135 003f 78       		.byte	(.L779-.L781)/2
+ 11136 0040 6C       		.byte	(.L783-.L781)/2
+ 11137 0041 78       		.byte	(.L779-.L781)/2
+ 11138 0042 78       		.byte	(.L779-.L781)/2
+ 11139 0043 78       		.byte	(.L779-.L781)/2
+ 11140 0044 70       		.byte	(.L782-.L781)/2
+ 11141 0045 78       		.byte	(.L779-.L781)/2
+ 11142 0046 78       		.byte	(.L779-.L781)/2
+ 11143 0047 78       		.byte	(.L779-.L781)/2
+ 11144 0048 74       		.byte	(.L780-.L781)/2
+ 11145 0049 00       		.p2align 1
+ 11146              	.L775:
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11147              		.loc 1 1479 7 is_stmt 0 discriminator 4 view .LVU3490
+ 11148 004a 90F83F30 		ldrb	r3, [r0, #63]	@ zero_extendqisi2
+ 11149 004e DBB2     		uxtb	r3, r3
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11150              		.loc 1 1479 44 discriminator 4 view .LVU3491
+ 11151 0050 013B     		subs	r3, r3, #1
+ 11152 0052 18BF     		it	ne
+ 11153 0054 0123     		movne	r3, #1
+ 11154 0056 E8E7     		b	.L777
+ 11155              	.L774:
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11156              		.loc 1 1479 7 discriminator 7 view .LVU3492
+ 11157 0058 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 11158 005c DBB2     		uxtb	r3, r3
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11159              		.loc 1 1479 44 discriminator 7 view .LVU3493
+ 11160 005e 013B     		subs	r3, r3, #1
+ 11161 0060 18BF     		it	ne
+ 11162 0062 0123     		movne	r3, #1
+ 11163 0064 E1E7     		b	.L777
+ 11164              	.L773:
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11165              		.loc 1 1479 7 discriminator 10 view .LVU3494
+ 11166 0066 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 11167 006a DBB2     		uxtb	r3, r3
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11168              		.loc 1 1479 44 discriminator 10 view .LVU3495
+ 11169 006c 013B     		subs	r3, r3, #1
+ 11170 006e 18BF     		it	ne
+ 11171 0070 0123     		movne	r3, #1
+ 11172 0072 DAE7     		b	.L777
+ 11173              	.L771:
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11174              		.loc 1 1479 7 discriminator 13 view .LVU3496
+ 11175 0074 90F84230 		ldrb	r3, [r0, #66]	@ zero_extendqisi2
+ARM GAS  /tmp/cc0wMqvE.s 			page 388
+
+
+ 11176 0078 DBB2     		uxtb	r3, r3
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11177              		.loc 1 1479 44 discriminator 13 view .LVU3497
+ 11178 007a 013B     		subs	r3, r3, #1
+ 11179 007c 18BF     		it	ne
+ 11180 007e 0123     		movne	r3, #1
+ 11181 0080 D3E7     		b	.L777
+ 11182              	.L770:
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11183              		.loc 1 1479 7 discriminator 14 view .LVU3498
+ 11184 0082 90F84330 		ldrb	r3, [r0, #67]	@ zero_extendqisi2
+ 11185 0086 DBB2     		uxtb	r3, r3
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11186              		.loc 1 1479 44 discriminator 14 view .LVU3499
+ 11187 0088 013B     		subs	r3, r3, #1
+ 11188 008a 18BF     		it	ne
+ 11189 008c 0123     		movne	r3, #1
+ 11190 008e CCE7     		b	.L777
+ 11191              	.L785:
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11192              		.loc 1 1485 3 discriminator 1 view .LVU3500
+ 11193 0090 0223     		movs	r3, #2
+ 11194 0092 84F83E30 		strb	r3, [r4, #62]
+ 11195              	.L786:
+1488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11196              		.loc 1 1488 3 is_stmt 1 view .LVU3501
+ 11197 0096 0122     		movs	r2, #1
+ 11198 0098 2068     		ldr	r0, [r4]
+ 11199              	.LVL880:
+1488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11200              		.loc 1 1488 3 is_stmt 0 view .LVU3502
+ 11201 009a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 11202              	.LVL881:
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11203              		.loc 1 1490 3 is_stmt 1 view .LVU3503
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11204              		.loc 1 1490 7 is_stmt 0 view .LVU3504
+ 11205 009e 2368     		ldr	r3, [r4]
+ 11206 00a0 2D4A     		ldr	r2, .L795
+ 11207 00a2 9342     		cmp	r3, r2
+ 11208 00a4 0FD0     		beq	.L787
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11209              		.loc 1 1490 7 discriminator 2 view .LVU3505
+ 11210 00a6 02F50062 		add	r2, r2, #2048
+ 11211 00aa 9342     		cmp	r3, r2
+ 11212 00ac 0BD0     		beq	.L787
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11213              		.loc 1 1490 7 discriminator 4 view .LVU3506
+ 11214 00ae 02F54062 		add	r2, r2, #3072
+ 11215 00b2 9342     		cmp	r3, r2
+ 11216 00b4 07D0     		beq	.L787
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11217              		.loc 1 1490 7 discriminator 6 view .LVU3507
+ 11218 00b6 02F58062 		add	r2, r2, #1024
+ 11219 00ba 9342     		cmp	r3, r2
+ 11220 00bc 03D0     		beq	.L787
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 389
+
+
+ 11221              		.loc 1 1490 7 discriminator 8 view .LVU3508
+ 11222 00be 02F58062 		add	r2, r2, #1024
+ 11223 00c2 9342     		cmp	r3, r2
+ 11224 00c4 03D1     		bne	.L788
+ 11225              	.L787:
+1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11226              		.loc 1 1493 5 is_stmt 1 view .LVU3509
+ 11227 00c6 5A6C     		ldr	r2, [r3, #68]
+ 11228 00c8 42F40042 		orr	r2, r2, #32768
+ 11229 00cc 5A64     		str	r2, [r3, #68]
+ 11230              	.L788:
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11231              		.loc 1 1497 3 view .LVU3510
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11232              		.loc 1 1497 7 is_stmt 0 view .LVU3511
+ 11233 00ce 2368     		ldr	r3, [r4]
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11234              		.loc 1 1497 6 view .LVU3512
+ 11235 00d0 214A     		ldr	r2, .L795
+ 11236 00d2 9342     		cmp	r3, r2
+ 11237 00d4 2CD0     		beq	.L789
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11238              		.loc 1 1497 7 discriminator 1 view .LVU3513
+ 11239 00d6 B3F1804F 		cmp	r3, #1073741824
+ 11240 00da 29D0     		beq	.L789
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11241              		.loc 1 1497 7 discriminator 2 view .LVU3514
+ 11242 00dc A2F59432 		sub	r2, r2, #75776
+ 11243 00e0 9342     		cmp	r3, r2
+ 11244 00e2 25D0     		beq	.L789
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11245              		.loc 1 1497 7 discriminator 3 view .LVU3515
+ 11246 00e4 02F58062 		add	r2, r2, #1024
+ 11247 00e8 9342     		cmp	r3, r2
+ 11248 00ea 21D0     		beq	.L789
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11249              		.loc 1 1497 7 discriminator 4 view .LVU3516
+ 11250 00ec 02F59632 		add	r2, r2, #76800
+ 11251 00f0 9342     		cmp	r3, r2
+ 11252 00f2 1DD0     		beq	.L789
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11253              		.loc 1 1497 7 discriminator 5 view .LVU3517
+ 11254 00f4 02F54062 		add	r2, r2, #3072
+ 11255 00f8 9342     		cmp	r3, r2
+ 11256 00fa 19D0     		beq	.L789
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11257              		.loc 1 1507 5 is_stmt 1 view .LVU3518
+ 11258 00fc 1A68     		ldr	r2, [r3]
+ 11259 00fe 42F00102 		orr	r2, r2, #1
+ 11260 0102 1A60     		str	r2, [r3]
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 11261              		.loc 1 1511 10 is_stmt 0 view .LVU3519
+ 11262 0104 0020     		movs	r0, #0
+ 11263 0106 22E0     		b	.L778
+ 11264              	.LVL882:
+ 11265              	.L784:
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 390
+
+
+ 11266              		.loc 1 1485 3 discriminator 3 view .LVU3520
+ 11267 0108 0223     		movs	r3, #2
+ 11268 010a 84F83F30 		strb	r3, [r4, #63]
+ 11269 010e C2E7     		b	.L786
+ 11270              	.L783:
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11271              		.loc 1 1485 3 discriminator 6 view .LVU3521
+ 11272 0110 0223     		movs	r3, #2
+ 11273 0112 84F84030 		strb	r3, [r4, #64]
+ 11274 0116 BEE7     		b	.L786
+ 11275              	.L782:
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11276              		.loc 1 1485 3 discriminator 9 view .LVU3522
+ 11277 0118 0223     		movs	r3, #2
+ 11278 011a 84F84130 		strb	r3, [r4, #65]
+ 11279 011e BAE7     		b	.L786
+ 11280              	.L780:
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11281              		.loc 1 1485 3 discriminator 12 view .LVU3523
+ 11282 0120 0223     		movs	r3, #2
+ 11283 0122 84F84230 		strb	r3, [r4, #66]
+ 11284 0126 B6E7     		b	.L786
+ 11285              	.L779:
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11286              		.loc 1 1485 3 discriminator 13 view .LVU3524
+ 11287 0128 0223     		movs	r3, #2
+ 11288 012a 84F84330 		strb	r3, [r4, #67]
+ 11289 012e B2E7     		b	.L786
+ 11290              	.LVL883:
+ 11291              	.L789:
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 11292              		.loc 1 1499 5 is_stmt 1 view .LVU3525
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 11293              		.loc 1 1499 29 is_stmt 0 view .LVU3526
+ 11294 0130 9968     		ldr	r1, [r3, #8]
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 11295              		.loc 1 1499 13 view .LVU3527
+ 11296 0132 0A4A     		ldr	r2, .L795+4
+ 11297 0134 0A40     		ands	r2, r2, r1
+ 11298              	.LVL884:
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11299              		.loc 1 1500 5 is_stmt 1 view .LVU3528
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11300              		.loc 1 1500 8 is_stmt 0 view .LVU3529
+ 11301 0136 062A     		cmp	r2, #6
+ 11302 0138 0AD0     		beq	.L792
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11303              		.loc 1 1500 9 discriminator 1 view .LVU3530
+ 11304 013a B2F5803F 		cmp	r2, #65536
+ 11305 013e 09D0     		beq	.L793
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11306              		.loc 1 1502 7 is_stmt 1 view .LVU3531
+ 11307 0140 1A68     		ldr	r2, [r3]
+ 11308              	.LVL885:
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11309              		.loc 1 1502 7 is_stmt 0 view .LVU3532
+ 11310 0142 42F00102 		orr	r2, r2, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 391
+
+
+ 11311 0146 1A60     		str	r2, [r3]
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 11312              		.loc 1 1511 10 view .LVU3533
+ 11313 0148 0020     		movs	r0, #0
+ 11314 014a 00E0     		b	.L778
+ 11315              	.LVL886:
+ 11316              	.L791:
+1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11317              		.loc 1 1481 12 view .LVU3534
+ 11318 014c 0120     		movs	r0, #1
+ 11319              	.LVL887:
+ 11320              	.L778:
+1512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11321              		.loc 1 1512 1 view .LVU3535
+ 11322 014e 10BD     		pop	{r4, pc}
+ 11323              	.LVL888:
+ 11324              	.L792:
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 11325              		.loc 1 1511 10 view .LVU3536
+ 11326 0150 0020     		movs	r0, #0
+ 11327 0152 FCE7     		b	.L778
+ 11328              	.L793:
+ 11329 0154 0020     		movs	r0, #0
+ 11330 0156 FAE7     		b	.L778
+ 11331              	.L796:
+ 11332              		.align	2
+ 11333              	.L795:
+ 11334 0158 002C0140 		.word	1073818624
+ 11335 015c 07000100 		.word	65543
+ 11336              		.cfi_endproc
+ 11337              	.LFE353:
+ 11339              		.section	.text.HAL_TIM_PWM_Stop,"ax",%progbits
+ 11340              		.align	1
+ 11341              		.global	HAL_TIM_PWM_Stop
+ 11342              		.syntax unified
+ 11343              		.thumb
+ 11344              		.thumb_func
+ 11346              	HAL_TIM_PWM_Stop:
+ 11347              	.LVL889:
+ 11348              	.LFB354:
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 11349              		.loc 1 1528 1 is_stmt 1 view -0
+ 11350              		.cfi_startproc
+ 11351              		@ args = 0, pretend = 0, frame = 0
+ 11352              		@ frame_needed = 0, uses_anonymous_args = 0
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 11353              		.loc 1 1528 1 is_stmt 0 view .LVU3538
+ 11354 0000 38B5     		push	{r3, r4, r5, lr}
+ 11355              	.LCFI92:
+ 11356              		.cfi_def_cfa_offset 16
+ 11357              		.cfi_offset 3, -16
+ 11358              		.cfi_offset 4, -12
+ 11359              		.cfi_offset 5, -8
+ 11360              		.cfi_offset 14, -4
+ 11361 0002 0446     		mov	r4, r0
+ 11362 0004 0D46     		mov	r5, r1
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 392
+
+
+ 11363              		.loc 1 1530 3 is_stmt 1 view .LVU3539
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11364              		.loc 1 1533 3 view .LVU3540
+ 11365 0006 0022     		movs	r2, #0
+ 11366 0008 0068     		ldr	r0, [r0]
+ 11367              	.LVL890:
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11368              		.loc 1 1533 3 is_stmt 0 view .LVU3541
+ 11369 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 11370              	.LVL891:
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11371              		.loc 1 1535 3 is_stmt 1 view .LVU3542
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11372              		.loc 1 1535 7 is_stmt 0 view .LVU3543
+ 11373 000e 2368     		ldr	r3, [r4]
+ 11374 0010 2A4A     		ldr	r2, .L810
+ 11375 0012 9342     		cmp	r3, r2
+ 11376 0014 0FD0     		beq	.L798
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11377              		.loc 1 1535 7 discriminator 2 view .LVU3544
+ 11378 0016 02F50062 		add	r2, r2, #2048
+ 11379 001a 9342     		cmp	r3, r2
+ 11380 001c 0BD0     		beq	.L798
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11381              		.loc 1 1535 7 discriminator 4 view .LVU3545
+ 11382 001e 02F54062 		add	r2, r2, #3072
+ 11383 0022 9342     		cmp	r3, r2
+ 11384 0024 07D0     		beq	.L798
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11385              		.loc 1 1535 7 discriminator 6 view .LVU3546
+ 11386 0026 02F58062 		add	r2, r2, #1024
+ 11387 002a 9342     		cmp	r3, r2
+ 11388 002c 03D0     		beq	.L798
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11389              		.loc 1 1535 7 discriminator 8 view .LVU3547
+ 11390 002e 02F58062 		add	r2, r2, #1024
+ 11391 0032 9342     		cmp	r3, r2
+ 11392 0034 0DD1     		bne	.L799
+ 11393              	.L798:
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11394              		.loc 1 1538 5 is_stmt 1 view .LVU3548
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11395              		.loc 1 1538 5 view .LVU3549
+ 11396 0036 196A     		ldr	r1, [r3, #32]
+ 11397 0038 41F21112 		movw	r2, #4369
+ 11398 003c 1142     		tst	r1, r2
+ 11399 003e 08D1     		bne	.L799
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11400              		.loc 1 1538 5 discriminator 1 view .LVU3550
+ 11401 0040 196A     		ldr	r1, [r3, #32]
+ 11402 0042 44F24442 		movw	r2, #17476
+ 11403 0046 1142     		tst	r1, r2
+ 11404 0048 03D1     		bne	.L799
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11405              		.loc 1 1538 5 discriminator 3 view .LVU3551
+ 11406 004a 5A6C     		ldr	r2, [r3, #68]
+ 11407 004c 22F40042 		bic	r2, r2, #32768
+ARM GAS  /tmp/cc0wMqvE.s 			page 393
+
+
+ 11408 0050 5A64     		str	r2, [r3, #68]
+ 11409              	.L799:
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11410              		.loc 1 1538 5 discriminator 5 view .LVU3552
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11411              		.loc 1 1542 3 discriminator 5 view .LVU3553
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11412              		.loc 1 1542 3 discriminator 5 view .LVU3554
+ 11413 0052 2368     		ldr	r3, [r4]
+ 11414 0054 196A     		ldr	r1, [r3, #32]
+ 11415 0056 41F21112 		movw	r2, #4369
+ 11416 005a 1142     		tst	r1, r2
+ 11417 005c 08D1     		bne	.L800
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11418              		.loc 1 1542 3 discriminator 1 view .LVU3555
+ 11419 005e 196A     		ldr	r1, [r3, #32]
+ 11420 0060 44F24442 		movw	r2, #17476
+ 11421 0064 1142     		tst	r1, r2
+ 11422 0066 03D1     		bne	.L800
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11423              		.loc 1 1542 3 discriminator 3 view .LVU3556
+ 11424 0068 1A68     		ldr	r2, [r3]
+ 11425 006a 22F00102 		bic	r2, r2, #1
+ 11426 006e 1A60     		str	r2, [r3]
+ 11427              	.L800:
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11428              		.loc 1 1542 3 discriminator 5 view .LVU3557
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11429              		.loc 1 1545 3 discriminator 5 view .LVU3558
+ 11430 0070 25B9     		cbnz	r5, .L801
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11431              		.loc 1 1545 3 is_stmt 0 discriminator 1 view .LVU3559
+ 11432 0072 0123     		movs	r3, #1
+ 11433 0074 84F83E30 		strb	r3, [r4, #62]
+ 11434              	.LVL892:
+ 11435              	.L802:
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 11436              		.loc 1 1548 3 is_stmt 1 view .LVU3560
+1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11437              		.loc 1 1549 1 is_stmt 0 view .LVU3561
+ 11438 0078 0020     		movs	r0, #0
+ 11439 007a 38BD     		pop	{r3, r4, r5, pc}
+ 11440              	.LVL893:
+ 11441              	.L801:
+1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11442              		.loc 1 1549 1 view .LVU3562
+ 11443 007c 043D     		subs	r5, r5, #4
+ 11444              	.LVL894:
+1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11445              		.loc 1 1549 1 view .LVU3563
+ 11446 007e 0C2D     		cmp	r5, #12
+ 11447 0080 18D8     		bhi	.L803
+ 11448 0082 DFE805F0 		tbb	[pc, r5]
+ 11449              	.L805:
+ 11450 0086 07       		.byte	(.L808-.L805)/2
+ 11451 0087 17       		.byte	(.L803-.L805)/2
+ 11452 0088 17       		.byte	(.L803-.L805)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 394
+
+
+ 11453 0089 17       		.byte	(.L803-.L805)/2
+ 11454 008a 0B       		.byte	(.L807-.L805)/2
+ 11455 008b 17       		.byte	(.L803-.L805)/2
+ 11456 008c 17       		.byte	(.L803-.L805)/2
+ 11457 008d 17       		.byte	(.L803-.L805)/2
+ 11458 008e 0F       		.byte	(.L806-.L805)/2
+ 11459 008f 17       		.byte	(.L803-.L805)/2
+ 11460 0090 17       		.byte	(.L803-.L805)/2
+ 11461 0091 17       		.byte	(.L803-.L805)/2
+ 11462 0092 13       		.byte	(.L804-.L805)/2
+ 11463 0093 00       		.p2align 1
+ 11464              	.L808:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11465              		.loc 1 1545 3 discriminator 3 view .LVU3564
+ 11466 0094 0123     		movs	r3, #1
+ 11467 0096 84F83F30 		strb	r3, [r4, #63]
+ 11468 009a EDE7     		b	.L802
+ 11469              	.L807:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11470              		.loc 1 1545 3 discriminator 6 view .LVU3565
+ 11471 009c 0123     		movs	r3, #1
+ 11472 009e 84F84030 		strb	r3, [r4, #64]
+ 11473 00a2 E9E7     		b	.L802
+ 11474              	.L806:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11475              		.loc 1 1545 3 discriminator 9 view .LVU3566
+ 11476 00a4 0123     		movs	r3, #1
+ 11477 00a6 84F84130 		strb	r3, [r4, #65]
+ 11478 00aa E5E7     		b	.L802
+ 11479              	.L804:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11480              		.loc 1 1545 3 discriminator 12 view .LVU3567
+ 11481 00ac 0123     		movs	r3, #1
+ 11482 00ae 84F84230 		strb	r3, [r4, #66]
+ 11483 00b2 E1E7     		b	.L802
+ 11484              	.L803:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11485              		.loc 1 1545 3 discriminator 13 view .LVU3568
+ 11486 00b4 0123     		movs	r3, #1
+ 11487 00b6 84F84330 		strb	r3, [r4, #67]
+ 11488 00ba DDE7     		b	.L802
+ 11489              	.L811:
+ 11490              		.align	2
+ 11491              	.L810:
+ 11492 00bc 002C0140 		.word	1073818624
+ 11493              		.cfi_endproc
+ 11494              	.LFE354:
+ 11496              		.section	.text.HAL_TIM_PWM_Start_IT,"ax",%progbits
+ 11497              		.align	1
+ 11498              		.global	HAL_TIM_PWM_Start_IT
+ 11499              		.syntax unified
+ 11500              		.thumb
+ 11501              		.thumb_func
+ 11503              	HAL_TIM_PWM_Start_IT:
+ 11504              	.LVL895:
+ 11505              	.LFB355:
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ARM GAS  /tmp/cc0wMqvE.s 			page 395
+
+
+ 11506              		.loc 1 1563 1 is_stmt 1 view -0
+ 11507              		.cfi_startproc
+ 11508              		@ args = 0, pretend = 0, frame = 0
+ 11509              		@ frame_needed = 0, uses_anonymous_args = 0
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 11510              		.loc 1 1563 1 is_stmt 0 view .LVU3570
+ 11511 0000 10B5     		push	{r4, lr}
+ 11512              	.LCFI93:
+ 11513              		.cfi_def_cfa_offset 8
+ 11514              		.cfi_offset 4, -8
+ 11515              		.cfi_offset 14, -4
+ 11516 0002 0446     		mov	r4, r0
+1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 11517              		.loc 1 1564 3 is_stmt 1 view .LVU3571
+ 11518              	.LVL896:
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11519              		.loc 1 1565 3 view .LVU3572
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11520              		.loc 1 1568 3 view .LVU3573
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11521              		.loc 1 1571 3 view .LVU3574
+ 11522 0004 1029     		cmp	r1, #16
+ 11523 0006 3DD8     		bhi	.L813
+ 11524 0008 DFE801F0 		tbb	[pc, r1]
+ 11525              	.L815:
+ 11526 000c 09       		.byte	(.L819-.L815)/2
+ 11527 000d 3C       		.byte	(.L813-.L815)/2
+ 11528 000e 3C       		.byte	(.L813-.L815)/2
+ 11529 000f 3C       		.byte	(.L813-.L815)/2
+ 11530 0010 20       		.byte	(.L818-.L815)/2
+ 11531 0011 3C       		.byte	(.L813-.L815)/2
+ 11532 0012 3C       		.byte	(.L813-.L815)/2
+ 11533 0013 3C       		.byte	(.L813-.L815)/2
+ 11534 0014 27       		.byte	(.L817-.L815)/2
+ 11535 0015 3C       		.byte	(.L813-.L815)/2
+ 11536 0016 3C       		.byte	(.L813-.L815)/2
+ 11537 0017 3C       		.byte	(.L813-.L815)/2
+ 11538 0018 2E       		.byte	(.L816-.L815)/2
+ 11539 0019 3C       		.byte	(.L813-.L815)/2
+ 11540 001a 3C       		.byte	(.L813-.L815)/2
+ 11541 001b 3C       		.byte	(.L813-.L815)/2
+ 11542 001c 35       		.byte	(.L814-.L815)/2
+ 11543 001d 00       		.p2align 1
+ 11544              	.L819:
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11545              		.loc 1 1571 7 is_stmt 0 discriminator 1 view .LVU3575
+ 11546 001e 90F83E30 		ldrb	r3, [r0, #62]	@ zero_extendqisi2
+ 11547 0022 DBB2     		uxtb	r3, r3
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11548              		.loc 1 1571 44 discriminator 1 view .LVU3576
+ 11549 0024 013B     		subs	r3, r3, #1
+ 11550 0026 18BF     		it	ne
+ 11551 0028 0123     		movne	r3, #1
+ 11552              	.L820:
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11553              		.loc 1 1571 6 discriminator 20 view .LVU3577
+ 11554 002a 002B     		cmp	r3, #0
+ARM GAS  /tmp/cc0wMqvE.s 			page 396
+
+
+ 11555 002c 40F0C280 		bne	.L839
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11556              		.loc 1 1577 3 is_stmt 1 view .LVU3578
+ 11557 0030 1029     		cmp	r1, #16
+ 11558 0032 00F28F80 		bhi	.L822
+ 11559 0036 DFE801F0 		tbb	[pc, r1]
+ 11560              	.L824:
+ 11561 003a 2C       		.byte	(.L828-.L824)/2
+ 11562 003b 8D       		.byte	(.L822-.L824)/2
+ 11563 003c 8D       		.byte	(.L822-.L824)/2
+ 11564 003d 8D       		.byte	(.L822-.L824)/2
+ 11565 003e 6D       		.byte	(.L827-.L824)/2
+ 11566 003f 8D       		.byte	(.L822-.L824)/2
+ 11567 0040 8D       		.byte	(.L822-.L824)/2
+ 11568 0041 8D       		.byte	(.L822-.L824)/2
+ 11569 0042 76       		.byte	(.L826-.L824)/2
+ 11570 0043 8D       		.byte	(.L822-.L824)/2
+ 11571 0044 8D       		.byte	(.L822-.L824)/2
+ 11572 0045 8D       		.byte	(.L822-.L824)/2
+ 11573 0046 7F       		.byte	(.L825-.L824)/2
+ 11574 0047 8D       		.byte	(.L822-.L824)/2
+ 11575 0048 8D       		.byte	(.L822-.L824)/2
+ 11576 0049 8D       		.byte	(.L822-.L824)/2
+ 11577 004a 88       		.byte	(.L823-.L824)/2
+ 11578 004b 00       		.p2align 1
+ 11579              	.L818:
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11580              		.loc 1 1571 7 is_stmt 0 discriminator 4 view .LVU3579
+ 11581 004c 90F83F30 		ldrb	r3, [r0, #63]	@ zero_extendqisi2
+ 11582 0050 DBB2     		uxtb	r3, r3
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11583              		.loc 1 1571 44 discriminator 4 view .LVU3580
+ 11584 0052 013B     		subs	r3, r3, #1
+ 11585 0054 18BF     		it	ne
+ 11586 0056 0123     		movne	r3, #1
+ 11587 0058 E7E7     		b	.L820
+ 11588              	.L817:
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11589              		.loc 1 1571 7 discriminator 7 view .LVU3581
+ 11590 005a 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 11591 005e DBB2     		uxtb	r3, r3
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11592              		.loc 1 1571 44 discriminator 7 view .LVU3582
+ 11593 0060 013B     		subs	r3, r3, #1
+ 11594 0062 18BF     		it	ne
+ 11595 0064 0123     		movne	r3, #1
+ 11596 0066 E0E7     		b	.L820
+ 11597              	.L816:
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11598              		.loc 1 1571 7 discriminator 10 view .LVU3583
+ 11599 0068 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 11600 006c DBB2     		uxtb	r3, r3
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11601              		.loc 1 1571 44 discriminator 10 view .LVU3584
+ 11602 006e 013B     		subs	r3, r3, #1
+ 11603 0070 18BF     		it	ne
+ 11604 0072 0123     		movne	r3, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 397
+
+
+ 11605 0074 D9E7     		b	.L820
+ 11606              	.L814:
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11607              		.loc 1 1571 7 discriminator 13 view .LVU3585
+ 11608 0076 90F84230 		ldrb	r3, [r0, #66]	@ zero_extendqisi2
+ 11609 007a DBB2     		uxtb	r3, r3
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11610              		.loc 1 1571 44 discriminator 13 view .LVU3586
+ 11611 007c 013B     		subs	r3, r3, #1
+ 11612 007e 18BF     		it	ne
+ 11613 0080 0123     		movne	r3, #1
+ 11614 0082 D2E7     		b	.L820
+ 11615              	.L813:
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11616              		.loc 1 1571 7 discriminator 14 view .LVU3587
+ 11617 0084 90F84330 		ldrb	r3, [r0, #67]	@ zero_extendqisi2
+ 11618 0088 DBB2     		uxtb	r3, r3
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11619              		.loc 1 1571 44 discriminator 14 view .LVU3588
+ 11620 008a 013B     		subs	r3, r3, #1
+ 11621 008c 18BF     		it	ne
+ 11622 008e 0123     		movne	r3, #1
+ 11623 0090 CBE7     		b	.L820
+ 11624              	.L828:
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11625              		.loc 1 1577 3 view .LVU3589
+ 11626 0092 0223     		movs	r3, #2
+ 11627 0094 84F83E30 		strb	r3, [r4, #62]
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11628              		.loc 1 1579 3 is_stmt 1 view .LVU3590
+ 11629              	.L829:
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 11630              		.loc 1 1584 7 view .LVU3591
+ 11631 0098 2268     		ldr	r2, [r4]
+ 11632 009a D368     		ldr	r3, [r2, #12]
+ 11633 009c 43F00203 		orr	r3, r3, #2
+ 11634 00a0 D360     		str	r3, [r2, #12]
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11635              		.loc 1 1585 7 view .LVU3592
+1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11636              		.loc 1 1614 3 view .LVU3593
+ 11637              	.L834:
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11638              		.loc 1 1617 5 view .LVU3594
+ 11639 00a2 0122     		movs	r2, #1
+ 11640 00a4 2068     		ldr	r0, [r4]
+ 11641              	.LVL897:
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11642              		.loc 1 1617 5 is_stmt 0 view .LVU3595
+ 11643 00a6 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 11644              	.LVL898:
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11645              		.loc 1 1619 5 is_stmt 1 view .LVU3596
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11646              		.loc 1 1619 9 is_stmt 0 view .LVU3597
+ 11647 00aa 2368     		ldr	r3, [r4]
+ 11648 00ac 454A     		ldr	r2, .L848
+ARM GAS  /tmp/cc0wMqvE.s 			page 398
+
+
+ 11649 00ae 9342     		cmp	r3, r2
+ 11650 00b0 0FD0     		beq	.L835
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11651              		.loc 1 1619 9 discriminator 2 view .LVU3598
+ 11652 00b2 02F50062 		add	r2, r2, #2048
+ 11653 00b6 9342     		cmp	r3, r2
+ 11654 00b8 0BD0     		beq	.L835
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11655              		.loc 1 1619 9 discriminator 4 view .LVU3599
+ 11656 00ba 02F54062 		add	r2, r2, #3072
+ 11657 00be 9342     		cmp	r3, r2
+ 11658 00c0 07D0     		beq	.L835
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11659              		.loc 1 1619 9 discriminator 6 view .LVU3600
+ 11660 00c2 02F58062 		add	r2, r2, #1024
+ 11661 00c6 9342     		cmp	r3, r2
+ 11662 00c8 03D0     		beq	.L835
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11663              		.loc 1 1619 9 discriminator 8 view .LVU3601
+ 11664 00ca 02F58062 		add	r2, r2, #1024
+ 11665 00ce 9342     		cmp	r3, r2
+ 11666 00d0 03D1     		bne	.L836
+ 11667              	.L835:
+1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11668              		.loc 1 1622 7 is_stmt 1 view .LVU3602
+ 11669 00d2 5A6C     		ldr	r2, [r3, #68]
+ 11670 00d4 42F40042 		orr	r2, r2, #32768
+ 11671 00d8 5A64     		str	r2, [r3, #68]
+ 11672              	.L836:
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11673              		.loc 1 1626 5 view .LVU3603
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11674              		.loc 1 1626 9 is_stmt 0 view .LVU3604
+ 11675 00da 2368     		ldr	r3, [r4]
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11676              		.loc 1 1626 8 view .LVU3605
+ 11677 00dc 394A     		ldr	r2, .L848
+ 11678 00de 9342     		cmp	r3, r2
+ 11679 00e0 5AD0     		beq	.L837
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11680              		.loc 1 1626 9 discriminator 1 view .LVU3606
+ 11681 00e2 B3F1804F 		cmp	r3, #1073741824
+ 11682 00e6 57D0     		beq	.L837
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11683              		.loc 1 1626 9 discriminator 2 view .LVU3607
+ 11684 00e8 A2F59432 		sub	r2, r2, #75776
+ 11685 00ec 9342     		cmp	r3, r2
+ 11686 00ee 53D0     		beq	.L837
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11687              		.loc 1 1626 9 discriminator 3 view .LVU3608
+ 11688 00f0 02F58062 		add	r2, r2, #1024
+ 11689 00f4 9342     		cmp	r3, r2
+ 11690 00f6 4FD0     		beq	.L837
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11691              		.loc 1 1626 9 discriminator 4 view .LVU3609
+ 11692 00f8 02F59632 		add	r2, r2, #76800
+ 11693 00fc 9342     		cmp	r3, r2
+ARM GAS  /tmp/cc0wMqvE.s 			page 399
+
+
+ 11694 00fe 4BD0     		beq	.L837
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11695              		.loc 1 1626 9 discriminator 5 view .LVU3610
+ 11696 0100 02F54062 		add	r2, r2, #3072
+ 11697 0104 9342     		cmp	r3, r2
+ 11698 0106 47D0     		beq	.L837
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11699              		.loc 1 1636 7 is_stmt 1 view .LVU3611
+ 11700 0108 1A68     		ldr	r2, [r3]
+ 11701 010a 42F00102 		orr	r2, r2, #1
+ 11702 010e 1A60     		str	r2, [r3]
+ 11703 0110 0020     		movs	r0, #0
+ 11704 0112 50E0     		b	.L821
+ 11705              	.LVL899:
+ 11706              	.L827:
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11707              		.loc 1 1577 3 is_stmt 0 view .LVU3612
+ 11708 0114 0223     		movs	r3, #2
+ 11709 0116 84F83F30 		strb	r3, [r4, #63]
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11710              		.loc 1 1579 3 is_stmt 1 view .LVU3613
+ 11711              	.L830:
+1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 11712              		.loc 1 1591 7 view .LVU3614
+ 11713 011a 2268     		ldr	r2, [r4]
+ 11714 011c D368     		ldr	r3, [r2, #12]
+ 11715 011e 43F00403 		orr	r3, r3, #4
+ 11716 0122 D360     		str	r3, [r2, #12]
+1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11717              		.loc 1 1592 7 view .LVU3615
+1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11718              		.loc 1 1614 3 view .LVU3616
+ 11719 0124 BDE7     		b	.L834
+ 11720              	.L826:
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11721              		.loc 1 1577 3 is_stmt 0 view .LVU3617
+ 11722 0126 0223     		movs	r3, #2
+ 11723 0128 84F84030 		strb	r3, [r4, #64]
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11724              		.loc 1 1579 3 is_stmt 1 view .LVU3618
+ 11725              	.L831:
+1598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 11726              		.loc 1 1598 7 view .LVU3619
+ 11727 012c 2268     		ldr	r2, [r4]
+ 11728 012e D368     		ldr	r3, [r2, #12]
+ 11729 0130 43F00803 		orr	r3, r3, #8
+ 11730 0134 D360     		str	r3, [r2, #12]
+1599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11731              		.loc 1 1599 7 view .LVU3620
+1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11732              		.loc 1 1614 3 view .LVU3621
+ 11733 0136 B4E7     		b	.L834
+ 11734              	.L825:
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11735              		.loc 1 1577 3 is_stmt 0 view .LVU3622
+ 11736 0138 0223     		movs	r3, #2
+ 11737 013a 84F84130 		strb	r3, [r4, #65]
+ARM GAS  /tmp/cc0wMqvE.s 			page 400
+
+
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11738              		.loc 1 1579 3 is_stmt 1 view .LVU3623
+ 11739              	.L832:
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 11740              		.loc 1 1605 7 view .LVU3624
+ 11741 013e 2268     		ldr	r2, [r4]
+ 11742 0140 D368     		ldr	r3, [r2, #12]
+ 11743 0142 43F01003 		orr	r3, r3, #16
+ 11744 0146 D360     		str	r3, [r2, #12]
+1606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11745              		.loc 1 1606 7 view .LVU3625
+1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11746              		.loc 1 1614 3 view .LVU3626
+ 11747 0148 ABE7     		b	.L834
+ 11748              	.L823:
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11749              		.loc 1 1577 3 is_stmt 0 view .LVU3627
+ 11750 014a 0223     		movs	r3, #2
+ 11751 014c 84F84230 		strb	r3, [r4, #66]
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11752              		.loc 1 1579 3 is_stmt 1 view .LVU3628
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11753              		.loc 1 1577 3 is_stmt 0 view .LVU3629
+ 11754 0150 0120     		movs	r0, #1
+ 11755              	.LVL900:
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11756              		.loc 1 1577 3 view .LVU3630
+ 11757 0152 30E0     		b	.L821
+ 11758              	.LVL901:
+ 11759              	.L822:
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11760              		.loc 1 1577 3 discriminator 13 view .LVU3631
+ 11761 0154 0223     		movs	r3, #2
+ 11762 0156 84F84330 		strb	r3, [r4, #67]
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11763              		.loc 1 1579 3 is_stmt 1 discriminator 13 view .LVU3632
+ 11764 015a 0C29     		cmp	r1, #12
+ 11765 015c 2CD8     		bhi	.L840
+ 11766 015e 01A3     		adr	r3, .L833
+ 11767 0160 53F821F0 		ldr	pc, [r3, r1, lsl #2]
+ 11768              		.p2align 2
+ 11769              	.L833:
+ 11770 0164 99000000 		.word	.L829+1
+ 11771 0168 B9010000 		.word	.L840+1
+ 11772 016c B9010000 		.word	.L840+1
+ 11773 0170 B9010000 		.word	.L840+1
+ 11774 0174 1B010000 		.word	.L830+1
+ 11775 0178 B9010000 		.word	.L840+1
+ 11776 017c B9010000 		.word	.L840+1
+ 11777 0180 B9010000 		.word	.L840+1
+ 11778 0184 2D010000 		.word	.L831+1
+ 11779 0188 B9010000 		.word	.L840+1
+ 11780 018c B9010000 		.word	.L840+1
+ 11781 0190 B9010000 		.word	.L840+1
+ 11782 0194 3F010000 		.word	.L832+1
+ 11783              	.LVL902:
+ 11784              		.p2align 1
+ARM GAS  /tmp/cc0wMqvE.s 			page 401
+
+
+ 11785              	.L837:
+1628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 11786              		.loc 1 1628 7 view .LVU3633
+1628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 11787              		.loc 1 1628 31 is_stmt 0 view .LVU3634
+ 11788 0198 9968     		ldr	r1, [r3, #8]
+1628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 11789              		.loc 1 1628 15 view .LVU3635
+ 11790 019a 0B4A     		ldr	r2, .L848+4
+ 11791 019c 0A40     		ands	r2, r2, r1
+ 11792              	.LVL903:
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 11793              		.loc 1 1629 7 is_stmt 1 view .LVU3636
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 11794              		.loc 1 1629 10 is_stmt 0 view .LVU3637
+ 11795 019e 062A     		cmp	r2, #6
+ 11796 01a0 0CD0     		beq	.L841
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 11797              		.loc 1 1629 11 discriminator 1 view .LVU3638
+ 11798 01a2 B2F5803F 		cmp	r2, #65536
+ 11799 01a6 0BD0     		beq	.L842
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 11800              		.loc 1 1631 9 is_stmt 1 view .LVU3639
+ 11801 01a8 1A68     		ldr	r2, [r3]
+ 11802              	.LVL904:
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 11803              		.loc 1 1631 9 is_stmt 0 view .LVU3640
+ 11804 01aa 42F00102 		orr	r2, r2, #1
+ 11805 01ae 1A60     		str	r2, [r3]
+ 11806 01b0 0020     		movs	r0, #0
+ 11807 01b2 00E0     		b	.L821
+ 11808              	.LVL905:
+ 11809              	.L839:
+1573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11810              		.loc 1 1573 12 view .LVU3641
+ 11811 01b4 0120     		movs	r0, #1
+ 11812              	.LVL906:
+ 11813              	.L821:
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11814              		.loc 1 1642 1 view .LVU3642
+ 11815 01b6 10BD     		pop	{r4, pc}
+ 11816              	.LVL907:
+ 11817              	.L840:
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11818              		.loc 1 1579 3 view .LVU3643
+ 11819 01b8 0120     		movs	r0, #1
+ 11820              	.LVL908:
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11821              		.loc 1 1579 3 view .LVU3644
+ 11822 01ba FCE7     		b	.L821
+ 11823              	.LVL909:
+ 11824              	.L841:
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11825              		.loc 1 1579 3 view .LVU3645
+ 11826 01bc 0020     		movs	r0, #0
+ 11827 01be FAE7     		b	.L821
+ 11828              	.L842:
+ARM GAS  /tmp/cc0wMqvE.s 			page 402
+
+
+ 11829 01c0 0020     		movs	r0, #0
+ 11830 01c2 F8E7     		b	.L821
+ 11831              	.L849:
+ 11832              		.align	2
+ 11833              	.L848:
+ 11834 01c4 002C0140 		.word	1073818624
+ 11835 01c8 07000100 		.word	65543
+ 11836              		.cfi_endproc
+ 11837              	.LFE355:
+ 11839              		.section	.text.HAL_TIM_PWM_Stop_IT,"ax",%progbits
+ 11840              		.align	1
+ 11841              		.global	HAL_TIM_PWM_Stop_IT
+ 11842              		.syntax unified
+ 11843              		.thumb
+ 11844              		.thumb_func
+ 11846              	HAL_TIM_PWM_Stop_IT:
+ 11847              	.LVL910:
+ 11848              	.LFB356:
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 11849              		.loc 1 1656 1 is_stmt 1 view -0
+ 11850              		.cfi_startproc
+ 11851              		@ args = 0, pretend = 0, frame = 0
+ 11852              		@ frame_needed = 0, uses_anonymous_args = 0
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 11853              		.loc 1 1656 1 is_stmt 0 view .LVU3647
+ 11854 0000 38B5     		push	{r3, r4, r5, lr}
+ 11855              	.LCFI94:
+ 11856              		.cfi_def_cfa_offset 16
+ 11857              		.cfi_offset 3, -16
+ 11858              		.cfi_offset 4, -12
+ 11859              		.cfi_offset 5, -8
+ 11860              		.cfi_offset 14, -4
+ 11861 0002 0546     		mov	r5, r0
+ 11862 0004 0C46     		mov	r4, r1
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11863              		.loc 1 1657 3 is_stmt 1 view .LVU3648
+ 11864              	.LVL911:
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11865              		.loc 1 1660 3 view .LVU3649
+1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11866              		.loc 1 1662 3 view .LVU3650
+ 11867 0006 0C29     		cmp	r1, #12
+ 11868 0008 00F28180 		bhi	.L868
+ 11869 000c DFE801F0 		tbb	[pc, r1]
+ 11870              	.L853:
+ 11871 0010 07       		.byte	(.L856-.L853)/2
+ 11872 0011 7F       		.byte	(.L868-.L853)/2
+ 11873 0012 7F       		.byte	(.L868-.L853)/2
+ 11874 0013 7F       		.byte	(.L868-.L853)/2
+ 11875 0014 48       		.byte	(.L855-.L853)/2
+ 11876 0015 7F       		.byte	(.L868-.L853)/2
+ 11877 0016 7F       		.byte	(.L868-.L853)/2
+ 11878 0017 7F       		.byte	(.L868-.L853)/2
+ 11879 0018 4E       		.byte	(.L854-.L853)/2
+ 11880 0019 7F       		.byte	(.L868-.L853)/2
+ 11881 001a 7F       		.byte	(.L868-.L853)/2
+ 11882 001b 7F       		.byte	(.L868-.L853)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 403
+
+
+ 11883 001c 54       		.byte	(.L852-.L853)/2
+ 11884 001d 00       		.p2align 1
+ 11885              	.L856:
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 11886              		.loc 1 1667 7 view .LVU3651
+ 11887 001e 0268     		ldr	r2, [r0]
+ 11888 0020 D368     		ldr	r3, [r2, #12]
+ 11889 0022 23F00203 		bic	r3, r3, #2
+ 11890 0026 D360     		str	r3, [r2, #12]
+1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11891              		.loc 1 1668 7 view .LVU3652
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11892              		.loc 1 1697 3 view .LVU3653
+ 11893              	.L857:
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11894              		.loc 1 1700 5 view .LVU3654
+ 11895 0028 0022     		movs	r2, #0
+ 11896 002a 2146     		mov	r1, r4
+ 11897              	.LVL912:
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11898              		.loc 1 1700 5 is_stmt 0 view .LVU3655
+ 11899 002c 2868     		ldr	r0, [r5]
+ 11900              	.LVL913:
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11901              		.loc 1 1700 5 view .LVU3656
+ 11902 002e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 11903              	.LVL914:
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11904              		.loc 1 1702 5 is_stmt 1 view .LVU3657
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11905              		.loc 1 1702 9 is_stmt 0 view .LVU3658
+ 11906 0032 2B68     		ldr	r3, [r5]
+ 11907 0034 374A     		ldr	r2, .L870
+ 11908 0036 9342     		cmp	r3, r2
+ 11909 0038 0FD0     		beq	.L858
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11910              		.loc 1 1702 9 discriminator 2 view .LVU3659
+ 11911 003a 02F50062 		add	r2, r2, #2048
+ 11912 003e 9342     		cmp	r3, r2
+ 11913 0040 0BD0     		beq	.L858
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11914              		.loc 1 1702 9 discriminator 4 view .LVU3660
+ 11915 0042 02F54062 		add	r2, r2, #3072
+ 11916 0046 9342     		cmp	r3, r2
+ 11917 0048 07D0     		beq	.L858
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11918              		.loc 1 1702 9 discriminator 6 view .LVU3661
+ 11919 004a 02F58062 		add	r2, r2, #1024
+ 11920 004e 9342     		cmp	r3, r2
+ 11921 0050 03D0     		beq	.L858
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 11922              		.loc 1 1702 9 discriminator 8 view .LVU3662
+ 11923 0052 02F58062 		add	r2, r2, #1024
+ 11924 0056 9342     		cmp	r3, r2
+ 11925 0058 0DD1     		bne	.L859
+ 11926              	.L858:
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ARM GAS  /tmp/cc0wMqvE.s 			page 404
+
+
+ 11927              		.loc 1 1705 7 is_stmt 1 view .LVU3663
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11928              		.loc 1 1705 7 view .LVU3664
+ 11929 005a 196A     		ldr	r1, [r3, #32]
+ 11930 005c 41F21112 		movw	r2, #4369
+ 11931 0060 1142     		tst	r1, r2
+ 11932 0062 08D1     		bne	.L859
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11933              		.loc 1 1705 7 discriminator 1 view .LVU3665
+ 11934 0064 196A     		ldr	r1, [r3, #32]
+ 11935 0066 44F24442 		movw	r2, #17476
+ 11936 006a 1142     		tst	r1, r2
+ 11937 006c 03D1     		bne	.L859
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11938              		.loc 1 1705 7 discriminator 3 view .LVU3666
+ 11939 006e 5A6C     		ldr	r2, [r3, #68]
+ 11940 0070 22F40042 		bic	r2, r2, #32768
+ 11941 0074 5A64     		str	r2, [r3, #68]
+ 11942              	.L859:
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11943              		.loc 1 1705 7 discriminator 5 view .LVU3667
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11944              		.loc 1 1709 5 discriminator 5 view .LVU3668
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11945              		.loc 1 1709 5 discriminator 5 view .LVU3669
+ 11946 0076 2B68     		ldr	r3, [r5]
+ 11947 0078 196A     		ldr	r1, [r3, #32]
+ 11948 007a 41F21112 		movw	r2, #4369
+ 11949 007e 1142     		tst	r1, r2
+ 11950 0080 08D1     		bne	.L860
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11951              		.loc 1 1709 5 discriminator 1 view .LVU3670
+ 11952 0082 196A     		ldr	r1, [r3, #32]
+ 11953 0084 44F24442 		movw	r2, #17476
+ 11954 0088 1142     		tst	r1, r2
+ 11955 008a 03D1     		bne	.L860
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11956              		.loc 1 1709 5 discriminator 3 view .LVU3671
+ 11957 008c 1A68     		ldr	r2, [r3]
+ 11958 008e 22F00102 		bic	r2, r2, #1
+ 11959 0092 1A60     		str	r2, [r3]
+ 11960              	.L860:
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 11961              		.loc 1 1709 5 discriminator 5 view .LVU3672
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11962              		.loc 1 1712 5 discriminator 5 view .LVU3673
+ 11963 0094 B4B9     		cbnz	r4, .L861
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 11964              		.loc 1 1712 5 is_stmt 0 discriminator 1 view .LVU3674
+ 11965 0096 0123     		movs	r3, #1
+ 11966 0098 85F83E30 		strb	r3, [r5, #62]
+ 11967 009c 0020     		movs	r0, #0
+ 11968 009e 37E0     		b	.L851
+ 11969              	.LVL915:
+ 11970              	.L855:
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 11971              		.loc 1 1674 7 is_stmt 1 view .LVU3675
+ARM GAS  /tmp/cc0wMqvE.s 			page 405
+
+
+ 11972 00a0 0268     		ldr	r2, [r0]
+ 11973 00a2 D368     		ldr	r3, [r2, #12]
+ 11974 00a4 23F00403 		bic	r3, r3, #4
+ 11975 00a8 D360     		str	r3, [r2, #12]
+1675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11976              		.loc 1 1675 7 view .LVU3676
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11977              		.loc 1 1697 3 view .LVU3677
+ 11978 00aa BDE7     		b	.L857
+ 11979              	.L854:
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 11980              		.loc 1 1681 7 view .LVU3678
+ 11981 00ac 0268     		ldr	r2, [r0]
+ 11982 00ae D368     		ldr	r3, [r2, #12]
+ 11983 00b0 23F00803 		bic	r3, r3, #8
+ 11984 00b4 D360     		str	r3, [r2, #12]
+1682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11985              		.loc 1 1682 7 view .LVU3679
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11986              		.loc 1 1697 3 view .LVU3680
+ 11987 00b6 B7E7     		b	.L857
+ 11988              	.L852:
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 11989              		.loc 1 1688 7 view .LVU3681
+ 11990 00b8 0268     		ldr	r2, [r0]
+ 11991 00ba D368     		ldr	r3, [r2, #12]
+ 11992 00bc 23F01003 		bic	r3, r3, #16
+ 11993 00c0 D360     		str	r3, [r2, #12]
+1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 11994              		.loc 1 1689 7 view .LVU3682
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11995              		.loc 1 1697 3 view .LVU3683
+ 11996 00c2 B1E7     		b	.L857
+ 11997              	.LVL916:
+ 11998              	.L861:
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 11999              		.loc 1 1697 3 is_stmt 0 view .LVU3684
+ 12000 00c4 043C     		subs	r4, r4, #4
+ 12001              	.LVL917:
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12002              		.loc 1 1697 3 view .LVU3685
+ 12003 00c6 0C2C     		cmp	r4, #12
+ 12004 00c8 1CD8     		bhi	.L862
+ 12005 00ca DFE804F0 		tbb	[pc, r4]
+ 12006              	.L864:
+ 12007 00ce 07       		.byte	(.L867-.L864)/2
+ 12008 00cf 1B       		.byte	(.L862-.L864)/2
+ 12009 00d0 1B       		.byte	(.L862-.L864)/2
+ 12010 00d1 1B       		.byte	(.L862-.L864)/2
+ 12011 00d2 0C       		.byte	(.L866-.L864)/2
+ 12012 00d3 1B       		.byte	(.L862-.L864)/2
+ 12013 00d4 1B       		.byte	(.L862-.L864)/2
+ 12014 00d5 1B       		.byte	(.L862-.L864)/2
+ 12015 00d6 11       		.byte	(.L865-.L864)/2
+ 12016 00d7 1B       		.byte	(.L862-.L864)/2
+ 12017 00d8 1B       		.byte	(.L862-.L864)/2
+ 12018 00d9 1B       		.byte	(.L862-.L864)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 406
+
+
+ 12019 00da 16       		.byte	(.L863-.L864)/2
+ 12020 00db 00       		.p2align 1
+ 12021              	.L867:
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12022              		.loc 1 1712 5 discriminator 3 view .LVU3686
+ 12023 00dc 0123     		movs	r3, #1
+ 12024 00de 85F83F30 		strb	r3, [r5, #63]
+ 12025 00e2 0020     		movs	r0, #0
+ 12026 00e4 14E0     		b	.L851
+ 12027              	.L866:
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12028              		.loc 1 1712 5 discriminator 6 view .LVU3687
+ 12029 00e6 0123     		movs	r3, #1
+ 12030 00e8 85F84030 		strb	r3, [r5, #64]
+ 12031 00ec 0020     		movs	r0, #0
+ 12032 00ee 0FE0     		b	.L851
+ 12033              	.L865:
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12034              		.loc 1 1712 5 discriminator 9 view .LVU3688
+ 12035 00f0 0123     		movs	r3, #1
+ 12036 00f2 85F84130 		strb	r3, [r5, #65]
+ 12037 00f6 0020     		movs	r0, #0
+ 12038 00f8 0AE0     		b	.L851
+ 12039              	.L863:
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12040              		.loc 1 1712 5 discriminator 12 view .LVU3689
+ 12041 00fa 0123     		movs	r3, #1
+ 12042 00fc 85F84230 		strb	r3, [r5, #66]
+ 12043 0100 0020     		movs	r0, #0
+ 12044 0102 05E0     		b	.L851
+ 12045              	.L862:
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12046              		.loc 1 1712 5 discriminator 13 view .LVU3690
+ 12047 0104 0123     		movs	r3, #1
+ 12048 0106 85F84330 		strb	r3, [r5, #67]
+ 12049 010a 0020     		movs	r0, #0
+ 12050 010c 00E0     		b	.L851
+ 12051              	.LVL918:
+ 12052              	.L868:
+1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12053              		.loc 1 1662 3 view .LVU3691
+ 12054 010e 0120     		movs	r0, #1
+ 12055              	.LVL919:
+ 12056              	.L851:
+1716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 12057              		.loc 1 1716 3 is_stmt 1 view .LVU3692
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12058              		.loc 1 1717 1 is_stmt 0 view .LVU3693
+ 12059 0110 38BD     		pop	{r3, r4, r5, pc}
+ 12060              	.LVL920:
+ 12061              	.L871:
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12062              		.loc 1 1717 1 view .LVU3694
+ 12063 0112 00BF     		.align	2
+ 12064              	.L870:
+ 12065 0114 002C0140 		.word	1073818624
+ 12066              		.cfi_endproc
+ARM GAS  /tmp/cc0wMqvE.s 			page 407
+
+
+ 12067              	.LFE356:
+ 12069              		.section	.text.HAL_TIM_PWM_Start_DMA,"ax",%progbits
+ 12070              		.align	1
+ 12071              		.global	HAL_TIM_PWM_Start_DMA
+ 12072              		.syntax unified
+ 12073              		.thumb
+ 12074              		.thumb_func
+ 12076              	HAL_TIM_PWM_Start_DMA:
+ 12077              	.LVL921:
+ 12078              	.LFB357:
+1733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 12079              		.loc 1 1733 1 is_stmt 1 view -0
+ 12080              		.cfi_startproc
+ 12081              		@ args = 0, pretend = 0, frame = 0
+ 12082              		@ frame_needed = 0, uses_anonymous_args = 0
+1733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 12083              		.loc 1 1733 1 is_stmt 0 view .LVU3696
+ 12084 0000 38B5     		push	{r3, r4, r5, lr}
+ 12085              	.LCFI95:
+ 12086              		.cfi_def_cfa_offset 16
+ 12087              		.cfi_offset 3, -16
+ 12088              		.cfi_offset 4, -12
+ 12089              		.cfi_offset 5, -8
+ 12090              		.cfi_offset 14, -4
+ 12091 0002 0446     		mov	r4, r0
+ 12092 0004 0D46     		mov	r5, r1
+ 12093 0006 1146     		mov	r1, r2
+ 12094              	.LVL922:
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 12095              		.loc 1 1734 3 is_stmt 1 view .LVU3697
+1735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12096              		.loc 1 1735 3 view .LVU3698
+1738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12097              		.loc 1 1738 3 view .LVU3699
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12098              		.loc 1 1741 3 view .LVU3700
+ 12099 0008 102D     		cmp	r5, #16
+ 12100 000a 41D8     		bhi	.L873
+ 12101 000c DFE805F0 		tbb	[pc, r5]
+ 12102              	.LVL923:
+ 12103              	.L875:
+ 12104 0010 09       		.byte	(.L879-.L875)/2
+ 12105 0011 40       		.byte	(.L873-.L875)/2
+ 12106 0012 40       		.byte	(.L873-.L875)/2
+ 12107 0013 40       		.byte	(.L873-.L875)/2
+ 12108 0014 20       		.byte	(.L878-.L875)/2
+ 12109 0015 40       		.byte	(.L873-.L875)/2
+ 12110 0016 40       		.byte	(.L873-.L875)/2
+ 12111 0017 40       		.byte	(.L873-.L875)/2
+ 12112 0018 28       		.byte	(.L877-.L875)/2
+ 12113 0019 40       		.byte	(.L873-.L875)/2
+ 12114 001a 40       		.byte	(.L873-.L875)/2
+ 12115 001b 40       		.byte	(.L873-.L875)/2
+ 12116 001c 30       		.byte	(.L876-.L875)/2
+ 12117 001d 40       		.byte	(.L873-.L875)/2
+ 12118 001e 40       		.byte	(.L873-.L875)/2
+ 12119 001f 40       		.byte	(.L873-.L875)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 408
+
+
+ 12120 0020 38       		.byte	(.L874-.L875)/2
+ 12121 0021 00       		.p2align 1
+ 12122              	.L879:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12123              		.loc 1 1741 7 is_stmt 0 discriminator 1 view .LVU3701
+ 12124 0022 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 12125              	.LVL924:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12126              		.loc 1 1741 7 discriminator 1 view .LVU3702
+ 12127 0026 C0B2     		uxtb	r0, r0
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12128              		.loc 1 1741 44 discriminator 1 view .LVU3703
+ 12129 0028 0228     		cmp	r0, #2
+ 12130 002a 14BF     		ite	ne
+ 12131 002c 0020     		movne	r0, #0
+ 12132 002e 0120     		moveq	r0, #1
+ 12133              	.L880:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12134              		.loc 1 1741 6 discriminator 20 view .LVU3704
+ 12135 0030 0028     		cmp	r0, #0
+ 12136 0032 40F05981 		bne	.L908
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12137              		.loc 1 1745 8 is_stmt 1 view .LVU3705
+ 12138 0036 102D     		cmp	r5, #16
+ 12139 0038 74D8     		bhi	.L882
+ 12140 003a DFE805F0 		tbb	[pc, r5]
+ 12141              	.L884:
+ 12142 003e 31       		.byte	(.L888-.L884)/2
+ 12143 003f 73       		.byte	(.L882-.L884)/2
+ 12144 0040 73       		.byte	(.L882-.L884)/2
+ 12145 0041 73       		.byte	(.L882-.L884)/2
+ 12146 0042 53       		.byte	(.L887-.L884)/2
+ 12147 0043 73       		.byte	(.L882-.L884)/2
+ 12148 0044 73       		.byte	(.L882-.L884)/2
+ 12149 0045 73       		.byte	(.L882-.L884)/2
+ 12150 0046 5B       		.byte	(.L886-.L884)/2
+ 12151 0047 73       		.byte	(.L882-.L884)/2
+ 12152 0048 73       		.byte	(.L882-.L884)/2
+ 12153 0049 73       		.byte	(.L882-.L884)/2
+ 12154 004a 63       		.byte	(.L885-.L884)/2
+ 12155 004b 73       		.byte	(.L882-.L884)/2
+ 12156 004c 73       		.byte	(.L882-.L884)/2
+ 12157 004d 73       		.byte	(.L882-.L884)/2
+ 12158 004e 6B       		.byte	(.L883-.L884)/2
+ 12159              	.LVL925:
+ 12160 004f 00       		.p2align 1
+ 12161              	.L878:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12162              		.loc 1 1741 7 is_stmt 0 discriminator 4 view .LVU3706
+ 12163 0050 90F83F00 		ldrb	r0, [r0, #63]	@ zero_extendqisi2
+ 12164              	.LVL926:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12165              		.loc 1 1741 7 discriminator 4 view .LVU3707
+ 12166 0054 C0B2     		uxtb	r0, r0
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12167              		.loc 1 1741 44 discriminator 4 view .LVU3708
+ 12168 0056 0228     		cmp	r0, #2
+ARM GAS  /tmp/cc0wMqvE.s 			page 409
+
+
+ 12169 0058 14BF     		ite	ne
+ 12170 005a 0020     		movne	r0, #0
+ 12171 005c 0120     		moveq	r0, #1
+ 12172 005e E7E7     		b	.L880
+ 12173              	.LVL927:
+ 12174              	.L877:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12175              		.loc 1 1741 7 discriminator 7 view .LVU3709
+ 12176 0060 90F84000 		ldrb	r0, [r0, #64]	@ zero_extendqisi2
+ 12177              	.LVL928:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12178              		.loc 1 1741 7 discriminator 7 view .LVU3710
+ 12179 0064 C0B2     		uxtb	r0, r0
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12180              		.loc 1 1741 44 discriminator 7 view .LVU3711
+ 12181 0066 0228     		cmp	r0, #2
+ 12182 0068 14BF     		ite	ne
+ 12183 006a 0020     		movne	r0, #0
+ 12184 006c 0120     		moveq	r0, #1
+ 12185 006e DFE7     		b	.L880
+ 12186              	.LVL929:
+ 12187              	.L876:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12188              		.loc 1 1741 7 discriminator 10 view .LVU3712
+ 12189 0070 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 12190              	.LVL930:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12191              		.loc 1 1741 7 discriminator 10 view .LVU3713
+ 12192 0074 C0B2     		uxtb	r0, r0
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12193              		.loc 1 1741 44 discriminator 10 view .LVU3714
+ 12194 0076 0228     		cmp	r0, #2
+ 12195 0078 14BF     		ite	ne
+ 12196 007a 0020     		movne	r0, #0
+ 12197 007c 0120     		moveq	r0, #1
+ 12198 007e D7E7     		b	.L880
+ 12199              	.LVL931:
+ 12200              	.L874:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12201              		.loc 1 1741 7 discriminator 13 view .LVU3715
+ 12202 0080 90F84200 		ldrb	r0, [r0, #66]	@ zero_extendqisi2
+ 12203              	.LVL932:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12204              		.loc 1 1741 7 discriminator 13 view .LVU3716
+ 12205 0084 C0B2     		uxtb	r0, r0
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12206              		.loc 1 1741 44 discriminator 13 view .LVU3717
+ 12207 0086 0228     		cmp	r0, #2
+ 12208 0088 14BF     		ite	ne
+ 12209 008a 0020     		movne	r0, #0
+ 12210 008c 0120     		moveq	r0, #1
+ 12211 008e CFE7     		b	.L880
+ 12212              	.LVL933:
+ 12213              	.L873:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12214              		.loc 1 1741 7 discriminator 14 view .LVU3718
+ 12215 0090 90F84300 		ldrb	r0, [r0, #67]	@ zero_extendqisi2
+ARM GAS  /tmp/cc0wMqvE.s 			page 410
+
+
+ 12216              	.LVL934:
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12217              		.loc 1 1741 7 discriminator 14 view .LVU3719
+ 12218 0094 C0B2     		uxtb	r0, r0
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12219              		.loc 1 1741 44 discriminator 14 view .LVU3720
+ 12220 0096 0228     		cmp	r0, #2
+ 12221 0098 14BF     		ite	ne
+ 12222 009a 0020     		movne	r0, #0
+ 12223 009c 0120     		moveq	r0, #1
+ 12224 009e C7E7     		b	.L880
+ 12225              	.L888:
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12226              		.loc 1 1745 12 discriminator 1 view .LVU3721
+ 12227 00a0 94F83E20 		ldrb	r2, [r4, #62]	@ zero_extendqisi2
+ 12228 00a4 D2B2     		uxtb	r2, r2
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12229              		.loc 1 1745 49 discriminator 1 view .LVU3722
+ 12230 00a6 012A     		cmp	r2, #1
+ 12231 00a8 14BF     		ite	ne
+ 12232 00aa 0022     		movne	r2, #0
+ 12233 00ac 0122     		moveq	r2, #1
+ 12234              	.L889:
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12235              		.loc 1 1745 11 discriminator 20 view .LVU3723
+ 12236 00ae 002A     		cmp	r2, #0
+ 12237 00b0 00F01C81 		beq	.L909
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12238              		.loc 1 1747 5 is_stmt 1 view .LVU3724
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12239              		.loc 1 1747 8 is_stmt 0 view .LVU3725
+ 12240 00b4 0029     		cmp	r1, #0
+ 12241 00b6 3DD0     		beq	.L923
+ 12242              	.L890:
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12243              		.loc 1 1753 7 is_stmt 1 view .LVU3726
+ 12244 00b8 102D     		cmp	r5, #16
+ 12245 00ba 00F2E580 		bhi	.L891
+ 12246 00be DFE815F0 		tbh	[pc, r5, lsl #1]
+ 12247              	.L893:
+ 12248 00c2 3D00     		.2byte	(.L897-.L893)/2
+ 12249 00c4 E300     		.2byte	(.L891-.L893)/2
+ 12250 00c6 E300     		.2byte	(.L891-.L893)/2
+ 12251 00c8 E300     		.2byte	(.L891-.L893)/2
+ 12252 00ca 9300     		.2byte	(.L896-.L893)/2
+ 12253 00cc E300     		.2byte	(.L891-.L893)/2
+ 12254 00ce E300     		.2byte	(.L891-.L893)/2
+ 12255 00d0 E300     		.2byte	(.L891-.L893)/2
+ 12256 00d2 AC00     		.2byte	(.L895-.L893)/2
+ 12257 00d4 E300     		.2byte	(.L891-.L893)/2
+ 12258 00d6 E300     		.2byte	(.L891-.L893)/2
+ 12259 00d8 E300     		.2byte	(.L891-.L893)/2
+ 12260 00da C500     		.2byte	(.L894-.L893)/2
+ 12261 00dc E300     		.2byte	(.L891-.L893)/2
+ 12262 00de E300     		.2byte	(.L891-.L893)/2
+ 12263 00e0 E300     		.2byte	(.L891-.L893)/2
+ 12264 00e2 DE00     		.2byte	(.L892-.L893)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 411
+
+
+ 12265              		.p2align 1
+ 12266              	.L887:
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12267              		.loc 1 1745 12 is_stmt 0 discriminator 4 view .LVU3727
+ 12268 00e4 94F83F20 		ldrb	r2, [r4, #63]	@ zero_extendqisi2
+ 12269 00e8 D2B2     		uxtb	r2, r2
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12270              		.loc 1 1745 49 discriminator 4 view .LVU3728
+ 12271 00ea 012A     		cmp	r2, #1
+ 12272 00ec 14BF     		ite	ne
+ 12273 00ee 0022     		movne	r2, #0
+ 12274 00f0 0122     		moveq	r2, #1
+ 12275 00f2 DCE7     		b	.L889
+ 12276              	.L886:
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12277              		.loc 1 1745 12 discriminator 7 view .LVU3729
+ 12278 00f4 94F84020 		ldrb	r2, [r4, #64]	@ zero_extendqisi2
+ 12279 00f8 D2B2     		uxtb	r2, r2
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12280              		.loc 1 1745 49 discriminator 7 view .LVU3730
+ 12281 00fa 012A     		cmp	r2, #1
+ 12282 00fc 14BF     		ite	ne
+ 12283 00fe 0022     		movne	r2, #0
+ 12284 0100 0122     		moveq	r2, #1
+ 12285 0102 D4E7     		b	.L889
+ 12286              	.L885:
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12287              		.loc 1 1745 12 discriminator 10 view .LVU3731
+ 12288 0104 94F84120 		ldrb	r2, [r4, #65]	@ zero_extendqisi2
+ 12289 0108 D2B2     		uxtb	r2, r2
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12290              		.loc 1 1745 49 discriminator 10 view .LVU3732
+ 12291 010a 012A     		cmp	r2, #1
+ 12292 010c 14BF     		ite	ne
+ 12293 010e 0022     		movne	r2, #0
+ 12294 0110 0122     		moveq	r2, #1
+ 12295 0112 CCE7     		b	.L889
+ 12296              	.L883:
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12297              		.loc 1 1745 12 discriminator 13 view .LVU3733
+ 12298 0114 94F84220 		ldrb	r2, [r4, #66]	@ zero_extendqisi2
+ 12299 0118 D2B2     		uxtb	r2, r2
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12300              		.loc 1 1745 49 discriminator 13 view .LVU3734
+ 12301 011a 012A     		cmp	r2, #1
+ 12302 011c 14BF     		ite	ne
+ 12303 011e 0022     		movne	r2, #0
+ 12304 0120 0122     		moveq	r2, #1
+ 12305 0122 C4E7     		b	.L889
+ 12306              	.L882:
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12307              		.loc 1 1745 12 discriminator 14 view .LVU3735
+ 12308 0124 94F84320 		ldrb	r2, [r4, #67]	@ zero_extendqisi2
+ 12309 0128 D2B2     		uxtb	r2, r2
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12310              		.loc 1 1745 49 discriminator 14 view .LVU3736
+ 12311 012a 012A     		cmp	r2, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 412
+
+
+ 12312 012c 14BF     		ite	ne
+ 12313 012e 0022     		movne	r2, #0
+ 12314 0130 0122     		moveq	r2, #1
+ 12315 0132 BCE7     		b	.L889
+ 12316              	.L923:
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12317              		.loc 1 1747 25 discriminator 1 view .LVU3737
+ 12318 0134 002B     		cmp	r3, #0
+ 12319 0136 BFD0     		beq	.L890
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12320              		.loc 1 1749 14 view .LVU3738
+ 12321 0138 0120     		movs	r0, #1
+ 12322 013a D8E0     		b	.L881
+ 12323              	.L897:
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12324              		.loc 1 1753 7 view .LVU3739
+ 12325 013c 0222     		movs	r2, #2
+ 12326 013e 84F83E20 		strb	r2, [r4, #62]
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12327              		.loc 1 1761 3 is_stmt 1 view .LVU3740
+ 12328              	.L898:
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 12329              		.loc 1 1766 7 view .LVU3741
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 12330              		.loc 1 1766 17 is_stmt 0 view .LVU3742
+ 12331 0142 626A     		ldr	r2, [r4, #36]
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 12332              		.loc 1 1766 52 view .LVU3743
+ 12333 0144 7148     		ldr	r0, .L924
+ 12334 0146 D062     		str	r0, [r2, #44]
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12335              		.loc 1 1767 7 is_stmt 1 view .LVU3744
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12336              		.loc 1 1767 17 is_stmt 0 view .LVU3745
+ 12337 0148 626A     		ldr	r2, [r4, #36]
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12338              		.loc 1 1767 56 view .LVU3746
+ 12339 014a 7148     		ldr	r0, .L924+4
+ 12340 014c 1063     		str	r0, [r2, #48]
+1770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12341              		.loc 1 1770 7 is_stmt 1 view .LVU3747
+1770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12342              		.loc 1 1770 17 is_stmt 0 view .LVU3748
+ 12343 014e 626A     		ldr	r2, [r4, #36]
+1770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12344              		.loc 1 1770 53 view .LVU3749
+ 12345 0150 7048     		ldr	r0, .L924+8
+ 12346 0152 5063     		str	r0, [r2, #52]
+1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12347              		.loc 1 1773 7 is_stmt 1 view .LVU3750
+1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12348              		.loc 1 1773 88 is_stmt 0 view .LVU3751
+ 12349 0154 2268     		ldr	r2, [r4]
+1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12350              		.loc 1 1773 11 view .LVU3752
+ 12351 0156 3432     		adds	r2, r2, #52
+ 12352 0158 606A     		ldr	r0, [r4, #36]
+ARM GAS  /tmp/cc0wMqvE.s 			page 413
+
+
+ 12353 015a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 12354              	.LVL935:
+1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12355              		.loc 1 1773 10 view .LVU3753
+ 12356 015e 0028     		cmp	r0, #0
+ 12357 0160 40F0C880 		bne	.L912
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12358              		.loc 1 1781 7 is_stmt 1 view .LVU3754
+ 12359 0164 2268     		ldr	r2, [r4]
+ 12360 0166 D368     		ldr	r3, [r2, #12]
+ 12361 0168 43F40073 		orr	r3, r3, #512
+ 12362 016c D360     		str	r3, [r2, #12]
+1782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12363              		.loc 1 1782 7 view .LVU3755
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12364              		.loc 1 1853 3 view .LVU3756
+ 12365              	.L903:
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12366              		.loc 1 1856 5 view .LVU3757
+ 12367 016e 0122     		movs	r2, #1
+ 12368 0170 2946     		mov	r1, r5
+ 12369 0172 2068     		ldr	r0, [r4]
+ 12370 0174 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 12371              	.LVL936:
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12372              		.loc 1 1858 5 view .LVU3758
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12373              		.loc 1 1858 9 is_stmt 0 view .LVU3759
+ 12374 0178 2368     		ldr	r3, [r4]
+ 12375 017a 674A     		ldr	r2, .L924+12
+ 12376 017c 9342     		cmp	r3, r2
+ 12377 017e 0FD0     		beq	.L904
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12378              		.loc 1 1858 9 discriminator 2 view .LVU3760
+ 12379 0180 02F50062 		add	r2, r2, #2048
+ 12380 0184 9342     		cmp	r3, r2
+ 12381 0186 0BD0     		beq	.L904
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12382              		.loc 1 1858 9 discriminator 4 view .LVU3761
+ 12383 0188 02F54062 		add	r2, r2, #3072
+ 12384 018c 9342     		cmp	r3, r2
+ 12385 018e 07D0     		beq	.L904
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12386              		.loc 1 1858 9 discriminator 6 view .LVU3762
+ 12387 0190 02F58062 		add	r2, r2, #1024
+ 12388 0194 9342     		cmp	r3, r2
+ 12389 0196 03D0     		beq	.L904
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12390              		.loc 1 1858 9 discriminator 8 view .LVU3763
+ 12391 0198 02F58062 		add	r2, r2, #1024
+ 12392 019c 9342     		cmp	r3, r2
+ 12393 019e 03D1     		bne	.L905
+ 12394              	.L904:
+1861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12395              		.loc 1 1861 7 is_stmt 1 view .LVU3764
+ 12396 01a0 5A6C     		ldr	r2, [r3, #68]
+ 12397 01a2 42F40042 		orr	r2, r2, #32768
+ARM GAS  /tmp/cc0wMqvE.s 			page 414
+
+
+ 12398 01a6 5A64     		str	r2, [r3, #68]
+ 12399              	.L905:
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12400              		.loc 1 1865 5 view .LVU3765
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12401              		.loc 1 1865 9 is_stmt 0 view .LVU3766
+ 12402 01a8 2368     		ldr	r3, [r4]
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12403              		.loc 1 1865 8 view .LVU3767
+ 12404 01aa 5B4A     		ldr	r2, .L924+12
+ 12405 01ac 9342     		cmp	r3, r2
+ 12406 01ae 00F08D80 		beq	.L906
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12407              		.loc 1 1865 9 discriminator 1 view .LVU3768
+ 12408 01b2 B3F1804F 		cmp	r3, #1073741824
+ 12409 01b6 00F08980 		beq	.L906
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12410              		.loc 1 1865 9 discriminator 2 view .LVU3769
+ 12411 01ba A2F59432 		sub	r2, r2, #75776
+ 12412 01be 9342     		cmp	r3, r2
+ 12413 01c0 00F08480 		beq	.L906
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12414              		.loc 1 1865 9 discriminator 3 view .LVU3770
+ 12415 01c4 02F58062 		add	r2, r2, #1024
+ 12416 01c8 9342     		cmp	r3, r2
+ 12417 01ca 7FD0     		beq	.L906
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12418              		.loc 1 1865 9 discriminator 4 view .LVU3771
+ 12419 01cc 02F59632 		add	r2, r2, #76800
+ 12420 01d0 9342     		cmp	r3, r2
+ 12421 01d2 7BD0     		beq	.L906
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12422              		.loc 1 1865 9 discriminator 5 view .LVU3772
+ 12423 01d4 02F54062 		add	r2, r2, #3072
+ 12424 01d8 9342     		cmp	r3, r2
+ 12425 01da 77D0     		beq	.L906
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12426              		.loc 1 1875 7 is_stmt 1 view .LVU3773
+ 12427 01dc 1A68     		ldr	r2, [r3]
+ 12428 01de 42F00102 		orr	r2, r2, #1
+ 12429 01e2 1A60     		str	r2, [r3]
+ 12430 01e4 0020     		movs	r0, #0
+ 12431 01e6 82E0     		b	.L881
+ 12432              	.LVL937:
+ 12433              	.L896:
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12434              		.loc 1 1753 7 is_stmt 0 view .LVU3774
+ 12435 01e8 0222     		movs	r2, #2
+ 12436 01ea 84F83F20 		strb	r2, [r4, #63]
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12437              		.loc 1 1761 3 is_stmt 1 view .LVU3775
+ 12438              	.L899:
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 12439              		.loc 1 1788 7 view .LVU3776
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 12440              		.loc 1 1788 17 is_stmt 0 view .LVU3777
+ 12441 01ee A26A     		ldr	r2, [r4, #40]
+ARM GAS  /tmp/cc0wMqvE.s 			page 415
+
+
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 12442              		.loc 1 1788 52 view .LVU3778
+ 12443 01f0 4648     		ldr	r0, .L924
+ 12444 01f2 D062     		str	r0, [r2, #44]
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12445              		.loc 1 1789 7 is_stmt 1 view .LVU3779
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12446              		.loc 1 1789 17 is_stmt 0 view .LVU3780
+ 12447 01f4 A26A     		ldr	r2, [r4, #40]
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12448              		.loc 1 1789 56 view .LVU3781
+ 12449 01f6 4648     		ldr	r0, .L924+4
+ 12450 01f8 1063     		str	r0, [r2, #48]
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12451              		.loc 1 1792 7 is_stmt 1 view .LVU3782
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12452              		.loc 1 1792 17 is_stmt 0 view .LVU3783
+ 12453 01fa A26A     		ldr	r2, [r4, #40]
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12454              		.loc 1 1792 53 view .LVU3784
+ 12455 01fc 4548     		ldr	r0, .L924+8
+ 12456 01fe 5063     		str	r0, [r2, #52]
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12457              		.loc 1 1795 7 is_stmt 1 view .LVU3785
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12458              		.loc 1 1795 88 is_stmt 0 view .LVU3786
+ 12459 0200 2268     		ldr	r2, [r4]
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12460              		.loc 1 1795 11 view .LVU3787
+ 12461 0202 3832     		adds	r2, r2, #56
+ 12462 0204 A06A     		ldr	r0, [r4, #40]
+ 12463 0206 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 12464              	.LVL938:
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12465              		.loc 1 1795 10 view .LVU3788
+ 12466 020a 0028     		cmp	r0, #0
+ 12467 020c 74D1     		bne	.L913
+1802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12468              		.loc 1 1802 7 is_stmt 1 view .LVU3789
+ 12469 020e 2268     		ldr	r2, [r4]
+ 12470 0210 D368     		ldr	r3, [r2, #12]
+ 12471 0212 43F48063 		orr	r3, r3, #1024
+ 12472 0216 D360     		str	r3, [r2, #12]
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12473              		.loc 1 1803 7 view .LVU3790
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12474              		.loc 1 1853 3 view .LVU3791
+ 12475 0218 A9E7     		b	.L903
+ 12476              	.LVL939:
+ 12477              	.L895:
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12478              		.loc 1 1753 7 is_stmt 0 view .LVU3792
+ 12479 021a 0222     		movs	r2, #2
+ 12480 021c 84F84020 		strb	r2, [r4, #64]
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12481              		.loc 1 1761 3 is_stmt 1 view .LVU3793
+ 12482              	.L900:
+ARM GAS  /tmp/cc0wMqvE.s 			page 416
+
+
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 12483              		.loc 1 1809 7 view .LVU3794
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 12484              		.loc 1 1809 17 is_stmt 0 view .LVU3795
+ 12485 0220 E26A     		ldr	r2, [r4, #44]
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 12486              		.loc 1 1809 52 view .LVU3796
+ 12487 0222 3A48     		ldr	r0, .L924
+ 12488 0224 D062     		str	r0, [r2, #44]
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12489              		.loc 1 1810 7 is_stmt 1 view .LVU3797
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12490              		.loc 1 1810 17 is_stmt 0 view .LVU3798
+ 12491 0226 E26A     		ldr	r2, [r4, #44]
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12492              		.loc 1 1810 56 view .LVU3799
+ 12493 0228 3948     		ldr	r0, .L924+4
+ 12494 022a 1063     		str	r0, [r2, #48]
+1813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12495              		.loc 1 1813 7 is_stmt 1 view .LVU3800
+1813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12496              		.loc 1 1813 17 is_stmt 0 view .LVU3801
+ 12497 022c E26A     		ldr	r2, [r4, #44]
+1813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12498              		.loc 1 1813 53 view .LVU3802
+ 12499 022e 3948     		ldr	r0, .L924+8
+ 12500 0230 5063     		str	r0, [r2, #52]
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12501              		.loc 1 1816 7 is_stmt 1 view .LVU3803
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12502              		.loc 1 1816 88 is_stmt 0 view .LVU3804
+ 12503 0232 2268     		ldr	r2, [r4]
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12504              		.loc 1 1816 11 view .LVU3805
+ 12505 0234 3C32     		adds	r2, r2, #60
+ 12506 0236 E06A     		ldr	r0, [r4, #44]
+ 12507 0238 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 12508              	.LVL940:
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12509              		.loc 1 1816 10 view .LVU3806
+ 12510 023c 0028     		cmp	r0, #0
+ 12511 023e 5DD1     		bne	.L914
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12512              		.loc 1 1823 7 is_stmt 1 view .LVU3807
+ 12513 0240 2268     		ldr	r2, [r4]
+ 12514 0242 D368     		ldr	r3, [r2, #12]
+ 12515 0244 43F40063 		orr	r3, r3, #2048
+ 12516 0248 D360     		str	r3, [r2, #12]
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12517              		.loc 1 1824 7 view .LVU3808
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12518              		.loc 1 1853 3 view .LVU3809
+ 12519 024a 90E7     		b	.L903
+ 12520              	.LVL941:
+ 12521              	.L894:
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12522              		.loc 1 1753 7 is_stmt 0 view .LVU3810
+ARM GAS  /tmp/cc0wMqvE.s 			page 417
+
+
+ 12523 024c 0222     		movs	r2, #2
+ 12524 024e 84F84120 		strb	r2, [r4, #65]
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12525              		.loc 1 1761 3 is_stmt 1 view .LVU3811
+ 12526              	.L901:
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 12527              		.loc 1 1830 7 view .LVU3812
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 12528              		.loc 1 1830 17 is_stmt 0 view .LVU3813
+ 12529 0252 226B     		ldr	r2, [r4, #48]
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 12530              		.loc 1 1830 52 view .LVU3814
+ 12531 0254 2D48     		ldr	r0, .L924
+ 12532 0256 D062     		str	r0, [r2, #44]
+1831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12533              		.loc 1 1831 7 is_stmt 1 view .LVU3815
+1831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12534              		.loc 1 1831 17 is_stmt 0 view .LVU3816
+ 12535 0258 226B     		ldr	r2, [r4, #48]
+1831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12536              		.loc 1 1831 56 view .LVU3817
+ 12537 025a 2D48     		ldr	r0, .L924+4
+ 12538 025c 1063     		str	r0, [r2, #48]
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12539              		.loc 1 1834 7 is_stmt 1 view .LVU3818
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12540              		.loc 1 1834 17 is_stmt 0 view .LVU3819
+ 12541 025e 226B     		ldr	r2, [r4, #48]
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12542              		.loc 1 1834 53 view .LVU3820
+ 12543 0260 2C48     		ldr	r0, .L924+8
+ 12544 0262 5063     		str	r0, [r2, #52]
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12545              		.loc 1 1837 7 is_stmt 1 view .LVU3821
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12546              		.loc 1 1837 88 is_stmt 0 view .LVU3822
+ 12547 0264 2268     		ldr	r2, [r4]
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12548              		.loc 1 1837 11 view .LVU3823
+ 12549 0266 4032     		adds	r2, r2, #64
+ 12550 0268 206B     		ldr	r0, [r4, #48]
+ 12551 026a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 12552              	.LVL942:
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 12553              		.loc 1 1837 10 view .LVU3824
+ 12554 026e 0028     		cmp	r0, #0
+ 12555 0270 46D1     		bne	.L915
+1844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12556              		.loc 1 1844 7 is_stmt 1 view .LVU3825
+ 12557 0272 2268     		ldr	r2, [r4]
+ 12558 0274 D368     		ldr	r3, [r2, #12]
+ 12559 0276 43F48053 		orr	r3, r3, #4096
+ 12560 027a D360     		str	r3, [r2, #12]
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12561              		.loc 1 1845 7 view .LVU3826
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12562              		.loc 1 1853 3 view .LVU3827
+ARM GAS  /tmp/cc0wMqvE.s 			page 418
+
+
+ 12563 027c 77E7     		b	.L903
+ 12564              	.LVL943:
+ 12565              	.L892:
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12566              		.loc 1 1753 7 is_stmt 0 view .LVU3828
+ 12567 027e 0223     		movs	r3, #2
+ 12568              	.LVL944:
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12569              		.loc 1 1753 7 view .LVU3829
+ 12570 0280 84F84230 		strb	r3, [r4, #66]
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12571              		.loc 1 1761 3 is_stmt 1 view .LVU3830
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12572              		.loc 1 1753 7 is_stmt 0 view .LVU3831
+ 12573 0284 0120     		movs	r0, #1
+ 12574 0286 32E0     		b	.L881
+ 12575              	.LVL945:
+ 12576              	.L891:
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12577              		.loc 1 1753 7 discriminator 13 view .LVU3832
+ 12578 0288 0222     		movs	r2, #2
+ 12579 028a 84F84320 		strb	r2, [r4, #67]
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12580              		.loc 1 1761 3 is_stmt 1 discriminator 13 view .LVU3833
+ 12581 028e 0C2D     		cmp	r5, #12
+ 12582 0290 2ED8     		bhi	.L911
+ 12583 0292 01A2     		adr	r2, .L902
+ 12584 0294 52F825F0 		ldr	pc, [r2, r5, lsl #2]
+ 12585              		.p2align 2
+ 12586              	.L902:
+ 12587 0298 43010000 		.word	.L898+1
+ 12588 029c F1020000 		.word	.L911+1
+ 12589 02a0 F1020000 		.word	.L911+1
+ 12590 02a4 F1020000 		.word	.L911+1
+ 12591 02a8 EF010000 		.word	.L899+1
+ 12592 02ac F1020000 		.word	.L911+1
+ 12593 02b0 F1020000 		.word	.L911+1
+ 12594 02b4 F1020000 		.word	.L911+1
+ 12595 02b8 21020000 		.word	.L900+1
+ 12596 02bc F1020000 		.word	.L911+1
+ 12597 02c0 F1020000 		.word	.L911+1
+ 12598 02c4 F1020000 		.word	.L911+1
+ 12599 02c8 53020000 		.word	.L901+1
+ 12600              	.LVL946:
+ 12601              		.p2align 1
+ 12602              	.L906:
+1867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 12603              		.loc 1 1867 7 view .LVU3834
+1867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 12604              		.loc 1 1867 31 is_stmt 0 view .LVU3835
+ 12605 02cc 9968     		ldr	r1, [r3, #8]
+1867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 12606              		.loc 1 1867 15 view .LVU3836
+ 12607 02ce 134A     		ldr	r2, .L924+16
+ 12608 02d0 0A40     		ands	r2, r2, r1
+ 12609              	.LVL947:
+1868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ARM GAS  /tmp/cc0wMqvE.s 			page 419
+
+
+ 12610              		.loc 1 1868 7 is_stmt 1 view .LVU3837
+1868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 12611              		.loc 1 1868 10 is_stmt 0 view .LVU3838
+ 12612 02d2 062A     		cmp	r2, #6
+ 12613 02d4 16D0     		beq	.L916
+1868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 12614              		.loc 1 1868 11 discriminator 1 view .LVU3839
+ 12615 02d6 B2F5803F 		cmp	r2, #65536
+ 12616 02da 15D0     		beq	.L917
+1870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 12617              		.loc 1 1870 9 is_stmt 1 view .LVU3840
+ 12618 02dc 1A68     		ldr	r2, [r3]
+ 12619              	.LVL948:
+1870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 12620              		.loc 1 1870 9 is_stmt 0 view .LVU3841
+ 12621 02de 42F00102 		orr	r2, r2, #1
+ 12622 02e2 1A60     		str	r2, [r3]
+ 12623 02e4 0020     		movs	r0, #0
+ 12624 02e6 02E0     		b	.L881
+ 12625              	.LVL949:
+ 12626              	.L908:
+1743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12627              		.loc 1 1743 12 view .LVU3842
+ 12628 02e8 0220     		movs	r0, #2
+ 12629 02ea 00E0     		b	.L881
+ 12630              	.L909:
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12631              		.loc 1 1758 12 view .LVU3843
+ 12632 02ec 0120     		movs	r0, #1
+ 12633              	.LVL950:
+ 12634              	.L881:
+1881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12635              		.loc 1 1881 1 view .LVU3844
+ 12636 02ee 38BD     		pop	{r3, r4, r5, pc}
+ 12637              	.LVL951:
+ 12638              	.L911:
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12639              		.loc 1 1761 3 view .LVU3845
+ 12640 02f0 0120     		movs	r0, #1
+ 12641 02f2 FCE7     		b	.L881
+ 12642              	.LVL952:
+ 12643              	.L912:
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 12644              		.loc 1 1777 16 view .LVU3846
+ 12645 02f4 0120     		movs	r0, #1
+ 12646 02f6 FAE7     		b	.L881
+ 12647              	.L913:
+1799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 12648              		.loc 1 1799 16 view .LVU3847
+ 12649 02f8 0120     		movs	r0, #1
+ 12650 02fa F8E7     		b	.L881
+ 12651              	.L914:
+1820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 12652              		.loc 1 1820 16 view .LVU3848
+ 12653 02fc 0120     		movs	r0, #1
+ 12654 02fe F6E7     		b	.L881
+ 12655              	.L915:
+ARM GAS  /tmp/cc0wMqvE.s 			page 420
+
+
+1841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 12656              		.loc 1 1841 16 view .LVU3849
+ 12657 0300 0120     		movs	r0, #1
+ 12658 0302 F4E7     		b	.L881
+ 12659              	.LVL953:
+ 12660              	.L916:
+1841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 12661              		.loc 1 1841 16 view .LVU3850
+ 12662 0304 0020     		movs	r0, #0
+ 12663 0306 F2E7     		b	.L881
+ 12664              	.L917:
+ 12665 0308 0020     		movs	r0, #0
+ 12666 030a F0E7     		b	.L881
+ 12667              	.L925:
+ 12668              		.align	2
+ 12669              	.L924:
+ 12670 030c 00000000 		.word	TIM_DMADelayPulseCplt
+ 12671 0310 00000000 		.word	TIM_DMADelayPulseHalfCplt
+ 12672 0314 00000000 		.word	TIM_DMAError
+ 12673 0318 002C0140 		.word	1073818624
+ 12674 031c 07000100 		.word	65543
+ 12675              		.cfi_endproc
+ 12676              	.LFE357:
+ 12678              		.section	.text.HAL_TIM_PWM_Stop_DMA,"ax",%progbits
+ 12679              		.align	1
+ 12680              		.global	HAL_TIM_PWM_Stop_DMA
+ 12681              		.syntax unified
+ 12682              		.thumb
+ 12683              		.thumb_func
+ 12685              	HAL_TIM_PWM_Stop_DMA:
+ 12686              	.LVL954:
+ 12687              	.LFB358:
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 12688              		.loc 1 1895 1 is_stmt 1 view -0
+ 12689              		.cfi_startproc
+ 12690              		@ args = 0, pretend = 0, frame = 0
+ 12691              		@ frame_needed = 0, uses_anonymous_args = 0
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 12692              		.loc 1 1895 1 is_stmt 0 view .LVU3852
+ 12693 0000 38B5     		push	{r3, r4, r5, lr}
+ 12694              	.LCFI96:
+ 12695              		.cfi_def_cfa_offset 16
+ 12696              		.cfi_offset 3, -16
+ 12697              		.cfi_offset 4, -12
+ 12698              		.cfi_offset 5, -8
+ 12699              		.cfi_offset 14, -4
+ 12700 0002 0546     		mov	r5, r0
+ 12701 0004 0C46     		mov	r4, r1
+1896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12702              		.loc 1 1896 3 is_stmt 1 view .LVU3853
+ 12703              	.LVL955:
+1899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12704              		.loc 1 1899 3 view .LVU3854
+1901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12705              		.loc 1 1901 3 view .LVU3855
+ 12706 0006 0C29     		cmp	r1, #12
+ 12707 0008 00F28D80 		bhi	.L944
+ARM GAS  /tmp/cc0wMqvE.s 			page 421
+
+
+ 12708 000c DFE801F0 		tbb	[pc, r1]
+ 12709              	.L929:
+ 12710 0010 07       		.byte	(.L932-.L929)/2
+ 12711 0011 8B       		.byte	(.L944-.L929)/2
+ 12712 0012 8B       		.byte	(.L944-.L929)/2
+ 12713 0013 8B       		.byte	(.L944-.L929)/2
+ 12714 0014 4B       		.byte	(.L931-.L929)/2
+ 12715 0015 8B       		.byte	(.L944-.L929)/2
+ 12716 0016 8B       		.byte	(.L944-.L929)/2
+ 12717 0017 8B       		.byte	(.L944-.L929)/2
+ 12718 0018 54       		.byte	(.L930-.L929)/2
+ 12719 0019 8B       		.byte	(.L944-.L929)/2
+ 12720 001a 8B       		.byte	(.L944-.L929)/2
+ 12721 001b 8B       		.byte	(.L944-.L929)/2
+ 12722 001c 5D       		.byte	(.L928-.L929)/2
+ 12723 001d 00       		.p2align 1
+ 12724              	.L932:
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 12725              		.loc 1 1906 7 view .LVU3856
+ 12726 001e 0268     		ldr	r2, [r0]
+ 12727 0020 D368     		ldr	r3, [r2, #12]
+ 12728 0022 23F40073 		bic	r3, r3, #512
+ 12729 0026 D360     		str	r3, [r2, #12]
+1907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12730              		.loc 1 1907 7 view .LVU3857
+1907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12731              		.loc 1 1907 13 is_stmt 0 view .LVU3858
+ 12732 0028 406A     		ldr	r0, [r0, #36]
+ 12733              	.LVL956:
+1907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12734              		.loc 1 1907 13 view .LVU3859
+ 12735 002a FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 12736              	.LVL957:
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12737              		.loc 1 1908 7 is_stmt 1 view .LVU3860
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12738              		.loc 1 1940 3 view .LVU3861
+ 12739              	.L933:
+1943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12740              		.loc 1 1943 5 view .LVU3862
+ 12741 002e 0022     		movs	r2, #0
+ 12742 0030 2146     		mov	r1, r4
+ 12743 0032 2868     		ldr	r0, [r5]
+ 12744 0034 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 12745              	.LVL958:
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12746              		.loc 1 1945 5 view .LVU3863
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12747              		.loc 1 1945 9 is_stmt 0 view .LVU3864
+ 12748 0038 2B68     		ldr	r3, [r5]
+ 12749 003a 3C4A     		ldr	r2, .L946
+ 12750 003c 9342     		cmp	r3, r2
+ 12751 003e 0FD0     		beq	.L934
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12752              		.loc 1 1945 9 discriminator 2 view .LVU3865
+ 12753 0040 02F50062 		add	r2, r2, #2048
+ 12754 0044 9342     		cmp	r3, r2
+ARM GAS  /tmp/cc0wMqvE.s 			page 422
+
+
+ 12755 0046 0BD0     		beq	.L934
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12756              		.loc 1 1945 9 discriminator 4 view .LVU3866
+ 12757 0048 02F54062 		add	r2, r2, #3072
+ 12758 004c 9342     		cmp	r3, r2
+ 12759 004e 07D0     		beq	.L934
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12760              		.loc 1 1945 9 discriminator 6 view .LVU3867
+ 12761 0050 02F58062 		add	r2, r2, #1024
+ 12762 0054 9342     		cmp	r3, r2
+ 12763 0056 03D0     		beq	.L934
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 12764              		.loc 1 1945 9 discriminator 8 view .LVU3868
+ 12765 0058 02F58062 		add	r2, r2, #1024
+ 12766 005c 9342     		cmp	r3, r2
+ 12767 005e 0DD1     		bne	.L935
+ 12768              	.L934:
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12769              		.loc 1 1948 7 is_stmt 1 view .LVU3869
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12770              		.loc 1 1948 7 view .LVU3870
+ 12771 0060 196A     		ldr	r1, [r3, #32]
+ 12772 0062 41F21112 		movw	r2, #4369
+ 12773 0066 1142     		tst	r1, r2
+ 12774 0068 08D1     		bne	.L935
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12775              		.loc 1 1948 7 discriminator 1 view .LVU3871
+ 12776 006a 196A     		ldr	r1, [r3, #32]
+ 12777 006c 44F24442 		movw	r2, #17476
+ 12778 0070 1142     		tst	r1, r2
+ 12779 0072 03D1     		bne	.L935
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12780              		.loc 1 1948 7 discriminator 3 view .LVU3872
+ 12781 0074 5A6C     		ldr	r2, [r3, #68]
+ 12782 0076 22F40042 		bic	r2, r2, #32768
+ 12783 007a 5A64     		str	r2, [r3, #68]
+ 12784              	.L935:
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12785              		.loc 1 1948 7 discriminator 5 view .LVU3873
+1952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12786              		.loc 1 1952 5 discriminator 5 view .LVU3874
+1952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12787              		.loc 1 1952 5 discriminator 5 view .LVU3875
+ 12788 007c 2B68     		ldr	r3, [r5]
+ 12789 007e 196A     		ldr	r1, [r3, #32]
+ 12790 0080 41F21112 		movw	r2, #4369
+ 12791 0084 1142     		tst	r1, r2
+ 12792 0086 08D1     		bne	.L936
+1952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12793              		.loc 1 1952 5 discriminator 1 view .LVU3876
+ 12794 0088 196A     		ldr	r1, [r3, #32]
+ 12795 008a 44F24442 		movw	r2, #17476
+ 12796 008e 1142     		tst	r1, r2
+ 12797 0090 03D1     		bne	.L936
+1952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12798              		.loc 1 1952 5 discriminator 3 view .LVU3877
+ 12799 0092 1A68     		ldr	r2, [r3]
+ARM GAS  /tmp/cc0wMqvE.s 			page 423
+
+
+ 12800 0094 22F00102 		bic	r2, r2, #1
+ 12801 0098 1A60     		str	r2, [r3]
+ 12802              	.L936:
+1952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12803              		.loc 1 1952 5 discriminator 5 view .LVU3878
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12804              		.loc 1 1955 5 discriminator 5 view .LVU3879
+ 12805 009a FCB9     		cbnz	r4, .L937
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12806              		.loc 1 1955 5 is_stmt 0 discriminator 1 view .LVU3880
+ 12807 009c 0123     		movs	r3, #1
+ 12808 009e 85F83E30 		strb	r3, [r5, #62]
+ 12809 00a2 0020     		movs	r0, #0
+ 12810 00a4 40E0     		b	.L927
+ 12811              	.LVL959:
+ 12812              	.L931:
+1914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 12813              		.loc 1 1914 7 is_stmt 1 view .LVU3881
+ 12814 00a6 0268     		ldr	r2, [r0]
+ 12815 00a8 D368     		ldr	r3, [r2, #12]
+ 12816 00aa 23F48063 		bic	r3, r3, #1024
+ 12817 00ae D360     		str	r3, [r2, #12]
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12818              		.loc 1 1915 7 view .LVU3882
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12819              		.loc 1 1915 13 is_stmt 0 view .LVU3883
+ 12820 00b0 806A     		ldr	r0, [r0, #40]
+ 12821              	.LVL960:
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12822              		.loc 1 1915 13 view .LVU3884
+ 12823 00b2 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 12824              	.LVL961:
+1916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12825              		.loc 1 1916 7 is_stmt 1 view .LVU3885
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12826              		.loc 1 1940 3 view .LVU3886
+ 12827 00b6 BAE7     		b	.L933
+ 12828              	.LVL962:
+ 12829              	.L930:
+1922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ 12830              		.loc 1 1922 7 view .LVU3887
+ 12831 00b8 0268     		ldr	r2, [r0]
+ 12832 00ba D368     		ldr	r3, [r2, #12]
+ 12833 00bc 23F40063 		bic	r3, r3, #2048
+ 12834 00c0 D360     		str	r3, [r2, #12]
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12835              		.loc 1 1923 7 view .LVU3888
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12836              		.loc 1 1923 13 is_stmt 0 view .LVU3889
+ 12837 00c2 C06A     		ldr	r0, [r0, #44]
+ 12838              	.LVL963:
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12839              		.loc 1 1923 13 view .LVU3890
+ 12840 00c4 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 12841              	.LVL964:
+1924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12842              		.loc 1 1924 7 is_stmt 1 view .LVU3891
+ARM GAS  /tmp/cc0wMqvE.s 			page 424
+
+
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12843              		.loc 1 1940 3 view .LVU3892
+ 12844 00c8 B1E7     		b	.L933
+ 12845              	.LVL965:
+ 12846              	.L928:
+1930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ 12847              		.loc 1 1930 7 view .LVU3893
+ 12848 00ca 0268     		ldr	r2, [r0]
+ 12849 00cc D368     		ldr	r3, [r2, #12]
+ 12850 00ce 23F48053 		bic	r3, r3, #4096
+ 12851 00d2 D360     		str	r3, [r2, #12]
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12852              		.loc 1 1931 7 view .LVU3894
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12853              		.loc 1 1931 13 is_stmt 0 view .LVU3895
+ 12854 00d4 006B     		ldr	r0, [r0, #48]
+ 12855              	.LVL966:
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 12856              		.loc 1 1931 13 view .LVU3896
+ 12857 00d6 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 12858              	.LVL967:
+1932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 12859              		.loc 1 1932 7 is_stmt 1 view .LVU3897
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12860              		.loc 1 1940 3 view .LVU3898
+ 12861 00da A8E7     		b	.L933
+ 12862              	.L937:
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12863              		.loc 1 1940 3 is_stmt 0 view .LVU3899
+ 12864 00dc 043C     		subs	r4, r4, #4
+ 12865              	.LVL968:
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12866              		.loc 1 1940 3 view .LVU3900
+ 12867 00de 0C2C     		cmp	r4, #12
+ 12868 00e0 1CD8     		bhi	.L938
+ 12869 00e2 DFE804F0 		tbb	[pc, r4]
+ 12870              	.L940:
+ 12871 00e6 07       		.byte	(.L943-.L940)/2
+ 12872 00e7 1B       		.byte	(.L938-.L940)/2
+ 12873 00e8 1B       		.byte	(.L938-.L940)/2
+ 12874 00e9 1B       		.byte	(.L938-.L940)/2
+ 12875 00ea 0C       		.byte	(.L942-.L940)/2
+ 12876 00eb 1B       		.byte	(.L938-.L940)/2
+ 12877 00ec 1B       		.byte	(.L938-.L940)/2
+ 12878 00ed 1B       		.byte	(.L938-.L940)/2
+ 12879 00ee 11       		.byte	(.L941-.L940)/2
+ 12880 00ef 1B       		.byte	(.L938-.L940)/2
+ 12881 00f0 1B       		.byte	(.L938-.L940)/2
+ 12882 00f1 1B       		.byte	(.L938-.L940)/2
+ 12883 00f2 16       		.byte	(.L939-.L940)/2
+ 12884 00f3 00       		.p2align 1
+ 12885              	.L943:
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12886              		.loc 1 1955 5 discriminator 3 view .LVU3901
+ 12887 00f4 0123     		movs	r3, #1
+ 12888 00f6 85F83F30 		strb	r3, [r5, #63]
+ 12889 00fa 0020     		movs	r0, #0
+ARM GAS  /tmp/cc0wMqvE.s 			page 425
+
+
+ 12890 00fc 14E0     		b	.L927
+ 12891              	.L942:
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12892              		.loc 1 1955 5 discriminator 6 view .LVU3902
+ 12893 00fe 0123     		movs	r3, #1
+ 12894 0100 85F84030 		strb	r3, [r5, #64]
+ 12895 0104 0020     		movs	r0, #0
+ 12896 0106 0FE0     		b	.L927
+ 12897              	.L941:
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12898              		.loc 1 1955 5 discriminator 9 view .LVU3903
+ 12899 0108 0123     		movs	r3, #1
+ 12900 010a 85F84130 		strb	r3, [r5, #65]
+ 12901 010e 0020     		movs	r0, #0
+ 12902 0110 0AE0     		b	.L927
+ 12903              	.L939:
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12904              		.loc 1 1955 5 discriminator 12 view .LVU3904
+ 12905 0112 0123     		movs	r3, #1
+ 12906 0114 85F84230 		strb	r3, [r5, #66]
+ 12907 0118 0020     		movs	r0, #0
+ 12908 011a 05E0     		b	.L927
+ 12909              	.L938:
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 12910              		.loc 1 1955 5 discriminator 13 view .LVU3905
+ 12911 011c 0123     		movs	r3, #1
+ 12912 011e 85F84330 		strb	r3, [r5, #67]
+ 12913 0122 0020     		movs	r0, #0
+ 12914 0124 00E0     		b	.L927
+ 12915              	.LVL969:
+ 12916              	.L944:
+1901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12917              		.loc 1 1901 3 view .LVU3906
+ 12918 0126 0120     		movs	r0, #1
+ 12919              	.LVL970:
+ 12920              	.L927:
+1959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 12921              		.loc 1 1959 3 is_stmt 1 view .LVU3907
+1960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12922              		.loc 1 1960 1 is_stmt 0 view .LVU3908
+ 12923 0128 38BD     		pop	{r3, r4, r5, pc}
+ 12924              	.LVL971:
+ 12925              	.L947:
+1960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12926              		.loc 1 1960 1 view .LVU3909
+ 12927 012a 00BF     		.align	2
+ 12928              	.L946:
+ 12929 012c 002C0140 		.word	1073818624
+ 12930              		.cfi_endproc
+ 12931              	.LFE358:
+ 12933              		.section	.text.HAL_TIM_IC_Start,"ax",%progbits
+ 12934              		.align	1
+ 12935              		.global	HAL_TIM_IC_Start
+ 12936              		.syntax unified
+ 12937              		.thumb
+ 12938              		.thumb_func
+ 12940              	HAL_TIM_IC_Start:
+ARM GAS  /tmp/cc0wMqvE.s 			page 426
+
+
+ 12941              	.LVL972:
+ 12942              	.LFB363:
+2136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 12943              		.loc 1 2136 1 is_stmt 1 view -0
+ 12944              		.cfi_startproc
+ 12945              		@ args = 0, pretend = 0, frame = 0
+ 12946              		@ frame_needed = 0, uses_anonymous_args = 0
+2136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 12947              		.loc 1 2136 1 is_stmt 0 view .LVU3911
+ 12948 0000 10B5     		push	{r4, lr}
+ 12949              	.LCFI97:
+ 12950              		.cfi_def_cfa_offset 8
+ 12951              		.cfi_offset 4, -8
+ 12952              		.cfi_offset 14, -4
+ 12953 0002 0446     		mov	r4, r0
+2137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ 12954              		.loc 1 2137 3 is_stmt 1 view .LVU3912
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12955              		.loc 1 2138 3 view .LVU3913
+ 12956 0004 1029     		cmp	r1, #16
+ 12957 0006 34D8     		bhi	.L949
+ 12958 0008 DFE801F0 		tbb	[pc, r1]
+ 12959              	.L951:
+ 12960 000c 09       		.byte	(.L955-.L951)/2
+ 12961 000d 33       		.byte	(.L949-.L951)/2
+ 12962 000e 33       		.byte	(.L949-.L951)/2
+ 12963 000f 33       		.byte	(.L949-.L951)/2
+ 12964 0010 23       		.byte	(.L954-.L951)/2
+ 12965 0011 33       		.byte	(.L949-.L951)/2
+ 12966 0012 33       		.byte	(.L949-.L951)/2
+ 12967 0013 33       		.byte	(.L949-.L951)/2
+ 12968 0014 27       		.byte	(.L953-.L951)/2
+ 12969 0015 33       		.byte	(.L949-.L951)/2
+ 12970 0016 33       		.byte	(.L949-.L951)/2
+ 12971 0017 33       		.byte	(.L949-.L951)/2
+ 12972 0018 2B       		.byte	(.L952-.L951)/2
+ 12973 0019 33       		.byte	(.L949-.L951)/2
+ 12974 001a 33       		.byte	(.L949-.L951)/2
+ 12975 001b 33       		.byte	(.L949-.L951)/2
+ 12976 001c 2F       		.byte	(.L950-.L951)/2
+ 12977 001d 00       		.p2align 1
+ 12978              	.L955:
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12979              		.loc 1 2138 47 is_stmt 0 discriminator 1 view .LVU3914
+ 12980 001e 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 12981              	.LVL973:
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12982              		.loc 1 2138 47 discriminator 1 view .LVU3915
+ 12983 0022 C0B2     		uxtb	r0, r0
+ 12984              	.L956:
+ 12985              	.LVL974:
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12986              		.loc 1 2139 3 is_stmt 1 discriminator 20 view .LVU3916
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12987              		.loc 1 2139 61 is_stmt 0 discriminator 20 view .LVU3917
+ 12988 0024 49BB     		cbnz	r1, .L957
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 427
+
+
+ 12989              		.loc 1 2139 61 discriminator 1 view .LVU3918
+ 12990 0026 94F84430 		ldrb	r3, [r4, #68]	@ zero_extendqisi2
+ 12991 002a DBB2     		uxtb	r3, r3
+ 12992              	.L958:
+ 12993              	.LVL975:
+2142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 12994              		.loc 1 2142 3 is_stmt 1 discriminator 12 view .LVU3919
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ 12995              		.loc 1 2145 3 discriminator 12 view .LVU3920
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ 12996              		.loc 1 2145 6 is_stmt 0 discriminator 12 view .LVU3921
+ 12997 002c 0128     		cmp	r0, #1
+ 12998 002e 40F08B80 		bne	.L975
+2146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 12999              		.loc 1 2146 7 view .LVU3922
+ 13000 0032 012B     		cmp	r3, #1
+ 13001 0034 40F08980 		bne	.L961
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13002              		.loc 1 2152 3 is_stmt 1 view .LVU3923
+ 13003 0038 1029     		cmp	r1, #16
+ 13004 003a 6BD8     		bhi	.L962
+ 13005 003c DFE801F0 		tbb	[pc, r1]
+ 13006              	.LVL976:
+ 13007              	.L964:
+ 13008 0040 2D       		.byte	(.L968-.L964)/2
+ 13009 0041 6A       		.byte	(.L962-.L964)/2
+ 13010 0042 6A       		.byte	(.L962-.L964)/2
+ 13011 0043 6A       		.byte	(.L962-.L964)/2
+ 13012 0044 33       		.byte	(.L967-.L964)/2
+ 13013 0045 6A       		.byte	(.L962-.L964)/2
+ 13014 0046 6A       		.byte	(.L962-.L964)/2
+ 13015 0047 6A       		.byte	(.L962-.L964)/2
+ 13016 0048 5E       		.byte	(.L966-.L964)/2
+ 13017 0049 6A       		.byte	(.L962-.L964)/2
+ 13018 004a 6A       		.byte	(.L962-.L964)/2
+ 13019 004b 6A       		.byte	(.L962-.L964)/2
+ 13020 004c 62       		.byte	(.L965-.L964)/2
+ 13021 004d 6A       		.byte	(.L962-.L964)/2
+ 13022 004e 6A       		.byte	(.L962-.L964)/2
+ 13023 004f 6A       		.byte	(.L962-.L964)/2
+ 13024 0050 66       		.byte	(.L963-.L964)/2
+ 13025 0051 00       		.p2align 1
+ 13026              	.L954:
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13027              		.loc 1 2138 47 is_stmt 0 discriminator 4 view .LVU3924
+ 13028 0052 90F83F00 		ldrb	r0, [r0, #63]	@ zero_extendqisi2
+ 13029              	.LVL977:
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13030              		.loc 1 2138 47 discriminator 4 view .LVU3925
+ 13031 0056 C0B2     		uxtb	r0, r0
+ 13032 0058 E4E7     		b	.L956
+ 13033              	.LVL978:
+ 13034              	.L953:
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13035              		.loc 1 2138 47 discriminator 7 view .LVU3926
+ 13036 005a 90F84000 		ldrb	r0, [r0, #64]	@ zero_extendqisi2
+ 13037              	.LVL979:
+ARM GAS  /tmp/cc0wMqvE.s 			page 428
+
+
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13038              		.loc 1 2138 47 discriminator 7 view .LVU3927
+ 13039 005e C0B2     		uxtb	r0, r0
+ 13040 0060 E0E7     		b	.L956
+ 13041              	.LVL980:
+ 13042              	.L952:
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13043              		.loc 1 2138 47 discriminator 10 view .LVU3928
+ 13044 0062 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 13045              	.LVL981:
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13046              		.loc 1 2138 47 discriminator 10 view .LVU3929
+ 13047 0066 C0B2     		uxtb	r0, r0
+ 13048 0068 DCE7     		b	.L956
+ 13049              	.LVL982:
+ 13050              	.L950:
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13051              		.loc 1 2138 47 discriminator 13 view .LVU3930
+ 13052 006a 90F84200 		ldrb	r0, [r0, #66]	@ zero_extendqisi2
+ 13053              	.LVL983:
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13054              		.loc 1 2138 47 discriminator 13 view .LVU3931
+ 13055 006e C0B2     		uxtb	r0, r0
+ 13056 0070 D8E7     		b	.L956
+ 13057              	.LVL984:
+ 13058              	.L949:
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13059              		.loc 1 2138 47 discriminator 14 view .LVU3932
+ 13060 0072 90F84300 		ldrb	r0, [r0, #67]	@ zero_extendqisi2
+ 13061              	.LVL985:
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13062              		.loc 1 2138 47 discriminator 14 view .LVU3933
+ 13063 0076 C0B2     		uxtb	r0, r0
+ 13064 0078 D4E7     		b	.L956
+ 13065              	.LVL986:
+ 13066              	.L957:
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13067              		.loc 1 2139 61 discriminator 2 view .LVU3934
+ 13068 007a 0429     		cmp	r1, #4
+ 13069 007c 05D0     		beq	.L979
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13070              		.loc 1 2139 61 discriminator 5 view .LVU3935
+ 13071 007e 0829     		cmp	r1, #8
+ 13072 0080 07D0     		beq	.L980
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13073              		.loc 1 2139 61 discriminator 8 view .LVU3936
+ 13074 0082 94F84730 		ldrb	r3, [r4, #71]	@ zero_extendqisi2
+ 13075 0086 DBB2     		uxtb	r3, r3
+ 13076 0088 D0E7     		b	.L958
+ 13077              	.L979:
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13078              		.loc 1 2139 61 discriminator 4 view .LVU3937
+ 13079 008a 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 13080 008e DBB2     		uxtb	r3, r3
+ 13081 0090 CCE7     		b	.L958
+ 13082              	.L980:
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 429
+
+
+ 13083              		.loc 1 2139 61 discriminator 7 view .LVU3938
+ 13084 0092 94F84630 		ldrb	r3, [r4, #70]	@ zero_extendqisi2
+ 13085 0096 DBB2     		uxtb	r3, r3
+ 13086 0098 C8E7     		b	.L958
+ 13087              	.LVL987:
+ 13088              	.L968:
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13089              		.loc 1 2152 3 view .LVU3939
+ 13090 009a 0223     		movs	r3, #2
+ 13091 009c 84F83E30 		strb	r3, [r4, #62]
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13092              		.loc 1 2153 3 is_stmt 1 view .LVU3940
+ 13093 00a0 84F84430 		strb	r3, [r4, #68]
+ 13094 00a4 09E0     		b	.L969
+ 13095              	.L967:
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13096              		.loc 1 2152 3 is_stmt 0 view .LVU3941
+ 13097 00a6 0223     		movs	r3, #2
+ 13098 00a8 84F83F30 		strb	r3, [r4, #63]
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13099              		.loc 1 2153 3 is_stmt 1 view .LVU3942
+ 13100              	.L970:
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13101              		.loc 1 2153 3 is_stmt 0 discriminator 2 view .LVU3943
+ 13102 00ac 0429     		cmp	r1, #4
+ 13103 00ae 35D0     		beq	.L981
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13104              		.loc 1 2153 3 discriminator 4 view .LVU3944
+ 13105 00b0 0829     		cmp	r1, #8
+ 13106 00b2 37D0     		beq	.L982
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13107              		.loc 1 2153 3 discriminator 7 view .LVU3945
+ 13108 00b4 0223     		movs	r3, #2
+ 13109 00b6 84F84730 		strb	r3, [r4, #71]
+ 13110              	.L969:
+2156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13111              		.loc 1 2156 3 is_stmt 1 view .LVU3946
+ 13112 00ba 0122     		movs	r2, #1
+ 13113 00bc 2068     		ldr	r0, [r4]
+ 13114              	.LVL988:
+2156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13115              		.loc 1 2156 3 is_stmt 0 view .LVU3947
+ 13116 00be FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 13117              	.LVL989:
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13118              		.loc 1 2159 3 is_stmt 1 view .LVU3948
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13119              		.loc 1 2159 7 is_stmt 0 view .LVU3949
+ 13120 00c2 2368     		ldr	r3, [r4]
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13121              		.loc 1 2159 6 view .LVU3950
+ 13122 00c4 234A     		ldr	r2, .L983
+ 13123 00c6 9342     		cmp	r3, r2
+ 13124 00c8 30D0     		beq	.L973
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13125              		.loc 1 2159 7 discriminator 1 view .LVU3951
+ 13126 00ca B3F1804F 		cmp	r3, #1073741824
+ARM GAS  /tmp/cc0wMqvE.s 			page 430
+
+
+ 13127 00ce 2DD0     		beq	.L973
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13128              		.loc 1 2159 7 discriminator 2 view .LVU3952
+ 13129 00d0 A2F59432 		sub	r2, r2, #75776
+ 13130 00d4 9342     		cmp	r3, r2
+ 13131 00d6 29D0     		beq	.L973
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13132              		.loc 1 2159 7 discriminator 3 view .LVU3953
+ 13133 00d8 02F58062 		add	r2, r2, #1024
+ 13134 00dc 9342     		cmp	r3, r2
+ 13135 00de 25D0     		beq	.L973
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13136              		.loc 1 2159 7 discriminator 4 view .LVU3954
+ 13137 00e0 02F59632 		add	r2, r2, #76800
+ 13138 00e4 9342     		cmp	r3, r2
+ 13139 00e6 21D0     		beq	.L973
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13140              		.loc 1 2159 7 discriminator 5 view .LVU3955
+ 13141 00e8 02F54062 		add	r2, r2, #3072
+ 13142 00ec 9342     		cmp	r3, r2
+ 13143 00ee 1DD0     		beq	.L973
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13144              		.loc 1 2169 5 is_stmt 1 view .LVU3956
+ 13145 00f0 1A68     		ldr	r2, [r3]
+ 13146 00f2 42F00102 		orr	r2, r2, #1
+ 13147 00f6 1A60     		str	r2, [r3]
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 13148              		.loc 1 2173 10 is_stmt 0 view .LVU3957
+ 13149 00f8 0020     		movs	r0, #0
+ 13150 00fa 26E0     		b	.L961
+ 13151              	.LVL990:
+ 13152              	.L966:
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13153              		.loc 1 2152 3 view .LVU3958
+ 13154 00fc 0223     		movs	r3, #2
+ 13155 00fe 84F84030 		strb	r3, [r4, #64]
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13156              		.loc 1 2153 3 is_stmt 1 view .LVU3959
+ 13157 0102 D3E7     		b	.L970
+ 13158              	.L965:
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13159              		.loc 1 2152 3 is_stmt 0 view .LVU3960
+ 13160 0104 0223     		movs	r3, #2
+ 13161 0106 84F84130 		strb	r3, [r4, #65]
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13162              		.loc 1 2153 3 is_stmt 1 view .LVU3961
+ 13163 010a CFE7     		b	.L970
+ 13164              	.L963:
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13165              		.loc 1 2152 3 is_stmt 0 view .LVU3962
+ 13166 010c 0223     		movs	r3, #2
+ 13167 010e 84F84230 		strb	r3, [r4, #66]
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13168              		.loc 1 2153 3 is_stmt 1 view .LVU3963
+ 13169 0112 CBE7     		b	.L970
+ 13170              	.L962:
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ARM GAS  /tmp/cc0wMqvE.s 			page 431
+
+
+ 13171              		.loc 1 2152 3 is_stmt 0 discriminator 13 view .LVU3964
+ 13172 0114 0223     		movs	r3, #2
+ 13173 0116 84F84330 		strb	r3, [r4, #67]
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13174              		.loc 1 2153 3 is_stmt 1 discriminator 13 view .LVU3965
+ 13175 011a C7E7     		b	.L970
+ 13176              	.L981:
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13177              		.loc 1 2153 3 is_stmt 0 discriminator 3 view .LVU3966
+ 13178 011c 0223     		movs	r3, #2
+ 13179 011e 84F84530 		strb	r3, [r4, #69]
+ 13180 0122 CAE7     		b	.L969
+ 13181              	.L982:
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13182              		.loc 1 2153 3 discriminator 6 view .LVU3967
+ 13183 0124 0223     		movs	r3, #2
+ 13184 0126 84F84630 		strb	r3, [r4, #70]
+ 13185 012a C6E7     		b	.L969
+ 13186              	.LVL991:
+ 13187              	.L973:
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 13188              		.loc 1 2161 5 is_stmt 1 view .LVU3968
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 13189              		.loc 1 2161 29 is_stmt 0 view .LVU3969
+ 13190 012c 9968     		ldr	r1, [r3, #8]
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 13191              		.loc 1 2161 13 view .LVU3970
+ 13192 012e 0A4A     		ldr	r2, .L983+4
+ 13193 0130 0A40     		ands	r2, r2, r1
+ 13194              	.LVL992:
+2162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 13195              		.loc 1 2162 5 is_stmt 1 view .LVU3971
+2162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 13196              		.loc 1 2162 8 is_stmt 0 view .LVU3972
+ 13197 0132 062A     		cmp	r2, #6
+ 13198 0134 0AD0     		beq	.L976
+2162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 13199              		.loc 1 2162 9 discriminator 1 view .LVU3973
+ 13200 0136 B2F5803F 		cmp	r2, #65536
+ 13201 013a 09D0     		beq	.L977
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 13202              		.loc 1 2164 7 is_stmt 1 view .LVU3974
+ 13203 013c 1A68     		ldr	r2, [r3]
+ 13204              	.LVL993:
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 13205              		.loc 1 2164 7 is_stmt 0 view .LVU3975
+ 13206 013e 42F00102 		orr	r2, r2, #1
+ 13207 0142 1A60     		str	r2, [r3]
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 13208              		.loc 1 2173 10 view .LVU3976
+ 13209 0144 0020     		movs	r0, #0
+ 13210 0146 00E0     		b	.L961
+ 13211              	.LVL994:
+ 13212              	.L975:
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13213              		.loc 1 2148 12 view .LVU3977
+ 13214 0148 0120     		movs	r0, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 432
+
+
+ 13215              	.LVL995:
+ 13216              	.L961:
+2174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13217              		.loc 1 2174 1 view .LVU3978
+ 13218 014a 10BD     		pop	{r4, pc}
+ 13219              	.LVL996:
+ 13220              	.L976:
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 13221              		.loc 1 2173 10 view .LVU3979
+ 13222 014c 0020     		movs	r0, #0
+ 13223 014e FCE7     		b	.L961
+ 13224              	.L977:
+ 13225 0150 0020     		movs	r0, #0
+ 13226 0152 FAE7     		b	.L961
+ 13227              	.L984:
+ 13228              		.align	2
+ 13229              	.L983:
+ 13230 0154 002C0140 		.word	1073818624
+ 13231 0158 07000100 		.word	65543
+ 13232              		.cfi_endproc
+ 13233              	.LFE363:
+ 13235              		.section	.text.HAL_TIM_IC_Stop,"ax",%progbits
+ 13236              		.align	1
+ 13237              		.global	HAL_TIM_IC_Stop
+ 13238              		.syntax unified
+ 13239              		.thumb
+ 13240              		.thumb_func
+ 13242              	HAL_TIM_IC_Stop:
+ 13243              	.LVL997:
+ 13244              	.LFB364:
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 13245              		.loc 1 2188 1 is_stmt 1 view -0
+ 13246              		.cfi_startproc
+ 13247              		@ args = 0, pretend = 0, frame = 0
+ 13248              		@ frame_needed = 0, uses_anonymous_args = 0
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 13249              		.loc 1 2188 1 is_stmt 0 view .LVU3981
+ 13250 0000 38B5     		push	{r3, r4, r5, lr}
+ 13251              	.LCFI98:
+ 13252              		.cfi_def_cfa_offset 16
+ 13253              		.cfi_offset 3, -16
+ 13254              		.cfi_offset 4, -12
+ 13255              		.cfi_offset 5, -8
+ 13256              		.cfi_offset 14, -4
+ 13257 0002 0446     		mov	r4, r0
+ 13258 0004 0D46     		mov	r5, r1
+2190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13259              		.loc 1 2190 3 is_stmt 1 view .LVU3982
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13260              		.loc 1 2193 3 view .LVU3983
+ 13261 0006 0022     		movs	r2, #0
+ 13262 0008 0068     		ldr	r0, [r0]
+ 13263              	.LVL998:
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13264              		.loc 1 2193 3 is_stmt 0 view .LVU3984
+ 13265 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 13266              	.LVL999:
+ARM GAS  /tmp/cc0wMqvE.s 			page 433
+
+
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13267              		.loc 1 2196 3 is_stmt 1 view .LVU3985
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13268              		.loc 1 2196 3 view .LVU3986
+ 13269 000e 2368     		ldr	r3, [r4]
+ 13270 0010 196A     		ldr	r1, [r3, #32]
+ 13271 0012 41F21112 		movw	r2, #4369
+ 13272 0016 1142     		tst	r1, r2
+ 13273 0018 08D1     		bne	.L986
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13274              		.loc 1 2196 3 discriminator 1 view .LVU3987
+ 13275 001a 196A     		ldr	r1, [r3, #32]
+ 13276 001c 44F24442 		movw	r2, #17476
+ 13277 0020 1142     		tst	r1, r2
+ 13278 0022 03D1     		bne	.L986
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13279              		.loc 1 2196 3 discriminator 3 view .LVU3988
+ 13280 0024 1A68     		ldr	r2, [r3]
+ 13281 0026 22F00102 		bic	r2, r2, #1
+ 13282 002a 1A60     		str	r2, [r3]
+ 13283              	.L986:
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13284              		.loc 1 2196 3 discriminator 5 view .LVU3989
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13285              		.loc 1 2199 3 discriminator 5 view .LVU3990
+ 13286 002c 35B9     		cbnz	r5, .L987
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13287              		.loc 1 2199 3 is_stmt 0 view .LVU3991
+ 13288 002e 0123     		movs	r3, #1
+ 13289 0030 84F83E30 		strb	r3, [r4, #62]
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13290              		.loc 1 2200 3 is_stmt 1 view .LVU3992
+ 13291 0034 84F84430 		strb	r3, [r4, #68]
+ 13292              	.L988:
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 13293              		.loc 1 2203 3 view .LVU3993
+2204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13294              		.loc 1 2204 1 is_stmt 0 view .LVU3994
+ 13295 0038 0020     		movs	r0, #0
+ 13296 003a 38BD     		pop	{r3, r4, r5, pc}
+ 13297              	.LVL1000:
+ 13298              	.L987:
+2204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13299              		.loc 1 2204 1 view .LVU3995
+ 13300 003c 2B1F     		subs	r3, r5, #4
+ 13301 003e 0C2B     		cmp	r3, #12
+ 13302 0040 1FD8     		bhi	.L989
+ 13303 0042 DFE803F0 		tbb	[pc, r3]
+ 13304              	.L991:
+ 13305 0046 07       		.byte	(.L994-.L991)/2
+ 13306 0047 1E       		.byte	(.L989-.L991)/2
+ 13307 0048 1E       		.byte	(.L989-.L991)/2
+ 13308 0049 1E       		.byte	(.L989-.L991)/2
+ 13309 004a 12       		.byte	(.L993-.L991)/2
+ 13310 004b 1E       		.byte	(.L989-.L991)/2
+ 13311 004c 1E       		.byte	(.L989-.L991)/2
+ 13312 004d 1E       		.byte	(.L989-.L991)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 434
+
+
+ 13313 004e 16       		.byte	(.L992-.L991)/2
+ 13314 004f 1E       		.byte	(.L989-.L991)/2
+ 13315 0050 1E       		.byte	(.L989-.L991)/2
+ 13316 0051 1E       		.byte	(.L989-.L991)/2
+ 13317 0052 1A       		.byte	(.L990-.L991)/2
+ 13318 0053 00       		.p2align 1
+ 13319              	.L994:
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13320              		.loc 1 2199 3 view .LVU3996
+ 13321 0054 0123     		movs	r3, #1
+ 13322 0056 84F83F30 		strb	r3, [r4, #63]
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13323              		.loc 1 2200 3 is_stmt 1 view .LVU3997
+ 13324              	.L995:
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13325              		.loc 1 2200 3 is_stmt 0 discriminator 2 view .LVU3998
+ 13326 005a 042D     		cmp	r5, #4
+ 13327 005c 15D0     		beq	.L999
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13328              		.loc 1 2200 3 discriminator 4 view .LVU3999
+ 13329 005e 082D     		cmp	r5, #8
+ 13330 0060 17D0     		beq	.L1000
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13331              		.loc 1 2200 3 discriminator 7 view .LVU4000
+ 13332 0062 0123     		movs	r3, #1
+ 13333 0064 84F84730 		strb	r3, [r4, #71]
+ 13334 0068 E6E7     		b	.L988
+ 13335              	.L993:
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13336              		.loc 1 2199 3 view .LVU4001
+ 13337 006a 0123     		movs	r3, #1
+ 13338 006c 84F84030 		strb	r3, [r4, #64]
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13339              		.loc 1 2200 3 is_stmt 1 view .LVU4002
+ 13340 0070 F3E7     		b	.L995
+ 13341              	.L992:
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13342              		.loc 1 2199 3 is_stmt 0 view .LVU4003
+ 13343 0072 0123     		movs	r3, #1
+ 13344 0074 84F84130 		strb	r3, [r4, #65]
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13345              		.loc 1 2200 3 is_stmt 1 view .LVU4004
+ 13346 0078 EFE7     		b	.L995
+ 13347              	.L990:
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13348              		.loc 1 2199 3 is_stmt 0 view .LVU4005
+ 13349 007a 0123     		movs	r3, #1
+ 13350 007c 84F84230 		strb	r3, [r4, #66]
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13351              		.loc 1 2200 3 is_stmt 1 view .LVU4006
+ 13352 0080 EBE7     		b	.L995
+ 13353              	.L989:
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13354              		.loc 1 2199 3 is_stmt 0 discriminator 13 view .LVU4007
+ 13355 0082 0123     		movs	r3, #1
+ 13356 0084 84F84330 		strb	r3, [r4, #67]
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 435
+
+
+ 13357              		.loc 1 2200 3 is_stmt 1 discriminator 13 view .LVU4008
+ 13358 0088 E7E7     		b	.L995
+ 13359              	.L999:
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13360              		.loc 1 2200 3 is_stmt 0 discriminator 3 view .LVU4009
+ 13361 008a 0123     		movs	r3, #1
+ 13362 008c 84F84530 		strb	r3, [r4, #69]
+ 13363 0090 D2E7     		b	.L988
+ 13364              	.L1000:
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13365              		.loc 1 2200 3 discriminator 6 view .LVU4010
+ 13366 0092 0123     		movs	r3, #1
+ 13367 0094 84F84630 		strb	r3, [r4, #70]
+ 13368 0098 CEE7     		b	.L988
+ 13369              		.cfi_endproc
+ 13370              	.LFE364:
+ 13372              		.section	.text.HAL_TIM_IC_Start_IT,"ax",%progbits
+ 13373              		.align	1
+ 13374              		.global	HAL_TIM_IC_Start_IT
+ 13375              		.syntax unified
+ 13376              		.thumb
+ 13377              		.thumb_func
+ 13379              	HAL_TIM_IC_Start_IT:
+ 13380              	.LVL1001:
+ 13381              	.LFB365:
+2218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 13382              		.loc 1 2218 1 is_stmt 1 view -0
+ 13383              		.cfi_startproc
+ 13384              		@ args = 0, pretend = 0, frame = 0
+ 13385              		@ frame_needed = 0, uses_anonymous_args = 0
+2218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 13386              		.loc 1 2218 1 is_stmt 0 view .LVU4012
+ 13387 0000 10B5     		push	{r4, lr}
+ 13388              	.LCFI99:
+ 13389              		.cfi_def_cfa_offset 8
+ 13390              		.cfi_offset 4, -8
+ 13391              		.cfi_offset 14, -4
+ 13392 0002 0446     		mov	r4, r0
+2219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 13393              		.loc 1 2219 3 is_stmt 1 view .LVU4013
+ 13394              	.LVL1002:
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13395              		.loc 1 2220 3 view .LVU4014
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13396              		.loc 1 2222 3 view .LVU4015
+ 13397 0004 1029     		cmp	r1, #16
+ 13398 0006 34D8     		bhi	.L1002
+ 13399 0008 DFE801F0 		tbb	[pc, r1]
+ 13400              	.L1004:
+ 13401 000c 09       		.byte	(.L1008-.L1004)/2
+ 13402 000d 33       		.byte	(.L1002-.L1004)/2
+ 13403 000e 33       		.byte	(.L1002-.L1004)/2
+ 13404 000f 33       		.byte	(.L1002-.L1004)/2
+ 13405 0010 23       		.byte	(.L1007-.L1004)/2
+ 13406 0011 33       		.byte	(.L1002-.L1004)/2
+ 13407 0012 33       		.byte	(.L1002-.L1004)/2
+ 13408 0013 33       		.byte	(.L1002-.L1004)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 436
+
+
+ 13409 0014 27       		.byte	(.L1006-.L1004)/2
+ 13410 0015 33       		.byte	(.L1002-.L1004)/2
+ 13411 0016 33       		.byte	(.L1002-.L1004)/2
+ 13412 0017 33       		.byte	(.L1002-.L1004)/2
+ 13413 0018 2B       		.byte	(.L1005-.L1004)/2
+ 13414 0019 33       		.byte	(.L1002-.L1004)/2
+ 13415 001a 33       		.byte	(.L1002-.L1004)/2
+ 13416 001b 33       		.byte	(.L1002-.L1004)/2
+ 13417 001c 2F       		.byte	(.L1003-.L1004)/2
+ 13418 001d 00       		.p2align 1
+ 13419              	.L1008:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13420              		.loc 1 2222 47 is_stmt 0 discriminator 1 view .LVU4016
+ 13421 001e 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 13422              	.LVL1003:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13423              		.loc 1 2222 47 discriminator 1 view .LVU4017
+ 13424 0022 C0B2     		uxtb	r0, r0
+ 13425              	.L1009:
+ 13426              	.LVL1004:
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13427              		.loc 1 2223 3 is_stmt 1 discriminator 20 view .LVU4018
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13428              		.loc 1 2223 61 is_stmt 0 discriminator 20 view .LVU4019
+ 13429 0024 49BB     		cbnz	r1, .L1010
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13430              		.loc 1 2223 61 discriminator 1 view .LVU4020
+ 13431 0026 94F84430 		ldrb	r3, [r4, #68]	@ zero_extendqisi2
+ 13432 002a DBB2     		uxtb	r3, r3
+ 13433              	.L1011:
+ 13434              	.LVL1005:
+2226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13435              		.loc 1 2226 3 is_stmt 1 discriminator 12 view .LVU4021
+2229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ 13436              		.loc 1 2229 3 discriminator 12 view .LVU4022
+2229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ 13437              		.loc 1 2229 6 is_stmt 0 discriminator 12 view .LVU4023
+ 13438 002c 0128     		cmp	r0, #1
+ 13439 002e 40F0AB80 		bne	.L1034
+2230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13440              		.loc 1 2230 7 view .LVU4024
+ 13441 0032 012B     		cmp	r3, #1
+ 13442 0034 40F0A980 		bne	.L1014
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13443              		.loc 1 2236 3 is_stmt 1 view .LVU4025
+ 13444 0038 1029     		cmp	r1, #16
+ 13445 003a 55D8     		bhi	.L1015
+ 13446 003c DFE801F0 		tbb	[pc, r1]
+ 13447              	.L1017:
+ 13448 0040 2D       		.byte	(.L1021-.L1017)/2
+ 13449 0041 54       		.byte	(.L1015-.L1017)/2
+ 13450 0042 54       		.byte	(.L1015-.L1017)/2
+ 13451 0043 54       		.byte	(.L1015-.L1017)/2
+ 13452 0044 33       		.byte	(.L1020-.L1017)/2
+ 13453 0045 54       		.byte	(.L1015-.L1017)/2
+ 13454 0046 54       		.byte	(.L1015-.L1017)/2
+ 13455 0047 54       		.byte	(.L1015-.L1017)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 437
+
+
+ 13456 0048 48       		.byte	(.L1019-.L1017)/2
+ 13457 0049 54       		.byte	(.L1015-.L1017)/2
+ 13458 004a 54       		.byte	(.L1015-.L1017)/2
+ 13459 004b 54       		.byte	(.L1015-.L1017)/2
+ 13460 004c 4C       		.byte	(.L1018-.L1017)/2
+ 13461 004d 54       		.byte	(.L1015-.L1017)/2
+ 13462 004e 54       		.byte	(.L1015-.L1017)/2
+ 13463 004f 54       		.byte	(.L1015-.L1017)/2
+ 13464 0050 50       		.byte	(.L1016-.L1017)/2
+ 13465              	.LVL1006:
+ 13466 0051 00       		.p2align 1
+ 13467              	.L1007:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13468              		.loc 1 2222 47 is_stmt 0 discriminator 4 view .LVU4026
+ 13469 0052 90F83F00 		ldrb	r0, [r0, #63]	@ zero_extendqisi2
+ 13470              	.LVL1007:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13471              		.loc 1 2222 47 discriminator 4 view .LVU4027
+ 13472 0056 C0B2     		uxtb	r0, r0
+ 13473 0058 E4E7     		b	.L1009
+ 13474              	.LVL1008:
+ 13475              	.L1006:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13476              		.loc 1 2222 47 discriminator 7 view .LVU4028
+ 13477 005a 90F84000 		ldrb	r0, [r0, #64]	@ zero_extendqisi2
+ 13478              	.LVL1009:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13479              		.loc 1 2222 47 discriminator 7 view .LVU4029
+ 13480 005e C0B2     		uxtb	r0, r0
+ 13481 0060 E0E7     		b	.L1009
+ 13482              	.LVL1010:
+ 13483              	.L1005:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13484              		.loc 1 2222 47 discriminator 10 view .LVU4030
+ 13485 0062 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 13486              	.LVL1011:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13487              		.loc 1 2222 47 discriminator 10 view .LVU4031
+ 13488 0066 C0B2     		uxtb	r0, r0
+ 13489 0068 DCE7     		b	.L1009
+ 13490              	.LVL1012:
+ 13491              	.L1003:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13492              		.loc 1 2222 47 discriminator 13 view .LVU4032
+ 13493 006a 90F84200 		ldrb	r0, [r0, #66]	@ zero_extendqisi2
+ 13494              	.LVL1013:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13495              		.loc 1 2222 47 discriminator 13 view .LVU4033
+ 13496 006e C0B2     		uxtb	r0, r0
+ 13497 0070 D8E7     		b	.L1009
+ 13498              	.LVL1014:
+ 13499              	.L1002:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13500              		.loc 1 2222 47 discriminator 14 view .LVU4034
+ 13501 0072 90F84300 		ldrb	r0, [r0, #67]	@ zero_extendqisi2
+ 13502              	.LVL1015:
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ARM GAS  /tmp/cc0wMqvE.s 			page 438
+
+
+ 13503              		.loc 1 2222 47 discriminator 14 view .LVU4035
+ 13504 0076 C0B2     		uxtb	r0, r0
+ 13505 0078 D4E7     		b	.L1009
+ 13506              	.LVL1016:
+ 13507              	.L1010:
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13508              		.loc 1 2223 61 discriminator 2 view .LVU4036
+ 13509 007a 0429     		cmp	r1, #4
+ 13510 007c 05D0     		beq	.L1041
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13511              		.loc 1 2223 61 discriminator 5 view .LVU4037
+ 13512 007e 0829     		cmp	r1, #8
+ 13513 0080 07D0     		beq	.L1042
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13514              		.loc 1 2223 61 discriminator 8 view .LVU4038
+ 13515 0082 94F84730 		ldrb	r3, [r4, #71]	@ zero_extendqisi2
+ 13516 0086 DBB2     		uxtb	r3, r3
+ 13517 0088 D0E7     		b	.L1011
+ 13518              	.L1041:
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13519              		.loc 1 2223 61 discriminator 4 view .LVU4039
+ 13520 008a 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 13521 008e DBB2     		uxtb	r3, r3
+ 13522 0090 CCE7     		b	.L1011
+ 13523              	.L1042:
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13524              		.loc 1 2223 61 discriminator 7 view .LVU4040
+ 13525 0092 94F84630 		ldrb	r3, [r4, #70]	@ zero_extendqisi2
+ 13526 0096 DBB2     		uxtb	r3, r3
+ 13527 0098 C8E7     		b	.L1011
+ 13528              	.LVL1017:
+ 13529              	.L1021:
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13530              		.loc 1 2236 3 view .LVU4041
+ 13531 009a 0222     		movs	r2, #2
+ 13532 009c 84F83E20 		strb	r2, [r4, #62]
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13533              		.loc 1 2237 3 is_stmt 1 view .LVU4042
+ 13534 00a0 84F84420 		strb	r2, [r4, #68]
+ 13535 00a4 09E0     		b	.L1022
+ 13536              	.L1020:
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13537              		.loc 1 2236 3 is_stmt 0 view .LVU4043
+ 13538 00a6 0222     		movs	r2, #2
+ 13539 00a8 84F83F20 		strb	r2, [r4, #63]
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13540              		.loc 1 2237 3 is_stmt 1 view .LVU4044
+ 13541              	.L1023:
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13542              		.loc 1 2237 3 is_stmt 0 discriminator 2 view .LVU4045
+ 13543 00ac 0429     		cmp	r1, #4
+ 13544 00ae 1FD0     		beq	.L1043
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13545              		.loc 1 2237 3 discriminator 4 view .LVU4046
+ 13546 00b0 0829     		cmp	r1, #8
+ 13547 00b2 46D0     		beq	.L1044
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 439
+
+
+ 13548              		.loc 1 2237 3 discriminator 7 view .LVU4047
+ 13549 00b4 0222     		movs	r2, #2
+ 13550 00b6 84F84720 		strb	r2, [r4, #71]
+ 13551              	.L1022:
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13552              		.loc 1 2239 3 is_stmt 1 view .LVU4048
+ 13553 00ba 0C29     		cmp	r1, #12
+ 13554 00bc 66D8     		bhi	.L1035
+ 13555 00be DFE801F0 		tbb	[pc, r1]
+ 13556              	.L1029:
+ 13557 00c2 49       		.byte	(.L1030-.L1029)/2
+ 13558 00c3 65       		.byte	(.L1035-.L1029)/2
+ 13559 00c4 65       		.byte	(.L1035-.L1029)/2
+ 13560 00c5 65       		.byte	(.L1035-.L1029)/2
+ 13561 00c6 1A       		.byte	(.L1025-.L1029)/2
+ 13562 00c7 65       		.byte	(.L1035-.L1029)/2
+ 13563 00c8 65       		.byte	(.L1035-.L1029)/2
+ 13564 00c9 65       		.byte	(.L1035-.L1029)/2
+ 13565 00ca 43       		.byte	(.L1027-.L1029)/2
+ 13566 00cb 65       		.byte	(.L1035-.L1029)/2
+ 13567 00cc 65       		.byte	(.L1035-.L1029)/2
+ 13568 00cd 65       		.byte	(.L1035-.L1029)/2
+ 13569 00ce 4F       		.byte	(.L1028-.L1029)/2
+ 13570 00cf 00       		.p2align 1
+ 13571              	.L1019:
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13572              		.loc 1 2236 3 is_stmt 0 view .LVU4049
+ 13573 00d0 0222     		movs	r2, #2
+ 13574 00d2 84F84020 		strb	r2, [r4, #64]
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13575              		.loc 1 2237 3 is_stmt 1 view .LVU4050
+ 13576 00d6 E9E7     		b	.L1023
+ 13577              	.L1018:
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13578              		.loc 1 2236 3 is_stmt 0 view .LVU4051
+ 13579 00d8 0222     		movs	r2, #2
+ 13580 00da 84F84120 		strb	r2, [r4, #65]
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13581              		.loc 1 2237 3 is_stmt 1 view .LVU4052
+ 13582 00de E5E7     		b	.L1023
+ 13583              	.L1016:
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13584              		.loc 1 2236 3 is_stmt 0 view .LVU4053
+ 13585 00e0 0222     		movs	r2, #2
+ 13586 00e2 84F84220 		strb	r2, [r4, #66]
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13587              		.loc 1 2237 3 is_stmt 1 view .LVU4054
+ 13588 00e6 E1E7     		b	.L1023
+ 13589              	.L1015:
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13590              		.loc 1 2236 3 is_stmt 0 discriminator 13 view .LVU4055
+ 13591 00e8 0222     		movs	r2, #2
+ 13592 00ea 84F84320 		strb	r2, [r4, #67]
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13593              		.loc 1 2237 3 is_stmt 1 discriminator 13 view .LVU4056
+ 13594 00ee DDE7     		b	.L1023
+ 13595              	.L1043:
+ARM GAS  /tmp/cc0wMqvE.s 			page 440
+
+
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13596              		.loc 1 2237 3 is_stmt 0 view .LVU4057
+ 13597 00f0 0223     		movs	r3, #2
+ 13598              	.LVL1018:
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13599              		.loc 1 2237 3 view .LVU4058
+ 13600 00f2 84F84530 		strb	r3, [r4, #69]
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13601              		.loc 1 2239 3 is_stmt 1 view .LVU4059
+ 13602              	.L1025:
+2251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 13603              		.loc 1 2251 7 view .LVU4060
+ 13604 00f6 2268     		ldr	r2, [r4]
+ 13605 00f8 D368     		ldr	r3, [r2, #12]
+ 13606 00fa 43F00403 		orr	r3, r3, #4
+ 13607 00fe D360     		str	r3, [r2, #12]
+2252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 13608              		.loc 1 2252 7 view .LVU4061
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13609              		.loc 1 2274 3 view .LVU4062
+ 13610              	.L1031:
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13611              		.loc 1 2277 5 view .LVU4063
+ 13612 0100 0122     		movs	r2, #1
+ 13613 0102 2068     		ldr	r0, [r4]
+ 13614              	.LVL1019:
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13615              		.loc 1 2277 5 is_stmt 0 view .LVU4064
+ 13616 0104 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 13617              	.LVL1020:
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 13618              		.loc 1 2280 5 is_stmt 1 view .LVU4065
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 13619              		.loc 1 2280 9 is_stmt 0 view .LVU4066
+ 13620 0108 2368     		ldr	r3, [r4]
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 13621              		.loc 1 2280 8 view .LVU4067
+ 13622 010a 234A     		ldr	r2, .L1045
+ 13623 010c 9342     		cmp	r3, r2
+ 13624 010e 2DD0     		beq	.L1032
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 13625              		.loc 1 2280 9 discriminator 1 view .LVU4068
+ 13626 0110 B3F1804F 		cmp	r3, #1073741824
+ 13627 0114 2AD0     		beq	.L1032
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 13628              		.loc 1 2280 9 discriminator 2 view .LVU4069
+ 13629 0116 A2F59432 		sub	r2, r2, #75776
+ 13630 011a 9342     		cmp	r3, r2
+ 13631 011c 26D0     		beq	.L1032
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 13632              		.loc 1 2280 9 discriminator 3 view .LVU4070
+ 13633 011e 02F58062 		add	r2, r2, #1024
+ 13634 0122 9342     		cmp	r3, r2
+ 13635 0124 22D0     		beq	.L1032
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 13636              		.loc 1 2280 9 discriminator 4 view .LVU4071
+ 13637 0126 02F59632 		add	r2, r2, #76800
+ARM GAS  /tmp/cc0wMqvE.s 			page 441
+
+
+ 13638 012a 9342     		cmp	r3, r2
+ 13639 012c 1ED0     		beq	.L1032
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 13640              		.loc 1 2280 9 discriminator 5 view .LVU4072
+ 13641 012e 02F54062 		add	r2, r2, #3072
+ 13642 0132 9342     		cmp	r3, r2
+ 13643 0134 1AD0     		beq	.L1032
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 13644              		.loc 1 2290 7 is_stmt 1 view .LVU4073
+ 13645 0136 1A68     		ldr	r2, [r3]
+ 13646 0138 42F00102 		orr	r2, r2, #1
+ 13647 013c 1A60     		str	r2, [r3]
+ 13648 013e 0020     		movs	r0, #0
+ 13649 0140 23E0     		b	.L1014
+ 13650              	.LVL1021:
+ 13651              	.L1044:
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13652              		.loc 1 2237 3 is_stmt 0 view .LVU4074
+ 13653 0142 0223     		movs	r3, #2
+ 13654              	.LVL1022:
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13655              		.loc 1 2237 3 view .LVU4075
+ 13656 0144 84F84630 		strb	r3, [r4, #70]
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13657              		.loc 1 2239 3 is_stmt 1 view .LVU4076
+ 13658              	.L1027:
+2258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 13659              		.loc 1 2258 7 view .LVU4077
+ 13660 0148 2268     		ldr	r2, [r4]
+ 13661 014a D368     		ldr	r3, [r2, #12]
+ 13662 014c 43F00803 		orr	r3, r3, #8
+ 13663 0150 D360     		str	r3, [r2, #12]
+2259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 13664              		.loc 1 2259 7 view .LVU4078
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13665              		.loc 1 2274 3 view .LVU4079
+ 13666 0152 D5E7     		b	.L1031
+ 13667              	.LVL1023:
+ 13668              	.L1030:
+2244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 13669              		.loc 1 2244 7 view .LVU4080
+ 13670 0154 2268     		ldr	r2, [r4]
+ 13671 0156 D368     		ldr	r3, [r2, #12]
+ 13672              	.LVL1024:
+2244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 13673              		.loc 1 2244 7 is_stmt 0 view .LVU4081
+ 13674 0158 43F00203 		orr	r3, r3, #2
+ 13675 015c D360     		str	r3, [r2, #12]
+2245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 13676              		.loc 1 2245 7 is_stmt 1 view .LVU4082
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13677              		.loc 1 2274 3 view .LVU4083
+ 13678 015e CFE7     		b	.L1031
+ 13679              	.LVL1025:
+ 13680              	.L1028:
+2265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 13681              		.loc 1 2265 7 view .LVU4084
+ARM GAS  /tmp/cc0wMqvE.s 			page 442
+
+
+ 13682 0160 2268     		ldr	r2, [r4]
+ 13683 0162 D368     		ldr	r3, [r2, #12]
+ 13684              	.LVL1026:
+2265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 13685              		.loc 1 2265 7 is_stmt 0 view .LVU4085
+ 13686 0164 43F01003 		orr	r3, r3, #16
+ 13687 0168 D360     		str	r3, [r2, #12]
+2266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 13688              		.loc 1 2266 7 is_stmt 1 view .LVU4086
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13689              		.loc 1 2274 3 view .LVU4087
+ 13690 016a C9E7     		b	.L1031
+ 13691              	.LVL1027:
+ 13692              	.L1032:
+2282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 13693              		.loc 1 2282 7 view .LVU4088
+2282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 13694              		.loc 1 2282 31 is_stmt 0 view .LVU4089
+ 13695 016c 9968     		ldr	r1, [r3, #8]
+2282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 13696              		.loc 1 2282 15 view .LVU4090
+ 13697 016e 0B4A     		ldr	r2, .L1045+4
+ 13698 0170 0A40     		ands	r2, r2, r1
+ 13699              	.LVL1028:
+2283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 13700              		.loc 1 2283 7 is_stmt 1 view .LVU4091
+2283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 13701              		.loc 1 2283 10 is_stmt 0 view .LVU4092
+ 13702 0172 062A     		cmp	r2, #6
+ 13703 0174 0CD0     		beq	.L1036
+2283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 13704              		.loc 1 2283 11 discriminator 1 view .LVU4093
+ 13705 0176 B2F5803F 		cmp	r2, #65536
+ 13706 017a 0BD0     		beq	.L1037
+2285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 13707              		.loc 1 2285 9 is_stmt 1 view .LVU4094
+ 13708 017c 1A68     		ldr	r2, [r3]
+ 13709              	.LVL1029:
+2285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 13710              		.loc 1 2285 9 is_stmt 0 view .LVU4095
+ 13711 017e 42F00102 		orr	r2, r2, #1
+ 13712 0182 1A60     		str	r2, [r3]
+ 13713 0184 0020     		movs	r0, #0
+ 13714 0186 00E0     		b	.L1014
+ 13715              	.LVL1030:
+ 13716              	.L1034:
+2232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13717              		.loc 1 2232 12 view .LVU4096
+ 13718 0188 0120     		movs	r0, #1
+ 13719              	.LVL1031:
+ 13720              	.L1014:
+2296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13721              		.loc 1 2296 1 view .LVU4097
+ 13722 018a 10BD     		pop	{r4, pc}
+ 13723              	.LVL1032:
+ 13724              	.L1035:
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 443
+
+
+ 13725              		.loc 1 2239 3 view .LVU4098
+ 13726 018c 1846     		mov	r0, r3
+ 13727              	.LVL1033:
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13728              		.loc 1 2239 3 view .LVU4099
+ 13729 018e FCE7     		b	.L1014
+ 13730              	.LVL1034:
+ 13731              	.L1036:
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13732              		.loc 1 2239 3 view .LVU4100
+ 13733 0190 0020     		movs	r0, #0
+ 13734 0192 FAE7     		b	.L1014
+ 13735              	.L1037:
+ 13736 0194 0020     		movs	r0, #0
+ 13737 0196 F8E7     		b	.L1014
+ 13738              	.L1046:
+ 13739              		.align	2
+ 13740              	.L1045:
+ 13741 0198 002C0140 		.word	1073818624
+ 13742 019c 07000100 		.word	65543
+ 13743              		.cfi_endproc
+ 13744              	.LFE365:
+ 13746              		.section	.text.HAL_TIM_IC_Stop_IT,"ax",%progbits
+ 13747              		.align	1
+ 13748              		.global	HAL_TIM_IC_Stop_IT
+ 13749              		.syntax unified
+ 13750              		.thumb
+ 13751              		.thumb_func
+ 13753              	HAL_TIM_IC_Stop_IT:
+ 13754              	.LVL1035:
+ 13755              	.LFB366:
+2310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 13756              		.loc 1 2310 1 is_stmt 1 view -0
+ 13757              		.cfi_startproc
+ 13758              		@ args = 0, pretend = 0, frame = 0
+ 13759              		@ frame_needed = 0, uses_anonymous_args = 0
+2310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 13760              		.loc 1 2310 1 is_stmt 0 view .LVU4102
+ 13761 0000 38B5     		push	{r3, r4, r5, lr}
+ 13762              	.LCFI100:
+ 13763              		.cfi_def_cfa_offset 16
+ 13764              		.cfi_offset 3, -16
+ 13765              		.cfi_offset 4, -12
+ 13766              		.cfi_offset 5, -8
+ 13767              		.cfi_offset 14, -4
+ 13768 0002 0546     		mov	r5, r0
+ 13769 0004 0C46     		mov	r4, r1
+2311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13770              		.loc 1 2311 3 is_stmt 1 view .LVU4103
+ 13771              	.LVL1036:
+2314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13772              		.loc 1 2314 3 view .LVU4104
+2316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13773              		.loc 1 2316 3 view .LVU4105
+ 13774 0006 0C29     		cmp	r1, #12
+ 13775 0008 6DD8     		bhi	.L1066
+ 13776 000a DFE801F0 		tbb	[pc, r1]
+ARM GAS  /tmp/cc0wMqvE.s 			page 444
+
+
+ 13777              	.L1050:
+ 13778 000e 07       		.byte	(.L1053-.L1050)/2
+ 13779 000f 6C       		.byte	(.L1066-.L1050)/2
+ 13780 0010 6C       		.byte	(.L1066-.L1050)/2
+ 13781 0011 6C       		.byte	(.L1066-.L1050)/2
+ 13782 0012 28       		.byte	(.L1052-.L1050)/2
+ 13783 0013 6C       		.byte	(.L1066-.L1050)/2
+ 13784 0014 6C       		.byte	(.L1066-.L1050)/2
+ 13785 0015 6C       		.byte	(.L1066-.L1050)/2
+ 13786 0016 2E       		.byte	(.L1051-.L1050)/2
+ 13787 0017 6C       		.byte	(.L1066-.L1050)/2
+ 13788 0018 6C       		.byte	(.L1066-.L1050)/2
+ 13789 0019 6C       		.byte	(.L1066-.L1050)/2
+ 13790 001a 34       		.byte	(.L1049-.L1050)/2
+ 13791 001b 00       		.p2align 1
+ 13792              	.L1053:
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 13793              		.loc 1 2321 7 view .LVU4106
+ 13794 001c 0268     		ldr	r2, [r0]
+ 13795 001e D368     		ldr	r3, [r2, #12]
+ 13796 0020 23F00203 		bic	r3, r3, #2
+ 13797 0024 D360     		str	r3, [r2, #12]
+2322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 13798              		.loc 1 2322 7 view .LVU4107
+2351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13799              		.loc 1 2351 3 view .LVU4108
+ 13800              	.L1054:
+2354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13801              		.loc 1 2354 5 view .LVU4109
+ 13802 0026 0022     		movs	r2, #0
+ 13803 0028 2146     		mov	r1, r4
+ 13804              	.LVL1037:
+2354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13805              		.loc 1 2354 5 is_stmt 0 view .LVU4110
+ 13806 002a 2868     		ldr	r0, [r5]
+ 13807              	.LVL1038:
+2354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13808              		.loc 1 2354 5 view .LVU4111
+ 13809 002c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 13810              	.LVL1039:
+2357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13811              		.loc 1 2357 5 is_stmt 1 view .LVU4112
+2357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13812              		.loc 1 2357 5 view .LVU4113
+ 13813 0030 2B68     		ldr	r3, [r5]
+ 13814 0032 196A     		ldr	r1, [r3, #32]
+ 13815 0034 41F21112 		movw	r2, #4369
+ 13816 0038 1142     		tst	r1, r2
+ 13817 003a 08D1     		bne	.L1055
+2357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13818              		.loc 1 2357 5 discriminator 1 view .LVU4114
+ 13819 003c 196A     		ldr	r1, [r3, #32]
+ 13820 003e 44F24442 		movw	r2, #17476
+ 13821 0042 1142     		tst	r1, r2
+ 13822 0044 03D1     		bne	.L1055
+2357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13823              		.loc 1 2357 5 discriminator 3 view .LVU4115
+ARM GAS  /tmp/cc0wMqvE.s 			page 445
+
+
+ 13824 0046 1A68     		ldr	r2, [r3]
+ 13825 0048 22F00102 		bic	r2, r2, #1
+ 13826 004c 1A60     		str	r2, [r3]
+ 13827              	.L1055:
+2357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13828              		.loc 1 2357 5 discriminator 5 view .LVU4116
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13829              		.loc 1 2360 5 discriminator 5 view .LVU4117
+ 13830 004e C4B9     		cbnz	r4, .L1056
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13831              		.loc 1 2360 5 is_stmt 0 view .LVU4118
+ 13832 0050 0123     		movs	r3, #1
+ 13833 0052 85F83E30 		strb	r3, [r5, #62]
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13834              		.loc 1 2361 5 is_stmt 1 view .LVU4119
+ 13835 0056 85F84430 		strb	r3, [r5, #68]
+ 13836 005a 0020     		movs	r0, #0
+ 13837 005c 44E0     		b	.L1048
+ 13838              	.LVL1040:
+ 13839              	.L1052:
+2328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 13840              		.loc 1 2328 7 view .LVU4120
+ 13841 005e 0268     		ldr	r2, [r0]
+ 13842 0060 D368     		ldr	r3, [r2, #12]
+ 13843 0062 23F00403 		bic	r3, r3, #4
+ 13844 0066 D360     		str	r3, [r2, #12]
+2329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 13845              		.loc 1 2329 7 view .LVU4121
+2351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13846              		.loc 1 2351 3 view .LVU4122
+ 13847 0068 DDE7     		b	.L1054
+ 13848              	.L1051:
+2335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 13849              		.loc 1 2335 7 view .LVU4123
+ 13850 006a 0268     		ldr	r2, [r0]
+ 13851 006c D368     		ldr	r3, [r2, #12]
+ 13852 006e 23F00803 		bic	r3, r3, #8
+ 13853 0072 D360     		str	r3, [r2, #12]
+2336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 13854              		.loc 1 2336 7 view .LVU4124
+2351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13855              		.loc 1 2351 3 view .LVU4125
+ 13856 0074 D7E7     		b	.L1054
+ 13857              	.L1049:
+2342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 13858              		.loc 1 2342 7 view .LVU4126
+ 13859 0076 0268     		ldr	r2, [r0]
+ 13860 0078 D368     		ldr	r3, [r2, #12]
+ 13861 007a 23F01003 		bic	r3, r3, #16
+ 13862 007e D360     		str	r3, [r2, #12]
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 13863              		.loc 1 2343 7 view .LVU4127
+2351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13864              		.loc 1 2351 3 view .LVU4128
+ 13865 0080 D1E7     		b	.L1054
+ 13866              	.LVL1041:
+ 13867              	.L1056:
+ARM GAS  /tmp/cc0wMqvE.s 			page 446
+
+
+2351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13868              		.loc 1 2351 3 is_stmt 0 view .LVU4129
+ 13869 0082 231F     		subs	r3, r4, #4
+ 13870 0084 0C2B     		cmp	r3, #12
+ 13871 0086 20D8     		bhi	.L1057
+ 13872 0088 DFE803F0 		tbb	[pc, r3]
+ 13873              	.L1059:
+ 13874 008c 07       		.byte	(.L1062-.L1059)/2
+ 13875 008d 1F       		.byte	(.L1057-.L1059)/2
+ 13876 008e 1F       		.byte	(.L1057-.L1059)/2
+ 13877 008f 1F       		.byte	(.L1057-.L1059)/2
+ 13878 0090 13       		.byte	(.L1061-.L1059)/2
+ 13879 0091 1F       		.byte	(.L1057-.L1059)/2
+ 13880 0092 1F       		.byte	(.L1057-.L1059)/2
+ 13881 0093 1F       		.byte	(.L1057-.L1059)/2
+ 13882 0094 17       		.byte	(.L1060-.L1059)/2
+ 13883 0095 1F       		.byte	(.L1057-.L1059)/2
+ 13884 0096 1F       		.byte	(.L1057-.L1059)/2
+ 13885 0097 1F       		.byte	(.L1057-.L1059)/2
+ 13886 0098 1B       		.byte	(.L1058-.L1059)/2
+ 13887 0099 00       		.p2align 1
+ 13888              	.L1062:
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13889              		.loc 1 2360 5 view .LVU4130
+ 13890 009a 0123     		movs	r3, #1
+ 13891 009c 85F83F30 		strb	r3, [r5, #63]
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13892              		.loc 1 2361 5 is_stmt 1 view .LVU4131
+ 13893              	.L1063:
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13894              		.loc 1 2361 5 is_stmt 0 discriminator 2 view .LVU4132
+ 13895 00a0 042C     		cmp	r4, #4
+ 13896 00a2 16D0     		beq	.L1068
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13897              		.loc 1 2361 5 discriminator 4 view .LVU4133
+ 13898 00a4 082C     		cmp	r4, #8
+ 13899 00a6 19D0     		beq	.L1069
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13900              		.loc 1 2361 5 discriminator 7 view .LVU4134
+ 13901 00a8 0123     		movs	r3, #1
+ 13902 00aa 85F84730 		strb	r3, [r5, #71]
+ 13903 00ae 0020     		movs	r0, #0
+ 13904 00b0 1AE0     		b	.L1048
+ 13905              	.L1061:
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13906              		.loc 1 2360 5 view .LVU4135
+ 13907 00b2 0123     		movs	r3, #1
+ 13908 00b4 85F84030 		strb	r3, [r5, #64]
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13909              		.loc 1 2361 5 is_stmt 1 view .LVU4136
+ 13910 00b8 F2E7     		b	.L1063
+ 13911              	.L1060:
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13912              		.loc 1 2360 5 is_stmt 0 view .LVU4137
+ 13913 00ba 0123     		movs	r3, #1
+ 13914 00bc 85F84130 		strb	r3, [r5, #65]
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ARM GAS  /tmp/cc0wMqvE.s 			page 447
+
+
+ 13915              		.loc 1 2361 5 is_stmt 1 view .LVU4138
+ 13916 00c0 EEE7     		b	.L1063
+ 13917              	.L1058:
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13918              		.loc 1 2360 5 is_stmt 0 view .LVU4139
+ 13919 00c2 0123     		movs	r3, #1
+ 13920 00c4 85F84230 		strb	r3, [r5, #66]
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13921              		.loc 1 2361 5 is_stmt 1 view .LVU4140
+ 13922 00c8 EAE7     		b	.L1063
+ 13923              	.L1057:
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13924              		.loc 1 2360 5 is_stmt 0 discriminator 13 view .LVU4141
+ 13925 00ca 0123     		movs	r3, #1
+ 13926 00cc 85F84330 		strb	r3, [r5, #67]
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13927              		.loc 1 2361 5 is_stmt 1 discriminator 13 view .LVU4142
+ 13928 00d0 E6E7     		b	.L1063
+ 13929              	.L1068:
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13930              		.loc 1 2361 5 is_stmt 0 discriminator 3 view .LVU4143
+ 13931 00d2 0123     		movs	r3, #1
+ 13932 00d4 85F84530 		strb	r3, [r5, #69]
+ 13933 00d8 0020     		movs	r0, #0
+ 13934 00da 05E0     		b	.L1048
+ 13935              	.L1069:
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 13936              		.loc 1 2361 5 discriminator 6 view .LVU4144
+ 13937 00dc 0123     		movs	r3, #1
+ 13938 00de 85F84630 		strb	r3, [r5, #70]
+ 13939 00e2 0020     		movs	r0, #0
+ 13940 00e4 00E0     		b	.L1048
+ 13941              	.LVL1042:
+ 13942              	.L1066:
+2316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 13943              		.loc 1 2316 3 view .LVU4145
+ 13944 00e6 0120     		movs	r0, #1
+ 13945              	.LVL1043:
+ 13946              	.L1048:
+2365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 13947              		.loc 1 2365 3 is_stmt 1 view .LVU4146
+2366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13948              		.loc 1 2366 1 is_stmt 0 view .LVU4147
+ 13949 00e8 38BD     		pop	{r3, r4, r5, pc}
+2366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13950              		.loc 1 2366 1 view .LVU4148
+ 13951              		.cfi_endproc
+ 13952              	.LFE366:
+ 13954              		.section	.text.HAL_TIM_IC_Start_DMA,"ax",%progbits
+ 13955              		.align	1
+ 13956              		.global	HAL_TIM_IC_Start_DMA
+ 13957              		.syntax unified
+ 13958              		.thumb
+ 13959              		.thumb_func
+ 13961              	HAL_TIM_IC_Start_DMA:
+ 13962              	.LVL1044:
+ 13963              	.LFB367:
+ARM GAS  /tmp/cc0wMqvE.s 			page 448
+
+
+2382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 13964              		.loc 1 2382 1 is_stmt 1 view -0
+ 13965              		.cfi_startproc
+ 13966              		@ args = 0, pretend = 0, frame = 0
+ 13967              		@ frame_needed = 0, uses_anonymous_args = 0
+2382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 13968              		.loc 1 2382 1 is_stmt 0 view .LVU4150
+ 13969 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 13970              	.LCFI101:
+ 13971              		.cfi_def_cfa_offset 24
+ 13972              		.cfi_offset 4, -24
+ 13973              		.cfi_offset 5, -20
+ 13974              		.cfi_offset 6, -16
+ 13975              		.cfi_offset 7, -12
+ 13976              		.cfi_offset 8, -8
+ 13977              		.cfi_offset 14, -4
+ 13978 0004 0546     		mov	r5, r0
+ 13979 0006 0C46     		mov	r4, r1
+ 13980 0008 1646     		mov	r6, r2
+ 13981 000a 1F46     		mov	r7, r3
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 13982              		.loc 1 2383 3 is_stmt 1 view .LVU4151
+ 13983              	.LVL1045:
+2384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 13984              		.loc 1 2384 3 view .LVU4152
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13985              		.loc 1 2386 3 view .LVU4153
+ 13986 000c 1029     		cmp	r1, #16
+ 13987 000e 3ED8     		bhi	.L1071
+ 13988 0010 DFE801F0 		tbb	[pc, r1]
+ 13989              	.LVL1046:
+ 13990              	.L1073:
+ 13991 0014 09       		.byte	(.L1077-.L1073)/2
+ 13992 0015 3D       		.byte	(.L1071-.L1073)/2
+ 13993 0016 3D       		.byte	(.L1071-.L1073)/2
+ 13994 0017 3D       		.byte	(.L1071-.L1073)/2
+ 13995 0018 2D       		.byte	(.L1076-.L1073)/2
+ 13996 0019 3D       		.byte	(.L1071-.L1073)/2
+ 13997 001a 3D       		.byte	(.L1071-.L1073)/2
+ 13998 001b 3D       		.byte	(.L1071-.L1073)/2
+ 13999 001c 31       		.byte	(.L1075-.L1073)/2
+ 14000 001d 3D       		.byte	(.L1071-.L1073)/2
+ 14001 001e 3D       		.byte	(.L1071-.L1073)/2
+ 14002 001f 3D       		.byte	(.L1071-.L1073)/2
+ 14003 0020 35       		.byte	(.L1074-.L1073)/2
+ 14004 0021 3D       		.byte	(.L1071-.L1073)/2
+ 14005 0022 3D       		.byte	(.L1071-.L1073)/2
+ 14006 0023 3D       		.byte	(.L1071-.L1073)/2
+ 14007 0024 39       		.byte	(.L1072-.L1073)/2
+ 14008 0025 00       		.p2align 1
+ 14009              	.L1077:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14010              		.loc 1 2386 47 is_stmt 0 discriminator 1 view .LVU4154
+ 14011 0026 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 14012              	.LVL1047:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14013              		.loc 1 2386 47 discriminator 1 view .LVU4155
+ARM GAS  /tmp/cc0wMqvE.s 			page 449
+
+
+ 14014 002a C0B2     		uxtb	r0, r0
+ 14015              	.LVL1048:
+ 14016              	.L1078:
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14017              		.loc 1 2387 3 is_stmt 1 discriminator 20 view .LVU4156
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14018              		.loc 1 2387 61 is_stmt 0 discriminator 20 view .LVU4157
+ 14019 002c 9CBB     		cbnz	r4, .L1079
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14020              		.loc 1 2387 61 discriminator 1 view .LVU4158
+ 14021 002e 95F84480 		ldrb	r8, [r5, #68]	@ zero_extendqisi2
+ 14022 0032 5FFA88F8 		uxtb	r8, r8
+ 14023              	.L1080:
+ 14024              	.LVL1049:
+2390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ 14025              		.loc 1 2390 3 is_stmt 1 discriminator 12 view .LVU4159
+2391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14026              		.loc 1 2391 3 discriminator 12 view .LVU4160
+2394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 14027              		.loc 1 2394 3 discriminator 12 view .LVU4161
+2394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 14028              		.loc 1 2394 6 is_stmt 0 discriminator 12 view .LVU4162
+ 14029 0036 0228     		cmp	r0, #2
+ 14030 0038 00F00C81 		beq	.L1083
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14031              		.loc 1 2395 7 view .LVU4163
+ 14032 003c B8F1020F 		cmp	r8, #2
+ 14033 0040 00F00581 		beq	.L1104
+2399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+ 14034              		.loc 1 2399 8 is_stmt 1 view .LVU4164
+2399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+ 14035              		.loc 1 2399 11 is_stmt 0 view .LVU4165
+ 14036 0044 0128     		cmp	r0, #1
+ 14037 0046 40F00481 		bne	.L1105
+2400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14038              		.loc 1 2400 12 view .LVU4166
+ 14039 004a B8F1010F 		cmp	r8, #1
+ 14040 004e 40F00181 		bne	.L1083
+2402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 14041              		.loc 1 2402 5 is_stmt 1 view .LVU4167
+2402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 14042              		.loc 1 2402 8 is_stmt 0 view .LVU4168
+ 14043 0052 9EB3     		cbz	r6, .L1115
+ 14044              	.L1084:
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14045              		.loc 1 2408 7 is_stmt 1 view .LVU4169
+ 14046 0054 102C     		cmp	r4, #16
+ 14047 0056 61D8     		bhi	.L1085
+ 14048 0058 DFE804F0 		tbb	[pc, r4]
+ 14049              	.L1087:
+ 14050 005c 34       		.byte	(.L1091-.L1087)/2
+ 14051 005d 60       		.byte	(.L1085-.L1087)/2
+ 14052 005e 60       		.byte	(.L1085-.L1087)/2
+ 14053 005f 60       		.byte	(.L1085-.L1087)/2
+ 14054 0060 3A       		.byte	(.L1090-.L1087)/2
+ 14055 0061 60       		.byte	(.L1085-.L1087)/2
+ 14056 0062 60       		.byte	(.L1085-.L1087)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 450
+
+
+ 14057 0063 60       		.byte	(.L1085-.L1087)/2
+ 14058 0064 54       		.byte	(.L1089-.L1087)/2
+ 14059 0065 60       		.byte	(.L1085-.L1087)/2
+ 14060 0066 60       		.byte	(.L1085-.L1087)/2
+ 14061 0067 60       		.byte	(.L1085-.L1087)/2
+ 14062 0068 58       		.byte	(.L1088-.L1087)/2
+ 14063 0069 60       		.byte	(.L1085-.L1087)/2
+ 14064 006a 60       		.byte	(.L1085-.L1087)/2
+ 14065 006b 60       		.byte	(.L1085-.L1087)/2
+ 14066 006c 5C       		.byte	(.L1086-.L1087)/2
+ 14067              	.LVL1050:
+ 14068 006d 00       		.p2align 1
+ 14069              	.L1076:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14070              		.loc 1 2386 47 is_stmt 0 discriminator 4 view .LVU4170
+ 14071 006e 90F83F00 		ldrb	r0, [r0, #63]	@ zero_extendqisi2
+ 14072              	.LVL1051:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14073              		.loc 1 2386 47 discriminator 4 view .LVU4171
+ 14074 0072 C0B2     		uxtb	r0, r0
+ 14075 0074 DAE7     		b	.L1078
+ 14076              	.LVL1052:
+ 14077              	.L1075:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14078              		.loc 1 2386 47 discriminator 7 view .LVU4172
+ 14079 0076 90F84000 		ldrb	r0, [r0, #64]	@ zero_extendqisi2
+ 14080              	.LVL1053:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14081              		.loc 1 2386 47 discriminator 7 view .LVU4173
+ 14082 007a C0B2     		uxtb	r0, r0
+ 14083 007c D6E7     		b	.L1078
+ 14084              	.LVL1054:
+ 14085              	.L1074:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14086              		.loc 1 2386 47 discriminator 10 view .LVU4174
+ 14087 007e 90F84110 		ldrb	r1, [r0, #65]	@ zero_extendqisi2
+ 14088              	.LVL1055:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14089              		.loc 1 2386 47 discriminator 10 view .LVU4175
+ 14090 0082 C8B2     		uxtb	r0, r1
+ 14091              	.LVL1056:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14092              		.loc 1 2386 47 discriminator 10 view .LVU4176
+ 14093 0084 D2E7     		b	.L1078
+ 14094              	.LVL1057:
+ 14095              	.L1072:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14096              		.loc 1 2386 47 discriminator 13 view .LVU4177
+ 14097 0086 90F84210 		ldrb	r1, [r0, #66]	@ zero_extendqisi2
+ 14098              	.LVL1058:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14099              		.loc 1 2386 47 discriminator 13 view .LVU4178
+ 14100 008a C8B2     		uxtb	r0, r1
+ 14101              	.LVL1059:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14102              		.loc 1 2386 47 discriminator 13 view .LVU4179
+ 14103 008c CEE7     		b	.L1078
+ARM GAS  /tmp/cc0wMqvE.s 			page 451
+
+
+ 14104              	.LVL1060:
+ 14105              	.L1071:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14106              		.loc 1 2386 47 discriminator 14 view .LVU4180
+ 14107 008e 90F84310 		ldrb	r1, [r0, #67]	@ zero_extendqisi2
+ 14108              	.LVL1061:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14109              		.loc 1 2386 47 discriminator 14 view .LVU4181
+ 14110 0092 C8B2     		uxtb	r0, r1
+ 14111              	.LVL1062:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 14112              		.loc 1 2386 47 discriminator 14 view .LVU4182
+ 14113 0094 CAE7     		b	.L1078
+ 14114              	.LVL1063:
+ 14115              	.L1079:
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14116              		.loc 1 2387 61 discriminator 2 view .LVU4183
+ 14117 0096 042C     		cmp	r4, #4
+ 14118 0098 06D0     		beq	.L1116
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14119              		.loc 1 2387 61 discriminator 5 view .LVU4184
+ 14120 009a 082C     		cmp	r4, #8
+ 14121 009c 09D0     		beq	.L1117
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14122              		.loc 1 2387 61 discriminator 8 view .LVU4185
+ 14123 009e 95F84780 		ldrb	r8, [r5, #71]	@ zero_extendqisi2
+ 14124 00a2 5FFA88F8 		uxtb	r8, r8
+ 14125 00a6 C6E7     		b	.L1080
+ 14126              	.L1116:
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14127              		.loc 1 2387 61 discriminator 4 view .LVU4186
+ 14128 00a8 95F84580 		ldrb	r8, [r5, #69]	@ zero_extendqisi2
+ 14129 00ac 5FFA88F8 		uxtb	r8, r8
+ 14130 00b0 C1E7     		b	.L1080
+ 14131              	.L1117:
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14132              		.loc 1 2387 61 discriminator 7 view .LVU4187
+ 14133 00b2 95F84680 		ldrb	r8, [r5, #70]	@ zero_extendqisi2
+ 14134 00b6 5FFA88F8 		uxtb	r8, r8
+ 14135 00ba BCE7     		b	.L1080
+ 14136              	.LVL1064:
+ 14137              	.L1115:
+2402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 14138              		.loc 1 2402 25 discriminator 1 view .LVU4188
+ 14139 00bc 002F     		cmp	r7, #0
+ 14140 00be C9D0     		beq	.L1084
+2404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14141              		.loc 1 2404 14 view .LVU4189
+ 14142 00c0 4046     		mov	r0, r8
+ 14143              	.LVL1065:
+2404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14144              		.loc 1 2404 14 view .LVU4190
+ 14145 00c2 C7E0     		b	.L1083
+ 14146              	.LVL1066:
+ 14147              	.L1091:
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14148              		.loc 1 2408 7 view .LVU4191
+ARM GAS  /tmp/cc0wMqvE.s 			page 452
+
+
+ 14149 00c4 0223     		movs	r3, #2
+ 14150 00c6 85F83E30 		strb	r3, [r5, #62]
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14151              		.loc 1 2409 7 is_stmt 1 view .LVU4192
+ 14152 00ca 85F84430 		strb	r3, [r5, #68]
+ 14153 00ce 09E0     		b	.L1092
+ 14154              	.L1090:
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14155              		.loc 1 2408 7 is_stmt 0 view .LVU4193
+ 14156 00d0 0223     		movs	r3, #2
+ 14157 00d2 85F83F30 		strb	r3, [r5, #63]
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14158              		.loc 1 2409 7 is_stmt 1 view .LVU4194
+ 14159              	.L1093:
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14160              		.loc 1 2409 7 is_stmt 0 discriminator 2 view .LVU4195
+ 14161 00d6 042C     		cmp	r4, #4
+ 14162 00d8 24D0     		beq	.L1118
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14163              		.loc 1 2409 7 discriminator 4 view .LVU4196
+ 14164 00da 082C     		cmp	r4, #8
+ 14165 00dc 26D0     		beq	.L1119
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14166              		.loc 1 2409 7 discriminator 7 view .LVU4197
+ 14167 00de 0223     		movs	r3, #2
+ 14168 00e0 85F84730 		strb	r3, [r5, #71]
+ 14169              	.L1092:
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14170              		.loc 1 2418 3 is_stmt 1 view .LVU4198
+ 14171 00e4 0122     		movs	r2, #1
+ 14172              	.LVL1067:
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14173              		.loc 1 2418 3 is_stmt 0 view .LVU4199
+ 14174 00e6 2146     		mov	r1, r4
+ 14175 00e8 2868     		ldr	r0, [r5]
+ 14176              	.LVL1068:
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14177              		.loc 1 2418 3 view .LVU4200
+ 14178 00ea FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14179              	.LVL1069:
+2420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14180              		.loc 1 2420 3 is_stmt 1 view .LVU4201
+ 14181 00ee 0C2C     		cmp	r4, #12
+ 14182 00f0 38D8     		bhi	.L1096
+ 14183 00f2 DFE804F0 		tbb	[pc, r4]
+ 14184              	.L1098:
+ 14185 00f6 1F       		.byte	(.L1101-.L1098)/2
+ 14186 00f7 37       		.byte	(.L1096-.L1098)/2
+ 14187 00f8 37       		.byte	(.L1096-.L1098)/2
+ 14188 00f9 37       		.byte	(.L1096-.L1098)/2
+ 14189 00fa 54       		.byte	(.L1100-.L1098)/2
+ 14190 00fb 37       		.byte	(.L1096-.L1098)/2
+ 14191 00fc 37       		.byte	(.L1096-.L1098)/2
+ 14192 00fd 37       		.byte	(.L1096-.L1098)/2
+ 14193 00fe 6D       		.byte	(.L1099-.L1098)/2
+ 14194 00ff 37       		.byte	(.L1096-.L1098)/2
+ 14195 0100 37       		.byte	(.L1096-.L1098)/2
+ARM GAS  /tmp/cc0wMqvE.s 			page 453
+
+
+ 14196 0101 37       		.byte	(.L1096-.L1098)/2
+ 14197 0102 86       		.byte	(.L1097-.L1098)/2
+ 14198              	.LVL1070:
+ 14199 0103 00       		.p2align 1
+ 14200              	.L1089:
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14201              		.loc 1 2408 7 is_stmt 0 view .LVU4202
+ 14202 0104 0223     		movs	r3, #2
+ 14203 0106 85F84030 		strb	r3, [r5, #64]
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14204              		.loc 1 2409 7 is_stmt 1 view .LVU4203
+ 14205 010a E4E7     		b	.L1093
+ 14206              	.L1088:
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14207              		.loc 1 2408 7 is_stmt 0 view .LVU4204
+ 14208 010c 0223     		movs	r3, #2
+ 14209 010e 85F84130 		strb	r3, [r5, #65]
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14210              		.loc 1 2409 7 is_stmt 1 view .LVU4205
+ 14211 0112 E0E7     		b	.L1093
+ 14212              	.L1086:
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14213              		.loc 1 2408 7 is_stmt 0 view .LVU4206
+ 14214 0114 0223     		movs	r3, #2
+ 14215 0116 85F84230 		strb	r3, [r5, #66]
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14216              		.loc 1 2409 7 is_stmt 1 view .LVU4207
+ 14217 011a DCE7     		b	.L1093
+ 14218              	.L1085:
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14219              		.loc 1 2408 7 is_stmt 0 discriminator 13 view .LVU4208
+ 14220 011c 0223     		movs	r3, #2
+ 14221 011e 85F84330 		strb	r3, [r5, #67]
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14222              		.loc 1 2409 7 is_stmt 1 discriminator 13 view .LVU4209
+ 14223 0122 D8E7     		b	.L1093
+ 14224              	.L1118:
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14225              		.loc 1 2409 7 is_stmt 0 discriminator 3 view .LVU4210
+ 14226 0124 0223     		movs	r3, #2
+ 14227 0126 85F84530 		strb	r3, [r5, #69]
+ 14228 012a DBE7     		b	.L1092
+ 14229              	.L1119:
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14230              		.loc 1 2409 7 discriminator 6 view .LVU4211
+ 14231 012c 0223     		movs	r3, #2
+ 14232 012e 85F84630 		strb	r3, [r5, #70]
+ 14233 0132 D7E7     		b	.L1092
+ 14234              	.LVL1071:
+ 14235              	.L1101:
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 14236              		.loc 1 2425 7 is_stmt 1 view .LVU4212
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 14237              		.loc 1 2425 17 is_stmt 0 view .LVU4213
+ 14238 0134 6B6A     		ldr	r3, [r5, #36]
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 14239              		.loc 1 2425 52 view .LVU4214
+ARM GAS  /tmp/cc0wMqvE.s 			page 454
+
+
+ 14240 0136 4E4A     		ldr	r2, .L1120
+ 14241 0138 DA62     		str	r2, [r3, #44]
+2426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14242              		.loc 1 2426 7 is_stmt 1 view .LVU4215
+2426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14243              		.loc 1 2426 17 is_stmt 0 view .LVU4216
+ 14244 013a 6B6A     		ldr	r3, [r5, #36]
+2426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14245              		.loc 1 2426 56 view .LVU4217
+ 14246 013c 4D4A     		ldr	r2, .L1120+4
+ 14247 013e 1A63     		str	r2, [r3, #48]
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14248              		.loc 1 2429 7 is_stmt 1 view .LVU4218
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14249              		.loc 1 2429 17 is_stmt 0 view .LVU4219
+ 14250 0140 6B6A     		ldr	r3, [r5, #36]
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14251              		.loc 1 2429 53 view .LVU4220
+ 14252 0142 4D4A     		ldr	r2, .L1120+8
+ 14253 0144 5A63     		str	r2, [r3, #52]
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14254              		.loc 1 2432 7 is_stmt 1 view .LVU4221
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14255              		.loc 1 2432 71 is_stmt 0 view .LVU4222
+ 14256 0146 2968     		ldr	r1, [r5]
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14257              		.loc 1 2432 11 view .LVU4223
+ 14258 0148 3B46     		mov	r3, r7
+ 14259 014a 3246     		mov	r2, r6
+ 14260 014c 3431     		adds	r1, r1, #52
+ 14261 014e 686A     		ldr	r0, [r5, #36]
+ 14262 0150 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 14263              	.LVL1072:
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14264              		.loc 1 2432 10 view .LVU4224
+ 14265 0154 0028     		cmp	r0, #0
+ 14266 0156 7FD1     		bne	.L1107
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 14267              		.loc 1 2439 7 is_stmt 1 view .LVU4225
+ 14268 0158 2A68     		ldr	r2, [r5]
+ 14269 015a D368     		ldr	r3, [r2, #12]
+ 14270 015c 43F40073 		orr	r3, r3, #512
+ 14271 0160 D360     		str	r3, [r2, #12]
+2440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14272              		.loc 1 2440 7 view .LVU4226
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 14273              		.loc 1 2383 21 is_stmt 0 view .LVU4227
+ 14274 0162 8046     		mov	r8, r0
+ 14275              	.LVL1073:
+ 14276              	.L1096:
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14277              		.loc 1 2512 3 is_stmt 1 view .LVU4228
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14278              		.loc 1 2512 7 is_stmt 0 view .LVU4229
+ 14279 0164 2B68     		ldr	r3, [r5]
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14280              		.loc 1 2512 6 view .LVU4230
+ARM GAS  /tmp/cc0wMqvE.s 			page 455
+
+
+ 14281 0166 454A     		ldr	r2, .L1120+12
+ 14282 0168 9342     		cmp	r3, r2
+ 14283 016a 62D0     		beq	.L1102
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14284              		.loc 1 2512 7 discriminator 1 view .LVU4231
+ 14285 016c B3F1804F 		cmp	r3, #1073741824
+ 14286 0170 5FD0     		beq	.L1102
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14287              		.loc 1 2512 7 discriminator 2 view .LVU4232
+ 14288 0172 A2F59432 		sub	r2, r2, #75776
+ 14289 0176 9342     		cmp	r3, r2
+ 14290 0178 5BD0     		beq	.L1102
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14291              		.loc 1 2512 7 discriminator 3 view .LVU4233
+ 14292 017a 02F58062 		add	r2, r2, #1024
+ 14293 017e 9342     		cmp	r3, r2
+ 14294 0180 57D0     		beq	.L1102
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14295              		.loc 1 2512 7 discriminator 4 view .LVU4234
+ 14296 0182 02F59632 		add	r2, r2, #76800
+ 14297 0186 9342     		cmp	r3, r2
+ 14298 0188 53D0     		beq	.L1102
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14299              		.loc 1 2512 7 discriminator 5 view .LVU4235
+ 14300 018a 02F54062 		add	r2, r2, #3072
+ 14301 018e 9342     		cmp	r3, r2
+ 14302 0190 4FD0     		beq	.L1102
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14303              		.loc 1 2522 5 is_stmt 1 view .LVU4236
+ 14304 0192 1A68     		ldr	r2, [r3]
+ 14305 0194 42F00102 		orr	r2, r2, #1
+ 14306 0198 1A60     		str	r2, [r3]
+2526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 14307              		.loc 1 2526 10 is_stmt 0 view .LVU4237
+ 14308 019a 4046     		mov	r0, r8
+ 14309 019c 5AE0     		b	.L1083
+ 14310              	.LVL1074:
+ 14311              	.L1100:
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 14312              		.loc 1 2446 7 is_stmt 1 view .LVU4238
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 14313              		.loc 1 2446 17 is_stmt 0 view .LVU4239
+ 14314 019e AB6A     		ldr	r3, [r5, #40]
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 14315              		.loc 1 2446 52 view .LVU4240
+ 14316 01a0 334A     		ldr	r2, .L1120
+ 14317 01a2 DA62     		str	r2, [r3, #44]
+2447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14318              		.loc 1 2447 7 is_stmt 1 view .LVU4241
+2447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14319              		.loc 1 2447 17 is_stmt 0 view .LVU4242
+ 14320 01a4 AB6A     		ldr	r3, [r5, #40]
+2447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14321              		.loc 1 2447 56 view .LVU4243
+ 14322 01a6 334A     		ldr	r2, .L1120+4
+ 14323 01a8 1A63     		str	r2, [r3, #48]
+2450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 456
+
+
+ 14324              		.loc 1 2450 7 is_stmt 1 view .LVU4244
+2450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14325              		.loc 1 2450 17 is_stmt 0 view .LVU4245
+ 14326 01aa AB6A     		ldr	r3, [r5, #40]
+2450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14327              		.loc 1 2450 53 view .LVU4246
+ 14328 01ac 324A     		ldr	r2, .L1120+8
+ 14329 01ae 5A63     		str	r2, [r3, #52]
+2453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14330              		.loc 1 2453 7 is_stmt 1 view .LVU4247
+2453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14331              		.loc 1 2453 71 is_stmt 0 view .LVU4248
+ 14332 01b0 2968     		ldr	r1, [r5]
+2453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14333              		.loc 1 2453 11 view .LVU4249
+ 14334 01b2 3B46     		mov	r3, r7
+ 14335 01b4 3246     		mov	r2, r6
+ 14336 01b6 3831     		adds	r1, r1, #56
+ 14337 01b8 A86A     		ldr	r0, [r5, #40]
+ 14338 01ba FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 14339              	.LVL1075:
+2453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14340              		.loc 1 2453 10 view .LVU4250
+ 14341 01be 0028     		cmp	r0, #0
+ 14342 01c0 4CD1     		bne	.L1108
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 14343              		.loc 1 2460 7 is_stmt 1 view .LVU4251
+ 14344 01c2 2A68     		ldr	r2, [r5]
+ 14345 01c4 D368     		ldr	r3, [r2, #12]
+ 14346 01c6 43F48063 		orr	r3, r3, #1024
+ 14347 01ca D360     		str	r3, [r2, #12]
+2461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14348              		.loc 1 2461 7 view .LVU4252
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 14349              		.loc 1 2383 21 is_stmt 0 view .LVU4253
+ 14350 01cc 8046     		mov	r8, r0
+ 14351              	.LVL1076:
+2461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14352              		.loc 1 2461 7 view .LVU4254
+ 14353 01ce C9E7     		b	.L1096
+ 14354              	.LVL1077:
+ 14355              	.L1099:
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 14356              		.loc 1 2467 7 is_stmt 1 view .LVU4255
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 14357              		.loc 1 2467 17 is_stmt 0 view .LVU4256
+ 14358 01d0 EB6A     		ldr	r3, [r5, #44]
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 14359              		.loc 1 2467 52 view .LVU4257
+ 14360 01d2 274A     		ldr	r2, .L1120
+ 14361 01d4 DA62     		str	r2, [r3, #44]
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14362              		.loc 1 2468 7 is_stmt 1 view .LVU4258
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14363              		.loc 1 2468 17 is_stmt 0 view .LVU4259
+ 14364 01d6 EB6A     		ldr	r3, [r5, #44]
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 457
+
+
+ 14365              		.loc 1 2468 56 view .LVU4260
+ 14366 01d8 264A     		ldr	r2, .L1120+4
+ 14367 01da 1A63     		str	r2, [r3, #48]
+2471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14368              		.loc 1 2471 7 is_stmt 1 view .LVU4261
+2471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14369              		.loc 1 2471 17 is_stmt 0 view .LVU4262
+ 14370 01dc EB6A     		ldr	r3, [r5, #44]
+2471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14371              		.loc 1 2471 53 view .LVU4263
+ 14372 01de 264A     		ldr	r2, .L1120+8
+ 14373 01e0 5A63     		str	r2, [r3, #52]
+2474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14374              		.loc 1 2474 7 is_stmt 1 view .LVU4264
+2474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14375              		.loc 1 2474 71 is_stmt 0 view .LVU4265
+ 14376 01e2 2968     		ldr	r1, [r5]
+2474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14377              		.loc 1 2474 11 view .LVU4266
+ 14378 01e4 3B46     		mov	r3, r7
+ 14379 01e6 3246     		mov	r2, r6
+ 14380 01e8 3C31     		adds	r1, r1, #60
+ 14381 01ea E86A     		ldr	r0, [r5, #44]
+ 14382 01ec FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 14383              	.LVL1078:
+2474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14384              		.loc 1 2474 10 view .LVU4267
+ 14385 01f0 0028     		cmp	r0, #0
+ 14386 01f2 35D1     		bne	.L1109
+2481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 14387              		.loc 1 2481 7 is_stmt 1 view .LVU4268
+ 14388 01f4 2A68     		ldr	r2, [r5]
+ 14389 01f6 D368     		ldr	r3, [r2, #12]
+ 14390 01f8 43F40063 		orr	r3, r3, #2048
+ 14391 01fc D360     		str	r3, [r2, #12]
+2482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14392              		.loc 1 2482 7 view .LVU4269
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 14393              		.loc 1 2383 21 is_stmt 0 view .LVU4270
+ 14394 01fe 8046     		mov	r8, r0
+ 14395              	.LVL1079:
+2482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14396              		.loc 1 2482 7 view .LVU4271
+ 14397 0200 B0E7     		b	.L1096
+ 14398              	.LVL1080:
+ 14399              	.L1097:
+2488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 14400              		.loc 1 2488 7 is_stmt 1 view .LVU4272
+2488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 14401              		.loc 1 2488 17 is_stmt 0 view .LVU4273
+ 14402 0202 2B6B     		ldr	r3, [r5, #48]
+2488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 14403              		.loc 1 2488 52 view .LVU4274
+ 14404 0204 1A4A     		ldr	r2, .L1120
+ 14405 0206 DA62     		str	r2, [r3, #44]
+2489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14406              		.loc 1 2489 7 is_stmt 1 view .LVU4275
+ARM GAS  /tmp/cc0wMqvE.s 			page 458
+
+
+2489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14407              		.loc 1 2489 17 is_stmt 0 view .LVU4276
+ 14408 0208 2B6B     		ldr	r3, [r5, #48]
+2489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14409              		.loc 1 2489 56 view .LVU4277
+ 14410 020a 1A4A     		ldr	r2, .L1120+4
+ 14411 020c 1A63     		str	r2, [r3, #48]
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14412              		.loc 1 2492 7 is_stmt 1 view .LVU4278
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14413              		.loc 1 2492 17 is_stmt 0 view .LVU4279
+ 14414 020e 2B6B     		ldr	r3, [r5, #48]
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14415              		.loc 1 2492 53 view .LVU4280
+ 14416 0210 194A     		ldr	r2, .L1120+8
+ 14417 0212 5A63     		str	r2, [r3, #52]
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14418              		.loc 1 2495 7 is_stmt 1 view .LVU4281
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14419              		.loc 1 2495 71 is_stmt 0 view .LVU4282
+ 14420 0214 2968     		ldr	r1, [r5]
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14421              		.loc 1 2495 11 view .LVU4283
+ 14422 0216 3B46     		mov	r3, r7
+ 14423 0218 3246     		mov	r2, r6
+ 14424 021a 4031     		adds	r1, r1, #64
+ 14425 021c 286B     		ldr	r0, [r5, #48]
+ 14426 021e FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 14427              	.LVL1081:
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 14428              		.loc 1 2495 10 view .LVU4284
+ 14429 0222 F8B9     		cbnz	r0, .L1110
+2502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 14430              		.loc 1 2502 7 is_stmt 1 view .LVU4285
+ 14431 0224 2A68     		ldr	r2, [r5]
+ 14432 0226 D368     		ldr	r3, [r2, #12]
+ 14433 0228 43F48053 		orr	r3, r3, #4096
+ 14434 022c D360     		str	r3, [r2, #12]
+2503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14435              		.loc 1 2503 7 view .LVU4286
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 14436              		.loc 1 2383 21 is_stmt 0 view .LVU4287
+ 14437 022e 8046     		mov	r8, r0
+ 14438              	.LVL1082:
+2503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14439              		.loc 1 2503 7 view .LVU4288
+ 14440 0230 98E7     		b	.L1096
+ 14441              	.LVL1083:
+ 14442              	.L1102:
+2514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 14443              		.loc 1 2514 5 is_stmt 1 view .LVU4289
+2514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 14444              		.loc 1 2514 29 is_stmt 0 view .LVU4290
+ 14445 0232 9968     		ldr	r1, [r3, #8]
+2514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 14446              		.loc 1 2514 13 view .LVU4291
+ 14447 0234 124A     		ldr	r2, .L1120+16
+ARM GAS  /tmp/cc0wMqvE.s 			page 459
+
+
+ 14448 0236 0A40     		ands	r2, r2, r1
+ 14449              	.LVL1084:
+2515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 14450              		.loc 1 2515 5 is_stmt 1 view .LVU4292
+2515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 14451              		.loc 1 2515 8 is_stmt 0 view .LVU4293
+ 14452 0238 062A     		cmp	r2, #6
+ 14453 023a 15D0     		beq	.L1111
+2515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 14454              		.loc 1 2515 9 discriminator 1 view .LVU4294
+ 14455 023c B2F5803F 		cmp	r2, #65536
+ 14456 0240 14D0     		beq	.L1112
+2517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14457              		.loc 1 2517 7 is_stmt 1 view .LVU4295
+ 14458 0242 1A68     		ldr	r2, [r3]
+ 14459              	.LVL1085:
+2517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14460              		.loc 1 2517 7 is_stmt 0 view .LVU4296
+ 14461 0244 42F00102 		orr	r2, r2, #1
+ 14462 0248 1A60     		str	r2, [r3]
+2526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 14463              		.loc 1 2526 10 view .LVU4297
+ 14464 024a 4046     		mov	r0, r8
+ 14465 024c 02E0     		b	.L1083
+ 14466              	.LVL1086:
+ 14467              	.L1104:
+2397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14468              		.loc 1 2397 12 view .LVU4298
+ 14469 024e 4046     		mov	r0, r8
+ 14470              	.LVL1087:
+2397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14471              		.loc 1 2397 12 view .LVU4299
+ 14472 0250 00E0     		b	.L1083
+ 14473              	.LVL1088:
+ 14474              	.L1105:
+2414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14475              		.loc 1 2414 12 view .LVU4300
+ 14476 0252 0120     		movs	r0, #1
+ 14477              	.LVL1089:
+ 14478              	.L1083:
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14479              		.loc 1 2527 1 view .LVU4301
+ 14480 0254 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 14481              	.LVL1090:
+ 14482              	.L1107:
+2436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 14483              		.loc 1 2436 16 view .LVU4302
+ 14484 0258 4046     		mov	r0, r8
+ 14485 025a FBE7     		b	.L1083
+ 14486              	.L1108:
+2457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 14487              		.loc 1 2457 16 view .LVU4303
+ 14488 025c 4046     		mov	r0, r8
+ 14489 025e F9E7     		b	.L1083
+ 14490              	.L1109:
+2478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 14491              		.loc 1 2478 16 view .LVU4304
+ARM GAS  /tmp/cc0wMqvE.s 			page 460
+
+
+ 14492 0260 4046     		mov	r0, r8
+ 14493 0262 F7E7     		b	.L1083
+ 14494              	.L1110:
+2499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 14495              		.loc 1 2499 16 view .LVU4305
+ 14496 0264 4046     		mov	r0, r8
+ 14497 0266 F5E7     		b	.L1083
+ 14498              	.LVL1091:
+ 14499              	.L1111:
+2526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 14500              		.loc 1 2526 10 view .LVU4306
+ 14501 0268 4046     		mov	r0, r8
+ 14502 026a F3E7     		b	.L1083
+ 14503              	.L1112:
+ 14504 026c 4046     		mov	r0, r8
+ 14505 026e F1E7     		b	.L1083
+ 14506              	.L1121:
+ 14507              		.align	2
+ 14508              	.L1120:
+ 14509 0270 00000000 		.word	TIM_DMACaptureCplt
+ 14510 0274 00000000 		.word	TIM_DMACaptureHalfCplt
+ 14511 0278 00000000 		.word	TIM_DMAError
+ 14512 027c 002C0140 		.word	1073818624
+ 14513 0280 07000100 		.word	65543
+ 14514              		.cfi_endproc
+ 14515              	.LFE367:
+ 14517              		.section	.text.HAL_TIM_IC_Stop_DMA,"ax",%progbits
+ 14518              		.align	1
+ 14519              		.global	HAL_TIM_IC_Stop_DMA
+ 14520              		.syntax unified
+ 14521              		.thumb
+ 14522              		.thumb_func
+ 14524              	HAL_TIM_IC_Stop_DMA:
+ 14525              	.LVL1092:
+ 14526              	.LFB368:
+2541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 14527              		.loc 1 2541 1 is_stmt 1 view -0
+ 14528              		.cfi_startproc
+ 14529              		@ args = 0, pretend = 0, frame = 0
+ 14530              		@ frame_needed = 0, uses_anonymous_args = 0
+2541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 14531              		.loc 1 2541 1 is_stmt 0 view .LVU4308
+ 14532 0000 38B5     		push	{r3, r4, r5, lr}
+ 14533              	.LCFI102:
+ 14534              		.cfi_def_cfa_offset 16
+ 14535              		.cfi_offset 3, -16
+ 14536              		.cfi_offset 4, -12
+ 14537              		.cfi_offset 5, -8
+ 14538              		.cfi_offset 14, -4
+ 14539 0002 0446     		mov	r4, r0
+ 14540 0004 0D46     		mov	r5, r1
+2542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14541              		.loc 1 2542 3 is_stmt 1 view .LVU4309
+ 14542              	.LVL1093:
+2545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ 14543              		.loc 1 2545 3 view .LVU4310
+2546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 461
+
+
+ 14544              		.loc 1 2546 3 view .LVU4311
+2549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14545              		.loc 1 2549 3 view .LVU4312
+ 14546 0006 0022     		movs	r2, #0
+ 14547 0008 0068     		ldr	r0, [r0]
+ 14548              	.LVL1094:
+2549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14549              		.loc 1 2549 3 is_stmt 0 view .LVU4313
+ 14550 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14551              	.LVL1095:
+2551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14552              		.loc 1 2551 3 is_stmt 1 view .LVU4314
+ 14553 000e 0C2D     		cmp	r5, #12
+ 14554 0010 74D8     		bhi	.L1141
+ 14555 0012 DFE805F0 		tbb	[pc, r5]
+ 14556              	.L1125:
+ 14557 0016 07       		.byte	(.L1128-.L1125)/2
+ 14558 0017 73       		.byte	(.L1141-.L1125)/2
+ 14559 0018 73       		.byte	(.L1141-.L1125)/2
+ 14560 0019 73       		.byte	(.L1141-.L1125)/2
+ 14561 001a 26       		.byte	(.L1127-.L1125)/2
+ 14562 001b 73       		.byte	(.L1141-.L1125)/2
+ 14563 001c 73       		.byte	(.L1141-.L1125)/2
+ 14564 001d 73       		.byte	(.L1141-.L1125)/2
+ 14565 001e 2F       		.byte	(.L1126-.L1125)/2
+ 14566 001f 73       		.byte	(.L1141-.L1125)/2
+ 14567 0020 73       		.byte	(.L1141-.L1125)/2
+ 14568 0021 73       		.byte	(.L1141-.L1125)/2
+ 14569 0022 38       		.byte	(.L1124-.L1125)/2
+ 14570 0023 00       		.p2align 1
+ 14571              	.L1128:
+2556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 14572              		.loc 1 2556 7 view .LVU4315
+ 14573 0024 2268     		ldr	r2, [r4]
+ 14574 0026 D368     		ldr	r3, [r2, #12]
+ 14575 0028 23F40073 		bic	r3, r3, #512
+ 14576 002c D360     		str	r3, [r2, #12]
+2557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 14577              		.loc 1 2557 7 view .LVU4316
+2557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 14578              		.loc 1 2557 13 is_stmt 0 view .LVU4317
+ 14579 002e 606A     		ldr	r0, [r4, #36]
+ 14580 0030 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 14581              	.LVL1096:
+2558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14582              		.loc 1 2558 7 is_stmt 1 view .LVU4318
+2590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14583              		.loc 1 2590 3 view .LVU4319
+ 14584              	.L1129:
+2593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14585              		.loc 1 2593 5 view .LVU4320
+2593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14586              		.loc 1 2593 5 view .LVU4321
+ 14587 0034 2368     		ldr	r3, [r4]
+ 14588 0036 196A     		ldr	r1, [r3, #32]
+ 14589 0038 41F21112 		movw	r2, #4369
+ 14590 003c 1142     		tst	r1, r2
+ARM GAS  /tmp/cc0wMqvE.s 			page 462
+
+
+ 14591 003e 08D1     		bne	.L1130
+2593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14592              		.loc 1 2593 5 discriminator 1 view .LVU4322
+ 14593 0040 196A     		ldr	r1, [r3, #32]
+ 14594 0042 44F24442 		movw	r2, #17476
+ 14595 0046 1142     		tst	r1, r2
+ 14596 0048 03D1     		bne	.L1130
+2593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14597              		.loc 1 2593 5 discriminator 3 view .LVU4323
+ 14598 004a 1A68     		ldr	r2, [r3]
+ 14599 004c 22F00102 		bic	r2, r2, #1
+ 14600 0050 1A60     		str	r2, [r3]
+ 14601              	.L1130:
+2593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14602              		.loc 1 2593 5 discriminator 5 view .LVU4324
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14603              		.loc 1 2596 5 discriminator 5 view .LVU4325
+ 14604 0052 0DBB     		cbnz	r5, .L1131
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14605              		.loc 1 2596 5 is_stmt 0 view .LVU4326
+ 14606 0054 0123     		movs	r3, #1
+ 14607 0056 84F83E30 		strb	r3, [r4, #62]
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14608              		.loc 1 2597 5 is_stmt 1 view .LVU4327
+ 14609 005a 84F84430 		strb	r3, [r4, #68]
+ 14610 005e 0020     		movs	r0, #0
+ 14611 0060 4DE0     		b	.L1123
+ 14612              	.L1127:
+2564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 14613              		.loc 1 2564 7 view .LVU4328
+ 14614 0062 2268     		ldr	r2, [r4]
+ 14615 0064 D368     		ldr	r3, [r2, #12]
+ 14616 0066 23F48063 		bic	r3, r3, #1024
+ 14617 006a D360     		str	r3, [r2, #12]
+2565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 14618              		.loc 1 2565 7 view .LVU4329
+2565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 14619              		.loc 1 2565 13 is_stmt 0 view .LVU4330
+ 14620 006c A06A     		ldr	r0, [r4, #40]
+ 14621 006e FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 14622              	.LVL1097:
+2566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14623              		.loc 1 2566 7 is_stmt 1 view .LVU4331
+2590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14624              		.loc 1 2590 3 view .LVU4332
+ 14625 0072 DFE7     		b	.L1129
+ 14626              	.L1126:
+2572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ 14627              		.loc 1 2572 7 view .LVU4333
+ 14628 0074 2268     		ldr	r2, [r4]
+ 14629 0076 D368     		ldr	r3, [r2, #12]
+ 14630 0078 23F40063 		bic	r3, r3, #2048
+ 14631 007c D360     		str	r3, [r2, #12]
+2573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 14632              		.loc 1 2573 7 view .LVU4334
+2573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 14633              		.loc 1 2573 13 is_stmt 0 view .LVU4335
+ARM GAS  /tmp/cc0wMqvE.s 			page 463
+
+
+ 14634 007e E06A     		ldr	r0, [r4, #44]
+ 14635 0080 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 14636              	.LVL1098:
+2574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14637              		.loc 1 2574 7 is_stmt 1 view .LVU4336
+2590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14638              		.loc 1 2590 3 view .LVU4337
+ 14639 0084 D6E7     		b	.L1129
+ 14640              	.L1124:
+2580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ 14641              		.loc 1 2580 7 view .LVU4338
+ 14642 0086 2268     		ldr	r2, [r4]
+ 14643 0088 D368     		ldr	r3, [r2, #12]
+ 14644 008a 23F48053 		bic	r3, r3, #4096
+ 14645 008e D360     		str	r3, [r2, #12]
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 14646              		.loc 1 2581 7 view .LVU4339
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 14647              		.loc 1 2581 13 is_stmt 0 view .LVU4340
+ 14648 0090 206B     		ldr	r0, [r4, #48]
+ 14649 0092 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 14650              	.LVL1099:
+2582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 14651              		.loc 1 2582 7 is_stmt 1 view .LVU4341
+2590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14652              		.loc 1 2590 3 view .LVU4342
+ 14653 0096 CDE7     		b	.L1129
+ 14654              	.L1131:
+2590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14655              		.loc 1 2590 3 is_stmt 0 view .LVU4343
+ 14656 0098 2B1F     		subs	r3, r5, #4
+ 14657 009a 0C2B     		cmp	r3, #12
+ 14658 009c 20D8     		bhi	.L1132
+ 14659 009e DFE803F0 		tbb	[pc, r3]
+ 14660              	.L1134:
+ 14661 00a2 07       		.byte	(.L1137-.L1134)/2
+ 14662 00a3 1F       		.byte	(.L1132-.L1134)/2
+ 14663 00a4 1F       		.byte	(.L1132-.L1134)/2
+ 14664 00a5 1F       		.byte	(.L1132-.L1134)/2
+ 14665 00a6 13       		.byte	(.L1136-.L1134)/2
+ 14666 00a7 1F       		.byte	(.L1132-.L1134)/2
+ 14667 00a8 1F       		.byte	(.L1132-.L1134)/2
+ 14668 00a9 1F       		.byte	(.L1132-.L1134)/2
+ 14669 00aa 17       		.byte	(.L1135-.L1134)/2
+ 14670 00ab 1F       		.byte	(.L1132-.L1134)/2
+ 14671 00ac 1F       		.byte	(.L1132-.L1134)/2
+ 14672 00ad 1F       		.byte	(.L1132-.L1134)/2
+ 14673 00ae 1B       		.byte	(.L1133-.L1134)/2
+ 14674 00af 00       		.p2align 1
+ 14675              	.L1137:
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14676              		.loc 1 2596 5 view .LVU4344
+ 14677 00b0 0123     		movs	r3, #1
+ 14678 00b2 84F83F30 		strb	r3, [r4, #63]
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14679              		.loc 1 2597 5 is_stmt 1 view .LVU4345
+ 14680              	.L1138:
+ARM GAS  /tmp/cc0wMqvE.s 			page 464
+
+
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14681              		.loc 1 2597 5 is_stmt 0 discriminator 2 view .LVU4346
+ 14682 00b6 042D     		cmp	r5, #4
+ 14683 00b8 16D0     		beq	.L1143
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14684              		.loc 1 2597 5 discriminator 4 view .LVU4347
+ 14685 00ba 082D     		cmp	r5, #8
+ 14686 00bc 19D0     		beq	.L1144
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14687              		.loc 1 2597 5 discriminator 7 view .LVU4348
+ 14688 00be 0123     		movs	r3, #1
+ 14689 00c0 84F84730 		strb	r3, [r4, #71]
+ 14690 00c4 0020     		movs	r0, #0
+ 14691 00c6 1AE0     		b	.L1123
+ 14692              	.L1136:
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14693              		.loc 1 2596 5 view .LVU4349
+ 14694 00c8 0123     		movs	r3, #1
+ 14695 00ca 84F84030 		strb	r3, [r4, #64]
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14696              		.loc 1 2597 5 is_stmt 1 view .LVU4350
+ 14697 00ce F2E7     		b	.L1138
+ 14698              	.L1135:
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14699              		.loc 1 2596 5 is_stmt 0 view .LVU4351
+ 14700 00d0 0123     		movs	r3, #1
+ 14701 00d2 84F84130 		strb	r3, [r4, #65]
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14702              		.loc 1 2597 5 is_stmt 1 view .LVU4352
+ 14703 00d6 EEE7     		b	.L1138
+ 14704              	.L1133:
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14705              		.loc 1 2596 5 is_stmt 0 view .LVU4353
+ 14706 00d8 0123     		movs	r3, #1
+ 14707 00da 84F84230 		strb	r3, [r4, #66]
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14708              		.loc 1 2597 5 is_stmt 1 view .LVU4354
+ 14709 00de EAE7     		b	.L1138
+ 14710              	.L1132:
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14711              		.loc 1 2596 5 is_stmt 0 discriminator 13 view .LVU4355
+ 14712 00e0 0123     		movs	r3, #1
+ 14713 00e2 84F84330 		strb	r3, [r4, #67]
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14714              		.loc 1 2597 5 is_stmt 1 discriminator 13 view .LVU4356
+ 14715 00e6 E6E7     		b	.L1138
+ 14716              	.L1143:
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14717              		.loc 1 2597 5 is_stmt 0 discriminator 3 view .LVU4357
+ 14718 00e8 0123     		movs	r3, #1
+ 14719 00ea 84F84530 		strb	r3, [r4, #69]
+ 14720 00ee 0020     		movs	r0, #0
+ 14721 00f0 05E0     		b	.L1123
+ 14722              	.L1144:
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14723              		.loc 1 2597 5 discriminator 6 view .LVU4358
+ 14724 00f2 0123     		movs	r3, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 465
+
+
+ 14725 00f4 84F84630 		strb	r3, [r4, #70]
+ 14726 00f8 0020     		movs	r0, #0
+ 14727 00fa 00E0     		b	.L1123
+ 14728              	.L1141:
+2551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14729              		.loc 1 2551 3 view .LVU4359
+ 14730 00fc 0120     		movs	r0, #1
+ 14731              	.L1123:
+ 14732              	.LVL1100:
+2601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 14733              		.loc 1 2601 3 is_stmt 1 view .LVU4360
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 14734              		.loc 1 2602 1 is_stmt 0 view .LVU4361
+ 14735 00fe 38BD     		pop	{r3, r4, r5, pc}
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** /**
+ 14736              		.loc 1 2602 1 view .LVU4362
+ 14737              		.cfi_endproc
+ 14738              	.LFE368:
+ 14740              		.section	.text.HAL_TIM_OnePulse_Start,"ax",%progbits
+ 14741              		.align	1
+ 14742              		.global	HAL_TIM_OnePulse_Start
+ 14743              		.syntax unified
+ 14744              		.thumb
+ 14745              		.thumb_func
+ 14747              	HAL_TIM_OnePulse_Start:
+ 14748              	.LVL1101:
+ 14749              	.LFB373:
+2794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 14750              		.loc 1 2794 1 is_stmt 1 view -0
+ 14751              		.cfi_startproc
+ 14752              		@ args = 0, pretend = 0, frame = 0
+ 14753              		@ frame_needed = 0, uses_anonymous_args = 0
+2794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 14754              		.loc 1 2794 1 is_stmt 0 view .LVU4364
+ 14755 0000 10B5     		push	{r4, lr}
+ 14756              	.LCFI103:
+ 14757              		.cfi_def_cfa_offset 8
+ 14758              		.cfi_offset 4, -8
+ 14759              		.cfi_offset 14, -4
+ 14760 0002 0446     		mov	r4, r0
+2795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14761              		.loc 1 2795 3 is_stmt 1 view .LVU4365
+2795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14762              		.loc 1 2795 31 is_stmt 0 view .LVU4366
+ 14763 0004 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 14764              	.LVL1102:
+2795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14765              		.loc 1 2795 31 view .LVU4367
+ 14766 0008 C0B2     		uxtb	r0, r0
+ 14767              	.LVL1103:
+2796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14768              		.loc 1 2796 3 is_stmt 1 view .LVU4368
+2796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14769              		.loc 1 2796 31 is_stmt 0 view .LVU4369
+ 14770 000a 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ 14771              	.LVL1104:
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ARM GAS  /tmp/cc0wMqvE.s 			page 466
+
+
+ 14772              		.loc 1 2797 3 is_stmt 1 view .LVU4370
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14773              		.loc 1 2797 31 is_stmt 0 view .LVU4371
+ 14774 000e 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 14775              	.LVL1105:
+2798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14776              		.loc 1 2798 3 is_stmt 1 view .LVU4372
+2798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14777              		.loc 1 2798 31 is_stmt 0 view .LVU4373
+ 14778 0012 94F84510 		ldrb	r1, [r4, #69]	@ zero_extendqisi2
+ 14779              	.LVL1106:
+2801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14780              		.loc 1 2801 3 is_stmt 1 view .LVU4374
+2804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 14781              		.loc 1 2804 3 view .LVU4375
+2804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 14782              		.loc 1 2804 6 is_stmt 0 view .LVU4376
+ 14783 0016 0128     		cmp	r0, #1
+ 14784 0018 38D1     		bne	.L1148
+ 14785 001a DBB2     		uxtb	r3, r3
+2804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 14786              		.loc 1 2804 6 view .LVU4377
+ 14787 001c D2B2     		uxtb	r2, r2
+2804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 14788              		.loc 1 2804 6 view .LVU4378
+ 14789 001e C9B2     		uxtb	r1, r1
+2805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 14790              		.loc 1 2805 7 view .LVU4379
+ 14791 0020 012B     		cmp	r3, #1
+ 14792 0022 34D1     		bne	.L1146
+2806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 14793              		.loc 1 2806 7 view .LVU4380
+ 14794 0024 012A     		cmp	r2, #1
+ 14795 0026 33D1     		bne	.L1149
+2807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14796              		.loc 1 2807 7 view .LVU4381
+ 14797 0028 0129     		cmp	r1, #1
+ 14798 002a 01D0     		beq	.L1153
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14799              		.loc 1 2809 12 view .LVU4382
+ 14800 002c 1046     		mov	r0, r2
+ 14801              	.LVL1107:
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14802              		.loc 1 2809 12 view .LVU4383
+ 14803 002e 2EE0     		b	.L1146
+ 14804              	.LVL1108:
+ 14805              	.L1153:
+2813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14806              		.loc 1 2813 3 is_stmt 1 view .LVU4384
+ 14807 0030 0223     		movs	r3, #2
+ 14808              	.LVL1109:
+2813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14809              		.loc 1 2813 3 is_stmt 0 view .LVU4385
+ 14810 0032 84F83E30 		strb	r3, [r4, #62]
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14811              		.loc 1 2814 3 is_stmt 1 view .LVU4386
+ 14812 0036 84F83F30 		strb	r3, [r4, #63]
+ARM GAS  /tmp/cc0wMqvE.s 			page 467
+
+
+2815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14813              		.loc 1 2815 3 view .LVU4387
+ 14814 003a 84F84430 		strb	r3, [r4, #68]
+2816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14815              		.loc 1 2816 3 view .LVU4388
+ 14816 003e 84F84530 		strb	r3, [r4, #69]
+2827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14817              		.loc 1 2827 3 view .LVU4389
+ 14818 0042 0021     		movs	r1, #0
+ 14819              	.LVL1110:
+2827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14820              		.loc 1 2827 3 is_stmt 0 view .LVU4390
+ 14821 0044 2068     		ldr	r0, [r4]
+ 14822              	.LVL1111:
+2827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14823              		.loc 1 2827 3 view .LVU4391
+ 14824 0046 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14825              	.LVL1112:
+2828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14826              		.loc 1 2828 3 is_stmt 1 view .LVU4392
+ 14827 004a 0122     		movs	r2, #1
+ 14828 004c 0421     		movs	r1, #4
+ 14829 004e 2068     		ldr	r0, [r4]
+ 14830 0050 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14831              	.LVL1113:
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14832              		.loc 1 2830 3 view .LVU4393
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14833              		.loc 1 2830 7 is_stmt 0 view .LVU4394
+ 14834 0054 2368     		ldr	r3, [r4]
+ 14835 0056 0F4A     		ldr	r2, .L1154
+ 14836 0058 9342     		cmp	r3, r2
+ 14837 005a 11D0     		beq	.L1147
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14838              		.loc 1 2830 7 discriminator 2 view .LVU4395
+ 14839 005c 02F50062 		add	r2, r2, #2048
+ 14840 0060 9342     		cmp	r3, r2
+ 14841 0062 0DD0     		beq	.L1147
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14842              		.loc 1 2830 7 discriminator 4 view .LVU4396
+ 14843 0064 02F54062 		add	r2, r2, #3072
+ 14844 0068 9342     		cmp	r3, r2
+ 14845 006a 09D0     		beq	.L1147
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14846              		.loc 1 2830 7 discriminator 6 view .LVU4397
+ 14847 006c 02F58062 		add	r2, r2, #1024
+ 14848 0070 9342     		cmp	r3, r2
+ 14849 0072 05D0     		beq	.L1147
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14850              		.loc 1 2830 7 discriminator 8 view .LVU4398
+ 14851 0074 02F58062 		add	r2, r2, #1024
+ 14852 0078 9342     		cmp	r3, r2
+ 14853 007a 01D0     		beq	.L1147
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 14854              		.loc 1 2837 10 view .LVU4399
+ 14855 007c 0020     		movs	r0, #0
+ 14856 007e 06E0     		b	.L1146
+ARM GAS  /tmp/cc0wMqvE.s 			page 468
+
+
+ 14857              	.L1147:
+2833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14858              		.loc 1 2833 5 is_stmt 1 view .LVU4400
+ 14859 0080 5A6C     		ldr	r2, [r3, #68]
+ 14860 0082 42F40042 		orr	r2, r2, #32768
+ 14861 0086 5A64     		str	r2, [r3, #68]
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 14862              		.loc 1 2837 10 is_stmt 0 view .LVU4401
+ 14863 0088 0020     		movs	r0, #0
+ 14864 008a 00E0     		b	.L1146
+ 14865              	.LVL1114:
+ 14866              	.L1148:
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14867              		.loc 1 2809 12 view .LVU4402
+ 14868 008c 0120     		movs	r0, #1
+ 14869              	.LVL1115:
+ 14870              	.L1146:
+2838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14871              		.loc 1 2838 1 view .LVU4403
+ 14872 008e 10BD     		pop	{r4, pc}
+ 14873              	.LVL1116:
+ 14874              	.L1149:
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14875              		.loc 1 2809 12 view .LVU4404
+ 14876 0090 1846     		mov	r0, r3
+ 14877              	.LVL1117:
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14878              		.loc 1 2809 12 view .LVU4405
+ 14879 0092 FCE7     		b	.L1146
+ 14880              	.L1155:
+ 14881              		.align	2
+ 14882              	.L1154:
+ 14883 0094 002C0140 		.word	1073818624
+ 14884              		.cfi_endproc
+ 14885              	.LFE373:
+ 14887              		.section	.text.HAL_TIM_OnePulse_Stop,"ax",%progbits
+ 14888              		.align	1
+ 14889              		.global	HAL_TIM_OnePulse_Stop
+ 14890              		.syntax unified
+ 14891              		.thumb
+ 14892              		.thumb_func
+ 14894              	HAL_TIM_OnePulse_Stop:
+ 14895              	.LVL1118:
+ 14896              	.LFB374:
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 14897              		.loc 1 2851 1 is_stmt 1 view -0
+ 14898              		.cfi_startproc
+ 14899              		@ args = 0, pretend = 0, frame = 0
+ 14900              		@ frame_needed = 0, uses_anonymous_args = 0
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 14901              		.loc 1 2851 1 is_stmt 0 view .LVU4407
+ 14902 0000 10B5     		push	{r4, lr}
+ 14903              	.LCFI104:
+ 14904              		.cfi_def_cfa_offset 8
+ 14905              		.cfi_offset 4, -8
+ 14906              		.cfi_offset 14, -4
+ 14907 0002 0446     		mov	r4, r0
+ARM GAS  /tmp/cc0wMqvE.s 			page 469
+
+
+2853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14908              		.loc 1 2853 3 is_stmt 1 view .LVU4408
+2861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 14909              		.loc 1 2861 3 view .LVU4409
+ 14910 0004 0022     		movs	r2, #0
+ 14911 0006 1146     		mov	r1, r2
+ 14912              	.LVL1119:
+2861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 14913              		.loc 1 2861 3 is_stmt 0 view .LVU4410
+ 14914 0008 0068     		ldr	r0, [r0]
+ 14915              	.LVL1120:
+2861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 14916              		.loc 1 2861 3 view .LVU4411
+ 14917 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14918              	.LVL1121:
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14919              		.loc 1 2862 3 is_stmt 1 view .LVU4412
+ 14920 000e 0022     		movs	r2, #0
+ 14921 0010 0421     		movs	r1, #4
+ 14922 0012 2068     		ldr	r0, [r4]
+ 14923 0014 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14924              	.LVL1122:
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14925              		.loc 1 2864 3 view .LVU4413
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14926              		.loc 1 2864 7 is_stmt 0 view .LVU4414
+ 14927 0018 2368     		ldr	r3, [r4]
+ 14928 001a 1D4A     		ldr	r2, .L1161
+ 14929 001c 9342     		cmp	r3, r2
+ 14930 001e 0FD0     		beq	.L1157
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14931              		.loc 1 2864 7 discriminator 2 view .LVU4415
+ 14932 0020 02F50062 		add	r2, r2, #2048
+ 14933 0024 9342     		cmp	r3, r2
+ 14934 0026 0BD0     		beq	.L1157
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14935              		.loc 1 2864 7 discriminator 4 view .LVU4416
+ 14936 0028 02F54062 		add	r2, r2, #3072
+ 14937 002c 9342     		cmp	r3, r2
+ 14938 002e 07D0     		beq	.L1157
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14939              		.loc 1 2864 7 discriminator 6 view .LVU4417
+ 14940 0030 02F58062 		add	r2, r2, #1024
+ 14941 0034 9342     		cmp	r3, r2
+ 14942 0036 03D0     		beq	.L1157
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 14943              		.loc 1 2864 7 discriminator 8 view .LVU4418
+ 14944 0038 02F58062 		add	r2, r2, #1024
+ 14945 003c 9342     		cmp	r3, r2
+ 14946 003e 0DD1     		bne	.L1158
+ 14947              	.L1157:
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14948              		.loc 1 2867 5 is_stmt 1 view .LVU4419
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14949              		.loc 1 2867 5 view .LVU4420
+ 14950 0040 196A     		ldr	r1, [r3, #32]
+ 14951 0042 41F21112 		movw	r2, #4369
+ARM GAS  /tmp/cc0wMqvE.s 			page 470
+
+
+ 14952 0046 1142     		tst	r1, r2
+ 14953 0048 08D1     		bne	.L1158
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14954              		.loc 1 2867 5 discriminator 1 view .LVU4421
+ 14955 004a 196A     		ldr	r1, [r3, #32]
+ 14956 004c 44F24442 		movw	r2, #17476
+ 14957 0050 1142     		tst	r1, r2
+ 14958 0052 03D1     		bne	.L1158
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14959              		.loc 1 2867 5 discriminator 3 view .LVU4422
+ 14960 0054 5A6C     		ldr	r2, [r3, #68]
+ 14961 0056 22F40042 		bic	r2, r2, #32768
+ 14962 005a 5A64     		str	r2, [r3, #68]
+ 14963              	.L1158:
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 14964              		.loc 1 2867 5 discriminator 5 view .LVU4423
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14965              		.loc 1 2871 3 discriminator 5 view .LVU4424
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14966              		.loc 1 2871 3 discriminator 5 view .LVU4425
+ 14967 005c 2368     		ldr	r3, [r4]
+ 14968 005e 196A     		ldr	r1, [r3, #32]
+ 14969 0060 41F21112 		movw	r2, #4369
+ 14970 0064 1142     		tst	r1, r2
+ 14971 0066 08D1     		bne	.L1159
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14972              		.loc 1 2871 3 discriminator 1 view .LVU4426
+ 14973 0068 196A     		ldr	r1, [r3, #32]
+ 14974 006a 44F24442 		movw	r2, #17476
+ 14975 006e 1142     		tst	r1, r2
+ 14976 0070 03D1     		bne	.L1159
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14977              		.loc 1 2871 3 discriminator 3 view .LVU4427
+ 14978 0072 1A68     		ldr	r2, [r3]
+ 14979 0074 22F00102 		bic	r2, r2, #1
+ 14980 0078 1A60     		str	r2, [r3]
+ 14981              	.L1159:
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14982              		.loc 1 2871 3 discriminator 5 view .LVU4428
+2874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 14983              		.loc 1 2874 3 discriminator 5 view .LVU4429
+ 14984 007a 0123     		movs	r3, #1
+ 14985 007c 84F83E30 		strb	r3, [r4, #62]
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 14986              		.loc 1 2875 3 discriminator 5 view .LVU4430
+ 14987 0080 84F83F30 		strb	r3, [r4, #63]
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 14988              		.loc 1 2876 3 discriminator 5 view .LVU4431
+ 14989 0084 84F84430 		strb	r3, [r4, #68]
+2877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14990              		.loc 1 2877 3 discriminator 5 view .LVU4432
+ 14991 0088 84F84530 		strb	r3, [r4, #69]
+2880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 14992              		.loc 1 2880 3 discriminator 5 view .LVU4433
+2881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14993              		.loc 1 2881 1 is_stmt 0 discriminator 5 view .LVU4434
+ 14994 008c 0020     		movs	r0, #0
+ARM GAS  /tmp/cc0wMqvE.s 			page 471
+
+
+ 14995 008e 10BD     		pop	{r4, pc}
+ 14996              	.LVL1123:
+ 14997              	.L1162:
+2881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 14998              		.loc 1 2881 1 discriminator 5 view .LVU4435
+ 14999              		.align	2
+ 15000              	.L1161:
+ 15001 0090 002C0140 		.word	1073818624
+ 15002              		.cfi_endproc
+ 15003              	.LFE374:
+ 15005              		.section	.text.HAL_TIM_OnePulse_Start_IT,"ax",%progbits
+ 15006              		.align	1
+ 15007              		.global	HAL_TIM_OnePulse_Start_IT
+ 15008              		.syntax unified
+ 15009              		.thumb
+ 15010              		.thumb_func
+ 15012              	HAL_TIM_OnePulse_Start_IT:
+ 15013              	.LVL1124:
+ 15014              	.LFB375:
+2894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 15015              		.loc 1 2894 1 is_stmt 1 view -0
+ 15016              		.cfi_startproc
+ 15017              		@ args = 0, pretend = 0, frame = 0
+ 15018              		@ frame_needed = 0, uses_anonymous_args = 0
+2894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 15019              		.loc 1 2894 1 is_stmt 0 view .LVU4437
+ 15020 0000 10B5     		push	{r4, lr}
+ 15021              	.LCFI105:
+ 15022              		.cfi_def_cfa_offset 8
+ 15023              		.cfi_offset 4, -8
+ 15024              		.cfi_offset 14, -4
+ 15025 0002 0446     		mov	r4, r0
+2895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 15026              		.loc 1 2895 3 is_stmt 1 view .LVU4438
+2895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 15027              		.loc 1 2895 31 is_stmt 0 view .LVU4439
+ 15028 0004 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 15029              	.LVL1125:
+2895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 15030              		.loc 1 2895 31 view .LVU4440
+ 15031 0008 C0B2     		uxtb	r0, r0
+ 15032              	.LVL1126:
+2896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15033              		.loc 1 2896 3 is_stmt 1 view .LVU4441
+2896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15034              		.loc 1 2896 31 is_stmt 0 view .LVU4442
+ 15035 000a 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ 15036              	.LVL1127:
+2897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15037              		.loc 1 2897 3 is_stmt 1 view .LVU4443
+2897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15038              		.loc 1 2897 31 is_stmt 0 view .LVU4444
+ 15039 000e 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 15040              	.LVL1128:
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15041              		.loc 1 2898 3 is_stmt 1 view .LVU4445
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ARM GAS  /tmp/cc0wMqvE.s 			page 472
+
+
+ 15042              		.loc 1 2898 31 is_stmt 0 view .LVU4446
+ 15043 0012 94F84510 		ldrb	r1, [r4, #69]	@ zero_extendqisi2
+ 15044              	.LVL1129:
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15045              		.loc 1 2901 3 is_stmt 1 view .LVU4447
+2904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15046              		.loc 1 2904 3 view .LVU4448
+2904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15047              		.loc 1 2904 6 is_stmt 0 view .LVU4449
+ 15048 0016 0128     		cmp	r0, #1
+ 15049 0018 43D1     		bne	.L1166
+ 15050 001a DBB2     		uxtb	r3, r3
+2904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15051              		.loc 1 2904 6 view .LVU4450
+ 15052 001c D2B2     		uxtb	r2, r2
+2904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15053              		.loc 1 2904 6 view .LVU4451
+ 15054 001e C9B2     		uxtb	r1, r1
+2905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15055              		.loc 1 2905 7 view .LVU4452
+ 15056 0020 012B     		cmp	r3, #1
+ 15057 0022 3FD1     		bne	.L1164
+2906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15058              		.loc 1 2906 7 view .LVU4453
+ 15059 0024 012A     		cmp	r2, #1
+ 15060 0026 3ED1     		bne	.L1167
+2907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15061              		.loc 1 2907 7 view .LVU4454
+ 15062 0028 0129     		cmp	r1, #1
+ 15063 002a 01D0     		beq	.L1171
+2909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15064              		.loc 1 2909 12 view .LVU4455
+ 15065 002c 1046     		mov	r0, r2
+ 15066              	.LVL1130:
+2909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15067              		.loc 1 2909 12 view .LVU4456
+ 15068 002e 39E0     		b	.L1164
+ 15069              	.LVL1131:
+ 15070              	.L1171:
+2913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15071              		.loc 1 2913 3 is_stmt 1 view .LVU4457
+ 15072 0030 0223     		movs	r3, #2
+ 15073              	.LVL1132:
+2913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15074              		.loc 1 2913 3 is_stmt 0 view .LVU4458
+ 15075 0032 84F83E30 		strb	r3, [r4, #62]
+2914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15076              		.loc 1 2914 3 is_stmt 1 view .LVU4459
+ 15077 0036 84F83F30 		strb	r3, [r4, #63]
+2915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15078              		.loc 1 2915 3 view .LVU4460
+ 15079 003a 84F84430 		strb	r3, [r4, #68]
+2916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15080              		.loc 1 2916 3 view .LVU4461
+ 15081 003e 84F84530 		strb	r3, [r4, #69]
+2928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15082              		.loc 1 2928 3 view .LVU4462
+ARM GAS  /tmp/cc0wMqvE.s 			page 473
+
+
+ 15083 0042 2268     		ldr	r2, [r4]
+ 15084              	.LVL1133:
+2928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15085              		.loc 1 2928 3 is_stmt 0 view .LVU4463
+ 15086 0044 D368     		ldr	r3, [r2, #12]
+ 15087 0046 43F00203 		orr	r3, r3, #2
+ 15088 004a D360     		str	r3, [r2, #12]
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15089              		.loc 1 2931 3 is_stmt 1 view .LVU4464
+ 15090 004c 2268     		ldr	r2, [r4]
+ 15091 004e D368     		ldr	r3, [r2, #12]
+ 15092 0050 43F00403 		orr	r3, r3, #4
+ 15093 0054 D360     		str	r3, [r2, #12]
+2933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 15094              		.loc 1 2933 3 view .LVU4465
+ 15095 0056 0122     		movs	r2, #1
+ 15096 0058 0021     		movs	r1, #0
+ 15097              	.LVL1134:
+2933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 15098              		.loc 1 2933 3 is_stmt 0 view .LVU4466
+ 15099 005a 2068     		ldr	r0, [r4]
+ 15100              	.LVL1135:
+2933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 15101              		.loc 1 2933 3 view .LVU4467
+ 15102 005c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15103              	.LVL1136:
+2934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15104              		.loc 1 2934 3 is_stmt 1 view .LVU4468
+ 15105 0060 0122     		movs	r2, #1
+ 15106 0062 0421     		movs	r1, #4
+ 15107 0064 2068     		ldr	r0, [r4]
+ 15108 0066 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15109              	.LVL1137:
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15110              		.loc 1 2936 3 view .LVU4469
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15111              		.loc 1 2936 7 is_stmt 0 view .LVU4470
+ 15112 006a 2368     		ldr	r3, [r4]
+ 15113 006c 0F4A     		ldr	r2, .L1172
+ 15114 006e 9342     		cmp	r3, r2
+ 15115 0070 11D0     		beq	.L1165
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15116              		.loc 1 2936 7 discriminator 2 view .LVU4471
+ 15117 0072 02F50062 		add	r2, r2, #2048
+ 15118 0076 9342     		cmp	r3, r2
+ 15119 0078 0DD0     		beq	.L1165
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15120              		.loc 1 2936 7 discriminator 4 view .LVU4472
+ 15121 007a 02F54062 		add	r2, r2, #3072
+ 15122 007e 9342     		cmp	r3, r2
+ 15123 0080 09D0     		beq	.L1165
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15124              		.loc 1 2936 7 discriminator 6 view .LVU4473
+ 15125 0082 02F58062 		add	r2, r2, #1024
+ 15126 0086 9342     		cmp	r3, r2
+ 15127 0088 05D0     		beq	.L1165
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 474
+
+
+ 15128              		.loc 1 2936 7 discriminator 8 view .LVU4474
+ 15129 008a 02F58062 		add	r2, r2, #1024
+ 15130 008e 9342     		cmp	r3, r2
+ 15131 0090 01D0     		beq	.L1165
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 15132              		.loc 1 2943 10 view .LVU4475
+ 15133 0092 0020     		movs	r0, #0
+ 15134 0094 06E0     		b	.L1164
+ 15135              	.L1165:
+2939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15136              		.loc 1 2939 5 is_stmt 1 view .LVU4476
+ 15137 0096 5A6C     		ldr	r2, [r3, #68]
+ 15138 0098 42F40042 		orr	r2, r2, #32768
+ 15139 009c 5A64     		str	r2, [r3, #68]
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 15140              		.loc 1 2943 10 is_stmt 0 view .LVU4477
+ 15141 009e 0020     		movs	r0, #0
+ 15142 00a0 00E0     		b	.L1164
+ 15143              	.LVL1138:
+ 15144              	.L1166:
+2909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15145              		.loc 1 2909 12 view .LVU4478
+ 15146 00a2 0120     		movs	r0, #1
+ 15147              	.LVL1139:
+ 15148              	.L1164:
+2944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15149              		.loc 1 2944 1 view .LVU4479
+ 15150 00a4 10BD     		pop	{r4, pc}
+ 15151              	.LVL1140:
+ 15152              	.L1167:
+2909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15153              		.loc 1 2909 12 view .LVU4480
+ 15154 00a6 1846     		mov	r0, r3
+ 15155              	.LVL1141:
+2909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15156              		.loc 1 2909 12 view .LVU4481
+ 15157 00a8 FCE7     		b	.L1164
+ 15158              	.L1173:
+ 15159 00aa 00BF     		.align	2
+ 15160              	.L1172:
+ 15161 00ac 002C0140 		.word	1073818624
+ 15162              		.cfi_endproc
+ 15163              	.LFE375:
+ 15165              		.section	.text.HAL_TIM_OnePulse_Stop_IT,"ax",%progbits
+ 15166              		.align	1
+ 15167              		.global	HAL_TIM_OnePulse_Stop_IT
+ 15168              		.syntax unified
+ 15169              		.thumb
+ 15170              		.thumb_func
+ 15172              	HAL_TIM_OnePulse_Stop_IT:
+ 15173              	.LVL1142:
+ 15174              	.LFB376:
+2957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 15175              		.loc 1 2957 1 is_stmt 1 view -0
+ 15176              		.cfi_startproc
+ 15177              		@ args = 0, pretend = 0, frame = 0
+ 15178              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cc0wMqvE.s 			page 475
+
+
+2957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 15179              		.loc 1 2957 1 is_stmt 0 view .LVU4483
+ 15180 0000 10B5     		push	{r4, lr}
+ 15181              	.LCFI106:
+ 15182              		.cfi_def_cfa_offset 8
+ 15183              		.cfi_offset 4, -8
+ 15184              		.cfi_offset 14, -4
+ 15185 0002 0446     		mov	r4, r0
+2959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15186              		.loc 1 2959 3 is_stmt 1 view .LVU4484
+2962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15187              		.loc 1 2962 3 view .LVU4485
+ 15188 0004 0268     		ldr	r2, [r0]
+ 15189 0006 D368     		ldr	r3, [r2, #12]
+ 15190 0008 23F00203 		bic	r3, r3, #2
+ 15191 000c D360     		str	r3, [r2, #12]
+2965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15192              		.loc 1 2965 3 view .LVU4486
+ 15193 000e 0268     		ldr	r2, [r0]
+ 15194 0010 D368     		ldr	r3, [r2, #12]
+ 15195 0012 23F00403 		bic	r3, r3, #4
+ 15196 0016 D360     		str	r3, [r2, #12]
+2972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15197              		.loc 1 2972 3 view .LVU4487
+ 15198 0018 0022     		movs	r2, #0
+ 15199 001a 1146     		mov	r1, r2
+ 15200              	.LVL1143:
+2972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15201              		.loc 1 2972 3 is_stmt 0 view .LVU4488
+ 15202 001c 0068     		ldr	r0, [r0]
+ 15203              	.LVL1144:
+2972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15204              		.loc 1 2972 3 view .LVU4489
+ 15205 001e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15206              	.LVL1145:
+2973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15207              		.loc 1 2973 3 is_stmt 1 view .LVU4490
+ 15208 0022 0022     		movs	r2, #0
+ 15209 0024 0421     		movs	r1, #4
+ 15210 0026 2068     		ldr	r0, [r4]
+ 15211 0028 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15212              	.LVL1146:
+2975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15213              		.loc 1 2975 3 view .LVU4491
+2975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15214              		.loc 1 2975 7 is_stmt 0 view .LVU4492
+ 15215 002c 2368     		ldr	r3, [r4]
+ 15216 002e 1D4A     		ldr	r2, .L1179
+ 15217 0030 9342     		cmp	r3, r2
+ 15218 0032 0FD0     		beq	.L1175
+2975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15219              		.loc 1 2975 7 discriminator 2 view .LVU4493
+ 15220 0034 02F50062 		add	r2, r2, #2048
+ 15221 0038 9342     		cmp	r3, r2
+ 15222 003a 0BD0     		beq	.L1175
+2975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15223              		.loc 1 2975 7 discriminator 4 view .LVU4494
+ARM GAS  /tmp/cc0wMqvE.s 			page 476
+
+
+ 15224 003c 02F54062 		add	r2, r2, #3072
+ 15225 0040 9342     		cmp	r3, r2
+ 15226 0042 07D0     		beq	.L1175
+2975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15227              		.loc 1 2975 7 discriminator 6 view .LVU4495
+ 15228 0044 02F58062 		add	r2, r2, #1024
+ 15229 0048 9342     		cmp	r3, r2
+ 15230 004a 03D0     		beq	.L1175
+2975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15231              		.loc 1 2975 7 discriminator 8 view .LVU4496
+ 15232 004c 02F58062 		add	r2, r2, #1024
+ 15233 0050 9342     		cmp	r3, r2
+ 15234 0052 0DD1     		bne	.L1176
+ 15235              	.L1175:
+2978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15236              		.loc 1 2978 5 is_stmt 1 view .LVU4497
+2978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15237              		.loc 1 2978 5 view .LVU4498
+ 15238 0054 196A     		ldr	r1, [r3, #32]
+ 15239 0056 41F21112 		movw	r2, #4369
+ 15240 005a 1142     		tst	r1, r2
+ 15241 005c 08D1     		bne	.L1176
+2978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15242              		.loc 1 2978 5 discriminator 1 view .LVU4499
+ 15243 005e 196A     		ldr	r1, [r3, #32]
+ 15244 0060 44F24442 		movw	r2, #17476
+ 15245 0064 1142     		tst	r1, r2
+ 15246 0066 03D1     		bne	.L1176
+2978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15247              		.loc 1 2978 5 discriminator 3 view .LVU4500
+ 15248 0068 5A6C     		ldr	r2, [r3, #68]
+ 15249 006a 22F40042 		bic	r2, r2, #32768
+ 15250 006e 5A64     		str	r2, [r3, #68]
+ 15251              	.L1176:
+2978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15252              		.loc 1 2978 5 discriminator 5 view .LVU4501
+2982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15253              		.loc 1 2982 3 discriminator 5 view .LVU4502
+2982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15254              		.loc 1 2982 3 discriminator 5 view .LVU4503
+ 15255 0070 2368     		ldr	r3, [r4]
+ 15256 0072 196A     		ldr	r1, [r3, #32]
+ 15257 0074 41F21112 		movw	r2, #4369
+ 15258 0078 1142     		tst	r1, r2
+ 15259 007a 08D1     		bne	.L1177
+2982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15260              		.loc 1 2982 3 discriminator 1 view .LVU4504
+ 15261 007c 196A     		ldr	r1, [r3, #32]
+ 15262 007e 44F24442 		movw	r2, #17476
+ 15263 0082 1142     		tst	r1, r2
+ 15264 0084 03D1     		bne	.L1177
+2982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15265              		.loc 1 2982 3 discriminator 3 view .LVU4505
+ 15266 0086 1A68     		ldr	r2, [r3]
+ 15267 0088 22F00102 		bic	r2, r2, #1
+ 15268 008c 1A60     		str	r2, [r3]
+ 15269              	.L1177:
+ARM GAS  /tmp/cc0wMqvE.s 			page 477
+
+
+2982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15270              		.loc 1 2982 3 discriminator 5 view .LVU4506
+2985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 15271              		.loc 1 2985 3 discriminator 5 view .LVU4507
+ 15272 008e 0123     		movs	r3, #1
+ 15273 0090 84F83E30 		strb	r3, [r4, #62]
+2986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 15274              		.loc 1 2986 3 discriminator 5 view .LVU4508
+ 15275 0094 84F83F30 		strb	r3, [r4, #63]
+2987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 15276              		.loc 1 2987 3 discriminator 5 view .LVU4509
+ 15277 0098 84F84430 		strb	r3, [r4, #68]
+2988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15278              		.loc 1 2988 3 discriminator 5 view .LVU4510
+ 15279 009c 84F84530 		strb	r3, [r4, #69]
+2991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 15280              		.loc 1 2991 3 discriminator 5 view .LVU4511
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15281              		.loc 1 2992 1 is_stmt 0 discriminator 5 view .LVU4512
+ 15282 00a0 0020     		movs	r0, #0
+ 15283 00a2 10BD     		pop	{r4, pc}
+ 15284              	.LVL1147:
+ 15285              	.L1180:
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15286              		.loc 1 2992 1 discriminator 5 view .LVU4513
+ 15287              		.align	2
+ 15288              	.L1179:
+ 15289 00a4 002C0140 		.word	1073818624
+ 15290              		.cfi_endproc
+ 15291              	.LFE376:
+ 15293              		.section	.text.HAL_TIM_Encoder_Start,"ax",%progbits
+ 15294              		.align	1
+ 15295              		.global	HAL_TIM_Encoder_Start
+ 15296              		.syntax unified
+ 15297              		.thumb
+ 15298              		.thumb_func
+ 15300              	HAL_TIM_Encoder_Start:
+ 15301              	.LVL1148:
+ 15302              	.LFB381:
+3230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 15303              		.loc 1 3230 1 is_stmt 1 view -0
+ 15304              		.cfi_startproc
+ 15305              		@ args = 0, pretend = 0, frame = 0
+ 15306              		@ frame_needed = 0, uses_anonymous_args = 0
+3230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 15307              		.loc 1 3230 1 is_stmt 0 view .LVU4515
+ 15308 0000 38B5     		push	{r3, r4, r5, lr}
+ 15309              	.LCFI107:
+ 15310              		.cfi_def_cfa_offset 16
+ 15311              		.cfi_offset 3, -16
+ 15312              		.cfi_offset 4, -12
+ 15313              		.cfi_offset 5, -8
+ 15314              		.cfi_offset 14, -4
+ 15315 0002 0446     		mov	r4, r0
+3231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 15316              		.loc 1 3231 3 is_stmt 1 view .LVU4516
+3231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ARM GAS  /tmp/cc0wMqvE.s 			page 478
+
+
+ 15317              		.loc 1 3231 31 is_stmt 0 view .LVU4517
+ 15318 0004 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 15319              	.LVL1149:
+3231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 15320              		.loc 1 3231 31 view .LVU4518
+ 15321 0008 C0B2     		uxtb	r0, r0
+ 15322              	.LVL1150:
+3232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15323              		.loc 1 3232 3 is_stmt 1 view .LVU4519
+3232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15324              		.loc 1 3232 31 is_stmt 0 view .LVU4520
+ 15325 000a 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ 15326              	.LVL1151:
+3233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15327              		.loc 1 3233 3 is_stmt 1 view .LVU4521
+3233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15328              		.loc 1 3233 31 is_stmt 0 view .LVU4522
+ 15329 000e 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 15330 0012 D2B2     		uxtb	r2, r2
+ 15331              	.LVL1152:
+3234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15332              		.loc 1 3234 3 is_stmt 1 view .LVU4523
+3234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15333              		.loc 1 3234 31 is_stmt 0 view .LVU4524
+ 15334 0014 94F845C0 		ldrb	ip, [r4, #69]	@ zero_extendqisi2
+ 15335              	.LVL1153:
+3237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15336              		.loc 1 3237 3 is_stmt 1 view .LVU4525
+3240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15337              		.loc 1 3240 3 view .LVU4526
+3240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15338              		.loc 1 3240 6 is_stmt 0 view .LVU4527
+ 15339 0018 0D46     		mov	r5, r1
+ 15340 001a B1B9     		cbnz	r1, .L1182
+3242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15341              		.loc 1 3242 5 is_stmt 1 view .LVU4528
+3242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15342              		.loc 1 3242 8 is_stmt 0 view .LVU4529
+ 15343 001c 0128     		cmp	r0, #1
+ 15344 001e 49D1     		bne	.L1190
+3243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 15345              		.loc 1 3243 9 view .LVU4530
+ 15346 0020 012A     		cmp	r2, #1
+ 15347 0022 48D1     		bne	.L1183
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15348              		.loc 1 3249 7 is_stmt 1 view .LVU4531
+ 15349 0024 0223     		movs	r3, #2
+ 15350              	.LVL1154:
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15351              		.loc 1 3249 7 is_stmt 0 view .LVU4532
+ 15352 0026 84F83E30 		strb	r3, [r4, #62]
+3250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15353              		.loc 1 3250 7 is_stmt 1 view .LVU4533
+ 15354 002a 84F84430 		strb	r3, [r4, #68]
+ 15355              	.LVL1155:
+ 15356              	.L1184:
+3285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 479
+
+
+ 15357              		.loc 1 3285 3 view .LVU4534
+ 15358 002e 7DB3     		cbz	r5, .L1186
+ 15359 0030 042D     		cmp	r5, #4
+ 15360 0032 39D0     		beq	.L1187
+3301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 15361              		.loc 1 3301 7 view .LVU4535
+ 15362 0034 0122     		movs	r2, #1
+ 15363              	.LVL1156:
+3301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 15364              		.loc 1 3301 7 is_stmt 0 view .LVU4536
+ 15365 0036 0021     		movs	r1, #0
+ 15366              	.LVL1157:
+3301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 15367              		.loc 1 3301 7 view .LVU4537
+ 15368 0038 2068     		ldr	r0, [r4]
+ 15369              	.LVL1158:
+3301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 15370              		.loc 1 3301 7 view .LVU4538
+ 15371 003a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15372              	.LVL1159:
+3302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15373              		.loc 1 3302 7 is_stmt 1 view .LVU4539
+ 15374 003e 0122     		movs	r2, #1
+ 15375 0040 0421     		movs	r1, #4
+ 15376 0042 2068     		ldr	r0, [r4]
+ 15377 0044 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15378              	.LVL1160:
+3303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15379              		.loc 1 3303 7 view .LVU4540
+ 15380 0048 27E0     		b	.L1189
+ 15381              	.LVL1161:
+ 15382              	.L1182:
+3303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15383              		.loc 1 3303 7 is_stmt 0 view .LVU4541
+ 15384 004a DBB2     		uxtb	r3, r3
+3303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15385              		.loc 1 3303 7 view .LVU4542
+ 15386 004c 5FFA8CFC 		uxtb	ip, ip
+3253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15387              		.loc 1 3253 8 is_stmt 1 view .LVU4543
+3253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15388              		.loc 1 3253 11 is_stmt 0 view .LVU4544
+ 15389 0050 0429     		cmp	r1, #4
+ 15390 0052 12D0     		beq	.L1198
+3268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15391              		.loc 1 3268 5 is_stmt 1 view .LVU4545
+3268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15392              		.loc 1 3268 8 is_stmt 0 view .LVU4546
+ 15393 0054 0128     		cmp	r0, #1
+ 15394 0056 33D1     		bne	.L1193
+3269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15395              		.loc 1 3269 9 view .LVU4547
+ 15396 0058 012B     		cmp	r3, #1
+ 15397 005a 2CD1     		bne	.L1183
+3270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15398              		.loc 1 3270 9 view .LVU4548
+ 15399 005c 012A     		cmp	r2, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 480
+
+
+ 15400 005e 31D1     		bne	.L1194
+3271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 15401              		.loc 1 3271 9 view .LVU4549
+ 15402 0060 BCF1010F 		cmp	ip, #1
+ 15403 0064 30D1     		bne	.L1195
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15404              		.loc 1 3277 7 is_stmt 1 view .LVU4550
+ 15405 0066 0223     		movs	r3, #2
+ 15406              	.LVL1162:
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15407              		.loc 1 3277 7 is_stmt 0 view .LVU4551
+ 15408 0068 84F83E30 		strb	r3, [r4, #62]
+3278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15409              		.loc 1 3278 7 is_stmt 1 view .LVU4552
+ 15410 006c 84F83F30 		strb	r3, [r4, #63]
+3279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15411              		.loc 1 3279 7 view .LVU4553
+ 15412 0070 84F84430 		strb	r3, [r4, #68]
+3280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15413              		.loc 1 3280 7 view .LVU4554
+ 15414 0074 84F84530 		strb	r3, [r4, #69]
+ 15415 0078 D9E7     		b	.L1184
+ 15416              	.LVL1163:
+ 15417              	.L1198:
+3255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15418              		.loc 1 3255 5 view .LVU4555
+3255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15419              		.loc 1 3255 8 is_stmt 0 view .LVU4556
+ 15420 007a 012B     		cmp	r3, #1
+ 15421 007c 1CD1     		bne	.L1191
+3256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 15422              		.loc 1 3256 9 view .LVU4557
+ 15423 007e BCF1010F 		cmp	ip, #1
+ 15424 0082 1BD1     		bne	.L1192
+3262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15425              		.loc 1 3262 7 is_stmt 1 view .LVU4558
+ 15426 0084 0223     		movs	r3, #2
+ 15427              	.LVL1164:
+3262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15428              		.loc 1 3262 7 is_stmt 0 view .LVU4559
+ 15429 0086 84F83F30 		strb	r3, [r4, #63]
+3263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15430              		.loc 1 3263 7 is_stmt 1 view .LVU4560
+ 15431 008a 84F84530 		strb	r3, [r4, #69]
+ 15432 008e CEE7     		b	.L1184
+ 15433              	.LVL1165:
+ 15434              	.L1186:
+3289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15435              		.loc 1 3289 7 view .LVU4561
+ 15436 0090 0122     		movs	r2, #1
+ 15437              	.LVL1166:
+3289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15438              		.loc 1 3289 7 is_stmt 0 view .LVU4562
+ 15439 0092 0021     		movs	r1, #0
+ 15440              	.LVL1167:
+3289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15441              		.loc 1 3289 7 view .LVU4563
+ARM GAS  /tmp/cc0wMqvE.s 			page 481
+
+
+ 15442 0094 2068     		ldr	r0, [r4]
+ 15443              	.LVL1168:
+3289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15444              		.loc 1 3289 7 view .LVU4564
+ 15445 0096 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15446              	.LVL1169:
+3290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15447              		.loc 1 3290 7 is_stmt 1 view .LVU4565
+ 15448              	.L1189:
+3307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15449              		.loc 1 3307 3 view .LVU4566
+ 15450 009a 2268     		ldr	r2, [r4]
+ 15451 009c 1368     		ldr	r3, [r2]
+ 15452 009e 43F00103 		orr	r3, r3, #1
+ 15453 00a2 1360     		str	r3, [r2]
+3310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 15454              		.loc 1 3310 3 view .LVU4567
+3310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 15455              		.loc 1 3310 10 is_stmt 0 view .LVU4568
+ 15456 00a4 0020     		movs	r0, #0
+ 15457 00a6 06E0     		b	.L1183
+ 15458              	.LVL1170:
+ 15459              	.L1187:
+3295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15460              		.loc 1 3295 7 is_stmt 1 view .LVU4569
+ 15461 00a8 0122     		movs	r2, #1
+ 15462              	.LVL1171:
+3295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15463              		.loc 1 3295 7 is_stmt 0 view .LVU4570
+ 15464 00aa 0421     		movs	r1, #4
+ 15465              	.LVL1172:
+3295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15466              		.loc 1 3295 7 view .LVU4571
+ 15467 00ac 2068     		ldr	r0, [r4]
+ 15468              	.LVL1173:
+3295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15469              		.loc 1 3295 7 view .LVU4572
+ 15470 00ae FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15471              	.LVL1174:
+3296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15472              		.loc 1 3296 7 is_stmt 1 view .LVU4573
+ 15473 00b2 F2E7     		b	.L1189
+ 15474              	.LVL1175:
+ 15475              	.L1190:
+3245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15476              		.loc 1 3245 14 is_stmt 0 view .LVU4574
+ 15477 00b4 0120     		movs	r0, #1
+ 15478              	.LVL1176:
+ 15479              	.L1183:
+3311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15480              		.loc 1 3311 1 view .LVU4575
+ 15481 00b6 38BD     		pop	{r3, r4, r5, pc}
+ 15482              	.LVL1177:
+ 15483              	.L1191:
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15484              		.loc 1 3258 14 view .LVU4576
+ 15485 00b8 0120     		movs	r0, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 482
+
+
+ 15486              	.LVL1178:
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15487              		.loc 1 3258 14 view .LVU4577
+ 15488 00ba FCE7     		b	.L1183
+ 15489              	.LVL1179:
+ 15490              	.L1192:
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15491              		.loc 1 3258 14 view .LVU4578
+ 15492 00bc 1846     		mov	r0, r3
+ 15493              	.LVL1180:
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15494              		.loc 1 3258 14 view .LVU4579
+ 15495 00be FAE7     		b	.L1183
+ 15496              	.LVL1181:
+ 15497              	.L1193:
+3273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15498              		.loc 1 3273 14 view .LVU4580
+ 15499 00c0 0120     		movs	r0, #1
+ 15500              	.LVL1182:
+3273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15501              		.loc 1 3273 14 view .LVU4581
+ 15502 00c2 F8E7     		b	.L1183
+ 15503              	.LVL1183:
+ 15504              	.L1194:
+3273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15505              		.loc 1 3273 14 view .LVU4582
+ 15506 00c4 1846     		mov	r0, r3
+ 15507              	.LVL1184:
+3273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15508              		.loc 1 3273 14 view .LVU4583
+ 15509 00c6 F6E7     		b	.L1183
+ 15510              	.LVL1185:
+ 15511              	.L1195:
+3273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15512              		.loc 1 3273 14 view .LVU4584
+ 15513 00c8 1046     		mov	r0, r2
+ 15514              	.LVL1186:
+3273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15515              		.loc 1 3273 14 view .LVU4585
+ 15516 00ca F4E7     		b	.L1183
+ 15517              		.cfi_endproc
+ 15518              	.LFE381:
+ 15520              		.section	.text.HAL_TIM_Encoder_Stop,"ax",%progbits
+ 15521              		.align	1
+ 15522              		.global	HAL_TIM_Encoder_Stop
+ 15523              		.syntax unified
+ 15524              		.thumb
+ 15525              		.thumb_func
+ 15527              	HAL_TIM_Encoder_Stop:
+ 15528              	.LVL1187:
+ 15529              	.LFB382:
+3324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 15530              		.loc 1 3324 1 is_stmt 1 view -0
+ 15531              		.cfi_startproc
+ 15532              		@ args = 0, pretend = 0, frame = 0
+ 15533              		@ frame_needed = 0, uses_anonymous_args = 0
+3324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ARM GAS  /tmp/cc0wMqvE.s 			page 483
+
+
+ 15534              		.loc 1 3324 1 is_stmt 0 view .LVU4587
+ 15535 0000 38B5     		push	{r3, r4, r5, lr}
+ 15536              	.LCFI108:
+ 15537              		.cfi_def_cfa_offset 16
+ 15538              		.cfi_offset 3, -16
+ 15539              		.cfi_offset 4, -12
+ 15540              		.cfi_offset 5, -8
+ 15541              		.cfi_offset 14, -4
+ 15542 0002 0446     		mov	r4, r0
+3326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15543              		.loc 1 3326 3 is_stmt 1 view .LVU4588
+3330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15544              		.loc 1 3330 3 view .LVU4589
+ 15545 0004 0D46     		mov	r5, r1
+ 15546 0006 61B1     		cbz	r1, .L1200
+ 15547 0008 0429     		cmp	r1, #4
+ 15548 000a 2BD0     		beq	.L1201
+3346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15549              		.loc 1 3346 7 view .LVU4590
+ 15550 000c 0022     		movs	r2, #0
+ 15551 000e 1146     		mov	r1, r2
+ 15552              	.LVL1188:
+3346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15553              		.loc 1 3346 7 is_stmt 0 view .LVU4591
+ 15554 0010 0068     		ldr	r0, [r0]
+ 15555              	.LVL1189:
+3346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15556              		.loc 1 3346 7 view .LVU4592
+ 15557 0012 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15558              	.LVL1190:
+3347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15559              		.loc 1 3347 7 is_stmt 1 view .LVU4593
+ 15560 0016 0022     		movs	r2, #0
+ 15561 0018 0421     		movs	r1, #4
+ 15562 001a 2068     		ldr	r0, [r4]
+ 15563 001c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15564              	.LVL1191:
+3348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15565              		.loc 1 3348 7 view .LVU4594
+ 15566 0020 04E0     		b	.L1203
+ 15567              	.LVL1192:
+ 15568              	.L1200:
+3334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15569              		.loc 1 3334 7 view .LVU4595
+ 15570 0022 0022     		movs	r2, #0
+ 15571 0024 1146     		mov	r1, r2
+ 15572              	.LVL1193:
+3334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15573              		.loc 1 3334 7 is_stmt 0 view .LVU4596
+ 15574 0026 0068     		ldr	r0, [r0]
+ 15575              	.LVL1194:
+3334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15576              		.loc 1 3334 7 view .LVU4597
+ 15577 0028 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15578              	.LVL1195:
+3335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15579              		.loc 1 3335 7 is_stmt 1 view .LVU4598
+ARM GAS  /tmp/cc0wMqvE.s 			page 484
+
+
+ 15580              	.L1203:
+3353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15581              		.loc 1 3353 3 view .LVU4599
+3353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15582              		.loc 1 3353 3 view .LVU4600
+ 15583 002c 2368     		ldr	r3, [r4]
+ 15584 002e 196A     		ldr	r1, [r3, #32]
+ 15585 0030 41F21112 		movw	r2, #4369
+ 15586 0034 1142     		tst	r1, r2
+ 15587 0036 08D1     		bne	.L1204
+3353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15588              		.loc 1 3353 3 discriminator 1 view .LVU4601
+ 15589 0038 196A     		ldr	r1, [r3, #32]
+ 15590 003a 44F24442 		movw	r2, #17476
+ 15591 003e 1142     		tst	r1, r2
+ 15592 0040 03D1     		bne	.L1204
+3353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15593              		.loc 1 3353 3 discriminator 3 view .LVU4602
+ 15594 0042 1A68     		ldr	r2, [r3]
+ 15595 0044 22F00102 		bic	r2, r2, #1
+ 15596 0048 1A60     		str	r2, [r3]
+ 15597              	.L1204:
+3353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15598              		.loc 1 3353 3 discriminator 5 view .LVU4603
+3356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15599              		.loc 1 3356 3 discriminator 5 view .LVU4604
+3356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15600              		.loc 1 3356 6 is_stmt 0 discriminator 5 view .LVU4605
+ 15601 004a 8DB1     		cbz	r5, .L1205
+3356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15602              		.loc 1 3356 34 discriminator 1 view .LVU4606
+ 15603 004c 042D     		cmp	r5, #4
+ 15604 004e 16D0     		beq	.L1212
+3363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 15605              		.loc 1 3363 5 is_stmt 1 view .LVU4607
+ 15606 0050 0123     		movs	r3, #1
+ 15607 0052 84F83E30 		strb	r3, [r4, #62]
+3364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 15608              		.loc 1 3364 5 view .LVU4608
+ 15609 0056 84F83F30 		strb	r3, [r4, #63]
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 15610              		.loc 1 3365 5 view .LVU4609
+ 15611 005a 84F84430 		strb	r3, [r4, #68]
+3366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15612              		.loc 1 3366 5 view .LVU4610
+ 15613 005e 84F84530 		strb	r3, [r4, #69]
+ 15614 0062 0AE0     		b	.L1208
+ 15615              	.LVL1196:
+ 15616              	.L1201:
+3340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15617              		.loc 1 3340 7 view .LVU4611
+ 15618 0064 0022     		movs	r2, #0
+ 15619 0066 0421     		movs	r1, #4
+ 15620              	.LVL1197:
+3340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15621              		.loc 1 3340 7 is_stmt 0 view .LVU4612
+ 15622 0068 0068     		ldr	r0, [r0]
+ARM GAS  /tmp/cc0wMqvE.s 			page 485
+
+
+ 15623              	.LVL1198:
+3340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15624              		.loc 1 3340 7 view .LVU4613
+ 15625 006a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15626              	.LVL1199:
+3341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15627              		.loc 1 3341 7 is_stmt 1 view .LVU4614
+ 15628 006e DDE7     		b	.L1203
+ 15629              	.L1205:
+3358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15630              		.loc 1 3358 5 discriminator 1 view .LVU4615
+ 15631 0070 0123     		movs	r3, #1
+ 15632 0072 84F83E30 		strb	r3, [r4, #62]
+3359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15633              		.loc 1 3359 5 discriminator 1 view .LVU4616
+ 15634 0076 84F84430 		strb	r3, [r4, #68]
+ 15635              	.L1208:
+3370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 15636              		.loc 1 3370 3 view .LVU4617
+3371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15637              		.loc 1 3371 1 is_stmt 0 view .LVU4618
+ 15638 007a 0020     		movs	r0, #0
+ 15639 007c 38BD     		pop	{r3, r4, r5, pc}
+ 15640              	.LVL1200:
+ 15641              	.L1212:
+3358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15642              		.loc 1 3358 5 is_stmt 1 view .LVU4619
+ 15643 007e 0123     		movs	r3, #1
+ 15644 0080 84F83F30 		strb	r3, [r4, #63]
+3359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15645              		.loc 1 3359 5 view .LVU4620
+ 15646 0084 84F84530 		strb	r3, [r4, #69]
+ 15647 0088 F7E7     		b	.L1208
+ 15648              		.cfi_endproc
+ 15649              	.LFE382:
+ 15651              		.section	.text.HAL_TIM_Encoder_Start_IT,"ax",%progbits
+ 15652              		.align	1
+ 15653              		.global	HAL_TIM_Encoder_Start_IT
+ 15654              		.syntax unified
+ 15655              		.thumb
+ 15656              		.thumb_func
+ 15658              	HAL_TIM_Encoder_Start_IT:
+ 15659              	.LVL1201:
+ 15660              	.LFB383:
+3384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 15661              		.loc 1 3384 1 view -0
+ 15662              		.cfi_startproc
+ 15663              		@ args = 0, pretend = 0, frame = 0
+ 15664              		@ frame_needed = 0, uses_anonymous_args = 0
+3384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 15665              		.loc 1 3384 1 is_stmt 0 view .LVU4622
+ 15666 0000 38B5     		push	{r3, r4, r5, lr}
+ 15667              	.LCFI109:
+ 15668              		.cfi_def_cfa_offset 16
+ 15669              		.cfi_offset 3, -16
+ 15670              		.cfi_offset 4, -12
+ 15671              		.cfi_offset 5, -8
+ARM GAS  /tmp/cc0wMqvE.s 			page 486
+
+
+ 15672              		.cfi_offset 14, -4
+ 15673 0002 0446     		mov	r4, r0
+3385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 15674              		.loc 1 3385 3 is_stmt 1 view .LVU4623
+3385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 15675              		.loc 1 3385 31 is_stmt 0 view .LVU4624
+ 15676 0004 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 15677              	.LVL1202:
+3385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 15678              		.loc 1 3385 31 view .LVU4625
+ 15679 0008 C0B2     		uxtb	r0, r0
+ 15680              	.LVL1203:
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15681              		.loc 1 3386 3 is_stmt 1 view .LVU4626
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15682              		.loc 1 3386 31 is_stmt 0 view .LVU4627
+ 15683 000a 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ 15684              	.LVL1204:
+3387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15685              		.loc 1 3387 3 is_stmt 1 view .LVU4628
+3387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15686              		.loc 1 3387 31 is_stmt 0 view .LVU4629
+ 15687 000e 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 15688 0012 D2B2     		uxtb	r2, r2
+ 15689              	.LVL1205:
+3388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15690              		.loc 1 3388 3 is_stmt 1 view .LVU4630
+3388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15691              		.loc 1 3388 31 is_stmt 0 view .LVU4631
+ 15692 0014 94F845C0 		ldrb	ip, [r4, #69]	@ zero_extendqisi2
+ 15693              	.LVL1206:
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15694              		.loc 1 3391 3 is_stmt 1 view .LVU4632
+3394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15695              		.loc 1 3394 3 view .LVU4633
+3394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15696              		.loc 1 3394 6 is_stmt 0 view .LVU4634
+ 15697 0018 0D46     		mov	r5, r1
+ 15698 001a 09BB     		cbnz	r1, .L1214
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15699              		.loc 1 3396 5 is_stmt 1 view .LVU4635
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15700              		.loc 1 3396 8 is_stmt 0 view .LVU4636
+ 15701 001c 0128     		cmp	r0, #1
+ 15702 001e 5ED1     		bne	.L1222
+3397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 15703              		.loc 1 3397 9 view .LVU4637
+ 15704 0020 012A     		cmp	r2, #1
+ 15705 0022 5DD1     		bne	.L1215
+3403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15706              		.loc 1 3403 7 is_stmt 1 view .LVU4638
+ 15707 0024 0223     		movs	r3, #2
+ 15708              	.LVL1207:
+3403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15709              		.loc 1 3403 7 is_stmt 0 view .LVU4639
+ 15710 0026 84F83E30 		strb	r3, [r4, #62]
+3404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ARM GAS  /tmp/cc0wMqvE.s 			page 487
+
+
+ 15711              		.loc 1 3404 7 is_stmt 1 view .LVU4640
+ 15712 002a 84F84430 		strb	r3, [r4, #68]
+ 15713              	.LVL1208:
+ 15714              	.L1216:
+3440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15715              		.loc 1 3440 3 view .LVU4641
+ 15716 002e 002D     		cmp	r5, #0
+ 15717 0030 39D0     		beq	.L1218
+ 15718 0032 042D     		cmp	r5, #4
+ 15719 0034 48D0     		beq	.L1219
+3458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 15720              		.loc 1 3458 7 view .LVU4642
+ 15721 0036 0122     		movs	r2, #1
+ 15722              	.LVL1209:
+3458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 15723              		.loc 1 3458 7 is_stmt 0 view .LVU4643
+ 15724 0038 0021     		movs	r1, #0
+ 15725              	.LVL1210:
+3458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 15726              		.loc 1 3458 7 view .LVU4644
+ 15727 003a 2068     		ldr	r0, [r4]
+ 15728              	.LVL1211:
+3458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 15729              		.loc 1 3458 7 view .LVU4645
+ 15730 003c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15731              	.LVL1212:
+3459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 15732              		.loc 1 3459 7 is_stmt 1 view .LVU4646
+ 15733 0040 0122     		movs	r2, #1
+ 15734 0042 0421     		movs	r1, #4
+ 15735 0044 2068     		ldr	r0, [r4]
+ 15736 0046 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15737              	.LVL1213:
+3460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 15738              		.loc 1 3460 7 view .LVU4647
+ 15739 004a 2268     		ldr	r2, [r4]
+ 15740 004c D368     		ldr	r3, [r2, #12]
+ 15741 004e 43F00203 		orr	r3, r3, #2
+ 15742 0052 D360     		str	r3, [r2, #12]
+3461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15743              		.loc 1 3461 7 view .LVU4648
+ 15744 0054 2268     		ldr	r2, [r4]
+ 15745 0056 D368     		ldr	r3, [r2, #12]
+ 15746 0058 43F00403 		orr	r3, r3, #4
+ 15747 005c D360     		str	r3, [r2, #12]
+3462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15748              		.loc 1 3462 7 view .LVU4649
+ 15749 005e 2CE0     		b	.L1221
+ 15750              	.LVL1214:
+ 15751              	.L1214:
+3462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15752              		.loc 1 3462 7 is_stmt 0 view .LVU4650
+ 15753 0060 DBB2     		uxtb	r3, r3
+3462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15754              		.loc 1 3462 7 view .LVU4651
+ 15755 0062 5FFA8CFC 		uxtb	ip, ip
+3407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ARM GAS  /tmp/cc0wMqvE.s 			page 488
+
+
+ 15756              		.loc 1 3407 8 is_stmt 1 view .LVU4652
+3407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15757              		.loc 1 3407 11 is_stmt 0 view .LVU4653
+ 15758 0066 0429     		cmp	r1, #4
+ 15759 0068 12D0     		beq	.L1230
+3422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15760              		.loc 1 3422 5 is_stmt 1 view .LVU4654
+3422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15761              		.loc 1 3422 8 is_stmt 0 view .LVU4655
+ 15762 006a 0128     		cmp	r0, #1
+ 15763 006c 3DD1     		bne	.L1225
+3423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15764              		.loc 1 3423 9 view .LVU4656
+ 15765 006e 012B     		cmp	r3, #1
+ 15766 0070 36D1     		bne	.L1215
+3424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15767              		.loc 1 3424 9 view .LVU4657
+ 15768 0072 012A     		cmp	r2, #1
+ 15769 0074 3BD1     		bne	.L1226
+3425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 15770              		.loc 1 3425 9 view .LVU4658
+ 15771 0076 BCF1010F 		cmp	ip, #1
+ 15772 007a 3AD1     		bne	.L1227
+3431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15773              		.loc 1 3431 7 is_stmt 1 view .LVU4659
+ 15774 007c 0223     		movs	r3, #2
+ 15775              	.LVL1215:
+3431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15776              		.loc 1 3431 7 is_stmt 0 view .LVU4660
+ 15777 007e 84F83E30 		strb	r3, [r4, #62]
+3432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15778              		.loc 1 3432 7 is_stmt 1 view .LVU4661
+ 15779 0082 84F83F30 		strb	r3, [r4, #63]
+3433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15780              		.loc 1 3433 7 view .LVU4662
+ 15781 0086 84F84430 		strb	r3, [r4, #68]
+3434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15782              		.loc 1 3434 7 view .LVU4663
+ 15783 008a 84F84530 		strb	r3, [r4, #69]
+ 15784 008e CEE7     		b	.L1216
+ 15785              	.LVL1216:
+ 15786              	.L1230:
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15787              		.loc 1 3409 5 view .LVU4664
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15788              		.loc 1 3409 8 is_stmt 0 view .LVU4665
+ 15789 0090 012B     		cmp	r3, #1
+ 15790 0092 26D1     		bne	.L1223
+3410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 15791              		.loc 1 3410 9 view .LVU4666
+ 15792 0094 BCF1010F 		cmp	ip, #1
+ 15793 0098 25D1     		bne	.L1224
+3416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15794              		.loc 1 3416 7 is_stmt 1 view .LVU4667
+ 15795 009a 0223     		movs	r3, #2
+ 15796              	.LVL1217:
+3416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ARM GAS  /tmp/cc0wMqvE.s 			page 489
+
+
+ 15797              		.loc 1 3416 7 is_stmt 0 view .LVU4668
+ 15798 009c 84F83F30 		strb	r3, [r4, #63]
+3417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15799              		.loc 1 3417 7 is_stmt 1 view .LVU4669
+ 15800 00a0 84F84530 		strb	r3, [r4, #69]
+ 15801 00a4 C3E7     		b	.L1216
+ 15802              	.LVL1218:
+ 15803              	.L1218:
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 15804              		.loc 1 3444 7 view .LVU4670
+ 15805 00a6 0122     		movs	r2, #1
+ 15806              	.LVL1219:
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 15807              		.loc 1 3444 7 is_stmt 0 view .LVU4671
+ 15808 00a8 0021     		movs	r1, #0
+ 15809              	.LVL1220:
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 15810              		.loc 1 3444 7 view .LVU4672
+ 15811 00aa 2068     		ldr	r0, [r4]
+ 15812              	.LVL1221:
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 15813              		.loc 1 3444 7 view .LVU4673
+ 15814 00ac FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15815              	.LVL1222:
+3445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15816              		.loc 1 3445 7 is_stmt 1 view .LVU4674
+ 15817 00b0 2268     		ldr	r2, [r4]
+ 15818 00b2 D368     		ldr	r3, [r2, #12]
+ 15819 00b4 43F00203 		orr	r3, r3, #2
+ 15820 00b8 D360     		str	r3, [r2, #12]
+3446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15821              		.loc 1 3446 7 view .LVU4675
+ 15822              	.L1221:
+3467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15823              		.loc 1 3467 3 view .LVU4676
+ 15824 00ba 2268     		ldr	r2, [r4]
+ 15825 00bc 1368     		ldr	r3, [r2]
+ 15826 00be 43F00103 		orr	r3, r3, #1
+ 15827 00c2 1360     		str	r3, [r2]
+3470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 15828              		.loc 1 3470 3 view .LVU4677
+3470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 15829              		.loc 1 3470 10 is_stmt 0 view .LVU4678
+ 15830 00c4 0020     		movs	r0, #0
+ 15831 00c6 0BE0     		b	.L1215
+ 15832              	.LVL1223:
+ 15833              	.L1219:
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 15834              		.loc 1 3451 7 is_stmt 1 view .LVU4679
+ 15835 00c8 0122     		movs	r2, #1
+ 15836              	.LVL1224:
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 15837              		.loc 1 3451 7 is_stmt 0 view .LVU4680
+ 15838 00ca 0421     		movs	r1, #4
+ 15839              	.LVL1225:
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 15840              		.loc 1 3451 7 view .LVU4681
+ARM GAS  /tmp/cc0wMqvE.s 			page 490
+
+
+ 15841 00cc 2068     		ldr	r0, [r4]
+ 15842              	.LVL1226:
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 15843              		.loc 1 3451 7 view .LVU4682
+ 15844 00ce FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15845              	.LVL1227:
+3452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       break;
+ 15846              		.loc 1 3452 7 is_stmt 1 view .LVU4683
+ 15847 00d2 2268     		ldr	r2, [r4]
+ 15848 00d4 D368     		ldr	r3, [r2, #12]
+ 15849 00d6 43F00403 		orr	r3, r3, #4
+ 15850 00da D360     		str	r3, [r2, #12]
+3453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15851              		.loc 1 3453 7 view .LVU4684
+ 15852 00dc EDE7     		b	.L1221
+ 15853              	.LVL1228:
+ 15854              	.L1222:
+3399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15855              		.loc 1 3399 14 is_stmt 0 view .LVU4685
+ 15856 00de 0120     		movs	r0, #1
+ 15857              	.LVL1229:
+ 15858              	.L1215:
+3471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15859              		.loc 1 3471 1 view .LVU4686
+ 15860 00e0 38BD     		pop	{r3, r4, r5, pc}
+ 15861              	.LVL1230:
+ 15862              	.L1223:
+3412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15863              		.loc 1 3412 14 view .LVU4687
+ 15864 00e2 0120     		movs	r0, #1
+ 15865              	.LVL1231:
+3412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15866              		.loc 1 3412 14 view .LVU4688
+ 15867 00e4 FCE7     		b	.L1215
+ 15868              	.LVL1232:
+ 15869              	.L1224:
+3412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15870              		.loc 1 3412 14 view .LVU4689
+ 15871 00e6 1846     		mov	r0, r3
+ 15872              	.LVL1233:
+3412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15873              		.loc 1 3412 14 view .LVU4690
+ 15874 00e8 FAE7     		b	.L1215
+ 15875              	.LVL1234:
+ 15876              	.L1225:
+3427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15877              		.loc 1 3427 14 view .LVU4691
+ 15878 00ea 0120     		movs	r0, #1
+ 15879              	.LVL1235:
+3427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15880              		.loc 1 3427 14 view .LVU4692
+ 15881 00ec F8E7     		b	.L1215
+ 15882              	.LVL1236:
+ 15883              	.L1226:
+3427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15884              		.loc 1 3427 14 view .LVU4693
+ 15885 00ee 1846     		mov	r0, r3
+ARM GAS  /tmp/cc0wMqvE.s 			page 491
+
+
+ 15886              	.LVL1237:
+3427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15887              		.loc 1 3427 14 view .LVU4694
+ 15888 00f0 F6E7     		b	.L1215
+ 15889              	.LVL1238:
+ 15890              	.L1227:
+3427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15891              		.loc 1 3427 14 view .LVU4695
+ 15892 00f2 1046     		mov	r0, r2
+ 15893              	.LVL1239:
+3427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 15894              		.loc 1 3427 14 view .LVU4696
+ 15895 00f4 F4E7     		b	.L1215
+ 15896              		.cfi_endproc
+ 15897              	.LFE383:
+ 15899              		.section	.text.HAL_TIM_Encoder_Stop_IT,"ax",%progbits
+ 15900              		.align	1
+ 15901              		.global	HAL_TIM_Encoder_Stop_IT
+ 15902              		.syntax unified
+ 15903              		.thumb
+ 15904              		.thumb_func
+ 15906              	HAL_TIM_Encoder_Stop_IT:
+ 15907              	.LVL1240:
+ 15908              	.LFB384:
+3484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 15909              		.loc 1 3484 1 is_stmt 1 view -0
+ 15910              		.cfi_startproc
+ 15911              		@ args = 0, pretend = 0, frame = 0
+ 15912              		@ frame_needed = 0, uses_anonymous_args = 0
+3484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 15913              		.loc 1 3484 1 is_stmt 0 view .LVU4698
+ 15914 0000 38B5     		push	{r3, r4, r5, lr}
+ 15915              	.LCFI110:
+ 15916              		.cfi_def_cfa_offset 16
+ 15917              		.cfi_offset 3, -16
+ 15918              		.cfi_offset 4, -12
+ 15919              		.cfi_offset 5, -8
+ 15920              		.cfi_offset 14, -4
+ 15921 0002 0446     		mov	r4, r0
+3486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15922              		.loc 1 3486 3 is_stmt 1 view .LVU4699
+3490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15923              		.loc 1 3490 3 view .LVU4700
+3490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15924              		.loc 1 3490 6 is_stmt 0 view .LVU4701
+ 15925 0004 0D46     		mov	r5, r1
+ 15926 0006 0029     		cmp	r1, #0
+ 15927 0008 31D0     		beq	.L1242
+3497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15928              		.loc 1 3497 8 is_stmt 1 view .LVU4702
+3497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15929              		.loc 1 3497 11 is_stmt 0 view .LVU4703
+ 15930 000a 0429     		cmp	r1, #4
+ 15931 000c 3AD0     		beq	.L1243
+3506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15932              		.loc 1 3506 5 is_stmt 1 view .LVU4704
+ 15933 000e 0022     		movs	r2, #0
+ARM GAS  /tmp/cc0wMqvE.s 			page 492
+
+
+ 15934 0010 1146     		mov	r1, r2
+ 15935              	.LVL1241:
+3506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15936              		.loc 1 3506 5 is_stmt 0 view .LVU4705
+ 15937 0012 0068     		ldr	r0, [r0]
+ 15938              	.LVL1242:
+3506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15939              		.loc 1 3506 5 view .LVU4706
+ 15940 0014 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15941              	.LVL1243:
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15942              		.loc 1 3507 5 is_stmt 1 view .LVU4707
+ 15943 0018 0022     		movs	r2, #0
+ 15944 001a 0421     		movs	r1, #4
+ 15945 001c 2068     		ldr	r0, [r4]
+ 15946 001e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15947              	.LVL1244:
+3510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ 15948              		.loc 1 3510 5 view .LVU4708
+ 15949 0022 2268     		ldr	r2, [r4]
+ 15950 0024 D368     		ldr	r3, [r2, #12]
+ 15951 0026 23F00203 		bic	r3, r3, #2
+ 15952 002a D360     		str	r3, [r2, #12]
+3511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15953              		.loc 1 3511 5 view .LVU4709
+ 15954 002c 2268     		ldr	r2, [r4]
+ 15955 002e D368     		ldr	r3, [r2, #12]
+ 15956 0030 23F00403 		bic	r3, r3, #4
+ 15957 0034 D360     		str	r3, [r2, #12]
+ 15958              	.L1233:
+3515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15959              		.loc 1 3515 3 view .LVU4710
+3515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15960              		.loc 1 3515 3 view .LVU4711
+ 15961 0036 2368     		ldr	r3, [r4]
+ 15962 0038 196A     		ldr	r1, [r3, #32]
+ 15963 003a 41F21112 		movw	r2, #4369
+ 15964 003e 1142     		tst	r1, r2
+ 15965 0040 08D1     		bne	.L1235
+3515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15966              		.loc 1 3515 3 discriminator 1 view .LVU4712
+ 15967 0042 196A     		ldr	r1, [r3, #32]
+ 15968 0044 44F24442 		movw	r2, #17476
+ 15969 0048 1142     		tst	r1, r2
+ 15970 004a 03D1     		bne	.L1235
+3515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15971              		.loc 1 3515 3 discriminator 3 view .LVU4713
+ 15972 004c 1A68     		ldr	r2, [r3]
+ 15973 004e 22F00102 		bic	r2, r2, #1
+ 15974 0052 1A60     		str	r2, [r3]
+ 15975              	.L1235:
+3515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15976              		.loc 1 3515 3 discriminator 5 view .LVU4714
+3518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15977              		.loc 1 3518 3 discriminator 5 view .LVU4715
+3518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15978              		.loc 1 3518 6 is_stmt 0 discriminator 5 view .LVU4716
+ARM GAS  /tmp/cc0wMqvE.s 			page 493
+
+
+ 15979 0054 0DB3     		cbz	r5, .L1236
+3518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 15980              		.loc 1 3518 34 discriminator 1 view .LVU4717
+ 15981 0056 042D     		cmp	r5, #4
+ 15982 0058 26D0     		beq	.L1244
+3525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 15983              		.loc 1 3525 5 is_stmt 1 view .LVU4718
+ 15984 005a 0123     		movs	r3, #1
+ 15985 005c 84F83E30 		strb	r3, [r4, #62]
+3526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 15986              		.loc 1 3526 5 view .LVU4719
+ 15987 0060 84F83F30 		strb	r3, [r4, #63]
+3527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 15988              		.loc 1 3527 5 view .LVU4720
+ 15989 0064 84F84430 		strb	r3, [r4, #68]
+3528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 15990              		.loc 1 3528 5 view .LVU4721
+ 15991 0068 84F84530 		strb	r3, [r4, #69]
+ 15992 006c 1AE0     		b	.L1239
+ 15993              	.LVL1245:
+ 15994              	.L1242:
+3492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15995              		.loc 1 3492 5 view .LVU4722
+ 15996 006e 0022     		movs	r2, #0
+ 15997 0070 1146     		mov	r1, r2
+ 15998              	.LVL1246:
+3492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 15999              		.loc 1 3492 5 is_stmt 0 view .LVU4723
+ 16000 0072 0068     		ldr	r0, [r0]
+ 16001              	.LVL1247:
+3492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16002              		.loc 1 3492 5 view .LVU4724
+ 16003 0074 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 16004              	.LVL1248:
+3495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 16005              		.loc 1 3495 5 is_stmt 1 view .LVU4725
+ 16006 0078 2268     		ldr	r2, [r4]
+ 16007 007a D368     		ldr	r3, [r2, #12]
+ 16008 007c 23F00203 		bic	r3, r3, #2
+ 16009 0080 D360     		str	r3, [r2, #12]
+ 16010 0082 D8E7     		b	.L1233
+ 16011              	.LVL1249:
+ 16012              	.L1243:
+3499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16013              		.loc 1 3499 5 view .LVU4726
+ 16014 0084 0022     		movs	r2, #0
+ 16015 0086 0421     		movs	r1, #4
+ 16016              	.LVL1250:
+3499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16017              		.loc 1 3499 5 is_stmt 0 view .LVU4727
+ 16018 0088 0068     		ldr	r0, [r0]
+ 16019              	.LVL1251:
+3499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16020              		.loc 1 3499 5 view .LVU4728
+ 16021 008a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 16022              	.LVL1252:
+3502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ARM GAS  /tmp/cc0wMqvE.s 			page 494
+
+
+ 16023              		.loc 1 3502 5 is_stmt 1 view .LVU4729
+ 16024 008e 2268     		ldr	r2, [r4]
+ 16025 0090 D368     		ldr	r3, [r2, #12]
+ 16026 0092 23F00403 		bic	r3, r3, #4
+ 16027 0096 D360     		str	r3, [r2, #12]
+ 16028 0098 CDE7     		b	.L1233
+ 16029              	.L1236:
+3520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16030              		.loc 1 3520 5 discriminator 1 view .LVU4730
+ 16031 009a 0123     		movs	r3, #1
+ 16032 009c 84F83E30 		strb	r3, [r4, #62]
+3521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 16033              		.loc 1 3521 5 discriminator 1 view .LVU4731
+ 16034 00a0 84F84430 		strb	r3, [r4, #68]
+ 16035              	.L1239:
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 16036              		.loc 1 3532 3 view .LVU4732
+3533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16037              		.loc 1 3533 1 is_stmt 0 view .LVU4733
+ 16038 00a4 0020     		movs	r0, #0
+ 16039 00a6 38BD     		pop	{r3, r4, r5, pc}
+ 16040              	.LVL1253:
+ 16041              	.L1244:
+3520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16042              		.loc 1 3520 5 is_stmt 1 view .LVU4734
+ 16043 00a8 0123     		movs	r3, #1
+ 16044 00aa 84F83F30 		strb	r3, [r4, #63]
+3521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 16045              		.loc 1 3521 5 view .LVU4735
+ 16046 00ae 84F84530 		strb	r3, [r4, #69]
+ 16047 00b2 F7E7     		b	.L1239
+ 16048              		.cfi_endproc
+ 16049              	.LFE384:
+ 16051              		.section	.text.HAL_TIM_Encoder_Start_DMA,"ax",%progbits
+ 16052              		.align	1
+ 16053              		.global	HAL_TIM_Encoder_Start_DMA
+ 16054              		.syntax unified
+ 16055              		.thumb
+ 16056              		.thumb_func
+ 16058              	HAL_TIM_Encoder_Start_DMA:
+ 16059              	.LVL1254:
+ 16060              	.LFB385:
+3550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 16061              		.loc 1 3550 1 view -0
+ 16062              		.cfi_startproc
+ 16063              		@ args = 4, pretend = 0, frame = 0
+ 16064              		@ frame_needed = 0, uses_anonymous_args = 0
+3550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 16065              		.loc 1 3550 1 is_stmt 0 view .LVU4737
+ 16066 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 16067              	.LCFI111:
+ 16068              		.cfi_def_cfa_offset 24
+ 16069              		.cfi_offset 3, -24
+ 16070              		.cfi_offset 4, -20
+ 16071              		.cfi_offset 5, -16
+ 16072              		.cfi_offset 6, -12
+ 16073              		.cfi_offset 7, -8
+ARM GAS  /tmp/cc0wMqvE.s 			page 495
+
+
+ 16074              		.cfi_offset 14, -4
+ 16075 0002 0446     		mov	r4, r0
+ 16076 0004 1E46     		mov	r6, r3
+ 16077 0006 BDF81870 		ldrh	r7, [sp, #24]
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 16078              		.loc 1 3551 3 is_stmt 1 view .LVU4738
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 16079              		.loc 1 3551 31 is_stmt 0 view .LVU4739
+ 16080 000a 90F83E50 		ldrb	r5, [r0, #62]	@ zero_extendqisi2
+ 16081 000e EDB2     		uxtb	r5, r5
+ 16082              	.LVL1255:
+3552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 16083              		.loc 1 3552 3 is_stmt 1 view .LVU4740
+3552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 16084              		.loc 1 3552 31 is_stmt 0 view .LVU4741
+ 16085 0010 90F83F00 		ldrb	r0, [r0, #63]	@ zero_extendqisi2
+ 16086              	.LVL1256:
+3552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 16087              		.loc 1 3552 31 view .LVU4742
+ 16088 0014 5FFA80FC 		uxtb	ip, r0
+ 16089              	.LVL1257:
+3553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 16090              		.loc 1 3553 3 is_stmt 1 view .LVU4743
+3553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 16091              		.loc 1 3553 31 is_stmt 0 view .LVU4744
+ 16092 0018 94F84400 		ldrb	r0, [r4, #68]	@ zero_extendqisi2
+ 16093 001c C0B2     		uxtb	r0, r0
+ 16094              	.LVL1258:
+3554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16095              		.loc 1 3554 3 is_stmt 1 view .LVU4745
+3554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16096              		.loc 1 3554 31 is_stmt 0 view .LVU4746
+ 16097 001e 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 16098              	.LVL1259:
+3557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16099              		.loc 1 3557 3 is_stmt 1 view .LVU4747
+3560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 16100              		.loc 1 3560 3 view .LVU4748
+3560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 16101              		.loc 1 3560 6 is_stmt 0 view .LVU4749
+ 16102 0022 8E46     		mov	lr, r1
+ 16103 0024 81BB     		cbnz	r1, .L1246
+3562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 16104              		.loc 1 3562 5 is_stmt 1 view .LVU4750
+3562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 16105              		.loc 1 3562 8 is_stmt 0 view .LVU4751
+ 16106 0026 022D     		cmp	r5, #2
+ 16107 0028 00F0EC80 		beq	.L1247
+3563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 16108              		.loc 1 3563 9 view .LVU4752
+ 16109 002c 0228     		cmp	r0, #2
+ 16110 002e 00F0E680 		beq	.L1257
+3567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ 16111              		.loc 1 3567 10 is_stmt 1 view .LVU4753
+3567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ 16112              		.loc 1 3567 13 is_stmt 0 view .LVU4754
+ 16113 0032 012D     		cmp	r5, #1
+ARM GAS  /tmp/cc0wMqvE.s 			page 496
+
+
+ 16114 0034 40F0E580 		bne	.L1258
+3568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 16115              		.loc 1 3568 14 view .LVU4755
+ 16116 0038 0128     		cmp	r0, #1
+ 16117 003a 40F0E380 		bne	.L1247
+3570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 16118              		.loc 1 3570 7 is_stmt 1 view .LVU4756
+3570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 16119              		.loc 1 3570 10 is_stmt 0 view .LVU4757
+ 16120 003e FAB1     		cbz	r2, .L1278
+ 16121              	.L1248:
+3576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 16122              		.loc 1 3576 9 is_stmt 1 view .LVU4758
+ 16123 0040 0223     		movs	r3, #2
+ 16124              	.LVL1260:
+3576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 16125              		.loc 1 3576 9 is_stmt 0 view .LVU4759
+ 16126 0042 84F83E30 		strb	r3, [r4, #62]
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16127              		.loc 1 3577 9 is_stmt 1 view .LVU4760
+ 16128 0046 84F84430 		strb	r3, [r4, #68]
+ 16129              	.L1249:
+3642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 16130              		.loc 1 3642 3 view .LVU4761
+ 16131 004a BEF1000F 		cmp	lr, #0
+ 16132 004e 61D0     		beq	.L1254
+ 16133 0050 BEF1040F 		cmp	lr, #4
+ 16134 0054 00F08180 		beq	.L1255
+3702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16135              		.loc 1 3702 7 view .LVU4762
+3702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16136              		.loc 1 3702 17 is_stmt 0 view .LVU4763
+ 16137 0058 636A     		ldr	r3, [r4, #36]
+3702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16138              		.loc 1 3702 52 view .LVU4764
+ 16139 005a 7549     		ldr	r1, .L1285
+ 16140              	.LVL1261:
+3702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16141              		.loc 1 3702 52 view .LVU4765
+ 16142 005c D962     		str	r1, [r3, #44]
+3703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16143              		.loc 1 3703 7 is_stmt 1 view .LVU4766
+3703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16144              		.loc 1 3703 17 is_stmt 0 view .LVU4767
+ 16145 005e 636A     		ldr	r3, [r4, #36]
+3703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16146              		.loc 1 3703 56 view .LVU4768
+ 16147 0060 7449     		ldr	r1, .L1285+4
+ 16148 0062 1963     		str	r1, [r3, #48]
+3706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16149              		.loc 1 3706 7 is_stmt 1 view .LVU4769
+3706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16150              		.loc 1 3706 17 is_stmt 0 view .LVU4770
+ 16151 0064 636A     		ldr	r3, [r4, #36]
+3706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16152              		.loc 1 3706 53 view .LVU4771
+ 16153 0066 7449     		ldr	r1, .L1285+8
+ARM GAS  /tmp/cc0wMqvE.s 			page 497
+
+
+ 16154 0068 5963     		str	r1, [r3, #52]
+3709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16155              		.loc 1 3709 7 is_stmt 1 view .LVU4772
+3709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16156              		.loc 1 3709 71 is_stmt 0 view .LVU4773
+ 16157 006a 2168     		ldr	r1, [r4]
+3709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16158              		.loc 1 3709 11 view .LVU4774
+ 16159 006c 3B46     		mov	r3, r7
+ 16160 006e 3431     		adds	r1, r1, #52
+ 16161 0070 606A     		ldr	r0, [r4, #36]
+ 16162              	.LVL1262:
+3709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16163              		.loc 1 3709 11 view .LVU4775
+ 16164 0072 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 16165              	.LVL1263:
+3709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16166              		.loc 1 3709 10 view .LVU4776
+ 16167 0076 0028     		cmp	r0, #0
+ 16168 0078 00F09380 		beq	.L1279
+3713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16169              		.loc 1 3713 16 view .LVU4777
+ 16170 007c 0125     		movs	r5, #1
+ 16171              	.LVL1264:
+3713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16172              		.loc 1 3713 16 view .LVU4778
+ 16173 007e C1E0     		b	.L1247
+ 16174              	.LVL1265:
+ 16175              	.L1278:
+3570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 16176              		.loc 1 3570 28 discriminator 1 view .LVU4779
+ 16177 0080 002F     		cmp	r7, #0
+ 16178 0082 DDD0     		beq	.L1248
+3572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16179              		.loc 1 3572 16 view .LVU4780
+ 16180 0084 0546     		mov	r5, r0
+ 16181              	.LVL1266:
+3572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16182              		.loc 1 3572 16 view .LVU4781
+ 16183 0086 BDE0     		b	.L1247
+ 16184              	.LVL1267:
+ 16185              	.L1246:
+3572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16186              		.loc 1 3572 16 view .LVU4782
+ 16187 0088 DBB2     		uxtb	r3, r3
+3585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 16188              		.loc 1 3585 8 is_stmt 1 view .LVU4783
+3585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 16189              		.loc 1 3585 11 is_stmt 0 view .LVU4784
+ 16190 008a 0429     		cmp	r1, #4
+ 16191 008c 25D0     		beq	.L1280
+3612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ 16192              		.loc 1 3612 5 is_stmt 1 view .LVU4785
+3612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ 16193              		.loc 1 3612 8 is_stmt 0 view .LVU4786
+ 16194 008e 022D     		cmp	r5, #2
+ 16195 0090 00F0B880 		beq	.L1247
+ARM GAS  /tmp/cc0wMqvE.s 			page 498
+
+
+3613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ 16196              		.loc 1 3613 9 view .LVU4787
+ 16197 0094 BCF1020F 		cmp	ip, #2
+ 16198 0098 00F0BE80 		beq	.L1265
+3614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 16199              		.loc 1 3614 9 view .LVU4788
+ 16200 009c 0228     		cmp	r0, #2
+ 16201 009e 00F0BD80 		beq	.L1266
+3615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 16202              		.loc 1 3615 9 view .LVU4789
+ 16203 00a2 022B     		cmp	r3, #2
+ 16204 00a4 00F0BC80 		beq	.L1267
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ 16205              		.loc 1 3619 10 is_stmt 1 view .LVU4790
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ 16206              		.loc 1 3619 13 is_stmt 0 view .LVU4791
+ 16207 00a8 012D     		cmp	r5, #1
+ 16208 00aa 40F0BB80 		bne	.L1268
+3620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ 16209              		.loc 1 3620 14 view .LVU4792
+ 16210 00ae BCF1010F 		cmp	ip, #1
+ 16211 00b2 40F0A780 		bne	.L1247
+3621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ 16212              		.loc 1 3621 14 view .LVU4793
+ 16213 00b6 0128     		cmp	r0, #1
+ 16214 00b8 40F0B680 		bne	.L1269
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 16215              		.loc 1 3622 14 view .LVU4794
+ 16216 00bc 012B     		cmp	r3, #1
+ 16217 00be 40F0B580 		bne	.L1270
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 16218              		.loc 1 3624 7 is_stmt 1 view .LVU4795
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 16219              		.loc 1 3624 10 is_stmt 0 view .LVU4796
+ 16220 00c2 1AB3     		cbz	r2, .L1252
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 16221              		.loc 1 3624 30 discriminator 2 view .LVU4797
+ 16222 00c4 16B3     		cbz	r6, .L1252
+ 16223              	.L1253:
+3630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 16224              		.loc 1 3630 9 is_stmt 1 view .LVU4798
+ 16225 00c6 0223     		movs	r3, #2
+ 16226              	.LVL1268:
+3630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 16227              		.loc 1 3630 9 is_stmt 0 view .LVU4799
+ 16228 00c8 84F83E30 		strb	r3, [r4, #62]
+3631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 16229              		.loc 1 3631 9 is_stmt 1 view .LVU4800
+ 16230 00cc 84F83F30 		strb	r3, [r4, #63]
+3632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 16231              		.loc 1 3632 9 view .LVU4801
+ 16232 00d0 84F84430 		strb	r3, [r4, #68]
+3633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16233              		.loc 1 3633 9 view .LVU4802
+ 16234 00d4 84F84530 		strb	r3, [r4, #69]
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 16235              		.loc 1 3624 10 is_stmt 0 view .LVU4803
+ARM GAS  /tmp/cc0wMqvE.s 			page 499
+
+
+ 16236 00d8 B7E7     		b	.L1249
+ 16237              	.LVL1269:
+ 16238              	.L1280:
+3587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 16239              		.loc 1 3587 5 is_stmt 1 view .LVU4804
+3587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 16240              		.loc 1 3587 8 is_stmt 0 view .LVU4805
+ 16241 00da BCF1020F 		cmp	ip, #2
+ 16242 00de 00F09380 		beq	.L1260
+3588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 16243              		.loc 1 3588 9 view .LVU4806
+ 16244 00e2 022B     		cmp	r3, #2
+ 16245 00e4 00F09280 		beq	.L1261
+3592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ 16246              		.loc 1 3592 10 is_stmt 1 view .LVU4807
+3592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ 16247              		.loc 1 3592 13 is_stmt 0 view .LVU4808
+ 16248 00e8 BCF1010F 		cmp	ip, #1
+ 16249 00ec 40F09080 		bne	.L1262
+3593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     {
+ 16250              		.loc 1 3593 14 view .LVU4809
+ 16251 00f0 012B     		cmp	r3, #1
+ 16252 00f2 40F08F80 		bne	.L1263
+3595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 16253              		.loc 1 3595 7 is_stmt 1 view .LVU4810
+3595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 16254              		.loc 1 3595 10 is_stmt 0 view .LVU4811
+ 16255 00f6 2EB1     		cbz	r6, .L1281
+ 16256              	.L1251:
+3601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 16257              		.loc 1 3601 9 is_stmt 1 view .LVU4812
+ 16258 00f8 0223     		movs	r3, #2
+ 16259              	.LVL1270:
+3601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 16260              		.loc 1 3601 9 is_stmt 0 view .LVU4813
+ 16261 00fa 84F83F30 		strb	r3, [r4, #63]
+3602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16262              		.loc 1 3602 9 is_stmt 1 view .LVU4814
+ 16263 00fe 84F84530 		strb	r3, [r4, #69]
+ 16264 0102 A2E7     		b	.L1249
+ 16265              	.LVL1271:
+ 16266              	.L1281:
+3595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 16267              		.loc 1 3595 28 is_stmt 0 discriminator 1 view .LVU4815
+ 16268 0104 002F     		cmp	r7, #0
+ 16269 0106 F7D0     		beq	.L1251
+3597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16270              		.loc 1 3597 16 view .LVU4816
+ 16271 0108 1D46     		mov	r5, r3
+ 16272              	.LVL1272:
+3597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16273              		.loc 1 3597 16 view .LVU4817
+ 16274 010a 7BE0     		b	.L1247
+ 16275              	.LVL1273:
+ 16276              	.L1252:
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       {
+ 16277              		.loc 1 3624 52 discriminator 3 view .LVU4818
+ARM GAS  /tmp/cc0wMqvE.s 			page 500
+
+
+ 16278 010c 002F     		cmp	r7, #0
+ 16279 010e DAD0     		beq	.L1253
+3626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16280              		.loc 1 3626 16 view .LVU4819
+ 16281 0110 1D46     		mov	r5, r3
+ 16282              	.LVL1274:
+3626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16283              		.loc 1 3626 16 view .LVU4820
+ 16284 0112 77E0     		b	.L1247
+ 16285              	.LVL1275:
+ 16286              	.L1254:
+3647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16287              		.loc 1 3647 7 is_stmt 1 view .LVU4821
+3647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16288              		.loc 1 3647 17 is_stmt 0 view .LVU4822
+ 16289 0114 636A     		ldr	r3, [r4, #36]
+3647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16290              		.loc 1 3647 52 view .LVU4823
+ 16291 0116 4649     		ldr	r1, .L1285
+ 16292              	.LVL1276:
+3647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16293              		.loc 1 3647 52 view .LVU4824
+ 16294 0118 D962     		str	r1, [r3, #44]
+3648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16295              		.loc 1 3648 7 is_stmt 1 view .LVU4825
+3648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16296              		.loc 1 3648 17 is_stmt 0 view .LVU4826
+ 16297 011a 636A     		ldr	r3, [r4, #36]
+3648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16298              		.loc 1 3648 56 view .LVU4827
+ 16299 011c 4549     		ldr	r1, .L1285+4
+ 16300 011e 1963     		str	r1, [r3, #48]
+3651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16301              		.loc 1 3651 7 is_stmt 1 view .LVU4828
+3651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16302              		.loc 1 3651 17 is_stmt 0 view .LVU4829
+ 16303 0120 636A     		ldr	r3, [r4, #36]
+3651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16304              		.loc 1 3651 53 view .LVU4830
+ 16305 0122 4549     		ldr	r1, .L1285+8
+ 16306 0124 5963     		str	r1, [r3, #52]
+3654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16307              		.loc 1 3654 7 is_stmt 1 view .LVU4831
+3654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16308              		.loc 1 3654 71 is_stmt 0 view .LVU4832
+ 16309 0126 2168     		ldr	r1, [r4]
+3654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16310              		.loc 1 3654 11 view .LVU4833
+ 16311 0128 3B46     		mov	r3, r7
+ 16312 012a 3431     		adds	r1, r1, #52
+ 16313 012c 606A     		ldr	r0, [r4, #36]
+ 16314              	.LVL1277:
+3654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16315              		.loc 1 3654 11 view .LVU4834
+ 16316 012e FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 16317              	.LVL1278:
+3654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ARM GAS  /tmp/cc0wMqvE.s 			page 501
+
+
+ 16318              		.loc 1 3654 10 view .LVU4835
+ 16319 0132 0546     		mov	r5, r0
+ 16320              	.LVL1279:
+3654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16321              		.loc 1 3654 10 view .LVU4836
+ 16322 0134 08B1     		cbz	r0, .L1282
+3658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16323              		.loc 1 3658 16 view .LVU4837
+ 16324 0136 0125     		movs	r5, #1
+ 16325 0138 64E0     		b	.L1247
+ 16326              	.L1282:
+3661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16327              		.loc 1 3661 7 is_stmt 1 view .LVU4838
+ 16328 013a 2268     		ldr	r2, [r4]
+ 16329 013c D368     		ldr	r3, [r2, #12]
+ 16330 013e 43F40073 		orr	r3, r3, #512
+ 16331 0142 D360     		str	r3, [r2, #12]
+3664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16332              		.loc 1 3664 7 view .LVU4839
+ 16333 0144 0122     		movs	r2, #1
+ 16334 0146 0021     		movs	r1, #0
+ 16335 0148 2068     		ldr	r0, [r4]
+ 16336 014a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 16337              	.LVL1280:
+3667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16338              		.loc 1 3667 7 view .LVU4840
+ 16339 014e 2268     		ldr	r2, [r4]
+ 16340 0150 1368     		ldr	r3, [r2]
+ 16341 0152 43F00103 		orr	r3, r3, #1
+ 16342 0156 1360     		str	r3, [r2]
+3669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16343              		.loc 1 3669 7 view .LVU4841
+ 16344 0158 54E0     		b	.L1247
+ 16345              	.LVL1281:
+ 16346              	.L1255:
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16347              		.loc 1 3675 7 view .LVU4842
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16348              		.loc 1 3675 17 is_stmt 0 view .LVU4843
+ 16349 015a A36A     		ldr	r3, [r4, #40]
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16350              		.loc 1 3675 52 view .LVU4844
+ 16351 015c 344A     		ldr	r2, .L1285
+ 16352              	.LVL1282:
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16353              		.loc 1 3675 52 view .LVU4845
+ 16354 015e DA62     		str	r2, [r3, #44]
+3676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16355              		.loc 1 3676 7 is_stmt 1 view .LVU4846
+3676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16356              		.loc 1 3676 17 is_stmt 0 view .LVU4847
+ 16357 0160 A36A     		ldr	r3, [r4, #40]
+3676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16358              		.loc 1 3676 56 view .LVU4848
+ 16359 0162 344A     		ldr	r2, .L1285+4
+ 16360 0164 1A63     		str	r2, [r3, #48]
+3679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+ARM GAS  /tmp/cc0wMqvE.s 			page 502
+
+
+ 16361              		.loc 1 3679 7 is_stmt 1 view .LVU4849
+3679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+ 16362              		.loc 1 3679 17 is_stmt 0 view .LVU4850
+ 16363 0166 A36A     		ldr	r3, [r4, #40]
+3679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the DMA channel */
+ 16364              		.loc 1 3679 53 view .LVU4851
+ 16365 0168 334A     		ldr	r2, .L1285+8
+ 16366 016a 5A63     		str	r2, [r3, #52]
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16367              		.loc 1 3681 7 is_stmt 1 view .LVU4852
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16368              		.loc 1 3681 71 is_stmt 0 view .LVU4853
+ 16369 016c 2168     		ldr	r1, [r4]
+ 16370              	.LVL1283:
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16371              		.loc 1 3681 11 view .LVU4854
+ 16372 016e 3B46     		mov	r3, r7
+ 16373 0170 3246     		mov	r2, r6
+ 16374 0172 3831     		adds	r1, r1, #56
+ 16375 0174 A06A     		ldr	r0, [r4, #40]
+ 16376              	.LVL1284:
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16377              		.loc 1 3681 11 view .LVU4855
+ 16378 0176 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 16379              	.LVL1285:
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16380              		.loc 1 3681 10 view .LVU4856
+ 16381 017a 0546     		mov	r5, r0
+ 16382              	.LVL1286:
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16383              		.loc 1 3681 10 view .LVU4857
+ 16384 017c 08B1     		cbz	r0, .L1283
+3685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16385              		.loc 1 3685 16 view .LVU4858
+ 16386 017e 0125     		movs	r5, #1
+ 16387 0180 40E0     		b	.L1247
+ 16388              	.L1283:
+3688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16389              		.loc 1 3688 7 is_stmt 1 view .LVU4859
+ 16390 0182 2268     		ldr	r2, [r4]
+ 16391 0184 D368     		ldr	r3, [r2, #12]
+ 16392 0186 43F48063 		orr	r3, r3, #1024
+ 16393 018a D360     		str	r3, [r2, #12]
+3691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16394              		.loc 1 3691 7 view .LVU4860
+ 16395 018c 0122     		movs	r2, #1
+ 16396 018e 0421     		movs	r1, #4
+ 16397 0190 2068     		ldr	r0, [r4]
+ 16398 0192 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 16399              	.LVL1287:
+3694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16400              		.loc 1 3694 7 view .LVU4861
+ 16401 0196 2268     		ldr	r2, [r4]
+ 16402 0198 1368     		ldr	r3, [r2]
+ 16403 019a 43F00103 		orr	r3, r3, #1
+ 16404 019e 1360     		str	r3, [r2]
+3696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ARM GAS  /tmp/cc0wMqvE.s 			page 503
+
+
+ 16405              		.loc 1 3696 7 view .LVU4862
+ 16406 01a0 30E0     		b	.L1247
+ 16407              	.LVL1288:
+ 16408              	.L1279:
+3717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16409              		.loc 1 3717 7 view .LVU4863
+3717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16410              		.loc 1 3717 17 is_stmt 0 view .LVU4864
+ 16411 01a2 A36A     		ldr	r3, [r4, #40]
+3717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 16412              		.loc 1 3717 52 view .LVU4865
+ 16413 01a4 224A     		ldr	r2, .L1285
+ 16414 01a6 DA62     		str	r2, [r3, #44]
+3718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16415              		.loc 1 3718 7 is_stmt 1 view .LVU4866
+3718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16416              		.loc 1 3718 17 is_stmt 0 view .LVU4867
+ 16417 01a8 A36A     		ldr	r3, [r4, #40]
+3718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16418              		.loc 1 3718 56 view .LVU4868
+ 16419 01aa 224A     		ldr	r2, .L1285+4
+ 16420 01ac 1A63     		str	r2, [r3, #48]
+3721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16421              		.loc 1 3721 7 is_stmt 1 view .LVU4869
+3721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16422              		.loc 1 3721 17 is_stmt 0 view .LVU4870
+ 16423 01ae A36A     		ldr	r3, [r4, #40]
+3721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16424              		.loc 1 3721 53 view .LVU4871
+ 16425 01b0 214A     		ldr	r2, .L1285+8
+ 16426 01b2 5A63     		str	r2, [r3, #52]
+3724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16427              		.loc 1 3724 7 is_stmt 1 view .LVU4872
+3724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16428              		.loc 1 3724 71 is_stmt 0 view .LVU4873
+ 16429 01b4 2168     		ldr	r1, [r4]
+3724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16430              		.loc 1 3724 11 view .LVU4874
+ 16431 01b6 3B46     		mov	r3, r7
+ 16432 01b8 3246     		mov	r2, r6
+ 16433 01ba 3831     		adds	r1, r1, #56
+ 16434 01bc A06A     		ldr	r0, [r4, #40]
+ 16435 01be FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 16436              	.LVL1289:
+3724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16437              		.loc 1 3724 10 view .LVU4875
+ 16438 01c2 0546     		mov	r5, r0
+ 16439              	.LVL1290:
+3724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****                            Length) != HAL_OK)
+ 16440              		.loc 1 3724 10 view .LVU4876
+ 16441 01c4 08B1     		cbz	r0, .L1284
+3728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       }
+ 16442              		.loc 1 3728 16 view .LVU4877
+ 16443 01c6 0125     		movs	r5, #1
+ 16444 01c8 1CE0     		b	.L1247
+ 16445              	.L1284:
+3732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       /* Enable the TIM Input Capture  DMA request */
+ARM GAS  /tmp/cc0wMqvE.s 			page 504
+
+
+ 16446              		.loc 1 3732 7 is_stmt 1 view .LVU4878
+ 16447 01ca 2268     		ldr	r2, [r4]
+ 16448 01cc D368     		ldr	r3, [r2, #12]
+ 16449 01ce 43F40073 		orr	r3, r3, #512
+ 16450 01d2 D360     		str	r3, [r2, #12]
+3734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16451              		.loc 1 3734 7 view .LVU4879
+ 16452 01d4 2268     		ldr	r2, [r4]
+ 16453 01d6 D368     		ldr	r3, [r2, #12]
+ 16454 01d8 43F48063 		orr	r3, r3, #1024
+ 16455 01dc D360     		str	r3, [r2, #12]
+3737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 16456              		.loc 1 3737 7 view .LVU4880
+ 16457 01de 0122     		movs	r2, #1
+ 16458 01e0 0021     		movs	r1, #0
+ 16459 01e2 2068     		ldr	r0, [r4]
+ 16460 01e4 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 16461              	.LVL1291:
+3738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16462              		.loc 1 3738 7 view .LVU4881
+ 16463 01e8 0122     		movs	r2, #1
+ 16464 01ea 0421     		movs	r1, #4
+ 16465 01ec 2068     		ldr	r0, [r4]
+ 16466 01ee FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 16467              	.LVL1292:
+3741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16468              		.loc 1 3741 7 view .LVU4882
+ 16469 01f2 2268     		ldr	r2, [r4]
+ 16470 01f4 1368     		ldr	r3, [r2]
+ 16471 01f6 43F00103 		orr	r3, r3, #1
+ 16472 01fa 1360     		str	r3, [r2]
+3743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16473              		.loc 1 3743 7 view .LVU4883
+ 16474 01fc 02E0     		b	.L1247
+ 16475              	.LVL1293:
+ 16476              	.L1257:
+3565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16477              		.loc 1 3565 14 is_stmt 0 view .LVU4884
+ 16478 01fe 0546     		mov	r5, r0
+ 16479              	.LVL1294:
+3565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16480              		.loc 1 3565 14 view .LVU4885
+ 16481 0200 00E0     		b	.L1247
+ 16482              	.LVL1295:
+ 16483              	.L1258:
+3582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16484              		.loc 1 3582 14 view .LVU4886
+ 16485 0202 0125     		movs	r5, #1
+ 16486              	.LVL1296:
+ 16487              	.L1247:
+3749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16488              		.loc 1 3749 1 view .LVU4887
+ 16489 0204 2846     		mov	r0, r5
+ 16490 0206 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 16491              	.LVL1297:
+ 16492              	.L1260:
+3590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ARM GAS  /tmp/cc0wMqvE.s 			page 505
+
+
+ 16493              		.loc 1 3590 14 view .LVU4888
+ 16494 0208 6546     		mov	r5, ip
+ 16495              	.LVL1298:
+3590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16496              		.loc 1 3590 14 view .LVU4889
+ 16497 020a FBE7     		b	.L1247
+ 16498              	.LVL1299:
+ 16499              	.L1261:
+3590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16500              		.loc 1 3590 14 view .LVU4890
+ 16501 020c 1D46     		mov	r5, r3
+ 16502              	.LVL1300:
+3590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16503              		.loc 1 3590 14 view .LVU4891
+ 16504 020e F9E7     		b	.L1247
+ 16505              	.LVL1301:
+ 16506              	.L1262:
+3607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16507              		.loc 1 3607 14 view .LVU4892
+ 16508 0210 0125     		movs	r5, #1
+ 16509              	.LVL1302:
+3607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16510              		.loc 1 3607 14 view .LVU4893
+ 16511 0212 F7E7     		b	.L1247
+ 16512              	.LVL1303:
+ 16513              	.L1263:
+3607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16514              		.loc 1 3607 14 view .LVU4894
+ 16515 0214 6546     		mov	r5, ip
+ 16516              	.LVL1304:
+3607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16517              		.loc 1 3607 14 view .LVU4895
+ 16518 0216 F5E7     		b	.L1247
+ 16519              	.LVL1305:
+ 16520              	.L1265:
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16521              		.loc 1 3617 14 view .LVU4896
+ 16522 0218 6546     		mov	r5, ip
+ 16523              	.LVL1306:
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16524              		.loc 1 3617 14 view .LVU4897
+ 16525 021a F3E7     		b	.L1247
+ 16526              	.LVL1307:
+ 16527              	.L1266:
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16528              		.loc 1 3617 14 view .LVU4898
+ 16529 021c 0546     		mov	r5, r0
+ 16530              	.LVL1308:
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16531              		.loc 1 3617 14 view .LVU4899
+ 16532 021e F1E7     		b	.L1247
+ 16533              	.LVL1309:
+ 16534              	.L1267:
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16535              		.loc 1 3617 14 view .LVU4900
+ 16536 0220 1D46     		mov	r5, r3
+ 16537              	.LVL1310:
+ARM GAS  /tmp/cc0wMqvE.s 			page 506
+
+
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16538              		.loc 1 3617 14 view .LVU4901
+ 16539 0222 EFE7     		b	.L1247
+ 16540              	.LVL1311:
+ 16541              	.L1268:
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16542              		.loc 1 3638 14 view .LVU4902
+ 16543 0224 0125     		movs	r5, #1
+ 16544              	.LVL1312:
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16545              		.loc 1 3638 14 view .LVU4903
+ 16546 0226 EDE7     		b	.L1247
+ 16547              	.LVL1313:
+ 16548              	.L1269:
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16549              		.loc 1 3638 14 view .LVU4904
+ 16550 0228 6546     		mov	r5, ip
+ 16551              	.LVL1314:
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16552              		.loc 1 3638 14 view .LVU4905
+ 16553 022a EBE7     		b	.L1247
+ 16554              	.LVL1315:
+ 16555              	.L1270:
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16556              		.loc 1 3638 14 view .LVU4906
+ 16557 022c 0546     		mov	r5, r0
+ 16558              	.LVL1316:
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     }
+ 16559              		.loc 1 3638 14 view .LVU4907
+ 16560 022e E9E7     		b	.L1247
+ 16561              	.L1286:
+ 16562              		.align	2
+ 16563              	.L1285:
+ 16564 0230 00000000 		.word	TIM_DMACaptureCplt
+ 16565 0234 00000000 		.word	TIM_DMACaptureHalfCplt
+ 16566 0238 00000000 		.word	TIM_DMAError
+ 16567              		.cfi_endproc
+ 16568              	.LFE385:
+ 16570              		.section	.text.HAL_TIM_Encoder_Stop_DMA,"ax",%progbits
+ 16571              		.align	1
+ 16572              		.global	HAL_TIM_Encoder_Stop_DMA
+ 16573              		.syntax unified
+ 16574              		.thumb
+ 16575              		.thumb_func
+ 16577              	HAL_TIM_Encoder_Stop_DMA:
+ 16578              	.LVL1317:
+ 16579              	.LFB386:
+3762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 16580              		.loc 1 3762 1 is_stmt 1 view -0
+ 16581              		.cfi_startproc
+ 16582              		@ args = 0, pretend = 0, frame = 0
+ 16583              		@ frame_needed = 0, uses_anonymous_args = 0
+3762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   /* Check the parameters */
+ 16584              		.loc 1 3762 1 is_stmt 0 view .LVU4909
+ 16585 0000 38B5     		push	{r3, r4, r5, lr}
+ 16586              	.LCFI112:
+ 16587              		.cfi_def_cfa_offset 16
+ARM GAS  /tmp/cc0wMqvE.s 			page 507
+
+
+ 16588              		.cfi_offset 3, -16
+ 16589              		.cfi_offset 4, -12
+ 16590              		.cfi_offset 5, -8
+ 16591              		.cfi_offset 14, -4
+ 16592 0002 0446     		mov	r4, r0
+3764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16593              		.loc 1 3764 3 is_stmt 1 view .LVU4910
+3768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 16594              		.loc 1 3768 3 view .LVU4911
+3768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 16595              		.loc 1 3768 6 is_stmt 0 view .LVU4912
+ 16596 0004 0D46     		mov	r5, r1
+ 16597 0006 0029     		cmp	r1, #0
+ 16598 0008 37D0     		beq	.L1298
+3776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 16599              		.loc 1 3776 8 is_stmt 1 view .LVU4913
+3776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 16600              		.loc 1 3776 11 is_stmt 0 view .LVU4914
+ 16601 000a 0429     		cmp	r1, #4
+ 16602 000c 43D0     		beq	.L1299
+3786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 16603              		.loc 1 3786 5 is_stmt 1 view .LVU4915
+ 16604 000e 0022     		movs	r2, #0
+ 16605 0010 1146     		mov	r1, r2
+ 16606              	.LVL1318:
+3786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 16607              		.loc 1 3786 5 is_stmt 0 view .LVU4916
+ 16608 0012 0068     		ldr	r0, [r0]
+ 16609              	.LVL1319:
+3786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 16610              		.loc 1 3786 5 view .LVU4917
+ 16611 0014 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 16612              	.LVL1320:
+3787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16613              		.loc 1 3787 5 is_stmt 1 view .LVU4918
+ 16614 0018 0022     		movs	r2, #0
+ 16615 001a 0421     		movs	r1, #4
+ 16616 001c 2068     		ldr	r0, [r4]
+ 16617 001e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 16618              	.LVL1321:
+3790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ 16619              		.loc 1 3790 5 view .LVU4919
+ 16620 0022 2268     		ldr	r2, [r4]
+ 16621 0024 D368     		ldr	r3, [r2, #12]
+ 16622 0026 23F40073 		bic	r3, r3, #512
+ 16623 002a D360     		str	r3, [r2, #12]
+3791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 16624              		.loc 1 3791 5 view .LVU4920
+ 16625 002c 2268     		ldr	r2, [r4]
+ 16626 002e D368     		ldr	r3, [r2, #12]
+ 16627 0030 23F48063 		bic	r3, r3, #1024
+ 16628 0034 D360     		str	r3, [r2, #12]
+3792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 16629              		.loc 1 3792 5 view .LVU4921
+3792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 16630              		.loc 1 3792 11 is_stmt 0 view .LVU4922
+ 16631 0036 606A     		ldr	r0, [r4, #36]
+ARM GAS  /tmp/cc0wMqvE.s 			page 508
+
+
+ 16632 0038 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 16633              	.LVL1322:
+3793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 16634              		.loc 1 3793 5 is_stmt 1 view .LVU4923
+3793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 16635              		.loc 1 3793 11 is_stmt 0 view .LVU4924
+ 16636 003c A06A     		ldr	r0, [r4, #40]
+ 16637 003e FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 16638              	.LVL1323:
+ 16639              	.L1289:
+3797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16640              		.loc 1 3797 3 is_stmt 1 view .LVU4925
+3797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16641              		.loc 1 3797 3 view .LVU4926
+ 16642 0042 2368     		ldr	r3, [r4]
+ 16643 0044 196A     		ldr	r1, [r3, #32]
+ 16644 0046 41F21112 		movw	r2, #4369
+ 16645 004a 1142     		tst	r1, r2
+ 16646 004c 08D1     		bne	.L1291
+3797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16647              		.loc 1 3797 3 discriminator 1 view .LVU4927
+ 16648 004e 196A     		ldr	r1, [r3, #32]
+ 16649 0050 44F24442 		movw	r2, #17476
+ 16650 0054 1142     		tst	r1, r2
+ 16651 0056 03D1     		bne	.L1291
+3797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16652              		.loc 1 3797 3 discriminator 3 view .LVU4928
+ 16653 0058 1A68     		ldr	r2, [r3]
+ 16654 005a 22F00102 		bic	r2, r2, #1
+ 16655 005e 1A60     		str	r2, [r3]
+ 16656              	.L1291:
+3797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16657              		.loc 1 3797 3 discriminator 5 view .LVU4929
+3800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 16658              		.loc 1 3800 3 discriminator 5 view .LVU4930
+3800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 16659              		.loc 1 3800 6 is_stmt 0 discriminator 5 view .LVU4931
+ 16660 0060 3DB3     		cbz	r5, .L1292
+3800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   {
+ 16661              		.loc 1 3800 34 discriminator 1 view .LVU4932
+ 16662 0062 042D     		cmp	r5, #4
+ 16663 0064 2CD0     		beq	.L1300
+3807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 16664              		.loc 1 3807 5 is_stmt 1 view .LVU4933
+ 16665 0066 0123     		movs	r3, #1
+ 16666 0068 84F83E30 		strb	r3, [r4, #62]
+3808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 16667              		.loc 1 3808 5 view .LVU4934
+ 16668 006c 84F83F30 		strb	r3, [r4, #63]
+3809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 16669              		.loc 1 3809 5 view .LVU4935
+ 16670 0070 84F84430 		strb	r3, [r4, #68]
+3810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 16671              		.loc 1 3810 5 view .LVU4936
+ 16672 0074 84F84530 		strb	r3, [r4, #69]
+ 16673 0078 20E0     		b	.L1295
+ 16674              	.LVL1324:
+ARM GAS  /tmp/cc0wMqvE.s 			page 509
+
+
+ 16675              	.L1298:
+3770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16676              		.loc 1 3770 5 view .LVU4937
+ 16677 007a 0022     		movs	r2, #0
+ 16678 007c 1146     		mov	r1, r2
+ 16679              	.LVL1325:
+3770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16680              		.loc 1 3770 5 is_stmt 0 view .LVU4938
+ 16681 007e 0068     		ldr	r0, [r0]
+ 16682              	.LVL1326:
+3770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16683              		.loc 1 3770 5 view .LVU4939
+ 16684 0080 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 16685              	.LVL1327:
+3773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 16686              		.loc 1 3773 5 is_stmt 1 view .LVU4940
+ 16687 0084 2268     		ldr	r2, [r4]
+ 16688 0086 D368     		ldr	r3, [r2, #12]
+ 16689 0088 23F40073 		bic	r3, r3, #512
+ 16690 008c D360     		str	r3, [r2, #12]
+3774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 16691              		.loc 1 3774 5 view .LVU4941
+3774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 16692              		.loc 1 3774 11 is_stmt 0 view .LVU4942
+ 16693 008e 606A     		ldr	r0, [r4, #36]
+ 16694 0090 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 16695              	.LVL1328:
+ 16696 0094 D5E7     		b	.L1289
+ 16697              	.LVL1329:
+ 16698              	.L1299:
+3778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16699              		.loc 1 3778 5 is_stmt 1 view .LVU4943
+ 16700 0096 0022     		movs	r2, #0
+ 16701 0098 0421     		movs	r1, #4
+ 16702              	.LVL1330:
+3778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16703              		.loc 1 3778 5 is_stmt 0 view .LVU4944
+ 16704 009a 0068     		ldr	r0, [r0]
+ 16705              	.LVL1331:
+3778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16706              		.loc 1 3778 5 view .LVU4945
+ 16707 009c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 16708              	.LVL1332:
+3781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 16709              		.loc 1 3781 5 is_stmt 1 view .LVU4946
+ 16710 00a0 2268     		ldr	r2, [r4]
+ 16711 00a2 D368     		ldr	r3, [r2, #12]
+ 16712 00a4 23F48063 		bic	r3, r3, #1024
+ 16713 00a8 D360     		str	r3, [r2, #12]
+3782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 16714              		.loc 1 3782 5 view .LVU4947
+3782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 16715              		.loc 1 3782 11 is_stmt 0 view .LVU4948
+ 16716 00aa A06A     		ldr	r0, [r4, #40]
+ 16717 00ac FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 16718              	.LVL1333:
+ 16719 00b0 C7E7     		b	.L1289
+ARM GAS  /tmp/cc0wMqvE.s 			page 510
+
+
+ 16720              	.L1292:
+3802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16721              		.loc 1 3802 5 is_stmt 1 discriminator 1 view .LVU4949
+ 16722 00b2 0123     		movs	r3, #1
+ 16723 00b4 84F83E30 		strb	r3, [r4, #62]
+3803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 16724              		.loc 1 3803 5 discriminator 1 view .LVU4950
+ 16725 00b8 84F84430 		strb	r3, [r4, #68]
+ 16726              	.L1295:
+3814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** }
+ 16727              		.loc 1 3814 3 view .LVU4951
+3815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c **** 
+ 16728              		.loc 1 3815 1 is_stmt 0 view .LVU4952
+ 16729 00bc 0020     		movs	r0, #0
+ 16730 00be 38BD     		pop	{r3, r4, r5, pc}
+ 16731              	.LVL1334:
+ 16732              	.L1300:
+3802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16733              		.loc 1 3802 5 is_stmt 1 view .LVU4953
+ 16734 00c0 0123     		movs	r3, #1
+ 16735 00c2 84F83F30 		strb	r3, [r4, #63]
+3803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ****   }
+ 16736              		.loc 1 3803 5 view .LVU4954
+ 16737 00c6 84F84530 		strb	r3, [r4, #69]
+ 16738 00ca F7E7     		b	.L1295
+ 16739              		.cfi_endproc
+ 16740              	.LFE386:
+ 16742              		.text
+ 16743              	.Letext0:
+ 16744              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 16745              		.file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 16746              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 16747              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 16748              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 16749              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"
+ 16750              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"
+ARM GAS  /tmp/cc0wMqvE.s 			page 511
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_tim.c
+     /tmp/cc0wMqvE.s:21     .text.TIM_OC1_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:26     .text.TIM_OC1_SetConfig:00000000 TIM_OC1_SetConfig
+     /tmp/cc0wMqvE.s:192    .text.TIM_OC1_SetConfig:00000098 $d
+     /tmp/cc0wMqvE.s:197    .text.TIM_OC3_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:202    .text.TIM_OC3_SetConfig:00000000 TIM_OC3_SetConfig
+     /tmp/cc0wMqvE.s:356    .text.TIM_OC3_SetConfig:00000088 $d
+     /tmp/cc0wMqvE.s:361    .text.TIM_OC4_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:366    .text.TIM_OC4_SetConfig:00000000 TIM_OC4_SetConfig
+     /tmp/cc0wMqvE.s:522    .text.TIM_OC4_SetConfig:00000088 $d
+     /tmp/cc0wMqvE.s:527    .text.TIM_OC5_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:532    .text.TIM_OC5_SetConfig:00000000 TIM_OC5_SetConfig
+     /tmp/cc0wMqvE.s:649    .text.TIM_OC5_SetConfig:00000064 $d
+     /tmp/cc0wMqvE.s:654    .text.TIM_OC6_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:659    .text.TIM_OC6_SetConfig:00000000 TIM_OC6_SetConfig
+     /tmp/cc0wMqvE.s:778    .text.TIM_OC6_SetConfig:00000068 $d
+     /tmp/cc0wMqvE.s:783    .text.TIM_TI1_ConfigInputStage:00000000 $t
+     /tmp/cc0wMqvE.s:788    .text.TIM_TI1_ConfigInputStage:00000000 TIM_TI1_ConfigInputStage
+     /tmp/cc0wMqvE.s:849    .text.TIM_TI2_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:854    .text.TIM_TI2_SetConfig:00000000 TIM_TI2_SetConfig
+     /tmp/cc0wMqvE.s:935    .text.TIM_TI2_ConfigInputStage:00000000 $t
+     /tmp/cc0wMqvE.s:940    .text.TIM_TI2_ConfigInputStage:00000000 TIM_TI2_ConfigInputStage
+     /tmp/cc0wMqvE.s:1001   .text.TIM_TI3_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:1006   .text.TIM_TI3_SetConfig:00000000 TIM_TI3_SetConfig
+     /tmp/cc0wMqvE.s:1087   .text.TIM_TI4_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:1092   .text.TIM_TI4_SetConfig:00000000 TIM_TI4_SetConfig
+     /tmp/cc0wMqvE.s:1173   .text.TIM_ITRx_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:1178   .text.TIM_ITRx_SetConfig:00000000 TIM_ITRx_SetConfig
+     /tmp/cc0wMqvE.s:1214   .text.HAL_TIM_Base_MspInit:00000000 $t
+     /tmp/cc0wMqvE.s:1220   .text.HAL_TIM_Base_MspInit:00000000 HAL_TIM_Base_MspInit
+     /tmp/cc0wMqvE.s:1235   .text.HAL_TIM_Base_MspDeInit:00000000 $t
+     /tmp/cc0wMqvE.s:1241   .text.HAL_TIM_Base_MspDeInit:00000000 HAL_TIM_Base_MspDeInit
+     /tmp/cc0wMqvE.s:1256   .text.HAL_TIM_Base_DeInit:00000000 $t
+     /tmp/cc0wMqvE.s:1262   .text.HAL_TIM_Base_DeInit:00000000 HAL_TIM_Base_DeInit
+     /tmp/cc0wMqvE.s:1348   .text.HAL_TIM_Base_Start:00000000 $t
+     /tmp/cc0wMqvE.s:1354   .text.HAL_TIM_Base_Start:00000000 HAL_TIM_Base_Start
+     /tmp/cc0wMqvE.s:1461   .text.HAL_TIM_Base_Start:00000074 $d
+     /tmp/cc0wMqvE.s:1467   .text.HAL_TIM_Base_Stop:00000000 $t
+     /tmp/cc0wMqvE.s:1473   .text.HAL_TIM_Base_Stop:00000000 HAL_TIM_Base_Stop
+     /tmp/cc0wMqvE.s:1514   .text.HAL_TIM_Base_Start_IT:00000000 $t
+     /tmp/cc0wMqvE.s:1520   .text.HAL_TIM_Base_Start_IT:00000000 HAL_TIM_Base_Start_IT
+     /tmp/cc0wMqvE.s:1632   .text.HAL_TIM_Base_Start_IT:0000007c $d
+     /tmp/cc0wMqvE.s:1638   .text.HAL_TIM_Base_Stop_IT:00000000 $t
+     /tmp/cc0wMqvE.s:1644   .text.HAL_TIM_Base_Stop_IT:00000000 HAL_TIM_Base_Stop_IT
+     /tmp/cc0wMqvE.s:1690   .text.HAL_TIM_Base_Start_DMA:00000000 $t
+     /tmp/cc0wMqvE.s:1696   .text.HAL_TIM_Base_Start_DMA:00000000 HAL_TIM_Base_Start_DMA
+     /tmp/cc0wMqvE.s:1861   .text.HAL_TIM_Base_Start_DMA:000000bc $d
+     /tmp/cc0wMqvE.s:3980   .text.TIM_DMAPeriodElapsedCplt:00000000 TIM_DMAPeriodElapsedCplt
+     /tmp/cc0wMqvE.s:4044   .text.TIM_DMAPeriodElapsedHalfCplt:00000000 TIM_DMAPeriodElapsedHalfCplt
+     /tmp/cc0wMqvE.s:5180   .text.TIM_DMAError:00000000 TIM_DMAError
+     /tmp/cc0wMqvE.s:1870   .text.HAL_TIM_Base_Stop_DMA:00000000 $t
+     /tmp/cc0wMqvE.s:1876   .text.HAL_TIM_Base_Stop_DMA:00000000 HAL_TIM_Base_Stop_DMA
+     /tmp/cc0wMqvE.s:1934   .text.HAL_TIM_OC_MspInit:00000000 $t
+     /tmp/cc0wMqvE.s:1940   .text.HAL_TIM_OC_MspInit:00000000 HAL_TIM_OC_MspInit
+     /tmp/cc0wMqvE.s:1955   .text.HAL_TIM_OC_MspDeInit:00000000 $t
+     /tmp/cc0wMqvE.s:1961   .text.HAL_TIM_OC_MspDeInit:00000000 HAL_TIM_OC_MspDeInit
+ARM GAS  /tmp/cc0wMqvE.s 			page 512
+
+
+     /tmp/cc0wMqvE.s:1976   .text.HAL_TIM_OC_DeInit:00000000 $t
+     /tmp/cc0wMqvE.s:1982   .text.HAL_TIM_OC_DeInit:00000000 HAL_TIM_OC_DeInit
+     /tmp/cc0wMqvE.s:2068   .text.HAL_TIM_PWM_MspInit:00000000 $t
+     /tmp/cc0wMqvE.s:2074   .text.HAL_TIM_PWM_MspInit:00000000 HAL_TIM_PWM_MspInit
+     /tmp/cc0wMqvE.s:2089   .text.HAL_TIM_PWM_MspDeInit:00000000 $t
+     /tmp/cc0wMqvE.s:2095   .text.HAL_TIM_PWM_MspDeInit:00000000 HAL_TIM_PWM_MspDeInit
+     /tmp/cc0wMqvE.s:2110   .text.HAL_TIM_PWM_DeInit:00000000 $t
+     /tmp/cc0wMqvE.s:2116   .text.HAL_TIM_PWM_DeInit:00000000 HAL_TIM_PWM_DeInit
+     /tmp/cc0wMqvE.s:2202   .text.HAL_TIM_IC_MspInit:00000000 $t
+     /tmp/cc0wMqvE.s:2208   .text.HAL_TIM_IC_MspInit:00000000 HAL_TIM_IC_MspInit
+     /tmp/cc0wMqvE.s:2223   .text.HAL_TIM_IC_MspDeInit:00000000 $t
+     /tmp/cc0wMqvE.s:2229   .text.HAL_TIM_IC_MspDeInit:00000000 HAL_TIM_IC_MspDeInit
+     /tmp/cc0wMqvE.s:2244   .text.HAL_TIM_IC_DeInit:00000000 $t
+     /tmp/cc0wMqvE.s:2250   .text.HAL_TIM_IC_DeInit:00000000 HAL_TIM_IC_DeInit
+     /tmp/cc0wMqvE.s:2336   .text.HAL_TIM_OnePulse_MspInit:00000000 $t
+     /tmp/cc0wMqvE.s:2342   .text.HAL_TIM_OnePulse_MspInit:00000000 HAL_TIM_OnePulse_MspInit
+     /tmp/cc0wMqvE.s:2357   .text.HAL_TIM_OnePulse_MspDeInit:00000000 $t
+     /tmp/cc0wMqvE.s:2363   .text.HAL_TIM_OnePulse_MspDeInit:00000000 HAL_TIM_OnePulse_MspDeInit
+     /tmp/cc0wMqvE.s:2378   .text.HAL_TIM_OnePulse_DeInit:00000000 $t
+     /tmp/cc0wMqvE.s:2384   .text.HAL_TIM_OnePulse_DeInit:00000000 HAL_TIM_OnePulse_DeInit
+     /tmp/cc0wMqvE.s:2454   .text.HAL_TIM_Encoder_MspInit:00000000 $t
+     /tmp/cc0wMqvE.s:2460   .text.HAL_TIM_Encoder_MspInit:00000000 HAL_TIM_Encoder_MspInit
+     /tmp/cc0wMqvE.s:2475   .text.HAL_TIM_Encoder_MspDeInit:00000000 $t
+     /tmp/cc0wMqvE.s:2481   .text.HAL_TIM_Encoder_MspDeInit:00000000 HAL_TIM_Encoder_MspDeInit
+     /tmp/cc0wMqvE.s:2496   .text.HAL_TIM_Encoder_DeInit:00000000 $t
+     /tmp/cc0wMqvE.s:2502   .text.HAL_TIM_Encoder_DeInit:00000000 HAL_TIM_Encoder_DeInit
+     /tmp/cc0wMqvE.s:2572   .text.HAL_TIM_DMABurst_MultiWriteStart:00000000 $t
+     /tmp/cc0wMqvE.s:2578   .text.HAL_TIM_DMABurst_MultiWriteStart:00000000 HAL_TIM_DMABurst_MultiWriteStart
+     /tmp/cc0wMqvE.s:2948   .text.HAL_TIM_DMABurst_MultiWriteStart:00000194 $d
+     /tmp/cc0wMqvE.s:4382   .text.TIM_DMADelayPulseCplt:00000000 TIM_DMADelayPulseCplt
+     /tmp/cc0wMqvE.s:4529   .text.TIM_DMADelayPulseHalfCplt:00000000 TIM_DMADelayPulseHalfCplt
+     /tmp/cc0wMqvE.s:5062   .text.TIM_DMATriggerCplt:00000000 TIM_DMATriggerCplt
+     /tmp/cc0wMqvE.s:5126   .text.TIM_DMATriggerHalfCplt:00000000 TIM_DMATriggerHalfCplt
+     /tmp/cc0wMqvE.s:2961   .text.HAL_TIM_DMABurst_WriteStart:00000000 $t
+     /tmp/cc0wMqvE.s:2967   .text.HAL_TIM_DMABurst_WriteStart:00000000 HAL_TIM_DMABurst_WriteStart
+     /tmp/cc0wMqvE.s:3007   .text.HAL_TIM_DMABurst_WriteStop:00000000 $t
+     /tmp/cc0wMqvE.s:3013   .text.HAL_TIM_DMABurst_WriteStop:00000000 HAL_TIM_DMABurst_WriteStop
+     /tmp/cc0wMqvE.s:3167   .text.HAL_TIM_DMABurst_MultiReadStart:00000000 $t
+     /tmp/cc0wMqvE.s:3173   .text.HAL_TIM_DMABurst_MultiReadStart:00000000 HAL_TIM_DMABurst_MultiReadStart
+     /tmp/cc0wMqvE.s:3543   .text.HAL_TIM_DMABurst_MultiReadStart:00000194 $d
+     /tmp/cc0wMqvE.s:4119   .text.TIM_DMACaptureCplt:00000000 TIM_DMACaptureCplt
+     /tmp/cc0wMqvE.s:4274   .text.TIM_DMACaptureHalfCplt:00000000 TIM_DMACaptureHalfCplt
+     /tmp/cc0wMqvE.s:3556   .text.HAL_TIM_DMABurst_ReadStart:00000000 $t
+     /tmp/cc0wMqvE.s:3562   .text.HAL_TIM_DMABurst_ReadStart:00000000 HAL_TIM_DMABurst_ReadStart
+     /tmp/cc0wMqvE.s:3602   .text.HAL_TIM_DMABurst_ReadStop:00000000 $t
+     /tmp/cc0wMqvE.s:3608   .text.HAL_TIM_DMABurst_ReadStop:00000000 HAL_TIM_DMABurst_ReadStop
+     /tmp/cc0wMqvE.s:3762   .text.HAL_TIM_GenerateEvent:00000000 $t
+     /tmp/cc0wMqvE.s:3768   .text.HAL_TIM_GenerateEvent:00000000 HAL_TIM_GenerateEvent
+     /tmp/cc0wMqvE.s:3821   .text.HAL_TIM_ConfigTI1Input:00000000 $t
+     /tmp/cc0wMqvE.s:3827   .text.HAL_TIM_ConfigTI1Input:00000000 HAL_TIM_ConfigTI1Input
+     /tmp/cc0wMqvE.s:3865   .text.HAL_TIM_ReadCapturedValue:00000000 $t
+     /tmp/cc0wMqvE.s:3871   .text.HAL_TIM_ReadCapturedValue:00000000 HAL_TIM_ReadCapturedValue
+     /tmp/cc0wMqvE.s:3885   .text.HAL_TIM_ReadCapturedValue:00000008 $d
+     /tmp/cc0wMqvE.s:3954   .text.HAL_TIM_PeriodElapsedCallback:00000000 $t
+     /tmp/cc0wMqvE.s:3960   .text.HAL_TIM_PeriodElapsedCallback:00000000 HAL_TIM_PeriodElapsedCallback
+     /tmp/cc0wMqvE.s:3975   .text.TIM_DMAPeriodElapsedCplt:00000000 $t
+     /tmp/cc0wMqvE.s:4018   .text.HAL_TIM_PeriodElapsedHalfCpltCallback:00000000 $t
+ARM GAS  /tmp/cc0wMqvE.s 			page 513
+
+
+     /tmp/cc0wMqvE.s:4024   .text.HAL_TIM_PeriodElapsedHalfCpltCallback:00000000 HAL_TIM_PeriodElapsedHalfCpltCallback
+     /tmp/cc0wMqvE.s:4039   .text.TIM_DMAPeriodElapsedHalfCplt:00000000 $t
+     /tmp/cc0wMqvE.s:4071   .text.HAL_TIM_OC_DelayElapsedCallback:00000000 $t
+     /tmp/cc0wMqvE.s:4077   .text.HAL_TIM_OC_DelayElapsedCallback:00000000 HAL_TIM_OC_DelayElapsedCallback
+     /tmp/cc0wMqvE.s:4092   .text.HAL_TIM_IC_CaptureCallback:00000000 $t
+     /tmp/cc0wMqvE.s:4098   .text.HAL_TIM_IC_CaptureCallback:00000000 HAL_TIM_IC_CaptureCallback
+     /tmp/cc0wMqvE.s:4113   .text.TIM_DMACaptureCplt:00000000 $t
+     /tmp/cc0wMqvE.s:4247   .text.HAL_TIM_IC_CaptureHalfCpltCallback:00000000 $t
+     /tmp/cc0wMqvE.s:4253   .text.HAL_TIM_IC_CaptureHalfCpltCallback:00000000 HAL_TIM_IC_CaptureHalfCpltCallback
+     /tmp/cc0wMqvE.s:4268   .text.TIM_DMACaptureHalfCplt:00000000 $t
+     /tmp/cc0wMqvE.s:4356   .text.HAL_TIM_PWM_PulseFinishedCallback:00000000 $t
+     /tmp/cc0wMqvE.s:4362   .text.HAL_TIM_PWM_PulseFinishedCallback:00000000 HAL_TIM_PWM_PulseFinishedCallback
+     /tmp/cc0wMqvE.s:4377   .text.TIM_DMADelayPulseCplt:00000000 $t
+     /tmp/cc0wMqvE.s:4502   .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback:00000000 $t
+     /tmp/cc0wMqvE.s:4508   .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback:00000000 HAL_TIM_PWM_PulseFinishedHalfCpltCallback
+     /tmp/cc0wMqvE.s:4523   .text.TIM_DMADelayPulseHalfCplt:00000000 $t
+     /tmp/cc0wMqvE.s:4611   .text.HAL_TIM_TriggerCallback:00000000 $t
+     /tmp/cc0wMqvE.s:4617   .text.HAL_TIM_TriggerCallback:00000000 HAL_TIM_TriggerCallback
+     /tmp/cc0wMqvE.s:4632   .text.HAL_TIM_IRQHandler:00000000 $t
+     /tmp/cc0wMqvE.s:4638   .text.HAL_TIM_IRQHandler:00000000 HAL_TIM_IRQHandler
+     /tmp/cc0wMqvE.s:5057   .text.TIM_DMATriggerCplt:00000000 $t
+     /tmp/cc0wMqvE.s:5100   .text.HAL_TIM_TriggerHalfCpltCallback:00000000 $t
+     /tmp/cc0wMqvE.s:5106   .text.HAL_TIM_TriggerHalfCpltCallback:00000000 HAL_TIM_TriggerHalfCpltCallback
+     /tmp/cc0wMqvE.s:5121   .text.TIM_DMATriggerHalfCplt:00000000 $t
+     /tmp/cc0wMqvE.s:5153   .text.HAL_TIM_ErrorCallback:00000000 $t
+     /tmp/cc0wMqvE.s:5159   .text.HAL_TIM_ErrorCallback:00000000 HAL_TIM_ErrorCallback
+     /tmp/cc0wMqvE.s:5174   .text.TIM_DMAError:00000000 $t
+     /tmp/cc0wMqvE.s:5278   .text.HAL_TIM_Base_GetState:00000000 $t
+     /tmp/cc0wMqvE.s:5284   .text.HAL_TIM_Base_GetState:00000000 HAL_TIM_Base_GetState
+     /tmp/cc0wMqvE.s:5302   .text.HAL_TIM_OC_GetState:00000000 $t
+     /tmp/cc0wMqvE.s:5308   .text.HAL_TIM_OC_GetState:00000000 HAL_TIM_OC_GetState
+     /tmp/cc0wMqvE.s:5326   .text.HAL_TIM_PWM_GetState:00000000 $t
+     /tmp/cc0wMqvE.s:5332   .text.HAL_TIM_PWM_GetState:00000000 HAL_TIM_PWM_GetState
+     /tmp/cc0wMqvE.s:5350   .text.HAL_TIM_IC_GetState:00000000 $t
+     /tmp/cc0wMqvE.s:5356   .text.HAL_TIM_IC_GetState:00000000 HAL_TIM_IC_GetState
+     /tmp/cc0wMqvE.s:5374   .text.HAL_TIM_OnePulse_GetState:00000000 $t
+     /tmp/cc0wMqvE.s:5380   .text.HAL_TIM_OnePulse_GetState:00000000 HAL_TIM_OnePulse_GetState
+     /tmp/cc0wMqvE.s:5398   .text.HAL_TIM_Encoder_GetState:00000000 $t
+     /tmp/cc0wMqvE.s:5404   .text.HAL_TIM_Encoder_GetState:00000000 HAL_TIM_Encoder_GetState
+     /tmp/cc0wMqvE.s:5422   .text.HAL_TIM_GetActiveChannel:00000000 $t
+     /tmp/cc0wMqvE.s:5428   .text.HAL_TIM_GetActiveChannel:00000000 HAL_TIM_GetActiveChannel
+     /tmp/cc0wMqvE.s:5446   .text.HAL_TIM_GetChannelState:00000000 $t
+     /tmp/cc0wMqvE.s:5452   .text.HAL_TIM_GetChannelState:00000000 HAL_TIM_GetChannelState
+     /tmp/cc0wMqvE.s:5467   .text.HAL_TIM_GetChannelState:00000008 $d
+     /tmp/cc0wMqvE.s:5539   .text.HAL_TIM_DMABurstState:00000000 $t
+     /tmp/cc0wMqvE.s:5545   .text.HAL_TIM_DMABurstState:00000000 HAL_TIM_DMABurstState
+     /tmp/cc0wMqvE.s:5564   .text.TIM_Base_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:5570   .text.TIM_Base_SetConfig:00000000 TIM_Base_SetConfig
+     /tmp/cc0wMqvE.s:5718   .text.TIM_Base_SetConfig:000000b4 $d
+     /tmp/cc0wMqvE.s:5723   .text.HAL_TIM_Base_Init:00000000 $t
+     /tmp/cc0wMqvE.s:5729   .text.HAL_TIM_Base_Init:00000000 HAL_TIM_Base_Init
+     /tmp/cc0wMqvE.s:5827   .text.HAL_TIM_OC_Init:00000000 $t
+     /tmp/cc0wMqvE.s:5833   .text.HAL_TIM_OC_Init:00000000 HAL_TIM_OC_Init
+     /tmp/cc0wMqvE.s:5931   .text.HAL_TIM_PWM_Init:00000000 $t
+     /tmp/cc0wMqvE.s:5937   .text.HAL_TIM_PWM_Init:00000000 HAL_TIM_PWM_Init
+     /tmp/cc0wMqvE.s:6035   .text.HAL_TIM_IC_Init:00000000 $t
+     /tmp/cc0wMqvE.s:6041   .text.HAL_TIM_IC_Init:00000000 HAL_TIM_IC_Init
+ARM GAS  /tmp/cc0wMqvE.s 			page 514
+
+
+     /tmp/cc0wMqvE.s:6139   .text.HAL_TIM_OnePulse_Init:00000000 $t
+     /tmp/cc0wMqvE.s:6145   .text.HAL_TIM_OnePulse_Init:00000000 HAL_TIM_OnePulse_Init
+     /tmp/cc0wMqvE.s:6249   .text.HAL_TIM_Encoder_Init:00000000 $t
+     /tmp/cc0wMqvE.s:6255   .text.HAL_TIM_Encoder_Init:00000000 HAL_TIM_Encoder_Init
+     /tmp/cc0wMqvE.s:6465   .text.TIM_OC2_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:6471   .text.TIM_OC2_SetConfig:00000000 TIM_OC2_SetConfig
+     /tmp/cc0wMqvE.s:6627   .text.TIM_OC2_SetConfig:00000088 $d
+     /tmp/cc0wMqvE.s:6632   .text.HAL_TIM_OC_ConfigChannel:00000000 $t
+     /tmp/cc0wMqvE.s:6638   .text.HAL_TIM_OC_ConfigChannel:00000000 HAL_TIM_OC_ConfigChannel
+     /tmp/cc0wMqvE.s:6670   .text.HAL_TIM_OC_ConfigChannel:0000001a $d
+     /tmp/cc0wMqvE.s:6804   .text.HAL_TIM_PWM_ConfigChannel:00000000 $t
+     /tmp/cc0wMqvE.s:6810   .text.HAL_TIM_PWM_ConfigChannel:00000000 HAL_TIM_PWM_ConfigChannel
+     /tmp/cc0wMqvE.s:6847   .text.HAL_TIM_PWM_ConfigChannel:00000020 $d
+     /tmp/cc0wMqvE.s:7135   .text.TIM_TI1_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:7141   .text.TIM_TI1_SetConfig:00000000 TIM_TI1_SetConfig
+     /tmp/cc0wMqvE.s:7257   .text.TIM_TI1_SetConfig:00000064 $d
+     /tmp/cc0wMqvE.s:7263   .text.HAL_TIM_IC_ConfigChannel:00000000 $t
+     /tmp/cc0wMqvE.s:7269   .text.HAL_TIM_IC_ConfigChannel:00000000 HAL_TIM_IC_ConfigChannel
+     /tmp/cc0wMqvE.s:7489   .text.HAL_TIM_OnePulse_ConfigChannel:00000000 $t
+     /tmp/cc0wMqvE.s:7495   .text.HAL_TIM_OnePulse_ConfigChannel:00000000 HAL_TIM_OnePulse_ConfigChannel
+     /tmp/cc0wMqvE.s:7772   .text.TIM_ETR_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:7778   .text.TIM_ETR_SetConfig:00000000 TIM_ETR_SetConfig
+     /tmp/cc0wMqvE.s:7822   .text.HAL_TIM_ConfigOCrefClear:00000000 $t
+     /tmp/cc0wMqvE.s:7828   .text.HAL_TIM_ConfigOCrefClear:00000000 HAL_TIM_ConfigOCrefClear
+     /tmp/cc0wMqvE.s:7956   .text.HAL_TIM_ConfigOCrefClear:000000b4 $d
+     /tmp/cc0wMqvE.s:7978   .text.HAL_TIM_ConfigOCrefClear:000000de $t
+     /tmp/cc0wMqvE.s:8262   .text.HAL_TIM_ConfigOCrefClear:00000260 $d
+     /tmp/cc0wMqvE.s:8267   .text.HAL_TIM_ConfigClockSource:00000000 $t
+     /tmp/cc0wMqvE.s:8273   .text.HAL_TIM_ConfigClockSource:00000000 HAL_TIM_ConfigClockSource
+     /tmp/cc0wMqvE.s:8602   .text.HAL_TIM_ConfigClockSource:0000012c $d
+     /tmp/cc0wMqvE.s:8609   .text.TIM_SlaveTimer_SetConfig:00000000 $t
+     /tmp/cc0wMqvE.s:8614   .text.TIM_SlaveTimer_SetConfig:00000000 TIM_SlaveTimer_SetConfig
+     /tmp/cc0wMqvE.s:8958   .text.TIM_SlaveTimer_SetConfig:0000010c $d
+     /tmp/cc0wMqvE.s:8964   .text.HAL_TIM_SlaveConfigSynchro:00000000 $t
+     /tmp/cc0wMqvE.s:8970   .text.HAL_TIM_SlaveConfigSynchro:00000000 HAL_TIM_SlaveConfigSynchro
+     /tmp/cc0wMqvE.s:9058   .text.HAL_TIM_SlaveConfigSynchro_IT:00000000 $t
+     /tmp/cc0wMqvE.s:9064   .text.HAL_TIM_SlaveConfigSynchro_IT:00000000 HAL_TIM_SlaveConfigSynchro_IT
+     /tmp/cc0wMqvE.s:9152   .text.TIM_CCxChannelCmd:00000000 $t
+     /tmp/cc0wMqvE.s:9158   .text.TIM_CCxChannelCmd:00000000 TIM_CCxChannelCmd
+     /tmp/cc0wMqvE.s:9198   .text.HAL_TIM_OC_Start:00000000 $t
+     /tmp/cc0wMqvE.s:9204   .text.HAL_TIM_OC_Start:00000000 HAL_TIM_OC_Start
+     /tmp/cc0wMqvE.s:9225   .text.HAL_TIM_OC_Start:0000000c $d
+     /tmp/cc0wMqvE.s:9260   .text.HAL_TIM_OC_Start:00000038 $d
+     /tmp/cc0wMqvE.s:9466   .text.HAL_TIM_OC_Start:00000158 $d
+     /tmp/cc0wMqvE.s:9472   .text.HAL_TIM_OC_Stop:00000000 $t
+     /tmp/cc0wMqvE.s:9478   .text.HAL_TIM_OC_Stop:00000000 HAL_TIM_OC_Stop
+     /tmp/cc0wMqvE.s:9582   .text.HAL_TIM_OC_Stop:00000086 $d
+     /tmp/cc0wMqvE.s:9624   .text.HAL_TIM_OC_Stop:000000bc $d
+     /tmp/cc0wMqvE.s:9629   .text.HAL_TIM_OC_Start_IT:00000000 $t
+     /tmp/cc0wMqvE.s:9635   .text.HAL_TIM_OC_Start_IT:00000000 HAL_TIM_OC_Start_IT
+     /tmp/cc0wMqvE.s:9658   .text.HAL_TIM_OC_Start_IT:0000000c $d
+     /tmp/cc0wMqvE.s:9693   .text.HAL_TIM_OC_Start_IT:0000003a $d
+     /tmp/cc0wMqvE.s:9902   .text.HAL_TIM_OC_Start_IT:00000164 $d
+     /tmp/cc0wMqvE.s:9916   .text.HAL_TIM_OC_Start_IT:00000198 $t
+     /tmp/cc0wMqvE.s:9966   .text.HAL_TIM_OC_Start_IT:000001c4 $d
+     /tmp/cc0wMqvE.s:9972   .text.HAL_TIM_OC_Stop_IT:00000000 $t
+     /tmp/cc0wMqvE.s:9978   .text.HAL_TIM_OC_Stop_IT:00000000 HAL_TIM_OC_Stop_IT
+ARM GAS  /tmp/cc0wMqvE.s 			page 515
+
+
+     /tmp/cc0wMqvE.s:10003  .text.HAL_TIM_OC_Stop_IT:00000010 $d
+     /tmp/cc0wMqvE.s:10139  .text.HAL_TIM_OC_Stop_IT:000000ce $d
+     /tmp/cc0wMqvE.s:10197  .text.HAL_TIM_OC_Stop_IT:00000114 $d
+     /tmp/cc0wMqvE.s:10202  .text.HAL_TIM_OC_Start_DMA:00000000 $t
+     /tmp/cc0wMqvE.s:10208  .text.HAL_TIM_OC_Start_DMA:00000000 HAL_TIM_OC_Start_DMA
+     /tmp/cc0wMqvE.s:10236  .text.HAL_TIM_OC_Start_DMA:00000010 $d
+     /tmp/cc0wMqvE.s:10274  .text.HAL_TIM_OC_Start_DMA:0000003e $d
+     /tmp/cc0wMqvE.s:10380  .text.HAL_TIM_OC_Start_DMA:000000c2 $d
+     /tmp/cc0wMqvE.s:10397  .text.HAL_TIM_OC_Start_DMA:000000e4 $t
+     /tmp/cc0wMqvE.s:10719  .text.HAL_TIM_OC_Start_DMA:00000298 $d
+     /tmp/cc0wMqvE.s:10733  .text.HAL_TIM_OC_Start_DMA:000002cc $t
+     /tmp/cc0wMqvE.s:10802  .text.HAL_TIM_OC_Start_DMA:0000030c $d
+     /tmp/cc0wMqvE.s:10811  .text.HAL_TIM_OC_Stop_DMA:00000000 $t
+     /tmp/cc0wMqvE.s:10817  .text.HAL_TIM_OC_Stop_DMA:00000000 HAL_TIM_OC_Stop_DMA
+     /tmp/cc0wMqvE.s:10842  .text.HAL_TIM_OC_Stop_DMA:00000010 $d
+     /tmp/cc0wMqvE.s:11003  .text.HAL_TIM_OC_Stop_DMA:000000e6 $d
+     /tmp/cc0wMqvE.s:11061  .text.HAL_TIM_OC_Stop_DMA:0000012c $d
+     /tmp/cc0wMqvE.s:11066  .text.HAL_TIM_PWM_Start:00000000 $t
+     /tmp/cc0wMqvE.s:11072  .text.HAL_TIM_PWM_Start:00000000 HAL_TIM_PWM_Start
+     /tmp/cc0wMqvE.s:11093  .text.HAL_TIM_PWM_Start:0000000c $d
+     /tmp/cc0wMqvE.s:11128  .text.HAL_TIM_PWM_Start:00000038 $d
+     /tmp/cc0wMqvE.s:11334  .text.HAL_TIM_PWM_Start:00000158 $d
+     /tmp/cc0wMqvE.s:11340  .text.HAL_TIM_PWM_Stop:00000000 $t
+     /tmp/cc0wMqvE.s:11346  .text.HAL_TIM_PWM_Stop:00000000 HAL_TIM_PWM_Stop
+     /tmp/cc0wMqvE.s:11450  .text.HAL_TIM_PWM_Stop:00000086 $d
+     /tmp/cc0wMqvE.s:11492  .text.HAL_TIM_PWM_Stop:000000bc $d
+     /tmp/cc0wMqvE.s:11497  .text.HAL_TIM_PWM_Start_IT:00000000 $t
+     /tmp/cc0wMqvE.s:11503  .text.HAL_TIM_PWM_Start_IT:00000000 HAL_TIM_PWM_Start_IT
+     /tmp/cc0wMqvE.s:11526  .text.HAL_TIM_PWM_Start_IT:0000000c $d
+     /tmp/cc0wMqvE.s:11561  .text.HAL_TIM_PWM_Start_IT:0000003a $d
+     /tmp/cc0wMqvE.s:11770  .text.HAL_TIM_PWM_Start_IT:00000164 $d
+     /tmp/cc0wMqvE.s:11784  .text.HAL_TIM_PWM_Start_IT:00000198 $t
+     /tmp/cc0wMqvE.s:11834  .text.HAL_TIM_PWM_Start_IT:000001c4 $d
+     /tmp/cc0wMqvE.s:11840  .text.HAL_TIM_PWM_Stop_IT:00000000 $t
+     /tmp/cc0wMqvE.s:11846  .text.HAL_TIM_PWM_Stop_IT:00000000 HAL_TIM_PWM_Stop_IT
+     /tmp/cc0wMqvE.s:11871  .text.HAL_TIM_PWM_Stop_IT:00000010 $d
+     /tmp/cc0wMqvE.s:12007  .text.HAL_TIM_PWM_Stop_IT:000000ce $d
+     /tmp/cc0wMqvE.s:12065  .text.HAL_TIM_PWM_Stop_IT:00000114 $d
+     /tmp/cc0wMqvE.s:12070  .text.HAL_TIM_PWM_Start_DMA:00000000 $t
+     /tmp/cc0wMqvE.s:12076  .text.HAL_TIM_PWM_Start_DMA:00000000 HAL_TIM_PWM_Start_DMA
+     /tmp/cc0wMqvE.s:12104  .text.HAL_TIM_PWM_Start_DMA:00000010 $d
+     /tmp/cc0wMqvE.s:12142  .text.HAL_TIM_PWM_Start_DMA:0000003e $d
+     /tmp/cc0wMqvE.s:12248  .text.HAL_TIM_PWM_Start_DMA:000000c2 $d
+     /tmp/cc0wMqvE.s:12265  .text.HAL_TIM_PWM_Start_DMA:000000e4 $t
+     /tmp/cc0wMqvE.s:12587  .text.HAL_TIM_PWM_Start_DMA:00000298 $d
+     /tmp/cc0wMqvE.s:12601  .text.HAL_TIM_PWM_Start_DMA:000002cc $t
+     /tmp/cc0wMqvE.s:12670  .text.HAL_TIM_PWM_Start_DMA:0000030c $d
+     /tmp/cc0wMqvE.s:12679  .text.HAL_TIM_PWM_Stop_DMA:00000000 $t
+     /tmp/cc0wMqvE.s:12685  .text.HAL_TIM_PWM_Stop_DMA:00000000 HAL_TIM_PWM_Stop_DMA
+     /tmp/cc0wMqvE.s:12710  .text.HAL_TIM_PWM_Stop_DMA:00000010 $d
+     /tmp/cc0wMqvE.s:12871  .text.HAL_TIM_PWM_Stop_DMA:000000e6 $d
+     /tmp/cc0wMqvE.s:12929  .text.HAL_TIM_PWM_Stop_DMA:0000012c $d
+     /tmp/cc0wMqvE.s:12934  .text.HAL_TIM_IC_Start:00000000 $t
+     /tmp/cc0wMqvE.s:12940  .text.HAL_TIM_IC_Start:00000000 HAL_TIM_IC_Start
+     /tmp/cc0wMqvE.s:12960  .text.HAL_TIM_IC_Start:0000000c $d
+     /tmp/cc0wMqvE.s:13008  .text.HAL_TIM_IC_Start:00000040 $d
+     /tmp/cc0wMqvE.s:13230  .text.HAL_TIM_IC_Start:00000154 $d
+ARM GAS  /tmp/cc0wMqvE.s 			page 516
+
+
+     /tmp/cc0wMqvE.s:13236  .text.HAL_TIM_IC_Stop:00000000 $t
+     /tmp/cc0wMqvE.s:13242  .text.HAL_TIM_IC_Stop:00000000 HAL_TIM_IC_Stop
+     /tmp/cc0wMqvE.s:13305  .text.HAL_TIM_IC_Stop:00000046 $d
+     /tmp/cc0wMqvE.s:13373  .text.HAL_TIM_IC_Start_IT:00000000 $t
+     /tmp/cc0wMqvE.s:13379  .text.HAL_TIM_IC_Start_IT:00000000 HAL_TIM_IC_Start_IT
+     /tmp/cc0wMqvE.s:13401  .text.HAL_TIM_IC_Start_IT:0000000c $d
+     /tmp/cc0wMqvE.s:13448  .text.HAL_TIM_IC_Start_IT:00000040 $d
+     /tmp/cc0wMqvE.s:13557  .text.HAL_TIM_IC_Start_IT:000000c2 $d
+     /tmp/cc0wMqvE.s:13741  .text.HAL_TIM_IC_Start_IT:00000198 $d
+     /tmp/cc0wMqvE.s:13747  .text.HAL_TIM_IC_Stop_IT:00000000 $t
+     /tmp/cc0wMqvE.s:13753  .text.HAL_TIM_IC_Stop_IT:00000000 HAL_TIM_IC_Stop_IT
+     /tmp/cc0wMqvE.s:13778  .text.HAL_TIM_IC_Stop_IT:0000000e $d
+     /tmp/cc0wMqvE.s:13874  .text.HAL_TIM_IC_Stop_IT:0000008c $d
+     /tmp/cc0wMqvE.s:13955  .text.HAL_TIM_IC_Start_DMA:00000000 $t
+     /tmp/cc0wMqvE.s:13961  .text.HAL_TIM_IC_Start_DMA:00000000 HAL_TIM_IC_Start_DMA
+     /tmp/cc0wMqvE.s:13991  .text.HAL_TIM_IC_Start_DMA:00000014 $d
+     /tmp/cc0wMqvE.s:14050  .text.HAL_TIM_IC_Start_DMA:0000005c $d
+     /tmp/cc0wMqvE.s:14185  .text.HAL_TIM_IC_Start_DMA:000000f6 $d
+     /tmp/cc0wMqvE.s:14509  .text.HAL_TIM_IC_Start_DMA:00000270 $d
+     /tmp/cc0wMqvE.s:14518  .text.HAL_TIM_IC_Stop_DMA:00000000 $t
+     /tmp/cc0wMqvE.s:14524  .text.HAL_TIM_IC_Stop_DMA:00000000 HAL_TIM_IC_Stop_DMA
+     /tmp/cc0wMqvE.s:14557  .text.HAL_TIM_IC_Stop_DMA:00000016 $d
+     /tmp/cc0wMqvE.s:14661  .text.HAL_TIM_IC_Stop_DMA:000000a2 $d
+     /tmp/cc0wMqvE.s:14741  .text.HAL_TIM_OnePulse_Start:00000000 $t
+     /tmp/cc0wMqvE.s:14747  .text.HAL_TIM_OnePulse_Start:00000000 HAL_TIM_OnePulse_Start
+     /tmp/cc0wMqvE.s:14883  .text.HAL_TIM_OnePulse_Start:00000094 $d
+     /tmp/cc0wMqvE.s:14888  .text.HAL_TIM_OnePulse_Stop:00000000 $t
+     /tmp/cc0wMqvE.s:14894  .text.HAL_TIM_OnePulse_Stop:00000000 HAL_TIM_OnePulse_Stop
+     /tmp/cc0wMqvE.s:15001  .text.HAL_TIM_OnePulse_Stop:00000090 $d
+     /tmp/cc0wMqvE.s:15006  .text.HAL_TIM_OnePulse_Start_IT:00000000 $t
+     /tmp/cc0wMqvE.s:15012  .text.HAL_TIM_OnePulse_Start_IT:00000000 HAL_TIM_OnePulse_Start_IT
+     /tmp/cc0wMqvE.s:15161  .text.HAL_TIM_OnePulse_Start_IT:000000ac $d
+     /tmp/cc0wMqvE.s:15166  .text.HAL_TIM_OnePulse_Stop_IT:00000000 $t
+     /tmp/cc0wMqvE.s:15172  .text.HAL_TIM_OnePulse_Stop_IT:00000000 HAL_TIM_OnePulse_Stop_IT
+     /tmp/cc0wMqvE.s:15289  .text.HAL_TIM_OnePulse_Stop_IT:000000a4 $d
+     /tmp/cc0wMqvE.s:15294  .text.HAL_TIM_Encoder_Start:00000000 $t
+     /tmp/cc0wMqvE.s:15300  .text.HAL_TIM_Encoder_Start:00000000 HAL_TIM_Encoder_Start
+     /tmp/cc0wMqvE.s:15521  .text.HAL_TIM_Encoder_Stop:00000000 $t
+     /tmp/cc0wMqvE.s:15527  .text.HAL_TIM_Encoder_Stop:00000000 HAL_TIM_Encoder_Stop
+     /tmp/cc0wMqvE.s:15652  .text.HAL_TIM_Encoder_Start_IT:00000000 $t
+     /tmp/cc0wMqvE.s:15658  .text.HAL_TIM_Encoder_Start_IT:00000000 HAL_TIM_Encoder_Start_IT
+     /tmp/cc0wMqvE.s:15900  .text.HAL_TIM_Encoder_Stop_IT:00000000 $t
+     /tmp/cc0wMqvE.s:15906  .text.HAL_TIM_Encoder_Stop_IT:00000000 HAL_TIM_Encoder_Stop_IT
+     /tmp/cc0wMqvE.s:16052  .text.HAL_TIM_Encoder_Start_DMA:00000000 $t
+     /tmp/cc0wMqvE.s:16058  .text.HAL_TIM_Encoder_Start_DMA:00000000 HAL_TIM_Encoder_Start_DMA
+     /tmp/cc0wMqvE.s:16564  .text.HAL_TIM_Encoder_Start_DMA:00000230 $d
+     /tmp/cc0wMqvE.s:16571  .text.HAL_TIM_Encoder_Stop_DMA:00000000 $t
+     /tmp/cc0wMqvE.s:16577  .text.HAL_TIM_Encoder_Stop_DMA:00000000 HAL_TIM_Encoder_Stop_DMA
+     /tmp/cc0wMqvE.s:3898   .text.HAL_TIM_ReadCapturedValue:00000015 $d
+     /tmp/cc0wMqvE.s:3898   .text.HAL_TIM_ReadCapturedValue:00000016 $t
+     /tmp/cc0wMqvE.s:5484   .text.HAL_TIM_GetChannelState:00000019 $d
+     /tmp/cc0wMqvE.s:5484   .text.HAL_TIM_GetChannelState:0000001a $t
+     /tmp/cc0wMqvE.s:6691   .text.HAL_TIM_OC_ConfigChannel:0000002f $d
+     /tmp/cc0wMqvE.s:6691   .text.HAL_TIM_OC_ConfigChannel:00000030 $t
+     /tmp/cc0wMqvE.s:6868   .text.HAL_TIM_PWM_ConfigChannel:00000035 $d
+     /tmp/cc0wMqvE.s:6868   .text.HAL_TIM_PWM_ConfigChannel:00000036 $t
+     /tmp/cc0wMqvE.s:9242   .text.HAL_TIM_OC_Start:0000001d $d
+ARM GAS  /tmp/cc0wMqvE.s 			page 517
+
+
+     /tmp/cc0wMqvE.s:9242   .text.HAL_TIM_OC_Start:0000001e $t
+     /tmp/cc0wMqvE.s:9277   .text.HAL_TIM_OC_Start:00000049 $d
+     /tmp/cc0wMqvE.s:9277   .text.HAL_TIM_OC_Start:0000004a $t
+     /tmp/cc0wMqvE.s:9595   .text.HAL_TIM_OC_Stop:00000093 $d
+     /tmp/cc0wMqvE.s:9595   .text.HAL_TIM_OC_Stop:00000094 $t
+     /tmp/cc0wMqvE.s:9675   .text.HAL_TIM_OC_Start_IT:0000001d $d
+     /tmp/cc0wMqvE.s:9675   .text.HAL_TIM_OC_Start_IT:0000001e $t
+     /tmp/cc0wMqvE.s:9710   .text.HAL_TIM_OC_Start_IT:0000004b $d
+     /tmp/cc0wMqvE.s:9710   .text.HAL_TIM_OC_Start_IT:0000004c $t
+     /tmp/cc0wMqvE.s:10016  .text.HAL_TIM_OC_Stop_IT:0000001d $d
+     /tmp/cc0wMqvE.s:10016  .text.HAL_TIM_OC_Stop_IT:0000001e $t
+     /tmp/cc0wMqvE.s:10152  .text.HAL_TIM_OC_Stop_IT:000000db $d
+     /tmp/cc0wMqvE.s:10152  .text.HAL_TIM_OC_Stop_IT:000000dc $t
+     /tmp/cc0wMqvE.s:10253  .text.HAL_TIM_OC_Start_DMA:00000021 $d
+     /tmp/cc0wMqvE.s:10253  .text.HAL_TIM_OC_Start_DMA:00000022 $t
+     /tmp/cc0wMqvE.s:10292  .text.HAL_TIM_OC_Start_DMA:0000004f $d
+     /tmp/cc0wMqvE.s:10292  .text.HAL_TIM_OC_Start_DMA:00000050 $t
+     /tmp/cc0wMqvE.s:10855  .text.HAL_TIM_OC_Stop_DMA:0000001d $d
+     /tmp/cc0wMqvE.s:10855  .text.HAL_TIM_OC_Stop_DMA:0000001e $t
+     /tmp/cc0wMqvE.s:11016  .text.HAL_TIM_OC_Stop_DMA:000000f3 $d
+     /tmp/cc0wMqvE.s:11016  .text.HAL_TIM_OC_Stop_DMA:000000f4 $t
+     /tmp/cc0wMqvE.s:11110  .text.HAL_TIM_PWM_Start:0000001d $d
+     /tmp/cc0wMqvE.s:11110  .text.HAL_TIM_PWM_Start:0000001e $t
+     /tmp/cc0wMqvE.s:11145  .text.HAL_TIM_PWM_Start:00000049 $d
+     /tmp/cc0wMqvE.s:11145  .text.HAL_TIM_PWM_Start:0000004a $t
+     /tmp/cc0wMqvE.s:11463  .text.HAL_TIM_PWM_Stop:00000093 $d
+     /tmp/cc0wMqvE.s:11463  .text.HAL_TIM_PWM_Stop:00000094 $t
+     /tmp/cc0wMqvE.s:11543  .text.HAL_TIM_PWM_Start_IT:0000001d $d
+     /tmp/cc0wMqvE.s:11543  .text.HAL_TIM_PWM_Start_IT:0000001e $t
+     /tmp/cc0wMqvE.s:11578  .text.HAL_TIM_PWM_Start_IT:0000004b $d
+     /tmp/cc0wMqvE.s:11578  .text.HAL_TIM_PWM_Start_IT:0000004c $t
+     /tmp/cc0wMqvE.s:11884  .text.HAL_TIM_PWM_Stop_IT:0000001d $d
+     /tmp/cc0wMqvE.s:11884  .text.HAL_TIM_PWM_Stop_IT:0000001e $t
+     /tmp/cc0wMqvE.s:12020  .text.HAL_TIM_PWM_Stop_IT:000000db $d
+     /tmp/cc0wMqvE.s:12020  .text.HAL_TIM_PWM_Stop_IT:000000dc $t
+     /tmp/cc0wMqvE.s:12121  .text.HAL_TIM_PWM_Start_DMA:00000021 $d
+     /tmp/cc0wMqvE.s:12121  .text.HAL_TIM_PWM_Start_DMA:00000022 $t
+     /tmp/cc0wMqvE.s:12160  .text.HAL_TIM_PWM_Start_DMA:0000004f $d
+     /tmp/cc0wMqvE.s:12160  .text.HAL_TIM_PWM_Start_DMA:00000050 $t
+     /tmp/cc0wMqvE.s:12723  .text.HAL_TIM_PWM_Stop_DMA:0000001d $d
+     /tmp/cc0wMqvE.s:12723  .text.HAL_TIM_PWM_Stop_DMA:0000001e $t
+     /tmp/cc0wMqvE.s:12884  .text.HAL_TIM_PWM_Stop_DMA:000000f3 $d
+     /tmp/cc0wMqvE.s:12884  .text.HAL_TIM_PWM_Stop_DMA:000000f4 $t
+     /tmp/cc0wMqvE.s:12977  .text.HAL_TIM_IC_Start:0000001d $d
+     /tmp/cc0wMqvE.s:12977  .text.HAL_TIM_IC_Start:0000001e $t
+     /tmp/cc0wMqvE.s:13025  .text.HAL_TIM_IC_Start:00000051 $d
+     /tmp/cc0wMqvE.s:13025  .text.HAL_TIM_IC_Start:00000052 $t
+     /tmp/cc0wMqvE.s:13318  .text.HAL_TIM_IC_Stop:00000053 $d
+     /tmp/cc0wMqvE.s:13318  .text.HAL_TIM_IC_Stop:00000054 $t
+     /tmp/cc0wMqvE.s:13418  .text.HAL_TIM_IC_Start_IT:0000001d $d
+     /tmp/cc0wMqvE.s:13418  .text.HAL_TIM_IC_Start_IT:0000001e $t
+     /tmp/cc0wMqvE.s:13466  .text.HAL_TIM_IC_Start_IT:00000051 $d
+     /tmp/cc0wMqvE.s:13466  .text.HAL_TIM_IC_Start_IT:00000052 $t
+     /tmp/cc0wMqvE.s:13570  .text.HAL_TIM_IC_Start_IT:000000cf $d
+     /tmp/cc0wMqvE.s:13570  .text.HAL_TIM_IC_Start_IT:000000d0 $t
+     /tmp/cc0wMqvE.s:13791  .text.HAL_TIM_IC_Stop_IT:0000001b $d
+     /tmp/cc0wMqvE.s:13791  .text.HAL_TIM_IC_Stop_IT:0000001c $t
+ARM GAS  /tmp/cc0wMqvE.s 			page 518
+
+
+     /tmp/cc0wMqvE.s:13887  .text.HAL_TIM_IC_Stop_IT:00000099 $d
+     /tmp/cc0wMqvE.s:13887  .text.HAL_TIM_IC_Stop_IT:0000009a $t
+     /tmp/cc0wMqvE.s:14008  .text.HAL_TIM_IC_Start_DMA:00000025 $d
+     /tmp/cc0wMqvE.s:14008  .text.HAL_TIM_IC_Start_DMA:00000026 $t
+     /tmp/cc0wMqvE.s:14068  .text.HAL_TIM_IC_Start_DMA:0000006d $d
+     /tmp/cc0wMqvE.s:14068  .text.HAL_TIM_IC_Start_DMA:0000006e $t
+     /tmp/cc0wMqvE.s:14199  .text.HAL_TIM_IC_Start_DMA:00000103 $d
+     /tmp/cc0wMqvE.s:14199  .text.HAL_TIM_IC_Start_DMA:00000104 $t
+     /tmp/cc0wMqvE.s:14570  .text.HAL_TIM_IC_Stop_DMA:00000023 $d
+     /tmp/cc0wMqvE.s:14570  .text.HAL_TIM_IC_Stop_DMA:00000024 $t
+     /tmp/cc0wMqvE.s:14674  .text.HAL_TIM_IC_Stop_DMA:000000af $d
+     /tmp/cc0wMqvE.s:14674  .text.HAL_TIM_IC_Stop_DMA:000000b0 $t
+
+UNDEFINED SYMBOLS
+HAL_DMA_Start_IT
+HAL_DMA_Abort_IT
+TIMEx_DMACommutationCplt
+TIMEx_DMACommutationHalfCplt
+HAL_TIMEx_BreakCallback
+HAL_TIMEx_Break2Callback
+HAL_TIMEx_CommutCallback
+HAL_TIMEx_EncoderIndexCallback
+HAL_TIMEx_DirectionChangeCallback
+HAL_TIMEx_IndexErrorCallback
+HAL_TIMEx_TransitionErrorCallback
diff --git a/squeow_sw/build/stm32g4xx_hal_tim.o b/squeow_sw/build/stm32g4xx_hal_tim.o
new file mode 100644
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diff --git a/squeow_sw/build/stm32g4xx_hal_tim_ex.d b/squeow_sw/build/stm32g4xx_hal_tim_ex.d
new file mode 100644
index 0000000..f34069f
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_tim_ex.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_tim_ex.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_tim_ex.lst b/squeow_sw/build/stm32g4xx_hal_tim_ex.lst
new file mode 100644
index 0000000..bf4f497
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_tim_ex.lst
@@ -0,0 +1,14004 @@
+ARM GAS  /tmp/cc9HXhVl.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_tim_ex.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c"
+  20              		.section	.text.TIM_CCxNChannelCmd,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	TIM_CCxNChannelCmd:
+  27              	.LVL0:
+  28              	.LFB397:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @file    stm32g4xx_hal_tim_ex.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief   TIM HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          functionalities of the Timer Extended peripheral:
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           + Time Hall Sensor Interface Initialization
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           + Time Hall Sensor Interface Start
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           + Time Complementary signal break and dead time configuration
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           + Time Master and Slave synchronization configuration
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           + Time OCRef clear configuration
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           + Timer remapping capabilities configuration
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           + Timer encoder index configuration
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ******************************************************************************
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @attention
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * Copyright (c) 2019 STMicroelectronics.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * All rights reserved.
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * in the root directory of this software component.
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ******************************************************************************
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   @verbatim
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                       ##### TIMER Extended features #####
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+ARM GAS  /tmp/cc9HXhVl.s 			page 2
+
+
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   [..]
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     The Timer Extended features include:
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (#) Complementary outputs with programmable dead-time for :
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         (++) Output Compare
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         (++) PWM generation (Edge and Center-aligned Mode)
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         (++) One-pulse mode output
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (#) Synchronization circuit to control the timer with external signals and to
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         interconnect several timers together.
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (#) Break input to put the timer output signals in reset state or in a known state.
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         positioning purposes
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (#) In case of Pulse on compare, configure pulse length and delay
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (#) Encoder index configuration
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             ##### How to use this driver #####
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     [..]
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****      (#) Initialize the TIM low level resources by implementing the following functions
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****          depending on the selected feature:
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****            (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****      (#) Initialize the TIM low level resources :
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         (##) TIM pins configuration
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             (+++) Enable the clock for the TIM GPIOs using the following function:
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****               __HAL_RCC_GPIOx_CLK_ENABLE();
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****      (#) The external Clock can be configured, if needed (the default clock is the
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****          internal clock from the APBx), using the following function:
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****          HAL_TIM_ConfigClockSource, the clock configuration should be done before
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****          any start function.
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****      (#) Configure the TIM in the desired functioning mode using one of the
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****          initialization function of this driver:
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                Timer Hall Sensor Interface and the commutation event with the corresponding
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                Interrupt and DMA request if needed (Note that One Timer is used to interface
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                with the Hall sensor Interface and another Timer should be used to use
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                the commutation event).
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****      (#) In case of Pulse On Compare:
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****            (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****      (#) Activate the TIM peripheral using one of the start functions:
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                 HAL_TIMEx_OCN_Start_IT()
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                 HAL_TIMEx_PWMN_Start_IT()
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePul
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA()
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                 HAL_TIMEx_HallSensor_Start_IT().
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   @endverbatim
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ******************************************************************************
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 3
+
+
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /* Includes ------------------------------------------------------------------*/
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #include "stm32g4xx_hal.h"
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @{
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /** @defgroup TIMEx TIMEx
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief TIM Extended HAL module driver
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @{
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #ifdef HAL_TIM_MODULE_ENABLED
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /* Private typedef -----------------------------------------------------------*/
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /* Private define ------------------------------------------------------------*/
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /* Private constants ---------------------------------------------------------*/
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @{
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /* Timeout for break input rearm */
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #define TIM_BREAKINPUT_REARM_TIMEOUT    5UL /* 5 milliseconds */
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @}
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /* End of private constants --------------------------------------------------*/
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /* Private macros ------------------------------------------------------------*/
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /* Private variables ---------------------------------------------------------*/
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /* Private function prototypes -----------------------------------------------*/
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /* Exported functions --------------------------------------------------------*/
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @{
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief    Timer Hall Sensor functions
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @verbatim
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                       ##### Timer Hall Sensor functions #####
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   [..]
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     This section provides functions allowing to:
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Initialize and configure TIM HAL Sensor.
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) De-initialize TIM HAL Sensor.
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Hall Sensor Interface.
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Hall Sensor Interface.
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Hall Sensor Interface and enable interrupts.
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Hall Sensor Interface and disable interrupts.
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Hall Sensor Interface and enable DMA transfers.
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Hall Sensor Interface and disable DMA transfers.
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 4
+
+
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @endverbatim
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @{
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   When the timer instance is initialized in Hall Sensor Interface mode,
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         timer channels 1 and channel 2 are reserved and cannot be used for
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         other purpose.
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  sConfig TIM Hall Sensor configuration structure
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sC
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_OC_InitTypeDef OC_Config;
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the TIM handle allocation */
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (htim == NULL)
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Allocate lock resource and initialize it */
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Lock = HAL_UNLOCKED;
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Reset interrupt callbacks to legacy week callbacks */
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_ResetCallback(htim);
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (htim->HallSensor_MspInitCallback == NULL)
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->HallSensor_MspInitCallback(htim);
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #else
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     HAL_TIMEx_HallSensor_MspInit(htim);
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM state */
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Configure the Time base in the Encoder Mode */
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ARM GAS  /tmp/cc9HXhVl.s 			page 5
+
+
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sens
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Reset the IC1PSC Bits */
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the IC1PSC value */
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Hall sensor interface (XOR function of the three inputs) */
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_CR2_TI1S;
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCMode = TIM_OCMODE_PWM2;
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.Pulse = sConfig->Commutation_Delay;
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     register to 101 */
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Initialize the DMA burst operation state */
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Initialize the TIM channels state */
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Initialize the TIM state*/
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_READY;
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  DeInitializes the TIM Hall Sensor interface
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+ARM GAS  /tmp/cc9HXhVl.s 			page 6
+
+
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the TIM Peripheral Clock */
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (htim->HallSensor_MspDeInitCallback == NULL)
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* DeInit the low level hardware */
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->HallSensor_MspDeInitCallback(htim);
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #else
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIMEx_HallSensor_MspDeInit(htim);
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Change the DMA burst operation state */
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Change the TIM channels state */
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Change TIM state */
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_RESET;
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Release Lock */
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Initializes the TIM Hall Sensor MSP.
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   UNUSED(htim);
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****    */
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  DeInitializes TIM Hall Sensor MSP.
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ARM GAS  /tmp/cc9HXhVl.s 			page 7
+
+
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   UNUSED(htim);
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****    */
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Starts the TIM Hall Sensor Interface.
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the TIM channels state */
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM channels state */
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Input Capture channel 1
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ARM GAS  /tmp/cc9HXhVl.s 			page 8
+
+
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE(htim);
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Stops the TIM Hall sensor Interface.
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Input Capture channels 1, 2 and 3
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM channels state */
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the TIM channels state */
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ARM GAS  /tmp/cc9HXhVl.s 			page 9
+
+
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM channels state */
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the capture compare Interrupts 1 event */
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Input Capture channel 1
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE(htim);
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Input Capture channel 1
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the capture compare Interrupts event */
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+ARM GAS  /tmp/cc9HXhVl.s 			page 10
+
+
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM channels state */
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  pData The destination Buffer address.
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Length The length of data to be transferred from TIM peripheral to memory.
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM channel state */
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_BUSY;
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****            && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if ((pData == NULL) && (Length > 0U))
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       return HAL_ERROR;
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     else
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Input Capture channel 1
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the DMA Input Capture 1 Callbacks */
+ARM GAS  /tmp/cc9HXhVl.s 			page 11
+
+
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the DMA channel for Capture 1*/
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Return error status */
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the capture compare 1 Interrupt */
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE(htim);
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Input Capture channel 1
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the capture compare Interrupts 1 event */
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM channel state */
+ARM GAS  /tmp/cc9HXhVl.s 			page 12
+
+
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @}
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *  @brief   Timer Complementary Output Compare functions
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @verbatim
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****               ##### Timer Complementary Output Compare functions #####
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   [..]
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     This section provides functions allowing to:
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary Output Compare/PWM.
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary Output Compare/PWM.
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary Output Compare/PWM and enable interrupts.
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @endverbatim
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @{
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Starts the TIM Output Compare signal generation on the complementary
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         output.
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Output Compare handle
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be enabled
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the TIM complementary channel state */
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+ARM GAS  /tmp/cc9HXhVl.s 			page 13
+
+
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Capture compare channel N */
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Main Output */
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_MOE_ENABLE(htim);
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE(htim);
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Stops the TIM Output Compare signal generation on the complementary
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         output.
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Capture compare channel N */
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Main Output */
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_MOE_DISABLE(htim);
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ARM GAS  /tmp/cc9HXhVl.s 			page 14
+
+
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         on the complementary output.
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM OC handle
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be enabled
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the TIM complementary channel state */
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (Channel)
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare interrupt */
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare interrupt */
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare interrupt */
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_4:
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ARM GAS  /tmp/cc9HXhVl.s 			page 15
+
+
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare interrupt */
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       status = HAL_ERROR;
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (status == HAL_OK)
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the TIM Break interrupt */
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the Capture compare channel N */
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the Main Output */
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_MOE_ENABLE(htim);
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         __HAL_TIM_ENABLE(htim);
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     else
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return status;
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         on the complementary output.
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Output Compare handle
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpccer;
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 16
+
+
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (Channel)
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare interrupt */
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare interrupt */
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare interrupt */
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_4:
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare interrupt */
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       status = HAL_ERROR;
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (status == HAL_OK)
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the Capture compare channel N */
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the TIM Break interrupt (only if no more channel is active) */
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     tmpccer = htim->Instance->CCER;
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE  | TIM_CCER_CC4NE)) == (uint32
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the Main Output */
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_MOE_DISABLE(htim);
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the Peripheral */
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_DISABLE(htim);
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Set the TIM complementary channel state */
+ARM GAS  /tmp/cc9HXhVl.s 			page 17
+
+
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return status;
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Starts the TIM Output Compare signal generation in DMA mode
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         on the complementary output.
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Output Compare handle
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be enabled
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  pData The source Buffer address.
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Length The length of data to be transferred from memory to TIM peripheral
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pDat
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_BUSY;
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if ((pData == NULL) && (Length > 0U))
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       return HAL_ERROR;
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     else
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (Channel)
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ARM GAS  /tmp/cc9HXhVl.s 			page 18
+
+
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the DMA channel */
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Return error status */
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         return HAL_ERROR;
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare DMA request */
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the DMA channel */
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Return error status */
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         return HAL_ERROR;
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare DMA request */
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the DMA channel */
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Return error status */
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         return HAL_ERROR;
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare DMA request */
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ARM GAS  /tmp/cc9HXhVl.s 			page 19
+
+
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_4:
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the DMA channel */
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Return error status */
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         return HAL_ERROR;
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare DMA request */
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       status = HAL_ERROR;
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (status == HAL_OK)
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the Capture compare channel N */
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the Main Output */
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_MOE_ENABLE(htim);
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         __HAL_TIM_ENABLE(htim);
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     else
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return status;
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Stops the TIM Output Compare signal generation in DMA mode
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         on the complementary output.
+ARM GAS  /tmp/cc9HXhVl.s 			page 20
+
+
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Output Compare handle
+1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (Channel)
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare DMA request */
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare DMA request */
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare DMA request */
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_4:
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare interrupt */
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       status = HAL_ERROR;
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (status == HAL_OK)
+1113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc9HXhVl.s 			page 21
+
+
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the Capture compare channel N */
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the Main Output */
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_MOE_DISABLE(htim);
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the Peripheral */
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_DISABLE(htim);
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Set the TIM complementary channel state */
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return status;
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @}
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief    Timer Complementary PWM functions
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @verbatim
+1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                  ##### Timer Complementary PWM functions #####
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   [..]
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     This section provides functions allowing to:
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary PWM.
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary PWM.
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary PWM and enable interrupts.
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary PWM and disable interrupts.
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary PWM and enable DMA transfers.
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary PWM and disable DMA transfers.
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary Input Capture measurement.
+1151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary Input Capture.
+1152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary Input Capture and enable interrupts.
+1153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary Input Capture and disable interrupts.
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary Input Capture and enable DMA transfers.
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary Input Capture and disable DMA transfers.
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary One Pulse generation.
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary One Pulse.
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary One Pulse and enable interrupts.
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary One Pulse and disable interrupts.
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @endverbatim
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @{
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Starts the PWM signal generation on the complementary output.
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be enabled
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ARM GAS  /tmp/cc9HXhVl.s 			page 22
+
+
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the TIM complementary channel state */
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the complementary PWM output  */
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+1194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Main Output */
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_MOE_ENABLE(htim);
+1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else
+1208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE(htim);
+1210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Stops the PWM signal generation on the complementary output.
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+1226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+ARM GAS  /tmp/cc9HXhVl.s 			page 23
+
+
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the complementary PWM output  */
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Main Output */
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_MOE_DISABLE(htim);
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+1240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Starts the PWM signal generation in interrupt mode on the
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         complementary output.
+1251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the TIM complementary channel state */
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (Channel)
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+1280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 1 interrupt */
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ARM GAS  /tmp/cc9HXhVl.s 			page 24
+
+
+1285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 2 interrupt */
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 3 interrupt */
+1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_4:
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 4 interrupt */
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+1304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       status = HAL_ERROR;
+1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (status == HAL_OK)
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the TIM Break interrupt */
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+1316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the complementary PWM output  */
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+1319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the Main Output */
+1321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_MOE_ENABLE(htim);
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         __HAL_TIM_ENABLE(htim);
+1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     else
+1333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return status;
+1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 25
+
+
+1342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Stops the PWM signal generation in interrupt mode on the
+1344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         complementary output.
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+1353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpccer;
+1358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (Channel)
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 1 interrupt */
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+1368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 2 interrupt */
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 3 interrupt */
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_4:
+1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 4 interrupt */
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       status = HAL_ERROR;
+1394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (status == HAL_OK)
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc9HXhVl.s 			page 26
+
+
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the complementary PWM output  */
+1400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+1401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the TIM Break interrupt (only if no more channel is active) */
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     tmpccer = htim->Instance->CCER;
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE  | TIM_CCER_CC4NE)) == (uint32
+1405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the Main Output */
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_MOE_DISABLE(htim);
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the Peripheral */
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_DISABLE(htim);
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Set the TIM complementary channel state */
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return status;
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Starts the TIM PWM signal generation in DMA mode on the
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         complementary output
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be enabled
+1428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  pData The source Buffer address.
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Length The length of data to be transferred from memory to TIM peripheral
+1435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+1436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pDa
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+1439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+1440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_BUSY;
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if ((pData == NULL) && (Length > 0U))
+1453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       return HAL_ERROR;
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ARM GAS  /tmp/cc9HXhVl.s 			page 27
+
+
+1456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     else
+1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else
+1462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+1464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (Channel)
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+1469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+1476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the DMA channel */
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+1480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Return error status */
+1482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         return HAL_ERROR;
+1483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+1484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 1 DMA request */
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+1486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the DMA channel */
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+1501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Return error status */
+1503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         return HAL_ERROR;
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+1505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 2 DMA request */
+1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+ARM GAS  /tmp/cc9HXhVl.s 			page 28
+
+
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the DMA channel */
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+1523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Return error status */
+1524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         return HAL_ERROR;
+1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 3 DMA request */
+1527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_4:
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
+1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the DMA channel */
+1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Return error status */
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         return HAL_ERROR;
+1546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+1547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 4 DMA request */
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       status = HAL_ERROR;
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (status == HAL_OK)
+1558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the complementary PWM output  */
+1560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+1561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the Main Output */
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_MOE_ENABLE(htim);
+1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ARM GAS  /tmp/cc9HXhVl.s 			page 29
+
+
+1570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         __HAL_TIM_ENABLE(htim);
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+1573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     else
+1575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+1581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return status;
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         output
+1587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+1589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+1595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+1598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+1599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (Channel)
+1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+1606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 1 DMA request */
+1608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+1610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 2 DMA request */
+1616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+1618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 3 DMA request */
+1624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ARM GAS  /tmp/cc9HXhVl.s 			page 30
+
+
+1627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_4:
+1630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 4 DMA request */
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+1638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       status = HAL_ERROR;
+1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (status == HAL_OK)
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the complementary PWM output */
+1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+1646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the Main Output */
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_MOE_DISABLE(htim);
+1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Disable the Peripheral */
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     __HAL_TIM_DISABLE(htim);
+1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Set the TIM complementary channel state */
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+1658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return status;
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @}
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+1666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief    Timer Complementary One Pulse functions
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @verbatim
+1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+1670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                 ##### Timer Complementary One Pulse functions #####
+1671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   [..]
+1673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     This section provides functions allowing to:
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary One Pulse generation.
+1675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary One Pulse.
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Start the Complementary One Pulse and enable interrupts.
+1677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Stop the Complementary One Pulse and disable interrupts.
+1678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @endverbatim
+1680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @{
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ARM GAS  /tmp/cc9HXhVl.s 			page 31
+
+
+1684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Starts the TIM One Pulse signal generation on the complementary
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         output.
+1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note OutputChannel must match the pulse output channel chosen when calling
+1687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM One Pulse handle
+1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  OutputChannel pulse output channel to enable
+1690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+1694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the TIM channels state */
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+1708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+1713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM channels state */
+1716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+1719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the complementary One Pulse output channel and the Input Capture channel */
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Main Output */
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_MOE_ENABLE(htim);
+1727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+1729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Stops the TIM One Pulse signal generation on the complementary
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         output.
+1735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note OutputChannel must match the pulse output channel chosen when calling
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM One Pulse handle
+1738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  OutputChannel pulse output channel to disable
+1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ARM GAS  /tmp/cc9HXhVl.s 			page 32
+
+
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+1743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+1750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the complementary One Pulse output channel and the Input Capture channel */
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Main Output */
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_MOE_DISABLE(htim);
+1757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+1760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM  channels state */
+1762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+1763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+1765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+1768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         complementary channel.
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note OutputChannel must match the pulse output channel chosen when calling
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM One Pulse handle
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  OutputChannel pulse output channel to enable
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+1782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+1790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the TIM channels state */
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+1796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+1797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ARM GAS  /tmp/cc9HXhVl.s 			page 33
+
+
+1798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+1799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     return HAL_ERROR;
+1801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM channels state */
+1804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+1805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+1808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the TIM Capture/Compare 1 interrupt */
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+1811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the TIM Capture/Compare 2 interrupt */
+1813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+1814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the complementary One Pulse output channel and the Input Capture channel */
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+1817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+1818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Main Output */
+1820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_MOE_ENABLE(htim);
+1821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+1828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         complementary channel.
+1829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note OutputChannel must match the pulse output channel chosen when calling
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+1831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM One Pulse handle
+1832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  OutputChannel pulse output channel to disable
+1833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+1841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+1843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+1844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the TIM Capture/Compare 1 interrupt */
+1846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+1847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the TIM Capture/Compare 2 interrupt */
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+1850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the complementary One Pulse output channel and the Input Capture channel */
+1852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+1854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 34
+
+
+1855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Main Output */
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_MOE_DISABLE(htim);
+1857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+1859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM  channels state */
+1862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+1863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+1864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+1866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Return function status */
+1868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+1869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @}
+1873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+1876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief    Peripheral Control functions
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+1878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @verbatim
+1879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                     ##### Peripheral Control functions #####
+1881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+1882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   [..]
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     This section provides functions allowing to:
+1884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (+) Configure the commutation event in case of use of the Hall sensor interface.
+1885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (+) Configure Output channels for OC and PWM mode.
+1886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (+) Configure Complementary channels, break features and dead time.
+1888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (+) Configure Master synchronization.
+1889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (+) Configure timer remapping capabilities.
+1890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (+) Select timer input source.
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (+) Enable or disable channel grouping.
+1892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (+) Configure Pulse on compare.
+1893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (+) Configure Encoder index.
+1894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @endverbatim
+1896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @{
+1897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Configure the TIM commutation event sequence.
+1901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note  This function is mandatory to use the commutation event in order to
+1902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        update the configuration at each commutation detection on the TRGI input of the Timer,
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        the typical use of this feature is with the use of another Timer(interface Timer)
+1904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        configured in Hall sensor interface, this interface Timer will generate the
+1905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        commutation at its TRGO output (connected to Timer used in this function) each time
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+1907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall 
+1909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+1911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+ARM GAS  /tmp/cc9HXhVl.s 			page 35
+
+
+1912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+1914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR4: Internal trigger 4 selected   (*)
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR5: Internal trigger 5 selected
+1916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR6: Internal trigger 6 selected
+1917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR7: Internal trigger 7 selected
+1918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR8: Internal trigger 8 selected
+1919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR9: Internal trigger 9 selected   (*)
+1920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR10: Internal trigger 10 selected
+1921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR11: Internal trigger 11 selected
+1922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_NONE: No trigger is needed
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+1924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         (*)  Value not defined in all devices.
+1925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+1926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  CommutationSource the Commutation Event source
+1927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+1929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG
+1930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+1932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+1933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                                               uint32_t  CommutationSource)
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+1935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+1936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+1938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #if defined(TIM5) && defined(TIM20)
+1942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+1943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+1944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR9) ||
+1947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #elif defined(TIM5)
+1949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+1950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
+1952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
+1953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR11))
+1954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #elif defined(TIM20)
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+1956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+1957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
+1958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
+1959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR9)  || (InputTrigger == TIM_TS_ITR11))
+1960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #else
+1961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+1962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+1963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
+1964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
+1965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR11))
+1966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* TIM5 && TIM20 */
+1967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+1968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Select the Input trigger */
+ARM GAS  /tmp/cc9HXhVl.s 			page 36
+
+
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR &= ~TIM_SMCR_TS;
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+1971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Capture Compare preload feature */
+1974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_CR2_CCPC;
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+1976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+1977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+1978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable Commutation Interrupt */
+1980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+1981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable Commutation DMA request */
+1983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+1984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+1988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+1989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+1990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+1991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Configure the TIM commutation event sequence with interrupt.
+1992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note  This function is mandatory to use the commutation event in order to
+1993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        update the configuration at each commutation detection on the TRGI input of the Timer,
+1994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        the typical use of this feature is with the use of another Timer(interface Timer)
+1995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        configured in Hall sensor interface, this interface Timer will generate the
+1996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        commutation at its TRGO output (connected to Timer used in this function) each time
+1997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+1998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall 
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+2001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+2002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+2003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+2004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+2005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR4: Internal trigger 4 selected   (*)
+2006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR5: Internal trigger 5 selected
+2007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR6: Internal trigger 6 selected
+2008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR7: Internal trigger 7 selected
+2009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR8: Internal trigger 8 selected
+2010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR9: Internal trigger 9 selected   (*)
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR10: Internal trigger 10 selected
+2012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR11: Internal trigger 11 selected
+2013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_NONE: No trigger is needed
+2014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         (*)  Value not defined in all devices.
+2016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  CommutationSource the Commutation Event source
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+2019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+2020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+2022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+2023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                                                  uint32_t  CommutationSource)
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+ARM GAS  /tmp/cc9HXhVl.s 			page 37
+
+
+2026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+2028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+2029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+2031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #if defined(TIM5) && defined(TIM20)
+2033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+2034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+2035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
+2036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
+2037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR9) ||
+2038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
+2039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #elif defined(TIM5)
+2040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+2041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR11))
+2045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #elif defined(TIM20)
+2046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+2047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+2048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
+2049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR9)  || (InputTrigger == TIM_TS_ITR11))
+2051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #else
+2052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+2054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
+2055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
+2056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR11))
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* TIM5 && TIM20 */
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+2059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Select the Input trigger */
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR &= ~TIM_SMCR_TS;
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+2062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+2063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Capture Compare preload feature */
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_CR2_CCPC;
+2066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+2069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable Commutation DMA request */
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+2072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Commutation Interrupt */
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+2075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+2080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Configure the TIM commutation event sequence with DMA.
+ARM GAS  /tmp/cc9HXhVl.s 			page 38
+
+
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note  This function is mandatory to use the commutation event in order to
+2084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        update the configuration at each commutation detection on the TRGI input of the Timer,
+2085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        the typical use of this feature is with the use of another Timer(interface Timer)
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        configured in Hall sensor interface, this interface Timer will generate the
+2087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        commutation at its TRGO output (connected to Timer used in this function) each time
+2088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+2089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note  The user should configure the DMA in his own software, in This function only the COMDE b
+2090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+2091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall 
+2092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+2093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+2094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+2095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+2097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR4: Internal trigger 4 selected   (*)
+2098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR5: Internal trigger 5 selected
+2099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR6: Internal trigger 6 selected
+2100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR7: Internal trigger 7 selected
+2101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR8: Internal trigger 8 selected
+2102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR9: Internal trigger 9 selected   (*)
+2103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR10: Internal trigger 10 selected
+2104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR11: Internal trigger 11 selected
+2105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TS_NONE: No trigger is needed
+2106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         (*)  Value not defined in all devices.
+2108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  CommutationSource the Commutation Event source
+2110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+2111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+2112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG
+2113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+2114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+2115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+2116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                                                   uint32_t  CommutationSource)
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+2118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+2119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+2121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+2123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #if defined(TIM5) && defined(TIM20)
+2125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+2126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+2127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
+2128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
+2129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR9) ||
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
+2131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #elif defined(TIM5)
+2132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+2133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+2134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
+2135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
+2136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR11))
+2137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #elif defined(TIM20)
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+ARM GAS  /tmp/cc9HXhVl.s 			page 39
+
+
+2140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
+2141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
+2142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR9)  || (InputTrigger == TIM_TS_ITR11))
+2143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #else
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+2146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
+2147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR11))
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* TIM5 && TIM20 */
+2150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Select the Input trigger */
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR &= ~TIM_SMCR_TS;
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+2155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Capture Compare preload feature */
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_CR2_CCPC;
+2158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Commutation DMA Request */
+2163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the DMA Commutation Callback */
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+2166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+2168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Disable Commutation Interrupt */
+2170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Enable the Commutation DMA Request */
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+2174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+2179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+2181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Configures the TIM in master mode.
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle.
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+2184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         contains the selected trigger output (TRGO) and the Master/Slave
+2185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         mode.
+2186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+2187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                                                         TIM_MasterConfigTypeDef *sMasterConfig)
+2190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+2191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpcr2;
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+2195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ARM GAS  /tmp/cc9HXhVl.s 			page 40
+
+
+2197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+2198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check input state */
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+2201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Change the handler state */
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_BUSY;
+2204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Get the TIMx CR2 register value */
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   tmpcr2 = htim->Instance->CR2;
+2207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Get the TIMx SMCR register value */
+2209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   tmpsmcr = htim->Instance->SMCR;
+2210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+2212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+2213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+2214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Check the parameters */
+2215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+2216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Clear the MMS2 bits */
+2218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     tmpcr2 &= ~TIM_CR2_MMS2;
+2219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Select the TRGO2 source*/
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+2221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Reset the MMS Bits */
+2224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   tmpcr2 &= ~TIM_CR2_MMS;
+2225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the TRGO source */
+2226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+2227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Update TIMx CR2 */
+2229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 = tmpcr2;
+2230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+2232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+2233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Reset the MSM Bit */
+2234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     tmpsmcr &= ~TIM_SMCR_MSM;
+2235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Set master mode */
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     tmpsmcr |= sMasterConfig->MasterSlaveMode;
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Update TIMx SMCR */
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR = tmpsmcr;
+2240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+2241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Change the htim state */
+2243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_READY;
+2244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+2248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+2249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+2251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+2252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         and the AOE(automatic output enable).
+2253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+ARM GAS  /tmp/cc9HXhVl.s 			page 41
+
+
+2254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+2255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         contains the BDTR Register configuration  information for the TIM peripheral.
+2256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   Interrupts can be generated when an active level is detected on the
+2257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         break input, the break 2 input or the system break input. Break
+2258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+2259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+2260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+2261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+2262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                                                 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfi
+2263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+2264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+2265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpbdtr = 0U;
+2266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+2268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+2269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+2270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+2271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+2272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+2273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+2275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+2276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check input state */
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+2282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****      the OSSI State, the dead time value and the Automatic Output Enable Bit */
+2283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the BDTR bits */
+2285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+2287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+2288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+2289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+2291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+2292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+2293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
+2295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+2296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Check the parameters */
+2297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
+2298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Set BREAK AF mode */
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
+2301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+2302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+2304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+2305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Check the parameters */
+2306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+2307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+2308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+2309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Set the BREAK2 input related BDTR bits */
+ARM GAS  /tmp/cc9HXhVl.s 			page 42
+
+
+2311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+2313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+2314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
+2316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Check the parameters */
+2318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
+2319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set BREAK2 AF mode */
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
+2322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+2324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set TIMx_BDTR */
+2326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->BDTR = tmpbdtr;
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+2332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+2334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Configures the break input source.
+2335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle.
+2336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  BreakInput Break input to configure
+2337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+2338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_BREAKINPUT_BRK: Timer break input
+2339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+2340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  sBreakInputConfig Break input source configuration
+2341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+2342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+2344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                                              uint32_t BreakInput,
+2345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                                              TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+2348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+2349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmporx;
+2350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t bkin_enable_mask;
+2351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t bkin_polarity_mask;
+2352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t bkin_enable_bitpos;
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t bkin_polarity_bitpos;
+2354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+2356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+2357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUT(BreakInput));
+2358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+2359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check input state */
+2363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+2364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (sBreakInputConfig->Source)
+2366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+2367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUTSOURCE_BKIN:
+ARM GAS  /tmp/cc9HXhVl.s 			page 43
+
+
+2368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_mask = TIM1_AF1_BKINE;
+2370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+2371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKINP;
+2372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+2373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUTSOURCE_COMP1:
+2376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_mask = TIM1_AF1_BKCMP1E;
+2378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
+2379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKCMP1P;
+2380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
+2381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUTSOURCE_COMP2:
+2384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_mask = TIM1_AF1_BKCMP2E;
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKCMP2P;
+2388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
+2389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUTSOURCE_COMP3:
+2392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_mask = TIM1_AF1_BKCMP3E;
+2394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos;
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKCMP3P;
+2396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos;
+2397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUTSOURCE_COMP4:
+2400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_mask = TIM1_AF1_BKCMP4E;
+2402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKCMP4E_Pos;
+2403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKCMP4P;
+2404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos;
+2405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #if defined (COMP5)
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUTSOURCE_COMP5:
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_mask = TIM1_AF1_BKCMP5E;
+2411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKCMP5E_Pos;
+2412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
+2413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = 0U;
+2414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = 0U;
+2415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* COMP5 */
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #if defined (COMP6)
+2419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUTSOURCE_COMP6:
+2420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_mask = TIM1_AF1_BKCMP6E;
+2422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKCMP6E_Pos;
+2423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
+2424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = 0U;
+ARM GAS  /tmp/cc9HXhVl.s 			page 44
+
+
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = 0U;
+2426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* COMP7 */
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #if defined (COMP7)
+2430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUTSOURCE_COMP7:
+2431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_mask = TIM1_AF1_BKCMP7E;
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKCMP7E_Pos;
+2434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
+2435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = 0U;
+2436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = 0U;
+2437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* COMP7 */
+2440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+2442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_mask = 0U;
+2444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = 0U;
+2445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = 0U;
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = 0U;
+2447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+2450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (BreakInput)
+2452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+2453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUT_BRK:
+2454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Get the TIMx_AF1 register value */
+2456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx = htim->Instance->AF1;
+2457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the break input */
+2459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx &= ~bkin_enable_mask;
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+2461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the break input polarity */
+2463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx &= ~bkin_polarity_mask;
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+2465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set TIMx_AF1 */
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->Instance->AF1 = tmporx;
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUT_BRK2:
+2471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Get the TIMx_AF2 register value */
+2473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx = htim->Instance->AF2;
+2474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Enable the break input */
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx &= ~bkin_enable_mask;
+2477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+2478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set the break input polarity */
+2480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx &= ~bkin_polarity_mask;
+2481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ARM GAS  /tmp/cc9HXhVl.s 			page 45
+
+
+2482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Set TIMx_AF2 */
+2484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->Instance->AF2 = tmporx;
+2485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+2488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       status = HAL_ERROR;
+2489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+2491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return status;
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+2496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+2498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Configures the TIMx Remapping input capabilities.
+2499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle.
+2500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Remap specifies the TIM remapping source.
+2501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM1, the parameter can take one of the following values:
+2502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_GPIO           TIM1 ETR is connected to GPIO
+2503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_COMP1          TIM1 ETR is connected to COMP1 output
+2504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_COMP2          TIM1 ETR is connected to COMP2 output
+2505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_COMP3          TIM1 ETR is connected to COMP3 output
+2506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_COMP4          TIM1 ETR is connected to COMP4 output
+2507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_COMP5          TIM1 ETR is connected to COMP5 output    (*)
+2508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_COMP6          TIM1 ETR is connected to COMP6 output    (*)
+2509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_COMP7          TIM1 ETR is connected to COMP7 output    (*)
+2510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_ADC1_AWD1      TIM1 ETR is connected to ADC1 AWD1
+2511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_ADC1_AWD2      TIM1 ETR is connected to ADC1 AWD2
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_ADC1_AWD3      TIM1 ETR is connected to ADC1 AWD3
+2513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_ADC4_AWD1      TIM1 ETR is connected to ADC4 AWD1       (*)
+2514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_ADC4_AWD2      TIM1 ETR is connected to ADC4 AWD2       (*)
+2515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_ETR_ADC4_AWD3      TIM1 ETR is connected to ADC4 AWD3       (*)
+2516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM2, the parameter can take one of the following values:
+2518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETR_GPIO           TIM2 ETR is connected to GPIO
+2519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETR_COMP1          TIM2 ETR is connected to COMP1 output
+2520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETR_COMP2          TIM2 ETR is connected to COMP2 output
+2521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETR_COMP3          TIM2 ETR is connected to COMP3 output
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETR_COMP4          TIM2 ETR is connected to COMP4 output
+2523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETR_COMP5          TIM2 ETR is connected to COMP5 output    (*)
+2524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETR_COMP6          TIM2 ETR is connected to COMP6 output    (*)
+2525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETR_COMP7          TIM2 ETR is connected to COMP7 output    (*)
+2526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETR_TIM3_ETR       TIM2 ETR is connected to TIM3 ETR pin
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETR_TIM4_ETR       TIM2 ETR is connected to TIM4 ETR pin
+2528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETR_TIM5_ETR       TIM2 ETR is connected to TIM5 ETR pin    (*)
+2529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETR_LSE
+2530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM3, the parameter can take one of the following values:
+2532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_GPIO           TIM3 ETR is connected to GPIO
+2533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_COMP1          TIM3 ETR is connected to COMP1 output
+2534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_COMP2          TIM3 ETR is connected to COMP2 output
+2535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_COMP3          TIM3 ETR is connected to COMP3 output
+2536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_COMP4          TIM3 ETR is connected to COMP4 output
+2537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_COMP5          TIM3 ETR is connected to COMP5 output    (*)
+2538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_COMP6          TIM3 ETR is connected to COMP6 output    (*)
+ARM GAS  /tmp/cc9HXhVl.s 			page 46
+
+
+2539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_COMP7          TIM3 ETR is connected to COMP7 output    (*)
+2540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_TIM2_ETR       TIM3 ETR is connected to TIM2 ETR pin
+2541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_TIM4_ETR       TIM3 ETR is connected to TIM4 ETR pin
+2542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_ADC2_AWD1      TIM3 ETR is connected to ADC2 AWD1
+2543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_ADC2_AWD2      TIM3 ETR is connected to ADC2 AWD2
+2544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_ETR_ADC2_AWD3      TIM3 ETR is connected to ADC2 AWD3
+2545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM4, the parameter can take one of the following values:
+2547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_ETR_GPIO           TIM4 ETR is connected to GPIO
+2548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_ETR_COMP1          TIM4 ETR is connected to COMP1 output
+2549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_ETR_COMP2          TIM4 ETR is connected to COMP2 output
+2550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_ETR_COMP3          TIM4 ETR is connected to COMP3 output
+2551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_ETR_COMP4          TIM4 ETR is connected to COMP4 output
+2552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_ETR_COMP5          TIM4 ETR is connected to COMP5 output    (*)
+2553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_ETR_COMP6          TIM4 ETR is connected to COMP6 output    (*)
+2554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_ETR_COMP7          TIM4 ETR is connected to COMP7 output    (*)
+2555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_ETR_TIM3_ETR       TIM4 ETR is connected to TIM3 ETR pin
+2556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_ETR_TIM5_ETR       TIM4 ETR is connected to TIM5 ETR pin    (*)
+2557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM5, the parameter can take one of the following values:       (**)
+2559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_ETR_GPIO           TIM5 ETR is connected to GPIO            (*)
+2560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_ETR_COMP1          TIM5 ETR is connected to COMP1 output    (*)
+2561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_ETR_COMP2          TIM5 ETR is connected to COMP2 output    (*)
+2562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_ETR_COMP3          TIM5 ETR is connected to COMP3 output    (*)
+2563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_ETR_COMP4          TIM5 ETR is connected to COMP4 output    (*)
+2564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_ETR_COMP5          TIM5 ETR is connected to COMP5 output    (*)
+2565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_ETR_COMP6          TIM5 ETR is connected to COMP6 output    (*)
+2566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_ETR_COMP7          TIM5 ETR is connected to COMP7 output    (*)
+2567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_ETR_TIM2_ETR       TIM5 ETR is connected to TIM2 ETR pin    (*)
+2568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_ETR_TIM3_ETR       TIM5 ETR is connected to TIM3 ETR pin    (*)
+2569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM8, the parameter can take one of the following values:
+2571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_GPIO            TIM8 ETR is connected to GPIO
+2572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_COMP1           TIM8 ETR is connected to COMP1 output
+2573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_COMP2           TIM8 ETR is connected to COMP2 output
+2574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_COMP3           TIM8 ETR is connected to COMP3 output
+2575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_COMP4           TIM8 ETR is connected to COMP4 output
+2576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_COMP5           TIM8 ETR is connected to COMP5 output    (*)
+2577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_COMP6           TIM8 ETR is connected to COMP6 output    (*)
+2578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_COMP7           TIM8 ETR is connected to COMP7 output    (*)
+2579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_ADC2_AWD1       TIM8 ETR is connected to ADC2 AWD1
+2580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_ADC2_AWD2       TIM8 ETR is connected to ADC2 AWD2
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_ADC2_AWD3       TIM8 ETR is connected to ADC2 AWD3
+2582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_ADC3_AWD1       TIM8 ETR is connected to ADC3 AWD1       (*)
+2583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_ADC3_AWD2       TIM8 ETR is connected to ADC3 AWD2       (*)
+2584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_ETR_ADC3_AWD3       TIM8 ETR is connected to ADC3 AWD3       (*)
+2585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM20, the parameter can take one of the following values:       (**)
+2587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_GPIO            TIM20 ETR is connected to GPIO
+2588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_COMP1           TIM20 ETR is connected to COMP1 output  (*)
+2589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_COMP2           TIM20 ETR is connected to COMP2 output  (*)
+2590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_COMP3           TIM20 ETR is connected to COMP3 output  (*)
+2591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_COMP4           TIM20 ETR is connected to COMP4 output  (*)
+2592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_COMP5           TIM20 ETR is connected to COMP5 output  (*)
+2593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_COMP6           TIM20 ETR is connected to COMP6 output  (*)
+2594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_COMP7           TIM20 ETR is connected to COMP7 output  (*)
+2595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_ADC3_AWD1       TIM20 ETR is connected to ADC3 AWD1     (*)
+ARM GAS  /tmp/cc9HXhVl.s 			page 47
+
+
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_ADC3_AWD2       TIM20 ETR is connected to ADC3 AWD2     (*)
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_ADC3_AWD3       TIM20 ETR is connected to ADC3 AWD3     (*)
+2598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_ADC5_AWD1       TIM20 ETR is connected to ADC5 AWD1     (*)
+2599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_ADC5_AWD2       TIM20 ETR is connected to ADC5 AWD2     (*)
+2600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_ETR_ADC5_AWD3       TIM20 ETR is connected to ADC5 AWD3     (*)
+2601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         (*)  Value not defined in all devices. \n
+2603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         (**) Register not available in all devices.
+2604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+2606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+2607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+2608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+2609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check parameters */
+2610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+2611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_REMAP(Remap));
+2612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+2614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
+2616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+2620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+2621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+2623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Select the timer input source
+2624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle.
+2625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel specifies the TIM Channel
+2626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+2627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TI1 input channel
+2628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TI2 input channel
+2629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TI3 input channel
+2630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TI4 input channel
+2631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  TISelection specifies the timer input source
+2632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM1 this parameter can be one of the following values:
+2633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
+2634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
+2635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_TI1_COMP2:               TIM1 TI1 is connected to COMP2 output
+2636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_TI1_COMP3:               TIM1 TI1 is connected to COMP3 output
+2637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM1_TI1_COMP4:               TIM1 TI1 is connected to COMP4 output
+2638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM2 this parameter can be one of the following values:
+2640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI1_GPIO:                TIM2 TI1 is connected to GPIO
+2641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI1_COMP1:               TIM2 TI1 is connected to COMP1 output
+2642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI1_COMP2:               TIM2 TI1 is connected to COMP2 output
+2643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI1_COMP3:               TIM2 TI1 is connected to COMP3 output
+2644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI1_COMP4:               TIM2 TI1 is connected to COMP4 output
+2645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI1_COMP5:               TIM2 TI1 is connected to COMP5 output     (*)
+2646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI2_GPIO:                TIM1 TI2 is connected to GPIO
+2648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI2_COMP1:               TIM2 TI2 is connected to COMP1 output
+2649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI2_COMP2:               TIM2 TI2 is connected to COMP2 output
+2650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI2_COMP3:               TIM2 TI2 is connected to COMP3 output
+2651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI2_COMP4:               TIM2 TI2 is connected to COMP4 output
+2652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI2_COMP6:               TIM2 TI2 is connected to COMP6 output     (*)
+ARM GAS  /tmp/cc9HXhVl.s 			page 48
+
+
+2653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI3_GPIO:                TIM2 TI3 is connected to GPIO
+2655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI3_COMP4:               TIM2 TI3 is connected to COMP4 output
+2656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
+2658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
+2659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
+2660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM3 this parameter can be one of the following values:
+2662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
+2663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
+2664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
+2665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI1_COMP3:               TIM3 TI1 is connected to COMP3 output
+2666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI1_COMP4:               TIM3 TI1 is connected to COMP4 output
+2667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI1_COMP5:               TIM3 TI1 is connected to COMP5 output     (*)
+2668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI1_COMP6:               TIM3 TI1 is connected to COMP6 output     (*)
+2669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI1_COMP7:               TIM3 TI1 is connected to COMP7 output     (*)
+2670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI2_GPIO:                TIM3 TI2 is connected to GPIO
+2672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI2_COMP1:               TIM3 TI2 is connected to COMP1 output
+2673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI2_COMP2:               TIM3 TI2 is connected to COMP2 output
+2674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI2_COMP3:               TIM3 TI2 is connected to COMP3 output
+2675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI2_COMP4:               TIM3 TI2 is connected to COMP4 output
+2676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI2_COMP5:               TIM3 TI2 is connected to COMP5 output     (*)
+2677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI2_COMP6:               TIM3 TI2 is connected to COMP6 output     (*)
+2678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI2_COMP7:               TIM3 TI2 is connected to COMP7 output     (*)
+2679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI3_GPIO:                TIM3 TI3 is connected to GPIO
+2681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM3_TI3_COMP3:               TIM3 TI3 is connected to COMP3 output
+2682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM4 this parameter can be one of the following values:
+2684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI1_GPIO:                TIM4 TI1 is connected to GPIO
+2685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI1_COMP1:               TIM4 TI1 is connected to COMP1 output
+2686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI1_COMP2:               TIM4 TI1 is connected to COMP2 output
+2687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI1_COMP3:               TIM4 TI1 is connected to COMP3 output
+2688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI1_COMP4:               TIM4 TI1 is connected to COMP4 output
+2689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI1_COMP5:               TIM4 TI1 is connected to COMP5 output     (*)
+2690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI1_COMP6:               TIM4 TI1 is connected to COMP6 output     (*)
+2691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI1_COMP7:               TIM4 TI1 is connected to COMP7 output     (*)
+2692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI2_GPIO:                TIM4 TI2 is connected to GPIO
+2694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI2_COMP1:               TIM4 TI2 is connected to COMP1 output
+2695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI2_COMP2:               TIM4 TI2 is connected to COMP2 output
+2696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI2_COMP3:               TIM4 TI2 is connected to COMP3 output
+2697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI2_COMP4:               TIM4 TI2 is connected to COMP4 output
+2698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI2_COMP5:               TIM4 TI2 is connected to COMP5 output     (*)
+2699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI2_COMP6:               TIM4 TI2 is connected to COMP6 output     (*)
+2700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI2_COMP7:               TIM4 TI2 is connected to COMP7 output     (*)
+2701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI3_GPIO:                TIM4 TI3 is connected to GPIO
+2703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI3_COMP5:               TIM4 TI3 is connected to COMP5 output     (*)
+2704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI4_GPIO:                TIM4 TI4 is connected to GPIO
+2706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM4_TI4_COMP6:               TIM4 TI4 is connected to COMP6 output     (*)
+2707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM5 this parameter can be one of the following values:    (**)
+2709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI1_GPIO:                TIM5 TI1 is connected to GPIO
+ARM GAS  /tmp/cc9HXhVl.s 			page 49
+
+
+2710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI1_LSI:                 TIM5 TI1 is connected to LSI clock        (*)
+2711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI1_LSE:                 TIM5 TI1 is connected to LSE clock        (*)
+2712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI1_RTC_WK:              TIM5 TI1 is connected to RTC Wakeup       (*)
+2713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI1_COMP1:               TIM5 TI1 is connected to COMP1 output     (*)
+2714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI1_COMP2:               TIM5 TI1 is connected to COMP2 output     (*)
+2715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI1_COMP3:               TIM5 TI1 is connected to COMP3 output     (*)
+2716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI1_COMP4:               TIM5 TI1 is connected to COMP4 output     (*)
+2717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI1_COMP5:               TIM5 TI1 is connected to COMP5 output     (*)
+2718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI1_COMP6:               TIM5 TI1 is connected to COMP6 output     (*)
+2719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI1_COMP7:               TIM5 TI1 is connected to COMP7 output     (*)
+2720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI2_GPIO:                TIM5 TI2 is connected to GPIO
+2722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI2_COMP1:               TIM5 TI2 is connected to COMP1 output
+2723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI2_COMP2:               TIM5 TI2 is connected to COMP2 output
+2724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI2_COMP3:               TIM5 TI2 is connected to COMP3 output
+2725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI2_COMP4:               TIM5 TI2 is connected to COMP4 output
+2726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI2_COMP5:               TIM5 TI2 is connected to COMP5 output     (*)
+2727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI2_COMP6:               TIM5 TI2 is connected to COMP6 output     (*)
+2728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_TI2_COMP7:               TIM5 TI2 is connected to COMP7 output     (*)
+2729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM8 this parameter can be one of the following values:
+2731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_TI1_GPIO:                TIM8 TI1 is connected to GPIO
+2732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_TI1_COMP1:               TIM8 TI1 is connected to COMP1 output
+2733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_TI1_COMP2:               TIM8 TI1 is connected to COMP2 output
+2734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_TI1_COMP3:               TIM8 TI1 is connected to COMP3 output
+2735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM8_TI1_COMP4:               TIM8 TI1 is connected to COMP4 output
+2736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM15 this parameter can be one of the following values:
+2738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM15_TI1_GPIO:                TIM15 TI1 is connected to GPIO
+2739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM15_TI1_LSE:                 TIM15 TI1 is connected to LSE clock
+2740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM15_TI1_COMP1:               TIM15 TI1 is connected to COMP1 output
+2741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM15_TI1_COMP2:               TIM15 TI1 is connected to COMP2 output
+2742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM15_TI1_COMP5:               TIM15 TI1 is connected to COMP5 output     (
+2743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM15_TI1_COMP7:               TIM15 TI1 is connected to COMP7 output     (
+2744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM15_TI2_GPIO:                TIM15 TI2 is connected to GPIO
+2746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM15_TI2_COMP2:               TIM15 TI2 is connected to COMP2 output
+2747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM15_TI2_COMP3:               TIM15 TI2 is connected to COMP3 output
+2748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM15_TI2_COMP6:               TIM15 TI2 is connected to COMP6 output     (
+2749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM15_TI2_COMP7:               TIM15 TI2 is connected to COMP7 output     (
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM16 this parameter can be one of the following values:
+2752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM16_TI1_GPIO:                TIM16 TI1 is connected to GPIO
+2753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM16_TI1_COMP6:               TIM16 TI1 is connected to COMP6 output     (
+2754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM16_TI1_MCO:                 TIM15 TI1 is connected to MCO output
+2755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM16_TI1_HSE_32:              TIM15 TI1 is connected to HSE div 32
+2756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM16_TI1_RTC_WK:              TIM15 TI1 is connected to RTC wakeup
+2757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM16_TI1_LSE:                 TIM15 TI1 is connected to LSE clock
+2758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM16_TI1_LSI:                 TIM15 TI1 is connected to LSI clock
+2759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM17 this parameter can be one of the following values:
+2761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM17_TI1_GPIO:                TIM17 TI1 is connected to GPIO
+2762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM17_TI1_COMP5:               TIM17 TI1 is connected to COMP5 output     (
+2763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM17_TI1_MCO:                 TIM17 TI1 is connected to MCO output
+2764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM17_TI1_HSE_32:              TIM17 TI1 is connected to HSE div 32
+2765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM17_TI1_RTC_WK:              TIM17 TI1 is connected to RTC wakeup
+2766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM17_TI1_LSE:                 TIM17 TI1 is connected to LSE clock
+ARM GAS  /tmp/cc9HXhVl.s 			page 50
+
+
+2767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM17_TI1_LSI:                 TIM17 TI1 is connected to LSI clock
+2768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         For TIM20 this parameter can be one of the following values:    (**)
+2770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_TI1_GPIO:                TIM20 TI1 is connected to GPIO
+2771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_TI1_COMP1:               TIM20 TI1 is connected to COMP1 output     (
+2772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_TI1_COMP2:               TIM20 TI1 is connected to COMP2 output     (
+2773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_TI1_COMP3:               TIM20 TI1 is connected to COMP3 output     (
+2774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_TIM20_TI1_COMP4:               TIM20 TI1 is connected to COMP4 output     (
+2775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         (*)  Value not defined in all devices. \n
+2777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         (**) Register not available in all devices.
+2778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+2779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+2780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+2781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Ch
+2782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+2784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check parameters */
+2786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_TISEL_TIX_INSTANCE(htim->Instance, Channel));
+2787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_TISEL(TISelection));
+2788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (Channel)
+2792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+2793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+2794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
+2795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* If required, set OR bit to request HSE/32 clock */
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (IS_TIM_HSE32_INSTANCE(htim->Instance))
+2798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+2799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         SET_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
+2800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+2801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       else
+2802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+2803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         CLEAR_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
+2804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+2805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+2807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
+2808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+2810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
+2811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_4:
+2813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+2816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       status = HAL_ERROR;
+2817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+2819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return status;
+2823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ARM GAS  /tmp/cc9HXhVl.s 			page 51
+
+
+2824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Group channel 5 and channel 1, 2 or 3
+2827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle.
+2828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
+2829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         This parameter can be any combination of the following values:
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+2831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+2832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+2833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+2834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+2835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+2836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+2838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check parameters */
+2839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+2840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_GROUPCH5(Channels));
+2841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Process Locked */
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+2844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_BUSY;
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Clear GC5Cx bit fields */
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+2849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set GC5Cx bit fields */
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CCR5 |= Channels;
+2852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Change the htim state */
+2854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_READY;
+2855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+2859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+2860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Disarm the designated break input (when it operates in bidirectional mode).
+2863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle.
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  BreakInput Break input to disarm
+2865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+2866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_BREAKINPUT_BRK: Timer break input
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+2868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note  The break input can be disarmed only when it is configured in
+2869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        bidirectional mode and when when MOE is reset.
+2870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note  Purpose is to be able to have the input voltage back to high-state,
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *        whatever the time constant on the output .
+2872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+2873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+2874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+2877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpbdtr;
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+2880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ARM GAS  /tmp/cc9HXhVl.s 			page 52
+
+
+2881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUT(BreakInput));
+2882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (BreakInput)
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+2885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUT_BRK:
+2886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Check initial conditions */
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmpbdtr = READ_REG(htim->Instance->BDTR);
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
+2890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+2891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+2892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Break input BRK is disarmed */
+2893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
+2894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+2895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUT_BRK2:
+2899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Check initial conditions */
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmpbdtr = READ_REG(htim->Instance->BDTR);
+2902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
+2903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+2904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+2905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Break input BRK is disarmed */
+2906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
+2907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+2908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+2911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       status = HAL_ERROR;
+2912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+2914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return status;
+2916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+2917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+2919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Arm the designated break input (when it operates in bidirectional mode).
+2920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle.
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  BreakInput Break input to arm
+2922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+2923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_BREAKINPUT_BRK: Timer break input
+2924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+2925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note  Arming is possible at anytime, even if fault is present.
+2926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note  Break input is automatically armed as soon as MOE bit is set.
+2927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+2928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+2929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+2930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+2932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tickstart;
+2933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+2935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUT(BreakInput));
+2937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 53
+
+
+2938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   switch (BreakInput)
+2939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+2940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUT_BRK:
+2941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Check initial conditions */
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
+2944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+2945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condi
+2946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Init tickstart for timeout management */
+2947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         tickstart = HAL_GetTick();
+2948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+2949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         {
+2950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+2951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           {
+2952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             /* New check to avoid false timeout detection in case of preemption */
+2953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+2954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             {
+2955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****               return HAL_TIMEOUT;
+2956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             }
+2957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           }
+2958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         }
+2959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+2960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_BREAKINPUT_BRK2:
+2964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+2965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       /* Check initial conditions */
+2966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
+2967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+2968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault cond
+2969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         /* Init tickstart for timeout management */
+2970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         tickstart = HAL_GetTick();
+2971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+2972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         {
+2973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+2974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           {
+2975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             /* New check to avoid false timeout detection in case of preemption */
+2976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+2977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             {
+2978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****               return HAL_TIMEOUT;
+2979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             }
+2980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           }
+2981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         }
+2982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+2983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+2985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+2986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       status = HAL_ERROR;
+2987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+2988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+2989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return status;
+2991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+2993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+2994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Enable dithering
+ARM GAS  /tmp/cc9HXhVl.s 			page 54
+
+
+2995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+2996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   Main usage is PWM mode
+2997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   This function must be called when timer is stopped or disabled (CEN =0)
+2998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
+2999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32
+3000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b ti
+3001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b
+3002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers
+3003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *             (corresponds to 4094 for the integer part and 15 for the dithered part).
+3004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER()  __HAL_TIM_CAL
+3005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         can be used to calculate period (ARR) and delay (CCRx) value.
+3006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the sam
+3007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the sam
+3008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_A
+3009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period 
+3010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim)
+3013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+3016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
+3018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Disable dithering
+3023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   This function must be called when timer is stopped or disabled (CEN =0)
+3025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
+3026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32
+3027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b ti
+3028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b
+3029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *           - ARR and CCRx values are limited to 0xFFEF in dithering mode
+3030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *             (corresponds to 4094 for the integer part and 15 for the dithered part).
+3031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the sa
+3032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_A
+3033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period 
+3034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim)
+3037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+3040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
+3042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Initializes the pulse on compare pulse width and pulse prescaler
+3047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Output Compare handle
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  PulseWidthPrescaler  Pulse width prescaler
+3049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7
+3050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  PulseWidth  Pulse width
+3051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
+ARM GAS  /tmp/cc9HXhVl.s 			page 55
+
+
+3052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim,
+3055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                                                     uint32_t PulseWidthPrescaler,
+3056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                                                     uint32_t PulseWidth)
+3057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpecr;
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
+3062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
+3063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
+3064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Process Locked */
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+3067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the TIM state */
+3069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_BUSY;
+3070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Get the TIMx ECR register value */
+3072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   tmpecr = htim->Instance->ECR;
+3073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Reset the Pulse width prescaler and the Pulse width */
+3074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
+3075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the Pulse width prescaler and Pulse width*/
+3076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
+3077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
+3078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Write to TIMx ECR */
+3079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->ECR = tmpecr;
+3080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Change the TIM state */
+3082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_READY;
+3083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Release Lock */
+3085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+3086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
+3092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Source Source of slave mode selection preload
+3094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         This parameter can be one of the following values:
+3095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mo
+3096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode
+3097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source)
+3100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+3103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
+3104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
+3106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 56
+
+
+3109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
+3111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim)
+3115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+3118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
+3125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim)
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+3132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
+3134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Enable deadtime preload
+3139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim)
+3143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+3146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
+3148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Disable deadtime preload
+3153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim)
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+3160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
+3162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ARM GAS  /tmp/cc9HXhVl.s 			page 57
+
+
+3166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Configure deadtime
+3167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Deadtime Deadtime value
+3169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
+3170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime)
+3173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+3176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_DEADTIME(Deadtime));
+3177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
+3179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Configure asymmetrical deadtime
+3184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  FallingDeadtime Falling edge deadtime value
+3186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
+3187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDea
+3190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+3193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_DEADTIME(FallingDeadtime));
+3194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
+3196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Enable asymmetrical deadtime
+3201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
+3205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+3208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
+3210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Disable asymmetrical deadtime
+3215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
+3219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+3222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 58
+
+
+3223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
+3224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Configures the encoder index.
+3229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @note   warning in case of encoder mode clock plus direction
+3230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *                    @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUS
+3231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *         Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN
+3232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle.
+3233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  sEncoderIndexConfig Encoder index configuration
+3234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
+3237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                                                TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig
+3238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
+3242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
+3243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
+3244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
+3245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
+3246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
+3247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Process Locked */
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+3250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Configures the TIMx External Trigger (ETR) which is used as Index input */
+3252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_ETR_SetConfig(htim->Instance,
+3253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                     sEncoderIndexConfig->Prescaler,
+3254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                     sEncoderIndexConfig->Polarity,
+3255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                     sEncoderIndexConfig->Filter);
+3256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Configures the encoder index */
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(htim->Instance->ECR,
+3259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****              TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
+3260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****              (sEncoderIndexConfig->Direction |
+3261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****               ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U)
+3262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****               sEncoderIndexConfig->Position |
+3263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****               TIM_ECR_IE));
+3264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+3266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Enable encoder index
+3272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim)
+3276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 59
+
+
+3280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
+3281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Disable encoder index
+3286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim)
+3290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
+3295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Enable encoder first index
+3300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim)
+3304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
+3309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Disable encoder first index
+3314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL status
+3316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim)
+3318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
+3323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+3324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @}
+3328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+3331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief    Extended Callbacks functions
+3332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+3333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @verbatim
+3334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+3335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                     ##### Extended Callbacks functions #####
+3336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+ARM GAS  /tmp/cc9HXhVl.s 			page 60
+
+
+3337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   [..]
+3338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     This section provides Extended TIM callback functions:
+3339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Timer Commutation callback
+3340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     (+) Timer Break callback
+3341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @endverbatim
+3343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @{
+3344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Hall commutation changed callback in non-blocking mode
+3348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+3350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+3352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+3354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   UNUSED(htim);
+3355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+3357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             the HAL_TIMEx_CommutCallback could be implemented in the user file
+3358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****    */
+3359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Hall commutation changed half complete callback in non-blocking mode
+3362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+3364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+3366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+3368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   UNUSED(htim);
+3369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+3371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+3372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****    */
+3373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Hall Break detection callback in non-blocking mode
+3377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+3383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   UNUSED(htim);
+3384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             the HAL_TIMEx_BreakCallback could be implemented in the user file
+3387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****    */
+3388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Hall Break2 detection callback in non blocking mode
+3392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim: TIM handle
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+ARM GAS  /tmp/cc9HXhVl.s 			page 61
+
+
+3394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+3398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   UNUSED(htim);
+3399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+3401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             the HAL_TIMEx_Break2Callback could be implemented in the user file
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****    */
+3403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Encoder index callback in non-blocking mode
+3407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
+3411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+3413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   UNUSED(htim);
+3414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+3416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
+3417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****    */
+3418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Direction change callback in non-blocking mode
+3422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+3424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
+3426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+3428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   UNUSED(htim);
+3429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+3431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
+3432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****    */
+3433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Index error callback in non-blocking mode
+3437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+3439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
+3441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+3443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   UNUSED(htim);
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+3446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
+3447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****    */
+3448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ARM GAS  /tmp/cc9HXhVl.s 			page 62
+
+
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Transition error callback in non-blocking mode
+3452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+3454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
+3456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+3458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   UNUSED(htim);
+3459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+3461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
+3462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****    */
+3463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @}
+3467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+3470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief    Extended Peripheral State functions
+3471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *
+3472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @verbatim
+3473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+3474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                 ##### Extended Peripheral State functions #####
+3475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   ==============================================================================
+3476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   [..]
+3477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     This subsection permits to get in run-time the status of the peripheral
+3478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     and the data flow.
+3479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** @endverbatim
+3481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @{
+3482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Return the TIM Hall Sensor interface handle state.
+3486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor handle
+3487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval HAL state
+3488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+3490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return htim->State;
+3492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Return actual state of the TIM complementary channel.
+3496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  htim TIM handle
+3497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  ChannelN TIM Complementary channel
+3498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+3499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1
+3500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2
+3501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3
+3502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4
+3503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval TIM Complementary channel state
+3504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN)
+3506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_state;
+ARM GAS  /tmp/cc9HXhVl.s 			page 63
+
+
+3508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+3510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+3511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+3513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return channel_state;
+3515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @}
+3518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @}
+3522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /* Private functions ---------------------------------------------------------*/
+3525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+3526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @{
+3527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  TIM DMA Commutation callback.
+3531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  hdma pointer to DMA handle.
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+3533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+3535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+3537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Change the htim state */
+3539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_READY;
+3540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->CommutationCallback(htim);
+3543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #else
+3544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIMEx_CommutCallback(htim);
+3545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  TIM DMA Commutation half complete callback.
+3550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  hdma pointer to DMA handle.
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+3552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+3554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+3556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Change the htim state */
+3558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_READY;
+3559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->CommutationHalfCpltCallback(htim);
+3562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #else
+3563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIMEx_CommutHalfCpltCallback(htim);
+3564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ARM GAS  /tmp/cc9HXhVl.s 			page 64
+
+
+3565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  TIM DMA Delay Pulse complete callback (complementary channel).
+3570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  hdma pointer to DMA handle.
+3571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+3572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
+3574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+3576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+3578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+3579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+3580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+3582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+3583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+3585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+3586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+3587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+3588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+3589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+3592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+3594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+3595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+3596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+3597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+3598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+3600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+3601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+3602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+3603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+3604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+3605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+3606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+3607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+3609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+3610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+3611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+3612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+3613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else
+3614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+3615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* nothing to do */
+3616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->PWM_PulseFinishedCallback(htim);
+3620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #else
+3621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_PWM_PulseFinishedCallback(htim);
+ARM GAS  /tmp/cc9HXhVl.s 			page 65
+
+
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+3625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  TIM DMA error callback (complementary channel)
+3629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  hdma pointer to DMA handle.
+3630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+3631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+3633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+3634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+3635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+3637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+3639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+3641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+3642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+3643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+3644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+3646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+3647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+3648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+3649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+3650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+3651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   else
+3652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+3653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* nothing to do */
+3654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+3655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->ErrorCallback(htim);
+3658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #else
+3659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ErrorCallback(htim);
+3660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+3663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+3664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+3666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @brief  Enables or disables the TIM Capture Compare Channel xN.
+3667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  TIMx to select the TIM peripheral
+3668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  Channel specifies the TIM Channel
+3669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2
+3672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3
+3673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4
+3674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+3676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   * @retval None
+3677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   */
+3678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+ARM GAS  /tmp/cc9HXhVl.s 			page 66
+
+
+3679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** {
+  29              		.loc 1 3679 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+3680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmp;
+  34              		.loc 1 3680 3 view .LVU1
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+  35              		.loc 1 3682 3 view .LVU2
+  36              		.loc 1 3682 36 is_stmt 0 view .LVU3
+  37 0000 01F01F01 		and	r1, r1, #31
+  38              	.LVL1:
+  39              		.loc 1 3682 7 view .LVU4
+  40 0004 4FF0040C 		mov	ip, #4
+  41 0008 0CFA01FC 		lsl	ip, ip, r1
+  42              	.LVL2:
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Reset the CCxNE Bit */
+3685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIMx->CCER &=  ~tmp;
+  43              		.loc 1 3685 3 is_stmt 1 view .LVU5
+  44              		.loc 1 3685 7 is_stmt 0 view .LVU6
+  45 000c 036A     		ldr	r3, [r0, #32]
+  46              		.loc 1 3685 14 view .LVU7
+  47 000e 23EA0C03 		bic	r3, r3, ip
+  48 0012 0362     		str	r3, [r0, #32]
+3686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+3687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set or reset the CCxNE Bit */
+3688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+  49              		.loc 1 3688 3 is_stmt 1 view .LVU8
+  50              		.loc 1 3688 7 is_stmt 0 view .LVU9
+  51 0014 036A     		ldr	r3, [r0, #32]
+  52              		.loc 1 3688 42 view .LVU10
+  53 0016 8A40     		lsls	r2, r2, r1
+  54              	.LVL3:
+  55              		.loc 1 3688 14 view .LVU11
+  56 0018 1343     		orrs	r3, r3, r2
+  57 001a 0362     		str	r3, [r0, #32]
+3689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+  58              		.loc 1 3689 1 view .LVU12
+  59 001c 7047     		bx	lr
+  60              		.cfi_endproc
+  61              	.LFE397:
+  63              		.section	.text.TIM_DMAErrorCCxN,"ax",%progbits
+  64              		.align	1
+  65              		.syntax unified
+  66              		.thumb
+  67              		.thumb_func
+  69              	TIM_DMAErrorCCxN:
+  70              	.LVL4:
+  71              	.LFB396:
+3633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  72              		.loc 1 3633 1 is_stmt 1 view -0
+  73              		.cfi_startproc
+  74              		@ args = 0, pretend = 0, frame = 0
+  75              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cc9HXhVl.s 			page 67
+
+
+3633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  76              		.loc 1 3633 1 is_stmt 0 view .LVU14
+  77 0000 10B5     		push	{r4, lr}
+  78              	.LCFI0:
+  79              		.cfi_def_cfa_offset 8
+  80              		.cfi_offset 4, -8
+  81              		.cfi_offset 14, -4
+3634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+  82              		.loc 1 3634 3 is_stmt 1 view .LVU15
+3634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+  83              		.loc 1 3634 22 is_stmt 0 view .LVU16
+  84 0002 846A     		ldr	r4, [r0, #40]
+  85              	.LVL5:
+3636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+  86              		.loc 1 3636 3 is_stmt 1 view .LVU17
+3636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+  87              		.loc 1 3636 25 is_stmt 0 view .LVU18
+  88 0004 636A     		ldr	r3, [r4, #36]
+3636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+  89              		.loc 1 3636 6 view .LVU19
+  90 0006 8342     		cmp	r3, r0
+  91 0008 0BD0     		beq	.L7
+3641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+  92              		.loc 1 3641 8 is_stmt 1 view .LVU20
+3641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+  93              		.loc 1 3641 30 is_stmt 0 view .LVU21
+  94 000a A36A     		ldr	r3, [r4, #40]
+3641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+  95              		.loc 1 3641 11 view .LVU22
+  96 000c 8342     		cmp	r3, r0
+  97 000e 0DD0     		beq	.L8
+3646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+  98              		.loc 1 3646 8 is_stmt 1 view .LVU23
+3646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+  99              		.loc 1 3646 30 is_stmt 0 view .LVU24
+ 100 0010 E36A     		ldr	r3, [r4, #44]
+3646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 101              		.loc 1 3646 11 view .LVU25
+ 102 0012 8342     		cmp	r3, r0
+ 103 0014 10D0     		beq	.L9
+ 104              	.L4:
+3654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 105              		.loc 1 3654 3 is_stmt 1 view .LVU26
+3659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 106              		.loc 1 3659 3 view .LVU27
+ 107 0016 2046     		mov	r0, r4
+ 108              	.LVL6:
+3659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 109              		.loc 1 3659 3 is_stmt 0 view .LVU28
+ 110 0018 FFF7FEFF 		bl	HAL_TIM_ErrorCallback
+ 111              	.LVL7:
+3662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 112              		.loc 1 3662 3 is_stmt 1 view .LVU29
+3662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 113              		.loc 1 3662 17 is_stmt 0 view .LVU30
+ 114 001c 0023     		movs	r3, #0
+ 115 001e 2377     		strb	r3, [r4, #28]
+ARM GAS  /tmp/cc9HXhVl.s 			page 68
+
+
+3663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 116              		.loc 1 3663 1 view .LVU31
+ 117 0020 10BD     		pop	{r4, pc}
+ 118              	.LVL8:
+ 119              	.L7:
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 120              		.loc 1 3638 5 is_stmt 1 view .LVU32
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 121              		.loc 1 3638 19 is_stmt 0 view .LVU33
+ 122 0022 0123     		movs	r3, #1
+ 123 0024 2377     		strb	r3, [r4, #28]
+3639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 124              		.loc 1 3639 5 is_stmt 1 view .LVU34
+ 125 0026 84F84430 		strb	r3, [r4, #68]
+ 126 002a F4E7     		b	.L4
+ 127              	.L8:
+3643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 128              		.loc 1 3643 5 view .LVU35
+3643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 129              		.loc 1 3643 19 is_stmt 0 view .LVU36
+ 130 002c 0223     		movs	r3, #2
+ 131 002e 2377     		strb	r3, [r4, #28]
+3644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 132              		.loc 1 3644 5 is_stmt 1 view .LVU37
+ 133 0030 0123     		movs	r3, #1
+ 134 0032 84F84530 		strb	r3, [r4, #69]
+ 135 0036 EEE7     		b	.L4
+ 136              	.L9:
+3648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ 137              		.loc 1 3648 5 view .LVU38
+3648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ 138              		.loc 1 3648 19 is_stmt 0 view .LVU39
+ 139 0038 0423     		movs	r3, #4
+ 140 003a 2377     		strb	r3, [r4, #28]
+3649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 141              		.loc 1 3649 5 is_stmt 1 view .LVU40
+ 142 003c 0123     		movs	r3, #1
+ 143 003e 84F84630 		strb	r3, [r4, #70]
+ 144 0042 E8E7     		b	.L4
+ 145              		.cfi_endproc
+ 146              	.LFE396:
+ 148              		.section	.text.TIM_DMADelayPulseNCplt,"ax",%progbits
+ 149              		.align	1
+ 150              		.syntax unified
+ 151              		.thumb
+ 152              		.thumb_func
+ 154              	TIM_DMADelayPulseNCplt:
+ 155              	.LVL9:
+ 156              	.LFB395:
+3574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 157              		.loc 1 3574 1 view -0
+ 158              		.cfi_startproc
+ 159              		@ args = 0, pretend = 0, frame = 0
+ 160              		@ frame_needed = 0, uses_anonymous_args = 0
+3574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 161              		.loc 1 3574 1 is_stmt 0 view .LVU42
+ 162 0000 10B5     		push	{r4, lr}
+ARM GAS  /tmp/cc9HXhVl.s 			page 69
+
+
+ 163              	.LCFI1:
+ 164              		.cfi_def_cfa_offset 8
+ 165              		.cfi_offset 4, -8
+ 166              		.cfi_offset 14, -4
+3575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 167              		.loc 1 3575 3 is_stmt 1 view .LVU43
+3575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 168              		.loc 1 3575 22 is_stmt 0 view .LVU44
+ 169 0002 846A     		ldr	r4, [r0, #40]
+ 170              	.LVL10:
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 171              		.loc 1 3577 3 is_stmt 1 view .LVU45
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 172              		.loc 1 3577 25 is_stmt 0 view .LVU46
+ 173 0004 636A     		ldr	r3, [r4, #36]
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 174              		.loc 1 3577 6 view .LVU47
+ 175 0006 8342     		cmp	r3, r0
+ 176 0008 0ED0     		beq	.L16
+3586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 177              		.loc 1 3586 8 is_stmt 1 view .LVU48
+3586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 178              		.loc 1 3586 30 is_stmt 0 view .LVU49
+ 179 000a A36A     		ldr	r3, [r4, #40]
+3586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 180              		.loc 1 3586 11 view .LVU50
+ 181 000c 8342     		cmp	r3, r0
+ 182 000e 14D0     		beq	.L17
+3595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 183              		.loc 1 3595 8 is_stmt 1 view .LVU51
+3595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 184              		.loc 1 3595 30 is_stmt 0 view .LVU52
+ 185 0010 E36A     		ldr	r3, [r4, #44]
+3595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 186              		.loc 1 3595 11 view .LVU53
+ 187 0012 8342     		cmp	r3, r0
+ 188 0014 1AD0     		beq	.L18
+3604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 189              		.loc 1 3604 8 is_stmt 1 view .LVU54
+3604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 190              		.loc 1 3604 30 is_stmt 0 view .LVU55
+ 191 0016 236B     		ldr	r3, [r4, #48]
+3604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 192              		.loc 1 3604 11 view .LVU56
+ 193 0018 8342     		cmp	r3, r0
+ 194 001a 20D0     		beq	.L19
+ 195              	.L12:
+3616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 196              		.loc 1 3616 3 is_stmt 1 view .LVU57
+3621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 197              		.loc 1 3621 3 view .LVU58
+ 198 001c 2046     		mov	r0, r4
+ 199              	.LVL11:
+3621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 200              		.loc 1 3621 3 is_stmt 0 view .LVU59
+ 201 001e FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedCallback
+ 202              	.LVL12:
+ARM GAS  /tmp/cc9HXhVl.s 			page 70
+
+
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 203              		.loc 1 3624 3 is_stmt 1 view .LVU60
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 204              		.loc 1 3624 17 is_stmt 0 view .LVU61
+ 205 0022 0023     		movs	r3, #0
+ 206 0024 2377     		strb	r3, [r4, #28]
+3625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 207              		.loc 1 3625 1 view .LVU62
+ 208 0026 10BD     		pop	{r4, pc}
+ 209              	.LVL13:
+ 210              	.L16:
+3579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 211              		.loc 1 3579 5 is_stmt 1 view .LVU63
+3579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 212              		.loc 1 3579 19 is_stmt 0 view .LVU64
+ 213 0028 0123     		movs	r3, #1
+ 214 002a 2377     		strb	r3, [r4, #28]
+3581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 215              		.loc 1 3581 5 is_stmt 1 view .LVU65
+3581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 216              		.loc 1 3581 19 is_stmt 0 view .LVU66
+ 217 002c C369     		ldr	r3, [r0, #28]
+3581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 218              		.loc 1 3581 8 view .LVU67
+ 219 002e 002B     		cmp	r3, #0
+ 220 0030 F4D1     		bne	.L12
+3583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 221              		.loc 1 3583 7 is_stmt 1 view .LVU68
+ 222 0032 0123     		movs	r3, #1
+ 223 0034 84F84430 		strb	r3, [r4, #68]
+ 224 0038 F0E7     		b	.L12
+ 225              	.L17:
+3588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 226              		.loc 1 3588 5 view .LVU69
+3588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 227              		.loc 1 3588 19 is_stmt 0 view .LVU70
+ 228 003a 0223     		movs	r3, #2
+ 229 003c 2377     		strb	r3, [r4, #28]
+3590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 230              		.loc 1 3590 5 is_stmt 1 view .LVU71
+3590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 231              		.loc 1 3590 19 is_stmt 0 view .LVU72
+ 232 003e C369     		ldr	r3, [r0, #28]
+3590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 233              		.loc 1 3590 8 view .LVU73
+ 234 0040 002B     		cmp	r3, #0
+ 235 0042 EBD1     		bne	.L12
+3592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 236              		.loc 1 3592 7 is_stmt 1 view .LVU74
+ 237 0044 0123     		movs	r3, #1
+ 238 0046 84F84530 		strb	r3, [r4, #69]
+ 239 004a E7E7     		b	.L12
+ 240              	.L18:
+3597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 241              		.loc 1 3597 5 view .LVU75
+3597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 242              		.loc 1 3597 19 is_stmt 0 view .LVU76
+ARM GAS  /tmp/cc9HXhVl.s 			page 71
+
+
+ 243 004c 0423     		movs	r3, #4
+ 244 004e 2377     		strb	r3, [r4, #28]
+3599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 245              		.loc 1 3599 5 is_stmt 1 view .LVU77
+3599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 246              		.loc 1 3599 19 is_stmt 0 view .LVU78
+ 247 0050 C369     		ldr	r3, [r0, #28]
+3599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 248              		.loc 1 3599 8 view .LVU79
+ 249 0052 002B     		cmp	r3, #0
+ 250 0054 E2D1     		bne	.L12
+3601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 251              		.loc 1 3601 7 is_stmt 1 view .LVU80
+ 252 0056 0123     		movs	r3, #1
+ 253 0058 84F84630 		strb	r3, [r4, #70]
+ 254 005c DEE7     		b	.L12
+ 255              	.L19:
+3606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 256              		.loc 1 3606 5 view .LVU81
+3606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 257              		.loc 1 3606 19 is_stmt 0 view .LVU82
+ 258 005e 0823     		movs	r3, #8
+ 259 0060 2377     		strb	r3, [r4, #28]
+3608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 260              		.loc 1 3608 5 is_stmt 1 view .LVU83
+3608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 261              		.loc 1 3608 19 is_stmt 0 view .LVU84
+ 262 0062 C369     		ldr	r3, [r0, #28]
+3608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 263              		.loc 1 3608 8 view .LVU85
+ 264 0064 002B     		cmp	r3, #0
+ 265 0066 D9D1     		bne	.L12
+3610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 266              		.loc 1 3610 7 is_stmt 1 view .LVU86
+ 267 0068 0123     		movs	r3, #1
+ 268 006a 84F84730 		strb	r3, [r4, #71]
+ 269 006e D5E7     		b	.L12
+ 270              		.cfi_endproc
+ 271              	.LFE395:
+ 273              		.section	.text.HAL_TIMEx_HallSensor_MspInit,"ax",%progbits
+ 274              		.align	1
+ 275              		.weak	HAL_TIMEx_HallSensor_MspInit
+ 276              		.syntax unified
+ 277              		.thumb
+ 278              		.thumb_func
+ 280              	HAL_TIMEx_HallSensor_MspInit:
+ 281              	.LVL14:
+ 282              	.LFB331:
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 283              		.loc 1 304 1 view -0
+ 284              		.cfi_startproc
+ 285              		@ args = 0, pretend = 0, frame = 0
+ 286              		@ frame_needed = 0, uses_anonymous_args = 0
+ 287              		@ link register save eliminated.
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 288              		.loc 1 306 3 view .LVU88
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 72
+
+
+ 289              		.loc 1 311 1 is_stmt 0 view .LVU89
+ 290 0000 7047     		bx	lr
+ 291              		.cfi_endproc
+ 292              	.LFE331:
+ 294              		.section	.text.HAL_TIMEx_HallSensor_Init,"ax",%progbits
+ 295              		.align	1
+ 296              		.global	HAL_TIMEx_HallSensor_Init
+ 297              		.syntax unified
+ 298              		.thumb
+ 299              		.thumb_func
+ 301              	HAL_TIMEx_HallSensor_Init:
+ 302              	.LVL15:
+ 303              	.LFB329:
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_OC_InitTypeDef OC_Config;
+ 304              		.loc 1 158 1 is_stmt 1 view -0
+ 305              		.cfi_startproc
+ 306              		@ args = 0, pretend = 0, frame = 32
+ 307              		@ frame_needed = 0, uses_anonymous_args = 0
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 308              		.loc 1 159 3 view .LVU91
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 309              		.loc 1 162 3 view .LVU92
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 310              		.loc 1 162 6 is_stmt 0 view .LVU93
+ 311 0000 0028     		cmp	r0, #0
+ 312 0002 6BD0     		beq	.L24
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_OC_InitTypeDef OC_Config;
+ 313              		.loc 1 158 1 view .LVU94
+ 314 0004 70B5     		push	{r4, r5, r6, lr}
+ 315              	.LCFI2:
+ 316              		.cfi_def_cfa_offset 16
+ 317              		.cfi_offset 4, -16
+ 318              		.cfi_offset 5, -12
+ 319              		.cfi_offset 6, -8
+ 320              		.cfi_offset 14, -4
+ 321 0006 88B0     		sub	sp, sp, #32
+ 322              	.LCFI3:
+ 323              		.cfi_def_cfa_offset 48
+ 324 0008 0E46     		mov	r6, r1
+ 325 000a 0446     		mov	r4, r0
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 326              		.loc 1 168 3 is_stmt 1 view .LVU95
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 327              		.loc 1 169 3 view .LVU96
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 328              		.loc 1 170 3 view .LVU97
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ 329              		.loc 1 171 3 view .LVU98
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ 330              		.loc 1 172 3 view .LVU99
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ 331              		.loc 1 173 3 view .LVU100
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 332              		.loc 1 174 3 view .LVU101
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 333              		.loc 1 176 3 view .LVU102
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc9HXhVl.s 			page 73
+
+
+ 334              		.loc 1 176 11 is_stmt 0 view .LVU103
+ 335 000c 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 336              		.loc 1 176 6 view .LVU104
+ 337 0010 002B     		cmp	r3, #0
+ 338 0012 5ED0     		beq	.L29
+ 339              	.LVL16:
+ 340              	.L23:
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 341              		.loc 1 198 3 is_stmt 1 view .LVU105
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 342              		.loc 1 198 15 is_stmt 0 view .LVU106
+ 343 0014 0223     		movs	r3, #2
+ 344 0016 84F83D30 		strb	r3, [r4, #61]
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 345              		.loc 1 201 3 is_stmt 1 view .LVU107
+ 346 001a 2146     		mov	r1, r4
+ 347 001c 51F8040B 		ldr	r0, [r1], #4
+ 348 0020 FFF7FEFF 		bl	TIM_Base_SetConfig
+ 349              	.LVL17:
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 350              		.loc 1 204 3 view .LVU108
+ 351 0024 B368     		ldr	r3, [r6, #8]
+ 352 0026 0322     		movs	r2, #3
+ 353 0028 3168     		ldr	r1, [r6]
+ 354 002a 2068     		ldr	r0, [r4]
+ 355 002c FFF7FEFF 		bl	TIM_TI1_SetConfig
+ 356              	.LVL18:
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the IC1PSC value */
+ 357              		.loc 1 207 3 view .LVU109
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the IC1PSC value */
+ 358              		.loc 1 207 7 is_stmt 0 view .LVU110
+ 359 0030 2268     		ldr	r2, [r4]
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the IC1PSC value */
+ 360              		.loc 1 207 17 view .LVU111
+ 361 0032 9369     		ldr	r3, [r2, #24]
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the IC1PSC value */
+ 362              		.loc 1 207 25 view .LVU112
+ 363 0034 23F00C03 		bic	r3, r3, #12
+ 364 0038 9361     		str	r3, [r2, #24]
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 365              		.loc 1 209 3 is_stmt 1 view .LVU113
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 366              		.loc 1 209 7 is_stmt 0 view .LVU114
+ 367 003a 2268     		ldr	r2, [r4]
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 368              		.loc 1 209 17 view .LVU115
+ 369 003c 9369     		ldr	r3, [r2, #24]
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 370              		.loc 1 209 35 view .LVU116
+ 371 003e 7168     		ldr	r1, [r6, #4]
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 372              		.loc 1 209 25 view .LVU117
+ 373 0040 0B43     		orrs	r3, r3, r1
+ 374 0042 9361     		str	r3, [r2, #24]
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 375              		.loc 1 212 3 is_stmt 1 view .LVU118
+ARM GAS  /tmp/cc9HXhVl.s 			page 74
+
+
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 376              		.loc 1 212 7 is_stmt 0 view .LVU119
+ 377 0044 2268     		ldr	r2, [r4]
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 378              		.loc 1 212 17 view .LVU120
+ 379 0046 5368     		ldr	r3, [r2, #4]
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 380              		.loc 1 212 23 view .LVU121
+ 381 0048 43F08003 		orr	r3, r3, #128
+ 382 004c 5360     		str	r3, [r2, #4]
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+ 383              		.loc 1 215 3 is_stmt 1 view .LVU122
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+ 384              		.loc 1 215 7 is_stmt 0 view .LVU123
+ 385 004e 2268     		ldr	r2, [r4]
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+ 386              		.loc 1 215 17 view .LVU124
+ 387 0050 9368     		ldr	r3, [r2, #8]
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+ 388              		.loc 1 215 24 view .LVU125
+ 389 0052 23F44013 		bic	r3, r3, #3145728
+ 390 0056 23F07003 		bic	r3, r3, #112
+ 391 005a 9360     		str	r3, [r2, #8]
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 392              		.loc 1 216 3 is_stmt 1 view .LVU126
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 393              		.loc 1 216 7 is_stmt 0 view .LVU127
+ 394 005c 2268     		ldr	r2, [r4]
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 395              		.loc 1 216 17 view .LVU128
+ 396 005e 9368     		ldr	r3, [r2, #8]
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 397              		.loc 1 216 24 view .LVU129
+ 398 0060 43F04003 		orr	r3, r3, #64
+ 399 0064 9360     		str	r3, [r2, #8]
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+ 400              		.loc 1 219 3 is_stmt 1 view .LVU130
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+ 401              		.loc 1 219 7 is_stmt 0 view .LVU131
+ 402 0066 2268     		ldr	r2, [r4]
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+ 403              		.loc 1 219 17 view .LVU132
+ 404 0068 9368     		ldr	r3, [r2, #8]
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+ 405              		.loc 1 219 24 view .LVU133
+ 406 006a 23F48033 		bic	r3, r3, #65536
+ 407 006e 23F00703 		bic	r3, r3, #7
+ 408 0072 9360     		str	r3, [r2, #8]
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 409              		.loc 1 220 3 is_stmt 1 view .LVU134
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 410              		.loc 1 220 7 is_stmt 0 view .LVU135
+ 411 0074 2268     		ldr	r2, [r4]
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 412              		.loc 1 220 17 view .LVU136
+ 413 0076 9368     		ldr	r3, [r2, #8]
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 75
+
+
+ 414              		.loc 1 220 24 view .LVU137
+ 415 0078 43F00403 		orr	r3, r3, #4
+ 416 007c 9360     		str	r3, [r2, #8]
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ 417              		.loc 1 223 3 is_stmt 1 view .LVU138
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ 418              		.loc 1 223 24 is_stmt 0 view .LVU139
+ 419 007e 0025     		movs	r5, #0
+ 420 0080 0595     		str	r5, [sp, #20]
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCMode = TIM_OCMODE_PWM2;
+ 421              		.loc 1 224 3 is_stmt 1 view .LVU140
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCMode = TIM_OCMODE_PWM2;
+ 422              		.loc 1 224 25 is_stmt 0 view .LVU141
+ 423 0082 0695     		str	r5, [sp, #24]
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ 424              		.loc 1 225 3 is_stmt 1 view .LVU142
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ 425              		.loc 1 225 20 is_stmt 0 view .LVU143
+ 426 0084 7023     		movs	r3, #112
+ 427 0086 0193     		str	r3, [sp, #4]
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ 428              		.loc 1 226 3 is_stmt 1 view .LVU144
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ 429              		.loc 1 226 26 is_stmt 0 view .LVU145
+ 430 0088 0795     		str	r5, [sp, #28]
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 431              		.loc 1 227 3 is_stmt 1 view .LVU146
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 432              		.loc 1 227 25 is_stmt 0 view .LVU147
+ 433 008a 0495     		str	r5, [sp, #16]
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.Pulse = sConfig->Commutation_Delay;
+ 434              		.loc 1 228 3 is_stmt 1 view .LVU148
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   OC_Config.Pulse = sConfig->Commutation_Delay;
+ 435              		.loc 1 228 24 is_stmt 0 view .LVU149
+ 436 008c 0395     		str	r5, [sp, #12]
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 437              		.loc 1 229 3 is_stmt 1 view .LVU150
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 438              		.loc 1 229 28 is_stmt 0 view .LVU151
+ 439 008e F368     		ldr	r3, [r6, #12]
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 440              		.loc 1 229 19 view .LVU152
+ 441 0090 0293     		str	r3, [sp, #8]
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 442              		.loc 1 231 3 is_stmt 1 view .LVU153
+ 443 0092 01A9     		add	r1, sp, #4
+ 444 0094 2068     		ldr	r0, [r4]
+ 445 0096 FFF7FEFF 		bl	TIM_OC2_SetConfig
+ 446              	.LVL19:
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ 447              		.loc 1 235 3 view .LVU154
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ 448              		.loc 1 235 7 is_stmt 0 view .LVU155
+ 449 009a 2268     		ldr	r2, [r4]
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ 450              		.loc 1 235 17 view .LVU156
+ 451 009c 5368     		ldr	r3, [r2, #4]
+ARM GAS  /tmp/cc9HXhVl.s 			page 76
+
+
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ 452              		.loc 1 235 23 view .LVU157
+ 453 009e 23F00073 		bic	r3, r3, #33554432
+ 454 00a2 23F07003 		bic	r3, r3, #112
+ 455 00a6 5360     		str	r3, [r2, #4]
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 456              		.loc 1 236 3 is_stmt 1 view .LVU158
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 457              		.loc 1 236 7 is_stmt 0 view .LVU159
+ 458 00a8 2268     		ldr	r2, [r4]
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 459              		.loc 1 236 17 view .LVU160
+ 460 00aa 5368     		ldr	r3, [r2, #4]
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 461              		.loc 1 236 23 view .LVU161
+ 462 00ac 43F05003 		orr	r3, r3, #80
+ 463 00b0 5360     		str	r3, [r2, #4]
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 464              		.loc 1 239 3 is_stmt 1 view .LVU162
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 465              		.loc 1 239 23 is_stmt 0 view .LVU163
+ 466 00b2 0123     		movs	r3, #1
+ 467 00b4 84F84830 		strb	r3, [r4, #72]
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 468              		.loc 1 242 3 is_stmt 1 view .LVU164
+ 469 00b8 84F83E30 		strb	r3, [r4, #62]
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 470              		.loc 1 243 3 view .LVU165
+ 471 00bc 84F83F30 		strb	r3, [r4, #63]
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 472              		.loc 1 244 3 view .LVU166
+ 473 00c0 84F84430 		strb	r3, [r4, #68]
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 474              		.loc 1 245 3 view .LVU167
+ 475 00c4 84F84530 		strb	r3, [r4, #69]
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 476              		.loc 1 248 3 view .LVU168
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 477              		.loc 1 248 15 is_stmt 0 view .LVU169
+ 478 00c8 84F83D30 		strb	r3, [r4, #61]
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 479              		.loc 1 250 3 is_stmt 1 view .LVU170
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 480              		.loc 1 250 10 is_stmt 0 view .LVU171
+ 481 00cc 2846     		mov	r0, r5
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 482              		.loc 1 251 1 view .LVU172
+ 483 00ce 08B0     		add	sp, sp, #32
+ 484              	.LCFI4:
+ 485              		.cfi_remember_state
+ 486              		.cfi_def_cfa_offset 16
+ 487              		@ sp needed
+ 488 00d0 70BD     		pop	{r4, r5, r6, pc}
+ 489              	.LVL20:
+ 490              	.L29:
+ 491              	.LCFI5:
+ 492              		.cfi_restore_state
+ARM GAS  /tmp/cc9HXhVl.s 			page 77
+
+
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 493              		.loc 1 179 5 is_stmt 1 view .LVU173
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 494              		.loc 1 179 16 is_stmt 0 view .LVU174
+ 495 00d2 80F83C30 		strb	r3, [r0, #60]
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 496              		.loc 1 193 5 is_stmt 1 view .LVU175
+ 497 00d6 FFF7FEFF 		bl	HAL_TIMEx_HallSensor_MspInit
+ 498              	.LVL21:
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 499              		.loc 1 193 5 is_stmt 0 view .LVU176
+ 500 00da 9BE7     		b	.L23
+ 501              	.LVL22:
+ 502              	.L24:
+ 503              	.LCFI6:
+ 504              		.cfi_def_cfa_offset 0
+ 505              		.cfi_restore 4
+ 506              		.cfi_restore 5
+ 507              		.cfi_restore 6
+ 508              		.cfi_restore 14
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 509              		.loc 1 164 12 view .LVU177
+ 510 00dc 0120     		movs	r0, #1
+ 511              	.LVL23:
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 512              		.loc 1 251 1 view .LVU178
+ 513 00de 7047     		bx	lr
+ 514              		.cfi_endproc
+ 515              	.LFE329:
+ 517              		.section	.text.HAL_TIMEx_HallSensor_MspDeInit,"ax",%progbits
+ 518              		.align	1
+ 519              		.weak	HAL_TIMEx_HallSensor_MspDeInit
+ 520              		.syntax unified
+ 521              		.thumb
+ 522              		.thumb_func
+ 524              	HAL_TIMEx_HallSensor_MspDeInit:
+ 525              	.LVL24:
+ 526              	.LFB332:
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 527              		.loc 1 319 1 is_stmt 1 view -0
+ 528              		.cfi_startproc
+ 529              		@ args = 0, pretend = 0, frame = 0
+ 530              		@ frame_needed = 0, uses_anonymous_args = 0
+ 531              		@ link register save eliminated.
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 532              		.loc 1 321 3 view .LVU180
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 533              		.loc 1 326 1 is_stmt 0 view .LVU181
+ 534 0000 7047     		bx	lr
+ 535              		.cfi_endproc
+ 536              	.LFE332:
+ 538              		.section	.text.HAL_TIMEx_HallSensor_DeInit,"ax",%progbits
+ 539              		.align	1
+ 540              		.global	HAL_TIMEx_HallSensor_DeInit
+ 541              		.syntax unified
+ 542              		.thumb
+ 543              		.thumb_func
+ARM GAS  /tmp/cc9HXhVl.s 			page 78
+
+
+ 545              	HAL_TIMEx_HallSensor_DeInit:
+ 546              	.LVL25:
+ 547              	.LFB330:
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 548              		.loc 1 259 1 is_stmt 1 view -0
+ 549              		.cfi_startproc
+ 550              		@ args = 0, pretend = 0, frame = 0
+ 551              		@ frame_needed = 0, uses_anonymous_args = 0
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 552              		.loc 1 259 1 is_stmt 0 view .LVU183
+ 553 0000 10B5     		push	{r4, lr}
+ 554              	.LCFI7:
+ 555              		.cfi_def_cfa_offset 8
+ 556              		.cfi_offset 4, -8
+ 557              		.cfi_offset 14, -4
+ 558 0002 0446     		mov	r4, r0
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 559              		.loc 1 261 3 is_stmt 1 view .LVU184
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 560              		.loc 1 263 3 view .LVU185
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 561              		.loc 1 263 15 is_stmt 0 view .LVU186
+ 562 0004 0223     		movs	r3, #2
+ 563 0006 80F83D30 		strb	r3, [r0, #61]
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 564              		.loc 1 266 3 is_stmt 1 view .LVU187
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 565              		.loc 1 266 3 view .LVU188
+ 566 000a 0368     		ldr	r3, [r0]
+ 567 000c 196A     		ldr	r1, [r3, #32]
+ 568 000e 41F21112 		movw	r2, #4369
+ 569 0012 1142     		tst	r1, r2
+ 570 0014 08D1     		bne	.L32
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 571              		.loc 1 266 3 discriminator 1 view .LVU189
+ 572 0016 196A     		ldr	r1, [r3, #32]
+ 573 0018 44F24442 		movw	r2, #17476
+ 574 001c 1142     		tst	r1, r2
+ 575 001e 03D1     		bne	.L32
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 576              		.loc 1 266 3 discriminator 3 view .LVU190
+ 577 0020 1A68     		ldr	r2, [r3]
+ 578 0022 22F00102 		bic	r2, r2, #1
+ 579 0026 1A60     		str	r2, [r3]
+ 580              	.L32:
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 581              		.loc 1 266 3 discriminator 5 view .LVU191
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 582              		.loc 1 277 3 discriminator 5 view .LVU192
+ 583 0028 2046     		mov	r0, r4
+ 584              	.LVL26:
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 585              		.loc 1 277 3 is_stmt 0 discriminator 5 view .LVU193
+ 586 002a FFF7FEFF 		bl	HAL_TIMEx_HallSensor_MspDeInit
+ 587              	.LVL27:
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 588              		.loc 1 281 3 is_stmt 1 discriminator 5 view .LVU194
+ARM GAS  /tmp/cc9HXhVl.s 			page 79
+
+
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 589              		.loc 1 281 23 is_stmt 0 discriminator 5 view .LVU195
+ 590 002e 0020     		movs	r0, #0
+ 591 0030 84F84800 		strb	r0, [r4, #72]
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 592              		.loc 1 284 3 is_stmt 1 discriminator 5 view .LVU196
+ 593 0034 84F83E00 		strb	r0, [r4, #62]
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ 594              		.loc 1 285 3 discriminator 5 view .LVU197
+ 595 0038 84F83F00 		strb	r0, [r4, #63]
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 596              		.loc 1 286 3 discriminator 5 view .LVU198
+ 597 003c 84F84400 		strb	r0, [r4, #68]
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 598              		.loc 1 287 3 discriminator 5 view .LVU199
+ 599 0040 84F84500 		strb	r0, [r4, #69]
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 600              		.loc 1 290 3 discriminator 5 view .LVU200
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 601              		.loc 1 290 15 is_stmt 0 discriminator 5 view .LVU201
+ 602 0044 84F83D00 		strb	r0, [r4, #61]
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 603              		.loc 1 293 3 is_stmt 1 discriminator 5 view .LVU202
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 604              		.loc 1 293 3 discriminator 5 view .LVU203
+ 605 0048 84F83C00 		strb	r0, [r4, #60]
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 606              		.loc 1 293 3 discriminator 5 view .LVU204
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 607              		.loc 1 295 3 discriminator 5 view .LVU205
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 608              		.loc 1 296 1 is_stmt 0 discriminator 5 view .LVU206
+ 609 004c 10BD     		pop	{r4, pc}
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 610              		.loc 1 296 1 discriminator 5 view .LVU207
+ 611              		.cfi_endproc
+ 612              	.LFE330:
+ 614              		.section	.text.HAL_TIMEx_HallSensor_Start,"ax",%progbits
+ 615              		.align	1
+ 616              		.global	HAL_TIMEx_HallSensor_Start
+ 617              		.syntax unified
+ 618              		.thumb
+ 619              		.thumb_func
+ 621              	HAL_TIMEx_HallSensor_Start:
+ 622              	.LVL28:
+ 623              	.LFB333:
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 624              		.loc 1 334 1 is_stmt 1 view -0
+ 625              		.cfi_startproc
+ 626              		@ args = 0, pretend = 0, frame = 0
+ 627              		@ frame_needed = 0, uses_anonymous_args = 0
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 628              		.loc 1 334 1 is_stmt 0 view .LVU209
+ 629 0000 10B5     		push	{r4, lr}
+ 630              	.LCFI8:
+ 631              		.cfi_def_cfa_offset 8
+ 632              		.cfi_offset 4, -8
+ARM GAS  /tmp/cc9HXhVl.s 			page 80
+
+
+ 633              		.cfi_offset 14, -4
+ 634 0002 0446     		mov	r4, r0
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 635              		.loc 1 335 3 is_stmt 1 view .LVU210
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 636              		.loc 1 336 3 view .LVU211
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 637              		.loc 1 336 31 is_stmt 0 view .LVU212
+ 638 0004 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 639              	.LVL29:
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 640              		.loc 1 336 31 view .LVU213
+ 641 0008 C0B2     		uxtb	r0, r0
+ 642              	.LVL30:
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 643              		.loc 1 337 3 is_stmt 1 view .LVU214
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 644              		.loc 1 337 31 is_stmt 0 view .LVU215
+ 645 000a 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ 646              	.LVL31:
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 647              		.loc 1 338 3 is_stmt 1 view .LVU216
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 648              		.loc 1 338 31 is_stmt 0 view .LVU217
+ 649 000e 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 650              	.LVL32:
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 651              		.loc 1 339 3 is_stmt 1 view .LVU218
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 652              		.loc 1 339 31 is_stmt 0 view .LVU219
+ 653 0012 94F84510 		ldrb	r1, [r4, #69]	@ zero_extendqisi2
+ 654              	.LVL33:
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 655              		.loc 1 342 3 is_stmt 1 view .LVU220
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 656              		.loc 1 345 3 view .LVU221
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 657              		.loc 1 345 6 is_stmt 0 view .LVU222
+ 658 0016 0128     		cmp	r0, #1
+ 659 0018 42D1     		bne	.L38
+ 660 001a DBB2     		uxtb	r3, r3
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 661              		.loc 1 345 6 view .LVU223
+ 662 001c D2B2     		uxtb	r2, r2
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 663              		.loc 1 345 6 view .LVU224
+ 664 001e C9B2     		uxtb	r1, r1
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 665              		.loc 1 346 7 view .LVU225
+ 666 0020 012B     		cmp	r3, #1
+ 667 0022 3ED1     		bne	.L35
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 668              		.loc 1 347 7 view .LVU226
+ 669 0024 012A     		cmp	r2, #1
+ 670 0026 3DD1     		bne	.L39
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 671              		.loc 1 348 7 view .LVU227
+ARM GAS  /tmp/cc9HXhVl.s 			page 81
+
+
+ 672 0028 0129     		cmp	r1, #1
+ 673 002a 01D0     		beq	.L44
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 674              		.loc 1 350 12 view .LVU228
+ 675 002c 1046     		mov	r0, r2
+ 676              	.LVL34:
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 677              		.loc 1 350 12 view .LVU229
+ 678 002e 38E0     		b	.L35
+ 679              	.LVL35:
+ 680              	.L44:
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 681              		.loc 1 354 3 is_stmt 1 view .LVU230
+ 682 0030 0223     		movs	r3, #2
+ 683              	.LVL36:
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 684              		.loc 1 354 3 is_stmt 0 view .LVU231
+ 685 0032 84F83E30 		strb	r3, [r4, #62]
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 686              		.loc 1 355 3 is_stmt 1 view .LVU232
+ 687 0036 84F83F30 		strb	r3, [r4, #63]
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 688              		.loc 1 356 3 view .LVU233
+ 689 003a 84F84430 		strb	r3, [r4, #68]
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 690              		.loc 1 357 3 view .LVU234
+ 691 003e 84F84530 		strb	r3, [r4, #69]
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 692              		.loc 1 362 3 view .LVU235
+ 693 0042 0021     		movs	r1, #0
+ 694              	.LVL37:
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 695              		.loc 1 362 3 is_stmt 0 view .LVU236
+ 696 0044 2068     		ldr	r0, [r4]
+ 697              	.LVL38:
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 698              		.loc 1 362 3 view .LVU237
+ 699 0046 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 700              	.LVL39:
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 701              		.loc 1 365 3 is_stmt 1 view .LVU238
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 702              		.loc 1 365 7 is_stmt 0 view .LVU239
+ 703 004a 2368     		ldr	r3, [r4]
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 704              		.loc 1 365 6 view .LVU240
+ 705 004c 184A     		ldr	r2, .L45
+ 706 004e 9342     		cmp	r3, r2
+ 707 0050 18D0     		beq	.L36
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 708              		.loc 1 365 7 discriminator 1 view .LVU241
+ 709 0052 B3F1804F 		cmp	r3, #1073741824
+ 710 0056 15D0     		beq	.L36
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 711              		.loc 1 365 7 discriminator 2 view .LVU242
+ 712 0058 A2F59432 		sub	r2, r2, #75776
+ 713 005c 9342     		cmp	r3, r2
+ARM GAS  /tmp/cc9HXhVl.s 			page 82
+
+
+ 714 005e 11D0     		beq	.L36
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 715              		.loc 1 365 7 discriminator 3 view .LVU243
+ 716 0060 02F58062 		add	r2, r2, #1024
+ 717 0064 9342     		cmp	r3, r2
+ 718 0066 0DD0     		beq	.L36
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 719              		.loc 1 365 7 discriminator 4 view .LVU244
+ 720 0068 02F59632 		add	r2, r2, #76800
+ 721 006c 9342     		cmp	r3, r2
+ 722 006e 09D0     		beq	.L36
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 723              		.loc 1 365 7 discriminator 5 view .LVU245
+ 724 0070 02F54062 		add	r2, r2, #3072
+ 725 0074 9342     		cmp	r3, r2
+ 726 0076 05D0     		beq	.L36
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 727              		.loc 1 375 5 is_stmt 1 view .LVU246
+ 728 0078 1A68     		ldr	r2, [r3]
+ 729 007a 42F00102 		orr	r2, r2, #1
+ 730 007e 1A60     		str	r2, [r3]
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 731              		.loc 1 379 10 is_stmt 0 view .LVU247
+ 732 0080 0020     		movs	r0, #0
+ 733 0082 0EE0     		b	.L35
+ 734              	.L36:
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 735              		.loc 1 367 5 is_stmt 1 view .LVU248
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 736              		.loc 1 367 29 is_stmt 0 view .LVU249
+ 737 0084 9968     		ldr	r1, [r3, #8]
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 738              		.loc 1 367 13 view .LVU250
+ 739 0086 0B4A     		ldr	r2, .L45+4
+ 740 0088 0A40     		ands	r2, r2, r1
+ 741              	.LVL40:
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 742              		.loc 1 368 5 is_stmt 1 view .LVU251
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 743              		.loc 1 368 8 is_stmt 0 view .LVU252
+ 744 008a 062A     		cmp	r2, #6
+ 745 008c 0CD0     		beq	.L41
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 746              		.loc 1 368 9 discriminator 1 view .LVU253
+ 747 008e B2F5803F 		cmp	r2, #65536
+ 748 0092 0BD0     		beq	.L42
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 749              		.loc 1 370 7 is_stmt 1 view .LVU254
+ 750 0094 1A68     		ldr	r2, [r3]
+ 751              	.LVL41:
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 752              		.loc 1 370 7 is_stmt 0 view .LVU255
+ 753 0096 42F00102 		orr	r2, r2, #1
+ 754 009a 1A60     		str	r2, [r3]
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 755              		.loc 1 379 10 view .LVU256
+ 756 009c 0020     		movs	r0, #0
+ARM GAS  /tmp/cc9HXhVl.s 			page 83
+
+
+ 757 009e 00E0     		b	.L35
+ 758              	.LVL42:
+ 759              	.L38:
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 760              		.loc 1 350 12 view .LVU257
+ 761 00a0 0120     		movs	r0, #1
+ 762              	.LVL43:
+ 763              	.L35:
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 764              		.loc 1 380 1 view .LVU258
+ 765 00a2 10BD     		pop	{r4, pc}
+ 766              	.LVL44:
+ 767              	.L39:
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 768              		.loc 1 350 12 view .LVU259
+ 769 00a4 1846     		mov	r0, r3
+ 770              	.LVL45:
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 771              		.loc 1 350 12 view .LVU260
+ 772 00a6 FCE7     		b	.L35
+ 773              	.LVL46:
+ 774              	.L41:
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 775              		.loc 1 379 10 view .LVU261
+ 776 00a8 0020     		movs	r0, #0
+ 777 00aa FAE7     		b	.L35
+ 778              	.L42:
+ 779 00ac 0020     		movs	r0, #0
+ 780 00ae F8E7     		b	.L35
+ 781              	.L46:
+ 782              		.align	2
+ 783              	.L45:
+ 784 00b0 002C0140 		.word	1073818624
+ 785 00b4 07000100 		.word	65543
+ 786              		.cfi_endproc
+ 787              	.LFE333:
+ 789              		.section	.text.HAL_TIMEx_HallSensor_Stop,"ax",%progbits
+ 790              		.align	1
+ 791              		.global	HAL_TIMEx_HallSensor_Stop
+ 792              		.syntax unified
+ 793              		.thumb
+ 794              		.thumb_func
+ 796              	HAL_TIMEx_HallSensor_Stop:
+ 797              	.LVL47:
+ 798              	.LFB334:
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 799              		.loc 1 388 1 is_stmt 1 view -0
+ 800              		.cfi_startproc
+ 801              		@ args = 0, pretend = 0, frame = 0
+ 802              		@ frame_needed = 0, uses_anonymous_args = 0
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 803              		.loc 1 388 1 is_stmt 0 view .LVU263
+ 804 0000 10B5     		push	{r4, lr}
+ 805              	.LCFI9:
+ 806              		.cfi_def_cfa_offset 8
+ 807              		.cfi_offset 4, -8
+ 808              		.cfi_offset 14, -4
+ARM GAS  /tmp/cc9HXhVl.s 			page 84
+
+
+ 809 0002 0446     		mov	r4, r0
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 810              		.loc 1 390 3 is_stmt 1 view .LVU264
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 811              		.loc 1 395 3 view .LVU265
+ 812 0004 0022     		movs	r2, #0
+ 813 0006 1146     		mov	r1, r2
+ 814 0008 0068     		ldr	r0, [r0]
+ 815              	.LVL48:
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 816              		.loc 1 395 3 is_stmt 0 view .LVU266
+ 817 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 818              	.LVL49:
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 819              		.loc 1 398 3 is_stmt 1 view .LVU267
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 820              		.loc 1 398 3 view .LVU268
+ 821 000e 2368     		ldr	r3, [r4]
+ 822 0010 196A     		ldr	r1, [r3, #32]
+ 823 0012 41F21112 		movw	r2, #4369
+ 824 0016 1142     		tst	r1, r2
+ 825 0018 08D1     		bne	.L48
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 826              		.loc 1 398 3 discriminator 1 view .LVU269
+ 827 001a 196A     		ldr	r1, [r3, #32]
+ 828 001c 44F24442 		movw	r2, #17476
+ 829 0020 1142     		tst	r1, r2
+ 830 0022 03D1     		bne	.L48
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 831              		.loc 1 398 3 discriminator 3 view .LVU270
+ 832 0024 1A68     		ldr	r2, [r3]
+ 833 0026 22F00102 		bic	r2, r2, #1
+ 834 002a 1A60     		str	r2, [r3]
+ 835              	.L48:
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 836              		.loc 1 398 3 discriminator 5 view .LVU271
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 837              		.loc 1 401 3 discriminator 5 view .LVU272
+ 838 002c 0123     		movs	r3, #1
+ 839 002e 84F83E30 		strb	r3, [r4, #62]
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 840              		.loc 1 402 3 discriminator 5 view .LVU273
+ 841 0032 84F83F30 		strb	r3, [r4, #63]
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 842              		.loc 1 403 3 discriminator 5 view .LVU274
+ 843 0036 84F84430 		strb	r3, [r4, #68]
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 844              		.loc 1 404 3 discriminator 5 view .LVU275
+ 845 003a 84F84530 		strb	r3, [r4, #69]
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 846              		.loc 1 407 3 discriminator 5 view .LVU276
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 847              		.loc 1 408 1 is_stmt 0 discriminator 5 view .LVU277
+ 848 003e 0020     		movs	r0, #0
+ 849 0040 10BD     		pop	{r4, pc}
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 850              		.loc 1 408 1 discriminator 5 view .LVU278
+ARM GAS  /tmp/cc9HXhVl.s 			page 85
+
+
+ 851              		.cfi_endproc
+ 852              	.LFE334:
+ 854              		.section	.text.HAL_TIMEx_HallSensor_Start_IT,"ax",%progbits
+ 855              		.align	1
+ 856              		.global	HAL_TIMEx_HallSensor_Start_IT
+ 857              		.syntax unified
+ 858              		.thumb
+ 859              		.thumb_func
+ 861              	HAL_TIMEx_HallSensor_Start_IT:
+ 862              	.LVL50:
+ 863              	.LFB335:
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 864              		.loc 1 416 1 is_stmt 1 view -0
+ 865              		.cfi_startproc
+ 866              		@ args = 0, pretend = 0, frame = 0
+ 867              		@ frame_needed = 0, uses_anonymous_args = 0
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 868              		.loc 1 416 1 is_stmt 0 view .LVU280
+ 869 0000 10B5     		push	{r4, lr}
+ 870              	.LCFI10:
+ 871              		.cfi_def_cfa_offset 8
+ 872              		.cfi_offset 4, -8
+ 873              		.cfi_offset 14, -4
+ 874 0002 0446     		mov	r4, r0
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 875              		.loc 1 417 3 is_stmt 1 view .LVU281
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 876              		.loc 1 418 3 view .LVU282
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 877              		.loc 1 418 31 is_stmt 0 view .LVU283
+ 878 0004 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 879              	.LVL51:
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 880              		.loc 1 418 31 view .LVU284
+ 881 0008 C0B2     		uxtb	r0, r0
+ 882              	.LVL52:
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 883              		.loc 1 419 3 is_stmt 1 view .LVU285
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 884              		.loc 1 419 31 is_stmt 0 view .LVU286
+ 885 000a 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ 886              	.LVL53:
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 887              		.loc 1 420 3 is_stmt 1 view .LVU287
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 888              		.loc 1 420 31 is_stmt 0 view .LVU288
+ 889 000e 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 890              	.LVL54:
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 891              		.loc 1 421 3 is_stmt 1 view .LVU289
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 892              		.loc 1 421 31 is_stmt 0 view .LVU290
+ 893 0012 94F84510 		ldrb	r1, [r4, #69]	@ zero_extendqisi2
+ 894              	.LVL55:
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 895              		.loc 1 424 3 is_stmt 1 view .LVU291
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ARM GAS  /tmp/cc9HXhVl.s 			page 86
+
+
+ 896              		.loc 1 427 3 view .LVU292
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 897              		.loc 1 427 6 is_stmt 0 view .LVU293
+ 898 0016 0128     		cmp	r0, #1
+ 899 0018 48D1     		bne	.L54
+ 900 001a DBB2     		uxtb	r3, r3
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 901              		.loc 1 427 6 view .LVU294
+ 902 001c D2B2     		uxtb	r2, r2
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 903              		.loc 1 427 6 view .LVU295
+ 904 001e C9B2     		uxtb	r1, r1
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 905              		.loc 1 428 7 view .LVU296
+ 906 0020 012B     		cmp	r3, #1
+ 907 0022 44D1     		bne	.L51
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 908              		.loc 1 429 7 view .LVU297
+ 909 0024 012A     		cmp	r2, #1
+ 910 0026 43D1     		bne	.L55
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 911              		.loc 1 430 7 view .LVU298
+ 912 0028 0129     		cmp	r1, #1
+ 913 002a 01D0     		beq	.L60
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 914              		.loc 1 432 12 view .LVU299
+ 915 002c 1046     		mov	r0, r2
+ 916              	.LVL56:
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 917              		.loc 1 432 12 view .LVU300
+ 918 002e 3EE0     		b	.L51
+ 919              	.LVL57:
+ 920              	.L60:
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 921              		.loc 1 436 3 is_stmt 1 view .LVU301
+ 922 0030 0223     		movs	r3, #2
+ 923              	.LVL58:
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 924              		.loc 1 436 3 is_stmt 0 view .LVU302
+ 925 0032 84F83E30 		strb	r3, [r4, #62]
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 926              		.loc 1 437 3 is_stmt 1 view .LVU303
+ 927 0036 84F83F30 		strb	r3, [r4, #63]
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 928              		.loc 1 438 3 view .LVU304
+ 929 003a 84F84430 		strb	r3, [r4, #68]
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 930              		.loc 1 439 3 view .LVU305
+ 931 003e 84F84530 		strb	r3, [r4, #69]
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 932              		.loc 1 442 3 view .LVU306
+ 933 0042 2268     		ldr	r2, [r4]
+ 934              	.LVL59:
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 935              		.loc 1 442 3 is_stmt 0 view .LVU307
+ 936 0044 D368     		ldr	r3, [r2, #12]
+ 937 0046 43F00203 		orr	r3, r3, #2
+ARM GAS  /tmp/cc9HXhVl.s 			page 87
+
+
+ 938 004a D360     		str	r3, [r2, #12]
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 939              		.loc 1 447 3 is_stmt 1 view .LVU308
+ 940 004c 0122     		movs	r2, #1
+ 941 004e 0021     		movs	r1, #0
+ 942              	.LVL60:
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 943              		.loc 1 447 3 is_stmt 0 view .LVU309
+ 944 0050 2068     		ldr	r0, [r4]
+ 945              	.LVL61:
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 946              		.loc 1 447 3 view .LVU310
+ 947 0052 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 948              	.LVL62:
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 949              		.loc 1 450 3 is_stmt 1 view .LVU311
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 950              		.loc 1 450 7 is_stmt 0 view .LVU312
+ 951 0056 2368     		ldr	r3, [r4]
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 952              		.loc 1 450 6 view .LVU313
+ 953 0058 184A     		ldr	r2, .L61
+ 954 005a 9342     		cmp	r3, r2
+ 955 005c 18D0     		beq	.L52
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 956              		.loc 1 450 7 discriminator 1 view .LVU314
+ 957 005e B3F1804F 		cmp	r3, #1073741824
+ 958 0062 15D0     		beq	.L52
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 959              		.loc 1 450 7 discriminator 2 view .LVU315
+ 960 0064 A2F59432 		sub	r2, r2, #75776
+ 961 0068 9342     		cmp	r3, r2
+ 962 006a 11D0     		beq	.L52
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 963              		.loc 1 450 7 discriminator 3 view .LVU316
+ 964 006c 02F58062 		add	r2, r2, #1024
+ 965 0070 9342     		cmp	r3, r2
+ 966 0072 0DD0     		beq	.L52
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 967              		.loc 1 450 7 discriminator 4 view .LVU317
+ 968 0074 02F59632 		add	r2, r2, #76800
+ 969 0078 9342     		cmp	r3, r2
+ 970 007a 09D0     		beq	.L52
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 971              		.loc 1 450 7 discriminator 5 view .LVU318
+ 972 007c 02F54062 		add	r2, r2, #3072
+ 973 0080 9342     		cmp	r3, r2
+ 974 0082 05D0     		beq	.L52
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 975              		.loc 1 460 5 is_stmt 1 view .LVU319
+ 976 0084 1A68     		ldr	r2, [r3]
+ 977 0086 42F00102 		orr	r2, r2, #1
+ 978 008a 1A60     		str	r2, [r3]
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 979              		.loc 1 464 10 is_stmt 0 view .LVU320
+ 980 008c 0020     		movs	r0, #0
+ 981 008e 0EE0     		b	.L51
+ARM GAS  /tmp/cc9HXhVl.s 			page 88
+
+
+ 982              	.L52:
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 983              		.loc 1 452 5 is_stmt 1 view .LVU321
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 984              		.loc 1 452 29 is_stmt 0 view .LVU322
+ 985 0090 9968     		ldr	r1, [r3, #8]
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 986              		.loc 1 452 13 view .LVU323
+ 987 0092 0B4A     		ldr	r2, .L61+4
+ 988 0094 0A40     		ands	r2, r2, r1
+ 989              	.LVL63:
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 990              		.loc 1 453 5 is_stmt 1 view .LVU324
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 991              		.loc 1 453 8 is_stmt 0 view .LVU325
+ 992 0096 062A     		cmp	r2, #6
+ 993 0098 0CD0     		beq	.L57
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 994              		.loc 1 453 9 discriminator 1 view .LVU326
+ 995 009a B2F5803F 		cmp	r2, #65536
+ 996 009e 0BD0     		beq	.L58
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 997              		.loc 1 455 7 is_stmt 1 view .LVU327
+ 998 00a0 1A68     		ldr	r2, [r3]
+ 999              	.LVL64:
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1000              		.loc 1 455 7 is_stmt 0 view .LVU328
+ 1001 00a2 42F00102 		orr	r2, r2, #1
+ 1002 00a6 1A60     		str	r2, [r3]
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 1003              		.loc 1 464 10 view .LVU329
+ 1004 00a8 0020     		movs	r0, #0
+ 1005 00aa 00E0     		b	.L51
+ 1006              	.LVL65:
+ 1007              	.L54:
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 1008              		.loc 1 432 12 view .LVU330
+ 1009 00ac 0120     		movs	r0, #1
+ 1010              	.LVL66:
+ 1011              	.L51:
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1012              		.loc 1 465 1 view .LVU331
+ 1013 00ae 10BD     		pop	{r4, pc}
+ 1014              	.LVL67:
+ 1015              	.L55:
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 1016              		.loc 1 432 12 view .LVU332
+ 1017 00b0 1846     		mov	r0, r3
+ 1018              	.LVL68:
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 1019              		.loc 1 432 12 view .LVU333
+ 1020 00b2 FCE7     		b	.L51
+ 1021              	.LVL69:
+ 1022              	.L57:
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 1023              		.loc 1 464 10 view .LVU334
+ 1024 00b4 0020     		movs	r0, #0
+ARM GAS  /tmp/cc9HXhVl.s 			page 89
+
+
+ 1025 00b6 FAE7     		b	.L51
+ 1026              	.L58:
+ 1027 00b8 0020     		movs	r0, #0
+ 1028 00ba F8E7     		b	.L51
+ 1029              	.L62:
+ 1030              		.align	2
+ 1031              	.L61:
+ 1032 00bc 002C0140 		.word	1073818624
+ 1033 00c0 07000100 		.word	65543
+ 1034              		.cfi_endproc
+ 1035              	.LFE335:
+ 1037              		.section	.text.HAL_TIMEx_HallSensor_Stop_IT,"ax",%progbits
+ 1038              		.align	1
+ 1039              		.global	HAL_TIMEx_HallSensor_Stop_IT
+ 1040              		.syntax unified
+ 1041              		.thumb
+ 1042              		.thumb_func
+ 1044              	HAL_TIMEx_HallSensor_Stop_IT:
+ 1045              	.LVL70:
+ 1046              	.LFB336:
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 1047              		.loc 1 473 1 is_stmt 1 view -0
+ 1048              		.cfi_startproc
+ 1049              		@ args = 0, pretend = 0, frame = 0
+ 1050              		@ frame_needed = 0, uses_anonymous_args = 0
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 1051              		.loc 1 473 1 is_stmt 0 view .LVU336
+ 1052 0000 10B5     		push	{r4, lr}
+ 1053              	.LCFI11:
+ 1054              		.cfi_def_cfa_offset 8
+ 1055              		.cfi_offset 4, -8
+ 1056              		.cfi_offset 14, -4
+ 1057 0002 0446     		mov	r4, r0
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1058              		.loc 1 475 3 is_stmt 1 view .LVU337
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1059              		.loc 1 480 3 view .LVU338
+ 1060 0004 0022     		movs	r2, #0
+ 1061 0006 1146     		mov	r1, r2
+ 1062 0008 0068     		ldr	r0, [r0]
+ 1063              	.LVL71:
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1064              		.loc 1 480 3 is_stmt 0 view .LVU339
+ 1065 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 1066              	.LVL72:
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1067              		.loc 1 483 3 is_stmt 1 view .LVU340
+ 1068 000e 2268     		ldr	r2, [r4]
+ 1069 0010 D368     		ldr	r3, [r2, #12]
+ 1070 0012 23F00203 		bic	r3, r3, #2
+ 1071 0016 D360     		str	r3, [r2, #12]
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1072              		.loc 1 486 3 view .LVU341
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1073              		.loc 1 486 3 view .LVU342
+ 1074 0018 2368     		ldr	r3, [r4]
+ 1075 001a 196A     		ldr	r1, [r3, #32]
+ARM GAS  /tmp/cc9HXhVl.s 			page 90
+
+
+ 1076 001c 41F21112 		movw	r2, #4369
+ 1077 0020 1142     		tst	r1, r2
+ 1078 0022 08D1     		bne	.L64
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1079              		.loc 1 486 3 discriminator 1 view .LVU343
+ 1080 0024 196A     		ldr	r1, [r3, #32]
+ 1081 0026 44F24442 		movw	r2, #17476
+ 1082 002a 1142     		tst	r1, r2
+ 1083 002c 03D1     		bne	.L64
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1084              		.loc 1 486 3 discriminator 3 view .LVU344
+ 1085 002e 1A68     		ldr	r2, [r3]
+ 1086 0030 22F00102 		bic	r2, r2, #1
+ 1087 0034 1A60     		str	r2, [r3]
+ 1088              	.L64:
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1089              		.loc 1 486 3 discriminator 5 view .LVU345
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 1090              		.loc 1 489 3 discriminator 5 view .LVU346
+ 1091 0036 0123     		movs	r3, #1
+ 1092 0038 84F83E30 		strb	r3, [r4, #62]
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 1093              		.loc 1 490 3 discriminator 5 view .LVU347
+ 1094 003c 84F83F30 		strb	r3, [r4, #63]
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 1095              		.loc 1 491 3 discriminator 5 view .LVU348
+ 1096 0040 84F84430 		strb	r3, [r4, #68]
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1097              		.loc 1 492 3 discriminator 5 view .LVU349
+ 1098 0044 84F84530 		strb	r3, [r4, #69]
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 1099              		.loc 1 495 3 discriminator 5 view .LVU350
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1100              		.loc 1 496 1 is_stmt 0 discriminator 5 view .LVU351
+ 1101 0048 0020     		movs	r0, #0
+ 1102 004a 10BD     		pop	{r4, pc}
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1103              		.loc 1 496 1 discriminator 5 view .LVU352
+ 1104              		.cfi_endproc
+ 1105              	.LFE336:
+ 1107              		.section	.text.HAL_TIMEx_HallSensor_Start_DMA,"ax",%progbits
+ 1108              		.align	1
+ 1109              		.global	HAL_TIMEx_HallSensor_Start_DMA
+ 1110              		.syntax unified
+ 1111              		.thumb
+ 1112              		.thumb_func
+ 1114              	HAL_TIMEx_HallSensor_Start_DMA:
+ 1115              	.LVL73:
+ 1116              	.LFB337:
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 1117              		.loc 1 506 1 is_stmt 1 view -0
+ 1118              		.cfi_startproc
+ 1119              		@ args = 0, pretend = 0, frame = 0
+ 1120              		@ frame_needed = 0, uses_anonymous_args = 0
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 1121              		.loc 1 506 1 is_stmt 0 view .LVU354
+ 1122 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ARM GAS  /tmp/cc9HXhVl.s 			page 91
+
+
+ 1123              	.LCFI12:
+ 1124              		.cfi_def_cfa_offset 24
+ 1125              		.cfi_offset 3, -24
+ 1126              		.cfi_offset 4, -20
+ 1127              		.cfi_offset 5, -16
+ 1128              		.cfi_offset 6, -12
+ 1129              		.cfi_offset 7, -8
+ 1130              		.cfi_offset 14, -4
+ 1131 0002 0446     		mov	r4, r0
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 1132              		.loc 1 507 3 is_stmt 1 view .LVU355
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 1133              		.loc 1 508 3 view .LVU356
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 1134              		.loc 1 508 31 is_stmt 0 view .LVU357
+ 1135 0004 90F83EC0 		ldrb	ip, [r0, #62]	@ zero_extendqisi2
+ 1136 0008 5FFA8CF0 		uxtb	r0, ip
+ 1137              	.LVL74:
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1138              		.loc 1 509 3 is_stmt 1 view .LVU358
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1139              		.loc 1 509 31 is_stmt 0 view .LVU359
+ 1140 000c 94F844C0 		ldrb	ip, [r4, #68]	@ zero_extendqisi2
+ 1141              	.LVL75:
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1142              		.loc 1 512 3 is_stmt 1 view .LVU360
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 1143              		.loc 1 515 3 view .LVU361
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 1144              		.loc 1 515 6 is_stmt 0 view .LVU362
+ 1145 0010 0228     		cmp	r0, #2
+ 1146 0012 5CD0     		beq	.L67
+ 1147 0014 0F46     		mov	r7, r1
+ 1148 0016 1646     		mov	r6, r2
+ 1149 0018 5FFA8CF5 		uxtb	r5, ip
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1150              		.loc 1 516 7 view .LVU363
+ 1151 001c 022D     		cmp	r5, #2
+ 1152 001e 53D0     		beq	.L71
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****            && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ 1153              		.loc 1 520 8 is_stmt 1 view .LVU364
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****            && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ 1154              		.loc 1 520 11 is_stmt 0 view .LVU365
+ 1155 0020 0128     		cmp	r0, #1
+ 1156 0022 53D1     		bne	.L72
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1157              		.loc 1 521 12 view .LVU366
+ 1158 0024 012D     		cmp	r5, #1
+ 1159 0026 52D1     		bne	.L67
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1160              		.loc 1 523 5 is_stmt 1 view .LVU367
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1161              		.loc 1 523 8 is_stmt 0 view .LVU368
+ 1162 0028 0029     		cmp	r1, #0
+ 1163 002a 3CD0     		beq	.L76
+ 1164              	.L68:
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ARM GAS  /tmp/cc9HXhVl.s 			page 92
+
+
+ 1165              		.loc 1 529 7 is_stmt 1 view .LVU369
+ 1166 002c 0223     		movs	r3, #2
+ 1167 002e 84F83E30 		strb	r3, [r4, #62]
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1168              		.loc 1 530 7 view .LVU370
+ 1169 0032 84F84430 		strb	r3, [r4, #68]
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1170              		.loc 1 541 3 view .LVU371
+ 1171 0036 0122     		movs	r2, #1
+ 1172              	.LVL76:
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1173              		.loc 1 541 3 is_stmt 0 view .LVU372
+ 1174 0038 0021     		movs	r1, #0
+ 1175              	.LVL77:
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1176              		.loc 1 541 3 view .LVU373
+ 1177 003a 2068     		ldr	r0, [r4]
+ 1178              	.LVL78:
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1179              		.loc 1 541 3 view .LVU374
+ 1180 003c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 1181              	.LVL79:
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 1182              		.loc 1 544 3 is_stmt 1 view .LVU375
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 1183              		.loc 1 544 13 is_stmt 0 view .LVU376
+ 1184 0040 636A     		ldr	r3, [r4, #36]
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 1185              		.loc 1 544 48 view .LVU377
+ 1186 0042 244A     		ldr	r2, .L77
+ 1187 0044 DA62     		str	r2, [r3, #44]
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 1188              		.loc 1 545 3 is_stmt 1 view .LVU378
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 1189              		.loc 1 545 13 is_stmt 0 view .LVU379
+ 1190 0046 636A     		ldr	r3, [r4, #36]
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 1191              		.loc 1 545 52 view .LVU380
+ 1192 0048 234A     		ldr	r2, .L77+4
+ 1193 004a 1A63     		str	r2, [r3, #48]
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1194              		.loc 1 547 3 is_stmt 1 view .LVU381
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1195              		.loc 1 547 13 is_stmt 0 view .LVU382
+ 1196 004c 636A     		ldr	r3, [r4, #36]
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1197              		.loc 1 547 49 view .LVU383
+ 1198 004e 234A     		ldr	r2, .L77+8
+ 1199 0050 5A63     		str	r2, [r3, #52]
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1200              		.loc 1 550 3 is_stmt 1 view .LVU384
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1201              		.loc 1 550 67 is_stmt 0 view .LVU385
+ 1202 0052 2168     		ldr	r1, [r4]
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1203              		.loc 1 550 7 view .LVU386
+ 1204 0054 3346     		mov	r3, r6
+ARM GAS  /tmp/cc9HXhVl.s 			page 93
+
+
+ 1205 0056 3A46     		mov	r2, r7
+ 1206 0058 3431     		adds	r1, r1, #52
+ 1207 005a 606A     		ldr	r0, [r4, #36]
+ 1208 005c FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 1209              	.LVL80:
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1210              		.loc 1 550 6 view .LVU387
+ 1211 0060 0028     		cmp	r0, #0
+ 1212 0062 35D1     		bne	.L74
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1213              		.loc 1 556 3 is_stmt 1 view .LVU388
+ 1214 0064 2268     		ldr	r2, [r4]
+ 1215 0066 D368     		ldr	r3, [r2, #12]
+ 1216 0068 43F40073 		orr	r3, r3, #512
+ 1217 006c D360     		str	r3, [r2, #12]
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1218              		.loc 1 559 3 view .LVU389
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1219              		.loc 1 559 7 is_stmt 0 view .LVU390
+ 1220 006e 2368     		ldr	r3, [r4]
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1221              		.loc 1 559 6 view .LVU391
+ 1222 0070 1B4A     		ldr	r2, .L77+12
+ 1223 0072 9342     		cmp	r3, r2
+ 1224 0074 1BD0     		beq	.L69
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1225              		.loc 1 559 7 discriminator 1 view .LVU392
+ 1226 0076 B3F1804F 		cmp	r3, #1073741824
+ 1227 007a 18D0     		beq	.L69
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1228              		.loc 1 559 7 discriminator 2 view .LVU393
+ 1229 007c A2F59432 		sub	r2, r2, #75776
+ 1230 0080 9342     		cmp	r3, r2
+ 1231 0082 14D0     		beq	.L69
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1232              		.loc 1 559 7 discriminator 3 view .LVU394
+ 1233 0084 02F58062 		add	r2, r2, #1024
+ 1234 0088 9342     		cmp	r3, r2
+ 1235 008a 10D0     		beq	.L69
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1236              		.loc 1 559 7 discriminator 4 view .LVU395
+ 1237 008c 02F59632 		add	r2, r2, #76800
+ 1238 0090 9342     		cmp	r3, r2
+ 1239 0092 0CD0     		beq	.L69
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1240              		.loc 1 559 7 discriminator 5 view .LVU396
+ 1241 0094 02F54062 		add	r2, r2, #3072
+ 1242 0098 9342     		cmp	r3, r2
+ 1243 009a 08D0     		beq	.L69
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 1244              		.loc 1 569 5 is_stmt 1 view .LVU397
+ 1245 009c 1A68     		ldr	r2, [r3]
+ 1246 009e 42F00102 		orr	r2, r2, #1
+ 1247 00a2 1A60     		str	r2, [r3]
+ 1248 00a4 13E0     		b	.L67
+ 1249              	.LVL81:
+ 1250              	.L76:
+ARM GAS  /tmp/cc9HXhVl.s 			page 94
+
+
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1251              		.loc 1 523 25 is_stmt 0 discriminator 1 view .LVU398
+ 1252 00a6 002A     		cmp	r2, #0
+ 1253 00a8 C0D0     		beq	.L68
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1254              		.loc 1 525 14 view .LVU399
+ 1255 00aa 2846     		mov	r0, r5
+ 1256              	.LVL82:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1257              		.loc 1 525 14 view .LVU400
+ 1258 00ac 0FE0     		b	.L67
+ 1259              	.LVL83:
+ 1260              	.L69:
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1261              		.loc 1 561 5 is_stmt 1 view .LVU401
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1262              		.loc 1 561 29 is_stmt 0 view .LVU402
+ 1263 00ae 9968     		ldr	r1, [r3, #8]
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1264              		.loc 1 561 13 view .LVU403
+ 1265 00b0 0C4A     		ldr	r2, .L77+16
+ 1266 00b2 0A40     		ands	r2, r2, r1
+ 1267              	.LVL84:
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1268              		.loc 1 562 5 is_stmt 1 view .LVU404
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1269              		.loc 1 562 8 is_stmt 0 view .LVU405
+ 1270 00b4 062A     		cmp	r2, #6
+ 1271 00b6 0AD0     		beq	.L67
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1272              		.loc 1 562 9 discriminator 1 view .LVU406
+ 1273 00b8 B2F5803F 		cmp	r2, #65536
+ 1274 00bc 07D0     		beq	.L67
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1275              		.loc 1 564 7 is_stmt 1 view .LVU407
+ 1276 00be 1A68     		ldr	r2, [r3]
+ 1277              	.LVL85:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1278              		.loc 1 564 7 is_stmt 0 view .LVU408
+ 1279 00c0 42F00102 		orr	r2, r2, #1
+ 1280 00c4 1A60     		str	r2, [r3]
+ 1281 00c6 02E0     		b	.L67
+ 1282              	.LVL86:
+ 1283              	.L71:
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 1284              		.loc 1 518 12 view .LVU409
+ 1285 00c8 2846     		mov	r0, r5
+ 1286              	.LVL87:
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 1287              		.loc 1 518 12 view .LVU410
+ 1288 00ca 00E0     		b	.L67
+ 1289              	.LVL88:
+ 1290              	.L72:
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 1291              		.loc 1 535 12 view .LVU411
+ 1292 00cc 0120     		movs	r0, #1
+ 1293              	.LVL89:
+ARM GAS  /tmp/cc9HXhVl.s 			page 95
+
+
+ 1294              	.L67:
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1295              		.loc 1 574 1 view .LVU412
+ 1296 00ce F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 1297              	.LVL90:
+ 1298              	.L74:
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 1299              		.loc 1 553 12 view .LVU413
+ 1300 00d0 2846     		mov	r0, r5
+ 1301 00d2 FCE7     		b	.L67
+ 1302              	.L78:
+ 1303              		.align	2
+ 1304              	.L77:
+ 1305 00d4 00000000 		.word	TIM_DMACaptureCplt
+ 1306 00d8 00000000 		.word	TIM_DMACaptureHalfCplt
+ 1307 00dc 00000000 		.word	TIM_DMAError
+ 1308 00e0 002C0140 		.word	1073818624
+ 1309 00e4 07000100 		.word	65543
+ 1310              		.cfi_endproc
+ 1311              	.LFE337:
+ 1313              		.section	.text.HAL_TIMEx_HallSensor_Stop_DMA,"ax",%progbits
+ 1314              		.align	1
+ 1315              		.global	HAL_TIMEx_HallSensor_Stop_DMA
+ 1316              		.syntax unified
+ 1317              		.thumb
+ 1318              		.thumb_func
+ 1320              	HAL_TIMEx_HallSensor_Stop_DMA:
+ 1321              	.LVL91:
+ 1322              	.LFB338:
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 1323              		.loc 1 582 1 is_stmt 1 view -0
+ 1324              		.cfi_startproc
+ 1325              		@ args = 0, pretend = 0, frame = 0
+ 1326              		@ frame_needed = 0, uses_anonymous_args = 0
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 1327              		.loc 1 582 1 is_stmt 0 view .LVU415
+ 1328 0000 10B5     		push	{r4, lr}
+ 1329              	.LCFI13:
+ 1330              		.cfi_def_cfa_offset 8
+ 1331              		.cfi_offset 4, -8
+ 1332              		.cfi_offset 14, -4
+ 1333 0002 0446     		mov	r4, r0
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1334              		.loc 1 584 3 is_stmt 1 view .LVU416
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1335              		.loc 1 589 3 view .LVU417
+ 1336 0004 0022     		movs	r2, #0
+ 1337 0006 1146     		mov	r1, r2
+ 1338 0008 0068     		ldr	r0, [r0]
+ 1339              	.LVL92:
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1340              		.loc 1 589 3 is_stmt 0 view .LVU418
+ 1341 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 1342              	.LVL93:
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1343              		.loc 1 593 3 is_stmt 1 view .LVU419
+ 1344 000e 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/cc9HXhVl.s 			page 96
+
+
+ 1345 0010 D368     		ldr	r3, [r2, #12]
+ 1346 0012 23F40073 		bic	r3, r3, #512
+ 1347 0016 D360     		str	r3, [r2, #12]
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1348              		.loc 1 595 3 view .LVU420
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1349              		.loc 1 595 9 is_stmt 0 view .LVU421
+ 1350 0018 606A     		ldr	r0, [r4, #36]
+ 1351 001a FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 1352              	.LVL94:
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1353              		.loc 1 598 3 is_stmt 1 view .LVU422
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1354              		.loc 1 598 3 view .LVU423
+ 1355 001e 2368     		ldr	r3, [r4]
+ 1356 0020 196A     		ldr	r1, [r3, #32]
+ 1357 0022 41F21112 		movw	r2, #4369
+ 1358 0026 1142     		tst	r1, r2
+ 1359 0028 08D1     		bne	.L80
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1360              		.loc 1 598 3 discriminator 1 view .LVU424
+ 1361 002a 196A     		ldr	r1, [r3, #32]
+ 1362 002c 44F24442 		movw	r2, #17476
+ 1363 0030 1142     		tst	r1, r2
+ 1364 0032 03D1     		bne	.L80
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1365              		.loc 1 598 3 discriminator 3 view .LVU425
+ 1366 0034 1A68     		ldr	r2, [r3]
+ 1367 0036 22F00102 		bic	r2, r2, #1
+ 1368 003a 1A60     		str	r2, [r3]
+ 1369              	.L80:
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1370              		.loc 1 598 3 discriminator 5 view .LVU426
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 1371              		.loc 1 601 3 discriminator 5 view .LVU427
+ 1372 003c 0123     		movs	r3, #1
+ 1373 003e 84F83E30 		strb	r3, [r4, #62]
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1374              		.loc 1 602 3 discriminator 5 view .LVU428
+ 1375 0042 84F84430 		strb	r3, [r4, #68]
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 1376              		.loc 1 605 3 discriminator 5 view .LVU429
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1377              		.loc 1 606 1 is_stmt 0 discriminator 5 view .LVU430
+ 1378 0046 0020     		movs	r0, #0
+ 1379 0048 10BD     		pop	{r4, pc}
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1380              		.loc 1 606 1 discriminator 5 view .LVU431
+ 1381              		.cfi_endproc
+ 1382              	.LFE338:
+ 1384              		.section	.text.HAL_TIMEx_OCN_Start,"ax",%progbits
+ 1385              		.align	1
+ 1386              		.global	HAL_TIMEx_OCN_Start
+ 1387              		.syntax unified
+ 1388              		.thumb
+ 1389              		.thumb_func
+ 1391              	HAL_TIMEx_OCN_Start:
+ARM GAS  /tmp/cc9HXhVl.s 			page 97
+
+
+ 1392              	.LVL95:
+ 1393              	.LFB339:
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 1394              		.loc 1 645 1 is_stmt 1 view -0
+ 1395              		.cfi_startproc
+ 1396              		@ args = 0, pretend = 0, frame = 0
+ 1397              		@ frame_needed = 0, uses_anonymous_args = 0
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 1398              		.loc 1 645 1 is_stmt 0 view .LVU433
+ 1399 0000 10B5     		push	{r4, lr}
+ 1400              	.LCFI14:
+ 1401              		.cfi_def_cfa_offset 8
+ 1402              		.cfi_offset 4, -8
+ 1403              		.cfi_offset 14, -4
+ 1404 0002 0446     		mov	r4, r0
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1405              		.loc 1 646 3 is_stmt 1 view .LVU434
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1406              		.loc 1 649 3 view .LVU435
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1407              		.loc 1 652 3 view .LVU436
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1408              		.loc 1 652 46 is_stmt 0 view .LVU437
+ 1409 0004 0846     		mov	r0, r1
+ 1410              	.LVL96:
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1411              		.loc 1 652 46 view .LVU438
+ 1412 0006 0029     		cmp	r1, #0
+ 1413 0008 33D1     		bne	.L83
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1414              		.loc 1 652 7 discriminator 1 view .LVU439
+ 1415 000a 94F84430 		ldrb	r3, [r4, #68]	@ zero_extendqisi2
+ 1416 000e DBB2     		uxtb	r3, r3
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1417              		.loc 1 652 46 discriminator 1 view .LVU440
+ 1418 0010 013B     		subs	r3, r3, #1
+ 1419 0012 18BF     		it	ne
+ 1420 0014 0123     		movne	r3, #1
+ 1421              	.L84:
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1422              		.loc 1 652 6 discriminator 12 view .LVU441
+ 1423 0016 002B     		cmp	r3, #0
+ 1424 0018 62D1     		bne	.L94
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1425              		.loc 1 658 3 is_stmt 1 view .LVU442
+ 1426 001a 0028     		cmp	r0, #0
+ 1427 001c 42D1     		bne	.L88
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1428              		.loc 1 658 3 is_stmt 0 discriminator 1 view .LVU443
+ 1429 001e 0223     		movs	r3, #2
+ 1430 0020 84F84430 		strb	r3, [r4, #68]
+ 1431              	.L89:
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1432              		.loc 1 661 3 is_stmt 1 view .LVU444
+ 1433 0024 0422     		movs	r2, #4
+ 1434 0026 0146     		mov	r1, r0
+ 1435              	.LVL97:
+ARM GAS  /tmp/cc9HXhVl.s 			page 98
+
+
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1436              		.loc 1 661 3 is_stmt 0 view .LVU445
+ 1437 0028 2068     		ldr	r0, [r4]
+ 1438              	.LVL98:
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1439              		.loc 1 661 3 view .LVU446
+ 1440 002a FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 1441              	.LVL99:
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1442              		.loc 1 664 3 is_stmt 1 view .LVU447
+ 1443 002e 2268     		ldr	r2, [r4]
+ 1444 0030 536C     		ldr	r3, [r2, #68]
+ 1445 0032 43F40043 		orr	r3, r3, #32768
+ 1446 0036 5364     		str	r3, [r2, #68]
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1447              		.loc 1 667 3 view .LVU448
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1448              		.loc 1 667 7 is_stmt 0 view .LVU449
+ 1449 0038 2368     		ldr	r3, [r4]
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1450              		.loc 1 667 6 view .LVU450
+ 1451 003a 2C4A     		ldr	r2, .L102
+ 1452 003c 9342     		cmp	r3, r2
+ 1453 003e 41D0     		beq	.L92
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1454              		.loc 1 667 7 discriminator 1 view .LVU451
+ 1455 0040 B3F1804F 		cmp	r3, #1073741824
+ 1456 0044 3ED0     		beq	.L92
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1457              		.loc 1 667 7 discriminator 2 view .LVU452
+ 1458 0046 A2F59432 		sub	r2, r2, #75776
+ 1459 004a 9342     		cmp	r3, r2
+ 1460 004c 3AD0     		beq	.L92
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1461              		.loc 1 667 7 discriminator 3 view .LVU453
+ 1462 004e 02F58062 		add	r2, r2, #1024
+ 1463 0052 9342     		cmp	r3, r2
+ 1464 0054 36D0     		beq	.L92
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1465              		.loc 1 667 7 discriminator 4 view .LVU454
+ 1466 0056 02F59632 		add	r2, r2, #76800
+ 1467 005a 9342     		cmp	r3, r2
+ 1468 005c 32D0     		beq	.L92
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1469              		.loc 1 667 7 discriminator 5 view .LVU455
+ 1470 005e 02F54062 		add	r2, r2, #3072
+ 1471 0062 9342     		cmp	r3, r2
+ 1472 0064 2ED0     		beq	.L92
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 1473              		.loc 1 677 5 is_stmt 1 view .LVU456
+ 1474 0066 1A68     		ldr	r2, [r3]
+ 1475 0068 42F00102 		orr	r2, r2, #1
+ 1476 006c 1A60     		str	r2, [r3]
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 1477              		.loc 1 681 10 is_stmt 0 view .LVU457
+ 1478 006e 0020     		movs	r0, #0
+ 1479 0070 37E0     		b	.L87
+ARM GAS  /tmp/cc9HXhVl.s 			page 99
+
+
+ 1480              	.LVL100:
+ 1481              	.L83:
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1482              		.loc 1 652 46 discriminator 2 view .LVU458
+ 1483 0072 0429     		cmp	r1, #4
+ 1484 0074 08D0     		beq	.L98
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1485              		.loc 1 652 46 discriminator 5 view .LVU459
+ 1486 0076 0829     		cmp	r1, #8
+ 1487 0078 0DD0     		beq	.L99
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1488              		.loc 1 652 7 discriminator 8 view .LVU460
+ 1489 007a 94F84730 		ldrb	r3, [r4, #71]	@ zero_extendqisi2
+ 1490 007e DBB2     		uxtb	r3, r3
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1491              		.loc 1 652 46 discriminator 8 view .LVU461
+ 1492 0080 013B     		subs	r3, r3, #1
+ 1493 0082 18BF     		it	ne
+ 1494 0084 0123     		movne	r3, #1
+ 1495 0086 C6E7     		b	.L84
+ 1496              	.L98:
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1497              		.loc 1 652 7 discriminator 4 view .LVU462
+ 1498 0088 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 1499 008c DBB2     		uxtb	r3, r3
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1500              		.loc 1 652 46 discriminator 4 view .LVU463
+ 1501 008e 013B     		subs	r3, r3, #1
+ 1502 0090 18BF     		it	ne
+ 1503 0092 0123     		movne	r3, #1
+ 1504 0094 BFE7     		b	.L84
+ 1505              	.L99:
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1506              		.loc 1 652 7 discriminator 7 view .LVU464
+ 1507 0096 94F84630 		ldrb	r3, [r4, #70]	@ zero_extendqisi2
+ 1508 009a DBB2     		uxtb	r3, r3
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1509              		.loc 1 652 46 discriminator 7 view .LVU465
+ 1510 009c 013B     		subs	r3, r3, #1
+ 1511 009e 18BF     		it	ne
+ 1512 00a0 0123     		movne	r3, #1
+ 1513 00a2 B8E7     		b	.L84
+ 1514              	.L88:
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1515              		.loc 1 658 3 discriminator 2 view .LVU466
+ 1516 00a4 0428     		cmp	r0, #4
+ 1517 00a6 05D0     		beq	.L100
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1518              		.loc 1 658 3 discriminator 4 view .LVU467
+ 1519 00a8 0828     		cmp	r0, #8
+ 1520 00aa 07D0     		beq	.L101
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1521              		.loc 1 658 3 discriminator 7 view .LVU468
+ 1522 00ac 0223     		movs	r3, #2
+ 1523 00ae 84F84730 		strb	r3, [r4, #71]
+ 1524 00b2 B7E7     		b	.L89
+ 1525              	.L100:
+ARM GAS  /tmp/cc9HXhVl.s 			page 100
+
+
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1526              		.loc 1 658 3 discriminator 3 view .LVU469
+ 1527 00b4 0223     		movs	r3, #2
+ 1528 00b6 84F84530 		strb	r3, [r4, #69]
+ 1529 00ba B3E7     		b	.L89
+ 1530              	.L101:
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1531              		.loc 1 658 3 discriminator 6 view .LVU470
+ 1532 00bc 0223     		movs	r3, #2
+ 1533 00be 84F84630 		strb	r3, [r4, #70]
+ 1534 00c2 AFE7     		b	.L89
+ 1535              	.LVL101:
+ 1536              	.L92:
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1537              		.loc 1 669 5 is_stmt 1 view .LVU471
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1538              		.loc 1 669 29 is_stmt 0 view .LVU472
+ 1539 00c4 9968     		ldr	r1, [r3, #8]
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1540              		.loc 1 669 13 view .LVU473
+ 1541 00c6 0A4A     		ldr	r2, .L102+4
+ 1542 00c8 0A40     		ands	r2, r2, r1
+ 1543              	.LVL102:
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1544              		.loc 1 670 5 is_stmt 1 view .LVU474
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1545              		.loc 1 670 8 is_stmt 0 view .LVU475
+ 1546 00ca 062A     		cmp	r2, #6
+ 1547 00cc 0AD0     		beq	.L95
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1548              		.loc 1 670 9 discriminator 1 view .LVU476
+ 1549 00ce B2F5803F 		cmp	r2, #65536
+ 1550 00d2 09D0     		beq	.L96
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1551              		.loc 1 672 7 is_stmt 1 view .LVU477
+ 1552 00d4 1A68     		ldr	r2, [r3]
+ 1553              	.LVL103:
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1554              		.loc 1 672 7 is_stmt 0 view .LVU478
+ 1555 00d6 42F00102 		orr	r2, r2, #1
+ 1556 00da 1A60     		str	r2, [r3]
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 1557              		.loc 1 681 10 view .LVU479
+ 1558 00dc 0020     		movs	r0, #0
+ 1559 00de 00E0     		b	.L87
+ 1560              	.LVL104:
+ 1561              	.L94:
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 1562              		.loc 1 654 12 view .LVU480
+ 1563 00e0 0120     		movs	r0, #1
+ 1564              	.LVL105:
+ 1565              	.L87:
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1566              		.loc 1 682 1 view .LVU481
+ 1567 00e2 10BD     		pop	{r4, pc}
+ 1568              	.LVL106:
+ 1569              	.L95:
+ARM GAS  /tmp/cc9HXhVl.s 			page 101
+
+
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 1570              		.loc 1 681 10 view .LVU482
+ 1571 00e4 0020     		movs	r0, #0
+ 1572 00e6 FCE7     		b	.L87
+ 1573              	.L96:
+ 1574 00e8 0020     		movs	r0, #0
+ 1575 00ea FAE7     		b	.L87
+ 1576              	.L103:
+ 1577              		.align	2
+ 1578              	.L102:
+ 1579 00ec 002C0140 		.word	1073818624
+ 1580 00f0 07000100 		.word	65543
+ 1581              		.cfi_endproc
+ 1582              	.LFE339:
+ 1584              		.section	.text.HAL_TIMEx_OCN_Stop,"ax",%progbits
+ 1585              		.align	1
+ 1586              		.global	HAL_TIMEx_OCN_Stop
+ 1587              		.syntax unified
+ 1588              		.thumb
+ 1589              		.thumb_func
+ 1591              	HAL_TIMEx_OCN_Stop:
+ 1592              	.LVL107:
+ 1593              	.LFB340:
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 1594              		.loc 1 697 1 is_stmt 1 view -0
+ 1595              		.cfi_startproc
+ 1596              		@ args = 0, pretend = 0, frame = 0
+ 1597              		@ frame_needed = 0, uses_anonymous_args = 0
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 1598              		.loc 1 697 1 is_stmt 0 view .LVU484
+ 1599 0000 38B5     		push	{r3, r4, r5, lr}
+ 1600              	.LCFI15:
+ 1601              		.cfi_def_cfa_offset 16
+ 1602              		.cfi_offset 3, -16
+ 1603              		.cfi_offset 4, -12
+ 1604              		.cfi_offset 5, -8
+ 1605              		.cfi_offset 14, -4
+ 1606 0002 0446     		mov	r4, r0
+ 1607 0004 0D46     		mov	r5, r1
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1608              		.loc 1 699 3 is_stmt 1 view .LVU485
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1609              		.loc 1 702 3 view .LVU486
+ 1610 0006 0022     		movs	r2, #0
+ 1611 0008 0068     		ldr	r0, [r0]
+ 1612              	.LVL108:
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1613              		.loc 1 702 3 is_stmt 0 view .LVU487
+ 1614 000a FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 1615              	.LVL109:
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1616              		.loc 1 705 3 is_stmt 1 view .LVU488
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1617              		.loc 1 705 3 view .LVU489
+ 1618 000e 2368     		ldr	r3, [r4]
+ 1619 0010 196A     		ldr	r1, [r3, #32]
+ 1620 0012 41F21112 		movw	r2, #4369
+ARM GAS  /tmp/cc9HXhVl.s 			page 102
+
+
+ 1621 0016 1142     		tst	r1, r2
+ 1622 0018 08D1     		bne	.L105
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1623              		.loc 1 705 3 discriminator 1 view .LVU490
+ 1624 001a 196A     		ldr	r1, [r3, #32]
+ 1625 001c 44F24442 		movw	r2, #17476
+ 1626 0020 1142     		tst	r1, r2
+ 1627 0022 03D1     		bne	.L105
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1628              		.loc 1 705 3 discriminator 3 view .LVU491
+ 1629 0024 5A6C     		ldr	r2, [r3, #68]
+ 1630 0026 22F40042 		bic	r2, r2, #32768
+ 1631 002a 5A64     		str	r2, [r3, #68]
+ 1632              	.L105:
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1633              		.loc 1 705 3 discriminator 5 view .LVU492
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1634              		.loc 1 708 3 discriminator 5 view .LVU493
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1635              		.loc 1 708 3 discriminator 5 view .LVU494
+ 1636 002c 2368     		ldr	r3, [r4]
+ 1637 002e 196A     		ldr	r1, [r3, #32]
+ 1638 0030 41F21112 		movw	r2, #4369
+ 1639 0034 1142     		tst	r1, r2
+ 1640 0036 08D1     		bne	.L106
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1641              		.loc 1 708 3 discriminator 1 view .LVU495
+ 1642 0038 196A     		ldr	r1, [r3, #32]
+ 1643 003a 44F24442 		movw	r2, #17476
+ 1644 003e 1142     		tst	r1, r2
+ 1645 0040 03D1     		bne	.L106
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1646              		.loc 1 708 3 discriminator 3 view .LVU496
+ 1647 0042 1A68     		ldr	r2, [r3]
+ 1648 0044 22F00102 		bic	r2, r2, #1
+ 1649 0048 1A60     		str	r2, [r3]
+ 1650              	.L106:
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1651              		.loc 1 708 3 discriminator 5 view .LVU497
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1652              		.loc 1 711 3 discriminator 5 view .LVU498
+ 1653 004a 25B9     		cbnz	r5, .L107
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1654              		.loc 1 711 3 is_stmt 0 discriminator 1 view .LVU499
+ 1655 004c 0123     		movs	r3, #1
+ 1656 004e 84F84430 		strb	r3, [r4, #68]
+ 1657              	.L108:
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 1658              		.loc 1 714 3 is_stmt 1 view .LVU500
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1659              		.loc 1 715 1 is_stmt 0 view .LVU501
+ 1660 0052 0020     		movs	r0, #0
+ 1661 0054 38BD     		pop	{r3, r4, r5, pc}
+ 1662              	.LVL110:
+ 1663              	.L107:
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1664              		.loc 1 711 3 discriminator 2 view .LVU502
+ARM GAS  /tmp/cc9HXhVl.s 			page 103
+
+
+ 1665 0056 042D     		cmp	r5, #4
+ 1666 0058 05D0     		beq	.L112
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1667              		.loc 1 711 3 discriminator 4 view .LVU503
+ 1668 005a 082D     		cmp	r5, #8
+ 1669 005c 07D0     		beq	.L113
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1670              		.loc 1 711 3 discriminator 7 view .LVU504
+ 1671 005e 0123     		movs	r3, #1
+ 1672 0060 84F84730 		strb	r3, [r4, #71]
+ 1673 0064 F5E7     		b	.L108
+ 1674              	.L112:
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1675              		.loc 1 711 3 discriminator 3 view .LVU505
+ 1676 0066 0123     		movs	r3, #1
+ 1677 0068 84F84530 		strb	r3, [r4, #69]
+ 1678 006c F1E7     		b	.L108
+ 1679              	.L113:
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1680              		.loc 1 711 3 discriminator 6 view .LVU506
+ 1681 006e 0123     		movs	r3, #1
+ 1682 0070 84F84630 		strb	r3, [r4, #70]
+ 1683 0074 EDE7     		b	.L108
+ 1684              		.cfi_endproc
+ 1685              	.LFE340:
+ 1687              		.section	.text.HAL_TIMEx_OCN_Start_IT,"ax",%progbits
+ 1688              		.align	1
+ 1689              		.global	HAL_TIMEx_OCN_Start_IT
+ 1690              		.syntax unified
+ 1691              		.thumb
+ 1692              		.thumb_func
+ 1694              	HAL_TIMEx_OCN_Start_IT:
+ 1695              	.LVL111:
+ 1696              	.LFB341:
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1697              		.loc 1 730 1 is_stmt 1 view -0
+ 1698              		.cfi_startproc
+ 1699              		@ args = 0, pretend = 0, frame = 0
+ 1700              		@ frame_needed = 0, uses_anonymous_args = 0
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1701              		.loc 1 730 1 is_stmt 0 view .LVU508
+ 1702 0000 10B5     		push	{r4, lr}
+ 1703              	.LCFI16:
+ 1704              		.cfi_def_cfa_offset 8
+ 1705              		.cfi_offset 4, -8
+ 1706              		.cfi_offset 14, -4
+ 1707 0002 0446     		mov	r4, r0
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 1708              		.loc 1 731 3 is_stmt 1 view .LVU509
+ 1709              	.LVL112:
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1710              		.loc 1 732 3 view .LVU510
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1711              		.loc 1 735 3 view .LVU511
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1712              		.loc 1 738 3 view .LVU512
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc9HXhVl.s 			page 104
+
+
+ 1713              		.loc 1 738 46 is_stmt 0 view .LVU513
+ 1714 0004 0846     		mov	r0, r1
+ 1715              	.LVL113:
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1716              		.loc 1 738 46 view .LVU514
+ 1717 0006 0029     		cmp	r1, #0
+ 1718 0008 3ED1     		bne	.L115
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1719              		.loc 1 738 7 discriminator 1 view .LVU515
+ 1720 000a 94F84430 		ldrb	r3, [r4, #68]	@ zero_extendqisi2
+ 1721 000e DBB2     		uxtb	r3, r3
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1722              		.loc 1 738 46 discriminator 1 view .LVU516
+ 1723 0010 013B     		subs	r3, r3, #1
+ 1724 0012 18BF     		it	ne
+ 1725 0014 0123     		movne	r3, #1
+ 1726              	.L116:
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1727              		.loc 1 738 6 discriminator 12 view .LVU517
+ 1728 0016 002B     		cmp	r3, #0
+ 1729 0018 40F09C80 		bne	.L131
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1730              		.loc 1 744 3 is_stmt 1 view .LVU518
+ 1731 001c 0028     		cmp	r0, #0
+ 1732 001e 4CD1     		bne	.L120
+ 1733 0020 0223     		movs	r3, #2
+ 1734 0022 84F84430 		strb	r3, [r4, #68]
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1735              		.loc 1 746 3 view .LVU519
+ 1736              	.L121:
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 1737              		.loc 1 751 7 view .LVU520
+ 1738 0026 2268     		ldr	r2, [r4]
+ 1739 0028 D368     		ldr	r3, [r2, #12]
+ 1740 002a 43F00203 		orr	r3, r3, #2
+ 1741 002e D360     		str	r3, [r2, #12]
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1742              		.loc 1 752 7 view .LVU521
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1743              		.loc 1 782 3 view .LVU522
+ 1744              	.L128:
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1745              		.loc 1 785 5 view .LVU523
+ 1746 0030 2268     		ldr	r2, [r4]
+ 1747 0032 D368     		ldr	r3, [r2, #12]
+ 1748 0034 43F08003 		orr	r3, r3, #128
+ 1749 0038 D360     		str	r3, [r2, #12]
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1750              		.loc 1 788 5 view .LVU524
+ 1751 003a 0422     		movs	r2, #4
+ 1752 003c 0146     		mov	r1, r0
+ 1753              	.LVL114:
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1754              		.loc 1 788 5 is_stmt 0 view .LVU525
+ 1755 003e 2068     		ldr	r0, [r4]
+ 1756              	.LVL115:
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 105
+
+
+ 1757              		.loc 1 788 5 view .LVU526
+ 1758 0040 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 1759              	.LVL116:
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1760              		.loc 1 791 5 is_stmt 1 view .LVU527
+ 1761 0044 2268     		ldr	r2, [r4]
+ 1762 0046 536C     		ldr	r3, [r2, #68]
+ 1763 0048 43F40043 		orr	r3, r3, #32768
+ 1764 004c 5364     		str	r3, [r2, #68]
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1765              		.loc 1 794 5 view .LVU528
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1766              		.loc 1 794 9 is_stmt 0 view .LVU529
+ 1767 004e 2368     		ldr	r3, [r4]
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1768              		.loc 1 794 8 view .LVU530
+ 1769 0050 444A     		ldr	r2, .L143
+ 1770 0052 9342     		cmp	r3, r2
+ 1771 0054 70D0     		beq	.L129
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1772              		.loc 1 794 9 discriminator 1 view .LVU531
+ 1773 0056 B3F1804F 		cmp	r3, #1073741824
+ 1774 005a 6DD0     		beq	.L129
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1775              		.loc 1 794 9 discriminator 2 view .LVU532
+ 1776 005c A2F59432 		sub	r2, r2, #75776
+ 1777 0060 9342     		cmp	r3, r2
+ 1778 0062 69D0     		beq	.L129
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1779              		.loc 1 794 9 discriminator 3 view .LVU533
+ 1780 0064 02F58062 		add	r2, r2, #1024
+ 1781 0068 9342     		cmp	r3, r2
+ 1782 006a 65D0     		beq	.L129
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1783              		.loc 1 794 9 discriminator 4 view .LVU534
+ 1784 006c 02F59632 		add	r2, r2, #76800
+ 1785 0070 9342     		cmp	r3, r2
+ 1786 0072 61D0     		beq	.L129
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 1787              		.loc 1 794 9 discriminator 5 view .LVU535
+ 1788 0074 02F54062 		add	r2, r2, #3072
+ 1789 0078 9342     		cmp	r3, r2
+ 1790 007a 5DD0     		beq	.L129
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1791              		.loc 1 804 7 is_stmt 1 view .LVU536
+ 1792 007c 1A68     		ldr	r2, [r3]
+ 1793 007e 42F00102 		orr	r2, r2, #1
+ 1794 0082 1A60     		str	r2, [r3]
+ 1795 0084 0020     		movs	r0, #0
+ 1796 0086 66E0     		b	.L119
+ 1797              	.LVL117:
+ 1798              	.L115:
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1799              		.loc 1 738 46 is_stmt 0 discriminator 2 view .LVU537
+ 1800 0088 0429     		cmp	r1, #4
+ 1801 008a 08D0     		beq	.L139
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc9HXhVl.s 			page 106
+
+
+ 1802              		.loc 1 738 46 discriminator 5 view .LVU538
+ 1803 008c 0829     		cmp	r1, #8
+ 1804 008e 0DD0     		beq	.L140
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1805              		.loc 1 738 7 discriminator 8 view .LVU539
+ 1806 0090 94F84730 		ldrb	r3, [r4, #71]	@ zero_extendqisi2
+ 1807 0094 DBB2     		uxtb	r3, r3
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1808              		.loc 1 738 46 discriminator 8 view .LVU540
+ 1809 0096 013B     		subs	r3, r3, #1
+ 1810 0098 18BF     		it	ne
+ 1811 009a 0123     		movne	r3, #1
+ 1812 009c BBE7     		b	.L116
+ 1813              	.L139:
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1814              		.loc 1 738 7 discriminator 4 view .LVU541
+ 1815 009e 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 1816 00a2 DBB2     		uxtb	r3, r3
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1817              		.loc 1 738 46 discriminator 4 view .LVU542
+ 1818 00a4 013B     		subs	r3, r3, #1
+ 1819 00a6 18BF     		it	ne
+ 1820 00a8 0123     		movne	r3, #1
+ 1821 00aa B4E7     		b	.L116
+ 1822              	.L140:
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1823              		.loc 1 738 7 discriminator 7 view .LVU543
+ 1824 00ac 94F84630 		ldrb	r3, [r4, #70]	@ zero_extendqisi2
+ 1825 00b0 DBB2     		uxtb	r3, r3
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1826              		.loc 1 738 46 discriminator 7 view .LVU544
+ 1827 00b2 013B     		subs	r3, r3, #1
+ 1828 00b4 18BF     		it	ne
+ 1829 00b6 0123     		movne	r3, #1
+ 1830 00b8 ADE7     		b	.L116
+ 1831              	.L120:
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1832              		.loc 1 744 3 discriminator 2 view .LVU545
+ 1833 00ba 0428     		cmp	r0, #4
+ 1834 00bc 24D0     		beq	.L141
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1835              		.loc 1 744 3 discriminator 4 view .LVU546
+ 1836 00be 0828     		cmp	r0, #8
+ 1837 00c0 2BD0     		beq	.L142
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1838              		.loc 1 744 3 discriminator 7 view .LVU547
+ 1839 00c2 0223     		movs	r3, #2
+ 1840 00c4 84F84730 		strb	r3, [r4, #71]
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1841              		.loc 1 746 3 is_stmt 1 discriminator 7 view .LVU548
+ 1842 00c8 0C28     		cmp	r0, #12
+ 1843 00ca 45D8     		bhi	.L132
+ 1844 00cc 01A3     		adr	r3, .L127
+ 1845 00ce 53F820F0 		ldr	pc, [r3, r0, lsl #2]
+ 1846 00d2 00BF     		.p2align 2
+ 1847              	.L127:
+ 1848 00d4 27000000 		.word	.L121+1
+ARM GAS  /tmp/cc9HXhVl.s 			page 107
+
+
+ 1849 00d8 59010000 		.word	.L132+1
+ 1850 00dc 59010000 		.word	.L132+1
+ 1851 00e0 59010000 		.word	.L132+1
+ 1852 00e4 0F010000 		.word	.L123+1
+ 1853 00e8 59010000 		.word	.L132+1
+ 1854 00ec 59010000 		.word	.L132+1
+ 1855 00f0 59010000 		.word	.L132+1
+ 1856 00f4 21010000 		.word	.L125+1
+ 1857 00f8 59010000 		.word	.L132+1
+ 1858 00fc 59010000 		.word	.L132+1
+ 1859 0100 59010000 		.word	.L132+1
+ 1860 0104 2D010000 		.word	.L126+1
+ 1861              		.p2align 1
+ 1862              	.L141:
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1863              		.loc 1 744 3 is_stmt 0 view .LVU549
+ 1864 0108 0223     		movs	r3, #2
+ 1865 010a 84F84530 		strb	r3, [r4, #69]
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1866              		.loc 1 746 3 is_stmt 1 view .LVU550
+ 1867              	.L123:
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 1868              		.loc 1 758 7 view .LVU551
+ 1869 010e 2268     		ldr	r2, [r4]
+ 1870 0110 D368     		ldr	r3, [r2, #12]
+ 1871 0112 43F00403 		orr	r3, r3, #4
+ 1872 0116 D360     		str	r3, [r2, #12]
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1873              		.loc 1 759 7 view .LVU552
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1874              		.loc 1 782 3 view .LVU553
+ 1875 0118 8AE7     		b	.L128
+ 1876              	.L142:
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1877              		.loc 1 744 3 is_stmt 0 view .LVU554
+ 1878 011a 0223     		movs	r3, #2
+ 1879 011c 84F84630 		strb	r3, [r4, #70]
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1880              		.loc 1 746 3 is_stmt 1 view .LVU555
+ 1881              	.L125:
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 1882              		.loc 1 765 7 view .LVU556
+ 1883 0120 2268     		ldr	r2, [r4]
+ 1884 0122 D368     		ldr	r3, [r2, #12]
+ 1885 0124 43F00803 		orr	r3, r3, #8
+ 1886 0128 D360     		str	r3, [r2, #12]
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1887              		.loc 1 766 7 view .LVU557
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1888              		.loc 1 782 3 view .LVU558
+ 1889 012a 81E7     		b	.L128
+ 1890              	.L126:
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 1891              		.loc 1 773 7 view .LVU559
+ 1892 012c 2268     		ldr	r2, [r4]
+ 1893 012e D368     		ldr	r3, [r2, #12]
+ 1894 0130 43F01003 		orr	r3, r3, #16
+ARM GAS  /tmp/cc9HXhVl.s 			page 108
+
+
+ 1895 0134 D360     		str	r3, [r2, #12]
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 1896              		.loc 1 774 7 view .LVU560
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1897              		.loc 1 782 3 view .LVU561
+ 1898 0136 7BE7     		b	.L128
+ 1899              	.LVL118:
+ 1900              	.L129:
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1901              		.loc 1 796 7 view .LVU562
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1902              		.loc 1 796 31 is_stmt 0 view .LVU563
+ 1903 0138 9968     		ldr	r1, [r3, #8]
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1904              		.loc 1 796 15 view .LVU564
+ 1905 013a 0B4A     		ldr	r2, .L143+4
+ 1906 013c 0A40     		ands	r2, r2, r1
+ 1907              	.LVL119:
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 1908              		.loc 1 797 7 is_stmt 1 view .LVU565
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 1909              		.loc 1 797 10 is_stmt 0 view .LVU566
+ 1910 013e 062A     		cmp	r2, #6
+ 1911 0140 0CD0     		beq	.L133
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 1912              		.loc 1 797 11 discriminator 1 view .LVU567
+ 1913 0142 B2F5803F 		cmp	r2, #65536
+ 1914 0146 0BD0     		beq	.L134
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 1915              		.loc 1 799 9 is_stmt 1 view .LVU568
+ 1916 0148 1A68     		ldr	r2, [r3]
+ 1917              	.LVL120:
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 1918              		.loc 1 799 9 is_stmt 0 view .LVU569
+ 1919 014a 42F00102 		orr	r2, r2, #1
+ 1920 014e 1A60     		str	r2, [r3]
+ 1921 0150 0020     		movs	r0, #0
+ 1922 0152 00E0     		b	.L119
+ 1923              	.LVL121:
+ 1924              	.L131:
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 1925              		.loc 1 740 12 view .LVU570
+ 1926 0154 0120     		movs	r0, #1
+ 1927              	.LVL122:
+ 1928              	.L119:
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1929              		.loc 1 810 1 view .LVU571
+ 1930 0156 10BD     		pop	{r4, pc}
+ 1931              	.LVL123:
+ 1932              	.L132:
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1933              		.loc 1 746 3 view .LVU572
+ 1934 0158 0120     		movs	r0, #1
+ 1935              	.LVL124:
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1936              		.loc 1 746 3 view .LVU573
+ 1937 015a FCE7     		b	.L119
+ARM GAS  /tmp/cc9HXhVl.s 			page 109
+
+
+ 1938              	.LVL125:
+ 1939              	.L133:
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1940              		.loc 1 746 3 view .LVU574
+ 1941 015c 0020     		movs	r0, #0
+ 1942 015e FAE7     		b	.L119
+ 1943              	.L134:
+ 1944 0160 0020     		movs	r0, #0
+ 1945 0162 F8E7     		b	.L119
+ 1946              	.L144:
+ 1947              		.align	2
+ 1948              	.L143:
+ 1949 0164 002C0140 		.word	1073818624
+ 1950 0168 07000100 		.word	65543
+ 1951              		.cfi_endproc
+ 1952              	.LFE341:
+ 1954              		.section	.text.HAL_TIMEx_OCN_Stop_IT,"ax",%progbits
+ 1955              		.align	1
+ 1956              		.global	HAL_TIMEx_OCN_Stop_IT
+ 1957              		.syntax unified
+ 1958              		.thumb
+ 1959              		.thumb_func
+ 1961              	HAL_TIMEx_OCN_Stop_IT:
+ 1962              	.LVL126:
+ 1963              	.LFB342:
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1964              		.loc 1 825 1 is_stmt 1 view -0
+ 1965              		.cfi_startproc
+ 1966              		@ args = 0, pretend = 0, frame = 0
+ 1967              		@ frame_needed = 0, uses_anonymous_args = 0
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1968              		.loc 1 825 1 is_stmt 0 view .LVU576
+ 1969 0000 38B5     		push	{r3, r4, r5, lr}
+ 1970              	.LCFI17:
+ 1971              		.cfi_def_cfa_offset 16
+ 1972              		.cfi_offset 3, -16
+ 1973              		.cfi_offset 4, -12
+ 1974              		.cfi_offset 5, -8
+ 1975              		.cfi_offset 14, -4
+ 1976 0002 0446     		mov	r4, r0
+ 1977 0004 0D46     		mov	r5, r1
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpccer;
+ 1978              		.loc 1 826 3 is_stmt 1 view .LVU577
+ 1979              	.LVL127:
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1980              		.loc 1 827 3 view .LVU578
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 1981              		.loc 1 830 3 view .LVU579
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 1982              		.loc 1 832 3 view .LVU580
+ 1983 0006 0C29     		cmp	r1, #12
+ 1984 0008 65D8     		bhi	.L159
+ 1985 000a DFE801F0 		tbb	[pc, r1]
+ 1986              	.L148:
+ 1987 000e 07       		.byte	(.L151-.L148)/2
+ 1988 000f 64       		.byte	(.L159-.L148)/2
+ 1989 0010 64       		.byte	(.L159-.L148)/2
+ARM GAS  /tmp/cc9HXhVl.s 			page 110
+
+
+ 1990 0011 64       		.byte	(.L159-.L148)/2
+ 1991 0012 3F       		.byte	(.L150-.L148)/2
+ 1992 0013 64       		.byte	(.L159-.L148)/2
+ 1993 0014 64       		.byte	(.L159-.L148)/2
+ 1994 0015 64       		.byte	(.L159-.L148)/2
+ 1995 0016 45       		.byte	(.L149-.L148)/2
+ 1996 0017 64       		.byte	(.L159-.L148)/2
+ 1997 0018 64       		.byte	(.L159-.L148)/2
+ 1998 0019 64       		.byte	(.L159-.L148)/2
+ 1999 001a 4B       		.byte	(.L147-.L148)/2
+ 2000 001b 00       		.p2align 1
+ 2001              	.L151:
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2002              		.loc 1 837 7 view .LVU581
+ 2003 001c 0268     		ldr	r2, [r0]
+ 2004 001e D368     		ldr	r3, [r2, #12]
+ 2005 0020 23F00203 		bic	r3, r3, #2
+ 2006 0024 D360     		str	r3, [r2, #12]
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2007              		.loc 1 838 7 view .LVU582
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2008              		.loc 1 867 3 view .LVU583
+ 2009              	.L152:
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2010              		.loc 1 870 5 view .LVU584
+ 2011 0026 0022     		movs	r2, #0
+ 2012 0028 2946     		mov	r1, r5
+ 2013              	.LVL128:
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2014              		.loc 1 870 5 is_stmt 0 view .LVU585
+ 2015 002a 2068     		ldr	r0, [r4]
+ 2016              	.LVL129:
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2017              		.loc 1 870 5 view .LVU586
+ 2018 002c FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 2019              	.LVL130:
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE  | TIM_CCER_CC4NE)) == (uint32
+ 2020              		.loc 1 873 5 is_stmt 1 view .LVU587
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE  | TIM_CCER_CC4NE)) == (uint32
+ 2021              		.loc 1 873 19 is_stmt 0 view .LVU588
+ 2022 0030 2368     		ldr	r3, [r4]
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE  | TIM_CCER_CC4NE)) == (uint32
+ 2023              		.loc 1 873 13 view .LVU589
+ 2024 0032 196A     		ldr	r1, [r3, #32]
+ 2025              	.LVL131:
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2026              		.loc 1 874 5 is_stmt 1 view .LVU590
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2027              		.loc 1 874 8 is_stmt 0 view .LVU591
+ 2028 0034 44F24442 		movw	r2, #17476
+ 2029 0038 1142     		tst	r1, r2
+ 2030 003a 03D1     		bne	.L153
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2031              		.loc 1 876 7 is_stmt 1 view .LVU592
+ 2032 003c DA68     		ldr	r2, [r3, #12]
+ 2033 003e 22F08002 		bic	r2, r2, #128
+ 2034 0042 DA60     		str	r2, [r3, #12]
+ARM GAS  /tmp/cc9HXhVl.s 			page 111
+
+
+ 2035              	.L153:
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2036              		.loc 1 880 5 view .LVU593
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2037              		.loc 1 880 5 view .LVU594
+ 2038 0044 2368     		ldr	r3, [r4]
+ 2039 0046 196A     		ldr	r1, [r3, #32]
+ 2040              	.LVL132:
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2041              		.loc 1 880 5 is_stmt 0 view .LVU595
+ 2042 0048 41F21112 		movw	r2, #4369
+ 2043 004c 1142     		tst	r1, r2
+ 2044 004e 08D1     		bne	.L154
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2045              		.loc 1 880 5 is_stmt 1 discriminator 1 view .LVU596
+ 2046 0050 196A     		ldr	r1, [r3, #32]
+ 2047 0052 44F24442 		movw	r2, #17476
+ 2048 0056 1142     		tst	r1, r2
+ 2049 0058 03D1     		bne	.L154
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2050              		.loc 1 880 5 discriminator 3 view .LVU597
+ 2051 005a 5A6C     		ldr	r2, [r3, #68]
+ 2052 005c 22F40042 		bic	r2, r2, #32768
+ 2053 0060 5A64     		str	r2, [r3, #68]
+ 2054              	.L154:
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2055              		.loc 1 880 5 discriminator 5 view .LVU598
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2056              		.loc 1 883 5 discriminator 5 view .LVU599
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2057              		.loc 1 883 5 discriminator 5 view .LVU600
+ 2058 0062 2368     		ldr	r3, [r4]
+ 2059 0064 196A     		ldr	r1, [r3, #32]
+ 2060 0066 41F21112 		movw	r2, #4369
+ 2061 006a 1142     		tst	r1, r2
+ 2062 006c 08D1     		bne	.L155
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2063              		.loc 1 883 5 discriminator 1 view .LVU601
+ 2064 006e 196A     		ldr	r1, [r3, #32]
+ 2065 0070 44F24442 		movw	r2, #17476
+ 2066 0074 1142     		tst	r1, r2
+ 2067 0076 03D1     		bne	.L155
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2068              		.loc 1 883 5 discriminator 3 view .LVU602
+ 2069 0078 1A68     		ldr	r2, [r3]
+ 2070 007a 22F00102 		bic	r2, r2, #1
+ 2071 007e 1A60     		str	r2, [r3]
+ 2072              	.L155:
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2073              		.loc 1 883 5 discriminator 5 view .LVU603
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2074              		.loc 1 886 5 discriminator 5 view .LVU604
+ 2075 0080 B5B9     		cbnz	r5, .L156
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2076              		.loc 1 886 5 is_stmt 0 discriminator 1 view .LVU605
+ 2077 0082 0123     		movs	r3, #1
+ 2078 0084 84F84430 		strb	r3, [r4, #68]
+ARM GAS  /tmp/cc9HXhVl.s 			page 112
+
+
+ 2079 0088 0020     		movs	r0, #0
+ 2080 008a 25E0     		b	.L146
+ 2081              	.LVL133:
+ 2082              	.L150:
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2083              		.loc 1 844 7 is_stmt 1 view .LVU606
+ 2084 008c 0268     		ldr	r2, [r0]
+ 2085 008e D368     		ldr	r3, [r2, #12]
+ 2086 0090 23F00403 		bic	r3, r3, #4
+ 2087 0094 D360     		str	r3, [r2, #12]
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2088              		.loc 1 845 7 view .LVU607
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2089              		.loc 1 867 3 view .LVU608
+ 2090 0096 C6E7     		b	.L152
+ 2091              	.L149:
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2092              		.loc 1 851 7 view .LVU609
+ 2093 0098 0268     		ldr	r2, [r0]
+ 2094 009a D368     		ldr	r3, [r2, #12]
+ 2095 009c 23F00803 		bic	r3, r3, #8
+ 2096 00a0 D360     		str	r3, [r2, #12]
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2097              		.loc 1 852 7 view .LVU610
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2098              		.loc 1 867 3 view .LVU611
+ 2099 00a2 C0E7     		b	.L152
+ 2100              	.L147:
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2101              		.loc 1 858 7 view .LVU612
+ 2102 00a4 0268     		ldr	r2, [r0]
+ 2103 00a6 D368     		ldr	r3, [r2, #12]
+ 2104 00a8 23F01003 		bic	r3, r3, #16
+ 2105 00ac D360     		str	r3, [r2, #12]
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2106              		.loc 1 859 7 view .LVU613
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2107              		.loc 1 867 3 view .LVU614
+ 2108 00ae BAE7     		b	.L152
+ 2109              	.LVL134:
+ 2110              	.L156:
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2111              		.loc 1 886 5 is_stmt 0 discriminator 2 view .LVU615
+ 2112 00b0 042D     		cmp	r5, #4
+ 2113 00b2 06D0     		beq	.L161
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2114              		.loc 1 886 5 discriminator 4 view .LVU616
+ 2115 00b4 082D     		cmp	r5, #8
+ 2116 00b6 09D0     		beq	.L162
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2117              		.loc 1 886 5 discriminator 7 view .LVU617
+ 2118 00b8 0123     		movs	r3, #1
+ 2119 00ba 84F84730 		strb	r3, [r4, #71]
+ 2120 00be 0020     		movs	r0, #0
+ 2121 00c0 0AE0     		b	.L146
+ 2122              	.L161:
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ARM GAS  /tmp/cc9HXhVl.s 			page 113
+
+
+ 2123              		.loc 1 886 5 discriminator 3 view .LVU618
+ 2124 00c2 0123     		movs	r3, #1
+ 2125 00c4 84F84530 		strb	r3, [r4, #69]
+ 2126 00c8 0020     		movs	r0, #0
+ 2127 00ca 05E0     		b	.L146
+ 2128              	.L162:
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2129              		.loc 1 886 5 discriminator 6 view .LVU619
+ 2130 00cc 0123     		movs	r3, #1
+ 2131 00ce 84F84630 		strb	r3, [r4, #70]
+ 2132 00d2 0020     		movs	r0, #0
+ 2133 00d4 00E0     		b	.L146
+ 2134              	.LVL135:
+ 2135              	.L159:
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2136              		.loc 1 832 3 view .LVU620
+ 2137 00d6 0120     		movs	r0, #1
+ 2138              	.LVL136:
+ 2139              	.L146:
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 2140              		.loc 1 890 3 is_stmt 1 view .LVU621
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2141              		.loc 1 891 1 is_stmt 0 view .LVU622
+ 2142 00d8 38BD     		pop	{r3, r4, r5, pc}
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2143              		.loc 1 891 1 view .LVU623
+ 2144              		.cfi_endproc
+ 2145              	.LFE342:
+ 2147              		.section	.text.HAL_TIMEx_OCN_Start_DMA,"ax",%progbits
+ 2148              		.align	1
+ 2149              		.global	HAL_TIMEx_OCN_Start_DMA
+ 2150              		.syntax unified
+ 2151              		.thumb
+ 2152              		.thumb_func
+ 2154              	HAL_TIMEx_OCN_Start_DMA:
+ 2155              	.LVL137:
+ 2156              	.LFB343:
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2157              		.loc 1 908 1 is_stmt 1 view -0
+ 2158              		.cfi_startproc
+ 2159              		@ args = 0, pretend = 0, frame = 0
+ 2160              		@ frame_needed = 0, uses_anonymous_args = 0
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2161              		.loc 1 908 1 is_stmt 0 view .LVU625
+ 2162 0000 70B5     		push	{r4, r5, r6, lr}
+ 2163              	.LCFI18:
+ 2164              		.cfi_def_cfa_offset 16
+ 2165              		.cfi_offset 4, -16
+ 2166              		.cfi_offset 5, -12
+ 2167              		.cfi_offset 6, -8
+ 2168              		.cfi_offset 14, -4
+ 2169 0002 0446     		mov	r4, r0
+ 2170 0004 1646     		mov	r6, r2
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 2171              		.loc 1 909 3 is_stmt 1 view .LVU626
+ 2172              	.LVL138:
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 114
+
+
+ 2173              		.loc 1 910 3 view .LVU627
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2174              		.loc 1 913 3 view .LVU628
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2175              		.loc 1 916 3 view .LVU629
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2176              		.loc 1 916 46 is_stmt 0 view .LVU630
+ 2177 0006 0D46     		mov	r5, r1
+ 2178 0008 0029     		cmp	r1, #0
+ 2179 000a 62D1     		bne	.L164
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2180              		.loc 1 916 7 discriminator 1 view .LVU631
+ 2181 000c 90F84400 		ldrb	r0, [r0, #68]	@ zero_extendqisi2
+ 2182              	.LVL139:
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2183              		.loc 1 916 7 discriminator 1 view .LVU632
+ 2184 0010 C0B2     		uxtb	r0, r0
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2185              		.loc 1 916 46 discriminator 1 view .LVU633
+ 2186 0012 0228     		cmp	r0, #2
+ 2187 0014 14BF     		ite	ne
+ 2188 0016 0020     		movne	r0, #0
+ 2189 0018 0120     		moveq	r0, #1
+ 2190              	.L165:
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2191              		.loc 1 916 6 discriminator 12 view .LVU634
+ 2192 001a 0028     		cmp	r0, #0
+ 2193 001c 40F01481 		bne	.L185
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2194              		.loc 1 920 8 is_stmt 1 view .LVU635
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2195              		.loc 1 920 51 is_stmt 0 view .LVU636
+ 2196 0020 002D     		cmp	r5, #0
+ 2197 0022 72D1     		bne	.L169
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2198              		.loc 1 920 12 discriminator 1 view .LVU637
+ 2199 0024 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 2200              	.LVL140:
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2201              		.loc 1 920 12 discriminator 1 view .LVU638
+ 2202 0028 D2B2     		uxtb	r2, r2
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2203              		.loc 1 920 51 discriminator 1 view .LVU639
+ 2204 002a 012A     		cmp	r2, #1
+ 2205 002c 14BF     		ite	ne
+ 2206 002e 0022     		movne	r2, #0
+ 2207 0030 0122     		moveq	r2, #1
+ 2208              	.L170:
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2209              		.loc 1 920 11 discriminator 12 view .LVU640
+ 2210 0032 002A     		cmp	r2, #0
+ 2211 0034 00F00A81 		beq	.L186
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2212              		.loc 1 922 5 is_stmt 1 view .LVU641
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2213              		.loc 1 922 8 is_stmt 0 view .LVU642
+ 2214 0038 002E     		cmp	r6, #0
+ARM GAS  /tmp/cc9HXhVl.s 			page 115
+
+
+ 2215 003a 00F08280 		beq	.L199
+ 2216              	.L173:
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2217              		.loc 1 928 7 is_stmt 1 view .LVU643
+ 2218 003e 002D     		cmp	r5, #0
+ 2219 0040 40F08480 		bne	.L174
+ 2220 0044 0222     		movs	r2, #2
+ 2221 0046 84F84420 		strb	r2, [r4, #68]
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2222              		.loc 1 936 3 view .LVU644
+ 2223              	.L175:
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2224              		.loc 1 941 7 view .LVU645
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2225              		.loc 1 941 17 is_stmt 0 view .LVU646
+ 2226 004a 626A     		ldr	r2, [r4, #36]
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2227              		.loc 1 941 52 view .LVU647
+ 2228 004c 8749     		ldr	r1, .L206
+ 2229              	.LVL141:
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2230              		.loc 1 941 52 view .LVU648
+ 2231 004e D162     		str	r1, [r2, #44]
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2232              		.loc 1 942 7 is_stmt 1 view .LVU649
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2233              		.loc 1 942 17 is_stmt 0 view .LVU650
+ 2234 0050 626A     		ldr	r2, [r4, #36]
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2235              		.loc 1 942 56 view .LVU651
+ 2236 0052 8749     		ldr	r1, .L206+4
+ 2237 0054 1163     		str	r1, [r2, #48]
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2238              		.loc 1 945 7 is_stmt 1 view .LVU652
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2239              		.loc 1 945 17 is_stmt 0 view .LVU653
+ 2240 0056 626A     		ldr	r2, [r4, #36]
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2241              		.loc 1 945 53 view .LVU654
+ 2242 0058 8649     		ldr	r1, .L206+8
+ 2243 005a 5163     		str	r1, [r2, #52]
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2244              		.loc 1 948 7 is_stmt 1 view .LVU655
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2245              		.loc 1 948 88 is_stmt 0 view .LVU656
+ 2246 005c 2268     		ldr	r2, [r4]
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2247              		.loc 1 948 11 view .LVU657
+ 2248 005e 3432     		adds	r2, r2, #52
+ 2249 0060 3146     		mov	r1, r6
+ 2250 0062 606A     		ldr	r0, [r4, #36]
+ 2251 0064 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2252              	.LVL142:
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2253              		.loc 1 948 10 view .LVU658
+ 2254 0068 0028     		cmp	r0, #0
+ 2255 006a 40F0F380 		bne	.L189
+ARM GAS  /tmp/cc9HXhVl.s 			page 116
+
+
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2256              		.loc 1 955 7 is_stmt 1 view .LVU659
+ 2257 006e 2268     		ldr	r2, [r4]
+ 2258 0070 D368     		ldr	r3, [r2, #12]
+ 2259 0072 43F40073 		orr	r3, r3, #512
+ 2260 0076 D360     		str	r3, [r2, #12]
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2261              		.loc 1 956 7 view .LVU660
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2262              		.loc 1 1027 3 view .LVU661
+ 2263              	.L182:
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2264              		.loc 1 1030 5 view .LVU662
+ 2265 0078 0422     		movs	r2, #4
+ 2266 007a 2946     		mov	r1, r5
+ 2267 007c 2068     		ldr	r0, [r4]
+ 2268 007e FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 2269              	.LVL143:
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2270              		.loc 1 1033 5 view .LVU663
+ 2271 0082 2268     		ldr	r2, [r4]
+ 2272 0084 536C     		ldr	r3, [r2, #68]
+ 2273 0086 43F40043 		orr	r3, r3, #32768
+ 2274 008a 5364     		str	r3, [r2, #68]
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2275              		.loc 1 1036 5 view .LVU664
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2276              		.loc 1 1036 9 is_stmt 0 view .LVU665
+ 2277 008c 2368     		ldr	r3, [r4]
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2278              		.loc 1 1036 8 view .LVU666
+ 2279 008e 7A4A     		ldr	r2, .L206+12
+ 2280 0090 9342     		cmp	r3, r2
+ 2281 0092 00F0CB80 		beq	.L183
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2282              		.loc 1 1036 9 discriminator 1 view .LVU667
+ 2283 0096 B3F1804F 		cmp	r3, #1073741824
+ 2284 009a 00F0C780 		beq	.L183
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2285              		.loc 1 1036 9 discriminator 2 view .LVU668
+ 2286 009e A2F59432 		sub	r2, r2, #75776
+ 2287 00a2 9342     		cmp	r3, r2
+ 2288 00a4 00F0C280 		beq	.L183
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2289              		.loc 1 1036 9 discriminator 3 view .LVU669
+ 2290 00a8 02F58062 		add	r2, r2, #1024
+ 2291 00ac 9342     		cmp	r3, r2
+ 2292 00ae 00F0BD80 		beq	.L183
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2293              		.loc 1 1036 9 discriminator 4 view .LVU670
+ 2294 00b2 02F59632 		add	r2, r2, #76800
+ 2295 00b6 9342     		cmp	r3, r2
+ 2296 00b8 00F0B880 		beq	.L183
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2297              		.loc 1 1036 9 discriminator 5 view .LVU671
+ 2298 00bc 02F54062 		add	r2, r2, #3072
+ 2299 00c0 9342     		cmp	r3, r2
+ARM GAS  /tmp/cc9HXhVl.s 			page 117
+
+
+ 2300 00c2 00F0B380 		beq	.L183
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2301              		.loc 1 1046 7 is_stmt 1 view .LVU672
+ 2302 00c6 1A68     		ldr	r2, [r3]
+ 2303 00c8 42F00102 		orr	r2, r2, #1
+ 2304 00cc 1A60     		str	r2, [r3]
+ 2305 00ce 0020     		movs	r0, #0
+ 2306 00d0 BDE0     		b	.L168
+ 2307              	.LVL144:
+ 2308              	.L164:
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2309              		.loc 1 916 46 is_stmt 0 discriminator 2 view .LVU673
+ 2310 00d2 0429     		cmp	r1, #4
+ 2311 00d4 09D0     		beq	.L200
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2312              		.loc 1 916 46 discriminator 5 view .LVU674
+ 2313 00d6 0829     		cmp	r1, #8
+ 2314 00d8 0FD0     		beq	.L201
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2315              		.loc 1 916 7 discriminator 8 view .LVU675
+ 2316 00da 90F84700 		ldrb	r0, [r0, #71]	@ zero_extendqisi2
+ 2317              	.LVL145:
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2318              		.loc 1 916 7 discriminator 8 view .LVU676
+ 2319 00de C0B2     		uxtb	r0, r0
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2320              		.loc 1 916 46 discriminator 8 view .LVU677
+ 2321 00e0 0228     		cmp	r0, #2
+ 2322 00e2 14BF     		ite	ne
+ 2323 00e4 0020     		movne	r0, #0
+ 2324 00e6 0120     		moveq	r0, #1
+ 2325 00e8 97E7     		b	.L165
+ 2326              	.LVL146:
+ 2327              	.L200:
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2328              		.loc 1 916 7 discriminator 4 view .LVU678
+ 2329 00ea 90F84500 		ldrb	r0, [r0, #69]	@ zero_extendqisi2
+ 2330              	.LVL147:
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2331              		.loc 1 916 7 discriminator 4 view .LVU679
+ 2332 00ee C0B2     		uxtb	r0, r0
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2333              		.loc 1 916 46 discriminator 4 view .LVU680
+ 2334 00f0 0228     		cmp	r0, #2
+ 2335 00f2 14BF     		ite	ne
+ 2336 00f4 0020     		movne	r0, #0
+ 2337 00f6 0120     		moveq	r0, #1
+ 2338 00f8 8FE7     		b	.L165
+ 2339              	.LVL148:
+ 2340              	.L201:
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2341              		.loc 1 916 7 discriminator 7 view .LVU681
+ 2342 00fa 90F84600 		ldrb	r0, [r0, #70]	@ zero_extendqisi2
+ 2343              	.LVL149:
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2344              		.loc 1 916 7 discriminator 7 view .LVU682
+ 2345 00fe C0B2     		uxtb	r0, r0
+ARM GAS  /tmp/cc9HXhVl.s 			page 118
+
+
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2346              		.loc 1 916 46 discriminator 7 view .LVU683
+ 2347 0100 0228     		cmp	r0, #2
+ 2348 0102 14BF     		ite	ne
+ 2349 0104 0020     		movne	r0, #0
+ 2350 0106 0120     		moveq	r0, #1
+ 2351 0108 87E7     		b	.L165
+ 2352              	.L169:
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2353              		.loc 1 920 51 discriminator 2 view .LVU684
+ 2354 010a 042D     		cmp	r5, #4
+ 2355 010c 09D0     		beq	.L202
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2356              		.loc 1 920 51 discriminator 5 view .LVU685
+ 2357 010e 082D     		cmp	r5, #8
+ 2358 0110 0FD0     		beq	.L203
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2359              		.loc 1 920 12 discriminator 8 view .LVU686
+ 2360 0112 94F84720 		ldrb	r2, [r4, #71]	@ zero_extendqisi2
+ 2361              	.LVL150:
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2362              		.loc 1 920 12 discriminator 8 view .LVU687
+ 2363 0116 D2B2     		uxtb	r2, r2
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2364              		.loc 1 920 51 discriminator 8 view .LVU688
+ 2365 0118 012A     		cmp	r2, #1
+ 2366 011a 14BF     		ite	ne
+ 2367 011c 0022     		movne	r2, #0
+ 2368 011e 0122     		moveq	r2, #1
+ 2369 0120 87E7     		b	.L170
+ 2370              	.LVL151:
+ 2371              	.L202:
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2372              		.loc 1 920 12 discriminator 4 view .LVU689
+ 2373 0122 94F84520 		ldrb	r2, [r4, #69]	@ zero_extendqisi2
+ 2374              	.LVL152:
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2375              		.loc 1 920 12 discriminator 4 view .LVU690
+ 2376 0126 D2B2     		uxtb	r2, r2
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2377              		.loc 1 920 51 discriminator 4 view .LVU691
+ 2378 0128 012A     		cmp	r2, #1
+ 2379 012a 14BF     		ite	ne
+ 2380 012c 0022     		movne	r2, #0
+ 2381 012e 0122     		moveq	r2, #1
+ 2382 0130 7FE7     		b	.L170
+ 2383              	.LVL153:
+ 2384              	.L203:
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2385              		.loc 1 920 12 discriminator 7 view .LVU692
+ 2386 0132 94F84620 		ldrb	r2, [r4, #70]	@ zero_extendqisi2
+ 2387              	.LVL154:
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2388              		.loc 1 920 12 discriminator 7 view .LVU693
+ 2389 0136 D2B2     		uxtb	r2, r2
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2390              		.loc 1 920 51 discriminator 7 view .LVU694
+ARM GAS  /tmp/cc9HXhVl.s 			page 119
+
+
+ 2391 0138 012A     		cmp	r2, #1
+ 2392 013a 14BF     		ite	ne
+ 2393 013c 0022     		movne	r2, #0
+ 2394 013e 0122     		moveq	r2, #1
+ 2395 0140 77E7     		b	.L170
+ 2396              	.L199:
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 2397              		.loc 1 922 25 discriminator 1 view .LVU695
+ 2398 0142 002B     		cmp	r3, #0
+ 2399 0144 3FF47BAF 		beq	.L173
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2400              		.loc 1 924 14 view .LVU696
+ 2401 0148 0120     		movs	r0, #1
+ 2402 014a 80E0     		b	.L168
+ 2403              	.L174:
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2404              		.loc 1 928 7 discriminator 2 view .LVU697
+ 2405 014c 042D     		cmp	r5, #4
+ 2406 014e 23D0     		beq	.L204
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2407              		.loc 1 928 7 discriminator 4 view .LVU698
+ 2408 0150 082D     		cmp	r5, #8
+ 2409 0152 3BD0     		beq	.L205
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2410              		.loc 1 928 7 discriminator 7 view .LVU699
+ 2411 0154 0222     		movs	r2, #2
+ 2412 0156 84F84720 		strb	r2, [r4, #71]
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2413              		.loc 1 936 3 is_stmt 1 discriminator 7 view .LVU700
+ 2414 015a 0C2D     		cmp	r5, #12
+ 2415 015c 78D8     		bhi	.L188
+ 2416 015e 01A2     		adr	r2, .L181
+ 2417 0160 52F825F0 		ldr	pc, [r2, r5, lsl #2]
+ 2418              		.p2align 2
+ 2419              	.L181:
+ 2420 0164 4B000000 		.word	.L175+1
+ 2421 0168 51020000 		.word	.L188+1
+ 2422 016c 51020000 		.word	.L188+1
+ 2423 0170 51020000 		.word	.L188+1
+ 2424 0174 9F010000 		.word	.L177+1
+ 2425 0178 51020000 		.word	.L188+1
+ 2426 017c 51020000 		.word	.L188+1
+ 2427 0180 51020000 		.word	.L188+1
+ 2428 0184 D3010000 		.word	.L179+1
+ 2429 0188 51020000 		.word	.L188+1
+ 2430 018c 51020000 		.word	.L188+1
+ 2431 0190 51020000 		.word	.L188+1
+ 2432 0194 01020000 		.word	.L180+1
+ 2433              		.p2align 1
+ 2434              	.L204:
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2435              		.loc 1 928 7 is_stmt 0 view .LVU701
+ 2436 0198 0222     		movs	r2, #2
+ 2437 019a 84F84520 		strb	r2, [r4, #69]
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2438              		.loc 1 936 3 is_stmt 1 view .LVU702
+ 2439              	.L177:
+ARM GAS  /tmp/cc9HXhVl.s 			page 120
+
+
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2440              		.loc 1 962 7 view .LVU703
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2441              		.loc 1 962 17 is_stmt 0 view .LVU704
+ 2442 019e A26A     		ldr	r2, [r4, #40]
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2443              		.loc 1 962 52 view .LVU705
+ 2444 01a0 3249     		ldr	r1, .L206
+ 2445              	.LVL155:
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2446              		.loc 1 962 52 view .LVU706
+ 2447 01a2 D162     		str	r1, [r2, #44]
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2448              		.loc 1 963 7 is_stmt 1 view .LVU707
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2449              		.loc 1 963 17 is_stmt 0 view .LVU708
+ 2450 01a4 A26A     		ldr	r2, [r4, #40]
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2451              		.loc 1 963 56 view .LVU709
+ 2452 01a6 3249     		ldr	r1, .L206+4
+ 2453 01a8 1163     		str	r1, [r2, #48]
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2454              		.loc 1 966 7 is_stmt 1 view .LVU710
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2455              		.loc 1 966 17 is_stmt 0 view .LVU711
+ 2456 01aa A26A     		ldr	r2, [r4, #40]
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2457              		.loc 1 966 53 view .LVU712
+ 2458 01ac 3149     		ldr	r1, .L206+8
+ 2459 01ae 5163     		str	r1, [r2, #52]
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2460              		.loc 1 969 7 is_stmt 1 view .LVU713
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2461              		.loc 1 969 88 is_stmt 0 view .LVU714
+ 2462 01b0 2268     		ldr	r2, [r4]
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2463              		.loc 1 969 11 view .LVU715
+ 2464 01b2 3832     		adds	r2, r2, #56
+ 2465 01b4 3146     		mov	r1, r6
+ 2466 01b6 A06A     		ldr	r0, [r4, #40]
+ 2467 01b8 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2468              	.LVL156:
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2469              		.loc 1 969 10 view .LVU716
+ 2470 01bc 0028     		cmp	r0, #0
+ 2471 01be 4BD1     		bne	.L190
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2472              		.loc 1 976 7 is_stmt 1 view .LVU717
+ 2473 01c0 2268     		ldr	r2, [r4]
+ 2474 01c2 D368     		ldr	r3, [r2, #12]
+ 2475 01c4 43F48063 		orr	r3, r3, #1024
+ 2476 01c8 D360     		str	r3, [r2, #12]
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2477              		.loc 1 977 7 view .LVU718
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2478              		.loc 1 1027 3 view .LVU719
+ 2479 01ca 55E7     		b	.L182
+ARM GAS  /tmp/cc9HXhVl.s 			page 121
+
+
+ 2480              	.LVL157:
+ 2481              	.L205:
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2482              		.loc 1 928 7 is_stmt 0 view .LVU720
+ 2483 01cc 0222     		movs	r2, #2
+ 2484 01ce 84F84620 		strb	r2, [r4, #70]
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2485              		.loc 1 936 3 is_stmt 1 view .LVU721
+ 2486              	.L179:
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2487              		.loc 1 983 7 view .LVU722
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2488              		.loc 1 983 17 is_stmt 0 view .LVU723
+ 2489 01d2 E26A     		ldr	r2, [r4, #44]
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2490              		.loc 1 983 52 view .LVU724
+ 2491 01d4 2549     		ldr	r1, .L206
+ 2492              	.LVL158:
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2493              		.loc 1 983 52 view .LVU725
+ 2494 01d6 D162     		str	r1, [r2, #44]
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2495              		.loc 1 984 7 is_stmt 1 view .LVU726
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2496              		.loc 1 984 17 is_stmt 0 view .LVU727
+ 2497 01d8 E26A     		ldr	r2, [r4, #44]
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2498              		.loc 1 984 56 view .LVU728
+ 2499 01da 2549     		ldr	r1, .L206+4
+ 2500 01dc 1163     		str	r1, [r2, #48]
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2501              		.loc 1 987 7 is_stmt 1 view .LVU729
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2502              		.loc 1 987 17 is_stmt 0 view .LVU730
+ 2503 01de E26A     		ldr	r2, [r4, #44]
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2504              		.loc 1 987 53 view .LVU731
+ 2505 01e0 2449     		ldr	r1, .L206+8
+ 2506 01e2 5163     		str	r1, [r2, #52]
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2507              		.loc 1 990 7 is_stmt 1 view .LVU732
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2508              		.loc 1 990 88 is_stmt 0 view .LVU733
+ 2509 01e4 2268     		ldr	r2, [r4]
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2510              		.loc 1 990 11 view .LVU734
+ 2511 01e6 3C32     		adds	r2, r2, #60
+ 2512 01e8 3146     		mov	r1, r6
+ 2513 01ea E06A     		ldr	r0, [r4, #44]
+ 2514 01ec FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2515              	.LVL159:
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2516              		.loc 1 990 10 view .LVU735
+ 2517 01f0 0028     		cmp	r0, #0
+ 2518 01f2 33D1     		bne	.L191
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2519              		.loc 1 997 7 is_stmt 1 view .LVU736
+ARM GAS  /tmp/cc9HXhVl.s 			page 122
+
+
+ 2520 01f4 2268     		ldr	r2, [r4]
+ 2521 01f6 D368     		ldr	r3, [r2, #12]
+ 2522 01f8 43F40063 		orr	r3, r3, #2048
+ 2523 01fc D360     		str	r3, [r2, #12]
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2524              		.loc 1 998 7 view .LVU737
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2525              		.loc 1 1027 3 view .LVU738
+ 2526 01fe 3BE7     		b	.L182
+ 2527              	.LVL160:
+ 2528              	.L180:
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2529              		.loc 1 1004 7 view .LVU739
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2530              		.loc 1 1004 17 is_stmt 0 view .LVU740
+ 2531 0200 226B     		ldr	r2, [r4, #48]
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2532              		.loc 1 1004 52 view .LVU741
+ 2533 0202 1A49     		ldr	r1, .L206
+ 2534              	.LVL161:
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2535              		.loc 1 1004 52 view .LVU742
+ 2536 0204 D162     		str	r1, [r2, #44]
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2537              		.loc 1 1005 7 is_stmt 1 view .LVU743
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2538              		.loc 1 1005 17 is_stmt 0 view .LVU744
+ 2539 0206 226B     		ldr	r2, [r4, #48]
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2540              		.loc 1 1005 56 view .LVU745
+ 2541 0208 1949     		ldr	r1, .L206+4
+ 2542 020a 1163     		str	r1, [r2, #48]
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2543              		.loc 1 1008 7 is_stmt 1 view .LVU746
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2544              		.loc 1 1008 17 is_stmt 0 view .LVU747
+ 2545 020c 226B     		ldr	r2, [r4, #48]
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2546              		.loc 1 1008 53 view .LVU748
+ 2547 020e 1949     		ldr	r1, .L206+8
+ 2548 0210 5163     		str	r1, [r2, #52]
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2549              		.loc 1 1011 7 is_stmt 1 view .LVU749
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2550              		.loc 1 1011 88 is_stmt 0 view .LVU750
+ 2551 0212 2268     		ldr	r2, [r4]
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2552              		.loc 1 1011 11 view .LVU751
+ 2553 0214 4032     		adds	r2, r2, #64
+ 2554 0216 3146     		mov	r1, r6
+ 2555 0218 206B     		ldr	r0, [r4, #48]
+ 2556 021a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2557              	.LVL162:
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2558              		.loc 1 1011 10 view .LVU752
+ 2559 021e F8B9     		cbnz	r0, .L192
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ARM GAS  /tmp/cc9HXhVl.s 			page 123
+
+
+ 2560              		.loc 1 1018 7 is_stmt 1 view .LVU753
+ 2561 0220 2268     		ldr	r2, [r4]
+ 2562 0222 D368     		ldr	r3, [r2, #12]
+ 2563 0224 43F48053 		orr	r3, r3, #4096
+ 2564 0228 D360     		str	r3, [r2, #12]
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2565              		.loc 1 1019 7 view .LVU754
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2566              		.loc 1 1027 3 view .LVU755
+ 2567 022a 25E7     		b	.L182
+ 2568              	.L183:
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 2569              		.loc 1 1038 7 view .LVU756
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 2570              		.loc 1 1038 31 is_stmt 0 view .LVU757
+ 2571 022c 9968     		ldr	r1, [r3, #8]
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 2572              		.loc 1 1038 15 view .LVU758
+ 2573 022e 134A     		ldr	r2, .L206+16
+ 2574 0230 0A40     		ands	r2, r2, r1
+ 2575              	.LVL163:
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 2576              		.loc 1 1039 7 is_stmt 1 view .LVU759
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 2577              		.loc 1 1039 10 is_stmt 0 view .LVU760
+ 2578 0232 062A     		cmp	r2, #6
+ 2579 0234 16D0     		beq	.L193
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 2580              		.loc 1 1039 11 discriminator 1 view .LVU761
+ 2581 0236 B2F5803F 		cmp	r2, #65536
+ 2582 023a 15D0     		beq	.L194
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 2583              		.loc 1 1041 9 is_stmt 1 view .LVU762
+ 2584 023c 1A68     		ldr	r2, [r3]
+ 2585              	.LVL164:
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 2586              		.loc 1 1041 9 is_stmt 0 view .LVU763
+ 2587 023e 42F00102 		orr	r2, r2, #1
+ 2588 0242 1A60     		str	r2, [r3]
+ 2589 0244 0020     		movs	r0, #0
+ 2590 0246 02E0     		b	.L168
+ 2591              	.LVL165:
+ 2592              	.L185:
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2593              		.loc 1 918 12 view .LVU764
+ 2594 0248 0220     		movs	r0, #2
+ 2595 024a 00E0     		b	.L168
+ 2596              	.LVL166:
+ 2597              	.L186:
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2598              		.loc 1 933 12 view .LVU765
+ 2599 024c 0120     		movs	r0, #1
+ 2600              	.LVL167:
+ 2601              	.L168:
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2602              		.loc 1 1052 1 view .LVU766
+ 2603 024e 70BD     		pop	{r4, r5, r6, pc}
+ARM GAS  /tmp/cc9HXhVl.s 			page 124
+
+
+ 2604              	.LVL168:
+ 2605              	.L188:
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2606              		.loc 1 936 3 view .LVU767
+ 2607 0250 0120     		movs	r0, #1
+ 2608 0252 FCE7     		b	.L168
+ 2609              	.LVL169:
+ 2610              	.L189:
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 2611              		.loc 1 952 16 view .LVU768
+ 2612 0254 0120     		movs	r0, #1
+ 2613 0256 FAE7     		b	.L168
+ 2614              	.L190:
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 2615              		.loc 1 973 16 view .LVU769
+ 2616 0258 0120     		movs	r0, #1
+ 2617 025a F8E7     		b	.L168
+ 2618              	.L191:
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 2619              		.loc 1 994 16 view .LVU770
+ 2620 025c 0120     		movs	r0, #1
+ 2621 025e F6E7     		b	.L168
+ 2622              	.L192:
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 2623              		.loc 1 1015 16 view .LVU771
+ 2624 0260 0120     		movs	r0, #1
+ 2625 0262 F4E7     		b	.L168
+ 2626              	.LVL170:
+ 2627              	.L193:
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 2628              		.loc 1 1015 16 view .LVU772
+ 2629 0264 0020     		movs	r0, #0
+ 2630 0266 F2E7     		b	.L168
+ 2631              	.L194:
+ 2632 0268 0020     		movs	r0, #0
+ 2633 026a F0E7     		b	.L168
+ 2634              	.L207:
+ 2635              		.align	2
+ 2636              	.L206:
+ 2637 026c 00000000 		.word	TIM_DMADelayPulseNCplt
+ 2638 0270 00000000 		.word	TIM_DMADelayPulseHalfCplt
+ 2639 0274 00000000 		.word	TIM_DMAErrorCCxN
+ 2640 0278 002C0140 		.word	1073818624
+ 2641 027c 07000100 		.word	65543
+ 2642              		.cfi_endproc
+ 2643              	.LFE343:
+ 2645              		.section	.text.HAL_TIMEx_OCN_Stop_DMA,"ax",%progbits
+ 2646              		.align	1
+ 2647              		.global	HAL_TIMEx_OCN_Stop_DMA
+ 2648              		.syntax unified
+ 2649              		.thumb
+ 2650              		.thumb_func
+ 2652              	HAL_TIMEx_OCN_Stop_DMA:
+ 2653              	.LVL171:
+ 2654              	.LFB344:
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2655              		.loc 1 1067 1 is_stmt 1 view -0
+ARM GAS  /tmp/cc9HXhVl.s 			page 125
+
+
+ 2656              		.cfi_startproc
+ 2657              		@ args = 0, pretend = 0, frame = 0
+ 2658              		@ frame_needed = 0, uses_anonymous_args = 0
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2659              		.loc 1 1067 1 is_stmt 0 view .LVU774
+ 2660 0000 38B5     		push	{r3, r4, r5, lr}
+ 2661              	.LCFI19:
+ 2662              		.cfi_def_cfa_offset 16
+ 2663              		.cfi_offset 3, -16
+ 2664              		.cfi_offset 4, -12
+ 2665              		.cfi_offset 5, -8
+ 2666              		.cfi_offset 14, -4
+ 2667 0002 0446     		mov	r4, r0
+ 2668 0004 0D46     		mov	r5, r1
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2669              		.loc 1 1068 3 is_stmt 1 view .LVU775
+ 2670              	.LVL172:
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2671              		.loc 1 1071 3 view .LVU776
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2672              		.loc 1 1073 3 view .LVU777
+ 2673 0006 0C29     		cmp	r1, #12
+ 2674 0008 67D8     		bhi	.L221
+ 2675 000a DFE801F0 		tbb	[pc, r1]
+ 2676              	.L211:
+ 2677 000e 07       		.byte	(.L214-.L211)/2
+ 2678 000f 66       		.byte	(.L221-.L211)/2
+ 2679 0010 66       		.byte	(.L221-.L211)/2
+ 2680 0011 66       		.byte	(.L221-.L211)/2
+ 2681 0012 38       		.byte	(.L213-.L211)/2
+ 2682 0013 66       		.byte	(.L221-.L211)/2
+ 2683 0014 66       		.byte	(.L221-.L211)/2
+ 2684 0015 66       		.byte	(.L221-.L211)/2
+ 2685 0016 41       		.byte	(.L212-.L211)/2
+ 2686 0017 66       		.byte	(.L221-.L211)/2
+ 2687 0018 66       		.byte	(.L221-.L211)/2
+ 2688 0019 66       		.byte	(.L221-.L211)/2
+ 2689 001a 4A       		.byte	(.L210-.L211)/2
+ 2690 001b 00       		.p2align 1
+ 2691              	.L214:
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 2692              		.loc 1 1078 7 view .LVU778
+ 2693 001c 0268     		ldr	r2, [r0]
+ 2694 001e D368     		ldr	r3, [r2, #12]
+ 2695 0020 23F40073 		bic	r3, r3, #512
+ 2696 0024 D360     		str	r3, [r2, #12]
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2697              		.loc 1 1079 7 view .LVU779
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2698              		.loc 1 1079 13 is_stmt 0 view .LVU780
+ 2699 0026 406A     		ldr	r0, [r0, #36]
+ 2700              	.LVL173:
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2701              		.loc 1 1079 13 view .LVU781
+ 2702 0028 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 2703              	.LVL174:
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ARM GAS  /tmp/cc9HXhVl.s 			page 126
+
+
+ 2704              		.loc 1 1080 7 is_stmt 1 view .LVU782
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2705              		.loc 1 1112 3 view .LVU783
+ 2706              	.L215:
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2707              		.loc 1 1115 5 view .LVU784
+ 2708 002c 0022     		movs	r2, #0
+ 2709 002e 2946     		mov	r1, r5
+ 2710 0030 2068     		ldr	r0, [r4]
+ 2711 0032 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 2712              	.LVL175:
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2713              		.loc 1 1118 5 view .LVU785
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2714              		.loc 1 1118 5 view .LVU786
+ 2715 0036 2368     		ldr	r3, [r4]
+ 2716 0038 196A     		ldr	r1, [r3, #32]
+ 2717 003a 41F21112 		movw	r2, #4369
+ 2718 003e 1142     		tst	r1, r2
+ 2719 0040 08D1     		bne	.L216
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2720              		.loc 1 1118 5 discriminator 1 view .LVU787
+ 2721 0042 196A     		ldr	r1, [r3, #32]
+ 2722 0044 44F24442 		movw	r2, #17476
+ 2723 0048 1142     		tst	r1, r2
+ 2724 004a 03D1     		bne	.L216
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2725              		.loc 1 1118 5 discriminator 3 view .LVU788
+ 2726 004c 5A6C     		ldr	r2, [r3, #68]
+ 2727 004e 22F40042 		bic	r2, r2, #32768
+ 2728 0052 5A64     		str	r2, [r3, #68]
+ 2729              	.L216:
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2730              		.loc 1 1118 5 discriminator 5 view .LVU789
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2731              		.loc 1 1121 5 discriminator 5 view .LVU790
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2732              		.loc 1 1121 5 discriminator 5 view .LVU791
+ 2733 0054 2368     		ldr	r3, [r4]
+ 2734 0056 196A     		ldr	r1, [r3, #32]
+ 2735 0058 41F21112 		movw	r2, #4369
+ 2736 005c 1142     		tst	r1, r2
+ 2737 005e 08D1     		bne	.L217
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2738              		.loc 1 1121 5 discriminator 1 view .LVU792
+ 2739 0060 196A     		ldr	r1, [r3, #32]
+ 2740 0062 44F24442 		movw	r2, #17476
+ 2741 0066 1142     		tst	r1, r2
+ 2742 0068 03D1     		bne	.L217
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2743              		.loc 1 1121 5 discriminator 3 view .LVU793
+ 2744 006a 1A68     		ldr	r2, [r3]
+ 2745 006c 22F00102 		bic	r2, r2, #1
+ 2746 0070 1A60     		str	r2, [r3]
+ 2747              	.L217:
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2748              		.loc 1 1121 5 discriminator 5 view .LVU794
+ARM GAS  /tmp/cc9HXhVl.s 			page 127
+
+
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2749              		.loc 1 1124 5 discriminator 5 view .LVU795
+ 2750 0072 FDB9     		cbnz	r5, .L218
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2751              		.loc 1 1124 5 is_stmt 0 discriminator 1 view .LVU796
+ 2752 0074 0123     		movs	r3, #1
+ 2753 0076 84F84430 		strb	r3, [r4, #68]
+ 2754 007a 0020     		movs	r0, #0
+ 2755 007c 2EE0     		b	.L209
+ 2756              	.LVL176:
+ 2757              	.L213:
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 2758              		.loc 1 1086 7 is_stmt 1 view .LVU797
+ 2759 007e 0268     		ldr	r2, [r0]
+ 2760 0080 D368     		ldr	r3, [r2, #12]
+ 2761 0082 23F48063 		bic	r3, r3, #1024
+ 2762 0086 D360     		str	r3, [r2, #12]
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2763              		.loc 1 1087 7 view .LVU798
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2764              		.loc 1 1087 13 is_stmt 0 view .LVU799
+ 2765 0088 806A     		ldr	r0, [r0, #40]
+ 2766              	.LVL177:
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2767              		.loc 1 1087 13 view .LVU800
+ 2768 008a FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 2769              	.LVL178:
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2770              		.loc 1 1088 7 is_stmt 1 view .LVU801
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2771              		.loc 1 1112 3 view .LVU802
+ 2772 008e CDE7     		b	.L215
+ 2773              	.LVL179:
+ 2774              	.L212:
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ 2775              		.loc 1 1094 7 view .LVU803
+ 2776 0090 0268     		ldr	r2, [r0]
+ 2777 0092 D368     		ldr	r3, [r2, #12]
+ 2778 0094 23F40063 		bic	r3, r3, #2048
+ 2779 0098 D360     		str	r3, [r2, #12]
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2780              		.loc 1 1095 7 view .LVU804
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2781              		.loc 1 1095 13 is_stmt 0 view .LVU805
+ 2782 009a C06A     		ldr	r0, [r0, #44]
+ 2783              	.LVL180:
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2784              		.loc 1 1095 13 view .LVU806
+ 2785 009c FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 2786              	.LVL181:
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2787              		.loc 1 1096 7 is_stmt 1 view .LVU807
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2788              		.loc 1 1112 3 view .LVU808
+ 2789 00a0 C4E7     		b	.L215
+ 2790              	.LVL182:
+ 2791              	.L210:
+ARM GAS  /tmp/cc9HXhVl.s 			page 128
+
+
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ 2792              		.loc 1 1102 7 view .LVU809
+ 2793 00a2 0268     		ldr	r2, [r0]
+ 2794 00a4 D368     		ldr	r3, [r2, #12]
+ 2795 00a6 23F48053 		bic	r3, r3, #4096
+ 2796 00aa D360     		str	r3, [r2, #12]
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2797              		.loc 1 1103 7 view .LVU810
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2798              		.loc 1 1103 13 is_stmt 0 view .LVU811
+ 2799 00ac 006B     		ldr	r0, [r0, #48]
+ 2800              	.LVL183:
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 2801              		.loc 1 1103 13 view .LVU812
+ 2802 00ae FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 2803              	.LVL184:
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 2804              		.loc 1 1104 7 is_stmt 1 view .LVU813
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2805              		.loc 1 1112 3 view .LVU814
+ 2806 00b2 BBE7     		b	.L215
+ 2807              	.L218:
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2808              		.loc 1 1124 5 is_stmt 0 discriminator 2 view .LVU815
+ 2809 00b4 042D     		cmp	r5, #4
+ 2810 00b6 06D0     		beq	.L223
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2811              		.loc 1 1124 5 discriminator 4 view .LVU816
+ 2812 00b8 082D     		cmp	r5, #8
+ 2813 00ba 09D0     		beq	.L224
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2814              		.loc 1 1124 5 discriminator 7 view .LVU817
+ 2815 00bc 0123     		movs	r3, #1
+ 2816 00be 84F84730 		strb	r3, [r4, #71]
+ 2817 00c2 0020     		movs	r0, #0
+ 2818 00c4 0AE0     		b	.L209
+ 2819              	.L223:
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2820              		.loc 1 1124 5 discriminator 3 view .LVU818
+ 2821 00c6 0123     		movs	r3, #1
+ 2822 00c8 84F84530 		strb	r3, [r4, #69]
+ 2823 00cc 0020     		movs	r0, #0
+ 2824 00ce 05E0     		b	.L209
+ 2825              	.L224:
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2826              		.loc 1 1124 5 discriminator 6 view .LVU819
+ 2827 00d0 0123     		movs	r3, #1
+ 2828 00d2 84F84630 		strb	r3, [r4, #70]
+ 2829 00d6 0020     		movs	r0, #0
+ 2830 00d8 00E0     		b	.L209
+ 2831              	.LVL185:
+ 2832              	.L221:
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2833              		.loc 1 1073 3 view .LVU820
+ 2834 00da 0120     		movs	r0, #1
+ 2835              	.LVL186:
+ 2836              	.L209:
+ARM GAS  /tmp/cc9HXhVl.s 			page 129
+
+
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 2837              		.loc 1 1128 3 is_stmt 1 view .LVU821
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2838              		.loc 1 1129 1 is_stmt 0 view .LVU822
+ 2839 00dc 38BD     		pop	{r3, r4, r5, pc}
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2840              		.loc 1 1129 1 view .LVU823
+ 2841              		.cfi_endproc
+ 2842              	.LFE344:
+ 2844              		.section	.text.HAL_TIMEx_PWMN_Start,"ax",%progbits
+ 2845              		.align	1
+ 2846              		.global	HAL_TIMEx_PWMN_Start
+ 2847              		.syntax unified
+ 2848              		.thumb
+ 2849              		.thumb_func
+ 2851              	HAL_TIMEx_PWMN_Start:
+ 2852              	.LVL187:
+ 2853              	.LFB345:
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 2854              		.loc 1 1177 1 is_stmt 1 view -0
+ 2855              		.cfi_startproc
+ 2856              		@ args = 0, pretend = 0, frame = 0
+ 2857              		@ frame_needed = 0, uses_anonymous_args = 0
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 2858              		.loc 1 1177 1 is_stmt 0 view .LVU825
+ 2859 0000 10B5     		push	{r4, lr}
+ 2860              	.LCFI20:
+ 2861              		.cfi_def_cfa_offset 8
+ 2862              		.cfi_offset 4, -8
+ 2863              		.cfi_offset 14, -4
+ 2864 0002 0446     		mov	r4, r0
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2865              		.loc 1 1178 3 is_stmt 1 view .LVU826
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2866              		.loc 1 1181 3 view .LVU827
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2867              		.loc 1 1184 3 view .LVU828
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2868              		.loc 1 1184 46 is_stmt 0 view .LVU829
+ 2869 0004 0846     		mov	r0, r1
+ 2870              	.LVL188:
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2871              		.loc 1 1184 46 view .LVU830
+ 2872 0006 0029     		cmp	r1, #0
+ 2873 0008 33D1     		bne	.L226
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2874              		.loc 1 1184 7 discriminator 1 view .LVU831
+ 2875 000a 94F84430 		ldrb	r3, [r4, #68]	@ zero_extendqisi2
+ 2876 000e DBB2     		uxtb	r3, r3
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2877              		.loc 1 1184 46 discriminator 1 view .LVU832
+ 2878 0010 013B     		subs	r3, r3, #1
+ 2879 0012 18BF     		it	ne
+ 2880 0014 0123     		movne	r3, #1
+ 2881              	.L227:
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2882              		.loc 1 1184 6 discriminator 12 view .LVU833
+ARM GAS  /tmp/cc9HXhVl.s 			page 130
+
+
+ 2883 0016 002B     		cmp	r3, #0
+ 2884 0018 62D1     		bne	.L237
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2885              		.loc 1 1190 3 is_stmt 1 view .LVU834
+ 2886 001a 0028     		cmp	r0, #0
+ 2887 001c 42D1     		bne	.L231
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2888              		.loc 1 1190 3 is_stmt 0 discriminator 1 view .LVU835
+ 2889 001e 0223     		movs	r3, #2
+ 2890 0020 84F84430 		strb	r3, [r4, #68]
+ 2891              	.L232:
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2892              		.loc 1 1193 3 is_stmt 1 view .LVU836
+ 2893 0024 0422     		movs	r2, #4
+ 2894 0026 0146     		mov	r1, r0
+ 2895              	.LVL189:
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2896              		.loc 1 1193 3 is_stmt 0 view .LVU837
+ 2897 0028 2068     		ldr	r0, [r4]
+ 2898              	.LVL190:
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2899              		.loc 1 1193 3 view .LVU838
+ 2900 002a FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 2901              	.LVL191:
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2902              		.loc 1 1196 3 is_stmt 1 view .LVU839
+ 2903 002e 2268     		ldr	r2, [r4]
+ 2904 0030 536C     		ldr	r3, [r2, #68]
+ 2905 0032 43F40043 		orr	r3, r3, #32768
+ 2906 0036 5364     		str	r3, [r2, #68]
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2907              		.loc 1 1199 3 view .LVU840
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2908              		.loc 1 1199 7 is_stmt 0 view .LVU841
+ 2909 0038 2368     		ldr	r3, [r4]
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2910              		.loc 1 1199 6 view .LVU842
+ 2911 003a 2C4A     		ldr	r2, .L245
+ 2912 003c 9342     		cmp	r3, r2
+ 2913 003e 41D0     		beq	.L235
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2914              		.loc 1 1199 7 discriminator 1 view .LVU843
+ 2915 0040 B3F1804F 		cmp	r3, #1073741824
+ 2916 0044 3ED0     		beq	.L235
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2917              		.loc 1 1199 7 discriminator 2 view .LVU844
+ 2918 0046 A2F59432 		sub	r2, r2, #75776
+ 2919 004a 9342     		cmp	r3, r2
+ 2920 004c 3AD0     		beq	.L235
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2921              		.loc 1 1199 7 discriminator 3 view .LVU845
+ 2922 004e 02F58062 		add	r2, r2, #1024
+ 2923 0052 9342     		cmp	r3, r2
+ 2924 0054 36D0     		beq	.L235
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2925              		.loc 1 1199 7 discriminator 4 view .LVU846
+ 2926 0056 02F59632 		add	r2, r2, #76800
+ARM GAS  /tmp/cc9HXhVl.s 			page 131
+
+
+ 2927 005a 9342     		cmp	r3, r2
+ 2928 005c 32D0     		beq	.L235
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2929              		.loc 1 1199 7 discriminator 5 view .LVU847
+ 2930 005e 02F54062 		add	r2, r2, #3072
+ 2931 0062 9342     		cmp	r3, r2
+ 2932 0064 2ED0     		beq	.L235
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 2933              		.loc 1 1209 5 is_stmt 1 view .LVU848
+ 2934 0066 1A68     		ldr	r2, [r3]
+ 2935 0068 42F00102 		orr	r2, r2, #1
+ 2936 006c 1A60     		str	r2, [r3]
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 2937              		.loc 1 1213 10 is_stmt 0 view .LVU849
+ 2938 006e 0020     		movs	r0, #0
+ 2939 0070 37E0     		b	.L230
+ 2940              	.LVL192:
+ 2941              	.L226:
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2942              		.loc 1 1184 46 discriminator 2 view .LVU850
+ 2943 0072 0429     		cmp	r1, #4
+ 2944 0074 08D0     		beq	.L241
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2945              		.loc 1 1184 46 discriminator 5 view .LVU851
+ 2946 0076 0829     		cmp	r1, #8
+ 2947 0078 0DD0     		beq	.L242
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2948              		.loc 1 1184 7 discriminator 8 view .LVU852
+ 2949 007a 94F84730 		ldrb	r3, [r4, #71]	@ zero_extendqisi2
+ 2950 007e DBB2     		uxtb	r3, r3
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2951              		.loc 1 1184 46 discriminator 8 view .LVU853
+ 2952 0080 013B     		subs	r3, r3, #1
+ 2953 0082 18BF     		it	ne
+ 2954 0084 0123     		movne	r3, #1
+ 2955 0086 C6E7     		b	.L227
+ 2956              	.L241:
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2957              		.loc 1 1184 7 discriminator 4 view .LVU854
+ 2958 0088 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 2959 008c DBB2     		uxtb	r3, r3
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2960              		.loc 1 1184 46 discriminator 4 view .LVU855
+ 2961 008e 013B     		subs	r3, r3, #1
+ 2962 0090 18BF     		it	ne
+ 2963 0092 0123     		movne	r3, #1
+ 2964 0094 BFE7     		b	.L227
+ 2965              	.L242:
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2966              		.loc 1 1184 7 discriminator 7 view .LVU856
+ 2967 0096 94F84630 		ldrb	r3, [r4, #70]	@ zero_extendqisi2
+ 2968 009a DBB2     		uxtb	r3, r3
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 2969              		.loc 1 1184 46 discriminator 7 view .LVU857
+ 2970 009c 013B     		subs	r3, r3, #1
+ 2971 009e 18BF     		it	ne
+ 2972 00a0 0123     		movne	r3, #1
+ARM GAS  /tmp/cc9HXhVl.s 			page 132
+
+
+ 2973 00a2 B8E7     		b	.L227
+ 2974              	.L231:
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2975              		.loc 1 1190 3 discriminator 2 view .LVU858
+ 2976 00a4 0428     		cmp	r0, #4
+ 2977 00a6 05D0     		beq	.L243
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2978              		.loc 1 1190 3 discriminator 4 view .LVU859
+ 2979 00a8 0828     		cmp	r0, #8
+ 2980 00aa 07D0     		beq	.L244
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2981              		.loc 1 1190 3 discriminator 7 view .LVU860
+ 2982 00ac 0223     		movs	r3, #2
+ 2983 00ae 84F84730 		strb	r3, [r4, #71]
+ 2984 00b2 B7E7     		b	.L232
+ 2985              	.L243:
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2986              		.loc 1 1190 3 discriminator 3 view .LVU861
+ 2987 00b4 0223     		movs	r3, #2
+ 2988 00b6 84F84530 		strb	r3, [r4, #69]
+ 2989 00ba B3E7     		b	.L232
+ 2990              	.L244:
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 2991              		.loc 1 1190 3 discriminator 6 view .LVU862
+ 2992 00bc 0223     		movs	r3, #2
+ 2993 00be 84F84630 		strb	r3, [r4, #70]
+ 2994 00c2 AFE7     		b	.L232
+ 2995              	.LVL193:
+ 2996              	.L235:
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 2997              		.loc 1 1201 5 is_stmt 1 view .LVU863
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 2998              		.loc 1 1201 29 is_stmt 0 view .LVU864
+ 2999 00c4 9968     		ldr	r1, [r3, #8]
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 3000              		.loc 1 1201 13 view .LVU865
+ 3001 00c6 0A4A     		ldr	r2, .L245+4
+ 3002 00c8 0A40     		ands	r2, r2, r1
+ 3003              	.LVL194:
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3004              		.loc 1 1202 5 is_stmt 1 view .LVU866
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3005              		.loc 1 1202 8 is_stmt 0 view .LVU867
+ 3006 00ca 062A     		cmp	r2, #6
+ 3007 00cc 0AD0     		beq	.L238
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3008              		.loc 1 1202 9 discriminator 1 view .LVU868
+ 3009 00ce B2F5803F 		cmp	r2, #65536
+ 3010 00d2 09D0     		beq	.L239
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3011              		.loc 1 1204 7 is_stmt 1 view .LVU869
+ 3012 00d4 1A68     		ldr	r2, [r3]
+ 3013              	.LVL195:
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3014              		.loc 1 1204 7 is_stmt 0 view .LVU870
+ 3015 00d6 42F00102 		orr	r2, r2, #1
+ 3016 00da 1A60     		str	r2, [r3]
+ARM GAS  /tmp/cc9HXhVl.s 			page 133
+
+
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 3017              		.loc 1 1213 10 view .LVU871
+ 3018 00dc 0020     		movs	r0, #0
+ 3019 00de 00E0     		b	.L230
+ 3020              	.LVL196:
+ 3021              	.L237:
+1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 3022              		.loc 1 1186 12 view .LVU872
+ 3023 00e0 0120     		movs	r0, #1
+ 3024              	.LVL197:
+ 3025              	.L230:
+1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3026              		.loc 1 1214 1 view .LVU873
+ 3027 00e2 10BD     		pop	{r4, pc}
+ 3028              	.LVL198:
+ 3029              	.L238:
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 3030              		.loc 1 1213 10 view .LVU874
+ 3031 00e4 0020     		movs	r0, #0
+ 3032 00e6 FCE7     		b	.L230
+ 3033              	.L239:
+ 3034 00e8 0020     		movs	r0, #0
+ 3035 00ea FAE7     		b	.L230
+ 3036              	.L246:
+ 3037              		.align	2
+ 3038              	.L245:
+ 3039 00ec 002C0140 		.word	1073818624
+ 3040 00f0 07000100 		.word	65543
+ 3041              		.cfi_endproc
+ 3042              	.LFE345:
+ 3044              		.section	.text.HAL_TIMEx_PWMN_Stop,"ax",%progbits
+ 3045              		.align	1
+ 3046              		.global	HAL_TIMEx_PWMN_Stop
+ 3047              		.syntax unified
+ 3048              		.thumb
+ 3049              		.thumb_func
+ 3051              	HAL_TIMEx_PWMN_Stop:
+ 3052              	.LVL199:
+ 3053              	.LFB346:
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 3054              		.loc 1 1228 1 is_stmt 1 view -0
+ 3055              		.cfi_startproc
+ 3056              		@ args = 0, pretend = 0, frame = 0
+ 3057              		@ frame_needed = 0, uses_anonymous_args = 0
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 3058              		.loc 1 1228 1 is_stmt 0 view .LVU876
+ 3059 0000 38B5     		push	{r3, r4, r5, lr}
+ 3060              	.LCFI21:
+ 3061              		.cfi_def_cfa_offset 16
+ 3062              		.cfi_offset 3, -16
+ 3063              		.cfi_offset 4, -12
+ 3064              		.cfi_offset 5, -8
+ 3065              		.cfi_offset 14, -4
+ 3066 0002 0446     		mov	r4, r0
+ 3067 0004 0D46     		mov	r5, r1
+1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3068              		.loc 1 1230 3 is_stmt 1 view .LVU877
+ARM GAS  /tmp/cc9HXhVl.s 			page 134
+
+
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3069              		.loc 1 1233 3 view .LVU878
+ 3070 0006 0022     		movs	r2, #0
+ 3071 0008 0068     		ldr	r0, [r0]
+ 3072              	.LVL200:
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3073              		.loc 1 1233 3 is_stmt 0 view .LVU879
+ 3074 000a FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 3075              	.LVL201:
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3076              		.loc 1 1236 3 is_stmt 1 view .LVU880
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3077              		.loc 1 1236 3 view .LVU881
+ 3078 000e 2368     		ldr	r3, [r4]
+ 3079 0010 196A     		ldr	r1, [r3, #32]
+ 3080 0012 41F21112 		movw	r2, #4369
+ 3081 0016 1142     		tst	r1, r2
+ 3082 0018 08D1     		bne	.L248
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3083              		.loc 1 1236 3 discriminator 1 view .LVU882
+ 3084 001a 196A     		ldr	r1, [r3, #32]
+ 3085 001c 44F24442 		movw	r2, #17476
+ 3086 0020 1142     		tst	r1, r2
+ 3087 0022 03D1     		bne	.L248
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3088              		.loc 1 1236 3 discriminator 3 view .LVU883
+ 3089 0024 5A6C     		ldr	r2, [r3, #68]
+ 3090 0026 22F40042 		bic	r2, r2, #32768
+ 3091 002a 5A64     		str	r2, [r3, #68]
+ 3092              	.L248:
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3093              		.loc 1 1236 3 discriminator 5 view .LVU884
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3094              		.loc 1 1239 3 discriminator 5 view .LVU885
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3095              		.loc 1 1239 3 discriminator 5 view .LVU886
+ 3096 002c 2368     		ldr	r3, [r4]
+ 3097 002e 196A     		ldr	r1, [r3, #32]
+ 3098 0030 41F21112 		movw	r2, #4369
+ 3099 0034 1142     		tst	r1, r2
+ 3100 0036 08D1     		bne	.L249
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3101              		.loc 1 1239 3 discriminator 1 view .LVU887
+ 3102 0038 196A     		ldr	r1, [r3, #32]
+ 3103 003a 44F24442 		movw	r2, #17476
+ 3104 003e 1142     		tst	r1, r2
+ 3105 0040 03D1     		bne	.L249
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3106              		.loc 1 1239 3 discriminator 3 view .LVU888
+ 3107 0042 1A68     		ldr	r2, [r3]
+ 3108 0044 22F00102 		bic	r2, r2, #1
+ 3109 0048 1A60     		str	r2, [r3]
+ 3110              	.L249:
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3111              		.loc 1 1239 3 discriminator 5 view .LVU889
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3112              		.loc 1 1242 3 discriminator 5 view .LVU890
+ARM GAS  /tmp/cc9HXhVl.s 			page 135
+
+
+ 3113 004a 25B9     		cbnz	r5, .L250
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3114              		.loc 1 1242 3 is_stmt 0 discriminator 1 view .LVU891
+ 3115 004c 0123     		movs	r3, #1
+ 3116 004e 84F84430 		strb	r3, [r4, #68]
+ 3117              	.L251:
+1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 3118              		.loc 1 1245 3 is_stmt 1 view .LVU892
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3119              		.loc 1 1246 1 is_stmt 0 view .LVU893
+ 3120 0052 0020     		movs	r0, #0
+ 3121 0054 38BD     		pop	{r3, r4, r5, pc}
+ 3122              	.LVL202:
+ 3123              	.L250:
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3124              		.loc 1 1242 3 discriminator 2 view .LVU894
+ 3125 0056 042D     		cmp	r5, #4
+ 3126 0058 05D0     		beq	.L255
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3127              		.loc 1 1242 3 discriminator 4 view .LVU895
+ 3128 005a 082D     		cmp	r5, #8
+ 3129 005c 07D0     		beq	.L256
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3130              		.loc 1 1242 3 discriminator 7 view .LVU896
+ 3131 005e 0123     		movs	r3, #1
+ 3132 0060 84F84730 		strb	r3, [r4, #71]
+ 3133 0064 F5E7     		b	.L251
+ 3134              	.L255:
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3135              		.loc 1 1242 3 discriminator 3 view .LVU897
+ 3136 0066 0123     		movs	r3, #1
+ 3137 0068 84F84530 		strb	r3, [r4, #69]
+ 3138 006c F1E7     		b	.L251
+ 3139              	.L256:
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3140              		.loc 1 1242 3 discriminator 6 view .LVU898
+ 3141 006e 0123     		movs	r3, #1
+ 3142 0070 84F84630 		strb	r3, [r4, #70]
+ 3143 0074 EDE7     		b	.L251
+ 3144              		.cfi_endproc
+ 3145              	.LFE346:
+ 3147              		.section	.text.HAL_TIMEx_PWMN_Start_IT,"ax",%progbits
+ 3148              		.align	1
+ 3149              		.global	HAL_TIMEx_PWMN_Start_IT
+ 3150              		.syntax unified
+ 3151              		.thumb
+ 3152              		.thumb_func
+ 3154              	HAL_TIMEx_PWMN_Start_IT:
+ 3155              	.LVL203:
+ 3156              	.LFB347:
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3157              		.loc 1 1261 1 is_stmt 1 view -0
+ 3158              		.cfi_startproc
+ 3159              		@ args = 0, pretend = 0, frame = 0
+ 3160              		@ frame_needed = 0, uses_anonymous_args = 0
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3161              		.loc 1 1261 1 is_stmt 0 view .LVU900
+ARM GAS  /tmp/cc9HXhVl.s 			page 136
+
+
+ 3162 0000 10B5     		push	{r4, lr}
+ 3163              	.LCFI22:
+ 3164              		.cfi_def_cfa_offset 8
+ 3165              		.cfi_offset 4, -8
+ 3166              		.cfi_offset 14, -4
+ 3167 0002 0446     		mov	r4, r0
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 3168              		.loc 1 1262 3 is_stmt 1 view .LVU901
+ 3169              	.LVL204:
+1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3170              		.loc 1 1263 3 view .LVU902
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3171              		.loc 1 1266 3 view .LVU903
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3172              		.loc 1 1269 3 view .LVU904
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3173              		.loc 1 1269 46 is_stmt 0 view .LVU905
+ 3174 0004 0846     		mov	r0, r1
+ 3175              	.LVL205:
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3176              		.loc 1 1269 46 view .LVU906
+ 3177 0006 0029     		cmp	r1, #0
+ 3178 0008 3ED1     		bne	.L258
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3179              		.loc 1 1269 7 discriminator 1 view .LVU907
+ 3180 000a 94F84430 		ldrb	r3, [r4, #68]	@ zero_extendqisi2
+ 3181 000e DBB2     		uxtb	r3, r3
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3182              		.loc 1 1269 46 discriminator 1 view .LVU908
+ 3183 0010 013B     		subs	r3, r3, #1
+ 3184 0012 18BF     		it	ne
+ 3185 0014 0123     		movne	r3, #1
+ 3186              	.L259:
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3187              		.loc 1 1269 6 discriminator 12 view .LVU909
+ 3188 0016 002B     		cmp	r3, #0
+ 3189 0018 40F09C80 		bne	.L274
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3190              		.loc 1 1275 3 is_stmt 1 view .LVU910
+ 3191 001c 0028     		cmp	r0, #0
+ 3192 001e 4CD1     		bne	.L263
+ 3193 0020 0223     		movs	r3, #2
+ 3194 0022 84F84430 		strb	r3, [r4, #68]
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3195              		.loc 1 1277 3 view .LVU911
+ 3196              	.L264:
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 3197              		.loc 1 1282 7 view .LVU912
+ 3198 0026 2268     		ldr	r2, [r4]
+ 3199 0028 D368     		ldr	r3, [r2, #12]
+ 3200 002a 43F00203 		orr	r3, r3, #2
+ 3201 002e D360     		str	r3, [r2, #12]
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3202              		.loc 1 1283 7 view .LVU913
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3203              		.loc 1 1312 3 view .LVU914
+ 3204              	.L271:
+ARM GAS  /tmp/cc9HXhVl.s 			page 137
+
+
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3205              		.loc 1 1315 5 view .LVU915
+ 3206 0030 2268     		ldr	r2, [r4]
+ 3207 0032 D368     		ldr	r3, [r2, #12]
+ 3208 0034 43F08003 		orr	r3, r3, #128
+ 3209 0038 D360     		str	r3, [r2, #12]
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3210              		.loc 1 1318 5 view .LVU916
+ 3211 003a 0422     		movs	r2, #4
+ 3212 003c 0146     		mov	r1, r0
+ 3213              	.LVL206:
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3214              		.loc 1 1318 5 is_stmt 0 view .LVU917
+ 3215 003e 2068     		ldr	r0, [r4]
+ 3216              	.LVL207:
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3217              		.loc 1 1318 5 view .LVU918
+ 3218 0040 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 3219              	.LVL208:
+1321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3220              		.loc 1 1321 5 is_stmt 1 view .LVU919
+ 3221 0044 2268     		ldr	r2, [r4]
+ 3222 0046 536C     		ldr	r3, [r2, #68]
+ 3223 0048 43F40043 		orr	r3, r3, #32768
+ 3224 004c 5364     		str	r3, [r2, #68]
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3225              		.loc 1 1324 5 view .LVU920
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3226              		.loc 1 1324 9 is_stmt 0 view .LVU921
+ 3227 004e 2368     		ldr	r3, [r4]
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3228              		.loc 1 1324 8 view .LVU922
+ 3229 0050 444A     		ldr	r2, .L286
+ 3230 0052 9342     		cmp	r3, r2
+ 3231 0054 70D0     		beq	.L272
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3232              		.loc 1 1324 9 discriminator 1 view .LVU923
+ 3233 0056 B3F1804F 		cmp	r3, #1073741824
+ 3234 005a 6DD0     		beq	.L272
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3235              		.loc 1 1324 9 discriminator 2 view .LVU924
+ 3236 005c A2F59432 		sub	r2, r2, #75776
+ 3237 0060 9342     		cmp	r3, r2
+ 3238 0062 69D0     		beq	.L272
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3239              		.loc 1 1324 9 discriminator 3 view .LVU925
+ 3240 0064 02F58062 		add	r2, r2, #1024
+ 3241 0068 9342     		cmp	r3, r2
+ 3242 006a 65D0     		beq	.L272
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3243              		.loc 1 1324 9 discriminator 4 view .LVU926
+ 3244 006c 02F59632 		add	r2, r2, #76800
+ 3245 0070 9342     		cmp	r3, r2
+ 3246 0072 61D0     		beq	.L272
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3247              		.loc 1 1324 9 discriminator 5 view .LVU927
+ 3248 0074 02F54062 		add	r2, r2, #3072
+ARM GAS  /tmp/cc9HXhVl.s 			page 138
+
+
+ 3249 0078 9342     		cmp	r3, r2
+ 3250 007a 5DD0     		beq	.L272
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3251              		.loc 1 1334 7 is_stmt 1 view .LVU928
+ 3252 007c 1A68     		ldr	r2, [r3]
+ 3253 007e 42F00102 		orr	r2, r2, #1
+ 3254 0082 1A60     		str	r2, [r3]
+ 3255 0084 0020     		movs	r0, #0
+ 3256 0086 66E0     		b	.L262
+ 3257              	.LVL209:
+ 3258              	.L258:
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3259              		.loc 1 1269 46 is_stmt 0 discriminator 2 view .LVU929
+ 3260 0088 0429     		cmp	r1, #4
+ 3261 008a 08D0     		beq	.L282
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3262              		.loc 1 1269 46 discriminator 5 view .LVU930
+ 3263 008c 0829     		cmp	r1, #8
+ 3264 008e 0DD0     		beq	.L283
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3265              		.loc 1 1269 7 discriminator 8 view .LVU931
+ 3266 0090 94F84730 		ldrb	r3, [r4, #71]	@ zero_extendqisi2
+ 3267 0094 DBB2     		uxtb	r3, r3
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3268              		.loc 1 1269 46 discriminator 8 view .LVU932
+ 3269 0096 013B     		subs	r3, r3, #1
+ 3270 0098 18BF     		it	ne
+ 3271 009a 0123     		movne	r3, #1
+ 3272 009c BBE7     		b	.L259
+ 3273              	.L282:
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3274              		.loc 1 1269 7 discriminator 4 view .LVU933
+ 3275 009e 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 3276 00a2 DBB2     		uxtb	r3, r3
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3277              		.loc 1 1269 46 discriminator 4 view .LVU934
+ 3278 00a4 013B     		subs	r3, r3, #1
+ 3279 00a6 18BF     		it	ne
+ 3280 00a8 0123     		movne	r3, #1
+ 3281 00aa B4E7     		b	.L259
+ 3282              	.L283:
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3283              		.loc 1 1269 7 discriminator 7 view .LVU935
+ 3284 00ac 94F84630 		ldrb	r3, [r4, #70]	@ zero_extendqisi2
+ 3285 00b0 DBB2     		uxtb	r3, r3
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3286              		.loc 1 1269 46 discriminator 7 view .LVU936
+ 3287 00b2 013B     		subs	r3, r3, #1
+ 3288 00b4 18BF     		it	ne
+ 3289 00b6 0123     		movne	r3, #1
+ 3290 00b8 ADE7     		b	.L259
+ 3291              	.L263:
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3292              		.loc 1 1275 3 discriminator 2 view .LVU937
+ 3293 00ba 0428     		cmp	r0, #4
+ 3294 00bc 24D0     		beq	.L284
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 139
+
+
+ 3295              		.loc 1 1275 3 discriminator 4 view .LVU938
+ 3296 00be 0828     		cmp	r0, #8
+ 3297 00c0 2BD0     		beq	.L285
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3298              		.loc 1 1275 3 discriminator 7 view .LVU939
+ 3299 00c2 0223     		movs	r3, #2
+ 3300 00c4 84F84730 		strb	r3, [r4, #71]
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3301              		.loc 1 1277 3 is_stmt 1 discriminator 7 view .LVU940
+ 3302 00c8 0C28     		cmp	r0, #12
+ 3303 00ca 45D8     		bhi	.L275
+ 3304 00cc 01A3     		adr	r3, .L270
+ 3305 00ce 53F820F0 		ldr	pc, [r3, r0, lsl #2]
+ 3306 00d2 00BF     		.p2align 2
+ 3307              	.L270:
+ 3308 00d4 27000000 		.word	.L264+1
+ 3309 00d8 59010000 		.word	.L275+1
+ 3310 00dc 59010000 		.word	.L275+1
+ 3311 00e0 59010000 		.word	.L275+1
+ 3312 00e4 0F010000 		.word	.L266+1
+ 3313 00e8 59010000 		.word	.L275+1
+ 3314 00ec 59010000 		.word	.L275+1
+ 3315 00f0 59010000 		.word	.L275+1
+ 3316 00f4 21010000 		.word	.L268+1
+ 3317 00f8 59010000 		.word	.L275+1
+ 3318 00fc 59010000 		.word	.L275+1
+ 3319 0100 59010000 		.word	.L275+1
+ 3320 0104 2D010000 		.word	.L269+1
+ 3321              		.p2align 1
+ 3322              	.L284:
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3323              		.loc 1 1275 3 is_stmt 0 view .LVU941
+ 3324 0108 0223     		movs	r3, #2
+ 3325 010a 84F84530 		strb	r3, [r4, #69]
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3326              		.loc 1 1277 3 is_stmt 1 view .LVU942
+ 3327              	.L266:
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 3328              		.loc 1 1289 7 view .LVU943
+ 3329 010e 2268     		ldr	r2, [r4]
+ 3330 0110 D368     		ldr	r3, [r2, #12]
+ 3331 0112 43F00403 		orr	r3, r3, #4
+ 3332 0116 D360     		str	r3, [r2, #12]
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3333              		.loc 1 1290 7 view .LVU944
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3334              		.loc 1 1312 3 view .LVU945
+ 3335 0118 8AE7     		b	.L271
+ 3336              	.L285:
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3337              		.loc 1 1275 3 is_stmt 0 view .LVU946
+ 3338 011a 0223     		movs	r3, #2
+ 3339 011c 84F84630 		strb	r3, [r4, #70]
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3340              		.loc 1 1277 3 is_stmt 1 view .LVU947
+ 3341              	.L268:
+1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ARM GAS  /tmp/cc9HXhVl.s 			page 140
+
+
+ 3342              		.loc 1 1296 7 view .LVU948
+ 3343 0120 2268     		ldr	r2, [r4]
+ 3344 0122 D368     		ldr	r3, [r2, #12]
+ 3345 0124 43F00803 		orr	r3, r3, #8
+ 3346 0128 D360     		str	r3, [r2, #12]
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3347              		.loc 1 1297 7 view .LVU949
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3348              		.loc 1 1312 3 view .LVU950
+ 3349 012a 81E7     		b	.L271
+ 3350              	.L269:
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 3351              		.loc 1 1303 7 view .LVU951
+ 3352 012c 2268     		ldr	r2, [r4]
+ 3353 012e D368     		ldr	r3, [r2, #12]
+ 3354 0130 43F01003 		orr	r3, r3, #16
+ 3355 0134 D360     		str	r3, [r2, #12]
+1304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3356              		.loc 1 1304 7 view .LVU952
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3357              		.loc 1 1312 3 view .LVU953
+ 3358 0136 7BE7     		b	.L271
+ 3359              	.LVL210:
+ 3360              	.L272:
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 3361              		.loc 1 1326 7 view .LVU954
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 3362              		.loc 1 1326 31 is_stmt 0 view .LVU955
+ 3363 0138 9968     		ldr	r1, [r3, #8]
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 3364              		.loc 1 1326 15 view .LVU956
+ 3365 013a 0B4A     		ldr	r2, .L286+4
+ 3366 013c 0A40     		ands	r2, r2, r1
+ 3367              	.LVL211:
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 3368              		.loc 1 1327 7 is_stmt 1 view .LVU957
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 3369              		.loc 1 1327 10 is_stmt 0 view .LVU958
+ 3370 013e 062A     		cmp	r2, #6
+ 3371 0140 0CD0     		beq	.L276
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 3372              		.loc 1 1327 11 discriminator 1 view .LVU959
+ 3373 0142 B2F5803F 		cmp	r2, #65536
+ 3374 0146 0BD0     		beq	.L277
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 3375              		.loc 1 1329 9 is_stmt 1 view .LVU960
+ 3376 0148 1A68     		ldr	r2, [r3]
+ 3377              	.LVL212:
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 3378              		.loc 1 1329 9 is_stmt 0 view .LVU961
+ 3379 014a 42F00102 		orr	r2, r2, #1
+ 3380 014e 1A60     		str	r2, [r3]
+ 3381 0150 0020     		movs	r0, #0
+ 3382 0152 00E0     		b	.L262
+ 3383              	.LVL213:
+ 3384              	.L274:
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ARM GAS  /tmp/cc9HXhVl.s 			page 141
+
+
+ 3385              		.loc 1 1271 12 view .LVU962
+ 3386 0154 0120     		movs	r0, #1
+ 3387              	.LVL214:
+ 3388              	.L262:
+1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3389              		.loc 1 1340 1 view .LVU963
+ 3390 0156 10BD     		pop	{r4, pc}
+ 3391              	.LVL215:
+ 3392              	.L275:
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3393              		.loc 1 1277 3 view .LVU964
+ 3394 0158 0120     		movs	r0, #1
+ 3395              	.LVL216:
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3396              		.loc 1 1277 3 view .LVU965
+ 3397 015a FCE7     		b	.L262
+ 3398              	.LVL217:
+ 3399              	.L276:
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3400              		.loc 1 1277 3 view .LVU966
+ 3401 015c 0020     		movs	r0, #0
+ 3402 015e FAE7     		b	.L262
+ 3403              	.L277:
+ 3404 0160 0020     		movs	r0, #0
+ 3405 0162 F8E7     		b	.L262
+ 3406              	.L287:
+ 3407              		.align	2
+ 3408              	.L286:
+ 3409 0164 002C0140 		.word	1073818624
+ 3410 0168 07000100 		.word	65543
+ 3411              		.cfi_endproc
+ 3412              	.LFE347:
+ 3414              		.section	.text.HAL_TIMEx_PWMN_Stop_IT,"ax",%progbits
+ 3415              		.align	1
+ 3416              		.global	HAL_TIMEx_PWMN_Stop_IT
+ 3417              		.syntax unified
+ 3418              		.thumb
+ 3419              		.thumb_func
+ 3421              	HAL_TIMEx_PWMN_Stop_IT:
+ 3422              	.LVL218:
+ 3423              	.LFB348:
+1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3424              		.loc 1 1355 1 is_stmt 1 view -0
+ 3425              		.cfi_startproc
+ 3426              		@ args = 0, pretend = 0, frame = 0
+ 3427              		@ frame_needed = 0, uses_anonymous_args = 0
+1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3428              		.loc 1 1355 1 is_stmt 0 view .LVU968
+ 3429 0000 38B5     		push	{r3, r4, r5, lr}
+ 3430              	.LCFI23:
+ 3431              		.cfi_def_cfa_offset 16
+ 3432              		.cfi_offset 3, -16
+ 3433              		.cfi_offset 4, -12
+ 3434              		.cfi_offset 5, -8
+ 3435              		.cfi_offset 14, -4
+ 3436 0002 0446     		mov	r4, r0
+ 3437 0004 0D46     		mov	r5, r1
+ARM GAS  /tmp/cc9HXhVl.s 			page 142
+
+
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpccer;
+ 3438              		.loc 1 1356 3 is_stmt 1 view .LVU969
+ 3439              	.LVL219:
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3440              		.loc 1 1357 3 view .LVU970
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3441              		.loc 1 1360 3 view .LVU971
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3442              		.loc 1 1362 3 view .LVU972
+ 3443 0006 0C29     		cmp	r1, #12
+ 3444 0008 65D8     		bhi	.L302
+ 3445 000a DFE801F0 		tbb	[pc, r1]
+ 3446              	.L291:
+ 3447 000e 07       		.byte	(.L294-.L291)/2
+ 3448 000f 64       		.byte	(.L302-.L291)/2
+ 3449 0010 64       		.byte	(.L302-.L291)/2
+ 3450 0011 64       		.byte	(.L302-.L291)/2
+ 3451 0012 3F       		.byte	(.L293-.L291)/2
+ 3452 0013 64       		.byte	(.L302-.L291)/2
+ 3453 0014 64       		.byte	(.L302-.L291)/2
+ 3454 0015 64       		.byte	(.L302-.L291)/2
+ 3455 0016 45       		.byte	(.L292-.L291)/2
+ 3456 0017 64       		.byte	(.L302-.L291)/2
+ 3457 0018 64       		.byte	(.L302-.L291)/2
+ 3458 0019 64       		.byte	(.L302-.L291)/2
+ 3459 001a 4B       		.byte	(.L290-.L291)/2
+ 3460 001b 00       		.p2align 1
+ 3461              	.L294:
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 3462              		.loc 1 1367 7 view .LVU973
+ 3463 001c 0268     		ldr	r2, [r0]
+ 3464 001e D368     		ldr	r3, [r2, #12]
+ 3465 0020 23F00203 		bic	r3, r3, #2
+ 3466 0024 D360     		str	r3, [r2, #12]
+1368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3467              		.loc 1 1368 7 view .LVU974
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3468              		.loc 1 1397 3 view .LVU975
+ 3469              	.L295:
+1400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3470              		.loc 1 1400 5 view .LVU976
+ 3471 0026 0022     		movs	r2, #0
+ 3472 0028 2946     		mov	r1, r5
+ 3473              	.LVL220:
+1400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3474              		.loc 1 1400 5 is_stmt 0 view .LVU977
+ 3475 002a 2068     		ldr	r0, [r4]
+ 3476              	.LVL221:
+1400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3477              		.loc 1 1400 5 view .LVU978
+ 3478 002c FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 3479              	.LVL222:
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE  | TIM_CCER_CC4NE)) == (uint32
+ 3480              		.loc 1 1403 5 is_stmt 1 view .LVU979
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE  | TIM_CCER_CC4NE)) == (uint32
+ 3481              		.loc 1 1403 19 is_stmt 0 view .LVU980
+ 3482 0030 2368     		ldr	r3, [r4]
+ARM GAS  /tmp/cc9HXhVl.s 			page 143
+
+
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE  | TIM_CCER_CC4NE)) == (uint32
+ 3483              		.loc 1 1403 13 view .LVU981
+ 3484 0032 196A     		ldr	r1, [r3, #32]
+ 3485              	.LVL223:
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3486              		.loc 1 1404 5 is_stmt 1 view .LVU982
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3487              		.loc 1 1404 8 is_stmt 0 view .LVU983
+ 3488 0034 44F24442 		movw	r2, #17476
+ 3489 0038 1142     		tst	r1, r2
+ 3490 003a 03D1     		bne	.L296
+1406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3491              		.loc 1 1406 7 is_stmt 1 view .LVU984
+ 3492 003c DA68     		ldr	r2, [r3, #12]
+ 3493 003e 22F08002 		bic	r2, r2, #128
+ 3494 0042 DA60     		str	r2, [r3, #12]
+ 3495              	.L296:
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3496              		.loc 1 1410 5 view .LVU985
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3497              		.loc 1 1410 5 view .LVU986
+ 3498 0044 2368     		ldr	r3, [r4]
+ 3499 0046 196A     		ldr	r1, [r3, #32]
+ 3500              	.LVL224:
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3501              		.loc 1 1410 5 is_stmt 0 view .LVU987
+ 3502 0048 41F21112 		movw	r2, #4369
+ 3503 004c 1142     		tst	r1, r2
+ 3504 004e 08D1     		bne	.L297
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3505              		.loc 1 1410 5 is_stmt 1 discriminator 1 view .LVU988
+ 3506 0050 196A     		ldr	r1, [r3, #32]
+ 3507 0052 44F24442 		movw	r2, #17476
+ 3508 0056 1142     		tst	r1, r2
+ 3509 0058 03D1     		bne	.L297
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3510              		.loc 1 1410 5 discriminator 3 view .LVU989
+ 3511 005a 5A6C     		ldr	r2, [r3, #68]
+ 3512 005c 22F40042 		bic	r2, r2, #32768
+ 3513 0060 5A64     		str	r2, [r3, #68]
+ 3514              	.L297:
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3515              		.loc 1 1410 5 discriminator 5 view .LVU990
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3516              		.loc 1 1413 5 discriminator 5 view .LVU991
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3517              		.loc 1 1413 5 discriminator 5 view .LVU992
+ 3518 0062 2368     		ldr	r3, [r4]
+ 3519 0064 196A     		ldr	r1, [r3, #32]
+ 3520 0066 41F21112 		movw	r2, #4369
+ 3521 006a 1142     		tst	r1, r2
+ 3522 006c 08D1     		bne	.L298
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3523              		.loc 1 1413 5 discriminator 1 view .LVU993
+ 3524 006e 196A     		ldr	r1, [r3, #32]
+ 3525 0070 44F24442 		movw	r2, #17476
+ 3526 0074 1142     		tst	r1, r2
+ARM GAS  /tmp/cc9HXhVl.s 			page 144
+
+
+ 3527 0076 03D1     		bne	.L298
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3528              		.loc 1 1413 5 discriminator 3 view .LVU994
+ 3529 0078 1A68     		ldr	r2, [r3]
+ 3530 007a 22F00102 		bic	r2, r2, #1
+ 3531 007e 1A60     		str	r2, [r3]
+ 3532              	.L298:
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3533              		.loc 1 1413 5 discriminator 5 view .LVU995
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 3534              		.loc 1 1416 5 discriminator 5 view .LVU996
+ 3535 0080 B5B9     		cbnz	r5, .L299
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 3536              		.loc 1 1416 5 is_stmt 0 discriminator 1 view .LVU997
+ 3537 0082 0123     		movs	r3, #1
+ 3538 0084 84F84430 		strb	r3, [r4, #68]
+ 3539 0088 0020     		movs	r0, #0
+ 3540 008a 25E0     		b	.L289
+ 3541              	.LVL225:
+ 3542              	.L293:
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 3543              		.loc 1 1374 7 is_stmt 1 view .LVU998
+ 3544 008c 0268     		ldr	r2, [r0]
+ 3545 008e D368     		ldr	r3, [r2, #12]
+ 3546 0090 23F00403 		bic	r3, r3, #4
+ 3547 0094 D360     		str	r3, [r2, #12]
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3548              		.loc 1 1375 7 view .LVU999
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3549              		.loc 1 1397 3 view .LVU1000
+ 3550 0096 C6E7     		b	.L295
+ 3551              	.L292:
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 3552              		.loc 1 1381 7 view .LVU1001
+ 3553 0098 0268     		ldr	r2, [r0]
+ 3554 009a D368     		ldr	r3, [r2, #12]
+ 3555 009c 23F00803 		bic	r3, r3, #8
+ 3556 00a0 D360     		str	r3, [r2, #12]
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3557              		.loc 1 1382 7 view .LVU1002
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3558              		.loc 1 1397 3 view .LVU1003
+ 3559 00a2 C0E7     		b	.L295
+ 3560              	.L290:
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 3561              		.loc 1 1388 7 view .LVU1004
+ 3562 00a4 0268     		ldr	r2, [r0]
+ 3563 00a6 D368     		ldr	r3, [r2, #12]
+ 3564 00a8 23F01003 		bic	r3, r3, #16
+ 3565 00ac D360     		str	r3, [r2, #12]
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3566              		.loc 1 1389 7 view .LVU1005
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3567              		.loc 1 1397 3 view .LVU1006
+ 3568 00ae BAE7     		b	.L295
+ 3569              	.LVL226:
+ 3570              	.L299:
+ARM GAS  /tmp/cc9HXhVl.s 			page 145
+
+
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 3571              		.loc 1 1416 5 is_stmt 0 discriminator 2 view .LVU1007
+ 3572 00b0 042D     		cmp	r5, #4
+ 3573 00b2 06D0     		beq	.L304
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 3574              		.loc 1 1416 5 discriminator 4 view .LVU1008
+ 3575 00b4 082D     		cmp	r5, #8
+ 3576 00b6 09D0     		beq	.L305
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 3577              		.loc 1 1416 5 discriminator 7 view .LVU1009
+ 3578 00b8 0123     		movs	r3, #1
+ 3579 00ba 84F84730 		strb	r3, [r4, #71]
+ 3580 00be 0020     		movs	r0, #0
+ 3581 00c0 0AE0     		b	.L289
+ 3582              	.L304:
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 3583              		.loc 1 1416 5 discriminator 3 view .LVU1010
+ 3584 00c2 0123     		movs	r3, #1
+ 3585 00c4 84F84530 		strb	r3, [r4, #69]
+ 3586 00c8 0020     		movs	r0, #0
+ 3587 00ca 05E0     		b	.L289
+ 3588              	.L305:
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 3589              		.loc 1 1416 5 discriminator 6 view .LVU1011
+ 3590 00cc 0123     		movs	r3, #1
+ 3591 00ce 84F84630 		strb	r3, [r4, #70]
+ 3592 00d2 0020     		movs	r0, #0
+ 3593 00d4 00E0     		b	.L289
+ 3594              	.LVL227:
+ 3595              	.L302:
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3596              		.loc 1 1362 3 view .LVU1012
+ 3597 00d6 0120     		movs	r0, #1
+ 3598              	.LVL228:
+ 3599              	.L289:
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 3600              		.loc 1 1420 3 is_stmt 1 view .LVU1013
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3601              		.loc 1 1421 1 is_stmt 0 view .LVU1014
+ 3602 00d8 38BD     		pop	{r3, r4, r5, pc}
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3603              		.loc 1 1421 1 view .LVU1015
+ 3604              		.cfi_endproc
+ 3605              	.LFE348:
+ 3607              		.section	.text.HAL_TIMEx_PWMN_Start_DMA,"ax",%progbits
+ 3608              		.align	1
+ 3609              		.global	HAL_TIMEx_PWMN_Start_DMA
+ 3610              		.syntax unified
+ 3611              		.thumb
+ 3612              		.thumb_func
+ 3614              	HAL_TIMEx_PWMN_Start_DMA:
+ 3615              	.LVL229:
+ 3616              	.LFB349:
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3617              		.loc 1 1438 1 is_stmt 1 view -0
+ 3618              		.cfi_startproc
+ 3619              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/cc9HXhVl.s 			page 146
+
+
+ 3620              		@ frame_needed = 0, uses_anonymous_args = 0
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3621              		.loc 1 1438 1 is_stmt 0 view .LVU1017
+ 3622 0000 70B5     		push	{r4, r5, r6, lr}
+ 3623              	.LCFI24:
+ 3624              		.cfi_def_cfa_offset 16
+ 3625              		.cfi_offset 4, -16
+ 3626              		.cfi_offset 5, -12
+ 3627              		.cfi_offset 6, -8
+ 3628              		.cfi_offset 14, -4
+ 3629 0002 0446     		mov	r4, r0
+ 3630 0004 1646     		mov	r6, r2
+1439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 3631              		.loc 1 1439 3 is_stmt 1 view .LVU1018
+ 3632              	.LVL230:
+1440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3633              		.loc 1 1440 3 view .LVU1019
+1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3634              		.loc 1 1443 3 view .LVU1020
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3635              		.loc 1 1446 3 view .LVU1021
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3636              		.loc 1 1446 46 is_stmt 0 view .LVU1022
+ 3637 0006 0D46     		mov	r5, r1
+ 3638 0008 0029     		cmp	r1, #0
+ 3639 000a 62D1     		bne	.L307
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3640              		.loc 1 1446 7 discriminator 1 view .LVU1023
+ 3641 000c 90F84400 		ldrb	r0, [r0, #68]	@ zero_extendqisi2
+ 3642              	.LVL231:
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3643              		.loc 1 1446 7 discriminator 1 view .LVU1024
+ 3644 0010 C0B2     		uxtb	r0, r0
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3645              		.loc 1 1446 46 discriminator 1 view .LVU1025
+ 3646 0012 0228     		cmp	r0, #2
+ 3647 0014 14BF     		ite	ne
+ 3648 0016 0020     		movne	r0, #0
+ 3649 0018 0120     		moveq	r0, #1
+ 3650              	.L308:
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3651              		.loc 1 1446 6 discriminator 12 view .LVU1026
+ 3652 001a 0028     		cmp	r0, #0
+ 3653 001c 40F01481 		bne	.L328
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3654              		.loc 1 1450 8 is_stmt 1 view .LVU1027
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3655              		.loc 1 1450 51 is_stmt 0 view .LVU1028
+ 3656 0020 002D     		cmp	r5, #0
+ 3657 0022 72D1     		bne	.L312
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3658              		.loc 1 1450 12 discriminator 1 view .LVU1029
+ 3659 0024 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 3660              	.LVL232:
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3661              		.loc 1 1450 12 discriminator 1 view .LVU1030
+ 3662 0028 D2B2     		uxtb	r2, r2
+ARM GAS  /tmp/cc9HXhVl.s 			page 147
+
+
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3663              		.loc 1 1450 51 discriminator 1 view .LVU1031
+ 3664 002a 012A     		cmp	r2, #1
+ 3665 002c 14BF     		ite	ne
+ 3666 002e 0022     		movne	r2, #0
+ 3667 0030 0122     		moveq	r2, #1
+ 3668              	.L313:
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3669              		.loc 1 1450 11 discriminator 12 view .LVU1032
+ 3670 0032 002A     		cmp	r2, #0
+ 3671 0034 00F00A81 		beq	.L329
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3672              		.loc 1 1452 5 is_stmt 1 view .LVU1033
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3673              		.loc 1 1452 8 is_stmt 0 view .LVU1034
+ 3674 0038 002E     		cmp	r6, #0
+ 3675 003a 00F08280 		beq	.L342
+ 3676              	.L316:
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3677              		.loc 1 1458 7 is_stmt 1 view .LVU1035
+ 3678 003e 002D     		cmp	r5, #0
+ 3679 0040 40F08480 		bne	.L317
+ 3680 0044 0222     		movs	r2, #2
+ 3681 0046 84F84420 		strb	r2, [r4, #68]
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3682              		.loc 1 1466 3 view .LVU1036
+ 3683              	.L318:
+1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3684              		.loc 1 1471 7 view .LVU1037
+1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3685              		.loc 1 1471 17 is_stmt 0 view .LVU1038
+ 3686 004a 626A     		ldr	r2, [r4, #36]
+1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3687              		.loc 1 1471 52 view .LVU1039
+ 3688 004c 8749     		ldr	r1, .L349
+ 3689              	.LVL233:
+1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3690              		.loc 1 1471 52 view .LVU1040
+ 3691 004e D162     		str	r1, [r2, #44]
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3692              		.loc 1 1472 7 is_stmt 1 view .LVU1041
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3693              		.loc 1 1472 17 is_stmt 0 view .LVU1042
+ 3694 0050 626A     		ldr	r2, [r4, #36]
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3695              		.loc 1 1472 56 view .LVU1043
+ 3696 0052 8749     		ldr	r1, .L349+4
+ 3697 0054 1163     		str	r1, [r2, #48]
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3698              		.loc 1 1475 7 is_stmt 1 view .LVU1044
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3699              		.loc 1 1475 17 is_stmt 0 view .LVU1045
+ 3700 0056 626A     		ldr	r2, [r4, #36]
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3701              		.loc 1 1475 53 view .LVU1046
+ 3702 0058 8649     		ldr	r1, .L349+8
+ 3703 005a 5163     		str	r1, [r2, #52]
+ARM GAS  /tmp/cc9HXhVl.s 			page 148
+
+
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3704              		.loc 1 1478 7 is_stmt 1 view .LVU1047
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3705              		.loc 1 1478 88 is_stmt 0 view .LVU1048
+ 3706 005c 2268     		ldr	r2, [r4]
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3707              		.loc 1 1478 11 view .LVU1049
+ 3708 005e 3432     		adds	r2, r2, #52
+ 3709 0060 3146     		mov	r1, r6
+ 3710 0062 606A     		ldr	r0, [r4, #36]
+ 3711 0064 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3712              	.LVL234:
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3713              		.loc 1 1478 10 view .LVU1050
+ 3714 0068 0028     		cmp	r0, #0
+ 3715 006a 40F0F380 		bne	.L332
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 3716              		.loc 1 1485 7 is_stmt 1 view .LVU1051
+ 3717 006e 2268     		ldr	r2, [r4]
+ 3718 0070 D368     		ldr	r3, [r2, #12]
+ 3719 0072 43F40073 		orr	r3, r3, #512
+ 3720 0076 D360     		str	r3, [r2, #12]
+1486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3721              		.loc 1 1486 7 view .LVU1052
+1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3722              		.loc 1 1557 3 view .LVU1053
+ 3723              	.L325:
+1560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3724              		.loc 1 1560 5 view .LVU1054
+ 3725 0078 0422     		movs	r2, #4
+ 3726 007a 2946     		mov	r1, r5
+ 3727 007c 2068     		ldr	r0, [r4]
+ 3728 007e FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 3729              	.LVL235:
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3730              		.loc 1 1563 5 view .LVU1055
+ 3731 0082 2268     		ldr	r2, [r4]
+ 3732 0084 536C     		ldr	r3, [r2, #68]
+ 3733 0086 43F40043 		orr	r3, r3, #32768
+ 3734 008a 5364     		str	r3, [r2, #68]
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3735              		.loc 1 1566 5 view .LVU1056
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3736              		.loc 1 1566 9 is_stmt 0 view .LVU1057
+ 3737 008c 2368     		ldr	r3, [r4]
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3738              		.loc 1 1566 8 view .LVU1058
+ 3739 008e 7A4A     		ldr	r2, .L349+12
+ 3740 0090 9342     		cmp	r3, r2
+ 3741 0092 00F0CB80 		beq	.L326
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3742              		.loc 1 1566 9 discriminator 1 view .LVU1059
+ 3743 0096 B3F1804F 		cmp	r3, #1073741824
+ 3744 009a 00F0C780 		beq	.L326
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3745              		.loc 1 1566 9 discriminator 2 view .LVU1060
+ 3746 009e A2F59432 		sub	r2, r2, #75776
+ARM GAS  /tmp/cc9HXhVl.s 			page 149
+
+
+ 3747 00a2 9342     		cmp	r3, r2
+ 3748 00a4 00F0C280 		beq	.L326
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3749              		.loc 1 1566 9 discriminator 3 view .LVU1061
+ 3750 00a8 02F58062 		add	r2, r2, #1024
+ 3751 00ac 9342     		cmp	r3, r2
+ 3752 00ae 00F0BD80 		beq	.L326
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3753              		.loc 1 1566 9 discriminator 4 view .LVU1062
+ 3754 00b2 02F59632 		add	r2, r2, #76800
+ 3755 00b6 9342     		cmp	r3, r2
+ 3756 00b8 00F0B880 		beq	.L326
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3757              		.loc 1 1566 9 discriminator 5 view .LVU1063
+ 3758 00bc 02F54062 		add	r2, r2, #3072
+ 3759 00c0 9342     		cmp	r3, r2
+ 3760 00c2 00F0B380 		beq	.L326
+1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3761              		.loc 1 1576 7 is_stmt 1 view .LVU1064
+ 3762 00c6 1A68     		ldr	r2, [r3]
+ 3763 00c8 42F00102 		orr	r2, r2, #1
+ 3764 00cc 1A60     		str	r2, [r3]
+ 3765 00ce 0020     		movs	r0, #0
+ 3766 00d0 BDE0     		b	.L311
+ 3767              	.LVL236:
+ 3768              	.L307:
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3769              		.loc 1 1446 46 is_stmt 0 discriminator 2 view .LVU1065
+ 3770 00d2 0429     		cmp	r1, #4
+ 3771 00d4 09D0     		beq	.L343
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3772              		.loc 1 1446 46 discriminator 5 view .LVU1066
+ 3773 00d6 0829     		cmp	r1, #8
+ 3774 00d8 0FD0     		beq	.L344
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3775              		.loc 1 1446 7 discriminator 8 view .LVU1067
+ 3776 00da 90F84700 		ldrb	r0, [r0, #71]	@ zero_extendqisi2
+ 3777              	.LVL237:
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3778              		.loc 1 1446 7 discriminator 8 view .LVU1068
+ 3779 00de C0B2     		uxtb	r0, r0
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3780              		.loc 1 1446 46 discriminator 8 view .LVU1069
+ 3781 00e0 0228     		cmp	r0, #2
+ 3782 00e2 14BF     		ite	ne
+ 3783 00e4 0020     		movne	r0, #0
+ 3784 00e6 0120     		moveq	r0, #1
+ 3785 00e8 97E7     		b	.L308
+ 3786              	.LVL238:
+ 3787              	.L343:
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3788              		.loc 1 1446 7 discriminator 4 view .LVU1070
+ 3789 00ea 90F84500 		ldrb	r0, [r0, #69]	@ zero_extendqisi2
+ 3790              	.LVL239:
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3791              		.loc 1 1446 7 discriminator 4 view .LVU1071
+ 3792 00ee C0B2     		uxtb	r0, r0
+ARM GAS  /tmp/cc9HXhVl.s 			page 150
+
+
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3793              		.loc 1 1446 46 discriminator 4 view .LVU1072
+ 3794 00f0 0228     		cmp	r0, #2
+ 3795 00f2 14BF     		ite	ne
+ 3796 00f4 0020     		movne	r0, #0
+ 3797 00f6 0120     		moveq	r0, #1
+ 3798 00f8 8FE7     		b	.L308
+ 3799              	.LVL240:
+ 3800              	.L344:
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3801              		.loc 1 1446 7 discriminator 7 view .LVU1073
+ 3802 00fa 90F84600 		ldrb	r0, [r0, #70]	@ zero_extendqisi2
+ 3803              	.LVL241:
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3804              		.loc 1 1446 7 discriminator 7 view .LVU1074
+ 3805 00fe C0B2     		uxtb	r0, r0
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3806              		.loc 1 1446 46 discriminator 7 view .LVU1075
+ 3807 0100 0228     		cmp	r0, #2
+ 3808 0102 14BF     		ite	ne
+ 3809 0104 0020     		movne	r0, #0
+ 3810 0106 0120     		moveq	r0, #1
+ 3811 0108 87E7     		b	.L308
+ 3812              	.L312:
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3813              		.loc 1 1450 51 discriminator 2 view .LVU1076
+ 3814 010a 042D     		cmp	r5, #4
+ 3815 010c 09D0     		beq	.L345
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3816              		.loc 1 1450 51 discriminator 5 view .LVU1077
+ 3817 010e 082D     		cmp	r5, #8
+ 3818 0110 0FD0     		beq	.L346
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3819              		.loc 1 1450 12 discriminator 8 view .LVU1078
+ 3820 0112 94F84720 		ldrb	r2, [r4, #71]	@ zero_extendqisi2
+ 3821              	.LVL242:
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3822              		.loc 1 1450 12 discriminator 8 view .LVU1079
+ 3823 0116 D2B2     		uxtb	r2, r2
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3824              		.loc 1 1450 51 discriminator 8 view .LVU1080
+ 3825 0118 012A     		cmp	r2, #1
+ 3826 011a 14BF     		ite	ne
+ 3827 011c 0022     		movne	r2, #0
+ 3828 011e 0122     		moveq	r2, #1
+ 3829 0120 87E7     		b	.L313
+ 3830              	.LVL243:
+ 3831              	.L345:
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3832              		.loc 1 1450 12 discriminator 4 view .LVU1081
+ 3833 0122 94F84520 		ldrb	r2, [r4, #69]	@ zero_extendqisi2
+ 3834              	.LVL244:
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3835              		.loc 1 1450 12 discriminator 4 view .LVU1082
+ 3836 0126 D2B2     		uxtb	r2, r2
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3837              		.loc 1 1450 51 discriminator 4 view .LVU1083
+ARM GAS  /tmp/cc9HXhVl.s 			page 151
+
+
+ 3838 0128 012A     		cmp	r2, #1
+ 3839 012a 14BF     		ite	ne
+ 3840 012c 0022     		movne	r2, #0
+ 3841 012e 0122     		moveq	r2, #1
+ 3842 0130 7FE7     		b	.L313
+ 3843              	.LVL245:
+ 3844              	.L346:
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3845              		.loc 1 1450 12 discriminator 7 view .LVU1084
+ 3846 0132 94F84620 		ldrb	r2, [r4, #70]	@ zero_extendqisi2
+ 3847              	.LVL246:
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3848              		.loc 1 1450 12 discriminator 7 view .LVU1085
+ 3849 0136 D2B2     		uxtb	r2, r2
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3850              		.loc 1 1450 51 discriminator 7 view .LVU1086
+ 3851 0138 012A     		cmp	r2, #1
+ 3852 013a 14BF     		ite	ne
+ 3853 013c 0022     		movne	r2, #0
+ 3854 013e 0122     		moveq	r2, #1
+ 3855 0140 77E7     		b	.L313
+ 3856              	.L342:
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 3857              		.loc 1 1452 25 discriminator 1 view .LVU1087
+ 3858 0142 002B     		cmp	r3, #0
+ 3859 0144 3FF47BAF 		beq	.L316
+1454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3860              		.loc 1 1454 14 view .LVU1088
+ 3861 0148 0120     		movs	r0, #1
+ 3862 014a 80E0     		b	.L311
+ 3863              	.L317:
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3864              		.loc 1 1458 7 discriminator 2 view .LVU1089
+ 3865 014c 042D     		cmp	r5, #4
+ 3866 014e 23D0     		beq	.L347
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3867              		.loc 1 1458 7 discriminator 4 view .LVU1090
+ 3868 0150 082D     		cmp	r5, #8
+ 3869 0152 3BD0     		beq	.L348
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3870              		.loc 1 1458 7 discriminator 7 view .LVU1091
+ 3871 0154 0222     		movs	r2, #2
+ 3872 0156 84F84720 		strb	r2, [r4, #71]
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3873              		.loc 1 1466 3 is_stmt 1 discriminator 7 view .LVU1092
+ 3874 015a 0C2D     		cmp	r5, #12
+ 3875 015c 78D8     		bhi	.L331
+ 3876 015e 01A2     		adr	r2, .L324
+ 3877 0160 52F825F0 		ldr	pc, [r2, r5, lsl #2]
+ 3878              		.p2align 2
+ 3879              	.L324:
+ 3880 0164 4B000000 		.word	.L318+1
+ 3881 0168 51020000 		.word	.L331+1
+ 3882 016c 51020000 		.word	.L331+1
+ 3883 0170 51020000 		.word	.L331+1
+ 3884 0174 9F010000 		.word	.L320+1
+ 3885 0178 51020000 		.word	.L331+1
+ARM GAS  /tmp/cc9HXhVl.s 			page 152
+
+
+ 3886 017c 51020000 		.word	.L331+1
+ 3887 0180 51020000 		.word	.L331+1
+ 3888 0184 D3010000 		.word	.L322+1
+ 3889 0188 51020000 		.word	.L331+1
+ 3890 018c 51020000 		.word	.L331+1
+ 3891 0190 51020000 		.word	.L331+1
+ 3892 0194 01020000 		.word	.L323+1
+ 3893              		.p2align 1
+ 3894              	.L347:
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3895              		.loc 1 1458 7 is_stmt 0 view .LVU1093
+ 3896 0198 0222     		movs	r2, #2
+ 3897 019a 84F84520 		strb	r2, [r4, #69]
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3898              		.loc 1 1466 3 is_stmt 1 view .LVU1094
+ 3899              	.L320:
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3900              		.loc 1 1492 7 view .LVU1095
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3901              		.loc 1 1492 17 is_stmt 0 view .LVU1096
+ 3902 019e A26A     		ldr	r2, [r4, #40]
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3903              		.loc 1 1492 52 view .LVU1097
+ 3904 01a0 3249     		ldr	r1, .L349
+ 3905              	.LVL247:
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3906              		.loc 1 1492 52 view .LVU1098
+ 3907 01a2 D162     		str	r1, [r2, #44]
+1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3908              		.loc 1 1493 7 is_stmt 1 view .LVU1099
+1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3909              		.loc 1 1493 17 is_stmt 0 view .LVU1100
+ 3910 01a4 A26A     		ldr	r2, [r4, #40]
+1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3911              		.loc 1 1493 56 view .LVU1101
+ 3912 01a6 3249     		ldr	r1, .L349+4
+ 3913 01a8 1163     		str	r1, [r2, #48]
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3914              		.loc 1 1496 7 is_stmt 1 view .LVU1102
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3915              		.loc 1 1496 17 is_stmt 0 view .LVU1103
+ 3916 01aa A26A     		ldr	r2, [r4, #40]
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3917              		.loc 1 1496 53 view .LVU1104
+ 3918 01ac 3149     		ldr	r1, .L349+8
+ 3919 01ae 5163     		str	r1, [r2, #52]
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3920              		.loc 1 1499 7 is_stmt 1 view .LVU1105
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3921              		.loc 1 1499 88 is_stmt 0 view .LVU1106
+ 3922 01b0 2268     		ldr	r2, [r4]
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3923              		.loc 1 1499 11 view .LVU1107
+ 3924 01b2 3832     		adds	r2, r2, #56
+ 3925 01b4 3146     		mov	r1, r6
+ 3926 01b6 A06A     		ldr	r0, [r4, #40]
+ 3927 01b8 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ARM GAS  /tmp/cc9HXhVl.s 			page 153
+
+
+ 3928              	.LVL248:
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3929              		.loc 1 1499 10 view .LVU1108
+ 3930 01bc 0028     		cmp	r0, #0
+ 3931 01be 4BD1     		bne	.L333
+1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 3932              		.loc 1 1506 7 is_stmt 1 view .LVU1109
+ 3933 01c0 2268     		ldr	r2, [r4]
+ 3934 01c2 D368     		ldr	r3, [r2, #12]
+ 3935 01c4 43F48063 		orr	r3, r3, #1024
+ 3936 01c8 D360     		str	r3, [r2, #12]
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3937              		.loc 1 1507 7 view .LVU1110
+1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3938              		.loc 1 1557 3 view .LVU1111
+ 3939 01ca 55E7     		b	.L325
+ 3940              	.LVL249:
+ 3941              	.L348:
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3942              		.loc 1 1458 7 is_stmt 0 view .LVU1112
+ 3943 01cc 0222     		movs	r2, #2
+ 3944 01ce 84F84620 		strb	r2, [r4, #70]
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3945              		.loc 1 1466 3 is_stmt 1 view .LVU1113
+ 3946              	.L322:
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3947              		.loc 1 1513 7 view .LVU1114
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3948              		.loc 1 1513 17 is_stmt 0 view .LVU1115
+ 3949 01d2 E26A     		ldr	r2, [r4, #44]
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3950              		.loc 1 1513 52 view .LVU1116
+ 3951 01d4 2549     		ldr	r1, .L349
+ 3952              	.LVL250:
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3953              		.loc 1 1513 52 view .LVU1117
+ 3954 01d6 D162     		str	r1, [r2, #44]
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3955              		.loc 1 1514 7 is_stmt 1 view .LVU1118
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3956              		.loc 1 1514 17 is_stmt 0 view .LVU1119
+ 3957 01d8 E26A     		ldr	r2, [r4, #44]
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3958              		.loc 1 1514 56 view .LVU1120
+ 3959 01da 2549     		ldr	r1, .L349+4
+ 3960 01dc 1163     		str	r1, [r2, #48]
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3961              		.loc 1 1517 7 is_stmt 1 view .LVU1121
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3962              		.loc 1 1517 17 is_stmt 0 view .LVU1122
+ 3963 01de E26A     		ldr	r2, [r4, #44]
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3964              		.loc 1 1517 53 view .LVU1123
+ 3965 01e0 2449     		ldr	r1, .L349+8
+ 3966 01e2 5163     		str	r1, [r2, #52]
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3967              		.loc 1 1520 7 is_stmt 1 view .LVU1124
+ARM GAS  /tmp/cc9HXhVl.s 			page 154
+
+
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3968              		.loc 1 1520 88 is_stmt 0 view .LVU1125
+ 3969 01e4 2268     		ldr	r2, [r4]
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3970              		.loc 1 1520 11 view .LVU1126
+ 3971 01e6 3C32     		adds	r2, r2, #60
+ 3972 01e8 3146     		mov	r1, r6
+ 3973 01ea E06A     		ldr	r0, [r4, #44]
+ 3974 01ec FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3975              	.LVL251:
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3976              		.loc 1 1520 10 view .LVU1127
+ 3977 01f0 0028     		cmp	r0, #0
+ 3978 01f2 33D1     		bne	.L334
+1527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 3979              		.loc 1 1527 7 is_stmt 1 view .LVU1128
+ 3980 01f4 2268     		ldr	r2, [r4]
+ 3981 01f6 D368     		ldr	r3, [r2, #12]
+ 3982 01f8 43F40063 		orr	r3, r3, #2048
+ 3983 01fc D360     		str	r3, [r2, #12]
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 3984              		.loc 1 1528 7 view .LVU1129
+1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 3985              		.loc 1 1557 3 view .LVU1130
+ 3986 01fe 3BE7     		b	.L325
+ 3987              	.LVL252:
+ 3988              	.L323:
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3989              		.loc 1 1534 7 view .LVU1131
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3990              		.loc 1 1534 17 is_stmt 0 view .LVU1132
+ 3991 0200 226B     		ldr	r2, [r4, #48]
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3992              		.loc 1 1534 52 view .LVU1133
+ 3993 0202 1A49     		ldr	r1, .L349
+ 3994              	.LVL253:
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3995              		.loc 1 1534 52 view .LVU1134
+ 3996 0204 D162     		str	r1, [r2, #44]
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3997              		.loc 1 1535 7 is_stmt 1 view .LVU1135
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 3998              		.loc 1 1535 17 is_stmt 0 view .LVU1136
+ 3999 0206 226B     		ldr	r2, [r4, #48]
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4000              		.loc 1 1535 56 view .LVU1137
+ 4001 0208 1949     		ldr	r1, .L349+4
+ 4002 020a 1163     		str	r1, [r2, #48]
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4003              		.loc 1 1538 7 is_stmt 1 view .LVU1138
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4004              		.loc 1 1538 17 is_stmt 0 view .LVU1139
+ 4005 020c 226B     		ldr	r2, [r4, #48]
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4006              		.loc 1 1538 53 view .LVU1140
+ 4007 020e 1949     		ldr	r1, .L349+8
+ 4008 0210 5163     		str	r1, [r2, #52]
+ARM GAS  /tmp/cc9HXhVl.s 			page 155
+
+
+1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 4009              		.loc 1 1541 7 is_stmt 1 view .LVU1141
+1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 4010              		.loc 1 1541 88 is_stmt 0 view .LVU1142
+ 4011 0212 2268     		ldr	r2, [r4]
+1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 4012              		.loc 1 1541 11 view .LVU1143
+ 4013 0214 4032     		adds	r2, r2, #64
+ 4014 0216 3146     		mov	r1, r6
+ 4015 0218 206B     		ldr	r0, [r4, #48]
+ 4016 021a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 4017              	.LVL254:
+1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 4018              		.loc 1 1541 10 view .LVU1144
+ 4019 021e F8B9     		cbnz	r0, .L335
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 4020              		.loc 1 1548 7 is_stmt 1 view .LVU1145
+ 4021 0220 2268     		ldr	r2, [r4]
+ 4022 0222 D368     		ldr	r3, [r2, #12]
+ 4023 0224 43F48053 		orr	r3, r3, #4096
+ 4024 0228 D360     		str	r3, [r2, #12]
+1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 4025              		.loc 1 1549 7 view .LVU1146
+1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 4026              		.loc 1 1557 3 view .LVU1147
+ 4027 022a 25E7     		b	.L325
+ 4028              	.L326:
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 4029              		.loc 1 1568 7 view .LVU1148
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 4030              		.loc 1 1568 31 is_stmt 0 view .LVU1149
+ 4031 022c 9968     		ldr	r1, [r3, #8]
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 4032              		.loc 1 1568 15 view .LVU1150
+ 4033 022e 134A     		ldr	r2, .L349+16
+ 4034 0230 0A40     		ands	r2, r2, r1
+ 4035              	.LVL255:
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 4036              		.loc 1 1569 7 is_stmt 1 view .LVU1151
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 4037              		.loc 1 1569 10 is_stmt 0 view .LVU1152
+ 4038 0232 062A     		cmp	r2, #6
+ 4039 0234 16D0     		beq	.L336
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 4040              		.loc 1 1569 11 discriminator 1 view .LVU1153
+ 4041 0236 B2F5803F 		cmp	r2, #65536
+ 4042 023a 15D0     		beq	.L337
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 4043              		.loc 1 1571 9 is_stmt 1 view .LVU1154
+ 4044 023c 1A68     		ldr	r2, [r3]
+ 4045              	.LVL256:
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 4046              		.loc 1 1571 9 is_stmt 0 view .LVU1155
+ 4047 023e 42F00102 		orr	r2, r2, #1
+ 4048 0242 1A60     		str	r2, [r3]
+ 4049 0244 0020     		movs	r0, #0
+ 4050 0246 02E0     		b	.L311
+ARM GAS  /tmp/cc9HXhVl.s 			page 156
+
+
+ 4051              	.LVL257:
+ 4052              	.L328:
+1448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4053              		.loc 1 1448 12 view .LVU1156
+ 4054 0248 0220     		movs	r0, #2
+ 4055 024a 00E0     		b	.L311
+ 4056              	.LVL258:
+ 4057              	.L329:
+1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4058              		.loc 1 1463 12 view .LVU1157
+ 4059 024c 0120     		movs	r0, #1
+ 4060              	.LVL259:
+ 4061              	.L311:
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4062              		.loc 1 1582 1 view .LVU1158
+ 4063 024e 70BD     		pop	{r4, r5, r6, pc}
+ 4064              	.LVL260:
+ 4065              	.L331:
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 4066              		.loc 1 1466 3 view .LVU1159
+ 4067 0250 0120     		movs	r0, #1
+ 4068 0252 FCE7     		b	.L311
+ 4069              	.LVL261:
+ 4070              	.L332:
+1482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 4071              		.loc 1 1482 16 view .LVU1160
+ 4072 0254 0120     		movs	r0, #1
+ 4073 0256 FAE7     		b	.L311
+ 4074              	.L333:
+1503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 4075              		.loc 1 1503 16 view .LVU1161
+ 4076 0258 0120     		movs	r0, #1
+ 4077 025a F8E7     		b	.L311
+ 4078              	.L334:
+1524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 4079              		.loc 1 1524 16 view .LVU1162
+ 4080 025c 0120     		movs	r0, #1
+ 4081 025e F6E7     		b	.L311
+ 4082              	.L335:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 4083              		.loc 1 1545 16 view .LVU1163
+ 4084 0260 0120     		movs	r0, #1
+ 4085 0262 F4E7     		b	.L311
+ 4086              	.LVL262:
+ 4087              	.L336:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 4088              		.loc 1 1545 16 view .LVU1164
+ 4089 0264 0020     		movs	r0, #0
+ 4090 0266 F2E7     		b	.L311
+ 4091              	.L337:
+ 4092 0268 0020     		movs	r0, #0
+ 4093 026a F0E7     		b	.L311
+ 4094              	.L350:
+ 4095              		.align	2
+ 4096              	.L349:
+ 4097 026c 00000000 		.word	TIM_DMADelayPulseNCplt
+ 4098 0270 00000000 		.word	TIM_DMADelayPulseHalfCplt
+ARM GAS  /tmp/cc9HXhVl.s 			page 157
+
+
+ 4099 0274 00000000 		.word	TIM_DMAErrorCCxN
+ 4100 0278 002C0140 		.word	1073818624
+ 4101 027c 07000100 		.word	65543
+ 4102              		.cfi_endproc
+ 4103              	.LFE349:
+ 4105              		.section	.text.HAL_TIMEx_PWMN_Stop_DMA,"ax",%progbits
+ 4106              		.align	1
+ 4107              		.global	HAL_TIMEx_PWMN_Stop_DMA
+ 4108              		.syntax unified
+ 4109              		.thumb
+ 4110              		.thumb_func
+ 4112              	HAL_TIMEx_PWMN_Stop_DMA:
+ 4113              	.LVL263:
+ 4114              	.LFB350:
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 4115              		.loc 1 1597 1 is_stmt 1 view -0
+ 4116              		.cfi_startproc
+ 4117              		@ args = 0, pretend = 0, frame = 0
+ 4118              		@ frame_needed = 0, uses_anonymous_args = 0
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 4119              		.loc 1 1597 1 is_stmt 0 view .LVU1166
+ 4120 0000 38B5     		push	{r3, r4, r5, lr}
+ 4121              	.LCFI25:
+ 4122              		.cfi_def_cfa_offset 16
+ 4123              		.cfi_offset 3, -16
+ 4124              		.cfi_offset 4, -12
+ 4125              		.cfi_offset 5, -8
+ 4126              		.cfi_offset 14, -4
+ 4127 0002 0446     		mov	r4, r0
+ 4128 0004 0D46     		mov	r5, r1
+1598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4129              		.loc 1 1598 3 is_stmt 1 view .LVU1167
+ 4130              	.LVL264:
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4131              		.loc 1 1601 3 view .LVU1168
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 4132              		.loc 1 1603 3 view .LVU1169
+ 4133 0006 0C29     		cmp	r1, #12
+ 4134 0008 67D8     		bhi	.L364
+ 4135 000a DFE801F0 		tbb	[pc, r1]
+ 4136              	.L354:
+ 4137 000e 07       		.byte	(.L357-.L354)/2
+ 4138 000f 66       		.byte	(.L364-.L354)/2
+ 4139 0010 66       		.byte	(.L364-.L354)/2
+ 4140 0011 66       		.byte	(.L364-.L354)/2
+ 4141 0012 38       		.byte	(.L356-.L354)/2
+ 4142 0013 66       		.byte	(.L364-.L354)/2
+ 4143 0014 66       		.byte	(.L364-.L354)/2
+ 4144 0015 66       		.byte	(.L364-.L354)/2
+ 4145 0016 41       		.byte	(.L355-.L354)/2
+ 4146 0017 66       		.byte	(.L364-.L354)/2
+ 4147 0018 66       		.byte	(.L364-.L354)/2
+ 4148 0019 66       		.byte	(.L364-.L354)/2
+ 4149 001a 4A       		.byte	(.L353-.L354)/2
+ 4150 001b 00       		.p2align 1
+ 4151              	.L357:
+1608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ARM GAS  /tmp/cc9HXhVl.s 			page 158
+
+
+ 4152              		.loc 1 1608 7 view .LVU1170
+ 4153 001c 0268     		ldr	r2, [r0]
+ 4154 001e D368     		ldr	r3, [r2, #12]
+ 4155 0020 23F40073 		bic	r3, r3, #512
+ 4156 0024 D360     		str	r3, [r2, #12]
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 4157              		.loc 1 1609 7 view .LVU1171
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 4158              		.loc 1 1609 13 is_stmt 0 view .LVU1172
+ 4159 0026 406A     		ldr	r0, [r0, #36]
+ 4160              	.LVL265:
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 4161              		.loc 1 1609 13 view .LVU1173
+ 4162 0028 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 4163              	.LVL266:
+1610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 4164              		.loc 1 1610 7 is_stmt 1 view .LVU1174
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 4165              		.loc 1 1642 3 view .LVU1175
+ 4166              	.L358:
+1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4167              		.loc 1 1645 5 view .LVU1176
+ 4168 002c 0022     		movs	r2, #0
+ 4169 002e 2946     		mov	r1, r5
+ 4170 0030 2068     		ldr	r0, [r4]
+ 4171 0032 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 4172              	.LVL267:
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4173              		.loc 1 1648 5 view .LVU1177
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4174              		.loc 1 1648 5 view .LVU1178
+ 4175 0036 2368     		ldr	r3, [r4]
+ 4176 0038 196A     		ldr	r1, [r3, #32]
+ 4177 003a 41F21112 		movw	r2, #4369
+ 4178 003e 1142     		tst	r1, r2
+ 4179 0040 08D1     		bne	.L359
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4180              		.loc 1 1648 5 discriminator 1 view .LVU1179
+ 4181 0042 196A     		ldr	r1, [r3, #32]
+ 4182 0044 44F24442 		movw	r2, #17476
+ 4183 0048 1142     		tst	r1, r2
+ 4184 004a 03D1     		bne	.L359
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4185              		.loc 1 1648 5 discriminator 3 view .LVU1180
+ 4186 004c 5A6C     		ldr	r2, [r3, #68]
+ 4187 004e 22F40042 		bic	r2, r2, #32768
+ 4188 0052 5A64     		str	r2, [r3, #68]
+ 4189              	.L359:
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4190              		.loc 1 1648 5 discriminator 5 view .LVU1181
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4191              		.loc 1 1651 5 discriminator 5 view .LVU1182
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4192              		.loc 1 1651 5 discriminator 5 view .LVU1183
+ 4193 0054 2368     		ldr	r3, [r4]
+ 4194 0056 196A     		ldr	r1, [r3, #32]
+ 4195 0058 41F21112 		movw	r2, #4369
+ARM GAS  /tmp/cc9HXhVl.s 			page 159
+
+
+ 4196 005c 1142     		tst	r1, r2
+ 4197 005e 08D1     		bne	.L360
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4198              		.loc 1 1651 5 discriminator 1 view .LVU1184
+ 4199 0060 196A     		ldr	r1, [r3, #32]
+ 4200 0062 44F24442 		movw	r2, #17476
+ 4201 0066 1142     		tst	r1, r2
+ 4202 0068 03D1     		bne	.L360
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4203              		.loc 1 1651 5 discriminator 3 view .LVU1185
+ 4204 006a 1A68     		ldr	r2, [r3]
+ 4205 006c 22F00102 		bic	r2, r2, #1
+ 4206 0070 1A60     		str	r2, [r3]
+ 4207              	.L360:
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4208              		.loc 1 1651 5 discriminator 5 view .LVU1186
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4209              		.loc 1 1654 5 discriminator 5 view .LVU1187
+ 4210 0072 FDB9     		cbnz	r5, .L361
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4211              		.loc 1 1654 5 is_stmt 0 discriminator 1 view .LVU1188
+ 4212 0074 0123     		movs	r3, #1
+ 4213 0076 84F84430 		strb	r3, [r4, #68]
+ 4214 007a 0020     		movs	r0, #0
+ 4215 007c 2EE0     		b	.L352
+ 4216              	.LVL268:
+ 4217              	.L356:
+1616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 4218              		.loc 1 1616 7 is_stmt 1 view .LVU1189
+ 4219 007e 0268     		ldr	r2, [r0]
+ 4220 0080 D368     		ldr	r3, [r2, #12]
+ 4221 0082 23F48063 		bic	r3, r3, #1024
+ 4222 0086 D360     		str	r3, [r2, #12]
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 4223              		.loc 1 1617 7 view .LVU1190
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 4224              		.loc 1 1617 13 is_stmt 0 view .LVU1191
+ 4225 0088 806A     		ldr	r0, [r0, #40]
+ 4226              	.LVL269:
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 4227              		.loc 1 1617 13 view .LVU1192
+ 4228 008a FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 4229              	.LVL270:
+1618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 4230              		.loc 1 1618 7 is_stmt 1 view .LVU1193
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 4231              		.loc 1 1642 3 view .LVU1194
+ 4232 008e CDE7     		b	.L358
+ 4233              	.LVL271:
+ 4234              	.L355:
+1624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ 4235              		.loc 1 1624 7 view .LVU1195
+ 4236 0090 0268     		ldr	r2, [r0]
+ 4237 0092 D368     		ldr	r3, [r2, #12]
+ 4238 0094 23F40063 		bic	r3, r3, #2048
+ 4239 0098 D360     		str	r3, [r2, #12]
+1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ARM GAS  /tmp/cc9HXhVl.s 			page 160
+
+
+ 4240              		.loc 1 1625 7 view .LVU1196
+1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 4241              		.loc 1 1625 13 is_stmt 0 view .LVU1197
+ 4242 009a C06A     		ldr	r0, [r0, #44]
+ 4243              	.LVL272:
+1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 4244              		.loc 1 1625 13 view .LVU1198
+ 4245 009c FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 4246              	.LVL273:
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 4247              		.loc 1 1626 7 is_stmt 1 view .LVU1199
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 4248              		.loc 1 1642 3 view .LVU1200
+ 4249 00a0 C4E7     		b	.L358
+ 4250              	.LVL274:
+ 4251              	.L353:
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ 4252              		.loc 1 1632 7 view .LVU1201
+ 4253 00a2 0268     		ldr	r2, [r0]
+ 4254 00a4 D368     		ldr	r3, [r2, #12]
+ 4255 00a6 23F48053 		bic	r3, r3, #4096
+ 4256 00aa D360     		str	r3, [r2, #12]
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 4257              		.loc 1 1633 7 view .LVU1202
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 4258              		.loc 1 1633 13 is_stmt 0 view .LVU1203
+ 4259 00ac 006B     		ldr	r0, [r0, #48]
+ 4260              	.LVL275:
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 4261              		.loc 1 1633 13 view .LVU1204
+ 4262 00ae FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 4263              	.LVL276:
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 4264              		.loc 1 1634 7 is_stmt 1 view .LVU1205
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 4265              		.loc 1 1642 3 view .LVU1206
+ 4266 00b2 BBE7     		b	.L358
+ 4267              	.L361:
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4268              		.loc 1 1654 5 is_stmt 0 discriminator 2 view .LVU1207
+ 4269 00b4 042D     		cmp	r5, #4
+ 4270 00b6 06D0     		beq	.L366
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4271              		.loc 1 1654 5 discriminator 4 view .LVU1208
+ 4272 00b8 082D     		cmp	r5, #8
+ 4273 00ba 09D0     		beq	.L367
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4274              		.loc 1 1654 5 discriminator 7 view .LVU1209
+ 4275 00bc 0123     		movs	r3, #1
+ 4276 00be 84F84730 		strb	r3, [r4, #71]
+ 4277 00c2 0020     		movs	r0, #0
+ 4278 00c4 0AE0     		b	.L352
+ 4279              	.L366:
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4280              		.loc 1 1654 5 discriminator 3 view .LVU1210
+ 4281 00c6 0123     		movs	r3, #1
+ 4282 00c8 84F84530 		strb	r3, [r4, #69]
+ARM GAS  /tmp/cc9HXhVl.s 			page 161
+
+
+ 4283 00cc 0020     		movs	r0, #0
+ 4284 00ce 05E0     		b	.L352
+ 4285              	.L367:
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4286              		.loc 1 1654 5 discriminator 6 view .LVU1211
+ 4287 00d0 0123     		movs	r3, #1
+ 4288 00d2 84F84630 		strb	r3, [r4, #70]
+ 4289 00d6 0020     		movs	r0, #0
+ 4290 00d8 00E0     		b	.L352
+ 4291              	.LVL277:
+ 4292              	.L364:
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 4293              		.loc 1 1603 3 view .LVU1212
+ 4294 00da 0120     		movs	r0, #1
+ 4295              	.LVL278:
+ 4296              	.L352:
+1658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 4297              		.loc 1 1658 3 is_stmt 1 view .LVU1213
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4298              		.loc 1 1659 1 is_stmt 0 view .LVU1214
+ 4299 00dc 38BD     		pop	{r3, r4, r5, pc}
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4300              		.loc 1 1659 1 view .LVU1215
+ 4301              		.cfi_endproc
+ 4302              	.LFE350:
+ 4304              		.section	.text.HAL_TIMEx_OnePulseN_Start,"ax",%progbits
+ 4305              		.align	1
+ 4306              		.global	HAL_TIMEx_OnePulseN_Start
+ 4307              		.syntax unified
+ 4308              		.thumb
+ 4309              		.thumb_func
+ 4311              	HAL_TIMEx_OnePulseN_Start:
+ 4312              	.LVL279:
+ 4313              	.LFB351:
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4314              		.loc 1 1696 1 is_stmt 1 view -0
+ 4315              		.cfi_startproc
+ 4316              		@ args = 0, pretend = 0, frame = 0
+ 4317              		@ frame_needed = 0, uses_anonymous_args = 0
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4318              		.loc 1 1696 1 is_stmt 0 view .LVU1217
+ 4319 0000 38B5     		push	{r3, r4, r5, lr}
+ 4320              	.LCFI26:
+ 4321              		.cfi_def_cfa_offset 16
+ 4322              		.cfi_offset 3, -16
+ 4323              		.cfi_offset 4, -12
+ 4324              		.cfi_offset 5, -8
+ 4325              		.cfi_offset 14, -4
+ 4326 0002 0446     		mov	r4, r0
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 4327              		.loc 1 1697 3 is_stmt 1 view .LVU1218
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 4328              		.loc 1 1697 77 is_stmt 0 view .LVU1219
+ 4329 0004 8E46     		mov	lr, r1
+ 4330 0006 C1B9     		cbnz	r1, .L371
+ 4331 0008 0425     		movs	r5, #4
+ 4332              	.L369:
+ARM GAS  /tmp/cc9HXhVl.s 			page 162
+
+
+ 4333              	.LVL280:
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 4334              		.loc 1 1698 3 is_stmt 1 discriminator 4 view .LVU1220
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 4335              		.loc 1 1698 31 is_stmt 0 discriminator 4 view .LVU1221
+ 4336 000a 94F83E00 		ldrb	r0, [r4, #62]	@ zero_extendqisi2
+ 4337              	.LVL281:
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 4338              		.loc 1 1698 31 discriminator 4 view .LVU1222
+ 4339 000e C0B2     		uxtb	r0, r0
+ 4340              	.LVL282:
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4341              		.loc 1 1699 3 is_stmt 1 discriminator 4 view .LVU1223
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4342              		.loc 1 1699 31 is_stmt 0 discriminator 4 view .LVU1224
+ 4343 0010 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ 4344 0014 DBB2     		uxtb	r3, r3
+ 4345              	.LVL283:
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4346              		.loc 1 1700 3 is_stmt 1 discriminator 4 view .LVU1225
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4347              		.loc 1 1700 31 is_stmt 0 discriminator 4 view .LVU1226
+ 4348 0016 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 4349 001a D2B2     		uxtb	r2, r2
+ 4350              	.LVL284:
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4351              		.loc 1 1701 3 is_stmt 1 discriminator 4 view .LVU1227
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4352              		.loc 1 1701 31 is_stmt 0 discriminator 4 view .LVU1228
+ 4353 001c 94F845C0 		ldrb	ip, [r4, #69]	@ zero_extendqisi2
+ 4354 0020 5FFA8CFC 		uxtb	ip, ip
+ 4355              	.LVL285:
+1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4356              		.loc 1 1704 3 is_stmt 1 discriminator 4 view .LVU1229
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 4357              		.loc 1 1707 3 discriminator 4 view .LVU1230
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 4358              		.loc 1 1707 6 is_stmt 0 discriminator 4 view .LVU1231
+ 4359 0024 0128     		cmp	r0, #1
+ 4360 0026 24D1     		bne	.L372
+1708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 4361              		.loc 1 1708 7 view .LVU1232
+ 4362 0028 012B     		cmp	r3, #1
+ 4363 002a 23D1     		bne	.L370
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 4364              		.loc 1 1709 7 view .LVU1233
+ 4365 002c 012A     		cmp	r2, #1
+ 4366 002e 22D1     		bne	.L373
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 4367              		.loc 1 1710 7 view .LVU1234
+ 4368 0030 BCF1010F 		cmp	ip, #1
+ 4369 0034 03D0     		beq	.L376
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4370              		.loc 1 1712 12 view .LVU1235
+ 4371 0036 1046     		mov	r0, r2
+ 4372              	.LVL286:
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ARM GAS  /tmp/cc9HXhVl.s 			page 163
+
+
+ 4373              		.loc 1 1712 12 view .LVU1236
+ 4374 0038 1CE0     		b	.L370
+ 4375              	.LVL287:
+ 4376              	.L371:
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 4377              		.loc 1 1697 77 view .LVU1237
+ 4378 003a 0025     		movs	r5, #0
+ 4379 003c E5E7     		b	.L369
+ 4380              	.LVL288:
+ 4381              	.L376:
+1716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4382              		.loc 1 1716 3 is_stmt 1 view .LVU1238
+ 4383 003e 0223     		movs	r3, #2
+ 4384              	.LVL289:
+1716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4385              		.loc 1 1716 3 is_stmt 0 view .LVU1239
+ 4386 0040 84F83E30 		strb	r3, [r4, #62]
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4387              		.loc 1 1717 3 is_stmt 1 view .LVU1240
+ 4388 0044 84F83F30 		strb	r3, [r4, #63]
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4389              		.loc 1 1718 3 view .LVU1241
+ 4390 0048 84F84430 		strb	r3, [r4, #68]
+1719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4391              		.loc 1 1719 3 view .LVU1242
+ 4392 004c 84F84530 		strb	r3, [r4, #69]
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4393              		.loc 1 1722 3 view .LVU1243
+ 4394 0050 0422     		movs	r2, #4
+ 4395              	.LVL290:
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4396              		.loc 1 1722 3 is_stmt 0 view .LVU1244
+ 4397 0052 7146     		mov	r1, lr
+ 4398              	.LVL291:
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4399              		.loc 1 1722 3 view .LVU1245
+ 4400 0054 2068     		ldr	r0, [r4]
+ 4401              	.LVL292:
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4402              		.loc 1 1722 3 view .LVU1246
+ 4403 0056 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 4404              	.LVL293:
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4405              		.loc 1 1723 3 is_stmt 1 view .LVU1247
+ 4406 005a 0122     		movs	r2, #1
+ 4407 005c 2946     		mov	r1, r5
+ 4408 005e 2068     		ldr	r0, [r4]
+ 4409 0060 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 4410              	.LVL294:
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4411              		.loc 1 1726 3 view .LVU1248
+ 4412 0064 2268     		ldr	r2, [r4]
+ 4413 0066 536C     		ldr	r3, [r2, #68]
+ 4414 0068 43F40043 		orr	r3, r3, #32768
+ 4415 006c 5364     		str	r3, [r2, #68]
+1729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 4416              		.loc 1 1729 3 view .LVU1249
+ARM GAS  /tmp/cc9HXhVl.s 			page 164
+
+
+1729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 4417              		.loc 1 1729 10 is_stmt 0 view .LVU1250
+ 4418 006e 0020     		movs	r0, #0
+ 4419 0070 00E0     		b	.L370
+ 4420              	.LVL295:
+ 4421              	.L372:
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4422              		.loc 1 1712 12 view .LVU1251
+ 4423 0072 0120     		movs	r0, #1
+ 4424              	.LVL296:
+ 4425              	.L370:
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4426              		.loc 1 1730 1 view .LVU1252
+ 4427 0074 38BD     		pop	{r3, r4, r5, pc}
+ 4428              	.LVL297:
+ 4429              	.L373:
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4430              		.loc 1 1712 12 view .LVU1253
+ 4431 0076 1846     		mov	r0, r3
+ 4432              	.LVL298:
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4433              		.loc 1 1712 12 view .LVU1254
+ 4434 0078 FCE7     		b	.L370
+ 4435              		.cfi_endproc
+ 4436              	.LFE351:
+ 4438              		.section	.text.HAL_TIMEx_OnePulseN_Stop,"ax",%progbits
+ 4439              		.align	1
+ 4440              		.global	HAL_TIMEx_OnePulseN_Stop
+ 4441              		.syntax unified
+ 4442              		.thumb
+ 4443              		.thumb_func
+ 4445              	HAL_TIMEx_OnePulseN_Stop:
+ 4446              	.LVL299:
+ 4447              	.LFB352:
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4448              		.loc 1 1745 1 is_stmt 1 view -0
+ 4449              		.cfi_startproc
+ 4450              		@ args = 0, pretend = 0, frame = 0
+ 4451              		@ frame_needed = 0, uses_anonymous_args = 0
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4452              		.loc 1 1745 1 is_stmt 0 view .LVU1256
+ 4453 0000 38B5     		push	{r3, r4, r5, lr}
+ 4454              	.LCFI27:
+ 4455              		.cfi_def_cfa_offset 16
+ 4456              		.cfi_offset 3, -16
+ 4457              		.cfi_offset 4, -12
+ 4458              		.cfi_offset 5, -8
+ 4459              		.cfi_offset 14, -4
+ 4460 0002 0446     		mov	r4, r0
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4461              		.loc 1 1746 3 is_stmt 1 view .LVU1257
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4462              		.loc 1 1746 77 is_stmt 0 view .LVU1258
+ 4463 0004 0029     		cmp	r1, #0
+ 4464 0006 32D1     		bne	.L381
+ 4465 0008 0425     		movs	r5, #4
+ 4466              	.L378:
+ARM GAS  /tmp/cc9HXhVl.s 			page 165
+
+
+ 4467              	.LVL300:
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4468              		.loc 1 1749 3 is_stmt 1 discriminator 4 view .LVU1259
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+ 4469              		.loc 1 1752 3 discriminator 4 view .LVU1260
+ 4470 000a 0022     		movs	r2, #0
+ 4471 000c 2068     		ldr	r0, [r4]
+ 4472              	.LVL301:
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+ 4473              		.loc 1 1752 3 is_stmt 0 discriminator 4 view .LVU1261
+ 4474 000e FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 4475              	.LVL302:
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4476              		.loc 1 1753 3 is_stmt 1 discriminator 4 view .LVU1262
+ 4477 0012 0022     		movs	r2, #0
+ 4478 0014 2946     		mov	r1, r5
+ 4479 0016 2068     		ldr	r0, [r4]
+ 4480 0018 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 4481              	.LVL303:
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4482              		.loc 1 1756 3 discriminator 4 view .LVU1263
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4483              		.loc 1 1756 3 discriminator 4 view .LVU1264
+ 4484 001c 2368     		ldr	r3, [r4]
+ 4485 001e 196A     		ldr	r1, [r3, #32]
+ 4486 0020 41F21112 		movw	r2, #4369
+ 4487 0024 1142     		tst	r1, r2
+ 4488 0026 08D1     		bne	.L379
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4489              		.loc 1 1756 3 discriminator 1 view .LVU1265
+ 4490 0028 196A     		ldr	r1, [r3, #32]
+ 4491 002a 44F24442 		movw	r2, #17476
+ 4492 002e 1142     		tst	r1, r2
+ 4493 0030 03D1     		bne	.L379
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4494              		.loc 1 1756 3 discriminator 3 view .LVU1266
+ 4495 0032 5A6C     		ldr	r2, [r3, #68]
+ 4496 0034 22F40042 		bic	r2, r2, #32768
+ 4497 0038 5A64     		str	r2, [r3, #68]
+ 4498              	.L379:
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4499              		.loc 1 1756 3 discriminator 5 view .LVU1267
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4500              		.loc 1 1759 3 discriminator 5 view .LVU1268
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4501              		.loc 1 1759 3 discriminator 5 view .LVU1269
+ 4502 003a 2368     		ldr	r3, [r4]
+ 4503 003c 196A     		ldr	r1, [r3, #32]
+ 4504 003e 41F21112 		movw	r2, #4369
+ 4505 0042 1142     		tst	r1, r2
+ 4506 0044 08D1     		bne	.L380
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4507              		.loc 1 1759 3 discriminator 1 view .LVU1270
+ 4508 0046 196A     		ldr	r1, [r3, #32]
+ 4509 0048 44F24442 		movw	r2, #17476
+ 4510 004c 1142     		tst	r1, r2
+ 4511 004e 03D1     		bne	.L380
+ARM GAS  /tmp/cc9HXhVl.s 			page 166
+
+
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4512              		.loc 1 1759 3 discriminator 3 view .LVU1271
+ 4513 0050 1A68     		ldr	r2, [r3]
+ 4514 0052 22F00102 		bic	r2, r2, #1
+ 4515 0056 1A60     		str	r2, [r3]
+ 4516              	.L380:
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4517              		.loc 1 1759 3 discriminator 5 view .LVU1272
+1762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 4518              		.loc 1 1762 3 discriminator 5 view .LVU1273
+ 4519 0058 0123     		movs	r3, #1
+ 4520 005a 84F83E30 		strb	r3, [r4, #62]
+1763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 4521              		.loc 1 1763 3 discriminator 5 view .LVU1274
+ 4522 005e 84F83F30 		strb	r3, [r4, #63]
+1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 4523              		.loc 1 1764 3 discriminator 5 view .LVU1275
+ 4524 0062 84F84430 		strb	r3, [r4, #68]
+1765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4525              		.loc 1 1765 3 discriminator 5 view .LVU1276
+ 4526 0066 84F84530 		strb	r3, [r4, #69]
+1768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 4527              		.loc 1 1768 3 discriminator 5 view .LVU1277
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4528              		.loc 1 1769 1 is_stmt 0 discriminator 5 view .LVU1278
+ 4529 006a 0020     		movs	r0, #0
+ 4530 006c 38BD     		pop	{r3, r4, r5, pc}
+ 4531              	.LVL304:
+ 4532              	.L381:
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4533              		.loc 1 1746 77 view .LVU1279
+ 4534 006e 0025     		movs	r5, #0
+ 4535 0070 CBE7     		b	.L378
+ 4536              		.cfi_endproc
+ 4537              	.LFE352:
+ 4539              		.section	.text.HAL_TIMEx_OnePulseN_Start_IT,"ax",%progbits
+ 4540              		.align	1
+ 4541              		.global	HAL_TIMEx_OnePulseN_Start_IT
+ 4542              		.syntax unified
+ 4543              		.thumb
+ 4544              		.thumb_func
+ 4546              	HAL_TIMEx_OnePulseN_Start_IT:
+ 4547              	.LVL305:
+ 4548              	.LFB353:
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4549              		.loc 1 1784 1 is_stmt 1 view -0
+ 4550              		.cfi_startproc
+ 4551              		@ args = 0, pretend = 0, frame = 0
+ 4552              		@ frame_needed = 0, uses_anonymous_args = 0
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4553              		.loc 1 1784 1 is_stmt 0 view .LVU1281
+ 4554 0000 38B5     		push	{r3, r4, r5, lr}
+ 4555              	.LCFI28:
+ 4556              		.cfi_def_cfa_offset 16
+ 4557              		.cfi_offset 3, -16
+ 4558              		.cfi_offset 4, -12
+ 4559              		.cfi_offset 5, -8
+ARM GAS  /tmp/cc9HXhVl.s 			page 167
+
+
+ 4560              		.cfi_offset 14, -4
+ 4561 0002 0446     		mov	r4, r0
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 4562              		.loc 1 1785 3 is_stmt 1 view .LVU1282
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 4563              		.loc 1 1785 77 is_stmt 0 view .LVU1283
+ 4564 0004 8E46     		mov	lr, r1
+ 4565 0006 C1B9     		cbnz	r1, .L386
+ 4566 0008 0425     		movs	r5, #4
+ 4567              	.L384:
+ 4568              	.LVL306:
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 4569              		.loc 1 1786 3 is_stmt 1 discriminator 4 view .LVU1284
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 4570              		.loc 1 1786 31 is_stmt 0 discriminator 4 view .LVU1285
+ 4571 000a 94F83E00 		ldrb	r0, [r4, #62]	@ zero_extendqisi2
+ 4572              	.LVL307:
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 4573              		.loc 1 1786 31 discriminator 4 view .LVU1286
+ 4574 000e C0B2     		uxtb	r0, r0
+ 4575              	.LVL308:
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4576              		.loc 1 1787 3 is_stmt 1 discriminator 4 view .LVU1287
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4577              		.loc 1 1787 31 is_stmt 0 discriminator 4 view .LVU1288
+ 4578 0010 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ 4579 0014 DBB2     		uxtb	r3, r3
+ 4580              	.LVL309:
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4581              		.loc 1 1788 3 is_stmt 1 discriminator 4 view .LVU1289
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4582              		.loc 1 1788 31 is_stmt 0 discriminator 4 view .LVU1290
+ 4583 0016 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 4584 001a D2B2     		uxtb	r2, r2
+ 4585              	.LVL310:
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4586              		.loc 1 1789 3 is_stmt 1 discriminator 4 view .LVU1291
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4587              		.loc 1 1789 31 is_stmt 0 discriminator 4 view .LVU1292
+ 4588 001c 94F845C0 		ldrb	ip, [r4, #69]	@ zero_extendqisi2
+ 4589 0020 5FFA8CFC 		uxtb	ip, ip
+ 4590              	.LVL311:
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4591              		.loc 1 1792 3 is_stmt 1 discriminator 4 view .LVU1293
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 4592              		.loc 1 1795 3 discriminator 4 view .LVU1294
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 4593              		.loc 1 1795 6 is_stmt 0 discriminator 4 view .LVU1295
+ 4594 0024 0128     		cmp	r0, #1
+ 4595 0026 2ED1     		bne	.L387
+1796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 4596              		.loc 1 1796 7 view .LVU1296
+ 4597 0028 012B     		cmp	r3, #1
+ 4598 002a 2DD1     		bne	.L385
+1797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 4599              		.loc 1 1797 7 view .LVU1297
+ 4600 002c 012A     		cmp	r2, #1
+ARM GAS  /tmp/cc9HXhVl.s 			page 168
+
+
+ 4601 002e 2CD1     		bne	.L388
+1798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 4602              		.loc 1 1798 7 view .LVU1298
+ 4603 0030 BCF1010F 		cmp	ip, #1
+ 4604 0034 03D0     		beq	.L391
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4605              		.loc 1 1800 12 view .LVU1299
+ 4606 0036 1046     		mov	r0, r2
+ 4607              	.LVL312:
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4608              		.loc 1 1800 12 view .LVU1300
+ 4609 0038 26E0     		b	.L385
+ 4610              	.LVL313:
+ 4611              	.L386:
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 4612              		.loc 1 1785 77 view .LVU1301
+ 4613 003a 0025     		movs	r5, #0
+ 4614 003c E5E7     		b	.L384
+ 4615              	.LVL314:
+ 4616              	.L391:
+1804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4617              		.loc 1 1804 3 is_stmt 1 view .LVU1302
+ 4618 003e 0223     		movs	r3, #2
+ 4619              	.LVL315:
+1804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4620              		.loc 1 1804 3 is_stmt 0 view .LVU1303
+ 4621 0040 84F83E30 		strb	r3, [r4, #62]
+1805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4622              		.loc 1 1805 3 is_stmt 1 view .LVU1304
+ 4623 0044 84F83F30 		strb	r3, [r4, #63]
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4624              		.loc 1 1806 3 view .LVU1305
+ 4625 0048 84F84430 		strb	r3, [r4, #68]
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4626              		.loc 1 1807 3 view .LVU1306
+ 4627 004c 84F84530 		strb	r3, [r4, #69]
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4628              		.loc 1 1810 3 view .LVU1307
+ 4629 0050 2268     		ldr	r2, [r4]
+ 4630              	.LVL316:
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4631              		.loc 1 1810 3 is_stmt 0 view .LVU1308
+ 4632 0052 D368     		ldr	r3, [r2, #12]
+ 4633 0054 43F00203 		orr	r3, r3, #2
+ 4634 0058 D360     		str	r3, [r2, #12]
+1813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4635              		.loc 1 1813 3 is_stmt 1 view .LVU1309
+ 4636 005a 2268     		ldr	r2, [r4]
+ 4637 005c D368     		ldr	r3, [r2, #12]
+ 4638 005e 43F00403 		orr	r3, r3, #4
+ 4639 0062 D360     		str	r3, [r2, #12]
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4640              		.loc 1 1816 3 view .LVU1310
+ 4641 0064 0422     		movs	r2, #4
+ 4642 0066 7146     		mov	r1, lr
+ 4643              	.LVL317:
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ARM GAS  /tmp/cc9HXhVl.s 			page 169
+
+
+ 4644              		.loc 1 1816 3 is_stmt 0 view .LVU1311
+ 4645 0068 2068     		ldr	r0, [r4]
+ 4646              	.LVL318:
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4647              		.loc 1 1816 3 view .LVU1312
+ 4648 006a FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 4649              	.LVL319:
+1817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4650              		.loc 1 1817 3 is_stmt 1 view .LVU1313
+ 4651 006e 0122     		movs	r2, #1
+ 4652 0070 2946     		mov	r1, r5
+ 4653 0072 2068     		ldr	r0, [r4]
+ 4654 0074 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 4655              	.LVL320:
+1820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4656              		.loc 1 1820 3 view .LVU1314
+ 4657 0078 2268     		ldr	r2, [r4]
+ 4658 007a 536C     		ldr	r3, [r2, #68]
+ 4659 007c 43F40043 		orr	r3, r3, #32768
+ 4660 0080 5364     		str	r3, [r2, #68]
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 4661              		.loc 1 1823 3 view .LVU1315
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 4662              		.loc 1 1823 10 is_stmt 0 view .LVU1316
+ 4663 0082 0020     		movs	r0, #0
+ 4664 0084 00E0     		b	.L385
+ 4665              	.LVL321:
+ 4666              	.L387:
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4667              		.loc 1 1800 12 view .LVU1317
+ 4668 0086 0120     		movs	r0, #1
+ 4669              	.LVL322:
+ 4670              	.L385:
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4671              		.loc 1 1824 1 view .LVU1318
+ 4672 0088 38BD     		pop	{r3, r4, r5, pc}
+ 4673              	.LVL323:
+ 4674              	.L388:
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4675              		.loc 1 1800 12 view .LVU1319
+ 4676 008a 1846     		mov	r0, r3
+ 4677              	.LVL324:
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4678              		.loc 1 1800 12 view .LVU1320
+ 4679 008c FCE7     		b	.L385
+ 4680              		.cfi_endproc
+ 4681              	.LFE353:
+ 4683              		.section	.text.HAL_TIMEx_OnePulseN_Stop_IT,"ax",%progbits
+ 4684              		.align	1
+ 4685              		.global	HAL_TIMEx_OnePulseN_Stop_IT
+ 4686              		.syntax unified
+ 4687              		.thumb
+ 4688              		.thumb_func
+ 4690              	HAL_TIMEx_OnePulseN_Stop_IT:
+ 4691              	.LVL325:
+ 4692              	.LFB354:
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ARM GAS  /tmp/cc9HXhVl.s 			page 170
+
+
+ 4693              		.loc 1 1839 1 is_stmt 1 view -0
+ 4694              		.cfi_startproc
+ 4695              		@ args = 0, pretend = 0, frame = 0
+ 4696              		@ frame_needed = 0, uses_anonymous_args = 0
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4697              		.loc 1 1839 1 is_stmt 0 view .LVU1322
+ 4698 0000 38B5     		push	{r3, r4, r5, lr}
+ 4699              	.LCFI29:
+ 4700              		.cfi_def_cfa_offset 16
+ 4701              		.cfi_offset 3, -16
+ 4702              		.cfi_offset 4, -12
+ 4703              		.cfi_offset 5, -8
+ 4704              		.cfi_offset 14, -4
+ 4705 0002 0446     		mov	r4, r0
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4706              		.loc 1 1840 3 is_stmt 1 view .LVU1323
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4707              		.loc 1 1840 77 is_stmt 0 view .LVU1324
+ 4708 0004 0029     		cmp	r1, #0
+ 4709 0006 3CD1     		bne	.L396
+ 4710 0008 0425     		movs	r5, #4
+ 4711              	.L393:
+ 4712              	.LVL326:
+1843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4713              		.loc 1 1843 3 is_stmt 1 discriminator 4 view .LVU1325
+1846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4714              		.loc 1 1846 3 discriminator 4 view .LVU1326
+ 4715 000a 2268     		ldr	r2, [r4]
+ 4716 000c D368     		ldr	r3, [r2, #12]
+ 4717 000e 23F00203 		bic	r3, r3, #2
+ 4718 0012 D360     		str	r3, [r2, #12]
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4719              		.loc 1 1849 3 discriminator 4 view .LVU1327
+ 4720 0014 2268     		ldr	r2, [r4]
+ 4721 0016 D368     		ldr	r3, [r2, #12]
+ 4722 0018 23F00403 		bic	r3, r3, #4
+ 4723 001c D360     		str	r3, [r2, #12]
+1852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+ 4724              		.loc 1 1852 3 discriminator 4 view .LVU1328
+ 4725 001e 0022     		movs	r2, #0
+ 4726 0020 2068     		ldr	r0, [r4]
+ 4727              	.LVL327:
+1852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+ 4728              		.loc 1 1852 3 is_stmt 0 discriminator 4 view .LVU1329
+ 4729 0022 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 4730              	.LVL328:
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4731              		.loc 1 1853 3 is_stmt 1 discriminator 4 view .LVU1330
+ 4732 0026 0022     		movs	r2, #0
+ 4733 0028 2946     		mov	r1, r5
+ 4734 002a 2068     		ldr	r0, [r4]
+ 4735 002c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 4736              	.LVL329:
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4737              		.loc 1 1856 3 discriminator 4 view .LVU1331
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4738              		.loc 1 1856 3 discriminator 4 view .LVU1332
+ARM GAS  /tmp/cc9HXhVl.s 			page 171
+
+
+ 4739 0030 2368     		ldr	r3, [r4]
+ 4740 0032 196A     		ldr	r1, [r3, #32]
+ 4741 0034 41F21112 		movw	r2, #4369
+ 4742 0038 1142     		tst	r1, r2
+ 4743 003a 08D1     		bne	.L394
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4744              		.loc 1 1856 3 discriminator 1 view .LVU1333
+ 4745 003c 196A     		ldr	r1, [r3, #32]
+ 4746 003e 44F24442 		movw	r2, #17476
+ 4747 0042 1142     		tst	r1, r2
+ 4748 0044 03D1     		bne	.L394
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4749              		.loc 1 1856 3 discriminator 3 view .LVU1334
+ 4750 0046 5A6C     		ldr	r2, [r3, #68]
+ 4751 0048 22F40042 		bic	r2, r2, #32768
+ 4752 004c 5A64     		str	r2, [r3, #68]
+ 4753              	.L394:
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4754              		.loc 1 1856 3 discriminator 5 view .LVU1335
+1859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4755              		.loc 1 1859 3 discriminator 5 view .LVU1336
+1859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4756              		.loc 1 1859 3 discriminator 5 view .LVU1337
+ 4757 004e 2368     		ldr	r3, [r4]
+ 4758 0050 196A     		ldr	r1, [r3, #32]
+ 4759 0052 41F21112 		movw	r2, #4369
+ 4760 0056 1142     		tst	r1, r2
+ 4761 0058 08D1     		bne	.L395
+1859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4762              		.loc 1 1859 3 discriminator 1 view .LVU1338
+ 4763 005a 196A     		ldr	r1, [r3, #32]
+ 4764 005c 44F24442 		movw	r2, #17476
+ 4765 0060 1142     		tst	r1, r2
+ 4766 0062 03D1     		bne	.L395
+1859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4767              		.loc 1 1859 3 discriminator 3 view .LVU1339
+ 4768 0064 1A68     		ldr	r2, [r3]
+ 4769 0066 22F00102 		bic	r2, r2, #1
+ 4770 006a 1A60     		str	r2, [r3]
+ 4771              	.L395:
+1859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4772              		.loc 1 1859 3 discriminator 5 view .LVU1340
+1862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 4773              		.loc 1 1862 3 discriminator 5 view .LVU1341
+ 4774 006c 0123     		movs	r3, #1
+ 4775 006e 84F83E30 		strb	r3, [r4, #62]
+1863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 4776              		.loc 1 1863 3 discriminator 5 view .LVU1342
+ 4777 0072 84F83F30 		strb	r3, [r4, #63]
+1864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 4778              		.loc 1 1864 3 discriminator 5 view .LVU1343
+ 4779 0076 84F84430 		strb	r3, [r4, #68]
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4780              		.loc 1 1865 3 discriminator 5 view .LVU1344
+ 4781 007a 84F84530 		strb	r3, [r4, #69]
+1868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 4782              		.loc 1 1868 3 discriminator 5 view .LVU1345
+ARM GAS  /tmp/cc9HXhVl.s 			page 172
+
+
+1869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4783              		.loc 1 1869 1 is_stmt 0 discriminator 5 view .LVU1346
+ 4784 007e 0020     		movs	r0, #0
+ 4785 0080 38BD     		pop	{r3, r4, r5, pc}
+ 4786              	.LVL330:
+ 4787              	.L396:
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4788              		.loc 1 1840 77 view .LVU1347
+ 4789 0082 0025     		movs	r5, #0
+ 4790 0084 C1E7     		b	.L393
+ 4791              		.cfi_endproc
+ 4792              	.LFE354:
+ 4794              		.section	.text.HAL_TIMEx_ConfigCommutEvent,"ax",%progbits
+ 4795              		.align	1
+ 4796              		.global	HAL_TIMEx_ConfigCommutEvent
+ 4797              		.syntax unified
+ 4798              		.thumb
+ 4799              		.thumb_func
+ 4801              	HAL_TIMEx_ConfigCommutEvent:
+ 4802              	.LVL331:
+ 4803              	.LFB355:
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 4804              		.loc 1 1934 1 is_stmt 1 view -0
+ 4805              		.cfi_startproc
+ 4806              		@ args = 0, pretend = 0, frame = 0
+ 4807              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4808              		@ link register save eliminated.
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 4809              		.loc 1 1934 1 is_stmt 0 view .LVU1349
+ 4810 0000 0346     		mov	r3, r0
+1936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+ 4811              		.loc 1 1936 3 is_stmt 1 view .LVU1350
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4812              		.loc 1 1937 3 view .LVU1351
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4813              		.loc 1 1939 3 view .LVU1352
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4814              		.loc 1 1939 3 view .LVU1353
+ 4815 0002 90F83C00 		ldrb	r0, [r0, #60]	@ zero_extendqisi2
+ 4816              	.LVL332:
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4817              		.loc 1 1939 3 is_stmt 0 view .LVU1354
+ 4818 0006 0128     		cmp	r0, #1
+ 4819 0008 46D0     		beq	.L404
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 4820              		.loc 1 1934 1 discriminator 2 view .LVU1355
+ 4821 000a 10B4     		push	{r4}
+ 4822              	.LCFI30:
+ 4823              		.cfi_def_cfa_offset 4
+ 4824              		.cfi_offset 4, -4
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4825              		.loc 1 1939 3 is_stmt 1 discriminator 2 view .LVU1356
+ 4826 000c 0120     		movs	r0, #1
+ 4827 000e 83F83C00 		strb	r0, [r3, #60]
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4828              		.loc 1 1939 3 discriminator 2 view .LVU1357
+1961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+ARM GAS  /tmp/cc9HXhVl.s 			page 173
+
+
+ 4829              		.loc 1 1961 3 discriminator 2 view .LVU1358
+1961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+ 4830              		.loc 1 1961 6 is_stmt 0 discriminator 2 view .LVU1359
+ 4831 0012 51B1     		cbz	r1, .L400
+ 4832 0014 2148     		ldr	r0, .L409
+ 4833 0016 8142     		cmp	r1, r0
+ 4834 0018 07D0     		beq	.L400
+ 4835 001a 33D8     		bhi	.L401
+ 4836 001c 3029     		cmp	r1, #48
+ 4837 001e 04D0     		beq	.L400
+ 4838 0020 2CD8     		bhi	.L402
+ 4839 0022 1029     		cmp	r1, #16
+ 4840 0024 01D0     		beq	.L400
+ 4841 0026 2029     		cmp	r1, #32
+ 4842 0028 0AD1     		bne	.L403
+ 4843              	.L400:
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4844              		.loc 1 1969 5 is_stmt 1 view .LVU1360
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4845              		.loc 1 1969 9 is_stmt 0 view .LVU1361
+ 4846 002a 1C68     		ldr	r4, [r3]
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4847              		.loc 1 1969 19 view .LVU1362
+ 4848 002c A068     		ldr	r0, [r4, #8]
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4849              		.loc 1 1969 26 view .LVU1363
+ 4850 002e 20F44010 		bic	r0, r0, #3145728
+ 4851 0032 20F07000 		bic	r0, r0, #112
+ 4852 0036 A060     		str	r0, [r4, #8]
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4853              		.loc 1 1970 5 is_stmt 1 view .LVU1364
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4854              		.loc 1 1970 9 is_stmt 0 view .LVU1365
+ 4855 0038 1C68     		ldr	r4, [r3]
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4856              		.loc 1 1970 19 view .LVU1366
+ 4857 003a A068     		ldr	r0, [r4, #8]
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4858              		.loc 1 1970 26 view .LVU1367
+ 4859 003c 0143     		orrs	r1, r1, r0
+ 4860              	.LVL333:
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 4861              		.loc 1 1970 26 view .LVU1368
+ 4862 003e A160     		str	r1, [r4, #8]
+ 4863              	.L403:
+1974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4864              		.loc 1 1974 3 is_stmt 1 view .LVU1369
+1974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4865              		.loc 1 1974 7 is_stmt 0 view .LVU1370
+ 4866 0040 1868     		ldr	r0, [r3]
+1974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4867              		.loc 1 1974 17 view .LVU1371
+ 4868 0042 4168     		ldr	r1, [r0, #4]
+1974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4869              		.loc 1 1974 23 view .LVU1372
+ 4870 0044 41F00101 		orr	r1, r1, #1
+ 4871 0048 4160     		str	r1, [r0, #4]
+ARM GAS  /tmp/cc9HXhVl.s 			page 174
+
+
+1976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 4872              		.loc 1 1976 3 is_stmt 1 view .LVU1373
+1976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 4873              		.loc 1 1976 7 is_stmt 0 view .LVU1374
+ 4874 004a 1868     		ldr	r0, [r3]
+1976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 4875              		.loc 1 1976 17 view .LVU1375
+ 4876 004c 4168     		ldr	r1, [r0, #4]
+1976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 4877              		.loc 1 1976 23 view .LVU1376
+ 4878 004e 21F00401 		bic	r1, r1, #4
+ 4879 0052 4160     		str	r1, [r0, #4]
+1977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4880              		.loc 1 1977 3 is_stmt 1 view .LVU1377
+1977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4881              		.loc 1 1977 7 is_stmt 0 view .LVU1378
+ 4882 0054 1868     		ldr	r0, [r3]
+1977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4883              		.loc 1 1977 17 view .LVU1379
+ 4884 0056 4168     		ldr	r1, [r0, #4]
+1977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4885              		.loc 1 1977 23 view .LVU1380
+ 4886 0058 0A43     		orrs	r2, r2, r1
+ 4887              	.LVL334:
+1977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4888              		.loc 1 1977 23 view .LVU1381
+ 4889 005a 4260     		str	r2, [r0, #4]
+1980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4890              		.loc 1 1980 3 is_stmt 1 view .LVU1382
+ 4891 005c 1968     		ldr	r1, [r3]
+ 4892 005e CA68     		ldr	r2, [r1, #12]
+ 4893 0060 22F02002 		bic	r2, r2, #32
+ 4894 0064 CA60     		str	r2, [r1, #12]
+1983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4895              		.loc 1 1983 3 view .LVU1383
+ 4896 0066 1968     		ldr	r1, [r3]
+ 4897 0068 CA68     		ldr	r2, [r1, #12]
+ 4898 006a 22F40052 		bic	r2, r2, #8192
+ 4899 006e CA60     		str	r2, [r1, #12]
+1985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4900              		.loc 1 1985 3 view .LVU1384
+1985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4901              		.loc 1 1985 3 view .LVU1385
+ 4902 0070 0020     		movs	r0, #0
+ 4903 0072 83F83C00 		strb	r0, [r3, #60]
+1985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4904              		.loc 1 1985 3 view .LVU1386
+1987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 4905              		.loc 1 1987 3 view .LVU1387
+1988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4906              		.loc 1 1988 1 is_stmt 0 view .LVU1388
+ 4907 0076 5DF8044B 		ldr	r4, [sp], #4
+ 4908              	.LCFI31:
+ 4909              		.cfi_remember_state
+ 4910              		.cfi_restore 4
+ 4911              		.cfi_def_cfa_offset 0
+ 4912 007a 7047     		bx	lr
+ARM GAS  /tmp/cc9HXhVl.s 			page 175
+
+
+ 4913              	.LVL335:
+ 4914              	.L402:
+ 4915              	.LCFI32:
+ 4916              		.cfi_restore_state
+1988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4917              		.loc 1 1988 1 view .LVU1389
+ 4918 007c B1F1101F 		cmp	r1, #1048592
+ 4919 0080 DED1     		bne	.L403
+ 4920 0082 D2E7     		b	.L400
+ 4921              	.L401:
+1988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4922              		.loc 1 1988 1 view .LVU1390
+ 4923 0084 0648     		ldr	r0, .L409+4
+ 4924 0086 8142     		cmp	r1, r0
+ 4925 0088 CFD0     		beq	.L400
+ 4926 008a 3030     		adds	r0, r0, #48
+ 4927 008c 8142     		cmp	r1, r0
+ 4928 008e CCD0     		beq	.L400
+ 4929 0090 4038     		subs	r0, r0, #64
+ 4930 0092 8142     		cmp	r1, r0
+ 4931 0094 D4D1     		bne	.L403
+ 4932 0096 C8E7     		b	.L400
+ 4933              	.L404:
+ 4934              	.LCFI33:
+ 4935              		.cfi_def_cfa_offset 0
+ 4936              		.cfi_restore 4
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4937              		.loc 1 1939 3 view .LVU1391
+ 4938 0098 0220     		movs	r0, #2
+1988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4939              		.loc 1 1988 1 view .LVU1392
+ 4940 009a 7047     		bx	lr
+ 4941              	.L410:
+ 4942              		.align	2
+ 4943              	.L409:
+ 4944 009c 20001000 		.word	1048608
+ 4945 00a0 40001000 		.word	1048640
+ 4946              		.cfi_endproc
+ 4947              	.LFE355:
+ 4949              		.section	.text.HAL_TIMEx_ConfigCommutEvent_IT,"ax",%progbits
+ 4950              		.align	1
+ 4951              		.global	HAL_TIMEx_ConfigCommutEvent_IT
+ 4952              		.syntax unified
+ 4953              		.thumb
+ 4954              		.thumb_func
+ 4956              	HAL_TIMEx_ConfigCommutEvent_IT:
+ 4957              	.LVL336:
+ 4958              	.LFB356:
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 4959              		.loc 1 2025 1 is_stmt 1 view -0
+ 4960              		.cfi_startproc
+ 4961              		@ args = 0, pretend = 0, frame = 0
+ 4962              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4963              		@ link register save eliminated.
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 4964              		.loc 1 2025 1 is_stmt 0 view .LVU1394
+ 4965 0000 0346     		mov	r3, r0
+ARM GAS  /tmp/cc9HXhVl.s 			page 176
+
+
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+ 4966              		.loc 1 2027 3 is_stmt 1 view .LVU1395
+2028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4967              		.loc 1 2028 3 view .LVU1396
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4968              		.loc 1 2030 3 view .LVU1397
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4969              		.loc 1 2030 3 view .LVU1398
+ 4970 0002 90F83C00 		ldrb	r0, [r0, #60]	@ zero_extendqisi2
+ 4971              	.LVL337:
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4972              		.loc 1 2030 3 is_stmt 0 view .LVU1399
+ 4973 0006 0128     		cmp	r0, #1
+ 4974 0008 46D0     		beq	.L417
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 4975              		.loc 1 2025 1 discriminator 2 view .LVU1400
+ 4976 000a 10B4     		push	{r4}
+ 4977              	.LCFI34:
+ 4978              		.cfi_def_cfa_offset 4
+ 4979              		.cfi_offset 4, -4
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4980              		.loc 1 2030 3 is_stmt 1 discriminator 2 view .LVU1401
+ 4981 000c 0120     		movs	r0, #1
+ 4982 000e 83F83C00 		strb	r0, [r3, #60]
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 4983              		.loc 1 2030 3 discriminator 2 view .LVU1402
+2052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+ 4984              		.loc 1 2052 3 discriminator 2 view .LVU1403
+2052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+ 4985              		.loc 1 2052 6 is_stmt 0 discriminator 2 view .LVU1404
+ 4986 0012 51B1     		cbz	r1, .L413
+ 4987 0014 2148     		ldr	r0, .L422
+ 4988 0016 8142     		cmp	r1, r0
+ 4989 0018 07D0     		beq	.L413
+ 4990 001a 33D8     		bhi	.L414
+ 4991 001c 3029     		cmp	r1, #48
+ 4992 001e 04D0     		beq	.L413
+ 4993 0020 2CD8     		bhi	.L415
+ 4994 0022 1029     		cmp	r1, #16
+ 4995 0024 01D0     		beq	.L413
+ 4996 0026 2029     		cmp	r1, #32
+ 4997 0028 0AD1     		bne	.L416
+ 4998              	.L413:
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4999              		.loc 1 2060 5 is_stmt 1 view .LVU1405
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 5000              		.loc 1 2060 9 is_stmt 0 view .LVU1406
+ 5001 002a 1C68     		ldr	r4, [r3]
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 5002              		.loc 1 2060 19 view .LVU1407
+ 5003 002c A068     		ldr	r0, [r4, #8]
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 5004              		.loc 1 2060 26 view .LVU1408
+ 5005 002e 20F44010 		bic	r0, r0, #3145728
+ 5006 0032 20F07000 		bic	r0, r0, #112
+ 5007 0036 A060     		str	r0, [r4, #8]
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ARM GAS  /tmp/cc9HXhVl.s 			page 177
+
+
+ 5008              		.loc 1 2061 5 is_stmt 1 view .LVU1409
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5009              		.loc 1 2061 9 is_stmt 0 view .LVU1410
+ 5010 0038 1C68     		ldr	r4, [r3]
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5011              		.loc 1 2061 19 view .LVU1411
+ 5012 003a A068     		ldr	r0, [r4, #8]
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5013              		.loc 1 2061 26 view .LVU1412
+ 5014 003c 0143     		orrs	r1, r1, r0
+ 5015              	.LVL338:
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5016              		.loc 1 2061 26 view .LVU1413
+ 5017 003e A160     		str	r1, [r4, #8]
+ 5018              	.L416:
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 5019              		.loc 1 2065 3 is_stmt 1 view .LVU1414
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 5020              		.loc 1 2065 7 is_stmt 0 view .LVU1415
+ 5021 0040 1868     		ldr	r0, [r3]
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 5022              		.loc 1 2065 17 view .LVU1416
+ 5023 0042 4168     		ldr	r1, [r0, #4]
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 5024              		.loc 1 2065 23 view .LVU1417
+ 5025 0044 41F00101 		orr	r1, r1, #1
+ 5026 0048 4160     		str	r1, [r0, #4]
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 5027              		.loc 1 2067 3 is_stmt 1 view .LVU1418
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 5028              		.loc 1 2067 7 is_stmt 0 view .LVU1419
+ 5029 004a 1868     		ldr	r0, [r3]
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 5030              		.loc 1 2067 17 view .LVU1420
+ 5031 004c 4168     		ldr	r1, [r0, #4]
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 5032              		.loc 1 2067 23 view .LVU1421
+ 5033 004e 21F00401 		bic	r1, r1, #4
+ 5034 0052 4160     		str	r1, [r0, #4]
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5035              		.loc 1 2068 3 is_stmt 1 view .LVU1422
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5036              		.loc 1 2068 7 is_stmt 0 view .LVU1423
+ 5037 0054 1868     		ldr	r0, [r3]
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5038              		.loc 1 2068 17 view .LVU1424
+ 5039 0056 4168     		ldr	r1, [r0, #4]
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5040              		.loc 1 2068 23 view .LVU1425
+ 5041 0058 0A43     		orrs	r2, r2, r1
+ 5042              	.LVL339:
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5043              		.loc 1 2068 23 view .LVU1426
+ 5044 005a 4260     		str	r2, [r0, #4]
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5045              		.loc 1 2071 3 is_stmt 1 view .LVU1427
+ 5046 005c 1968     		ldr	r1, [r3]
+ARM GAS  /tmp/cc9HXhVl.s 			page 178
+
+
+ 5047 005e CA68     		ldr	r2, [r1, #12]
+ 5048 0060 22F40052 		bic	r2, r2, #8192
+ 5049 0064 CA60     		str	r2, [r1, #12]
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5050              		.loc 1 2074 3 view .LVU1428
+ 5051 0066 1968     		ldr	r1, [r3]
+ 5052 0068 CA68     		ldr	r2, [r1, #12]
+ 5053 006a 42F02002 		orr	r2, r2, #32
+ 5054 006e CA60     		str	r2, [r1, #12]
+2076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5055              		.loc 1 2076 3 view .LVU1429
+2076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5056              		.loc 1 2076 3 view .LVU1430
+ 5057 0070 0020     		movs	r0, #0
+ 5058 0072 83F83C00 		strb	r0, [r3, #60]
+2076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5059              		.loc 1 2076 3 view .LVU1431
+2078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 5060              		.loc 1 2078 3 view .LVU1432
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5061              		.loc 1 2079 1 is_stmt 0 view .LVU1433
+ 5062 0076 5DF8044B 		ldr	r4, [sp], #4
+ 5063              	.LCFI35:
+ 5064              		.cfi_remember_state
+ 5065              		.cfi_restore 4
+ 5066              		.cfi_def_cfa_offset 0
+ 5067 007a 7047     		bx	lr
+ 5068              	.LVL340:
+ 5069              	.L415:
+ 5070              	.LCFI36:
+ 5071              		.cfi_restore_state
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5072              		.loc 1 2079 1 view .LVU1434
+ 5073 007c B1F1101F 		cmp	r1, #1048592
+ 5074 0080 DED1     		bne	.L416
+ 5075 0082 D2E7     		b	.L413
+ 5076              	.L414:
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5077              		.loc 1 2079 1 view .LVU1435
+ 5078 0084 0648     		ldr	r0, .L422+4
+ 5079 0086 8142     		cmp	r1, r0
+ 5080 0088 CFD0     		beq	.L413
+ 5081 008a 3030     		adds	r0, r0, #48
+ 5082 008c 8142     		cmp	r1, r0
+ 5083 008e CCD0     		beq	.L413
+ 5084 0090 4038     		subs	r0, r0, #64
+ 5085 0092 8142     		cmp	r1, r0
+ 5086 0094 D4D1     		bne	.L416
+ 5087 0096 C8E7     		b	.L413
+ 5088              	.L417:
+ 5089              	.LCFI37:
+ 5090              		.cfi_def_cfa_offset 0
+ 5091              		.cfi_restore 4
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5092              		.loc 1 2030 3 view .LVU1436
+ 5093 0098 0220     		movs	r0, #2
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 179
+
+
+ 5094              		.loc 1 2079 1 view .LVU1437
+ 5095 009a 7047     		bx	lr
+ 5096              	.L423:
+ 5097              		.align	2
+ 5098              	.L422:
+ 5099 009c 20001000 		.word	1048608
+ 5100 00a0 40001000 		.word	1048640
+ 5101              		.cfi_endproc
+ 5102              	.LFE356:
+ 5104              		.section	.text.HAL_TIMEx_ConfigCommutEvent_DMA,"ax",%progbits
+ 5105              		.align	1
+ 5106              		.global	HAL_TIMEx_ConfigCommutEvent_DMA
+ 5107              		.syntax unified
+ 5108              		.thumb
+ 5109              		.thumb_func
+ 5111              	HAL_TIMEx_ConfigCommutEvent_DMA:
+ 5112              	.LVL341:
+ 5113              	.LFB357:
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 5114              		.loc 1 2117 1 is_stmt 1 view -0
+ 5115              		.cfi_startproc
+ 5116              		@ args = 0, pretend = 0, frame = 0
+ 5117              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5118              		@ link register save eliminated.
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 5119              		.loc 1 2117 1 is_stmt 0 view .LVU1439
+ 5120 0000 0346     		mov	r3, r0
+2119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+ 5121              		.loc 1 2119 3 is_stmt 1 view .LVU1440
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5122              		.loc 1 2120 3 view .LVU1441
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5123              		.loc 1 2122 3 view .LVU1442
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5124              		.loc 1 2122 3 view .LVU1443
+ 5125 0002 90F83C00 		ldrb	r0, [r0, #60]	@ zero_extendqisi2
+ 5126              	.LVL342:
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5127              		.loc 1 2122 3 is_stmt 0 view .LVU1444
+ 5128 0006 0128     		cmp	r0, #1
+ 5129 0008 4FD0     		beq	.L430
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 5130              		.loc 1 2117 1 discriminator 2 view .LVU1445
+ 5131 000a 10B4     		push	{r4}
+ 5132              	.LCFI38:
+ 5133              		.cfi_def_cfa_offset 4
+ 5134              		.cfi_offset 4, -4
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5135              		.loc 1 2122 3 is_stmt 1 discriminator 2 view .LVU1446
+ 5136 000c 0120     		movs	r0, #1
+ 5137 000e 83F83C00 		strb	r0, [r3, #60]
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5138              		.loc 1 2122 3 discriminator 2 view .LVU1447
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+ 5139              		.loc 1 2144 3 discriminator 2 view .LVU1448
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+ 5140              		.loc 1 2144 6 is_stmt 0 discriminator 2 view .LVU1449
+ARM GAS  /tmp/cc9HXhVl.s 			page 180
+
+
+ 5141 0012 51B1     		cbz	r1, .L426
+ 5142 0014 2648     		ldr	r0, .L435
+ 5143 0016 8142     		cmp	r1, r0
+ 5144 0018 07D0     		beq	.L426
+ 5145 001a 3CD8     		bhi	.L427
+ 5146 001c 3029     		cmp	r1, #48
+ 5147 001e 04D0     		beq	.L426
+ 5148 0020 35D8     		bhi	.L428
+ 5149 0022 1029     		cmp	r1, #16
+ 5150 0024 01D0     		beq	.L426
+ 5151 0026 2029     		cmp	r1, #32
+ 5152 0028 0AD1     		bne	.L429
+ 5153              	.L426:
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 5154              		.loc 1 2152 5 is_stmt 1 view .LVU1450
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 5155              		.loc 1 2152 9 is_stmt 0 view .LVU1451
+ 5156 002a 1C68     		ldr	r4, [r3]
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 5157              		.loc 1 2152 19 view .LVU1452
+ 5158 002c A068     		ldr	r0, [r4, #8]
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 5159              		.loc 1 2152 26 view .LVU1453
+ 5160 002e 20F44010 		bic	r0, r0, #3145728
+ 5161 0032 20F07000 		bic	r0, r0, #112
+ 5162 0036 A060     		str	r0, [r4, #8]
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5163              		.loc 1 2153 5 is_stmt 1 view .LVU1454
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5164              		.loc 1 2153 9 is_stmt 0 view .LVU1455
+ 5165 0038 1C68     		ldr	r4, [r3]
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5166              		.loc 1 2153 19 view .LVU1456
+ 5167 003a A068     		ldr	r0, [r4, #8]
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5168              		.loc 1 2153 26 view .LVU1457
+ 5169 003c 0143     		orrs	r1, r1, r0
+ 5170              	.LVL343:
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5171              		.loc 1 2153 26 view .LVU1458
+ 5172 003e A160     		str	r1, [r4, #8]
+ 5173              	.L429:
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 5174              		.loc 1 2157 3 is_stmt 1 view .LVU1459
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 5175              		.loc 1 2157 7 is_stmt 0 view .LVU1460
+ 5176 0040 1868     		ldr	r0, [r3]
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 5177              		.loc 1 2157 17 view .LVU1461
+ 5178 0042 4168     		ldr	r1, [r0, #4]
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 5179              		.loc 1 2157 23 view .LVU1462
+ 5180 0044 41F00101 		orr	r1, r1, #1
+ 5181 0048 4160     		str	r1, [r0, #4]
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 5182              		.loc 1 2159 3 is_stmt 1 view .LVU1463
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ARM GAS  /tmp/cc9HXhVl.s 			page 181
+
+
+ 5183              		.loc 1 2159 7 is_stmt 0 view .LVU1464
+ 5184 004a 1868     		ldr	r0, [r3]
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 5185              		.loc 1 2159 17 view .LVU1465
+ 5186 004c 4168     		ldr	r1, [r0, #4]
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 5187              		.loc 1 2159 23 view .LVU1466
+ 5188 004e 21F00401 		bic	r1, r1, #4
+ 5189 0052 4160     		str	r1, [r0, #4]
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5190              		.loc 1 2160 3 is_stmt 1 view .LVU1467
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5191              		.loc 1 2160 7 is_stmt 0 view .LVU1468
+ 5192 0054 1868     		ldr	r0, [r3]
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5193              		.loc 1 2160 17 view .LVU1469
+ 5194 0056 4168     		ldr	r1, [r0, #4]
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5195              		.loc 1 2160 23 view .LVU1470
+ 5196 0058 0A43     		orrs	r2, r2, r1
+ 5197              	.LVL344:
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5198              		.loc 1 2160 23 view .LVU1471
+ 5199 005a 4260     		str	r2, [r0, #4]
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+ 5200              		.loc 1 2164 3 is_stmt 1 view .LVU1472
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+ 5201              		.loc 1 2164 13 is_stmt 0 view .LVU1473
+ 5202 005c 5A6B     		ldr	r2, [r3, #52]
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+ 5203              		.loc 1 2164 56 view .LVU1474
+ 5204 005e 1549     		ldr	r1, .L435+4
+ 5205 0060 D162     		str	r1, [r2, #44]
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 5206              		.loc 1 2165 3 is_stmt 1 view .LVU1475
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 5207              		.loc 1 2165 13 is_stmt 0 view .LVU1476
+ 5208 0062 5A6B     		ldr	r2, [r3, #52]
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 5209              		.loc 1 2165 60 view .LVU1477
+ 5210 0064 1449     		ldr	r1, .L435+8
+ 5211 0066 1163     		str	r1, [r2, #48]
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5212              		.loc 1 2167 3 is_stmt 1 view .LVU1478
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5213              		.loc 1 2167 13 is_stmt 0 view .LVU1479
+ 5214 0068 5A6B     		ldr	r2, [r3, #52]
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5215              		.loc 1 2167 57 view .LVU1480
+ 5216 006a 1449     		ldr	r1, .L435+12
+ 5217 006c 5163     		str	r1, [r2, #52]
+2170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5218              		.loc 1 2170 3 is_stmt 1 view .LVU1481
+ 5219 006e 1968     		ldr	r1, [r3]
+ 5220 0070 CA68     		ldr	r2, [r1, #12]
+ 5221 0072 22F02002 		bic	r2, r2, #32
+ 5222 0076 CA60     		str	r2, [r1, #12]
+ARM GAS  /tmp/cc9HXhVl.s 			page 182
+
+
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5223              		.loc 1 2173 3 view .LVU1482
+ 5224 0078 1968     		ldr	r1, [r3]
+ 5225 007a CA68     		ldr	r2, [r1, #12]
+ 5226 007c 42F40052 		orr	r2, r2, #8192
+ 5227 0080 CA60     		str	r2, [r1, #12]
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5228              		.loc 1 2175 3 view .LVU1483
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5229              		.loc 1 2175 3 view .LVU1484
+ 5230 0082 0020     		movs	r0, #0
+ 5231 0084 83F83C00 		strb	r0, [r3, #60]
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5232              		.loc 1 2175 3 view .LVU1485
+2177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 5233              		.loc 1 2177 3 view .LVU1486
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5234              		.loc 1 2178 1 is_stmt 0 view .LVU1487
+ 5235 0088 5DF8044B 		ldr	r4, [sp], #4
+ 5236              	.LCFI39:
+ 5237              		.cfi_remember_state
+ 5238              		.cfi_restore 4
+ 5239              		.cfi_def_cfa_offset 0
+ 5240 008c 7047     		bx	lr
+ 5241              	.LVL345:
+ 5242              	.L428:
+ 5243              	.LCFI40:
+ 5244              		.cfi_restore_state
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5245              		.loc 1 2178 1 view .LVU1488
+ 5246 008e B1F1101F 		cmp	r1, #1048592
+ 5247 0092 D5D1     		bne	.L429
+ 5248 0094 C9E7     		b	.L426
+ 5249              	.L427:
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5250              		.loc 1 2178 1 view .LVU1489
+ 5251 0096 0A48     		ldr	r0, .L435+16
+ 5252 0098 8142     		cmp	r1, r0
+ 5253 009a C6D0     		beq	.L426
+ 5254 009c 3030     		adds	r0, r0, #48
+ 5255 009e 8142     		cmp	r1, r0
+ 5256 00a0 C3D0     		beq	.L426
+ 5257 00a2 4038     		subs	r0, r0, #64
+ 5258 00a4 8142     		cmp	r1, r0
+ 5259 00a6 CBD1     		bne	.L429
+ 5260 00a8 BFE7     		b	.L426
+ 5261              	.L430:
+ 5262              	.LCFI41:
+ 5263              		.cfi_def_cfa_offset 0
+ 5264              		.cfi_restore 4
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5265              		.loc 1 2122 3 view .LVU1490
+ 5266 00aa 0220     		movs	r0, #2
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5267              		.loc 1 2178 1 view .LVU1491
+ 5268 00ac 7047     		bx	lr
+ 5269              	.L436:
+ARM GAS  /tmp/cc9HXhVl.s 			page 183
+
+
+ 5270 00ae 00BF     		.align	2
+ 5271              	.L435:
+ 5272 00b0 20001000 		.word	1048608
+ 5273 00b4 00000000 		.word	TIMEx_DMACommutationCplt
+ 5274 00b8 00000000 		.word	TIMEx_DMACommutationHalfCplt
+ 5275 00bc 00000000 		.word	TIM_DMAError
+ 5276 00c0 40001000 		.word	1048640
+ 5277              		.cfi_endproc
+ 5278              	.LFE357:
+ 5280              		.section	.text.HAL_TIMEx_MasterConfigSynchronization,"ax",%progbits
+ 5281              		.align	1
+ 5282              		.global	HAL_TIMEx_MasterConfigSynchronization
+ 5283              		.syntax unified
+ 5284              		.thumb
+ 5285              		.thumb_func
+ 5287              	HAL_TIMEx_MasterConfigSynchronization:
+ 5288              	.LVL346:
+ 5289              	.LFB358:
+2190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpcr2;
+ 5290              		.loc 1 2190 1 is_stmt 1 view -0
+ 5291              		.cfi_startproc
+ 5292              		@ args = 0, pretend = 0, frame = 0
+ 5293              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5294              		@ link register save eliminated.
+2191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 5295              		.loc 1 2191 3 view .LVU1493
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5296              		.loc 1 2192 3 view .LVU1494
+2195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ 5297              		.loc 1 2195 3 view .LVU1495
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+ 5298              		.loc 1 2196 3 view .LVU1496
+2197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5299              		.loc 1 2197 3 view .LVU1497
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5300              		.loc 1 2200 3 view .LVU1498
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5301              		.loc 1 2200 3 view .LVU1499
+ 5302 0000 90F83C20 		ldrb	r2, [r0, #60]	@ zero_extendqisi2
+ 5303 0004 012A     		cmp	r2, #1
+ 5304 0006 40D0     		beq	.L443
+2190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpcr2;
+ 5305              		.loc 1 2190 1 is_stmt 0 discriminator 2 view .LVU1500
+ 5306 0008 30B4     		push	{r4, r5}
+ 5307              	.LCFI42:
+ 5308              		.cfi_def_cfa_offset 8
+ 5309              		.cfi_offset 4, -8
+ 5310              		.cfi_offset 5, -4
+ 5311 000a 0346     		mov	r3, r0
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5312              		.loc 1 2200 3 is_stmt 1 discriminator 2 view .LVU1501
+ 5313 000c 0122     		movs	r2, #1
+ 5314 000e 80F83C20 		strb	r2, [r0, #60]
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5315              		.loc 1 2200 3 discriminator 2 view .LVU1502
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5316              		.loc 1 2203 3 discriminator 2 view .LVU1503
+ARM GAS  /tmp/cc9HXhVl.s 			page 184
+
+
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5317              		.loc 1 2203 15 is_stmt 0 discriminator 2 view .LVU1504
+ 5318 0012 0222     		movs	r2, #2
+ 5319 0014 80F83D20 		strb	r2, [r0, #61]
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5320              		.loc 1 2206 3 is_stmt 1 discriminator 2 view .LVU1505
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5321              		.loc 1 2206 16 is_stmt 0 discriminator 2 view .LVU1506
+ 5322 0018 0068     		ldr	r0, [r0]
+ 5323              	.LVL347:
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5324              		.loc 1 2206 10 discriminator 2 view .LVU1507
+ 5325 001a 4268     		ldr	r2, [r0, #4]
+ 5326              	.LVL348:
+2209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5327              		.loc 1 2209 3 is_stmt 1 discriminator 2 view .LVU1508
+2209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5328              		.loc 1 2209 11 is_stmt 0 discriminator 2 view .LVU1509
+ 5329 001c 8468     		ldr	r4, [r0, #8]
+ 5330              	.LVL349:
+2212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5331              		.loc 1 2212 3 is_stmt 1 discriminator 2 view .LVU1510
+2212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5332              		.loc 1 2212 6 is_stmt 0 discriminator 2 view .LVU1511
+ 5333 001e 1C4D     		ldr	r5, .L448
+ 5334 0020 A842     		cmp	r0, r5
+ 5335 0022 03D0     		beq	.L439
+2212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5336              		.loc 1 2212 7 discriminator 1 view .LVU1512
+ 5337 0024 05F50065 		add	r5, r5, #2048
+ 5338 0028 A842     		cmp	r0, r5
+ 5339 002a 03D1     		bne	.L440
+ 5340              	.L439:
+2215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5341              		.loc 1 2215 5 is_stmt 1 view .LVU1513
+2218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Select the TRGO2 source*/
+ 5342              		.loc 1 2218 5 view .LVU1514
+2218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Select the TRGO2 source*/
+ 5343              		.loc 1 2218 12 is_stmt 0 view .LVU1515
+ 5344 002c 22F47002 		bic	r2, r2, #15728640
+ 5345              	.LVL350:
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5346              		.loc 1 2220 5 is_stmt 1 view .LVU1516
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5347              		.loc 1 2220 28 is_stmt 0 view .LVU1517
+ 5348 0030 4D68     		ldr	r5, [r1, #4]
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5349              		.loc 1 2220 12 view .LVU1518
+ 5350 0032 2A43     		orrs	r2, r2, r5
+ 5351              	.LVL351:
+ 5352              	.L440:
+2224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the TRGO source */
+ 5353              		.loc 1 2224 3 is_stmt 1 view .LVU1519
+2224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the TRGO source */
+ 5354              		.loc 1 2224 10 is_stmt 0 view .LVU1520
+ 5355 0034 22F00072 		bic	r2, r2, #33554432
+ 5356              	.LVL352:
+ARM GAS  /tmp/cc9HXhVl.s 			page 185
+
+
+2224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Select the TRGO source */
+ 5357              		.loc 1 2224 10 view .LVU1521
+ 5358 0038 22F07002 		bic	r2, r2, #112
+ 5359              	.LVL353:
+2226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5360              		.loc 1 2226 3 is_stmt 1 view .LVU1522
+2226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5361              		.loc 1 2226 10 is_stmt 0 view .LVU1523
+ 5362 003c 0D68     		ldr	r5, [r1]
+ 5363 003e 2A43     		orrs	r2, r2, r5
+ 5364              	.LVL354:
+2229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5365              		.loc 1 2229 3 is_stmt 1 view .LVU1524
+2229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5366              		.loc 1 2229 23 is_stmt 0 view .LVU1525
+ 5367 0040 4260     		str	r2, [r0, #4]
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5368              		.loc 1 2231 3 is_stmt 1 view .LVU1526
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5369              		.loc 1 2231 7 is_stmt 0 view .LVU1527
+ 5370 0042 1A68     		ldr	r2, [r3]
+ 5371              	.LVL355:
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5372              		.loc 1 2231 6 view .LVU1528
+ 5373 0044 1248     		ldr	r0, .L448
+ 5374              	.LVL356:
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5375              		.loc 1 2231 6 view .LVU1529
+ 5376 0046 8242     		cmp	r2, r0
+ 5377 0048 12D0     		beq	.L441
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5378              		.loc 1 2231 7 discriminator 1 view .LVU1530
+ 5379 004a B2F1804F 		cmp	r2, #1073741824
+ 5380 004e 0FD0     		beq	.L441
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5381              		.loc 1 2231 7 discriminator 2 view .LVU1531
+ 5382 0050 A0F59430 		sub	r0, r0, #75776
+ 5383 0054 8242     		cmp	r2, r0
+ 5384 0056 0BD0     		beq	.L441
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5385              		.loc 1 2231 7 discriminator 3 view .LVU1532
+ 5386 0058 00F58060 		add	r0, r0, #1024
+ 5387 005c 8242     		cmp	r2, r0
+ 5388 005e 07D0     		beq	.L441
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5389              		.loc 1 2231 7 discriminator 4 view .LVU1533
+ 5390 0060 00F59630 		add	r0, r0, #76800
+ 5391 0064 8242     		cmp	r2, r0
+ 5392 0066 03D0     		beq	.L441
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5393              		.loc 1 2231 7 discriminator 5 view .LVU1534
+ 5394 0068 00F54060 		add	r0, r0, #3072
+ 5395 006c 8242     		cmp	r2, r0
+ 5396 006e 04D1     		bne	.L442
+ 5397              	.L441:
+2234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Set master mode */
+ 5398              		.loc 1 2234 5 is_stmt 1 view .LVU1535
+ARM GAS  /tmp/cc9HXhVl.s 			page 186
+
+
+2234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     /* Set master mode */
+ 5399              		.loc 1 2234 13 is_stmt 0 view .LVU1536
+ 5400 0070 24F08004 		bic	r4, r4, #128
+ 5401              	.LVL357:
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5402              		.loc 1 2236 5 is_stmt 1 view .LVU1537
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5403              		.loc 1 2236 29 is_stmt 0 view .LVU1538
+ 5404 0074 8968     		ldr	r1, [r1, #8]
+ 5405              	.LVL358:
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5406              		.loc 1 2236 13 view .LVU1539
+ 5407 0076 2143     		orrs	r1, r1, r4
+ 5408              	.LVL359:
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5409              		.loc 1 2239 5 is_stmt 1 view .LVU1540
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5410              		.loc 1 2239 26 is_stmt 0 view .LVU1541
+ 5411 0078 9160     		str	r1, [r2, #8]
+ 5412              	.LVL360:
+ 5413              	.L442:
+2243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5414              		.loc 1 2243 3 is_stmt 1 view .LVU1542
+2243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5415              		.loc 1 2243 15 is_stmt 0 view .LVU1543
+ 5416 007a 0122     		movs	r2, #1
+ 5417 007c 83F83D20 		strb	r2, [r3, #61]
+2245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5418              		.loc 1 2245 3 is_stmt 1 view .LVU1544
+2245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5419              		.loc 1 2245 3 view .LVU1545
+ 5420 0080 0020     		movs	r0, #0
+ 5421 0082 83F83C00 		strb	r0, [r3, #60]
+2245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5422              		.loc 1 2245 3 view .LVU1546
+2247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 5423              		.loc 1 2247 3 view .LVU1547
+2248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5424              		.loc 1 2248 1 is_stmt 0 view .LVU1548
+ 5425 0086 30BC     		pop	{r4, r5}
+ 5426              	.LCFI43:
+ 5427              		.cfi_restore 5
+ 5428              		.cfi_restore 4
+ 5429              		.cfi_def_cfa_offset 0
+ 5430 0088 7047     		bx	lr
+ 5431              	.LVL361:
+ 5432              	.L443:
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5433              		.loc 1 2200 3 view .LVU1549
+ 5434 008a 0220     		movs	r0, #2
+ 5435              	.LVL362:
+2248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5436              		.loc 1 2248 1 view .LVU1550
+ 5437 008c 7047     		bx	lr
+ 5438              	.L449:
+ 5439 008e 00BF     		.align	2
+ 5440              	.L448:
+ARM GAS  /tmp/cc9HXhVl.s 			page 187
+
+
+ 5441 0090 002C0140 		.word	1073818624
+ 5442              		.cfi_endproc
+ 5443              	.LFE358:
+ 5445              		.section	.text.HAL_TIMEx_ConfigBreakDeadTime,"ax",%progbits
+ 5446              		.align	1
+ 5447              		.global	HAL_TIMEx_ConfigBreakDeadTime
+ 5448              		.syntax unified
+ 5449              		.thumb
+ 5450              		.thumb_func
+ 5452              	HAL_TIMEx_ConfigBreakDeadTime:
+ 5453              	.LVL363:
+ 5454              	.LFB359:
+2263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+ 5455              		.loc 1 2263 1 is_stmt 1 view -0
+ 5456              		.cfi_startproc
+ 5457              		@ args = 0, pretend = 0, frame = 0
+ 5458              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5459              		@ link register save eliminated.
+2265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5460              		.loc 1 2265 3 view .LVU1552
+2268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ 5461              		.loc 1 2268 3 view .LVU1553
+2269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ 5462              		.loc 1 2269 3 view .LVU1554
+2270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ 5463              		.loc 1 2270 3 view .LVU1555
+2271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ 5464              		.loc 1 2271 3 view .LVU1556
+2272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ 5465              		.loc 1 2272 3 view .LVU1557
+2273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ 5466              		.loc 1 2273 3 view .LVU1558
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+ 5467              		.loc 1 2274 3 view .LVU1559
+2275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+ 5468              		.loc 1 2275 3 view .LVU1560
+2276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5469              		.loc 1 2276 3 view .LVU1561
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5470              		.loc 1 2279 3 view .LVU1562
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5471              		.loc 1 2279 3 view .LVU1563
+ 5472 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 5473 0004 012B     		cmp	r3, #1
+ 5474 0006 55D0     		beq	.L457
+2263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+ 5475              		.loc 1 2263 1 is_stmt 0 discriminator 2 view .LVU1564
+ 5476 0008 10B4     		push	{r4}
+ 5477              	.LCFI44:
+ 5478              		.cfi_def_cfa_offset 4
+ 5479              		.cfi_offset 4, -4
+ 5480 000a 0246     		mov	r2, r0
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5481              		.loc 1 2279 3 is_stmt 1 discriminator 2 view .LVU1565
+ 5482 000c 0123     		movs	r3, #1
+ 5483 000e 80F83C30 		strb	r3, [r0, #60]
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 188
+
+
+ 5484              		.loc 1 2279 3 discriminator 2 view .LVU1566
+2285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+ 5485              		.loc 1 2285 3 discriminator 2 view .LVU1567
+ 5486 0012 CB68     		ldr	r3, [r1, #12]
+ 5487              	.LVL364:
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ 5488              		.loc 1 2286 3 discriminator 2 view .LVU1568
+ 5489 0014 23F44073 		bic	r3, r3, #768
+ 5490              	.LVL365:
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ 5491              		.loc 1 2286 3 is_stmt 0 discriminator 2 view .LVU1569
+ 5492 0018 8868     		ldr	r0, [r1, #8]
+ 5493              	.LVL366:
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ 5494              		.loc 1 2286 3 discriminator 2 view .LVU1570
+ 5495 001a 0343     		orrs	r3, r3, r0
+ 5496              	.LVL367:
+2287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ 5497              		.loc 1 2287 3 is_stmt 1 discriminator 2 view .LVU1571
+ 5498 001c 23F48063 		bic	r3, r3, #1024
+ 5499              	.LVL368:
+2287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ 5500              		.loc 1 2287 3 is_stmt 0 discriminator 2 view .LVU1572
+ 5501 0020 4868     		ldr	r0, [r1, #4]
+ 5502              	.LVL369:
+2287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ 5503              		.loc 1 2287 3 discriminator 2 view .LVU1573
+ 5504 0022 0343     		orrs	r3, r3, r0
+ 5505              	.LVL370:
+2288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ 5506              		.loc 1 2288 3 is_stmt 1 discriminator 2 view .LVU1574
+ 5507 0024 23F40063 		bic	r3, r3, #2048
+ 5508              	.LVL371:
+2288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ 5509              		.loc 1 2288 3 is_stmt 0 discriminator 2 view .LVU1575
+ 5510 0028 0868     		ldr	r0, [r1]
+ 5511              	.LVL372:
+2288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ 5512              		.loc 1 2288 3 discriminator 2 view .LVU1576
+ 5513 002a 0343     		orrs	r3, r3, r0
+ 5514              	.LVL373:
+2289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ 5515              		.loc 1 2289 3 is_stmt 1 discriminator 2 view .LVU1577
+ 5516 002c 23F48053 		bic	r3, r3, #4096
+ 5517              	.LVL374:
+2289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ 5518              		.loc 1 2289 3 is_stmt 0 discriminator 2 view .LVU1578
+ 5519 0030 0869     		ldr	r0, [r1, #16]
+ 5520              	.LVL375:
+2289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ 5521              		.loc 1 2289 3 discriminator 2 view .LVU1579
+ 5522 0032 0343     		orrs	r3, r3, r0
+ 5523              	.LVL376:
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ 5524              		.loc 1 2290 3 is_stmt 1 discriminator 2 view .LVU1580
+ 5525 0034 23F40053 		bic	r3, r3, #8192
+ 5526              	.LVL377:
+ARM GAS  /tmp/cc9HXhVl.s 			page 189
+
+
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ 5527              		.loc 1 2290 3 is_stmt 0 discriminator 2 view .LVU1581
+ 5528 0038 4869     		ldr	r0, [r1, #20]
+ 5529              	.LVL378:
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ 5530              		.loc 1 2290 3 discriminator 2 view .LVU1582
+ 5531 003a 0343     		orrs	r3, r3, r0
+ 5532              	.LVL379:
+2291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+ 5533              		.loc 1 2291 3 is_stmt 1 discriminator 2 view .LVU1583
+ 5534 003c 23F48043 		bic	r3, r3, #16384
+ 5535              	.LVL380:
+2291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+ 5536              		.loc 1 2291 3 is_stmt 0 discriminator 2 view .LVU1584
+ 5537 0040 086B     		ldr	r0, [r1, #48]
+ 5538              	.LVL381:
+2291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+ 5539              		.loc 1 2291 3 discriminator 2 view .LVU1585
+ 5540 0042 0343     		orrs	r3, r3, r0
+ 5541              	.LVL382:
+2292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5542              		.loc 1 2292 3 is_stmt 1 discriminator 2 view .LVU1586
+ 5543 0044 23F47023 		bic	r3, r3, #983040
+ 5544              	.LVL383:
+2292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5545              		.loc 1 2292 3 is_stmt 0 discriminator 2 view .LVU1587
+ 5546 0048 8869     		ldr	r0, [r1, #24]
+ 5547              	.LVL384:
+2292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5548              		.loc 1 2292 3 discriminator 2 view .LVU1588
+ 5549 004a 43EA0043 		orr	r3, r3, r0, lsl #16
+ 5550              	.LVL385:
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5551              		.loc 1 2294 3 is_stmt 1 discriminator 2 view .LVU1589
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5552              		.loc 1 2294 7 is_stmt 0 discriminator 2 view .LVU1590
+ 5553 004e 1068     		ldr	r0, [r2]
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5554              		.loc 1 2294 6 discriminator 2 view .LVU1591
+ 5555 0050 194C     		ldr	r4, .L462
+ 5556 0052 A042     		cmp	r0, r4
+ 5557 0054 03D0     		beq	.L452
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5558              		.loc 1 2294 7 discriminator 1 view .LVU1592
+ 5559 0056 04F50064 		add	r4, r4, #2048
+ 5560 005a A042     		cmp	r0, r4
+ 5561 005c 03D1     		bne	.L453
+ 5562              	.L452:
+2297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5563              		.loc 1 2297 5 is_stmt 1 view .LVU1593
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5564              		.loc 1 2300 5 view .LVU1594
+ 5565 005e 23F08053 		bic	r3, r3, #268435456
+ 5566              	.LVL386:
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   }
+ 5567              		.loc 1 2300 5 is_stmt 0 view .LVU1595
+ 5568 0062 CC69     		ldr	r4, [r1, #28]
+ARM GAS  /tmp/cc9HXhVl.s 			page 190
+
+
+ 5569 0064 2343     		orrs	r3, r3, r4
+ 5570              	.LVL387:
+ 5571              	.L453:
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5572              		.loc 1 2303 3 is_stmt 1 view .LVU1596
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5573              		.loc 1 2303 6 is_stmt 0 view .LVU1597
+ 5574 0066 144C     		ldr	r4, .L462
+ 5575 0068 A042     		cmp	r0, r4
+ 5576 006a 0AD0     		beq	.L454
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5577              		.loc 1 2303 7 discriminator 1 view .LVU1598
+ 5578 006c 04F50064 		add	r4, r4, #2048
+ 5579 0070 A042     		cmp	r0, r4
+ 5580 0072 06D0     		beq	.L454
+ 5581              	.LVL388:
+ 5582              	.L455:
+2326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5583              		.loc 1 2326 3 is_stmt 1 view .LVU1599
+2326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5584              		.loc 1 2326 24 is_stmt 0 view .LVU1600
+ 5585 0074 4364     		str	r3, [r0, #68]
+2328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5586              		.loc 1 2328 3 is_stmt 1 view .LVU1601
+2328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5587              		.loc 1 2328 3 view .LVU1602
+ 5588 0076 0020     		movs	r0, #0
+ 5589 0078 82F83C00 		strb	r0, [r2, #60]
+2328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5590              		.loc 1 2328 3 view .LVU1603
+2330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 5591              		.loc 1 2330 3 view .LVU1604
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5592              		.loc 1 2331 1 is_stmt 0 view .LVU1605
+ 5593 007c 5DF8044B 		ldr	r4, [sp], #4
+ 5594              	.LCFI45:
+ 5595              		.cfi_remember_state
+ 5596              		.cfi_restore 4
+ 5597              		.cfi_def_cfa_offset 0
+ 5598 0080 7047     		bx	lr
+ 5599              	.LVL389:
+ 5600              	.L454:
+ 5601              	.LCFI46:
+ 5602              		.cfi_restore_state
+2306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+ 5603              		.loc 1 2306 5 is_stmt 1 view .LVU1606
+2307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+ 5604              		.loc 1 2307 5 view .LVU1607
+2308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5605              		.loc 1 2308 5 view .LVU1608
+2311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+ 5606              		.loc 1 2311 5 view .LVU1609
+ 5607 0082 23F47003 		bic	r3, r3, #15728640
+ 5608              	.LVL390:
+2311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+ 5609              		.loc 1 2311 5 is_stmt 0 view .LVU1610
+ 5610 0086 8C6A     		ldr	r4, [r1, #40]
+ARM GAS  /tmp/cc9HXhVl.s 			page 191
+
+
+ 5611 0088 43EA0453 		orr	r3, r3, r4, lsl #20
+ 5612              	.LVL391:
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+ 5613              		.loc 1 2312 5 is_stmt 1 view .LVU1611
+ 5614 008c 23F08073 		bic	r3, r3, #16777216
+ 5615              	.LVL392:
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+ 5616              		.loc 1 2312 5 is_stmt 0 view .LVU1612
+ 5617 0090 0C6A     		ldr	r4, [r1, #32]
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+ 5618              		.loc 1 2312 5 view .LVU1613
+ 5619 0092 2343     		orrs	r3, r3, r4
+ 5620              	.LVL393:
+2313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5621              		.loc 1 2313 5 is_stmt 1 view .LVU1614
+ 5622 0094 23F00073 		bic	r3, r3, #33554432
+ 5623              	.LVL394:
+2313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5624              		.loc 1 2313 5 is_stmt 0 view .LVU1615
+ 5625 0098 4C6A     		ldr	r4, [r1, #36]
+ 5626 009a 2343     		orrs	r3, r3, r4
+ 5627              	.LVL395:
+2315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 5628              		.loc 1 2315 5 is_stmt 1 view .LVU1616
+2315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 5629              		.loc 1 2315 8 is_stmt 0 view .LVU1617
+ 5630 009c 064C     		ldr	r4, .L462
+ 5631 009e A042     		cmp	r0, r4
+ 5632 00a0 03D0     		beq	.L456
+2315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     {
+ 5633              		.loc 1 2315 9 discriminator 1 view .LVU1618
+ 5634 00a2 04F50064 		add	r4, r4, #2048
+ 5635 00a6 A042     		cmp	r0, r4
+ 5636 00a8 E4D1     		bne	.L455
+ 5637              	.L456:
+2318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5638              		.loc 1 2318 7 is_stmt 1 view .LVU1619
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5639              		.loc 1 2321 7 view .LVU1620
+ 5640 00aa 23F00053 		bic	r3, r3, #536870912
+ 5641              	.LVL396:
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5642              		.loc 1 2321 7 is_stmt 0 view .LVU1621
+ 5643 00ae C96A     		ldr	r1, [r1, #44]
+ 5644              	.LVL397:
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5645              		.loc 1 2321 7 view .LVU1622
+ 5646 00b0 0B43     		orrs	r3, r3, r1
+ 5647              	.LVL398:
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5648              		.loc 1 2321 7 view .LVU1623
+ 5649 00b2 DFE7     		b	.L455
+ 5650              	.LVL399:
+ 5651              	.L457:
+ 5652              	.LCFI47:
+ 5653              		.cfi_def_cfa_offset 0
+ 5654              		.cfi_restore 4
+ARM GAS  /tmp/cc9HXhVl.s 			page 192
+
+
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5655              		.loc 1 2279 3 view .LVU1624
+ 5656 00b4 0220     		movs	r0, #2
+ 5657              	.LVL400:
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5658              		.loc 1 2331 1 view .LVU1625
+ 5659 00b6 7047     		bx	lr
+ 5660              	.L463:
+ 5661              		.align	2
+ 5662              	.L462:
+ 5663 00b8 002C0140 		.word	1073818624
+ 5664              		.cfi_endproc
+ 5665              	.LFE359:
+ 5667              		.section	.text.HAL_TIMEx_ConfigBreakInput,"ax",%progbits
+ 5668              		.align	1
+ 5669              		.global	HAL_TIMEx_ConfigBreakInput
+ 5670              		.syntax unified
+ 5671              		.thumb
+ 5672              		.thumb_func
+ 5674              	HAL_TIMEx_ConfigBreakInput:
+ 5675              	.LVL401:
+ 5676              	.LFB360:
+2347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 5677              		.loc 1 2347 1 is_stmt 1 view -0
+ 5678              		.cfi_startproc
+ 5679              		@ args = 0, pretend = 0, frame = 0
+ 5680              		@ frame_needed = 0, uses_anonymous_args = 0
+2347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 5681              		.loc 1 2347 1 is_stmt 0 view .LVU1627
+ 5682 0000 0346     		mov	r3, r0
+2348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmporx;
+ 5683              		.loc 1 2348 3 is_stmt 1 view .LVU1628
+ 5684              	.LVL402:
+2349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t bkin_enable_mask;
+ 5685              		.loc 1 2349 3 view .LVU1629
+2350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t bkin_polarity_mask;
+ 5686              		.loc 1 2350 3 view .LVU1630
+2351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t bkin_enable_bitpos;
+ 5687              		.loc 1 2351 3 view .LVU1631
+2352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t bkin_polarity_bitpos;
+ 5688              		.loc 1 2352 3 view .LVU1632
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5689              		.loc 1 2353 3 view .LVU1633
+2356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUT(BreakInput));
+ 5690              		.loc 1 2356 3 view .LVU1634
+2357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+ 5691              		.loc 1 2357 3 view .LVU1635
+2358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+ 5692              		.loc 1 2358 3 view .LVU1636
+2359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+ 5693              		.loc 1 2359 3 view .LVU1637
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5694              		.loc 1 2360 3 view .LVU1638
+2363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5695              		.loc 1 2363 3 view .LVU1639
+2363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5696              		.loc 1 2363 3 view .LVU1640
+ARM GAS  /tmp/cc9HXhVl.s 			page 193
+
+
+ 5697 0002 90F83C00 		ldrb	r0, [r0, #60]	@ zero_extendqisi2
+ 5698              	.LVL403:
+2363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5699              		.loc 1 2363 3 is_stmt 0 view .LVU1641
+ 5700 0006 0128     		cmp	r0, #1
+ 5701 0008 5ED0     		beq	.L476
+2347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 5702              		.loc 1 2347 1 discriminator 2 view .LVU1642
+ 5703 000a 70B5     		push	{r4, r5, r6, lr}
+ 5704              	.LCFI48:
+ 5705              		.cfi_def_cfa_offset 16
+ 5706              		.cfi_offset 4, -16
+ 5707              		.cfi_offset 5, -12
+ 5708              		.cfi_offset 6, -8
+ 5709              		.cfi_offset 14, -4
+2363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5710              		.loc 1 2363 3 is_stmt 1 discriminator 2 view .LVU1643
+ 5711 000c 0120     		movs	r0, #1
+ 5712 000e 83F83C00 		strb	r0, [r3, #60]
+2363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5713              		.loc 1 2363 3 discriminator 2 view .LVU1644
+2365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5714              		.loc 1 2365 3 discriminator 2 view .LVU1645
+2365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5715              		.loc 1 2365 28 is_stmt 0 discriminator 2 view .LVU1646
+ 5716 0012 1568     		ldr	r5, [r2]
+2365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5717              		.loc 1 2365 3 discriminator 2 view .LVU1647
+ 5718 0014 681E     		subs	r0, r5, #1
+ 5719 0016 0F28     		cmp	r0, #15
+ 5720 0018 29D8     		bhi	.L466
+ 5721 001a DFE800F0 		tbb	[pc, r0]
+ 5722              	.L468:
+ 5723 001e 08       		.byte	(.L472-.L468)/2
+ 5724 001f 2D       		.byte	(.L477-.L468)/2
+ 5725 0020 28       		.byte	(.L466-.L468)/2
+ 5726 0021 0E       		.byte	(.L470-.L468)/2
+ 5727 0022 28       		.byte	(.L466-.L468)/2
+ 5728 0023 28       		.byte	(.L466-.L468)/2
+ 5729 0024 28       		.byte	(.L466-.L468)/2
+ 5730 0025 1C       		.byte	(.L469-.L468)/2
+ 5731 0026 28       		.byte	(.L466-.L468)/2
+ 5732 0027 28       		.byte	(.L466-.L468)/2
+ 5733 0028 28       		.byte	(.L466-.L468)/2
+ 5734 0029 28       		.byte	(.L466-.L468)/2
+ 5735 002a 28       		.byte	(.L466-.L468)/2
+ 5736 002b 28       		.byte	(.L466-.L468)/2
+ 5737 002c 28       		.byte	(.L466-.L468)/2
+ 5738 002d 22       		.byte	(.L467-.L468)/2
+ 5739              		.p2align 1
+ 5740              	.L472:
+2365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5741              		.loc 1 2365 3 view .LVU1648
+ 5742 002e 0920     		movs	r0, #9
+ 5743 0030 4FF0000E 		mov	lr, #0
+ 5744 0034 4FF4007C 		mov	ip, #512
+ 5745 0038 04E0     		b	.L471
+ARM GAS  /tmp/cc9HXhVl.s 			page 194
+
+
+ 5746              	.L470:
+2385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
+ 5747              		.loc 1 2385 7 is_stmt 1 view .LVU1649
+ 5748              	.LVL404:
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKCMP2P;
+ 5749              		.loc 1 2386 7 view .LVU1650
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
+ 5750              		.loc 1 2387 7 view .LVU1651
+2388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5751              		.loc 1 2388 7 view .LVU1652
+2389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5752              		.loc 1 2389 7 view .LVU1653
+2388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5753              		.loc 1 2388 28 is_stmt 0 view .LVU1654
+ 5754 003a 0B20     		movs	r0, #11
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKCMP2P;
+ 5755              		.loc 1 2386 26 view .LVU1655
+ 5756 003c 4FF0020E 		mov	lr, #2
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
+ 5757              		.loc 1 2387 26 view .LVU1656
+ 5758 0040 4FF4006C 		mov	ip, #2048
+ 5759              	.LVL405:
+ 5760              	.L471:
+2451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 5761              		.loc 1 2451 3 is_stmt 1 view .LVU1657
+ 5762 0044 0129     		cmp	r1, #1
+ 5763 0046 1DD0     		beq	.L473
+ 5764 0048 0229     		cmp	r1, #2
+ 5765 004a 2CD0     		beq	.L474
+ 5766 004c 0120     		movs	r0, #1
+ 5767              	.LVL406:
+ 5768              	.L475:
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5769              		.loc 1 2492 3 view .LVU1658
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5770              		.loc 1 2492 3 view .LVU1659
+ 5771 004e 0022     		movs	r2, #0
+ 5772 0050 83F83C20 		strb	r2, [r3, #60]
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5773              		.loc 1 2492 3 view .LVU1660
+2494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 5774              		.loc 1 2494 3 view .LVU1661
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5775              		.loc 1 2495 1 is_stmt 0 view .LVU1662
+ 5776 0054 70BD     		pop	{r4, r5, r6, pc}
+ 5777              	.LVL407:
+ 5778              	.L469:
+2393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos;
+ 5779              		.loc 1 2393 7 is_stmt 1 view .LVU1663
+2394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKCMP3P;
+ 5780              		.loc 1 2394 7 view .LVU1664
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos;
+ 5781              		.loc 1 2395 7 view .LVU1665
+2396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5782              		.loc 1 2396 7 view .LVU1666
+2397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5783              		.loc 1 2397 7 view .LVU1667
+ARM GAS  /tmp/cc9HXhVl.s 			page 195
+
+
+2396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5784              		.loc 1 2396 28 is_stmt 0 view .LVU1668
+ 5785 0056 0C20     		movs	r0, #12
+2394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKCMP3P;
+ 5786              		.loc 1 2394 26 view .LVU1669
+ 5787 0058 4FF0030E 		mov	lr, #3
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos;
+ 5788              		.loc 1 2395 26 view .LVU1670
+ 5789 005c 4FF4805C 		mov	ip, #4096
+2397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5790              		.loc 1 2397 7 view .LVU1671
+ 5791 0060 F0E7     		b	.L471
+ 5792              	.LVL408:
+ 5793              	.L467:
+2401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKCMP4E_Pos;
+ 5794              		.loc 1 2401 7 is_stmt 1 view .LVU1672
+2402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKCMP4P;
+ 5795              		.loc 1 2402 7 view .LVU1673
+2403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos;
+ 5796              		.loc 1 2403 7 view .LVU1674
+2404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5797              		.loc 1 2404 7 view .LVU1675
+2405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5798              		.loc 1 2405 7 view .LVU1676
+2404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5799              		.loc 1 2404 28 is_stmt 0 view .LVU1677
+ 5800 0062 0D20     		movs	r0, #13
+2402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKCMP4P;
+ 5801              		.loc 1 2402 26 view .LVU1678
+ 5802 0064 4FF0040E 		mov	lr, #4
+2403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos;
+ 5803              		.loc 1 2403 26 view .LVU1679
+ 5804 0068 4FF4005C 		mov	ip, #8192
+2405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5805              		.loc 1 2405 7 view .LVU1680
+ 5806 006c EAE7     		b	.L471
+ 5807              	.LVL409:
+ 5808              	.L466:
+2443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = 0U;
+ 5809              		.loc 1 2443 7 is_stmt 1 view .LVU1681
+2444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = 0U;
+ 5810              		.loc 1 2444 7 view .LVU1682
+2445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = 0U;
+ 5811              		.loc 1 2445 7 view .LVU1683
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5812              		.loc 1 2446 7 view .LVU1684
+2447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5813              		.loc 1 2447 7 view .LVU1685
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5814              		.loc 1 2446 28 is_stmt 0 view .LVU1686
+ 5815 006e 0020     		movs	r0, #0
+2445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = 0U;
+ 5816              		.loc 1 2445 26 view .LVU1687
+ 5817 0070 8646     		mov	lr, r0
+2444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_enable_bitpos = 0U;
+ 5818              		.loc 1 2444 26 view .LVU1688
+ 5819 0072 8446     		mov	ip, r0
+ARM GAS  /tmp/cc9HXhVl.s 			page 196
+
+
+2443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = 0U;
+ 5820              		.loc 1 2443 24 view .LVU1689
+ 5821 0074 0546     		mov	r5, r0
+2447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5822              		.loc 1 2447 7 view .LVU1690
+ 5823 0076 E5E7     		b	.L471
+ 5824              	.LVL410:
+ 5825              	.L477:
+2380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5826              		.loc 1 2380 28 view .LVU1691
+ 5827 0078 0A20     		movs	r0, #10
+2378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKCMP1P;
+ 5828              		.loc 1 2378 26 view .LVU1692
+ 5829 007a 4FF0010E 		mov	lr, #1
+2379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
+ 5830              		.loc 1 2379 26 view .LVU1693
+ 5831 007e 4FF4806C 		mov	ip, #1024
+ 5832 0082 DFE7     		b	.L471
+ 5833              	.LVL411:
+ 5834              	.L473:
+2456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5835              		.loc 1 2456 7 is_stmt 1 view .LVU1694
+2456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5836              		.loc 1 2456 20 is_stmt 0 view .LVU1695
+ 5837 0084 1C68     		ldr	r4, [r3]
+2456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5838              		.loc 1 2456 14 view .LVU1696
+ 5839 0086 266E     		ldr	r6, [r4, #96]
+ 5840              	.LVL412:
+2459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+ 5841              		.loc 1 2459 7 is_stmt 1 view .LVU1697
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5842              		.loc 1 2460 7 view .LVU1698
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5843              		.loc 1 2460 35 is_stmt 0 view .LVU1699
+ 5844 0088 5168     		ldr	r1, [r2, #4]
+ 5845              	.LVL413:
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5846              		.loc 1 2460 44 view .LVU1700
+ 5847 008a 01FA0EF1 		lsl	r1, r1, lr
+ 5848 008e 7140     		eors	r1, r1, r6
+ 5849 0090 2940     		ands	r1, r1, r5
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5850              		.loc 1 2460 14 view .LVU1701
+ 5851 0092 7140     		eors	r1, r1, r6
+ 5852              	.LVL414:
+2463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ 5853              		.loc 1 2463 7 is_stmt 1 view .LVU1702
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5854              		.loc 1 2464 7 view .LVU1703
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5855              		.loc 1 2464 35 is_stmt 0 view .LVU1704
+ 5856 0094 9268     		ldr	r2, [r2, #8]
+ 5857              	.LVL415:
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5858              		.loc 1 2464 46 view .LVU1705
+ 5859 0096 8240     		lsls	r2, r2, r0
+ARM GAS  /tmp/cc9HXhVl.s 			page 197
+
+
+ 5860 0098 4A40     		eors	r2, r2, r1
+ 5861 009a 02EA0C02 		and	r2, r2, ip
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5862              		.loc 1 2464 14 view .LVU1706
+ 5863 009e 4A40     		eors	r2, r2, r1
+ 5864              	.LVL416:
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5865              		.loc 1 2467 7 is_stmt 1 view .LVU1707
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5866              		.loc 1 2467 27 is_stmt 0 view .LVU1708
+ 5867 00a0 2266     		str	r2, [r4, #96]
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5868              		.loc 1 2468 7 is_stmt 1 view .LVU1709
+2348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmporx;
+ 5869              		.loc 1 2348 21 is_stmt 0 view .LVU1710
+ 5870 00a2 0020     		movs	r0, #0
+ 5871              	.LVL417:
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5872              		.loc 1 2468 7 view .LVU1711
+ 5873 00a4 D3E7     		b	.L475
+ 5874              	.LVL418:
+ 5875              	.L474:
+2473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5876              		.loc 1 2473 7 is_stmt 1 view .LVU1712
+2473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5877              		.loc 1 2473 20 is_stmt 0 view .LVU1713
+ 5878 00a6 1C68     		ldr	r4, [r3]
+2473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5879              		.loc 1 2473 14 view .LVU1714
+ 5880 00a8 666E     		ldr	r6, [r4, #100]
+ 5881              	.LVL419:
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+ 5882              		.loc 1 2476 7 is_stmt 1 view .LVU1715
+2477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5883              		.loc 1 2477 7 view .LVU1716
+2477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5884              		.loc 1 2477 35 is_stmt 0 view .LVU1717
+ 5885 00aa 5168     		ldr	r1, [r2, #4]
+ 5886              	.LVL420:
+2477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5887              		.loc 1 2477 44 view .LVU1718
+ 5888 00ac 01FA0EF1 		lsl	r1, r1, lr
+ 5889 00b0 7140     		eors	r1, r1, r6
+ 5890 00b2 2940     		ands	r1, r1, r5
+2477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5891              		.loc 1 2477 14 view .LVU1719
+ 5892 00b4 7140     		eors	r1, r1, r6
+ 5893              	.LVL421:
+2480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ 5894              		.loc 1 2480 7 is_stmt 1 view .LVU1720
+2481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5895              		.loc 1 2481 7 view .LVU1721
+2481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5896              		.loc 1 2481 35 is_stmt 0 view .LVU1722
+ 5897 00b6 9268     		ldr	r2, [r2, #8]
+ 5898              	.LVL422:
+2481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 198
+
+
+ 5899              		.loc 1 2481 46 view .LVU1723
+ 5900 00b8 8240     		lsls	r2, r2, r0
+ 5901 00ba 4A40     		eors	r2, r2, r1
+ 5902 00bc 02EA0C02 		and	r2, r2, ip
+2481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5903              		.loc 1 2481 14 view .LVU1724
+ 5904 00c0 4A40     		eors	r2, r2, r1
+ 5905              	.LVL423:
+2484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5906              		.loc 1 2484 7 is_stmt 1 view .LVU1725
+2484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 5907              		.loc 1 2484 27 is_stmt 0 view .LVU1726
+ 5908 00c2 6266     		str	r2, [r4, #100]
+2485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5909              		.loc 1 2485 7 is_stmt 1 view .LVU1727
+2348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmporx;
+ 5910              		.loc 1 2348 21 is_stmt 0 view .LVU1728
+ 5911 00c4 0020     		movs	r0, #0
+ 5912              	.LVL424:
+2485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     }
+ 5913              		.loc 1 2485 7 view .LVU1729
+ 5914 00c6 C2E7     		b	.L475
+ 5915              	.LVL425:
+ 5916              	.L476:
+ 5917              	.LCFI49:
+ 5918              		.cfi_def_cfa_offset 0
+ 5919              		.cfi_restore 4
+ 5920              		.cfi_restore 5
+ 5921              		.cfi_restore 6
+ 5922              		.cfi_restore 14
+2363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5923              		.loc 1 2363 3 view .LVU1730
+ 5924 00c8 0220     		movs	r0, #2
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5925              		.loc 1 2495 1 view .LVU1731
+ 5926 00ca 7047     		bx	lr
+ 5927              		.cfi_endproc
+ 5928              	.LFE360:
+ 5930              		.section	.text.HAL_TIMEx_RemapConfig,"ax",%progbits
+ 5931              		.align	1
+ 5932              		.global	HAL_TIMEx_RemapConfig
+ 5933              		.syntax unified
+ 5934              		.thumb
+ 5935              		.thumb_func
+ 5937              	HAL_TIMEx_RemapConfig:
+ 5938              	.LVL426:
+ 5939              	.LFB361:
+2608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check parameters */
+ 5940              		.loc 1 2608 1 is_stmt 1 view -0
+ 5941              		.cfi_startproc
+ 5942              		@ args = 0, pretend = 0, frame = 0
+ 5943              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5944              		@ link register save eliminated.
+2610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_REMAP(Remap));
+ 5945              		.loc 1 2610 3 view .LVU1733
+2611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5946              		.loc 1 2611 3 view .LVU1734
+ARM GAS  /tmp/cc9HXhVl.s 			page 199
+
+
+2613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5947              		.loc 1 2613 3 view .LVU1735
+2613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5948              		.loc 1 2613 3 view .LVU1736
+ 5949 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 5950 0004 012B     		cmp	r3, #1
+ 5951 0006 0DD0     		beq	.L484
+2613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5952              		.loc 1 2613 3 discriminator 2 view .LVU1737
+ 5953 0008 0123     		movs	r3, #1
+ 5954 000a 80F83C30 		strb	r3, [r0, #60]
+2613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5955              		.loc 1 2613 3 discriminator 2 view .LVU1738
+2615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5956              		.loc 1 2615 3 discriminator 2 view .LVU1739
+ 5957 000e 0268     		ldr	r2, [r0]
+ 5958 0010 136E     		ldr	r3, [r2, #96]
+ 5959 0012 23F47033 		bic	r3, r3, #245760
+ 5960 0016 1943     		orrs	r1, r1, r3
+ 5961              	.LVL427:
+2615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5962              		.loc 1 2615 3 is_stmt 0 discriminator 2 view .LVU1740
+ 5963 0018 1166     		str	r1, [r2, #96]
+2617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5964              		.loc 1 2617 3 is_stmt 1 discriminator 2 view .LVU1741
+2617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5965              		.loc 1 2617 3 discriminator 2 view .LVU1742
+ 5966 001a 0023     		movs	r3, #0
+ 5967 001c 80F83C30 		strb	r3, [r0, #60]
+2617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5968              		.loc 1 2617 3 discriminator 2 view .LVU1743
+2619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 5969              		.loc 1 2619 3 discriminator 2 view .LVU1744
+2619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 5970              		.loc 1 2619 10 is_stmt 0 discriminator 2 view .LVU1745
+ 5971 0020 1846     		mov	r0, r3
+ 5972              	.LVL428:
+2619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 5973              		.loc 1 2619 10 discriminator 2 view .LVU1746
+ 5974 0022 7047     		bx	lr
+ 5975              	.LVL429:
+ 5976              	.L484:
+2613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5977              		.loc 1 2613 3 view .LVU1747
+ 5978 0024 0220     		movs	r0, #2
+ 5979              	.LVL430:
+2620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 5980              		.loc 1 2620 1 view .LVU1748
+ 5981 0026 7047     		bx	lr
+ 5982              		.cfi_endproc
+ 5983              	.LFE361:
+ 5985              		.section	.text.HAL_TIMEx_TISelection,"ax",%progbits
+ 5986              		.align	1
+ 5987              		.global	HAL_TIMEx_TISelection
+ 5988              		.syntax unified
+ 5989              		.thumb
+ 5990              		.thumb_func
+ARM GAS  /tmp/cc9HXhVl.s 			page 200
+
+
+ 5992              	HAL_TIMEx_TISelection:
+ 5993              	.LVL431:
+ 5994              	.LFB362:
+2782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 5995              		.loc 1 2782 1 is_stmt 1 view -0
+ 5996              		.cfi_startproc
+ 5997              		@ args = 0, pretend = 0, frame = 0
+ 5998              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5999              		@ link register save eliminated.
+2782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 6000              		.loc 1 2782 1 is_stmt 0 view .LVU1750
+ 6001 0000 0346     		mov	r3, r0
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6002              		.loc 1 2783 3 is_stmt 1 view .LVU1751
+ 6003              	.LVL432:
+2786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_TISEL(TISelection));
+ 6004              		.loc 1 2786 3 view .LVU1752
+2787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6005              		.loc 1 2787 3 view .LVU1753
+2789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6006              		.loc 1 2789 3 view .LVU1754
+2789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6007              		.loc 1 2789 3 view .LVU1755
+ 6008 0002 90F83C00 		ldrb	r0, [r0, #60]	@ zero_extendqisi2
+ 6009              	.LVL433:
+2789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6010              		.loc 1 2789 3 is_stmt 0 view .LVU1756
+ 6011 0006 0128     		cmp	r0, #1
+ 6012 0008 44D0     		beq	.L495
+2789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6013              		.loc 1 2789 3 is_stmt 1 discriminator 2 view .LVU1757
+ 6014 000a 0120     		movs	r0, #1
+ 6015 000c 83F83C00 		strb	r0, [r3, #60]
+2789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6016              		.loc 1 2789 3 discriminator 2 view .LVU1758
+2791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 6017              		.loc 1 2791 3 discriminator 2 view .LVU1759
+ 6018 0010 0C2A     		cmp	r2, #12
+ 6019 0012 3AD8     		bhi	.L496
+ 6020 0014 DFE802F0 		tbb	[pc, r2]
+ 6021              	.L489:
+ 6022 0018 07       		.byte	(.L492-.L489)/2
+ 6023 0019 39       		.byte	(.L496-.L489)/2
+ 6024 001a 39       		.byte	(.L496-.L489)/2
+ 6025 001b 39       		.byte	(.L496-.L489)/2
+ 6026 001c 21       		.byte	(.L491-.L489)/2
+ 6027 001d 39       		.byte	(.L496-.L489)/2
+ 6028 001e 39       		.byte	(.L496-.L489)/2
+ 6029 001f 39       		.byte	(.L496-.L489)/2
+ 6030 0020 29       		.byte	(.L490-.L489)/2
+ 6031 0021 39       		.byte	(.L496-.L489)/2
+ 6032 0022 39       		.byte	(.L496-.L489)/2
+ 6033 0023 39       		.byte	(.L496-.L489)/2
+ 6034 0024 31       		.byte	(.L488-.L489)/2
+ 6035 0025 00       		.p2align 1
+ 6036              	.L492:
+2794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 201
+
+
+ 6037              		.loc 1 2794 7 view .LVU1760
+ 6038 0026 1868     		ldr	r0, [r3]
+ 6039 0028 C26D     		ldr	r2, [r0, #92]
+ 6040              	.LVL434:
+2794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6041              		.loc 1 2794 7 is_stmt 0 view .LVU1761
+ 6042 002a 22F00F02 		bic	r2, r2, #15
+ 6043 002e 0A43     		orrs	r2, r2, r1
+ 6044 0030 C265     		str	r2, [r0, #92]
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 6045              		.loc 1 2797 7 is_stmt 1 view .LVU1762
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 6046              		.loc 1 2797 11 is_stmt 0 view .LVU1763
+ 6047 0032 1A68     		ldr	r2, [r3]
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 6048              		.loc 1 2797 10 view .LVU1764
+ 6049 0034 1849     		ldr	r1, .L497
+ 6050              	.LVL435:
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 6051              		.loc 1 2797 10 view .LVU1765
+ 6052 0036 8A42     		cmp	r2, r1
+ 6053 0038 09D0     		beq	.L493
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 6054              		.loc 1 2797 11 discriminator 1 view .LVU1766
+ 6055 003a 01F58061 		add	r1, r1, #1024
+ 6056 003e 8A42     		cmp	r2, r1
+ 6057 0040 05D0     		beq	.L493
+2803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 6058              		.loc 1 2803 9 is_stmt 1 view .LVU1767
+ 6059 0042 916E     		ldr	r1, [r2, #104]
+ 6060 0044 21F00101 		bic	r1, r1, #1
+ 6061 0048 9166     		str	r1, [r2, #104]
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6062              		.loc 1 2783 21 is_stmt 0 view .LVU1768
+ 6063 004a 0020     		movs	r0, #0
+ 6064 004c 1EE0     		b	.L487
+ 6065              	.L493:
+2799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 6066              		.loc 1 2799 9 is_stmt 1 view .LVU1769
+ 6067 004e 916E     		ldr	r1, [r2, #104]
+ 6068 0050 41F00101 		orr	r1, r1, #1
+ 6069 0054 9166     		str	r1, [r2, #104]
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6070              		.loc 1 2783 21 is_stmt 0 view .LVU1770
+ 6071 0056 0020     		movs	r0, #0
+2799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 6072              		.loc 1 2799 9 view .LVU1771
+ 6073 0058 18E0     		b	.L487
+ 6074              	.LVL436:
+ 6075              	.L491:
+2807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 6076              		.loc 1 2807 7 is_stmt 1 view .LVU1772
+ 6077 005a 1868     		ldr	r0, [r3]
+ 6078 005c C26D     		ldr	r2, [r0, #92]
+ 6079              	.LVL437:
+2807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 6080              		.loc 1 2807 7 is_stmt 0 view .LVU1773
+ARM GAS  /tmp/cc9HXhVl.s 			page 202
+
+
+ 6081 005e 22F47062 		bic	r2, r2, #3840
+ 6082 0062 0A43     		orrs	r2, r2, r1
+ 6083 0064 C265     		str	r2, [r0, #92]
+2808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+ 6084              		.loc 1 2808 7 is_stmt 1 view .LVU1774
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6085              		.loc 1 2783 21 is_stmt 0 view .LVU1775
+ 6086 0066 0020     		movs	r0, #0
+2808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+ 6087              		.loc 1 2808 7 view .LVU1776
+ 6088 0068 10E0     		b	.L487
+ 6089              	.LVL438:
+ 6090              	.L490:
+2810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 6091              		.loc 1 2810 7 is_stmt 1 view .LVU1777
+ 6092 006a 1868     		ldr	r0, [r3]
+ 6093 006c C26D     		ldr	r2, [r0, #92]
+ 6094              	.LVL439:
+2810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 6095              		.loc 1 2810 7 is_stmt 0 view .LVU1778
+ 6096 006e 22F47022 		bic	r2, r2, #983040
+ 6097 0072 0A43     		orrs	r2, r2, r1
+ 6098 0074 C265     		str	r2, [r0, #92]
+2811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_4:
+ 6099              		.loc 1 2811 7 is_stmt 1 view .LVU1779
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6100              		.loc 1 2783 21 is_stmt 0 view .LVU1780
+ 6101 0076 0020     		movs	r0, #0
+2811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     case TIM_CHANNEL_4:
+ 6102              		.loc 1 2811 7 view .LVU1781
+ 6103 0078 08E0     		b	.L487
+ 6104              	.LVL440:
+ 6105              	.L488:
+2813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 6106              		.loc 1 2813 7 is_stmt 1 view .LVU1782
+ 6107 007a 1868     		ldr	r0, [r3]
+ 6108 007c C26D     		ldr	r2, [r0, #92]
+ 6109              	.LVL441:
+2813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       break;
+ 6110              		.loc 1 2813 7 is_stmt 0 view .LVU1783
+ 6111 007e 22F07062 		bic	r2, r2, #251658240
+ 6112 0082 0A43     		orrs	r2, r2, r1
+ 6113 0084 C265     		str	r2, [r0, #92]
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+ 6114              		.loc 1 2814 7 is_stmt 1 view .LVU1784
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6115              		.loc 1 2783 21 is_stmt 0 view .LVU1785
+ 6116 0086 0020     		movs	r0, #0
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****     default:
+ 6117              		.loc 1 2814 7 view .LVU1786
+ 6118 0088 00E0     		b	.L487
+ 6119              	.LVL442:
+ 6120              	.L496:
+2791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 6121              		.loc 1 2791 3 view .LVU1787
+ 6122 008a 0120     		movs	r0, #1
+ 6123              	.LVL443:
+ARM GAS  /tmp/cc9HXhVl.s 			page 203
+
+
+ 6124              	.L487:
+2820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6125              		.loc 1 2820 3 is_stmt 1 view .LVU1788
+2820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6126              		.loc 1 2820 3 view .LVU1789
+ 6127 008c 0022     		movs	r2, #0
+ 6128 008e 83F83C20 		strb	r2, [r3, #60]
+2820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6129              		.loc 1 2820 3 view .LVU1790
+2822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6130              		.loc 1 2822 3 view .LVU1791
+2822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6131              		.loc 1 2822 10 is_stmt 0 view .LVU1792
+ 6132 0092 7047     		bx	lr
+ 6133              	.LVL444:
+ 6134              	.L495:
+2789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6135              		.loc 1 2789 3 view .LVU1793
+ 6136 0094 0220     		movs	r0, #2
+2823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6137              		.loc 1 2823 1 view .LVU1794
+ 6138 0096 7047     		bx	lr
+ 6139              	.L498:
+ 6140              		.align	2
+ 6141              	.L497:
+ 6142 0098 00440140 		.word	1073824768
+ 6143              		.cfi_endproc
+ 6144              	.LFE362:
+ 6146              		.section	.text.HAL_TIMEx_GroupChannel5,"ax",%progbits
+ 6147              		.align	1
+ 6148              		.global	HAL_TIMEx_GroupChannel5
+ 6149              		.syntax unified
+ 6150              		.thumb
+ 6151              		.thumb_func
+ 6153              	HAL_TIMEx_GroupChannel5:
+ 6154              	.LVL445:
+ 6155              	.LFB363:
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check parameters */
+ 6156              		.loc 1 2837 1 is_stmt 1 view -0
+ 6157              		.cfi_startproc
+ 6158              		@ args = 0, pretend = 0, frame = 0
+ 6159              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6160              		@ link register save eliminated.
+2839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_GROUPCH5(Channels));
+ 6161              		.loc 1 2839 3 view .LVU1796
+2840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6162              		.loc 1 2840 3 view .LVU1797
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6163              		.loc 1 2843 3 view .LVU1798
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6164              		.loc 1 2843 3 view .LVU1799
+ 6165 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 6166 0004 012B     		cmp	r3, #1
+ 6167 0006 18D0     		beq	.L501
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check parameters */
+ 6168              		.loc 1 2837 1 is_stmt 0 discriminator 2 view .LVU1800
+ 6169 0008 10B4     		push	{r4}
+ARM GAS  /tmp/cc9HXhVl.s 			page 204
+
+
+ 6170              	.LCFI50:
+ 6171              		.cfi_def_cfa_offset 4
+ 6172              		.cfi_offset 4, -4
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6173              		.loc 1 2843 3 is_stmt 1 discriminator 2 view .LVU1801
+ 6174 000a 0122     		movs	r2, #1
+ 6175 000c 80F83C20 		strb	r2, [r0, #60]
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6176              		.loc 1 2843 3 discriminator 2 view .LVU1802
+2845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6177              		.loc 1 2845 3 discriminator 2 view .LVU1803
+2845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6178              		.loc 1 2845 15 is_stmt 0 discriminator 2 view .LVU1804
+ 6179 0010 0223     		movs	r3, #2
+ 6180 0012 80F83D30 		strb	r3, [r0, #61]
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6181              		.loc 1 2848 3 is_stmt 1 discriminator 2 view .LVU1805
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6182              		.loc 1 2848 7 is_stmt 0 discriminator 2 view .LVU1806
+ 6183 0016 0468     		ldr	r4, [r0]
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6184              		.loc 1 2848 17 discriminator 2 view .LVU1807
+ 6185 0018 A36C     		ldr	r3, [r4, #72]
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6186              		.loc 1 2848 24 discriminator 2 view .LVU1808
+ 6187 001a 23F06043 		bic	r3, r3, #-536870912
+ 6188 001e A364     		str	r3, [r4, #72]
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6189              		.loc 1 2851 3 is_stmt 1 discriminator 2 view .LVU1809
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6190              		.loc 1 2851 7 is_stmt 0 discriminator 2 view .LVU1810
+ 6191 0020 0468     		ldr	r4, [r0]
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6192              		.loc 1 2851 17 discriminator 2 view .LVU1811
+ 6193 0022 A36C     		ldr	r3, [r4, #72]
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6194              		.loc 1 2851 24 discriminator 2 view .LVU1812
+ 6195 0024 0B43     		orrs	r3, r3, r1
+ 6196 0026 A364     		str	r3, [r4, #72]
+2854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6197              		.loc 1 2854 3 is_stmt 1 discriminator 2 view .LVU1813
+2854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6198              		.loc 1 2854 15 is_stmt 0 discriminator 2 view .LVU1814
+ 6199 0028 80F83D20 		strb	r2, [r0, #61]
+2856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6200              		.loc 1 2856 3 is_stmt 1 discriminator 2 view .LVU1815
+2856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6201              		.loc 1 2856 3 discriminator 2 view .LVU1816
+ 6202 002c 0023     		movs	r3, #0
+ 6203 002e 80F83C30 		strb	r3, [r0, #60]
+2856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6204              		.loc 1 2856 3 discriminator 2 view .LVU1817
+2858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6205              		.loc 1 2858 3 discriminator 2 view .LVU1818
+2858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6206              		.loc 1 2858 10 is_stmt 0 discriminator 2 view .LVU1819
+ 6207 0032 1846     		mov	r0, r3
+ARM GAS  /tmp/cc9HXhVl.s 			page 205
+
+
+ 6208              	.LVL446:
+2859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6209              		.loc 1 2859 1 discriminator 2 view .LVU1820
+ 6210 0034 5DF8044B 		ldr	r4, [sp], #4
+ 6211              	.LCFI51:
+ 6212              		.cfi_restore 4
+ 6213              		.cfi_def_cfa_offset 0
+ 6214 0038 7047     		bx	lr
+ 6215              	.LVL447:
+ 6216              	.L501:
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6217              		.loc 1 2843 3 view .LVU1821
+ 6218 003a 0220     		movs	r0, #2
+ 6219              	.LVL448:
+2859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6220              		.loc 1 2859 1 view .LVU1822
+ 6221 003c 7047     		bx	lr
+ 6222              		.cfi_endproc
+ 6223              	.LFE363:
+ 6225              		.section	.text.HAL_TIMEx_DisarmBreakInput,"ax",%progbits
+ 6226              		.align	1
+ 6227              		.global	HAL_TIMEx_DisarmBreakInput
+ 6228              		.syntax unified
+ 6229              		.thumb
+ 6230              		.thumb_func
+ 6232              	HAL_TIMEx_DisarmBreakInput:
+ 6233              	.LVL449:
+ 6234              	.LFB364:
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 6235              		.loc 1 2875 1 is_stmt 1 view -0
+ 6236              		.cfi_startproc
+ 6237              		@ args = 0, pretend = 0, frame = 0
+ 6238              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6239              		@ link register save eliminated.
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpbdtr;
+ 6240              		.loc 1 2876 3 view .LVU1824
+2877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6241              		.loc 1 2877 3 view .LVU1825
+2880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUT(BreakInput));
+ 6242              		.loc 1 2880 3 view .LVU1826
+2881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6243              		.loc 1 2881 3 view .LVU1827
+2883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 6244              		.loc 1 2883 3 view .LVU1828
+ 6245 0000 0129     		cmp	r1, #1
+ 6246 0002 03D0     		beq	.L507
+ 6247 0004 0229     		cmp	r1, #2
+ 6248 0006 10D0     		beq	.L508
+ 6249 0008 0120     		movs	r0, #1
+ 6250              	.LVL450:
+2883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 6251              		.loc 1 2883 3 is_stmt 0 view .LVU1829
+ 6252 000a 7047     		bx	lr
+ 6253              	.LVL451:
+ 6254              	.L507:
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
+ 6255              		.loc 1 2888 7 is_stmt 1 view .LVU1830
+ARM GAS  /tmp/cc9HXhVl.s 			page 206
+
+
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
+ 6256              		.loc 1 2888 17 is_stmt 0 view .LVU1831
+ 6257 000c 0268     		ldr	r2, [r0]
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
+ 6258              		.loc 1 2888 15 view .LVU1832
+ 6259 000e 516C     		ldr	r1, [r2, #68]
+ 6260              	.LVL452:
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ 6261              		.loc 1 2889 7 is_stmt 1 view .LVU1833
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ 6262              		.loc 1 2889 65 is_stmt 0 view .LVU1834
+ 6263 0010 0D4B     		ldr	r3, .L514
+ 6264 0012 0B40     		ands	r3, r3, r1
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ 6265              		.loc 1 2889 10 view .LVU1835
+ 6266 0014 B3F1805F 		cmp	r3, #268435456
+ 6267 0018 01D0     		beq	.L512
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpbdtr;
+ 6268              		.loc 1 2876 21 view .LVU1836
+ 6269 001a 0020     		movs	r0, #0
+ 6270              	.LVL453:
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpbdtr;
+ 6271              		.loc 1 2876 21 view .LVU1837
+ 6272 001c 7047     		bx	lr
+ 6273              	.LVL454:
+ 6274              	.L512:
+2893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 6275              		.loc 1 2893 9 is_stmt 1 view .LVU1838
+ 6276 001e 536C     		ldr	r3, [r2, #68]
+ 6277 0020 43F08063 		orr	r3, r3, #67108864
+ 6278 0024 5364     		str	r3, [r2, #68]
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpbdtr;
+ 6279              		.loc 1 2876 21 is_stmt 0 view .LVU1839
+ 6280 0026 0020     		movs	r0, #0
+ 6281              	.LVL455:
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpbdtr;
+ 6282              		.loc 1 2876 21 view .LVU1840
+ 6283 0028 7047     		bx	lr
+ 6284              	.LVL456:
+ 6285              	.L508:
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
+ 6286              		.loc 1 2901 7 is_stmt 1 view .LVU1841
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
+ 6287              		.loc 1 2901 17 is_stmt 0 view .LVU1842
+ 6288 002a 0268     		ldr	r2, [r0]
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
+ 6289              		.loc 1 2901 15 view .LVU1843
+ 6290 002c 516C     		ldr	r1, [r2, #68]
+ 6291              	.LVL457:
+2902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ 6292              		.loc 1 2902 7 is_stmt 1 view .LVU1844
+2902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ 6293              		.loc 1 2902 67 is_stmt 0 view .LVU1845
+ 6294 002e 074B     		ldr	r3, .L514+4
+ 6295 0030 0B40     		ands	r3, r3, r1
+2902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ 6296              		.loc 1 2902 10 view .LVU1846
+ARM GAS  /tmp/cc9HXhVl.s 			page 207
+
+
+ 6297 0032 B3F1005F 		cmp	r3, #536870912
+ 6298 0036 01D0     		beq	.L513
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpbdtr;
+ 6299              		.loc 1 2876 21 view .LVU1847
+ 6300 0038 0020     		movs	r0, #0
+ 6301              	.LVL458:
+2915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6302              		.loc 1 2915 3 is_stmt 1 view .LVU1848
+2916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6303              		.loc 1 2916 1 is_stmt 0 view .LVU1849
+ 6304 003a 7047     		bx	lr
+ 6305              	.LVL459:
+ 6306              	.L513:
+2906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       }
+ 6307              		.loc 1 2906 9 is_stmt 1 view .LVU1850
+ 6308 003c 536C     		ldr	r3, [r2, #68]
+ 6309 003e 43F00063 		orr	r3, r3, #134217728
+ 6310 0042 5364     		str	r3, [r2, #68]
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpbdtr;
+ 6311              		.loc 1 2876 21 is_stmt 0 view .LVU1851
+ 6312 0044 0020     		movs	r0, #0
+ 6313              	.LVL460:
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpbdtr;
+ 6314              		.loc 1 2876 21 view .LVU1852
+ 6315 0046 7047     		bx	lr
+ 6316              	.L515:
+ 6317              		.align	2
+ 6318              	.L514:
+ 6319 0048 00800010 		.word	268468224
+ 6320 004c 00800020 		.word	536903680
+ 6321              		.cfi_endproc
+ 6322              	.LFE364:
+ 6324              		.section	.text.HAL_TIMEx_ReArmBreakInput,"ax",%progbits
+ 6325              		.align	1
+ 6326              		.global	HAL_TIMEx_ReArmBreakInput
+ 6327              		.syntax unified
+ 6328              		.thumb
+ 6329              		.thumb_func
+ 6331              	HAL_TIMEx_ReArmBreakInput:
+ 6332              	.LVL461:
+ 6333              	.LFB365:
+2930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 6334              		.loc 1 2930 1 is_stmt 1 view -0
+ 6335              		.cfi_startproc
+ 6336              		@ args = 0, pretend = 0, frame = 0
+ 6337              		@ frame_needed = 0, uses_anonymous_args = 0
+2930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 6338              		.loc 1 2930 1 is_stmt 0 view .LVU1854
+ 6339 0000 38B5     		push	{r3, r4, r5, lr}
+ 6340              	.LCFI52:
+ 6341              		.cfi_def_cfa_offset 16
+ 6342              		.cfi_offset 3, -16
+ 6343              		.cfi_offset 4, -12
+ 6344              		.cfi_offset 5, -8
+ 6345              		.cfi_offset 14, -4
+ 6346 0002 0446     		mov	r4, r0
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tickstart;
+ARM GAS  /tmp/cc9HXhVl.s 			page 208
+
+
+ 6347              		.loc 1 2931 3 is_stmt 1 view .LVU1855
+ 6348              	.LVL462:
+2932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6349              		.loc 1 2932 3 view .LVU1856
+2935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUT(BreakInput));
+ 6350              		.loc 1 2935 3 view .LVU1857
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6351              		.loc 1 2936 3 view .LVU1858
+2938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   {
+ 6352              		.loc 1 2938 3 view .LVU1859
+ 6353 0004 0129     		cmp	r1, #1
+ 6354 0006 03D0     		beq	.L517
+ 6355 0008 0229     		cmp	r1, #2
+ 6356 000a 1ED0     		beq	.L518
+ 6357 000c 0120     		movs	r0, #1
+ 6358              	.LVL463:
+ 6359              	.L519:
+2991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6360              		.loc 1 2991 1 is_stmt 0 view .LVU1860
+ 6361 000e 38BD     		pop	{r3, r4, r5, pc}
+ 6362              	.LVL464:
+ 6363              	.L517:
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 6364              		.loc 1 2943 7 is_stmt 1 view .LVU1861
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 6365              		.loc 1 2943 11 is_stmt 0 view .LVU1862
+ 6366 0010 0368     		ldr	r3, [r0]
+ 6367 0012 5B6C     		ldr	r3, [r3, #68]
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 6368              		.loc 1 2943 10 view .LVU1863
+ 6369 0014 13F0805F 		tst	r3, #268435456
+ 6370 0018 01D1     		bne	.L529
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tickstart;
+ 6371              		.loc 1 2931 21 view .LVU1864
+ 6372 001a 0020     		movs	r0, #0
+ 6373              	.LVL465:
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tickstart;
+ 6374              		.loc 1 2931 21 view .LVU1865
+ 6375 001c F7E7     		b	.L519
+ 6376              	.LVL466:
+ 6377              	.L529:
+2947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+ 6378              		.loc 1 2947 9 is_stmt 1 view .LVU1866
+2947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+ 6379              		.loc 1 2947 21 is_stmt 0 view .LVU1867
+ 6380 001e FFF7FEFF 		bl	HAL_GetTick
+ 6381              	.LVL467:
+2947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+ 6382              		.loc 1 2947 21 view .LVU1868
+ 6383 0022 0546     		mov	r5, r0
+ 6384              	.LVL468:
+2948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         {
+ 6385              		.loc 1 2948 9 is_stmt 1 view .LVU1869
+ 6386              	.L520:
+2948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         {
+ 6387              		.loc 1 2948 64 view .LVU1870
+2948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         {
+ARM GAS  /tmp/cc9HXhVl.s 			page 209
+
+
+ 6388              		.loc 1 2948 16 is_stmt 0 view .LVU1871
+ 6389 0024 2368     		ldr	r3, [r4]
+ 6390 0026 5B6C     		ldr	r3, [r3, #68]
+2948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         {
+ 6391              		.loc 1 2948 64 view .LVU1872
+ 6392 0028 13F0806F 		tst	r3, #67108864
+ 6393 002c 0BD0     		beq	.L530
+2950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           {
+ 6394              		.loc 1 2950 11 is_stmt 1 view .LVU1873
+2950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           {
+ 6395              		.loc 1 2950 16 is_stmt 0 view .LVU1874
+ 6396 002e FFF7FEFF 		bl	HAL_GetTick
+ 6397              	.LVL469:
+2950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           {
+ 6398              		.loc 1 2950 30 view .LVU1875
+ 6399 0032 401B     		subs	r0, r0, r5
+2950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           {
+ 6400              		.loc 1 2950 14 view .LVU1876
+ 6401 0034 0528     		cmp	r0, #5
+ 6402 0036 F5D9     		bls	.L520
+2953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             {
+ 6403              		.loc 1 2953 13 is_stmt 1 view .LVU1877
+2953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             {
+ 6404              		.loc 1 2953 17 is_stmt 0 view .LVU1878
+ 6405 0038 2368     		ldr	r3, [r4]
+ 6406 003a 5B6C     		ldr	r3, [r3, #68]
+2953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             {
+ 6407              		.loc 1 2953 16 view .LVU1879
+ 6408 003c 13F0806F 		tst	r3, #67108864
+ 6409 0040 F0D0     		beq	.L520
+2955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             }
+ 6410              		.loc 1 2955 22 view .LVU1880
+ 6411 0042 0320     		movs	r0, #3
+ 6412 0044 E3E7     		b	.L519
+ 6413              	.L530:
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tickstart;
+ 6414              		.loc 1 2931 21 view .LVU1881
+ 6415 0046 0020     		movs	r0, #0
+ 6416 0048 E1E7     		b	.L519
+ 6417              	.LVL470:
+ 6418              	.L518:
+2966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 6419              		.loc 1 2966 7 is_stmt 1 view .LVU1882
+2966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 6420              		.loc 1 2966 11 is_stmt 0 view .LVU1883
+ 6421 004a 0368     		ldr	r3, [r0]
+ 6422 004c 5B6C     		ldr	r3, [r3, #68]
+2966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****       {
+ 6423              		.loc 1 2966 10 view .LVU1884
+ 6424 004e 13F0005F 		tst	r3, #536870912
+ 6425 0052 01D1     		bne	.L531
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tickstart;
+ 6426              		.loc 1 2931 21 view .LVU1885
+ 6427 0054 0020     		movs	r0, #0
+ 6428              	.LVL471:
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tickstart;
+ 6429              		.loc 1 2931 21 view .LVU1886
+ARM GAS  /tmp/cc9HXhVl.s 			page 210
+
+
+ 6430 0056 DAE7     		b	.L519
+ 6431              	.LVL472:
+ 6432              	.L531:
+2970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+ 6433              		.loc 1 2970 9 is_stmt 1 view .LVU1887
+2970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+ 6434              		.loc 1 2970 21 is_stmt 0 view .LVU1888
+ 6435 0058 FFF7FEFF 		bl	HAL_GetTick
+ 6436              	.LVL473:
+2970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+ 6437              		.loc 1 2970 21 view .LVU1889
+ 6438 005c 0546     		mov	r5, r0
+ 6439              	.LVL474:
+2971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         {
+ 6440              		.loc 1 2971 9 is_stmt 1 view .LVU1890
+ 6441              	.L522:
+2971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         {
+ 6442              		.loc 1 2971 65 view .LVU1891
+2971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         {
+ 6443              		.loc 1 2971 16 is_stmt 0 view .LVU1892
+ 6444 005e 2368     		ldr	r3, [r4]
+ 6445 0060 5B6C     		ldr	r3, [r3, #68]
+2971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****         {
+ 6446              		.loc 1 2971 65 view .LVU1893
+ 6447 0062 13F0006F 		tst	r3, #134217728
+ 6448 0066 0BD0     		beq	.L532
+2973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           {
+ 6449              		.loc 1 2973 11 is_stmt 1 view .LVU1894
+2973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           {
+ 6450              		.loc 1 2973 16 is_stmt 0 view .LVU1895
+ 6451 0068 FFF7FEFF 		bl	HAL_GetTick
+ 6452              	.LVL475:
+2973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           {
+ 6453              		.loc 1 2973 30 view .LVU1896
+ 6454 006c 401B     		subs	r0, r0, r5
+2973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****           {
+ 6455              		.loc 1 2973 14 view .LVU1897
+ 6456 006e 0528     		cmp	r0, #5
+ 6457 0070 F5D9     		bls	.L522
+2976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             {
+ 6458              		.loc 1 2976 13 is_stmt 1 view .LVU1898
+2976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             {
+ 6459              		.loc 1 2976 17 is_stmt 0 view .LVU1899
+ 6460 0072 2368     		ldr	r3, [r4]
+ 6461 0074 5B6C     		ldr	r3, [r3, #68]
+2976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             {
+ 6462              		.loc 1 2976 16 view .LVU1900
+ 6463 0076 13F0006F 		tst	r3, #134217728
+ 6464 007a F0D0     		beq	.L522
+2978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****             }
+ 6465              		.loc 1 2978 22 view .LVU1901
+ 6466 007c 0320     		movs	r0, #3
+ 6467 007e C6E7     		b	.L519
+ 6468              	.L532:
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tickstart;
+ 6469              		.loc 1 2931 21 view .LVU1902
+ 6470 0080 0020     		movs	r0, #0
+ARM GAS  /tmp/cc9HXhVl.s 			page 211
+
+
+ 6471 0082 C4E7     		b	.L519
+ 6472              		.cfi_endproc
+ 6473              	.LFE365:
+ 6475              		.section	.text.HAL_TIMEx_DitheringEnable,"ax",%progbits
+ 6476              		.align	1
+ 6477              		.global	HAL_TIMEx_DitheringEnable
+ 6478              		.syntax unified
+ 6479              		.thumb
+ 6480              		.thumb_func
+ 6482              	HAL_TIMEx_DitheringEnable:
+ 6483              	.LVL476:
+ 6484              	.LFB366:
+3013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6485              		.loc 1 3013 1 is_stmt 1 view -0
+ 6486              		.cfi_startproc
+ 6487              		@ args = 0, pretend = 0, frame = 0
+ 6488              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6489              		@ link register save eliminated.
+3015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6490              		.loc 1 3015 3 view .LVU1904
+3017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 6491              		.loc 1 3017 3 view .LVU1905
+ 6492 0000 0268     		ldr	r2, [r0]
+ 6493 0002 1368     		ldr	r3, [r2]
+ 6494 0004 43F48053 		orr	r3, r3, #4096
+ 6495 0008 1360     		str	r3, [r2]
+3018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6496              		.loc 1 3018 3 view .LVU1906
+3019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6497              		.loc 1 3019 1 is_stmt 0 view .LVU1907
+ 6498 000a 0020     		movs	r0, #0
+ 6499              	.LVL477:
+3019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6500              		.loc 1 3019 1 view .LVU1908
+ 6501 000c 7047     		bx	lr
+ 6502              		.cfi_endproc
+ 6503              	.LFE366:
+ 6505              		.section	.text.HAL_TIMEx_DitheringDisable,"ax",%progbits
+ 6506              		.align	1
+ 6507              		.global	HAL_TIMEx_DitheringDisable
+ 6508              		.syntax unified
+ 6509              		.thumb
+ 6510              		.thumb_func
+ 6512              	HAL_TIMEx_DitheringDisable:
+ 6513              	.LVL478:
+ 6514              	.LFB367:
+3037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6515              		.loc 1 3037 1 is_stmt 1 view -0
+ 6516              		.cfi_startproc
+ 6517              		@ args = 0, pretend = 0, frame = 0
+ 6518              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6519              		@ link register save eliminated.
+3039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6520              		.loc 1 3039 3 view .LVU1910
+3041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 6521              		.loc 1 3041 3 view .LVU1911
+ 6522 0000 0268     		ldr	r2, [r0]
+ARM GAS  /tmp/cc9HXhVl.s 			page 212
+
+
+ 6523 0002 1368     		ldr	r3, [r2]
+ 6524 0004 23F48053 		bic	r3, r3, #4096
+ 6525 0008 1360     		str	r3, [r2]
+3042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6526              		.loc 1 3042 3 view .LVU1912
+3043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6527              		.loc 1 3043 1 is_stmt 0 view .LVU1913
+ 6528 000a 0020     		movs	r0, #0
+ 6529              	.LVL479:
+3043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6530              		.loc 1 3043 1 view .LVU1914
+ 6531 000c 7047     		bx	lr
+ 6532              		.cfi_endproc
+ 6533              	.LFE367:
+ 6535              		.section	.text.HAL_TIMEx_OC_ConfigPulseOnCompare,"ax",%progbits
+ 6536              		.align	1
+ 6537              		.global	HAL_TIMEx_OC_ConfigPulseOnCompare
+ 6538              		.syntax unified
+ 6539              		.thumb
+ 6540              		.thumb_func
+ 6542              	HAL_TIMEx_OC_ConfigPulseOnCompare:
+ 6543              	.LVL480:
+ 6544              	.LFB368:
+3057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpecr;
+ 6545              		.loc 1 3057 1 is_stmt 1 view -0
+ 6546              		.cfi_startproc
+ 6547              		@ args = 0, pretend = 0, frame = 0
+ 6548              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6549              		@ link register save eliminated.
+3058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6550              		.loc 1 3058 3 view .LVU1916
+3061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
+ 6551              		.loc 1 3061 3 view .LVU1917
+3062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
+ 6552              		.loc 1 3062 3 view .LVU1918
+3063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6553              		.loc 1 3063 3 view .LVU1919
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6554              		.loc 1 3066 3 view .LVU1920
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6555              		.loc 1 3066 3 view .LVU1921
+ 6556 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 6557 0004 012B     		cmp	r3, #1
+ 6558 0006 1BD0     		beq	.L537
+3057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   uint32_t tmpecr;
+ 6559              		.loc 1 3057 1 is_stmt 0 discriminator 2 view .LVU1922
+ 6560 0008 10B4     		push	{r4}
+ 6561              	.LCFI53:
+ 6562              		.cfi_def_cfa_offset 4
+ 6563              		.cfi_offset 4, -4
+ 6564 000a 8446     		mov	ip, r0
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6565              		.loc 1 3066 3 is_stmt 1 discriminator 2 view .LVU1923
+ 6566 000c 0120     		movs	r0, #1
+ 6567              	.LVL481:
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6568              		.loc 1 3066 3 is_stmt 0 discriminator 2 view .LVU1924
+ARM GAS  /tmp/cc9HXhVl.s 			page 213
+
+
+ 6569 000e 8CF83C00 		strb	r0, [ip, #60]
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6570              		.loc 1 3066 3 is_stmt 1 discriminator 2 view .LVU1925
+3069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6571              		.loc 1 3069 3 discriminator 2 view .LVU1926
+3069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6572              		.loc 1 3069 15 is_stmt 0 discriminator 2 view .LVU1927
+ 6573 0012 0223     		movs	r3, #2
+ 6574 0014 8CF83D30 		strb	r3, [ip, #61]
+3072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Reset the Pulse width prescaler and the Pulse width */
+ 6575              		.loc 1 3072 3 is_stmt 1 discriminator 2 view .LVU1928
+3072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Reset the Pulse width prescaler and the Pulse width */
+ 6576              		.loc 1 3072 16 is_stmt 0 discriminator 2 view .LVU1929
+ 6577 0018 DCF80040 		ldr	r4, [ip]
+3072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Reset the Pulse width prescaler and the Pulse width */
+ 6578              		.loc 1 3072 10 discriminator 2 view .LVU1930
+ 6579 001c A36D     		ldr	r3, [r4, #88]
+ 6580              	.LVL482:
+3074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the Pulse width prescaler and Pulse width*/
+ 6581              		.loc 1 3074 3 is_stmt 1 discriminator 2 view .LVU1931
+3074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the Pulse width prescaler and Pulse width*/
+ 6582              		.loc 1 3074 10 is_stmt 0 discriminator 2 view .LVU1932
+ 6583 001e 23F0FF63 		bic	r3, r3, #133693440
+ 6584              	.LVL483:
+3074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Set the Pulse width prescaler and Pulse width*/
+ 6585              		.loc 1 3074 10 discriminator 2 view .LVU1933
+ 6586 0022 23F4E023 		bic	r3, r3, #458752
+ 6587              	.LVL484:
+3076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
+ 6588              		.loc 1 3076 3 is_stmt 1 discriminator 2 view .LVU1934
+3076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
+ 6589              		.loc 1 3076 10 is_stmt 0 discriminator 2 view .LVU1935
+ 6590 0026 43EA0163 		orr	r3, r3, r1, lsl #24
+ 6591              	.LVL485:
+3077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Write to TIMx ECR */
+ 6592              		.loc 1 3077 3 is_stmt 1 discriminator 2 view .LVU1936
+3077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Write to TIMx ECR */
+ 6593              		.loc 1 3077 10 is_stmt 0 discriminator 2 view .LVU1937
+ 6594 002a 43EA0242 		orr	r2, r3, r2, lsl #16
+ 6595              	.LVL486:
+3079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6596              		.loc 1 3079 3 is_stmt 1 discriminator 2 view .LVU1938
+3079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6597              		.loc 1 3079 23 is_stmt 0 discriminator 2 view .LVU1939
+ 6598 002e A265     		str	r2, [r4, #88]
+3082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6599              		.loc 1 3082 3 is_stmt 1 discriminator 2 view .LVU1940
+3082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6600              		.loc 1 3082 15 is_stmt 0 discriminator 2 view .LVU1941
+ 6601 0030 8CF83D00 		strb	r0, [ip, #61]
+3085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6602              		.loc 1 3085 3 is_stmt 1 discriminator 2 view .LVU1942
+3085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6603              		.loc 1 3085 3 discriminator 2 view .LVU1943
+ 6604 0034 0020     		movs	r0, #0
+ 6605 0036 8CF83C00 		strb	r0, [ip, #60]
+3085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 214
+
+
+ 6606              		.loc 1 3085 3 discriminator 2 view .LVU1944
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6607              		.loc 1 3087 3 discriminator 2 view .LVU1945
+3088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6608              		.loc 1 3088 1 is_stmt 0 discriminator 2 view .LVU1946
+ 6609 003a 5DF8044B 		ldr	r4, [sp], #4
+ 6610              	.LCFI54:
+ 6611              		.cfi_restore 4
+ 6612              		.cfi_def_cfa_offset 0
+ 6613 003e 7047     		bx	lr
+ 6614              	.LVL487:
+ 6615              	.L537:
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6616              		.loc 1 3066 3 view .LVU1947
+ 6617 0040 0220     		movs	r0, #2
+ 6618              	.LVL488:
+3088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6619              		.loc 1 3088 1 view .LVU1948
+ 6620 0042 7047     		bx	lr
+ 6621              		.cfi_endproc
+ 6622              	.LFE368:
+ 6624              		.section	.text.HAL_TIMEx_ConfigSlaveModePreload,"ax",%progbits
+ 6625              		.align	1
+ 6626              		.global	HAL_TIMEx_ConfigSlaveModePreload
+ 6627              		.syntax unified
+ 6628              		.thumb
+ 6629              		.thumb_func
+ 6631              	HAL_TIMEx_ConfigSlaveModePreload:
+ 6632              	.LVL489:
+ 6633              	.LFB369:
+3100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6634              		.loc 1 3100 1 is_stmt 1 view -0
+ 6635              		.cfi_startproc
+ 6636              		@ args = 0, pretend = 0, frame = 0
+ 6637              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6638              		@ link register save eliminated.
+3102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
+ 6639              		.loc 1 3102 3 view .LVU1950
+3103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6640              		.loc 1 3103 3 view .LVU1951
+3105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 6641              		.loc 1 3105 3 view .LVU1952
+ 6642 0000 0268     		ldr	r2, [r0]
+ 6643 0002 9368     		ldr	r3, [r2, #8]
+ 6644 0004 23F00073 		bic	r3, r3, #33554432
+ 6645 0008 0B43     		orrs	r3, r3, r1
+ 6646 000a 9360     		str	r3, [r2, #8]
+3106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6647              		.loc 1 3106 3 view .LVU1953
+3107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6648              		.loc 1 3107 1 is_stmt 0 view .LVU1954
+ 6649 000c 0020     		movs	r0, #0
+ 6650              	.LVL490:
+3107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6651              		.loc 1 3107 1 view .LVU1955
+ 6652 000e 7047     		bx	lr
+ 6653              		.cfi_endproc
+ARM GAS  /tmp/cc9HXhVl.s 			page 215
+
+
+ 6654              	.LFE369:
+ 6656              		.section	.text.HAL_TIMEx_EnableSlaveModePreload,"ax",%progbits
+ 6657              		.align	1
+ 6658              		.global	HAL_TIMEx_EnableSlaveModePreload
+ 6659              		.syntax unified
+ 6660              		.thumb
+ 6661              		.thumb_func
+ 6663              	HAL_TIMEx_EnableSlaveModePreload:
+ 6664              	.LVL491:
+ 6665              	.LFB370:
+3115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6666              		.loc 1 3115 1 is_stmt 1 view -0
+ 6667              		.cfi_startproc
+ 6668              		@ args = 0, pretend = 0, frame = 0
+ 6669              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6670              		@ link register save eliminated.
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6671              		.loc 1 3117 3 view .LVU1957
+3119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 6672              		.loc 1 3119 3 view .LVU1958
+ 6673 0000 0268     		ldr	r2, [r0]
+ 6674 0002 9368     		ldr	r3, [r2, #8]
+ 6675 0004 43F08073 		orr	r3, r3, #16777216
+ 6676 0008 9360     		str	r3, [r2, #8]
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6677              		.loc 1 3120 3 view .LVU1959
+3121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6678              		.loc 1 3121 1 is_stmt 0 view .LVU1960
+ 6679 000a 0020     		movs	r0, #0
+ 6680              	.LVL492:
+3121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6681              		.loc 1 3121 1 view .LVU1961
+ 6682 000c 7047     		bx	lr
+ 6683              		.cfi_endproc
+ 6684              	.LFE370:
+ 6686              		.section	.text.HAL_TIMEx_DisableSlaveModePreload,"ax",%progbits
+ 6687              		.align	1
+ 6688              		.global	HAL_TIMEx_DisableSlaveModePreload
+ 6689              		.syntax unified
+ 6690              		.thumb
+ 6691              		.thumb_func
+ 6693              	HAL_TIMEx_DisableSlaveModePreload:
+ 6694              	.LVL493:
+ 6695              	.LFB371:
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6696              		.loc 1 3129 1 is_stmt 1 view -0
+ 6697              		.cfi_startproc
+ 6698              		@ args = 0, pretend = 0, frame = 0
+ 6699              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6700              		@ link register save eliminated.
+3131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6701              		.loc 1 3131 3 view .LVU1963
+3133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 6702              		.loc 1 3133 3 view .LVU1964
+ 6703 0000 0268     		ldr	r2, [r0]
+ 6704 0002 9368     		ldr	r3, [r2, #8]
+ 6705 0004 23F08073 		bic	r3, r3, #16777216
+ARM GAS  /tmp/cc9HXhVl.s 			page 216
+
+
+ 6706 0008 9360     		str	r3, [r2, #8]
+3134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6707              		.loc 1 3134 3 view .LVU1965
+3135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6708              		.loc 1 3135 1 is_stmt 0 view .LVU1966
+ 6709 000a 0020     		movs	r0, #0
+ 6710              	.LVL494:
+3135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6711              		.loc 1 3135 1 view .LVU1967
+ 6712 000c 7047     		bx	lr
+ 6713              		.cfi_endproc
+ 6714              	.LFE371:
+ 6716              		.section	.text.HAL_TIMEx_EnableDeadTimePreload,"ax",%progbits
+ 6717              		.align	1
+ 6718              		.global	HAL_TIMEx_EnableDeadTimePreload
+ 6719              		.syntax unified
+ 6720              		.thumb
+ 6721              		.thumb_func
+ 6723              	HAL_TIMEx_EnableDeadTimePreload:
+ 6724              	.LVL495:
+ 6725              	.LFB372:
+3143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6726              		.loc 1 3143 1 is_stmt 1 view -0
+ 6727              		.cfi_startproc
+ 6728              		@ args = 0, pretend = 0, frame = 0
+ 6729              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6730              		@ link register save eliminated.
+3145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6731              		.loc 1 3145 3 view .LVU1969
+3147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 6732              		.loc 1 3147 3 view .LVU1970
+ 6733 0000 0268     		ldr	r2, [r0]
+ 6734 0002 536D     		ldr	r3, [r2, #84]
+ 6735 0004 43F40033 		orr	r3, r3, #131072
+ 6736 0008 5365     		str	r3, [r2, #84]
+3148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6737              		.loc 1 3148 3 view .LVU1971
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6738              		.loc 1 3149 1 is_stmt 0 view .LVU1972
+ 6739 000a 0020     		movs	r0, #0
+ 6740              	.LVL496:
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6741              		.loc 1 3149 1 view .LVU1973
+ 6742 000c 7047     		bx	lr
+ 6743              		.cfi_endproc
+ 6744              	.LFE372:
+ 6746              		.section	.text.HAL_TIMEx_DisableDeadTimePreload,"ax",%progbits
+ 6747              		.align	1
+ 6748              		.global	HAL_TIMEx_DisableDeadTimePreload
+ 6749              		.syntax unified
+ 6750              		.thumb
+ 6751              		.thumb_func
+ 6753              	HAL_TIMEx_DisableDeadTimePreload:
+ 6754              	.LVL497:
+ 6755              	.LFB373:
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6756              		.loc 1 3157 1 is_stmt 1 view -0
+ARM GAS  /tmp/cc9HXhVl.s 			page 217
+
+
+ 6757              		.cfi_startproc
+ 6758              		@ args = 0, pretend = 0, frame = 0
+ 6759              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6760              		@ link register save eliminated.
+3159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6761              		.loc 1 3159 3 view .LVU1975
+3161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 6762              		.loc 1 3161 3 view .LVU1976
+ 6763 0000 0268     		ldr	r2, [r0]
+ 6764 0002 536D     		ldr	r3, [r2, #84]
+ 6765 0004 23F40033 		bic	r3, r3, #131072
+ 6766 0008 5365     		str	r3, [r2, #84]
+3162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6767              		.loc 1 3162 3 view .LVU1977
+3163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6768              		.loc 1 3163 1 is_stmt 0 view .LVU1978
+ 6769 000a 0020     		movs	r0, #0
+ 6770              	.LVL498:
+3163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6771              		.loc 1 3163 1 view .LVU1979
+ 6772 000c 7047     		bx	lr
+ 6773              		.cfi_endproc
+ 6774              	.LFE373:
+ 6776              		.section	.text.HAL_TIMEx_ConfigDeadTime,"ax",%progbits
+ 6777              		.align	1
+ 6778              		.global	HAL_TIMEx_ConfigDeadTime
+ 6779              		.syntax unified
+ 6780              		.thumb
+ 6781              		.thumb_func
+ 6783              	HAL_TIMEx_ConfigDeadTime:
+ 6784              	.LVL499:
+ 6785              	.LFB374:
+3173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6786              		.loc 1 3173 1 is_stmt 1 view -0
+ 6787              		.cfi_startproc
+ 6788              		@ args = 0, pretend = 0, frame = 0
+ 6789              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6790              		@ link register save eliminated.
+3175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_DEADTIME(Deadtime));
+ 6791              		.loc 1 3175 3 view .LVU1981
+3176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6792              		.loc 1 3176 3 view .LVU1982
+3178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 6793              		.loc 1 3178 3 view .LVU1983
+ 6794 0000 0268     		ldr	r2, [r0]
+ 6795 0002 536C     		ldr	r3, [r2, #68]
+ 6796 0004 23F0FF03 		bic	r3, r3, #255
+ 6797 0008 0B43     		orrs	r3, r3, r1
+ 6798 000a 5364     		str	r3, [r2, #68]
+3179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6799              		.loc 1 3179 3 view .LVU1984
+3180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6800              		.loc 1 3180 1 is_stmt 0 view .LVU1985
+ 6801 000c 0020     		movs	r0, #0
+ 6802              	.LVL500:
+3180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6803              		.loc 1 3180 1 view .LVU1986
+ARM GAS  /tmp/cc9HXhVl.s 			page 218
+
+
+ 6804 000e 7047     		bx	lr
+ 6805              		.cfi_endproc
+ 6806              	.LFE374:
+ 6808              		.section	.text.HAL_TIMEx_ConfigAsymmetricalDeadTime,"ax",%progbits
+ 6809              		.align	1
+ 6810              		.global	HAL_TIMEx_ConfigAsymmetricalDeadTime
+ 6811              		.syntax unified
+ 6812              		.thumb
+ 6813              		.thumb_func
+ 6815              	HAL_TIMEx_ConfigAsymmetricalDeadTime:
+ 6816              	.LVL501:
+ 6817              	.LFB375:
+3190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6818              		.loc 1 3190 1 is_stmt 1 view -0
+ 6819              		.cfi_startproc
+ 6820              		@ args = 0, pretend = 0, frame = 0
+ 6821              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6822              		@ link register save eliminated.
+3192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_DEADTIME(FallingDeadtime));
+ 6823              		.loc 1 3192 3 view .LVU1988
+3193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6824              		.loc 1 3193 3 view .LVU1989
+3195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 6825              		.loc 1 3195 3 view .LVU1990
+ 6826 0000 0268     		ldr	r2, [r0]
+ 6827 0002 536D     		ldr	r3, [r2, #84]
+ 6828 0004 23F0FF03 		bic	r3, r3, #255
+ 6829 0008 0B43     		orrs	r3, r3, r1
+ 6830 000a 5365     		str	r3, [r2, #84]
+3196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6831              		.loc 1 3196 3 view .LVU1991
+3197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6832              		.loc 1 3197 1 is_stmt 0 view .LVU1992
+ 6833 000c 0020     		movs	r0, #0
+ 6834              	.LVL502:
+3197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6835              		.loc 1 3197 1 view .LVU1993
+ 6836 000e 7047     		bx	lr
+ 6837              		.cfi_endproc
+ 6838              	.LFE375:
+ 6840              		.section	.text.HAL_TIMEx_EnableAsymmetricalDeadTime,"ax",%progbits
+ 6841              		.align	1
+ 6842              		.global	HAL_TIMEx_EnableAsymmetricalDeadTime
+ 6843              		.syntax unified
+ 6844              		.thumb
+ 6845              		.thumb_func
+ 6847              	HAL_TIMEx_EnableAsymmetricalDeadTime:
+ 6848              	.LVL503:
+ 6849              	.LFB376:
+3205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6850              		.loc 1 3205 1 is_stmt 1 view -0
+ 6851              		.cfi_startproc
+ 6852              		@ args = 0, pretend = 0, frame = 0
+ 6853              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6854              		@ link register save eliminated.
+3207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6855              		.loc 1 3207 3 view .LVU1995
+ARM GAS  /tmp/cc9HXhVl.s 			page 219
+
+
+3209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 6856              		.loc 1 3209 3 view .LVU1996
+ 6857 0000 0268     		ldr	r2, [r0]
+ 6858 0002 536D     		ldr	r3, [r2, #84]
+ 6859 0004 43F48033 		orr	r3, r3, #65536
+ 6860 0008 5365     		str	r3, [r2, #84]
+3210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6861              		.loc 1 3210 3 view .LVU1997
+3211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6862              		.loc 1 3211 1 is_stmt 0 view .LVU1998
+ 6863 000a 0020     		movs	r0, #0
+ 6864              	.LVL504:
+3211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6865              		.loc 1 3211 1 view .LVU1999
+ 6866 000c 7047     		bx	lr
+ 6867              		.cfi_endproc
+ 6868              	.LFE376:
+ 6870              		.section	.text.HAL_TIMEx_DisableAsymmetricalDeadTime,"ax",%progbits
+ 6871              		.align	1
+ 6872              		.global	HAL_TIMEx_DisableAsymmetricalDeadTime
+ 6873              		.syntax unified
+ 6874              		.thumb
+ 6875              		.thumb_func
+ 6877              	HAL_TIMEx_DisableAsymmetricalDeadTime:
+ 6878              	.LVL505:
+ 6879              	.LFB377:
+3219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6880              		.loc 1 3219 1 is_stmt 1 view -0
+ 6881              		.cfi_startproc
+ 6882              		@ args = 0, pretend = 0, frame = 0
+ 6883              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6884              		@ link register save eliminated.
+3221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6885              		.loc 1 3221 3 view .LVU2001
+3223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 6886              		.loc 1 3223 3 view .LVU2002
+ 6887 0000 0268     		ldr	r2, [r0]
+ 6888 0002 536D     		ldr	r3, [r2, #84]
+ 6889 0004 23F48033 		bic	r3, r3, #65536
+ 6890 0008 5365     		str	r3, [r2, #84]
+3224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6891              		.loc 1 3224 3 view .LVU2003
+3225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6892              		.loc 1 3225 1 is_stmt 0 view .LVU2004
+ 6893 000a 0020     		movs	r0, #0
+ 6894              	.LVL506:
+3225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6895              		.loc 1 3225 1 view .LVU2005
+ 6896 000c 7047     		bx	lr
+ 6897              		.cfi_endproc
+ 6898              	.LFE377:
+ 6900              		.section	.text.HAL_TIMEx_ConfigEncoderIndex,"ax",%progbits
+ 6901              		.align	1
+ 6902              		.global	HAL_TIMEx_ConfigEncoderIndex
+ 6903              		.syntax unified
+ 6904              		.thumb
+ 6905              		.thumb_func
+ARM GAS  /tmp/cc9HXhVl.s 			page 220
+
+
+ 6907              	HAL_TIMEx_ConfigEncoderIndex:
+ 6908              	.LVL507:
+ 6909              	.LFB378:
+3238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6910              		.loc 1 3238 1 is_stmt 1 view -0
+ 6911              		.cfi_startproc
+ 6912              		@ args = 0, pretend = 0, frame = 0
+ 6913              		@ frame_needed = 0, uses_anonymous_args = 0
+3238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 6914              		.loc 1 3238 1 is_stmt 0 view .LVU2007
+ 6915 0000 38B5     		push	{r3, r4, r5, lr}
+ 6916              	.LCFI55:
+ 6917              		.cfi_def_cfa_offset 16
+ 6918              		.cfi_offset 3, -16
+ 6919              		.cfi_offset 4, -12
+ 6920              		.cfi_offset 5, -8
+ 6921              		.cfi_offset 14, -4
+3240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
+ 6922              		.loc 1 3240 3 is_stmt 1 view .LVU2008
+3241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
+ 6923              		.loc 1 3241 3 view .LVU2009
+3242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
+ 6924              		.loc 1 3242 3 view .LVU2010
+3243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
+ 6925              		.loc 1 3243 3 view .LVU2011
+3244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
+ 6926              		.loc 1 3244 3 view .LVU2012
+3245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
+ 6927              		.loc 1 3245 3 view .LVU2013
+3246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6928              		.loc 1 3246 3 view .LVU2014
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6929              		.loc 1 3249 3 view .LVU2015
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6930              		.loc 1 3249 3 view .LVU2016
+ 6931 0002 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 6932 0006 012B     		cmp	r3, #1
+ 6933 0008 20D0     		beq	.L554
+ 6934 000a 0546     		mov	r5, r0
+ 6935 000c 0C46     		mov	r4, r1
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6936              		.loc 1 3249 3 discriminator 2 view .LVU2017
+ 6937 000e 0123     		movs	r3, #1
+ 6938 0010 80F83C30 		strb	r3, [r0, #60]
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6939              		.loc 1 3249 3 discriminator 2 view .LVU2018
+3252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                     sEncoderIndexConfig->Prescaler,
+ 6940              		.loc 1 3252 3 discriminator 2 view .LVU2019
+ 6941 0014 8B68     		ldr	r3, [r1, #8]
+ 6942 0016 0A68     		ldr	r2, [r1]
+ 6943 0018 4968     		ldr	r1, [r1, #4]
+ 6944              	.LVL508:
+3252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                     sEncoderIndexConfig->Prescaler,
+ 6945              		.loc 1 3252 3 is_stmt 0 discriminator 2 view .LVU2020
+ 6946 001a 0068     		ldr	r0, [r0]
+ 6947              	.LVL509:
+3252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****                     sEncoderIndexConfig->Prescaler,
+ARM GAS  /tmp/cc9HXhVl.s 			page 221
+
+
+ 6948              		.loc 1 3252 3 discriminator 2 view .LVU2021
+ 6949 001c FFF7FEFF 		bl	TIM_ETR_SetConfig
+ 6950              	.LVL510:
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****              TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
+ 6951              		.loc 1 3258 3 is_stmt 1 discriminator 2 view .LVU2022
+ 6952 0020 2968     		ldr	r1, [r5]
+ 6953 0022 8B6D     		ldr	r3, [r1, #88]
+ 6954 0024 23F0E603 		bic	r3, r3, #230
+ 6955 0028 6269     		ldr	r2, [r4, #20]
+ 6956 002a 207B     		ldrb	r0, [r4, #12]	@ zero_extendqisi2
+ 6957 002c 0128     		cmp	r0, #1
+ 6958 002e 0BD0     		beq	.L557
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****              TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
+ 6959              		.loc 1 3258 3 is_stmt 0 view .LVU2023
+ 6960 0030 0020     		movs	r0, #0
+ 6961              	.L553:
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****              TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
+ 6962              		.loc 1 3258 3 discriminator 4 view .LVU2024
+ 6963 0032 0243     		orrs	r2, r2, r0
+ 6964 0034 2069     		ldr	r0, [r4, #16]
+ 6965 0036 0243     		orrs	r2, r2, r0
+ 6966 0038 1343     		orrs	r3, r3, r2
+ 6967 003a 43F00103 		orr	r3, r3, #1
+ 6968 003e 8B65     		str	r3, [r1, #88]
+3265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6969              		.loc 1 3265 3 is_stmt 1 discriminator 4 view .LVU2025
+3265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6970              		.loc 1 3265 3 discriminator 4 view .LVU2026
+ 6971 0040 0020     		movs	r0, #0
+ 6972 0042 85F83C00 		strb	r0, [r5, #60]
+3265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6973              		.loc 1 3265 3 discriminator 4 view .LVU2027
+3267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 6974              		.loc 1 3267 3 discriminator 4 view .LVU2028
+ 6975              	.LVL511:
+ 6976              	.L552:
+3268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6977              		.loc 1 3268 1 is_stmt 0 view .LVU2029
+ 6978 0046 38BD     		pop	{r3, r4, r5, pc}
+ 6979              	.LVL512:
+ 6980              	.L557:
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****              TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
+ 6981              		.loc 1 3258 3 view .LVU2030
+ 6982 0048 2020     		movs	r0, #32
+ 6983 004a F2E7     		b	.L553
+ 6984              	.LVL513:
+ 6985              	.L554:
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6986              		.loc 1 3249 3 view .LVU2031
+ 6987 004c 0220     		movs	r0, #2
+ 6988              	.LVL514:
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 6989              		.loc 1 3249 3 view .LVU2032
+ 6990 004e FAE7     		b	.L552
+ 6991              		.cfi_endproc
+ 6992              	.LFE378:
+ 6994              		.section	.text.HAL_TIMEx_EnableEncoderIndex,"ax",%progbits
+ARM GAS  /tmp/cc9HXhVl.s 			page 222
+
+
+ 6995              		.align	1
+ 6996              		.global	HAL_TIMEx_EnableEncoderIndex
+ 6997              		.syntax unified
+ 6998              		.thumb
+ 6999              		.thumb_func
+ 7001              	HAL_TIMEx_EnableEncoderIndex:
+ 7002              	.LVL515:
+ 7003              	.LFB379:
+3276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 7004              		.loc 1 3276 1 is_stmt 1 view -0
+ 7005              		.cfi_startproc
+ 7006              		@ args = 0, pretend = 0, frame = 0
+ 7007              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7008              		@ link register save eliminated.
+3278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7009              		.loc 1 3278 3 view .LVU2034
+3280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 7010              		.loc 1 3280 3 view .LVU2035
+ 7011 0000 0268     		ldr	r2, [r0]
+ 7012 0002 936D     		ldr	r3, [r2, #88]
+ 7013 0004 43F00103 		orr	r3, r3, #1
+ 7014 0008 9365     		str	r3, [r2, #88]
+3281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 7015              		.loc 1 3281 3 view .LVU2036
+3282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7016              		.loc 1 3282 1 is_stmt 0 view .LVU2037
+ 7017 000a 0020     		movs	r0, #0
+ 7018              	.LVL516:
+3282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7019              		.loc 1 3282 1 view .LVU2038
+ 7020 000c 7047     		bx	lr
+ 7021              		.cfi_endproc
+ 7022              	.LFE379:
+ 7024              		.section	.text.HAL_TIMEx_DisableEncoderIndex,"ax",%progbits
+ 7025              		.align	1
+ 7026              		.global	HAL_TIMEx_DisableEncoderIndex
+ 7027              		.syntax unified
+ 7028              		.thumb
+ 7029              		.thumb_func
+ 7031              	HAL_TIMEx_DisableEncoderIndex:
+ 7032              	.LVL517:
+ 7033              	.LFB380:
+3290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 7034              		.loc 1 3290 1 is_stmt 1 view -0
+ 7035              		.cfi_startproc
+ 7036              		@ args = 0, pretend = 0, frame = 0
+ 7037              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7038              		@ link register save eliminated.
+3292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7039              		.loc 1 3292 3 view .LVU2040
+3294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 7040              		.loc 1 3294 3 view .LVU2041
+ 7041 0000 0268     		ldr	r2, [r0]
+ 7042 0002 936D     		ldr	r3, [r2, #88]
+ 7043 0004 23F00103 		bic	r3, r3, #1
+ 7044 0008 9365     		str	r3, [r2, #88]
+3295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ARM GAS  /tmp/cc9HXhVl.s 			page 223
+
+
+ 7045              		.loc 1 3295 3 view .LVU2042
+3296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7046              		.loc 1 3296 1 is_stmt 0 view .LVU2043
+ 7047 000a 0020     		movs	r0, #0
+ 7048              	.LVL518:
+3296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7049              		.loc 1 3296 1 view .LVU2044
+ 7050 000c 7047     		bx	lr
+ 7051              		.cfi_endproc
+ 7052              	.LFE380:
+ 7054              		.section	.text.HAL_TIMEx_EnableEncoderFirstIndex,"ax",%progbits
+ 7055              		.align	1
+ 7056              		.global	HAL_TIMEx_EnableEncoderFirstIndex
+ 7057              		.syntax unified
+ 7058              		.thumb
+ 7059              		.thumb_func
+ 7061              	HAL_TIMEx_EnableEncoderFirstIndex:
+ 7062              	.LVL519:
+ 7063              	.LFB381:
+3304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 7064              		.loc 1 3304 1 is_stmt 1 view -0
+ 7065              		.cfi_startproc
+ 7066              		@ args = 0, pretend = 0, frame = 0
+ 7067              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7068              		@ link register save eliminated.
+3306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7069              		.loc 1 3306 3 view .LVU2046
+3308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 7070              		.loc 1 3308 3 view .LVU2047
+ 7071 0000 0268     		ldr	r2, [r0]
+ 7072 0002 936D     		ldr	r3, [r2, #88]
+ 7073 0004 43F02003 		orr	r3, r3, #32
+ 7074 0008 9365     		str	r3, [r2, #88]
+3309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 7075              		.loc 1 3309 3 view .LVU2048
+3310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7076              		.loc 1 3310 1 is_stmt 0 view .LVU2049
+ 7077 000a 0020     		movs	r0, #0
+ 7078              	.LVL520:
+3310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7079              		.loc 1 3310 1 view .LVU2050
+ 7080 000c 7047     		bx	lr
+ 7081              		.cfi_endproc
+ 7082              	.LFE381:
+ 7084              		.section	.text.HAL_TIMEx_DisableEncoderFirstIndex,"ax",%progbits
+ 7085              		.align	1
+ 7086              		.global	HAL_TIMEx_DisableEncoderFirstIndex
+ 7087              		.syntax unified
+ 7088              		.thumb
+ 7089              		.thumb_func
+ 7091              	HAL_TIMEx_DisableEncoderFirstIndex:
+ 7092              	.LVL521:
+ 7093              	.LFB382:
+3318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Check the parameters */
+ 7094              		.loc 1 3318 1 is_stmt 1 view -0
+ 7095              		.cfi_startproc
+ 7096              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/cc9HXhVl.s 			page 224
+
+
+ 7097              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7098              		@ link register save eliminated.
+3320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7099              		.loc 1 3320 3 view .LVU2052
+3322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return HAL_OK;
+ 7100              		.loc 1 3322 3 view .LVU2053
+ 7101 0000 0268     		ldr	r2, [r0]
+ 7102 0002 936D     		ldr	r3, [r2, #88]
+ 7103 0004 23F02003 		bic	r3, r3, #32
+ 7104 0008 9365     		str	r3, [r2, #88]
+3323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 7105              		.loc 1 3323 3 view .LVU2054
+3324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7106              		.loc 1 3324 1 is_stmt 0 view .LVU2055
+ 7107 000a 0020     		movs	r0, #0
+ 7108              	.LVL522:
+3324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7109              		.loc 1 3324 1 view .LVU2056
+ 7110 000c 7047     		bx	lr
+ 7111              		.cfi_endproc
+ 7112              	.LFE382:
+ 7114              		.section	.text.HAL_TIMEx_CommutCallback,"ax",%progbits
+ 7115              		.align	1
+ 7116              		.weak	HAL_TIMEx_CommutCallback
+ 7117              		.syntax unified
+ 7118              		.thumb
+ 7119              		.thumb_func
+ 7121              	HAL_TIMEx_CommutCallback:
+ 7122              	.LVL523:
+ 7123              	.LFB383:
+3352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 7124              		.loc 1 3352 1 is_stmt 1 view -0
+ 7125              		.cfi_startproc
+ 7126              		@ args = 0, pretend = 0, frame = 0
+ 7127              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7128              		@ link register save eliminated.
+3354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7129              		.loc 1 3354 3 view .LVU2058
+3359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 7130              		.loc 1 3359 1 is_stmt 0 view .LVU2059
+ 7131 0000 7047     		bx	lr
+ 7132              		.cfi_endproc
+ 7133              	.LFE383:
+ 7135              		.section	.text.TIMEx_DMACommutationCplt,"ax",%progbits
+ 7136              		.align	1
+ 7137              		.global	TIMEx_DMACommutationCplt
+ 7138              		.syntax unified
+ 7139              		.thumb
+ 7140              		.thumb_func
+ 7142              	TIMEx_DMACommutationCplt:
+ 7143              	.LVL524:
+ 7144              	.LFB393:
+3535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 7145              		.loc 1 3535 1 is_stmt 1 view -0
+ 7146              		.cfi_startproc
+ 7147              		@ args = 0, pretend = 0, frame = 0
+ 7148              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cc9HXhVl.s 			page 225
+
+
+3535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 7149              		.loc 1 3535 1 is_stmt 0 view .LVU2061
+ 7150 0000 08B5     		push	{r3, lr}
+ 7151              	.LCFI56:
+ 7152              		.cfi_def_cfa_offset 8
+ 7153              		.cfi_offset 3, -8
+ 7154              		.cfi_offset 14, -4
+3536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7155              		.loc 1 3536 3 is_stmt 1 view .LVU2062
+3536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7156              		.loc 1 3536 22 is_stmt 0 view .LVU2063
+ 7157 0002 806A     		ldr	r0, [r0, #40]
+ 7158              	.LVL525:
+3539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7159              		.loc 1 3539 3 is_stmt 1 view .LVU2064
+3539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7160              		.loc 1 3539 15 is_stmt 0 view .LVU2065
+ 7161 0004 0123     		movs	r3, #1
+ 7162 0006 80F83D30 		strb	r3, [r0, #61]
+3544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 7163              		.loc 1 3544 3 is_stmt 1 view .LVU2066
+ 7164 000a FFF7FEFF 		bl	HAL_TIMEx_CommutCallback
+ 7165              	.LVL526:
+3546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7166              		.loc 1 3546 1 is_stmt 0 view .LVU2067
+ 7167 000e 08BD     		pop	{r3, pc}
+ 7168              		.cfi_endproc
+ 7169              	.LFE393:
+ 7171              		.section	.text.HAL_TIMEx_CommutHalfCpltCallback,"ax",%progbits
+ 7172              		.align	1
+ 7173              		.weak	HAL_TIMEx_CommutHalfCpltCallback
+ 7174              		.syntax unified
+ 7175              		.thumb
+ 7176              		.thumb_func
+ 7178              	HAL_TIMEx_CommutHalfCpltCallback:
+ 7179              	.LVL527:
+ 7180              	.LFB384:
+3366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 7181              		.loc 1 3366 1 is_stmt 1 view -0
+ 7182              		.cfi_startproc
+ 7183              		@ args = 0, pretend = 0, frame = 0
+ 7184              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7185              		@ link register save eliminated.
+3368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7186              		.loc 1 3368 3 view .LVU2069
+3373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7187              		.loc 1 3373 1 is_stmt 0 view .LVU2070
+ 7188 0000 7047     		bx	lr
+ 7189              		.cfi_endproc
+ 7190              	.LFE384:
+ 7192              		.section	.text.TIMEx_DMACommutationHalfCplt,"ax",%progbits
+ 7193              		.align	1
+ 7194              		.global	TIMEx_DMACommutationHalfCplt
+ 7195              		.syntax unified
+ 7196              		.thumb
+ 7197              		.thumb_func
+ 7199              	TIMEx_DMACommutationHalfCplt:
+ARM GAS  /tmp/cc9HXhVl.s 			page 226
+
+
+ 7200              	.LVL528:
+ 7201              	.LFB394:
+3554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 7202              		.loc 1 3554 1 is_stmt 1 view -0
+ 7203              		.cfi_startproc
+ 7204              		@ args = 0, pretend = 0, frame = 0
+ 7205              		@ frame_needed = 0, uses_anonymous_args = 0
+3554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 7206              		.loc 1 3554 1 is_stmt 0 view .LVU2072
+ 7207 0000 08B5     		push	{r3, lr}
+ 7208              	.LCFI57:
+ 7209              		.cfi_def_cfa_offset 8
+ 7210              		.cfi_offset 3, -8
+ 7211              		.cfi_offset 14, -4
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7212              		.loc 1 3555 3 is_stmt 1 view .LVU2073
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7213              		.loc 1 3555 22 is_stmt 0 view .LVU2074
+ 7214 0002 806A     		ldr	r0, [r0, #40]
+ 7215              	.LVL529:
+3558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7216              		.loc 1 3558 3 is_stmt 1 view .LVU2075
+3558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7217              		.loc 1 3558 15 is_stmt 0 view .LVU2076
+ 7218 0004 0123     		movs	r3, #1
+ 7219 0006 80F83D30 		strb	r3, [r0, #61]
+3563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 7220              		.loc 1 3563 3 is_stmt 1 view .LVU2077
+ 7221 000a FFF7FEFF 		bl	HAL_TIMEx_CommutHalfCpltCallback
+ 7222              	.LVL530:
+3565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7223              		.loc 1 3565 1 is_stmt 0 view .LVU2078
+ 7224 000e 08BD     		pop	{r3, pc}
+ 7225              		.cfi_endproc
+ 7226              	.LFE394:
+ 7228              		.section	.text.HAL_TIMEx_BreakCallback,"ax",%progbits
+ 7229              		.align	1
+ 7230              		.weak	HAL_TIMEx_BreakCallback
+ 7231              		.syntax unified
+ 7232              		.thumb
+ 7233              		.thumb_func
+ 7235              	HAL_TIMEx_BreakCallback:
+ 7236              	.LVL531:
+ 7237              	.LFB385:
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 7238              		.loc 1 3381 1 is_stmt 1 view -0
+ 7239              		.cfi_startproc
+ 7240              		@ args = 0, pretend = 0, frame = 0
+ 7241              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7242              		@ link register save eliminated.
+3383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7243              		.loc 1 3383 3 view .LVU2080
+3388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7244              		.loc 1 3388 1 is_stmt 0 view .LVU2081
+ 7245 0000 7047     		bx	lr
+ 7246              		.cfi_endproc
+ 7247              	.LFE385:
+ARM GAS  /tmp/cc9HXhVl.s 			page 227
+
+
+ 7249              		.section	.text.HAL_TIMEx_Break2Callback,"ax",%progbits
+ 7250              		.align	1
+ 7251              		.weak	HAL_TIMEx_Break2Callback
+ 7252              		.syntax unified
+ 7253              		.thumb
+ 7254              		.thumb_func
+ 7256              	HAL_TIMEx_Break2Callback:
+ 7257              	.LVL532:
+ 7258              	.LFB386:
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 7259              		.loc 1 3396 1 is_stmt 1 view -0
+ 7260              		.cfi_startproc
+ 7261              		@ args = 0, pretend = 0, frame = 0
+ 7262              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7263              		@ link register save eliminated.
+3398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7264              		.loc 1 3398 3 view .LVU2083
+3403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7265              		.loc 1 3403 1 is_stmt 0 view .LVU2084
+ 7266 0000 7047     		bx	lr
+ 7267              		.cfi_endproc
+ 7268              	.LFE386:
+ 7270              		.section	.text.HAL_TIMEx_EncoderIndexCallback,"ax",%progbits
+ 7271              		.align	1
+ 7272              		.weak	HAL_TIMEx_EncoderIndexCallback
+ 7273              		.syntax unified
+ 7274              		.thumb
+ 7275              		.thumb_func
+ 7277              	HAL_TIMEx_EncoderIndexCallback:
+ 7278              	.LVL533:
+ 7279              	.LFB387:
+3411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 7280              		.loc 1 3411 1 is_stmt 1 view -0
+ 7281              		.cfi_startproc
+ 7282              		@ args = 0, pretend = 0, frame = 0
+ 7283              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7284              		@ link register save eliminated.
+3413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7285              		.loc 1 3413 3 view .LVU2086
+3418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7286              		.loc 1 3418 1 is_stmt 0 view .LVU2087
+ 7287 0000 7047     		bx	lr
+ 7288              		.cfi_endproc
+ 7289              	.LFE387:
+ 7291              		.section	.text.HAL_TIMEx_DirectionChangeCallback,"ax",%progbits
+ 7292              		.align	1
+ 7293              		.weak	HAL_TIMEx_DirectionChangeCallback
+ 7294              		.syntax unified
+ 7295              		.thumb
+ 7296              		.thumb_func
+ 7298              	HAL_TIMEx_DirectionChangeCallback:
+ 7299              	.LVL534:
+ 7300              	.LFB388:
+3426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 7301              		.loc 1 3426 1 is_stmt 1 view -0
+ 7302              		.cfi_startproc
+ 7303              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/cc9HXhVl.s 			page 228
+
+
+ 7304              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7305              		@ link register save eliminated.
+3428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7306              		.loc 1 3428 3 view .LVU2089
+3433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7307              		.loc 1 3433 1 is_stmt 0 view .LVU2090
+ 7308 0000 7047     		bx	lr
+ 7309              		.cfi_endproc
+ 7310              	.LFE388:
+ 7312              		.section	.text.HAL_TIMEx_IndexErrorCallback,"ax",%progbits
+ 7313              		.align	1
+ 7314              		.weak	HAL_TIMEx_IndexErrorCallback
+ 7315              		.syntax unified
+ 7316              		.thumb
+ 7317              		.thumb_func
+ 7319              	HAL_TIMEx_IndexErrorCallback:
+ 7320              	.LVL535:
+ 7321              	.LFB389:
+3441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 7322              		.loc 1 3441 1 is_stmt 1 view -0
+ 7323              		.cfi_startproc
+ 7324              		@ args = 0, pretend = 0, frame = 0
+ 7325              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7326              		@ link register save eliminated.
+3443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7327              		.loc 1 3443 3 view .LVU2092
+3448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7328              		.loc 1 3448 1 is_stmt 0 view .LVU2093
+ 7329 0000 7047     		bx	lr
+ 7330              		.cfi_endproc
+ 7331              	.LFE389:
+ 7333              		.section	.text.HAL_TIMEx_TransitionErrorCallback,"ax",%progbits
+ 7334              		.align	1
+ 7335              		.weak	HAL_TIMEx_TransitionErrorCallback
+ 7336              		.syntax unified
+ 7337              		.thumb
+ 7338              		.thumb_func
+ 7340              	HAL_TIMEx_TransitionErrorCallback:
+ 7341              	.LVL536:
+ 7342              	.LFB390:
+3456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 7343              		.loc 1 3456 1 is_stmt 1 view -0
+ 7344              		.cfi_startproc
+ 7345              		@ args = 0, pretend = 0, frame = 0
+ 7346              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7347              		@ link register save eliminated.
+3458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7348              		.loc 1 3458 3 view .LVU2095
+3463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7349              		.loc 1 3463 1 is_stmt 0 view .LVU2096
+ 7350 0000 7047     		bx	lr
+ 7351              		.cfi_endproc
+ 7352              	.LFE390:
+ 7354              		.section	.text.HAL_TIMEx_HallSensor_GetState,"ax",%progbits
+ 7355              		.align	1
+ 7356              		.global	HAL_TIMEx_HallSensor_GetState
+ 7357              		.syntax unified
+ARM GAS  /tmp/cc9HXhVl.s 			page 229
+
+
+ 7358              		.thumb
+ 7359              		.thumb_func
+ 7361              	HAL_TIMEx_HallSensor_GetState:
+ 7362              	.LVL537:
+ 7363              	.LFB391:
+3490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   return htim->State;
+ 7364              		.loc 1 3490 1 is_stmt 1 view -0
+ 7365              		.cfi_startproc
+ 7366              		@ args = 0, pretend = 0, frame = 0
+ 7367              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7368              		@ link register save eliminated.
+3491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 7369              		.loc 1 3491 3 view .LVU2098
+3491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 7370              		.loc 1 3491 14 is_stmt 0 view .LVU2099
+ 7371 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 7372              	.LVL538:
+3492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7373              		.loc 1 3492 1 view .LVU2100
+ 7374 0004 7047     		bx	lr
+ 7375              		.cfi_endproc
+ 7376              	.LFE391:
+ 7378              		.section	.text.HAL_TIMEx_GetChannelNState,"ax",%progbits
+ 7379              		.align	1
+ 7380              		.global	HAL_TIMEx_GetChannelNState
+ 7381              		.syntax unified
+ 7382              		.thumb
+ 7383              		.thumb_func
+ 7385              	HAL_TIMEx_GetChannelNState:
+ 7386              	.LVL539:
+ 7387              	.LFB392:
+3506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_state;
+ 7388              		.loc 1 3506 1 is_stmt 1 view -0
+ 7389              		.cfi_startproc
+ 7390              		@ args = 0, pretend = 0, frame = 0
+ 7391              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7392              		@ link register save eliminated.
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7393              		.loc 1 3507 3 view .LVU2102
+3510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7394              		.loc 1 3510 3 view .LVU2103
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7395              		.loc 1 3512 3 view .LVU2104
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7396              		.loc 1 3512 19 is_stmt 0 view .LVU2105
+ 7397 0000 19B9     		cbnz	r1, .L576
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7398              		.loc 1 3512 19 discriminator 1 view .LVU2106
+ 7399 0002 90F84400 		ldrb	r0, [r0, #68]	@ zero_extendqisi2
+ 7400              	.LVL540:
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7401              		.loc 1 3512 19 discriminator 1 view .LVU2107
+ 7402 0006 C0B2     		uxtb	r0, r0
+ 7403 0008 7047     		bx	lr
+ 7404              	.LVL541:
+ 7405              	.L576:
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc9HXhVl.s 			page 230
+
+
+ 7406              		.loc 1 3512 19 discriminator 2 view .LVU2108
+ 7407 000a 0429     		cmp	r1, #4
+ 7408 000c 05D0     		beq	.L580
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7409              		.loc 1 3512 19 discriminator 5 view .LVU2109
+ 7410 000e 0829     		cmp	r1, #8
+ 7411 0010 07D0     		beq	.L581
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7412              		.loc 1 3512 19 discriminator 8 view .LVU2110
+ 7413 0012 90F84700 		ldrb	r0, [r0, #71]	@ zero_extendqisi2
+ 7414              	.LVL542:
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7415              		.loc 1 3512 19 discriminator 8 view .LVU2111
+ 7416 0016 C0B2     		uxtb	r0, r0
+ 7417              	.LVL543:
+3514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** }
+ 7418              		.loc 1 3514 3 is_stmt 1 discriminator 8 view .LVU2112
+3515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** /**
+ 7419              		.loc 1 3515 1 is_stmt 0 discriminator 8 view .LVU2113
+ 7420 0018 7047     		bx	lr
+ 7421              	.LVL544:
+ 7422              	.L580:
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7423              		.loc 1 3512 19 discriminator 4 view .LVU2114
+ 7424 001a 90F84500 		ldrb	r0, [r0, #69]	@ zero_extendqisi2
+ 7425              	.LVL545:
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7426              		.loc 1 3512 19 discriminator 4 view .LVU2115
+ 7427 001e C0B2     		uxtb	r0, r0
+ 7428 0020 7047     		bx	lr
+ 7429              	.LVL546:
+ 7430              	.L581:
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7431              		.loc 1 3512 19 discriminator 7 view .LVU2116
+ 7432 0022 90F84600 		ldrb	r0, [r0, #70]	@ zero_extendqisi2
+ 7433              	.LVL547:
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c **** 
+ 7434              		.loc 1 3512 19 discriminator 7 view .LVU2117
+ 7435 0026 C0B2     		uxtb	r0, r0
+ 7436 0028 7047     		bx	lr
+ 7437              		.cfi_endproc
+ 7438              	.LFE392:
+ 7440              		.text
+ 7441              	.Letext0:
+ 7442              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 7443              		.file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 7444              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 7445              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 7446              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 7447              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"
+ 7448              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"
+ 7449              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ARM GAS  /tmp/cc9HXhVl.s 			page 231
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_tim_ex.c
+     /tmp/cc9HXhVl.s:21     .text.TIM_CCxNChannelCmd:00000000 $t
+     /tmp/cc9HXhVl.s:26     .text.TIM_CCxNChannelCmd:00000000 TIM_CCxNChannelCmd
+     /tmp/cc9HXhVl.s:64     .text.TIM_DMAErrorCCxN:00000000 $t
+     /tmp/cc9HXhVl.s:69     .text.TIM_DMAErrorCCxN:00000000 TIM_DMAErrorCCxN
+     /tmp/cc9HXhVl.s:149    .text.TIM_DMADelayPulseNCplt:00000000 $t
+     /tmp/cc9HXhVl.s:154    .text.TIM_DMADelayPulseNCplt:00000000 TIM_DMADelayPulseNCplt
+     /tmp/cc9HXhVl.s:274    .text.HAL_TIMEx_HallSensor_MspInit:00000000 $t
+     /tmp/cc9HXhVl.s:280    .text.HAL_TIMEx_HallSensor_MspInit:00000000 HAL_TIMEx_HallSensor_MspInit
+     /tmp/cc9HXhVl.s:295    .text.HAL_TIMEx_HallSensor_Init:00000000 $t
+     /tmp/cc9HXhVl.s:301    .text.HAL_TIMEx_HallSensor_Init:00000000 HAL_TIMEx_HallSensor_Init
+     /tmp/cc9HXhVl.s:518    .text.HAL_TIMEx_HallSensor_MspDeInit:00000000 $t
+     /tmp/cc9HXhVl.s:524    .text.HAL_TIMEx_HallSensor_MspDeInit:00000000 HAL_TIMEx_HallSensor_MspDeInit
+     /tmp/cc9HXhVl.s:539    .text.HAL_TIMEx_HallSensor_DeInit:00000000 $t
+     /tmp/cc9HXhVl.s:545    .text.HAL_TIMEx_HallSensor_DeInit:00000000 HAL_TIMEx_HallSensor_DeInit
+     /tmp/cc9HXhVl.s:615    .text.HAL_TIMEx_HallSensor_Start:00000000 $t
+     /tmp/cc9HXhVl.s:621    .text.HAL_TIMEx_HallSensor_Start:00000000 HAL_TIMEx_HallSensor_Start
+     /tmp/cc9HXhVl.s:784    .text.HAL_TIMEx_HallSensor_Start:000000b0 $d
+     /tmp/cc9HXhVl.s:790    .text.HAL_TIMEx_HallSensor_Stop:00000000 $t
+     /tmp/cc9HXhVl.s:796    .text.HAL_TIMEx_HallSensor_Stop:00000000 HAL_TIMEx_HallSensor_Stop
+     /tmp/cc9HXhVl.s:855    .text.HAL_TIMEx_HallSensor_Start_IT:00000000 $t
+     /tmp/cc9HXhVl.s:861    .text.HAL_TIMEx_HallSensor_Start_IT:00000000 HAL_TIMEx_HallSensor_Start_IT
+     /tmp/cc9HXhVl.s:1032   .text.HAL_TIMEx_HallSensor_Start_IT:000000bc $d
+     /tmp/cc9HXhVl.s:1038   .text.HAL_TIMEx_HallSensor_Stop_IT:00000000 $t
+     /tmp/cc9HXhVl.s:1044   .text.HAL_TIMEx_HallSensor_Stop_IT:00000000 HAL_TIMEx_HallSensor_Stop_IT
+     /tmp/cc9HXhVl.s:1108   .text.HAL_TIMEx_HallSensor_Start_DMA:00000000 $t
+     /tmp/cc9HXhVl.s:1114   .text.HAL_TIMEx_HallSensor_Start_DMA:00000000 HAL_TIMEx_HallSensor_Start_DMA
+     /tmp/cc9HXhVl.s:1305   .text.HAL_TIMEx_HallSensor_Start_DMA:000000d4 $d
+     /tmp/cc9HXhVl.s:1314   .text.HAL_TIMEx_HallSensor_Stop_DMA:00000000 $t
+     /tmp/cc9HXhVl.s:1320   .text.HAL_TIMEx_HallSensor_Stop_DMA:00000000 HAL_TIMEx_HallSensor_Stop_DMA
+     /tmp/cc9HXhVl.s:1385   .text.HAL_TIMEx_OCN_Start:00000000 $t
+     /tmp/cc9HXhVl.s:1391   .text.HAL_TIMEx_OCN_Start:00000000 HAL_TIMEx_OCN_Start
+     /tmp/cc9HXhVl.s:1579   .text.HAL_TIMEx_OCN_Start:000000ec $d
+     /tmp/cc9HXhVl.s:1585   .text.HAL_TIMEx_OCN_Stop:00000000 $t
+     /tmp/cc9HXhVl.s:1591   .text.HAL_TIMEx_OCN_Stop:00000000 HAL_TIMEx_OCN_Stop
+     /tmp/cc9HXhVl.s:1688   .text.HAL_TIMEx_OCN_Start_IT:00000000 $t
+     /tmp/cc9HXhVl.s:1694   .text.HAL_TIMEx_OCN_Start_IT:00000000 HAL_TIMEx_OCN_Start_IT
+     /tmp/cc9HXhVl.s:1848   .text.HAL_TIMEx_OCN_Start_IT:000000d4 $d
+     /tmp/cc9HXhVl.s:1861   .text.HAL_TIMEx_OCN_Start_IT:00000108 $t
+     /tmp/cc9HXhVl.s:1949   .text.HAL_TIMEx_OCN_Start_IT:00000164 $d
+     /tmp/cc9HXhVl.s:1955   .text.HAL_TIMEx_OCN_Stop_IT:00000000 $t
+     /tmp/cc9HXhVl.s:1961   .text.HAL_TIMEx_OCN_Stop_IT:00000000 HAL_TIMEx_OCN_Stop_IT
+     /tmp/cc9HXhVl.s:1987   .text.HAL_TIMEx_OCN_Stop_IT:0000000e $d
+     /tmp/cc9HXhVl.s:2148   .text.HAL_TIMEx_OCN_Start_DMA:00000000 $t
+     /tmp/cc9HXhVl.s:2154   .text.HAL_TIMEx_OCN_Start_DMA:00000000 HAL_TIMEx_OCN_Start_DMA
+     /tmp/cc9HXhVl.s:2420   .text.HAL_TIMEx_OCN_Start_DMA:00000164 $d
+     /tmp/cc9HXhVl.s:2433   .text.HAL_TIMEx_OCN_Start_DMA:00000198 $t
+     /tmp/cc9HXhVl.s:2637   .text.HAL_TIMEx_OCN_Start_DMA:0000026c $d
+     /tmp/cc9HXhVl.s:2646   .text.HAL_TIMEx_OCN_Stop_DMA:00000000 $t
+     /tmp/cc9HXhVl.s:2652   .text.HAL_TIMEx_OCN_Stop_DMA:00000000 HAL_TIMEx_OCN_Stop_DMA
+     /tmp/cc9HXhVl.s:2677   .text.HAL_TIMEx_OCN_Stop_DMA:0000000e $d
+     /tmp/cc9HXhVl.s:2845   .text.HAL_TIMEx_PWMN_Start:00000000 $t
+     /tmp/cc9HXhVl.s:2851   .text.HAL_TIMEx_PWMN_Start:00000000 HAL_TIMEx_PWMN_Start
+     /tmp/cc9HXhVl.s:3039   .text.HAL_TIMEx_PWMN_Start:000000ec $d
+     /tmp/cc9HXhVl.s:3045   .text.HAL_TIMEx_PWMN_Stop:00000000 $t
+     /tmp/cc9HXhVl.s:3051   .text.HAL_TIMEx_PWMN_Stop:00000000 HAL_TIMEx_PWMN_Stop
+ARM GAS  /tmp/cc9HXhVl.s 			page 232
+
+
+     /tmp/cc9HXhVl.s:3148   .text.HAL_TIMEx_PWMN_Start_IT:00000000 $t
+     /tmp/cc9HXhVl.s:3154   .text.HAL_TIMEx_PWMN_Start_IT:00000000 HAL_TIMEx_PWMN_Start_IT
+     /tmp/cc9HXhVl.s:3308   .text.HAL_TIMEx_PWMN_Start_IT:000000d4 $d
+     /tmp/cc9HXhVl.s:3321   .text.HAL_TIMEx_PWMN_Start_IT:00000108 $t
+     /tmp/cc9HXhVl.s:3409   .text.HAL_TIMEx_PWMN_Start_IT:00000164 $d
+     /tmp/cc9HXhVl.s:3415   .text.HAL_TIMEx_PWMN_Stop_IT:00000000 $t
+     /tmp/cc9HXhVl.s:3421   .text.HAL_TIMEx_PWMN_Stop_IT:00000000 HAL_TIMEx_PWMN_Stop_IT
+     /tmp/cc9HXhVl.s:3447   .text.HAL_TIMEx_PWMN_Stop_IT:0000000e $d
+     /tmp/cc9HXhVl.s:3608   .text.HAL_TIMEx_PWMN_Start_DMA:00000000 $t
+     /tmp/cc9HXhVl.s:3614   .text.HAL_TIMEx_PWMN_Start_DMA:00000000 HAL_TIMEx_PWMN_Start_DMA
+     /tmp/cc9HXhVl.s:3880   .text.HAL_TIMEx_PWMN_Start_DMA:00000164 $d
+     /tmp/cc9HXhVl.s:3893   .text.HAL_TIMEx_PWMN_Start_DMA:00000198 $t
+     /tmp/cc9HXhVl.s:4097   .text.HAL_TIMEx_PWMN_Start_DMA:0000026c $d
+     /tmp/cc9HXhVl.s:4106   .text.HAL_TIMEx_PWMN_Stop_DMA:00000000 $t
+     /tmp/cc9HXhVl.s:4112   .text.HAL_TIMEx_PWMN_Stop_DMA:00000000 HAL_TIMEx_PWMN_Stop_DMA
+     /tmp/cc9HXhVl.s:4137   .text.HAL_TIMEx_PWMN_Stop_DMA:0000000e $d
+     /tmp/cc9HXhVl.s:4305   .text.HAL_TIMEx_OnePulseN_Start:00000000 $t
+     /tmp/cc9HXhVl.s:4311   .text.HAL_TIMEx_OnePulseN_Start:00000000 HAL_TIMEx_OnePulseN_Start
+     /tmp/cc9HXhVl.s:4439   .text.HAL_TIMEx_OnePulseN_Stop:00000000 $t
+     /tmp/cc9HXhVl.s:4445   .text.HAL_TIMEx_OnePulseN_Stop:00000000 HAL_TIMEx_OnePulseN_Stop
+     /tmp/cc9HXhVl.s:4540   .text.HAL_TIMEx_OnePulseN_Start_IT:00000000 $t
+     /tmp/cc9HXhVl.s:4546   .text.HAL_TIMEx_OnePulseN_Start_IT:00000000 HAL_TIMEx_OnePulseN_Start_IT
+     /tmp/cc9HXhVl.s:4684   .text.HAL_TIMEx_OnePulseN_Stop_IT:00000000 $t
+     /tmp/cc9HXhVl.s:4690   .text.HAL_TIMEx_OnePulseN_Stop_IT:00000000 HAL_TIMEx_OnePulseN_Stop_IT
+     /tmp/cc9HXhVl.s:4795   .text.HAL_TIMEx_ConfigCommutEvent:00000000 $t
+     /tmp/cc9HXhVl.s:4801   .text.HAL_TIMEx_ConfigCommutEvent:00000000 HAL_TIMEx_ConfigCommutEvent
+     /tmp/cc9HXhVl.s:4944   .text.HAL_TIMEx_ConfigCommutEvent:0000009c $d
+     /tmp/cc9HXhVl.s:4950   .text.HAL_TIMEx_ConfigCommutEvent_IT:00000000 $t
+     /tmp/cc9HXhVl.s:4956   .text.HAL_TIMEx_ConfigCommutEvent_IT:00000000 HAL_TIMEx_ConfigCommutEvent_IT
+     /tmp/cc9HXhVl.s:5099   .text.HAL_TIMEx_ConfigCommutEvent_IT:0000009c $d
+     /tmp/cc9HXhVl.s:5105   .text.HAL_TIMEx_ConfigCommutEvent_DMA:00000000 $t
+     /tmp/cc9HXhVl.s:5111   .text.HAL_TIMEx_ConfigCommutEvent_DMA:00000000 HAL_TIMEx_ConfigCommutEvent_DMA
+     /tmp/cc9HXhVl.s:5272   .text.HAL_TIMEx_ConfigCommutEvent_DMA:000000b0 $d
+     /tmp/cc9HXhVl.s:7142   .text.TIMEx_DMACommutationCplt:00000000 TIMEx_DMACommutationCplt
+     /tmp/cc9HXhVl.s:7199   .text.TIMEx_DMACommutationHalfCplt:00000000 TIMEx_DMACommutationHalfCplt
+     /tmp/cc9HXhVl.s:5281   .text.HAL_TIMEx_MasterConfigSynchronization:00000000 $t
+     /tmp/cc9HXhVl.s:5287   .text.HAL_TIMEx_MasterConfigSynchronization:00000000 HAL_TIMEx_MasterConfigSynchronization
+     /tmp/cc9HXhVl.s:5441   .text.HAL_TIMEx_MasterConfigSynchronization:00000090 $d
+     /tmp/cc9HXhVl.s:5446   .text.HAL_TIMEx_ConfigBreakDeadTime:00000000 $t
+     /tmp/cc9HXhVl.s:5452   .text.HAL_TIMEx_ConfigBreakDeadTime:00000000 HAL_TIMEx_ConfigBreakDeadTime
+     /tmp/cc9HXhVl.s:5663   .text.HAL_TIMEx_ConfigBreakDeadTime:000000b8 $d
+     /tmp/cc9HXhVl.s:5668   .text.HAL_TIMEx_ConfigBreakInput:00000000 $t
+     /tmp/cc9HXhVl.s:5674   .text.HAL_TIMEx_ConfigBreakInput:00000000 HAL_TIMEx_ConfigBreakInput
+     /tmp/cc9HXhVl.s:5723   .text.HAL_TIMEx_ConfigBreakInput:0000001e $d
+     /tmp/cc9HXhVl.s:5739   .text.HAL_TIMEx_ConfigBreakInput:0000002e $t
+     /tmp/cc9HXhVl.s:5931   .text.HAL_TIMEx_RemapConfig:00000000 $t
+     /tmp/cc9HXhVl.s:5937   .text.HAL_TIMEx_RemapConfig:00000000 HAL_TIMEx_RemapConfig
+     /tmp/cc9HXhVl.s:5986   .text.HAL_TIMEx_TISelection:00000000 $t
+     /tmp/cc9HXhVl.s:5992   .text.HAL_TIMEx_TISelection:00000000 HAL_TIMEx_TISelection
+     /tmp/cc9HXhVl.s:6022   .text.HAL_TIMEx_TISelection:00000018 $d
+     /tmp/cc9HXhVl.s:6142   .text.HAL_TIMEx_TISelection:00000098 $d
+     /tmp/cc9HXhVl.s:6147   .text.HAL_TIMEx_GroupChannel5:00000000 $t
+     /tmp/cc9HXhVl.s:6153   .text.HAL_TIMEx_GroupChannel5:00000000 HAL_TIMEx_GroupChannel5
+     /tmp/cc9HXhVl.s:6226   .text.HAL_TIMEx_DisarmBreakInput:00000000 $t
+     /tmp/cc9HXhVl.s:6232   .text.HAL_TIMEx_DisarmBreakInput:00000000 HAL_TIMEx_DisarmBreakInput
+     /tmp/cc9HXhVl.s:6319   .text.HAL_TIMEx_DisarmBreakInput:00000048 $d
+     /tmp/cc9HXhVl.s:6325   .text.HAL_TIMEx_ReArmBreakInput:00000000 $t
+ARM GAS  /tmp/cc9HXhVl.s 			page 233
+
+
+     /tmp/cc9HXhVl.s:6331   .text.HAL_TIMEx_ReArmBreakInput:00000000 HAL_TIMEx_ReArmBreakInput
+     /tmp/cc9HXhVl.s:6476   .text.HAL_TIMEx_DitheringEnable:00000000 $t
+     /tmp/cc9HXhVl.s:6482   .text.HAL_TIMEx_DitheringEnable:00000000 HAL_TIMEx_DitheringEnable
+     /tmp/cc9HXhVl.s:6506   .text.HAL_TIMEx_DitheringDisable:00000000 $t
+     /tmp/cc9HXhVl.s:6512   .text.HAL_TIMEx_DitheringDisable:00000000 HAL_TIMEx_DitheringDisable
+     /tmp/cc9HXhVl.s:6536   .text.HAL_TIMEx_OC_ConfigPulseOnCompare:00000000 $t
+     /tmp/cc9HXhVl.s:6542   .text.HAL_TIMEx_OC_ConfigPulseOnCompare:00000000 HAL_TIMEx_OC_ConfigPulseOnCompare
+     /tmp/cc9HXhVl.s:6625   .text.HAL_TIMEx_ConfigSlaveModePreload:00000000 $t
+     /tmp/cc9HXhVl.s:6631   .text.HAL_TIMEx_ConfigSlaveModePreload:00000000 HAL_TIMEx_ConfigSlaveModePreload
+     /tmp/cc9HXhVl.s:6657   .text.HAL_TIMEx_EnableSlaveModePreload:00000000 $t
+     /tmp/cc9HXhVl.s:6663   .text.HAL_TIMEx_EnableSlaveModePreload:00000000 HAL_TIMEx_EnableSlaveModePreload
+     /tmp/cc9HXhVl.s:6687   .text.HAL_TIMEx_DisableSlaveModePreload:00000000 $t
+     /tmp/cc9HXhVl.s:6693   .text.HAL_TIMEx_DisableSlaveModePreload:00000000 HAL_TIMEx_DisableSlaveModePreload
+     /tmp/cc9HXhVl.s:6717   .text.HAL_TIMEx_EnableDeadTimePreload:00000000 $t
+     /tmp/cc9HXhVl.s:6723   .text.HAL_TIMEx_EnableDeadTimePreload:00000000 HAL_TIMEx_EnableDeadTimePreload
+     /tmp/cc9HXhVl.s:6747   .text.HAL_TIMEx_DisableDeadTimePreload:00000000 $t
+     /tmp/cc9HXhVl.s:6753   .text.HAL_TIMEx_DisableDeadTimePreload:00000000 HAL_TIMEx_DisableDeadTimePreload
+     /tmp/cc9HXhVl.s:6777   .text.HAL_TIMEx_ConfigDeadTime:00000000 $t
+     /tmp/cc9HXhVl.s:6783   .text.HAL_TIMEx_ConfigDeadTime:00000000 HAL_TIMEx_ConfigDeadTime
+     /tmp/cc9HXhVl.s:6809   .text.HAL_TIMEx_ConfigAsymmetricalDeadTime:00000000 $t
+     /tmp/cc9HXhVl.s:6815   .text.HAL_TIMEx_ConfigAsymmetricalDeadTime:00000000 HAL_TIMEx_ConfigAsymmetricalDeadTime
+     /tmp/cc9HXhVl.s:6841   .text.HAL_TIMEx_EnableAsymmetricalDeadTime:00000000 $t
+     /tmp/cc9HXhVl.s:6847   .text.HAL_TIMEx_EnableAsymmetricalDeadTime:00000000 HAL_TIMEx_EnableAsymmetricalDeadTime
+     /tmp/cc9HXhVl.s:6871   .text.HAL_TIMEx_DisableAsymmetricalDeadTime:00000000 $t
+     /tmp/cc9HXhVl.s:6877   .text.HAL_TIMEx_DisableAsymmetricalDeadTime:00000000 HAL_TIMEx_DisableAsymmetricalDeadTime
+     /tmp/cc9HXhVl.s:6901   .text.HAL_TIMEx_ConfigEncoderIndex:00000000 $t
+     /tmp/cc9HXhVl.s:6907   .text.HAL_TIMEx_ConfigEncoderIndex:00000000 HAL_TIMEx_ConfigEncoderIndex
+     /tmp/cc9HXhVl.s:6995   .text.HAL_TIMEx_EnableEncoderIndex:00000000 $t
+     /tmp/cc9HXhVl.s:7001   .text.HAL_TIMEx_EnableEncoderIndex:00000000 HAL_TIMEx_EnableEncoderIndex
+     /tmp/cc9HXhVl.s:7025   .text.HAL_TIMEx_DisableEncoderIndex:00000000 $t
+     /tmp/cc9HXhVl.s:7031   .text.HAL_TIMEx_DisableEncoderIndex:00000000 HAL_TIMEx_DisableEncoderIndex
+     /tmp/cc9HXhVl.s:7055   .text.HAL_TIMEx_EnableEncoderFirstIndex:00000000 $t
+     /tmp/cc9HXhVl.s:7061   .text.HAL_TIMEx_EnableEncoderFirstIndex:00000000 HAL_TIMEx_EnableEncoderFirstIndex
+     /tmp/cc9HXhVl.s:7085   .text.HAL_TIMEx_DisableEncoderFirstIndex:00000000 $t
+     /tmp/cc9HXhVl.s:7091   .text.HAL_TIMEx_DisableEncoderFirstIndex:00000000 HAL_TIMEx_DisableEncoderFirstIndex
+     /tmp/cc9HXhVl.s:7115   .text.HAL_TIMEx_CommutCallback:00000000 $t
+     /tmp/cc9HXhVl.s:7121   .text.HAL_TIMEx_CommutCallback:00000000 HAL_TIMEx_CommutCallback
+     /tmp/cc9HXhVl.s:7136   .text.TIMEx_DMACommutationCplt:00000000 $t
+     /tmp/cc9HXhVl.s:7172   .text.HAL_TIMEx_CommutHalfCpltCallback:00000000 $t
+     /tmp/cc9HXhVl.s:7178   .text.HAL_TIMEx_CommutHalfCpltCallback:00000000 HAL_TIMEx_CommutHalfCpltCallback
+     /tmp/cc9HXhVl.s:7193   .text.TIMEx_DMACommutationHalfCplt:00000000 $t
+     /tmp/cc9HXhVl.s:7229   .text.HAL_TIMEx_BreakCallback:00000000 $t
+     /tmp/cc9HXhVl.s:7235   .text.HAL_TIMEx_BreakCallback:00000000 HAL_TIMEx_BreakCallback
+     /tmp/cc9HXhVl.s:7250   .text.HAL_TIMEx_Break2Callback:00000000 $t
+     /tmp/cc9HXhVl.s:7256   .text.HAL_TIMEx_Break2Callback:00000000 HAL_TIMEx_Break2Callback
+     /tmp/cc9HXhVl.s:7271   .text.HAL_TIMEx_EncoderIndexCallback:00000000 $t
+     /tmp/cc9HXhVl.s:7277   .text.HAL_TIMEx_EncoderIndexCallback:00000000 HAL_TIMEx_EncoderIndexCallback
+     /tmp/cc9HXhVl.s:7292   .text.HAL_TIMEx_DirectionChangeCallback:00000000 $t
+     /tmp/cc9HXhVl.s:7298   .text.HAL_TIMEx_DirectionChangeCallback:00000000 HAL_TIMEx_DirectionChangeCallback
+     /tmp/cc9HXhVl.s:7313   .text.HAL_TIMEx_IndexErrorCallback:00000000 $t
+     /tmp/cc9HXhVl.s:7319   .text.HAL_TIMEx_IndexErrorCallback:00000000 HAL_TIMEx_IndexErrorCallback
+     /tmp/cc9HXhVl.s:7334   .text.HAL_TIMEx_TransitionErrorCallback:00000000 $t
+     /tmp/cc9HXhVl.s:7340   .text.HAL_TIMEx_TransitionErrorCallback:00000000 HAL_TIMEx_TransitionErrorCallback
+     /tmp/cc9HXhVl.s:7355   .text.HAL_TIMEx_HallSensor_GetState:00000000 $t
+     /tmp/cc9HXhVl.s:7361   .text.HAL_TIMEx_HallSensor_GetState:00000000 HAL_TIMEx_HallSensor_GetState
+     /tmp/cc9HXhVl.s:7379   .text.HAL_TIMEx_GetChannelNState:00000000 $t
+     /tmp/cc9HXhVl.s:7385   .text.HAL_TIMEx_GetChannelNState:00000000 HAL_TIMEx_GetChannelNState
+ARM GAS  /tmp/cc9HXhVl.s 			page 234
+
+
+     /tmp/cc9HXhVl.s:2000   .text.HAL_TIMEx_OCN_Stop_IT:0000001b $d
+     /tmp/cc9HXhVl.s:2000   .text.HAL_TIMEx_OCN_Stop_IT:0000001c $t
+     /tmp/cc9HXhVl.s:2690   .text.HAL_TIMEx_OCN_Stop_DMA:0000001b $d
+     /tmp/cc9HXhVl.s:2690   .text.HAL_TIMEx_OCN_Stop_DMA:0000001c $t
+     /tmp/cc9HXhVl.s:3460   .text.HAL_TIMEx_PWMN_Stop_IT:0000001b $d
+     /tmp/cc9HXhVl.s:3460   .text.HAL_TIMEx_PWMN_Stop_IT:0000001c $t
+     /tmp/cc9HXhVl.s:4150   .text.HAL_TIMEx_PWMN_Stop_DMA:0000001b $d
+     /tmp/cc9HXhVl.s:4150   .text.HAL_TIMEx_PWMN_Stop_DMA:0000001c $t
+     /tmp/cc9HXhVl.s:6035   .text.HAL_TIMEx_TISelection:00000025 $d
+     /tmp/cc9HXhVl.s:6035   .text.HAL_TIMEx_TISelection:00000026 $t
+
+UNDEFINED SYMBOLS
+HAL_TIM_ErrorCallback
+HAL_TIM_PWM_PulseFinishedCallback
+TIM_Base_SetConfig
+TIM_TI1_SetConfig
+TIM_OC2_SetConfig
+TIM_CCxChannelCmd
+HAL_DMA_Start_IT
+TIM_DMACaptureCplt
+TIM_DMACaptureHalfCplt
+TIM_DMAError
+HAL_DMA_Abort_IT
+TIM_DMADelayPulseHalfCplt
+HAL_GetTick
+TIM_ETR_SetConfig
diff --git a/squeow_sw/build/stm32g4xx_hal_tim_ex.o b/squeow_sw/build/stm32g4xx_hal_tim_ex.o
new file mode 100644
index 0000000000000000000000000000000000000000..87e517d7ed99beb4b5d214012cf2f5a5ffc72850
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diff --git a/squeow_sw/build/stm32g4xx_hal_uart.d b/squeow_sw/build/stm32g4xx_hal_uart.d
new file mode 100644
index 0000000..da5e8c0
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_uart.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_uart.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_uart.lst b/squeow_sw/build/stm32g4xx_hal_uart.lst
new file mode 100644
index 0000000..704e90f
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_uart.lst
@@ -0,0 +1,24070 @@
+ARM GAS  /tmp/cceWHrnJ.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_uart.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c"
+  20              		.section	.text.UART_EndTxTransfer,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	UART_EndTxTransfer:
+  27              	.LFB378:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @file    stm32g4xx_hal_uart.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief   UART HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           + IO operation functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           + Peripheral Control functions
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ******************************************************************************
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @attention
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * Copyright (c) 2019 STMicroelectronics.
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * All rights reserved.
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * in the root directory of this software component.
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ******************************************************************************
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   @verbatim
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****  ===============================================================================
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                         ##### How to use this driver #####
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****  ===============================================================================
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   [..]
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     The UART HAL driver can be used as follows:
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+ARM GAS  /tmp/cceWHrnJ.s 			page 2
+
+
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) Enable the USARTx interface clock.
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) UART pins configuration:
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             (+++) Enable the clock for the UART GPIOs.
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             (+++) Configure these UART pins as alternate function pull-up.
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****              and HAL_UART_Receive_IT() APIs):
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             (+++) Configure the USARTx interrupt priority.
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             (+++) Enable the NVIC USART IRQ handle.
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) UART interrupts handling:
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****               -@@-  The specific UART interrupts (Transmission complete interrupt,
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                 RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                 are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                 inside the transmit and receive processes.
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****              and HAL_UART_Receive_DMA() APIs):
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             (+++) Declare a DMA handle structure for the Tx/Rx channel.
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             (+++) Enable the DMAx interface clock.
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             (+++) Configure the DMA Tx/Rx channel.
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             (+++) Configure the priority and enable the NVIC for the transfer complete
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                   interrupt on the DMA Tx/Rx channel.
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         in the huart handle AdvancedInit structure.
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) For the UART asynchronous mode, initialize the UART registers by calling
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         the HAL_UART_Init() API.
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) For the UART Half duplex mode, initialize the UART registers by calling
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         the HAL_HalfDuplex_Init() API.
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         by calling the HAL_LIN_Init() API.
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) For the UART Multiprocessor mode, initialize the UART registers
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         by calling the HAL_MultiProcessor_Init() API.
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         by calling the HAL_RS485Ex_Init() API.
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     [..]
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Ini
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         calling the customized HAL_UART_MspInit() API.
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ##### Callback registration #####
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ==================================
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     [..]
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     allows the user to configure dynamically the driver callbacks.
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 3
+
+
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     [..]
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     Use Function HAL_UART_RegisterCallback() to register a user callback.
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     Function HAL_UART_RegisterCallback() allows to register following callbacks:
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) TxCpltCallback            : Tx Complete Callback.
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) RxCpltCallback            : Rx Complete Callback.
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) ErrorCallback             : Error Callback.
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) AbortCpltCallback         : Abort Complete Callback.
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) WakeupCallback            : Wakeup Callback.
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) MspInitCallback           : UART MspInit.
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) MspDeInitCallback         : UART MspDeInit.
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     This function takes as parameters the HAL peripheral handle, the Callback ID
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     and a pointer to the user callback function.
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     [..]
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     weak (surcharged) function.
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     and the Callback ID.
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     This function allows to reset following callbacks:
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) TxCpltCallback            : Tx Complete Callback.
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) RxCpltCallback            : Rx Complete Callback.
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) ErrorCallback             : Error Callback.
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) AbortCpltCallback         : Abort Complete Callback.
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) WakeupCallback            : Wakeup Callback.
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) MspInitCallback           : UART MspInit.
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (+) MspDeInitCallback         : UART MspDeInit.
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     [..]
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     For specific callback RxEventCallback, use dedicated registration/reset functions:
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     [..]
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     all callbacks are set to the corresponding weak (surcharged) functions:
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     Exception done for MspInit and MspDeInit functions that are respectively
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     [..]
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     Exception done MspInit/MspDeInit that can be registered/unregistered
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+ARM GAS  /tmp/cceWHrnJ.s 			page 4
+
+
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MspInit/DeInit callbacks can be used during the Init/DeInit.
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     In that case first register the MspInit/MspDeInit user callbacks
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     or HAL_UART_Init() function.
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     [..]
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     not defined, the callback registration feature is not available
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     and weak (surcharged) callbacks are used.
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   @endverbatim
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ******************************************************************************
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /* Includes ------------------------------------------------------------------*/
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #include "stm32g4xx_hal.h"
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /** @addtogroup STM32G4xx_HAL_Driver
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @{
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /** @defgroup UART UART
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief HAL UART module driver
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @{
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #ifdef HAL_UART_MODULE_ENABLED
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /* Private typedef -----------------------------------------------------------*/
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /* Private define ------------------------------------------------------------*/
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /** @defgroup UART_Private_Constants UART Private Constants
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @{
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | U
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                       USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 f
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                       USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of paramete
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @}
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /* Private macros ------------------------------------------------------------*/
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /* Private function prototypes -----------------------------------------------*/
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /** @addtogroup UART_Private_Functions
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @{
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+ARM GAS  /tmp/cceWHrnJ.s 			page 5
+
+
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMAError(DMA_HandleTypeDef *hdma);
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @}
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /* Private variables ---------------------------------------------------------*/
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /** @addtogroup UART_Private_variables
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @{
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @}
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /* Exported Constants --------------------------------------------------------*/
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /* Exported functions --------------------------------------------------------*/
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /** @defgroup UART_Exported_Functions UART Exported Functions
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @{
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *  @brief    Initialization and Configuration functions
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** @verbatim
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** ===============================================================================
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             ##### Initialization and Configuration functions #####
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****  ===============================================================================
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     [..]
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     in asynchronous mode.
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (+) For the asynchronous mode the parameters below can be configured:
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) Baud Rate
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) Word Length
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) Stop Bit
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****              in the data register is transmitted but is changed by the parity bit.
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) Hardware flow control
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) Receiver/transmitter modes
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) Over Sampling Method
+ARM GAS  /tmp/cceWHrnJ.s 			page 6
+
+
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) One-Bit Sampling Method
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (+) For the asynchronous mode, the following advanced features can be configured as well:
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) TX and/or RX pin level inversion
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) data logical level inversion
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) RX and TX pins swap
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) RX overrun detection disabling
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) DMA disabling on RX error
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) MSB first on communication line
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (++) auto Baud rate detection
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     [..]
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     and UART multiprocessor mode configuration procedures (details for the procedures
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     are available in reference manual).
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** @endverbatim
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   8-bit or 9-bit), the possible UART formats are listed in the
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   following table.
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   Table 1. UART frame format.
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     +-----------------------------------------------------------------------+
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |---------|---------|-----------|---------------------------------------|
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |---------|---------|-----------|---------------------------------------|
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |---------|---------|-----------|---------------------------------------|
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |---------|---------|-----------|---------------------------------------|
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |---------|---------|-----------|---------------------------------------|
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |---------|---------|-----------|---------------------------------------|
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     +-----------------------------------------------------------------------+
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @{
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Initialize the UART mode according to the specified
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *        parameters in the UART_InitTypeDef and initialize the associated handle.
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart == NULL)
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ARM GAS  /tmp/cceWHrnJ.s 			page 7
+
+
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Check the parameters */
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Check the parameters */
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_RESET)
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Allocate lock resource and initialize it */
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->Lock = HAL_UNLOCKED;
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_InitCallbacksToDefault(huart);
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->MspInitCallback == NULL)
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->MspInitCallback = HAL_UART_MspInit;
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Init the low level hardware */
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->MspInitCallback(huart);
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Init the low level hardware : GPIO, CLOCK */
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UART_MspInit(huart);
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_DISABLE(huart);
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Set the UART Communication parameters */
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (UART_SetConfig(huart) == HAL_ERROR)
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_AdvFeatureConfig(huart);
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* In asynchronous mode, the following bits must be kept cleared:
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   - LINEN and CLKEN bits in the USART_CR2 register,
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_ENABLE(huart);
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return (UART_CheckIdleState(huart));
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 8
+
+
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Initialize the half-duplex mode according to the specified
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *        parameters in the UART_InitTypeDef and creates the associated handle.
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart == NULL)
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check UART instance */
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_RESET)
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Allocate lock resource and initialize it */
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->Lock = HAL_UNLOCKED;
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_InitCallbacksToDefault(huart);
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->MspInitCallback == NULL)
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->MspInitCallback = HAL_UART_MspInit;
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Init the low level hardware */
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->MspInitCallback(huart);
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Init the low level hardware : GPIO, CLOCK */
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UART_MspInit(huart);
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_DISABLE(huart);
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Set the UART Communication parameters */
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (UART_SetConfig(huart) == HAL_ERROR)
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_AdvFeatureConfig(huart);
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* In half-duplex mode, the following bits must be kept cleared:
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   - LINEN and CLKEN bits in the USART_CR2 register,
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   - SCEN and IREN bits in the USART_CR3 register.*/
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ARM GAS  /tmp/cceWHrnJ.s 			page 9
+
+
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_ENABLE(huart);
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return (UART_CheckIdleState(huart));
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Initialize the LIN mode according to the specified
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *        parameters in the UART_InitTypeDef and creates the associated handle.
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart             UART handle.
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param BreakDetectLength Specifies the LIN break detection length.
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *        This parameter can be one of the following values:
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart == NULL)
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the LIN UART instance */
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the Break detection length parameter */
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* LIN mode limited to 16-bit oversampling only */
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* LIN mode limited to 8-bit data length */
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->Init.WordLength != UART_WORDLENGTH_8B)
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_RESET)
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Allocate lock resource and initialize it */
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->Lock = HAL_UNLOCKED;
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_InitCallbacksToDefault(huart);
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->MspInitCallback == NULL)
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->MspInitCallback = HAL_UART_MspInit;
+ARM GAS  /tmp/cceWHrnJ.s 			page 10
+
+
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Init the low level hardware */
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->MspInitCallback(huart);
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Init the low level hardware : GPIO, CLOCK */
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UART_MspInit(huart);
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_DISABLE(huart);
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Set the UART Communication parameters */
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (UART_SetConfig(huart) == HAL_ERROR)
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_AdvFeatureConfig(huart);
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* In LIN mode, the following bits must be kept cleared:
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   - LINEN and CLKEN bits in the USART_CR2 register,
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   - SCEN and IREN bits in the USART_CR3 register.*/
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Set the USART LIN Break detection length. */
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_ENABLE(huart);
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return (UART_CheckIdleState(huart));
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Initialize the multiprocessor mode according to the specified
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *        parameters in the UART_InitTypeDef and initialize the associated handle.
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart        UART handle.
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Address      UART node address (4-, 6-, 7- or 8-bit long).
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param WakeUpMethod Specifies the UART wakeup method.
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *        This parameter can be one of the following values:
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note  If the user resorts to idle line detection wake up, the Address parameter
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *        is useless and ignored by the initialization function.
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note  If the user resorts to address mark wake up, the address length detection
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *        is configured by default to 4 bits only. For the UART to be able to
+ARM GAS  /tmp/cceWHrnJ.s 			page 11
+
+
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *        manage 6-, 7- or 8-bit long addresses detection, the API
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *        HAL_MultiProcessor_Init().
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t Wake
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart == NULL)
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the wake up method parameter */
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_RESET)
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Allocate lock resource and initialize it */
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->Lock = HAL_UNLOCKED;
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_InitCallbacksToDefault(huart);
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->MspInitCallback == NULL)
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->MspInitCallback = HAL_UART_MspInit;
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Init the low level hardware */
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->MspInitCallback(huart);
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Init the low level hardware : GPIO, CLOCK */
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UART_MspInit(huart);
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_DISABLE(huart);
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Set the UART Communication parameters */
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (UART_SetConfig(huart) == HAL_ERROR)
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_AdvFeatureConfig(huart);
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* In multiprocessor mode, the following bits must be kept cleared:
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   - LINEN and CLKEN bits in the USART_CR2 register,
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ARM GAS  /tmp/cceWHrnJ.s 			page 12
+
+
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* If address mark wake up method is chosen, set the USART address node */
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Set the wake up method by setting the WAKE bit in the CR1 register */
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_ENABLE(huart);
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return (UART_CheckIdleState(huart));
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief DeInitialize the UART peripheral.
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart == NULL)
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the parameters */
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_DISABLE(huart);
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->Instance->CR1 = 0x0U;
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->Instance->CR2 = 0x0U;
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->Instance->CR3 = 0x0U;
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->MspDeInitCallback == NULL)
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* DeInit the low level hardware */
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->MspDeInitCallback(huart);
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* DeInit the low level hardware */
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_UART_MspDeInit(huart);
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_RESET;
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_RESET;
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ARM GAS  /tmp/cceWHrnJ.s 			page 13
+
+
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UNLOCK(huart);
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Initialize the UART MSP.
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(huart);
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             the HAL_UART_MspInit can be implemented in the user file
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****    */
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief DeInitialize the UART MSP.
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(huart);
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             the HAL_UART_MspDeInit can be implemented in the user file
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****    */
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Register a User UART Callback
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         To be used instead of the weak predefined callback
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart uart handle
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  CallbackID ID of the callback to be registered
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         This parameter can be one of the following values:
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  pCallback pointer to the Callback function
+ARM GAS  /tmp/cceWHrnJ.s 			page 14
+
+
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef C
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                             pUART_CallbackTypeDef pCallback)
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (pCallback == NULL)
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_READY)
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     switch (CallbackID)
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxHalfCpltCallback = pCallback;
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_TX_COMPLETE_CB_ID :
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxCpltCallback = pCallback;
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxHalfCpltCallback = pCallback;
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_RX_COMPLETE_CB_ID :
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxCpltCallback = pCallback;
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_ERROR_CB_ID :
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ErrorCallback = pCallback;
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_ABORT_COMPLETE_CB_ID :
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->AbortCpltCallback = pCallback;
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->AbortTransmitCpltCallback = pCallback;
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->AbortReceiveCpltCallback = pCallback;
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_WAKEUP_CB_ID :
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->WakeupCallback = pCallback;
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_RX_FIFO_FULL_CB_ID :
+ARM GAS  /tmp/cceWHrnJ.s 			page 15
+
+
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxFifoFullCallback = pCallback;
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxFifoEmptyCallback = pCallback;
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_MSPINIT_CB_ID :
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->MspInitCallback = pCallback;
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_MSPDEINIT_CB_ID :
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->MspDeInitCallback = pCallback;
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       default :
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         status =  HAL_ERROR;
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else if (huart->gState == HAL_UART_STATE_RESET)
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     switch (CallbackID)
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_MSPINIT_CB_ID :
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->MspInitCallback = pCallback;
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_MSPDEINIT_CB_ID :
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->MspDeInitCallback = pCallback;
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       default :
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         status =  HAL_ERROR;
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     status =  HAL_ERROR;
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UNLOCK(huart);
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return status;
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Unregister an UART Callback
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         UART callaback is redirected to the weak predefined callback
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart uart handle
+ARM GAS  /tmp/cceWHrnJ.s 			page 16
+
+
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  CallbackID ID of the callback to be unregistered
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         This parameter can be one of the following values:
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_UART_STATE_READY == huart->gState)
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     switch (CallbackID)
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHa
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_TX_COMPLETE_CB_ID :
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpl
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHal
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_RX_COMPLETE_CB_ID :
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpl
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_ERROR_CB_ID :
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak Error
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_ABORT_COMPLETE_CB_ID :
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak Abort
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                                                   AbortTransmitCplt
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ARM GAS  /tmp/cceWHrnJ.s 			page 17
+
+
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                                                   AbortReceiveCpltC
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_WAKEUP_CB_ID :
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak Wakeu
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_RX_FIFO_FULL_CB_ID :
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFif
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFif
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_MSPINIT_CB_ID :
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspIn
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_MSPDEINIT_CB_ID :
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDe
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       default :
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         status =  HAL_ERROR;
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else if (HAL_UART_STATE_RESET == huart->gState)
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     switch (CallbackID)
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_MSPINIT_CB_ID :
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->MspInitCallback = HAL_UART_MspInit;
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case HAL_UART_MSPDEINIT_CB_ID :
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       default :
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         status =  HAL_ERROR;
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     status =  HAL_ERROR;
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 18
+
+
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UNLOCK(huart);
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return status;
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Register a User UART Rx Event Callback
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         To be used instead of the weak predefined callback
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart     Uart handle
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  pCallback Pointer to the Rx Event Callback function
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallback
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (pCallback == NULL)
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Process locked */
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_READY)
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxEventCallback = pCallback;
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     status =  HAL_ERROR;
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Release Lock */
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UNLOCK(huart);
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return status;
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  UnRegister the UART Rx Event Callback
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefine
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart     Uart handle
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Process locked */
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_READY)
+ARM GAS  /tmp/cceWHrnJ.s 			page 19
+
+
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     status =  HAL_ERROR;
+1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Release Lock */
+1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UNLOCK(huart);
+1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return status;
+1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @}
+1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group2 IO operation functions
+1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief UART Transmit/Receive functions
+1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *
+1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** @verbatim
+1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****  ===============================================================================
+1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                       ##### IO operation functions #####
+1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****  ===============================================================================
+1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     This subsection provides a set of functions allowing to manage the UART asynchronous
+1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     and Half duplex data transfers.
+1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) There are two mode of transfer:
+1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****        (+) Blocking mode: The communication is performed in polling mode.
+1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            The HAL status of all data processing is returned by the same function
+1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            after finishing transfer.
+1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****        (+) Non-Blocking mode: The communication is performed using Interrupts
+1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            or DMA, These API's return the HAL status.
+1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            The end of the data processing will be indicated through the
+1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            using DMA mode.
+1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            will be executed respectively at the end of the transmit or Receive process
+1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is
+1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) Blocking mode API's are :
+1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_Transmit()
+1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_Receive()
+1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) Non-Blocking mode API's with Interrupt are :
+1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_Transmit_IT()
+1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_Receive_IT()
+1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_IRQHandler()
+1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) Non-Blocking mode API's with DMA are :
+1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_Transmit_DMA()
+1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_Receive_DMA()
+1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_DMAPause()
+ARM GAS  /tmp/cceWHrnJ.s 			page 20
+
+
+1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_DMAResume()
+1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_DMAStop()
+1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_TxHalfCpltCallback()
+1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_TxCpltCallback()
+1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_RxHalfCpltCallback()
+1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_RxCpltCallback()
+1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_ErrorCallback()
+1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) Non-Blocking mode transfers could be aborted using Abort API's :
+1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_Abort()
+1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_AbortTransmit()
+1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_AbortReceive()
+1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_Abort_IT()
+1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_AbortTransmit_IT()
+1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_AbortReceive_IT()
+1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Call
+1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_AbortCpltCallback()
+1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_AbortTransmitCpltCallback()
+1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UART_AbortReceiveCpltCallback()
+1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes o
+1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         reception services:
+1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         (+) HAL_UARTEx_RxEventCallback()
+1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         Errors are handled as follows :
+1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but er
+1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            in Interrupt mode reception .
+1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            Received character is then retrieved and stored in Rx buffer, Error code is set to allow
+1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            Transfer is kept ongoing on UART side.
+1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            If user wants to abort it, Abort services should be called by user.
+1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborte
+1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
+1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            user callback is executed.
+1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     -@- In the Half duplex communication, it is forbidden to run the transmit
+1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** @endverbatim
+1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @{
+1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Send an amount of data in blocking mode.
+1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-
+1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         of u16 provided through pData.
+1111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *       data to the TXFIFO. Write operations to the TDR register are performed
+1113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *       when TXFNF flag is set. From hardware perspective, TXFNF flag and
+1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *       TXE are mapped on the same bit-field.
+ARM GAS  /tmp/cceWHrnJ.s 			page 21
+
+
+1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart   UART handle.
+1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param pData   Pointer to data buffer (u8 or u16 data elements).
+1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Size    Amount of data elements (u8 or u16) to be sent.
+1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Timeout Timeout duration.
+1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size,
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const uint8_t  *pdata8bits;
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const uint16_t *pdata16bits;
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t tickstart;
+1126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Tx process is not already ongoing */
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_READY)
+1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((pData == NULL) || (Size == 0U))
+1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return  HAL_ERROR;
+1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_LOCK(huart);
+1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ErrorCode = HAL_UART_ERROR_NONE;
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->gState = HAL_UART_STATE_BUSY_TX;
+1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Init tickstart for timeout management */
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     tickstart = HAL_GetTick();
+1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferSize  = Size;
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = Size;
+1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       pdata8bits  = NULL;
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       pdata16bits = (const uint16_t *) pData;
+1151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+1153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       pdata8bits  = pData;
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       pdata16bits = NULL;
+1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UNLOCK(huart);
+1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     while (huart->TxXferCount > 0U)
+1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         return HAL_TIMEOUT;
+1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (pdata8bits == NULL)
+1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata16bits++;
+1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+ARM GAS  /tmp/cceWHrnJ.s 			page 22
+
+
+1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata8bits++;
+1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->TxXferCount--;
+1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return HAL_TIMEOUT;
+1182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* At end of Tx process, restore huart->gState to Ready */
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->gState = HAL_UART_STATE_READY;
+1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_OK;
+1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_BUSY;
+1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Receive an amount of data in blocking mode.
+1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-
+1198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         the received data is handled as a set of u16. In this case, Size must indicate the numb
+1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         of u16 available through pData.
+1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *       is not empty. Read operations from the RDR register are performed when
+1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *       RXFNE flag is set. From hardware perspective, RXFNE flag and
+1203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *       RXNE are mapped on the same bit-field.
+1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart   UART handle.
+1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param pData   Pointer to data buffer (u8 or u16 data elements).
+1206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Size    Amount of data elements (u8 or u16) to be received.
+1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Timeout Timeout duration.
+1208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint8_t  *pdata8bits;
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t *pdata16bits;
+1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t uhMask;
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t tickstart;
+1216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Rx process is not already ongoing */
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->RxState == HAL_UART_STATE_READY)
+1219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((pData == NULL) || (Size == 0U))
+1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return  HAL_ERROR;
+1223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_LOCK(huart);
+1226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ErrorCode = HAL_UART_ERROR_NONE;
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxState = HAL_UART_STATE_BUSY_RX;
+ARM GAS  /tmp/cceWHrnJ.s 			page 23
+
+
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Init tickstart for timeout management */
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     tickstart = HAL_GetTick();
+1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferSize  = Size;
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount = Size;
+1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Computation of UART mask to apply to RDR register */
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_MASK_COMPUTATION(huart);
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+1240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+1243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       pdata8bits  = NULL;
+1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       pdata16bits = (uint16_t *) pData;
+1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+1248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       pdata8bits  = pData;
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       pdata16bits = NULL;
+1251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UNLOCK(huart);
+1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* as long as data have to be received */
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     while (huart->RxXferCount > 0U)
+1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         return HAL_TIMEOUT;
+1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (pdata8bits == NULL)
+1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata16bits++;
+1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata8bits++;
+1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxXferCount--;
+1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* At end of Rx process, restore huart->RxState to Ready */
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxState = HAL_UART_STATE_READY;
+1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_OK;
+1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_BUSY;
+1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 24
+
+
+1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Send an amount of data in interrupt mode.
+1288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-
+1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         of u16 provided through pData.
+1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param pData Pointer to data buffer (u8 or u16 data elements).
+1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Size  Amount of data elements (u8 or u16) to be sent.
+1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Si
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Tx process is not already ongoing */
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_READY)
+1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((pData == NULL) || (Size == 0U))
+1302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return HAL_ERROR;
+1304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_LOCK(huart);
+1307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pTxBuffPtr  = pData;
+1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferSize  = Size;
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = Size;
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxISR       = NULL;
+1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ErrorCode = HAL_UART_ERROR_NONE;
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->gState = HAL_UART_STATE_BUSY_TX;
+1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Configure Tx interrupt processing */
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the Tx ISR function pointer according to the data word length */
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE
+1321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxISR = UART_TxISR_16BIT_FIFOEN;
+1323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+1325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxISR = UART_TxISR_8BIT_FIFOEN;
+1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UNLOCK(huart);
+1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Enable the TX FIFO threshold interrupt */
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+1333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the Tx ISR function pointer according to the data word length */
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE
+1338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxISR = UART_TxISR_16BIT;
+1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+1342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ARM GAS  /tmp/cceWHrnJ.s 			page 25
+
+
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxISR = UART_TxISR_8BIT;
+1344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UNLOCK(huart);
+1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Enable the Transmit Data Register Empty interrupt */
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+1350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_OK;
+1353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_BUSY;
+1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Receive an amount of data in interrupt mode.
+1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-
+1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         the received data is handled as a set of u16. In this case, Size must indicate the numb
+1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         of u16 available through pData.
+1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param pData Pointer to data buffer (u8 or u16 data elements).
+1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Size  Amount of data elements (u8 or u16) to be received.
+1368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Rx process is not already ongoing */
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->RxState == HAL_UART_STATE_READY)
+1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((pData == NULL) || (Size == 0U))
+1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return HAL_ERROR;
+1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_LOCK(huart);
+1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Set Reception type to Standard reception */
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+1384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (!(IS_LPUART_INSTANCE(huart->Instance)))
+1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Check that USART RTOEN bit is set */
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Enable the UART Receiver Timeout Interrupt */
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+1392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return (UART_Start_Receive_IT(huart, pData, Size));
+1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_BUSY;
+ARM GAS  /tmp/cceWHrnJ.s 			page 26
+
+
+1400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Send an amount of data in DMA mode.
+1405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-
+1406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         of u16 provided through pData.
+1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param pData Pointer to data buffer (u8 or u16 data elements).
+1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Size  Amount of data elements (u8 or u16) to be sent.
+1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t S
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Tx process is not already ongoing */
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_READY)
+1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((pData == NULL) || (Size == 0U))
+1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return HAL_ERROR;
+1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_LOCK(huart);
+1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pTxBuffPtr  = pData;
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferSize  = Size;
+1427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = Size;
+1428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ErrorCode = HAL_UART_ERROR_NONE;
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->gState = HAL_UART_STATE_BUSY_TX;
+1431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmatx != NULL)
+1433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the UART DMA transfer complete callback */
+1435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+1436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the UART DMA Half transfer complete callback */
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+1439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the DMA error callback */
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmatx->XferErrorCallback = UART_DMAError;
+1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the DMA abort callback */
+1444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmatx->XferAbortCallback = NULL;
+1445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Enable the UART transmit DMA channel */
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->
+1448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Set error code to DMA */
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ErrorCode = HAL_UART_ERROR_DMA;
+1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         __HAL_UNLOCK(huart);
+1453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Restore huart->gState to ready */
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->gState = HAL_UART_STATE_READY;
+1456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 27
+
+
+1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         return HAL_ERROR;
+1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Clear the TC flag in the ICR register */
+1461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+1462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UNLOCK(huart);
+1464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Enable the DMA transfer for transmit request by setting the DMAT bit
+1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     in the UART CR3 register */
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+1468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_OK;
+1470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_BUSY;
+1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Receive an amount of data in DMA mode.
+1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   When the UART parity is enabled (PCE = 1), the received data contain
+1480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         the parity bit (MSB position).
+1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-
+1482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         the received data is handled as a set of u16. In this case, Size must indicate the numb
+1483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         of u16 available through pData.
+1484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param pData Pointer to data buffer (u8 or u16 data elements).
+1486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Size  Amount of data elements (u8 or u16) to be received.
+1487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Rx process is not already ongoing */
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->RxState == HAL_UART_STATE_READY)
+1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((pData == NULL) || (Size == 0U))
+1495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return HAL_ERROR;
+1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_LOCK(huart);
+1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Set Reception type to Standard reception */
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+1503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (!(IS_LPUART_INSTANCE(huart->Instance)))
+1505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Check that USART RTOEN bit is set */
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+1508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Enable the UART Receiver Timeout Interrupt */
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 28
+
+
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return (UART_Start_Receive_DMA(huart, pData, Size));
+1515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_BUSY;
+1519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Pause the DMA Transfer.
+1524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef gstate = huart->gState;
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef rxstate = huart->RxState;
+1531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+1536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable the UART DMA Tx request */
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+1546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable the UART DMA Rx request */
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UNLOCK(huart);
+1552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Resume the DMA Transfer.
+1558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_BUSY_TX)
+1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Enable the UART DMA Tx request */
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ARM GAS  /tmp/cceWHrnJ.s 			page 29
+
+
+1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Clear the Overrun flag before resuming the Rx transfer */
+1573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+1574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->Init.Parity != UART_PARITY_NONE)
+1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {    
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+1581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Enable the UART DMA Rx request */
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UNLOCK(huart);
+1587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+1589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Stop the DMA Transfer.
+1593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+1594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* The Lock is not implemented on this API to allow the user application
+1599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
+1600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+1602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      the stream and the corresponding call back is executed. */
+1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef gstate = huart->gState;
+1606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef rxstate = huart->RxState;
+1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Stop UART DMA Tx request if ongoing */
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+1610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+1611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Abort the UART DMA Tx channel */
+1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmatx != NULL)
+1616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+1618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+1620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+1621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Set error code to DMA */
+1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode = HAL_UART_ERROR_DMA;
+1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           return HAL_TIMEOUT;
+1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ARM GAS  /tmp/cceWHrnJ.s 			page 30
+
+
+1628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_EndTxTransfer(huart);
+1630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Stop UART DMA Rx request if ongoing */
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+1637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Abort the UART DMA Rx channel */
+1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmarx != NULL)
+1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+1644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Set error code to DMA */
+1646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode = HAL_UART_ERROR_DMA;
+1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           return HAL_TIMEOUT;
+1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_EndRxTransfer(huart);
+1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Abort ongoing transfers (blocking mode).
+1661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or 
+1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         This procedure performs following operations :
+1664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Disable UART Interrupts (Tx and Rx)
+1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Disable the DMA transfer in the peripheral register (if enabled)
+1666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Set handle State to READY
+1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considere
+1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interr
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+1675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+1677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+1679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+1680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+1682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Abort the UART DMA Tx channel if enabled */
+ARM GAS  /tmp/cceWHrnJ.s 			page 31
+
+
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable the UART DMA Tx request if enabled */
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmatx != NULL)
+1692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the UART DMA Abort callback to Null.
+1694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          No call back execution at end of DMA abort procedure */
+1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmatx->XferAbortCallback = NULL;
+1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Set error code to DMA */
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode = HAL_UART_ERROR_DMA;
+1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           return HAL_TIMEOUT;
+1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+1706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Abort the UART DMA Rx channel if enabled */
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable the UART DMA Rx request if enabled */
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmarx != NULL)
+1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the UART DMA Abort callback to Null.
+1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          No call back execution at end of DMA abort procedure */
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmarx->XferAbortCallback = NULL;
+1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+1727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Set error code to DMA */
+1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode = HAL_UART_ERROR_DMA;
+1729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           return HAL_TIMEOUT;
+1731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+1732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Reset Tx and Rx transfer counters */
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxXferCount = 0U;
+1738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Clear the Error flags in the ICR register */
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+ARM GAS  /tmp/cceWHrnJ.s 			page 32
+
+
+1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Flush the whole TX FIFO (if needed) */
+1744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Discard the received data */
+1750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+1751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Restore huart->gState and huart->RxState to Ready */
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState  = HAL_UART_STATE_READY;
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ErrorCode = HAL_UART_ERROR_NONE;
+1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+1760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Abort ongoing Transmit transfer (blocking mode).
+1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+1765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt 
+1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         This procedure performs following operations :
+1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Disable UART Interrupts (Tx)
+1768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Disable the DMA transfer in the peripheral register (if enabled)
+1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+1770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Set handle State to READY
+1771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considere
+1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable TCIE, TXEIE and TXFTIE interrupts */
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Abort the UART DMA Tx channel if enabled */
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+1782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable the UART DMA Tx request if enabled */
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmatx != NULL)
+1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the UART DMA Abort callback to Null.
+1790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          No call back execution at end of DMA abort procedure */
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmatx->XferAbortCallback = NULL;
+1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+1794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+1796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+1797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Set error code to DMA */
+1798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode = HAL_UART_ERROR_DMA;
+ARM GAS  /tmp/cceWHrnJ.s 			page 33
+
+
+1799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           return HAL_TIMEOUT;
+1801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+1802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Reset Tx transfer counter */
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxXferCount = 0U;
+1808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Flush the whole TX FIFO (if needed) */
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+1811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+1813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Restore huart->gState to Ready */
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_READY;
+1817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+1819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Abort ongoing Receive transfer (blocking mode).
+1823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+1824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt 
+1825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         This procedure performs following operations :
+1826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Disable UART Interrupts (Rx)
+1827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Disable the DMA transfer in the peripheral register (if enabled)
+1828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+1829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Set handle State to READY
+1830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considere
+1831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+1838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+1841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+1843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Abort the UART DMA Rx channel if enabled */
+1846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+1847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable the UART DMA Rx request if enabled */
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+1850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+1852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmarx != NULL)
+1853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the UART DMA Abort callback to Null.
+1855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          No call back execution at end of DMA abort procedure */
+ARM GAS  /tmp/cceWHrnJ.s 			page 34
+
+
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmarx->XferAbortCallback = NULL;
+1857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+1859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+1861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+1862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Set error code to DMA */
+1863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode = HAL_UART_ERROR_DMA;
+1864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           return HAL_TIMEOUT;
+1866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+1867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Reset Rx transfer counter */
+1872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+1873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Clear the Error flags in the ICR register */
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+1876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Discard the received data */
+1878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+1879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Restore huart->RxState to Ready */
+1881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+1882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+1883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+1885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+1886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+1888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Abort ongoing transfers (Interrupt mode).
+1889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+1890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or 
+1891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         This procedure performs following operations :
+1892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Disable UART Interrupts (Tx and Rx)
+1893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Disable the DMA transfer in the peripheral register (if enabled)
+1894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+1895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Set handle State to READY
+1896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - At abort completion, call user abort complete callback
+1897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+1898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         considered as completed only when user abort complete callback is executed (not when ex
+1899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+1900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+1901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+1902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t abortcplt = 1U;
+1904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable interrupts */
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEI
+1907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE));
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+1909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+1911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+1912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ARM GAS  /tmp/cceWHrnJ.s 			page 35
+
+
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+1914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks sh
+1917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      before any call to DMA Abort functions */
+1918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* DMA Tx Handle is valid */
+1919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->hdmatx != NULL)
+1920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+1922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****        Otherwise, set it to NULL */
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+1924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+1926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+1928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmatx->XferAbortCallback = NULL;
+1930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* DMA Rx Handle is valid */
+1933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->hdmarx != NULL)
+1934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+1936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****        Otherwise, set it to NULL */
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+1938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+1940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+1942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmarx->XferAbortCallback = NULL;
+1944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Abort the UART DMA Tx channel if enabled */
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+1949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable DMA Tx at UART level */
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+1952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+1954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmatx != NULL)
+1955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* UART Tx DMA Abort callback has already been initialised :
+1957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+1958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Abort DMA TX */
+1960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+1961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->hdmatx->XferAbortCallback = NULL;
+1963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+1965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         abortcplt = 0U;
+1967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ARM GAS  /tmp/cceWHrnJ.s 			page 36
+
+
+1970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Abort the UART DMA Rx channel if enabled */
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+1973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable the UART DMA Rx request if enabled */
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+1976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+1978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmarx != NULL)
+1979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+1980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* UART Rx DMA Abort callback has already been initialised :
+1981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+1982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Abort DMA RX */
+1984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+1985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->hdmarx->XferAbortCallback = NULL;
+1987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         abortcplt = 1U;
+1988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+1990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+1991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         abortcplt = 0U;
+1992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+1993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+1994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+1995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+1996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* if no DMA abort complete callback execution is required => call user Abort Complete callback *
+1997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (abortcplt == 1U)
+1998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+1999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Reset Tx and Rx transfer counters */
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = 0U;
+2001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount = 0U;
+2002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Clear ISR function pointers */
+2004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxISR = NULL;
+2005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxISR = NULL;
+2006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Reset errorCode */
+2008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ErrorCode = HAL_UART_ERROR_NONE;
+2009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Clear the Error flags in the ICR register */
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF
+2012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Flush the whole TX FIFO (if needed) */
+2014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+2015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+2017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Discard the received data */
+2020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+2021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Restore huart->gState and huart->RxState to Ready */
+2023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->gState  = HAL_UART_STATE_READY;
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxState = HAL_UART_STATE_READY;
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+2026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 37
+
+
+2027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* As no DMA to be aborted, call directly user Abort complete callback */
+2028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call registered Abort complete callback */
+2030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->AbortCpltCallback(huart);
+2031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call legacy weak Abort complete callback */
+2033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UART_AbortCpltCallback(huart);
+2034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+2035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+2038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+2042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt 
+2044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         This procedure performs following operations :
+2045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Disable UART Interrupts (Tx)
+2046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Disable the DMA transfer in the peripheral register (if enabled)
+2047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+2048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Set handle State to READY
+2049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - At abort completion, call user abort complete callback
+2050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+2051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         considered as completed only when user abort complete callback is executed (not when ex
+2052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+2053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+2055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable interrupts */
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+2059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Abort the UART DMA Tx channel if enabled */
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+2062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable the UART DMA Tx request if enabled */
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+2065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmatx != NULL)
+2068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the UART DMA Abort callback :
+2070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+2072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Abort DMA TX */
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+2075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+2076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+2077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->hdmatx->XferAbortCallback(huart->hdmatx);
+2078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+2079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+2081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Reset Tx transfer counter */
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->TxXferCount = 0U;
+ARM GAS  /tmp/cceWHrnJ.s 			page 38
+
+
+2084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Clear TxISR function pointers */
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->TxISR = NULL;
+2087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Restore huart->gState to Ready */
+2089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->gState = HAL_UART_STATE_READY;
+2090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* As no DMA to be aborted, call directly user Abort complete callback */
+2092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Call registered Abort Transmit Complete Callback */
+2094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->AbortTransmitCpltCallback(huart);
+2095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Call legacy weak Abort Transmit Complete Callback */
+2097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       HAL_UART_AbortTransmitCpltCallback(huart);
+2098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+2099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+2102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Reset Tx transfer counter */
+2104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = 0U;
+2105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Clear TxISR function pointers */
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxISR = NULL;
+2108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Flush the whole TX FIFO (if needed) */
+2110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+2111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+2113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Restore huart->gState to Ready */
+2116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->gState = HAL_UART_STATE_READY;
+2117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* As no DMA to be aborted, call directly user Abort complete callback */
+2119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call registered Abort Transmit Complete Callback */
+2121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->AbortTransmitCpltCallback(huart);
+2122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call legacy weak Abort Transmit Complete Callback */
+2124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UART_AbortTransmitCpltCallback(huart);
+2125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+2126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+2129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Abort ongoing Receive transfer (Interrupt mode).
+2133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt 
+2135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         This procedure performs following operations :
+2136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Disable UART Interrupts (Rx)
+2137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Disable the DMA transfer in the peripheral register (if enabled)
+2138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+2139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - Set handle State to READY
+2140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *           - At abort completion, call user abort complete callback
+ARM GAS  /tmp/cceWHrnJ.s 			page 39
+
+
+2141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+2142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         considered as completed only when user abort complete callback is executed (not when ex
+2143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+2144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+2146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+2150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+2153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+2155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Abort the UART DMA Rx channel if enabled */
+2158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+2159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable the UART DMA Rx request if enabled */
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+2162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmarx != NULL)
+2165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the UART DMA Abort callback :
+2167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+2168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+2169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Abort DMA RX */
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+2172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+2173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+2174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->hdmarx->XferAbortCallback(huart->hdmarx);
+2175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+2176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+2178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Reset Rx transfer counter */
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxXferCount = 0U;
+2181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Clear RxISR function pointer */
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pRxBuffPtr = NULL;
+2184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Clear the Error flags in the ICR register */
+2186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_F
+2187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Discard the received data */
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+2190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Restore huart->RxState to Ready */
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxState = HAL_UART_STATE_READY;
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+2194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* As no DMA to be aborted, call directly user Abort complete callback */
+2196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Call registered Abort Receive Complete Callback */
+ARM GAS  /tmp/cceWHrnJ.s 			page 40
+
+
+2198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->AbortReceiveCpltCallback(huart);
+2199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Call legacy weak Abort Receive Complete Callback */
+2201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       HAL_UART_AbortReceiveCpltCallback(huart);
+2202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+2203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+2206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Reset Rx transfer counter */
+2208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount = 0U;
+2209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Clear RxISR function pointer */
+2211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pRxBuffPtr = NULL;
+2212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Clear the Error flags in the ICR register */
+2214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF
+2215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Restore huart->RxState to Ready */
+2217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxState = HAL_UART_STATE_READY;
+2218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+2219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* As no DMA to be aborted, call directly user Abort complete callback */
+2221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call registered Abort Receive Complete Callback */
+2223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->AbortReceiveCpltCallback(huart);
+2224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call legacy weak Abort Receive Complete Callback */
+2226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UART_AbortReceiveCpltCallback(huart);
+2227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+2228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Handle UART interrupt request.
+2235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+2236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+2237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+2241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+2242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+2243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t errorflags;
+2245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t errorcode;
+2246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* If no error occurs */
+2248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | 
+2249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (errorflags == 0U)
+2250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* UART in mode Receiver ---------------------------------------------------*/
+2252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+2253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+2254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ARM GAS  /tmp/cceWHrnJ.s 			page 41
+
+
+2255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (huart->RxISR != NULL)
+2257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+2258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxISR(huart);
+2259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+2260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return;
+2261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* If some errors occur */
+2265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if ((errorflags != 0U)
+2266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+2267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+2268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* UART parity error interrupt occurred -------------------------------------*/
+2270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+2271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+2273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->ErrorCode |= HAL_UART_ERROR_PE;
+2275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* UART frame error interrupt occurred --------------------------------------*/
+2278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+2279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+2281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->ErrorCode |= HAL_UART_ERROR_FE;
+2283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* UART noise error interrupt occurred --------------------------------------*/
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+2287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+2289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->ErrorCode |= HAL_UART_ERROR_NE;
+2291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* UART Over-Run interrupt occurred -----------------------------------------*/
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (((isrflags & USART_ISR_ORE) != 0U)
+2295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+2296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+2297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+2299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->ErrorCode |= HAL_UART_ERROR_ORE;
+2301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+2304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+2305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+2307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->ErrorCode |= HAL_UART_ERROR_RTO;
+2309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call UART Error Call back function if need be ----------------------------*/
+ARM GAS  /tmp/cceWHrnJ.s 			page 42
+
+
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+2313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* UART in mode Receiver --------------------------------------------------*/
+2315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+2316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+2317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+2318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+2319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (huart->RxISR != NULL)
+2320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->RxISR(huart);
+2322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+2323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+2324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* If Error is to be considered as blocking :
+2326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           - Receiver Timeout error in Reception
+2327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           - Overrun error in Reception
+2328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           - any error occurs in DMA mode reception
+2329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       */
+2330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       errorcode = huart->ErrorCode;
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+2332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+2333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+2334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Blocking error : transfer is aborted
+2335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            Set the UART state ready to be able to start again the process,
+2336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+2337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         UART_EndRxTransfer(huart);
+2338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Abort the UART DMA Rx channel if enabled */
+2340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+2341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+2342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Disable the UART DMA Rx request if enabled */
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+2344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Abort the UART DMA Rx channel */
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           if (huart->hdmarx != NULL)
+2347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+2348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             /* Set the UART DMA Abort callback :
+2349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+2350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+2351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             /* Abort DMA RX */
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+2354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             {
+2355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****               /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+2356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****               huart->hdmarx->XferAbortCallback(huart->hdmarx);
+2357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             }
+2358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           }
+2359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           else
+2360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+2361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             /* Call user error callback */
+2362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             /*Call registered error callback*/
+2364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             huart->ErrorCallback(huart);
+2365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             /*Call legacy weak error callback*/
+2367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             HAL_UART_ErrorCallback(huart);
+2368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ARM GAS  /tmp/cceWHrnJ.s 			page 43
+
+
+2369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           }
+2371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+2372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         else
+2373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+2374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Call user error callback */
+2375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call registered error callback*/
+2377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCallback(huart);
+2378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call legacy weak error callback*/
+2380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           HAL_UART_ErrorCallback(huart);
+2381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+2382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+2383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+2384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+2385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+2386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Non Blocking error : transfer could go on.
+2387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            Error is notified to user through user error callback */
+2388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call registered error callback*/
+2390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ErrorCallback(huart);
+2391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call legacy weak error callback*/
+2393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         HAL_UART_ErrorCallback(huart);
+2394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ErrorCode = HAL_UART_ERROR_NONE;
+2396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+2397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return;
+2399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   } /* End if some error occurs */
+2401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check current reception Mode :
+2403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      If Reception till IDLE event has been selected : */
+2404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+2405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       && ((isrflags & USART_ISR_IDLE) != 0U)
+2406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       && ((cr1its & USART_ISR_IDLE) != 0U))
+2407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+2409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Check if DMA mode is enabled in UART */
+2411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+2412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* DMA mode enabled */
+2414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Check received length : If all expected data are received, do nothing,
+2415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          (DMA cplt callback will be called).
+2416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          Otherwise, if at least one data has already been received, IDLE event is to be notified to
+2417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((nb_remaining_rx_data > 0U)
+2419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           && (nb_remaining_rx_data < huart->RxXferSize))
+2420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+2421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Reception is not complete */
+2422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxXferCount = nb_remaining_rx_data;
+2423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
+ARM GAS  /tmp/cceWHrnJ.s 			page 44
+
+
+2426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+2427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+2430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+2432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****              in the UART CR3 register */
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+2434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* At end of Rx process, restore huart->RxState to Ready */
+2436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->RxState = HAL_UART_STATE_READY;
+2437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+2438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+2440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Last bytes received, so no need as the abort is immediate */
+2442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           (void)HAL_DMA_Abort(huart->hdmarx);
+2443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+2444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call registered Rx Event callback*/
+2446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+2447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call legacy weak Rx Event callback*/
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+2450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+2451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+2452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return;
+2453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+2455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* DMA mode not enabled */
+2457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Check received length : If all expected data are received, do nothing.
+2458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          Otherwise, if at least one data has already been received, IDLE event is to be notified to
+2459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((huart->RxXferCount > 0U)
+2461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           && (nb_rx_data > 0U))
+2462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+2463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+2465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO T
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+2468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Rx process is completed, restore huart->RxState to Ready */
+2470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxState = HAL_UART_STATE_READY;
+2471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+2472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Clear RxISR function pointer */
+2474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxISR = NULL;
+2475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+2477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call registered Rx complete callback*/
+2479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxEventCallback(huart, nb_rx_data);
+2480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call legacy weak Rx Event callback*/
+2482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+ARM GAS  /tmp/cceWHrnJ.s 			page 45
+
+
+2483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+2484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+2485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return;
+2486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+2490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+2491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+2493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* UART Rx state is not reset as a reception process might be ongoing.
+2495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****        If UART handle state fields need to be reset to READY, this could be done in Wakeup callback
+2496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call registered Wakeup Callback */
+2499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->WakeupCallback(huart);
+2500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call legacy weak Wakeup Callback */
+2502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UARTEx_WakeupCallback(huart);
+2503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+2504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return;
+2505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* UART in mode Transmitter ------------------------------------------------*/
+2508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+2509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+2510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+2511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->TxISR != NULL)
+2513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->TxISR(huart);
+2515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return;
+2517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* UART in mode Transmitter (transmission end) -----------------------------*/
+2520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+2521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_EndTransmit_IT(huart);
+2523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return;
+2524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* UART TX Fifo Empty occurred ----------------------------------------------*/
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+2528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call registered Tx Fifo Empty Callback */
+2531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxFifoEmptyCallback(huart);
+2532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call legacy weak Tx Fifo Empty Callback */
+2534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UARTEx_TxFifoEmptyCallback(huart);
+2535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+2536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return;
+2537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* UART RX Fifo Full occurred ----------------------------------------------*/
+ARM GAS  /tmp/cceWHrnJ.s 			page 46
+
+
+2540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+2541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call registered Rx Fifo Full Callback */
+2544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxFifoFullCallback(huart);
+2545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+2546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Call legacy weak Rx Fifo Full Callback */
+2547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UARTEx_RxFifoFullCallback(huart);
+2548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+2549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return;
+2550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Tx Transfer completed callback.
+2555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+2556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+2557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+2559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+2561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(huart);
+2562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             the HAL_UART_TxCpltCallback can be implemented in the user file.
+2565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****    */
+2566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Tx Half Transfer completed callback.
+2570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+2572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+2574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+2576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(huart);
+2577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* NOTE: This function should not be modified, when the callback is needed,
+2579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+2580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****    */
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Rx Transfer completed callback.
+2585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+2587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+2589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+2591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(huart);
+2592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             the HAL_UART_RxCpltCallback can be implemented in the user file.
+2595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****    */
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ARM GAS  /tmp/cceWHrnJ.s 			page 47
+
+
+2597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Rx Half Transfer completed callback.
+2600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+2602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+2604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+2606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(huart);
+2607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* NOTE: This function should not be modified, when the callback is needed,
+2609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+2610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****    */
+2611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  UART error callback.
+2615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+2617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+2619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+2621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(huart);
+2622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             the HAL_UART_ErrorCallback can be implemented in the user file.
+2625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****    */
+2626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  UART Abort Complete callback.
+2630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+2632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+2634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+2636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(huart);
+2637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             the HAL_UART_AbortCpltCallback can be implemented in the user file.
+2640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****    */
+2641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  UART Abort Complete callback.
+2645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+2647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** __weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+2649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+2651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(huart);
+2652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ARM GAS  /tmp/cceWHrnJ.s 			page 48
+
+
+2654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+2655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****    */
+2656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  UART Abort Receive Complete callback.
+2660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+2662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+2664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+2666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(huart);
+2667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+2670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****    */
+2671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Reception Event Callback (Rx event notification called after use of advanced reception 
+2675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle
+2676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  Size  Number of data available in application reception buffer (indicates a position in
+2677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *               reception buffer until which, data are available)
+2678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+2679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+2681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+2683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(huart);
+2684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(Size);
+2685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+2688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****    */
+2689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @}
+2693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+2696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *  @brief   UART control functions
+2697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *
+2698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** @verbatim
+2699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****  ===============================================================================
+2700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                       ##### Peripheral Control functions #####
+2701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****  ===============================================================================
+2702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     [..]
+2703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     This subsection provides a set of functions allowing to control the UART.
+2704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on th
+2705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
+2706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
+2707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+2708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+2709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+2710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      (+) UART_SetConfig() API configures the UART peripheral
+ARM GAS  /tmp/cceWHrnJ.s 			page 49
+
+
+2711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+2712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+2713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+2714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+2715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      (+) HAL_LIN_SendBreak() API transmits the break characters
+2716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** @endverbatim
+2717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @{
+2718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Update on the fly the receiver timeout value in RTOR register.
+2722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+2723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *                    the configuration information for the specified UART module.
+2724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  TimeoutValue receiver timeout value in number of baud blocks. The timeout
+2725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *                     value must be less or equal to 0x0FFFFFFFF.
+2726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+2727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
+2729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (!(IS_LPUART_INSTANCE(huart->Instance)))
+2731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+2733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+2734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Enable the UART receiver timeout feature.
+2739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+2740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *                    the configuration information for the specified UART module.
+2741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+2742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
+2744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (!(IS_LPUART_INSTANCE(huart->Instance)))
+2746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->gState == HAL_UART_STATE_READY)
+2748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Process Locked */
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_LOCK(huart);
+2751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->gState = HAL_UART_STATE_BUSY;
+2753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set the USART RTOEN bit */
+2755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+2756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->gState = HAL_UART_STATE_READY;
+2758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Process Unlocked */
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UNLOCK(huart);
+2761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return HAL_OK;
+2763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+2765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return HAL_BUSY;
+2767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ARM GAS  /tmp/cceWHrnJ.s 			page 50
+
+
+2768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+2770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+2772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Disable the UART receiver timeout feature.
+2777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+2778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *                    the configuration information for the specified UART module.
+2779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+2780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
+2782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (!(IS_LPUART_INSTANCE(huart->Instance)))
+2784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->gState == HAL_UART_STATE_READY)
+2786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Process Locked */
+2788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_LOCK(huart);
+2789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->gState = HAL_UART_STATE_BUSY;
+2791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Clear the USART RTOEN bit */
+2793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+2794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->gState = HAL_UART_STATE_READY;
+2796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Process Unlocked */
+2798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UNLOCK(huart);
+2799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return HAL_OK;
+2801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+2803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+2804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return HAL_BUSY;
+2805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+2806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+2808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return HAL_ERROR;
+2810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+2811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Enable UART in mute mode (does not mean UART enters mute mode;
+2815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+2816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+2818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+2820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+2822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+2824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 51
+
+
+2825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Enable USART mute mode by setting the MME bit in the CR1 register */
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+2827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_READY;
+2829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return (UART_CheckIdleState(huart));
+2831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
+2835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         as it may not have been in mute mode at this very moment).
+2836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+2838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+2840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+2842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+2844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+2847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_READY;
+2849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return (UART_CheckIdleState(huart));
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Enter UART mute mode (means UART actually enters mute mode).
+2855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+2856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+2857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+2858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+2860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Enable the UART transmitter and disable the UART receiver.
+2866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+2868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+2870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+2872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+2873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Clear TE and RE bits */
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+2876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+2879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_READY;
+2881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 52
+
+
+2882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UNLOCK(huart);
+2883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+2885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Enable the UART receiver and disable the UART transmitter.
+2889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status.
+2891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+2893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+2895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+2896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Clear TE and RE bits */
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+2899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+2902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_READY;
+2904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UNLOCK(huart);
+2906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+2908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Transmit break characters.
+2913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+2914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+2915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+2917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the parameters */
+2919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+2920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+2922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+2924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Send break characters */
+2926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+2927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_READY;
+2929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UNLOCK(huart);
+2931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+2933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @}
+2937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 53
+
+
+2939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+2940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *  @brief   UART Peripheral State functions
+2941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *
+2942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** @verbatim
+2943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ==============================================================================
+2944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             ##### Peripheral State and Error functions #####
+2945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ==============================================================================
+2946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     [..]
+2947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     This subsection provides functions allowing to :
+2948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (+) Return the UART handle state.
+2949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (+) Return the UART handle error code
+2950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** @endverbatim
+2952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @{
+2953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Return the UART handle state.
+2957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+2958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *               the configuration information for the specified UART.
+2959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL state
+2960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+2962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t temp1;
+2964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t temp2;
+2965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   temp1 = huart->gState;
+2966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   temp2 = huart->RxState;
+2967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return (HAL_UART_StateTypeDef)(temp1 | temp2);
+2969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Return the UART handle error code.
+2973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+2974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *               the configuration information for the specified UART.
+2975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval UART Error Code
+2976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+2978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+2979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return huart->ErrorCode;
+2980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+2981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @}
+2983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @}
+2987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /** @defgroup UART_Private_Functions UART Private Functions
+2990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @{
+2991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+2993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+2994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Initialize the callbacks to their default values.
+2995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+ARM GAS  /tmp/cceWHrnJ.s 			page 54
+
+
+2996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval none
+2997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+2998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+2999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+3000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Init the UART Callback settings */
+3002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltC
+3003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallb
+3004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltC
+3005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallb
+3006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallba
+3007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCa
+3008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransm
+3009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiv
+3010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallb
+3011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullC
+3012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmpty
+3013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCall
+3014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Configure the UART peripheral.
+3020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+3021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+3022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+3024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t tmpreg;
+3026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t brrtemp;
+3027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_ClockSourceTypeDef clocksource;
+3028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t usartdiv;
+3029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_StatusTypeDef ret               = HAL_OK;
+3030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t lpuart_ker_ck_pres;
+3031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t pclk;
+3032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the parameters */
+3034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+3035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+3036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (UART_INSTANCE_LOWPOWER(huart))
+3037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
+3039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+3041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+3043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+3044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_PARITY(huart->Init.Parity));
+3047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_MODE(huart->Init.Mode));
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+3049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+3050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
+3051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*-------------------------- USART CR1 Configuration -----------------------*/
+ARM GAS  /tmp/cceWHrnJ.s 			page 55
+
+
+3053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+3054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *  the UART Word Length, Parity, Mode and oversampling:
+3055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *  set the M bits according to huart->Init.WordLength value
+3056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *  set PCE and PS bits according to huart->Init.Parity value
+3057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *  set TE and RE bits according to huart->Init.Mode value
+3058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *  set OVER8 bit according to huart->Init.OverSampling value */
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.O
+3060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+3061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*-------------------------- USART CR2 Configuration -----------------------*/
+3063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+3064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * to huart->Init.StopBits value */
+3065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+3066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*-------------------------- USART CR3 Configuration -----------------------*/
+3068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Configure
+3069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * - UART HardWare Flow Control: set CTSE and RTSE bits according
+3070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *   to huart->Init.HwFlowCtl value
+3071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * - one-bit sampling method versus three samples' majority rule according
+3072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *   to huart->Init.OneBitSampling (not applicable to LPUART) */
+3073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+3074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (!(UART_INSTANCE_LOWPOWER(huart)))
+3076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     tmpreg |= huart->Init.OneBitSampling;
+3078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+3080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*-------------------------- USART PRESC Configuration -----------------------*/
+3082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Configure
+3083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
+3084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+3085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*-------------------------- USART BRR Configuration -----------------------*/
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_GETCLOCKSOURCE(huart, clocksource);
+3088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check LPUART instance */
+3090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (UART_INSTANCE_LOWPOWER(huart))
+3091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Retrieve frequency clock */
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     switch (clocksource)
+3094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_PCLK1:
+3096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = HAL_RCC_GetPCLK1Freq();
+3097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_HSI:
+3099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = (uint32_t) HSI_VALUE;
+3100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_SYSCLK:
+3102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = HAL_RCC_GetSysClockFreq();
+3103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_LSE:
+3105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = (uint32_t) LSE_VALUE;
+3106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       default:
+3108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = 0U;
+3109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ret = HAL_ERROR;
+ARM GAS  /tmp/cceWHrnJ.s 			page 56
+
+
+3110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* If proper clock source reported */
+3114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (pclk != 0U)
+3115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Compute clock after Prescaler */
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
+3118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+3121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+3122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+3123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ret = HAL_ERROR;
+3124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+3125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+3126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+3127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Check computed UsartDiv value is in allocated range
+3128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescale
+3130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+3131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+3132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->Instance->BRR = usartdiv;
+3133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+3134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         else
+3135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+3136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ret = HAL_ERROR;
+3137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+3138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
+3139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                 (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+3140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     } /* if (pclk != 0) */
+3141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check UART Over Sampling to set Baud Rate Register */
+3143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+3144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     switch (clocksource)
+3146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_PCLK1:
+3148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = HAL_RCC_GetPCLK1Freq();
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_PCLK2:
+3151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = HAL_RCC_GetPCLK2Freq();
+3152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_HSI:
+3154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = (uint32_t) HSI_VALUE;
+3155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_SYSCLK:
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = HAL_RCC_GetSysClockFreq();
+3158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_LSE:
+3160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = (uint32_t) LSE_VALUE;
+3161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       default:
+3163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = 0U;
+3164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ret = HAL_ERROR;
+3165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ARM GAS  /tmp/cceWHrnJ.s 			page 57
+
+
+3167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* USARTDIV must be greater than or equal to 0d16 */
+3169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (pclk != 0U)
+3170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescal
+3172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+3173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+3174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+3175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+3176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->Instance->BRR = brrtemp;
+3177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+3178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+3179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+3180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ret = HAL_ERROR;
+3181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+3182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+3185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     switch (clocksource)
+3187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_PCLK1:
+3189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = HAL_RCC_GetPCLK1Freq();
+3190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_PCLK2:
+3192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = HAL_RCC_GetPCLK2Freq();
+3193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_HSI:
+3195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = (uint32_t) HSI_VALUE;
+3196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_SYSCLK:
+3198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = HAL_RCC_GetSysClockFreq();
+3199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_LSE:
+3201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = (uint32_t) LSE_VALUE;
+3202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       default:
+3204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pclk = 0U;
+3205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ret = HAL_ERROR;
+3206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+3207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (pclk != 0U)
+3210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* USARTDIV must be greater than or equal to 0d16 */
+3212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPresca
+3213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+3214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+3215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->Instance->BRR = (uint16_t)usartdiv;
+3216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+3217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+3218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+3219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ret = HAL_ERROR;
+3220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+3221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 58
+
+
+3224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Initialize the number of data to process during RX/TX ISR execution */
+3225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->NbTxDataToProcess = 1;
+3226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->NbRxDataToProcess = 1;
+3227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Clear ISR function pointers */
+3229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxISR = NULL;
+3230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxISR = NULL;
+3231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return ret;
+3233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Configure the UART peripheral advanced features.
+3237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+3238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+3241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check whether the set of advanced features to configure is properly set */
+3243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+3244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* if required, configure TX pin active level inversion */
+3246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+3247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+3250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* if required, configure RX pin active level inversion */
+3253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+3254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+3256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+3257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* if required, configure data inversion */
+3260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+3261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+3263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+3264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* if required, configure RX/TX pins swap */
+3267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+3268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+3270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+3271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* if required, configure RX overrun detection disabling */
+3274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+3275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+3278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* if required, configure DMA disabling on reception error */
+ARM GAS  /tmp/cceWHrnJ.s 			page 59
+
+
+3281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+3282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+3284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+3285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* if required, configure auto Baud rate detection scheme */
+3288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+3289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+3291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+3292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+3293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* set auto Baudrate detection parameters if detection is enabled */
+3294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+3295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+3297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+3298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* if required, configure MSB first on communication line */
+3302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+3303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+3305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+3306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief Check the UART Idle State.
+3311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+3312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+3313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+3315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t tickstart;
+3317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Initialize the UART ErrorCode */
+3319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ErrorCode = HAL_UART_ERROR_NONE;
+3320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Init tickstart for timeout management */
+3322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   tickstart = HAL_GetTick();
+3323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check if the Transmitter is enabled */
+3325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+3326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Wait until TEACK flag is set */
+3328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALU
+3329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Timeout occurred */
+3331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return HAL_TIMEOUT;
+3332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check if the Receiver is enabled */
+3336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+3337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ARM GAS  /tmp/cceWHrnJ.s 			page 60
+
+
+3338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Wait until REACK flag is set */
+3339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALU
+3340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Timeout occurred */
+3342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return HAL_TIMEOUT;
+3343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Initialize the UART State */
+3347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_READY;
+3348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+3349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+3350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UNLOCK(huart);
+3352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+3354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  This function handles UART Communication Timeout. It waits
+3358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *                  until a flag is no longer in the specified status.
+3359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart     UART handle.
+3360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Flag      Specifies the UART flag to check
+3361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Status    The actual Flag status (SET or RESET)
+3362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Tickstart Tick start value
+3363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param Timeout   Timeout duration
+3364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+3365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus 
+3367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                               uint32_t Tickstart, uint32_t Timeout)
+3368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Wait until flag is set */
+3370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+3371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Check for the Timeout */
+3373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (Timeout != HAL_MAX_DELAY)
+3374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+3376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+3377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+3378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            interrupts for the interrupt process */
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+3380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                 USART_CR1_TXEIE_TXFNFIE));
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+3382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->gState = HAL_UART_STATE_READY;
+3384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxState = HAL_UART_STATE_READY;
+3385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         __HAL_UNLOCK(huart);
+3387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         return HAL_TIMEOUT;
+3389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+3390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+3392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+3394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ARM GAS  /tmp/cceWHrnJ.s 			page 61
+
+
+3395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Clear Receiver Timeout flag*/
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+3397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+3399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****              interrupts for the interrupt process */
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+3401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                   USART_CR1_TXEIE_TXFNFIE));
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+3403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->gState = HAL_UART_STATE_READY;
+3405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->RxState = HAL_UART_STATE_READY;
+3406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode = HAL_UART_ERROR_RTO;
+3407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Process Unlocked */
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           __HAL_UNLOCK(huart);
+3410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           return HAL_TIMEOUT;
+3412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+3413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+3414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+3417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Start Receive operation in interrupt mode.
+3421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This function could be called by all HAL UART API providing reception in Interrupt mode
+3422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   When calling this function, parameters validity is considered as already checked,
+3423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         i.e. Rx State, buffer address, ...
+3424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         UART Handle is assumed as Locked.
+3425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+3426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  pData Pointer to data buffer (u8 or u16 data elements).
+3427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  Size  Amount of data elements (u8 or u16) to be received.
+3428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+3429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+3431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->pRxBuffPtr  = pData;
+3433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferSize  = Size;
+3434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = Size;
+3435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxISR       = NULL;
+3436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Computation of UART mask to apply to RDR register */
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_MASK_COMPUTATION(huart);
+3439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ErrorCode = HAL_UART_ERROR_NONE;
+3441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_BUSY_RX;
+3442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+3445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Configure Rx interrupt processing */
+3447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+3448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Set the Rx ISR function pointer according to the data word length */
+3450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+3451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ARM GAS  /tmp/cceWHrnJ.s 			page 62
+
+
+3452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+3453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+3455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+3457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UNLOCK(huart);
+3460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+3462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->Init.Parity != UART_PARITY_NONE)
+3463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+3465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+3467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+3469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Set the Rx ISR function pointer according to the data word length */
+3471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+3472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxISR = UART_RxISR_16BIT;
+3474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+3476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxISR = UART_RxISR_8BIT;
+3478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UNLOCK(huart);
+3481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+3483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->Init.Parity != UART_PARITY_NONE)
+3484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+3486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+3488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+3490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }  
+3491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+3493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Start Receive operation in DMA mode.
+3497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   This function could be called by all HAL UART API providing reception in DMA mode.
+3498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   When calling this function, parameters validity is considered as already checked,
+3499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         i.e. Rx State, buffer address, ...
+3500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         UART Handle is assumed as Locked.
+3501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+3502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  pData Pointer to data buffer (u8 or u16 data elements).
+3503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  Size  Amount of data elements (u8 or u16) to be received.
+3504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval HAL status
+3505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->pRxBuffPtr = pData;
+ARM GAS  /tmp/cceWHrnJ.s 			page 63
+
+
+3509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferSize = Size;
+3510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ErrorCode = HAL_UART_ERROR_NONE;
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_BUSY_RX;
+3513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->hdmarx != NULL)
+3515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Set the UART DMA transfer complete callback */
+3517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+3518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Set the UART DMA Half transfer complete callback */
+3520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+3521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Set the DMA error callback */
+3523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->hdmarx->XferErrorCallback = UART_DMAError;
+3524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Set the DMA abort callback */
+3526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->hdmarx->XferAbortCallback = NULL;
+3527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Enable the DMA channel */
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPt
+3530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Set error code to DMA */
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->ErrorCode = HAL_UART_ERROR_DMA;
+3533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       __HAL_UNLOCK(huart);
+3535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Restore huart->RxState to ready */
+3537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxState = HAL_UART_STATE_READY;
+3538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return HAL_ERROR;
+3540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UNLOCK(huart);
+3543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Enable the UART Parity Error Interrupt */
+3545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->Init.Parity != UART_PARITY_NONE)
+3546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+3548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+3552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+3554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   in the UART CR3 register */
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+3556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return HAL_OK;
+3558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit compl
+3563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+3564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+ARM GAS  /tmp/cceWHrnJ.s 			page 64
+
+
+3566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+3567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+  28              		.loc 1 3567 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  33              	.LVL0:
+  34              	.L2:
+3568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable TXEIE, TCIE, TXFT interrupts */
+3569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  35              		.loc 1 3569 3 discriminator 1 view .LVU1
+  36              	.LBB509:
+  37              		.loc 1 3569 3 discriminator 1 view .LVU2
+  38              		.loc 1 3569 3 discriminator 1 view .LVU3
+  39              		.loc 1 3569 3 discriminator 1 view .LVU4
+  40 0000 0268     		ldr	r2, [r0]
+  41              	.LVL1:
+  42              	.LBB510:
+  43              	.LBI510:
+  44              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.2.0
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     08. May 2019
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+ARM GAS  /tmp/cceWHrnJ.s 			page 65
+
+
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/cceWHrnJ.s 			page 66
+
+
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 67
+
+
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ARM GAS  /tmp/cceWHrnJ.s 			page 68
+
+
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/cceWHrnJ.s 			page 69
+
+
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 70
+
+
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/cceWHrnJ.s 			page 71
+
+
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ARM GAS  /tmp/cceWHrnJ.s 			page 72
+
+
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/cceWHrnJ.s 			page 73
+
+
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ARM GAS  /tmp/cceWHrnJ.s 			page 74
+
+
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ARM GAS  /tmp/cceWHrnJ.s 			page 75
+
+
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ARM GAS  /tmp/cceWHrnJ.s 			page 76
+
+
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ARM GAS  /tmp/cceWHrnJ.s 			page 77
+
+
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ARM GAS  /tmp/cceWHrnJ.s 			page 78
+
+
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/cceWHrnJ.s 			page 79
+
+
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 882:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 883:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 885:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 888:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ARM GAS  /tmp/cceWHrnJ.s 			page 80
+
+
+ 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 900:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 901:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 902:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 904:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 906:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 908:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 913:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 915:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 916:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 918:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 922:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 923:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 925:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 928:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 930:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 931:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 932:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 938:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 940:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 942:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 943:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+ 945:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 946:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 947:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 948:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 81
+
+
+ 949:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 950:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ 952:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 953:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 954:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
+ 956:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 958:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 959:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 960:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 961:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 962:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
+ 963:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
+ 964:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 965:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 966:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 967:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+ 968:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 969:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ 970:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_bswap32(value);
+ 971:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 972:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 974:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 975:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 976:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 977:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 978:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 979:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 980:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 982:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 984:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 985:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 986:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+ 987:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 989:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 990:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 991:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 992:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 993:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 994:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 995:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 996:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 997:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
+ 998:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 999:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+1000:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1001:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+1002:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1003:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1004:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
+1005:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ARM GAS  /tmp/cceWHrnJ.s 			page 82
+
+
+1006:Drivers/CMSIS/Include/cmsis_gcc.h ****   int16_t result;
+1007:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1008:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+1009:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+1010:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1011:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1014:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1015:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
+1016:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
+1017:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
+1018:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
+1019:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Rotated value
+1020:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1021:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+1022:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1023:Drivers/CMSIS/Include/cmsis_gcc.h ****   op2 %= 32U;
+1024:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (op2 == 0U)
+1025:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1026:Drivers/CMSIS/Include/cmsis_gcc.h ****     return op1;
+1027:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1028:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
+1029:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1030:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1031:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1032:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1033:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Breakpoint
+1034:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
+1035:Drivers/CMSIS/Include/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
+1036:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
+1037:Drivers/CMSIS/Include/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
+1038:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1039:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+1040:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1041:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1042:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1043:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse bit order of value
+1044:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
+1045:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+1046:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+1047:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+1049:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1050:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+1051:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+1053:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+1054:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+1055:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+1056:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1057:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+1058:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1059:Drivers/CMSIS/Include/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
+1060:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
+1061:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1062:Drivers/CMSIS/Include/cmsis_gcc.h ****     result <<= 1U;
+ARM GAS  /tmp/cceWHrnJ.s 			page 83
+
+
+1063:Drivers/CMSIS/Include/cmsis_gcc.h ****     result |= value & 1U;
+1064:Drivers/CMSIS/Include/cmsis_gcc.h ****     s--;
+1065:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1066:Drivers/CMSIS/Include/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
+1067:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1068:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+1069:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1072:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1073:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Count leading zeros
+1074:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
+1075:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
+1076:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             number of leading zeros in value
+1077:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+1079:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1080:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+1081:Drivers/CMSIS/Include/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
+1082:Drivers/CMSIS/Include/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
+1083:Drivers/CMSIS/Include/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
+1084:Drivers/CMSIS/Include/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
+1085:Drivers/CMSIS/Include/cmsis_gcc.h ****      is non-zero".
+1086:Drivers/CMSIS/Include/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+1087:Drivers/CMSIS/Include/cmsis_gcc.h ****      single CLZ instruction.
+1088:Drivers/CMSIS/Include/cmsis_gcc.h ****    */
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (value == 0U)
+1090:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****     return 32U;
+1092:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1093:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_clz(value);
+1094:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1095:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1096:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1097:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+1098:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+1099:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+1100:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+1101:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1102:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (8 bit)
+1103:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 8 bit value.
+1104:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
+1105:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
+1106:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1107:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+1108:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1109:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
+1110:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1111:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1112:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+1113:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1114:Drivers/CMSIS/Include/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+1115:Drivers/CMSIS/Include/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
+1116:Drivers/CMSIS/Include/cmsis_gcc.h ****     */
+1117:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+1118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1119:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
+ARM GAS  /tmp/cceWHrnJ.s 			page 84
+
+
+1120:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1122:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1123:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1124:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (16 bit)
+1125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 16 bit values.
+1126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
+1127:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
+1128:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+1130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1131:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
+1132:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1133:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1134:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+1135:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1136:Drivers/CMSIS/Include/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+1137:Drivers/CMSIS/Include/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
+1138:Drivers/CMSIS/Include/cmsis_gcc.h ****     */
+1139:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+1140:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1141:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
+1142:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1143:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1144:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1145:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1146:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (32 bit)
+1147:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 32 bit values.
+1148:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
+1149:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
+1150:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+  45              		.loc 2 1151 31 discriminator 1 view .LVU5
+  46              	.LBB511:
+1152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1153:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
+  47              		.loc 2 1153 5 discriminator 1 view .LVU6
+1154:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+  48              		.loc 2 1155 4 discriminator 1 view .LVU7
+  49              		.syntax unified
+  50              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+  51 0002 52E8003F 		ldrex r3, [r2]
+  52              	@ 0 "" 2
+  53              	.LVL2:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+  54              		.loc 2 1156 4 discriminator 1 view .LVU8
+  55              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU9
+  56              		.thumb
+  57              		.syntax unified
+  58              	.LBE511:
+  59              	.LBE510:
+  60              		.loc 1 3569 3 discriminator 1 view .LVU10
+  61 0006 23F0C003 		bic	r3, r3, #192
+  62              	.LVL3:
+  63              		.loc 1 3569 3 is_stmt 1 discriminator 1 view .LVU11
+  64              	.LBB512:
+ARM GAS  /tmp/cceWHrnJ.s 			page 85
+
+
+  65              	.LBI512:
+1157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1158:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1159:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1160:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1161:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (8 bit)
+1162:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 8 bit values.
+1163:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
+1164:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
+1165:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
+1166:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
+1167:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1168:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+1169:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1170:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
+1171:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1172:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+1173:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+1174:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1175:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1177:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1178:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (16 bit)
+1179:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 16 bit values.
+1180:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
+1181:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
+1182:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
+1183:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
+1184:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1185:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+1186:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1187:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
+1188:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1189:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+1190:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+1191:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1192:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1193:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1194:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1195:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (32 bit)
+1196:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 32 bit values.
+1197:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
+1198:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
+1199:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
+1200:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
+1201:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+  66              		.loc 2 1202 31 discriminator 1 view .LVU12
+  67              	.LBB513:
+1203:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1204:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
+  68              		.loc 2 1204 4 discriminator 1 view .LVU13
+1205:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+  69              		.loc 2 1206 4 discriminator 1 view .LVU14
+  70              		.syntax unified
+  71              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ARM GAS  /tmp/cceWHrnJ.s 			page 86
+
+
+  72 000a 42E80031 		strex r1, r3, [r2]
+  73              	@ 0 "" 2
+  74              	.LVL4:
+1207:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+  75              		.loc 2 1207 4 discriminator 1 view .LVU15
+  76              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU16
+  77              		.thumb
+  78              		.syntax unified
+  79              	.LBE513:
+  80              	.LBE512:
+  81              		.loc 1 3569 3 discriminator 1 view .LVU17
+  82 000e 0029     		cmp	r1, #0
+  83 0010 F6D1     		bne	.L2
+  84              	.LVL5:
+  85              	.L3:
+  86              		.loc 1 3569 3 discriminator 1 view .LVU18
+  87              	.LBE509:
+  88              		.loc 1 3569 3 is_stmt 1 discriminator 1 view .LVU19
+3570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+  89              		.loc 1 3570 3 discriminator 1 view .LVU20
+  90              	.LBB514:
+  91              		.loc 1 3570 3 discriminator 1 view .LVU21
+  92              		.loc 1 3570 3 discriminator 1 view .LVU22
+  93              		.loc 1 3570 3 discriminator 1 view .LVU23
+  94 0012 0268     		ldr	r2, [r0]
+  95              	.LVL6:
+  96              	.LBB515:
+  97              	.LBI515:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+  98              		.loc 2 1151 31 discriminator 1 view .LVU24
+  99              	.LBB516:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 100              		.loc 2 1153 5 discriminator 1 view .LVU25
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 101              		.loc 2 1155 4 discriminator 1 view .LVU26
+ 102 0014 02F10803 		add	r3, r2, #8
+ 103              	.LVL7:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 104              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU27
+ 105              		.syntax unified
+ 106              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 107 0018 53E8003F 		ldrex r3, [r3]
+ 108              	@ 0 "" 2
+ 109              	.LVL8:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 110              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU28
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 111              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU29
+ 112              		.thumb
+ 113              		.syntax unified
+ 114              	.LBE516:
+ 115              	.LBE515:
+ 116              		.loc 1 3570 3 discriminator 1 view .LVU30
+ 117 001c 23F40003 		bic	r3, r3, #8388608
+ 118              	.LVL9:
+ 119              		.loc 1 3570 3 is_stmt 1 discriminator 1 view .LVU31
+ 120              	.LBB517:
+ARM GAS  /tmp/cceWHrnJ.s 			page 87
+
+
+ 121              	.LBI517:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 122              		.loc 2 1202 31 discriminator 1 view .LVU32
+ 123              	.LBB518:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124              		.loc 2 1204 4 discriminator 1 view .LVU33
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 125              		.loc 2 1206 4 discriminator 1 view .LVU34
+ 126 0020 0832     		adds	r2, r2, #8
+ 127              	.LVL10:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 128              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU35
+ 129              		.syntax unified
+ 130              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 131 0022 42E80031 		strex r1, r3, [r2]
+ 132              	@ 0 "" 2
+ 133              	.LVL11:
+ 134              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU36
+ 135              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU37
+ 136              		.thumb
+ 137              		.syntax unified
+ 138              	.LBE518:
+ 139              	.LBE517:
+ 140              		.loc 1 3570 3 discriminator 1 view .LVU38
+ 141 0026 0029     		cmp	r1, #0
+ 142 0028 F3D1     		bne	.L3
+ 143              	.LBE514:
+ 144              		.loc 1 3570 3 is_stmt 1 discriminator 2 view .LVU39
+3571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* At end of Tx process, restore huart->gState to Ready */
+3573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_READY;
+ 145              		.loc 1 3573 3 discriminator 2 view .LVU40
+ 146              		.loc 1 3573 17 is_stmt 0 discriminator 2 view .LVU41
+ 147 002a 2023     		movs	r3, #32
+ 148              	.LVL12:
+ 149              		.loc 1 3573 17 discriminator 2 view .LVU42
+ 150 002c C0F88430 		str	r3, [r0, #132]
+3574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 151              		.loc 1 3574 1 discriminator 2 view .LVU43
+ 152 0030 7047     		bx	lr
+ 153              		.cfi_endproc
+ 154              	.LFE378:
+ 156              		.section	.text.UART_EndRxTransfer,"ax",%progbits
+ 157              		.align	1
+ 158              		.syntax unified
+ 159              		.thumb
+ 160              		.thumb_func
+ 162              	UART_EndRxTransfer:
+ 163              	.LFB379:
+3575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception comp
+3579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart UART handle.
+3580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+ARM GAS  /tmp/cceWHrnJ.s 			page 88
+
+
+3583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 164              		.loc 1 3583 1 is_stmt 1 view -0
+ 165              		.cfi_startproc
+ 166              		@ args = 0, pretend = 0, frame = 0
+ 167              		@ frame_needed = 0, uses_anonymous_args = 0
+ 168              		@ link register save eliminated.
+ 169              	.LVL13:
+ 170              	.L5:
+3584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+3585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ 171              		.loc 1 3585 3 discriminator 1 view .LVU45
+ 172              	.LBB519:
+ 173              		.loc 1 3585 3 discriminator 1 view .LVU46
+ 174              		.loc 1 3585 3 discriminator 1 view .LVU47
+ 175              		.loc 1 3585 3 discriminator 1 view .LVU48
+ 176 0000 0268     		ldr	r2, [r0]
+ 177              	.LVL14:
+ 178              	.LBB520:
+ 179              	.LBI520:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 180              		.loc 2 1151 31 discriminator 1 view .LVU49
+ 181              	.LBB521:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 182              		.loc 2 1153 5 discriminator 1 view .LVU50
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 183              		.loc 2 1155 4 discriminator 1 view .LVU51
+ 184              		.syntax unified
+ 185              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 186 0002 52E8003F 		ldrex r3, [r2]
+ 187              	@ 0 "" 2
+ 188              	.LVL15:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 189              		.loc 2 1156 4 discriminator 1 view .LVU52
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 190              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU53
+ 191              		.thumb
+ 192              		.syntax unified
+ 193              	.LBE521:
+ 194              	.LBE520:
+ 195              		.loc 1 3585 3 discriminator 1 view .LVU54
+ 196 0006 23F49073 		bic	r3, r3, #288
+ 197              	.LVL16:
+ 198              		.loc 1 3585 3 is_stmt 1 discriminator 1 view .LVU55
+ 199              	.LBB522:
+ 200              	.LBI522:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 201              		.loc 2 1202 31 discriminator 1 view .LVU56
+ 202              	.LBB523:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 203              		.loc 2 1204 4 discriminator 1 view .LVU57
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 204              		.loc 2 1206 4 discriminator 1 view .LVU58
+ 205              		.syntax unified
+ 206              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 207 000a 42E80031 		strex r1, r3, [r2]
+ 208              	@ 0 "" 2
+ 209              	.LVL17:
+ARM GAS  /tmp/cceWHrnJ.s 			page 89
+
+
+ 210              		.loc 2 1207 4 discriminator 1 view .LVU59
+ 211              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU60
+ 212              		.thumb
+ 213              		.syntax unified
+ 214              	.LBE523:
+ 215              	.LBE522:
+ 216              		.loc 1 3585 3 discriminator 1 view .LVU61
+ 217 000e 0029     		cmp	r1, #0
+ 218 0010 F6D1     		bne	.L5
+ 219              	.LVL18:
+ 220              	.L6:
+ 221              		.loc 1 3585 3 discriminator 1 view .LVU62
+ 222              	.LBE519:
+ 223              		.loc 1 3585 3 is_stmt 1 discriminator 1 view .LVU63
+3586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 224              		.loc 1 3586 3 discriminator 1 view .LVU64
+ 225              	.LBB524:
+ 226              		.loc 1 3586 3 discriminator 1 view .LVU65
+ 227              		.loc 1 3586 3 discriminator 1 view .LVU66
+ 228              		.loc 1 3586 3 discriminator 1 view .LVU67
+ 229 0012 0268     		ldr	r2, [r0]
+ 230              	.LVL19:
+ 231              	.LBB525:
+ 232              	.LBI525:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 233              		.loc 2 1151 31 discriminator 1 view .LVU68
+ 234              	.LBB526:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 235              		.loc 2 1153 5 discriminator 1 view .LVU69
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 236              		.loc 2 1155 4 discriminator 1 view .LVU70
+ 237 0014 02F10803 		add	r3, r2, #8
+ 238              	.LVL20:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 239              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU71
+ 240              		.syntax unified
+ 241              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 242 0018 53E8003F 		ldrex r3, [r3]
+ 243              	@ 0 "" 2
+ 244              	.LVL21:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 245              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU72
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 246              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU73
+ 247              		.thumb
+ 248              		.syntax unified
+ 249              	.LBE526:
+ 250              	.LBE525:
+ 251              		.loc 1 3586 3 discriminator 1 view .LVU74
+ 252 001c 23F08053 		bic	r3, r3, #268435456
+ 253 0020 23F00103 		bic	r3, r3, #1
+ 254              	.LVL22:
+ 255              		.loc 1 3586 3 is_stmt 1 discriminator 1 view .LVU75
+ 256              	.LBB527:
+ 257              	.LBI527:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 258              		.loc 2 1202 31 discriminator 1 view .LVU76
+ARM GAS  /tmp/cceWHrnJ.s 			page 90
+
+
+ 259              	.LBB528:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 260              		.loc 2 1204 4 discriminator 1 view .LVU77
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 261              		.loc 2 1206 4 discriminator 1 view .LVU78
+ 262 0024 0832     		adds	r2, r2, #8
+ 263              	.LVL23:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 264              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU79
+ 265              		.syntax unified
+ 266              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 267 0026 42E80031 		strex r1, r3, [r2]
+ 268              	@ 0 "" 2
+ 269              	.LVL24:
+ 270              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU80
+ 271              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU81
+ 272              		.thumb
+ 273              		.syntax unified
+ 274              	.LBE528:
+ 275              	.LBE527:
+ 276              		.loc 1 3586 3 discriminator 1 view .LVU82
+ 277 002a 0029     		cmp	r1, #0
+ 278 002c F1D1     		bne	.L6
+ 279              	.LBE524:
+ 280              		.loc 1 3586 3 is_stmt 1 discriminator 2 view .LVU83
+3587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+3589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 281              		.loc 1 3589 3 discriminator 2 view .LVU84
+ 282              		.loc 1 3589 12 is_stmt 0 discriminator 2 view .LVU85
+ 283 002e C36E     		ldr	r3, [r0, #108]
+ 284              	.LVL25:
+ 285              		.loc 1 3589 6 discriminator 2 view .LVU86
+ 286 0030 012B     		cmp	r3, #1
+ 287 0032 06D0     		beq	.L8
+ 288              	.L7:
+3590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 289              		.loc 1 3591 5 is_stmt 1 discriminator 2 view .LVU87
+3592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* At end of Rx process, restore huart->RxState to Ready */
+3595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 290              		.loc 1 3595 3 discriminator 2 view .LVU88
+ 291              		.loc 1 3595 18 is_stmt 0 discriminator 2 view .LVU89
+ 292 0034 2023     		movs	r3, #32
+ 293 0036 C0F88830 		str	r3, [r0, #136]
+3596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 294              		.loc 1 3596 3 is_stmt 1 discriminator 2 view .LVU90
+ 295              		.loc 1 3596 24 is_stmt 0 discriminator 2 view .LVU91
+ 296 003a 0023     		movs	r3, #0
+ 297 003c C366     		str	r3, [r0, #108]
+3597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Reset RxIsr function pointer */
+3599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxISR = NULL;
+ 298              		.loc 1 3599 3 is_stmt 1 discriminator 2 view .LVU92
+ 299              		.loc 1 3599 16 is_stmt 0 discriminator 2 view .LVU93
+ARM GAS  /tmp/cceWHrnJ.s 			page 91
+
+
+ 300 003e 0367     		str	r3, [r0, #112]
+3600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 301              		.loc 1 3600 1 discriminator 2 view .LVU94
+ 302 0040 7047     		bx	lr
+ 303              	.L8:
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 304              		.loc 1 3591 5 is_stmt 1 discriminator 1 view .LVU95
+ 305              	.LBB529:
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 306              		.loc 1 3591 5 discriminator 1 view .LVU96
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 307              		.loc 1 3591 5 discriminator 1 view .LVU97
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 308              		.loc 1 3591 5 discriminator 1 view .LVU98
+ 309 0042 0268     		ldr	r2, [r0]
+ 310              	.LVL26:
+ 311              	.LBB530:
+ 312              	.LBI530:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 313              		.loc 2 1151 31 discriminator 1 view .LVU99
+ 314              	.LBB531:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 315              		.loc 2 1153 5 discriminator 1 view .LVU100
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 316              		.loc 2 1155 4 discriminator 1 view .LVU101
+ 317              		.syntax unified
+ 318              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 319 0044 52E8003F 		ldrex r3, [r2]
+ 320              	@ 0 "" 2
+ 321              	.LVL27:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 322              		.loc 2 1156 4 discriminator 1 view .LVU102
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 323              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU103
+ 324              		.thumb
+ 325              		.syntax unified
+ 326              	.LBE531:
+ 327              	.LBE530:
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 328              		.loc 1 3591 5 discriminator 1 view .LVU104
+ 329 0048 23F01003 		bic	r3, r3, #16
+ 330              	.LVL28:
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 331              		.loc 1 3591 5 is_stmt 1 discriminator 1 view .LVU105
+ 332              	.LBB532:
+ 333              	.LBI532:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 334              		.loc 2 1202 31 discriminator 1 view .LVU106
+ 335              	.LBB533:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 336              		.loc 2 1204 4 discriminator 1 view .LVU107
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 337              		.loc 2 1206 4 discriminator 1 view .LVU108
+ 338              		.syntax unified
+ 339              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 340 004c 42E80031 		strex r1, r3, [r2]
+ 341              	@ 0 "" 2
+ARM GAS  /tmp/cceWHrnJ.s 			page 92
+
+
+ 342              	.LVL29:
+ 343              		.loc 2 1207 4 discriminator 1 view .LVU109
+ 344              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU110
+ 345              		.thumb
+ 346              		.syntax unified
+ 347              	.LBE533:
+ 348              	.LBE532:
+3591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 349              		.loc 1 3591 5 discriminator 1 view .LVU111
+ 350 0050 0029     		cmp	r1, #0
+ 351 0052 F6D1     		bne	.L8
+ 352 0054 EEE7     		b	.L7
+ 353              	.LBE529:
+ 354              		.cfi_endproc
+ 355              	.LFE379:
+ 357              		.section	.text.UART_TxISR_8BIT,"ax",%progbits
+ 358              		.align	1
+ 359              		.syntax unified
+ 360              		.thumb
+ 361              		.thumb_func
+ 363              	UART_TxISR_8BIT:
+ 364              	.LVL30:
+ 365              	.LFB390:
+3601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief DMA UART transmit process complete callback.
+3605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param hdma DMA handle.
+3606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+3609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+3611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* DMA Normal mode */
+3613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+3614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = 0U;
+3616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+3618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****        in the UART CR3 register */
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+3620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Enable the UART Transmit Complete Interrupt */
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+3623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* DMA Circular mode */
+3625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+3626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+3628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /*Call registered Tx complete callback*/
+3629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxCpltCallback(huart);
+3630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+3631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /*Call legacy weak Tx complete callback*/
+3632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UART_TxCpltCallback(huart);
+3633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ARM GAS  /tmp/cceWHrnJ.s 			page 93
+
+
+3635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief DMA UART transmit process half complete callback.
+3639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param hdma DMA handle.
+3640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+3643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+3645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+3647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*Call registered Tx Half complete callback*/
+3648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxHalfCpltCallback(huart);
+3649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+3650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*Call legacy weak Tx Half complete callback*/
+3651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_UART_TxHalfCpltCallback(huart);
+3652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief DMA UART receive process complete callback.
+3657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param hdma DMA handle.
+3658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+3661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+3663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* DMA Normal mode */
+3665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+3666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount = 0U;
+3668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+3672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+3674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****        in the UART CR3 register */
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+3676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* At end of Rx process, restore huart->RxState to Ready */
+3678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxState = HAL_UART_STATE_READY;
+3679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+3682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+3684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check current reception Mode :
+3688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      If Reception till IDLE event has been selected : use Rx Event callback */
+3689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+3690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ARM GAS  /tmp/cceWHrnJ.s 			page 94
+
+
+3692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /*Call registered Rx Event callback*/
+3693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxEventCallback(huart, huart->RxXferSize);
+3694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+3695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /*Call legacy weak Rx Event callback*/
+3696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+3697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+3700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* In other cases : use Rx Complete callback */
+3702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+3703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /*Call registered Rx complete callback*/
+3704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxCpltCallback(huart);
+3705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+3706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /*Call legacy weak Rx complete callback*/
+3707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UART_RxCpltCallback(huart);
+3708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief DMA UART receive process half complete callback.
+3714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param hdma DMA handle.
+3715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+3718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+3720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check current reception Mode :
+3722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****      If Reception till IDLE event has been selected : use Rx Event callback */
+3723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+3724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+3726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /*Call registered Rx Event callback*/
+3727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxEventCallback(huart, huart->RxXferSize / 2U);
+3728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+3729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /*Call legacy weak Rx Event callback*/
+3730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
+3731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+3734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* In other cases : use Rx Half Complete callback */
+3736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+3737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /*Call registered Rx Half complete callback*/
+3738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxHalfCpltCallback(huart);
+3739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+3740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /*Call legacy weak Rx Half complete callback*/
+3741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     HAL_UART_RxHalfCpltCallback(huart);
+3742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief DMA UART communication error callback.
+3748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param hdma DMA handle.
+ARM GAS  /tmp/cceWHrnJ.s 			page 95
+
+
+3749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMAError(DMA_HandleTypeDef *hdma)
+3752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+3754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef gstate = huart->gState;
+3756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef rxstate = huart->RxState;
+3757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Stop UART DMA Tx request if ongoing */
+3759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+3760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+3761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = 0U;
+3763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_EndTxTransfer(huart);
+3764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Stop UART DMA Rx request if ongoing */
+3767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+3768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+3769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount = 0U;
+3771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_EndRxTransfer(huart);
+3772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ErrorCode |= HAL_UART_ERROR_DMA;
+3775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+3777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*Call registered error callback*/
+3778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ErrorCallback(huart);
+3779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+3780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*Call legacy weak error callback*/
+3781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_UART_ErrorCallback(huart);
+3782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
+3787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         (To be called at end of DMA Abort procedure following error occurrence).
+3788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  hdma DMA handle.
+3789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+3792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+3794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+3795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxXferCount = 0U;
+3796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+3798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*Call registered error callback*/
+3799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ErrorCallback(huart);
+3800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+3801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*Call legacy weak error callback*/
+3802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_UART_ErrorCallback(huart);
+3803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 96
+
+
+3806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  DMA UART Tx communication abort callback, when initiated by user
+3808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         (To be called at end of DMA Tx Abort procedure following user abort request).
+3809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   When this callback is executed, User Abort complete call back is called only if no
+3810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         Abort still ongoing for Rx DMA Handle.
+3811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  hdma DMA handle.
+3812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+3815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+3817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->hdmatx->XferAbortCallback = NULL;
+3819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check if an Abort process is still ongoing */
+3821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->hdmarx != NULL)
+3822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmarx->XferAbortCallback != NULL)
+3824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return;
+3826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callba
+3830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxXferCount = 0U;
+3831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+3832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Reset errorCode */
+3834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ErrorCode = HAL_UART_ERROR_NONE;
+3835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Clear the Error flags in the ICR register */
+3837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+3838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Flush the whole TX FIFO (if needed) */
+3840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+3841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+3843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Restore huart->gState and huart->RxState to Ready */
+3846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState  = HAL_UART_STATE_READY;
+3847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+3848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+3849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Call user Abort complete callback */
+3851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+3852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Call registered Abort complete callback */
+3853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->AbortCpltCallback(huart);
+3854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+3855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Call legacy weak Abort complete callback */
+3856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_UART_AbortCpltCallback(huart);
+3857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  DMA UART Rx communication abort callback, when initiated by user
+ARM GAS  /tmp/cceWHrnJ.s 			page 97
+
+
+3863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         (To be called at end of DMA Rx Abort procedure following user abort request).
+3864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   When this callback is executed, User Abort complete call back is called only if no
+3865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         Abort still ongoing for Tx DMA Handle.
+3866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  hdma DMA handle.
+3867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+3870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+3872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->hdmarx->XferAbortCallback = NULL;
+3874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check if an Abort process is still ongoing */
+3876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->hdmatx != NULL)
+3877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->hdmatx->XferAbortCallback != NULL)
+3879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       return;
+3881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+3882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callba
+3885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxXferCount = 0U;
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+3887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Reset errorCode */
+3889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ErrorCode = HAL_UART_ERROR_NONE;
+3890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Clear the Error flags in the ICR register */
+3892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+3893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Discard the received data */
+3895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+3896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Restore huart->gState and huart->RxState to Ready */
+3898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState  = HAL_UART_STATE_READY;
+3899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+3900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+3901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Call user Abort complete callback */
+3903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+3904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Call registered Abort complete callback */
+3905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->AbortCpltCallback(huart);
+3906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+3907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Call legacy weak Abort complete callback */
+3908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_UART_AbortCpltCallback(huart);
+3909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
+3915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+3916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         (This callback is executed at end of DMA Tx Abort procedure following user abort reques
+3917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         and leads to user Tx Abort Complete callback execution).
+3918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  hdma DMA handle.
+3919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+ARM GAS  /tmp/cceWHrnJ.s 			page 98
+
+
+3920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+3922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+3924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxXferCount = 0U;
+3926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Flush the whole TX FIFO (if needed) */
+3928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+3929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+3931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+3932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Restore huart->gState to Ready */
+3934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_READY;
+3935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Call user Abort complete callback */
+3937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+3938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Call registered Abort Transmit Complete Callback */
+3939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->AbortTransmitCpltCallback(huart);
+3940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+3941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Call legacy weak Abort Transmit Complete Callback */
+3942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_UART_AbortTransmitCpltCallback(huart);
+3943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
+3948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+3949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         (This callback is executed at end of DMA Rx Abort procedure following user abort reques
+3950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         and leads to user Rx Abort Complete callback execution).
+3951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  hdma DMA handle.
+3952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+3955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+3956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+3957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+3959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Clear the Error flags in the ICR register */
+3961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+3962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Discard the received data */
+3964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+3965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Restore huart->RxState to Ready */
+3967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+3968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+3969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Call user Abort complete callback */
+3971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+3972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Call registered Abort Receive Complete Callback */
+3973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->AbortReceiveCpltCallback(huart);
+3974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+3975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Call legacy weak Abort Receive Complete Callback */
+3976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_UART_AbortReceiveCpltCallback(huart);
+ARM GAS  /tmp/cceWHrnJ.s 			page 99
+
+
+3977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+3978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+3979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+3981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief TX interrupt handler for 7 or 8 bits data word length .
+3982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   Function is called under interruption only, once
+3983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         interruptions have been enabled by HAL_UART_Transmit_IT().
+3984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+3985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+3986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+3987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
+3988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 366              		.loc 1 3988 1 is_stmt 1 view -0
+ 367              		.cfi_startproc
+ 368              		@ args = 0, pretend = 0, frame = 0
+ 369              		@ frame_needed = 0, uses_anonymous_args = 0
+ 370              		@ link register save eliminated.
+3989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Tx process is ongoing */
+3990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ 371              		.loc 1 3990 3 view .LVU113
+ 372              		.loc 1 3990 12 is_stmt 0 view .LVU114
+ 373 0000 D0F88430 		ldr	r3, [r0, #132]
+ 374              		.loc 1 3990 6 view .LVU115
+ 375 0004 212B     		cmp	r3, #33
+ 376 0006 00D0     		beq	.L14
+ 377              	.L9:
+3991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+3992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->TxXferCount == 0U)
+3993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+3994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Disable the UART Transmit Data Register Empty Interrupt */
+3995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+3996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+3997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Enable the UART Transmit Complete Interrupt */
+3998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+3999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+4000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+4001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+4002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+4003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pTxBuffPtr++;
+4004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->TxXferCount--;
+4005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+4006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+4007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 378              		.loc 1 4007 1 view .LVU116
+ 379 0008 7047     		bx	lr
+ 380              	.L14:
+3992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 381              		.loc 1 3992 5 is_stmt 1 view .LVU117
+3992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 382              		.loc 1 3992 14 is_stmt 0 view .LVU118
+ 383 000a B0F85630 		ldrh	r3, [r0, #86]
+ 384 000e 9BB2     		uxth	r3, r3
+3992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 385              		.loc 1 3992 8 view .LVU119
+ 386 0010 93B9     		cbnz	r3, .L11
+ 387              	.L12:
+3995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 100
+
+
+ 388              		.loc 1 3995 7 is_stmt 1 discriminator 1 view .LVU120
+ 389              	.LBB534:
+3995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 390              		.loc 1 3995 7 discriminator 1 view .LVU121
+3995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 391              		.loc 1 3995 7 discriminator 1 view .LVU122
+3995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 392              		.loc 1 3995 7 discriminator 1 view .LVU123
+ 393 0012 0268     		ldr	r2, [r0]
+ 394              	.LVL31:
+ 395              	.LBB535:
+ 396              	.LBI535:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 397              		.loc 2 1151 31 discriminator 1 view .LVU124
+ 398              	.LBB536:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 399              		.loc 2 1153 5 discriminator 1 view .LVU125
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 400              		.loc 2 1155 4 discriminator 1 view .LVU126
+ 401              		.syntax unified
+ 402              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 403 0014 52E8003F 		ldrex r3, [r2]
+ 404              	@ 0 "" 2
+ 405              	.LVL32:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 406              		.loc 2 1156 4 discriminator 1 view .LVU127
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 407              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU128
+ 408              		.thumb
+ 409              		.syntax unified
+ 410              	.LBE536:
+ 411              	.LBE535:
+3995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 412              		.loc 1 3995 7 discriminator 1 view .LVU129
+ 413 0018 23F08003 		bic	r3, r3, #128
+ 414              	.LVL33:
+3995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 415              		.loc 1 3995 7 is_stmt 1 discriminator 1 view .LVU130
+ 416              	.LBB537:
+ 417              	.LBI537:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 418              		.loc 2 1202 31 discriminator 1 view .LVU131
+ 419              	.LBB538:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 420              		.loc 2 1204 4 discriminator 1 view .LVU132
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 421              		.loc 2 1206 4 discriminator 1 view .LVU133
+ 422              		.syntax unified
+ 423              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 424 001c 42E80031 		strex r1, r3, [r2]
+ 425              	@ 0 "" 2
+ 426              	.LVL34:
+ 427              		.loc 2 1207 4 discriminator 1 view .LVU134
+ 428              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU135
+ 429              		.thumb
+ 430              		.syntax unified
+ 431              	.LBE538:
+ARM GAS  /tmp/cceWHrnJ.s 			page 101
+
+
+ 432              	.LBE537:
+3995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 433              		.loc 1 3995 7 discriminator 1 view .LVU136
+ 434 0020 0029     		cmp	r1, #0
+ 435 0022 F6D1     		bne	.L12
+ 436              	.LVL35:
+ 437              	.L13:
+3995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 438              		.loc 1 3995 7 discriminator 1 view .LVU137
+ 439              	.LBE534:
+3995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 440              		.loc 1 3995 7 is_stmt 1 discriminator 1 view .LVU138
+3998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 441              		.loc 1 3998 7 discriminator 1 view .LVU139
+ 442              	.LBB539:
+3998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 443              		.loc 1 3998 7 discriminator 1 view .LVU140
+3998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 444              		.loc 1 3998 7 discriminator 1 view .LVU141
+3998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 445              		.loc 1 3998 7 discriminator 1 view .LVU142
+ 446 0024 0268     		ldr	r2, [r0]
+ 447              	.LVL36:
+ 448              	.LBB540:
+ 449              	.LBI540:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 450              		.loc 2 1151 31 discriminator 1 view .LVU143
+ 451              	.LBB541:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 452              		.loc 2 1153 5 discriminator 1 view .LVU144
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 453              		.loc 2 1155 4 discriminator 1 view .LVU145
+ 454              		.syntax unified
+ 455              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 456 0026 52E8003F 		ldrex r3, [r2]
+ 457              	@ 0 "" 2
+ 458              	.LVL37:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 459              		.loc 2 1156 4 discriminator 1 view .LVU146
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 460              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU147
+ 461              		.thumb
+ 462              		.syntax unified
+ 463              	.LBE541:
+ 464              	.LBE540:
+3998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 465              		.loc 1 3998 7 discriminator 1 view .LVU148
+ 466 002a 43F04003 		orr	r3, r3, #64
+ 467              	.LVL38:
+3998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 468              		.loc 1 3998 7 is_stmt 1 discriminator 1 view .LVU149
+ 469              	.LBB542:
+ 470              	.LBI542:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 471              		.loc 2 1202 31 discriminator 1 view .LVU150
+ 472              	.LBB543:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 102
+
+
+ 473              		.loc 2 1204 4 discriminator 1 view .LVU151
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 474              		.loc 2 1206 4 discriminator 1 view .LVU152
+ 475              		.syntax unified
+ 476              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 477 002e 42E80031 		strex r1, r3, [r2]
+ 478              	@ 0 "" 2
+ 479              	.LVL39:
+ 480              		.loc 2 1207 4 discriminator 1 view .LVU153
+ 481              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU154
+ 482              		.thumb
+ 483              		.syntax unified
+ 484              	.LBE543:
+ 485              	.LBE542:
+3998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 486              		.loc 1 3998 7 discriminator 1 view .LVU155
+ 487 0032 0029     		cmp	r1, #0
+ 488 0034 F6D1     		bne	.L13
+ 489 0036 7047     		bx	lr
+ 490              	.LVL40:
+ 491              	.L11:
+3998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 492              		.loc 1 3998 7 discriminator 1 view .LVU156
+ 493              	.LBE539:
+4002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pTxBuffPtr++;
+ 494              		.loc 1 4002 7 is_stmt 1 view .LVU157
+4002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pTxBuffPtr++;
+ 495              		.loc 1 4002 46 is_stmt 0 view .LVU158
+ 496 0038 036D     		ldr	r3, [r0, #80]
+4002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pTxBuffPtr++;
+ 497              		.loc 1 4002 40 view .LVU159
+ 498 003a 1A78     		ldrb	r2, [r3]	@ zero_extendqisi2
+4002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pTxBuffPtr++;
+ 499              		.loc 1 4002 12 view .LVU160
+ 500 003c 0368     		ldr	r3, [r0]
+4002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pTxBuffPtr++;
+ 501              		.loc 1 4002 28 view .LVU161
+ 502 003e 9A62     		str	r2, [r3, #40]
+4003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->TxXferCount--;
+ 503              		.loc 1 4003 7 is_stmt 1 view .LVU162
+4003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->TxXferCount--;
+ 504              		.loc 1 4003 12 is_stmt 0 view .LVU163
+ 505 0040 036D     		ldr	r3, [r0, #80]
+4003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->TxXferCount--;
+ 506              		.loc 1 4003 24 view .LVU164
+ 507 0042 0133     		adds	r3, r3, #1
+ 508 0044 0365     		str	r3, [r0, #80]
+4004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 509              		.loc 1 4004 7 is_stmt 1 view .LVU165
+4004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 510              		.loc 1 4004 12 is_stmt 0 view .LVU166
+ 511 0046 B0F85630 		ldrh	r3, [r0, #86]
+ 512 004a 9BB2     		uxth	r3, r3
+4004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 513              		.loc 1 4004 25 view .LVU167
+ 514 004c 013B     		subs	r3, r3, #1
+ 515 004e 9BB2     		uxth	r3, r3
+ARM GAS  /tmp/cceWHrnJ.s 			page 103
+
+
+ 516 0050 A0F85630 		strh	r3, [r0, #86]	@ movhi
+ 517              		.loc 1 4007 1 view .LVU168
+ 518 0054 D8E7     		b	.L9
+ 519              		.cfi_endproc
+ 520              	.LFE390:
+ 522              		.section	.text.UART_TxISR_16BIT,"ax",%progbits
+ 523              		.align	1
+ 524              		.syntax unified
+ 525              		.thumb
+ 526              		.thumb_func
+ 528              	UART_TxISR_16BIT:
+ 529              	.LVL41:
+ 530              	.LFB391:
+4008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+4010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief TX interrupt handler for 9 bits data word length.
+4011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   Function is called under interruption only, once
+4012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         interruptions have been enabled by HAL_UART_Transmit_IT().
+4013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+4014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+4015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+4016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
+4017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 531              		.loc 1 4017 1 is_stmt 1 view -0
+ 532              		.cfi_startproc
+ 533              		@ args = 0, pretend = 0, frame = 0
+ 534              		@ frame_needed = 0, uses_anonymous_args = 0
+ 535              		@ link register save eliminated.
+4018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const uint16_t *tmp;
+ 536              		.loc 1 4018 3 view .LVU170
+4019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Tx process is ongoing */
+4021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ 537              		.loc 1 4021 3 view .LVU171
+ 538              		.loc 1 4021 12 is_stmt 0 view .LVU172
+ 539 0000 D0F88430 		ldr	r3, [r0, #132]
+ 540              		.loc 1 4021 6 view .LVU173
+ 541 0004 212B     		cmp	r3, #33
+ 542 0006 00D0     		beq	.L20
+ 543              	.L15:
+4022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+4023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->TxXferCount == 0U)
+4024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+4025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Disable the UART Transmit Data Register Empty Interrupt */
+4026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+4027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Enable the UART Transmit Complete Interrupt */
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+4030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+4031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     else
+4032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+4033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       tmp = (const uint16_t *) huart->pTxBuffPtr;
+4034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+4035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pTxBuffPtr += 2U;
+4036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->TxXferCount--;
+4037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+4038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ARM GAS  /tmp/cceWHrnJ.s 			page 104
+
+
+4039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 544              		.loc 1 4039 1 view .LVU174
+ 545 0008 7047     		bx	lr
+ 546              	.L20:
+4023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 547              		.loc 1 4023 5 is_stmt 1 view .LVU175
+4023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 548              		.loc 1 4023 14 is_stmt 0 view .LVU176
+ 549 000a B0F85630 		ldrh	r3, [r0, #86]
+ 550 000e 9BB2     		uxth	r3, r3
+4023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 551              		.loc 1 4023 8 view .LVU177
+ 552 0010 93B9     		cbnz	r3, .L17
+ 553              	.L18:
+4026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 554              		.loc 1 4026 7 is_stmt 1 discriminator 1 view .LVU178
+ 555              	.LBB544:
+4026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 556              		.loc 1 4026 7 discriminator 1 view .LVU179
+4026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 557              		.loc 1 4026 7 discriminator 1 view .LVU180
+4026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 558              		.loc 1 4026 7 discriminator 1 view .LVU181
+ 559 0012 0268     		ldr	r2, [r0]
+ 560              	.LVL42:
+ 561              	.LBB545:
+ 562              	.LBI545:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 563              		.loc 2 1151 31 discriminator 1 view .LVU182
+ 564              	.LBB546:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 565              		.loc 2 1153 5 discriminator 1 view .LVU183
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 566              		.loc 2 1155 4 discriminator 1 view .LVU184
+ 567              		.syntax unified
+ 568              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 569 0014 52E8003F 		ldrex r3, [r2]
+ 570              	@ 0 "" 2
+ 571              	.LVL43:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 572              		.loc 2 1156 4 discriminator 1 view .LVU185
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 573              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU186
+ 574              		.thumb
+ 575              		.syntax unified
+ 576              	.LBE546:
+ 577              	.LBE545:
+4026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 578              		.loc 1 4026 7 discriminator 1 view .LVU187
+ 579 0018 23F08003 		bic	r3, r3, #128
+ 580              	.LVL44:
+4026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 581              		.loc 1 4026 7 is_stmt 1 discriminator 1 view .LVU188
+ 582              	.LBB547:
+ 583              	.LBI547:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 584              		.loc 2 1202 31 discriminator 1 view .LVU189
+ARM GAS  /tmp/cceWHrnJ.s 			page 105
+
+
+ 585              	.LBB548:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 586              		.loc 2 1204 4 discriminator 1 view .LVU190
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 587              		.loc 2 1206 4 discriminator 1 view .LVU191
+ 588              		.syntax unified
+ 589              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 590 001c 42E80031 		strex r1, r3, [r2]
+ 591              	@ 0 "" 2
+ 592              	.LVL45:
+ 593              		.loc 2 1207 4 discriminator 1 view .LVU192
+ 594              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU193
+ 595              		.thumb
+ 596              		.syntax unified
+ 597              	.LBE548:
+ 598              	.LBE547:
+4026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 599              		.loc 1 4026 7 discriminator 1 view .LVU194
+ 600 0020 0029     		cmp	r1, #0
+ 601 0022 F6D1     		bne	.L18
+ 602              	.LVL46:
+ 603              	.L19:
+4026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 604              		.loc 1 4026 7 discriminator 1 view .LVU195
+ 605              	.LBE544:
+4026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 606              		.loc 1 4026 7 is_stmt 1 discriminator 1 view .LVU196
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 607              		.loc 1 4029 7 discriminator 1 view .LVU197
+ 608              	.LBB549:
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 609              		.loc 1 4029 7 discriminator 1 view .LVU198
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 610              		.loc 1 4029 7 discriminator 1 view .LVU199
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 611              		.loc 1 4029 7 discriminator 1 view .LVU200
+ 612 0024 0268     		ldr	r2, [r0]
+ 613              	.LVL47:
+ 614              	.LBB550:
+ 615              	.LBI550:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 616              		.loc 2 1151 31 discriminator 1 view .LVU201
+ 617              	.LBB551:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 618              		.loc 2 1153 5 discriminator 1 view .LVU202
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 619              		.loc 2 1155 4 discriminator 1 view .LVU203
+ 620              		.syntax unified
+ 621              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 622 0026 52E8003F 		ldrex r3, [r2]
+ 623              	@ 0 "" 2
+ 624              	.LVL48:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 625              		.loc 2 1156 4 discriminator 1 view .LVU204
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 626              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU205
+ 627              		.thumb
+ARM GAS  /tmp/cceWHrnJ.s 			page 106
+
+
+ 628              		.syntax unified
+ 629              	.LBE551:
+ 630              	.LBE550:
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 631              		.loc 1 4029 7 discriminator 1 view .LVU206
+ 632 002a 43F04003 		orr	r3, r3, #64
+ 633              	.LVL49:
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 634              		.loc 1 4029 7 is_stmt 1 discriminator 1 view .LVU207
+ 635              	.LBB552:
+ 636              	.LBI552:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 637              		.loc 2 1202 31 discriminator 1 view .LVU208
+ 638              	.LBB553:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 639              		.loc 2 1204 4 discriminator 1 view .LVU209
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 640              		.loc 2 1206 4 discriminator 1 view .LVU210
+ 641              		.syntax unified
+ 642              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 643 002e 42E80031 		strex r1, r3, [r2]
+ 644              	@ 0 "" 2
+ 645              	.LVL50:
+ 646              		.loc 2 1207 4 discriminator 1 view .LVU211
+ 647              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU212
+ 648              		.thumb
+ 649              		.syntax unified
+ 650              	.LBE553:
+ 651              	.LBE552:
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 652              		.loc 1 4029 7 discriminator 1 view .LVU213
+ 653 0032 0029     		cmp	r1, #0
+ 654 0034 F6D1     		bne	.L19
+ 655 0036 7047     		bx	lr
+ 656              	.LVL51:
+ 657              	.L17:
+4029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 658              		.loc 1 4029 7 discriminator 1 view .LVU214
+ 659              	.LBE549:
+4033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ 660              		.loc 1 4033 7 is_stmt 1 view .LVU215
+4033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ 661              		.loc 1 4033 11 is_stmt 0 view .LVU216
+ 662 0038 036D     		ldr	r3, [r0, #80]
+ 663              	.LVL52:
+4034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pTxBuffPtr += 2U;
+ 664              		.loc 1 4034 7 is_stmt 1 view .LVU217
+4034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pTxBuffPtr += 2U;
+ 665              		.loc 1 4034 43 is_stmt 0 view .LVU218
+ 666 003a 1B88     		ldrh	r3, [r3]
+ 667              	.LVL53:
+4034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pTxBuffPtr += 2U;
+ 668              		.loc 1 4034 12 view .LVU219
+ 669 003c 0268     		ldr	r2, [r0]
+4034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pTxBuffPtr += 2U;
+ 670              		.loc 1 4034 50 view .LVU220
+ 671 003e C3F30803 		ubfx	r3, r3, #0, #9
+ARM GAS  /tmp/cceWHrnJ.s 			page 107
+
+
+4034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pTxBuffPtr += 2U;
+ 672              		.loc 1 4034 28 view .LVU221
+ 673 0042 9362     		str	r3, [r2, #40]
+ 674              	.LVL54:
+4035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->TxXferCount--;
+ 675              		.loc 1 4035 7 is_stmt 1 view .LVU222
+4035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->TxXferCount--;
+ 676              		.loc 1 4035 12 is_stmt 0 view .LVU223
+ 677 0044 036D     		ldr	r3, [r0, #80]
+4035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->TxXferCount--;
+ 678              		.loc 1 4035 25 view .LVU224
+ 679 0046 0233     		adds	r3, r3, #2
+ 680 0048 0365     		str	r3, [r0, #80]
+4036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 681              		.loc 1 4036 7 is_stmt 1 view .LVU225
+4036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 682              		.loc 1 4036 12 is_stmt 0 view .LVU226
+ 683 004a B0F85630 		ldrh	r3, [r0, #86]
+ 684 004e 9BB2     		uxth	r3, r3
+4036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 685              		.loc 1 4036 25 view .LVU227
+ 686 0050 013B     		subs	r3, r3, #1
+ 687 0052 9BB2     		uxth	r3, r3
+ 688 0054 A0F85630 		strh	r3, [r0, #86]	@ movhi
+ 689              		.loc 1 4039 1 view .LVU228
+ 690 0058 D6E7     		b	.L15
+ 691              		.cfi_endproc
+ 692              	.LFE391:
+ 694              		.section	.text.UART_TxISR_8BIT_FIFOEN,"ax",%progbits
+ 695              		.align	1
+ 696              		.syntax unified
+ 697              		.thumb
+ 698              		.thumb_func
+ 700              	UART_TxISR_8BIT_FIFOEN:
+ 701              	.LVL55:
+ 702              	.LFB392:
+4040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+4042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+4043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   Function is called under interruption only, once
+4044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         interruptions have been enabled by HAL_UART_Transmit_IT().
+4045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+4046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+4047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+4048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+4049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 703              		.loc 1 4049 1 is_stmt 1 view -0
+ 704              		.cfi_startproc
+ 705              		@ args = 0, pretend = 0, frame = 0
+ 706              		@ frame_needed = 0, uses_anonymous_args = 0
+ 707              		@ link register save eliminated.
+4050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t  nb_tx_data;
+ 708              		.loc 1 4050 3 view .LVU230
+4051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Tx process is ongoing */
+4053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ 709              		.loc 1 4053 3 view .LVU231
+ARM GAS  /tmp/cceWHrnJ.s 			page 108
+
+
+ 710              		.loc 1 4053 12 is_stmt 0 view .LVU232
+ 711 0000 D0F88430 		ldr	r3, [r0, #132]
+ 712              		.loc 1 4053 6 view .LVU233
+ 713 0004 212B     		cmp	r3, #33
+ 714 0006 00D0     		beq	.L29
+ 715              	.L21:
+4054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+4055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+4056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+4057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (huart->TxXferCount == 0U)
+4058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Disable the TX FIFO threshold interrupt */
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+4061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Enable the UART Transmit Complete Interrupt */
+4063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+4064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break; /* force exit loop */
+4066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+4068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+4070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->pTxBuffPtr++;
+4071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxXferCount--;
+4072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+4074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Nothing to do */
+4076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+4078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+4079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 716              		.loc 1 4079 1 view .LVU234
+ 717 0008 7047     		bx	lr
+ 718              	.L29:
+4055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 719              		.loc 1 4055 5 is_stmt 1 view .LVU235
+4055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 720              		.loc 1 4055 21 is_stmt 0 view .LVU236
+ 721 000a B0F86A30 		ldrh	r3, [r0, #106]
+ 722              	.LVL56:
+4055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 723              		.loc 1 4055 5 view .LVU237
+ 724 000e 17E0     		b	.L23
+ 725              	.LVL57:
+ 726              	.L25:
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 727              		.loc 1 4060 9 is_stmt 1 discriminator 1 view .LVU238
+ 728              	.LBB554:
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 729              		.loc 1 4060 9 discriminator 1 view .LVU239
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 730              		.loc 1 4060 9 discriminator 1 view .LVU240
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 731              		.loc 1 4060 9 discriminator 1 view .LVU241
+ 732 0010 0268     		ldr	r2, [r0]
+ 733              	.LVL58:
+ARM GAS  /tmp/cceWHrnJ.s 			page 109
+
+
+ 734              	.LBB555:
+ 735              	.LBI555:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 736              		.loc 2 1151 31 discriminator 1 view .LVU242
+ 737              	.LBB556:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 738              		.loc 2 1153 5 discriminator 1 view .LVU243
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 739              		.loc 2 1155 4 discriminator 1 view .LVU244
+ 740 0012 02F10803 		add	r3, r2, #8
+ 741              	.LVL59:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 742              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU245
+ 743              		.syntax unified
+ 744              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 745 0016 53E8003F 		ldrex r3, [r3]
+ 746              	@ 0 "" 2
+ 747              	.LVL60:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 748              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU246
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 749              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU247
+ 750              		.thumb
+ 751              		.syntax unified
+ 752              	.LBE556:
+ 753              	.LBE555:
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 754              		.loc 1 4060 9 discriminator 1 view .LVU248
+ 755 001a 23F40003 		bic	r3, r3, #8388608
+ 756              	.LVL61:
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 757              		.loc 1 4060 9 is_stmt 1 discriminator 1 view .LVU249
+ 758              	.LBB557:
+ 759              	.LBI557:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 760              		.loc 2 1202 31 discriminator 1 view .LVU250
+ 761              	.LBB558:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 762              		.loc 2 1204 4 discriminator 1 view .LVU251
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 763              		.loc 2 1206 4 discriminator 1 view .LVU252
+ 764 001e 0832     		adds	r2, r2, #8
+ 765              	.LVL62:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 766              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU253
+ 767              		.syntax unified
+ 768              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 769 0020 42E80031 		strex r1, r3, [r2]
+ 770              	@ 0 "" 2
+ 771              	.LVL63:
+ 772              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU254
+ 773              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU255
+ 774              		.thumb
+ 775              		.syntax unified
+ 776              	.LBE558:
+ 777              	.LBE557:
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 110
+
+
+ 778              		.loc 1 4060 9 discriminator 1 view .LVU256
+ 779 0024 0029     		cmp	r1, #0
+ 780 0026 F3D1     		bne	.L25
+ 781              	.LVL64:
+ 782              	.L26:
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 783              		.loc 1 4060 9 discriminator 1 view .LVU257
+ 784              	.LBE554:
+4060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 785              		.loc 1 4060 9 is_stmt 1 discriminator 1 view .LVU258
+4063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 786              		.loc 1 4063 9 discriminator 1 view .LVU259
+ 787              	.LBB559:
+4063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 788              		.loc 1 4063 9 discriminator 1 view .LVU260
+4063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 789              		.loc 1 4063 9 discriminator 1 view .LVU261
+4063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 790              		.loc 1 4063 9 discriminator 1 view .LVU262
+ 791 0028 0268     		ldr	r2, [r0]
+ 792              	.LVL65:
+ 793              	.LBB560:
+ 794              	.LBI560:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 795              		.loc 2 1151 31 discriminator 1 view .LVU263
+ 796              	.LBB561:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 797              		.loc 2 1153 5 discriminator 1 view .LVU264
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 798              		.loc 2 1155 4 discriminator 1 view .LVU265
+ 799              		.syntax unified
+ 800              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 801 002a 52E8003F 		ldrex r3, [r2]
+ 802              	@ 0 "" 2
+ 803              	.LVL66:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 804              		.loc 2 1156 4 discriminator 1 view .LVU266
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 805              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU267
+ 806              		.thumb
+ 807              		.syntax unified
+ 808              	.LBE561:
+ 809              	.LBE560:
+4063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 810              		.loc 1 4063 9 discriminator 1 view .LVU268
+ 811 002e 43F04003 		orr	r3, r3, #64
+ 812              	.LVL67:
+4063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 813              		.loc 1 4063 9 is_stmt 1 discriminator 1 view .LVU269
+ 814              	.LBB562:
+ 815              	.LBI562:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 816              		.loc 2 1202 31 discriminator 1 view .LVU270
+ 817              	.LBB563:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 818              		.loc 2 1204 4 discriminator 1 view .LVU271
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ARM GAS  /tmp/cceWHrnJ.s 			page 111
+
+
+ 819              		.loc 2 1206 4 discriminator 1 view .LVU272
+ 820              		.syntax unified
+ 821              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 822 0032 42E80031 		strex r1, r3, [r2]
+ 823              	@ 0 "" 2
+ 824              	.LVL68:
+ 825              		.loc 2 1207 4 discriminator 1 view .LVU273
+ 826              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU274
+ 827              		.thumb
+ 828              		.syntax unified
+ 829              	.LBE563:
+ 830              	.LBE562:
+4063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 831              		.loc 1 4063 9 discriminator 1 view .LVU275
+ 832 0036 0029     		cmp	r1, #0
+ 833 0038 F6D1     		bne	.L26
+ 834 003a 7047     		bx	lr
+ 835              	.LVL69:
+ 836              	.L27:
+4063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 837              		.loc 1 4063 9 discriminator 1 view .LVU276
+ 838              	.LBE559:
+4076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 839              		.loc 1 4076 7 is_stmt 1 discriminator 2 view .LVU277
+4055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 840              		.loc 1 4055 78 discriminator 2 view .LVU278
+ 841 003c 013B     		subs	r3, r3, #1
+ 842              	.LVL70:
+4055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 843              		.loc 1 4055 78 is_stmt 0 discriminator 2 view .LVU279
+ 844 003e 9BB2     		uxth	r3, r3
+ 845              	.LVL71:
+ 846              	.L23:
+4055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 847              		.loc 1 4055 61 is_stmt 1 discriminator 1 view .LVU280
+ 848 0040 002B     		cmp	r3, #0
+ 849 0042 E1D0     		beq	.L21
+4057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 850              		.loc 1 4057 7 view .LVU281
+4057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 851              		.loc 1 4057 16 is_stmt 0 view .LVU282
+ 852 0044 B0F85620 		ldrh	r2, [r0, #86]
+ 853 0048 92B2     		uxth	r2, r2
+4057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 854              		.loc 1 4057 10 view .LVU283
+ 855 004a 002A     		cmp	r2, #0
+ 856 004c E0D0     		beq	.L25
+4067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 857              		.loc 1 4067 12 is_stmt 1 view .LVU284
+4067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 858              		.loc 1 4067 16 is_stmt 0 view .LVU285
+ 859 004e 0268     		ldr	r2, [r0]
+ 860 0050 D169     		ldr	r1, [r2, #28]
+4067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 861              		.loc 1 4067 15 view .LVU286
+ 862 0052 11F0800F 		tst	r1, #128
+ 863 0056 F1D0     		beq	.L27
+ARM GAS  /tmp/cceWHrnJ.s 			page 112
+
+
+4069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->pTxBuffPtr++;
+ 864              		.loc 1 4069 9 is_stmt 1 view .LVU287
+4069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->pTxBuffPtr++;
+ 865              		.loc 1 4069 48 is_stmt 0 view .LVU288
+ 866 0058 016D     		ldr	r1, [r0, #80]
+4069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->pTxBuffPtr++;
+ 867              		.loc 1 4069 42 view .LVU289
+ 868 005a 0978     		ldrb	r1, [r1]	@ zero_extendqisi2
+4069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->pTxBuffPtr++;
+ 869              		.loc 1 4069 30 view .LVU290
+ 870 005c 9162     		str	r1, [r2, #40]
+4070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxXferCount--;
+ 871              		.loc 1 4070 9 is_stmt 1 view .LVU291
+4070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxXferCount--;
+ 872              		.loc 1 4070 14 is_stmt 0 view .LVU292
+ 873 005e 026D     		ldr	r2, [r0, #80]
+4070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxXferCount--;
+ 874              		.loc 1 4070 26 view .LVU293
+ 875 0060 0132     		adds	r2, r2, #1
+ 876 0062 0265     		str	r2, [r0, #80]
+4071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 877              		.loc 1 4071 9 is_stmt 1 view .LVU294
+4071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 878              		.loc 1 4071 14 is_stmt 0 view .LVU295
+ 879 0064 B0F85620 		ldrh	r2, [r0, #86]
+ 880 0068 92B2     		uxth	r2, r2
+4071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 881              		.loc 1 4071 27 view .LVU296
+ 882 006a 013A     		subs	r2, r2, #1
+ 883 006c 92B2     		uxth	r2, r2
+ 884 006e A0F85620 		strh	r2, [r0, #86]	@ movhi
+ 885 0072 E3E7     		b	.L27
+ 886              		.cfi_endproc
+ 887              	.LFE392:
+ 889              		.section	.text.UART_TxISR_16BIT_FIFOEN,"ax",%progbits
+ 890              		.align	1
+ 891              		.syntax unified
+ 892              		.thumb
+ 893              		.thumb_func
+ 895              	UART_TxISR_16BIT_FIFOEN:
+ 896              	.LVL72:
+ 897              	.LFB393:
+4080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+4082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+4083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   Function is called under interruption only, once
+4084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         interruptions have been enabled by HAL_UART_Transmit_IT().
+4085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+4086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+4087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+4088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+4089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 898              		.loc 1 4089 1 is_stmt 1 view -0
+ 899              		.cfi_startproc
+ 900              		@ args = 0, pretend = 0, frame = 0
+ 901              		@ frame_needed = 0, uses_anonymous_args = 0
+ 902              		@ link register save eliminated.
+ARM GAS  /tmp/cceWHrnJ.s 			page 113
+
+
+4090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const uint16_t *tmp;
+ 903              		.loc 1 4090 3 view .LVU298
+4091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t  nb_tx_data;
+ 904              		.loc 1 4091 3 view .LVU299
+4092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Tx process is ongoing */
+4094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ 905              		.loc 1 4094 3 view .LVU300
+ 906              		.loc 1 4094 12 is_stmt 0 view .LVU301
+ 907 0000 D0F88430 		ldr	r3, [r0, #132]
+ 908              		.loc 1 4094 6 view .LVU302
+ 909 0004 212B     		cmp	r3, #33
+ 910 0006 00D0     		beq	.L38
+ 911              	.L30:
+4095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+4096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+4097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+4098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (huart->TxXferCount == 0U)
+4099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Disable the TX FIFO threshold interrupt */
+4101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+4102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Enable the UART Transmit Complete Interrupt */
+4104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+4105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break; /* force exit loop */
+4107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+4109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         tmp = (const uint16_t *) huart->pTxBuffPtr;
+4111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+4112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->pTxBuffPtr += 2U;
+4113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxXferCount--;
+4114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+4116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Nothing to do */
+4118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+4120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+4121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 912              		.loc 1 4121 1 view .LVU303
+ 913 0008 7047     		bx	lr
+ 914              	.L38:
+4096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 915              		.loc 1 4096 5 is_stmt 1 view .LVU304
+4096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 916              		.loc 1 4096 21 is_stmt 0 view .LVU305
+ 917 000a B0F86A30 		ldrh	r3, [r0, #106]
+ 918              	.LVL73:
+4096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 919              		.loc 1 4096 5 view .LVU306
+ 920 000e 17E0     		b	.L32
+ 921              	.LVL74:
+ 922              	.L34:
+4101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 923              		.loc 1 4101 9 is_stmt 1 discriminator 1 view .LVU307
+ARM GAS  /tmp/cceWHrnJ.s 			page 114
+
+
+ 924              	.LBB564:
+4101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 925              		.loc 1 4101 9 discriminator 1 view .LVU308
+4101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 926              		.loc 1 4101 9 discriminator 1 view .LVU309
+4101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 927              		.loc 1 4101 9 discriminator 1 view .LVU310
+ 928 0010 0268     		ldr	r2, [r0]
+ 929              	.LVL75:
+ 930              	.LBB565:
+ 931              	.LBI565:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 932              		.loc 2 1151 31 discriminator 1 view .LVU311
+ 933              	.LBB566:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 934              		.loc 2 1153 5 discriminator 1 view .LVU312
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 935              		.loc 2 1155 4 discriminator 1 view .LVU313
+ 936 0012 02F10803 		add	r3, r2, #8
+ 937              	.LVL76:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 938              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU314
+ 939              		.syntax unified
+ 940              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 941 0016 53E8003F 		ldrex r3, [r3]
+ 942              	@ 0 "" 2
+ 943              	.LVL77:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 944              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU315
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 945              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU316
+ 946              		.thumb
+ 947              		.syntax unified
+ 948              	.LBE566:
+ 949              	.LBE565:
+4101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 950              		.loc 1 4101 9 discriminator 1 view .LVU317
+ 951 001a 23F40003 		bic	r3, r3, #8388608
+ 952              	.LVL78:
+4101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 953              		.loc 1 4101 9 is_stmt 1 discriminator 1 view .LVU318
+ 954              	.LBB567:
+ 955              	.LBI567:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 956              		.loc 2 1202 31 discriminator 1 view .LVU319
+ 957              	.LBB568:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 958              		.loc 2 1204 4 discriminator 1 view .LVU320
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 959              		.loc 2 1206 4 discriminator 1 view .LVU321
+ 960 001e 0832     		adds	r2, r2, #8
+ 961              	.LVL79:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 962              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU322
+ 963              		.syntax unified
+ 964              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 965 0020 42E80031 		strex r1, r3, [r2]
+ARM GAS  /tmp/cceWHrnJ.s 			page 115
+
+
+ 966              	@ 0 "" 2
+ 967              	.LVL80:
+ 968              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU323
+ 969              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU324
+ 970              		.thumb
+ 971              		.syntax unified
+ 972              	.LBE568:
+ 973              	.LBE567:
+4101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 974              		.loc 1 4101 9 discriminator 1 view .LVU325
+ 975 0024 0029     		cmp	r1, #0
+ 976 0026 F3D1     		bne	.L34
+ 977              	.LVL81:
+ 978              	.L35:
+4101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 979              		.loc 1 4101 9 discriminator 1 view .LVU326
+ 980              	.LBE564:
+4101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 981              		.loc 1 4101 9 is_stmt 1 discriminator 1 view .LVU327
+4104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 982              		.loc 1 4104 9 discriminator 1 view .LVU328
+ 983              	.LBB569:
+4104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 984              		.loc 1 4104 9 discriminator 1 view .LVU329
+4104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 985              		.loc 1 4104 9 discriminator 1 view .LVU330
+4104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 986              		.loc 1 4104 9 discriminator 1 view .LVU331
+ 987 0028 0268     		ldr	r2, [r0]
+ 988              	.LVL82:
+ 989              	.LBB570:
+ 990              	.LBI570:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 991              		.loc 2 1151 31 discriminator 1 view .LVU332
+ 992              	.LBB571:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 993              		.loc 2 1153 5 discriminator 1 view .LVU333
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 994              		.loc 2 1155 4 discriminator 1 view .LVU334
+ 995              		.syntax unified
+ 996              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 997 002a 52E8003F 		ldrex r3, [r2]
+ 998              	@ 0 "" 2
+ 999              	.LVL83:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1000              		.loc 2 1156 4 discriminator 1 view .LVU335
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1001              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU336
+ 1002              		.thumb
+ 1003              		.syntax unified
+ 1004              	.LBE571:
+ 1005              	.LBE570:
+4104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1006              		.loc 1 4104 9 discriminator 1 view .LVU337
+ 1007 002e 43F04003 		orr	r3, r3, #64
+ 1008              	.LVL84:
+4104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 116
+
+
+ 1009              		.loc 1 4104 9 is_stmt 1 discriminator 1 view .LVU338
+ 1010              	.LBB572:
+ 1011              	.LBI572:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1012              		.loc 2 1202 31 discriminator 1 view .LVU339
+ 1013              	.LBB573:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1014              		.loc 2 1204 4 discriminator 1 view .LVU340
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1015              		.loc 2 1206 4 discriminator 1 view .LVU341
+ 1016              		.syntax unified
+ 1017              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1018 0032 42E80031 		strex r1, r3, [r2]
+ 1019              	@ 0 "" 2
+ 1020              	.LVL85:
+ 1021              		.loc 2 1207 4 discriminator 1 view .LVU342
+ 1022              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU343
+ 1023              		.thumb
+ 1024              		.syntax unified
+ 1025              	.LBE573:
+ 1026              	.LBE572:
+4104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1027              		.loc 1 4104 9 discriminator 1 view .LVU344
+ 1028 0036 0029     		cmp	r1, #0
+ 1029 0038 F6D1     		bne	.L35
+ 1030 003a 7047     		bx	lr
+ 1031              	.LVL86:
+ 1032              	.L36:
+4104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1033              		.loc 1 4104 9 discriminator 1 view .LVU345
+ 1034              	.LBE569:
+4118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1035              		.loc 1 4118 7 is_stmt 1 discriminator 2 view .LVU346
+4096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1036              		.loc 1 4096 78 discriminator 2 view .LVU347
+ 1037 003c 013B     		subs	r3, r3, #1
+ 1038              	.LVL87:
+4096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1039              		.loc 1 4096 78 is_stmt 0 discriminator 2 view .LVU348
+ 1040 003e 9BB2     		uxth	r3, r3
+ 1041              	.LVL88:
+ 1042              	.L32:
+4096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1043              		.loc 1 4096 61 is_stmt 1 discriminator 1 view .LVU349
+ 1044 0040 002B     		cmp	r3, #0
+ 1045 0042 E1D0     		beq	.L30
+4098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1046              		.loc 1 4098 7 view .LVU350
+4098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1047              		.loc 1 4098 16 is_stmt 0 view .LVU351
+ 1048 0044 B0F85620 		ldrh	r2, [r0, #86]
+ 1049 0048 92B2     		uxth	r2, r2
+4098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1050              		.loc 1 4098 10 view .LVU352
+ 1051 004a 002A     		cmp	r2, #0
+ 1052 004c E0D0     		beq	.L34
+4108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ARM GAS  /tmp/cceWHrnJ.s 			page 117
+
+
+ 1053              		.loc 1 4108 12 is_stmt 1 view .LVU353
+4108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1054              		.loc 1 4108 16 is_stmt 0 view .LVU354
+ 1055 004e 0268     		ldr	r2, [r0]
+ 1056 0050 D169     		ldr	r1, [r2, #28]
+4108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1057              		.loc 1 4108 15 view .LVU355
+ 1058 0052 11F0800F 		tst	r1, #128
+ 1059 0056 F1D0     		beq	.L36
+4110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ 1060              		.loc 1 4110 9 is_stmt 1 view .LVU356
+4110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ 1061              		.loc 1 4110 13 is_stmt 0 view .LVU357
+ 1062 0058 016D     		ldr	r1, [r0, #80]
+ 1063              	.LVL89:
+4111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->pTxBuffPtr += 2U;
+ 1064              		.loc 1 4111 9 is_stmt 1 view .LVU358
+4111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->pTxBuffPtr += 2U;
+ 1065              		.loc 1 4111 45 is_stmt 0 view .LVU359
+ 1066 005a 0988     		ldrh	r1, [r1]
+ 1067              	.LVL90:
+4111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->pTxBuffPtr += 2U;
+ 1068              		.loc 1 4111 52 view .LVU360
+ 1069 005c C1F30801 		ubfx	r1, r1, #0, #9
+4111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->pTxBuffPtr += 2U;
+ 1070              		.loc 1 4111 30 view .LVU361
+ 1071 0060 9162     		str	r1, [r2, #40]
+ 1072              	.LVL91:
+4112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxXferCount--;
+ 1073              		.loc 1 4112 9 is_stmt 1 view .LVU362
+4112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxXferCount--;
+ 1074              		.loc 1 4112 14 is_stmt 0 view .LVU363
+ 1075 0062 026D     		ldr	r2, [r0, #80]
+4112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->TxXferCount--;
+ 1076              		.loc 1 4112 27 view .LVU364
+ 1077 0064 0232     		adds	r2, r2, #2
+ 1078 0066 0265     		str	r2, [r0, #80]
+4113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1079              		.loc 1 4113 9 is_stmt 1 view .LVU365
+4113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1080              		.loc 1 4113 14 is_stmt 0 view .LVU366
+ 1081 0068 B0F85620 		ldrh	r2, [r0, #86]
+ 1082 006c 92B2     		uxth	r2, r2
+4113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1083              		.loc 1 4113 27 view .LVU367
+ 1084 006e 013A     		subs	r2, r2, #1
+ 1085 0070 92B2     		uxth	r2, r2
+ 1086 0072 A0F85620 		strh	r2, [r0, #86]	@ movhi
+ 1087 0076 E1E7     		b	.L36
+ 1088              		.cfi_endproc
+ 1089              	.LFE393:
+ 1091              		.section	.text.HAL_UART_MspInit,"ax",%progbits
+ 1092              		.align	1
+ 1093              		.weak	HAL_UART_MspInit
+ 1094              		.syntax unified
+ 1095              		.thumb
+ 1096              		.thumb_func
+ARM GAS  /tmp/cceWHrnJ.s 			page 118
+
+
+ 1098              	HAL_UART_MspInit:
+ 1099              	.LVL92:
+ 1100              	.LFB334:
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 1101              		.loc 1 671 1 is_stmt 1 view -0
+ 1102              		.cfi_startproc
+ 1103              		@ args = 0, pretend = 0, frame = 0
+ 1104              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1105              		@ link register save eliminated.
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1106              		.loc 1 673 3 view .LVU369
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1107              		.loc 1 678 1 is_stmt 0 view .LVU370
+ 1108 0000 7047     		bx	lr
+ 1109              		.cfi_endproc
+ 1110              	.LFE334:
+ 1112              		.section	.text.HAL_UART_MspDeInit,"ax",%progbits
+ 1113              		.align	1
+ 1114              		.weak	HAL_UART_MspDeInit
+ 1115              		.syntax unified
+ 1116              		.thumb
+ 1117              		.thumb_func
+ 1119              	HAL_UART_MspDeInit:
+ 1120              	.LVL93:
+ 1121              	.LFB335:
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 1122              		.loc 1 686 1 is_stmt 1 view -0
+ 1123              		.cfi_startproc
+ 1124              		@ args = 0, pretend = 0, frame = 0
+ 1125              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1126              		@ link register save eliminated.
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1127              		.loc 1 688 3 view .LVU372
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1128              		.loc 1 693 1 is_stmt 0 view .LVU373
+ 1129 0000 7047     		bx	lr
+ 1130              		.cfi_endproc
+ 1131              	.LFE335:
+ 1133              		.section	.text.HAL_UART_DeInit,"ax",%progbits
+ 1134              		.align	1
+ 1135              		.global	HAL_UART_DeInit
+ 1136              		.syntax unified
+ 1137              		.thumb
+ 1138              		.thumb_func
+ 1140              	HAL_UART_DeInit:
+ 1141              	.LVL94:
+ 1142              	.LFB333:
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 1143              		.loc 1 625 1 is_stmt 1 view -0
+ 1144              		.cfi_startproc
+ 1145              		@ args = 0, pretend = 0, frame = 0
+ 1146              		@ frame_needed = 0, uses_anonymous_args = 0
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 1147              		.loc 1 627 3 view .LVU375
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 1148              		.loc 1 627 6 is_stmt 0 view .LVU376
+ 1149 0000 E8B1     		cbz	r0, .L43
+ARM GAS  /tmp/cceWHrnJ.s 			page 119
+
+
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 1150              		.loc 1 625 1 view .LVU377
+ 1151 0002 38B5     		push	{r3, r4, r5, lr}
+ 1152              	.LCFI0:
+ 1153              		.cfi_def_cfa_offset 16
+ 1154              		.cfi_offset 3, -16
+ 1155              		.cfi_offset 4, -12
+ 1156              		.cfi_offset 5, -8
+ 1157              		.cfi_offset 14, -4
+ 1158 0004 0546     		mov	r5, r0
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1159              		.loc 1 633 3 is_stmt 1 view .LVU378
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1160              		.loc 1 635 3 view .LVU379
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1161              		.loc 1 635 17 is_stmt 0 view .LVU380
+ 1162 0006 2423     		movs	r3, #36
+ 1163 0008 C0F88430 		str	r3, [r0, #132]
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1164              		.loc 1 637 3 is_stmt 1 view .LVU381
+ 1165 000c 0268     		ldr	r2, [r0]
+ 1166 000e 1368     		ldr	r3, [r2]
+ 1167 0010 23F00103 		bic	r3, r3, #1
+ 1168 0014 1360     		str	r3, [r2]
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->Instance->CR2 = 0x0U;
+ 1169              		.loc 1 639 3 view .LVU382
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->Instance->CR2 = 0x0U;
+ 1170              		.loc 1 639 8 is_stmt 0 view .LVU383
+ 1171 0016 0368     		ldr	r3, [r0]
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->Instance->CR2 = 0x0U;
+ 1172              		.loc 1 639 24 view .LVU384
+ 1173 0018 0024     		movs	r4, #0
+ 1174 001a 1C60     		str	r4, [r3]
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->Instance->CR3 = 0x0U;
+ 1175              		.loc 1 640 3 is_stmt 1 view .LVU385
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->Instance->CR3 = 0x0U;
+ 1176              		.loc 1 640 8 is_stmt 0 view .LVU386
+ 1177 001c 0368     		ldr	r3, [r0]
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->Instance->CR3 = 0x0U;
+ 1178              		.loc 1 640 24 view .LVU387
+ 1179 001e 5C60     		str	r4, [r3, #4]
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1180              		.loc 1 641 3 is_stmt 1 view .LVU388
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1181              		.loc 1 641 8 is_stmt 0 view .LVU389
+ 1182 0020 0368     		ldr	r3, [r0]
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1183              		.loc 1 641 24 view .LVU390
+ 1184 0022 9C60     		str	r4, [r3, #8]
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 1185              		.loc 1 652 3 is_stmt 1 view .LVU391
+ 1186 0024 FFF7FEFF 		bl	HAL_UART_MspDeInit
+ 1187              	.LVL95:
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_RESET;
+ 1188              		.loc 1 655 3 view .LVU392
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_RESET;
+ 1189              		.loc 1 655 20 is_stmt 0 view .LVU393
+ARM GAS  /tmp/cceWHrnJ.s 			page 120
+
+
+ 1190 0028 C5F88C40 		str	r4, [r5, #140]
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_RESET;
+ 1191              		.loc 1 656 3 is_stmt 1 view .LVU394
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_RESET;
+ 1192              		.loc 1 656 17 is_stmt 0 view .LVU395
+ 1193 002c C5F88440 		str	r4, [r5, #132]
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 1194              		.loc 1 657 3 is_stmt 1 view .LVU396
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 1195              		.loc 1 657 18 is_stmt 0 view .LVU397
+ 1196 0030 C5F88840 		str	r4, [r5, #136]
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1197              		.loc 1 658 3 is_stmt 1 view .LVU398
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1198              		.loc 1 658 24 is_stmt 0 view .LVU399
+ 1199 0034 EC66     		str	r4, [r5, #108]
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1200              		.loc 1 660 3 is_stmt 1 view .LVU400
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1201              		.loc 1 660 3 view .LVU401
+ 1202 0036 85F88040 		strb	r4, [r5, #128]
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1203              		.loc 1 660 3 view .LVU402
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 1204              		.loc 1 662 3 view .LVU403
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 1205              		.loc 1 662 10 is_stmt 0 view .LVU404
+ 1206 003a 2046     		mov	r0, r4
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1207              		.loc 1 663 1 view .LVU405
+ 1208 003c 38BD     		pop	{r3, r4, r5, pc}
+ 1209              	.LVL96:
+ 1210              	.L43:
+ 1211              	.LCFI1:
+ 1212              		.cfi_def_cfa_offset 0
+ 1213              		.cfi_restore 3
+ 1214              		.cfi_restore 4
+ 1215              		.cfi_restore 5
+ 1216              		.cfi_restore 14
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1217              		.loc 1 629 12 view .LVU406
+ 1218 003e 0120     		movs	r0, #1
+ 1219              	.LVL97:
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1220              		.loc 1 663 1 view .LVU407
+ 1221 0040 7047     		bx	lr
+ 1222              		.cfi_endproc
+ 1223              	.LFE333:
+ 1225              		.section	.text.HAL_UART_Transmit_IT,"ax",%progbits
+ 1226              		.align	1
+ 1227              		.global	HAL_UART_Transmit_IT
+ 1228              		.syntax unified
+ 1229              		.thumb
+ 1230              		.thumb_func
+ 1232              	HAL_UART_Transmit_IT:
+ 1233              	.LVL98:
+ 1234              	.LFB338:
+ARM GAS  /tmp/cceWHrnJ.s 			page 121
+
+
+1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Tx process is not already ongoing */
+ 1235              		.loc 1 1297 1 is_stmt 1 view -0
+ 1236              		.cfi_startproc
+ 1237              		@ args = 0, pretend = 0, frame = 0
+ 1238              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1239              		@ link register save eliminated.
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 1240              		.loc 1 1299 3 view .LVU409
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 1241              		.loc 1 1299 12 is_stmt 0 view .LVU410
+ 1242 0000 D0F88430 		ldr	r3, [r0, #132]
+1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 1243              		.loc 1 1299 6 view .LVU411
+ 1244 0004 202B     		cmp	r3, #32
+ 1245 0006 50D1     		bne	.L58
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1246              		.loc 1 1301 5 is_stmt 1 view .LVU412
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1247              		.loc 1 1301 8 is_stmt 0 view .LVU413
+ 1248 0008 0029     		cmp	r1, #0
+ 1249 000a 50D0     		beq	.L59
+1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1250              		.loc 1 1301 25 discriminator 1 view .LVU414
+ 1251 000c 002A     		cmp	r2, #0
+ 1252 000e 50D0     		beq	.L60
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1253              		.loc 1 1306 5 is_stmt 1 view .LVU415
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1254              		.loc 1 1306 5 view .LVU416
+ 1255 0010 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 1256 0014 012B     		cmp	r3, #1
+ 1257 0016 4ED0     		beq	.L61
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1258              		.loc 1 1306 5 discriminator 2 view .LVU417
+ 1259 0018 0123     		movs	r3, #1
+ 1260 001a 80F88030 		strb	r3, [r0, #128]
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1261              		.loc 1 1306 5 discriminator 2 view .LVU418
+1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferSize  = Size;
+ 1262              		.loc 1 1308 5 discriminator 2 view .LVU419
+1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferSize  = Size;
+ 1263              		.loc 1 1308 24 is_stmt 0 discriminator 2 view .LVU420
+ 1264 001e 0165     		str	r1, [r0, #80]
+1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = Size;
+ 1265              		.loc 1 1309 5 is_stmt 1 discriminator 2 view .LVU421
+1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = Size;
+ 1266              		.loc 1 1309 24 is_stmt 0 discriminator 2 view .LVU422
+ 1267 0020 A0F85420 		strh	r2, [r0, #84]	@ movhi
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxISR       = NULL;
+ 1268              		.loc 1 1310 5 is_stmt 1 discriminator 2 view .LVU423
+1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxISR       = NULL;
+ 1269              		.loc 1 1310 24 is_stmt 0 discriminator 2 view .LVU424
+ 1270 0024 A0F85620 		strh	r2, [r0, #86]	@ movhi
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1271              		.loc 1 1311 5 is_stmt 1 discriminator 2 view .LVU425
+1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1272              		.loc 1 1311 24 is_stmt 0 discriminator 2 view .LVU426
+ARM GAS  /tmp/cceWHrnJ.s 			page 122
+
+
+ 1273 0028 0023     		movs	r3, #0
+ 1274 002a 4367     		str	r3, [r0, #116]
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->gState = HAL_UART_STATE_BUSY_TX;
+ 1275              		.loc 1 1313 5 is_stmt 1 discriminator 2 view .LVU427
+1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->gState = HAL_UART_STATE_BUSY_TX;
+ 1276              		.loc 1 1313 22 is_stmt 0 discriminator 2 view .LVU428
+ 1277 002c C0F88C30 		str	r3, [r0, #140]
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1278              		.loc 1 1314 5 is_stmt 1 discriminator 2 view .LVU429
+1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1279              		.loc 1 1314 19 is_stmt 0 discriminator 2 view .LVU430
+ 1280 0030 2123     		movs	r3, #33
+ 1281 0032 C0F88430 		str	r3, [r0, #132]
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1282              		.loc 1 1317 5 is_stmt 1 discriminator 2 view .LVU431
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1283              		.loc 1 1317 14 is_stmt 0 discriminator 2 view .LVU432
+ 1284 0036 436E     		ldr	r3, [r0, #100]
+1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1285              		.loc 1 1317 8 discriminator 2 view .LVU433
+ 1286 0038 B3F1005F 		cmp	r3, #536870912
+ 1287 003c 13D0     		beq	.L62
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1288              		.loc 1 1337 7 is_stmt 1 view .LVU434
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1289              		.loc 1 1337 23 is_stmt 0 view .LVU435
+ 1290 003e 8368     		ldr	r3, [r0, #8]
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1291              		.loc 1 1337 10 view .LVU436
+ 1292 0040 B3F5805F 		cmp	r3, #4096
+ 1293 0044 2BD0     		beq	.L63
+ 1294              	.L55:
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1295              		.loc 1 1343 9 is_stmt 1 view .LVU437
+1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1296              		.loc 1 1343 22 is_stmt 0 view .LVU438
+ 1297 0046 1D4B     		ldr	r3, .L65
+ 1298 0048 4367     		str	r3, [r0, #116]
+ 1299              	.L56:
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1300              		.loc 1 1346 7 is_stmt 1 view .LVU439
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1301              		.loc 1 1346 7 view .LVU440
+ 1302 004a 0023     		movs	r3, #0
+ 1303 004c 80F88030 		strb	r3, [r0, #128]
+ 1304              	.LVL99:
+ 1305              	.L57:
+1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1306              		.loc 1 1346 7 discriminator 1 view .LVU441
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1307              		.loc 1 1349 7 discriminator 1 view .LVU442
+ 1308              	.LBB574:
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1309              		.loc 1 1349 7 discriminator 1 view .LVU443
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1310              		.loc 1 1349 7 discriminator 1 view .LVU444
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ARM GAS  /tmp/cceWHrnJ.s 			page 123
+
+
+ 1311              		.loc 1 1349 7 discriminator 1 view .LVU445
+ 1312 0050 0268     		ldr	r2, [r0]
+ 1313              	.LVL100:
+ 1314              	.LBB575:
+ 1315              	.LBI575:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1316              		.loc 2 1151 31 discriminator 1 view .LVU446
+ 1317              	.LBB576:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1318              		.loc 2 1153 5 discriminator 1 view .LVU447
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1319              		.loc 2 1155 4 discriminator 1 view .LVU448
+ 1320              		.syntax unified
+ 1321              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1322 0052 52E8003F 		ldrex r3, [r2]
+ 1323              	@ 0 "" 2
+ 1324              	.LVL101:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1325              		.loc 2 1156 4 discriminator 1 view .LVU449
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1326              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU450
+ 1327              		.thumb
+ 1328              		.syntax unified
+ 1329              	.LBE576:
+ 1330              	.LBE575:
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1331              		.loc 1 1349 7 discriminator 1 view .LVU451
+ 1332 0056 43F08003 		orr	r3, r3, #128
+ 1333              	.LVL102:
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1334              		.loc 1 1349 7 is_stmt 1 discriminator 1 view .LVU452
+ 1335              	.LBB577:
+ 1336              	.LBI577:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1337              		.loc 2 1202 31 discriminator 1 view .LVU453
+ 1338              	.LBB578:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1339              		.loc 2 1204 4 discriminator 1 view .LVU454
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1340              		.loc 2 1206 4 discriminator 1 view .LVU455
+ 1341              		.syntax unified
+ 1342              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1343 005a 42E80031 		strex r1, r3, [r2]
+ 1344              	@ 0 "" 2
+ 1345              	.LVL103:
+ 1346              		.loc 2 1207 4 discriminator 1 view .LVU456
+ 1347              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU457
+ 1348              		.thumb
+ 1349              		.syntax unified
+ 1350              	.LBE578:
+ 1351              	.LBE577:
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1352              		.loc 1 1349 7 discriminator 1 view .LVU458
+ 1353 005e 0029     		cmp	r1, #0
+ 1354 0060 F6D1     		bne	.L57
+ 1355              	.LVL104:
+ 1356              	.L54:
+ARM GAS  /tmp/cceWHrnJ.s 			page 124
+
+
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1357              		.loc 1 1349 7 discriminator 1 view .LVU459
+ 1358              	.LBE574:
+1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1359              		.loc 1 1349 7 is_stmt 1 discriminator 2 view .LVU460
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1360              		.loc 1 1352 5 discriminator 2 view .LVU461
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1361              		.loc 1 1352 12 is_stmt 0 discriminator 2 view .LVU462
+ 1362 0062 0020     		movs	r0, #0
+ 1363              	.LVL105:
+1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1364              		.loc 1 1352 12 discriminator 2 view .LVU463
+ 1365 0064 7047     		bx	lr
+ 1366              	.LVL106:
+ 1367              	.L62:
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1368              		.loc 1 1320 7 is_stmt 1 view .LVU464
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1369              		.loc 1 1320 23 is_stmt 0 view .LVU465
+ 1370 0066 8368     		ldr	r3, [r0, #8]
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1371              		.loc 1 1320 10 view .LVU466
+ 1372 0068 B3F5805F 		cmp	r3, #4096
+ 1373 006c 11D0     		beq	.L64
+ 1374              	.L51:
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1375              		.loc 1 1326 9 is_stmt 1 view .LVU467
+1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1376              		.loc 1 1326 22 is_stmt 0 view .LVU468
+ 1377 006e 144B     		ldr	r3, .L65+4
+ 1378 0070 4367     		str	r3, [r0, #116]
+ 1379              	.L52:
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1380              		.loc 1 1329 7 is_stmt 1 view .LVU469
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1381              		.loc 1 1329 7 view .LVU470
+ 1382 0072 0023     		movs	r3, #0
+ 1383 0074 80F88030 		strb	r3, [r0, #128]
+ 1384              	.LVL107:
+ 1385              	.L53:
+1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1386              		.loc 1 1329 7 discriminator 1 view .LVU471
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1387              		.loc 1 1332 7 discriminator 1 view .LVU472
+ 1388              	.LBB579:
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1389              		.loc 1 1332 7 discriminator 1 view .LVU473
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1390              		.loc 1 1332 7 discriminator 1 view .LVU474
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1391              		.loc 1 1332 7 discriminator 1 view .LVU475
+ 1392 0078 0268     		ldr	r2, [r0]
+ 1393              	.LVL108:
+ 1394              	.LBB580:
+ 1395              	.LBI580:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/cceWHrnJ.s 			page 125
+
+
+ 1396              		.loc 2 1151 31 discriminator 1 view .LVU476
+ 1397              	.LBB581:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1398              		.loc 2 1153 5 discriminator 1 view .LVU477
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1399              		.loc 2 1155 4 discriminator 1 view .LVU478
+ 1400 007a 02F10803 		add	r3, r2, #8
+ 1401              	.LVL109:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1402              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU479
+ 1403              		.syntax unified
+ 1404              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1405 007e 53E8003F 		ldrex r3, [r3]
+ 1406              	@ 0 "" 2
+ 1407              	.LVL110:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1408              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU480
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1409              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU481
+ 1410              		.thumb
+ 1411              		.syntax unified
+ 1412              	.LBE581:
+ 1413              	.LBE580:
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1414              		.loc 1 1332 7 discriminator 1 view .LVU482
+ 1415 0082 43F40003 		orr	r3, r3, #8388608
+ 1416              	.LVL111:
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1417              		.loc 1 1332 7 is_stmt 1 discriminator 1 view .LVU483
+ 1418              	.LBB582:
+ 1419              	.LBI582:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1420              		.loc 2 1202 31 discriminator 1 view .LVU484
+ 1421              	.LBB583:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1422              		.loc 2 1204 4 discriminator 1 view .LVU485
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1423              		.loc 2 1206 4 discriminator 1 view .LVU486
+ 1424 0086 0832     		adds	r2, r2, #8
+ 1425              	.LVL112:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1426              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU487
+ 1427              		.syntax unified
+ 1428              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1429 0088 42E80031 		strex r1, r3, [r2]
+ 1430              	@ 0 "" 2
+ 1431              	.LVL113:
+ 1432              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU488
+ 1433              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU489
+ 1434              		.thumb
+ 1435              		.syntax unified
+ 1436              	.LBE583:
+ 1437              	.LBE582:
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1438              		.loc 1 1332 7 discriminator 1 view .LVU490
+ 1439 008c 0029     		cmp	r1, #0
+ 1440 008e F3D1     		bne	.L53
+ARM GAS  /tmp/cceWHrnJ.s 			page 126
+
+
+ 1441 0090 E7E7     		b	.L54
+ 1442              	.LVL114:
+ 1443              	.L64:
+1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1444              		.loc 1 1332 7 discriminator 1 view .LVU491
+ 1445              	.LBE579:
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1446              		.loc 1 1320 73 discriminator 1 view .LVU492
+ 1447 0092 0369     		ldr	r3, [r0, #16]
+1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1448              		.loc 1 1320 58 discriminator 1 view .LVU493
+ 1449 0094 002B     		cmp	r3, #0
+ 1450 0096 EAD1     		bne	.L51
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1451              		.loc 1 1322 9 is_stmt 1 view .LVU494
+1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1452              		.loc 1 1322 22 is_stmt 0 view .LVU495
+ 1453 0098 0A4B     		ldr	r3, .L65+8
+ 1454 009a 4367     		str	r3, [r0, #116]
+ 1455 009c E9E7     		b	.L52
+ 1456              	.L63:
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1457              		.loc 1 1337 73 discriminator 1 view .LVU496
+ 1458 009e 0369     		ldr	r3, [r0, #16]
+1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1459              		.loc 1 1337 58 discriminator 1 view .LVU497
+ 1460 00a0 002B     		cmp	r3, #0
+ 1461 00a2 D0D1     		bne	.L55
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1462              		.loc 1 1339 9 is_stmt 1 view .LVU498
+1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1463              		.loc 1 1339 22 is_stmt 0 view .LVU499
+ 1464 00a4 084B     		ldr	r3, .L65+12
+ 1465 00a6 4367     		str	r3, [r0, #116]
+ 1466 00a8 CFE7     		b	.L56
+ 1467              	.L58:
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1468              		.loc 1 1356 12 view .LVU500
+ 1469 00aa 0220     		movs	r0, #2
+ 1470              	.LVL115:
+1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1471              		.loc 1 1356 12 view .LVU501
+ 1472 00ac 7047     		bx	lr
+ 1473              	.LVL116:
+ 1474              	.L59:
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1475              		.loc 1 1303 14 view .LVU502
+ 1476 00ae 0120     		movs	r0, #1
+ 1477              	.LVL117:
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1478              		.loc 1 1303 14 view .LVU503
+ 1479 00b0 7047     		bx	lr
+ 1480              	.LVL118:
+ 1481              	.L60:
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1482              		.loc 1 1303 14 view .LVU504
+ 1483 00b2 0120     		movs	r0, #1
+ARM GAS  /tmp/cceWHrnJ.s 			page 127
+
+
+ 1484              	.LVL119:
+1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1485              		.loc 1 1303 14 view .LVU505
+ 1486 00b4 7047     		bx	lr
+ 1487              	.LVL120:
+ 1488              	.L61:
+1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1489              		.loc 1 1306 5 view .LVU506
+ 1490 00b6 0220     		movs	r0, #2
+ 1491              	.LVL121:
+1358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1492              		.loc 1 1358 1 view .LVU507
+ 1493 00b8 7047     		bx	lr
+ 1494              	.L66:
+ 1495 00ba 00BF     		.align	2
+ 1496              	.L65:
+ 1497 00bc 00000000 		.word	UART_TxISR_8BIT
+ 1498 00c0 00000000 		.word	UART_TxISR_8BIT_FIFOEN
+ 1499 00c4 00000000 		.word	UART_TxISR_16BIT_FIFOEN
+ 1500 00c8 00000000 		.word	UART_TxISR_16BIT
+ 1501              		.cfi_endproc
+ 1502              	.LFE338:
+ 1504              		.section	.text.HAL_UART_Transmit_DMA,"ax",%progbits
+ 1505              		.align	1
+ 1506              		.global	HAL_UART_Transmit_DMA
+ 1507              		.syntax unified
+ 1508              		.thumb
+ 1509              		.thumb_func
+ 1511              	HAL_UART_Transmit_DMA:
+ 1512              	.LVL122:
+ 1513              	.LFB340:
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Tx process is not already ongoing */
+ 1514              		.loc 1 1414 1 is_stmt 1 view -0
+ 1515              		.cfi_startproc
+ 1516              		@ args = 0, pretend = 0, frame = 0
+ 1517              		@ frame_needed = 0, uses_anonymous_args = 0
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Tx process is not already ongoing */
+ 1518              		.loc 1 1414 1 is_stmt 0 view .LVU509
+ 1519 0000 1346     		mov	r3, r2
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 1520              		.loc 1 1416 3 is_stmt 1 view .LVU510
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 1521              		.loc 1 1416 12 is_stmt 0 view .LVU511
+ 1522 0002 D0F88420 		ldr	r2, [r0, #132]
+ 1523              	.LVL123:
+1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 1524              		.loc 1 1416 6 view .LVU512
+ 1525 0006 202A     		cmp	r2, #32
+ 1526 0008 4AD1     		bne	.L71
+1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Tx process is not already ongoing */
+ 1527              		.loc 1 1414 1 view .LVU513
+ 1528 000a 10B5     		push	{r4, lr}
+ 1529              	.LCFI2:
+ 1530              		.cfi_def_cfa_offset 8
+ 1531              		.cfi_offset 4, -8
+ 1532              		.cfi_offset 14, -4
+ 1533 000c 0446     		mov	r4, r0
+ARM GAS  /tmp/cceWHrnJ.s 			page 128
+
+
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1534              		.loc 1 1418 5 is_stmt 1 view .LVU514
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1535              		.loc 1 1418 8 is_stmt 0 view .LVU515
+ 1536 000e 0029     		cmp	r1, #0
+ 1537 0010 48D0     		beq	.L72
+1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1538              		.loc 1 1418 25 discriminator 1 view .LVU516
+ 1539 0012 002B     		cmp	r3, #0
+ 1540 0014 48D0     		beq	.L73
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1541              		.loc 1 1423 5 is_stmt 1 view .LVU517
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1542              		.loc 1 1423 5 view .LVU518
+ 1543 0016 90F88020 		ldrb	r2, [r0, #128]	@ zero_extendqisi2
+ 1544 001a 012A     		cmp	r2, #1
+ 1545 001c 46D0     		beq	.L74
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1546              		.loc 1 1423 5 discriminator 2 view .LVU519
+ 1547 001e 0122     		movs	r2, #1
+ 1548 0020 80F88020 		strb	r2, [r0, #128]
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1549              		.loc 1 1423 5 discriminator 2 view .LVU520
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferSize  = Size;
+ 1550              		.loc 1 1425 5 discriminator 2 view .LVU521
+1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferSize  = Size;
+ 1551              		.loc 1 1425 24 is_stmt 0 discriminator 2 view .LVU522
+ 1552 0024 0165     		str	r1, [r0, #80]
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = Size;
+ 1553              		.loc 1 1426 5 is_stmt 1 discriminator 2 view .LVU523
+1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = Size;
+ 1554              		.loc 1 1426 24 is_stmt 0 discriminator 2 view .LVU524
+ 1555 0026 A0F85430 		strh	r3, [r0, #84]	@ movhi
+1427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1556              		.loc 1 1427 5 is_stmt 1 discriminator 2 view .LVU525
+1427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1557              		.loc 1 1427 24 is_stmt 0 discriminator 2 view .LVU526
+ 1558 002a A0F85630 		strh	r3, [r0, #86]	@ movhi
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->gState = HAL_UART_STATE_BUSY_TX;
+ 1559              		.loc 1 1429 5 is_stmt 1 discriminator 2 view .LVU527
+1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->gState = HAL_UART_STATE_BUSY_TX;
+ 1560              		.loc 1 1429 22 is_stmt 0 discriminator 2 view .LVU528
+ 1561 002e 0022     		movs	r2, #0
+ 1562 0030 C0F88C20 		str	r2, [r0, #140]
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1563              		.loc 1 1430 5 is_stmt 1 discriminator 2 view .LVU529
+1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1564              		.loc 1 1430 19 is_stmt 0 discriminator 2 view .LVU530
+ 1565 0034 2122     		movs	r2, #33
+ 1566 0036 C0F88420 		str	r2, [r0, #132]
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1567              		.loc 1 1432 5 is_stmt 1 discriminator 2 view .LVU531
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1568              		.loc 1 1432 14 is_stmt 0 discriminator 2 view .LVU532
+ 1569 003a 826F     		ldr	r2, [r0, #120]
+1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 1570              		.loc 1 1432 8 discriminator 2 view .LVU533
+ARM GAS  /tmp/cceWHrnJ.s 			page 129
+
+
+ 1571 003c E2B1     		cbz	r2, .L69
+1435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1572              		.loc 1 1435 7 is_stmt 1 view .LVU534
+1435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1573              		.loc 1 1435 39 is_stmt 0 view .LVU535
+ 1574 003e 1C49     		ldr	r1, .L79
+ 1575              	.LVL124:
+1435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1576              		.loc 1 1435 39 view .LVU536
+ 1577 0040 D162     		str	r1, [r2, #44]
+ 1578              	.LVL125:
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1579              		.loc 1 1438 7 is_stmt 1 view .LVU537
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1580              		.loc 1 1438 12 is_stmt 0 view .LVU538
+ 1581 0042 826F     		ldr	r2, [r0, #120]
+1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1582              		.loc 1 1438 43 view .LVU539
+ 1583 0044 1B49     		ldr	r1, .L79+4
+ 1584 0046 1163     		str	r1, [r2, #48]
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1585              		.loc 1 1441 7 is_stmt 1 view .LVU540
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1586              		.loc 1 1441 12 is_stmt 0 view .LVU541
+ 1587 0048 826F     		ldr	r2, [r0, #120]
+1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1588              		.loc 1 1441 40 view .LVU542
+ 1589 004a 1B49     		ldr	r1, .L79+8
+ 1590 004c 5163     		str	r1, [r2, #52]
+1444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1591              		.loc 1 1444 7 is_stmt 1 view .LVU543
+1444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1592              		.loc 1 1444 12 is_stmt 0 view .LVU544
+ 1593 004e 826F     		ldr	r2, [r0, #120]
+1444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1594              		.loc 1 1444 40 view .LVU545
+ 1595 0050 0021     		movs	r1, #0
+ 1596 0052 9163     		str	r1, [r2, #56]
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1597              		.loc 1 1447 7 is_stmt 1 view .LVU546
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1598              		.loc 1 1447 88 is_stmt 0 view .LVU547
+ 1599 0054 0268     		ldr	r2, [r0]
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1600              		.loc 1 1447 11 view .LVU548
+ 1601 0056 2832     		adds	r2, r2, #40
+ 1602 0058 016D     		ldr	r1, [r0, #80]
+ 1603 005a 806F     		ldr	r0, [r0, #120]
+ 1604              	.LVL126:
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1605              		.loc 1 1447 11 view .LVU549
+ 1606 005c FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 1607              	.LVL127:
+1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 1608              		.loc 1 1447 10 view .LVU550
+ 1609 0060 50B1     		cbz	r0, .L69
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 130
+
+
+ 1610              		.loc 1 1450 9 is_stmt 1 view .LVU551
+1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1611              		.loc 1 1450 26 is_stmt 0 view .LVU552
+ 1612 0062 1023     		movs	r3, #16
+ 1613 0064 C4F88C30 		str	r3, [r4, #140]
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1614              		.loc 1 1452 9 is_stmt 1 view .LVU553
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1615              		.loc 1 1452 9 view .LVU554
+ 1616 0068 0023     		movs	r3, #0
+ 1617 006a 84F88030 		strb	r3, [r4, #128]
+1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1618              		.loc 1 1452 9 view .LVU555
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1619              		.loc 1 1455 9 view .LVU556
+1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1620              		.loc 1 1455 23 is_stmt 0 view .LVU557
+ 1621 006e 2023     		movs	r3, #32
+ 1622 0070 C4F88430 		str	r3, [r4, #132]
+1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1623              		.loc 1 1457 9 is_stmt 1 view .LVU558
+1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 1624              		.loc 1 1457 16 is_stmt 0 view .LVU559
+ 1625 0074 0120     		movs	r0, #1
+ 1626 0076 12E0     		b	.L68
+ 1627              	.L69:
+1461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1628              		.loc 1 1461 5 is_stmt 1 view .LVU560
+ 1629 0078 2368     		ldr	r3, [r4]
+ 1630 007a 4022     		movs	r2, #64
+ 1631 007c 1A62     		str	r2, [r3, #32]
+1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1632              		.loc 1 1463 5 view .LVU561
+1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1633              		.loc 1 1463 5 view .LVU562
+ 1634 007e 0023     		movs	r3, #0
+ 1635 0080 84F88030 		strb	r3, [r4, #128]
+ 1636              	.L70:
+1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1637              		.loc 1 1463 5 discriminator 1 view .LVU563
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1638              		.loc 1 1467 5 discriminator 1 view .LVU564
+ 1639              	.LBB584:
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1640              		.loc 1 1467 5 discriminator 1 view .LVU565
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1641              		.loc 1 1467 5 discriminator 1 view .LVU566
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1642              		.loc 1 1467 5 discriminator 1 view .LVU567
+ 1643 0084 2268     		ldr	r2, [r4]
+ 1644              	.LVL128:
+ 1645              	.LBB585:
+ 1646              	.LBI585:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1647              		.loc 2 1151 31 discriminator 1 view .LVU568
+ 1648              	.LBB586:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 131
+
+
+ 1649              		.loc 2 1153 5 discriminator 1 view .LVU569
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1650              		.loc 2 1155 4 discriminator 1 view .LVU570
+ 1651 0086 02F10803 		add	r3, r2, #8
+ 1652              	.LVL129:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1653              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU571
+ 1654              		.syntax unified
+ 1655              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1656 008a 53E8003F 		ldrex r3, [r3]
+ 1657              	@ 0 "" 2
+ 1658              	.LVL130:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1659              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU572
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1660              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU573
+ 1661              		.thumb
+ 1662              		.syntax unified
+ 1663              	.LBE586:
+ 1664              	.LBE585:
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1665              		.loc 1 1467 5 discriminator 1 view .LVU574
+ 1666 008e 43F08003 		orr	r3, r3, #128
+ 1667              	.LVL131:
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1668              		.loc 1 1467 5 is_stmt 1 discriminator 1 view .LVU575
+ 1669              	.LBB587:
+ 1670              	.LBI587:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1671              		.loc 2 1202 31 discriminator 1 view .LVU576
+ 1672              	.LBB588:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1673              		.loc 2 1204 4 discriminator 1 view .LVU577
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1674              		.loc 2 1206 4 discriminator 1 view .LVU578
+ 1675 0092 0832     		adds	r2, r2, #8
+ 1676              	.LVL132:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1677              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU579
+ 1678              		.syntax unified
+ 1679              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1680 0094 42E80031 		strex r1, r3, [r2]
+ 1681              	@ 0 "" 2
+ 1682              	.LVL133:
+ 1683              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU580
+ 1684              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU581
+ 1685              		.thumb
+ 1686              		.syntax unified
+ 1687              	.LBE588:
+ 1688              	.LBE587:
+1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1689              		.loc 1 1467 5 discriminator 1 view .LVU582
+ 1690 0098 0029     		cmp	r1, #0
+ 1691 009a F3D1     		bne	.L70
+ 1692              	.LBE584:
+1469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1693              		.loc 1 1469 12 view .LVU583
+ARM GAS  /tmp/cceWHrnJ.s 			page 132
+
+
+ 1694 009c 0020     		movs	r0, #0
+ 1695              	.LVL134:
+ 1696              	.L68:
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1697              		.loc 1 1475 1 view .LVU584
+ 1698 009e 10BD     		pop	{r4, pc}
+ 1699              	.LVL135:
+ 1700              	.L71:
+ 1701              	.LCFI3:
+ 1702              		.cfi_def_cfa_offset 0
+ 1703              		.cfi_restore 4
+ 1704              		.cfi_restore 14
+1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1705              		.loc 1 1473 12 view .LVU585
+ 1706 00a0 0220     		movs	r0, #2
+ 1707              	.LVL136:
+1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1708              		.loc 1 1475 1 view .LVU586
+ 1709 00a2 7047     		bx	lr
+ 1710              	.LVL137:
+ 1711              	.L72:
+ 1712              	.LCFI4:
+ 1713              		.cfi_def_cfa_offset 8
+ 1714              		.cfi_offset 4, -8
+ 1715              		.cfi_offset 14, -4
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1716              		.loc 1 1420 14 view .LVU587
+ 1717 00a4 0120     		movs	r0, #1
+ 1718              	.LVL138:
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1719              		.loc 1 1420 14 view .LVU588
+ 1720 00a6 FAE7     		b	.L68
+ 1721              	.LVL139:
+ 1722              	.L73:
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1723              		.loc 1 1420 14 view .LVU589
+ 1724 00a8 0120     		movs	r0, #1
+ 1725              	.LVL140:
+1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 1726              		.loc 1 1420 14 view .LVU590
+ 1727 00aa F8E7     		b	.L68
+ 1728              	.LVL141:
+ 1729              	.L74:
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1730              		.loc 1 1423 5 view .LVU591
+ 1731 00ac 0220     		movs	r0, #2
+ 1732              	.LVL142:
+1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1733              		.loc 1 1423 5 view .LVU592
+ 1734 00ae F6E7     		b	.L68
+ 1735              	.L80:
+ 1736              		.align	2
+ 1737              	.L79:
+ 1738 00b0 00000000 		.word	UART_DMATransmitCplt
+ 1739 00b4 00000000 		.word	UART_DMATxHalfCplt
+ 1740 00b8 00000000 		.word	UART_DMAError
+ 1741              		.cfi_endproc
+ARM GAS  /tmp/cceWHrnJ.s 			page 133
+
+
+ 1742              	.LFE340:
+ 1744              		.section	.text.HAL_UART_DMAPause,"ax",%progbits
+ 1745              		.align	1
+ 1746              		.global	HAL_UART_DMAPause
+ 1747              		.syntax unified
+ 1748              		.thumb
+ 1749              		.thumb_func
+ 1751              	HAL_UART_DMAPause:
+ 1752              	.LVL143:
+ 1753              	.LFB342:
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef gstate = huart->gState;
+ 1754              		.loc 1 1528 1 is_stmt 1 view -0
+ 1755              		.cfi_startproc
+ 1756              		@ args = 0, pretend = 0, frame = 0
+ 1757              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1758              		@ link register save eliminated.
+1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef gstate = huart->gState;
+ 1759              		.loc 1 1528 1 is_stmt 0 view .LVU594
+ 1760 0000 10B4     		push	{r4}
+ 1761              	.LCFI5:
+ 1762              		.cfi_def_cfa_offset 4
+ 1763              		.cfi_offset 4, -4
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef rxstate = huart->RxState;
+ 1764              		.loc 1 1529 3 is_stmt 1 view .LVU595
+1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef rxstate = huart->RxState;
+ 1765              		.loc 1 1529 31 is_stmt 0 view .LVU596
+ 1766 0002 D0F88410 		ldr	r1, [r0, #132]
+ 1767              	.LVL144:
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1768              		.loc 1 1530 3 is_stmt 1 view .LVU597
+1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1769              		.loc 1 1530 31 is_stmt 0 view .LVU598
+ 1770 0006 D0F88840 		ldr	r4, [r0, #136]
+ 1771              	.LVL145:
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1772              		.loc 1 1532 3 is_stmt 1 view .LVU599
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1773              		.loc 1 1532 3 view .LVU600
+ 1774 000a 90F88020 		ldrb	r2, [r0, #128]	@ zero_extendqisi2
+ 1775 000e 012A     		cmp	r2, #1
+ 1776 0010 46D0     		beq	.L89
+ 1777 0012 0346     		mov	r3, r0
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1778              		.loc 1 1532 3 discriminator 2 view .LVU601
+ 1779 0014 0122     		movs	r2, #1
+ 1780 0016 80F88020 		strb	r2, [r0, #128]
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1781              		.loc 1 1532 3 discriminator 2 view .LVU602
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+ 1782              		.loc 1 1534 3 discriminator 2 view .LVU603
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+ 1783              		.loc 1 1534 8 is_stmt 0 discriminator 2 view .LVU604
+ 1784 001a 0268     		ldr	r2, [r0]
+ 1785 001c 9268     		ldr	r2, [r2, #8]
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+ 1786              		.loc 1 1534 6 discriminator 2 view .LVU605
+ 1787 001e 12F0800F 		tst	r2, #128
+ARM GAS  /tmp/cceWHrnJ.s 			page 134
+
+
+ 1788 0022 01D0     		beq	.L83
+1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+ 1789              		.loc 1 1534 62 discriminator 1 view .LVU606
+ 1790 0024 2129     		cmp	r1, #33
+ 1791 0026 0CD0     		beq	.L84
+ 1792              	.LVL146:
+ 1793              	.L83:
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1794              		.loc 1 1538 5 is_stmt 1 discriminator 2 view .LVU607
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+ 1795              		.loc 1 1540 3 discriminator 2 view .LVU608
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+ 1796              		.loc 1 1540 8 is_stmt 0 discriminator 2 view .LVU609
+ 1797 0028 1A68     		ldr	r2, [r3]
+ 1798 002a 9268     		ldr	r2, [r2, #8]
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+ 1799              		.loc 1 1540 6 discriminator 2 view .LVU610
+ 1800 002c 12F0400F 		tst	r2, #64
+ 1801 0030 01D0     		beq	.L85
+1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+ 1802              		.loc 1 1540 62 discriminator 1 view .LVU611
+ 1803 0032 222C     		cmp	r4, #34
+ 1804 0034 12D0     		beq	.L86
+ 1805              	.L85:
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1806              		.loc 1 1548 5 is_stmt 1 discriminator 2 view .LVU612
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1807              		.loc 1 1551 3 discriminator 2 view .LVU613
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1808              		.loc 1 1551 3 discriminator 2 view .LVU614
+ 1809 0036 0020     		movs	r0, #0
+ 1810 0038 83F88000 		strb	r0, [r3, #128]
+1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1811              		.loc 1 1551 3 discriminator 2 view .LVU615
+1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 1812              		.loc 1 1553 3 discriminator 2 view .LVU616
+ 1813              	.LVL147:
+ 1814              	.L82:
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1815              		.loc 1 1554 1 is_stmt 0 view .LVU617
+ 1816 003c 5DF8044B 		ldr	r4, [sp], #4
+ 1817              	.LCFI6:
+ 1818              		.cfi_remember_state
+ 1819              		.cfi_restore 4
+ 1820              		.cfi_def_cfa_offset 0
+ 1821              	.LVL148:
+1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1822              		.loc 1 1554 1 view .LVU618
+ 1823 0040 7047     		bx	lr
+ 1824              	.LVL149:
+ 1825              	.L84:
+ 1826              	.LCFI7:
+ 1827              		.cfi_restore_state
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1828              		.loc 1 1538 5 is_stmt 1 discriminator 1 view .LVU619
+ 1829              	.LBB589:
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ARM GAS  /tmp/cceWHrnJ.s 			page 135
+
+
+ 1830              		.loc 1 1538 5 discriminator 1 view .LVU620
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1831              		.loc 1 1538 5 discriminator 1 view .LVU621
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1832              		.loc 1 1538 5 discriminator 1 view .LVU622
+ 1833 0042 1968     		ldr	r1, [r3]
+ 1834              	.LVL150:
+ 1835              	.LBB590:
+ 1836              	.LBI590:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1837              		.loc 2 1151 31 discriminator 1 view .LVU623
+ 1838              	.LBB591:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1839              		.loc 2 1153 5 discriminator 1 view .LVU624
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1840              		.loc 2 1155 4 discriminator 1 view .LVU625
+ 1841 0044 01F10802 		add	r2, r1, #8
+ 1842              	.LVL151:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1843              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU626
+ 1844              		.syntax unified
+ 1845              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1846 0048 52E8002F 		ldrex r2, [r2]
+ 1847              	@ 0 "" 2
+ 1848              	.LVL152:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1849              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU627
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1850              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU628
+ 1851              		.thumb
+ 1852              		.syntax unified
+ 1853              	.LBE591:
+ 1854              	.LBE590:
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1855              		.loc 1 1538 5 discriminator 1 view .LVU629
+ 1856 004c 22F08002 		bic	r2, r2, #128
+ 1857              	.LVL153:
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1858              		.loc 1 1538 5 is_stmt 1 discriminator 1 view .LVU630
+ 1859              	.LBB592:
+ 1860              	.LBI592:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1861              		.loc 2 1202 31 discriminator 1 view .LVU631
+ 1862              	.LBB593:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1863              		.loc 2 1204 4 discriminator 1 view .LVU632
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1864              		.loc 2 1206 4 discriminator 1 view .LVU633
+ 1865 0050 0831     		adds	r1, r1, #8
+ 1866              	.LVL154:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1867              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU634
+ 1868              		.syntax unified
+ 1869              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1870 0052 41E80020 		strex r0, r2, [r1]
+ 1871              	@ 0 "" 2
+ 1872              	.LVL155:
+ARM GAS  /tmp/cceWHrnJ.s 			page 136
+
+
+ 1873              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU635
+ 1874              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU636
+ 1875              		.thumb
+ 1876              		.syntax unified
+ 1877              	.LBE593:
+ 1878              	.LBE592:
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1879              		.loc 1 1538 5 discriminator 1 view .LVU637
+ 1880 0056 0028     		cmp	r0, #0
+ 1881 0058 F3D1     		bne	.L84
+ 1882 005a E5E7     		b	.L83
+ 1883              	.LVL156:
+ 1884              	.L86:
+1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1885              		.loc 1 1538 5 discriminator 1 view .LVU638
+ 1886              	.LBE589:
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 1887              		.loc 1 1544 5 is_stmt 1 discriminator 1 view .LVU639
+ 1888              	.LBB594:
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 1889              		.loc 1 1544 5 discriminator 1 view .LVU640
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 1890              		.loc 1 1544 5 discriminator 1 view .LVU641
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 1891              		.loc 1 1544 5 discriminator 1 view .LVU642
+ 1892 005c 1968     		ldr	r1, [r3]
+ 1893              	.LVL157:
+ 1894              	.LBB595:
+ 1895              	.LBI595:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1896              		.loc 2 1151 31 discriminator 1 view .LVU643
+ 1897              	.LBB596:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1898              		.loc 2 1153 5 discriminator 1 view .LVU644
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1899              		.loc 2 1155 4 discriminator 1 view .LVU645
+ 1900              		.syntax unified
+ 1901              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1902 005e 51E8002F 		ldrex r2, [r1]
+ 1903              	@ 0 "" 2
+ 1904              	.LVL158:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1905              		.loc 2 1156 4 discriminator 1 view .LVU646
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1906              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU647
+ 1907              		.thumb
+ 1908              		.syntax unified
+ 1909              	.LBE596:
+ 1910              	.LBE595:
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 1911              		.loc 1 1544 5 discriminator 1 view .LVU648
+ 1912 0062 22F48072 		bic	r2, r2, #256
+ 1913              	.LVL159:
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 1914              		.loc 1 1544 5 is_stmt 1 discriminator 1 view .LVU649
+ 1915              	.LBB597:
+ 1916              	.LBI597:
+ARM GAS  /tmp/cceWHrnJ.s 			page 137
+
+
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1917              		.loc 2 1202 31 discriminator 1 view .LVU650
+ 1918              	.LBB598:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1919              		.loc 2 1204 4 discriminator 1 view .LVU651
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1920              		.loc 2 1206 4 discriminator 1 view .LVU652
+ 1921              		.syntax unified
+ 1922              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1923 0066 41E80020 		strex r0, r2, [r1]
+ 1924              	@ 0 "" 2
+ 1925              	.LVL160:
+ 1926              		.loc 2 1207 4 discriminator 1 view .LVU653
+ 1927              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU654
+ 1928              		.thumb
+ 1929              		.syntax unified
+ 1930              	.LBE598:
+ 1931              	.LBE597:
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 1932              		.loc 1 1544 5 discriminator 1 view .LVU655
+ 1933 006a 0028     		cmp	r0, #0
+ 1934 006c F6D1     		bne	.L86
+ 1935              	.LVL161:
+ 1936              	.L87:
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 1937              		.loc 1 1544 5 discriminator 1 view .LVU656
+ 1938              	.LBE594:
+1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 1939              		.loc 1 1544 5 is_stmt 1 discriminator 1 view .LVU657
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1940              		.loc 1 1545 5 discriminator 1 view .LVU658
+ 1941              	.LBB599:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1942              		.loc 1 1545 5 discriminator 1 view .LVU659
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1943              		.loc 1 1545 5 discriminator 1 view .LVU660
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1944              		.loc 1 1545 5 discriminator 1 view .LVU661
+ 1945 006e 1968     		ldr	r1, [r3]
+ 1946              	.LVL162:
+ 1947              	.LBB600:
+ 1948              	.LBI600:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1949              		.loc 2 1151 31 discriminator 1 view .LVU662
+ 1950              	.LBB601:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1951              		.loc 2 1153 5 discriminator 1 view .LVU663
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1952              		.loc 2 1155 4 discriminator 1 view .LVU664
+ 1953 0070 01F10802 		add	r2, r1, #8
+ 1954              	.LVL163:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1955              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU665
+ 1956              		.syntax unified
+ 1957              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1958 0074 52E8002F 		ldrex r2, [r2]
+ 1959              	@ 0 "" 2
+ARM GAS  /tmp/cceWHrnJ.s 			page 138
+
+
+ 1960              	.LVL164:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1961              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU666
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1962              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU667
+ 1963              		.thumb
+ 1964              		.syntax unified
+ 1965              	.LBE601:
+ 1966              	.LBE600:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1967              		.loc 1 1545 5 discriminator 1 view .LVU668
+ 1968 0078 22F00102 		bic	r2, r2, #1
+ 1969              	.LVL165:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1970              		.loc 1 1545 5 is_stmt 1 discriminator 1 view .LVU669
+ 1971              	.LBB602:
+ 1972              	.LBI602:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1973              		.loc 2 1202 31 discriminator 1 view .LVU670
+ 1974              	.LBB603:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1975              		.loc 2 1204 4 discriminator 1 view .LVU671
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1976              		.loc 2 1206 4 discriminator 1 view .LVU672
+ 1977 007c 0831     		adds	r1, r1, #8
+ 1978              	.LVL166:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1979              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU673
+ 1980              		.syntax unified
+ 1981              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1982 007e 41E80020 		strex r0, r2, [r1]
+ 1983              	@ 0 "" 2
+ 1984              	.LVL167:
+ 1985              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU674
+ 1986              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU675
+ 1987              		.thumb
+ 1988              		.syntax unified
+ 1989              	.LBE603:
+ 1990              	.LBE602:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1991              		.loc 1 1545 5 discriminator 1 view .LVU676
+ 1992 0082 0028     		cmp	r0, #0
+ 1993 0084 F3D1     		bne	.L87
+ 1994              	.LVL168:
+ 1995              	.L88:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1996              		.loc 1 1545 5 discriminator 1 view .LVU677
+ 1997              	.LBE599:
+1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 1998              		.loc 1 1545 5 is_stmt 1 discriminator 1 view .LVU678
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 1999              		.loc 1 1548 5 discriminator 1 view .LVU679
+ 2000              	.LBB604:
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2001              		.loc 1 1548 5 discriminator 1 view .LVU680
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2002              		.loc 1 1548 5 discriminator 1 view .LVU681
+ARM GAS  /tmp/cceWHrnJ.s 			page 139
+
+
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2003              		.loc 1 1548 5 discriminator 1 view .LVU682
+ 2004 0086 1968     		ldr	r1, [r3]
+ 2005              	.LVL169:
+ 2006              	.LBB605:
+ 2007              	.LBI605:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2008              		.loc 2 1151 31 discriminator 1 view .LVU683
+ 2009              	.LBB606:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2010              		.loc 2 1153 5 discriminator 1 view .LVU684
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2011              		.loc 2 1155 4 discriminator 1 view .LVU685
+ 2012 0088 01F10802 		add	r2, r1, #8
+ 2013              	.LVL170:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2014              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU686
+ 2015              		.syntax unified
+ 2016              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2017 008c 52E8002F 		ldrex r2, [r2]
+ 2018              	@ 0 "" 2
+ 2019              	.LVL171:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2020              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU687
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2021              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU688
+ 2022              		.thumb
+ 2023              		.syntax unified
+ 2024              	.LBE606:
+ 2025              	.LBE605:
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2026              		.loc 1 1548 5 discriminator 1 view .LVU689
+ 2027 0090 22F04002 		bic	r2, r2, #64
+ 2028              	.LVL172:
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2029              		.loc 1 1548 5 is_stmt 1 discriminator 1 view .LVU690
+ 2030              	.LBB607:
+ 2031              	.LBI607:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2032              		.loc 2 1202 31 discriminator 1 view .LVU691
+ 2033              	.LBB608:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2034              		.loc 2 1204 4 discriminator 1 view .LVU692
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2035              		.loc 2 1206 4 discriminator 1 view .LVU693
+ 2036 0094 0831     		adds	r1, r1, #8
+ 2037              	.LVL173:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2038              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU694
+ 2039              		.syntax unified
+ 2040              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2041 0096 41E80020 		strex r0, r2, [r1]
+ 2042              	@ 0 "" 2
+ 2043              	.LVL174:
+ 2044              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU695
+ 2045              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU696
+ 2046              		.thumb
+ARM GAS  /tmp/cceWHrnJ.s 			page 140
+
+
+ 2047              		.syntax unified
+ 2048              	.LBE608:
+ 2049              	.LBE607:
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2050              		.loc 1 1548 5 discriminator 1 view .LVU697
+ 2051 009a 0028     		cmp	r0, #0
+ 2052 009c F3D1     		bne	.L88
+ 2053 009e CAE7     		b	.L85
+ 2054              	.LVL175:
+ 2055              	.L89:
+1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2056              		.loc 1 1548 5 discriminator 1 view .LVU698
+ 2057              	.LBE604:
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2058              		.loc 1 1532 3 view .LVU699
+ 2059 00a0 0220     		movs	r0, #2
+ 2060              	.LVL176:
+1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2061              		.loc 1 1532 3 view .LVU700
+ 2062 00a2 CBE7     		b	.L82
+ 2063              		.cfi_endproc
+ 2064              	.LFE342:
+ 2066              		.section	.text.HAL_UART_DMAResume,"ax",%progbits
+ 2067              		.align	1
+ 2068              		.global	HAL_UART_DMAResume
+ 2069              		.syntax unified
+ 2070              		.thumb
+ 2071              		.thumb_func
+ 2073              	HAL_UART_DMAResume:
+ 2074              	.LVL177:
+ 2075              	.LFB343:
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+ 2076              		.loc 1 1562 1 is_stmt 1 view -0
+ 2077              		.cfi_startproc
+ 2078              		@ args = 0, pretend = 0, frame = 0
+ 2079              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2080              		@ link register save eliminated.
+1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+ 2081              		.loc 1 1562 1 is_stmt 0 view .LVU702
+ 2082 0000 0346     		mov	r3, r0
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2083              		.loc 1 1563 3 is_stmt 1 view .LVU703
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2084              		.loc 1 1563 3 view .LVU704
+ 2085 0002 90F88020 		ldrb	r2, [r0, #128]	@ zero_extendqisi2
+ 2086 0006 012A     		cmp	r2, #1
+ 2087 0008 42D0     		beq	.L100
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2088              		.loc 1 1563 3 discriminator 2 view .LVU705
+ 2089 000a 0122     		movs	r2, #1
+ 2090 000c 80F88020 		strb	r2, [r0, #128]
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2091              		.loc 1 1563 3 discriminator 2 view .LVU706
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2092              		.loc 1 1565 3 discriminator 2 view .LVU707
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2093              		.loc 1 1565 12 is_stmt 0 discriminator 2 view .LVU708
+ARM GAS  /tmp/cceWHrnJ.s 			page 141
+
+
+ 2094 0010 D0F88420 		ldr	r2, [r0, #132]
+1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2095              		.loc 1 1565 6 discriminator 2 view .LVU709
+ 2096 0014 212A     		cmp	r2, #33
+ 2097 0016 07D0     		beq	.L94
+ 2098              	.LVL178:
+ 2099              	.L93:
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2100              		.loc 1 1568 5 is_stmt 1 discriminator 2 view .LVU710
+1570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2101              		.loc 1 1570 3 discriminator 2 view .LVU711
+1570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2102              		.loc 1 1570 12 is_stmt 0 discriminator 2 view .LVU712
+ 2103 0018 D3F88820 		ldr	r2, [r3, #136]
+1570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2104              		.loc 1 1570 6 discriminator 2 view .LVU713
+ 2105 001c 222A     		cmp	r2, #34
+ 2106 001e 10D0     		beq	.L101
+ 2107              	.L95:
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2108              		.loc 1 1583 5 is_stmt 1 discriminator 2 view .LVU714
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2109              		.loc 1 1586 3 discriminator 2 view .LVU715
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2110              		.loc 1 1586 3 discriminator 2 view .LVU716
+ 2111 0020 0020     		movs	r0, #0
+ 2112 0022 83F88000 		strb	r0, [r3, #128]
+1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2113              		.loc 1 1586 3 discriminator 2 view .LVU717
+1588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 2114              		.loc 1 1588 3 discriminator 2 view .LVU718
+1588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 2115              		.loc 1 1588 10 is_stmt 0 discriminator 2 view .LVU719
+ 2116 0026 7047     		bx	lr
+ 2117              	.L94:
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2118              		.loc 1 1568 5 is_stmt 1 discriminator 1 view .LVU720
+ 2119              	.LBB609:
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2120              		.loc 1 1568 5 discriminator 1 view .LVU721
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2121              		.loc 1 1568 5 discriminator 1 view .LVU722
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2122              		.loc 1 1568 5 discriminator 1 view .LVU723
+ 2123 0028 1968     		ldr	r1, [r3]
+ 2124              	.LVL179:
+ 2125              	.LBB610:
+ 2126              	.LBI610:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2127              		.loc 2 1151 31 discriminator 1 view .LVU724
+ 2128              	.LBB611:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2129              		.loc 2 1153 5 discriminator 1 view .LVU725
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2130              		.loc 2 1155 4 discriminator 1 view .LVU726
+ 2131 002a 01F10802 		add	r2, r1, #8
+ 2132              	.LVL180:
+ARM GAS  /tmp/cceWHrnJ.s 			page 142
+
+
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2133              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU727
+ 2134              		.syntax unified
+ 2135              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2136 002e 52E8002F 		ldrex r2, [r2]
+ 2137              	@ 0 "" 2
+ 2138              	.LVL181:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2139              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU728
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2140              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU729
+ 2141              		.thumb
+ 2142              		.syntax unified
+ 2143              	.LBE611:
+ 2144              	.LBE610:
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2145              		.loc 1 1568 5 discriminator 1 view .LVU730
+ 2146 0032 42F08002 		orr	r2, r2, #128
+ 2147              	.LVL182:
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2148              		.loc 1 1568 5 is_stmt 1 discriminator 1 view .LVU731
+ 2149              	.LBB612:
+ 2150              	.LBI612:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2151              		.loc 2 1202 31 discriminator 1 view .LVU732
+ 2152              	.LBB613:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2153              		.loc 2 1204 4 discriminator 1 view .LVU733
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2154              		.loc 2 1206 4 discriminator 1 view .LVU734
+ 2155 0036 0831     		adds	r1, r1, #8
+ 2156              	.LVL183:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2157              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU735
+ 2158              		.syntax unified
+ 2159              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2160 0038 41E80020 		strex r0, r2, [r1]
+ 2161              	@ 0 "" 2
+ 2162              	.LVL184:
+ 2163              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU736
+ 2164              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU737
+ 2165              		.thumb
+ 2166              		.syntax unified
+ 2167              	.LBE613:
+ 2168              	.LBE612:
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2169              		.loc 1 1568 5 discriminator 1 view .LVU738
+ 2170 003c 0028     		cmp	r0, #0
+ 2171 003e F3D1     		bne	.L94
+ 2172 0040 EAE7     		b	.L93
+ 2173              	.LVL185:
+ 2174              	.L101:
+1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2175              		.loc 1 1568 5 discriminator 1 view .LVU739
+ 2176              	.LBE609:
+1573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2177              		.loc 1 1573 5 is_stmt 1 view .LVU740
+ARM GAS  /tmp/cceWHrnJ.s 			page 143
+
+
+ 2178 0042 1A68     		ldr	r2, [r3]
+ 2179 0044 0821     		movs	r1, #8
+ 2180 0046 1162     		str	r1, [r2, #32]
+1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {    
+ 2181              		.loc 1 1576 5 view .LVU741
+1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {    
+ 2182              		.loc 1 1576 20 is_stmt 0 view .LVU742
+ 2183 0048 1A69     		ldr	r2, [r3, #16]
+1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {    
+ 2184              		.loc 1 1576 8 view .LVU743
+ 2185 004a 42B1     		cbz	r2, .L98
+ 2186              	.L97:
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 2187              		.loc 1 1578 7 is_stmt 1 discriminator 1 view .LVU744
+ 2188              	.LBB614:
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 2189              		.loc 1 1578 7 discriminator 1 view .LVU745
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 2190              		.loc 1 1578 7 discriminator 1 view .LVU746
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 2191              		.loc 1 1578 7 discriminator 1 view .LVU747
+ 2192 004c 1968     		ldr	r1, [r3]
+ 2193              	.LVL186:
+ 2194              	.LBB615:
+ 2195              	.LBI615:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2196              		.loc 2 1151 31 discriminator 1 view .LVU748
+ 2197              	.LBB616:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2198              		.loc 2 1153 5 discriminator 1 view .LVU749
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2199              		.loc 2 1155 4 discriminator 1 view .LVU750
+ 2200              		.syntax unified
+ 2201              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2202 004e 51E8002F 		ldrex r2, [r1]
+ 2203              	@ 0 "" 2
+ 2204              	.LVL187:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2205              		.loc 2 1156 4 discriminator 1 view .LVU751
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2206              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU752
+ 2207              		.thumb
+ 2208              		.syntax unified
+ 2209              	.LBE616:
+ 2210              	.LBE615:
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 2211              		.loc 1 1578 7 discriminator 1 view .LVU753
+ 2212 0052 42F48072 		orr	r2, r2, #256
+ 2213              	.LVL188:
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 2214              		.loc 1 1578 7 is_stmt 1 discriminator 1 view .LVU754
+ 2215              	.LBB617:
+ 2216              	.LBI617:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2217              		.loc 2 1202 31 discriminator 1 view .LVU755
+ 2218              	.LBB618:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 144
+
+
+ 2219              		.loc 2 1204 4 discriminator 1 view .LVU756
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2220              		.loc 2 1206 4 discriminator 1 view .LVU757
+ 2221              		.syntax unified
+ 2222              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2223 0056 41E80020 		strex r0, r2, [r1]
+ 2224              	@ 0 "" 2
+ 2225              	.LVL189:
+ 2226              		.loc 2 1207 4 discriminator 1 view .LVU758
+ 2227              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU759
+ 2228              		.thumb
+ 2229              		.syntax unified
+ 2230              	.LBE618:
+ 2231              	.LBE617:
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 2232              		.loc 1 1578 7 discriminator 1 view .LVU760
+ 2233 005a 0028     		cmp	r0, #0
+ 2234 005c F6D1     		bne	.L97
+ 2235              	.LVL190:
+ 2236              	.L98:
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 2237              		.loc 1 1578 7 discriminator 1 view .LVU761
+ 2238              	.LBE614:
+1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 2239              		.loc 1 1578 7 is_stmt 1 discriminator 1 view .LVU762
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2240              		.loc 1 1580 5 discriminator 1 view .LVU763
+ 2241              	.LBB619:
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2242              		.loc 1 1580 5 discriminator 1 view .LVU764
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2243              		.loc 1 1580 5 discriminator 1 view .LVU765
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2244              		.loc 1 1580 5 discriminator 1 view .LVU766
+ 2245 005e 1968     		ldr	r1, [r3]
+ 2246              	.LVL191:
+ 2247              	.LBB620:
+ 2248              	.LBI620:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2249              		.loc 2 1151 31 discriminator 1 view .LVU767
+ 2250              	.LBB621:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2251              		.loc 2 1153 5 discriminator 1 view .LVU768
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2252              		.loc 2 1155 4 discriminator 1 view .LVU769
+ 2253 0060 01F10802 		add	r2, r1, #8
+ 2254              	.LVL192:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2255              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU770
+ 2256              		.syntax unified
+ 2257              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2258 0064 52E8002F 		ldrex r2, [r2]
+ 2259              	@ 0 "" 2
+ 2260              	.LVL193:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2261              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU771
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ARM GAS  /tmp/cceWHrnJ.s 			page 145
+
+
+ 2262              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU772
+ 2263              		.thumb
+ 2264              		.syntax unified
+ 2265              	.LBE621:
+ 2266              	.LBE620:
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2267              		.loc 1 1580 5 discriminator 1 view .LVU773
+ 2268 0068 42F00102 		orr	r2, r2, #1
+ 2269              	.LVL194:
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2270              		.loc 1 1580 5 is_stmt 1 discriminator 1 view .LVU774
+ 2271              	.LBB622:
+ 2272              	.LBI622:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2273              		.loc 2 1202 31 discriminator 1 view .LVU775
+ 2274              	.LBB623:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2275              		.loc 2 1204 4 discriminator 1 view .LVU776
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2276              		.loc 2 1206 4 discriminator 1 view .LVU777
+ 2277 006c 0831     		adds	r1, r1, #8
+ 2278              	.LVL195:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2279              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU778
+ 2280              		.syntax unified
+ 2281              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2282 006e 41E80020 		strex r0, r2, [r1]
+ 2283              	@ 0 "" 2
+ 2284              	.LVL196:
+ 2285              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU779
+ 2286              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU780
+ 2287              		.thumb
+ 2288              		.syntax unified
+ 2289              	.LBE623:
+ 2290              	.LBE622:
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2291              		.loc 1 1580 5 discriminator 1 view .LVU781
+ 2292 0072 0028     		cmp	r0, #0
+ 2293 0074 F3D1     		bne	.L98
+ 2294              	.LVL197:
+ 2295              	.L99:
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2296              		.loc 1 1580 5 discriminator 1 view .LVU782
+ 2297              	.LBE619:
+1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2298              		.loc 1 1580 5 is_stmt 1 discriminator 1 view .LVU783
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2299              		.loc 1 1583 5 discriminator 1 view .LVU784
+ 2300              	.LBB624:
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2301              		.loc 1 1583 5 discriminator 1 view .LVU785
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2302              		.loc 1 1583 5 discriminator 1 view .LVU786
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2303              		.loc 1 1583 5 discriminator 1 view .LVU787
+ 2304 0076 1968     		ldr	r1, [r3]
+ 2305              	.LVL198:
+ARM GAS  /tmp/cceWHrnJ.s 			page 146
+
+
+ 2306              	.LBB625:
+ 2307              	.LBI625:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2308              		.loc 2 1151 31 discriminator 1 view .LVU788
+ 2309              	.LBB626:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2310              		.loc 2 1153 5 discriminator 1 view .LVU789
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2311              		.loc 2 1155 4 discriminator 1 view .LVU790
+ 2312 0078 01F10802 		add	r2, r1, #8
+ 2313              	.LVL199:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2314              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU791
+ 2315              		.syntax unified
+ 2316              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2317 007c 52E8002F 		ldrex r2, [r2]
+ 2318              	@ 0 "" 2
+ 2319              	.LVL200:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2320              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU792
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2321              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU793
+ 2322              		.thumb
+ 2323              		.syntax unified
+ 2324              	.LBE626:
+ 2325              	.LBE625:
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2326              		.loc 1 1583 5 discriminator 1 view .LVU794
+ 2327 0080 42F04002 		orr	r2, r2, #64
+ 2328              	.LVL201:
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2329              		.loc 1 1583 5 is_stmt 1 discriminator 1 view .LVU795
+ 2330              	.LBB627:
+ 2331              	.LBI627:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2332              		.loc 2 1202 31 discriminator 1 view .LVU796
+ 2333              	.LBB628:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2334              		.loc 2 1204 4 discriminator 1 view .LVU797
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2335              		.loc 2 1206 4 discriminator 1 view .LVU798
+ 2336 0084 0831     		adds	r1, r1, #8
+ 2337              	.LVL202:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2338              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU799
+ 2339              		.syntax unified
+ 2340              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2341 0086 41E80020 		strex r0, r2, [r1]
+ 2342              	@ 0 "" 2
+ 2343              	.LVL203:
+ 2344              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU800
+ 2345              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU801
+ 2346              		.thumb
+ 2347              		.syntax unified
+ 2348              	.LBE628:
+ 2349              	.LBE627:
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ARM GAS  /tmp/cceWHrnJ.s 			page 147
+
+
+ 2350              		.loc 1 1583 5 discriminator 1 view .LVU802
+ 2351 008a 0028     		cmp	r0, #0
+ 2352 008c F3D1     		bne	.L99
+ 2353 008e C7E7     		b	.L95
+ 2354              	.LVL204:
+ 2355              	.L100:
+1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2356              		.loc 1 1583 5 discriminator 1 view .LVU803
+ 2357              	.LBE624:
+1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2358              		.loc 1 1563 3 view .LVU804
+ 2359 0090 0220     		movs	r0, #2
+ 2360              	.LVL205:
+1589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2361              		.loc 1 1589 1 view .LVU805
+ 2362 0092 7047     		bx	lr
+ 2363              		.cfi_endproc
+ 2364              	.LFE343:
+ 2366              		.section	.text.HAL_UART_DMAStop,"ax",%progbits
+ 2367              		.align	1
+ 2368              		.global	HAL_UART_DMAStop
+ 2369              		.syntax unified
+ 2370              		.thumb
+ 2371              		.thumb_func
+ 2373              	HAL_UART_DMAStop:
+ 2374              	.LVL206:
+ 2375              	.LFB344:
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* The Lock is not implemented on this API to allow the user application
+ 2376              		.loc 1 1597 1 is_stmt 1 view -0
+ 2377              		.cfi_startproc
+ 2378              		@ args = 0, pretend = 0, frame = 0
+ 2379              		@ frame_needed = 0, uses_anonymous_args = 0
+1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* The Lock is not implemented on this API to allow the user application
+ 2380              		.loc 1 1597 1 is_stmt 0 view .LVU807
+ 2381 0000 38B5     		push	{r3, r4, r5, lr}
+ 2382              	.LCFI8:
+ 2383              		.cfi_def_cfa_offset 16
+ 2384              		.cfi_offset 3, -16
+ 2385              		.cfi_offset 4, -12
+ 2386              		.cfi_offset 5, -8
+ 2387              		.cfi_offset 14, -4
+ 2388 0002 0446     		mov	r4, r0
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef rxstate = huart->RxState;
+ 2389              		.loc 1 1605 3 is_stmt 1 view .LVU808
+1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef rxstate = huart->RxState;
+ 2390              		.loc 1 1605 31 is_stmt 0 view .LVU809
+ 2391 0004 D0F88420 		ldr	r2, [r0, #132]
+ 2392              	.LVL207:
+1606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2393              		.loc 1 1606 3 is_stmt 1 view .LVU810
+1606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2394              		.loc 1 1606 31 is_stmt 0 view .LVU811
+ 2395 0008 D0F88850 		ldr	r5, [r0, #136]
+ 2396              	.LVL208:
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+ 2397              		.loc 1 1609 3 is_stmt 1 view .LVU812
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+ARM GAS  /tmp/cceWHrnJ.s 			page 148
+
+
+ 2398              		.loc 1 1609 8 is_stmt 0 view .LVU813
+ 2399 000c 0368     		ldr	r3, [r0]
+ 2400 000e 9B68     		ldr	r3, [r3, #8]
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+ 2401              		.loc 1 1609 6 view .LVU814
+ 2402 0010 13F0800F 		tst	r3, #128
+ 2403 0014 01D0     		beq	.L103
+1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+ 2404              		.loc 1 1609 62 discriminator 1 view .LVU815
+ 2405 0016 212A     		cmp	r2, #33
+ 2406 0018 08D0     		beq	.L104
+ 2407              	.LVL209:
+ 2408              	.L103:
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+ 2409              		.loc 1 1633 3 is_stmt 1 view .LVU816
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+ 2410              		.loc 1 1633 8 is_stmt 0 view .LVU817
+ 2411 001a 2368     		ldr	r3, [r4]
+ 2412 001c 9B68     		ldr	r3, [r3, #8]
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+ 2413              		.loc 1 1633 6 view .LVU818
+ 2414 001e 13F0400F 		tst	r3, #64
+ 2415 0022 42D0     		beq	.L109
+1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+ 2416              		.loc 1 1633 62 discriminator 1 view .LVU819
+ 2417 0024 222D     		cmp	r5, #34
+ 2418 0026 20D0     		beq	.L107
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 2419              		.loc 1 1656 10 view .LVU820
+ 2420 0028 0020     		movs	r0, #0
+ 2421 002a 3FE0     		b	.L106
+ 2422              	.LVL210:
+ 2423              	.L104:
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2424              		.loc 1 1612 5 is_stmt 1 discriminator 1 view .LVU821
+ 2425              	.LBB629:
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2426              		.loc 1 1612 5 discriminator 1 view .LVU822
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2427              		.loc 1 1612 5 discriminator 1 view .LVU823
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2428              		.loc 1 1612 5 discriminator 1 view .LVU824
+ 2429 002c 2268     		ldr	r2, [r4]
+ 2430              	.LVL211:
+ 2431              	.LBB630:
+ 2432              	.LBI630:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2433              		.loc 2 1151 31 discriminator 1 view .LVU825
+ 2434              	.LBB631:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2435              		.loc 2 1153 5 discriminator 1 view .LVU826
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2436              		.loc 2 1155 4 discriminator 1 view .LVU827
+ 2437 002e 02F10803 		add	r3, r2, #8
+ 2438              	.LVL212:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2439              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU828
+ARM GAS  /tmp/cceWHrnJ.s 			page 149
+
+
+ 2440              		.syntax unified
+ 2441              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2442 0032 53E8003F 		ldrex r3, [r3]
+ 2443              	@ 0 "" 2
+ 2444              	.LVL213:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2445              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU829
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2446              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU830
+ 2447              		.thumb
+ 2448              		.syntax unified
+ 2449              	.LBE631:
+ 2450              	.LBE630:
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2451              		.loc 1 1612 5 discriminator 1 view .LVU831
+ 2452 0036 23F08003 		bic	r3, r3, #128
+ 2453              	.LVL214:
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2454              		.loc 1 1612 5 is_stmt 1 discriminator 1 view .LVU832
+ 2455              	.LBB632:
+ 2456              	.LBI632:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2457              		.loc 2 1202 31 discriminator 1 view .LVU833
+ 2458              	.LBB633:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2459              		.loc 2 1204 4 discriminator 1 view .LVU834
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2460              		.loc 2 1206 4 discriminator 1 view .LVU835
+ 2461 003a 0832     		adds	r2, r2, #8
+ 2462              	.LVL215:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2463              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU836
+ 2464              		.syntax unified
+ 2465              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2466 003c 42E80031 		strex r1, r3, [r2]
+ 2467              	@ 0 "" 2
+ 2468              	.LVL216:
+ 2469              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU837
+ 2470              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU838
+ 2471              		.thumb
+ 2472              		.syntax unified
+ 2473              	.LBE633:
+ 2474              	.LBE632:
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2475              		.loc 1 1612 5 discriminator 1 view .LVU839
+ 2476 0040 0029     		cmp	r1, #0
+ 2477 0042 F3D1     		bne	.L104
+ 2478              	.LBE629:
+1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2479              		.loc 1 1612 5 is_stmt 1 discriminator 2 view .LVU840
+1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 2480              		.loc 1 1615 5 discriminator 2 view .LVU841
+1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 2481              		.loc 1 1615 14 is_stmt 0 discriminator 2 view .LVU842
+ 2482 0044 A06F     		ldr	r0, [r4, #120]
+ 2483              	.LVL217:
+1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ARM GAS  /tmp/cceWHrnJ.s 			page 150
+
+
+ 2484              		.loc 1 1615 8 discriminator 2 view .LVU843
+ 2485 0046 10B1     		cbz	r0, .L105
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2486              		.loc 1 1617 7 is_stmt 1 view .LVU844
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2487              		.loc 1 1617 11 is_stmt 0 view .LVU845
+ 2488 0048 FFF7FEFF 		bl	HAL_DMA_Abort
+ 2489              	.LVL218:
+1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2490              		.loc 1 1617 10 view .LVU846
+ 2491 004c 18B9     		cbnz	r0, .L112
+ 2492              	.L105:
+1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2493              		.loc 1 1629 5 is_stmt 1 view .LVU847
+ 2494 004e 2046     		mov	r0, r4
+ 2495 0050 FFF7FEFF 		bl	UART_EndTxTransfer
+ 2496              	.LVL219:
+ 2497 0054 E1E7     		b	.L103
+ 2498              	.L112:
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 2499              		.loc 1 1619 9 view .LVU848
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 2500              		.loc 1 1619 13 is_stmt 0 view .LVU849
+ 2501 0056 A06F     		ldr	r0, [r4, #120]
+ 2502 0058 FFF7FEFF 		bl	HAL_DMA_GetError
+ 2503              	.LVL220:
+1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 2504              		.loc 1 1619 12 view .LVU850
+ 2505 005c 2028     		cmp	r0, #32
+ 2506 005e F6D1     		bne	.L105
+1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2507              		.loc 1 1622 11 is_stmt 1 view .LVU851
+1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2508              		.loc 1 1622 28 is_stmt 0 view .LVU852
+ 2509 0060 1023     		movs	r3, #16
+ 2510 0062 C4F88C30 		str	r3, [r4, #140]
+1624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 2511              		.loc 1 1624 11 is_stmt 1 view .LVU853
+1624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 2512              		.loc 1 1624 18 is_stmt 0 view .LVU854
+ 2513 0066 0320     		movs	r0, #3
+ 2514 0068 20E0     		b	.L106
+ 2515              	.LVL221:
+ 2516              	.L107:
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2517              		.loc 1 1636 5 is_stmt 1 discriminator 1 view .LVU855
+ 2518              	.LBB634:
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2519              		.loc 1 1636 5 discriminator 1 view .LVU856
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2520              		.loc 1 1636 5 discriminator 1 view .LVU857
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2521              		.loc 1 1636 5 discriminator 1 view .LVU858
+ 2522 006a 2268     		ldr	r2, [r4]
+ 2523              	.LVL222:
+ 2524              	.LBB635:
+ 2525              	.LBI635:
+ARM GAS  /tmp/cceWHrnJ.s 			page 151
+
+
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2526              		.loc 2 1151 31 discriminator 1 view .LVU859
+ 2527              	.LBB636:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2528              		.loc 2 1153 5 discriminator 1 view .LVU860
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2529              		.loc 2 1155 4 discriminator 1 view .LVU861
+ 2530 006c 02F10803 		add	r3, r2, #8
+ 2531              	.LVL223:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2532              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU862
+ 2533              		.syntax unified
+ 2534              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2535 0070 53E8003F 		ldrex r3, [r3]
+ 2536              	@ 0 "" 2
+ 2537              	.LVL224:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2538              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU863
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2539              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU864
+ 2540              		.thumb
+ 2541              		.syntax unified
+ 2542              	.LBE636:
+ 2543              	.LBE635:
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2544              		.loc 1 1636 5 discriminator 1 view .LVU865
+ 2545 0074 23F04003 		bic	r3, r3, #64
+ 2546              	.LVL225:
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2547              		.loc 1 1636 5 is_stmt 1 discriminator 1 view .LVU866
+ 2548              	.LBB637:
+ 2549              	.LBI637:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2550              		.loc 2 1202 31 discriminator 1 view .LVU867
+ 2551              	.LBB638:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2552              		.loc 2 1204 4 discriminator 1 view .LVU868
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2553              		.loc 2 1206 4 discriminator 1 view .LVU869
+ 2554 0078 0832     		adds	r2, r2, #8
+ 2555              	.LVL226:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2556              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU870
+ 2557              		.syntax unified
+ 2558              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2559 007a 42E80031 		strex r1, r3, [r2]
+ 2560              	@ 0 "" 2
+ 2561              	.LVL227:
+ 2562              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU871
+ 2563              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU872
+ 2564              		.thumb
+ 2565              		.syntax unified
+ 2566              	.LBE638:
+ 2567              	.LBE637:
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2568              		.loc 1 1636 5 discriminator 1 view .LVU873
+ 2569 007e 0029     		cmp	r1, #0
+ARM GAS  /tmp/cceWHrnJ.s 			page 152
+
+
+ 2570 0080 F3D1     		bne	.L107
+ 2571              	.LBE634:
+1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2572              		.loc 1 1636 5 is_stmt 1 discriminator 2 view .LVU874
+1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 2573              		.loc 1 1639 5 discriminator 2 view .LVU875
+1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 2574              		.loc 1 1639 14 is_stmt 0 discriminator 2 view .LVU876
+ 2575 0082 E06F     		ldr	r0, [r4, #124]
+1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 2576              		.loc 1 1639 8 discriminator 2 view .LVU877
+ 2577 0084 10B1     		cbz	r0, .L108
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2578              		.loc 1 1641 7 is_stmt 1 view .LVU878
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2579              		.loc 1 1641 11 is_stmt 0 view .LVU879
+ 2580 0086 FFF7FEFF 		bl	HAL_DMA_Abort
+ 2581              	.LVL228:
+1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2582              		.loc 1 1641 10 view .LVU880
+ 2583 008a 20B9     		cbnz	r0, .L113
+ 2584              	.L108:
+1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2585              		.loc 1 1653 5 is_stmt 1 view .LVU881
+ 2586 008c 2046     		mov	r0, r4
+ 2587 008e FFF7FEFF 		bl	UART_EndRxTransfer
+ 2588              	.LVL229:
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 2589              		.loc 1 1656 10 is_stmt 0 view .LVU882
+ 2590 0092 0020     		movs	r0, #0
+ 2591 0094 0AE0     		b	.L106
+ 2592              	.L113:
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 2593              		.loc 1 1643 9 is_stmt 1 view .LVU883
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 2594              		.loc 1 1643 13 is_stmt 0 view .LVU884
+ 2595 0096 E06F     		ldr	r0, [r4, #124]
+ 2596 0098 FFF7FEFF 		bl	HAL_DMA_GetError
+ 2597              	.LVL230:
+1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 2598              		.loc 1 1643 12 view .LVU885
+ 2599 009c 2028     		cmp	r0, #32
+ 2600 009e F5D1     		bne	.L108
+1646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2601              		.loc 1 1646 11 is_stmt 1 view .LVU886
+1646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2602              		.loc 1 1646 28 is_stmt 0 view .LVU887
+ 2603 00a0 1023     		movs	r3, #16
+ 2604 00a2 C4F88C30 		str	r3, [r4, #140]
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 2605              		.loc 1 1648 11 is_stmt 1 view .LVU888
+1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 2606              		.loc 1 1648 18 is_stmt 0 view .LVU889
+ 2607 00a6 0320     		movs	r0, #3
+ 2608 00a8 00E0     		b	.L106
+ 2609              	.LVL231:
+ 2610              	.L109:
+ARM GAS  /tmp/cceWHrnJ.s 			page 153
+
+
+1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 2611              		.loc 1 1656 10 view .LVU890
+ 2612 00aa 0020     		movs	r0, #0
+ 2613              	.L106:
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2614              		.loc 1 1657 1 view .LVU891
+ 2615 00ac 38BD     		pop	{r3, r4, r5, pc}
+1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2616              		.loc 1 1657 1 view .LVU892
+ 2617              		.cfi_endproc
+ 2618              	.LFE344:
+ 2620              		.section	.text.HAL_UART_Abort,"ax",%progbits
+ 2621              		.align	1
+ 2622              		.global	HAL_UART_Abort
+ 2623              		.syntax unified
+ 2624              		.thumb
+ 2625              		.thumb_func
+ 2627              	HAL_UART_Abort:
+ 2628              	.LVL232:
+ 2629              	.LFB345:
+1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interr
+ 2630              		.loc 1 1672 1 is_stmt 1 view -0
+ 2631              		.cfi_startproc
+ 2632              		@ args = 0, pretend = 0, frame = 0
+ 2633              		@ frame_needed = 0, uses_anonymous_args = 0
+1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interr
+ 2634              		.loc 1 1672 1 is_stmt 0 view .LVU894
+ 2635 0000 10B5     		push	{r4, lr}
+ 2636              	.LCFI9:
+ 2637              		.cfi_def_cfa_offset 8
+ 2638              		.cfi_offset 4, -8
+ 2639              		.cfi_offset 14, -4
+ 2640 0002 0446     		mov	r4, r0
+ 2641              	.L115:
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ 2642              		.loc 1 1674 3 is_stmt 1 discriminator 1 view .LVU895
+ 2643              	.LBB639:
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ 2644              		.loc 1 1674 3 discriminator 1 view .LVU896
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ 2645              		.loc 1 1674 3 discriminator 1 view .LVU897
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ 2646              		.loc 1 1674 3 discriminator 1 view .LVU898
+ 2647 0004 2268     		ldr	r2, [r4]
+ 2648              	.LVL233:
+ 2649              	.LBB640:
+ 2650              	.LBI640:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2651              		.loc 2 1151 31 discriminator 1 view .LVU899
+ 2652              	.LBB641:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2653              		.loc 2 1153 5 discriminator 1 view .LVU900
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2654              		.loc 2 1155 4 discriminator 1 view .LVU901
+ 2655              		.syntax unified
+ 2656              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2657 0006 52E8003F 		ldrex r3, [r2]
+ARM GAS  /tmp/cceWHrnJ.s 			page 154
+
+
+ 2658              	@ 0 "" 2
+ 2659              	.LVL234:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2660              		.loc 2 1156 4 discriminator 1 view .LVU902
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2661              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU903
+ 2662              		.thumb
+ 2663              		.syntax unified
+ 2664              	.LBE641:
+ 2665              	.LBE640:
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ 2666              		.loc 1 1674 3 discriminator 1 view .LVU904
+ 2667 000a 23F4F073 		bic	r3, r3, #480
+ 2668              	.LVL235:
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ 2669              		.loc 1 1674 3 is_stmt 1 discriminator 1 view .LVU905
+ 2670              	.LBB642:
+ 2671              	.LBI642:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2672              		.loc 2 1202 31 discriminator 1 view .LVU906
+ 2673              	.LBB643:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2674              		.loc 2 1204 4 discriminator 1 view .LVU907
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2675              		.loc 2 1206 4 discriminator 1 view .LVU908
+ 2676              		.syntax unified
+ 2677              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2678 000e 42E80031 		strex r1, r3, [r2]
+ 2679              	@ 0 "" 2
+ 2680              	.LVL236:
+ 2681              		.loc 2 1207 4 discriminator 1 view .LVU909
+ 2682              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU910
+ 2683              		.thumb
+ 2684              		.syntax unified
+ 2685              	.LBE643:
+ 2686              	.LBE642:
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ 2687              		.loc 1 1674 3 discriminator 1 view .LVU911
+ 2688 0012 0029     		cmp	r1, #0
+ 2689 0014 F6D1     		bne	.L115
+ 2690              	.LVL237:
+ 2691              	.L116:
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ 2692              		.loc 1 1674 3 discriminator 1 view .LVU912
+ 2693              	.LBE639:
+1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ 2694              		.loc 1 1674 3 is_stmt 1 discriminator 1 view .LVU913
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2695              		.loc 1 1676 3 discriminator 1 view .LVU914
+ 2696              	.LBB644:
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2697              		.loc 1 1676 3 discriminator 1 view .LVU915
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2698              		.loc 1 1676 3 discriminator 1 view .LVU916
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2699              		.loc 1 1676 3 discriminator 1 view .LVU917
+ 2700 0016 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/cceWHrnJ.s 			page 155
+
+
+ 2701              	.LVL238:
+ 2702              	.LBB645:
+ 2703              	.LBI645:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2704              		.loc 2 1151 31 discriminator 1 view .LVU918
+ 2705              	.LBB646:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2706              		.loc 2 1153 5 discriminator 1 view .LVU919
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2707              		.loc 2 1155 4 discriminator 1 view .LVU920
+ 2708 0018 02F10803 		add	r3, r2, #8
+ 2709              	.LVL239:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2710              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU921
+ 2711              		.syntax unified
+ 2712              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2713 001c 53E8003F 		ldrex r3, [r3]
+ 2714              	@ 0 "" 2
+ 2715              	.LVL240:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2716              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU922
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2717              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU923
+ 2718              		.thumb
+ 2719              		.syntax unified
+ 2720              	.LBE646:
+ 2721              	.LBE645:
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2722              		.loc 1 1676 3 discriminator 1 view .LVU924
+ 2723 0020 23F08453 		bic	r3, r3, #276824064
+ 2724 0024 23F00103 		bic	r3, r3, #1
+ 2725              	.LVL241:
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2726              		.loc 1 1676 3 is_stmt 1 discriminator 1 view .LVU925
+ 2727              	.LBB647:
+ 2728              	.LBI647:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2729              		.loc 2 1202 31 discriminator 1 view .LVU926
+ 2730              	.LBB648:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2731              		.loc 2 1204 4 discriminator 1 view .LVU927
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2732              		.loc 2 1206 4 discriminator 1 view .LVU928
+ 2733 0028 0832     		adds	r2, r2, #8
+ 2734              	.LVL242:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2735              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU929
+ 2736              		.syntax unified
+ 2737              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2738 002a 42E80031 		strex r1, r3, [r2]
+ 2739              	@ 0 "" 2
+ 2740              	.LVL243:
+ 2741              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU930
+ 2742              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU931
+ 2743              		.thumb
+ 2744              		.syntax unified
+ 2745              	.LBE648:
+ARM GAS  /tmp/cceWHrnJ.s 			page 156
+
+
+ 2746              	.LBE647:
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2747              		.loc 1 1676 3 discriminator 1 view .LVU932
+ 2748 002e 0029     		cmp	r1, #0
+ 2749 0030 F1D1     		bne	.L116
+ 2750              	.LBE644:
+1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2751              		.loc 1 1676 3 is_stmt 1 discriminator 2 view .LVU933
+1679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2752              		.loc 1 1679 3 discriminator 2 view .LVU934
+1679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2753              		.loc 1 1679 12 is_stmt 0 discriminator 2 view .LVU935
+ 2754 0032 E36E     		ldr	r3, [r4, #108]
+ 2755              	.LVL244:
+1679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2756              		.loc 1 1679 6 discriminator 2 view .LVU936
+ 2757 0034 012B     		cmp	r3, #1
+ 2758 0036 4DD0     		beq	.L118
+ 2759              	.L117:
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2760              		.loc 1 1681 5 is_stmt 1 discriminator 2 view .LVU937
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2761              		.loc 1 1685 3 discriminator 2 view .LVU938
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2762              		.loc 1 1685 7 is_stmt 0 discriminator 2 view .LVU939
+ 2763 0038 2368     		ldr	r3, [r4]
+ 2764 003a 9B68     		ldr	r3, [r3, #8]
+1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2765              		.loc 1 1685 6 discriminator 2 view .LVU940
+ 2766 003c 13F0800F 		tst	r3, #128
+ 2767 0040 14D0     		beq	.L119
+ 2768              	.L120:
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2769              		.loc 1 1688 5 is_stmt 1 discriminator 1 view .LVU941
+ 2770              	.LBB649:
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2771              		.loc 1 1688 5 discriminator 1 view .LVU942
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2772              		.loc 1 1688 5 discriminator 1 view .LVU943
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2773              		.loc 1 1688 5 discriminator 1 view .LVU944
+ 2774 0042 2268     		ldr	r2, [r4]
+ 2775              	.LVL245:
+ 2776              	.LBB650:
+ 2777              	.LBI650:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2778              		.loc 2 1151 31 discriminator 1 view .LVU945
+ 2779              	.LBB651:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2780              		.loc 2 1153 5 discriminator 1 view .LVU946
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2781              		.loc 2 1155 4 discriminator 1 view .LVU947
+ 2782 0044 02F10803 		add	r3, r2, #8
+ 2783              	.LVL246:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2784              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU948
+ 2785              		.syntax unified
+ARM GAS  /tmp/cceWHrnJ.s 			page 157
+
+
+ 2786              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2787 0048 53E8003F 		ldrex r3, [r3]
+ 2788              	@ 0 "" 2
+ 2789              	.LVL247:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2790              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU949
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2791              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU950
+ 2792              		.thumb
+ 2793              		.syntax unified
+ 2794              	.LBE651:
+ 2795              	.LBE650:
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2796              		.loc 1 1688 5 discriminator 1 view .LVU951
+ 2797 004c 23F08003 		bic	r3, r3, #128
+ 2798              	.LVL248:
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2799              		.loc 1 1688 5 is_stmt 1 discriminator 1 view .LVU952
+ 2800              	.LBB652:
+ 2801              	.LBI652:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2802              		.loc 2 1202 31 discriminator 1 view .LVU953
+ 2803              	.LBB653:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2804              		.loc 2 1204 4 discriminator 1 view .LVU954
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2805              		.loc 2 1206 4 discriminator 1 view .LVU955
+ 2806 0050 0832     		adds	r2, r2, #8
+ 2807              	.LVL249:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2808              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU956
+ 2809              		.syntax unified
+ 2810              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2811 0052 42E80031 		strex r1, r3, [r2]
+ 2812              	@ 0 "" 2
+ 2813              	.LVL250:
+ 2814              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU957
+ 2815              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU958
+ 2816              		.thumb
+ 2817              		.syntax unified
+ 2818              	.LBE653:
+ 2819              	.LBE652:
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2820              		.loc 1 1688 5 discriminator 1 view .LVU959
+ 2821 0056 0029     		cmp	r1, #0
+ 2822 0058 F3D1     		bne	.L120
+ 2823              	.LBE649:
+1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2824              		.loc 1 1688 5 is_stmt 1 discriminator 2 view .LVU960
+1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 2825              		.loc 1 1691 5 discriminator 2 view .LVU961
+1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 2826              		.loc 1 1691 14 is_stmt 0 discriminator 2 view .LVU962
+ 2827 005a A36F     		ldr	r3, [r4, #120]
+ 2828              	.LVL251:
+1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 2829              		.loc 1 1691 8 discriminator 2 view .LVU963
+ARM GAS  /tmp/cceWHrnJ.s 			page 158
+
+
+ 2830 005c 33B1     		cbz	r3, .L119
+1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2831              		.loc 1 1695 7 is_stmt 1 view .LVU964
+1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2832              		.loc 1 1695 40 is_stmt 0 view .LVU965
+ 2833 005e 0022     		movs	r2, #0
+ 2834 0060 9A63     		str	r2, [r3, #56]
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2835              		.loc 1 1697 7 is_stmt 1 view .LVU966
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2836              		.loc 1 1697 11 is_stmt 0 view .LVU967
+ 2837 0062 A06F     		ldr	r0, [r4, #120]
+ 2838              	.LVL252:
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2839              		.loc 1 1697 11 view .LVU968
+ 2840 0064 FFF7FEFF 		bl	HAL_DMA_Abort
+ 2841              	.LVL253:
+1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2842              		.loc 1 1697 10 view .LVU969
+ 2843 0068 0028     		cmp	r0, #0
+ 2844 006a 3DD1     		bne	.L126
+ 2845              	.LVL254:
+ 2846              	.L119:
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2847              		.loc 1 1711 3 is_stmt 1 view .LVU970
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2848              		.loc 1 1711 7 is_stmt 0 view .LVU971
+ 2849 006c 2368     		ldr	r3, [r4]
+ 2850 006e 9B68     		ldr	r3, [r3, #8]
+1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2851              		.loc 1 1711 6 view .LVU972
+ 2852 0070 13F0400F 		tst	r3, #64
+ 2853 0074 13D0     		beq	.L122
+ 2854              	.L123:
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2855              		.loc 1 1714 5 is_stmt 1 discriminator 1 view .LVU973
+ 2856              	.LBB654:
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2857              		.loc 1 1714 5 discriminator 1 view .LVU974
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2858              		.loc 1 1714 5 discriminator 1 view .LVU975
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2859              		.loc 1 1714 5 discriminator 1 view .LVU976
+ 2860 0076 2268     		ldr	r2, [r4]
+ 2861              	.LVL255:
+ 2862              	.LBB655:
+ 2863              	.LBI655:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2864              		.loc 2 1151 31 discriminator 1 view .LVU977
+ 2865              	.LBB656:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2866              		.loc 2 1153 5 discriminator 1 view .LVU978
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2867              		.loc 2 1155 4 discriminator 1 view .LVU979
+ 2868 0078 02F10803 		add	r3, r2, #8
+ 2869              	.LVL256:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ARM GAS  /tmp/cceWHrnJ.s 			page 159
+
+
+ 2870              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU980
+ 2871              		.syntax unified
+ 2872              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2873 007c 53E8003F 		ldrex r3, [r3]
+ 2874              	@ 0 "" 2
+ 2875              	.LVL257:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2876              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU981
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2877              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU982
+ 2878              		.thumb
+ 2879              		.syntax unified
+ 2880              	.LBE656:
+ 2881              	.LBE655:
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2882              		.loc 1 1714 5 discriminator 1 view .LVU983
+ 2883 0080 23F04003 		bic	r3, r3, #64
+ 2884              	.LVL258:
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2885              		.loc 1 1714 5 is_stmt 1 discriminator 1 view .LVU984
+ 2886              	.LBB657:
+ 2887              	.LBI657:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2888              		.loc 2 1202 31 discriminator 1 view .LVU985
+ 2889              	.LBB658:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2890              		.loc 2 1204 4 discriminator 1 view .LVU986
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2891              		.loc 2 1206 4 discriminator 1 view .LVU987
+ 2892 0084 0832     		adds	r2, r2, #8
+ 2893              	.LVL259:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2894              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU988
+ 2895              		.syntax unified
+ 2896              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2897 0086 42E80031 		strex r1, r3, [r2]
+ 2898              	@ 0 "" 2
+ 2899              	.LVL260:
+ 2900              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU989
+ 2901              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU990
+ 2902              		.thumb
+ 2903              		.syntax unified
+ 2904              	.LBE658:
+ 2905              	.LBE657:
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2906              		.loc 1 1714 5 discriminator 1 view .LVU991
+ 2907 008a 0029     		cmp	r1, #0
+ 2908 008c F3D1     		bne	.L123
+ 2909              	.LBE654:
+1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2910              		.loc 1 1714 5 is_stmt 1 discriminator 2 view .LVU992
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 2911              		.loc 1 1717 5 discriminator 2 view .LVU993
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 2912              		.loc 1 1717 14 is_stmt 0 discriminator 2 view .LVU994
+ 2913 008e E36F     		ldr	r3, [r4, #124]
+ 2914              	.LVL261:
+ARM GAS  /tmp/cceWHrnJ.s 			page 160
+
+
+1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 2915              		.loc 1 1717 8 discriminator 2 view .LVU995
+ 2916 0090 2BB1     		cbz	r3, .L122
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2917              		.loc 1 1721 7 is_stmt 1 view .LVU996
+1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2918              		.loc 1 1721 40 is_stmt 0 view .LVU997
+ 2919 0092 0022     		movs	r2, #0
+ 2920 0094 9A63     		str	r2, [r3, #56]
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2921              		.loc 1 1723 7 is_stmt 1 view .LVU998
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2922              		.loc 1 1723 11 is_stmt 0 view .LVU999
+ 2923 0096 E06F     		ldr	r0, [r4, #124]
+ 2924 0098 FFF7FEFF 		bl	HAL_DMA_Abort
+ 2925              	.LVL262:
+1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 2926              		.loc 1 1723 10 view .LVU1000
+ 2927 009c 70BB     		cbnz	r0, .L127
+ 2928              	.LVL263:
+ 2929              	.L122:
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+ 2930              		.loc 1 1737 3 is_stmt 1 view .LVU1001
+1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+ 2931              		.loc 1 1737 22 is_stmt 0 view .LVU1002
+ 2932 009e 0023     		movs	r3, #0
+ 2933 00a0 A4F85630 		strh	r3, [r4, #86]	@ movhi
+1738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2934              		.loc 1 1738 3 is_stmt 1 view .LVU1003
+1738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2935              		.loc 1 1738 22 is_stmt 0 view .LVU1004
+ 2936 00a4 A4F85E30 		strh	r3, [r4, #94]	@ movhi
+1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2937              		.loc 1 1741 3 is_stmt 1 view .LVU1005
+ 2938 00a8 2368     		ldr	r3, [r4]
+ 2939 00aa 0F22     		movs	r2, #15
+ 2940 00ac 1A62     		str	r2, [r3, #32]
+1744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2941              		.loc 1 1744 3 view .LVU1006
+1744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2942              		.loc 1 1744 12 is_stmt 0 view .LVU1007
+ 2943 00ae 636E     		ldr	r3, [r4, #100]
+1744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 2944              		.loc 1 1744 6 view .LVU1008
+ 2945 00b0 B3F1005F 		cmp	r3, #536870912
+ 2946 00b4 2CD0     		beq	.L128
+ 2947              	.L124:
+1750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2948              		.loc 1 1750 3 is_stmt 1 view .LVU1009
+ 2949 00b6 2268     		ldr	r2, [r4]
+ 2950 00b8 9369     		ldr	r3, [r2, #24]
+ 2951 00ba 43F00803 		orr	r3, r3, #8
+ 2952 00be 9361     		str	r3, [r2, #24]
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 2953              		.loc 1 1753 3 view .LVU1010
+1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 2954              		.loc 1 1753 18 is_stmt 0 view .LVU1011
+ARM GAS  /tmp/cceWHrnJ.s 			page 161
+
+
+ 2955 00c0 2023     		movs	r3, #32
+ 2956 00c2 C4F88430 		str	r3, [r4, #132]
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 2957              		.loc 1 1754 3 is_stmt 1 view .LVU1012
+1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 2958              		.loc 1 1754 18 is_stmt 0 view .LVU1013
+ 2959 00c6 C4F88830 		str	r3, [r4, #136]
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2960              		.loc 1 1755 3 is_stmt 1 view .LVU1014
+1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2961              		.loc 1 1755 24 is_stmt 0 view .LVU1015
+ 2962 00ca 0020     		movs	r0, #0
+ 2963 00cc E066     		str	r0, [r4, #108]
+1757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2964              		.loc 1 1757 3 is_stmt 1 view .LVU1016
+1757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2965              		.loc 1 1757 20 is_stmt 0 view .LVU1017
+ 2966 00ce C4F88C00 		str	r0, [r4, #140]
+1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 2967              		.loc 1 1759 3 is_stmt 1 view .LVU1018
+ 2968              	.L121:
+1760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 2969              		.loc 1 1760 1 is_stmt 0 view .LVU1019
+ 2970 00d2 10BD     		pop	{r4, pc}
+ 2971              	.LVL264:
+ 2972              	.L118:
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2973              		.loc 1 1681 5 is_stmt 1 discriminator 1 view .LVU1020
+ 2974              	.LBB659:
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2975              		.loc 1 1681 5 discriminator 1 view .LVU1021
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2976              		.loc 1 1681 5 discriminator 1 view .LVU1022
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2977              		.loc 1 1681 5 discriminator 1 view .LVU1023
+ 2978 00d4 2268     		ldr	r2, [r4]
+ 2979              	.LVL265:
+ 2980              	.LBB660:
+ 2981              	.LBI660:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 2982              		.loc 2 1151 31 discriminator 1 view .LVU1024
+ 2983              	.LBB661:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 2984              		.loc 2 1153 5 discriminator 1 view .LVU1025
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 2985              		.loc 2 1155 4 discriminator 1 view .LVU1026
+ 2986              		.syntax unified
+ 2987              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2988 00d6 52E8003F 		ldrex r3, [r2]
+ 2989              	@ 0 "" 2
+ 2990              	.LVL266:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2991              		.loc 2 1156 4 discriminator 1 view .LVU1027
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 2992              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1028
+ 2993              		.thumb
+ 2994              		.syntax unified
+ARM GAS  /tmp/cceWHrnJ.s 			page 162
+
+
+ 2995              	.LBE661:
+ 2996              	.LBE660:
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 2997              		.loc 1 1681 5 discriminator 1 view .LVU1029
+ 2998 00da 23F01003 		bic	r3, r3, #16
+ 2999              	.LVL267:
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3000              		.loc 1 1681 5 is_stmt 1 discriminator 1 view .LVU1030
+ 3001              	.LBB662:
+ 3002              	.LBI662:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3003              		.loc 2 1202 31 discriminator 1 view .LVU1031
+ 3004              	.LBB663:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3005              		.loc 2 1204 4 discriminator 1 view .LVU1032
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3006              		.loc 2 1206 4 discriminator 1 view .LVU1033
+ 3007              		.syntax unified
+ 3008              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3009 00de 42E80031 		strex r1, r3, [r2]
+ 3010              	@ 0 "" 2
+ 3011              	.LVL268:
+ 3012              		.loc 2 1207 4 discriminator 1 view .LVU1034
+ 3013              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1035
+ 3014              		.thumb
+ 3015              		.syntax unified
+ 3016              	.LBE663:
+ 3017              	.LBE662:
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3018              		.loc 1 1681 5 discriminator 1 view .LVU1036
+ 3019 00e2 0029     		cmp	r1, #0
+ 3020 00e4 F6D1     		bne	.L118
+ 3021 00e6 A7E7     		b	.L117
+ 3022              	.LVL269:
+ 3023              	.L126:
+1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3024              		.loc 1 1681 5 discriminator 1 view .LVU1037
+ 3025              	.LBE659:
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 3026              		.loc 1 1699 9 is_stmt 1 view .LVU1038
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 3027              		.loc 1 1699 13 is_stmt 0 view .LVU1039
+ 3028 00e8 A06F     		ldr	r0, [r4, #120]
+ 3029 00ea FFF7FEFF 		bl	HAL_DMA_GetError
+ 3030              	.LVL270:
+1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 3031              		.loc 1 1699 12 view .LVU1040
+ 3032 00ee 2028     		cmp	r0, #32
+ 3033 00f0 BCD1     		bne	.L119
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3034              		.loc 1 1702 11 is_stmt 1 view .LVU1041
+1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3035              		.loc 1 1702 28 is_stmt 0 view .LVU1042
+ 3036 00f2 1023     		movs	r3, #16
+ 3037 00f4 C4F88C30 		str	r3, [r4, #140]
+1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 3038              		.loc 1 1704 11 is_stmt 1 view .LVU1043
+ARM GAS  /tmp/cceWHrnJ.s 			page 163
+
+
+1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 3039              		.loc 1 1704 18 is_stmt 0 view .LVU1044
+ 3040 00f8 0320     		movs	r0, #3
+ 3041 00fa EAE7     		b	.L121
+ 3042              	.LVL271:
+ 3043              	.L127:
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 3044              		.loc 1 1725 9 is_stmt 1 view .LVU1045
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 3045              		.loc 1 1725 13 is_stmt 0 view .LVU1046
+ 3046 00fc E06F     		ldr	r0, [r4, #124]
+ 3047 00fe FFF7FEFF 		bl	HAL_DMA_GetError
+ 3048              	.LVL272:
+1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 3049              		.loc 1 1725 12 view .LVU1047
+ 3050 0102 2028     		cmp	r0, #32
+ 3051 0104 CBD1     		bne	.L122
+1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3052              		.loc 1 1728 11 is_stmt 1 view .LVU1048
+1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3053              		.loc 1 1728 28 is_stmt 0 view .LVU1049
+ 3054 0106 1023     		movs	r3, #16
+ 3055 0108 C4F88C30 		str	r3, [r4, #140]
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 3056              		.loc 1 1730 11 is_stmt 1 view .LVU1050
+1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 3057              		.loc 1 1730 18 is_stmt 0 view .LVU1051
+ 3058 010c 0320     		movs	r0, #3
+ 3059 010e E0E7     		b	.L121
+ 3060              	.LVL273:
+ 3061              	.L128:
+1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3062              		.loc 1 1746 5 is_stmt 1 view .LVU1052
+ 3063 0110 2268     		ldr	r2, [r4]
+ 3064 0112 9369     		ldr	r3, [r2, #24]
+ 3065 0114 43F01003 		orr	r3, r3, #16
+ 3066 0118 9361     		str	r3, [r2, #24]
+ 3067 011a CCE7     		b	.L124
+ 3068              		.cfi_endproc
+ 3069              	.LFE345:
+ 3071              		.section	.text.HAL_UART_AbortTransmit,"ax",%progbits
+ 3072              		.align	1
+ 3073              		.global	HAL_UART_AbortTransmit
+ 3074              		.syntax unified
+ 3075              		.thumb
+ 3076              		.thumb_func
+ 3078              	HAL_UART_AbortTransmit:
+ 3079              	.LVL274:
+ 3080              	.LFB346:
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable TCIE, TXEIE and TXFTIE interrupts */
+ 3081              		.loc 1 1775 1 view -0
+ 3082              		.cfi_startproc
+ 3083              		@ args = 0, pretend = 0, frame = 0
+ 3084              		@ frame_needed = 0, uses_anonymous_args = 0
+1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable TCIE, TXEIE and TXFTIE interrupts */
+ 3085              		.loc 1 1775 1 is_stmt 0 view .LVU1054
+ 3086 0000 10B5     		push	{r4, lr}
+ARM GAS  /tmp/cceWHrnJ.s 			page 164
+
+
+ 3087              	.LCFI10:
+ 3088              		.cfi_def_cfa_offset 8
+ 3089              		.cfi_offset 4, -8
+ 3090              		.cfi_offset 14, -4
+ 3091 0002 0446     		mov	r4, r0
+ 3092              	.L130:
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 3093              		.loc 1 1777 3 is_stmt 1 discriminator 1 view .LVU1055
+ 3094              	.LBB664:
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 3095              		.loc 1 1777 3 discriminator 1 view .LVU1056
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 3096              		.loc 1 1777 3 discriminator 1 view .LVU1057
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 3097              		.loc 1 1777 3 discriminator 1 view .LVU1058
+ 3098 0004 2268     		ldr	r2, [r4]
+ 3099              	.LVL275:
+ 3100              	.LBB665:
+ 3101              	.LBI665:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3102              		.loc 2 1151 31 discriminator 1 view .LVU1059
+ 3103              	.LBB666:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3104              		.loc 2 1153 5 discriminator 1 view .LVU1060
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3105              		.loc 2 1155 4 discriminator 1 view .LVU1061
+ 3106              		.syntax unified
+ 3107              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3108 0006 52E8003F 		ldrex r3, [r2]
+ 3109              	@ 0 "" 2
+ 3110              	.LVL276:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3111              		.loc 2 1156 4 discriminator 1 view .LVU1062
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3112              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1063
+ 3113              		.thumb
+ 3114              		.syntax unified
+ 3115              	.LBE666:
+ 3116              	.LBE665:
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 3117              		.loc 1 1777 3 discriminator 1 view .LVU1064
+ 3118 000a 23F0C003 		bic	r3, r3, #192
+ 3119              	.LVL277:
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 3120              		.loc 1 1777 3 is_stmt 1 discriminator 1 view .LVU1065
+ 3121              	.LBB667:
+ 3122              	.LBI667:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3123              		.loc 2 1202 31 discriminator 1 view .LVU1066
+ 3124              	.LBB668:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3125              		.loc 2 1204 4 discriminator 1 view .LVU1067
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3126              		.loc 2 1206 4 discriminator 1 view .LVU1068
+ 3127              		.syntax unified
+ 3128              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3129 000e 42E80031 		strex r1, r3, [r2]
+ARM GAS  /tmp/cceWHrnJ.s 			page 165
+
+
+ 3130              	@ 0 "" 2
+ 3131              	.LVL278:
+ 3132              		.loc 2 1207 4 discriminator 1 view .LVU1069
+ 3133              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1070
+ 3134              		.thumb
+ 3135              		.syntax unified
+ 3136              	.LBE668:
+ 3137              	.LBE667:
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 3138              		.loc 1 1777 3 discriminator 1 view .LVU1071
+ 3139 0012 0029     		cmp	r1, #0
+ 3140 0014 F6D1     		bne	.L130
+ 3141              	.LVL279:
+ 3142              	.L131:
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 3143              		.loc 1 1777 3 discriminator 1 view .LVU1072
+ 3144              	.LBE664:
+1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 3145              		.loc 1 1777 3 is_stmt 1 discriminator 1 view .LVU1073
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3146              		.loc 1 1778 3 discriminator 1 view .LVU1074
+ 3147              	.LBB669:
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3148              		.loc 1 1778 3 discriminator 1 view .LVU1075
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3149              		.loc 1 1778 3 discriminator 1 view .LVU1076
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3150              		.loc 1 1778 3 discriminator 1 view .LVU1077
+ 3151 0016 2268     		ldr	r2, [r4]
+ 3152              	.LVL280:
+ 3153              	.LBB670:
+ 3154              	.LBI670:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3155              		.loc 2 1151 31 discriminator 1 view .LVU1078
+ 3156              	.LBB671:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3157              		.loc 2 1153 5 discriminator 1 view .LVU1079
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3158              		.loc 2 1155 4 discriminator 1 view .LVU1080
+ 3159 0018 02F10803 		add	r3, r2, #8
+ 3160              	.LVL281:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3161              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU1081
+ 3162              		.syntax unified
+ 3163              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3164 001c 53E8003F 		ldrex r3, [r3]
+ 3165              	@ 0 "" 2
+ 3166              	.LVL282:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3167              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU1082
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3168              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1083
+ 3169              		.thumb
+ 3170              		.syntax unified
+ 3171              	.LBE671:
+ 3172              	.LBE670:
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 166
+
+
+ 3173              		.loc 1 1778 3 discriminator 1 view .LVU1084
+ 3174 0020 23F40003 		bic	r3, r3, #8388608
+ 3175              	.LVL283:
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3176              		.loc 1 1778 3 is_stmt 1 discriminator 1 view .LVU1085
+ 3177              	.LBB672:
+ 3178              	.LBI672:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3179              		.loc 2 1202 31 discriminator 1 view .LVU1086
+ 3180              	.LBB673:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3181              		.loc 2 1204 4 discriminator 1 view .LVU1087
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3182              		.loc 2 1206 4 discriminator 1 view .LVU1088
+ 3183 0024 0832     		adds	r2, r2, #8
+ 3184              	.LVL284:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3185              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU1089
+ 3186              		.syntax unified
+ 3187              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3188 0026 42E80031 		strex r1, r3, [r2]
+ 3189              	@ 0 "" 2
+ 3190              	.LVL285:
+ 3191              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU1090
+ 3192              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1091
+ 3193              		.thumb
+ 3194              		.syntax unified
+ 3195              	.LBE673:
+ 3196              	.LBE672:
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3197              		.loc 1 1778 3 discriminator 1 view .LVU1092
+ 3198 002a 0029     		cmp	r1, #0
+ 3199 002c F3D1     		bne	.L131
+ 3200              	.LBE669:
+1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3201              		.loc 1 1778 3 is_stmt 1 discriminator 2 view .LVU1093
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3202              		.loc 1 1781 3 discriminator 2 view .LVU1094
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3203              		.loc 1 1781 7 is_stmt 0 discriminator 2 view .LVU1095
+ 3204 002e 2368     		ldr	r3, [r4]
+ 3205              	.LVL286:
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3206              		.loc 1 1781 7 discriminator 2 view .LVU1096
+ 3207 0030 9B68     		ldr	r3, [r3, #8]
+1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3208              		.loc 1 1781 6 discriminator 2 view .LVU1097
+ 3209 0032 13F0800F 		tst	r3, #128
+ 3210 0036 13D0     		beq	.L132
+ 3211              	.L133:
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3212              		.loc 1 1784 5 is_stmt 1 discriminator 1 view .LVU1098
+ 3213              	.LBB674:
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3214              		.loc 1 1784 5 discriminator 1 view .LVU1099
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3215              		.loc 1 1784 5 discriminator 1 view .LVU1100
+ARM GAS  /tmp/cceWHrnJ.s 			page 167
+
+
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3216              		.loc 1 1784 5 discriminator 1 view .LVU1101
+ 3217 0038 2268     		ldr	r2, [r4]
+ 3218              	.LVL287:
+ 3219              	.LBB675:
+ 3220              	.LBI675:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3221              		.loc 2 1151 31 discriminator 1 view .LVU1102
+ 3222              	.LBB676:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3223              		.loc 2 1153 5 discriminator 1 view .LVU1103
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3224              		.loc 2 1155 4 discriminator 1 view .LVU1104
+ 3225 003a 02F10803 		add	r3, r2, #8
+ 3226              	.LVL288:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3227              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU1105
+ 3228              		.syntax unified
+ 3229              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3230 003e 53E8003F 		ldrex r3, [r3]
+ 3231              	@ 0 "" 2
+ 3232              	.LVL289:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3233              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU1106
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3234              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1107
+ 3235              		.thumb
+ 3236              		.syntax unified
+ 3237              	.LBE676:
+ 3238              	.LBE675:
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3239              		.loc 1 1784 5 discriminator 1 view .LVU1108
+ 3240 0042 23F08003 		bic	r3, r3, #128
+ 3241              	.LVL290:
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3242              		.loc 1 1784 5 is_stmt 1 discriminator 1 view .LVU1109
+ 3243              	.LBB677:
+ 3244              	.LBI677:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3245              		.loc 2 1202 31 discriminator 1 view .LVU1110
+ 3246              	.LBB678:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3247              		.loc 2 1204 4 discriminator 1 view .LVU1111
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3248              		.loc 2 1206 4 discriminator 1 view .LVU1112
+ 3249 0046 0832     		adds	r2, r2, #8
+ 3250              	.LVL291:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3251              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU1113
+ 3252              		.syntax unified
+ 3253              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3254 0048 42E80031 		strex r1, r3, [r2]
+ 3255              	@ 0 "" 2
+ 3256              	.LVL292:
+ 3257              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU1114
+ 3258              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1115
+ 3259              		.thumb
+ARM GAS  /tmp/cceWHrnJ.s 			page 168
+
+
+ 3260              		.syntax unified
+ 3261              	.LBE678:
+ 3262              	.LBE677:
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3263              		.loc 1 1784 5 discriminator 1 view .LVU1116
+ 3264 004c 0029     		cmp	r1, #0
+ 3265 004e F3D1     		bne	.L133
+ 3266              	.LBE674:
+1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3267              		.loc 1 1784 5 is_stmt 1 discriminator 2 view .LVU1117
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 3268              		.loc 1 1787 5 discriminator 2 view .LVU1118
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 3269              		.loc 1 1787 14 is_stmt 0 discriminator 2 view .LVU1119
+ 3270 0050 A36F     		ldr	r3, [r4, #120]
+ 3271              	.LVL293:
+1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 3272              		.loc 1 1787 8 discriminator 2 view .LVU1120
+ 3273 0052 2BB1     		cbz	r3, .L132
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3274              		.loc 1 1791 7 is_stmt 1 view .LVU1121
+1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3275              		.loc 1 1791 40 is_stmt 0 view .LVU1122
+ 3276 0054 0022     		movs	r2, #0
+ 3277 0056 9A63     		str	r2, [r3, #56]
+1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 3278              		.loc 1 1793 7 is_stmt 1 view .LVU1123
+1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 3279              		.loc 1 1793 11 is_stmt 0 view .LVU1124
+ 3280 0058 A06F     		ldr	r0, [r4, #120]
+ 3281              	.LVL294:
+1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 3282              		.loc 1 1793 11 view .LVU1125
+ 3283 005a FFF7FEFF 		bl	HAL_DMA_Abort
+ 3284              	.LVL295:
+1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 3285              		.loc 1 1793 10 view .LVU1126
+ 3286 005e 58B9     		cbnz	r0, .L137
+ 3287              	.LVL296:
+ 3288              	.L132:
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3289              		.loc 1 1807 3 is_stmt 1 view .LVU1127
+1807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3290              		.loc 1 1807 22 is_stmt 0 view .LVU1128
+ 3291 0060 0023     		movs	r3, #0
+ 3292 0062 A4F85630 		strh	r3, [r4, #86]	@ movhi
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3293              		.loc 1 1810 3 is_stmt 1 view .LVU1129
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3294              		.loc 1 1810 12 is_stmt 0 view .LVU1130
+ 3295 0066 636E     		ldr	r3, [r4, #100]
+1810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3296              		.loc 1 1810 6 view .LVU1131
+ 3297 0068 B3F1005F 		cmp	r3, #536870912
+ 3298 006c 0ED0     		beq	.L138
+ 3299              	.L135:
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 169
+
+
+ 3300              		.loc 1 1816 3 is_stmt 1 view .LVU1132
+1816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3301              		.loc 1 1816 17 is_stmt 0 view .LVU1133
+ 3302 006e 2023     		movs	r3, #32
+ 3303 0070 C4F88430 		str	r3, [r4, #132]
+1818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 3304              		.loc 1 1818 3 is_stmt 1 view .LVU1134
+1818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 3305              		.loc 1 1818 10 is_stmt 0 view .LVU1135
+ 3306 0074 0020     		movs	r0, #0
+ 3307              	.L134:
+1819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3308              		.loc 1 1819 1 view .LVU1136
+ 3309 0076 10BD     		pop	{r4, pc}
+ 3310              	.LVL297:
+ 3311              	.L137:
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 3312              		.loc 1 1795 9 is_stmt 1 view .LVU1137
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 3313              		.loc 1 1795 13 is_stmt 0 view .LVU1138
+ 3314 0078 A06F     		ldr	r0, [r4, #120]
+ 3315 007a FFF7FEFF 		bl	HAL_DMA_GetError
+ 3316              	.LVL298:
+1795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 3317              		.loc 1 1795 12 view .LVU1139
+ 3318 007e 2028     		cmp	r0, #32
+ 3319 0080 EED1     		bne	.L132
+1798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3320              		.loc 1 1798 11 is_stmt 1 view .LVU1140
+1798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3321              		.loc 1 1798 28 is_stmt 0 view .LVU1141
+ 3322 0082 1023     		movs	r3, #16
+ 3323 0084 C4F88C30 		str	r3, [r4, #140]
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 3324              		.loc 1 1800 11 is_stmt 1 view .LVU1142
+1800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 3325              		.loc 1 1800 18 is_stmt 0 view .LVU1143
+ 3326 0088 0320     		movs	r0, #3
+ 3327 008a F4E7     		b	.L134
+ 3328              	.LVL299:
+ 3329              	.L138:
+1812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3330              		.loc 1 1812 5 is_stmt 1 view .LVU1144
+ 3331 008c 2268     		ldr	r2, [r4]
+ 3332 008e 9369     		ldr	r3, [r2, #24]
+ 3333 0090 43F01003 		orr	r3, r3, #16
+ 3334 0094 9361     		str	r3, [r2, #24]
+ 3335 0096 EAE7     		b	.L135
+ 3336              		.cfi_endproc
+ 3337              	.LFE346:
+ 3339              		.section	.text.HAL_UART_AbortReceive,"ax",%progbits
+ 3340              		.align	1
+ 3341              		.global	HAL_UART_AbortReceive
+ 3342              		.syntax unified
+ 3343              		.thumb
+ 3344              		.thumb_func
+ 3346              	HAL_UART_AbortReceive:
+ARM GAS  /tmp/cceWHrnJ.s 			page 170
+
+
+ 3347              	.LVL300:
+ 3348              	.LFB347:
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+ 3349              		.loc 1 1834 1 view -0
+ 3350              		.cfi_startproc
+ 3351              		@ args = 0, pretend = 0, frame = 0
+ 3352              		@ frame_needed = 0, uses_anonymous_args = 0
+1834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+ 3353              		.loc 1 1834 1 is_stmt 0 view .LVU1146
+ 3354 0000 10B5     		push	{r4, lr}
+ 3355              	.LCFI11:
+ 3356              		.cfi_def_cfa_offset 8
+ 3357              		.cfi_offset 4, -8
+ 3358              		.cfi_offset 14, -4
+ 3359 0002 0446     		mov	r4, r0
+ 3360              	.L140:
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ 3361              		.loc 1 1836 3 is_stmt 1 discriminator 1 view .LVU1147
+ 3362              	.LBB679:
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ 3363              		.loc 1 1836 3 discriminator 1 view .LVU1148
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ 3364              		.loc 1 1836 3 discriminator 1 view .LVU1149
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ 3365              		.loc 1 1836 3 discriminator 1 view .LVU1150
+ 3366 0004 2268     		ldr	r2, [r4]
+ 3367              	.LVL301:
+ 3368              	.LBB680:
+ 3369              	.LBI680:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3370              		.loc 2 1151 31 discriminator 1 view .LVU1151
+ 3371              	.LBB681:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3372              		.loc 2 1153 5 discriminator 1 view .LVU1152
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3373              		.loc 2 1155 4 discriminator 1 view .LVU1153
+ 3374              		.syntax unified
+ 3375              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3376 0006 52E8003F 		ldrex r3, [r2]
+ 3377              	@ 0 "" 2
+ 3378              	.LVL302:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3379              		.loc 2 1156 4 discriminator 1 view .LVU1154
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3380              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1155
+ 3381              		.thumb
+ 3382              		.syntax unified
+ 3383              	.LBE681:
+ 3384              	.LBE680:
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ 3385              		.loc 1 1836 3 discriminator 1 view .LVU1156
+ 3386 000a 23F49073 		bic	r3, r3, #288
+ 3387              	.LVL303:
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ 3388              		.loc 1 1836 3 is_stmt 1 discriminator 1 view .LVU1157
+ 3389              	.LBB682:
+ 3390              	.LBI682:
+ARM GAS  /tmp/cceWHrnJ.s 			page 171
+
+
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3391              		.loc 2 1202 31 discriminator 1 view .LVU1158
+ 3392              	.LBB683:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3393              		.loc 2 1204 4 discriminator 1 view .LVU1159
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3394              		.loc 2 1206 4 discriminator 1 view .LVU1160
+ 3395              		.syntax unified
+ 3396              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3397 000e 42E80031 		strex r1, r3, [r2]
+ 3398              	@ 0 "" 2
+ 3399              	.LVL304:
+ 3400              		.loc 2 1207 4 discriminator 1 view .LVU1161
+ 3401              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1162
+ 3402              		.thumb
+ 3403              		.syntax unified
+ 3404              	.LBE683:
+ 3405              	.LBE682:
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ 3406              		.loc 1 1836 3 discriminator 1 view .LVU1163
+ 3407 0012 0029     		cmp	r1, #0
+ 3408 0014 F6D1     		bne	.L140
+ 3409              	.LVL305:
+ 3410              	.L141:
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ 3411              		.loc 1 1836 3 discriminator 1 view .LVU1164
+ 3412              	.LBE679:
+1836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ 3413              		.loc 1 1836 3 is_stmt 1 discriminator 1 view .LVU1165
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3414              		.loc 1 1837 3 discriminator 1 view .LVU1166
+ 3415              	.LBB684:
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3416              		.loc 1 1837 3 discriminator 1 view .LVU1167
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3417              		.loc 1 1837 3 discriminator 1 view .LVU1168
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3418              		.loc 1 1837 3 discriminator 1 view .LVU1169
+ 3419 0016 2268     		ldr	r2, [r4]
+ 3420              	.LVL306:
+ 3421              	.LBB685:
+ 3422              	.LBI685:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3423              		.loc 2 1151 31 discriminator 1 view .LVU1170
+ 3424              	.LBB686:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3425              		.loc 2 1153 5 discriminator 1 view .LVU1171
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3426              		.loc 2 1155 4 discriminator 1 view .LVU1172
+ 3427 0018 02F10803 		add	r3, r2, #8
+ 3428              	.LVL307:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3429              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU1173
+ 3430              		.syntax unified
+ 3431              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3432 001c 53E8003F 		ldrex r3, [r3]
+ 3433              	@ 0 "" 2
+ARM GAS  /tmp/cceWHrnJ.s 			page 172
+
+
+ 3434              	.LVL308:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3435              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU1174
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3436              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1175
+ 3437              		.thumb
+ 3438              		.syntax unified
+ 3439              	.LBE686:
+ 3440              	.LBE685:
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3441              		.loc 1 1837 3 discriminator 1 view .LVU1176
+ 3442 0020 23F08053 		bic	r3, r3, #268435456
+ 3443 0024 23F00103 		bic	r3, r3, #1
+ 3444              	.LVL309:
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3445              		.loc 1 1837 3 is_stmt 1 discriminator 1 view .LVU1177
+ 3446              	.LBB687:
+ 3447              	.LBI687:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3448              		.loc 2 1202 31 discriminator 1 view .LVU1178
+ 3449              	.LBB688:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3450              		.loc 2 1204 4 discriminator 1 view .LVU1179
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3451              		.loc 2 1206 4 discriminator 1 view .LVU1180
+ 3452 0028 0832     		adds	r2, r2, #8
+ 3453              	.LVL310:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3454              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU1181
+ 3455              		.syntax unified
+ 3456              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3457 002a 42E80031 		strex r1, r3, [r2]
+ 3458              	@ 0 "" 2
+ 3459              	.LVL311:
+ 3460              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU1182
+ 3461              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1183
+ 3462              		.thumb
+ 3463              		.syntax unified
+ 3464              	.LBE688:
+ 3465              	.LBE687:
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3466              		.loc 1 1837 3 discriminator 1 view .LVU1184
+ 3467 002e 0029     		cmp	r1, #0
+ 3468 0030 F1D1     		bne	.L141
+ 3469              	.LBE684:
+1837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3470              		.loc 1 1837 3 is_stmt 1 discriminator 2 view .LVU1185
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3471              		.loc 1 1840 3 discriminator 2 view .LVU1186
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3472              		.loc 1 1840 12 is_stmt 0 discriminator 2 view .LVU1187
+ 3473 0032 E36E     		ldr	r3, [r4, #108]
+ 3474              	.LVL312:
+1840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3475              		.loc 1 1840 6 discriminator 2 view .LVU1188
+ 3476 0034 012B     		cmp	r3, #1
+ 3477 0036 28D0     		beq	.L143
+ARM GAS  /tmp/cceWHrnJ.s 			page 173
+
+
+ 3478              	.L142:
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3479              		.loc 1 1842 5 is_stmt 1 discriminator 2 view .LVU1189
+1846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3480              		.loc 1 1846 3 discriminator 2 view .LVU1190
+1846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3481              		.loc 1 1846 7 is_stmt 0 discriminator 2 view .LVU1191
+ 3482 0038 2368     		ldr	r3, [r4]
+ 3483 003a 9B68     		ldr	r3, [r3, #8]
+1846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3484              		.loc 1 1846 6 discriminator 2 view .LVU1192
+ 3485 003c 13F0400F 		tst	r3, #64
+ 3486 0040 13D0     		beq	.L144
+ 3487              	.L145:
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3488              		.loc 1 1849 5 is_stmt 1 discriminator 1 view .LVU1193
+ 3489              	.LBB689:
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3490              		.loc 1 1849 5 discriminator 1 view .LVU1194
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3491              		.loc 1 1849 5 discriminator 1 view .LVU1195
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3492              		.loc 1 1849 5 discriminator 1 view .LVU1196
+ 3493 0042 2268     		ldr	r2, [r4]
+ 3494              	.LVL313:
+ 3495              	.LBB690:
+ 3496              	.LBI690:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3497              		.loc 2 1151 31 discriminator 1 view .LVU1197
+ 3498              	.LBB691:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3499              		.loc 2 1153 5 discriminator 1 view .LVU1198
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3500              		.loc 2 1155 4 discriminator 1 view .LVU1199
+ 3501 0044 02F10803 		add	r3, r2, #8
+ 3502              	.LVL314:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3503              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU1200
+ 3504              		.syntax unified
+ 3505              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3506 0048 53E8003F 		ldrex r3, [r3]
+ 3507              	@ 0 "" 2
+ 3508              	.LVL315:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3509              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU1201
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3510              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1202
+ 3511              		.thumb
+ 3512              		.syntax unified
+ 3513              	.LBE691:
+ 3514              	.LBE690:
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3515              		.loc 1 1849 5 discriminator 1 view .LVU1203
+ 3516 004c 23F04003 		bic	r3, r3, #64
+ 3517              	.LVL316:
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3518              		.loc 1 1849 5 is_stmt 1 discriminator 1 view .LVU1204
+ARM GAS  /tmp/cceWHrnJ.s 			page 174
+
+
+ 3519              	.LBB692:
+ 3520              	.LBI692:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3521              		.loc 2 1202 31 discriminator 1 view .LVU1205
+ 3522              	.LBB693:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3523              		.loc 2 1204 4 discriminator 1 view .LVU1206
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3524              		.loc 2 1206 4 discriminator 1 view .LVU1207
+ 3525 0050 0832     		adds	r2, r2, #8
+ 3526              	.LVL317:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3527              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU1208
+ 3528              		.syntax unified
+ 3529              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3530 0052 42E80031 		strex r1, r3, [r2]
+ 3531              	@ 0 "" 2
+ 3532              	.LVL318:
+ 3533              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU1209
+ 3534              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1210
+ 3535              		.thumb
+ 3536              		.syntax unified
+ 3537              	.LBE693:
+ 3538              	.LBE692:
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3539              		.loc 1 1849 5 discriminator 1 view .LVU1211
+ 3540 0056 0029     		cmp	r1, #0
+ 3541 0058 F3D1     		bne	.L145
+ 3542              	.LBE689:
+1849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3543              		.loc 1 1849 5 is_stmt 1 discriminator 2 view .LVU1212
+1852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 3544              		.loc 1 1852 5 discriminator 2 view .LVU1213
+1852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 3545              		.loc 1 1852 14 is_stmt 0 discriminator 2 view .LVU1214
+ 3546 005a E36F     		ldr	r3, [r4, #124]
+ 3547              	.LVL319:
+1852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 3548              		.loc 1 1852 8 discriminator 2 view .LVU1215
+ 3549 005c 2BB1     		cbz	r3, .L144
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3550              		.loc 1 1856 7 is_stmt 1 view .LVU1216
+1856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3551              		.loc 1 1856 40 is_stmt 0 view .LVU1217
+ 3552 005e 0022     		movs	r2, #0
+ 3553 0060 9A63     		str	r2, [r3, #56]
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 3554              		.loc 1 1858 7 is_stmt 1 view .LVU1218
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 3555              		.loc 1 1858 11 is_stmt 0 view .LVU1219
+ 3556 0062 E06F     		ldr	r0, [r4, #124]
+ 3557              	.LVL320:
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 3558              		.loc 1 1858 11 view .LVU1220
+ 3559 0064 FFF7FEFF 		bl	HAL_DMA_Abort
+ 3560              	.LVL321:
+1858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ARM GAS  /tmp/cceWHrnJ.s 			page 175
+
+
+ 3561              		.loc 1 1858 10 view .LVU1221
+ 3562 0068 C8B9     		cbnz	r0, .L148
+ 3563              	.LVL322:
+ 3564              	.L144:
+1872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3565              		.loc 1 1872 3 is_stmt 1 view .LVU1222
+1872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3566              		.loc 1 1872 22 is_stmt 0 view .LVU1223
+ 3567 006a 0020     		movs	r0, #0
+ 3568 006c A4F85E00 		strh	r0, [r4, #94]	@ movhi
+1875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3569              		.loc 1 1875 3 is_stmt 1 view .LVU1224
+ 3570 0070 2368     		ldr	r3, [r4]
+ 3571 0072 0F22     		movs	r2, #15
+ 3572 0074 1A62     		str	r2, [r3, #32]
+1878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3573              		.loc 1 1878 3 view .LVU1225
+ 3574 0076 2268     		ldr	r2, [r4]
+ 3575 0078 9369     		ldr	r3, [r2, #24]
+ 3576 007a 43F00803 		orr	r3, r3, #8
+ 3577 007e 9361     		str	r3, [r2, #24]
+1881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 3578              		.loc 1 1881 3 view .LVU1226
+1881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 3579              		.loc 1 1881 18 is_stmt 0 view .LVU1227
+ 3580 0080 2023     		movs	r3, #32
+ 3581 0082 C4F88830 		str	r3, [r4, #136]
+1882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3582              		.loc 1 1882 3 is_stmt 1 view .LVU1228
+1882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3583              		.loc 1 1882 24 is_stmt 0 view .LVU1229
+ 3584 0086 E066     		str	r0, [r4, #108]
+1884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 3585              		.loc 1 1884 3 is_stmt 1 view .LVU1230
+ 3586              	.L146:
+1885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3587              		.loc 1 1885 1 is_stmt 0 view .LVU1231
+ 3588 0088 10BD     		pop	{r4, pc}
+ 3589              	.LVL323:
+ 3590              	.L143:
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3591              		.loc 1 1842 5 is_stmt 1 discriminator 1 view .LVU1232
+ 3592              	.LBB694:
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3593              		.loc 1 1842 5 discriminator 1 view .LVU1233
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3594              		.loc 1 1842 5 discriminator 1 view .LVU1234
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3595              		.loc 1 1842 5 discriminator 1 view .LVU1235
+ 3596 008a 2268     		ldr	r2, [r4]
+ 3597              	.LVL324:
+ 3598              	.LBB695:
+ 3599              	.LBI695:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3600              		.loc 2 1151 31 discriminator 1 view .LVU1236
+ 3601              	.LBB696:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 176
+
+
+ 3602              		.loc 2 1153 5 discriminator 1 view .LVU1237
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3603              		.loc 2 1155 4 discriminator 1 view .LVU1238
+ 3604              		.syntax unified
+ 3605              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3606 008c 52E8003F 		ldrex r3, [r2]
+ 3607              	@ 0 "" 2
+ 3608              	.LVL325:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3609              		.loc 2 1156 4 discriminator 1 view .LVU1239
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3610              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1240
+ 3611              		.thumb
+ 3612              		.syntax unified
+ 3613              	.LBE696:
+ 3614              	.LBE695:
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3615              		.loc 1 1842 5 discriminator 1 view .LVU1241
+ 3616 0090 23F01003 		bic	r3, r3, #16
+ 3617              	.LVL326:
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3618              		.loc 1 1842 5 is_stmt 1 discriminator 1 view .LVU1242
+ 3619              	.LBB697:
+ 3620              	.LBI697:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3621              		.loc 2 1202 31 discriminator 1 view .LVU1243
+ 3622              	.LBB698:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3623              		.loc 2 1204 4 discriminator 1 view .LVU1244
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3624              		.loc 2 1206 4 discriminator 1 view .LVU1245
+ 3625              		.syntax unified
+ 3626              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3627 0094 42E80031 		strex r1, r3, [r2]
+ 3628              	@ 0 "" 2
+ 3629              	.LVL327:
+ 3630              		.loc 2 1207 4 discriminator 1 view .LVU1246
+ 3631              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1247
+ 3632              		.thumb
+ 3633              		.syntax unified
+ 3634              	.LBE698:
+ 3635              	.LBE697:
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3636              		.loc 1 1842 5 discriminator 1 view .LVU1248
+ 3637 0098 0029     		cmp	r1, #0
+ 3638 009a F6D1     		bne	.L143
+ 3639 009c CCE7     		b	.L142
+ 3640              	.LVL328:
+ 3641              	.L148:
+1842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3642              		.loc 1 1842 5 discriminator 1 view .LVU1249
+ 3643              	.LBE694:
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 3644              		.loc 1 1860 9 is_stmt 1 view .LVU1250
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 3645              		.loc 1 1860 13 is_stmt 0 view .LVU1251
+ 3646 009e E06F     		ldr	r0, [r4, #124]
+ARM GAS  /tmp/cceWHrnJ.s 			page 177
+
+
+ 3647 00a0 FFF7FEFF 		bl	HAL_DMA_GetError
+ 3648              	.LVL329:
+1860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 3649              		.loc 1 1860 12 view .LVU1252
+ 3650 00a4 2028     		cmp	r0, #32
+ 3651 00a6 E0D1     		bne	.L144
+1863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3652              		.loc 1 1863 11 is_stmt 1 view .LVU1253
+1863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3653              		.loc 1 1863 28 is_stmt 0 view .LVU1254
+ 3654 00a8 1023     		movs	r3, #16
+ 3655 00aa C4F88C30 		str	r3, [r4, #140]
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 3656              		.loc 1 1865 11 is_stmt 1 view .LVU1255
+1865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 3657              		.loc 1 1865 18 is_stmt 0 view .LVU1256
+ 3658 00ae 0320     		movs	r0, #3
+ 3659 00b0 EAE7     		b	.L146
+ 3660              		.cfi_endproc
+ 3661              	.LFE347:
+ 3663              		.section	.text.HAL_UART_TxCpltCallback,"ax",%progbits
+ 3664              		.align	1
+ 3665              		.weak	HAL_UART_TxCpltCallback
+ 3666              		.syntax unified
+ 3667              		.thumb
+ 3668              		.thumb_func
+ 3670              	HAL_UART_TxCpltCallback:
+ 3671              	.LVL330:
+ 3672              	.LFB352:
+2559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 3673              		.loc 1 2559 1 is_stmt 1 view -0
+ 3674              		.cfi_startproc
+ 3675              		@ args = 0, pretend = 0, frame = 0
+ 3676              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3677              		@ link register save eliminated.
+2561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3678              		.loc 1 2561 3 view .LVU1258
+2566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3679              		.loc 1 2566 1 is_stmt 0 view .LVU1259
+ 3680 0000 7047     		bx	lr
+ 3681              		.cfi_endproc
+ 3682              	.LFE352:
+ 3684              		.section	.text.UART_DMATransmitCplt,"ax",%progbits
+ 3685              		.align	1
+ 3686              		.syntax unified
+ 3687              		.thumb
+ 3688              		.thumb_func
+ 3690              	UART_DMATransmitCplt:
+ 3691              	.LVL331:
+ 3692              	.LFB380:
+3609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 3693              		.loc 1 3609 1 is_stmt 1 view -0
+ 3694              		.cfi_startproc
+ 3695              		@ args = 0, pretend = 0, frame = 0
+ 3696              		@ frame_needed = 0, uses_anonymous_args = 0
+3609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 3697              		.loc 1 3609 1 is_stmt 0 view .LVU1261
+ARM GAS  /tmp/cceWHrnJ.s 			page 178
+
+
+ 3698 0000 08B5     		push	{r3, lr}
+ 3699              	.LCFI12:
+ 3700              		.cfi_def_cfa_offset 8
+ 3701              		.cfi_offset 3, -8
+ 3702              		.cfi_offset 14, -4
+ 3703 0002 0346     		mov	r3, r0
+3610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3704              		.loc 1 3610 3 is_stmt 1 view .LVU1262
+3610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3705              		.loc 1 3610 23 is_stmt 0 view .LVU1263
+ 3706 0004 806A     		ldr	r0, [r0, #40]
+ 3707              	.LVL332:
+3613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3708              		.loc 1 3613 3 is_stmt 1 view .LVU1264
+3613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3709              		.loc 1 3613 7 is_stmt 0 view .LVU1265
+ 3710 0006 1B68     		ldr	r3, [r3]
+ 3711              	.LVL333:
+3613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3712              		.loc 1 3613 7 view .LVU1266
+ 3713 0008 1B68     		ldr	r3, [r3]
+3613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 3714              		.loc 1 3613 6 view .LVU1267
+ 3715 000a 13F0200F 		tst	r3, #32
+ 3716 000e 18D1     		bne	.L151
+3615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3717              		.loc 1 3615 5 is_stmt 1 view .LVU1268
+3615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3718              		.loc 1 3615 24 is_stmt 0 view .LVU1269
+ 3719 0010 0023     		movs	r3, #0
+ 3720 0012 A0F85630 		strh	r3, [r0, #86]	@ movhi
+ 3721              	.L152:
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3722              		.loc 1 3619 5 is_stmt 1 discriminator 1 view .LVU1270
+ 3723              	.LBB699:
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3724              		.loc 1 3619 5 discriminator 1 view .LVU1271
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3725              		.loc 1 3619 5 discriminator 1 view .LVU1272
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3726              		.loc 1 3619 5 discriminator 1 view .LVU1273
+ 3727 0016 0268     		ldr	r2, [r0]
+ 3728              	.LVL334:
+ 3729              	.LBB700:
+ 3730              	.LBI700:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3731              		.loc 2 1151 31 discriminator 1 view .LVU1274
+ 3732              	.LBB701:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3733              		.loc 2 1153 5 discriminator 1 view .LVU1275
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3734              		.loc 2 1155 4 discriminator 1 view .LVU1276
+ 3735 0018 02F10803 		add	r3, r2, #8
+ 3736              	.LVL335:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3737              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU1277
+ 3738              		.syntax unified
+ARM GAS  /tmp/cceWHrnJ.s 			page 179
+
+
+ 3739              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3740 001c 53E8003F 		ldrex r3, [r3]
+ 3741              	@ 0 "" 2
+ 3742              	.LVL336:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3743              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU1278
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3744              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1279
+ 3745              		.thumb
+ 3746              		.syntax unified
+ 3747              	.LBE701:
+ 3748              	.LBE700:
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3749              		.loc 1 3619 5 discriminator 1 view .LVU1280
+ 3750 0020 23F08003 		bic	r3, r3, #128
+ 3751              	.LVL337:
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3752              		.loc 1 3619 5 is_stmt 1 discriminator 1 view .LVU1281
+ 3753              	.LBB702:
+ 3754              	.LBI702:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3755              		.loc 2 1202 31 discriminator 1 view .LVU1282
+ 3756              	.LBB703:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3757              		.loc 2 1204 4 discriminator 1 view .LVU1283
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3758              		.loc 2 1206 4 discriminator 1 view .LVU1284
+ 3759 0024 0832     		adds	r2, r2, #8
+ 3760              	.LVL338:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3761              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU1285
+ 3762              		.syntax unified
+ 3763              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3764 0026 42E80031 		strex r1, r3, [r2]
+ 3765              	@ 0 "" 2
+ 3766              	.LVL339:
+ 3767              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU1286
+ 3768              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1287
+ 3769              		.thumb
+ 3770              		.syntax unified
+ 3771              	.LBE703:
+ 3772              	.LBE702:
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3773              		.loc 1 3619 5 discriminator 1 view .LVU1288
+ 3774 002a 0029     		cmp	r1, #0
+ 3775 002c F3D1     		bne	.L152
+ 3776              	.LVL340:
+ 3777              	.L153:
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3778              		.loc 1 3619 5 discriminator 1 view .LVU1289
+ 3779              	.LBE699:
+3619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3780              		.loc 1 3619 5 is_stmt 1 discriminator 1 view .LVU1290
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3781              		.loc 1 3622 5 discriminator 1 view .LVU1291
+ 3782              	.LBB704:
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ARM GAS  /tmp/cceWHrnJ.s 			page 180
+
+
+ 3783              		.loc 1 3622 5 discriminator 1 view .LVU1292
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3784              		.loc 1 3622 5 discriminator 1 view .LVU1293
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3785              		.loc 1 3622 5 discriminator 1 view .LVU1294
+ 3786 002e 0268     		ldr	r2, [r0]
+ 3787              	.LVL341:
+ 3788              	.LBB705:
+ 3789              	.LBI705:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3790              		.loc 2 1151 31 discriminator 1 view .LVU1295
+ 3791              	.LBB706:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3792              		.loc 2 1153 5 discriminator 1 view .LVU1296
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3793              		.loc 2 1155 4 discriminator 1 view .LVU1297
+ 3794              		.syntax unified
+ 3795              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3796 0030 52E8003F 		ldrex r3, [r2]
+ 3797              	@ 0 "" 2
+ 3798              	.LVL342:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3799              		.loc 2 1156 4 discriminator 1 view .LVU1298
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3800              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1299
+ 3801              		.thumb
+ 3802              		.syntax unified
+ 3803              	.LBE706:
+ 3804              	.LBE705:
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3805              		.loc 1 3622 5 discriminator 1 view .LVU1300
+ 3806 0034 43F04003 		orr	r3, r3, #64
+ 3807              	.LVL343:
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3808              		.loc 1 3622 5 is_stmt 1 discriminator 1 view .LVU1301
+ 3809              	.LBB707:
+ 3810              	.LBI707:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3811              		.loc 2 1202 31 discriminator 1 view .LVU1302
+ 3812              	.LBB708:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3813              		.loc 2 1204 4 discriminator 1 view .LVU1303
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3814              		.loc 2 1206 4 discriminator 1 view .LVU1304
+ 3815              		.syntax unified
+ 3816              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3817 0038 42E80031 		strex r1, r3, [r2]
+ 3818              	@ 0 "" 2
+ 3819              	.LVL344:
+ 3820              		.loc 2 1207 4 discriminator 1 view .LVU1305
+ 3821              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1306
+ 3822              		.thumb
+ 3823              		.syntax unified
+ 3824              	.LBE708:
+ 3825              	.LBE707:
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3826              		.loc 1 3622 5 discriminator 1 view .LVU1307
+ARM GAS  /tmp/cceWHrnJ.s 			page 181
+
+
+ 3827 003c 0029     		cmp	r1, #0
+ 3828 003e F6D1     		bne	.L153
+ 3829              	.LVL345:
+ 3830              	.L150:
+3622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 3831              		.loc 1 3622 5 discriminator 1 view .LVU1308
+ 3832              	.LBE704:
+3635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3833              		.loc 1 3635 1 view .LVU1309
+ 3834 0040 08BD     		pop	{r3, pc}
+ 3835              	.LVL346:
+ 3836              	.L151:
+3632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 3837              		.loc 1 3632 5 is_stmt 1 view .LVU1310
+ 3838 0042 FFF7FEFF 		bl	HAL_UART_TxCpltCallback
+ 3839              	.LVL347:
+3635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3840              		.loc 1 3635 1 is_stmt 0 view .LVU1311
+ 3841 0046 FBE7     		b	.L150
+ 3842              		.cfi_endproc
+ 3843              	.LFE380:
+ 3845              		.section	.text.UART_EndTransmit_IT,"ax",%progbits
+ 3846              		.align	1
+ 3847              		.syntax unified
+ 3848              		.thumb
+ 3849              		.thumb_func
+ 3851              	UART_EndTransmit_IT:
+ 3852              	.LFB394:
+4122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+4124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief  Wrap up transmission in non-blocking mode.
+4125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param  huart pointer to a UART_HandleTypeDef structure that contains
+4126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *                the configuration information for the specified UART module.
+4127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+4128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+4129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+4130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 3853              		.loc 1 4130 1 is_stmt 1 view -0
+ 3854              		.cfi_startproc
+ 3855              		@ args = 0, pretend = 0, frame = 0
+ 3856              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3857              	.LVL348:
+ 3858              		.loc 1 4130 1 is_stmt 0 view .LVU1313
+ 3859 0000 08B5     		push	{r3, lr}
+ 3860              	.LCFI13:
+ 3861              		.cfi_def_cfa_offset 8
+ 3862              		.cfi_offset 3, -8
+ 3863              		.cfi_offset 14, -4
+ 3864              	.L157:
+4131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable the UART Transmit Complete Interrupt */
+4132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ 3865              		.loc 1 4132 3 is_stmt 1 discriminator 1 view .LVU1314
+ 3866              	.LBB709:
+ 3867              		.loc 1 4132 3 discriminator 1 view .LVU1315
+ 3868              		.loc 1 4132 3 discriminator 1 view .LVU1316
+ 3869              		.loc 1 4132 3 discriminator 1 view .LVU1317
+ 3870 0002 0268     		ldr	r2, [r0]
+ARM GAS  /tmp/cceWHrnJ.s 			page 182
+
+
+ 3871              	.LVL349:
+ 3872              	.LBB710:
+ 3873              	.LBI710:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3874              		.loc 2 1151 31 discriminator 1 view .LVU1318
+ 3875              	.LBB711:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3876              		.loc 2 1153 5 discriminator 1 view .LVU1319
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3877              		.loc 2 1155 4 discriminator 1 view .LVU1320
+ 3878              		.syntax unified
+ 3879              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3880 0004 52E8003F 		ldrex r3, [r2]
+ 3881              	@ 0 "" 2
+ 3882              	.LVL350:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3883              		.loc 2 1156 4 discriminator 1 view .LVU1321
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 3884              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1322
+ 3885              		.thumb
+ 3886              		.syntax unified
+ 3887              	.LBE711:
+ 3888              	.LBE710:
+ 3889              		.loc 1 4132 3 discriminator 1 view .LVU1323
+ 3890 0008 23F04003 		bic	r3, r3, #64
+ 3891              	.LVL351:
+ 3892              		.loc 1 4132 3 is_stmt 1 discriminator 1 view .LVU1324
+ 3893              	.LBB712:
+ 3894              	.LBI712:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 3895              		.loc 2 1202 31 discriminator 1 view .LVU1325
+ 3896              	.LBB713:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 3897              		.loc 2 1204 4 discriminator 1 view .LVU1326
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 3898              		.loc 2 1206 4 discriminator 1 view .LVU1327
+ 3899              		.syntax unified
+ 3900              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 3901 000c 42E80031 		strex r1, r3, [r2]
+ 3902              	@ 0 "" 2
+ 3903              	.LVL352:
+ 3904              		.loc 2 1207 4 discriminator 1 view .LVU1328
+ 3905              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1329
+ 3906              		.thumb
+ 3907              		.syntax unified
+ 3908              	.LBE713:
+ 3909              	.LBE712:
+ 3910              		.loc 1 4132 3 discriminator 1 view .LVU1330
+ 3911 0010 0029     		cmp	r1, #0
+ 3912 0012 F6D1     		bne	.L157
+ 3913              	.LBE709:
+ 3914              		.loc 1 4132 3 is_stmt 1 discriminator 2 view .LVU1331
+4133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Tx process is ended, restore huart->gState to Ready */
+4135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_READY;
+ 3915              		.loc 1 4135 3 discriminator 2 view .LVU1332
+ 3916              		.loc 1 4135 17 is_stmt 0 discriminator 2 view .LVU1333
+ARM GAS  /tmp/cceWHrnJ.s 			page 183
+
+
+ 3917 0014 2023     		movs	r3, #32
+ 3918              	.LVL353:
+ 3919              		.loc 1 4135 17 discriminator 2 view .LVU1334
+ 3920 0016 C0F88430 		str	r3, [r0, #132]
+4136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Cleat TxISR function pointer */
+4138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxISR = NULL;
+ 3921              		.loc 1 4138 3 is_stmt 1 discriminator 2 view .LVU1335
+ 3922              		.loc 1 4138 16 is_stmt 0 discriminator 2 view .LVU1336
+ 3923 001a 0023     		movs	r3, #0
+ 3924 001c 4367     		str	r3, [r0, #116]
+4139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+4141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*Call registered Tx complete callback*/
+4142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxCpltCallback(huart);
+4143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+4144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /*Call legacy weak Tx complete callback*/
+4145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_UART_TxCpltCallback(huart);
+ 3925              		.loc 1 4145 3 is_stmt 1 discriminator 2 view .LVU1337
+ 3926 001e FFF7FEFF 		bl	HAL_UART_TxCpltCallback
+ 3927              	.LVL354:
+4146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+4147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 3928              		.loc 1 4147 1 is_stmt 0 discriminator 2 view .LVU1338
+ 3929 0022 08BD     		pop	{r3, pc}
+ 3930              		.cfi_endproc
+ 3931              	.LFE394:
+ 3933              		.section	.text.HAL_UART_TxHalfCpltCallback,"ax",%progbits
+ 3934              		.align	1
+ 3935              		.weak	HAL_UART_TxHalfCpltCallback
+ 3936              		.syntax unified
+ 3937              		.thumb
+ 3938              		.thumb_func
+ 3940              	HAL_UART_TxHalfCpltCallback:
+ 3941              	.LVL355:
+ 3942              	.LFB353:
+2574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 3943              		.loc 1 2574 1 is_stmt 1 view -0
+ 3944              		.cfi_startproc
+ 3945              		@ args = 0, pretend = 0, frame = 0
+ 3946              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3947              		@ link register save eliminated.
+2576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3948              		.loc 1 2576 3 view .LVU1340
+2581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3949              		.loc 1 2581 1 is_stmt 0 view .LVU1341
+ 3950 0000 7047     		bx	lr
+ 3951              		.cfi_endproc
+ 3952              	.LFE353:
+ 3954              		.section	.text.UART_DMATxHalfCplt,"ax",%progbits
+ 3955              		.align	1
+ 3956              		.syntax unified
+ 3957              		.thumb
+ 3958              		.thumb_func
+ 3960              	UART_DMATxHalfCplt:
+ 3961              	.LVL356:
+ 3962              	.LFB381:
+ARM GAS  /tmp/cceWHrnJ.s 			page 184
+
+
+3643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 3963              		.loc 1 3643 1 is_stmt 1 view -0
+ 3964              		.cfi_startproc
+ 3965              		@ args = 0, pretend = 0, frame = 0
+ 3966              		@ frame_needed = 0, uses_anonymous_args = 0
+3643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 3967              		.loc 1 3643 1 is_stmt 0 view .LVU1343
+ 3968 0000 08B5     		push	{r3, lr}
+ 3969              	.LCFI14:
+ 3970              		.cfi_def_cfa_offset 8
+ 3971              		.cfi_offset 3, -8
+ 3972              		.cfi_offset 14, -4
+3644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3973              		.loc 1 3644 3 is_stmt 1 view .LVU1344
+ 3974              	.LVL357:
+3651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 3975              		.loc 1 3651 3 view .LVU1345
+ 3976 0002 806A     		ldr	r0, [r0, #40]
+ 3977              	.LVL358:
+3651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 3978              		.loc 1 3651 3 is_stmt 0 view .LVU1346
+ 3979 0004 FFF7FEFF 		bl	HAL_UART_TxHalfCpltCallback
+ 3980              	.LVL359:
+3653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 3981              		.loc 1 3653 1 view .LVU1347
+ 3982 0008 08BD     		pop	{r3, pc}
+ 3983              		.cfi_endproc
+ 3984              	.LFE381:
+ 3986              		.section	.text.HAL_UART_RxCpltCallback,"ax",%progbits
+ 3987              		.align	1
+ 3988              		.weak	HAL_UART_RxCpltCallback
+ 3989              		.syntax unified
+ 3990              		.thumb
+ 3991              		.thumb_func
+ 3993              	HAL_UART_RxCpltCallback:
+ 3994              	.LVL360:
+ 3995              	.LFB354:
+2589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 3996              		.loc 1 2589 1 is_stmt 1 view -0
+ 3997              		.cfi_startproc
+ 3998              		@ args = 0, pretend = 0, frame = 0
+ 3999              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4000              		@ link register save eliminated.
+2591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4001              		.loc 1 2591 3 view .LVU1349
+2596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4002              		.loc 1 2596 1 is_stmt 0 view .LVU1350
+ 4003 0000 7047     		bx	lr
+ 4004              		.cfi_endproc
+ 4005              	.LFE354:
+ 4007              		.section	.text.HAL_UART_RxHalfCpltCallback,"ax",%progbits
+ 4008              		.align	1
+ 4009              		.weak	HAL_UART_RxHalfCpltCallback
+ 4010              		.syntax unified
+ 4011              		.thumb
+ 4012              		.thumb_func
+ 4014              	HAL_UART_RxHalfCpltCallback:
+ARM GAS  /tmp/cceWHrnJ.s 			page 185
+
+
+ 4015              	.LVL361:
+ 4016              	.LFB355:
+2604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 4017              		.loc 1 2604 1 is_stmt 1 view -0
+ 4018              		.cfi_startproc
+ 4019              		@ args = 0, pretend = 0, frame = 0
+ 4020              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4021              		@ link register save eliminated.
+2606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4022              		.loc 1 2606 3 view .LVU1352
+2611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4023              		.loc 1 2611 1 is_stmt 0 view .LVU1353
+ 4024 0000 7047     		bx	lr
+ 4025              		.cfi_endproc
+ 4026              	.LFE355:
+ 4028              		.section	.text.HAL_UART_ErrorCallback,"ax",%progbits
+ 4029              		.align	1
+ 4030              		.weak	HAL_UART_ErrorCallback
+ 4031              		.syntax unified
+ 4032              		.thumb
+ 4033              		.thumb_func
+ 4035              	HAL_UART_ErrorCallback:
+ 4036              	.LVL362:
+ 4037              	.LFB356:
+2619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 4038              		.loc 1 2619 1 is_stmt 1 view -0
+ 4039              		.cfi_startproc
+ 4040              		@ args = 0, pretend = 0, frame = 0
+ 4041              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4042              		@ link register save eliminated.
+2621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4043              		.loc 1 2621 3 view .LVU1355
+2626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4044              		.loc 1 2626 1 is_stmt 0 view .LVU1356
+ 4045 0000 7047     		bx	lr
+ 4046              		.cfi_endproc
+ 4047              	.LFE356:
+ 4049              		.section	.text.UART_DMAError,"ax",%progbits
+ 4050              		.align	1
+ 4051              		.syntax unified
+ 4052              		.thumb
+ 4053              		.thumb_func
+ 4055              	UART_DMAError:
+ 4056              	.LVL363:
+ 4057              	.LFB384:
+3752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 4058              		.loc 1 3752 1 is_stmt 1 view -0
+ 4059              		.cfi_startproc
+ 4060              		@ args = 0, pretend = 0, frame = 0
+ 4061              		@ frame_needed = 0, uses_anonymous_args = 0
+3752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 4062              		.loc 1 3752 1 is_stmt 0 view .LVU1358
+ 4063 0000 38B5     		push	{r3, r4, r5, lr}
+ 4064              	.LCFI15:
+ 4065              		.cfi_def_cfa_offset 16
+ 4066              		.cfi_offset 3, -16
+ 4067              		.cfi_offset 4, -12
+ARM GAS  /tmp/cceWHrnJ.s 			page 186
+
+
+ 4068              		.cfi_offset 5, -8
+ 4069              		.cfi_offset 14, -4
+3753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4070              		.loc 1 3753 3 is_stmt 1 view .LVU1359
+3753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4071              		.loc 1 3753 23 is_stmt 0 view .LVU1360
+ 4072 0002 846A     		ldr	r4, [r0, #40]
+ 4073              	.LVL364:
+3755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef rxstate = huart->RxState;
+ 4074              		.loc 1 3755 3 is_stmt 1 view .LVU1361
+3755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const HAL_UART_StateTypeDef rxstate = huart->RxState;
+ 4075              		.loc 1 3755 31 is_stmt 0 view .LVU1362
+ 4076 0004 D4F88420 		ldr	r2, [r4, #132]
+ 4077              	.LVL365:
+3756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4078              		.loc 1 3756 3 is_stmt 1 view .LVU1363
+3756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4079              		.loc 1 3756 31 is_stmt 0 view .LVU1364
+ 4080 0008 D4F88850 		ldr	r5, [r4, #136]
+ 4081              	.LVL366:
+3759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+ 4082              		.loc 1 3759 3 is_stmt 1 view .LVU1365
+3759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+ 4083              		.loc 1 3759 8 is_stmt 0 view .LVU1366
+ 4084 000c 2368     		ldr	r3, [r4]
+ 4085 000e 9B68     		ldr	r3, [r3, #8]
+3759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+ 4086              		.loc 1 3759 6 view .LVU1367
+ 4087 0010 13F0800F 		tst	r3, #128
+ 4088 0014 01D0     		beq	.L166
+3759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (gstate == HAL_UART_STATE_BUSY_TX))
+ 4089              		.loc 1 3759 62 discriminator 1 view .LVU1368
+ 4090 0016 212A     		cmp	r2, #33
+ 4091 0018 10D0     		beq	.L169
+ 4092              	.LVL367:
+ 4093              	.L166:
+3767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+ 4094              		.loc 1 3767 3 is_stmt 1 view .LVU1369
+3767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+ 4095              		.loc 1 3767 8 is_stmt 0 view .LVU1370
+ 4096 001a 2368     		ldr	r3, [r4]
+ 4097 001c 9B68     		ldr	r3, [r3, #8]
+3767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+ 4098              		.loc 1 3767 6 view .LVU1371
+ 4099 001e 13F0400F 		tst	r3, #64
+ 4100 0022 01D0     		beq	.L167
+3767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       (rxstate == HAL_UART_STATE_BUSY_RX))
+ 4101              		.loc 1 3767 62 discriminator 1 view .LVU1372
+ 4102 0024 222D     		cmp	r5, #34
+ 4103 0026 10D0     		beq	.L170
+ 4104              	.L167:
+3774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4105              		.loc 1 3774 3 is_stmt 1 view .LVU1373
+3774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4106              		.loc 1 3774 8 is_stmt 0 view .LVU1374
+ 4107 0028 D4F88C30 		ldr	r3, [r4, #140]
+3774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 187
+
+
+ 4108              		.loc 1 3774 20 view .LVU1375
+ 4109 002c 43F01003 		orr	r3, r3, #16
+ 4110 0030 C4F88C30 		str	r3, [r4, #140]
+3781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 4111              		.loc 1 3781 3 is_stmt 1 view .LVU1376
+ 4112 0034 2046     		mov	r0, r4
+ 4113 0036 FFF7FEFF 		bl	HAL_UART_ErrorCallback
+ 4114              	.LVL368:
+3783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4115              		.loc 1 3783 1 is_stmt 0 view .LVU1377
+ 4116 003a 38BD     		pop	{r3, r4, r5, pc}
+ 4117              	.LVL369:
+ 4118              	.L169:
+3762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_EndTxTransfer(huart);
+ 4119              		.loc 1 3762 5 is_stmt 1 view .LVU1378
+3762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_EndTxTransfer(huart);
+ 4120              		.loc 1 3762 24 is_stmt 0 view .LVU1379
+ 4121 003c 0023     		movs	r3, #0
+ 4122 003e A4F85630 		strh	r3, [r4, #86]	@ movhi
+3763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4123              		.loc 1 3763 5 is_stmt 1 view .LVU1380
+ 4124 0042 2046     		mov	r0, r4
+ 4125              	.LVL370:
+3763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4126              		.loc 1 3763 5 is_stmt 0 view .LVU1381
+ 4127 0044 FFF7FEFF 		bl	UART_EndTxTransfer
+ 4128              	.LVL371:
+3763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4129              		.loc 1 3763 5 view .LVU1382
+ 4130 0048 E7E7     		b	.L166
+ 4131              	.L170:
+3770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_EndRxTransfer(huart);
+ 4132              		.loc 1 3770 5 is_stmt 1 view .LVU1383
+3770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     UART_EndRxTransfer(huart);
+ 4133              		.loc 1 3770 24 is_stmt 0 view .LVU1384
+ 4134 004a 0023     		movs	r3, #0
+ 4135 004c A4F85E30 		strh	r3, [r4, #94]	@ movhi
+3771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4136              		.loc 1 3771 5 is_stmt 1 view .LVU1385
+ 4137 0050 2046     		mov	r0, r4
+ 4138 0052 FFF7FEFF 		bl	UART_EndRxTransfer
+ 4139              	.LVL372:
+ 4140 0056 E7E7     		b	.L167
+ 4141              		.cfi_endproc
+ 4142              	.LFE384:
+ 4144              		.section	.text.UART_DMAAbortOnError,"ax",%progbits
+ 4145              		.align	1
+ 4146              		.syntax unified
+ 4147              		.thumb
+ 4148              		.thumb_func
+ 4150              	UART_DMAAbortOnError:
+ 4151              	.LVL373:
+ 4152              	.LFB385:
+3792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 4153              		.loc 1 3792 1 view -0
+ 4154              		.cfi_startproc
+ 4155              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/cceWHrnJ.s 			page 188
+
+
+ 4156              		@ frame_needed = 0, uses_anonymous_args = 0
+3792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 4157              		.loc 1 3792 1 is_stmt 0 view .LVU1387
+ 4158 0000 08B5     		push	{r3, lr}
+ 4159              	.LCFI16:
+ 4160              		.cfi_def_cfa_offset 8
+ 4161              		.cfi_offset 3, -8
+ 4162              		.cfi_offset 14, -4
+3793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+ 4163              		.loc 1 3793 3 is_stmt 1 view .LVU1388
+3793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+ 4164              		.loc 1 3793 23 is_stmt 0 view .LVU1389
+ 4165 0002 806A     		ldr	r0, [r0, #40]
+ 4166              	.LVL374:
+3794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxXferCount = 0U;
+ 4167              		.loc 1 3794 3 is_stmt 1 view .LVU1390
+3794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxXferCount = 0U;
+ 4168              		.loc 1 3794 22 is_stmt 0 view .LVU1391
+ 4169 0004 0023     		movs	r3, #0
+ 4170 0006 A0F85E30 		strh	r3, [r0, #94]	@ movhi
+3795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4171              		.loc 1 3795 3 is_stmt 1 view .LVU1392
+3795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4172              		.loc 1 3795 22 is_stmt 0 view .LVU1393
+ 4173 000a A0F85630 		strh	r3, [r0, #86]	@ movhi
+3802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 4174              		.loc 1 3802 3 is_stmt 1 view .LVU1394
+ 4175 000e FFF7FEFF 		bl	HAL_UART_ErrorCallback
+ 4176              	.LVL375:
+3804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4177              		.loc 1 3804 1 is_stmt 0 view .LVU1395
+ 4178 0012 08BD     		pop	{r3, pc}
+ 4179              		.cfi_endproc
+ 4180              	.LFE385:
+ 4182              		.section	.text.HAL_UART_AbortCpltCallback,"ax",%progbits
+ 4183              		.align	1
+ 4184              		.weak	HAL_UART_AbortCpltCallback
+ 4185              		.syntax unified
+ 4186              		.thumb
+ 4187              		.thumb_func
+ 4189              	HAL_UART_AbortCpltCallback:
+ 4190              	.LVL376:
+ 4191              	.LFB357:
+2634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 4192              		.loc 1 2634 1 is_stmt 1 view -0
+ 4193              		.cfi_startproc
+ 4194              		@ args = 0, pretend = 0, frame = 0
+ 4195              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4196              		@ link register save eliminated.
+2636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4197              		.loc 1 2636 3 view .LVU1397
+2641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4198              		.loc 1 2641 1 is_stmt 0 view .LVU1398
+ 4199 0000 7047     		bx	lr
+ 4200              		.cfi_endproc
+ 4201              	.LFE357:
+ 4203              		.section	.text.HAL_UART_Abort_IT,"ax",%progbits
+ARM GAS  /tmp/cceWHrnJ.s 			page 189
+
+
+ 4204              		.align	1
+ 4205              		.global	HAL_UART_Abort_IT
+ 4206              		.syntax unified
+ 4207              		.thumb
+ 4208              		.thumb_func
+ 4210              	HAL_UART_Abort_IT:
+ 4211              	.LVL377:
+ 4212              	.LFB348:
+1902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t abortcplt = 1U;
+ 4213              		.loc 1 1902 1 is_stmt 1 view -0
+ 4214              		.cfi_startproc
+ 4215              		@ args = 0, pretend = 0, frame = 0
+ 4216              		@ frame_needed = 0, uses_anonymous_args = 0
+1902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t abortcplt = 1U;
+ 4217              		.loc 1 1902 1 is_stmt 0 view .LVU1400
+ 4218 0000 38B5     		push	{r3, r4, r5, lr}
+ 4219              	.LCFI17:
+ 4220              		.cfi_def_cfa_offset 16
+ 4221              		.cfi_offset 3, -16
+ 4222              		.cfi_offset 4, -12
+ 4223              		.cfi_offset 5, -8
+ 4224              		.cfi_offset 14, -4
+ 4225 0002 0446     		mov	r4, r0
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4226              		.loc 1 1903 3 is_stmt 1 view .LVU1401
+ 4227              	.LVL378:
+ 4228              	.L175:
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE));
+ 4229              		.loc 1 1906 3 discriminator 1 view .LVU1402
+ 4230              	.LBB714:
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE));
+ 4231              		.loc 1 1906 3 discriminator 1 view .LVU1403
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE));
+ 4232              		.loc 1 1906 3 discriminator 1 view .LVU1404
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE));
+ 4233              		.loc 1 1906 3 discriminator 1 view .LVU1405
+ 4234 0004 2268     		ldr	r2, [r4]
+ 4235              	.LVL379:
+ 4236              	.LBB715:
+ 4237              	.LBI715:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4238              		.loc 2 1151 31 discriminator 1 view .LVU1406
+ 4239              	.LBB716:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4240              		.loc 2 1153 5 discriminator 1 view .LVU1407
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4241              		.loc 2 1155 4 discriminator 1 view .LVU1408
+ 4242              		.syntax unified
+ 4243              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4244 0006 52E8003F 		ldrex r3, [r2]
+ 4245              	@ 0 "" 2
+ 4246              	.LVL380:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4247              		.loc 2 1156 4 discriminator 1 view .LVU1409
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4248              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1410
+ 4249              		.thumb
+ARM GAS  /tmp/cceWHrnJ.s 			page 190
+
+
+ 4250              		.syntax unified
+ 4251              	.LBE716:
+ 4252              	.LBE715:
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE));
+ 4253              		.loc 1 1906 3 discriminator 1 view .LVU1411
+ 4254 000a 23F4F073 		bic	r3, r3, #480
+ 4255              	.LVL381:
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE));
+ 4256              		.loc 1 1906 3 is_stmt 1 discriminator 1 view .LVU1412
+ 4257              	.LBB717:
+ 4258              	.LBI717:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4259              		.loc 2 1202 31 discriminator 1 view .LVU1413
+ 4260              	.LBB718:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4261              		.loc 2 1204 4 discriminator 1 view .LVU1414
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4262              		.loc 2 1206 4 discriminator 1 view .LVU1415
+ 4263              		.syntax unified
+ 4264              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4265 000e 42E80031 		strex r1, r3, [r2]
+ 4266              	@ 0 "" 2
+ 4267              	.LVL382:
+ 4268              		.loc 2 1207 4 discriminator 1 view .LVU1416
+ 4269              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1417
+ 4270              		.thumb
+ 4271              		.syntax unified
+ 4272              	.LBE718:
+ 4273              	.LBE717:
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE));
+ 4274              		.loc 1 1906 3 discriminator 1 view .LVU1418
+ 4275 0012 0029     		cmp	r1, #0
+ 4276 0014 F6D1     		bne	.L175
+ 4277              	.LVL383:
+ 4278              	.L176:
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE));
+ 4279              		.loc 1 1906 3 discriminator 1 view .LVU1419
+ 4280              	.LBE714:
+1906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                           USART_CR1_TXEIE_TXFNFIE));
+ 4281              		.loc 1 1906 3 is_stmt 1 discriminator 1 view .LVU1420
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4282              		.loc 1 1908 3 discriminator 1 view .LVU1421
+ 4283              	.LBB719:
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4284              		.loc 1 1908 3 discriminator 1 view .LVU1422
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4285              		.loc 1 1908 3 discriminator 1 view .LVU1423
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4286              		.loc 1 1908 3 discriminator 1 view .LVU1424
+ 4287 0016 2268     		ldr	r2, [r4]
+ 4288              	.LVL384:
+ 4289              	.LBB720:
+ 4290              	.LBI720:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4291              		.loc 2 1151 31 discriminator 1 view .LVU1425
+ 4292              	.LBB721:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 191
+
+
+ 4293              		.loc 2 1153 5 discriminator 1 view .LVU1426
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4294              		.loc 2 1155 4 discriminator 1 view .LVU1427
+ 4295 0018 02F10803 		add	r3, r2, #8
+ 4296              	.LVL385:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4297              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU1428
+ 4298              		.syntax unified
+ 4299              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4300 001c 53E8003F 		ldrex r3, [r3]
+ 4301              	@ 0 "" 2
+ 4302              	.LVL386:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4303              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU1429
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4304              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1430
+ 4305              		.thumb
+ 4306              		.syntax unified
+ 4307              	.LBE721:
+ 4308              	.LBE720:
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4309              		.loc 1 1908 3 discriminator 1 view .LVU1431
+ 4310 0020 23F08453 		bic	r3, r3, #276824064
+ 4311 0024 23F00103 		bic	r3, r3, #1
+ 4312              	.LVL387:
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4313              		.loc 1 1908 3 is_stmt 1 discriminator 1 view .LVU1432
+ 4314              	.LBB722:
+ 4315              	.LBI722:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4316              		.loc 2 1202 31 discriminator 1 view .LVU1433
+ 4317              	.LBB723:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4318              		.loc 2 1204 4 discriminator 1 view .LVU1434
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4319              		.loc 2 1206 4 discriminator 1 view .LVU1435
+ 4320 0028 0832     		adds	r2, r2, #8
+ 4321              	.LVL388:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4322              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU1436
+ 4323              		.syntax unified
+ 4324              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4325 002a 42E80031 		strex r1, r3, [r2]
+ 4326              	@ 0 "" 2
+ 4327              	.LVL389:
+ 4328              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU1437
+ 4329              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1438
+ 4330              		.thumb
+ 4331              		.syntax unified
+ 4332              	.LBE723:
+ 4333              	.LBE722:
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4334              		.loc 1 1908 3 discriminator 1 view .LVU1439
+ 4335 002e 0029     		cmp	r1, #0
+ 4336 0030 F1D1     		bne	.L176
+ 4337              	.LBE719:
+1908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 192
+
+
+ 4338              		.loc 1 1908 3 is_stmt 1 discriminator 2 view .LVU1440
+1911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4339              		.loc 1 1911 3 discriminator 2 view .LVU1441
+1911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4340              		.loc 1 1911 12 is_stmt 0 discriminator 2 view .LVU1442
+ 4341 0032 E36E     		ldr	r3, [r4, #108]
+ 4342              	.LVL390:
+1911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4343              		.loc 1 1911 6 discriminator 2 view .LVU1443
+ 4344 0034 012B     		cmp	r3, #1
+ 4345 0036 2ED0     		beq	.L178
+ 4346              	.L177:
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4347              		.loc 1 1913 5 is_stmt 1 discriminator 2 view .LVU1444
+1919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4348              		.loc 1 1919 3 discriminator 2 view .LVU1445
+1919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4349              		.loc 1 1919 12 is_stmt 0 discriminator 2 view .LVU1446
+ 4350 0038 A36F     		ldr	r3, [r4, #120]
+1919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4351              		.loc 1 1919 6 discriminator 2 view .LVU1447
+ 4352 003a 33B1     		cbz	r3, .L179
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4353              		.loc 1 1923 5 is_stmt 1 view .LVU1448
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4354              		.loc 1 1923 9 is_stmt 0 view .LVU1449
+ 4355 003c 2268     		ldr	r2, [r4]
+ 4356 003e 9268     		ldr	r2, [r2, #8]
+1923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4357              		.loc 1 1923 8 view .LVU1450
+ 4358 0040 12F0800F 		tst	r2, #128
+ 4359 0044 31D0     		beq	.L180
+1925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 4360              		.loc 1 1925 7 is_stmt 1 view .LVU1451
+1925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 4361              		.loc 1 1925 40 is_stmt 0 view .LVU1452
+ 4362 0046 3F4A     		ldr	r2, .L194
+ 4363 0048 9A63     		str	r2, [r3, #56]
+ 4364              	.L179:
+1933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4365              		.loc 1 1933 3 is_stmt 1 view .LVU1453
+1933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4366              		.loc 1 1933 12 is_stmt 0 view .LVU1454
+ 4367 004a E36F     		ldr	r3, [r4, #124]
+1933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4368              		.loc 1 1933 6 view .LVU1455
+ 4369 004c 33B1     		cbz	r3, .L181
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4370              		.loc 1 1937 5 is_stmt 1 view .LVU1456
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4371              		.loc 1 1937 9 is_stmt 0 view .LVU1457
+ 4372 004e 2268     		ldr	r2, [r4]
+ 4373 0050 9268     		ldr	r2, [r2, #8]
+1937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4374              		.loc 1 1937 8 view .LVU1458
+ 4375 0052 12F0400F 		tst	r2, #64
+ 4376 0056 2BD0     		beq	.L182
+ARM GAS  /tmp/cceWHrnJ.s 			page 193
+
+
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 4377              		.loc 1 1939 7 is_stmt 1 view .LVU1459
+1939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 4378              		.loc 1 1939 40 is_stmt 0 view .LVU1460
+ 4379 0058 3B4A     		ldr	r2, .L194+4
+ 4380 005a 9A63     		str	r2, [r3, #56]
+ 4381              	.L181:
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4382              		.loc 1 1948 3 is_stmt 1 view .LVU1461
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4383              		.loc 1 1948 7 is_stmt 0 view .LVU1462
+ 4384 005c 2368     		ldr	r3, [r4]
+ 4385 005e 9B68     		ldr	r3, [r3, #8]
+1948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4386              		.loc 1 1948 6 view .LVU1463
+ 4387 0060 13F0800F 		tst	r3, #128
+ 4388 0064 27D0     		beq	.L190
+ 4389              	.L184:
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4390              		.loc 1 1951 5 is_stmt 1 discriminator 1 view .LVU1464
+ 4391              	.LBB724:
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4392              		.loc 1 1951 5 discriminator 1 view .LVU1465
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4393              		.loc 1 1951 5 discriminator 1 view .LVU1466
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4394              		.loc 1 1951 5 discriminator 1 view .LVU1467
+ 4395 0066 2168     		ldr	r1, [r4]
+ 4396              	.LVL391:
+ 4397              	.LBB725:
+ 4398              	.LBI725:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4399              		.loc 2 1151 31 discriminator 1 view .LVU1468
+ 4400              	.LBB726:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4401              		.loc 2 1153 5 discriminator 1 view .LVU1469
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4402              		.loc 2 1155 4 discriminator 1 view .LVU1470
+ 4403 0068 01F10803 		add	r3, r1, #8
+ 4404              	.LVL392:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4405              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU1471
+ 4406              		.syntax unified
+ 4407              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4408 006c 53E8003F 		ldrex r3, [r3]
+ 4409              	@ 0 "" 2
+ 4410              	.LVL393:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4411              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU1472
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4412              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1473
+ 4413              		.thumb
+ 4414              		.syntax unified
+ 4415              	.LBE726:
+ 4416              	.LBE725:
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4417              		.loc 1 1951 5 discriminator 1 view .LVU1474
+ARM GAS  /tmp/cceWHrnJ.s 			page 194
+
+
+ 4418 0070 23F08003 		bic	r3, r3, #128
+ 4419              	.LVL394:
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4420              		.loc 1 1951 5 is_stmt 1 discriminator 1 view .LVU1475
+ 4421              	.LBB727:
+ 4422              	.LBI727:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4423              		.loc 2 1202 31 discriminator 1 view .LVU1476
+ 4424              	.LBB728:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4425              		.loc 2 1204 4 discriminator 1 view .LVU1477
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4426              		.loc 2 1206 4 discriminator 1 view .LVU1478
+ 4427 0074 0831     		adds	r1, r1, #8
+ 4428              	.LVL395:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4429              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU1479
+ 4430              		.syntax unified
+ 4431              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4432 0076 41E80032 		strex r2, r3, [r1]
+ 4433              	@ 0 "" 2
+ 4434              		.thumb
+ 4435              		.syntax unified
+ 4436 007a 1546     		mov	r5, r2
+ 4437              	.LVL396:
+ 4438              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU1480
+ 4439              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1481
+ 4440              	.LBE728:
+ 4441              	.LBE727:
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4442              		.loc 1 1951 5 discriminator 1 view .LVU1482
+ 4443 007c 002A     		cmp	r2, #0
+ 4444 007e F2D1     		bne	.L184
+ 4445              	.LBE724:
+1951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4446              		.loc 1 1951 5 is_stmt 1 discriminator 2 view .LVU1483
+1954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4447              		.loc 1 1954 5 discriminator 2 view .LVU1484
+1954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4448              		.loc 1 1954 14 is_stmt 0 discriminator 2 view .LVU1485
+ 4449 0080 A06F     		ldr	r0, [r4, #120]
+ 4450              	.LVL397:
+1954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4451              		.loc 1 1954 8 discriminator 2 view .LVU1486
+ 4452 0082 0028     		cmp	r0, #0
+ 4453 0084 51D0     		beq	.L191
+1960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 4454              		.loc 1 1960 7 is_stmt 1 view .LVU1487
+1960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 4455              		.loc 1 1960 11 is_stmt 0 view .LVU1488
+ 4456 0086 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 4457              	.LVL398:
+1960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 4458              		.loc 1 1960 10 view .LVU1489
+ 4459 008a A8B1     		cbz	r0, .L183
+1962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 4460              		.loc 1 1962 9 is_stmt 1 view .LVU1490
+ARM GAS  /tmp/cceWHrnJ.s 			page 195
+
+
+1962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 4461              		.loc 1 1962 14 is_stmt 0 view .LVU1491
+ 4462 008c A36F     		ldr	r3, [r4, #120]
+1962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 4463              		.loc 1 1962 42 view .LVU1492
+ 4464 008e 0022     		movs	r2, #0
+ 4465 0090 9A63     		str	r2, [r3, #56]
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4466              		.loc 1 1903 12 view .LVU1493
+ 4467 0092 0125     		movs	r5, #1
+ 4468 0094 10E0     		b	.L183
+ 4469              	.LVL399:
+ 4470              	.L178:
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4471              		.loc 1 1913 5 is_stmt 1 discriminator 1 view .LVU1494
+ 4472              	.LBB729:
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4473              		.loc 1 1913 5 discriminator 1 view .LVU1495
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4474              		.loc 1 1913 5 discriminator 1 view .LVU1496
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4475              		.loc 1 1913 5 discriminator 1 view .LVU1497
+ 4476 0096 2268     		ldr	r2, [r4]
+ 4477              	.LVL400:
+ 4478              	.LBB730:
+ 4479              	.LBI730:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4480              		.loc 2 1151 31 discriminator 1 view .LVU1498
+ 4481              	.LBB731:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4482              		.loc 2 1153 5 discriminator 1 view .LVU1499
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4483              		.loc 2 1155 4 discriminator 1 view .LVU1500
+ 4484              		.syntax unified
+ 4485              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4486 0098 52E8003F 		ldrex r3, [r2]
+ 4487              	@ 0 "" 2
+ 4488              	.LVL401:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4489              		.loc 2 1156 4 discriminator 1 view .LVU1501
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4490              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1502
+ 4491              		.thumb
+ 4492              		.syntax unified
+ 4493              	.LBE731:
+ 4494              	.LBE730:
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4495              		.loc 1 1913 5 discriminator 1 view .LVU1503
+ 4496 009c 23F01003 		bic	r3, r3, #16
+ 4497              	.LVL402:
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4498              		.loc 1 1913 5 is_stmt 1 discriminator 1 view .LVU1504
+ 4499              	.LBB732:
+ 4500              	.LBI732:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4501              		.loc 2 1202 31 discriminator 1 view .LVU1505
+ 4502              	.LBB733:
+ARM GAS  /tmp/cceWHrnJ.s 			page 196
+
+
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4503              		.loc 2 1204 4 discriminator 1 view .LVU1506
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4504              		.loc 2 1206 4 discriminator 1 view .LVU1507
+ 4505              		.syntax unified
+ 4506              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4507 00a0 42E80031 		strex r1, r3, [r2]
+ 4508              	@ 0 "" 2
+ 4509              	.LVL403:
+ 4510              		.loc 2 1207 4 discriminator 1 view .LVU1508
+ 4511              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1509
+ 4512              		.thumb
+ 4513              		.syntax unified
+ 4514              	.LBE733:
+ 4515              	.LBE732:
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4516              		.loc 1 1913 5 discriminator 1 view .LVU1510
+ 4517 00a4 0029     		cmp	r1, #0
+ 4518 00a6 F6D1     		bne	.L178
+ 4519 00a8 C6E7     		b	.L177
+ 4520              	.LVL404:
+ 4521              	.L180:
+1913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4522              		.loc 1 1913 5 discriminator 1 view .LVU1511
+ 4523              	.LBE729:
+1929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 4524              		.loc 1 1929 7 is_stmt 1 view .LVU1512
+1929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 4525              		.loc 1 1929 40 is_stmt 0 view .LVU1513
+ 4526 00aa 0022     		movs	r2, #0
+ 4527 00ac 9A63     		str	r2, [r3, #56]
+ 4528 00ae CCE7     		b	.L179
+ 4529              	.L182:
+1943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 4530              		.loc 1 1943 7 is_stmt 1 view .LVU1514
+1943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 4531              		.loc 1 1943 40 is_stmt 0 view .LVU1515
+ 4532 00b0 0022     		movs	r2, #0
+ 4533 00b2 9A63     		str	r2, [r3, #56]
+ 4534 00b4 D2E7     		b	.L181
+ 4535              	.L190:
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4536              		.loc 1 1903 12 view .LVU1516
+ 4537 00b6 0125     		movs	r5, #1
+ 4538              	.LVL405:
+ 4539              	.L183:
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4540              		.loc 1 1972 3 is_stmt 1 view .LVU1517
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4541              		.loc 1 1972 7 is_stmt 0 view .LVU1518
+ 4542 00b8 2368     		ldr	r3, [r4]
+ 4543 00ba 9B68     		ldr	r3, [r3, #8]
+1972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4544              		.loc 1 1972 6 view .LVU1519
+ 4545 00bc 13F0400F 		tst	r3, #64
+ 4546 00c0 35D0     		beq	.L185
+ 4547              	.L186:
+ARM GAS  /tmp/cceWHrnJ.s 			page 197
+
+
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4548              		.loc 1 1975 5 is_stmt 1 discriminator 1 view .LVU1520
+ 4549              	.LBB734:
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4550              		.loc 1 1975 5 discriminator 1 view .LVU1521
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4551              		.loc 1 1975 5 discriminator 1 view .LVU1522
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4552              		.loc 1 1975 5 discriminator 1 view .LVU1523
+ 4553 00c2 2268     		ldr	r2, [r4]
+ 4554              	.LVL406:
+ 4555              	.LBB735:
+ 4556              	.LBI735:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4557              		.loc 2 1151 31 discriminator 1 view .LVU1524
+ 4558              	.LBB736:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4559              		.loc 2 1153 5 discriminator 1 view .LVU1525
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4560              		.loc 2 1155 4 discriminator 1 view .LVU1526
+ 4561 00c4 02F10803 		add	r3, r2, #8
+ 4562              	.LVL407:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4563              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU1527
+ 4564              		.syntax unified
+ 4565              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4566 00c8 53E8003F 		ldrex r3, [r3]
+ 4567              	@ 0 "" 2
+ 4568              	.LVL408:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4569              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU1528
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4570              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1529
+ 4571              		.thumb
+ 4572              		.syntax unified
+ 4573              	.LBE736:
+ 4574              	.LBE735:
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4575              		.loc 1 1975 5 discriminator 1 view .LVU1530
+ 4576 00cc 23F04003 		bic	r3, r3, #64
+ 4577              	.LVL409:
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4578              		.loc 1 1975 5 is_stmt 1 discriminator 1 view .LVU1531
+ 4579              	.LBB737:
+ 4580              	.LBI737:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4581              		.loc 2 1202 31 discriminator 1 view .LVU1532
+ 4582              	.LBB738:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4583              		.loc 2 1204 4 discriminator 1 view .LVU1533
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4584              		.loc 2 1206 4 discriminator 1 view .LVU1534
+ 4585 00d0 0832     		adds	r2, r2, #8
+ 4586              	.LVL410:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4587              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU1535
+ 4588              		.syntax unified
+ARM GAS  /tmp/cceWHrnJ.s 			page 198
+
+
+ 4589              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4590 00d2 42E80031 		strex r1, r3, [r2]
+ 4591              	@ 0 "" 2
+ 4592              	.LVL411:
+ 4593              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU1536
+ 4594              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1537
+ 4595              		.thumb
+ 4596              		.syntax unified
+ 4597              	.LBE738:
+ 4598              	.LBE737:
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4599              		.loc 1 1975 5 discriminator 1 view .LVU1538
+ 4600 00d6 0029     		cmp	r1, #0
+ 4601 00d8 F3D1     		bne	.L186
+ 4602              	.LBE734:
+1975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4603              		.loc 1 1975 5 is_stmt 1 discriminator 2 view .LVU1539
+1978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4604              		.loc 1 1978 5 discriminator 2 view .LVU1540
+1978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4605              		.loc 1 1978 14 is_stmt 0 discriminator 2 view .LVU1541
+ 4606 00da E06F     		ldr	r0, [r4, #124]
+1978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4607              		.loc 1 1978 8 discriminator 2 view .LVU1542
+ 4608 00dc 38B3     		cbz	r0, .L185
+1984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 4609              		.loc 1 1984 7 is_stmt 1 view .LVU1543
+1984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 4610              		.loc 1 1984 11 is_stmt 0 view .LVU1544
+ 4611 00de FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 4612              	.LVL412:
+1984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 4613              		.loc 1 1984 10 view .LVU1545
+ 4614 00e2 30B3     		cbz	r0, .L187
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         abortcplt = 1U;
+ 4615              		.loc 1 1986 9 is_stmt 1 view .LVU1546
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         abortcplt = 1U;
+ 4616              		.loc 1 1986 14 is_stmt 0 view .LVU1547
+ 4617 00e4 E36F     		ldr	r3, [r4, #124]
+1986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         abortcplt = 1U;
+ 4618              		.loc 1 1986 42 view .LVU1548
+ 4619 00e6 0022     		movs	r2, #0
+ 4620 00e8 9A63     		str	r2, [r3, #56]
+1987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 4621              		.loc 1 1987 9 is_stmt 1 view .LVU1549
+ 4622              	.LVL413:
+1997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4623              		.loc 1 1997 3 view .LVU1550
+ 4624              	.L188:
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount = 0U;
+ 4625              		.loc 1 2000 5 view .LVU1551
+2000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount = 0U;
+ 4626              		.loc 1 2000 24 is_stmt 0 view .LVU1552
+ 4627 00ea 0023     		movs	r3, #0
+ 4628 00ec A4F85630 		strh	r3, [r4, #86]	@ movhi
+2001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4629              		.loc 1 2001 5 is_stmt 1 view .LVU1553
+ARM GAS  /tmp/cceWHrnJ.s 			page 199
+
+
+2001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4630              		.loc 1 2001 24 is_stmt 0 view .LVU1554
+ 4631 00f0 A4F85E30 		strh	r3, [r4, #94]	@ movhi
+2004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxISR = NULL;
+ 4632              		.loc 1 2004 5 is_stmt 1 view .LVU1555
+2004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxISR = NULL;
+ 4633              		.loc 1 2004 18 is_stmt 0 view .LVU1556
+ 4634 00f4 2367     		str	r3, [r4, #112]
+2005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4635              		.loc 1 2005 5 is_stmt 1 view .LVU1557
+2005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4636              		.loc 1 2005 18 is_stmt 0 view .LVU1558
+ 4637 00f6 6367     		str	r3, [r4, #116]
+2008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4638              		.loc 1 2008 5 is_stmt 1 view .LVU1559
+2008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4639              		.loc 1 2008 22 is_stmt 0 view .LVU1560
+ 4640 00f8 C4F88C30 		str	r3, [r4, #140]
+2011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4641              		.loc 1 2011 5 is_stmt 1 view .LVU1561
+ 4642 00fc 2368     		ldr	r3, [r4]
+ 4643 00fe 0F22     		movs	r2, #15
+ 4644 0100 1A62     		str	r2, [r3, #32]
+2014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4645              		.loc 1 2014 5 view .LVU1562
+2014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4646              		.loc 1 2014 14 is_stmt 0 view .LVU1563
+ 4647 0102 636E     		ldr	r3, [r4, #100]
+2014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4648              		.loc 1 2014 8 view .LVU1564
+ 4649 0104 B3F1005F 		cmp	r3, #536870912
+ 4650 0108 15D0     		beq	.L193
+ 4651              	.L189:
+2020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4652              		.loc 1 2020 5 is_stmt 1 view .LVU1565
+ 4653 010a 2268     		ldr	r2, [r4]
+ 4654 010c 9369     		ldr	r3, [r2, #24]
+ 4655 010e 43F00803 		orr	r3, r3, #8
+ 4656 0112 9361     		str	r3, [r2, #24]
+2023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxState = HAL_UART_STATE_READY;
+ 4657              		.loc 1 2023 5 view .LVU1566
+2023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxState = HAL_UART_STATE_READY;
+ 4658              		.loc 1 2023 20 is_stmt 0 view .LVU1567
+ 4659 0114 2023     		movs	r3, #32
+ 4660 0116 C4F88430 		str	r3, [r4, #132]
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 4661              		.loc 1 2024 5 is_stmt 1 view .LVU1568
+2024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 4662              		.loc 1 2024 20 is_stmt 0 view .LVU1569
+ 4663 011a C4F88830 		str	r3, [r4, #136]
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4664              		.loc 1 2025 5 is_stmt 1 view .LVU1570
+2025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4665              		.loc 1 2025 26 is_stmt 0 view .LVU1571
+ 4666 011e 0023     		movs	r3, #0
+ 4667 0120 E366     		str	r3, [r4, #108]
+2033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ARM GAS  /tmp/cceWHrnJ.s 			page 200
+
+
+ 4668              		.loc 1 2033 5 is_stmt 1 view .LVU1572
+ 4669 0122 2046     		mov	r0, r4
+ 4670 0124 FFF7FEFF 		bl	HAL_UART_AbortCpltCallback
+ 4671              	.LVL414:
+ 4672 0128 03E0     		b	.L187
+ 4673              	.LVL415:
+ 4674              	.L191:
+1903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4675              		.loc 1 1903 12 is_stmt 0 view .LVU1573
+ 4676 012a 0125     		movs	r5, #1
+ 4677 012c C4E7     		b	.L183
+ 4678              	.LVL416:
+ 4679              	.L185:
+1997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4680              		.loc 1 1997 3 is_stmt 1 view .LVU1574
+1997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4681              		.loc 1 1997 6 is_stmt 0 view .LVU1575
+ 4682 012e 012D     		cmp	r5, #1
+ 4683 0130 DBD0     		beq	.L188
+ 4684              	.LVL417:
+ 4685              	.L187:
+2037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 4686              		.loc 1 2037 3 is_stmt 1 view .LVU1576
+2038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4687              		.loc 1 2038 1 is_stmt 0 view .LVU1577
+ 4688 0132 0020     		movs	r0, #0
+ 4689 0134 38BD     		pop	{r3, r4, r5, pc}
+ 4690              	.LVL418:
+ 4691              	.L193:
+2016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 4692              		.loc 1 2016 7 is_stmt 1 view .LVU1578
+ 4693 0136 2268     		ldr	r2, [r4]
+ 4694 0138 9369     		ldr	r3, [r2, #24]
+ 4695 013a 43F01003 		orr	r3, r3, #16
+ 4696 013e 9361     		str	r3, [r2, #24]
+ 4697 0140 E3E7     		b	.L189
+ 4698              	.L195:
+ 4699 0142 00BF     		.align	2
+ 4700              	.L194:
+ 4701 0144 00000000 		.word	UART_DMATxAbortCallback
+ 4702 0148 00000000 		.word	UART_DMARxAbortCallback
+ 4703              		.cfi_endproc
+ 4704              	.LFE348:
+ 4706              		.section	.text.UART_DMARxAbortCallback,"ax",%progbits
+ 4707              		.align	1
+ 4708              		.syntax unified
+ 4709              		.thumb
+ 4710              		.thumb_func
+ 4712              	UART_DMARxAbortCallback:
+ 4713              	.LVL419:
+ 4714              	.LFB387:
+3870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 4715              		.loc 1 3870 1 view -0
+ 4716              		.cfi_startproc
+ 4717              		@ args = 0, pretend = 0, frame = 0
+ 4718              		@ frame_needed = 0, uses_anonymous_args = 0
+3870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ARM GAS  /tmp/cceWHrnJ.s 			page 201
+
+
+ 4719              		.loc 1 3870 1 is_stmt 0 view .LVU1580
+ 4720 0000 08B5     		push	{r3, lr}
+ 4721              	.LCFI18:
+ 4722              		.cfi_def_cfa_offset 8
+ 4723              		.cfi_offset 3, -8
+ 4724              		.cfi_offset 14, -4
+3871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4725              		.loc 1 3871 3 is_stmt 1 view .LVU1581
+3871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4726              		.loc 1 3871 23 is_stmt 0 view .LVU1582
+ 4727 0002 806A     		ldr	r0, [r0, #40]
+ 4728              	.LVL420:
+3873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4729              		.loc 1 3873 3 is_stmt 1 view .LVU1583
+3873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4730              		.loc 1 3873 8 is_stmt 0 view .LVU1584
+ 4731 0004 C36F     		ldr	r3, [r0, #124]
+3873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4732              		.loc 1 3873 36 view .LVU1585
+ 4733 0006 0022     		movs	r2, #0
+ 4734 0008 9A63     		str	r2, [r3, #56]
+3876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4735              		.loc 1 3876 3 is_stmt 1 view .LVU1586
+3876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4736              		.loc 1 3876 12 is_stmt 0 view .LVU1587
+ 4737 000a 836F     		ldr	r3, [r0, #120]
+3876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4738              		.loc 1 3876 6 view .LVU1588
+ 4739 000c 0BB1     		cbz	r3, .L197
+3878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4740              		.loc 1 3878 5 is_stmt 1 view .LVU1589
+3878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4741              		.loc 1 3878 22 is_stmt 0 view .LVU1590
+ 4742 000e 9B6B     		ldr	r3, [r3, #56]
+3878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4743              		.loc 1 3878 8 view .LVU1591
+ 4744 0010 B3B9     		cbnz	r3, .L196
+ 4745              	.L197:
+3885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+ 4746              		.loc 1 3885 3 is_stmt 1 view .LVU1592
+3885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+ 4747              		.loc 1 3885 22 is_stmt 0 view .LVU1593
+ 4748 0012 0023     		movs	r3, #0
+ 4749 0014 A0F85630 		strh	r3, [r0, #86]	@ movhi
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4750              		.loc 1 3886 3 is_stmt 1 view .LVU1594
+3886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4751              		.loc 1 3886 22 is_stmt 0 view .LVU1595
+ 4752 0018 A0F85E30 		strh	r3, [r0, #94]	@ movhi
+3889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4753              		.loc 1 3889 3 is_stmt 1 view .LVU1596
+3889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4754              		.loc 1 3889 20 is_stmt 0 view .LVU1597
+ 4755 001c C0F88C30 		str	r3, [r0, #140]
+3892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4756              		.loc 1 3892 3 is_stmt 1 view .LVU1598
+ 4757 0020 0268     		ldr	r2, [r0]
+ARM GAS  /tmp/cceWHrnJ.s 			page 202
+
+
+ 4758 0022 0F21     		movs	r1, #15
+ 4759 0024 1162     		str	r1, [r2, #32]
+3895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4760              		.loc 1 3895 3 view .LVU1599
+ 4761 0026 0168     		ldr	r1, [r0]
+ 4762 0028 8A69     		ldr	r2, [r1, #24]
+ 4763 002a 42F00802 		orr	r2, r2, #8
+ 4764 002e 8A61     		str	r2, [r1, #24]
+3898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 4765              		.loc 1 3898 3 view .LVU1600
+3898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 4766              		.loc 1 3898 18 is_stmt 0 view .LVU1601
+ 4767 0030 2022     		movs	r2, #32
+ 4768 0032 C0F88420 		str	r2, [r0, #132]
+3899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 4769              		.loc 1 3899 3 is_stmt 1 view .LVU1602
+3899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 4770              		.loc 1 3899 18 is_stmt 0 view .LVU1603
+ 4771 0036 C0F88820 		str	r2, [r0, #136]
+3900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4772              		.loc 1 3900 3 is_stmt 1 view .LVU1604
+3900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4773              		.loc 1 3900 24 is_stmt 0 view .LVU1605
+ 4774 003a C366     		str	r3, [r0, #108]
+3908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 4775              		.loc 1 3908 3 is_stmt 1 view .LVU1606
+ 4776 003c FFF7FEFF 		bl	HAL_UART_AbortCpltCallback
+ 4777              	.LVL421:
+ 4778              	.L196:
+3910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4779              		.loc 1 3910 1 is_stmt 0 view .LVU1607
+ 4780 0040 08BD     		pop	{r3, pc}
+ 4781              		.cfi_endproc
+ 4782              	.LFE387:
+ 4784              		.section	.text.UART_DMATxAbortCallback,"ax",%progbits
+ 4785              		.align	1
+ 4786              		.syntax unified
+ 4787              		.thumb
+ 4788              		.thumb_func
+ 4790              	UART_DMATxAbortCallback:
+ 4791              	.LVL422:
+ 4792              	.LFB386:
+3815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 4793              		.loc 1 3815 1 is_stmt 1 view -0
+ 4794              		.cfi_startproc
+ 4795              		@ args = 0, pretend = 0, frame = 0
+ 4796              		@ frame_needed = 0, uses_anonymous_args = 0
+3815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 4797              		.loc 1 3815 1 is_stmt 0 view .LVU1609
+ 4798 0000 08B5     		push	{r3, lr}
+ 4799              	.LCFI19:
+ 4800              		.cfi_def_cfa_offset 8
+ 4801              		.cfi_offset 3, -8
+ 4802              		.cfi_offset 14, -4
+3816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4803              		.loc 1 3816 3 is_stmt 1 view .LVU1610
+3816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 203
+
+
+ 4804              		.loc 1 3816 23 is_stmt 0 view .LVU1611
+ 4805 0002 806A     		ldr	r0, [r0, #40]
+ 4806              	.LVL423:
+3818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4807              		.loc 1 3818 3 is_stmt 1 view .LVU1612
+3818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4808              		.loc 1 3818 8 is_stmt 0 view .LVU1613
+ 4809 0004 836F     		ldr	r3, [r0, #120]
+3818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4810              		.loc 1 3818 36 view .LVU1614
+ 4811 0006 0022     		movs	r2, #0
+ 4812 0008 9A63     		str	r2, [r3, #56]
+3821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4813              		.loc 1 3821 3 is_stmt 1 view .LVU1615
+3821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4814              		.loc 1 3821 12 is_stmt 0 view .LVU1616
+ 4815 000a C36F     		ldr	r3, [r0, #124]
+3821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4816              		.loc 1 3821 6 view .LVU1617
+ 4817 000c 0BB1     		cbz	r3, .L201
+3823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4818              		.loc 1 3823 5 is_stmt 1 view .LVU1618
+3823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4819              		.loc 1 3823 22 is_stmt 0 view .LVU1619
+ 4820 000e 9B6B     		ldr	r3, [r3, #56]
+3823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 4821              		.loc 1 3823 8 view .LVU1620
+ 4822 0010 B3B9     		cbnz	r3, .L200
+ 4823              	.L201:
+3830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+ 4824              		.loc 1 3830 3 is_stmt 1 view .LVU1621
+3830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = 0U;
+ 4825              		.loc 1 3830 22 is_stmt 0 view .LVU1622
+ 4826 0012 0023     		movs	r3, #0
+ 4827 0014 A0F85630 		strh	r3, [r0, #86]	@ movhi
+3831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4828              		.loc 1 3831 3 is_stmt 1 view .LVU1623
+3831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4829              		.loc 1 3831 22 is_stmt 0 view .LVU1624
+ 4830 0018 A0F85E30 		strh	r3, [r0, #94]	@ movhi
+3834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4831              		.loc 1 3834 3 is_stmt 1 view .LVU1625
+3834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4832              		.loc 1 3834 20 is_stmt 0 view .LVU1626
+ 4833 001c C0F88C30 		str	r3, [r0, #140]
+3837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4834              		.loc 1 3837 3 is_stmt 1 view .LVU1627
+ 4835 0020 0368     		ldr	r3, [r0]
+ 4836 0022 0F22     		movs	r2, #15
+ 4837 0024 1A62     		str	r2, [r3, #32]
+3840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4838              		.loc 1 3840 3 view .LVU1628
+3840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4839              		.loc 1 3840 12 is_stmt 0 view .LVU1629
+ 4840 0026 436E     		ldr	r3, [r0, #100]
+3840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 4841              		.loc 1 3840 6 view .LVU1630
+ARM GAS  /tmp/cceWHrnJ.s 			page 204
+
+
+ 4842 0028 B3F1005F 		cmp	r3, #536870912
+ 4843 002c 09D0     		beq	.L205
+ 4844              	.L203:
+3846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 4845              		.loc 1 3846 3 is_stmt 1 view .LVU1631
+3846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 4846              		.loc 1 3846 18 is_stmt 0 view .LVU1632
+ 4847 002e 2023     		movs	r3, #32
+ 4848 0030 C0F88430 		str	r3, [r0, #132]
+3847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 4849              		.loc 1 3847 3 is_stmt 1 view .LVU1633
+3847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 4850              		.loc 1 3847 18 is_stmt 0 view .LVU1634
+ 4851 0034 C0F88830 		str	r3, [r0, #136]
+3848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4852              		.loc 1 3848 3 is_stmt 1 view .LVU1635
+3848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4853              		.loc 1 3848 24 is_stmt 0 view .LVU1636
+ 4854 0038 0023     		movs	r3, #0
+ 4855 003a C366     		str	r3, [r0, #108]
+3856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 4856              		.loc 1 3856 3 is_stmt 1 view .LVU1637
+ 4857 003c FFF7FEFF 		bl	HAL_UART_AbortCpltCallback
+ 4858              	.LVL424:
+ 4859              	.L200:
+3858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4860              		.loc 1 3858 1 is_stmt 0 view .LVU1638
+ 4861 0040 08BD     		pop	{r3, pc}
+ 4862              	.LVL425:
+ 4863              	.L205:
+3842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 4864              		.loc 1 3842 5 is_stmt 1 view .LVU1639
+ 4865 0042 0268     		ldr	r2, [r0]
+ 4866 0044 9369     		ldr	r3, [r2, #24]
+ 4867 0046 43F01003 		orr	r3, r3, #16
+ 4868 004a 9361     		str	r3, [r2, #24]
+ 4869 004c EFE7     		b	.L203
+ 4870              		.cfi_endproc
+ 4871              	.LFE386:
+ 4873              		.section	.text.HAL_UART_AbortTransmitCpltCallback,"ax",%progbits
+ 4874              		.align	1
+ 4875              		.weak	HAL_UART_AbortTransmitCpltCallback
+ 4876              		.syntax unified
+ 4877              		.thumb
+ 4878              		.thumb_func
+ 4880              	HAL_UART_AbortTransmitCpltCallback:
+ 4881              	.LVL426:
+ 4882              	.LFB358:
+2649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 4883              		.loc 1 2649 1 view -0
+ 4884              		.cfi_startproc
+ 4885              		@ args = 0, pretend = 0, frame = 0
+ 4886              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4887              		@ link register save eliminated.
+2651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4888              		.loc 1 2651 3 view .LVU1641
+2656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 205
+
+
+ 4889              		.loc 1 2656 1 is_stmt 0 view .LVU1642
+ 4890 0000 7047     		bx	lr
+ 4891              		.cfi_endproc
+ 4892              	.LFE358:
+ 4894              		.section	.text.HAL_UART_AbortTransmit_IT,"ax",%progbits
+ 4895              		.align	1
+ 4896              		.global	HAL_UART_AbortTransmit_IT
+ 4897              		.syntax unified
+ 4898              		.thumb
+ 4899              		.thumb_func
+ 4901              	HAL_UART_AbortTransmit_IT:
+ 4902              	.LVL427:
+ 4903              	.LFB349:
+2055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable interrupts */
+ 4904              		.loc 1 2055 1 is_stmt 1 view -0
+ 4905              		.cfi_startproc
+ 4906              		@ args = 0, pretend = 0, frame = 0
+ 4907              		@ frame_needed = 0, uses_anonymous_args = 0
+2055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable interrupts */
+ 4908              		.loc 1 2055 1 is_stmt 0 view .LVU1644
+ 4909 0000 10B5     		push	{r4, lr}
+ 4910              	.LCFI20:
+ 4911              		.cfi_def_cfa_offset 8
+ 4912              		.cfi_offset 4, -8
+ 4913              		.cfi_offset 14, -4
+ 4914 0002 0446     		mov	r4, r0
+ 4915              	.L208:
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 4916              		.loc 1 2057 3 is_stmt 1 discriminator 1 view .LVU1645
+ 4917              	.LBB739:
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 4918              		.loc 1 2057 3 discriminator 1 view .LVU1646
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 4919              		.loc 1 2057 3 discriminator 1 view .LVU1647
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 4920              		.loc 1 2057 3 discriminator 1 view .LVU1648
+ 4921 0004 2268     		ldr	r2, [r4]
+ 4922              	.LVL428:
+ 4923              	.LBB740:
+ 4924              	.LBI740:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4925              		.loc 2 1151 31 discriminator 1 view .LVU1649
+ 4926              	.LBB741:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4927              		.loc 2 1153 5 discriminator 1 view .LVU1650
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4928              		.loc 2 1155 4 discriminator 1 view .LVU1651
+ 4929              		.syntax unified
+ 4930              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4931 0006 52E8003F 		ldrex r3, [r2]
+ 4932              	@ 0 "" 2
+ 4933              	.LVL429:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4934              		.loc 2 1156 4 discriminator 1 view .LVU1652
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4935              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1653
+ 4936              		.thumb
+ARM GAS  /tmp/cceWHrnJ.s 			page 206
+
+
+ 4937              		.syntax unified
+ 4938              	.LBE741:
+ 4939              	.LBE740:
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 4940              		.loc 1 2057 3 discriminator 1 view .LVU1654
+ 4941 000a 23F0C003 		bic	r3, r3, #192
+ 4942              	.LVL430:
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 4943              		.loc 1 2057 3 is_stmt 1 discriminator 1 view .LVU1655
+ 4944              	.LBB742:
+ 4945              	.LBI742:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4946              		.loc 2 1202 31 discriminator 1 view .LVU1656
+ 4947              	.LBB743:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 4948              		.loc 2 1204 4 discriminator 1 view .LVU1657
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4949              		.loc 2 1206 4 discriminator 1 view .LVU1658
+ 4950              		.syntax unified
+ 4951              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4952 000e 42E80031 		strex r1, r3, [r2]
+ 4953              	@ 0 "" 2
+ 4954              	.LVL431:
+ 4955              		.loc 2 1207 4 discriminator 1 view .LVU1659
+ 4956              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1660
+ 4957              		.thumb
+ 4958              		.syntax unified
+ 4959              	.LBE743:
+ 4960              	.LBE742:
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 4961              		.loc 1 2057 3 discriminator 1 view .LVU1661
+ 4962 0012 0029     		cmp	r1, #0
+ 4963 0014 F6D1     		bne	.L208
+ 4964              	.LVL432:
+ 4965              	.L209:
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 4966              		.loc 1 2057 3 discriminator 1 view .LVU1662
+ 4967              	.LBE739:
+2057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ 4968              		.loc 1 2057 3 is_stmt 1 discriminator 1 view .LVU1663
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4969              		.loc 1 2058 3 discriminator 1 view .LVU1664
+ 4970              	.LBB744:
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4971              		.loc 1 2058 3 discriminator 1 view .LVU1665
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4972              		.loc 1 2058 3 discriminator 1 view .LVU1666
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4973              		.loc 1 2058 3 discriminator 1 view .LVU1667
+ 4974 0016 2268     		ldr	r2, [r4]
+ 4975              	.LVL433:
+ 4976              	.LBB745:
+ 4977              	.LBI745:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 4978              		.loc 2 1151 31 discriminator 1 view .LVU1668
+ 4979              	.LBB746:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 207
+
+
+ 4980              		.loc 2 1153 5 discriminator 1 view .LVU1669
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4981              		.loc 2 1155 4 discriminator 1 view .LVU1670
+ 4982 0018 02F10803 		add	r3, r2, #8
+ 4983              	.LVL434:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4984              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU1671
+ 4985              		.syntax unified
+ 4986              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4987 001c 53E8003F 		ldrex r3, [r3]
+ 4988              	@ 0 "" 2
+ 4989              	.LVL435:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4990              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU1672
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 4991              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1673
+ 4992              		.thumb
+ 4993              		.syntax unified
+ 4994              	.LBE746:
+ 4995              	.LBE745:
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4996              		.loc 1 2058 3 discriminator 1 view .LVU1674
+ 4997 0020 23F40003 		bic	r3, r3, #8388608
+ 4998              	.LVL436:
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 4999              		.loc 1 2058 3 is_stmt 1 discriminator 1 view .LVU1675
+ 5000              	.LBB747:
+ 5001              	.LBI747:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5002              		.loc 2 1202 31 discriminator 1 view .LVU1676
+ 5003              	.LBB748:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 5004              		.loc 2 1204 4 discriminator 1 view .LVU1677
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5005              		.loc 2 1206 4 discriminator 1 view .LVU1678
+ 5006 0024 0832     		adds	r2, r2, #8
+ 5007              	.LVL437:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5008              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU1679
+ 5009              		.syntax unified
+ 5010              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5011 0026 42E80031 		strex r1, r3, [r2]
+ 5012              	@ 0 "" 2
+ 5013              	.LVL438:
+ 5014              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU1680
+ 5015              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1681
+ 5016              		.thumb
+ 5017              		.syntax unified
+ 5018              	.LBE748:
+ 5019              	.LBE747:
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5020              		.loc 1 2058 3 discriminator 1 view .LVU1682
+ 5021 002a 0029     		cmp	r1, #0
+ 5022 002c F3D1     		bne	.L209
+ 5023              	.LBE744:
+2058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5024              		.loc 1 2058 3 is_stmt 1 discriminator 2 view .LVU1683
+ARM GAS  /tmp/cceWHrnJ.s 			page 208
+
+
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5025              		.loc 1 2061 3 discriminator 2 view .LVU1684
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5026              		.loc 1 2061 7 is_stmt 0 discriminator 2 view .LVU1685
+ 5027 002e 2368     		ldr	r3, [r4]
+ 5028              	.LVL439:
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5029              		.loc 1 2061 7 discriminator 2 view .LVU1686
+ 5030 0030 9A68     		ldr	r2, [r3, #8]
+2061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5031              		.loc 1 2061 6 discriminator 2 view .LVU1687
+ 5032 0032 12F0800F 		tst	r2, #128
+ 5033 0036 22D0     		beq	.L210
+ 5034              	.L211:
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5035              		.loc 1 2064 5 is_stmt 1 discriminator 1 view .LVU1688
+ 5036              	.LBB749:
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5037              		.loc 1 2064 5 discriminator 1 view .LVU1689
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5038              		.loc 1 2064 5 discriminator 1 view .LVU1690
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5039              		.loc 1 2064 5 discriminator 1 view .LVU1691
+ 5040 0038 2268     		ldr	r2, [r4]
+ 5041              	.LVL440:
+ 5042              	.LBB750:
+ 5043              	.LBI750:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5044              		.loc 2 1151 31 discriminator 1 view .LVU1692
+ 5045              	.LBB751:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 5046              		.loc 2 1153 5 discriminator 1 view .LVU1693
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5047              		.loc 2 1155 4 discriminator 1 view .LVU1694
+ 5048 003a 02F10803 		add	r3, r2, #8
+ 5049              	.LVL441:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5050              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU1695
+ 5051              		.syntax unified
+ 5052              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5053 003e 53E8003F 		ldrex r3, [r3]
+ 5054              	@ 0 "" 2
+ 5055              	.LVL442:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5056              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU1696
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5057              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1697
+ 5058              		.thumb
+ 5059              		.syntax unified
+ 5060              	.LBE751:
+ 5061              	.LBE750:
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5062              		.loc 1 2064 5 discriminator 1 view .LVU1698
+ 5063 0042 23F08003 		bic	r3, r3, #128
+ 5064              	.LVL443:
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5065              		.loc 1 2064 5 is_stmt 1 discriminator 1 view .LVU1699
+ARM GAS  /tmp/cceWHrnJ.s 			page 209
+
+
+ 5066              	.LBB752:
+ 5067              	.LBI752:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5068              		.loc 2 1202 31 discriminator 1 view .LVU1700
+ 5069              	.LBB753:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 5070              		.loc 2 1204 4 discriminator 1 view .LVU1701
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5071              		.loc 2 1206 4 discriminator 1 view .LVU1702
+ 5072 0046 0832     		adds	r2, r2, #8
+ 5073              	.LVL444:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5074              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU1703
+ 5075              		.syntax unified
+ 5076              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5077 0048 42E80031 		strex r1, r3, [r2]
+ 5078              	@ 0 "" 2
+ 5079              	.LVL445:
+ 5080              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU1704
+ 5081              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1705
+ 5082              		.thumb
+ 5083              		.syntax unified
+ 5084              	.LBE753:
+ 5085              	.LBE752:
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5086              		.loc 1 2064 5 discriminator 1 view .LVU1706
+ 5087 004c 0029     		cmp	r1, #0
+ 5088 004e F3D1     		bne	.L211
+ 5089              	.LBE749:
+2064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5090              		.loc 1 2064 5 is_stmt 1 discriminator 2 view .LVU1707
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5091              		.loc 1 2067 5 discriminator 2 view .LVU1708
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5092              		.loc 1 2067 14 is_stmt 0 discriminator 2 view .LVU1709
+ 5093 0050 A36F     		ldr	r3, [r4, #120]
+ 5094              	.LVL446:
+2067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5095              		.loc 1 2067 8 discriminator 2 view .LVU1710
+ 5096 0052 4BB1     		cbz	r3, .L212
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5097              		.loc 1 2071 7 is_stmt 1 view .LVU1711
+2071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5098              		.loc 1 2071 40 is_stmt 0 view .LVU1712
+ 5099 0054 144A     		ldr	r2, .L217
+ 5100 0056 9A63     		str	r2, [r3, #56]
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 5101              		.loc 1 2074 7 is_stmt 1 view .LVU1713
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 5102              		.loc 1 2074 11 is_stmt 0 view .LVU1714
+ 5103 0058 A06F     		ldr	r0, [r4, #120]
+ 5104              	.LVL447:
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 5105              		.loc 1 2074 11 view .LVU1715
+ 5106 005a FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 5107              	.LVL448:
+2074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ARM GAS  /tmp/cceWHrnJ.s 			page 210
+
+
+ 5108              		.loc 1 2074 10 view .LVU1716
+ 5109 005e E0B1     		cbz	r0, .L213
+2077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 5110              		.loc 1 2077 9 is_stmt 1 view .LVU1717
+2077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 5111              		.loc 1 2077 14 is_stmt 0 view .LVU1718
+ 5112 0060 A06F     		ldr	r0, [r4, #120]
+2077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 5113              		.loc 1 2077 22 view .LVU1719
+ 5114 0062 836B     		ldr	r3, [r0, #56]
+2077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 5115              		.loc 1 2077 9 view .LVU1720
+ 5116 0064 9847     		blx	r3
+ 5117              	.LVL449:
+ 5118 0066 18E0     		b	.L213
+ 5119              	.LVL450:
+ 5120              	.L212:
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5121              		.loc 1 2083 7 is_stmt 1 view .LVU1721
+2083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5122              		.loc 1 2083 26 is_stmt 0 view .LVU1722
+ 5123 0068 0023     		movs	r3, #0
+ 5124 006a A4F85630 		strh	r3, [r4, #86]	@ movhi
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5125              		.loc 1 2086 7 is_stmt 1 view .LVU1723
+2086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5126              		.loc 1 2086 20 is_stmt 0 view .LVU1724
+ 5127 006e 6367     		str	r3, [r4, #116]
+2089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5128              		.loc 1 2089 7 is_stmt 1 view .LVU1725
+2089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5129              		.loc 1 2089 21 is_stmt 0 view .LVU1726
+ 5130 0070 2023     		movs	r3, #32
+ 5131 0072 C4F88430 		str	r3, [r4, #132]
+2097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 5132              		.loc 1 2097 7 is_stmt 1 view .LVU1727
+ 5133 0076 2046     		mov	r0, r4
+ 5134              	.LVL451:
+2097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 5135              		.loc 1 2097 7 is_stmt 0 view .LVU1728
+ 5136 0078 FFF7FEFF 		bl	HAL_UART_AbortTransmitCpltCallback
+ 5137              	.LVL452:
+ 5138 007c 0DE0     		b	.L213
+ 5139              	.LVL453:
+ 5140              	.L210:
+2104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5141              		.loc 1 2104 5 is_stmt 1 view .LVU1729
+2104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5142              		.loc 1 2104 24 is_stmt 0 view .LVU1730
+ 5143 007e 0022     		movs	r2, #0
+ 5144 0080 A4F85620 		strh	r2, [r4, #86]	@ movhi
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5145              		.loc 1 2107 5 is_stmt 1 view .LVU1731
+2107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5146              		.loc 1 2107 18 is_stmt 0 view .LVU1732
+ 5147 0084 6267     		str	r2, [r4, #116]
+2110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ARM GAS  /tmp/cceWHrnJ.s 			page 211
+
+
+ 5148              		.loc 1 2110 5 is_stmt 1 view .LVU1733
+2110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5149              		.loc 1 2110 14 is_stmt 0 view .LVU1734
+ 5150 0086 626E     		ldr	r2, [r4, #100]
+2110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5151              		.loc 1 2110 8 view .LVU1735
+ 5152 0088 B2F1005F 		cmp	r2, #536870912
+ 5153 008c 07D0     		beq	.L216
+ 5154              	.L214:
+2116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5155              		.loc 1 2116 5 is_stmt 1 view .LVU1736
+2116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5156              		.loc 1 2116 19 is_stmt 0 view .LVU1737
+ 5157 008e 2023     		movs	r3, #32
+ 5158 0090 C4F88430 		str	r3, [r4, #132]
+2124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 5159              		.loc 1 2124 5 is_stmt 1 view .LVU1738
+ 5160 0094 2046     		mov	r0, r4
+ 5161              	.LVL454:
+2124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 5162              		.loc 1 2124 5 is_stmt 0 view .LVU1739
+ 5163 0096 FFF7FEFF 		bl	HAL_UART_AbortTransmitCpltCallback
+ 5164              	.LVL455:
+ 5165              	.L213:
+2128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 5166              		.loc 1 2128 3 is_stmt 1 view .LVU1740
+2129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5167              		.loc 1 2129 1 is_stmt 0 view .LVU1741
+ 5168 009a 0020     		movs	r0, #0
+ 5169 009c 10BD     		pop	{r4, pc}
+ 5170              	.LVL456:
+ 5171              	.L216:
+2112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5172              		.loc 1 2112 7 is_stmt 1 view .LVU1742
+ 5173 009e 9A69     		ldr	r2, [r3, #24]
+ 5174 00a0 42F01002 		orr	r2, r2, #16
+ 5175 00a4 9A61     		str	r2, [r3, #24]
+ 5176 00a6 F2E7     		b	.L214
+ 5177              	.L218:
+ 5178              		.align	2
+ 5179              	.L217:
+ 5180 00a8 00000000 		.word	UART_DMATxOnlyAbortCallback
+ 5181              		.cfi_endproc
+ 5182              	.LFE349:
+ 5184              		.section	.text.UART_DMATxOnlyAbortCallback,"ax",%progbits
+ 5185              		.align	1
+ 5186              		.syntax unified
+ 5187              		.thumb
+ 5188              		.thumb_func
+ 5190              	UART_DMATxOnlyAbortCallback:
+ 5191              	.LVL457:
+ 5192              	.LFB388:
+3922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 5193              		.loc 1 3922 1 view -0
+ 5194              		.cfi_startproc
+ 5195              		@ args = 0, pretend = 0, frame = 0
+ 5196              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cceWHrnJ.s 			page 212
+
+
+3922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 5197              		.loc 1 3922 1 is_stmt 0 view .LVU1744
+ 5198 0000 08B5     		push	{r3, lr}
+ 5199              	.LCFI21:
+ 5200              		.cfi_def_cfa_offset 8
+ 5201              		.cfi_offset 3, -8
+ 5202              		.cfi_offset 14, -4
+3923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5203              		.loc 1 3923 3 is_stmt 1 view .LVU1745
+3923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5204              		.loc 1 3923 23 is_stmt 0 view .LVU1746
+ 5205 0002 806A     		ldr	r0, [r0, #40]
+ 5206              	.LVL458:
+3925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5207              		.loc 1 3925 3 is_stmt 1 view .LVU1747
+3925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5208              		.loc 1 3925 22 is_stmt 0 view .LVU1748
+ 5209 0004 0023     		movs	r3, #0
+ 5210 0006 A0F85630 		strh	r3, [r0, #86]	@ movhi
+3928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5211              		.loc 1 3928 3 is_stmt 1 view .LVU1749
+3928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5212              		.loc 1 3928 12 is_stmt 0 view .LVU1750
+ 5213 000a 436E     		ldr	r3, [r0, #100]
+3928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5214              		.loc 1 3928 6 view .LVU1751
+ 5215 000c B3F1005F 		cmp	r3, #536870912
+ 5216 0010 05D0     		beq	.L222
+ 5217              	.L220:
+3934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5218              		.loc 1 3934 3 is_stmt 1 view .LVU1752
+3934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5219              		.loc 1 3934 17 is_stmt 0 view .LVU1753
+ 5220 0012 2023     		movs	r3, #32
+ 5221 0014 C0F88430 		str	r3, [r0, #132]
+3942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 5222              		.loc 1 3942 3 is_stmt 1 view .LVU1754
+ 5223 0018 FFF7FEFF 		bl	HAL_UART_AbortTransmitCpltCallback
+ 5224              	.LVL459:
+3944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5225              		.loc 1 3944 1 is_stmt 0 view .LVU1755
+ 5226 001c 08BD     		pop	{r3, pc}
+ 5227              	.LVL460:
+ 5228              	.L222:
+3930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 5229              		.loc 1 3930 5 is_stmt 1 view .LVU1756
+ 5230 001e 0268     		ldr	r2, [r0]
+ 5231 0020 9369     		ldr	r3, [r2, #24]
+ 5232 0022 43F01003 		orr	r3, r3, #16
+ 5233 0026 9361     		str	r3, [r2, #24]
+ 5234 0028 F3E7     		b	.L220
+ 5235              		.cfi_endproc
+ 5236              	.LFE388:
+ 5238              		.section	.text.HAL_UART_AbortReceiveCpltCallback,"ax",%progbits
+ 5239              		.align	1
+ 5240              		.weak	HAL_UART_AbortReceiveCpltCallback
+ 5241              		.syntax unified
+ARM GAS  /tmp/cceWHrnJ.s 			page 213
+
+
+ 5242              		.thumb
+ 5243              		.thumb_func
+ 5245              	HAL_UART_AbortReceiveCpltCallback:
+ 5246              	.LVL461:
+ 5247              	.LFB359:
+2664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 5248              		.loc 1 2664 1 view -0
+ 5249              		.cfi_startproc
+ 5250              		@ args = 0, pretend = 0, frame = 0
+ 5251              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5252              		@ link register save eliminated.
+2666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5253              		.loc 1 2666 3 view .LVU1758
+2671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5254              		.loc 1 2671 1 is_stmt 0 view .LVU1759
+ 5255 0000 7047     		bx	lr
+ 5256              		.cfi_endproc
+ 5257              	.LFE359:
+ 5259              		.section	.text.HAL_UART_AbortReceive_IT,"ax",%progbits
+ 5260              		.align	1
+ 5261              		.global	HAL_UART_AbortReceive_IT
+ 5262              		.syntax unified
+ 5263              		.thumb
+ 5264              		.thumb_func
+ 5266              	HAL_UART_AbortReceive_IT:
+ 5267              	.LVL462:
+ 5268              	.LFB350:
+2146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ 5269              		.loc 1 2146 1 is_stmt 1 view -0
+ 5270              		.cfi_startproc
+ 5271              		@ args = 0, pretend = 0, frame = 0
+ 5272              		@ frame_needed = 0, uses_anonymous_args = 0
+2146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ 5273              		.loc 1 2146 1 is_stmt 0 view .LVU1761
+ 5274 0000 10B5     		push	{r4, lr}
+ 5275              	.LCFI22:
+ 5276              		.cfi_def_cfa_offset 8
+ 5277              		.cfi_offset 4, -8
+ 5278              		.cfi_offset 14, -4
+ 5279 0002 0446     		mov	r4, r0
+ 5280              	.L225:
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 5281              		.loc 1 2148 3 is_stmt 1 discriminator 1 view .LVU1762
+ 5282              	.LBB754:
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 5283              		.loc 1 2148 3 discriminator 1 view .LVU1763
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 5284              		.loc 1 2148 3 discriminator 1 view .LVU1764
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 5285              		.loc 1 2148 3 discriminator 1 view .LVU1765
+ 5286 0004 2268     		ldr	r2, [r4]
+ 5287              	.LVL463:
+ 5288              	.LBB755:
+ 5289              	.LBI755:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5290              		.loc 2 1151 31 discriminator 1 view .LVU1766
+ 5291              	.LBB756:
+ARM GAS  /tmp/cceWHrnJ.s 			page 214
+
+
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 5292              		.loc 2 1153 5 discriminator 1 view .LVU1767
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5293              		.loc 2 1155 4 discriminator 1 view .LVU1768
+ 5294              		.syntax unified
+ 5295              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5296 0006 52E8003F 		ldrex r3, [r2]
+ 5297              	@ 0 "" 2
+ 5298              	.LVL464:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5299              		.loc 2 1156 4 discriminator 1 view .LVU1769
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5300              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1770
+ 5301              		.thumb
+ 5302              		.syntax unified
+ 5303              	.LBE756:
+ 5304              	.LBE755:
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 5305              		.loc 1 2148 3 discriminator 1 view .LVU1771
+ 5306 000a 23F49073 		bic	r3, r3, #288
+ 5307              	.LVL465:
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 5308              		.loc 1 2148 3 is_stmt 1 discriminator 1 view .LVU1772
+ 5309              	.LBB757:
+ 5310              	.LBI757:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5311              		.loc 2 1202 31 discriminator 1 view .LVU1773
+ 5312              	.LBB758:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 5313              		.loc 2 1204 4 discriminator 1 view .LVU1774
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5314              		.loc 2 1206 4 discriminator 1 view .LVU1775
+ 5315              		.syntax unified
+ 5316              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5317 000e 42E80031 		strex r1, r3, [r2]
+ 5318              	@ 0 "" 2
+ 5319              	.LVL466:
+ 5320              		.loc 2 1207 4 discriminator 1 view .LVU1776
+ 5321              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1777
+ 5322              		.thumb
+ 5323              		.syntax unified
+ 5324              	.LBE758:
+ 5325              	.LBE757:
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 5326              		.loc 1 2148 3 discriminator 1 view .LVU1778
+ 5327 0012 0029     		cmp	r1, #0
+ 5328 0014 F6D1     		bne	.L225
+ 5329              	.LVL467:
+ 5330              	.L226:
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 5331              		.loc 1 2148 3 discriminator 1 view .LVU1779
+ 5332              	.LBE754:
+2148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 5333              		.loc 1 2148 3 is_stmt 1 discriminator 1 view .LVU1780
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5334              		.loc 1 2149 3 discriminator 1 view .LVU1781
+ 5335              	.LBB759:
+ARM GAS  /tmp/cceWHrnJ.s 			page 215
+
+
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5336              		.loc 1 2149 3 discriminator 1 view .LVU1782
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5337              		.loc 1 2149 3 discriminator 1 view .LVU1783
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5338              		.loc 1 2149 3 discriminator 1 view .LVU1784
+ 5339 0016 2268     		ldr	r2, [r4]
+ 5340              	.LVL468:
+ 5341              	.LBB760:
+ 5342              	.LBI760:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5343              		.loc 2 1151 31 discriminator 1 view .LVU1785
+ 5344              	.LBB761:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 5345              		.loc 2 1153 5 discriminator 1 view .LVU1786
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5346              		.loc 2 1155 4 discriminator 1 view .LVU1787
+ 5347 0018 02F10803 		add	r3, r2, #8
+ 5348              	.LVL469:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5349              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU1788
+ 5350              		.syntax unified
+ 5351              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5352 001c 53E8003F 		ldrex r3, [r3]
+ 5353              	@ 0 "" 2
+ 5354              	.LVL470:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5355              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU1789
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5356              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1790
+ 5357              		.thumb
+ 5358              		.syntax unified
+ 5359              	.LBE761:
+ 5360              	.LBE760:
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5361              		.loc 1 2149 3 discriminator 1 view .LVU1791
+ 5362 0020 23F08053 		bic	r3, r3, #268435456
+ 5363 0024 23F00103 		bic	r3, r3, #1
+ 5364              	.LVL471:
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5365              		.loc 1 2149 3 is_stmt 1 discriminator 1 view .LVU1792
+ 5366              	.LBB762:
+ 5367              	.LBI762:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5368              		.loc 2 1202 31 discriminator 1 view .LVU1793
+ 5369              	.LBB763:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 5370              		.loc 2 1204 4 discriminator 1 view .LVU1794
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5371              		.loc 2 1206 4 discriminator 1 view .LVU1795
+ 5372 0028 0832     		adds	r2, r2, #8
+ 5373              	.LVL472:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5374              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU1796
+ 5375              		.syntax unified
+ 5376              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5377 002a 42E80031 		strex r1, r3, [r2]
+ARM GAS  /tmp/cceWHrnJ.s 			page 216
+
+
+ 5378              	@ 0 "" 2
+ 5379              	.LVL473:
+ 5380              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU1797
+ 5381              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1798
+ 5382              		.thumb
+ 5383              		.syntax unified
+ 5384              	.LBE763:
+ 5385              	.LBE762:
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5386              		.loc 1 2149 3 discriminator 1 view .LVU1799
+ 5387 002e 0029     		cmp	r1, #0
+ 5388 0030 F1D1     		bne	.L226
+ 5389              	.LBE759:
+2149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5390              		.loc 1 2149 3 is_stmt 1 discriminator 2 view .LVU1800
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5391              		.loc 1 2152 3 discriminator 2 view .LVU1801
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5392              		.loc 1 2152 12 is_stmt 0 discriminator 2 view .LVU1802
+ 5393 0032 E36E     		ldr	r3, [r4, #108]
+ 5394              	.LVL474:
+2152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5395              		.loc 1 2152 6 discriminator 2 view .LVU1803
+ 5396 0034 012B     		cmp	r3, #1
+ 5397 0036 1CD0     		beq	.L228
+ 5398              	.L227:
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 5399              		.loc 1 2154 5 is_stmt 1 discriminator 2 view .LVU1804
+2158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5400              		.loc 1 2158 3 discriminator 2 view .LVU1805
+2158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5401              		.loc 1 2158 7 is_stmt 0 discriminator 2 view .LVU1806
+ 5402 0038 2368     		ldr	r3, [r4]
+ 5403 003a 9A68     		ldr	r2, [r3, #8]
+2158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5404              		.loc 1 2158 6 discriminator 2 view .LVU1807
+ 5405 003c 12F0400F 		tst	r2, #64
+ 5406 0040 35D0     		beq	.L229
+ 5407              	.L230:
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5408              		.loc 1 2161 5 is_stmt 1 discriminator 1 view .LVU1808
+ 5409              	.LBB764:
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5410              		.loc 1 2161 5 discriminator 1 view .LVU1809
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5411              		.loc 1 2161 5 discriminator 1 view .LVU1810
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5412              		.loc 1 2161 5 discriminator 1 view .LVU1811
+ 5413 0042 2268     		ldr	r2, [r4]
+ 5414              	.LVL475:
+ 5415              	.LBB765:
+ 5416              	.LBI765:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5417              		.loc 2 1151 31 discriminator 1 view .LVU1812
+ 5418              	.LBB766:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 5419              		.loc 2 1153 5 discriminator 1 view .LVU1813
+ARM GAS  /tmp/cceWHrnJ.s 			page 217
+
+
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5420              		.loc 2 1155 4 discriminator 1 view .LVU1814
+ 5421 0044 02F10803 		add	r3, r2, #8
+ 5422              	.LVL476:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5423              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU1815
+ 5424              		.syntax unified
+ 5425              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5426 0048 53E8003F 		ldrex r3, [r3]
+ 5427              	@ 0 "" 2
+ 5428              	.LVL477:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5429              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU1816
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5430              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1817
+ 5431              		.thumb
+ 5432              		.syntax unified
+ 5433              	.LBE766:
+ 5434              	.LBE765:
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5435              		.loc 1 2161 5 discriminator 1 view .LVU1818
+ 5436 004c 23F04003 		bic	r3, r3, #64
+ 5437              	.LVL478:
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5438              		.loc 1 2161 5 is_stmt 1 discriminator 1 view .LVU1819
+ 5439              	.LBB767:
+ 5440              	.LBI767:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5441              		.loc 2 1202 31 discriminator 1 view .LVU1820
+ 5442              	.LBB768:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 5443              		.loc 2 1204 4 discriminator 1 view .LVU1821
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5444              		.loc 2 1206 4 discriminator 1 view .LVU1822
+ 5445 0050 0832     		adds	r2, r2, #8
+ 5446              	.LVL479:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5447              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU1823
+ 5448              		.syntax unified
+ 5449              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5450 0052 42E80031 		strex r1, r3, [r2]
+ 5451              	@ 0 "" 2
+ 5452              	.LVL480:
+ 5453              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU1824
+ 5454              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1825
+ 5455              		.thumb
+ 5456              		.syntax unified
+ 5457              	.LBE768:
+ 5458              	.LBE767:
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5459              		.loc 1 2161 5 discriminator 1 view .LVU1826
+ 5460 0056 0029     		cmp	r1, #0
+ 5461 0058 F3D1     		bne	.L230
+ 5462              	.LBE764:
+2161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5463              		.loc 1 2161 5 is_stmt 1 discriminator 2 view .LVU1827
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ARM GAS  /tmp/cceWHrnJ.s 			page 218
+
+
+ 5464              		.loc 1 2164 5 discriminator 2 view .LVU1828
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5465              		.loc 1 2164 14 is_stmt 0 discriminator 2 view .LVU1829
+ 5466 005a E36F     		ldr	r3, [r4, #124]
+ 5467              	.LVL481:
+2164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5468              		.loc 1 2164 8 discriminator 2 view .LVU1830
+ 5469 005c 9BB1     		cbz	r3, .L231
+2168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5470              		.loc 1 2168 7 is_stmt 1 view .LVU1831
+2168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5471              		.loc 1 2168 40 is_stmt 0 view .LVU1832
+ 5472 005e 1B4A     		ldr	r2, .L234
+ 5473 0060 9A63     		str	r2, [r3, #56]
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 5474              		.loc 1 2171 7 is_stmt 1 view .LVU1833
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 5475              		.loc 1 2171 11 is_stmt 0 view .LVU1834
+ 5476 0062 E06F     		ldr	r0, [r4, #124]
+ 5477              	.LVL482:
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 5478              		.loc 1 2171 11 view .LVU1835
+ 5479 0064 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 5480              	.LVL483:
+2171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 5481              		.loc 1 2171 10 view .LVU1836
+ 5482 0068 70B3     		cbz	r0, .L232
+2174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 5483              		.loc 1 2174 9 is_stmt 1 view .LVU1837
+2174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 5484              		.loc 1 2174 14 is_stmt 0 view .LVU1838
+ 5485 006a E06F     		ldr	r0, [r4, #124]
+2174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 5486              		.loc 1 2174 22 view .LVU1839
+ 5487 006c 836B     		ldr	r3, [r0, #56]
+2174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 5488              		.loc 1 2174 9 view .LVU1840
+ 5489 006e 9847     		blx	r3
+ 5490              	.LVL484:
+ 5491 0070 2AE0     		b	.L232
+ 5492              	.LVL485:
+ 5493              	.L228:
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 5494              		.loc 1 2154 5 is_stmt 1 discriminator 1 view .LVU1841
+ 5495              	.LBB769:
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 5496              		.loc 1 2154 5 discriminator 1 view .LVU1842
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 5497              		.loc 1 2154 5 discriminator 1 view .LVU1843
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 5498              		.loc 1 2154 5 discriminator 1 view .LVU1844
+ 5499 0072 2268     		ldr	r2, [r4]
+ 5500              	.LVL486:
+ 5501              	.LBB770:
+ 5502              	.LBI770:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5503              		.loc 2 1151 31 discriminator 1 view .LVU1845
+ARM GAS  /tmp/cceWHrnJ.s 			page 219
+
+
+ 5504              	.LBB771:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 5505              		.loc 2 1153 5 discriminator 1 view .LVU1846
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5506              		.loc 2 1155 4 discriminator 1 view .LVU1847
+ 5507              		.syntax unified
+ 5508              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5509 0074 52E8003F 		ldrex r3, [r2]
+ 5510              	@ 0 "" 2
+ 5511              	.LVL487:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5512              		.loc 2 1156 4 discriminator 1 view .LVU1848
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5513              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU1849
+ 5514              		.thumb
+ 5515              		.syntax unified
+ 5516              	.LBE771:
+ 5517              	.LBE770:
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 5518              		.loc 1 2154 5 discriminator 1 view .LVU1850
+ 5519 0078 23F01003 		bic	r3, r3, #16
+ 5520              	.LVL488:
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 5521              		.loc 1 2154 5 is_stmt 1 discriminator 1 view .LVU1851
+ 5522              	.LBB772:
+ 5523              	.LBI772:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5524              		.loc 2 1202 31 discriminator 1 view .LVU1852
+ 5525              	.LBB773:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 5526              		.loc 2 1204 4 discriminator 1 view .LVU1853
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5527              		.loc 2 1206 4 discriminator 1 view .LVU1854
+ 5528              		.syntax unified
+ 5529              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5530 007c 42E80031 		strex r1, r3, [r2]
+ 5531              	@ 0 "" 2
+ 5532              	.LVL489:
+ 5533              		.loc 2 1207 4 discriminator 1 view .LVU1855
+ 5534              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU1856
+ 5535              		.thumb
+ 5536              		.syntax unified
+ 5537              	.LBE773:
+ 5538              	.LBE772:
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 5539              		.loc 1 2154 5 discriminator 1 view .LVU1857
+ 5540 0080 0029     		cmp	r1, #0
+ 5541 0082 F6D1     		bne	.L228
+ 5542 0084 D8E7     		b	.L227
+ 5543              	.LVL490:
+ 5544              	.L231:
+2154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 5545              		.loc 1 2154 5 discriminator 1 view .LVU1858
+ 5546              	.LBE769:
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5547              		.loc 1 2180 7 is_stmt 1 view .LVU1859
+2180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 220
+
+
+ 5548              		.loc 1 2180 26 is_stmt 0 view .LVU1860
+ 5549 0086 0023     		movs	r3, #0
+ 5550 0088 A4F85E30 		strh	r3, [r4, #94]	@ movhi
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5551              		.loc 1 2183 7 is_stmt 1 view .LVU1861
+2183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5552              		.loc 1 2183 25 is_stmt 0 view .LVU1862
+ 5553 008c A365     		str	r3, [r4, #88]
+2186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5554              		.loc 1 2186 7 is_stmt 1 view .LVU1863
+ 5555 008e 2268     		ldr	r2, [r4]
+ 5556 0090 0F21     		movs	r1, #15
+ 5557 0092 1162     		str	r1, [r2, #32]
+2189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5558              		.loc 1 2189 7 view .LVU1864
+ 5559 0094 2168     		ldr	r1, [r4]
+ 5560 0096 8A69     		ldr	r2, [r1, #24]
+ 5561 0098 42F00802 		orr	r2, r2, #8
+ 5562 009c 8A61     		str	r2, [r1, #24]
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 5563              		.loc 1 2192 7 view .LVU1865
+2192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 5564              		.loc 1 2192 22 is_stmt 0 view .LVU1866
+ 5565 009e 2022     		movs	r2, #32
+ 5566 00a0 C4F88820 		str	r2, [r4, #136]
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5567              		.loc 1 2193 7 is_stmt 1 view .LVU1867
+2193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5568              		.loc 1 2193 28 is_stmt 0 view .LVU1868
+ 5569 00a4 E366     		str	r3, [r4, #108]
+2201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 5570              		.loc 1 2201 7 is_stmt 1 view .LVU1869
+ 5571 00a6 2046     		mov	r0, r4
+ 5572              	.LVL491:
+2201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 5573              		.loc 1 2201 7 is_stmt 0 view .LVU1870
+ 5574 00a8 FFF7FEFF 		bl	HAL_UART_AbortReceiveCpltCallback
+ 5575              	.LVL492:
+ 5576 00ac 0CE0     		b	.L232
+ 5577              	.LVL493:
+ 5578              	.L229:
+2208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5579              		.loc 1 2208 5 is_stmt 1 view .LVU1871
+2208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5580              		.loc 1 2208 24 is_stmt 0 view .LVU1872
+ 5581 00ae 0022     		movs	r2, #0
+ 5582 00b0 A4F85E20 		strh	r2, [r4, #94]	@ movhi
+2211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5583              		.loc 1 2211 5 is_stmt 1 view .LVU1873
+2211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5584              		.loc 1 2211 23 is_stmt 0 view .LVU1874
+ 5585 00b4 A265     		str	r2, [r4, #88]
+2214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5586              		.loc 1 2214 5 is_stmt 1 view .LVU1875
+ 5587 00b6 0F21     		movs	r1, #15
+ 5588 00b8 1962     		str	r1, [r3, #32]
+2217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ARM GAS  /tmp/cceWHrnJ.s 			page 221
+
+
+ 5589              		.loc 1 2217 5 view .LVU1876
+2217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 5590              		.loc 1 2217 20 is_stmt 0 view .LVU1877
+ 5591 00ba 2023     		movs	r3, #32
+ 5592 00bc C4F88830 		str	r3, [r4, #136]
+2218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5593              		.loc 1 2218 5 is_stmt 1 view .LVU1878
+2218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5594              		.loc 1 2218 26 is_stmt 0 view .LVU1879
+ 5595 00c0 E266     		str	r2, [r4, #108]
+2226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 5596              		.loc 1 2226 5 is_stmt 1 view .LVU1880
+ 5597 00c2 2046     		mov	r0, r4
+ 5598              	.LVL494:
+2226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 5599              		.loc 1 2226 5 is_stmt 0 view .LVU1881
+ 5600 00c4 FFF7FEFF 		bl	HAL_UART_AbortReceiveCpltCallback
+ 5601              	.LVL495:
+ 5602              	.L232:
+2230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 5603              		.loc 1 2230 3 is_stmt 1 view .LVU1882
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5604              		.loc 1 2231 1 is_stmt 0 view .LVU1883
+ 5605 00c8 0020     		movs	r0, #0
+ 5606 00ca 10BD     		pop	{r4, pc}
+ 5607              	.LVL496:
+ 5608              	.L235:
+2231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5609              		.loc 1 2231 1 view .LVU1884
+ 5610              		.align	2
+ 5611              	.L234:
+ 5612 00cc 00000000 		.word	UART_DMARxOnlyAbortCallback
+ 5613              		.cfi_endproc
+ 5614              	.LFE350:
+ 5616              		.section	.text.UART_DMARxOnlyAbortCallback,"ax",%progbits
+ 5617              		.align	1
+ 5618              		.syntax unified
+ 5619              		.thumb
+ 5620              		.thumb_func
+ 5622              	UART_DMARxOnlyAbortCallback:
+ 5623              	.LVL497:
+ 5624              	.LFB389:
+3955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 5625              		.loc 1 3955 1 is_stmt 1 view -0
+ 5626              		.cfi_startproc
+ 5627              		@ args = 0, pretend = 0, frame = 0
+ 5628              		@ frame_needed = 0, uses_anonymous_args = 0
+3955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 5629              		.loc 1 3955 1 is_stmt 0 view .LVU1886
+ 5630 0000 08B5     		push	{r3, lr}
+ 5631              	.LCFI23:
+ 5632              		.cfi_def_cfa_offset 8
+ 5633              		.cfi_offset 3, -8
+ 5634              		.cfi_offset 14, -4
+3956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5635              		.loc 1 3956 3 is_stmt 1 view .LVU1887
+3956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 222
+
+
+ 5636              		.loc 1 3956 23 is_stmt 0 view .LVU1888
+ 5637 0002 806A     		ldr	r0, [r0, #40]
+ 5638              	.LVL498:
+3958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5639              		.loc 1 3958 3 is_stmt 1 view .LVU1889
+3958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5640              		.loc 1 3958 22 is_stmt 0 view .LVU1890
+ 5641 0004 0022     		movs	r2, #0
+ 5642 0006 A0F85E20 		strh	r2, [r0, #94]	@ movhi
+3961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5643              		.loc 1 3961 3 is_stmt 1 view .LVU1891
+ 5644 000a 0368     		ldr	r3, [r0]
+ 5645 000c 0F21     		movs	r1, #15
+ 5646 000e 1962     		str	r1, [r3, #32]
+3964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5647              		.loc 1 3964 3 view .LVU1892
+ 5648 0010 0168     		ldr	r1, [r0]
+ 5649 0012 8B69     		ldr	r3, [r1, #24]
+ 5650 0014 43F00803 		orr	r3, r3, #8
+ 5651 0018 8B61     		str	r3, [r1, #24]
+3967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 5652              		.loc 1 3967 3 view .LVU1893
+3967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 5653              		.loc 1 3967 18 is_stmt 0 view .LVU1894
+ 5654 001a 2023     		movs	r3, #32
+ 5655 001c C0F88830 		str	r3, [r0, #136]
+3968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5656              		.loc 1 3968 3 is_stmt 1 view .LVU1895
+3968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5657              		.loc 1 3968 24 is_stmt 0 view .LVU1896
+ 5658 0020 C266     		str	r2, [r0, #108]
+3976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 5659              		.loc 1 3976 3 is_stmt 1 view .LVU1897
+ 5660 0022 FFF7FEFF 		bl	HAL_UART_AbortReceiveCpltCallback
+ 5661              	.LVL499:
+3978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5662              		.loc 1 3978 1 is_stmt 0 view .LVU1898
+ 5663 0026 08BD     		pop	{r3, pc}
+ 5664              		.cfi_endproc
+ 5665              	.LFE389:
+ 5667              		.section	.text.HAL_UARTEx_RxEventCallback,"ax",%progbits
+ 5668              		.align	1
+ 5669              		.weak	HAL_UARTEx_RxEventCallback
+ 5670              		.syntax unified
+ 5671              		.thumb
+ 5672              		.thumb_func
+ 5674              	HAL_UARTEx_RxEventCallback:
+ 5675              	.LVL500:
+ 5676              	.LFB360:
+2681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Prevent unused argument(s) compilation warning */
+ 5677              		.loc 1 2681 1 is_stmt 1 view -0
+ 5678              		.cfi_startproc
+ 5679              		@ args = 0, pretend = 0, frame = 0
+ 5680              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5681              		@ link register save eliminated.
+2683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UNUSED(Size);
+ 5682              		.loc 1 2683 3 view .LVU1900
+ARM GAS  /tmp/cceWHrnJ.s 			page 223
+
+
+2684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5683              		.loc 1 2684 3 view .LVU1901
+2689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5684              		.loc 1 2689 1 is_stmt 0 view .LVU1902
+ 5685 0000 7047     		bx	lr
+ 5686              		.cfi_endproc
+ 5687              	.LFE360:
+ 5689              		.section	.text.HAL_UART_IRQHandler,"ax",%progbits
+ 5690              		.align	1
+ 5691              		.global	HAL_UART_IRQHandler
+ 5692              		.syntax unified
+ 5693              		.thumb
+ 5694              		.thumb_func
+ 5696              	HAL_UART_IRQHandler:
+ 5697              	.LVL501:
+ 5698              	.LFB351:
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+ 5699              		.loc 1 2239 1 is_stmt 1 view -0
+ 5700              		.cfi_startproc
+ 5701              		@ args = 0, pretend = 0, frame = 0
+ 5702              		@ frame_needed = 0, uses_anonymous_args = 0
+2239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+ 5703              		.loc 1 2239 1 is_stmt 0 view .LVU1904
+ 5704 0000 70B5     		push	{r4, r5, r6, lr}
+ 5705              	.LCFI24:
+ 5706              		.cfi_def_cfa_offset 16
+ 5707              		.cfi_offset 4, -16
+ 5708              		.cfi_offset 5, -12
+ 5709              		.cfi_offset 6, -8
+ 5710              		.cfi_offset 14, -4
+ 5711 0002 0446     		mov	r4, r0
+2240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+ 5712              		.loc 1 2240 3 is_stmt 1 view .LVU1905
+2240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+ 5713              		.loc 1 2240 25 is_stmt 0 view .LVU1906
+ 5714 0004 0268     		ldr	r2, [r0]
+2240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+ 5715              		.loc 1 2240 12 view .LVU1907
+ 5716 0006 D369     		ldr	r3, [r2, #28]
+ 5717              	.LVL502:
+2241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+ 5718              		.loc 1 2241 3 is_stmt 1 view .LVU1908
+2241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+ 5719              		.loc 1 2241 12 is_stmt 0 view .LVU1909
+ 5720 0008 1068     		ldr	r0, [r2]
+ 5721              	.LVL503:
+2242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5722              		.loc 1 2242 3 is_stmt 1 view .LVU1910
+2242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5723              		.loc 1 2242 12 is_stmt 0 view .LVU1911
+ 5724 000a 9168     		ldr	r1, [r2, #8]
+ 5725              	.LVL504:
+2244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t errorcode;
+ 5726              		.loc 1 2244 3 is_stmt 1 view .LVU1912
+2245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5727              		.loc 1 2245 3 view .LVU1913
+2248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (errorflags == 0U)
+ARM GAS  /tmp/cceWHrnJ.s 			page 224
+
+
+ 5728              		.loc 1 2248 3 view .LVU1914
+2249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5729              		.loc 1 2249 3 view .LVU1915
+2249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5730              		.loc 1 2249 6 is_stmt 0 view .LVU1916
+ 5731 000c 40F60F0C 		movw	ip, #2063
+ 5732 0010 13EA0C0F 		tst	r3, ip
+ 5733 0014 0DD1     		bne	.L240
+2252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ 5734              		.loc 1 2252 5 is_stmt 1 view .LVU1917
+2252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ 5735              		.loc 1 2252 8 is_stmt 0 view .LVU1918
+ 5736 0016 13F0200F 		tst	r3, #32
+ 5737 001a 10D0     		beq	.L241
+2253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ 5738              		.loc 1 2253 9 view .LVU1919
+ 5739 001c 10F0200F 		tst	r0, #32
+ 5740 0020 02D1     		bne	.L242
+2254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5741              		.loc 1 2254 13 view .LVU1920
+ 5742 0022 11F0805F 		tst	r1, #268435456
+ 5743 0026 0AD0     		beq	.L241
+ 5744              	.L242:
+2256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 5745              		.loc 1 2256 7 is_stmt 1 view .LVU1921
+2256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 5746              		.loc 1 2256 16 is_stmt 0 view .LVU1922
+ 5747 0028 236F     		ldr	r3, [r4, #112]
+ 5748              	.LVL505:
+2256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 5749              		.loc 1 2256 10 view .LVU1923
+ 5750 002a 93B3     		cbz	r3, .L239
+2258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 5751              		.loc 1 2258 9 is_stmt 1 view .LVU1924
+ 5752 002c 2046     		mov	r0, r4
+ 5753              	.LVL506:
+2258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 5754              		.loc 1 2258 9 is_stmt 0 view .LVU1925
+ 5755 002e 9847     		blx	r3
+ 5756              	.LVL507:
+2260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5757              		.loc 1 2260 7 is_stmt 1 view .LVU1926
+ 5758 0030 2FE0     		b	.L239
+ 5759              	.LVL508:
+ 5760              	.L240:
+2266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+ 5761              		.loc 1 2266 21 is_stmt 0 view .LVU1927
+ 5762 0032 B04D     		ldr	r5, .L284
+2266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+ 5763              		.loc 1 2266 7 view .LVU1928
+ 5764 0034 0D40     		ands	r5, r1, r5
+ 5765 0036 2DD1     		bne	.L245
+2267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5766              		.loc 1 2267 12 view .LVU1929
+ 5767 0038 AF4E     		ldr	r6, .L284+4
+ 5768 003a 3042     		tst	r0, r6
+ 5769 003c 2AD1     		bne	.L245
+ARM GAS  /tmp/cceWHrnJ.s 			page 225
+
+
+ 5770              	.L241:
+2404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       && ((isrflags & USART_ISR_IDLE) != 0U)
+ 5771              		.loc 1 2404 3 is_stmt 1 view .LVU1930
+2404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       && ((isrflags & USART_ISR_IDLE) != 0U)
+ 5772              		.loc 1 2404 13 is_stmt 0 view .LVU1931
+ 5773 003e E56E     		ldr	r5, [r4, #108]
+2404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       && ((isrflags & USART_ISR_IDLE) != 0U)
+ 5774              		.loc 1 2404 6 view .LVU1932
+ 5775 0040 012D     		cmp	r5, #1
+ 5776 0042 00F0BD80 		beq	.L279
+ 5777              	.L260:
+2490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5778              		.loc 1 2490 3 is_stmt 1 view .LVU1933
+2490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5779              		.loc 1 2490 6 is_stmt 0 view .LVU1934
+ 5780 0046 13F4801F 		tst	r3, #1048576
+ 5781 004a 03D0     		beq	.L272
+2490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5782              		.loc 1 2490 42 discriminator 1 view .LVU1935
+ 5783 004c 11F4800F 		tst	r1, #4194304
+ 5784 0050 40F05681 		bne	.L280
+ 5785              	.L272:
+2508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+ 5786              		.loc 1 2508 3 is_stmt 1 view .LVU1936
+2508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+ 5787              		.loc 1 2508 6 is_stmt 0 view .LVU1937
+ 5788 0054 13F0800F 		tst	r3, #128
+ 5789 0058 07D0     		beq	.L273
+2509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+ 5790              		.loc 1 2509 7 view .LVU1938
+ 5791 005a 10F0800F 		tst	r0, #128
+ 5792 005e 40F05681 		bne	.L274
+2510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5793              		.loc 1 2510 11 view .LVU1939
+ 5794 0062 11F4000F 		tst	r1, #8388608
+ 5795 0066 40F05281 		bne	.L274
+ 5796              	.L273:
+2520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5797              		.loc 1 2520 3 is_stmt 1 view .LVU1940
+2520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5798              		.loc 1 2520 6 is_stmt 0 view .LVU1941
+ 5799 006a 13F0400F 		tst	r3, #64
+ 5800 006e 03D0     		beq	.L276
+2520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5801              		.loc 1 2520 41 discriminator 1 view .LVU1942
+ 5802 0070 10F0400F 		tst	r0, #64
+ 5803 0074 40F05281 		bne	.L281
+ 5804              	.L276:
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5805              		.loc 1 2527 3 is_stmt 1 view .LVU1943
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5806              		.loc 1 2527 6 is_stmt 0 view .LVU1944
+ 5807 0078 13F4000F 		tst	r3, #8388608
+ 5808 007c 03D0     		beq	.L277
+2527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5809              		.loc 1 2527 43 discriminator 1 view .LVU1945
+ 5810 007e 10F0804F 		tst	r0, #1073741824
+ARM GAS  /tmp/cceWHrnJ.s 			page 226
+
+
+ 5811 0082 40F04F81 		bne	.L282
+ 5812              	.L277:
+2540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5813              		.loc 1 2540 3 is_stmt 1 view .LVU1946
+2540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5814              		.loc 1 2540 6 is_stmt 0 view .LVU1947
+ 5815 0086 13F0807F 		tst	r3, #16777216
+ 5816 008a 02D0     		beq	.L239
+2540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 5817              		.loc 1 2540 43 discriminator 1 view .LVU1948
+ 5818 008c 0028     		cmp	r0, #0
+ 5819 008e C0F24D81 		blt	.L283
+ 5820              	.LVL509:
+ 5821              	.L239:
+2551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5822              		.loc 1 2551 1 view .LVU1949
+ 5823 0092 70BD     		pop	{r4, r5, r6, pc}
+ 5824              	.LVL510:
+ 5825              	.L245:
+2270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5826              		.loc 1 2270 5 is_stmt 1 view .LVU1950
+2270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5827              		.loc 1 2270 8 is_stmt 0 view .LVU1951
+ 5828 0094 13F0010F 		tst	r3, #1
+ 5829 0098 09D0     		beq	.L246
+2270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5830              		.loc 1 2270 43 discriminator 1 view .LVU1952
+ 5831 009a 10F4807F 		tst	r0, #256
+ 5832 009e 06D0     		beq	.L246
+2272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5833              		.loc 1 2272 7 is_stmt 1 view .LVU1953
+ 5834 00a0 0126     		movs	r6, #1
+ 5835 00a2 1662     		str	r6, [r2, #32]
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5836              		.loc 1 2274 7 view .LVU1954
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5837              		.loc 1 2274 12 is_stmt 0 view .LVU1955
+ 5838 00a4 D4F88C20 		ldr	r2, [r4, #140]
+2274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5839              		.loc 1 2274 24 view .LVU1956
+ 5840 00a8 3243     		orrs	r2, r2, r6
+ 5841 00aa C4F88C20 		str	r2, [r4, #140]
+ 5842              	.L246:
+2278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5843              		.loc 1 2278 5 is_stmt 1 view .LVU1957
+2278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5844              		.loc 1 2278 8 is_stmt 0 view .LVU1958
+ 5845 00ae 13F0020F 		tst	r3, #2
+ 5846 00b2 0BD0     		beq	.L247
+2278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5847              		.loc 1 2278 43 discriminator 1 view .LVU1959
+ 5848 00b4 11F0010F 		tst	r1, #1
+ 5849 00b8 08D0     		beq	.L247
+2280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5850              		.loc 1 2280 7 is_stmt 1 view .LVU1960
+ 5851 00ba 2268     		ldr	r2, [r4]
+ 5852 00bc 0226     		movs	r6, #2
+ARM GAS  /tmp/cceWHrnJ.s 			page 227
+
+
+ 5853 00be 1662     		str	r6, [r2, #32]
+2282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5854              		.loc 1 2282 7 view .LVU1961
+2282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5855              		.loc 1 2282 12 is_stmt 0 view .LVU1962
+ 5856 00c0 D4F88C20 		ldr	r2, [r4, #140]
+2282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5857              		.loc 1 2282 24 view .LVU1963
+ 5858 00c4 42F00402 		orr	r2, r2, #4
+ 5859 00c8 C4F88C20 		str	r2, [r4, #140]
+ 5860              	.L247:
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5861              		.loc 1 2286 5 is_stmt 1 view .LVU1964
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5862              		.loc 1 2286 8 is_stmt 0 view .LVU1965
+ 5863 00cc 13F0040F 		tst	r3, #4
+ 5864 00d0 0BD0     		beq	.L248
+2286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5865              		.loc 1 2286 43 discriminator 1 view .LVU1966
+ 5866 00d2 11F0010F 		tst	r1, #1
+ 5867 00d6 08D0     		beq	.L248
+2288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5868              		.loc 1 2288 7 is_stmt 1 view .LVU1967
+ 5869 00d8 2268     		ldr	r2, [r4]
+ 5870 00da 0426     		movs	r6, #4
+ 5871 00dc 1662     		str	r6, [r2, #32]
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5872              		.loc 1 2290 7 view .LVU1968
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5873              		.loc 1 2290 12 is_stmt 0 view .LVU1969
+ 5874 00de D4F88C20 		ldr	r2, [r4, #140]
+2290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5875              		.loc 1 2290 24 view .LVU1970
+ 5876 00e2 42F00202 		orr	r2, r2, #2
+ 5877 00e6 C4F88C20 		str	r2, [r4, #140]
+ 5878              	.L248:
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ 5879              		.loc 1 2294 5 is_stmt 1 view .LVU1971
+2294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ 5880              		.loc 1 2294 8 is_stmt 0 view .LVU1972
+ 5881 00ea 13F0080F 		tst	r3, #8
+ 5882 00ee 0BD0     		beq	.L249
+2295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+ 5883              		.loc 1 2295 9 view .LVU1973
+ 5884 00f0 10F0200F 		tst	r0, #32
+ 5885 00f4 00D1     		bne	.L250
+2295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+ 5886              		.loc 1 2295 57 discriminator 1 view .LVU1974
+ 5887 00f6 3DB1     		cbz	r5, .L249
+ 5888              	.L250:
+2298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5889              		.loc 1 2298 7 is_stmt 1 view .LVU1975
+ 5890 00f8 2268     		ldr	r2, [r4]
+ 5891 00fa 0825     		movs	r5, #8
+ 5892 00fc 1562     		str	r5, [r2, #32]
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5893              		.loc 1 2300 7 view .LVU1976
+ARM GAS  /tmp/cceWHrnJ.s 			page 228
+
+
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5894              		.loc 1 2300 12 is_stmt 0 view .LVU1977
+ 5895 00fe D4F88C20 		ldr	r2, [r4, #140]
+2300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5896              		.loc 1 2300 24 view .LVU1978
+ 5897 0102 2A43     		orrs	r2, r2, r5
+ 5898 0104 C4F88C20 		str	r2, [r4, #140]
+ 5899              	.L249:
+2304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5900              		.loc 1 2304 5 is_stmt 1 view .LVU1979
+2304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5901              		.loc 1 2304 8 is_stmt 0 view .LVU1980
+ 5902 0108 13F4006F 		tst	r3, #2048
+ 5903 010c 0CD0     		beq	.L251
+2304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5904              		.loc 1 2304 45 discriminator 1 view .LVU1981
+ 5905 010e 10F0806F 		tst	r0, #67108864
+ 5906 0112 09D0     		beq	.L251
+2306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5907              		.loc 1 2306 7 is_stmt 1 view .LVU1982
+ 5908 0114 2268     		ldr	r2, [r4]
+ 5909 0116 4FF40065 		mov	r5, #2048
+ 5910 011a 1562     		str	r5, [r2, #32]
+2308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5911              		.loc 1 2308 7 view .LVU1983
+2308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5912              		.loc 1 2308 12 is_stmt 0 view .LVU1984
+ 5913 011c D4F88C20 		ldr	r2, [r4, #140]
+2308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 5914              		.loc 1 2308 24 view .LVU1985
+ 5915 0120 42F02002 		orr	r2, r2, #32
+ 5916 0124 C4F88C20 		str	r2, [r4, #140]
+ 5917              	.L251:
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5918              		.loc 1 2312 5 is_stmt 1 view .LVU1986
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5919              		.loc 1 2312 14 is_stmt 0 view .LVU1987
+ 5920 0128 D4F88C20 		ldr	r2, [r4, #140]
+2312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 5921              		.loc 1 2312 8 view .LVU1988
+ 5922 012c 002A     		cmp	r2, #0
+ 5923 012e B0D0     		beq	.L239
+2315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ 5924              		.loc 1 2315 7 is_stmt 1 view .LVU1989
+2315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ 5925              		.loc 1 2315 10 is_stmt 0 view .LVU1990
+ 5926 0130 13F0200F 		tst	r3, #32
+ 5927 0134 09D0     		beq	.L253
+2316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ 5928              		.loc 1 2316 11 view .LVU1991
+ 5929 0136 10F0200F 		tst	r0, #32
+ 5930 013a 02D1     		bne	.L254
+2317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 5931              		.loc 1 2317 15 view .LVU1992
+ 5932 013c 11F0805F 		tst	r1, #268435456
+ 5933 0140 03D0     		beq	.L253
+ 5934              	.L254:
+ARM GAS  /tmp/cceWHrnJ.s 			page 229
+
+
+2319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 5935              		.loc 1 2319 9 is_stmt 1 view .LVU1993
+2319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 5936              		.loc 1 2319 18 is_stmt 0 view .LVU1994
+ 5937 0142 236F     		ldr	r3, [r4, #112]
+ 5938              	.LVL511:
+2319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 5939              		.loc 1 2319 12 view .LVU1995
+ 5940 0144 0BB1     		cbz	r3, .L253
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 5941              		.loc 1 2321 11 is_stmt 1 view .LVU1996
+ 5942 0146 2046     		mov	r0, r4
+ 5943              	.LVL512:
+2321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 5944              		.loc 1 2321 11 is_stmt 0 view .LVU1997
+ 5945 0148 9847     		blx	r3
+ 5946              	.LVL513:
+ 5947              	.L253:
+2330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ 5948              		.loc 1 2330 7 is_stmt 1 view .LVU1998
+2330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ 5949              		.loc 1 2330 17 is_stmt 0 view .LVU1999
+ 5950 014a D4F88C20 		ldr	r2, [r4, #140]
+ 5951              	.LVL514:
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+ 5952              		.loc 1 2331 7 is_stmt 1 view .LVU2000
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+ 5953              		.loc 1 2331 12 is_stmt 0 view .LVU2001
+ 5954 014e 2368     		ldr	r3, [r4]
+ 5955 0150 9B68     		ldr	r3, [r3, #8]
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+ 5956              		.loc 1 2331 10 view .LVU2002
+ 5957 0152 13F0400F 		tst	r3, #64
+ 5958 0156 02D1     		bne	.L255
+2331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+ 5959              		.loc 1 2331 66 discriminator 1 view .LVU2003
+ 5960 0158 12F0280F 		tst	r2, #40
+ 5961 015c 29D0     		beq	.L256
+ 5962              	.L255:
+2337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5963              		.loc 1 2337 9 is_stmt 1 view .LVU2004
+ 5964 015e 2046     		mov	r0, r4
+ 5965 0160 FFF7FEFF 		bl	UART_EndRxTransfer
+ 5966              	.LVL515:
+2340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 5967              		.loc 1 2340 9 view .LVU2005
+2340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 5968              		.loc 1 2340 13 is_stmt 0 view .LVU2006
+ 5969 0164 2368     		ldr	r3, [r4]
+ 5970 0166 9B68     		ldr	r3, [r3, #8]
+2340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 5971              		.loc 1 2340 12 view .LVU2007
+ 5972 0168 13F0400F 		tst	r3, #64
+ 5973 016c 1DD0     		beq	.L257
+ 5974              	.L258:
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5975              		.loc 1 2343 11 is_stmt 1 discriminator 1 view .LVU2008
+ARM GAS  /tmp/cceWHrnJ.s 			page 230
+
+
+ 5976              	.LBB774:
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5977              		.loc 1 2343 11 discriminator 1 view .LVU2009
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5978              		.loc 1 2343 11 discriminator 1 view .LVU2010
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 5979              		.loc 1 2343 11 discriminator 1 view .LVU2011
+ 5980 016e 2268     		ldr	r2, [r4]
+ 5981              	.LVL516:
+ 5982              	.LBB775:
+ 5983              	.LBI775:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5984              		.loc 2 1151 31 discriminator 1 view .LVU2012
+ 5985              	.LBB776:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 5986              		.loc 2 1153 5 discriminator 1 view .LVU2013
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5987              		.loc 2 1155 4 discriminator 1 view .LVU2014
+ 5988 0170 02F10803 		add	r3, r2, #8
+ 5989              	.LVL517:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 5990              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU2015
+ 5991              		.syntax unified
+ 5992              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5993 0174 53E8003F 		ldrex r3, [r3]
+ 5994              	@ 0 "" 2
+ 5995              	.LVL518:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5996              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU2016
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5997              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2017
+ 5998              		.thumb
+ 5999              		.syntax unified
+ 6000              	.LBE776:
+ 6001              	.LBE775:
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6002              		.loc 1 2343 11 discriminator 1 view .LVU2018
+ 6003 0178 23F04003 		bic	r3, r3, #64
+ 6004              	.LVL519:
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6005              		.loc 1 2343 11 is_stmt 1 discriminator 1 view .LVU2019
+ 6006              	.LBB777:
+ 6007              	.LBI777:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6008              		.loc 2 1202 31 discriminator 1 view .LVU2020
+ 6009              	.LBB778:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6010              		.loc 2 1204 4 discriminator 1 view .LVU2021
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6011              		.loc 2 1206 4 discriminator 1 view .LVU2022
+ 6012 017c 0832     		adds	r2, r2, #8
+ 6013              	.LVL520:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6014              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU2023
+ 6015              		.syntax unified
+ 6016              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6017 017e 42E80031 		strex r1, r3, [r2]
+ARM GAS  /tmp/cceWHrnJ.s 			page 231
+
+
+ 6018              	@ 0 "" 2
+ 6019              	.LVL521:
+ 6020              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU2024
+ 6021              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2025
+ 6022              		.thumb
+ 6023              		.syntax unified
+ 6024              	.LBE778:
+ 6025              	.LBE777:
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6026              		.loc 1 2343 11 discriminator 1 view .LVU2026
+ 6027 0182 0029     		cmp	r1, #0
+ 6028 0184 F3D1     		bne	.L258
+ 6029              	.LBE774:
+2343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6030              		.loc 1 2343 11 is_stmt 1 discriminator 2 view .LVU2027
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+ 6031              		.loc 1 2346 11 discriminator 2 view .LVU2028
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+ 6032              		.loc 1 2346 20 is_stmt 0 discriminator 2 view .LVU2029
+ 6033 0186 E36F     		ldr	r3, [r4, #124]
+ 6034              	.LVL522:
+2346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+ 6035              		.loc 1 2346 14 discriminator 2 view .LVU2030
+ 6036 0188 5BB1     		cbz	r3, .L259
+2350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6037              		.loc 1 2350 13 is_stmt 1 view .LVU2031
+2350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6038              		.loc 1 2350 46 is_stmt 0 view .LVU2032
+ 6039 018a 5C4A     		ldr	r2, .L284+8
+ 6040 018c 9A63     		str	r2, [r3, #56]
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             {
+ 6041              		.loc 1 2353 13 is_stmt 1 view .LVU2033
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             {
+ 6042              		.loc 1 2353 17 is_stmt 0 view .LVU2034
+ 6043 018e E06F     		ldr	r0, [r4, #124]
+ 6044 0190 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 6045              	.LVL523:
+2353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             {
+ 6046              		.loc 1 2353 16 view .LVU2035
+ 6047 0194 0028     		cmp	r0, #0
+ 6048 0196 3FF47CAF 		beq	.L239
+2356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             }
+ 6049              		.loc 1 2356 15 is_stmt 1 view .LVU2036
+2356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             }
+ 6050              		.loc 1 2356 20 is_stmt 0 view .LVU2037
+ 6051 019a E06F     		ldr	r0, [r4, #124]
+2356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             }
+ 6052              		.loc 1 2356 28 view .LVU2038
+ 6053 019c 836B     		ldr	r3, [r0, #56]
+2356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             }
+ 6054              		.loc 1 2356 15 view .LVU2039
+ 6055 019e 9847     		blx	r3
+ 6056              	.LVL524:
+ 6057 01a0 77E7     		b	.L239
+ 6058              	.L259:
+2367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 6059              		.loc 1 2367 13 is_stmt 1 view .LVU2040
+ARM GAS  /tmp/cceWHrnJ.s 			page 232
+
+
+ 6060 01a2 2046     		mov	r0, r4
+ 6061 01a4 FFF7FEFF 		bl	HAL_UART_ErrorCallback
+ 6062              	.LVL525:
+ 6063 01a8 73E7     		b	.L239
+ 6064              	.LVL526:
+ 6065              	.L257:
+2380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 6066              		.loc 1 2380 11 view .LVU2041
+ 6067 01aa 2046     		mov	r0, r4
+ 6068 01ac FFF7FEFF 		bl	HAL_UART_ErrorCallback
+ 6069              	.LVL527:
+ 6070 01b0 6FE7     		b	.L239
+ 6071              	.LVL528:
+ 6072              	.L256:
+2393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 6073              		.loc 1 2393 9 view .LVU2042
+ 6074 01b2 2046     		mov	r0, r4
+ 6075 01b4 FFF7FEFF 		bl	HAL_UART_ErrorCallback
+ 6076              	.LVL529:
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 6077              		.loc 1 2395 9 view .LVU2043
+2395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 6078              		.loc 1 2395 26 is_stmt 0 view .LVU2044
+ 6079 01b8 0023     		movs	r3, #0
+ 6080 01ba C4F88C30 		str	r3, [r4, #140]
+2398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6081              		.loc 1 2398 5 is_stmt 1 view .LVU2045
+ 6082 01be 68E7     		b	.L239
+ 6083              	.LVL530:
+ 6084              	.L279:
+2405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       && ((cr1its & USART_ISR_IDLE) != 0U))
+ 6085              		.loc 1 2405 7 is_stmt 0 view .LVU2046
+ 6086 01c0 13F0100F 		tst	r3, #16
+ 6087 01c4 3FF43FAF 		beq	.L260
+2406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 6088              		.loc 1 2406 7 view .LVU2047
+ 6089 01c8 10F0100F 		tst	r0, #16
+ 6090 01cc 3FF43BAF 		beq	.L260
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6091              		.loc 1 2408 5 is_stmt 1 view .LVU2048
+ 6092 01d0 1023     		movs	r3, #16
+ 6093              	.LVL531:
+2408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6094              		.loc 1 2408 5 is_stmt 0 view .LVU2049
+ 6095 01d2 1362     		str	r3, [r2, #32]
+2411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 6096              		.loc 1 2411 5 is_stmt 1 view .LVU2050
+2411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 6097              		.loc 1 2411 9 is_stmt 0 view .LVU2051
+ 6098 01d4 2368     		ldr	r3, [r4]
+ 6099 01d6 9B68     		ldr	r3, [r3, #8]
+2411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 6100              		.loc 1 2411 8 view .LVU2052
+ 6101 01d8 13F0400F 		tst	r3, #64
+ 6102 01dc 4FD0     		beq	.L261
+ 6103              	.LBB779:
+2417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((nb_remaining_rx_data > 0U)
+ARM GAS  /tmp/cceWHrnJ.s 			page 233
+
+
+ 6104              		.loc 1 2417 7 is_stmt 1 view .LVU2053
+2417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((nb_remaining_rx_data > 0U)
+ 6105              		.loc 1 2417 50 is_stmt 0 view .LVU2054
+ 6106 01de E26F     		ldr	r2, [r4, #124]
+ 6107 01e0 1368     		ldr	r3, [r2]
+ 6108 01e2 5B68     		ldr	r3, [r3, #4]
+2417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((nb_remaining_rx_data > 0U)
+ 6109              		.loc 1 2417 16 view .LVU2055
+ 6110 01e4 9BB2     		uxth	r3, r3
+ 6111              	.LVL532:
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           && (nb_remaining_rx_data < huart->RxXferSize))
+ 6112              		.loc 1 2418 7 is_stmt 1 view .LVU2056
+2418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           && (nb_remaining_rx_data < huart->RxXferSize))
+ 6113              		.loc 1 2418 10 is_stmt 0 view .LVU2057
+ 6114 01e6 002B     		cmp	r3, #0
+ 6115 01e8 3FF453AF 		beq	.L239
+2419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 6116              		.loc 1 2419 43 view .LVU2058
+ 6117 01ec B4F85C10 		ldrh	r1, [r4, #92]
+ 6118              	.LVL533:
+2419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 6119              		.loc 1 2419 11 view .LVU2059
+ 6120 01f0 9942     		cmp	r1, r3
+ 6121 01f2 7FF64EAF 		bls	.L239
+2422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6122              		.loc 1 2422 9 is_stmt 1 view .LVU2060
+2422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6123              		.loc 1 2422 28 is_stmt 0 view .LVU2061
+ 6124 01f6 A4F85E30 		strh	r3, [r4, #94]	@ movhi
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 6125              		.loc 1 2425 9 is_stmt 1 view .LVU2062
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 6126              		.loc 1 2425 13 is_stmt 0 view .LVU2063
+ 6127 01fa 1368     		ldr	r3, [r2]
+ 6128              	.LVL534:
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 6129              		.loc 1 2425 13 view .LVU2064
+ 6130 01fc 1B68     		ldr	r3, [r3]
+2425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 6131              		.loc 1 2425 12 view .LVU2065
+ 6132 01fe 13F0200F 		tst	r3, #32
+ 6133 0202 31D1     		bne	.L263
+ 6134              	.L264:
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 6135              		.loc 1 2428 11 is_stmt 1 discriminator 1 view .LVU2066
+ 6136              	.LBB780:
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 6137              		.loc 1 2428 11 discriminator 1 view .LVU2067
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 6138              		.loc 1 2428 11 discriminator 1 view .LVU2068
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 6139              		.loc 1 2428 11 discriminator 1 view .LVU2069
+ 6140 0204 2268     		ldr	r2, [r4]
+ 6141              	.LVL535:
+ 6142              	.LBB781:
+ 6143              	.LBI781:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/cceWHrnJ.s 			page 234
+
+
+ 6144              		.loc 2 1151 31 discriminator 1 view .LVU2070
+ 6145              	.LBB782:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6146              		.loc 2 1153 5 discriminator 1 view .LVU2071
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6147              		.loc 2 1155 4 discriminator 1 view .LVU2072
+ 6148              		.syntax unified
+ 6149              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6150 0206 52E8003F 		ldrex r3, [r2]
+ 6151              	@ 0 "" 2
+ 6152              	.LVL536:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6153              		.loc 2 1156 4 discriminator 1 view .LVU2073
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6154              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2074
+ 6155              		.thumb
+ 6156              		.syntax unified
+ 6157              	.LBE782:
+ 6158              	.LBE781:
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 6159              		.loc 1 2428 11 discriminator 1 view .LVU2075
+ 6160 020a 23F48073 		bic	r3, r3, #256
+ 6161              	.LVL537:
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 6162              		.loc 1 2428 11 is_stmt 1 discriminator 1 view .LVU2076
+ 6163              	.LBB783:
+ 6164              	.LBI783:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6165              		.loc 2 1202 31 discriminator 1 view .LVU2077
+ 6166              	.LBB784:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6167              		.loc 2 1204 4 discriminator 1 view .LVU2078
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6168              		.loc 2 1206 4 discriminator 1 view .LVU2079
+ 6169              		.syntax unified
+ 6170              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6171 020e 42E80031 		strex r1, r3, [r2]
+ 6172              	@ 0 "" 2
+ 6173              	.LVL538:
+ 6174              		.loc 2 1207 4 discriminator 1 view .LVU2080
+ 6175              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2081
+ 6176              		.thumb
+ 6177              		.syntax unified
+ 6178              	.LBE784:
+ 6179              	.LBE783:
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 6180              		.loc 1 2428 11 discriminator 1 view .LVU2082
+ 6181 0212 0029     		cmp	r1, #0
+ 6182 0214 F6D1     		bne	.L264
+ 6183              	.LVL539:
+ 6184              	.L265:
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 6185              		.loc 1 2428 11 discriminator 1 view .LVU2083
+ 6186              	.LBE780:
+2428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 6187              		.loc 1 2428 11 is_stmt 1 discriminator 1 view .LVU2084
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 235
+
+
+ 6188              		.loc 1 2429 11 discriminator 1 view .LVU2085
+ 6189              	.LBB785:
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6190              		.loc 1 2429 11 discriminator 1 view .LVU2086
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6191              		.loc 1 2429 11 discriminator 1 view .LVU2087
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6192              		.loc 1 2429 11 discriminator 1 view .LVU2088
+ 6193 0216 2268     		ldr	r2, [r4]
+ 6194              	.LVL540:
+ 6195              	.LBB786:
+ 6196              	.LBI786:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6197              		.loc 2 1151 31 discriminator 1 view .LVU2089
+ 6198              	.LBB787:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6199              		.loc 2 1153 5 discriminator 1 view .LVU2090
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6200              		.loc 2 1155 4 discriminator 1 view .LVU2091
+ 6201 0218 02F10803 		add	r3, r2, #8
+ 6202              	.LVL541:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6203              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU2092
+ 6204              		.syntax unified
+ 6205              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6206 021c 53E8003F 		ldrex r3, [r3]
+ 6207              	@ 0 "" 2
+ 6208              	.LVL542:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6209              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU2093
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6210              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2094
+ 6211              		.thumb
+ 6212              		.syntax unified
+ 6213              	.LBE787:
+ 6214              	.LBE786:
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6215              		.loc 1 2429 11 discriminator 1 view .LVU2095
+ 6216 0220 23F00103 		bic	r3, r3, #1
+ 6217              	.LVL543:
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6218              		.loc 1 2429 11 is_stmt 1 discriminator 1 view .LVU2096
+ 6219              	.LBB788:
+ 6220              	.LBI788:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6221              		.loc 2 1202 31 discriminator 1 view .LVU2097
+ 6222              	.LBB789:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6223              		.loc 2 1204 4 discriminator 1 view .LVU2098
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6224              		.loc 2 1206 4 discriminator 1 view .LVU2099
+ 6225 0224 0832     		adds	r2, r2, #8
+ 6226              	.LVL544:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6227              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU2100
+ 6228              		.syntax unified
+ 6229              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ARM GAS  /tmp/cceWHrnJ.s 			page 236
+
+
+ 6230 0226 42E80031 		strex r1, r3, [r2]
+ 6231              	@ 0 "" 2
+ 6232              	.LVL545:
+ 6233              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU2101
+ 6234              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2102
+ 6235              		.thumb
+ 6236              		.syntax unified
+ 6237              	.LBE789:
+ 6238              	.LBE788:
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6239              		.loc 1 2429 11 discriminator 1 view .LVU2103
+ 6240 022a 0029     		cmp	r1, #0
+ 6241 022c F3D1     		bne	.L265
+ 6242              	.LVL546:
+ 6243              	.L266:
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6244              		.loc 1 2429 11 discriminator 1 view .LVU2104
+ 6245              	.LBE785:
+2429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6246              		.loc 1 2429 11 is_stmt 1 discriminator 1 view .LVU2105
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6247              		.loc 1 2433 11 discriminator 1 view .LVU2106
+ 6248              	.LBB790:
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6249              		.loc 1 2433 11 discriminator 1 view .LVU2107
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6250              		.loc 1 2433 11 discriminator 1 view .LVU2108
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6251              		.loc 1 2433 11 discriminator 1 view .LVU2109
+ 6252 022e 2268     		ldr	r2, [r4]
+ 6253              	.LVL547:
+ 6254              	.LBB791:
+ 6255              	.LBI791:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6256              		.loc 2 1151 31 discriminator 1 view .LVU2110
+ 6257              	.LBB792:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6258              		.loc 2 1153 5 discriminator 1 view .LVU2111
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6259              		.loc 2 1155 4 discriminator 1 view .LVU2112
+ 6260 0230 02F10803 		add	r3, r2, #8
+ 6261              	.LVL548:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6262              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU2113
+ 6263              		.syntax unified
+ 6264              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6265 0234 53E8003F 		ldrex r3, [r3]
+ 6266              	@ 0 "" 2
+ 6267              	.LVL549:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6268              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU2114
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6269              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2115
+ 6270              		.thumb
+ 6271              		.syntax unified
+ 6272              	.LBE792:
+ 6273              	.LBE791:
+ARM GAS  /tmp/cceWHrnJ.s 			page 237
+
+
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6274              		.loc 1 2433 11 discriminator 1 view .LVU2116
+ 6275 0238 23F04003 		bic	r3, r3, #64
+ 6276              	.LVL550:
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6277              		.loc 1 2433 11 is_stmt 1 discriminator 1 view .LVU2117
+ 6278              	.LBB793:
+ 6279              	.LBI793:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6280              		.loc 2 1202 31 discriminator 1 view .LVU2118
+ 6281              	.LBB794:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6282              		.loc 2 1204 4 discriminator 1 view .LVU2119
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6283              		.loc 2 1206 4 discriminator 1 view .LVU2120
+ 6284 023c 0832     		adds	r2, r2, #8
+ 6285              	.LVL551:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6286              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU2121
+ 6287              		.syntax unified
+ 6288              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6289 023e 42E80031 		strex r1, r3, [r2]
+ 6290              	@ 0 "" 2
+ 6291              	.LVL552:
+ 6292              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU2122
+ 6293              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2123
+ 6294              		.thumb
+ 6295              		.syntax unified
+ 6296              	.LBE794:
+ 6297              	.LBE793:
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6298              		.loc 1 2433 11 discriminator 1 view .LVU2124
+ 6299 0242 0029     		cmp	r1, #0
+ 6300 0244 F3D1     		bne	.L266
+ 6301              	.LBE790:
+2433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6302              		.loc 1 2433 11 is_stmt 1 discriminator 2 view .LVU2125
+2436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 6303              		.loc 1 2436 11 discriminator 2 view .LVU2126
+2436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 6304              		.loc 1 2436 26 is_stmt 0 discriminator 2 view .LVU2127
+ 6305 0246 2023     		movs	r3, #32
+ 6306              	.LVL553:
+2436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 6307              		.loc 1 2436 26 discriminator 2 view .LVU2128
+ 6308 0248 C4F88830 		str	r3, [r4, #136]
+ 6309              	.LVL554:
+2437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6310              		.loc 1 2437 11 is_stmt 1 discriminator 2 view .LVU2129
+2437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6311              		.loc 1 2437 32 is_stmt 0 discriminator 2 view .LVU2130
+ 6312 024c 0023     		movs	r3, #0
+ 6313 024e E366     		str	r3, [r4, #108]
+ 6314              	.L267:
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6315              		.loc 1 2439 11 is_stmt 1 discriminator 1 view .LVU2131
+ 6316              	.LBB795:
+ARM GAS  /tmp/cceWHrnJ.s 			page 238
+
+
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6317              		.loc 1 2439 11 discriminator 1 view .LVU2132
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6318              		.loc 1 2439 11 discriminator 1 view .LVU2133
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6319              		.loc 1 2439 11 discriminator 1 view .LVU2134
+ 6320 0250 2268     		ldr	r2, [r4]
+ 6321              	.LVL555:
+ 6322              	.LBB796:
+ 6323              	.LBI796:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6324              		.loc 2 1151 31 discriminator 1 view .LVU2135
+ 6325              	.LBB797:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6326              		.loc 2 1153 5 discriminator 1 view .LVU2136
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6327              		.loc 2 1155 4 discriminator 1 view .LVU2137
+ 6328              		.syntax unified
+ 6329              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6330 0252 52E8003F 		ldrex r3, [r2]
+ 6331              	@ 0 "" 2
+ 6332              	.LVL556:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6333              		.loc 2 1156 4 discriminator 1 view .LVU2138
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6334              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2139
+ 6335              		.thumb
+ 6336              		.syntax unified
+ 6337              	.LBE797:
+ 6338              	.LBE796:
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6339              		.loc 1 2439 11 discriminator 1 view .LVU2140
+ 6340 0256 23F01003 		bic	r3, r3, #16
+ 6341              	.LVL557:
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6342              		.loc 1 2439 11 is_stmt 1 discriminator 1 view .LVU2141
+ 6343              	.LBB798:
+ 6344              	.LBI798:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6345              		.loc 2 1202 31 discriminator 1 view .LVU2142
+ 6346              	.LBB799:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6347              		.loc 2 1204 4 discriminator 1 view .LVU2143
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6348              		.loc 2 1206 4 discriminator 1 view .LVU2144
+ 6349              		.syntax unified
+ 6350              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6351 025a 42E80031 		strex r1, r3, [r2]
+ 6352              	@ 0 "" 2
+ 6353              	.LVL558:
+ 6354              		.loc 2 1207 4 discriminator 1 view .LVU2145
+ 6355              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2146
+ 6356              		.thumb
+ 6357              		.syntax unified
+ 6358              	.LBE799:
+ 6359              	.LBE798:
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 239
+
+
+ 6360              		.loc 1 2439 11 discriminator 1 view .LVU2147
+ 6361 025e 0029     		cmp	r1, #0
+ 6362 0260 F6D1     		bne	.L267
+ 6363              	.LBE795:
+2439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6364              		.loc 1 2439 11 is_stmt 1 discriminator 2 view .LVU2148
+2442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 6365              		.loc 1 2442 11 discriminator 2 view .LVU2149
+2442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 6366              		.loc 1 2442 17 is_stmt 0 discriminator 2 view .LVU2150
+ 6367 0262 E06F     		ldr	r0, [r4, #124]
+ 6368              	.LVL559:
+2442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 6369              		.loc 1 2442 17 discriminator 2 view .LVU2151
+ 6370 0264 FFF7FEFF 		bl	HAL_DMA_Abort
+ 6371              	.LVL560:
+ 6372              	.L263:
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 6373              		.loc 1 2449 9 is_stmt 1 view .LVU2152
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 6374              		.loc 1 2449 49 is_stmt 0 view .LVU2153
+ 6375 0268 B4F85C10 		ldrh	r1, [r4, #92]
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 6376              		.loc 1 2449 69 view .LVU2154
+ 6377 026c B4F85E30 		ldrh	r3, [r4, #94]
+ 6378 0270 9BB2     		uxth	r3, r3
+2449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 6379              		.loc 1 2449 9 view .LVU2155
+ 6380 0272 C91A     		subs	r1, r1, r3
+ 6381 0274 89B2     		uxth	r1, r1
+ 6382 0276 2046     		mov	r0, r4
+ 6383 0278 FFF7FEFF 		bl	HAL_UARTEx_RxEventCallback
+ 6384              	.LVL561:
+2452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 6385              		.loc 1 2452 7 is_stmt 1 view .LVU2156
+ 6386 027c 09E7     		b	.L239
+ 6387              	.LVL562:
+ 6388              	.L261:
+2452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 6389              		.loc 1 2452 7 is_stmt 0 view .LVU2157
+ 6390              	.LBE779:
+ 6391              	.LBB800:
+2459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((huart->RxXferCount > 0U)
+ 6392              		.loc 1 2459 7 is_stmt 1 view .LVU2158
+2459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((huart->RxXferCount > 0U)
+ 6393              		.loc 1 2459 34 is_stmt 0 view .LVU2159
+ 6394 027e B4F85C10 		ldrh	r1, [r4, #92]
+ 6395              	.LVL563:
+2459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((huart->RxXferCount > 0U)
+ 6396              		.loc 1 2459 54 view .LVU2160
+ 6397 0282 B4F85E30 		ldrh	r3, [r4, #94]
+ 6398 0286 9BB2     		uxth	r3, r3
+2459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((huart->RxXferCount > 0U)
+ 6399              		.loc 1 2459 16 view .LVU2161
+ 6400 0288 C91A     		subs	r1, r1, r3
+ 6401 028a 89B2     		uxth	r1, r1
+ 6402              	.LVL564:
+ARM GAS  /tmp/cceWHrnJ.s 			page 240
+
+
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           && (nb_rx_data > 0U))
+ 6403              		.loc 1 2460 7 is_stmt 1 view .LVU2162
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           && (nb_rx_data > 0U))
+ 6404              		.loc 1 2460 17 is_stmt 0 view .LVU2163
+ 6405 028c B4F85E30 		ldrh	r3, [r4, #94]
+ 6406 0290 9BB2     		uxth	r3, r3
+2460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           && (nb_rx_data > 0U))
+ 6407              		.loc 1 2460 10 view .LVU2164
+ 6408 0292 002B     		cmp	r3, #0
+ 6409 0294 3FF4FDAE 		beq	.L239
+2461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 6410              		.loc 1 2461 11 view .LVU2165
+ 6411 0298 0029     		cmp	r1, #0
+ 6412 029a 3FF4FAAE 		beq	.L239
+ 6413              	.LVL565:
+ 6414              	.L269:
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6415              		.loc 1 2464 9 is_stmt 1 discriminator 1 view .LVU2166
+ 6416              	.LBB801:
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6417              		.loc 1 2464 9 discriminator 1 view .LVU2167
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6418              		.loc 1 2464 9 discriminator 1 view .LVU2168
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6419              		.loc 1 2464 9 discriminator 1 view .LVU2169
+ 6420 029e 2268     		ldr	r2, [r4]
+ 6421              	.LVL566:
+ 6422              	.LBB802:
+ 6423              	.LBI802:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6424              		.loc 2 1151 31 discriminator 1 view .LVU2170
+ 6425              	.LBB803:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6426              		.loc 2 1153 5 discriminator 1 view .LVU2171
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6427              		.loc 2 1155 4 discriminator 1 view .LVU2172
+ 6428              		.syntax unified
+ 6429              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6430 02a0 52E8003F 		ldrex r3, [r2]
+ 6431              	@ 0 "" 2
+ 6432              	.LVL567:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6433              		.loc 2 1156 4 discriminator 1 view .LVU2173
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6434              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2174
+ 6435              		.thumb
+ 6436              		.syntax unified
+ 6437              	.LBE803:
+ 6438              	.LBE802:
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6439              		.loc 1 2464 9 discriminator 1 view .LVU2175
+ 6440 02a4 23F49073 		bic	r3, r3, #288
+ 6441              	.LVL568:
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6442              		.loc 1 2464 9 is_stmt 1 discriminator 1 view .LVU2176
+ 6443              	.LBB804:
+ 6444              	.LBI804:
+ARM GAS  /tmp/cceWHrnJ.s 			page 241
+
+
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6445              		.loc 2 1202 31 discriminator 1 view .LVU2177
+ 6446              	.LBB805:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6447              		.loc 2 1204 4 discriminator 1 view .LVU2178
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6448              		.loc 2 1206 4 discriminator 1 view .LVU2179
+ 6449              		.syntax unified
+ 6450              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6451 02a8 42E80030 		strex r0, r3, [r2]
+ 6452              	@ 0 "" 2
+ 6453              	.LVL569:
+ 6454              		.loc 2 1207 4 discriminator 1 view .LVU2180
+ 6455              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2181
+ 6456              		.thumb
+ 6457              		.syntax unified
+ 6458              	.LBE805:
+ 6459              	.LBE804:
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6460              		.loc 1 2464 9 discriminator 1 view .LVU2182
+ 6461 02ac 0028     		cmp	r0, #0
+ 6462 02ae F6D1     		bne	.L269
+ 6463              	.LVL570:
+ 6464              	.L270:
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6465              		.loc 1 2464 9 discriminator 1 view .LVU2183
+ 6466              	.LBE801:
+2464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6467              		.loc 1 2464 9 is_stmt 1 discriminator 1 view .LVU2184
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6468              		.loc 1 2467 9 discriminator 1 view .LVU2185
+ 6469              	.LBB806:
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6470              		.loc 1 2467 9 discriminator 1 view .LVU2186
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6471              		.loc 1 2467 9 discriminator 1 view .LVU2187
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6472              		.loc 1 2467 9 discriminator 1 view .LVU2188
+ 6473 02b0 2268     		ldr	r2, [r4]
+ 6474              	.LVL571:
+ 6475              	.LBB807:
+ 6476              	.LBI807:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6477              		.loc 2 1151 31 discriminator 1 view .LVU2189
+ 6478              	.LBB808:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6479              		.loc 2 1153 5 discriminator 1 view .LVU2190
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6480              		.loc 2 1155 4 discriminator 1 view .LVU2191
+ 6481 02b2 02F10803 		add	r3, r2, #8
+ 6482              	.LVL572:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6483              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU2192
+ 6484              		.syntax unified
+ 6485              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6486 02b6 53E8003F 		ldrex r3, [r3]
+ 6487              	@ 0 "" 2
+ARM GAS  /tmp/cceWHrnJ.s 			page 242
+
+
+ 6488              	.LVL573:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6489              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU2193
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6490              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2194
+ 6491              		.thumb
+ 6492              		.syntax unified
+ 6493              	.LBE808:
+ 6494              	.LBE807:
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6495              		.loc 1 2467 9 discriminator 1 view .LVU2195
+ 6496 02ba 23F08053 		bic	r3, r3, #268435456
+ 6497 02be 23F00103 		bic	r3, r3, #1
+ 6498              	.LVL574:
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6499              		.loc 1 2467 9 is_stmt 1 discriminator 1 view .LVU2196
+ 6500              	.LBB809:
+ 6501              	.LBI809:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6502              		.loc 2 1202 31 discriminator 1 view .LVU2197
+ 6503              	.LBB810:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6504              		.loc 2 1204 4 discriminator 1 view .LVU2198
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6505              		.loc 2 1206 4 discriminator 1 view .LVU2199
+ 6506 02c2 0832     		adds	r2, r2, #8
+ 6507              	.LVL575:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6508              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU2200
+ 6509              		.syntax unified
+ 6510              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6511 02c4 42E80030 		strex r0, r3, [r2]
+ 6512              	@ 0 "" 2
+ 6513              	.LVL576:
+ 6514              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU2201
+ 6515              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2202
+ 6516              		.thumb
+ 6517              		.syntax unified
+ 6518              	.LBE810:
+ 6519              	.LBE809:
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6520              		.loc 1 2467 9 discriminator 1 view .LVU2203
+ 6521 02c8 0028     		cmp	r0, #0
+ 6522 02ca F1D1     		bne	.L270
+ 6523              	.LBE806:
+2467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6524              		.loc 1 2467 9 is_stmt 1 discriminator 2 view .LVU2204
+2470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 6525              		.loc 1 2470 9 discriminator 2 view .LVU2205
+2470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 6526              		.loc 1 2470 24 is_stmt 0 discriminator 2 view .LVU2206
+ 6527 02cc 2023     		movs	r3, #32
+ 6528              	.LVL577:
+2470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 6529              		.loc 1 2470 24 discriminator 2 view .LVU2207
+ 6530 02ce C4F88830 		str	r3, [r4, #136]
+2471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 243
+
+
+ 6531              		.loc 1 2471 9 is_stmt 1 discriminator 2 view .LVU2208
+2471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6532              		.loc 1 2471 30 is_stmt 0 discriminator 2 view .LVU2209
+ 6533 02d2 0023     		movs	r3, #0
+ 6534 02d4 E366     		str	r3, [r4, #108]
+2474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6535              		.loc 1 2474 9 is_stmt 1 discriminator 2 view .LVU2210
+2474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6536              		.loc 1 2474 22 is_stmt 0 discriminator 2 view .LVU2211
+ 6537 02d6 2367     		str	r3, [r4, #112]
+ 6538              	.L271:
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 6539              		.loc 1 2476 9 is_stmt 1 discriminator 1 view .LVU2212
+ 6540              	.LBB811:
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 6541              		.loc 1 2476 9 discriminator 1 view .LVU2213
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 6542              		.loc 1 2476 9 discriminator 1 view .LVU2214
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 6543              		.loc 1 2476 9 discriminator 1 view .LVU2215
+ 6544 02d8 2268     		ldr	r2, [r4]
+ 6545              	.LVL578:
+ 6546              	.LBB812:
+ 6547              	.LBI812:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6548              		.loc 2 1151 31 discriminator 1 view .LVU2216
+ 6549              	.LBB813:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6550              		.loc 2 1153 5 discriminator 1 view .LVU2217
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6551              		.loc 2 1155 4 discriminator 1 view .LVU2218
+ 6552              		.syntax unified
+ 6553              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6554 02da 52E8003F 		ldrex r3, [r2]
+ 6555              	@ 0 "" 2
+ 6556              	.LVL579:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6557              		.loc 2 1156 4 discriminator 1 view .LVU2219
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6558              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2220
+ 6559              		.thumb
+ 6560              		.syntax unified
+ 6561              	.LBE813:
+ 6562              	.LBE812:
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 6563              		.loc 1 2476 9 discriminator 1 view .LVU2221
+ 6564 02de 23F01003 		bic	r3, r3, #16
+ 6565              	.LVL580:
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 6566              		.loc 1 2476 9 is_stmt 1 discriminator 1 view .LVU2222
+ 6567              	.LBB814:
+ 6568              	.LBI814:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6569              		.loc 2 1202 31 discriminator 1 view .LVU2223
+ 6570              	.LBB815:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6571              		.loc 2 1204 4 discriminator 1 view .LVU2224
+ARM GAS  /tmp/cceWHrnJ.s 			page 244
+
+
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6572              		.loc 2 1206 4 discriminator 1 view .LVU2225
+ 6573              		.syntax unified
+ 6574              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6575 02e2 42E80030 		strex r0, r3, [r2]
+ 6576              	@ 0 "" 2
+ 6577              	.LVL581:
+ 6578              		.loc 2 1207 4 discriminator 1 view .LVU2226
+ 6579              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2227
+ 6580              		.thumb
+ 6581              		.syntax unified
+ 6582              	.LBE815:
+ 6583              	.LBE814:
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 6584              		.loc 1 2476 9 discriminator 1 view .LVU2228
+ 6585 02e6 0028     		cmp	r0, #0
+ 6586 02e8 F6D1     		bne	.L271
+ 6587              	.LBE811:
+2476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 6588              		.loc 1 2476 9 is_stmt 1 discriminator 2 view .LVU2229
+2482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 6589              		.loc 1 2482 9 discriminator 2 view .LVU2230
+ 6590 02ea 2046     		mov	r0, r4
+ 6591 02ec FFF7FEFF 		bl	HAL_UARTEx_RxEventCallback
+ 6592              	.LVL582:
+2485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 6593              		.loc 1 2485 7 discriminator 2 view .LVU2231
+ 6594 02f0 CFE6     		b	.L239
+ 6595              	.L285:
+ 6596 02f2 00BF     		.align	2
+ 6597              	.L284:
+ 6598 02f4 01000010 		.word	268435457
+ 6599 02f8 20010004 		.word	67109152
+ 6600 02fc 00000000 		.word	UART_DMAAbortOnError
+ 6601              	.LVL583:
+ 6602              	.L280:
+2485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 6603              		.loc 1 2485 7 is_stmt 0 discriminator 2 view .LVU2232
+ 6604              	.LBE800:
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6605              		.loc 1 2492 5 is_stmt 1 view .LVU2233
+ 6606 0300 4FF48013 		mov	r3, #1048576
+ 6607              	.LVL584:
+2492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6608              		.loc 1 2492 5 is_stmt 0 view .LVU2234
+ 6609 0304 1362     		str	r3, [r2, #32]
+2502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 6610              		.loc 1 2502 5 is_stmt 1 view .LVU2235
+ 6611 0306 2046     		mov	r0, r4
+ 6612              	.LVL585:
+2502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 6613              		.loc 1 2502 5 is_stmt 0 view .LVU2236
+ 6614 0308 FFF7FEFF 		bl	HAL_UARTEx_WakeupCallback
+ 6615              	.LVL586:
+2504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 6616              		.loc 1 2504 5 is_stmt 1 view .LVU2237
+ 6617 030c C1E6     		b	.L239
+ARM GAS  /tmp/cceWHrnJ.s 			page 245
+
+
+ 6618              	.LVL587:
+ 6619              	.L274:
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 6620              		.loc 1 2512 5 view .LVU2238
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 6621              		.loc 1 2512 14 is_stmt 0 view .LVU2239
+ 6622 030e 636F     		ldr	r3, [r4, #116]
+ 6623              	.LVL588:
+2512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 6624              		.loc 1 2512 8 view .LVU2240
+ 6625 0310 002B     		cmp	r3, #0
+ 6626 0312 3FF4BEAE 		beq	.L239
+2514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 6627              		.loc 1 2514 7 is_stmt 1 view .LVU2241
+ 6628 0316 2046     		mov	r0, r4
+ 6629              	.LVL589:
+2514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 6630              		.loc 1 2514 7 is_stmt 0 view .LVU2242
+ 6631 0318 9847     		blx	r3
+ 6632              	.LVL590:
+2516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 6633              		.loc 1 2516 5 is_stmt 1 view .LVU2243
+ 6634 031a BAE6     		b	.L239
+ 6635              	.LVL591:
+ 6636              	.L281:
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return;
+ 6637              		.loc 1 2522 5 view .LVU2244
+ 6638 031c 2046     		mov	r0, r4
+ 6639              	.LVL592:
+2522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     return;
+ 6640              		.loc 1 2522 5 is_stmt 0 view .LVU2245
+ 6641 031e FFF7FEFF 		bl	UART_EndTransmit_IT
+ 6642              	.LVL593:
+2523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 6643              		.loc 1 2523 5 is_stmt 1 view .LVU2246
+ 6644 0322 B6E6     		b	.L239
+ 6645              	.LVL594:
+ 6646              	.L282:
+2534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 6647              		.loc 1 2534 5 view .LVU2247
+ 6648 0324 2046     		mov	r0, r4
+ 6649              	.LVL595:
+2534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 6650              		.loc 1 2534 5 is_stmt 0 view .LVU2248
+ 6651 0326 FFF7FEFF 		bl	HAL_UARTEx_TxFifoEmptyCallback
+ 6652              	.LVL596:
+2536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 6653              		.loc 1 2536 5 is_stmt 1 view .LVU2249
+ 6654 032a B2E6     		b	.L239
+ 6655              	.LVL597:
+ 6656              	.L283:
+2547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 6657              		.loc 1 2547 5 view .LVU2250
+ 6658 032c 2046     		mov	r0, r4
+ 6659              	.LVL598:
+2547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 6660              		.loc 1 2547 5 is_stmt 0 view .LVU2251
+ARM GAS  /tmp/cceWHrnJ.s 			page 246
+
+
+ 6661 032e FFF7FEFF 		bl	HAL_UARTEx_RxFifoFullCallback
+ 6662              	.LVL599:
+2549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 6663              		.loc 1 2549 5 is_stmt 1 view .LVU2252
+ 6664 0332 AEE6     		b	.L239
+ 6665              		.cfi_endproc
+ 6666              	.LFE351:
+ 6668              		.section	.text.UART_RxISR_8BIT,"ax",%progbits
+ 6669              		.align	1
+ 6670              		.syntax unified
+ 6671              		.thumb
+ 6672              		.thumb_func
+ 6674              	UART_RxISR_8BIT:
+ 6675              	.LVL600:
+ 6676              	.LFB395:
+4148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+4150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief RX interrupt handler for 7 or 8 bits data word length .
+4151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+4152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+4153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+4154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+4155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 6677              		.loc 1 4155 1 view -0
+ 6678              		.cfi_startproc
+ 6679              		@ args = 0, pretend = 0, frame = 0
+ 6680              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6681              		.loc 1 4155 1 is_stmt 0 view .LVU2254
+ 6682 0000 08B5     		push	{r3, lr}
+ 6683              	.LCFI25:
+ 6684              		.cfi_def_cfa_offset 8
+ 6685              		.cfi_offset 3, -8
+ 6686              		.cfi_offset 14, -4
+4156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t uhMask = huart->Mask;
+ 6687              		.loc 1 4156 3 is_stmt 1 view .LVU2255
+ 6688              		.loc 1 4156 12 is_stmt 0 view .LVU2256
+ 6689 0002 B0F86030 		ldrh	r3, [r0, #96]
+ 6690              	.LVL601:
+4157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t  uhdata;
+ 6691              		.loc 1 4157 3 is_stmt 1 view .LVU2257
+4158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Rx process is ongoing */
+4160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ 6692              		.loc 1 4160 3 view .LVU2258
+ 6693              		.loc 1 4160 12 is_stmt 0 view .LVU2259
+ 6694 0006 D0F88820 		ldr	r2, [r0, #136]
+ 6695              		.loc 1 4160 6 view .LVU2260
+ 6696 000a 222A     		cmp	r2, #34
+ 6697 000c 05D0     		beq	.L295
+4161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+4162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+4163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+4164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pRxBuffPtr++;
+4165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount--;
+4166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->RxXferCount == 0U)
+4168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ARM GAS  /tmp/cceWHrnJ.s 			page 247
+
+
+4169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+4171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+4174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Rx process is completed, restore huart->RxState to Ready */
+4176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxState = HAL_UART_STATE_READY;
+4177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Clear RxISR function pointer */
+4179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxISR = NULL;
+4180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Check current reception Mode :
+4182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          If Reception till IDLE event has been selected : */
+4183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+4184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Set reception type to Standard */
+4186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+4187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Disable IDLE interrupt */
+4189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+4190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+4192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Clear IDLE Flag */
+4194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+4195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+4197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call registered Rx Event callback*/
+4198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxEventCallback(huart, huart->RxXferSize);
+4199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+4200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call legacy weak Rx Event callback*/
+4201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+4202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+4203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+4205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Standard reception API called */
+4207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+4208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call registered Rx complete callback*/
+4209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxCpltCallback(huart);
+4210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+4211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call legacy weak Rx complete callback*/
+4212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         HAL_UART_RxCpltCallback(huart);
+4213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+4214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+4216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+4217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+4218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+4219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Clear RXNE interrupt flag */
+4220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ 6698              		.loc 1 4220 5 is_stmt 1 view .LVU2261
+ 6699 000e 0268     		ldr	r2, [r0]
+ 6700 0010 9369     		ldr	r3, [r2, #24]
+ 6701              	.LVL602:
+ 6702              		.loc 1 4220 5 is_stmt 0 view .LVU2262
+ARM GAS  /tmp/cceWHrnJ.s 			page 248
+
+
+ 6703 0012 43F00803 		orr	r3, r3, #8
+ 6704 0016 9361     		str	r3, [r2, #24]
+ 6705              	.LVL603:
+ 6706              	.L286:
+4221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+4222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 6707              		.loc 1 4222 1 view .LVU2263
+ 6708 0018 08BD     		pop	{r3, pc}
+ 6709              	.LVL604:
+ 6710              	.L295:
+4162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ 6711              		.loc 1 4162 5 is_stmt 1 view .LVU2264
+4162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ 6712              		.loc 1 4162 25 is_stmt 0 view .LVU2265
+ 6713 001a 0268     		ldr	r2, [r0]
+ 6714 001c 516A     		ldr	r1, [r2, #36]
+ 6715              	.LVL605:
+4163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pRxBuffPtr++;
+ 6716              		.loc 1 4163 5 is_stmt 1 view .LVU2266
+4163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pRxBuffPtr++;
+ 6717              		.loc 1 4163 45 is_stmt 0 view .LVU2267
+ 6718 001e DBB2     		uxtb	r3, r3
+ 6719              	.LVL606:
+4163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pRxBuffPtr++;
+ 6720              		.loc 1 4163 11 view .LVU2268
+ 6721 0020 826D     		ldr	r2, [r0, #88]
+4163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pRxBuffPtr++;
+ 6722              		.loc 1 4163 26 view .LVU2269
+ 6723 0022 0B40     		ands	r3, r3, r1
+4163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pRxBuffPtr++;
+ 6724              		.loc 1 4163 24 view .LVU2270
+ 6725 0024 1370     		strb	r3, [r2]
+ 6726              	.LVL607:
+4164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount--;
+ 6727              		.loc 1 4164 5 is_stmt 1 view .LVU2271
+4164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount--;
+ 6728              		.loc 1 4164 10 is_stmt 0 view .LVU2272
+ 6729 0026 836D     		ldr	r3, [r0, #88]
+4164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount--;
+ 6730              		.loc 1 4164 22 view .LVU2273
+ 6731 0028 0133     		adds	r3, r3, #1
+ 6732 002a 8365     		str	r3, [r0, #88]
+4165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6733              		.loc 1 4165 5 is_stmt 1 view .LVU2274
+4165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6734              		.loc 1 4165 10 is_stmt 0 view .LVU2275
+ 6735 002c B0F85E30 		ldrh	r3, [r0, #94]
+ 6736 0030 9BB2     		uxth	r3, r3
+4165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6737              		.loc 1 4165 23 view .LVU2276
+ 6738 0032 013B     		subs	r3, r3, #1
+ 6739 0034 9BB2     		uxth	r3, r3
+ 6740 0036 A0F85E30 		strh	r3, [r0, #94]	@ movhi
+4167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 6741              		.loc 1 4167 5 is_stmt 1 view .LVU2277
+4167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 6742              		.loc 1 4167 14 is_stmt 0 view .LVU2278
+ARM GAS  /tmp/cceWHrnJ.s 			page 249
+
+
+ 6743 003a B0F85E30 		ldrh	r3, [r0, #94]
+ 6744 003e 9BB2     		uxth	r3, r3
+4167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 6745              		.loc 1 4167 8 view .LVU2279
+ 6746 0040 002B     		cmp	r3, #0
+ 6747 0042 E9D1     		bne	.L286
+ 6748              	.LVL608:
+ 6749              	.L289:
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6750              		.loc 1 4170 7 is_stmt 1 discriminator 1 view .LVU2280
+ 6751              	.LBB816:
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6752              		.loc 1 4170 7 discriminator 1 view .LVU2281
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6753              		.loc 1 4170 7 discriminator 1 view .LVU2282
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6754              		.loc 1 4170 7 discriminator 1 view .LVU2283
+ 6755 0044 0268     		ldr	r2, [r0]
+ 6756              	.LVL609:
+ 6757              	.LBB817:
+ 6758              	.LBI817:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6759              		.loc 2 1151 31 discriminator 1 view .LVU2284
+ 6760              	.LBB818:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6761              		.loc 2 1153 5 discriminator 1 view .LVU2285
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6762              		.loc 2 1155 4 discriminator 1 view .LVU2286
+ 6763              		.syntax unified
+ 6764              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6765 0046 52E8003F 		ldrex r3, [r2]
+ 6766              	@ 0 "" 2
+ 6767              	.LVL610:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6768              		.loc 2 1156 4 discriminator 1 view .LVU2287
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6769              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2288
+ 6770              		.thumb
+ 6771              		.syntax unified
+ 6772              	.LBE818:
+ 6773              	.LBE817:
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6774              		.loc 1 4170 7 discriminator 1 view .LVU2289
+ 6775 004a 23F49073 		bic	r3, r3, #288
+ 6776              	.LVL611:
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6777              		.loc 1 4170 7 is_stmt 1 discriminator 1 view .LVU2290
+ 6778              	.LBB819:
+ 6779              	.LBI819:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6780              		.loc 2 1202 31 discriminator 1 view .LVU2291
+ 6781              	.LBB820:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6782              		.loc 2 1204 4 discriminator 1 view .LVU2292
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6783              		.loc 2 1206 4 discriminator 1 view .LVU2293
+ 6784              		.syntax unified
+ARM GAS  /tmp/cceWHrnJ.s 			page 250
+
+
+ 6785              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6786 004e 42E80031 		strex r1, r3, [r2]
+ 6787              	@ 0 "" 2
+ 6788              	.LVL612:
+ 6789              		.loc 2 1207 4 discriminator 1 view .LVU2294
+ 6790              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2295
+ 6791              		.thumb
+ 6792              		.syntax unified
+ 6793              	.LBE820:
+ 6794              	.LBE819:
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6795              		.loc 1 4170 7 discriminator 1 view .LVU2296
+ 6796 0052 0029     		cmp	r1, #0
+ 6797 0054 F6D1     		bne	.L289
+ 6798              	.LVL613:
+ 6799              	.L290:
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6800              		.loc 1 4170 7 discriminator 1 view .LVU2297
+ 6801              	.LBE816:
+4170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6802              		.loc 1 4170 7 is_stmt 1 discriminator 1 view .LVU2298
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6803              		.loc 1 4173 7 discriminator 1 view .LVU2299
+ 6804              	.LBB821:
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6805              		.loc 1 4173 7 discriminator 1 view .LVU2300
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6806              		.loc 1 4173 7 discriminator 1 view .LVU2301
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6807              		.loc 1 4173 7 discriminator 1 view .LVU2302
+ 6808 0056 0268     		ldr	r2, [r0]
+ 6809              	.LVL614:
+ 6810              	.LBB822:
+ 6811              	.LBI822:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6812              		.loc 2 1151 31 discriminator 1 view .LVU2303
+ 6813              	.LBB823:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6814              		.loc 2 1153 5 discriminator 1 view .LVU2304
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6815              		.loc 2 1155 4 discriminator 1 view .LVU2305
+ 6816 0058 02F10803 		add	r3, r2, #8
+ 6817              	.LVL615:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6818              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU2306
+ 6819              		.syntax unified
+ 6820              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6821 005c 53E8003F 		ldrex r3, [r3]
+ 6822              	@ 0 "" 2
+ 6823              	.LVL616:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6824              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU2307
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6825              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2308
+ 6826              		.thumb
+ 6827              		.syntax unified
+ 6828              	.LBE823:
+ARM GAS  /tmp/cceWHrnJ.s 			page 251
+
+
+ 6829              	.LBE822:
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6830              		.loc 1 4173 7 discriminator 1 view .LVU2309
+ 6831 0060 23F00103 		bic	r3, r3, #1
+ 6832              	.LVL617:
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6833              		.loc 1 4173 7 is_stmt 1 discriminator 1 view .LVU2310
+ 6834              	.LBB824:
+ 6835              	.LBI824:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6836              		.loc 2 1202 31 discriminator 1 view .LVU2311
+ 6837              	.LBB825:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6838              		.loc 2 1204 4 discriminator 1 view .LVU2312
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6839              		.loc 2 1206 4 discriminator 1 view .LVU2313
+ 6840 0064 0832     		adds	r2, r2, #8
+ 6841              	.LVL618:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6842              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU2314
+ 6843              		.syntax unified
+ 6844              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6845 0066 42E80031 		strex r1, r3, [r2]
+ 6846              	@ 0 "" 2
+ 6847              	.LVL619:
+ 6848              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU2315
+ 6849              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2316
+ 6850              		.thumb
+ 6851              		.syntax unified
+ 6852              	.LBE825:
+ 6853              	.LBE824:
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6854              		.loc 1 4173 7 discriminator 1 view .LVU2317
+ 6855 006a 0029     		cmp	r1, #0
+ 6856 006c F3D1     		bne	.L290
+ 6857              	.LBE821:
+4173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6858              		.loc 1 4173 7 is_stmt 1 discriminator 2 view .LVU2318
+4176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6859              		.loc 1 4176 7 discriminator 2 view .LVU2319
+4176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6860              		.loc 1 4176 22 is_stmt 0 discriminator 2 view .LVU2320
+ 6861 006e 2023     		movs	r3, #32
+ 6862              	.LVL620:
+4176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6863              		.loc 1 4176 22 discriminator 2 view .LVU2321
+ 6864 0070 C0F88830 		str	r3, [r0, #136]
+4179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6865              		.loc 1 4179 7 is_stmt 1 discriminator 2 view .LVU2322
+4179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6866              		.loc 1 4179 20 is_stmt 0 discriminator 2 view .LVU2323
+ 6867 0074 0023     		movs	r3, #0
+ 6868 0076 0367     		str	r3, [r0, #112]
+4183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 6869              		.loc 1 4183 7 is_stmt 1 discriminator 2 view .LVU2324
+4183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 6870              		.loc 1 4183 16 is_stmt 0 discriminator 2 view .LVU2325
+ARM GAS  /tmp/cceWHrnJ.s 			page 252
+
+
+ 6871 0078 C36E     		ldr	r3, [r0, #108]
+4183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 6872              		.loc 1 4183 10 discriminator 2 view .LVU2326
+ 6873 007a 012B     		cmp	r3, #1
+ 6874 007c 16D1     		bne	.L291
+4186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6875              		.loc 1 4186 9 is_stmt 1 view .LVU2327
+4186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6876              		.loc 1 4186 30 is_stmt 0 view .LVU2328
+ 6877 007e 0023     		movs	r3, #0
+ 6878 0080 C366     		str	r3, [r0, #108]
+ 6879              	.L292:
+4189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6880              		.loc 1 4189 9 is_stmt 1 discriminator 1 view .LVU2329
+ 6881              	.LBB826:
+4189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6882              		.loc 1 4189 9 discriminator 1 view .LVU2330
+4189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6883              		.loc 1 4189 9 discriminator 1 view .LVU2331
+4189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6884              		.loc 1 4189 9 discriminator 1 view .LVU2332
+ 6885 0082 0268     		ldr	r2, [r0]
+ 6886              	.LVL621:
+ 6887              	.LBB827:
+ 6888              	.LBI827:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6889              		.loc 2 1151 31 discriminator 1 view .LVU2333
+ 6890              	.LBB828:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6891              		.loc 2 1153 5 discriminator 1 view .LVU2334
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6892              		.loc 2 1155 4 discriminator 1 view .LVU2335
+ 6893              		.syntax unified
+ 6894              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6895 0084 52E8003F 		ldrex r3, [r2]
+ 6896              	@ 0 "" 2
+ 6897              	.LVL622:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6898              		.loc 2 1156 4 discriminator 1 view .LVU2336
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6899              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2337
+ 6900              		.thumb
+ 6901              		.syntax unified
+ 6902              	.LBE828:
+ 6903              	.LBE827:
+4189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6904              		.loc 1 4189 9 discriminator 1 view .LVU2338
+ 6905 0088 23F01003 		bic	r3, r3, #16
+ 6906              	.LVL623:
+4189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6907              		.loc 1 4189 9 is_stmt 1 discriminator 1 view .LVU2339
+ 6908              	.LBB829:
+ 6909              	.LBI829:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6910              		.loc 2 1202 31 discriminator 1 view .LVU2340
+ 6911              	.LBB830:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 253
+
+
+ 6912              		.loc 2 1204 4 discriminator 1 view .LVU2341
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6913              		.loc 2 1206 4 discriminator 1 view .LVU2342
+ 6914              		.syntax unified
+ 6915              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6916 008c 42E80031 		strex r1, r3, [r2]
+ 6917              	@ 0 "" 2
+ 6918              	.LVL624:
+ 6919              		.loc 2 1207 4 discriminator 1 view .LVU2343
+ 6920              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2344
+ 6921              		.thumb
+ 6922              		.syntax unified
+ 6923              	.LBE830:
+ 6924              	.LBE829:
+4189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6925              		.loc 1 4189 9 discriminator 1 view .LVU2345
+ 6926 0090 0029     		cmp	r1, #0
+ 6927 0092 F6D1     		bne	.L292
+ 6928              	.LBE826:
+4189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 6929              		.loc 1 4189 9 is_stmt 1 discriminator 2 view .LVU2346
+4191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 6930              		.loc 1 4191 9 discriminator 2 view .LVU2347
+4191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 6931              		.loc 1 4191 13 is_stmt 0 discriminator 2 view .LVU2348
+ 6932 0094 0368     		ldr	r3, [r0]
+ 6933              	.LVL625:
+4191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 6934              		.loc 1 4191 13 discriminator 2 view .LVU2349
+ 6935 0096 DA69     		ldr	r2, [r3, #28]
+4191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 6936              		.loc 1 4191 12 discriminator 2 view .LVU2350
+ 6937 0098 12F0100F 		tst	r2, #16
+ 6938 009c 01D0     		beq	.L293
+4194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 6939              		.loc 1 4194 11 is_stmt 1 view .LVU2351
+ 6940 009e 1022     		movs	r2, #16
+ 6941 00a0 1A62     		str	r2, [r3, #32]
+ 6942              	.L293:
+4201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 6943              		.loc 1 4201 9 view .LVU2352
+ 6944 00a2 B0F85C10 		ldrh	r1, [r0, #92]
+ 6945 00a6 FFF7FEFF 		bl	HAL_UARTEx_RxEventCallback
+ 6946              	.LVL626:
+4201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 6947              		.loc 1 4201 9 is_stmt 0 view .LVU2353
+ 6948 00aa B5E7     		b	.L286
+ 6949              	.LVL627:
+ 6950              	.L291:
+4212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 6951              		.loc 1 4212 9 is_stmt 1 view .LVU2354
+ 6952 00ac FFF7FEFF 		bl	HAL_UART_RxCpltCallback
+ 6953              	.LVL628:
+4212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 6954              		.loc 1 4212 9 is_stmt 0 view .LVU2355
+ 6955 00b0 B2E7     		b	.L286
+ 6956              		.cfi_endproc
+ARM GAS  /tmp/cceWHrnJ.s 			page 254
+
+
+ 6957              	.LFE395:
+ 6959              		.section	.text.UART_RxISR_16BIT,"ax",%progbits
+ 6960              		.align	1
+ 6961              		.syntax unified
+ 6962              		.thumb
+ 6963              		.thumb_func
+ 6965              	UART_RxISR_16BIT:
+ 6966              	.LVL629:
+ 6967              	.LFB396:
+4223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+4225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief RX interrupt handler for 9 bits data word length .
+4226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   Function is called under interruption only, once
+4227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         interruptions have been enabled by HAL_UART_Receive_IT()
+4228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+4229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+4230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+4231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+4232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 6968              		.loc 1 4232 1 is_stmt 1 view -0
+ 6969              		.cfi_startproc
+ 6970              		@ args = 0, pretend = 0, frame = 0
+ 6971              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6972              		.loc 1 4232 1 is_stmt 0 view .LVU2357
+ 6973 0000 08B5     		push	{r3, lr}
+ 6974              	.LCFI26:
+ 6975              		.cfi_def_cfa_offset 8
+ 6976              		.cfi_offset 3, -8
+ 6977              		.cfi_offset 14, -4
+4233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t *tmp;
+ 6978              		.loc 1 4233 3 is_stmt 1 view .LVU2358
+4234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t uhMask = huart->Mask;
+ 6979              		.loc 1 4234 3 view .LVU2359
+ 6980              		.loc 1 4234 12 is_stmt 0 view .LVU2360
+ 6981 0002 B0F86020 		ldrh	r2, [r0, #96]
+ 6982              	.LVL630:
+4235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t  uhdata;
+ 6983              		.loc 1 4235 3 is_stmt 1 view .LVU2361
+4236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Rx process is ongoing */
+4238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ 6984              		.loc 1 4238 3 view .LVU2362
+ 6985              		.loc 1 4238 12 is_stmt 0 view .LVU2363
+ 6986 0006 D0F88830 		ldr	r3, [r0, #136]
+ 6987              		.loc 1 4238 6 view .LVU2364
+ 6988 000a 222B     		cmp	r3, #34
+ 6989 000c 05D0     		beq	.L305
+4239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+4240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+4241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     tmp = (uint16_t *) huart->pRxBuffPtr ;
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     *tmp = (uint16_t)(uhdata & uhMask);
+4243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pRxBuffPtr += 2U;
+4244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount--;
+4245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if (huart->RxXferCount == 0U)
+4247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+4248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+ARM GAS  /tmp/cceWHrnJ.s 			page 255
+
+
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+4250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+4253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Rx process is completed, restore huart->RxState to Ready */
+4255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxState = HAL_UART_STATE_READY;
+4256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Clear RxISR function pointer */
+4258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxISR = NULL;
+4259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Check current reception Mode :
+4261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****          If Reception till IDLE event has been selected : */
+4262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+4263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Set reception type to Standard */
+4265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+4266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Disable IDLE interrupt */
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+4269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+4271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Clear IDLE Flag */
+4273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+4274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+4276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call registered Rx Event callback*/
+4277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxEventCallback(huart, huart->RxXferSize);
+4278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+4279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call legacy weak Rx Event callback*/
+4280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+4281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+4282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       else
+4284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Standard reception API called */
+4286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+4287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call registered Rx complete callback*/
+4288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxCpltCallback(huart);
+4289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+4290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /*Call legacy weak Rx complete callback*/
+4291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         HAL_UART_RxCpltCallback(huart);
+4292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+4293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+4295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+4296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+4297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+4298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Clear RXNE interrupt flag */
+4299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ 6990              		.loc 1 4299 5 is_stmt 1 view .LVU2365
+ 6991 000e 0268     		ldr	r2, [r0]
+ 6992              	.LVL631:
+ 6993              		.loc 1 4299 5 is_stmt 0 view .LVU2366
+ 6994 0010 9369     		ldr	r3, [r2, #24]
+ 6995 0012 43F00803 		orr	r3, r3, #8
+ARM GAS  /tmp/cceWHrnJ.s 			page 256
+
+
+ 6996 0016 9361     		str	r3, [r2, #24]
+ 6997              	.LVL632:
+ 6998              	.L296:
+4300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+4301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 6999              		.loc 1 4301 1 view .LVU2367
+ 7000 0018 08BD     		pop	{r3, pc}
+ 7001              	.LVL633:
+ 7002              	.L305:
+4240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     tmp = (uint16_t *) huart->pRxBuffPtr ;
+ 7003              		.loc 1 4240 5 is_stmt 1 view .LVU2368
+4240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     tmp = (uint16_t *) huart->pRxBuffPtr ;
+ 7004              		.loc 1 4240 25 is_stmt 0 view .LVU2369
+ 7005 001a 0368     		ldr	r3, [r0]
+ 7006 001c 5B6A     		ldr	r3, [r3, #36]
+ 7007              	.LVL634:
+4241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     *tmp = (uint16_t)(uhdata & uhMask);
+ 7008              		.loc 1 4241 5 is_stmt 1 view .LVU2370
+4241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     *tmp = (uint16_t)(uhdata & uhMask);
+ 7009              		.loc 1 4241 9 is_stmt 0 view .LVU2371
+ 7010 001e 816D     		ldr	r1, [r0, #88]
+ 7011              	.LVL635:
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pRxBuffPtr += 2U;
+ 7012              		.loc 1 4242 5 is_stmt 1 view .LVU2372
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pRxBuffPtr += 2U;
+ 7013              		.loc 1 4242 12 is_stmt 0 view .LVU2373
+ 7014 0020 1340     		ands	r3, r3, r2
+ 7015              	.LVL636:
+4242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->pRxBuffPtr += 2U;
+ 7016              		.loc 1 4242 10 view .LVU2374
+ 7017 0022 0B80     		strh	r3, [r1]	@ movhi
+4243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount--;
+ 7018              		.loc 1 4243 5 is_stmt 1 view .LVU2375
+4243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount--;
+ 7019              		.loc 1 4243 10 is_stmt 0 view .LVU2376
+ 7020 0024 836D     		ldr	r3, [r0, #88]
+4243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount--;
+ 7021              		.loc 1 4243 23 view .LVU2377
+ 7022 0026 0233     		adds	r3, r3, #2
+ 7023 0028 8365     		str	r3, [r0, #88]
+4244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7024              		.loc 1 4244 5 is_stmt 1 view .LVU2378
+4244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7025              		.loc 1 4244 10 is_stmt 0 view .LVU2379
+ 7026 002a B0F85E30 		ldrh	r3, [r0, #94]
+ 7027 002e 9BB2     		uxth	r3, r3
+4244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7028              		.loc 1 4244 23 view .LVU2380
+ 7029 0030 013B     		subs	r3, r3, #1
+ 7030 0032 9BB2     		uxth	r3, r3
+ 7031 0034 A0F85E30 		strh	r3, [r0, #94]	@ movhi
+4246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7032              		.loc 1 4246 5 is_stmt 1 view .LVU2381
+4246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7033              		.loc 1 4246 14 is_stmt 0 view .LVU2382
+ 7034 0038 B0F85E30 		ldrh	r3, [r0, #94]
+ 7035 003c 9BB2     		uxth	r3, r3
+ARM GAS  /tmp/cceWHrnJ.s 			page 257
+
+
+4246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7036              		.loc 1 4246 8 view .LVU2383
+ 7037 003e 002B     		cmp	r3, #0
+ 7038 0040 EAD1     		bne	.L296
+ 7039              	.LVL637:
+ 7040              	.L299:
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7041              		.loc 1 4249 7 is_stmt 1 discriminator 1 view .LVU2384
+ 7042              	.LBB831:
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7043              		.loc 1 4249 7 discriminator 1 view .LVU2385
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7044              		.loc 1 4249 7 discriminator 1 view .LVU2386
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7045              		.loc 1 4249 7 discriminator 1 view .LVU2387
+ 7046 0042 0268     		ldr	r2, [r0]
+ 7047              	.LVL638:
+ 7048              	.LBB832:
+ 7049              	.LBI832:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7050              		.loc 2 1151 31 discriminator 1 view .LVU2388
+ 7051              	.LBB833:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7052              		.loc 2 1153 5 discriminator 1 view .LVU2389
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7053              		.loc 2 1155 4 discriminator 1 view .LVU2390
+ 7054              		.syntax unified
+ 7055              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7056 0044 52E8003F 		ldrex r3, [r2]
+ 7057              	@ 0 "" 2
+ 7058              	.LVL639:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7059              		.loc 2 1156 4 discriminator 1 view .LVU2391
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7060              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2392
+ 7061              		.thumb
+ 7062              		.syntax unified
+ 7063              	.LBE833:
+ 7064              	.LBE832:
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7065              		.loc 1 4249 7 discriminator 1 view .LVU2393
+ 7066 0048 23F49073 		bic	r3, r3, #288
+ 7067              	.LVL640:
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7068              		.loc 1 4249 7 is_stmt 1 discriminator 1 view .LVU2394
+ 7069              	.LBB834:
+ 7070              	.LBI834:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7071              		.loc 2 1202 31 discriminator 1 view .LVU2395
+ 7072              	.LBB835:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7073              		.loc 2 1204 4 discriminator 1 view .LVU2396
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7074              		.loc 2 1206 4 discriminator 1 view .LVU2397
+ 7075              		.syntax unified
+ 7076              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7077 004c 42E80031 		strex r1, r3, [r2]
+ARM GAS  /tmp/cceWHrnJ.s 			page 258
+
+
+ 7078              	@ 0 "" 2
+ 7079              	.LVL641:
+ 7080              		.loc 2 1207 4 discriminator 1 view .LVU2398
+ 7081              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2399
+ 7082              		.thumb
+ 7083              		.syntax unified
+ 7084              	.LBE835:
+ 7085              	.LBE834:
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7086              		.loc 1 4249 7 discriminator 1 view .LVU2400
+ 7087 0050 0029     		cmp	r1, #0
+ 7088 0052 F6D1     		bne	.L299
+ 7089              	.LVL642:
+ 7090              	.L300:
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7091              		.loc 1 4249 7 discriminator 1 view .LVU2401
+ 7092              	.LBE831:
+4249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7093              		.loc 1 4249 7 is_stmt 1 discriminator 1 view .LVU2402
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7094              		.loc 1 4252 7 discriminator 1 view .LVU2403
+ 7095              	.LBB836:
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7096              		.loc 1 4252 7 discriminator 1 view .LVU2404
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7097              		.loc 1 4252 7 discriminator 1 view .LVU2405
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7098              		.loc 1 4252 7 discriminator 1 view .LVU2406
+ 7099 0054 0268     		ldr	r2, [r0]
+ 7100              	.LVL643:
+ 7101              	.LBB837:
+ 7102              	.LBI837:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7103              		.loc 2 1151 31 discriminator 1 view .LVU2407
+ 7104              	.LBB838:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7105              		.loc 2 1153 5 discriminator 1 view .LVU2408
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7106              		.loc 2 1155 4 discriminator 1 view .LVU2409
+ 7107 0056 02F10803 		add	r3, r2, #8
+ 7108              	.LVL644:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7109              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU2410
+ 7110              		.syntax unified
+ 7111              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7112 005a 53E8003F 		ldrex r3, [r3]
+ 7113              	@ 0 "" 2
+ 7114              	.LVL645:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7115              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU2411
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7116              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2412
+ 7117              		.thumb
+ 7118              		.syntax unified
+ 7119              	.LBE838:
+ 7120              	.LBE837:
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 259
+
+
+ 7121              		.loc 1 4252 7 discriminator 1 view .LVU2413
+ 7122 005e 23F00103 		bic	r3, r3, #1
+ 7123              	.LVL646:
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7124              		.loc 1 4252 7 is_stmt 1 discriminator 1 view .LVU2414
+ 7125              	.LBB839:
+ 7126              	.LBI839:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7127              		.loc 2 1202 31 discriminator 1 view .LVU2415
+ 7128              	.LBB840:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7129              		.loc 2 1204 4 discriminator 1 view .LVU2416
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7130              		.loc 2 1206 4 discriminator 1 view .LVU2417
+ 7131 0062 0832     		adds	r2, r2, #8
+ 7132              	.LVL647:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7133              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU2418
+ 7134              		.syntax unified
+ 7135              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7136 0064 42E80031 		strex r1, r3, [r2]
+ 7137              	@ 0 "" 2
+ 7138              	.LVL648:
+ 7139              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU2419
+ 7140              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2420
+ 7141              		.thumb
+ 7142              		.syntax unified
+ 7143              	.LBE840:
+ 7144              	.LBE839:
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7145              		.loc 1 4252 7 discriminator 1 view .LVU2421
+ 7146 0068 0029     		cmp	r1, #0
+ 7147 006a F3D1     		bne	.L300
+ 7148              	.LBE836:
+4252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7149              		.loc 1 4252 7 is_stmt 1 discriminator 2 view .LVU2422
+4255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7150              		.loc 1 4255 7 discriminator 2 view .LVU2423
+4255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7151              		.loc 1 4255 22 is_stmt 0 discriminator 2 view .LVU2424
+ 7152 006c 2023     		movs	r3, #32
+ 7153              	.LVL649:
+4255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7154              		.loc 1 4255 22 discriminator 2 view .LVU2425
+ 7155 006e C0F88830 		str	r3, [r0, #136]
+4258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7156              		.loc 1 4258 7 is_stmt 1 discriminator 2 view .LVU2426
+4258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7157              		.loc 1 4258 20 is_stmt 0 discriminator 2 view .LVU2427
+ 7158 0072 0023     		movs	r3, #0
+ 7159 0074 0367     		str	r3, [r0, #112]
+4262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 7160              		.loc 1 4262 7 is_stmt 1 discriminator 2 view .LVU2428
+4262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 7161              		.loc 1 4262 16 is_stmt 0 discriminator 2 view .LVU2429
+ 7162 0076 C36E     		ldr	r3, [r0, #108]
+4262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ARM GAS  /tmp/cceWHrnJ.s 			page 260
+
+
+ 7163              		.loc 1 4262 10 discriminator 2 view .LVU2430
+ 7164 0078 012B     		cmp	r3, #1
+ 7165 007a 16D1     		bne	.L301
+4265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7166              		.loc 1 4265 9 is_stmt 1 view .LVU2431
+4265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7167              		.loc 1 4265 30 is_stmt 0 view .LVU2432
+ 7168 007c 0023     		movs	r3, #0
+ 7169 007e C366     		str	r3, [r0, #108]
+ 7170              	.L302:
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7171              		.loc 1 4268 9 is_stmt 1 discriminator 1 view .LVU2433
+ 7172              	.LBB841:
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7173              		.loc 1 4268 9 discriminator 1 view .LVU2434
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7174              		.loc 1 4268 9 discriminator 1 view .LVU2435
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7175              		.loc 1 4268 9 discriminator 1 view .LVU2436
+ 7176 0080 0268     		ldr	r2, [r0]
+ 7177              	.LVL650:
+ 7178              	.LBB842:
+ 7179              	.LBI842:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7180              		.loc 2 1151 31 discriminator 1 view .LVU2437
+ 7181              	.LBB843:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7182              		.loc 2 1153 5 discriminator 1 view .LVU2438
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7183              		.loc 2 1155 4 discriminator 1 view .LVU2439
+ 7184              		.syntax unified
+ 7185              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7186 0082 52E8003F 		ldrex r3, [r2]
+ 7187              	@ 0 "" 2
+ 7188              	.LVL651:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7189              		.loc 2 1156 4 discriminator 1 view .LVU2440
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7190              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2441
+ 7191              		.thumb
+ 7192              		.syntax unified
+ 7193              	.LBE843:
+ 7194              	.LBE842:
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7195              		.loc 1 4268 9 discriminator 1 view .LVU2442
+ 7196 0086 23F01003 		bic	r3, r3, #16
+ 7197              	.LVL652:
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7198              		.loc 1 4268 9 is_stmt 1 discriminator 1 view .LVU2443
+ 7199              	.LBB844:
+ 7200              	.LBI844:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7201              		.loc 2 1202 31 discriminator 1 view .LVU2444
+ 7202              	.LBB845:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7203              		.loc 2 1204 4 discriminator 1 view .LVU2445
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ARM GAS  /tmp/cceWHrnJ.s 			page 261
+
+
+ 7204              		.loc 2 1206 4 discriminator 1 view .LVU2446
+ 7205              		.syntax unified
+ 7206              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7207 008a 42E80031 		strex r1, r3, [r2]
+ 7208              	@ 0 "" 2
+ 7209              	.LVL653:
+ 7210              		.loc 2 1207 4 discriminator 1 view .LVU2447
+ 7211              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2448
+ 7212              		.thumb
+ 7213              		.syntax unified
+ 7214              	.LBE845:
+ 7215              	.LBE844:
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7216              		.loc 1 4268 9 discriminator 1 view .LVU2449
+ 7217 008e 0029     		cmp	r1, #0
+ 7218 0090 F6D1     		bne	.L302
+ 7219              	.LBE841:
+4268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7220              		.loc 1 4268 9 is_stmt 1 discriminator 2 view .LVU2450
+4270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7221              		.loc 1 4270 9 discriminator 2 view .LVU2451
+4270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7222              		.loc 1 4270 13 is_stmt 0 discriminator 2 view .LVU2452
+ 7223 0092 0368     		ldr	r3, [r0]
+ 7224              	.LVL654:
+4270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7225              		.loc 1 4270 13 discriminator 2 view .LVU2453
+ 7226 0094 DA69     		ldr	r2, [r3, #28]
+4270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7227              		.loc 1 4270 12 discriminator 2 view .LVU2454
+ 7228 0096 12F0100F 		tst	r2, #16
+ 7229 009a 01D0     		beq	.L303
+4273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7230              		.loc 1 4273 11 is_stmt 1 view .LVU2455
+ 7231 009c 1022     		movs	r2, #16
+ 7232 009e 1A62     		str	r2, [r3, #32]
+ 7233              	.L303:
+4280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 7234              		.loc 1 4280 9 view .LVU2456
+ 7235 00a0 B0F85C10 		ldrh	r1, [r0, #92]
+ 7236 00a4 FFF7FEFF 		bl	HAL_UARTEx_RxEventCallback
+ 7237              	.LVL655:
+4280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 7238              		.loc 1 4280 9 is_stmt 0 view .LVU2457
+ 7239 00a8 B6E7     		b	.L296
+ 7240              	.LVL656:
+ 7241              	.L301:
+4291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 7242              		.loc 1 4291 9 is_stmt 1 view .LVU2458
+ 7243 00aa FFF7FEFF 		bl	HAL_UART_RxCpltCallback
+ 7244              	.LVL657:
+4291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 7245              		.loc 1 4291 9 is_stmt 0 view .LVU2459
+ 7246 00ae B3E7     		b	.L296
+ 7247              		.cfi_endproc
+ 7248              	.LFE396:
+ 7250              		.section	.text.UART_RxISR_8BIT_FIFOEN,"ax",%progbits
+ARM GAS  /tmp/cceWHrnJ.s 			page 262
+
+
+ 7251              		.align	1
+ 7252              		.syntax unified
+ 7253              		.thumb
+ 7254              		.thumb_func
+ 7256              	UART_RxISR_8BIT_FIFOEN:
+ 7257              	.LVL658:
+ 7258              	.LFB397:
+4302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+4304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief RX interrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.
+4305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   Function is called under interruption only, once
+4306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         interruptions have been enabled by HAL_UART_Receive_IT()
+4307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+4308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+4309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+4310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+4311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 7259              		.loc 1 4311 1 is_stmt 1 view -0
+ 7260              		.cfi_startproc
+ 7261              		@ args = 0, pretend = 0, frame = 0
+ 7262              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7263              		.loc 1 4311 1 is_stmt 0 view .LVU2461
+ 7264 0000 2DE9F843 		push	{r3, r4, r5, r6, r7, r8, r9, lr}
+ 7265              	.LCFI27:
+ 7266              		.cfi_def_cfa_offset 32
+ 7267              		.cfi_offset 3, -32
+ 7268              		.cfi_offset 4, -28
+ 7269              		.cfi_offset 5, -24
+ 7270              		.cfi_offset 6, -20
+ 7271              		.cfi_offset 7, -16
+ 7272              		.cfi_offset 8, -12
+ 7273              		.cfi_offset 9, -8
+ 7274              		.cfi_offset 14, -4
+4312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t  uhMask = huart->Mask;
+ 7275              		.loc 1 4312 3 is_stmt 1 view .LVU2462
+ 7276              		.loc 1 4312 13 is_stmt 0 view .LVU2463
+ 7277 0004 B0F86060 		ldrh	r6, [r0, #96]
+ 7278              	.LVL659:
+4313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t  uhdata;
+ 7279              		.loc 1 4313 3 is_stmt 1 view .LVU2464
+4314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t  nb_rx_data;
+ 7280              		.loc 1 4314 3 view .LVU2465
+4315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t  rxdatacount;
+ 7281              		.loc 1 4315 3 view .LVU2466
+4316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t  isrflags = READ_REG(huart->Instance->ISR);
+ 7282              		.loc 1 4316 3 view .LVU2467
+ 7283              		.loc 1 4316 24 is_stmt 0 view .LVU2468
+ 7284 0008 0368     		ldr	r3, [r0]
+ 7285              		.loc 1 4316 13 view .LVU2469
+ 7286 000a DD69     		ldr	r5, [r3, #28]
+ 7287              	.LVL660:
+4317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
+ 7288              		.loc 1 4317 3 is_stmt 1 view .LVU2470
+ 7289              		.loc 1 4317 13 is_stmt 0 view .LVU2471
+ 7290 000c D3F80090 		ldr	r9, [r3]
+ 7291              	.LVL661:
+4318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
+ARM GAS  /tmp/cceWHrnJ.s 			page 263
+
+
+ 7292              		.loc 1 4318 3 is_stmt 1 view .LVU2472
+ 7293              		.loc 1 4318 13 is_stmt 0 view .LVU2473
+ 7294 0010 D3F80880 		ldr	r8, [r3, #8]
+ 7295              	.LVL662:
+4319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Rx process is ongoing */
+4321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ 7296              		.loc 1 4321 3 is_stmt 1 view .LVU2474
+ 7297              		.loc 1 4321 12 is_stmt 0 view .LVU2475
+ 7298 0014 D0F88820 		ldr	r2, [r0, #136]
+ 7299              		.loc 1 4321 6 view .LVU2476
+ 7300 0018 222A     		cmp	r2, #34
+ 7301 001a 05D0     		beq	.L325
+4322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+4323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     nb_rx_data = huart->NbRxDataToProcess;
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+4325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+4326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+4327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+4328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pRxBuffPtr++;
+4329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxXferCount--;
+4330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       isrflags = READ_REG(huart->Instance->ISR);
+4331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* If some non blocking errors occurred */
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+4334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* UART parity error interrupt occurred -------------------------------------*/
+4336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+4337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+4339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode |= HAL_UART_ERROR_PE;
+4341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* UART frame error interrupt occurred --------------------------------------*/
+4344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+4345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+4347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode |= HAL_UART_ERROR_FE;
+4349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* UART noise error interrupt occurred --------------------------------------*/
+4352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+4353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+4355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode |= HAL_UART_ERROR_NE;
+4357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Call UART Error Call back function if need be ----------------------------*/
+4360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+4361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Non Blocking error : transfer could go on.
+4363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           Error is notified to user through user error callback */
+4364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+4365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call registered error callback*/
+ARM GAS  /tmp/cceWHrnJ.s 			page 264
+
+
+4366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCallback(huart);
+4367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+4368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call legacy weak error callback*/
+4369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           HAL_UART_ErrorCallback(huart);
+4370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+4371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode = HAL_UART_ERROR_NONE;
+4372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (huart->RxXferCount == 0U)
+4376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+4378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+4379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+4381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            and RX FIFO Threshold interrupt */
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+4383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Rx process is completed, restore huart->RxState to Ready */
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxState = HAL_UART_STATE_READY;
+4386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Clear RxISR function pointer */
+4388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxISR = NULL;
+4389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Check current reception Mode :
+4391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            If Reception till IDLE event has been selected : */
+4392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+4393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Set reception type to Standard */
+4395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+4396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Disable IDLE interrupt */
+4398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+4399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+4401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+4402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             /* Clear IDLE Flag */
+4403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+4404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           }
+4405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+4406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call registered Rx Event callback*/
+4407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->RxEventCallback(huart, huart->RxXferSize);
+4408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+4409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call legacy weak Rx Event callback*/
+4410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+4411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+4412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         else
+4414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Standard reception API called */
+4416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+4417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call registered Rx complete callback*/
+4418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->RxCpltCallback(huart);
+4419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+4420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call legacy weak Rx complete callback*/
+4421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           HAL_UART_RxCpltCallback(huart);
+4422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ARM GAS  /tmp/cceWHrnJ.s 			page 265
+
+
+4423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+4426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* When remaining number of bytes to receive is less than the RX FIFO
+4428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     threshold, next incoming frames are processed as if FIFO mode was
+4429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     disabled (i.e. one interrupt per received frame).
+4430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     */
+4431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     rxdatacount = huart->RxXferCount;
+4432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+4433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+4434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Disable the UART RXFT interrupt*/
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+4436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Update the RxISR function pointer */
+4438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxISR = UART_RxISR_8BIT;
+4439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Enable the UART Data Register Not Empty interrupt */
+4441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+4442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+4443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+4444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+4445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+4446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Clear RXNE interrupt flag */
+4447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ 7302              		.loc 1 4447 5 is_stmt 1 view .LVU2477
+ 7303 001c 9A69     		ldr	r2, [r3, #24]
+ 7304 001e 42F00802 		orr	r2, r2, #8
+ 7305 0022 9A61     		str	r2, [r3, #24]
+ 7306              	.LVL663:
+ 7307              	.L306:
+4448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+4449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 7308              		.loc 1 4449 1 is_stmt 0 view .LVU2478
+ 7309 0024 BDE8F883 		pop	{r3, r4, r5, r6, r7, r8, r9, pc}
+ 7310              	.LVL664:
+ 7311              	.L325:
+ 7312              		.loc 1 4449 1 view .LVU2479
+ 7313 0028 0446     		mov	r4, r0
+4323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+ 7314              		.loc 1 4323 5 is_stmt 1 view .LVU2480
+4323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+ 7315              		.loc 1 4323 16 is_stmt 0 view .LVU2481
+ 7316 002a B0F86870 		ldrh	r7, [r0, #104]
+ 7317              	.LVL665:
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7318              		.loc 1 4324 5 is_stmt 1 view .LVU2482
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7319              		.loc 1 4324 11 is_stmt 0 view .LVU2483
+ 7320 002e 08E0     		b	.L308
+ 7321              	.LVL666:
+ 7322              	.L312:
+4360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7323              		.loc 1 4360 9 is_stmt 1 view .LVU2484
+4360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7324              		.loc 1 4360 18 is_stmt 0 view .LVU2485
+ 7325 0030 D4F88C30 		ldr	r3, [r4, #140]
+ARM GAS  /tmp/cceWHrnJ.s 			page 266
+
+
+4360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7326              		.loc 1 4360 12 view .LVU2486
+ 7327 0034 002B     		cmp	r3, #0
+ 7328 0036 4CD1     		bne	.L326
+ 7329              	.LVL667:
+ 7330              	.L309:
+4375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 7331              		.loc 1 4375 7 is_stmt 1 view .LVU2487
+4375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 7332              		.loc 1 4375 16 is_stmt 0 view .LVU2488
+ 7333 0038 B4F85E30 		ldrh	r3, [r4, #94]
+ 7334 003c 9BB2     		uxth	r3, r3
+4375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 7335              		.loc 1 4375 10 view .LVU2489
+ 7336 003e 002B     		cmp	r3, #0
+ 7337 0040 4ED0     		beq	.L314
+ 7338              	.LVL668:
+ 7339              	.L308:
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7340              		.loc 1 4324 30 is_stmt 1 view .LVU2490
+ 7341 0042 002F     		cmp	r7, #0
+ 7342 0044 00F08780 		beq	.L319
+4324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7343              		.loc 1 4324 30 is_stmt 0 discriminator 1 view .LVU2491
+ 7344 0048 15F0200F 		tst	r5, #32
+ 7345 004c 00F08380 		beq	.L319
+4326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ 7346              		.loc 1 4326 7 is_stmt 1 view .LVU2492
+4326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ 7347              		.loc 1 4326 27 is_stmt 0 view .LVU2493
+ 7348 0050 2368     		ldr	r3, [r4]
+ 7349 0052 596A     		ldr	r1, [r3, #36]
+ 7350              	.LVL669:
+4327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pRxBuffPtr++;
+ 7351              		.loc 1 4327 7 is_stmt 1 view .LVU2494
+4327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pRxBuffPtr++;
+ 7352              		.loc 1 4327 47 is_stmt 0 view .LVU2495
+ 7353 0054 F3B2     		uxtb	r3, r6
+4327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pRxBuffPtr++;
+ 7354              		.loc 1 4327 13 view .LVU2496
+ 7355 0056 A26D     		ldr	r2, [r4, #88]
+4327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pRxBuffPtr++;
+ 7356              		.loc 1 4327 28 view .LVU2497
+ 7357 0058 0B40     		ands	r3, r3, r1
+4327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pRxBuffPtr++;
+ 7358              		.loc 1 4327 26 view .LVU2498
+ 7359 005a 1370     		strb	r3, [r2]
+4328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxXferCount--;
+ 7360              		.loc 1 4328 7 is_stmt 1 view .LVU2499
+4328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxXferCount--;
+ 7361              		.loc 1 4328 12 is_stmt 0 view .LVU2500
+ 7362 005c A36D     		ldr	r3, [r4, #88]
+4328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxXferCount--;
+ 7363              		.loc 1 4328 24 view .LVU2501
+ 7364 005e 0133     		adds	r3, r3, #1
+ 7365 0060 A365     		str	r3, [r4, #88]
+4329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       isrflags = READ_REG(huart->Instance->ISR);
+ARM GAS  /tmp/cceWHrnJ.s 			page 267
+
+
+ 7366              		.loc 1 4329 7 is_stmt 1 view .LVU2502
+4329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       isrflags = READ_REG(huart->Instance->ISR);
+ 7367              		.loc 1 4329 12 is_stmt 0 view .LVU2503
+ 7368 0062 B4F85E30 		ldrh	r3, [r4, #94]
+ 7369 0066 9BB2     		uxth	r3, r3
+4329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       isrflags = READ_REG(huart->Instance->ISR);
+ 7370              		.loc 1 4329 25 view .LVU2504
+ 7371 0068 013B     		subs	r3, r3, #1
+ 7372 006a 9BB2     		uxth	r3, r3
+ 7373 006c A4F85E30 		strh	r3, [r4, #94]	@ movhi
+4330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7374              		.loc 1 4330 7 is_stmt 1 view .LVU2505
+4330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7375              		.loc 1 4330 18 is_stmt 0 view .LVU2506
+ 7376 0070 2368     		ldr	r3, [r4]
+4330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7377              		.loc 1 4330 16 view .LVU2507
+ 7378 0072 DD69     		ldr	r5, [r3, #28]
+ 7379              	.LVL670:
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 7380              		.loc 1 4333 7 is_stmt 1 view .LVU2508
+4333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 7381              		.loc 1 4333 10 is_stmt 0 view .LVU2509
+ 7382 0074 15F0070F 		tst	r5, #7
+ 7383 0078 DED0     		beq	.L309
+4336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7384              		.loc 1 4336 9 is_stmt 1 view .LVU2510
+4336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7385              		.loc 1 4336 12 is_stmt 0 view .LVU2511
+ 7386 007a 15F0010F 		tst	r5, #1
+ 7387 007e 09D0     		beq	.L310
+4336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7388              		.loc 1 4336 47 discriminator 1 view .LVU2512
+ 7389 0080 19F4807F 		tst	r9, #256
+ 7390 0084 06D0     		beq	.L310
+4338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7391              		.loc 1 4338 11 is_stmt 1 view .LVU2513
+ 7392 0086 0122     		movs	r2, #1
+ 7393 0088 1A62     		str	r2, [r3, #32]
+4340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7394              		.loc 1 4340 11 view .LVU2514
+4340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7395              		.loc 1 4340 16 is_stmt 0 view .LVU2515
+ 7396 008a D4F88C30 		ldr	r3, [r4, #140]
+4340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7397              		.loc 1 4340 28 view .LVU2516
+ 7398 008e 1343     		orrs	r3, r3, r2
+ 7399 0090 C4F88C30 		str	r3, [r4, #140]
+ 7400              	.L310:
+4344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7401              		.loc 1 4344 9 is_stmt 1 view .LVU2517
+4344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7402              		.loc 1 4344 12 is_stmt 0 view .LVU2518
+ 7403 0094 15F0020F 		tst	r5, #2
+ 7404 0098 0BD0     		beq	.L311
+4344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7405              		.loc 1 4344 47 discriminator 1 view .LVU2519
+ARM GAS  /tmp/cceWHrnJ.s 			page 268
+
+
+ 7406 009a 18F0010F 		tst	r8, #1
+ 7407 009e 08D0     		beq	.L311
+4346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7408              		.loc 1 4346 11 is_stmt 1 view .LVU2520
+ 7409 00a0 2368     		ldr	r3, [r4]
+ 7410 00a2 0222     		movs	r2, #2
+ 7411 00a4 1A62     		str	r2, [r3, #32]
+4348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7412              		.loc 1 4348 11 view .LVU2521
+4348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7413              		.loc 1 4348 16 is_stmt 0 view .LVU2522
+ 7414 00a6 D4F88C30 		ldr	r3, [r4, #140]
+4348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7415              		.loc 1 4348 28 view .LVU2523
+ 7416 00aa 43F00403 		orr	r3, r3, #4
+ 7417 00ae C4F88C30 		str	r3, [r4, #140]
+ 7418              	.L311:
+4352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7419              		.loc 1 4352 9 is_stmt 1 view .LVU2524
+4352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7420              		.loc 1 4352 12 is_stmt 0 view .LVU2525
+ 7421 00b2 15F0040F 		tst	r5, #4
+ 7422 00b6 BBD0     		beq	.L312
+4352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7423              		.loc 1 4352 47 discriminator 1 view .LVU2526
+ 7424 00b8 18F0010F 		tst	r8, #1
+ 7425 00bc B8D0     		beq	.L312
+4354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7426              		.loc 1 4354 11 is_stmt 1 view .LVU2527
+ 7427 00be 2368     		ldr	r3, [r4]
+ 7428 00c0 0422     		movs	r2, #4
+ 7429 00c2 1A62     		str	r2, [r3, #32]
+4356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7430              		.loc 1 4356 11 view .LVU2528
+4356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7431              		.loc 1 4356 16 is_stmt 0 view .LVU2529
+ 7432 00c4 D4F88C30 		ldr	r3, [r4, #140]
+4356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7433              		.loc 1 4356 28 view .LVU2530
+ 7434 00c8 43F00203 		orr	r3, r3, #2
+ 7435 00cc C4F88C30 		str	r3, [r4, #140]
+ 7436 00d0 AEE7     		b	.L312
+ 7437              	.L326:
+4369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 7438              		.loc 1 4369 11 is_stmt 1 view .LVU2531
+ 7439 00d2 2046     		mov	r0, r4
+ 7440 00d4 FFF7FEFF 		bl	HAL_UART_ErrorCallback
+ 7441              	.LVL671:
+4371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7442              		.loc 1 4371 11 view .LVU2532
+4371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7443              		.loc 1 4371 28 is_stmt 0 view .LVU2533
+ 7444 00d8 0023     		movs	r3, #0
+ 7445 00da C4F88C30 		str	r3, [r4, #140]
+ 7446 00de ABE7     		b	.L309
+ 7447              	.L314:
+4378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 269
+
+
+ 7448              		.loc 1 4378 9 is_stmt 1 discriminator 1 view .LVU2534
+ 7449              	.LBB846:
+4378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7450              		.loc 1 4378 9 discriminator 1 view .LVU2535
+4378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7451              		.loc 1 4378 9 discriminator 1 view .LVU2536
+4378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7452              		.loc 1 4378 9 discriminator 1 view .LVU2537
+ 7453 00e0 2268     		ldr	r2, [r4]
+ 7454              	.LVL672:
+ 7455              	.LBB847:
+ 7456              	.LBI847:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7457              		.loc 2 1151 31 discriminator 1 view .LVU2538
+ 7458              	.LBB848:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7459              		.loc 2 1153 5 discriminator 1 view .LVU2539
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7460              		.loc 2 1155 4 discriminator 1 view .LVU2540
+ 7461              		.syntax unified
+ 7462              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7463 00e2 52E8003F 		ldrex r3, [r2]
+ 7464              	@ 0 "" 2
+ 7465              	.LVL673:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7466              		.loc 2 1156 4 discriminator 1 view .LVU2541
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7467              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2542
+ 7468              		.thumb
+ 7469              		.syntax unified
+ 7470              	.LBE848:
+ 7471              	.LBE847:
+4378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7472              		.loc 1 4378 9 discriminator 1 view .LVU2543
+ 7473 00e6 23F48073 		bic	r3, r3, #256
+ 7474              	.LVL674:
+4378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7475              		.loc 1 4378 9 is_stmt 1 discriminator 1 view .LVU2544
+ 7476              	.LBB849:
+ 7477              	.LBI849:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7478              		.loc 2 1202 31 discriminator 1 view .LVU2545
+ 7479              	.LBB850:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7480              		.loc 2 1204 4 discriminator 1 view .LVU2546
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7481              		.loc 2 1206 4 discriminator 1 view .LVU2547
+ 7482              		.syntax unified
+ 7483              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7484 00ea 42E80031 		strex r1, r3, [r2]
+ 7485              	@ 0 "" 2
+ 7486              	.LVL675:
+ 7487              		.loc 2 1207 4 discriminator 1 view .LVU2548
+ 7488              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2549
+ 7489              		.thumb
+ 7490              		.syntax unified
+ 7491              	.LBE850:
+ARM GAS  /tmp/cceWHrnJ.s 			page 270
+
+
+ 7492              	.LBE849:
+4378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7493              		.loc 1 4378 9 discriminator 1 view .LVU2550
+ 7494 00ee 0029     		cmp	r1, #0
+ 7495 00f0 F6D1     		bne	.L314
+ 7496              	.LVL676:
+ 7497              	.L315:
+4378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7498              		.loc 1 4378 9 discriminator 1 view .LVU2551
+ 7499              	.LBE846:
+4378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7500              		.loc 1 4378 9 is_stmt 1 discriminator 1 view .LVU2552
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7501              		.loc 1 4382 9 discriminator 1 view .LVU2553
+ 7502              	.LBB851:
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7503              		.loc 1 4382 9 discriminator 1 view .LVU2554
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7504              		.loc 1 4382 9 discriminator 1 view .LVU2555
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7505              		.loc 1 4382 9 discriminator 1 view .LVU2556
+ 7506 00f2 2268     		ldr	r2, [r4]
+ 7507              	.LVL677:
+ 7508              	.LBB852:
+ 7509              	.LBI852:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7510              		.loc 2 1151 31 discriminator 1 view .LVU2557
+ 7511              	.LBB853:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7512              		.loc 2 1153 5 discriminator 1 view .LVU2558
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7513              		.loc 2 1155 4 discriminator 1 view .LVU2559
+ 7514 00f4 02F10803 		add	r3, r2, #8
+ 7515              	.LVL678:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7516              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU2560
+ 7517              		.syntax unified
+ 7518              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7519 00f8 53E8003F 		ldrex r3, [r3]
+ 7520              	@ 0 "" 2
+ 7521              	.LVL679:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7522              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU2561
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7523              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2562
+ 7524              		.thumb
+ 7525              		.syntax unified
+ 7526              	.LBE853:
+ 7527              	.LBE852:
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7528              		.loc 1 4382 9 discriminator 1 view .LVU2563
+ 7529 00fc 23F08053 		bic	r3, r3, #268435456
+ 7530 0100 23F00103 		bic	r3, r3, #1
+ 7531              	.LVL680:
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7532              		.loc 1 4382 9 is_stmt 1 discriminator 1 view .LVU2564
+ 7533              	.LBB854:
+ARM GAS  /tmp/cceWHrnJ.s 			page 271
+
+
+ 7534              	.LBI854:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7535              		.loc 2 1202 31 discriminator 1 view .LVU2565
+ 7536              	.LBB855:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7537              		.loc 2 1204 4 discriminator 1 view .LVU2566
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7538              		.loc 2 1206 4 discriminator 1 view .LVU2567
+ 7539 0104 0832     		adds	r2, r2, #8
+ 7540              	.LVL681:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7541              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU2568
+ 7542              		.syntax unified
+ 7543              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7544 0106 42E80031 		strex r1, r3, [r2]
+ 7545              	@ 0 "" 2
+ 7546              	.LVL682:
+ 7547              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU2569
+ 7548              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2570
+ 7549              		.thumb
+ 7550              		.syntax unified
+ 7551              	.LBE855:
+ 7552              	.LBE854:
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7553              		.loc 1 4382 9 discriminator 1 view .LVU2571
+ 7554 010a 0029     		cmp	r1, #0
+ 7555 010c F1D1     		bne	.L315
+ 7556              	.LBE851:
+4382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7557              		.loc 1 4382 9 is_stmt 1 discriminator 2 view .LVU2572
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7558              		.loc 1 4385 9 discriminator 2 view .LVU2573
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7559              		.loc 1 4385 24 is_stmt 0 discriminator 2 view .LVU2574
+ 7560 010e 2023     		movs	r3, #32
+ 7561              	.LVL683:
+4385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7562              		.loc 1 4385 24 discriminator 2 view .LVU2575
+ 7563 0110 C4F88830 		str	r3, [r4, #136]
+4388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7564              		.loc 1 4388 9 is_stmt 1 discriminator 2 view .LVU2576
+4388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7565              		.loc 1 4388 22 is_stmt 0 discriminator 2 view .LVU2577
+ 7566 0114 0023     		movs	r3, #0
+ 7567 0116 2367     		str	r3, [r4, #112]
+4392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7568              		.loc 1 4392 9 is_stmt 1 discriminator 2 view .LVU2578
+4392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7569              		.loc 1 4392 18 is_stmt 0 discriminator 2 view .LVU2579
+ 7570 0118 E36E     		ldr	r3, [r4, #108]
+4392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7571              		.loc 1 4392 12 discriminator 2 view .LVU2580
+ 7572 011a 012B     		cmp	r3, #1
+ 7573 011c 03D0     		beq	.L327
+4421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 7574              		.loc 1 4421 11 is_stmt 1 view .LVU2581
+ 7575 011e 2046     		mov	r0, r4
+ARM GAS  /tmp/cceWHrnJ.s 			page 272
+
+
+ 7576 0120 FFF7FEFF 		bl	HAL_UART_RxCpltCallback
+ 7577              	.LVL684:
+ 7578 0124 8DE7     		b	.L308
+ 7579              	.L327:
+4395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7580              		.loc 1 4395 11 view .LVU2582
+4395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7581              		.loc 1 4395 32 is_stmt 0 view .LVU2583
+ 7582 0126 0023     		movs	r3, #0
+ 7583 0128 E366     		str	r3, [r4, #108]
+ 7584              	.L317:
+4398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7585              		.loc 1 4398 11 is_stmt 1 discriminator 1 view .LVU2584
+ 7586              	.LBB856:
+4398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7587              		.loc 1 4398 11 discriminator 1 view .LVU2585
+4398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7588              		.loc 1 4398 11 discriminator 1 view .LVU2586
+4398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7589              		.loc 1 4398 11 discriminator 1 view .LVU2587
+ 7590 012a 2268     		ldr	r2, [r4]
+ 7591              	.LVL685:
+ 7592              	.LBB857:
+ 7593              	.LBI857:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7594              		.loc 2 1151 31 discriminator 1 view .LVU2588
+ 7595              	.LBB858:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7596              		.loc 2 1153 5 discriminator 1 view .LVU2589
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7597              		.loc 2 1155 4 discriminator 1 view .LVU2590
+ 7598              		.syntax unified
+ 7599              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7600 012c 52E8003F 		ldrex r3, [r2]
+ 7601              	@ 0 "" 2
+ 7602              	.LVL686:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7603              		.loc 2 1156 4 discriminator 1 view .LVU2591
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7604              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2592
+ 7605              		.thumb
+ 7606              		.syntax unified
+ 7607              	.LBE858:
+ 7608              	.LBE857:
+4398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7609              		.loc 1 4398 11 discriminator 1 view .LVU2593
+ 7610 0130 23F01003 		bic	r3, r3, #16
+ 7611              	.LVL687:
+4398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7612              		.loc 1 4398 11 is_stmt 1 discriminator 1 view .LVU2594
+ 7613              	.LBB859:
+ 7614              	.LBI859:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7615              		.loc 2 1202 31 discriminator 1 view .LVU2595
+ 7616              	.LBB860:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7617              		.loc 2 1204 4 discriminator 1 view .LVU2596
+ARM GAS  /tmp/cceWHrnJ.s 			page 273
+
+
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7618              		.loc 2 1206 4 discriminator 1 view .LVU2597
+ 7619              		.syntax unified
+ 7620              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7621 0134 42E80031 		strex r1, r3, [r2]
+ 7622              	@ 0 "" 2
+ 7623              	.LVL688:
+ 7624              		.loc 2 1207 4 discriminator 1 view .LVU2598
+ 7625              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2599
+ 7626              		.thumb
+ 7627              		.syntax unified
+ 7628              	.LBE860:
+ 7629              	.LBE859:
+4398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7630              		.loc 1 4398 11 discriminator 1 view .LVU2600
+ 7631 0138 0029     		cmp	r1, #0
+ 7632 013a F6D1     		bne	.L317
+ 7633              	.LBE856:
+4398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7634              		.loc 1 4398 11 is_stmt 1 discriminator 2 view .LVU2601
+4400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+ 7635              		.loc 1 4400 11 discriminator 2 view .LVU2602
+4400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+ 7636              		.loc 1 4400 15 is_stmt 0 discriminator 2 view .LVU2603
+ 7637 013c 2368     		ldr	r3, [r4]
+ 7638              	.LVL689:
+4400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+ 7639              		.loc 1 4400 15 discriminator 2 view .LVU2604
+ 7640 013e DA69     		ldr	r2, [r3, #28]
+4400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+ 7641              		.loc 1 4400 14 discriminator 2 view .LVU2605
+ 7642 0140 12F0100F 		tst	r2, #16
+ 7643 0144 01D0     		beq	.L318
+4403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           }
+ 7644              		.loc 1 4403 13 is_stmt 1 view .LVU2606
+ 7645 0146 1022     		movs	r2, #16
+ 7646 0148 1A62     		str	r2, [r3, #32]
+ 7647              	.L318:
+4410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 7648              		.loc 1 4410 11 view .LVU2607
+ 7649 014a B4F85C10 		ldrh	r1, [r4, #92]
+ 7650 014e 2046     		mov	r0, r4
+ 7651 0150 FFF7FEFF 		bl	HAL_UARTEx_RxEventCallback
+ 7652              	.LVL690:
+ 7653 0154 75E7     		b	.L308
+ 7654              	.LVL691:
+ 7655              	.L319:
+4431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+ 7656              		.loc 1 4431 5 view .LVU2608
+4431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+ 7657              		.loc 1 4431 17 is_stmt 0 view .LVU2609
+ 7658 0156 B4F85E30 		ldrh	r3, [r4, #94]
+ 7659 015a 9BB2     		uxth	r3, r3
+ 7660              	.LVL692:
+4432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7661              		.loc 1 4432 5 is_stmt 1 view .LVU2610
+4432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ARM GAS  /tmp/cceWHrnJ.s 			page 274
+
+
+ 7662              		.loc 1 4432 8 is_stmt 0 view .LVU2611
+ 7663 015c 002B     		cmp	r3, #0
+ 7664 015e 3FF461AF 		beq	.L306
+4432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7665              		.loc 1 4432 52 discriminator 1 view .LVU2612
+ 7666 0162 B4F86820 		ldrh	r2, [r4, #104]
+4432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7667              		.loc 1 4432 29 discriminator 1 view .LVU2613
+ 7668 0166 9A42     		cmp	r2, r3
+ 7669 0168 7FF65CAF 		bls	.L306
+ 7670              	.LVL693:
+ 7671              	.L322:
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7672              		.loc 1 4435 7 is_stmt 1 discriminator 1 view .LVU2614
+ 7673              	.LBB861:
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7674              		.loc 1 4435 7 discriminator 1 view .LVU2615
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7675              		.loc 1 4435 7 discriminator 1 view .LVU2616
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7676              		.loc 1 4435 7 discriminator 1 view .LVU2617
+ 7677 016c 2268     		ldr	r2, [r4]
+ 7678              	.LVL694:
+ 7679              	.LBB862:
+ 7680              	.LBI862:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7681              		.loc 2 1151 31 discriminator 1 view .LVU2618
+ 7682              	.LBB863:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7683              		.loc 2 1153 5 discriminator 1 view .LVU2619
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7684              		.loc 2 1155 4 discriminator 1 view .LVU2620
+ 7685 016e 02F10803 		add	r3, r2, #8
+ 7686              	.LVL695:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7687              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU2621
+ 7688              		.syntax unified
+ 7689              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7690 0172 53E8003F 		ldrex r3, [r3]
+ 7691              	@ 0 "" 2
+ 7692              	.LVL696:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7693              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU2622
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7694              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2623
+ 7695              		.thumb
+ 7696              		.syntax unified
+ 7697              	.LBE863:
+ 7698              	.LBE862:
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7699              		.loc 1 4435 7 discriminator 1 view .LVU2624
+ 7700 0176 23F08053 		bic	r3, r3, #268435456
+ 7701              	.LVL697:
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7702              		.loc 1 4435 7 is_stmt 1 discriminator 1 view .LVU2625
+ 7703              	.LBB864:
+ 7704              	.LBI864:
+ARM GAS  /tmp/cceWHrnJ.s 			page 275
+
+
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7705              		.loc 2 1202 31 discriminator 1 view .LVU2626
+ 7706              	.LBB865:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7707              		.loc 2 1204 4 discriminator 1 view .LVU2627
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7708              		.loc 2 1206 4 discriminator 1 view .LVU2628
+ 7709 017a 0832     		adds	r2, r2, #8
+ 7710              	.LVL698:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7711              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU2629
+ 7712              		.syntax unified
+ 7713              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7714 017c 42E80031 		strex r1, r3, [r2]
+ 7715              	@ 0 "" 2
+ 7716              	.LVL699:
+ 7717              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU2630
+ 7718              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2631
+ 7719              		.thumb
+ 7720              		.syntax unified
+ 7721              	.LBE865:
+ 7722              	.LBE864:
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7723              		.loc 1 4435 7 discriminator 1 view .LVU2632
+ 7724 0180 0029     		cmp	r1, #0
+ 7725 0182 F3D1     		bne	.L322
+ 7726              	.LBE861:
+4435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7727              		.loc 1 4435 7 is_stmt 1 discriminator 2 view .LVU2633
+4438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7728              		.loc 1 4438 7 discriminator 2 view .LVU2634
+4438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7729              		.loc 1 4438 20 is_stmt 0 discriminator 2 view .LVU2635
+ 7730 0184 054B     		ldr	r3, .L328
+ 7731              	.LVL700:
+4438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7732              		.loc 1 4438 20 discriminator 2 view .LVU2636
+ 7733 0186 2367     		str	r3, [r4, #112]
+ 7734              	.L323:
+4441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 7735              		.loc 1 4441 7 is_stmt 1 discriminator 1 view .LVU2637
+ 7736              	.LBB866:
+4441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 7737              		.loc 1 4441 7 discriminator 1 view .LVU2638
+4441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 7738              		.loc 1 4441 7 discriminator 1 view .LVU2639
+4441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 7739              		.loc 1 4441 7 discriminator 1 view .LVU2640
+ 7740 0188 2268     		ldr	r2, [r4]
+ 7741              	.LVL701:
+ 7742              	.LBB867:
+ 7743              	.LBI867:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7744              		.loc 2 1151 31 discriminator 1 view .LVU2641
+ 7745              	.LBB868:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7746              		.loc 2 1153 5 discriminator 1 view .LVU2642
+ARM GAS  /tmp/cceWHrnJ.s 			page 276
+
+
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7747              		.loc 2 1155 4 discriminator 1 view .LVU2643
+ 7748              		.syntax unified
+ 7749              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7750 018a 52E8003F 		ldrex r3, [r2]
+ 7751              	@ 0 "" 2
+ 7752              	.LVL702:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7753              		.loc 2 1156 4 discriminator 1 view .LVU2644
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7754              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2645
+ 7755              		.thumb
+ 7756              		.syntax unified
+ 7757              	.LBE868:
+ 7758              	.LBE867:
+4441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 7759              		.loc 1 4441 7 discriminator 1 view .LVU2646
+ 7760 018e 43F02003 		orr	r3, r3, #32
+ 7761              	.LVL703:
+4441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 7762              		.loc 1 4441 7 is_stmt 1 discriminator 1 view .LVU2647
+ 7763              	.LBB869:
+ 7764              	.LBI869:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7765              		.loc 2 1202 31 discriminator 1 view .LVU2648
+ 7766              	.LBB870:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7767              		.loc 2 1204 4 discriminator 1 view .LVU2649
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7768              		.loc 2 1206 4 discriminator 1 view .LVU2650
+ 7769              		.syntax unified
+ 7770              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7771 0192 42E80031 		strex r1, r3, [r2]
+ 7772              	@ 0 "" 2
+ 7773              	.LVL704:
+ 7774              		.loc 2 1207 4 discriminator 1 view .LVU2651
+ 7775              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2652
+ 7776              		.thumb
+ 7777              		.syntax unified
+ 7778              	.LBE870:
+ 7779              	.LBE869:
+4441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 7780              		.loc 1 4441 7 discriminator 1 view .LVU2653
+ 7781 0196 0029     		cmp	r1, #0
+ 7782 0198 F6D1     		bne	.L323
+ 7783 019a 43E7     		b	.L306
+ 7784              	.L329:
+ 7785              		.align	2
+ 7786              	.L328:
+ 7787 019c 00000000 		.word	UART_RxISR_8BIT
+ 7788              	.LBE866:
+ 7789              		.cfi_endproc
+ 7790              	.LFE397:
+ 7792              		.section	.text.UART_RxISR_16BIT_FIFOEN,"ax",%progbits
+ 7793              		.align	1
+ 7794              		.syntax unified
+ 7795              		.thumb
+ARM GAS  /tmp/cceWHrnJ.s 			page 277
+
+
+ 7796              		.thumb_func
+ 7798              	UART_RxISR_16BIT_FIFOEN:
+ 7799              	.LVL705:
+ 7800              	.LFB398:
+4450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+4452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+4453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @note   Function is called under interruption only, once
+4454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   *         interruptions have been enabled by HAL_UART_Receive_IT()
+4455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @param huart UART handle.
+4456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   * @retval None
+4457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   */
+4458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+4459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** {
+ 7801              		.loc 1 4459 1 is_stmt 1 view -0
+ 7802              		.cfi_startproc
+ 7803              		@ args = 0, pretend = 0, frame = 0
+ 7804              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7805              		.loc 1 4459 1 is_stmt 0 view .LVU2655
+ 7806 0000 2DE9F843 		push	{r3, r4, r5, r6, r7, r8, r9, lr}
+ 7807              	.LCFI28:
+ 7808              		.cfi_def_cfa_offset 32
+ 7809              		.cfi_offset 3, -32
+ 7810              		.cfi_offset 4, -28
+ 7811              		.cfi_offset 5, -24
+ 7812              		.cfi_offset 6, -20
+ 7813              		.cfi_offset 7, -16
+ 7814              		.cfi_offset 8, -12
+ 7815              		.cfi_offset 9, -8
+ 7816              		.cfi_offset 14, -4
+4460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t *tmp;
+ 7817              		.loc 1 4460 3 is_stmt 1 view .LVU2656
+4461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t  uhMask = huart->Mask;
+ 7818              		.loc 1 4461 3 view .LVU2657
+ 7819              		.loc 1 4461 13 is_stmt 0 view .LVU2658
+ 7820 0004 B0F86060 		ldrh	r6, [r0, #96]
+ 7821              	.LVL706:
+4462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t  uhdata;
+ 7822              		.loc 1 4462 3 is_stmt 1 view .LVU2659
+4463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t  nb_rx_data;
+ 7823              		.loc 1 4463 3 view .LVU2660
+4464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t  rxdatacount;
+ 7824              		.loc 1 4464 3 view .LVU2661
+4465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t  isrflags = READ_REG(huart->Instance->ISR);
+ 7825              		.loc 1 4465 3 view .LVU2662
+ 7826              		.loc 1 4465 24 is_stmt 0 view .LVU2663
+ 7827 0008 0368     		ldr	r3, [r0]
+ 7828              		.loc 1 4465 13 view .LVU2664
+ 7829 000a DD69     		ldr	r5, [r3, #28]
+ 7830              	.LVL707:
+4466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
+ 7831              		.loc 1 4466 3 is_stmt 1 view .LVU2665
+ 7832              		.loc 1 4466 13 is_stmt 0 view .LVU2666
+ 7833 000c D3F80090 		ldr	r9, [r3]
+ 7834              	.LVL708:
+4467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
+ 7835              		.loc 1 4467 3 is_stmt 1 view .LVU2667
+ARM GAS  /tmp/cceWHrnJ.s 			page 278
+
+
+ 7836              		.loc 1 4467 13 is_stmt 0 view .LVU2668
+ 7837 0010 D3F80880 		ldr	r8, [r3, #8]
+ 7838              	.LVL709:
+4468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Rx process is ongoing */
+4470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ 7839              		.loc 1 4470 3 is_stmt 1 view .LVU2669
+ 7840              		.loc 1 4470 12 is_stmt 0 view .LVU2670
+ 7841 0014 D0F88820 		ldr	r2, [r0, #136]
+ 7842              		.loc 1 4470 6 view .LVU2671
+ 7843 0018 222A     		cmp	r2, #34
+ 7844 001a 05D0     		beq	.L349
+4471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+4472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     nb_rx_data = huart->NbRxDataToProcess;
+4473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+4474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+4475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+4476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       tmp = (uint16_t *) huart->pRxBuffPtr ;
+4477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       *tmp = (uint16_t)(uhdata & uhMask);
+4478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pRxBuffPtr += 2U;
+4479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxXferCount--;
+4480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       isrflags = READ_REG(huart->Instance->ISR);
+4481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* If some non blocking errors occurred */
+4483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+4484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* UART parity error interrupt occurred -------------------------------------*/
+4486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+4487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+4489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode |= HAL_UART_ERROR_PE;
+4491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* UART frame error interrupt occurred --------------------------------------*/
+4494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+4495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+4497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode |= HAL_UART_ERROR_FE;
+4499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* UART noise error interrupt occurred --------------------------------------*/
+4502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+4503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+4505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode |= HAL_UART_ERROR_NE;
+4507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Call UART Error Call back function if need be ----------------------------*/
+4510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+4511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Non Blocking error : transfer could go on.
+4513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           Error is notified to user through user error callback */
+4514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+4515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call registered error callback*/
+ARM GAS  /tmp/cceWHrnJ.s 			page 279
+
+
+4516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCallback(huart);
+4517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+4518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call legacy weak error callback*/
+4519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           HAL_UART_ErrorCallback(huart);
+4520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+4521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode = HAL_UART_ERROR_NONE;
+4522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if (huart->RxXferCount == 0U)
+4526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+4527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+4529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+4531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            and RX FIFO Threshold interrupt */
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+4533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Rx process is completed, restore huart->RxState to Ready */
+4535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxState = HAL_UART_STATE_READY;
+4536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Clear RxISR function pointer */
+4538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxISR = NULL;
+4539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         /* Check current reception Mode :
+4541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****            If Reception till IDLE event has been selected : */
+4542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+4543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Set reception type to Standard */
+4545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+4546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Disable IDLE interrupt */
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+4549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+4551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+4552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             /* Clear IDLE Flag */
+4553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****             __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+4554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           }
+4555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+4556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call registered Rx Event callback*/
+4557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->RxEventCallback(huart, huart->RxXferSize);
+4558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+4559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call legacy weak Rx Event callback*/
+4560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+4561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+4562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         else
+4564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+4565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /* Standard reception API called */
+4566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+4567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call registered Rx complete callback*/
+4568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->RxCpltCallback(huart);
+4569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #else
+4570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           /*Call legacy weak Rx complete callback*/
+4571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           HAL_UART_RxCpltCallback(huart);
+4572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ARM GAS  /tmp/cceWHrnJ.s 			page 280
+
+
+4573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+4574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+4575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+4576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* When remaining number of bytes to receive is less than the RX FIFO
+4578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     threshold, next incoming frames are processed as if FIFO mode was
+4579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     disabled (i.e. one interrupt per received frame).
+4580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     */
+4581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     rxdatacount = huart->RxXferCount;
+4582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+4583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+4584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Disable the UART RXFT interrupt*/
+4585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+4586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Update the RxISR function pointer */
+4588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxISR = UART_RxISR_16BIT;
+4589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+4590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       /* Enable the UART Data Register Not Empty interrupt */
+4591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+4592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+4593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+4594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   else
+4595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+4596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* Clear RXNE interrupt flag */
+4597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ 7845              		.loc 1 4597 5 is_stmt 1 view .LVU2672
+ 7846 001c 9A69     		ldr	r2, [r3, #24]
+ 7847 001e 42F00802 		orr	r2, r2, #8
+ 7848 0022 9A61     		str	r2, [r3, #24]
+ 7849              	.LVL710:
+ 7850              	.L330:
+4598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+4599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 7851              		.loc 1 4599 1 is_stmt 0 view .LVU2673
+ 7852 0024 BDE8F883 		pop	{r3, r4, r5, r6, r7, r8, r9, pc}
+ 7853              	.LVL711:
+ 7854              	.L349:
+ 7855              		.loc 1 4599 1 view .LVU2674
+ 7856 0028 0446     		mov	r4, r0
+4472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+ 7857              		.loc 1 4472 5 is_stmt 1 view .LVU2675
+4472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+ 7858              		.loc 1 4472 16 is_stmt 0 view .LVU2676
+ 7859 002a B0F86870 		ldrh	r7, [r0, #104]
+ 7860              	.LVL712:
+4473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7861              		.loc 1 4473 5 is_stmt 1 view .LVU2677
+4473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7862              		.loc 1 4473 11 is_stmt 0 view .LVU2678
+ 7863 002e 08E0     		b	.L332
+ 7864              	.LVL713:
+ 7865              	.L336:
+4510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7866              		.loc 1 4510 9 is_stmt 1 view .LVU2679
+4510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7867              		.loc 1 4510 18 is_stmt 0 view .LVU2680
+ 7868 0030 D4F88C30 		ldr	r3, [r4, #140]
+ARM GAS  /tmp/cceWHrnJ.s 			page 281
+
+
+4510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7869              		.loc 1 4510 12 view .LVU2681
+ 7870 0034 002B     		cmp	r3, #0
+ 7871 0036 4BD1     		bne	.L350
+ 7872              	.L333:
+4525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 7873              		.loc 1 4525 7 is_stmt 1 view .LVU2682
+4525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 7874              		.loc 1 4525 16 is_stmt 0 view .LVU2683
+ 7875 0038 B4F85E30 		ldrh	r3, [r4, #94]
+ 7876 003c 9BB2     		uxth	r3, r3
+4525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 7877              		.loc 1 4525 10 view .LVU2684
+ 7878 003e 002B     		cmp	r3, #0
+ 7879 0040 4DD0     		beq	.L338
+ 7880              	.LVL714:
+ 7881              	.L332:
+4473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7882              		.loc 1 4473 30 is_stmt 1 view .LVU2685
+ 7883 0042 002F     		cmp	r7, #0
+ 7884 0044 00F08680 		beq	.L343
+4473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 7885              		.loc 1 4473 30 is_stmt 0 discriminator 1 view .LVU2686
+ 7886 0048 15F0200F 		tst	r5, #32
+ 7887 004c 00F08280 		beq	.L343
+4475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       tmp = (uint16_t *) huart->pRxBuffPtr ;
+ 7888              		.loc 1 4475 7 is_stmt 1 view .LVU2687
+4475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       tmp = (uint16_t *) huart->pRxBuffPtr ;
+ 7889              		.loc 1 4475 27 is_stmt 0 view .LVU2688
+ 7890 0050 2368     		ldr	r3, [r4]
+ 7891 0052 5B6A     		ldr	r3, [r3, #36]
+ 7892              	.LVL715:
+4476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       *tmp = (uint16_t)(uhdata & uhMask);
+ 7893              		.loc 1 4476 7 is_stmt 1 view .LVU2689
+4476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       *tmp = (uint16_t)(uhdata & uhMask);
+ 7894              		.loc 1 4476 11 is_stmt 0 view .LVU2690
+ 7895 0054 A26D     		ldr	r2, [r4, #88]
+ 7896              	.LVL716:
+4477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pRxBuffPtr += 2U;
+ 7897              		.loc 1 4477 7 is_stmt 1 view .LVU2691
+4477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pRxBuffPtr += 2U;
+ 7898              		.loc 1 4477 14 is_stmt 0 view .LVU2692
+ 7899 0056 3340     		ands	r3, r3, r6
+ 7900              	.LVL717:
+4477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->pRxBuffPtr += 2U;
+ 7901              		.loc 1 4477 12 view .LVU2693
+ 7902 0058 1380     		strh	r3, [r2]	@ movhi
+4478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxXferCount--;
+ 7903              		.loc 1 4478 7 is_stmt 1 view .LVU2694
+4478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxXferCount--;
+ 7904              		.loc 1 4478 12 is_stmt 0 view .LVU2695
+ 7905 005a A36D     		ldr	r3, [r4, #88]
+4478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       huart->RxXferCount--;
+ 7906              		.loc 1 4478 25 view .LVU2696
+ 7907 005c 0233     		adds	r3, r3, #2
+ 7908 005e A365     		str	r3, [r4, #88]
+4479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       isrflags = READ_REG(huart->Instance->ISR);
+ARM GAS  /tmp/cceWHrnJ.s 			page 282
+
+
+ 7909              		.loc 1 4479 7 is_stmt 1 view .LVU2697
+4479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       isrflags = READ_REG(huart->Instance->ISR);
+ 7910              		.loc 1 4479 12 is_stmt 0 view .LVU2698
+ 7911 0060 B4F85E30 		ldrh	r3, [r4, #94]
+ 7912 0064 9BB2     		uxth	r3, r3
+4479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       isrflags = READ_REG(huart->Instance->ISR);
+ 7913              		.loc 1 4479 25 view .LVU2699
+ 7914 0066 013B     		subs	r3, r3, #1
+ 7915 0068 9BB2     		uxth	r3, r3
+ 7916 006a A4F85E30 		strh	r3, [r4, #94]	@ movhi
+4480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7917              		.loc 1 4480 7 is_stmt 1 view .LVU2700
+4480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7918              		.loc 1 4480 18 is_stmt 0 view .LVU2701
+ 7919 006e 2368     		ldr	r3, [r4]
+4480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7920              		.loc 1 4480 16 view .LVU2702
+ 7921 0070 DD69     		ldr	r5, [r3, #28]
+ 7922              	.LVL718:
+4483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 7923              		.loc 1 4483 7 is_stmt 1 view .LVU2703
+4483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 7924              		.loc 1 4483 10 is_stmt 0 view .LVU2704
+ 7925 0072 15F0070F 		tst	r5, #7
+ 7926 0076 DFD0     		beq	.L333
+4486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7927              		.loc 1 4486 9 is_stmt 1 view .LVU2705
+4486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7928              		.loc 1 4486 12 is_stmt 0 view .LVU2706
+ 7929 0078 15F0010F 		tst	r5, #1
+ 7930 007c 09D0     		beq	.L334
+4486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7931              		.loc 1 4486 47 discriminator 1 view .LVU2707
+ 7932 007e 19F4807F 		tst	r9, #256
+ 7933 0082 06D0     		beq	.L334
+4488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7934              		.loc 1 4488 11 is_stmt 1 view .LVU2708
+ 7935 0084 0122     		movs	r2, #1
+ 7936              	.LVL719:
+4488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7937              		.loc 1 4488 11 is_stmt 0 view .LVU2709
+ 7938 0086 1A62     		str	r2, [r3, #32]
+4490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7939              		.loc 1 4490 11 is_stmt 1 view .LVU2710
+4490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7940              		.loc 1 4490 16 is_stmt 0 view .LVU2711
+ 7941 0088 D4F88C30 		ldr	r3, [r4, #140]
+4490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7942              		.loc 1 4490 28 view .LVU2712
+ 7943 008c 1343     		orrs	r3, r3, r2
+ 7944 008e C4F88C30 		str	r3, [r4, #140]
+ 7945              	.L334:
+4494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7946              		.loc 1 4494 9 is_stmt 1 view .LVU2713
+4494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7947              		.loc 1 4494 12 is_stmt 0 view .LVU2714
+ 7948 0092 15F0020F 		tst	r5, #2
+ARM GAS  /tmp/cceWHrnJ.s 			page 283
+
+
+ 7949 0096 0BD0     		beq	.L335
+4494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7950              		.loc 1 4494 47 discriminator 1 view .LVU2715
+ 7951 0098 18F0010F 		tst	r8, #1
+ 7952 009c 08D0     		beq	.L335
+4496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7953              		.loc 1 4496 11 is_stmt 1 view .LVU2716
+ 7954 009e 2368     		ldr	r3, [r4]
+ 7955 00a0 0222     		movs	r2, #2
+ 7956 00a2 1A62     		str	r2, [r3, #32]
+4498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7957              		.loc 1 4498 11 view .LVU2717
+4498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7958              		.loc 1 4498 16 is_stmt 0 view .LVU2718
+ 7959 00a4 D4F88C30 		ldr	r3, [r4, #140]
+4498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7960              		.loc 1 4498 28 view .LVU2719
+ 7961 00a8 43F00403 		orr	r3, r3, #4
+ 7962 00ac C4F88C30 		str	r3, [r4, #140]
+ 7963              	.L335:
+4502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7964              		.loc 1 4502 9 is_stmt 1 view .LVU2720
+4502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7965              		.loc 1 4502 12 is_stmt 0 view .LVU2721
+ 7966 00b0 15F0040F 		tst	r5, #4
+ 7967 00b4 BCD0     		beq	.L336
+4502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 7968              		.loc 1 4502 47 discriminator 1 view .LVU2722
+ 7969 00b6 18F0010F 		tst	r8, #1
+ 7970 00ba B9D0     		beq	.L336
+4504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7971              		.loc 1 4504 11 is_stmt 1 view .LVU2723
+ 7972 00bc 2368     		ldr	r3, [r4]
+ 7973 00be 0422     		movs	r2, #4
+ 7974 00c0 1A62     		str	r2, [r3, #32]
+4506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7975              		.loc 1 4506 11 view .LVU2724
+4506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7976              		.loc 1 4506 16 is_stmt 0 view .LVU2725
+ 7977 00c2 D4F88C30 		ldr	r3, [r4, #140]
+4506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7978              		.loc 1 4506 28 view .LVU2726
+ 7979 00c6 43F00203 		orr	r3, r3, #2
+ 7980 00ca C4F88C30 		str	r3, [r4, #140]
+ 7981 00ce AFE7     		b	.L336
+ 7982              	.L350:
+4519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 7983              		.loc 1 4519 11 is_stmt 1 view .LVU2727
+ 7984 00d0 2046     		mov	r0, r4
+ 7985 00d2 FFF7FEFF 		bl	HAL_UART_ErrorCallback
+ 7986              	.LVL720:
+4521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7987              		.loc 1 4521 11 view .LVU2728
+4521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 7988              		.loc 1 4521 28 is_stmt 0 view .LVU2729
+ 7989 00d6 0023     		movs	r3, #0
+ 7990 00d8 C4F88C30 		str	r3, [r4, #140]
+ARM GAS  /tmp/cceWHrnJ.s 			page 284
+
+
+ 7991 00dc ACE7     		b	.L333
+ 7992              	.L338:
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7993              		.loc 1 4528 9 is_stmt 1 discriminator 1 view .LVU2730
+ 7994              	.LBB871:
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7995              		.loc 1 4528 9 discriminator 1 view .LVU2731
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7996              		.loc 1 4528 9 discriminator 1 view .LVU2732
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 7997              		.loc 1 4528 9 discriminator 1 view .LVU2733
+ 7998 00de 2268     		ldr	r2, [r4]
+ 7999              	.LVL721:
+ 8000              	.LBB872:
+ 8001              	.LBI872:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8002              		.loc 2 1151 31 discriminator 1 view .LVU2734
+ 8003              	.LBB873:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8004              		.loc 2 1153 5 discriminator 1 view .LVU2735
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8005              		.loc 2 1155 4 discriminator 1 view .LVU2736
+ 8006              		.syntax unified
+ 8007              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8008 00e0 52E8003F 		ldrex r3, [r2]
+ 8009              	@ 0 "" 2
+ 8010              	.LVL722:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8011              		.loc 2 1156 4 discriminator 1 view .LVU2737
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8012              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2738
+ 8013              		.thumb
+ 8014              		.syntax unified
+ 8015              	.LBE873:
+ 8016              	.LBE872:
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8017              		.loc 1 4528 9 discriminator 1 view .LVU2739
+ 8018 00e4 23F48073 		bic	r3, r3, #256
+ 8019              	.LVL723:
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8020              		.loc 1 4528 9 is_stmt 1 discriminator 1 view .LVU2740
+ 8021              	.LBB874:
+ 8022              	.LBI874:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8023              		.loc 2 1202 31 discriminator 1 view .LVU2741
+ 8024              	.LBB875:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8025              		.loc 2 1204 4 discriminator 1 view .LVU2742
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8026              		.loc 2 1206 4 discriminator 1 view .LVU2743
+ 8027              		.syntax unified
+ 8028              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8029 00e8 42E80031 		strex r1, r3, [r2]
+ 8030              	@ 0 "" 2
+ 8031              	.LVL724:
+ 8032              		.loc 2 1207 4 discriminator 1 view .LVU2744
+ 8033              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2745
+ARM GAS  /tmp/cceWHrnJ.s 			page 285
+
+
+ 8034              		.thumb
+ 8035              		.syntax unified
+ 8036              	.LBE875:
+ 8037              	.LBE874:
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8038              		.loc 1 4528 9 discriminator 1 view .LVU2746
+ 8039 00ec 0029     		cmp	r1, #0
+ 8040 00ee F6D1     		bne	.L338
+ 8041              	.LVL725:
+ 8042              	.L339:
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8043              		.loc 1 4528 9 discriminator 1 view .LVU2747
+ 8044              	.LBE871:
+4528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8045              		.loc 1 4528 9 is_stmt 1 discriminator 1 view .LVU2748
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8046              		.loc 1 4532 9 discriminator 1 view .LVU2749
+ 8047              	.LBB876:
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8048              		.loc 1 4532 9 discriminator 1 view .LVU2750
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8049              		.loc 1 4532 9 discriminator 1 view .LVU2751
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8050              		.loc 1 4532 9 discriminator 1 view .LVU2752
+ 8051 00f0 2268     		ldr	r2, [r4]
+ 8052              	.LVL726:
+ 8053              	.LBB877:
+ 8054              	.LBI877:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8055              		.loc 2 1151 31 discriminator 1 view .LVU2753
+ 8056              	.LBB878:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8057              		.loc 2 1153 5 discriminator 1 view .LVU2754
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8058              		.loc 2 1155 4 discriminator 1 view .LVU2755
+ 8059 00f2 02F10803 		add	r3, r2, #8
+ 8060              	.LVL727:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8061              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU2756
+ 8062              		.syntax unified
+ 8063              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8064 00f6 53E8003F 		ldrex r3, [r3]
+ 8065              	@ 0 "" 2
+ 8066              	.LVL728:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8067              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU2757
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8068              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2758
+ 8069              		.thumb
+ 8070              		.syntax unified
+ 8071              	.LBE878:
+ 8072              	.LBE877:
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8073              		.loc 1 4532 9 discriminator 1 view .LVU2759
+ 8074 00fa 23F08053 		bic	r3, r3, #268435456
+ 8075 00fe 23F00103 		bic	r3, r3, #1
+ 8076              	.LVL729:
+ARM GAS  /tmp/cceWHrnJ.s 			page 286
+
+
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8077              		.loc 1 4532 9 is_stmt 1 discriminator 1 view .LVU2760
+ 8078              	.LBB879:
+ 8079              	.LBI879:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8080              		.loc 2 1202 31 discriminator 1 view .LVU2761
+ 8081              	.LBB880:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8082              		.loc 2 1204 4 discriminator 1 view .LVU2762
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8083              		.loc 2 1206 4 discriminator 1 view .LVU2763
+ 8084 0102 0832     		adds	r2, r2, #8
+ 8085              	.LVL730:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8086              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU2764
+ 8087              		.syntax unified
+ 8088              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8089 0104 42E80031 		strex r1, r3, [r2]
+ 8090              	@ 0 "" 2
+ 8091              	.LVL731:
+ 8092              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU2765
+ 8093              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2766
+ 8094              		.thumb
+ 8095              		.syntax unified
+ 8096              	.LBE880:
+ 8097              	.LBE879:
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8098              		.loc 1 4532 9 discriminator 1 view .LVU2767
+ 8099 0108 0029     		cmp	r1, #0
+ 8100 010a F1D1     		bne	.L339
+ 8101              	.LBE876:
+4532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8102              		.loc 1 4532 9 is_stmt 1 discriminator 2 view .LVU2768
+4535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8103              		.loc 1 4535 9 discriminator 2 view .LVU2769
+4535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8104              		.loc 1 4535 24 is_stmt 0 discriminator 2 view .LVU2770
+ 8105 010c 2023     		movs	r3, #32
+ 8106              	.LVL732:
+4535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8107              		.loc 1 4535 24 discriminator 2 view .LVU2771
+ 8108 010e C4F88830 		str	r3, [r4, #136]
+4538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8109              		.loc 1 4538 9 is_stmt 1 discriminator 2 view .LVU2772
+4538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8110              		.loc 1 4538 22 is_stmt 0 discriminator 2 view .LVU2773
+ 8111 0112 0023     		movs	r3, #0
+ 8112 0114 2367     		str	r3, [r4, #112]
+4542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 8113              		.loc 1 4542 9 is_stmt 1 discriminator 2 view .LVU2774
+4542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 8114              		.loc 1 4542 18 is_stmt 0 discriminator 2 view .LVU2775
+ 8115 0116 E36E     		ldr	r3, [r4, #108]
+4542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 8116              		.loc 1 4542 12 discriminator 2 view .LVU2776
+ 8117 0118 012B     		cmp	r3, #1
+ 8118 011a 03D0     		beq	.L351
+ARM GAS  /tmp/cceWHrnJ.s 			page 287
+
+
+4571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 8119              		.loc 1 4571 11 is_stmt 1 view .LVU2777
+ 8120 011c 2046     		mov	r0, r4
+ 8121 011e FFF7FEFF 		bl	HAL_UART_RxCpltCallback
+ 8122              	.LVL733:
+ 8123 0122 8EE7     		b	.L332
+ 8124              	.L351:
+4545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8125              		.loc 1 4545 11 view .LVU2778
+4545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8126              		.loc 1 4545 32 is_stmt 0 view .LVU2779
+ 8127 0124 0023     		movs	r3, #0
+ 8128 0126 E366     		str	r3, [r4, #108]
+ 8129              	.L341:
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8130              		.loc 1 4548 11 is_stmt 1 discriminator 1 view .LVU2780
+ 8131              	.LBB881:
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8132              		.loc 1 4548 11 discriminator 1 view .LVU2781
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8133              		.loc 1 4548 11 discriminator 1 view .LVU2782
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8134              		.loc 1 4548 11 discriminator 1 view .LVU2783
+ 8135 0128 2268     		ldr	r2, [r4]
+ 8136              	.LVL734:
+ 8137              	.LBB882:
+ 8138              	.LBI882:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8139              		.loc 2 1151 31 discriminator 1 view .LVU2784
+ 8140              	.LBB883:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8141              		.loc 2 1153 5 discriminator 1 view .LVU2785
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8142              		.loc 2 1155 4 discriminator 1 view .LVU2786
+ 8143              		.syntax unified
+ 8144              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8145 012a 52E8003F 		ldrex r3, [r2]
+ 8146              	@ 0 "" 2
+ 8147              	.LVL735:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8148              		.loc 2 1156 4 discriminator 1 view .LVU2787
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8149              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2788
+ 8150              		.thumb
+ 8151              		.syntax unified
+ 8152              	.LBE883:
+ 8153              	.LBE882:
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8154              		.loc 1 4548 11 discriminator 1 view .LVU2789
+ 8155 012e 23F01003 		bic	r3, r3, #16
+ 8156              	.LVL736:
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8157              		.loc 1 4548 11 is_stmt 1 discriminator 1 view .LVU2790
+ 8158              	.LBB884:
+ 8159              	.LBI884:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8160              		.loc 2 1202 31 discriminator 1 view .LVU2791
+ARM GAS  /tmp/cceWHrnJ.s 			page 288
+
+
+ 8161              	.LBB885:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8162              		.loc 2 1204 4 discriminator 1 view .LVU2792
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8163              		.loc 2 1206 4 discriminator 1 view .LVU2793
+ 8164              		.syntax unified
+ 8165              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8166 0132 42E80031 		strex r1, r3, [r2]
+ 8167              	@ 0 "" 2
+ 8168              	.LVL737:
+ 8169              		.loc 2 1207 4 discriminator 1 view .LVU2794
+ 8170              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2795
+ 8171              		.thumb
+ 8172              		.syntax unified
+ 8173              	.LBE885:
+ 8174              	.LBE884:
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8175              		.loc 1 4548 11 discriminator 1 view .LVU2796
+ 8176 0136 0029     		cmp	r1, #0
+ 8177 0138 F6D1     		bne	.L341
+ 8178              	.LBE881:
+4548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8179              		.loc 1 4548 11 is_stmt 1 discriminator 2 view .LVU2797
+4550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+ 8180              		.loc 1 4550 11 discriminator 2 view .LVU2798
+4550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+ 8181              		.loc 1 4550 15 is_stmt 0 discriminator 2 view .LVU2799
+ 8182 013a 2368     		ldr	r3, [r4]
+ 8183              	.LVL738:
+4550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+ 8184              		.loc 1 4550 15 discriminator 2 view .LVU2800
+ 8185 013c DA69     		ldr	r2, [r3, #28]
+4550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           {
+ 8186              		.loc 1 4550 14 discriminator 2 view .LVU2801
+ 8187 013e 12F0100F 		tst	r2, #16
+ 8188 0142 01D0     		beq	.L342
+4553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           }
+ 8189              		.loc 1 4553 13 is_stmt 1 view .LVU2802
+ 8190 0144 1022     		movs	r2, #16
+ 8191 0146 1A62     		str	r2, [r3, #32]
+ 8192              	.L342:
+4560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 8193              		.loc 1 4560 11 view .LVU2803
+ 8194 0148 B4F85C10 		ldrh	r1, [r4, #92]
+ 8195 014c 2046     		mov	r0, r4
+ 8196 014e FFF7FEFF 		bl	HAL_UARTEx_RxEventCallback
+ 8197              	.LVL739:
+ 8198 0152 76E7     		b	.L332
+ 8199              	.LVL740:
+ 8200              	.L343:
+4581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+ 8201              		.loc 1 4581 5 view .LVU2804
+4581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+ 8202              		.loc 1 4581 17 is_stmt 0 view .LVU2805
+ 8203 0154 B4F85E30 		ldrh	r3, [r4, #94]
+ 8204 0158 9BB2     		uxth	r3, r3
+ 8205              	.LVL741:
+ARM GAS  /tmp/cceWHrnJ.s 			page 289
+
+
+4582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8206              		.loc 1 4582 5 is_stmt 1 view .LVU2806
+4582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8207              		.loc 1 4582 8 is_stmt 0 view .LVU2807
+ 8208 015a 002B     		cmp	r3, #0
+ 8209 015c 3FF462AF 		beq	.L330
+4582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8210              		.loc 1 4582 52 discriminator 1 view .LVU2808
+ 8211 0160 B4F86820 		ldrh	r2, [r4, #104]
+4582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8212              		.loc 1 4582 29 discriminator 1 view .LVU2809
+ 8213 0164 9A42     		cmp	r2, r3
+ 8214 0166 7FF65DAF 		bls	.L330
+ 8215              	.LVL742:
+ 8216              	.L346:
+4585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8217              		.loc 1 4585 7 is_stmt 1 discriminator 1 view .LVU2810
+ 8218              	.LBB886:
+4585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8219              		.loc 1 4585 7 discriminator 1 view .LVU2811
+4585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8220              		.loc 1 4585 7 discriminator 1 view .LVU2812
+4585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8221              		.loc 1 4585 7 discriminator 1 view .LVU2813
+ 8222 016a 2268     		ldr	r2, [r4]
+ 8223              	.LVL743:
+ 8224              	.LBB887:
+ 8225              	.LBI887:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8226              		.loc 2 1151 31 discriminator 1 view .LVU2814
+ 8227              	.LBB888:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8228              		.loc 2 1153 5 discriminator 1 view .LVU2815
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8229              		.loc 2 1155 4 discriminator 1 view .LVU2816
+ 8230 016c 02F10803 		add	r3, r2, #8
+ 8231              	.LVL744:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8232              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU2817
+ 8233              		.syntax unified
+ 8234              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8235 0170 53E8003F 		ldrex r3, [r3]
+ 8236              	@ 0 "" 2
+ 8237              	.LVL745:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8238              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU2818
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8239              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2819
+ 8240              		.thumb
+ 8241              		.syntax unified
+ 8242              	.LBE888:
+ 8243              	.LBE887:
+4585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8244              		.loc 1 4585 7 discriminator 1 view .LVU2820
+ 8245 0174 23F08053 		bic	r3, r3, #268435456
+ 8246              	.LVL746:
+4585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 290
+
+
+ 8247              		.loc 1 4585 7 is_stmt 1 discriminator 1 view .LVU2821
+ 8248              	.LBB889:
+ 8249              	.LBI889:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8250              		.loc 2 1202 31 discriminator 1 view .LVU2822
+ 8251              	.LBB890:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8252              		.loc 2 1204 4 discriminator 1 view .LVU2823
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8253              		.loc 2 1206 4 discriminator 1 view .LVU2824
+ 8254 0178 0832     		adds	r2, r2, #8
+ 8255              	.LVL747:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8256              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU2825
+ 8257              		.syntax unified
+ 8258              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8259 017a 42E80031 		strex r1, r3, [r2]
+ 8260              	@ 0 "" 2
+ 8261              	.LVL748:
+ 8262              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU2826
+ 8263              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2827
+ 8264              		.thumb
+ 8265              		.syntax unified
+ 8266              	.LBE890:
+ 8267              	.LBE889:
+4585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8268              		.loc 1 4585 7 discriminator 1 view .LVU2828
+ 8269 017e 0029     		cmp	r1, #0
+ 8270 0180 F3D1     		bne	.L346
+ 8271              	.LBE886:
+4585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8272              		.loc 1 4585 7 is_stmt 1 discriminator 2 view .LVU2829
+4588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8273              		.loc 1 4588 7 discriminator 2 view .LVU2830
+4588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8274              		.loc 1 4588 20 is_stmt 0 discriminator 2 view .LVU2831
+ 8275 0182 064B     		ldr	r3, .L352
+ 8276              	.LVL749:
+4588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8277              		.loc 1 4588 20 discriminator 2 view .LVU2832
+ 8278 0184 2367     		str	r3, [r4, #112]
+ 8279              	.L347:
+4591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8280              		.loc 1 4591 7 is_stmt 1 discriminator 1 view .LVU2833
+ 8281              	.LBB891:
+4591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8282              		.loc 1 4591 7 discriminator 1 view .LVU2834
+4591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8283              		.loc 1 4591 7 discriminator 1 view .LVU2835
+4591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8284              		.loc 1 4591 7 discriminator 1 view .LVU2836
+ 8285 0186 2268     		ldr	r2, [r4]
+ 8286              	.LVL750:
+ 8287              	.LBB892:
+ 8288              	.LBI892:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8289              		.loc 2 1151 31 discriminator 1 view .LVU2837
+ARM GAS  /tmp/cceWHrnJ.s 			page 291
+
+
+ 8290              	.LBB893:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8291              		.loc 2 1153 5 discriminator 1 view .LVU2838
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8292              		.loc 2 1155 4 discriminator 1 view .LVU2839
+ 8293              		.syntax unified
+ 8294              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8295 0188 52E8003F 		ldrex r3, [r2]
+ 8296              	@ 0 "" 2
+ 8297              	.LVL751:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8298              		.loc 2 1156 4 discriminator 1 view .LVU2840
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8299              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2841
+ 8300              		.thumb
+ 8301              		.syntax unified
+ 8302              	.LBE893:
+ 8303              	.LBE892:
+4591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8304              		.loc 1 4591 7 discriminator 1 view .LVU2842
+ 8305 018c 43F02003 		orr	r3, r3, #32
+ 8306              	.LVL752:
+4591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8307              		.loc 1 4591 7 is_stmt 1 discriminator 1 view .LVU2843
+ 8308              	.LBB894:
+ 8309              	.LBI894:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8310              		.loc 2 1202 31 discriminator 1 view .LVU2844
+ 8311              	.LBB895:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8312              		.loc 2 1204 4 discriminator 1 view .LVU2845
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8313              		.loc 2 1206 4 discriminator 1 view .LVU2846
+ 8314              		.syntax unified
+ 8315              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8316 0190 42E80031 		strex r1, r3, [r2]
+ 8317              	@ 0 "" 2
+ 8318              	.LVL753:
+ 8319              		.loc 2 1207 4 discriminator 1 view .LVU2847
+ 8320              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2848
+ 8321              		.thumb
+ 8322              		.syntax unified
+ 8323              	.LBE895:
+ 8324              	.LBE894:
+4591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8325              		.loc 1 4591 7 discriminator 1 view .LVU2849
+ 8326 0194 0029     		cmp	r1, #0
+ 8327 0196 F6D1     		bne	.L347
+ 8328 0198 44E7     		b	.L330
+ 8329              	.L353:
+ 8330 019a 00BF     		.align	2
+ 8331              	.L352:
+ 8332 019c 00000000 		.word	UART_RxISR_16BIT
+ 8333              	.LBE891:
+ 8334              		.cfi_endproc
+ 8335              	.LFE398:
+ 8337              		.section	.text.UART_DMARxHalfCplt,"ax",%progbits
+ARM GAS  /tmp/cceWHrnJ.s 			page 292
+
+
+ 8338              		.align	1
+ 8339              		.syntax unified
+ 8340              		.thumb
+ 8341              		.thumb_func
+ 8343              	UART_DMARxHalfCplt:
+ 8344              	.LVL754:
+ 8345              	.LFB383:
+3718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 8346              		.loc 1 3718 1 is_stmt 1 view -0
+ 8347              		.cfi_startproc
+ 8348              		@ args = 0, pretend = 0, frame = 0
+ 8349              		@ frame_needed = 0, uses_anonymous_args = 0
+3718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 8350              		.loc 1 3718 1 is_stmt 0 view .LVU2851
+ 8351 0000 08B5     		push	{r3, lr}
+ 8352              	.LCFI29:
+ 8353              		.cfi_def_cfa_offset 8
+ 8354              		.cfi_offset 3, -8
+ 8355              		.cfi_offset 14, -4
+3719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8356              		.loc 1 3719 3 is_stmt 1 view .LVU2852
+3719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8357              		.loc 1 3719 23 is_stmt 0 view .LVU2853
+ 8358 0002 806A     		ldr	r0, [r0, #40]
+ 8359              	.LVL755:
+3723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8360              		.loc 1 3723 3 is_stmt 1 view .LVU2854
+3723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8361              		.loc 1 3723 12 is_stmt 0 view .LVU2855
+ 8362 0004 C36E     		ldr	r3, [r0, #108]
+3723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8363              		.loc 1 3723 6 view .LVU2856
+ 8364 0006 012B     		cmp	r3, #1
+ 8365 0008 02D0     		beq	.L358
+3741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 8366              		.loc 1 3741 5 is_stmt 1 view .LVU2857
+ 8367 000a FFF7FEFF 		bl	HAL_UART_RxHalfCpltCallback
+ 8368              	.LVL756:
+ 8369              	.L354:
+3744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8370              		.loc 1 3744 1 is_stmt 0 view .LVU2858
+ 8371 000e 08BD     		pop	{r3, pc}
+ 8372              	.LVL757:
+ 8373              	.L358:
+3730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 8374              		.loc 1 3730 5 is_stmt 1 view .LVU2859
+3730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 8375              		.loc 1 3730 44 is_stmt 0 view .LVU2860
+ 8376 0010 B0F85C10 		ldrh	r1, [r0, #92]
+3730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 8377              		.loc 1 3730 5 view .LVU2861
+ 8378 0014 4908     		lsrs	r1, r1, #1
+ 8379 0016 FFF7FEFF 		bl	HAL_UARTEx_RxEventCallback
+ 8380              	.LVL758:
+3730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 8381              		.loc 1 3730 5 view .LVU2862
+ 8382 001a F8E7     		b	.L354
+ARM GAS  /tmp/cceWHrnJ.s 			page 293
+
+
+ 8383              		.cfi_endproc
+ 8384              	.LFE383:
+ 8386              		.section	.text.UART_DMAReceiveCplt,"ax",%progbits
+ 8387              		.align	1
+ 8388              		.syntax unified
+ 8389              		.thumb
+ 8390              		.thumb_func
+ 8392              	UART_DMAReceiveCplt:
+ 8393              	.LVL759:
+ 8394              	.LFB382:
+3661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 8395              		.loc 1 3661 1 is_stmt 1 view -0
+ 8396              		.cfi_startproc
+ 8397              		@ args = 0, pretend = 0, frame = 0
+ 8398              		@ frame_needed = 0, uses_anonymous_args = 0
+3661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 8399              		.loc 1 3661 1 is_stmt 0 view .LVU2864
+ 8400 0000 08B5     		push	{r3, lr}
+ 8401              	.LCFI30:
+ 8402              		.cfi_def_cfa_offset 8
+ 8403              		.cfi_offset 3, -8
+ 8404              		.cfi_offset 14, -4
+ 8405 0002 0346     		mov	r3, r0
+3662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8406              		.loc 1 3662 3 is_stmt 1 view .LVU2865
+3662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8407              		.loc 1 3662 23 is_stmt 0 view .LVU2866
+ 8408 0004 806A     		ldr	r0, [r0, #40]
+ 8409              	.LVL760:
+3665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8410              		.loc 1 3665 3 is_stmt 1 view .LVU2867
+3665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8411              		.loc 1 3665 7 is_stmt 0 view .LVU2868
+ 8412 0006 1B68     		ldr	r3, [r3]
+ 8413              	.LVL761:
+3665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8414              		.loc 1 3665 7 view .LVU2869
+ 8415 0008 1B68     		ldr	r3, [r3]
+3665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8416              		.loc 1 3665 6 view .LVU2870
+ 8417 000a 13F0200F 		tst	r3, #32
+ 8418 000e 29D1     		bne	.L360
+3667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8419              		.loc 1 3667 5 is_stmt 1 view .LVU2871
+3667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8420              		.loc 1 3667 24 is_stmt 0 view .LVU2872
+ 8421 0010 0023     		movs	r3, #0
+ 8422 0012 A0F85E30 		strh	r3, [r0, #94]	@ movhi
+ 8423              	.L361:
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8424              		.loc 1 3670 5 is_stmt 1 discriminator 1 view .LVU2873
+ 8425              	.LBB896:
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8426              		.loc 1 3670 5 discriminator 1 view .LVU2874
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8427              		.loc 1 3670 5 discriminator 1 view .LVU2875
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ARM GAS  /tmp/cceWHrnJ.s 			page 294
+
+
+ 8428              		.loc 1 3670 5 discriminator 1 view .LVU2876
+ 8429 0016 0268     		ldr	r2, [r0]
+ 8430              	.LVL762:
+ 8431              	.LBB897:
+ 8432              	.LBI897:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8433              		.loc 2 1151 31 discriminator 1 view .LVU2877
+ 8434              	.LBB898:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8435              		.loc 2 1153 5 discriminator 1 view .LVU2878
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8436              		.loc 2 1155 4 discriminator 1 view .LVU2879
+ 8437              		.syntax unified
+ 8438              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8439 0018 52E8003F 		ldrex r3, [r2]
+ 8440              	@ 0 "" 2
+ 8441              	.LVL763:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8442              		.loc 2 1156 4 discriminator 1 view .LVU2880
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8443              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2881
+ 8444              		.thumb
+ 8445              		.syntax unified
+ 8446              	.LBE898:
+ 8447              	.LBE897:
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8448              		.loc 1 3670 5 discriminator 1 view .LVU2882
+ 8449 001c 23F48073 		bic	r3, r3, #256
+ 8450              	.LVL764:
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8451              		.loc 1 3670 5 is_stmt 1 discriminator 1 view .LVU2883
+ 8452              	.LBB899:
+ 8453              	.LBI899:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8454              		.loc 2 1202 31 discriminator 1 view .LVU2884
+ 8455              	.LBB900:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8456              		.loc 2 1204 4 discriminator 1 view .LVU2885
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8457              		.loc 2 1206 4 discriminator 1 view .LVU2886
+ 8458              		.syntax unified
+ 8459              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8460 0020 42E80031 		strex r1, r3, [r2]
+ 8461              	@ 0 "" 2
+ 8462              	.LVL765:
+ 8463              		.loc 2 1207 4 discriminator 1 view .LVU2887
+ 8464              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2888
+ 8465              		.thumb
+ 8466              		.syntax unified
+ 8467              	.LBE900:
+ 8468              	.LBE899:
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8469              		.loc 1 3670 5 discriminator 1 view .LVU2889
+ 8470 0024 0029     		cmp	r1, #0
+ 8471 0026 F6D1     		bne	.L361
+ 8472              	.LVL766:
+ 8473              	.L362:
+ARM GAS  /tmp/cceWHrnJ.s 			page 295
+
+
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8474              		.loc 1 3670 5 discriminator 1 view .LVU2890
+ 8475              	.LBE896:
+3670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8476              		.loc 1 3670 5 is_stmt 1 discriminator 1 view .LVU2891
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8477              		.loc 1 3671 5 discriminator 1 view .LVU2892
+ 8478              	.LBB901:
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8479              		.loc 1 3671 5 discriminator 1 view .LVU2893
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8480              		.loc 1 3671 5 discriminator 1 view .LVU2894
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8481              		.loc 1 3671 5 discriminator 1 view .LVU2895
+ 8482 0028 0268     		ldr	r2, [r0]
+ 8483              	.LVL767:
+ 8484              	.LBB902:
+ 8485              	.LBI902:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8486              		.loc 2 1151 31 discriminator 1 view .LVU2896
+ 8487              	.LBB903:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8488              		.loc 2 1153 5 discriminator 1 view .LVU2897
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8489              		.loc 2 1155 4 discriminator 1 view .LVU2898
+ 8490 002a 02F10803 		add	r3, r2, #8
+ 8491              	.LVL768:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8492              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU2899
+ 8493              		.syntax unified
+ 8494              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8495 002e 53E8003F 		ldrex r3, [r3]
+ 8496              	@ 0 "" 2
+ 8497              	.LVL769:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8498              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU2900
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8499              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2901
+ 8500              		.thumb
+ 8501              		.syntax unified
+ 8502              	.LBE903:
+ 8503              	.LBE902:
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8504              		.loc 1 3671 5 discriminator 1 view .LVU2902
+ 8505 0032 23F00103 		bic	r3, r3, #1
+ 8506              	.LVL770:
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8507              		.loc 1 3671 5 is_stmt 1 discriminator 1 view .LVU2903
+ 8508              	.LBB904:
+ 8509              	.LBI904:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8510              		.loc 2 1202 31 discriminator 1 view .LVU2904
+ 8511              	.LBB905:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8512              		.loc 2 1204 4 discriminator 1 view .LVU2905
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8513              		.loc 2 1206 4 discriminator 1 view .LVU2906
+ARM GAS  /tmp/cceWHrnJ.s 			page 296
+
+
+ 8514 0036 0832     		adds	r2, r2, #8
+ 8515              	.LVL771:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8516              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU2907
+ 8517              		.syntax unified
+ 8518              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8519 0038 42E80031 		strex r1, r3, [r2]
+ 8520              	@ 0 "" 2
+ 8521              	.LVL772:
+ 8522              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU2908
+ 8523              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2909
+ 8524              		.thumb
+ 8525              		.syntax unified
+ 8526              	.LBE905:
+ 8527              	.LBE904:
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8528              		.loc 1 3671 5 discriminator 1 view .LVU2910
+ 8529 003c 0029     		cmp	r1, #0
+ 8530 003e F3D1     		bne	.L362
+ 8531              	.LVL773:
+ 8532              	.L363:
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8533              		.loc 1 3671 5 discriminator 1 view .LVU2911
+ 8534              	.LBE901:
+3671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8535              		.loc 1 3671 5 is_stmt 1 discriminator 1 view .LVU2912
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8536              		.loc 1 3675 5 discriminator 1 view .LVU2913
+ 8537              	.LBB906:
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8538              		.loc 1 3675 5 discriminator 1 view .LVU2914
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8539              		.loc 1 3675 5 discriminator 1 view .LVU2915
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8540              		.loc 1 3675 5 discriminator 1 view .LVU2916
+ 8541 0040 0268     		ldr	r2, [r0]
+ 8542              	.LVL774:
+ 8543              	.LBB907:
+ 8544              	.LBI907:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8545              		.loc 2 1151 31 discriminator 1 view .LVU2917
+ 8546              	.LBB908:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8547              		.loc 2 1153 5 discriminator 1 view .LVU2918
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8548              		.loc 2 1155 4 discriminator 1 view .LVU2919
+ 8549 0042 02F10803 		add	r3, r2, #8
+ 8550              	.LVL775:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8551              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU2920
+ 8552              		.syntax unified
+ 8553              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8554 0046 53E8003F 		ldrex r3, [r3]
+ 8555              	@ 0 "" 2
+ 8556              	.LVL776:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8557              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU2921
+ARM GAS  /tmp/cceWHrnJ.s 			page 297
+
+
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8558              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2922
+ 8559              		.thumb
+ 8560              		.syntax unified
+ 8561              	.LBE908:
+ 8562              	.LBE907:
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8563              		.loc 1 3675 5 discriminator 1 view .LVU2923
+ 8564 004a 23F04003 		bic	r3, r3, #64
+ 8565              	.LVL777:
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8566              		.loc 1 3675 5 is_stmt 1 discriminator 1 view .LVU2924
+ 8567              	.LBB909:
+ 8568              	.LBI909:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8569              		.loc 2 1202 31 discriminator 1 view .LVU2925
+ 8570              	.LBB910:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8571              		.loc 2 1204 4 discriminator 1 view .LVU2926
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8572              		.loc 2 1206 4 discriminator 1 view .LVU2927
+ 8573 004e 0832     		adds	r2, r2, #8
+ 8574              	.LVL778:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8575              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU2928
+ 8576              		.syntax unified
+ 8577              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8578 0050 42E80031 		strex r1, r3, [r2]
+ 8579              	@ 0 "" 2
+ 8580              	.LVL779:
+ 8581              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU2929
+ 8582              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2930
+ 8583              		.thumb
+ 8584              		.syntax unified
+ 8585              	.LBE910:
+ 8586              	.LBE909:
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8587              		.loc 1 3675 5 discriminator 1 view .LVU2931
+ 8588 0054 0029     		cmp	r1, #0
+ 8589 0056 F3D1     		bne	.L363
+ 8590              	.LBE906:
+3675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8591              		.loc 1 3675 5 is_stmt 1 discriminator 2 view .LVU2932
+3678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8592              		.loc 1 3678 5 discriminator 2 view .LVU2933
+3678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8593              		.loc 1 3678 20 is_stmt 0 discriminator 2 view .LVU2934
+ 8594 0058 2023     		movs	r3, #32
+ 8595              	.LVL780:
+3678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8596              		.loc 1 3678 20 discriminator 2 view .LVU2935
+ 8597 005a C0F88830 		str	r3, [r0, #136]
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8598              		.loc 1 3681 5 is_stmt 1 discriminator 2 view .LVU2936
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8599              		.loc 1 3681 14 is_stmt 0 discriminator 2 view .LVU2937
+ 8600 005e C36E     		ldr	r3, [r0, #108]
+ARM GAS  /tmp/cceWHrnJ.s 			page 298
+
+
+3681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8601              		.loc 1 3681 8 discriminator 2 view .LVU2938
+ 8602 0060 012B     		cmp	r3, #1
+ 8603 0062 05D0     		beq	.L364
+ 8604              	.LVL781:
+ 8605              	.L360:
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8606              		.loc 1 3683 7 is_stmt 1 discriminator 2 view .LVU2939
+3689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8607              		.loc 1 3689 3 discriminator 2 view .LVU2940
+3689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8608              		.loc 1 3689 12 is_stmt 0 discriminator 2 view .LVU2941
+ 8609 0064 C36E     		ldr	r3, [r0, #108]
+3689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8610              		.loc 1 3689 6 discriminator 2 view .LVU2942
+ 8611 0066 012B     		cmp	r3, #1
+ 8612 0068 0CD0     		beq	.L368
+3707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 8613              		.loc 1 3707 5 is_stmt 1 view .LVU2943
+ 8614 006a FFF7FEFF 		bl	HAL_UART_RxCpltCallback
+ 8615              	.LVL782:
+ 8616              	.L359:
+3710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8617              		.loc 1 3710 1 is_stmt 0 view .LVU2944
+ 8618 006e 08BD     		pop	{r3, pc}
+ 8619              	.LVL783:
+ 8620              	.L364:
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8621              		.loc 1 3683 7 is_stmt 1 discriminator 1 view .LVU2945
+ 8622              	.LBB911:
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8623              		.loc 1 3683 7 discriminator 1 view .LVU2946
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8624              		.loc 1 3683 7 discriminator 1 view .LVU2947
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8625              		.loc 1 3683 7 discriminator 1 view .LVU2948
+ 8626 0070 0268     		ldr	r2, [r0]
+ 8627              	.LVL784:
+ 8628              	.LBB912:
+ 8629              	.LBI912:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8630              		.loc 2 1151 31 discriminator 1 view .LVU2949
+ 8631              	.LBB913:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8632              		.loc 2 1153 5 discriminator 1 view .LVU2950
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8633              		.loc 2 1155 4 discriminator 1 view .LVU2951
+ 8634              		.syntax unified
+ 8635              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8636 0072 52E8003F 		ldrex r3, [r2]
+ 8637              	@ 0 "" 2
+ 8638              	.LVL785:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8639              		.loc 2 1156 4 discriminator 1 view .LVU2952
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8640              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU2953
+ 8641              		.thumb
+ARM GAS  /tmp/cceWHrnJ.s 			page 299
+
+
+ 8642              		.syntax unified
+ 8643              	.LBE913:
+ 8644              	.LBE912:
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8645              		.loc 1 3683 7 discriminator 1 view .LVU2954
+ 8646 0076 23F01003 		bic	r3, r3, #16
+ 8647              	.LVL786:
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8648              		.loc 1 3683 7 is_stmt 1 discriminator 1 view .LVU2955
+ 8649              	.LBB914:
+ 8650              	.LBI914:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8651              		.loc 2 1202 31 discriminator 1 view .LVU2956
+ 8652              	.LBB915:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8653              		.loc 2 1204 4 discriminator 1 view .LVU2957
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8654              		.loc 2 1206 4 discriminator 1 view .LVU2958
+ 8655              		.syntax unified
+ 8656              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8657 007a 42E80031 		strex r1, r3, [r2]
+ 8658              	@ 0 "" 2
+ 8659              	.LVL787:
+ 8660              		.loc 2 1207 4 discriminator 1 view .LVU2959
+ 8661              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU2960
+ 8662              		.thumb
+ 8663              		.syntax unified
+ 8664              	.LBE915:
+ 8665              	.LBE914:
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8666              		.loc 1 3683 7 discriminator 1 view .LVU2961
+ 8667 007e 0029     		cmp	r1, #0
+ 8668 0080 F6D1     		bne	.L364
+ 8669 0082 EFE7     		b	.L360
+ 8670              	.LVL788:
+ 8671              	.L368:
+3683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8672              		.loc 1 3683 7 discriminator 1 view .LVU2962
+ 8673              	.LBE911:
+3696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 8674              		.loc 1 3696 5 is_stmt 1 view .LVU2963
+ 8675 0084 B0F85C10 		ldrh	r1, [r0, #92]
+ 8676 0088 FFF7FEFF 		bl	HAL_UARTEx_RxEventCallback
+ 8677              	.LVL789:
+3696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ 8678              		.loc 1 3696 5 is_stmt 0 view .LVU2964
+ 8679 008c EFE7     		b	.L359
+ 8680              		.cfi_endproc
+ 8681              	.LFE382:
+ 8683              		.section	.text.HAL_UART_ReceiverTimeout_Config,"ax",%progbits
+ 8684              		.align	1
+ 8685              		.global	HAL_UART_ReceiverTimeout_Config
+ 8686              		.syntax unified
+ 8687              		.thumb
+ 8688              		.thumb_func
+ 8690              	HAL_UART_ReceiverTimeout_Config:
+ 8691              	.LVL790:
+ARM GAS  /tmp/cceWHrnJ.s 			page 300
+
+
+ 8692              	.LFB361:
+2729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ 8693              		.loc 1 2729 1 is_stmt 1 view -0
+ 8694              		.cfi_startproc
+ 8695              		@ args = 0, pretend = 0, frame = 0
+ 8696              		@ frame_needed = 0, uses_anonymous_args = 0
+ 8697              		@ link register save eliminated.
+2730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8698              		.loc 1 2730 3 view .LVU2966
+2730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8699              		.loc 1 2730 9 is_stmt 0 view .LVU2967
+ 8700 0000 0268     		ldr	r2, [r0]
+2730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8701              		.loc 1 2730 6 view .LVU2968
+ 8702 0002 044B     		ldr	r3, .L371
+ 8703 0004 9A42     		cmp	r2, r3
+ 8704 0006 04D0     		beq	.L369
+2732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+ 8705              		.loc 1 2732 5 is_stmt 1 view .LVU2969
+2733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 8706              		.loc 1 2733 5 view .LVU2970
+ 8707 0008 5369     		ldr	r3, [r2, #20]
+ 8708 000a 03F07F43 		and	r3, r3, #-16777216
+ 8709 000e 1943     		orrs	r1, r1, r3
+ 8710              	.LVL791:
+2733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 8711              		.loc 1 2733 5 is_stmt 0 view .LVU2971
+ 8712 0010 5161     		str	r1, [r2, #20]
+ 8713              	.L369:
+2735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8714              		.loc 1 2735 1 view .LVU2972
+ 8715 0012 7047     		bx	lr
+ 8716              	.L372:
+ 8717              		.align	2
+ 8718              	.L371:
+ 8719 0014 00800040 		.word	1073774592
+ 8720              		.cfi_endproc
+ 8721              	.LFE361:
+ 8723              		.section	.text.HAL_UART_EnableReceiverTimeout,"ax",%progbits
+ 8724              		.align	1
+ 8725              		.global	HAL_UART_EnableReceiverTimeout
+ 8726              		.syntax unified
+ 8727              		.thumb
+ 8728              		.thumb_func
+ 8730              	HAL_UART_EnableReceiverTimeout:
+ 8731              	.LVL792:
+ 8732              	.LFB362:
+2744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ 8733              		.loc 1 2744 1 is_stmt 1 view -0
+ 8734              		.cfi_startproc
+ 8735              		@ args = 0, pretend = 0, frame = 0
+ 8736              		@ frame_needed = 0, uses_anonymous_args = 0
+ 8737              		@ link register save eliminated.
+2745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8738              		.loc 1 2745 3 view .LVU2974
+2745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8739              		.loc 1 2745 9 is_stmt 0 view .LVU2975
+ARM GAS  /tmp/cceWHrnJ.s 			page 301
+
+
+ 8740 0000 0368     		ldr	r3, [r0]
+2745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8741              		.loc 1 2745 6 view .LVU2976
+ 8742 0002 114A     		ldr	r2, .L378
+ 8743 0004 9342     		cmp	r3, r2
+ 8744 0006 19D0     		beq	.L375
+2747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8745              		.loc 1 2747 5 is_stmt 1 view .LVU2977
+2747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8746              		.loc 1 2747 14 is_stmt 0 view .LVU2978
+ 8747 0008 D0F88420 		ldr	r2, [r0, #132]
+2747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8748              		.loc 1 2747 8 view .LVU2979
+ 8749 000c 202A     		cmp	r2, #32
+ 8750 000e 17D1     		bne	.L376
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8751              		.loc 1 2750 7 is_stmt 1 view .LVU2980
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8752              		.loc 1 2750 7 view .LVU2981
+ 8753 0010 90F88020 		ldrb	r2, [r0, #128]	@ zero_extendqisi2
+ 8754 0014 012A     		cmp	r2, #1
+ 8755 0016 15D0     		beq	.L377
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8756              		.loc 1 2750 7 discriminator 2 view .LVU2982
+ 8757 0018 0122     		movs	r2, #1
+ 8758 001a 80F88020 		strb	r2, [r0, #128]
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8759              		.loc 1 2750 7 discriminator 2 view .LVU2983
+2752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8760              		.loc 1 2752 7 discriminator 2 view .LVU2984
+2752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8761              		.loc 1 2752 21 is_stmt 0 discriminator 2 view .LVU2985
+ 8762 001e 2422     		movs	r2, #36
+ 8763 0020 C0F88420 		str	r2, [r0, #132]
+2755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8764              		.loc 1 2755 7 is_stmt 1 discriminator 2 view .LVU2986
+ 8765 0024 5A68     		ldr	r2, [r3, #4]
+ 8766 0026 42F40002 		orr	r2, r2, #8388608
+ 8767 002a 5A60     		str	r2, [r3, #4]
+2757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8768              		.loc 1 2757 7 discriminator 2 view .LVU2987
+2757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8769              		.loc 1 2757 21 is_stmt 0 discriminator 2 view .LVU2988
+ 8770 002c 2023     		movs	r3, #32
+ 8771 002e C0F88430 		str	r3, [r0, #132]
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8772              		.loc 1 2760 7 is_stmt 1 discriminator 2 view .LVU2989
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8773              		.loc 1 2760 7 discriminator 2 view .LVU2990
+ 8774 0032 0023     		movs	r3, #0
+ 8775 0034 80F88030 		strb	r3, [r0, #128]
+2760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8776              		.loc 1 2760 7 discriminator 2 view .LVU2991
+2762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8777              		.loc 1 2762 7 discriminator 2 view .LVU2992
+2762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8778              		.loc 1 2762 14 is_stmt 0 discriminator 2 view .LVU2993
+ARM GAS  /tmp/cceWHrnJ.s 			page 302
+
+
+ 8779 0038 1846     		mov	r0, r3
+ 8780              	.LVL793:
+2762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8781              		.loc 1 2762 14 discriminator 2 view .LVU2994
+ 8782 003a 7047     		bx	lr
+ 8783              	.LVL794:
+ 8784              	.L375:
+2771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 8785              		.loc 1 2771 12 view .LVU2995
+ 8786 003c 0120     		movs	r0, #1
+ 8787              	.LVL795:
+2771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 8788              		.loc 1 2771 12 view .LVU2996
+ 8789 003e 7047     		bx	lr
+ 8790              	.LVL796:
+ 8791              	.L376:
+2766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8792              		.loc 1 2766 14 view .LVU2997
+ 8793 0040 0220     		movs	r0, #2
+ 8794              	.LVL797:
+2766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8795              		.loc 1 2766 14 view .LVU2998
+ 8796 0042 7047     		bx	lr
+ 8797              	.LVL798:
+ 8798              	.L377:
+2750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8799              		.loc 1 2750 7 view .LVU2999
+ 8800 0044 0220     		movs	r0, #2
+ 8801              	.LVL799:
+2773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8802              		.loc 1 2773 1 view .LVU3000
+ 8803 0046 7047     		bx	lr
+ 8804              	.L379:
+ 8805              		.align	2
+ 8806              	.L378:
+ 8807 0048 00800040 		.word	1073774592
+ 8808              		.cfi_endproc
+ 8809              	.LFE362:
+ 8811              		.section	.text.HAL_UART_DisableReceiverTimeout,"ax",%progbits
+ 8812              		.align	1
+ 8813              		.global	HAL_UART_DisableReceiverTimeout
+ 8814              		.syntax unified
+ 8815              		.thumb
+ 8816              		.thumb_func
+ 8818              	HAL_UART_DisableReceiverTimeout:
+ 8819              	.LVL800:
+ 8820              	.LFB363:
+2782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ 8821              		.loc 1 2782 1 is_stmt 1 view -0
+ 8822              		.cfi_startproc
+ 8823              		@ args = 0, pretend = 0, frame = 0
+ 8824              		@ frame_needed = 0, uses_anonymous_args = 0
+ 8825              		@ link register save eliminated.
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8826              		.loc 1 2783 3 view .LVU3002
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8827              		.loc 1 2783 9 is_stmt 0 view .LVU3003
+ARM GAS  /tmp/cceWHrnJ.s 			page 303
+
+
+ 8828 0000 0368     		ldr	r3, [r0]
+2783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 8829              		.loc 1 2783 6 view .LVU3004
+ 8830 0002 114A     		ldr	r2, .L385
+ 8831 0004 9342     		cmp	r3, r2
+ 8832 0006 19D0     		beq	.L382
+2785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8833              		.loc 1 2785 5 is_stmt 1 view .LVU3005
+2785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8834              		.loc 1 2785 14 is_stmt 0 view .LVU3006
+ 8835 0008 D0F88420 		ldr	r2, [r0, #132]
+2785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 8836              		.loc 1 2785 8 view .LVU3007
+ 8837 000c 202A     		cmp	r2, #32
+ 8838 000e 17D1     		bne	.L383
+2788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8839              		.loc 1 2788 7 is_stmt 1 view .LVU3008
+2788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8840              		.loc 1 2788 7 view .LVU3009
+ 8841 0010 90F88020 		ldrb	r2, [r0, #128]	@ zero_extendqisi2
+ 8842 0014 012A     		cmp	r2, #1
+ 8843 0016 15D0     		beq	.L384
+2788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8844              		.loc 1 2788 7 discriminator 2 view .LVU3010
+ 8845 0018 0122     		movs	r2, #1
+ 8846 001a 80F88020 		strb	r2, [r0, #128]
+2788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8847              		.loc 1 2788 7 discriminator 2 view .LVU3011
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8848              		.loc 1 2790 7 discriminator 2 view .LVU3012
+2790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8849              		.loc 1 2790 21 is_stmt 0 discriminator 2 view .LVU3013
+ 8850 001e 2422     		movs	r2, #36
+ 8851 0020 C0F88420 		str	r2, [r0, #132]
+2793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8852              		.loc 1 2793 7 is_stmt 1 discriminator 2 view .LVU3014
+ 8853 0024 5A68     		ldr	r2, [r3, #4]
+ 8854 0026 22F40002 		bic	r2, r2, #8388608
+ 8855 002a 5A60     		str	r2, [r3, #4]
+2795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8856              		.loc 1 2795 7 discriminator 2 view .LVU3015
+2795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8857              		.loc 1 2795 21 is_stmt 0 discriminator 2 view .LVU3016
+ 8858 002c 2023     		movs	r3, #32
+ 8859 002e C0F88430 		str	r3, [r0, #132]
+2798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8860              		.loc 1 2798 7 is_stmt 1 discriminator 2 view .LVU3017
+2798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8861              		.loc 1 2798 7 discriminator 2 view .LVU3018
+ 8862 0032 0023     		movs	r3, #0
+ 8863 0034 80F88030 		strb	r3, [r0, #128]
+2798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8864              		.loc 1 2798 7 discriminator 2 view .LVU3019
+2800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8865              		.loc 1 2800 7 discriminator 2 view .LVU3020
+2800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8866              		.loc 1 2800 14 is_stmt 0 discriminator 2 view .LVU3021
+ARM GAS  /tmp/cceWHrnJ.s 			page 304
+
+
+ 8867 0038 1846     		mov	r0, r3
+ 8868              	.LVL801:
+2800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8869              		.loc 1 2800 14 discriminator 2 view .LVU3022
+ 8870 003a 7047     		bx	lr
+ 8871              	.LVL802:
+ 8872              	.L382:
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 8873              		.loc 1 2809 12 view .LVU3023
+ 8874 003c 0120     		movs	r0, #1
+ 8875              	.LVL803:
+2809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 8876              		.loc 1 2809 12 view .LVU3024
+ 8877 003e 7047     		bx	lr
+ 8878              	.LVL804:
+ 8879              	.L383:
+2804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8880              		.loc 1 2804 14 view .LVU3025
+ 8881 0040 0220     		movs	r0, #2
+ 8882              	.LVL805:
+2804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 8883              		.loc 1 2804 14 view .LVU3026
+ 8884 0042 7047     		bx	lr
+ 8885              	.LVL806:
+ 8886              	.L384:
+2788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8887              		.loc 1 2788 7 view .LVU3027
+ 8888 0044 0220     		movs	r0, #2
+ 8889              	.LVL807:
+2811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8890              		.loc 1 2811 1 view .LVU3028
+ 8891 0046 7047     		bx	lr
+ 8892              	.L386:
+ 8893              		.align	2
+ 8894              	.L385:
+ 8895 0048 00800040 		.word	1073774592
+ 8896              		.cfi_endproc
+ 8897              	.LFE363:
+ 8899              		.section	.text.HAL_MultiProcessor_EnterMuteMode,"ax",%progbits
+ 8900              		.align	1
+ 8901              		.global	HAL_MultiProcessor_EnterMuteMode
+ 8902              		.syntax unified
+ 8903              		.thumb
+ 8904              		.thumb_func
+ 8906              	HAL_MultiProcessor_EnterMuteMode:
+ 8907              	.LVL808:
+ 8908              	.LFB366:
+2860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+ 8909              		.loc 1 2860 1 is_stmt 1 view -0
+ 8910              		.cfi_startproc
+ 8911              		@ args = 0, pretend = 0, frame = 0
+ 8912              		@ frame_needed = 0, uses_anonymous_args = 0
+ 8913              		@ link register save eliminated.
+2861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 8914              		.loc 1 2861 3 view .LVU3030
+ 8915 0000 0268     		ldr	r2, [r0]
+ 8916 0002 9369     		ldr	r3, [r2, #24]
+ARM GAS  /tmp/cceWHrnJ.s 			page 305
+
+
+ 8917 0004 43F00403 		orr	r3, r3, #4
+ 8918 0008 9361     		str	r3, [r2, #24]
+2862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8919              		.loc 1 2862 1 is_stmt 0 view .LVU3031
+ 8920 000a 7047     		bx	lr
+ 8921              		.cfi_endproc
+ 8922              	.LFE366:
+ 8924              		.section	.text.HAL_HalfDuplex_EnableTransmitter,"ax",%progbits
+ 8925              		.align	1
+ 8926              		.global	HAL_HalfDuplex_EnableTransmitter
+ 8927              		.syntax unified
+ 8928              		.thumb
+ 8929              		.thumb_func
+ 8931              	HAL_HalfDuplex_EnableTransmitter:
+ 8932              	.LVL809:
+ 8933              	.LFB367:
+2870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+ 8934              		.loc 1 2870 1 is_stmt 1 view -0
+ 8935              		.cfi_startproc
+ 8936              		@ args = 0, pretend = 0, frame = 0
+ 8937              		@ frame_needed = 0, uses_anonymous_args = 0
+ 8938              		@ link register save eliminated.
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 8939              		.loc 1 2871 3 view .LVU3033
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 8940              		.loc 1 2871 3 view .LVU3034
+ 8941 0000 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 8942 0004 012B     		cmp	r3, #1
+ 8943 0006 1FD0     		beq	.L392
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 8944              		.loc 1 2871 3 discriminator 2 view .LVU3035
+ 8945 0008 0123     		movs	r3, #1
+ 8946 000a 80F88030 		strb	r3, [r0, #128]
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 8947              		.loc 1 2871 3 discriminator 2 view .LVU3036
+2872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8948              		.loc 1 2872 3 discriminator 2 view .LVU3037
+2872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8949              		.loc 1 2872 17 is_stmt 0 discriminator 2 view .LVU3038
+ 8950 000e 2423     		movs	r3, #36
+ 8951 0010 C0F88430 		str	r3, [r0, #132]
+ 8952              	.L390:
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8953              		.loc 1 2875 3 is_stmt 1 discriminator 1 view .LVU3039
+ 8954              	.LBB916:
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8955              		.loc 1 2875 3 discriminator 1 view .LVU3040
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8956              		.loc 1 2875 3 discriminator 1 view .LVU3041
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8957              		.loc 1 2875 3 discriminator 1 view .LVU3042
+ 8958 0014 0268     		ldr	r2, [r0]
+ 8959              	.LVL810:
+ 8960              	.LBB917:
+ 8961              	.LBI917:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8962              		.loc 2 1151 31 discriminator 1 view .LVU3043
+ARM GAS  /tmp/cceWHrnJ.s 			page 306
+
+
+ 8963              	.LBB918:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8964              		.loc 2 1153 5 discriminator 1 view .LVU3044
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8965              		.loc 2 1155 4 discriminator 1 view .LVU3045
+ 8966              		.syntax unified
+ 8967              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8968 0016 52E8003F 		ldrex r3, [r2]
+ 8969              	@ 0 "" 2
+ 8970              	.LVL811:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8971              		.loc 2 1156 4 discriminator 1 view .LVU3046
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 8972              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU3047
+ 8973              		.thumb
+ 8974              		.syntax unified
+ 8975              	.LBE918:
+ 8976              	.LBE917:
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8977              		.loc 1 2875 3 discriminator 1 view .LVU3048
+ 8978 001a 23F00C03 		bic	r3, r3, #12
+ 8979              	.LVL812:
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8980              		.loc 1 2875 3 is_stmt 1 discriminator 1 view .LVU3049
+ 8981              	.LBB919:
+ 8982              	.LBI919:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 8983              		.loc 2 1202 31 discriminator 1 view .LVU3050
+ 8984              	.LBB920:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 8985              		.loc 2 1204 4 discriminator 1 view .LVU3051
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 8986              		.loc 2 1206 4 discriminator 1 view .LVU3052
+ 8987              		.syntax unified
+ 8988              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 8989 001e 42E80031 		strex r1, r3, [r2]
+ 8990              	@ 0 "" 2
+ 8991              	.LVL813:
+ 8992              		.loc 2 1207 4 discriminator 1 view .LVU3053
+ 8993              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU3054
+ 8994              		.thumb
+ 8995              		.syntax unified
+ 8996              	.LBE920:
+ 8997              	.LBE919:
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 8998              		.loc 1 2875 3 discriminator 1 view .LVU3055
+ 8999 0022 0029     		cmp	r1, #0
+ 9000 0024 F6D1     		bne	.L390
+ 9001              	.LVL814:
+ 9002              	.L391:
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9003              		.loc 1 2875 3 discriminator 1 view .LVU3056
+ 9004              	.LBE916:
+2875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9005              		.loc 1 2875 3 is_stmt 1 discriminator 1 view .LVU3057
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9006              		.loc 1 2878 3 discriminator 1 view .LVU3058
+ARM GAS  /tmp/cceWHrnJ.s 			page 307
+
+
+ 9007              	.LBB921:
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9008              		.loc 1 2878 3 discriminator 1 view .LVU3059
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9009              		.loc 1 2878 3 discriminator 1 view .LVU3060
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9010              		.loc 1 2878 3 discriminator 1 view .LVU3061
+ 9011 0026 0268     		ldr	r2, [r0]
+ 9012              	.LVL815:
+ 9013              	.LBB922:
+ 9014              	.LBI922:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 9015              		.loc 2 1151 31 discriminator 1 view .LVU3062
+ 9016              	.LBB923:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 9017              		.loc 2 1153 5 discriminator 1 view .LVU3063
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 9018              		.loc 2 1155 4 discriminator 1 view .LVU3064
+ 9019              		.syntax unified
+ 9020              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 9021 0028 52E8003F 		ldrex r3, [r2]
+ 9022              	@ 0 "" 2
+ 9023              	.LVL816:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 9024              		.loc 2 1156 4 discriminator 1 view .LVU3065
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 9025              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU3066
+ 9026              		.thumb
+ 9027              		.syntax unified
+ 9028              	.LBE923:
+ 9029              	.LBE922:
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9030              		.loc 1 2878 3 discriminator 1 view .LVU3067
+ 9031 002c 43F00803 		orr	r3, r3, #8
+ 9032              	.LVL817:
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9033              		.loc 1 2878 3 is_stmt 1 discriminator 1 view .LVU3068
+ 9034              	.LBB924:
+ 9035              	.LBI924:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 9036              		.loc 2 1202 31 discriminator 1 view .LVU3069
+ 9037              	.LBB925:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 9038              		.loc 2 1204 4 discriminator 1 view .LVU3070
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 9039              		.loc 2 1206 4 discriminator 1 view .LVU3071
+ 9040              		.syntax unified
+ 9041              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 9042 0030 42E80031 		strex r1, r3, [r2]
+ 9043              	@ 0 "" 2
+ 9044              	.LVL818:
+ 9045              		.loc 2 1207 4 discriminator 1 view .LVU3072
+ 9046              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU3073
+ 9047              		.thumb
+ 9048              		.syntax unified
+ 9049              	.LBE925:
+ 9050              	.LBE924:
+ARM GAS  /tmp/cceWHrnJ.s 			page 308
+
+
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9051              		.loc 1 2878 3 discriminator 1 view .LVU3074
+ 9052 0034 0029     		cmp	r1, #0
+ 9053 0036 F6D1     		bne	.L391
+ 9054              	.LBE921:
+2878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9055              		.loc 1 2878 3 is_stmt 1 discriminator 2 view .LVU3075
+2880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9056              		.loc 1 2880 3 discriminator 2 view .LVU3076
+2880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9057              		.loc 1 2880 17 is_stmt 0 discriminator 2 view .LVU3077
+ 9058 0038 2023     		movs	r3, #32
+ 9059              	.LVL819:
+2880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9060              		.loc 1 2880 17 discriminator 2 view .LVU3078
+ 9061 003a C0F88430 		str	r3, [r0, #132]
+2882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9062              		.loc 1 2882 3 is_stmt 1 discriminator 2 view .LVU3079
+2882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9063              		.loc 1 2882 3 discriminator 2 view .LVU3080
+ 9064 003e 0023     		movs	r3, #0
+ 9065 0040 80F88030 		strb	r3, [r0, #128]
+2882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9066              		.loc 1 2882 3 discriminator 2 view .LVU3081
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9067              		.loc 1 2884 3 discriminator 2 view .LVU3082
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9068              		.loc 1 2884 10 is_stmt 0 discriminator 2 view .LVU3083
+ 9069 0044 1846     		mov	r0, r3
+ 9070              	.LVL820:
+2884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9071              		.loc 1 2884 10 discriminator 2 view .LVU3084
+ 9072 0046 7047     		bx	lr
+ 9073              	.LVL821:
+ 9074              	.L392:
+2871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 9075              		.loc 1 2871 3 view .LVU3085
+ 9076 0048 0220     		movs	r0, #2
+ 9077              	.LVL822:
+2885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9078              		.loc 1 2885 1 view .LVU3086
+ 9079 004a 7047     		bx	lr
+ 9080              		.cfi_endproc
+ 9081              	.LFE367:
+ 9083              		.section	.text.HAL_HalfDuplex_EnableReceiver,"ax",%progbits
+ 9084              		.align	1
+ 9085              		.global	HAL_HalfDuplex_EnableReceiver
+ 9086              		.syntax unified
+ 9087              		.thumb
+ 9088              		.thumb_func
+ 9090              	HAL_HalfDuplex_EnableReceiver:
+ 9091              	.LVL823:
+ 9092              	.LFB368:
+2893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+ 9093              		.loc 1 2893 1 is_stmt 1 view -0
+ 9094              		.cfi_startproc
+ 9095              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/cceWHrnJ.s 			page 309
+
+
+ 9096              		@ frame_needed = 0, uses_anonymous_args = 0
+ 9097              		@ link register save eliminated.
+2894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 9098              		.loc 1 2894 3 view .LVU3088
+2894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 9099              		.loc 1 2894 3 view .LVU3089
+ 9100 0000 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 9101 0004 012B     		cmp	r3, #1
+ 9102 0006 1FD0     		beq	.L397
+2894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 9103              		.loc 1 2894 3 discriminator 2 view .LVU3090
+ 9104 0008 0123     		movs	r3, #1
+ 9105 000a 80F88030 		strb	r3, [r0, #128]
+2894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 9106              		.loc 1 2894 3 discriminator 2 view .LVU3091
+2895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9107              		.loc 1 2895 3 discriminator 2 view .LVU3092
+2895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9108              		.loc 1 2895 17 is_stmt 0 discriminator 2 view .LVU3093
+ 9109 000e 2423     		movs	r3, #36
+ 9110 0010 C0F88430 		str	r3, [r0, #132]
+ 9111              	.L395:
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9112              		.loc 1 2898 3 is_stmt 1 discriminator 1 view .LVU3094
+ 9113              	.LBB926:
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9114              		.loc 1 2898 3 discriminator 1 view .LVU3095
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9115              		.loc 1 2898 3 discriminator 1 view .LVU3096
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9116              		.loc 1 2898 3 discriminator 1 view .LVU3097
+ 9117 0014 0268     		ldr	r2, [r0]
+ 9118              	.LVL824:
+ 9119              	.LBB927:
+ 9120              	.LBI927:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 9121              		.loc 2 1151 31 discriminator 1 view .LVU3098
+ 9122              	.LBB928:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 9123              		.loc 2 1153 5 discriminator 1 view .LVU3099
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 9124              		.loc 2 1155 4 discriminator 1 view .LVU3100
+ 9125              		.syntax unified
+ 9126              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 9127 0016 52E8003F 		ldrex r3, [r2]
+ 9128              	@ 0 "" 2
+ 9129              	.LVL825:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 9130              		.loc 2 1156 4 discriminator 1 view .LVU3101
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 9131              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU3102
+ 9132              		.thumb
+ 9133              		.syntax unified
+ 9134              	.LBE928:
+ 9135              	.LBE927:
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9136              		.loc 1 2898 3 discriminator 1 view .LVU3103
+ARM GAS  /tmp/cceWHrnJ.s 			page 310
+
+
+ 9137 001a 23F00C03 		bic	r3, r3, #12
+ 9138              	.LVL826:
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9139              		.loc 1 2898 3 is_stmt 1 discriminator 1 view .LVU3104
+ 9140              	.LBB929:
+ 9141              	.LBI929:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 9142              		.loc 2 1202 31 discriminator 1 view .LVU3105
+ 9143              	.LBB930:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 9144              		.loc 2 1204 4 discriminator 1 view .LVU3106
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 9145              		.loc 2 1206 4 discriminator 1 view .LVU3107
+ 9146              		.syntax unified
+ 9147              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 9148 001e 42E80031 		strex r1, r3, [r2]
+ 9149              	@ 0 "" 2
+ 9150              	.LVL827:
+ 9151              		.loc 2 1207 4 discriminator 1 view .LVU3108
+ 9152              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU3109
+ 9153              		.thumb
+ 9154              		.syntax unified
+ 9155              	.LBE930:
+ 9156              	.LBE929:
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9157              		.loc 1 2898 3 discriminator 1 view .LVU3110
+ 9158 0022 0029     		cmp	r1, #0
+ 9159 0024 F6D1     		bne	.L395
+ 9160              	.LVL828:
+ 9161              	.L396:
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9162              		.loc 1 2898 3 discriminator 1 view .LVU3111
+ 9163              	.LBE926:
+2898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9164              		.loc 1 2898 3 is_stmt 1 discriminator 1 view .LVU3112
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9165              		.loc 1 2901 3 discriminator 1 view .LVU3113
+ 9166              	.LBB931:
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9167              		.loc 1 2901 3 discriminator 1 view .LVU3114
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9168              		.loc 1 2901 3 discriminator 1 view .LVU3115
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9169              		.loc 1 2901 3 discriminator 1 view .LVU3116
+ 9170 0026 0268     		ldr	r2, [r0]
+ 9171              	.LVL829:
+ 9172              	.LBB932:
+ 9173              	.LBI932:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 9174              		.loc 2 1151 31 discriminator 1 view .LVU3117
+ 9175              	.LBB933:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 9176              		.loc 2 1153 5 discriminator 1 view .LVU3118
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 9177              		.loc 2 1155 4 discriminator 1 view .LVU3119
+ 9178              		.syntax unified
+ 9179              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ARM GAS  /tmp/cceWHrnJ.s 			page 311
+
+
+ 9180 0028 52E8003F 		ldrex r3, [r2]
+ 9181              	@ 0 "" 2
+ 9182              	.LVL830:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 9183              		.loc 2 1156 4 discriminator 1 view .LVU3120
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 9184              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU3121
+ 9185              		.thumb
+ 9186              		.syntax unified
+ 9187              	.LBE933:
+ 9188              	.LBE932:
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9189              		.loc 1 2901 3 discriminator 1 view .LVU3122
+ 9190 002c 43F00403 		orr	r3, r3, #4
+ 9191              	.LVL831:
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9192              		.loc 1 2901 3 is_stmt 1 discriminator 1 view .LVU3123
+ 9193              	.LBB934:
+ 9194              	.LBI934:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 9195              		.loc 2 1202 31 discriminator 1 view .LVU3124
+ 9196              	.LBB935:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 9197              		.loc 2 1204 4 discriminator 1 view .LVU3125
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 9198              		.loc 2 1206 4 discriminator 1 view .LVU3126
+ 9199              		.syntax unified
+ 9200              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 9201 0030 42E80031 		strex r1, r3, [r2]
+ 9202              	@ 0 "" 2
+ 9203              	.LVL832:
+ 9204              		.loc 2 1207 4 discriminator 1 view .LVU3127
+ 9205              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU3128
+ 9206              		.thumb
+ 9207              		.syntax unified
+ 9208              	.LBE935:
+ 9209              	.LBE934:
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9210              		.loc 1 2901 3 discriminator 1 view .LVU3129
+ 9211 0034 0029     		cmp	r1, #0
+ 9212 0036 F6D1     		bne	.L396
+ 9213              	.LBE931:
+2901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9214              		.loc 1 2901 3 is_stmt 1 discriminator 2 view .LVU3130
+2903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9215              		.loc 1 2903 3 discriminator 2 view .LVU3131
+2903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9216              		.loc 1 2903 17 is_stmt 0 discriminator 2 view .LVU3132
+ 9217 0038 2023     		movs	r3, #32
+ 9218              	.LVL833:
+2903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9219              		.loc 1 2903 17 discriminator 2 view .LVU3133
+ 9220 003a C0F88430 		str	r3, [r0, #132]
+2905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9221              		.loc 1 2905 3 is_stmt 1 discriminator 2 view .LVU3134
+2905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9222              		.loc 1 2905 3 discriminator 2 view .LVU3135
+ARM GAS  /tmp/cceWHrnJ.s 			page 312
+
+
+ 9223 003e 0023     		movs	r3, #0
+ 9224 0040 80F88030 		strb	r3, [r0, #128]
+2905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9225              		.loc 1 2905 3 discriminator 2 view .LVU3136
+2907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9226              		.loc 1 2907 3 discriminator 2 view .LVU3137
+2907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9227              		.loc 1 2907 10 is_stmt 0 discriminator 2 view .LVU3138
+ 9228 0044 1846     		mov	r0, r3
+ 9229              	.LVL834:
+2907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9230              		.loc 1 2907 10 discriminator 2 view .LVU3139
+ 9231 0046 7047     		bx	lr
+ 9232              	.LVL835:
+ 9233              	.L397:
+2894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 9234              		.loc 1 2894 3 view .LVU3140
+ 9235 0048 0220     		movs	r0, #2
+ 9236              	.LVL836:
+2908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9237              		.loc 1 2908 1 view .LVU3141
+ 9238 004a 7047     		bx	lr
+ 9239              		.cfi_endproc
+ 9240              	.LFE368:
+ 9242              		.section	.text.HAL_LIN_SendBreak,"ax",%progbits
+ 9243              		.align	1
+ 9244              		.global	HAL_LIN_SendBreak
+ 9245              		.syntax unified
+ 9246              		.thumb
+ 9247              		.thumb_func
+ 9249              	HAL_LIN_SendBreak:
+ 9250              	.LVL837:
+ 9251              	.LFB369:
+2917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the parameters */
+ 9252              		.loc 1 2917 1 is_stmt 1 view -0
+ 9253              		.cfi_startproc
+ 9254              		@ args = 0, pretend = 0, frame = 0
+ 9255              		@ frame_needed = 0, uses_anonymous_args = 0
+ 9256              		@ link register save eliminated.
+2919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9257              		.loc 1 2919 3 view .LVU3143
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9258              		.loc 1 2921 3 view .LVU3144
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9259              		.loc 1 2921 3 view .LVU3145
+ 9260 0000 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 9261 0004 012B     		cmp	r3, #1
+ 9262 0006 12D0     		beq	.L400
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9263              		.loc 1 2921 3 discriminator 2 view .LVU3146
+ 9264 0008 0123     		movs	r3, #1
+ 9265 000a 80F88030 		strb	r3, [r0, #128]
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9266              		.loc 1 2921 3 discriminator 2 view .LVU3147
+2923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9267              		.loc 1 2923 3 discriminator 2 view .LVU3148
+2923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 313
+
+
+ 9268              		.loc 1 2923 17 is_stmt 0 discriminator 2 view .LVU3149
+ 9269 000e 2423     		movs	r3, #36
+ 9270 0010 C0F88430 		str	r3, [r0, #132]
+2926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9271              		.loc 1 2926 3 is_stmt 1 discriminator 2 view .LVU3150
+ 9272 0014 0268     		ldr	r2, [r0]
+ 9273 0016 9369     		ldr	r3, [r2, #24]
+ 9274 0018 43F00203 		orr	r3, r3, #2
+ 9275 001c 9361     		str	r3, [r2, #24]
+2928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9276              		.loc 1 2928 3 discriminator 2 view .LVU3151
+2928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9277              		.loc 1 2928 17 is_stmt 0 discriminator 2 view .LVU3152
+ 9278 001e 2023     		movs	r3, #32
+ 9279 0020 C0F88430 		str	r3, [r0, #132]
+2930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9280              		.loc 1 2930 3 is_stmt 1 discriminator 2 view .LVU3153
+2930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9281              		.loc 1 2930 3 discriminator 2 view .LVU3154
+ 9282 0024 0023     		movs	r3, #0
+ 9283 0026 80F88030 		strb	r3, [r0, #128]
+2930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9284              		.loc 1 2930 3 discriminator 2 view .LVU3155
+2932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9285              		.loc 1 2932 3 discriminator 2 view .LVU3156
+2932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9286              		.loc 1 2932 10 is_stmt 0 discriminator 2 view .LVU3157
+ 9287 002a 1846     		mov	r0, r3
+ 9288              	.LVL838:
+2932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9289              		.loc 1 2932 10 discriminator 2 view .LVU3158
+ 9290 002c 7047     		bx	lr
+ 9291              	.LVL839:
+ 9292              	.L400:
+2921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9293              		.loc 1 2921 3 view .LVU3159
+ 9294 002e 0220     		movs	r0, #2
+ 9295              	.LVL840:
+2933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9296              		.loc 1 2933 1 view .LVU3160
+ 9297 0030 7047     		bx	lr
+ 9298              		.cfi_endproc
+ 9299              	.LFE369:
+ 9301              		.section	.text.HAL_UART_GetState,"ax",%progbits
+ 9302              		.align	1
+ 9303              		.global	HAL_UART_GetState
+ 9304              		.syntax unified
+ 9305              		.thumb
+ 9306              		.thumb_func
+ 9308              	HAL_UART_GetState:
+ 9309              	.LVL841:
+ 9310              	.LFB370:
+2962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t temp1;
+ 9311              		.loc 1 2962 1 is_stmt 1 view -0
+ 9312              		.cfi_startproc
+ 9313              		@ args = 0, pretend = 0, frame = 0
+ 9314              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cceWHrnJ.s 			page 314
+
+
+ 9315              		@ link register save eliminated.
+2963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t temp2;
+ 9316              		.loc 1 2963 3 view .LVU3162
+2964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   temp1 = huart->gState;
+ 9317              		.loc 1 2964 3 view .LVU3163
+2965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   temp2 = huart->RxState;
+ 9318              		.loc 1 2965 3 view .LVU3164
+2965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   temp2 = huart->RxState;
+ 9319              		.loc 1 2965 9 is_stmt 0 view .LVU3165
+ 9320 0000 D0F88420 		ldr	r2, [r0, #132]
+ 9321              	.LVL842:
+2966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9322              		.loc 1 2966 3 is_stmt 1 view .LVU3166
+2966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9323              		.loc 1 2966 9 is_stmt 0 view .LVU3167
+ 9324 0004 D0F88800 		ldr	r0, [r0, #136]
+ 9325              	.LVL843:
+2968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9326              		.loc 1 2968 3 is_stmt 1 view .LVU3168
+2969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9327              		.loc 1 2969 1 is_stmt 0 view .LVU3169
+ 9328 0008 1043     		orrs	r0, r0, r2
+ 9329              	.LVL844:
+2969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9330              		.loc 1 2969 1 view .LVU3170
+ 9331 000a 7047     		bx	lr
+ 9332              		.cfi_endproc
+ 9333              	.LFE370:
+ 9335              		.section	.text.HAL_UART_GetError,"ax",%progbits
+ 9336              		.align	1
+ 9337              		.global	HAL_UART_GetError
+ 9338              		.syntax unified
+ 9339              		.thumb
+ 9340              		.thumb_func
+ 9342              	HAL_UART_GetError:
+ 9343              	.LVL845:
+ 9344              	.LFB371:
+2978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   return huart->ErrorCode;
+ 9345              		.loc 1 2978 1 is_stmt 1 view -0
+ 9346              		.cfi_startproc
+ 9347              		@ args = 0, pretend = 0, frame = 0
+ 9348              		@ frame_needed = 0, uses_anonymous_args = 0
+ 9349              		@ link register save eliminated.
+2979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9350              		.loc 1 2979 3 view .LVU3172
+2979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9351              		.loc 1 2979 15 is_stmt 0 view .LVU3173
+ 9352 0000 D0F88C00 		ldr	r0, [r0, #140]
+ 9353              	.LVL846:
+2980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** /**
+ 9354              		.loc 1 2980 1 view .LVU3174
+ 9355 0004 7047     		bx	lr
+ 9356              		.cfi_endproc
+ 9357              	.LFE371:
+ 9359              		.global	__aeabi_uldivmod
+ 9360              		.section	.text.UART_SetConfig,"ax",%progbits
+ 9361              		.align	1
+ARM GAS  /tmp/cceWHrnJ.s 			page 315
+
+
+ 9362              		.global	UART_SetConfig
+ 9363              		.syntax unified
+ 9364              		.thumb
+ 9365              		.thumb_func
+ 9367              	UART_SetConfig:
+ 9368              	.LVL847:
+ 9369              	.LFB372:
+3024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t tmpreg;
+ 9370              		.loc 1 3024 1 is_stmt 1 view -0
+ 9371              		.cfi_startproc
+ 9372              		@ args = 0, pretend = 0, frame = 0
+ 9373              		@ frame_needed = 0, uses_anonymous_args = 0
+3024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t tmpreg;
+ 9374              		.loc 1 3024 1 is_stmt 0 view .LVU3176
+ 9375 0000 70B5     		push	{r4, r5, r6, lr}
+ 9376              	.LCFI31:
+ 9377              		.cfi_def_cfa_offset 16
+ 9378              		.cfi_offset 4, -16
+ 9379              		.cfi_offset 5, -12
+ 9380              		.cfi_offset 6, -8
+ 9381              		.cfi_offset 14, -4
+ 9382 0002 0446     		mov	r4, r0
+3025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t brrtemp;
+ 9383              		.loc 1 3025 3 is_stmt 1 view .LVU3177
+3026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   UART_ClockSourceTypeDef clocksource;
+ 9384              		.loc 1 3026 3 view .LVU3178
+3027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t usartdiv;
+ 9385              		.loc 1 3027 3 view .LVU3179
+3028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   HAL_StatusTypeDef ret               = HAL_OK;
+ 9386              		.loc 1 3028 3 view .LVU3180
+3029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t lpuart_ker_ck_pres;
+ 9387              		.loc 1 3029 3 view .LVU3181
+ 9388              	.LVL848:
+3030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t pclk;
+ 9389              		.loc 1 3030 3 view .LVU3182
+3031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9390              		.loc 1 3031 3 view .LVU3183
+3034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ 9391              		.loc 1 3034 3 view .LVU3184
+3035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   if (UART_INSTANCE_LOWPOWER(huart))
+ 9392              		.loc 1 3035 3 view .LVU3185
+3036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 9393              		.loc 1 3036 3 view .LVU3186
+3036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 9394              		.loc 1 3036 7 is_stmt 0 view .LVU3187
+ 9395 0004 0168     		ldr	r1, [r0]
+3042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+ 9396              		.loc 1 3042 5 is_stmt 1 view .LVU3188
+3043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 9397              		.loc 1 3043 5 view .LVU3189
+3046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_MODE(huart->Init.Mode));
+ 9398              		.loc 1 3046 3 view .LVU3190
+3047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ 9399              		.loc 1 3047 3 view .LVU3191
+3048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+ 9400              		.loc 1 3048 3 view .LVU3192
+3049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
+ARM GAS  /tmp/cceWHrnJ.s 			page 316
+
+
+ 9401              		.loc 1 3049 3 view .LVU3193
+3050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9402              		.loc 1 3050 3 view .LVU3194
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 9403              		.loc 1 3059 3 view .LVU3195
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 9404              		.loc 1 3059 33 is_stmt 0 view .LVU3196
+ 9405 0006 8368     		ldr	r3, [r0, #8]
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 9406              		.loc 1 3059 58 view .LVU3197
+ 9407 0008 0269     		ldr	r2, [r0, #16]
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 9408              		.loc 1 3059 45 view .LVU3198
+ 9409 000a 1343     		orrs	r3, r3, r2
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 9410              		.loc 1 3059 79 view .LVU3199
+ 9411 000c 4269     		ldr	r2, [r0, #20]
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 9412              		.loc 1 3059 66 view .LVU3200
+ 9413 000e 1343     		orrs	r3, r3, r2
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 9414              		.loc 1 3059 98 view .LVU3201
+ 9415 0010 C269     		ldr	r2, [r0, #28]
+3059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 9416              		.loc 1 3059 10 view .LVU3202
+ 9417 0012 1343     		orrs	r3, r3, r2
+ 9418              	.LVL849:
+3060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9419              		.loc 1 3060 3 is_stmt 1 view .LVU3203
+ 9420 0014 0868     		ldr	r0, [r1]
+ 9421              	.LVL850:
+3060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9422              		.loc 1 3060 3 is_stmt 0 view .LVU3204
+ 9423 0016 8B4A     		ldr	r2, .L483
+ 9424 0018 0240     		ands	r2, r2, r0
+ 9425 001a 1A43     		orrs	r2, r2, r3
+ 9426 001c 0A60     		str	r2, [r1]
+3065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9427              		.loc 1 3065 3 is_stmt 1 view .LVU3205
+ 9428 001e 2268     		ldr	r2, [r4]
+ 9429 0020 5368     		ldr	r3, [r2, #4]
+ 9430              	.LVL851:
+3065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9431              		.loc 1 3065 3 is_stmt 0 view .LVU3206
+ 9432 0022 23F44053 		bic	r3, r3, #12288
+ 9433 0026 E168     		ldr	r1, [r4, #12]
+ 9434 0028 0B43     		orrs	r3, r3, r1
+ 9435 002a 5360     		str	r3, [r2, #4]
+3073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9436              		.loc 1 3073 3 is_stmt 1 view .LVU3207
+3073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9437              		.loc 1 3073 10 is_stmt 0 view .LVU3208
+ 9438 002c A169     		ldr	r1, [r4, #24]
+ 9439              	.LVL852:
+3075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 9440              		.loc 1 3075 3 is_stmt 1 view .LVU3209
+3075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ARM GAS  /tmp/cceWHrnJ.s 			page 317
+
+
+ 9441              		.loc 1 3075 9 is_stmt 0 view .LVU3210
+ 9442 002e 2268     		ldr	r2, [r4]
+3075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 9443              		.loc 1 3075 6 view .LVU3211
+ 9444 0030 854B     		ldr	r3, .L483+4
+ 9445 0032 9A42     		cmp	r2, r3
+ 9446 0034 01D0     		beq	.L404
+3077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 9447              		.loc 1 3077 5 is_stmt 1 view .LVU3212
+3077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 9448              		.loc 1 3077 26 is_stmt 0 view .LVU3213
+ 9449 0036 236A     		ldr	r3, [r4, #32]
+3077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 9450              		.loc 1 3077 12 view .LVU3214
+ 9451 0038 1943     		orrs	r1, r1, r3
+ 9452              	.LVL853:
+ 9453              	.L404:
+3079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9454              		.loc 1 3079 3 is_stmt 1 view .LVU3215
+ 9455 003a 9368     		ldr	r3, [r2, #8]
+ 9456 003c 23F06E43 		bic	r3, r3, #-301989888
+ 9457 0040 23F43063 		bic	r3, r3, #2816
+ 9458 0044 0B43     		orrs	r3, r3, r1
+ 9459 0046 9360     		str	r3, [r2, #8]
+3084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9460              		.loc 1 3084 3 view .LVU3216
+ 9461 0048 2268     		ldr	r2, [r4]
+ 9462 004a D36A     		ldr	r3, [r2, #44]
+ 9463 004c 23F00F03 		bic	r3, r3, #15
+ 9464 0050 616A     		ldr	r1, [r4, #36]
+ 9465              	.LVL854:
+3084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9466              		.loc 1 3084 3 is_stmt 0 view .LVU3217
+ 9467 0052 0B43     		orrs	r3, r3, r1
+ 9468 0054 D362     		str	r3, [r2, #44]
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9469              		.loc 1 3087 3 is_stmt 1 view .LVU3218
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9470              		.loc 1 3087 3 view .LVU3219
+ 9471 0056 2368     		ldr	r3, [r4]
+ 9472 0058 7C4A     		ldr	r2, .L483+8
+ 9473 005a 9342     		cmp	r3, r2
+ 9474 005c 23D0     		beq	.L476
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9475              		.loc 1 3087 3 discriminator 2 view .LVU3220
+ 9476 005e 7C4A     		ldr	r2, .L483+12
+ 9477 0060 9342     		cmp	r3, r2
+ 9478 0062 34D0     		beq	.L477
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9479              		.loc 1 3087 3 discriminator 9 view .LVU3221
+ 9480 0064 7B4A     		ldr	r2, .L483+16
+ 9481 0066 9342     		cmp	r3, r2
+ 9482 0068 4AD0     		beq	.L478
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9483              		.loc 1 3087 3 discriminator 16 view .LVU3222
+ 9484 006a 7B4A     		ldr	r2, .L483+20
+ 9485 006c 9342     		cmp	r3, r2
+ARM GAS  /tmp/cceWHrnJ.s 			page 318
+
+
+ 9486 006e 59D0     		beq	.L479
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9487              		.loc 1 3087 3 discriminator 23 view .LVU3223
+ 9488 0070 754A     		ldr	r2, .L483+4
+ 9489 0072 9342     		cmp	r3, r2
+ 9490 0074 68D0     		beq	.L480
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9491              		.loc 1 3087 3 is_stmt 0 view .LVU3224
+ 9492 0076 1022     		movs	r2, #16
+ 9493              	.L409:
+ 9494              	.LVL855:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9495              		.loc 1 3087 3 is_stmt 1 discriminator 36 view .LVU3225
+3090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 9496              		.loc 1 3090 3 discriminator 36 view .LVU3226
+3090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 9497              		.loc 1 3090 6 is_stmt 0 discriminator 36 view .LVU3227
+ 9498 0078 7349     		ldr	r1, .L483+4
+ 9499 007a 8B42     		cmp	r3, r1
+ 9500 007c 00F09580 		beq	.L481
+3143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 9501              		.loc 1 3143 8 is_stmt 1 view .LVU3228
+3143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 9502              		.loc 1 3143 23 is_stmt 0 view .LVU3229
+ 9503 0080 E069     		ldr	r0, [r4, #28]
+3143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 9504              		.loc 1 3143 11 view .LVU3230
+ 9505 0082 B0F5004F 		cmp	r0, #32768
+ 9506 0086 00F0D280 		beq	.L482
+3186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9507              		.loc 1 3186 5 is_stmt 1 view .LVU3231
+ 9508 008a 082A     		cmp	r2, #8
+ 9509 008c 00F24F81 		bhi	.L470
+ 9510 0090 DFE812F0 		tbh	[pc, r2, lsl #1]
+ 9511              	.L440:
+ 9512 0094 1201     		.2byte	(.L444-.L440)/2
+ 9513 0096 3401     		.2byte	(.L443-.L440)/2
+ 9514 0098 1001     		.2byte	(.L442-.L440)/2
+ 9515 009a 4D01     		.2byte	(.L470-.L440)/2
+ 9516 009c 3701     		.2byte	(.L441-.L440)/2
+ 9517 009e 4D01     		.2byte	(.L470-.L440)/2
+ 9518 00a0 4D01     		.2byte	(.L470-.L440)/2
+ 9519 00a2 4D01     		.2byte	(.L470-.L440)/2
+ 9520 00a4 3A01     		.2byte	(.L471-.L440)/2
+ 9521              	.LVL856:
+ 9522              		.p2align 1
+ 9523              	.L476:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9524              		.loc 1 3087 3 discriminator 1 view .LVU3232
+ 9525 00a6 02F55842 		add	r2, r2, #55296
+ 9526 00aa D2F88820 		ldr	r2, [r2, #136]
+ 9527 00ae 02F00302 		and	r2, r2, #3
+ 9528 00b2 032A     		cmp	r2, #3
+ 9529 00b4 09D8     		bhi	.L406
+ 9530 00b6 DFE802F0 		tbb	[pc, r2]
+ 9531              	.L408:
+ 9532 00ba 02       		.byte	(.L411-.L408)/2
+ARM GAS  /tmp/cceWHrnJ.s 			page 319
+
+
+ 9533 00bb 04       		.byte	(.L410-.L408)/2
+ 9534 00bc 5C       		.byte	(.L446-.L408)/2
+ 9535 00bd 06       		.byte	(.L407-.L408)/2
+ 9536              		.p2align 1
+ 9537              	.L411:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9538              		.loc 1 3087 3 is_stmt 0 view .LVU3233
+ 9539 00be 0122     		movs	r2, #1
+ 9540 00c0 DAE7     		b	.L409
+ 9541              	.L410:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9542              		.loc 1 3087 3 is_stmt 1 discriminator 5 view .LVU3234
+ 9543              	.LVL857:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9544              		.loc 1 3087 3 discriminator 5 view .LVU3235
+ 9545 00c2 0422     		movs	r2, #4
+ 9546 00c4 D8E7     		b	.L409
+ 9547              	.LVL858:
+ 9548              	.L407:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9549              		.loc 1 3087 3 discriminator 7 view .LVU3236
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9550              		.loc 1 3087 3 discriminator 7 view .LVU3237
+ 9551 00c6 0822     		movs	r2, #8
+ 9552 00c8 D6E7     		b	.L409
+ 9553              	.LVL859:
+ 9554              	.L406:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9555              		.loc 1 3087 3 discriminator 3 view .LVU3238
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9556              		.loc 1 3087 3 discriminator 3 view .LVU3239
+ 9557 00ca 1022     		movs	r2, #16
+ 9558 00cc D4E7     		b	.L409
+ 9559              	.LVL860:
+ 9560              	.L477:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9561              		.loc 1 3087 3 discriminator 8 view .LVU3240
+ 9562 00ce 02F5E632 		add	r2, r2, #117760
+ 9563 00d2 D2F88820 		ldr	r2, [r2, #136]
+ 9564 00d6 02F00C02 		and	r2, r2, #12
+ 9565 00da 0C2A     		cmp	r2, #12
+ 9566 00dc 0ED8     		bhi	.L413
+ 9567 00de DFE802F0 		tbb	[pc, r2]
+ 9568              	.L415:
+ 9569 00e2 07       		.byte	(.L417-.L415)/2
+ 9570 00e3 0D       		.byte	(.L413-.L415)/2
+ 9571 00e4 0D       		.byte	(.L413-.L415)/2
+ 9572 00e5 0D       		.byte	(.L413-.L415)/2
+ 9573 00e6 09       		.byte	(.L416-.L415)/2
+ 9574 00e7 0D       		.byte	(.L413-.L415)/2
+ 9575 00e8 0D       		.byte	(.L413-.L415)/2
+ 9576 00e9 0D       		.byte	(.L413-.L415)/2
+ 9577 00ea 4A       		.byte	(.L447-.L415)/2
+ 9578 00eb 0D       		.byte	(.L413-.L415)/2
+ 9579 00ec 0D       		.byte	(.L413-.L415)/2
+ 9580 00ed 0D       		.byte	(.L413-.L415)/2
+ 9581 00ee 0B       		.byte	(.L414-.L415)/2
+ARM GAS  /tmp/cceWHrnJ.s 			page 320
+
+
+ 9582 00ef 00       		.p2align 1
+ 9583              	.L417:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9584              		.loc 1 3087 3 is_stmt 0 view .LVU3241
+ 9585 00f0 0022     		movs	r2, #0
+ 9586 00f2 C1E7     		b	.L409
+ 9587              	.L416:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9588              		.loc 1 3087 3 is_stmt 1 discriminator 12 view .LVU3242
+ 9589              	.LVL861:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9590              		.loc 1 3087 3 discriminator 12 view .LVU3243
+ 9591 00f4 0422     		movs	r2, #4
+ 9592 00f6 BFE7     		b	.L409
+ 9593              	.LVL862:
+ 9594              	.L414:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9595              		.loc 1 3087 3 discriminator 14 view .LVU3244
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9596              		.loc 1 3087 3 discriminator 14 view .LVU3245
+ 9597 00f8 0822     		movs	r2, #8
+ 9598 00fa BDE7     		b	.L409
+ 9599              	.LVL863:
+ 9600              	.L413:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9601              		.loc 1 3087 3 discriminator 10 view .LVU3246
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9602              		.loc 1 3087 3 discriminator 10 view .LVU3247
+ 9603 00fc 1022     		movs	r2, #16
+ 9604 00fe BBE7     		b	.L409
+ 9605              	.LVL864:
+ 9606              	.L478:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9607              		.loc 1 3087 3 discriminator 15 view .LVU3248
+ 9608 0100 02F5E432 		add	r2, r2, #116736
+ 9609 0104 D2F88820 		ldr	r2, [r2, #136]
+ 9610 0108 02F03002 		and	r2, r2, #48
+ 9611 010c 202A     		cmp	r2, #32
+ 9612 010e 34D0     		beq	.L448
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9613              		.loc 1 3087 3 is_stmt 0 view .LVU3249
+ 9614 0110 04D8     		bhi	.L419
+ 9615 0112 A2B3     		cbz	r2, .L449
+ 9616 0114 102A     		cmp	r2, #16
+ 9617 0116 34D1     		bne	.L450
+ 9618 0118 0422     		movs	r2, #4
+ 9619 011a ADE7     		b	.L409
+ 9620              	.L419:
+ 9621 011c 302A     		cmp	r2, #48
+ 9622 011e 32D1     		bne	.L451
+ 9623 0120 0822     		movs	r2, #8
+ 9624 0122 A9E7     		b	.L409
+ 9625              	.L479:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9626              		.loc 1 3087 3 is_stmt 1 discriminator 22 view .LVU3250
+ 9627 0124 02F5E232 		add	r2, r2, #115712
+ 9628 0128 D2F88820 		ldr	r2, [r2, #136]
+ARM GAS  /tmp/cceWHrnJ.s 			page 321
+
+
+ 9629 012c 02F0C002 		and	r2, r2, #192
+ 9630 0130 802A     		cmp	r2, #128
+ 9631 0132 2AD0     		beq	.L452
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9632              		.loc 1 3087 3 is_stmt 0 view .LVU3251
+ 9633 0134 04D8     		bhi	.L421
+ 9634 0136 52B3     		cbz	r2, .L453
+ 9635 0138 402A     		cmp	r2, #64
+ 9636 013a 2AD1     		bne	.L454
+ 9637 013c 0422     		movs	r2, #4
+ 9638 013e 9BE7     		b	.L409
+ 9639              	.L421:
+ 9640 0140 C02A     		cmp	r2, #192
+ 9641 0142 28D1     		bne	.L455
+ 9642 0144 0822     		movs	r2, #8
+ 9643 0146 97E7     		b	.L409
+ 9644              	.L480:
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9645              		.loc 1 3087 3 is_stmt 1 discriminator 29 view .LVU3252
+ 9646 0148 02F5C832 		add	r2, r2, #102400
+ 9647 014c D2F88820 		ldr	r2, [r2, #136]
+ 9648 0150 02F44062 		and	r2, r2, #3072
+ 9649 0154 B2F5006F 		cmp	r2, #2048
+ 9650 0158 1FD0     		beq	.L457
+3087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9651              		.loc 1 3087 3 is_stmt 0 view .LVU3253
+ 9652 015a 05D8     		bhi	.L422
+ 9653 015c FAB1     		cbz	r2, .L458
+ 9654 015e B2F5806F 		cmp	r2, #1024
+ 9655 0162 1ED1     		bne	.L459
+ 9656 0164 0422     		movs	r2, #4
+ 9657 0166 87E7     		b	.L409
+ 9658              	.L422:
+ 9659 0168 B2F5406F 		cmp	r2, #3072
+ 9660 016c 1BD1     		bne	.L460
+ 9661 016e 0822     		movs	r2, #8
+ 9662 0170 82E7     		b	.L409
+ 9663              	.L446:
+ 9664 0172 0222     		movs	r2, #2
+ 9665 0174 80E7     		b	.L409
+ 9666              	.L447:
+ 9667 0176 0222     		movs	r2, #2
+ 9668 0178 7EE7     		b	.L409
+ 9669              	.L448:
+ 9670 017a 0222     		movs	r2, #2
+ 9671 017c 7CE7     		b	.L409
+ 9672              	.L449:
+ 9673 017e 0022     		movs	r2, #0
+ 9674 0180 7AE7     		b	.L409
+ 9675              	.L450:
+ 9676 0182 1022     		movs	r2, #16
+ 9677 0184 78E7     		b	.L409
+ 9678              	.L451:
+ 9679 0186 1022     		movs	r2, #16
+ 9680 0188 76E7     		b	.L409
+ 9681              	.L452:
+ 9682 018a 0222     		movs	r2, #2
+ARM GAS  /tmp/cceWHrnJ.s 			page 322
+
+
+ 9683 018c 74E7     		b	.L409
+ 9684              	.L453:
+ 9685 018e 0022     		movs	r2, #0
+ 9686 0190 72E7     		b	.L409
+ 9687              	.L454:
+ 9688 0192 1022     		movs	r2, #16
+ 9689 0194 70E7     		b	.L409
+ 9690              	.L455:
+ 9691 0196 1022     		movs	r2, #16
+ 9692 0198 6EE7     		b	.L409
+ 9693              	.L457:
+ 9694 019a 0222     		movs	r2, #2
+ 9695 019c 6CE7     		b	.L409
+ 9696              	.L458:
+ 9697 019e 0022     		movs	r2, #0
+ 9698 01a0 6AE7     		b	.L409
+ 9699              	.L459:
+ 9700 01a2 1022     		movs	r2, #16
+ 9701 01a4 68E7     		b	.L409
+ 9702              	.L460:
+ 9703 01a6 1022     		movs	r2, #16
+ 9704 01a8 66E7     		b	.L409
+ 9705              	.LVL865:
+ 9706              	.L481:
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9707              		.loc 1 3093 5 is_stmt 1 view .LVU3254
+ 9708 01aa 082A     		cmp	r2, #8
+ 9709 01ac 00F2AF80 		bhi	.L461
+ 9710 01b0 DFE802F0 		tbb	[pc, r2]
+ 9711              	.L426:
+ 9712 01b4 08       		.byte	(.L429-.L426)/2
+ 9713 01b5 AD       		.byte	(.L461-.L426)/2
+ 9714 01b6 3B       		.byte	(.L462-.L426)/2
+ 9715 01b7 AD       		.byte	(.L461-.L426)/2
+ 9716 01b8 38       		.byte	(.L427-.L426)/2
+ 9717 01b9 AD       		.byte	(.L461-.L426)/2
+ 9718 01ba AD       		.byte	(.L461-.L426)/2
+ 9719 01bb AD       		.byte	(.L461-.L426)/2
+ 9720 01bc 05       		.byte	(.L425-.L426)/2
+ 9721 01bd 00       		.p2align 1
+ 9722              	.L425:
+ 9723 01be 4FF40040 		mov	r0, #32768
+ 9724 01c2 04E0     		b	.L428
+ 9725              	.L429:
+3096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9726              		.loc 1 3096 9 view .LVU3255
+3096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9727              		.loc 1 3096 16 is_stmt 0 view .LVU3256
+ 9728 01c4 FFF7FEFF 		bl	HAL_RCC_GetPCLK1Freq
+ 9729              	.LVL866:
+3097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_HSI:
+ 9730              		.loc 1 3097 9 is_stmt 1 view .LVU3257
+ 9731              	.L430:
+3114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9732              		.loc 1 3114 5 view .LVU3258
+3114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9733              		.loc 1 3114 8 is_stmt 0 view .LVU3259
+ARM GAS  /tmp/cceWHrnJ.s 			page 323
+
+
+ 9734 01c8 0028     		cmp	r0, #0
+ 9735 01ca 00F0A280 		beq	.L463
+ 9736              	.LVL867:
+ 9737              	.L428:
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9738              		.loc 1 3117 7 is_stmt 1 view .LVU3260
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9739              		.loc 1 3117 62 is_stmt 0 view .LVU3261
+ 9740 01ce 626A     		ldr	r2, [r4, #36]
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9741              		.loc 1 3117 50 view .LVU3262
+ 9742 01d0 224B     		ldr	r3, .L483+24
+ 9743 01d2 33F81220 		ldrh	r2, [r3, r2, lsl #1]
+3117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9744              		.loc 1 3117 26 view .LVU3263
+ 9745 01d6 B0FBF2F3 		udiv	r3, r0, r2
+ 9746              	.LVL868:
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+ 9747              		.loc 1 3120 7 is_stmt 1 view .LVU3264
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+ 9748              		.loc 1 3120 50 is_stmt 0 view .LVU3265
+ 9749 01da 6568     		ldr	r5, [r4, #4]
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+ 9750              		.loc 1 3120 37 view .LVU3266
+ 9751 01dc 05EB4501 		add	r1, r5, r5, lsl #1
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+ 9752              		.loc 1 3120 10 view .LVU3267
+ 9753 01e0 9942     		cmp	r1, r3
+ 9754 01e2 00F29880 		bhi	.L464
+3120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+ 9755              		.loc 1 3120 62 discriminator 1 view .LVU3268
+ 9756 01e6 B3EB053F 		cmp	r3, r5, lsl #12
+ 9757 01ea 00F29680 		bhi	.L465
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+ 9758              		.loc 1 3129 9 is_stmt 1 view .LVU3269
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+ 9759              		.loc 1 3129 31 is_stmt 0 view .LVU3270
+ 9760 01ee 0026     		movs	r6, #0
+ 9761 01f0 3346     		mov	r3, r6
+ 9762              	.LVL869:
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+ 9763              		.loc 1 3129 31 view .LVU3271
+ 9764 01f2 3146     		mov	r1, r6
+ 9765 01f4 FFF7FEFF 		bl	__aeabi_uldivmod
+ 9766              	.LVL870:
+3129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+ 9767              		.loc 1 3129 31 view .LVU3272
+ 9768 01f8 0902     		lsls	r1, r1, #8
+ 9769 01fa 41EA1061 		orr	r1, r1, r0, lsr #24
+ 9770 01fe 0002     		lsls	r0, r0, #8
+ 9771 0200 6B08     		lsrs	r3, r5, #1
+ 9772 0202 C018     		adds	r0, r0, r3
+ 9773 0204 2A46     		mov	r2, r5
+ 9774 0206 3346     		mov	r3, r6
+ 9775 0208 41F10001 		adc	r1, r1, #0
+ 9776 020c FFF7FEFF 		bl	__aeabi_uldivmod
+ 9777              	.LVL871:
+ARM GAS  /tmp/cceWHrnJ.s 			page 324
+
+
+3130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 9778              		.loc 1 3130 9 is_stmt 1 view .LVU3273
+3130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 9779              		.loc 1 3130 42 is_stmt 0 view .LVU3274
+ 9780 0210 A0F54072 		sub	r2, r0, #768
+3130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 9781              		.loc 1 3130 12 view .LVU3275
+ 9782 0214 124B     		ldr	r3, .L483+28
+ 9783 0216 9A42     		cmp	r2, r3
+ 9784 0218 00F28180 		bhi	.L466
+3132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 9785              		.loc 1 3132 11 is_stmt 1 view .LVU3276
+3132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 9786              		.loc 1 3132 16 is_stmt 0 view .LVU3277
+ 9787 021c 2368     		ldr	r3, [r4]
+3132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 9788              		.loc 1 3132 32 view .LVU3278
+ 9789 021e D860     		str	r0, [r3, #12]
+ 9790 0220 3046     		mov	r0, r6
+ 9791              	.LVL872:
+3132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 9792              		.loc 1 3132 32 view .LVU3279
+ 9793 0222 62E0     		b	.L424
+ 9794              	.LVL873:
+ 9795              	.L427:
+3102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9796              		.loc 1 3102 9 is_stmt 1 view .LVU3280
+3102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9797              		.loc 1 3102 16 is_stmt 0 view .LVU3281
+ 9798 0224 FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 9799              	.LVL874:
+3103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_LSE:
+ 9800              		.loc 1 3103 9 is_stmt 1 view .LVU3282
+ 9801 0228 CEE7     		b	.L430
+ 9802              	.LVL875:
+ 9803              	.L462:
+3099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9804              		.loc 1 3099 14 is_stmt 0 view .LVU3283
+ 9805 022a 0E48     		ldr	r0, .L483+32
+ 9806 022c CFE7     		b	.L428
+ 9807              	.L482:
+3145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9808              		.loc 1 3145 5 is_stmt 1 view .LVU3284
+ 9809 022e 082A     		cmp	r2, #8
+ 9810 0230 77D8     		bhi	.L467
+ 9811 0232 DFE802F0 		tbb	[pc, r2]
+ 9812              	.L433:
+ 9813 0236 19       		.byte	(.L437-.L433)/2
+ 9814 0237 39       		.byte	(.L436-.L433)/2
+ 9815 0238 05       		.byte	(.L435-.L433)/2
+ 9816 0239 76       		.byte	(.L467-.L433)/2
+ 9817 023a 3C       		.byte	(.L434-.L433)/2
+ 9818 023b 76       		.byte	(.L467-.L433)/2
+ 9819 023c 76       		.byte	(.L467-.L433)/2
+ 9820 023d 76       		.byte	(.L467-.L433)/2
+ 9821 023e 1D       		.byte	(.L432-.L433)/2
+ 9822 023f 00       		.p2align 1
+ARM GAS  /tmp/cceWHrnJ.s 			page 325
+
+
+ 9823              	.L435:
+ 9824 0240 0848     		ldr	r0, .L483+32
+ 9825 0242 15E0     		b	.L432
+ 9826              	.L484:
+ 9827              		.align	2
+ 9828              	.L483:
+ 9829 0244 F369FFCF 		.word	-805344781
+ 9830 0248 00800040 		.word	1073774592
+ 9831 024c 00380140 		.word	1073821696
+ 9832 0250 00440040 		.word	1073759232
+ 9833 0254 00480040 		.word	1073760256
+ 9834 0258 004C0040 		.word	1073761280
+ 9835 025c 00000000 		.word	UARTPrescTable
+ 9836 0260 FFFC0F00 		.word	1047807
+ 9837 0264 0024F400 		.word	16000000
+ 9838              	.L437:
+3148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9839              		.loc 1 3148 9 view .LVU3285
+3148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9840              		.loc 1 3148 16 is_stmt 0 view .LVU3286
+ 9841 0268 FFF7FEFF 		bl	HAL_RCC_GetPCLK1Freq
+ 9842              	.LVL876:
+3149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_PCLK2:
+ 9843              		.loc 1 3149 9 is_stmt 1 view .LVU3287
+ 9844              	.L438:
+3169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9845              		.loc 1 3169 5 view .LVU3288
+3169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9846              		.loc 1 3169 8 is_stmt 0 view .LVU3289
+ 9847 026c 0028     		cmp	r0, #0
+ 9848 026e 5AD0     		beq	.L468
+ 9849              	.LVL877:
+ 9850              	.L432:
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 9851              		.loc 1 3171 7 is_stmt 1 view .LVU3290
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 9852              		.loc 1 3171 29 is_stmt 0 view .LVU3291
+ 9853 0270 626A     		ldr	r2, [r4, #36]
+ 9854 0272 324B     		ldr	r3, .L485
+ 9855 0274 33F81230 		ldrh	r3, [r3, r2, lsl #1]
+ 9856 0278 B0FBF3F0 		udiv	r0, r0, r3
+ 9857 027c 6268     		ldr	r2, [r4, #4]
+ 9858 027e 5308     		lsrs	r3, r2, #1
+ 9859 0280 03EB4003 		add	r3, r3, r0, lsl #1
+3171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 9860              		.loc 1 3171 16 view .LVU3292
+ 9861 0284 B3FBF2F3 		udiv	r3, r3, r2
+ 9862              	.LVL878:
+3172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 9863              		.loc 1 3172 7 is_stmt 1 view .LVU3293
+3172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 9864              		.loc 1 3172 38 is_stmt 0 view .LVU3294
+ 9865 0288 A3F11001 		sub	r1, r3, #16
+3172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 9866              		.loc 1 3172 10 view .LVU3295
+ 9867 028c 4FF6EF72 		movw	r2, #65519
+ 9868 0290 9142     		cmp	r1, r2
+ARM GAS  /tmp/cceWHrnJ.s 			page 326
+
+
+ 9869 0292 4AD8     		bhi	.L469
+3174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 9870              		.loc 1 3174 9 is_stmt 1 view .LVU3296
+3174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 9871              		.loc 1 3174 19 is_stmt 0 view .LVU3297
+ 9872 0294 9AB2     		uxth	r2, r3
+3174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 9873              		.loc 1 3174 17 view .LVU3298
+ 9874 0296 22F00F02 		bic	r2, r2, #15
+ 9875              	.LVL879:
+3175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->Instance->BRR = brrtemp;
+ 9876              		.loc 1 3175 9 is_stmt 1 view .LVU3299
+3175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->Instance->BRR = brrtemp;
+ 9877              		.loc 1 3175 20 is_stmt 0 view .LVU3300
+ 9878 029a C3F34203 		ubfx	r3, r3, #1, #3
+ 9879              	.LVL880:
+3175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->Instance->BRR = brrtemp;
+ 9880              		.loc 1 3175 17 view .LVU3301
+ 9881 029e 1343     		orrs	r3, r3, r2
+ 9882              	.LVL881:
+3176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 9883              		.loc 1 3176 9 is_stmt 1 view .LVU3302
+3176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 9884              		.loc 1 3176 14 is_stmt 0 view .LVU3303
+ 9885 02a0 2268     		ldr	r2, [r4]
+3176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 9886              		.loc 1 3176 30 view .LVU3304
+ 9887 02a2 D360     		str	r3, [r2, #12]
+ 9888 02a4 0020     		movs	r0, #0
+ 9889 02a6 20E0     		b	.L424
+ 9890              	.LVL882:
+ 9891              	.L436:
+3151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9892              		.loc 1 3151 9 is_stmt 1 view .LVU3305
+3151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9893              		.loc 1 3151 16 is_stmt 0 view .LVU3306
+ 9894 02a8 FFF7FEFF 		bl	HAL_RCC_GetPCLK2Freq
+ 9895              	.LVL883:
+3152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_HSI:
+ 9896              		.loc 1 3152 9 is_stmt 1 view .LVU3307
+ 9897 02ac DEE7     		b	.L438
+ 9898              	.LVL884:
+ 9899              	.L434:
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9900              		.loc 1 3157 9 view .LVU3308
+3157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9901              		.loc 1 3157 16 is_stmt 0 view .LVU3309
+ 9902 02ae FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 9903              	.LVL885:
+3158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_LSE:
+ 9904              		.loc 1 3158 9 is_stmt 1 view .LVU3310
+ 9905 02b2 DBE7     		b	.L438
+ 9906              	.LVL886:
+ 9907              	.L442:
+3186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9908              		.loc 1 3186 5 is_stmt 0 view .LVU3311
+ 9909 02b4 2248     		ldr	r0, .L485+4
+ARM GAS  /tmp/cceWHrnJ.s 			page 327
+
+
+ 9910 02b6 03E0     		b	.L439
+ 9911              	.L444:
+3189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9912              		.loc 1 3189 9 is_stmt 1 view .LVU3312
+3189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9913              		.loc 1 3189 16 is_stmt 0 view .LVU3313
+ 9914 02b8 FFF7FEFF 		bl	HAL_RCC_GetPCLK1Freq
+ 9915              	.LVL887:
+3190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_PCLK2:
+ 9916              		.loc 1 3190 9 is_stmt 1 view .LVU3314
+ 9917              	.L445:
+3209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9918              		.loc 1 3209 5 view .LVU3315
+3209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9919              		.loc 1 3209 8 is_stmt 0 view .LVU3316
+ 9920 02bc 0028     		cmp	r0, #0
+ 9921 02be 38D0     		beq	.L472
+ 9922              	.LVL888:
+ 9923              	.L439:
+3212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 9924              		.loc 1 3212 7 is_stmt 1 view .LVU3317
+3212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 9925              		.loc 1 3212 29 is_stmt 0 view .LVU3318
+ 9926 02c0 626A     		ldr	r2, [r4, #36]
+ 9927 02c2 1E4B     		ldr	r3, .L485
+ 9928 02c4 33F81230 		ldrh	r3, [r3, r2, lsl #1]
+ 9929 02c8 B0FBF3F0 		udiv	r0, r0, r3
+ 9930 02cc 6368     		ldr	r3, [r4, #4]
+ 9931 02ce 00EB5300 		add	r0, r0, r3, lsr #1
+3212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 9932              		.loc 1 3212 16 view .LVU3319
+ 9933 02d2 B0FBF3F0 		udiv	r0, r0, r3
+ 9934              	.LVL889:
+3213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 9935              		.loc 1 3213 7 is_stmt 1 view .LVU3320
+3213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 9936              		.loc 1 3213 38 is_stmt 0 view .LVU3321
+ 9937 02d6 A0F11002 		sub	r2, r0, #16
+3213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 9938              		.loc 1 3213 10 view .LVU3322
+ 9939 02da 4FF6EF73 		movw	r3, #65519
+ 9940 02de 9A42     		cmp	r2, r3
+ 9941 02e0 29D8     		bhi	.L473
+3215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 9942              		.loc 1 3215 9 is_stmt 1 view .LVU3323
+3215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 9943              		.loc 1 3215 14 is_stmt 0 view .LVU3324
+ 9944 02e2 2368     		ldr	r3, [r4]
+ 9945 02e4 80B2     		uxth	r0, r0
+ 9946              	.LVL890:
+3215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 9947              		.loc 1 3215 30 view .LVU3325
+ 9948 02e6 D860     		str	r0, [r3, #12]
+ 9949 02e8 0020     		movs	r0, #0
+ 9950              	.LVL891:
+ 9951              	.L424:
+3225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->NbRxDataToProcess = 1;
+ARM GAS  /tmp/cceWHrnJ.s 			page 328
+
+
+ 9952              		.loc 1 3225 3 is_stmt 1 view .LVU3326
+3225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->NbRxDataToProcess = 1;
+ 9953              		.loc 1 3225 28 is_stmt 0 view .LVU3327
+ 9954 02ea 0123     		movs	r3, #1
+ 9955 02ec A4F86A30 		strh	r3, [r4, #106]	@ movhi
+3226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9956              		.loc 1 3226 3 is_stmt 1 view .LVU3328
+3226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9957              		.loc 1 3226 28 is_stmt 0 view .LVU3329
+ 9958 02f0 A4F86830 		strh	r3, [r4, #104]	@ movhi
+3229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxISR = NULL;
+ 9959              		.loc 1 3229 3 is_stmt 1 view .LVU3330
+3229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->TxISR = NULL;
+ 9960              		.loc 1 3229 16 is_stmt 0 view .LVU3331
+ 9961 02f4 0023     		movs	r3, #0
+ 9962 02f6 2367     		str	r3, [r4, #112]
+3230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9963              		.loc 1 3230 3 is_stmt 1 view .LVU3332
+3230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9964              		.loc 1 3230 16 is_stmt 0 view .LVU3333
+ 9965 02f8 6367     		str	r3, [r4, #116]
+3232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 9966              		.loc 1 3232 3 is_stmt 1 view .LVU3334
+3233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 9967              		.loc 1 3233 1 is_stmt 0 view .LVU3335
+ 9968 02fa 70BD     		pop	{r4, r5, r6, pc}
+ 9969              	.LVL892:
+ 9970              	.L443:
+3192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9971              		.loc 1 3192 9 is_stmt 1 view .LVU3336
+3192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9972              		.loc 1 3192 16 is_stmt 0 view .LVU3337
+ 9973 02fc FFF7FEFF 		bl	HAL_RCC_GetPCLK2Freq
+ 9974              	.LVL893:
+3193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_HSI:
+ 9975              		.loc 1 3193 9 is_stmt 1 view .LVU3338
+ 9976 0300 DCE7     		b	.L445
+ 9977              	.LVL894:
+ 9978              	.L441:
+3198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9979              		.loc 1 3198 9 view .LVU3339
+3198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9980              		.loc 1 3198 16 is_stmt 0 view .LVU3340
+ 9981 0302 FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 9982              	.LVL895:
+3199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       case UART_CLOCKSOURCE_LSE:
+ 9983              		.loc 1 3199 9 is_stmt 1 view .LVU3341
+ 9984 0306 D9E7     		b	.L445
+ 9985              	.LVL896:
+ 9986              	.L471:
+3201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         break;
+ 9987              		.loc 1 3201 14 is_stmt 0 view .LVU3342
+ 9988 0308 4FF40040 		mov	r0, #32768
+ 9989 030c D8E7     		b	.L439
+ 9990              	.L461:
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9991              		.loc 1 3093 5 view .LVU3343
+ARM GAS  /tmp/cceWHrnJ.s 			page 329
+
+
+ 9992 030e 0120     		movs	r0, #1
+ 9993 0310 EBE7     		b	.L424
+ 9994              	.LVL897:
+ 9995              	.L463:
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9996              		.loc 1 3093 5 view .LVU3344
+ 9997 0312 0020     		movs	r0, #0
+ 9998              	.LVL898:
+3093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 9999              		.loc 1 3093 5 view .LVU3345
+ 10000 0314 E9E7     		b	.L424
+ 10001              	.LVL899:
+ 10002              	.L464:
+3123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 10003              		.loc 1 3123 13 view .LVU3346
+ 10004 0316 0120     		movs	r0, #1
+ 10005 0318 E7E7     		b	.L424
+ 10006              	.L465:
+ 10007 031a 0120     		movs	r0, #1
+ 10008 031c E5E7     		b	.L424
+ 10009              	.LVL900:
+ 10010              	.L466:
+3136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 10011              		.loc 1 3136 15 view .LVU3347
+ 10012 031e 0120     		movs	r0, #1
+ 10013              	.LVL901:
+3136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 10014              		.loc 1 3136 15 view .LVU3348
+ 10015 0320 E3E7     		b	.L424
+ 10016              	.LVL902:
+ 10017              	.L467:
+3145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10018              		.loc 1 3145 5 view .LVU3349
+ 10019 0322 0120     		movs	r0, #1
+ 10020 0324 E1E7     		b	.L424
+ 10021              	.LVL903:
+ 10022              	.L468:
+3145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10023              		.loc 1 3145 5 view .LVU3350
+ 10024 0326 0020     		movs	r0, #0
+ 10025              	.LVL904:
+3145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10026              		.loc 1 3145 5 view .LVU3351
+ 10027 0328 DFE7     		b	.L424
+ 10028              	.LVL905:
+ 10029              	.L469:
+3180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 10030              		.loc 1 3180 13 view .LVU3352
+ 10031 032a 0120     		movs	r0, #1
+ 10032 032c DDE7     		b	.L424
+ 10033              	.LVL906:
+ 10034              	.L470:
+3186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10035              		.loc 1 3186 5 view .LVU3353
+ 10036 032e 0120     		movs	r0, #1
+ 10037 0330 DBE7     		b	.L424
+ 10038              	.LVL907:
+ARM GAS  /tmp/cceWHrnJ.s 			page 330
+
+
+ 10039              	.L472:
+3186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10040              		.loc 1 3186 5 view .LVU3354
+ 10041 0332 0020     		movs	r0, #0
+ 10042              	.LVL908:
+3186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10043              		.loc 1 3186 5 view .LVU3355
+ 10044 0334 D9E7     		b	.L424
+ 10045              	.LVL909:
+ 10046              	.L473:
+3219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 10047              		.loc 1 3219 13 view .LVU3356
+ 10048 0336 0120     		movs	r0, #1
+ 10049              	.LVL910:
+3219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 10050              		.loc 1 3219 13 view .LVU3357
+ 10051 0338 D7E7     		b	.L424
+ 10052              	.L486:
+ 10053 033a 00BF     		.align	2
+ 10054              	.L485:
+ 10055 033c 00000000 		.word	UARTPrescTable
+ 10056 0340 0024F400 		.word	16000000
+ 10057              		.cfi_endproc
+ 10058              	.LFE372:
+ 10060              		.section	.text.UART_AdvFeatureConfig,"ax",%progbits
+ 10061              		.align	1
+ 10062              		.global	UART_AdvFeatureConfig
+ 10063              		.syntax unified
+ 10064              		.thumb
+ 10065              		.thumb_func
+ 10067              	UART_AdvFeatureConfig:
+ 10068              	.LVL911:
+ 10069              	.LFB373:
+3241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check whether the set of advanced features to configure is properly set */
+ 10070              		.loc 1 3241 1 is_stmt 1 view -0
+ 10071              		.cfi_startproc
+ 10072              		@ args = 0, pretend = 0, frame = 0
+ 10073              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10074              		@ link register save eliminated.
+3243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10075              		.loc 1 3243 3 view .LVU3359
+3246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10076              		.loc 1 3246 3 view .LVU3360
+3246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10077              		.loc 1 3246 7 is_stmt 0 view .LVU3361
+ 10078 0000 836A     		ldr	r3, [r0, #40]
+3246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10079              		.loc 1 3246 6 view .LVU3362
+ 10080 0002 13F0010F 		tst	r3, #1
+ 10081 0006 06D0     		beq	.L488
+3248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ 10082              		.loc 1 3248 5 is_stmt 1 view .LVU3363
+3249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 10083              		.loc 1 3249 5 view .LVU3364
+ 10084 0008 0268     		ldr	r2, [r0]
+ 10085 000a 5368     		ldr	r3, [r2, #4]
+ 10086 000c 23F40033 		bic	r3, r3, #131072
+ARM GAS  /tmp/cceWHrnJ.s 			page 331
+
+
+ 10087 0010 C16A     		ldr	r1, [r0, #44]
+ 10088 0012 0B43     		orrs	r3, r3, r1
+ 10089 0014 5360     		str	r3, [r2, #4]
+ 10090              	.L488:
+3253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10091              		.loc 1 3253 3 view .LVU3365
+3253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10092              		.loc 1 3253 7 is_stmt 0 view .LVU3366
+ 10093 0016 836A     		ldr	r3, [r0, #40]
+3253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10094              		.loc 1 3253 6 view .LVU3367
+ 10095 0018 13F0020F 		tst	r3, #2
+ 10096 001c 06D0     		beq	.L489
+3255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ 10097              		.loc 1 3255 5 is_stmt 1 view .LVU3368
+3256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 10098              		.loc 1 3256 5 view .LVU3369
+ 10099 001e 0268     		ldr	r2, [r0]
+ 10100 0020 5368     		ldr	r3, [r2, #4]
+ 10101 0022 23F48033 		bic	r3, r3, #65536
+ 10102 0026 016B     		ldr	r1, [r0, #48]
+ 10103 0028 0B43     		orrs	r3, r3, r1
+ 10104 002a 5360     		str	r3, [r2, #4]
+ 10105              	.L489:
+3260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10106              		.loc 1 3260 3 view .LVU3370
+3260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10107              		.loc 1 3260 7 is_stmt 0 view .LVU3371
+ 10108 002c 836A     		ldr	r3, [r0, #40]
+3260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10109              		.loc 1 3260 6 view .LVU3372
+ 10110 002e 13F0040F 		tst	r3, #4
+ 10111 0032 06D0     		beq	.L490
+3262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ 10112              		.loc 1 3262 5 is_stmt 1 view .LVU3373
+3263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 10113              		.loc 1 3263 5 view .LVU3374
+ 10114 0034 0268     		ldr	r2, [r0]
+ 10115 0036 5368     		ldr	r3, [r2, #4]
+ 10116 0038 23F48023 		bic	r3, r3, #262144
+ 10117 003c 416B     		ldr	r1, [r0, #52]
+ 10118 003e 0B43     		orrs	r3, r3, r1
+ 10119 0040 5360     		str	r3, [r2, #4]
+ 10120              	.L490:
+3267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10121              		.loc 1 3267 3 view .LVU3375
+3267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10122              		.loc 1 3267 7 is_stmt 0 view .LVU3376
+ 10123 0042 836A     		ldr	r3, [r0, #40]
+3267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10124              		.loc 1 3267 6 view .LVU3377
+ 10125 0044 13F0080F 		tst	r3, #8
+ 10126 0048 06D0     		beq	.L491
+3269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ 10127              		.loc 1 3269 5 is_stmt 1 view .LVU3378
+3270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 10128              		.loc 1 3270 5 view .LVU3379
+ARM GAS  /tmp/cceWHrnJ.s 			page 332
+
+
+ 10129 004a 0268     		ldr	r2, [r0]
+ 10130 004c 5368     		ldr	r3, [r2, #4]
+ 10131 004e 23F40043 		bic	r3, r3, #32768
+ 10132 0052 816B     		ldr	r1, [r0, #56]
+ 10133 0054 0B43     		orrs	r3, r3, r1
+ 10134 0056 5360     		str	r3, [r2, #4]
+ 10135              	.L491:
+3274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10136              		.loc 1 3274 3 view .LVU3380
+3274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10137              		.loc 1 3274 7 is_stmt 0 view .LVU3381
+ 10138 0058 836A     		ldr	r3, [r0, #40]
+3274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10139              		.loc 1 3274 6 view .LVU3382
+ 10140 005a 13F0100F 		tst	r3, #16
+ 10141 005e 06D0     		beq	.L492
+3276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ 10142              		.loc 1 3276 5 is_stmt 1 view .LVU3383
+3277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 10143              		.loc 1 3277 5 view .LVU3384
+ 10144 0060 0268     		ldr	r2, [r0]
+ 10145 0062 9368     		ldr	r3, [r2, #8]
+ 10146 0064 23F48053 		bic	r3, r3, #4096
+ 10147 0068 C16B     		ldr	r1, [r0, #60]
+ 10148 006a 0B43     		orrs	r3, r3, r1
+ 10149 006c 9360     		str	r3, [r2, #8]
+ 10150              	.L492:
+3281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10151              		.loc 1 3281 3 view .LVU3385
+3281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10152              		.loc 1 3281 7 is_stmt 0 view .LVU3386
+ 10153 006e 836A     		ldr	r3, [r0, #40]
+3281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10154              		.loc 1 3281 6 view .LVU3387
+ 10155 0070 13F0200F 		tst	r3, #32
+ 10156 0074 06D0     		beq	.L493
+3283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ 10157              		.loc 1 3283 5 is_stmt 1 view .LVU3388
+3284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 10158              		.loc 1 3284 5 view .LVU3389
+ 10159 0076 0268     		ldr	r2, [r0]
+ 10160 0078 9368     		ldr	r3, [r2, #8]
+ 10161 007a 23F40053 		bic	r3, r3, #8192
+ 10162 007e 016C     		ldr	r1, [r0, #64]
+ 10163 0080 0B43     		orrs	r3, r3, r1
+ 10164 0082 9360     		str	r3, [r2, #8]
+ 10165              	.L493:
+3288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10166              		.loc 1 3288 3 view .LVU3390
+3288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10167              		.loc 1 3288 7 is_stmt 0 view .LVU3391
+ 10168 0084 836A     		ldr	r3, [r0, #40]
+3288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10169              		.loc 1 3288 6 view .LVU3392
+ 10170 0086 13F0400F 		tst	r3, #64
+ 10171 008a 0AD0     		beq	.L494
+3290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+ARM GAS  /tmp/cceWHrnJ.s 			page 333
+
+
+ 10172              		.loc 1 3290 5 is_stmt 1 view .LVU3393
+3291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ 10173              		.loc 1 3291 5 view .LVU3394
+3292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     /* set auto Baudrate detection parameters if detection is enabled */
+ 10174              		.loc 1 3292 5 view .LVU3395
+ 10175 008c 0268     		ldr	r2, [r0]
+ 10176 008e 5368     		ldr	r3, [r2, #4]
+ 10177 0090 23F48013 		bic	r3, r3, #1048576
+ 10178 0094 416C     		ldr	r1, [r0, #68]
+ 10179 0096 0B43     		orrs	r3, r3, r1
+ 10180 0098 5360     		str	r3, [r2, #4]
+3294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10181              		.loc 1 3294 5 view .LVU3396
+3294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10182              		.loc 1 3294 28 is_stmt 0 view .LVU3397
+ 10183 009a 436C     		ldr	r3, [r0, #68]
+3294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10184              		.loc 1 3294 8 view .LVU3398
+ 10185 009c B3F5801F 		cmp	r3, #1048576
+ 10186 00a0 0BD0     		beq	.L496
+ 10187              	.L494:
+3302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10188              		.loc 1 3302 3 is_stmt 1 view .LVU3399
+3302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10189              		.loc 1 3302 7 is_stmt 0 view .LVU3400
+ 10190 00a2 836A     		ldr	r3, [r0, #40]
+3302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10191              		.loc 1 3302 6 view .LVU3401
+ 10192 00a4 13F0800F 		tst	r3, #128
+ 10193 00a8 06D0     		beq	.L487
+3304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ 10194              		.loc 1 3304 5 is_stmt 1 view .LVU3402
+3305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 10195              		.loc 1 3305 5 view .LVU3403
+ 10196 00aa 0268     		ldr	r2, [r0]
+ 10197 00ac 5368     		ldr	r3, [r2, #4]
+ 10198 00ae 23F40023 		bic	r3, r3, #524288
+ 10199 00b2 C16C     		ldr	r1, [r0, #76]
+ 10200 00b4 0B43     		orrs	r3, r3, r1
+ 10201 00b6 5360     		str	r3, [r2, #4]
+ 10202              	.L487:
+3307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10203              		.loc 1 3307 1 is_stmt 0 view .LVU3404
+ 10204 00b8 7047     		bx	lr
+ 10205              	.L496:
+3296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ 10206              		.loc 1 3296 7 is_stmt 1 view .LVU3405
+3297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10207              		.loc 1 3297 7 view .LVU3406
+ 10208 00ba 0268     		ldr	r2, [r0]
+ 10209 00bc 5368     		ldr	r3, [r2, #4]
+ 10210 00be 23F4C003 		bic	r3, r3, #6291456
+ 10211 00c2 816C     		ldr	r1, [r0, #72]
+ 10212 00c4 0B43     		orrs	r3, r3, r1
+ 10213 00c6 5360     		str	r3, [r2, #4]
+ 10214 00c8 EBE7     		b	.L494
+ 10215              		.cfi_endproc
+ARM GAS  /tmp/cceWHrnJ.s 			page 334
+
+
+ 10216              	.LFE373:
+ 10218              		.section	.text.UART_WaitOnFlagUntilTimeout,"ax",%progbits
+ 10219              		.align	1
+ 10220              		.global	UART_WaitOnFlagUntilTimeout
+ 10221              		.syntax unified
+ 10222              		.thumb
+ 10223              		.thumb_func
+ 10225              	UART_WaitOnFlagUntilTimeout:
+ 10226              	.LVL912:
+ 10227              	.LFB375:
+3368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Wait until flag is set */
+ 10228              		.loc 1 3368 1 view -0
+ 10229              		.cfi_startproc
+ 10230              		@ args = 4, pretend = 0, frame = 0
+ 10231              		@ frame_needed = 0, uses_anonymous_args = 0
+3368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Wait until flag is set */
+ 10232              		.loc 1 3368 1 is_stmt 0 view .LVU3408
+ 10233 0000 2DE9F843 		push	{r3, r4, r5, r6, r7, r8, r9, lr}
+ 10234              	.LCFI32:
+ 10235              		.cfi_def_cfa_offset 32
+ 10236              		.cfi_offset 3, -32
+ 10237              		.cfi_offset 4, -28
+ 10238              		.cfi_offset 5, -24
+ 10239              		.cfi_offset 6, -20
+ 10240              		.cfi_offset 7, -16
+ 10241              		.cfi_offset 8, -12
+ 10242              		.cfi_offset 9, -8
+ 10243              		.cfi_offset 14, -4
+ 10244 0004 0546     		mov	r5, r0
+ 10245 0006 0F46     		mov	r7, r1
+ 10246 0008 1646     		mov	r6, r2
+ 10247 000a 9946     		mov	r9, r3
+ 10248 000c DDF82080 		ldr	r8, [sp, #32]
+3370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10249              		.loc 1 3370 3 is_stmt 1 view .LVU3409
+ 10250              	.LVL913:
+ 10251              	.L499:
+3370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10252              		.loc 1 3370 59 view .LVU3410
+3370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10253              		.loc 1 3370 11 is_stmt 0 view .LVU3411
+ 10254 0010 2B68     		ldr	r3, [r5]
+ 10255 0012 DC69     		ldr	r4, [r3, #28]
+3370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10256              		.loc 1 3370 50 view .LVU3412
+ 10257 0014 37EA0404 		bics	r4, r7, r4
+ 10258 0018 0CBF     		ite	eq
+ 10259 001a 0124     		moveq	r4, #1
+ 10260 001c 0024     		movne	r4, #0
+3370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10261              		.loc 1 3370 59 view .LVU3413
+ 10262 001e B442     		cmp	r4, r6
+ 10263 0020 57D1     		bne	.L509
+3373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10264              		.loc 1 3373 5 is_stmt 1 view .LVU3414
+3373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10265              		.loc 1 3373 8 is_stmt 0 view .LVU3415
+ARM GAS  /tmp/cceWHrnJ.s 			page 335
+
+
+ 10266 0022 B8F1FF3F 		cmp	r8, #-1
+ 10267 0026 F3D0     		beq	.L499
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10268              		.loc 1 3375 7 is_stmt 1 view .LVU3416
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10269              		.loc 1 3375 13 is_stmt 0 view .LVU3417
+ 10270 0028 FFF7FEFF 		bl	HAL_GetTick
+ 10271              	.LVL914:
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10272              		.loc 1 3375 27 view .LVU3418
+ 10273 002c A0EB0900 		sub	r0, r0, r9
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10274              		.loc 1 3375 10 view .LVU3419
+ 10275 0030 4045     		cmp	r0, r8
+ 10276 0032 2FD8     		bhi	.L502
+3375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10277              		.loc 1 3375 51 discriminator 1 view .LVU3420
+ 10278 0034 B8F1000F 		cmp	r8, #0
+ 10279 0038 2CD0     		beq	.L502
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10280              		.loc 1 3391 7 is_stmt 1 view .LVU3421
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10281              		.loc 1 3391 11 is_stmt 0 view .LVU3422
+ 10282 003a 2B68     		ldr	r3, [r5]
+ 10283 003c 1A68     		ldr	r2, [r3]
+3391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10284              		.loc 1 3391 10 view .LVU3423
+ 10285 003e 12F0040F 		tst	r2, #4
+ 10286 0042 E5D0     		beq	.L499
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 10287              		.loc 1 3393 9 is_stmt 1 view .LVU3424
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 10288              		.loc 1 3393 13 is_stmt 0 view .LVU3425
+ 10289 0044 DA69     		ldr	r2, [r3, #28]
+3393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         {
+ 10290              		.loc 1 3393 12 view .LVU3426
+ 10291 0046 12F4006F 		tst	r2, #2048
+ 10292 004a E1D0     		beq	.L499
+3396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10293              		.loc 1 3396 11 is_stmt 1 view .LVU3427
+ 10294 004c 4FF40062 		mov	r2, #2048
+ 10295 0050 1A62     		str	r2, [r3, #32]
+ 10296              	.L505:
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                   USART_CR1_TXEIE_TXFNFIE));
+ 10297              		.loc 1 3400 11 discriminator 1 view .LVU3428
+ 10298              	.LBB936:
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                   USART_CR1_TXEIE_TXFNFIE));
+ 10299              		.loc 1 3400 11 discriminator 1 view .LVU3429
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                   USART_CR1_TXEIE_TXFNFIE));
+ 10300              		.loc 1 3400 11 discriminator 1 view .LVU3430
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                   USART_CR1_TXEIE_TXFNFIE));
+ 10301              		.loc 1 3400 11 discriminator 1 view .LVU3431
+ 10302 0052 2A68     		ldr	r2, [r5]
+ 10303              	.LVL915:
+ 10304              	.LBB937:
+ 10305              	.LBI937:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/cceWHrnJ.s 			page 336
+
+
+ 10306              		.loc 2 1151 31 discriminator 1 view .LVU3432
+ 10307              	.LBB938:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 10308              		.loc 2 1153 5 discriminator 1 view .LVU3433
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 10309              		.loc 2 1155 4 discriminator 1 view .LVU3434
+ 10310              		.syntax unified
+ 10311              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 10312 0054 52E8003F 		ldrex r3, [r2]
+ 10313              	@ 0 "" 2
+ 10314              	.LVL916:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 10315              		.loc 2 1156 4 discriminator 1 view .LVU3435
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 10316              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU3436
+ 10317              		.thumb
+ 10318              		.syntax unified
+ 10319              	.LBE938:
+ 10320              	.LBE937:
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                   USART_CR1_TXEIE_TXFNFIE));
+ 10321              		.loc 1 3400 11 discriminator 1 view .LVU3437
+ 10322 0058 23F4D073 		bic	r3, r3, #416
+ 10323              	.LVL917:
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                   USART_CR1_TXEIE_TXFNFIE));
+ 10324              		.loc 1 3400 11 is_stmt 1 discriminator 1 view .LVU3438
+ 10325              	.LBB939:
+ 10326              	.LBI939:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 10327              		.loc 2 1202 31 discriminator 1 view .LVU3439
+ 10328              	.LBB940:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 10329              		.loc 2 1204 4 discriminator 1 view .LVU3440
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 10330              		.loc 2 1206 4 discriminator 1 view .LVU3441
+ 10331              		.syntax unified
+ 10332              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 10333 005c 42E80031 		strex r1, r3, [r2]
+ 10334              	@ 0 "" 2
+ 10335              	.LVL918:
+ 10336              		.loc 2 1207 4 discriminator 1 view .LVU3442
+ 10337              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU3443
+ 10338              		.thumb
+ 10339              		.syntax unified
+ 10340              	.LBE940:
+ 10341              	.LBE939:
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                   USART_CR1_TXEIE_TXFNFIE));
+ 10342              		.loc 1 3400 11 discriminator 1 view .LVU3444
+ 10343 0060 0029     		cmp	r1, #0
+ 10344 0062 F6D1     		bne	.L505
+ 10345              	.LVL919:
+ 10346              	.L506:
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                   USART_CR1_TXEIE_TXFNFIE));
+ 10347              		.loc 1 3400 11 discriminator 1 view .LVU3445
+ 10348              	.LBE936:
+3400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                   USART_CR1_TXEIE_TXFNFIE));
+ 10349              		.loc 1 3400 11 is_stmt 1 discriminator 1 view .LVU3446
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 337
+
+
+ 10350              		.loc 1 3402 11 discriminator 1 view .LVU3447
+ 10351              	.LBB941:
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10352              		.loc 1 3402 11 discriminator 1 view .LVU3448
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10353              		.loc 1 3402 11 discriminator 1 view .LVU3449
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10354              		.loc 1 3402 11 discriminator 1 view .LVU3450
+ 10355 0064 2A68     		ldr	r2, [r5]
+ 10356              	.LVL920:
+ 10357              	.LBB942:
+ 10358              	.LBI942:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 10359              		.loc 2 1151 31 discriminator 1 view .LVU3451
+ 10360              	.LBB943:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 10361              		.loc 2 1153 5 discriminator 1 view .LVU3452
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 10362              		.loc 2 1155 4 discriminator 1 view .LVU3453
+ 10363 0066 02F10803 		add	r3, r2, #8
+ 10364              	.LVL921:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 10365              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU3454
+ 10366              		.syntax unified
+ 10367              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 10368 006a 53E8003F 		ldrex r3, [r3]
+ 10369              	@ 0 "" 2
+ 10370              	.LVL922:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 10371              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU3455
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 10372              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU3456
+ 10373              		.thumb
+ 10374              		.syntax unified
+ 10375              	.LBE943:
+ 10376              	.LBE942:
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10377              		.loc 1 3402 11 discriminator 1 view .LVU3457
+ 10378 006e 23F00103 		bic	r3, r3, #1
+ 10379              	.LVL923:
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10380              		.loc 1 3402 11 is_stmt 1 discriminator 1 view .LVU3458
+ 10381              	.LBB944:
+ 10382              	.LBI944:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 10383              		.loc 2 1202 31 discriminator 1 view .LVU3459
+ 10384              	.LBB945:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 10385              		.loc 2 1204 4 discriminator 1 view .LVU3460
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 10386              		.loc 2 1206 4 discriminator 1 view .LVU3461
+ 10387 0072 0832     		adds	r2, r2, #8
+ 10388              	.LVL924:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 10389              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU3462
+ 10390              		.syntax unified
+ 10391              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ARM GAS  /tmp/cceWHrnJ.s 			page 338
+
+
+ 10392 0074 42E80031 		strex r1, r3, [r2]
+ 10393              	@ 0 "" 2
+ 10394              	.LVL925:
+ 10395              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU3463
+ 10396              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU3464
+ 10397              		.thumb
+ 10398              		.syntax unified
+ 10399              	.LBE945:
+ 10400              	.LBE944:
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10401              		.loc 1 3402 11 discriminator 1 view .LVU3465
+ 10402 0078 0029     		cmp	r1, #0
+ 10403 007a F3D1     		bne	.L506
+ 10404              	.LBE941:
+3402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10405              		.loc 1 3402 11 is_stmt 1 discriminator 2 view .LVU3466
+3404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->RxState = HAL_UART_STATE_READY;
+ 10406              		.loc 1 3404 11 discriminator 2 view .LVU3467
+3404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->RxState = HAL_UART_STATE_READY;
+ 10407              		.loc 1 3404 25 is_stmt 0 discriminator 2 view .LVU3468
+ 10408 007c 2023     		movs	r3, #32
+ 10409              	.LVL926:
+3404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->RxState = HAL_UART_STATE_READY;
+ 10410              		.loc 1 3404 25 discriminator 2 view .LVU3469
+ 10411 007e C5F88430 		str	r3, [r5, #132]
+3405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode = HAL_UART_ERROR_RTO;
+ 10412              		.loc 1 3405 11 is_stmt 1 discriminator 2 view .LVU3470
+3405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****           huart->ErrorCode = HAL_UART_ERROR_RTO;
+ 10413              		.loc 1 3405 26 is_stmt 0 discriminator 2 view .LVU3471
+ 10414 0082 C5F88830 		str	r3, [r5, #136]
+3406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10415              		.loc 1 3406 11 is_stmt 1 discriminator 2 view .LVU3472
+3406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10416              		.loc 1 3406 28 is_stmt 0 discriminator 2 view .LVU3473
+ 10417 0086 C5F88C30 		str	r3, [r5, #140]
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10418              		.loc 1 3409 11 is_stmt 1 discriminator 2 view .LVU3474
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10419              		.loc 1 3409 11 discriminator 2 view .LVU3475
+ 10420 008a 0023     		movs	r3, #0
+ 10421 008c 85F88030 		strb	r3, [r5, #128]
+3409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10422              		.loc 1 3409 11 discriminator 2 view .LVU3476
+3411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 10423              		.loc 1 3411 11 discriminator 2 view .LVU3477
+3411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         }
+ 10424              		.loc 1 3411 18 is_stmt 0 discriminator 2 view .LVU3478
+ 10425 0090 0320     		movs	r0, #3
+ 10426 0092 1FE0     		b	.L504
+ 10427              	.LVL927:
+ 10428              	.L502:
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                 USART_CR1_TXEIE_TXFNFIE));
+ 10429              		.loc 1 3379 9 is_stmt 1 discriminator 1 view .LVU3479
+ 10430              	.LBB946:
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                 USART_CR1_TXEIE_TXFNFIE));
+ 10431              		.loc 1 3379 9 discriminator 1 view .LVU3480
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                 USART_CR1_TXEIE_TXFNFIE));
+ARM GAS  /tmp/cceWHrnJ.s 			page 339
+
+
+ 10432              		.loc 1 3379 9 discriminator 1 view .LVU3481
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                 USART_CR1_TXEIE_TXFNFIE));
+ 10433              		.loc 1 3379 9 discriminator 1 view .LVU3482
+ 10434 0094 2A68     		ldr	r2, [r5]
+ 10435              	.LVL928:
+ 10436              	.LBB947:
+ 10437              	.LBI947:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 10438              		.loc 2 1151 31 discriminator 1 view .LVU3483
+ 10439              	.LBB948:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 10440              		.loc 2 1153 5 discriminator 1 view .LVU3484
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 10441              		.loc 2 1155 4 discriminator 1 view .LVU3485
+ 10442              		.syntax unified
+ 10443              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 10444 0096 52E8003F 		ldrex r3, [r2]
+ 10445              	@ 0 "" 2
+ 10446              	.LVL929:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 10447              		.loc 2 1156 4 discriminator 1 view .LVU3486
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 10448              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU3487
+ 10449              		.thumb
+ 10450              		.syntax unified
+ 10451              	.LBE948:
+ 10452              	.LBE947:
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                 USART_CR1_TXEIE_TXFNFIE));
+ 10453              		.loc 1 3379 9 discriminator 1 view .LVU3488
+ 10454 009a 23F4D073 		bic	r3, r3, #416
+ 10455              	.LVL930:
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                 USART_CR1_TXEIE_TXFNFIE));
+ 10456              		.loc 1 3379 9 is_stmt 1 discriminator 1 view .LVU3489
+ 10457              	.LBB949:
+ 10458              	.LBI949:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 10459              		.loc 2 1202 31 discriminator 1 view .LVU3490
+ 10460              	.LBB950:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 10461              		.loc 2 1204 4 discriminator 1 view .LVU3491
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 10462              		.loc 2 1206 4 discriminator 1 view .LVU3492
+ 10463              		.syntax unified
+ 10464              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 10465 009e 42E80031 		strex r1, r3, [r2]
+ 10466              	@ 0 "" 2
+ 10467              	.LVL931:
+ 10468              		.loc 2 1207 4 discriminator 1 view .LVU3493
+ 10469              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU3494
+ 10470              		.thumb
+ 10471              		.syntax unified
+ 10472              	.LBE950:
+ 10473              	.LBE949:
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                 USART_CR1_TXEIE_TXFNFIE));
+ 10474              		.loc 1 3379 9 discriminator 1 view .LVU3495
+ 10475 00a2 0029     		cmp	r1, #0
+ 10476 00a4 F6D1     		bne	.L502
+ARM GAS  /tmp/cceWHrnJ.s 			page 340
+
+
+ 10477              	.LVL932:
+ 10478              	.L503:
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                 USART_CR1_TXEIE_TXFNFIE));
+ 10479              		.loc 1 3379 9 discriminator 1 view .LVU3496
+ 10480              	.LBE946:
+3379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****                                                 USART_CR1_TXEIE_TXFNFIE));
+ 10481              		.loc 1 3379 9 is_stmt 1 discriminator 1 view .LVU3497
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10482              		.loc 1 3381 9 discriminator 1 view .LVU3498
+ 10483              	.LBB951:
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10484              		.loc 1 3381 9 discriminator 1 view .LVU3499
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10485              		.loc 1 3381 9 discriminator 1 view .LVU3500
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10486              		.loc 1 3381 9 discriminator 1 view .LVU3501
+ 10487 00a6 2A68     		ldr	r2, [r5]
+ 10488              	.LVL933:
+ 10489              	.LBB952:
+ 10490              	.LBI952:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 10491              		.loc 2 1151 31 discriminator 1 view .LVU3502
+ 10492              	.LBB953:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 10493              		.loc 2 1153 5 discriminator 1 view .LVU3503
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 10494              		.loc 2 1155 4 discriminator 1 view .LVU3504
+ 10495 00a8 02F10803 		add	r3, r2, #8
+ 10496              	.LVL934:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 10497              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU3505
+ 10498              		.syntax unified
+ 10499              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 10500 00ac 53E8003F 		ldrex r3, [r3]
+ 10501              	@ 0 "" 2
+ 10502              	.LVL935:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 10503              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU3506
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 10504              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU3507
+ 10505              		.thumb
+ 10506              		.syntax unified
+ 10507              	.LBE953:
+ 10508              	.LBE952:
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10509              		.loc 1 3381 9 discriminator 1 view .LVU3508
+ 10510 00b0 23F00103 		bic	r3, r3, #1
+ 10511              	.LVL936:
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10512              		.loc 1 3381 9 is_stmt 1 discriminator 1 view .LVU3509
+ 10513              	.LBB954:
+ 10514              	.LBI954:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 10515              		.loc 2 1202 31 discriminator 1 view .LVU3510
+ 10516              	.LBB955:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 10517              		.loc 2 1204 4 discriminator 1 view .LVU3511
+ARM GAS  /tmp/cceWHrnJ.s 			page 341
+
+
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 10518              		.loc 2 1206 4 discriminator 1 view .LVU3512
+ 10519 00b4 0832     		adds	r2, r2, #8
+ 10520              	.LVL937:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 10521              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU3513
+ 10522              		.syntax unified
+ 10523              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 10524 00b6 42E80031 		strex r1, r3, [r2]
+ 10525              	@ 0 "" 2
+ 10526              	.LVL938:
+ 10527              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU3514
+ 10528              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU3515
+ 10529              		.thumb
+ 10530              		.syntax unified
+ 10531              	.LBE955:
+ 10532              	.LBE954:
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10533              		.loc 1 3381 9 discriminator 1 view .LVU3516
+ 10534 00ba 0029     		cmp	r1, #0
+ 10535 00bc F3D1     		bne	.L503
+ 10536              	.LBE951:
+3381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10537              		.loc 1 3381 9 is_stmt 1 discriminator 2 view .LVU3517
+3383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxState = HAL_UART_STATE_READY;
+ 10538              		.loc 1 3383 9 discriminator 2 view .LVU3518
+3383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxState = HAL_UART_STATE_READY;
+ 10539              		.loc 1 3383 23 is_stmt 0 discriminator 2 view .LVU3519
+ 10540 00be 2023     		movs	r3, #32
+ 10541              	.LVL939:
+3383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         huart->RxState = HAL_UART_STATE_READY;
+ 10542              		.loc 1 3383 23 discriminator 2 view .LVU3520
+ 10543 00c0 C5F88430 		str	r3, [r5, #132]
+3384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10544              		.loc 1 3384 9 is_stmt 1 discriminator 2 view .LVU3521
+3384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10545              		.loc 1 3384 24 is_stmt 0 discriminator 2 view .LVU3522
+ 10546 00c4 C5F88830 		str	r3, [r5, #136]
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10547              		.loc 1 3386 9 is_stmt 1 discriminator 2 view .LVU3523
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10548              		.loc 1 3386 9 discriminator 2 view .LVU3524
+ 10549 00c8 0023     		movs	r3, #0
+ 10550 00ca 85F88030 		strb	r3, [r5, #128]
+3386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10551              		.loc 1 3386 9 discriminator 2 view .LVU3525
+3388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 10552              		.loc 1 3388 9 discriminator 2 view .LVU3526
+3388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 10553              		.loc 1 3388 16 is_stmt 0 discriminator 2 view .LVU3527
+ 10554 00ce 0320     		movs	r0, #3
+ 10555 00d0 00E0     		b	.L504
+ 10556              	.LVL940:
+ 10557              	.L509:
+3416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 10558              		.loc 1 3416 10 view .LVU3528
+ 10559 00d2 0020     		movs	r0, #0
+ARM GAS  /tmp/cceWHrnJ.s 			page 342
+
+
+ 10560              	.L504:
+3417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10561              		.loc 1 3417 1 view .LVU3529
+ 10562 00d4 BDE8F883 		pop	{r3, r4, r5, r6, r7, r8, r9, pc}
+3417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10563              		.loc 1 3417 1 view .LVU3530
+ 10564              		.cfi_endproc
+ 10565              	.LFE375:
+ 10567              		.section	.text.HAL_UART_Transmit,"ax",%progbits
+ 10568              		.align	1
+ 10569              		.global	HAL_UART_Transmit
+ 10570              		.syntax unified
+ 10571              		.thumb
+ 10572              		.thumb_func
+ 10574              	HAL_UART_Transmit:
+ 10575              	.LVL941:
+ 10576              	.LFB336:
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const uint8_t  *pdata8bits;
+ 10577              		.loc 1 1122 1 is_stmt 1 view -0
+ 10578              		.cfi_startproc
+ 10579              		@ args = 0, pretend = 0, frame = 0
+ 10580              		@ frame_needed = 0, uses_anonymous_args = 0
+1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const uint8_t  *pdata8bits;
+ 10581              		.loc 1 1122 1 is_stmt 0 view .LVU3532
+ 10582 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 10583              	.LCFI33:
+ 10584              		.cfi_def_cfa_offset 24
+ 10585              		.cfi_offset 4, -24
+ 10586              		.cfi_offset 5, -20
+ 10587              		.cfi_offset 6, -16
+ 10588              		.cfi_offset 7, -12
+ 10589              		.cfi_offset 8, -8
+ 10590              		.cfi_offset 14, -4
+ 10591 0004 82B0     		sub	sp, sp, #8
+ 10592              	.LCFI34:
+ 10593              		.cfi_def_cfa_offset 32
+ 10594 0006 1E46     		mov	r6, r3
+1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   const uint16_t *pdata16bits;
+ 10595              		.loc 1 1123 3 is_stmt 1 view .LVU3533
+1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t tickstart;
+ 10596              		.loc 1 1124 3 view .LVU3534
+1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10597              		.loc 1 1125 3 view .LVU3535
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10598              		.loc 1 1128 3 view .LVU3536
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10599              		.loc 1 1128 12 is_stmt 0 view .LVU3537
+ 10600 0008 D0F88430 		ldr	r3, [r0, #132]
+ 10601              	.LVL942:
+1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10602              		.loc 1 1128 6 view .LVU3538
+ 10603 000c 202B     		cmp	r3, #32
+ 10604 000e 58D1     		bne	.L517
+ 10605 0010 0446     		mov	r4, r0
+ 10606 0012 0D46     		mov	r5, r1
+ 10607 0014 9046     		mov	r8, r2
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ARM GAS  /tmp/cceWHrnJ.s 			page 343
+
+
+ 10608              		.loc 1 1130 5 is_stmt 1 view .LVU3539
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10609              		.loc 1 1130 8 is_stmt 0 view .LVU3540
+ 10610 0016 0029     		cmp	r1, #0
+ 10611 0018 57D0     		beq	.L518
+1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10612              		.loc 1 1130 25 discriminator 1 view .LVU3541
+ 10613 001a 002A     		cmp	r2, #0
+ 10614 001c 57D0     		beq	.L519
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10615              		.loc 1 1135 5 is_stmt 1 view .LVU3542
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10616              		.loc 1 1135 5 view .LVU3543
+ 10617 001e 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 10618 0022 012B     		cmp	r3, #1
+ 10619 0024 55D0     		beq	.L520
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10620              		.loc 1 1135 5 discriminator 2 view .LVU3544
+ 10621 0026 0123     		movs	r3, #1
+ 10622 0028 80F88030 		strb	r3, [r0, #128]
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10623              		.loc 1 1135 5 discriminator 2 view .LVU3545
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->gState = HAL_UART_STATE_BUSY_TX;
+ 10624              		.loc 1 1137 5 discriminator 2 view .LVU3546
+1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->gState = HAL_UART_STATE_BUSY_TX;
+ 10625              		.loc 1 1137 22 is_stmt 0 discriminator 2 view .LVU3547
+ 10626 002c 0023     		movs	r3, #0
+ 10627 002e C0F88C30 		str	r3, [r0, #140]
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10628              		.loc 1 1138 5 is_stmt 1 discriminator 2 view .LVU3548
+1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10629              		.loc 1 1138 19 is_stmt 0 discriminator 2 view .LVU3549
+ 10630 0032 2123     		movs	r3, #33
+ 10631 0034 C0F88430 		str	r3, [r0, #132]
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10632              		.loc 1 1141 5 is_stmt 1 discriminator 2 view .LVU3550
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10633              		.loc 1 1141 17 is_stmt 0 discriminator 2 view .LVU3551
+ 10634 0038 FFF7FEFF 		bl	HAL_GetTick
+ 10635              	.LVL943:
+1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10636              		.loc 1 1141 17 discriminator 2 view .LVU3552
+ 10637 003c 0746     		mov	r7, r0
+ 10638              	.LVL944:
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = Size;
+ 10639              		.loc 1 1143 5 is_stmt 1 discriminator 2 view .LVU3553
+1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->TxXferCount = Size;
+ 10640              		.loc 1 1143 24 is_stmt 0 discriminator 2 view .LVU3554
+ 10641 003e A4F85480 		strh	r8, [r4, #84]	@ movhi
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10642              		.loc 1 1144 5 is_stmt 1 discriminator 2 view .LVU3555
+1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10643              		.loc 1 1144 24 is_stmt 0 discriminator 2 view .LVU3556
+ 10644 0042 A4F85680 		strh	r8, [r4, #86]	@ movhi
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10645              		.loc 1 1147 5 is_stmt 1 discriminator 2 view .LVU3557
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ARM GAS  /tmp/cceWHrnJ.s 			page 344
+
+
+ 10646              		.loc 1 1147 21 is_stmt 0 discriminator 2 view .LVU3558
+ 10647 0046 A368     		ldr	r3, [r4, #8]
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10648              		.loc 1 1147 8 discriminator 2 view .LVU3559
+ 10649 0048 B3F5805F 		cmp	r3, #4096
+ 10650 004c 05D0     		beq	.L526
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10651              		.loc 1 1155 19 view .LVU3560
+ 10652 004e 4FF00008 		mov	r8, #0
+ 10653              	.LVL945:
+ 10654              	.L512:
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10655              		.loc 1 1158 5 is_stmt 1 view .LVU3561
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10656              		.loc 1 1158 5 view .LVU3562
+ 10657 0052 0023     		movs	r3, #0
+ 10658 0054 84F88030 		strb	r3, [r4, #128]
+1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10659              		.loc 1 1158 5 view .LVU3563
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10660              		.loc 1 1160 5 view .LVU3564
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10661              		.loc 1 1160 11 is_stmt 0 view .LVU3565
+ 10662 0058 14E0     		b	.L513
+ 10663              	.LVL946:
+ 10664              	.L526:
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10665              		.loc 1 1147 71 discriminator 1 view .LVU3566
+ 10666 005a 2369     		ldr	r3, [r4, #16]
+1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10667              		.loc 1 1147 56 discriminator 1 view .LVU3567
+ 10668 005c 13B1     		cbz	r3, .L522
+1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10669              		.loc 1 1155 19 view .LVU3568
+ 10670 005e 4FF00008 		mov	r8, #0
+ 10671 0062 F6E7     		b	.L512
+ 10672              	.L522:
+1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10673              		.loc 1 1150 19 view .LVU3569
+ 10674 0064 A846     		mov	r8, r5
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       pdata16bits = (const uint16_t *) pData;
+ 10675              		.loc 1 1149 19 view .LVU3570
+ 10676 0066 0025     		movs	r5, #0
+ 10677              	.LVL947:
+1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       pdata16bits = (const uint16_t *) pData;
+ 10678              		.loc 1 1149 19 view .LVU3571
+ 10679 0068 F3E7     		b	.L512
+ 10680              	.LVL948:
+ 10681              	.L528:
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata16bits++;
+ 10682              		.loc 1 1168 9 is_stmt 1 view .LVU3572
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata16bits++;
+ 10683              		.loc 1 1168 43 is_stmt 0 view .LVU3573
+ 10684 006a 38F8023B 		ldrh	r3, [r8], #2
+ 10685              	.LVL949:
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata16bits++;
+ 10686              		.loc 1 1168 14 view .LVU3574
+ARM GAS  /tmp/cceWHrnJ.s 			page 345
+
+
+ 10687 006e 2268     		ldr	r2, [r4]
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata16bits++;
+ 10688              		.loc 1 1168 32 view .LVU3575
+ 10689 0070 C3F30803 		ubfx	r3, r3, #0, #9
+1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata16bits++;
+ 10690              		.loc 1 1168 30 view .LVU3576
+ 10691 0074 9362     		str	r3, [r2, #40]
+1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 10692              		.loc 1 1169 9 is_stmt 1 view .LVU3577
+ 10693              	.LVL950:
+ 10694              	.L515:
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10695              		.loc 1 1176 7 view .LVU3578
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10696              		.loc 1 1176 12 is_stmt 0 view .LVU3579
+ 10697 0076 B4F85620 		ldrh	r2, [r4, #86]
+ 10698 007a 92B2     		uxth	r2, r2
+1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10699              		.loc 1 1176 25 view .LVU3580
+ 10700 007c 013A     		subs	r2, r2, #1
+ 10701 007e 92B2     		uxth	r2, r2
+ 10702 0080 A4F85620 		strh	r2, [r4, #86]	@ movhi
+ 10703              	.L513:
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10704              		.loc 1 1160 31 is_stmt 1 view .LVU3581
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10705              		.loc 1 1160 17 is_stmt 0 view .LVU3582
+ 10706 0084 B4F85630 		ldrh	r3, [r4, #86]
+ 10707 0088 9BB2     		uxth	r3, r3
+1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10708              		.loc 1 1160 31 view .LVU3583
+ 10709 008a 73B1     		cbz	r3, .L527
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10710              		.loc 1 1162 7 is_stmt 1 view .LVU3584
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10711              		.loc 1 1162 11 is_stmt 0 view .LVU3585
+ 10712 008c 0096     		str	r6, [sp]
+ 10713 008e 3B46     		mov	r3, r7
+ 10714 0090 0022     		movs	r2, #0
+ 10715 0092 8021     		movs	r1, #128
+ 10716 0094 2046     		mov	r0, r4
+ 10717 0096 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 10718              	.LVL951:
+1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10719              		.loc 1 1162 10 view .LVU3586
+ 10720 009a E0B9     		cbnz	r0, .L523
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10721              		.loc 1 1166 7 is_stmt 1 view .LVU3587
+1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 10722              		.loc 1 1166 10 is_stmt 0 view .LVU3588
+ 10723 009c 002D     		cmp	r5, #0
+ 10724 009e E4D0     		beq	.L528
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata8bits++;
+ 10725              		.loc 1 1173 9 is_stmt 1 view .LVU3589
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata8bits++;
+ 10726              		.loc 1 1173 42 is_stmt 0 view .LVU3590
+ 10727 00a0 15F8012B 		ldrb	r2, [r5], #1	@ zero_extendqisi2
+ARM GAS  /tmp/cceWHrnJ.s 			page 346
+
+
+ 10728              	.LVL952:
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata8bits++;
+ 10729              		.loc 1 1173 14 view .LVU3591
+ 10730 00a4 2368     		ldr	r3, [r4]
+1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata8bits++;
+ 10731              		.loc 1 1173 30 view .LVU3592
+ 10732 00a6 9A62     		str	r2, [r3, #40]
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 10733              		.loc 1 1174 9 is_stmt 1 view .LVU3593
+ 10734              	.LVL953:
+1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 10735              		.loc 1 1174 9 is_stmt 0 view .LVU3594
+ 10736 00a8 E5E7     		b	.L515
+ 10737              	.L527:
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10738              		.loc 1 1179 5 is_stmt 1 view .LVU3595
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10739              		.loc 1 1179 9 is_stmt 0 view .LVU3596
+ 10740 00aa 0096     		str	r6, [sp]
+ 10741 00ac 3B46     		mov	r3, r7
+ 10742 00ae 0022     		movs	r2, #0
+ 10743 00b0 4021     		movs	r1, #64
+ 10744 00b2 2046     		mov	r0, r4
+ 10745 00b4 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 10746              	.LVL954:
+1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10747              		.loc 1 1179 8 view .LVU3597
+ 10748 00b8 78B9     		cbnz	r0, .L524
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10749              		.loc 1 1185 5 is_stmt 1 view .LVU3598
+1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10750              		.loc 1 1185 19 is_stmt 0 view .LVU3599
+ 10751 00ba 2023     		movs	r3, #32
+ 10752 00bc C4F88430 		str	r3, [r4, #132]
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 10753              		.loc 1 1187 5 is_stmt 1 view .LVU3600
+1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 10754              		.loc 1 1187 12 is_stmt 0 view .LVU3601
+ 10755 00c0 00E0     		b	.L511
+ 10756              	.LVL955:
+ 10757              	.L517:
+1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 10758              		.loc 1 1191 12 view .LVU3602
+ 10759 00c2 0220     		movs	r0, #2
+ 10760              	.LVL956:
+ 10761              	.L511:
+1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10762              		.loc 1 1193 1 view .LVU3603
+ 10763 00c4 02B0     		add	sp, sp, #8
+ 10764              	.LCFI35:
+ 10765              		.cfi_remember_state
+ 10766              		.cfi_def_cfa_offset 24
+ 10767              		@ sp needed
+ 10768 00c6 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 10769              	.LVL957:
+ 10770              	.L518:
+ 10771              	.LCFI36:
+ARM GAS  /tmp/cceWHrnJ.s 			page 347
+
+
+ 10772              		.cfi_restore_state
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10773              		.loc 1 1132 15 view .LVU3604
+ 10774 00ca 0120     		movs	r0, #1
+ 10775              	.LVL958:
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10776              		.loc 1 1132 15 view .LVU3605
+ 10777 00cc FAE7     		b	.L511
+ 10778              	.LVL959:
+ 10779              	.L519:
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10780              		.loc 1 1132 15 view .LVU3606
+ 10781 00ce 0120     		movs	r0, #1
+ 10782              	.LVL960:
+1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10783              		.loc 1 1132 15 view .LVU3607
+ 10784 00d0 F8E7     		b	.L511
+ 10785              	.LVL961:
+ 10786              	.L520:
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10787              		.loc 1 1135 5 view .LVU3608
+ 10788 00d2 0220     		movs	r0, #2
+ 10789              	.LVL962:
+1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10790              		.loc 1 1135 5 view .LVU3609
+ 10791 00d4 F6E7     		b	.L511
+ 10792              	.LVL963:
+ 10793              	.L523:
+1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 10794              		.loc 1 1164 16 view .LVU3610
+ 10795 00d6 0320     		movs	r0, #3
+ 10796 00d8 F4E7     		b	.L511
+ 10797              	.L524:
+1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10798              		.loc 1 1181 14 view .LVU3611
+ 10799 00da 0320     		movs	r0, #3
+ 10800 00dc F2E7     		b	.L511
+ 10801              		.cfi_endproc
+ 10802              	.LFE336:
+ 10804              		.section	.text.HAL_UART_Receive,"ax",%progbits
+ 10805              		.align	1
+ 10806              		.global	HAL_UART_Receive
+ 10807              		.syntax unified
+ 10808              		.thumb
+ 10809              		.thumb_func
+ 10811              	HAL_UART_Receive:
+ 10812              	.LVL964:
+ 10813              	.LFB337:
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint8_t  *pdata8bits;
+ 10814              		.loc 1 1211 1 is_stmt 1 view -0
+ 10815              		.cfi_startproc
+ 10816              		@ args = 0, pretend = 0, frame = 0
+ 10817              		@ frame_needed = 0, uses_anonymous_args = 0
+1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint8_t  *pdata8bits;
+ 10818              		.loc 1 1211 1 is_stmt 0 view .LVU3613
+ 10819 0000 2DE9F043 		push	{r4, r5, r6, r7, r8, r9, lr}
+ 10820              	.LCFI37:
+ARM GAS  /tmp/cceWHrnJ.s 			page 348
+
+
+ 10821              		.cfi_def_cfa_offset 28
+ 10822              		.cfi_offset 4, -28
+ 10823              		.cfi_offset 5, -24
+ 10824              		.cfi_offset 6, -20
+ 10825              		.cfi_offset 7, -16
+ 10826              		.cfi_offset 8, -12
+ 10827              		.cfi_offset 9, -8
+ 10828              		.cfi_offset 14, -4
+ 10829 0004 83B0     		sub	sp, sp, #12
+ 10830              	.LCFI38:
+ 10831              		.cfi_def_cfa_offset 40
+ 10832 0006 1E46     		mov	r6, r3
+1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t *pdata16bits;
+ 10833              		.loc 1 1212 3 is_stmt 1 view .LVU3614
+1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint16_t uhMask;
+ 10834              		.loc 1 1213 3 view .LVU3615
+1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t tickstart;
+ 10835              		.loc 1 1214 3 view .LVU3616
+1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10836              		.loc 1 1215 3 view .LVU3617
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10837              		.loc 1 1218 3 view .LVU3618
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10838              		.loc 1 1218 12 is_stmt 0 view .LVU3619
+ 10839 0008 D0F88830 		ldr	r3, [r0, #136]
+ 10840              	.LVL965:
+1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 10841              		.loc 1 1218 6 view .LVU3620
+ 10842 000c 202B     		cmp	r3, #32
+ 10843 000e 40F08180 		bne	.L543
+ 10844 0012 0446     		mov	r4, r0
+ 10845 0014 0D46     		mov	r5, r1
+ 10846 0016 9046     		mov	r8, r2
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10847              		.loc 1 1220 5 is_stmt 1 view .LVU3621
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10848              		.loc 1 1220 8 is_stmt 0 view .LVU3622
+ 10849 0018 0029     		cmp	r1, #0
+ 10850 001a 7FD0     		beq	.L544
+1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10851              		.loc 1 1220 25 discriminator 1 view .LVU3623
+ 10852 001c 002A     		cmp	r2, #0
+ 10853 001e 7FD0     		beq	.L545
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10854              		.loc 1 1225 5 is_stmt 1 view .LVU3624
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10855              		.loc 1 1225 5 view .LVU3625
+ 10856 0020 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 10857 0024 012B     		cmp	r3, #1
+ 10858 0026 7DD0     		beq	.L546
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10859              		.loc 1 1225 5 discriminator 2 view .LVU3626
+ 10860 0028 0123     		movs	r3, #1
+ 10861 002a 80F88030 		strb	r3, [r0, #128]
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10862              		.loc 1 1225 5 discriminator 2 view .LVU3627
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxState = HAL_UART_STATE_BUSY_RX;
+ARM GAS  /tmp/cceWHrnJ.s 			page 349
+
+
+ 10863              		.loc 1 1227 5 discriminator 2 view .LVU3628
+1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 10864              		.loc 1 1227 22 is_stmt 0 discriminator 2 view .LVU3629
+ 10865 002e 0023     		movs	r3, #0
+ 10866 0030 C0F88C30 		str	r3, [r0, #140]
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 10867              		.loc 1 1228 5 is_stmt 1 discriminator 2 view .LVU3630
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 10868              		.loc 1 1228 20 is_stmt 0 discriminator 2 view .LVU3631
+ 10869 0034 2222     		movs	r2, #34
+ 10870              	.LVL966:
+1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 10871              		.loc 1 1228 20 discriminator 2 view .LVU3632
+ 10872 0036 C0F88820 		str	r2, [r0, #136]
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10873              		.loc 1 1229 5 is_stmt 1 discriminator 2 view .LVU3633
+1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10874              		.loc 1 1229 26 is_stmt 0 discriminator 2 view .LVU3634
+ 10875 003a C366     		str	r3, [r0, #108]
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10876              		.loc 1 1232 5 is_stmt 1 discriminator 2 view .LVU3635
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10877              		.loc 1 1232 17 is_stmt 0 discriminator 2 view .LVU3636
+ 10878 003c FFF7FEFF 		bl	HAL_GetTick
+ 10879              	.LVL967:
+1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10880              		.loc 1 1232 17 discriminator 2 view .LVU3637
+ 10881 0040 0746     		mov	r7, r0
+ 10882              	.LVL968:
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount = Size;
+ 10883              		.loc 1 1234 5 is_stmt 1 discriminator 2 view .LVU3638
+1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     huart->RxXferCount = Size;
+ 10884              		.loc 1 1234 24 is_stmt 0 discriminator 2 view .LVU3639
+ 10885 0042 A4F85C80 		strh	r8, [r4, #92]	@ movhi
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10886              		.loc 1 1235 5 is_stmt 1 discriminator 2 view .LVU3640
+1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10887              		.loc 1 1235 24 is_stmt 0 discriminator 2 view .LVU3641
+ 10888 0046 A4F85E80 		strh	r8, [r4, #94]	@ movhi
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10889              		.loc 1 1238 5 is_stmt 1 discriminator 2 view .LVU3642
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10890              		.loc 1 1238 5 discriminator 2 view .LVU3643
+ 10891 004a A368     		ldr	r3, [r4, #8]
+ 10892 004c B3F5805F 		cmp	r3, #4096
+ 10893 0050 06D0     		beq	.L551
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10894              		.loc 1 1238 5 discriminator 2 view .LVU3644
+ 10895 0052 A3B9     		cbnz	r3, .L534
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10896              		.loc 1 1238 5 discriminator 5 view .LVU3645
+ 10897 0054 2269     		ldr	r2, [r4, #16]
+ 10898 0056 72B9     		cbnz	r2, .L535
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10899              		.loc 1 1238 5 discriminator 7 view .LVU3646
+ 10900 0058 FF22     		movs	r2, #255
+ 10901 005a A4F86020 		strh	r2, [r4, #96]	@ movhi
+ARM GAS  /tmp/cceWHrnJ.s 			page 350
+
+
+ 10902 005e 14E0     		b	.L533
+ 10903              	.L551:
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10904              		.loc 1 1238 5 discriminator 1 view .LVU3647
+ 10905 0060 2269     		ldr	r2, [r4, #16]
+ 10906 0062 22B9     		cbnz	r2, .L532
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10907              		.loc 1 1238 5 discriminator 3 view .LVU3648
+ 10908 0064 40F2FF12 		movw	r2, #511
+ 10909 0068 A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 10910 006c 0DE0     		b	.L533
+ 10911              	.L532:
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10912              		.loc 1 1238 5 discriminator 4 view .LVU3649
+ 10913 006e FF22     		movs	r2, #255
+ 10914 0070 A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 10915 0074 09E0     		b	.L533
+ 10916              	.L535:
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10917              		.loc 1 1238 5 discriminator 8 view .LVU3650
+ 10918 0076 7F22     		movs	r2, #127
+ 10919 0078 A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 10920 007c 05E0     		b	.L533
+ 10921              	.L534:
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10922              		.loc 1 1238 5 discriminator 6 view .LVU3651
+ 10923 007e B3F1805F 		cmp	r3, #268435456
+ 10924 0082 0DD0     		beq	.L552
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10925              		.loc 1 1238 5 discriminator 10 view .LVU3652
+ 10926 0084 0022     		movs	r2, #0
+ 10927 0086 A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 10928              	.L533:
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10929              		.loc 1 1238 5 discriminator 13 view .LVU3653
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10930              		.loc 1 1239 5 discriminator 13 view .LVU3654
+1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10931              		.loc 1 1239 12 is_stmt 0 discriminator 13 view .LVU3655
+ 10932 008a B4F86080 		ldrh	r8, [r4, #96]
+ 10933              	.LVL969:
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10934              		.loc 1 1242 5 is_stmt 1 discriminator 13 view .LVU3656
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10935              		.loc 1 1242 8 is_stmt 0 discriminator 13 view .LVU3657
+ 10936 008e B3F5805F 		cmp	r3, #4096
+ 10937 0092 0FD0     		beq	.L553
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10938              		.loc 1 1250 19 view .LVU3658
+ 10939 0094 4FF00009 		mov	r9, #0
+ 10940              	.LVL970:
+ 10941              	.L538:
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10942              		.loc 1 1253 5 is_stmt 1 view .LVU3659
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10943              		.loc 1 1253 5 view .LVU3660
+ 10944 0098 0023     		movs	r3, #0
+ARM GAS  /tmp/cceWHrnJ.s 			page 351
+
+
+ 10945 009a 84F88030 		strb	r3, [r4, #128]
+1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 10946              		.loc 1 1253 5 view .LVU3661
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10947              		.loc 1 1256 5 view .LVU3662
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10948              		.loc 1 1256 11 is_stmt 0 view .LVU3663
+ 10949 009e 1EE0     		b	.L539
+ 10950              	.LVL971:
+ 10951              	.L552:
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10952              		.loc 1 1238 5 is_stmt 1 discriminator 9 view .LVU3664
+ 10953 00a0 2269     		ldr	r2, [r4, #16]
+ 10954 00a2 1AB9     		cbnz	r2, .L537
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10955              		.loc 1 1238 5 discriminator 11 view .LVU3665
+ 10956 00a4 7F22     		movs	r2, #127
+ 10957 00a6 A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 10958 00aa EEE7     		b	.L533
+ 10959              	.L537:
+1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     uhMask = huart->Mask;
+ 10960              		.loc 1 1238 5 discriminator 12 view .LVU3666
+ 10961 00ac 3F22     		movs	r2, #63
+ 10962 00ae A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 10963 00b2 EAE7     		b	.L533
+ 10964              	.LVL972:
+ 10965              	.L553:
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10966              		.loc 1 1242 71 is_stmt 0 discriminator 1 view .LVU3667
+ 10967 00b4 2369     		ldr	r3, [r4, #16]
+1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 10968              		.loc 1 1242 56 discriminator 1 view .LVU3668
+ 10969 00b6 13B1     		cbz	r3, .L548
+1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10970              		.loc 1 1250 19 view .LVU3669
+ 10971 00b8 4FF00009 		mov	r9, #0
+ 10972 00bc ECE7     		b	.L538
+ 10973              	.L548:
+1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10974              		.loc 1 1245 19 view .LVU3670
+ 10975 00be A946     		mov	r9, r5
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       pdata16bits = (uint16_t *) pData;
+ 10976              		.loc 1 1244 19 view .LVU3671
+ 10977 00c0 0025     		movs	r5, #0
+ 10978              	.LVL973:
+1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       pdata16bits = (uint16_t *) pData;
+ 10979              		.loc 1 1244 19 view .LVU3672
+ 10980 00c2 E9E7     		b	.L538
+ 10981              	.LVL974:
+ 10982              	.L555:
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata16bits++;
+ 10983              		.loc 1 1264 9 is_stmt 1 view .LVU3673
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata16bits++;
+ 10984              		.loc 1 1264 40 is_stmt 0 view .LVU3674
+ 10985 00c4 2368     		ldr	r3, [r4]
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata16bits++;
+ 10986              		.loc 1 1264 50 view .LVU3675
+ARM GAS  /tmp/cceWHrnJ.s 			page 352
+
+
+ 10987 00c6 5B6A     		ldr	r3, [r3, #36]
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata16bits++;
+ 10988              		.loc 1 1264 24 view .LVU3676
+ 10989 00c8 08EA0303 		and	r3, r8, r3
+1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata16bits++;
+ 10990              		.loc 1 1264 22 view .LVU3677
+ 10991 00cc 29F8023B 		strh	r3, [r9], #2	@ movhi
+ 10992              	.LVL975:
+1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 10993              		.loc 1 1265 9 is_stmt 1 view .LVU3678
+ 10994              	.L541:
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10995              		.loc 1 1272 7 view .LVU3679
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10996              		.loc 1 1272 12 is_stmt 0 view .LVU3680
+ 10997 00d0 B4F85E20 		ldrh	r2, [r4, #94]
+ 10998 00d4 92B2     		uxth	r2, r2
+1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 10999              		.loc 1 1272 25 view .LVU3681
+ 11000 00d6 013A     		subs	r2, r2, #1
+ 11001 00d8 92B2     		uxth	r2, r2
+ 11002 00da A4F85E20 		strh	r2, [r4, #94]	@ movhi
+ 11003              	.L539:
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 11004              		.loc 1 1256 31 is_stmt 1 view .LVU3682
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 11005              		.loc 1 1256 17 is_stmt 0 view .LVU3683
+ 11006 00de B4F85E30 		ldrh	r3, [r4, #94]
+ 11007 00e2 9BB2     		uxth	r3, r3
+1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 11008              		.loc 1 1256 31 view .LVU3684
+ 11009 00e4 8BB1     		cbz	r3, .L554
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 11010              		.loc 1 1258 7 is_stmt 1 view .LVU3685
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 11011              		.loc 1 1258 11 is_stmt 0 view .LVU3686
+ 11012 00e6 0096     		str	r6, [sp]
+ 11013 00e8 3B46     		mov	r3, r7
+ 11014 00ea 0022     		movs	r2, #0
+ 11015 00ec 2021     		movs	r1, #32
+ 11016 00ee 2046     		mov	r0, r4
+ 11017 00f0 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 11018              	.LVL976:
+1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 11019              		.loc 1 1258 10 view .LVU3687
+ 11020 00f4 C0B9     		cbnz	r0, .L549
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 11021              		.loc 1 1262 7 is_stmt 1 view .LVU3688
+1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 11022              		.loc 1 1262 10 is_stmt 0 view .LVU3689
+ 11023 00f6 002D     		cmp	r5, #0
+ 11024 00f8 E4D0     		beq	.L555
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata8bits++;
+ 11025              		.loc 1 1269 9 is_stmt 1 view .LVU3690
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata8bits++;
+ 11026              		.loc 1 1269 38 is_stmt 0 view .LVU3691
+ 11027 00fa 2368     		ldr	r3, [r4]
+ARM GAS  /tmp/cceWHrnJ.s 			page 353
+
+
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata8bits++;
+ 11028              		.loc 1 1269 48 view .LVU3692
+ 11029 00fc 5A6A     		ldr	r2, [r3, #36]
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata8bits++;
+ 11030              		.loc 1 1269 56 view .LVU3693
+ 11031 00fe 5FFA88F3 		uxtb	r3, r8
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata8bits++;
+ 11032              		.loc 1 1269 23 view .LVU3694
+ 11033 0102 1340     		ands	r3, r3, r2
+1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****         pdata8bits++;
+ 11034              		.loc 1 1269 21 view .LVU3695
+ 11035 0104 05F8013B 		strb	r3, [r5], #1
+ 11036              	.LVL977:
+1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 11037              		.loc 1 1270 9 is_stmt 1 view .LVU3696
+1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 11038              		.loc 1 1270 9 is_stmt 0 view .LVU3697
+ 11039 0108 E2E7     		b	.L541
+ 11040              	.L554:
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11041              		.loc 1 1276 5 is_stmt 1 view .LVU3698
+1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11042              		.loc 1 1276 20 is_stmt 0 view .LVU3699
+ 11043 010a 2023     		movs	r3, #32
+ 11044 010c C4F88830 		str	r3, [r4, #136]
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11045              		.loc 1 1278 5 is_stmt 1 view .LVU3700
+1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11046              		.loc 1 1278 12 is_stmt 0 view .LVU3701
+ 11047 0110 0020     		movs	r0, #0
+ 11048 0112 00E0     		b	.L530
+ 11049              	.LVL978:
+ 11050              	.L543:
+1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11051              		.loc 1 1282 12 view .LVU3702
+ 11052 0114 0220     		movs	r0, #2
+ 11053              	.LVL979:
+ 11054              	.L530:
+1284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11055              		.loc 1 1284 1 view .LVU3703
+ 11056 0116 03B0     		add	sp, sp, #12
+ 11057              	.LCFI39:
+ 11058              		.cfi_remember_state
+ 11059              		.cfi_def_cfa_offset 28
+ 11060              		@ sp needed
+ 11061 0118 BDE8F083 		pop	{r4, r5, r6, r7, r8, r9, pc}
+ 11062              	.LVL980:
+ 11063              	.L544:
+ 11064              	.LCFI40:
+ 11065              		.cfi_restore_state
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 11066              		.loc 1 1222 15 view .LVU3704
+ 11067 011c 0120     		movs	r0, #1
+ 11068              	.LVL981:
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 11069              		.loc 1 1222 15 view .LVU3705
+ 11070 011e FAE7     		b	.L530
+ARM GAS  /tmp/cceWHrnJ.s 			page 354
+
+
+ 11071              	.LVL982:
+ 11072              	.L545:
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 11073              		.loc 1 1222 15 view .LVU3706
+ 11074 0120 0120     		movs	r0, #1
+ 11075              	.LVL983:
+1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 11076              		.loc 1 1222 15 view .LVU3707
+ 11077 0122 F8E7     		b	.L530
+ 11078              	.LVL984:
+ 11079              	.L546:
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11080              		.loc 1 1225 5 view .LVU3708
+ 11081 0124 0220     		movs	r0, #2
+ 11082              	.LVL985:
+1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11083              		.loc 1 1225 5 view .LVU3709
+ 11084 0126 F6E7     		b	.L530
+ 11085              	.LVL986:
+ 11086              	.L549:
+1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 11087              		.loc 1 1260 16 view .LVU3710
+ 11088 0128 0320     		movs	r0, #3
+ 11089 012a F4E7     		b	.L530
+ 11090              		.cfi_endproc
+ 11091              	.LFE337:
+ 11093              		.section	.text.UART_CheckIdleState,"ax",%progbits
+ 11094              		.align	1
+ 11095              		.global	UART_CheckIdleState
+ 11096              		.syntax unified
+ 11097              		.thumb
+ 11098              		.thumb_func
+ 11100              	UART_CheckIdleState:
+ 11101              	.LVL987:
+ 11102              	.LFB374:
+3315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t tickstart;
+ 11103              		.loc 1 3315 1 is_stmt 1 view -0
+ 11104              		.cfi_startproc
+ 11105              		@ args = 0, pretend = 0, frame = 0
+ 11106              		@ frame_needed = 0, uses_anonymous_args = 0
+3315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   uint32_t tickstart;
+ 11107              		.loc 1 3315 1 is_stmt 0 view .LVU3712
+ 11108 0000 30B5     		push	{r4, r5, lr}
+ 11109              	.LCFI41:
+ 11110              		.cfi_def_cfa_offset 12
+ 11111              		.cfi_offset 4, -12
+ 11112              		.cfi_offset 5, -8
+ 11113              		.cfi_offset 14, -4
+ 11114 0002 83B0     		sub	sp, sp, #12
+ 11115              	.LCFI42:
+ 11116              		.cfi_def_cfa_offset 24
+ 11117 0004 0446     		mov	r4, r0
+3316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11118              		.loc 1 3316 3 is_stmt 1 view .LVU3713
+3319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11119              		.loc 1 3319 3 view .LVU3714
+3319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 355
+
+
+ 11120              		.loc 1 3319 20 is_stmt 0 view .LVU3715
+ 11121 0006 0023     		movs	r3, #0
+ 11122 0008 C0F88C30 		str	r3, [r0, #140]
+3322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11123              		.loc 1 3322 3 is_stmt 1 view .LVU3716
+3322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11124              		.loc 1 3322 15 is_stmt 0 view .LVU3717
+ 11125 000c FFF7FEFF 		bl	HAL_GetTick
+ 11126              	.LVL988:
+3322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11127              		.loc 1 3322 15 view .LVU3718
+ 11128 0010 0546     		mov	r5, r0
+ 11129              	.LVL989:
+3325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11130              		.loc 1 3325 3 is_stmt 1 view .LVU3719
+3325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11131              		.loc 1 3325 13 is_stmt 0 view .LVU3720
+ 11132 0012 2268     		ldr	r2, [r4]
+3325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11133              		.loc 1 3325 23 view .LVU3721
+ 11134 0014 1268     		ldr	r2, [r2]
+3325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11135              		.loc 1 3325 6 view .LVU3722
+ 11136 0016 12F0080F 		tst	r2, #8
+ 11137 001a 0FD1     		bne	.L563
+ 11138              	.LVL990:
+ 11139              	.L557:
+3336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11140              		.loc 1 3336 3 is_stmt 1 view .LVU3723
+3336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11141              		.loc 1 3336 13 is_stmt 0 view .LVU3724
+ 11142 001c 2368     		ldr	r3, [r4]
+3336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11143              		.loc 1 3336 23 view .LVU3725
+ 11144 001e 1B68     		ldr	r3, [r3]
+3336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11145              		.loc 1 3336 6 view .LVU3726
+ 11146 0020 13F0040F 		tst	r3, #4
+ 11147 0024 18D1     		bne	.L564
+ 11148              	.L559:
+3347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 11149              		.loc 1 3347 3 is_stmt 1 view .LVU3727
+3347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 11150              		.loc 1 3347 17 is_stmt 0 view .LVU3728
+ 11151 0026 2023     		movs	r3, #32
+ 11152 0028 C4F88430 		str	r3, [r4, #132]
+3348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 11153              		.loc 1 3348 3 is_stmt 1 view .LVU3729
+3348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 11154              		.loc 1 3348 18 is_stmt 0 view .LVU3730
+ 11155 002c C4F88830 		str	r3, [r4, #136]
+3349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11156              		.loc 1 3349 3 is_stmt 1 view .LVU3731
+3349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11157              		.loc 1 3349 24 is_stmt 0 view .LVU3732
+ 11158 0030 0020     		movs	r0, #0
+ 11159 0032 E066     		str	r0, [r4, #108]
+ARM GAS  /tmp/cceWHrnJ.s 			page 356
+
+
+3351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11160              		.loc 1 3351 3 is_stmt 1 view .LVU3733
+3351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11161              		.loc 1 3351 3 view .LVU3734
+ 11162 0034 84F88000 		strb	r0, [r4, #128]
+3351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11163              		.loc 1 3351 3 view .LVU3735
+3353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11164              		.loc 1 3353 3 view .LVU3736
+ 11165              	.L558:
+3354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11166              		.loc 1 3354 1 is_stmt 0 view .LVU3737
+ 11167 0038 03B0     		add	sp, sp, #12
+ 11168              	.LCFI43:
+ 11169              		.cfi_remember_state
+ 11170              		.cfi_def_cfa_offset 12
+ 11171              		@ sp needed
+ 11172 003a 30BD     		pop	{r4, r5, pc}
+ 11173              	.LVL991:
+ 11174              	.L563:
+ 11175              	.LCFI44:
+ 11176              		.cfi_restore_state
+3328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 11177              		.loc 1 3328 5 is_stmt 1 view .LVU3738
+3328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 11178              		.loc 1 3328 9 is_stmt 0 view .LVU3739
+ 11179 003c 6FF07E43 		mvn	r3, #-33554432
+ 11180 0040 0093     		str	r3, [sp]
+ 11181 0042 0346     		mov	r3, r0
+ 11182 0044 0022     		movs	r2, #0
+ 11183 0046 4FF40011 		mov	r1, #2097152
+ 11184 004a 2046     		mov	r0, r4
+ 11185              	.LVL992:
+3328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 11186              		.loc 1 3328 9 view .LVU3740
+ 11187 004c FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 11188              	.LVL993:
+3328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 11189              		.loc 1 3328 8 view .LVU3741
+ 11190 0050 0028     		cmp	r0, #0
+ 11191 0052 E3D0     		beq	.L557
+3331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 11192              		.loc 1 3331 14 view .LVU3742
+ 11193 0054 0320     		movs	r0, #3
+ 11194 0056 EFE7     		b	.L558
+ 11195              	.L564:
+3339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 11196              		.loc 1 3339 5 is_stmt 1 view .LVU3743
+3339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 11197              		.loc 1 3339 9 is_stmt 0 view .LVU3744
+ 11198 0058 6FF07E43 		mvn	r3, #-33554432
+ 11199 005c 0093     		str	r3, [sp]
+ 11200 005e 2B46     		mov	r3, r5
+ 11201 0060 0022     		movs	r2, #0
+ 11202 0062 4FF48001 		mov	r1, #4194304
+ 11203 0066 2046     		mov	r0, r4
+ 11204 0068 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ARM GAS  /tmp/cceWHrnJ.s 			page 357
+
+
+ 11205              	.LVL994:
+3339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 11206              		.loc 1 3339 8 view .LVU3745
+ 11207 006c 0028     		cmp	r0, #0
+ 11208 006e DAD0     		beq	.L559
+3342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 11209              		.loc 1 3342 14 view .LVU3746
+ 11210 0070 0320     		movs	r0, #3
+ 11211 0072 E1E7     		b	.L558
+ 11212              		.cfi_endproc
+ 11213              	.LFE374:
+ 11215              		.section	.text.HAL_UART_Init,"ax",%progbits
+ 11216              		.align	1
+ 11217              		.global	HAL_UART_Init
+ 11218              		.syntax unified
+ 11219              		.thumb
+ 11220              		.thumb_func
+ 11222              	HAL_UART_Init:
+ 11223              	.LVL995:
+ 11224              	.LFB329:
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 11225              		.loc 1 308 1 is_stmt 1 view -0
+ 11226              		.cfi_startproc
+ 11227              		@ args = 0, pretend = 0, frame = 0
+ 11228              		@ frame_needed = 0, uses_anonymous_args = 0
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11229              		.loc 1 310 3 view .LVU3748
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11230              		.loc 1 310 6 is_stmt 0 view .LVU3749
+ 11231 0000 78B3     		cbz	r0, .L569
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 11232              		.loc 1 308 1 view .LVU3750
+ 11233 0002 10B5     		push	{r4, lr}
+ 11234              	.LCFI45:
+ 11235              		.cfi_def_cfa_offset 8
+ 11236              		.cfi_offset 4, -8
+ 11237              		.cfi_offset 14, -4
+ 11238 0004 0446     		mov	r4, r0
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11239              		.loc 1 315 3 is_stmt 1 view .LVU3751
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11240              		.loc 1 323 5 view .LVU3752
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11241              		.loc 1 326 3 view .LVU3753
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11242              		.loc 1 326 12 is_stmt 0 view .LVU3754
+ 11243 0006 D0F88430 		ldr	r3, [r0, #132]
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11244              		.loc 1 326 6 view .LVU3755
+ 11245 000a 0BB3     		cbz	r3, .L574
+ 11246              	.LVL996:
+ 11247              	.L567:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11248              		.loc 1 347 3 is_stmt 1 view .LVU3756
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11249              		.loc 1 347 17 is_stmt 0 view .LVU3757
+ 11250 000c 2423     		movs	r3, #36
+ARM GAS  /tmp/cceWHrnJ.s 			page 358
+
+
+ 11251 000e C4F88430 		str	r3, [r4, #132]
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11252              		.loc 1 349 3 is_stmt 1 view .LVU3758
+ 11253 0012 2268     		ldr	r2, [r4]
+ 11254 0014 1368     		ldr	r3, [r2]
+ 11255 0016 23F00103 		bic	r3, r3, #1
+ 11256 001a 1360     		str	r3, [r2]
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11257              		.loc 1 352 3 view .LVU3759
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11258              		.loc 1 352 7 is_stmt 0 view .LVU3760
+ 11259 001c 2046     		mov	r0, r4
+ 11260 001e FFF7FEFF 		bl	UART_SetConfig
+ 11261              	.LVL997:
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11262              		.loc 1 352 6 view .LVU3761
+ 11263 0022 0128     		cmp	r0, #1
+ 11264 0024 13D0     		beq	.L566
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11265              		.loc 1 357 3 is_stmt 1 view .LVU3762
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11266              		.loc 1 357 26 is_stmt 0 view .LVU3763
+ 11267 0026 A36A     		ldr	r3, [r4, #40]
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11268              		.loc 1 357 6 view .LVU3764
+ 11269 0028 BBB9     		cbnz	r3, .L575
+ 11270              	.L568:
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ 11271              		.loc 1 365 3 is_stmt 1 view .LVU3765
+ 11272 002a 2268     		ldr	r2, [r4]
+ 11273 002c 5368     		ldr	r3, [r2, #4]
+ 11274 002e 23F49043 		bic	r3, r3, #18432
+ 11275 0032 5360     		str	r3, [r2, #4]
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11276              		.loc 1 366 3 view .LVU3766
+ 11277 0034 2268     		ldr	r2, [r4]
+ 11278 0036 9368     		ldr	r3, [r2, #8]
+ 11279 0038 23F02A03 		bic	r3, r3, #42
+ 11280 003c 9360     		str	r3, [r2, #8]
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11281              		.loc 1 368 3 view .LVU3767
+ 11282 003e 2268     		ldr	r2, [r4]
+ 11283 0040 1368     		ldr	r3, [r2]
+ 11284 0042 43F00103 		orr	r3, r3, #1
+ 11285 0046 1360     		str	r3, [r2]
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11286              		.loc 1 371 3 view .LVU3768
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11287              		.loc 1 371 11 is_stmt 0 view .LVU3769
+ 11288 0048 2046     		mov	r0, r4
+ 11289 004a FFF7FEFF 		bl	UART_CheckIdleState
+ 11290              	.LVL998:
+ 11291              	.L566:
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11292              		.loc 1 372 1 view .LVU3770
+ 11293 004e 10BD     		pop	{r4, pc}
+ 11294              	.LVL999:
+ARM GAS  /tmp/cceWHrnJ.s 			page 359
+
+
+ 11295              	.L574:
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11296              		.loc 1 329 5 is_stmt 1 view .LVU3771
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11297              		.loc 1 329 17 is_stmt 0 view .LVU3772
+ 11298 0050 80F88030 		strb	r3, [r0, #128]
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 11299              		.loc 1 343 5 is_stmt 1 view .LVU3773
+ 11300 0054 FFF7FEFF 		bl	HAL_UART_MspInit
+ 11301              	.LVL1000:
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 11302              		.loc 1 343 5 is_stmt 0 view .LVU3774
+ 11303 0058 D8E7     		b	.L567
+ 11304              	.L575:
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11305              		.loc 1 359 5 is_stmt 1 view .LVU3775
+ 11306 005a 2046     		mov	r0, r4
+ 11307 005c FFF7FEFF 		bl	UART_AdvFeatureConfig
+ 11308              	.LVL1001:
+ 11309 0060 E3E7     		b	.L568
+ 11310              	.LVL1002:
+ 11311              	.L569:
+ 11312              	.LCFI46:
+ 11313              		.cfi_def_cfa_offset 0
+ 11314              		.cfi_restore 4
+ 11315              		.cfi_restore 14
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11316              		.loc 1 312 12 is_stmt 0 view .LVU3776
+ 11317 0062 0120     		movs	r0, #1
+ 11318              	.LVL1003:
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11319              		.loc 1 372 1 view .LVU3777
+ 11320 0064 7047     		bx	lr
+ 11321              		.cfi_endproc
+ 11322              	.LFE329:
+ 11324              		.section	.text.HAL_HalfDuplex_Init,"ax",%progbits
+ 11325              		.align	1
+ 11326              		.global	HAL_HalfDuplex_Init
+ 11327              		.syntax unified
+ 11328              		.thumb
+ 11329              		.thumb_func
+ 11331              	HAL_HalfDuplex_Init:
+ 11332              	.LVL1004:
+ 11333              	.LFB330:
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 11334              		.loc 1 381 1 is_stmt 1 view -0
+ 11335              		.cfi_startproc
+ 11336              		@ args = 0, pretend = 0, frame = 0
+ 11337              		@ frame_needed = 0, uses_anonymous_args = 0
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11338              		.loc 1 383 3 view .LVU3779
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11339              		.loc 1 383 6 is_stmt 0 view .LVU3780
+ 11340 0000 0028     		cmp	r0, #0
+ 11341 0002 34D0     		beq	.L580
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 11342              		.loc 1 381 1 view .LVU3781
+ARM GAS  /tmp/cceWHrnJ.s 			page 360
+
+
+ 11343 0004 10B5     		push	{r4, lr}
+ 11344              	.LCFI47:
+ 11345              		.cfi_def_cfa_offset 8
+ 11346              		.cfi_offset 4, -8
+ 11347              		.cfi_offset 14, -4
+ 11348 0006 0446     		mov	r4, r0
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11349              		.loc 1 389 3 is_stmt 1 view .LVU3782
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11350              		.loc 1 391 3 view .LVU3783
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11351              		.loc 1 391 12 is_stmt 0 view .LVU3784
+ 11352 0008 D0F88430 		ldr	r3, [r0, #132]
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11353              		.loc 1 391 6 view .LVU3785
+ 11354 000c 33B3     		cbz	r3, .L585
+ 11355              	.LVL1005:
+ 11356              	.L578:
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11357              		.loc 1 412 3 is_stmt 1 view .LVU3786
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11358              		.loc 1 412 17 is_stmt 0 view .LVU3787
+ 11359 000e 2423     		movs	r3, #36
+ 11360 0010 C4F88430 		str	r3, [r4, #132]
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11361              		.loc 1 414 3 is_stmt 1 view .LVU3788
+ 11362 0014 2268     		ldr	r2, [r4]
+ 11363 0016 1368     		ldr	r3, [r2]
+ 11364 0018 23F00103 		bic	r3, r3, #1
+ 11365 001c 1360     		str	r3, [r2]
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11366              		.loc 1 417 3 view .LVU3789
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11367              		.loc 1 417 7 is_stmt 0 view .LVU3790
+ 11368 001e 2046     		mov	r0, r4
+ 11369 0020 FFF7FEFF 		bl	UART_SetConfig
+ 11370              	.LVL1006:
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11371              		.loc 1 417 6 view .LVU3791
+ 11372 0024 0128     		cmp	r0, #1
+ 11373 0026 18D0     		beq	.L577
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11374              		.loc 1 422 3 is_stmt 1 view .LVU3792
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11375              		.loc 1 422 26 is_stmt 0 view .LVU3793
+ 11376 0028 A36A     		ldr	r3, [r4, #40]
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11377              		.loc 1 422 6 view .LVU3794
+ 11378 002a E3B9     		cbnz	r3, .L586
+ 11379              	.L579:
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+ 11380              		.loc 1 430 3 is_stmt 1 view .LVU3795
+ 11381 002c 2268     		ldr	r2, [r4]
+ 11382 002e 5368     		ldr	r3, [r2, #4]
+ 11383 0030 23F49043 		bic	r3, r3, #18432
+ 11384 0034 5360     		str	r3, [r2, #4]
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 361
+
+
+ 11385              		.loc 1 431 3 view .LVU3796
+ 11386 0036 2268     		ldr	r2, [r4]
+ 11387 0038 9368     		ldr	r3, [r2, #8]
+ 11388 003a 23F02203 		bic	r3, r3, #34
+ 11389 003e 9360     		str	r3, [r2, #8]
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11390              		.loc 1 434 3 view .LVU3797
+ 11391 0040 2268     		ldr	r2, [r4]
+ 11392 0042 9368     		ldr	r3, [r2, #8]
+ 11393 0044 43F00803 		orr	r3, r3, #8
+ 11394 0048 9360     		str	r3, [r2, #8]
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11395              		.loc 1 436 3 view .LVU3798
+ 11396 004a 2268     		ldr	r2, [r4]
+ 11397 004c 1368     		ldr	r3, [r2]
+ 11398 004e 43F00103 		orr	r3, r3, #1
+ 11399 0052 1360     		str	r3, [r2]
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11400              		.loc 1 439 3 view .LVU3799
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11401              		.loc 1 439 11 is_stmt 0 view .LVU3800
+ 11402 0054 2046     		mov	r0, r4
+ 11403 0056 FFF7FEFF 		bl	UART_CheckIdleState
+ 11404              	.LVL1007:
+ 11405              	.L577:
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11406              		.loc 1 440 1 view .LVU3801
+ 11407 005a 10BD     		pop	{r4, pc}
+ 11408              	.LVL1008:
+ 11409              	.L585:
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11410              		.loc 1 394 5 is_stmt 1 view .LVU3802
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11411              		.loc 1 394 17 is_stmt 0 view .LVU3803
+ 11412 005c 80F88030 		strb	r3, [r0, #128]
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 11413              		.loc 1 408 5 is_stmt 1 view .LVU3804
+ 11414 0060 FFF7FEFF 		bl	HAL_UART_MspInit
+ 11415              	.LVL1009:
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 11416              		.loc 1 408 5 is_stmt 0 view .LVU3805
+ 11417 0064 D3E7     		b	.L578
+ 11418              	.L586:
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11419              		.loc 1 424 5 is_stmt 1 view .LVU3806
+ 11420 0066 2046     		mov	r0, r4
+ 11421 0068 FFF7FEFF 		bl	UART_AdvFeatureConfig
+ 11422              	.LVL1010:
+ 11423 006c DEE7     		b	.L579
+ 11424              	.LVL1011:
+ 11425              	.L580:
+ 11426              	.LCFI48:
+ 11427              		.cfi_def_cfa_offset 0
+ 11428              		.cfi_restore 4
+ 11429              		.cfi_restore 14
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11430              		.loc 1 385 12 is_stmt 0 view .LVU3807
+ARM GAS  /tmp/cceWHrnJ.s 			page 362
+
+
+ 11431 006e 0120     		movs	r0, #1
+ 11432              	.LVL1012:
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11433              		.loc 1 440 1 view .LVU3808
+ 11434 0070 7047     		bx	lr
+ 11435              		.cfi_endproc
+ 11436              	.LFE330:
+ 11438              		.section	.text.HAL_LIN_Init,"ax",%progbits
+ 11439              		.align	1
+ 11440              		.global	HAL_LIN_Init
+ 11441              		.syntax unified
+ 11442              		.thumb
+ 11443              		.thumb_func
+ 11445              	HAL_LIN_Init:
+ 11446              	.LVL1013:
+ 11447              	.LFB331:
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 11448              		.loc 1 454 1 is_stmt 1 view -0
+ 11449              		.cfi_startproc
+ 11450              		@ args = 0, pretend = 0, frame = 0
+ 11451              		@ frame_needed = 0, uses_anonymous_args = 0
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11452              		.loc 1 456 3 view .LVU3810
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11453              		.loc 1 456 6 is_stmt 0 view .LVU3811
+ 11454 0000 0028     		cmp	r0, #0
+ 11455 0002 42D0     		beq	.L591
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 11456              		.loc 1 454 1 view .LVU3812
+ 11457 0004 38B5     		push	{r3, r4, r5, lr}
+ 11458              	.LCFI49:
+ 11459              		.cfi_def_cfa_offset 16
+ 11460              		.cfi_offset 3, -16
+ 11461              		.cfi_offset 4, -12
+ 11462              		.cfi_offset 5, -8
+ 11463              		.cfi_offset 14, -4
+ 11464 0006 0D46     		mov	r5, r1
+ 11465 0008 0446     		mov	r4, r0
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the Break detection length parameter */
+ 11466              		.loc 1 462 3 is_stmt 1 view .LVU3813
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11467              		.loc 1 464 3 view .LVU3814
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11468              		.loc 1 467 3 view .LVU3815
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11469              		.loc 1 467 18 is_stmt 0 view .LVU3816
+ 11470 000a C369     		ldr	r3, [r0, #28]
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11471              		.loc 1 467 6 view .LVU3817
+ 11472 000c B3F5004F 		cmp	r3, #32768
+ 11473 0010 3DD0     		beq	.L592
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11474              		.loc 1 472 3 is_stmt 1 view .LVU3818
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11475              		.loc 1 472 18 is_stmt 0 view .LVU3819
+ 11476 0012 8368     		ldr	r3, [r0, #8]
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ARM GAS  /tmp/cceWHrnJ.s 			page 363
+
+
+ 11477              		.loc 1 472 6 view .LVU3820
+ 11478 0014 002B     		cmp	r3, #0
+ 11479 0016 3CD1     		bne	.L593
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11480              		.loc 1 477 3 is_stmt 1 view .LVU3821
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11481              		.loc 1 477 12 is_stmt 0 view .LVU3822
+ 11482 0018 D0F88430 		ldr	r3, [r0, #132]
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11483              		.loc 1 477 6 view .LVU3823
+ 11484 001c 63B3     		cbz	r3, .L598
+ 11485              	.LVL1014:
+ 11486              	.L589:
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11487              		.loc 1 498 3 is_stmt 1 view .LVU3824
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11488              		.loc 1 498 17 is_stmt 0 view .LVU3825
+ 11489 001e 2423     		movs	r3, #36
+ 11490 0020 C4F88430 		str	r3, [r4, #132]
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11491              		.loc 1 500 3 is_stmt 1 view .LVU3826
+ 11492 0024 2268     		ldr	r2, [r4]
+ 11493 0026 1368     		ldr	r3, [r2]
+ 11494 0028 23F00103 		bic	r3, r3, #1
+ 11495 002c 1360     		str	r3, [r2]
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11496              		.loc 1 503 3 view .LVU3827
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11497              		.loc 1 503 7 is_stmt 0 view .LVU3828
+ 11498 002e 2046     		mov	r0, r4
+ 11499 0030 FFF7FEFF 		bl	UART_SetConfig
+ 11500              	.LVL1015:
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11501              		.loc 1 503 6 view .LVU3829
+ 11502 0034 0128     		cmp	r0, #1
+ 11503 0036 1ED0     		beq	.L588
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11504              		.loc 1 508 3 is_stmt 1 view .LVU3830
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11505              		.loc 1 508 26 is_stmt 0 view .LVU3831
+ 11506 0038 A36A     		ldr	r3, [r4, #40]
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11507              		.loc 1 508 6 view .LVU3832
+ 11508 003a 13BB     		cbnz	r3, .L599
+ 11509              	.L590:
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+ 11510              		.loc 1 516 3 is_stmt 1 view .LVU3833
+ 11511 003c 2268     		ldr	r2, [r4]
+ 11512 003e 5368     		ldr	r3, [r2, #4]
+ 11513 0040 23F40063 		bic	r3, r3, #2048
+ 11514 0044 5360     		str	r3, [r2, #4]
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11515              		.loc 1 517 3 view .LVU3834
+ 11516 0046 2268     		ldr	r2, [r4]
+ 11517 0048 9368     		ldr	r3, [r2, #8]
+ 11518 004a 23F02A03 		bic	r3, r3, #42
+ 11519 004e 9360     		str	r3, [r2, #8]
+ARM GAS  /tmp/cceWHrnJ.s 			page 364
+
+
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11520              		.loc 1 520 3 view .LVU3835
+ 11521 0050 2268     		ldr	r2, [r4]
+ 11522 0052 5368     		ldr	r3, [r2, #4]
+ 11523 0054 43F48043 		orr	r3, r3, #16384
+ 11524 0058 5360     		str	r3, [r2, #4]
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11525              		.loc 1 523 3 view .LVU3836
+ 11526 005a 2268     		ldr	r2, [r4]
+ 11527 005c 5368     		ldr	r3, [r2, #4]
+ 11528 005e 23F02003 		bic	r3, r3, #32
+ 11529 0062 2B43     		orrs	r3, r3, r5
+ 11530 0064 5360     		str	r3, [r2, #4]
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11531              		.loc 1 525 3 view .LVU3837
+ 11532 0066 2268     		ldr	r2, [r4]
+ 11533 0068 1368     		ldr	r3, [r2]
+ 11534 006a 43F00103 		orr	r3, r3, #1
+ 11535 006e 1360     		str	r3, [r2]
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11536              		.loc 1 528 3 view .LVU3838
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11537              		.loc 1 528 11 is_stmt 0 view .LVU3839
+ 11538 0070 2046     		mov	r0, r4
+ 11539 0072 FFF7FEFF 		bl	UART_CheckIdleState
+ 11540              	.LVL1016:
+ 11541              	.L588:
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11542              		.loc 1 529 1 view .LVU3840
+ 11543 0076 38BD     		pop	{r3, r4, r5, pc}
+ 11544              	.LVL1017:
+ 11545              	.L598:
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11546              		.loc 1 480 5 is_stmt 1 view .LVU3841
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11547              		.loc 1 480 17 is_stmt 0 view .LVU3842
+ 11548 0078 80F88030 		strb	r3, [r0, #128]
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 11549              		.loc 1 494 5 is_stmt 1 view .LVU3843
+ 11550 007c FFF7FEFF 		bl	HAL_UART_MspInit
+ 11551              	.LVL1018:
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 11552              		.loc 1 494 5 is_stmt 0 view .LVU3844
+ 11553 0080 CDE7     		b	.L589
+ 11554              	.L599:
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11555              		.loc 1 510 5 is_stmt 1 view .LVU3845
+ 11556 0082 2046     		mov	r0, r4
+ 11557 0084 FFF7FEFF 		bl	UART_AdvFeatureConfig
+ 11558              	.LVL1019:
+ 11559 0088 D8E7     		b	.L590
+ 11560              	.LVL1020:
+ 11561              	.L591:
+ 11562              	.LCFI50:
+ 11563              		.cfi_def_cfa_offset 0
+ 11564              		.cfi_restore 3
+ 11565              		.cfi_restore 4
+ARM GAS  /tmp/cceWHrnJ.s 			page 365
+
+
+ 11566              		.cfi_restore 5
+ 11567              		.cfi_restore 14
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11568              		.loc 1 458 12 is_stmt 0 view .LVU3846
+ 11569 008a 0120     		movs	r0, #1
+ 11570              	.LVL1021:
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11571              		.loc 1 529 1 view .LVU3847
+ 11572 008c 7047     		bx	lr
+ 11573              	.LVL1022:
+ 11574              	.L592:
+ 11575              	.LCFI51:
+ 11576              		.cfi_def_cfa_offset 16
+ 11577              		.cfi_offset 3, -16
+ 11578              		.cfi_offset 4, -12
+ 11579              		.cfi_offset 5, -8
+ 11580              		.cfi_offset 14, -4
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11581              		.loc 1 469 12 view .LVU3848
+ 11582 008e 0120     		movs	r0, #1
+ 11583              	.LVL1023:
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11584              		.loc 1 469 12 view .LVU3849
+ 11585 0090 F1E7     		b	.L588
+ 11586              	.LVL1024:
+ 11587              	.L593:
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11588              		.loc 1 474 12 view .LVU3850
+ 11589 0092 0120     		movs	r0, #1
+ 11590              	.LVL1025:
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11591              		.loc 1 474 12 view .LVU3851
+ 11592 0094 EFE7     		b	.L588
+ 11593              		.cfi_endproc
+ 11594              	.LFE331:
+ 11596              		.section	.text.HAL_MultiProcessor_Init,"ax",%progbits
+ 11597              		.align	1
+ 11598              		.global	HAL_MultiProcessor_Init
+ 11599              		.syntax unified
+ 11600              		.thumb
+ 11601              		.thumb_func
+ 11603              	HAL_MultiProcessor_Init:
+ 11604              	.LVL1026:
+ 11605              	.LFB332:
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 11606              		.loc 1 551 1 is_stmt 1 view -0
+ 11607              		.cfi_startproc
+ 11608              		@ args = 0, pretend = 0, frame = 0
+ 11609              		@ frame_needed = 0, uses_anonymous_args = 0
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11610              		.loc 1 553 3 view .LVU3853
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11611              		.loc 1 553 6 is_stmt 0 view .LVU3854
+ 11612 0000 0028     		cmp	r0, #0
+ 11613 0002 42D0     		beq	.L605
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check the UART handle allocation */
+ 11614              		.loc 1 551 1 view .LVU3855
+ARM GAS  /tmp/cceWHrnJ.s 			page 366
+
+
+ 11615 0004 70B5     		push	{r4, r5, r6, lr}
+ 11616              	.LCFI52:
+ 11617              		.cfi_def_cfa_offset 16
+ 11618              		.cfi_offset 4, -16
+ 11619              		.cfi_offset 5, -12
+ 11620              		.cfi_offset 6, -8
+ 11621              		.cfi_offset 14, -4
+ 11622 0006 0E46     		mov	r6, r1
+ 11623 0008 1546     		mov	r5, r2
+ 11624 000a 0446     		mov	r4, r0
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11625              		.loc 1 559 3 is_stmt 1 view .LVU3856
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11626              		.loc 1 561 3 view .LVU3857
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11627              		.loc 1 561 12 is_stmt 0 view .LVU3858
+ 11628 000c D0F88430 		ldr	r3, [r0, #132]
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11629              		.loc 1 561 6 view .LVU3859
+ 11630 0010 53B3     		cbz	r3, .L610
+ 11631              	.LVL1027:
+ 11632              	.L602:
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11633              		.loc 1 582 3 is_stmt 1 view .LVU3860
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11634              		.loc 1 582 17 is_stmt 0 view .LVU3861
+ 11635 0012 2423     		movs	r3, #36
+ 11636 0014 C4F88430 		str	r3, [r4, #132]
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11637              		.loc 1 584 3 is_stmt 1 view .LVU3862
+ 11638 0018 2268     		ldr	r2, [r4]
+ 11639 001a 1368     		ldr	r3, [r2]
+ 11640 001c 23F00103 		bic	r3, r3, #1
+ 11641 0020 1360     		str	r3, [r2]
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11642              		.loc 1 587 3 view .LVU3863
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11643              		.loc 1 587 7 is_stmt 0 view .LVU3864
+ 11644 0022 2046     		mov	r0, r4
+ 11645 0024 FFF7FEFF 		bl	UART_SetConfig
+ 11646              	.LVL1028:
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11647              		.loc 1 587 6 view .LVU3865
+ 11648 0028 0128     		cmp	r0, #1
+ 11649 002a 1CD0     		beq	.L601
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11650              		.loc 1 592 3 is_stmt 1 view .LVU3866
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11651              		.loc 1 592 26 is_stmt 0 view .LVU3867
+ 11652 002c A36A     		ldr	r3, [r4, #40]
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11653              		.loc 1 592 6 view .LVU3868
+ 11654 002e 03BB     		cbnz	r3, .L611
+ 11655              	.L603:
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ 11656              		.loc 1 600 3 is_stmt 1 view .LVU3869
+ 11657 0030 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/cceWHrnJ.s 			page 367
+
+
+ 11658 0032 5368     		ldr	r3, [r2, #4]
+ 11659 0034 23F49043 		bic	r3, r3, #18432
+ 11660 0038 5360     		str	r3, [r2, #4]
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11661              		.loc 1 601 3 view .LVU3870
+ 11662 003a 2268     		ldr	r2, [r4]
+ 11663 003c 9368     		ldr	r3, [r2, #8]
+ 11664 003e 23F02A03 		bic	r3, r3, #42
+ 11665 0042 9360     		str	r3, [r2, #8]
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11666              		.loc 1 603 3 view .LVU3871
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 11667              		.loc 1 603 6 is_stmt 0 view .LVU3872
+ 11668 0044 B5F5006F 		cmp	r5, #2048
+ 11669 0048 17D0     		beq	.L612
+ 11670              	.L604:
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11671              		.loc 1 610 3 is_stmt 1 view .LVU3873
+ 11672 004a 2268     		ldr	r2, [r4]
+ 11673 004c 1368     		ldr	r3, [r2]
+ 11674 004e 23F40063 		bic	r3, r3, #2048
+ 11675 0052 2B43     		orrs	r3, r3, r5
+ 11676 0054 1360     		str	r3, [r2]
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11677              		.loc 1 612 3 view .LVU3874
+ 11678 0056 2268     		ldr	r2, [r4]
+ 11679 0058 1368     		ldr	r3, [r2]
+ 11680 005a 43F00103 		orr	r3, r3, #1
+ 11681 005e 1360     		str	r3, [r2]
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11682              		.loc 1 615 3 view .LVU3875
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11683              		.loc 1 615 11 is_stmt 0 view .LVU3876
+ 11684 0060 2046     		mov	r0, r4
+ 11685 0062 FFF7FEFF 		bl	UART_CheckIdleState
+ 11686              	.LVL1029:
+ 11687              	.L601:
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11688              		.loc 1 616 1 view .LVU3877
+ 11689 0066 70BD     		pop	{r4, r5, r6, pc}
+ 11690              	.LVL1030:
+ 11691              	.L610:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11692              		.loc 1 564 5 is_stmt 1 view .LVU3878
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11693              		.loc 1 564 17 is_stmt 0 view .LVU3879
+ 11694 0068 80F88030 		strb	r3, [r0, #128]
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 11695              		.loc 1 578 5 is_stmt 1 view .LVU3880
+ 11696 006c FFF7FEFF 		bl	HAL_UART_MspInit
+ 11697              	.LVL1031:
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 11698              		.loc 1 578 5 is_stmt 0 view .LVU3881
+ 11699 0070 CFE7     		b	.L602
+ 11700              	.L611:
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11701              		.loc 1 594 5 is_stmt 1 view .LVU3882
+ARM GAS  /tmp/cceWHrnJ.s 			page 368
+
+
+ 11702 0072 2046     		mov	r0, r4
+ 11703 0074 FFF7FEFF 		bl	UART_AdvFeatureConfig
+ 11704              	.LVL1032:
+ 11705 0078 DAE7     		b	.L603
+ 11706              	.L612:
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11707              		.loc 1 606 5 view .LVU3883
+ 11708 007a 2268     		ldr	r2, [r4]
+ 11709 007c 5368     		ldr	r3, [r2, #4]
+ 11710 007e 23F07F43 		bic	r3, r3, #-16777216
+ 11711 0082 43EA0663 		orr	r3, r3, r6, lsl #24
+ 11712 0086 5360     		str	r3, [r2, #4]
+ 11713 0088 DFE7     		b	.L604
+ 11714              	.LVL1033:
+ 11715              	.L605:
+ 11716              	.LCFI53:
+ 11717              		.cfi_def_cfa_offset 0
+ 11718              		.cfi_restore 4
+ 11719              		.cfi_restore 5
+ 11720              		.cfi_restore 6
+ 11721              		.cfi_restore 14
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 11722              		.loc 1 555 12 is_stmt 0 view .LVU3884
+ 11723 008a 0120     		movs	r0, #1
+ 11724              	.LVL1034:
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11725              		.loc 1 616 1 view .LVU3885
+ 11726 008c 7047     		bx	lr
+ 11727              		.cfi_endproc
+ 11728              	.LFE332:
+ 11730              		.section	.text.HAL_MultiProcessor_EnableMuteMode,"ax",%progbits
+ 11731              		.align	1
+ 11732              		.global	HAL_MultiProcessor_EnableMuteMode
+ 11733              		.syntax unified
+ 11734              		.thumb
+ 11735              		.thumb_func
+ 11737              	HAL_MultiProcessor_EnableMuteMode:
+ 11738              	.LVL1035:
+ 11739              	.LFB364:
+2820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+ 11740              		.loc 1 2820 1 is_stmt 1 view -0
+ 11741              		.cfi_startproc
+ 11742              		@ args = 0, pretend = 0, frame = 0
+ 11743              		@ frame_needed = 0, uses_anonymous_args = 0
+2820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+ 11744              		.loc 1 2820 1 is_stmt 0 view .LVU3887
+ 11745 0000 08B5     		push	{r3, lr}
+ 11746              	.LCFI54:
+ 11747              		.cfi_def_cfa_offset 8
+ 11748              		.cfi_offset 3, -8
+ 11749              		.cfi_offset 14, -4
+2821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11750              		.loc 1 2821 3 is_stmt 1 view .LVU3888
+2821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11751              		.loc 1 2821 3 view .LVU3889
+ 11752 0002 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 11753 0006 012B     		cmp	r3, #1
+ARM GAS  /tmp/cceWHrnJ.s 			page 369
+
+
+ 11754 0008 14D0     		beq	.L616
+2821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11755              		.loc 1 2821 3 discriminator 2 view .LVU3890
+ 11756 000a 0123     		movs	r3, #1
+ 11757 000c 80F88030 		strb	r3, [r0, #128]
+2821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11758              		.loc 1 2821 3 discriminator 2 view .LVU3891
+2823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11759              		.loc 1 2823 3 discriminator 2 view .LVU3892
+2823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11760              		.loc 1 2823 17 is_stmt 0 discriminator 2 view .LVU3893
+ 11761 0010 2423     		movs	r3, #36
+ 11762 0012 C0F88430 		str	r3, [r0, #132]
+ 11763              	.L615:
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11764              		.loc 1 2826 3 is_stmt 1 discriminator 1 view .LVU3894
+ 11765              	.LBB956:
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11766              		.loc 1 2826 3 discriminator 1 view .LVU3895
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11767              		.loc 1 2826 3 discriminator 1 view .LVU3896
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11768              		.loc 1 2826 3 discriminator 1 view .LVU3897
+ 11769 0016 0268     		ldr	r2, [r0]
+ 11770              	.LVL1036:
+ 11771              	.LBB957:
+ 11772              	.LBI957:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 11773              		.loc 2 1151 31 discriminator 1 view .LVU3898
+ 11774              	.LBB958:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 11775              		.loc 2 1153 5 discriminator 1 view .LVU3899
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 11776              		.loc 2 1155 4 discriminator 1 view .LVU3900
+ 11777              		.syntax unified
+ 11778              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 11779 0018 52E8003F 		ldrex r3, [r2]
+ 11780              	@ 0 "" 2
+ 11781              	.LVL1037:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 11782              		.loc 2 1156 4 discriminator 1 view .LVU3901
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 11783              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU3902
+ 11784              		.thumb
+ 11785              		.syntax unified
+ 11786              	.LBE958:
+ 11787              	.LBE957:
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11788              		.loc 1 2826 3 discriminator 1 view .LVU3903
+ 11789 001c 43F40053 		orr	r3, r3, #8192
+ 11790              	.LVL1038:
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11791              		.loc 1 2826 3 is_stmt 1 discriminator 1 view .LVU3904
+ 11792              	.LBB959:
+ 11793              	.LBI959:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 11794              		.loc 2 1202 31 discriminator 1 view .LVU3905
+ARM GAS  /tmp/cceWHrnJ.s 			page 370
+
+
+ 11795              	.LBB960:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 11796              		.loc 2 1204 4 discriminator 1 view .LVU3906
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 11797              		.loc 2 1206 4 discriminator 1 view .LVU3907
+ 11798              		.syntax unified
+ 11799              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 11800 0020 42E80031 		strex r1, r3, [r2]
+ 11801              	@ 0 "" 2
+ 11802              	.LVL1039:
+ 11803              		.loc 2 1207 4 discriminator 1 view .LVU3908
+ 11804              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU3909
+ 11805              		.thumb
+ 11806              		.syntax unified
+ 11807              	.LBE960:
+ 11808              	.LBE959:
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11809              		.loc 1 2826 3 discriminator 1 view .LVU3910
+ 11810 0024 0029     		cmp	r1, #0
+ 11811 0026 F6D1     		bne	.L615
+ 11812              	.LBE956:
+2826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11813              		.loc 1 2826 3 is_stmt 1 discriminator 2 view .LVU3911
+2828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11814              		.loc 1 2828 3 discriminator 2 view .LVU3912
+2828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11815              		.loc 1 2828 17 is_stmt 0 discriminator 2 view .LVU3913
+ 11816 0028 2023     		movs	r3, #32
+ 11817              	.LVL1040:
+2828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11818              		.loc 1 2828 17 discriminator 2 view .LVU3914
+ 11819 002a C0F88430 		str	r3, [r0, #132]
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11820              		.loc 1 2830 3 is_stmt 1 discriminator 2 view .LVU3915
+2830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11821              		.loc 1 2830 11 is_stmt 0 discriminator 2 view .LVU3916
+ 11822 002e FFF7FEFF 		bl	UART_CheckIdleState
+ 11823              	.LVL1041:
+ 11824              	.L614:
+2831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11825              		.loc 1 2831 1 view .LVU3917
+ 11826 0032 08BD     		pop	{r3, pc}
+ 11827              	.LVL1042:
+ 11828              	.L616:
+2821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11829              		.loc 1 2821 3 view .LVU3918
+ 11830 0034 0220     		movs	r0, #2
+ 11831              	.LVL1043:
+2821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11832              		.loc 1 2821 3 view .LVU3919
+ 11833 0036 FCE7     		b	.L614
+ 11834              		.cfi_endproc
+ 11835              	.LFE364:
+ 11837              		.section	.text.HAL_MultiProcessor_DisableMuteMode,"ax",%progbits
+ 11838              		.align	1
+ 11839              		.global	HAL_MultiProcessor_DisableMuteMode
+ 11840              		.syntax unified
+ARM GAS  /tmp/cceWHrnJ.s 			page 371
+
+
+ 11841              		.thumb
+ 11842              		.thumb_func
+ 11844              	HAL_MultiProcessor_DisableMuteMode:
+ 11845              	.LVL1044:
+ 11846              	.LFB365:
+2840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+ 11847              		.loc 1 2840 1 is_stmt 1 view -0
+ 11848              		.cfi_startproc
+ 11849              		@ args = 0, pretend = 0, frame = 0
+ 11850              		@ frame_needed = 0, uses_anonymous_args = 0
+2840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   __HAL_LOCK(huart);
+ 11851              		.loc 1 2840 1 is_stmt 0 view .LVU3921
+ 11852 0000 08B5     		push	{r3, lr}
+ 11853              	.LCFI55:
+ 11854              		.cfi_def_cfa_offset 8
+ 11855              		.cfi_offset 3, -8
+ 11856              		.cfi_offset 14, -4
+2841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11857              		.loc 1 2841 3 is_stmt 1 view .LVU3922
+2841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11858              		.loc 1 2841 3 view .LVU3923
+ 11859 0002 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 11860 0006 012B     		cmp	r3, #1
+ 11861 0008 14D0     		beq	.L621
+2841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11862              		.loc 1 2841 3 discriminator 2 view .LVU3924
+ 11863 000a 0123     		movs	r3, #1
+ 11864 000c 80F88030 		strb	r3, [r0, #128]
+2841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11865              		.loc 1 2841 3 discriminator 2 view .LVU3925
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11866              		.loc 1 2843 3 discriminator 2 view .LVU3926
+2843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11867              		.loc 1 2843 17 is_stmt 0 discriminator 2 view .LVU3927
+ 11868 0010 2423     		movs	r3, #36
+ 11869 0012 C0F88430 		str	r3, [r0, #132]
+ 11870              	.L620:
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11871              		.loc 1 2846 3 is_stmt 1 discriminator 1 view .LVU3928
+ 11872              	.LBB961:
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11873              		.loc 1 2846 3 discriminator 1 view .LVU3929
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11874              		.loc 1 2846 3 discriminator 1 view .LVU3930
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11875              		.loc 1 2846 3 discriminator 1 view .LVU3931
+ 11876 0016 0268     		ldr	r2, [r0]
+ 11877              	.LVL1045:
+ 11878              	.LBB962:
+ 11879              	.LBI962:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 11880              		.loc 2 1151 31 discriminator 1 view .LVU3932
+ 11881              	.LBB963:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 11882              		.loc 2 1153 5 discriminator 1 view .LVU3933
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 11883              		.loc 2 1155 4 discriminator 1 view .LVU3934
+ARM GAS  /tmp/cceWHrnJ.s 			page 372
+
+
+ 11884              		.syntax unified
+ 11885              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 11886 0018 52E8003F 		ldrex r3, [r2]
+ 11887              	@ 0 "" 2
+ 11888              	.LVL1046:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 11889              		.loc 2 1156 4 discriminator 1 view .LVU3935
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 11890              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU3936
+ 11891              		.thumb
+ 11892              		.syntax unified
+ 11893              	.LBE963:
+ 11894              	.LBE962:
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11895              		.loc 1 2846 3 discriminator 1 view .LVU3937
+ 11896 001c 23F40053 		bic	r3, r3, #8192
+ 11897              	.LVL1047:
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11898              		.loc 1 2846 3 is_stmt 1 discriminator 1 view .LVU3938
+ 11899              	.LBB964:
+ 11900              	.LBI964:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 11901              		.loc 2 1202 31 discriminator 1 view .LVU3939
+ 11902              	.LBB965:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 11903              		.loc 2 1204 4 discriminator 1 view .LVU3940
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 11904              		.loc 2 1206 4 discriminator 1 view .LVU3941
+ 11905              		.syntax unified
+ 11906              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 11907 0020 42E80031 		strex r1, r3, [r2]
+ 11908              	@ 0 "" 2
+ 11909              	.LVL1048:
+ 11910              		.loc 2 1207 4 discriminator 1 view .LVU3942
+ 11911              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU3943
+ 11912              		.thumb
+ 11913              		.syntax unified
+ 11914              	.LBE965:
+ 11915              	.LBE964:
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11916              		.loc 1 2846 3 discriminator 1 view .LVU3944
+ 11917 0024 0029     		cmp	r1, #0
+ 11918 0026 F6D1     		bne	.L620
+ 11919              	.LBE961:
+2846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11920              		.loc 1 2846 3 is_stmt 1 discriminator 2 view .LVU3945
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11921              		.loc 1 2848 3 discriminator 2 view .LVU3946
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11922              		.loc 1 2848 17 is_stmt 0 discriminator 2 view .LVU3947
+ 11923 0028 2023     		movs	r3, #32
+ 11924              	.LVL1049:
+2848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11925              		.loc 1 2848 17 discriminator 2 view .LVU3948
+ 11926 002a C0F88430 		str	r3, [r0, #132]
+2850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11927              		.loc 1 2850 3 is_stmt 1 discriminator 2 view .LVU3949
+ARM GAS  /tmp/cceWHrnJ.s 			page 373
+
+
+2850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 11928              		.loc 1 2850 11 is_stmt 0 discriminator 2 view .LVU3950
+ 11929 002e FFF7FEFF 		bl	UART_CheckIdleState
+ 11930              	.LVL1050:
+ 11931              	.L619:
+2851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11932              		.loc 1 2851 1 view .LVU3951
+ 11933 0032 08BD     		pop	{r3, pc}
+ 11934              	.LVL1051:
+ 11935              	.L621:
+2841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11936              		.loc 1 2841 3 view .LVU3952
+ 11937 0034 0220     		movs	r0, #2
+ 11938              	.LVL1052:
+2841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11939              		.loc 1 2841 3 view .LVU3953
+ 11940 0036 FCE7     		b	.L619
+ 11941              		.cfi_endproc
+ 11942              	.LFE365:
+ 11944              		.section	.text.UART_Start_Receive_IT,"ax",%progbits
+ 11945              		.align	1
+ 11946              		.global	UART_Start_Receive_IT
+ 11947              		.syntax unified
+ 11948              		.thumb
+ 11949              		.thumb_func
+ 11951              	UART_Start_Receive_IT:
+ 11952              	.LVL1053:
+ 11953              	.LFB376:
+3431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->pRxBuffPtr  = pData;
+ 11954              		.loc 1 3431 1 is_stmt 1 view -0
+ 11955              		.cfi_startproc
+ 11956              		@ args = 0, pretend = 0, frame = 0
+ 11957              		@ frame_needed = 0, uses_anonymous_args = 0
+ 11958              		@ link register save eliminated.
+3431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->pRxBuffPtr  = pData;
+ 11959              		.loc 1 3431 1 is_stmt 0 view .LVU3955
+ 11960 0000 10B4     		push	{r4}
+ 11961              	.LCFI56:
+ 11962              		.cfi_def_cfa_offset 4
+ 11963              		.cfi_offset 4, -4
+3432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferSize  = Size;
+ 11964              		.loc 1 3432 3 is_stmt 1 view .LVU3956
+3432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferSize  = Size;
+ 11965              		.loc 1 3432 22 is_stmt 0 view .LVU3957
+ 11966 0002 8165     		str	r1, [r0, #88]
+3433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = Size;
+ 11967              		.loc 1 3433 3 is_stmt 1 view .LVU3958
+3433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferCount = Size;
+ 11968              		.loc 1 3433 22 is_stmt 0 view .LVU3959
+ 11969 0004 A0F85C20 		strh	r2, [r0, #92]	@ movhi
+3434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxISR       = NULL;
+ 11970              		.loc 1 3434 3 is_stmt 1 view .LVU3960
+3434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxISR       = NULL;
+ 11971              		.loc 1 3434 22 is_stmt 0 view .LVU3961
+ 11972 0008 A0F85E20 		strh	r2, [r0, #94]	@ movhi
+3435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11973              		.loc 1 3435 3 is_stmt 1 view .LVU3962
+ARM GAS  /tmp/cceWHrnJ.s 			page 374
+
+
+3435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11974              		.loc 1 3435 22 is_stmt 0 view .LVU3963
+ 11975 000c 0023     		movs	r3, #0
+ 11976 000e 0367     		str	r3, [r0, #112]
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11977              		.loc 1 3438 3 is_stmt 1 view .LVU3964
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11978              		.loc 1 3438 3 view .LVU3965
+ 11979 0010 8368     		ldr	r3, [r0, #8]
+ 11980 0012 B3F5805F 		cmp	r3, #4096
+ 11981 0016 06D0     		beq	.L644
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11982              		.loc 1 3438 3 discriminator 2 view .LVU3966
+ 11983 0018 A3B9     		cbnz	r3, .L627
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11984              		.loc 1 3438 3 discriminator 5 view .LVU3967
+ 11985 001a 0369     		ldr	r3, [r0, #16]
+ 11986 001c 73B9     		cbnz	r3, .L628
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11987              		.loc 1 3438 3 discriminator 7 view .LVU3968
+ 11988 001e FF23     		movs	r3, #255
+ 11989 0020 A0F86030 		strh	r3, [r0, #96]	@ movhi
+ 11990 0024 14E0     		b	.L626
+ 11991              	.L644:
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11992              		.loc 1 3438 3 discriminator 1 view .LVU3969
+ 11993 0026 0369     		ldr	r3, [r0, #16]
+ 11994 0028 23B9     		cbnz	r3, .L625
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 11995              		.loc 1 3438 3 discriminator 3 view .LVU3970
+ 11996 002a 40F2FF13 		movw	r3, #511
+ 11997 002e A0F86030 		strh	r3, [r0, #96]	@ movhi
+ 11998 0032 0DE0     		b	.L626
+ 11999              	.L625:
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12000              		.loc 1 3438 3 discriminator 4 view .LVU3971
+ 12001 0034 FF23     		movs	r3, #255
+ 12002 0036 A0F86030 		strh	r3, [r0, #96]	@ movhi
+ 12003 003a 09E0     		b	.L626
+ 12004              	.L628:
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12005              		.loc 1 3438 3 discriminator 8 view .LVU3972
+ 12006 003c 7F23     		movs	r3, #127
+ 12007 003e A0F86030 		strh	r3, [r0, #96]	@ movhi
+ 12008 0042 05E0     		b	.L626
+ 12009              	.L627:
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12010              		.loc 1 3438 3 discriminator 6 view .LVU3973
+ 12011 0044 B3F1805F 		cmp	r3, #268435456
+ 12012 0048 31D0     		beq	.L645
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12013              		.loc 1 3438 3 discriminator 10 view .LVU3974
+ 12014 004a 0023     		movs	r3, #0
+ 12015 004c A0F86030 		strh	r3, [r0, #96]	@ movhi
+ 12016              	.L626:
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12017              		.loc 1 3438 3 discriminator 13 view .LVU3975
+ARM GAS  /tmp/cceWHrnJ.s 			page 375
+
+
+3440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 12018              		.loc 1 3440 3 discriminator 13 view .LVU3976
+3440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 12019              		.loc 1 3440 20 is_stmt 0 discriminator 13 view .LVU3977
+ 12020 0050 0023     		movs	r3, #0
+ 12021 0052 C0F88C30 		str	r3, [r0, #140]
+3441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12022              		.loc 1 3441 3 is_stmt 1 discriminator 13 view .LVU3978
+3441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12023              		.loc 1 3441 18 is_stmt 0 discriminator 13 view .LVU3979
+ 12024 0056 2223     		movs	r3, #34
+ 12025 0058 C0F88830 		str	r3, [r0, #136]
+ 12026              	.LVL1054:
+ 12027              	.L631:
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12028              		.loc 1 3444 3 is_stmt 1 discriminator 1 view .LVU3980
+ 12029              	.LBB966:
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12030              		.loc 1 3444 3 discriminator 1 view .LVU3981
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12031              		.loc 1 3444 3 discriminator 1 view .LVU3982
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12032              		.loc 1 3444 3 discriminator 1 view .LVU3983
+ 12033 005c 0168     		ldr	r1, [r0]
+ 12034              	.LVL1055:
+ 12035              	.LBB967:
+ 12036              	.LBI967:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12037              		.loc 2 1151 31 discriminator 1 view .LVU3984
+ 12038              	.LBB968:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12039              		.loc 2 1153 5 discriminator 1 view .LVU3985
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12040              		.loc 2 1155 4 discriminator 1 view .LVU3986
+ 12041 005e 01F10803 		add	r3, r1, #8
+ 12042              	.LVL1056:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12043              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU3987
+ 12044              		.syntax unified
+ 12045              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12046 0062 53E8003F 		ldrex r3, [r3]
+ 12047              	@ 0 "" 2
+ 12048              	.LVL1057:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12049              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU3988
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12050              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU3989
+ 12051              		.thumb
+ 12052              		.syntax unified
+ 12053              	.LBE968:
+ 12054              	.LBE967:
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12055              		.loc 1 3444 3 discriminator 1 view .LVU3990
+ 12056 0066 43F00103 		orr	r3, r3, #1
+ 12057              	.LVL1058:
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12058              		.loc 1 3444 3 is_stmt 1 discriminator 1 view .LVU3991
+ARM GAS  /tmp/cceWHrnJ.s 			page 376
+
+
+ 12059              	.LBB969:
+ 12060              	.LBI969:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12061              		.loc 2 1202 31 discriminator 1 view .LVU3992
+ 12062              	.LBB970:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12063              		.loc 2 1204 4 discriminator 1 view .LVU3993
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12064              		.loc 2 1206 4 discriminator 1 view .LVU3994
+ 12065 006a 0831     		adds	r1, r1, #8
+ 12066              	.LVL1059:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12067              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU3995
+ 12068              		.syntax unified
+ 12069              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12070 006c 41E80034 		strex r4, r3, [r1]
+ 12071              	@ 0 "" 2
+ 12072              	.LVL1060:
+ 12073              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU3996
+ 12074              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU3997
+ 12075              		.thumb
+ 12076              		.syntax unified
+ 12077              	.LBE970:
+ 12078              	.LBE969:
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12079              		.loc 1 3444 3 discriminator 1 view .LVU3998
+ 12080 0070 002C     		cmp	r4, #0
+ 12081 0072 F3D1     		bne	.L631
+ 12082              	.LBE966:
+3444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12083              		.loc 1 3444 3 is_stmt 1 discriminator 2 view .LVU3999
+3447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12084              		.loc 1 3447 3 discriminator 2 view .LVU4000
+3447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12085              		.loc 1 3447 13 is_stmt 0 discriminator 2 view .LVU4001
+ 12086 0074 436E     		ldr	r3, [r0, #100]
+ 12087              	.LVL1061:
+3447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12088              		.loc 1 3447 6 discriminator 2 view .LVU4002
+ 12089 0076 B3F1005F 		cmp	r3, #536870912
+ 12090 007a 22D0     		beq	.L646
+ 12091              	.L632:
+3471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12092              		.loc 1 3471 5 is_stmt 1 view .LVU4003
+3471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12093              		.loc 1 3471 21 is_stmt 0 view .LVU4004
+ 12094 007c 8368     		ldr	r3, [r0, #8]
+3471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12095              		.loc 1 3471 8 view .LVU4005
+ 12096 007e B3F5805F 		cmp	r3, #4096
+ 12097 0082 49D0     		beq	.L647
+ 12098              	.L639:
+3477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12099              		.loc 1 3477 7 is_stmt 1 view .LVU4006
+3477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12100              		.loc 1 3477 20 is_stmt 0 view .LVU4007
+ 12101 0084 2C4B     		ldr	r3, .L649
+ARM GAS  /tmp/cceWHrnJ.s 			page 377
+
+
+ 12102 0086 0367     		str	r3, [r0, #112]
+ 12103              	.L640:
+3480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12104              		.loc 1 3480 5 is_stmt 1 view .LVU4008
+3480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12105              		.loc 1 3480 5 view .LVU4009
+ 12106 0088 0023     		movs	r3, #0
+ 12107 008a 80F88030 		strb	r3, [r0, #128]
+3480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12108              		.loc 1 3480 5 view .LVU4010
+3483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12109              		.loc 1 3483 5 view .LVU4011
+3483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12110              		.loc 1 3483 20 is_stmt 0 view .LVU4012
+ 12111 008e 0369     		ldr	r3, [r0, #16]
+3483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12112              		.loc 1 3483 8 view .LVU4013
+ 12113 0090 002B     		cmp	r3, #0
+ 12114 0092 47D0     		beq	.L641
+ 12115              	.LVL1062:
+ 12116              	.L642:
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12117              		.loc 1 3485 7 is_stmt 1 discriminator 1 view .LVU4014
+ 12118              	.LBB971:
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12119              		.loc 1 3485 7 discriminator 1 view .LVU4015
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12120              		.loc 1 3485 7 discriminator 1 view .LVU4016
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12121              		.loc 1 3485 7 discriminator 1 view .LVU4017
+ 12122 0094 0268     		ldr	r2, [r0]
+ 12123              	.LVL1063:
+ 12124              	.LBB972:
+ 12125              	.LBI972:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12126              		.loc 2 1151 31 discriminator 1 view .LVU4018
+ 12127              	.LBB973:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12128              		.loc 2 1153 5 discriminator 1 view .LVU4019
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12129              		.loc 2 1155 4 discriminator 1 view .LVU4020
+ 12130              		.syntax unified
+ 12131              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12132 0096 52E8003F 		ldrex r3, [r2]
+ 12133              	@ 0 "" 2
+ 12134              	.LVL1064:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12135              		.loc 2 1156 4 discriminator 1 view .LVU4021
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12136              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU4022
+ 12137              		.thumb
+ 12138              		.syntax unified
+ 12139              	.LBE973:
+ 12140              	.LBE972:
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12141              		.loc 1 3485 7 discriminator 1 view .LVU4023
+ 12142 009a 43F49073 		orr	r3, r3, #288
+ARM GAS  /tmp/cceWHrnJ.s 			page 378
+
+
+ 12143              	.LVL1065:
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12144              		.loc 1 3485 7 is_stmt 1 discriminator 1 view .LVU4024
+ 12145              	.LBB974:
+ 12146              	.LBI974:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12147              		.loc 2 1202 31 discriminator 1 view .LVU4025
+ 12148              	.LBB975:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12149              		.loc 2 1204 4 discriminator 1 view .LVU4026
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12150              		.loc 2 1206 4 discriminator 1 view .LVU4027
+ 12151              		.syntax unified
+ 12152              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12153 009e 42E80031 		strex r1, r3, [r2]
+ 12154              	@ 0 "" 2
+ 12155              	.LVL1066:
+ 12156              		.loc 2 1207 4 discriminator 1 view .LVU4028
+ 12157              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU4029
+ 12158              		.thumb
+ 12159              		.syntax unified
+ 12160              	.LBE975:
+ 12161              	.LBE974:
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12162              		.loc 1 3485 7 discriminator 1 view .LVU4030
+ 12163 00a2 0029     		cmp	r1, #0
+ 12164 00a4 F6D1     		bne	.L642
+ 12165              	.LVL1067:
+ 12166              	.L638:
+3485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12167              		.loc 1 3485 7 discriminator 1 view .LVU4031
+ 12168              	.LBE971:
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }  
+ 12169              		.loc 1 3489 7 is_stmt 1 discriminator 2 view .LVU4032
+3492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 12170              		.loc 1 3492 3 discriminator 2 view .LVU4033
+3493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12171              		.loc 1 3493 1 is_stmt 0 discriminator 2 view .LVU4034
+ 12172 00a6 0020     		movs	r0, #0
+ 12173              	.LVL1068:
+3493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12174              		.loc 1 3493 1 discriminator 2 view .LVU4035
+ 12175 00a8 5DF8044B 		ldr	r4, [sp], #4
+ 12176              	.LCFI57:
+ 12177              		.cfi_remember_state
+ 12178              		.cfi_restore 4
+ 12179              		.cfi_def_cfa_offset 0
+ 12180 00ac 7047     		bx	lr
+ 12181              	.LVL1069:
+ 12182              	.L645:
+ 12183              	.LCFI58:
+ 12184              		.cfi_restore_state
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12185              		.loc 1 3438 3 is_stmt 1 discriminator 9 view .LVU4036
+ 12186 00ae 0369     		ldr	r3, [r0, #16]
+ 12187 00b0 1BB9     		cbnz	r3, .L630
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 379
+
+
+ 12188              		.loc 1 3438 3 discriminator 11 view .LVU4037
+ 12189 00b2 7F23     		movs	r3, #127
+ 12190 00b4 A0F86030 		strh	r3, [r0, #96]	@ movhi
+ 12191 00b8 CAE7     		b	.L626
+ 12192              	.L630:
+3438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12193              		.loc 1 3438 3 discriminator 12 view .LVU4038
+ 12194 00ba 3F23     		movs	r3, #63
+ 12195 00bc A0F86030 		strh	r3, [r0, #96]	@ movhi
+ 12196 00c0 C6E7     		b	.L626
+ 12197              	.LVL1070:
+ 12198              	.L646:
+3447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12199              		.loc 1 3447 66 is_stmt 0 discriminator 1 view .LVU4039
+ 12200 00c2 B0F86830 		ldrh	r3, [r0, #104]
+3447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12201              		.loc 1 3447 49 discriminator 1 view .LVU4040
+ 12202 00c6 9342     		cmp	r3, r2
+ 12203 00c8 D8D8     		bhi	.L632
+3450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12204              		.loc 1 3450 5 is_stmt 1 view .LVU4041
+3450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12205              		.loc 1 3450 21 is_stmt 0 view .LVU4042
+ 12206 00ca 8368     		ldr	r3, [r0, #8]
+3450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12207              		.loc 1 3450 8 view .LVU4043
+ 12208 00cc B3F5805F 		cmp	r3, #4096
+ 12209 00d0 1CD0     		beq	.L648
+ 12210              	.L633:
+3456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12211              		.loc 1 3456 7 is_stmt 1 view .LVU4044
+3456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12212              		.loc 1 3456 20 is_stmt 0 view .LVU4045
+ 12213 00d2 1A4B     		ldr	r3, .L649+4
+ 12214 00d4 0367     		str	r3, [r0, #112]
+ 12215              	.L634:
+3459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12216              		.loc 1 3459 5 is_stmt 1 view .LVU4046
+3459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12217              		.loc 1 3459 5 view .LVU4047
+ 12218 00d6 0023     		movs	r3, #0
+ 12219 00d8 80F88030 		strb	r3, [r0, #128]
+3459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12220              		.loc 1 3459 5 view .LVU4048
+3462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12221              		.loc 1 3462 5 view .LVU4049
+3462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12222              		.loc 1 3462 20 is_stmt 0 view .LVU4050
+ 12223 00dc 0369     		ldr	r3, [r0, #16]
+3462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12224              		.loc 1 3462 8 view .LVU4051
+ 12225 00de 43B1     		cbz	r3, .L637
+ 12226              	.LVL1071:
+ 12227              	.L636:
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12228              		.loc 1 3464 7 is_stmt 1 discriminator 1 view .LVU4052
+ 12229              	.LBB976:
+ARM GAS  /tmp/cceWHrnJ.s 			page 380
+
+
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12230              		.loc 1 3464 7 discriminator 1 view .LVU4053
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12231              		.loc 1 3464 7 discriminator 1 view .LVU4054
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12232              		.loc 1 3464 7 discriminator 1 view .LVU4055
+ 12233 00e0 0268     		ldr	r2, [r0]
+ 12234              	.LVL1072:
+ 12235              	.LBB977:
+ 12236              	.LBI977:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12237              		.loc 2 1151 31 discriminator 1 view .LVU4056
+ 12238              	.LBB978:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12239              		.loc 2 1153 5 discriminator 1 view .LVU4057
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12240              		.loc 2 1155 4 discriminator 1 view .LVU4058
+ 12241              		.syntax unified
+ 12242              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12243 00e2 52E8003F 		ldrex r3, [r2]
+ 12244              	@ 0 "" 2
+ 12245              	.LVL1073:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12246              		.loc 2 1156 4 discriminator 1 view .LVU4059
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12247              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU4060
+ 12248              		.thumb
+ 12249              		.syntax unified
+ 12250              	.LBE978:
+ 12251              	.LBE977:
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12252              		.loc 1 3464 7 discriminator 1 view .LVU4061
+ 12253 00e6 43F48073 		orr	r3, r3, #256
+ 12254              	.LVL1074:
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12255              		.loc 1 3464 7 is_stmt 1 discriminator 1 view .LVU4062
+ 12256              	.LBB979:
+ 12257              	.LBI979:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12258              		.loc 2 1202 31 discriminator 1 view .LVU4063
+ 12259              	.LBB980:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12260              		.loc 2 1204 4 discriminator 1 view .LVU4064
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12261              		.loc 2 1206 4 discriminator 1 view .LVU4065
+ 12262              		.syntax unified
+ 12263              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12264 00ea 42E80031 		strex r1, r3, [r2]
+ 12265              	@ 0 "" 2
+ 12266              	.LVL1075:
+ 12267              		.loc 2 1207 4 discriminator 1 view .LVU4066
+ 12268              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU4067
+ 12269              		.thumb
+ 12270              		.syntax unified
+ 12271              	.LBE980:
+ 12272              	.LBE979:
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ARM GAS  /tmp/cceWHrnJ.s 			page 381
+
+
+ 12273              		.loc 1 3464 7 discriminator 1 view .LVU4068
+ 12274 00ee 0029     		cmp	r1, #0
+ 12275 00f0 F6D1     		bne	.L636
+ 12276              	.LVL1076:
+ 12277              	.L637:
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12278              		.loc 1 3464 7 discriminator 1 view .LVU4069
+ 12279              	.LBE976:
+3464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12280              		.loc 1 3464 7 is_stmt 1 discriminator 1 view .LVU4070
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12281              		.loc 1 3466 5 discriminator 1 view .LVU4071
+ 12282              	.LBB981:
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12283              		.loc 1 3466 5 discriminator 1 view .LVU4072
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12284              		.loc 1 3466 5 discriminator 1 view .LVU4073
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12285              		.loc 1 3466 5 discriminator 1 view .LVU4074
+ 12286 00f2 0268     		ldr	r2, [r0]
+ 12287              	.LVL1077:
+ 12288              	.LBB982:
+ 12289              	.LBI982:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12290              		.loc 2 1151 31 discriminator 1 view .LVU4075
+ 12291              	.LBB983:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12292              		.loc 2 1153 5 discriminator 1 view .LVU4076
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12293              		.loc 2 1155 4 discriminator 1 view .LVU4077
+ 12294 00f4 02F10803 		add	r3, r2, #8
+ 12295              	.LVL1078:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12296              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU4078
+ 12297              		.syntax unified
+ 12298              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12299 00f8 53E8003F 		ldrex r3, [r3]
+ 12300              	@ 0 "" 2
+ 12301              	.LVL1079:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12302              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU4079
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12303              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU4080
+ 12304              		.thumb
+ 12305              		.syntax unified
+ 12306              	.LBE983:
+ 12307              	.LBE982:
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12308              		.loc 1 3466 5 discriminator 1 view .LVU4081
+ 12309 00fc 43F08053 		orr	r3, r3, #268435456
+ 12310              	.LVL1080:
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12311              		.loc 1 3466 5 is_stmt 1 discriminator 1 view .LVU4082
+ 12312              	.LBB984:
+ 12313              	.LBI984:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12314              		.loc 2 1202 31 discriminator 1 view .LVU4083
+ARM GAS  /tmp/cceWHrnJ.s 			page 382
+
+
+ 12315              	.LBB985:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12316              		.loc 2 1204 4 discriminator 1 view .LVU4084
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12317              		.loc 2 1206 4 discriminator 1 view .LVU4085
+ 12318 0100 0832     		adds	r2, r2, #8
+ 12319              	.LVL1081:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12320              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU4086
+ 12321              		.syntax unified
+ 12322              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12323 0102 42E80031 		strex r1, r3, [r2]
+ 12324              	@ 0 "" 2
+ 12325              	.LVL1082:
+ 12326              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU4087
+ 12327              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU4088
+ 12328              		.thumb
+ 12329              		.syntax unified
+ 12330              	.LBE985:
+ 12331              	.LBE984:
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12332              		.loc 1 3466 5 discriminator 1 view .LVU4089
+ 12333 0106 0029     		cmp	r1, #0
+ 12334 0108 F3D1     		bne	.L637
+ 12335 010a CCE7     		b	.L638
+ 12336              	.LVL1083:
+ 12337              	.L648:
+3466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12338              		.loc 1 3466 5 discriminator 1 view .LVU4090
+ 12339              	.LBE981:
+3450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12340              		.loc 1 3450 71 discriminator 1 view .LVU4091
+ 12341 010c 0369     		ldr	r3, [r0, #16]
+3450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12342              		.loc 1 3450 56 discriminator 1 view .LVU4092
+ 12343 010e 002B     		cmp	r3, #0
+ 12344 0110 DFD1     		bne	.L633
+3452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12345              		.loc 1 3452 7 is_stmt 1 view .LVU4093
+3452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12346              		.loc 1 3452 20 is_stmt 0 view .LVU4094
+ 12347 0112 0B4B     		ldr	r3, .L649+8
+ 12348 0114 0367     		str	r3, [r0, #112]
+ 12349 0116 DEE7     		b	.L634
+ 12350              	.L647:
+3471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12351              		.loc 1 3471 71 discriminator 1 view .LVU4095
+ 12352 0118 0369     		ldr	r3, [r0, #16]
+3471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12353              		.loc 1 3471 56 discriminator 1 view .LVU4096
+ 12354 011a 002B     		cmp	r3, #0
+ 12355 011c B2D1     		bne	.L639
+3473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12356              		.loc 1 3473 7 is_stmt 1 view .LVU4097
+3473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12357              		.loc 1 3473 20 is_stmt 0 view .LVU4098
+ 12358 011e 094B     		ldr	r3, .L649+12
+ARM GAS  /tmp/cceWHrnJ.s 			page 383
+
+
+ 12359 0120 0367     		str	r3, [r0, #112]
+ 12360 0122 B1E7     		b	.L640
+ 12361              	.LVL1084:
+ 12362              	.L641:
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }  
+ 12363              		.loc 1 3489 7 is_stmt 1 discriminator 1 view .LVU4099
+ 12364              	.LBB986:
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }  
+ 12365              		.loc 1 3489 7 discriminator 1 view .LVU4100
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }  
+ 12366              		.loc 1 3489 7 discriminator 1 view .LVU4101
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }  
+ 12367              		.loc 1 3489 7 discriminator 1 view .LVU4102
+ 12368 0124 0268     		ldr	r2, [r0]
+ 12369              	.LVL1085:
+ 12370              	.LBB987:
+ 12371              	.LBI987:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12372              		.loc 2 1151 31 discriminator 1 view .LVU4103
+ 12373              	.LBB988:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12374              		.loc 2 1153 5 discriminator 1 view .LVU4104
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12375              		.loc 2 1155 4 discriminator 1 view .LVU4105
+ 12376              		.syntax unified
+ 12377              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12378 0126 52E8003F 		ldrex r3, [r2]
+ 12379              	@ 0 "" 2
+ 12380              	.LVL1086:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12381              		.loc 2 1156 4 discriminator 1 view .LVU4106
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12382              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU4107
+ 12383              		.thumb
+ 12384              		.syntax unified
+ 12385              	.LBE988:
+ 12386              	.LBE987:
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }  
+ 12387              		.loc 1 3489 7 discriminator 1 view .LVU4108
+ 12388 012a 43F02003 		orr	r3, r3, #32
+ 12389              	.LVL1087:
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }  
+ 12390              		.loc 1 3489 7 is_stmt 1 discriminator 1 view .LVU4109
+ 12391              	.LBB989:
+ 12392              	.LBI989:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12393              		.loc 2 1202 31 discriminator 1 view .LVU4110
+ 12394              	.LBB990:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12395              		.loc 2 1204 4 discriminator 1 view .LVU4111
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12396              		.loc 2 1206 4 discriminator 1 view .LVU4112
+ 12397              		.syntax unified
+ 12398              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12399 012e 42E80031 		strex r1, r3, [r2]
+ 12400              	@ 0 "" 2
+ 12401              	.LVL1088:
+ARM GAS  /tmp/cceWHrnJ.s 			page 384
+
+
+ 12402              		.loc 2 1207 4 discriminator 1 view .LVU4113
+ 12403              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU4114
+ 12404              		.thumb
+ 12405              		.syntax unified
+ 12406              	.LBE990:
+ 12407              	.LBE989:
+3489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }  
+ 12408              		.loc 1 3489 7 discriminator 1 view .LVU4115
+ 12409 0132 0029     		cmp	r1, #0
+ 12410 0134 F6D1     		bne	.L641
+ 12411 0136 B6E7     		b	.L638
+ 12412              	.L650:
+ 12413              		.align	2
+ 12414              	.L649:
+ 12415 0138 00000000 		.word	UART_RxISR_8BIT
+ 12416 013c 00000000 		.word	UART_RxISR_8BIT_FIFOEN
+ 12417 0140 00000000 		.word	UART_RxISR_16BIT_FIFOEN
+ 12418 0144 00000000 		.word	UART_RxISR_16BIT
+ 12419              	.LBE986:
+ 12420              		.cfi_endproc
+ 12421              	.LFE376:
+ 12423              		.section	.text.HAL_UART_Receive_IT,"ax",%progbits
+ 12424              		.align	1
+ 12425              		.global	HAL_UART_Receive_IT
+ 12426              		.syntax unified
+ 12427              		.thumb
+ 12428              		.thumb_func
+ 12430              	HAL_UART_Receive_IT:
+ 12431              	.LVL1089:
+ 12432              	.LFB339:
+1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Rx process is not already ongoing */
+ 12433              		.loc 1 1371 1 is_stmt 1 view -0
+ 12434              		.cfi_startproc
+ 12435              		@ args = 0, pretend = 0, frame = 0
+ 12436              		@ frame_needed = 0, uses_anonymous_args = 0
+1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Rx process is not already ongoing */
+ 12437              		.loc 1 1371 1 is_stmt 0 view .LVU4117
+ 12438 0000 38B5     		push	{r3, r4, r5, lr}
+ 12439              	.LCFI59:
+ 12440              		.cfi_def_cfa_offset 16
+ 12441              		.cfi_offset 3, -16
+ 12442              		.cfi_offset 4, -12
+ 12443              		.cfi_offset 5, -8
+ 12444              		.cfi_offset 14, -4
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12445              		.loc 1 1373 3 is_stmt 1 view .LVU4118
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12446              		.loc 1 1373 12 is_stmt 0 view .LVU4119
+ 12447 0002 D0F88830 		ldr	r3, [r0, #136]
+1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12448              		.loc 1 1373 6 view .LVU4120
+ 12449 0006 202B     		cmp	r3, #32
+ 12450 0008 1ED1     		bne	.L655
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12451              		.loc 1 1375 5 is_stmt 1 view .LVU4121
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12452              		.loc 1 1375 8 is_stmt 0 view .LVU4122
+ARM GAS  /tmp/cceWHrnJ.s 			page 385
+
+
+ 12453 000a F9B1     		cbz	r1, .L656
+1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12454              		.loc 1 1375 25 discriminator 1 view .LVU4123
+ 12455 000c 02B3     		cbz	r2, .L657
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12456              		.loc 1 1380 5 is_stmt 1 view .LVU4124
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12457              		.loc 1 1380 5 view .LVU4125
+ 12458 000e 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 12459 0012 012B     		cmp	r3, #1
+ 12460 0014 1ED0     		beq	.L658
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12461              		.loc 1 1380 5 discriminator 2 view .LVU4126
+ 12462 0016 0123     		movs	r3, #1
+ 12463 0018 80F88030 		strb	r3, [r0, #128]
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12464              		.loc 1 1380 5 discriminator 2 view .LVU4127
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12465              		.loc 1 1383 5 discriminator 2 view .LVU4128
+1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12466              		.loc 1 1383 26 is_stmt 0 discriminator 2 view .LVU4129
+ 12467 001c 0023     		movs	r3, #0
+ 12468 001e C366     		str	r3, [r0, #108]
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12469              		.loc 1 1385 5 is_stmt 1 discriminator 2 view .LVU4130
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12470              		.loc 1 1385 11 is_stmt 0 discriminator 2 view .LVU4131
+ 12471 0020 0368     		ldr	r3, [r0]
+1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12472              		.loc 1 1385 8 discriminator 2 view .LVU4132
+ 12473 0022 0D4C     		ldr	r4, .L660
+ 12474 0024 A342     		cmp	r3, r4
+ 12475 0026 0CD0     		beq	.L653
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 12476              		.loc 1 1388 7 is_stmt 1 view .LVU4133
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 12477              		.loc 1 1388 11 is_stmt 0 view .LVU4134
+ 12478 0028 5B68     		ldr	r3, [r3, #4]
+1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 12479              		.loc 1 1388 10 view .LVU4135
+ 12480 002a 13F4000F 		tst	r3, #8388608
+ 12481 002e 08D0     		beq	.L653
+ 12482              	.L654:
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12483              		.loc 1 1391 9 is_stmt 1 discriminator 1 view .LVU4136
+ 12484              	.LBB991:
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12485              		.loc 1 1391 9 discriminator 1 view .LVU4137
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12486              		.loc 1 1391 9 discriminator 1 view .LVU4138
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12487              		.loc 1 1391 9 discriminator 1 view .LVU4139
+ 12488 0030 0468     		ldr	r4, [r0]
+ 12489              	.LVL1090:
+ 12490              	.LBB992:
+ 12491              	.LBI992:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/cceWHrnJ.s 			page 386
+
+
+ 12492              		.loc 2 1151 31 discriminator 1 view .LVU4140
+ 12493              	.LBB993:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12494              		.loc 2 1153 5 discriminator 1 view .LVU4141
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12495              		.loc 2 1155 4 discriminator 1 view .LVU4142
+ 12496              		.syntax unified
+ 12497              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12498 0032 54E8003F 		ldrex r3, [r4]
+ 12499              	@ 0 "" 2
+ 12500              	.LVL1091:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12501              		.loc 2 1156 4 discriminator 1 view .LVU4143
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12502              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU4144
+ 12503              		.thumb
+ 12504              		.syntax unified
+ 12505              	.LBE993:
+ 12506              	.LBE992:
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12507              		.loc 1 1391 9 discriminator 1 view .LVU4145
+ 12508 0036 43F08063 		orr	r3, r3, #67108864
+ 12509              	.LVL1092:
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12510              		.loc 1 1391 9 is_stmt 1 discriminator 1 view .LVU4146
+ 12511              	.LBB994:
+ 12512              	.LBI994:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12513              		.loc 2 1202 31 discriminator 1 view .LVU4147
+ 12514              	.LBB995:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12515              		.loc 2 1204 4 discriminator 1 view .LVU4148
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12516              		.loc 2 1206 4 discriminator 1 view .LVU4149
+ 12517              		.syntax unified
+ 12518              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12519 003a 44E80035 		strex r5, r3, [r4]
+ 12520              	@ 0 "" 2
+ 12521              	.LVL1093:
+ 12522              		.loc 2 1207 4 discriminator 1 view .LVU4150
+ 12523              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU4151
+ 12524              		.thumb
+ 12525              		.syntax unified
+ 12526              	.LBE995:
+ 12527              	.LBE994:
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12528              		.loc 1 1391 9 discriminator 1 view .LVU4152
+ 12529 003e 002D     		cmp	r5, #0
+ 12530 0040 F6D1     		bne	.L654
+ 12531              	.LVL1094:
+ 12532              	.L653:
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12533              		.loc 1 1391 9 discriminator 1 view .LVU4153
+ 12534              	.LBE991:
+1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12535              		.loc 1 1391 9 is_stmt 1 discriminator 2 view .LVU4154
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ARM GAS  /tmp/cceWHrnJ.s 			page 387
+
+
+ 12536              		.loc 1 1395 5 discriminator 2 view .LVU4155
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12537              		.loc 1 1395 13 is_stmt 0 discriminator 2 view .LVU4156
+ 12538 0042 FFF7FEFF 		bl	UART_Start_Receive_IT
+ 12539              	.LVL1095:
+1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12540              		.loc 1 1395 13 discriminator 2 view .LVU4157
+ 12541 0046 00E0     		b	.L652
+ 12542              	.LVL1096:
+ 12543              	.L655:
+1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12544              		.loc 1 1399 12 view .LVU4158
+ 12545 0048 0220     		movs	r0, #2
+ 12546              	.LVL1097:
+ 12547              	.L652:
+1401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12548              		.loc 1 1401 1 view .LVU4159
+ 12549 004a 38BD     		pop	{r3, r4, r5, pc}
+ 12550              	.LVL1098:
+ 12551              	.L656:
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12552              		.loc 1 1377 14 view .LVU4160
+ 12553 004c 0120     		movs	r0, #1
+ 12554              	.LVL1099:
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12555              		.loc 1 1377 14 view .LVU4161
+ 12556 004e FCE7     		b	.L652
+ 12557              	.LVL1100:
+ 12558              	.L657:
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12559              		.loc 1 1377 14 view .LVU4162
+ 12560 0050 0120     		movs	r0, #1
+ 12561              	.LVL1101:
+1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12562              		.loc 1 1377 14 view .LVU4163
+ 12563 0052 FAE7     		b	.L652
+ 12564              	.LVL1102:
+ 12565              	.L658:
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12566              		.loc 1 1380 5 view .LVU4164
+ 12567 0054 0220     		movs	r0, #2
+ 12568              	.LVL1103:
+1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12569              		.loc 1 1380 5 view .LVU4165
+ 12570 0056 F8E7     		b	.L652
+ 12571              	.L661:
+ 12572              		.align	2
+ 12573              	.L660:
+ 12574 0058 00800040 		.word	1073774592
+ 12575              		.cfi_endproc
+ 12576              	.LFE339:
+ 12578              		.section	.text.UART_Start_Receive_DMA,"ax",%progbits
+ 12579              		.align	1
+ 12580              		.global	UART_Start_Receive_DMA
+ 12581              		.syntax unified
+ 12582              		.thumb
+ 12583              		.thumb_func
+ARM GAS  /tmp/cceWHrnJ.s 			page 388
+
+
+ 12585              	UART_Start_Receive_DMA:
+ 12586              	.LVL1104:
+ 12587              	.LFB377:
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->pRxBuffPtr = pData;
+ 12588              		.loc 1 3507 1 is_stmt 1 view -0
+ 12589              		.cfi_startproc
+ 12590              		@ args = 0, pretend = 0, frame = 0
+ 12591              		@ frame_needed = 0, uses_anonymous_args = 0
+3507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->pRxBuffPtr = pData;
+ 12592              		.loc 1 3507 1 is_stmt 0 view .LVU4167
+ 12593 0000 10B5     		push	{r4, lr}
+ 12594              	.LCFI60:
+ 12595              		.cfi_def_cfa_offset 8
+ 12596              		.cfi_offset 4, -8
+ 12597              		.cfi_offset 14, -4
+ 12598 0002 0446     		mov	r4, r0
+ 12599 0004 1346     		mov	r3, r2
+3508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferSize = Size;
+ 12600              		.loc 1 3508 3 is_stmt 1 view .LVU4168
+3508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxXferSize = Size;
+ 12601              		.loc 1 3508 21 is_stmt 0 view .LVU4169
+ 12602 0006 8165     		str	r1, [r0, #88]
+3509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12603              		.loc 1 3509 3 is_stmt 1 view .LVU4170
+3509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12604              		.loc 1 3509 21 is_stmt 0 view .LVU4171
+ 12605 0008 A0F85C20 		strh	r2, [r0, #92]	@ movhi
+3511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 12606              		.loc 1 3511 3 is_stmt 1 view .LVU4172
+3511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 12607              		.loc 1 3511 20 is_stmt 0 view .LVU4173
+ 12608 000c 0022     		movs	r2, #0
+ 12609              	.LVL1105:
+3511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 12610              		.loc 1 3511 20 view .LVU4174
+ 12611 000e C0F88C20 		str	r2, [r0, #140]
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12612              		.loc 1 3512 3 is_stmt 1 view .LVU4175
+3512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12613              		.loc 1 3512 18 is_stmt 0 view .LVU4176
+ 12614 0012 2222     		movs	r2, #34
+ 12615 0014 C0F88820 		str	r2, [r0, #136]
+3514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12616              		.loc 1 3514 3 is_stmt 1 view .LVU4177
+3514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12617              		.loc 1 3514 12 is_stmt 0 view .LVU4178
+ 12618 0018 C26F     		ldr	r2, [r0, #124]
+3514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12619              		.loc 1 3514 6 view .LVU4179
+ 12620 001a 8AB1     		cbz	r2, .L663
+3517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12621              		.loc 1 3517 5 is_stmt 1 view .LVU4180
+3517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12622              		.loc 1 3517 37 is_stmt 0 view .LVU4181
+ 12623 001c 2249     		ldr	r1, .L671
+ 12624              	.LVL1106:
+3517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ARM GAS  /tmp/cceWHrnJ.s 			page 389
+
+
+ 12625              		.loc 1 3517 37 view .LVU4182
+ 12626 001e D162     		str	r1, [r2, #44]
+ 12627              	.LVL1107:
+3520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12628              		.loc 1 3520 5 is_stmt 1 view .LVU4183
+3520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12629              		.loc 1 3520 10 is_stmt 0 view .LVU4184
+ 12630 0020 C26F     		ldr	r2, [r0, #124]
+3520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12631              		.loc 1 3520 41 view .LVU4185
+ 12632 0022 2249     		ldr	r1, .L671+4
+ 12633 0024 1163     		str	r1, [r2, #48]
+3523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12634              		.loc 1 3523 5 is_stmt 1 view .LVU4186
+3523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12635              		.loc 1 3523 10 is_stmt 0 view .LVU4187
+ 12636 0026 C26F     		ldr	r2, [r0, #124]
+3523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12637              		.loc 1 3523 38 view .LVU4188
+ 12638 0028 2149     		ldr	r1, .L671+8
+ 12639 002a 5163     		str	r1, [r2, #52]
+3526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12640              		.loc 1 3526 5 is_stmt 1 view .LVU4189
+3526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12641              		.loc 1 3526 10 is_stmt 0 view .LVU4190
+ 12642 002c C26F     		ldr	r2, [r0, #124]
+3526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12643              		.loc 1 3526 38 view .LVU4191
+ 12644 002e 0021     		movs	r1, #0
+ 12645 0030 9163     		str	r1, [r2, #56]
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12646              		.loc 1 3529 5 is_stmt 1 view .LVU4192
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12647              		.loc 1 3529 57 is_stmt 0 view .LVU4193
+ 12648 0032 0168     		ldr	r1, [r0]
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12649              		.loc 1 3529 9 view .LVU4194
+ 12650 0034 826D     		ldr	r2, [r0, #88]
+ 12651 0036 2431     		adds	r1, r1, #36
+ 12652 0038 C06F     		ldr	r0, [r0, #124]
+ 12653              	.LVL1108:
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12654              		.loc 1 3529 9 view .LVU4195
+ 12655 003a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 12656              	.LVL1109:
+3529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12657              		.loc 1 3529 8 view .LVU4196
+ 12658 003e 38BB     		cbnz	r0, .L670
+ 12659              	.L663:
+3542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12660              		.loc 1 3542 3 is_stmt 1 view .LVU4197
+3542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12661              		.loc 1 3542 3 view .LVU4198
+ 12662 0040 0023     		movs	r3, #0
+ 12663 0042 84F88030 		strb	r3, [r4, #128]
+3542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12664              		.loc 1 3542 3 view .LVU4199
+ARM GAS  /tmp/cceWHrnJ.s 			page 390
+
+
+3545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12665              		.loc 1 3545 3 view .LVU4200
+3545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12666              		.loc 1 3545 18 is_stmt 0 view .LVU4201
+ 12667 0046 2369     		ldr	r3, [r4, #16]
+3545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12668              		.loc 1 3545 6 view .LVU4202
+ 12669 0048 43B1     		cbz	r3, .L667
+ 12670              	.L666:
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12671              		.loc 1 3547 5 is_stmt 1 discriminator 1 view .LVU4203
+ 12672              	.LBB996:
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12673              		.loc 1 3547 5 discriminator 1 view .LVU4204
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12674              		.loc 1 3547 5 discriminator 1 view .LVU4205
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12675              		.loc 1 3547 5 discriminator 1 view .LVU4206
+ 12676 004a 2268     		ldr	r2, [r4]
+ 12677              	.LVL1110:
+ 12678              	.LBB997:
+ 12679              	.LBI997:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12680              		.loc 2 1151 31 discriminator 1 view .LVU4207
+ 12681              	.LBB998:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12682              		.loc 2 1153 5 discriminator 1 view .LVU4208
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12683              		.loc 2 1155 4 discriminator 1 view .LVU4209
+ 12684              		.syntax unified
+ 12685              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12686 004c 52E8003F 		ldrex r3, [r2]
+ 12687              	@ 0 "" 2
+ 12688              	.LVL1111:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12689              		.loc 2 1156 4 discriminator 1 view .LVU4210
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12690              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU4211
+ 12691              		.thumb
+ 12692              		.syntax unified
+ 12693              	.LBE998:
+ 12694              	.LBE997:
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12695              		.loc 1 3547 5 discriminator 1 view .LVU4212
+ 12696 0050 43F48073 		orr	r3, r3, #256
+ 12697              	.LVL1112:
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12698              		.loc 1 3547 5 is_stmt 1 discriminator 1 view .LVU4213
+ 12699              	.LBB999:
+ 12700              	.LBI999:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12701              		.loc 2 1202 31 discriminator 1 view .LVU4214
+ 12702              	.LBB1000:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12703              		.loc 2 1204 4 discriminator 1 view .LVU4215
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12704              		.loc 2 1206 4 discriminator 1 view .LVU4216
+ARM GAS  /tmp/cceWHrnJ.s 			page 391
+
+
+ 12705              		.syntax unified
+ 12706              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12707 0054 42E80031 		strex r1, r3, [r2]
+ 12708              	@ 0 "" 2
+ 12709              	.LVL1113:
+ 12710              		.loc 2 1207 4 discriminator 1 view .LVU4217
+ 12711              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU4218
+ 12712              		.thumb
+ 12713              		.syntax unified
+ 12714              	.LBE1000:
+ 12715              	.LBE999:
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12716              		.loc 1 3547 5 discriminator 1 view .LVU4219
+ 12717 0058 0029     		cmp	r1, #0
+ 12718 005a F6D1     		bne	.L666
+ 12719              	.LVL1114:
+ 12720              	.L667:
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12721              		.loc 1 3547 5 discriminator 1 view .LVU4220
+ 12722              	.LBE996:
+3547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12723              		.loc 1 3547 5 is_stmt 1 discriminator 1 view .LVU4221
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12724              		.loc 1 3551 3 discriminator 1 view .LVU4222
+ 12725              	.LBB1001:
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12726              		.loc 1 3551 3 discriminator 1 view .LVU4223
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12727              		.loc 1 3551 3 discriminator 1 view .LVU4224
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12728              		.loc 1 3551 3 discriminator 1 view .LVU4225
+ 12729 005c 2268     		ldr	r2, [r4]
+ 12730              	.LVL1115:
+ 12731              	.LBB1002:
+ 12732              	.LBI1002:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12733              		.loc 2 1151 31 discriminator 1 view .LVU4226
+ 12734              	.LBB1003:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12735              		.loc 2 1153 5 discriminator 1 view .LVU4227
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12736              		.loc 2 1155 4 discriminator 1 view .LVU4228
+ 12737 005e 02F10803 		add	r3, r2, #8
+ 12738              	.LVL1116:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12739              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU4229
+ 12740              		.syntax unified
+ 12741              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12742 0062 53E8003F 		ldrex r3, [r3]
+ 12743              	@ 0 "" 2
+ 12744              	.LVL1117:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12745              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU4230
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12746              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU4231
+ 12747              		.thumb
+ 12748              		.syntax unified
+ARM GAS  /tmp/cceWHrnJ.s 			page 392
+
+
+ 12749              	.LBE1003:
+ 12750              	.LBE1002:
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12751              		.loc 1 3551 3 discriminator 1 view .LVU4232
+ 12752 0066 43F00103 		orr	r3, r3, #1
+ 12753              	.LVL1118:
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12754              		.loc 1 3551 3 is_stmt 1 discriminator 1 view .LVU4233
+ 12755              	.LBB1004:
+ 12756              	.LBI1004:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12757              		.loc 2 1202 31 discriminator 1 view .LVU4234
+ 12758              	.LBB1005:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12759              		.loc 2 1204 4 discriminator 1 view .LVU4235
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12760              		.loc 2 1206 4 discriminator 1 view .LVU4236
+ 12761 006a 0832     		adds	r2, r2, #8
+ 12762              	.LVL1119:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12763              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU4237
+ 12764              		.syntax unified
+ 12765              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12766 006c 42E80031 		strex r1, r3, [r2]
+ 12767              	@ 0 "" 2
+ 12768              	.LVL1120:
+ 12769              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU4238
+ 12770              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU4239
+ 12771              		.thumb
+ 12772              		.syntax unified
+ 12773              	.LBE1005:
+ 12774              	.LBE1004:
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12775              		.loc 1 3551 3 discriminator 1 view .LVU4240
+ 12776 0070 0029     		cmp	r1, #0
+ 12777 0072 F3D1     		bne	.L667
+ 12778              	.LVL1121:
+ 12779              	.L668:
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12780              		.loc 1 3551 3 discriminator 1 view .LVU4241
+ 12781              	.LBE1001:
+3551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12782              		.loc 1 3551 3 is_stmt 1 discriminator 1 view .LVU4242
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12783              		.loc 1 3555 3 discriminator 1 view .LVU4243
+ 12784              	.LBB1006:
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12785              		.loc 1 3555 3 discriminator 1 view .LVU4244
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12786              		.loc 1 3555 3 discriminator 1 view .LVU4245
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12787              		.loc 1 3555 3 discriminator 1 view .LVU4246
+ 12788 0074 2268     		ldr	r2, [r4]
+ 12789              	.LVL1122:
+ 12790              	.LBB1007:
+ 12791              	.LBI1007:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/cceWHrnJ.s 			page 393
+
+
+ 12792              		.loc 2 1151 31 discriminator 1 view .LVU4247
+ 12793              	.LBB1008:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12794              		.loc 2 1153 5 discriminator 1 view .LVU4248
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12795              		.loc 2 1155 4 discriminator 1 view .LVU4249
+ 12796 0076 02F10803 		add	r3, r2, #8
+ 12797              	.LVL1123:
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12798              		.loc 2 1155 4 is_stmt 0 discriminator 1 view .LVU4250
+ 12799              		.syntax unified
+ 12800              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12801 007a 53E8003F 		ldrex r3, [r3]
+ 12802              	@ 0 "" 2
+ 12803              	.LVL1124:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12804              		.loc 2 1156 4 is_stmt 1 discriminator 1 view .LVU4251
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12805              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU4252
+ 12806              		.thumb
+ 12807              		.syntax unified
+ 12808              	.LBE1008:
+ 12809              	.LBE1007:
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12810              		.loc 1 3555 3 discriminator 1 view .LVU4253
+ 12811 007e 43F04003 		orr	r3, r3, #64
+ 12812              	.LVL1125:
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12813              		.loc 1 3555 3 is_stmt 1 discriminator 1 view .LVU4254
+ 12814              	.LBB1009:
+ 12815              	.LBI1009:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12816              		.loc 2 1202 31 discriminator 1 view .LVU4255
+ 12817              	.LBB1010:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12818              		.loc 2 1204 4 discriminator 1 view .LVU4256
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12819              		.loc 2 1206 4 discriminator 1 view .LVU4257
+ 12820 0082 0832     		adds	r2, r2, #8
+ 12821              	.LVL1126:
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12822              		.loc 2 1206 4 is_stmt 0 discriminator 1 view .LVU4258
+ 12823              		.syntax unified
+ 12824              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12825 0084 42E80031 		strex r1, r3, [r2]
+ 12826              	@ 0 "" 2
+ 12827              	.LVL1127:
+ 12828              		.loc 2 1207 4 is_stmt 1 discriminator 1 view .LVU4259
+ 12829              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU4260
+ 12830              		.thumb
+ 12831              		.syntax unified
+ 12832              	.LBE1010:
+ 12833              	.LBE1009:
+3555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12834              		.loc 1 3555 3 discriminator 1 view .LVU4261
+ 12835 0088 0029     		cmp	r1, #0
+ 12836 008a F3D1     		bne	.L668
+ARM GAS  /tmp/cceWHrnJ.s 			page 394
+
+
+ 12837              	.LBE1006:
+3557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** }
+ 12838              		.loc 1 3557 10 view .LVU4262
+ 12839 008c 0020     		movs	r0, #0
+ 12840              	.LVL1128:
+ 12841              	.L664:
+3558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12842              		.loc 1 3558 1 view .LVU4263
+ 12843 008e 10BD     		pop	{r4, pc}
+ 12844              	.LVL1129:
+ 12845              	.L670:
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12846              		.loc 1 3532 7 is_stmt 1 view .LVU4264
+3532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12847              		.loc 1 3532 24 is_stmt 0 view .LVU4265
+ 12848 0090 1023     		movs	r3, #16
+ 12849 0092 C4F88C30 		str	r3, [r4, #140]
+3534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12850              		.loc 1 3534 7 is_stmt 1 view .LVU4266
+3534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12851              		.loc 1 3534 7 view .LVU4267
+ 12852 0096 0023     		movs	r3, #0
+ 12853 0098 84F88030 		strb	r3, [r4, #128]
+3534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12854              		.loc 1 3534 7 view .LVU4268
+3537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12855              		.loc 1 3537 7 view .LVU4269
+3537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12856              		.loc 1 3537 22 is_stmt 0 view .LVU4270
+ 12857 009c 2023     		movs	r3, #32
+ 12858 009e C4F88830 		str	r3, [r4, #136]
+3539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12859              		.loc 1 3539 7 is_stmt 1 view .LVU4271
+3539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 12860              		.loc 1 3539 14 is_stmt 0 view .LVU4272
+ 12861 00a2 0120     		movs	r0, #1
+ 12862 00a4 F3E7     		b	.L664
+ 12863              	.L672:
+ 12864 00a6 00BF     		.align	2
+ 12865              	.L671:
+ 12866 00a8 00000000 		.word	UART_DMAReceiveCplt
+ 12867 00ac 00000000 		.word	UART_DMARxHalfCplt
+ 12868 00b0 00000000 		.word	UART_DMAError
+ 12869              		.cfi_endproc
+ 12870              	.LFE377:
+ 12872              		.section	.text.HAL_UART_Receive_DMA,"ax",%progbits
+ 12873              		.align	1
+ 12874              		.global	HAL_UART_Receive_DMA
+ 12875              		.syntax unified
+ 12876              		.thumb
+ 12877              		.thumb_func
+ 12879              	HAL_UART_Receive_DMA:
+ 12880              	.LVL1130:
+ 12881              	.LFB341:
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Rx process is not already ongoing */
+ 12882              		.loc 1 1490 1 is_stmt 1 view -0
+ 12883              		.cfi_startproc
+ARM GAS  /tmp/cceWHrnJ.s 			page 395
+
+
+ 12884              		@ args = 0, pretend = 0, frame = 0
+ 12885              		@ frame_needed = 0, uses_anonymous_args = 0
+1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   /* Check that a Rx process is not already ongoing */
+ 12886              		.loc 1 1490 1 is_stmt 0 view .LVU4274
+ 12887 0000 38B5     		push	{r3, r4, r5, lr}
+ 12888              	.LCFI61:
+ 12889              		.cfi_def_cfa_offset 16
+ 12890              		.cfi_offset 3, -16
+ 12891              		.cfi_offset 4, -12
+ 12892              		.cfi_offset 5, -8
+ 12893              		.cfi_offset 14, -4
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12894              		.loc 1 1492 3 is_stmt 1 view .LVU4275
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12895              		.loc 1 1492 12 is_stmt 0 view .LVU4276
+ 12896 0002 D0F88830 		ldr	r3, [r0, #136]
+1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   {
+ 12897              		.loc 1 1492 6 view .LVU4277
+ 12898 0006 202B     		cmp	r3, #32
+ 12899 0008 1ED1     		bne	.L677
+1494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12900              		.loc 1 1494 5 is_stmt 1 view .LVU4278
+1494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12901              		.loc 1 1494 8 is_stmt 0 view .LVU4279
+ 12902 000a F9B1     		cbz	r1, .L678
+1494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12903              		.loc 1 1494 25 discriminator 1 view .LVU4280
+ 12904 000c 02B3     		cbz	r2, .L679
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12905              		.loc 1 1499 5 is_stmt 1 view .LVU4281
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12906              		.loc 1 1499 5 view .LVU4282
+ 12907 000e 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 12908 0012 012B     		cmp	r3, #1
+ 12909 0014 1ED0     		beq	.L680
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12910              		.loc 1 1499 5 discriminator 2 view .LVU4283
+ 12911 0016 0123     		movs	r3, #1
+ 12912 0018 80F88030 		strb	r3, [r0, #128]
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12913              		.loc 1 1499 5 discriminator 2 view .LVU4284
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12914              		.loc 1 1502 5 discriminator 2 view .LVU4285
+1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12915              		.loc 1 1502 26 is_stmt 0 discriminator 2 view .LVU4286
+ 12916 001c 0023     		movs	r3, #0
+ 12917 001e C366     		str	r3, [r0, #108]
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12918              		.loc 1 1504 5 is_stmt 1 discriminator 2 view .LVU4287
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12919              		.loc 1 1504 11 is_stmt 0 discriminator 2 view .LVU4288
+ 12920 0020 0368     		ldr	r3, [r0]
+1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     {
+ 12921              		.loc 1 1504 8 discriminator 2 view .LVU4289
+ 12922 0022 0D4C     		ldr	r4, .L682
+ 12923 0024 A342     		cmp	r3, r4
+ 12924 0026 0CD0     		beq	.L675
+ARM GAS  /tmp/cceWHrnJ.s 			page 396
+
+
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 12925              		.loc 1 1507 7 is_stmt 1 view .LVU4290
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 12926              		.loc 1 1507 11 is_stmt 0 view .LVU4291
+ 12927 0028 5B68     		ldr	r3, [r3, #4]
+1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       {
+ 12928              		.loc 1 1507 10 view .LVU4292
+ 12929 002a 13F4000F 		tst	r3, #8388608
+ 12930 002e 08D0     		beq	.L675
+ 12931              	.L676:
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12932              		.loc 1 1510 9 is_stmt 1 discriminator 1 view .LVU4293
+ 12933              	.LBB1011:
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12934              		.loc 1 1510 9 discriminator 1 view .LVU4294
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12935              		.loc 1 1510 9 discriminator 1 view .LVU4295
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12936              		.loc 1 1510 9 discriminator 1 view .LVU4296
+ 12937 0030 0468     		ldr	r4, [r0]
+ 12938              	.LVL1131:
+ 12939              	.LBB1012:
+ 12940              	.LBI1012:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12941              		.loc 2 1151 31 discriminator 1 view .LVU4297
+ 12942              	.LBB1013:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12943              		.loc 2 1153 5 discriminator 1 view .LVU4298
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 12944              		.loc 2 1155 4 discriminator 1 view .LVU4299
+ 12945              		.syntax unified
+ 12946              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12947 0032 54E8003F 		ldrex r3, [r4]
+ 12948              	@ 0 "" 2
+ 12949              	.LVL1132:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12950              		.loc 2 1156 4 discriminator 1 view .LVU4300
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 12951              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU4301
+ 12952              		.thumb
+ 12953              		.syntax unified
+ 12954              	.LBE1013:
+ 12955              	.LBE1012:
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12956              		.loc 1 1510 9 discriminator 1 view .LVU4302
+ 12957 0036 43F08063 		orr	r3, r3, #67108864
+ 12958              	.LVL1133:
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12959              		.loc 1 1510 9 is_stmt 1 discriminator 1 view .LVU4303
+ 12960              	.LBB1014:
+ 12961              	.LBI1014:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 12962              		.loc 2 1202 31 discriminator 1 view .LVU4304
+ 12963              	.LBB1015:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 12964              		.loc 2 1204 4 discriminator 1 view .LVU4305
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ARM GAS  /tmp/cceWHrnJ.s 			page 397
+
+
+ 12965              		.loc 2 1206 4 discriminator 1 view .LVU4306
+ 12966              		.syntax unified
+ 12967              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 12968 003a 44E80035 		strex r5, r3, [r4]
+ 12969              	@ 0 "" 2
+ 12970              	.LVL1134:
+ 12971              		.loc 2 1207 4 discriminator 1 view .LVU4307
+ 12972              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU4308
+ 12973              		.thumb
+ 12974              		.syntax unified
+ 12975              	.LBE1015:
+ 12976              	.LBE1014:
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12977              		.loc 1 1510 9 discriminator 1 view .LVU4309
+ 12978 003e 002D     		cmp	r5, #0
+ 12979 0040 F6D1     		bne	.L676
+ 12980              	.LVL1135:
+ 12981              	.L675:
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12982              		.loc 1 1510 9 discriminator 1 view .LVU4310
+ 12983              	.LBE1011:
+1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****       }
+ 12984              		.loc 1 1510 9 is_stmt 1 discriminator 2 view .LVU4311
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12985              		.loc 1 1514 5 discriminator 2 view .LVU4312
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12986              		.loc 1 1514 13 is_stmt 0 discriminator 2 view .LVU4313
+ 12987 0042 FFF7FEFF 		bl	UART_Start_Receive_DMA
+ 12988              	.LVL1136:
+1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12989              		.loc 1 1514 13 discriminator 2 view .LVU4314
+ 12990 0046 00E0     		b	.L674
+ 12991              	.LVL1137:
+ 12992              	.L677:
+1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****   }
+ 12993              		.loc 1 1518 12 view .LVU4315
+ 12994 0048 0220     		movs	r0, #2
+ 12995              	.LVL1138:
+ 12996              	.L674:
+1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 12997              		.loc 1 1520 1 view .LVU4316
+ 12998 004a 38BD     		pop	{r3, r4, r5, pc}
+ 12999              	.LVL1139:
+ 13000              	.L678:
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 13001              		.loc 1 1496 14 view .LVU4317
+ 13002 004c 0120     		movs	r0, #1
+ 13003              	.LVL1140:
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 13004              		.loc 1 1496 14 view .LVU4318
+ 13005 004e FCE7     		b	.L674
+ 13006              	.LVL1141:
+ 13007              	.L679:
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 13008              		.loc 1 1496 14 view .LVU4319
+ 13009 0050 0120     		movs	r0, #1
+ 13010              	.LVL1142:
+ARM GAS  /tmp/cceWHrnJ.s 			page 398
+
+
+1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c ****     }
+ 13011              		.loc 1 1496 14 view .LVU4320
+ 13012 0052 FAE7     		b	.L674
+ 13013              	.LVL1143:
+ 13014              	.L680:
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 13015              		.loc 1 1499 5 view .LVU4321
+ 13016 0054 0220     		movs	r0, #2
+ 13017              	.LVL1144:
+1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c **** 
+ 13018              		.loc 1 1499 5 view .LVU4322
+ 13019 0056 F8E7     		b	.L674
+ 13020              	.L683:
+ 13021              		.align	2
+ 13022              	.L682:
+ 13023 0058 00800040 		.word	1073774592
+ 13024              		.cfi_endproc
+ 13025              	.LFE341:
+ 13027              		.global	UARTPrescTable
+ 13028              		.section	.rodata.UARTPrescTable,"a"
+ 13029              		.align	2
+ 13032              	UARTPrescTable:
+ 13033 0000 0100     		.short	1
+ 13034 0002 0200     		.short	2
+ 13035 0004 0400     		.short	4
+ 13036 0006 0600     		.short	6
+ 13037 0008 0800     		.short	8
+ 13038 000a 0A00     		.short	10
+ 13039 000c 0C00     		.short	12
+ 13040 000e 1000     		.short	16
+ 13041 0010 2000     		.short	32
+ 13042 0012 4000     		.short	64
+ 13043 0014 8000     		.short	128
+ 13044 0016 0001     		.short	256
+ 13045              		.text
+ 13046              	.Letext0:
+ 13047              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 13048              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 13049              		.file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 13050              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 13051              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 13052              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h"
+ 13053              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"
+ 13054              		.file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h"
+ 13055              		.file 11 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ARM GAS  /tmp/cceWHrnJ.s 			page 399
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_uart.c
+     /tmp/cceWHrnJ.s:21     .text.UART_EndTxTransfer:00000000 $t
+     /tmp/cceWHrnJ.s:26     .text.UART_EndTxTransfer:00000000 UART_EndTxTransfer
+     /tmp/cceWHrnJ.s:157    .text.UART_EndRxTransfer:00000000 $t
+     /tmp/cceWHrnJ.s:162    .text.UART_EndRxTransfer:00000000 UART_EndRxTransfer
+     /tmp/cceWHrnJ.s:358    .text.UART_TxISR_8BIT:00000000 $t
+     /tmp/cceWHrnJ.s:363    .text.UART_TxISR_8BIT:00000000 UART_TxISR_8BIT
+     /tmp/cceWHrnJ.s:523    .text.UART_TxISR_16BIT:00000000 $t
+     /tmp/cceWHrnJ.s:528    .text.UART_TxISR_16BIT:00000000 UART_TxISR_16BIT
+     /tmp/cceWHrnJ.s:695    .text.UART_TxISR_8BIT_FIFOEN:00000000 $t
+     /tmp/cceWHrnJ.s:700    .text.UART_TxISR_8BIT_FIFOEN:00000000 UART_TxISR_8BIT_FIFOEN
+     /tmp/cceWHrnJ.s:890    .text.UART_TxISR_16BIT_FIFOEN:00000000 $t
+     /tmp/cceWHrnJ.s:895    .text.UART_TxISR_16BIT_FIFOEN:00000000 UART_TxISR_16BIT_FIFOEN
+     /tmp/cceWHrnJ.s:1092   .text.HAL_UART_MspInit:00000000 $t
+     /tmp/cceWHrnJ.s:1098   .text.HAL_UART_MspInit:00000000 HAL_UART_MspInit
+     /tmp/cceWHrnJ.s:1113   .text.HAL_UART_MspDeInit:00000000 $t
+     /tmp/cceWHrnJ.s:1119   .text.HAL_UART_MspDeInit:00000000 HAL_UART_MspDeInit
+     /tmp/cceWHrnJ.s:1134   .text.HAL_UART_DeInit:00000000 $t
+     /tmp/cceWHrnJ.s:1140   .text.HAL_UART_DeInit:00000000 HAL_UART_DeInit
+     /tmp/cceWHrnJ.s:1226   .text.HAL_UART_Transmit_IT:00000000 $t
+     /tmp/cceWHrnJ.s:1232   .text.HAL_UART_Transmit_IT:00000000 HAL_UART_Transmit_IT
+     /tmp/cceWHrnJ.s:1497   .text.HAL_UART_Transmit_IT:000000bc $d
+     /tmp/cceWHrnJ.s:1505   .text.HAL_UART_Transmit_DMA:00000000 $t
+     /tmp/cceWHrnJ.s:1511   .text.HAL_UART_Transmit_DMA:00000000 HAL_UART_Transmit_DMA
+     /tmp/cceWHrnJ.s:1738   .text.HAL_UART_Transmit_DMA:000000b0 $d
+     /tmp/cceWHrnJ.s:3690   .text.UART_DMATransmitCplt:00000000 UART_DMATransmitCplt
+     /tmp/cceWHrnJ.s:3960   .text.UART_DMATxHalfCplt:00000000 UART_DMATxHalfCplt
+     /tmp/cceWHrnJ.s:4055   .text.UART_DMAError:00000000 UART_DMAError
+     /tmp/cceWHrnJ.s:1745   .text.HAL_UART_DMAPause:00000000 $t
+     /tmp/cceWHrnJ.s:1751   .text.HAL_UART_DMAPause:00000000 HAL_UART_DMAPause
+     /tmp/cceWHrnJ.s:2067   .text.HAL_UART_DMAResume:00000000 $t
+     /tmp/cceWHrnJ.s:2073   .text.HAL_UART_DMAResume:00000000 HAL_UART_DMAResume
+     /tmp/cceWHrnJ.s:2367   .text.HAL_UART_DMAStop:00000000 $t
+     /tmp/cceWHrnJ.s:2373   .text.HAL_UART_DMAStop:00000000 HAL_UART_DMAStop
+     /tmp/cceWHrnJ.s:2621   .text.HAL_UART_Abort:00000000 $t
+     /tmp/cceWHrnJ.s:2627   .text.HAL_UART_Abort:00000000 HAL_UART_Abort
+     /tmp/cceWHrnJ.s:3072   .text.HAL_UART_AbortTransmit:00000000 $t
+     /tmp/cceWHrnJ.s:3078   .text.HAL_UART_AbortTransmit:00000000 HAL_UART_AbortTransmit
+     /tmp/cceWHrnJ.s:3340   .text.HAL_UART_AbortReceive:00000000 $t
+     /tmp/cceWHrnJ.s:3346   .text.HAL_UART_AbortReceive:00000000 HAL_UART_AbortReceive
+     /tmp/cceWHrnJ.s:3664   .text.HAL_UART_TxCpltCallback:00000000 $t
+     /tmp/cceWHrnJ.s:3670   .text.HAL_UART_TxCpltCallback:00000000 HAL_UART_TxCpltCallback
+     /tmp/cceWHrnJ.s:3685   .text.UART_DMATransmitCplt:00000000 $t
+     /tmp/cceWHrnJ.s:3846   .text.UART_EndTransmit_IT:00000000 $t
+     /tmp/cceWHrnJ.s:3851   .text.UART_EndTransmit_IT:00000000 UART_EndTransmit_IT
+     /tmp/cceWHrnJ.s:3934   .text.HAL_UART_TxHalfCpltCallback:00000000 $t
+     /tmp/cceWHrnJ.s:3940   .text.HAL_UART_TxHalfCpltCallback:00000000 HAL_UART_TxHalfCpltCallback
+     /tmp/cceWHrnJ.s:3955   .text.UART_DMATxHalfCplt:00000000 $t
+     /tmp/cceWHrnJ.s:3987   .text.HAL_UART_RxCpltCallback:00000000 $t
+     /tmp/cceWHrnJ.s:3993   .text.HAL_UART_RxCpltCallback:00000000 HAL_UART_RxCpltCallback
+     /tmp/cceWHrnJ.s:4008   .text.HAL_UART_RxHalfCpltCallback:00000000 $t
+     /tmp/cceWHrnJ.s:4014   .text.HAL_UART_RxHalfCpltCallback:00000000 HAL_UART_RxHalfCpltCallback
+     /tmp/cceWHrnJ.s:4029   .text.HAL_UART_ErrorCallback:00000000 $t
+     /tmp/cceWHrnJ.s:4035   .text.HAL_UART_ErrorCallback:00000000 HAL_UART_ErrorCallback
+     /tmp/cceWHrnJ.s:4050   .text.UART_DMAError:00000000 $t
+     /tmp/cceWHrnJ.s:4145   .text.UART_DMAAbortOnError:00000000 $t
+ARM GAS  /tmp/cceWHrnJ.s 			page 400
+
+
+     /tmp/cceWHrnJ.s:4150   .text.UART_DMAAbortOnError:00000000 UART_DMAAbortOnError
+     /tmp/cceWHrnJ.s:4183   .text.HAL_UART_AbortCpltCallback:00000000 $t
+     /tmp/cceWHrnJ.s:4189   .text.HAL_UART_AbortCpltCallback:00000000 HAL_UART_AbortCpltCallback
+     /tmp/cceWHrnJ.s:4204   .text.HAL_UART_Abort_IT:00000000 $t
+     /tmp/cceWHrnJ.s:4210   .text.HAL_UART_Abort_IT:00000000 HAL_UART_Abort_IT
+     /tmp/cceWHrnJ.s:4701   .text.HAL_UART_Abort_IT:00000144 $d
+     /tmp/cceWHrnJ.s:4790   .text.UART_DMATxAbortCallback:00000000 UART_DMATxAbortCallback
+     /tmp/cceWHrnJ.s:4712   .text.UART_DMARxAbortCallback:00000000 UART_DMARxAbortCallback
+     /tmp/cceWHrnJ.s:4707   .text.UART_DMARxAbortCallback:00000000 $t
+     /tmp/cceWHrnJ.s:4785   .text.UART_DMATxAbortCallback:00000000 $t
+     /tmp/cceWHrnJ.s:4874   .text.HAL_UART_AbortTransmitCpltCallback:00000000 $t
+     /tmp/cceWHrnJ.s:4880   .text.HAL_UART_AbortTransmitCpltCallback:00000000 HAL_UART_AbortTransmitCpltCallback
+     /tmp/cceWHrnJ.s:4895   .text.HAL_UART_AbortTransmit_IT:00000000 $t
+     /tmp/cceWHrnJ.s:4901   .text.HAL_UART_AbortTransmit_IT:00000000 HAL_UART_AbortTransmit_IT
+     /tmp/cceWHrnJ.s:5180   .text.HAL_UART_AbortTransmit_IT:000000a8 $d
+     /tmp/cceWHrnJ.s:5190   .text.UART_DMATxOnlyAbortCallback:00000000 UART_DMATxOnlyAbortCallback
+     /tmp/cceWHrnJ.s:5185   .text.UART_DMATxOnlyAbortCallback:00000000 $t
+     /tmp/cceWHrnJ.s:5239   .text.HAL_UART_AbortReceiveCpltCallback:00000000 $t
+     /tmp/cceWHrnJ.s:5245   .text.HAL_UART_AbortReceiveCpltCallback:00000000 HAL_UART_AbortReceiveCpltCallback
+     /tmp/cceWHrnJ.s:5260   .text.HAL_UART_AbortReceive_IT:00000000 $t
+     /tmp/cceWHrnJ.s:5266   .text.HAL_UART_AbortReceive_IT:00000000 HAL_UART_AbortReceive_IT
+     /tmp/cceWHrnJ.s:5612   .text.HAL_UART_AbortReceive_IT:000000cc $d
+     /tmp/cceWHrnJ.s:5622   .text.UART_DMARxOnlyAbortCallback:00000000 UART_DMARxOnlyAbortCallback
+     /tmp/cceWHrnJ.s:5617   .text.UART_DMARxOnlyAbortCallback:00000000 $t
+     /tmp/cceWHrnJ.s:5668   .text.HAL_UARTEx_RxEventCallback:00000000 $t
+     /tmp/cceWHrnJ.s:5674   .text.HAL_UARTEx_RxEventCallback:00000000 HAL_UARTEx_RxEventCallback
+     /tmp/cceWHrnJ.s:5690   .text.HAL_UART_IRQHandler:00000000 $t
+     /tmp/cceWHrnJ.s:5696   .text.HAL_UART_IRQHandler:00000000 HAL_UART_IRQHandler
+     /tmp/cceWHrnJ.s:6598   .text.HAL_UART_IRQHandler:000002f4 $d
+     /tmp/cceWHrnJ.s:6606   .text.HAL_UART_IRQHandler:00000300 $t
+     /tmp/cceWHrnJ.s:6669   .text.UART_RxISR_8BIT:00000000 $t
+     /tmp/cceWHrnJ.s:6674   .text.UART_RxISR_8BIT:00000000 UART_RxISR_8BIT
+     /tmp/cceWHrnJ.s:6960   .text.UART_RxISR_16BIT:00000000 $t
+     /tmp/cceWHrnJ.s:6965   .text.UART_RxISR_16BIT:00000000 UART_RxISR_16BIT
+     /tmp/cceWHrnJ.s:7251   .text.UART_RxISR_8BIT_FIFOEN:00000000 $t
+     /tmp/cceWHrnJ.s:7256   .text.UART_RxISR_8BIT_FIFOEN:00000000 UART_RxISR_8BIT_FIFOEN
+     /tmp/cceWHrnJ.s:7787   .text.UART_RxISR_8BIT_FIFOEN:0000019c $d
+     /tmp/cceWHrnJ.s:7793   .text.UART_RxISR_16BIT_FIFOEN:00000000 $t
+     /tmp/cceWHrnJ.s:7798   .text.UART_RxISR_16BIT_FIFOEN:00000000 UART_RxISR_16BIT_FIFOEN
+     /tmp/cceWHrnJ.s:8332   .text.UART_RxISR_16BIT_FIFOEN:0000019c $d
+     /tmp/cceWHrnJ.s:8338   .text.UART_DMARxHalfCplt:00000000 $t
+     /tmp/cceWHrnJ.s:8343   .text.UART_DMARxHalfCplt:00000000 UART_DMARxHalfCplt
+     /tmp/cceWHrnJ.s:8387   .text.UART_DMAReceiveCplt:00000000 $t
+     /tmp/cceWHrnJ.s:8392   .text.UART_DMAReceiveCplt:00000000 UART_DMAReceiveCplt
+     /tmp/cceWHrnJ.s:8684   .text.HAL_UART_ReceiverTimeout_Config:00000000 $t
+     /tmp/cceWHrnJ.s:8690   .text.HAL_UART_ReceiverTimeout_Config:00000000 HAL_UART_ReceiverTimeout_Config
+     /tmp/cceWHrnJ.s:8719   .text.HAL_UART_ReceiverTimeout_Config:00000014 $d
+     /tmp/cceWHrnJ.s:8724   .text.HAL_UART_EnableReceiverTimeout:00000000 $t
+     /tmp/cceWHrnJ.s:8730   .text.HAL_UART_EnableReceiverTimeout:00000000 HAL_UART_EnableReceiverTimeout
+     /tmp/cceWHrnJ.s:8807   .text.HAL_UART_EnableReceiverTimeout:00000048 $d
+     /tmp/cceWHrnJ.s:8812   .text.HAL_UART_DisableReceiverTimeout:00000000 $t
+     /tmp/cceWHrnJ.s:8818   .text.HAL_UART_DisableReceiverTimeout:00000000 HAL_UART_DisableReceiverTimeout
+     /tmp/cceWHrnJ.s:8895   .text.HAL_UART_DisableReceiverTimeout:00000048 $d
+     /tmp/cceWHrnJ.s:8900   .text.HAL_MultiProcessor_EnterMuteMode:00000000 $t
+     /tmp/cceWHrnJ.s:8906   .text.HAL_MultiProcessor_EnterMuteMode:00000000 HAL_MultiProcessor_EnterMuteMode
+     /tmp/cceWHrnJ.s:8925   .text.HAL_HalfDuplex_EnableTransmitter:00000000 $t
+     /tmp/cceWHrnJ.s:8931   .text.HAL_HalfDuplex_EnableTransmitter:00000000 HAL_HalfDuplex_EnableTransmitter
+ARM GAS  /tmp/cceWHrnJ.s 			page 401
+
+
+     /tmp/cceWHrnJ.s:9084   .text.HAL_HalfDuplex_EnableReceiver:00000000 $t
+     /tmp/cceWHrnJ.s:9090   .text.HAL_HalfDuplex_EnableReceiver:00000000 HAL_HalfDuplex_EnableReceiver
+     /tmp/cceWHrnJ.s:9243   .text.HAL_LIN_SendBreak:00000000 $t
+     /tmp/cceWHrnJ.s:9249   .text.HAL_LIN_SendBreak:00000000 HAL_LIN_SendBreak
+     /tmp/cceWHrnJ.s:9302   .text.HAL_UART_GetState:00000000 $t
+     /tmp/cceWHrnJ.s:9308   .text.HAL_UART_GetState:00000000 HAL_UART_GetState
+     /tmp/cceWHrnJ.s:9336   .text.HAL_UART_GetError:00000000 $t
+     /tmp/cceWHrnJ.s:9342   .text.HAL_UART_GetError:00000000 HAL_UART_GetError
+     /tmp/cceWHrnJ.s:9361   .text.UART_SetConfig:00000000 $t
+     /tmp/cceWHrnJ.s:9367   .text.UART_SetConfig:00000000 UART_SetConfig
+     /tmp/cceWHrnJ.s:9512   .text.UART_SetConfig:00000094 $d
+     /tmp/cceWHrnJ.s:9522   .text.UART_SetConfig:000000a6 $t
+     /tmp/cceWHrnJ.s:9532   .text.UART_SetConfig:000000ba $d
+     /tmp/cceWHrnJ.s:9536   .text.UART_SetConfig:000000be $t
+     /tmp/cceWHrnJ.s:9569   .text.UART_SetConfig:000000e2 $d
+     /tmp/cceWHrnJ.s:9712   .text.UART_SetConfig:000001b4 $d
+     /tmp/cceWHrnJ.s:9813   .text.UART_SetConfig:00000236 $d
+     /tmp/cceWHrnJ.s:9829   .text.UART_SetConfig:00000244 $d
+     /tmp/cceWHrnJ.s:13032  .rodata.UARTPrescTable:00000000 UARTPrescTable
+     /tmp/cceWHrnJ.s:9841   .text.UART_SetConfig:00000268 $t
+     /tmp/cceWHrnJ.s:10055  .text.UART_SetConfig:0000033c $d
+     /tmp/cceWHrnJ.s:10061  .text.UART_AdvFeatureConfig:00000000 $t
+     /tmp/cceWHrnJ.s:10067  .text.UART_AdvFeatureConfig:00000000 UART_AdvFeatureConfig
+     /tmp/cceWHrnJ.s:10219  .text.UART_WaitOnFlagUntilTimeout:00000000 $t
+     /tmp/cceWHrnJ.s:10225  .text.UART_WaitOnFlagUntilTimeout:00000000 UART_WaitOnFlagUntilTimeout
+     /tmp/cceWHrnJ.s:10568  .text.HAL_UART_Transmit:00000000 $t
+     /tmp/cceWHrnJ.s:10574  .text.HAL_UART_Transmit:00000000 HAL_UART_Transmit
+     /tmp/cceWHrnJ.s:10805  .text.HAL_UART_Receive:00000000 $t
+     /tmp/cceWHrnJ.s:10811  .text.HAL_UART_Receive:00000000 HAL_UART_Receive
+     /tmp/cceWHrnJ.s:11094  .text.UART_CheckIdleState:00000000 $t
+     /tmp/cceWHrnJ.s:11100  .text.UART_CheckIdleState:00000000 UART_CheckIdleState
+     /tmp/cceWHrnJ.s:11216  .text.HAL_UART_Init:00000000 $t
+     /tmp/cceWHrnJ.s:11222  .text.HAL_UART_Init:00000000 HAL_UART_Init
+     /tmp/cceWHrnJ.s:11325  .text.HAL_HalfDuplex_Init:00000000 $t
+     /tmp/cceWHrnJ.s:11331  .text.HAL_HalfDuplex_Init:00000000 HAL_HalfDuplex_Init
+     /tmp/cceWHrnJ.s:11439  .text.HAL_LIN_Init:00000000 $t
+     /tmp/cceWHrnJ.s:11445  .text.HAL_LIN_Init:00000000 HAL_LIN_Init
+     /tmp/cceWHrnJ.s:11597  .text.HAL_MultiProcessor_Init:00000000 $t
+     /tmp/cceWHrnJ.s:11603  .text.HAL_MultiProcessor_Init:00000000 HAL_MultiProcessor_Init
+     /tmp/cceWHrnJ.s:11731  .text.HAL_MultiProcessor_EnableMuteMode:00000000 $t
+     /tmp/cceWHrnJ.s:11737  .text.HAL_MultiProcessor_EnableMuteMode:00000000 HAL_MultiProcessor_EnableMuteMode
+     /tmp/cceWHrnJ.s:11838  .text.HAL_MultiProcessor_DisableMuteMode:00000000 $t
+     /tmp/cceWHrnJ.s:11844  .text.HAL_MultiProcessor_DisableMuteMode:00000000 HAL_MultiProcessor_DisableMuteMode
+     /tmp/cceWHrnJ.s:11945  .text.UART_Start_Receive_IT:00000000 $t
+     /tmp/cceWHrnJ.s:11951  .text.UART_Start_Receive_IT:00000000 UART_Start_Receive_IT
+     /tmp/cceWHrnJ.s:12415  .text.UART_Start_Receive_IT:00000138 $d
+     /tmp/cceWHrnJ.s:12424  .text.HAL_UART_Receive_IT:00000000 $t
+     /tmp/cceWHrnJ.s:12430  .text.HAL_UART_Receive_IT:00000000 HAL_UART_Receive_IT
+     /tmp/cceWHrnJ.s:12574  .text.HAL_UART_Receive_IT:00000058 $d
+     /tmp/cceWHrnJ.s:12579  .text.UART_Start_Receive_DMA:00000000 $t
+     /tmp/cceWHrnJ.s:12585  .text.UART_Start_Receive_DMA:00000000 UART_Start_Receive_DMA
+     /tmp/cceWHrnJ.s:12866  .text.UART_Start_Receive_DMA:000000a8 $d
+     /tmp/cceWHrnJ.s:12873  .text.HAL_UART_Receive_DMA:00000000 $t
+     /tmp/cceWHrnJ.s:12879  .text.HAL_UART_Receive_DMA:00000000 HAL_UART_Receive_DMA
+     /tmp/cceWHrnJ.s:13023  .text.HAL_UART_Receive_DMA:00000058 $d
+     /tmp/cceWHrnJ.s:13029  .rodata.UARTPrescTable:00000000 $d
+     /tmp/cceWHrnJ.s:9582   .text.UART_SetConfig:000000ef $d
+ARM GAS  /tmp/cceWHrnJ.s 			page 402
+
+
+     /tmp/cceWHrnJ.s:9582   .text.UART_SetConfig:000000f0 $t
+     /tmp/cceWHrnJ.s:9721   .text.UART_SetConfig:000001bd $d
+     /tmp/cceWHrnJ.s:9721   .text.UART_SetConfig:000001be $t
+     /tmp/cceWHrnJ.s:9822   .text.UART_SetConfig:0000023f $d
+     /tmp/cceWHrnJ.s:9822   .text.UART_SetConfig:00000240 $t
+
+UNDEFINED SYMBOLS
+HAL_DMA_Start_IT
+HAL_DMA_Abort
+HAL_DMA_GetError
+HAL_DMA_Abort_IT
+HAL_UARTEx_WakeupCallback
+HAL_UARTEx_TxFifoEmptyCallback
+HAL_UARTEx_RxFifoFullCallback
+__aeabi_uldivmod
+HAL_RCC_GetPCLK1Freq
+HAL_RCC_GetSysClockFreq
+HAL_RCC_GetPCLK2Freq
+HAL_GetTick
diff --git a/squeow_sw/build/stm32g4xx_hal_uart.o b/squeow_sw/build/stm32g4xx_hal_uart.o
new file mode 100644
index 0000000000000000000000000000000000000000..ef7df5fb5ebd95dcf748c172b266f656722aceca
GIT binary patch
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diff --git a/squeow_sw/build/stm32g4xx_hal_uart_ex.d b/squeow_sw/build/stm32g4xx_hal_uart_ex.d
new file mode 100644
index 0000000..f706d9f
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_uart_ex.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_hal_uart_ex.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_hal_uart_ex.lst b/squeow_sw/build/stm32g4xx_hal_uart_ex.lst
new file mode 100644
index 0000000..8e3ca64
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_hal_uart_ex.lst
@@ -0,0 +1,4750 @@
+ARM GAS  /tmp/ccEfj1JP.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_hal_uart_ex.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c"
+  20              		.section	.text.UARTEx_Wakeup_AddressConfig,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	UARTEx_Wakeup_AddressConfig:
+  27              	.LVL0:
+  28              	.LFB344:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @file    stm32g4xx_hal_uart_ex.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief   Extended UART HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          This file provides firmware functions to manage the following extended
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *           + Peripheral Control functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   ******************************************************************************
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @attention
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * Copyright (c) 2019 STMicroelectronics.
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * All rights reserved.
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * in the root directory of this software component.
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   ******************************************************************************
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   @verbatim
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   ==============================================================================
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****                ##### UART peripheral extended features  #####
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   ==============================================================================
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     (#) Declare a UART_HandleTypeDef handle structure.
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+ARM GAS  /tmp/ccEfj1JP.s 			page 2
+
+
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         by calling the HAL_RS485Ex_Init() API.
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****             configured prior starting RX/TX transfers.
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   @endverbatim
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   ******************************************************************************
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Includes ------------------------------------------------------------------*/
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #include "stm32g4xx_hal.h"
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @addtogroup STM32G4xx_HAL_Driver
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @{
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx UARTEx
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief UART Extended HAL module driver
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @{
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #ifdef HAL_UART_MODULE_ENABLED
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private typedef -----------------------------------------------------------*/
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private define ------------------------------------------------------------*/
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEX_Private_Constants UARTEx Private Constants
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @{
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* UART RX FIFO depth */
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #define RX_FIFO_DEPTH 8U
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* UART TX FIFO depth */
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #define TX_FIFO_DEPTH 8U
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @}
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private macros ------------------------------------------------------------*/
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private variables ---------------------------------------------------------*/
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private function prototypes -----------------------------------------------*/
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @{
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelecti
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @}
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Exported functions --------------------------------------------------------*/
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @{
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ARM GAS  /tmp/ccEfj1JP.s 			page 3
+
+
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief    Extended Initialization and Configuration Functions
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @verbatim
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ===============================================================================
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****             ##### Initialization and Configuration functions #####
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****  ===============================================================================
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     [..]
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     in asynchronous mode.
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       (+) For the asynchronous mode the parameters below can be configured:
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) Baud Rate
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) Word Length
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) Stop Bit
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****              in the data register is transmitted but is changed by the parity bit.
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) Hardware flow control
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) Receiver/transmitter modes
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) Over Sampling Method
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) One-Bit Sampling Method
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       (+) For the asynchronous mode, the following advanced features can be configured as well:
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) TX and/or RX pin level inversion
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) data logical level inversion
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) RX and TX pins swap
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) RX overrun detection disabling
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) DMA disabling on RX error
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) MSB first on communication line
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (++) auto Baud rate detection
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     [..]
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****      procedures (details for the procedures are available in reference manual).
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @endverbatim
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   8-bit or 9-bit), the possible UART formats are listed in the
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   following table.
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     Table 1. UART frame format.
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     +-----------------------------------------------------------------------+
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |---------|---------|-----------|---------------------------------------|
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |---------|---------|-----------|---------------------------------------|
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |---------|---------|-----------|---------------------------------------|
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |---------|---------|-----------|---------------------------------------|
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |---------|---------|-----------|---------------------------------------|
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |---------|---------|-----------|---------------------------------------|
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     +-----------------------------------------------------------------------+
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @{
+ARM GAS  /tmp/ccEfj1JP.s 			page 4
+
+
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief Initialize the RS485 Driver enable feature according to the specified
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *         parameters in the UART_InitTypeDef and creates the associated handle.
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart            UART handle.
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param Polarity         Select the driver enable polarity.
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          This parameter can be one of the following values:
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param AssertionTime    Driver Enable assertion time:
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *       5-bit value defining the time between the activation of the DE (Driver Enable)
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *       signal and the beginning of the start bit. It is expressed in sample time
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *       units (1/8 or 1/16 bit time, depending on the oversampling rate)
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param DeassertionTime  Driver Enable deassertion time:
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *       5-bit value defining the time between the end of the last stop bit, in a
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *       transmitted message, and the de-activation of the DE (Driver Enable) signal.
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *       oversampling rate).
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval HAL status
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t Assertion
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****                                    uint32_t DeassertionTime)
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t temp;
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check the UART handle allocation */
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   if (huart == NULL)
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     return HAL_ERROR;
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check the Driver Enable UART instance */
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check the Driver Enable polarity */
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_DE_POLARITY(Polarity));
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check the Driver Enable assertion time */
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check the Driver Enable deassertion time */
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   if (huart->gState == HAL_UART_STATE_RESET)
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* Allocate lock resource and initialize it */
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->Lock = HAL_UNLOCKED;
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     UART_InitCallbacksToDefault(huart);
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     if (huart->MspInitCallback == NULL)
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       huart->MspInitCallback = HAL_UART_MspInit;
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* Init the low level hardware */
+ARM GAS  /tmp/ccEfj1JP.s 			page 5
+
+
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->MspInitCallback(huart);
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #else
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     HAL_UART_MspInit(huart);
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Disable the Peripheral */
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UART_DISABLE(huart);
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Set the UART Communication parameters */
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   if (UART_SetConfig(huart) == HAL_ERROR)
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     return HAL_ERROR;
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     UART_AdvFeatureConfig(huart);
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Set the Driver Enable polarity */
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Set the Driver Enable assertion and deassertion times */
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Enable the Peripheral */
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UART_ENABLE(huart);
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   return (UART_CheckIdleState(huart));
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @}
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *  @brief Extended functions
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @verbatim
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****  ===============================================================================
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****                       ##### IO operation functions #####
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****  ===============================================================================
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     This subsection provides a set of Wakeup and FIFO mode related callback functions.
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     (#) Wakeup from Stop mode Callback:
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (+) HAL_UARTEx_WakeupCallback()
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 6
+
+
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     (#) TX/RX Fifos Callbacks:
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (+) HAL_UARTEx_RxFifoFullCallback()
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (+) HAL_UARTEx_TxFifoEmptyCallback()
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @endverbatim
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @{
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief UART wakeup from Stop mode callback.
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart UART handle.
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval None
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   UNUSED(huart);
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****             the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****    */
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief  UART RX Fifo full callback.
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param  huart UART handle.
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval None
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   UNUSED(huart);
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****             the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****    */
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief  UART TX Fifo empty callback.
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param  huart UART handle.
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval None
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   UNUSED(huart);
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****             the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****    */
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @}
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 7
+
+
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief    Extended Peripheral Control functions
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @verbatim
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****  ===============================================================================
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****                       ##### Peripheral Control functions #####
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****  ===============================================================================
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     [..] This section provides the following functions:
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****      (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****          detection length to more than 4 bits for multiprocessor address mark wake up.
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****      (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****          trigger: address match, Start Bit detection or RXNE bit status.
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****      (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****      (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****      (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****      (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****      (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****      (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     [..] This subsection also provides a set of additional functions providing enhanced reception
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     services to user. (For example, these functions allow application to handle use cases
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     where number of data to be received is unknown).
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     (#) Compared to standard reception services which only consider number of received
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         data elements as reception completion criteria, these functions also consider additional ev
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         as triggers for updating reception status to caller :
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****        (+) Detection of inactivity period (RX line has not been active for a given period).
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally 
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****                for 1 frame time, after last received byte.
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           (++) RX inactivity detected by RTO, i.e. line has been in idle state
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****                for a programmable time, after last received byte.
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****        (+) Detection that a specific character has been received.
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     (#) There are two mode of transfer:
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****        (+) Blocking mode: The reception is performed in polling mode, until either expected number 
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            or till IDLE event occurs. Reception is handled only during function execution.
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            When function exits, no data reception could occur. HAL status and number of actually re
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            are returned by function after finishing transfer.
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****        (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            These API's return the HAL status.
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            The end of the data processing will be indicated through the
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            The HAL_UART_ErrorCallback()user callback will be executed when a reception error is det
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     (#) Blocking mode API:
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (+) HAL_UARTEx_ReceiveToIdle()
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     (#) Non-Blocking mode API with Interrupt:
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (+) HAL_UARTEx_ReceiveToIdle_IT()
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     (#) Non-Blocking mode API with DMA:
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         (+) HAL_UARTEx_ReceiveToIdle_DMA()
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @endverbatim
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @{
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ARM GAS  /tmp/ccEfj1JP.s 			page 8
+
+
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief By default in multiprocessor mode, when the wake up method is set
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        to address mark, the UART handles only 4-bit long addresses detection;
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        long).
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart         UART handle.
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param AddressLength This parameter can be one of the following values:
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval HAL status
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t Addres
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check the UART handle allocation */
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   if (huart == NULL)
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     return HAL_ERROR;
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check the address length parameter */
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Disable the Peripheral */
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UART_DISABLE(huart);
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Set the address length */
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Enable the Peripheral */
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UART_ENABLE(huart);
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* TEACK and/or REACK to check before moving huart->gState to Ready */
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   return (UART_CheckIdleState(huart));
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief Set Wakeup from Stop mode interrupt flag selection.
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @note It is the application responsibility to enable the interrupt used as
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *       usart_wkup interrupt source before entering low-power mode.
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart           UART handle.
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          This parameter can be one of the following values:
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          @arg @ref UART_WAKEUP_ON_ADDRESS
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          @arg @ref UART_WAKEUP_ON_STARTBIT
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval HAL status
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeD
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tickstart;
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 9
+
+
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* check the wake-up from stop mode UART instance */
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* check the wake-up selection parameter */
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Locked */
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_LOCK(huart);
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Disable the Peripheral */
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UART_DISABLE(huart);
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Set the wake-up selection scheme */
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Enable the Peripheral */
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UART_ENABLE(huart);
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Init tickstart for timeout management */
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   tickstart = HAL_GetTick();
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Wait until REACK flag is set */
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE)
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     status = HAL_TIMEOUT;
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   else
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* Initialize the UART State */
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->gState = HAL_UART_STATE_READY;
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Unlocked */
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UNLOCK(huart);
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   return status;
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief Enable UART Stop Mode.
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart UART handle.
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval HAL status
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Locked */
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_LOCK(huart);
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Set UESM bit */
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+ARM GAS  /tmp/ccEfj1JP.s 			page 10
+
+
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Unlocked */
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UNLOCK(huart);
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   return HAL_OK;
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief Disable UART Stop Mode.
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart UART handle.
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval HAL status
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Locked */
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_LOCK(huart);
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Clear UESM bit */
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Unlocked */
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UNLOCK(huart);
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   return HAL_OK;
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief  Enable the FIFO mode.
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart      UART handle.
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval HAL status
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tmpcr1;
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check parameters */
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Locked */
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_LOCK(huart);
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Save actual UART configuration */
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   tmpcr1 = READ_REG(huart->Instance->CR1);
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Disable UART */
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UART_DISABLE(huart);
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Enable FIFO mode */
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->FifoMode = UART_FIFOMODE_ENABLE;
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Restore UART configuration */
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Determine the number of data to process during RX/TX ISR execution */
+ARM GAS  /tmp/ccEfj1JP.s 			page 11
+
+
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   UARTEx_SetNbDataToProcess(huart);
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->gState = HAL_UART_STATE_READY;
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Unlocked */
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UNLOCK(huart);
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   return HAL_OK;
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief  Disable the FIFO mode.
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart      UART handle.
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval HAL status
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tmpcr1;
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check parameters */
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Locked */
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_LOCK(huart);
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Save actual UART configuration */
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   tmpcr1 = READ_REG(huart->Instance->CR1);
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Disable UART */
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UART_DISABLE(huart);
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Enable FIFO mode */
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->FifoMode = UART_FIFOMODE_DISABLE;
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Restore UART configuration */
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->gState = HAL_UART_STATE_READY;
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Unlocked */
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UNLOCK(huart);
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   return HAL_OK;
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief  Set the TXFIFO threshold.
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart      UART handle.
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param Threshold  TX FIFO threshold value
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          This parameter can be one of the following values:
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *            @arg @ref UART_TXFIFO_THRESHOLD_1_8
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *            @arg @ref UART_TXFIFO_THRESHOLD_1_4
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *            @arg @ref UART_TXFIFO_THRESHOLD_1_2
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *            @arg @ref UART_TXFIFO_THRESHOLD_3_4
+ARM GAS  /tmp/ccEfj1JP.s 			page 12
+
+
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval HAL status
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tmpcr1;
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check parameters */
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Locked */
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_LOCK(huart);
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Save actual UART configuration */
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   tmpcr1 = READ_REG(huart->Instance->CR1);
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Disable UART */
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UART_DISABLE(huart);
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Update TX threshold configuration */
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Determine the number of data to process during RX/TX ISR execution */
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   UARTEx_SetNbDataToProcess(huart);
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Restore UART configuration */
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->gState = HAL_UART_STATE_READY;
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Unlocked */
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UNLOCK(huart);
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   return HAL_OK;
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief  Set the RXFIFO threshold.
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart      UART handle.
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param Threshold  RX FIFO threshold value
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *          This parameter can be one of the following values:
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *            @arg @ref UART_RXFIFO_THRESHOLD_1_8
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *            @arg @ref UART_RXFIFO_THRESHOLD_1_4
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *            @arg @ref UART_RXFIFO_THRESHOLD_1_2
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *            @arg @ref UART_RXFIFO_THRESHOLD_3_4
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval HAL status
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tmpcr1;
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 13
+
+
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check the parameters */
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Locked */
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_LOCK(huart);
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->gState = HAL_UART_STATE_BUSY;
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Save actual UART configuration */
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   tmpcr1 = READ_REG(huart->Instance->CR1);
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Disable UART */
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UART_DISABLE(huart);
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Update RX threshold configuration */
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Determine the number of data to process during RX/TX ISR execution */
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   UARTEx_SetNbDataToProcess(huart);
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Restore UART configuration */
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->gState = HAL_UART_STATE_READY;
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Unlocked */
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   __HAL_UNLOCK(huart);
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   return HAL_OK;
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief Receive an amount of data in blocking mode till either the expected number of data
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        is received or an IDLE event occurs.
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @note  HAL_OK is returned if reception is completed (expected number of data has been received)
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        or if reception is stopped after IDLE event (less than the expected number of data has b
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        In this case, RxLen output parameter indicates number of data available in reception buf
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        the received data is handled as a set of uint16_t. In this case, Size must indicate the 
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        of uint16_t available through pData.
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *       is not empty. Read operations from the RDR register are performed when
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *       RXFNE flag is set. From hardware perspective, RXFNE flag and
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *       RXNE are mapped on the same bit-field.
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart   UART handle.
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param RxLen   Number of data elements finally received
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *                (could be lower than Size, in case reception ends on IDLE event)
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval HAL status
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****                                            uint32_t Timeout)
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint8_t  *pdata8bits;
+ARM GAS  /tmp/ccEfj1JP.s 			page 14
+
+
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint16_t *pdata16bits;
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint16_t uhMask;
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tickstart;
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check that a Rx process is not already ongoing */
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   if (huart->RxState == HAL_UART_STATE_READY)
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     if ((pData == NULL) || (Size == 0U))
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       return  HAL_ERROR;
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     __HAL_LOCK(huart);
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* Init tickstart for timeout management */
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     tickstart = HAL_GetTick();
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->RxXferSize  = Size;
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->RxXferCount = Size;
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* Computation of UART mask to apply to RDR register */
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     UART_MASK_COMPUTATION(huart);
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       pdata8bits  = NULL;
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       pdata16bits = (uint16_t *) pData;
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     else
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       pdata8bits  = pData;
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       pdata16bits = NULL;
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     __HAL_UNLOCK(huart);
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* Initialize output number of received elements */
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     *RxLen = 0U;
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* as long as data have to be received */
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     while (huart->RxXferCount > 0U)
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       /* Check if IDLE flag is set */
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         /* Clear IDLE flag in ISR */
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         /* If Set, but no data ever received, clear flag without exiting loop */
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         /* If Set, and data has already been received, this means Idle Event is valid : End recepti
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         if (*RxLen > 0U)
+ARM GAS  /tmp/ccEfj1JP.s 			page 15
+
+
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           huart->RxState = HAL_UART_STATE_READY;
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           return HAL_OK;
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         }
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       /* Check if RXNE flag is set */
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         if (pdata8bits == NULL)
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           pdata16bits++;
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         }
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         else
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           pdata8bits++;
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         }
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         /* Increment number of received elements */
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         *RxLen += 1U;
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         huart->RxXferCount--;
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       /* Check for the Timeout */
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       if (Timeout != HAL_MAX_DELAY)
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           huart->RxState = HAL_UART_STATE_READY;
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           return HAL_TIMEOUT;
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         }
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* Set number of received elements in output parameter : RxLen */
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     *RxLen = huart->RxXferSize - huart->RxXferCount;
+ 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* At end of Rx process, restore huart->RxState to Ready */
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->RxState = HAL_UART_STATE_READY;
+ 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     return HAL_OK;
+ 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   else
+ 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     return HAL_BUSY;
+ 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief Receive an amount of data in interrupt mode till either the expected number of data
+ 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        is received or an IDLE event occurs.
+ 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @note  Reception is initiated by this function call. Further progress of reception is achieved 
+ 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        to UART interrupts raised by RXNE and IDLE events. Callback is called at end of receptio
+ 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        number of received data elements.
+ 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M
+ARM GAS  /tmp/ccEfj1JP.s 			page 16
+
+
+ 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        the received data is handled as a set of uint16_t. In this case, Size must indicate the 
+ 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        of uint16_t available through pData.
+ 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart UART handle.
+ 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+ 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval HAL status
+ 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t S
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   HAL_StatusTypeDef status;
+ 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check that a Rx process is not already ongoing */
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   if (huart->RxState == HAL_UART_STATE_READY)
+ 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     if ((pData == NULL) || (Size == 0U))
+ 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       return HAL_ERROR;
+ 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     __HAL_LOCK(huart);
+ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* Set Reception type to reception till IDLE Event*/
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     status =  UART_Start_Receive_IT(huart, pData, Size);
+ 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* Check Rx process has been successfully started */
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     if (status == HAL_OK)
+ 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       else
+ 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         /* In case of errors already pending when reception is started,
+ 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            Interrupts may have already been raised and lead to reception abortion.
+ 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            (Overrun error for instance).
+ 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         status = HAL_ERROR;
+ 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     return status;
+ 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   else
+ 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     return HAL_BUSY;
+ 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief Receive an amount of data in DMA mode till either the expected number
+ 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        of data is received or an IDLE event occurs.
+ 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @note  Reception is initiated by this function call. Further progress of reception is achieved 
+ 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        to DMA services, transferring automatically received data elements in user reception buf
+ARM GAS  /tmp/ccEfj1JP.s 			page 17
+
+
+ 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        calling registered callbacks at half/end of reception. UART IDLE events are also used to
+ 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        reception phase as ended. In all cases, callback execution will indicate number of recei
+ 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @note  When the UART parity is enabled (PCE = 1), the received data contain
+ 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        the parity bit (MSB position).
+ 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M
+ 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        the received data is handled as a set of uint16_t. In this case, Size must indicate the 
+ 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *        of uint16_t available through pData.
+ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart UART handle.
+ 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+ 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval HAL status
+ 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t 
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   HAL_StatusTypeDef status;
+ 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check that a Rx process is not already ongoing */
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   if (huart->RxState == HAL_UART_STATE_READY)
+ 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     if ((pData == NULL) || (Size == 0U))
+ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       return HAL_ERROR;
+ 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     __HAL_LOCK(huart);
+ 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* Set Reception type to reception till IDLE Event*/
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     status =  UART_Start_Receive_DMA(huart, pData, Size);
+ 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* Check Rx process has been successfully started */
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     if (status == HAL_OK)
+ 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       else
+ 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         /* In case of errors already pending when reception is started,
+ 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            Interrupts may have already been raised and lead to reception abortion.
+ 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            (Overrun error for instance).
+ 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****            In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         status = HAL_ERROR;
+ 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     return status;
+ 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   else
+ 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     return HAL_BUSY;
+ 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 18
+
+
+ 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @}
+ 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @}
+ 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @addtogroup UARTEx_Private_Functions
+ 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @{
+ 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detectio
+ 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart           UART handle.
+ 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param WakeUpSelection UART wake up from stop mode parameters.
+ 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval None
+ 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelecti
+ 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+  29              		.loc 1 962 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 8
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+  34              		.loc 1 962 1 is_stmt 0 view .LVU1
+  35 0000 82B0     		sub	sp, sp, #8
+  36              	.LCFI0:
+  37              		.cfi_def_cfa_offset 8
+  38 0002 02AB     		add	r3, sp, #8
+  39 0004 03E90600 		stmdb	r3, {r1, r2}
+ 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+  40              		.loc 1 963 3 is_stmt 1 view .LVU2
+ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Set the USART address length */
+ 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+  41              		.loc 1 966 3 view .LVU3
+  42 0008 0268     		ldr	r2, [r0]
+  43 000a 5368     		ldr	r3, [r2, #4]
+  44 000c 23F01003 		bic	r3, r3, #16
+  45 0010 BDF80410 		ldrh	r1, [sp, #4]
+  46 0014 0B43     		orrs	r3, r3, r1
+  47 0016 5360     		str	r3, [r2, #4]
+ 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Set the USART address node */
+ 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_AD
+  48              		.loc 1 969 3 view .LVU4
+  49 0018 0268     		ldr	r2, [r0]
+  50 001a 5368     		ldr	r3, [r2, #4]
+  51 001c 23F07F43 		bic	r3, r3, #-16777216
+  52 0020 9DF80610 		ldrb	r1, [sp, #6]	@ zero_extendqisi2
+  53 0024 43EA0163 		orr	r3, r3, r1, lsl #24
+  54 0028 5360     		str	r3, [r2, #4]
+ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+  55              		.loc 1 970 1 is_stmt 0 view .LVU5
+  56 002a 02B0     		add	sp, sp, #8
+  57              	.LCFI1:
+ARM GAS  /tmp/ccEfj1JP.s 			page 19
+
+
+  58              		.cfi_def_cfa_offset 0
+  59              		@ sp needed
+  60 002c 7047     		bx	lr
+  61              		.cfi_endproc
+  62              	.LFE344:
+  64              		.section	.text.UARTEx_SetNbDataToProcess,"ax",%progbits
+  65              		.align	1
+  66              		.syntax unified
+  67              		.thumb
+  68              		.thumb_func
+  70              	UARTEx_SetNbDataToProcess:
+  71              	.LVL1:
+  72              	.LFB345:
+ 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
+ 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @brief Calculate the number of data to process in RX/TX ISR.
+ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @note The RX FIFO depth and the TX FIFO depth is extracted from
+ 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   *       the UART configuration registers.
+ 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @param huart UART handle.
+ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   * @retval None
+ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   */
+ 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
+  73              		.loc 1 980 1 is_stmt 1 view -0
+  74              		.cfi_startproc
+  75              		@ args = 0, pretend = 0, frame = 0
+  76              		@ frame_needed = 0, uses_anonymous_args = 0
+  77              		@ link register save eliminated.
+ 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint8_t rx_fifo_depth;
+  78              		.loc 1 981 3 view .LVU7
+ 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint8_t tx_fifo_depth;
+  79              		.loc 1 982 3 view .LVU8
+ 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint8_t rx_fifo_threshold;
+  80              		.loc 1 983 3 view .LVU9
+ 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint8_t tx_fifo_threshold;
+  81              		.loc 1 984 3 view .LVU10
+ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  82              		.loc 1 985 3 view .LVU11
+ 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+  83              		.loc 1 986 3 view .LVU12
+ 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+  84              		.loc 1 988 3 view .LVU13
+  85              		.loc 1 988 12 is_stmt 0 view .LVU14
+  86 0000 436E     		ldr	r3, [r0, #100]
+  87              		.loc 1 988 6 view .LVU15
+  88 0002 2BB9     		cbnz	r3, .L4
+ 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->NbTxDataToProcess = 1U;
+  89              		.loc 1 990 5 is_stmt 1 view .LVU16
+  90              		.loc 1 990 30 is_stmt 0 view .LVU17
+  91 0004 0123     		movs	r3, #1
+  92 0006 A0F86A30 		strh	r3, [r0, #106]	@ movhi
+ 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->NbRxDataToProcess = 1U;
+  93              		.loc 1 991 5 is_stmt 1 view .LVU18
+  94              		.loc 1 991 30 is_stmt 0 view .LVU19
+  95 000a A0F86830 		strh	r3, [r0, #104]	@ movhi
+ARM GAS  /tmp/ccEfj1JP.s 			page 20
+
+
+  96 000e 7047     		bx	lr
+  97              	.L4:
+ 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint8_t rx_fifo_depth;
+  98              		.loc 1 980 1 view .LVU20
+  99 0010 30B4     		push	{r4, r5}
+ 100              	.LCFI2:
+ 101              		.cfi_def_cfa_offset 8
+ 102              		.cfi_offset 4, -8
+ 103              		.cfi_offset 5, -4
+ 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   else
+ 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     rx_fifo_depth = RX_FIFO_DEPTH;
+ 104              		.loc 1 995 5 is_stmt 1 view .LVU21
+ 105              	.LVL2:
+ 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     tx_fifo_depth = TX_FIFO_DEPTH;
+ 106              		.loc 1 996 5 view .LVU22
+ 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RX
+ 107              		.loc 1 997 5 view .LVU23
+ 108              		.loc 1 997 35 is_stmt 0 view .LVU24
+ 109 0012 0368     		ldr	r3, [r0]
+ 110 0014 9A68     		ldr	r2, [r3, #8]
+ 111              		.loc 1 997 23 view .LVU25
+ 112 0016 C2F34262 		ubfx	r2, r2, #25, #3
+ 113              	.LVL3:
+ 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TX
+ 114              		.loc 1 998 5 is_stmt 1 view .LVU26
+ 115              		.loc 1 998 35 is_stmt 0 view .LVU27
+ 116 001a 9968     		ldr	r1, [r3, #8]
+ 117              		.loc 1 998 23 view .LVU28
+ 118 001c 490F     		lsrs	r1, r1, #29
+ 119              	.LVL4:
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ 120              		.loc 1 999 5 is_stmt 1 view .LVU29
+ 121              		.loc 1 999 68 is_stmt 0 view .LVU30
+ 122 001e 094D     		ldr	r5, .L9
+ 123 0020 6B5C     		ldrb	r3, [r5, r1]	@ zero_extendqisi2
+ 124              		.loc 1 999 57 view .LVU31
+ 125 0022 DB00     		lsls	r3, r3, #3
+1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****                                (uint16_t)denominator[tx_fifo_threshold];
+ 126              		.loc 1 1000 53 view .LVU32
+ 127 0024 084C     		ldr	r4, .L9+4
+ 128 0026 615C     		ldrb	r1, [r4, r1]	@ zero_extendqisi2
+ 129              	.LVL5:
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ 130              		.loc 1 999 89 view .LVU33
+ 131 0028 93FBF1F3 		sdiv	r3, r3, r1
+ 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ 132              		.loc 1 999 30 view .LVU34
+ 133 002c A0F86A30 		strh	r3, [r0, #106]	@ movhi
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ 134              		.loc 1 1001 5 is_stmt 1 view .LVU35
+ 135              		.loc 1 1001 68 is_stmt 0 view .LVU36
+ 136 0030 AB5C     		ldrb	r3, [r5, r2]	@ zero_extendqisi2
+ 137              		.loc 1 1001 57 view .LVU37
+ 138 0032 DB00     		lsls	r3, r3, #3
+1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****                                (uint16_t)denominator[rx_fifo_threshold];
+ARM GAS  /tmp/ccEfj1JP.s 			page 21
+
+
+ 139              		.loc 1 1002 53 view .LVU38
+ 140 0034 A25C     		ldrb	r2, [r4, r2]	@ zero_extendqisi2
+ 141              	.LVL6:
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ 142              		.loc 1 1001 89 view .LVU39
+ 143 0036 93FBF2F3 		sdiv	r3, r3, r2
+1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ 144              		.loc 1 1001 30 view .LVU40
+ 145 003a A0F86830 		strh	r3, [r0, #104]	@ movhi
+1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 146              		.loc 1 1004 1 view .LVU41
+ 147 003e 30BC     		pop	{r4, r5}
+ 148              	.LCFI3:
+ 149              		.cfi_restore 5
+ 150              		.cfi_restore 4
+ 151              		.cfi_def_cfa_offset 0
+ 152 0040 7047     		bx	lr
+ 153              	.L10:
+ 154 0042 00BF     		.align	2
+ 155              	.L9:
+ 156 0044 00000000 		.word	numerator.1
+ 157 0048 00000000 		.word	denominator.0
+ 158              		.cfi_endproc
+ 159              	.LFE345:
+ 161              		.section	.text.HAL_RS485Ex_Init,"ax",%progbits
+ 162              		.align	1
+ 163              		.global	HAL_RS485Ex_Init
+ 164              		.syntax unified
+ 165              		.thumb
+ 166              		.thumb_func
+ 168              	HAL_RS485Ex_Init:
+ 169              	.LVL7:
+ 170              	.LFB329:
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t temp;
+ 171              		.loc 1 168 1 is_stmt 1 view -0
+ 172              		.cfi_startproc
+ 173              		@ args = 0, pretend = 0, frame = 0
+ 174              		@ frame_needed = 0, uses_anonymous_args = 0
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 175              		.loc 1 169 3 view .LVU43
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 176              		.loc 1 172 3 view .LVU44
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 177              		.loc 1 172 6 is_stmt 0 view .LVU45
+ 178 0000 0028     		cmp	r0, #0
+ 179 0002 3ED0     		beq	.L15
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t temp;
+ 180              		.loc 1 168 1 view .LVU46
+ 181 0004 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 182              	.LCFI4:
+ 183              		.cfi_def_cfa_offset 24
+ 184              		.cfi_offset 3, -24
+ 185              		.cfi_offset 4, -20
+ 186              		.cfi_offset 5, -16
+ 187              		.cfi_offset 6, -12
+ 188              		.cfi_offset 7, -8
+ARM GAS  /tmp/ccEfj1JP.s 			page 22
+
+
+ 189              		.cfi_offset 14, -4
+ 190 0006 0F46     		mov	r7, r1
+ 191 0008 1646     		mov	r6, r2
+ 192 000a 1D46     		mov	r5, r3
+ 193 000c 0446     		mov	r4, r0
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 194              		.loc 1 177 3 is_stmt 1 view .LVU47
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 195              		.loc 1 180 3 view .LVU48
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 196              		.loc 1 183 3 view .LVU49
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 197              		.loc 1 186 3 view .LVU50
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 198              		.loc 1 188 3 view .LVU51
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 199              		.loc 1 188 12 is_stmt 0 view .LVU52
+ 200 000e D0F88430 		ldr	r3, [r0, #132]
+ 201              	.LVL8:
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 202              		.loc 1 188 6 view .LVU53
+ 203 0012 6BB3     		cbz	r3, .L20
+ 204              	.LVL9:
+ 205              	.L13:
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 206              		.loc 1 209 3 is_stmt 1 view .LVU54
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 207              		.loc 1 209 17 is_stmt 0 view .LVU55
+ 208 0014 2423     		movs	r3, #36
+ 209 0016 C4F88430 		str	r3, [r4, #132]
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 210              		.loc 1 212 3 is_stmt 1 view .LVU56
+ 211 001a 2268     		ldr	r2, [r4]
+ 212 001c 1368     		ldr	r3, [r2]
+ 213 001e 23F00103 		bic	r3, r3, #1
+ 214 0022 1360     		str	r3, [r2]
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 215              		.loc 1 215 3 view .LVU57
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 216              		.loc 1 215 7 is_stmt 0 view .LVU58
+ 217 0024 2046     		mov	r0, r4
+ 218 0026 FFF7FEFF 		bl	UART_SetConfig
+ 219              	.LVL10:
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 220              		.loc 1 215 6 view .LVU59
+ 221 002a 0128     		cmp	r0, #1
+ 222 002c 1FD0     		beq	.L12
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 223              		.loc 1 220 3 is_stmt 1 view .LVU60
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 224              		.loc 1 220 26 is_stmt 0 view .LVU61
+ 225 002e A36A     		ldr	r3, [r4, #40]
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 226              		.loc 1 220 6 view .LVU62
+ 227 0030 1BBB     		cbnz	r3, .L21
+ 228              	.L14:
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 23
+
+
+ 229              		.loc 1 226 3 is_stmt 1 view .LVU63
+ 230 0032 2268     		ldr	r2, [r4]
+ 231 0034 9368     		ldr	r3, [r2, #8]
+ 232 0036 43F48043 		orr	r3, r3, #16384
+ 233 003a 9360     		str	r3, [r2, #8]
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 234              		.loc 1 229 3 view .LVU64
+ 235 003c 2268     		ldr	r2, [r4]
+ 236 003e 9368     		ldr	r3, [r2, #8]
+ 237 0040 23F40043 		bic	r3, r3, #32768
+ 238 0044 3B43     		orrs	r3, r3, r7
+ 239 0046 9360     		str	r3, [r2, #8]
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ 240              		.loc 1 232 3 view .LVU65
+ 241              	.LVL11:
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+ 242              		.loc 1 233 3 view .LVU66
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+ 243              		.loc 1 233 28 is_stmt 0 view .LVU67
+ 244 0048 2D04     		lsls	r5, r5, #16
+ 245              	.LVL12:
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+ 246              		.loc 1 233 8 view .LVU68
+ 247 004a 45EA4652 		orr	r2, r5, r6, lsl #21
+ 248              	.LVL13:
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 249              		.loc 1 234 3 is_stmt 1 view .LVU69
+ 250 004e 2168     		ldr	r1, [r4]
+ 251 0050 0B68     		ldr	r3, [r1]
+ 252 0052 23F07F73 		bic	r3, r3, #66846720
+ 253 0056 23F44033 		bic	r3, r3, #196608
+ 254 005a 1343     		orrs	r3, r3, r2
+ 255 005c 0B60     		str	r3, [r1]
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 256              		.loc 1 237 3 view .LVU70
+ 257 005e 2268     		ldr	r2, [r4]
+ 258              	.LVL14:
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 259              		.loc 1 237 3 is_stmt 0 view .LVU71
+ 260 0060 1368     		ldr	r3, [r2]
+ 261 0062 43F00103 		orr	r3, r3, #1
+ 262 0066 1360     		str	r3, [r2]
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 263              		.loc 1 240 3 is_stmt 1 view .LVU72
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 264              		.loc 1 240 11 is_stmt 0 view .LVU73
+ 265 0068 2046     		mov	r0, r4
+ 266 006a FFF7FEFF 		bl	UART_CheckIdleState
+ 267              	.LVL15:
+ 268              	.L12:
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 269              		.loc 1 241 1 view .LVU74
+ 270 006e F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 271              	.LVL16:
+ 272              	.L20:
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 273              		.loc 1 191 5 is_stmt 1 view .LVU75
+ARM GAS  /tmp/ccEfj1JP.s 			page 24
+
+
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 274              		.loc 1 191 17 is_stmt 0 view .LVU76
+ 275 0070 80F88030 		strb	r3, [r0, #128]
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 276              		.loc 1 205 5 is_stmt 1 view .LVU77
+ 277 0074 FFF7FEFF 		bl	HAL_UART_MspInit
+ 278              	.LVL17:
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ 279              		.loc 1 205 5 is_stmt 0 view .LVU78
+ 280 0078 CCE7     		b	.L13
+ 281              	.L21:
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 282              		.loc 1 222 5 is_stmt 1 view .LVU79
+ 283 007a 2046     		mov	r0, r4
+ 284 007c FFF7FEFF 		bl	UART_AdvFeatureConfig
+ 285              	.LVL18:
+ 286 0080 D7E7     		b	.L14
+ 287              	.LVL19:
+ 288              	.L15:
+ 289              	.LCFI5:
+ 290              		.cfi_def_cfa_offset 0
+ 291              		.cfi_restore 3
+ 292              		.cfi_restore 4
+ 293              		.cfi_restore 5
+ 294              		.cfi_restore 6
+ 295              		.cfi_restore 7
+ 296              		.cfi_restore 14
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 297              		.loc 1 174 12 is_stmt 0 view .LVU80
+ 298 0082 0120     		movs	r0, #1
+ 299              	.LVL20:
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 300              		.loc 1 241 1 view .LVU81
+ 301 0084 7047     		bx	lr
+ 302              		.cfi_endproc
+ 303              	.LFE329:
+ 305              		.section	.text.HAL_UARTEx_WakeupCallback,"ax",%progbits
+ 306              		.align	1
+ 307              		.weak	HAL_UARTEx_WakeupCallback
+ 308              		.syntax unified
+ 309              		.thumb
+ 310              		.thumb_func
+ 312              	HAL_UARTEx_WakeupCallback:
+ 313              	.LVL21:
+ 314              	.LFB330:
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 315              		.loc 1 273 1 is_stmt 1 view -0
+ 316              		.cfi_startproc
+ 317              		@ args = 0, pretend = 0, frame = 0
+ 318              		@ frame_needed = 0, uses_anonymous_args = 0
+ 319              		@ link register save eliminated.
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 320              		.loc 1 275 3 view .LVU83
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 321              		.loc 1 280 1 is_stmt 0 view .LVU84
+ 322 0000 7047     		bx	lr
+ 323              		.cfi_endproc
+ARM GAS  /tmp/ccEfj1JP.s 			page 25
+
+
+ 324              	.LFE330:
+ 326              		.section	.text.HAL_UARTEx_RxFifoFullCallback,"ax",%progbits
+ 327              		.align	1
+ 328              		.weak	HAL_UARTEx_RxFifoFullCallback
+ 329              		.syntax unified
+ 330              		.thumb
+ 331              		.thumb_func
+ 333              	HAL_UARTEx_RxFifoFullCallback:
+ 334              	.LVL22:
+ 335              	.LFB331:
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 336              		.loc 1 288 1 is_stmt 1 view -0
+ 337              		.cfi_startproc
+ 338              		@ args = 0, pretend = 0, frame = 0
+ 339              		@ frame_needed = 0, uses_anonymous_args = 0
+ 340              		@ link register save eliminated.
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 341              		.loc 1 290 3 view .LVU86
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 342              		.loc 1 295 1 is_stmt 0 view .LVU87
+ 343 0000 7047     		bx	lr
+ 344              		.cfi_endproc
+ 345              	.LFE331:
+ 347              		.section	.text.HAL_UARTEx_TxFifoEmptyCallback,"ax",%progbits
+ 348              		.align	1
+ 349              		.weak	HAL_UARTEx_TxFifoEmptyCallback
+ 350              		.syntax unified
+ 351              		.thumb
+ 352              		.thumb_func
+ 354              	HAL_UARTEx_TxFifoEmptyCallback:
+ 355              	.LVL23:
+ 356              	.LFB332:
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 357              		.loc 1 303 1 is_stmt 1 view -0
+ 358              		.cfi_startproc
+ 359              		@ args = 0, pretend = 0, frame = 0
+ 360              		@ frame_needed = 0, uses_anonymous_args = 0
+ 361              		@ link register save eliminated.
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 362              		.loc 1 305 3 view .LVU89
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 363              		.loc 1 310 1 is_stmt 0 view .LVU90
+ 364 0000 7047     		bx	lr
+ 365              		.cfi_endproc
+ 366              	.LFE332:
+ 368              		.section	.text.HAL_MultiProcessorEx_AddressLength_Set,"ax",%progbits
+ 369              		.align	1
+ 370              		.global	HAL_MultiProcessorEx_AddressLength_Set
+ 371              		.syntax unified
+ 372              		.thumb
+ 373              		.thumb_func
+ 375              	HAL_MultiProcessorEx_AddressLength_Set:
+ 376              	.LVL24:
+ 377              	.LFB333:
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check the UART handle allocation */
+ 378              		.loc 1 388 1 is_stmt 1 view -0
+ 379              		.cfi_startproc
+ARM GAS  /tmp/ccEfj1JP.s 			page 26
+
+
+ 380              		@ args = 0, pretend = 0, frame = 0
+ 381              		@ frame_needed = 0, uses_anonymous_args = 0
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 382              		.loc 1 390 3 view .LVU92
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 383              		.loc 1 390 6 is_stmt 0 view .LVU93
+ 384 0000 C0B1     		cbz	r0, .L27
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Check the UART handle allocation */
+ 385              		.loc 1 388 1 view .LVU94
+ 386 0002 08B5     		push	{r3, lr}
+ 387              	.LCFI6:
+ 388              		.cfi_def_cfa_offset 8
+ 389              		.cfi_offset 3, -8
+ 390              		.cfi_offset 14, -4
+ 391 0004 0346     		mov	r3, r0
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 392              		.loc 1 396 3 is_stmt 1 view .LVU95
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 393              		.loc 1 398 3 view .LVU96
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 394              		.loc 1 398 17 is_stmt 0 view .LVU97
+ 395 0006 2422     		movs	r2, #36
+ 396 0008 C0F88420 		str	r2, [r0, #132]
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 397              		.loc 1 401 3 is_stmt 1 view .LVU98
+ 398 000c 0068     		ldr	r0, [r0]
+ 399              	.LVL25:
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 400              		.loc 1 401 3 is_stmt 0 view .LVU99
+ 401 000e 0268     		ldr	r2, [r0]
+ 402 0010 22F00102 		bic	r2, r2, #1
+ 403 0014 0260     		str	r2, [r0]
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 404              		.loc 1 404 3 is_stmt 1 view .LVU100
+ 405 0016 1868     		ldr	r0, [r3]
+ 406 0018 4268     		ldr	r2, [r0, #4]
+ 407 001a 22F01002 		bic	r2, r2, #16
+ 408 001e 1143     		orrs	r1, r1, r2
+ 409              	.LVL26:
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 410              		.loc 1 404 3 is_stmt 0 view .LVU101
+ 411 0020 4160     		str	r1, [r0, #4]
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 412              		.loc 1 407 3 is_stmt 1 view .LVU102
+ 413 0022 1968     		ldr	r1, [r3]
+ 414 0024 0A68     		ldr	r2, [r1]
+ 415 0026 42F00102 		orr	r2, r2, #1
+ 416 002a 0A60     		str	r2, [r1]
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 417              		.loc 1 410 3 view .LVU103
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 418              		.loc 1 410 11 is_stmt 0 view .LVU104
+ 419 002c 1846     		mov	r0, r3
+ 420 002e FFF7FEFF 		bl	UART_CheckIdleState
+ 421              	.LVL27:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 422              		.loc 1 411 1 view .LVU105
+ARM GAS  /tmp/ccEfj1JP.s 			page 27
+
+
+ 423 0032 08BD     		pop	{r3, pc}
+ 424              	.LVL28:
+ 425              	.L27:
+ 426              	.LCFI7:
+ 427              		.cfi_def_cfa_offset 0
+ 428              		.cfi_restore 3
+ 429              		.cfi_restore 14
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 430              		.loc 1 392 12 view .LVU106
+ 431 0034 0120     		movs	r0, #1
+ 432              	.LVL29:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 433              		.loc 1 411 1 view .LVU107
+ 434 0036 7047     		bx	lr
+ 435              		.cfi_endproc
+ 436              	.LFE333:
+ 438              		.section	.text.HAL_UARTEx_StopModeWakeUpSourceConfig,"ax",%progbits
+ 439              		.align	1
+ 440              		.global	HAL_UARTEx_StopModeWakeUpSourceConfig
+ 441              		.syntax unified
+ 442              		.thumb
+ 443              		.thumb_func
+ 445              	HAL_UARTEx_StopModeWakeUpSourceConfig:
+ 446              	.LVL30:
+ 447              	.LFB334:
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 448              		.loc 1 426 1 is_stmt 1 view -0
+ 449              		.cfi_startproc
+ 450              		@ args = 0, pretend = 0, frame = 8
+ 451              		@ frame_needed = 0, uses_anonymous_args = 0
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 452              		.loc 1 426 1 is_stmt 0 view .LVU109
+ 453 0000 10B5     		push	{r4, lr}
+ 454              	.LCFI8:
+ 455              		.cfi_def_cfa_offset 8
+ 456              		.cfi_offset 4, -8
+ 457              		.cfi_offset 14, -4
+ 458 0002 84B0     		sub	sp, sp, #16
+ 459              	.LCFI9:
+ 460              		.cfi_def_cfa_offset 24
+ 461 0004 04AB     		add	r3, sp, #16
+ 462 0006 03E90600 		stmdb	r3, {r1, r2}
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tickstart;
+ 463              		.loc 1 427 3 is_stmt 1 view .LVU110
+ 464              	.LVL31:
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 465              		.loc 1 428 3 view .LVU111
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* check the wake-up selection parameter */
+ 466              		.loc 1 431 3 view .LVU112
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 467              		.loc 1 433 3 view .LVU113
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 468              		.loc 1 436 3 view .LVU114
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 469              		.loc 1 436 3 view .LVU115
+ 470 000a 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 471 000e 012B     		cmp	r3, #1
+ARM GAS  /tmp/ccEfj1JP.s 			page 28
+
+
+ 472 0010 35D0     		beq	.L36
+ 473 0012 0446     		mov	r4, r0
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 474              		.loc 1 436 3 discriminator 2 view .LVU116
+ 475 0014 0123     		movs	r3, #1
+ 476 0016 80F88030 		strb	r3, [r0, #128]
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 477              		.loc 1 436 3 discriminator 2 view .LVU117
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 478              		.loc 1 438 3 discriminator 2 view .LVU118
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 479              		.loc 1 438 17 is_stmt 0 discriminator 2 view .LVU119
+ 480 001a 2423     		movs	r3, #36
+ 481 001c C0F88430 		str	r3, [r0, #132]
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 482              		.loc 1 441 3 is_stmt 1 discriminator 2 view .LVU120
+ 483 0020 0268     		ldr	r2, [r0]
+ 484 0022 1368     		ldr	r3, [r2]
+ 485 0024 23F00103 		bic	r3, r3, #1
+ 486 0028 1360     		str	r3, [r2]
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 487              		.loc 1 444 3 discriminator 2 view .LVU121
+ 488 002a 0168     		ldr	r1, [r0]
+ 489 002c 8B68     		ldr	r3, [r1, #8]
+ 490 002e 23F44013 		bic	r3, r3, #3145728
+ 491 0032 029A     		ldr	r2, [sp, #8]
+ 492 0034 1343     		orrs	r3, r3, r2
+ 493 0036 8B60     		str	r3, [r1, #8]
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 494              		.loc 1 446 3 discriminator 2 view .LVU122
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 495              		.loc 1 446 6 is_stmt 0 discriminator 2 view .LVU123
+ 496 0038 AAB1     		cbz	r2, .L39
+ 497              	.LVL32:
+ 498              	.L34:
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 499              		.loc 1 452 3 is_stmt 1 view .LVU124
+ 500 003a 2268     		ldr	r2, [r4]
+ 501 003c 1368     		ldr	r3, [r2]
+ 502 003e 43F00103 		orr	r3, r3, #1
+ 503 0042 1360     		str	r3, [r2]
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 504              		.loc 1 455 3 view .LVU125
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 505              		.loc 1 455 15 is_stmt 0 view .LVU126
+ 506 0044 FFF7FEFF 		bl	HAL_GetTick
+ 507              	.LVL33:
+ 508 0048 0346     		mov	r3, r0
+ 509              	.LVL34:
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 510              		.loc 1 458 3 is_stmt 1 view .LVU127
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 511              		.loc 1 458 7 is_stmt 0 view .LVU128
+ 512 004a 6FF07E42 		mvn	r2, #-33554432
+ 513 004e 0092     		str	r2, [sp]
+ 514 0050 0022     		movs	r2, #0
+ 515 0052 4FF48001 		mov	r1, #4194304
+ARM GAS  /tmp/ccEfj1JP.s 			page 29
+
+
+ 516 0056 2046     		mov	r0, r4
+ 517              	.LVL35:
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 518              		.loc 1 458 7 view .LVU129
+ 519 0058 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 520              	.LVL36:
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 521              		.loc 1 458 6 view .LVU130
+ 522 005c 48B9     		cbnz	r0, .L37
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 523              		.loc 1 465 5 is_stmt 1 view .LVU131
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 524              		.loc 1 465 19 is_stmt 0 view .LVU132
+ 525 005e 2023     		movs	r3, #32
+ 526 0060 C4F88430 		str	r3, [r4, #132]
+ 527 0064 06E0     		b	.L35
+ 528              	.LVL37:
+ 529              	.L39:
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 530              		.loc 1 448 5 is_stmt 1 view .LVU133
+ 531 0066 04AB     		add	r3, sp, #16
+ 532 0068 13E90600 		ldmdb	r3, {r1, r2}
+ 533 006c FFF7FEFF 		bl	UARTEx_Wakeup_AddressConfig
+ 534              	.LVL38:
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 535              		.loc 1 448 5 is_stmt 0 view .LVU134
+ 536 0070 E3E7     		b	.L34
+ 537              	.LVL39:
+ 538              	.L37:
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 539              		.loc 1 460 12 view .LVU135
+ 540 0072 0320     		movs	r0, #3
+ 541              	.L35:
+ 542              	.LVL40:
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 543              		.loc 1 469 3 is_stmt 1 view .LVU136
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 544              		.loc 1 469 3 view .LVU137
+ 545 0074 0023     		movs	r3, #0
+ 546 0076 84F88030 		strb	r3, [r4, #128]
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 547              		.loc 1 469 3 view .LVU138
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 548              		.loc 1 471 3 view .LVU139
+ 549              	.LVL41:
+ 550              	.L33:
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 551              		.loc 1 472 1 is_stmt 0 view .LVU140
+ 552 007a 04B0     		add	sp, sp, #16
+ 553              	.LCFI10:
+ 554              		.cfi_remember_state
+ 555              		.cfi_def_cfa_offset 8
+ 556              		@ sp needed
+ 557 007c 10BD     		pop	{r4, pc}
+ 558              	.LVL42:
+ 559              	.L36:
+ 560              	.LCFI11:
+ARM GAS  /tmp/ccEfj1JP.s 			page 30
+
+
+ 561              		.cfi_restore_state
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 562              		.loc 1 436 3 view .LVU141
+ 563 007e 0220     		movs	r0, #2
+ 564              	.LVL43:
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 565              		.loc 1 436 3 view .LVU142
+ 566 0080 FBE7     		b	.L33
+ 567              		.cfi_endproc
+ 568              	.LFE334:
+ 570              		.section	.text.HAL_UARTEx_EnableStopMode,"ax",%progbits
+ 571              		.align	1
+ 572              		.global	HAL_UARTEx_EnableStopMode
+ 573              		.syntax unified
+ 574              		.thumb
+ 575              		.thumb_func
+ 577              	HAL_UARTEx_EnableStopMode:
+ 578              	.LVL44:
+ 579              	.LFB335:
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Locked */
+ 580              		.loc 1 481 1 is_stmt 1 view -0
+ 581              		.cfi_startproc
+ 582              		@ args = 0, pretend = 0, frame = 0
+ 583              		@ frame_needed = 0, uses_anonymous_args = 0
+ 584              		@ link register save eliminated.
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 585              		.loc 1 483 3 view .LVU144
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 586              		.loc 1 483 3 view .LVU145
+ 587 0000 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 588 0004 012B     		cmp	r3, #1
+ 589 0006 10D0     		beq	.L43
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 590              		.loc 1 483 3 discriminator 2 view .LVU146
+ 591 0008 0123     		movs	r3, #1
+ 592 000a 80F88030 		strb	r3, [r0, #128]
+ 593              	.L42:
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 594              		.loc 1 483 3 discriminator 1 view .LVU147
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 595              		.loc 1 486 3 discriminator 1 view .LVU148
+ 596              	.LBB22:
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 597              		.loc 1 486 3 discriminator 1 view .LVU149
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 598              		.loc 1 486 3 discriminator 1 view .LVU150
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 599              		.loc 1 486 3 discriminator 1 view .LVU151
+ 600 000e 0268     		ldr	r2, [r0]
+ 601              	.LVL45:
+ 602              	.LBB23:
+ 603              	.LBI23:
+ 604              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.2.0
+ARM GAS  /tmp/ccEfj1JP.s 			page 31
+
+
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     08. May 2019
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+ARM GAS  /tmp/ccEfj1JP.s 			page 32
+
+
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccEfj1JP.s 			page 33
+
+
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****  
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccEfj1JP.s 			page 34
+
+
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ARM GAS  /tmp/ccEfj1JP.s 			page 35
+
+
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 36
+
+
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ARM GAS  /tmp/ccEfj1JP.s 			page 37
+
+
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 38
+
+
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ARM GAS  /tmp/ccEfj1JP.s 			page 39
+
+
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ARM GAS  /tmp/ccEfj1JP.s 			page 40
+
+
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccEfj1JP.s 			page 41
+
+
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/ccEfj1JP.s 			page 42
+
+
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ARM GAS  /tmp/ccEfj1JP.s 			page 43
+
+
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ARM GAS  /tmp/ccEfj1JP.s 			page 44
+
+
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 45
+
+
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ARM GAS  /tmp/ccEfj1JP.s 			page 46
+
+
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 882:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 883:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 885:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 888:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 900:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 901:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 902:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 904:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 906:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 908:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 913:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 915:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 916:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ARM GAS  /tmp/ccEfj1JP.s 			page 47
+
+
+ 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 918:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 922:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 923:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 925:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 928:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 930:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 931:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 932:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 938:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 940:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 942:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 943:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+ 945:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 946:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 947:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 948:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 949:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 950:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ 952:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 953:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 954:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
+ 956:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 958:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 959:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 960:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 961:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 962:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
+ 963:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
+ 964:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 965:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 966:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 967:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+ 968:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 969:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ 970:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_bswap32(value);
+ 971:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 972:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 48
+
+
+ 974:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 975:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 976:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 977:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 978:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 979:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 980:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 982:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 984:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 985:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 986:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+ 987:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 989:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 990:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 991:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 992:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 993:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 994:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 995:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 996:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 997:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
+ 998:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 999:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+1000:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1001:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+1002:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1003:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1004:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
+1005:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1006:Drivers/CMSIS/Include/cmsis_gcc.h ****   int16_t result;
+1007:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1008:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+1009:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+1010:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1011:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1014:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1015:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
+1016:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
+1017:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
+1018:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
+1019:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Rotated value
+1020:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1021:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+1022:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1023:Drivers/CMSIS/Include/cmsis_gcc.h ****   op2 %= 32U;
+1024:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (op2 == 0U)
+1025:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1026:Drivers/CMSIS/Include/cmsis_gcc.h ****     return op1;
+1027:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1028:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
+1029:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1030:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 49
+
+
+1031:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1032:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1033:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Breakpoint
+1034:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
+1035:Drivers/CMSIS/Include/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
+1036:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
+1037:Drivers/CMSIS/Include/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
+1038:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1039:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+1040:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1041:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1042:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1043:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse bit order of value
+1044:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
+1045:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+1046:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+1047:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1048:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+1049:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1050:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+1051:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+1053:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+1054:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+1055:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+1056:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1057:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+1058:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1059:Drivers/CMSIS/Include/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
+1060:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
+1061:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1062:Drivers/CMSIS/Include/cmsis_gcc.h ****     result <<= 1U;
+1063:Drivers/CMSIS/Include/cmsis_gcc.h ****     result |= value & 1U;
+1064:Drivers/CMSIS/Include/cmsis_gcc.h ****     s--;
+1065:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1066:Drivers/CMSIS/Include/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
+1067:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1068:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+1069:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1072:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1073:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Count leading zeros
+1074:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
+1075:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
+1076:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             number of leading zeros in value
+1077:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1078:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+1079:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1080:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+1081:Drivers/CMSIS/Include/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
+1082:Drivers/CMSIS/Include/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
+1083:Drivers/CMSIS/Include/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
+1084:Drivers/CMSIS/Include/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
+1085:Drivers/CMSIS/Include/cmsis_gcc.h ****      is non-zero".
+1086:Drivers/CMSIS/Include/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+1087:Drivers/CMSIS/Include/cmsis_gcc.h ****      single CLZ instruction.
+ARM GAS  /tmp/ccEfj1JP.s 			page 50
+
+
+1088:Drivers/CMSIS/Include/cmsis_gcc.h ****    */
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (value == 0U)
+1090:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+1091:Drivers/CMSIS/Include/cmsis_gcc.h ****     return 32U;
+1092:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+1093:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_clz(value);
+1094:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1095:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1096:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1097:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+1098:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+1099:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+1100:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+1101:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1102:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (8 bit)
+1103:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 8 bit value.
+1104:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
+1105:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
+1106:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1107:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+1108:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1109:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
+1110:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1111:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1112:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+1113:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1114:Drivers/CMSIS/Include/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+1115:Drivers/CMSIS/Include/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
+1116:Drivers/CMSIS/Include/cmsis_gcc.h ****     */
+1117:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+1118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1119:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
+1120:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1122:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1123:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1124:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (16 bit)
+1125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 16 bit values.
+1126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
+1127:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
+1128:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+1130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1131:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
+1132:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1133:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1134:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+1135:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1136:Drivers/CMSIS/Include/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+1137:Drivers/CMSIS/Include/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
+1138:Drivers/CMSIS/Include/cmsis_gcc.h ****     */
+1139:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+1140:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1141:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
+1142:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1143:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1144:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 51
+
+
+1145:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1146:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (32 bit)
+1147:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 32 bit values.
+1148:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
+1149:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
+1150:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+ 605              		.loc 2 1151 31 discriminator 1 view .LVU152
+ 606              	.LBB24:
+1152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1153:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
+ 607              		.loc 2 1153 5 discriminator 1 view .LVU153
+1154:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 608              		.loc 2 1155 4 discriminator 1 view .LVU154
+ 609              		.syntax unified
+ 610              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 611 0010 52E8003F 		ldrex r3, [r2]
+ 612              	@ 0 "" 2
+ 613              	.LVL46:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 614              		.loc 2 1156 4 discriminator 1 view .LVU155
+ 615              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU156
+ 616              		.thumb
+ 617              		.syntax unified
+ 618              	.LBE24:
+ 619              	.LBE23:
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 620              		.loc 1 486 3 discriminator 1 view .LVU157
+ 621 0014 43F00203 		orr	r3, r3, #2
+ 622              	.LVL47:
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 623              		.loc 1 486 3 is_stmt 1 discriminator 1 view .LVU158
+ 624              	.LBB25:
+ 625              	.LBI25:
+1157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1158:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1159:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1160:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1161:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (8 bit)
+1162:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 8 bit values.
+1163:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
+1164:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
+1165:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
+1166:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
+1167:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1168:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+1169:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1170:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
+1171:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1172:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+1173:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+1174:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1175:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1177:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1178:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (16 bit)
+ARM GAS  /tmp/ccEfj1JP.s 			page 52
+
+
+1179:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 16 bit values.
+1180:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
+1181:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
+1182:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
+1183:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
+1184:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1185:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+1186:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1187:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
+1188:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1189:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+1190:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+1191:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1192:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1193:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1194:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1195:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (32 bit)
+1196:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 32 bit values.
+1197:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
+1198:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
+1199:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
+1200:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
+1201:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+ 626              		.loc 2 1202 31 discriminator 1 view .LVU159
+ 627              	.LBB26:
+1203:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1204:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
+ 628              		.loc 2 1204 4 discriminator 1 view .LVU160
+1205:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 629              		.loc 2 1206 4 discriminator 1 view .LVU161
+ 630              		.syntax unified
+ 631              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 632 0018 42E80031 		strex r1, r3, [r2]
+ 633              	@ 0 "" 2
+ 634              	.LVL48:
+1207:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 635              		.loc 2 1207 4 discriminator 1 view .LVU162
+ 636              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU163
+ 637              		.thumb
+ 638              		.syntax unified
+ 639              	.LBE26:
+ 640              	.LBE25:
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 641              		.loc 1 486 3 discriminator 1 view .LVU164
+ 642 001c 0029     		cmp	r1, #0
+ 643 001e F6D1     		bne	.L42
+ 644              	.LBE22:
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 645              		.loc 1 486 3 is_stmt 1 discriminator 2 view .LVU165
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 646              		.loc 1 489 3 discriminator 2 view .LVU166
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 647              		.loc 1 489 3 discriminator 2 view .LVU167
+ 648 0020 0023     		movs	r3, #0
+ 649              	.LVL49:
+ARM GAS  /tmp/ccEfj1JP.s 			page 53
+
+
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 650              		.loc 1 489 3 is_stmt 0 discriminator 2 view .LVU168
+ 651 0022 80F88030 		strb	r3, [r0, #128]
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 652              		.loc 1 489 3 is_stmt 1 discriminator 2 view .LVU169
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 653              		.loc 1 491 3 discriminator 2 view .LVU170
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 654              		.loc 1 491 10 is_stmt 0 discriminator 2 view .LVU171
+ 655 0026 1846     		mov	r0, r3
+ 656              	.LVL50:
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 657              		.loc 1 491 10 discriminator 2 view .LVU172
+ 658 0028 7047     		bx	lr
+ 659              	.LVL51:
+ 660              	.L43:
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 661              		.loc 1 483 3 view .LVU173
+ 662 002a 0220     		movs	r0, #2
+ 663              	.LVL52:
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 664              		.loc 1 492 1 view .LVU174
+ 665 002c 7047     		bx	lr
+ 666              		.cfi_endproc
+ 667              	.LFE335:
+ 669              		.section	.text.HAL_UARTEx_DisableStopMode,"ax",%progbits
+ 670              		.align	1
+ 671              		.global	HAL_UARTEx_DisableStopMode
+ 672              		.syntax unified
+ 673              		.thumb
+ 674              		.thumb_func
+ 676              	HAL_UARTEx_DisableStopMode:
+ 677              	.LVL53:
+ 678              	.LFB336:
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   /* Process Locked */
+ 679              		.loc 1 500 1 is_stmt 1 view -0
+ 680              		.cfi_startproc
+ 681              		@ args = 0, pretend = 0, frame = 0
+ 682              		@ frame_needed = 0, uses_anonymous_args = 0
+ 683              		@ link register save eliminated.
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 684              		.loc 1 502 3 view .LVU176
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 685              		.loc 1 502 3 view .LVU177
+ 686 0000 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 687 0004 012B     		cmp	r3, #1
+ 688 0006 10D0     		beq	.L47
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 689              		.loc 1 502 3 discriminator 2 view .LVU178
+ 690 0008 0123     		movs	r3, #1
+ 691 000a 80F88030 		strb	r3, [r0, #128]
+ 692              	.L46:
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 693              		.loc 1 502 3 discriminator 1 view .LVU179
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 694              		.loc 1 505 3 discriminator 1 view .LVU180
+ 695              	.LBB27:
+ARM GAS  /tmp/ccEfj1JP.s 			page 54
+
+
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 696              		.loc 1 505 3 discriminator 1 view .LVU181
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 697              		.loc 1 505 3 discriminator 1 view .LVU182
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 698              		.loc 1 505 3 discriminator 1 view .LVU183
+ 699 000e 0268     		ldr	r2, [r0]
+ 700              	.LVL54:
+ 701              	.LBB28:
+ 702              	.LBI28:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 703              		.loc 2 1151 31 discriminator 1 view .LVU184
+ 704              	.LBB29:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 705              		.loc 2 1153 5 discriminator 1 view .LVU185
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 706              		.loc 2 1155 4 discriminator 1 view .LVU186
+ 707              		.syntax unified
+ 708              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 709 0010 52E8003F 		ldrex r3, [r2]
+ 710              	@ 0 "" 2
+ 711              	.LVL55:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 712              		.loc 2 1156 4 discriminator 1 view .LVU187
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 713              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU188
+ 714              		.thumb
+ 715              		.syntax unified
+ 716              	.LBE29:
+ 717              	.LBE28:
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 718              		.loc 1 505 3 discriminator 1 view .LVU189
+ 719 0014 23F00203 		bic	r3, r3, #2
+ 720              	.LVL56:
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 721              		.loc 1 505 3 is_stmt 1 discriminator 1 view .LVU190
+ 722              	.LBB30:
+ 723              	.LBI30:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 724              		.loc 2 1202 31 discriminator 1 view .LVU191
+ 725              	.LBB31:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 726              		.loc 2 1204 4 discriminator 1 view .LVU192
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 727              		.loc 2 1206 4 discriminator 1 view .LVU193
+ 728              		.syntax unified
+ 729              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 730 0018 42E80031 		strex r1, r3, [r2]
+ 731              	@ 0 "" 2
+ 732              	.LVL57:
+ 733              		.loc 2 1207 4 discriminator 1 view .LVU194
+ 734              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU195
+ 735              		.thumb
+ 736              		.syntax unified
+ 737              	.LBE31:
+ 738              	.LBE30:
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 55
+
+
+ 739              		.loc 1 505 3 discriminator 1 view .LVU196
+ 740 001c 0029     		cmp	r1, #0
+ 741 001e F6D1     		bne	.L46
+ 742              	.LBE27:
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 743              		.loc 1 505 3 is_stmt 1 discriminator 2 view .LVU197
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 744              		.loc 1 508 3 discriminator 2 view .LVU198
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 745              		.loc 1 508 3 discriminator 2 view .LVU199
+ 746 0020 0023     		movs	r3, #0
+ 747              	.LVL58:
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 748              		.loc 1 508 3 is_stmt 0 discriminator 2 view .LVU200
+ 749 0022 80F88030 		strb	r3, [r0, #128]
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 750              		.loc 1 508 3 is_stmt 1 discriminator 2 view .LVU201
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 751              		.loc 1 510 3 discriminator 2 view .LVU202
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 752              		.loc 1 510 10 is_stmt 0 discriminator 2 view .LVU203
+ 753 0026 1846     		mov	r0, r3
+ 754              	.LVL59:
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 755              		.loc 1 510 10 discriminator 2 view .LVU204
+ 756 0028 7047     		bx	lr
+ 757              	.LVL60:
+ 758              	.L47:
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 759              		.loc 1 502 3 view .LVU205
+ 760 002a 0220     		movs	r0, #2
+ 761              	.LVL61:
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 762              		.loc 1 511 1 view .LVU206
+ 763 002c 7047     		bx	lr
+ 764              		.cfi_endproc
+ 765              	.LFE336:
+ 767              		.section	.text.HAL_UARTEx_EnableFifoMode,"ax",%progbits
+ 768              		.align	1
+ 769              		.global	HAL_UARTEx_EnableFifoMode
+ 770              		.syntax unified
+ 771              		.thumb
+ 772              		.thumb_func
+ 774              	HAL_UARTEx_EnableFifoMode:
+ 775              	.LVL62:
+ 776              	.LFB337:
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tmpcr1;
+ 777              		.loc 1 519 1 is_stmt 1 view -0
+ 778              		.cfi_startproc
+ 779              		@ args = 0, pretend = 0, frame = 0
+ 780              		@ frame_needed = 0, uses_anonymous_args = 0
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 781              		.loc 1 520 3 view .LVU208
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 782              		.loc 1 523 3 view .LVU209
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 783              		.loc 1 526 3 view .LVU210
+ARM GAS  /tmp/ccEfj1JP.s 			page 56
+
+
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 784              		.loc 1 526 3 view .LVU211
+ 785 0000 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 786 0004 012B     		cmp	r3, #1
+ 787 0006 1DD0     		beq	.L50
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tmpcr1;
+ 788              		.loc 1 519 1 is_stmt 0 discriminator 2 view .LVU212
+ 789 0008 10B5     		push	{r4, lr}
+ 790              	.LCFI12:
+ 791              		.cfi_def_cfa_offset 8
+ 792              		.cfi_offset 4, -8
+ 793              		.cfi_offset 14, -4
+ 794 000a 0446     		mov	r4, r0
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 795              		.loc 1 526 3 is_stmt 1 discriminator 2 view .LVU213
+ 796 000c 0123     		movs	r3, #1
+ 797 000e 80F88030 		strb	r3, [r0, #128]
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 798              		.loc 1 526 3 discriminator 2 view .LVU214
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 799              		.loc 1 528 3 discriminator 2 view .LVU215
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 800              		.loc 1 528 17 is_stmt 0 discriminator 2 view .LVU216
+ 801 0012 2423     		movs	r3, #36
+ 802 0014 C0F88430 		str	r3, [r0, #132]
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 803              		.loc 1 531 3 is_stmt 1 discriminator 2 view .LVU217
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 804              		.loc 1 531 12 is_stmt 0 discriminator 2 view .LVU218
+ 805 0018 0268     		ldr	r2, [r0]
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 806              		.loc 1 531 10 discriminator 2 view .LVU219
+ 807 001a 1368     		ldr	r3, [r2]
+ 808              	.LVL63:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 809              		.loc 1 534 3 is_stmt 1 discriminator 2 view .LVU220
+ 810 001c 1168     		ldr	r1, [r2]
+ 811 001e 21F00101 		bic	r1, r1, #1
+ 812 0022 1160     		str	r1, [r2]
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->FifoMode = UART_FIFOMODE_ENABLE;
+ 813              		.loc 1 537 3 discriminator 2 view .LVU221
+ 814 0024 43F00053 		orr	r3, r3, #536870912
+ 815              	.LVL64:
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 816              		.loc 1 538 3 discriminator 2 view .LVU222
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 817              		.loc 1 538 19 is_stmt 0 discriminator 2 view .LVU223
+ 818 0028 4FF00052 		mov	r2, #536870912
+ 819 002c 4266     		str	r2, [r0, #100]
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 820              		.loc 1 541 3 is_stmt 1 discriminator 2 view .LVU224
+ 821 002e 0268     		ldr	r2, [r0]
+ 822 0030 1360     		str	r3, [r2]
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 823              		.loc 1 544 3 discriminator 2 view .LVU225
+ 824 0032 FFF7FEFF 		bl	UARTEx_SetNbDataToProcess
+ 825              	.LVL65:
+ARM GAS  /tmp/ccEfj1JP.s 			page 57
+
+
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 826              		.loc 1 546 3 discriminator 2 view .LVU226
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 827              		.loc 1 546 17 is_stmt 0 discriminator 2 view .LVU227
+ 828 0036 2023     		movs	r3, #32
+ 829 0038 C4F88430 		str	r3, [r4, #132]
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 830              		.loc 1 549 3 is_stmt 1 discriminator 2 view .LVU228
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 831              		.loc 1 549 3 discriminator 2 view .LVU229
+ 832 003c 0020     		movs	r0, #0
+ 833 003e 84F88000 		strb	r0, [r4, #128]
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 834              		.loc 1 549 3 discriminator 2 view .LVU230
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 835              		.loc 1 551 3 discriminator 2 view .LVU231
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 836              		.loc 1 552 1 is_stmt 0 discriminator 2 view .LVU232
+ 837 0042 10BD     		pop	{r4, pc}
+ 838              	.LVL66:
+ 839              	.L50:
+ 840              	.LCFI13:
+ 841              		.cfi_def_cfa_offset 0
+ 842              		.cfi_restore 4
+ 843              		.cfi_restore 14
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 844              		.loc 1 526 3 view .LVU233
+ 845 0044 0220     		movs	r0, #2
+ 846              	.LVL67:
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 847              		.loc 1 552 1 view .LVU234
+ 848 0046 7047     		bx	lr
+ 849              		.cfi_endproc
+ 850              	.LFE337:
+ 852              		.section	.text.HAL_UARTEx_DisableFifoMode,"ax",%progbits
+ 853              		.align	1
+ 854              		.global	HAL_UARTEx_DisableFifoMode
+ 855              		.syntax unified
+ 856              		.thumb
+ 857              		.thumb_func
+ 859              	HAL_UARTEx_DisableFifoMode:
+ 860              	.LVL68:
+ 861              	.LFB338:
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tmpcr1;
+ 862              		.loc 1 560 1 is_stmt 1 view -0
+ 863              		.cfi_startproc
+ 864              		@ args = 0, pretend = 0, frame = 0
+ 865              		@ frame_needed = 0, uses_anonymous_args = 0
+ 866              		@ link register save eliminated.
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 867              		.loc 1 561 3 view .LVU236
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 868              		.loc 1 564 3 view .LVU237
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 869              		.loc 1 567 3 view .LVU238
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 870              		.loc 1 567 3 view .LVU239
+ARM GAS  /tmp/ccEfj1JP.s 			page 58
+
+
+ 871 0000 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 872 0004 012B     		cmp	r3, #1
+ 873 0006 18D0     		beq	.L57
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 874              		.loc 1 567 3 discriminator 2 view .LVU240
+ 875 0008 0123     		movs	r3, #1
+ 876 000a 80F88030 		strb	r3, [r0, #128]
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 877              		.loc 1 567 3 discriminator 2 view .LVU241
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 878              		.loc 1 569 3 discriminator 2 view .LVU242
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 879              		.loc 1 569 17 is_stmt 0 discriminator 2 view .LVU243
+ 880 000e 2423     		movs	r3, #36
+ 881 0010 C0F88430 		str	r3, [r0, #132]
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 882              		.loc 1 572 3 is_stmt 1 discriminator 2 view .LVU244
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 883              		.loc 1 572 12 is_stmt 0 discriminator 2 view .LVU245
+ 884 0014 0368     		ldr	r3, [r0]
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 885              		.loc 1 572 10 discriminator 2 view .LVU246
+ 886 0016 1A68     		ldr	r2, [r3]
+ 887              	.LVL69:
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 888              		.loc 1 575 3 is_stmt 1 discriminator 2 view .LVU247
+ 889 0018 1968     		ldr	r1, [r3]
+ 890 001a 21F00101 		bic	r1, r1, #1
+ 891 001e 1960     		str	r1, [r3]
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   huart->FifoMode = UART_FIFOMODE_DISABLE;
+ 892              		.loc 1 578 3 discriminator 2 view .LVU248
+ 893 0020 22F00052 		bic	r2, r2, #536870912
+ 894              	.LVL70:
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 895              		.loc 1 579 3 discriminator 2 view .LVU249
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 896              		.loc 1 579 19 is_stmt 0 discriminator 2 view .LVU250
+ 897 0024 0023     		movs	r3, #0
+ 898 0026 4366     		str	r3, [r0, #100]
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 899              		.loc 1 582 3 is_stmt 1 discriminator 2 view .LVU251
+ 900 0028 0168     		ldr	r1, [r0]
+ 901 002a 0A60     		str	r2, [r1]
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 902              		.loc 1 584 3 discriminator 2 view .LVU252
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 903              		.loc 1 584 17 is_stmt 0 discriminator 2 view .LVU253
+ 904 002c 2022     		movs	r2, #32
+ 905              	.LVL71:
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 906              		.loc 1 584 17 discriminator 2 view .LVU254
+ 907 002e C0F88420 		str	r2, [r0, #132]
+ 908              	.LVL72:
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 909              		.loc 1 587 3 is_stmt 1 discriminator 2 view .LVU255
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 910              		.loc 1 587 3 discriminator 2 view .LVU256
+ARM GAS  /tmp/ccEfj1JP.s 			page 59
+
+
+ 911 0032 80F88030 		strb	r3, [r0, #128]
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 912              		.loc 1 587 3 discriminator 2 view .LVU257
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 913              		.loc 1 589 3 discriminator 2 view .LVU258
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 914              		.loc 1 589 10 is_stmt 0 discriminator 2 view .LVU259
+ 915 0036 1846     		mov	r0, r3
+ 916              	.LVL73:
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 917              		.loc 1 589 10 discriminator 2 view .LVU260
+ 918 0038 7047     		bx	lr
+ 919              	.LVL74:
+ 920              	.L57:
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 921              		.loc 1 567 3 view .LVU261
+ 922 003a 0220     		movs	r0, #2
+ 923              	.LVL75:
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 924              		.loc 1 590 1 view .LVU262
+ 925 003c 7047     		bx	lr
+ 926              		.cfi_endproc
+ 927              	.LFE338:
+ 929              		.section	.text.HAL_UARTEx_SetTxFifoThreshold,"ax",%progbits
+ 930              		.align	1
+ 931              		.global	HAL_UARTEx_SetTxFifoThreshold
+ 932              		.syntax unified
+ 933              		.thumb
+ 934              		.thumb_func
+ 936              	HAL_UARTEx_SetTxFifoThreshold:
+ 937              	.LVL76:
+ 938              	.LFB339:
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tmpcr1;
+ 939              		.loc 1 606 1 is_stmt 1 view -0
+ 940              		.cfi_startproc
+ 941              		@ args = 0, pretend = 0, frame = 0
+ 942              		@ frame_needed = 0, uses_anonymous_args = 0
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tmpcr1;
+ 943              		.loc 1 606 1 is_stmt 0 view .LVU264
+ 944 0000 38B5     		push	{r3, r4, r5, lr}
+ 945              	.LCFI14:
+ 946              		.cfi_def_cfa_offset 16
+ 947              		.cfi_offset 3, -16
+ 948              		.cfi_offset 4, -12
+ 949              		.cfi_offset 5, -8
+ 950              		.cfi_offset 14, -4
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 951              		.loc 1 607 3 is_stmt 1 view .LVU265
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+ 952              		.loc 1 610 3 view .LVU266
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 953              		.loc 1 611 3 view .LVU267
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 954              		.loc 1 614 3 view .LVU268
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 955              		.loc 1 614 3 view .LVU269
+ 956 0002 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ARM GAS  /tmp/ccEfj1JP.s 			page 60
+
+
+ 957 0006 012B     		cmp	r3, #1
+ 958 0008 1DD0     		beq	.L60
+ 959 000a 0446     		mov	r4, r0
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 960              		.loc 1 614 3 discriminator 2 view .LVU270
+ 961 000c 0123     		movs	r3, #1
+ 962 000e 80F88030 		strb	r3, [r0, #128]
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 963              		.loc 1 614 3 discriminator 2 view .LVU271
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 964              		.loc 1 616 3 discriminator 2 view .LVU272
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 965              		.loc 1 616 17 is_stmt 0 discriminator 2 view .LVU273
+ 966 0012 2423     		movs	r3, #36
+ 967 0014 C0F88430 		str	r3, [r0, #132]
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 968              		.loc 1 619 3 is_stmt 1 discriminator 2 view .LVU274
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 969              		.loc 1 619 12 is_stmt 0 discriminator 2 view .LVU275
+ 970 0018 0368     		ldr	r3, [r0]
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 971              		.loc 1 619 10 discriminator 2 view .LVU276
+ 972 001a 1D68     		ldr	r5, [r3]
+ 973              	.LVL77:
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 974              		.loc 1 622 3 is_stmt 1 discriminator 2 view .LVU277
+ 975 001c 1A68     		ldr	r2, [r3]
+ 976 001e 22F00102 		bic	r2, r2, #1
+ 977 0022 1A60     		str	r2, [r3]
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 978              		.loc 1 625 3 discriminator 2 view .LVU278
+ 979 0024 0268     		ldr	r2, [r0]
+ 980 0026 9368     		ldr	r3, [r2, #8]
+ 981 0028 23F06043 		bic	r3, r3, #-536870912
+ 982 002c 1943     		orrs	r1, r1, r3
+ 983              	.LVL78:
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 984              		.loc 1 625 3 is_stmt 0 discriminator 2 view .LVU279
+ 985 002e 9160     		str	r1, [r2, #8]
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 986              		.loc 1 628 3 is_stmt 1 discriminator 2 view .LVU280
+ 987 0030 FFF7FEFF 		bl	UARTEx_SetNbDataToProcess
+ 988              	.LVL79:
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 989              		.loc 1 631 3 discriminator 2 view .LVU281
+ 990 0034 2368     		ldr	r3, [r4]
+ 991 0036 1D60     		str	r5, [r3]
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 992              		.loc 1 633 3 discriminator 2 view .LVU282
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 993              		.loc 1 633 17 is_stmt 0 discriminator 2 view .LVU283
+ 994 0038 2023     		movs	r3, #32
+ 995 003a C4F88430 		str	r3, [r4, #132]
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 996              		.loc 1 636 3 is_stmt 1 discriminator 2 view .LVU284
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 997              		.loc 1 636 3 discriminator 2 view .LVU285
+ARM GAS  /tmp/ccEfj1JP.s 			page 61
+
+
+ 998 003e 0020     		movs	r0, #0
+ 999 0040 84F88000 		strb	r0, [r4, #128]
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1000              		.loc 1 636 3 discriminator 2 view .LVU286
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 1001              		.loc 1 638 3 discriminator 2 view .LVU287
+ 1002              	.LVL80:
+ 1003              	.L59:
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1004              		.loc 1 639 1 is_stmt 0 view .LVU288
+ 1005 0044 38BD     		pop	{r3, r4, r5, pc}
+ 1006              	.LVL81:
+ 1007              	.L60:
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1008              		.loc 1 614 3 view .LVU289
+ 1009 0046 0220     		movs	r0, #2
+ 1010              	.LVL82:
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1011              		.loc 1 614 3 view .LVU290
+ 1012 0048 FCE7     		b	.L59
+ 1013              		.cfi_endproc
+ 1014              	.LFE339:
+ 1016              		.section	.text.HAL_UARTEx_SetRxFifoThreshold,"ax",%progbits
+ 1017              		.align	1
+ 1018              		.global	HAL_UARTEx_SetRxFifoThreshold
+ 1019              		.syntax unified
+ 1020              		.thumb
+ 1021              		.thumb_func
+ 1023              	HAL_UARTEx_SetRxFifoThreshold:
+ 1024              	.LVL83:
+ 1025              	.LFB340:
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tmpcr1;
+ 1026              		.loc 1 655 1 is_stmt 1 view -0
+ 1027              		.cfi_startproc
+ 1028              		@ args = 0, pretend = 0, frame = 0
+ 1029              		@ frame_needed = 0, uses_anonymous_args = 0
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tmpcr1;
+ 1030              		.loc 1 655 1 is_stmt 0 view .LVU292
+ 1031 0000 38B5     		push	{r3, r4, r5, lr}
+ 1032              	.LCFI15:
+ 1033              		.cfi_def_cfa_offset 16
+ 1034              		.cfi_offset 3, -16
+ 1035              		.cfi_offset 4, -12
+ 1036              		.cfi_offset 5, -8
+ 1037              		.cfi_offset 14, -4
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1038              		.loc 1 656 3 is_stmt 1 view .LVU293
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+ 1039              		.loc 1 659 3 view .LVU294
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1040              		.loc 1 660 3 view .LVU295
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1041              		.loc 1 663 3 view .LVU296
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1042              		.loc 1 663 3 view .LVU297
+ 1043 0002 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 1044 0006 012B     		cmp	r3, #1
+ARM GAS  /tmp/ccEfj1JP.s 			page 62
+
+
+ 1045 0008 1DD0     		beq	.L64
+ 1046 000a 0446     		mov	r4, r0
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1047              		.loc 1 663 3 discriminator 2 view .LVU298
+ 1048 000c 0123     		movs	r3, #1
+ 1049 000e 80F88030 		strb	r3, [r0, #128]
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1050              		.loc 1 663 3 discriminator 2 view .LVU299
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1051              		.loc 1 665 3 discriminator 2 view .LVU300
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1052              		.loc 1 665 17 is_stmt 0 discriminator 2 view .LVU301
+ 1053 0012 2423     		movs	r3, #36
+ 1054 0014 C0F88430 		str	r3, [r0, #132]
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1055              		.loc 1 668 3 is_stmt 1 discriminator 2 view .LVU302
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1056              		.loc 1 668 12 is_stmt 0 discriminator 2 view .LVU303
+ 1057 0018 0368     		ldr	r3, [r0]
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1058              		.loc 1 668 10 discriminator 2 view .LVU304
+ 1059 001a 1D68     		ldr	r5, [r3]
+ 1060              	.LVL84:
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1061              		.loc 1 671 3 is_stmt 1 discriminator 2 view .LVU305
+ 1062 001c 1A68     		ldr	r2, [r3]
+ 1063 001e 22F00102 		bic	r2, r2, #1
+ 1064 0022 1A60     		str	r2, [r3]
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1065              		.loc 1 674 3 discriminator 2 view .LVU306
+ 1066 0024 0268     		ldr	r2, [r0]
+ 1067 0026 9368     		ldr	r3, [r2, #8]
+ 1068 0028 23F06063 		bic	r3, r3, #234881024
+ 1069 002c 1943     		orrs	r1, r1, r3
+ 1070              	.LVL85:
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1071              		.loc 1 674 3 is_stmt 0 discriminator 2 view .LVU307
+ 1072 002e 9160     		str	r1, [r2, #8]
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1073              		.loc 1 677 3 is_stmt 1 discriminator 2 view .LVU308
+ 1074 0030 FFF7FEFF 		bl	UARTEx_SetNbDataToProcess
+ 1075              	.LVL86:
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1076              		.loc 1 680 3 discriminator 2 view .LVU309
+ 1077 0034 2368     		ldr	r3, [r4]
+ 1078 0036 1D60     		str	r5, [r3]
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1079              		.loc 1 682 3 discriminator 2 view .LVU310
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1080              		.loc 1 682 17 is_stmt 0 discriminator 2 view .LVU311
+ 1081 0038 2023     		movs	r3, #32
+ 1082 003a C4F88430 		str	r3, [r4, #132]
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1083              		.loc 1 685 3 is_stmt 1 discriminator 2 view .LVU312
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1084              		.loc 1 685 3 discriminator 2 view .LVU313
+ 1085 003e 0020     		movs	r0, #0
+ARM GAS  /tmp/ccEfj1JP.s 			page 63
+
+
+ 1086 0040 84F88000 		strb	r0, [r4, #128]
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1087              		.loc 1 685 3 discriminator 2 view .LVU314
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
+ 1088              		.loc 1 687 3 discriminator 2 view .LVU315
+ 1089              	.LVL87:
+ 1090              	.L63:
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1091              		.loc 1 688 1 is_stmt 0 view .LVU316
+ 1092 0044 38BD     		pop	{r3, r4, r5, pc}
+ 1093              	.LVL88:
+ 1094              	.L64:
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1095              		.loc 1 663 3 view .LVU317
+ 1096 0046 0220     		movs	r0, #2
+ 1097              	.LVL89:
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1098              		.loc 1 663 3 view .LVU318
+ 1099 0048 FCE7     		b	.L63
+ 1100              		.cfi_endproc
+ 1101              	.LFE340:
+ 1103              		.section	.text.HAL_UARTEx_ReceiveToIdle,"ax",%progbits
+ 1104              		.align	1
+ 1105              		.global	HAL_UARTEx_ReceiveToIdle
+ 1106              		.syntax unified
+ 1107              		.thumb
+ 1108              		.thumb_func
+ 1110              	HAL_UARTEx_ReceiveToIdle:
+ 1111              	.LVL90:
+ 1112              	.LFB341:
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint8_t  *pdata8bits;
+ 1113              		.loc 1 713 1 is_stmt 1 view -0
+ 1114              		.cfi_startproc
+ 1115              		@ args = 4, pretend = 0, frame = 0
+ 1116              		@ frame_needed = 0, uses_anonymous_args = 0
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint8_t  *pdata8bits;
+ 1117              		.loc 1 713 1 is_stmt 0 view .LVU320
+ 1118 0000 2DE9F047 		push	{r4, r5, r6, r7, r8, r9, r10, lr}
+ 1119              	.LCFI16:
+ 1120              		.cfi_def_cfa_offset 32
+ 1121              		.cfi_offset 4, -32
+ 1122              		.cfi_offset 5, -28
+ 1123              		.cfi_offset 6, -24
+ 1124              		.cfi_offset 7, -20
+ 1125              		.cfi_offset 8, -16
+ 1126              		.cfi_offset 9, -12
+ 1127              		.cfi_offset 10, -8
+ 1128              		.cfi_offset 14, -4
+ 1129 0004 1D46     		mov	r5, r3
+ 1130 0006 089E     		ldr	r6, [sp, #32]
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint16_t *pdata16bits;
+ 1131              		.loc 1 714 3 is_stmt 1 view .LVU321
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint16_t uhMask;
+ 1132              		.loc 1 715 3 view .LVU322
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   uint32_t tickstart;
+ 1133              		.loc 1 716 3 view .LVU323
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ARM GAS  /tmp/ccEfj1JP.s 			page 64
+
+
+ 1134              		.loc 1 717 3 view .LVU324
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 1135              		.loc 1 720 3 view .LVU325
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 1136              		.loc 1 720 12 is_stmt 0 view .LVU326
+ 1137 0008 D0F88830 		ldr	r3, [r0, #136]
+ 1138              	.LVL91:
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 1139              		.loc 1 720 6 view .LVU327
+ 1140 000c 202B     		cmp	r3, #32
+ 1141 000e 40F0A980 		bne	.L84
+ 1142 0012 0446     		mov	r4, r0
+ 1143 0014 0F46     		mov	r7, r1
+ 1144 0016 9146     		mov	r9, r2
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1145              		.loc 1 722 5 is_stmt 1 view .LVU328
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1146              		.loc 1 722 8 is_stmt 0 view .LVU329
+ 1147 0018 0029     		cmp	r1, #0
+ 1148 001a 00F0A680 		beq	.L85
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1149              		.loc 1 722 25 discriminator 1 view .LVU330
+ 1150 001e 002A     		cmp	r2, #0
+ 1151 0020 00F0A580 		beq	.L86
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1152              		.loc 1 727 5 is_stmt 1 view .LVU331
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1153              		.loc 1 727 5 view .LVU332
+ 1154 0024 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 1155 0028 012B     		cmp	r3, #1
+ 1156 002a 00F0A280 		beq	.L87
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1157              		.loc 1 727 5 discriminator 2 view .LVU333
+ 1158 002e 0123     		movs	r3, #1
+ 1159 0030 80F88030 		strb	r3, [r0, #128]
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1160              		.loc 1 727 5 discriminator 2 view .LVU334
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 1161              		.loc 1 729 5 discriminator 2 view .LVU335
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 1162              		.loc 1 729 22 is_stmt 0 discriminator 2 view .LVU336
+ 1163 0034 0022     		movs	r2, #0
+ 1164              	.LVL92:
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 1165              		.loc 1 729 22 discriminator 2 view .LVU337
+ 1166 0036 C0F88C20 		str	r2, [r0, #140]
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ 1167              		.loc 1 730 5 is_stmt 1 discriminator 2 view .LVU338
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ 1168              		.loc 1 730 20 is_stmt 0 discriminator 2 view .LVU339
+ 1169 003a 2222     		movs	r2, #34
+ 1170 003c C0F88820 		str	r2, [r0, #136]
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1171              		.loc 1 731 5 is_stmt 1 discriminator 2 view .LVU340
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1172              		.loc 1 731 26 is_stmt 0 discriminator 2 view .LVU341
+ 1173 0040 C366     		str	r3, [r0, #108]
+ARM GAS  /tmp/ccEfj1JP.s 			page 65
+
+
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1174              		.loc 1 734 5 is_stmt 1 discriminator 2 view .LVU342
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1175              		.loc 1 734 17 is_stmt 0 discriminator 2 view .LVU343
+ 1176 0042 FFF7FEFF 		bl	HAL_GetTick
+ 1177              	.LVL93:
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1178              		.loc 1 734 17 discriminator 2 view .LVU344
+ 1179 0046 8046     		mov	r8, r0
+ 1180              	.LVL94:
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->RxXferCount = Size;
+ 1181              		.loc 1 736 5 is_stmt 1 discriminator 2 view .LVU345
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     huart->RxXferCount = Size;
+ 1182              		.loc 1 736 24 is_stmt 0 discriminator 2 view .LVU346
+ 1183 0048 A4F85C90 		strh	r9, [r4, #92]	@ movhi
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1184              		.loc 1 737 5 is_stmt 1 discriminator 2 view .LVU347
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1185              		.loc 1 737 24 is_stmt 0 discriminator 2 view .LVU348
+ 1186 004c A4F85E90 		strh	r9, [r4, #94]	@ movhi
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1187              		.loc 1 740 5 is_stmt 1 discriminator 2 view .LVU349
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1188              		.loc 1 740 5 discriminator 2 view .LVU350
+ 1189 0050 A368     		ldr	r3, [r4, #8]
+ 1190 0052 B3F5805F 		cmp	r3, #4096
+ 1191 0056 06D0     		beq	.L91
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1192              		.loc 1 740 5 discriminator 2 view .LVU351
+ 1193 0058 A3B9     		cbnz	r3, .L71
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1194              		.loc 1 740 5 discriminator 5 view .LVU352
+ 1195 005a 2269     		ldr	r2, [r4, #16]
+ 1196 005c 72B9     		cbnz	r2, .L72
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1197              		.loc 1 740 5 discriminator 7 view .LVU353
+ 1198 005e FF22     		movs	r2, #255
+ 1199 0060 A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 1200 0064 14E0     		b	.L70
+ 1201              	.L91:
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1202              		.loc 1 740 5 discriminator 1 view .LVU354
+ 1203 0066 2269     		ldr	r2, [r4, #16]
+ 1204 0068 22B9     		cbnz	r2, .L69
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1205              		.loc 1 740 5 discriminator 3 view .LVU355
+ 1206 006a 40F2FF12 		movw	r2, #511
+ 1207 006e A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 1208 0072 0DE0     		b	.L70
+ 1209              	.L69:
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1210              		.loc 1 740 5 discriminator 4 view .LVU356
+ 1211 0074 FF22     		movs	r2, #255
+ 1212 0076 A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 1213 007a 09E0     		b	.L70
+ 1214              	.L72:
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ARM GAS  /tmp/ccEfj1JP.s 			page 66
+
+
+ 1215              		.loc 1 740 5 discriminator 8 view .LVU357
+ 1216 007c 7F22     		movs	r2, #127
+ 1217 007e A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 1218 0082 05E0     		b	.L70
+ 1219              	.L71:
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1220              		.loc 1 740 5 discriminator 6 view .LVU358
+ 1221 0084 B3F1805F 		cmp	r3, #268435456
+ 1222 0088 0ED0     		beq	.L92
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1223              		.loc 1 740 5 discriminator 10 view .LVU359
+ 1224 008a 0022     		movs	r2, #0
+ 1225 008c A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 1226              	.L70:
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1227              		.loc 1 740 5 discriminator 13 view .LVU360
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1228              		.loc 1 741 5 discriminator 13 view .LVU361
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1229              		.loc 1 741 12 is_stmt 0 discriminator 13 view .LVU362
+ 1230 0090 B4F86090 		ldrh	r9, [r4, #96]
+ 1231              	.LVL95:
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1232              		.loc 1 744 5 is_stmt 1 discriminator 13 view .LVU363
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1233              		.loc 1 744 8 is_stmt 0 discriminator 13 view .LVU364
+ 1234 0094 B3F5805F 		cmp	r3, #4096
+ 1235 0098 10D0     		beq	.L93
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1236              		.loc 1 752 19 view .LVU365
+ 1237 009a 4FF0000A 		mov	r10, #0
+ 1238              	.LVL96:
+ 1239              	.L75:
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1240              		.loc 1 755 5 is_stmt 1 view .LVU366
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1241              		.loc 1 755 5 view .LVU367
+ 1242 009e 0023     		movs	r3, #0
+ 1243 00a0 84F88030 		strb	r3, [r4, #128]
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1244              		.loc 1 755 5 view .LVU368
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1245              		.loc 1 758 5 view .LVU369
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1246              		.loc 1 758 12 is_stmt 0 view .LVU370
+ 1247 00a4 2B80     		strh	r3, [r5]	@ movhi
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1248              		.loc 1 761 5 is_stmt 1 view .LVU371
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1249              		.loc 1 761 11 is_stmt 0 view .LVU372
+ 1250 00a6 28E0     		b	.L76
+ 1251              	.LVL97:
+ 1252              	.L92:
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1253              		.loc 1 740 5 is_stmt 1 discriminator 9 view .LVU373
+ 1254 00a8 2269     		ldr	r2, [r4, #16]
+ 1255 00aa 1AB9     		cbnz	r2, .L74
+ARM GAS  /tmp/ccEfj1JP.s 			page 67
+
+
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1256              		.loc 1 740 5 discriminator 11 view .LVU374
+ 1257 00ac 7F22     		movs	r2, #127
+ 1258 00ae A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 1259 00b2 EDE7     		b	.L70
+ 1260              	.L74:
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     uhMask = huart->Mask;
+ 1261              		.loc 1 740 5 discriminator 12 view .LVU375
+ 1262 00b4 3F22     		movs	r2, #63
+ 1263 00b6 A4F86020 		strh	r2, [r4, #96]	@ movhi
+ 1264 00ba E9E7     		b	.L70
+ 1265              	.LVL98:
+ 1266              	.L93:
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1267              		.loc 1 744 71 is_stmt 0 discriminator 1 view .LVU376
+ 1268 00bc 2369     		ldr	r3, [r4, #16]
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1269              		.loc 1 744 56 discriminator 1 view .LVU377
+ 1270 00be 13B1     		cbz	r3, .L89
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1271              		.loc 1 752 19 view .LVU378
+ 1272 00c0 4FF0000A 		mov	r10, #0
+ 1273 00c4 EBE7     		b	.L75
+ 1274              	.L89:
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1275              		.loc 1 747 19 view .LVU379
+ 1276 00c6 BA46     		mov	r10, r7
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       pdata16bits = (uint16_t *) pData;
+ 1277              		.loc 1 746 19 view .LVU380
+ 1278 00c8 0027     		movs	r7, #0
+ 1279              	.LVL99:
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       pdata16bits = (uint16_t *) pData;
+ 1280              		.loc 1 746 19 view .LVU381
+ 1281 00ca E8E7     		b	.L75
+ 1282              	.LVL100:
+ 1283              	.L96:
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1284              		.loc 1 773 11 is_stmt 1 view .LVU382
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1285              		.loc 1 773 26 is_stmt 0 view .LVU383
+ 1286 00cc 2023     		movs	r3, #32
+ 1287 00ce C4F88830 		str	r3, [r4, #136]
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         }
+ 1288              		.loc 1 775 11 is_stmt 1 view .LVU384
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         }
+ 1289              		.loc 1 775 18 is_stmt 0 view .LVU385
+ 1290 00d2 0020     		movs	r0, #0
+ 1291 00d4 47E0     		b	.L67
+ 1292              	.L97:
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           pdata16bits++;
+ 1293              		.loc 1 784 11 is_stmt 1 view .LVU386
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           pdata16bits++;
+ 1294              		.loc 1 784 52 is_stmt 0 view .LVU387
+ 1295 00d6 5B6A     		ldr	r3, [r3, #36]
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           pdata16bits++;
+ 1296              		.loc 1 784 26 view .LVU388
+ 1297 00d8 09EA0303 		and	r3, r9, r3
+ARM GAS  /tmp/ccEfj1JP.s 			page 68
+
+
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           pdata16bits++;
+ 1298              		.loc 1 784 24 view .LVU389
+ 1299 00dc 2AF8023B 		strh	r3, [r10], #2	@ movhi
+ 1300              	.LVL101:
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         }
+ 1301              		.loc 1 785 11 is_stmt 1 view .LVU390
+ 1302              	.L80:
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         huart->RxXferCount--;
+ 1303              		.loc 1 793 9 view .LVU391
+ 1304 00e0 2B88     		ldrh	r3, [r5]
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         huart->RxXferCount--;
+ 1305              		.loc 1 793 16 is_stmt 0 view .LVU392
+ 1306 00e2 0133     		adds	r3, r3, #1
+ 1307 00e4 2B80     		strh	r3, [r5]	@ movhi
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1308              		.loc 1 794 9 is_stmt 1 view .LVU393
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1309              		.loc 1 794 14 is_stmt 0 view .LVU394
+ 1310 00e6 B4F85E30 		ldrh	r3, [r4, #94]
+ 1311 00ea 9BB2     		uxth	r3, r3
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1312              		.loc 1 794 27 view .LVU395
+ 1313 00ec 013B     		subs	r3, r3, #1
+ 1314 00ee 9BB2     		uxth	r3, r3
+ 1315 00f0 A4F85E30 		strh	r3, [r4, #94]	@ movhi
+ 1316              	.L78:
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1317              		.loc 1 798 7 is_stmt 1 view .LVU396
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1318              		.loc 1 798 10 is_stmt 0 view .LVU397
+ 1319 00f4 B6F1FF3F 		cmp	r6, #-1
+ 1320 00f8 1BD1     		bne	.L94
+ 1321              	.L76:
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1322              		.loc 1 761 31 is_stmt 1 view .LVU398
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1323              		.loc 1 761 17 is_stmt 0 view .LVU399
+ 1324 00fa B4F85E20 		ldrh	r2, [r4, #94]
+ 1325 00fe 92B2     		uxth	r2, r2
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1326              		.loc 1 761 31 view .LVU400
+ 1327 0100 22B3     		cbz	r2, .L95
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1328              		.loc 1 764 7 is_stmt 1 view .LVU401
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1329              		.loc 1 764 11 is_stmt 0 view .LVU402
+ 1330 0102 2368     		ldr	r3, [r4]
+ 1331 0104 DA69     		ldr	r2, [r3, #28]
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1332              		.loc 1 764 10 view .LVU403
+ 1333 0106 12F0100F 		tst	r2, #16
+ 1334 010a 04D0     		beq	.L77
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1335              		.loc 1 767 9 is_stmt 1 view .LVU404
+ 1336 010c 1022     		movs	r2, #16
+ 1337 010e 1A62     		str	r2, [r3, #32]
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ARM GAS  /tmp/ccEfj1JP.s 			page 69
+
+
+ 1338              		.loc 1 771 9 view .LVU405
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 1339              		.loc 1 771 13 is_stmt 0 view .LVU406
+ 1340 0110 2B88     		ldrh	r3, [r5]
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 1341              		.loc 1 771 12 view .LVU407
+ 1342 0112 002B     		cmp	r3, #0
+ 1343 0114 DAD1     		bne	.L96
+ 1344              	.L77:
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1345              		.loc 1 780 7 is_stmt 1 view .LVU408
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1346              		.loc 1 780 11 is_stmt 0 view .LVU409
+ 1347 0116 2368     		ldr	r3, [r4]
+ 1348 0118 DA69     		ldr	r2, [r3, #28]
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1349              		.loc 1 780 10 view .LVU410
+ 1350 011a 12F0200F 		tst	r2, #32
+ 1351 011e E9D0     		beq	.L78
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 1352              		.loc 1 782 9 is_stmt 1 view .LVU411
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 1353              		.loc 1 782 12 is_stmt 0 view .LVU412
+ 1354 0120 002F     		cmp	r7, #0
+ 1355 0122 D8D0     		beq	.L97
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           pdata8bits++;
+ 1356              		.loc 1 789 11 is_stmt 1 view .LVU413
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           pdata8bits++;
+ 1357              		.loc 1 789 50 is_stmt 0 view .LVU414
+ 1358 0124 5A6A     		ldr	r2, [r3, #36]
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           pdata8bits++;
+ 1359              		.loc 1 789 58 view .LVU415
+ 1360 0126 5FFA89F3 		uxtb	r3, r9
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           pdata8bits++;
+ 1361              		.loc 1 789 25 view .LVU416
+ 1362 012a 1340     		ands	r3, r3, r2
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****           pdata8bits++;
+ 1363              		.loc 1 789 23 view .LVU417
+ 1364 012c 07F8013B 		strb	r3, [r7], #1
+ 1365              	.LVL102:
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         }
+ 1366              		.loc 1 790 11 is_stmt 1 view .LVU418
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         }
+ 1367              		.loc 1 790 11 is_stmt 0 view .LVU419
+ 1368 0130 D6E7     		b	.L80
+ 1369              	.L94:
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 1370              		.loc 1 800 9 is_stmt 1 view .LVU420
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 1371              		.loc 1 800 15 is_stmt 0 view .LVU421
+ 1372 0132 FFF7FEFF 		bl	HAL_GetTick
+ 1373              	.LVL103:
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 1374              		.loc 1 800 29 view .LVU422
+ 1375 0136 A0EB0800 		sub	r0, r0, r8
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 1376              		.loc 1 800 12 view .LVU423
+ARM GAS  /tmp/ccEfj1JP.s 			page 70
+
+
+ 1377 013a B042     		cmp	r0, r6
+ 1378 013c 01D8     		bhi	.L82
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         {
+ 1379              		.loc 1 800 53 discriminator 1 view .LVU424
+ 1380 013e 002E     		cmp	r6, #0
+ 1381 0140 DBD1     		bne	.L76
+ 1382              	.L82:
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1383              		.loc 1 802 11 is_stmt 1 view .LVU425
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1384              		.loc 1 802 26 is_stmt 0 view .LVU426
+ 1385 0142 2023     		movs	r3, #32
+ 1386 0144 C4F88830 		str	r3, [r4, #136]
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         }
+ 1387              		.loc 1 804 11 is_stmt 1 view .LVU427
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         }
+ 1388              		.loc 1 804 18 is_stmt 0 view .LVU428
+ 1389 0148 0320     		movs	r0, #3
+ 1390 014a 0CE0     		b	.L67
+ 1391              	.L95:
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* At end of Rx process, restore huart->RxState to Ready */
+ 1392              		.loc 1 810 5 is_stmt 1 view .LVU429
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* At end of Rx process, restore huart->RxState to Ready */
+ 1393              		.loc 1 810 19 is_stmt 0 view .LVU430
+ 1394 014c B4F85C30 		ldrh	r3, [r4, #92]
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* At end of Rx process, restore huart->RxState to Ready */
+ 1395              		.loc 1 810 39 view .LVU431
+ 1396 0150 B4F85E20 		ldrh	r2, [r4, #94]
+ 1397 0154 92B2     		uxth	r2, r2
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* At end of Rx process, restore huart->RxState to Ready */
+ 1398              		.loc 1 810 32 view .LVU432
+ 1399 0156 9B1A     		subs	r3, r3, r2
+ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     /* At end of Rx process, restore huart->RxState to Ready */
+ 1400              		.loc 1 810 12 view .LVU433
+ 1401 0158 2B80     		strh	r3, [r5]	@ movhi
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1402              		.loc 1 812 5 is_stmt 1 view .LVU434
+ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1403              		.loc 1 812 20 is_stmt 0 view .LVU435
+ 1404 015a 2023     		movs	r3, #32
+ 1405 015c C4F88830 		str	r3, [r4, #136]
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 1406              		.loc 1 814 5 is_stmt 1 view .LVU436
+ 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 1407              		.loc 1 814 12 is_stmt 0 view .LVU437
+ 1408 0160 0020     		movs	r0, #0
+ 1409 0162 00E0     		b	.L67
+ 1410              	.LVL104:
+ 1411              	.L84:
+ 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 1412              		.loc 1 818 12 view .LVU438
+ 1413 0164 0220     		movs	r0, #2
+ 1414              	.LVL105:
+ 1415              	.L67:
+ 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1416              		.loc 1 820 1 view .LVU439
+ 1417 0166 BDE8F087 		pop	{r4, r5, r6, r7, r8, r9, r10, pc}
+ARM GAS  /tmp/ccEfj1JP.s 			page 71
+
+
+ 1418              	.LVL106:
+ 1419              	.L85:
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1420              		.loc 1 724 15 view .LVU440
+ 1421 016a 0120     		movs	r0, #1
+ 1422              	.LVL107:
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1423              		.loc 1 724 15 view .LVU441
+ 1424 016c FBE7     		b	.L67
+ 1425              	.LVL108:
+ 1426              	.L86:
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1427              		.loc 1 724 15 view .LVU442
+ 1428 016e 0120     		movs	r0, #1
+ 1429              	.LVL109:
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1430              		.loc 1 724 15 view .LVU443
+ 1431 0170 F9E7     		b	.L67
+ 1432              	.LVL110:
+ 1433              	.L87:
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1434              		.loc 1 727 5 view .LVU444
+ 1435 0172 0220     		movs	r0, #2
+ 1436              	.LVL111:
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1437              		.loc 1 727 5 view .LVU445
+ 1438 0174 F7E7     		b	.L67
+ 1439              		.cfi_endproc
+ 1440              	.LFE341:
+ 1442              		.section	.text.HAL_UARTEx_ReceiveToIdle_IT,"ax",%progbits
+ 1443              		.align	1
+ 1444              		.global	HAL_UARTEx_ReceiveToIdle_IT
+ 1445              		.syntax unified
+ 1446              		.thumb
+ 1447              		.thumb_func
+ 1449              	HAL_UARTEx_ReceiveToIdle_IT:
+ 1450              	.LVL112:
+ 1451              	.LFB342:
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   HAL_StatusTypeDef status;
+ 1452              		.loc 1 837 1 is_stmt 1 view -0
+ 1453              		.cfi_startproc
+ 1454              		@ args = 0, pretend = 0, frame = 0
+ 1455              		@ frame_needed = 0, uses_anonymous_args = 0
+ 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1456              		.loc 1 838 3 view .LVU447
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 1457              		.loc 1 841 3 view .LVU448
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 1458              		.loc 1 841 12 is_stmt 0 view .LVU449
+ 1459 0000 D0F88830 		ldr	r3, [r0, #136]
+ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 1460              		.loc 1 841 6 view .LVU450
+ 1461 0004 202B     		cmp	r3, #32
+ 1462 0006 20D1     		bne	.L102
+ 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   HAL_StatusTypeDef status;
+ 1463              		.loc 1 837 1 view .LVU451
+ 1464 0008 10B5     		push	{r4, lr}
+ARM GAS  /tmp/ccEfj1JP.s 			page 72
+
+
+ 1465              	.LCFI17:
+ 1466              		.cfi_def_cfa_offset 8
+ 1467              		.cfi_offset 4, -8
+ 1468              		.cfi_offset 14, -4
+ 1469 000a 0446     		mov	r4, r0
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1470              		.loc 1 843 5 is_stmt 1 view .LVU452
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1471              		.loc 1 843 8 is_stmt 0 view .LVU453
+ 1472 000c F9B1     		cbz	r1, .L103
+ 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1473              		.loc 1 843 25 discriminator 1 view .LVU454
+ 1474 000e 02B3     		cbz	r2, .L104
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1475              		.loc 1 848 5 is_stmt 1 view .LVU455
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1476              		.loc 1 848 5 view .LVU456
+ 1477 0010 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ 1478 0014 012B     		cmp	r3, #1
+ 1479 0016 1ED0     		beq	.L105
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1480              		.loc 1 848 5 discriminator 2 view .LVU457
+ 1481 0018 0123     		movs	r3, #1
+ 1482 001a 80F88030 		strb	r3, [r0, #128]
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1483              		.loc 1 848 5 discriminator 2 view .LVU458
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1484              		.loc 1 851 5 discriminator 2 view .LVU459
+ 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1485              		.loc 1 851 26 is_stmt 0 discriminator 2 view .LVU460
+ 1486 001e C366     		str	r3, [r0, #108]
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1487              		.loc 1 853 5 is_stmt 1 discriminator 2 view .LVU461
+ 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1488              		.loc 1 853 15 is_stmt 0 discriminator 2 view .LVU462
+ 1489 0020 FFF7FEFF 		bl	UART_Start_Receive_IT
+ 1490              	.LVL113:
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1491              		.loc 1 856 5 is_stmt 1 discriminator 2 view .LVU463
+ 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1492              		.loc 1 856 8 is_stmt 0 discriminator 2 view .LVU464
+ 1493 0024 B0B9     		cbnz	r0, .L99
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1494              		.loc 1 858 7 is_stmt 1 view .LVU465
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1495              		.loc 1 858 16 is_stmt 0 view .LVU466
+ 1496 0026 E36E     		ldr	r3, [r4, #108]
+ 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1497              		.loc 1 858 10 view .LVU467
+ 1498 0028 012B     		cmp	r3, #1
+ 1499 002a 01D0     		beq	.L111
+ 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1500              		.loc 1 869 16 view .LVU468
+ 1501 002c 0120     		movs	r0, #1
+ 1502              	.LVL114:
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 1503              		.loc 1 873 5 is_stmt 1 view .LVU469
+ARM GAS  /tmp/ccEfj1JP.s 			page 73
+
+
+ 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 1504              		.loc 1 873 12 is_stmt 0 view .LVU470
+ 1505 002e 11E0     		b	.L99
+ 1506              	.LVL115:
+ 1507              	.L111:
+ 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 1508              		.loc 1 860 9 is_stmt 1 view .LVU471
+ 1509 0030 2368     		ldr	r3, [r4]
+ 1510 0032 1022     		movs	r2, #16
+ 1511 0034 1A62     		str	r2, [r3, #32]
+ 1512              	.L101:
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1513              		.loc 1 861 9 discriminator 1 view .LVU472
+ 1514              	.LBB32:
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1515              		.loc 1 861 9 discriminator 1 view .LVU473
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1516              		.loc 1 861 9 discriminator 1 view .LVU474
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1517              		.loc 1 861 9 discriminator 1 view .LVU475
+ 1518 0036 2268     		ldr	r2, [r4]
+ 1519              	.LVL116:
+ 1520              	.LBB33:
+ 1521              	.LBI33:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1522              		.loc 2 1151 31 discriminator 1 view .LVU476
+ 1523              	.LBB34:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1524              		.loc 2 1153 5 discriminator 1 view .LVU477
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1525              		.loc 2 1155 4 discriminator 1 view .LVU478
+ 1526              		.syntax unified
+ 1527              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1528 0038 52E8003F 		ldrex r3, [r2]
+ 1529              	@ 0 "" 2
+ 1530              	.LVL117:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1531              		.loc 2 1156 4 discriminator 1 view .LVU479
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1532              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU480
+ 1533              		.thumb
+ 1534              		.syntax unified
+ 1535              	.LBE34:
+ 1536              	.LBE33:
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1537              		.loc 1 861 9 discriminator 1 view .LVU481
+ 1538 003c 43F01003 		orr	r3, r3, #16
+ 1539              	.LVL118:
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1540              		.loc 1 861 9 is_stmt 1 discriminator 1 view .LVU482
+ 1541              	.LBB35:
+ 1542              	.LBI35:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1543              		.loc 2 1202 31 discriminator 1 view .LVU483
+ 1544              	.LBB36:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1545              		.loc 2 1204 4 discriminator 1 view .LVU484
+ARM GAS  /tmp/ccEfj1JP.s 			page 74
+
+
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1546              		.loc 2 1206 4 discriminator 1 view .LVU485
+ 1547              		.syntax unified
+ 1548              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1549 0040 42E80031 		strex r1, r3, [r2]
+ 1550              	@ 0 "" 2
+ 1551              	.LVL119:
+ 1552              		.loc 2 1207 4 discriminator 1 view .LVU486
+ 1553              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU487
+ 1554              		.thumb
+ 1555              		.syntax unified
+ 1556              	.LBE36:
+ 1557              	.LBE35:
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1558              		.loc 1 861 9 discriminator 1 view .LVU488
+ 1559 0044 0029     		cmp	r1, #0
+ 1560 0046 F6D1     		bne	.L101
+ 1561 0048 04E0     		b	.L99
+ 1562              	.LVL120:
+ 1563              	.L102:
+ 1564              	.LCFI18:
+ 1565              		.cfi_def_cfa_offset 0
+ 1566              		.cfi_restore 4
+ 1567              		.cfi_restore 14
+ 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1568              		.loc 1 861 9 discriminator 1 view .LVU489
+ 1569              	.LBE32:
+ 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 1570              		.loc 1 877 12 view .LVU490
+ 1571 004a 0220     		movs	r0, #2
+ 1572              	.LVL121:
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1573              		.loc 1 879 1 view .LVU491
+ 1574 004c 7047     		bx	lr
+ 1575              	.LVL122:
+ 1576              	.L103:
+ 1577              	.LCFI19:
+ 1578              		.cfi_def_cfa_offset 8
+ 1579              		.cfi_offset 4, -8
+ 1580              		.cfi_offset 14, -4
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1581              		.loc 1 845 14 view .LVU492
+ 1582 004e 0120     		movs	r0, #1
+ 1583              	.LVL123:
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1584              		.loc 1 845 14 view .LVU493
+ 1585 0050 00E0     		b	.L99
+ 1586              	.LVL124:
+ 1587              	.L104:
+ 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1588              		.loc 1 845 14 view .LVU494
+ 1589 0052 0120     		movs	r0, #1
+ 1590              	.LVL125:
+ 1591              	.L99:
+ 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1592              		.loc 1 879 1 view .LVU495
+ 1593 0054 10BD     		pop	{r4, pc}
+ARM GAS  /tmp/ccEfj1JP.s 			page 75
+
+
+ 1594              	.LVL126:
+ 1595              	.L105:
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1596              		.loc 1 848 5 view .LVU496
+ 1597 0056 0220     		movs	r0, #2
+ 1598              	.LVL127:
+ 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1599              		.loc 1 848 5 view .LVU497
+ 1600 0058 FCE7     		b	.L99
+ 1601              		.cfi_endproc
+ 1602              	.LFE342:
+ 1604              		.section	.text.HAL_UARTEx_ReceiveToIdle_DMA,"ax",%progbits
+ 1605              		.align	1
+ 1606              		.global	HAL_UARTEx_ReceiveToIdle_DMA
+ 1607              		.syntax unified
+ 1608              		.thumb
+ 1609              		.thumb_func
+ 1611              	HAL_UARTEx_ReceiveToIdle_DMA:
+ 1612              	.LVL128:
+ 1613              	.LFB343:
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   HAL_StatusTypeDef status;
+ 1614              		.loc 1 899 1 is_stmt 1 view -0
+ 1615              		.cfi_startproc
+ 1616              		@ args = 0, pretend = 0, frame = 0
+ 1617              		@ frame_needed = 0, uses_anonymous_args = 0
+ 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1618              		.loc 1 900 3 view .LVU499
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 1619              		.loc 1 903 3 view .LVU500
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 1620              		.loc 1 903 12 is_stmt 0 view .LVU501
+ 1621 0000 D0F88830 		ldr	r3, [r0, #136]
+ 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   {
+ 1622              		.loc 1 903 6 view .LVU502
+ 1623 0004 202B     		cmp	r3, #32
+ 1624 0006 20D1     		bne	.L116
+ 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   HAL_StatusTypeDef status;
+ 1625              		.loc 1 899 1 view .LVU503
+ 1626 0008 10B5     		push	{r4, lr}
+ 1627              	.LCFI20:
+ 1628              		.cfi_def_cfa_offset 8
+ 1629              		.cfi_offset 4, -8
+ 1630              		.cfi_offset 14, -4
+ 1631 000a 0446     		mov	r4, r0
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1632              		.loc 1 905 5 is_stmt 1 view .LVU504
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1633              		.loc 1 905 8 is_stmt 0 view .LVU505
+ 1634 000c F9B1     		cbz	r1, .L117
+ 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1635              		.loc 1 905 25 discriminator 1 view .LVU506
+ 1636 000e 02B3     		cbz	r2, .L118
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1637              		.loc 1 910 5 is_stmt 1 view .LVU507
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1638              		.loc 1 910 5 view .LVU508
+ 1639 0010 90F88030 		ldrb	r3, [r0, #128]	@ zero_extendqisi2
+ARM GAS  /tmp/ccEfj1JP.s 			page 76
+
+
+ 1640 0014 012B     		cmp	r3, #1
+ 1641 0016 1ED0     		beq	.L119
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1642              		.loc 1 910 5 discriminator 2 view .LVU509
+ 1643 0018 0123     		movs	r3, #1
+ 1644 001a 80F88030 		strb	r3, [r0, #128]
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1645              		.loc 1 910 5 discriminator 2 view .LVU510
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1646              		.loc 1 913 5 discriminator 2 view .LVU511
+ 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1647              		.loc 1 913 26 is_stmt 0 discriminator 2 view .LVU512
+ 1648 001e C366     		str	r3, [r0, #108]
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1649              		.loc 1 915 5 is_stmt 1 discriminator 2 view .LVU513
+ 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1650              		.loc 1 915 15 is_stmt 0 discriminator 2 view .LVU514
+ 1651 0020 FFF7FEFF 		bl	UART_Start_Receive_DMA
+ 1652              	.LVL129:
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1653              		.loc 1 918 5 is_stmt 1 discriminator 2 view .LVU515
+ 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     {
+ 1654              		.loc 1 918 8 is_stmt 0 discriminator 2 view .LVU516
+ 1655 0024 B0B9     		cbnz	r0, .L113
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1656              		.loc 1 920 7 is_stmt 1 view .LVU517
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1657              		.loc 1 920 16 is_stmt 0 view .LVU518
+ 1658 0026 E36E     		ldr	r3, [r4, #108]
+ 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       {
+ 1659              		.loc 1 920 10 view .LVU519
+ 1660 0028 012B     		cmp	r3, #1
+ 1661 002a 01D0     		beq	.L125
+ 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1662              		.loc 1 931 16 view .LVU520
+ 1663 002c 0120     		movs	r0, #1
+ 1664              	.LVL130:
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 1665              		.loc 1 935 5 is_stmt 1 view .LVU521
+ 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 1666              		.loc 1 935 12 is_stmt 0 view .LVU522
+ 1667 002e 11E0     		b	.L113
+ 1668              	.LVL131:
+ 1669              	.L125:
+ 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 1670              		.loc 1 922 9 is_stmt 1 view .LVU523
+ 1671 0030 2368     		ldr	r3, [r4]
+ 1672 0032 1022     		movs	r2, #16
+ 1673 0034 1A62     		str	r2, [r3, #32]
+ 1674              	.L115:
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1675              		.loc 1 923 9 discriminator 1 view .LVU524
+ 1676              	.LBB37:
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1677              		.loc 1 923 9 discriminator 1 view .LVU525
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1678              		.loc 1 923 9 discriminator 1 view .LVU526
+ARM GAS  /tmp/ccEfj1JP.s 			page 77
+
+
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1679              		.loc 1 923 9 discriminator 1 view .LVU527
+ 1680 0036 2268     		ldr	r2, [r4]
+ 1681              	.LVL132:
+ 1682              	.LBB38:
+ 1683              	.LBI38:
+1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1684              		.loc 2 1151 31 discriminator 1 view .LVU528
+ 1685              	.LBB39:
+1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1686              		.loc 2 1153 5 discriminator 1 view .LVU529
+1155:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1687              		.loc 2 1155 4 discriminator 1 view .LVU530
+ 1688              		.syntax unified
+ 1689              	@ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1690 0038 52E8003F 		ldrex r3, [r2]
+ 1691              	@ 0 "" 2
+ 1692              	.LVL133:
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1693              		.loc 2 1156 4 discriminator 1 view .LVU531
+1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 1694              		.loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU532
+ 1695              		.thumb
+ 1696              		.syntax unified
+ 1697              	.LBE39:
+ 1698              	.LBE38:
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1699              		.loc 1 923 9 discriminator 1 view .LVU533
+ 1700 003c 43F01003 		orr	r3, r3, #16
+ 1701              	.LVL134:
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1702              		.loc 1 923 9 is_stmt 1 discriminator 1 view .LVU534
+ 1703              	.LBB40:
+ 1704              	.LBI40:
+1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1705              		.loc 2 1202 31 discriminator 1 view .LVU535
+ 1706              	.LBB41:
+1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 1707              		.loc 2 1204 4 discriminator 1 view .LVU536
+1206:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1708              		.loc 2 1206 4 discriminator 1 view .LVU537
+ 1709              		.syntax unified
+ 1710              	@ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1711 0040 42E80031 		strex r1, r3, [r2]
+ 1712              	@ 0 "" 2
+ 1713              	.LVL135:
+ 1714              		.loc 2 1207 4 discriminator 1 view .LVU538
+ 1715              		.loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU539
+ 1716              		.thumb
+ 1717              		.syntax unified
+ 1718              	.LBE41:
+ 1719              	.LBE40:
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1720              		.loc 1 923 9 discriminator 1 view .LVU540
+ 1721 0044 0029     		cmp	r1, #0
+ 1722 0046 F6D1     		bne	.L115
+ 1723 0048 04E0     		b	.L113
+ARM GAS  /tmp/ccEfj1JP.s 			page 78
+
+
+ 1724              	.LVL136:
+ 1725              	.L116:
+ 1726              	.LCFI21:
+ 1727              		.cfi_def_cfa_offset 0
+ 1728              		.cfi_restore 4
+ 1729              		.cfi_restore 14
+ 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****       }
+ 1730              		.loc 1 923 9 discriminator 1 view .LVU541
+ 1731              	.LBE37:
+ 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****   }
+ 1732              		.loc 1 939 12 view .LVU542
+ 1733 004a 0220     		movs	r0, #2
+ 1734              	.LVL137:
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1735              		.loc 1 941 1 view .LVU543
+ 1736 004c 7047     		bx	lr
+ 1737              	.LVL138:
+ 1738              	.L117:
+ 1739              	.LCFI22:
+ 1740              		.cfi_def_cfa_offset 8
+ 1741              		.cfi_offset 4, -8
+ 1742              		.cfi_offset 14, -4
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1743              		.loc 1 907 14 view .LVU544
+ 1744 004e 0120     		movs	r0, #1
+ 1745              	.LVL139:
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1746              		.loc 1 907 14 view .LVU545
+ 1747 0050 00E0     		b	.L113
+ 1748              	.LVL140:
+ 1749              	.L118:
+ 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****     }
+ 1750              		.loc 1 907 14 view .LVU546
+ 1751 0052 0120     		movs	r0, #1
+ 1752              	.LVL141:
+ 1753              	.L113:
+ 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1754              		.loc 1 941 1 view .LVU547
+ 1755 0054 10BD     		pop	{r4, pc}
+ 1756              	.LVL142:
+ 1757              	.L119:
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1758              		.loc 1 910 5 view .LVU548
+ 1759 0056 0220     		movs	r0, #2
+ 1760              	.LVL143:
+ 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 
+ 1761              		.loc 1 910 5 view .LVU549
+ 1762 0058 FCE7     		b	.L113
+ 1763              		.cfi_endproc
+ 1764              	.LFE343:
+ 1766              		.section	.rodata.denominator.0,"a"
+ 1767              		.align	2
+ 1770              	denominator.0:
+ 1771 0000 08040204 		.ascii	"\010\004\002\004\010\001\001\001"
+ 1771      08010101 
+ 1772              		.section	.rodata.numerator.1,"a"
+ 1773              		.align	2
+ARM GAS  /tmp/ccEfj1JP.s 			page 79
+
+
+ 1776              	numerator.1:
+ 1777 0000 01010103 		.ascii	"\001\001\001\003\007\001\000\000"
+ 1777      07010000 
+ 1778              		.text
+ 1779              	.Letext0:
+ 1780              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 1781              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 1782              		.file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 1783              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 1784              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 1785              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h"
+ 1786              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h"
+ 1787              		.file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ARM GAS  /tmp/ccEfj1JP.s 			page 80
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_hal_uart_ex.c
+     /tmp/ccEfj1JP.s:21     .text.UARTEx_Wakeup_AddressConfig:00000000 $t
+     /tmp/ccEfj1JP.s:26     .text.UARTEx_Wakeup_AddressConfig:00000000 UARTEx_Wakeup_AddressConfig
+     /tmp/ccEfj1JP.s:65     .text.UARTEx_SetNbDataToProcess:00000000 $t
+     /tmp/ccEfj1JP.s:70     .text.UARTEx_SetNbDataToProcess:00000000 UARTEx_SetNbDataToProcess
+     /tmp/ccEfj1JP.s:156    .text.UARTEx_SetNbDataToProcess:00000044 $d
+     /tmp/ccEfj1JP.s:1776   .rodata.numerator.1:00000000 numerator.1
+     /tmp/ccEfj1JP.s:1770   .rodata.denominator.0:00000000 denominator.0
+     /tmp/ccEfj1JP.s:162    .text.HAL_RS485Ex_Init:00000000 $t
+     /tmp/ccEfj1JP.s:168    .text.HAL_RS485Ex_Init:00000000 HAL_RS485Ex_Init
+     /tmp/ccEfj1JP.s:306    .text.HAL_UARTEx_WakeupCallback:00000000 $t
+     /tmp/ccEfj1JP.s:312    .text.HAL_UARTEx_WakeupCallback:00000000 HAL_UARTEx_WakeupCallback
+     /tmp/ccEfj1JP.s:327    .text.HAL_UARTEx_RxFifoFullCallback:00000000 $t
+     /tmp/ccEfj1JP.s:333    .text.HAL_UARTEx_RxFifoFullCallback:00000000 HAL_UARTEx_RxFifoFullCallback
+     /tmp/ccEfj1JP.s:348    .text.HAL_UARTEx_TxFifoEmptyCallback:00000000 $t
+     /tmp/ccEfj1JP.s:354    .text.HAL_UARTEx_TxFifoEmptyCallback:00000000 HAL_UARTEx_TxFifoEmptyCallback
+     /tmp/ccEfj1JP.s:369    .text.HAL_MultiProcessorEx_AddressLength_Set:00000000 $t
+     /tmp/ccEfj1JP.s:375    .text.HAL_MultiProcessorEx_AddressLength_Set:00000000 HAL_MultiProcessorEx_AddressLength_Set
+     /tmp/ccEfj1JP.s:439    .text.HAL_UARTEx_StopModeWakeUpSourceConfig:00000000 $t
+     /tmp/ccEfj1JP.s:445    .text.HAL_UARTEx_StopModeWakeUpSourceConfig:00000000 HAL_UARTEx_StopModeWakeUpSourceConfig
+     /tmp/ccEfj1JP.s:571    .text.HAL_UARTEx_EnableStopMode:00000000 $t
+     /tmp/ccEfj1JP.s:577    .text.HAL_UARTEx_EnableStopMode:00000000 HAL_UARTEx_EnableStopMode
+     /tmp/ccEfj1JP.s:670    .text.HAL_UARTEx_DisableStopMode:00000000 $t
+     /tmp/ccEfj1JP.s:676    .text.HAL_UARTEx_DisableStopMode:00000000 HAL_UARTEx_DisableStopMode
+     /tmp/ccEfj1JP.s:768    .text.HAL_UARTEx_EnableFifoMode:00000000 $t
+     /tmp/ccEfj1JP.s:774    .text.HAL_UARTEx_EnableFifoMode:00000000 HAL_UARTEx_EnableFifoMode
+     /tmp/ccEfj1JP.s:853    .text.HAL_UARTEx_DisableFifoMode:00000000 $t
+     /tmp/ccEfj1JP.s:859    .text.HAL_UARTEx_DisableFifoMode:00000000 HAL_UARTEx_DisableFifoMode
+     /tmp/ccEfj1JP.s:930    .text.HAL_UARTEx_SetTxFifoThreshold:00000000 $t
+     /tmp/ccEfj1JP.s:936    .text.HAL_UARTEx_SetTxFifoThreshold:00000000 HAL_UARTEx_SetTxFifoThreshold
+     /tmp/ccEfj1JP.s:1017   .text.HAL_UARTEx_SetRxFifoThreshold:00000000 $t
+     /tmp/ccEfj1JP.s:1023   .text.HAL_UARTEx_SetRxFifoThreshold:00000000 HAL_UARTEx_SetRxFifoThreshold
+     /tmp/ccEfj1JP.s:1104   .text.HAL_UARTEx_ReceiveToIdle:00000000 $t
+     /tmp/ccEfj1JP.s:1110   .text.HAL_UARTEx_ReceiveToIdle:00000000 HAL_UARTEx_ReceiveToIdle
+     /tmp/ccEfj1JP.s:1443   .text.HAL_UARTEx_ReceiveToIdle_IT:00000000 $t
+     /tmp/ccEfj1JP.s:1449   .text.HAL_UARTEx_ReceiveToIdle_IT:00000000 HAL_UARTEx_ReceiveToIdle_IT
+     /tmp/ccEfj1JP.s:1605   .text.HAL_UARTEx_ReceiveToIdle_DMA:00000000 $t
+     /tmp/ccEfj1JP.s:1611   .text.HAL_UARTEx_ReceiveToIdle_DMA:00000000 HAL_UARTEx_ReceiveToIdle_DMA
+     /tmp/ccEfj1JP.s:1767   .rodata.denominator.0:00000000 $d
+     /tmp/ccEfj1JP.s:1773   .rodata.numerator.1:00000000 $d
+
+UNDEFINED SYMBOLS
+UART_SetConfig
+UART_CheckIdleState
+HAL_UART_MspInit
+UART_AdvFeatureConfig
+HAL_GetTick
+UART_WaitOnFlagUntilTimeout
+UART_Start_Receive_IT
+UART_Start_Receive_DMA
diff --git a/squeow_sw/build/stm32g4xx_hal_uart_ex.o b/squeow_sw/build/stm32g4xx_hal_uart_ex.o
new file mode 100644
index 0000000000000000000000000000000000000000..3e1a4e17ba11317017baa4f49a3a5d149e573996
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diff --git a/squeow_sw/build/stm32g4xx_it.d b/squeow_sw/build/stm32g4xx_it.d
new file mode 100644
index 0000000..539acf4
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_it.d
@@ -0,0 +1,76 @@
+build/stm32g4xx_it.o: Src/stm32g4xx_it.c Inc/main.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h \
+ Inc/stm32g4xx_it.h
+Inc/main.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
+Inc/stm32g4xx_it.h:
diff --git a/squeow_sw/build/stm32g4xx_it.lst b/squeow_sw/build/stm32g4xx_it.lst
new file mode 100644
index 0000000..1c19007
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_it.lst
@@ -0,0 +1,563 @@
+ARM GAS  /tmp/cciBLZ6U.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_it.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Src/stm32g4xx_it.c"
+  20              		.section	.text.NMI_Handler,"ax",%progbits
+  21              		.align	1
+  22              		.global	NMI_Handler
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	NMI_Handler:
+  28              	.LFB329:
+   1:Src/stm32g4xx_it.c **** /* USER CODE BEGIN Header */
+   2:Src/stm32g4xx_it.c **** /**
+   3:Src/stm32g4xx_it.c ****   ******************************************************************************
+   4:Src/stm32g4xx_it.c ****   * @file    stm32g4xx_it.c
+   5:Src/stm32g4xx_it.c ****   * @brief   Interrupt Service Routines.
+   6:Src/stm32g4xx_it.c ****   ******************************************************************************
+   7:Src/stm32g4xx_it.c ****   * @attention
+   8:Src/stm32g4xx_it.c ****   *
+   9:Src/stm32g4xx_it.c ****   * Copyright (c) 2022 STMicroelectronics.
+  10:Src/stm32g4xx_it.c ****   * All rights reserved.
+  11:Src/stm32g4xx_it.c ****   *
+  12:Src/stm32g4xx_it.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Src/stm32g4xx_it.c ****   * in the root directory of this software component.
+  14:Src/stm32g4xx_it.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Src/stm32g4xx_it.c ****   *
+  16:Src/stm32g4xx_it.c ****   ******************************************************************************
+  17:Src/stm32g4xx_it.c ****   */
+  18:Src/stm32g4xx_it.c **** /* USER CODE END Header */
+  19:Src/stm32g4xx_it.c **** 
+  20:Src/stm32g4xx_it.c **** /* Includes ------------------------------------------------------------------*/
+  21:Src/stm32g4xx_it.c **** #include "main.h"
+  22:Src/stm32g4xx_it.c **** #include "stm32g4xx_it.h"
+  23:Src/stm32g4xx_it.c **** /* Private includes ----------------------------------------------------------*/
+  24:Src/stm32g4xx_it.c **** /* USER CODE BEGIN Includes */
+  25:Src/stm32g4xx_it.c **** /* USER CODE END Includes */
+  26:Src/stm32g4xx_it.c **** 
+  27:Src/stm32g4xx_it.c **** /* Private typedef -----------------------------------------------------------*/
+  28:Src/stm32g4xx_it.c **** /* USER CODE BEGIN TD */
+  29:Src/stm32g4xx_it.c **** 
+  30:Src/stm32g4xx_it.c **** /* USER CODE END TD */
+ARM GAS  /tmp/cciBLZ6U.s 			page 2
+
+
+  31:Src/stm32g4xx_it.c **** 
+  32:Src/stm32g4xx_it.c **** /* Private define ------------------------------------------------------------*/
+  33:Src/stm32g4xx_it.c **** /* USER CODE BEGIN PD */
+  34:Src/stm32g4xx_it.c **** 
+  35:Src/stm32g4xx_it.c **** /* USER CODE END PD */
+  36:Src/stm32g4xx_it.c **** 
+  37:Src/stm32g4xx_it.c **** /* Private macro -------------------------------------------------------------*/
+  38:Src/stm32g4xx_it.c **** /* USER CODE BEGIN PM */
+  39:Src/stm32g4xx_it.c **** 
+  40:Src/stm32g4xx_it.c **** /* USER CODE END PM */
+  41:Src/stm32g4xx_it.c **** 
+  42:Src/stm32g4xx_it.c **** /* Private variables ---------------------------------------------------------*/
+  43:Src/stm32g4xx_it.c **** /* USER CODE BEGIN PV */
+  44:Src/stm32g4xx_it.c **** 
+  45:Src/stm32g4xx_it.c **** /* USER CODE END PV */
+  46:Src/stm32g4xx_it.c **** 
+  47:Src/stm32g4xx_it.c **** /* Private function prototypes -----------------------------------------------*/
+  48:Src/stm32g4xx_it.c **** /* USER CODE BEGIN PFP */
+  49:Src/stm32g4xx_it.c **** 
+  50:Src/stm32g4xx_it.c **** /* USER CODE END PFP */
+  51:Src/stm32g4xx_it.c **** 
+  52:Src/stm32g4xx_it.c **** /* Private user code ---------------------------------------------------------*/
+  53:Src/stm32g4xx_it.c **** /* USER CODE BEGIN 0 */
+  54:Src/stm32g4xx_it.c **** 
+  55:Src/stm32g4xx_it.c **** /* USER CODE END 0 */
+  56:Src/stm32g4xx_it.c **** 
+  57:Src/stm32g4xx_it.c **** /* External variables --------------------------------------------------------*/
+  58:Src/stm32g4xx_it.c **** extern PCD_HandleTypeDef hpcd_USB_FS;
+  59:Src/stm32g4xx_it.c **** extern TIM_HandleTypeDef htim3;
+  60:Src/stm32g4xx_it.c **** /* USER CODE BEGIN EV */
+  61:Src/stm32g4xx_it.c **** 
+  62:Src/stm32g4xx_it.c **** /* USER CODE END EV */
+  63:Src/stm32g4xx_it.c **** 
+  64:Src/stm32g4xx_it.c **** /******************************************************************************/
+  65:Src/stm32g4xx_it.c **** /*           Cortex-M4 Processor Interruption and Exception Handlers          */
+  66:Src/stm32g4xx_it.c **** /******************************************************************************/
+  67:Src/stm32g4xx_it.c **** /**
+  68:Src/stm32g4xx_it.c ****   * @brief This function handles Non maskable interrupt.
+  69:Src/stm32g4xx_it.c ****   */
+  70:Src/stm32g4xx_it.c **** void NMI_Handler(void)
+  71:Src/stm32g4xx_it.c **** {
+  29              		.loc 1 71 1 view -0
+  30              		.cfi_startproc
+  31              		@ Volatile: function does not return.
+  32              		@ args = 0, pretend = 0, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		@ link register save eliminated.
+  35              	.L2:
+  72:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+  73:Src/stm32g4xx_it.c **** 
+  74:Src/stm32g4xx_it.c ****   /* USER CODE END NonMaskableInt_IRQn 0 */
+  75:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+  76:Src/stm32g4xx_it.c ****   while (1)
+  36              		.loc 1 76 3 discriminator 1 view .LVU1
+  77:Src/stm32g4xx_it.c ****   {
+  78:Src/stm32g4xx_it.c ****   }
+  37              		.loc 1 78 3 discriminator 1 view .LVU2
+ARM GAS  /tmp/cciBLZ6U.s 			page 3
+
+
+  76:Src/stm32g4xx_it.c ****   {
+  38              		.loc 1 76 9 discriminator 1 view .LVU3
+  39 0000 FEE7     		b	.L2
+  40              		.cfi_endproc
+  41              	.LFE329:
+  43              		.section	.text.HardFault_Handler,"ax",%progbits
+  44              		.align	1
+  45              		.global	HardFault_Handler
+  46              		.syntax unified
+  47              		.thumb
+  48              		.thumb_func
+  50              	HardFault_Handler:
+  51              	.LFB330:
+  79:Src/stm32g4xx_it.c ****   /* USER CODE END NonMaskableInt_IRQn 1 */
+  80:Src/stm32g4xx_it.c **** }
+  81:Src/stm32g4xx_it.c **** 
+  82:Src/stm32g4xx_it.c **** /**
+  83:Src/stm32g4xx_it.c ****   * @brief This function handles Hard fault interrupt.
+  84:Src/stm32g4xx_it.c ****   */
+  85:Src/stm32g4xx_it.c **** void HardFault_Handler(void)
+  86:Src/stm32g4xx_it.c **** {
+  52              		.loc 1 86 1 view -0
+  53              		.cfi_startproc
+  54              		@ Volatile: function does not return.
+  55              		@ args = 0, pretend = 0, frame = 0
+  56              		@ frame_needed = 0, uses_anonymous_args = 0
+  57              		@ link register save eliminated.
+  58              	.L4:
+  87:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN HardFault_IRQn 0 */
+  88:Src/stm32g4xx_it.c **** 
+  89:Src/stm32g4xx_it.c ****   /* USER CODE END HardFault_IRQn 0 */
+  90:Src/stm32g4xx_it.c ****   while (1)
+  59              		.loc 1 90 3 discriminator 1 view .LVU5
+  91:Src/stm32g4xx_it.c ****   {
+  92:Src/stm32g4xx_it.c ****     /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+  93:Src/stm32g4xx_it.c ****     /* USER CODE END W1_HardFault_IRQn 0 */
+  94:Src/stm32g4xx_it.c ****   }
+  60              		.loc 1 94 3 discriminator 1 view .LVU6
+  90:Src/stm32g4xx_it.c ****   {
+  61              		.loc 1 90 9 discriminator 1 view .LVU7
+  62 0000 FEE7     		b	.L4
+  63              		.cfi_endproc
+  64              	.LFE330:
+  66              		.section	.text.MemManage_Handler,"ax",%progbits
+  67              		.align	1
+  68              		.global	MemManage_Handler
+  69              		.syntax unified
+  70              		.thumb
+  71              		.thumb_func
+  73              	MemManage_Handler:
+  74              	.LFB331:
+  95:Src/stm32g4xx_it.c **** }
+  96:Src/stm32g4xx_it.c **** 
+  97:Src/stm32g4xx_it.c **** /**
+  98:Src/stm32g4xx_it.c ****   * @brief This function handles Memory management fault.
+  99:Src/stm32g4xx_it.c ****   */
+ 100:Src/stm32g4xx_it.c **** void MemManage_Handler(void)
+ARM GAS  /tmp/cciBLZ6U.s 			page 4
+
+
+ 101:Src/stm32g4xx_it.c **** {
+  75              		.loc 1 101 1 view -0
+  76              		.cfi_startproc
+  77              		@ Volatile: function does not return.
+  78              		@ args = 0, pretend = 0, frame = 0
+  79              		@ frame_needed = 0, uses_anonymous_args = 0
+  80              		@ link register save eliminated.
+  81              	.L6:
+ 102:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+ 103:Src/stm32g4xx_it.c **** 
+ 104:Src/stm32g4xx_it.c ****   /* USER CODE END MemoryManagement_IRQn 0 */
+ 105:Src/stm32g4xx_it.c ****   while (1)
+  82              		.loc 1 105 3 discriminator 1 view .LVU9
+ 106:Src/stm32g4xx_it.c ****   {
+ 107:Src/stm32g4xx_it.c ****     /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+ 108:Src/stm32g4xx_it.c ****     /* USER CODE END W1_MemoryManagement_IRQn 0 */
+ 109:Src/stm32g4xx_it.c ****   }
+  83              		.loc 1 109 3 discriminator 1 view .LVU10
+ 105:Src/stm32g4xx_it.c ****   {
+  84              		.loc 1 105 9 discriminator 1 view .LVU11
+  85 0000 FEE7     		b	.L6
+  86              		.cfi_endproc
+  87              	.LFE331:
+  89              		.section	.text.BusFault_Handler,"ax",%progbits
+  90              		.align	1
+  91              		.global	BusFault_Handler
+  92              		.syntax unified
+  93              		.thumb
+  94              		.thumb_func
+  96              	BusFault_Handler:
+  97              	.LFB332:
+ 110:Src/stm32g4xx_it.c **** }
+ 111:Src/stm32g4xx_it.c **** 
+ 112:Src/stm32g4xx_it.c **** /**
+ 113:Src/stm32g4xx_it.c ****   * @brief This function handles Prefetch fault, memory access fault.
+ 114:Src/stm32g4xx_it.c ****   */
+ 115:Src/stm32g4xx_it.c **** void BusFault_Handler(void)
+ 116:Src/stm32g4xx_it.c **** {
+  98              		.loc 1 116 1 view -0
+  99              		.cfi_startproc
+ 100              		@ Volatile: function does not return.
+ 101              		@ args = 0, pretend = 0, frame = 0
+ 102              		@ frame_needed = 0, uses_anonymous_args = 0
+ 103              		@ link register save eliminated.
+ 104              	.L8:
+ 117:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN BusFault_IRQn 0 */
+ 118:Src/stm32g4xx_it.c **** 
+ 119:Src/stm32g4xx_it.c ****   /* USER CODE END BusFault_IRQn 0 */
+ 120:Src/stm32g4xx_it.c ****   while (1)
+ 105              		.loc 1 120 3 discriminator 1 view .LVU13
+ 121:Src/stm32g4xx_it.c ****   {
+ 122:Src/stm32g4xx_it.c ****     /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+ 123:Src/stm32g4xx_it.c ****     /* USER CODE END W1_BusFault_IRQn 0 */
+ 124:Src/stm32g4xx_it.c ****   }
+ 106              		.loc 1 124 3 discriminator 1 view .LVU14
+ 120:Src/stm32g4xx_it.c ****   {
+ 107              		.loc 1 120 9 discriminator 1 view .LVU15
+ARM GAS  /tmp/cciBLZ6U.s 			page 5
+
+
+ 108 0000 FEE7     		b	.L8
+ 109              		.cfi_endproc
+ 110              	.LFE332:
+ 112              		.section	.text.UsageFault_Handler,"ax",%progbits
+ 113              		.align	1
+ 114              		.global	UsageFault_Handler
+ 115              		.syntax unified
+ 116              		.thumb
+ 117              		.thumb_func
+ 119              	UsageFault_Handler:
+ 120              	.LFB333:
+ 125:Src/stm32g4xx_it.c **** }
+ 126:Src/stm32g4xx_it.c **** 
+ 127:Src/stm32g4xx_it.c **** /**
+ 128:Src/stm32g4xx_it.c ****   * @brief This function handles Undefined instruction or illegal state.
+ 129:Src/stm32g4xx_it.c ****   */
+ 130:Src/stm32g4xx_it.c **** void UsageFault_Handler(void)
+ 131:Src/stm32g4xx_it.c **** {
+ 121              		.loc 1 131 1 view -0
+ 122              		.cfi_startproc
+ 123              		@ Volatile: function does not return.
+ 124              		@ args = 0, pretend = 0, frame = 0
+ 125              		@ frame_needed = 0, uses_anonymous_args = 0
+ 126              		@ link register save eliminated.
+ 127              	.L10:
+ 132:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN UsageFault_IRQn 0 */
+ 133:Src/stm32g4xx_it.c **** 
+ 134:Src/stm32g4xx_it.c ****   /* USER CODE END UsageFault_IRQn 0 */
+ 135:Src/stm32g4xx_it.c ****   while (1)
+ 128              		.loc 1 135 3 discriminator 1 view .LVU17
+ 136:Src/stm32g4xx_it.c ****   {
+ 137:Src/stm32g4xx_it.c ****     /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+ 138:Src/stm32g4xx_it.c ****     /* USER CODE END W1_UsageFault_IRQn 0 */
+ 139:Src/stm32g4xx_it.c ****   }
+ 129              		.loc 1 139 3 discriminator 1 view .LVU18
+ 135:Src/stm32g4xx_it.c ****   {
+ 130              		.loc 1 135 9 discriminator 1 view .LVU19
+ 131 0000 FEE7     		b	.L10
+ 132              		.cfi_endproc
+ 133              	.LFE333:
+ 135              		.section	.text.SVC_Handler,"ax",%progbits
+ 136              		.align	1
+ 137              		.global	SVC_Handler
+ 138              		.syntax unified
+ 139              		.thumb
+ 140              		.thumb_func
+ 142              	SVC_Handler:
+ 143              	.LFB334:
+ 140:Src/stm32g4xx_it.c **** }
+ 141:Src/stm32g4xx_it.c **** 
+ 142:Src/stm32g4xx_it.c **** /**
+ 143:Src/stm32g4xx_it.c ****   * @brief This function handles System service call via SWI instruction.
+ 144:Src/stm32g4xx_it.c ****   */
+ 145:Src/stm32g4xx_it.c **** void SVC_Handler(void)
+ 146:Src/stm32g4xx_it.c **** {
+ 144              		.loc 1 146 1 view -0
+ 145              		.cfi_startproc
+ARM GAS  /tmp/cciBLZ6U.s 			page 6
+
+
+ 146              		@ args = 0, pretend = 0, frame = 0
+ 147              		@ frame_needed = 0, uses_anonymous_args = 0
+ 148              		@ link register save eliminated.
+ 147:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN SVCall_IRQn 0 */
+ 148:Src/stm32g4xx_it.c **** 
+ 149:Src/stm32g4xx_it.c ****   /* USER CODE END SVCall_IRQn 0 */
+ 150:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN SVCall_IRQn 1 */
+ 151:Src/stm32g4xx_it.c **** 
+ 152:Src/stm32g4xx_it.c ****   /* USER CODE END SVCall_IRQn 1 */
+ 153:Src/stm32g4xx_it.c **** }
+ 149              		.loc 1 153 1 view .LVU21
+ 150 0000 7047     		bx	lr
+ 151              		.cfi_endproc
+ 152              	.LFE334:
+ 154              		.section	.text.DebugMon_Handler,"ax",%progbits
+ 155              		.align	1
+ 156              		.global	DebugMon_Handler
+ 157              		.syntax unified
+ 158              		.thumb
+ 159              		.thumb_func
+ 161              	DebugMon_Handler:
+ 162              	.LFB335:
+ 154:Src/stm32g4xx_it.c **** 
+ 155:Src/stm32g4xx_it.c **** /**
+ 156:Src/stm32g4xx_it.c ****   * @brief This function handles Debug monitor.
+ 157:Src/stm32g4xx_it.c ****   */
+ 158:Src/stm32g4xx_it.c **** void DebugMon_Handler(void)
+ 159:Src/stm32g4xx_it.c **** {
+ 163              		.loc 1 159 1 view -0
+ 164              		.cfi_startproc
+ 165              		@ args = 0, pretend = 0, frame = 0
+ 166              		@ frame_needed = 0, uses_anonymous_args = 0
+ 167              		@ link register save eliminated.
+ 160:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+ 161:Src/stm32g4xx_it.c **** 
+ 162:Src/stm32g4xx_it.c ****   /* USER CODE END DebugMonitor_IRQn 0 */
+ 163:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+ 164:Src/stm32g4xx_it.c **** 
+ 165:Src/stm32g4xx_it.c ****   /* USER CODE END DebugMonitor_IRQn 1 */
+ 166:Src/stm32g4xx_it.c **** }
+ 168              		.loc 1 166 1 view .LVU23
+ 169 0000 7047     		bx	lr
+ 170              		.cfi_endproc
+ 171              	.LFE335:
+ 173              		.section	.text.PendSV_Handler,"ax",%progbits
+ 174              		.align	1
+ 175              		.global	PendSV_Handler
+ 176              		.syntax unified
+ 177              		.thumb
+ 178              		.thumb_func
+ 180              	PendSV_Handler:
+ 181              	.LFB336:
+ 167:Src/stm32g4xx_it.c **** 
+ 168:Src/stm32g4xx_it.c **** /**
+ 169:Src/stm32g4xx_it.c ****   * @brief This function handles Pendable request for system service.
+ 170:Src/stm32g4xx_it.c ****   */
+ 171:Src/stm32g4xx_it.c **** void PendSV_Handler(void)
+ARM GAS  /tmp/cciBLZ6U.s 			page 7
+
+
+ 172:Src/stm32g4xx_it.c **** {
+ 182              		.loc 1 172 1 view -0
+ 183              		.cfi_startproc
+ 184              		@ args = 0, pretend = 0, frame = 0
+ 185              		@ frame_needed = 0, uses_anonymous_args = 0
+ 186              		@ link register save eliminated.
+ 173:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN PendSV_IRQn 0 */
+ 174:Src/stm32g4xx_it.c **** 
+ 175:Src/stm32g4xx_it.c ****   /* USER CODE END PendSV_IRQn 0 */
+ 176:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN PendSV_IRQn 1 */
+ 177:Src/stm32g4xx_it.c **** 
+ 178:Src/stm32g4xx_it.c ****   /* USER CODE END PendSV_IRQn 1 */
+ 179:Src/stm32g4xx_it.c **** }
+ 187              		.loc 1 179 1 view .LVU25
+ 188 0000 7047     		bx	lr
+ 189              		.cfi_endproc
+ 190              	.LFE336:
+ 192              		.section	.text.SysTick_Handler,"ax",%progbits
+ 193              		.align	1
+ 194              		.global	SysTick_Handler
+ 195              		.syntax unified
+ 196              		.thumb
+ 197              		.thumb_func
+ 199              	SysTick_Handler:
+ 200              	.LFB337:
+ 180:Src/stm32g4xx_it.c **** 
+ 181:Src/stm32g4xx_it.c **** /**
+ 182:Src/stm32g4xx_it.c ****   * @brief This function handles System tick timer.
+ 183:Src/stm32g4xx_it.c ****   */
+ 184:Src/stm32g4xx_it.c **** void SysTick_Handler(void)
+ 185:Src/stm32g4xx_it.c **** {
+ 201              		.loc 1 185 1 view -0
+ 202              		.cfi_startproc
+ 203              		@ args = 0, pretend = 0, frame = 0
+ 204              		@ frame_needed = 0, uses_anonymous_args = 0
+ 205 0000 08B5     		push	{r3, lr}
+ 206              	.LCFI0:
+ 207              		.cfi_def_cfa_offset 8
+ 208              		.cfi_offset 3, -8
+ 209              		.cfi_offset 14, -4
+ 186:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN SysTick_IRQn 0 */
+ 187:Src/stm32g4xx_it.c **** 
+ 188:Src/stm32g4xx_it.c ****   /* USER CODE END SysTick_IRQn 0 */
+ 189:Src/stm32g4xx_it.c ****   HAL_IncTick();
+ 210              		.loc 1 189 3 view .LVU27
+ 211 0002 FFF7FEFF 		bl	HAL_IncTick
+ 212              	.LVL0:
+ 190:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN SysTick_IRQn 1 */
+ 191:Src/stm32g4xx_it.c **** 
+ 192:Src/stm32g4xx_it.c ****   /* USER CODE END SysTick_IRQn 1 */
+ 193:Src/stm32g4xx_it.c **** }
+ 213              		.loc 1 193 1 is_stmt 0 view .LVU28
+ 214 0006 08BD     		pop	{r3, pc}
+ 215              		.cfi_endproc
+ 216              	.LFE337:
+ 218              		.section	.text.USB_LP_IRQHandler,"ax",%progbits
+ 219              		.align	1
+ARM GAS  /tmp/cciBLZ6U.s 			page 8
+
+
+ 220              		.global	USB_LP_IRQHandler
+ 221              		.syntax unified
+ 222              		.thumb
+ 223              		.thumb_func
+ 225              	USB_LP_IRQHandler:
+ 226              	.LFB338:
+ 194:Src/stm32g4xx_it.c **** 
+ 195:Src/stm32g4xx_it.c **** /******************************************************************************/
+ 196:Src/stm32g4xx_it.c **** /* STM32G4xx Peripheral Interrupt Handlers                                    */
+ 197:Src/stm32g4xx_it.c **** /* Add here the Interrupt Handlers for the used peripherals.                  */
+ 198:Src/stm32g4xx_it.c **** /* For the available peripheral interrupt handler names,                      */
+ 199:Src/stm32g4xx_it.c **** /* please refer to the startup file (startup_stm32g4xx.s).                    */
+ 200:Src/stm32g4xx_it.c **** /******************************************************************************/
+ 201:Src/stm32g4xx_it.c **** 
+ 202:Src/stm32g4xx_it.c **** /**
+ 203:Src/stm32g4xx_it.c ****   * @brief This function handles USB low priority interrupt remap.
+ 204:Src/stm32g4xx_it.c ****   */
+ 205:Src/stm32g4xx_it.c **** void USB_LP_IRQHandler(void)
+ 206:Src/stm32g4xx_it.c **** {
+ 227              		.loc 1 206 1 is_stmt 1 view -0
+ 228              		.cfi_startproc
+ 229              		@ args = 0, pretend = 0, frame = 0
+ 230              		@ frame_needed = 0, uses_anonymous_args = 0
+ 231 0000 08B5     		push	{r3, lr}
+ 232              	.LCFI1:
+ 233              		.cfi_def_cfa_offset 8
+ 234              		.cfi_offset 3, -8
+ 235              		.cfi_offset 14, -4
+ 207:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN USB_LP_IRQn 0 */
+ 208:Src/stm32g4xx_it.c **** 
+ 209:Src/stm32g4xx_it.c ****   /* USER CODE END USB_LP_IRQn 0 */
+ 210:Src/stm32g4xx_it.c ****   HAL_PCD_IRQHandler(&hpcd_USB_FS);
+ 236              		.loc 1 210 3 view .LVU30
+ 237 0002 0248     		ldr	r0, .L18
+ 238 0004 FFF7FEFF 		bl	HAL_PCD_IRQHandler
+ 239              	.LVL1:
+ 211:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN USB_LP_IRQn 1 */
+ 212:Src/stm32g4xx_it.c **** 
+ 213:Src/stm32g4xx_it.c ****   /* USER CODE END USB_LP_IRQn 1 */
+ 214:Src/stm32g4xx_it.c **** }
+ 240              		.loc 1 214 1 is_stmt 0 view .LVU31
+ 241 0008 08BD     		pop	{r3, pc}
+ 242              	.L19:
+ 243 000a 00BF     		.align	2
+ 244              	.L18:
+ 245 000c 00000000 		.word	hpcd_USB_FS
+ 246              		.cfi_endproc
+ 247              	.LFE338:
+ 249              		.section	.text.TIM3_IRQHandler,"ax",%progbits
+ 250              		.align	1
+ 251              		.global	TIM3_IRQHandler
+ 252              		.syntax unified
+ 253              		.thumb
+ 254              		.thumb_func
+ 256              	TIM3_IRQHandler:
+ 257              	.LFB339:
+ 215:Src/stm32g4xx_it.c **** 
+ARM GAS  /tmp/cciBLZ6U.s 			page 9
+
+
+ 216:Src/stm32g4xx_it.c **** /**
+ 217:Src/stm32g4xx_it.c ****   * @brief This function handles TIM3 global interrupt.
+ 218:Src/stm32g4xx_it.c ****   */
+ 219:Src/stm32g4xx_it.c **** void TIM3_IRQHandler(void)
+ 220:Src/stm32g4xx_it.c **** {
+ 258              		.loc 1 220 1 is_stmt 1 view -0
+ 259              		.cfi_startproc
+ 260              		@ args = 0, pretend = 0, frame = 0
+ 261              		@ frame_needed = 0, uses_anonymous_args = 0
+ 262 0000 08B5     		push	{r3, lr}
+ 263              	.LCFI2:
+ 264              		.cfi_def_cfa_offset 8
+ 265              		.cfi_offset 3, -8
+ 266              		.cfi_offset 14, -4
+ 221:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN TIM3_IRQn 0 */
+ 222:Src/stm32g4xx_it.c **** 
+ 223:Src/stm32g4xx_it.c ****   /* USER CODE END TIM3_IRQn 0 */
+ 224:Src/stm32g4xx_it.c ****   HAL_TIM_IRQHandler(&htim3);
+ 267              		.loc 1 224 3 view .LVU33
+ 268 0002 0248     		ldr	r0, .L22
+ 269 0004 FFF7FEFF 		bl	HAL_TIM_IRQHandler
+ 270              	.LVL2:
+ 225:Src/stm32g4xx_it.c ****   /* USER CODE BEGIN TIM3_IRQn 1 */
+ 226:Src/stm32g4xx_it.c **** 
+ 227:Src/stm32g4xx_it.c ****   /* USER CODE END TIM3_IRQn 1 */
+ 228:Src/stm32g4xx_it.c **** }
+ 271              		.loc 1 228 1 is_stmt 0 view .LVU34
+ 272 0008 08BD     		pop	{r3, pc}
+ 273              	.L23:
+ 274 000a 00BF     		.align	2
+ 275              	.L22:
+ 276 000c 00000000 		.word	htim3
+ 277              		.cfi_endproc
+ 278              	.LFE339:
+ 280              		.text
+ 281              	.Letext0:
+ 282              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 283              		.file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 284              		.file 4 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 285              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
+ 286              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h"
+ 287              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h"
+ 288              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"
+ 289              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ARM GAS  /tmp/cciBLZ6U.s 			page 10
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_it.c
+     /tmp/cciBLZ6U.s:21     .text.NMI_Handler:00000000 $t
+     /tmp/cciBLZ6U.s:27     .text.NMI_Handler:00000000 NMI_Handler
+     /tmp/cciBLZ6U.s:44     .text.HardFault_Handler:00000000 $t
+     /tmp/cciBLZ6U.s:50     .text.HardFault_Handler:00000000 HardFault_Handler
+     /tmp/cciBLZ6U.s:67     .text.MemManage_Handler:00000000 $t
+     /tmp/cciBLZ6U.s:73     .text.MemManage_Handler:00000000 MemManage_Handler
+     /tmp/cciBLZ6U.s:90     .text.BusFault_Handler:00000000 $t
+     /tmp/cciBLZ6U.s:96     .text.BusFault_Handler:00000000 BusFault_Handler
+     /tmp/cciBLZ6U.s:113    .text.UsageFault_Handler:00000000 $t
+     /tmp/cciBLZ6U.s:119    .text.UsageFault_Handler:00000000 UsageFault_Handler
+     /tmp/cciBLZ6U.s:136    .text.SVC_Handler:00000000 $t
+     /tmp/cciBLZ6U.s:142    .text.SVC_Handler:00000000 SVC_Handler
+     /tmp/cciBLZ6U.s:155    .text.DebugMon_Handler:00000000 $t
+     /tmp/cciBLZ6U.s:161    .text.DebugMon_Handler:00000000 DebugMon_Handler
+     /tmp/cciBLZ6U.s:174    .text.PendSV_Handler:00000000 $t
+     /tmp/cciBLZ6U.s:180    .text.PendSV_Handler:00000000 PendSV_Handler
+     /tmp/cciBLZ6U.s:193    .text.SysTick_Handler:00000000 $t
+     /tmp/cciBLZ6U.s:199    .text.SysTick_Handler:00000000 SysTick_Handler
+     /tmp/cciBLZ6U.s:219    .text.USB_LP_IRQHandler:00000000 $t
+     /tmp/cciBLZ6U.s:225    .text.USB_LP_IRQHandler:00000000 USB_LP_IRQHandler
+     /tmp/cciBLZ6U.s:245    .text.USB_LP_IRQHandler:0000000c $d
+     /tmp/cciBLZ6U.s:250    .text.TIM3_IRQHandler:00000000 $t
+     /tmp/cciBLZ6U.s:256    .text.TIM3_IRQHandler:00000000 TIM3_IRQHandler
+     /tmp/cciBLZ6U.s:276    .text.TIM3_IRQHandler:0000000c $d
+
+UNDEFINED SYMBOLS
+HAL_IncTick
+HAL_PCD_IRQHandler
+hpcd_USB_FS
+HAL_TIM_IRQHandler
+htim3
diff --git a/squeow_sw/build/stm32g4xx_it.o b/squeow_sw/build/stm32g4xx_it.o
new file mode 100644
index 0000000000000000000000000000000000000000..2d789126c13c19b5d4c06c4c78d65623b14e173b
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diff --git a/squeow_sw/build/stm32g4xx_ll_adc.d b/squeow_sw/build/stm32g4xx_ll_adc.d
new file mode 100644
index 0000000..d414128
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_ll_adc.d
@@ -0,0 +1,2 @@
+build/stm32g4xx_ll_adc.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c
diff --git a/squeow_sw/build/stm32g4xx_ll_adc.lst b/squeow_sw/build/stm32g4xx_ll_adc.lst
new file mode 100644
index 0000000..d380929
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_ll_adc.lst
@@ -0,0 +1,30 @@
+ARM GAS  /tmp/ccsoDKzN.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_ll_adc.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c"
+  20              	.Letext0:
+ARM GAS  /tmp/ccsoDKzN.s 			page 2
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_ll_adc.c
+
+NO UNDEFINED SYMBOLS
diff --git a/squeow_sw/build/stm32g4xx_ll_adc.o b/squeow_sw/build/stm32g4xx_ll_adc.o
new file mode 100644
index 0000000000000000000000000000000000000000..51f87b848bb3dab3fde10cad567d5fcf1e7e636a
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literal 0
HcmV?d00001

diff --git a/squeow_sw/build/stm32g4xx_ll_usb.d b/squeow_sw/build/stm32g4xx_ll_usb.d
new file mode 100644
index 0000000..f711e1a
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_ll_usb.d
@@ -0,0 +1,74 @@
+build/stm32g4xx_ll_usb.o: \
+ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/stm32g4xx_ll_usb.lst b/squeow_sw/build/stm32g4xx_ll_usb.lst
new file mode 100644
index 0000000..5963056
--- /dev/null
+++ b/squeow_sw/build/stm32g4xx_ll_usb.lst
@@ -0,0 +1,5711 @@
+ARM GAS  /tmp/cc2t6zYn.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"stm32g4xx_ll_usb.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c"
+  20              		.section	.text.USB_CoreInit,"ax",%progbits
+  21              		.align	1
+  22              		.global	USB_CoreInit
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	USB_CoreInit:
+  28              	.LVL0:
+  29              	.LFB329:
+   1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+   2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   ******************************************************************************
+   3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @file    stm32g4xx_ll_usb.c
+   4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @author  MCD Application Team
+   5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief   USB Low Layer HAL module driver.
+   6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *
+   7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *          This file provides firmware functions to manage the following
+   8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *          functionalities of the USB Peripheral Controller:
+   9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *           + Initialization/de-initialization functions
+  10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *           + I/O operation functions
+  11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *           + Peripheral Control functions
+  12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *           + Peripheral State functions
+  13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *
+  14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   ******************************************************************************
+  15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @attention
+  16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *
+  17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * Copyright (c) 2019 STMicroelectronics.
+  18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * All rights reserved.
+  19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *
+  20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * in the root directory of this software component.
+  22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *
+  24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   ******************************************************************************
+  25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   @verbatim
+  26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   ==============================================================================
+  27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****                     ##### How to use this driver #####
+  28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   ==============================================================================
+  29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     [..]
+ARM GAS  /tmp/cc2t6zYn.s 			page 2
+
+
+  30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
+  31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+  33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+  35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   @endverbatim
+  37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   ******************************************************************************
+  39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+  40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /* Includes ------------------------------------------------------------------*/
+  42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #include "stm32g4xx_hal.h"
+  43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /** @addtogroup STM32G4xx_LL_USB_DRIVER
+  45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @{
+  46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+  47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
+  49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #if defined (USB)
+  50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /* Private typedef -----------------------------------------------------------*/
+  51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /* Private define ------------------------------------------------------------*/
+  52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /* Private macro -------------------------------------------------------------*/
+  53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /* Private variables ---------------------------------------------------------*/
+  54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /* Private function prototypes -----------------------------------------------*/
+  55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /* Private functions ---------------------------------------------------------*/
+  56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+  58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  Initializes the USB Core
+  59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx USB Instance
+  60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  cfg pointer to a USB_CfgTypeDef structure that contains
+  61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *         the configuration information for the specified USBx peripheral.
+  62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+  63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+  64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
+  65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+  30              		.loc 1 65 1 view -0
+  31              		.cfi_startproc
+  32              		@ args = 36, pretend = 16, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		@ link register save eliminated.
+  35              		.loc 1 65 1 is_stmt 0 view .LVU1
+  36 0000 84B0     		sub	sp, sp, #16
+  37              	.LCFI0:
+  38              		.cfi_def_cfa_offset 16
+  39 0002 01A8     		add	r0, sp, #4
+  40              	.LVL1:
+  41              		.loc 1 65 1 view .LVU2
+  42 0004 80E80E00 		stm	r0, {r1, r2, r3}
+  66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Prevent unused argument(s) compilation warning */
+  67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   UNUSED(USBx);
+  43              		.loc 1 67 3 is_stmt 1 view .LVU3
+  68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   UNUSED(cfg);
+  44              		.loc 1 68 3 view .LVU4
+  69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+  71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               only by USB OTG FS peripheral.
+ARM GAS  /tmp/cc2t6zYn.s 			page 3
+
+
+  72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             - This function is added to ensure compatibility across platforms.
+  73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****    */
+  74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+  45              		.loc 1 75 3 view .LVU5
+  76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+  46              		.loc 1 76 1 is_stmt 0 view .LVU6
+  47 0008 0020     		movs	r0, #0
+  48 000a 04B0     		add	sp, sp, #16
+  49              	.LCFI1:
+  50              		.cfi_def_cfa_offset 0
+  51 000c 7047     		bx	lr
+  52              		.cfi_endproc
+  53              	.LFE329:
+  55              		.section	.text.USB_EnableGlobalInt,"ax",%progbits
+  56              		.align	1
+  57              		.global	USB_EnableGlobalInt
+  58              		.syntax unified
+  59              		.thumb
+  60              		.thumb_func
+  62              	USB_EnableGlobalInt:
+  63              	.LVL2:
+  64              	.LFB330:
+  77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+  79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_EnableGlobalInt
+  80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *         Enables the controller's Global Int in the AHB Config reg
+  81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+  82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+  83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+  84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
+  85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+  65              		.loc 1 85 1 is_stmt 1 view -0
+  66              		.cfi_startproc
+  67              		@ args = 0, pretend = 0, frame = 0
+  68              		@ frame_needed = 0, uses_anonymous_args = 0
+  69              		@ link register save eliminated.
+  70              		.loc 1 85 1 is_stmt 0 view .LVU8
+  71 0000 0346     		mov	r3, r0
+  86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t winterruptmask;
+  72              		.loc 1 86 3 is_stmt 1 view .LVU9
+  87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Clear pending interrupts */
+  89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->ISTR = 0U;
+  73              		.loc 1 89 3 view .LVU10
+  74              		.loc 1 89 14 is_stmt 0 view .LVU11
+  75 0002 0020     		movs	r0, #0
+  76              	.LVL3:
+  77              		.loc 1 89 14 view .LVU12
+  78 0004 A3F84400 		strh	r0, [r3, #68]	@ movhi
+  90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Set winterruptmask variable */
+  92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM |
+  79              		.loc 1 92 3 is_stmt 1 view .LVU13
+  80              	.LVL4:
+  93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****                    USB_CNTR_SUSPM | USB_CNTR_ERRM |
+  94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****                    USB_CNTR_SOFM | USB_CNTR_ESOFM |
+ARM GAS  /tmp/cc2t6zYn.s 			page 4
+
+
+  95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****                    USB_CNTR_RESETM | USB_CNTR_L1REQM;
+  96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+  97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Set interrupt mask */
+  98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->CNTR = (uint16_t)winterruptmask;
+  81              		.loc 1 98 3 view .LVU14
+  82              		.loc 1 98 14 is_stmt 0 view .LVU15
+  83 0008 4BF68072 		movw	r2, #49024
+  84 000c A3F84020 		strh	r2, [r3, #64]	@ movhi
+  99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+  85              		.loc 1 100 3 is_stmt 1 view .LVU16
+ 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+  86              		.loc 1 101 1 is_stmt 0 view .LVU17
+  87 0010 7047     		bx	lr
+  88              		.cfi_endproc
+  89              	.LFE330:
+  91              		.section	.text.USB_DisableGlobalInt,"ax",%progbits
+  92              		.align	1
+  93              		.global	USB_DisableGlobalInt
+  94              		.syntax unified
+  95              		.thumb
+  96              		.thumb_func
+  98              	USB_DisableGlobalInt:
+  99              	.LVL5:
+ 100              	.LFB331:
+ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_DisableGlobalInt
+ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *         Disable the controller's Global Int in the AHB Config reg
+ 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
+ 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 101              		.loc 1 110 1 is_stmt 1 view -0
+ 102              		.cfi_startproc
+ 103              		@ args = 0, pretend = 0, frame = 0
+ 104              		@ frame_needed = 0, uses_anonymous_args = 0
+ 105              		@ link register save eliminated.
+ 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t winterruptmask;
+ 106              		.loc 1 111 3 view .LVU19
+ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Set winterruptmask variable */
+ 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM |
+ 107              		.loc 1 114 3 view .LVU20
+ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****                    USB_CNTR_SUSPM | USB_CNTR_ERRM |
+ 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****                    USB_CNTR_SOFM | USB_CNTR_ESOFM |
+ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****                    USB_CNTR_RESETM | USB_CNTR_L1REQM;
+ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Clear interrupt mask */
+ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->CNTR &= (uint16_t)(~winterruptmask);
+ 108              		.loc 1 120 3 view .LVU21
+ 109              		.loc 1 120 7 is_stmt 0 view .LVU22
+ 110 0000 B0F84030 		ldrh	r3, [r0, #64]
+ 111              		.loc 1 120 14 view .LVU23
+ 112 0004 23F47E53 		bic	r3, r3, #16256
+ 113 0008 5B04     		lsls	r3, r3, #17
+ARM GAS  /tmp/cc2t6zYn.s 			page 5
+
+
+ 114 000a 5B0C     		lsrs	r3, r3, #17
+ 115 000c A0F84030 		strh	r3, [r0, #64]	@ movhi
+ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ 116              		.loc 1 122 3 is_stmt 1 view .LVU24
+ 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 117              		.loc 1 123 1 is_stmt 0 view .LVU25
+ 118 0010 0020     		movs	r0, #0
+ 119              	.LVL6:
+ 120              		.loc 1 123 1 view .LVU26
+ 121 0012 7047     		bx	lr
+ 122              		.cfi_endproc
+ 123              	.LFE331:
+ 125              		.section	.text.USB_SetCurrentMode,"ax",%progbits
+ 126              		.align	1
+ 127              		.global	USB_SetCurrentMode
+ 128              		.syntax unified
+ 129              		.thumb
+ 130              		.thumb_func
+ 132              	USB_SetCurrentMode:
+ 133              	.LVL7:
+ 134              	.LFB332:
+ 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_SetCurrentMode Set functional mode
+ 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  mode current core mode
+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *          This parameter can be one of the these values:
+ 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *            @arg USB_DEVICE_MODE Peripheral mode
+ 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
+ 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 135              		.loc 1 134 1 is_stmt 1 view -0
+ 136              		.cfi_startproc
+ 137              		@ args = 0, pretend = 0, frame = 0
+ 138              		@ frame_needed = 0, uses_anonymous_args = 0
+ 139              		@ link register save eliminated.
+ 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Prevent unused argument(s) compilation warning */
+ 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   UNUSED(USBx);
+ 140              		.loc 1 136 3 view .LVU28
+ 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   UNUSED(mode);
+ 141              		.loc 1 137 3 view .LVU29
+ 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               only by USB OTG FS peripheral.
+ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             - This function is added to ensure compatibility across platforms.
+ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****    */
+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ 142              		.loc 1 143 3 view .LVU30
+ 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 143              		.loc 1 144 1 is_stmt 0 view .LVU31
+ 144 0000 0020     		movs	r0, #0
+ 145              	.LVL8:
+ 146              		.loc 1 144 1 view .LVU32
+ 147 0002 7047     		bx	lr
+ 148              		.cfi_endproc
+ARM GAS  /tmp/cc2t6zYn.s 			page 6
+
+
+ 149              	.LFE332:
+ 151              		.section	.text.USB_DevInit,"ax",%progbits
+ 152              		.align	1
+ 153              		.global	USB_DevInit
+ 154              		.syntax unified
+ 155              		.thumb
+ 156              		.thumb_func
+ 158              	USB_DevInit:
+ 159              	.LVL9:
+ 160              	.LFB333:
+ 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_DevInit Initializes the USB controller registers
+ 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *         for device mode
+ 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  cfg  pointer to a USB_CfgTypeDef structure that contains
+ 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *         the configuration information for the specified USBx peripheral.
+ 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
+ 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 161              		.loc 1 155 1 is_stmt 1 view -0
+ 162              		.cfi_startproc
+ 163              		@ args = 36, pretend = 16, frame = 0
+ 164              		@ frame_needed = 0, uses_anonymous_args = 0
+ 165              		@ link register save eliminated.
+ 166              		.loc 1 155 1 is_stmt 0 view .LVU34
+ 167 0000 84B0     		sub	sp, sp, #16
+ 168              	.LCFI2:
+ 169              		.cfi_def_cfa_offset 16
+ 170 0002 8446     		mov	ip, r0
+ 171 0004 01A8     		add	r0, sp, #4
+ 172              	.LVL10:
+ 173              		.loc 1 155 1 view .LVU35
+ 174 0006 80E80E00 		stm	r0, {r1, r2, r3}
+ 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Prevent unused argument(s) compilation warning */
+ 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   UNUSED(cfg);
+ 175              		.loc 1 157 3 is_stmt 1 view .LVU36
+ 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Init Device */
+ 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* CNTR_FRES = 1 */
+ 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->CNTR = (uint16_t)USB_CNTR_FRES;
+ 176              		.loc 1 161 3 view .LVU37
+ 177              		.loc 1 161 14 is_stmt 0 view .LVU38
+ 178 000a 0123     		movs	r3, #1
+ 179 000c ACF84030 		strh	r3, [ip, #64]	@ movhi
+ 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* CNTR_FRES = 0 */
+ 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->CNTR = 0U;
+ 180              		.loc 1 164 3 is_stmt 1 view .LVU39
+ 181              		.loc 1 164 14 is_stmt 0 view .LVU40
+ 182 0010 0020     		movs	r0, #0
+ 183 0012 ACF84000 		strh	r0, [ip, #64]	@ movhi
+ 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Clear pending interrupts */
+ 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->ISTR = 0U;
+ 184              		.loc 1 167 3 is_stmt 1 view .LVU41
+ARM GAS  /tmp/cc2t6zYn.s 			page 7
+
+
+ 185              		.loc 1 167 14 is_stmt 0 view .LVU42
+ 186 0016 ACF84400 		strh	r0, [ip, #68]	@ movhi
+ 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /*Set Btable Address*/
+ 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->BTABLE = BTABLE_ADDRESS;
+ 187              		.loc 1 170 3 is_stmt 1 view .LVU43
+ 188              		.loc 1 170 16 is_stmt 0 view .LVU44
+ 189 001a ACF85000 		strh	r0, [ip, #80]	@ movhi
+ 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ 190              		.loc 1 172 3 is_stmt 1 view .LVU45
+ 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 191              		.loc 1 173 1 is_stmt 0 view .LVU46
+ 192 001e 04B0     		add	sp, sp, #16
+ 193              	.LCFI3:
+ 194              		.cfi_def_cfa_offset 0
+ 195 0020 7047     		bx	lr
+ 196              		.cfi_endproc
+ 197              	.LFE333:
+ 199              		.section	.text.USB_ActivateEndpoint,"ax",%progbits
+ 200              		.align	1
+ 201              		.global	USB_ActivateEndpoint
+ 202              		.syntax unified
+ 203              		.thumb
+ 204              		.thumb_func
+ 206              	USB_ActivateEndpoint:
+ 207              	.LVL11:
+ 208              	.LFB334:
+ 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #if defined (HAL_PCD_MODULE_ENABLED)
+ 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  Activate and configure an endpoint
+ 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  ep pointer to endpoint structure
+ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 209              		.loc 1 183 1 is_stmt 1 view -0
+ 210              		.cfi_startproc
+ 211              		@ args = 0, pretend = 0, frame = 0
+ 212              		@ frame_needed = 0, uses_anonymous_args = 0
+ 213              		.loc 1 183 1 is_stmt 0 view .LVU48
+ 214 0000 10B5     		push	{r4, lr}
+ 215              	.LCFI4:
+ 216              		.cfi_def_cfa_offset 8
+ 217              		.cfi_offset 4, -8
+ 218              		.cfi_offset 14, -4
+ 219 0002 0346     		mov	r3, r0
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   HAL_StatusTypeDef ret = HAL_OK;
+ 220              		.loc 1 184 3 is_stmt 1 view .LVU49
+ 221              	.LVL12:
+ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint16_t wEpRegVal;
+ 222              		.loc 1 185 3 view .LVU50
+ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
+ 223              		.loc 1 187 3 view .LVU51
+ARM GAS  /tmp/cc2t6zYn.s 			page 8
+
+
+ 224              		.loc 1 187 15 is_stmt 0 view .LVU52
+ 225 0004 91F800C0 		ldrb	ip, [r1]	@ zero_extendqisi2
+ 226              		.loc 1 187 47 view .LVU53
+ 227 0008 30F82C20 		ldrh	r2, [r0, ip, lsl #2]
+ 228 000c 92B2     		uxth	r2, r2
+ 229              		.loc 1 187 13 view .LVU54
+ 230 000e 22F4EC42 		bic	r2, r2, #30208
+ 231 0012 22F07002 		bic	r2, r2, #112
+ 232 0016 92B2     		uxth	r2, r2
+ 233              	.LVL13:
+ 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* initialize Endpoint */
+ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   switch (ep->type)
+ 234              		.loc 1 190 3 is_stmt 1 view .LVU55
+ 235              		.loc 1 190 13 is_stmt 0 view .LVU56
+ 236 0018 C878     		ldrb	r0, [r1, #3]	@ zero_extendqisi2
+ 237              	.LVL14:
+ 238              		.loc 1 190 3 view .LVU57
+ 239 001a 0328     		cmp	r0, #3
+ 240 001c 61D8     		bhi	.L35
+ 241 001e DFE800F0 		tbb	[pc, r0]
+ 242              	.L11:
+ 243 0022 55       		.byte	(.L14-.L11)/2
+ 244 0023 5C       		.byte	(.L13-.L11)/2
+ 245 0024 02       		.byte	(.L12-.L11)/2
+ 246 0025 58       		.byte	(.L10-.L11)/2
+ 247              		.p2align 1
+ 248              	.L12:
+ 249 0026 0020     		movs	r0, #0
+ 250              	.L9:
+ 251              	.LVL15:
+ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     case EP_TYPE_CTRL:
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       wEpRegVal |= USB_EP_CONTROL;
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       break;
+ 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     case EP_TYPE_BULK:
+ 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       wEpRegVal |= USB_EP_BULK;
+ 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       break;
+ 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     case EP_TYPE_INTR:
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       wEpRegVal |= USB_EP_INTERRUPT;
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       break;
+ 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     case EP_TYPE_ISOC:
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       wEpRegVal |= USB_EP_ISOCHRONOUS;
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       break;
+ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     default:
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       ret = HAL_ERROR;
+ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       break;
+ 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
+ 252              		.loc 1 213 3 is_stmt 1 view .LVU58
+ 253 0028 48F2800E 		movw	lr, #32896
+ 254 002c 42EA0E02 		orr	r2, r2, lr
+ARM GAS  /tmp/cc2t6zYn.s 			page 9
+
+
+ 255              	.LVL16:
+ 256              		.loc 1 213 3 is_stmt 0 view .LVU59
+ 257 0030 23F82C20 		strh	r2, [r3, ip, lsl #2]	@ movhi
+ 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
+ 258              		.loc 1 215 3 is_stmt 1 view .LVU60
+ 259              	.LBB2:
+ 260              		.loc 1 215 3 view .LVU61
+ 261              		.loc 1 215 3 view .LVU62
+ 262 0034 91F800C0 		ldrb	ip, [r1]	@ zero_extendqisi2
+ 263 0038 33F82C20 		ldrh	r2, [r3, ip, lsl #2]
+ 264 003c 92B2     		uxth	r2, r2
+ 265 003e 22F4E042 		bic	r2, r2, #28672
+ 266 0042 22F07002 		bic	r2, r2, #112
+ 267 0046 4CEA0202 		orr	r2, ip, r2
+ 268              	.LVL17:
+ 269              		.loc 1 215 3 view .LVU63
+ 270 004a 42EA0E02 		orr	r2, r2, lr
+ 271              	.LVL18:
+ 272              		.loc 1 215 3 is_stmt 0 view .LVU64
+ 273 004e 23F82C20 		strh	r2, [r3, ip, lsl #2]	@ movhi
+ 274              	.LBE2:
+ 275              		.loc 1 215 3 is_stmt 1 view .LVU65
+ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   if (ep->doublebuffer == 0U)
+ 276              		.loc 1 217 3 view .LVU66
+ 277              		.loc 1 217 9 is_stmt 0 view .LVU67
+ 278 0052 0A7B     		ldrb	r2, [r1, #12]	@ zero_extendqisi2
+ 279              		.loc 1 217 6 view .LVU68
+ 280 0054 002A     		cmp	r2, #0
+ 281 0056 40F0C280 		bne	.L15
+ 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     if (ep->is_in != 0U)
+ 282              		.loc 1 219 5 is_stmt 1 view .LVU69
+ 283              		.loc 1 219 11 is_stmt 0 view .LVU70
+ 284 005a 4A78     		ldrb	r2, [r1, #1]	@ zero_extendqisi2
+ 285              		.loc 1 219 8 view .LVU71
+ 286 005c 002A     		cmp	r2, #0
+ 287 005e 51D0     		beq	.L16
+ 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /*Set the endpoint Transmit buffer address */
+ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
+ 288              		.loc 1 222 7 is_stmt 1 view .LVU72
+ 289              	.LBB3:
+ 290              		.loc 1 222 7 view .LVU73
+ 291              		.loc 1 222 7 view .LVU74
+ 292              	.LVL19:
+ 293              		.loc 1 222 7 view .LVU75
+ 294 0060 B3F85020 		ldrh	r2, [r3, #80]
+ 295 0064 13FA82F2 		uxtah	r2, r3, r2
+ 296              	.LVL20:
+ 297              		.loc 1 222 7 view .LVU76
+ 298 0068 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 299 006a 02EBC402 		add	r2, r2, r4, lsl #3
+ 300              	.LVL21:
+ 301              		.loc 1 222 7 view .LVU77
+ 302 006e B1F806C0 		ldrh	ip, [r1, #6]
+ARM GAS  /tmp/cc2t6zYn.s 			page 10
+
+
+ 303              		.loc 1 222 7 is_stmt 0 view .LVU78
+ 304 0072 4FEA5C0C 		lsr	ip, ip, #1
+ 305 0076 4FEA4C0C 		lsl	ip, ip, #1
+ 306 007a A2F800C4 		strh	ip, [r2, #1024]	@ movhi
+ 307              	.LBE3:
+ 308              		.loc 1 222 7 is_stmt 1 view .LVU79
+ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 309              		.loc 1 223 7 view .LVU80
+ 310              	.LBB4:
+ 311              		.loc 1 223 7 view .LVU81
+ 312              		.loc 1 223 7 view .LVU82
+ 313 007e 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 314 0080 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 315              	.LVL22:
+ 316              		.loc 1 223 7 view .LVU83
+ 317 0084 12F0400F 		tst	r2, #64
+ 318 0088 0CD0     		beq	.L17
+ 319              		.loc 1 223 7 discriminator 1 view .LVU84
+ 320              	.LBB5:
+ 321              		.loc 1 223 7 discriminator 1 view .LVU85
+ 322              		.loc 1 223 7 discriminator 1 view .LVU86
+ 323 008a 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 324              	.LVL23:
+ 325              		.loc 1 223 7 is_stmt 0 discriminator 1 view .LVU87
+ 326 008e 92B2     		uxth	r2, r2
+ 327 0090 22F4E042 		bic	r2, r2, #28672
+ 328 0094 22F07002 		bic	r2, r2, #112
+ 329              	.LVL24:
+ 330              		.loc 1 223 7 is_stmt 1 discriminator 1 view .LVU88
+ 331 0098 42F40042 		orr	r2, r2, #32768
+ 332              	.LVL25:
+ 333              		.loc 1 223 7 is_stmt 0 discriminator 1 view .LVU89
+ 334 009c 42F0C002 		orr	r2, r2, #192
+ 335 00a0 23F82420 		strh	r2, [r3, r4, lsl #2]	@ movhi
+ 336              	.LVL26:
+ 337              	.L17:
+ 338              		.loc 1 223 7 discriminator 1 view .LVU90
+ 339              	.LBE5:
+ 340              		.loc 1 223 7 is_stmt 1 discriminator 3 view .LVU91
+ 341              	.LBE4:
+ 342              		.loc 1 223 7 discriminator 3 view .LVU92
+ 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       if (ep->type != EP_TYPE_ISOC)
+ 343              		.loc 1 225 7 discriminator 3 view .LVU93
+ 344              		.loc 1 225 13 is_stmt 0 discriminator 3 view .LVU94
+ 345 00a4 CA78     		ldrb	r2, [r1, #3]	@ zero_extendqisi2
+ 346              		.loc 1 225 10 discriminator 3 view .LVU95
+ 347 00a6 012A     		cmp	r2, #1
+ 348 00a8 1DD0     		beq	.L18
+ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         /* Configure NAK status for the Endpoint */
+ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ 349              		.loc 1 228 9 is_stmt 1 view .LVU96
+ 350              	.LBB6:
+ 351              		.loc 1 228 9 view .LVU97
+ 352              		.loc 1 228 9 view .LVU98
+ 353 00aa 0978     		ldrb	r1, [r1]	@ zero_extendqisi2
+ARM GAS  /tmp/cc2t6zYn.s 			page 11
+
+
+ 354              	.LVL27:
+ 355              		.loc 1 228 9 is_stmt 0 view .LVU99
+ 356 00ac 33F82120 		ldrh	r2, [r3, r1, lsl #2]
+ 357 00b0 92B2     		uxth	r2, r2
+ 358 00b2 22F4E042 		bic	r2, r2, #28672
+ 359 00b6 22F04002 		bic	r2, r2, #64
+ 360              	.LVL28:
+ 361              		.loc 1 228 9 is_stmt 1 view .LVU100
+ 362              		.loc 1 228 9 view .LVU101
+ 363              		.loc 1 228 9 view .LVU102
+ 364 00ba 82F02002 		eor	r2, r2, #32
+ 365              	.LVL29:
+ 366              		.loc 1 228 9 view .LVU103
+ 367 00be 42F40042 		orr	r2, r2, #32768
+ 368              	.LVL30:
+ 369              		.loc 1 228 9 is_stmt 0 view .LVU104
+ 370 00c2 42F08002 		orr	r2, r2, #128
+ 371 00c6 23F82120 		strh	r2, [r3, r1, lsl #2]	@ movhi
+ 372              	.LBE6:
+ 373              		.loc 1 228 9 is_stmt 1 view .LVU105
+ 374 00ca 66E0     		b	.L19
+ 375              	.LVL31:
+ 376              	.L14:
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       break;
+ 377              		.loc 1 193 7 view .LVU106
+ 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       break;
+ 378              		.loc 1 193 17 is_stmt 0 view .LVU107
+ 379 00cc 42F40072 		orr	r2, r2, #512
+ 380              	.LVL32:
+ 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 381              		.loc 1 194 7 is_stmt 1 view .LVU108
+ 382 00d0 AAE7     		b	.L9
+ 383              	.L10:
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       break;
+ 384              		.loc 1 201 7 view .LVU109
+ 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       break;
+ 385              		.loc 1 201 17 is_stmt 0 view .LVU110
+ 386 00d2 42F4C062 		orr	r2, r2, #1536
+ 387              	.LVL33:
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 388              		.loc 1 202 7 is_stmt 1 view .LVU111
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint16_t wEpRegVal;
+ 389              		.loc 1 184 21 is_stmt 0 view .LVU112
+ 390 00d6 0020     		movs	r0, #0
+ 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 391              		.loc 1 202 7 view .LVU113
+ 392 00d8 A6E7     		b	.L9
+ 393              	.L13:
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       break;
+ 394              		.loc 1 205 7 is_stmt 1 view .LVU114
+ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       break;
+ 395              		.loc 1 205 17 is_stmt 0 view .LVU115
+ 396 00da 42F48062 		orr	r2, r2, #1024
+ 397              	.LVL34:
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 398              		.loc 1 206 7 is_stmt 1 view .LVU116
+ 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint16_t wEpRegVal;
+ARM GAS  /tmp/cc2t6zYn.s 			page 12
+
+
+ 399              		.loc 1 184 21 is_stmt 0 view .LVU117
+ 400 00de 0020     		movs	r0, #0
+ 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 401              		.loc 1 206 7 view .LVU118
+ 402 00e0 A2E7     		b	.L9
+ 403              	.L35:
+ 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       break;
+ 404              		.loc 1 209 11 view .LVU119
+ 405 00e2 0120     		movs	r0, #1
+ 406 00e4 A0E7     		b	.L9
+ 407              	.LVL35:
+ 408              	.L18:
+ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       else
+ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         /* Configure TX Endpoint to disabled state */
+ 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 409              		.loc 1 233 9 is_stmt 1 view .LVU120
+ 410              	.LBB7:
+ 411              		.loc 1 233 9 view .LVU121
+ 412              		.loc 1 233 9 view .LVU122
+ 413 00e6 0978     		ldrb	r1, [r1]	@ zero_extendqisi2
+ 414              	.LVL36:
+ 415              		.loc 1 233 9 is_stmt 0 view .LVU123
+ 416 00e8 33F82120 		ldrh	r2, [r3, r1, lsl #2]
+ 417 00ec 92B2     		uxth	r2, r2
+ 418 00ee 22F4E042 		bic	r2, r2, #28672
+ 419 00f2 22F04002 		bic	r2, r2, #64
+ 420              	.LVL37:
+ 421              		.loc 1 233 9 is_stmt 1 view .LVU124
+ 422              		.loc 1 233 9 view .LVU125
+ 423              		.loc 1 233 9 view .LVU126
+ 424 00f6 42F40042 		orr	r2, r2, #32768
+ 425              	.LVL38:
+ 426              		.loc 1 233 9 is_stmt 0 view .LVU127
+ 427 00fa 42F08002 		orr	r2, r2, #128
+ 428 00fe 23F82120 		strh	r2, [r3, r1, lsl #2]	@ movhi
+ 429 0102 4AE0     		b	.L19
+ 430              	.LVL39:
+ 431              	.L16:
+ 432              		.loc 1 233 9 view .LVU128
+ 433              	.LBE7:
+ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     else
+ 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Set the endpoint Receive buffer address */
+ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
+ 434              		.loc 1 239 7 is_stmt 1 view .LVU129
+ 435              	.LBB8:
+ 436              		.loc 1 239 7 view .LVU130
+ 437              		.loc 1 239 7 view .LVU131
+ 438              		.loc 1 239 7 view .LVU132
+ 439 0104 B3F85020 		ldrh	r2, [r3, #80]
+ 440 0108 13FA82F2 		uxtah	r2, r3, r2
+ 441              	.LVL40:
+ 442              		.loc 1 239 7 view .LVU133
+ARM GAS  /tmp/cc2t6zYn.s 			page 13
+
+
+ 443 010c 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 444 010e 02EBC402 		add	r2, r2, r4, lsl #3
+ 445              	.LVL41:
+ 446              		.loc 1 239 7 view .LVU134
+ 447 0112 B1F806C0 		ldrh	ip, [r1, #6]
+ 448              		.loc 1 239 7 is_stmt 0 view .LVU135
+ 449 0116 4FEA5C0C 		lsr	ip, ip, #1
+ 450 011a 4FEA4C0C 		lsl	ip, ip, #1
+ 451 011e A2F804C4 		strh	ip, [r2, #1028]	@ movhi
+ 452              	.LBE8:
+ 453              		.loc 1 239 7 is_stmt 1 view .LVU136
+ 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Set the endpoint Receive buffer counter */
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
+ 454              		.loc 1 242 7 view .LVU137
+ 455              	.LBB9:
+ 456              		.loc 1 242 7 view .LVU138
+ 457              	.LVL42:
+ 458              		.loc 1 242 7 view .LVU139
+ 459              		.loc 1 242 7 view .LVU140
+ 460 0122 B3F85020 		ldrh	r2, [r3, #80]
+ 461              	.LVL43:
+ 462              		.loc 1 242 7 is_stmt 0 view .LVU141
+ 463 0126 13FA82F2 		uxtah	r2, r3, r2
+ 464              	.LVL44:
+ 465              		.loc 1 242 7 is_stmt 1 view .LVU142
+ 466 012a 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 467              		.loc 1 242 7 is_stmt 0 view .LVU143
+ 468 012c 02EBC402 		add	r2, r2, r4, lsl #3
+ 469              	.LVL45:
+ 470              		.loc 1 242 7 is_stmt 1 view .LVU144
+ 471              	.LBB10:
+ 472              		.loc 1 242 7 view .LVU145
+ 473              		.loc 1 242 7 view .LVU146
+ 474 0130 0C69     		ldr	r4, [r1, #16]
+ 475 0132 3E2C     		cmp	r4, #62
+ 476 0134 32D9     		bls	.L20
+ 477              		.loc 1 242 7 discriminator 1 view .LVU147
+ 478              		.loc 1 242 7 discriminator 1 view .LVU148
+ 479 0136 4FEA541C 		lsr	ip, r4, #5
+ 480              	.LVL46:
+ 481              		.loc 1 242 7 discriminator 1 view .LVU149
+ 482 013a 14F01F0F 		tst	r4, #31
+ 483 013e 01D1     		bne	.L21
+ 484              		.loc 1 242 7 discriminator 3 view .LVU150
+ 485 0140 0CF1FF3C 		add	ip, ip, #-1
+ 486              	.LVL47:
+ 487              	.L21:
+ 488              		.loc 1 242 7 discriminator 5 view .LVU151
+ 489 0144 6FEACC6C 		mvn	ip, ip, lsl #27
+ 490              	.LVL48:
+ 491              		.loc 1 242 7 is_stmt 0 discriminator 5 view .LVU152
+ 492 0148 6FEA5C4C 		mvn	ip, ip, lsr #17
+ 493 014c 1FFA8CFC 		uxth	ip, ip
+ 494 0150 A2F806C4 		strh	ip, [r2, #1030]	@ movhi
+ 495              		.loc 1 242 7 is_stmt 1 discriminator 5 view .LVU153
+ 496              	.LVL49:
+ARM GAS  /tmp/cc2t6zYn.s 			page 14
+
+
+ 497              	.L22:
+ 498              		.loc 1 242 7 discriminator 13 view .LVU154
+ 499              	.LBE10:
+ 500              		.loc 1 242 7 discriminator 13 view .LVU155
+ 501              	.LBE9:
+ 502              		.loc 1 242 7 discriminator 13 view .LVU156
+ 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 503              		.loc 1 243 7 discriminator 13 view .LVU157
+ 504              	.LBB12:
+ 505              		.loc 1 243 7 discriminator 13 view .LVU158
+ 506              		.loc 1 243 7 discriminator 13 view .LVU159
+ 507 0154 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 508 0156 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 509              	.LVL50:
+ 510              		.loc 1 243 7 discriminator 13 view .LVU160
+ 511 015a 12F4804F 		tst	r2, #16384
+ 512 015e 0CD0     		beq	.L25
+ 513              		.loc 1 243 7 discriminator 1 view .LVU161
+ 514              	.LBB13:
+ 515              		.loc 1 243 7 discriminator 1 view .LVU162
+ 516              		.loc 1 243 7 discriminator 1 view .LVU163
+ 517 0160 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 518              	.LVL51:
+ 519              		.loc 1 243 7 is_stmt 0 discriminator 1 view .LVU164
+ 520 0164 92B2     		uxth	r2, r2
+ 521 0166 22F4E042 		bic	r2, r2, #28672
+ 522 016a 22F07002 		bic	r2, r2, #112
+ 523              	.LVL52:
+ 524              		.loc 1 243 7 is_stmt 1 discriminator 1 view .LVU165
+ 525 016e 42F44042 		orr	r2, r2, #49152
+ 526              	.LVL53:
+ 527              		.loc 1 243 7 is_stmt 0 discriminator 1 view .LVU166
+ 528 0172 42F08002 		orr	r2, r2, #128
+ 529 0176 23F82420 		strh	r2, [r3, r4, lsl #2]	@ movhi
+ 530              	.LVL54:
+ 531              	.L25:
+ 532              		.loc 1 243 7 discriminator 1 view .LVU167
+ 533              	.LBE13:
+ 534              		.loc 1 243 7 is_stmt 1 discriminator 3 view .LVU168
+ 535              	.LBE12:
+ 536              		.loc 1 243 7 discriminator 3 view .LVU169
+ 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Configure VALID status for the Endpoint */
+ 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ 537              		.loc 1 246 7 discriminator 3 view .LVU170
+ 538              	.LBB14:
+ 539              		.loc 1 246 7 discriminator 3 view .LVU171
+ 540              		.loc 1 246 7 discriminator 3 view .LVU172
+ 541 017a 0978     		ldrb	r1, [r1]	@ zero_extendqisi2
+ 542              	.LVL55:
+ 543              		.loc 1 246 7 is_stmt 0 discriminator 3 view .LVU173
+ 544 017c 33F82120 		ldrh	r2, [r3, r1, lsl #2]
+ 545 0180 92B2     		uxth	r2, r2
+ 546 0182 22F48042 		bic	r2, r2, #16384
+ 547 0186 22F07002 		bic	r2, r2, #112
+ 548              	.LVL56:
+ 549              		.loc 1 246 7 is_stmt 1 discriminator 3 view .LVU174
+ARM GAS  /tmp/cc2t6zYn.s 			page 15
+
+
+ 550              		.loc 1 246 7 discriminator 3 view .LVU175
+ 551              		.loc 1 246 7 discriminator 3 view .LVU176
+ 552              		.loc 1 246 7 discriminator 3 view .LVU177
+ 553 018a 82F44052 		eor	r2, r2, #12288
+ 554              	.LVL57:
+ 555              		.loc 1 246 7 discriminator 3 view .LVU178
+ 556 018e 42F40042 		orr	r2, r2, #32768
+ 557              	.LVL58:
+ 558              		.loc 1 246 7 is_stmt 0 discriminator 3 view .LVU179
+ 559 0192 42F08002 		orr	r2, r2, #128
+ 560 0196 23F82120 		strh	r2, [r3, r1, lsl #2]	@ movhi
+ 561              	.LVL59:
+ 562              	.L19:
+ 563              		.loc 1 246 7 discriminator 3 view .LVU180
+ 564              	.LBE14:
+ 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #if (USE_USB_DOUBLE_BUFFER == 1U)
+ 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Double Buffer */
+ 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   else
+ 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     if (ep->type == EP_TYPE_BULK)
+ 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Set bulk endpoint as double buffered */
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_BULK_EP_DBUF(USBx, ep->num);
+ 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     else
+ 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Set the ISOC endpoint in double buffer mode */
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_EP_KIND(USBx, ep->num);
+ 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     /* Set buffer address for double buffered mode */
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
+ 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     if (ep->is_in == 0U)
+ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Clear the data toggle bits for the endpoint IN/OUT */
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     else
+ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Clear the data toggle bits for the endpoint IN/OUT */
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       if (ep->type != EP_TYPE_ISOC)
+ 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         /* Configure NAK status for the Endpoint */
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       else
+ 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ARM GAS  /tmp/cc2t6zYn.s 			page 16
+
+
+ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         /* Configure TX Endpoint to disabled state */
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ 565              		.loc 1 293 7 is_stmt 1 discriminator 7 view .LVU181
+ 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return ret;
+ 566              		.loc 1 298 3 discriminator 7 view .LVU182
+ 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 567              		.loc 1 299 1 is_stmt 0 discriminator 7 view .LVU183
+ 568 019a 10BD     		pop	{r4, pc}
+ 569              	.LVL60:
+ 570              	.L20:
+ 571              	.LBB15:
+ 572              	.LBB11:
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 573              		.loc 1 242 7 is_stmt 1 discriminator 2 view .LVU184
+ 574 019c 8CB9     		cbnz	r4, .L23
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 575              		.loc 1 242 7 discriminator 7 view .LVU185
+ 576 019e B2F80644 		ldrh	r4, [r2, #1030]
+ 577 01a2 A4B2     		uxth	r4, r4
+ 578 01a4 24F4F844 		bic	r4, r4, #31744
+ 579 01a8 A4B2     		uxth	r4, r4
+ 580 01aa A2F80644 		strh	r4, [r2, #1030]	@ movhi
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 581              		.loc 1 242 7 discriminator 7 view .LVU186
+ 582 01ae B2F80644 		ldrh	r4, [r2, #1030]
+ 583 01b2 6FEA4444 		mvn	r4, r4, lsl #17
+ 584 01b6 6FEA5444 		mvn	r4, r4, lsr #17
+ 585 01ba A4B2     		uxth	r4, r4
+ 586 01bc A2F80644 		strh	r4, [r2, #1030]	@ movhi
+ 587 01c0 C8E7     		b	.L22
+ 588              	.L23:
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 589              		.loc 1 242 7 discriminator 8 view .LVU187
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 590              		.loc 1 242 7 discriminator 8 view .LVU188
+ 591 01c2 4FEA540C 		lsr	ip, r4, #1
+ 592              	.LVL61:
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 593              		.loc 1 242 7 discriminator 8 view .LVU189
+ 594 01c6 14F0010F 		tst	r4, #1
+ 595 01ca 01D0     		beq	.L24
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 596              		.loc 1 242 7 discriminator 10 view .LVU190
+ 597 01cc 0CF1010C 		add	ip, ip, #1
+ 598              	.LVL62:
+ 599              	.L24:
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 600              		.loc 1 242 7 discriminator 12 view .LVU191
+ 601 01d0 4FEA8C2C 		lsl	ip, ip, #10
+ 602              	.LVL63:
+ARM GAS  /tmp/cc2t6zYn.s 			page 17
+
+
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 603              		.loc 1 242 7 is_stmt 0 discriminator 12 view .LVU192
+ 604 01d4 1FFA8CFC 		uxth	ip, ip
+ 605 01d8 A2F806C4 		strh	ip, [r2, #1030]	@ movhi
+ 606 01dc BAE7     		b	.L22
+ 607              	.LVL64:
+ 608              	.L15:
+ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 609              		.loc 1 242 7 discriminator 12 view .LVU193
+ 610              	.LBE11:
+ 611              	.LBE15:
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 612              		.loc 1 253 5 is_stmt 1 view .LVU194
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 613              		.loc 1 253 11 is_stmt 0 view .LVU195
+ 614 01de CA78     		ldrb	r2, [r1, #3]	@ zero_extendqisi2
+ 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 615              		.loc 1 253 8 view .LVU196
+ 616 01e0 022A     		cmp	r2, #2
+ 617 01e2 72D0     		beq	.L37
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 618              		.loc 1 261 7 is_stmt 1 view .LVU197
+ 619              	.LBB16:
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 620              		.loc 1 261 7 view .LVU198
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 621              		.loc 1 261 7 view .LVU199
+ 622 01e4 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 623 01e6 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 624 01ea 92B2     		uxth	r2, r2
+ 625 01ec 22F4E242 		bic	r2, r2, #28928
+ 626 01f0 22F07002 		bic	r2, r2, #112
+ 627              	.LVL65:
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 628              		.loc 1 261 7 view .LVU200
+ 629 01f4 42F40042 		orr	r2, r2, #32768
+ 630              	.LVL66:
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 631              		.loc 1 261 7 is_stmt 0 view .LVU201
+ 632 01f8 42F08002 		orr	r2, r2, #128
+ 633 01fc 23F82420 		strh	r2, [r3, r4, lsl #2]	@ movhi
+ 634              	.LVL67:
+ 635              	.L27:
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 636              		.loc 1 261 7 view .LVU202
+ 637              	.LBE16:
+ 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 638              		.loc 1 261 7 is_stmt 1 discriminator 1 view .LVU203
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 639              		.loc 1 265 5 discriminator 1 view .LVU204
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 640              		.loc 1 265 5 discriminator 1 view .LVU205
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 641              		.loc 1 265 5 discriminator 1 view .LVU206
+ 642              	.LBB17:
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 643              		.loc 1 265 5 discriminator 1 view .LVU207
+ARM GAS  /tmp/cc2t6zYn.s 			page 18
+
+
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 644              		.loc 1 265 5 discriminator 1 view .LVU208
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 645              		.loc 1 265 5 discriminator 1 view .LVU209
+ 646 0200 B3F85020 		ldrh	r2, [r3, #80]
+ 647 0204 13FA82F2 		uxtah	r2, r3, r2
+ 648              	.LVL68:
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 649              		.loc 1 265 5 discriminator 1 view .LVU210
+ 650 0208 91F800C0 		ldrb	ip, [r1]	@ zero_extendqisi2
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 651              		.loc 1 265 5 is_stmt 0 discriminator 1 view .LVU211
+ 652 020c 02EBCC02 		add	r2, r2, ip, lsl #3
+ 653              	.LVL69:
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 654              		.loc 1 265 5 is_stmt 1 discriminator 1 view .LVU212
+ 655 0210 B1F808C0 		ldrh	ip, [r1, #8]
+ 656 0214 4FEA5C0C 		lsr	ip, ip, #1
+ 657 0218 4FEA4C0C 		lsl	ip, ip, #1
+ 658 021c A2F800C4 		strh	ip, [r2, #1024]	@ movhi
+ 659              	.LBE17:
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 660              		.loc 1 265 5 discriminator 1 view .LVU213
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 661              		.loc 1 265 5 discriminator 1 view .LVU214
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 662              		.loc 1 265 5 discriminator 1 view .LVU215
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 663              		.loc 1 265 5 discriminator 1 view .LVU216
+ 664              	.LBB18:
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 665              		.loc 1 265 5 discriminator 1 view .LVU217
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 666              		.loc 1 265 5 discriminator 1 view .LVU218
+ 667              	.LVL70:
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 668              		.loc 1 265 5 discriminator 1 view .LVU219
+ 669 0220 B3F85020 		ldrh	r2, [r3, #80]
+ 670              	.LVL71:
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 671              		.loc 1 265 5 is_stmt 0 discriminator 1 view .LVU220
+ 672 0224 13FA82F2 		uxtah	r2, r3, r2
+ 673              	.LVL72:
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 674              		.loc 1 265 5 is_stmt 1 discriminator 1 view .LVU221
+ 675 0228 91F800C0 		ldrb	ip, [r1]	@ zero_extendqisi2
+ 676 022c 02EBCC02 		add	r2, r2, ip, lsl #3
+ 677              	.LVL73:
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 678              		.loc 1 265 5 discriminator 1 view .LVU222
+ 679 0230 B1F80AC0 		ldrh	ip, [r1, #10]
+ 680 0234 4FEA5C0C 		lsr	ip, ip, #1
+ 681 0238 4FEA4C0C 		lsl	ip, ip, #1
+ 682 023c A2F804C4 		strh	ip, [r2, #1028]	@ movhi
+ 683              	.LBE18:
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 684              		.loc 1 265 5 discriminator 1 view .LVU223
+ARM GAS  /tmp/cc2t6zYn.s 			page 19
+
+
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 685              		.loc 1 265 5 discriminator 1 view .LVU224
+ 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 686              		.loc 1 265 5 discriminator 1 view .LVU225
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 687              		.loc 1 267 5 discriminator 1 view .LVU226
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 688              		.loc 1 267 11 is_stmt 0 discriminator 1 view .LVU227
+ 689 0240 4A78     		ldrb	r2, [r1, #1]	@ zero_extendqisi2
+ 690              	.LVL74:
+ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 691              		.loc 1 267 8 discriminator 1 view .LVU228
+ 692 0242 002A     		cmp	r2, #0
+ 693 0244 50D1     		bne	.L28
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 694              		.loc 1 270 7 is_stmt 1 view .LVU229
+ 695              	.LBB19:
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 696              		.loc 1 270 7 view .LVU230
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 697              		.loc 1 270 7 view .LVU231
+ 698 0246 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 699 0248 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 700              	.LVL75:
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 701              		.loc 1 270 7 view .LVU232
+ 702 024c 12F4804F 		tst	r2, #16384
+ 703 0250 0CD0     		beq	.L29
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 704              		.loc 1 270 7 discriminator 1 view .LVU233
+ 705              	.LBB20:
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 706              		.loc 1 270 7 discriminator 1 view .LVU234
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 707              		.loc 1 270 7 discriminator 1 view .LVU235
+ 708 0252 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 709              	.LVL76:
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 710              		.loc 1 270 7 is_stmt 0 discriminator 1 view .LVU236
+ 711 0256 92B2     		uxth	r2, r2
+ 712 0258 22F4E042 		bic	r2, r2, #28672
+ 713 025c 22F07002 		bic	r2, r2, #112
+ 714              	.LVL77:
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 715              		.loc 1 270 7 is_stmt 1 discriminator 1 view .LVU237
+ 716 0260 42F44042 		orr	r2, r2, #49152
+ 717              	.LVL78:
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 718              		.loc 1 270 7 is_stmt 0 discriminator 1 view .LVU238
+ 719 0264 42F08002 		orr	r2, r2, #128
+ 720 0268 23F82420 		strh	r2, [r3, r4, lsl #2]	@ movhi
+ 721              	.LVL79:
+ 722              	.L29:
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 723              		.loc 1 270 7 discriminator 1 view .LVU239
+ 724              	.LBE20:
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ARM GAS  /tmp/cc2t6zYn.s 			page 20
+
+
+ 725              		.loc 1 270 7 is_stmt 1 discriminator 3 view .LVU240
+ 726              	.LBE19:
+ 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 727              		.loc 1 270 7 discriminator 3 view .LVU241
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 728              		.loc 1 271 7 discriminator 3 view .LVU242
+ 729              	.LBB21:
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 730              		.loc 1 271 7 discriminator 3 view .LVU243
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 731              		.loc 1 271 7 discriminator 3 view .LVU244
+ 732 026c 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 733 026e 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 734              	.LVL80:
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 735              		.loc 1 271 7 discriminator 3 view .LVU245
+ 736 0272 12F0400F 		tst	r2, #64
+ 737 0276 0CD0     		beq	.L30
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 738              		.loc 1 271 7 discriminator 1 view .LVU246
+ 739              	.LBB22:
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 740              		.loc 1 271 7 discriminator 1 view .LVU247
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 741              		.loc 1 271 7 discriminator 1 view .LVU248
+ 742 0278 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 743              	.LVL81:
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 744              		.loc 1 271 7 is_stmt 0 discriminator 1 view .LVU249
+ 745 027c 92B2     		uxth	r2, r2
+ 746 027e 22F4E042 		bic	r2, r2, #28672
+ 747 0282 22F07002 		bic	r2, r2, #112
+ 748              	.LVL82:
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 749              		.loc 1 271 7 is_stmt 1 discriminator 1 view .LVU250
+ 750 0286 42F40042 		orr	r2, r2, #32768
+ 751              	.LVL83:
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 752              		.loc 1 271 7 is_stmt 0 discriminator 1 view .LVU251
+ 753 028a 42F0C002 		orr	r2, r2, #192
+ 754 028e 23F82420 		strh	r2, [r3, r4, lsl #2]	@ movhi
+ 755              	.LVL84:
+ 756              	.L30:
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 757              		.loc 1 271 7 discriminator 1 view .LVU252
+ 758              	.LBE22:
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 759              		.loc 1 271 7 is_stmt 1 discriminator 3 view .LVU253
+ 760              	.LBE21:
+ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 761              		.loc 1 271 7 discriminator 3 view .LVU254
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 762              		.loc 1 273 7 discriminator 3 view .LVU255
+ 763              	.LBB23:
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 764              		.loc 1 273 7 discriminator 3 view .LVU256
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ARM GAS  /tmp/cc2t6zYn.s 			page 21
+
+
+ 765              		.loc 1 273 7 discriminator 3 view .LVU257
+ 766 0292 91F800C0 		ldrb	ip, [r1]	@ zero_extendqisi2
+ 767 0296 33F82C20 		ldrh	r2, [r3, ip, lsl #2]
+ 768 029a 92B2     		uxth	r2, r2
+ 769 029c 22F48042 		bic	r2, r2, #16384
+ 770 02a0 22F07002 		bic	r2, r2, #112
+ 771              	.LVL85:
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 772              		.loc 1 273 7 discriminator 3 view .LVU258
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 773              		.loc 1 273 7 discriminator 3 view .LVU259
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 774              		.loc 1 273 7 discriminator 3 view .LVU260
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 775              		.loc 1 273 7 discriminator 3 view .LVU261
+ 776 02a4 82F44052 		eor	r2, r2, #12288
+ 777              	.LVL86:
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 778              		.loc 1 273 7 discriminator 3 view .LVU262
+ 779 02a8 48F28004 		movw	r4, #32896
+ 780 02ac 2243     		orrs	r2, r2, r4
+ 781              	.LVL87:
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 782              		.loc 1 273 7 is_stmt 0 discriminator 3 view .LVU263
+ 783 02ae 23F82C20 		strh	r2, [r3, ip, lsl #2]	@ movhi
+ 784              	.LBE23:
+ 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 785              		.loc 1 273 7 is_stmt 1 discriminator 3 view .LVU264
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 786              		.loc 1 274 7 discriminator 3 view .LVU265
+ 787              	.LBB24:
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 788              		.loc 1 274 7 discriminator 3 view .LVU266
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 789              		.loc 1 274 7 discriminator 3 view .LVU267
+ 790 02b2 0978     		ldrb	r1, [r1]	@ zero_extendqisi2
+ 791              	.LVL88:
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 792              		.loc 1 274 7 is_stmt 0 discriminator 3 view .LVU268
+ 793 02b4 33F82120 		ldrh	r2, [r3, r1, lsl #2]
+ 794 02b8 92B2     		uxth	r2, r2
+ 795 02ba 22F4E042 		bic	r2, r2, #28672
+ 796 02be 22F04002 		bic	r2, r2, #64
+ 797              	.LVL89:
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 798              		.loc 1 274 7 is_stmt 1 discriminator 3 view .LVU269
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 799              		.loc 1 274 7 discriminator 3 view .LVU270
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 800              		.loc 1 274 7 discriminator 3 view .LVU271
+ 801 02c2 2243     		orrs	r2, r2, r4
+ 802              	.LVL90:
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 803              		.loc 1 274 7 is_stmt 0 discriminator 3 view .LVU272
+ 804 02c4 23F82120 		strh	r2, [r3, r1, lsl #2]	@ movhi
+ 805              	.LBE24:
+ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ARM GAS  /tmp/cc2t6zYn.s 			page 22
+
+
+ 806              		.loc 1 274 7 is_stmt 1 discriminator 3 view .LVU273
+ 807 02c8 67E7     		b	.L19
+ 808              	.LVL91:
+ 809              	.L37:
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 810              		.loc 1 256 7 view .LVU274
+ 811              	.LBB25:
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 812              		.loc 1 256 7 view .LVU275
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 813              		.loc 1 256 7 view .LVU276
+ 814 02ca 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 815 02cc 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 816 02d0 92B2     		uxth	r2, r2
+ 817 02d2 22F4E042 		bic	r2, r2, #28672
+ 818 02d6 22F07002 		bic	r2, r2, #112
+ 819              	.LVL92:
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 820              		.loc 1 256 7 view .LVU277
+ 821 02da 42F40142 		orr	r2, r2, #33024
+ 822              	.LVL93:
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 823              		.loc 1 256 7 is_stmt 0 view .LVU278
+ 824 02de 42F08002 		orr	r2, r2, #128
+ 825 02e2 23F82420 		strh	r2, [r3, r4, lsl #2]	@ movhi
+ 826              	.LBE25:
+ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 827              		.loc 1 256 7 is_stmt 1 view .LVU279
+ 828 02e6 8BE7     		b	.L27
+ 829              	.LVL94:
+ 830              	.L28:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 831              		.loc 1 279 7 view .LVU280
+ 832              	.LBB26:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 833              		.loc 1 279 7 view .LVU281
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 834              		.loc 1 279 7 view .LVU282
+ 835 02e8 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 836 02ea 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 837              	.LVL95:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 838              		.loc 1 279 7 view .LVU283
+ 839 02ee 12F4804F 		tst	r2, #16384
+ 840 02f2 0CD0     		beq	.L31
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 841              		.loc 1 279 7 discriminator 1 view .LVU284
+ 842              	.LBB27:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 843              		.loc 1 279 7 discriminator 1 view .LVU285
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 844              		.loc 1 279 7 discriminator 1 view .LVU286
+ 845 02f4 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 846              	.LVL96:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 847              		.loc 1 279 7 is_stmt 0 discriminator 1 view .LVU287
+ 848 02f8 92B2     		uxth	r2, r2
+ARM GAS  /tmp/cc2t6zYn.s 			page 23
+
+
+ 849 02fa 22F4E042 		bic	r2, r2, #28672
+ 850 02fe 22F07002 		bic	r2, r2, #112
+ 851              	.LVL97:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 852              		.loc 1 279 7 is_stmt 1 discriminator 1 view .LVU288
+ 853 0302 42F44042 		orr	r2, r2, #49152
+ 854              	.LVL98:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 855              		.loc 1 279 7 is_stmt 0 discriminator 1 view .LVU289
+ 856 0306 42F08002 		orr	r2, r2, #128
+ 857 030a 23F82420 		strh	r2, [r3, r4, lsl #2]	@ movhi
+ 858              	.LVL99:
+ 859              	.L31:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 860              		.loc 1 279 7 discriminator 1 view .LVU290
+ 861              	.LBE27:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 862              		.loc 1 279 7 is_stmt 1 discriminator 3 view .LVU291
+ 863              	.LBE26:
+ 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 864              		.loc 1 279 7 discriminator 3 view .LVU292
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 865              		.loc 1 280 7 discriminator 3 view .LVU293
+ 866              	.LBB28:
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 867              		.loc 1 280 7 discriminator 3 view .LVU294
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 868              		.loc 1 280 7 discriminator 3 view .LVU295
+ 869 030e 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 870 0310 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 871              	.LVL100:
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 872              		.loc 1 280 7 discriminator 3 view .LVU296
+ 873 0314 12F0400F 		tst	r2, #64
+ 874 0318 0CD0     		beq	.L32
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 875              		.loc 1 280 7 discriminator 1 view .LVU297
+ 876              	.LBB29:
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 877              		.loc 1 280 7 discriminator 1 view .LVU298
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 878              		.loc 1 280 7 discriminator 1 view .LVU299
+ 879 031a 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 880              	.LVL101:
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 881              		.loc 1 280 7 is_stmt 0 discriminator 1 view .LVU300
+ 882 031e 92B2     		uxth	r2, r2
+ 883 0320 22F4E042 		bic	r2, r2, #28672
+ 884 0324 22F07002 		bic	r2, r2, #112
+ 885              	.LVL102:
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 886              		.loc 1 280 7 is_stmt 1 discriminator 1 view .LVU301
+ 887 0328 42F40042 		orr	r2, r2, #32768
+ 888              	.LVL103:
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 889              		.loc 1 280 7 is_stmt 0 discriminator 1 view .LVU302
+ 890 032c 42F0C002 		orr	r2, r2, #192
+ARM GAS  /tmp/cc2t6zYn.s 			page 24
+
+
+ 891 0330 23F82420 		strh	r2, [r3, r4, lsl #2]	@ movhi
+ 892              	.LVL104:
+ 893              	.L32:
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 894              		.loc 1 280 7 discriminator 1 view .LVU303
+ 895              	.LBE29:
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 896              		.loc 1 280 7 is_stmt 1 discriminator 3 view .LVU304
+ 897              	.LBE28:
+ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 898              		.loc 1 280 7 discriminator 3 view .LVU305
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 899              		.loc 1 282 7 discriminator 3 view .LVU306
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 900              		.loc 1 282 13 is_stmt 0 discriminator 3 view .LVU307
+ 901 0334 CA78     		ldrb	r2, [r1, #3]	@ zero_extendqisi2
+ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 902              		.loc 1 282 10 discriminator 3 view .LVU308
+ 903 0336 012A     		cmp	r2, #1
+ 904 0338 1ED0     		beq	.L33
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 905              		.loc 1 285 9 is_stmt 1 view .LVU309
+ 906              	.LBB30:
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 907              		.loc 1 285 9 view .LVU310
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 908              		.loc 1 285 9 view .LVU311
+ 909 033a 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 910 033c 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 911 0340 92B2     		uxth	r2, r2
+ 912 0342 22F4E042 		bic	r2, r2, #28672
+ 913 0346 22F04002 		bic	r2, r2, #64
+ 914              	.LVL105:
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 915              		.loc 1 285 9 view .LVU312
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 916              		.loc 1 285 9 view .LVU313
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 917              		.loc 1 285 9 view .LVU314
+ 918 034a 82F02002 		eor	r2, r2, #32
+ 919              	.LVL106:
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 920              		.loc 1 285 9 view .LVU315
+ 921 034e 42F40042 		orr	r2, r2, #32768
+ 922              	.LVL107:
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 923              		.loc 1 285 9 is_stmt 0 view .LVU316
+ 924 0352 42F08002 		orr	r2, r2, #128
+ 925 0356 23F82420 		strh	r2, [r3, r4, lsl #2]	@ movhi
+ 926              	.LBE30:
+ 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 927              		.loc 1 285 9 is_stmt 1 view .LVU317
+ 928              	.LVL108:
+ 929              	.L34:
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 930              		.loc 1 290 9 discriminator 7 view .LVU318
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ARM GAS  /tmp/cc2t6zYn.s 			page 25
+
+
+ 931              		.loc 1 293 7 discriminator 7 view .LVU319
+ 932              	.LBB31:
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 933              		.loc 1 293 7 discriminator 7 view .LVU320
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 934              		.loc 1 293 7 discriminator 7 view .LVU321
+ 935 035a 0978     		ldrb	r1, [r1]	@ zero_extendqisi2
+ 936              	.LVL109:
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 937              		.loc 1 293 7 is_stmt 0 discriminator 7 view .LVU322
+ 938 035c 33F82120 		ldrh	r2, [r3, r1, lsl #2]
+ 939 0360 92B2     		uxth	r2, r2
+ 940 0362 22F48042 		bic	r2, r2, #16384
+ 941 0366 22F07002 		bic	r2, r2, #112
+ 942              	.LVL110:
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 943              		.loc 1 293 7 is_stmt 1 discriminator 7 view .LVU323
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 944              		.loc 1 293 7 discriminator 7 view .LVU324
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 945              		.loc 1 293 7 discriminator 7 view .LVU325
+ 946 036a 42F40042 		orr	r2, r2, #32768
+ 947              	.LVL111:
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 948              		.loc 1 293 7 is_stmt 0 discriminator 7 view .LVU326
+ 949 036e 42F08002 		orr	r2, r2, #128
+ 950 0372 23F82120 		strh	r2, [r3, r1, lsl #2]	@ movhi
+ 951 0376 10E7     		b	.L19
+ 952              	.LVL112:
+ 953              	.L33:
+ 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 954              		.loc 1 293 7 discriminator 7 view .LVU327
+ 955              	.LBE31:
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 956              		.loc 1 290 9 is_stmt 1 view .LVU328
+ 957              	.LBB32:
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 958              		.loc 1 290 9 view .LVU329
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 959              		.loc 1 290 9 view .LVU330
+ 960 0378 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 961 037a 33F82420 		ldrh	r2, [r3, r4, lsl #2]
+ 962 037e 92B2     		uxth	r2, r2
+ 963 0380 22F4E042 		bic	r2, r2, #28672
+ 964 0384 22F04002 		bic	r2, r2, #64
+ 965              	.LVL113:
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 966              		.loc 1 290 9 view .LVU331
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 967              		.loc 1 290 9 view .LVU332
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 968              		.loc 1 290 9 view .LVU333
+ 969 0388 42F40042 		orr	r2, r2, #32768
+ 970              	.LVL114:
+ 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 971              		.loc 1 290 9 is_stmt 0 view .LVU334
+ 972 038c 42F08002 		orr	r2, r2, #128
+ARM GAS  /tmp/cc2t6zYn.s 			page 26
+
+
+ 973 0390 23F82420 		strh	r2, [r3, r4, lsl #2]	@ movhi
+ 974 0394 E1E7     		b	.L34
+ 975              	.LBE32:
+ 976              		.cfi_endproc
+ 977              	.LFE334:
+ 979              		.section	.text.USB_DeactivateEndpoint,"ax",%progbits
+ 980              		.align	1
+ 981              		.global	USB_DeactivateEndpoint
+ 982              		.syntax unified
+ 983              		.thumb
+ 984              		.thumb_func
+ 986              	USB_DeactivateEndpoint:
+ 987              	.LVL115:
+ 988              	.LFB335:
+ 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  De-activate and de-initialize an endpoint
+ 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  ep pointer to endpoint structure
+ 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+ 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 989              		.loc 1 308 1 is_stmt 1 view -0
+ 990              		.cfi_startproc
+ 991              		@ args = 0, pretend = 0, frame = 0
+ 992              		@ frame_needed = 0, uses_anonymous_args = 0
+ 993              		@ link register save eliminated.
+ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   if (ep->doublebuffer == 0U)
+ 994              		.loc 1 309 3 view .LVU336
+ 995              		.loc 1 309 9 is_stmt 0 view .LVU337
+ 996 0000 0B7B     		ldrb	r3, [r1, #12]	@ zero_extendqisi2
+ 997              		.loc 1 309 6 view .LVU338
+ 998 0002 002B     		cmp	r3, #0
+ 999 0004 46D1     		bne	.L39
+ 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     if (ep->is_in != 0U)
+ 1000              		.loc 1 311 5 is_stmt 1 view .LVU339
+ 1001              		.loc 1 311 11 is_stmt 0 view .LVU340
+ 1002 0006 4B78     		ldrb	r3, [r1, #1]	@ zero_extendqisi2
+ 1003              		.loc 1 311 8 view .LVU341
+ 1004 0008 13B3     		cbz	r3, .L40
+ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1005              		.loc 1 313 7 is_stmt 1 view .LVU342
+ 1006              	.LBB33:
+ 1007              		.loc 1 313 7 view .LVU343
+ 1008              		.loc 1 313 7 view .LVU344
+ 1009 000a 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1010 000c 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1011              	.LVL116:
+ 1012              		.loc 1 313 7 view .LVU345
+ 1013 0010 13F0400F 		tst	r3, #64
+ 1014 0014 0CD0     		beq	.L41
+ 1015              		.loc 1 313 7 discriminator 1 view .LVU346
+ 1016              	.LBB34:
+ 1017              		.loc 1 313 7 discriminator 1 view .LVU347
+ARM GAS  /tmp/cc2t6zYn.s 			page 27
+
+
+ 1018              		.loc 1 313 7 discriminator 1 view .LVU348
+ 1019 0016 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1020              	.LVL117:
+ 1021              		.loc 1 313 7 is_stmt 0 discriminator 1 view .LVU349
+ 1022 001a 9BB2     		uxth	r3, r3
+ 1023 001c 23F4E043 		bic	r3, r3, #28672
+ 1024 0020 23F07003 		bic	r3, r3, #112
+ 1025              	.LVL118:
+ 1026              		.loc 1 313 7 is_stmt 1 discriminator 1 view .LVU350
+ 1027 0024 43F40043 		orr	r3, r3, #32768
+ 1028              	.LVL119:
+ 1029              		.loc 1 313 7 is_stmt 0 discriminator 1 view .LVU351
+ 1030 0028 43F0C003 		orr	r3, r3, #192
+ 1031 002c 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1032              	.LVL120:
+ 1033              	.L41:
+ 1034              		.loc 1 313 7 discriminator 1 view .LVU352
+ 1035              	.LBE34:
+ 1036              		.loc 1 313 7 is_stmt 1 discriminator 3 view .LVU353
+ 1037              	.LBE33:
+ 1038              		.loc 1 313 7 discriminator 3 view .LVU354
+ 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Configure DISABLE status for the Endpoint */
+ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 1039              		.loc 1 316 7 discriminator 3 view .LVU355
+ 1040              	.LBB35:
+ 1041              		.loc 1 316 7 discriminator 3 view .LVU356
+ 1042              		.loc 1 316 7 discriminator 3 view .LVU357
+ 1043 0030 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1044 0032 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1045 0036 9BB2     		uxth	r3, r3
+ 1046 0038 23F4E043 		bic	r3, r3, #28672
+ 1047 003c 23F04003 		bic	r3, r3, #64
+ 1048              	.LVL121:
+ 1049              		.loc 1 316 7 discriminator 3 view .LVU358
+ 1050              		.loc 1 316 7 discriminator 3 view .LVU359
+ 1051              		.loc 1 316 7 discriminator 3 view .LVU360
+ 1052 0040 43F40043 		orr	r3, r3, #32768
+ 1053              	.LVL122:
+ 1054              		.loc 1 316 7 is_stmt 0 discriminator 3 view .LVU361
+ 1055 0044 43F08003 		orr	r3, r3, #128
+ 1056 0048 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1057              	.LBE35:
+ 1058              		.loc 1 316 7 is_stmt 1 discriminator 3 view .LVU362
+ 1059              	.LVL123:
+ 1060              	.L42:
+ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     else
+ 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Configure DISABLE status for the Endpoint */
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #if (USE_USB_DOUBLE_BUFFER == 1U)
+ARM GAS  /tmp/cc2t6zYn.s 			page 28
+
+
+ 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Double Buffer */
+ 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   else
+ 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     if (ep->is_in == 0U)
+ 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Clear the data toggle bits for the endpoint IN/OUT*/
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Reset value of the data toggle bits for the endpoint out*/
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_TX_DTOG(USBx, ep->num);
+ 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     else
+ 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Clear the data toggle bits for the endpoint IN/OUT*/
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Configure DISABLE status for the Endpoint*/
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ 1061              		.loc 1 352 7 discriminator 7 view .LVU363
+ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ 1062              		.loc 1 357 3 discriminator 7 view .LVU364
+ 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 1063              		.loc 1 358 1 is_stmt 0 discriminator 7 view .LVU365
+ 1064 004c 0020     		movs	r0, #0
+ 1065              	.LVL124:
+ 1066              		.loc 1 358 1 discriminator 7 view .LVU366
+ 1067 004e 7047     		bx	lr
+ 1068              	.LVL125:
+ 1069              	.L40:
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1070              		.loc 1 321 7 is_stmt 1 view .LVU367
+ 1071              	.LBB36:
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1072              		.loc 1 321 7 view .LVU368
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1073              		.loc 1 321 7 view .LVU369
+ 1074 0050 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1075 0052 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1076              	.LVL126:
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1077              		.loc 1 321 7 view .LVU370
+ 1078 0056 13F4804F 		tst	r3, #16384
+ 1079 005a 0CD0     		beq	.L43
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1080              		.loc 1 321 7 discriminator 1 view .LVU371
+ 1081              	.LBB37:
+ARM GAS  /tmp/cc2t6zYn.s 			page 29
+
+
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1082              		.loc 1 321 7 discriminator 1 view .LVU372
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1083              		.loc 1 321 7 discriminator 1 view .LVU373
+ 1084 005c 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1085              	.LVL127:
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1086              		.loc 1 321 7 is_stmt 0 discriminator 1 view .LVU374
+ 1087 0060 9BB2     		uxth	r3, r3
+ 1088 0062 23F4E043 		bic	r3, r3, #28672
+ 1089 0066 23F07003 		bic	r3, r3, #112
+ 1090              	.LVL128:
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1091              		.loc 1 321 7 is_stmt 1 discriminator 1 view .LVU375
+ 1092 006a 43F44043 		orr	r3, r3, #49152
+ 1093              	.LVL129:
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1094              		.loc 1 321 7 is_stmt 0 discriminator 1 view .LVU376
+ 1095 006e 43F08003 		orr	r3, r3, #128
+ 1096 0072 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1097              	.LVL130:
+ 1098              	.L43:
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1099              		.loc 1 321 7 discriminator 1 view .LVU377
+ 1100              	.LBE37:
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1101              		.loc 1 321 7 is_stmt 1 discriminator 3 view .LVU378
+ 1102              	.LBE36:
+ 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1103              		.loc 1 321 7 discriminator 3 view .LVU379
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1104              		.loc 1 324 7 discriminator 3 view .LVU380
+ 1105              	.LBB38:
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1106              		.loc 1 324 7 discriminator 3 view .LVU381
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1107              		.loc 1 324 7 discriminator 3 view .LVU382
+ 1108 0076 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1109 0078 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1110 007c 9BB2     		uxth	r3, r3
+ 1111 007e 23F48043 		bic	r3, r3, #16384
+ 1112 0082 23F07003 		bic	r3, r3, #112
+ 1113              	.LVL131:
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1114              		.loc 1 324 7 discriminator 3 view .LVU383
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1115              		.loc 1 324 7 discriminator 3 view .LVU384
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1116              		.loc 1 324 7 discriminator 3 view .LVU385
+ 1117 0086 43F40043 		orr	r3, r3, #32768
+ 1118              	.LVL132:
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1119              		.loc 1 324 7 is_stmt 0 discriminator 3 view .LVU386
+ 1120 008a 43F08003 		orr	r3, r3, #128
+ 1121 008e 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1122 0092 DBE7     		b	.L42
+ 1123              	.LVL133:
+ARM GAS  /tmp/cc2t6zYn.s 			page 30
+
+
+ 1124              	.L39:
+ 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1125              		.loc 1 324 7 discriminator 3 view .LVU387
+ 1126              	.LBE38:
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 1127              		.loc 1 331 5 is_stmt 1 view .LVU388
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 1128              		.loc 1 331 11 is_stmt 0 view .LVU389
+ 1129 0094 4B78     		ldrb	r3, [r1, #1]	@ zero_extendqisi2
+ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 1130              		.loc 1 331 8 view .LVU390
+ 1131 0096 002B     		cmp	r3, #0
+ 1132 0098 4ED1     		bne	.L44
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1133              		.loc 1 334 7 is_stmt 1 view .LVU391
+ 1134              	.LBB39:
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1135              		.loc 1 334 7 view .LVU392
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1136              		.loc 1 334 7 view .LVU393
+ 1137 009a 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1138 009c 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1139              	.LVL134:
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1140              		.loc 1 334 7 view .LVU394
+ 1141 00a0 13F4804F 		tst	r3, #16384
+ 1142 00a4 0CD0     		beq	.L45
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1143              		.loc 1 334 7 discriminator 1 view .LVU395
+ 1144              	.LBB40:
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1145              		.loc 1 334 7 discriminator 1 view .LVU396
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1146              		.loc 1 334 7 discriminator 1 view .LVU397
+ 1147 00a6 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1148              	.LVL135:
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1149              		.loc 1 334 7 is_stmt 0 discriminator 1 view .LVU398
+ 1150 00aa 9BB2     		uxth	r3, r3
+ 1151 00ac 23F4E043 		bic	r3, r3, #28672
+ 1152 00b0 23F07003 		bic	r3, r3, #112
+ 1153              	.LVL136:
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1154              		.loc 1 334 7 is_stmt 1 discriminator 1 view .LVU399
+ 1155 00b4 43F44043 		orr	r3, r3, #49152
+ 1156              	.LVL137:
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1157              		.loc 1 334 7 is_stmt 0 discriminator 1 view .LVU400
+ 1158 00b8 43F08003 		orr	r3, r3, #128
+ 1159 00bc 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1160              	.LVL138:
+ 1161              	.L45:
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1162              		.loc 1 334 7 discriminator 1 view .LVU401
+ 1163              	.LBE40:
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1164              		.loc 1 334 7 is_stmt 1 discriminator 3 view .LVU402
+ARM GAS  /tmp/cc2t6zYn.s 			page 31
+
+
+ 1165              	.LBE39:
+ 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1166              		.loc 1 334 7 discriminator 3 view .LVU403
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1167              		.loc 1 335 7 discriminator 3 view .LVU404
+ 1168              	.LBB41:
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1169              		.loc 1 335 7 discriminator 3 view .LVU405
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1170              		.loc 1 335 7 discriminator 3 view .LVU406
+ 1171 00c0 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1172 00c2 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1173              	.LVL139:
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1174              		.loc 1 335 7 discriminator 3 view .LVU407
+ 1175 00c6 13F0400F 		tst	r3, #64
+ 1176 00ca 0CD0     		beq	.L46
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1177              		.loc 1 335 7 discriminator 1 view .LVU408
+ 1178              	.LBB42:
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1179              		.loc 1 335 7 discriminator 1 view .LVU409
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1180              		.loc 1 335 7 discriminator 1 view .LVU410
+ 1181 00cc 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1182              	.LVL140:
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1183              		.loc 1 335 7 is_stmt 0 discriminator 1 view .LVU411
+ 1184 00d0 9BB2     		uxth	r3, r3
+ 1185 00d2 23F4E043 		bic	r3, r3, #28672
+ 1186 00d6 23F07003 		bic	r3, r3, #112
+ 1187              	.LVL141:
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1188              		.loc 1 335 7 is_stmt 1 discriminator 1 view .LVU412
+ 1189 00da 43F40043 		orr	r3, r3, #32768
+ 1190              	.LVL142:
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1191              		.loc 1 335 7 is_stmt 0 discriminator 1 view .LVU413
+ 1192 00de 43F0C003 		orr	r3, r3, #192
+ 1193 00e2 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1194              	.LVL143:
+ 1195              	.L46:
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1196              		.loc 1 335 7 discriminator 1 view .LVU414
+ 1197              	.LBE42:
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1198              		.loc 1 335 7 is_stmt 1 discriminator 3 view .LVU415
+ 1199              	.LBE41:
+ 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1200              		.loc 1 335 7 discriminator 3 view .LVU416
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1201              		.loc 1 338 7 discriminator 3 view .LVU417
+ 1202              	.LBB43:
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1203              		.loc 1 338 7 discriminator 3 view .LVU418
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1204              		.loc 1 338 7 discriminator 3 view .LVU419
+ARM GAS  /tmp/cc2t6zYn.s 			page 32
+
+
+ 1205 00e6 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1206 00e8 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1207 00ec 9BB2     		uxth	r3, r3
+ 1208 00ee 23F4E043 		bic	r3, r3, #28672
+ 1209 00f2 23F07003 		bic	r3, r3, #112
+ 1210              	.LVL144:
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1211              		.loc 1 338 7 discriminator 3 view .LVU420
+ 1212 00f6 43F40043 		orr	r3, r3, #32768
+ 1213              	.LVL145:
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1214              		.loc 1 338 7 is_stmt 0 discriminator 3 view .LVU421
+ 1215 00fa 43F0C003 		orr	r3, r3, #192
+ 1216 00fe 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1217              	.LBE43:
+ 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1218              		.loc 1 338 7 is_stmt 1 discriminator 3 view .LVU422
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 1219              		.loc 1 340 7 discriminator 3 view .LVU423
+ 1220              	.LBB44:
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 1221              		.loc 1 340 7 discriminator 3 view .LVU424
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 1222              		.loc 1 340 7 discriminator 3 view .LVU425
+ 1223 0102 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1224 0104 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1225 0108 9BB2     		uxth	r3, r3
+ 1226 010a 23F48043 		bic	r3, r3, #16384
+ 1227 010e 23F07003 		bic	r3, r3, #112
+ 1228              	.LVL146:
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 1229              		.loc 1 340 7 discriminator 3 view .LVU426
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 1230              		.loc 1 340 7 discriminator 3 view .LVU427
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 1231              		.loc 1 340 7 discriminator 3 view .LVU428
+ 1232 0112 48F2800C 		movw	ip, #32896
+ 1233 0116 43EA0C03 		orr	r3, r3, ip
+ 1234              	.LVL147:
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 1235              		.loc 1 340 7 is_stmt 0 discriminator 3 view .LVU429
+ 1236 011a 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1237              	.LBE44:
+ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ 1238              		.loc 1 340 7 is_stmt 1 discriminator 3 view .LVU430
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1239              		.loc 1 341 7 discriminator 3 view .LVU431
+ 1240              	.LBB45:
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1241              		.loc 1 341 7 discriminator 3 view .LVU432
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1242              		.loc 1 341 7 discriminator 3 view .LVU433
+ 1243 011e 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1244 0120 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1245 0124 9BB2     		uxth	r3, r3
+ 1246 0126 23F4E043 		bic	r3, r3, #28672
+ 1247 012a 23F04003 		bic	r3, r3, #64
+ARM GAS  /tmp/cc2t6zYn.s 			page 33
+
+
+ 1248              	.LVL148:
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1249              		.loc 1 341 7 discriminator 3 view .LVU434
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1250              		.loc 1 341 7 discriminator 3 view .LVU435
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1251              		.loc 1 341 7 discriminator 3 view .LVU436
+ 1252 012e 43EA0C03 		orr	r3, r3, ip
+ 1253              	.LVL149:
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1254              		.loc 1 341 7 is_stmt 0 discriminator 3 view .LVU437
+ 1255 0132 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1256              	.LBE45:
+ 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1257              		.loc 1 341 7 is_stmt 1 discriminator 3 view .LVU438
+ 1258 0136 89E7     		b	.L42
+ 1259              	.LVL150:
+ 1260              	.L44:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1261              		.loc 1 346 7 view .LVU439
+ 1262              	.LBB46:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1263              		.loc 1 346 7 view .LVU440
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1264              		.loc 1 346 7 view .LVU441
+ 1265 0138 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1266 013a 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1267              	.LVL151:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1268              		.loc 1 346 7 view .LVU442
+ 1269 013e 13F4804F 		tst	r3, #16384
+ 1270 0142 0CD0     		beq	.L47
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1271              		.loc 1 346 7 discriminator 1 view .LVU443
+ 1272              	.LBB47:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1273              		.loc 1 346 7 discriminator 1 view .LVU444
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1274              		.loc 1 346 7 discriminator 1 view .LVU445
+ 1275 0144 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1276              	.LVL152:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1277              		.loc 1 346 7 is_stmt 0 discriminator 1 view .LVU446
+ 1278 0148 9BB2     		uxth	r3, r3
+ 1279 014a 23F4E043 		bic	r3, r3, #28672
+ 1280 014e 23F07003 		bic	r3, r3, #112
+ 1281              	.LVL153:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1282              		.loc 1 346 7 is_stmt 1 discriminator 1 view .LVU447
+ 1283 0152 43F44043 		orr	r3, r3, #49152
+ 1284              	.LVL154:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1285              		.loc 1 346 7 is_stmt 0 discriminator 1 view .LVU448
+ 1286 0156 43F08003 		orr	r3, r3, #128
+ 1287 015a 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1288              	.LVL155:
+ 1289              	.L47:
+ARM GAS  /tmp/cc2t6zYn.s 			page 34
+
+
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1290              		.loc 1 346 7 discriminator 1 view .LVU449
+ 1291              	.LBE47:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1292              		.loc 1 346 7 is_stmt 1 discriminator 3 view .LVU450
+ 1293              	.LBE46:
+ 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1294              		.loc 1 346 7 discriminator 3 view .LVU451
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1295              		.loc 1 347 7 discriminator 3 view .LVU452
+ 1296              	.LBB48:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1297              		.loc 1 347 7 discriminator 3 view .LVU453
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1298              		.loc 1 347 7 discriminator 3 view .LVU454
+ 1299 015e 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1300 0160 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1301              	.LVL156:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1302              		.loc 1 347 7 discriminator 3 view .LVU455
+ 1303 0164 13F0400F 		tst	r3, #64
+ 1304 0168 0CD0     		beq	.L48
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1305              		.loc 1 347 7 discriminator 1 view .LVU456
+ 1306              	.LBB49:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1307              		.loc 1 347 7 discriminator 1 view .LVU457
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1308              		.loc 1 347 7 discriminator 1 view .LVU458
+ 1309 016a 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1310              	.LVL157:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1311              		.loc 1 347 7 is_stmt 0 discriminator 1 view .LVU459
+ 1312 016e 9BB2     		uxth	r3, r3
+ 1313 0170 23F4E043 		bic	r3, r3, #28672
+ 1314 0174 23F07003 		bic	r3, r3, #112
+ 1315              	.LVL158:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1316              		.loc 1 347 7 is_stmt 1 discriminator 1 view .LVU460
+ 1317 0178 43F40043 		orr	r3, r3, #32768
+ 1318              	.LVL159:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1319              		.loc 1 347 7 is_stmt 0 discriminator 1 view .LVU461
+ 1320 017c 43F0C003 		orr	r3, r3, #192
+ 1321 0180 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1322              	.LVL160:
+ 1323              	.L48:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1324              		.loc 1 347 7 discriminator 1 view .LVU462
+ 1325              	.LBE49:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1326              		.loc 1 347 7 is_stmt 1 discriminator 3 view .LVU463
+ 1327              	.LBE48:
+ 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_RX_DTOG(USBx, ep->num);
+ 1328              		.loc 1 347 7 discriminator 3 view .LVU464
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1329              		.loc 1 348 7 discriminator 3 view .LVU465
+ARM GAS  /tmp/cc2t6zYn.s 			page 35
+
+
+ 1330              	.LBB50:
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1331              		.loc 1 348 7 discriminator 3 view .LVU466
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1332              		.loc 1 348 7 discriminator 3 view .LVU467
+ 1333 0184 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1334 0186 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1335 018a 9BB2     		uxth	r3, r3
+ 1336 018c 23F4E043 		bic	r3, r3, #28672
+ 1337 0190 23F07003 		bic	r3, r3, #112
+ 1338              	.LVL161:
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1339              		.loc 1 348 7 discriminator 3 view .LVU468
+ 1340 0194 43F44043 		orr	r3, r3, #49152
+ 1341              	.LVL162:
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1342              		.loc 1 348 7 is_stmt 0 discriminator 3 view .LVU469
+ 1343 0198 43F08003 		orr	r3, r3, #128
+ 1344 019c 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1345              	.LBE50:
+ 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 1346              		.loc 1 348 7 is_stmt 1 discriminator 3 view .LVU470
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ 1347              		.loc 1 351 7 discriminator 3 view .LVU471
+ 1348              	.LBB51:
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ 1349              		.loc 1 351 7 discriminator 3 view .LVU472
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ 1350              		.loc 1 351 7 discriminator 3 view .LVU473
+ 1351 01a0 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1352 01a2 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1353 01a6 9BB2     		uxth	r3, r3
+ 1354 01a8 23F4E043 		bic	r3, r3, #28672
+ 1355 01ac 23F04003 		bic	r3, r3, #64
+ 1356              	.LVL163:
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ 1357              		.loc 1 351 7 discriminator 3 view .LVU474
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ 1358              		.loc 1 351 7 discriminator 3 view .LVU475
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ 1359              		.loc 1 351 7 discriminator 3 view .LVU476
+ 1360 01b0 48F2800C 		movw	ip, #32896
+ 1361 01b4 43EA0C03 		orr	r3, r3, ip
+ 1362              	.LVL164:
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ 1363              		.loc 1 351 7 is_stmt 0 discriminator 3 view .LVU477
+ 1364 01b8 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1365              	.LBE51:
+ 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ 1366              		.loc 1 351 7 is_stmt 1 discriminator 3 view .LVU478
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1367              		.loc 1 352 7 discriminator 3 view .LVU479
+ 1368              	.LBB52:
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1369              		.loc 1 352 7 discriminator 3 view .LVU480
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1370              		.loc 1 352 7 discriminator 3 view .LVU481
+ARM GAS  /tmp/cc2t6zYn.s 			page 36
+
+
+ 1371 01bc 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1372 01be 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1373 01c2 9BB2     		uxth	r3, r3
+ 1374 01c4 23F48043 		bic	r3, r3, #16384
+ 1375 01c8 23F07003 		bic	r3, r3, #112
+ 1376              	.LVL165:
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1377              		.loc 1 352 7 discriminator 3 view .LVU482
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1378              		.loc 1 352 7 discriminator 3 view .LVU483
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1379              		.loc 1 352 7 discriminator 3 view .LVU484
+ 1380 01cc 43EA0C03 		orr	r3, r3, ip
+ 1381              	.LVL166:
+ 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1382              		.loc 1 352 7 is_stmt 0 discriminator 3 view .LVU485
+ 1383 01d0 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1384 01d4 3AE7     		b	.L42
+ 1385              	.LBE52:
+ 1386              		.cfi_endproc
+ 1387              	.LFE335:
+ 1389              		.section	.text.USB_EPSetStall,"ax",%progbits
+ 1390              		.align	1
+ 1391              		.global	USB_EPSetStall
+ 1392              		.syntax unified
+ 1393              		.thumb
+ 1394              		.thumb_func
+ 1396              	USB_EPSetStall:
+ 1397              	.LVL167:
+ 1398              	.LFB337:
+ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_EPStartXfer setup and starts a transfer over an EP
+ 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  ep pointer to endpoint structure
+ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t len;
+ 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #if (USE_USB_DOUBLE_BUFFER == 1U)
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint16_t pmabuffer;
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint16_t wEPVal;
+ 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* IN endpoint */
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   if (ep->is_in == 1U)
+ 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     /*Multi packet transfer*/
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     if (ep->xfer_len > ep->maxpacket)
+ 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       len = ep->maxpacket;
+ 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     else
+ 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       len = ep->xfer_len;
+ 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ARM GAS  /tmp/cc2t6zYn.s 			page 37
+
+
+ 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     /* configure and validate Tx endpoint */
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     if (ep->doublebuffer == 0U)
+ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #if (USE_USB_DOUBLE_BUFFER == 1U)
+ 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     else
+ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* double buffer bulk management */
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       if (ep->type == EP_TYPE_BULK)
+ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         if (ep->xfer_len_db > ep->maxpacket)
+ 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           /* enable double buffer */
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           PCD_SET_BULK_EP_DBUF(USBx, ep->num);
+ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           /* each Time to write in PMA xfer_len_db will */
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           ep->xfer_len_db -= len;
+ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           /* Fill the two first buffer in the Buffer0 & Buffer1 */
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
+ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           {
+ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             /* Set the Double buffer counter for pmabuffer1 */
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             /* Write the user buffer to USB PMA */
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             ep->xfer_buff += len;
+ 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             if (ep->xfer_len_db > ep->maxpacket)
+ 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             {
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               ep->xfer_len_db -= len;
+ 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             }
+ 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             else
+ 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             {
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               len = ep->xfer_len_db;
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               ep->xfer_len_db = 0U;
+ 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             }
+ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             /* Set the Double buffer counter for pmabuffer0 */
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             /* Write the user buffer to USB PMA */
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           else
+ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           {
+ 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             /* Set the Double buffer counter for pmabuffer0 */
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             /* Write the user buffer to USB PMA */
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ARM GAS  /tmp/cc2t6zYn.s 			page 38
+
+
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             ep->xfer_buff += len;
+ 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             if (ep->xfer_len_db > ep->maxpacket)
+ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             {
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               ep->xfer_len_db -= len;
+ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             }
+ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             else
+ 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             {
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               len = ep->xfer_len_db;
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               ep->xfer_len_db = 0U;
+ 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             }
+ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             /* Set the Double buffer counter for pmabuffer1 */
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             /* Write the user buffer to USB PMA */
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         /* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer 
+ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         else
+ 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           len = ep->xfer_len_db;
+ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           /* disable double buffer mode for Bulk endpoint */
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
+ 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           /* Set Tx count with nbre of byte to be transmitted */
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           /* Write the user buffer to USB PMA */
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       else /* manage isochronous double buffer IN mode */
+ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         /* each Time to write in PMA xfer_len_db will */
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         ep->xfer_len_db -= len;
+ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         /* Fill the data buffer */
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
+ 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           /* Set the Double buffer counter for pmabuffer1 */
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           /* Write the user buffer to USB PMA */
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         else
+ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           /* Set the Double buffer counter for pmabuffer0 */
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ARM GAS  /tmp/cc2t6zYn.s 			page 39
+
+
+ 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           /* Write the user buffer to USB PMA */
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
+ 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   else /* OUT endpoint */
+ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     if (ep->doublebuffer == 0U)
+ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Multi packet transfer */
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       if (ep->xfer_len > ep->maxpacket)
+ 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         len = ep->maxpacket;
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         ep->xfer_len -= len;
+ 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       else
+ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         len = ep->xfer_len;
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         ep->xfer_len = 0U;
+ 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* configure and validate Rx endpoint */
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_CNT(USBx, ep->num, len);
+ 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #if (USE_USB_DOUBLE_BUFFER == 1U)
+ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     else
+ 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
+ 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Set the Double buffer counter */
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       if (ep->type == EP_TYPE_BULK)
+ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
+ 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         /* Coming from ISR */
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         if (ep->xfer_count != 0U)
+ 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           /* update last value to check if there is blocking state */
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
+ 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           /*Blocking State */
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
+ 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
+ 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           {
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
+ 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* iso out double */
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       else if (ep->type == EP_TYPE_ISOC)
+ 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         /* Multi packet transfer */
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         if (ep->xfer_len > ep->maxpacket)
+ 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           len = ep->maxpacket;
+ARM GAS  /tmp/cc2t6zYn.s 			page 40
+
+
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           ep->xfer_len -= len;
+ 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         else
+ 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           len = ep->xfer_len;
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           ep->xfer_len = 0U;
+ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
+ 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       else
+ 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         return HAL_ERROR;
+ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+ 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_EPSetStall set a stall condition over an EP
+ 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  ep pointer to endpoint structure
+ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+ 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 1399              		.loc 1 587 1 is_stmt 1 view -0
+ 1400              		.cfi_startproc
+ 1401              		@ args = 0, pretend = 0, frame = 0
+ 1402              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1403              		@ link register save eliminated.
+ 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   if (ep->is_in != 0U)
+ 1404              		.loc 1 588 3 view .LVU487
+ 1405              		.loc 1 588 9 is_stmt 0 view .LVU488
+ 1406 0000 4B78     		ldrb	r3, [r1, #1]	@ zero_extendqisi2
+ 1407              		.loc 1 588 6 view .LVU489
+ 1408 0002 8BB1     		cbz	r3, .L50
+ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
+ 1409              		.loc 1 590 5 is_stmt 1 view .LVU490
+ 1410              	.LBB53:
+ 1411              		.loc 1 590 5 view .LVU491
+ 1412              		.loc 1 590 5 view .LVU492
+ 1413 0004 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1414 0006 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1415 000a 9BB2     		uxth	r3, r3
+ 1416 000c 23F4E043 		bic	r3, r3, #28672
+ 1417 0010 23F04003 		bic	r3, r3, #64
+ 1418              	.LVL168:
+ 1419              		.loc 1 590 5 view .LVU493
+ 1420              		.loc 1 590 5 view .LVU494
+ 1421 0014 83F01003 		eor	r3, r3, #16
+ARM GAS  /tmp/cc2t6zYn.s 			page 41
+
+
+ 1422              	.LVL169:
+ 1423              		.loc 1 590 5 view .LVU495
+ 1424              		.loc 1 590 5 view .LVU496
+ 1425 0018 43F40043 		orr	r3, r3, #32768
+ 1426              	.LVL170:
+ 1427              		.loc 1 590 5 is_stmt 0 view .LVU497
+ 1428 001c 43F08003 		orr	r3, r3, #128
+ 1429 0020 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1430              	.LBE53:
+ 1431              		.loc 1 590 5 is_stmt 1 view .LVU498
+ 1432              	.LVL171:
+ 1433              	.L51:
+ 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   else
+ 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
+ 1434              		.loc 1 594 5 discriminator 7 view .LVU499
+ 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ 1435              		.loc 1 597 3 discriminator 7 view .LVU500
+ 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 1436              		.loc 1 598 1 is_stmt 0 discriminator 7 view .LVU501
+ 1437 0024 0020     		movs	r0, #0
+ 1438              	.LVL172:
+ 1439              		.loc 1 598 1 discriminator 7 view .LVU502
+ 1440 0026 7047     		bx	lr
+ 1441              	.LVL173:
+ 1442              	.L50:
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 1443              		.loc 1 594 5 is_stmt 1 view .LVU503
+ 1444              	.LBB54:
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 1445              		.loc 1 594 5 view .LVU504
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 1446              		.loc 1 594 5 view .LVU505
+ 1447 0028 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1448 002a 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1449 002e 9BB2     		uxth	r3, r3
+ 1450 0030 23F48043 		bic	r3, r3, #16384
+ 1451 0034 23F07003 		bic	r3, r3, #112
+ 1452              	.LVL174:
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 1453              		.loc 1 594 5 view .LVU506
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 1454              		.loc 1 594 5 view .LVU507
+ 1455 0038 83F48053 		eor	r3, r3, #4096
+ 1456              	.LVL175:
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 1457              		.loc 1 594 5 view .LVU508
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 1458              		.loc 1 594 5 view .LVU509
+ 1459 003c 43F40043 		orr	r3, r3, #32768
+ 1460              	.LVL176:
+ 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 1461              		.loc 1 594 5 is_stmt 0 view .LVU510
+ 1462 0040 43F08003 		orr	r3, r3, #128
+ARM GAS  /tmp/cc2t6zYn.s 			page 42
+
+
+ 1463 0044 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1464 0048 ECE7     		b	.L51
+ 1465              	.LBE54:
+ 1466              		.cfi_endproc
+ 1467              	.LFE337:
+ 1469              		.section	.text.USB_EPClearStall,"ax",%progbits
+ 1470              		.align	1
+ 1471              		.global	USB_EPClearStall
+ 1472              		.syntax unified
+ 1473              		.thumb
+ 1474              		.thumb_func
+ 1476              	USB_EPClearStall:
+ 1477              	.LVL177:
+ 1478              	.LFB338:
+ 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_EPClearStall Clear a stall condition over an EP
+ 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  ep pointer to endpoint structure
+ 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 1479              		.loc 1 607 1 is_stmt 1 view -0
+ 1480              		.cfi_startproc
+ 1481              		@ args = 0, pretend = 0, frame = 0
+ 1482              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1483              		@ link register save eliminated.
+ 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   if (ep->doublebuffer == 0U)
+ 1484              		.loc 1 608 3 view .LVU512
+ 1485              		.loc 1 608 9 is_stmt 0 view .LVU513
+ 1486 0000 0B7B     		ldrb	r3, [r1, #12]	@ zero_extendqisi2
+ 1487              		.loc 1 608 6 view .LVU514
+ 1488 0002 002B     		cmp	r3, #0
+ 1489 0004 4BD1     		bne	.L53
+ 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     if (ep->is_in != 0U)
+ 1490              		.loc 1 610 5 is_stmt 1 view .LVU515
+ 1491              		.loc 1 610 11 is_stmt 0 view .LVU516
+ 1492 0006 4B78     		ldrb	r3, [r1, #1]	@ zero_extendqisi2
+ 1493              		.loc 1 610 8 view .LVU517
+ 1494 0008 33B3     		cbz	r3, .L54
+ 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ 1495              		.loc 1 612 7 is_stmt 1 view .LVU518
+ 1496              	.LBB55:
+ 1497              		.loc 1 612 7 view .LVU519
+ 1498              		.loc 1 612 7 view .LVU520
+ 1499 000a 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1500 000c 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1501              	.LVL178:
+ 1502              		.loc 1 612 7 view .LVU521
+ 1503 0010 13F0400F 		tst	r3, #64
+ 1504 0014 0CD0     		beq	.L55
+ 1505              		.loc 1 612 7 discriminator 1 view .LVU522
+ 1506              	.LBB56:
+ 1507              		.loc 1 612 7 discriminator 1 view .LVU523
+ARM GAS  /tmp/cc2t6zYn.s 			page 43
+
+
+ 1508              		.loc 1 612 7 discriminator 1 view .LVU524
+ 1509 0016 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1510              	.LVL179:
+ 1511              		.loc 1 612 7 is_stmt 0 discriminator 1 view .LVU525
+ 1512 001a 9BB2     		uxth	r3, r3
+ 1513 001c 23F4E043 		bic	r3, r3, #28672
+ 1514 0020 23F07003 		bic	r3, r3, #112
+ 1515              	.LVL180:
+ 1516              		.loc 1 612 7 is_stmt 1 discriminator 1 view .LVU526
+ 1517 0024 43F40043 		orr	r3, r3, #32768
+ 1518              	.LVL181:
+ 1519              		.loc 1 612 7 is_stmt 0 discriminator 1 view .LVU527
+ 1520 0028 43F0C003 		orr	r3, r3, #192
+ 1521 002c 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1522              	.LVL182:
+ 1523              	.L55:
+ 1524              		.loc 1 612 7 discriminator 1 view .LVU528
+ 1525              	.LBE56:
+ 1526              		.loc 1 612 7 is_stmt 1 discriminator 3 view .LVU529
+ 1527              	.LBE55:
+ 1528              		.loc 1 612 7 discriminator 3 view .LVU530
+ 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       if (ep->type != EP_TYPE_ISOC)
+ 1529              		.loc 1 614 7 discriminator 3 view .LVU531
+ 1530              		.loc 1 614 13 is_stmt 0 discriminator 3 view .LVU532
+ 1531 0030 CB78     		ldrb	r3, [r1, #3]	@ zero_extendqisi2
+ 1532              		.loc 1 614 10 discriminator 3 view .LVU533
+ 1533 0032 012B     		cmp	r3, #1
+ 1534 0034 33D0     		beq	.L53
+ 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         /* Configure NAK status for the Endpoint */
+ 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ 1535              		.loc 1 617 9 is_stmt 1 view .LVU534
+ 1536              	.LBB57:
+ 1537              		.loc 1 617 9 view .LVU535
+ 1538              		.loc 1 617 9 view .LVU536
+ 1539 0036 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1540 0038 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1541 003c 9BB2     		uxth	r3, r3
+ 1542 003e 23F4E043 		bic	r3, r3, #28672
+ 1543 0042 23F04003 		bic	r3, r3, #64
+ 1544              	.LVL183:
+ 1545              		.loc 1 617 9 view .LVU537
+ 1546              		.loc 1 617 9 view .LVU538
+ 1547              		.loc 1 617 9 view .LVU539
+ 1548 0046 83F02003 		eor	r3, r3, #32
+ 1549              	.LVL184:
+ 1550              		.loc 1 617 9 view .LVU540
+ 1551 004a 43F40043 		orr	r3, r3, #32768
+ 1552              	.LVL185:
+ 1553              		.loc 1 617 9 is_stmt 0 view .LVU541
+ 1554 004e 43F08003 		orr	r3, r3, #128
+ 1555 0052 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1556 0056 22E0     		b	.L53
+ 1557              	.LVL186:
+ 1558              	.L54:
+ 1559              		.loc 1 617 9 view .LVU542
+ARM GAS  /tmp/cc2t6zYn.s 			page 44
+
+
+ 1560              	.LBE57:
+ 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     else
+ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ 1561              		.loc 1 622 7 is_stmt 1 view .LVU543
+ 1562              	.LBB58:
+ 1563              		.loc 1 622 7 view .LVU544
+ 1564              		.loc 1 622 7 view .LVU545
+ 1565 0058 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1566 005a 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1567              	.LVL187:
+ 1568              		.loc 1 622 7 view .LVU546
+ 1569 005e 13F4804F 		tst	r3, #16384
+ 1570 0062 0CD0     		beq	.L56
+ 1571              		.loc 1 622 7 discriminator 1 view .LVU547
+ 1572              	.LBB59:
+ 1573              		.loc 1 622 7 discriminator 1 view .LVU548
+ 1574              		.loc 1 622 7 discriminator 1 view .LVU549
+ 1575 0064 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1576              	.LVL188:
+ 1577              		.loc 1 622 7 is_stmt 0 discriminator 1 view .LVU550
+ 1578 0068 9BB2     		uxth	r3, r3
+ 1579 006a 23F4E043 		bic	r3, r3, #28672
+ 1580 006e 23F07003 		bic	r3, r3, #112
+ 1581              	.LVL189:
+ 1582              		.loc 1 622 7 is_stmt 1 discriminator 1 view .LVU551
+ 1583 0072 43F44043 		orr	r3, r3, #49152
+ 1584              	.LVL190:
+ 1585              		.loc 1 622 7 is_stmt 0 discriminator 1 view .LVU552
+ 1586 0076 43F08003 		orr	r3, r3, #128
+ 1587 007a 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1588              	.LVL191:
+ 1589              	.L56:
+ 1590              		.loc 1 622 7 discriminator 1 view .LVU553
+ 1591              	.LBE59:
+ 1592              		.loc 1 622 7 is_stmt 1 discriminator 3 view .LVU554
+ 1593              	.LBE58:
+ 1594              		.loc 1 622 7 discriminator 3 view .LVU555
+ 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       /* Configure VALID status for the Endpoint */
+ 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ 1595              		.loc 1 625 7 discriminator 3 view .LVU556
+ 1596              	.LBB60:
+ 1597              		.loc 1 625 7 discriminator 3 view .LVU557
+ 1598              		.loc 1 625 7 discriminator 3 view .LVU558
+ 1599 007e 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 1600 0080 30F82230 		ldrh	r3, [r0, r2, lsl #2]
+ 1601 0084 9BB2     		uxth	r3, r3
+ 1602 0086 23F48043 		bic	r3, r3, #16384
+ 1603 008a 23F07003 		bic	r3, r3, #112
+ 1604              	.LVL192:
+ 1605              		.loc 1 625 7 discriminator 3 view .LVU559
+ 1606              		.loc 1 625 7 discriminator 3 view .LVU560
+ 1607              		.loc 1 625 7 discriminator 3 view .LVU561
+ 1608              		.loc 1 625 7 discriminator 3 view .LVU562
+ARM GAS  /tmp/cc2t6zYn.s 			page 45
+
+
+ 1609 008e 83F44053 		eor	r3, r3, #12288
+ 1610              	.LVL193:
+ 1611              		.loc 1 625 7 discriminator 3 view .LVU563
+ 1612 0092 43F40043 		orr	r3, r3, #32768
+ 1613              	.LVL194:
+ 1614              		.loc 1 625 7 is_stmt 0 discriminator 3 view .LVU564
+ 1615 0096 43F08003 		orr	r3, r3, #128
+ 1616 009a 20F82230 		strh	r3, [r0, r2, lsl #2]	@ movhi
+ 1617              	.LVL195:
+ 1618              	.L53:
+ 1619              		.loc 1 625 7 discriminator 3 view .LVU565
+ 1620              	.LBE60:
+ 1621              		.loc 1 625 7 is_stmt 1 discriminator 7 view .LVU566
+ 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ 1622              		.loc 1 629 3 discriminator 7 view .LVU567
+ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 1623              		.loc 1 630 1 is_stmt 0 discriminator 7 view .LVU568
+ 1624 009e 0020     		movs	r0, #0
+ 1625              	.LVL196:
+ 1626              		.loc 1 630 1 discriminator 7 view .LVU569
+ 1627 00a0 7047     		bx	lr
+ 1628              		.cfi_endproc
+ 1629              	.LFE338:
+ 1631              		.section	.text.USB_StopDevice,"ax",%progbits
+ 1632              		.align	1
+ 1633              		.global	USB_StopDevice
+ 1634              		.syntax unified
+ 1635              		.thumb
+ 1636              		.thumb_func
+ 1638              	USB_StopDevice:
+ 1639              	.LVL197:
+ 1640              	.LFB339:
+ 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #endif /* defined (HAL_PCD_MODULE_ENABLED) */
+ 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_StopDevice Stop the usb device mode
+ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
+ 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 1641              		.loc 1 639 1 is_stmt 1 view -0
+ 1642              		.cfi_startproc
+ 1643              		@ args = 0, pretend = 0, frame = 0
+ 1644              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1645              		@ link register save eliminated.
+ 1646              		.loc 1 639 1 is_stmt 0 view .LVU571
+ 1647 0000 0346     		mov	r3, r0
+ 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* disable all interrupts and force USB reset */
+ 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->CNTR = (uint16_t)USB_CNTR_FRES;
+ 1648              		.loc 1 641 3 is_stmt 1 view .LVU572
+ 1649              		.loc 1 641 14 is_stmt 0 view .LVU573
+ 1650 0002 0122     		movs	r2, #1
+ 1651 0004 A0F84020 		strh	r2, [r0, #64]	@ movhi
+ARM GAS  /tmp/cc2t6zYn.s 			page 46
+
+
+ 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* clear interrupt status register */
+ 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->ISTR = 0U;
+ 1652              		.loc 1 644 3 is_stmt 1 view .LVU574
+ 1653              		.loc 1 644 14 is_stmt 0 view .LVU575
+ 1654 0008 0020     		movs	r0, #0
+ 1655              	.LVL198:
+ 1656              		.loc 1 644 14 view .LVU576
+ 1657 000a A3F84400 		strh	r0, [r3, #68]	@ movhi
+ 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* switch-off device */
+ 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
+ 1658              		.loc 1 647 3 is_stmt 1 view .LVU577
+ 1659              		.loc 1 647 14 is_stmt 0 view .LVU578
+ 1660 000e 0322     		movs	r2, #3
+ 1661 0010 A3F84020 		strh	r2, [r3, #64]	@ movhi
+ 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ 1662              		.loc 1 649 3 is_stmt 1 view .LVU579
+ 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 1663              		.loc 1 650 1 is_stmt 0 view .LVU580
+ 1664 0014 7047     		bx	lr
+ 1665              		.cfi_endproc
+ 1666              	.LFE339:
+ 1668              		.section	.text.USB_SetDevAddress,"ax",%progbits
+ 1669              		.align	1
+ 1670              		.global	USB_SetDevAddress
+ 1671              		.syntax unified
+ 1672              		.thumb
+ 1673              		.thumb_func
+ 1675              	USB_SetDevAddress:
+ 1676              	.LVL199:
+ 1677              	.LFB340:
+ 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_SetDevAddress Stop the usb device mode
+ 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  address new device address to be assigned
+ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   *          This parameter can be a value from 0 to 255
+ 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef  USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
+ 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 1678              		.loc 1 660 1 is_stmt 1 view -0
+ 1679              		.cfi_startproc
+ 1680              		@ args = 0, pretend = 0, frame = 0
+ 1681              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1682              		@ link register save eliminated.
+ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   if (address == 0U)
+ 1683              		.loc 1 661 3 view .LVU582
+ 1684              		.loc 1 661 6 is_stmt 0 view .LVU583
+ 1685 0000 11B9     		cbnz	r1, .L59
+ 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     /* set device address and enable function */
+ 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     USBx->DADDR = (uint16_t)USB_DADDR_EF;
+ 1686              		.loc 1 664 5 is_stmt 1 view .LVU584
+ 1687              		.loc 1 664 17 is_stmt 0 view .LVU585
+ARM GAS  /tmp/cc2t6zYn.s 			page 47
+
+
+ 1688 0002 8023     		movs	r3, #128
+ 1689 0004 A0F84C30 		strh	r3, [r0, #76]	@ movhi
+ 1690              	.L59:
+ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ 1691              		.loc 1 667 3 is_stmt 1 view .LVU586
+ 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 1692              		.loc 1 668 1 is_stmt 0 view .LVU587
+ 1693 0008 0020     		movs	r0, #0
+ 1694              	.LVL200:
+ 1695              		.loc 1 668 1 view .LVU588
+ 1696 000a 7047     		bx	lr
+ 1697              		.cfi_endproc
+ 1698              	.LFE340:
+ 1700              		.section	.text.USB_DevConnect,"ax",%progbits
+ 1701              		.align	1
+ 1702              		.global	USB_DevConnect
+ 1703              		.syntax unified
+ 1704              		.thumb
+ 1705              		.thumb_func
+ 1707              	USB_DevConnect:
+ 1708              	.LVL201:
+ 1709              	.LFB341:
+ 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
+ 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef  USB_DevConnect(USB_TypeDef *USBx)
+ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 1710              		.loc 1 676 1 is_stmt 1 view -0
+ 1711              		.cfi_startproc
+ 1712              		@ args = 0, pretend = 0, frame = 0
+ 1713              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1714              		@ link register save eliminated.
+ 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
+ 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->BCDR |= (uint16_t)USB_BCDR_DPPU;
+ 1715              		.loc 1 678 3 view .LVU590
+ 1716              		.loc 1 678 7 is_stmt 0 view .LVU591
+ 1717 0000 B0F85830 		ldrh	r3, [r0, #88]
+ 1718              		.loc 1 678 14 view .LVU592
+ 1719 0004 6FEA4343 		mvn	r3, r3, lsl #17
+ 1720 0008 6FEA5343 		mvn	r3, r3, lsr #17
+ 1721 000c 9BB2     		uxth	r3, r3
+ 1722 000e A0F85830 		strh	r3, [r0, #88]	@ movhi
+ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ 1723              		.loc 1 680 3 is_stmt 1 view .LVU593
+ 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 1724              		.loc 1 681 1 is_stmt 0 view .LVU594
+ 1725 0012 0020     		movs	r0, #0
+ 1726              	.LVL202:
+ 1727              		.loc 1 681 1 view .LVU595
+ 1728 0014 7047     		bx	lr
+ 1729              		.cfi_endproc
+ARM GAS  /tmp/cc2t6zYn.s 			page 48
+
+
+ 1730              	.LFE341:
+ 1732              		.section	.text.USB_DevDisconnect,"ax",%progbits
+ 1733              		.align	1
+ 1734              		.global	USB_DevDisconnect
+ 1735              		.syntax unified
+ 1736              		.thumb
+ 1737              		.thumb_func
+ 1739              	USB_DevDisconnect:
+ 1740              	.LVL203:
+ 1741              	.LFB342:
+ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
+ 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef  USB_DevDisconnect(USB_TypeDef *USBx)
+ 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 1742              		.loc 1 689 1 is_stmt 1 view -0
+ 1743              		.cfi_startproc
+ 1744              		@ args = 0, pretend = 0, frame = 0
+ 1745              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1746              		@ link register save eliminated.
+ 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */
+ 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));
+ 1747              		.loc 1 691 3 view .LVU597
+ 1748              		.loc 1 691 7 is_stmt 0 view .LVU598
+ 1749 0000 B0F85830 		ldrh	r3, [r0, #88]
+ 1750              		.loc 1 691 14 view .LVU599
+ 1751 0004 C3F30E03 		ubfx	r3, r3, #0, #15
+ 1752 0008 A0F85830 		strh	r3, [r0, #88]	@ movhi
+ 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ 1753              		.loc 1 693 3 is_stmt 1 view .LVU600
+ 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 1754              		.loc 1 694 1 is_stmt 0 view .LVU601
+ 1755 000c 0020     		movs	r0, #0
+ 1756              	.LVL204:
+ 1757              		.loc 1 694 1 view .LVU602
+ 1758 000e 7047     		bx	lr
+ 1759              		.cfi_endproc
+ 1760              	.LFE342:
+ 1762              		.section	.text.USB_ReadInterrupts,"ax",%progbits
+ 1763              		.align	1
+ 1764              		.global	USB_ReadInterrupts
+ 1765              		.syntax unified
+ 1766              		.thumb
+ 1767              		.thumb_func
+ 1769              	USB_ReadInterrupts:
+ 1770              	.LVL205:
+ 1771              	.LFB343:
+ 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_ReadInterrupts return the global USB interrupt status
+ 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ARM GAS  /tmp/cc2t6zYn.s 			page 49
+
+
+ 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** uint32_t  USB_ReadInterrupts(USB_TypeDef *USBx)
+ 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 1772              		.loc 1 702 1 is_stmt 1 view -0
+ 1773              		.cfi_startproc
+ 1774              		@ args = 0, pretend = 0, frame = 0
+ 1775              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1776              		@ link register save eliminated.
+ 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t tmpreg;
+ 1777              		.loc 1 703 3 view .LVU604
+ 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   tmpreg = USBx->ISTR;
+ 1778              		.loc 1 705 3 view .LVU605
+ 1779              		.loc 1 705 16 is_stmt 0 view .LVU606
+ 1780 0000 B0F84400 		ldrh	r0, [r0, #68]
+ 1781              	.LVL206:
+ 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return tmpreg;
+ 1782              		.loc 1 706 3 is_stmt 1 view .LVU607
+ 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 1783              		.loc 1 707 1 is_stmt 0 view .LVU608
+ 1784 0004 80B2     		uxth	r0, r0
+ 1785              	.LVL207:
+ 1786              		.loc 1 707 1 view .LVU609
+ 1787 0006 7047     		bx	lr
+ 1788              		.cfi_endproc
+ 1789              	.LFE343:
+ 1791              		.section	.text.USB_ActivateRemoteWakeup,"ax",%progbits
+ 1792              		.align	1
+ 1793              		.global	USB_ActivateRemoteWakeup
+ 1794              		.syntax unified
+ 1795              		.thumb
+ 1796              		.thumb_func
+ 1798              	USB_ActivateRemoteWakeup:
+ 1799              	.LVL208:
+ 1800              	.LFB344:
+ 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_ActivateRemoteWakeup : active remote wakeup signalling
+ 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
+ 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 1801              		.loc 1 715 1 is_stmt 1 view -0
+ 1802              		.cfi_startproc
+ 1803              		@ args = 0, pretend = 0, frame = 0
+ 1804              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1805              		@ link register save eliminated.
+ 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->CNTR |= (uint16_t)USB_CNTR_RESUME;
+ 1806              		.loc 1 716 3 view .LVU611
+ 1807              		.loc 1 716 7 is_stmt 0 view .LVU612
+ 1808 0000 B0F84030 		ldrh	r3, [r0, #64]
+ 1809 0004 9BB2     		uxth	r3, r3
+ 1810              		.loc 1 716 14 view .LVU613
+ 1811 0006 43F01003 		orr	r3, r3, #16
+ 1812 000a A0F84030 		strh	r3, [r0, #64]	@ movhi
+ 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ARM GAS  /tmp/cc2t6zYn.s 			page 50
+
+
+ 1813              		.loc 1 718 3 is_stmt 1 view .LVU614
+ 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 1814              		.loc 1 719 1 is_stmt 0 view .LVU615
+ 1815 000e 0020     		movs	r0, #0
+ 1816              	.LVL209:
+ 1817              		.loc 1 719 1 view .LVU616
+ 1818 0010 7047     		bx	lr
+ 1819              		.cfi_endproc
+ 1820              	.LFE344:
+ 1822              		.section	.text.USB_DeActivateRemoteWakeup,"ax",%progbits
+ 1823              		.align	1
+ 1824              		.global	USB_DeActivateRemoteWakeup
+ 1825              		.syntax unified
+ 1826              		.thumb
+ 1827              		.thumb_func
+ 1829              	USB_DeActivateRemoteWakeup:
+ 1830              	.LVL210:
+ 1831              	.LFB345:
+ 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+ 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param  USBx Selected device
+ 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval HAL status
+ 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
+ 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 1832              		.loc 1 727 1 is_stmt 1 view -0
+ 1833              		.cfi_startproc
+ 1834              		@ args = 0, pretend = 0, frame = 0
+ 1835              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1836              		@ link register save eliminated.
+ 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
+ 1837              		.loc 1 728 3 view .LVU618
+ 1838              		.loc 1 728 7 is_stmt 0 view .LVU619
+ 1839 0000 B0F84030 		ldrh	r3, [r0, #64]
+ 1840 0004 9BB2     		uxth	r3, r3
+ 1841              		.loc 1 728 14 view .LVU620
+ 1842 0006 23F01003 		bic	r3, r3, #16
+ 1843 000a 9BB2     		uxth	r3, r3
+ 1844 000c A0F84030 		strh	r3, [r0, #64]	@ movhi
+ 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   return HAL_OK;
+ 1845              		.loc 1 730 3 is_stmt 1 view .LVU621
+ 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 1846              		.loc 1 731 1 is_stmt 0 view .LVU622
+ 1847 0010 0020     		movs	r0, #0
+ 1848              	.LVL211:
+ 1849              		.loc 1 731 1 view .LVU623
+ 1850 0012 7047     		bx	lr
+ 1851              		.cfi_endproc
+ 1852              	.LFE345:
+ 1854              		.section	.text.USB_WritePMA,"ax",%progbits
+ 1855              		.align	1
+ 1856              		.global	USB_WritePMA
+ 1857              		.syntax unified
+ 1858              		.thumb
+ 1859              		.thumb_func
+ARM GAS  /tmp/cc2t6zYn.s 			page 51
+
+
+ 1861              	USB_WritePMA:
+ 1862              	.LVL212:
+ 1863              	.LFB346:
+ 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param   USBx USB peripheral instance register address.
+ 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param   pbUsrBuf pointer to user memory area.
+ 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param   wPMABufAddr address into PMA.
+ 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param   wNBytes no. of bytes to be copied.
+ 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval None
+ 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+ 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 1864              		.loc 1 742 1 is_stmt 1 view -0
+ 1865              		.cfi_startproc
+ 1866              		@ args = 0, pretend = 0, frame = 0
+ 1867              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1868              		@ link register save eliminated.
+ 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
+ 1869              		.loc 1 743 3 view .LVU625
+ 1870              		.loc 1 743 35 is_stmt 0 view .LVU626
+ 1871 0000 0133     		adds	r3, r3, #1
+ 1872              	.LVL213:
+ 1873              		.loc 1 743 12 view .LVU627
+ 1874 0002 5B08     		lsrs	r3, r3, #1
+ 1875              	.LVL214:
+ 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t BaseAddr = (uint32_t)USBx;
+ 1876              		.loc 1 744 3 is_stmt 1 view .LVU628
+ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t i;
+ 1877              		.loc 1 745 3 view .LVU629
+ 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t temp1;
+ 1878              		.loc 1 746 3 view .LVU630
+ 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t temp2;
+ 1879              		.loc 1 747 3 view .LVU631
+ 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   __IO uint16_t *pdwVal;
+ 1880              		.loc 1 748 3 view .LVU632
+ 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint8_t *pBuf = pbUsrBuf;
+ 1881              		.loc 1 749 3 view .LVU633
+ 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
+ 1882              		.loc 1 751 3 view .LVU634
+ 1883              		.loc 1 751 48 is_stmt 0 view .LVU635
+ 1884 0004 0244     		add	r2, r2, r0
+ 1885              	.LVL215:
+ 1886              		.loc 1 751 48 view .LVU636
+ 1887 0006 02F58062 		add	r2, r2, #1024
+ 1888              	.LVL216:
+ 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   for (i = n; i != 0U; i--)
+ 1889              		.loc 1 753 3 is_stmt 1 view .LVU637
+ 1890              		.loc 1 753 3 is_stmt 0 view .LVU638
+ 1891 000a 08E0     		b	.L66
+ 1892              	.LVL217:
+ 1893              	.L67:
+ 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     temp1 = *pBuf;
+ARM GAS  /tmp/cc2t6zYn.s 			page 52
+
+
+ 1894              		.loc 1 755 5 is_stmt 1 discriminator 3 view .LVU639
+ 1895              		.loc 1 755 13 is_stmt 0 discriminator 3 view .LVU640
+ 1896 000c 0878     		ldrb	r0, [r1]	@ zero_extendqisi2
+ 1897              	.LVL218:
+ 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     pBuf++;
+ 1898              		.loc 1 756 5 is_stmt 1 discriminator 3 view .LVU641
+ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8));
+ 1899              		.loc 1 757 5 discriminator 3 view .LVU642
+ 1900              		.loc 1 757 44 is_stmt 0 discriminator 3 view .LVU643
+ 1901 000e 91F801C0 		ldrb	ip, [r1, #1]	@ zero_extendqisi2
+ 1902              	.LVL219:
+ 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     *pdwVal = (uint16_t)temp2;
+ 1903              		.loc 1 758 5 is_stmt 1 discriminator 3 view .LVU644
+ 1904              		.loc 1 758 15 is_stmt 0 discriminator 3 view .LVU645
+ 1905 0012 40EA0C20 		orr	r0, r0, ip, lsl #8
+ 1906              	.LVL220:
+ 1907              		.loc 1 758 13 discriminator 3 view .LVU646
+ 1908 0016 22F8020B 		strh	r0, [r2], #2	@ movhi
+ 1909              	.LVL221:
+ 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     pdwVal++;
+ 1910              		.loc 1 759 5 is_stmt 1 discriminator 3 view .LVU647
+ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #if PMA_ACCESS > 1U
+ 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     pdwVal++;
+ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #endif /* PMA_ACCESS */
+ 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     pBuf++;
+ 1911              		.loc 1 765 5 discriminator 3 view .LVU648
+ 1912              		.loc 1 765 9 is_stmt 0 discriminator 3 view .LVU649
+ 1913 001a 0231     		adds	r1, r1, #2
+ 1914              	.LVL222:
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 1915              		.loc 1 753 25 is_stmt 1 discriminator 3 view .LVU650
+ 1916 001c 013B     		subs	r3, r3, #1
+ 1917              	.LVL223:
+ 1918              	.L66:
+ 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 1919              		.loc 1 753 17 discriminator 1 view .LVU651
+ 1920 001e 002B     		cmp	r3, #0
+ 1921 0020 F4D1     		bne	.L67
+ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 1922              		.loc 1 767 1 is_stmt 0 view .LVU652
+ 1923 0022 7047     		bx	lr
+ 1924              		.cfi_endproc
+ 1925              	.LFE346:
+ 1927              		.section	.text.USB_EPStartXfer,"ax",%progbits
+ 1928              		.align	1
+ 1929              		.global	USB_EPStartXfer
+ 1930              		.syntax unified
+ 1931              		.thumb
+ 1932              		.thumb_func
+ 1934              	USB_EPStartXfer:
+ 1935              	.LVL224:
+ 1936              	.LFB336:
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t len;
+ 1937              		.loc 1 367 1 is_stmt 1 view -0
+ARM GAS  /tmp/cc2t6zYn.s 			page 53
+
+
+ 1938              		.cfi_startproc
+ 1939              		@ args = 0, pretend = 0, frame = 0
+ 1940              		@ frame_needed = 0, uses_anonymous_args = 0
+ 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t len;
+ 1941              		.loc 1 367 1 is_stmt 0 view .LVU654
+ 1942 0000 70B5     		push	{r4, r5, r6, lr}
+ 1943              	.LCFI5:
+ 1944              		.cfi_def_cfa_offset 16
+ 1945              		.cfi_offset 4, -16
+ 1946              		.cfi_offset 5, -12
+ 1947              		.cfi_offset 6, -8
+ 1948              		.cfi_offset 14, -4
+ 1949 0002 0546     		mov	r5, r0
+ 1950 0004 0C46     		mov	r4, r1
+ 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #if (USE_USB_DOUBLE_BUFFER == 1U)
+ 1951              		.loc 1 368 3 is_stmt 1 view .LVU655
+ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint16_t wEPVal;
+ 1952              		.loc 1 370 3 view .LVU656
+ 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+ 1953              		.loc 1 371 3 view .LVU657
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 1954              		.loc 1 375 3 view .LVU658
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 1955              		.loc 1 375 9 is_stmt 0 view .LVU659
+ 1956 0006 4A78     		ldrb	r2, [r1, #1]	@ zero_extendqisi2
+ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 1957              		.loc 1 375 6 view .LVU660
+ 1958 0008 012A     		cmp	r2, #1
+ 1959 000a 32D0     		beq	.L153
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 1960              		.loc 1 511 5 is_stmt 1 view .LVU661
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 1961              		.loc 1 511 11 is_stmt 0 view .LVU662
+ 1962 000c 0B7B     		ldrb	r3, [r1, #12]	@ zero_extendqisi2
+ 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 1963              		.loc 1 511 8 view .LVU663
+ 1964 000e 002B     		cmp	r3, #0
+ 1965 0010 40F08382 		bne	.L118
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 1966              		.loc 1 514 7 is_stmt 1 view .LVU664
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 1967              		.loc 1 514 13 is_stmt 0 view .LVU665
+ 1968 0014 8B69     		ldr	r3, [r1, #24]
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 1969              		.loc 1 514 28 view .LVU666
+ 1970 0016 0A69     		ldr	r2, [r1, #16]
+ 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 1971              		.loc 1 514 10 view .LVU667
+ 1972 0018 9342     		cmp	r3, r2
+ 1973 001a 40F25D82 		bls	.L119
+ 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         ep->xfer_len -= len;
+ 1974              		.loc 1 516 9 is_stmt 1 view .LVU668
+ 1975              	.LVL225:
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 1976              		.loc 1 517 9 view .LVU669
+ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 1977              		.loc 1 517 22 is_stmt 0 view .LVU670
+ARM GAS  /tmp/cc2t6zYn.s 			page 54
+
+
+ 1978 001e 9B1A     		subs	r3, r3, r2
+ 1979 0020 8B61     		str	r3, [r1, #24]
+ 1980              	.L120:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1981              		.loc 1 525 7 is_stmt 1 view .LVU671
+ 1982              	.LBB61:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1983              		.loc 1 525 7 view .LVU672
+ 1984              	.LVL226:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1985              		.loc 1 525 7 view .LVU673
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1986              		.loc 1 525 7 view .LVU674
+ 1987 0022 B5F85030 		ldrh	r3, [r5, #80]
+ 1988 0026 15FA83F3 		uxtah	r3, r5, r3
+ 1989              	.LVL227:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1990              		.loc 1 525 7 view .LVU675
+ 1991 002a 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 1992              	.LVL228:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1993              		.loc 1 525 7 is_stmt 0 view .LVU676
+ 1994 002c 03EBC103 		add	r3, r3, r1, lsl #3
+ 1995              	.LVL229:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1996              		.loc 1 525 7 is_stmt 1 view .LVU677
+ 1997              	.LBB62:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1998              		.loc 1 525 7 view .LVU678
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 1999              		.loc 1 525 7 view .LVU679
+ 2000 0030 3E2A     		cmp	r2, #62
+ 2001 0032 40F25582 		bls	.L121
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2002              		.loc 1 525 7 discriminator 1 view .LVU680
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2003              		.loc 1 525 7 discriminator 1 view .LVU681
+ 2004 0036 5109     		lsrs	r1, r2, #5
+ 2005              	.LVL230:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2006              		.loc 1 525 7 discriminator 1 view .LVU682
+ 2007 0038 12F01F0F 		tst	r2, #31
+ 2008 003c 00D1     		bne	.L122
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2009              		.loc 1 525 7 discriminator 3 view .LVU683
+ 2010 003e 0139     		subs	r1, r1, #1
+ 2011              	.LVL231:
+ 2012              	.L122:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2013              		.loc 1 525 7 discriminator 5 view .LVU684
+ 2014 0040 6FEAC161 		mvn	r1, r1, lsl #27
+ 2015              	.LVL232:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2016              		.loc 1 525 7 is_stmt 0 discriminator 5 view .LVU685
+ 2017 0044 6FEA5141 		mvn	r1, r1, lsr #17
+ 2018 0048 89B2     		uxth	r1, r1
+ 2019 004a A3F80614 		strh	r1, [r3, #1030]	@ movhi
+ARM GAS  /tmp/cc2t6zYn.s 			page 55
+
+
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2020              		.loc 1 525 7 is_stmt 1 discriminator 5 view .LVU686
+ 2021              	.LVL233:
+ 2022              	.L123:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2023              		.loc 1 525 7 is_stmt 0 discriminator 5 view .LVU687
+ 2024              	.LBE62:
+ 2025              	.LBE61:
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2026              		.loc 1 573 5 is_stmt 1 view .LVU688
+ 2027              	.LBB64:
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2028              		.loc 1 573 5 view .LVU689
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2029              		.loc 1 573 5 view .LVU690
+ 2030 004e 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 2031 0050 35F82230 		ldrh	r3, [r5, r2, lsl #2]
+ 2032 0054 9BB2     		uxth	r3, r3
+ 2033 0056 23F48043 		bic	r3, r3, #16384
+ 2034 005a 23F07003 		bic	r3, r3, #112
+ 2035              	.LVL234:
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2036              		.loc 1 573 5 view .LVU691
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2037              		.loc 1 573 5 view .LVU692
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2038              		.loc 1 573 5 view .LVU693
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2039              		.loc 1 573 5 view .LVU694
+ 2040 005e 83F44053 		eor	r3, r3, #12288
+ 2041              	.LVL235:
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2042              		.loc 1 573 5 view .LVU695
+ 2043 0062 43F40043 		orr	r3, r3, #32768
+ 2044              	.LVL236:
+ 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2045              		.loc 1 573 5 is_stmt 0 view .LVU696
+ 2046 0066 43F08003 		orr	r3, r3, #128
+ 2047 006a 25F82230 		strh	r3, [r5, r2, lsl #2]	@ movhi
+ 2048              	.LBE64:
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 2049              		.loc 1 576 10 view .LVU697
+ 2050 006e 0020     		movs	r0, #0
+ 2051              	.LVL237:
+ 2052              	.L117:
+ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2053              		.loc 1 577 1 view .LVU698
+ 2054 0070 70BD     		pop	{r4, r5, r6, pc}
+ 2055              	.LVL238:
+ 2056              	.L153:
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 2057              		.loc 1 378 5 is_stmt 1 view .LVU699
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 2058              		.loc 1 378 11 is_stmt 0 view .LVU700
+ 2059 0072 8E69     		ldr	r6, [r1, #24]
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 2060              		.loc 1 378 26 view .LVU701
+ARM GAS  /tmp/cc2t6zYn.s 			page 56
+
+
+ 2061 0074 0969     		ldr	r1, [r1, #16]
+ 2062              	.LVL239:
+ 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 2063              		.loc 1 378 8 view .LVU702
+ 2064 0076 8E42     		cmp	r6, r1
+ 2065 0078 00D9     		bls	.L70
+ 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2066              		.loc 1 380 11 view .LVU703
+ 2067 007a 0E46     		mov	r6, r1
+ 2068              	.L70:
+ 2069              	.LVL240:
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 2070              		.loc 1 388 5 is_stmt 1 view .LVU704
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 2071              		.loc 1 388 11 is_stmt 0 view .LVU705
+ 2072 007c 237B     		ldrb	r3, [r4, #12]	@ zero_extendqisi2
+ 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     {
+ 2073              		.loc 1 388 8 view .LVU706
+ 2074 007e 2BB3     		cbz	r3, .L154
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 2075              		.loc 1 397 7 is_stmt 1 view .LVU707
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 2076              		.loc 1 397 13 is_stmt 0 view .LVU708
+ 2077 0080 E378     		ldrb	r3, [r4, #3]	@ zero_extendqisi2
+ 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 2078              		.loc 1 397 10 view .LVU709
+ 2079 0082 022B     		cmp	r3, #2
+ 2080 0084 44D0     		beq	.L155
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2081              		.loc 1 482 9 is_stmt 1 view .LVU710
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2082              		.loc 1 482 11 is_stmt 0 view .LVU711
+ 2083 0086 236A     		ldr	r3, [r4, #32]
+ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2084              		.loc 1 482 25 view .LVU712
+ 2085 0088 9B1B     		subs	r3, r3, r6
+ 2086 008a 2362     		str	r3, [r4, #32]
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 2087              		.loc 1 485 9 is_stmt 1 view .LVU713
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 2088              		.loc 1 485 14 is_stmt 0 view .LVU714
+ 2089 008c 2378     		ldrb	r3, [r4]	@ zero_extendqisi2
+ 2090 008e 35F82310 		ldrh	r1, [r5, r3, lsl #2]
+ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 2091              		.loc 1 485 12 view .LVU715
+ 2092 0092 11F0400F 		tst	r1, #64
+ 2093 0096 00F0DC81 		beq	.L104
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2094              		.loc 1 488 11 is_stmt 1 view .LVU716
+ 2095              	.LBB65:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2096              		.loc 1 488 11 view .LVU717
+ 2097              	.LVL241:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2098              		.loc 1 488 11 view .LVU718
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2099              		.loc 1 488 11 view .LVU719
+ARM GAS  /tmp/cc2t6zYn.s 			page 57
+
+
+ 2100 009a 002A     		cmp	r2, #0
+ 2101 009c 40F0C981 		bne	.L105
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2102              		.loc 1 488 11 discriminator 1 view .LVU720
+ 2103              	.LBB66:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2104              		.loc 1 488 11 discriminator 1 view .LVU721
+ 2105              	.LVL242:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2106              		.loc 1 488 11 discriminator 1 view .LVU722
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2107              		.loc 1 488 11 discriminator 1 view .LVU723
+ 2108 00a0 B5F85020 		ldrh	r2, [r5, #80]
+ 2109 00a4 15FA82F2 		uxtah	r2, r5, r2
+ 2110              	.LVL243:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2111              		.loc 1 488 11 discriminator 1 view .LVU724
+ 2112 00a8 02EBC303 		add	r3, r2, r3, lsl #3
+ 2113              	.LVL244:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2114              		.loc 1 488 11 discriminator 1 view .LVU725
+ 2115              	.LBB67:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2116              		.loc 1 488 11 discriminator 1 view .LVU726
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2117              		.loc 1 488 11 discriminator 1 view .LVU727
+ 2118 00ac 3E2E     		cmp	r6, #62
+ 2119 00ae 40F2A381 		bls	.L106
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2120              		.loc 1 488 11 discriminator 3 view .LVU728
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2121              		.loc 1 488 11 discriminator 3 view .LVU729
+ 2122 00b2 7209     		lsrs	r2, r6, #5
+ 2123              	.LVL245:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2124              		.loc 1 488 11 discriminator 3 view .LVU730
+ 2125 00b4 16F01F0F 		tst	r6, #31
+ 2126 00b8 00D1     		bne	.L107
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2127              		.loc 1 488 11 discriminator 5 view .LVU731
+ 2128 00ba 013A     		subs	r2, r2, #1
+ 2129              	.LVL246:
+ 2130              	.L107:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2131              		.loc 1 488 11 discriminator 7 view .LVU732
+ 2132 00bc 6FEAC262 		mvn	r2, r2, lsl #27
+ 2133              	.LVL247:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2134              		.loc 1 488 11 is_stmt 0 discriminator 7 view .LVU733
+ 2135 00c0 6FEA5242 		mvn	r2, r2, lsr #17
+ 2136 00c4 92B2     		uxth	r2, r2
+ 2137 00c6 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2138              		.loc 1 488 11 is_stmt 1 discriminator 7 view .LVU734
+ 2139 00ca BBE1     		b	.L108
+ 2140              	.LVL248:
+ 2141              	.L154:
+ARM GAS  /tmp/cc2t6zYn.s 			page 58
+
+
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2142              		.loc 1 488 11 is_stmt 0 discriminator 7 view .LVU735
+ 2143              	.LBE67:
+ 2144              	.LBE66:
+ 2145              	.LBE65:
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+ 2146              		.loc 1 390 7 is_stmt 1 view .LVU736
+ 2147 00cc B6B2     		uxth	r6, r6
+ 2148              	.LVL249:
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+ 2149              		.loc 1 390 7 is_stmt 0 view .LVU737
+ 2150 00ce 3346     		mov	r3, r6
+ 2151 00d0 E288     		ldrh	r2, [r4, #6]
+ 2152 00d2 6169     		ldr	r1, [r4, #20]
+ 2153 00d4 2846     		mov	r0, r5
+ 2154              	.LVL250:
+ 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+ 2155              		.loc 1 390 7 view .LVU738
+ 2156 00d6 FFF7FEFF 		bl	USB_WritePMA
+ 2157              	.LVL251:
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2158              		.loc 1 391 7 is_stmt 1 view .LVU739
+ 2159              	.LBB70:
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2160              		.loc 1 391 7 view .LVU740
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2161              		.loc 1 391 7 view .LVU741
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2162              		.loc 1 391 7 view .LVU742
+ 2163 00da B5F85030 		ldrh	r3, [r5, #80]
+ 2164 00de 15FA83F3 		uxtah	r3, r5, r3
+ 2165              	.LVL252:
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2166              		.loc 1 391 7 view .LVU743
+ 2167 00e2 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 2168 00e4 03EBC203 		add	r3, r3, r2, lsl #3
+ 2169              	.LVL253:
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2170              		.loc 1 391 7 view .LVU744
+ 2171 00e8 A3F80264 		strh	r6, [r3, #1026]	@ movhi
+ 2172              	.LBE70:
+ 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 2173              		.loc 1 391 7 view .LVU745
+ 2174              	.LVL254:
+ 2175              	.L72:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2176              		.loc 1 507 5 view .LVU746
+ 2177              	.LBB71:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2178              		.loc 1 507 5 view .LVU747
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2179              		.loc 1 507 5 view .LVU748
+ 2180 00ec 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 2181 00ee 35F82230 		ldrh	r3, [r5, r2, lsl #2]
+ 2182 00f2 9BB2     		uxth	r3, r3
+ 2183 00f4 23F4E043 		bic	r3, r3, #28672
+ 2184 00f8 23F04003 		bic	r3, r3, #64
+ARM GAS  /tmp/cc2t6zYn.s 			page 59
+
+
+ 2185              	.LVL255:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2186              		.loc 1 507 5 view .LVU749
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2187              		.loc 1 507 5 view .LVU750
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2188              		.loc 1 507 5 view .LVU751
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2189              		.loc 1 507 5 view .LVU752
+ 2190 00fc 83F03003 		eor	r3, r3, #48
+ 2191              	.LVL256:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2192              		.loc 1 507 5 view .LVU753
+ 2193 0100 43F40043 		orr	r3, r3, #32768
+ 2194              	.LVL257:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2195              		.loc 1 507 5 is_stmt 0 view .LVU754
+ 2196 0104 43F08003 		orr	r3, r3, #128
+ 2197 0108 25F82230 		strh	r3, [r5, r2, lsl #2]	@ movhi
+ 2198              	.LBE71:
+ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 2199              		.loc 1 507 5 is_stmt 1 view .LVU755
+ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 2200              		.loc 1 576 10 is_stmt 0 view .LVU756
+ 2201 010c 0020     		movs	r0, #0
+ 2202 010e AFE7     		b	.L117
+ 2203              	.LVL258:
+ 2204              	.L155:
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 2205              		.loc 1 399 9 is_stmt 1 view .LVU757
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 2206              		.loc 1 399 15 is_stmt 0 view .LVU758
+ 2207 0110 236A     		ldr	r3, [r4, #32]
+ 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 2208              		.loc 1 399 12 view .LVU759
+ 2209 0112 9942     		cmp	r1, r3
+ 2210 0114 80F05281 		bcs	.L74
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2211              		.loc 1 402 11 is_stmt 1 view .LVU760
+ 2212              	.LBB72:
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2213              		.loc 1 402 11 view .LVU761
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2214              		.loc 1 402 11 view .LVU762
+ 2215 0118 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 2216 011a 35F82230 		ldrh	r3, [r5, r2, lsl #2]
+ 2217 011e 9BB2     		uxth	r3, r3
+ 2218 0120 23F4E043 		bic	r3, r3, #28672
+ 2219 0124 23F07003 		bic	r3, r3, #112
+ 2220              	.LVL259:
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2221              		.loc 1 402 11 view .LVU763
+ 2222 0128 43F40143 		orr	r3, r3, #33024
+ 2223              	.LVL260:
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2224              		.loc 1 402 11 is_stmt 0 view .LVU764
+ 2225 012c 43F08003 		orr	r3, r3, #128
+ARM GAS  /tmp/cc2t6zYn.s 			page 60
+
+
+ 2226 0130 25F82230 		strh	r3, [r5, r2, lsl #2]	@ movhi
+ 2227              	.LBE72:
+ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2228              		.loc 1 402 11 is_stmt 1 view .LVU765
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2229              		.loc 1 405 11 view .LVU766
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2230              		.loc 1 405 13 is_stmt 0 view .LVU767
+ 2231 0134 236A     		ldr	r3, [r4, #32]
+ 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2232              		.loc 1 405 27 view .LVU768
+ 2233 0136 9B1B     		subs	r3, r3, r6
+ 2234 0138 2362     		str	r3, [r4, #32]
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           {
+ 2235              		.loc 1 408 11 is_stmt 1 view .LVU769
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           {
+ 2236              		.loc 1 408 16 is_stmt 0 view .LVU770
+ 2237 013a 2378     		ldrb	r3, [r4]	@ zero_extendqisi2
+ 2238 013c 35F82320 		ldrh	r2, [r5, r3, lsl #2]
+ 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           {
+ 2239              		.loc 1 408 14 view .LVU771
+ 2240 0140 12F0400F 		tst	r2, #64
+ 2241 0144 00F09D80 		beq	.L75
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2242              		.loc 1 411 13 is_stmt 1 view .LVU772
+ 2243              	.LBB73:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2244              		.loc 1 411 13 view .LVU773
+ 2245              	.LVL261:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2246              		.loc 1 411 13 view .LVU774
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2247              		.loc 1 411 13 view .LVU775
+ 2248 0148 6278     		ldrb	r2, [r4, #1]	@ zero_extendqisi2
+ 2249 014a 8ABB     		cbnz	r2, .L76
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2250              		.loc 1 411 13 discriminator 1 view .LVU776
+ 2251              	.LBB74:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2252              		.loc 1 411 13 discriminator 1 view .LVU777
+ 2253              	.LVL262:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2254              		.loc 1 411 13 discriminator 1 view .LVU778
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2255              		.loc 1 411 13 discriminator 1 view .LVU779
+ 2256 014c B5F85020 		ldrh	r2, [r5, #80]
+ 2257 0150 15FA82F2 		uxtah	r2, r5, r2
+ 2258              	.LVL263:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2259              		.loc 1 411 13 discriminator 1 view .LVU780
+ 2260 0154 02EBC303 		add	r3, r2, r3, lsl #3
+ 2261              	.LVL264:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2262              		.loc 1 411 13 discriminator 1 view .LVU781
+ 2263              	.LBB75:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2264              		.loc 1 411 13 discriminator 1 view .LVU782
+ARM GAS  /tmp/cc2t6zYn.s 			page 61
+
+
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2265              		.loc 1 411 13 discriminator 1 view .LVU783
+ 2266 0158 3E2E     		cmp	r6, #62
+ 2267 015a 0CD9     		bls	.L77
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2268              		.loc 1 411 13 discriminator 3 view .LVU784
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2269              		.loc 1 411 13 discriminator 3 view .LVU785
+ 2270 015c 7209     		lsrs	r2, r6, #5
+ 2271              	.LVL265:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2272              		.loc 1 411 13 discriminator 3 view .LVU786
+ 2273 015e 16F01F0F 		tst	r6, #31
+ 2274 0162 00D1     		bne	.L78
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2275              		.loc 1 411 13 discriminator 5 view .LVU787
+ 2276 0164 013A     		subs	r2, r2, #1
+ 2277              	.LVL266:
+ 2278              	.L78:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2279              		.loc 1 411 13 discriminator 7 view .LVU788
+ 2280 0166 6FEAC262 		mvn	r2, r2, lsl #27
+ 2281              	.LVL267:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2282              		.loc 1 411 13 is_stmt 0 discriminator 7 view .LVU789
+ 2283 016a 6FEA5242 		mvn	r2, r2, lsr #17
+ 2284 016e 92B2     		uxth	r2, r2
+ 2285 0170 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2286              		.loc 1 411 13 is_stmt 1 discriminator 7 view .LVU790
+ 2287 0174 1EE0     		b	.L79
+ 2288              	.LVL268:
+ 2289              	.L77:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2290              		.loc 1 411 13 discriminator 4 view .LVU791
+ 2291 0176 8EB9     		cbnz	r6, .L80
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2292              		.loc 1 411 13 discriminator 9 view .LVU792
+ 2293 0178 B3F80624 		ldrh	r2, [r3, #1030]
+ 2294              	.LVL269:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2295              		.loc 1 411 13 is_stmt 0 discriminator 9 view .LVU793
+ 2296 017c 92B2     		uxth	r2, r2
+ 2297 017e 22F4F842 		bic	r2, r2, #31744
+ 2298 0182 92B2     		uxth	r2, r2
+ 2299 0184 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2300              		.loc 1 411 13 is_stmt 1 discriminator 9 view .LVU794
+ 2301 0188 B3F80624 		ldrh	r2, [r3, #1030]
+ 2302 018c 6FEA4242 		mvn	r2, r2, lsl #17
+ 2303 0190 6FEA5242 		mvn	r2, r2, lsr #17
+ 2304 0194 92B2     		uxth	r2, r2
+ 2305 0196 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 2306 019a 0BE0     		b	.L79
+ 2307              	.LVL270:
+ 2308              	.L80:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ARM GAS  /tmp/cc2t6zYn.s 			page 62
+
+
+ 2309              		.loc 1 411 13 discriminator 10 view .LVU795
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2310              		.loc 1 411 13 discriminator 10 view .LVU796
+ 2311 019c 7208     		lsrs	r2, r6, #1
+ 2312              	.LVL271:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2313              		.loc 1 411 13 discriminator 10 view .LVU797
+ 2314 019e 16F0010F 		tst	r6, #1
+ 2315 01a2 00D0     		beq	.L81
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2316              		.loc 1 411 13 discriminator 12 view .LVU798
+ 2317 01a4 0132     		adds	r2, r2, #1
+ 2318              	.LVL272:
+ 2319              	.L81:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2320              		.loc 1 411 13 discriminator 14 view .LVU799
+ 2321 01a6 9202     		lsls	r2, r2, #10
+ 2322              	.LVL273:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2323              		.loc 1 411 13 is_stmt 0 discriminator 14 view .LVU800
+ 2324 01a8 92B2     		uxth	r2, r2
+ 2325 01aa A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 2326 01ae 01E0     		b	.L79
+ 2327              	.LVL274:
+ 2328              	.L76:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2329              		.loc 1 411 13 discriminator 14 view .LVU801
+ 2330              	.LBE75:
+ 2331              	.LBE74:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2332              		.loc 1 411 13 is_stmt 1 discriminator 2 view .LVU802
+ 2333 01b0 012A     		cmp	r2, #1
+ 2334 01b2 27D0     		beq	.L156
+ 2335              	.LVL275:
+ 2336              	.L79:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2337              		.loc 1 411 13 is_stmt 0 discriminator 2 view .LVU803
+ 2338              	.LBE73:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2339              		.loc 1 411 13 is_stmt 1 discriminator 18 view .LVU804
+ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2340              		.loc 1 412 13 discriminator 18 view .LVU805
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             ep->xfer_buff += len;
+ 2341              		.loc 1 415 13 discriminator 18 view .LVU806
+ 2342 01b4 B3B2     		uxth	r3, r6
+ 2343 01b6 6289     		ldrh	r2, [r4, #10]
+ 2344 01b8 6169     		ldr	r1, [r4, #20]
+ 2345 01ba 2846     		mov	r0, r5
+ 2346              	.LVL276:
+ 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             ep->xfer_buff += len;
+ 2347              		.loc 1 415 13 is_stmt 0 discriminator 18 view .LVU807
+ 2348 01bc FFF7FEFF 		bl	USB_WritePMA
+ 2349              	.LVL277:
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2350              		.loc 1 416 13 is_stmt 1 discriminator 18 view .LVU808
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2351              		.loc 1 416 15 is_stmt 0 discriminator 18 view .LVU809
+ARM GAS  /tmp/cc2t6zYn.s 			page 63
+
+
+ 2352 01c0 6369     		ldr	r3, [r4, #20]
+ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2353              		.loc 1 416 27 discriminator 18 view .LVU810
+ 2354 01c2 3344     		add	r3, r3, r6
+ 2355 01c4 6361     		str	r3, [r4, #20]
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             {
+ 2356              		.loc 1 418 13 is_stmt 1 discriminator 18 view .LVU811
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             {
+ 2357              		.loc 1 418 19 is_stmt 0 discriminator 18 view .LVU812
+ 2358 01c6 236A     		ldr	r3, [r4, #32]
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             {
+ 2359              		.loc 1 418 37 discriminator 18 view .LVU813
+ 2360 01c8 2269     		ldr	r2, [r4, #16]
+ 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             {
+ 2361              		.loc 1 418 16 discriminator 18 view .LVU814
+ 2362 01ca 9342     		cmp	r3, r2
+ 2363 01cc 24D9     		bls	.L82
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             }
+ 2364              		.loc 1 420 15 is_stmt 1 view .LVU815
+ 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             }
+ 2365              		.loc 1 420 31 is_stmt 0 view .LVU816
+ 2366 01ce 9B1B     		subs	r3, r3, r6
+ 2367 01d0 2362     		str	r3, [r4, #32]
+ 2368              	.L83:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2369              		.loc 1 429 13 is_stmt 1 view .LVU817
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2370              		.loc 1 429 13 view .LVU818
+ 2371 01d2 6378     		ldrb	r3, [r4, #1]	@ zero_extendqisi2
+ 2372 01d4 002B     		cmp	r3, #0
+ 2373 01d6 40D1     		bne	.L84
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2374              		.loc 1 429 13 discriminator 1 view .LVU819
+ 2375              	.LBB76:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2376              		.loc 1 429 13 discriminator 1 view .LVU820
+ 2377              	.LVL278:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2378              		.loc 1 429 13 discriminator 1 view .LVU821
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2379              		.loc 1 429 13 discriminator 1 view .LVU822
+ 2380 01d8 B5F85030 		ldrh	r3, [r5, #80]
+ 2381 01dc 15FA83F3 		uxtah	r3, r5, r3
+ 2382              	.LVL279:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2383              		.loc 1 429 13 discriminator 1 view .LVU823
+ 2384 01e0 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 2385 01e2 03EBC203 		add	r3, r3, r2, lsl #3
+ 2386              	.LVL280:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2387              		.loc 1 429 13 discriminator 1 view .LVU824
+ 2388              	.LBB77:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2389              		.loc 1 429 13 discriminator 1 view .LVU825
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2390              		.loc 1 429 13 discriminator 1 view .LVU826
+ 2391 01e6 3E2E     		cmp	r6, #62
+ARM GAS  /tmp/cc2t6zYn.s 			page 64
+
+
+ 2392 01e8 1AD9     		bls	.L85
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2393              		.loc 1 429 13 discriminator 3 view .LVU827
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2394              		.loc 1 429 13 discriminator 3 view .LVU828
+ 2395 01ea 7209     		lsrs	r2, r6, #5
+ 2396              	.LVL281:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2397              		.loc 1 429 13 discriminator 3 view .LVU829
+ 2398 01ec 16F01F0F 		tst	r6, #31
+ 2399 01f0 00D1     		bne	.L86
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2400              		.loc 1 429 13 discriminator 5 view .LVU830
+ 2401 01f2 013A     		subs	r2, r2, #1
+ 2402              	.LVL282:
+ 2403              	.L86:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2404              		.loc 1 429 13 discriminator 7 view .LVU831
+ 2405 01f4 6FEAC262 		mvn	r2, r2, lsl #27
+ 2406              	.LVL283:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2407              		.loc 1 429 13 is_stmt 0 discriminator 7 view .LVU832
+ 2408 01f8 6FEA5242 		mvn	r2, r2, lsr #17
+ 2409 01fc 92B2     		uxth	r2, r2
+ 2410 01fe A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2411              		.loc 1 429 13 is_stmt 1 discriminator 7 view .LVU833
+ 2412 0202 2CE0     		b	.L87
+ 2413              	.LVL284:
+ 2414              	.L156:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2415              		.loc 1 429 13 is_stmt 0 discriminator 7 view .LVU834
+ 2416              	.LBE77:
+ 2417              	.LBE76:
+ 2418              	.LBB79:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2419              		.loc 1 411 13 is_stmt 1 discriminator 16 view .LVU835
+ 2420 0204 B5F85020 		ldrh	r2, [r5, #80]
+ 2421 0208 15FA82F2 		uxtah	r2, r5, r2
+ 2422              	.LVL285:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2423              		.loc 1 411 13 discriminator 16 view .LVU836
+ 2424 020c 02EBC303 		add	r3, r2, r3, lsl #3
+ 2425              	.LVL286:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2426              		.loc 1 411 13 discriminator 16 view .LVU837
+ 2427 0210 B2B2     		uxth	r2, r6
+ 2428              	.LVL287:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2429              		.loc 1 411 13 is_stmt 0 discriminator 16 view .LVU838
+ 2430 0212 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 2431 0216 CDE7     		b	.L79
+ 2432              	.LVL288:
+ 2433              	.L82:
+ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2434              		.loc 1 411 13 discriminator 16 view .LVU839
+ 2435              	.LBE79:
+ARM GAS  /tmp/cc2t6zYn.s 			page 65
+
+
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               ep->xfer_len_db = 0U;
+ 2436              		.loc 1 424 15 is_stmt 1 view .LVU840
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             }
+ 2437              		.loc 1 425 15 view .LVU841
+ 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             }
+ 2438              		.loc 1 425 31 is_stmt 0 view .LVU842
+ 2439 0218 0022     		movs	r2, #0
+ 2440 021a 2262     		str	r2, [r4, #32]
+ 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               ep->xfer_len_db = 0U;
+ 2441              		.loc 1 424 19 view .LVU843
+ 2442 021c 1E46     		mov	r6, r3
+ 2443 021e D8E7     		b	.L83
+ 2444              	.LVL289:
+ 2445              	.L85:
+ 2446              	.LBB80:
+ 2447              	.LBB78:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2448              		.loc 1 429 13 is_stmt 1 discriminator 4 view .LVU844
+ 2449 0220 8EB9     		cbnz	r6, .L88
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2450              		.loc 1 429 13 discriminator 9 view .LVU845
+ 2451 0222 B3F80224 		ldrh	r2, [r3, #1026]
+ 2452 0226 92B2     		uxth	r2, r2
+ 2453 0228 22F4F842 		bic	r2, r2, #31744
+ 2454 022c 92B2     		uxth	r2, r2
+ 2455 022e A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2456              		.loc 1 429 13 discriminator 9 view .LVU846
+ 2457 0232 B3F80224 		ldrh	r2, [r3, #1026]
+ 2458 0236 6FEA4242 		mvn	r2, r2, lsl #17
+ 2459 023a 6FEA5242 		mvn	r2, r2, lsr #17
+ 2460 023e 92B2     		uxth	r2, r2
+ 2461 0240 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 2462 0244 0BE0     		b	.L87
+ 2463              	.L88:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2464              		.loc 1 429 13 discriminator 10 view .LVU847
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2465              		.loc 1 429 13 discriminator 10 view .LVU848
+ 2466 0246 7208     		lsrs	r2, r6, #1
+ 2467              	.LVL290:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2468              		.loc 1 429 13 discriminator 10 view .LVU849
+ 2469 0248 16F0010F 		tst	r6, #1
+ 2470 024c 00D0     		beq	.L89
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2471              		.loc 1 429 13 discriminator 12 view .LVU850
+ 2472 024e 0132     		adds	r2, r2, #1
+ 2473              	.LVL291:
+ 2474              	.L89:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2475              		.loc 1 429 13 discriminator 14 view .LVU851
+ 2476 0250 9202     		lsls	r2, r2, #10
+ 2477              	.LVL292:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2478              		.loc 1 429 13 is_stmt 0 discriminator 14 view .LVU852
+ 2479 0252 92B2     		uxth	r2, r2
+ARM GAS  /tmp/cc2t6zYn.s 			page 66
+
+
+ 2480 0254 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 2481 0258 01E0     		b	.L87
+ 2482              	.LVL293:
+ 2483              	.L84:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2484              		.loc 1 429 13 discriminator 14 view .LVU853
+ 2485              	.LBE78:
+ 2486              	.LBE80:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2487              		.loc 1 429 13 is_stmt 1 discriminator 2 view .LVU854
+ 2488 025a 012B     		cmp	r3, #1
+ 2489 025c 06D0     		beq	.L157
+ 2490              	.L87:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2491              		.loc 1 429 13 discriminator 18 view .LVU855
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2492              		.loc 1 429 13 discriminator 18 view .LVU856
+ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2493              		.loc 1 430 13 discriminator 18 view .LVU857
+ 2494              	.LVL294:
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 2495              		.loc 1 433 13 discriminator 18 view .LVU858
+ 2496 025e B3B2     		uxth	r3, r6
+ 2497 0260 2289     		ldrh	r2, [r4, #8]
+ 2498 0262 6169     		ldr	r1, [r4, #20]
+ 2499 0264 2846     		mov	r0, r5
+ 2500 0266 FFF7FEFF 		bl	USB_WritePMA
+ 2501              	.LVL295:
+ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 2502              		.loc 1 433 13 is_stmt 0 discriminator 18 view .LVU859
+ 2503 026a 3FE7     		b	.L72
+ 2504              	.L157:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2505              		.loc 1 429 13 is_stmt 1 discriminator 16 view .LVU860
+ 2506              	.LBB81:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2507              		.loc 1 429 13 discriminator 16 view .LVU861
+ 2508              	.LVL296:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2509              		.loc 1 429 13 discriminator 16 view .LVU862
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2510              		.loc 1 429 13 discriminator 16 view .LVU863
+ 2511 026c B5F85030 		ldrh	r3, [r5, #80]
+ 2512 0270 15FA83F3 		uxtah	r3, r5, r3
+ 2513              	.LVL297:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2514              		.loc 1 429 13 discriminator 16 view .LVU864
+ 2515 0274 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 2516 0276 03EBC203 		add	r3, r3, r2, lsl #3
+ 2517              	.LVL298:
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2518              		.loc 1 429 13 discriminator 16 view .LVU865
+ 2519 027a B2B2     		uxth	r2, r6
+ 2520 027c A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 2521 0280 EDE7     		b	.L87
+ 2522              	.LVL299:
+ 2523              	.L75:
+ARM GAS  /tmp/cc2t6zYn.s 			page 67
+
+
+ 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2524              		.loc 1 429 13 is_stmt 0 discriminator 16 view .LVU866
+ 2525              	.LBE81:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2526              		.loc 1 438 13 is_stmt 1 view .LVU867
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2527              		.loc 1 438 13 view .LVU868
+ 2528 0282 6278     		ldrb	r2, [r4, #1]	@ zero_extendqisi2
+ 2529 0284 8ABB     		cbnz	r2, .L90
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2530              		.loc 1 438 13 discriminator 1 view .LVU869
+ 2531              	.LBB82:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2532              		.loc 1 438 13 discriminator 1 view .LVU870
+ 2533              	.LVL300:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2534              		.loc 1 438 13 discriminator 1 view .LVU871
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2535              		.loc 1 438 13 discriminator 1 view .LVU872
+ 2536 0286 B5F85020 		ldrh	r2, [r5, #80]
+ 2537 028a 15FA82F2 		uxtah	r2, r5, r2
+ 2538              	.LVL301:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2539              		.loc 1 438 13 discriminator 1 view .LVU873
+ 2540 028e 02EBC303 		add	r3, r2, r3, lsl #3
+ 2541              	.LVL302:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2542              		.loc 1 438 13 discriminator 1 view .LVU874
+ 2543              	.LBB83:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2544              		.loc 1 438 13 discriminator 1 view .LVU875
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2545              		.loc 1 438 13 discriminator 1 view .LVU876
+ 2546 0292 3E2E     		cmp	r6, #62
+ 2547 0294 0CD9     		bls	.L91
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2548              		.loc 1 438 13 discriminator 3 view .LVU877
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2549              		.loc 1 438 13 discriminator 3 view .LVU878
+ 2550 0296 7209     		lsrs	r2, r6, #5
+ 2551              	.LVL303:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2552              		.loc 1 438 13 discriminator 3 view .LVU879
+ 2553 0298 16F01F0F 		tst	r6, #31
+ 2554 029c 00D1     		bne	.L92
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2555              		.loc 1 438 13 discriminator 5 view .LVU880
+ 2556 029e 013A     		subs	r2, r2, #1
+ 2557              	.LVL304:
+ 2558              	.L92:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2559              		.loc 1 438 13 discriminator 7 view .LVU881
+ 2560 02a0 6FEAC262 		mvn	r2, r2, lsl #27
+ 2561              	.LVL305:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2562              		.loc 1 438 13 is_stmt 0 discriminator 7 view .LVU882
+ 2563 02a4 6FEA5242 		mvn	r2, r2, lsr #17
+ARM GAS  /tmp/cc2t6zYn.s 			page 68
+
+
+ 2564 02a8 92B2     		uxth	r2, r2
+ 2565 02aa A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2566              		.loc 1 438 13 is_stmt 1 discriminator 7 view .LVU883
+ 2567 02ae 1EE0     		b	.L93
+ 2568              	.LVL306:
+ 2569              	.L91:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2570              		.loc 1 438 13 discriminator 4 view .LVU884
+ 2571 02b0 8EB9     		cbnz	r6, .L94
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2572              		.loc 1 438 13 discriminator 9 view .LVU885
+ 2573 02b2 B3F80224 		ldrh	r2, [r3, #1026]
+ 2574              	.LVL307:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2575              		.loc 1 438 13 is_stmt 0 discriminator 9 view .LVU886
+ 2576 02b6 92B2     		uxth	r2, r2
+ 2577 02b8 22F4F842 		bic	r2, r2, #31744
+ 2578 02bc 92B2     		uxth	r2, r2
+ 2579 02be A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2580              		.loc 1 438 13 is_stmt 1 discriminator 9 view .LVU887
+ 2581 02c2 B3F80224 		ldrh	r2, [r3, #1026]
+ 2582 02c6 6FEA4242 		mvn	r2, r2, lsl #17
+ 2583 02ca 6FEA5242 		mvn	r2, r2, lsr #17
+ 2584 02ce 92B2     		uxth	r2, r2
+ 2585 02d0 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 2586 02d4 0BE0     		b	.L93
+ 2587              	.LVL308:
+ 2588              	.L94:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2589              		.loc 1 438 13 discriminator 10 view .LVU888
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2590              		.loc 1 438 13 discriminator 10 view .LVU889
+ 2591 02d6 7208     		lsrs	r2, r6, #1
+ 2592              	.LVL309:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2593              		.loc 1 438 13 discriminator 10 view .LVU890
+ 2594 02d8 16F0010F 		tst	r6, #1
+ 2595 02dc 00D0     		beq	.L95
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2596              		.loc 1 438 13 discriminator 12 view .LVU891
+ 2597 02de 0132     		adds	r2, r2, #1
+ 2598              	.LVL310:
+ 2599              	.L95:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2600              		.loc 1 438 13 discriminator 14 view .LVU892
+ 2601 02e0 9202     		lsls	r2, r2, #10
+ 2602              	.LVL311:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2603              		.loc 1 438 13 is_stmt 0 discriminator 14 view .LVU893
+ 2604 02e2 92B2     		uxth	r2, r2
+ 2605 02e4 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 2606 02e8 01E0     		b	.L93
+ 2607              	.LVL312:
+ 2608              	.L90:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ARM GAS  /tmp/cc2t6zYn.s 			page 69
+
+
+ 2609              		.loc 1 438 13 discriminator 14 view .LVU894
+ 2610              	.LBE83:
+ 2611              	.LBE82:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2612              		.loc 1 438 13 is_stmt 1 discriminator 2 view .LVU895
+ 2613 02ea 012A     		cmp	r2, #1
+ 2614 02ec 27D0     		beq	.L158
+ 2615              	.L93:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2616              		.loc 1 438 13 discriminator 18 view .LVU896
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2617              		.loc 1 438 13 discriminator 18 view .LVU897
+ 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2618              		.loc 1 439 13 discriminator 18 view .LVU898
+ 2619              	.LVL313:
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             ep->xfer_buff += len;
+ 2620              		.loc 1 442 13 discriminator 18 view .LVU899
+ 2621 02ee B3B2     		uxth	r3, r6
+ 2622 02f0 2289     		ldrh	r2, [r4, #8]
+ 2623 02f2 6169     		ldr	r1, [r4, #20]
+ 2624 02f4 2846     		mov	r0, r5
+ 2625              	.LVL314:
+ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             ep->xfer_buff += len;
+ 2626              		.loc 1 442 13 is_stmt 0 discriminator 18 view .LVU900
+ 2627 02f6 FFF7FEFF 		bl	USB_WritePMA
+ 2628              	.LVL315:
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2629              		.loc 1 443 13 is_stmt 1 discriminator 18 view .LVU901
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2630              		.loc 1 443 15 is_stmt 0 discriminator 18 view .LVU902
+ 2631 02fa 6369     		ldr	r3, [r4, #20]
+ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2632              		.loc 1 443 27 discriminator 18 view .LVU903
+ 2633 02fc 3344     		add	r3, r3, r6
+ 2634 02fe 6361     		str	r3, [r4, #20]
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             {
+ 2635              		.loc 1 445 13 is_stmt 1 discriminator 18 view .LVU904
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             {
+ 2636              		.loc 1 445 19 is_stmt 0 discriminator 18 view .LVU905
+ 2637 0300 236A     		ldr	r3, [r4, #32]
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             {
+ 2638              		.loc 1 445 37 discriminator 18 view .LVU906
+ 2639 0302 2269     		ldr	r2, [r4, #16]
+ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             {
+ 2640              		.loc 1 445 16 discriminator 18 view .LVU907
+ 2641 0304 9342     		cmp	r3, r2
+ 2642 0306 24D9     		bls	.L96
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             }
+ 2643              		.loc 1 447 15 is_stmt 1 view .LVU908
+ 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             }
+ 2644              		.loc 1 447 31 is_stmt 0 view .LVU909
+ 2645 0308 9B1B     		subs	r3, r3, r6
+ 2646 030a 2362     		str	r3, [r4, #32]
+ 2647              	.L97:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2648              		.loc 1 456 13 is_stmt 1 view .LVU910
+ 2649              	.LBB84:
+ARM GAS  /tmp/cc2t6zYn.s 			page 70
+
+
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2650              		.loc 1 456 13 view .LVU911
+ 2651              	.LVL316:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2652              		.loc 1 456 13 view .LVU912
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2653              		.loc 1 456 13 view .LVU913
+ 2654 030c 6378     		ldrb	r3, [r4, #1]	@ zero_extendqisi2
+ 2655 030e 002B     		cmp	r3, #0
+ 2656 0310 40D1     		bne	.L98
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2657              		.loc 1 456 13 discriminator 1 view .LVU914
+ 2658              	.LBB85:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2659              		.loc 1 456 13 discriminator 1 view .LVU915
+ 2660              	.LVL317:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2661              		.loc 1 456 13 discriminator 1 view .LVU916
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2662              		.loc 1 456 13 discriminator 1 view .LVU917
+ 2663 0312 B5F85030 		ldrh	r3, [r5, #80]
+ 2664 0316 15FA83F3 		uxtah	r3, r5, r3
+ 2665              	.LVL318:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2666              		.loc 1 456 13 discriminator 1 view .LVU918
+ 2667 031a 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 2668 031c 03EBC203 		add	r3, r3, r2, lsl #3
+ 2669              	.LVL319:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2670              		.loc 1 456 13 discriminator 1 view .LVU919
+ 2671              	.LBB86:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2672              		.loc 1 456 13 discriminator 1 view .LVU920
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2673              		.loc 1 456 13 discriminator 1 view .LVU921
+ 2674 0320 3E2E     		cmp	r6, #62
+ 2675 0322 1AD9     		bls	.L99
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2676              		.loc 1 456 13 discriminator 3 view .LVU922
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2677              		.loc 1 456 13 discriminator 3 view .LVU923
+ 2678 0324 7209     		lsrs	r2, r6, #5
+ 2679              	.LVL320:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2680              		.loc 1 456 13 discriminator 3 view .LVU924
+ 2681 0326 16F01F0F 		tst	r6, #31
+ 2682 032a 00D1     		bne	.L100
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2683              		.loc 1 456 13 discriminator 5 view .LVU925
+ 2684 032c 013A     		subs	r2, r2, #1
+ 2685              	.LVL321:
+ 2686              	.L100:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2687              		.loc 1 456 13 discriminator 7 view .LVU926
+ 2688 032e 6FEAC262 		mvn	r2, r2, lsl #27
+ 2689              	.LVL322:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ARM GAS  /tmp/cc2t6zYn.s 			page 71
+
+
+ 2690              		.loc 1 456 13 is_stmt 0 discriminator 7 view .LVU927
+ 2691 0332 6FEA5242 		mvn	r2, r2, lsr #17
+ 2692 0336 92B2     		uxth	r2, r2
+ 2693 0338 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2694              		.loc 1 456 13 is_stmt 1 discriminator 7 view .LVU928
+ 2695 033c 2CE0     		b	.L101
+ 2696              	.LVL323:
+ 2697              	.L158:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2698              		.loc 1 456 13 is_stmt 0 discriminator 7 view .LVU929
+ 2699              	.LBE86:
+ 2700              	.LBE85:
+ 2701              	.LBE84:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2702              		.loc 1 438 13 is_stmt 1 discriminator 16 view .LVU930
+ 2703              	.LBB89:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2704              		.loc 1 438 13 discriminator 16 view .LVU931
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2705              		.loc 1 438 13 discriminator 16 view .LVU932
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2706              		.loc 1 438 13 discriminator 16 view .LVU933
+ 2707 033e B5F85020 		ldrh	r2, [r5, #80]
+ 2708 0342 15FA82F2 		uxtah	r2, r5, r2
+ 2709              	.LVL324:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2710              		.loc 1 438 13 discriminator 16 view .LVU934
+ 2711 0346 02EBC303 		add	r3, r2, r3, lsl #3
+ 2712              	.LVL325:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2713              		.loc 1 438 13 discriminator 16 view .LVU935
+ 2714 034a B2B2     		uxth	r2, r6
+ 2715              	.LVL326:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2716              		.loc 1 438 13 is_stmt 0 discriminator 16 view .LVU936
+ 2717 034c A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 2718 0350 CDE7     		b	.L93
+ 2719              	.LVL327:
+ 2720              	.L96:
+ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr0;
+ 2721              		.loc 1 438 13 discriminator 16 view .LVU937
+ 2722              	.LBE89:
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               ep->xfer_len_db = 0U;
+ 2723              		.loc 1 451 15 is_stmt 1 view .LVU938
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             }
+ 2724              		.loc 1 452 15 view .LVU939
+ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             }
+ 2725              		.loc 1 452 31 is_stmt 0 view .LVU940
+ 2726 0352 0022     		movs	r2, #0
+ 2727 0354 2262     		str	r2, [r4, #32]
+ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               ep->xfer_len_db = 0U;
+ 2728              		.loc 1 451 19 view .LVU941
+ 2729 0356 1E46     		mov	r6, r3
+ 2730 0358 D8E7     		b	.L97
+ 2731              	.LVL328:
+ 2732              	.L99:
+ARM GAS  /tmp/cc2t6zYn.s 			page 72
+
+
+ 2733              	.LBB90:
+ 2734              	.LBB88:
+ 2735              	.LBB87:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2736              		.loc 1 456 13 is_stmt 1 discriminator 4 view .LVU942
+ 2737 035a 8EB9     		cbnz	r6, .L102
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2738              		.loc 1 456 13 discriminator 9 view .LVU943
+ 2739 035c B3F80624 		ldrh	r2, [r3, #1030]
+ 2740 0360 92B2     		uxth	r2, r2
+ 2741 0362 22F4F842 		bic	r2, r2, #31744
+ 2742 0366 92B2     		uxth	r2, r2
+ 2743 0368 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2744              		.loc 1 456 13 discriminator 9 view .LVU944
+ 2745 036c B3F80624 		ldrh	r2, [r3, #1030]
+ 2746 0370 6FEA4242 		mvn	r2, r2, lsl #17
+ 2747 0374 6FEA5242 		mvn	r2, r2, lsr #17
+ 2748 0378 92B2     		uxth	r2, r2
+ 2749 037a A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 2750 037e 0BE0     		b	.L101
+ 2751              	.L102:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2752              		.loc 1 456 13 discriminator 10 view .LVU945
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2753              		.loc 1 456 13 discriminator 10 view .LVU946
+ 2754 0380 7208     		lsrs	r2, r6, #1
+ 2755              	.LVL329:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2756              		.loc 1 456 13 discriminator 10 view .LVU947
+ 2757 0382 16F0010F 		tst	r6, #1
+ 2758 0386 00D0     		beq	.L103
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2759              		.loc 1 456 13 discriminator 12 view .LVU948
+ 2760 0388 0132     		adds	r2, r2, #1
+ 2761              	.LVL330:
+ 2762              	.L103:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2763              		.loc 1 456 13 discriminator 14 view .LVU949
+ 2764 038a 9202     		lsls	r2, r2, #10
+ 2765              	.LVL331:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2766              		.loc 1 456 13 is_stmt 0 discriminator 14 view .LVU950
+ 2767 038c 92B2     		uxth	r2, r2
+ 2768 038e A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 2769 0392 01E0     		b	.L101
+ 2770              	.LVL332:
+ 2771              	.L98:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2772              		.loc 1 456 13 discriminator 14 view .LVU951
+ 2773              	.LBE87:
+ 2774              	.LBE88:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2775              		.loc 1 456 13 is_stmt 1 discriminator 2 view .LVU952
+ 2776 0394 012B     		cmp	r3, #1
+ 2777 0396 06D0     		beq	.L159
+ 2778              	.LVL333:
+ARM GAS  /tmp/cc2t6zYn.s 			page 73
+
+
+ 2779              	.L101:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2780              		.loc 1 456 13 is_stmt 0 discriminator 2 view .LVU953
+ 2781              	.LBE90:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2782              		.loc 1 456 13 is_stmt 1 discriminator 18 view .LVU954
+ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2783              		.loc 1 457 13 discriminator 18 view .LVU955
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 2784              		.loc 1 460 13 discriminator 18 view .LVU956
+ 2785 0398 B3B2     		uxth	r3, r6
+ 2786 039a 6289     		ldrh	r2, [r4, #10]
+ 2787 039c 6169     		ldr	r1, [r4, #20]
+ 2788 039e 2846     		mov	r0, r5
+ 2789 03a0 FFF7FEFF 		bl	USB_WritePMA
+ 2790              	.LVL334:
+ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 2791              		.loc 1 460 13 is_stmt 0 discriminator 18 view .LVU957
+ 2792 03a4 A2E6     		b	.L72
+ 2793              	.LVL335:
+ 2794              	.L159:
+ 2795              	.LBB91:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2796              		.loc 1 456 13 is_stmt 1 discriminator 16 view .LVU958
+ 2797 03a6 B5F85030 		ldrh	r3, [r5, #80]
+ 2798 03aa 15FA83F3 		uxtah	r3, r5, r3
+ 2799              	.LVL336:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2800              		.loc 1 456 13 discriminator 16 view .LVU959
+ 2801 03ae 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 2802 03b0 03EBC203 		add	r3, r3, r2, lsl #3
+ 2803              	.LVL337:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2804              		.loc 1 456 13 discriminator 16 view .LVU960
+ 2805 03b4 B2B2     		uxth	r2, r6
+ 2806 03b6 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 2807 03ba EDE7     		b	.L101
+ 2808              	.LVL338:
+ 2809              	.L74:
+ 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****             pmabuffer = ep->pmaaddr1;
+ 2810              		.loc 1 456 13 is_stmt 0 discriminator 16 view .LVU961
+ 2811              	.LBE91:
+ 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2812              		.loc 1 466 11 is_stmt 1 view .LVU962
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2813              		.loc 1 469 11 view .LVU963
+ 2814              	.LBB92:
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2815              		.loc 1 469 11 view .LVU964
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2816              		.loc 1 469 11 view .LVU965
+ 2817 03bc 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 2818 03be 35F82120 		ldrh	r2, [r5, r1, lsl #2]
+ 2819 03c2 92B2     		uxth	r2, r2
+ 2820 03c4 22F4E242 		bic	r2, r2, #28928
+ 2821 03c8 22F07002 		bic	r2, r2, #112
+ 2822              	.LVL339:
+ARM GAS  /tmp/cc2t6zYn.s 			page 74
+
+
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2823              		.loc 1 469 11 view .LVU966
+ 2824 03cc 42F40042 		orr	r2, r2, #32768
+ 2825              	.LVL340:
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2826              		.loc 1 469 11 is_stmt 0 view .LVU967
+ 2827 03d0 42F08002 		orr	r2, r2, #128
+ 2828 03d4 25F82120 		strh	r2, [r5, r1, lsl #2]	@ movhi
+ 2829              	.LBE92:
+ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2830              		.loc 1 469 11 is_stmt 1 view .LVU968
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2831              		.loc 1 472 11 view .LVU969
+ 2832              	.LBB93:
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2833              		.loc 1 472 11 view .LVU970
+ 2834              	.LVL341:
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2835              		.loc 1 472 11 view .LVU971
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2836              		.loc 1 472 11 view .LVU972
+ 2837 03d8 B5F85020 		ldrh	r2, [r5, #80]
+ 2838 03dc 15FA82F2 		uxtah	r2, r5, r2
+ 2839              	.LVL342:
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2840              		.loc 1 472 11 view .LVU973
+ 2841 03e0 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 2842 03e2 02EBC102 		add	r2, r2, r1, lsl #3
+ 2843              	.LVL343:
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2844              		.loc 1 472 11 view .LVU974
+ 2845 03e6 9BB2     		uxth	r3, r3
+ 2846              	.LVL344:
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2847              		.loc 1 472 11 is_stmt 0 view .LVU975
+ 2848 03e8 A2F80234 		strh	r3, [r2, #1026]	@ movhi
+ 2849              	.LBE93:
+ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2850              		.loc 1 472 11 is_stmt 1 view .LVU976
+ 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2851              		.loc 1 473 11 view .LVU977
+ 2852              	.LVL345:
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 2853              		.loc 1 476 11 view .LVU978
+ 2854 03ec 2289     		ldrh	r2, [r4, #8]
+ 2855              	.LVL346:
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 2856              		.loc 1 476 11 is_stmt 0 view .LVU979
+ 2857 03ee 6169     		ldr	r1, [r4, #20]
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 2858              		.loc 1 476 11 view .LVU980
+ 2859 03f0 2846     		mov	r0, r5
+ 2860              	.LVL347:
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 2861              		.loc 1 476 11 view .LVU981
+ 2862 03f2 FFF7FEFF 		bl	USB_WritePMA
+ 2863              	.LVL348:
+ARM GAS  /tmp/cc2t6zYn.s 			page 75
+
+
+ 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 2864              		.loc 1 476 11 view .LVU982
+ 2865 03f6 79E6     		b	.L72
+ 2866              	.LVL349:
+ 2867              	.L106:
+ 2868              	.LBB94:
+ 2869              	.LBB69:
+ 2870              	.LBB68:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2871              		.loc 1 488 11 is_stmt 1 discriminator 4 view .LVU983
+ 2872 03f8 8EB9     		cbnz	r6, .L109
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2873              		.loc 1 488 11 discriminator 9 view .LVU984
+ 2874 03fa B3F80624 		ldrh	r2, [r3, #1030]
+ 2875              	.LVL350:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2876              		.loc 1 488 11 is_stmt 0 discriminator 9 view .LVU985
+ 2877 03fe 92B2     		uxth	r2, r2
+ 2878 0400 22F4F842 		bic	r2, r2, #31744
+ 2879 0404 92B2     		uxth	r2, r2
+ 2880 0406 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2881              		.loc 1 488 11 is_stmt 1 discriminator 9 view .LVU986
+ 2882 040a B3F80624 		ldrh	r2, [r3, #1030]
+ 2883 040e 6FEA4242 		mvn	r2, r2, lsl #17
+ 2884 0412 6FEA5242 		mvn	r2, r2, lsr #17
+ 2885 0416 92B2     		uxth	r2, r2
+ 2886 0418 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 2887 041c 12E0     		b	.L108
+ 2888              	.LVL351:
+ 2889              	.L109:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2890              		.loc 1 488 11 discriminator 10 view .LVU987
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2891              		.loc 1 488 11 discriminator 10 view .LVU988
+ 2892 041e 7208     		lsrs	r2, r6, #1
+ 2893              	.LVL352:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2894              		.loc 1 488 11 discriminator 10 view .LVU989
+ 2895 0420 16F0010F 		tst	r6, #1
+ 2896 0424 00D0     		beq	.L110
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2897              		.loc 1 488 11 discriminator 12 view .LVU990
+ 2898 0426 0132     		adds	r2, r2, #1
+ 2899              	.LVL353:
+ 2900              	.L110:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2901              		.loc 1 488 11 discriminator 14 view .LVU991
+ 2902 0428 9202     		lsls	r2, r2, #10
+ 2903              	.LVL354:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2904              		.loc 1 488 11 is_stmt 0 discriminator 14 view .LVU992
+ 2905 042a 92B2     		uxth	r2, r2
+ 2906 042c A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 2907 0430 08E0     		b	.L108
+ 2908              	.LVL355:
+ 2909              	.L105:
+ARM GAS  /tmp/cc2t6zYn.s 			page 76
+
+
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2910              		.loc 1 488 11 discriminator 14 view .LVU993
+ 2911              	.LBE68:
+ 2912              	.LBE69:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2913              		.loc 1 488 11 is_stmt 1 discriminator 16 view .LVU994
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2914              		.loc 1 488 11 discriminator 16 view .LVU995
+ 2915 0432 B5F85020 		ldrh	r2, [r5, #80]
+ 2916 0436 15FA82F2 		uxtah	r2, r5, r2
+ 2917              	.LVL356:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2918              		.loc 1 488 11 discriminator 16 view .LVU996
+ 2919 043a 02EBC303 		add	r3, r2, r3, lsl #3
+ 2920              	.LVL357:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2921              		.loc 1 488 11 discriminator 16 view .LVU997
+ 2922 043e B2B2     		uxth	r2, r6
+ 2923              	.LVL358:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2924              		.loc 1 488 11 is_stmt 0 discriminator 16 view .LVU998
+ 2925 0440 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 2926              	.LVL359:
+ 2927              	.L108:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2928              		.loc 1 488 11 discriminator 16 view .LVU999
+ 2929              	.LBE94:
+ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr1;
+ 2930              		.loc 1 488 11 is_stmt 1 discriminator 18 view .LVU1000
+ 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 2931              		.loc 1 489 11 discriminator 18 view .LVU1001
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 2932              		.loc 1 492 11 discriminator 18 view .LVU1002
+ 2933 0444 B3B2     		uxth	r3, r6
+ 2934 0446 6289     		ldrh	r2, [r4, #10]
+ 2935 0448 6169     		ldr	r1, [r4, #20]
+ 2936 044a 2846     		mov	r0, r5
+ 2937              	.LVL360:
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 2938              		.loc 1 492 11 is_stmt 0 discriminator 18 view .LVU1003
+ 2939 044c FFF7FEFF 		bl	USB_WritePMA
+ 2940              	.LVL361:
+ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 2941              		.loc 1 492 11 discriminator 18 view .LVU1004
+ 2942 0450 4CE6     		b	.L72
+ 2943              	.LVL362:
+ 2944              	.L104:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2945              		.loc 1 497 11 is_stmt 1 view .LVU1005
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2946              		.loc 1 497 11 view .LVU1006
+ 2947 0452 8ABB     		cbnz	r2, .L111
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2948              		.loc 1 497 11 discriminator 1 view .LVU1007
+ 2949              	.LBB95:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2950              		.loc 1 497 11 discriminator 1 view .LVU1008
+ARM GAS  /tmp/cc2t6zYn.s 			page 77
+
+
+ 2951              	.LVL363:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2952              		.loc 1 497 11 discriminator 1 view .LVU1009
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2953              		.loc 1 497 11 discriminator 1 view .LVU1010
+ 2954 0454 B5F85020 		ldrh	r2, [r5, #80]
+ 2955 0458 15FA82F2 		uxtah	r2, r5, r2
+ 2956              	.LVL364:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2957              		.loc 1 497 11 discriminator 1 view .LVU1011
+ 2958 045c 02EBC303 		add	r3, r2, r3, lsl #3
+ 2959              	.LVL365:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2960              		.loc 1 497 11 discriminator 1 view .LVU1012
+ 2961              	.LBB96:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2962              		.loc 1 497 11 discriminator 1 view .LVU1013
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2963              		.loc 1 497 11 discriminator 1 view .LVU1014
+ 2964 0460 3E2E     		cmp	r6, #62
+ 2965 0462 0CD9     		bls	.L112
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2966              		.loc 1 497 11 discriminator 3 view .LVU1015
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2967              		.loc 1 497 11 discriminator 3 view .LVU1016
+ 2968 0464 7209     		lsrs	r2, r6, #5
+ 2969              	.LVL366:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2970              		.loc 1 497 11 discriminator 3 view .LVU1017
+ 2971 0466 16F01F0F 		tst	r6, #31
+ 2972 046a 00D1     		bne	.L113
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2973              		.loc 1 497 11 discriminator 5 view .LVU1018
+ 2974 046c 013A     		subs	r2, r2, #1
+ 2975              	.LVL367:
+ 2976              	.L113:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2977              		.loc 1 497 11 discriminator 7 view .LVU1019
+ 2978 046e 6FEAC262 		mvn	r2, r2, lsl #27
+ 2979              	.LVL368:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2980              		.loc 1 497 11 is_stmt 0 discriminator 7 view .LVU1020
+ 2981 0472 6FEA5242 		mvn	r2, r2, lsr #17
+ 2982 0476 92B2     		uxth	r2, r2
+ 2983 0478 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2984              		.loc 1 497 11 is_stmt 1 discriminator 7 view .LVU1021
+ 2985 047c 25E0     		b	.L114
+ 2986              	.LVL369:
+ 2987              	.L112:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2988              		.loc 1 497 11 discriminator 4 view .LVU1022
+ 2989 047e 8EB9     		cbnz	r6, .L115
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2990              		.loc 1 497 11 discriminator 9 view .LVU1023
+ 2991 0480 B3F80224 		ldrh	r2, [r3, #1026]
+ 2992              	.LVL370:
+ARM GAS  /tmp/cc2t6zYn.s 			page 78
+
+
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2993              		.loc 1 497 11 is_stmt 0 discriminator 9 view .LVU1024
+ 2994 0484 92B2     		uxth	r2, r2
+ 2995 0486 22F4F842 		bic	r2, r2, #31744
+ 2996 048a 92B2     		uxth	r2, r2
+ 2997 048c A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 2998              		.loc 1 497 11 is_stmt 1 discriminator 9 view .LVU1025
+ 2999 0490 B3F80224 		ldrh	r2, [r3, #1026]
+ 3000 0494 6FEA4242 		mvn	r2, r2, lsl #17
+ 3001 0498 6FEA5242 		mvn	r2, r2, lsr #17
+ 3002 049c 92B2     		uxth	r2, r2
+ 3003 049e A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 3004 04a2 12E0     		b	.L114
+ 3005              	.LVL371:
+ 3006              	.L115:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3007              		.loc 1 497 11 discriminator 10 view .LVU1026
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3008              		.loc 1 497 11 discriminator 10 view .LVU1027
+ 3009 04a4 7208     		lsrs	r2, r6, #1
+ 3010              	.LVL372:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3011              		.loc 1 497 11 discriminator 10 view .LVU1028
+ 3012 04a6 16F0010F 		tst	r6, #1
+ 3013 04aa 00D0     		beq	.L116
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3014              		.loc 1 497 11 discriminator 12 view .LVU1029
+ 3015 04ac 0132     		adds	r2, r2, #1
+ 3016              	.LVL373:
+ 3017              	.L116:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3018              		.loc 1 497 11 discriminator 14 view .LVU1030
+ 3019 04ae 9202     		lsls	r2, r2, #10
+ 3020              	.LVL374:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3021              		.loc 1 497 11 is_stmt 0 discriminator 14 view .LVU1031
+ 3022 04b0 92B2     		uxth	r2, r2
+ 3023 04b2 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 3024 04b6 08E0     		b	.L114
+ 3025              	.LVL375:
+ 3026              	.L111:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3027              		.loc 1 497 11 discriminator 14 view .LVU1032
+ 3028              	.LBE96:
+ 3029              	.LBE95:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3030              		.loc 1 497 11 is_stmt 1 discriminator 16 view .LVU1033
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3031              		.loc 1 497 11 discriminator 16 view .LVU1034
+ 3032              	.LBB97:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3033              		.loc 1 497 11 discriminator 16 view .LVU1035
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3034              		.loc 1 497 11 discriminator 16 view .LVU1036
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3035              		.loc 1 497 11 discriminator 16 view .LVU1037
+ARM GAS  /tmp/cc2t6zYn.s 			page 79
+
+
+ 3036 04b8 B5F85020 		ldrh	r2, [r5, #80]
+ 3037 04bc 15FA82F2 		uxtah	r2, r5, r2
+ 3038              	.LVL376:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3039              		.loc 1 497 11 discriminator 16 view .LVU1038
+ 3040 04c0 02EBC303 		add	r3, r2, r3, lsl #3
+ 3041              	.LVL377:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3042              		.loc 1 497 11 discriminator 16 view .LVU1039
+ 3043 04c4 B2B2     		uxth	r2, r6
+ 3044              	.LVL378:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3045              		.loc 1 497 11 is_stmt 0 discriminator 16 view .LVU1040
+ 3046 04c6 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 3047              	.LVL379:
+ 3048              	.L114:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3049              		.loc 1 497 11 discriminator 16 view .LVU1041
+ 3050              	.LBE97:
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3051              		.loc 1 497 11 is_stmt 1 discriminator 18 view .LVU1042
+ 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           pmabuffer = ep->pmaaddr0;
+ 3052              		.loc 1 497 11 discriminator 18 view .LVU1043
+ 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3053              		.loc 1 498 11 discriminator 18 view .LVU1044
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 3054              		.loc 1 501 11 discriminator 18 view .LVU1045
+ 3055 04ca B3B2     		uxth	r3, r6
+ 3056 04cc 2289     		ldrh	r2, [r4, #8]
+ 3057 04ce 6169     		ldr	r1, [r4, #20]
+ 3058 04d0 2846     		mov	r0, r5
+ 3059              	.LVL380:
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 3060              		.loc 1 501 11 is_stmt 0 discriminator 18 view .LVU1046
+ 3061 04d2 FFF7FEFF 		bl	USB_WritePMA
+ 3062              	.LVL381:
+ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 3063              		.loc 1 501 11 discriminator 18 view .LVU1047
+ 3064 04d6 09E6     		b	.L72
+ 3065              	.LVL382:
+ 3066              	.L119:
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         ep->xfer_len = 0U;
+ 3067              		.loc 1 521 9 is_stmt 1 view .LVU1048
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3068              		.loc 1 522 9 view .LVU1049
+ 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3069              		.loc 1 522 22 is_stmt 0 view .LVU1050
+ 3070 04d8 0022     		movs	r2, #0
+ 3071 04da 8A61     		str	r2, [r1, #24]
+ 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         ep->xfer_len = 0U;
+ 3072              		.loc 1 521 13 view .LVU1051
+ 3073 04dc 1A46     		mov	r2, r3
+ 3074 04de A0E5     		b	.L120
+ 3075              	.LVL383:
+ 3076              	.L121:
+ 3077              	.LBB98:
+ 3078              	.LBB63:
+ARM GAS  /tmp/cc2t6zYn.s 			page 80
+
+
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 3079              		.loc 1 525 7 is_stmt 1 discriminator 2 view .LVU1052
+ 3080 04e0 8AB9     		cbnz	r2, .L124
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 3081              		.loc 1 525 7 discriminator 7 view .LVU1053
+ 3082 04e2 B3F80624 		ldrh	r2, [r3, #1030]
+ 3083              	.LVL384:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 3084              		.loc 1 525 7 is_stmt 0 discriminator 7 view .LVU1054
+ 3085 04e6 92B2     		uxth	r2, r2
+ 3086 04e8 22F4F842 		bic	r2, r2, #31744
+ 3087 04ec 92B2     		uxth	r2, r2
+ 3088 04ee A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 3089              		.loc 1 525 7 is_stmt 1 discriminator 7 view .LVU1055
+ 3090 04f2 B3F80624 		ldrh	r2, [r3, #1030]
+ 3091 04f6 6FEA4242 		mvn	r2, r2, lsl #17
+ 3092 04fa 6FEA5242 		mvn	r2, r2, lsr #17
+ 3093 04fe 92B2     		uxth	r2, r2
+ 3094 0500 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 3095 0504 A3E5     		b	.L123
+ 3096              	.LVL385:
+ 3097              	.L124:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 3098              		.loc 1 525 7 discriminator 8 view .LVU1056
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 3099              		.loc 1 525 7 discriminator 8 view .LVU1057
+ 3100 0506 5108     		lsrs	r1, r2, #1
+ 3101              	.LVL386:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 3102              		.loc 1 525 7 discriminator 8 view .LVU1058
+ 3103 0508 12F0010F 		tst	r2, #1
+ 3104 050c 00D0     		beq	.L125
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 3105              		.loc 1 525 7 discriminator 10 view .LVU1059
+ 3106 050e 0131     		adds	r1, r1, #1
+ 3107              	.LVL387:
+ 3108              	.L125:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 3109              		.loc 1 525 7 discriminator 12 view .LVU1060
+ 3110 0510 8902     		lsls	r1, r1, #10
+ 3111              	.LVL388:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 3112              		.loc 1 525 7 is_stmt 0 discriminator 12 view .LVU1061
+ 3113 0512 89B2     		uxth	r1, r1
+ 3114 0514 A3F80614 		strh	r1, [r3, #1030]	@ movhi
+ 3115 0518 99E5     		b	.L123
+ 3116              	.LVL389:
+ 3117              	.L118:
+ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     }
+ 3118              		.loc 1 525 7 discriminator 12 view .LVU1062
+ 3119              	.LBE63:
+ 3120              	.LBE98:
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 3121              		.loc 1 532 7 is_stmt 1 view .LVU1063
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 3122              		.loc 1 532 13 is_stmt 0 view .LVU1064
+ARM GAS  /tmp/cc2t6zYn.s 			page 81
+
+
+ 3123 051a CB78     		ldrb	r3, [r1, #3]	@ zero_extendqisi2
+ 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 3124              		.loc 1 532 10 view .LVU1065
+ 3125 051c 022B     		cmp	r3, #2
+ 3126 051e 3BD0     		beq	.L160
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 3127              		.loc 1 551 12 is_stmt 1 view .LVU1066
+ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       {
+ 3128              		.loc 1 551 15 is_stmt 0 view .LVU1067
+ 3129 0520 012B     		cmp	r3, #1
+ 3130 0522 40F01B81 		bne	.L151
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 3131              		.loc 1 554 9 is_stmt 1 view .LVU1068
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 3132              		.loc 1 554 15 is_stmt 0 view .LVU1069
+ 3133 0526 8969     		ldr	r1, [r1, #24]
+ 3134              	.LVL390:
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 3135              		.loc 1 554 30 view .LVU1070
+ 3136 0528 2369     		ldr	r3, [r4, #16]
+ 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 3137              		.loc 1 554 12 view .LVU1071
+ 3138 052a 9942     		cmp	r1, r3
+ 3139 052c 40F2CA80 		bls	.L139
+ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           ep->xfer_len -= len;
+ 3140              		.loc 1 556 11 is_stmt 1 view .LVU1072
+ 3141              	.LVL391:
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 3142              		.loc 1 557 11 view .LVU1073
+ 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 3143              		.loc 1 557 24 is_stmt 0 view .LVU1074
+ 3144 0530 C91A     		subs	r1, r1, r3
+ 3145 0532 A161     		str	r1, [r4, #24]
+ 3146              	.L140:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3147              		.loc 1 564 9 is_stmt 1 view .LVU1075
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3148              		.loc 1 564 9 view .LVU1076
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3149              		.loc 1 564 9 view .LVU1077
+ 3150 0534 AAB9     		cbnz	r2, .L141
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3151              		.loc 1 564 9 discriminator 1 view .LVU1078
+ 3152              	.LBB99:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3153              		.loc 1 564 9 discriminator 1 view .LVU1079
+ 3154              	.LVL392:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3155              		.loc 1 564 9 discriminator 1 view .LVU1080
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3156              		.loc 1 564 9 discriminator 1 view .LVU1081
+ 3157 0536 B5F85020 		ldrh	r2, [r5, #80]
+ 3158 053a 15FA82F2 		uxtah	r2, r5, r2
+ 3159              	.LVL393:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3160              		.loc 1 564 9 discriminator 1 view .LVU1082
+ 3161 053e 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ARM GAS  /tmp/cc2t6zYn.s 			page 82
+
+
+ 3162 0540 02EBC102 		add	r2, r2, r1, lsl #3
+ 3163              	.LVL394:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3164              		.loc 1 564 9 discriminator 1 view .LVU1083
+ 3165              	.LBB100:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3166              		.loc 1 564 9 discriminator 1 view .LVU1084
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3167              		.loc 1 564 9 discriminator 1 view .LVU1085
+ 3168 0544 3E2B     		cmp	r3, #62
+ 3169 0546 40F2C180 		bls	.L142
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3170              		.loc 1 564 9 discriminator 3 view .LVU1086
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3171              		.loc 1 564 9 discriminator 3 view .LVU1087
+ 3172 054a 5909     		lsrs	r1, r3, #5
+ 3173              	.LVL395:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3174              		.loc 1 564 9 discriminator 3 view .LVU1088
+ 3175 054c 13F01F0F 		tst	r3, #31
+ 3176 0550 00D1     		bne	.L143
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3177              		.loc 1 564 9 discriminator 5 view .LVU1089
+ 3178 0552 0139     		subs	r1, r1, #1
+ 3179              	.LVL396:
+ 3180              	.L143:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3181              		.loc 1 564 9 discriminator 7 view .LVU1090
+ 3182 0554 6FEAC161 		mvn	r1, r1, lsl #27
+ 3183              	.LVL397:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3184              		.loc 1 564 9 is_stmt 0 discriminator 7 view .LVU1091
+ 3185 0558 6FEA5141 		mvn	r1, r1, lsr #17
+ 3186 055c 89B2     		uxth	r1, r1
+ 3187 055e A2F80214 		strh	r1, [r2, #1026]	@ movhi
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3188              		.loc 1 564 9 is_stmt 1 discriminator 7 view .LVU1092
+ 3189              	.LVL398:
+ 3190              	.L141:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3191              		.loc 1 564 9 is_stmt 0 discriminator 7 view .LVU1093
+ 3192              	.LBE100:
+ 3193              	.LBE99:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3194              		.loc 1 564 9 is_stmt 1 discriminator 18 view .LVU1094
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3195              		.loc 1 564 9 discriminator 18 view .LVU1095
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3196              		.loc 1 564 9 discriminator 18 view .LVU1096
+ 3197              	.LBB102:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3198              		.loc 1 564 9 discriminator 18 view .LVU1097
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3199              		.loc 1 564 9 discriminator 18 view .LVU1098
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3200              		.loc 1 564 9 discriminator 18 view .LVU1099
+ 3201 0562 6278     		ldrb	r2, [r4, #1]	@ zero_extendqisi2
+ARM GAS  /tmp/cc2t6zYn.s 			page 83
+
+
+ 3202 0564 002A     		cmp	r2, #0
+ 3203 0566 40F0EB80 		bne	.L146
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3204              		.loc 1 564 9 discriminator 19 view .LVU1100
+ 3205              	.LBB103:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3206              		.loc 1 564 9 discriminator 19 view .LVU1101
+ 3207              	.LVL399:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3208              		.loc 1 564 9 discriminator 19 view .LVU1102
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3209              		.loc 1 564 9 discriminator 19 view .LVU1103
+ 3210 056a B5F85020 		ldrh	r2, [r5, #80]
+ 3211 056e 15FA82F2 		uxtah	r2, r5, r2
+ 3212              	.LVL400:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3213              		.loc 1 564 9 discriminator 19 view .LVU1104
+ 3214 0572 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 3215 0574 02EBC102 		add	r2, r2, r1, lsl #3
+ 3216              	.LVL401:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3217              		.loc 1 564 9 discriminator 19 view .LVU1105
+ 3218              	.LBB104:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3219              		.loc 1 564 9 discriminator 19 view .LVU1106
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3220              		.loc 1 564 9 discriminator 19 view .LVU1107
+ 3221 0578 3E2B     		cmp	r3, #62
+ 3222 057a 40F2C480 		bls	.L147
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3223              		.loc 1 564 9 discriminator 21 view .LVU1108
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3224              		.loc 1 564 9 discriminator 21 view .LVU1109
+ 3225 057e 5909     		lsrs	r1, r3, #5
+ 3226              	.LVL402:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3227              		.loc 1 564 9 discriminator 21 view .LVU1110
+ 3228 0580 13F01F0F 		tst	r3, #31
+ 3229 0584 00D1     		bne	.L148
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3230              		.loc 1 564 9 discriminator 23 view .LVU1111
+ 3231 0586 0139     		subs	r1, r1, #1
+ 3232              	.LVL403:
+ 3233              	.L148:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3234              		.loc 1 564 9 discriminator 25 view .LVU1112
+ 3235 0588 6FEAC163 		mvn	r3, r1, lsl #27
+ 3236              	.LVL404:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3237              		.loc 1 564 9 is_stmt 0 discriminator 25 view .LVU1113
+ 3238 058c 6FEA5343 		mvn	r3, r3, lsr #17
+ 3239 0590 9BB2     		uxth	r3, r3
+ 3240 0592 A2F80634 		strh	r3, [r2, #1030]	@ movhi
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3241              		.loc 1 564 9 is_stmt 1 discriminator 25 view .LVU1114
+ 3242 0596 5AE5     		b	.L123
+ 3243              	.LVL405:
+ARM GAS  /tmp/cc2t6zYn.s 			page 84
+
+
+ 3244              	.L160:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3245              		.loc 1 564 9 is_stmt 0 discriminator 25 view .LVU1115
+ 3246              	.LBE104:
+ 3247              	.LBE103:
+ 3248              	.LBE102:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3249              		.loc 1 534 9 is_stmt 1 view .LVU1116
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3250              		.loc 1 534 9 view .LVU1117
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3251              		.loc 1 534 9 view .LVU1118
+ 3252 0598 AAB9     		cbnz	r2, .L127
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3253              		.loc 1 534 9 discriminator 1 view .LVU1119
+ 3254              	.LBB107:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3255              		.loc 1 534 9 discriminator 1 view .LVU1120
+ 3256              	.LVL406:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3257              		.loc 1 534 9 discriminator 1 view .LVU1121
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3258              		.loc 1 534 9 discriminator 1 view .LVU1122
+ 3259 059a B0F85030 		ldrh	r3, [r0, #80]
+ 3260 059e 10FA83F3 		uxtah	r3, r0, r3
+ 3261              	.LVL407:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3262              		.loc 1 534 9 discriminator 1 view .LVU1123
+ 3263 05a2 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 3264 05a4 03EBC203 		add	r3, r3, r2, lsl #3
+ 3265              	.LVL408:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3266              		.loc 1 534 9 discriminator 1 view .LVU1124
+ 3267              	.LBB108:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3268              		.loc 1 534 9 discriminator 1 view .LVU1125
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3269              		.loc 1 534 9 discriminator 1 view .LVU1126
+ 3270 05a8 0969     		ldr	r1, [r1, #16]
+ 3271              	.LVL409:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3272              		.loc 1 534 9 is_stmt 0 discriminator 1 view .LVU1127
+ 3273 05aa 3E29     		cmp	r1, #62
+ 3274 05ac 25D9     		bls	.L128
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3275              		.loc 1 534 9 is_stmt 1 discriminator 3 view .LVU1128
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3276              		.loc 1 534 9 discriminator 3 view .LVU1129
+ 3277 05ae 4A09     		lsrs	r2, r1, #5
+ 3278              	.LVL410:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3279              		.loc 1 534 9 discriminator 3 view .LVU1130
+ 3280 05b0 11F01F0F 		tst	r1, #31
+ 3281 05b4 00D1     		bne	.L129
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3282              		.loc 1 534 9 discriminator 5 view .LVU1131
+ 3283 05b6 013A     		subs	r2, r2, #1
+ARM GAS  /tmp/cc2t6zYn.s 			page 85
+
+
+ 3284              	.LVL411:
+ 3285              	.L129:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3286              		.loc 1 534 9 discriminator 7 view .LVU1132
+ 3287 05b8 6FEAC262 		mvn	r2, r2, lsl #27
+ 3288              	.LVL412:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3289              		.loc 1 534 9 is_stmt 0 discriminator 7 view .LVU1133
+ 3290 05bc 6FEA5242 		mvn	r2, r2, lsr #17
+ 3291 05c0 92B2     		uxth	r2, r2
+ 3292 05c2 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3293              		.loc 1 534 9 is_stmt 1 discriminator 7 view .LVU1134
+ 3294              	.LVL413:
+ 3295              	.L127:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3296              		.loc 1 534 9 is_stmt 0 discriminator 7 view .LVU1135
+ 3297              	.LBE108:
+ 3298              	.LBE107:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3299              		.loc 1 534 9 is_stmt 1 discriminator 18 view .LVU1136
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3300              		.loc 1 534 9 discriminator 18 view .LVU1137
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3301              		.loc 1 534 9 discriminator 18 view .LVU1138
+ 3302              	.LBB110:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3303              		.loc 1 534 9 discriminator 18 view .LVU1139
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3304              		.loc 1 534 9 discriminator 18 view .LVU1140
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3305              		.loc 1 534 9 discriminator 18 view .LVU1141
+ 3306 05c6 6378     		ldrb	r3, [r4, #1]	@ zero_extendqisi2
+ 3307 05c8 002B     		cmp	r3, #0
+ 3308 05ca 50D1     		bne	.L132
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3309              		.loc 1 534 9 discriminator 19 view .LVU1142
+ 3310              	.LBB111:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3311              		.loc 1 534 9 discriminator 19 view .LVU1143
+ 3312              	.LVL414:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3313              		.loc 1 534 9 discriminator 19 view .LVU1144
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3314              		.loc 1 534 9 discriminator 19 view .LVU1145
+ 3315 05cc B5F85030 		ldrh	r3, [r5, #80]
+ 3316 05d0 15FA83F3 		uxtah	r3, r5, r3
+ 3317              	.LVL415:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3318              		.loc 1 534 9 discriminator 19 view .LVU1146
+ 3319 05d4 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 3320 05d6 03EBC203 		add	r3, r3, r2, lsl #3
+ 3321              	.LVL416:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3322              		.loc 1 534 9 discriminator 19 view .LVU1147
+ 3323              	.LBB112:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ARM GAS  /tmp/cc2t6zYn.s 			page 86
+
+
+ 3324              		.loc 1 534 9 discriminator 19 view .LVU1148
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3325              		.loc 1 534 9 discriminator 19 view .LVU1149
+ 3326 05da 2169     		ldr	r1, [r4, #16]
+ 3327 05dc 3E29     		cmp	r1, #62
+ 3328 05de 29D9     		bls	.L133
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3329              		.loc 1 534 9 discriminator 21 view .LVU1150
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3330              		.loc 1 534 9 discriminator 21 view .LVU1151
+ 3331 05e0 4A09     		lsrs	r2, r1, #5
+ 3332              	.LVL417:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3333              		.loc 1 534 9 discriminator 21 view .LVU1152
+ 3334 05e2 11F01F0F 		tst	r1, #31
+ 3335 05e6 00D1     		bne	.L134
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3336              		.loc 1 534 9 discriminator 23 view .LVU1153
+ 3337 05e8 013A     		subs	r2, r2, #1
+ 3338              	.LVL418:
+ 3339              	.L134:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3340              		.loc 1 534 9 discriminator 25 view .LVU1154
+ 3341 05ea 6FEAC262 		mvn	r2, r2, lsl #27
+ 3342              	.LVL419:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3343              		.loc 1 534 9 is_stmt 0 discriminator 25 view .LVU1155
+ 3344 05ee 6FEA5242 		mvn	r2, r2, lsr #17
+ 3345 05f2 92B2     		uxth	r2, r2
+ 3346 05f4 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3347              		.loc 1 534 9 is_stmt 1 discriminator 25 view .LVU1156
+ 3348 05f8 3BE0     		b	.L135
+ 3349              	.LVL420:
+ 3350              	.L128:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3351              		.loc 1 534 9 is_stmt 0 discriminator 25 view .LVU1157
+ 3352              	.LBE112:
+ 3353              	.LBE111:
+ 3354              	.LBE110:
+ 3355              	.LBB115:
+ 3356              	.LBB109:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3357              		.loc 1 534 9 is_stmt 1 discriminator 4 view .LVU1158
+ 3358 05fa 89B9     		cbnz	r1, .L130
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3359              		.loc 1 534 9 discriminator 9 view .LVU1159
+ 3360 05fc B3F80224 		ldrh	r2, [r3, #1026]
+ 3361 0600 92B2     		uxth	r2, r2
+ 3362 0602 22F4F842 		bic	r2, r2, #31744
+ 3363 0606 92B2     		uxth	r2, r2
+ 3364 0608 A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3365              		.loc 1 534 9 discriminator 9 view .LVU1160
+ 3366 060c B3F80224 		ldrh	r2, [r3, #1026]
+ 3367 0610 6FEA4242 		mvn	r2, r2, lsl #17
+ 3368 0614 6FEA5242 		mvn	r2, r2, lsr #17
+ARM GAS  /tmp/cc2t6zYn.s 			page 87
+
+
+ 3369 0618 92B2     		uxth	r2, r2
+ 3370 061a A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 3371 061e D2E7     		b	.L127
+ 3372              	.L130:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3373              		.loc 1 534 9 discriminator 10 view .LVU1161
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3374              		.loc 1 534 9 discriminator 10 view .LVU1162
+ 3375 0620 4A08     		lsrs	r2, r1, #1
+ 3376              	.LVL421:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3377              		.loc 1 534 9 discriminator 10 view .LVU1163
+ 3378 0622 11F0010F 		tst	r1, #1
+ 3379 0626 00D0     		beq	.L131
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3380              		.loc 1 534 9 discriminator 12 view .LVU1164
+ 3381 0628 0132     		adds	r2, r2, #1
+ 3382              	.LVL422:
+ 3383              	.L131:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3384              		.loc 1 534 9 discriminator 14 view .LVU1165
+ 3385 062a 9202     		lsls	r2, r2, #10
+ 3386              	.LVL423:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3387              		.loc 1 534 9 is_stmt 0 discriminator 14 view .LVU1166
+ 3388 062c 92B2     		uxth	r2, r2
+ 3389 062e A3F80224 		strh	r2, [r3, #1026]	@ movhi
+ 3390 0632 C8E7     		b	.L127
+ 3391              	.LVL424:
+ 3392              	.L133:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3393              		.loc 1 534 9 discriminator 14 view .LVU1167
+ 3394              	.LBE109:
+ 3395              	.LBE115:
+ 3396              	.LBB116:
+ 3397              	.LBB114:
+ 3398              	.LBB113:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3399              		.loc 1 534 9 is_stmt 1 discriminator 22 view .LVU1168
+ 3400 0634 89B9     		cbnz	r1, .L136
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3401              		.loc 1 534 9 discriminator 27 view .LVU1169
+ 3402 0636 B3F80624 		ldrh	r2, [r3, #1030]
+ 3403 063a 92B2     		uxth	r2, r2
+ 3404 063c 22F4F842 		bic	r2, r2, #31744
+ 3405 0640 92B2     		uxth	r2, r2
+ 3406 0642 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3407              		.loc 1 534 9 discriminator 27 view .LVU1170
+ 3408 0646 B3F80624 		ldrh	r2, [r3, #1030]
+ 3409 064a 6FEA4242 		mvn	r2, r2, lsl #17
+ 3410 064e 6FEA5242 		mvn	r2, r2, lsr #17
+ 3411 0652 92B2     		uxth	r2, r2
+ 3412 0654 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 3413 0658 0BE0     		b	.L135
+ 3414              	.L136:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ARM GAS  /tmp/cc2t6zYn.s 			page 88
+
+
+ 3415              		.loc 1 534 9 discriminator 28 view .LVU1171
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3416              		.loc 1 534 9 discriminator 28 view .LVU1172
+ 3417 065a 4A08     		lsrs	r2, r1, #1
+ 3418              	.LVL425:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3419              		.loc 1 534 9 discriminator 28 view .LVU1173
+ 3420 065c 11F0010F 		tst	r1, #1
+ 3421 0660 00D0     		beq	.L137
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3422              		.loc 1 534 9 discriminator 30 view .LVU1174
+ 3423 0662 0132     		adds	r2, r2, #1
+ 3424              	.LVL426:
+ 3425              	.L137:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3426              		.loc 1 534 9 discriminator 32 view .LVU1175
+ 3427 0664 9202     		lsls	r2, r2, #10
+ 3428              	.LVL427:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3429              		.loc 1 534 9 is_stmt 0 discriminator 32 view .LVU1176
+ 3430 0666 92B2     		uxth	r2, r2
+ 3431 0668 A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 3432 066c 01E0     		b	.L135
+ 3433              	.LVL428:
+ 3434              	.L132:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3435              		.loc 1 534 9 discriminator 32 view .LVU1177
+ 3436              	.LBE113:
+ 3437              	.LBE114:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3438              		.loc 1 534 9 is_stmt 1 discriminator 20 view .LVU1178
+ 3439 066e 012B     		cmp	r3, #1
+ 3440 0670 1DD0     		beq	.L161
+ 3441              	.LVL429:
+ 3442              	.L135:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3443              		.loc 1 534 9 is_stmt 0 discriminator 20 view .LVU1179
+ 3444              	.LBE116:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3445              		.loc 1 534 9 is_stmt 1 discriminator 36 view .LVU1180
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3446              		.loc 1 534 9 discriminator 36 view .LVU1181
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 3447              		.loc 1 537 9 discriminator 36 view .LVU1182
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 3448              		.loc 1 537 15 is_stmt 0 discriminator 36 view .LVU1183
+ 3449 0672 E369     		ldr	r3, [r4, #28]
+ 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         {
+ 3450              		.loc 1 537 12 discriminator 36 view .LVU1184
+ 3451 0674 002B     		cmp	r3, #0
+ 3452 0676 3FF4EAAC 		beq	.L123
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3453              		.loc 1 540 11 is_stmt 1 view .LVU1185
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3454              		.loc 1 540 20 is_stmt 0 view .LVU1186
+ 3455 067a 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ARM GAS  /tmp/cc2t6zYn.s 			page 89
+
+
+ 3456              		.loc 1 540 18 view .LVU1187
+ 3457 067c 35F82210 		ldrh	r1, [r5, r2, lsl #2]
+ 3458              	.LVL430:
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
+ 3459              		.loc 1 543 11 is_stmt 1 view .LVU1188
+ 3460 0680 44F24003 		movw	r3, #16448
+ 3461 0684 03EA0100 		and	r0, r3, r1
+ 3462              	.LVL431:
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
+ 3463              		.loc 1 543 14 is_stmt 0 view .LVU1189
+ 3464 0688 8B43     		bics	r3, r3, r1
+ 3465 068a 02D0     		beq	.L138
+ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****               (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
+ 3466              		.loc 1 543 88 discriminator 1 view .LVU1190
+ 3467 068c 0028     		cmp	r0, #0
+ 3468 068e 7FF4DEAC 		bne	.L123
+ 3469              	.L138:
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 3470              		.loc 1 546 13 is_stmt 1 discriminator 1 view .LVU1191
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 3471              		.loc 1 546 13 discriminator 1 view .LVU1192
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 3472              		.loc 1 546 13 discriminator 1 view .LVU1193
+ 3473              	.LBB117:
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 3474              		.loc 1 546 13 discriminator 1 view .LVU1194
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 3475              		.loc 1 546 13 discriminator 1 view .LVU1195
+ 3476 0692 35F82230 		ldrh	r3, [r5, r2, lsl #2]
+ 3477 0696 9BB2     		uxth	r3, r3
+ 3478 0698 23F4E043 		bic	r3, r3, #28672
+ 3479 069c 23F07003 		bic	r3, r3, #112
+ 3480              	.LVL432:
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 3481              		.loc 1 546 13 discriminator 1 view .LVU1196
+ 3482 06a0 43F40043 		orr	r3, r3, #32768
+ 3483              	.LVL433:
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 3484              		.loc 1 546 13 is_stmt 0 discriminator 1 view .LVU1197
+ 3485 06a4 43F0C003 		orr	r3, r3, #192
+ 3486 06a8 25F82230 		strh	r3, [r5, r2, lsl #2]	@ movhi
+ 3487              	.LBE117:
+ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           }
+ 3488              		.loc 1 546 13 is_stmt 1 discriminator 1 view .LVU1198
+ 3489 06ac CFE4     		b	.L123
+ 3490              	.LVL434:
+ 3491              	.L161:
+ 3492              	.LBB118:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3493              		.loc 1 534 9 discriminator 34 view .LVU1199
+ 3494 06ae B5F85030 		ldrh	r3, [r5, #80]
+ 3495 06b2 15FA83F3 		uxtah	r3, r5, r3
+ 3496              	.LVL435:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3497              		.loc 1 534 9 discriminator 34 view .LVU1200
+ 3498 06b6 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 3499 06b8 03EBC203 		add	r3, r3, r2, lsl #3
+ARM GAS  /tmp/cc2t6zYn.s 			page 90
+
+
+ 3500              	.LVL436:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3501              		.loc 1 534 9 discriminator 34 view .LVU1201
+ 3502 06bc 228A     		ldrh	r2, [r4, #16]
+ 3503 06be A3F80624 		strh	r2, [r3, #1030]	@ movhi
+ 3504 06c2 D6E7     		b	.L135
+ 3505              	.LVL437:
+ 3506              	.L139:
+ 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 3507              		.loc 1 534 9 is_stmt 0 discriminator 34 view .LVU1202
+ 3508              	.LBE118:
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           ep->xfer_len = 0U;
+ 3509              		.loc 1 561 11 is_stmt 1 view .LVU1203
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 3510              		.loc 1 562 11 view .LVU1204
+ 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****         }
+ 3511              		.loc 1 562 24 is_stmt 0 view .LVU1205
+ 3512 06c4 0023     		movs	r3, #0
+ 3513 06c6 A361     		str	r3, [r4, #24]
+ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****           ep->xfer_len = 0U;
+ 3514              		.loc 1 561 15 view .LVU1206
+ 3515 06c8 0B46     		mov	r3, r1
+ 3516 06ca 33E7     		b	.L140
+ 3517              	.LVL438:
+ 3518              	.L142:
+ 3519              	.LBB119:
+ 3520              	.LBB101:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3521              		.loc 1 564 9 is_stmt 1 discriminator 4 view .LVU1207
+ 3522 06cc 8BB9     		cbnz	r3, .L144
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3523              		.loc 1 564 9 discriminator 9 view .LVU1208
+ 3524 06ce B2F80214 		ldrh	r1, [r2, #1026]
+ 3525 06d2 89B2     		uxth	r1, r1
+ 3526 06d4 21F4F841 		bic	r1, r1, #31744
+ 3527 06d8 89B2     		uxth	r1, r1
+ 3528 06da A2F80214 		strh	r1, [r2, #1026]	@ movhi
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3529              		.loc 1 564 9 discriminator 9 view .LVU1209
+ 3530 06de B2F80214 		ldrh	r1, [r2, #1026]
+ 3531 06e2 6FEA4141 		mvn	r1, r1, lsl #17
+ 3532 06e6 6FEA5141 		mvn	r1, r1, lsr #17
+ 3533 06ea 89B2     		uxth	r1, r1
+ 3534 06ec A2F80214 		strh	r1, [r2, #1026]	@ movhi
+ 3535 06f0 37E7     		b	.L141
+ 3536              	.L144:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3537              		.loc 1 564 9 discriminator 10 view .LVU1210
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3538              		.loc 1 564 9 discriminator 10 view .LVU1211
+ 3539 06f2 5908     		lsrs	r1, r3, #1
+ 3540              	.LVL439:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3541              		.loc 1 564 9 discriminator 10 view .LVU1212
+ 3542 06f4 13F0010F 		tst	r3, #1
+ 3543 06f8 00D0     		beq	.L145
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ARM GAS  /tmp/cc2t6zYn.s 			page 91
+
+
+ 3544              		.loc 1 564 9 discriminator 12 view .LVU1213
+ 3545 06fa 0131     		adds	r1, r1, #1
+ 3546              	.LVL440:
+ 3547              	.L145:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3548              		.loc 1 564 9 discriminator 14 view .LVU1214
+ 3549 06fc 8902     		lsls	r1, r1, #10
+ 3550              	.LVL441:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3551              		.loc 1 564 9 is_stmt 0 discriminator 14 view .LVU1215
+ 3552 06fe 89B2     		uxth	r1, r1
+ 3553 0700 A2F80214 		strh	r1, [r2, #1026]	@ movhi
+ 3554 0704 2DE7     		b	.L141
+ 3555              	.LVL442:
+ 3556              	.L147:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3557              		.loc 1 564 9 discriminator 14 view .LVU1216
+ 3558              	.LBE101:
+ 3559              	.LBE119:
+ 3560              	.LBB120:
+ 3561              	.LBB106:
+ 3562              	.LBB105:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3563              		.loc 1 564 9 is_stmt 1 discriminator 22 view .LVU1217
+ 3564 0706 8BB9     		cbnz	r3, .L149
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3565              		.loc 1 564 9 discriminator 27 view .LVU1218
+ 3566 0708 B2F80634 		ldrh	r3, [r2, #1030]
+ 3567              	.LVL443:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3568              		.loc 1 564 9 is_stmt 0 discriminator 27 view .LVU1219
+ 3569 070c 9BB2     		uxth	r3, r3
+ 3570 070e 23F4F843 		bic	r3, r3, #31744
+ 3571 0712 9BB2     		uxth	r3, r3
+ 3572 0714 A2F80634 		strh	r3, [r2, #1030]	@ movhi
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3573              		.loc 1 564 9 is_stmt 1 discriminator 27 view .LVU1220
+ 3574 0718 B2F80634 		ldrh	r3, [r2, #1030]
+ 3575 071c 6FEA4343 		mvn	r3, r3, lsl #17
+ 3576 0720 6FEA5343 		mvn	r3, r3, lsr #17
+ 3577 0724 9BB2     		uxth	r3, r3
+ 3578 0726 A2F80634 		strh	r3, [r2, #1030]	@ movhi
+ 3579 072a 90E4     		b	.L123
+ 3580              	.LVL444:
+ 3581              	.L149:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3582              		.loc 1 564 9 discriminator 28 view .LVU1221
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3583              		.loc 1 564 9 discriminator 28 view .LVU1222
+ 3584 072c 5908     		lsrs	r1, r3, #1
+ 3585              	.LVL445:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3586              		.loc 1 564 9 discriminator 28 view .LVU1223
+ 3587 072e 13F0010F 		tst	r3, #1
+ 3588 0732 00D0     		beq	.L150
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3589              		.loc 1 564 9 discriminator 30 view .LVU1224
+ARM GAS  /tmp/cc2t6zYn.s 			page 92
+
+
+ 3590 0734 0131     		adds	r1, r1, #1
+ 3591              	.LVL446:
+ 3592              	.L150:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3593              		.loc 1 564 9 discriminator 32 view .LVU1225
+ 3594 0736 8B02     		lsls	r3, r1, #10
+ 3595              	.LVL447:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3596              		.loc 1 564 9 is_stmt 0 discriminator 32 view .LVU1226
+ 3597 0738 9BB2     		uxth	r3, r3
+ 3598 073a A2F80634 		strh	r3, [r2, #1030]	@ movhi
+ 3599 073e 86E4     		b	.L123
+ 3600              	.LVL448:
+ 3601              	.L146:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3602              		.loc 1 564 9 discriminator 32 view .LVU1227
+ 3603              	.LBE105:
+ 3604              	.LBE106:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3605              		.loc 1 564 9 is_stmt 1 discriminator 20 view .LVU1228
+ 3606 0740 012A     		cmp	r2, #1
+ 3607 0742 7FF484AC 		bne	.L123
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3608              		.loc 1 564 9 discriminator 34 view .LVU1229
+ 3609 0746 B5F85020 		ldrh	r2, [r5, #80]
+ 3610 074a 15FA82F2 		uxtah	r2, r5, r2
+ 3611              	.LVL449:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3612              		.loc 1 564 9 discriminator 34 view .LVU1230
+ 3613 074e 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 3614 0750 02EBC102 		add	r2, r2, r1, lsl #3
+ 3615              	.LVL450:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3616              		.loc 1 564 9 discriminator 34 view .LVU1231
+ 3617 0754 9BB2     		uxth	r3, r3
+ 3618              	.LVL451:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3619              		.loc 1 564 9 is_stmt 0 discriminator 34 view .LVU1232
+ 3620 0756 A2F80634 		strh	r3, [r2, #1030]	@ movhi
+ 3621 075a 78E4     		b	.L123
+ 3622              	.LVL452:
+ 3623              	.L151:
+ 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3624              		.loc 1 564 9 discriminator 34 view .LVU1233
+ 3625              	.LBE120:
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3626              		.loc 1 568 16 view .LVU1234
+ 3627 075c 0120     		movs	r0, #1
+ 3628              	.LVL453:
+ 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****       }
+ 3629              		.loc 1 568 16 view .LVU1235
+ 3630 075e 87E4     		b	.L117
+ 3631              		.cfi_endproc
+ 3632              	.LFE336:
+ 3634              		.section	.text.USB_ReadPMA,"ax",%progbits
+ 3635              		.align	1
+ 3636              		.global	USB_ReadPMA
+ARM GAS  /tmp/cc2t6zYn.s 			page 93
+
+
+ 3637              		.syntax unified
+ 3638              		.thumb
+ 3639              		.thumb_func
+ 3641              	USB_ReadPMA:
+ 3642              	.LVL454:
+ 3643              	.LFB347:
+ 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** /**
+ 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @brief Copy data from packet memory area (PMA) to user memory buffer
+ 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param   USBx USB peripheral instance register address.
+ 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param   pbUsrBuf pointer to user memory area.
+ 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param   wPMABufAddr address into PMA.
+ 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @param   wNBytes no. of bytes to be copied.
+ 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   * @retval None
+ 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   */
+ 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+ 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** {
+ 3644              		.loc 1 778 1 is_stmt 1 view -0
+ 3645              		.cfi_startproc
+ 3646              		@ args = 0, pretend = 0, frame = 0
+ 3647              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3648              		@ link register save eliminated.
+ 3649              		.loc 1 778 1 is_stmt 0 view .LVU1237
+ 3650 0000 10B4     		push	{r4}
+ 3651              	.LCFI6:
+ 3652              		.cfi_def_cfa_offset 4
+ 3653              		.cfi_offset 4, -4
+ 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t n = (uint32_t)wNBytes >> 1;
+ 3654              		.loc 1 779 3 is_stmt 1 view .LVU1238
+ 3655              		.loc 1 779 34 is_stmt 0 view .LVU1239
+ 3656 0002 5C08     		lsrs	r4, r3, #1
+ 3657              	.LVL455:
+ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t BaseAddr = (uint32_t)USBx;
+ 3658              		.loc 1 780 3 is_stmt 1 view .LVU1240
+ 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t i;
+ 3659              		.loc 1 781 3 view .LVU1241
+ 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint32_t temp;
+ 3660              		.loc 1 782 3 view .LVU1242
+ 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   __IO uint16_t *pdwVal;
+ 3661              		.loc 1 783 3 view .LVU1243
+ 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   uint8_t *pBuf = pbUsrBuf;
+ 3662              		.loc 1 784 3 view .LVU1244
+ 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
+ 3663              		.loc 1 786 3 view .LVU1245
+ 3664              		.loc 1 786 48 is_stmt 0 view .LVU1246
+ 3665 0004 0244     		add	r2, r2, r0
+ 3666              	.LVL456:
+ 3667              		.loc 1 786 48 view .LVU1247
+ 3668 0006 02F58062 		add	r2, r2, #1024
+ 3669              	.LVL457:
+ 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   for (i = n; i != 0U; i--)
+ 3670              		.loc 1 788 3 is_stmt 1 view .LVU1248
+ 3671              		.loc 1 788 3 is_stmt 0 view .LVU1249
+ 3672 000a 07E0     		b	.L163
+ 3673              	.LVL458:
+ARM GAS  /tmp/cc2t6zYn.s 			page 94
+
+
+ 3674              	.L164:
+ 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     temp = *(__IO uint16_t *)pdwVal;
+ 3675              		.loc 1 790 5 is_stmt 1 discriminator 3 view .LVU1250
+ 3676              		.loc 1 790 12 is_stmt 0 discriminator 3 view .LVU1251
+ 3677 000c 32F8020B 		ldrh	r0, [r2], #2
+ 3678              	.LVL459:
+ 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     pdwVal++;
+ 3679              		.loc 1 791 5 is_stmt 1 discriminator 3 view .LVU1252
+ 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
+ 3680              		.loc 1 792 5 discriminator 3 view .LVU1253
+ 3681              		.loc 1 792 11 is_stmt 0 discriminator 3 view .LVU1254
+ 3682 0010 0870     		strb	r0, [r1]
+ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     pBuf++;
+ 3683              		.loc 1 793 5 is_stmt 1 discriminator 3 view .LVU1255
+ 3684              	.LVL460:
+ 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
+ 3685              		.loc 1 794 5 discriminator 3 view .LVU1256
+ 3686              		.loc 1 794 13 is_stmt 0 discriminator 3 view .LVU1257
+ 3687 0012 C0F30720 		ubfx	r0, r0, #8, #8
+ 3688              	.LVL461:
+ 3689              		.loc 1 794 11 discriminator 3 view .LVU1258
+ 3690 0016 4870     		strb	r0, [r1, #1]
+ 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     pBuf++;
+ 3691              		.loc 1 795 5 is_stmt 1 discriminator 3 view .LVU1259
+ 3692              		.loc 1 795 9 is_stmt 0 discriminator 3 view .LVU1260
+ 3693 0018 0231     		adds	r1, r1, #2
+ 3694              	.LVL462:
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 3695              		.loc 1 788 25 is_stmt 1 discriminator 3 view .LVU1261
+ 3696 001a 013C     		subs	r4, r4, #1
+ 3697              	.LVL463:
+ 3698              	.L163:
+ 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 3699              		.loc 1 788 17 discriminator 1 view .LVU1262
+ 3700 001c 002C     		cmp	r4, #0
+ 3701 001e F5D1     		bne	.L164
+ 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #if PMA_ACCESS > 1U
+ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     pdwVal++;
+ 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** #endif /* PMA_ACCESS */
+ 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** 
+ 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   if ((wNBytes % 2U) != 0U)
+ 3702              		.loc 1 802 3 view .LVU1263
+ 3703              		.loc 1 802 6 is_stmt 0 view .LVU1264
+ 3704 0020 13F0010F 		tst	r3, #1
+ 3705 0024 01D0     		beq	.L162
+ 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   {
+ 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     temp = *pdwVal;
+ 3706              		.loc 1 804 5 is_stmt 1 view .LVU1265
+ 3707              		.loc 1 804 12 is_stmt 0 view .LVU1266
+ 3708 0026 1388     		ldrh	r3, [r2]
+ 3709              	.LVL464:
+ 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****     *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
+ 3710              		.loc 1 805 5 is_stmt 1 view .LVU1267
+ 3711              		.loc 1 805 11 is_stmt 0 view .LVU1268
+ARM GAS  /tmp/cc2t6zYn.s 			page 95
+
+
+ 3712 0028 0B70     		strb	r3, [r1]
+ 3713              	.LVL465:
+ 3714              	.L162:
+ 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c ****   }
+ 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c **** }
+ 3715              		.loc 1 807 1 view .LVU1269
+ 3716 002a 5DF8044B 		ldr	r4, [sp], #4
+ 3717              	.LCFI7:
+ 3718              		.cfi_restore 4
+ 3719              		.cfi_def_cfa_offset 0
+ 3720              	.LVL466:
+ 3721              		.loc 1 807 1 view .LVU1270
+ 3722 002e 7047     		bx	lr
+ 3723              		.cfi_endproc
+ 3724              	.LFE347:
+ 3726              		.text
+ 3727              	.Letext0:
+ 3728              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 3729              		.file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 3730              		.file 4 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 3731              		.file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h"
+ARM GAS  /tmp/cc2t6zYn.s 			page 96
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 stm32g4xx_ll_usb.c
+     /tmp/cc2t6zYn.s:21     .text.USB_CoreInit:00000000 $t
+     /tmp/cc2t6zYn.s:27     .text.USB_CoreInit:00000000 USB_CoreInit
+     /tmp/cc2t6zYn.s:56     .text.USB_EnableGlobalInt:00000000 $t
+     /tmp/cc2t6zYn.s:62     .text.USB_EnableGlobalInt:00000000 USB_EnableGlobalInt
+     /tmp/cc2t6zYn.s:92     .text.USB_DisableGlobalInt:00000000 $t
+     /tmp/cc2t6zYn.s:98     .text.USB_DisableGlobalInt:00000000 USB_DisableGlobalInt
+     /tmp/cc2t6zYn.s:126    .text.USB_SetCurrentMode:00000000 $t
+     /tmp/cc2t6zYn.s:132    .text.USB_SetCurrentMode:00000000 USB_SetCurrentMode
+     /tmp/cc2t6zYn.s:152    .text.USB_DevInit:00000000 $t
+     /tmp/cc2t6zYn.s:158    .text.USB_DevInit:00000000 USB_DevInit
+     /tmp/cc2t6zYn.s:200    .text.USB_ActivateEndpoint:00000000 $t
+     /tmp/cc2t6zYn.s:206    .text.USB_ActivateEndpoint:00000000 USB_ActivateEndpoint
+     /tmp/cc2t6zYn.s:243    .text.USB_ActivateEndpoint:00000022 $d
+     /tmp/cc2t6zYn.s:247    .text.USB_ActivateEndpoint:00000026 $t
+     /tmp/cc2t6zYn.s:980    .text.USB_DeactivateEndpoint:00000000 $t
+     /tmp/cc2t6zYn.s:986    .text.USB_DeactivateEndpoint:00000000 USB_DeactivateEndpoint
+     /tmp/cc2t6zYn.s:1390   .text.USB_EPSetStall:00000000 $t
+     /tmp/cc2t6zYn.s:1396   .text.USB_EPSetStall:00000000 USB_EPSetStall
+     /tmp/cc2t6zYn.s:1470   .text.USB_EPClearStall:00000000 $t
+     /tmp/cc2t6zYn.s:1476   .text.USB_EPClearStall:00000000 USB_EPClearStall
+     /tmp/cc2t6zYn.s:1632   .text.USB_StopDevice:00000000 $t
+     /tmp/cc2t6zYn.s:1638   .text.USB_StopDevice:00000000 USB_StopDevice
+     /tmp/cc2t6zYn.s:1669   .text.USB_SetDevAddress:00000000 $t
+     /tmp/cc2t6zYn.s:1675   .text.USB_SetDevAddress:00000000 USB_SetDevAddress
+     /tmp/cc2t6zYn.s:1701   .text.USB_DevConnect:00000000 $t
+     /tmp/cc2t6zYn.s:1707   .text.USB_DevConnect:00000000 USB_DevConnect
+     /tmp/cc2t6zYn.s:1733   .text.USB_DevDisconnect:00000000 $t
+     /tmp/cc2t6zYn.s:1739   .text.USB_DevDisconnect:00000000 USB_DevDisconnect
+     /tmp/cc2t6zYn.s:1763   .text.USB_ReadInterrupts:00000000 $t
+     /tmp/cc2t6zYn.s:1769   .text.USB_ReadInterrupts:00000000 USB_ReadInterrupts
+     /tmp/cc2t6zYn.s:1792   .text.USB_ActivateRemoteWakeup:00000000 $t
+     /tmp/cc2t6zYn.s:1798   .text.USB_ActivateRemoteWakeup:00000000 USB_ActivateRemoteWakeup
+     /tmp/cc2t6zYn.s:1823   .text.USB_DeActivateRemoteWakeup:00000000 $t
+     /tmp/cc2t6zYn.s:1829   .text.USB_DeActivateRemoteWakeup:00000000 USB_DeActivateRemoteWakeup
+     /tmp/cc2t6zYn.s:1855   .text.USB_WritePMA:00000000 $t
+     /tmp/cc2t6zYn.s:1861   .text.USB_WritePMA:00000000 USB_WritePMA
+     /tmp/cc2t6zYn.s:1928   .text.USB_EPStartXfer:00000000 $t
+     /tmp/cc2t6zYn.s:1934   .text.USB_EPStartXfer:00000000 USB_EPStartXfer
+     /tmp/cc2t6zYn.s:3635   .text.USB_ReadPMA:00000000 $t
+     /tmp/cc2t6zYn.s:3641   .text.USB_ReadPMA:00000000 USB_ReadPMA
+
+NO UNDEFINED SYMBOLS
diff --git a/squeow_sw/build/stm32g4xx_ll_usb.o b/squeow_sw/build/stm32g4xx_ll_usb.o
new file mode 100644
index 0000000000000000000000000000000000000000..b6a19134f756571fb72dc881cb172c1866d97514
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literal 0
HcmV?d00001

diff --git a/squeow_sw/build/system_stm32g4xx.d b/squeow_sw/build/system_stm32g4xx.d
new file mode 100644
index 0000000..d3a631c
--- /dev/null
+++ b/squeow_sw/build/system_stm32g4xx.d
@@ -0,0 +1,73 @@
+build/system_stm32g4xx.o: Src/system_stm32g4xx.c \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
diff --git a/squeow_sw/build/system_stm32g4xx.lst b/squeow_sw/build/system_stm32g4xx.lst
new file mode 100644
index 0000000..ef9d1bd
--- /dev/null
+++ b/squeow_sw/build/system_stm32g4xx.lst
@@ -0,0 +1,570 @@
+ARM GAS  /tmp/cc1Ld1Ft.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"system_stm32g4xx.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Src/system_stm32g4xx.c"
+  20              		.section	.text.SystemInit,"ax",%progbits
+  21              		.align	1
+  22              		.global	SystemInit
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	SystemInit:
+  28              	.LFB329:
+   1:Src/system_stm32g4xx.c **** /**
+   2:Src/system_stm32g4xx.c ****   ******************************************************************************
+   3:Src/system_stm32g4xx.c ****   * @file    system_stm32g4xx.c
+   4:Src/system_stm32g4xx.c ****   * @author  MCD Application Team
+   5:Src/system_stm32g4xx.c ****   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
+   6:Src/system_stm32g4xx.c ****   *
+   7:Src/system_stm32g4xx.c ****   *   This file provides two functions and one global variable to be called from
+   8:Src/system_stm32g4xx.c ****   *   user application:
+   9:Src/system_stm32g4xx.c ****   *      - SystemInit(): This function is called at startup just after reset and
+  10:Src/system_stm32g4xx.c ****   *                      before branch to main program. This call is made inside
+  11:Src/system_stm32g4xx.c ****   *                      the "startup_stm32g4xx.s" file.
+  12:Src/system_stm32g4xx.c ****   *
+  13:Src/system_stm32g4xx.c ****   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  14:Src/system_stm32g4xx.c ****   *                                  by the user application to setup the SysTick
+  15:Src/system_stm32g4xx.c ****   *                                  timer or configure other parameters.
+  16:Src/system_stm32g4xx.c ****   *
+  17:Src/system_stm32g4xx.c ****   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  18:Src/system_stm32g4xx.c ****   *                                 be called whenever the core clock is changed
+  19:Src/system_stm32g4xx.c ****   *                                 during program execution.
+  20:Src/system_stm32g4xx.c ****   *
+  21:Src/system_stm32g4xx.c ****   *   After each device reset the HSI (16 MHz) is used as system clock source.
+  22:Src/system_stm32g4xx.c ****   *   Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to
+  23:Src/system_stm32g4xx.c ****   *   configure the system clock before to branch to main program.
+  24:Src/system_stm32g4xx.c ****   *
+  25:Src/system_stm32g4xx.c ****   *   This file configures the system clock as follows:
+  26:Src/system_stm32g4xx.c ****   *=============================================================================
+  27:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  28:Src/system_stm32g4xx.c ****   *        System Clock source                    | HSI
+  29:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  30:Src/system_stm32g4xx.c ****   *        SYSCLK(Hz)                             | 16000000
+ARM GAS  /tmp/cc1Ld1Ft.s 			page 2
+
+
+  31:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  32:Src/system_stm32g4xx.c ****   *        HCLK(Hz)                               | 16000000
+  33:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  34:Src/system_stm32g4xx.c ****   *        AHB Prescaler                          | 1
+  35:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  36:Src/system_stm32g4xx.c ****   *        APB1 Prescaler                         | 1
+  37:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  38:Src/system_stm32g4xx.c ****   *        APB2 Prescaler                         | 1
+  39:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  40:Src/system_stm32g4xx.c ****   *        PLL_M                                  | 1
+  41:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  42:Src/system_stm32g4xx.c ****   *        PLL_N                                  | 16
+  43:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  44:Src/system_stm32g4xx.c ****   *        PLL_P                                  | 7
+  45:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  46:Src/system_stm32g4xx.c ****   *        PLL_Q                                  | 2
+  47:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  48:Src/system_stm32g4xx.c ****   *        PLL_R                                  | 2
+  49:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  50:Src/system_stm32g4xx.c ****   *        Require 48MHz for RNG                  | Disabled
+  51:Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
+  52:Src/system_stm32g4xx.c ****   *=============================================================================
+  53:Src/system_stm32g4xx.c ****   ******************************************************************************
+  54:Src/system_stm32g4xx.c ****   * @attention
+  55:Src/system_stm32g4xx.c ****   *
+  56:Src/system_stm32g4xx.c ****   * Copyright (c) 2019 STMicroelectronics.
+  57:Src/system_stm32g4xx.c ****   * All rights reserved.
+  58:Src/system_stm32g4xx.c ****   *
+  59:Src/system_stm32g4xx.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  60:Src/system_stm32g4xx.c ****   * in the root directory of this software component.
+  61:Src/system_stm32g4xx.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  62:Src/system_stm32g4xx.c ****   *
+  63:Src/system_stm32g4xx.c ****   ******************************************************************************
+  64:Src/system_stm32g4xx.c ****   */
+  65:Src/system_stm32g4xx.c **** 
+  66:Src/system_stm32g4xx.c **** /** @addtogroup CMSIS
+  67:Src/system_stm32g4xx.c ****   * @{
+  68:Src/system_stm32g4xx.c ****   */
+  69:Src/system_stm32g4xx.c **** 
+  70:Src/system_stm32g4xx.c **** /** @addtogroup stm32g4xx_system
+  71:Src/system_stm32g4xx.c ****   * @{
+  72:Src/system_stm32g4xx.c ****   */
+  73:Src/system_stm32g4xx.c **** 
+  74:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Includes
+  75:Src/system_stm32g4xx.c ****   * @{
+  76:Src/system_stm32g4xx.c ****   */
+  77:Src/system_stm32g4xx.c **** 
+  78:Src/system_stm32g4xx.c **** #include "stm32g4xx.h"
+  79:Src/system_stm32g4xx.c **** 
+  80:Src/system_stm32g4xx.c **** #if !defined  (HSE_VALUE)
+  81:Src/system_stm32g4xx.c ****   #define HSE_VALUE     24000000U /*!< Value of the External oscillator in Hz */
+  82:Src/system_stm32g4xx.c **** #endif /* HSE_VALUE */
+  83:Src/system_stm32g4xx.c **** 
+  84:Src/system_stm32g4xx.c **** #if !defined  (HSI_VALUE)
+  85:Src/system_stm32g4xx.c ****   #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
+  86:Src/system_stm32g4xx.c **** #endif /* HSI_VALUE */
+  87:Src/system_stm32g4xx.c **** 
+ARM GAS  /tmp/cc1Ld1Ft.s 			page 3
+
+
+  88:Src/system_stm32g4xx.c **** /**
+  89:Src/system_stm32g4xx.c ****   * @}
+  90:Src/system_stm32g4xx.c ****   */
+  91:Src/system_stm32g4xx.c **** 
+  92:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_TypesDefinitions
+  93:Src/system_stm32g4xx.c ****   * @{
+  94:Src/system_stm32g4xx.c ****   */
+  95:Src/system_stm32g4xx.c **** 
+  96:Src/system_stm32g4xx.c **** /**
+  97:Src/system_stm32g4xx.c ****   * @}
+  98:Src/system_stm32g4xx.c ****   */
+  99:Src/system_stm32g4xx.c **** 
+ 100:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Defines
+ 101:Src/system_stm32g4xx.c ****   * @{
+ 102:Src/system_stm32g4xx.c ****   */
+ 103:Src/system_stm32g4xx.c **** 
+ 104:Src/system_stm32g4xx.c **** /************************* Miscellaneous Configuration ************************/
+ 105:Src/system_stm32g4xx.c **** /* Note: Following vector table addresses must be defined in line with linker
+ 106:Src/system_stm32g4xx.c ****          configuration. */
+ 107:Src/system_stm32g4xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
+ 108:Src/system_stm32g4xx.c ****      anywhere in Flash or Sram, else the vector table is kept at the automatic
+ 109:Src/system_stm32g4xx.c ****      remap of boot address selected */
+ 110:Src/system_stm32g4xx.c **** /* #define USER_VECT_TAB_ADDRESS */
+ 111:Src/system_stm32g4xx.c **** 
+ 112:Src/system_stm32g4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
+ 113:Src/system_stm32g4xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
+ 114:Src/system_stm32g4xx.c ****      in Sram else user remap will be done in Flash. */
+ 115:Src/system_stm32g4xx.c **** /* #define VECT_TAB_SRAM */
+ 116:Src/system_stm32g4xx.c **** #if defined(VECT_TAB_SRAM)
+ 117:Src/system_stm32g4xx.c **** #define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
+ 118:Src/system_stm32g4xx.c ****                                                      This value must be a multiple of 0x200. */
+ 119:Src/system_stm32g4xx.c **** #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+ 120:Src/system_stm32g4xx.c ****                                                      This value must be a multiple of 0x200. */
+ 121:Src/system_stm32g4xx.c **** #else
+ 122:Src/system_stm32g4xx.c **** #define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
+ 123:Src/system_stm32g4xx.c ****                                                      This value must be a multiple of 0x200. */
+ 124:Src/system_stm32g4xx.c **** #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+ 125:Src/system_stm32g4xx.c ****                                                      This value must be a multiple of 0x200. */
+ 126:Src/system_stm32g4xx.c **** #endif /* VECT_TAB_SRAM */
+ 127:Src/system_stm32g4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
+ 128:Src/system_stm32g4xx.c **** /******************************************************************************/
+ 129:Src/system_stm32g4xx.c **** /**
+ 130:Src/system_stm32g4xx.c ****   * @}
+ 131:Src/system_stm32g4xx.c ****   */
+ 132:Src/system_stm32g4xx.c **** 
+ 133:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Macros
+ 134:Src/system_stm32g4xx.c ****   * @{
+ 135:Src/system_stm32g4xx.c ****   */
+ 136:Src/system_stm32g4xx.c **** 
+ 137:Src/system_stm32g4xx.c **** /**
+ 138:Src/system_stm32g4xx.c ****   * @}
+ 139:Src/system_stm32g4xx.c ****   */
+ 140:Src/system_stm32g4xx.c **** 
+ 141:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Variables
+ 142:Src/system_stm32g4xx.c ****   * @{
+ 143:Src/system_stm32g4xx.c ****   */
+ 144:Src/system_stm32g4xx.c ****   /* The SystemCoreClock variable is updated in three ways:
+ARM GAS  /tmp/cc1Ld1Ft.s 			page 4
+
+
+ 145:Src/system_stm32g4xx.c ****       1) by calling CMSIS function SystemCoreClockUpdate()
+ 146:Src/system_stm32g4xx.c ****       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 147:Src/system_stm32g4xx.c ****       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ 148:Src/system_stm32g4xx.c ****          Note: If you use this function to configure the system clock; then there
+ 149:Src/system_stm32g4xx.c ****                is no need to call the 2 first functions listed above, since SystemCoreClock
+ 150:Src/system_stm32g4xx.c ****                variable is updated automatically.
+ 151:Src/system_stm32g4xx.c ****   */
+ 152:Src/system_stm32g4xx.c ****   uint32_t SystemCoreClock = HSI_VALUE;
+ 153:Src/system_stm32g4xx.c **** 
+ 154:Src/system_stm32g4xx.c ****   const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U
+ 155:Src/system_stm32g4xx.c ****   const uint8_t APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+ 156:Src/system_stm32g4xx.c **** 
+ 157:Src/system_stm32g4xx.c **** /**
+ 158:Src/system_stm32g4xx.c ****   * @}
+ 159:Src/system_stm32g4xx.c ****   */
+ 160:Src/system_stm32g4xx.c **** 
+ 161:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
+ 162:Src/system_stm32g4xx.c ****   * @{
+ 163:Src/system_stm32g4xx.c ****   */
+ 164:Src/system_stm32g4xx.c **** 
+ 165:Src/system_stm32g4xx.c **** /**
+ 166:Src/system_stm32g4xx.c ****   * @}
+ 167:Src/system_stm32g4xx.c ****   */
+ 168:Src/system_stm32g4xx.c **** 
+ 169:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Functions
+ 170:Src/system_stm32g4xx.c ****   * @{
+ 171:Src/system_stm32g4xx.c ****   */
+ 172:Src/system_stm32g4xx.c **** 
+ 173:Src/system_stm32g4xx.c **** /**
+ 174:Src/system_stm32g4xx.c ****   * @brief  Setup the microcontroller system.
+ 175:Src/system_stm32g4xx.c ****   * @param  None
+ 176:Src/system_stm32g4xx.c ****   * @retval None
+ 177:Src/system_stm32g4xx.c ****   */
+ 178:Src/system_stm32g4xx.c **** 
+ 179:Src/system_stm32g4xx.c **** void SystemInit(void)
+ 180:Src/system_stm32g4xx.c **** {
+  29              		.loc 1 180 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+ 181:Src/system_stm32g4xx.c ****   /* FPU settings ------------------------------------------------------------*/
+ 182:Src/system_stm32g4xx.c ****   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ 183:Src/system_stm32g4xx.c ****     SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
+  34              		.loc 1 183 5 view .LVU1
+  35              		.loc 1 183 8 is_stmt 0 view .LVU2
+  36 0000 034A     		ldr	r2, .L2
+  37 0002 D2F88830 		ldr	r3, [r2, #136]
+  38              		.loc 1 183 16 view .LVU3
+  39 0006 43F47003 		orr	r3, r3, #15728640
+  40 000a C2F88830 		str	r3, [r2, #136]
+ 184:Src/system_stm32g4xx.c ****   #endif
+ 185:Src/system_stm32g4xx.c **** 
+ 186:Src/system_stm32g4xx.c ****   /* Configure the Vector Table location add offset address ------------------*/
+ 187:Src/system_stm32g4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
+ 188:Src/system_stm32g4xx.c ****   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM 
+ 189:Src/system_stm32g4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
+ARM GAS  /tmp/cc1Ld1Ft.s 			page 5
+
+
+ 190:Src/system_stm32g4xx.c **** }
+  41              		.loc 1 190 1 view .LVU4
+  42 000e 7047     		bx	lr
+  43              	.L3:
+  44              		.align	2
+  45              	.L2:
+  46 0010 00ED00E0 		.word	-536810240
+  47              		.cfi_endproc
+  48              	.LFE329:
+  50              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
+  51              		.align	1
+  52              		.global	SystemCoreClockUpdate
+  53              		.syntax unified
+  54              		.thumb
+  55              		.thumb_func
+  57              	SystemCoreClockUpdate:
+  58              	.LFB330:
+ 191:Src/system_stm32g4xx.c **** 
+ 192:Src/system_stm32g4xx.c **** /**
+ 193:Src/system_stm32g4xx.c ****   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+ 194:Src/system_stm32g4xx.c ****   *         The SystemCoreClock variable contains the core clock (HCLK), it can
+ 195:Src/system_stm32g4xx.c ****   *         be used by the user application to setup the SysTick timer or configure
+ 196:Src/system_stm32g4xx.c ****   *         other parameters.
+ 197:Src/system_stm32g4xx.c ****   *
+ 198:Src/system_stm32g4xx.c ****   * @note   Each time the core clock (HCLK) changes, this function must be called
+ 199:Src/system_stm32g4xx.c ****   *         to update SystemCoreClock variable value. Otherwise, any configuration
+ 200:Src/system_stm32g4xx.c ****   *         based on this variable will be incorrect.
+ 201:Src/system_stm32g4xx.c ****   *
+ 202:Src/system_stm32g4xx.c ****   * @note   - The system frequency computed by this function is not the real
+ 203:Src/system_stm32g4xx.c ****   *           frequency in the chip. It is calculated based on the predefined
+ 204:Src/system_stm32g4xx.c ****   *           constant and the selected clock source:
+ 205:Src/system_stm32g4xx.c ****   *
+ 206:Src/system_stm32g4xx.c ****   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ 207:Src/system_stm32g4xx.c ****   *
+ 208:Src/system_stm32g4xx.c ****   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ 209:Src/system_stm32g4xx.c ****   *
+ 210:Src/system_stm32g4xx.c ****   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+ 211:Src/system_stm32g4xx.c ****   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ 212:Src/system_stm32g4xx.c ****   *
+ 213:Src/system_stm32g4xx.c ****   *         (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value
+ 214:Src/system_stm32g4xx.c ****   *              16 MHz) but the real value may vary depending on the variations
+ 215:Src/system_stm32g4xx.c ****   *              in voltage and temperature.
+ 216:Src/system_stm32g4xx.c ****   *
+ 217:Src/system_stm32g4xx.c ****   *         (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value
+ 218:Src/system_stm32g4xx.c ****   *              24 MHz), user has to ensure that HSE_VALUE is same as the real
+ 219:Src/system_stm32g4xx.c ****   *              frequency of the crystal used. Otherwise, this function may
+ 220:Src/system_stm32g4xx.c ****   *              have wrong result.
+ 221:Src/system_stm32g4xx.c ****   *
+ 222:Src/system_stm32g4xx.c ****   *         - The result of this function could be not correct when using fractional
+ 223:Src/system_stm32g4xx.c ****   *           value for HSE crystal.
+ 224:Src/system_stm32g4xx.c ****   *
+ 225:Src/system_stm32g4xx.c ****   * @param  None
+ 226:Src/system_stm32g4xx.c ****   * @retval None
+ 227:Src/system_stm32g4xx.c ****   */
+ 228:Src/system_stm32g4xx.c **** void SystemCoreClockUpdate(void)
+ 229:Src/system_stm32g4xx.c **** {
+  59              		.loc 1 229 1 is_stmt 1 view -0
+ARM GAS  /tmp/cc1Ld1Ft.s 			page 6
+
+
+  60              		.cfi_startproc
+  61              		@ args = 0, pretend = 0, frame = 0
+  62              		@ frame_needed = 0, uses_anonymous_args = 0
+  63              		@ link register save eliminated.
+ 230:Src/system_stm32g4xx.c ****   uint32_t tmp, pllvco, pllr, pllsource, pllm;
+  64              		.loc 1 230 3 view .LVU6
+ 231:Src/system_stm32g4xx.c **** 
+ 232:Src/system_stm32g4xx.c ****   /* Get SYSCLK source -------------------------------------------------------*/
+ 233:Src/system_stm32g4xx.c ****   switch (RCC->CFGR & RCC_CFGR_SWS)
+  65              		.loc 1 233 3 view .LVU7
+  66              		.loc 1 233 14 is_stmt 0 view .LVU8
+  67 0000 1E4B     		ldr	r3, .L12
+  68 0002 9B68     		ldr	r3, [r3, #8]
+  69              		.loc 1 233 21 view .LVU9
+  70 0004 03F00C03 		and	r3, r3, #12
+  71              		.loc 1 233 3 view .LVU10
+  72 0008 082B     		cmp	r3, #8
+  73 000a 12D0     		beq	.L5
+  74 000c 0C2B     		cmp	r3, #12
+  75 000e 14D0     		beq	.L6
+  76 0010 042B     		cmp	r3, #4
+  77 0012 0AD0     		beq	.L10
+  78              	.L7:
+ 234:Src/system_stm32g4xx.c ****   {
+ 235:Src/system_stm32g4xx.c ****     case 0x04:  /* HSI used as system clock source */
+ 236:Src/system_stm32g4xx.c ****       SystemCoreClock = HSI_VALUE;
+ 237:Src/system_stm32g4xx.c ****       break;
+ 238:Src/system_stm32g4xx.c **** 
+ 239:Src/system_stm32g4xx.c ****     case 0x08:  /* HSE used as system clock source */
+ 240:Src/system_stm32g4xx.c ****       SystemCoreClock = HSE_VALUE;
+ 241:Src/system_stm32g4xx.c ****       break;
+ 242:Src/system_stm32g4xx.c **** 
+ 243:Src/system_stm32g4xx.c ****     case 0x0C:  /* PLL used as system clock  source */
+ 244:Src/system_stm32g4xx.c ****       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ 245:Src/system_stm32g4xx.c ****          SYSCLK = PLL_VCO / PLLR
+ 246:Src/system_stm32g4xx.c ****          */
+ 247:Src/system_stm32g4xx.c ****       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+ 248:Src/system_stm32g4xx.c ****       pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
+ 249:Src/system_stm32g4xx.c ****       if (pllsource == 0x02UL) /* HSI used as PLL clock source */
+ 250:Src/system_stm32g4xx.c ****       {
+ 251:Src/system_stm32g4xx.c ****         pllvco = (HSI_VALUE / pllm);
+ 252:Src/system_stm32g4xx.c ****       }
+ 253:Src/system_stm32g4xx.c ****       else                   /* HSE used as PLL clock source */
+ 254:Src/system_stm32g4xx.c ****       {
+ 255:Src/system_stm32g4xx.c ****         pllvco = (HSE_VALUE / pllm);
+ 256:Src/system_stm32g4xx.c ****       }
+ 257:Src/system_stm32g4xx.c ****       pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
+ 258:Src/system_stm32g4xx.c ****       pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
+ 259:Src/system_stm32g4xx.c ****       SystemCoreClock = pllvco/pllr;
+ 260:Src/system_stm32g4xx.c ****       break;
+ 261:Src/system_stm32g4xx.c **** 
+ 262:Src/system_stm32g4xx.c ****     default:
+ 263:Src/system_stm32g4xx.c ****       break;
+ 264:Src/system_stm32g4xx.c ****   }
+ 265:Src/system_stm32g4xx.c ****   /* Compute HCLK clock frequency --------------------------------------------*/
+ 266:Src/system_stm32g4xx.c ****   /* Get HCLK prescaler */
+ 267:Src/system_stm32g4xx.c ****   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ARM GAS  /tmp/cc1Ld1Ft.s 			page 7
+
+
+  79              		.loc 1 267 3 is_stmt 1 view .LVU11
+  80              		.loc 1 267 28 is_stmt 0 view .LVU12
+  81 0014 194B     		ldr	r3, .L12
+  82 0016 9B68     		ldr	r3, [r3, #8]
+  83              		.loc 1 267 52 view .LVU13
+  84 0018 C3F30313 		ubfx	r3, r3, #4, #4
+  85              		.loc 1 267 22 view .LVU14
+  86 001c 184A     		ldr	r2, .L12+4
+  87 001e D15C     		ldrb	r1, [r2, r3]	@ zero_extendqisi2
+  88              	.LVL0:
+ 268:Src/system_stm32g4xx.c ****   /* HCLK clock frequency */
+ 269:Src/system_stm32g4xx.c ****   SystemCoreClock >>= tmp;
+  89              		.loc 1 269 3 is_stmt 1 view .LVU15
+  90              		.loc 1 269 19 is_stmt 0 view .LVU16
+  91 0020 184A     		ldr	r2, .L12+8
+  92 0022 1368     		ldr	r3, [r2]
+  93 0024 CB40     		lsrs	r3, r3, r1
+  94 0026 1360     		str	r3, [r2]
+ 270:Src/system_stm32g4xx.c **** }
+  95              		.loc 1 270 1 view .LVU17
+  96 0028 7047     		bx	lr
+  97              	.LVL1:
+  98              	.L10:
+ 236:Src/system_stm32g4xx.c ****       break;
+  99              		.loc 1 236 7 is_stmt 1 view .LVU18
+ 236:Src/system_stm32g4xx.c ****       break;
+ 100              		.loc 1 236 23 is_stmt 0 view .LVU19
+ 101 002a 164B     		ldr	r3, .L12+8
+ 102 002c 164A     		ldr	r2, .L12+12
+ 103 002e 1A60     		str	r2, [r3]
+ 237:Src/system_stm32g4xx.c **** 
+ 104              		.loc 1 237 7 is_stmt 1 view .LVU20
+ 105 0030 F0E7     		b	.L7
+ 106              	.L5:
+ 240:Src/system_stm32g4xx.c ****       break;
+ 107              		.loc 1 240 7 view .LVU21
+ 240:Src/system_stm32g4xx.c ****       break;
+ 108              		.loc 1 240 23 is_stmt 0 view .LVU22
+ 109 0032 144B     		ldr	r3, .L12+8
+ 110 0034 154A     		ldr	r2, .L12+16
+ 111 0036 1A60     		str	r2, [r3]
+ 241:Src/system_stm32g4xx.c **** 
+ 112              		.loc 1 241 7 is_stmt 1 view .LVU23
+ 113 0038 ECE7     		b	.L7
+ 114              	.L6:
+ 247:Src/system_stm32g4xx.c ****       pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
+ 115              		.loc 1 247 7 view .LVU24
+ 247:Src/system_stm32g4xx.c ****       pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
+ 116              		.loc 1 247 23 is_stmt 0 view .LVU25
+ 117 003a 104A     		ldr	r2, .L12
+ 118 003c D368     		ldr	r3, [r2, #12]
+ 247:Src/system_stm32g4xx.c ****       pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
+ 119              		.loc 1 247 17 view .LVU26
+ 120 003e 03F00303 		and	r3, r3, #3
+ 121              	.LVL2:
+ 248:Src/system_stm32g4xx.c ****       if (pllsource == 0x02UL) /* HSI used as PLL clock source */
+ 122              		.loc 1 248 7 is_stmt 1 view .LVU27
+ARM GAS  /tmp/cc1Ld1Ft.s 			page 8
+
+
+ 248:Src/system_stm32g4xx.c ****       if (pllsource == 0x02UL) /* HSI used as PLL clock source */
+ 123              		.loc 1 248 19 is_stmt 0 view .LVU28
+ 124 0042 D268     		ldr	r2, [r2, #12]
+ 248:Src/system_stm32g4xx.c ****       if (pllsource == 0x02UL) /* HSI used as PLL clock source */
+ 125              		.loc 1 248 49 view .LVU29
+ 126 0044 C2F30312 		ubfx	r2, r2, #4, #4
+ 248:Src/system_stm32g4xx.c ****       if (pllsource == 0x02UL) /* HSI used as PLL clock source */
+ 127              		.loc 1 248 12 view .LVU30
+ 128 0048 0132     		adds	r2, r2, #1
+ 129              	.LVL3:
+ 249:Src/system_stm32g4xx.c ****       {
+ 130              		.loc 1 249 7 is_stmt 1 view .LVU31
+ 249:Src/system_stm32g4xx.c ****       {
+ 131              		.loc 1 249 10 is_stmt 0 view .LVU32
+ 132 004a 022B     		cmp	r3, #2
+ 133 004c 12D0     		beq	.L11
+ 255:Src/system_stm32g4xx.c ****       }
+ 134              		.loc 1 255 9 is_stmt 1 view .LVU33
+ 255:Src/system_stm32g4xx.c ****       }
+ 135              		.loc 1 255 16 is_stmt 0 view .LVU34
+ 136 004e 0F4B     		ldr	r3, .L12+16
+ 137              	.LVL4:
+ 255:Src/system_stm32g4xx.c ****       }
+ 138              		.loc 1 255 16 view .LVU35
+ 139 0050 B3FBF2F2 		udiv	r2, r3, r2
+ 140              	.LVL5:
+ 141              	.L9:
+ 257:Src/system_stm32g4xx.c ****       pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
+ 142              		.loc 1 257 7 is_stmt 1 view .LVU36
+ 257:Src/system_stm32g4xx.c ****       pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
+ 143              		.loc 1 257 30 is_stmt 0 view .LVU37
+ 144 0054 0949     		ldr	r1, .L12
+ 145 0056 CB68     		ldr	r3, [r1, #12]
+ 257:Src/system_stm32g4xx.c ****       pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
+ 146              		.loc 1 257 60 view .LVU38
+ 147 0058 C3F30623 		ubfx	r3, r3, #8, #7
+ 257:Src/system_stm32g4xx.c ****       pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
+ 148              		.loc 1 257 14 view .LVU39
+ 149 005c 02FB03F3 		mul	r3, r2, r3
+ 150              	.LVL6:
+ 258:Src/system_stm32g4xx.c ****       SystemCoreClock = pllvco/pllr;
+ 151              		.loc 1 258 7 is_stmt 1 view .LVU40
+ 258:Src/system_stm32g4xx.c ****       SystemCoreClock = pllvco/pllr;
+ 152              		.loc 1 258 20 is_stmt 0 view .LVU41
+ 153 0060 CA68     		ldr	r2, [r1, #12]
+ 258:Src/system_stm32g4xx.c ****       SystemCoreClock = pllvco/pllr;
+ 154              		.loc 1 258 50 view .LVU42
+ 155 0062 C2F34162 		ubfx	r2, r2, #25, #2
+ 258:Src/system_stm32g4xx.c ****       SystemCoreClock = pllvco/pllr;
+ 156              		.loc 1 258 57 view .LVU43
+ 157 0066 0132     		adds	r2, r2, #1
+ 258:Src/system_stm32g4xx.c ****       SystemCoreClock = pllvco/pllr;
+ 158              		.loc 1 258 12 view .LVU44
+ 159 0068 5200     		lsls	r2, r2, #1
+ 160              	.LVL7:
+ 259:Src/system_stm32g4xx.c ****       break;
+ 161              		.loc 1 259 7 is_stmt 1 view .LVU45
+ARM GAS  /tmp/cc1Ld1Ft.s 			page 9
+
+
+ 259:Src/system_stm32g4xx.c ****       break;
+ 162              		.loc 1 259 31 is_stmt 0 view .LVU46
+ 163 006a B3FBF2F3 		udiv	r3, r3, r2
+ 164              	.LVL8:
+ 259:Src/system_stm32g4xx.c ****       break;
+ 165              		.loc 1 259 23 view .LVU47
+ 166 006e 054A     		ldr	r2, .L12+8
+ 167              	.LVL9:
+ 259:Src/system_stm32g4xx.c ****       break;
+ 168              		.loc 1 259 23 view .LVU48
+ 169 0070 1360     		str	r3, [r2]
+ 260:Src/system_stm32g4xx.c **** 
+ 170              		.loc 1 260 7 is_stmt 1 view .LVU49
+ 171 0072 CFE7     		b	.L7
+ 172              	.LVL10:
+ 173              	.L11:
+ 251:Src/system_stm32g4xx.c ****       }
+ 174              		.loc 1 251 9 view .LVU50
+ 251:Src/system_stm32g4xx.c ****       }
+ 175              		.loc 1 251 16 is_stmt 0 view .LVU51
+ 176 0074 044B     		ldr	r3, .L12+12
+ 177              	.LVL11:
+ 251:Src/system_stm32g4xx.c ****       }
+ 178              		.loc 1 251 16 view .LVU52
+ 179 0076 B3FBF2F2 		udiv	r2, r3, r2
+ 180              	.LVL12:
+ 251:Src/system_stm32g4xx.c ****       }
+ 181              		.loc 1 251 16 view .LVU53
+ 182 007a EBE7     		b	.L9
+ 183              	.L13:
+ 184              		.align	2
+ 185              	.L12:
+ 186 007c 00100240 		.word	1073876992
+ 187 0080 00000000 		.word	AHBPrescTable
+ 188 0084 00000000 		.word	SystemCoreClock
+ 189 0088 0024F400 		.word	16000000
+ 190 008c 0080BB00 		.word	12288000
+ 191              		.cfi_endproc
+ 192              	.LFE330:
+ 194              		.global	APBPrescTable
+ 195              		.section	.rodata.APBPrescTable,"a"
+ 196              		.align	2
+ 199              	APBPrescTable:
+ 200 0000 00000000 		.ascii	"\000\000\000\000\001\002\003\004"
+ 200      01020304 
+ 201              		.global	AHBPrescTable
+ 202              		.section	.rodata.AHBPrescTable,"a"
+ 203              		.align	2
+ 206              	AHBPrescTable:
+ 207 0000 00000000 		.ascii	"\000\000\000\000\000\000\000\000\001\002\003\004\006"
+ 207      00000000 
+ 207      01020304 
+ 207      06
+ 208 000d 070809   		.ascii	"\007\010\011"
+ 209              		.global	SystemCoreClock
+ 210              		.section	.data.SystemCoreClock,"aw"
+ 211              		.align	2
+ARM GAS  /tmp/cc1Ld1Ft.s 			page 10
+
+
+ 214              	SystemCoreClock:
+ 215 0000 0024F400 		.word	16000000
+ 216              		.text
+ 217              	.Letext0:
+ 218              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 219              		.file 3 "Drivers/CMSIS/Include/core_cm4.h"
+ 220              		.file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
+ 221              		.file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ARM GAS  /tmp/cc1Ld1Ft.s 			page 11
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 system_stm32g4xx.c
+     /tmp/cc1Ld1Ft.s:21     .text.SystemInit:00000000 $t
+     /tmp/cc1Ld1Ft.s:27     .text.SystemInit:00000000 SystemInit
+     /tmp/cc1Ld1Ft.s:46     .text.SystemInit:00000010 $d
+     /tmp/cc1Ld1Ft.s:51     .text.SystemCoreClockUpdate:00000000 $t
+     /tmp/cc1Ld1Ft.s:57     .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
+     /tmp/cc1Ld1Ft.s:186    .text.SystemCoreClockUpdate:0000007c $d
+     /tmp/cc1Ld1Ft.s:206    .rodata.AHBPrescTable:00000000 AHBPrescTable
+     /tmp/cc1Ld1Ft.s:214    .data.SystemCoreClock:00000000 SystemCoreClock
+     /tmp/cc1Ld1Ft.s:199    .rodata.APBPrescTable:00000000 APBPrescTable
+     /tmp/cc1Ld1Ft.s:196    .rodata.APBPrescTable:00000000 $d
+     /tmp/cc1Ld1Ft.s:203    .rodata.AHBPrescTable:00000000 $d
+     /tmp/cc1Ld1Ft.s:211    .data.SystemCoreClock:00000000 $d
+
+NO UNDEFINED SYMBOLS
diff --git a/squeow_sw/build/system_stm32g4xx.o b/squeow_sw/build/system_stm32g4xx.o
new file mode 100644
index 0000000000000000000000000000000000000000..03975347c7b08d2dcf537f0a79ec0217807ba181
GIT binary patch
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HcmV?d00001

diff --git a/squeow_sw/build/usb_device.d b/squeow_sw/build/usb_device.d
new file mode 100644
index 0000000..eee431b
--- /dev/null
+++ b/squeow_sw/build/usb_device.d
@@ -0,0 +1,96 @@
+build/usb_device.o: Src/usb_device.c Inc/usb_device.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \
+ Inc/usbd_conf.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \
+ Inc/usbd_desc.h \
+ Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Inc/usbd_audio_if.h
+Inc/usb_device.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
+Inc/usbd_conf.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h:
+Inc/usbd_desc.h:
+Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Inc/usbd_audio_if.h:
diff --git a/squeow_sw/build/usb_device.lst b/squeow_sw/build/usb_device.lst
new file mode 100644
index 0000000..ce7b331
--- /dev/null
+++ b/squeow_sw/build/usb_device.lst
@@ -0,0 +1,245 @@
+ARM GAS  /tmp/ccKCpqw4.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"usb_device.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Src/usb_device.c"
+  20              		.section	.text.MX_USB_Device_Init,"ax",%progbits
+  21              		.align	1
+  22              		.global	MX_USB_Device_Init
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	MX_USB_Device_Init:
+  28              	.LFB333:
+   1:Src/usb_device.c **** /* USER CODE BEGIN Header */
+   2:Src/usb_device.c **** /**
+   3:Src/usb_device.c ****   ******************************************************************************
+   4:Src/usb_device.c ****   * @file           : usb_device.c
+   5:Src/usb_device.c ****   * @version        : v3.0_Cube
+   6:Src/usb_device.c ****   * @brief          : This file implements the USB Device
+   7:Src/usb_device.c ****   ******************************************************************************
+   8:Src/usb_device.c ****   * @attention
+   9:Src/usb_device.c ****   *
+  10:Src/usb_device.c ****   * Copyright (c) 2022 STMicroelectronics.
+  11:Src/usb_device.c ****   * All rights reserved.
+  12:Src/usb_device.c ****   *
+  13:Src/usb_device.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  14:Src/usb_device.c ****   * in the root directory of this software component.
+  15:Src/usb_device.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  16:Src/usb_device.c ****   *
+  17:Src/usb_device.c ****   ******************************************************************************
+  18:Src/usb_device.c ****   */
+  19:Src/usb_device.c **** /* USER CODE END Header */
+  20:Src/usb_device.c **** 
+  21:Src/usb_device.c **** /* Includes ------------------------------------------------------------------*/
+  22:Src/usb_device.c **** 
+  23:Src/usb_device.c **** #include "usb_device.h"
+  24:Src/usb_device.c **** #include "usbd_core.h"
+  25:Src/usb_device.c **** #include "usbd_desc.h"
+  26:Src/usb_device.c **** #include "usbd_audio.h"
+  27:Src/usb_device.c **** #include "usbd_audio_if.h"
+  28:Src/usb_device.c **** 
+  29:Src/usb_device.c **** /* USER CODE BEGIN Includes */
+  30:Src/usb_device.c **** 
+ARM GAS  /tmp/ccKCpqw4.s 			page 2
+
+
+  31:Src/usb_device.c **** /* USER CODE END Includes */
+  32:Src/usb_device.c **** 
+  33:Src/usb_device.c **** /* USER CODE BEGIN PV */
+  34:Src/usb_device.c **** /* Private variables ---------------------------------------------------------*/
+  35:Src/usb_device.c **** 
+  36:Src/usb_device.c **** /* USER CODE END PV */
+  37:Src/usb_device.c **** 
+  38:Src/usb_device.c **** /* USER CODE BEGIN PFP */
+  39:Src/usb_device.c **** /* Private function prototypes -----------------------------------------------*/
+  40:Src/usb_device.c **** 
+  41:Src/usb_device.c **** /* USER CODE END PFP */
+  42:Src/usb_device.c **** 
+  43:Src/usb_device.c **** extern void Error_Handler(void);
+  44:Src/usb_device.c **** /* USB Device Core handle declaration. */
+  45:Src/usb_device.c **** USBD_HandleTypeDef hUsbDeviceFS;
+  46:Src/usb_device.c **** extern USBD_DescriptorsTypeDef AUDIO_Desc;
+  47:Src/usb_device.c **** 
+  48:Src/usb_device.c **** /*
+  49:Src/usb_device.c ****  * -- Insert your variables declaration here --
+  50:Src/usb_device.c ****  */
+  51:Src/usb_device.c **** /* USER CODE BEGIN 0 */
+  52:Src/usb_device.c **** 
+  53:Src/usb_device.c **** /* USER CODE END 0 */
+  54:Src/usb_device.c **** 
+  55:Src/usb_device.c **** /*
+  56:Src/usb_device.c ****  * -- Insert your external function declaration here --
+  57:Src/usb_device.c ****  */
+  58:Src/usb_device.c **** /* USER CODE BEGIN 1 */
+  59:Src/usb_device.c **** 
+  60:Src/usb_device.c **** /* USER CODE END 1 */
+  61:Src/usb_device.c **** 
+  62:Src/usb_device.c **** /**
+  63:Src/usb_device.c ****   * Init USB device Library, add supported class and start the library
+  64:Src/usb_device.c ****   * @retval None
+  65:Src/usb_device.c ****   */
+  66:Src/usb_device.c **** void MX_USB_Device_Init(void)
+  67:Src/usb_device.c **** {
+  29              		.loc 1 67 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33 0000 08B5     		push	{r3, lr}
+  34              	.LCFI0:
+  35              		.cfi_def_cfa_offset 8
+  36              		.cfi_offset 3, -8
+  37              		.cfi_offset 14, -4
+  68:Src/usb_device.c ****   /* USER CODE BEGIN USB_Device_Init_PreTreatment */
+  69:Src/usb_device.c **** 
+  70:Src/usb_device.c ****   /* USER CODE END USB_Device_Init_PreTreatment */
+  71:Src/usb_device.c **** 
+  72:Src/usb_device.c ****   /* Init Device Library, add supported class and start the library. */
+  73:Src/usb_device.c ****   if (USBD_Init(&hUsbDeviceFS, &AUDIO_Desc, DEVICE_FS) != USBD_OK) {
+  38              		.loc 1 73 3 view .LVU1
+  39              		.loc 1 73 7 is_stmt 0 view .LVU2
+  40 0002 0022     		movs	r2, #0
+  41 0004 0F49     		ldr	r1, .L11
+  42 0006 1048     		ldr	r0, .L11+4
+ARM GAS  /tmp/ccKCpqw4.s 			page 3
+
+
+  43 0008 FFF7FEFF 		bl	USBD_Init
+  44              	.LVL0:
+  45              		.loc 1 73 6 view .LVU3
+  46 000c 70B9     		cbnz	r0, .L7
+  47              	.L2:
+  74:Src/usb_device.c ****     Error_Handler();
+  75:Src/usb_device.c ****   }
+  76:Src/usb_device.c ****   if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_AUDIO) != USBD_OK) {
+  48              		.loc 1 76 3 is_stmt 1 view .LVU4
+  49              		.loc 1 76 7 is_stmt 0 view .LVU5
+  50 000e 0F49     		ldr	r1, .L11+8
+  51 0010 0D48     		ldr	r0, .L11+4
+  52 0012 FFF7FEFF 		bl	USBD_RegisterClass
+  53              	.LVL1:
+  54              		.loc 1 76 6 view .LVU6
+  55 0016 60B9     		cbnz	r0, .L8
+  56              	.L3:
+  77:Src/usb_device.c ****     Error_Handler();
+  78:Src/usb_device.c ****   }
+  79:Src/usb_device.c ****   if (USBD_AUDIO_RegisterInterface(&hUsbDeviceFS, &USBD_AUDIO_fops_FS) != USBD_OK) {
+  57              		.loc 1 79 3 is_stmt 1 view .LVU7
+  58              		.loc 1 79 7 is_stmt 0 view .LVU8
+  59 0018 0D49     		ldr	r1, .L11+12
+  60 001a 0B48     		ldr	r0, .L11+4
+  61 001c FFF7FEFF 		bl	USBD_AUDIO_RegisterInterface
+  62              	.LVL2:
+  63              		.loc 1 79 6 view .LVU9
+  64 0020 50B9     		cbnz	r0, .L9
+  65              	.L4:
+  80:Src/usb_device.c ****     Error_Handler();
+  81:Src/usb_device.c ****   }
+  82:Src/usb_device.c ****   if (USBD_Start(&hUsbDeviceFS) != USBD_OK) {
+  66              		.loc 1 82 3 is_stmt 1 view .LVU10
+  67              		.loc 1 82 7 is_stmt 0 view .LVU11
+  68 0022 0948     		ldr	r0, .L11+4
+  69 0024 FFF7FEFF 		bl	USBD_Start
+  70              	.LVL3:
+  71              		.loc 1 82 6 view .LVU12
+  72 0028 48B9     		cbnz	r0, .L10
+  73              	.L1:
+  83:Src/usb_device.c ****     Error_Handler();
+  84:Src/usb_device.c ****   }
+  85:Src/usb_device.c ****   /* USER CODE BEGIN USB_Device_Init_PostTreatment */
+  86:Src/usb_device.c **** 
+  87:Src/usb_device.c ****   /* USER CODE END USB_Device_Init_PostTreatment */
+  88:Src/usb_device.c **** }
+  74              		.loc 1 88 1 view .LVU13
+  75 002a 08BD     		pop	{r3, pc}
+  76              	.L7:
+  74:Src/usb_device.c ****   }
+  77              		.loc 1 74 5 is_stmt 1 view .LVU14
+  78 002c FFF7FEFF 		bl	Error_Handler
+  79              	.LVL4:
+  80 0030 EDE7     		b	.L2
+  81              	.L8:
+  77:Src/usb_device.c ****   }
+  82              		.loc 1 77 5 view .LVU15
+ARM GAS  /tmp/ccKCpqw4.s 			page 4
+
+
+  83 0032 FFF7FEFF 		bl	Error_Handler
+  84              	.LVL5:
+  85 0036 EFE7     		b	.L3
+  86              	.L9:
+  80:Src/usb_device.c ****   }
+  87              		.loc 1 80 5 view .LVU16
+  88 0038 FFF7FEFF 		bl	Error_Handler
+  89              	.LVL6:
+  90 003c F1E7     		b	.L4
+  91              	.L10:
+  83:Src/usb_device.c ****   }
+  92              		.loc 1 83 5 view .LVU17
+  93 003e FFF7FEFF 		bl	Error_Handler
+  94              	.LVL7:
+  95              		.loc 1 88 1 is_stmt 0 view .LVU18
+  96 0042 F2E7     		b	.L1
+  97              	.L12:
+  98              		.align	2
+  99              	.L11:
+ 100 0044 00000000 		.word	AUDIO_Desc
+ 101 0048 00000000 		.word	hUsbDeviceFS
+ 102 004c 00000000 		.word	USBD_AUDIO
+ 103 0050 00000000 		.word	USBD_AUDIO_fops_FS
+ 104              		.cfi_endproc
+ 105              	.LFE333:
+ 107              		.global	hUsbDeviceFS
+ 108              		.section	.bss.hUsbDeviceFS,"aw",%nobits
+ 109              		.align	2
+ 112              	hUsbDeviceFS:
+ 113 0000 00000000 		.space	720
+ 113      00000000 
+ 113      00000000 
+ 113      00000000 
+ 113      00000000 
+ 114              		.text
+ 115              	.Letext0:
+ 116              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 117              		.file 3 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h"
+ 118              		.file 4 "Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h"
+ 119              		.file 5 "Inc/usbd_desc.h"
+ 120              		.file 6 "Inc/usbd_audio_if.h"
+ 121              		.file 7 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h"
+ARM GAS  /tmp/ccKCpqw4.s 			page 5
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 usb_device.c
+     /tmp/ccKCpqw4.s:21     .text.MX_USB_Device_Init:00000000 $t
+     /tmp/ccKCpqw4.s:27     .text.MX_USB_Device_Init:00000000 MX_USB_Device_Init
+     /tmp/ccKCpqw4.s:100    .text.MX_USB_Device_Init:00000044 $d
+     /tmp/ccKCpqw4.s:112    .bss.hUsbDeviceFS:00000000 hUsbDeviceFS
+     /tmp/ccKCpqw4.s:109    .bss.hUsbDeviceFS:00000000 $d
+
+UNDEFINED SYMBOLS
+USBD_Init
+USBD_RegisterClass
+USBD_AUDIO_RegisterInterface
+USBD_Start
+Error_Handler
+AUDIO_Desc
+USBD_AUDIO
+USBD_AUDIO_fops_FS
diff --git a/squeow_sw/build/usb_device.o b/squeow_sw/build/usb_device.o
new file mode 100644
index 0000000000000000000000000000000000000000..055b33edd3d961b3a8b15ba13138fdcd1b573090
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diff --git a/squeow_sw/build/usbd_audio.d b/squeow_sw/build/usbd_audio.d
new file mode 100644
index 0000000..0abe015
--- /dev/null
+++ b/squeow_sw/build/usbd_audio.d
@@ -0,0 +1,89 @@
+build/usbd_audio.o: \
+ Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c \
+ Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \
+ Inc/usbd_conf.h Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
+Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
+Inc/usbd_conf.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h:
diff --git a/squeow_sw/build/usbd_audio.lst b/squeow_sw/build/usbd_audio.lst
new file mode 100644
index 0000000..3ec1680
--- /dev/null
+++ b/squeow_sw/build/usbd_audio.lst
@@ -0,0 +1,2657 @@
+ARM GAS  /tmp/ccdtFdaF.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"usbd_audio.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c"
+  20              		.section	.text.USBD_AUDIO_GetCfgDesc,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	USBD_AUDIO_GetCfgDesc:
+  27              	.LVL0:
+  28              	.LFB336:
+   1:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+   2:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   ******************************************************************************
+   3:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @file    usbd_audio.c
+   4:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @author  MCD Application Team
+   5:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief   This file provides the Audio core functions.
+   6:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *
+   7:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @verbatim
+   8:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *
+   9:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *          ===================================================================
+  10:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *                                AUDIO Class  Description
+  11:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *          ===================================================================
+  12:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *           This driver manages the Audio Class 1.0 following the "USB Device Class Definition fo
+  13:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *           Audio Devices V1.0 Mar 18, 98".
+  14:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *           This driver implements the following aspects of the specification:
+  15:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Device descriptor management
+  16:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Configuration descriptor management
+  17:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Standard AC Interface Descriptor management
+  18:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - 1 Audio Streaming Interface (with single channel, PCM, Stereo mode)
+  19:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - 1 Audio Streaming Endpoint
+  20:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - 1 Audio Terminal Input (1 channel)
+  21:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Audio Class-Specific AC Interfaces
+  22:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Audio Class-Specific AS Interfaces
+  23:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - AudioControl Requests: only SET_CUR and GET_CUR requests are supported (for Mute)
+  24:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Audio Feature Unit (limited to Mute control)
+  25:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Audio Synchronization type: Asynchronous
+  26:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Single fixed audio sampling rate (configurable in usbd_conf.h file)
+  27:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *          The current audio class version supports the following audio features:
+  28:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Pulse Coded Modulation (PCM) format
+  29:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - sampling rate: 48KHz.
+  30:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Bit resolution: 16
+ARM GAS  /tmp/ccdtFdaF.s 			page 2
+
+
+  31:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Number of channels: 2
+  32:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - No volume control
+  33:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Mute/Unmute capability
+  34:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *             - Asynchronous Endpoints
+  35:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *
+  36:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @note     In HS mode and when the DMA is used, all variables and data structures
+  37:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *           dealing with the DMA during the transaction process should be 32-bit aligned.
+  38:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *
+  39:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *
+  40:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *  @endverbatim
+  41:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *
+  42:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   ******************************************************************************
+  43:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @attention
+  44:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *
+  45:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  46:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * All rights reserved.</center></h2>
+  47:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *
+  48:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * This software component is licensed by ST under Ultimate Liberty license
+  49:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * SLA0044, the "License"; You may not use this file except in compliance with
+  50:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * the License. You may obtain a copy of the License at:
+  51:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *                      www.st.com/SLA0044
+  52:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *
+  53:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   ******************************************************************************
+  54:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+  55:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+  56:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /* BSPDependencies
+  57:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** - "stm32xxxxx_{eval}{discovery}.c"
+  58:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** - "stm32xxxxx_{eval}{discovery}_io.c"
+  59:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** - "stm32xxxxx_{eval}{discovery}_audio.c"
+  60:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** EndBSPDependencies */
+  61:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+  62:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /* Includes ------------------------------------------------------------------*/
+  63:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** #include "usbd_audio.h"
+  64:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** #include "usbd_ctlreq.h"
+  65:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+  66:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+  67:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /** @addtogroup STM32_USB_DEVICE_LIBRARY
+  68:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @{
+  69:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+  70:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+  71:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+  72:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /** @defgroup USBD_AUDIO
+  73:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief usbd core module
+  74:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @{
+  75:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+  76:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+  77:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /** @defgroup USBD_AUDIO_Private_TypesDefinitions
+  78:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @{
+  79:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+  80:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+  81:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @}
+  82:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+  83:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+  84:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+  85:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /** @defgroup USBD_AUDIO_Private_Defines
+  86:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @{
+  87:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ARM GAS  /tmp/ccdtFdaF.s 			page 3
+
+
+  88:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+  89:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @}
+  90:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+  91:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+  92:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+  93:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /** @defgroup USBD_AUDIO_Private_Macros
+  94:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @{
+  95:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+  96:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** #define AUDIO_SAMPLE_FREQ(frq)         (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16)
+  97:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+  98:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** #define AUDIO_PACKET_SZE(frq)          (uint8_t)(((frq * 2U * 2U)/1000U) & 0xFFU), \
+  99:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                        (uint8_t)((((frq * 2U * 2U)/1000U) >> 8) & 0xFFU)
+ 100:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 101:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 102:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @}
+ 103:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 104:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 105:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 106:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /** @defgroup USBD_AUDIO_Private_FunctionPrototypes
+ 107:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @{
+ 108:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 109:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+ 110:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+ 111:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 112:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_Setup(USBD_HandleTypeDef *pdev,
+ 113:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                 USBD_SetupReqTypedef *req);
+ 114:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 115:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t *USBD_AUDIO_GetCfgDesc(uint16_t *length);
+ 116:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t *USBD_AUDIO_GetDeviceQualifierDesc(uint16_t *length);
+ 117:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum);
+ 118:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum);
+ 119:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_EP0_RxReady(USBD_HandleTypeDef *pdev);
+ 120:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_EP0_TxReady(USBD_HandleTypeDef *pdev);
+ 121:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_SOF(USBD_HandleTypeDef *pdev);
+ 122:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 123:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
+ 124:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
+ 125:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static void AUDIO_REQ_GetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+ 126:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static void AUDIO_REQ_SetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+ 127:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 128:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 129:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @}
+ 130:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 131:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 132:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /** @defgroup USBD_AUDIO_Private_Variables
+ 133:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @{
+ 134:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 135:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 136:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** USBD_ClassTypeDef USBD_AUDIO =
+ 137:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 138:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_Init,
+ 139:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_DeInit,
+ 140:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_Setup,
+ 141:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_EP0_TxReady,
+ 142:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_EP0_RxReady,
+ 143:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_DataIn,
+ 144:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_DataOut,
+ARM GAS  /tmp/ccdtFdaF.s 			page 4
+
+
+ 145:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_SOF,
+ 146:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_IsoINIncomplete,
+ 147:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_IsoOutIncomplete,
+ 148:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_GetCfgDesc,
+ 149:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_GetCfgDesc,
+ 150:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_GetCfgDesc,
+ 151:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_GetDeviceQualifierDesc,
+ 152:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** };
+ 153:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 154:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /* USB AUDIO device Configuration Descriptor */
+ 155:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** __ALIGN_BEGIN static uint8_t USBD_AUDIO_CfgDesc[USB_AUDIO_CONFIG_DESC_SIZ] __ALIGN_END =
+ 156:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 157:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Configuration 1 */
+ 158:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x09,                                 /* bLength */
+ 159:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USB_DESC_TYPE_CONFIGURATION,          /* bDescriptorType */
+ 160:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   LOBYTE(USB_AUDIO_CONFIG_DESC_SIZ),    /* wTotalLength  109 bytes*/
+ 161:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   HIBYTE(USB_AUDIO_CONFIG_DESC_SIZ),
+ 162:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x02,                                 /* bNumInterfaces */
+ 163:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bConfigurationValue */
+ 164:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* iConfiguration */
+ 165:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** #if (USBD_SELF_POWERED == 1U)
+ 166:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0xC0,                                 /* bmAttributes: Bus Powered according to user configuratio
+ 167:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** #else
+ 168:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x80,                                 /* bmAttributes: Bus Powered according to user configuratio
+ 169:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** #endif
+ 170:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_MAX_POWER,                       /* bMaxPower = 100 mA */
+ 171:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* 09 byte*/
+ 172:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 173:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* USB Speaker Standard interface descriptor */
+ 174:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_INTERFACE_DESC_SIZE,            /* bLength */
+ 175:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USB_DESC_TYPE_INTERFACE,              /* bDescriptorType */
+ 176:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* bInterfaceNumber */
+ 177:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* bAlternateSetting */
+ 178:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* bNumEndpoints */
+ 179:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USB_DEVICE_CLASS_AUDIO,               /* bInterfaceClass */
+ 180:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_SUBCLASS_AUDIOCONTROL,          /* bInterfaceSubClass */
+ 181:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_PROTOCOL_UNDEFINED,             /* bInterfaceProtocol */
+ 182:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* iInterface */
+ 183:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* 09 byte*/
+ 184:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 185:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* USB Speaker Class-specific AC Interface Descriptor */
+ 186:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_INTERFACE_DESC_SIZE,            /* bLength */
+ 187:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+ 188:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_CONTROL_HEADER,                 /* bDescriptorSubtype */
+ 189:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,          /* 1.00 */             /* bcdADC */
+ 190:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,
+ 191:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x27,                                 /* wTotalLength = 39*/
+ 192:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,
+ 193:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bInCollection */
+ 194:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* baInterfaceNr */
+ 195:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* 09 byte*/
+ 196:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 197:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* USB Speaker Input Terminal Descriptor */
+ 198:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_INPUT_TERMINAL_DESC_SIZE,       /* bLength */
+ 199:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+ 200:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_CONTROL_INPUT_TERMINAL,         /* bDescriptorSubtype */
+ 201:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bTerminalID */
+ARM GAS  /tmp/ccdtFdaF.s 			page 5
+
+
+ 202:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* wTerminalType AUDIO_TERMINAL_USB_STREAMING   0x0101 */
+ 203:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,
+ 204:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* bAssocTerminal */
+ 205:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bNrChannels */
+ 206:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* wChannelConfig 0x0000  Mono */
+ 207:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,
+ 208:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* iChannelNames */
+ 209:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* iTerminal */
+ 210:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* 12 byte*/
+ 211:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 212:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* USB Speaker Audio Feature Unit Descriptor */
+ 213:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x09,                                 /* bLength */
+ 214:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+ 215:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_CONTROL_FEATURE_UNIT,           /* bDescriptorSubtype */
+ 216:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_OUT_STREAMING_CTRL,             /* bUnitID */
+ 217:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bSourceID */
+ 218:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bControlSize */
+ 219:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_CONTROL_MUTE,                   /* bmaControls(0) */
+ 220:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0,                                    /* bmaControls(1) */
+ 221:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* iTerminal */
+ 222:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* 09 byte*/
+ 223:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 224:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /*USB Speaker Output Terminal Descriptor */
+ 225:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x09,      /* bLength */
+ 226:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+ 227:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_CONTROL_OUTPUT_TERMINAL,        /* bDescriptorSubtype */
+ 228:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x03,                                 /* bTerminalID */
+ 229:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* wTerminalType  0x0301*/
+ 230:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x03,
+ 231:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* bAssocTerminal */
+ 232:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x02,                                 /* bSourceID */
+ 233:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* iTerminal */
+ 234:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* 09 byte*/
+ 235:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 236:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Zero Bandwidth */
+ 237:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Interface 1, Alternate Setting 0                                             */
+ 238:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_INTERFACE_DESC_SIZE,            /* bLength */
+ 239:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USB_DESC_TYPE_INTERFACE,              /* bDescriptorType */
+ 240:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bInterfaceNumber */
+ 241:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* bAlternateSetting */
+ 242:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* bNumEndpoints */
+ 243:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USB_DEVICE_CLASS_AUDIO,               /* bInterfaceClass */
+ 244:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_SUBCLASS_AUDIOSTREAMING,        /* bInterfaceSubClass */
+ 245:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_PROTOCOL_UNDEFINED,             /* bInterfaceProtocol */
+ 246:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* iInterface */
+ 247:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* 09 byte*/
+ 248:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 249:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Operational */
+ 250:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Interface 1, Alternate Setting 1                                           */
+ 251:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_INTERFACE_DESC_SIZE,            /* bLength */
+ 252:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USB_DESC_TYPE_INTERFACE,              /* bDescriptorType */
+ 253:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bInterfaceNumber */
+ 254:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bAlternateSetting */
+ 255:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bNumEndpoints */
+ 256:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USB_DEVICE_CLASS_AUDIO,               /* bInterfaceClass */
+ 257:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_SUBCLASS_AUDIOSTREAMING,        /* bInterfaceSubClass */
+ 258:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_PROTOCOL_UNDEFINED,             /* bInterfaceProtocol */
+ARM GAS  /tmp/ccdtFdaF.s 			page 6
+
+
+ 259:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* iInterface */
+ 260:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* 09 byte*/
+ 261:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 262:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* USB Speaker Audio Streaming Interface Descriptor */
+ 263:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_STREAMING_INTERFACE_DESC_SIZE,  /* bLength */
+ 264:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+ 265:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_STREAMING_GENERAL,              /* bDescriptorSubtype */
+ 266:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bTerminalLink */
+ 267:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bDelay */
+ 268:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* wFormatTag AUDIO_FORMAT_PCM  0x0001 */
+ 269:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,
+ 270:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* 07 byte*/
+ 271:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 272:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* USB Speaker Audio Type III Format Interface Descriptor */
+ 273:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x0B,                                 /* bLength */
+ 274:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+ 275:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_STREAMING_FORMAT_TYPE,          /* bDescriptorSubtype */
+ 276:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_FORMAT_TYPE_I,                  /* bFormatType */
+ 277:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x02,                                 /* bNrChannels */
+ 278:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x02,                                 /* bSubFrameSize :  2 Bytes per frame (16bits) */
+ 279:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   16,                                   /* bBitResolution (16-bits per sample) */
+ 280:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,                                 /* bSamFreqType only one frequency supported */
+ 281:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_SAMPLE_FREQ(USBD_AUDIO_FREQ),   /* Audio sampling frequency coded on 3 bytes */
+ 282:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* 11 byte*/
+ 283:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 284:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Endpoint 1 - Standard Descriptor */
+ 285:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_STANDARD_ENDPOINT_DESC_SIZE,    /* bLength */
+ 286:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USB_DESC_TYPE_ENDPOINT,               /* bDescriptorType */
+ 287:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_OUT_EP,                         /* bEndpointAddress 1 out endpoint */
+ 288:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_EP_TYPE_ISOC,                    /* bmAttributes */
+ 289:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_PACKET_SZE(USBD_AUDIO_FREQ),    /* wMaxPacketSize in Bytes (Freq(Samples)*2(Stereo)*2(HalfW
+ 290:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_FS_BINTERVAL,                   /* bInterval */
+ 291:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* bRefresh */
+ 292:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* bSynchAddress */
+ 293:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* 09 byte*/
+ 294:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 295:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Endpoint - Audio Streaming Descriptor*/
+ 296:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_STREAMING_ENDPOINT_DESC_SIZE,   /* bLength */
+ 297:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_ENDPOINT_DESCRIPTOR_TYPE,       /* bDescriptorType */
+ 298:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   AUDIO_ENDPOINT_GENERAL,               /* bDescriptor */
+ 299:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* bmAttributes */
+ 300:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* bLockDelayUnits */
+ 301:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,                                 /* wLockDelay */
+ 302:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,
+ 303:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* 07 byte*/
+ 304:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** } ;
+ 305:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 306:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /* USB Standard Device Descriptor */
+ 307:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** __ALIGN_BEGIN static uint8_t USBD_AUDIO_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END
+ 308:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 309:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USB_LEN_DEV_QUALIFIER_DESC,
+ 310:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USB_DESC_TYPE_DEVICE_QUALIFIER,
+ 311:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,
+ 312:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x02,
+ 313:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,
+ 314:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,
+ 315:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,
+ARM GAS  /tmp/ccdtFdaF.s 			page 7
+
+
+ 316:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x40,
+ 317:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x01,
+ 318:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   0x00,
+ 319:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** };
+ 320:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 321:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 322:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @}
+ 323:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 324:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 325:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /** @defgroup USBD_AUDIO_Private_Functions
+ 326:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @{
+ 327:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 328:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 329:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 330:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_Init
+ 331:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         Initialize the AUDIO interface
+ 332:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: device instance
+ 333:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  cfgidx: Configuration index
+ 334:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 335:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 336:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
+ 337:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 338:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(cfgidx);
+ 339:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 340:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 341:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Allocate Audio structure */
+ 342:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio = USBD_malloc(sizeof(USBD_AUDIO_HandleTypeDef));
+ 343:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 344:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (haudio == NULL)
+ 345:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 346:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     pdev->pClassData = NULL;
+ 347:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     return (uint8_t)USBD_EMEM;
+ 348:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 349:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 350:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->pClassData = (void *)haudio;
+ 351:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 352:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (pdev->dev_speed == USBD_SPEED_HIGH)
+ 353:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 354:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     pdev->ep_out[AUDIO_OUT_EP & 0xFU].bInterval = AUDIO_HS_BINTERVAL;
+ 355:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 356:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   else   /* LOW and FULL-speed endpoints */
+ 357:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 358:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     pdev->ep_out[AUDIO_OUT_EP & 0xFU].bInterval = AUDIO_FS_BINTERVAL;
+ 359:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 360:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 361:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Open EP OUT */
+ 362:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   (void)USBD_LL_OpenEP(pdev, AUDIO_OUT_EP, USBD_EP_TYPE_ISOC, AUDIO_OUT_PACKET);
+ 363:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 1U;
+ 364:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 365:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->alt_setting = 0U;
+ 366:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->offset = AUDIO_OFFSET_UNKNOWN;
+ 367:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->wr_ptr = 0U;
+ 368:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->rd_ptr = 0U;
+ 369:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->rd_enable = 0U;
+ 370:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 371:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Initialize the Audio output Hardware layer */
+ 372:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->Init(USBD_AUDIO_FREQ,
+ARM GAS  /tmp/ccdtFdaF.s 			page 8
+
+
+ 373:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                        AUDIO_DEFAULT_VOLUME,
+ 374:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                        0U) != 0U)
+ 375:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 376:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     return (uint8_t)USBD_FAIL;
+ 377:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 378:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 379:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Prepare Out endpoint to receive 1st packet */
+ 380:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   (void)USBD_LL_PrepareReceive(pdev, AUDIO_OUT_EP, haudio->buffer,
+ 381:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                AUDIO_OUT_PACKET);
+ 382:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 383:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return (uint8_t)USBD_OK;
+ 384:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 385:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 386:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 387:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_Init
+ 388:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         DeInitialize the AUDIO layer
+ 389:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: device instance
+ 390:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  cfgidx: Configuration index
+ 391:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 392:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 393:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
+ 394:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 395:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(cfgidx);
+ 396:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 397:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Open EP OUT */
+ 398:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   (void)USBD_LL_CloseEP(pdev, AUDIO_OUT_EP);
+ 399:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 0U;
+ 400:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->ep_out[AUDIO_OUT_EP & 0xFU].bInterval = 0U;
+ 401:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 402:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* DeInit  physical Interface components */
+ 403:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (pdev->pClassData != NULL)
+ 404:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 405:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->DeInit(0U);
+ 406:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     (void)USBD_free(pdev->pClassData);
+ 407:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     pdev->pClassData = NULL;
+ 408:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 409:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 410:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return (uint8_t)USBD_OK;
+ 411:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 412:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 413:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 414:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_Setup
+ 415:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         Handle the AUDIO specific requests
+ 416:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: instance
+ 417:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  req: usb requests
+ 418:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 419:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 420:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_Setup(USBD_HandleTypeDef *pdev,
+ 421:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                 USBD_SetupReqTypedef *req)
+ 422:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 423:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 424:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   uint16_t len;
+ 425:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   uint8_t *pbuf;
+ 426:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   uint16_t status_info = 0U;
+ 427:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 428:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 429:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+ARM GAS  /tmp/ccdtFdaF.s 			page 9
+
+
+ 430:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 431:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (haudio == NULL)
+ 432:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 433:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     return (uint8_t)USBD_FAIL;
+ 434:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 435:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 436:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   switch (req->bmRequest & USB_REQ_TYPE_MASK)
+ 437:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 438:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     case USB_REQ_TYPE_CLASS:
+ 439:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       switch (req->bRequest)
+ 440:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 441:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         case AUDIO_REQ_GET_CUR:
+ 442:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           AUDIO_REQ_GetCurrent(pdev, req);
+ 443:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 444:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 445:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         case AUDIO_REQ_SET_CUR:
+ 446:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           AUDIO_REQ_SetCurrent(pdev, req);
+ 447:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 448:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 449:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         default:
+ 450:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           USBD_CtlError(pdev, req);
+ 451:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           ret = USBD_FAIL;
+ 452:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 453:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 454:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       break;
+ 455:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 456:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     case USB_REQ_TYPE_STANDARD:
+ 457:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       switch (req->bRequest)
+ 458:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 459:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         case USB_REQ_GET_STATUS:
+ 460:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           if (pdev->dev_state == USBD_STATE_CONFIGURED)
+ 461:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 462:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
+ 463:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 464:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           else
+ 465:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 466:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             USBD_CtlError(pdev, req);
+ 467:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             ret = USBD_FAIL;
+ 468:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 469:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 470:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 471:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         case USB_REQ_GET_DESCRIPTOR:
+ 472:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           if ((req->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE)
+ 473:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 474:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             pbuf = USBD_AUDIO_CfgDesc + 18;
+ 475:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             len = MIN(USB_AUDIO_DESC_SIZ, req->wLength);
+ 476:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 477:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             (void)USBD_CtlSendData(pdev, pbuf, len);
+ 478:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 479:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 480:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 481:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         case USB_REQ_GET_INTERFACE:
+ 482:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           if (pdev->dev_state == USBD_STATE_CONFIGURED)
+ 483:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 484:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             (void)USBD_CtlSendData(pdev, (uint8_t *)&haudio->alt_setting, 1U);
+ 485:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 486:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           else
+ARM GAS  /tmp/ccdtFdaF.s 			page 10
+
+
+ 487:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 488:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             USBD_CtlError(pdev, req);
+ 489:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             ret = USBD_FAIL;
+ 490:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 491:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 492:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 493:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         case USB_REQ_SET_INTERFACE:
+ 494:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           if (pdev->dev_state == USBD_STATE_CONFIGURED)
+ 495:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 496:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             if ((uint8_t)(req->wValue) <= USBD_MAX_NUM_INTERFACES)
+ 497:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             {
+ 498:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****               haudio->alt_setting = (uint8_t)(req->wValue);
+ 499:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             }
+ 500:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             else
+ 501:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             {
+ 502:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****               /* Call the error management function (command will be NAKed */
+ 503:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****               USBD_CtlError(pdev, req);
+ 504:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****               ret = USBD_FAIL;
+ 505:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             }
+ 506:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 507:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           else
+ 508:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 509:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             USBD_CtlError(pdev, req);
+ 510:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             ret = USBD_FAIL;
+ 511:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 512:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 513:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 514:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         case USB_REQ_CLEAR_FEATURE:
+ 515:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 516:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 517:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         default:
+ 518:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           USBD_CtlError(pdev, req);
+ 519:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           ret = USBD_FAIL;
+ 520:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 521:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 522:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       break;
+ 523:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     default:
+ 524:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       USBD_CtlError(pdev, req);
+ 525:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       ret = USBD_FAIL;
+ 526:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       break;
+ 527:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 528:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 529:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return (uint8_t)ret;
+ 530:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 531:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 532:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 533:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 534:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_GetCfgDesc
+ 535:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         return configuration descriptor
+ 536:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  speed : current device speed
+ 537:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  length : pointer data length
+ 538:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval pointer to descriptor buffer
+ 539:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 540:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t *USBD_AUDIO_GetCfgDesc(uint16_t *length)
+ 541:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+  29              		.loc 1 541 1 view -0
+  30              		.cfi_startproc
+ARM GAS  /tmp/ccdtFdaF.s 			page 11
+
+
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+ 542:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *length = (uint16_t)sizeof(USBD_AUDIO_CfgDesc);
+  34              		.loc 1 542 3 view .LVU1
+  35              		.loc 1 542 11 is_stmt 0 view .LVU2
+  36 0000 6D23     		movs	r3, #109
+  37 0002 0380     		strh	r3, [r0]	@ movhi
+ 543:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 544:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return USBD_AUDIO_CfgDesc;
+  38              		.loc 1 544 3 is_stmt 1 view .LVU3
+ 545:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+  39              		.loc 1 545 1 is_stmt 0 view .LVU4
+  40 0004 0048     		ldr	r0, .L2
+  41              	.LVL1:
+  42              		.loc 1 545 1 view .LVU5
+  43 0006 7047     		bx	lr
+  44              	.L3:
+  45              		.align	2
+  46              	.L2:
+  47 0008 00000000 		.word	USBD_AUDIO_CfgDesc
+  48              		.cfi_endproc
+  49              	.LFE336:
+  51              		.section	.text.USBD_AUDIO_DataIn,"ax",%progbits
+  52              		.align	1
+  53              		.syntax unified
+  54              		.thumb
+  55              		.thumb_func
+  57              	USBD_AUDIO_DataIn:
+  58              	.LVL2:
+  59              	.LFB337:
+ 546:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 547:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 548:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_DataIn
+ 549:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         handle data IN Stage
+ 550:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: device instance
+ 551:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  epnum: endpoint index
+ 552:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 553:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 554:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
+ 555:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+  60              		.loc 1 555 1 is_stmt 1 view -0
+  61              		.cfi_startproc
+  62              		@ args = 0, pretend = 0, frame = 0
+  63              		@ frame_needed = 0, uses_anonymous_args = 0
+  64              		@ link register save eliminated.
+ 556:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(pdev);
+  65              		.loc 1 556 3 view .LVU7
+ 557:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(epnum);
+  66              		.loc 1 557 3 view .LVU8
+ 558:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 559:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Only OUT data are processed */
+ 560:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return (uint8_t)USBD_OK;
+  67              		.loc 1 560 3 view .LVU9
+ 561:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+  68              		.loc 1 561 1 is_stmt 0 view .LVU10
+  69 0000 0020     		movs	r0, #0
+ARM GAS  /tmp/ccdtFdaF.s 			page 12
+
+
+  70              	.LVL3:
+  71              		.loc 1 561 1 view .LVU11
+  72 0002 7047     		bx	lr
+  73              		.cfi_endproc
+  74              	.LFE337:
+  76              		.section	.text.USBD_AUDIO_EP0_RxReady,"ax",%progbits
+  77              		.align	1
+  78              		.syntax unified
+  79              		.thumb
+  80              		.thumb_func
+  82              	USBD_AUDIO_EP0_RxReady:
+  83              	.LVL4:
+  84              	.LFB338:
+ 562:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 563:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 564:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_EP0_RxReady
+ 565:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         handle EP0 Rx Ready event
+ 566:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: device instance
+ 567:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 568:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 569:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_EP0_RxReady(USBD_HandleTypeDef *pdev)
+ 570:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+  85              		.loc 1 570 1 is_stmt 1 view -0
+  86              		.cfi_startproc
+  87              		@ args = 0, pretend = 0, frame = 0
+  88              		@ frame_needed = 0, uses_anonymous_args = 0
+  89              		.loc 1 570 1 is_stmt 0 view .LVU13
+  90 0000 10B5     		push	{r4, lr}
+  91              	.LCFI0:
+  92              		.cfi_def_cfa_offset 8
+  93              		.cfi_offset 4, -8
+  94              		.cfi_offset 14, -4
+ 571:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+  95              		.loc 1 571 3 is_stmt 1 view .LVU14
+ 572:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+  96              		.loc 1 572 3 view .LVU15
+  97              		.loc 1 572 10 is_stmt 0 view .LVU16
+  98 0002 D0F8BC42 		ldr	r4, [r0, #700]
+  99              	.LVL5:
+ 573:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 574:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (haudio == NULL)
+ 100              		.loc 1 574 3 is_stmt 1 view .LVU17
+ 101              		.loc 1 574 6 is_stmt 0 view .LVU18
+ 102 0006 ECB1     		cbz	r4, .L7
+ 575:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 576:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     return (uint8_t)USBD_FAIL;
+ 577:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 578:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 579:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (haudio->control.cmd == AUDIO_REQ_SET_CUR)
+ 103              		.loc 1 579 3 is_stmt 1 view .LVU19
+ 104              		.loc 1 579 22 is_stmt 0 view .LVU20
+ 105 0008 04F58052 		add	r2, r4, #4096
+ 106 000c 92F88A2B 		ldrb	r2, [r2, #2954]	@ zero_extendqisi2
+ 107              		.loc 1 579 6 view .LVU21
+ 108 0010 012A     		cmp	r2, #1
+ 109 0012 01D0     		beq	.L11
+ 580:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ARM GAS  /tmp/ccdtFdaF.s 			page 13
+
+
+ 581:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     /* In this driver, to simplify code, only SET_CUR request is managed */
+ 582:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 583:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     if (haudio->control.unit == AUDIO_OUT_STREAMING_CTRL)
+ 584:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 585:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->MuteCtl(haudio->control.data[0]);
+ 586:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       haudio->control.cmd = 0U;
+ 587:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       haudio->control.len = 0U;
+ 588:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 589:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 590:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 591:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return (uint8_t)USBD_OK;
+ 110              		.loc 1 591 10 view .LVU22
+ 111 0014 0020     		movs	r0, #0
+ 112              	.LVL6:
+ 113              	.L6:
+ 592:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 114              		.loc 1 592 1 view .LVU23
+ 115 0016 10BD     		pop	{r4, pc}
+ 116              	.LVL7:
+ 117              	.L11:
+ 583:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 118              		.loc 1 583 5 is_stmt 1 view .LVU24
+ 583:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 119              		.loc 1 583 24 is_stmt 0 view .LVU25
+ 120 0018 04F58052 		add	r2, r4, #4096
+ 121 001c 92F8CC2B 		ldrb	r2, [r2, #3020]	@ zero_extendqisi2
+ 583:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 122              		.loc 1 583 8 view .LVU26
+ 123 0020 022A     		cmp	r2, #2
+ 124 0022 01D0     		beq	.L12
+ 591:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 125              		.loc 1 591 10 view .LVU27
+ 126 0024 0020     		movs	r0, #0
+ 127              	.LVL8:
+ 591:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 128              		.loc 1 591 10 view .LVU28
+ 129 0026 F6E7     		b	.L6
+ 130              	.LVL9:
+ 131              	.L12:
+ 585:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       haudio->control.cmd = 0U;
+ 132              		.loc 1 585 7 is_stmt 1 view .LVU29
+ 585:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       haudio->control.cmd = 0U;
+ 133              		.loc 1 585 37 is_stmt 0 view .LVU30
+ 134 0028 D0F8C022 		ldr	r2, [r0, #704]
+ 585:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       haudio->control.cmd = 0U;
+ 135              		.loc 1 585 49 view .LVU31
+ 136 002c 1269     		ldr	r2, [r2, #16]
+ 585:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       haudio->control.cmd = 0U;
+ 137              		.loc 1 585 8 view .LVU32
+ 138 002e 04F58054 		add	r4, r4, #4096
+ 139              	.LVL10:
+ 585:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       haudio->control.cmd = 0U;
+ 140              		.loc 1 585 8 view .LVU33
+ 141 0032 94F88B0B 		ldrb	r0, [r4, #2955]	@ zero_extendqisi2
+ 142              	.LVL11:
+ 585:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       haudio->control.cmd = 0U;
+ 143              		.loc 1 585 8 view .LVU34
+ARM GAS  /tmp/ccdtFdaF.s 			page 14
+
+
+ 144 0036 9047     		blx	r2
+ 145              	.LVL12:
+ 586:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       haudio->control.len = 0U;
+ 146              		.loc 1 586 7 is_stmt 1 view .LVU35
+ 586:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       haudio->control.len = 0U;
+ 147              		.loc 1 586 27 is_stmt 0 view .LVU36
+ 148 0038 0020     		movs	r0, #0
+ 149 003a 84F88A0B 		strb	r0, [r4, #2954]
+ 587:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 150              		.loc 1 587 7 is_stmt 1 view .LVU37
+ 587:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 151              		.loc 1 587 27 is_stmt 0 view .LVU38
+ 152 003e 84F8CB0B 		strb	r0, [r4, #3019]
+ 153 0042 E8E7     		b	.L6
+ 154              	.LVL13:
+ 155              	.L7:
+ 576:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 156              		.loc 1 576 12 view .LVU39
+ 157 0044 0320     		movs	r0, #3
+ 158              	.LVL14:
+ 576:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 159              		.loc 1 576 12 view .LVU40
+ 160 0046 E6E7     		b	.L6
+ 161              		.cfi_endproc
+ 162              	.LFE338:
+ 164              		.section	.text.USBD_AUDIO_EP0_TxReady,"ax",%progbits
+ 165              		.align	1
+ 166              		.syntax unified
+ 167              		.thumb
+ 168              		.thumb_func
+ 170              	USBD_AUDIO_EP0_TxReady:
+ 171              	.LVL15:
+ 172              	.LFB339:
+ 593:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 594:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_EP0_TxReady
+ 595:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         handle EP0 TRx Ready event
+ 596:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: device instance
+ 597:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 598:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 599:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_EP0_TxReady(USBD_HandleTypeDef *pdev)
+ 600:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 173              		.loc 1 600 1 is_stmt 1 view -0
+ 174              		.cfi_startproc
+ 175              		@ args = 0, pretend = 0, frame = 0
+ 176              		@ frame_needed = 0, uses_anonymous_args = 0
+ 177              		@ link register save eliminated.
+ 601:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(pdev);
+ 178              		.loc 1 601 3 view .LVU42
+ 602:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 603:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Only OUT control data are processed */
+ 604:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return (uint8_t)USBD_OK;
+ 179              		.loc 1 604 3 view .LVU43
+ 605:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 180              		.loc 1 605 1 is_stmt 0 view .LVU44
+ 181 0000 0020     		movs	r0, #0
+ 182              	.LVL16:
+ 183              		.loc 1 605 1 view .LVU45
+ARM GAS  /tmp/ccdtFdaF.s 			page 15
+
+
+ 184 0002 7047     		bx	lr
+ 185              		.cfi_endproc
+ 186              	.LFE339:
+ 188              		.section	.text.USBD_AUDIO_SOF,"ax",%progbits
+ 189              		.align	1
+ 190              		.syntax unified
+ 191              		.thumb
+ 192              		.thumb_func
+ 194              	USBD_AUDIO_SOF:
+ 195              	.LVL17:
+ 196              	.LFB340:
+ 606:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 607:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_SOF
+ 608:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         handle SOF event
+ 609:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: device instance
+ 610:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 611:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 612:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_SOF(USBD_HandleTypeDef *pdev)
+ 613:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 197              		.loc 1 613 1 is_stmt 1 view -0
+ 198              		.cfi_startproc
+ 199              		@ args = 0, pretend = 0, frame = 0
+ 200              		@ frame_needed = 0, uses_anonymous_args = 0
+ 201              		@ link register save eliminated.
+ 614:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(pdev);
+ 202              		.loc 1 614 3 view .LVU47
+ 615:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 616:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return (uint8_t)USBD_OK;
+ 203              		.loc 1 616 3 view .LVU48
+ 617:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 204              		.loc 1 617 1 is_stmt 0 view .LVU49
+ 205 0000 0020     		movs	r0, #0
+ 206              	.LVL18:
+ 207              		.loc 1 617 1 view .LVU50
+ 208 0002 7047     		bx	lr
+ 209              		.cfi_endproc
+ 210              	.LFE340:
+ 212              		.section	.text.USBD_AUDIO_IsoINIncomplete,"ax",%progbits
+ 213              		.align	1
+ 214              		.syntax unified
+ 215              		.thumb
+ 216              		.thumb_func
+ 218              	USBD_AUDIO_IsoINIncomplete:
+ 219              	.LVL19:
+ 220              	.LFB342:
+ 618:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 619:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 620:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_SOF
+ 621:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         handle SOF event
+ 622:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: device instance
+ 623:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 624:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 625:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** void USBD_AUDIO_Sync(USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset)
+ 626:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 627:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 628:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   uint32_t BufferSize = AUDIO_TOTAL_BUF_SIZE / 2U;
+ 629:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ARM GAS  /tmp/ccdtFdaF.s 			page 16
+
+
+ 630:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (pdev->pClassData == NULL)
+ 631:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 632:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     return;
+ 633:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 634:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 635:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+ 636:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 637:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->offset = offset;
+ 638:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 639:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (haudio->rd_enable == 1U)
+ 640:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 641:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     haudio->rd_ptr += (uint16_t)BufferSize;
+ 642:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 643:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     if (haudio->rd_ptr == AUDIO_TOTAL_BUF_SIZE)
+ 644:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 645:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       /* roll back */
+ 646:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       haudio->rd_ptr = 0U;
+ 647:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 648:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 649:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 650:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (haudio->rd_ptr > haudio->wr_ptr)
+ 651:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 652:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     if ((haudio->rd_ptr - haudio->wr_ptr) < AUDIO_OUT_PACKET)
+ 653:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 654:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       BufferSize += 4U;
+ 655:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 656:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     else
+ 657:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 658:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       if ((haudio->rd_ptr - haudio->wr_ptr) > (AUDIO_TOTAL_BUF_SIZE - AUDIO_OUT_PACKET))
+ 659:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 660:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         BufferSize -= 4U;
+ 661:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 662:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 663:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 664:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   else
+ 665:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 666:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     if ((haudio->wr_ptr - haudio->rd_ptr) < AUDIO_OUT_PACKET)
+ 667:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 668:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       BufferSize -= 4U;
+ 669:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 670:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     else
+ 671:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 672:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       if ((haudio->wr_ptr - haudio->rd_ptr) > (AUDIO_TOTAL_BUF_SIZE - AUDIO_OUT_PACKET))
+ 673:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 674:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         BufferSize += 4U;
+ 675:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 676:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 677:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 678:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 679:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (haudio->offset == AUDIO_OFFSET_FULL)
+ 680:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 681:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->AudioCmd(&haudio->buffer[0],
+ 682:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                          BufferSize, AUDIO_CMD_PLAY);
+ 683:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     haudio->offset = AUDIO_OFFSET_NONE;
+ 684:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 685:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 686:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ARM GAS  /tmp/ccdtFdaF.s 			page 17
+
+
+ 687:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 688:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_IsoINIncomplete
+ 689:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         handle data ISO IN Incomplete event
+ 690:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: device instance
+ 691:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  epnum: endpoint index
+ 692:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 693:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 694:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum)
+ 695:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 221              		.loc 1 695 1 is_stmt 1 view -0
+ 222              		.cfi_startproc
+ 223              		@ args = 0, pretend = 0, frame = 0
+ 224              		@ frame_needed = 0, uses_anonymous_args = 0
+ 225              		@ link register save eliminated.
+ 696:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(pdev);
+ 226              		.loc 1 696 3 view .LVU52
+ 697:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(epnum);
+ 227              		.loc 1 697 3 view .LVU53
+ 698:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 699:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return (uint8_t)USBD_OK;
+ 228              		.loc 1 699 3 view .LVU54
+ 700:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 229              		.loc 1 700 1 is_stmt 0 view .LVU55
+ 230 0000 0020     		movs	r0, #0
+ 231              	.LVL20:
+ 232              		.loc 1 700 1 view .LVU56
+ 233 0002 7047     		bx	lr
+ 234              		.cfi_endproc
+ 235              	.LFE342:
+ 237              		.section	.text.USBD_AUDIO_IsoOutIncomplete,"ax",%progbits
+ 238              		.align	1
+ 239              		.syntax unified
+ 240              		.thumb
+ 241              		.thumb_func
+ 243              	USBD_AUDIO_IsoOutIncomplete:
+ 244              	.LVL21:
+ 245              	.LFB343:
+ 701:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 702:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_IsoOutIncomplete
+ 703:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         handle data ISO OUT Incomplete event
+ 704:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: device instance
+ 705:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  epnum: endpoint index
+ 706:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 707:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 708:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum)
+ 709:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 246              		.loc 1 709 1 is_stmt 1 view -0
+ 247              		.cfi_startproc
+ 248              		@ args = 0, pretend = 0, frame = 0
+ 249              		@ frame_needed = 0, uses_anonymous_args = 0
+ 250              		@ link register save eliminated.
+ 710:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(pdev);
+ 251              		.loc 1 710 3 view .LVU58
+ 711:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(epnum);
+ 252              		.loc 1 711 3 view .LVU59
+ 712:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 713:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return (uint8_t)USBD_OK;
+ARM GAS  /tmp/ccdtFdaF.s 			page 18
+
+
+ 253              		.loc 1 713 3 view .LVU60
+ 714:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 254              		.loc 1 714 1 is_stmt 0 view .LVU61
+ 255 0000 0020     		movs	r0, #0
+ 256              	.LVL22:
+ 257              		.loc 1 714 1 view .LVU62
+ 258 0002 7047     		bx	lr
+ 259              		.cfi_endproc
+ 260              	.LFE343:
+ 262              		.section	.text.USBD_AUDIO_GetDeviceQualifierDesc,"ax",%progbits
+ 263              		.align	1
+ 264              		.syntax unified
+ 265              		.thumb
+ 266              		.thumb_func
+ 268              	USBD_AUDIO_GetDeviceQualifierDesc:
+ 269              	.LVL23:
+ 270              	.LFB347:
+ 715:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 716:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_DataOut
+ 717:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         handle data OUT Stage
+ 718:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: device instance
+ 719:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  epnum: endpoint index
+ 720:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 721:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 722:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t USBD_AUDIO_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
+ 723:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 724:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   uint16_t PacketSize;
+ 725:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 726:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 727:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+ 728:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 729:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (haudio == NULL)
+ 730:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 731:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     return (uint8_t)USBD_FAIL;
+ 732:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 733:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 734:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (epnum == AUDIO_OUT_EP)
+ 735:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 736:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     /* Get received data packet length */
+ 737:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     PacketSize = (uint16_t)USBD_LL_GetRxDataSize(pdev, epnum);
+ 738:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 739:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     /* Packet received Callback */
+ 740:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->PeriodicTC(&haudio->buffer[haudio->wr_ptr],
+ 741:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                            PacketSize, AUDIO_OUT_TC);
+ 742:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 743:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     /* Increment the Buffer pointer or roll it back when all buffers are full */
+ 744:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     haudio->wr_ptr += PacketSize;
+ 745:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 746:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     if (haudio->wr_ptr == AUDIO_TOTAL_BUF_SIZE)
+ 747:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 748:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       /* All buffers are full: roll back */
+ 749:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       haudio->wr_ptr = 0U;
+ 750:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 751:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       if (haudio->offset == AUDIO_OFFSET_UNKNOWN)
+ 752:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 753:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->AudioCmd(&haudio->buffer[0],
+ 754:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                              AUDIO_TOTAL_BUF_SIZE / 2U,
+ARM GAS  /tmp/ccdtFdaF.s 			page 19
+
+
+ 755:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                              AUDIO_CMD_START);
+ 756:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         haudio->offset = AUDIO_OFFSET_NONE;
+ 757:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 758:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 759:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 760:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     if (haudio->rd_enable == 0U)
+ 761:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 762:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       if (haudio->wr_ptr == (AUDIO_TOTAL_BUF_SIZE / 2U))
+ 763:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 764:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****         haudio->rd_enable = 1U;
+ 765:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 766:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 767:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 768:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     /* Prepare Out endpoint to receive next audio packet */
+ 769:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     (void)USBD_LL_PrepareReceive(pdev, AUDIO_OUT_EP,
+ 770:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                  &haudio->buffer[haudio->wr_ptr],
+ 771:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                  AUDIO_OUT_PACKET);
+ 772:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 773:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 774:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return (uint8_t)USBD_OK;
+ 775:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 776:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 777:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 778:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  AUDIO_Req_GetCurrent
+ 779:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         Handles the GET_CUR Audio control request.
+ 780:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: instance
+ 781:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  req: setup class request
+ 782:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 783:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 784:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static void AUDIO_REQ_GetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 785:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 786:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 787:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+ 788:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 789:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (haudio == NULL)
+ 790:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 791:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     return;
+ 792:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 793:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 794:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   (void)USBD_memset(haudio->control.data, 0, 64U);
+ 795:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 796:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   /* Send the current mute state */
+ 797:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   (void)USBD_CtlSendData(pdev, haudio->control.data, req->wLength);
+ 798:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 799:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 800:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 801:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  AUDIO_Req_SetCurrent
+ 802:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         Handles the SET_CUR Audio control request.
+ 803:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  pdev: instance
+ 804:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  req: setup class request
+ 805:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 806:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 807:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static void AUDIO_REQ_SetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 808:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 809:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 810:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+ 811:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ARM GAS  /tmp/ccdtFdaF.s 			page 20
+
+
+ 812:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (haudio == NULL)
+ 813:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 814:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     return;
+ 815:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 816:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 817:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (req->wLength != 0U)
+ 818:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 819:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     /* Prepare the reception of the buffer over EP0 */
+ 820:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     (void)USBD_CtlPrepareRx(pdev, haudio->control.data, req->wLength);
+ 821:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 822:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     haudio->control.cmd = AUDIO_REQ_SET_CUR;     /* Set the request value */
+ 823:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     haudio->control.len = (uint8_t)req->wLength; /* Set the request data length */
+ 824:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     haudio->control.unit = HIBYTE(req->wIndex);  /* Set the request target unit */
+ 825:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 826:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 827:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 828:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 829:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 830:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  DeviceQualifierDescriptor
+ 831:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *         return Device Qualifier descriptor
+ 832:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  length : pointer data length
+ 833:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval pointer to descriptor buffer
+ 834:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 835:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** static uint8_t *USBD_AUDIO_GetDeviceQualifierDesc(uint16_t *length)
+ 836:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 271              		.loc 1 836 1 is_stmt 1 view -0
+ 272              		.cfi_startproc
+ 273              		@ args = 0, pretend = 0, frame = 0
+ 274              		@ frame_needed = 0, uses_anonymous_args = 0
+ 275              		@ link register save eliminated.
+ 837:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   *length = (uint16_t)sizeof(USBD_AUDIO_DeviceQualifierDesc);
+ 276              		.loc 1 837 3 view .LVU64
+ 277              		.loc 1 837 11 is_stmt 0 view .LVU65
+ 278 0000 0A23     		movs	r3, #10
+ 279 0002 0380     		strh	r3, [r0]	@ movhi
+ 838:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 839:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return USBD_AUDIO_DeviceQualifierDesc;
+ 280              		.loc 1 839 3 is_stmt 1 view .LVU66
+ 840:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 281              		.loc 1 840 1 is_stmt 0 view .LVU67
+ 282 0004 0048     		ldr	r0, .L18
+ 283              	.LVL24:
+ 284              		.loc 1 840 1 view .LVU68
+ 285 0006 7047     		bx	lr
+ 286              	.L19:
+ 287              		.align	2
+ 288              	.L18:
+ 289 0008 00000000 		.word	USBD_AUDIO_DeviceQualifierDesc
+ 290              		.cfi_endproc
+ 291              	.LFE347:
+ 293              		.section	.text.USBD_AUDIO_DataOut,"ax",%progbits
+ 294              		.align	1
+ 295              		.syntax unified
+ 296              		.thumb
+ 297              		.thumb_func
+ 299              	USBD_AUDIO_DataOut:
+ 300              	.LVL25:
+ARM GAS  /tmp/ccdtFdaF.s 			page 21
+
+
+ 301              	.LFB344:
+ 723:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   uint16_t PacketSize;
+ 302              		.loc 1 723 1 is_stmt 1 view -0
+ 303              		.cfi_startproc
+ 304              		@ args = 0, pretend = 0, frame = 0
+ 305              		@ frame_needed = 0, uses_anonymous_args = 0
+ 723:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   uint16_t PacketSize;
+ 306              		.loc 1 723 1 is_stmt 0 view .LVU70
+ 307 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 308              	.LCFI1:
+ 309              		.cfi_def_cfa_offset 24
+ 310              		.cfi_offset 3, -24
+ 311              		.cfi_offset 4, -20
+ 312              		.cfi_offset 5, -16
+ 313              		.cfi_offset 6, -12
+ 314              		.cfi_offset 7, -8
+ 315              		.cfi_offset 14, -4
+ 724:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 316              		.loc 1 724 3 is_stmt 1 view .LVU71
+ 725:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 317              		.loc 1 725 3 view .LVU72
+ 727:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 318              		.loc 1 727 3 view .LVU73
+ 727:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 319              		.loc 1 727 10 is_stmt 0 view .LVU74
+ 320 0002 D0F8BC52 		ldr	r5, [r0, #700]
+ 321              	.LVL26:
+ 729:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 322              		.loc 1 729 3 is_stmt 1 view .LVU75
+ 729:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 323              		.loc 1 729 6 is_stmt 0 view .LVU76
+ 324 0006 002D     		cmp	r5, #0
+ 325 0008 4ED0     		beq	.L24
+ 326 000a 0446     		mov	r4, r0
+ 734:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 327              		.loc 1 734 3 is_stmt 1 view .LVU77
+ 734:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 328              		.loc 1 734 6 is_stmt 0 view .LVU78
+ 329 000c 0129     		cmp	r1, #1
+ 330 000e 01D0     		beq	.L27
+ 774:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 331              		.loc 1 774 10 view .LVU79
+ 332 0010 0020     		movs	r0, #0
+ 333              	.LVL27:
+ 334              	.L21:
+ 775:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 335              		.loc 1 775 1 view .LVU80
+ 336 0012 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 337              	.LVL28:
+ 338              	.L27:
+ 737:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 339              		.loc 1 737 5 is_stmt 1 view .LVU81
+ 737:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 340              		.loc 1 737 28 is_stmt 0 view .LVU82
+ 341 0014 FFF7FEFF 		bl	USBD_LL_GetRxDataSize
+ 342              	.LVL29:
+ 737:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ARM GAS  /tmp/ccdtFdaF.s 			page 22
+
+
+ 343              		.loc 1 737 16 view .LVU83
+ 344 0018 86B2     		uxth	r6, r0
+ 345              	.LVL30:
+ 740:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                            PacketSize, AUDIO_OUT_TC);
+ 346              		.loc 1 740 5 is_stmt 1 view .LVU84
+ 740:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                            PacketSize, AUDIO_OUT_TC);
+ 347              		.loc 1 740 35 is_stmt 0 view .LVU85
+ 348 001a D4F8C032 		ldr	r3, [r4, #704]
+ 740:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                            PacketSize, AUDIO_OUT_TC);
+ 349              		.loc 1 740 47 view .LVU86
+ 350 001e 5B69     		ldr	r3, [r3, #20]
+ 740:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                            PacketSize, AUDIO_OUT_TC);
+ 351              		.loc 1 740 82 view .LVU87
+ 352 0020 05F58057 		add	r7, r5, #4096
+ 353 0024 B7F8880B 		ldrh	r0, [r7, #2952]
+ 740:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                            PacketSize, AUDIO_OUT_TC);
+ 354              		.loc 1 740 6 view .LVU88
+ 355 0028 2844     		add	r0, r0, r5
+ 356 002a 0122     		movs	r2, #1
+ 357 002c 3146     		mov	r1, r6
+ 358 002e 0430     		adds	r0, r0, #4
+ 359 0030 9847     		blx	r3
+ 360              	.LVL31:
+ 744:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 361              		.loc 1 744 5 is_stmt 1 view .LVU89
+ 744:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 362              		.loc 1 744 11 is_stmt 0 view .LVU90
+ 363 0032 B7F8883B 		ldrh	r3, [r7, #2952]
+ 744:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 364              		.loc 1 744 20 view .LVU91
+ 365 0036 3344     		add	r3, r3, r6
+ 366 0038 9BB2     		uxth	r3, r3
+ 367 003a A7F8883B 		strh	r3, [r7, #2952]	@ movhi
+ 746:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 368              		.loc 1 746 5 is_stmt 1 view .LVU92
+ 746:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 369              		.loc 1 746 8 is_stmt 0 view .LVU93
+ 370 003e B3F5DC5F 		cmp	r3, #7040
+ 371 0042 18D0     		beq	.L28
+ 372              	.L22:
+ 760:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 373              		.loc 1 760 5 is_stmt 1 view .LVU94
+ 760:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 374              		.loc 1 760 15 is_stmt 0 view .LVU95
+ 375 0044 05F58053 		add	r3, r5, #4096
+ 376 0048 93F8853B 		ldrb	r3, [r3, #2949]	@ zero_extendqisi2
+ 760:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 377              		.loc 1 760 8 view .LVU96
+ 378 004c 33B9     		cbnz	r3, .L23
+ 762:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 379              		.loc 1 762 7 is_stmt 1 view .LVU97
+ 762:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 380              		.loc 1 762 17 is_stmt 0 view .LVU98
+ 381 004e 05F58053 		add	r3, r5, #4096
+ 382 0052 B3F8883B 		ldrh	r3, [r3, #2952]
+ 762:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 383              		.loc 1 762 10 view .LVU99
+ARM GAS  /tmp/ccdtFdaF.s 			page 23
+
+
+ 384 0056 B3F55C6F 		cmp	r3, #3520
+ 385 005a 1FD0     		beq	.L29
+ 386              	.L23:
+ 769:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                  &haudio->buffer[haudio->wr_ptr],
+ 387              		.loc 1 769 5 is_stmt 1 view .LVU100
+ 770:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                  AUDIO_OUT_PACKET);
+ 388              		.loc 1 770 56 is_stmt 0 view .LVU101
+ 389 005c 05F58053 		add	r3, r5, #4096
+ 390 0060 B3F8883B 		ldrh	r3, [r3, #2952]
+ 769:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                  &haudio->buffer[haudio->wr_ptr],
+ 391              		.loc 1 769 11 view .LVU102
+ 392 0064 EA18     		adds	r2, r5, r3
+ 393 0066 5823     		movs	r3, #88
+ 394 0068 0432     		adds	r2, r2, #4
+ 395 006a 0121     		movs	r1, #1
+ 396 006c 2046     		mov	r0, r4
+ 397 006e FFF7FEFF 		bl	USBD_LL_PrepareReceive
+ 398              	.LVL32:
+ 774:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 399              		.loc 1 774 10 view .LVU103
+ 400 0072 0020     		movs	r0, #0
+ 401 0074 CDE7     		b	.L21
+ 402              	.L28:
+ 749:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 403              		.loc 1 749 7 is_stmt 1 view .LVU104
+ 749:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 404              		.loc 1 749 22 is_stmt 0 view .LVU105
+ 405 0076 0022     		movs	r2, #0
+ 406 0078 A7F8882B 		strh	r2, [r7, #2952]	@ movhi
+ 751:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 407              		.loc 1 751 7 is_stmt 1 view .LVU106
+ 751:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 408              		.loc 1 751 17 is_stmt 0 view .LVU107
+ 409 007c 97F8843B 		ldrb	r3, [r7, #2948]	@ zero_extendqisi2
+ 751:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 410              		.loc 1 751 10 view .LVU108
+ 411 0080 032B     		cmp	r3, #3
+ 412 0082 DFD1     		bne	.L22
+ 753:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                              AUDIO_TOTAL_BUF_SIZE / 2U,
+ 413              		.loc 1 753 9 is_stmt 1 view .LVU109
+ 753:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                              AUDIO_TOTAL_BUF_SIZE / 2U,
+ 414              		.loc 1 753 39 is_stmt 0 view .LVU110
+ 415 0084 D4F8C032 		ldr	r3, [r4, #704]
+ 753:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                              AUDIO_TOTAL_BUF_SIZE / 2U,
+ 416              		.loc 1 753 51 view .LVU111
+ 417 0088 9B68     		ldr	r3, [r3, #8]
+ 753:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                              AUDIO_TOTAL_BUF_SIZE / 2U,
+ 418              		.loc 1 753 10 view .LVU112
+ 419 008a 0122     		movs	r2, #1
+ 420 008c 4FF45C61 		mov	r1, #3520
+ 421 0090 281D     		adds	r0, r5, #4
+ 422 0092 9847     		blx	r3
+ 423              	.LVL33:
+ 756:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 424              		.loc 1 756 9 is_stmt 1 view .LVU113
+ 756:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 425              		.loc 1 756 24 is_stmt 0 view .LVU114
+ARM GAS  /tmp/ccdtFdaF.s 			page 24
+
+
+ 426 0094 0022     		movs	r2, #0
+ 427 0096 87F8842B 		strb	r2, [r7, #2948]
+ 428 009a D3E7     		b	.L22
+ 429              	.L29:
+ 764:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 430              		.loc 1 764 9 is_stmt 1 view .LVU115
+ 764:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 431              		.loc 1 764 27 is_stmt 0 view .LVU116
+ 432 009c 05F58053 		add	r3, r5, #4096
+ 433 00a0 0122     		movs	r2, #1
+ 434 00a2 83F8852B 		strb	r2, [r3, #2949]
+ 435 00a6 D9E7     		b	.L23
+ 436              	.LVL34:
+ 437              	.L24:
+ 731:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 438              		.loc 1 731 12 view .LVU117
+ 439 00a8 0320     		movs	r0, #3
+ 440              	.LVL35:
+ 731:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 441              		.loc 1 731 12 view .LVU118
+ 442 00aa B2E7     		b	.L21
+ 443              		.cfi_endproc
+ 444              	.LFE344:
+ 446              		.section	.text.AUDIO_REQ_GetCurrent,"ax",%progbits
+ 447              		.align	1
+ 448              		.syntax unified
+ 449              		.thumb
+ 450              		.thumb_func
+ 452              	AUDIO_REQ_GetCurrent:
+ 453              	.LVL36:
+ 454              	.LFB345:
+ 785:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 455              		.loc 1 785 1 is_stmt 1 view -0
+ 456              		.cfi_startproc
+ 457              		@ args = 0, pretend = 0, frame = 0
+ 458              		@ frame_needed = 0, uses_anonymous_args = 0
+ 785:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 459              		.loc 1 785 1 is_stmt 0 view .LVU120
+ 460 0000 70B5     		push	{r4, r5, r6, lr}
+ 461              	.LCFI2:
+ 462              		.cfi_def_cfa_offset 16
+ 463              		.cfi_offset 4, -16
+ 464              		.cfi_offset 5, -12
+ 465              		.cfi_offset 6, -8
+ 466              		.cfi_offset 14, -4
+ 786:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+ 467              		.loc 1 786 3 is_stmt 1 view .LVU121
+ 787:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 468              		.loc 1 787 3 view .LVU122
+ 787:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 469              		.loc 1 787 10 is_stmt 0 view .LVU123
+ 470 0002 D0F8BC42 		ldr	r4, [r0, #700]
+ 471              	.LVL37:
+ 789:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 472              		.loc 1 789 3 is_stmt 1 view .LVU124
+ 789:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 473              		.loc 1 789 6 is_stmt 0 view .LVU125
+ARM GAS  /tmp/ccdtFdaF.s 			page 25
+
+
+ 474 0006 74B1     		cbz	r4, .L30
+ 475 0008 0546     		mov	r5, r0
+ 476 000a 0E46     		mov	r6, r1
+ 794:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 477              		.loc 1 794 3 is_stmt 1 view .LVU126
+ 794:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 478              		.loc 1 794 36 is_stmt 0 view .LVU127
+ 479 000c 04F5DC54 		add	r4, r4, #7040
+ 480              	.LVL38:
+ 794:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 481              		.loc 1 794 36 view .LVU128
+ 482 0010 0B34     		adds	r4, r4, #11
+ 794:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 483              		.loc 1 794 9 view .LVU129
+ 484 0012 4022     		movs	r2, #64
+ 485 0014 0021     		movs	r1, #0
+ 486              	.LVL39:
+ 794:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 487              		.loc 1 794 9 view .LVU130
+ 488 0016 2046     		mov	r0, r4
+ 489              	.LVL40:
+ 794:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 490              		.loc 1 794 9 view .LVU131
+ 491 0018 FFF7FEFF 		bl	memset
+ 492              	.LVL41:
+ 797:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 493              		.loc 1 797 3 is_stmt 1 view .LVU132
+ 797:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 494              		.loc 1 797 9 is_stmt 0 view .LVU133
+ 495 001c F288     		ldrh	r2, [r6, #6]
+ 496 001e 2146     		mov	r1, r4
+ 497 0020 2846     		mov	r0, r5
+ 498 0022 FFF7FEFF 		bl	USBD_CtlSendData
+ 499              	.LVL42:
+ 500              	.L30:
+ 798:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 501              		.loc 1 798 1 view .LVU134
+ 502 0026 70BD     		pop	{r4, r5, r6, pc}
+ 503              		.cfi_endproc
+ 504              	.LFE345:
+ 506              		.section	.text.AUDIO_REQ_SetCurrent,"ax",%progbits
+ 507              		.align	1
+ 508              		.syntax unified
+ 509              		.thumb
+ 510              		.thumb_func
+ 512              	AUDIO_REQ_SetCurrent:
+ 513              	.LVL43:
+ 514              	.LFB346:
+ 808:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 515              		.loc 1 808 1 is_stmt 1 view -0
+ 516              		.cfi_startproc
+ 517              		@ args = 0, pretend = 0, frame = 0
+ 518              		@ frame_needed = 0, uses_anonymous_args = 0
+ 808:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 519              		.loc 1 808 1 is_stmt 0 view .LVU136
+ 520 0000 38B5     		push	{r3, r4, r5, lr}
+ 521              	.LCFI3:
+ARM GAS  /tmp/ccdtFdaF.s 			page 26
+
+
+ 522              		.cfi_def_cfa_offset 16
+ 523              		.cfi_offset 3, -16
+ 524              		.cfi_offset 4, -12
+ 525              		.cfi_offset 5, -8
+ 526              		.cfi_offset 14, -4
+ 809:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData;
+ 527              		.loc 1 809 3 is_stmt 1 view .LVU137
+ 810:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 528              		.loc 1 810 3 view .LVU138
+ 810:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 529              		.loc 1 810 10 is_stmt 0 view .LVU139
+ 530 0002 D0F8BC52 		ldr	r5, [r0, #700]
+ 531              	.LVL44:
+ 812:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 532              		.loc 1 812 3 is_stmt 1 view .LVU140
+ 812:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 533              		.loc 1 812 6 is_stmt 0 view .LVU141
+ 534 0006 15B1     		cbz	r5, .L33
+ 535 0008 0C46     		mov	r4, r1
+ 817:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 536              		.loc 1 817 3 is_stmt 1 view .LVU142
+ 817:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 537              		.loc 1 817 10 is_stmt 0 view .LVU143
+ 538 000a CA88     		ldrh	r2, [r1, #6]
+ 817:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 539              		.loc 1 817 6 view .LVU144
+ 540 000c 02B9     		cbnz	r2, .L36
+ 541              	.LVL45:
+ 542              	.L33:
+ 826:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 543              		.loc 1 826 1 view .LVU145
+ 544 000e 38BD     		pop	{r3, r4, r5, pc}
+ 545              	.LVL46:
+ 546              	.L36:
+ 820:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 547              		.loc 1 820 5 is_stmt 1 view .LVU146
+ 820:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 548              		.loc 1 820 11 is_stmt 0 view .LVU147
+ 549 0010 05F5DC51 		add	r1, r5, #7040
+ 550              	.LVL47:
+ 820:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 551              		.loc 1 820 11 view .LVU148
+ 552 0014 0B31     		adds	r1, r1, #11
+ 553 0016 FFF7FEFF 		bl	USBD_CtlPrepareRx
+ 554              	.LVL48:
+ 822:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     haudio->control.len = (uint8_t)req->wLength; /* Set the request data length */
+ 555              		.loc 1 822 5 is_stmt 1 view .LVU149
+ 822:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     haudio->control.len = (uint8_t)req->wLength; /* Set the request data length */
+ 556              		.loc 1 822 25 is_stmt 0 view .LVU150
+ 557 001a 05F58055 		add	r5, r5, #4096
+ 558              	.LVL49:
+ 822:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     haudio->control.len = (uint8_t)req->wLength; /* Set the request data length */
+ 559              		.loc 1 822 25 view .LVU151
+ 560 001e 0123     		movs	r3, #1
+ 561 0020 85F88A3B 		strb	r3, [r5, #2954]
+ 823:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     haudio->control.unit = HIBYTE(req->wIndex);  /* Set the request target unit */
+ 562              		.loc 1 823 5 is_stmt 1 view .LVU152
+ARM GAS  /tmp/ccdtFdaF.s 			page 27
+
+
+ 823:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     haudio->control.unit = HIBYTE(req->wIndex);  /* Set the request target unit */
+ 563              		.loc 1 823 27 is_stmt 0 view .LVU153
+ 564 0024 A379     		ldrb	r3, [r4, #6]	@ zero_extendqisi2
+ 823:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     haudio->control.unit = HIBYTE(req->wIndex);  /* Set the request target unit */
+ 565              		.loc 1 823 25 view .LVU154
+ 566 0026 85F8CB3B 		strb	r3, [r5, #3019]
+ 824:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 567              		.loc 1 824 5 is_stmt 1 view .LVU155
+ 824:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 568              		.loc 1 824 28 is_stmt 0 view .LVU156
+ 569 002a A388     		ldrh	r3, [r4, #4]
+ 570 002c 1B0A     		lsrs	r3, r3, #8
+ 824:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 571              		.loc 1 824 26 view .LVU157
+ 572 002e 85F8CC3B 		strb	r3, [r5, #3020]
+ 573 0032 ECE7     		b	.L33
+ 574              		.cfi_endproc
+ 575              	.LFE346:
+ 577              		.section	.text.USBD_AUDIO_Setup,"ax",%progbits
+ 578              		.align	1
+ 579              		.syntax unified
+ 580              		.thumb
+ 581              		.thumb_func
+ 583              	USBD_AUDIO_Setup:
+ 584              	.LVL50:
+ 585              	.LFB335:
+ 422:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 586              		.loc 1 422 1 is_stmt 1 view -0
+ 587              		.cfi_startproc
+ 588              		@ args = 0, pretend = 0, frame = 8
+ 589              		@ frame_needed = 0, uses_anonymous_args = 0
+ 422:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 590              		.loc 1 422 1 is_stmt 0 view .LVU159
+ 591 0000 30B5     		push	{r4, r5, lr}
+ 592              	.LCFI4:
+ 593              		.cfi_def_cfa_offset 12
+ 594              		.cfi_offset 4, -12
+ 595              		.cfi_offset 5, -8
+ 596              		.cfi_offset 14, -4
+ 597 0002 83B0     		sub	sp, sp, #12
+ 598              	.LCFI5:
+ 599              		.cfi_def_cfa_offset 24
+ 423:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   uint16_t len;
+ 600              		.loc 1 423 3 is_stmt 1 view .LVU160
+ 424:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   uint8_t *pbuf;
+ 601              		.loc 1 424 3 view .LVU161
+ 425:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   uint16_t status_info = 0U;
+ 602              		.loc 1 425 3 view .LVU162
+ 426:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 603              		.loc 1 426 3 view .LVU163
+ 426:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 604              		.loc 1 426 12 is_stmt 0 view .LVU164
+ 605 0004 0023     		movs	r3, #0
+ 606 0006 ADF80630 		strh	r3, [sp, #6]	@ movhi
+ 427:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 607              		.loc 1 427 3 is_stmt 1 view .LVU165
+ 608              	.LVL51:
+ARM GAS  /tmp/ccdtFdaF.s 			page 28
+
+
+ 429:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 609              		.loc 1 429 3 view .LVU166
+ 429:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 610              		.loc 1 429 10 is_stmt 0 view .LVU167
+ 611 000a D0F8BC32 		ldr	r3, [r0, #700]
+ 612              	.LVL52:
+ 431:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 613              		.loc 1 431 3 is_stmt 1 view .LVU168
+ 431:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 614              		.loc 1 431 6 is_stmt 0 view .LVU169
+ 615 000e 002B     		cmp	r3, #0
+ 616 0010 67D0     		beq	.L53
+ 436:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 617              		.loc 1 436 3 is_stmt 1 view .LVU170
+ 436:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 618              		.loc 1 436 14 is_stmt 0 view .LVU171
+ 619 0012 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 436:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 620              		.loc 1 436 3 view .LVU172
+ 621 0014 14F06004 		ands	r4, r4, #96
+ 622 0018 12D0     		beq	.L39
+ 623 001a 202C     		cmp	r4, #32
+ 624 001c 5BD1     		bne	.L40
+ 439:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 625              		.loc 1 439 7 is_stmt 1 view .LVU173
+ 439:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 626              		.loc 1 439 18 is_stmt 0 view .LVU174
+ 627 001e 4B78     		ldrb	r3, [r1, #1]	@ zero_extendqisi2
+ 628              	.LVL53:
+ 439:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 629              		.loc 1 439 18 view .LVU175
+ 630 0020 012B     		cmp	r3, #1
+ 631 0022 05D0     		beq	.L41
+ 632 0024 812B     		cmp	r3, #129
+ 633 0026 07D1     		bne	.L42
+ 442:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 634              		.loc 1 442 11 is_stmt 1 view .LVU176
+ 635 0028 FFF7FEFF 		bl	AUDIO_REQ_GetCurrent
+ 636              	.LVL54:
+ 443:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 637              		.loc 1 443 11 view .LVU177
+ 427:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 638              		.loc 1 427 22 is_stmt 0 view .LVU178
+ 639 002c 0024     		movs	r4, #0
+ 443:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 640              		.loc 1 443 11 view .LVU179
+ 641 002e 55E0     		b	.L38
+ 642              	.LVL55:
+ 643              	.L41:
+ 446:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 644              		.loc 1 446 11 is_stmt 1 view .LVU180
+ 645 0030 FFF7FEFF 		bl	AUDIO_REQ_SetCurrent
+ 646              	.LVL56:
+ 447:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 647              		.loc 1 447 11 view .LVU181
+ 427:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 648              		.loc 1 427 22 is_stmt 0 view .LVU182
+ARM GAS  /tmp/ccdtFdaF.s 			page 29
+
+
+ 649 0034 0024     		movs	r4, #0
+ 447:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 650              		.loc 1 447 11 view .LVU183
+ 651 0036 51E0     		b	.L38
+ 652              	.LVL57:
+ 653              	.L42:
+ 450:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           ret = USBD_FAIL;
+ 654              		.loc 1 450 11 is_stmt 1 view .LVU184
+ 655 0038 FFF7FEFF 		bl	USBD_CtlError
+ 656              	.LVL58:
+ 451:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 657              		.loc 1 451 11 view .LVU185
+ 452:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 658              		.loc 1 452 11 view .LVU186
+ 451:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 659              		.loc 1 451 15 is_stmt 0 view .LVU187
+ 660 003c 0324     		movs	r4, #3
+ 452:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 661              		.loc 1 452 11 view .LVU188
+ 662 003e 4DE0     		b	.L38
+ 663              	.LVL59:
+ 664              	.L39:
+ 457:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 665              		.loc 1 457 7 is_stmt 1 view .LVU189
+ 457:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 666              		.loc 1 457 18 is_stmt 0 view .LVU190
+ 667 0040 4D78     		ldrb	r5, [r1, #1]	@ zero_extendqisi2
+ 668 0042 0B2D     		cmp	r5, #11
+ 669 0044 43D8     		bhi	.L43
+ 670 0046 DFE805F0 		tbb	[pc, r5]
+ 671              	.L45:
+ 672 004a 06       		.byte	(.L48-.L45)/2
+ 673 004b 49       		.byte	(.L38-.L45)/2
+ 674 004c 42       		.byte	(.L43-.L45)/2
+ 675 004d 42       		.byte	(.L43-.L45)/2
+ 676 004e 42       		.byte	(.L43-.L45)/2
+ 677 004f 42       		.byte	(.L43-.L45)/2
+ 678 0050 16       		.byte	(.L47-.L45)/2
+ 679 0051 42       		.byte	(.L43-.L45)/2
+ 680 0052 42       		.byte	(.L43-.L45)/2
+ 681 0053 42       		.byte	(.L43-.L45)/2
+ 682 0054 22       		.byte	(.L46-.L45)/2
+ 683 0055 30       		.byte	(.L44-.L45)/2
+ 684              		.p2align 1
+ 685              	.L48:
+ 460:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 686              		.loc 1 460 11 is_stmt 1 view .LVU191
+ 460:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 687              		.loc 1 460 19 is_stmt 0 view .LVU192
+ 688 0056 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 689              	.LVL60:
+ 460:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 690              		.loc 1 460 19 view .LVU193
+ 691 005a DBB2     		uxtb	r3, r3
+ 460:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 692              		.loc 1 460 14 view .LVU194
+ 693 005c 032B     		cmp	r3, #3
+ARM GAS  /tmp/ccdtFdaF.s 			page 30
+
+
+ 694 005e 03D0     		beq	.L56
+ 466:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             ret = USBD_FAIL;
+ 695              		.loc 1 466 13 is_stmt 1 view .LVU195
+ 696 0060 FFF7FEFF 		bl	USBD_CtlError
+ 697              	.LVL61:
+ 467:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 698              		.loc 1 467 13 view .LVU196
+ 467:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 699              		.loc 1 467 17 is_stmt 0 view .LVU197
+ 700 0064 0324     		movs	r4, #3
+ 701 0066 39E0     		b	.L38
+ 702              	.LVL62:
+ 703              	.L56:
+ 462:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 704              		.loc 1 462 13 is_stmt 1 view .LVU198
+ 462:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 705              		.loc 1 462 19 is_stmt 0 view .LVU199
+ 706 0068 0222     		movs	r2, #2
+ 707 006a 0DF10601 		add	r1, sp, #6
+ 708              	.LVL63:
+ 462:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 709              		.loc 1 462 19 view .LVU200
+ 710 006e FFF7FEFF 		bl	USBD_CtlSendData
+ 711              	.LVL64:
+ 427:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 712              		.loc 1 427 22 view .LVU201
+ 713 0072 2C46     		mov	r4, r5
+ 714 0074 32E0     		b	.L38
+ 715              	.LVL65:
+ 716              	.L47:
+ 472:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 717              		.loc 1 472 11 is_stmt 1 view .LVU202
+ 472:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 718              		.loc 1 472 19 is_stmt 0 view .LVU203
+ 719 0076 4B88     		ldrh	r3, [r1, #2]
+ 720              	.LVL66:
+ 472:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 721              		.loc 1 472 34 view .LVU204
+ 722 0078 1B0A     		lsrs	r3, r3, #8
+ 472:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 723              		.loc 1 472 14 view .LVU205
+ 724 007a 212B     		cmp	r3, #33
+ 725 007c 2ED1     		bne	.L38
+ 474:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             len = MIN(USB_AUDIO_DESC_SIZ, req->wLength);
+ 726              		.loc 1 474 13 is_stmt 1 view .LVU206
+ 727              	.LVL67:
+ 475:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 728              		.loc 1 475 13 view .LVU207
+ 475:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 729              		.loc 1 475 19 is_stmt 0 view .LVU208
+ 730 007e CA88     		ldrh	r2, [r1, #6]
+ 731              	.LVL68:
+ 477:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 732              		.loc 1 477 13 is_stmt 1 view .LVU209
+ 477:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 733              		.loc 1 477 19 is_stmt 0 view .LVU210
+ 734 0080 092A     		cmp	r2, #9
+ARM GAS  /tmp/ccdtFdaF.s 			page 31
+
+
+ 735 0082 28BF     		it	cs
+ 736 0084 0922     		movcs	r2, #9
+ 737              	.LVL69:
+ 477:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 738              		.loc 1 477 19 view .LVU211
+ 739 0086 1849     		ldr	r1, .L58
+ 740              	.LVL70:
+ 477:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 741              		.loc 1 477 19 view .LVU212
+ 742 0088 FFF7FEFF 		bl	USBD_CtlSendData
+ 743              	.LVL71:
+ 477:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 744              		.loc 1 477 19 view .LVU213
+ 745 008c 26E0     		b	.L38
+ 746              	.LVL72:
+ 747              	.L46:
+ 482:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 748              		.loc 1 482 11 is_stmt 1 view .LVU214
+ 482:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 749              		.loc 1 482 19 is_stmt 0 view .LVU215
+ 750 008e 90F89C22 		ldrb	r2, [r0, #668]	@ zero_extendqisi2
+ 751 0092 D2B2     		uxtb	r2, r2
+ 482:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 752              		.loc 1 482 14 view .LVU216
+ 753 0094 032A     		cmp	r2, #3
+ 754 0096 03D0     		beq	.L57
+ 488:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             ret = USBD_FAIL;
+ 755              		.loc 1 488 13 is_stmt 1 view .LVU217
+ 756 0098 FFF7FEFF 		bl	USBD_CtlError
+ 757              	.LVL73:
+ 489:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 758              		.loc 1 489 13 view .LVU218
+ 489:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 759              		.loc 1 489 17 is_stmt 0 view .LVU219
+ 760 009c 0324     		movs	r4, #3
+ 761 009e 1DE0     		b	.L38
+ 762              	.LVL74:
+ 763              	.L57:
+ 484:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 764              		.loc 1 484 13 is_stmt 1 view .LVU220
+ 484:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 765              		.loc 1 484 19 is_stmt 0 view .LVU221
+ 766 00a0 0122     		movs	r2, #1
+ 767 00a2 1946     		mov	r1, r3
+ 768              	.LVL75:
+ 484:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 769              		.loc 1 484 19 view .LVU222
+ 770 00a4 FFF7FEFF 		bl	USBD_CtlSendData
+ 771              	.LVL76:
+ 484:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 772              		.loc 1 484 19 view .LVU223
+ 773 00a8 18E0     		b	.L38
+ 774              	.LVL77:
+ 775              	.L44:
+ 494:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 776              		.loc 1 494 11 is_stmt 1 view .LVU224
+ 494:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ARM GAS  /tmp/ccdtFdaF.s 			page 32
+
+
+ 777              		.loc 1 494 19 is_stmt 0 view .LVU225
+ 778 00aa 90F89C52 		ldrb	r5, [r0, #668]	@ zero_extendqisi2
+ 779 00ae EDB2     		uxtb	r5, r5
+ 494:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           {
+ 780              		.loc 1 494 14 view .LVU226
+ 781 00b0 032D     		cmp	r5, #3
+ 782 00b2 08D1     		bne	.L51
+ 496:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             {
+ 783              		.loc 1 496 13 is_stmt 1 view .LVU227
+ 496:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             {
+ 784              		.loc 1 496 17 is_stmt 0 view .LVU228
+ 785 00b4 8A78     		ldrb	r2, [r1, #2]	@ zero_extendqisi2
+ 496:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             {
+ 786              		.loc 1 496 16 view .LVU229
+ 787 00b6 012A     		cmp	r2, #1
+ 788 00b8 01D8     		bhi	.L52
+ 498:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             }
+ 789              		.loc 1 498 15 is_stmt 1 view .LVU230
+ 498:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             }
+ 790              		.loc 1 498 35 is_stmt 0 view .LVU231
+ 791 00ba 1A60     		str	r2, [r3]
+ 792 00bc 0EE0     		b	.L38
+ 793              	.L52:
+ 503:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****               ret = USBD_FAIL;
+ 794              		.loc 1 503 15 is_stmt 1 view .LVU232
+ 795 00be FFF7FEFF 		bl	USBD_CtlError
+ 796              	.LVL78:
+ 504:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             }
+ 797              		.loc 1 504 15 view .LVU233
+ 504:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             }
+ 798              		.loc 1 504 19 is_stmt 0 view .LVU234
+ 799 00c2 2C46     		mov	r4, r5
+ 800 00c4 0AE0     		b	.L38
+ 801              	.LVL79:
+ 802              	.L51:
+ 509:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****             ret = USBD_FAIL;
+ 803              		.loc 1 509 13 is_stmt 1 view .LVU235
+ 804 00c6 FFF7FEFF 		bl	USBD_CtlError
+ 805              	.LVL80:
+ 510:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 806              		.loc 1 510 13 view .LVU236
+ 510:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           }
+ 807              		.loc 1 510 17 is_stmt 0 view .LVU237
+ 808 00ca 0324     		movs	r4, #3
+ 809 00cc 06E0     		b	.L38
+ 810              	.LVL81:
+ 811              	.L43:
+ 518:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           ret = USBD_FAIL;
+ 812              		.loc 1 518 11 is_stmt 1 view .LVU238
+ 813 00ce FFF7FEFF 		bl	USBD_CtlError
+ 814              	.LVL82:
+ 519:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 815              		.loc 1 519 11 view .LVU239
+ 520:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 816              		.loc 1 520 11 view .LVU240
+ 519:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****           break;
+ 817              		.loc 1 519 15 is_stmt 0 view .LVU241
+ARM GAS  /tmp/ccdtFdaF.s 			page 33
+
+
+ 818 00d2 0324     		movs	r4, #3
+ 520:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 819              		.loc 1 520 11 view .LVU242
+ 820 00d4 02E0     		b	.L38
+ 821              	.LVL83:
+ 822              	.L40:
+ 524:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       ret = USBD_FAIL;
+ 823              		.loc 1 524 7 is_stmt 1 view .LVU243
+ 824 00d6 FFF7FEFF 		bl	USBD_CtlError
+ 825              	.LVL84:
+ 525:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       break;
+ 826              		.loc 1 525 7 view .LVU244
+ 526:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 827              		.loc 1 526 7 view .LVU245
+ 525:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       break;
+ 828              		.loc 1 525 11 is_stmt 0 view .LVU246
+ 829 00da 0324     		movs	r4, #3
+ 830              	.LVL85:
+ 831              	.L38:
+ 530:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 832              		.loc 1 530 1 view .LVU247
+ 833 00dc 2046     		mov	r0, r4
+ 834 00de 03B0     		add	sp, sp, #12
+ 835              	.LCFI6:
+ 836              		.cfi_remember_state
+ 837              		.cfi_def_cfa_offset 12
+ 838              		@ sp needed
+ 839 00e0 30BD     		pop	{r4, r5, pc}
+ 840              	.LVL86:
+ 841              	.L53:
+ 842              	.LCFI7:
+ 843              		.cfi_restore_state
+ 433:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 844              		.loc 1 433 12 view .LVU248
+ 845 00e2 0324     		movs	r4, #3
+ 846 00e4 FAE7     		b	.L38
+ 847              	.L59:
+ 848 00e6 00BF     		.align	2
+ 849              	.L58:
+ 850 00e8 12000000 		.word	USBD_AUDIO_CfgDesc+18
+ 851              		.cfi_endproc
+ 852              	.LFE335:
+ 854              		.section	.text.USBD_AUDIO_DeInit,"ax",%progbits
+ 855              		.align	1
+ 856              		.syntax unified
+ 857              		.thumb
+ 858              		.thumb_func
+ 860              	USBD_AUDIO_DeInit:
+ 861              	.LVL87:
+ 862              	.LFB334:
+ 394:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(cfgidx);
+ 863              		.loc 1 394 1 is_stmt 1 view -0
+ 864              		.cfi_startproc
+ 865              		@ args = 0, pretend = 0, frame = 0
+ 866              		@ frame_needed = 0, uses_anonymous_args = 0
+ 394:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(cfgidx);
+ 867              		.loc 1 394 1 is_stmt 0 view .LVU250
+ARM GAS  /tmp/ccdtFdaF.s 			page 34
+
+
+ 868 0000 10B5     		push	{r4, lr}
+ 869              	.LCFI8:
+ 870              		.cfi_def_cfa_offset 8
+ 871              		.cfi_offset 4, -8
+ 872              		.cfi_offset 14, -4
+ 873 0002 0446     		mov	r4, r0
+ 395:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 874              		.loc 1 395 3 is_stmt 1 view .LVU251
+ 398:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 0U;
+ 875              		.loc 1 398 3 view .LVU252
+ 398:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 0U;
+ 876              		.loc 1 398 9 is_stmt 0 view .LVU253
+ 877 0004 0121     		movs	r1, #1
+ 878              	.LVL88:
+ 398:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 0U;
+ 879              		.loc 1 398 9 view .LVU254
+ 880 0006 FFF7FEFF 		bl	USBD_LL_CloseEP
+ 881              	.LVL89:
+ 399:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->ep_out[AUDIO_OUT_EP & 0xFU].bInterval = 0U;
+ 882              		.loc 1 399 3 is_stmt 1 view .LVU255
+ 399:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->ep_out[AUDIO_OUT_EP & 0xFU].bInterval = 0U;
+ 883              		.loc 1 399 45 is_stmt 0 view .LVU256
+ 884 000a 0023     		movs	r3, #0
+ 885 000c A4F87831 		strh	r3, [r4, #376]	@ movhi
+ 400:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 886              		.loc 1 400 3 is_stmt 1 view .LVU257
+ 400:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 887              		.loc 1 400 47 is_stmt 0 view .LVU258
+ 888 0010 A4F87A31 		strh	r3, [r4, #378]	@ movhi
+ 403:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 889              		.loc 1 403 3 is_stmt 1 view .LVU259
+ 403:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 890              		.loc 1 403 11 is_stmt 0 view .LVU260
+ 891 0014 D4F8BC32 		ldr	r3, [r4, #700]
+ 403:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 892              		.loc 1 403 6 view .LVU261
+ 893 0018 5BB1     		cbz	r3, .L61
+ 405:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     (void)USBD_free(pdev->pClassData);
+ 894              		.loc 1 405 5 is_stmt 1 view .LVU262
+ 405:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     (void)USBD_free(pdev->pClassData);
+ 895              		.loc 1 405 35 is_stmt 0 view .LVU263
+ 896 001a D4F8C032 		ldr	r3, [r4, #704]
+ 405:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     (void)USBD_free(pdev->pClassData);
+ 897              		.loc 1 405 47 view .LVU264
+ 898 001e 5B68     		ldr	r3, [r3, #4]
+ 405:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     (void)USBD_free(pdev->pClassData);
+ 899              		.loc 1 405 6 view .LVU265
+ 900 0020 0020     		movs	r0, #0
+ 901 0022 9847     		blx	r3
+ 902              	.LVL90:
+ 406:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     pdev->pClassData = NULL;
+ 903              		.loc 1 406 5 is_stmt 1 view .LVU266
+ 904 0024 D4F8BC02 		ldr	r0, [r4, #700]
+ 905 0028 FFF7FEFF 		bl	USBD_static_free
+ 906              	.LVL91:
+ 407:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 907              		.loc 1 407 5 view .LVU267
+ARM GAS  /tmp/ccdtFdaF.s 			page 35
+
+
+ 407:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 908              		.loc 1 407 22 is_stmt 0 view .LVU268
+ 909 002c 0023     		movs	r3, #0
+ 910 002e C4F8BC32 		str	r3, [r4, #700]
+ 911              	.L61:
+ 410:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 912              		.loc 1 410 3 is_stmt 1 view .LVU269
+ 411:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 913              		.loc 1 411 1 is_stmt 0 view .LVU270
+ 914 0032 0020     		movs	r0, #0
+ 915 0034 10BD     		pop	{r4, pc}
+ 411:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 916              		.loc 1 411 1 view .LVU271
+ 917              		.cfi_endproc
+ 918              	.LFE334:
+ 920              		.section	.text.USBD_AUDIO_Init,"ax",%progbits
+ 921              		.align	1
+ 922              		.syntax unified
+ 923              		.thumb
+ 924              		.thumb_func
+ 926              	USBD_AUDIO_Init:
+ 927              	.LVL92:
+ 928              	.LFB333:
+ 337:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(cfgidx);
+ 929              		.loc 1 337 1 is_stmt 1 view -0
+ 930              		.cfi_startproc
+ 931              		@ args = 0, pretend = 0, frame = 0
+ 932              		@ frame_needed = 0, uses_anonymous_args = 0
+ 337:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   UNUSED(cfgidx);
+ 933              		.loc 1 337 1 is_stmt 0 view .LVU273
+ 934 0000 38B5     		push	{r3, r4, r5, lr}
+ 935              	.LCFI9:
+ 936              		.cfi_def_cfa_offset 16
+ 937              		.cfi_offset 3, -16
+ 938              		.cfi_offset 4, -12
+ 939              		.cfi_offset 5, -8
+ 940              		.cfi_offset 14, -4
+ 941 0002 0446     		mov	r4, r0
+ 338:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 942              		.loc 1 338 3 is_stmt 1 view .LVU274
+ 339:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 943              		.loc 1 339 3 view .LVU275
+ 342:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 944              		.loc 1 342 3 view .LVU276
+ 342:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 945              		.loc 1 342 12 is_stmt 0 view .LVU277
+ 946 0004 41F6D030 		movw	r0, #7120
+ 947              	.LVL93:
+ 342:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 948              		.loc 1 342 12 view .LVU278
+ 949 0008 FFF7FEFF 		bl	USBD_static_malloc
+ 950              	.LVL94:
+ 344:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 951              		.loc 1 344 3 is_stmt 1 view .LVU279
+ 344:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 952              		.loc 1 344 6 is_stmt 0 view .LVU280
+ 953 000c 68B3     		cbz	r0, .L70
+ARM GAS  /tmp/ccdtFdaF.s 			page 36
+
+
+ 954 000e 0546     		mov	r5, r0
+ 350:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 955              		.loc 1 350 3 is_stmt 1 view .LVU281
+ 350:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 956              		.loc 1 350 20 is_stmt 0 view .LVU282
+ 957 0010 C4F8BC02 		str	r0, [r4, #700]
+ 352:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 958              		.loc 1 352 3 is_stmt 1 view .LVU283
+ 352:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 959              		.loc 1 352 11 is_stmt 0 view .LVU284
+ 960 0014 237C     		ldrb	r3, [r4, #16]	@ zero_extendqisi2
+ 352:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 961              		.loc 1 352 6 view .LVU285
+ 962 0016 6BBB     		cbnz	r3, .L66
+ 354:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 963              		.loc 1 354 5 is_stmt 1 view .LVU286
+ 354:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 964              		.loc 1 354 49 is_stmt 0 view .LVU287
+ 965 0018 0123     		movs	r3, #1
+ 966 001a A4F87A31 		strh	r3, [r4, #378]	@ movhi
+ 967              	.L67:
+ 362:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 1U;
+ 968              		.loc 1 362 3 is_stmt 1 view .LVU288
+ 362:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 1U;
+ 969              		.loc 1 362 9 is_stmt 0 view .LVU289
+ 970 001e 5823     		movs	r3, #88
+ 971 0020 0122     		movs	r2, #1
+ 972 0022 1146     		mov	r1, r2
+ 973 0024 2046     		mov	r0, r4
+ 974              	.LVL95:
+ 362:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 1U;
+ 975              		.loc 1 362 9 view .LVU290
+ 976 0026 FFF7FEFF 		bl	USBD_LL_OpenEP
+ 977              	.LVL96:
+ 363:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 978              		.loc 1 363 3 is_stmt 1 view .LVU291
+ 363:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 979              		.loc 1 363 45 is_stmt 0 view .LVU292
+ 980 002a 0123     		movs	r3, #1
+ 981 002c A4F87831 		strh	r3, [r4, #376]	@ movhi
+ 365:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->offset = AUDIO_OFFSET_UNKNOWN;
+ 982              		.loc 1 365 3 is_stmt 1 view .LVU293
+ 365:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->offset = AUDIO_OFFSET_UNKNOWN;
+ 983              		.loc 1 365 23 is_stmt 0 view .LVU294
+ 984 0030 0022     		movs	r2, #0
+ 985 0032 2A60     		str	r2, [r5]
+ 366:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->wr_ptr = 0U;
+ 986              		.loc 1 366 3 is_stmt 1 view .LVU295
+ 366:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->wr_ptr = 0U;
+ 987              		.loc 1 366 18 is_stmt 0 view .LVU296
+ 988 0034 05F58053 		add	r3, r5, #4096
+ 989 0038 0321     		movs	r1, #3
+ 990 003a 83F8841B 		strb	r1, [r3, #2948]
+ 367:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->rd_ptr = 0U;
+ 991              		.loc 1 367 3 is_stmt 1 view .LVU297
+ 367:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->rd_ptr = 0U;
+ 992              		.loc 1 367 18 is_stmt 0 view .LVU298
+ARM GAS  /tmp/ccdtFdaF.s 			page 37
+
+
+ 993 003e A3F8882B 		strh	r2, [r3, #2952]	@ movhi
+ 368:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->rd_enable = 0U;
+ 994              		.loc 1 368 3 is_stmt 1 view .LVU299
+ 368:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   haudio->rd_enable = 0U;
+ 995              		.loc 1 368 18 is_stmt 0 view .LVU300
+ 996 0042 A3F8862B 		strh	r2, [r3, #2950]	@ movhi
+ 369:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 997              		.loc 1 369 3 is_stmt 1 view .LVU301
+ 369:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 998              		.loc 1 369 21 is_stmt 0 view .LVU302
+ 999 0046 83F8852B 		strb	r2, [r3, #2949]
+ 372:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                        AUDIO_DEFAULT_VOLUME,
+ 1000              		.loc 1 372 3 is_stmt 1 view .LVU303
+ 372:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                        AUDIO_DEFAULT_VOLUME,
+ 1001              		.loc 1 372 37 is_stmt 0 view .LVU304
+ 1002 004a D4F8C032 		ldr	r3, [r4, #704]
+ 372:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                        AUDIO_DEFAULT_VOLUME,
+ 1003              		.loc 1 372 49 view .LVU305
+ 1004 004e 1B68     		ldr	r3, [r3]
+ 372:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                        AUDIO_DEFAULT_VOLUME,
+ 1005              		.loc 1 372 8 view .LVU306
+ 1006 0050 4621     		movs	r1, #70
+ 1007 0052 45F25460 		movw	r0, #22100
+ 1008 0056 9847     		blx	r3
+ 1009              	.LVL97:
+ 372:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                        AUDIO_DEFAULT_VOLUME,
+ 1010              		.loc 1 372 6 view .LVU307
+ 1011 0058 80B9     		cbnz	r0, .L68
+ 380:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                AUDIO_OUT_PACKET);
+ 1012              		.loc 1 380 3 is_stmt 1 view .LVU308
+ 380:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                AUDIO_OUT_PACKET);
+ 1013              		.loc 1 380 9 is_stmt 0 view .LVU309
+ 1014 005a 5823     		movs	r3, #88
+ 1015 005c 2A1D     		adds	r2, r5, #4
+ 1016 005e 0121     		movs	r1, #1
+ 1017 0060 2046     		mov	r0, r4
+ 1018 0062 FFF7FEFF 		bl	USBD_LL_PrepareReceive
+ 1019              	.LVL98:
+ 383:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 1020              		.loc 1 383 3 is_stmt 1 view .LVU310
+ 383:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 1021              		.loc 1 383 10 is_stmt 0 view .LVU311
+ 1022 0066 0020     		movs	r0, #0
+ 1023              	.LVL99:
+ 1024              	.L65:
+ 384:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 1025              		.loc 1 384 1 view .LVU312
+ 1026 0068 38BD     		pop	{r3, r4, r5, pc}
+ 1027              	.LVL100:
+ 1028              	.L70:
+ 346:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     return (uint8_t)USBD_EMEM;
+ 1029              		.loc 1 346 5 is_stmt 1 view .LVU313
+ 346:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     return (uint8_t)USBD_EMEM;
+ 1030              		.loc 1 346 22 is_stmt 0 view .LVU314
+ 1031 006a 0023     		movs	r3, #0
+ 1032 006c C4F8BC32 		str	r3, [r4, #700]
+ 347:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ARM GAS  /tmp/ccdtFdaF.s 			page 38
+
+
+ 1033              		.loc 1 347 5 is_stmt 1 view .LVU315
+ 347:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 1034              		.loc 1 347 12 is_stmt 0 view .LVU316
+ 1035 0070 0220     		movs	r0, #2
+ 1036              	.LVL101:
+ 347:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 1037              		.loc 1 347 12 view .LVU317
+ 1038 0072 F9E7     		b	.L65
+ 1039              	.LVL102:
+ 1040              	.L66:
+ 358:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 1041              		.loc 1 358 5 is_stmt 1 view .LVU318
+ 358:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 1042              		.loc 1 358 49 is_stmt 0 view .LVU319
+ 1043 0074 0123     		movs	r3, #1
+ 1044 0076 A4F87A31 		strh	r3, [r4, #378]	@ movhi
+ 1045 007a D0E7     		b	.L67
+ 1046              	.LVL103:
+ 1047              	.L68:
+ 376:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 1048              		.loc 1 376 12 view .LVU320
+ 1049 007c 0320     		movs	r0, #3
+ 1050 007e F3E7     		b	.L65
+ 1051              		.cfi_endproc
+ 1052              	.LFE333:
+ 1054              		.section	.text.USBD_AUDIO_Sync,"ax",%progbits
+ 1055              		.align	1
+ 1056              		.global	USBD_AUDIO_Sync
+ 1057              		.syntax unified
+ 1058              		.thumb
+ 1059              		.thumb_func
+ 1061              	USBD_AUDIO_Sync:
+ 1062              	.LVL104:
+ 1063              	.LFB341:
+ 626:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 1064              		.loc 1 626 1 is_stmt 1 view -0
+ 1065              		.cfi_startproc
+ 1066              		@ args = 0, pretend = 0, frame = 0
+ 1067              		@ frame_needed = 0, uses_anonymous_args = 0
+ 626:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   USBD_AUDIO_HandleTypeDef *haudio;
+ 1068              		.loc 1 626 1 is_stmt 0 view .LVU322
+ 1069 0000 10B5     		push	{r4, lr}
+ 1070              	.LCFI10:
+ 1071              		.cfi_def_cfa_offset 8
+ 1072              		.cfi_offset 4, -8
+ 1073              		.cfi_offset 14, -4
+ 627:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   uint32_t BufferSize = AUDIO_TOTAL_BUF_SIZE / 2U;
+ 1074              		.loc 1 627 3 is_stmt 1 view .LVU323
+ 628:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 1075              		.loc 1 628 3 view .LVU324
+ 1076              	.LVL105:
+ 630:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 1077              		.loc 1 630 3 view .LVU325
+ 630:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 1078              		.loc 1 630 11 is_stmt 0 view .LVU326
+ 1079 0002 D0F8BC42 		ldr	r4, [r0, #700]
+ 630:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ARM GAS  /tmp/ccdtFdaF.s 			page 39
+
+
+ 1080              		.loc 1 630 6 view .LVU327
+ 1081 0006 CCB3     		cbz	r4, .L71
+ 1082 0008 0B46     		mov	r3, r1
+ 635:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 1083              		.loc 1 635 3 is_stmt 1 view .LVU328
+ 1084              	.LVL106:
+ 637:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 1085              		.loc 1 637 3 view .LVU329
+ 637:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 1086              		.loc 1 637 18 is_stmt 0 view .LVU330
+ 1087 000a 04F58052 		add	r2, r4, #4096
+ 1088 000e 82F8841B 		strb	r1, [r2, #2948]
+ 639:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 1089              		.loc 1 639 3 is_stmt 1 view .LVU331
+ 639:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 1090              		.loc 1 639 13 is_stmt 0 view .LVU332
+ 1091 0012 92F8852B 		ldrb	r2, [r2, #2949]	@ zero_extendqisi2
+ 639:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 1092              		.loc 1 639 6 view .LVU333
+ 1093 0016 012A     		cmp	r2, #1
+ 1094 0018 11D0     		beq	.L81
+ 1095              	.LVL107:
+ 1096              	.L73:
+ 650:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 1097              		.loc 1 650 3 is_stmt 1 view .LVU334
+ 650:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 1098              		.loc 1 650 13 is_stmt 0 view .LVU335
+ 1099 001a 04F58052 		add	r2, r4, #4096
+ 1100 001e B2F8861B 		ldrh	r1, [r2, #2950]
+ 650:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 1101              		.loc 1 650 30 view .LVU336
+ 1102 0022 B2F8882B 		ldrh	r2, [r2, #2952]
+ 650:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 1103              		.loc 1 650 6 view .LVU337
+ 1104 0026 9142     		cmp	r1, r2
+ 1105 0028 1AD9     		bls	.L74
+ 652:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 1106              		.loc 1 652 5 is_stmt 1 view .LVU338
+ 652:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 1107              		.loc 1 652 25 is_stmt 0 view .LVU339
+ 1108 002a 891A     		subs	r1, r1, r2
+ 652:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 1109              		.loc 1 652 8 view .LVU340
+ 1110 002c 5729     		cmp	r1, #87
+ 1111 002e 21DD     		ble	.L76
+ 658:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 1112              		.loc 1 658 7 is_stmt 1 view .LVU341
+ 658:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 1113              		.loc 1 658 10 is_stmt 0 view .LVU342
+ 1114 0030 41F62832 		movw	r2, #6952
+ 1115 0034 9142     		cmp	r1, r2
+ 1116 0036 22DC     		bgt	.L77
+ 628:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 1117              		.loc 1 628 12 view .LVU343
+ 1118 0038 4FF45C61 		mov	r1, #3520
+ 1119 003c 1CE0     		b	.L75
+ 1120              	.LVL108:
+ARM GAS  /tmp/ccdtFdaF.s 			page 40
+
+
+ 1121              	.L81:
+ 641:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 1122              		.loc 1 641 5 is_stmt 1 view .LVU344
+ 641:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 1123              		.loc 1 641 11 is_stmt 0 view .LVU345
+ 1124 003e 04F58051 		add	r1, r4, #4096
+ 1125              	.LVL109:
+ 641:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 1126              		.loc 1 641 11 view .LVU346
+ 1127 0042 B1F8862B 		ldrh	r2, [r1, #2950]
+ 641:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 1128              		.loc 1 641 20 view .LVU347
+ 1129 0046 02F55C62 		add	r2, r2, #3520
+ 1130 004a 92B2     		uxth	r2, r2
+ 1131 004c A1F8862B 		strh	r2, [r1, #2950]	@ movhi
+ 643:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 1132              		.loc 1 643 5 is_stmt 1 view .LVU348
+ 643:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 1133              		.loc 1 643 8 is_stmt 0 view .LVU349
+ 1134 0050 B2F5DC5F 		cmp	r2, #7040
+ 1135 0054 E1D1     		bne	.L73
+ 646:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 1136              		.loc 1 646 7 is_stmt 1 view .LVU350
+ 646:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 1137              		.loc 1 646 22 is_stmt 0 view .LVU351
+ 1138 0056 0A46     		mov	r2, r1
+ 1139 0058 0021     		movs	r1, #0
+ 1140 005a A2F8861B 		strh	r1, [r2, #2950]	@ movhi
+ 1141 005e DCE7     		b	.L73
+ 1142              	.L74:
+ 666:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 1143              		.loc 1 666 5 is_stmt 1 view .LVU352
+ 666:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 1144              		.loc 1 666 25 is_stmt 0 view .LVU353
+ 1145 0060 521A     		subs	r2, r2, r1
+ 666:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     {
+ 1146              		.loc 1 666 8 view .LVU354
+ 1147 0062 572A     		cmp	r2, #87
+ 1148 0064 0EDD     		ble	.L78
+ 672:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 1149              		.loc 1 672 7 is_stmt 1 view .LVU355
+ 672:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       {
+ 1150              		.loc 1 672 10 is_stmt 0 view .LVU356
+ 1151 0066 41F62831 		movw	r1, #6952
+ 1152 006a 8A42     		cmp	r2, r1
+ 1153 006c 0DDC     		bgt	.L79
+ 628:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 1154              		.loc 1 628 12 view .LVU357
+ 1155 006e 4FF45C61 		mov	r1, #3520
+ 1156 0072 01E0     		b	.L75
+ 1157              	.L76:
+ 654:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 1158              		.loc 1 654 18 view .LVU358
+ 1159 0074 40F6C451 		movw	r1, #3524
+ 1160              	.L75:
+ 1161              	.LVL110:
+ 679:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ARM GAS  /tmp/ccdtFdaF.s 			page 41
+
+
+ 1162              		.loc 1 679 3 is_stmt 1 view .LVU359
+ 679:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 1163              		.loc 1 679 6 is_stmt 0 view .LVU360
+ 1164 0078 022B     		cmp	r3, #2
+ 1165 007a 09D0     		beq	.L82
+ 1166              	.LVL111:
+ 1167              	.L71:
+ 685:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 1168              		.loc 1 685 1 view .LVU361
+ 1169 007c 10BD     		pop	{r4, pc}
+ 1170              	.LVL112:
+ 1171              	.L77:
+ 660:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 1172              		.loc 1 660 20 view .LVU362
+ 1173 007e 40F6BC51 		movw	r1, #3516
+ 1174 0082 F9E7     		b	.L75
+ 1175              	.L78:
+ 668:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     }
+ 1176              		.loc 1 668 18 view .LVU363
+ 1177 0084 40F6BC51 		movw	r1, #3516
+ 1178 0088 F6E7     		b	.L75
+ 1179              	.L79:
+ 674:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****       }
+ 1180              		.loc 1 674 20 view .LVU364
+ 1181 008a 40F6C451 		movw	r1, #3524
+ 1182 008e F3E7     		b	.L75
+ 1183              	.LVL113:
+ 1184              	.L82:
+ 681:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                          BufferSize, AUDIO_CMD_PLAY);
+ 1185              		.loc 1 681 5 is_stmt 1 view .LVU365
+ 681:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                          BufferSize, AUDIO_CMD_PLAY);
+ 1186              		.loc 1 681 35 is_stmt 0 view .LVU366
+ 1187 0090 D0F8C032 		ldr	r3, [r0, #704]
+ 681:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                          BufferSize, AUDIO_CMD_PLAY);
+ 1188              		.loc 1 681 47 view .LVU367
+ 1189 0094 9B68     		ldr	r3, [r3, #8]
+ 681:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                          BufferSize, AUDIO_CMD_PLAY);
+ 1190              		.loc 1 681 6 view .LVU368
+ 1191 0096 0222     		movs	r2, #2
+ 1192 0098 201D     		adds	r0, r4, #4
+ 1193              	.LVL114:
+ 681:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                                          BufferSize, AUDIO_CMD_PLAY);
+ 1194              		.loc 1 681 6 view .LVU369
+ 1195 009a 9847     		blx	r3
+ 1196              	.LVL115:
+ 683:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 1197              		.loc 1 683 5 is_stmt 1 view .LVU370
+ 683:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 1198              		.loc 1 683 20 is_stmt 0 view .LVU371
+ 1199 009c 04F58054 		add	r4, r4, #4096
+ 1200              	.LVL116:
+ 683:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 1201              		.loc 1 683 20 view .LVU372
+ 1202 00a0 0023     		movs	r3, #0
+ 1203 00a2 84F8843B 		strb	r3, [r4, #2948]
+ 1204 00a6 E9E7     		b	.L71
+ 1205              		.cfi_endproc
+ARM GAS  /tmp/ccdtFdaF.s 			page 42
+
+
+ 1206              	.LFE341:
+ 1208              		.section	.text.USBD_AUDIO_RegisterInterface,"ax",%progbits
+ 1209              		.align	1
+ 1210              		.global	USBD_AUDIO_RegisterInterface
+ 1211              		.syntax unified
+ 1212              		.thumb
+ 1213              		.thumb_func
+ 1215              	USBD_AUDIO_RegisterInterface:
+ 1216              	.LVL117:
+ 1217              	.LFB348:
+ 841:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 842:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** /**
+ 843:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @brief  USBD_AUDIO_RegisterInterface
+ 844:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @param  fops: Audio interface callback
+ 845:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   * @retval status
+ 846:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   */
+ 847:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** uint8_t USBD_AUDIO_RegisterInterface(USBD_HandleTypeDef *pdev,
+ 848:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****                                      USBD_AUDIO_ItfTypeDef *fops)
+ 849:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** {
+ 1218              		.loc 1 849 1 is_stmt 1 view -0
+ 1219              		.cfi_startproc
+ 1220              		@ args = 0, pretend = 0, frame = 0
+ 1221              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1222              		@ link register save eliminated.
+ 850:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   if (fops == NULL)
+ 1223              		.loc 1 850 3 view .LVU374
+ 1224              		.loc 1 850 6 is_stmt 0 view .LVU375
+ 1225 0000 19B1     		cbz	r1, .L85
+ 851:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   {
+ 852:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****     return (uint8_t)USBD_FAIL;
+ 853:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 854:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 855:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   pdev->pUserData = fops;
+ 1226              		.loc 1 855 3 is_stmt 1 view .LVU376
+ 1227              		.loc 1 855 19 is_stmt 0 view .LVU377
+ 1228 0002 C0F8C012 		str	r1, [r0, #704]
+ 856:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** 
+ 857:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   return (uint8_t)USBD_OK;
+ 1229              		.loc 1 857 3 is_stmt 1 view .LVU378
+ 1230              		.loc 1 857 10 is_stmt 0 view .LVU379
+ 1231 0006 0020     		movs	r0, #0
+ 1232              	.LVL118:
+ 1233              		.loc 1 857 10 view .LVU380
+ 1234 0008 7047     		bx	lr
+ 1235              	.LVL119:
+ 1236              	.L85:
+ 852:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c ****   }
+ 1237              		.loc 1 852 12 view .LVU381
+ 1238 000a 0320     		movs	r0, #3
+ 1239              	.LVL120:
+ 858:Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c **** }
+ 1240              		.loc 1 858 1 view .LVU382
+ 1241 000c 7047     		bx	lr
+ 1242              		.cfi_endproc
+ 1243              	.LFE348:
+ 1245              		.section	.data.USBD_AUDIO_DeviceQualifierDesc,"aw"
+ 1246              		.align	2
+ARM GAS  /tmp/ccdtFdaF.s 			page 43
+
+
+ 1249              	USBD_AUDIO_DeviceQualifierDesc:
+ 1250 0000 0A060002 		.ascii	"\012\006\000\002\000\000\000@\001\000"
+ 1250      00000040 
+ 1250      0100
+ 1251              		.section	.data.USBD_AUDIO_CfgDesc,"aw"
+ 1252              		.align	2
+ 1255              	USBD_AUDIO_CfgDesc:
+ 1256 0000 09026D00 		.ascii	"\011\002m\000\002\001\000\3002\011\004\000\000\000\001"
+ 1256      020100C0 
+ 1256      32090400 
+ 1256      000001
+ 1257 000f 01000009 		.ascii	"\001\000\000\011$\001\000\001'\000\001\001\014$\002"
+ 1257      24010001 
+ 1257      27000101 
+ 1257      0C2402
+ 1258 001e 01010100 		.ascii	"\001\001\001\000\001\000\000\000\000\011$\006\002\001"
+ 1258      01000000 
+ 1258      00092406 
+ 1258      0201
+ 1259 002c 01010000 		.ascii	"\001\001\000\000\011$\003\003\001\003\000\002\000\011"
+ 1259      09240303 
+ 1259      01030002 
+ 1259      0009
+ 1260 003a 04010000 		.ascii	"\004\001\000\000\001\002\000\000\011\004\001\001\001"
+ 1260      01020000 
+ 1260      09040101 
+ 1260      01
+ 1261 0047 01020000 		.ascii	"\001\002\000\000\007$\001\001\001\001\000\013$\002\001"
+ 1261      07240101 
+ 1261      0101000B 
+ 1261      240201
+ 1262 0056 02021001 		.ascii	"\002\002\020\001TV\000\011\005\001\001X\000\001\000"
+ 1262      54560009 
+ 1262      05010158 
+ 1262      000100
+ 1263 0065 00072501 		.ascii	"\000\007%\001\000\000\000\000"
+ 1263      00000000 
+ 1264              		.global	USBD_AUDIO
+ 1265              		.section	.data.USBD_AUDIO,"aw"
+ 1266              		.align	2
+ 1269              	USBD_AUDIO:
+ 1270 0000 00000000 		.word	USBD_AUDIO_Init
+ 1271 0004 00000000 		.word	USBD_AUDIO_DeInit
+ 1272 0008 00000000 		.word	USBD_AUDIO_Setup
+ 1273 000c 00000000 		.word	USBD_AUDIO_EP0_TxReady
+ 1274 0010 00000000 		.word	USBD_AUDIO_EP0_RxReady
+ 1275 0014 00000000 		.word	USBD_AUDIO_DataIn
+ 1276 0018 00000000 		.word	USBD_AUDIO_DataOut
+ 1277 001c 00000000 		.word	USBD_AUDIO_SOF
+ 1278 0020 00000000 		.word	USBD_AUDIO_IsoINIncomplete
+ 1279 0024 00000000 		.word	USBD_AUDIO_IsoOutIncomplete
+ 1280 0028 00000000 		.word	USBD_AUDIO_GetCfgDesc
+ 1281 002c 00000000 		.word	USBD_AUDIO_GetCfgDesc
+ 1282 0030 00000000 		.word	USBD_AUDIO_GetCfgDesc
+ 1283 0034 00000000 		.word	USBD_AUDIO_GetDeviceQualifierDesc
+ 1284              		.text
+ 1285              	.Letext0:
+ARM GAS  /tmp/ccdtFdaF.s 			page 44
+
+
+ 1286              		.file 2 "/usr/include/newlib/machine/_default_types.h"
+ 1287              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stddef.h"
+ 1288              		.file 4 "/usr/include/newlib/sys/_stdint.h"
+ 1289              		.file 5 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h"
+ 1290              		.file 6 "Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h"
+ 1291              		.file 7 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h"
+ 1292              		.file 8 "Inc/usbd_conf.h"
+ 1293              		.file 9 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h"
+ 1294              		.file 10 "/usr/include/newlib/string.h"
+ 1295              		.file 11 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h"
+ 1296              		.file 12 "<built-in>"
+ARM GAS  /tmp/ccdtFdaF.s 			page 45
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 usbd_audio.c
+     /tmp/ccdtFdaF.s:21     .text.USBD_AUDIO_GetCfgDesc:00000000 $t
+     /tmp/ccdtFdaF.s:26     .text.USBD_AUDIO_GetCfgDesc:00000000 USBD_AUDIO_GetCfgDesc
+     /tmp/ccdtFdaF.s:47     .text.USBD_AUDIO_GetCfgDesc:00000008 $d
+     /tmp/ccdtFdaF.s:1255   .data.USBD_AUDIO_CfgDesc:00000000 USBD_AUDIO_CfgDesc
+     /tmp/ccdtFdaF.s:52     .text.USBD_AUDIO_DataIn:00000000 $t
+     /tmp/ccdtFdaF.s:57     .text.USBD_AUDIO_DataIn:00000000 USBD_AUDIO_DataIn
+     /tmp/ccdtFdaF.s:77     .text.USBD_AUDIO_EP0_RxReady:00000000 $t
+     /tmp/ccdtFdaF.s:82     .text.USBD_AUDIO_EP0_RxReady:00000000 USBD_AUDIO_EP0_RxReady
+     /tmp/ccdtFdaF.s:165    .text.USBD_AUDIO_EP0_TxReady:00000000 $t
+     /tmp/ccdtFdaF.s:170    .text.USBD_AUDIO_EP0_TxReady:00000000 USBD_AUDIO_EP0_TxReady
+     /tmp/ccdtFdaF.s:189    .text.USBD_AUDIO_SOF:00000000 $t
+     /tmp/ccdtFdaF.s:194    .text.USBD_AUDIO_SOF:00000000 USBD_AUDIO_SOF
+     /tmp/ccdtFdaF.s:213    .text.USBD_AUDIO_IsoINIncomplete:00000000 $t
+     /tmp/ccdtFdaF.s:218    .text.USBD_AUDIO_IsoINIncomplete:00000000 USBD_AUDIO_IsoINIncomplete
+     /tmp/ccdtFdaF.s:238    .text.USBD_AUDIO_IsoOutIncomplete:00000000 $t
+     /tmp/ccdtFdaF.s:243    .text.USBD_AUDIO_IsoOutIncomplete:00000000 USBD_AUDIO_IsoOutIncomplete
+     /tmp/ccdtFdaF.s:263    .text.USBD_AUDIO_GetDeviceQualifierDesc:00000000 $t
+     /tmp/ccdtFdaF.s:268    .text.USBD_AUDIO_GetDeviceQualifierDesc:00000000 USBD_AUDIO_GetDeviceQualifierDesc
+     /tmp/ccdtFdaF.s:289    .text.USBD_AUDIO_GetDeviceQualifierDesc:00000008 $d
+     /tmp/ccdtFdaF.s:1249   .data.USBD_AUDIO_DeviceQualifierDesc:00000000 USBD_AUDIO_DeviceQualifierDesc
+     /tmp/ccdtFdaF.s:294    .text.USBD_AUDIO_DataOut:00000000 $t
+     /tmp/ccdtFdaF.s:299    .text.USBD_AUDIO_DataOut:00000000 USBD_AUDIO_DataOut
+     /tmp/ccdtFdaF.s:447    .text.AUDIO_REQ_GetCurrent:00000000 $t
+     /tmp/ccdtFdaF.s:452    .text.AUDIO_REQ_GetCurrent:00000000 AUDIO_REQ_GetCurrent
+     /tmp/ccdtFdaF.s:507    .text.AUDIO_REQ_SetCurrent:00000000 $t
+     /tmp/ccdtFdaF.s:512    .text.AUDIO_REQ_SetCurrent:00000000 AUDIO_REQ_SetCurrent
+     /tmp/ccdtFdaF.s:578    .text.USBD_AUDIO_Setup:00000000 $t
+     /tmp/ccdtFdaF.s:583    .text.USBD_AUDIO_Setup:00000000 USBD_AUDIO_Setup
+     /tmp/ccdtFdaF.s:672    .text.USBD_AUDIO_Setup:0000004a $d
+     /tmp/ccdtFdaF.s:684    .text.USBD_AUDIO_Setup:00000056 $t
+     /tmp/ccdtFdaF.s:850    .text.USBD_AUDIO_Setup:000000e8 $d
+     /tmp/ccdtFdaF.s:855    .text.USBD_AUDIO_DeInit:00000000 $t
+     /tmp/ccdtFdaF.s:860    .text.USBD_AUDIO_DeInit:00000000 USBD_AUDIO_DeInit
+     /tmp/ccdtFdaF.s:921    .text.USBD_AUDIO_Init:00000000 $t
+     /tmp/ccdtFdaF.s:926    .text.USBD_AUDIO_Init:00000000 USBD_AUDIO_Init
+     /tmp/ccdtFdaF.s:1055   .text.USBD_AUDIO_Sync:00000000 $t
+     /tmp/ccdtFdaF.s:1061   .text.USBD_AUDIO_Sync:00000000 USBD_AUDIO_Sync
+     /tmp/ccdtFdaF.s:1209   .text.USBD_AUDIO_RegisterInterface:00000000 $t
+     /tmp/ccdtFdaF.s:1215   .text.USBD_AUDIO_RegisterInterface:00000000 USBD_AUDIO_RegisterInterface
+     /tmp/ccdtFdaF.s:1246   .data.USBD_AUDIO_DeviceQualifierDesc:00000000 $d
+     /tmp/ccdtFdaF.s:1252   .data.USBD_AUDIO_CfgDesc:00000000 $d
+     /tmp/ccdtFdaF.s:1269   .data.USBD_AUDIO:00000000 USBD_AUDIO
+     /tmp/ccdtFdaF.s:1266   .data.USBD_AUDIO:00000000 $d
+
+UNDEFINED SYMBOLS
+USBD_LL_GetRxDataSize
+USBD_LL_PrepareReceive
+memset
+USBD_CtlSendData
+USBD_CtlPrepareRx
+USBD_CtlError
+USBD_LL_CloseEP
+USBD_static_free
+USBD_static_malloc
+USBD_LL_OpenEP
+ARM GAS  /tmp/ccdtFdaF.s 			page 46
+
+
diff --git a/squeow_sw/build/usbd_audio.o b/squeow_sw/build/usbd_audio.o
new file mode 100644
index 0000000000000000000000000000000000000000..09417e2d3baf2cc96d1a82ee9054b9f97c0adbb6
GIT binary patch
literal 26716
zcmc(n33yf2x%c;Q_DN21GKVpMCj$@?GBT>D0YV^*nLwNxLUKZK4M|K+7`$3h0TE~G
zr_?D_X+_KDfUQb}YAvnST19KCZE2-yi?+0Ct$eAq*Zcpk_3o3ML+tH$@Ao|4ezNmh
z?^^GA*Sp5O_CEWZD;6xRGELKP57Wpu1|`F2S))>%=?eMAG^5;DpKEV17IiOFQK9aI
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diff --git a/squeow_sw/build/usbd_audio_if.d b/squeow_sw/build/usbd_audio_if.d
new file mode 100644
index 0000000..883b53a
--- /dev/null
+++ b/squeow_sw/build/usbd_audio_if.d
@@ -0,0 +1,87 @@
+build/usbd_audio_if.o: Src/usbd_audio_if.c Inc/usbd_audio_if.h \
+ Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \
+ Inc/usbd_conf.h Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
+Inc/usbd_audio_if.h:
+Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
+Inc/usbd_conf.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h:
diff --git a/squeow_sw/build/usbd_audio_if.lst b/squeow_sw/build/usbd_audio_if.lst
new file mode 100644
index 0000000..1420bb6
--- /dev/null
+++ b/squeow_sw/build/usbd_audio_if.lst
@@ -0,0 +1,588 @@
+ARM GAS  /tmp/ccLD46hm.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"usbd_audio_if.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Src/usbd_audio_if.c"
+  20              		.section	.text.AUDIO_Init_FS,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	AUDIO_Init_FS:
+  27              	.LVL0:
+  28              	.LFB333:
+   1:Src/usbd_audio_if.c **** /* USER CODE BEGIN Header */
+   2:Src/usbd_audio_if.c **** /**
+   3:Src/usbd_audio_if.c ****   ******************************************************************************
+   4:Src/usbd_audio_if.c ****   * @file           : usbd_audio_if.c
+   5:Src/usbd_audio_if.c ****   * @version        : v3.0_Cube
+   6:Src/usbd_audio_if.c ****   * @brief          : Generic media access layer.
+   7:Src/usbd_audio_if.c ****   ******************************************************************************
+   8:Src/usbd_audio_if.c ****   * @attention
+   9:Src/usbd_audio_if.c ****   *
+  10:Src/usbd_audio_if.c ****   * Copyright (c) 2022 STMicroelectronics.
+  11:Src/usbd_audio_if.c ****   * All rights reserved.
+  12:Src/usbd_audio_if.c ****   *
+  13:Src/usbd_audio_if.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  14:Src/usbd_audio_if.c ****   * in the root directory of this software component.
+  15:Src/usbd_audio_if.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  16:Src/usbd_audio_if.c ****   *
+  17:Src/usbd_audio_if.c ****   ******************************************************************************
+  18:Src/usbd_audio_if.c ****   */
+  19:Src/usbd_audio_if.c ****  /* USER CODE END Header */
+  20:Src/usbd_audio_if.c **** 
+  21:Src/usbd_audio_if.c **** /* Includes ------------------------------------------------------------------*/
+  22:Src/usbd_audio_if.c **** #include "usbd_audio_if.h"
+  23:Src/usbd_audio_if.c **** 
+  24:Src/usbd_audio_if.c **** /* USER CODE BEGIN INCLUDE */
+  25:Src/usbd_audio_if.c **** 
+  26:Src/usbd_audio_if.c **** /* USER CODE END INCLUDE */
+  27:Src/usbd_audio_if.c **** 
+  28:Src/usbd_audio_if.c **** /* Private typedef -----------------------------------------------------------*/
+  29:Src/usbd_audio_if.c **** /* Private define ------------------------------------------------------------*/
+  30:Src/usbd_audio_if.c **** /* Private macro -------------------------------------------------------------*/
+ARM GAS  /tmp/ccLD46hm.s 			page 2
+
+
+  31:Src/usbd_audio_if.c **** 
+  32:Src/usbd_audio_if.c **** /* USER CODE BEGIN PV */
+  33:Src/usbd_audio_if.c **** /* Private variables ---------------------------------------------------------*/
+  34:Src/usbd_audio_if.c **** 
+  35:Src/usbd_audio_if.c **** /* USER CODE END PV */
+  36:Src/usbd_audio_if.c **** 
+  37:Src/usbd_audio_if.c **** /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  38:Src/usbd_audio_if.c ****   * @brief Usb device library.
+  39:Src/usbd_audio_if.c ****   * @{
+  40:Src/usbd_audio_if.c ****   */
+  41:Src/usbd_audio_if.c **** 
+  42:Src/usbd_audio_if.c **** /** @addtogroup USBD_AUDIO_IF
+  43:Src/usbd_audio_if.c ****   * @{
+  44:Src/usbd_audio_if.c ****   */
+  45:Src/usbd_audio_if.c **** 
+  46:Src/usbd_audio_if.c **** /** @defgroup USBD_AUDIO_IF_Private_TypesDefinitions USBD_AUDIO_IF_Private_TypesDefinitions
+  47:Src/usbd_audio_if.c ****   * @brief Private types.
+  48:Src/usbd_audio_if.c ****   * @{
+  49:Src/usbd_audio_if.c ****   */
+  50:Src/usbd_audio_if.c **** 
+  51:Src/usbd_audio_if.c **** /* USER CODE BEGIN PRIVATE_TYPES */
+  52:Src/usbd_audio_if.c **** 
+  53:Src/usbd_audio_if.c **** /* USER CODE END PRIVATE_TYPES */
+  54:Src/usbd_audio_if.c **** 
+  55:Src/usbd_audio_if.c **** /**
+  56:Src/usbd_audio_if.c ****   * @}
+  57:Src/usbd_audio_if.c ****   */
+  58:Src/usbd_audio_if.c **** 
+  59:Src/usbd_audio_if.c **** /** @defgroup USBD_AUDIO_IF_Private_Defines USBD_AUDIO_IF_Private_Defines
+  60:Src/usbd_audio_if.c ****   * @brief Private defines.
+  61:Src/usbd_audio_if.c ****   * @{
+  62:Src/usbd_audio_if.c ****   */
+  63:Src/usbd_audio_if.c **** 
+  64:Src/usbd_audio_if.c **** /* USER CODE BEGIN PRIVATE_DEFINES */
+  65:Src/usbd_audio_if.c **** 
+  66:Src/usbd_audio_if.c **** /* USER CODE END PRIVATE_DEFINES */
+  67:Src/usbd_audio_if.c **** 
+  68:Src/usbd_audio_if.c **** /**
+  69:Src/usbd_audio_if.c ****   * @}
+  70:Src/usbd_audio_if.c ****   */
+  71:Src/usbd_audio_if.c **** 
+  72:Src/usbd_audio_if.c **** /** @defgroup USBD_AUDIO_IF_Private_Macros USBD_AUDIO_IF_Private_Macros
+  73:Src/usbd_audio_if.c ****   * @brief Private macros.
+  74:Src/usbd_audio_if.c ****   * @{
+  75:Src/usbd_audio_if.c ****   */
+  76:Src/usbd_audio_if.c **** 
+  77:Src/usbd_audio_if.c **** /* USER CODE BEGIN PRIVATE_MACRO */
+  78:Src/usbd_audio_if.c **** 
+  79:Src/usbd_audio_if.c **** /* USER CODE END PRIVATE_MACRO */
+  80:Src/usbd_audio_if.c **** 
+  81:Src/usbd_audio_if.c **** /**
+  82:Src/usbd_audio_if.c ****   * @}
+  83:Src/usbd_audio_if.c ****   */
+  84:Src/usbd_audio_if.c **** 
+  85:Src/usbd_audio_if.c **** /** @defgroup USBD_AUDIO_IF_Private_Variables USBD_AUDIO_IF_Private_Variables
+  86:Src/usbd_audio_if.c ****   * @brief Private variables.
+  87:Src/usbd_audio_if.c ****   * @{
+ARM GAS  /tmp/ccLD46hm.s 			page 3
+
+
+  88:Src/usbd_audio_if.c ****   */
+  89:Src/usbd_audio_if.c **** 
+  90:Src/usbd_audio_if.c **** /* USER CODE BEGIN PRIVATE_VARIABLES */
+  91:Src/usbd_audio_if.c **** 
+  92:Src/usbd_audio_if.c **** /* USER CODE END PRIVATE_VARIABLES */
+  93:Src/usbd_audio_if.c **** 
+  94:Src/usbd_audio_if.c **** /**
+  95:Src/usbd_audio_if.c ****   * @}
+  96:Src/usbd_audio_if.c ****   */
+  97:Src/usbd_audio_if.c **** 
+  98:Src/usbd_audio_if.c **** /** @defgroup USBD_AUDIO_IF_Exported_Variables USBD_AUDIO_IF_Exported_Variables
+  99:Src/usbd_audio_if.c ****   * @brief Public variables.
+ 100:Src/usbd_audio_if.c ****   * @{
+ 101:Src/usbd_audio_if.c ****   */
+ 102:Src/usbd_audio_if.c **** 
+ 103:Src/usbd_audio_if.c **** extern USBD_HandleTypeDef hUsbDeviceFS;
+ 104:Src/usbd_audio_if.c **** 
+ 105:Src/usbd_audio_if.c **** /* USER CODE BEGIN EXPORTED_VARIABLES */
+ 106:Src/usbd_audio_if.c **** 
+ 107:Src/usbd_audio_if.c **** /* USER CODE END EXPORTED_VARIABLES */
+ 108:Src/usbd_audio_if.c **** 
+ 109:Src/usbd_audio_if.c **** /**
+ 110:Src/usbd_audio_if.c ****   * @}
+ 111:Src/usbd_audio_if.c ****   */
+ 112:Src/usbd_audio_if.c **** 
+ 113:Src/usbd_audio_if.c **** /** @defgroup USBD_AUDIO_IF_Private_FunctionPrototypes USBD_AUDIO_IF_Private_FunctionPrototypes
+ 114:Src/usbd_audio_if.c ****   * @brief Private functions declaration.
+ 115:Src/usbd_audio_if.c ****   * @{
+ 116:Src/usbd_audio_if.c ****   */
+ 117:Src/usbd_audio_if.c **** 
+ 118:Src/usbd_audio_if.c **** static int8_t AUDIO_Init_FS(uint32_t AudioFreq, uint32_t Volume, uint32_t options);
+ 119:Src/usbd_audio_if.c **** static int8_t AUDIO_DeInit_FS(uint32_t options);
+ 120:Src/usbd_audio_if.c **** static int8_t AUDIO_AudioCmd_FS(uint8_t* pbuf, uint32_t size, uint8_t cmd);
+ 121:Src/usbd_audio_if.c **** static int8_t AUDIO_VolumeCtl_FS(uint8_t vol);
+ 122:Src/usbd_audio_if.c **** static int8_t AUDIO_MuteCtl_FS(uint8_t cmd);
+ 123:Src/usbd_audio_if.c **** static int8_t AUDIO_PeriodicTC_FS(uint8_t *pbuf, uint32_t size, uint8_t cmd);
+ 124:Src/usbd_audio_if.c **** static int8_t AUDIO_GetState_FS(void);
+ 125:Src/usbd_audio_if.c **** 
+ 126:Src/usbd_audio_if.c **** /* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */
+ 127:Src/usbd_audio_if.c **** 
+ 128:Src/usbd_audio_if.c **** /* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */
+ 129:Src/usbd_audio_if.c **** 
+ 130:Src/usbd_audio_if.c **** /**
+ 131:Src/usbd_audio_if.c ****   * @}
+ 132:Src/usbd_audio_if.c ****   */
+ 133:Src/usbd_audio_if.c **** 
+ 134:Src/usbd_audio_if.c **** USBD_AUDIO_ItfTypeDef USBD_AUDIO_fops_FS =
+ 135:Src/usbd_audio_if.c **** {
+ 136:Src/usbd_audio_if.c ****   AUDIO_Init_FS,
+ 137:Src/usbd_audio_if.c ****   AUDIO_DeInit_FS,
+ 138:Src/usbd_audio_if.c ****   AUDIO_AudioCmd_FS,
+ 139:Src/usbd_audio_if.c ****   AUDIO_VolumeCtl_FS,
+ 140:Src/usbd_audio_if.c ****   AUDIO_MuteCtl_FS,
+ 141:Src/usbd_audio_if.c ****   AUDIO_PeriodicTC_FS,
+ 142:Src/usbd_audio_if.c ****   AUDIO_GetState_FS,
+ 143:Src/usbd_audio_if.c **** };
+ 144:Src/usbd_audio_if.c **** 
+ARM GAS  /tmp/ccLD46hm.s 			page 4
+
+
+ 145:Src/usbd_audio_if.c **** /* Private functions ---------------------------------------------------------*/
+ 146:Src/usbd_audio_if.c **** /**
+ 147:Src/usbd_audio_if.c ****   * @brief  Initializes the AUDIO media low layer over USB FS IP
+ 148:Src/usbd_audio_if.c ****   * @param  AudioFreq: Audio frequency used to play the audio stream.
+ 149:Src/usbd_audio_if.c ****   * @param  Volume: Initial volume level (from 0 (Mute) to 100 (Max))
+ 150:Src/usbd_audio_if.c ****   * @param  options: Reserved for future use
+ 151:Src/usbd_audio_if.c ****   * @retval USBD_OK if all operations are OK else USBD_FAIL
+ 152:Src/usbd_audio_if.c ****   */
+ 153:Src/usbd_audio_if.c **** static int8_t AUDIO_Init_FS(uint32_t AudioFreq, uint32_t Volume, uint32_t options)
+ 154:Src/usbd_audio_if.c **** {
+  29              		.loc 1 154 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+ 155:Src/usbd_audio_if.c ****   /* USER CODE BEGIN 0 */
+ 156:Src/usbd_audio_if.c ****   UNUSED(AudioFreq);
+  34              		.loc 1 156 3 view .LVU1
+ 157:Src/usbd_audio_if.c ****   UNUSED(Volume);
+  35              		.loc 1 157 3 view .LVU2
+ 158:Src/usbd_audio_if.c ****   UNUSED(options);
+  36              		.loc 1 158 3 view .LVU3
+ 159:Src/usbd_audio_if.c ****   return (USBD_OK);
+  37              		.loc 1 159 3 view .LVU4
+ 160:Src/usbd_audio_if.c ****   /* USER CODE END 0 */
+ 161:Src/usbd_audio_if.c **** }
+  38              		.loc 1 161 1 is_stmt 0 view .LVU5
+  39 0000 0020     		movs	r0, #0
+  40              	.LVL1:
+  41              		.loc 1 161 1 view .LVU6
+  42 0002 7047     		bx	lr
+  43              		.cfi_endproc
+  44              	.LFE333:
+  46              		.section	.text.AUDIO_DeInit_FS,"ax",%progbits
+  47              		.align	1
+  48              		.syntax unified
+  49              		.thumb
+  50              		.thumb_func
+  52              	AUDIO_DeInit_FS:
+  53              	.LVL2:
+  54              	.LFB334:
+ 162:Src/usbd_audio_if.c **** 
+ 163:Src/usbd_audio_if.c **** /**
+ 164:Src/usbd_audio_if.c ****   * @brief  De-Initializes the AUDIO media low layer
+ 165:Src/usbd_audio_if.c ****   * @param  options: Reserved for future use
+ 166:Src/usbd_audio_if.c ****   * @retval USBD_OK if all operations are OK else USBD_FAIL
+ 167:Src/usbd_audio_if.c ****   */
+ 168:Src/usbd_audio_if.c **** static int8_t AUDIO_DeInit_FS(uint32_t options)
+ 169:Src/usbd_audio_if.c **** {
+  55              		.loc 1 169 1 is_stmt 1 view -0
+  56              		.cfi_startproc
+  57              		@ args = 0, pretend = 0, frame = 0
+  58              		@ frame_needed = 0, uses_anonymous_args = 0
+  59              		@ link register save eliminated.
+ 170:Src/usbd_audio_if.c ****   /* USER CODE BEGIN 1 */
+ 171:Src/usbd_audio_if.c ****   UNUSED(options);
+  60              		.loc 1 171 3 view .LVU8
+ARM GAS  /tmp/ccLD46hm.s 			page 5
+
+
+ 172:Src/usbd_audio_if.c ****   return (USBD_OK);
+  61              		.loc 1 172 3 view .LVU9
+ 173:Src/usbd_audio_if.c ****   /* USER CODE END 1 */
+ 174:Src/usbd_audio_if.c **** }
+  62              		.loc 1 174 1 is_stmt 0 view .LVU10
+  63 0000 0020     		movs	r0, #0
+  64              	.LVL3:
+  65              		.loc 1 174 1 view .LVU11
+  66 0002 7047     		bx	lr
+  67              		.cfi_endproc
+  68              	.LFE334:
+  70              		.section	.text.AUDIO_AudioCmd_FS,"ax",%progbits
+  71              		.align	1
+  72              		.syntax unified
+  73              		.thumb
+  74              		.thumb_func
+  76              	AUDIO_AudioCmd_FS:
+  77              	.LVL4:
+  78              	.LFB335:
+ 175:Src/usbd_audio_if.c **** 
+ 176:Src/usbd_audio_if.c **** /**
+ 177:Src/usbd_audio_if.c ****   * @brief  Handles AUDIO command.
+ 178:Src/usbd_audio_if.c ****   * @param  pbuf: Pointer to buffer of data to be sent
+ 179:Src/usbd_audio_if.c ****   * @param  size: Number of data to be sent (in bytes)
+ 180:Src/usbd_audio_if.c ****   * @param  cmd: Command opcode
+ 181:Src/usbd_audio_if.c ****   * @retval USBD_OK if all operations are OK else USBD_FAIL
+ 182:Src/usbd_audio_if.c ****   */
+ 183:Src/usbd_audio_if.c **** static int8_t AUDIO_AudioCmd_FS(uint8_t* pbuf, uint32_t size, uint8_t cmd)
+ 184:Src/usbd_audio_if.c **** {
+  79              		.loc 1 184 1 is_stmt 1 view -0
+  80              		.cfi_startproc
+  81              		@ args = 0, pretend = 0, frame = 0
+  82              		@ frame_needed = 0, uses_anonymous_args = 0
+  83              		@ link register save eliminated.
+ 185:Src/usbd_audio_if.c ****   /* USER CODE BEGIN 2 */
+ 186:Src/usbd_audio_if.c ****   switch(cmd)
+  84              		.loc 1 186 3 view .LVU13
+ 187:Src/usbd_audio_if.c ****   {
+ 188:Src/usbd_audio_if.c ****     case AUDIO_CMD_START:
+ 189:Src/usbd_audio_if.c ****     break;
+ 190:Src/usbd_audio_if.c **** 
+ 191:Src/usbd_audio_if.c ****     case AUDIO_CMD_PLAY:
+ 192:Src/usbd_audio_if.c ****     break;
+ 193:Src/usbd_audio_if.c ****   }
+ 194:Src/usbd_audio_if.c ****   UNUSED(pbuf);
+  85              		.loc 1 194 3 view .LVU14
+ 195:Src/usbd_audio_if.c ****   UNUSED(size);
+  86              		.loc 1 195 3 view .LVU15
+ 196:Src/usbd_audio_if.c ****   UNUSED(cmd);
+  87              		.loc 1 196 3 view .LVU16
+ 197:Src/usbd_audio_if.c ****   return (USBD_OK);
+  88              		.loc 1 197 3 view .LVU17
+ 198:Src/usbd_audio_if.c ****   /* USER CODE END 2 */
+ 199:Src/usbd_audio_if.c **** }
+  89              		.loc 1 199 1 is_stmt 0 view .LVU18
+  90 0000 0020     		movs	r0, #0
+  91              	.LVL5:
+ARM GAS  /tmp/ccLD46hm.s 			page 6
+
+
+  92              		.loc 1 199 1 view .LVU19
+  93 0002 7047     		bx	lr
+  94              		.cfi_endproc
+  95              	.LFE335:
+  97              		.section	.text.AUDIO_VolumeCtl_FS,"ax",%progbits
+  98              		.align	1
+  99              		.syntax unified
+ 100              		.thumb
+ 101              		.thumb_func
+ 103              	AUDIO_VolumeCtl_FS:
+ 104              	.LVL6:
+ 105              	.LFB336:
+ 200:Src/usbd_audio_if.c **** 
+ 201:Src/usbd_audio_if.c **** /**
+ 202:Src/usbd_audio_if.c ****   * @brief  Controls AUDIO Volume.
+ 203:Src/usbd_audio_if.c ****   * @param  vol: volume level (0..100)
+ 204:Src/usbd_audio_if.c ****   * @retval USBD_OK if all operations are OK else USBD_FAIL
+ 205:Src/usbd_audio_if.c ****   */
+ 206:Src/usbd_audio_if.c **** static int8_t AUDIO_VolumeCtl_FS(uint8_t vol)
+ 207:Src/usbd_audio_if.c **** {
+ 106              		.loc 1 207 1 is_stmt 1 view -0
+ 107              		.cfi_startproc
+ 108              		@ args = 0, pretend = 0, frame = 0
+ 109              		@ frame_needed = 0, uses_anonymous_args = 0
+ 110              		@ link register save eliminated.
+ 208:Src/usbd_audio_if.c ****   /* USER CODE BEGIN 3 */
+ 209:Src/usbd_audio_if.c ****   UNUSED(vol);
+ 111              		.loc 1 209 3 view .LVU21
+ 210:Src/usbd_audio_if.c ****   return (USBD_OK);
+ 112              		.loc 1 210 3 view .LVU22
+ 211:Src/usbd_audio_if.c ****   /* USER CODE END 3 */
+ 212:Src/usbd_audio_if.c **** }
+ 113              		.loc 1 212 1 is_stmt 0 view .LVU23
+ 114 0000 0020     		movs	r0, #0
+ 115              	.LVL7:
+ 116              		.loc 1 212 1 view .LVU24
+ 117 0002 7047     		bx	lr
+ 118              		.cfi_endproc
+ 119              	.LFE336:
+ 121              		.section	.text.AUDIO_MuteCtl_FS,"ax",%progbits
+ 122              		.align	1
+ 123              		.syntax unified
+ 124              		.thumb
+ 125              		.thumb_func
+ 127              	AUDIO_MuteCtl_FS:
+ 128              	.LVL8:
+ 129              	.LFB337:
+ 213:Src/usbd_audio_if.c **** 
+ 214:Src/usbd_audio_if.c **** /**
+ 215:Src/usbd_audio_if.c ****   * @brief  Controls AUDIO Mute.
+ 216:Src/usbd_audio_if.c ****   * @param  cmd: command opcode
+ 217:Src/usbd_audio_if.c ****   * @retval USBD_OK if all operations are OK else USBD_FAIL
+ 218:Src/usbd_audio_if.c ****   */
+ 219:Src/usbd_audio_if.c **** static int8_t AUDIO_MuteCtl_FS(uint8_t cmd)
+ 220:Src/usbd_audio_if.c **** {
+ 130              		.loc 1 220 1 is_stmt 1 view -0
+ 131              		.cfi_startproc
+ARM GAS  /tmp/ccLD46hm.s 			page 7
+
+
+ 132              		@ args = 0, pretend = 0, frame = 0
+ 133              		@ frame_needed = 0, uses_anonymous_args = 0
+ 134              		@ link register save eliminated.
+ 221:Src/usbd_audio_if.c ****   /* USER CODE BEGIN 4 */
+ 222:Src/usbd_audio_if.c ****   UNUSED(cmd);
+ 135              		.loc 1 222 3 view .LVU26
+ 223:Src/usbd_audio_if.c ****   return (USBD_OK);
+ 136              		.loc 1 223 3 view .LVU27
+ 224:Src/usbd_audio_if.c ****   /* USER CODE END 4 */
+ 225:Src/usbd_audio_if.c **** }
+ 137              		.loc 1 225 1 is_stmt 0 view .LVU28
+ 138 0000 0020     		movs	r0, #0
+ 139              	.LVL9:
+ 140              		.loc 1 225 1 view .LVU29
+ 141 0002 7047     		bx	lr
+ 142              		.cfi_endproc
+ 143              	.LFE337:
+ 145              		.section	.text.AUDIO_PeriodicTC_FS,"ax",%progbits
+ 146              		.align	1
+ 147              		.syntax unified
+ 148              		.thumb
+ 149              		.thumb_func
+ 151              	AUDIO_PeriodicTC_FS:
+ 152              	.LVL10:
+ 153              	.LFB338:
+ 226:Src/usbd_audio_if.c **** 
+ 227:Src/usbd_audio_if.c **** /**
+ 228:Src/usbd_audio_if.c ****   * @brief  AUDIO_PeriodicT_FS
+ 229:Src/usbd_audio_if.c ****   * @param  cmd: Command opcode
+ 230:Src/usbd_audio_if.c ****   * @retval USBD_OK if all operations are OK else USBD_FAIL
+ 231:Src/usbd_audio_if.c ****   */
+ 232:Src/usbd_audio_if.c **** static int8_t AUDIO_PeriodicTC_FS(uint8_t *pbuf, uint32_t size, uint8_t cmd)
+ 233:Src/usbd_audio_if.c **** {
+ 154              		.loc 1 233 1 is_stmt 1 view -0
+ 155              		.cfi_startproc
+ 156              		@ args = 0, pretend = 0, frame = 0
+ 157              		@ frame_needed = 0, uses_anonymous_args = 0
+ 158              		@ link register save eliminated.
+ 234:Src/usbd_audio_if.c ****   /* USER CODE BEGIN 5 */
+ 235:Src/usbd_audio_if.c ****   UNUSED(pbuf);
+ 159              		.loc 1 235 3 view .LVU31
+ 236:Src/usbd_audio_if.c ****   UNUSED(size);
+ 160              		.loc 1 236 3 view .LVU32
+ 237:Src/usbd_audio_if.c ****   UNUSED(cmd);
+ 161              		.loc 1 237 3 view .LVU33
+ 238:Src/usbd_audio_if.c ****   return (USBD_OK);
+ 162              		.loc 1 238 3 view .LVU34
+ 239:Src/usbd_audio_if.c ****   /* USER CODE END 5 */
+ 240:Src/usbd_audio_if.c **** }
+ 163              		.loc 1 240 1 is_stmt 0 view .LVU35
+ 164 0000 0020     		movs	r0, #0
+ 165              	.LVL11:
+ 166              		.loc 1 240 1 view .LVU36
+ 167 0002 7047     		bx	lr
+ 168              		.cfi_endproc
+ 169              	.LFE338:
+ 171              		.section	.text.AUDIO_GetState_FS,"ax",%progbits
+ARM GAS  /tmp/ccLD46hm.s 			page 8
+
+
+ 172              		.align	1
+ 173              		.syntax unified
+ 174              		.thumb
+ 175              		.thumb_func
+ 177              	AUDIO_GetState_FS:
+ 178              	.LFB339:
+ 241:Src/usbd_audio_if.c **** 
+ 242:Src/usbd_audio_if.c **** /**
+ 243:Src/usbd_audio_if.c ****   * @brief  Gets AUDIO State.
+ 244:Src/usbd_audio_if.c ****   * @retval USBD_OK if all operations are OK else USBD_FAIL
+ 245:Src/usbd_audio_if.c ****   */
+ 246:Src/usbd_audio_if.c **** static int8_t AUDIO_GetState_FS(void)
+ 247:Src/usbd_audio_if.c **** {
+ 179              		.loc 1 247 1 is_stmt 1 view -0
+ 180              		.cfi_startproc
+ 181              		@ args = 0, pretend = 0, frame = 0
+ 182              		@ frame_needed = 0, uses_anonymous_args = 0
+ 183              		@ link register save eliminated.
+ 248:Src/usbd_audio_if.c ****   /* USER CODE BEGIN 6 */
+ 249:Src/usbd_audio_if.c ****   return (USBD_OK);
+ 184              		.loc 1 249 3 view .LVU38
+ 250:Src/usbd_audio_if.c ****   /* USER CODE END 6 */
+ 251:Src/usbd_audio_if.c **** }
+ 185              		.loc 1 251 1 is_stmt 0 view .LVU39
+ 186 0000 0020     		movs	r0, #0
+ 187 0002 7047     		bx	lr
+ 188              		.cfi_endproc
+ 189              	.LFE339:
+ 191              		.section	.text.TransferComplete_CallBack_FS,"ax",%progbits
+ 192              		.align	1
+ 193              		.global	TransferComplete_CallBack_FS
+ 194              		.syntax unified
+ 195              		.thumb
+ 196              		.thumb_func
+ 198              	TransferComplete_CallBack_FS:
+ 199              	.LFB340:
+ 252:Src/usbd_audio_if.c **** 
+ 253:Src/usbd_audio_if.c **** /**
+ 254:Src/usbd_audio_if.c ****   * @brief  Manages the DMA full transfer complete event.
+ 255:Src/usbd_audio_if.c ****   * @retval None
+ 256:Src/usbd_audio_if.c ****   */
+ 257:Src/usbd_audio_if.c **** void TransferComplete_CallBack_FS(void)
+ 258:Src/usbd_audio_if.c **** {
+ 200              		.loc 1 258 1 is_stmt 1 view -0
+ 201              		.cfi_startproc
+ 202              		@ args = 0, pretend = 0, frame = 0
+ 203              		@ frame_needed = 0, uses_anonymous_args = 0
+ 204 0000 08B5     		push	{r3, lr}
+ 205              	.LCFI0:
+ 206              		.cfi_def_cfa_offset 8
+ 207              		.cfi_offset 3, -8
+ 208              		.cfi_offset 14, -4
+ 259:Src/usbd_audio_if.c ****   /* USER CODE BEGIN 7 */
+ 260:Src/usbd_audio_if.c ****   USBD_AUDIO_Sync(&hUsbDeviceFS, AUDIO_OFFSET_FULL);
+ 209              		.loc 1 260 3 view .LVU41
+ 210 0002 0221     		movs	r1, #2
+ 211 0004 0148     		ldr	r0, .L10
+ARM GAS  /tmp/ccLD46hm.s 			page 9
+
+
+ 212 0006 FFF7FEFF 		bl	USBD_AUDIO_Sync
+ 213              	.LVL12:
+ 261:Src/usbd_audio_if.c ****   /* USER CODE END 7 */
+ 262:Src/usbd_audio_if.c **** }
+ 214              		.loc 1 262 1 is_stmt 0 view .LVU42
+ 215 000a 08BD     		pop	{r3, pc}
+ 216              	.L11:
+ 217              		.align	2
+ 218              	.L10:
+ 219 000c 00000000 		.word	hUsbDeviceFS
+ 220              		.cfi_endproc
+ 221              	.LFE340:
+ 223              		.section	.text.HalfTransfer_CallBack_FS,"ax",%progbits
+ 224              		.align	1
+ 225              		.global	HalfTransfer_CallBack_FS
+ 226              		.syntax unified
+ 227              		.thumb
+ 228              		.thumb_func
+ 230              	HalfTransfer_CallBack_FS:
+ 231              	.LFB341:
+ 263:Src/usbd_audio_if.c **** 
+ 264:Src/usbd_audio_if.c **** /**
+ 265:Src/usbd_audio_if.c ****   * @brief  Manages the DMA Half transfer complete event.
+ 266:Src/usbd_audio_if.c ****   * @retval None
+ 267:Src/usbd_audio_if.c ****   */
+ 268:Src/usbd_audio_if.c **** void HalfTransfer_CallBack_FS(void)
+ 269:Src/usbd_audio_if.c **** {
+ 232              		.loc 1 269 1 is_stmt 1 view -0
+ 233              		.cfi_startproc
+ 234              		@ args = 0, pretend = 0, frame = 0
+ 235              		@ frame_needed = 0, uses_anonymous_args = 0
+ 236 0000 08B5     		push	{r3, lr}
+ 237              	.LCFI1:
+ 238              		.cfi_def_cfa_offset 8
+ 239              		.cfi_offset 3, -8
+ 240              		.cfi_offset 14, -4
+ 270:Src/usbd_audio_if.c ****   /* USER CODE BEGIN 8 */
+ 271:Src/usbd_audio_if.c ****   USBD_AUDIO_Sync(&hUsbDeviceFS, AUDIO_OFFSET_HALF);
+ 241              		.loc 1 271 3 view .LVU44
+ 242 0002 0121     		movs	r1, #1
+ 243 0004 0148     		ldr	r0, .L14
+ 244 0006 FFF7FEFF 		bl	USBD_AUDIO_Sync
+ 245              	.LVL13:
+ 272:Src/usbd_audio_if.c ****   /* USER CODE END 8 */
+ 273:Src/usbd_audio_if.c **** }
+ 246              		.loc 1 273 1 is_stmt 0 view .LVU45
+ 247 000a 08BD     		pop	{r3, pc}
+ 248              	.L15:
+ 249              		.align	2
+ 250              	.L14:
+ 251 000c 00000000 		.word	hUsbDeviceFS
+ 252              		.cfi_endproc
+ 253              	.LFE341:
+ 255              		.global	USBD_AUDIO_fops_FS
+ 256              		.section	.data.USBD_AUDIO_fops_FS,"aw"
+ 257              		.align	2
+ 260              	USBD_AUDIO_fops_FS:
+ARM GAS  /tmp/ccLD46hm.s 			page 10
+
+
+ 261 0000 00000000 		.word	AUDIO_Init_FS
+ 262 0004 00000000 		.word	AUDIO_DeInit_FS
+ 263 0008 00000000 		.word	AUDIO_AudioCmd_FS
+ 264 000c 00000000 		.word	AUDIO_VolumeCtl_FS
+ 265 0010 00000000 		.word	AUDIO_MuteCtl_FS
+ 266 0014 00000000 		.word	AUDIO_PeriodicTC_FS
+ 267 0018 00000000 		.word	AUDIO_GetState_FS
+ 268              		.text
+ 269              	.Letext0:
+ 270              		.file 2 "/usr/include/newlib/machine/_default_types.h"
+ 271              		.file 3 "/usr/include/newlib/sys/_stdint.h"
+ 272              		.file 4 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h"
+ 273              		.file 5 "Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h"
+ 274              		.file 6 "Inc/usbd_audio_if.h"
+ARM GAS  /tmp/ccLD46hm.s 			page 11
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 usbd_audio_if.c
+     /tmp/ccLD46hm.s:21     .text.AUDIO_Init_FS:00000000 $t
+     /tmp/ccLD46hm.s:26     .text.AUDIO_Init_FS:00000000 AUDIO_Init_FS
+     /tmp/ccLD46hm.s:47     .text.AUDIO_DeInit_FS:00000000 $t
+     /tmp/ccLD46hm.s:52     .text.AUDIO_DeInit_FS:00000000 AUDIO_DeInit_FS
+     /tmp/ccLD46hm.s:71     .text.AUDIO_AudioCmd_FS:00000000 $t
+     /tmp/ccLD46hm.s:76     .text.AUDIO_AudioCmd_FS:00000000 AUDIO_AudioCmd_FS
+     /tmp/ccLD46hm.s:98     .text.AUDIO_VolumeCtl_FS:00000000 $t
+     /tmp/ccLD46hm.s:103    .text.AUDIO_VolumeCtl_FS:00000000 AUDIO_VolumeCtl_FS
+     /tmp/ccLD46hm.s:122    .text.AUDIO_MuteCtl_FS:00000000 $t
+     /tmp/ccLD46hm.s:127    .text.AUDIO_MuteCtl_FS:00000000 AUDIO_MuteCtl_FS
+     /tmp/ccLD46hm.s:146    .text.AUDIO_PeriodicTC_FS:00000000 $t
+     /tmp/ccLD46hm.s:151    .text.AUDIO_PeriodicTC_FS:00000000 AUDIO_PeriodicTC_FS
+     /tmp/ccLD46hm.s:172    .text.AUDIO_GetState_FS:00000000 $t
+     /tmp/ccLD46hm.s:177    .text.AUDIO_GetState_FS:00000000 AUDIO_GetState_FS
+     /tmp/ccLD46hm.s:192    .text.TransferComplete_CallBack_FS:00000000 $t
+     /tmp/ccLD46hm.s:198    .text.TransferComplete_CallBack_FS:00000000 TransferComplete_CallBack_FS
+     /tmp/ccLD46hm.s:219    .text.TransferComplete_CallBack_FS:0000000c $d
+     /tmp/ccLD46hm.s:224    .text.HalfTransfer_CallBack_FS:00000000 $t
+     /tmp/ccLD46hm.s:230    .text.HalfTransfer_CallBack_FS:00000000 HalfTransfer_CallBack_FS
+     /tmp/ccLD46hm.s:251    .text.HalfTransfer_CallBack_FS:0000000c $d
+     /tmp/ccLD46hm.s:260    .data.USBD_AUDIO_fops_FS:00000000 USBD_AUDIO_fops_FS
+     /tmp/ccLD46hm.s:257    .data.USBD_AUDIO_fops_FS:00000000 $d
+
+UNDEFINED SYMBOLS
+USBD_AUDIO_Sync
+hUsbDeviceFS
diff --git a/squeow_sw/build/usbd_audio_if.o b/squeow_sw/build/usbd_audio_if.o
new file mode 100644
index 0000000000000000000000000000000000000000..de2986fedf07c58d12fe8cff964450aec59a2537
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/squeow_sw/build/usbd_conf.d b/squeow_sw/build/usbd_conf.d
new file mode 100644
index 0000000..58f153d
--- /dev/null
+++ b/squeow_sw/build/usbd_conf.d
@@ -0,0 +1,91 @@
+build/usbd_conf.o: Src/usbd_conf.c \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \
+ Inc/usbd_conf.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
+Inc/usbd_conf.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
diff --git a/squeow_sw/build/usbd_conf.lst b/squeow_sw/build/usbd_conf.lst
new file mode 100644
index 0000000..d04a847
--- /dev/null
+++ b/squeow_sw/build/usbd_conf.lst
@@ -0,0 +1,2810 @@
+ARM GAS  /tmp/ccf5FGie.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"usbd_conf.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Src/usbd_conf.c"
+  20              		.section	.text.USBD_Get_USB_Status,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	USBD_Get_USB_Status:
+  27              	.LVL0:
+  28              	.LFB365:
+   1:Src/usbd_conf.c **** /* USER CODE BEGIN Header */
+   2:Src/usbd_conf.c **** /**
+   3:Src/usbd_conf.c ****   ******************************************************************************
+   4:Src/usbd_conf.c ****   * @file           : usbd_conf.c
+   5:Src/usbd_conf.c ****   * @version        : v3.0_Cube
+   6:Src/usbd_conf.c ****   * @brief          : This file implements the board support package for the USB device library
+   7:Src/usbd_conf.c ****   ******************************************************************************
+   8:Src/usbd_conf.c ****   * @attention
+   9:Src/usbd_conf.c ****   *
+  10:Src/usbd_conf.c ****   * Copyright (c) 2022 STMicroelectronics.
+  11:Src/usbd_conf.c ****   * All rights reserved.
+  12:Src/usbd_conf.c ****   *
+  13:Src/usbd_conf.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  14:Src/usbd_conf.c ****   * in the root directory of this software component.
+  15:Src/usbd_conf.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  16:Src/usbd_conf.c ****   *
+  17:Src/usbd_conf.c ****   ******************************************************************************
+  18:Src/usbd_conf.c ****   */
+  19:Src/usbd_conf.c **** /* USER CODE END Header */
+  20:Src/usbd_conf.c **** 
+  21:Src/usbd_conf.c **** /* Includes ------------------------------------------------------------------*/
+  22:Src/usbd_conf.c **** #include "stm32g4xx.h"
+  23:Src/usbd_conf.c **** #include "stm32g4xx_hal.h"
+  24:Src/usbd_conf.c **** #include "usbd_def.h"
+  25:Src/usbd_conf.c **** #include "usbd_core.h"
+  26:Src/usbd_conf.c **** 
+  27:Src/usbd_conf.c **** #include "usbd_audio.h"
+  28:Src/usbd_conf.c **** 
+  29:Src/usbd_conf.c **** /* USER CODE BEGIN Includes */
+  30:Src/usbd_conf.c **** 
+ARM GAS  /tmp/ccf5FGie.s 			page 2
+
+
+  31:Src/usbd_conf.c **** /* USER CODE END Includes */
+  32:Src/usbd_conf.c **** 
+  33:Src/usbd_conf.c **** /* Private typedef -----------------------------------------------------------*/
+  34:Src/usbd_conf.c **** /* Private define ------------------------------------------------------------*/
+  35:Src/usbd_conf.c **** /* Private macro -------------------------------------------------------------*/
+  36:Src/usbd_conf.c **** 
+  37:Src/usbd_conf.c **** /* Private variables ---------------------------------------------------------*/
+  38:Src/usbd_conf.c **** /* USER CODE BEGIN PV */
+  39:Src/usbd_conf.c **** 
+  40:Src/usbd_conf.c **** /* USER CODE END PV */
+  41:Src/usbd_conf.c **** 
+  42:Src/usbd_conf.c **** PCD_HandleTypeDef hpcd_USB_FS;
+  43:Src/usbd_conf.c **** void Error_Handler(void);
+  44:Src/usbd_conf.c **** 
+  45:Src/usbd_conf.c **** /* USER CODE BEGIN 0 */
+  46:Src/usbd_conf.c **** 
+  47:Src/usbd_conf.c **** /* USER CODE END 0 */
+  48:Src/usbd_conf.c **** 
+  49:Src/usbd_conf.c **** /* Exported function prototypes ----------------------------------------------*/
+  50:Src/usbd_conf.c **** 
+  51:Src/usbd_conf.c **** /* USER CODE BEGIN PFP */
+  52:Src/usbd_conf.c **** /* Private function prototypes -----------------------------------------------*/
+  53:Src/usbd_conf.c **** 
+  54:Src/usbd_conf.c **** /* USER CODE END PFP */
+  55:Src/usbd_conf.c **** 
+  56:Src/usbd_conf.c **** /* Private functions ---------------------------------------------------------*/
+  57:Src/usbd_conf.c **** static USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status);
+  58:Src/usbd_conf.c **** /* USER CODE BEGIN 1 */
+  59:Src/usbd_conf.c **** static void SystemClockConfig_Resume(void);
+  60:Src/usbd_conf.c **** 
+  61:Src/usbd_conf.c **** /* USER CODE END 1 */
+  62:Src/usbd_conf.c **** extern void SystemClock_Config(void);
+  63:Src/usbd_conf.c **** 
+  64:Src/usbd_conf.c **** /*******************************************************************************
+  65:Src/usbd_conf.c ****                        LL Driver Callbacks (PCD -> USB Device Library)
+  66:Src/usbd_conf.c **** *******************************************************************************/
+  67:Src/usbd_conf.c **** /* MSP Init */
+  68:Src/usbd_conf.c **** 
+  69:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  70:Src/usbd_conf.c **** static void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
+  71:Src/usbd_conf.c **** #else
+  72:Src/usbd_conf.c **** void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
+  73:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  74:Src/usbd_conf.c **** {
+  75:Src/usbd_conf.c ****   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  76:Src/usbd_conf.c ****   if(pcdHandle->Instance==USB)
+  77:Src/usbd_conf.c ****   {
+  78:Src/usbd_conf.c ****   /* USER CODE BEGIN USB_MspInit 0 */
+  79:Src/usbd_conf.c **** 
+  80:Src/usbd_conf.c ****   /* USER CODE END USB_MspInit 0 */
+  81:Src/usbd_conf.c **** 
+  82:Src/usbd_conf.c ****   /** Initializes the peripherals clocks
+  83:Src/usbd_conf.c ****   */
+  84:Src/usbd_conf.c ****     PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  85:Src/usbd_conf.c ****     PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  86:Src/usbd_conf.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  87:Src/usbd_conf.c ****     {
+ARM GAS  /tmp/ccf5FGie.s 			page 3
+
+
+  88:Src/usbd_conf.c ****       Error_Handler();
+  89:Src/usbd_conf.c ****     }
+  90:Src/usbd_conf.c **** 
+  91:Src/usbd_conf.c ****     /* Peripheral clock enable */
+  92:Src/usbd_conf.c ****     __HAL_RCC_USB_CLK_ENABLE();
+  93:Src/usbd_conf.c **** 
+  94:Src/usbd_conf.c ****     /* Peripheral interrupt init */
+  95:Src/usbd_conf.c ****     HAL_NVIC_SetPriority(USB_LP_IRQn, 0, 0);
+  96:Src/usbd_conf.c ****     HAL_NVIC_EnableIRQ(USB_LP_IRQn);
+  97:Src/usbd_conf.c ****   /* USER CODE BEGIN USB_MspInit 1 */
+  98:Src/usbd_conf.c **** 
+  99:Src/usbd_conf.c ****   /* USER CODE END USB_MspInit 1 */
+ 100:Src/usbd_conf.c ****   }
+ 101:Src/usbd_conf.c **** }
+ 102:Src/usbd_conf.c **** 
+ 103:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 104:Src/usbd_conf.c **** static void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
+ 105:Src/usbd_conf.c **** #else
+ 106:Src/usbd_conf.c **** void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
+ 107:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 108:Src/usbd_conf.c **** {
+ 109:Src/usbd_conf.c ****   if(pcdHandle->Instance==USB)
+ 110:Src/usbd_conf.c ****   {
+ 111:Src/usbd_conf.c ****   /* USER CODE BEGIN USB_MspDeInit 0 */
+ 112:Src/usbd_conf.c **** 
+ 113:Src/usbd_conf.c ****   /* USER CODE END USB_MspDeInit 0 */
+ 114:Src/usbd_conf.c ****     /* Peripheral clock disable */
+ 115:Src/usbd_conf.c ****     __HAL_RCC_USB_CLK_DISABLE();
+ 116:Src/usbd_conf.c **** 
+ 117:Src/usbd_conf.c ****     /* Peripheral interrupt Deinit*/
+ 118:Src/usbd_conf.c ****     HAL_NVIC_DisableIRQ(USB_LP_IRQn);
+ 119:Src/usbd_conf.c **** 
+ 120:Src/usbd_conf.c ****   /* USER CODE BEGIN USB_MspDeInit 1 */
+ 121:Src/usbd_conf.c **** 
+ 122:Src/usbd_conf.c ****   /* USER CODE END USB_MspDeInit 1 */
+ 123:Src/usbd_conf.c ****   }
+ 124:Src/usbd_conf.c **** }
+ 125:Src/usbd_conf.c **** 
+ 126:Src/usbd_conf.c **** /**
+ 127:Src/usbd_conf.c ****   * @brief  Setup stage callback
+ 128:Src/usbd_conf.c ****   * @param  hpcd: PCD handle
+ 129:Src/usbd_conf.c ****   * @retval None
+ 130:Src/usbd_conf.c ****   */
+ 131:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 132:Src/usbd_conf.c **** static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+ 133:Src/usbd_conf.c **** #else
+ 134:Src/usbd_conf.c **** void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+ 135:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 136:Src/usbd_conf.c **** {
+ 137:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PreTreatment */
+ 138:Src/usbd_conf.c **** 
+ 139:Src/usbd_conf.c ****   /* USER CODE END  HAL_PCD_SetupStageCallback_PreTreatment */
+ 140:Src/usbd_conf.c ****   USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
+ 141:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PostTreatment */
+ 142:Src/usbd_conf.c **** 
+ 143:Src/usbd_conf.c ****   /* USER CODE END  HAL_PCD_SetupStageCallback_PostTreatment */
+ 144:Src/usbd_conf.c **** }
+ARM GAS  /tmp/ccf5FGie.s 			page 4
+
+
+ 145:Src/usbd_conf.c **** 
+ 146:Src/usbd_conf.c **** /**
+ 147:Src/usbd_conf.c ****   * @brief  Data Out stage callback.
+ 148:Src/usbd_conf.c ****   * @param  hpcd: PCD handle
+ 149:Src/usbd_conf.c ****   * @param  epnum: Endpoint number
+ 150:Src/usbd_conf.c ****   * @retval None
+ 151:Src/usbd_conf.c ****   */
+ 152:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 153:Src/usbd_conf.c **** static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+ 154:Src/usbd_conf.c **** #else
+ 155:Src/usbd_conf.c **** void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+ 156:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 157:Src/usbd_conf.c **** {
+ 158:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PreTreatment */
+ 159:Src/usbd_conf.c **** 
+ 160:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_DataOutStageCallback_PreTreatment */
+ 161:Src/usbd_conf.c ****   USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
+ 162:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PostTreatment */
+ 163:Src/usbd_conf.c **** 
+ 164:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_DataOutStageCallback_PostTreatment */
+ 165:Src/usbd_conf.c **** }
+ 166:Src/usbd_conf.c **** 
+ 167:Src/usbd_conf.c **** /**
+ 168:Src/usbd_conf.c ****   * @brief  Data In stage callback.
+ 169:Src/usbd_conf.c ****   * @param  hpcd: PCD handle
+ 170:Src/usbd_conf.c ****   * @param  epnum: Endpoint number
+ 171:Src/usbd_conf.c ****   * @retval None
+ 172:Src/usbd_conf.c ****   */
+ 173:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 174:Src/usbd_conf.c **** static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+ 175:Src/usbd_conf.c **** #else
+ 176:Src/usbd_conf.c **** void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+ 177:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 178:Src/usbd_conf.c **** {
+ 179:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PreTreatment */
+ 180:Src/usbd_conf.c **** 
+ 181:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_DataInStageCallback_PreTreatment */
+ 182:Src/usbd_conf.c ****   USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
+ 183:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PostTreatment  */
+ 184:Src/usbd_conf.c **** 
+ 185:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_DataInStageCallback_PostTreatment */
+ 186:Src/usbd_conf.c **** }
+ 187:Src/usbd_conf.c **** 
+ 188:Src/usbd_conf.c **** /**
+ 189:Src/usbd_conf.c ****   * @brief  SOF callback.
+ 190:Src/usbd_conf.c ****   * @param  hpcd: PCD handle
+ 191:Src/usbd_conf.c ****   * @retval None
+ 192:Src/usbd_conf.c ****   */
+ 193:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 194:Src/usbd_conf.c **** static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+ 195:Src/usbd_conf.c **** #else
+ 196:Src/usbd_conf.c **** void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+ 197:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 198:Src/usbd_conf.c **** {
+ 199:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SOFCallback_PreTreatment */
+ 200:Src/usbd_conf.c **** 
+ 201:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_SOFCallback_PreTreatment */
+ARM GAS  /tmp/ccf5FGie.s 			page 5
+
+
+ 202:Src/usbd_conf.c ****   USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
+ 203:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SOFCallback_PostTreatment */
+ 204:Src/usbd_conf.c **** 
+ 205:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_SOFCallback_PostTreatment */
+ 206:Src/usbd_conf.c **** }
+ 207:Src/usbd_conf.c **** 
+ 208:Src/usbd_conf.c **** /**
+ 209:Src/usbd_conf.c ****   * @brief  Reset callback.
+ 210:Src/usbd_conf.c ****   * @param  hpcd: PCD handle
+ 211:Src/usbd_conf.c ****   * @retval None
+ 212:Src/usbd_conf.c ****   */
+ 213:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 214:Src/usbd_conf.c **** static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+ 215:Src/usbd_conf.c **** #else
+ 216:Src/usbd_conf.c **** void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+ 217:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 218:Src/usbd_conf.c **** {
+ 219:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ResetCallback_PreTreatment */
+ 220:Src/usbd_conf.c **** 
+ 221:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_ResetCallback_PreTreatment */
+ 222:Src/usbd_conf.c ****   USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
+ 223:Src/usbd_conf.c **** 
+ 224:Src/usbd_conf.c ****   if ( hpcd->Init.speed != PCD_SPEED_FULL)
+ 225:Src/usbd_conf.c ****   {
+ 226:Src/usbd_conf.c ****     Error_Handler();
+ 227:Src/usbd_conf.c ****   }
+ 228:Src/usbd_conf.c ****     /* Set Speed. */
+ 229:Src/usbd_conf.c ****   USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
+ 230:Src/usbd_conf.c **** 
+ 231:Src/usbd_conf.c ****   /* Reset Device. */
+ 232:Src/usbd_conf.c ****   USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
+ 233:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ResetCallback_PostTreatment */
+ 234:Src/usbd_conf.c **** 
+ 235:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_ResetCallback_PostTreatment */
+ 236:Src/usbd_conf.c **** }
+ 237:Src/usbd_conf.c **** 
+ 238:Src/usbd_conf.c **** /**
+ 239:Src/usbd_conf.c ****   * @brief  Suspend callback.
+ 240:Src/usbd_conf.c ****   * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+ 241:Src/usbd_conf.c ****   * @param  hpcd: PCD handle
+ 242:Src/usbd_conf.c ****   * @retval None
+ 243:Src/usbd_conf.c ****   */
+ 244:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 245:Src/usbd_conf.c **** static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+ 246:Src/usbd_conf.c **** #else
+ 247:Src/usbd_conf.c **** void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+ 248:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 249:Src/usbd_conf.c **** {
+ 250:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SuspendCallback_PreTreatment */
+ 251:Src/usbd_conf.c **** 
+ 252:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_SuspendCallback_PreTreatment */
+ 253:Src/usbd_conf.c ****   /* Inform USB library that core enters in suspend Mode. */
+ 254:Src/usbd_conf.c ****   USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
+ 255:Src/usbd_conf.c ****   /* Enter in STOP mode. */
+ 256:Src/usbd_conf.c ****   /* USER CODE BEGIN 2 */
+ 257:Src/usbd_conf.c ****   if (hpcd->Init.low_power_enable)
+ 258:Src/usbd_conf.c ****   {
+ARM GAS  /tmp/ccf5FGie.s 			page 6
+
+
+ 259:Src/usbd_conf.c ****     /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
+ 260:Src/usbd_conf.c ****     SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+ 261:Src/usbd_conf.c ****   }
+ 262:Src/usbd_conf.c ****   /* USER CODE END 2 */
+ 263:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SuspendCallback_PostTreatment */
+ 264:Src/usbd_conf.c **** 
+ 265:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_SuspendCallback_PostTreatment */
+ 266:Src/usbd_conf.c **** }
+ 267:Src/usbd_conf.c **** 
+ 268:Src/usbd_conf.c **** /**
+ 269:Src/usbd_conf.c ****   * @brief  Resume callback.
+ 270:Src/usbd_conf.c ****   * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+ 271:Src/usbd_conf.c ****   * @param  hpcd: PCD handle
+ 272:Src/usbd_conf.c ****   * @retval None
+ 273:Src/usbd_conf.c ****   */
+ 274:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 275:Src/usbd_conf.c **** static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+ 276:Src/usbd_conf.c **** #else
+ 277:Src/usbd_conf.c **** void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+ 278:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 279:Src/usbd_conf.c **** {
+ 280:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ResumeCallback_PreTreatment */
+ 281:Src/usbd_conf.c **** 
+ 282:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_ResumeCallback_PreTreatment */
+ 283:Src/usbd_conf.c **** 
+ 284:Src/usbd_conf.c ****   /* USER CODE BEGIN 3 */
+ 285:Src/usbd_conf.c ****   if (hpcd->Init.low_power_enable)
+ 286:Src/usbd_conf.c ****   {
+ 287:Src/usbd_conf.c ****     /* Reset SLEEPDEEP bit of Cortex System Control Register. */
+ 288:Src/usbd_conf.c ****     SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+ 289:Src/usbd_conf.c ****     SystemClockConfig_Resume();
+ 290:Src/usbd_conf.c ****   }
+ 291:Src/usbd_conf.c ****   /* USER CODE END 3 */
+ 292:Src/usbd_conf.c **** 
+ 293:Src/usbd_conf.c ****   USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
+ 294:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ResumeCallback_PostTreatment */
+ 295:Src/usbd_conf.c **** 
+ 296:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_ResumeCallback_PostTreatment */
+ 297:Src/usbd_conf.c **** }
+ 298:Src/usbd_conf.c **** 
+ 299:Src/usbd_conf.c **** /**
+ 300:Src/usbd_conf.c ****   * @brief  ISOOUTIncomplete callback.
+ 301:Src/usbd_conf.c ****   * @param  hpcd: PCD handle
+ 302:Src/usbd_conf.c ****   * @param  epnum: Endpoint number
+ 303:Src/usbd_conf.c ****   * @retval None
+ 304:Src/usbd_conf.c ****   */
+ 305:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 306:Src/usbd_conf.c **** static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+ 307:Src/usbd_conf.c **** #else
+ 308:Src/usbd_conf.c **** void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+ 309:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 310:Src/usbd_conf.c **** {
+ 311:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ISOOUTIncompleteCallback_PreTreatment */
+ 312:Src/usbd_conf.c **** 
+ 313:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_ISOOUTIncompleteCallback_PreTreatment */
+ 314:Src/usbd_conf.c ****   USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+ 315:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ISOOUTIncompleteCallback_PostTreatment */
+ARM GAS  /tmp/ccf5FGie.s 			page 7
+
+
+ 316:Src/usbd_conf.c **** 
+ 317:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_ISOOUTIncompleteCallback_PostTreatment */
+ 318:Src/usbd_conf.c **** }
+ 319:Src/usbd_conf.c **** 
+ 320:Src/usbd_conf.c **** /**
+ 321:Src/usbd_conf.c ****   * @brief  ISOINIncomplete callback.
+ 322:Src/usbd_conf.c ****   * @param  hpcd: PCD handle
+ 323:Src/usbd_conf.c ****   * @param  epnum: Endpoint number
+ 324:Src/usbd_conf.c ****   * @retval None
+ 325:Src/usbd_conf.c ****   */
+ 326:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 327:Src/usbd_conf.c **** static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+ 328:Src/usbd_conf.c **** #else
+ 329:Src/usbd_conf.c **** void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+ 330:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 331:Src/usbd_conf.c **** {
+ 332:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ISOINIncompleteCallback_PreTreatment */
+ 333:Src/usbd_conf.c **** 
+ 334:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_ISOINIncompleteCallback_PreTreatment */
+ 335:Src/usbd_conf.c ****   USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+ 336:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ISOINIncompleteCallback_PostTreatment */
+ 337:Src/usbd_conf.c **** 
+ 338:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_ISOINIncompleteCallback_PostTreatment */
+ 339:Src/usbd_conf.c **** }
+ 340:Src/usbd_conf.c **** 
+ 341:Src/usbd_conf.c **** /**
+ 342:Src/usbd_conf.c ****   * @brief  Connect callback.
+ 343:Src/usbd_conf.c ****   * @param  hpcd: PCD handle
+ 344:Src/usbd_conf.c ****   * @retval None
+ 345:Src/usbd_conf.c ****   */
+ 346:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 347:Src/usbd_conf.c **** static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+ 348:Src/usbd_conf.c **** #else
+ 349:Src/usbd_conf.c **** void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+ 350:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 351:Src/usbd_conf.c **** {
+ 352:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ConnectCallback_PreTreatment */
+ 353:Src/usbd_conf.c **** 
+ 354:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_ConnectCallback_PreTreatment */
+ 355:Src/usbd_conf.c ****   USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
+ 356:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ConnectCallback_PostTreatment */
+ 357:Src/usbd_conf.c **** 
+ 358:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_ConnectCallback_PostTreatment */
+ 359:Src/usbd_conf.c **** }
+ 360:Src/usbd_conf.c **** 
+ 361:Src/usbd_conf.c **** /**
+ 362:Src/usbd_conf.c ****   * @brief  Disconnect callback.
+ 363:Src/usbd_conf.c ****   * @param  hpcd: PCD handle
+ 364:Src/usbd_conf.c ****   * @retval None
+ 365:Src/usbd_conf.c ****   */
+ 366:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 367:Src/usbd_conf.c **** static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+ 368:Src/usbd_conf.c **** #else
+ 369:Src/usbd_conf.c **** void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+ 370:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 371:Src/usbd_conf.c **** {
+ 372:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DisconnectCallback_PreTreatment */
+ARM GAS  /tmp/ccf5FGie.s 			page 8
+
+
+ 373:Src/usbd_conf.c **** 
+ 374:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_DisconnectCallback_PreTreatment */
+ 375:Src/usbd_conf.c ****   USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
+ 376:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DisconnectCallback_PostTreatment */
+ 377:Src/usbd_conf.c **** 
+ 378:Src/usbd_conf.c ****   /* USER CODE END HAL_PCD_DisconnectCallback_PostTreatment */
+ 379:Src/usbd_conf.c **** }
+ 380:Src/usbd_conf.c **** 
+ 381:Src/usbd_conf.c ****   /* USER CODE BEGIN LowLevelInterface */
+ 382:Src/usbd_conf.c **** 
+ 383:Src/usbd_conf.c ****   /* USER CODE END LowLevelInterface */
+ 384:Src/usbd_conf.c **** 
+ 385:Src/usbd_conf.c **** /*******************************************************************************
+ 386:Src/usbd_conf.c ****                        LL Driver Interface (USB Device Library --> PCD)
+ 387:Src/usbd_conf.c **** *******************************************************************************/
+ 388:Src/usbd_conf.c **** 
+ 389:Src/usbd_conf.c **** /**
+ 390:Src/usbd_conf.c ****   * @brief  Initializes the low level portion of the device driver.
+ 391:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 392:Src/usbd_conf.c ****   * @retval USBD status
+ 393:Src/usbd_conf.c ****   */
+ 394:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
+ 395:Src/usbd_conf.c **** {
+ 396:Src/usbd_conf.c ****   /* Init USB Ip. */
+ 397:Src/usbd_conf.c ****   hpcd_USB_FS.pData = pdev;
+ 398:Src/usbd_conf.c ****   /* Link the driver to the stack. */
+ 399:Src/usbd_conf.c ****   pdev->pData = &hpcd_USB_FS;
+ 400:Src/usbd_conf.c **** 
+ 401:Src/usbd_conf.c ****   hpcd_USB_FS.Instance = USB;
+ 402:Src/usbd_conf.c ****   hpcd_USB_FS.Init.dev_endpoints = 8;
+ 403:Src/usbd_conf.c ****   hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
+ 404:Src/usbd_conf.c ****   hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
+ 405:Src/usbd_conf.c ****   hpcd_USB_FS.Init.Sof_enable = DISABLE;
+ 406:Src/usbd_conf.c ****   hpcd_USB_FS.Init.low_power_enable = DISABLE;
+ 407:Src/usbd_conf.c ****   hpcd_USB_FS.Init.lpm_enable = DISABLE;
+ 408:Src/usbd_conf.c ****   hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
+ 409:Src/usbd_conf.c **** 
+ 410:Src/usbd_conf.c ****   #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 411:Src/usbd_conf.c ****   /* register Msp Callbacks (before the Init) */
+ 412:Src/usbd_conf.c ****   HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPINIT_CB_ID, PCD_MspInit);
+ 413:Src/usbd_conf.c ****   HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPDEINIT_CB_ID, PCD_MspDeInit);
+ 414:Src/usbd_conf.c ****   #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 415:Src/usbd_conf.c **** 
+ 416:Src/usbd_conf.c ****   if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
+ 417:Src/usbd_conf.c ****   {
+ 418:Src/usbd_conf.c ****     Error_Handler( );
+ 419:Src/usbd_conf.c ****   }
+ 420:Src/usbd_conf.c **** 
+ 421:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 422:Src/usbd_conf.c ****   /* Register USB PCD CallBacks */
+ 423:Src/usbd_conf.c ****   HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback);
+ 424:Src/usbd_conf.c ****   HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback);
+ 425:Src/usbd_conf.c ****   HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback);
+ 426:Src/usbd_conf.c ****   HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback);
+ 427:Src/usbd_conf.c ****   HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback);
+ 428:Src/usbd_conf.c ****   HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback);
+ 429:Src/usbd_conf.c ****   HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback);
+ARM GAS  /tmp/ccf5FGie.s 			page 9
+
+
+ 430:Src/usbd_conf.c ****   /* USER CODE BEGIN RegisterCallBackFirstPart */
+ 431:Src/usbd_conf.c **** 
+ 432:Src/usbd_conf.c ****   /* USER CODE END RegisterCallBackFirstPart */
+ 433:Src/usbd_conf.c ****   HAL_PCD_RegisterLpmCallback(&hpcd_USB_FS, PCDEx_LPM_Callback);
+ 434:Src/usbd_conf.c ****   HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_FS, PCD_DataOutStageCallback);
+ 435:Src/usbd_conf.c ****   HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback);
+ 436:Src/usbd_conf.c ****   HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback);
+ 437:Src/usbd_conf.c ****   HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback);
+ 438:Src/usbd_conf.c ****   /* USER CODE BEGIN RegisterCallBackSecondPart */
+ 439:Src/usbd_conf.c **** 
+ 440:Src/usbd_conf.c ****   /* USER CODE END RegisterCallBackSecondPart */
+ 441:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 442:Src/usbd_conf.c ****   /* USER CODE BEGIN EndPoint_Configuration */
+ 443:Src/usbd_conf.c ****   HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, 0x00, PCD_SNG_BUF, 0x10);
+ 444:Src/usbd_conf.c ****   HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, 0x80, PCD_SNG_BUF, 0x50);
+ 445:Src/usbd_conf.c ****   /* USER CODE END EndPoint_Configuration */
+ 446:Src/usbd_conf.c ****   /* USER CODE BEGIN EndPoint_Configuration_AUDIO */
+ 447:Src/usbd_conf.c ****   HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, AUDIO_OUT_EP, PCD_DBL_BUF, 0x01500090);
+ 448:Src/usbd_conf.c ****   /* USER CODE END EndPoint_Configuration_AUDIO */
+ 449:Src/usbd_conf.c ****   return USBD_OK;
+ 450:Src/usbd_conf.c **** }
+ 451:Src/usbd_conf.c **** 
+ 452:Src/usbd_conf.c **** /**
+ 453:Src/usbd_conf.c ****   * @brief  De-Initializes the low level portion of the device driver.
+ 454:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 455:Src/usbd_conf.c ****   * @retval USBD status
+ 456:Src/usbd_conf.c ****   */
+ 457:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
+ 458:Src/usbd_conf.c **** {
+ 459:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 460:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 461:Src/usbd_conf.c **** 
+ 462:Src/usbd_conf.c ****   hal_status = HAL_PCD_DeInit(pdev->pData);
+ 463:Src/usbd_conf.c **** 
+ 464:Src/usbd_conf.c ****   usb_status =  USBD_Get_USB_Status(hal_status);
+ 465:Src/usbd_conf.c **** 
+ 466:Src/usbd_conf.c ****   return usb_status;
+ 467:Src/usbd_conf.c **** }
+ 468:Src/usbd_conf.c **** 
+ 469:Src/usbd_conf.c **** /**
+ 470:Src/usbd_conf.c ****   * @brief  Starts the low level portion of the device driver.
+ 471:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 472:Src/usbd_conf.c ****   * @retval USBD status
+ 473:Src/usbd_conf.c ****   */
+ 474:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
+ 475:Src/usbd_conf.c **** {
+ 476:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 477:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 478:Src/usbd_conf.c **** 
+ 479:Src/usbd_conf.c ****   hal_status = HAL_PCD_Start(pdev->pData);
+ 480:Src/usbd_conf.c **** 
+ 481:Src/usbd_conf.c ****   usb_status =  USBD_Get_USB_Status(hal_status);
+ 482:Src/usbd_conf.c **** 
+ 483:Src/usbd_conf.c ****   return usb_status;
+ 484:Src/usbd_conf.c **** }
+ 485:Src/usbd_conf.c **** 
+ 486:Src/usbd_conf.c **** /**
+ARM GAS  /tmp/ccf5FGie.s 			page 10
+
+
+ 487:Src/usbd_conf.c ****   * @brief  Stops the low level portion of the device driver.
+ 488:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 489:Src/usbd_conf.c ****   * @retval USBD status
+ 490:Src/usbd_conf.c ****   */
+ 491:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
+ 492:Src/usbd_conf.c **** {
+ 493:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 494:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 495:Src/usbd_conf.c **** 
+ 496:Src/usbd_conf.c ****   hal_status = HAL_PCD_Stop(pdev->pData);
+ 497:Src/usbd_conf.c **** 
+ 498:Src/usbd_conf.c ****   usb_status =  USBD_Get_USB_Status(hal_status);
+ 499:Src/usbd_conf.c **** 
+ 500:Src/usbd_conf.c ****   return usb_status;
+ 501:Src/usbd_conf.c **** }
+ 502:Src/usbd_conf.c **** 
+ 503:Src/usbd_conf.c **** /**
+ 504:Src/usbd_conf.c ****   * @brief  Opens an endpoint of the low level driver.
+ 505:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 506:Src/usbd_conf.c ****   * @param  ep_addr: Endpoint number
+ 507:Src/usbd_conf.c ****   * @param  ep_type: Endpoint type
+ 508:Src/usbd_conf.c ****   * @param  ep_mps: Endpoint max packet size
+ 509:Src/usbd_conf.c ****   * @retval USBD status
+ 510:Src/usbd_conf.c ****   */
+ 511:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint1
+ 512:Src/usbd_conf.c **** {
+ 513:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 514:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 515:Src/usbd_conf.c **** 
+ 516:Src/usbd_conf.c ****   hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
+ 517:Src/usbd_conf.c **** 
+ 518:Src/usbd_conf.c ****   usb_status =  USBD_Get_USB_Status(hal_status);
+ 519:Src/usbd_conf.c **** 
+ 520:Src/usbd_conf.c ****   return usb_status;
+ 521:Src/usbd_conf.c **** }
+ 522:Src/usbd_conf.c **** 
+ 523:Src/usbd_conf.c **** /**
+ 524:Src/usbd_conf.c ****   * @brief  Closes an endpoint of the low level driver.
+ 525:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 526:Src/usbd_conf.c ****   * @param  ep_addr: Endpoint number
+ 527:Src/usbd_conf.c ****   * @retval USBD status
+ 528:Src/usbd_conf.c ****   */
+ 529:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+ 530:Src/usbd_conf.c **** {
+ 531:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 532:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 533:Src/usbd_conf.c **** 
+ 534:Src/usbd_conf.c ****   hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
+ 535:Src/usbd_conf.c **** 
+ 536:Src/usbd_conf.c ****   usb_status =  USBD_Get_USB_Status(hal_status);
+ 537:Src/usbd_conf.c **** 
+ 538:Src/usbd_conf.c ****   return usb_status;
+ 539:Src/usbd_conf.c **** }
+ 540:Src/usbd_conf.c **** 
+ 541:Src/usbd_conf.c **** /**
+ 542:Src/usbd_conf.c ****   * @brief  Flushes an endpoint of the Low Level Driver.
+ 543:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ARM GAS  /tmp/ccf5FGie.s 			page 11
+
+
+ 544:Src/usbd_conf.c ****   * @param  ep_addr: Endpoint number
+ 545:Src/usbd_conf.c ****   * @retval USBD status
+ 546:Src/usbd_conf.c ****   */
+ 547:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+ 548:Src/usbd_conf.c **** {
+ 549:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 550:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 551:Src/usbd_conf.c **** 
+ 552:Src/usbd_conf.c ****   hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr);
+ 553:Src/usbd_conf.c **** 
+ 554:Src/usbd_conf.c ****   usb_status =  USBD_Get_USB_Status(hal_status);
+ 555:Src/usbd_conf.c **** 
+ 556:Src/usbd_conf.c ****   return usb_status;
+ 557:Src/usbd_conf.c **** }
+ 558:Src/usbd_conf.c **** 
+ 559:Src/usbd_conf.c **** /**
+ 560:Src/usbd_conf.c ****   * @brief  Sets a Stall condition on an endpoint of the Low Level Driver.
+ 561:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 562:Src/usbd_conf.c ****   * @param  ep_addr: Endpoint number
+ 563:Src/usbd_conf.c ****   * @retval USBD status
+ 564:Src/usbd_conf.c ****   */
+ 565:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+ 566:Src/usbd_conf.c **** {
+ 567:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 568:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 569:Src/usbd_conf.c **** 
+ 570:Src/usbd_conf.c ****   hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
+ 571:Src/usbd_conf.c **** 
+ 572:Src/usbd_conf.c ****   usb_status =  USBD_Get_USB_Status(hal_status);
+ 573:Src/usbd_conf.c **** 
+ 574:Src/usbd_conf.c ****   return usb_status;
+ 575:Src/usbd_conf.c **** }
+ 576:Src/usbd_conf.c **** 
+ 577:Src/usbd_conf.c **** /**
+ 578:Src/usbd_conf.c ****   * @brief  Clears a Stall condition on an endpoint of the Low Level Driver.
+ 579:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 580:Src/usbd_conf.c ****   * @param  ep_addr: Endpoint number
+ 581:Src/usbd_conf.c ****   * @retval USBD status
+ 582:Src/usbd_conf.c ****   */
+ 583:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+ 584:Src/usbd_conf.c **** {
+ 585:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 586:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 587:Src/usbd_conf.c **** 
+ 588:Src/usbd_conf.c ****   hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
+ 589:Src/usbd_conf.c **** 
+ 590:Src/usbd_conf.c ****   usb_status =  USBD_Get_USB_Status(hal_status);
+ 591:Src/usbd_conf.c **** 
+ 592:Src/usbd_conf.c ****   return usb_status;
+ 593:Src/usbd_conf.c **** }
+ 594:Src/usbd_conf.c **** 
+ 595:Src/usbd_conf.c **** /**
+ 596:Src/usbd_conf.c ****   * @brief  Returns Stall condition.
+ 597:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 598:Src/usbd_conf.c ****   * @param  ep_addr: Endpoint number
+ 599:Src/usbd_conf.c ****   * @retval Stall (1: Yes, 0: No)
+ 600:Src/usbd_conf.c ****   */
+ARM GAS  /tmp/ccf5FGie.s 			page 12
+
+
+ 601:Src/usbd_conf.c **** uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+ 602:Src/usbd_conf.c **** {
+ 603:Src/usbd_conf.c ****   PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
+ 604:Src/usbd_conf.c **** 
+ 605:Src/usbd_conf.c ****   if((ep_addr & 0x80) == 0x80)
+ 606:Src/usbd_conf.c ****   {
+ 607:Src/usbd_conf.c ****     return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
+ 608:Src/usbd_conf.c ****   }
+ 609:Src/usbd_conf.c ****   else
+ 610:Src/usbd_conf.c ****   {
+ 611:Src/usbd_conf.c ****     return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
+ 612:Src/usbd_conf.c ****   }
+ 613:Src/usbd_conf.c **** }
+ 614:Src/usbd_conf.c **** 
+ 615:Src/usbd_conf.c **** /**
+ 616:Src/usbd_conf.c ****   * @brief  Assigns a USB address to the device.
+ 617:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 618:Src/usbd_conf.c ****   * @param  dev_addr: Device address
+ 619:Src/usbd_conf.c ****   * @retval USBD status
+ 620:Src/usbd_conf.c ****   */
+ 621:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
+ 622:Src/usbd_conf.c **** {
+ 623:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 624:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 625:Src/usbd_conf.c **** 
+ 626:Src/usbd_conf.c ****   hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
+ 627:Src/usbd_conf.c **** 
+ 628:Src/usbd_conf.c ****   usb_status =  USBD_Get_USB_Status(hal_status);
+ 629:Src/usbd_conf.c **** 
+ 630:Src/usbd_conf.c ****   return usb_status;
+ 631:Src/usbd_conf.c **** }
+ 632:Src/usbd_conf.c **** 
+ 633:Src/usbd_conf.c **** /**
+ 634:Src/usbd_conf.c ****   * @brief  Transmits data over an endpoint.
+ 635:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 636:Src/usbd_conf.c ****   * @param  ep_addr: Endpoint number
+ 637:Src/usbd_conf.c ****   * @param  pbuf: Pointer to data to be sent
+ 638:Src/usbd_conf.c ****   * @param  size: Data size
+ 639:Src/usbd_conf.c ****   * @retval USBD status
+ 640:Src/usbd_conf.c ****   */
+ 641:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint3
+ 642:Src/usbd_conf.c **** {
+ 643:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 644:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 645:Src/usbd_conf.c **** 
+ 646:Src/usbd_conf.c ****   hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
+ 647:Src/usbd_conf.c **** 
+ 648:Src/usbd_conf.c ****   usb_status =  USBD_Get_USB_Status(hal_status);
+ 649:Src/usbd_conf.c **** 
+ 650:Src/usbd_conf.c ****   return usb_status;
+ 651:Src/usbd_conf.c **** }
+ 652:Src/usbd_conf.c **** 
+ 653:Src/usbd_conf.c **** /**
+ 654:Src/usbd_conf.c ****   * @brief  Prepares an endpoint for reception.
+ 655:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 656:Src/usbd_conf.c ****   * @param  ep_addr: Endpoint number
+ 657:Src/usbd_conf.c ****   * @param  pbuf: Pointer to data to be received
+ARM GAS  /tmp/ccf5FGie.s 			page 13
+
+
+ 658:Src/usbd_conf.c ****   * @param  size: Data size
+ 659:Src/usbd_conf.c ****   * @retval USBD status
+ 660:Src/usbd_conf.c ****   */
+ 661:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf,
+ 662:Src/usbd_conf.c **** {
+ 663:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 664:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 665:Src/usbd_conf.c **** 
+ 666:Src/usbd_conf.c ****   hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
+ 667:Src/usbd_conf.c **** 
+ 668:Src/usbd_conf.c ****   usb_status =  USBD_Get_USB_Status(hal_status);
+ 669:Src/usbd_conf.c **** 
+ 670:Src/usbd_conf.c ****   return usb_status;
+ 671:Src/usbd_conf.c **** }
+ 672:Src/usbd_conf.c **** 
+ 673:Src/usbd_conf.c **** /**
+ 674:Src/usbd_conf.c ****   * @brief  Returns the last transferred packet size.
+ 675:Src/usbd_conf.c ****   * @param  pdev: Device handle
+ 676:Src/usbd_conf.c ****   * @param  ep_addr: Endpoint number
+ 677:Src/usbd_conf.c ****   * @retval Received Data Size
+ 678:Src/usbd_conf.c ****   */
+ 679:Src/usbd_conf.c **** uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+ 680:Src/usbd_conf.c **** {
+ 681:Src/usbd_conf.c ****   return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
+ 682:Src/usbd_conf.c **** }
+ 683:Src/usbd_conf.c **** 
+ 684:Src/usbd_conf.c **** /**
+ 685:Src/usbd_conf.c ****   * @brief  Send LPM message to user layer
+ 686:Src/usbd_conf.c ****   * @param  hpcd: PCD handle
+ 687:Src/usbd_conf.c ****   * @param  msg: LPM message
+ 688:Src/usbd_conf.c ****   * @retval None
+ 689:Src/usbd_conf.c ****   */
+ 690:Src/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ 691:Src/usbd_conf.c **** static void PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+ 692:Src/usbd_conf.c **** #else
+ 693:Src/usbd_conf.c **** void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+ 694:Src/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ 695:Src/usbd_conf.c **** {
+ 696:Src/usbd_conf.c ****   /* USER CODE BEGIN LPM_Callback */
+ 697:Src/usbd_conf.c ****   switch (msg)
+ 698:Src/usbd_conf.c ****   {
+ 699:Src/usbd_conf.c ****   case PCD_LPM_L0_ACTIVE:
+ 700:Src/usbd_conf.c ****     if (hpcd->Init.low_power_enable)
+ 701:Src/usbd_conf.c ****     {
+ 702:Src/usbd_conf.c ****       SystemClockConfig_Resume();
+ 703:Src/usbd_conf.c **** 
+ 704:Src/usbd_conf.c ****       /* Reset SLEEPDEEP bit of Cortex System Control Register. */
+ 705:Src/usbd_conf.c ****       SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+ 706:Src/usbd_conf.c ****     }
+ 707:Src/usbd_conf.c ****     USBD_LL_Resume(hpcd->pData);
+ 708:Src/usbd_conf.c ****     break;
+ 709:Src/usbd_conf.c **** 
+ 710:Src/usbd_conf.c ****   case PCD_LPM_L1_ACTIVE:
+ 711:Src/usbd_conf.c ****     USBD_LL_Suspend(hpcd->pData);
+ 712:Src/usbd_conf.c **** 
+ 713:Src/usbd_conf.c ****     /* Enter in STOP mode. */
+ 714:Src/usbd_conf.c ****     if (hpcd->Init.low_power_enable)
+ARM GAS  /tmp/ccf5FGie.s 			page 14
+
+
+ 715:Src/usbd_conf.c ****     {
+ 716:Src/usbd_conf.c ****       /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
+ 717:Src/usbd_conf.c ****       SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+ 718:Src/usbd_conf.c ****     }
+ 719:Src/usbd_conf.c ****     break;
+ 720:Src/usbd_conf.c ****   }
+ 721:Src/usbd_conf.c ****   /* USER CODE END LPM_Callback */
+ 722:Src/usbd_conf.c **** }
+ 723:Src/usbd_conf.c **** 
+ 724:Src/usbd_conf.c **** /**
+ 725:Src/usbd_conf.c ****   * @brief  Delays routine for the USB Device Library.
+ 726:Src/usbd_conf.c ****   * @param  Delay: Delay in ms
+ 727:Src/usbd_conf.c ****   * @retval None
+ 728:Src/usbd_conf.c ****   */
+ 729:Src/usbd_conf.c **** void USBD_LL_Delay(uint32_t Delay)
+ 730:Src/usbd_conf.c **** {
+ 731:Src/usbd_conf.c ****   HAL_Delay(Delay);
+ 732:Src/usbd_conf.c **** }
+ 733:Src/usbd_conf.c **** 
+ 734:Src/usbd_conf.c **** /**
+ 735:Src/usbd_conf.c ****   * @brief  Static single allocation.
+ 736:Src/usbd_conf.c ****   * @param  size: Size of allocated memory
+ 737:Src/usbd_conf.c ****   * @retval None
+ 738:Src/usbd_conf.c ****   */
+ 739:Src/usbd_conf.c **** void *USBD_static_malloc(uint32_t size)
+ 740:Src/usbd_conf.c **** {
+ 741:Src/usbd_conf.c ****   static uint32_t mem[(sizeof(USBD_AUDIO_HandleTypeDef)/4)+1];/* On 32-bit boundary */
+ 742:Src/usbd_conf.c ****   return mem;
+ 743:Src/usbd_conf.c **** }
+ 744:Src/usbd_conf.c **** 
+ 745:Src/usbd_conf.c **** /**
+ 746:Src/usbd_conf.c ****   * @brief  Dummy memory free
+ 747:Src/usbd_conf.c ****   * @param  p: Pointer to allocated  memory address
+ 748:Src/usbd_conf.c ****   * @retval None
+ 749:Src/usbd_conf.c ****   */
+ 750:Src/usbd_conf.c **** void USBD_static_free(void *p)
+ 751:Src/usbd_conf.c **** {
+ 752:Src/usbd_conf.c **** 
+ 753:Src/usbd_conf.c **** }
+ 754:Src/usbd_conf.c **** 
+ 755:Src/usbd_conf.c **** /* USER CODE BEGIN 5 */
+ 756:Src/usbd_conf.c **** /**
+ 757:Src/usbd_conf.c ****   * @brief  Configures system clock after wake-up from USB resume callBack:
+ 758:Src/usbd_conf.c ****   *         enable HSI, PLL and select PLL as system clock source.
+ 759:Src/usbd_conf.c ****   * @retval None
+ 760:Src/usbd_conf.c ****   */
+ 761:Src/usbd_conf.c **** static void SystemClockConfig_Resume(void)
+ 762:Src/usbd_conf.c **** {
+ 763:Src/usbd_conf.c ****   SystemClock_Config();
+ 764:Src/usbd_conf.c **** }
+ 765:Src/usbd_conf.c **** /* USER CODE END 5 */
+ 766:Src/usbd_conf.c **** 
+ 767:Src/usbd_conf.c **** /**
+ 768:Src/usbd_conf.c ****   * @brief  Returns the USB status depending on the HAL status:
+ 769:Src/usbd_conf.c ****   * @param  hal_status: HAL status
+ 770:Src/usbd_conf.c ****   * @retval USB status
+ 771:Src/usbd_conf.c ****   */
+ARM GAS  /tmp/ccf5FGie.s 			page 15
+
+
+ 772:Src/usbd_conf.c **** USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
+ 773:Src/usbd_conf.c **** {
+  29              		.loc 1 773 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+ 774:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+  34              		.loc 1 774 3 view .LVU1
+ 775:Src/usbd_conf.c **** 
+ 776:Src/usbd_conf.c ****   switch (hal_status)
+  35              		.loc 1 776 3 view .LVU2
+  36 0000 0328     		cmp	r0, #3
+  37 0002 05D8     		bhi	.L7
+  38 0004 DFE800F0 		tbb	[pc, r0]
+  39              	.L4:
+  40 0008 05       		.byte	(.L2-.L4)/2
+  41 0009 04       		.byte	(.L7-.L4)/2
+  42 000a 02       		.byte	(.L5-.L4)/2
+  43 000b 05       		.byte	(.L2-.L4)/2
+  44              		.p2align 1
+  45              	.L5:
+ 777:Src/usbd_conf.c ****   {
+ 778:Src/usbd_conf.c ****     case HAL_OK :
+ 779:Src/usbd_conf.c ****       usb_status = USBD_OK;
+ 780:Src/usbd_conf.c ****     break;
+ 781:Src/usbd_conf.c ****     case HAL_ERROR :
+ 782:Src/usbd_conf.c ****       usb_status = USBD_FAIL;
+ 783:Src/usbd_conf.c ****     break;
+ 784:Src/usbd_conf.c ****     case HAL_BUSY :
+ 785:Src/usbd_conf.c ****       usb_status = USBD_BUSY;
+  46              		.loc 1 785 7 view .LVU3
+  47              	.LVL1:
+ 786:Src/usbd_conf.c ****     break;
+  48              		.loc 1 786 5 view .LVU4
+ 785:Src/usbd_conf.c ****     break;
+  49              		.loc 1 785 18 is_stmt 0 view .LVU5
+  50 000c 0120     		movs	r0, #1
+  51              	.LVL2:
+  52              		.loc 1 786 5 view .LVU6
+  53 000e 7047     		bx	lr
+  54              	.LVL3:
+  55              	.L7:
+ 782:Src/usbd_conf.c ****     break;
+  56              		.loc 1 782 18 view .LVU7
+  57 0010 0320     		movs	r0, #3
+  58              	.LVL4:
+  59              	.L2:
+ 787:Src/usbd_conf.c ****     case HAL_TIMEOUT :
+ 788:Src/usbd_conf.c ****       usb_status = USBD_FAIL;
+ 789:Src/usbd_conf.c ****     break;
+ 790:Src/usbd_conf.c ****     default :
+ 791:Src/usbd_conf.c ****       usb_status = USBD_FAIL;
+ 792:Src/usbd_conf.c ****     break;
+ 793:Src/usbd_conf.c ****   }
+ 794:Src/usbd_conf.c ****   return usb_status;
+  60              		.loc 1 794 3 is_stmt 1 view .LVU8
+ARM GAS  /tmp/ccf5FGie.s 			page 16
+
+
+ 795:Src/usbd_conf.c **** }
+  61              		.loc 1 795 1 is_stmt 0 view .LVU9
+  62 0012 7047     		bx	lr
+  63              		.cfi_endproc
+  64              	.LFE365:
+  66              		.section	.text.SystemClockConfig_Resume,"ax",%progbits
+  67              		.align	1
+  68              		.syntax unified
+  69              		.thumb
+  70              		.thumb_func
+  72              	SystemClockConfig_Resume:
+  73              	.LFB364:
+ 762:Src/usbd_conf.c ****   SystemClock_Config();
+  74              		.loc 1 762 1 is_stmt 1 view -0
+  75              		.cfi_startproc
+  76              		@ args = 0, pretend = 0, frame = 0
+  77              		@ frame_needed = 0, uses_anonymous_args = 0
+  78 0000 08B5     		push	{r3, lr}
+  79              	.LCFI0:
+  80              		.cfi_def_cfa_offset 8
+  81              		.cfi_offset 3, -8
+  82              		.cfi_offset 14, -4
+ 763:Src/usbd_conf.c **** }
+  83              		.loc 1 763 3 view .LVU11
+  84 0002 FFF7FEFF 		bl	SystemClock_Config
+  85              	.LVL5:
+ 764:Src/usbd_conf.c **** /* USER CODE END 5 */
+  86              		.loc 1 764 1 is_stmt 0 view .LVU12
+  87 0006 08BD     		pop	{r3, pc}
+  88              		.cfi_endproc
+  89              	.LFE364:
+  91              		.section	.text.HAL_PCD_MspInit,"ax",%progbits
+  92              		.align	1
+  93              		.global	HAL_PCD_MspInit
+  94              		.syntax unified
+  95              		.thumb
+  96              		.thumb_func
+  98              	HAL_PCD_MspInit:
+  99              	.LVL6:
+ 100              	.LFB333:
+  74:Src/usbd_conf.c ****   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ 101              		.loc 1 74 1 is_stmt 1 view -0
+ 102              		.cfi_startproc
+ 103              		@ args = 0, pretend = 0, frame = 72
+ 104              		@ frame_needed = 0, uses_anonymous_args = 0
+  74:Src/usbd_conf.c ****   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ 105              		.loc 1 74 1 is_stmt 0 view .LVU14
+ 106 0000 10B5     		push	{r4, lr}
+ 107              	.LCFI1:
+ 108              		.cfi_def_cfa_offset 8
+ 109              		.cfi_offset 4, -8
+ 110              		.cfi_offset 14, -4
+ 111 0002 92B0     		sub	sp, sp, #72
+ 112              	.LCFI2:
+ 113              		.cfi_def_cfa_offset 80
+ 114 0004 0446     		mov	r4, r0
+  75:Src/usbd_conf.c ****   if(pcdHandle->Instance==USB)
+ARM GAS  /tmp/ccf5FGie.s 			page 17
+
+
+ 115              		.loc 1 75 3 is_stmt 1 view .LVU15
+  75:Src/usbd_conf.c ****   if(pcdHandle->Instance==USB)
+ 116              		.loc 1 75 28 is_stmt 0 view .LVU16
+ 117 0006 4422     		movs	r2, #68
+ 118 0008 0021     		movs	r1, #0
+ 119 000a 01A8     		add	r0, sp, #4
+ 120              	.LVL7:
+  75:Src/usbd_conf.c ****   if(pcdHandle->Instance==USB)
+ 121              		.loc 1 75 28 view .LVU17
+ 122 000c FFF7FEFF 		bl	memset
+ 123              	.LVL8:
+  76:Src/usbd_conf.c ****   {
+ 124              		.loc 1 76 3 is_stmt 1 view .LVU18
+  76:Src/usbd_conf.c ****   {
+ 125              		.loc 1 76 15 is_stmt 0 view .LVU19
+ 126 0010 2268     		ldr	r2, [r4]
+  76:Src/usbd_conf.c ****   {
+ 127              		.loc 1 76 5 view .LVU20
+ 128 0012 114B     		ldr	r3, .L16
+ 129 0014 9A42     		cmp	r2, r3
+ 130 0016 01D0     		beq	.L14
+ 131              	.L10:
+ 101:Src/usbd_conf.c **** 
+ 132              		.loc 1 101 1 view .LVU21
+ 133 0018 12B0     		add	sp, sp, #72
+ 134              	.LCFI3:
+ 135              		.cfi_remember_state
+ 136              		.cfi_def_cfa_offset 8
+ 137              		@ sp needed
+ 138 001a 10BD     		pop	{r4, pc}
+ 139              	.LVL9:
+ 140              	.L14:
+ 141              	.LCFI4:
+ 142              		.cfi_restore_state
+  84:Src/usbd_conf.c ****     PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ 143              		.loc 1 84 5 is_stmt 1 view .LVU22
+  84:Src/usbd_conf.c ****     PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ 144              		.loc 1 84 40 is_stmt 0 view .LVU23
+ 145 001c 4FF40053 		mov	r3, #8192
+ 146 0020 0193     		str	r3, [sp, #4]
+  85:Src/usbd_conf.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 147              		.loc 1 85 5 is_stmt 1 view .LVU24
+  86:Src/usbd_conf.c ****     {
+ 148              		.loc 1 86 5 view .LVU25
+  86:Src/usbd_conf.c ****     {
+ 149              		.loc 1 86 9 is_stmt 0 view .LVU26
+ 150 0022 01A8     		add	r0, sp, #4
+ 151 0024 FFF7FEFF 		bl	HAL_RCCEx_PeriphCLKConfig
+ 152              	.LVL10:
+  86:Src/usbd_conf.c ****     {
+ 153              		.loc 1 86 8 view .LVU27
+ 154 0028 90B9     		cbnz	r0, .L15
+ 155              	.L12:
+  92:Src/usbd_conf.c **** 
+ 156              		.loc 1 92 5 is_stmt 1 view .LVU28
+ 157              	.LBB2:
+  92:Src/usbd_conf.c **** 
+ARM GAS  /tmp/ccf5FGie.s 			page 18
+
+
+ 158              		.loc 1 92 5 view .LVU29
+  92:Src/usbd_conf.c **** 
+ 159              		.loc 1 92 5 view .LVU30
+ 160 002a 0C4B     		ldr	r3, .L16+4
+ 161 002c 9A6D     		ldr	r2, [r3, #88]
+ 162 002e 42F40002 		orr	r2, r2, #8388608
+ 163 0032 9A65     		str	r2, [r3, #88]
+  92:Src/usbd_conf.c **** 
+ 164              		.loc 1 92 5 view .LVU31
+ 165 0034 9B6D     		ldr	r3, [r3, #88]
+ 166 0036 03F40003 		and	r3, r3, #8388608
+ 167 003a 0093     		str	r3, [sp]
+  92:Src/usbd_conf.c **** 
+ 168              		.loc 1 92 5 view .LVU32
+ 169 003c 009B     		ldr	r3, [sp]
+ 170              	.LBE2:
+  92:Src/usbd_conf.c **** 
+ 171              		.loc 1 92 5 view .LVU33
+  95:Src/usbd_conf.c ****     HAL_NVIC_EnableIRQ(USB_LP_IRQn);
+ 172              		.loc 1 95 5 view .LVU34
+ 173 003e 0022     		movs	r2, #0
+ 174 0040 1146     		mov	r1, r2
+ 175 0042 1420     		movs	r0, #20
+ 176 0044 FFF7FEFF 		bl	HAL_NVIC_SetPriority
+ 177              	.LVL11:
+  96:Src/usbd_conf.c ****   /* USER CODE BEGIN USB_MspInit 1 */
+ 178              		.loc 1 96 5 view .LVU35
+ 179 0048 1420     		movs	r0, #20
+ 180 004a FFF7FEFF 		bl	HAL_NVIC_EnableIRQ
+ 181              	.LVL12:
+ 101:Src/usbd_conf.c **** 
+ 182              		.loc 1 101 1 is_stmt 0 view .LVU36
+ 183 004e E3E7     		b	.L10
+ 184              	.L15:
+  88:Src/usbd_conf.c ****     }
+ 185              		.loc 1 88 7 is_stmt 1 view .LVU37
+ 186 0050 FFF7FEFF 		bl	Error_Handler
+ 187              	.LVL13:
+ 188 0054 E9E7     		b	.L12
+ 189              	.L17:
+ 190 0056 00BF     		.align	2
+ 191              	.L16:
+ 192 0058 005C0040 		.word	1073765376
+ 193 005c 00100240 		.word	1073876992
+ 194              		.cfi_endproc
+ 195              	.LFE333:
+ 197              		.section	.text.HAL_PCD_MspDeInit,"ax",%progbits
+ 198              		.align	1
+ 199              		.global	HAL_PCD_MspDeInit
+ 200              		.syntax unified
+ 201              		.thumb
+ 202              		.thumb_func
+ 204              	HAL_PCD_MspDeInit:
+ 205              	.LVL14:
+ 206              	.LFB334:
+ 108:Src/usbd_conf.c ****   if(pcdHandle->Instance==USB)
+ 207              		.loc 1 108 1 view -0
+ARM GAS  /tmp/ccf5FGie.s 			page 19
+
+
+ 208              		.cfi_startproc
+ 209              		@ args = 0, pretend = 0, frame = 0
+ 210              		@ frame_needed = 0, uses_anonymous_args = 0
+ 108:Src/usbd_conf.c ****   if(pcdHandle->Instance==USB)
+ 211              		.loc 1 108 1 is_stmt 0 view .LVU39
+ 212 0000 08B5     		push	{r3, lr}
+ 213              	.LCFI5:
+ 214              		.cfi_def_cfa_offset 8
+ 215              		.cfi_offset 3, -8
+ 216              		.cfi_offset 14, -4
+ 109:Src/usbd_conf.c ****   {
+ 217              		.loc 1 109 3 is_stmt 1 view .LVU40
+ 109:Src/usbd_conf.c ****   {
+ 218              		.loc 1 109 15 is_stmt 0 view .LVU41
+ 219 0002 0268     		ldr	r2, [r0]
+ 109:Src/usbd_conf.c ****   {
+ 220              		.loc 1 109 5 view .LVU42
+ 221 0004 064B     		ldr	r3, .L22
+ 222 0006 9A42     		cmp	r2, r3
+ 223 0008 00D0     		beq	.L21
+ 224              	.LVL15:
+ 225              	.L18:
+ 124:Src/usbd_conf.c **** 
+ 226              		.loc 1 124 1 view .LVU43
+ 227 000a 08BD     		pop	{r3, pc}
+ 228              	.LVL16:
+ 229              	.L21:
+ 115:Src/usbd_conf.c **** 
+ 230              		.loc 1 115 5 is_stmt 1 view .LVU44
+ 231 000c 054A     		ldr	r2, .L22+4
+ 232 000e 936D     		ldr	r3, [r2, #88]
+ 233 0010 23F40003 		bic	r3, r3, #8388608
+ 234 0014 9365     		str	r3, [r2, #88]
+ 118:Src/usbd_conf.c **** 
+ 235              		.loc 1 118 5 view .LVU45
+ 236 0016 1420     		movs	r0, #20
+ 237              	.LVL17:
+ 118:Src/usbd_conf.c **** 
+ 238              		.loc 1 118 5 is_stmt 0 view .LVU46
+ 239 0018 FFF7FEFF 		bl	HAL_NVIC_DisableIRQ
+ 240              	.LVL18:
+ 124:Src/usbd_conf.c **** 
+ 241              		.loc 1 124 1 view .LVU47
+ 242 001c F5E7     		b	.L18
+ 243              	.L23:
+ 244 001e 00BF     		.align	2
+ 245              	.L22:
+ 246 0020 005C0040 		.word	1073765376
+ 247 0024 00100240 		.word	1073876992
+ 248              		.cfi_endproc
+ 249              	.LFE334:
+ 251              		.section	.text.HAL_PCD_SetupStageCallback,"ax",%progbits
+ 252              		.align	1
+ 253              		.global	HAL_PCD_SetupStageCallback
+ 254              		.syntax unified
+ 255              		.thumb
+ 256              		.thumb_func
+ARM GAS  /tmp/ccf5FGie.s 			page 20
+
+
+ 258              	HAL_PCD_SetupStageCallback:
+ 259              	.LVL19:
+ 260              	.LFB335:
+ 136:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PreTreatment */
+ 261              		.loc 1 136 1 is_stmt 1 view -0
+ 262              		.cfi_startproc
+ 263              		@ args = 0, pretend = 0, frame = 0
+ 264              		@ frame_needed = 0, uses_anonymous_args = 0
+ 136:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PreTreatment */
+ 265              		.loc 1 136 1 is_stmt 0 view .LVU49
+ 266 0000 08B5     		push	{r3, lr}
+ 267              	.LCFI6:
+ 268              		.cfi_def_cfa_offset 8
+ 269              		.cfi_offset 3, -8
+ 270              		.cfi_offset 14, -4
+ 140:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PostTreatment */
+ 271              		.loc 1 140 3 is_stmt 1 view .LVU50
+ 272 0002 00F52C71 		add	r1, r0, #688
+ 273 0006 D0F8F002 		ldr	r0, [r0, #752]
+ 274              	.LVL20:
+ 140:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PostTreatment */
+ 275              		.loc 1 140 3 is_stmt 0 view .LVU51
+ 276 000a FFF7FEFF 		bl	USBD_LL_SetupStage
+ 277              	.LVL21:
+ 144:Src/usbd_conf.c **** 
+ 278              		.loc 1 144 1 view .LVU52
+ 279 000e 08BD     		pop	{r3, pc}
+ 280              		.cfi_endproc
+ 281              	.LFE335:
+ 283              		.section	.text.HAL_PCD_DataOutStageCallback,"ax",%progbits
+ 284              		.align	1
+ 285              		.global	HAL_PCD_DataOutStageCallback
+ 286              		.syntax unified
+ 287              		.thumb
+ 288              		.thumb_func
+ 290              	HAL_PCD_DataOutStageCallback:
+ 291              	.LVL22:
+ 292              	.LFB336:
+ 157:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PreTreatment */
+ 293              		.loc 1 157 1 is_stmt 1 view -0
+ 294              		.cfi_startproc
+ 295              		@ args = 0, pretend = 0, frame = 0
+ 296              		@ frame_needed = 0, uses_anonymous_args = 0
+ 157:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PreTreatment */
+ 297              		.loc 1 157 1 is_stmt 0 view .LVU54
+ 298 0000 08B5     		push	{r3, lr}
+ 299              	.LCFI7:
+ 300              		.cfi_def_cfa_offset 8
+ 301              		.cfi_offset 3, -8
+ 302              		.cfi_offset 14, -4
+ 161:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PostTreatment */
+ 303              		.loc 1 161 3 is_stmt 1 view .LVU55
+ 304 0002 01EB8103 		add	r3, r1, r1, lsl #2
+ 305 0006 00EBC303 		add	r3, r0, r3, lsl #3
+ 306 000a D3F87C21 		ldr	r2, [r3, #380]
+ 307 000e D0F8F002 		ldr	r0, [r0, #752]
+ 308              	.LVL23:
+ARM GAS  /tmp/ccf5FGie.s 			page 21
+
+
+ 161:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PostTreatment */
+ 309              		.loc 1 161 3 is_stmt 0 view .LVU56
+ 310 0012 FFF7FEFF 		bl	USBD_LL_DataOutStage
+ 311              	.LVL24:
+ 165:Src/usbd_conf.c **** 
+ 312              		.loc 1 165 1 view .LVU57
+ 313 0016 08BD     		pop	{r3, pc}
+ 314              		.cfi_endproc
+ 315              	.LFE336:
+ 317              		.section	.text.HAL_PCD_DataInStageCallback,"ax",%progbits
+ 318              		.align	1
+ 319              		.global	HAL_PCD_DataInStageCallback
+ 320              		.syntax unified
+ 321              		.thumb
+ 322              		.thumb_func
+ 324              	HAL_PCD_DataInStageCallback:
+ 325              	.LVL25:
+ 326              	.LFB337:
+ 178:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PreTreatment */
+ 327              		.loc 1 178 1 is_stmt 1 view -0
+ 328              		.cfi_startproc
+ 329              		@ args = 0, pretend = 0, frame = 0
+ 330              		@ frame_needed = 0, uses_anonymous_args = 0
+ 178:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PreTreatment */
+ 331              		.loc 1 178 1 is_stmt 0 view .LVU59
+ 332 0000 08B5     		push	{r3, lr}
+ 333              	.LCFI8:
+ 334              		.cfi_def_cfa_offset 8
+ 335              		.cfi_offset 3, -8
+ 336              		.cfi_offset 14, -4
+ 182:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PostTreatment  */
+ 337              		.loc 1 182 3 is_stmt 1 view .LVU60
+ 338 0002 01EB8103 		add	r3, r1, r1, lsl #2
+ 339 0006 00EBC303 		add	r3, r0, r3, lsl #3
+ 340 000a DA6B     		ldr	r2, [r3, #60]
+ 341 000c D0F8F002 		ldr	r0, [r0, #752]
+ 342              	.LVL26:
+ 182:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PostTreatment  */
+ 343              		.loc 1 182 3 is_stmt 0 view .LVU61
+ 344 0010 FFF7FEFF 		bl	USBD_LL_DataInStage
+ 345              	.LVL27:
+ 186:Src/usbd_conf.c **** 
+ 346              		.loc 1 186 1 view .LVU62
+ 347 0014 08BD     		pop	{r3, pc}
+ 348              		.cfi_endproc
+ 349              	.LFE337:
+ 351              		.section	.text.HAL_PCD_SOFCallback,"ax",%progbits
+ 352              		.align	1
+ 353              		.global	HAL_PCD_SOFCallback
+ 354              		.syntax unified
+ 355              		.thumb
+ 356              		.thumb_func
+ 358              	HAL_PCD_SOFCallback:
+ 359              	.LVL28:
+ 360              	.LFB338:
+ 198:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SOFCallback_PreTreatment */
+ 361              		.loc 1 198 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccf5FGie.s 			page 22
+
+
+ 362              		.cfi_startproc
+ 363              		@ args = 0, pretend = 0, frame = 0
+ 364              		@ frame_needed = 0, uses_anonymous_args = 0
+ 198:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SOFCallback_PreTreatment */
+ 365              		.loc 1 198 1 is_stmt 0 view .LVU64
+ 366 0000 08B5     		push	{r3, lr}
+ 367              	.LCFI9:
+ 368              		.cfi_def_cfa_offset 8
+ 369              		.cfi_offset 3, -8
+ 370              		.cfi_offset 14, -4
+ 202:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SOFCallback_PostTreatment */
+ 371              		.loc 1 202 3 is_stmt 1 view .LVU65
+ 372 0002 D0F8F002 		ldr	r0, [r0, #752]
+ 373              	.LVL29:
+ 202:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SOFCallback_PostTreatment */
+ 374              		.loc 1 202 3 is_stmt 0 view .LVU66
+ 375 0006 FFF7FEFF 		bl	USBD_LL_SOF
+ 376              	.LVL30:
+ 206:Src/usbd_conf.c **** 
+ 377              		.loc 1 206 1 view .LVU67
+ 378 000a 08BD     		pop	{r3, pc}
+ 379              		.cfi_endproc
+ 380              	.LFE338:
+ 382              		.section	.text.HAL_PCD_ResetCallback,"ax",%progbits
+ 383              		.align	1
+ 384              		.global	HAL_PCD_ResetCallback
+ 385              		.syntax unified
+ 386              		.thumb
+ 387              		.thumb_func
+ 389              	HAL_PCD_ResetCallback:
+ 390              	.LVL31:
+ 391              	.LFB339:
+ 218:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ResetCallback_PreTreatment */
+ 392              		.loc 1 218 1 is_stmt 1 view -0
+ 393              		.cfi_startproc
+ 394              		@ args = 0, pretend = 0, frame = 0
+ 395              		@ frame_needed = 0, uses_anonymous_args = 0
+ 218:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ResetCallback_PreTreatment */
+ 396              		.loc 1 218 1 is_stmt 0 view .LVU69
+ 397 0000 10B5     		push	{r4, lr}
+ 398              	.LCFI10:
+ 399              		.cfi_def_cfa_offset 8
+ 400              		.cfi_offset 4, -8
+ 401              		.cfi_offset 14, -4
+ 402 0002 0446     		mov	r4, r0
+ 222:Src/usbd_conf.c **** 
+ 403              		.loc 1 222 3 is_stmt 1 view .LVU70
+ 404              	.LVL32:
+ 224:Src/usbd_conf.c ****   {
+ 405              		.loc 1 224 3 view .LVU71
+ 224:Src/usbd_conf.c ****   {
+ 406              		.loc 1 224 18 is_stmt 0 view .LVU72
+ 407 0004 8368     		ldr	r3, [r0, #8]
+ 224:Src/usbd_conf.c ****   {
+ 408              		.loc 1 224 6 view .LVU73
+ 409 0006 022B     		cmp	r3, #2
+ 410 0008 09D1     		bne	.L35
+ARM GAS  /tmp/ccf5FGie.s 			page 23
+
+
+ 411              	.LVL33:
+ 412              	.L33:
+ 229:Src/usbd_conf.c **** 
+ 413              		.loc 1 229 3 is_stmt 1 view .LVU74
+ 414 000a 0121     		movs	r1, #1
+ 415 000c D4F8F002 		ldr	r0, [r4, #752]
+ 416 0010 FFF7FEFF 		bl	USBD_LL_SetSpeed
+ 417              	.LVL34:
+ 232:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ResetCallback_PostTreatment */
+ 418              		.loc 1 232 3 view .LVU75
+ 419 0014 D4F8F002 		ldr	r0, [r4, #752]
+ 420 0018 FFF7FEFF 		bl	USBD_LL_Reset
+ 421              	.LVL35:
+ 236:Src/usbd_conf.c **** 
+ 422              		.loc 1 236 1 is_stmt 0 view .LVU76
+ 423 001c 10BD     		pop	{r4, pc}
+ 424              	.LVL36:
+ 425              	.L35:
+ 226:Src/usbd_conf.c ****   }
+ 426              		.loc 1 226 5 is_stmt 1 view .LVU77
+ 427 001e FFF7FEFF 		bl	Error_Handler
+ 428              	.LVL37:
+ 226:Src/usbd_conf.c ****   }
+ 429              		.loc 1 226 5 is_stmt 0 view .LVU78
+ 430 0022 F2E7     		b	.L33
+ 431              		.cfi_endproc
+ 432              	.LFE339:
+ 434              		.section	.text.HAL_PCD_SuspendCallback,"ax",%progbits
+ 435              		.align	1
+ 436              		.global	HAL_PCD_SuspendCallback
+ 437              		.syntax unified
+ 438              		.thumb
+ 439              		.thumb_func
+ 441              	HAL_PCD_SuspendCallback:
+ 442              	.LVL38:
+ 443              	.LFB340:
+ 249:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SuspendCallback_PreTreatment */
+ 444              		.loc 1 249 1 is_stmt 1 view -0
+ 445              		.cfi_startproc
+ 446              		@ args = 0, pretend = 0, frame = 0
+ 447              		@ frame_needed = 0, uses_anonymous_args = 0
+ 249:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_SuspendCallback_PreTreatment */
+ 448              		.loc 1 249 1 is_stmt 0 view .LVU80
+ 449 0000 10B5     		push	{r4, lr}
+ 450              	.LCFI11:
+ 451              		.cfi_def_cfa_offset 8
+ 452              		.cfi_offset 4, -8
+ 453              		.cfi_offset 14, -4
+ 454 0002 0446     		mov	r4, r0
+ 254:Src/usbd_conf.c ****   /* Enter in STOP mode. */
+ 455              		.loc 1 254 3 is_stmt 1 view .LVU81
+ 456 0004 D0F8F002 		ldr	r0, [r0, #752]
+ 457              	.LVL39:
+ 254:Src/usbd_conf.c ****   /* Enter in STOP mode. */
+ 458              		.loc 1 254 3 is_stmt 0 view .LVU82
+ 459 0008 FFF7FEFF 		bl	USBD_LL_Suspend
+ 460              	.LVL40:
+ARM GAS  /tmp/ccf5FGie.s 			page 24
+
+
+ 257:Src/usbd_conf.c ****   {
+ 461              		.loc 1 257 3 is_stmt 1 view .LVU83
+ 257:Src/usbd_conf.c ****   {
+ 462              		.loc 1 257 17 is_stmt 0 view .LVU84
+ 463 000c A369     		ldr	r3, [r4, #24]
+ 257:Src/usbd_conf.c ****   {
+ 464              		.loc 1 257 6 view .LVU85
+ 465 000e 23B1     		cbz	r3, .L36
+ 260:Src/usbd_conf.c ****   }
+ 466              		.loc 1 260 5 is_stmt 1 view .LVU86
+ 260:Src/usbd_conf.c ****   }
+ 467              		.loc 1 260 8 is_stmt 0 view .LVU87
+ 468 0010 024A     		ldr	r2, .L39
+ 469 0012 1369     		ldr	r3, [r2, #16]
+ 260:Src/usbd_conf.c ****   }
+ 470              		.loc 1 260 14 view .LVU88
+ 471 0014 43F00603 		orr	r3, r3, #6
+ 472 0018 1361     		str	r3, [r2, #16]
+ 473              	.L36:
+ 266:Src/usbd_conf.c **** 
+ 474              		.loc 1 266 1 view .LVU89
+ 475 001a 10BD     		pop	{r4, pc}
+ 476              	.LVL41:
+ 477              	.L40:
+ 266:Src/usbd_conf.c **** 
+ 478              		.loc 1 266 1 view .LVU90
+ 479              		.align	2
+ 480              	.L39:
+ 481 001c 00ED00E0 		.word	-536810240
+ 482              		.cfi_endproc
+ 483              	.LFE340:
+ 485              		.section	.text.HAL_PCD_ResumeCallback,"ax",%progbits
+ 486              		.align	1
+ 487              		.global	HAL_PCD_ResumeCallback
+ 488              		.syntax unified
+ 489              		.thumb
+ 490              		.thumb_func
+ 492              	HAL_PCD_ResumeCallback:
+ 493              	.LVL42:
+ 494              	.LFB341:
+ 279:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ResumeCallback_PreTreatment */
+ 495              		.loc 1 279 1 is_stmt 1 view -0
+ 496              		.cfi_startproc
+ 497              		@ args = 0, pretend = 0, frame = 0
+ 498              		@ frame_needed = 0, uses_anonymous_args = 0
+ 279:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ResumeCallback_PreTreatment */
+ 499              		.loc 1 279 1 is_stmt 0 view .LVU92
+ 500 0000 10B5     		push	{r4, lr}
+ 501              	.LCFI12:
+ 502              		.cfi_def_cfa_offset 8
+ 503              		.cfi_offset 4, -8
+ 504              		.cfi_offset 14, -4
+ 505 0002 0446     		mov	r4, r0
+ 285:Src/usbd_conf.c ****   {
+ 506              		.loc 1 285 3 is_stmt 1 view .LVU93
+ 285:Src/usbd_conf.c ****   {
+ 507              		.loc 1 285 17 is_stmt 0 view .LVU94
+ARM GAS  /tmp/ccf5FGie.s 			page 25
+
+
+ 508 0004 8369     		ldr	r3, [r0, #24]
+ 285:Src/usbd_conf.c ****   {
+ 509              		.loc 1 285 6 view .LVU95
+ 510 0006 23B9     		cbnz	r3, .L44
+ 511              	.LVL43:
+ 512              	.L42:
+ 293:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ResumeCallback_PostTreatment */
+ 513              		.loc 1 293 3 is_stmt 1 view .LVU96
+ 514 0008 D4F8F002 		ldr	r0, [r4, #752]
+ 515 000c FFF7FEFF 		bl	USBD_LL_Resume
+ 516              	.LVL44:
+ 297:Src/usbd_conf.c **** 
+ 517              		.loc 1 297 1 is_stmt 0 view .LVU97
+ 518 0010 10BD     		pop	{r4, pc}
+ 519              	.LVL45:
+ 520              	.L44:
+ 288:Src/usbd_conf.c ****     SystemClockConfig_Resume();
+ 521              		.loc 1 288 5 is_stmt 1 view .LVU98
+ 288:Src/usbd_conf.c ****     SystemClockConfig_Resume();
+ 522              		.loc 1 288 8 is_stmt 0 view .LVU99
+ 523 0012 044A     		ldr	r2, .L45
+ 524 0014 1369     		ldr	r3, [r2, #16]
+ 288:Src/usbd_conf.c ****     SystemClockConfig_Resume();
+ 525              		.loc 1 288 14 view .LVU100
+ 526 0016 23F00603 		bic	r3, r3, #6
+ 527 001a 1361     		str	r3, [r2, #16]
+ 289:Src/usbd_conf.c ****   }
+ 528              		.loc 1 289 5 is_stmt 1 view .LVU101
+ 529 001c FFF7FEFF 		bl	SystemClockConfig_Resume
+ 530              	.LVL46:
+ 289:Src/usbd_conf.c ****   }
+ 531              		.loc 1 289 5 is_stmt 0 view .LVU102
+ 532 0020 F2E7     		b	.L42
+ 533              	.L46:
+ 534 0022 00BF     		.align	2
+ 535              	.L45:
+ 536 0024 00ED00E0 		.word	-536810240
+ 537              		.cfi_endproc
+ 538              	.LFE341:
+ 540              		.section	.text.HAL_PCD_ISOOUTIncompleteCallback,"ax",%progbits
+ 541              		.align	1
+ 542              		.global	HAL_PCD_ISOOUTIncompleteCallback
+ 543              		.syntax unified
+ 544              		.thumb
+ 545              		.thumb_func
+ 547              	HAL_PCD_ISOOUTIncompleteCallback:
+ 548              	.LVL47:
+ 549              	.LFB342:
+ 310:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ISOOUTIncompleteCallback_PreTreatment */
+ 550              		.loc 1 310 1 is_stmt 1 view -0
+ 551              		.cfi_startproc
+ 552              		@ args = 0, pretend = 0, frame = 0
+ 553              		@ frame_needed = 0, uses_anonymous_args = 0
+ 310:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ISOOUTIncompleteCallback_PreTreatment */
+ 554              		.loc 1 310 1 is_stmt 0 view .LVU104
+ 555 0000 08B5     		push	{r3, lr}
+ 556              	.LCFI13:
+ARM GAS  /tmp/ccf5FGie.s 			page 26
+
+
+ 557              		.cfi_def_cfa_offset 8
+ 558              		.cfi_offset 3, -8
+ 559              		.cfi_offset 14, -4
+ 314:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ISOOUTIncompleteCallback_PostTreatment */
+ 560              		.loc 1 314 3 is_stmt 1 view .LVU105
+ 561 0002 D0F8F002 		ldr	r0, [r0, #752]
+ 562              	.LVL48:
+ 314:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ISOOUTIncompleteCallback_PostTreatment */
+ 563              		.loc 1 314 3 is_stmt 0 view .LVU106
+ 564 0006 FFF7FEFF 		bl	USBD_LL_IsoOUTIncomplete
+ 565              	.LVL49:
+ 318:Src/usbd_conf.c **** 
+ 566              		.loc 1 318 1 view .LVU107
+ 567 000a 08BD     		pop	{r3, pc}
+ 568              		.cfi_endproc
+ 569              	.LFE342:
+ 571              		.section	.text.HAL_PCD_ISOINIncompleteCallback,"ax",%progbits
+ 572              		.align	1
+ 573              		.global	HAL_PCD_ISOINIncompleteCallback
+ 574              		.syntax unified
+ 575              		.thumb
+ 576              		.thumb_func
+ 578              	HAL_PCD_ISOINIncompleteCallback:
+ 579              	.LVL50:
+ 580              	.LFB343:
+ 331:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ISOINIncompleteCallback_PreTreatment */
+ 581              		.loc 1 331 1 is_stmt 1 view -0
+ 582              		.cfi_startproc
+ 583              		@ args = 0, pretend = 0, frame = 0
+ 584              		@ frame_needed = 0, uses_anonymous_args = 0
+ 331:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ISOINIncompleteCallback_PreTreatment */
+ 585              		.loc 1 331 1 is_stmt 0 view .LVU109
+ 586 0000 08B5     		push	{r3, lr}
+ 587              	.LCFI14:
+ 588              		.cfi_def_cfa_offset 8
+ 589              		.cfi_offset 3, -8
+ 590              		.cfi_offset 14, -4
+ 335:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ISOINIncompleteCallback_PostTreatment */
+ 591              		.loc 1 335 3 is_stmt 1 view .LVU110
+ 592 0002 D0F8F002 		ldr	r0, [r0, #752]
+ 593              	.LVL51:
+ 335:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ISOINIncompleteCallback_PostTreatment */
+ 594              		.loc 1 335 3 is_stmt 0 view .LVU111
+ 595 0006 FFF7FEFF 		bl	USBD_LL_IsoINIncomplete
+ 596              	.LVL52:
+ 339:Src/usbd_conf.c **** 
+ 597              		.loc 1 339 1 view .LVU112
+ 598 000a 08BD     		pop	{r3, pc}
+ 599              		.cfi_endproc
+ 600              	.LFE343:
+ 602              		.section	.text.HAL_PCD_ConnectCallback,"ax",%progbits
+ 603              		.align	1
+ 604              		.global	HAL_PCD_ConnectCallback
+ 605              		.syntax unified
+ 606              		.thumb
+ 607              		.thumb_func
+ 609              	HAL_PCD_ConnectCallback:
+ARM GAS  /tmp/ccf5FGie.s 			page 27
+
+
+ 610              	.LVL53:
+ 611              	.LFB344:
+ 351:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ConnectCallback_PreTreatment */
+ 612              		.loc 1 351 1 is_stmt 1 view -0
+ 613              		.cfi_startproc
+ 614              		@ args = 0, pretend = 0, frame = 0
+ 615              		@ frame_needed = 0, uses_anonymous_args = 0
+ 351:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ConnectCallback_PreTreatment */
+ 616              		.loc 1 351 1 is_stmt 0 view .LVU114
+ 617 0000 08B5     		push	{r3, lr}
+ 618              	.LCFI15:
+ 619              		.cfi_def_cfa_offset 8
+ 620              		.cfi_offset 3, -8
+ 621              		.cfi_offset 14, -4
+ 355:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ConnectCallback_PostTreatment */
+ 622              		.loc 1 355 3 is_stmt 1 view .LVU115
+ 623 0002 D0F8F002 		ldr	r0, [r0, #752]
+ 624              	.LVL54:
+ 355:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_ConnectCallback_PostTreatment */
+ 625              		.loc 1 355 3 is_stmt 0 view .LVU116
+ 626 0006 FFF7FEFF 		bl	USBD_LL_DevConnected
+ 627              	.LVL55:
+ 359:Src/usbd_conf.c **** 
+ 628              		.loc 1 359 1 view .LVU117
+ 629 000a 08BD     		pop	{r3, pc}
+ 630              		.cfi_endproc
+ 631              	.LFE344:
+ 633              		.section	.text.HAL_PCD_DisconnectCallback,"ax",%progbits
+ 634              		.align	1
+ 635              		.global	HAL_PCD_DisconnectCallback
+ 636              		.syntax unified
+ 637              		.thumb
+ 638              		.thumb_func
+ 640              	HAL_PCD_DisconnectCallback:
+ 641              	.LVL56:
+ 642              	.LFB345:
+ 371:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DisconnectCallback_PreTreatment */
+ 643              		.loc 1 371 1 is_stmt 1 view -0
+ 644              		.cfi_startproc
+ 645              		@ args = 0, pretend = 0, frame = 0
+ 646              		@ frame_needed = 0, uses_anonymous_args = 0
+ 371:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DisconnectCallback_PreTreatment */
+ 647              		.loc 1 371 1 is_stmt 0 view .LVU119
+ 648 0000 08B5     		push	{r3, lr}
+ 649              	.LCFI16:
+ 650              		.cfi_def_cfa_offset 8
+ 651              		.cfi_offset 3, -8
+ 652              		.cfi_offset 14, -4
+ 375:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DisconnectCallback_PostTreatment */
+ 653              		.loc 1 375 3 is_stmt 1 view .LVU120
+ 654 0002 D0F8F002 		ldr	r0, [r0, #752]
+ 655              	.LVL57:
+ 375:Src/usbd_conf.c ****   /* USER CODE BEGIN HAL_PCD_DisconnectCallback_PostTreatment */
+ 656              		.loc 1 375 3 is_stmt 0 view .LVU121
+ 657 0006 FFF7FEFF 		bl	USBD_LL_DevDisconnected
+ 658              	.LVL58:
+ 379:Src/usbd_conf.c **** 
+ARM GAS  /tmp/ccf5FGie.s 			page 28
+
+
+ 659              		.loc 1 379 1 view .LVU122
+ 660 000a 08BD     		pop	{r3, pc}
+ 661              		.cfi_endproc
+ 662              	.LFE345:
+ 664              		.section	.text.USBD_LL_Init,"ax",%progbits
+ 665              		.align	1
+ 666              		.global	USBD_LL_Init
+ 667              		.syntax unified
+ 668              		.thumb
+ 669              		.thumb_func
+ 671              	USBD_LL_Init:
+ 672              	.LVL59:
+ 673              	.LFB346:
+ 395:Src/usbd_conf.c ****   /* Init USB Ip. */
+ 674              		.loc 1 395 1 is_stmt 1 view -0
+ 675              		.cfi_startproc
+ 676              		@ args = 0, pretend = 0, frame = 0
+ 677              		@ frame_needed = 0, uses_anonymous_args = 0
+ 395:Src/usbd_conf.c ****   /* Init USB Ip. */
+ 678              		.loc 1 395 1 is_stmt 0 view .LVU124
+ 679 0000 10B5     		push	{r4, lr}
+ 680              	.LCFI17:
+ 681              		.cfi_def_cfa_offset 8
+ 682              		.cfi_offset 4, -8
+ 683              		.cfi_offset 14, -4
+ 684 0002 0446     		mov	r4, r0
+ 397:Src/usbd_conf.c ****   /* Link the driver to the stack. */
+ 685              		.loc 1 397 3 is_stmt 1 view .LVU125
+ 397:Src/usbd_conf.c ****   /* Link the driver to the stack. */
+ 686              		.loc 1 397 21 is_stmt 0 view .LVU126
+ 687 0004 1648     		ldr	r0, .L59
+ 688              	.LVL60:
+ 397:Src/usbd_conf.c ****   /* Link the driver to the stack. */
+ 689              		.loc 1 397 21 view .LVU127
+ 690 0006 C0F8F042 		str	r4, [r0, #752]
+ 399:Src/usbd_conf.c **** 
+ 691              		.loc 1 399 3 is_stmt 1 view .LVU128
+ 399:Src/usbd_conf.c **** 
+ 692              		.loc 1 399 15 is_stmt 0 view .LVU129
+ 693 000a C4F8C402 		str	r0, [r4, #708]
+ 401:Src/usbd_conf.c ****   hpcd_USB_FS.Init.dev_endpoints = 8;
+ 694              		.loc 1 401 3 is_stmt 1 view .LVU130
+ 401:Src/usbd_conf.c ****   hpcd_USB_FS.Init.dev_endpoints = 8;
+ 695              		.loc 1 401 24 is_stmt 0 view .LVU131
+ 696 000e 154B     		ldr	r3, .L59+4
+ 697 0010 0360     		str	r3, [r0]
+ 402:Src/usbd_conf.c ****   hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
+ 698              		.loc 1 402 3 is_stmt 1 view .LVU132
+ 402:Src/usbd_conf.c ****   hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
+ 699              		.loc 1 402 34 is_stmt 0 view .LVU133
+ 700 0012 0823     		movs	r3, #8
+ 701 0014 4360     		str	r3, [r0, #4]
+ 403:Src/usbd_conf.c ****   hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
+ 702              		.loc 1 403 3 is_stmt 1 view .LVU134
+ 403:Src/usbd_conf.c ****   hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
+ 703              		.loc 1 403 26 is_stmt 0 view .LVU135
+ 704 0016 0223     		movs	r3, #2
+ARM GAS  /tmp/ccf5FGie.s 			page 29
+
+
+ 705 0018 8360     		str	r3, [r0, #8]
+ 404:Src/usbd_conf.c ****   hpcd_USB_FS.Init.Sof_enable = DISABLE;
+ 706              		.loc 1 404 3 is_stmt 1 view .LVU136
+ 404:Src/usbd_conf.c ****   hpcd_USB_FS.Init.Sof_enable = DISABLE;
+ 707              		.loc 1 404 31 is_stmt 0 view .LVU137
+ 708 001a 0361     		str	r3, [r0, #16]
+ 405:Src/usbd_conf.c ****   hpcd_USB_FS.Init.low_power_enable = DISABLE;
+ 709              		.loc 1 405 3 is_stmt 1 view .LVU138
+ 405:Src/usbd_conf.c ****   hpcd_USB_FS.Init.low_power_enable = DISABLE;
+ 710              		.loc 1 405 31 is_stmt 0 view .LVU139
+ 711 001c 0023     		movs	r3, #0
+ 712 001e 4361     		str	r3, [r0, #20]
+ 406:Src/usbd_conf.c ****   hpcd_USB_FS.Init.lpm_enable = DISABLE;
+ 713              		.loc 1 406 3 is_stmt 1 view .LVU140
+ 406:Src/usbd_conf.c ****   hpcd_USB_FS.Init.lpm_enable = DISABLE;
+ 714              		.loc 1 406 37 is_stmt 0 view .LVU141
+ 715 0020 8361     		str	r3, [r0, #24]
+ 407:Src/usbd_conf.c ****   hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
+ 716              		.loc 1 407 3 is_stmt 1 view .LVU142
+ 407:Src/usbd_conf.c ****   hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
+ 717              		.loc 1 407 31 is_stmt 0 view .LVU143
+ 718 0022 C361     		str	r3, [r0, #28]
+ 408:Src/usbd_conf.c **** 
+ 719              		.loc 1 408 3 is_stmt 1 view .LVU144
+ 408:Src/usbd_conf.c **** 
+ 720              		.loc 1 408 44 is_stmt 0 view .LVU145
+ 721 0024 0362     		str	r3, [r0, #32]
+ 416:Src/usbd_conf.c ****   {
+ 722              		.loc 1 416 3 is_stmt 1 view .LVU146
+ 416:Src/usbd_conf.c ****   {
+ 723              		.loc 1 416 7 is_stmt 0 view .LVU147
+ 724 0026 FFF7FEFF 		bl	HAL_PCD_Init
+ 725              	.LVL61:
+ 416:Src/usbd_conf.c ****   {
+ 726              		.loc 1 416 6 view .LVU148
+ 727 002a B0B9     		cbnz	r0, .L58
+ 728              	.L56:
+ 443:Src/usbd_conf.c ****   HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData, 0x80, PCD_SNG_BUF, 0x50);
+ 729              		.loc 1 443 3 is_stmt 1 view .LVU149
+ 730 002c 1023     		movs	r3, #16
+ 731 002e 0022     		movs	r2, #0
+ 732 0030 1146     		mov	r1, r2
+ 733 0032 D4F8C402 		ldr	r0, [r4, #708]
+ 734 0036 FFF7FEFF 		bl	HAL_PCDEx_PMAConfig
+ 735              	.LVL62:
+ 444:Src/usbd_conf.c ****   /* USER CODE END EndPoint_Configuration */
+ 736              		.loc 1 444 3 view .LVU150
+ 737 003a 5023     		movs	r3, #80
+ 738 003c 0022     		movs	r2, #0
+ 739 003e 8021     		movs	r1, #128
+ 740 0040 D4F8C402 		ldr	r0, [r4, #708]
+ 741 0044 FFF7FEFF 		bl	HAL_PCDEx_PMAConfig
+ 742              	.LVL63:
+ 447:Src/usbd_conf.c ****   /* USER CODE END EndPoint_Configuration_AUDIO */
+ 743              		.loc 1 447 3 view .LVU151
+ 744 0048 074B     		ldr	r3, .L59+8
+ 745 004a 0122     		movs	r2, #1
+ARM GAS  /tmp/ccf5FGie.s 			page 30
+
+
+ 746 004c 1146     		mov	r1, r2
+ 747 004e D4F8C402 		ldr	r0, [r4, #708]
+ 748 0052 FFF7FEFF 		bl	HAL_PCDEx_PMAConfig
+ 749              	.LVL64:
+ 449:Src/usbd_conf.c **** }
+ 750              		.loc 1 449 3 view .LVU152
+ 450:Src/usbd_conf.c **** 
+ 751              		.loc 1 450 1 is_stmt 0 view .LVU153
+ 752 0056 0020     		movs	r0, #0
+ 753 0058 10BD     		pop	{r4, pc}
+ 754              	.LVL65:
+ 755              	.L58:
+ 418:Src/usbd_conf.c ****   }
+ 756              		.loc 1 418 5 is_stmt 1 view .LVU154
+ 757 005a FFF7FEFF 		bl	Error_Handler
+ 758              	.LVL66:
+ 759 005e E5E7     		b	.L56
+ 760              	.L60:
+ 761              		.align	2
+ 762              	.L59:
+ 763 0060 00000000 		.word	hpcd_USB_FS
+ 764 0064 005C0040 		.word	1073765376
+ 765 0068 90005001 		.word	22020240
+ 766              		.cfi_endproc
+ 767              	.LFE346:
+ 769              		.section	.text.USBD_LL_DeInit,"ax",%progbits
+ 770              		.align	1
+ 771              		.global	USBD_LL_DeInit
+ 772              		.syntax unified
+ 773              		.thumb
+ 774              		.thumb_func
+ 776              	USBD_LL_DeInit:
+ 777              	.LVL67:
+ 778              	.LFB347:
+ 458:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 779              		.loc 1 458 1 view -0
+ 780              		.cfi_startproc
+ 781              		@ args = 0, pretend = 0, frame = 0
+ 782              		@ frame_needed = 0, uses_anonymous_args = 0
+ 458:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 783              		.loc 1 458 1 is_stmt 0 view .LVU156
+ 784 0000 08B5     		push	{r3, lr}
+ 785              	.LCFI18:
+ 786              		.cfi_def_cfa_offset 8
+ 787              		.cfi_offset 3, -8
+ 788              		.cfi_offset 14, -4
+ 459:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 789              		.loc 1 459 3 is_stmt 1 view .LVU157
+ 790              	.LVL68:
+ 460:Src/usbd_conf.c **** 
+ 791              		.loc 1 460 3 view .LVU158
+ 462:Src/usbd_conf.c **** 
+ 792              		.loc 1 462 3 view .LVU159
+ 462:Src/usbd_conf.c **** 
+ 793              		.loc 1 462 16 is_stmt 0 view .LVU160
+ 794 0002 D0F8C402 		ldr	r0, [r0, #708]
+ 795              	.LVL69:
+ARM GAS  /tmp/ccf5FGie.s 			page 31
+
+
+ 462:Src/usbd_conf.c **** 
+ 796              		.loc 1 462 16 view .LVU161
+ 797 0006 FFF7FEFF 		bl	HAL_PCD_DeInit
+ 798              	.LVL70:
+ 464:Src/usbd_conf.c **** 
+ 799              		.loc 1 464 3 is_stmt 1 view .LVU162
+ 464:Src/usbd_conf.c **** 
+ 800              		.loc 1 464 17 is_stmt 0 view .LVU163
+ 801 000a FFF7FEFF 		bl	USBD_Get_USB_Status
+ 802              	.LVL71:
+ 466:Src/usbd_conf.c **** }
+ 803              		.loc 1 466 3 is_stmt 1 view .LVU164
+ 467:Src/usbd_conf.c **** 
+ 804              		.loc 1 467 1 is_stmt 0 view .LVU165
+ 805 000e 08BD     		pop	{r3, pc}
+ 806              		.cfi_endproc
+ 807              	.LFE347:
+ 809              		.section	.text.USBD_LL_Start,"ax",%progbits
+ 810              		.align	1
+ 811              		.global	USBD_LL_Start
+ 812              		.syntax unified
+ 813              		.thumb
+ 814              		.thumb_func
+ 816              	USBD_LL_Start:
+ 817              	.LVL72:
+ 818              	.LFB348:
+ 475:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 819              		.loc 1 475 1 is_stmt 1 view -0
+ 820              		.cfi_startproc
+ 821              		@ args = 0, pretend = 0, frame = 0
+ 822              		@ frame_needed = 0, uses_anonymous_args = 0
+ 475:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 823              		.loc 1 475 1 is_stmt 0 view .LVU167
+ 824 0000 08B5     		push	{r3, lr}
+ 825              	.LCFI19:
+ 826              		.cfi_def_cfa_offset 8
+ 827              		.cfi_offset 3, -8
+ 828              		.cfi_offset 14, -4
+ 476:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 829              		.loc 1 476 3 is_stmt 1 view .LVU168
+ 830              	.LVL73:
+ 477:Src/usbd_conf.c **** 
+ 831              		.loc 1 477 3 view .LVU169
+ 479:Src/usbd_conf.c **** 
+ 832              		.loc 1 479 3 view .LVU170
+ 479:Src/usbd_conf.c **** 
+ 833              		.loc 1 479 16 is_stmt 0 view .LVU171
+ 834 0002 D0F8C402 		ldr	r0, [r0, #708]
+ 835              	.LVL74:
+ 479:Src/usbd_conf.c **** 
+ 836              		.loc 1 479 16 view .LVU172
+ 837 0006 FFF7FEFF 		bl	HAL_PCD_Start
+ 838              	.LVL75:
+ 481:Src/usbd_conf.c **** 
+ 839              		.loc 1 481 3 is_stmt 1 view .LVU173
+ 481:Src/usbd_conf.c **** 
+ 840              		.loc 1 481 17 is_stmt 0 view .LVU174
+ARM GAS  /tmp/ccf5FGie.s 			page 32
+
+
+ 841 000a FFF7FEFF 		bl	USBD_Get_USB_Status
+ 842              	.LVL76:
+ 483:Src/usbd_conf.c **** }
+ 843              		.loc 1 483 3 is_stmt 1 view .LVU175
+ 484:Src/usbd_conf.c **** 
+ 844              		.loc 1 484 1 is_stmt 0 view .LVU176
+ 845 000e 08BD     		pop	{r3, pc}
+ 846              		.cfi_endproc
+ 847              	.LFE348:
+ 849              		.section	.text.USBD_LL_Stop,"ax",%progbits
+ 850              		.align	1
+ 851              		.global	USBD_LL_Stop
+ 852              		.syntax unified
+ 853              		.thumb
+ 854              		.thumb_func
+ 856              	USBD_LL_Stop:
+ 857              	.LVL77:
+ 858              	.LFB349:
+ 492:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 859              		.loc 1 492 1 is_stmt 1 view -0
+ 860              		.cfi_startproc
+ 861              		@ args = 0, pretend = 0, frame = 0
+ 862              		@ frame_needed = 0, uses_anonymous_args = 0
+ 492:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 863              		.loc 1 492 1 is_stmt 0 view .LVU178
+ 864 0000 08B5     		push	{r3, lr}
+ 865              	.LCFI20:
+ 866              		.cfi_def_cfa_offset 8
+ 867              		.cfi_offset 3, -8
+ 868              		.cfi_offset 14, -4
+ 493:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 869              		.loc 1 493 3 is_stmt 1 view .LVU179
+ 870              	.LVL78:
+ 494:Src/usbd_conf.c **** 
+ 871              		.loc 1 494 3 view .LVU180
+ 496:Src/usbd_conf.c **** 
+ 872              		.loc 1 496 3 view .LVU181
+ 496:Src/usbd_conf.c **** 
+ 873              		.loc 1 496 16 is_stmt 0 view .LVU182
+ 874 0002 D0F8C402 		ldr	r0, [r0, #708]
+ 875              	.LVL79:
+ 496:Src/usbd_conf.c **** 
+ 876              		.loc 1 496 16 view .LVU183
+ 877 0006 FFF7FEFF 		bl	HAL_PCD_Stop
+ 878              	.LVL80:
+ 498:Src/usbd_conf.c **** 
+ 879              		.loc 1 498 3 is_stmt 1 view .LVU184
+ 498:Src/usbd_conf.c **** 
+ 880              		.loc 1 498 17 is_stmt 0 view .LVU185
+ 881 000a FFF7FEFF 		bl	USBD_Get_USB_Status
+ 882              	.LVL81:
+ 500:Src/usbd_conf.c **** }
+ 883              		.loc 1 500 3 is_stmt 1 view .LVU186
+ 501:Src/usbd_conf.c **** 
+ 884              		.loc 1 501 1 is_stmt 0 view .LVU187
+ 885 000e 08BD     		pop	{r3, pc}
+ 886              		.cfi_endproc
+ARM GAS  /tmp/ccf5FGie.s 			page 33
+
+
+ 887              	.LFE349:
+ 889              		.section	.text.USBD_LL_OpenEP,"ax",%progbits
+ 890              		.align	1
+ 891              		.global	USBD_LL_OpenEP
+ 892              		.syntax unified
+ 893              		.thumb
+ 894              		.thumb_func
+ 896              	USBD_LL_OpenEP:
+ 897              	.LVL82:
+ 898              	.LFB350:
+ 512:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 899              		.loc 1 512 1 is_stmt 1 view -0
+ 900              		.cfi_startproc
+ 901              		@ args = 0, pretend = 0, frame = 0
+ 902              		@ frame_needed = 0, uses_anonymous_args = 0
+ 512:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 903              		.loc 1 512 1 is_stmt 0 view .LVU189
+ 904 0000 08B5     		push	{r3, lr}
+ 905              	.LCFI21:
+ 906              		.cfi_def_cfa_offset 8
+ 907              		.cfi_offset 3, -8
+ 908              		.cfi_offset 14, -4
+ 909 0002 9446     		mov	ip, r2
+ 910 0004 1A46     		mov	r2, r3
+ 911              	.LVL83:
+ 513:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 912              		.loc 1 513 3 is_stmt 1 view .LVU190
+ 514:Src/usbd_conf.c **** 
+ 913              		.loc 1 514 3 view .LVU191
+ 516:Src/usbd_conf.c **** 
+ 914              		.loc 1 516 3 view .LVU192
+ 516:Src/usbd_conf.c **** 
+ 915              		.loc 1 516 16 is_stmt 0 view .LVU193
+ 916 0006 6346     		mov	r3, ip
+ 917              	.LVL84:
+ 516:Src/usbd_conf.c **** 
+ 918              		.loc 1 516 16 view .LVU194
+ 919 0008 D0F8C402 		ldr	r0, [r0, #708]
+ 920              	.LVL85:
+ 516:Src/usbd_conf.c **** 
+ 921              		.loc 1 516 16 view .LVU195
+ 922 000c FFF7FEFF 		bl	HAL_PCD_EP_Open
+ 923              	.LVL86:
+ 518:Src/usbd_conf.c **** 
+ 924              		.loc 1 518 3 is_stmt 1 view .LVU196
+ 518:Src/usbd_conf.c **** 
+ 925              		.loc 1 518 17 is_stmt 0 view .LVU197
+ 926 0010 FFF7FEFF 		bl	USBD_Get_USB_Status
+ 927              	.LVL87:
+ 520:Src/usbd_conf.c **** }
+ 928              		.loc 1 520 3 is_stmt 1 view .LVU198
+ 521:Src/usbd_conf.c **** 
+ 929              		.loc 1 521 1 is_stmt 0 view .LVU199
+ 930 0014 08BD     		pop	{r3, pc}
+ 931              		.cfi_endproc
+ 932              	.LFE350:
+ 934              		.section	.text.USBD_LL_CloseEP,"ax",%progbits
+ARM GAS  /tmp/ccf5FGie.s 			page 34
+
+
+ 935              		.align	1
+ 936              		.global	USBD_LL_CloseEP
+ 937              		.syntax unified
+ 938              		.thumb
+ 939              		.thumb_func
+ 941              	USBD_LL_CloseEP:
+ 942              	.LVL88:
+ 943              	.LFB351:
+ 530:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 944              		.loc 1 530 1 is_stmt 1 view -0
+ 945              		.cfi_startproc
+ 946              		@ args = 0, pretend = 0, frame = 0
+ 947              		@ frame_needed = 0, uses_anonymous_args = 0
+ 530:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 948              		.loc 1 530 1 is_stmt 0 view .LVU201
+ 949 0000 08B5     		push	{r3, lr}
+ 950              	.LCFI22:
+ 951              		.cfi_def_cfa_offset 8
+ 952              		.cfi_offset 3, -8
+ 953              		.cfi_offset 14, -4
+ 531:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 954              		.loc 1 531 3 is_stmt 1 view .LVU202
+ 955              	.LVL89:
+ 532:Src/usbd_conf.c **** 
+ 956              		.loc 1 532 3 view .LVU203
+ 534:Src/usbd_conf.c **** 
+ 957              		.loc 1 534 3 view .LVU204
+ 534:Src/usbd_conf.c **** 
+ 958              		.loc 1 534 16 is_stmt 0 view .LVU205
+ 959 0002 D0F8C402 		ldr	r0, [r0, #708]
+ 960              	.LVL90:
+ 534:Src/usbd_conf.c **** 
+ 961              		.loc 1 534 16 view .LVU206
+ 962 0006 FFF7FEFF 		bl	HAL_PCD_EP_Close
+ 963              	.LVL91:
+ 536:Src/usbd_conf.c **** 
+ 964              		.loc 1 536 3 is_stmt 1 view .LVU207
+ 536:Src/usbd_conf.c **** 
+ 965              		.loc 1 536 17 is_stmt 0 view .LVU208
+ 966 000a FFF7FEFF 		bl	USBD_Get_USB_Status
+ 967              	.LVL92:
+ 538:Src/usbd_conf.c **** }
+ 968              		.loc 1 538 3 is_stmt 1 view .LVU209
+ 539:Src/usbd_conf.c **** 
+ 969              		.loc 1 539 1 is_stmt 0 view .LVU210
+ 970 000e 08BD     		pop	{r3, pc}
+ 971              		.cfi_endproc
+ 972              	.LFE351:
+ 974              		.section	.text.USBD_LL_FlushEP,"ax",%progbits
+ 975              		.align	1
+ 976              		.global	USBD_LL_FlushEP
+ 977              		.syntax unified
+ 978              		.thumb
+ 979              		.thumb_func
+ 981              	USBD_LL_FlushEP:
+ 982              	.LVL93:
+ 983              	.LFB352:
+ARM GAS  /tmp/ccf5FGie.s 			page 35
+
+
+ 548:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 984              		.loc 1 548 1 is_stmt 1 view -0
+ 985              		.cfi_startproc
+ 986              		@ args = 0, pretend = 0, frame = 0
+ 987              		@ frame_needed = 0, uses_anonymous_args = 0
+ 548:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 988              		.loc 1 548 1 is_stmt 0 view .LVU212
+ 989 0000 08B5     		push	{r3, lr}
+ 990              	.LCFI23:
+ 991              		.cfi_def_cfa_offset 8
+ 992              		.cfi_offset 3, -8
+ 993              		.cfi_offset 14, -4
+ 549:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 994              		.loc 1 549 3 is_stmt 1 view .LVU213
+ 995              	.LVL94:
+ 550:Src/usbd_conf.c **** 
+ 996              		.loc 1 550 3 view .LVU214
+ 552:Src/usbd_conf.c **** 
+ 997              		.loc 1 552 3 view .LVU215
+ 552:Src/usbd_conf.c **** 
+ 998              		.loc 1 552 16 is_stmt 0 view .LVU216
+ 999 0002 D0F8C402 		ldr	r0, [r0, #708]
+ 1000              	.LVL95:
+ 552:Src/usbd_conf.c **** 
+ 1001              		.loc 1 552 16 view .LVU217
+ 1002 0006 FFF7FEFF 		bl	HAL_PCD_EP_Flush
+ 1003              	.LVL96:
+ 554:Src/usbd_conf.c **** 
+ 1004              		.loc 1 554 3 is_stmt 1 view .LVU218
+ 554:Src/usbd_conf.c **** 
+ 1005              		.loc 1 554 17 is_stmt 0 view .LVU219
+ 1006 000a FFF7FEFF 		bl	USBD_Get_USB_Status
+ 1007              	.LVL97:
+ 556:Src/usbd_conf.c **** }
+ 1008              		.loc 1 556 3 is_stmt 1 view .LVU220
+ 557:Src/usbd_conf.c **** 
+ 1009              		.loc 1 557 1 is_stmt 0 view .LVU221
+ 1010 000e 08BD     		pop	{r3, pc}
+ 1011              		.cfi_endproc
+ 1012              	.LFE352:
+ 1014              		.section	.text.USBD_LL_StallEP,"ax",%progbits
+ 1015              		.align	1
+ 1016              		.global	USBD_LL_StallEP
+ 1017              		.syntax unified
+ 1018              		.thumb
+ 1019              		.thumb_func
+ 1021              	USBD_LL_StallEP:
+ 1022              	.LVL98:
+ 1023              	.LFB353:
+ 566:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 1024              		.loc 1 566 1 is_stmt 1 view -0
+ 1025              		.cfi_startproc
+ 1026              		@ args = 0, pretend = 0, frame = 0
+ 1027              		@ frame_needed = 0, uses_anonymous_args = 0
+ 566:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 1028              		.loc 1 566 1 is_stmt 0 view .LVU223
+ 1029 0000 08B5     		push	{r3, lr}
+ARM GAS  /tmp/ccf5FGie.s 			page 36
+
+
+ 1030              	.LCFI24:
+ 1031              		.cfi_def_cfa_offset 8
+ 1032              		.cfi_offset 3, -8
+ 1033              		.cfi_offset 14, -4
+ 567:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 1034              		.loc 1 567 3 is_stmt 1 view .LVU224
+ 1035              	.LVL99:
+ 568:Src/usbd_conf.c **** 
+ 1036              		.loc 1 568 3 view .LVU225
+ 570:Src/usbd_conf.c **** 
+ 1037              		.loc 1 570 3 view .LVU226
+ 570:Src/usbd_conf.c **** 
+ 1038              		.loc 1 570 16 is_stmt 0 view .LVU227
+ 1039 0002 D0F8C402 		ldr	r0, [r0, #708]
+ 1040              	.LVL100:
+ 570:Src/usbd_conf.c **** 
+ 1041              		.loc 1 570 16 view .LVU228
+ 1042 0006 FFF7FEFF 		bl	HAL_PCD_EP_SetStall
+ 1043              	.LVL101:
+ 572:Src/usbd_conf.c **** 
+ 1044              		.loc 1 572 3 is_stmt 1 view .LVU229
+ 572:Src/usbd_conf.c **** 
+ 1045              		.loc 1 572 17 is_stmt 0 view .LVU230
+ 1046 000a FFF7FEFF 		bl	USBD_Get_USB_Status
+ 1047              	.LVL102:
+ 574:Src/usbd_conf.c **** }
+ 1048              		.loc 1 574 3 is_stmt 1 view .LVU231
+ 575:Src/usbd_conf.c **** 
+ 1049              		.loc 1 575 1 is_stmt 0 view .LVU232
+ 1050 000e 08BD     		pop	{r3, pc}
+ 1051              		.cfi_endproc
+ 1052              	.LFE353:
+ 1054              		.section	.text.USBD_LL_ClearStallEP,"ax",%progbits
+ 1055              		.align	1
+ 1056              		.global	USBD_LL_ClearStallEP
+ 1057              		.syntax unified
+ 1058              		.thumb
+ 1059              		.thumb_func
+ 1061              	USBD_LL_ClearStallEP:
+ 1062              	.LVL103:
+ 1063              	.LFB354:
+ 584:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 1064              		.loc 1 584 1 is_stmt 1 view -0
+ 1065              		.cfi_startproc
+ 1066              		@ args = 0, pretend = 0, frame = 0
+ 1067              		@ frame_needed = 0, uses_anonymous_args = 0
+ 584:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 1068              		.loc 1 584 1 is_stmt 0 view .LVU234
+ 1069 0000 08B5     		push	{r3, lr}
+ 1070              	.LCFI25:
+ 1071              		.cfi_def_cfa_offset 8
+ 1072              		.cfi_offset 3, -8
+ 1073              		.cfi_offset 14, -4
+ 585:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 1074              		.loc 1 585 3 is_stmt 1 view .LVU235
+ 1075              	.LVL104:
+ 586:Src/usbd_conf.c **** 
+ARM GAS  /tmp/ccf5FGie.s 			page 37
+
+
+ 1076              		.loc 1 586 3 view .LVU236
+ 588:Src/usbd_conf.c **** 
+ 1077              		.loc 1 588 3 view .LVU237
+ 588:Src/usbd_conf.c **** 
+ 1078              		.loc 1 588 16 is_stmt 0 view .LVU238
+ 1079 0002 D0F8C402 		ldr	r0, [r0, #708]
+ 1080              	.LVL105:
+ 588:Src/usbd_conf.c **** 
+ 1081              		.loc 1 588 16 view .LVU239
+ 1082 0006 FFF7FEFF 		bl	HAL_PCD_EP_ClrStall
+ 1083              	.LVL106:
+ 590:Src/usbd_conf.c **** 
+ 1084              		.loc 1 590 3 is_stmt 1 view .LVU240
+ 590:Src/usbd_conf.c **** 
+ 1085              		.loc 1 590 17 is_stmt 0 view .LVU241
+ 1086 000a FFF7FEFF 		bl	USBD_Get_USB_Status
+ 1087              	.LVL107:
+ 592:Src/usbd_conf.c **** }
+ 1088              		.loc 1 592 3 is_stmt 1 view .LVU242
+ 593:Src/usbd_conf.c **** 
+ 1089              		.loc 1 593 1 is_stmt 0 view .LVU243
+ 1090 000e 08BD     		pop	{r3, pc}
+ 1091              		.cfi_endproc
+ 1092              	.LFE354:
+ 1094              		.section	.text.USBD_LL_IsStallEP,"ax",%progbits
+ 1095              		.align	1
+ 1096              		.global	USBD_LL_IsStallEP
+ 1097              		.syntax unified
+ 1098              		.thumb
+ 1099              		.thumb_func
+ 1101              	USBD_LL_IsStallEP:
+ 1102              	.LVL108:
+ 1103              	.LFB355:
+ 602:Src/usbd_conf.c ****   PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
+ 1104              		.loc 1 602 1 is_stmt 1 view -0
+ 1105              		.cfi_startproc
+ 1106              		@ args = 0, pretend = 0, frame = 0
+ 1107              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1108              		@ link register save eliminated.
+ 603:Src/usbd_conf.c **** 
+ 1109              		.loc 1 603 3 view .LVU245
+ 603:Src/usbd_conf.c **** 
+ 1110              		.loc 1 603 22 is_stmt 0 view .LVU246
+ 1111 0000 D0F8C432 		ldr	r3, [r0, #708]
+ 1112              	.LVL109:
+ 605:Src/usbd_conf.c ****   {
+ 1113              		.loc 1 605 3 is_stmt 1 view .LVU247
+ 605:Src/usbd_conf.c ****   {
+ 1114              		.loc 1 605 5 is_stmt 0 view .LVU248
+ 1115 0004 11F0800F 		tst	r1, #128
+ 1116 0008 08D1     		bne	.L80
+ 611:Src/usbd_conf.c ****   }
+ 1117              		.loc 1 611 5 is_stmt 1 view .LVU249
+ 611:Src/usbd_conf.c ****   }
+ 1118              		.loc 1 611 33 is_stmt 0 view .LVU250
+ 1119 000a 01F07F01 		and	r1, r1, #127
+ 1120              	.LVL110:
+ARM GAS  /tmp/ccf5FGie.s 			page 38
+
+
+ 611:Src/usbd_conf.c ****   }
+ 1121              		.loc 1 611 40 view .LVU251
+ 1122 000e 01EB8101 		add	r1, r1, r1, lsl #2
+ 1123 0012 03EBC103 		add	r3, r3, r1, lsl #3
+ 1124              	.LVL111:
+ 611:Src/usbd_conf.c ****   }
+ 1125              		.loc 1 611 40 view .LVU252
+ 1126 0016 93F86A01 		ldrb	r0, [r3, #362]	@ zero_extendqisi2
+ 1127              	.LVL112:
+ 613:Src/usbd_conf.c **** 
+ 1128              		.loc 1 613 1 view .LVU253
+ 1129 001a 7047     		bx	lr
+ 1130              	.LVL113:
+ 1131              	.L80:
+ 607:Src/usbd_conf.c ****   }
+ 1132              		.loc 1 607 5 is_stmt 1 view .LVU254
+ 607:Src/usbd_conf.c ****   }
+ 1133              		.loc 1 607 32 is_stmt 0 view .LVU255
+ 1134 001c 01F07F01 		and	r1, r1, #127
+ 1135              	.LVL114:
+ 607:Src/usbd_conf.c ****   }
+ 1136              		.loc 1 607 39 view .LVU256
+ 1137 0020 0131     		adds	r1, r1, #1
+ 1138 0022 01EB8101 		add	r1, r1, r1, lsl #2
+ 1139 0026 03EBC103 		add	r3, r3, r1, lsl #3
+ 1140              	.LVL115:
+ 607:Src/usbd_conf.c ****   }
+ 1141              		.loc 1 607 39 view .LVU257
+ 1142 002a 9878     		ldrb	r0, [r3, #2]	@ zero_extendqisi2
+ 1143              	.LVL116:
+ 607:Src/usbd_conf.c ****   }
+ 1144              		.loc 1 607 39 view .LVU258
+ 1145 002c 7047     		bx	lr
+ 1146              		.cfi_endproc
+ 1147              	.LFE355:
+ 1149              		.section	.text.USBD_LL_SetUSBAddress,"ax",%progbits
+ 1150              		.align	1
+ 1151              		.global	USBD_LL_SetUSBAddress
+ 1152              		.syntax unified
+ 1153              		.thumb
+ 1154              		.thumb_func
+ 1156              	USBD_LL_SetUSBAddress:
+ 1157              	.LVL117:
+ 1158              	.LFB356:
+ 622:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 1159              		.loc 1 622 1 is_stmt 1 view -0
+ 1160              		.cfi_startproc
+ 1161              		@ args = 0, pretend = 0, frame = 0
+ 1162              		@ frame_needed = 0, uses_anonymous_args = 0
+ 622:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 1163              		.loc 1 622 1 is_stmt 0 view .LVU260
+ 1164 0000 08B5     		push	{r3, lr}
+ 1165              	.LCFI26:
+ 1166              		.cfi_def_cfa_offset 8
+ 1167              		.cfi_offset 3, -8
+ 1168              		.cfi_offset 14, -4
+ 623:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ARM GAS  /tmp/ccf5FGie.s 			page 39
+
+
+ 1169              		.loc 1 623 3 is_stmt 1 view .LVU261
+ 1170              	.LVL118:
+ 624:Src/usbd_conf.c **** 
+ 1171              		.loc 1 624 3 view .LVU262
+ 626:Src/usbd_conf.c **** 
+ 1172              		.loc 1 626 3 view .LVU263
+ 626:Src/usbd_conf.c **** 
+ 1173              		.loc 1 626 16 is_stmt 0 view .LVU264
+ 1174 0002 D0F8C402 		ldr	r0, [r0, #708]
+ 1175              	.LVL119:
+ 626:Src/usbd_conf.c **** 
+ 1176              		.loc 1 626 16 view .LVU265
+ 1177 0006 FFF7FEFF 		bl	HAL_PCD_SetAddress
+ 1178              	.LVL120:
+ 628:Src/usbd_conf.c **** 
+ 1179              		.loc 1 628 3 is_stmt 1 view .LVU266
+ 628:Src/usbd_conf.c **** 
+ 1180              		.loc 1 628 17 is_stmt 0 view .LVU267
+ 1181 000a FFF7FEFF 		bl	USBD_Get_USB_Status
+ 1182              	.LVL121:
+ 630:Src/usbd_conf.c **** }
+ 1183              		.loc 1 630 3 is_stmt 1 view .LVU268
+ 631:Src/usbd_conf.c **** 
+ 1184              		.loc 1 631 1 is_stmt 0 view .LVU269
+ 1185 000e 08BD     		pop	{r3, pc}
+ 1186              		.cfi_endproc
+ 1187              	.LFE356:
+ 1189              		.section	.text.USBD_LL_Transmit,"ax",%progbits
+ 1190              		.align	1
+ 1191              		.global	USBD_LL_Transmit
+ 1192              		.syntax unified
+ 1193              		.thumb
+ 1194              		.thumb_func
+ 1196              	USBD_LL_Transmit:
+ 1197              	.LVL122:
+ 1198              	.LFB357:
+ 642:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 1199              		.loc 1 642 1 is_stmt 1 view -0
+ 1200              		.cfi_startproc
+ 1201              		@ args = 0, pretend = 0, frame = 0
+ 1202              		@ frame_needed = 0, uses_anonymous_args = 0
+ 642:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 1203              		.loc 1 642 1 is_stmt 0 view .LVU271
+ 1204 0000 08B5     		push	{r3, lr}
+ 1205              	.LCFI27:
+ 1206              		.cfi_def_cfa_offset 8
+ 1207              		.cfi_offset 3, -8
+ 1208              		.cfi_offset 14, -4
+ 643:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 1209              		.loc 1 643 3 is_stmt 1 view .LVU272
+ 1210              	.LVL123:
+ 644:Src/usbd_conf.c **** 
+ 1211              		.loc 1 644 3 view .LVU273
+ 646:Src/usbd_conf.c **** 
+ 1212              		.loc 1 646 3 view .LVU274
+ 646:Src/usbd_conf.c **** 
+ 1213              		.loc 1 646 16 is_stmt 0 view .LVU275
+ARM GAS  /tmp/ccf5FGie.s 			page 40
+
+
+ 1214 0002 D0F8C402 		ldr	r0, [r0, #708]
+ 1215              	.LVL124:
+ 646:Src/usbd_conf.c **** 
+ 1216              		.loc 1 646 16 view .LVU276
+ 1217 0006 FFF7FEFF 		bl	HAL_PCD_EP_Transmit
+ 1218              	.LVL125:
+ 648:Src/usbd_conf.c **** 
+ 1219              		.loc 1 648 3 is_stmt 1 view .LVU277
+ 648:Src/usbd_conf.c **** 
+ 1220              		.loc 1 648 17 is_stmt 0 view .LVU278
+ 1221 000a FFF7FEFF 		bl	USBD_Get_USB_Status
+ 1222              	.LVL126:
+ 650:Src/usbd_conf.c **** }
+ 1223              		.loc 1 650 3 is_stmt 1 view .LVU279
+ 651:Src/usbd_conf.c **** 
+ 1224              		.loc 1 651 1 is_stmt 0 view .LVU280
+ 1225 000e 08BD     		pop	{r3, pc}
+ 1226              		.cfi_endproc
+ 1227              	.LFE357:
+ 1229              		.section	.text.USBD_LL_PrepareReceive,"ax",%progbits
+ 1230              		.align	1
+ 1231              		.global	USBD_LL_PrepareReceive
+ 1232              		.syntax unified
+ 1233              		.thumb
+ 1234              		.thumb_func
+ 1236              	USBD_LL_PrepareReceive:
+ 1237              	.LVL127:
+ 1238              	.LFB358:
+ 662:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 1239              		.loc 1 662 1 is_stmt 1 view -0
+ 1240              		.cfi_startproc
+ 1241              		@ args = 0, pretend = 0, frame = 0
+ 1242              		@ frame_needed = 0, uses_anonymous_args = 0
+ 662:Src/usbd_conf.c ****   HAL_StatusTypeDef hal_status = HAL_OK;
+ 1243              		.loc 1 662 1 is_stmt 0 view .LVU282
+ 1244 0000 08B5     		push	{r3, lr}
+ 1245              	.LCFI28:
+ 1246              		.cfi_def_cfa_offset 8
+ 1247              		.cfi_offset 3, -8
+ 1248              		.cfi_offset 14, -4
+ 663:Src/usbd_conf.c ****   USBD_StatusTypeDef usb_status = USBD_OK;
+ 1249              		.loc 1 663 3 is_stmt 1 view .LVU283
+ 1250              	.LVL128:
+ 664:Src/usbd_conf.c **** 
+ 1251              		.loc 1 664 3 view .LVU284
+ 666:Src/usbd_conf.c **** 
+ 1252              		.loc 1 666 3 view .LVU285
+ 666:Src/usbd_conf.c **** 
+ 1253              		.loc 1 666 16 is_stmt 0 view .LVU286
+ 1254 0002 D0F8C402 		ldr	r0, [r0, #708]
+ 1255              	.LVL129:
+ 666:Src/usbd_conf.c **** 
+ 1256              		.loc 1 666 16 view .LVU287
+ 1257 0006 FFF7FEFF 		bl	HAL_PCD_EP_Receive
+ 1258              	.LVL130:
+ 668:Src/usbd_conf.c **** 
+ 1259              		.loc 1 668 3 is_stmt 1 view .LVU288
+ARM GAS  /tmp/ccf5FGie.s 			page 41
+
+
+ 668:Src/usbd_conf.c **** 
+ 1260              		.loc 1 668 17 is_stmt 0 view .LVU289
+ 1261 000a FFF7FEFF 		bl	USBD_Get_USB_Status
+ 1262              	.LVL131:
+ 670:Src/usbd_conf.c **** }
+ 1263              		.loc 1 670 3 is_stmt 1 view .LVU290
+ 671:Src/usbd_conf.c **** 
+ 1264              		.loc 1 671 1 is_stmt 0 view .LVU291
+ 1265 000e 08BD     		pop	{r3, pc}
+ 1266              		.cfi_endproc
+ 1267              	.LFE358:
+ 1269              		.section	.text.USBD_LL_GetRxDataSize,"ax",%progbits
+ 1270              		.align	1
+ 1271              		.global	USBD_LL_GetRxDataSize
+ 1272              		.syntax unified
+ 1273              		.thumb
+ 1274              		.thumb_func
+ 1276              	USBD_LL_GetRxDataSize:
+ 1277              	.LVL132:
+ 1278              	.LFB359:
+ 680:Src/usbd_conf.c ****   return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
+ 1279              		.loc 1 680 1 is_stmt 1 view -0
+ 1280              		.cfi_startproc
+ 1281              		@ args = 0, pretend = 0, frame = 0
+ 1282              		@ frame_needed = 0, uses_anonymous_args = 0
+ 680:Src/usbd_conf.c ****   return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
+ 1283              		.loc 1 680 1 is_stmt 0 view .LVU293
+ 1284 0000 08B5     		push	{r3, lr}
+ 1285              	.LCFI29:
+ 1286              		.cfi_def_cfa_offset 8
+ 1287              		.cfi_offset 3, -8
+ 1288              		.cfi_offset 14, -4
+ 681:Src/usbd_conf.c **** }
+ 1289              		.loc 1 681 3 is_stmt 1 view .LVU294
+ 681:Src/usbd_conf.c **** }
+ 1290              		.loc 1 681 10 is_stmt 0 view .LVU295
+ 1291 0002 D0F8C402 		ldr	r0, [r0, #708]
+ 1292              	.LVL133:
+ 681:Src/usbd_conf.c **** }
+ 1293              		.loc 1 681 10 view .LVU296
+ 1294 0006 FFF7FEFF 		bl	HAL_PCD_EP_GetRxCount
+ 1295              	.LVL134:
+ 682:Src/usbd_conf.c **** 
+ 1296              		.loc 1 682 1 view .LVU297
+ 1297 000a 08BD     		pop	{r3, pc}
+ 1298              		.cfi_endproc
+ 1299              	.LFE359:
+ 1301              		.section	.text.HAL_PCDEx_LPM_Callback,"ax",%progbits
+ 1302              		.align	1
+ 1303              		.global	HAL_PCDEx_LPM_Callback
+ 1304              		.syntax unified
+ 1305              		.thumb
+ 1306              		.thumb_func
+ 1308              	HAL_PCDEx_LPM_Callback:
+ 1309              	.LVL135:
+ 1310              	.LFB360:
+ 695:Src/usbd_conf.c ****   /* USER CODE BEGIN LPM_Callback */
+ARM GAS  /tmp/ccf5FGie.s 			page 42
+
+
+ 1311              		.loc 1 695 1 is_stmt 1 view -0
+ 1312              		.cfi_startproc
+ 1313              		@ args = 0, pretend = 0, frame = 0
+ 1314              		@ frame_needed = 0, uses_anonymous_args = 0
+ 695:Src/usbd_conf.c ****   /* USER CODE BEGIN LPM_Callback */
+ 1315              		.loc 1 695 1 is_stmt 0 view .LVU299
+ 1316 0000 10B5     		push	{r4, lr}
+ 1317              	.LCFI30:
+ 1318              		.cfi_def_cfa_offset 8
+ 1319              		.cfi_offset 4, -8
+ 1320              		.cfi_offset 14, -4
+ 1321 0002 0446     		mov	r4, r0
+ 697:Src/usbd_conf.c ****   {
+ 1322              		.loc 1 697 3 is_stmt 1 view .LVU300
+ 1323 0004 11B1     		cbz	r1, .L90
+ 1324 0006 0129     		cmp	r1, #1
+ 1325 0008 0FD0     		beq	.L91
+ 1326              	.LVL136:
+ 1327              	.L89:
+ 722:Src/usbd_conf.c **** 
+ 1328              		.loc 1 722 1 is_stmt 0 view .LVU301
+ 1329 000a 10BD     		pop	{r4, pc}
+ 1330              	.LVL137:
+ 1331              	.L90:
+ 700:Src/usbd_conf.c ****     {
+ 1332              		.loc 1 700 5 is_stmt 1 view .LVU302
+ 700:Src/usbd_conf.c ****     {
+ 1333              		.loc 1 700 19 is_stmt 0 view .LVU303
+ 1334 000c 8369     		ldr	r3, [r0, #24]
+ 700:Src/usbd_conf.c ****     {
+ 1335              		.loc 1 700 8 view .LVU304
+ 1336 000e 23B9     		cbnz	r3, .L95
+ 1337              	.LVL138:
+ 1338              	.L93:
+ 707:Src/usbd_conf.c ****     break;
+ 1339              		.loc 1 707 5 is_stmt 1 view .LVU305
+ 1340 0010 D4F8F002 		ldr	r0, [r4, #752]
+ 1341 0014 FFF7FEFF 		bl	USBD_LL_Resume
+ 1342              	.LVL139:
+ 708:Src/usbd_conf.c **** 
+ 1343              		.loc 1 708 5 view .LVU306
+ 1344 0018 F7E7     		b	.L89
+ 1345              	.LVL140:
+ 1346              	.L95:
+ 702:Src/usbd_conf.c **** 
+ 1347              		.loc 1 702 7 view .LVU307
+ 1348 001a FFF7FEFF 		bl	SystemClockConfig_Resume
+ 1349              	.LVL141:
+ 705:Src/usbd_conf.c ****     }
+ 1350              		.loc 1 705 7 view .LVU308
+ 705:Src/usbd_conf.c ****     }
+ 1351              		.loc 1 705 10 is_stmt 0 view .LVU309
+ 1352 001e 094A     		ldr	r2, .L96
+ 1353 0020 1369     		ldr	r3, [r2, #16]
+ 705:Src/usbd_conf.c ****     }
+ 1354              		.loc 1 705 16 view .LVU310
+ 1355 0022 23F00603 		bic	r3, r3, #6
+ARM GAS  /tmp/ccf5FGie.s 			page 43
+
+
+ 1356 0026 1361     		str	r3, [r2, #16]
+ 1357 0028 F2E7     		b	.L93
+ 1358              	.LVL142:
+ 1359              	.L91:
+ 711:Src/usbd_conf.c **** 
+ 1360              		.loc 1 711 5 is_stmt 1 view .LVU311
+ 1361 002a D0F8F002 		ldr	r0, [r0, #752]
+ 1362              	.LVL143:
+ 711:Src/usbd_conf.c **** 
+ 1363              		.loc 1 711 5 is_stmt 0 view .LVU312
+ 1364 002e FFF7FEFF 		bl	USBD_LL_Suspend
+ 1365              	.LVL144:
+ 714:Src/usbd_conf.c ****     {
+ 1366              		.loc 1 714 5 is_stmt 1 view .LVU313
+ 714:Src/usbd_conf.c ****     {
+ 1367              		.loc 1 714 19 is_stmt 0 view .LVU314
+ 1368 0032 A369     		ldr	r3, [r4, #24]
+ 714:Src/usbd_conf.c ****     {
+ 1369              		.loc 1 714 8 view .LVU315
+ 1370 0034 002B     		cmp	r3, #0
+ 1371 0036 E8D0     		beq	.L89
+ 717:Src/usbd_conf.c ****     }
+ 1372              		.loc 1 717 7 is_stmt 1 view .LVU316
+ 717:Src/usbd_conf.c ****     }
+ 1373              		.loc 1 717 10 is_stmt 0 view .LVU317
+ 1374 0038 024A     		ldr	r2, .L96
+ 1375 003a 1369     		ldr	r3, [r2, #16]
+ 717:Src/usbd_conf.c ****     }
+ 1376              		.loc 1 717 16 view .LVU318
+ 1377 003c 43F00603 		orr	r3, r3, #6
+ 1378 0040 1361     		str	r3, [r2, #16]
+ 722:Src/usbd_conf.c **** 
+ 1379              		.loc 1 722 1 view .LVU319
+ 1380 0042 E2E7     		b	.L89
+ 1381              	.L97:
+ 1382              		.align	2
+ 1383              	.L96:
+ 1384 0044 00ED00E0 		.word	-536810240
+ 1385              		.cfi_endproc
+ 1386              	.LFE360:
+ 1388              		.section	.text.USBD_LL_Delay,"ax",%progbits
+ 1389              		.align	1
+ 1390              		.global	USBD_LL_Delay
+ 1391              		.syntax unified
+ 1392              		.thumb
+ 1393              		.thumb_func
+ 1395              	USBD_LL_Delay:
+ 1396              	.LVL145:
+ 1397              	.LFB361:
+ 730:Src/usbd_conf.c ****   HAL_Delay(Delay);
+ 1398              		.loc 1 730 1 is_stmt 1 view -0
+ 1399              		.cfi_startproc
+ 1400              		@ args = 0, pretend = 0, frame = 0
+ 1401              		@ frame_needed = 0, uses_anonymous_args = 0
+ 730:Src/usbd_conf.c ****   HAL_Delay(Delay);
+ 1402              		.loc 1 730 1 is_stmt 0 view .LVU321
+ 1403 0000 08B5     		push	{r3, lr}
+ARM GAS  /tmp/ccf5FGie.s 			page 44
+
+
+ 1404              	.LCFI31:
+ 1405              		.cfi_def_cfa_offset 8
+ 1406              		.cfi_offset 3, -8
+ 1407              		.cfi_offset 14, -4
+ 731:Src/usbd_conf.c **** }
+ 1408              		.loc 1 731 3 is_stmt 1 view .LVU322
+ 1409 0002 FFF7FEFF 		bl	HAL_Delay
+ 1410              	.LVL146:
+ 732:Src/usbd_conf.c **** 
+ 1411              		.loc 1 732 1 is_stmt 0 view .LVU323
+ 1412 0006 08BD     		pop	{r3, pc}
+ 1413              		.cfi_endproc
+ 1414              	.LFE361:
+ 1416              		.section	.text.USBD_static_malloc,"ax",%progbits
+ 1417              		.align	1
+ 1418              		.global	USBD_static_malloc
+ 1419              		.syntax unified
+ 1420              		.thumb
+ 1421              		.thumb_func
+ 1423              	USBD_static_malloc:
+ 1424              	.LVL147:
+ 1425              	.LFB362:
+ 740:Src/usbd_conf.c ****   static uint32_t mem[(sizeof(USBD_AUDIO_HandleTypeDef)/4)+1];/* On 32-bit boundary */
+ 1426              		.loc 1 740 1 is_stmt 1 view -0
+ 1427              		.cfi_startproc
+ 1428              		@ args = 0, pretend = 0, frame = 0
+ 1429              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1430              		@ link register save eliminated.
+ 741:Src/usbd_conf.c ****   return mem;
+ 1431              		.loc 1 741 3 view .LVU325
+ 742:Src/usbd_conf.c **** }
+ 1432              		.loc 1 742 3 view .LVU326
+ 743:Src/usbd_conf.c **** 
+ 1433              		.loc 1 743 1 is_stmt 0 view .LVU327
+ 1434 0000 0048     		ldr	r0, .L101
+ 1435              	.LVL148:
+ 743:Src/usbd_conf.c **** 
+ 1436              		.loc 1 743 1 view .LVU328
+ 1437 0002 7047     		bx	lr
+ 1438              	.L102:
+ 1439              		.align	2
+ 1440              	.L101:
+ 1441 0004 00000000 		.word	mem.0
+ 1442              		.cfi_endproc
+ 1443              	.LFE362:
+ 1445              		.section	.text.USBD_static_free,"ax",%progbits
+ 1446              		.align	1
+ 1447              		.global	USBD_static_free
+ 1448              		.syntax unified
+ 1449              		.thumb
+ 1450              		.thumb_func
+ 1452              	USBD_static_free:
+ 1453              	.LVL149:
+ 1454              	.LFB363:
+ 751:Src/usbd_conf.c **** 
+ 1455              		.loc 1 751 1 is_stmt 1 view -0
+ 1456              		.cfi_startproc
+ARM GAS  /tmp/ccf5FGie.s 			page 45
+
+
+ 1457              		@ args = 0, pretend = 0, frame = 0
+ 1458              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1459              		@ link register save eliminated.
+ 753:Src/usbd_conf.c **** 
+ 1460              		.loc 1 753 1 view .LVU330
+ 1461 0000 7047     		bx	lr
+ 1462              		.cfi_endproc
+ 1463              	.LFE363:
+ 1465              		.section	.bss.mem.0,"aw",%nobits
+ 1466              		.align	2
+ 1469              	mem.0:
+ 1470 0000 00000000 		.space	7124
+ 1470      00000000 
+ 1470      00000000 
+ 1470      00000000 
+ 1470      00000000 
+ 1471              		.global	hpcd_USB_FS
+ 1472              		.section	.bss.hpcd_USB_FS,"aw",%nobits
+ 1473              		.align	2
+ 1476              	hpcd_USB_FS:
+ 1477 0000 00000000 		.space	756
+ 1477      00000000 
+ 1477      00000000 
+ 1477      00000000 
+ 1477      00000000 
+ 1478              		.text
+ 1479              	.Letext0:
+ 1480              		.file 2 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
+ 1481              		.file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
+ 1482              		.file 4 "Drivers/CMSIS/Include/core_cm4.h"
+ 1483              		.file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
+ 1484              		.file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
+ 1485              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"
+ 1486              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h"
+ 1487              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h"
+ 1488              		.file 10 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h"
+ 1489              		.file 11 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h"
+ 1490              		.file 12 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h"
+ 1491              		.file 13 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
+ 1492              		.file 14 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"
+ 1493              		.file 15 "<built-in>"
+ARM GAS  /tmp/ccf5FGie.s 			page 46
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 usbd_conf.c
+     /tmp/ccf5FGie.s:21     .text.USBD_Get_USB_Status:00000000 $t
+     /tmp/ccf5FGie.s:26     .text.USBD_Get_USB_Status:00000000 USBD_Get_USB_Status
+     /tmp/ccf5FGie.s:40     .text.USBD_Get_USB_Status:00000008 $d
+     /tmp/ccf5FGie.s:44     .text.USBD_Get_USB_Status:0000000c $t
+     /tmp/ccf5FGie.s:67     .text.SystemClockConfig_Resume:00000000 $t
+     /tmp/ccf5FGie.s:72     .text.SystemClockConfig_Resume:00000000 SystemClockConfig_Resume
+     /tmp/ccf5FGie.s:92     .text.HAL_PCD_MspInit:00000000 $t
+     /tmp/ccf5FGie.s:98     .text.HAL_PCD_MspInit:00000000 HAL_PCD_MspInit
+     /tmp/ccf5FGie.s:192    .text.HAL_PCD_MspInit:00000058 $d
+     /tmp/ccf5FGie.s:198    .text.HAL_PCD_MspDeInit:00000000 $t
+     /tmp/ccf5FGie.s:204    .text.HAL_PCD_MspDeInit:00000000 HAL_PCD_MspDeInit
+     /tmp/ccf5FGie.s:246    .text.HAL_PCD_MspDeInit:00000020 $d
+     /tmp/ccf5FGie.s:252    .text.HAL_PCD_SetupStageCallback:00000000 $t
+     /tmp/ccf5FGie.s:258    .text.HAL_PCD_SetupStageCallback:00000000 HAL_PCD_SetupStageCallback
+     /tmp/ccf5FGie.s:284    .text.HAL_PCD_DataOutStageCallback:00000000 $t
+     /tmp/ccf5FGie.s:290    .text.HAL_PCD_DataOutStageCallback:00000000 HAL_PCD_DataOutStageCallback
+     /tmp/ccf5FGie.s:318    .text.HAL_PCD_DataInStageCallback:00000000 $t
+     /tmp/ccf5FGie.s:324    .text.HAL_PCD_DataInStageCallback:00000000 HAL_PCD_DataInStageCallback
+     /tmp/ccf5FGie.s:352    .text.HAL_PCD_SOFCallback:00000000 $t
+     /tmp/ccf5FGie.s:358    .text.HAL_PCD_SOFCallback:00000000 HAL_PCD_SOFCallback
+     /tmp/ccf5FGie.s:383    .text.HAL_PCD_ResetCallback:00000000 $t
+     /tmp/ccf5FGie.s:389    .text.HAL_PCD_ResetCallback:00000000 HAL_PCD_ResetCallback
+     /tmp/ccf5FGie.s:435    .text.HAL_PCD_SuspendCallback:00000000 $t
+     /tmp/ccf5FGie.s:441    .text.HAL_PCD_SuspendCallback:00000000 HAL_PCD_SuspendCallback
+     /tmp/ccf5FGie.s:481    .text.HAL_PCD_SuspendCallback:0000001c $d
+     /tmp/ccf5FGie.s:486    .text.HAL_PCD_ResumeCallback:00000000 $t
+     /tmp/ccf5FGie.s:492    .text.HAL_PCD_ResumeCallback:00000000 HAL_PCD_ResumeCallback
+     /tmp/ccf5FGie.s:536    .text.HAL_PCD_ResumeCallback:00000024 $d
+     /tmp/ccf5FGie.s:541    .text.HAL_PCD_ISOOUTIncompleteCallback:00000000 $t
+     /tmp/ccf5FGie.s:547    .text.HAL_PCD_ISOOUTIncompleteCallback:00000000 HAL_PCD_ISOOUTIncompleteCallback
+     /tmp/ccf5FGie.s:572    .text.HAL_PCD_ISOINIncompleteCallback:00000000 $t
+     /tmp/ccf5FGie.s:578    .text.HAL_PCD_ISOINIncompleteCallback:00000000 HAL_PCD_ISOINIncompleteCallback
+     /tmp/ccf5FGie.s:603    .text.HAL_PCD_ConnectCallback:00000000 $t
+     /tmp/ccf5FGie.s:609    .text.HAL_PCD_ConnectCallback:00000000 HAL_PCD_ConnectCallback
+     /tmp/ccf5FGie.s:634    .text.HAL_PCD_DisconnectCallback:00000000 $t
+     /tmp/ccf5FGie.s:640    .text.HAL_PCD_DisconnectCallback:00000000 HAL_PCD_DisconnectCallback
+     /tmp/ccf5FGie.s:665    .text.USBD_LL_Init:00000000 $t
+     /tmp/ccf5FGie.s:671    .text.USBD_LL_Init:00000000 USBD_LL_Init
+     /tmp/ccf5FGie.s:763    .text.USBD_LL_Init:00000060 $d
+     /tmp/ccf5FGie.s:1476   .bss.hpcd_USB_FS:00000000 hpcd_USB_FS
+     /tmp/ccf5FGie.s:770    .text.USBD_LL_DeInit:00000000 $t
+     /tmp/ccf5FGie.s:776    .text.USBD_LL_DeInit:00000000 USBD_LL_DeInit
+     /tmp/ccf5FGie.s:810    .text.USBD_LL_Start:00000000 $t
+     /tmp/ccf5FGie.s:816    .text.USBD_LL_Start:00000000 USBD_LL_Start
+     /tmp/ccf5FGie.s:850    .text.USBD_LL_Stop:00000000 $t
+     /tmp/ccf5FGie.s:856    .text.USBD_LL_Stop:00000000 USBD_LL_Stop
+     /tmp/ccf5FGie.s:890    .text.USBD_LL_OpenEP:00000000 $t
+     /tmp/ccf5FGie.s:896    .text.USBD_LL_OpenEP:00000000 USBD_LL_OpenEP
+     /tmp/ccf5FGie.s:935    .text.USBD_LL_CloseEP:00000000 $t
+     /tmp/ccf5FGie.s:941    .text.USBD_LL_CloseEP:00000000 USBD_LL_CloseEP
+     /tmp/ccf5FGie.s:975    .text.USBD_LL_FlushEP:00000000 $t
+     /tmp/ccf5FGie.s:981    .text.USBD_LL_FlushEP:00000000 USBD_LL_FlushEP
+     /tmp/ccf5FGie.s:1015   .text.USBD_LL_StallEP:00000000 $t
+     /tmp/ccf5FGie.s:1021   .text.USBD_LL_StallEP:00000000 USBD_LL_StallEP
+     /tmp/ccf5FGie.s:1055   .text.USBD_LL_ClearStallEP:00000000 $t
+ARM GAS  /tmp/ccf5FGie.s 			page 47
+
+
+     /tmp/ccf5FGie.s:1061   .text.USBD_LL_ClearStallEP:00000000 USBD_LL_ClearStallEP
+     /tmp/ccf5FGie.s:1095   .text.USBD_LL_IsStallEP:00000000 $t
+     /tmp/ccf5FGie.s:1101   .text.USBD_LL_IsStallEP:00000000 USBD_LL_IsStallEP
+     /tmp/ccf5FGie.s:1150   .text.USBD_LL_SetUSBAddress:00000000 $t
+     /tmp/ccf5FGie.s:1156   .text.USBD_LL_SetUSBAddress:00000000 USBD_LL_SetUSBAddress
+     /tmp/ccf5FGie.s:1190   .text.USBD_LL_Transmit:00000000 $t
+     /tmp/ccf5FGie.s:1196   .text.USBD_LL_Transmit:00000000 USBD_LL_Transmit
+     /tmp/ccf5FGie.s:1230   .text.USBD_LL_PrepareReceive:00000000 $t
+     /tmp/ccf5FGie.s:1236   .text.USBD_LL_PrepareReceive:00000000 USBD_LL_PrepareReceive
+     /tmp/ccf5FGie.s:1270   .text.USBD_LL_GetRxDataSize:00000000 $t
+     /tmp/ccf5FGie.s:1276   .text.USBD_LL_GetRxDataSize:00000000 USBD_LL_GetRxDataSize
+     /tmp/ccf5FGie.s:1302   .text.HAL_PCDEx_LPM_Callback:00000000 $t
+     /tmp/ccf5FGie.s:1308   .text.HAL_PCDEx_LPM_Callback:00000000 HAL_PCDEx_LPM_Callback
+     /tmp/ccf5FGie.s:1384   .text.HAL_PCDEx_LPM_Callback:00000044 $d
+     /tmp/ccf5FGie.s:1389   .text.USBD_LL_Delay:00000000 $t
+     /tmp/ccf5FGie.s:1395   .text.USBD_LL_Delay:00000000 USBD_LL_Delay
+     /tmp/ccf5FGie.s:1417   .text.USBD_static_malloc:00000000 $t
+     /tmp/ccf5FGie.s:1423   .text.USBD_static_malloc:00000000 USBD_static_malloc
+     /tmp/ccf5FGie.s:1441   .text.USBD_static_malloc:00000004 $d
+     /tmp/ccf5FGie.s:1469   .bss.mem.0:00000000 mem.0
+     /tmp/ccf5FGie.s:1446   .text.USBD_static_free:00000000 $t
+     /tmp/ccf5FGie.s:1452   .text.USBD_static_free:00000000 USBD_static_free
+     /tmp/ccf5FGie.s:1466   .bss.mem.0:00000000 $d
+     /tmp/ccf5FGie.s:1473   .bss.hpcd_USB_FS:00000000 $d
+
+UNDEFINED SYMBOLS
+SystemClock_Config
+memset
+HAL_RCCEx_PeriphCLKConfig
+HAL_NVIC_SetPriority
+HAL_NVIC_EnableIRQ
+Error_Handler
+HAL_NVIC_DisableIRQ
+USBD_LL_SetupStage
+USBD_LL_DataOutStage
+USBD_LL_DataInStage
+USBD_LL_SOF
+USBD_LL_SetSpeed
+USBD_LL_Reset
+USBD_LL_Suspend
+USBD_LL_Resume
+USBD_LL_IsoOUTIncomplete
+USBD_LL_IsoINIncomplete
+USBD_LL_DevConnected
+USBD_LL_DevDisconnected
+HAL_PCD_Init
+HAL_PCDEx_PMAConfig
+HAL_PCD_DeInit
+HAL_PCD_Start
+HAL_PCD_Stop
+HAL_PCD_EP_Open
+HAL_PCD_EP_Close
+HAL_PCD_EP_Flush
+HAL_PCD_EP_SetStall
+HAL_PCD_EP_ClrStall
+HAL_PCD_SetAddress
+HAL_PCD_EP_Transmit
+ARM GAS  /tmp/ccf5FGie.s 			page 48
+
+
+HAL_PCD_EP_Receive
+HAL_PCD_EP_GetRxCount
+HAL_Delay
diff --git a/squeow_sw/build/usbd_conf.o b/squeow_sw/build/usbd_conf.o
new file mode 100644
index 0000000000000000000000000000000000000000..56e88fbacf4dd9bcf820435fd908757763e2f1d3
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diff --git a/squeow_sw/build/usbd_core.d b/squeow_sw/build/usbd_core.d
new file mode 100644
index 0000000..bf6340a
--- /dev/null
+++ b/squeow_sw/build/usbd_core.d
@@ -0,0 +1,85 @@
+build/usbd_core.o: \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \
+ Inc/usbd_conf.h Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h:
+Inc/usbd_conf.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h:
diff --git a/squeow_sw/build/usbd_core.lst b/squeow_sw/build/usbd_core.lst
new file mode 100644
index 0000000..e3e1776
--- /dev/null
+++ b/squeow_sw/build/usbd_core.lst
@@ -0,0 +1,2360 @@
+ARM GAS  /tmp/ccXNKvGT.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"usbd_core.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c"
+  20              		.section	.text.USBD_Init,"ax",%progbits
+  21              		.align	1
+  22              		.global	USBD_Init
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	USBD_Init:
+  28              	.LVL0:
+  29              	.LFB333:
+   1:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+   2:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   ******************************************************************************
+   3:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @file    usbd_core.c
+   4:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @author  MCD Application Team
+   5:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief   This file provides all the USBD core functions.
+   6:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   ******************************************************************************
+   7:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @attention
+   8:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *
+   9:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  10:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * All rights reserved.</center></h2>
+  11:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *
+  12:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * This software component is licensed by ST under Ultimate Liberty license
+  13:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * SLA0044, the "License"; You may not use this file except in compliance with
+  14:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * the License. You may obtain a copy of the License at:
+  15:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *                      www.st.com/SLA0044
+  16:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *
+  17:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   ******************************************************************************
+  18:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  19:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  20:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Includes ------------------------------------------------------------------*/
+  21:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #include "usbd_core.h"
+  22:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  23:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @addtogroup STM32_USBD_DEVICE_LIBRARY
+  24:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @{
+  25:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  26:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  27:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  28:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE
+  29:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief usbd core module
+ARM GAS  /tmp/ccXNKvGT.s 			page 2
+
+
+  30:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @{
+  31:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  32:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  33:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE_Private_TypesDefinitions
+  34:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @{
+  35:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  36:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  37:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+  38:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @}
+  39:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  40:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  41:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  42:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE_Private_Defines
+  43:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @{
+  44:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  45:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  46:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+  47:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @}
+  48:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  49:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  50:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  51:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE_Private_Macros
+  52:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @{
+  53:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  54:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  55:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+  56:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @}
+  57:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  58:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  59:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  60:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE_Private_FunctionPrototypes
+  61:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @{
+  62:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  63:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  64:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+  65:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @}
+  66:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  67:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  68:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE_Private_Variables
+  69:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @{
+  70:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  71:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  72:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+  73:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @}
+  74:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  75:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  76:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  77:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE_Private_Functions
+  78:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @{
+  79:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  80:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  81:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+  82:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_Init
+  83:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Initializes the device stack and load the class driver
+  84:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+  85:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdesc: Descriptor structure address
+  86:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  id: Low level core index
+ARM GAS  /tmp/ccXNKvGT.s 			page 3
+
+
+  87:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval None
+  88:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+  89:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
+  90:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****                              USBD_DescriptorsTypeDef *pdesc, uint8_t id)
+  91:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+  30              		.loc 1 91 1 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  92:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   USBD_StatusTypeDef ret;
+  34              		.loc 1 92 3 view .LVU1
+  93:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+  94:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Check whether the USB Host handle is valid */
+  95:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev == NULL)
+  35              		.loc 1 95 3 view .LVU2
+  36              		.loc 1 95 6 is_stmt 0 view .LVU3
+  37 0000 98B1     		cbz	r0, .L4
+  91:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   USBD_StatusTypeDef ret;
+  38              		.loc 1 91 1 view .LVU4
+  39 0002 08B5     		push	{r3, lr}
+  40              	.LCFI0:
+  41              		.cfi_def_cfa_offset 8
+  42              		.cfi_offset 3, -8
+  43              		.cfi_offset 14, -4
+  44 0004 0346     		mov	r3, r0
+  96:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+  97:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #if (USBD_DEBUG_LEVEL > 1U)
+  98:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     USBD_ErrLog("Invalid Device handle");
+  99:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #endif
+ 100:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     return USBD_FAIL;
+ 101:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 102:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 103:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Unlink previous class resources */
+ 104:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->pClass = NULL;
+  45              		.loc 1 104 3 is_stmt 1 view .LVU5
+  46              		.loc 1 104 16 is_stmt 0 view .LVU6
+  47 0006 0020     		movs	r0, #0
+  48              	.LVL1:
+  49              		.loc 1 104 16 view .LVU7
+  50 0008 C3F8B802 		str	r0, [r3, #696]
+ 105:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->pUserData = NULL;
+  51              		.loc 1 105 3 is_stmt 1 view .LVU8
+  52              		.loc 1 105 19 is_stmt 0 view .LVU9
+  53 000c C3F8C002 		str	r0, [r3, #704]
+ 106:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->pConfDesc = NULL;
+  54              		.loc 1 106 3 is_stmt 1 view .LVU10
+  55              		.loc 1 106 19 is_stmt 0 view .LVU11
+  56 0010 C3F8CC02 		str	r0, [r3, #716]
+ 107:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Assign USBD Descriptors */
+ 109:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdesc != NULL)
+  57              		.loc 1 109 3 is_stmt 1 view .LVU12
+  58              		.loc 1 109 6 is_stmt 0 view .LVU13
+  59 0014 09B1     		cbz	r1, .L3
+ 110:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 111:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     pdev->pDesc = pdesc;
+  60              		.loc 1 111 5 is_stmt 1 view .LVU14
+ARM GAS  /tmp/ccXNKvGT.s 			page 4
+
+
+  61              		.loc 1 111 17 is_stmt 0 view .LVU15
+  62 0016 C3F8B412 		str	r1, [r3, #692]
+  63              	.L3:
+ 112:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 113:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 114:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Set Device initial State */
+ 115:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->dev_state = USBD_STATE_DEFAULT;
+  64              		.loc 1 115 3 is_stmt 1 view .LVU16
+  65              		.loc 1 115 19 is_stmt 0 view .LVU17
+  66 001a 0121     		movs	r1, #1
+  67              	.LVL2:
+  68              		.loc 1 115 19 view .LVU18
+  69 001c 83F89C12 		strb	r1, [r3, #668]
+ 116:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->id = id;
+  70              		.loc 1 116 3 is_stmt 1 view .LVU19
+  71              		.loc 1 116 12 is_stmt 0 view .LVU20
+  72 0020 1A70     		strb	r2, [r3]
+ 117:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 118:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Initialize low level driver */
+ 119:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   ret = USBD_LL_Init(pdev);
+  73              		.loc 1 119 3 is_stmt 1 view .LVU21
+  74              		.loc 1 119 9 is_stmt 0 view .LVU22
+  75 0022 1846     		mov	r0, r3
+  76 0024 FFF7FEFF 		bl	USBD_LL_Init
+  77              	.LVL3:
+ 120:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 121:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return ret;
+  78              		.loc 1 121 3 is_stmt 1 view .LVU23
+ 122:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+  79              		.loc 1 122 1 is_stmt 0 view .LVU24
+  80 0028 08BD     		pop	{r3, pc}
+  81              	.LVL4:
+  82              	.L4:
+  83              	.LCFI1:
+  84              		.cfi_def_cfa_offset 0
+  85              		.cfi_restore 3
+  86              		.cfi_restore 14
+ 100:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+  87              		.loc 1 100 12 view .LVU25
+  88 002a 0320     		movs	r0, #3
+  89              	.LVL5:
+  90              		.loc 1 122 1 view .LVU26
+  91 002c 7047     		bx	lr
+  92              		.cfi_endproc
+  93              	.LFE333:
+  95              		.section	.text.USBD_DeInit,"ax",%progbits
+  96              		.align	1
+  97              		.global	USBD_DeInit
+  98              		.syntax unified
+  99              		.thumb
+ 100              		.thumb_func
+ 102              	USBD_DeInit:
+ 103              	.LVL6:
+ 104              	.LFB334:
+ 123:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 124:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 125:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_DeInit
+ARM GAS  /tmp/ccXNKvGT.s 			page 5
+
+
+ 126:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Re-Initialize the device library
+ 127:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 128:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status: status
+ 129:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 130:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
+ 131:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 105              		.loc 1 131 1 is_stmt 1 view -0
+ 106              		.cfi_startproc
+ 107              		@ args = 0, pretend = 0, frame = 0
+ 108              		@ frame_needed = 0, uses_anonymous_args = 0
+ 109              		.loc 1 131 1 is_stmt 0 view .LVU28
+ 110 0000 10B5     		push	{r4, lr}
+ 111              	.LCFI2:
+ 112              		.cfi_def_cfa_offset 8
+ 113              		.cfi_offset 4, -8
+ 114              		.cfi_offset 14, -4
+ 115 0002 0446     		mov	r4, r0
+ 132:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   USBD_StatusTypeDef ret;
+ 116              		.loc 1 132 3 is_stmt 1 view .LVU29
+ 133:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 134:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Disconnect the USB Device */
+ 135:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   (void)USBD_LL_Stop(pdev);
+ 117              		.loc 1 135 3 view .LVU30
+ 118              		.loc 1 135 9 is_stmt 0 view .LVU31
+ 119 0004 FFF7FEFF 		bl	USBD_LL_Stop
+ 120              	.LVL7:
+ 136:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 137:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Set Default State */
+ 138:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->dev_state = USBD_STATE_DEFAULT;
+ 121              		.loc 1 138 3 is_stmt 1 view .LVU32
+ 122              		.loc 1 138 19 is_stmt 0 view .LVU33
+ 123 0008 0123     		movs	r3, #1
+ 124 000a 84F89C32 		strb	r3, [r4, #668]
+ 139:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 140:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Free Class Resources */
+ 141:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass != NULL)
+ 125              		.loc 1 141 3 is_stmt 1 view .LVU34
+ 126              		.loc 1 141 11 is_stmt 0 view .LVU35
+ 127 000e D4F8B832 		ldr	r3, [r4, #696]
+ 128              		.loc 1 141 6 view .LVU36
+ 129 0012 43B1     		cbz	r3, .L10
+ 142:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 143:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+ 130              		.loc 1 143 5 is_stmt 1 view .LVU37
+ 131              		.loc 1 143 17 is_stmt 0 view .LVU38
+ 132 0014 5B68     		ldr	r3, [r3, #4]
+ 133              		.loc 1 143 5 view .LVU39
+ 134 0016 2179     		ldrb	r1, [r4, #4]	@ zero_extendqisi2
+ 135 0018 2046     		mov	r0, r4
+ 136 001a 9847     		blx	r3
+ 137              	.LVL8:
+ 144:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     pdev->pClass = NULL;
+ 138              		.loc 1 144 5 is_stmt 1 view .LVU40
+ 139              		.loc 1 144 18 is_stmt 0 view .LVU41
+ 140 001c 0023     		movs	r3, #0
+ 141 001e C4F8B832 		str	r3, [r4, #696]
+ 145:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     pdev->pUserData = NULL;
+ARM GAS  /tmp/ccXNKvGT.s 			page 6
+
+
+ 142              		.loc 1 145 5 is_stmt 1 view .LVU42
+ 143              		.loc 1 145 21 is_stmt 0 view .LVU43
+ 144 0022 C4F8C032 		str	r3, [r4, #704]
+ 145              	.L10:
+ 146:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 147:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 148:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Free Device descriptors resources */
+ 149:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->pDesc = NULL;
+ 146              		.loc 1 149 3 is_stmt 1 view .LVU44
+ 147              		.loc 1 149 15 is_stmt 0 view .LVU45
+ 148 0026 0023     		movs	r3, #0
+ 149 0028 C4F8B432 		str	r3, [r4, #692]
+ 150:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->pConfDesc = NULL;
+ 150              		.loc 1 150 3 is_stmt 1 view .LVU46
+ 151              		.loc 1 150 19 is_stmt 0 view .LVU47
+ 152 002c C4F8CC32 		str	r3, [r4, #716]
+ 151:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 152:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* DeInitialize low level driver */
+ 153:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   ret = USBD_LL_DeInit(pdev);
+ 153              		.loc 1 153 3 is_stmt 1 view .LVU48
+ 154              		.loc 1 153 9 is_stmt 0 view .LVU49
+ 155 0030 2046     		mov	r0, r4
+ 156 0032 FFF7FEFF 		bl	USBD_LL_DeInit
+ 157              	.LVL9:
+ 154:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 155:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return ret;
+ 158              		.loc 1 155 3 is_stmt 1 view .LVU50
+ 156:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 159              		.loc 1 156 1 is_stmt 0 view .LVU51
+ 160 0036 10BD     		pop	{r4, pc}
+ 161              		.loc 1 156 1 view .LVU52
+ 162              		.cfi_endproc
+ 163              	.LFE334:
+ 165              		.section	.text.USBD_RegisterClass,"ax",%progbits
+ 166              		.align	1
+ 167              		.global	USBD_RegisterClass
+ 168              		.syntax unified
+ 169              		.thumb
+ 170              		.thumb_func
+ 172              	USBD_RegisterClass:
+ 173              	.LVL10:
+ 174              	.LFB335:
+ 157:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 158:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 159:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_RegisterClass
+ 160:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Link class driver to Device Core.
+ 161:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pDevice : Device Handle
+ 162:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pclass: Class handle
+ 163:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval USBD Status
+ 164:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
+ 166:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 175              		.loc 1 166 1 is_stmt 1 view -0
+ 176              		.cfi_startproc
+ 177              		@ args = 0, pretend = 0, frame = 8
+ 178              		@ frame_needed = 0, uses_anonymous_args = 0
+ 179              		.loc 1 166 1 is_stmt 0 view .LVU54
+ARM GAS  /tmp/ccXNKvGT.s 			page 7
+
+
+ 180 0000 10B5     		push	{r4, lr}
+ 181              	.LCFI3:
+ 182              		.cfi_def_cfa_offset 8
+ 183              		.cfi_offset 4, -8
+ 184              		.cfi_offset 14, -4
+ 185 0002 82B0     		sub	sp, sp, #8
+ 186              	.LCFI4:
+ 187              		.cfi_def_cfa_offset 16
+ 167:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   uint16_t len = 0U;
+ 188              		.loc 1 167 3 is_stmt 1 view .LVU55
+ 189              		.loc 1 167 12 is_stmt 0 view .LVU56
+ 190 0004 0023     		movs	r3, #0
+ 191 0006 ADF80630 		strh	r3, [sp, #6]	@ movhi
+ 168:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 169:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pclass == NULL)
+ 192              		.loc 1 169 3 is_stmt 1 view .LVU57
+ 193              		.loc 1 169 6 is_stmt 0 view .LVU58
+ 194 000a 61B1     		cbz	r1, .L14
+ 195 000c 0446     		mov	r4, r0
+ 170:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 171:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #if (USBD_DEBUG_LEVEL > 1U)
+ 172:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     USBD_ErrLog("Invalid Class handle");
+ 173:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #endif
+ 174:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     return USBD_FAIL;
+ 175:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 176:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 177:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* link the class to the USB Device handle */
+ 178:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->pClass = pclass;
+ 196              		.loc 1 178 3 is_stmt 1 view .LVU59
+ 197              		.loc 1 178 16 is_stmt 0 view .LVU60
+ 198 000e C0F8B812 		str	r1, [r0, #696]
+ 179:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Get Device Configuration Descriptor */
+ 181:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #ifdef USE_USB_HS
+ 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass->GetHSConfigDescriptor != NULL)
+ 183:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     pdev->pConfDesc = (void *)pdev->pClass->GetHSConfigDescriptor(&len);
+ 185:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 186:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #else /* Default USE_USB_FS */
+ 187:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass->GetFSConfigDescriptor != NULL)
+ 199              		.loc 1 187 3 is_stmt 1 view .LVU61
+ 200              		.loc 1 187 19 is_stmt 0 view .LVU62
+ 201 0012 CB6A     		ldr	r3, [r1, #44]
+ 202              		.loc 1 187 6 view .LVU63
+ 203 0014 4BB1     		cbz	r3, .L15
+ 188:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 189:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     pdev->pConfDesc = (void *)pdev->pClass->GetFSConfigDescriptor(&len);
+ 204              		.loc 1 189 5 is_stmt 1 view .LVU64
+ 205              		.loc 1 189 31 is_stmt 0 view .LVU65
+ 206 0016 0DF10600 		add	r0, sp, #6
+ 207              	.LVL11:
+ 208              		.loc 1 189 31 view .LVU66
+ 209 001a 9847     		blx	r3
+ 210              	.LVL12:
+ 211              		.loc 1 189 21 view .LVU67
+ 212 001c C4F8CC02 		str	r0, [r4, #716]
+ 190:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ARM GAS  /tmp/ccXNKvGT.s 			page 8
+
+
+ 191:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #endif /* USE_USB_FS */
+ 192:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 193:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 213              		.loc 1 193 10 view .LVU68
+ 214 0020 0020     		movs	r0, #0
+ 215              	.LVL13:
+ 216              	.L13:
+ 194:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 217              		.loc 1 194 1 view .LVU69
+ 218 0022 02B0     		add	sp, sp, #8
+ 219              	.LCFI5:
+ 220              		.cfi_remember_state
+ 221              		.cfi_def_cfa_offset 8
+ 222              		@ sp needed
+ 223 0024 10BD     		pop	{r4, pc}
+ 224              	.LVL14:
+ 225              	.L14:
+ 226              	.LCFI6:
+ 227              		.cfi_restore_state
+ 174:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 228              		.loc 1 174 12 view .LVU70
+ 229 0026 0320     		movs	r0, #3
+ 230              	.LVL15:
+ 174:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 231              		.loc 1 174 12 view .LVU71
+ 232 0028 FBE7     		b	.L13
+ 233              	.LVL16:
+ 234              	.L15:
+ 193:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 235              		.loc 1 193 10 view .LVU72
+ 236 002a 0020     		movs	r0, #0
+ 237              	.LVL17:
+ 193:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 238              		.loc 1 193 10 view .LVU73
+ 239 002c F9E7     		b	.L13
+ 240              		.cfi_endproc
+ 241              	.LFE335:
+ 243              		.section	.text.USBD_Start,"ax",%progbits
+ 244              		.align	1
+ 245              		.global	USBD_Start
+ 246              		.syntax unified
+ 247              		.thumb
+ 248              		.thumb_func
+ 250              	USBD_Start:
+ 251              	.LVL18:
+ 252              	.LFB336:
+ 195:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 196:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 197:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_Start
+ 198:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Start the USB Device Core.
+ 199:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: Device Handle
+ 200:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval USBD Status
+ 201:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 202:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
+ 203:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 253              		.loc 1 203 1 is_stmt 1 view -0
+ 254              		.cfi_startproc
+ARM GAS  /tmp/ccXNKvGT.s 			page 9
+
+
+ 255              		@ args = 0, pretend = 0, frame = 0
+ 256              		@ frame_needed = 0, uses_anonymous_args = 0
+ 257              		.loc 1 203 1 is_stmt 0 view .LVU75
+ 258 0000 08B5     		push	{r3, lr}
+ 259              	.LCFI7:
+ 260              		.cfi_def_cfa_offset 8
+ 261              		.cfi_offset 3, -8
+ 262              		.cfi_offset 14, -4
+ 204:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Start the low level driver  */
+ 205:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_LL_Start(pdev);
+ 263              		.loc 1 205 3 is_stmt 1 view .LVU76
+ 264              		.loc 1 205 10 is_stmt 0 view .LVU77
+ 265 0002 FFF7FEFF 		bl	USBD_LL_Start
+ 266              	.LVL19:
+ 206:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 267              		.loc 1 206 1 view .LVU78
+ 268 0006 08BD     		pop	{r3, pc}
+ 269              		.cfi_endproc
+ 270              	.LFE336:
+ 272              		.section	.text.USBD_Stop,"ax",%progbits
+ 273              		.align	1
+ 274              		.global	USBD_Stop
+ 275              		.syntax unified
+ 276              		.thumb
+ 277              		.thumb_func
+ 279              	USBD_Stop:
+ 280              	.LVL20:
+ 281              	.LFB337:
+ 207:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 208:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 209:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_Stop
+ 210:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Stop the USB Device Core.
+ 211:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: Device Handle
+ 212:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval USBD Status
+ 213:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 214:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev)
+ 215:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 282              		.loc 1 215 1 is_stmt 1 view -0
+ 283              		.cfi_startproc
+ 284              		@ args = 0, pretend = 0, frame = 0
+ 285              		@ frame_needed = 0, uses_anonymous_args = 0
+ 286              		.loc 1 215 1 is_stmt 0 view .LVU80
+ 287 0000 10B5     		push	{r4, lr}
+ 288              	.LCFI8:
+ 289              		.cfi_def_cfa_offset 8
+ 290              		.cfi_offset 4, -8
+ 291              		.cfi_offset 14, -4
+ 292 0002 0446     		mov	r4, r0
+ 216:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Disconnect USB Device */
+ 217:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   (void)USBD_LL_Stop(pdev);
+ 293              		.loc 1 217 3 is_stmt 1 view .LVU81
+ 294              		.loc 1 217 9 is_stmt 0 view .LVU82
+ 295 0004 FFF7FEFF 		bl	USBD_LL_Stop
+ 296              	.LVL21:
+ 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 219:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Free Class Resources */
+ 220:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass != NULL)
+ARM GAS  /tmp/ccXNKvGT.s 			page 10
+
+
+ 297              		.loc 1 220 3 is_stmt 1 view .LVU83
+ 298              		.loc 1 220 11 is_stmt 0 view .LVU84
+ 299 0008 D4F8B832 		ldr	r3, [r4, #696]
+ 300              		.loc 1 220 6 view .LVU85
+ 301 000c 1BB1     		cbz	r3, .L20
+ 221:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 222:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+ 302              		.loc 1 222 5 is_stmt 1 view .LVU86
+ 303              		.loc 1 222 23 is_stmt 0 view .LVU87
+ 304 000e 5B68     		ldr	r3, [r3, #4]
+ 305              		.loc 1 222 11 view .LVU88
+ 306 0010 2179     		ldrb	r1, [r4, #4]	@ zero_extendqisi2
+ 307 0012 2046     		mov	r0, r4
+ 308 0014 9847     		blx	r3
+ 309              	.LVL22:
+ 310              	.L20:
+ 223:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 224:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 311              		.loc 1 225 3 is_stmt 1 view .LVU89
+ 226:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 312              		.loc 1 226 1 is_stmt 0 view .LVU90
+ 313 0016 0020     		movs	r0, #0
+ 314 0018 10BD     		pop	{r4, pc}
+ 315              		.loc 1 226 1 view .LVU91
+ 316              		.cfi_endproc
+ 317              	.LFE337:
+ 319              		.section	.text.USBD_RunTestMode,"ax",%progbits
+ 320              		.align	1
+ 321              		.global	USBD_RunTestMode
+ 322              		.syntax unified
+ 323              		.thumb
+ 324              		.thumb_func
+ 326              	USBD_RunTestMode:
+ 327              	.LVL23:
+ 328              	.LFB338:
+ 227:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 228:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 229:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_RunTestMode
+ 230:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Launch test mode process
+ 231:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 232:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 233:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 234:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef  *pdev)
+ 235:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 329              		.loc 1 235 1 is_stmt 1 view -0
+ 330              		.cfi_startproc
+ 331              		@ args = 0, pretend = 0, frame = 0
+ 332              		@ frame_needed = 0, uses_anonymous_args = 0
+ 333              		@ link register save eliminated.
+ 236:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Prevent unused argument compilation warning */
+ 237:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   UNUSED(pdev);
+ 334              		.loc 1 237 3 view .LVU93
+ 238:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 239:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 335              		.loc 1 239 3 view .LVU94
+ 240:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ARM GAS  /tmp/ccXNKvGT.s 			page 11
+
+
+ 336              		.loc 1 240 1 is_stmt 0 view .LVU95
+ 337 0000 0020     		movs	r0, #0
+ 338              	.LVL24:
+ 339              		.loc 1 240 1 view .LVU96
+ 340 0002 7047     		bx	lr
+ 341              		.cfi_endproc
+ 342              	.LFE338:
+ 344              		.section	.text.USBD_SetClassConfig,"ax",%progbits
+ 345              		.align	1
+ 346              		.global	USBD_SetClassConfig
+ 347              		.syntax unified
+ 348              		.thumb
+ 349              		.thumb_func
+ 351              	USBD_SetClassConfig:
+ 352              	.LVL25:
+ 353              	.LFB339:
+ 241:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 242:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 243:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_SetClassConfig
+ 244:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *        Configure device and start the interface
+ 245:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 246:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  cfgidx: configuration index
+ 247:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 248:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 250:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
+ 251:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 354              		.loc 1 251 1 is_stmt 1 view -0
+ 355              		.cfi_startproc
+ 356              		@ args = 0, pretend = 0, frame = 0
+ 357              		@ frame_needed = 0, uses_anonymous_args = 0
+ 358              		.loc 1 251 1 is_stmt 0 view .LVU98
+ 359 0000 08B5     		push	{r3, lr}
+ 360              	.LCFI9:
+ 361              		.cfi_def_cfa_offset 8
+ 362              		.cfi_offset 3, -8
+ 363              		.cfi_offset 14, -4
+ 252:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   USBD_StatusTypeDef ret = USBD_FAIL;
+ 364              		.loc 1 252 3 is_stmt 1 view .LVU99
+ 365              	.LVL26:
+ 253:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 254:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass != NULL)
+ 366              		.loc 1 254 3 view .LVU100
+ 367              		.loc 1 254 11 is_stmt 0 view .LVU101
+ 368 0002 D0F8B832 		ldr	r3, [r0, #696]
+ 369              		.loc 1 254 6 view .LVU102
+ 370 0006 13B1     		cbz	r3, .L25
+ 255:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 256:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     /* Set configuration and Start the Class */
+ 257:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     ret = (USBD_StatusTypeDef)pdev->pClass->Init(pdev, cfgidx);
+ 371              		.loc 1 257 5 is_stmt 1 view .LVU103
+ 372              		.loc 1 257 43 is_stmt 0 view .LVU104
+ 373 0008 1B68     		ldr	r3, [r3]
+ 374              		.loc 1 257 31 view .LVU105
+ 375 000a 9847     		blx	r3
+ 376              	.LVL27:
+ 377              	.L24:
+ARM GAS  /tmp/ccXNKvGT.s 			page 12
+
+
+ 258:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 259:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 260:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return ret;
+ 378              		.loc 1 260 3 is_stmt 1 view .LVU106
+ 261:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 379              		.loc 1 261 1 is_stmt 0 view .LVU107
+ 380 000c 08BD     		pop	{r3, pc}
+ 381              	.LVL28:
+ 382              	.L25:
+ 252:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 383              		.loc 1 252 22 view .LVU108
+ 384 000e 0320     		movs	r0, #3
+ 385              	.LVL29:
+ 252:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 386              		.loc 1 252 22 view .LVU109
+ 387 0010 FCE7     		b	.L24
+ 388              		.cfi_endproc
+ 389              	.LFE339:
+ 391              		.section	.text.USBD_ClrClassConfig,"ax",%progbits
+ 392              		.align	1
+ 393              		.global	USBD_ClrClassConfig
+ 394              		.syntax unified
+ 395              		.thumb
+ 396              		.thumb_func
+ 398              	USBD_ClrClassConfig:
+ 399              	.LVL30:
+ 400              	.LFB340:
+ 262:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 263:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 264:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_ClrClassConfig
+ 265:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Clear current configuration
+ 266:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 267:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  cfgidx: configuration index
+ 268:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status: USBD_StatusTypeDef
+ 269:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 270:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
+ 271:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 401              		.loc 1 271 1 is_stmt 1 view -0
+ 402              		.cfi_startproc
+ 403              		@ args = 0, pretend = 0, frame = 0
+ 404              		@ frame_needed = 0, uses_anonymous_args = 0
+ 405              		.loc 1 271 1 is_stmt 0 view .LVU111
+ 406 0000 08B5     		push	{r3, lr}
+ 407              	.LCFI10:
+ 408              		.cfi_def_cfa_offset 8
+ 409              		.cfi_offset 3, -8
+ 410              		.cfi_offset 14, -4
+ 272:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Clear configuration and De-initialize the Class process */
+ 273:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass != NULL)
+ 411              		.loc 1 273 3 is_stmt 1 view .LVU112
+ 412              		.loc 1 273 11 is_stmt 0 view .LVU113
+ 413 0002 D0F8B832 		ldr	r3, [r0, #696]
+ 414              		.loc 1 273 6 view .LVU114
+ 415 0006 0BB1     		cbz	r3, .L28
+ 274:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 275:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     pdev->pClass->DeInit(pdev, cfgidx);
+ 416              		.loc 1 275 5 is_stmt 1 view .LVU115
+ARM GAS  /tmp/ccXNKvGT.s 			page 13
+
+
+ 417              		.loc 1 275 17 is_stmt 0 view .LVU116
+ 418 0008 5B68     		ldr	r3, [r3, #4]
+ 419              		.loc 1 275 5 view .LVU117
+ 420 000a 9847     		blx	r3
+ 421              	.LVL31:
+ 422              	.L28:
+ 276:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 277:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 278:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 423              		.loc 1 278 3 is_stmt 1 view .LVU118
+ 279:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 424              		.loc 1 279 1 is_stmt 0 view .LVU119
+ 425 000c 0020     		movs	r0, #0
+ 426 000e 08BD     		pop	{r3, pc}
+ 427              		.cfi_endproc
+ 428              	.LFE340:
+ 430              		.section	.text.USBD_LL_SetupStage,"ax",%progbits
+ 431              		.align	1
+ 432              		.global	USBD_LL_SetupStage
+ 433              		.syntax unified
+ 434              		.thumb
+ 435              		.thumb_func
+ 437              	USBD_LL_SetupStage:
+ 438              	.LVL32:
+ 439              	.LFB341:
+ 280:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 281:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 282:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 283:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_LL_SetupStage
+ 284:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Handle the setup stage
+ 285:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 286:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 287:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
+ 289:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 440              		.loc 1 289 1 is_stmt 1 view -0
+ 441              		.cfi_startproc
+ 442              		@ args = 0, pretend = 0, frame = 0
+ 443              		@ frame_needed = 0, uses_anonymous_args = 0
+ 444              		.loc 1 289 1 is_stmt 0 view .LVU121
+ 445 0000 38B5     		push	{r3, r4, r5, lr}
+ 446              	.LCFI11:
+ 447              		.cfi_def_cfa_offset 16
+ 448              		.cfi_offset 3, -16
+ 449              		.cfi_offset 4, -12
+ 450              		.cfi_offset 5, -8
+ 451              		.cfi_offset 14, -4
+ 452 0002 0446     		mov	r4, r0
+ 290:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   USBD_StatusTypeDef ret;
+ 453              		.loc 1 290 3 is_stmt 1 view .LVU122
+ 291:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 292:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   USBD_ParseSetupRequest(&pdev->request, psetup);
+ 454              		.loc 1 292 3 view .LVU123
+ 455 0004 00F2AA25 		addw	r5, r0, #682
+ 456 0008 2846     		mov	r0, r5
+ 457              	.LVL33:
+ 458              		.loc 1 292 3 is_stmt 0 view .LVU124
+ARM GAS  /tmp/ccXNKvGT.s 			page 14
+
+
+ 459 000a FFF7FEFF 		bl	USBD_ParseSetupRequest
+ 460              	.LVL34:
+ 293:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 294:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->ep0_state = USBD_EP0_SETUP;
+ 461              		.loc 1 294 3 is_stmt 1 view .LVU125
+ 462              		.loc 1 294 19 is_stmt 0 view .LVU126
+ 463 000e 0123     		movs	r3, #1
+ 464 0010 C4F89432 		str	r3, [r4, #660]
+ 295:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 296:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->ep0_data_len = pdev->request.wLength;
+ 465              		.loc 1 296 3 is_stmt 1 view .LVU127
+ 466              		.loc 1 296 37 is_stmt 0 view .LVU128
+ 467 0014 B4F8B032 		ldrh	r3, [r4, #688]
+ 468              		.loc 1 296 22 view .LVU129
+ 469 0018 C4F89832 		str	r3, [r4, #664]
+ 297:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 298:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   switch (pdev->request.bmRequest & 0x1FU)
+ 470              		.loc 1 298 3 is_stmt 1 view .LVU130
+ 471              		.loc 1 298 24 is_stmt 0 view .LVU131
+ 472 001c 94F8AA12 		ldrb	r1, [r4, #682]	@ zero_extendqisi2
+ 473 0020 01F01F03 		and	r3, r1, #31
+ 474              		.loc 1 298 3 view .LVU132
+ 475 0024 012B     		cmp	r3, #1
+ 476 0026 0DD0     		beq	.L31
+ 477 0028 022B     		cmp	r3, #2
+ 478 002a 10D0     		beq	.L32
+ 479 002c 2BB1     		cbz	r3, .L36
+ 299:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 300:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     case USB_REQ_RECIPIENT_DEVICE:
+ 301:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       ret = USBD_StdDevReq(pdev, &pdev->request);
+ 302:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       break;
+ 303:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 304:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     case USB_REQ_RECIPIENT_INTERFACE:
+ 305:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       ret = USBD_StdItfReq(pdev, &pdev->request);
+ 306:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       break;
+ 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 308:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     case USB_REQ_RECIPIENT_ENDPOINT:
+ 309:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       ret = USBD_StdEPReq(pdev, &pdev->request);
+ 310:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       break;
+ 311:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 312:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     default:
+ 313:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
+ 480              		.loc 1 313 7 is_stmt 1 view .LVU133
+ 481              		.loc 1 313 13 is_stmt 0 view .LVU134
+ 482 002e 01F08001 		and	r1, r1, #128
+ 483 0032 2046     		mov	r0, r4
+ 484 0034 FFF7FEFF 		bl	USBD_LL_StallEP
+ 485              	.LVL35:
+ 314:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       break;
+ 486              		.loc 1 314 7 is_stmt 1 view .LVU135
+ 487 0038 03E0     		b	.L34
+ 488              	.LVL36:
+ 489              	.L36:
+ 301:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       break;
+ 490              		.loc 1 301 7 view .LVU136
+ 301:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       break;
+ 491              		.loc 1 301 13 is_stmt 0 view .LVU137
+ARM GAS  /tmp/ccXNKvGT.s 			page 15
+
+
+ 492 003a 2946     		mov	r1, r5
+ 493 003c 2046     		mov	r0, r4
+ 494 003e FFF7FEFF 		bl	USBD_StdDevReq
+ 495              	.LVL37:
+ 302:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 496              		.loc 1 302 7 is_stmt 1 view .LVU138
+ 497              	.L34:
+ 315:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 316:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 317:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return ret;
+ 498              		.loc 1 317 3 view .LVU139
+ 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 499              		.loc 1 318 1 is_stmt 0 view .LVU140
+ 500 0042 38BD     		pop	{r3, r4, r5, pc}
+ 501              	.LVL38:
+ 502              	.L31:
+ 305:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       break;
+ 503              		.loc 1 305 7 is_stmt 1 view .LVU141
+ 305:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       break;
+ 504              		.loc 1 305 13 is_stmt 0 view .LVU142
+ 505 0044 2946     		mov	r1, r5
+ 506 0046 2046     		mov	r0, r4
+ 507 0048 FFF7FEFF 		bl	USBD_StdItfReq
+ 508              	.LVL39:
+ 306:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 509              		.loc 1 306 7 is_stmt 1 view .LVU143
+ 510 004c F9E7     		b	.L34
+ 511              	.LVL40:
+ 512              	.L32:
+ 309:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       break;
+ 513              		.loc 1 309 7 view .LVU144
+ 309:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       break;
+ 514              		.loc 1 309 13 is_stmt 0 view .LVU145
+ 515 004e 2946     		mov	r1, r5
+ 516 0050 2046     		mov	r0, r4
+ 517 0052 FFF7FEFF 		bl	USBD_StdEPReq
+ 518              	.LVL41:
+ 310:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 519              		.loc 1 310 7 is_stmt 1 view .LVU146
+ 520 0056 F4E7     		b	.L34
+ 521              		.cfi_endproc
+ 522              	.LFE341:
+ 524              		.section	.text.USBD_LL_DataOutStage,"ax",%progbits
+ 525              		.align	1
+ 526              		.global	USBD_LL_DataOutStage
+ 527              		.syntax unified
+ 528              		.thumb
+ 529              		.thumb_func
+ 531              	USBD_LL_DataOutStage:
+ 532              	.LVL42:
+ 533              	.LFB342:
+ 319:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 320:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 321:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_LL_DataOutStage
+ 322:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Handle data OUT stage
+ 323:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 324:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  epnum: endpoint index
+ARM GAS  /tmp/ccXNKvGT.s 			page 16
+
+
+ 325:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdata: data pointer
+ 326:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 327:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 328:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
+ 329:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****                                         uint8_t epnum, uint8_t *pdata)
+ 330:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 534              		.loc 1 330 1 view -0
+ 535              		.cfi_startproc
+ 536              		@ args = 0, pretend = 0, frame = 0
+ 537              		@ frame_needed = 0, uses_anonymous_args = 0
+ 538              		.loc 1 330 1 is_stmt 0 view .LVU148
+ 539 0000 38B5     		push	{r3, r4, r5, lr}
+ 540              	.LCFI12:
+ 541              		.cfi_def_cfa_offset 16
+ 542              		.cfi_offset 3, -16
+ 543              		.cfi_offset 4, -12
+ 544              		.cfi_offset 5, -8
+ 545              		.cfi_offset 14, -4
+ 546 0002 0446     		mov	r4, r0
+ 331:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   USBD_EndpointTypeDef *pep;
+ 547              		.loc 1 331 3 is_stmt 1 view .LVU149
+ 332:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   USBD_StatusTypeDef ret;
+ 548              		.loc 1 332 3 view .LVU150
+ 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 334:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (epnum == 0U)
+ 549              		.loc 1 334 3 view .LVU151
+ 550              		.loc 1 334 6 is_stmt 0 view .LVU152
+ 551 0004 0D46     		mov	r5, r1
+ 552 0006 41BB     		cbnz	r1, .L38
+ 553 0008 1346     		mov	r3, r2
+ 335:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 336:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     pep = &pdev->ep_out[0];
+ 554              		.loc 1 336 5 is_stmt 1 view .LVU153
+ 555              	.LVL43:
+ 337:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 338:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     if (pdev->ep0_state == USBD_EP0_DATA_OUT)
+ 556              		.loc 1 338 5 view .LVU154
+ 557              		.loc 1 338 13 is_stmt 0 view .LVU155
+ 558 000a D0F89422 		ldr	r2, [r0, #660]
+ 559              	.LVL44:
+ 560              		.loc 1 338 8 view .LVU156
+ 561 000e 032A     		cmp	r2, #3
+ 562 0010 01D0     		beq	.L46
+ 339:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       if (pep->rem_length > pep->maxpacket)
+ 341:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 342:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         pep->rem_length -= pep->maxpacket;
+ 343:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 344:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         (void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket));
+ 345:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 346:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       else
+ 347:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 348:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         if (pdev->dev_state == USBD_STATE_CONFIGURED)
+ 349:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         {
+ 350:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           if (pdev->pClass->EP0_RxReady != NULL)
+ 351:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           {
+ 352:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             pdev->pClass->EP0_RxReady(pdev);
+ARM GAS  /tmp/ccXNKvGT.s 			page 17
+
+
+ 353:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           }
+ 354:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         }
+ 355:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 356:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         (void)USBD_CtlSendStatus(pdev);
+ 357:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 358:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 359:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     else
+ 360:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 361:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #if 0
+ 362:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
+ 363:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 364:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         /*
+ 365:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           * STATUS PHASE completed, update ep0_state to idle
+ 366:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           */
+ 367:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         pdev->ep0_state = USBD_EP0_IDLE;
+ 368:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         (void)USBD_LL_StallEP(pdev, 0U);
+ 369:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 370:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #endif
+ 371:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 372:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 373:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   else
+ 374:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 375:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     if (pdev->dev_state == USBD_STATE_CONFIGURED)
+ 376:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 377:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       if (pdev->pClass->DataOut != NULL)
+ 378:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 379:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         ret = (USBD_StatusTypeDef)pdev->pClass->DataOut(pdev, epnum);
+ 380:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         if (ret != USBD_OK)
+ 382:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         {
+ 383:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           return ret;
+ 384:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         }
+ 385:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 386:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 387:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 388:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 389:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 563              		.loc 1 389 10 view .LVU157
+ 564 0012 0846     		mov	r0, r1
+ 565              	.LVL45:
+ 566              	.L39:
+ 390:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 567              		.loc 1 390 1 view .LVU158
+ 568 0014 38BD     		pop	{r3, r4, r5, pc}
+ 569              	.LVL46:
+ 570              	.L46:
+ 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 571              		.loc 1 340 7 is_stmt 1 view .LVU159
+ 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 572              		.loc 1 340 14 is_stmt 0 view .LVU160
+ 573 0016 D0F85C11 		ldr	r1, [r0, #348]
+ 574              	.LVL47:
+ 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 575              		.loc 1 340 32 view .LVU161
+ 576 001a D0F86021 		ldr	r2, [r0, #352]
+ 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 577              		.loc 1 340 10 view .LVU162
+ARM GAS  /tmp/ccXNKvGT.s 			page 18
+
+
+ 578 001e 9142     		cmp	r1, r2
+ 579 0020 09D8     		bhi	.L47
+ 348:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         {
+ 580              		.loc 1 348 9 is_stmt 1 view .LVU163
+ 348:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         {
+ 581              		.loc 1 348 17 is_stmt 0 view .LVU164
+ 582 0022 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 583              	.LVL48:
+ 348:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         {
+ 584              		.loc 1 348 17 view .LVU165
+ 585 0026 DBB2     		uxtb	r3, r3
+ 348:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         {
+ 586              		.loc 1 348 12 view .LVU166
+ 587 0028 032B     		cmp	r3, #3
+ 588 002a 0FD0     		beq	.L48
+ 589              	.LVL49:
+ 590              	.L41:
+ 356:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 591              		.loc 1 356 9 is_stmt 1 view .LVU167
+ 356:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 592              		.loc 1 356 15 is_stmt 0 view .LVU168
+ 593 002c 2046     		mov	r0, r4
+ 594 002e FFF7FEFF 		bl	USBD_CtlSendStatus
+ 595              	.LVL50:
+ 389:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 596              		.loc 1 389 10 view .LVU169
+ 597 0032 2846     		mov	r0, r5
+ 598 0034 EEE7     		b	.L39
+ 599              	.LVL51:
+ 600              	.L47:
+ 342:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 601              		.loc 1 342 9 is_stmt 1 view .LVU170
+ 342:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 602              		.loc 1 342 25 is_stmt 0 view .LVU171
+ 603 0036 891A     		subs	r1, r1, r2
+ 604 0038 C0F85C11 		str	r1, [r0, #348]
+ 344:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 605              		.loc 1 344 9 is_stmt 1 view .LVU172
+ 344:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 606              		.loc 1 344 15 is_stmt 0 view .LVU173
+ 607 003c 8A42     		cmp	r2, r1
+ 608 003e 28BF     		it	cs
+ 609 0040 0A46     		movcs	r2, r1
+ 610 0042 1946     		mov	r1, r3
+ 611 0044 FFF7FEFF 		bl	USBD_CtlContinueRx
+ 612              	.LVL52:
+ 389:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 613              		.loc 1 389 10 view .LVU174
+ 614 0048 2846     		mov	r0, r5
+ 615 004a E3E7     		b	.L39
+ 616              	.LVL53:
+ 617              	.L48:
+ 350:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           {
+ 618              		.loc 1 350 11 is_stmt 1 view .LVU175
+ 350:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           {
+ 619              		.loc 1 350 19 is_stmt 0 view .LVU176
+ 620 004c D0F8B832 		ldr	r3, [r0, #696]
+ARM GAS  /tmp/ccXNKvGT.s 			page 19
+
+
+ 350:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           {
+ 621              		.loc 1 350 27 view .LVU177
+ 622 0050 1B69     		ldr	r3, [r3, #16]
+ 350:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           {
+ 623              		.loc 1 350 14 view .LVU178
+ 624 0052 002B     		cmp	r3, #0
+ 625 0054 EAD0     		beq	.L41
+ 352:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           }
+ 626              		.loc 1 352 13 is_stmt 1 view .LVU179
+ 627 0056 9847     		blx	r3
+ 628              	.LVL54:
+ 352:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           }
+ 629              		.loc 1 352 13 is_stmt 0 view .LVU180
+ 630 0058 E8E7     		b	.L41
+ 631              	.LVL55:
+ 632              	.L38:
+ 375:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 633              		.loc 1 375 5 is_stmt 1 view .LVU181
+ 375:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 634              		.loc 1 375 13 is_stmt 0 view .LVU182
+ 635 005a 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 636 005e DBB2     		uxtb	r3, r3
+ 375:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 637              		.loc 1 375 8 view .LVU183
+ 638 0060 032B     		cmp	r3, #3
+ 639 0062 01D0     		beq	.L49
+ 389:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 640              		.loc 1 389 10 view .LVU184
+ 641 0064 0020     		movs	r0, #0
+ 642              	.LVL56:
+ 389:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 643              		.loc 1 389 10 view .LVU185
+ 644 0066 D5E7     		b	.L39
+ 645              	.LVL57:
+ 646              	.L49:
+ 377:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 647              		.loc 1 377 7 is_stmt 1 view .LVU186
+ 377:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 648              		.loc 1 377 15 is_stmt 0 view .LVU187
+ 649 0068 D0F8B832 		ldr	r3, [r0, #696]
+ 377:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 650              		.loc 1 377 23 view .LVU188
+ 651 006c 9B69     		ldr	r3, [r3, #24]
+ 377:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 652              		.loc 1 377 10 view .LVU189
+ 653 006e 0BB1     		cbz	r3, .L44
+ 379:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 654              		.loc 1 379 9 is_stmt 1 view .LVU190
+ 379:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 655              		.loc 1 379 35 is_stmt 0 view .LVU191
+ 656 0070 9847     		blx	r3
+ 657              	.LVL58:
+ 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         {
+ 658              		.loc 1 381 9 is_stmt 1 view .LVU192
+ 659 0072 CFE7     		b	.L39
+ 660              	.LVL59:
+ 661              	.L44:
+ARM GAS  /tmp/ccXNKvGT.s 			page 20
+
+
+ 389:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 662              		.loc 1 389 10 is_stmt 0 view .LVU193
+ 663 0074 0020     		movs	r0, #0
+ 664              	.LVL60:
+ 389:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 665              		.loc 1 389 10 view .LVU194
+ 666 0076 CDE7     		b	.L39
+ 667              		.cfi_endproc
+ 668              	.LFE342:
+ 670              		.section	.text.USBD_LL_DataInStage,"ax",%progbits
+ 671              		.align	1
+ 672              		.global	USBD_LL_DataInStage
+ 673              		.syntax unified
+ 674              		.thumb
+ 675              		.thumb_func
+ 677              	USBD_LL_DataInStage:
+ 678              	.LVL61:
+ 679              	.LFB343:
+ 391:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 392:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 393:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_LL_DataInStage
+ 394:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Handle data in stage
+ 395:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 396:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  epnum: endpoint index
+ 397:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 398:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 399:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
+ 400:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****                                        uint8_t epnum, uint8_t *pdata)
+ 401:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 680              		.loc 1 401 1 is_stmt 1 view -0
+ 681              		.cfi_startproc
+ 682              		@ args = 0, pretend = 0, frame = 0
+ 683              		@ frame_needed = 0, uses_anonymous_args = 0
+ 684              		.loc 1 401 1 is_stmt 0 view .LVU196
+ 685 0000 38B5     		push	{r3, r4, r5, lr}
+ 686              	.LCFI13:
+ 687              		.cfi_def_cfa_offset 16
+ 688              		.cfi_offset 3, -16
+ 689              		.cfi_offset 4, -12
+ 690              		.cfi_offset 5, -8
+ 691              		.cfi_offset 14, -4
+ 692 0002 0446     		mov	r4, r0
+ 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   USBD_EndpointTypeDef *pep;
+ 693              		.loc 1 402 3 is_stmt 1 view .LVU197
+ 403:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   USBD_StatusTypeDef ret;
+ 694              		.loc 1 403 3 view .LVU198
+ 404:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 405:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (epnum == 0U)
+ 695              		.loc 1 405 3 view .LVU199
+ 696              		.loc 1 405 6 is_stmt 0 view .LVU200
+ 697 0004 0D46     		mov	r5, r1
+ 698 0006 0029     		cmp	r1, #0
+ 699 0008 4AD1     		bne	.L51
+ 700 000a 1346     		mov	r3, r2
+ 406:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 407:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     pep = &pdev->ep_in[0];
+ 701              		.loc 1 407 5 is_stmt 1 view .LVU201
+ARM GAS  /tmp/ccXNKvGT.s 			page 21
+
+
+ 702              	.LVL62:
+ 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 409:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     if (pdev->ep0_state == USBD_EP0_DATA_IN)
+ 703              		.loc 1 409 5 view .LVU202
+ 704              		.loc 1 409 13 is_stmt 0 view .LVU203
+ 705 000c D0F89422 		ldr	r2, [r0, #660]
+ 706              	.LVL63:
+ 707              		.loc 1 409 8 view .LVU204
+ 708 0010 022A     		cmp	r2, #2
+ 709 0012 05D0     		beq	.L61
+ 710              	.LVL64:
+ 711              	.L52:
+ 410:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 411:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       if (pep->rem_length > pep->maxpacket)
+ 412:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         pep->rem_length -= pep->maxpacket;
+ 414:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 415:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         (void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length);
+ 416:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 417:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         /* Prepare endpoint for premature end of transfer */
+ 418:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
+ 419:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 420:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       else
+ 421:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 422:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         /* last packet is MPS multiple, so send ZLP packet */
+ 423:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         if ((pep->maxpacket == pep->rem_length) &&
+ 424:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             (pep->total_length >= pep->maxpacket) &&
+ 425:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             (pep->total_length < pdev->ep0_data_len))
+ 426:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         {
+ 427:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           (void)USBD_CtlContinueSendData(pdev, NULL, 0U);
+ 428:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           pdev->ep0_data_len = 0U;
+ 429:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 430:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           /* Prepare endpoint for premature end of transfer */
+ 431:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
+ 432:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         }
+ 433:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         else
+ 434:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         {
+ 435:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           if (pdev->dev_state == USBD_STATE_CONFIGURED)
+ 436:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           {
+ 437:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             if (pdev->pClass->EP0_TxSent != NULL)
+ 438:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             {
+ 439:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****               pdev->pClass->EP0_TxSent(pdev);
+ 440:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             }
+ 441:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           }
+ 442:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           (void)USBD_LL_StallEP(pdev, 0x80U);
+ 443:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           (void)USBD_CtlReceiveStatus(pdev);
+ 444:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         }
+ 445:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 447:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     else
+ 448:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 449:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #if 0
+ 450:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
+ 451:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           (pdev->ep0_state == USBD_EP0_IDLE))
+ 452:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 453:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         (void)USBD_LL_StallEP(pdev, 0x80U);
+ 454:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ARM GAS  /tmp/ccXNKvGT.s 			page 22
+
+
+ 455:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #endif
+ 456:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 712              		.loc 1 456 5 is_stmt 1 view .LVU205
+ 457:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 458:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     if (pdev->dev_test_mode == 1U)
+ 713              		.loc 1 458 5 view .LVU206
+ 714              		.loc 1 458 13 is_stmt 0 view .LVU207
+ 715 0014 94F8A032 		ldrb	r3, [r4, #672]	@ zero_extendqisi2
+ 716              		.loc 1 458 8 view .LVU208
+ 717 0018 012B     		cmp	r3, #1
+ 718 001a 3CD0     		beq	.L62
+ 459:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 460:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       (void)USBD_RunTestMode(pdev);
+ 461:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       pdev->dev_test_mode = 0U;
+ 462:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 463:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 464:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   else
+ 465:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 466:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     if (pdev->dev_state == USBD_STATE_CONFIGURED)
+ 467:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 468:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       if (pdev->pClass->DataIn != NULL)
+ 469:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         ret = (USBD_StatusTypeDef)pdev->pClass->DataIn(pdev, epnum);
+ 471:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 472:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         if (ret != USBD_OK)
+ 473:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         {
+ 474:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           return ret;
+ 475:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         }
+ 476:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 477:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 478:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 479:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 480:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 719              		.loc 1 480 10 view .LVU209
+ 720 001c 2846     		mov	r0, r5
+ 721              	.LVL65:
+ 722              	.L56:
+ 481:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 723              		.loc 1 481 1 view .LVU210
+ 724 001e 38BD     		pop	{r3, r4, r5, pc}
+ 725              	.LVL66:
+ 726              	.L61:
+ 411:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 727              		.loc 1 411 7 is_stmt 1 view .LVU211
+ 411:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 728              		.loc 1 411 14 is_stmt 0 view .LVU212
+ 729 0020 C269     		ldr	r2, [r0, #28]
+ 411:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 730              		.loc 1 411 32 view .LVU213
+ 731 0022 016A     		ldr	r1, [r0, #32]
+ 732              	.LVL67:
+ 411:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 733              		.loc 1 411 10 view .LVU214
+ 734 0024 8A42     		cmp	r2, r1
+ 735 0026 0ED8     		bhi	.L63
+ 423:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             (pep->total_length >= pep->maxpacket) &&
+ 736              		.loc 1 423 9 is_stmt 1 view .LVU215
+ARM GAS  /tmp/ccXNKvGT.s 			page 23
+
+
+ 423:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             (pep->total_length >= pep->maxpacket) &&
+ 737              		.loc 1 423 12 is_stmt 0 view .LVU216
+ 738 0028 8A42     		cmp	r2, r1
+ 739 002a 18D0     		beq	.L64
+ 740              	.LVL68:
+ 741              	.L54:
+ 435:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           {
+ 742              		.loc 1 435 11 is_stmt 1 view .LVU217
+ 435:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           {
+ 743              		.loc 1 435 19 is_stmt 0 view .LVU218
+ 744 002c 94F89C32 		ldrb	r3, [r4, #668]	@ zero_extendqisi2
+ 745 0030 DBB2     		uxtb	r3, r3
+ 435:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           {
+ 746              		.loc 1 435 14 view .LVU219
+ 747 0032 032B     		cmp	r3, #3
+ 748 0034 27D0     		beq	.L65
+ 749              	.LVL69:
+ 750              	.L55:
+ 442:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           (void)USBD_CtlReceiveStatus(pdev);
+ 751              		.loc 1 442 11 is_stmt 1 view .LVU220
+ 442:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           (void)USBD_CtlReceiveStatus(pdev);
+ 752              		.loc 1 442 17 is_stmt 0 view .LVU221
+ 753 0036 8021     		movs	r1, #128
+ 754 0038 2046     		mov	r0, r4
+ 755 003a FFF7FEFF 		bl	USBD_LL_StallEP
+ 756              	.LVL70:
+ 443:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         }
+ 757              		.loc 1 443 11 is_stmt 1 view .LVU222
+ 443:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         }
+ 758              		.loc 1 443 17 is_stmt 0 view .LVU223
+ 759 003e 2046     		mov	r0, r4
+ 760 0040 FFF7FEFF 		bl	USBD_CtlReceiveStatus
+ 761              	.LVL71:
+ 762 0044 E6E7     		b	.L52
+ 763              	.LVL72:
+ 764              	.L63:
+ 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 765              		.loc 1 413 9 is_stmt 1 view .LVU224
+ 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 766              		.loc 1 413 25 is_stmt 0 view .LVU225
+ 767 0046 521A     		subs	r2, r2, r1
+ 768 0048 C261     		str	r2, [r0, #28]
+ 415:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 769              		.loc 1 415 9 is_stmt 1 view .LVU226
+ 415:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 770              		.loc 1 415 15 is_stmt 0 view .LVU227
+ 771 004a 1946     		mov	r1, r3
+ 772 004c FFF7FEFF 		bl	USBD_CtlContinueSendData
+ 773              	.LVL73:
+ 418:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 774              		.loc 1 418 9 is_stmt 1 view .LVU228
+ 418:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       }
+ 775              		.loc 1 418 15 is_stmt 0 view .LVU229
+ 776 0050 0023     		movs	r3, #0
+ 777 0052 1A46     		mov	r2, r3
+ 778 0054 1946     		mov	r1, r3
+ 779 0056 2046     		mov	r0, r4
+ARM GAS  /tmp/ccXNKvGT.s 			page 24
+
+
+ 780 0058 FFF7FEFF 		bl	USBD_LL_PrepareReceive
+ 781              	.LVL74:
+ 782 005c DAE7     		b	.L52
+ 783              	.LVL75:
+ 784              	.L64:
+ 424:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             (pep->total_length < pdev->ep0_data_len))
+ 785              		.loc 1 424 17 discriminator 1 view .LVU230
+ 786 005e 8369     		ldr	r3, [r0, #24]
+ 787              	.LVL76:
+ 423:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             (pep->total_length >= pep->maxpacket) &&
+ 788              		.loc 1 423 49 discriminator 1 view .LVU231
+ 789 0060 9942     		cmp	r1, r3
+ 790 0062 E3D8     		bhi	.L54
+ 425:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         {
+ 791              		.loc 1 425 38 view .LVU232
+ 792 0064 D0F89822 		ldr	r2, [r0, #664]
+ 424:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             (pep->total_length < pdev->ep0_data_len))
+ 793              		.loc 1 424 51 view .LVU233
+ 794 0068 9342     		cmp	r3, r2
+ 795 006a DFD2     		bcs	.L54
+ 427:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           pdev->ep0_data_len = 0U;
+ 796              		.loc 1 427 11 is_stmt 1 view .LVU234
+ 427:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****           pdev->ep0_data_len = 0U;
+ 797              		.loc 1 427 17 is_stmt 0 view .LVU235
+ 798 006c 0022     		movs	r2, #0
+ 799 006e 1146     		mov	r1, r2
+ 800 0070 FFF7FEFF 		bl	USBD_CtlContinueSendData
+ 801              	.LVL77:
+ 428:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 802              		.loc 1 428 11 is_stmt 1 view .LVU236
+ 428:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 803              		.loc 1 428 30 is_stmt 0 view .LVU237
+ 804 0074 0021     		movs	r1, #0
+ 805 0076 C4F89812 		str	r1, [r4, #664]
+ 431:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         }
+ 806              		.loc 1 431 11 is_stmt 1 view .LVU238
+ 431:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         }
+ 807              		.loc 1 431 17 is_stmt 0 view .LVU239
+ 808 007a 0B46     		mov	r3, r1
+ 809 007c 0A46     		mov	r2, r1
+ 810 007e 2046     		mov	r0, r4
+ 811 0080 FFF7FEFF 		bl	USBD_LL_PrepareReceive
+ 812              	.LVL78:
+ 431:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         }
+ 813              		.loc 1 431 11 view .LVU240
+ 814 0084 C6E7     		b	.L52
+ 815              	.LVL79:
+ 816              	.L65:
+ 437:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             {
+ 817              		.loc 1 437 13 is_stmt 1 view .LVU241
+ 437:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             {
+ 818              		.loc 1 437 21 is_stmt 0 view .LVU242
+ 819 0086 D4F8B832 		ldr	r3, [r4, #696]
+ 437:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             {
+ 820              		.loc 1 437 29 view .LVU243
+ 821 008a DB68     		ldr	r3, [r3, #12]
+ 437:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             {
+ARM GAS  /tmp/ccXNKvGT.s 			page 25
+
+
+ 822              		.loc 1 437 16 view .LVU244
+ 823 008c 002B     		cmp	r3, #0
+ 824 008e D2D0     		beq	.L55
+ 439:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             }
+ 825              		.loc 1 439 15 is_stmt 1 view .LVU245
+ 826 0090 2046     		mov	r0, r4
+ 827              	.LVL80:
+ 439:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****             }
+ 828              		.loc 1 439 15 is_stmt 0 view .LVU246
+ 829 0092 9847     		blx	r3
+ 830              	.LVL81:
+ 831 0094 CFE7     		b	.L55
+ 832              	.L62:
+ 460:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       pdev->dev_test_mode = 0U;
+ 833              		.loc 1 460 7 is_stmt 1 view .LVU247
+ 461:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 834              		.loc 1 461 7 view .LVU248
+ 461:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 835              		.loc 1 461 27 is_stmt 0 view .LVU249
+ 836 0096 0023     		movs	r3, #0
+ 837 0098 84F8A032 		strb	r3, [r4, #672]
+ 480:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 838              		.loc 1 480 10 view .LVU250
+ 839 009c 2846     		mov	r0, r5
+ 840 009e BEE7     		b	.L56
+ 841              	.LVL82:
+ 842              	.L51:
+ 466:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 843              		.loc 1 466 5 is_stmt 1 view .LVU251
+ 466:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 844              		.loc 1 466 13 is_stmt 0 view .LVU252
+ 845 00a0 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 846 00a4 DBB2     		uxtb	r3, r3
+ 466:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 847              		.loc 1 466 8 view .LVU253
+ 848 00a6 032B     		cmp	r3, #3
+ 849 00a8 01D0     		beq	.L66
+ 480:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 850              		.loc 1 480 10 view .LVU254
+ 851 00aa 0020     		movs	r0, #0
+ 852              	.LVL83:
+ 480:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 853              		.loc 1 480 10 view .LVU255
+ 854 00ac B7E7     		b	.L56
+ 855              	.LVL84:
+ 856              	.L66:
+ 468:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 857              		.loc 1 468 7 is_stmt 1 view .LVU256
+ 468:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 858              		.loc 1 468 15 is_stmt 0 view .LVU257
+ 859 00ae D0F8B832 		ldr	r3, [r0, #696]
+ 468:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 860              		.loc 1 468 23 view .LVU258
+ 861 00b2 5B69     		ldr	r3, [r3, #20]
+ 468:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       {
+ 862              		.loc 1 468 10 view .LVU259
+ 863 00b4 0BB1     		cbz	r3, .L59
+ARM GAS  /tmp/ccXNKvGT.s 			page 26
+
+
+ 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 864              		.loc 1 470 9 is_stmt 1 view .LVU260
+ 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 865              		.loc 1 470 35 is_stmt 0 view .LVU261
+ 866 00b6 9847     		blx	r3
+ 867              	.LVL85:
+ 472:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****         {
+ 868              		.loc 1 472 9 is_stmt 1 view .LVU262
+ 869 00b8 B1E7     		b	.L56
+ 870              	.LVL86:
+ 871              	.L59:
+ 480:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 872              		.loc 1 480 10 is_stmt 0 view .LVU263
+ 873 00ba 0020     		movs	r0, #0
+ 874              	.LVL87:
+ 480:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 875              		.loc 1 480 10 view .LVU264
+ 876 00bc AFE7     		b	.L56
+ 877              		.cfi_endproc
+ 878              	.LFE343:
+ 880              		.section	.text.USBD_LL_Reset,"ax",%progbits
+ 881              		.align	1
+ 882              		.global	USBD_LL_Reset
+ 883              		.syntax unified
+ 884              		.thumb
+ 885              		.thumb_func
+ 887              	USBD_LL_Reset:
+ 888              	.LVL88:
+ 889              	.LFB344:
+ 482:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 483:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 484:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_LL_Reset
+ 485:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Handle Reset event
+ 486:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 487:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 488:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 489:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 490:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
+ 491:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 890              		.loc 1 491 1 is_stmt 1 view -0
+ 891              		.cfi_startproc
+ 892              		@ args = 0, pretend = 0, frame = 0
+ 893              		@ frame_needed = 0, uses_anonymous_args = 0
+ 492:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Upon Reset call user call back */
+ 493:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->dev_state = USBD_STATE_DEFAULT;
+ 894              		.loc 1 493 3 view .LVU266
+ 895              		.loc 1 493 19 is_stmt 0 view .LVU267
+ 896 0000 0123     		movs	r3, #1
+ 897 0002 80F89C32 		strb	r3, [r0, #668]
+ 494:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->ep0_state = USBD_EP0_IDLE;
+ 898              		.loc 1 494 3 is_stmt 1 view .LVU268
+ 899              		.loc 1 494 19 is_stmt 0 view .LVU269
+ 900 0006 0023     		movs	r3, #0
+ 901 0008 C0F89432 		str	r3, [r0, #660]
+ 495:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->dev_config = 0U;
+ 902              		.loc 1 495 3 is_stmt 1 view .LVU270
+ 903              		.loc 1 495 20 is_stmt 0 view .LVU271
+ARM GAS  /tmp/ccXNKvGT.s 			page 27
+
+
+ 904 000c 4360     		str	r3, [r0, #4]
+ 496:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->dev_remote_wakeup = 0U;
+ 905              		.loc 1 496 3 is_stmt 1 view .LVU272
+ 906              		.loc 1 496 27 is_stmt 0 view .LVU273
+ 907 000e C0F8A432 		str	r3, [r0, #676]
+ 497:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 498:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass == NULL)
+ 908              		.loc 1 498 3 is_stmt 1 view .LVU274
+ 909              		.loc 1 498 11 is_stmt 0 view .LVU275
+ 910 0012 D0F8B832 		ldr	r3, [r0, #696]
+ 911              		.loc 1 498 6 view .LVU276
+ 912 0016 F3B1     		cbz	r3, .L70
+ 491:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Upon Reset call user call back */
+ 913              		.loc 1 491 1 view .LVU277
+ 914 0018 70B5     		push	{r4, r5, r6, lr}
+ 915              	.LCFI14:
+ 916              		.cfi_def_cfa_offset 16
+ 917              		.cfi_offset 4, -16
+ 918              		.cfi_offset 5, -12
+ 919              		.cfi_offset 6, -8
+ 920              		.cfi_offset 14, -4
+ 921 001a 0446     		mov	r4, r0
+ 499:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 500:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     return USBD_FAIL;
+ 501:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 502:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 503:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClassData != NULL)
+ 922              		.loc 1 503 3 is_stmt 1 view .LVU278
+ 923              		.loc 1 503 11 is_stmt 0 view .LVU279
+ 924 001c D0F8BC22 		ldr	r2, [r0, #700]
+ 925              		.loc 1 503 6 view .LVU280
+ 926 0020 1AB1     		cbz	r2, .L69
+ 504:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 505:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     if (pdev->pClass->DeInit != NULL)
+ 927              		.loc 1 505 5 is_stmt 1 view .LVU281
+ 928              		.loc 1 505 21 is_stmt 0 view .LVU282
+ 929 0022 5B68     		ldr	r3, [r3, #4]
+ 930              		.loc 1 505 8 view .LVU283
+ 931 0024 0BB1     		cbz	r3, .L69
+ 506:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 507:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+ 932              		.loc 1 507 7 is_stmt 1 view .LVU284
+ 933              		.loc 1 507 13 is_stmt 0 view .LVU285
+ 934 0026 0021     		movs	r1, #0
+ 935 0028 9847     		blx	r3
+ 936              	.LVL89:
+ 937              	.L69:
+ 508:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 509:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 510:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 511:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Open EP0 OUT */
+ 512:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
+ 938              		.loc 1 512 3 is_stmt 1 view .LVU286
+ 939              		.loc 1 512 9 is_stmt 0 view .LVU287
+ 940 002a 4023     		movs	r3, #64
+ 941 002c 0022     		movs	r2, #0
+ 942 002e 1146     		mov	r1, r2
+ARM GAS  /tmp/ccXNKvGT.s 			page 28
+
+
+ 943 0030 2046     		mov	r0, r4
+ 944 0032 FFF7FEFF 		bl	USBD_LL_OpenEP
+ 945              	.LVL90:
+ 513:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->ep_out[0x00U & 0xFU].is_used = 1U;
+ 946              		.loc 1 513 3 is_stmt 1 view .LVU288
+ 947              		.loc 1 513 38 is_stmt 0 view .LVU289
+ 948 0036 0126     		movs	r6, #1
+ 949 0038 A4F86461 		strh	r6, [r4, #356]	@ movhi
+ 514:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 515:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
+ 950              		.loc 1 515 3 is_stmt 1 view .LVU290
+ 951              		.loc 1 515 29 is_stmt 0 view .LVU291
+ 952 003c 4025     		movs	r5, #64
+ 953 003e C4F86051 		str	r5, [r4, #352]
+ 516:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 517:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Open EP0 IN */
+ 518:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
+ 954              		.loc 1 518 3 is_stmt 1 view .LVU292
+ 955              		.loc 1 518 9 is_stmt 0 view .LVU293
+ 956 0042 2B46     		mov	r3, r5
+ 957 0044 0022     		movs	r2, #0
+ 958 0046 8021     		movs	r1, #128
+ 959 0048 2046     		mov	r0, r4
+ 960 004a FFF7FEFF 		bl	USBD_LL_OpenEP
+ 961              	.LVL91:
+ 519:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->ep_in[0x80U & 0xFU].is_used = 1U;
+ 962              		.loc 1 519 3 is_stmt 1 view .LVU294
+ 963              		.loc 1 519 37 is_stmt 0 view .LVU295
+ 964 004e A684     		strh	r6, [r4, #36]	@ movhi
+ 520:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 521:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
+ 965              		.loc 1 521 3 is_stmt 1 view .LVU296
+ 966              		.loc 1 521 28 is_stmt 0 view .LVU297
+ 967 0050 2562     		str	r5, [r4, #32]
+ 522:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 523:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 968              		.loc 1 523 3 is_stmt 1 view .LVU298
+ 969              		.loc 1 523 10 is_stmt 0 view .LVU299
+ 970 0052 0020     		movs	r0, #0
+ 524:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 971              		.loc 1 524 1 view .LVU300
+ 972 0054 70BD     		pop	{r4, r5, r6, pc}
+ 973              	.LVL92:
+ 974              	.L70:
+ 975              	.LCFI15:
+ 976              		.cfi_def_cfa_offset 0
+ 977              		.cfi_restore 4
+ 978              		.cfi_restore 5
+ 979              		.cfi_restore 6
+ 980              		.cfi_restore 14
+ 500:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 981              		.loc 1 500 12 view .LVU301
+ 982 0056 0320     		movs	r0, #3
+ 983              	.LVL93:
+ 984              		.loc 1 524 1 view .LVU302
+ 985 0058 7047     		bx	lr
+ 986              		.cfi_endproc
+ARM GAS  /tmp/ccXNKvGT.s 			page 29
+
+
+ 987              	.LFE344:
+ 989              		.section	.text.USBD_LL_SetSpeed,"ax",%progbits
+ 990              		.align	1
+ 991              		.global	USBD_LL_SetSpeed
+ 992              		.syntax unified
+ 993              		.thumb
+ 994              		.thumb_func
+ 996              	USBD_LL_SetSpeed:
+ 997              	.LVL94:
+ 998              	.LFB345:
+ 525:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 526:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 527:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_LL_SetSpeed
+ 528:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Handle Reset event
+ 529:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 530:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 531:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 532:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
+ 533:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****                                     USBD_SpeedTypeDef speed)
+ 534:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 999              		.loc 1 534 1 is_stmt 1 view -0
+ 1000              		.cfi_startproc
+ 1001              		@ args = 0, pretend = 0, frame = 0
+ 1002              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1003              		@ link register save eliminated.
+ 535:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->dev_speed = speed;
+ 1004              		.loc 1 535 3 view .LVU304
+ 1005              		.loc 1 535 19 is_stmt 0 view .LVU305
+ 1006 0000 0174     		strb	r1, [r0, #16]
+ 536:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 537:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 1007              		.loc 1 537 3 is_stmt 1 view .LVU306
+ 538:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1008              		.loc 1 538 1 is_stmt 0 view .LVU307
+ 1009 0002 0020     		movs	r0, #0
+ 1010              	.LVL95:
+ 1011              		.loc 1 538 1 view .LVU308
+ 1012 0004 7047     		bx	lr
+ 1013              		.cfi_endproc
+ 1014              	.LFE345:
+ 1016              		.section	.text.USBD_LL_Suspend,"ax",%progbits
+ 1017              		.align	1
+ 1018              		.global	USBD_LL_Suspend
+ 1019              		.syntax unified
+ 1020              		.thumb
+ 1021              		.thumb_func
+ 1023              	USBD_LL_Suspend:
+ 1024              	.LVL96:
+ 1025              	.LFB346:
+ 539:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 540:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 541:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_LL_Suspend
+ 542:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Handle Suspend event
+ 543:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 544:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 545:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 546:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ARM GAS  /tmp/ccXNKvGT.s 			page 30
+
+
+ 547:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
+ 548:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 1026              		.loc 1 548 1 is_stmt 1 view -0
+ 1027              		.cfi_startproc
+ 1028              		@ args = 0, pretend = 0, frame = 0
+ 1029              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1030              		@ link register save eliminated.
+ 549:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->dev_old_state = pdev->dev_state;
+ 1031              		.loc 1 549 3 view .LVU310
+ 1032              		.loc 1 549 29 is_stmt 0 view .LVU311
+ 1033 0000 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 1034 0004 DBB2     		uxtb	r3, r3
+ 1035              		.loc 1 549 23 view .LVU312
+ 1036 0006 80F89D32 		strb	r3, [r0, #669]
+ 550:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->dev_state = USBD_STATE_SUSPENDED;
+ 1037              		.loc 1 550 3 is_stmt 1 view .LVU313
+ 1038              		.loc 1 550 19 is_stmt 0 view .LVU314
+ 1039 000a 0423     		movs	r3, #4
+ 1040 000c 80F89C32 		strb	r3, [r0, #668]
+ 551:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 552:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 1041              		.loc 1 552 3 is_stmt 1 view .LVU315
+ 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1042              		.loc 1 553 1 is_stmt 0 view .LVU316
+ 1043 0010 0020     		movs	r0, #0
+ 1044              	.LVL97:
+ 1045              		.loc 1 553 1 view .LVU317
+ 1046 0012 7047     		bx	lr
+ 1047              		.cfi_endproc
+ 1048              	.LFE346:
+ 1050              		.section	.text.USBD_LL_Resume,"ax",%progbits
+ 1051              		.align	1
+ 1052              		.global	USBD_LL_Resume
+ 1053              		.syntax unified
+ 1054              		.thumb
+ 1055              		.thumb_func
+ 1057              	USBD_LL_Resume:
+ 1058              	.LVL98:
+ 1059              	.LFB347:
+ 554:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 555:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 556:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_LL_Resume
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Handle Resume event
+ 558:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 559:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 560:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 561:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 562:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
+ 563:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 1060              		.loc 1 563 1 is_stmt 1 view -0
+ 1061              		.cfi_startproc
+ 1062              		@ args = 0, pretend = 0, frame = 0
+ 1063              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1064              		@ link register save eliminated.
+ 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->dev_state == USBD_STATE_SUSPENDED)
+ 1065              		.loc 1 564 3 view .LVU319
+ 1066              		.loc 1 564 11 is_stmt 0 view .LVU320
+ARM GAS  /tmp/ccXNKvGT.s 			page 31
+
+
+ 1067 0000 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 1068 0004 DBB2     		uxtb	r3, r3
+ 1069              		.loc 1 564 6 view .LVU321
+ 1070 0006 042B     		cmp	r3, #4
+ 1071 0008 01D0     		beq	.L79
+ 1072              	.L78:
+ 565:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 566:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     pdev->dev_state = pdev->dev_old_state;
+ 567:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 568:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 569:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 1073              		.loc 1 569 3 is_stmt 1 view .LVU322
+ 570:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1074              		.loc 1 570 1 is_stmt 0 view .LVU323
+ 1075 000a 0020     		movs	r0, #0
+ 1076              	.LVL99:
+ 1077              		.loc 1 570 1 view .LVU324
+ 1078 000c 7047     		bx	lr
+ 1079              	.LVL100:
+ 1080              	.L79:
+ 566:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 1081              		.loc 1 566 5 is_stmt 1 view .LVU325
+ 566:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 1082              		.loc 1 566 27 is_stmt 0 view .LVU326
+ 1083 000e 90F89D32 		ldrb	r3, [r0, #669]	@ zero_extendqisi2
+ 1084 0012 DBB2     		uxtb	r3, r3
+ 566:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 1085              		.loc 1 566 21 view .LVU327
+ 1086 0014 80F89C32 		strb	r3, [r0, #668]
+ 1087 0018 F7E7     		b	.L78
+ 1088              		.cfi_endproc
+ 1089              	.LFE347:
+ 1091              		.section	.text.USBD_LL_SOF,"ax",%progbits
+ 1092              		.align	1
+ 1093              		.global	USBD_LL_SOF
+ 1094              		.syntax unified
+ 1095              		.thumb
+ 1096              		.thumb_func
+ 1098              	USBD_LL_SOF:
+ 1099              	.LVL101:
+ 1100              	.LFB348:
+ 571:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 572:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 573:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_LL_SOF
+ 574:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Handle SOF event
+ 575:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 576:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 577:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 578:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 579:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
+ 580:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 1101              		.loc 1 580 1 is_stmt 1 view -0
+ 1102              		.cfi_startproc
+ 1103              		@ args = 0, pretend = 0, frame = 0
+ 1104              		@ frame_needed = 0, uses_anonymous_args = 0
+ 581:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass == NULL)
+ 1105              		.loc 1 581 3 view .LVU329
+ARM GAS  /tmp/ccXNKvGT.s 			page 32
+
+
+ 1106              		.loc 1 581 11 is_stmt 0 view .LVU330
+ 1107 0000 D0F8B822 		ldr	r2, [r0, #696]
+ 1108              		.loc 1 581 6 view .LVU331
+ 1109 0004 62B1     		cbz	r2, .L82
+ 580:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass == NULL)
+ 1110              		.loc 1 580 1 view .LVU332
+ 1111 0006 08B5     		push	{r3, lr}
+ 1112              	.LCFI16:
+ 1113              		.cfi_def_cfa_offset 8
+ 1114              		.cfi_offset 3, -8
+ 1115              		.cfi_offset 14, -4
+ 582:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 583:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     return USBD_FAIL;
+ 584:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 585:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 586:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->dev_state == USBD_STATE_CONFIGURED)
+ 1116              		.loc 1 586 3 is_stmt 1 view .LVU333
+ 1117              		.loc 1 586 11 is_stmt 0 view .LVU334
+ 1118 0008 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 1119 000c DBB2     		uxtb	r3, r3
+ 1120              		.loc 1 586 6 view .LVU335
+ 1121 000e 032B     		cmp	r3, #3
+ 1122 0010 01D0     		beq	.L89
+ 587:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 588:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     if (pdev->pClass->SOF != NULL)
+ 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 590:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       (void)pdev->pClass->SOF(pdev);
+ 591:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 592:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 593:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 594:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 1123              		.loc 1 594 10 view .LVU336
+ 1124 0012 0020     		movs	r0, #0
+ 1125              	.LVL102:
+ 1126              	.L81:
+ 595:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1127              		.loc 1 595 1 view .LVU337
+ 1128 0014 08BD     		pop	{r3, pc}
+ 1129              	.LVL103:
+ 1130              	.L89:
+ 588:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 1131              		.loc 1 588 5 is_stmt 1 view .LVU338
+ 588:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 1132              		.loc 1 588 21 is_stmt 0 view .LVU339
+ 1133 0016 D369     		ldr	r3, [r2, #28]
+ 588:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 1134              		.loc 1 588 8 view .LVU340
+ 1135 0018 23B1     		cbz	r3, .L84
+ 590:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 1136              		.loc 1 590 7 is_stmt 1 view .LVU341
+ 590:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 1137              		.loc 1 590 13 is_stmt 0 view .LVU342
+ 1138 001a 9847     		blx	r3
+ 1139              	.LVL104:
+ 594:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1140              		.loc 1 594 10 view .LVU343
+ 1141 001c 0020     		movs	r0, #0
+ARM GAS  /tmp/ccXNKvGT.s 			page 33
+
+
+ 1142 001e F9E7     		b	.L81
+ 1143              	.LVL105:
+ 1144              	.L82:
+ 1145              	.LCFI17:
+ 1146              		.cfi_def_cfa_offset 0
+ 1147              		.cfi_restore 3
+ 1148              		.cfi_restore 14
+ 583:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 1149              		.loc 1 583 12 view .LVU344
+ 1150 0020 0320     		movs	r0, #3
+ 1151              	.LVL106:
+ 1152              		.loc 1 595 1 view .LVU345
+ 1153 0022 7047     		bx	lr
+ 1154              	.LVL107:
+ 1155              	.L84:
+ 1156              	.LCFI18:
+ 1157              		.cfi_def_cfa_offset 8
+ 1158              		.cfi_offset 3, -8
+ 1159              		.cfi_offset 14, -4
+ 594:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1160              		.loc 1 594 10 view .LVU346
+ 1161 0024 0020     		movs	r0, #0
+ 1162              	.LVL108:
+ 594:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1163              		.loc 1 594 10 view .LVU347
+ 1164 0026 F5E7     		b	.L81
+ 1165              		.cfi_endproc
+ 1166              	.LFE348:
+ 1168              		.section	.text.USBD_LL_IsoINIncomplete,"ax",%progbits
+ 1169              		.align	1
+ 1170              		.global	USBD_LL_IsoINIncomplete
+ 1171              		.syntax unified
+ 1172              		.thumb
+ 1173              		.thumb_func
+ 1175              	USBD_LL_IsoINIncomplete:
+ 1176              	.LVL109:
+ 1177              	.LFB349:
+ 596:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 597:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 598:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_LL_IsoINIncomplete
+ 599:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Handle iso in incomplete event
+ 600:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 601:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 602:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 603:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
+ 604:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****                                            uint8_t epnum)
+ 605:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 1178              		.loc 1 605 1 is_stmt 1 view -0
+ 1179              		.cfi_startproc
+ 1180              		@ args = 0, pretend = 0, frame = 0
+ 1181              		@ frame_needed = 0, uses_anonymous_args = 0
+ 606:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass == NULL)
+ 1182              		.loc 1 606 3 view .LVU349
+ 1183              		.loc 1 606 11 is_stmt 0 view .LVU350
+ 1184 0000 D0F8B822 		ldr	r2, [r0, #696]
+ 1185              		.loc 1 606 6 view .LVU351
+ 1186 0004 62B1     		cbz	r2, .L92
+ARM GAS  /tmp/ccXNKvGT.s 			page 34
+
+
+ 605:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass == NULL)
+ 1187              		.loc 1 605 1 view .LVU352
+ 1188 0006 08B5     		push	{r3, lr}
+ 1189              	.LCFI19:
+ 1190              		.cfi_def_cfa_offset 8
+ 1191              		.cfi_offset 3, -8
+ 1192              		.cfi_offset 14, -4
+ 607:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 608:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     return USBD_FAIL;
+ 609:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 610:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 611:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->dev_state == USBD_STATE_CONFIGURED)
+ 1193              		.loc 1 611 3 is_stmt 1 view .LVU353
+ 1194              		.loc 1 611 11 is_stmt 0 view .LVU354
+ 1195 0008 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 1196 000c DBB2     		uxtb	r3, r3
+ 1197              		.loc 1 611 6 view .LVU355
+ 1198 000e 032B     		cmp	r3, #3
+ 1199 0010 01D0     		beq	.L99
+ 612:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 613:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     if (pdev->pClass->IsoINIncomplete != NULL)
+ 614:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 615:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       (void)pdev->pClass->IsoINIncomplete(pdev, epnum);
+ 616:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 617:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 618:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 619:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 1200              		.loc 1 619 10 view .LVU356
+ 1201 0012 0020     		movs	r0, #0
+ 1202              	.LVL110:
+ 1203              	.L91:
+ 620:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1204              		.loc 1 620 1 view .LVU357
+ 1205 0014 08BD     		pop	{r3, pc}
+ 1206              	.LVL111:
+ 1207              	.L99:
+ 613:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 1208              		.loc 1 613 5 is_stmt 1 view .LVU358
+ 613:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 1209              		.loc 1 613 21 is_stmt 0 view .LVU359
+ 1210 0016 136A     		ldr	r3, [r2, #32]
+ 613:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 1211              		.loc 1 613 8 view .LVU360
+ 1212 0018 23B1     		cbz	r3, .L94
+ 615:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 1213              		.loc 1 615 7 is_stmt 1 view .LVU361
+ 615:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 1214              		.loc 1 615 13 is_stmt 0 view .LVU362
+ 1215 001a 9847     		blx	r3
+ 1216              	.LVL112:
+ 619:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1217              		.loc 1 619 10 view .LVU363
+ 1218 001c 0020     		movs	r0, #0
+ 1219 001e F9E7     		b	.L91
+ 1220              	.LVL113:
+ 1221              	.L92:
+ 1222              	.LCFI20:
+ARM GAS  /tmp/ccXNKvGT.s 			page 35
+
+
+ 1223              		.cfi_def_cfa_offset 0
+ 1224              		.cfi_restore 3
+ 1225              		.cfi_restore 14
+ 608:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 1226              		.loc 1 608 12 view .LVU364
+ 1227 0020 0320     		movs	r0, #3
+ 1228              	.LVL114:
+ 1229              		.loc 1 620 1 view .LVU365
+ 1230 0022 7047     		bx	lr
+ 1231              	.LVL115:
+ 1232              	.L94:
+ 1233              	.LCFI21:
+ 1234              		.cfi_def_cfa_offset 8
+ 1235              		.cfi_offset 3, -8
+ 1236              		.cfi_offset 14, -4
+ 619:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1237              		.loc 1 619 10 view .LVU366
+ 1238 0024 0020     		movs	r0, #0
+ 1239              	.LVL116:
+ 619:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1240              		.loc 1 619 10 view .LVU367
+ 1241 0026 F5E7     		b	.L91
+ 1242              		.cfi_endproc
+ 1243              	.LFE349:
+ 1245              		.section	.text.USBD_LL_IsoOUTIncomplete,"ax",%progbits
+ 1246              		.align	1
+ 1247              		.global	USBD_LL_IsoOUTIncomplete
+ 1248              		.syntax unified
+ 1249              		.thumb
+ 1250              		.thumb_func
+ 1252              	USBD_LL_IsoOUTIncomplete:
+ 1253              	.LVL117:
+ 1254              	.LFB350:
+ 621:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 622:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 623:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_LL_IsoOUTIncomplete
+ 624:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Handle iso out incomplete event
+ 625:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 626:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 627:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 628:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
+ 629:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****                                             uint8_t epnum)
+ 630:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 1255              		.loc 1 630 1 is_stmt 1 view -0
+ 1256              		.cfi_startproc
+ 1257              		@ args = 0, pretend = 0, frame = 0
+ 1258              		@ frame_needed = 0, uses_anonymous_args = 0
+ 631:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass == NULL)
+ 1259              		.loc 1 631 3 view .LVU369
+ 1260              		.loc 1 631 11 is_stmt 0 view .LVU370
+ 1261 0000 D0F8B822 		ldr	r2, [r0, #696]
+ 1262              		.loc 1 631 6 view .LVU371
+ 1263 0004 62B1     		cbz	r2, .L102
+ 630:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass == NULL)
+ 1264              		.loc 1 630 1 view .LVU372
+ 1265 0006 08B5     		push	{r3, lr}
+ 1266              	.LCFI22:
+ARM GAS  /tmp/ccXNKvGT.s 			page 36
+
+
+ 1267              		.cfi_def_cfa_offset 8
+ 1268              		.cfi_offset 3, -8
+ 1269              		.cfi_offset 14, -4
+ 632:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 633:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     return USBD_FAIL;
+ 634:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 635:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 636:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->dev_state == USBD_STATE_CONFIGURED)
+ 1270              		.loc 1 636 3 is_stmt 1 view .LVU373
+ 1271              		.loc 1 636 11 is_stmt 0 view .LVU374
+ 1272 0008 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 1273 000c DBB2     		uxtb	r3, r3
+ 1274              		.loc 1 636 6 view .LVU375
+ 1275 000e 032B     		cmp	r3, #3
+ 1276 0010 01D0     		beq	.L109
+ 637:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 638:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     if (pdev->pClass->IsoOUTIncomplete != NULL)
+ 639:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 640:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****       (void)pdev->pClass->IsoOUTIncomplete(pdev, epnum);
+ 641:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 642:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 643:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 644:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 1277              		.loc 1 644 10 view .LVU376
+ 1278 0012 0020     		movs	r0, #0
+ 1279              	.LVL118:
+ 1280              	.L101:
+ 645:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1281              		.loc 1 645 1 view .LVU377
+ 1282 0014 08BD     		pop	{r3, pc}
+ 1283              	.LVL119:
+ 1284              	.L109:
+ 638:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 1285              		.loc 1 638 5 is_stmt 1 view .LVU378
+ 638:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 1286              		.loc 1 638 21 is_stmt 0 view .LVU379
+ 1287 0016 536A     		ldr	r3, [r2, #36]
+ 638:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     {
+ 1288              		.loc 1 638 8 view .LVU380
+ 1289 0018 23B1     		cbz	r3, .L104
+ 640:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 1290              		.loc 1 640 7 is_stmt 1 view .LVU381
+ 640:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     }
+ 1291              		.loc 1 640 13 is_stmt 0 view .LVU382
+ 1292 001a 9847     		blx	r3
+ 1293              	.LVL120:
+ 644:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1294              		.loc 1 644 10 view .LVU383
+ 1295 001c 0020     		movs	r0, #0
+ 1296 001e F9E7     		b	.L101
+ 1297              	.LVL121:
+ 1298              	.L102:
+ 1299              	.LCFI23:
+ 1300              		.cfi_def_cfa_offset 0
+ 1301              		.cfi_restore 3
+ 1302              		.cfi_restore 14
+ 633:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ARM GAS  /tmp/ccXNKvGT.s 			page 37
+
+
+ 1303              		.loc 1 633 12 view .LVU384
+ 1304 0020 0320     		movs	r0, #3
+ 1305              	.LVL122:
+ 1306              		.loc 1 645 1 view .LVU385
+ 1307 0022 7047     		bx	lr
+ 1308              	.LVL123:
+ 1309              	.L104:
+ 1310              	.LCFI24:
+ 1311              		.cfi_def_cfa_offset 8
+ 1312              		.cfi_offset 3, -8
+ 1313              		.cfi_offset 14, -4
+ 644:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1314              		.loc 1 644 10 view .LVU386
+ 1315 0024 0020     		movs	r0, #0
+ 1316              	.LVL124:
+ 644:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1317              		.loc 1 644 10 view .LVU387
+ 1318 0026 F5E7     		b	.L101
+ 1319              		.cfi_endproc
+ 1320              	.LFE350:
+ 1322              		.section	.text.USBD_LL_DevConnected,"ax",%progbits
+ 1323              		.align	1
+ 1324              		.global	USBD_LL_DevConnected
+ 1325              		.syntax unified
+ 1326              		.thumb
+ 1327              		.thumb_func
+ 1329              	USBD_LL_DevConnected:
+ 1330              	.LVL125:
+ 1331              	.LFB351:
+ 646:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 647:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 648:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_LL_DevConnected
+ 649:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Handle device connection event
+ 650:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 651:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 652:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 653:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
+ 654:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 1332              		.loc 1 654 1 is_stmt 1 view -0
+ 1333              		.cfi_startproc
+ 1334              		@ args = 0, pretend = 0, frame = 0
+ 1335              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1336              		@ link register save eliminated.
+ 655:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Prevent unused argument compilation warning */
+ 656:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   UNUSED(pdev);
+ 1337              		.loc 1 656 3 view .LVU389
+ 657:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 658:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 1338              		.loc 1 658 3 view .LVU390
+ 659:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1339              		.loc 1 659 1 is_stmt 0 view .LVU391
+ 1340 0000 0020     		movs	r0, #0
+ 1341              	.LVL126:
+ 1342              		.loc 1 659 1 view .LVU392
+ 1343 0002 7047     		bx	lr
+ 1344              		.cfi_endproc
+ 1345              	.LFE351:
+ARM GAS  /tmp/ccXNKvGT.s 			page 38
+
+
+ 1347              		.section	.text.USBD_LL_DevDisconnected,"ax",%progbits
+ 1348              		.align	1
+ 1349              		.global	USBD_LL_DevDisconnected
+ 1350              		.syntax unified
+ 1351              		.thumb
+ 1352              		.thumb_func
+ 1354              	USBD_LL_DevDisconnected:
+ 1355              	.LVL127:
+ 1356              	.LFB352:
+ 660:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 661:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /**
+ 662:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @brief  USBD_LL_DevDisconnected
+ 663:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   *         Handle device disconnection event
+ 664:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @param  pdev: device instance
+ 665:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   * @retval status
+ 666:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   */
+ 667:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
+ 668:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** {
+ 1357              		.loc 1 668 1 is_stmt 1 view -0
+ 1358              		.cfi_startproc
+ 1359              		@ args = 0, pretend = 0, frame = 0
+ 1360              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1361              		.loc 1 668 1 is_stmt 0 view .LVU394
+ 1362 0000 08B5     		push	{r3, lr}
+ 1363              	.LCFI25:
+ 1364              		.cfi_def_cfa_offset 8
+ 1365              		.cfi_offset 3, -8
+ 1366              		.cfi_offset 14, -4
+ 669:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   /* Free Class Resources */
+ 670:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   pdev->dev_state = USBD_STATE_DEFAULT;
+ 1367              		.loc 1 670 3 is_stmt 1 view .LVU395
+ 1368              		.loc 1 670 19 is_stmt 0 view .LVU396
+ 1369 0002 0123     		movs	r3, #1
+ 1370 0004 80F89C32 		strb	r3, [r0, #668]
+ 671:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 672:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   if (pdev->pClass != NULL)
+ 1371              		.loc 1 672 3 is_stmt 1 view .LVU397
+ 1372              		.loc 1 672 11 is_stmt 0 view .LVU398
+ 1373 0008 D0F8B832 		ldr	r3, [r0, #696]
+ 1374              		.loc 1 672 6 view .LVU399
+ 1375 000c 13B1     		cbz	r3, .L112
+ 673:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   {
+ 674:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****     (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+ 1376              		.loc 1 674 5 is_stmt 1 view .LVU400
+ 1377              		.loc 1 674 23 is_stmt 0 view .LVU401
+ 1378 000e 5B68     		ldr	r3, [r3, #4]
+ 1379              		.loc 1 674 11 view .LVU402
+ 1380 0010 0179     		ldrb	r1, [r0, #4]	@ zero_extendqisi2
+ 1381 0012 9847     		blx	r3
+ 1382              	.LVL128:
+ 1383              	.L112:
+ 675:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   }
+ 676:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** 
+ 677:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c ****   return USBD_OK;
+ 1384              		.loc 1 677 3 is_stmt 1 view .LVU403
+ 678:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** }
+ 1385              		.loc 1 678 1 is_stmt 0 view .LVU404
+ARM GAS  /tmp/ccXNKvGT.s 			page 39
+
+
+ 1386 0014 0020     		movs	r0, #0
+ 1387 0016 08BD     		pop	{r3, pc}
+ 1388              		.cfi_endproc
+ 1389              	.LFE352:
+ 1391              		.text
+ 1392              	.Letext0:
+ 1393              		.file 2 "/usr/include/newlib/machine/_default_types.h"
+ 1394              		.file 3 "/usr/include/newlib/sys/_stdint.h"
+ 1395              		.file 4 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h"
+ 1396              		.file 5 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h"
+ 1397              		.file 6 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h"
+ 1398              		.file 7 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h"
+ARM GAS  /tmp/ccXNKvGT.s 			page 40
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 usbd_core.c
+     /tmp/ccXNKvGT.s:21     .text.USBD_Init:00000000 $t
+     /tmp/ccXNKvGT.s:27     .text.USBD_Init:00000000 USBD_Init
+     /tmp/ccXNKvGT.s:96     .text.USBD_DeInit:00000000 $t
+     /tmp/ccXNKvGT.s:102    .text.USBD_DeInit:00000000 USBD_DeInit
+     /tmp/ccXNKvGT.s:166    .text.USBD_RegisterClass:00000000 $t
+     /tmp/ccXNKvGT.s:172    .text.USBD_RegisterClass:00000000 USBD_RegisterClass
+     /tmp/ccXNKvGT.s:244    .text.USBD_Start:00000000 $t
+     /tmp/ccXNKvGT.s:250    .text.USBD_Start:00000000 USBD_Start
+     /tmp/ccXNKvGT.s:273    .text.USBD_Stop:00000000 $t
+     /tmp/ccXNKvGT.s:279    .text.USBD_Stop:00000000 USBD_Stop
+     /tmp/ccXNKvGT.s:320    .text.USBD_RunTestMode:00000000 $t
+     /tmp/ccXNKvGT.s:326    .text.USBD_RunTestMode:00000000 USBD_RunTestMode
+     /tmp/ccXNKvGT.s:345    .text.USBD_SetClassConfig:00000000 $t
+     /tmp/ccXNKvGT.s:351    .text.USBD_SetClassConfig:00000000 USBD_SetClassConfig
+     /tmp/ccXNKvGT.s:392    .text.USBD_ClrClassConfig:00000000 $t
+     /tmp/ccXNKvGT.s:398    .text.USBD_ClrClassConfig:00000000 USBD_ClrClassConfig
+     /tmp/ccXNKvGT.s:431    .text.USBD_LL_SetupStage:00000000 $t
+     /tmp/ccXNKvGT.s:437    .text.USBD_LL_SetupStage:00000000 USBD_LL_SetupStage
+     /tmp/ccXNKvGT.s:525    .text.USBD_LL_DataOutStage:00000000 $t
+     /tmp/ccXNKvGT.s:531    .text.USBD_LL_DataOutStage:00000000 USBD_LL_DataOutStage
+     /tmp/ccXNKvGT.s:671    .text.USBD_LL_DataInStage:00000000 $t
+     /tmp/ccXNKvGT.s:677    .text.USBD_LL_DataInStage:00000000 USBD_LL_DataInStage
+     /tmp/ccXNKvGT.s:881    .text.USBD_LL_Reset:00000000 $t
+     /tmp/ccXNKvGT.s:887    .text.USBD_LL_Reset:00000000 USBD_LL_Reset
+     /tmp/ccXNKvGT.s:990    .text.USBD_LL_SetSpeed:00000000 $t
+     /tmp/ccXNKvGT.s:996    .text.USBD_LL_SetSpeed:00000000 USBD_LL_SetSpeed
+     /tmp/ccXNKvGT.s:1017   .text.USBD_LL_Suspend:00000000 $t
+     /tmp/ccXNKvGT.s:1023   .text.USBD_LL_Suspend:00000000 USBD_LL_Suspend
+     /tmp/ccXNKvGT.s:1051   .text.USBD_LL_Resume:00000000 $t
+     /tmp/ccXNKvGT.s:1057   .text.USBD_LL_Resume:00000000 USBD_LL_Resume
+     /tmp/ccXNKvGT.s:1092   .text.USBD_LL_SOF:00000000 $t
+     /tmp/ccXNKvGT.s:1098   .text.USBD_LL_SOF:00000000 USBD_LL_SOF
+     /tmp/ccXNKvGT.s:1169   .text.USBD_LL_IsoINIncomplete:00000000 $t
+     /tmp/ccXNKvGT.s:1175   .text.USBD_LL_IsoINIncomplete:00000000 USBD_LL_IsoINIncomplete
+     /tmp/ccXNKvGT.s:1246   .text.USBD_LL_IsoOUTIncomplete:00000000 $t
+     /tmp/ccXNKvGT.s:1252   .text.USBD_LL_IsoOUTIncomplete:00000000 USBD_LL_IsoOUTIncomplete
+     /tmp/ccXNKvGT.s:1323   .text.USBD_LL_DevConnected:00000000 $t
+     /tmp/ccXNKvGT.s:1329   .text.USBD_LL_DevConnected:00000000 USBD_LL_DevConnected
+     /tmp/ccXNKvGT.s:1348   .text.USBD_LL_DevDisconnected:00000000 $t
+     /tmp/ccXNKvGT.s:1354   .text.USBD_LL_DevDisconnected:00000000 USBD_LL_DevDisconnected
+
+UNDEFINED SYMBOLS
+USBD_LL_Init
+USBD_LL_Stop
+USBD_LL_DeInit
+USBD_LL_Start
+USBD_ParseSetupRequest
+USBD_LL_StallEP
+USBD_StdDevReq
+USBD_StdItfReq
+USBD_StdEPReq
+USBD_CtlSendStatus
+USBD_CtlContinueRx
+USBD_CtlReceiveStatus
+USBD_CtlContinueSendData
+ARM GAS  /tmp/ccXNKvGT.s 			page 41
+
+
+USBD_LL_PrepareReceive
+USBD_LL_OpenEP
diff --git a/squeow_sw/build/usbd_core.o b/squeow_sw/build/usbd_core.o
new file mode 100644
index 0000000000000000000000000000000000000000..b05106bd23c1fb95112ebd7b27585edc1a597b8a
GIT binary patch
literal 26720
zcmeI433yf2x%c-zL&!u<NCJdGIUx*D$Usm)1!N2a88V<n9Abt8i493iP8e#vQbeoP
zI+a?iws5OfYi$)Pm20&{#o<=lMyr-;TkW+LrIW4NM%!Dz|9`FjK4+gp?Ct%Y?>^7>
zJ<qpcpWlApcdd85YuIbAz0b+Mbm__(*L59lbDc6LDLGF21;!FS$)L=c=~O$r_hs%6
z);Q6}2M+`uA3TWt*+AC5#|IxMa7!*5ytQC#PjStMfBE}|nU4gcJ<Ia<hm7Qw?i{?e
z`h~#*)r<F?(_XSITC;nZQ+f#Up}~XIJbC~}&sIlG>ikFY_wTsRDgDM^Mpg5^P|d-?
z0|n1qc*efrf6Q=pFGIS36Aj##j}rcR#EHItBy+zl(JPJRj7ydi&40u}ESdWUpfB7v
zu6_41M)x=5qb3I_5luAnkvWLg`P1E#%M|mW!Clo44Bm&xc31Bjyt}}CdqU8iHhds3
zEq`FzKKJeIu8lYN+6guGXwD<v(fdcdqj!(c@9>(1-zlsa7~C~6c%nOySu^L6fx&Y}
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diff --git a/squeow_sw/build/usbd_ctlreq.d b/squeow_sw/build/usbd_ctlreq.d
new file mode 100644
index 0000000..3368e96
--- /dev/null
+++ b/squeow_sw/build/usbd_ctlreq.d
@@ -0,0 +1,87 @@
+build/usbd_ctlreq.o: \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \
+ Inc/usbd_conf.h Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
+Inc/usbd_conf.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h:
diff --git a/squeow_sw/build/usbd_ctlreq.lst b/squeow_sw/build/usbd_ctlreq.lst
new file mode 100644
index 0000000..a8d58ac
--- /dev/null
+++ b/squeow_sw/build/usbd_ctlreq.lst
@@ -0,0 +1,4356 @@
+ARM GAS  /tmp/ccQ58aJU.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"usbd_ctlreq.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c"
+  20              		.section	.text.USBD_GetLen,"ax",%progbits
+  21              		.align	1
+  22              		.syntax unified
+  23              		.thumb
+  24              		.thumb_func
+  26              	USBD_GetLen:
+  27              	.LVL0:
+  28              	.LFB346:
+   1:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+   2:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   ******************************************************************************
+   3:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @file    usbd_req.c
+   4:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @author  MCD Application Team
+   5:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief   This file provides the standard USB requests following chapter 9.
+   6:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   ******************************************************************************
+   7:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @attention
+   8:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *
+   9:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  10:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * All rights reserved.</center></h2>
+  11:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *
+  12:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * This software component is licensed by ST under Ultimate Liberty license
+  13:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * SLA0044, the "License"; You may not use this file except in compliance with
+  14:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * the License. You may obtain a copy of the License at:
+  15:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *                      www.st.com/SLA0044
+  16:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *
+  17:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   ******************************************************************************
+  18:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  19:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  20:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /* Includes ------------------------------------------------------------------*/
+  21:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #include "usbd_ctlreq.h"
+  22:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #include "usbd_ioreq.h"
+  23:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  24:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  25:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY
+  26:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @{
+  27:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  28:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  29:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  30:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ
+ARM GAS  /tmp/ccQ58aJU.s 			page 2
+
+
+  31:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief USB standard requests module
+  32:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @{
+  33:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  34:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  35:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ_Private_TypesDefinitions
+  36:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @{
+  37:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  38:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  39:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+  40:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @}
+  41:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  42:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  43:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  44:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ_Private_Defines
+  45:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @{
+  46:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  47:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  48:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+  49:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @}
+  50:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  51:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  52:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  53:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ_Private_Macros
+  54:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @{
+  55:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  56:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  57:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+  58:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @}
+  59:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  60:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  61:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  62:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ_Private_Variables
+  63:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @{
+  64:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  65:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  66:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+  67:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @}
+  68:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  69:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  70:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  71:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ_Private_FunctionPrototypes
+  72:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @{
+  73:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  74:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+  75:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+  76:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+  77:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+  78:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+  79:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+  80:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+  81:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static uint8_t USBD_GetLen(uint8_t *buf);
+  82:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  83:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+  84:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @}
+  85:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  86:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  87:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ARM GAS  /tmp/ccQ58aJU.s 			page 3
+
+
+  88:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ_Private_Functions
+  89:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @{
+  90:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+  91:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  92:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  93:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+  94:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_StdDevReq
+  95:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Handle standard usb device requests
+  96:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  pdev: device instance
+  97:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  req: usb request
+  98:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval status
+  99:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 100:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 101:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 102:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 103:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 104:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   switch (req->bmRequest & USB_REQ_TYPE_MASK)
+ 105:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 106:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_REQ_TYPE_CLASS:
+ 107:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_REQ_TYPE_VENDOR:
+ 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+ 109:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 110:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 111:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_REQ_TYPE_STANDARD:
+ 112:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       switch (req->bRequest)
+ 113:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 114:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USB_REQ_GET_DESCRIPTOR:
+ 115:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           USBD_GetDescriptor(pdev, req);
+ 116:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 117:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 118:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USB_REQ_SET_ADDRESS:
+ 119:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           USBD_SetAddress(pdev, req);
+ 120:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 121:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 122:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USB_REQ_SET_CONFIGURATION:
+ 123:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           ret = USBD_SetConfig(pdev, req);
+ 124:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 125:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 126:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USB_REQ_GET_CONFIGURATION:
+ 127:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           USBD_GetConfig(pdev, req);
+ 128:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 129:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 130:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USB_REQ_GET_STATUS:
+ 131:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           USBD_GetStatus(pdev, req);
+ 132:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 133:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 134:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USB_REQ_SET_FEATURE:
+ 135:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           USBD_SetFeature(pdev, req);
+ 136:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 137:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 138:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USB_REQ_CLEAR_FEATURE:
+ 139:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           USBD_ClrFeature(pdev, req);
+ 140:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 141:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 142:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         default:
+ 143:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           USBD_CtlError(pdev, req);
+ 144:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ARM GAS  /tmp/ccQ58aJU.s 			page 4
+
+
+ 145:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 146:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 147:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 148:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     default:
+ 149:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       USBD_CtlError(pdev, req);
+ 150:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 151:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 152:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 153:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   return ret;
+ 154:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 155:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 156:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 157:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_StdItfReq
+ 158:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Handle standard usb interface requests
+ 159:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  pdev: device instance
+ 160:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  req: usb request
+ 161:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval status
+ 162:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 163:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 164:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 166:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 167:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   switch (req->bmRequest & USB_REQ_TYPE_MASK)
+ 168:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 169:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_REQ_TYPE_CLASS:
+ 170:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_REQ_TYPE_VENDOR:
+ 171:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_REQ_TYPE_STANDARD:
+ 172:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       switch (pdev->dev_state)
+ 173:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 174:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USBD_STATE_DEFAULT:
+ 175:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USBD_STATE_ADDRESSED:
+ 176:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USBD_STATE_CONFIGURED:
+ 177:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 178:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
+ 179:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+ 181:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             if ((req->wLength == 0U) && (ret == USBD_OK))
+ 183:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             {
+ 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               (void)USBD_CtlSendStatus(pdev);
+ 185:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             }
+ 186:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 187:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           else
+ 188:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 189:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             USBD_CtlError(pdev, req);
+ 190:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 191:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 192:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 193:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         default:
+ 194:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           USBD_CtlError(pdev, req);
+ 195:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 196:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 197:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 198:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 199:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     default:
+ 200:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       USBD_CtlError(pdev, req);
+ 201:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ARM GAS  /tmp/ccQ58aJU.s 			page 5
+
+
+ 202:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 203:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 204:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   return ret;
+ 205:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 206:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 207:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 208:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_StdEPReq
+ 209:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Handle standard usb endpoint requests
+ 210:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  pdev: device instance
+ 211:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  req: usb request
+ 212:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval status
+ 213:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 214:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 215:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 216:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_EndpointTypeDef *pep;
+ 217:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t ep_addr;
+ 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 219:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   ep_addr = LOBYTE(req->wIndex);
+ 220:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 221:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   switch (req->bmRequest & USB_REQ_TYPE_MASK)
+ 222:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 223:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_REQ_TYPE_CLASS:
+ 224:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_REQ_TYPE_VENDOR:
+ 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+ 226:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 227:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 228:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_REQ_TYPE_STANDARD:
+ 229:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       switch (req->bRequest)
+ 230:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 231:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USB_REQ_SET_FEATURE:
+ 232:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           switch (pdev->dev_state)
+ 233:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 234:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             case USBD_STATE_ADDRESSED:
+ 235:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+ 236:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 237:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 (void)USBD_LL_StallEP(pdev, ep_addr);
+ 238:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 (void)USBD_LL_StallEP(pdev, 0x80U);
+ 239:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 240:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               else
+ 241:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 242:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 USBD_CtlError(pdev, req);
+ 243:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 244:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 245:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 246:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             case USBD_STATE_CONFIGURED:
+ 247:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               if (req->wValue == USB_FEATURE_EP_HALT)
+ 248:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U))
+ 250:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 251:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                   (void)USBD_LL_StallEP(pdev, ep_addr);
+ 252:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 253:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 254:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               (void)USBD_CtlSendStatus(pdev);
+ 255:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 256:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 257:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 258:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             default:
+ARM GAS  /tmp/ccQ58aJU.s 			page 6
+
+
+ 259:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               USBD_CtlError(pdev, req);
+ 260:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 261:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 262:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 263:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 264:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USB_REQ_CLEAR_FEATURE:
+ 265:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 266:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           switch (pdev->dev_state)
+ 267:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 268:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             case USBD_STATE_ADDRESSED:
+ 269:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+ 270:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 271:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 (void)USBD_LL_StallEP(pdev, ep_addr);
+ 272:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 (void)USBD_LL_StallEP(pdev, 0x80U);
+ 273:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 274:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               else
+ 275:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 276:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 USBD_CtlError(pdev, req);
+ 277:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 278:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 279:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 280:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             case USBD_STATE_CONFIGURED:
+ 281:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               if (req->wValue == USB_FEATURE_EP_HALT)
+ 282:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 283:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 if ((ep_addr & 0x7FU) != 0x00U)
+ 284:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 285:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                   (void)USBD_LL_ClearStallEP(pdev, ep_addr);
+ 286:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 287:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 (void)USBD_CtlSendStatus(pdev);
+ 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+ 289:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 290:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 291:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 292:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             default:
+ 293:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               USBD_CtlError(pdev, req);
+ 294:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 295:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 296:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 297:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 298:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USB_REQ_GET_STATUS:
+ 299:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           switch (pdev->dev_state)
+ 300:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 301:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             case USBD_STATE_ADDRESSED:
+ 302:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+ 303:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 304:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 USBD_CtlError(pdev, req);
+ 305:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 break;
+ 306:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
+ 308:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                     &pdev->ep_out[ep_addr & 0x7FU];
+ 309:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 310:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               pep->status = 0x0000U;
+ 311:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 312:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
+ 313:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 314:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 315:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             case USBD_STATE_CONFIGURED:
+ARM GAS  /tmp/ccQ58aJU.s 			page 7
+
+
+ 316:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               if ((ep_addr & 0x80U) == 0x80U)
+ 317:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
+ 319:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 320:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                   USBD_CtlError(pdev, req);
+ 321:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                   break;
+ 322:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 323:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 324:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               else
+ 325:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 326:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
+ 327:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 328:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                   USBD_CtlError(pdev, req);
+ 329:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                   break;
+ 330:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 331:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 332:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
+ 334:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                     &pdev->ep_out[ep_addr & 0x7FU];
+ 335:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 336:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
+ 337:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 338:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 pep->status = 0x0000U;
+ 339:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U)
+ 341:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 342:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 pep->status = 0x0001U;
+ 343:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 344:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               else
+ 345:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 346:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 pep->status = 0x0000U;
+ 347:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 348:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 349:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
+ 350:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 351:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 352:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             default:
+ 353:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               USBD_CtlError(pdev, req);
+ 354:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 355:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 356:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 357:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 358:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         default:
+ 359:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           USBD_CtlError(pdev, req);
+ 360:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 361:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 362:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 363:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 364:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     default:
+ 365:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       USBD_CtlError(pdev, req);
+ 366:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 367:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 368:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 369:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   return ret;
+ 370:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 371:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 372:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ARM GAS  /tmp/ccQ58aJU.s 			page 8
+
+
+ 373:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 374:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_GetDescriptor
+ 375:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Handle Get Descriptor requests
+ 376:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  pdev: device instance
+ 377:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  req: usb request
+ 378:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval status
+ 379:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 380:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 382:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint16_t len = 0U;
+ 383:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t *pbuf = NULL;
+ 384:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t err = 0U;
+ 385:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 386:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   switch (req->wValue >> 8)
+ 387:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 388:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U))
+ 389:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_DESC_TYPE_BOS:
+ 390:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       if (pdev->pDesc->GetBOSDescriptor != NULL)
+ 391:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 392:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
+ 393:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 394:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       else
+ 395:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 396:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         USBD_CtlError(pdev, req);
+ 397:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         err++;
+ 398:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 399:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 400:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #endif
+ 401:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_DESC_TYPE_DEVICE:
+ 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
+ 403:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 404:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 405:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_DESC_TYPE_CONFIGURATION:
+ 406:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       if (pdev->dev_speed == USBD_SPEED_HIGH)
+ 407:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf = pdev->pClass->GetHSConfigDescriptor(&len);
+ 409:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+ 410:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 411:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       else
+ 412:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
+ 414:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+ 415:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 416:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 417:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 418:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_DESC_TYPE_STRING:
+ 419:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       switch ((uint8_t)(req->wValue))
+ 420:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 421:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USBD_IDX_LANGID_STR:
+ 422:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
+ 423:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 424:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
+ 425:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 426:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           else
+ 427:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 428:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             USBD_CtlError(pdev, req);
+ 429:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ARM GAS  /tmp/ccQ58aJU.s 			page 9
+
+
+ 430:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 431:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 432:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 433:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USBD_IDX_MFC_STR:
+ 434:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
+ 435:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 436:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
+ 437:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 438:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           else
+ 439:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 440:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             USBD_CtlError(pdev, req);
+ 441:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 442:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 443:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 444:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 445:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USBD_IDX_PRODUCT_STR:
+ 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           if (pdev->pDesc->GetProductStrDescriptor != NULL)
+ 447:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 448:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
+ 449:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 450:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           else
+ 451:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 452:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             USBD_CtlError(pdev, req);
+ 453:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 454:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 455:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 456:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 457:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USBD_IDX_SERIAL_STR:
+ 458:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           if (pdev->pDesc->GetSerialStrDescriptor != NULL)
+ 459:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 460:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
+ 461:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 462:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           else
+ 463:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 464:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             USBD_CtlError(pdev, req);
+ 465:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 466:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 467:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 468:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 469:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USBD_IDX_CONFIG_STR:
+ 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
+ 471:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 472:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
+ 473:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 474:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           else
+ 475:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 476:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             USBD_CtlError(pdev, req);
+ 477:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 478:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 479:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 480:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 481:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         case USBD_IDX_INTERFACE_STR:
+ 482:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
+ 483:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 484:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
+ 485:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 486:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           else
+ARM GAS  /tmp/ccQ58aJU.s 			page 10
+
+
+ 487:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 488:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             USBD_CtlError(pdev, req);
+ 489:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 490:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 491:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 492:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 493:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         default:
+ 494:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #if (USBD_SUPPORT_USER_STRING_DESC == 1U)
+ 495:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           if (pdev->pClass->GetUsrStrDescriptor != NULL)
+ 496:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 497:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue), &len);
+ 498:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 499:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           else
+ 500:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 501:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             USBD_CtlError(pdev, req);
+ 502:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 503:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 504:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #endif
+ 505:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 506:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #if (USBD_CLASS_USER_STRING_DESC == 1U)
+ 507:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           if (pdev->pDesc->GetUserStrDescriptor != NULL)
+ 508:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 509:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             pbuf = pdev->pDesc->GetUserStrDescriptor(pdev->dev_speed, (req->wValue), &len);
+ 510:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 511:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           else
+ 512:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 513:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             USBD_CtlError(pdev, req);
+ 514:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 515:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 516:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #endif
+ 517:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 518:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U))
+ 519:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           USBD_CtlError(pdev, req);
+ 520:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           err++;
+ 521:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #endif
+ 522:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 523:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 524:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 525:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 526:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_DESC_TYPE_DEVICE_QUALIFIER:
+ 527:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       if (pdev->dev_speed == USBD_SPEED_HIGH)
+ 528:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 529:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len);
+ 530:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 531:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       else
+ 532:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 533:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         USBD_CtlError(pdev, req);
+ 534:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         err++;
+ 535:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 536:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 537:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 538:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
+ 539:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       if (pdev->dev_speed == USBD_SPEED_HIGH)
+ 540:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 541:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
+ 542:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
+ 543:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ARM GAS  /tmp/ccQ58aJU.s 			page 11
+
+
+ 544:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       else
+ 545:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 546:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         USBD_CtlError(pdev, req);
+ 547:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         err++;
+ 548:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 549:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 550:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 551:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     default:
+ 552:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       USBD_CtlError(pdev, req);
+ 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       err++;
+ 554:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 555:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 556:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   if (err != 0U)
+ 558:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 559:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     return;
+ 560:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 561:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 562:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   if (req->wLength != 0U)
+ 563:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     if (len != 0U)
+ 565:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 566:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       len = MIN(len, req->wLength);
+ 567:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_CtlSendData(pdev, pbuf, len);
+ 568:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ 569:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     else
+ 570:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 571:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       USBD_CtlError(pdev, req);
+ 572:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ 573:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 574:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   else
+ 575:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 576:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     (void)USBD_CtlSendStatus(pdev);
+ 577:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 578:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 579:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 580:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 581:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 582:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_SetAddress
+ 583:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Set device address
+ 584:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  pdev: device instance
+ 585:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  req: usb request
+ 586:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval status
+ 587:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 588:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 590:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t  dev_addr;
+ 591:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 592:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
+ 593:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 594:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     dev_addr = (uint8_t)(req->wValue) & 0x7FU;
+ 595:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 596:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     if (pdev->dev_state == USBD_STATE_CONFIGURED)
+ 597:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 598:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       USBD_CtlError(pdev, req);
+ 599:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ 600:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     else
+ARM GAS  /tmp/ccQ58aJU.s 			page 12
+
+
+ 601:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 602:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       pdev->dev_address = dev_addr;
+ 603:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_LL_SetUSBAddress(pdev, dev_addr);
+ 604:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_CtlSendStatus(pdev);
+ 605:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 606:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       if (dev_addr != 0U)
+ 607:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 608:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pdev->dev_state = USBD_STATE_ADDRESSED;
+ 609:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 610:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       else
+ 611:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 612:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pdev->dev_state = USBD_STATE_DEFAULT;
+ 613:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 614:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ 615:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 616:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   else
+ 617:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 618:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     USBD_CtlError(pdev, req);
+ 619:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 620:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 621:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 622:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 623:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_SetConfig
+ 624:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Handle Set device configuration request
+ 625:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  pdev: device instance
+ 626:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  req: usb request
+ 627:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval status
+ 628:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 629:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 630:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 631:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 632:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   static uint8_t cfgidx;
+ 633:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 634:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   cfgidx = (uint8_t)(req->wValue);
+ 635:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 636:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
+ 637:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 638:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     USBD_CtlError(pdev, req);
+ 639:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     return USBD_FAIL;
+ 640:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 641:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 642:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   switch (pdev->dev_state)
+ 643:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 644:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USBD_STATE_ADDRESSED:
+ 645:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       if (cfgidx != 0U)
+ 646:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 647:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pdev->dev_config = cfgidx;
+ 648:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 649:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         ret = USBD_SetClassConfig(pdev, cfgidx);
+ 650:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 651:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         if (ret != USBD_OK)
+ 652:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         {
+ 653:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           USBD_CtlError(pdev, req);
+ 654:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 655:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         else
+ 656:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         {
+ 657:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           (void)USBD_CtlSendStatus(pdev);
+ARM GAS  /tmp/ccQ58aJU.s 			page 13
+
+
+ 658:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           pdev->dev_state = USBD_STATE_CONFIGURED;
+ 659:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 660:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 661:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       else
+ 662:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 663:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendStatus(pdev);
+ 664:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 665:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 666:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 667:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USBD_STATE_CONFIGURED:
+ 668:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       if (cfgidx == 0U)
+ 669:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 670:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pdev->dev_state = USBD_STATE_ADDRESSED;
+ 671:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pdev->dev_config = cfgidx;
+ 672:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_ClrClassConfig(pdev, cfgidx);
+ 673:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendStatus(pdev);
+ 674:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 675:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       else if (cfgidx != pdev->dev_config)
+ 676:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 677:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         /* Clear old configuration */
+ 678:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
+ 679:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 680:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         /* set new configuration */
+ 681:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pdev->dev_config = cfgidx;
+ 682:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 683:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         ret = USBD_SetClassConfig(pdev, cfgidx);
+ 684:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 685:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         if (ret != USBD_OK)
+ 686:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         {
+ 687:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           USBD_CtlError(pdev, req);
+ 688:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
+ 689:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           pdev->dev_state = USBD_STATE_ADDRESSED;
+ 690:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 691:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         else
+ 692:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         {
+ 693:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           (void)USBD_CtlSendStatus(pdev);
+ 694:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 695:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 696:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       else
+ 697:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 698:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendStatus(pdev);
+ 699:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 700:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 701:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 702:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     default:
+ 703:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       USBD_CtlError(pdev, req);
+ 704:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_ClrClassConfig(pdev, cfgidx);
+ 705:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       ret = USBD_FAIL;
+ 706:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 707:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 708:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 709:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   return ret;
+ 710:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 711:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 712:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 713:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_GetConfig
+ 714:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Handle Get device configuration request
+ARM GAS  /tmp/ccQ58aJU.s 			page 14
+
+
+ 715:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  pdev: device instance
+ 716:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  req: usb request
+ 717:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval status
+ 718:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 719:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 720:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 721:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   if (req->wLength != 1U)
+ 722:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 723:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     USBD_CtlError(pdev, req);
+ 724:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 725:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   else
+ 726:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 727:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     switch (pdev->dev_state)
+ 728:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 729:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       case USBD_STATE_DEFAULT:
+ 730:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       case USBD_STATE_ADDRESSED:
+ 731:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pdev->dev_default_config = 0U;
+ 732:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
+ 733:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         break;
+ 734:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 735:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       case USBD_STATE_CONFIGURED:
+ 736:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U);
+ 737:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         break;
+ 738:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 739:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       default:
+ 740:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         USBD_CtlError(pdev, req);
+ 741:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         break;
+ 742:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ 743:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 744:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 745:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 746:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 747:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_GetStatus
+ 748:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Handle Get Status request
+ 749:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  pdev: device instance
+ 750:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  req: usb request
+ 751:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval status
+ 752:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 753:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 754:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 755:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   switch (pdev->dev_state)
+ 756:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 757:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USBD_STATE_DEFAULT:
+ 758:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USBD_STATE_ADDRESSED:
+ 759:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USBD_STATE_CONFIGURED:
+ 760:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       if (req->wLength != 0x2U)
+ 761:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 762:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         USBD_CtlError(pdev, req);
+ 763:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         break;
+ 764:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 765:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 766:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #if (USBD_SELF_POWERED == 1U)
+ 767:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
+ 768:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #else
+ 769:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       pdev->dev_config_status = 0U;
+ 770:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #endif
+ 771:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ARM GAS  /tmp/ccQ58aJU.s 			page 15
+
+
+ 772:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       if (pdev->dev_remote_wakeup != 0U)
+ 773:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 774:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
+ 775:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 776:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 777:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U);
+ 778:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 779:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 780:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     default:
+ 781:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       USBD_CtlError(pdev, req);
+ 782:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 783:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 784:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 785:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 786:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 787:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 788:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_SetFeature
+ 789:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Handle Set device feature request
+ 790:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  pdev: device instance
+ 791:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  req: usb request
+ 792:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval status
+ 793:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 794:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 795:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 796:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
+ 797:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 798:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     pdev->dev_remote_wakeup = 1U;
+ 799:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     (void)USBD_CtlSendStatus(pdev);
+ 800:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 801:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 802:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 803:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 804:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 805:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_ClrFeature
+ 806:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Handle clear device feature request
+ 807:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  pdev: device instance
+ 808:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  req: usb request
+ 809:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval status
+ 810:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 811:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 812:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 813:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   switch (pdev->dev_state)
+ 814:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 815:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USBD_STATE_DEFAULT:
+ 816:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USBD_STATE_ADDRESSED:
+ 817:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     case USBD_STATE_CONFIGURED:
+ 818:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
+ 819:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 820:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pdev->dev_remote_wakeup = 0U;
+ 821:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendStatus(pdev);
+ 822:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 823:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 824:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 825:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     default:
+ 826:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       USBD_CtlError(pdev, req);
+ 827:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 828:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ARM GAS  /tmp/ccQ58aJU.s 			page 16
+
+
+ 829:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 830:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 831:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 832:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 833:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_ParseSetupRequest
+ 834:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Copy buffer into setup structure
+ 835:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  pdev: device instance
+ 836:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  req: usb request
+ 837:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval None
+ 838:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 839:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
+ 840:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 841:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t *pbuff = pdata;
+ 842:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 843:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   req->bmRequest = *(uint8_t *)(pbuff);
+ 844:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 845:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   pbuff++;
+ 846:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   req->bRequest = *(uint8_t *)(pbuff);
+ 847:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 848:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   pbuff++;
+ 849:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   req->wValue = SWAPBYTE(pbuff);
+ 850:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 851:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   pbuff++;
+ 852:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   pbuff++;
+ 853:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   req->wIndex = SWAPBYTE(pbuff);
+ 854:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 855:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   pbuff++;
+ 856:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   pbuff++;
+ 857:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   req->wLength = SWAPBYTE(pbuff);
+ 858:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 859:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 860:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 861:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 862:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_CtlError
+ 863:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Handle USB low level Error
+ 864:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  pdev: device instance
+ 865:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  req: usb request
+ 866:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval None
+ 867:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 868:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+ 869:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 870:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   UNUSED(req);
+ 871:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 872:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   (void)USBD_LL_StallEP(pdev, 0x80U);
+ 873:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   (void)USBD_LL_StallEP(pdev, 0U);
+ 874:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 875:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 876:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 877:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 878:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_GetString
+ 879:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         Convert Ascii string into unicode one
+ 880:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  desc : descriptor buffer
+ 881:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  unicode : Formatted string buffer (unicode)
+ 882:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @param  len : descriptor length
+ 883:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval None
+ 884:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 885:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
+ARM GAS  /tmp/ccQ58aJU.s 			page 17
+
+
+ 886:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+ 887:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t idx = 0U;
+ 888:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t *pdesc;
+ 889:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 890:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   if (desc == NULL)
+ 891:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 892:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     return;
+ 893:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 894:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 895:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   pdesc = desc;
+ 896:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *len = ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U;
+ 897:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 898:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   unicode[idx] = *(uint8_t *)len;
+ 899:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   idx++;
+ 900:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   unicode[idx] = USB_DESC_TYPE_STRING;
+ 901:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   idx++;
+ 902:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 903:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   while (*pdesc != (uint8_t)'\0')
+ 904:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 905:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     unicode[idx] = *pdesc;
+ 906:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     pdesc++;
+ 907:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     idx++;
+ 908:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 909:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     unicode[idx] = 0U;
+ 910:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     idx++;
+ 911:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 912:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 913:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 914:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 915:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /**
+ 916:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @brief  USBD_GetLen
+ 917:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *         return the string length
+ 918:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****    * @param  buf : pointer to the ascii string buffer
+ 919:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   * @retval string length
+ 920:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   */
+ 921:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static uint8_t USBD_GetLen(uint8_t *buf)
+ 922:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** {
+  29              		.loc 1 922 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+  34              		.loc 1 922 1 is_stmt 0 view .LVU1
+  35 0000 0346     		mov	r3, r0
+ 923:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t  len = 0U;
+  36              		.loc 1 923 3 is_stmt 1 view .LVU2
+  37              	.LVL1:
+ 924:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t *pbuff = buf;
+  38              		.loc 1 924 3 view .LVU3
+ 925:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 926:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   while (*pbuff != (uint8_t)'\0')
+  39              		.loc 1 926 3 view .LVU4
+ 923:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t *pbuff = buf;
+  40              		.loc 1 923 12 is_stmt 0 view .LVU5
+  41 0002 0020     		movs	r0, #0
+  42              	.LVL2:
+  43              		.loc 1 926 9 view .LVU6
+ARM GAS  /tmp/ccQ58aJU.s 			page 18
+
+
+  44 0004 02E0     		b	.L2
+  45              	.LVL3:
+  46              	.L3:
+ 927:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 928:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     len++;
+  47              		.loc 1 928 5 is_stmt 1 view .LVU7
+  48              		.loc 1 928 8 is_stmt 0 view .LVU8
+  49 0006 0130     		adds	r0, r0, #1
+  50              	.LVL4:
+  51              		.loc 1 928 8 view .LVU9
+  52 0008 C0B2     		uxtb	r0, r0
+  53              	.LVL5:
+ 929:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     pbuff++;
+  54              		.loc 1 929 5 is_stmt 1 view .LVU10
+  55              		.loc 1 929 10 is_stmt 0 view .LVU11
+  56 000a 0133     		adds	r3, r3, #1
+  57              	.LVL6:
+  58              	.L2:
+ 926:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+  59              		.loc 1 926 17 is_stmt 1 view .LVU12
+ 926:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+  60              		.loc 1 926 10 is_stmt 0 view .LVU13
+  61 000c 1A78     		ldrb	r2, [r3]	@ zero_extendqisi2
+ 926:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+  62              		.loc 1 926 17 view .LVU14
+  63 000e 002A     		cmp	r2, #0
+  64 0010 F9D1     		bne	.L3
+ 930:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 931:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 932:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   return len;
+  65              		.loc 1 932 3 is_stmt 1 view .LVU15
+ 933:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+  66              		.loc 1 933 1 is_stmt 0 view .LVU16
+  67 0012 7047     		bx	lr
+  68              		.cfi_endproc
+  69              	.LFE346:
+  71              		.section	.text.USBD_SetFeature,"ax",%progbits
+  72              		.align	1
+  73              		.syntax unified
+  74              		.thumb
+  75              		.thumb_func
+  77              	USBD_SetFeature:
+  78              	.LVL7:
+  79              	.LFB341:
+ 795:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
+  80              		.loc 1 795 1 is_stmt 1 view -0
+  81              		.cfi_startproc
+  82              		@ args = 0, pretend = 0, frame = 0
+  83              		@ frame_needed = 0, uses_anonymous_args = 0
+ 795:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
+  84              		.loc 1 795 1 is_stmt 0 view .LVU18
+  85 0000 08B5     		push	{r3, lr}
+  86              	.LCFI0:
+  87              		.cfi_def_cfa_offset 8
+  88              		.cfi_offset 3, -8
+  89              		.cfi_offset 14, -4
+ 796:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ARM GAS  /tmp/ccQ58aJU.s 			page 19
+
+
+  90              		.loc 1 796 3 is_stmt 1 view .LVU19
+ 796:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+  91              		.loc 1 796 10 is_stmt 0 view .LVU20
+  92 0002 4B88     		ldrh	r3, [r1, #2]
+ 796:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+  93              		.loc 1 796 6 view .LVU21
+  94 0004 012B     		cmp	r3, #1
+  95 0006 00D0     		beq	.L7
+  96              	.LVL8:
+  97              	.L4:
+ 801:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+  98              		.loc 1 801 1 view .LVU22
+  99 0008 08BD     		pop	{r3, pc}
+ 100              	.LVL9:
+ 101              	.L7:
+ 798:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     (void)USBD_CtlSendStatus(pdev);
+ 102              		.loc 1 798 5 is_stmt 1 view .LVU23
+ 798:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     (void)USBD_CtlSendStatus(pdev);
+ 103              		.loc 1 798 29 is_stmt 0 view .LVU24
+ 104 000a C0F8A432 		str	r3, [r0, #676]
+ 799:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 105              		.loc 1 799 5 is_stmt 1 view .LVU25
+ 799:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 106              		.loc 1 799 11 is_stmt 0 view .LVU26
+ 107 000e FFF7FEFF 		bl	USBD_CtlSendStatus
+ 108              	.LVL10:
+ 801:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 109              		.loc 1 801 1 view .LVU27
+ 110 0012 F9E7     		b	.L4
+ 111              		.cfi_endproc
+ 112              	.LFE341:
+ 114              		.section	.text.USBD_ParseSetupRequest,"ax",%progbits
+ 115              		.align	1
+ 116              		.global	USBD_ParseSetupRequest
+ 117              		.syntax unified
+ 118              		.thumb
+ 119              		.thumb_func
+ 121              	USBD_ParseSetupRequest:
+ 122              	.LVL11:
+ 123              	.LFB343:
+ 840:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t *pbuff = pdata;
+ 124              		.loc 1 840 1 is_stmt 1 view -0
+ 125              		.cfi_startproc
+ 126              		@ args = 0, pretend = 0, frame = 0
+ 127              		@ frame_needed = 0, uses_anonymous_args = 0
+ 128              		@ link register save eliminated.
+ 841:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 129              		.loc 1 841 3 view .LVU29
+ 843:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 130              		.loc 1 843 3 view .LVU30
+ 843:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 131              		.loc 1 843 20 is_stmt 0 view .LVU31
+ 132 0000 0B78     		ldrb	r3, [r1]	@ zero_extendqisi2
+ 843:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 133              		.loc 1 843 18 view .LVU32
+ 134 0002 0370     		strb	r3, [r0]
+ 845:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   req->bRequest = *(uint8_t *)(pbuff);
+ARM GAS  /tmp/ccQ58aJU.s 			page 20
+
+
+ 135              		.loc 1 845 3 is_stmt 1 view .LVU33
+ 136              	.LVL12:
+ 846:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 137              		.loc 1 846 3 view .LVU34
+ 846:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 138              		.loc 1 846 19 is_stmt 0 view .LVU35
+ 139 0004 4B78     		ldrb	r3, [r1, #1]	@ zero_extendqisi2
+ 846:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 140              		.loc 1 846 17 view .LVU36
+ 141 0006 4370     		strb	r3, [r0, #1]
+ 848:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   req->wValue = SWAPBYTE(pbuff);
+ 142              		.loc 1 848 3 is_stmt 1 view .LVU37
+ 143              	.LVL13:
+ 849:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 144              		.loc 1 849 3 view .LVU38
+ 145              	.LBB8:
+ 146              	.LBI8:
+ 147              		.file 2 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h"
+   1:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /**
+   2:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   ******************************************************************************
+   3:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * @file    usbd_def.h
+   4:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * @author  MCD Application Team
+   5:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * @brief   General defines for the usb device library
+   6:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   ******************************************************************************
+   7:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * @attention
+   8:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   *
+   9:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  10:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * All rights reserved.</center></h2>
+  11:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   *
+  12:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * This software component is licensed by ST under Ultimate Liberty license
+  13:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * SLA0044, the "License"; You may not use this file except in compliance with
+  14:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * the License. You may obtain a copy of the License at:
+  15:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   *                      www.st.com/SLA0044
+  16:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   *
+  17:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   ******************************************************************************
+  18:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   */
+  19:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  20:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  21:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef __USBD_DEF_H
+  22:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define __USBD_DEF_H
+  23:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  24:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifdef __cplusplus
+  25:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** extern "C" {
+  26:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif
+  27:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  28:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* Includes ------------------------------------------------------------------*/
+  29:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #include "usbd_conf.h"
+  30:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  31:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** @addtogroup STM32_USBD_DEVICE_LIBRARY
+  32:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * @{
+  33:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   */
+  34:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  35:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** @defgroup USB_DEF
+  36:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * @brief general defines for the usb device library file
+  37:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * @{
+  38:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   */
+  39:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ARM GAS  /tmp/ccQ58aJU.s 			page 21
+
+
+  40:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** @defgroup USB_DEF_Exported_Defines
+  41:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * @{
+  42:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   */
+  43:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  44:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef NULL
+  45:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define NULL                                            0U
+  46:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* NULL */
+  47:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  48:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_MAX_NUM_INTERFACES
+  49:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_MAX_NUM_INTERFACES                         1U
+  50:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* USBD_MAX_NUM_CONFIGURATION */
+  51:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  52:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_MAX_NUM_CONFIGURATION
+  53:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_MAX_NUM_CONFIGURATION                      1U
+  54:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* USBD_MAX_NUM_CONFIGURATION */
+  55:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  56:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_LPM_ENABLED
+  57:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_LPM_ENABLED                                0U
+  58:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* USBD_LPM_ENABLED */
+  59:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  60:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_SELF_POWERED
+  61:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_SELF_POWERED                               1U
+  62:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /*USBD_SELF_POWERED */
+  63:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  64:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_MAX_POWER
+  65:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_MAX_POWER                                  0x32U /* 100 mA */
+  66:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* USBD_MAX_POWER */
+  67:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  68:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_SUPPORT_USER_STRING_DESC
+  69:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_SUPPORT_USER_STRING_DESC                   0U
+  70:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* USBD_SUPPORT_USER_STRING_DESC */
+  71:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  72:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_CLASS_USER_STRING_DESC
+  73:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_CLASS_USER_STRING_DESC                     0U
+  74:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* USBD_CLASS_USER_STRING_DESC */
+  75:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  76:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_LEN_DEV_QUALIFIER_DESC                     0x0AU
+  77:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_LEN_DEV_DESC                               0x12U
+  78:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_LEN_CFG_DESC                               0x09U
+  79:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_LEN_IF_DESC                                0x09U
+  80:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_LEN_EP_DESC                                0x07U
+  81:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_LEN_OTG_DESC                               0x03U
+  82:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_LEN_LANGID_STR_DESC                        0x04U
+  83:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_LEN_OTHER_SPEED_DESC_SIZ                   0x09U
+  84:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  85:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USBD_IDX_LANGID_STR                            0x00U
+  86:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USBD_IDX_MFC_STR                               0x01U
+  87:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USBD_IDX_PRODUCT_STR                           0x02U
+  88:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USBD_IDX_SERIAL_STR                            0x03U
+  89:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USBD_IDX_CONFIG_STR                            0x04U
+  90:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USBD_IDX_INTERFACE_STR                         0x05U
+  91:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+  92:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_TYPE_STANDARD                          0x00U
+  93:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_TYPE_CLASS                             0x20U
+  94:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_TYPE_VENDOR                            0x40U
+  95:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_TYPE_MASK                              0x60U
+  96:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ARM GAS  /tmp/ccQ58aJU.s 			page 22
+
+
+  97:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_RECIPIENT_DEVICE                       0x00U
+  98:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_RECIPIENT_INTERFACE                    0x01U
+  99:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_RECIPIENT_ENDPOINT                     0x02U
+ 100:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_RECIPIENT_MASK                         0x03U
+ 101:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 102:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_GET_STATUS                             0x00U
+ 103:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_CLEAR_FEATURE                          0x01U
+ 104:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_SET_FEATURE                            0x03U
+ 105:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_SET_ADDRESS                            0x05U
+ 106:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_GET_DESCRIPTOR                         0x06U
+ 107:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_SET_DESCRIPTOR                         0x07U
+ 108:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_GET_CONFIGURATION                      0x08U
+ 109:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_SET_CONFIGURATION                      0x09U
+ 110:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_GET_INTERFACE                          0x0AU
+ 111:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_SET_INTERFACE                          0x0BU
+ 112:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_REQ_SYNCH_FRAME                            0x0CU
+ 113:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 114:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_DESC_TYPE_DEVICE                           0x01U
+ 115:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_DESC_TYPE_CONFIGURATION                    0x02U
+ 116:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_DESC_TYPE_STRING                           0x03U
+ 117:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_DESC_TYPE_INTERFACE                        0x04U
+ 118:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_DESC_TYPE_ENDPOINT                         0x05U
+ 119:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_DESC_TYPE_DEVICE_QUALIFIER                 0x06U
+ 120:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION        0x07U
+ 121:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_DESC_TYPE_IAD                              0x0BU
+ 122:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define  USB_DESC_TYPE_BOS                              0x0FU
+ 123:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 124:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_CONFIG_REMOTE_WAKEUP                        0x02U
+ 125:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_CONFIG_SELF_POWERED                         0x01U
+ 126:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 127:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_FEATURE_EP_HALT                             0x00U
+ 128:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_FEATURE_REMOTE_WAKEUP                       0x01U
+ 129:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_FEATURE_TEST_MODE                           0x02U
+ 130:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 131:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_DEVICE_CAPABITY_TYPE                        0x10U
+ 132:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 133:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_CONF_DESC_SIZE                              0x09U
+ 134:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_IF_DESC_SIZE                                0x09U
+ 135:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_EP_DESC_SIZE                                0x07U
+ 136:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_IAD_DESC_SIZE                               0x08U
+ 137:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 138:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_HS_MAX_PACKET_SIZE                          512U
+ 139:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_FS_MAX_PACKET_SIZE                          64U
+ 140:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_MAX_EP0_SIZE                                64U
+ 141:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 142:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /*  Device Status */
+ 143:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_STATE_DEFAULT                              0x01U
+ 144:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_STATE_ADDRESSED                            0x02U
+ 145:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_STATE_CONFIGURED                           0x03U
+ 146:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_STATE_SUSPENDED                            0x04U
+ 147:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 148:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 149:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /*  EP0 State */
+ 150:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_IDLE                                   0x00U
+ 151:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_SETUP                                  0x01U
+ 152:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_DATA_IN                                0x02U
+ 153:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_DATA_OUT                               0x03U
+ARM GAS  /tmp/ccQ58aJU.s 			page 23
+
+
+ 154:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_STATUS_IN                              0x04U
+ 155:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_STATUS_OUT                             0x05U
+ 156:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_STALL                                  0x06U
+ 157:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 158:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP_TYPE_CTRL                               0x00U
+ 159:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP_TYPE_ISOC                               0x01U
+ 160:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP_TYPE_BULK                               0x02U
+ 161:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP_TYPE_INTR                               0x03U
+ 162:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 163:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /**
+ 164:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * @}
+ 165:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   */
+ 166:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 167:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 168:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** @defgroup USBD_DEF_Exported_TypesDefinitions
+ 169:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * @{
+ 170:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   */
+ 171:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 172:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef  struct  usb_setup_req
+ 173:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 174:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bmRequest;
+ 175:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bRequest;
+ 176:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint16_t  wValue;
+ 177:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint16_t  wIndex;
+ 178:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint16_t  wLength;
+ 179:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_SetupReqTypedef;
+ 180:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 181:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct
+ 182:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 183:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bLength;
+ 184:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bDescriptorType;
+ 185:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint16_t  wTotalLength;
+ 186:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bNumInterfaces;
+ 187:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bConfigurationValue;
+ 188:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   iConfiguration;
+ 189:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bmAttributes;
+ 190:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bMaxPower;
+ 191:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_ConfigDescTypedef;
+ 192:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 193:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct
+ 194:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 195:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bLength;
+ 196:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bDescriptorType;
+ 197:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint16_t  wTotalLength;
+ 198:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bNumDeviceCaps;
+ 199:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_BosDescTypedef;
+ 200:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 201:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct
+ 202:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 203:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bLength;
+ 204:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bDescriptorType;
+ 205:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bEndpointAddress;
+ 206:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bmAttributes;
+ 207:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint16_t  wMaxPacketSize;
+ 208:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t   bInterval;
+ 209:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_EpDescTypedef;
+ 210:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ARM GAS  /tmp/ccQ58aJU.s 			page 24
+
+
+ 211:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** struct _USBD_HandleTypeDef;
+ 212:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 213:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct _Device_cb
+ 214:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 215:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t (*Init)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+ 216:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t (*DeInit)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+ 217:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   /* Control Endpoints*/
+ 218:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t (*Setup)(struct _USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef  *req);
+ 219:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t (*EP0_TxSent)(struct _USBD_HandleTypeDef *pdev);
+ 220:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t (*EP0_RxReady)(struct _USBD_HandleTypeDef *pdev);
+ 221:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   /* Class Specific Endpoints*/
+ 222:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t (*DataIn)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+ 223:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t (*DataOut)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+ 224:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t (*SOF)(struct _USBD_HandleTypeDef *pdev);
+ 225:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t (*IsoINIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+ 226:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t (*IsoOUTIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+ 227:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 228:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t  *(*GetHSConfigDescriptor)(uint16_t *length);
+ 229:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t  *(*GetFSConfigDescriptor)(uint16_t *length);
+ 230:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t  *(*GetOtherSpeedConfigDescriptor)(uint16_t *length);
+ 231:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t  *(*GetDeviceQualifierDescriptor)(uint16_t *length);
+ 232:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #if (USBD_SUPPORT_USER_STRING_DESC == 1U)
+ 233:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t  *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint8_t index,  uint16_t *leng
+ 234:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif
+ 235:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 236:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_ClassTypeDef;
+ 237:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 238:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* Following USB Device Speed */
+ 239:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef enum
+ 240:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 241:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_SPEED_HIGH  = 0U,
+ 242:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_SPEED_FULL  = 1U,
+ 243:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_SPEED_LOW   = 2U,
+ 244:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_SpeedTypeDef;
+ 245:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 246:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* Following USB Device status */
+ 247:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef enum
+ 248:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 249:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_OK = 0U,
+ 250:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_BUSY,
+ 251:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_EMEM,
+ 252:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_FAIL,
+ 253:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_StatusTypeDef;
+ 254:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 255:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* USB Device descriptors structure */
+ 256:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct
+ 257:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 258:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+ 259:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+ 260:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+ 261:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+ 262:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+ 263:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+ 264:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+ 265:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #if (USBD_CLASS_USER_STRING_DESC == 1)
+ 266:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t *(*GetUserStrDescriptor)(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length);
+ 267:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif
+ARM GAS  /tmp/ccQ58aJU.s 			page 25
+
+
+ 268:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1))
+ 269:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+ 270:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif
+ 271:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_DescriptorsTypeDef;
+ 272:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 273:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* USB Device handle structure */
+ 274:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct
+ 275:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 276:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint32_t status;
+ 277:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint32_t total_length;
+ 278:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint32_t rem_length;
+ 279:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint32_t maxpacket;
+ 280:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint16_t is_used;
+ 281:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint16_t bInterval;
+ 282:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_EndpointTypeDef;
+ 283:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 284:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* USB Device handle structure */
+ 285:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct _USBD_HandleTypeDef
+ 286:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 287:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t                 id;
+ 288:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint32_t                dev_config;
+ 289:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint32_t                dev_default_config;
+ 290:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint32_t                dev_config_status;
+ 291:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_SpeedTypeDef       dev_speed;
+ 292:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_EndpointTypeDef    ep_in[16];
+ 293:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_EndpointTypeDef    ep_out[16];
+ 294:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   __IO uint32_t           ep0_state;
+ 295:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint32_t                ep0_data_len;
+ 296:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   __IO uint8_t            dev_state;
+ 297:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   __IO uint8_t            dev_old_state;
+ 298:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t                 dev_address;
+ 299:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t                 dev_connection_status;
+ 300:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t                 dev_test_mode;
+ 301:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint32_t                dev_remote_wakeup;
+ 302:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t                 ConfIdx;
+ 303:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 304:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_SetupReqTypedef    request;
+ 305:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_DescriptorsTypeDef *pDesc;
+ 306:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   USBD_ClassTypeDef       *pClass;
+ 307:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   void                    *pClassData;
+ 308:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   void                    *pUserData;
+ 309:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   void                    *pData;
+ 310:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   void                    *pBosDesc;
+ 311:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   void                    *pConfDesc;
+ 312:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_HandleTypeDef;
+ 313:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 314:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /**
+ 315:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * @}
+ 316:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   */
+ 317:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 318:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 319:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 320:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** @defgroup USBD_DEF_Exported_Macros
+ 321:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   * @{
+ 322:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   */
+ 323:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
+ 148              		.loc 2 323 26 view .LVU39
+ARM GAS  /tmp/ccQ58aJU.s 			page 26
+
+
+ 149              	.LBB9:
+ 324:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 325:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint16_t _SwapVal, _Byte1, _Byte2;
+ 150              		.loc 2 325 3 view .LVU40
+ 326:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t *_pbuff = addr;
+ 151              		.loc 2 326 3 view .LVU41
+ 327:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 328:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   _Byte1 = *(uint8_t *)_pbuff;
+ 152              		.loc 2 328 3 view .LVU42
+ 153              		.loc 2 328 12 is_stmt 0 view .LVU43
+ 154 0008 8B78     		ldrb	r3, [r1, #2]	@ zero_extendqisi2
+ 155              	.LVL14:
+ 329:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   _pbuff++;
+ 156              		.loc 2 329 3 is_stmt 1 view .LVU44
+ 330:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   _Byte2 = *(uint8_t *)_pbuff;
+ 157              		.loc 2 330 3 view .LVU45
+ 158              		.loc 2 330 12 is_stmt 0 view .LVU46
+ 159 000a CA78     		ldrb	r2, [r1, #3]	@ zero_extendqisi2
+ 160              	.LVL15:
+ 331:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 332:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   _SwapVal = (_Byte2 << 8) | _Byte1;
+ 161              		.loc 2 332 3 is_stmt 1 view .LVU47
+ 162              		.loc 2 332 12 is_stmt 0 view .LVU48
+ 163 000c 43EA0223 		orr	r3, r3, r2, lsl #8
+ 164              	.LVL16:
+ 333:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 334:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   return _SwapVal;
+ 165              		.loc 2 334 3 is_stmt 1 view .LVU49
+ 166              		.loc 2 334 3 is_stmt 0 view .LVU50
+ 167              	.LBE9:
+ 168              	.LBE8:
+ 849:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 169              		.loc 1 849 15 view .LVU51
+ 170 0010 4380     		strh	r3, [r0, #2]	@ movhi
+ 171              	.LVL17:
+ 851:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   pbuff++;
+ 172              		.loc 1 851 3 is_stmt 1 view .LVU52
+ 852:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   req->wIndex = SWAPBYTE(pbuff);
+ 173              		.loc 1 852 3 view .LVU53
+ 853:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 174              		.loc 1 853 3 view .LVU54
+ 175              	.LBB10:
+ 176              	.LBI10:
+ 323:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 177              		.loc 2 323 26 view .LVU55
+ 178              	.LBB11:
+ 325:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t *_pbuff = addr;
+ 179              		.loc 2 325 3 view .LVU56
+ 326:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 180              		.loc 2 326 3 view .LVU57
+ 328:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   _pbuff++;
+ 181              		.loc 2 328 3 view .LVU58
+ 328:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   _pbuff++;
+ 182              		.loc 2 328 12 is_stmt 0 view .LVU59
+ 183 0012 0B79     		ldrb	r3, [r1, #4]	@ zero_extendqisi2
+ 184              	.LVL18:
+ 329:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   _Byte2 = *(uint8_t *)_pbuff;
+ARM GAS  /tmp/ccQ58aJU.s 			page 27
+
+
+ 185              		.loc 2 329 3 is_stmt 1 view .LVU60
+ 330:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 186              		.loc 2 330 3 view .LVU61
+ 330:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 187              		.loc 2 330 12 is_stmt 0 view .LVU62
+ 188 0014 4A79     		ldrb	r2, [r1, #5]	@ zero_extendqisi2
+ 189              	.LVL19:
+ 332:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 190              		.loc 2 332 3 is_stmt 1 view .LVU63
+ 332:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 191              		.loc 2 332 12 is_stmt 0 view .LVU64
+ 192 0016 43EA0223 		orr	r3, r3, r2, lsl #8
+ 193              	.LVL20:
+ 194              		.loc 2 334 3 is_stmt 1 view .LVU65
+ 195              		.loc 2 334 3 is_stmt 0 view .LVU66
+ 196              	.LBE11:
+ 197              	.LBE10:
+ 853:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 198              		.loc 1 853 15 view .LVU67
+ 199 001a 8380     		strh	r3, [r0, #4]	@ movhi
+ 200              	.LVL21:
+ 855:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   pbuff++;
+ 201              		.loc 1 855 3 is_stmt 1 view .LVU68
+ 856:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   req->wLength = SWAPBYTE(pbuff);
+ 202              		.loc 1 856 3 view .LVU69
+ 857:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 203              		.loc 1 857 3 view .LVU70
+ 204              	.LBB12:
+ 205              	.LBI12:
+ 323:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** {
+ 206              		.loc 2 323 26 view .LVU71
+ 207              	.LBB13:
+ 325:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   uint8_t *_pbuff = addr;
+ 208              		.loc 2 325 3 view .LVU72
+ 326:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 209              		.loc 2 326 3 view .LVU73
+ 328:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   _pbuff++;
+ 210              		.loc 2 328 3 view .LVU74
+ 328:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   _pbuff++;
+ 211              		.loc 2 328 12 is_stmt 0 view .LVU75
+ 212 001c 8B79     		ldrb	r3, [r1, #6]	@ zero_extendqisi2
+ 213              	.LVL22:
+ 329:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h ****   _Byte2 = *(uint8_t *)_pbuff;
+ 214              		.loc 2 329 3 is_stmt 1 view .LVU76
+ 330:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 215              		.loc 2 330 3 view .LVU77
+ 330:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 216              		.loc 2 330 12 is_stmt 0 view .LVU78
+ 217 001e CA79     		ldrb	r2, [r1, #7]	@ zero_extendqisi2
+ 218              	.LVL23:
+ 332:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 219              		.loc 2 332 3 is_stmt 1 view .LVU79
+ 332:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** 
+ 220              		.loc 2 332 12 is_stmt 0 view .LVU80
+ 221 0020 43EA0223 		orr	r3, r3, r2, lsl #8
+ 222              	.LVL24:
+ 223              		.loc 2 334 3 is_stmt 1 view .LVU81
+ARM GAS  /tmp/ccQ58aJU.s 			page 28
+
+
+ 224              		.loc 2 334 3 is_stmt 0 view .LVU82
+ 225              	.LBE13:
+ 226              	.LBE12:
+ 857:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 227              		.loc 1 857 16 view .LVU83
+ 228 0024 C380     		strh	r3, [r0, #6]	@ movhi
+ 229              	.LVL25:
+ 858:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 230              		.loc 1 858 1 view .LVU84
+ 231 0026 7047     		bx	lr
+ 232              		.cfi_endproc
+ 233              	.LFE343:
+ 235              		.section	.text.USBD_CtlError,"ax",%progbits
+ 236              		.align	1
+ 237              		.global	USBD_CtlError
+ 238              		.syntax unified
+ 239              		.thumb
+ 240              		.thumb_func
+ 242              	USBD_CtlError:
+ 243              	.LVL26:
+ 244              	.LFB344:
+ 869:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   UNUSED(req);
+ 245              		.loc 1 869 1 is_stmt 1 view -0
+ 246              		.cfi_startproc
+ 247              		@ args = 0, pretend = 0, frame = 0
+ 248              		@ frame_needed = 0, uses_anonymous_args = 0
+ 869:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   UNUSED(req);
+ 249              		.loc 1 869 1 is_stmt 0 view .LVU86
+ 250 0000 10B5     		push	{r4, lr}
+ 251              	.LCFI1:
+ 252              		.cfi_def_cfa_offset 8
+ 253              		.cfi_offset 4, -8
+ 254              		.cfi_offset 14, -4
+ 255 0002 0446     		mov	r4, r0
+ 870:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 256              		.loc 1 870 3 is_stmt 1 view .LVU87
+ 872:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   (void)USBD_LL_StallEP(pdev, 0U);
+ 257              		.loc 1 872 3 view .LVU88
+ 872:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   (void)USBD_LL_StallEP(pdev, 0U);
+ 258              		.loc 1 872 9 is_stmt 0 view .LVU89
+ 259 0004 8021     		movs	r1, #128
+ 260              	.LVL27:
+ 872:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   (void)USBD_LL_StallEP(pdev, 0U);
+ 261              		.loc 1 872 9 view .LVU90
+ 262 0006 FFF7FEFF 		bl	USBD_LL_StallEP
+ 263              	.LVL28:
+ 873:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 264              		.loc 1 873 3 is_stmt 1 view .LVU91
+ 873:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 265              		.loc 1 873 9 is_stmt 0 view .LVU92
+ 266 000a 0021     		movs	r1, #0
+ 267 000c 2046     		mov	r0, r4
+ 268 000e FFF7FEFF 		bl	USBD_LL_StallEP
+ 269              	.LVL29:
+ 874:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 270              		.loc 1 874 1 view .LVU93
+ 271 0012 10BD     		pop	{r4, pc}
+ARM GAS  /tmp/ccQ58aJU.s 			page 29
+
+
+ 874:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 272              		.loc 1 874 1 view .LVU94
+ 273              		.cfi_endproc
+ 274              	.LFE344:
+ 276              		.section	.text.USBD_GetDescriptor,"ax",%progbits
+ 277              		.align	1
+ 278              		.syntax unified
+ 279              		.thumb
+ 280              		.thumb_func
+ 282              	USBD_GetDescriptor:
+ 283              	.LVL30:
+ 284              	.LFB336:
+ 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint16_t len = 0U;
+ 285              		.loc 1 381 1 is_stmt 1 view -0
+ 286              		.cfi_startproc
+ 287              		@ args = 0, pretend = 0, frame = 8
+ 288              		@ frame_needed = 0, uses_anonymous_args = 0
+ 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint16_t len = 0U;
+ 289              		.loc 1 381 1 is_stmt 0 view .LVU96
+ 290 0000 30B5     		push	{r4, r5, lr}
+ 291              	.LCFI2:
+ 292              		.cfi_def_cfa_offset 12
+ 293              		.cfi_offset 4, -12
+ 294              		.cfi_offset 5, -8
+ 295              		.cfi_offset 14, -4
+ 296 0002 83B0     		sub	sp, sp, #12
+ 297              	.LCFI3:
+ 298              		.cfi_def_cfa_offset 24
+ 299 0004 0446     		mov	r4, r0
+ 300 0006 0D46     		mov	r5, r1
+ 382:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t *pbuf = NULL;
+ 301              		.loc 1 382 3 is_stmt 1 view .LVU97
+ 382:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t *pbuf = NULL;
+ 302              		.loc 1 382 12 is_stmt 0 view .LVU98
+ 303 0008 0023     		movs	r3, #0
+ 304 000a ADF80630 		strh	r3, [sp, #6]	@ movhi
+ 383:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t err = 0U;
+ 305              		.loc 1 383 3 is_stmt 1 view .LVU99
+ 306              	.LVL31:
+ 384:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 307              		.loc 1 384 3 view .LVU100
+ 386:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 308              		.loc 1 386 3 view .LVU101
+ 386:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 309              		.loc 1 386 14 is_stmt 0 view .LVU102
+ 310 000e 4A88     		ldrh	r2, [r1, #2]
+ 386:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 311              		.loc 1 386 23 view .LVU103
+ 312 0010 130A     		lsrs	r3, r2, #8
+ 386:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 313              		.loc 1 386 3 view .LVU104
+ 314 0012 013B     		subs	r3, r3, #1
+ 315 0014 0E2B     		cmp	r3, #14
+ 316 0016 00F2BC80 		bhi	.L12
+ 317 001a DFE803F0 		tbb	[pc, r3]
+ 318              	.LVL32:
+ 319              	.L14:
+ARM GAS  /tmp/ccQ58aJU.s 			page 30
+
+
+ 320 001e 15       		.byte	(.L19-.L14)/2
+ 321 001f 30       		.byte	(.L18-.L14)/2
+ 322 0020 44       		.byte	(.L17-.L14)/2
+ 323 0021 BA       		.byte	(.L12-.L14)/2
+ 324 0022 BA       		.byte	(.L12-.L14)/2
+ 325 0023 9E       		.byte	(.L16-.L14)/2
+ 326 0024 AB       		.byte	(.L15-.L14)/2
+ 327 0025 BA       		.byte	(.L12-.L14)/2
+ 328 0026 BA       		.byte	(.L12-.L14)/2
+ 329 0027 BA       		.byte	(.L12-.L14)/2
+ 330 0028 BA       		.byte	(.L12-.L14)/2
+ 331 0029 BA       		.byte	(.L12-.L14)/2
+ 332 002a BA       		.byte	(.L12-.L14)/2
+ 333 002b BA       		.byte	(.L12-.L14)/2
+ 334 002c 08       		.byte	(.L13-.L14)/2
+ 335 002d 00       		.p2align 1
+ 336              	.L13:
+ 390:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 337              		.loc 1 390 7 is_stmt 1 view .LVU105
+ 390:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 338              		.loc 1 390 15 is_stmt 0 view .LVU106
+ 339 002e D0F8B432 		ldr	r3, [r0, #692]
+ 390:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 340              		.loc 1 390 22 view .LVU107
+ 341 0032 DB69     		ldr	r3, [r3, #28]
+ 390:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 342              		.loc 1 390 10 view .LVU108
+ 343 0034 23B1     		cbz	r3, .L20
+ 392:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 344              		.loc 1 392 9 is_stmt 1 view .LVU109
+ 392:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 345              		.loc 1 392 16 is_stmt 0 view .LVU110
+ 346 0036 0DF10601 		add	r1, sp, #6
+ 347 003a 007C     		ldrb	r0, [r0, #16]	@ zero_extendqisi2
+ 348              	.LVL33:
+ 392:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 349              		.loc 1 392 16 view .LVU111
+ 350 003c 9847     		blx	r3
+ 351              	.LVL34:
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 352              		.loc 1 557 3 is_stmt 1 view .LVU112
+ 353 003e 0AE0     		b	.L21
+ 354              	.LVL35:
+ 355              	.L20:
+ 396:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         err++;
+ 356              		.loc 1 396 9 view .LVU113
+ 357 0040 2946     		mov	r1, r5
+ 358 0042 FFF7FEFF 		bl	USBD_CtlError
+ 359              	.LVL36:
+ 397:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 360              		.loc 1 397 9 view .LVU114
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 361              		.loc 1 557 3 view .LVU115
+ 362 0046 18E0     		b	.L11
+ 363              	.LVL37:
+ 364              	.L19:
+ 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ARM GAS  /tmp/ccQ58aJU.s 			page 31
+
+
+ 365              		.loc 1 402 7 view .LVU116
+ 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 366              		.loc 1 402 18 is_stmt 0 view .LVU117
+ 367 0048 D0F8B432 		ldr	r3, [r0, #692]
+ 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 368              		.loc 1 402 25 view .LVU118
+ 369 004c 1B68     		ldr	r3, [r3]
+ 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 370              		.loc 1 402 14 view .LVU119
+ 371 004e 0DF10601 		add	r1, sp, #6
+ 372 0052 007C     		ldrb	r0, [r0, #16]	@ zero_extendqisi2
+ 373              	.LVL38:
+ 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 374              		.loc 1 402 14 view .LVU120
+ 375 0054 9847     		blx	r3
+ 376              	.LVL39:
+ 403:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 377              		.loc 1 403 7 is_stmt 1 view .LVU121
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 378              		.loc 1 557 3 view .LVU122
+ 379              	.L21:
+ 562:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 380              		.loc 1 562 3 view .LVU123
+ 562:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 381              		.loc 1 562 10 is_stmt 0 view .LVU124
+ 382 0056 EA88     		ldrh	r2, [r5, #6]
+ 562:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 383              		.loc 1 562 6 view .LVU125
+ 384 0058 002A     		cmp	r2, #0
+ 385 005a 00F0A380 		beq	.L41
+ 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 386              		.loc 1 564 5 is_stmt 1 view .LVU126
+ 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 387              		.loc 1 564 13 is_stmt 0 view .LVU127
+ 388 005e BDF80630 		ldrh	r3, [sp, #6]
+ 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 389              		.loc 1 564 8 view .LVU128
+ 390 0062 002B     		cmp	r3, #0
+ 391 0064 00F09980 		beq	.L42
+ 566:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_CtlSendData(pdev, pbuf, len);
+ 392              		.loc 1 566 7 is_stmt 1 view .LVU129
+ 566:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_CtlSendData(pdev, pbuf, len);
+ 393              		.loc 1 566 13 is_stmt 0 view .LVU130
+ 394 0068 9A42     		cmp	r2, r3
+ 395 006a 28BF     		it	cs
+ 396 006c 1A46     		movcs	r2, r3
+ 566:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_CtlSendData(pdev, pbuf, len);
+ 397              		.loc 1 566 11 view .LVU131
+ 398 006e ADF80620 		strh	r2, [sp, #6]	@ movhi
+ 567:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ 399              		.loc 1 567 7 is_stmt 1 view .LVU132
+ 567:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ 400              		.loc 1 567 13 is_stmt 0 view .LVU133
+ 401 0072 0146     		mov	r1, r0
+ 402 0074 2046     		mov	r0, r4
+ 403              	.LVL40:
+ 567:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ARM GAS  /tmp/ccQ58aJU.s 			page 32
+
+
+ 404              		.loc 1 567 13 view .LVU134
+ 405 0076 FFF7FEFF 		bl	USBD_CtlSendData
+ 406              	.LVL41:
+ 407              	.L11:
+ 578:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 408              		.loc 1 578 1 view .LVU135
+ 409 007a 03B0     		add	sp, sp, #12
+ 410              	.LCFI4:
+ 411              		.cfi_remember_state
+ 412              		.cfi_def_cfa_offset 12
+ 413              		@ sp needed
+ 414 007c 30BD     		pop	{r4, r5, pc}
+ 415              	.LVL42:
+ 416              	.L18:
+ 417              	.LCFI5:
+ 418              		.cfi_restore_state
+ 406:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 419              		.loc 1 406 7 is_stmt 1 view .LVU136
+ 406:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 420              		.loc 1 406 15 is_stmt 0 view .LVU137
+ 421 007e 037C     		ldrb	r3, [r0, #16]	@ zero_extendqisi2
+ 406:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 422              		.loc 1 406 10 view .LVU138
+ 423 0080 43B9     		cbnz	r3, .L23
+ 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+ 424              		.loc 1 408 9 is_stmt 1 view .LVU139
+ 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+ 425              		.loc 1 408 20 is_stmt 0 view .LVU140
+ 426 0082 D0F8B832 		ldr	r3, [r0, #696]
+ 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+ 427              		.loc 1 408 28 view .LVU141
+ 428 0086 9B6A     		ldr	r3, [r3, #40]
+ 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+ 429              		.loc 1 408 16 view .LVU142
+ 430 0088 0DF10600 		add	r0, sp, #6
+ 431              	.LVL43:
+ 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+ 432              		.loc 1 408 16 view .LVU143
+ 433 008c 9847     		blx	r3
+ 434              	.LVL44:
+ 409:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 435              		.loc 1 409 9 is_stmt 1 view .LVU144
+ 409:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 436              		.loc 1 409 17 is_stmt 0 view .LVU145
+ 437 008e 0223     		movs	r3, #2
+ 438 0090 4370     		strb	r3, [r0, #1]
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 439              		.loc 1 557 3 is_stmt 1 view .LVU146
+ 440 0092 E0E7     		b	.L21
+ 441              	.LVL45:
+ 442              	.L23:
+ 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+ 443              		.loc 1 413 9 view .LVU147
+ 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+ 444              		.loc 1 413 20 is_stmt 0 view .LVU148
+ 445 0094 D0F8B832 		ldr	r3, [r0, #696]
+ 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+ARM GAS  /tmp/ccQ58aJU.s 			page 33
+
+
+ 446              		.loc 1 413 28 view .LVU149
+ 447 0098 DB6A     		ldr	r3, [r3, #44]
+ 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+ 448              		.loc 1 413 16 view .LVU150
+ 449 009a 0DF10600 		add	r0, sp, #6
+ 450              	.LVL46:
+ 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+ 451              		.loc 1 413 16 view .LVU151
+ 452 009e 9847     		blx	r3
+ 453              	.LVL47:
+ 414:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 454              		.loc 1 414 9 is_stmt 1 view .LVU152
+ 414:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 455              		.loc 1 414 17 is_stmt 0 view .LVU153
+ 456 00a0 0223     		movs	r3, #2
+ 457 00a2 4370     		strb	r3, [r0, #1]
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 458              		.loc 1 557 3 is_stmt 1 view .LVU154
+ 459 00a4 D7E7     		b	.L21
+ 460              	.LVL48:
+ 461              	.L17:
+ 419:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 462              		.loc 1 419 7 view .LVU155
+ 419:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 463              		.loc 1 419 15 is_stmt 0 view .LVU156
+ 464 00a6 D2B2     		uxtb	r2, r2
+ 465 00a8 052A     		cmp	r2, #5
+ 466 00aa 52D8     		bhi	.L24
+ 467 00ac DFE802F0 		tbb	[pc, r2]
+ 468              	.L26:
+ 469 00b0 03       		.byte	(.L31-.L26)/2
+ 470 00b1 10       		.byte	(.L30-.L26)/2
+ 471 00b2 1D       		.byte	(.L29-.L26)/2
+ 472 00b3 2A       		.byte	(.L28-.L26)/2
+ 473 00b4 37       		.byte	(.L27-.L26)/2
+ 474 00b5 44       		.byte	(.L25-.L26)/2
+ 475              		.p2align 1
+ 476              	.L31:
+ 422:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 477              		.loc 1 422 11 is_stmt 1 view .LVU157
+ 422:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 478              		.loc 1 422 19 is_stmt 0 view .LVU158
+ 479 00b6 D0F8B432 		ldr	r3, [r0, #692]
+ 422:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 480              		.loc 1 422 26 view .LVU159
+ 481 00ba 5B68     		ldr	r3, [r3, #4]
+ 422:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 482              		.loc 1 422 14 view .LVU160
+ 483 00bc 23B1     		cbz	r3, .L32
+ 424:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 484              		.loc 1 424 13 is_stmt 1 view .LVU161
+ 424:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 485              		.loc 1 424 20 is_stmt 0 view .LVU162
+ 486 00be 0DF10601 		add	r1, sp, #6
+ 487 00c2 007C     		ldrb	r0, [r0, #16]	@ zero_extendqisi2
+ 488              	.LVL49:
+ 424:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ARM GAS  /tmp/ccQ58aJU.s 			page 34
+
+
+ 489              		.loc 1 424 20 view .LVU163
+ 490 00c4 9847     		blx	r3
+ 491              	.LVL50:
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 492              		.loc 1 557 3 is_stmt 1 view .LVU164
+ 493 00c6 C6E7     		b	.L21
+ 494              	.LVL51:
+ 495              	.L32:
+ 428:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 496              		.loc 1 428 13 view .LVU165
+ 497 00c8 2946     		mov	r1, r5
+ 498 00ca FFF7FEFF 		bl	USBD_CtlError
+ 499              	.LVL52:
+ 429:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 500              		.loc 1 429 13 view .LVU166
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 501              		.loc 1 557 3 view .LVU167
+ 502 00ce D4E7     		b	.L11
+ 503              	.LVL53:
+ 504              	.L30:
+ 434:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 505              		.loc 1 434 11 view .LVU168
+ 434:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 506              		.loc 1 434 19 is_stmt 0 view .LVU169
+ 507 00d0 D0F8B432 		ldr	r3, [r0, #692]
+ 434:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 508              		.loc 1 434 26 view .LVU170
+ 509 00d4 9B68     		ldr	r3, [r3, #8]
+ 434:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 510              		.loc 1 434 14 view .LVU171
+ 511 00d6 23B1     		cbz	r3, .L33
+ 436:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 512              		.loc 1 436 13 is_stmt 1 view .LVU172
+ 436:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 513              		.loc 1 436 20 is_stmt 0 view .LVU173
+ 514 00d8 0DF10601 		add	r1, sp, #6
+ 515 00dc 007C     		ldrb	r0, [r0, #16]	@ zero_extendqisi2
+ 516              	.LVL54:
+ 436:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 517              		.loc 1 436 20 view .LVU174
+ 518 00de 9847     		blx	r3
+ 519              	.LVL55:
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 520              		.loc 1 557 3 is_stmt 1 view .LVU175
+ 521 00e0 B9E7     		b	.L21
+ 522              	.LVL56:
+ 523              	.L33:
+ 440:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 524              		.loc 1 440 13 view .LVU176
+ 525 00e2 2946     		mov	r1, r5
+ 526 00e4 FFF7FEFF 		bl	USBD_CtlError
+ 527              	.LVL57:
+ 441:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 528              		.loc 1 441 13 view .LVU177
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 529              		.loc 1 557 3 view .LVU178
+ 530 00e8 C7E7     		b	.L11
+ARM GAS  /tmp/ccQ58aJU.s 			page 35
+
+
+ 531              	.LVL58:
+ 532              	.L29:
+ 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 533              		.loc 1 446 11 view .LVU179
+ 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 534              		.loc 1 446 19 is_stmt 0 view .LVU180
+ 535 00ea D0F8B432 		ldr	r3, [r0, #692]
+ 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 536              		.loc 1 446 26 view .LVU181
+ 537 00ee DB68     		ldr	r3, [r3, #12]
+ 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 538              		.loc 1 446 14 view .LVU182
+ 539 00f0 23B1     		cbz	r3, .L34
+ 448:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 540              		.loc 1 448 13 is_stmt 1 view .LVU183
+ 448:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 541              		.loc 1 448 20 is_stmt 0 view .LVU184
+ 542 00f2 0DF10601 		add	r1, sp, #6
+ 543 00f6 007C     		ldrb	r0, [r0, #16]	@ zero_extendqisi2
+ 544              	.LVL59:
+ 448:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 545              		.loc 1 448 20 view .LVU185
+ 546 00f8 9847     		blx	r3
+ 547              	.LVL60:
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 548              		.loc 1 557 3 is_stmt 1 view .LVU186
+ 549 00fa ACE7     		b	.L21
+ 550              	.LVL61:
+ 551              	.L34:
+ 452:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 552              		.loc 1 452 13 view .LVU187
+ 553 00fc 2946     		mov	r1, r5
+ 554 00fe FFF7FEFF 		bl	USBD_CtlError
+ 555              	.LVL62:
+ 453:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 556              		.loc 1 453 13 view .LVU188
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 557              		.loc 1 557 3 view .LVU189
+ 558 0102 BAE7     		b	.L11
+ 559              	.LVL63:
+ 560              	.L28:
+ 458:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 561              		.loc 1 458 11 view .LVU190
+ 458:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 562              		.loc 1 458 19 is_stmt 0 view .LVU191
+ 563 0104 D0F8B432 		ldr	r3, [r0, #692]
+ 458:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 564              		.loc 1 458 26 view .LVU192
+ 565 0108 1B69     		ldr	r3, [r3, #16]
+ 458:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 566              		.loc 1 458 14 view .LVU193
+ 567 010a 23B1     		cbz	r3, .L35
+ 460:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 568              		.loc 1 460 13 is_stmt 1 view .LVU194
+ 460:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 569              		.loc 1 460 20 is_stmt 0 view .LVU195
+ 570 010c 0DF10601 		add	r1, sp, #6
+ARM GAS  /tmp/ccQ58aJU.s 			page 36
+
+
+ 571 0110 007C     		ldrb	r0, [r0, #16]	@ zero_extendqisi2
+ 572              	.LVL64:
+ 460:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 573              		.loc 1 460 20 view .LVU196
+ 574 0112 9847     		blx	r3
+ 575              	.LVL65:
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 576              		.loc 1 557 3 is_stmt 1 view .LVU197
+ 577 0114 9FE7     		b	.L21
+ 578              	.LVL66:
+ 579              	.L35:
+ 464:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 580              		.loc 1 464 13 view .LVU198
+ 581 0116 2946     		mov	r1, r5
+ 582 0118 FFF7FEFF 		bl	USBD_CtlError
+ 583              	.LVL67:
+ 465:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 584              		.loc 1 465 13 view .LVU199
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 585              		.loc 1 557 3 view .LVU200
+ 586 011c ADE7     		b	.L11
+ 587              	.LVL68:
+ 588              	.L27:
+ 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 589              		.loc 1 470 11 view .LVU201
+ 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 590              		.loc 1 470 19 is_stmt 0 view .LVU202
+ 591 011e D0F8B432 		ldr	r3, [r0, #692]
+ 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 592              		.loc 1 470 26 view .LVU203
+ 593 0122 5B69     		ldr	r3, [r3, #20]
+ 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 594              		.loc 1 470 14 view .LVU204
+ 595 0124 23B1     		cbz	r3, .L36
+ 472:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 596              		.loc 1 472 13 is_stmt 1 view .LVU205
+ 472:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 597              		.loc 1 472 20 is_stmt 0 view .LVU206
+ 598 0126 0DF10601 		add	r1, sp, #6
+ 599 012a 007C     		ldrb	r0, [r0, #16]	@ zero_extendqisi2
+ 600              	.LVL69:
+ 472:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 601              		.loc 1 472 20 view .LVU207
+ 602 012c 9847     		blx	r3
+ 603              	.LVL70:
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 604              		.loc 1 557 3 is_stmt 1 view .LVU208
+ 605 012e 92E7     		b	.L21
+ 606              	.LVL71:
+ 607              	.L36:
+ 476:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 608              		.loc 1 476 13 view .LVU209
+ 609 0130 2946     		mov	r1, r5
+ 610 0132 FFF7FEFF 		bl	USBD_CtlError
+ 611              	.LVL72:
+ 477:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 612              		.loc 1 477 13 view .LVU210
+ARM GAS  /tmp/ccQ58aJU.s 			page 37
+
+
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 613              		.loc 1 557 3 view .LVU211
+ 614 0136 A0E7     		b	.L11
+ 615              	.LVL73:
+ 616              	.L25:
+ 482:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 617              		.loc 1 482 11 view .LVU212
+ 482:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 618              		.loc 1 482 19 is_stmt 0 view .LVU213
+ 619 0138 D0F8B432 		ldr	r3, [r0, #692]
+ 482:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 620              		.loc 1 482 26 view .LVU214
+ 621 013c 9B69     		ldr	r3, [r3, #24]
+ 482:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 622              		.loc 1 482 14 view .LVU215
+ 623 013e 23B1     		cbz	r3, .L37
+ 484:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 624              		.loc 1 484 13 is_stmt 1 view .LVU216
+ 484:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 625              		.loc 1 484 20 is_stmt 0 view .LVU217
+ 626 0140 0DF10601 		add	r1, sp, #6
+ 627 0144 007C     		ldrb	r0, [r0, #16]	@ zero_extendqisi2
+ 628              	.LVL74:
+ 484:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 629              		.loc 1 484 20 view .LVU218
+ 630 0146 9847     		blx	r3
+ 631              	.LVL75:
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 632              		.loc 1 557 3 is_stmt 1 view .LVU219
+ 633 0148 85E7     		b	.L21
+ 634              	.LVL76:
+ 635              	.L37:
+ 488:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             err++;
+ 636              		.loc 1 488 13 view .LVU220
+ 637 014a 2946     		mov	r1, r5
+ 638 014c FFF7FEFF 		bl	USBD_CtlError
+ 639              	.LVL77:
+ 489:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 640              		.loc 1 489 13 view .LVU221
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 641              		.loc 1 557 3 view .LVU222
+ 642 0150 93E7     		b	.L11
+ 643              	.LVL78:
+ 644              	.L24:
+ 519:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           err++;
+ 645              		.loc 1 519 11 view .LVU223
+ 646 0152 2946     		mov	r1, r5
+ 647 0154 FFF7FEFF 		bl	USBD_CtlError
+ 648              	.LVL79:
+ 520:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #endif
+ 649              		.loc 1 520 11 view .LVU224
+ 522:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 650              		.loc 1 522 11 view .LVU225
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 651              		.loc 1 557 3 view .LVU226
+ 652 0158 8FE7     		b	.L11
+ 653              	.LVL80:
+ARM GAS  /tmp/ccQ58aJU.s 			page 38
+
+
+ 654              	.L16:
+ 527:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 655              		.loc 1 527 7 view .LVU227
+ 527:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 656              		.loc 1 527 15 is_stmt 0 view .LVU228
+ 657 015a 037C     		ldrb	r3, [r0, #16]	@ zero_extendqisi2
+ 527:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 658              		.loc 1 527 10 view .LVU229
+ 659 015c 33B9     		cbnz	r3, .L38
+ 529:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 660              		.loc 1 529 9 is_stmt 1 view .LVU230
+ 529:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 661              		.loc 1 529 20 is_stmt 0 view .LVU231
+ 662 015e D0F8B832 		ldr	r3, [r0, #696]
+ 529:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 663              		.loc 1 529 28 view .LVU232
+ 664 0162 5B6B     		ldr	r3, [r3, #52]
+ 529:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 665              		.loc 1 529 16 view .LVU233
+ 666 0164 0DF10600 		add	r0, sp, #6
+ 667              	.LVL81:
+ 529:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 668              		.loc 1 529 16 view .LVU234
+ 669 0168 9847     		blx	r3
+ 670              	.LVL82:
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 671              		.loc 1 557 3 is_stmt 1 view .LVU235
+ 672 016a 74E7     		b	.L21
+ 673              	.LVL83:
+ 674              	.L38:
+ 533:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         err++;
+ 675              		.loc 1 533 9 view .LVU236
+ 676 016c 2946     		mov	r1, r5
+ 677 016e FFF7FEFF 		bl	USBD_CtlError
+ 678              	.LVL84:
+ 534:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 679              		.loc 1 534 9 view .LVU237
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 680              		.loc 1 557 3 view .LVU238
+ 681 0172 82E7     		b	.L11
+ 682              	.LVL85:
+ 683              	.L15:
+ 539:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 684              		.loc 1 539 7 view .LVU239
+ 539:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 685              		.loc 1 539 15 is_stmt 0 view .LVU240
+ 686 0174 037C     		ldrb	r3, [r0, #16]	@ zero_extendqisi2
+ 539:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 687              		.loc 1 539 10 view .LVU241
+ 688 0176 43B9     		cbnz	r3, .L39
+ 541:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
+ 689              		.loc 1 541 9 is_stmt 1 view .LVU242
+ 541:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
+ 690              		.loc 1 541 20 is_stmt 0 view .LVU243
+ 691 0178 D0F8B832 		ldr	r3, [r0, #696]
+ 541:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
+ 692              		.loc 1 541 28 view .LVU244
+ARM GAS  /tmp/ccQ58aJU.s 			page 39
+
+
+ 693 017c 1B6B     		ldr	r3, [r3, #48]
+ 541:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
+ 694              		.loc 1 541 16 view .LVU245
+ 695 017e 0DF10600 		add	r0, sp, #6
+ 696              	.LVL86:
+ 541:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
+ 697              		.loc 1 541 16 view .LVU246
+ 698 0182 9847     		blx	r3
+ 699              	.LVL87:
+ 542:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 700              		.loc 1 542 9 is_stmt 1 view .LVU247
+ 542:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 701              		.loc 1 542 17 is_stmt 0 view .LVU248
+ 702 0184 0723     		movs	r3, #7
+ 703 0186 4370     		strb	r3, [r0, #1]
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 704              		.loc 1 557 3 is_stmt 1 view .LVU249
+ 705 0188 65E7     		b	.L21
+ 706              	.LVL88:
+ 707              	.L39:
+ 546:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         err++;
+ 708              		.loc 1 546 9 view .LVU250
+ 709 018a 2946     		mov	r1, r5
+ 710 018c FFF7FEFF 		bl	USBD_CtlError
+ 711              	.LVL89:
+ 547:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 712              		.loc 1 547 9 view .LVU251
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 713              		.loc 1 557 3 view .LVU252
+ 714 0190 73E7     		b	.L11
+ 715              	.LVL90:
+ 716              	.L12:
+ 552:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       err++;
+ 717              		.loc 1 552 7 view .LVU253
+ 718 0192 2946     		mov	r1, r5
+ 719 0194 FFF7FEFF 		bl	USBD_CtlError
+ 720              	.LVL91:
+ 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 721              		.loc 1 553 7 view .LVU254
+ 554:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 722              		.loc 1 554 7 view .LVU255
+ 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 723              		.loc 1 557 3 view .LVU256
+ 559:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 724              		.loc 1 559 5 view .LVU257
+ 725 0198 6FE7     		b	.L11
+ 726              	.LVL92:
+ 727              	.L42:
+ 571:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ 728              		.loc 1 571 7 view .LVU258
+ 729 019a 2946     		mov	r1, r5
+ 730 019c 2046     		mov	r0, r4
+ 731              	.LVL93:
+ 571:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ 732              		.loc 1 571 7 is_stmt 0 view .LVU259
+ 733 019e FFF7FEFF 		bl	USBD_CtlError
+ 734              	.LVL94:
+ARM GAS  /tmp/ccQ58aJU.s 			page 40
+
+
+ 735 01a2 6AE7     		b	.L11
+ 736              	.LVL95:
+ 737              	.L41:
+ 576:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 738              		.loc 1 576 5 is_stmt 1 view .LVU260
+ 576:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 739              		.loc 1 576 11 is_stmt 0 view .LVU261
+ 740 01a4 2046     		mov	r0, r4
+ 741              	.LVL96:
+ 576:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 742              		.loc 1 576 11 view .LVU262
+ 743 01a6 FFF7FEFF 		bl	USBD_CtlSendStatus
+ 744              	.LVL97:
+ 745 01aa 66E7     		b	.L11
+ 746              		.cfi_endproc
+ 747              	.LFE336:
+ 749              		.section	.text.USBD_SetAddress,"ax",%progbits
+ 750              		.align	1
+ 751              		.syntax unified
+ 752              		.thumb
+ 753              		.thumb_func
+ 755              	USBD_SetAddress:
+ 756              	.LVL98:
+ 757              	.LFB337:
+ 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t  dev_addr;
+ 758              		.loc 1 589 1 is_stmt 1 view -0
+ 759              		.cfi_startproc
+ 760              		@ args = 0, pretend = 0, frame = 0
+ 761              		@ frame_needed = 0, uses_anonymous_args = 0
+ 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t  dev_addr;
+ 762              		.loc 1 589 1 is_stmt 0 view .LVU264
+ 763 0000 38B5     		push	{r3, r4, r5, lr}
+ 764              	.LCFI6:
+ 765              		.cfi_def_cfa_offset 16
+ 766              		.cfi_offset 3, -16
+ 767              		.cfi_offset 4, -12
+ 768              		.cfi_offset 5, -8
+ 769              		.cfi_offset 14, -4
+ 770 0002 0446     		mov	r4, r0
+ 590:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 771              		.loc 1 590 3 is_stmt 1 view .LVU265
+ 592:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 772              		.loc 1 592 3 view .LVU266
+ 592:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 773              		.loc 1 592 11 is_stmt 0 view .LVU267
+ 774 0004 8B88     		ldrh	r3, [r1, #4]
+ 592:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 775              		.loc 1 592 6 view .LVU268
+ 776 0006 FBB9     		cbnz	r3, .L46
+ 592:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 777              		.loc 1 592 34 discriminator 1 view .LVU269
+ 778 0008 CB88     		ldrh	r3, [r1, #6]
+ 592:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 779              		.loc 1 592 27 discriminator 1 view .LVU270
+ 780 000a EBB9     		cbnz	r3, .L46
+ 592:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 781              		.loc 1 592 58 discriminator 2 view .LVU271
+ARM GAS  /tmp/ccQ58aJU.s 			page 41
+
+
+ 782 000c 4B88     		ldrh	r3, [r1, #2]
+ 592:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 783              		.loc 1 592 51 discriminator 2 view .LVU272
+ 784 000e 7F2B     		cmp	r3, #127
+ 785 0010 1AD8     		bhi	.L46
+ 594:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 786              		.loc 1 594 5 is_stmt 1 view .LVU273
+ 594:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 787              		.loc 1 594 14 is_stmt 0 view .LVU274
+ 788 0012 03F07F05 		and	r5, r3, #127
+ 789              	.LVL99:
+ 596:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 790              		.loc 1 596 5 is_stmt 1 view .LVU275
+ 596:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 791              		.loc 1 596 13 is_stmt 0 view .LVU276
+ 792 0016 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 793 001a DBB2     		uxtb	r3, r3
+ 596:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 794              		.loc 1 596 8 view .LVU277
+ 795 001c 032B     		cmp	r3, #3
+ 796 001e 0CD0     		beq	.L51
+ 602:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_LL_SetUSBAddress(pdev, dev_addr);
+ 797              		.loc 1 602 7 is_stmt 1 view .LVU278
+ 602:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_LL_SetUSBAddress(pdev, dev_addr);
+ 798              		.loc 1 602 25 is_stmt 0 view .LVU279
+ 799 0020 80F89E52 		strb	r5, [r0, #670]
+ 603:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_CtlSendStatus(pdev);
+ 800              		.loc 1 603 7 is_stmt 1 view .LVU280
+ 603:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_CtlSendStatus(pdev);
+ 801              		.loc 1 603 13 is_stmt 0 view .LVU281
+ 802 0024 2946     		mov	r1, r5
+ 803              	.LVL100:
+ 603:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_CtlSendStatus(pdev);
+ 804              		.loc 1 603 13 view .LVU282
+ 805 0026 FFF7FEFF 		bl	USBD_LL_SetUSBAddress
+ 806              	.LVL101:
+ 604:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 807              		.loc 1 604 7 is_stmt 1 view .LVU283
+ 604:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 808              		.loc 1 604 13 is_stmt 0 view .LVU284
+ 809 002a 2046     		mov	r0, r4
+ 810 002c FFF7FEFF 		bl	USBD_CtlSendStatus
+ 811              	.LVL102:
+ 606:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 812              		.loc 1 606 7 is_stmt 1 view .LVU285
+ 606:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 813              		.loc 1 606 10 is_stmt 0 view .LVU286
+ 814 0030 35B1     		cbz	r5, .L49
+ 608:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 815              		.loc 1 608 9 is_stmt 1 view .LVU287
+ 608:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 816              		.loc 1 608 25 is_stmt 0 view .LVU288
+ 817 0032 0223     		movs	r3, #2
+ 818 0034 84F89C32 		strb	r3, [r4, #668]
+ 819 0038 09E0     		b	.L45
+ 820              	.LVL103:
+ 821              	.L51:
+ARM GAS  /tmp/ccQ58aJU.s 			page 42
+
+
+ 598:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ 822              		.loc 1 598 7 is_stmt 1 view .LVU289
+ 823 003a FFF7FEFF 		bl	USBD_CtlError
+ 824              	.LVL104:
+ 598:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ 825              		.loc 1 598 7 is_stmt 0 view .LVU290
+ 826 003e 06E0     		b	.L45
+ 827              	.L49:
+ 612:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 828              		.loc 1 612 9 is_stmt 1 view .LVU291
+ 612:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 829              		.loc 1 612 25 is_stmt 0 view .LVU292
+ 830 0040 0123     		movs	r3, #1
+ 831 0042 84F89C32 		strb	r3, [r4, #668]
+ 832 0046 02E0     		b	.L45
+ 833              	.LVL105:
+ 834              	.L46:
+ 618:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 835              		.loc 1 618 5 is_stmt 1 view .LVU293
+ 836 0048 2046     		mov	r0, r4
+ 837              	.LVL106:
+ 618:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 838              		.loc 1 618 5 is_stmt 0 view .LVU294
+ 839 004a FFF7FEFF 		bl	USBD_CtlError
+ 840              	.LVL107:
+ 841              	.L45:
+ 620:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 842              		.loc 1 620 1 view .LVU295
+ 843 004e 38BD     		pop	{r3, r4, r5, pc}
+ 620:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 844              		.loc 1 620 1 view .LVU296
+ 845              		.cfi_endproc
+ 846              	.LFE337:
+ 848              		.section	.text.USBD_SetConfig,"ax",%progbits
+ 849              		.align	1
+ 850              		.syntax unified
+ 851              		.thumb
+ 852              		.thumb_func
+ 854              	USBD_SetConfig:
+ 855              	.LVL108:
+ 856              	.LFB338:
+ 630:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 857              		.loc 1 630 1 is_stmt 1 view -0
+ 858              		.cfi_startproc
+ 859              		@ args = 0, pretend = 0, frame = 0
+ 860              		@ frame_needed = 0, uses_anonymous_args = 0
+ 630:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 861              		.loc 1 630 1 is_stmt 0 view .LVU298
+ 862 0000 70B5     		push	{r4, r5, r6, lr}
+ 863              	.LCFI7:
+ 864              		.cfi_def_cfa_offset 16
+ 865              		.cfi_offset 4, -16
+ 866              		.cfi_offset 5, -12
+ 867              		.cfi_offset 6, -8
+ 868              		.cfi_offset 14, -4
+ 869 0002 0446     		mov	r4, r0
+ 870 0004 0E46     		mov	r6, r1
+ARM GAS  /tmp/ccQ58aJU.s 			page 43
+
+
+ 631:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   static uint8_t cfgidx;
+ 871              		.loc 1 631 3 is_stmt 1 view .LVU299
+ 872              	.LVL109:
+ 632:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 873              		.loc 1 632 3 view .LVU300
+ 634:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 874              		.loc 1 634 3 view .LVU301
+ 634:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 875              		.loc 1 634 12 is_stmt 0 view .LVU302
+ 876 0006 8D78     		ldrb	r5, [r1, #2]	@ zero_extendqisi2
+ 634:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 877              		.loc 1 634 10 view .LVU303
+ 878 0008 2E4B     		ldr	r3, .L67
+ 879 000a 1D70     		strb	r5, [r3]
+ 636:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 880              		.loc 1 636 3 is_stmt 1 view .LVU304
+ 636:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 881              		.loc 1 636 6 is_stmt 0 view .LVU305
+ 882 000c 012D     		cmp	r5, #1
+ 883 000e 10D8     		bhi	.L65
+ 642:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 884              		.loc 1 642 3 is_stmt 1 view .LVU306
+ 642:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 885              		.loc 1 642 15 is_stmt 0 view .LVU307
+ 886 0010 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 887 0014 DBB2     		uxtb	r3, r3
+ 642:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 888              		.loc 1 642 3 view .LVU308
+ 889 0016 022B     		cmp	r3, #2
+ 890 0018 0FD0     		beq	.L55
+ 891 001a 032B     		cmp	r3, #3
+ 892 001c 23D0     		beq	.L56
+ 703:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       (void)USBD_ClrClassConfig(pdev, cfgidx);
+ 893              		.loc 1 703 7 is_stmt 1 view .LVU309
+ 894 001e FFF7FEFF 		bl	USBD_CtlError
+ 895              	.LVL110:
+ 704:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       ret = USBD_FAIL;
+ 896              		.loc 1 704 7 view .LVU310
+ 704:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       ret = USBD_FAIL;
+ 897              		.loc 1 704 13 is_stmt 0 view .LVU311
+ 898 0022 284B     		ldr	r3, .L67
+ 899 0024 1978     		ldrb	r1, [r3]	@ zero_extendqisi2
+ 900 0026 2046     		mov	r0, r4
+ 901 0028 FFF7FEFF 		bl	USBD_ClrClassConfig
+ 902              	.LVL111:
+ 705:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 903              		.loc 1 705 7 is_stmt 1 view .LVU312
+ 706:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 904              		.loc 1 706 7 view .LVU313
+ 705:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 905              		.loc 1 705 11 is_stmt 0 view .LVU314
+ 906 002c 0325     		movs	r5, #3
+ 907              	.LVL112:
+ 908              	.L54:
+ 710:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 909              		.loc 1 710 1 view .LVU315
+ 910 002e 2846     		mov	r0, r5
+ARM GAS  /tmp/ccQ58aJU.s 			page 44
+
+
+ 911 0030 70BD     		pop	{r4, r5, r6, pc}
+ 912              	.LVL113:
+ 913              	.L65:
+ 638:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     return USBD_FAIL;
+ 914              		.loc 1 638 5 is_stmt 1 view .LVU316
+ 915 0032 FFF7FEFF 		bl	USBD_CtlError
+ 916              	.LVL114:
+ 639:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 917              		.loc 1 639 5 view .LVU317
+ 639:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 918              		.loc 1 639 12 is_stmt 0 view .LVU318
+ 919 0036 0325     		movs	r5, #3
+ 920 0038 F9E7     		b	.L54
+ 921              	.LVL115:
+ 922              	.L55:
+ 645:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 923              		.loc 1 645 7 is_stmt 1 view .LVU319
+ 645:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 924              		.loc 1 645 10 is_stmt 0 view .LVU320
+ 925 003a 8DB1     		cbz	r5, .L58
+ 647:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 926              		.loc 1 647 9 is_stmt 1 view .LVU321
+ 647:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 927              		.loc 1 647 26 is_stmt 0 view .LVU322
+ 928 003c 4560     		str	r5, [r0, #4]
+ 649:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 929              		.loc 1 649 9 is_stmt 1 view .LVU323
+ 649:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 930              		.loc 1 649 15 is_stmt 0 view .LVU324
+ 931 003e 2946     		mov	r1, r5
+ 932              	.LVL116:
+ 649:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 933              		.loc 1 649 15 view .LVU325
+ 934 0040 FFF7FEFF 		bl	USBD_SetClassConfig
+ 935              	.LVL117:
+ 651:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         {
+ 936              		.loc 1 651 9 is_stmt 1 view .LVU326
+ 651:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         {
+ 937              		.loc 1 651 12 is_stmt 0 view .LVU327
+ 938 0044 0546     		mov	r5, r0
+ 939 0046 20B1     		cbz	r0, .L59
+ 653:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 940              		.loc 1 653 11 is_stmt 1 view .LVU328
+ 941 0048 3146     		mov	r1, r6
+ 942 004a 2046     		mov	r0, r4
+ 943              	.LVL118:
+ 653:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 944              		.loc 1 653 11 is_stmt 0 view .LVU329
+ 945 004c FFF7FEFF 		bl	USBD_CtlError
+ 946              	.LVL119:
+ 947 0050 EDE7     		b	.L54
+ 948              	.LVL120:
+ 949              	.L59:
+ 657:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           pdev->dev_state = USBD_STATE_CONFIGURED;
+ 950              		.loc 1 657 11 is_stmt 1 view .LVU330
+ 657:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           pdev->dev_state = USBD_STATE_CONFIGURED;
+ 951              		.loc 1 657 17 is_stmt 0 view .LVU331
+ARM GAS  /tmp/ccQ58aJU.s 			page 45
+
+
+ 952 0052 2046     		mov	r0, r4
+ 953              	.LVL121:
+ 657:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           pdev->dev_state = USBD_STATE_CONFIGURED;
+ 954              		.loc 1 657 17 view .LVU332
+ 955 0054 FFF7FEFF 		bl	USBD_CtlSendStatus
+ 956              	.LVL122:
+ 658:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 957              		.loc 1 658 11 is_stmt 1 view .LVU333
+ 658:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 958              		.loc 1 658 27 is_stmt 0 view .LVU334
+ 959 0058 0323     		movs	r3, #3
+ 960 005a 84F89C32 		strb	r3, [r4, #668]
+ 961 005e E6E7     		b	.L54
+ 962              	.LVL123:
+ 963              	.L58:
+ 663:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 964              		.loc 1 663 9 is_stmt 1 view .LVU335
+ 663:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 965              		.loc 1 663 15 is_stmt 0 view .LVU336
+ 966 0060 FFF7FEFF 		bl	USBD_CtlSendStatus
+ 967              	.LVL124:
+ 663:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 968              		.loc 1 663 15 view .LVU337
+ 969 0064 E3E7     		b	.L54
+ 970              	.LVL125:
+ 971              	.L56:
+ 668:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 972              		.loc 1 668 7 is_stmt 1 view .LVU338
+ 668:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 973              		.loc 1 668 10 is_stmt 0 view .LVU339
+ 974 0066 CDB1     		cbz	r5, .L66
+ 675:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 975              		.loc 1 675 12 is_stmt 1 view .LVU340
+ 675:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 976              		.loc 1 675 30 is_stmt 0 view .LVU341
+ 977 0068 4168     		ldr	r1, [r0, #4]
+ 978              	.LVL126:
+ 675:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 979              		.loc 1 675 15 view .LVU342
+ 980 006a 8D42     		cmp	r5, r1
+ 981 006c 25D0     		beq	.L61
+ 678:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 982              		.loc 1 678 9 is_stmt 1 view .LVU343
+ 678:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 983              		.loc 1 678 15 is_stmt 0 view .LVU344
+ 984 006e C9B2     		uxtb	r1, r1
+ 985 0070 FFF7FEFF 		bl	USBD_ClrClassConfig
+ 986              	.LVL127:
+ 681:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 987              		.loc 1 681 9 is_stmt 1 view .LVU345
+ 681:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 988              		.loc 1 681 26 is_stmt 0 view .LVU346
+ 989 0074 134B     		ldr	r3, .L67
+ 990 0076 1978     		ldrb	r1, [r3]	@ zero_extendqisi2
+ 991 0078 6160     		str	r1, [r4, #4]
+ 683:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 992              		.loc 1 683 9 is_stmt 1 view .LVU347
+ARM GAS  /tmp/ccQ58aJU.s 			page 46
+
+
+ 683:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 993              		.loc 1 683 15 is_stmt 0 view .LVU348
+ 994 007a 2046     		mov	r0, r4
+ 995 007c FFF7FEFF 		bl	USBD_SetClassConfig
+ 996              	.LVL128:
+ 685:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         {
+ 997              		.loc 1 685 9 is_stmt 1 view .LVU349
+ 685:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         {
+ 998              		.loc 1 685 12 is_stmt 0 view .LVU350
+ 999 0080 0546     		mov	r5, r0
+ 1000 0082 B0B1     		cbz	r0, .L62
+ 687:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
+ 1001              		.loc 1 687 11 is_stmt 1 view .LVU351
+ 1002 0084 3146     		mov	r1, r6
+ 1003 0086 2046     		mov	r0, r4
+ 1004              	.LVL129:
+ 687:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
+ 1005              		.loc 1 687 11 is_stmt 0 view .LVU352
+ 1006 0088 FFF7FEFF 		bl	USBD_CtlError
+ 1007              	.LVL130:
+ 688:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           pdev->dev_state = USBD_STATE_ADDRESSED;
+ 1008              		.loc 1 688 11 is_stmt 1 view .LVU353
+ 688:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           pdev->dev_state = USBD_STATE_ADDRESSED;
+ 1009              		.loc 1 688 17 is_stmt 0 view .LVU354
+ 1010 008c 2179     		ldrb	r1, [r4, #4]	@ zero_extendqisi2
+ 1011 008e 2046     		mov	r0, r4
+ 1012 0090 FFF7FEFF 		bl	USBD_ClrClassConfig
+ 1013              	.LVL131:
+ 689:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 1014              		.loc 1 689 11 is_stmt 1 view .LVU355
+ 689:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 1015              		.loc 1 689 27 is_stmt 0 view .LVU356
+ 1016 0094 0223     		movs	r3, #2
+ 1017 0096 84F89C32 		strb	r3, [r4, #668]
+ 1018 009a C8E7     		b	.L54
+ 1019              	.LVL132:
+ 1020              	.L66:
+ 670:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pdev->dev_config = cfgidx;
+ 1021              		.loc 1 670 9 is_stmt 1 view .LVU357
+ 670:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         pdev->dev_config = cfgidx;
+ 1022              		.loc 1 670 25 is_stmt 0 view .LVU358
+ 1023 009c 0223     		movs	r3, #2
+ 1024 009e 80F89C32 		strb	r3, [r0, #668]
+ 671:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_ClrClassConfig(pdev, cfgidx);
+ 1025              		.loc 1 671 9 is_stmt 1 view .LVU359
+ 671:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_ClrClassConfig(pdev, cfgidx);
+ 1026              		.loc 1 671 26 is_stmt 0 view .LVU360
+ 1027 00a2 4560     		str	r5, [r0, #4]
+ 672:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendStatus(pdev);
+ 1028              		.loc 1 672 9 is_stmt 1 view .LVU361
+ 672:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendStatus(pdev);
+ 1029              		.loc 1 672 15 is_stmt 0 view .LVU362
+ 1030 00a4 2946     		mov	r1, r5
+ 1031              	.LVL133:
+ 672:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendStatus(pdev);
+ 1032              		.loc 1 672 15 view .LVU363
+ 1033 00a6 FFF7FEFF 		bl	USBD_ClrClassConfig
+ARM GAS  /tmp/ccQ58aJU.s 			page 47
+
+
+ 1034              	.LVL134:
+ 673:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1035              		.loc 1 673 9 is_stmt 1 view .LVU364
+ 673:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1036              		.loc 1 673 15 is_stmt 0 view .LVU365
+ 1037 00aa 2046     		mov	r0, r4
+ 1038 00ac FFF7FEFF 		bl	USBD_CtlSendStatus
+ 1039              	.LVL135:
+ 1040 00b0 BDE7     		b	.L54
+ 1041              	.LVL136:
+ 1042              	.L62:
+ 693:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 1043              		.loc 1 693 11 is_stmt 1 view .LVU366
+ 693:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 1044              		.loc 1 693 17 is_stmt 0 view .LVU367
+ 1045 00b2 2046     		mov	r0, r4
+ 1046              	.LVL137:
+ 693:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         }
+ 1047              		.loc 1 693 17 view .LVU368
+ 1048 00b4 FFF7FEFF 		bl	USBD_CtlSendStatus
+ 1049              	.LVL138:
+ 1050 00b8 B9E7     		b	.L54
+ 1051              	.LVL139:
+ 1052              	.L61:
+ 698:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1053              		.loc 1 698 9 is_stmt 1 view .LVU369
+ 698:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1054              		.loc 1 698 15 is_stmt 0 view .LVU370
+ 1055 00ba FFF7FEFF 		bl	USBD_CtlSendStatus
+ 1056              	.LVL140:
+ 631:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   static uint8_t cfgidx;
+ 1057              		.loc 1 631 22 view .LVU371
+ 1058 00be 0025     		movs	r5, #0
+ 1059 00c0 B5E7     		b	.L54
+ 1060              	.L68:
+ 1061 00c2 00BF     		.align	2
+ 1062              	.L67:
+ 1063 00c4 00000000 		.word	cfgidx.0
+ 1064              		.cfi_endproc
+ 1065              	.LFE338:
+ 1067              		.section	.text.USBD_GetConfig,"ax",%progbits
+ 1068              		.align	1
+ 1069              		.syntax unified
+ 1070              		.thumb
+ 1071              		.thumb_func
+ 1073              	USBD_GetConfig:
+ 1074              	.LVL141:
+ 1075              	.LFB339:
+ 720:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   if (req->wLength != 1U)
+ 1076              		.loc 1 720 1 is_stmt 1 view -0
+ 1077              		.cfi_startproc
+ 1078              		@ args = 0, pretend = 0, frame = 0
+ 1079              		@ frame_needed = 0, uses_anonymous_args = 0
+ 720:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   if (req->wLength != 1U)
+ 1080              		.loc 1 720 1 is_stmt 0 view .LVU373
+ 1081 0000 08B5     		push	{r3, lr}
+ 1082              	.LCFI8:
+ARM GAS  /tmp/ccQ58aJU.s 			page 48
+
+
+ 1083              		.cfi_def_cfa_offset 8
+ 1084              		.cfi_offset 3, -8
+ 1085              		.cfi_offset 14, -4
+ 721:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1086              		.loc 1 721 3 is_stmt 1 view .LVU374
+ 721:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1087              		.loc 1 721 10 is_stmt 0 view .LVU375
+ 1088 0002 CB88     		ldrh	r3, [r1, #6]
+ 721:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1089              		.loc 1 721 6 view .LVU376
+ 1090 0004 012B     		cmp	r3, #1
+ 1091 0006 0BD1     		bne	.L77
+ 727:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 1092              		.loc 1 727 5 is_stmt 1 view .LVU377
+ 727:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 1093              		.loc 1 727 17 is_stmt 0 view .LVU378
+ 1094 0008 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 1095 000c DBB2     		uxtb	r3, r3
+ 727:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 1096              		.loc 1 727 5 view .LVU379
+ 1097 000e 022B     		cmp	r3, #2
+ 1098 0010 09D9     		bls	.L78
+ 1099 0012 032B     		cmp	r3, #3
+ 1100 0014 09D1     		bne	.L74
+ 736:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         break;
+ 1101              		.loc 1 736 9 is_stmt 1 view .LVU380
+ 736:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         break;
+ 1102              		.loc 1 736 15 is_stmt 0 view .LVU381
+ 1103 0016 0122     		movs	r2, #1
+ 1104 0018 011D     		adds	r1, r0, #4
+ 1105              	.LVL142:
+ 736:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         break;
+ 1106              		.loc 1 736 15 view .LVU382
+ 1107 001a FFF7FEFF 		bl	USBD_CtlSendData
+ 1108              	.LVL143:
+ 737:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1109              		.loc 1 737 9 is_stmt 1 view .LVU383
+ 1110 001e 01E0     		b	.L69
+ 1111              	.LVL144:
+ 1112              	.L77:
+ 723:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 1113              		.loc 1 723 5 view .LVU384
+ 1114 0020 FFF7FEFF 		bl	USBD_CtlError
+ 1115              	.LVL145:
+ 1116              	.L69:
+ 744:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1117              		.loc 1 744 1 is_stmt 0 view .LVU385
+ 1118 0024 08BD     		pop	{r3, pc}
+ 1119              	.LVL146:
+ 1120              	.L78:
+ 727:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     {
+ 1121              		.loc 1 727 5 view .LVU386
+ 1122 0026 5BB2     		sxtb	r3, r3
+ 1123 0028 13B9     		cbnz	r3, .L79
+ 1124              	.L74:
+ 740:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         break;
+ 1125              		.loc 1 740 9 is_stmt 1 view .LVU387
+ARM GAS  /tmp/ccQ58aJU.s 			page 49
+
+
+ 1126 002a FFF7FEFF 		bl	USBD_CtlError
+ 1127              	.LVL147:
+ 741:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     }
+ 1128              		.loc 1 741 9 view .LVU388
+ 744:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1129              		.loc 1 744 1 is_stmt 0 view .LVU389
+ 1130 002e F9E7     		b	.L69
+ 1131              	.LVL148:
+ 1132              	.L79:
+ 731:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
+ 1133              		.loc 1 731 9 is_stmt 1 view .LVU390
+ 731:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
+ 1134              		.loc 1 731 34 is_stmt 0 view .LVU391
+ 1135 0030 0146     		mov	r1, r0
+ 1136              	.LVL149:
+ 731:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
+ 1137              		.loc 1 731 34 view .LVU392
+ 1138 0032 0023     		movs	r3, #0
+ 1139 0034 41F8083F 		str	r3, [r1, #8]!
+ 732:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         break;
+ 1140              		.loc 1 732 9 is_stmt 1 view .LVU393
+ 732:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         break;
+ 1141              		.loc 1 732 15 is_stmt 0 view .LVU394
+ 1142 0038 0122     		movs	r2, #1
+ 1143 003a FFF7FEFF 		bl	USBD_CtlSendData
+ 1144              	.LVL150:
+ 733:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1145              		.loc 1 733 9 is_stmt 1 view .LVU395
+ 1146 003e F1E7     		b	.L69
+ 1147              		.cfi_endproc
+ 1148              	.LFE339:
+ 1150              		.section	.text.USBD_GetStatus,"ax",%progbits
+ 1151              		.align	1
+ 1152              		.syntax unified
+ 1153              		.thumb
+ 1154              		.thumb_func
+ 1156              	USBD_GetStatus:
+ 1157              	.LVL151:
+ 1158              	.LFB340:
+ 754:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   switch (pdev->dev_state)
+ 1159              		.loc 1 754 1 view -0
+ 1160              		.cfi_startproc
+ 1161              		@ args = 0, pretend = 0, frame = 0
+ 1162              		@ frame_needed = 0, uses_anonymous_args = 0
+ 754:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   switch (pdev->dev_state)
+ 1163              		.loc 1 754 1 is_stmt 0 view .LVU397
+ 1164 0000 08B5     		push	{r3, lr}
+ 1165              	.LCFI9:
+ 1166              		.cfi_def_cfa_offset 8
+ 1167              		.cfi_offset 3, -8
+ 1168              		.cfi_offset 14, -4
+ 755:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1169              		.loc 1 755 3 is_stmt 1 view .LVU398
+ 755:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1170              		.loc 1 755 15 is_stmt 0 view .LVU399
+ 1171 0002 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 755:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ARM GAS  /tmp/ccQ58aJU.s 			page 50
+
+
+ 1172              		.loc 1 755 3 view .LVU400
+ 1173 0006 013B     		subs	r3, r3, #1
+ 1174 0008 022B     		cmp	r3, #2
+ 1175 000a 12D8     		bhi	.L81
+ 760:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1176              		.loc 1 760 7 is_stmt 1 view .LVU401
+ 760:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1177              		.loc 1 760 14 is_stmt 0 view .LVU402
+ 1178 000c CB88     		ldrh	r3, [r1, #6]
+ 760:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1179              		.loc 1 760 10 view .LVU403
+ 1180 000e 022B     		cmp	r3, #2
+ 1181 0010 0CD1     		bne	.L86
+ 767:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #else
+ 1182              		.loc 1 767 7 is_stmt 1 view .LVU404
+ 767:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #else
+ 1183              		.loc 1 767 31 is_stmt 0 view .LVU405
+ 1184 0012 0123     		movs	r3, #1
+ 1185 0014 C360     		str	r3, [r0, #12]
+ 772:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1186              		.loc 1 772 7 is_stmt 1 view .LVU406
+ 772:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1187              		.loc 1 772 15 is_stmt 0 view .LVU407
+ 1188 0016 D0F8A432 		ldr	r3, [r0, #676]
+ 772:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1189              		.loc 1 772 10 view .LVU408
+ 1190 001a 0BB1     		cbz	r3, .L84
+ 774:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1191              		.loc 1 774 9 is_stmt 1 view .LVU409
+ 774:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1192              		.loc 1 774 33 is_stmt 0 view .LVU410
+ 1193 001c 0323     		movs	r3, #3
+ 1194 001e C360     		str	r3, [r0, #12]
+ 1195              	.L84:
+ 777:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1196              		.loc 1 777 7 is_stmt 1 view .LVU411
+ 777:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1197              		.loc 1 777 13 is_stmt 0 view .LVU412
+ 1198 0020 0222     		movs	r2, #2
+ 1199 0022 00F10C01 		add	r1, r0, #12
+ 1200              	.LVL152:
+ 777:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1201              		.loc 1 777 13 view .LVU413
+ 1202 0026 FFF7FEFF 		bl	USBD_CtlSendData
+ 1203              	.LVL153:
+ 778:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1204              		.loc 1 778 7 is_stmt 1 view .LVU414
+ 1205              	.L80:
+ 784:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1206              		.loc 1 784 1 is_stmt 0 view .LVU415
+ 1207 002a 08BD     		pop	{r3, pc}
+ 1208              	.LVL154:
+ 1209              	.L86:
+ 762:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         break;
+ 1210              		.loc 1 762 9 is_stmt 1 view .LVU416
+ 1211 002c FFF7FEFF 		bl	USBD_CtlError
+ 1212              	.LVL155:
+ARM GAS  /tmp/ccQ58aJU.s 			page 51
+
+
+ 763:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1213              		.loc 1 763 9 view .LVU417
+ 1214 0030 FBE7     		b	.L80
+ 1215              	.LVL156:
+ 1216              	.L81:
+ 781:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1217              		.loc 1 781 7 view .LVU418
+ 1218 0032 FFF7FEFF 		bl	USBD_CtlError
+ 1219              	.LVL157:
+ 782:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 1220              		.loc 1 782 7 view .LVU419
+ 784:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1221              		.loc 1 784 1 is_stmt 0 view .LVU420
+ 1222 0036 F8E7     		b	.L80
+ 1223              		.cfi_endproc
+ 1224              	.LFE340:
+ 1226              		.section	.text.USBD_ClrFeature,"ax",%progbits
+ 1227              		.align	1
+ 1228              		.syntax unified
+ 1229              		.thumb
+ 1230              		.thumb_func
+ 1232              	USBD_ClrFeature:
+ 1233              	.LVL158:
+ 1234              	.LFB342:
+ 812:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   switch (pdev->dev_state)
+ 1235              		.loc 1 812 1 is_stmt 1 view -0
+ 1236              		.cfi_startproc
+ 1237              		@ args = 0, pretend = 0, frame = 0
+ 1238              		@ frame_needed = 0, uses_anonymous_args = 0
+ 812:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   switch (pdev->dev_state)
+ 1239              		.loc 1 812 1 is_stmt 0 view .LVU422
+ 1240 0000 08B5     		push	{r3, lr}
+ 1241              	.LCFI10:
+ 1242              		.cfi_def_cfa_offset 8
+ 1243              		.cfi_offset 3, -8
+ 1244              		.cfi_offset 14, -4
+ 813:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1245              		.loc 1 813 3 is_stmt 1 view .LVU423
+ 813:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1246              		.loc 1 813 15 is_stmt 0 view .LVU424
+ 1247 0002 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 813:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1248              		.loc 1 813 3 view .LVU425
+ 1249 0006 013B     		subs	r3, r3, #1
+ 1250 0008 022B     		cmp	r3, #2
+ 1251 000a 09D8     		bhi	.L88
+ 818:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1252              		.loc 1 818 7 is_stmt 1 view .LVU426
+ 818:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1253              		.loc 1 818 14 is_stmt 0 view .LVU427
+ 1254 000c 4B88     		ldrh	r3, [r1, #2]
+ 818:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1255              		.loc 1 818 10 view .LVU428
+ 1256 000e 012B     		cmp	r3, #1
+ 1257 0010 00D0     		beq	.L91
+ 1258              	.LVL159:
+ 1259              	.L87:
+ARM GAS  /tmp/ccQ58aJU.s 			page 52
+
+
+ 829:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1260              		.loc 1 829 1 view .LVU429
+ 1261 0012 08BD     		pop	{r3, pc}
+ 1262              	.LVL160:
+ 1263              	.L91:
+ 820:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendStatus(pdev);
+ 1264              		.loc 1 820 9 is_stmt 1 view .LVU430
+ 820:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****         (void)USBD_CtlSendStatus(pdev);
+ 1265              		.loc 1 820 33 is_stmt 0 view .LVU431
+ 1266 0014 0023     		movs	r3, #0
+ 1267 0016 C0F8A432 		str	r3, [r0, #676]
+ 821:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1268              		.loc 1 821 9 is_stmt 1 view .LVU432
+ 821:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1269              		.loc 1 821 15 is_stmt 0 view .LVU433
+ 1270 001a FFF7FEFF 		bl	USBD_CtlSendStatus
+ 1271              	.LVL161:
+ 821:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1272              		.loc 1 821 15 view .LVU434
+ 1273 001e F8E7     		b	.L87
+ 1274              	.LVL162:
+ 1275              	.L88:
+ 826:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1276              		.loc 1 826 7 is_stmt 1 view .LVU435
+ 1277 0020 FFF7FEFF 		bl	USBD_CtlError
+ 1278              	.LVL163:
+ 827:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 1279              		.loc 1 827 7 view .LVU436
+ 829:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1280              		.loc 1 829 1 is_stmt 0 view .LVU437
+ 1281 0024 F5E7     		b	.L87
+ 1282              		.cfi_endproc
+ 1283              	.LFE342:
+ 1285              		.section	.text.USBD_StdDevReq,"ax",%progbits
+ 1286              		.align	1
+ 1287              		.global	USBD_StdDevReq
+ 1288              		.syntax unified
+ 1289              		.thumb
+ 1290              		.thumb_func
+ 1292              	USBD_StdDevReq:
+ 1293              	.LVL164:
+ 1294              	.LFB333:
+ 101:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 1295              		.loc 1 101 1 is_stmt 1 view -0
+ 1296              		.cfi_startproc
+ 1297              		@ args = 0, pretend = 0, frame = 0
+ 1298              		@ frame_needed = 0, uses_anonymous_args = 0
+ 101:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 1299              		.loc 1 101 1 is_stmt 0 view .LVU439
+ 1300 0000 38B5     		push	{r3, r4, r5, lr}
+ 1301              	.LCFI11:
+ 1302              		.cfi_def_cfa_offset 16
+ 1303              		.cfi_offset 3, -16
+ 1304              		.cfi_offset 4, -12
+ 1305              		.cfi_offset 5, -8
+ 1306              		.cfi_offset 14, -4
+ 102:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ARM GAS  /tmp/ccQ58aJU.s 			page 53
+
+
+ 1307              		.loc 1 102 3 is_stmt 1 view .LVU440
+ 1308              	.LVL165:
+ 104:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1309              		.loc 1 104 3 view .LVU441
+ 104:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1310              		.loc 1 104 14 is_stmt 0 view .LVU442
+ 1311 0002 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 1312 0004 04F06004 		and	r4, r4, #96
+ 104:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1313              		.loc 1 104 3 view .LVU443
+ 1314 0008 202C     		cmp	r4, #32
+ 1315 000a 06D0     		beq	.L93
+ 1316 000c 402C     		cmp	r4, #64
+ 1317 000e 04D0     		beq	.L93
+ 1318 0010 54B1     		cbz	r4, .L108
+ 149:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1319              		.loc 1 149 7 is_stmt 1 view .LVU444
+ 1320 0012 FFF7FEFF 		bl	USBD_CtlError
+ 1321              	.LVL166:
+ 150:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 1322              		.loc 1 150 7 view .LVU445
+ 102:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1323              		.loc 1 102 22 is_stmt 0 view .LVU446
+ 1324 0016 0024     		movs	r4, #0
+ 150:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 1325              		.loc 1 150 7 view .LVU447
+ 1326 0018 04E0     		b	.L96
+ 1327              	.LVL167:
+ 1328              	.L93:
+ 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1329              		.loc 1 108 7 is_stmt 1 view .LVU448
+ 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1330              		.loc 1 108 37 is_stmt 0 view .LVU449
+ 1331 001a D0F8B832 		ldr	r3, [r0, #696]
+ 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1332              		.loc 1 108 45 view .LVU450
+ 1333 001e 9B68     		ldr	r3, [r3, #8]
+ 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1334              		.loc 1 108 33 view .LVU451
+ 1335 0020 9847     		blx	r3
+ 1336              	.LVL168:
+ 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1337              		.loc 1 108 33 view .LVU452
+ 1338 0022 0446     		mov	r4, r0
+ 1339              	.LVL169:
+ 109:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1340              		.loc 1 109 7 is_stmt 1 view .LVU453
+ 1341              	.L96:
+ 153:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 1342              		.loc 1 153 3 view .LVU454
+ 154:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1343              		.loc 1 154 1 is_stmt 0 view .LVU455
+ 1344 0024 2046     		mov	r0, r4
+ 1345 0026 38BD     		pop	{r3, r4, r5, pc}
+ 1346              	.LVL170:
+ 1347              	.L108:
+ 112:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ARM GAS  /tmp/ccQ58aJU.s 			page 54
+
+
+ 1348              		.loc 1 112 7 is_stmt 1 view .LVU456
+ 112:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1349              		.loc 1 112 18 is_stmt 0 view .LVU457
+ 1350 0028 4D78     		ldrb	r5, [r1, #1]	@ zero_extendqisi2
+ 1351 002a 092D     		cmp	r5, #9
+ 1352 002c 1DD8     		bhi	.L97
+ 1353 002e DFE805F0 		tbb	[pc, r5]
+ 1354              	.L99:
+ 1355 0032 12       		.byte	(.L105-.L99)/2
+ 1356 0033 19       		.byte	(.L104-.L99)/2
+ 1357 0034 1C       		.byte	(.L97-.L99)/2
+ 1358 0035 16       		.byte	(.L103-.L99)/2
+ 1359 0036 1C       		.byte	(.L97-.L99)/2
+ 1360 0037 08       		.byte	(.L102-.L99)/2
+ 1361 0038 05       		.byte	(.L101-.L99)/2
+ 1362 0039 1C       		.byte	(.L97-.L99)/2
+ 1363 003a 0F       		.byte	(.L100-.L99)/2
+ 1364 003b 0B       		.byte	(.L98-.L99)/2
+ 1365              		.p2align 1
+ 1366              	.L101:
+ 115:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1367              		.loc 1 115 11 is_stmt 1 view .LVU458
+ 1368 003c FFF7FEFF 		bl	USBD_GetDescriptor
+ 1369              	.LVL171:
+ 116:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1370              		.loc 1 116 11 view .LVU459
+ 1371 0040 F0E7     		b	.L96
+ 1372              	.LVL172:
+ 1373              	.L102:
+ 119:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1374              		.loc 1 119 11 view .LVU460
+ 1375 0042 FFF7FEFF 		bl	USBD_SetAddress
+ 1376              	.LVL173:
+ 120:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1377              		.loc 1 120 11 view .LVU461
+ 1378 0046 EDE7     		b	.L96
+ 1379              	.LVL174:
+ 1380              	.L98:
+ 123:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1381              		.loc 1 123 11 view .LVU462
+ 123:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1382              		.loc 1 123 17 is_stmt 0 view .LVU463
+ 1383 0048 FFF7FEFF 		bl	USBD_SetConfig
+ 1384              	.LVL175:
+ 123:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1385              		.loc 1 123 17 view .LVU464
+ 1386 004c 0446     		mov	r4, r0
+ 1387              	.LVL176:
+ 124:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1388              		.loc 1 124 11 is_stmt 1 view .LVU465
+ 1389 004e E9E7     		b	.L96
+ 1390              	.LVL177:
+ 1391              	.L100:
+ 127:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1392              		.loc 1 127 11 view .LVU466
+ 1393 0050 FFF7FEFF 		bl	USBD_GetConfig
+ 1394              	.LVL178:
+ARM GAS  /tmp/ccQ58aJU.s 			page 55
+
+
+ 128:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1395              		.loc 1 128 11 view .LVU467
+ 1396 0054 E6E7     		b	.L96
+ 1397              	.LVL179:
+ 1398              	.L105:
+ 131:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1399              		.loc 1 131 11 view .LVU468
+ 1400 0056 FFF7FEFF 		bl	USBD_GetStatus
+ 1401              	.LVL180:
+ 132:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1402              		.loc 1 132 11 view .LVU469
+ 102:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1403              		.loc 1 102 22 is_stmt 0 view .LVU470
+ 1404 005a 2C46     		mov	r4, r5
+ 132:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1405              		.loc 1 132 11 view .LVU471
+ 1406 005c E2E7     		b	.L96
+ 1407              	.LVL181:
+ 1408              	.L103:
+ 135:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1409              		.loc 1 135 11 is_stmt 1 view .LVU472
+ 1410 005e FFF7FEFF 		bl	USBD_SetFeature
+ 1411              	.LVL182:
+ 136:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1412              		.loc 1 136 11 view .LVU473
+ 1413 0062 DFE7     		b	.L96
+ 1414              	.LVL183:
+ 1415              	.L104:
+ 139:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1416              		.loc 1 139 11 view .LVU474
+ 1417 0064 FFF7FEFF 		bl	USBD_ClrFeature
+ 1418              	.LVL184:
+ 140:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1419              		.loc 1 140 11 view .LVU475
+ 1420 0068 DCE7     		b	.L96
+ 1421              	.LVL185:
+ 1422              	.L97:
+ 143:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1423              		.loc 1 143 11 view .LVU476
+ 1424 006a FFF7FEFF 		bl	USBD_CtlError
+ 1425              	.LVL186:
+ 144:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1426              		.loc 1 144 11 view .LVU477
+ 1427 006e D9E7     		b	.L96
+ 1428              		.cfi_endproc
+ 1429              	.LFE333:
+ 1431              		.section	.text.USBD_StdItfReq,"ax",%progbits
+ 1432              		.align	1
+ 1433              		.global	USBD_StdItfReq
+ 1434              		.syntax unified
+ 1435              		.thumb
+ 1436              		.thumb_func
+ 1438              	USBD_StdItfReq:
+ 1439              	.LVL187:
+ 1440              	.LFB334:
+ 164:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 1441              		.loc 1 164 1 view -0
+ARM GAS  /tmp/ccQ58aJU.s 			page 56
+
+
+ 1442              		.cfi_startproc
+ 1443              		@ args = 0, pretend = 0, frame = 0
+ 1444              		@ frame_needed = 0, uses_anonymous_args = 0
+ 164:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 1445              		.loc 1 164 1 is_stmt 0 view .LVU479
+ 1446 0000 70B5     		push	{r4, r5, r6, lr}
+ 1447              	.LCFI12:
+ 1448              		.cfi_def_cfa_offset 16
+ 1449              		.cfi_offset 4, -16
+ 1450              		.cfi_offset 5, -12
+ 1451              		.cfi_offset 6, -8
+ 1452              		.cfi_offset 14, -4
+ 1453 0002 0546     		mov	r5, r0
+ 1454 0004 0C46     		mov	r4, r1
+ 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1455              		.loc 1 165 3 is_stmt 1 view .LVU480
+ 1456              	.LVL188:
+ 167:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1457              		.loc 1 167 3 view .LVU481
+ 167:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1458              		.loc 1 167 14 is_stmt 0 view .LVU482
+ 1459 0006 0B78     		ldrb	r3, [r1]	@ zero_extendqisi2
+ 1460 0008 03F06003 		and	r3, r3, #96
+ 167:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1461              		.loc 1 167 3 view .LVU483
+ 1462 000c 202B     		cmp	r3, #32
+ 1463 000e 07D0     		beq	.L110
+ 1464 0010 402B     		cmp	r3, #64
+ 1465 0012 05D0     		beq	.L110
+ 1466 0014 23B1     		cbz	r3, .L110
+ 200:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1467              		.loc 1 200 7 is_stmt 1 view .LVU484
+ 1468 0016 FFF7FEFF 		bl	USBD_CtlError
+ 1469              	.LVL189:
+ 201:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 1470              		.loc 1 201 7 view .LVU485
+ 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1471              		.loc 1 165 22 is_stmt 0 view .LVU486
+ 1472 001a 0026     		movs	r6, #0
+ 1473              	.LVL190:
+ 1474              	.L114:
+ 204:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 1475              		.loc 1 204 3 is_stmt 1 view .LVU487
+ 205:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1476              		.loc 1 205 1 is_stmt 0 view .LVU488
+ 1477 001c 3046     		mov	r0, r6
+ 1478 001e 70BD     		pop	{r4, r5, r6, pc}
+ 1479              	.LVL191:
+ 1480              	.L110:
+ 172:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1481              		.loc 1 172 7 is_stmt 1 view .LVU489
+ 172:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1482              		.loc 1 172 19 is_stmt 0 view .LVU490
+ 1483 0020 95F89C32 		ldrb	r3, [r5, #668]	@ zero_extendqisi2
+ 1484 0024 013B     		subs	r3, r3, #1
+ 1485 0026 022B     		cmp	r3, #2
+ 1486 0028 18D8     		bhi	.L112
+ARM GAS  /tmp/ccQ58aJU.s 			page 57
+
+
+ 178:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 1487              		.loc 1 178 11 is_stmt 1 view .LVU491
+ 178:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 1488              		.loc 1 178 15 is_stmt 0 view .LVU492
+ 1489 002a 2379     		ldrb	r3, [r4, #4]	@ zero_extendqisi2
+ 178:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 1490              		.loc 1 178 14 view .LVU493
+ 1491 002c 012B     		cmp	r3, #1
+ 1492 002e 0FD8     		bhi	.L113
+ 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1493              		.loc 1 180 13 is_stmt 1 view .LVU494
+ 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1494              		.loc 1 180 43 is_stmt 0 view .LVU495
+ 1495 0030 D5F8B832 		ldr	r3, [r5, #696]
+ 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1496              		.loc 1 180 51 view .LVU496
+ 1497 0034 9B68     		ldr	r3, [r3, #8]
+ 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1498              		.loc 1 180 39 view .LVU497
+ 1499 0036 2146     		mov	r1, r4
+ 1500              	.LVL192:
+ 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1501              		.loc 1 180 39 view .LVU498
+ 1502 0038 2846     		mov	r0, r5
+ 1503              	.LVL193:
+ 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1504              		.loc 1 180 39 view .LVU499
+ 1505 003a 9847     		blx	r3
+ 1506              	.LVL194:
+ 1507 003c 0646     		mov	r6, r0
+ 1508              	.LVL195:
+ 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             {
+ 1509              		.loc 1 182 13 is_stmt 1 view .LVU500
+ 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             {
+ 1510              		.loc 1 182 21 is_stmt 0 view .LVU501
+ 1511 003e E388     		ldrh	r3, [r4, #6]
+ 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             {
+ 1512              		.loc 1 182 16 view .LVU502
+ 1513 0040 002B     		cmp	r3, #0
+ 1514 0042 EBD1     		bne	.L114
+ 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             {
+ 1515              		.loc 1 182 38 discriminator 1 view .LVU503
+ 1516 0044 0028     		cmp	r0, #0
+ 1517 0046 E9D1     		bne	.L114
+ 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             }
+ 1518              		.loc 1 184 15 is_stmt 1 view .LVU504
+ 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             }
+ 1519              		.loc 1 184 21 is_stmt 0 view .LVU505
+ 1520 0048 2846     		mov	r0, r5
+ 1521              	.LVL196:
+ 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****             }
+ 1522              		.loc 1 184 21 view .LVU506
+ 1523 004a FFF7FEFF 		bl	USBD_CtlSendStatus
+ 1524              	.LVL197:
+ 1525 004e E5E7     		b	.L114
+ 1526              	.LVL198:
+ 1527              	.L113:
+ARM GAS  /tmp/ccQ58aJU.s 			page 58
+
+
+ 189:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 1528              		.loc 1 189 13 is_stmt 1 view .LVU507
+ 1529 0050 2146     		mov	r1, r4
+ 1530              	.LVL199:
+ 189:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 1531              		.loc 1 189 13 is_stmt 0 view .LVU508
+ 1532 0052 2846     		mov	r0, r5
+ 1533              	.LVL200:
+ 189:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 1534              		.loc 1 189 13 view .LVU509
+ 1535 0054 FFF7FEFF 		bl	USBD_CtlError
+ 1536              	.LVL201:
+ 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1537              		.loc 1 165 22 view .LVU510
+ 1538 0058 0026     		movs	r6, #0
+ 1539 005a DFE7     		b	.L114
+ 1540              	.LVL202:
+ 1541              	.L112:
+ 194:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1542              		.loc 1 194 11 is_stmt 1 view .LVU511
+ 1543 005c 2146     		mov	r1, r4
+ 1544              	.LVL203:
+ 194:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1545              		.loc 1 194 11 is_stmt 0 view .LVU512
+ 1546 005e 2846     		mov	r0, r5
+ 1547              	.LVL204:
+ 194:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1548              		.loc 1 194 11 view .LVU513
+ 1549 0060 FFF7FEFF 		bl	USBD_CtlError
+ 1550              	.LVL205:
+ 195:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1551              		.loc 1 195 11 is_stmt 1 view .LVU514
+ 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1552              		.loc 1 165 22 is_stmt 0 view .LVU515
+ 1553 0064 0026     		movs	r6, #0
+ 195:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1554              		.loc 1 195 11 view .LVU516
+ 1555 0066 D9E7     		b	.L114
+ 1556              		.cfi_endproc
+ 1557              	.LFE334:
+ 1559              		.section	.text.USBD_StdEPReq,"ax",%progbits
+ 1560              		.align	1
+ 1561              		.global	USBD_StdEPReq
+ 1562              		.syntax unified
+ 1563              		.thumb
+ 1564              		.thumb_func
+ 1566              	USBD_StdEPReq:
+ 1567              	.LVL206:
+ 1568              	.LFB335:
+ 215:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_EndpointTypeDef *pep;
+ 1569              		.loc 1 215 1 is_stmt 1 view -0
+ 1570              		.cfi_startproc
+ 1571              		@ args = 0, pretend = 0, frame = 0
+ 1572              		@ frame_needed = 0, uses_anonymous_args = 0
+ 215:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_EndpointTypeDef *pep;
+ 1573              		.loc 1 215 1 is_stmt 0 view .LVU518
+ 1574 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ARM GAS  /tmp/ccQ58aJU.s 			page 59
+
+
+ 1575              	.LCFI13:
+ 1576              		.cfi_def_cfa_offset 24
+ 1577              		.cfi_offset 3, -24
+ 1578              		.cfi_offset 4, -20
+ 1579              		.cfi_offset 5, -16
+ 1580              		.cfi_offset 6, -12
+ 1581              		.cfi_offset 7, -8
+ 1582              		.cfi_offset 14, -4
+ 1583 0002 0646     		mov	r6, r0
+ 1584 0004 0D46     		mov	r5, r1
+ 216:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t ep_addr;
+ 1585              		.loc 1 216 3 is_stmt 1 view .LVU519
+ 217:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   USBD_StatusTypeDef ret = USBD_OK;
+ 1586              		.loc 1 217 3 view .LVU520
+ 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   ep_addr = LOBYTE(req->wIndex);
+ 1587              		.loc 1 218 3 view .LVU521
+ 1588              	.LVL207:
+ 219:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1589              		.loc 1 219 3 view .LVU522
+ 219:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1590              		.loc 1 219 13 is_stmt 0 view .LVU523
+ 1591 0006 8B88     		ldrh	r3, [r1, #4]
+ 1592              	.LVL208:
+ 221:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1593              		.loc 1 221 3 is_stmt 1 view .LVU524
+ 221:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1594              		.loc 1 221 14 is_stmt 0 view .LVU525
+ 1595 0008 0C78     		ldrb	r4, [r1]	@ zero_extendqisi2
+ 1596 000a 04F06004 		and	r4, r4, #96
+ 221:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1597              		.loc 1 221 3 view .LVU526
+ 1598 000e 202C     		cmp	r4, #32
+ 1599 0010 08D0     		beq	.L117
+ 1600 0012 D9B2     		uxtb	r1, r3
+ 1601              	.LVL209:
+ 221:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 1602              		.loc 1 221 3 view .LVU527
+ 1603 0014 402C     		cmp	r4, #64
+ 1604 0016 05D0     		beq	.L117
+ 1605 0018 6CB1     		cbz	r4, .L155
+ 365:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1606              		.loc 1 365 7 is_stmt 1 view .LVU528
+ 1607 001a 2946     		mov	r1, r5
+ 1608 001c FFF7FEFF 		bl	USBD_CtlError
+ 1609              	.LVL210:
+ 366:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 1610              		.loc 1 366 7 view .LVU529
+ 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   ep_addr = LOBYTE(req->wIndex);
+ 1611              		.loc 1 218 22 is_stmt 0 view .LVU530
+ 1612 0020 0024     		movs	r4, #0
+ 366:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 1613              		.loc 1 366 7 view .LVU531
+ 1614 0022 06E0     		b	.L120
+ 1615              	.LVL211:
+ 1616              	.L117:
+ 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1617              		.loc 1 225 7 is_stmt 1 view .LVU532
+ARM GAS  /tmp/ccQ58aJU.s 			page 60
+
+
+ 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1618              		.loc 1 225 37 is_stmt 0 view .LVU533
+ 1619 0024 D6F8B832 		ldr	r3, [r6, #696]
+ 1620              	.LVL212:
+ 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1621              		.loc 1 225 45 view .LVU534
+ 1622 0028 9B68     		ldr	r3, [r3, #8]
+ 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1623              		.loc 1 225 33 view .LVU535
+ 1624 002a 2946     		mov	r1, r5
+ 1625 002c 3046     		mov	r0, r6
+ 1626              	.LVL213:
+ 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1627              		.loc 1 225 33 view .LVU536
+ 1628 002e 9847     		blx	r3
+ 1629              	.LVL214:
+ 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       break;
+ 1630              		.loc 1 225 33 view .LVU537
+ 1631 0030 0446     		mov	r4, r0
+ 1632              	.LVL215:
+ 226:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1633              		.loc 1 226 7 is_stmt 1 view .LVU538
+ 1634              	.L120:
+ 369:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** }
+ 1635              		.loc 1 369 3 view .LVU539
+ 370:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1636              		.loc 1 370 1 is_stmt 0 view .LVU540
+ 1637 0032 2046     		mov	r0, r4
+ 1638 0034 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 1639              	.LVL216:
+ 1640              	.L155:
+ 229:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1641              		.loc 1 229 7 is_stmt 1 view .LVU541
+ 229:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       {
+ 1642              		.loc 1 229 18 is_stmt 0 view .LVU542
+ 1643 0036 6F78     		ldrb	r7, [r5, #1]	@ zero_extendqisi2
+ 1644 0038 012F     		cmp	r7, #1
+ 1645 003a 2FD0     		beq	.L121
+ 1646 003c 032F     		cmp	r7, #3
+ 1647 003e 05D0     		beq	.L122
+ 1648 0040 002F     		cmp	r7, #0
+ 1649 0042 59D0     		beq	.L156
+ 359:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           break;
+ 1650              		.loc 1 359 11 is_stmt 1 view .LVU543
+ 1651 0044 2946     		mov	r1, r5
+ 1652 0046 FFF7FEFF 		bl	USBD_CtlError
+ 1653              	.LVL217:
+ 360:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****       }
+ 1654              		.loc 1 360 11 view .LVU544
+ 1655 004a F2E7     		b	.L120
+ 1656              	.LVL218:
+ 1657              	.L122:
+ 232:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 1658              		.loc 1 232 11 discriminator 3 view .LVU545
+ 232:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 1659              		.loc 1 232 23 is_stmt 0 discriminator 3 view .LVU546
+ 1660 004c 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ARM GAS  /tmp/ccQ58aJU.s 			page 61
+
+
+ 1661              	.LVL219:
+ 232:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 1662              		.loc 1 232 23 discriminator 3 view .LVU547
+ 1663 0050 DBB2     		uxtb	r3, r3
+ 1664 0052 022B     		cmp	r3, #2
+ 1665 0054 05D0     		beq	.L125
+ 1666 0056 032B     		cmp	r3, #3
+ 1667 0058 12D0     		beq	.L126
+ 259:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 1668              		.loc 1 259 15 is_stmt 1 view .LVU548
+ 1669 005a 2946     		mov	r1, r5
+ 1670              	.LVL220:
+ 259:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 1671              		.loc 1 259 15 is_stmt 0 view .LVU549
+ 1672 005c FFF7FEFF 		bl	USBD_CtlError
+ 1673              	.LVL221:
+ 260:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 1674              		.loc 1 260 15 is_stmt 1 view .LVU550
+ 1675 0060 E7E7     		b	.L120
+ 1676              	.LVL222:
+ 1677              	.L125:
+ 235:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1678              		.loc 1 235 15 view .LVU551
+ 235:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1679              		.loc 1 235 18 is_stmt 0 view .LVU552
+ 1680 0062 09B1     		cbz	r1, .L128
+ 235:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1681              		.loc 1 235 38 discriminator 1 view .LVU553
+ 1682 0064 8029     		cmp	r1, #128
+ 1683 0066 04D1     		bne	.L157
+ 1684              	.L128:
+ 242:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1685              		.loc 1 242 17 is_stmt 1 view .LVU554
+ 1686 0068 2946     		mov	r1, r5
+ 1687              	.LVL223:
+ 242:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1688              		.loc 1 242 17 is_stmt 0 view .LVU555
+ 1689 006a 3046     		mov	r0, r6
+ 1690              	.LVL224:
+ 242:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1691              		.loc 1 242 17 view .LVU556
+ 1692 006c FFF7FEFF 		bl	USBD_CtlError
+ 1693              	.LVL225:
+ 242:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1694              		.loc 1 242 17 view .LVU557
+ 1695 0070 DFE7     		b	.L120
+ 1696              	.LVL226:
+ 1697              	.L157:
+ 237:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 (void)USBD_LL_StallEP(pdev, 0x80U);
+ 1698              		.loc 1 237 17 is_stmt 1 view .LVU558
+ 237:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 (void)USBD_LL_StallEP(pdev, 0x80U);
+ 1699              		.loc 1 237 23 is_stmt 0 view .LVU559
+ 1700 0072 FFF7FEFF 		bl	USBD_LL_StallEP
+ 1701              	.LVL227:
+ 238:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1702              		.loc 1 238 17 is_stmt 1 view .LVU560
+ 238:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ARM GAS  /tmp/ccQ58aJU.s 			page 62
+
+
+ 1703              		.loc 1 238 23 is_stmt 0 view .LVU561
+ 1704 0076 8021     		movs	r1, #128
+ 1705 0078 3046     		mov	r0, r6
+ 1706 007a FFF7FEFF 		bl	USBD_LL_StallEP
+ 1707              	.LVL228:
+ 238:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1708              		.loc 1 238 17 view .LVU562
+ 1709 007e D8E7     		b	.L120
+ 1710              	.LVL229:
+ 1711              	.L126:
+ 247:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1712              		.loc 1 247 15 is_stmt 1 view .LVU563
+ 247:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1713              		.loc 1 247 22 is_stmt 0 view .LVU564
+ 1714 0080 6B88     		ldrh	r3, [r5, #2]
+ 247:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1715              		.loc 1 247 18 view .LVU565
+ 1716 0082 23B9     		cbnz	r3, .L129
+ 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1717              		.loc 1 249 17 is_stmt 1 view .LVU566
+ 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1718              		.loc 1 249 20 is_stmt 0 view .LVU567
+ 1719 0084 19B1     		cbz	r1, .L129
+ 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1720              		.loc 1 249 40 discriminator 1 view .LVU568
+ 1721 0086 8029     		cmp	r1, #128
+ 1722 0088 01D0     		beq	.L129
+ 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1723              		.loc 1 249 69 discriminator 2 view .LVU569
+ 1724 008a EB88     		ldrh	r3, [r5, #6]
+ 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1725              		.loc 1 249 62 discriminator 2 view .LVU570
+ 1726 008c 1BB1     		cbz	r3, .L158
+ 1727              	.LVL230:
+ 1728              	.L129:
+ 254:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1729              		.loc 1 254 15 is_stmt 1 view .LVU571
+ 254:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1730              		.loc 1 254 21 is_stmt 0 view .LVU572
+ 1731 008e 3046     		mov	r0, r6
+ 1732 0090 FFF7FEFF 		bl	USBD_CtlSendStatus
+ 1733              	.LVL231:
+ 256:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1734              		.loc 1 256 15 is_stmt 1 view .LVU573
+ 1735 0094 CDE7     		b	.L120
+ 1736              	.LVL232:
+ 1737              	.L158:
+ 251:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 1738              		.loc 1 251 19 view .LVU574
+ 251:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 1739              		.loc 1 251 25 is_stmt 0 view .LVU575
+ 1740 0096 FFF7FEFF 		bl	USBD_LL_StallEP
+ 1741              	.LVL233:
+ 251:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 1742              		.loc 1 251 25 view .LVU576
+ 1743 009a F8E7     		b	.L129
+ 1744              	.LVL234:
+ARM GAS  /tmp/ccQ58aJU.s 			page 63
+
+
+ 1745              	.L121:
+ 266:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 1746              		.loc 1 266 11 is_stmt 1 discriminator 2 view .LVU577
+ 266:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 1747              		.loc 1 266 23 is_stmt 0 discriminator 2 view .LVU578
+ 1748 009c 90F89C32 		ldrb	r3, [r0, #668]	@ zero_extendqisi2
+ 1749              	.LVL235:
+ 266:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 1750              		.loc 1 266 23 discriminator 2 view .LVU579
+ 1751 00a0 DBB2     		uxtb	r3, r3
+ 1752 00a2 022B     		cmp	r3, #2
+ 1753 00a4 05D0     		beq	.L130
+ 1754 00a6 032B     		cmp	r3, #3
+ 1755 00a8 12D0     		beq	.L131
+ 293:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 1756              		.loc 1 293 15 is_stmt 1 view .LVU580
+ 1757 00aa 2946     		mov	r1, r5
+ 1758              	.LVL236:
+ 293:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 1759              		.loc 1 293 15 is_stmt 0 view .LVU581
+ 1760 00ac FFF7FEFF 		bl	USBD_CtlError
+ 1761              	.LVL237:
+ 294:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 1762              		.loc 1 294 15 is_stmt 1 view .LVU582
+ 1763 00b0 BFE7     		b	.L120
+ 1764              	.LVL238:
+ 1765              	.L130:
+ 269:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1766              		.loc 1 269 15 view .LVU583
+ 269:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1767              		.loc 1 269 18 is_stmt 0 view .LVU584
+ 1768 00b2 09B1     		cbz	r1, .L133
+ 269:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1769              		.loc 1 269 38 discriminator 1 view .LVU585
+ 1770 00b4 8029     		cmp	r1, #128
+ 1771 00b6 04D1     		bne	.L159
+ 1772              	.L133:
+ 276:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1773              		.loc 1 276 17 is_stmt 1 view .LVU586
+ 1774 00b8 2946     		mov	r1, r5
+ 1775              	.LVL239:
+ 276:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1776              		.loc 1 276 17 is_stmt 0 view .LVU587
+ 1777 00ba 3046     		mov	r0, r6
+ 1778              	.LVL240:
+ 276:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1779              		.loc 1 276 17 view .LVU588
+ 1780 00bc FFF7FEFF 		bl	USBD_CtlError
+ 1781              	.LVL241:
+ 276:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1782              		.loc 1 276 17 view .LVU589
+ 1783 00c0 B7E7     		b	.L120
+ 1784              	.LVL242:
+ 1785              	.L159:
+ 271:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 (void)USBD_LL_StallEP(pdev, 0x80U);
+ 1786              		.loc 1 271 17 is_stmt 1 view .LVU590
+ 271:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 (void)USBD_LL_StallEP(pdev, 0x80U);
+ARM GAS  /tmp/ccQ58aJU.s 			page 64
+
+
+ 1787              		.loc 1 271 23 is_stmt 0 view .LVU591
+ 1788 00c2 FFF7FEFF 		bl	USBD_LL_StallEP
+ 1789              	.LVL243:
+ 272:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1790              		.loc 1 272 17 is_stmt 1 view .LVU592
+ 272:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1791              		.loc 1 272 23 is_stmt 0 view .LVU593
+ 1792 00c6 8021     		movs	r1, #128
+ 1793 00c8 3046     		mov	r0, r6
+ 1794 00ca FFF7FEFF 		bl	USBD_LL_StallEP
+ 1795              	.LVL244:
+ 272:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1796              		.loc 1 272 17 view .LVU594
+ 1797 00ce B0E7     		b	.L120
+ 1798              	.LVL245:
+ 1799              	.L131:
+ 281:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1800              		.loc 1 281 15 is_stmt 1 view .LVU595
+ 281:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1801              		.loc 1 281 22 is_stmt 0 view .LVU596
+ 1802 00d0 6B88     		ldrh	r3, [r5, #2]
+ 281:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1803              		.loc 1 281 18 view .LVU597
+ 1804 00d2 002B     		cmp	r3, #0
+ 1805 00d4 ADD1     		bne	.L120
+ 283:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1806              		.loc 1 283 17 is_stmt 1 view .LVU598
+ 283:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1807              		.loc 1 283 20 is_stmt 0 view .LVU599
+ 1808 00d6 11F07F0F 		tst	r1, #127
+ 1809 00da 0AD1     		bne	.L160
+ 1810              	.LVL246:
+ 1811              	.L134:
+ 287:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+ 1812              		.loc 1 287 17 is_stmt 1 view .LVU600
+ 287:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+ 1813              		.loc 1 287 23 is_stmt 0 view .LVU601
+ 1814 00dc 3046     		mov	r0, r6
+ 1815 00de FFF7FEFF 		bl	USBD_CtlSendStatus
+ 1816              	.LVL247:
+ 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1817              		.loc 1 288 17 is_stmt 1 view .LVU602
+ 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1818              		.loc 1 288 47 is_stmt 0 view .LVU603
+ 1819 00e2 D6F8B832 		ldr	r3, [r6, #696]
+ 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1820              		.loc 1 288 55 view .LVU604
+ 1821 00e6 9B68     		ldr	r3, [r3, #8]
+ 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1822              		.loc 1 288 43 view .LVU605
+ 1823 00e8 2946     		mov	r1, r5
+ 1824 00ea 3046     		mov	r0, r6
+ 1825 00ec 9847     		blx	r3
+ 1826              	.LVL248:
+ 1827 00ee 0446     		mov	r4, r0
+ 1828              	.LVL249:
+ 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ARM GAS  /tmp/ccQ58aJU.s 			page 65
+
+
+ 1829              		.loc 1 288 43 view .LVU606
+ 1830 00f0 9FE7     		b	.L120
+ 1831              	.LVL250:
+ 1832              	.L160:
+ 285:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 1833              		.loc 1 285 19 is_stmt 1 view .LVU607
+ 285:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 1834              		.loc 1 285 25 is_stmt 0 view .LVU608
+ 1835 00f2 FFF7FEFF 		bl	USBD_LL_ClearStallEP
+ 1836              	.LVL251:
+ 285:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 1837              		.loc 1 285 25 view .LVU609
+ 1838 00f6 F1E7     		b	.L134
+ 1839              	.LVL252:
+ 1840              	.L156:
+ 299:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 1841              		.loc 1 299 11 is_stmt 1 discriminator 1 view .LVU610
+ 299:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           {
+ 1842              		.loc 1 299 23 is_stmt 0 discriminator 1 view .LVU611
+ 1843 00f8 90F89C22 		ldrb	r2, [r0, #668]	@ zero_extendqisi2
+ 1844 00fc D2B2     		uxtb	r2, r2
+ 1845 00fe 022A     		cmp	r2, #2
+ 1846 0100 06D0     		beq	.L135
+ 1847 0102 032A     		cmp	r2, #3
+ 1848 0104 29D0     		beq	.L136
+ 353:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 1849              		.loc 1 353 15 is_stmt 1 view .LVU612
+ 1850 0106 2946     		mov	r1, r5
+ 1851 0108 FFF7FEFF 		bl	USBD_CtlError
+ 1852              	.LVL253:
+ 354:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 1853              		.loc 1 354 15 view .LVU613
+ 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   ep_addr = LOBYTE(req->wIndex);
+ 1854              		.loc 1 218 22 is_stmt 0 view .LVU614
+ 1855 010c 3C46     		mov	r4, r7
+ 354:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****           }
+ 1856              		.loc 1 354 15 view .LVU615
+ 1857 010e 90E7     		b	.L120
+ 1858              	.LVL254:
+ 1859              	.L135:
+ 302:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1860              		.loc 1 302 15 is_stmt 1 view .LVU616
+ 302:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1861              		.loc 1 302 18 is_stmt 0 view .LVU617
+ 1862 0110 09B1     		cbz	r1, .L138
+ 302:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1863              		.loc 1 302 38 discriminator 1 view .LVU618
+ 1864 0112 8029     		cmp	r1, #128
+ 1865 0114 13D1     		bne	.L161
+ 1866              	.L138:
+ 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                     &pdev->ep_out[ep_addr & 0x7FU];
+ 1867              		.loc 1 307 15 is_stmt 1 view .LVU619
+ 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                     &pdev->ep_out[ep_addr & 0x7FU];
+ 1868              		.loc 1 307 82 is_stmt 0 view .LVU620
+ 1869 0116 13F0800F 		tst	r3, #128
+ 1870 011a 15D1     		bne	.L162
+ 308:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ARM GAS  /tmp/ccQ58aJU.s 			page 66
+
+
+ 1871              		.loc 1 308 43 discriminator 2 view .LVU621
+ 1872 011c 01F07F01 		and	r1, r1, #127
+ 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                     &pdev->ep_out[ep_addr & 0x7FU];
+ 1873              		.loc 1 307 82 discriminator 2 view .LVU622
+ 1874 0120 01EB8101 		add	r1, r1, r1, lsl #2
+ 1875 0124 8900     		lsls	r1, r1, #2
+ 1876 0126 01F5A871 		add	r1, r1, #336
+ 1877 012a 3144     		add	r1, r1, r6
+ 1878 012c 0431     		adds	r1, r1, #4
+ 1879              	.L140:
+ 1880              	.LVL255:
+ 310:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1881              		.loc 1 310 15 is_stmt 1 discriminator 4 view .LVU623
+ 310:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1882              		.loc 1 310 27 is_stmt 0 discriminator 4 view .LVU624
+ 1883 012e 0023     		movs	r3, #0
+ 1884              	.LVL256:
+ 310:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1885              		.loc 1 310 27 discriminator 4 view .LVU625
+ 1886 0130 0B60     		str	r3, [r1]
+ 1887              	.LVL257:
+ 312:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 1888              		.loc 1 312 15 is_stmt 1 discriminator 4 view .LVU626
+ 312:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 1889              		.loc 1 312 21 is_stmt 0 discriminator 4 view .LVU627
+ 1890 0132 0222     		movs	r2, #2
+ 1891 0134 3046     		mov	r0, r6
+ 1892              	.LVL258:
+ 312:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 1893              		.loc 1 312 21 discriminator 4 view .LVU628
+ 1894 0136 FFF7FEFF 		bl	USBD_CtlSendData
+ 1895              	.LVL259:
+ 313:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1896              		.loc 1 313 15 is_stmt 1 discriminator 4 view .LVU629
+ 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   ep_addr = LOBYTE(req->wIndex);
+ 1897              		.loc 1 218 22 is_stmt 0 discriminator 4 view .LVU630
+ 1898 013a 3C46     		mov	r4, r7
+ 313:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1899              		.loc 1 313 15 discriminator 4 view .LVU631
+ 1900 013c 79E7     		b	.L120
+ 1901              	.LVL260:
+ 1902              	.L161:
+ 304:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 break;
+ 1903              		.loc 1 304 17 is_stmt 1 view .LVU632
+ 1904 013e 2946     		mov	r1, r5
+ 1905 0140 FFF7FEFF 		bl	USBD_CtlError
+ 1906              	.LVL261:
+ 305:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1907              		.loc 1 305 17 view .LVU633
+ 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   ep_addr = LOBYTE(req->wIndex);
+ 1908              		.loc 1 218 22 is_stmt 0 view .LVU634
+ 1909 0144 3C46     		mov	r4, r7
+ 305:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1910              		.loc 1 305 17 view .LVU635
+ 1911 0146 74E7     		b	.L120
+ 1912              	.LVL262:
+ 1913              	.L162:
+ARM GAS  /tmp/ccQ58aJU.s 			page 67
+
+
+ 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                     &pdev->ep_out[ep_addr & 0x7FU];
+ 1914              		.loc 1 307 73 discriminator 1 view .LVU636
+ 1915 0148 01F07F01 		and	r1, r1, #127
+ 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                     &pdev->ep_out[ep_addr & 0x7FU];
+ 1916              		.loc 1 307 82 discriminator 1 view .LVU637
+ 1917 014c 01EB8101 		add	r1, r1, r1, lsl #2
+ 1918 0150 8900     		lsls	r1, r1, #2
+ 1919 0152 1031     		adds	r1, r1, #16
+ 1920 0154 3144     		add	r1, r1, r6
+ 1921 0156 0431     		adds	r1, r1, #4
+ 1922 0158 E9E7     		b	.L140
+ 1923              	.L136:
+ 316:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1924              		.loc 1 316 15 is_stmt 1 view .LVU638
+ 316:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1925              		.loc 1 316 37 is_stmt 0 view .LVU639
+ 1926 015a 5BB2     		sxtb	r3, r3
+ 316:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1927              		.loc 1 316 18 view .LVU640
+ 1928 015c 002B     		cmp	r3, #0
+ 1929 015e 1FDB     		blt	.L163
+ 326:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1930              		.loc 1 326 17 is_stmt 1 view .LVU641
+ 326:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1931              		.loc 1 326 42 is_stmt 0 view .LVU642
+ 1932 0160 01F00F02 		and	r2, r1, #15
+ 326:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1933              		.loc 1 326 49 view .LVU643
+ 1934 0164 02EB8202 		add	r2, r2, r2, lsl #2
+ 1935 0168 00EB8202 		add	r2, r0, r2, lsl #2
+ 1936 016c B2F86421 		ldrh	r2, [r2, #356]
+ 326:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1937              		.loc 1 326 20 view .LVU644
+ 1938 0170 22B3     		cbz	r2, .L164
+ 1939              	.L142:
+ 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                     &pdev->ep_out[ep_addr & 0x7FU];
+ 1940              		.loc 1 333 15 is_stmt 1 view .LVU645
+ 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                     &pdev->ep_out[ep_addr & 0x7FU];
+ 1941              		.loc 1 333 82 is_stmt 0 view .LVU646
+ 1942 0172 002B     		cmp	r3, #0
+ 1943 0174 27DB     		blt	.L165
+ 334:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1944              		.loc 1 334 43 discriminator 2 view .LVU647
+ 1945 0176 01F07F03 		and	r3, r1, #127
+ 1946              	.LVL263:
+ 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                     &pdev->ep_out[ep_addr & 0x7FU];
+ 1947              		.loc 1 333 82 discriminator 2 view .LVU648
+ 1948 017a 03EB8303 		add	r3, r3, r3, lsl #2
+ 1949 017e 9C00     		lsls	r4, r3, #2
+ 1950 0180 04F5A874 		add	r4, r4, #336
+ 1951 0184 3444     		add	r4, r4, r6
+ 1952 0186 0434     		adds	r4, r4, #4
+ 1953              	.L144:
+ 1954              	.LVL264:
+ 336:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1955              		.loc 1 336 15 is_stmt 1 discriminator 4 view .LVU649
+ 336:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ARM GAS  /tmp/ccQ58aJU.s 			page 68
+
+
+ 1956              		.loc 1 336 18 is_stmt 0 discriminator 4 view .LVU650
+ 1957 0188 09B1     		cbz	r1, .L145
+ 336:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 1958              		.loc 1 336 38 discriminator 1 view .LVU651
+ 1959 018a 8029     		cmp	r1, #128
+ 1960 018c 24D1     		bne	.L146
+ 1961              	.L145:
+ 338:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1962              		.loc 1 338 17 is_stmt 1 view .LVU652
+ 338:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 1963              		.loc 1 338 29 is_stmt 0 view .LVU653
+ 1964 018e 0023     		movs	r3, #0
+ 1965 0190 2360     		str	r3, [r4]
+ 1966              	.LVL265:
+ 1967              	.L147:
+ 349:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 1968              		.loc 1 349 15 is_stmt 1 view .LVU654
+ 349:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               break;
+ 1969              		.loc 1 349 21 is_stmt 0 view .LVU655
+ 1970 0192 0222     		movs	r2, #2
+ 1971 0194 2146     		mov	r1, r4
+ 1972 0196 3046     		mov	r0, r6
+ 1973 0198 FFF7FEFF 		bl	USBD_CtlSendData
+ 1974              	.LVL266:
+ 350:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1975              		.loc 1 350 15 is_stmt 1 view .LVU656
+ 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   ep_addr = LOBYTE(req->wIndex);
+ 1976              		.loc 1 218 22 is_stmt 0 view .LVU657
+ 1977 019c 3C46     		mov	r4, r7
+ 1978              	.LVL267:
+ 350:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 1979              		.loc 1 350 15 view .LVU658
+ 1980 019e 48E7     		b	.L120
+ 1981              	.LVL268:
+ 1982              	.L163:
+ 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1983              		.loc 1 318 17 is_stmt 1 view .LVU659
+ 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1984              		.loc 1 318 41 is_stmt 0 view .LVU660
+ 1985 01a0 01F00F02 		and	r2, r1, #15
+ 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1986              		.loc 1 318 48 view .LVU661
+ 1987 01a4 02EB8202 		add	r2, r2, r2, lsl #2
+ 1988 01a8 00EB8202 		add	r2, r0, r2, lsl #2
+ 1989 01ac 928C     		ldrh	r2, [r2, #36]
+ 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 {
+ 1990              		.loc 1 318 20 view .LVU662
+ 1991 01ae 002A     		cmp	r2, #0
+ 1992 01b0 DFD1     		bne	.L142
+ 320:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                   break;
+ 1993              		.loc 1 320 19 is_stmt 1 view .LVU663
+ 1994 01b2 2946     		mov	r1, r5
+ 1995 01b4 FFF7FEFF 		bl	USBD_CtlError
+ 1996              	.LVL269:
+ 321:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 1997              		.loc 1 321 19 view .LVU664
+ 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   ep_addr = LOBYTE(req->wIndex);
+ARM GAS  /tmp/ccQ58aJU.s 			page 69
+
+
+ 1998              		.loc 1 218 22 is_stmt 0 view .LVU665
+ 1999 01b8 3C46     		mov	r4, r7
+ 321:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 2000              		.loc 1 321 19 view .LVU666
+ 2001 01ba 3AE7     		b	.L120
+ 2002              	.LVL270:
+ 2003              	.L164:
+ 328:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                   break;
+ 2004              		.loc 1 328 19 is_stmt 1 view .LVU667
+ 2005 01bc 2946     		mov	r1, r5
+ 2006 01be FFF7FEFF 		bl	USBD_CtlError
+ 2007              	.LVL271:
+ 329:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 2008              		.loc 1 329 19 view .LVU668
+ 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   ep_addr = LOBYTE(req->wIndex);
+ 2009              		.loc 1 218 22 is_stmt 0 view .LVU669
+ 2010 01c2 3C46     		mov	r4, r7
+ 329:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                 }
+ 2011              		.loc 1 329 19 view .LVU670
+ 2012 01c4 35E7     		b	.L120
+ 2013              	.LVL272:
+ 2014              	.L165:
+ 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                     &pdev->ep_out[ep_addr & 0x7FU];
+ 2015              		.loc 1 333 73 discriminator 1 view .LVU671
+ 2016 01c6 01F07F03 		and	r3, r1, #127
+ 2017              	.LVL273:
+ 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****                     &pdev->ep_out[ep_addr & 0x7FU];
+ 2018              		.loc 1 333 82 discriminator 1 view .LVU672
+ 2019 01ca 03EB8303 		add	r3, r3, r3, lsl #2
+ 2020 01ce 9C00     		lsls	r4, r3, #2
+ 2021 01d0 1034     		adds	r4, r4, #16
+ 2022 01d2 3444     		add	r4, r4, r6
+ 2023 01d4 0434     		adds	r4, r4, #4
+ 2024 01d6 D7E7     		b	.L144
+ 2025              	.LVL274:
+ 2026              	.L146:
+ 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 2027              		.loc 1 340 20 is_stmt 1 view .LVU673
+ 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 2028              		.loc 1 340 24 is_stmt 0 view .LVU674
+ 2029 01d8 3046     		mov	r0, r6
+ 2030              	.LVL275:
+ 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 2031              		.loc 1 340 24 view .LVU675
+ 2032 01da FFF7FEFF 		bl	USBD_LL_IsStallEP
+ 2033              	.LVL276:
+ 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               {
+ 2034              		.loc 1 340 23 view .LVU676
+ 2035 01de 10B1     		cbz	r0, .L148
+ 342:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 2036              		.loc 1 342 17 is_stmt 1 view .LVU677
+ 342:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 2037              		.loc 1 342 29 is_stmt 0 view .LVU678
+ 2038 01e0 0123     		movs	r3, #1
+ 2039 01e2 2360     		str	r3, [r4]
+ 2040 01e4 D5E7     		b	.L147
+ 2041              	.L148:
+ARM GAS  /tmp/ccQ58aJU.s 			page 70
+
+
+ 346:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 2042              		.loc 1 346 17 is_stmt 1 view .LVU679
+ 346:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****               }
+ 2043              		.loc 1 346 29 is_stmt 0 view .LVU680
+ 2044 01e6 0023     		movs	r3, #0
+ 2045 01e8 2360     		str	r3, [r4]
+ 2046 01ea D2E7     		b	.L147
+ 2047              		.cfi_endproc
+ 2048              	.LFE335:
+ 2050              		.section	.text.USBD_GetString,"ax",%progbits
+ 2051              		.align	1
+ 2052              		.global	USBD_GetString
+ 2053              		.syntax unified
+ 2054              		.thumb
+ 2055              		.thumb_func
+ 2057              	USBD_GetString:
+ 2058              	.LVL277:
+ 2059              	.LFB345:
+ 886:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t idx = 0U;
+ 2060              		.loc 1 886 1 is_stmt 1 view -0
+ 2061              		.cfi_startproc
+ 2062              		@ args = 0, pretend = 0, frame = 0
+ 2063              		@ frame_needed = 0, uses_anonymous_args = 0
+ 887:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t *pdesc;
+ 2064              		.loc 1 887 3 view .LVU682
+ 888:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 2065              		.loc 1 888 3 view .LVU683
+ 890:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 2066              		.loc 1 890 3 view .LVU684
+ 890:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 2067              		.loc 1 890 6 is_stmt 0 view .LVU685
+ 2068 0000 D0B1     		cbz	r0, .L171
+ 886:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   uint8_t idx = 0U;
+ 2069              		.loc 1 886 1 view .LVU686
+ 2070 0002 70B5     		push	{r4, r5, r6, lr}
+ 2071              	.LCFI14:
+ 2072              		.cfi_def_cfa_offset 16
+ 2073              		.cfi_offset 4, -16
+ 2074              		.cfi_offset 5, -12
+ 2075              		.cfi_offset 6, -8
+ 2076              		.cfi_offset 14, -4
+ 2077 0004 0D46     		mov	r5, r1
+ 2078 0006 1646     		mov	r6, r2
+ 2079 0008 0446     		mov	r4, r0
+ 895:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   *len = ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U;
+ 2080              		.loc 1 895 3 is_stmt 1 view .LVU687
+ 2081              	.LVL278:
+ 896:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 2082              		.loc 1 896 3 view .LVU688
+ 896:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 2083              		.loc 1 896 21 is_stmt 0 view .LVU689
+ 2084 000a FFF7FEFF 		bl	USBD_GetLen
+ 2085              	.LVL279:
+ 896:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 2086              		.loc 1 896 46 view .LVU690
+ 2087 000e 431C     		adds	r3, r0, #1
+ 896:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ARM GAS  /tmp/ccQ58aJU.s 			page 71
+
+
+ 2088              		.loc 1 896 8 view .LVU691
+ 2089 0010 5B00     		lsls	r3, r3, #1
+ 2090 0012 9BB2     		uxth	r3, r3
+ 2091 0014 3380     		strh	r3, [r6]	@ movhi
+ 898:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   idx++;
+ 2092              		.loc 1 898 3 is_stmt 1 view .LVU692
+ 898:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   idx++;
+ 2093              		.loc 1 898 16 is_stmt 0 view .LVU693
+ 2094 0016 2B70     		strb	r3, [r5]
+ 899:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   unicode[idx] = USB_DESC_TYPE_STRING;
+ 2095              		.loc 1 899 3 is_stmt 1 view .LVU694
+ 2096              	.LVL280:
+ 900:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   idx++;
+ 2097              		.loc 1 900 3 view .LVU695
+ 900:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   idx++;
+ 2098              		.loc 1 900 16 is_stmt 0 view .LVU696
+ 2099 0018 0323     		movs	r3, #3
+ 2100 001a 6B70     		strb	r3, [r5, #1]
+ 901:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 2101              		.loc 1 901 3 is_stmt 1 view .LVU697
+ 2102              	.LVL281:
+ 903:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 2103              		.loc 1 903 3 view .LVU698
+ 901:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 2104              		.loc 1 901 6 is_stmt 0 view .LVU699
+ 2105 001c 0223     		movs	r3, #2
+ 903:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 2106              		.loc 1 903 9 view .LVU700
+ 2107 001e 07E0     		b	.L168
+ 2108              	.LVL282:
+ 2109              	.L169:
+ 905:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     pdesc++;
+ 2110              		.loc 1 905 5 is_stmt 1 view .LVU701
+ 905:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     pdesc++;
+ 2111              		.loc 1 905 18 is_stmt 0 view .LVU702
+ 2112 0020 EA54     		strb	r2, [r5, r3]
+ 906:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     idx++;
+ 2113              		.loc 1 906 5 is_stmt 1 view .LVU703
+ 906:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     idx++;
+ 2114              		.loc 1 906 10 is_stmt 0 view .LVU704
+ 2115 0022 0134     		adds	r4, r4, #1
+ 2116              	.LVL283:
+ 907:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 2117              		.loc 1 907 5 is_stmt 1 view .LVU705
+ 907:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 2118              		.loc 1 907 8 is_stmt 0 view .LVU706
+ 2119 0024 5A1C     		adds	r2, r3, #1
+ 2120 0026 D2B2     		uxtb	r2, r2
+ 2121              	.LVL284:
+ 909:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     idx++;
+ 2122              		.loc 1 909 5 is_stmt 1 view .LVU707
+ 909:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****     idx++;
+ 2123              		.loc 1 909 18 is_stmt 0 view .LVU708
+ 2124 0028 0021     		movs	r1, #0
+ 2125 002a A954     		strb	r1, [r5, r2]
+ 910:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 2126              		.loc 1 910 5 is_stmt 1 view .LVU709
+ARM GAS  /tmp/ccQ58aJU.s 			page 72
+
+
+ 910:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   }
+ 2127              		.loc 1 910 8 is_stmt 0 view .LVU710
+ 2128 002c 0233     		adds	r3, r3, #2
+ 2129 002e DBB2     		uxtb	r3, r3
+ 2130              	.LVL285:
+ 2131              	.L168:
+ 903:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 2132              		.loc 1 903 17 is_stmt 1 view .LVU711
+ 903:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 2133              		.loc 1 903 10 is_stmt 0 view .LVU712
+ 2134 0030 2278     		ldrb	r2, [r4]	@ zero_extendqisi2
+ 903:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c ****   {
+ 2135              		.loc 1 903 17 view .LVU713
+ 2136 0032 002A     		cmp	r2, #0
+ 2137 0034 F4D1     		bne	.L169
+ 912:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 2138              		.loc 1 912 1 view .LVU714
+ 2139 0036 70BD     		pop	{r4, r5, r6, pc}
+ 2140              	.LVL286:
+ 2141              	.L171:
+ 2142              	.LCFI15:
+ 2143              		.cfi_def_cfa_offset 0
+ 2144              		.cfi_restore 4
+ 2145              		.cfi_restore 5
+ 2146              		.cfi_restore 6
+ 2147              		.cfi_restore 14
+ 912:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** 
+ 2148              		.loc 1 912 1 view .LVU715
+ 2149 0038 7047     		bx	lr
+ 2150              		.cfi_endproc
+ 2151              	.LFE345:
+ 2153              		.section	.bss.cfgidx.0,"aw",%nobits
+ 2156              	cfgidx.0:
+ 2157 0000 00       		.space	1
+ 2158              		.text
+ 2159              	.Letext0:
+ 2160              		.file 3 "/usr/include/newlib/machine/_default_types.h"
+ 2161              		.file 4 "/usr/include/newlib/sys/_stdint.h"
+ 2162              		.file 5 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h"
+ 2163              		.file 6 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h"
+ARM GAS  /tmp/ccQ58aJU.s 			page 73
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 usbd_ctlreq.c
+     /tmp/ccQ58aJU.s:21     .text.USBD_GetLen:00000000 $t
+     /tmp/ccQ58aJU.s:26     .text.USBD_GetLen:00000000 USBD_GetLen
+     /tmp/ccQ58aJU.s:72     .text.USBD_SetFeature:00000000 $t
+     /tmp/ccQ58aJU.s:77     .text.USBD_SetFeature:00000000 USBD_SetFeature
+     /tmp/ccQ58aJU.s:115    .text.USBD_ParseSetupRequest:00000000 $t
+     /tmp/ccQ58aJU.s:121    .text.USBD_ParseSetupRequest:00000000 USBD_ParseSetupRequest
+     /tmp/ccQ58aJU.s:236    .text.USBD_CtlError:00000000 $t
+     /tmp/ccQ58aJU.s:242    .text.USBD_CtlError:00000000 USBD_CtlError
+     /tmp/ccQ58aJU.s:277    .text.USBD_GetDescriptor:00000000 $t
+     /tmp/ccQ58aJU.s:282    .text.USBD_GetDescriptor:00000000 USBD_GetDescriptor
+     /tmp/ccQ58aJU.s:320    .text.USBD_GetDescriptor:0000001e $d
+     /tmp/ccQ58aJU.s:469    .text.USBD_GetDescriptor:000000b0 $d
+     /tmp/ccQ58aJU.s:475    .text.USBD_GetDescriptor:000000b6 $t
+     /tmp/ccQ58aJU.s:750    .text.USBD_SetAddress:00000000 $t
+     /tmp/ccQ58aJU.s:755    .text.USBD_SetAddress:00000000 USBD_SetAddress
+     /tmp/ccQ58aJU.s:849    .text.USBD_SetConfig:00000000 $t
+     /tmp/ccQ58aJU.s:854    .text.USBD_SetConfig:00000000 USBD_SetConfig
+     /tmp/ccQ58aJU.s:1063   .text.USBD_SetConfig:000000c4 $d
+     /tmp/ccQ58aJU.s:2156   .bss.cfgidx.0:00000000 cfgidx.0
+     /tmp/ccQ58aJU.s:1068   .text.USBD_GetConfig:00000000 $t
+     /tmp/ccQ58aJU.s:1073   .text.USBD_GetConfig:00000000 USBD_GetConfig
+     /tmp/ccQ58aJU.s:1151   .text.USBD_GetStatus:00000000 $t
+     /tmp/ccQ58aJU.s:1156   .text.USBD_GetStatus:00000000 USBD_GetStatus
+     /tmp/ccQ58aJU.s:1227   .text.USBD_ClrFeature:00000000 $t
+     /tmp/ccQ58aJU.s:1232   .text.USBD_ClrFeature:00000000 USBD_ClrFeature
+     /tmp/ccQ58aJU.s:1286   .text.USBD_StdDevReq:00000000 $t
+     /tmp/ccQ58aJU.s:1292   .text.USBD_StdDevReq:00000000 USBD_StdDevReq
+     /tmp/ccQ58aJU.s:1355   .text.USBD_StdDevReq:00000032 $d
+     /tmp/ccQ58aJU.s:1365   .text.USBD_StdDevReq:0000003c $t
+     /tmp/ccQ58aJU.s:1432   .text.USBD_StdItfReq:00000000 $t
+     /tmp/ccQ58aJU.s:1438   .text.USBD_StdItfReq:00000000 USBD_StdItfReq
+     /tmp/ccQ58aJU.s:1560   .text.USBD_StdEPReq:00000000 $t
+     /tmp/ccQ58aJU.s:1566   .text.USBD_StdEPReq:00000000 USBD_StdEPReq
+     /tmp/ccQ58aJU.s:2051   .text.USBD_GetString:00000000 $t
+     /tmp/ccQ58aJU.s:2057   .text.USBD_GetString:00000000 USBD_GetString
+     /tmp/ccQ58aJU.s:2157   .bss.cfgidx.0:00000000 $d
+     /tmp/ccQ58aJU.s:335    .text.USBD_GetDescriptor:0000002d $d
+     /tmp/ccQ58aJU.s:335    .text.USBD_GetDescriptor:0000002e $t
+
+UNDEFINED SYMBOLS
+USBD_CtlSendStatus
+USBD_LL_StallEP
+USBD_CtlSendData
+USBD_LL_SetUSBAddress
+USBD_ClrClassConfig
+USBD_SetClassConfig
+USBD_LL_ClearStallEP
+USBD_LL_IsStallEP
diff --git a/squeow_sw/build/usbd_ctlreq.o b/squeow_sw/build/usbd_ctlreq.o
new file mode 100644
index 0000000000000000000000000000000000000000..6758051423e602385130834bd15fca7c2aaab604
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diff --git a/squeow_sw/build/usbd_desc.d b/squeow_sw/build/usbd_desc.d
new file mode 100644
index 0000000..6f04039
--- /dev/null
+++ b/squeow_sw/build/usbd_desc.d
@@ -0,0 +1,88 @@
+build/usbd_desc.o: Src/usbd_desc.c \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \
+ Inc/usbd_conf.h Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \
+ Inc/usbd_desc.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h:
+Inc/usbd_conf.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h:
+Inc/usbd_desc.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
diff --git a/squeow_sw/build/usbd_desc.lst b/squeow_sw/build/usbd_desc.lst
new file mode 100644
index 0000000..52afc53
--- /dev/null
+++ b/squeow_sw/build/usbd_desc.lst
@@ -0,0 +1,1131 @@
+ARM GAS  /tmp/ccDO9gP0.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"usbd_desc.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Src/usbd_desc.c"
+  20              		.section	.text.USBD_AUDIO_DeviceDescriptor,"ax",%progbits
+  21              		.align	1
+  22              		.global	USBD_AUDIO_DeviceDescriptor
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	USBD_AUDIO_DeviceDescriptor:
+  28              	.LVL0:
+  29              	.LFB333:
+   1:Src/usbd_desc.c **** /* USER CODE BEGIN Header */
+   2:Src/usbd_desc.c **** /**
+   3:Src/usbd_desc.c ****   ******************************************************************************
+   4:Src/usbd_desc.c ****   * @file           : usbd_desc.c
+   5:Src/usbd_desc.c ****   * @version        : v3.0_Cube
+   6:Src/usbd_desc.c ****   * @brief          : This file implements the USB device descriptors.
+   7:Src/usbd_desc.c ****   ******************************************************************************
+   8:Src/usbd_desc.c ****   * @attention
+   9:Src/usbd_desc.c ****   *
+  10:Src/usbd_desc.c ****   * Copyright (c) 2022 STMicroelectronics.
+  11:Src/usbd_desc.c ****   * All rights reserved.
+  12:Src/usbd_desc.c ****   *
+  13:Src/usbd_desc.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  14:Src/usbd_desc.c ****   * in the root directory of this software component.
+  15:Src/usbd_desc.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  16:Src/usbd_desc.c ****   *
+  17:Src/usbd_desc.c ****   ******************************************************************************
+  18:Src/usbd_desc.c ****   */
+  19:Src/usbd_desc.c **** /* USER CODE END Header */
+  20:Src/usbd_desc.c **** 
+  21:Src/usbd_desc.c **** /* Includes ------------------------------------------------------------------*/
+  22:Src/usbd_desc.c **** #include "usbd_core.h"
+  23:Src/usbd_desc.c **** #include "usbd_desc.h"
+  24:Src/usbd_desc.c **** #include "usbd_conf.h"
+  25:Src/usbd_desc.c **** 
+  26:Src/usbd_desc.c **** /* USER CODE BEGIN INCLUDE */
+  27:Src/usbd_desc.c **** 
+  28:Src/usbd_desc.c **** /* USER CODE END INCLUDE */
+  29:Src/usbd_desc.c **** 
+ARM GAS  /tmp/ccDO9gP0.s 			page 2
+
+
+  30:Src/usbd_desc.c **** /* Private typedef -----------------------------------------------------------*/
+  31:Src/usbd_desc.c **** /* Private define ------------------------------------------------------------*/
+  32:Src/usbd_desc.c **** /* Private macro -------------------------------------------------------------*/
+  33:Src/usbd_desc.c **** 
+  34:Src/usbd_desc.c **** /* USER CODE BEGIN PV */
+  35:Src/usbd_desc.c **** /* Private variables ---------------------------------------------------------*/
+  36:Src/usbd_desc.c **** 
+  37:Src/usbd_desc.c **** /* USER CODE END PV */
+  38:Src/usbd_desc.c **** 
+  39:Src/usbd_desc.c **** /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  40:Src/usbd_desc.c ****   * @{
+  41:Src/usbd_desc.c ****   */
+  42:Src/usbd_desc.c **** 
+  43:Src/usbd_desc.c **** /** @addtogroup USBD_DESC
+  44:Src/usbd_desc.c ****   * @{
+  45:Src/usbd_desc.c ****   */
+  46:Src/usbd_desc.c **** 
+  47:Src/usbd_desc.c **** /** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions
+  48:Src/usbd_desc.c ****   * @brief Private types.
+  49:Src/usbd_desc.c ****   * @{
+  50:Src/usbd_desc.c ****   */
+  51:Src/usbd_desc.c **** 
+  52:Src/usbd_desc.c **** /* USER CODE BEGIN PRIVATE_TYPES */
+  53:Src/usbd_desc.c **** 
+  54:Src/usbd_desc.c **** /* USER CODE END PRIVATE_TYPES */
+  55:Src/usbd_desc.c **** 
+  56:Src/usbd_desc.c **** /**
+  57:Src/usbd_desc.c ****   * @}
+  58:Src/usbd_desc.c ****   */
+  59:Src/usbd_desc.c **** 
+  60:Src/usbd_desc.c **** /** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines
+  61:Src/usbd_desc.c ****   * @brief Private defines.
+  62:Src/usbd_desc.c ****   * @{
+  63:Src/usbd_desc.c ****   */
+  64:Src/usbd_desc.c **** 
+  65:Src/usbd_desc.c **** #define USBD_VID     1155
+  66:Src/usbd_desc.c **** #define USBD_LANGID_STRING     1033
+  67:Src/usbd_desc.c **** #define USBD_MANUFACTURER_STRING     "STMicroelectronics"
+  68:Src/usbd_desc.c **** #define USBD_PID     22336
+  69:Src/usbd_desc.c **** #define USBD_PRODUCT_STRING     "STM32 Audio Class"
+  70:Src/usbd_desc.c **** #define USBD_CONFIGURATION_STRING     "AUDIO Config"
+  71:Src/usbd_desc.c **** #define USBD_INTERFACE_STRING     "AUDIO Interface"
+  72:Src/usbd_desc.c **** 
+  73:Src/usbd_desc.c **** /* USER CODE BEGIN PRIVATE_DEFINES */
+  74:Src/usbd_desc.c **** 
+  75:Src/usbd_desc.c **** /* USER CODE END PRIVATE_DEFINES */
+  76:Src/usbd_desc.c **** 
+  77:Src/usbd_desc.c **** /**
+  78:Src/usbd_desc.c ****   * @}
+  79:Src/usbd_desc.c ****   */
+  80:Src/usbd_desc.c **** 
+  81:Src/usbd_desc.c **** /* USER CODE BEGIN 0 */
+  82:Src/usbd_desc.c **** 
+  83:Src/usbd_desc.c **** /* USER CODE END 0 */
+  84:Src/usbd_desc.c **** 
+  85:Src/usbd_desc.c **** /** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros
+  86:Src/usbd_desc.c ****   * @brief Private macros.
+ARM GAS  /tmp/ccDO9gP0.s 			page 3
+
+
+  87:Src/usbd_desc.c ****   * @{
+  88:Src/usbd_desc.c ****   */
+  89:Src/usbd_desc.c **** 
+  90:Src/usbd_desc.c **** /* USER CODE BEGIN PRIVATE_MACRO */
+  91:Src/usbd_desc.c **** 
+  92:Src/usbd_desc.c **** /* USER CODE END PRIVATE_MACRO */
+  93:Src/usbd_desc.c **** 
+  94:Src/usbd_desc.c **** /**
+  95:Src/usbd_desc.c ****   * @}
+  96:Src/usbd_desc.c ****   */
+  97:Src/usbd_desc.c **** 
+  98:Src/usbd_desc.c **** /** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  99:Src/usbd_desc.c ****   * @brief Private functions declaration.
+ 100:Src/usbd_desc.c ****   * @{
+ 101:Src/usbd_desc.c ****   */
+ 102:Src/usbd_desc.c **** 
+ 103:Src/usbd_desc.c **** static void Get_SerialNum(void);
+ 104:Src/usbd_desc.c **** static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len);
+ 105:Src/usbd_desc.c **** 
+ 106:Src/usbd_desc.c **** /**
+ 107:Src/usbd_desc.c ****   * @}
+ 108:Src/usbd_desc.c ****   */
+ 109:Src/usbd_desc.c **** 
+ 110:Src/usbd_desc.c **** /** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+ 111:Src/usbd_desc.c ****   * @brief Private functions declaration.
+ 112:Src/usbd_desc.c ****   * @{
+ 113:Src/usbd_desc.c ****   */
+ 114:Src/usbd_desc.c **** 
+ 115:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+ 116:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+ 117:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+ 118:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+ 119:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+ 120:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+ 121:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+ 122:Src/usbd_desc.c **** 
+ 123:Src/usbd_desc.c **** /**
+ 124:Src/usbd_desc.c ****   * @}
+ 125:Src/usbd_desc.c ****   */
+ 126:Src/usbd_desc.c **** 
+ 127:Src/usbd_desc.c **** /** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+ 128:Src/usbd_desc.c ****   * @brief Private variables.
+ 129:Src/usbd_desc.c ****   * @{
+ 130:Src/usbd_desc.c ****   */
+ 131:Src/usbd_desc.c **** 
+ 132:Src/usbd_desc.c **** USBD_DescriptorsTypeDef AUDIO_Desc =
+ 133:Src/usbd_desc.c **** {
+ 134:Src/usbd_desc.c ****   USBD_AUDIO_DeviceDescriptor,
+ 135:Src/usbd_desc.c ****   USBD_AUDIO_LangIDStrDescriptor,
+ 136:Src/usbd_desc.c ****   USBD_AUDIO_ManufacturerStrDescriptor,
+ 137:Src/usbd_desc.c ****   USBD_AUDIO_ProductStrDescriptor,
+ 138:Src/usbd_desc.c ****   USBD_AUDIO_SerialStrDescriptor,
+ 139:Src/usbd_desc.c ****   USBD_AUDIO_ConfigStrDescriptor,
+ 140:Src/usbd_desc.c ****   USBD_AUDIO_InterfaceStrDescriptor
+ 141:Src/usbd_desc.c **** };
+ 142:Src/usbd_desc.c **** 
+ 143:Src/usbd_desc.c **** #if defined ( __ICCARM__ ) /* IAR Compiler */
+ARM GAS  /tmp/ccDO9gP0.s 			page 4
+
+
+ 144:Src/usbd_desc.c ****   #pragma data_alignment=4
+ 145:Src/usbd_desc.c **** #endif /* defined ( __ICCARM__ ) */
+ 146:Src/usbd_desc.c **** /** USB standard device descriptor. */
+ 147:Src/usbd_desc.c **** __ALIGN_BEGIN uint8_t USBD_AUDIO_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END =
+ 148:Src/usbd_desc.c **** {
+ 149:Src/usbd_desc.c ****   0x12,                       /*bLength */
+ 150:Src/usbd_desc.c ****   USB_DESC_TYPE_DEVICE,       /*bDescriptorType*/
+ 151:Src/usbd_desc.c ****   0x00,                       /*bcdUSB */
+ 152:Src/usbd_desc.c ****   0x02,
+ 153:Src/usbd_desc.c ****   0x00,                       /*bDeviceClass*/
+ 154:Src/usbd_desc.c ****   0x00,                       /*bDeviceSubClass*/
+ 155:Src/usbd_desc.c ****   0x00,                       /*bDeviceProtocol*/
+ 156:Src/usbd_desc.c ****   USB_MAX_EP0_SIZE,           /*bMaxPacketSize*/
+ 157:Src/usbd_desc.c ****   LOBYTE(USBD_VID),           /*idVendor*/
+ 158:Src/usbd_desc.c ****   HIBYTE(USBD_VID),           /*idVendor*/
+ 159:Src/usbd_desc.c ****   LOBYTE(USBD_PID),           /*idProduct*/
+ 160:Src/usbd_desc.c ****   HIBYTE(USBD_PID),           /*idProduct*/
+ 161:Src/usbd_desc.c ****   0x00,                       /*bcdDevice rel. 2.00*/
+ 162:Src/usbd_desc.c ****   0x02,
+ 163:Src/usbd_desc.c ****   USBD_IDX_MFC_STR,           /*Index of manufacturer  string*/
+ 164:Src/usbd_desc.c ****   USBD_IDX_PRODUCT_STR,       /*Index of product string*/
+ 165:Src/usbd_desc.c ****   USBD_IDX_SERIAL_STR,        /*Index of serial number string*/
+ 166:Src/usbd_desc.c ****   USBD_MAX_NUM_CONFIGURATION  /*bNumConfigurations*/
+ 167:Src/usbd_desc.c **** };
+ 168:Src/usbd_desc.c **** 
+ 169:Src/usbd_desc.c **** /* USB_DeviceDescriptor */
+ 170:Src/usbd_desc.c **** 
+ 171:Src/usbd_desc.c **** /**
+ 172:Src/usbd_desc.c ****   * @}
+ 173:Src/usbd_desc.c ****   */
+ 174:Src/usbd_desc.c **** 
+ 175:Src/usbd_desc.c **** /** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+ 176:Src/usbd_desc.c ****   * @brief Private variables.
+ 177:Src/usbd_desc.c ****   * @{
+ 178:Src/usbd_desc.c ****   */
+ 179:Src/usbd_desc.c **** 
+ 180:Src/usbd_desc.c **** #if defined ( __ICCARM__ ) /* IAR Compiler */
+ 181:Src/usbd_desc.c ****   #pragma data_alignment=4
+ 182:Src/usbd_desc.c **** #endif /* defined ( __ICCARM__ ) */
+ 183:Src/usbd_desc.c **** 
+ 184:Src/usbd_desc.c **** /** USB lang identifier descriptor. */
+ 185:Src/usbd_desc.c **** __ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =
+ 186:Src/usbd_desc.c **** {
+ 187:Src/usbd_desc.c ****      USB_LEN_LANGID_STR_DESC,
+ 188:Src/usbd_desc.c ****      USB_DESC_TYPE_STRING,
+ 189:Src/usbd_desc.c ****      LOBYTE(USBD_LANGID_STRING),
+ 190:Src/usbd_desc.c ****      HIBYTE(USBD_LANGID_STRING)
+ 191:Src/usbd_desc.c **** };
+ 192:Src/usbd_desc.c **** 
+ 193:Src/usbd_desc.c **** #if defined ( __ICCARM__ ) /* IAR Compiler */
+ 194:Src/usbd_desc.c ****   #pragma data_alignment=4
+ 195:Src/usbd_desc.c **** #endif /* defined ( __ICCARM__ ) */
+ 196:Src/usbd_desc.c **** /* Internal string descriptor. */
+ 197:Src/usbd_desc.c **** __ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
+ 198:Src/usbd_desc.c **** 
+ 199:Src/usbd_desc.c **** #if defined ( __ICCARM__ ) /*!< IAR Compiler */
+ 200:Src/usbd_desc.c ****   #pragma data_alignment=4
+ARM GAS  /tmp/ccDO9gP0.s 			page 5
+
+
+ 201:Src/usbd_desc.c **** #endif
+ 202:Src/usbd_desc.c **** __ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = {
+ 203:Src/usbd_desc.c ****   USB_SIZ_STRING_SERIAL,
+ 204:Src/usbd_desc.c ****   USB_DESC_TYPE_STRING,
+ 205:Src/usbd_desc.c **** };
+ 206:Src/usbd_desc.c **** 
+ 207:Src/usbd_desc.c **** /**
+ 208:Src/usbd_desc.c ****   * @}
+ 209:Src/usbd_desc.c ****   */
+ 210:Src/usbd_desc.c **** 
+ 211:Src/usbd_desc.c **** /** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions
+ 212:Src/usbd_desc.c ****   * @brief Private functions.
+ 213:Src/usbd_desc.c ****   * @{
+ 214:Src/usbd_desc.c ****   */
+ 215:Src/usbd_desc.c **** 
+ 216:Src/usbd_desc.c **** /**
+ 217:Src/usbd_desc.c ****   * @brief  Return the device descriptor
+ 218:Src/usbd_desc.c ****   * @param  speed : Current device speed
+ 219:Src/usbd_desc.c ****   * @param  length : Pointer to data length variable
+ 220:Src/usbd_desc.c ****   * @retval Pointer to descriptor buffer
+ 221:Src/usbd_desc.c ****   */
+ 222:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+ 223:Src/usbd_desc.c **** {
+  30              		.loc 1 223 1 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		@ link register save eliminated.
+ 224:Src/usbd_desc.c ****   UNUSED(speed);
+  35              		.loc 1 224 3 view .LVU1
+ 225:Src/usbd_desc.c ****   *length = sizeof(USBD_AUDIO_DeviceDesc);
+  36              		.loc 1 225 3 view .LVU2
+  37              		.loc 1 225 11 is_stmt 0 view .LVU3
+  38 0000 1223     		movs	r3, #18
+  39 0002 0B80     		strh	r3, [r1]	@ movhi
+ 226:Src/usbd_desc.c ****   return USBD_AUDIO_DeviceDesc;
+  40              		.loc 1 226 3 is_stmt 1 view .LVU4
+ 227:Src/usbd_desc.c **** }
+  41              		.loc 1 227 1 is_stmt 0 view .LVU5
+  42 0004 0048     		ldr	r0, .L2
+  43              	.LVL1:
+  44              		.loc 1 227 1 view .LVU6
+  45 0006 7047     		bx	lr
+  46              	.L3:
+  47              		.align	2
+  48              	.L2:
+  49 0008 00000000 		.word	USBD_AUDIO_DeviceDesc
+  50              		.cfi_endproc
+  51              	.LFE333:
+  53              		.section	.text.USBD_AUDIO_LangIDStrDescriptor,"ax",%progbits
+  54              		.align	1
+  55              		.global	USBD_AUDIO_LangIDStrDescriptor
+  56              		.syntax unified
+  57              		.thumb
+  58              		.thumb_func
+  60              	USBD_AUDIO_LangIDStrDescriptor:
+  61              	.LVL2:
+ARM GAS  /tmp/ccDO9gP0.s 			page 6
+
+
+  62              	.LFB334:
+ 228:Src/usbd_desc.c **** 
+ 229:Src/usbd_desc.c **** /**
+ 230:Src/usbd_desc.c ****   * @brief  Return the LangID string descriptor
+ 231:Src/usbd_desc.c ****   * @param  speed : Current device speed
+ 232:Src/usbd_desc.c ****   * @param  length : Pointer to data length variable
+ 233:Src/usbd_desc.c ****   * @retval Pointer to descriptor buffer
+ 234:Src/usbd_desc.c ****   */
+ 235:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+ 236:Src/usbd_desc.c **** {
+  63              		.loc 1 236 1 is_stmt 1 view -0
+  64              		.cfi_startproc
+  65              		@ args = 0, pretend = 0, frame = 0
+  66              		@ frame_needed = 0, uses_anonymous_args = 0
+  67              		@ link register save eliminated.
+ 237:Src/usbd_desc.c ****   UNUSED(speed);
+  68              		.loc 1 237 3 view .LVU8
+ 238:Src/usbd_desc.c ****   *length = sizeof(USBD_LangIDDesc);
+  69              		.loc 1 238 3 view .LVU9
+  70              		.loc 1 238 11 is_stmt 0 view .LVU10
+  71 0000 0423     		movs	r3, #4
+  72 0002 0B80     		strh	r3, [r1]	@ movhi
+ 239:Src/usbd_desc.c ****   return USBD_LangIDDesc;
+  73              		.loc 1 239 3 is_stmt 1 view .LVU11
+ 240:Src/usbd_desc.c **** }
+  74              		.loc 1 240 1 is_stmt 0 view .LVU12
+  75 0004 0048     		ldr	r0, .L5
+  76              	.LVL3:
+  77              		.loc 1 240 1 view .LVU13
+  78 0006 7047     		bx	lr
+  79              	.L6:
+  80              		.align	2
+  81              	.L5:
+  82 0008 00000000 		.word	USBD_LangIDDesc
+  83              		.cfi_endproc
+  84              	.LFE334:
+  86              		.section	.text.IntToUnicode,"ax",%progbits
+  87              		.align	1
+  88              		.syntax unified
+  89              		.thumb
+  90              		.thumb_func
+  92              	IntToUnicode:
+  93              	.LVL4:
+  94              	.LFB341:
+ 241:Src/usbd_desc.c **** 
+ 242:Src/usbd_desc.c **** /**
+ 243:Src/usbd_desc.c ****   * @brief  Return the product string descriptor
+ 244:Src/usbd_desc.c ****   * @param  speed : Current device speed
+ 245:Src/usbd_desc.c ****   * @param  length : Pointer to data length variable
+ 246:Src/usbd_desc.c ****   * @retval Pointer to descriptor buffer
+ 247:Src/usbd_desc.c ****   */
+ 248:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+ 249:Src/usbd_desc.c **** {
+ 250:Src/usbd_desc.c ****   if(speed == 0)
+ 251:Src/usbd_desc.c ****   {
+ 252:Src/usbd_desc.c ****     USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length);
+ 253:Src/usbd_desc.c ****   }
+ARM GAS  /tmp/ccDO9gP0.s 			page 7
+
+
+ 254:Src/usbd_desc.c ****   else
+ 255:Src/usbd_desc.c ****   {
+ 256:Src/usbd_desc.c ****     USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length);
+ 257:Src/usbd_desc.c ****   }
+ 258:Src/usbd_desc.c ****   return USBD_StrDesc;
+ 259:Src/usbd_desc.c **** }
+ 260:Src/usbd_desc.c **** 
+ 261:Src/usbd_desc.c **** /**
+ 262:Src/usbd_desc.c ****   * @brief  Return the manufacturer string descriptor
+ 263:Src/usbd_desc.c ****   * @param  speed : Current device speed
+ 264:Src/usbd_desc.c ****   * @param  length : Pointer to data length variable
+ 265:Src/usbd_desc.c ****   * @retval Pointer to descriptor buffer
+ 266:Src/usbd_desc.c ****   */
+ 267:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+ 268:Src/usbd_desc.c **** {
+ 269:Src/usbd_desc.c ****   UNUSED(speed);
+ 270:Src/usbd_desc.c ****   USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
+ 271:Src/usbd_desc.c ****   return USBD_StrDesc;
+ 272:Src/usbd_desc.c **** }
+ 273:Src/usbd_desc.c **** 
+ 274:Src/usbd_desc.c **** /**
+ 275:Src/usbd_desc.c ****   * @brief  Return the serial number string descriptor
+ 276:Src/usbd_desc.c ****   * @param  speed : Current device speed
+ 277:Src/usbd_desc.c ****   * @param  length : Pointer to data length variable
+ 278:Src/usbd_desc.c ****   * @retval Pointer to descriptor buffer
+ 279:Src/usbd_desc.c ****   */
+ 280:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+ 281:Src/usbd_desc.c **** {
+ 282:Src/usbd_desc.c ****   UNUSED(speed);
+ 283:Src/usbd_desc.c ****   *length = USB_SIZ_STRING_SERIAL;
+ 284:Src/usbd_desc.c **** 
+ 285:Src/usbd_desc.c ****   /* Update the serial number string descriptor with the data from the unique
+ 286:Src/usbd_desc.c ****    * ID */
+ 287:Src/usbd_desc.c ****   Get_SerialNum();
+ 288:Src/usbd_desc.c **** 
+ 289:Src/usbd_desc.c ****   /* USER CODE BEGIN USBD_AUDIO_SerialStrDescriptor */
+ 290:Src/usbd_desc.c **** 
+ 291:Src/usbd_desc.c ****   /* USER CODE END USBD_AUDIO_SerialStrDescriptor */
+ 292:Src/usbd_desc.c **** 
+ 293:Src/usbd_desc.c ****   return (uint8_t *) USBD_StringSerial;
+ 294:Src/usbd_desc.c **** }
+ 295:Src/usbd_desc.c **** 
+ 296:Src/usbd_desc.c **** /**
+ 297:Src/usbd_desc.c ****   * @brief  Return the configuration string descriptor
+ 298:Src/usbd_desc.c ****   * @param  speed : Current device speed
+ 299:Src/usbd_desc.c ****   * @param  length : Pointer to data length variable
+ 300:Src/usbd_desc.c ****   * @retval Pointer to descriptor buffer
+ 301:Src/usbd_desc.c ****   */
+ 302:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+ 303:Src/usbd_desc.c **** {
+ 304:Src/usbd_desc.c ****   if(speed == USBD_SPEED_HIGH)
+ 305:Src/usbd_desc.c ****   {
+ 306:Src/usbd_desc.c ****     USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length);
+ 307:Src/usbd_desc.c ****   }
+ 308:Src/usbd_desc.c ****   else
+ 309:Src/usbd_desc.c ****   {
+ 310:Src/usbd_desc.c ****     USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length);
+ARM GAS  /tmp/ccDO9gP0.s 			page 8
+
+
+ 311:Src/usbd_desc.c ****   }
+ 312:Src/usbd_desc.c ****   return USBD_StrDesc;
+ 313:Src/usbd_desc.c **** }
+ 314:Src/usbd_desc.c **** 
+ 315:Src/usbd_desc.c **** /**
+ 316:Src/usbd_desc.c ****   * @brief  Return the interface string descriptor
+ 317:Src/usbd_desc.c ****   * @param  speed : Current device speed
+ 318:Src/usbd_desc.c ****   * @param  length : Pointer to data length variable
+ 319:Src/usbd_desc.c ****   * @retval Pointer to descriptor buffer
+ 320:Src/usbd_desc.c ****   */
+ 321:Src/usbd_desc.c **** uint8_t * USBD_AUDIO_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+ 322:Src/usbd_desc.c **** {
+ 323:Src/usbd_desc.c ****   if(speed == 0)
+ 324:Src/usbd_desc.c ****   {
+ 325:Src/usbd_desc.c ****     USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length);
+ 326:Src/usbd_desc.c ****   }
+ 327:Src/usbd_desc.c ****   else
+ 328:Src/usbd_desc.c ****   {
+ 329:Src/usbd_desc.c ****     USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length);
+ 330:Src/usbd_desc.c ****   }
+ 331:Src/usbd_desc.c ****   return USBD_StrDesc;
+ 332:Src/usbd_desc.c **** }
+ 333:Src/usbd_desc.c **** 
+ 334:Src/usbd_desc.c **** /**
+ 335:Src/usbd_desc.c ****   * @brief  Create the serial number string descriptor
+ 336:Src/usbd_desc.c ****   * @param  None
+ 337:Src/usbd_desc.c ****   * @retval None
+ 338:Src/usbd_desc.c ****   */
+ 339:Src/usbd_desc.c **** static void Get_SerialNum(void)
+ 340:Src/usbd_desc.c **** {
+ 341:Src/usbd_desc.c ****   uint32_t deviceserial0;
+ 342:Src/usbd_desc.c ****   uint32_t deviceserial1;
+ 343:Src/usbd_desc.c ****   uint32_t deviceserial2;
+ 344:Src/usbd_desc.c **** 
+ 345:Src/usbd_desc.c ****   deviceserial0 = *(uint32_t *) DEVICE_ID1;
+ 346:Src/usbd_desc.c ****   deviceserial1 = *(uint32_t *) DEVICE_ID2;
+ 347:Src/usbd_desc.c ****   deviceserial2 = *(uint32_t *) DEVICE_ID3;
+ 348:Src/usbd_desc.c **** 
+ 349:Src/usbd_desc.c ****   deviceserial0 += deviceserial2;
+ 350:Src/usbd_desc.c **** 
+ 351:Src/usbd_desc.c ****   if (deviceserial0 != 0)
+ 352:Src/usbd_desc.c ****   {
+ 353:Src/usbd_desc.c ****     IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
+ 354:Src/usbd_desc.c ****     IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
+ 355:Src/usbd_desc.c ****   }
+ 356:Src/usbd_desc.c **** }
+ 357:Src/usbd_desc.c **** 
+ 358:Src/usbd_desc.c **** /**
+ 359:Src/usbd_desc.c ****   * @brief  Convert Hex 32Bits value into char
+ 360:Src/usbd_desc.c ****   * @param  value: value to convert
+ 361:Src/usbd_desc.c ****   * @param  pbuf: pointer to the buffer
+ 362:Src/usbd_desc.c ****   * @param  len: buffer length
+ 363:Src/usbd_desc.c ****   * @retval None
+ 364:Src/usbd_desc.c ****   */
+ 365:Src/usbd_desc.c **** static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
+ 366:Src/usbd_desc.c **** {
+  95              		.loc 1 366 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccDO9gP0.s 			page 9
+
+
+  96              		.cfi_startproc
+  97              		@ args = 0, pretend = 0, frame = 0
+  98              		@ frame_needed = 0, uses_anonymous_args = 0
+ 367:Src/usbd_desc.c ****   uint8_t idx = 0;
+  99              		.loc 1 367 3 view .LVU15
+ 368:Src/usbd_desc.c **** 
+ 369:Src/usbd_desc.c ****   for (idx = 0; idx < len; idx++)
+ 100              		.loc 1 369 3 view .LVU16
+ 101              		.loc 1 369 12 is_stmt 0 view .LVU17
+ 102 0000 0023     		movs	r3, #0
+ 103              	.LVL5:
+ 104              		.loc 1 369 21 is_stmt 1 view .LVU18
+ 105 0002 9342     		cmp	r3, r2
+ 106 0004 1ED2     		bcs	.L15
+ 366:Src/usbd_desc.c ****   uint8_t idx = 0;
+ 107              		.loc 1 366 1 is_stmt 0 view .LVU19
+ 108 0006 00B5     		push	{lr}
+ 109              	.LCFI0:
+ 110              		.cfi_def_cfa_offset 4
+ 111              		.cfi_offset 14, -4
+ 112 0008 10E0     		b	.L11
+ 113              	.L9:
+ 370:Src/usbd_desc.c ****   {
+ 371:Src/usbd_desc.c ****     if (((value >> 28)) < 0xA)
+ 372:Src/usbd_desc.c ****     {
+ 373:Src/usbd_desc.c ****       pbuf[2 * idx] = (value >> 28) + '0';
+ 374:Src/usbd_desc.c ****     }
+ 375:Src/usbd_desc.c ****     else
+ 376:Src/usbd_desc.c ****     {
+ 377:Src/usbd_desc.c ****       pbuf[2 * idx] = (value >> 28) + 'A' - 10;
+ 114              		.loc 1 377 7 is_stmt 1 view .LVU20
+ 115              		.loc 1 377 43 is_stmt 0 view .LVU21
+ 116 000a 0CF1370C 		add	ip, ip, #55
+ 117              		.loc 1 377 21 view .LVU22
+ 118 000e 01F813C0 		strb	ip, [r1, r3, lsl #1]
+ 119              	.L10:
+ 378:Src/usbd_desc.c ****     }
+ 379:Src/usbd_desc.c **** 
+ 380:Src/usbd_desc.c ****     value = value << 4;
+ 120              		.loc 1 380 5 is_stmt 1 discriminator 2 view .LVU23
+ 121              		.loc 1 380 11 is_stmt 0 discriminator 2 view .LVU24
+ 122 0012 0001     		lsls	r0, r0, #4
+ 123              	.LVL6:
+ 381:Src/usbd_desc.c **** 
+ 382:Src/usbd_desc.c ****     pbuf[2 * idx + 1] = 0;
+ 124              		.loc 1 382 5 is_stmt 1 discriminator 2 view .LVU25
+ 125              		.loc 1 382 12 is_stmt 0 discriminator 2 view .LVU26
+ 126 0014 4FEA430C 		lsl	ip, r3, #1
+ 127              		.loc 1 382 9 discriminator 2 view .LVU27
+ 128 0018 0CF1010C 		add	ip, ip, #1
+ 129              		.loc 1 382 23 discriminator 2 view .LVU28
+ 130 001c 4FF0000E 		mov	lr, #0
+ 131 0020 01F80CE0 		strb	lr, [r1, ip]
+ 369:Src/usbd_desc.c ****   {
+ 132              		.loc 1 369 31 is_stmt 1 discriminator 2 view .LVU29
+ 133 0024 0133     		adds	r3, r3, #1
+ 134              	.LVL7:
+ARM GAS  /tmp/ccDO9gP0.s 			page 10
+
+
+ 369:Src/usbd_desc.c ****   {
+ 135              		.loc 1 369 31 is_stmt 0 discriminator 2 view .LVU30
+ 136 0026 DBB2     		uxtb	r3, r3
+ 137              	.LVL8:
+ 369:Src/usbd_desc.c ****   {
+ 138              		.loc 1 369 21 is_stmt 1 discriminator 2 view .LVU31
+ 139 0028 9342     		cmp	r3, r2
+ 140 002a 09D2     		bcs	.L16
+ 141              	.L11:
+ 371:Src/usbd_desc.c ****     {
+ 142              		.loc 1 371 5 view .LVU32
+ 371:Src/usbd_desc.c ****     {
+ 143              		.loc 1 371 17 is_stmt 0 view .LVU33
+ 144 002c 4FEA107C 		lsr	ip, r0, #28
+ 371:Src/usbd_desc.c ****     {
+ 145              		.loc 1 371 8 view .LVU34
+ 146 0030 B0F1204F 		cmp	r0, #-1610612736
+ 147 0034 E9D2     		bcs	.L9
+ 373:Src/usbd_desc.c ****     }
+ 148              		.loc 1 373 7 is_stmt 1 view .LVU35
+ 373:Src/usbd_desc.c ****     }
+ 149              		.loc 1 373 37 is_stmt 0 view .LVU36
+ 150 0036 0CF1300C 		add	ip, ip, #48
+ 373:Src/usbd_desc.c ****     }
+ 151              		.loc 1 373 21 view .LVU37
+ 152 003a 01F813C0 		strb	ip, [r1, r3, lsl #1]
+ 153 003e E8E7     		b	.L10
+ 154              	.L16:
+ 383:Src/usbd_desc.c ****   }
+ 384:Src/usbd_desc.c **** }
+ 155              		.loc 1 384 1 view .LVU38
+ 156 0040 5DF804FB 		ldr	pc, [sp], #4
+ 157              	.L15:
+ 158              	.LCFI1:
+ 159              		.cfi_def_cfa_offset 0
+ 160              		.cfi_restore 14
+ 161              		.loc 1 384 1 view .LVU39
+ 162 0044 7047     		bx	lr
+ 163              		.cfi_endproc
+ 164              	.LFE341:
+ 166              		.section	.text.Get_SerialNum,"ax",%progbits
+ 167              		.align	1
+ 168              		.syntax unified
+ 169              		.thumb
+ 170              		.thumb_func
+ 172              	Get_SerialNum:
+ 173              	.LFB340:
+ 340:Src/usbd_desc.c ****   uint32_t deviceserial0;
+ 174              		.loc 1 340 1 is_stmt 1 view -0
+ 175              		.cfi_startproc
+ 176              		@ args = 0, pretend = 0, frame = 0
+ 177              		@ frame_needed = 0, uses_anonymous_args = 0
+ 178 0000 38B5     		push	{r3, r4, r5, lr}
+ 179              	.LCFI2:
+ 180              		.cfi_def_cfa_offset 16
+ 181              		.cfi_offset 3, -16
+ 182              		.cfi_offset 4, -12
+ARM GAS  /tmp/ccDO9gP0.s 			page 11
+
+
+ 183              		.cfi_offset 5, -8
+ 184              		.cfi_offset 14, -4
+ 341:Src/usbd_desc.c ****   uint32_t deviceserial1;
+ 185              		.loc 1 341 3 view .LVU41
+ 342:Src/usbd_desc.c ****   uint32_t deviceserial2;
+ 186              		.loc 1 342 3 view .LVU42
+ 343:Src/usbd_desc.c **** 
+ 187              		.loc 1 343 3 view .LVU43
+ 345:Src/usbd_desc.c ****   deviceserial1 = *(uint32_t *) DEVICE_ID2;
+ 188              		.loc 1 345 3 view .LVU44
+ 345:Src/usbd_desc.c ****   deviceserial1 = *(uint32_t *) DEVICE_ID2;
+ 189              		.loc 1 345 17 is_stmt 0 view .LVU45
+ 190 0002 0B4B     		ldr	r3, .L21
+ 191 0004 D3F89005 		ldr	r0, [r3, #1424]
+ 192              	.LVL9:
+ 346:Src/usbd_desc.c ****   deviceserial2 = *(uint32_t *) DEVICE_ID3;
+ 193              		.loc 1 346 3 is_stmt 1 view .LVU46
+ 346:Src/usbd_desc.c ****   deviceserial2 = *(uint32_t *) DEVICE_ID3;
+ 194              		.loc 1 346 17 is_stmt 0 view .LVU47
+ 195 0008 D3F89445 		ldr	r4, [r3, #1428]
+ 196              	.LVL10:
+ 347:Src/usbd_desc.c **** 
+ 197              		.loc 1 347 3 is_stmt 1 view .LVU48
+ 347:Src/usbd_desc.c **** 
+ 198              		.loc 1 347 17 is_stmt 0 view .LVU49
+ 199 000c D3F89835 		ldr	r3, [r3, #1432]
+ 200              	.LVL11:
+ 349:Src/usbd_desc.c **** 
+ 201              		.loc 1 349 3 is_stmt 1 view .LVU50
+ 351:Src/usbd_desc.c ****   {
+ 202              		.loc 1 351 3 view .LVU51
+ 351:Src/usbd_desc.c ****   {
+ 203              		.loc 1 351 6 is_stmt 0 view .LVU52
+ 204 0010 C018     		adds	r0, r0, r3
+ 205              	.LVL12:
+ 351:Src/usbd_desc.c ****   {
+ 206              		.loc 1 351 6 view .LVU53
+ 207 0012 00D1     		bne	.L20
+ 208              	.LVL13:
+ 209              	.L17:
+ 356:Src/usbd_desc.c **** 
+ 210              		.loc 1 356 1 view .LVU54
+ 211 0014 38BD     		pop	{r3, r4, r5, pc}
+ 212              	.LVL14:
+ 213              	.L20:
+ 353:Src/usbd_desc.c ****     IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
+ 214              		.loc 1 353 5 is_stmt 1 view .LVU55
+ 215 0016 074D     		ldr	r5, .L21+4
+ 216 0018 0822     		movs	r2, #8
+ 217 001a 2946     		mov	r1, r5
+ 218 001c FFF7FEFF 		bl	IntToUnicode
+ 219              	.LVL15:
+ 354:Src/usbd_desc.c ****   }
+ 220              		.loc 1 354 5 view .LVU56
+ 221 0020 0422     		movs	r2, #4
+ 222 0022 05F11001 		add	r1, r5, #16
+ 223 0026 2046     		mov	r0, r4
+ARM GAS  /tmp/ccDO9gP0.s 			page 12
+
+
+ 224 0028 FFF7FEFF 		bl	IntToUnicode
+ 225              	.LVL16:
+ 356:Src/usbd_desc.c **** 
+ 226              		.loc 1 356 1 is_stmt 0 view .LVU57
+ 227 002c F2E7     		b	.L17
+ 228              	.L22:
+ 229 002e 00BF     		.align	2
+ 230              	.L21:
+ 231 0030 0070FF1F 		.word	536834048
+ 232 0034 02000000 		.word	USBD_StringSerial+2
+ 233              		.cfi_endproc
+ 234              	.LFE340:
+ 236              		.section	.text.USBD_AUDIO_SerialStrDescriptor,"ax",%progbits
+ 237              		.align	1
+ 238              		.global	USBD_AUDIO_SerialStrDescriptor
+ 239              		.syntax unified
+ 240              		.thumb
+ 241              		.thumb_func
+ 243              	USBD_AUDIO_SerialStrDescriptor:
+ 244              	.LVL17:
+ 245              	.LFB337:
+ 281:Src/usbd_desc.c ****   UNUSED(speed);
+ 246              		.loc 1 281 1 is_stmt 1 view -0
+ 247              		.cfi_startproc
+ 248              		@ args = 0, pretend = 0, frame = 0
+ 249              		@ frame_needed = 0, uses_anonymous_args = 0
+ 281:Src/usbd_desc.c ****   UNUSED(speed);
+ 250              		.loc 1 281 1 is_stmt 0 view .LVU59
+ 251 0000 08B5     		push	{r3, lr}
+ 252              	.LCFI3:
+ 253              		.cfi_def_cfa_offset 8
+ 254              		.cfi_offset 3, -8
+ 255              		.cfi_offset 14, -4
+ 282:Src/usbd_desc.c ****   *length = USB_SIZ_STRING_SERIAL;
+ 256              		.loc 1 282 3 is_stmt 1 view .LVU60
+ 283:Src/usbd_desc.c **** 
+ 257              		.loc 1 283 3 view .LVU61
+ 283:Src/usbd_desc.c **** 
+ 258              		.loc 1 283 11 is_stmt 0 view .LVU62
+ 259 0002 1A23     		movs	r3, #26
+ 260 0004 0B80     		strh	r3, [r1]	@ movhi
+ 287:Src/usbd_desc.c **** 
+ 261              		.loc 1 287 3 is_stmt 1 view .LVU63
+ 262 0006 FFF7FEFF 		bl	Get_SerialNum
+ 263              	.LVL18:
+ 293:Src/usbd_desc.c **** }
+ 264              		.loc 1 293 3 view .LVU64
+ 294:Src/usbd_desc.c **** 
+ 265              		.loc 1 294 1 is_stmt 0 view .LVU65
+ 266 000a 0148     		ldr	r0, .L25
+ 267 000c 08BD     		pop	{r3, pc}
+ 268              	.L26:
+ 269 000e 00BF     		.align	2
+ 270              	.L25:
+ 271 0010 00000000 		.word	USBD_StringSerial
+ 272              		.cfi_endproc
+ 273              	.LFE337:
+ARM GAS  /tmp/ccDO9gP0.s 			page 13
+
+
+ 275              		.section	.rodata.USBD_AUDIO_ProductStrDescriptor.str1.4,"aMS",%progbits,1
+ 276              		.align	2
+ 277              	.LC0:
+ 278 0000 53544D33 		.ascii	"STM32 Audio Class\000"
+ 278      32204175 
+ 278      64696F20 
+ 278      436C6173 
+ 278      7300
+ 279              		.section	.text.USBD_AUDIO_ProductStrDescriptor,"ax",%progbits
+ 280              		.align	1
+ 281              		.global	USBD_AUDIO_ProductStrDescriptor
+ 282              		.syntax unified
+ 283              		.thumb
+ 284              		.thumb_func
+ 286              	USBD_AUDIO_ProductStrDescriptor:
+ 287              	.LVL19:
+ 288              	.LFB335:
+ 249:Src/usbd_desc.c ****   if(speed == 0)
+ 289              		.loc 1 249 1 is_stmt 1 view -0
+ 290              		.cfi_startproc
+ 291              		@ args = 0, pretend = 0, frame = 0
+ 292              		@ frame_needed = 0, uses_anonymous_args = 0
+ 249:Src/usbd_desc.c ****   if(speed == 0)
+ 293              		.loc 1 249 1 is_stmt 0 view .LVU67
+ 294 0000 08B5     		push	{r3, lr}
+ 295              	.LCFI4:
+ 296              		.cfi_def_cfa_offset 8
+ 297              		.cfi_offset 3, -8
+ 298              		.cfi_offset 14, -4
+ 299 0002 0A46     		mov	r2, r1
+ 250:Src/usbd_desc.c ****   {
+ 300              		.loc 1 250 3 is_stmt 1 view .LVU68
+ 250:Src/usbd_desc.c ****   {
+ 301              		.loc 1 250 5 is_stmt 0 view .LVU69
+ 302 0004 28B9     		cbnz	r0, .L28
+ 252:Src/usbd_desc.c ****   }
+ 303              		.loc 1 252 5 is_stmt 1 view .LVU70
+ 304 0006 0549     		ldr	r1, .L31
+ 305              	.LVL20:
+ 252:Src/usbd_desc.c ****   }
+ 306              		.loc 1 252 5 is_stmt 0 view .LVU71
+ 307 0008 0548     		ldr	r0, .L31+4
+ 308              	.LVL21:
+ 252:Src/usbd_desc.c ****   }
+ 309              		.loc 1 252 5 view .LVU72
+ 310 000a FFF7FEFF 		bl	USBD_GetString
+ 311              	.LVL22:
+ 312              	.L29:
+ 258:Src/usbd_desc.c **** }
+ 313              		.loc 1 258 3 is_stmt 1 view .LVU73
+ 259:Src/usbd_desc.c **** 
+ 314              		.loc 1 259 1 is_stmt 0 view .LVU74
+ 315 000e 0348     		ldr	r0, .L31
+ 316 0010 08BD     		pop	{r3, pc}
+ 317              	.LVL23:
+ 318              	.L28:
+ 256:Src/usbd_desc.c ****   }
+ARM GAS  /tmp/ccDO9gP0.s 			page 14
+
+
+ 319              		.loc 1 256 5 is_stmt 1 view .LVU75
+ 320 0012 0249     		ldr	r1, .L31
+ 321              	.LVL24:
+ 256:Src/usbd_desc.c ****   }
+ 322              		.loc 1 256 5 is_stmt 0 view .LVU76
+ 323 0014 0248     		ldr	r0, .L31+4
+ 324              	.LVL25:
+ 256:Src/usbd_desc.c ****   }
+ 325              		.loc 1 256 5 view .LVU77
+ 326 0016 FFF7FEFF 		bl	USBD_GetString
+ 327              	.LVL26:
+ 256:Src/usbd_desc.c ****   }
+ 328              		.loc 1 256 5 view .LVU78
+ 329 001a F8E7     		b	.L29
+ 330              	.L32:
+ 331              		.align	2
+ 332              	.L31:
+ 333 001c 00000000 		.word	USBD_StrDesc
+ 334 0020 00000000 		.word	.LC0
+ 335              		.cfi_endproc
+ 336              	.LFE335:
+ 338              		.section	.rodata.USBD_AUDIO_ManufacturerStrDescriptor.str1.4,"aMS",%progbits,1
+ 339              		.align	2
+ 340              	.LC1:
+ 341 0000 53544D69 		.ascii	"STMicroelectronics\000"
+ 341      63726F65 
+ 341      6C656374 
+ 341      726F6E69 
+ 341      637300
+ 342              		.section	.text.USBD_AUDIO_ManufacturerStrDescriptor,"ax",%progbits
+ 343              		.align	1
+ 344              		.global	USBD_AUDIO_ManufacturerStrDescriptor
+ 345              		.syntax unified
+ 346              		.thumb
+ 347              		.thumb_func
+ 349              	USBD_AUDIO_ManufacturerStrDescriptor:
+ 350              	.LVL27:
+ 351              	.LFB336:
+ 268:Src/usbd_desc.c ****   UNUSED(speed);
+ 352              		.loc 1 268 1 is_stmt 1 view -0
+ 353              		.cfi_startproc
+ 354              		@ args = 0, pretend = 0, frame = 0
+ 355              		@ frame_needed = 0, uses_anonymous_args = 0
+ 268:Src/usbd_desc.c ****   UNUSED(speed);
+ 356              		.loc 1 268 1 is_stmt 0 view .LVU80
+ 357 0000 10B5     		push	{r4, lr}
+ 358              	.LCFI5:
+ 359              		.cfi_def_cfa_offset 8
+ 360              		.cfi_offset 4, -8
+ 361              		.cfi_offset 14, -4
+ 362 0002 0A46     		mov	r2, r1
+ 269:Src/usbd_desc.c ****   USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
+ 363              		.loc 1 269 3 is_stmt 1 view .LVU81
+ 270:Src/usbd_desc.c ****   return USBD_StrDesc;
+ 364              		.loc 1 270 3 view .LVU82
+ 365 0004 034C     		ldr	r4, .L35
+ 366 0006 2146     		mov	r1, r4
+ARM GAS  /tmp/ccDO9gP0.s 			page 15
+
+
+ 367              	.LVL28:
+ 270:Src/usbd_desc.c ****   return USBD_StrDesc;
+ 368              		.loc 1 270 3 is_stmt 0 view .LVU83
+ 369 0008 0348     		ldr	r0, .L35+4
+ 370              	.LVL29:
+ 270:Src/usbd_desc.c ****   return USBD_StrDesc;
+ 371              		.loc 1 270 3 view .LVU84
+ 372 000a FFF7FEFF 		bl	USBD_GetString
+ 373              	.LVL30:
+ 271:Src/usbd_desc.c **** }
+ 374              		.loc 1 271 3 is_stmt 1 view .LVU85
+ 272:Src/usbd_desc.c **** 
+ 375              		.loc 1 272 1 is_stmt 0 view .LVU86
+ 376 000e 2046     		mov	r0, r4
+ 377 0010 10BD     		pop	{r4, pc}
+ 378              	.L36:
+ 379 0012 00BF     		.align	2
+ 380              	.L35:
+ 381 0014 00000000 		.word	USBD_StrDesc
+ 382 0018 00000000 		.word	.LC1
+ 383              		.cfi_endproc
+ 384              	.LFE336:
+ 386              		.section	.rodata.USBD_AUDIO_ConfigStrDescriptor.str1.4,"aMS",%progbits,1
+ 387              		.align	2
+ 388              	.LC2:
+ 389 0000 41554449 		.ascii	"AUDIO Config\000"
+ 389      4F20436F 
+ 389      6E666967 
+ 389      00
+ 390              		.section	.text.USBD_AUDIO_ConfigStrDescriptor,"ax",%progbits
+ 391              		.align	1
+ 392              		.global	USBD_AUDIO_ConfigStrDescriptor
+ 393              		.syntax unified
+ 394              		.thumb
+ 395              		.thumb_func
+ 397              	USBD_AUDIO_ConfigStrDescriptor:
+ 398              	.LVL31:
+ 399              	.LFB338:
+ 303:Src/usbd_desc.c ****   if(speed == USBD_SPEED_HIGH)
+ 400              		.loc 1 303 1 is_stmt 1 view -0
+ 401              		.cfi_startproc
+ 402              		@ args = 0, pretend = 0, frame = 0
+ 403              		@ frame_needed = 0, uses_anonymous_args = 0
+ 303:Src/usbd_desc.c ****   if(speed == USBD_SPEED_HIGH)
+ 404              		.loc 1 303 1 is_stmt 0 view .LVU88
+ 405 0000 08B5     		push	{r3, lr}
+ 406              	.LCFI6:
+ 407              		.cfi_def_cfa_offset 8
+ 408              		.cfi_offset 3, -8
+ 409              		.cfi_offset 14, -4
+ 410 0002 0A46     		mov	r2, r1
+ 304:Src/usbd_desc.c ****   {
+ 411              		.loc 1 304 3 is_stmt 1 view .LVU89
+ 304:Src/usbd_desc.c ****   {
+ 412              		.loc 1 304 5 is_stmt 0 view .LVU90
+ 413 0004 28B9     		cbnz	r0, .L38
+ 306:Src/usbd_desc.c ****   }
+ARM GAS  /tmp/ccDO9gP0.s 			page 16
+
+
+ 414              		.loc 1 306 5 is_stmt 1 view .LVU91
+ 415 0006 0549     		ldr	r1, .L41
+ 416              	.LVL32:
+ 306:Src/usbd_desc.c ****   }
+ 417              		.loc 1 306 5 is_stmt 0 view .LVU92
+ 418 0008 0548     		ldr	r0, .L41+4
+ 419              	.LVL33:
+ 306:Src/usbd_desc.c ****   }
+ 420              		.loc 1 306 5 view .LVU93
+ 421 000a FFF7FEFF 		bl	USBD_GetString
+ 422              	.LVL34:
+ 423              	.L39:
+ 312:Src/usbd_desc.c **** }
+ 424              		.loc 1 312 3 is_stmt 1 view .LVU94
+ 313:Src/usbd_desc.c **** 
+ 425              		.loc 1 313 1 is_stmt 0 view .LVU95
+ 426 000e 0348     		ldr	r0, .L41
+ 427 0010 08BD     		pop	{r3, pc}
+ 428              	.LVL35:
+ 429              	.L38:
+ 310:Src/usbd_desc.c ****   }
+ 430              		.loc 1 310 5 is_stmt 1 view .LVU96
+ 431 0012 0249     		ldr	r1, .L41
+ 432              	.LVL36:
+ 310:Src/usbd_desc.c ****   }
+ 433              		.loc 1 310 5 is_stmt 0 view .LVU97
+ 434 0014 0248     		ldr	r0, .L41+4
+ 435              	.LVL37:
+ 310:Src/usbd_desc.c ****   }
+ 436              		.loc 1 310 5 view .LVU98
+ 437 0016 FFF7FEFF 		bl	USBD_GetString
+ 438              	.LVL38:
+ 310:Src/usbd_desc.c ****   }
+ 439              		.loc 1 310 5 view .LVU99
+ 440 001a F8E7     		b	.L39
+ 441              	.L42:
+ 442              		.align	2
+ 443              	.L41:
+ 444 001c 00000000 		.word	USBD_StrDesc
+ 445 0020 00000000 		.word	.LC2
+ 446              		.cfi_endproc
+ 447              	.LFE338:
+ 449              		.section	.rodata.USBD_AUDIO_InterfaceStrDescriptor.str1.4,"aMS",%progbits,1
+ 450              		.align	2
+ 451              	.LC3:
+ 452 0000 41554449 		.ascii	"AUDIO Interface\000"
+ 452      4F20496E 
+ 452      74657266 
+ 452      61636500 
+ 453              		.section	.text.USBD_AUDIO_InterfaceStrDescriptor,"ax",%progbits
+ 454              		.align	1
+ 455              		.global	USBD_AUDIO_InterfaceStrDescriptor
+ 456              		.syntax unified
+ 457              		.thumb
+ 458              		.thumb_func
+ 460              	USBD_AUDIO_InterfaceStrDescriptor:
+ 461              	.LVL39:
+ARM GAS  /tmp/ccDO9gP0.s 			page 17
+
+
+ 462              	.LFB339:
+ 322:Src/usbd_desc.c ****   if(speed == 0)
+ 463              		.loc 1 322 1 is_stmt 1 view -0
+ 464              		.cfi_startproc
+ 465              		@ args = 0, pretend = 0, frame = 0
+ 466              		@ frame_needed = 0, uses_anonymous_args = 0
+ 322:Src/usbd_desc.c ****   if(speed == 0)
+ 467              		.loc 1 322 1 is_stmt 0 view .LVU101
+ 468 0000 08B5     		push	{r3, lr}
+ 469              	.LCFI7:
+ 470              		.cfi_def_cfa_offset 8
+ 471              		.cfi_offset 3, -8
+ 472              		.cfi_offset 14, -4
+ 473 0002 0A46     		mov	r2, r1
+ 323:Src/usbd_desc.c ****   {
+ 474              		.loc 1 323 3 is_stmt 1 view .LVU102
+ 323:Src/usbd_desc.c ****   {
+ 475              		.loc 1 323 5 is_stmt 0 view .LVU103
+ 476 0004 28B9     		cbnz	r0, .L44
+ 325:Src/usbd_desc.c ****   }
+ 477              		.loc 1 325 5 is_stmt 1 view .LVU104
+ 478 0006 0549     		ldr	r1, .L47
+ 479              	.LVL40:
+ 325:Src/usbd_desc.c ****   }
+ 480              		.loc 1 325 5 is_stmt 0 view .LVU105
+ 481 0008 0548     		ldr	r0, .L47+4
+ 482              	.LVL41:
+ 325:Src/usbd_desc.c ****   }
+ 483              		.loc 1 325 5 view .LVU106
+ 484 000a FFF7FEFF 		bl	USBD_GetString
+ 485              	.LVL42:
+ 486              	.L45:
+ 331:Src/usbd_desc.c **** }
+ 487              		.loc 1 331 3 is_stmt 1 view .LVU107
+ 332:Src/usbd_desc.c **** 
+ 488              		.loc 1 332 1 is_stmt 0 view .LVU108
+ 489 000e 0348     		ldr	r0, .L47
+ 490 0010 08BD     		pop	{r3, pc}
+ 491              	.LVL43:
+ 492              	.L44:
+ 329:Src/usbd_desc.c ****   }
+ 493              		.loc 1 329 5 is_stmt 1 view .LVU109
+ 494 0012 0249     		ldr	r1, .L47
+ 495              	.LVL44:
+ 329:Src/usbd_desc.c ****   }
+ 496              		.loc 1 329 5 is_stmt 0 view .LVU110
+ 497 0014 0248     		ldr	r0, .L47+4
+ 498              	.LVL45:
+ 329:Src/usbd_desc.c ****   }
+ 499              		.loc 1 329 5 view .LVU111
+ 500 0016 FFF7FEFF 		bl	USBD_GetString
+ 501              	.LVL46:
+ 329:Src/usbd_desc.c ****   }
+ 502              		.loc 1 329 5 view .LVU112
+ 503 001a F8E7     		b	.L45
+ 504              	.L48:
+ 505              		.align	2
+ARM GAS  /tmp/ccDO9gP0.s 			page 18
+
+
+ 506              	.L47:
+ 507 001c 00000000 		.word	USBD_StrDesc
+ 508 0020 00000000 		.word	.LC3
+ 509              		.cfi_endproc
+ 510              	.LFE339:
+ 512              		.global	USBD_StringSerial
+ 513              		.section	.data.USBD_StringSerial,"aw"
+ 514              		.align	2
+ 517              	USBD_StringSerial:
+ 518 0000 1A0300   		.ascii	"\032\003\000"
+ 519 0003 00000000 		.space	23
+ 519      00000000 
+ 519      00000000 
+ 519      00000000 
+ 519      00000000 
+ 520              		.global	USBD_StrDesc
+ 521              		.section	.bss.USBD_StrDesc,"aw",%nobits
+ 522              		.align	2
+ 525              	USBD_StrDesc:
+ 526 0000 00000000 		.space	512
+ 526      00000000 
+ 526      00000000 
+ 526      00000000 
+ 526      00000000 
+ 527              		.global	USBD_LangIDDesc
+ 528              		.section	.data.USBD_LangIDDesc,"aw"
+ 529              		.align	2
+ 532              	USBD_LangIDDesc:
+ 533 0000 04030904 		.ascii	"\004\003\011\004"
+ 534              		.global	USBD_AUDIO_DeviceDesc
+ 535              		.section	.data.USBD_AUDIO_DeviceDesc,"aw"
+ 536              		.align	2
+ 539              	USBD_AUDIO_DeviceDesc:
+ 540 0000 12010002 		.ascii	"\022\001\000\002\000\000\000@\203\004@W\000\002\001"
+ 540      00000040 
+ 540      83044057 
+ 540      000201
+ 541 000f 020301   		.ascii	"\002\003\001"
+ 542              		.global	AUDIO_Desc
+ 543              		.section	.data.AUDIO_Desc,"aw"
+ 544              		.align	2
+ 547              	AUDIO_Desc:
+ 548 0000 00000000 		.word	USBD_AUDIO_DeviceDescriptor
+ 549 0004 00000000 		.word	USBD_AUDIO_LangIDStrDescriptor
+ 550 0008 00000000 		.word	USBD_AUDIO_ManufacturerStrDescriptor
+ 551 000c 00000000 		.word	USBD_AUDIO_ProductStrDescriptor
+ 552 0010 00000000 		.word	USBD_AUDIO_SerialStrDescriptor
+ 553 0014 00000000 		.word	USBD_AUDIO_ConfigStrDescriptor
+ 554 0018 00000000 		.word	USBD_AUDIO_InterfaceStrDescriptor
+ 555 001c 00000000 		.space	4
+ 556              		.text
+ 557              	.Letext0:
+ 558              		.file 2 "/usr/include/newlib/machine/_default_types.h"
+ 559              		.file 3 "/usr/include/newlib/sys/_stdint.h"
+ 560              		.file 4 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h"
+ 561              		.file 5 "Inc/usbd_desc.h"
+ 562              		.file 6 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h"
+ARM GAS  /tmp/ccDO9gP0.s 			page 19
+
+
+ARM GAS  /tmp/ccDO9gP0.s 			page 20
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 usbd_desc.c
+     /tmp/ccDO9gP0.s:21     .text.USBD_AUDIO_DeviceDescriptor:00000000 $t
+     /tmp/ccDO9gP0.s:27     .text.USBD_AUDIO_DeviceDescriptor:00000000 USBD_AUDIO_DeviceDescriptor
+     /tmp/ccDO9gP0.s:49     .text.USBD_AUDIO_DeviceDescriptor:00000008 $d
+     /tmp/ccDO9gP0.s:539    .data.USBD_AUDIO_DeviceDesc:00000000 USBD_AUDIO_DeviceDesc
+     /tmp/ccDO9gP0.s:54     .text.USBD_AUDIO_LangIDStrDescriptor:00000000 $t
+     /tmp/ccDO9gP0.s:60     .text.USBD_AUDIO_LangIDStrDescriptor:00000000 USBD_AUDIO_LangIDStrDescriptor
+     /tmp/ccDO9gP0.s:82     .text.USBD_AUDIO_LangIDStrDescriptor:00000008 $d
+     /tmp/ccDO9gP0.s:532    .data.USBD_LangIDDesc:00000000 USBD_LangIDDesc
+     /tmp/ccDO9gP0.s:87     .text.IntToUnicode:00000000 $t
+     /tmp/ccDO9gP0.s:92     .text.IntToUnicode:00000000 IntToUnicode
+     /tmp/ccDO9gP0.s:167    .text.Get_SerialNum:00000000 $t
+     /tmp/ccDO9gP0.s:172    .text.Get_SerialNum:00000000 Get_SerialNum
+     /tmp/ccDO9gP0.s:231    .text.Get_SerialNum:00000030 $d
+     /tmp/ccDO9gP0.s:517    .data.USBD_StringSerial:00000000 USBD_StringSerial
+     /tmp/ccDO9gP0.s:237    .text.USBD_AUDIO_SerialStrDescriptor:00000000 $t
+     /tmp/ccDO9gP0.s:243    .text.USBD_AUDIO_SerialStrDescriptor:00000000 USBD_AUDIO_SerialStrDescriptor
+     /tmp/ccDO9gP0.s:271    .text.USBD_AUDIO_SerialStrDescriptor:00000010 $d
+     /tmp/ccDO9gP0.s:276    .rodata.USBD_AUDIO_ProductStrDescriptor.str1.4:00000000 $d
+     /tmp/ccDO9gP0.s:280    .text.USBD_AUDIO_ProductStrDescriptor:00000000 $t
+     /tmp/ccDO9gP0.s:286    .text.USBD_AUDIO_ProductStrDescriptor:00000000 USBD_AUDIO_ProductStrDescriptor
+     /tmp/ccDO9gP0.s:333    .text.USBD_AUDIO_ProductStrDescriptor:0000001c $d
+     /tmp/ccDO9gP0.s:525    .bss.USBD_StrDesc:00000000 USBD_StrDesc
+     /tmp/ccDO9gP0.s:339    .rodata.USBD_AUDIO_ManufacturerStrDescriptor.str1.4:00000000 $d
+     /tmp/ccDO9gP0.s:343    .text.USBD_AUDIO_ManufacturerStrDescriptor:00000000 $t
+     /tmp/ccDO9gP0.s:349    .text.USBD_AUDIO_ManufacturerStrDescriptor:00000000 USBD_AUDIO_ManufacturerStrDescriptor
+     /tmp/ccDO9gP0.s:381    .text.USBD_AUDIO_ManufacturerStrDescriptor:00000014 $d
+     /tmp/ccDO9gP0.s:387    .rodata.USBD_AUDIO_ConfigStrDescriptor.str1.4:00000000 $d
+     /tmp/ccDO9gP0.s:391    .text.USBD_AUDIO_ConfigStrDescriptor:00000000 $t
+     /tmp/ccDO9gP0.s:397    .text.USBD_AUDIO_ConfigStrDescriptor:00000000 USBD_AUDIO_ConfigStrDescriptor
+     /tmp/ccDO9gP0.s:444    .text.USBD_AUDIO_ConfigStrDescriptor:0000001c $d
+     /tmp/ccDO9gP0.s:450    .rodata.USBD_AUDIO_InterfaceStrDescriptor.str1.4:00000000 $d
+     /tmp/ccDO9gP0.s:454    .text.USBD_AUDIO_InterfaceStrDescriptor:00000000 $t
+     /tmp/ccDO9gP0.s:460    .text.USBD_AUDIO_InterfaceStrDescriptor:00000000 USBD_AUDIO_InterfaceStrDescriptor
+     /tmp/ccDO9gP0.s:507    .text.USBD_AUDIO_InterfaceStrDescriptor:0000001c $d
+     /tmp/ccDO9gP0.s:514    .data.USBD_StringSerial:00000000 $d
+     /tmp/ccDO9gP0.s:522    .bss.USBD_StrDesc:00000000 $d
+     /tmp/ccDO9gP0.s:529    .data.USBD_LangIDDesc:00000000 $d
+     /tmp/ccDO9gP0.s:536    .data.USBD_AUDIO_DeviceDesc:00000000 $d
+     /tmp/ccDO9gP0.s:547    .data.AUDIO_Desc:00000000 AUDIO_Desc
+     /tmp/ccDO9gP0.s:544    .data.AUDIO_Desc:00000000 $d
+
+UNDEFINED SYMBOLS
+USBD_GetString
diff --git a/squeow_sw/build/usbd_desc.o b/squeow_sw/build/usbd_desc.o
new file mode 100644
index 0000000000000000000000000000000000000000..e6dee593094562dac4355c9d0e2ea78eca8bf939
GIT binary patch
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HcmV?d00001

diff --git a/squeow_sw/build/usbd_ioreq.d b/squeow_sw/build/usbd_ioreq.d
new file mode 100644
index 0000000..efed58a
--- /dev/null
+++ b/squeow_sw/build/usbd_ioreq.d
@@ -0,0 +1,85 @@
+build/usbd_ioreq.o: \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \
+ Inc/usbd_conf.h Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \
+ Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \
+ Inc/stm32g4xx_hal_conf.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h \
+ Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \
+ Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
+Inc/usbd_conf.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h:
+Drivers/CMSIS/Include/core_cm4.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h:
+Inc/stm32g4xx_hal_conf.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h:
+Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h:
+Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h:
diff --git a/squeow_sw/build/usbd_ioreq.lst b/squeow_sw/build/usbd_ioreq.lst
new file mode 100644
index 0000000..d0bf3d7
--- /dev/null
+++ b/squeow_sw/build/usbd_ioreq.lst
@@ -0,0 +1,549 @@
+ARM GAS  /tmp/ccxQwdeR.s 			page 1
+
+
+   1              		.cpu cortex-m4
+   2              		.arch armv7e-m
+   3              		.fpu fpv4-sp-d16
+   4              		.eabi_attribute 27, 1
+   5              		.eabi_attribute 28, 1
+   6              		.eabi_attribute 20, 1
+   7              		.eabi_attribute 21, 1
+   8              		.eabi_attribute 23, 3
+   9              		.eabi_attribute 24, 1
+  10              		.eabi_attribute 25, 1
+  11              		.eabi_attribute 26, 1
+  12              		.eabi_attribute 30, 1
+  13              		.eabi_attribute 34, 1
+  14              		.eabi_attribute 18, 4
+  15              		.file	"usbd_ioreq.c"
+  16              		.text
+  17              	.Ltext0:
+  18              		.cfi_sections	.debug_frame
+  19              		.file 1 "Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c"
+  20              		.section	.text.USBD_CtlSendData,"ax",%progbits
+  21              		.align	1
+  22              		.global	USBD_CtlSendData
+  23              		.syntax unified
+  24              		.thumb
+  25              		.thumb_func
+  27              	USBD_CtlSendData:
+  28              	.LVL0:
+  29              	.LFB333:
+   1:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+   2:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   ******************************************************************************
+   3:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @file    usbd_ioreq.c
+   4:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @author  MCD Application Team
+   5:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @brief   This file provides the IO requests APIs for control endpoints.
+   6:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   ******************************************************************************
+   7:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @attention
+   8:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   *
+   9:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  10:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * All rights reserved.</center></h2>
+  11:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   *
+  12:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * This software component is licensed by ST under Ultimate Liberty license
+  13:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * SLA0044, the "License"; You may not use this file except in compliance with
+  14:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * the License. You may obtain a copy of the License at:
+  15:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   *                      www.st.com/SLA0044
+  16:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   *
+  17:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   ******************************************************************************
+  18:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  19:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  20:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /* Includes ------------------------------------------------------------------*/
+  21:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** #include "usbd_ioreq.h"
+  22:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  23:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @addtogroup STM32_USB_DEVICE_LIBRARY
+  24:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @{
+  25:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  26:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  27:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  28:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ
+  29:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @brief control I/O requests module
+ARM GAS  /tmp/ccxQwdeR.s 			page 2
+
+
+  30:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @{
+  31:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  32:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  33:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ_Private_TypesDefinitions
+  34:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @{
+  35:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  36:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+  37:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @}
+  38:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  39:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  40:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  41:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ_Private_Defines
+  42:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @{
+  43:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  44:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  45:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+  46:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @}
+  47:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  48:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  49:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  50:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ_Private_Macros
+  51:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @{
+  52:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  53:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+  54:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @}
+  55:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  56:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  57:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  58:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ_Private_Variables
+  59:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @{
+  60:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  61:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  62:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+  63:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @}
+  64:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  65:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  66:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  67:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ_Private_FunctionPrototypes
+  68:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @{
+  69:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  70:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+  71:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @}
+  72:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  73:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  74:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  75:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ_Private_Functions
+  76:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @{
+  77:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+  78:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  79:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+  80:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @brief  USBD_CtlSendData
+  81:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   *         send data on the ctl pipe
+  82:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  pdev: device instance
+  83:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  buff: pointer to data buffer
+  84:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  len: length of data to be sent
+  85:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @retval status
+  86:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+ARM GAS  /tmp/ccxQwdeR.s 			page 3
+
+
+  87:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
+  88:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****                                     uint8_t *pbuf, uint32_t len)
+  89:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** {
+  30              		.loc 1 89 1 view -0
+  31              		.cfi_startproc
+  32              		@ args = 0, pretend = 0, frame = 0
+  33              		@ frame_needed = 0, uses_anonymous_args = 0
+  34              		.loc 1 89 1 is_stmt 0 view .LVU1
+  35 0000 08B5     		push	{r3, lr}
+  36              	.LCFI0:
+  37              		.cfi_def_cfa_offset 8
+  38              		.cfi_offset 3, -8
+  39              		.cfi_offset 14, -4
+  40 0002 1346     		mov	r3, r2
+  90:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   /* Set EP0 State */
+  91:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   pdev->ep0_state = USBD_EP0_DATA_IN;
+  41              		.loc 1 91 3 is_stmt 1 view .LVU2
+  42              		.loc 1 91 19 is_stmt 0 view .LVU3
+  43 0004 0222     		movs	r2, #2
+  44              	.LVL1:
+  45              		.loc 1 91 19 view .LVU4
+  46 0006 C0F89422 		str	r2, [r0, #660]
+  92:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   pdev->ep_in[0].total_length = len;
+  47              		.loc 1 92 3 is_stmt 1 view .LVU5
+  48              		.loc 1 92 31 is_stmt 0 view .LVU6
+  49 000a 8361     		str	r3, [r0, #24]
+  93:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+  94:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** #ifdef USBD_AVOID_PACKET_SPLIT_MPS
+  95:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   pdev->ep_in[0].rem_length = 0U;
+  96:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** #else
+  97:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   pdev->ep_in[0].rem_length = len;
+  50              		.loc 1 97 3 is_stmt 1 view .LVU7
+  51              		.loc 1 97 29 is_stmt 0 view .LVU8
+  52 000c C361     		str	r3, [r0, #28]
+  98:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** #endif
+  99:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 100:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   /* Start the transfer */
+ 101:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
+  53              		.loc 1 101 3 is_stmt 1 view .LVU9
+  54              		.loc 1 101 9 is_stmt 0 view .LVU10
+  55 000e 0A46     		mov	r2, r1
+  56 0010 0021     		movs	r1, #0
+  57              	.LVL2:
+  58              		.loc 1 101 9 view .LVU11
+  59 0012 FFF7FEFF 		bl	USBD_LL_Transmit
+  60              	.LVL3:
+ 102:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 103:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   return USBD_OK;
+  61              		.loc 1 103 3 is_stmt 1 view .LVU12
+ 104:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** }
+  62              		.loc 1 104 1 is_stmt 0 view .LVU13
+  63 0016 0020     		movs	r0, #0
+  64 0018 08BD     		pop	{r3, pc}
+  65              		.cfi_endproc
+  66              	.LFE333:
+  68              		.section	.text.USBD_CtlContinueSendData,"ax",%progbits
+  69              		.align	1
+ARM GAS  /tmp/ccxQwdeR.s 			page 4
+
+
+  70              		.global	USBD_CtlContinueSendData
+  71              		.syntax unified
+  72              		.thumb
+  73              		.thumb_func
+  75              	USBD_CtlContinueSendData:
+  76              	.LVL4:
+  77              	.LFB334:
+ 105:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 106:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+ 107:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @brief  USBD_CtlContinueSendData
+ 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   *         continue sending data on the ctl pipe
+ 109:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  pdev: device instance
+ 110:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  buff: pointer to data buffer
+ 111:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  len: length of data to be sent
+ 112:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @retval status
+ 113:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+ 114:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
+ 115:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****                                             uint8_t *pbuf, uint32_t len)
+ 116:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** {
+  78              		.loc 1 116 1 is_stmt 1 view -0
+  79              		.cfi_startproc
+  80              		@ args = 0, pretend = 0, frame = 0
+  81              		@ frame_needed = 0, uses_anonymous_args = 0
+  82              		.loc 1 116 1 is_stmt 0 view .LVU15
+  83 0000 08B5     		push	{r3, lr}
+  84              	.LCFI1:
+  85              		.cfi_def_cfa_offset 8
+  86              		.cfi_offset 3, -8
+  87              		.cfi_offset 14, -4
+  88 0002 1346     		mov	r3, r2
+ 117:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   /* Start the next transfer */
+ 118:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
+  89              		.loc 1 118 3 is_stmt 1 view .LVU16
+  90              		.loc 1 118 9 is_stmt 0 view .LVU17
+  91 0004 0A46     		mov	r2, r1
+  92              	.LVL5:
+  93              		.loc 1 118 9 view .LVU18
+  94 0006 0021     		movs	r1, #0
+  95              	.LVL6:
+  96              		.loc 1 118 9 view .LVU19
+  97 0008 FFF7FEFF 		bl	USBD_LL_Transmit
+  98              	.LVL7:
+ 119:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 120:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   return USBD_OK;
+  99              		.loc 1 120 3 is_stmt 1 view .LVU20
+ 121:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** }
+ 100              		.loc 1 121 1 is_stmt 0 view .LVU21
+ 101 000c 0020     		movs	r0, #0
+ 102 000e 08BD     		pop	{r3, pc}
+ 103              		.cfi_endproc
+ 104              	.LFE334:
+ 106              		.section	.text.USBD_CtlPrepareRx,"ax",%progbits
+ 107              		.align	1
+ 108              		.global	USBD_CtlPrepareRx
+ 109              		.syntax unified
+ 110              		.thumb
+ 111              		.thumb_func
+ARM GAS  /tmp/ccxQwdeR.s 			page 5
+
+
+ 113              	USBD_CtlPrepareRx:
+ 114              	.LVL8:
+ 115              	.LFB335:
+ 122:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 123:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+ 124:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @brief  USBD_CtlPrepareRx
+ 125:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   *         receive data on the ctl pipe
+ 126:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  pdev: device instance
+ 127:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  buff: pointer to data buffer
+ 128:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  len: length of data to be received
+ 129:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @retval status
+ 130:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+ 131:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
+ 132:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****                                      uint8_t *pbuf, uint32_t len)
+ 133:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** {
+ 116              		.loc 1 133 1 is_stmt 1 view -0
+ 117              		.cfi_startproc
+ 118              		@ args = 0, pretend = 0, frame = 0
+ 119              		@ frame_needed = 0, uses_anonymous_args = 0
+ 120              		.loc 1 133 1 is_stmt 0 view .LVU23
+ 121 0000 08B5     		push	{r3, lr}
+ 122              	.LCFI2:
+ 123              		.cfi_def_cfa_offset 8
+ 124              		.cfi_offset 3, -8
+ 125              		.cfi_offset 14, -4
+ 126 0002 1346     		mov	r3, r2
+ 134:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   /* Set EP0 State */
+ 135:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   pdev->ep0_state = USBD_EP0_DATA_OUT;
+ 127              		.loc 1 135 3 is_stmt 1 view .LVU24
+ 128              		.loc 1 135 19 is_stmt 0 view .LVU25
+ 129 0004 0322     		movs	r2, #3
+ 130              	.LVL9:
+ 131              		.loc 1 135 19 view .LVU26
+ 132 0006 C0F89422 		str	r2, [r0, #660]
+ 136:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   pdev->ep_out[0].total_length = len;
+ 133              		.loc 1 136 3 is_stmt 1 view .LVU27
+ 134              		.loc 1 136 32 is_stmt 0 view .LVU28
+ 135 000a C0F85831 		str	r3, [r0, #344]
+ 137:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 138:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** #ifdef USBD_AVOID_PACKET_SPLIT_MPS
+ 139:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   pdev->ep_out[0].rem_length = 0U;
+ 140:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** #else
+ 141:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   pdev->ep_out[0].rem_length = len;
+ 136              		.loc 1 141 3 is_stmt 1 view .LVU29
+ 137              		.loc 1 141 30 is_stmt 0 view .LVU30
+ 138 000e C0F85C31 		str	r3, [r0, #348]
+ 142:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** #endif
+ 143:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 144:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   /* Start the transfer */
+ 145:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
+ 139              		.loc 1 145 3 is_stmt 1 view .LVU31
+ 140              		.loc 1 145 9 is_stmt 0 view .LVU32
+ 141 0012 0A46     		mov	r2, r1
+ 142 0014 0021     		movs	r1, #0
+ 143              	.LVL10:
+ 144              		.loc 1 145 9 view .LVU33
+ 145 0016 FFF7FEFF 		bl	USBD_LL_PrepareReceive
+ARM GAS  /tmp/ccxQwdeR.s 			page 6
+
+
+ 146              	.LVL11:
+ 146:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 147:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   return USBD_OK;
+ 147              		.loc 1 147 3 is_stmt 1 view .LVU34
+ 148:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** }
+ 148              		.loc 1 148 1 is_stmt 0 view .LVU35
+ 149 001a 0020     		movs	r0, #0
+ 150 001c 08BD     		pop	{r3, pc}
+ 151              		.cfi_endproc
+ 152              	.LFE335:
+ 154              		.section	.text.USBD_CtlContinueRx,"ax",%progbits
+ 155              		.align	1
+ 156              		.global	USBD_CtlContinueRx
+ 157              		.syntax unified
+ 158              		.thumb
+ 159              		.thumb_func
+ 161              	USBD_CtlContinueRx:
+ 162              	.LVL12:
+ 163              	.LFB336:
+ 149:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 150:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+ 151:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @brief  USBD_CtlContinueRx
+ 152:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   *         continue receive data on the ctl pipe
+ 153:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  pdev: device instance
+ 154:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  buff: pointer to data buffer
+ 155:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  len: length of data to be received
+ 156:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @retval status
+ 157:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+ 158:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
+ 159:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****                                       uint8_t *pbuf, uint32_t len)
+ 160:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** {
+ 164              		.loc 1 160 1 is_stmt 1 view -0
+ 165              		.cfi_startproc
+ 166              		@ args = 0, pretend = 0, frame = 0
+ 167              		@ frame_needed = 0, uses_anonymous_args = 0
+ 168              		.loc 1 160 1 is_stmt 0 view .LVU37
+ 169 0000 08B5     		push	{r3, lr}
+ 170              	.LCFI3:
+ 171              		.cfi_def_cfa_offset 8
+ 172              		.cfi_offset 3, -8
+ 173              		.cfi_offset 14, -4
+ 174 0002 1346     		mov	r3, r2
+ 161:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
+ 175              		.loc 1 161 3 is_stmt 1 view .LVU38
+ 176              		.loc 1 161 9 is_stmt 0 view .LVU39
+ 177 0004 0A46     		mov	r2, r1
+ 178              	.LVL13:
+ 179              		.loc 1 161 9 view .LVU40
+ 180 0006 0021     		movs	r1, #0
+ 181              	.LVL14:
+ 182              		.loc 1 161 9 view .LVU41
+ 183 0008 FFF7FEFF 		bl	USBD_LL_PrepareReceive
+ 184              	.LVL15:
+ 162:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 163:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   return USBD_OK;
+ 185              		.loc 1 163 3 is_stmt 1 view .LVU42
+ 164:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** }
+ARM GAS  /tmp/ccxQwdeR.s 			page 7
+
+
+ 186              		.loc 1 164 1 is_stmt 0 view .LVU43
+ 187 000c 0020     		movs	r0, #0
+ 188 000e 08BD     		pop	{r3, pc}
+ 189              		.cfi_endproc
+ 190              	.LFE336:
+ 192              		.section	.text.USBD_CtlSendStatus,"ax",%progbits
+ 193              		.align	1
+ 194              		.global	USBD_CtlSendStatus
+ 195              		.syntax unified
+ 196              		.thumb
+ 197              		.thumb_func
+ 199              	USBD_CtlSendStatus:
+ 200              	.LVL16:
+ 201              	.LFB337:
+ 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 166:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+ 167:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @brief  USBD_CtlSendStatus
+ 168:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   *         send zero lzngth packet on the ctl pipe
+ 169:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  pdev: device instance
+ 170:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @retval status
+ 171:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+ 172:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
+ 173:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** {
+ 202              		.loc 1 173 1 is_stmt 1 view -0
+ 203              		.cfi_startproc
+ 204              		@ args = 0, pretend = 0, frame = 0
+ 205              		@ frame_needed = 0, uses_anonymous_args = 0
+ 206              		.loc 1 173 1 is_stmt 0 view .LVU45
+ 207 0000 08B5     		push	{r3, lr}
+ 208              	.LCFI4:
+ 209              		.cfi_def_cfa_offset 8
+ 210              		.cfi_offset 3, -8
+ 211              		.cfi_offset 14, -4
+ 174:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   /* Set EP0 State */
+ 175:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   pdev->ep0_state = USBD_EP0_STATUS_IN;
+ 212              		.loc 1 175 3 is_stmt 1 view .LVU46
+ 213              		.loc 1 175 19 is_stmt 0 view .LVU47
+ 214 0002 0422     		movs	r2, #4
+ 215 0004 C0F89422 		str	r2, [r0, #660]
+ 176:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 177:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   /* Start the transfer */
+ 178:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
+ 216              		.loc 1 178 3 is_stmt 1 view .LVU48
+ 217              		.loc 1 178 9 is_stmt 0 view .LVU49
+ 218 0008 0023     		movs	r3, #0
+ 219 000a 1A46     		mov	r2, r3
+ 220 000c 1946     		mov	r1, r3
+ 221 000e FFF7FEFF 		bl	USBD_LL_Transmit
+ 222              	.LVL17:
+ 179:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   return USBD_OK;
+ 223              		.loc 1 180 3 is_stmt 1 view .LVU50
+ 181:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** }
+ 224              		.loc 1 181 1 is_stmt 0 view .LVU51
+ 225 0012 0020     		movs	r0, #0
+ 226 0014 08BD     		pop	{r3, pc}
+ 227              		.cfi_endproc
+ARM GAS  /tmp/ccxQwdeR.s 			page 8
+
+
+ 228              	.LFE337:
+ 230              		.section	.text.USBD_CtlReceiveStatus,"ax",%progbits
+ 231              		.align	1
+ 232              		.global	USBD_CtlReceiveStatus
+ 233              		.syntax unified
+ 234              		.thumb
+ 235              		.thumb_func
+ 237              	USBD_CtlReceiveStatus:
+ 238              	.LVL18:
+ 239              	.LFB338:
+ 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 183:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+ 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @brief  USBD_CtlReceiveStatus
+ 185:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   *         receive zero lzngth packet on the ctl pipe
+ 186:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  pdev: device instance
+ 187:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @retval status
+ 188:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+ 189:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
+ 190:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** {
+ 240              		.loc 1 190 1 is_stmt 1 view -0
+ 241              		.cfi_startproc
+ 242              		@ args = 0, pretend = 0, frame = 0
+ 243              		@ frame_needed = 0, uses_anonymous_args = 0
+ 244              		.loc 1 190 1 is_stmt 0 view .LVU53
+ 245 0000 08B5     		push	{r3, lr}
+ 246              	.LCFI5:
+ 247              		.cfi_def_cfa_offset 8
+ 248              		.cfi_offset 3, -8
+ 249              		.cfi_offset 14, -4
+ 191:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   /* Set EP0 State */
+ 192:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   pdev->ep0_state = USBD_EP0_STATUS_OUT;
+ 250              		.loc 1 192 3 is_stmt 1 view .LVU54
+ 251              		.loc 1 192 19 is_stmt 0 view .LVU55
+ 252 0002 0522     		movs	r2, #5
+ 253 0004 C0F89422 		str	r2, [r0, #660]
+ 193:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 194:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   /* Start the transfer */
+ 195:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
+ 254              		.loc 1 195 3 is_stmt 1 view .LVU56
+ 255              		.loc 1 195 9 is_stmt 0 view .LVU57
+ 256 0008 0023     		movs	r3, #0
+ 257 000a 1A46     		mov	r2, r3
+ 258 000c 1946     		mov	r1, r3
+ 259 000e FFF7FEFF 		bl	USBD_LL_PrepareReceive
+ 260              	.LVL19:
+ 196:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 197:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   return USBD_OK;
+ 261              		.loc 1 197 3 is_stmt 1 view .LVU58
+ 198:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** }
+ 262              		.loc 1 198 1 is_stmt 0 view .LVU59
+ 263 0012 0020     		movs	r0, #0
+ 264 0014 08BD     		pop	{r3, pc}
+ 265              		.cfi_endproc
+ 266              	.LFE338:
+ 268              		.section	.text.USBD_GetRxCount,"ax",%progbits
+ 269              		.align	1
+ 270              		.global	USBD_GetRxCount
+ARM GAS  /tmp/ccxQwdeR.s 			page 9
+
+
+ 271              		.syntax unified
+ 272              		.thumb
+ 273              		.thumb_func
+ 275              	USBD_GetRxCount:
+ 276              	.LVL20:
+ 277              	.LFB339:
+ 199:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** 
+ 200:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /**
+ 201:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @brief  USBD_GetRxCount
+ 202:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   *         returns the received data length
+ 203:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  pdev: device instance
+ 204:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @param  ep_addr: endpoint address
+ 205:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   * @retval Rx Data blength
+ 206:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   */
+ 207:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+ 208:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** {
+ 278              		.loc 1 208 1 is_stmt 1 view -0
+ 279              		.cfi_startproc
+ 280              		@ args = 0, pretend = 0, frame = 0
+ 281              		@ frame_needed = 0, uses_anonymous_args = 0
+ 282              		.loc 1 208 1 is_stmt 0 view .LVU61
+ 283 0000 08B5     		push	{r3, lr}
+ 284              	.LCFI6:
+ 285              		.cfi_def_cfa_offset 8
+ 286              		.cfi_offset 3, -8
+ 287              		.cfi_offset 14, -4
+ 209:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c ****   return USBD_LL_GetRxDataSize(pdev, ep_addr);
+ 288              		.loc 1 209 3 is_stmt 1 view .LVU62
+ 289              		.loc 1 209 10 is_stmt 0 view .LVU63
+ 290 0002 FFF7FEFF 		bl	USBD_LL_GetRxDataSize
+ 291              	.LVL21:
+ 210:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** }
+ 292              		.loc 1 210 1 view .LVU64
+ 293 0006 08BD     		pop	{r3, pc}
+ 294              		.cfi_endproc
+ 295              	.LFE339:
+ 297              		.text
+ 298              	.Letext0:
+ 299              		.file 2 "/usr/include/newlib/machine/_default_types.h"
+ 300              		.file 3 "/usr/include/newlib/sys/_stdint.h"
+ 301              		.file 4 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h"
+ 302              		.file 5 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h"
+ARM GAS  /tmp/ccxQwdeR.s 			page 10
+
+
+DEFINED SYMBOLS
+                            *ABS*:00000000 usbd_ioreq.c
+     /tmp/ccxQwdeR.s:21     .text.USBD_CtlSendData:00000000 $t
+     /tmp/ccxQwdeR.s:27     .text.USBD_CtlSendData:00000000 USBD_CtlSendData
+     /tmp/ccxQwdeR.s:69     .text.USBD_CtlContinueSendData:00000000 $t
+     /tmp/ccxQwdeR.s:75     .text.USBD_CtlContinueSendData:00000000 USBD_CtlContinueSendData
+     /tmp/ccxQwdeR.s:107    .text.USBD_CtlPrepareRx:00000000 $t
+     /tmp/ccxQwdeR.s:113    .text.USBD_CtlPrepareRx:00000000 USBD_CtlPrepareRx
+     /tmp/ccxQwdeR.s:155    .text.USBD_CtlContinueRx:00000000 $t
+     /tmp/ccxQwdeR.s:161    .text.USBD_CtlContinueRx:00000000 USBD_CtlContinueRx
+     /tmp/ccxQwdeR.s:193    .text.USBD_CtlSendStatus:00000000 $t
+     /tmp/ccxQwdeR.s:199    .text.USBD_CtlSendStatus:00000000 USBD_CtlSendStatus
+     /tmp/ccxQwdeR.s:231    .text.USBD_CtlReceiveStatus:00000000 $t
+     /tmp/ccxQwdeR.s:237    .text.USBD_CtlReceiveStatus:00000000 USBD_CtlReceiveStatus
+     /tmp/ccxQwdeR.s:269    .text.USBD_GetRxCount:00000000 $t
+     /tmp/ccxQwdeR.s:275    .text.USBD_GetRxCount:00000000 USBD_GetRxCount
+
+UNDEFINED SYMBOLS
+USBD_LL_Transmit
+USBD_LL_PrepareReceive
+USBD_LL_GetRxDataSize
diff --git a/squeow_sw/build/usbd_ioreq.o b/squeow_sw/build/usbd_ioreq.o
new file mode 100644
index 0000000000000000000000000000000000000000..b3ede2c2f2bd1fc9599e0b0191b89cd82e714986
GIT binary patch
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HcmV?d00001

diff --git a/squeow_sw/squeow_codice.ioc b/squeow_sw/squeow_codice.ioc
new file mode 100644
index 0000000..e52badc
--- /dev/null
+++ b/squeow_sw/squeow_codice.ioc
@@ -0,0 +1,288 @@
+#MicroXplorer Configuration settings - do not modify
+ADC1.Channel-2\#ChannelRegularConversion=ADC_CHANNEL_15
+ADC1.CommonPathInternal=null|null|null|null
+ADC1.IPParameters=Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion,OffsetNumber-2\#ChannelRegularConversion,NbrOfConversionFlag,master,CommonPathInternal
+ADC1.NbrOfConversionFlag=1
+ADC1.OffsetNumber-2\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC1.Rank-2\#ChannelRegularConversion=1
+ADC1.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
+ADC1.master=1
+ADC2.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_3
+ADC2.Channel-4\#ChannelRegularConversion=ADC_CHANNEL_3
+ADC2.Channel-5\#ChannelRegularConversion=ADC_CHANNEL_3
+ADC2.Channel-6\#ChannelRegularConversion=ADC_CHANNEL_3
+ADC2.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV2
+ADC2.CommonPathInternal=null|null|null|null
+ADC2.EOCSelection=ADC_EOC_SEQ_CONV
+ADC2.IPParameters=Rank-3\#ChannelRegularConversion,ClockPrescaler,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,OffsetNumber-3\#ChannelRegularConversion,NbrOfConversionFlag,Rank-4\#ChannelRegularConversion,Channel-4\#ChannelRegularConversion,SamplingTime-4\#ChannelRegularConversion,OffsetNumber-4\#ChannelRegularConversion,Rank-5\#ChannelRegularConversion,Channel-5\#ChannelRegularConversion,SamplingTime-5\#ChannelRegularConversion,OffsetNumber-5\#ChannelRegularConversion,Rank-6\#ChannelRegularConversion,Channel-6\#ChannelRegularConversion,SamplingTime-6\#ChannelRegularConversion,OffsetNumber-6\#ChannelRegularConversion,NbrOfConversion,EOCSelection,CommonPathInternal
+ADC2.NbrOfConversion=4
+ADC2.NbrOfConversionFlag=1
+ADC2.OffsetNumber-3\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC2.OffsetNumber-4\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC2.OffsetNumber-5\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC2.OffsetNumber-6\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC2.Rank-3\#ChannelRegularConversion=1
+ADC2.Rank-4\#ChannelRegularConversion=2
+ADC2.Rank-5\#ChannelRegularConversion=3
+ADC2.Rank-6\#ChannelRegularConversion=4
+ADC2.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
+ADC2.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
+ADC2.SamplingTime-5\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
+ADC2.SamplingTime-6\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+I2C1.IPParameters=Timing
+I2C1.Timing=0x208080C1
+KeepUserPlacement=false
+Mcu.CPN=STM32G431KBT6
+Mcu.Family=STM32G4
+Mcu.IP0=ADC1
+Mcu.IP1=ADC2
+Mcu.IP10=USB_DEVICE
+Mcu.IP2=I2C1
+Mcu.IP3=NVIC
+Mcu.IP4=RCC
+Mcu.IP5=SYS
+Mcu.IP6=TIM2
+Mcu.IP7=TIM3
+Mcu.IP8=USART1
+Mcu.IP9=USB
+Mcu.IPNb=11
+Mcu.Name=STM32G431K(6-8-B)Tx
+Mcu.Package=LQFP32
+Mcu.Pin0=PF0-OSC_IN
+Mcu.Pin1=PF1-OSC_OUT
+Mcu.Pin10=PA7
+Mcu.Pin11=PB0
+Mcu.Pin12=PA9
+Mcu.Pin13=PA10
+Mcu.Pin14=PA11
+Mcu.Pin15=PA12
+Mcu.Pin16=PA13
+Mcu.Pin17=PA14
+Mcu.Pin18=PA15
+Mcu.Pin19=PB3
+Mcu.Pin2=PG10-NRST
+Mcu.Pin20=PB7
+Mcu.Pin21=PB8-BOOT0
+Mcu.Pin22=VP_SYS_VS_Systick
+Mcu.Pin23=VP_SYS_VS_DBSignals
+Mcu.Pin24=VP_TIM2_VS_ClockSourceINT
+Mcu.Pin25=VP_TIM3_VS_ClockSourceINT
+Mcu.Pin26=VP_USB_DEVICE_VS_USB_DEVICE_AUDIO_FS
+Mcu.Pin3=PA0
+Mcu.Pin4=PA1
+Mcu.Pin5=PA2
+Mcu.Pin6=PA3
+Mcu.Pin7=PA4
+Mcu.Pin8=PA5
+Mcu.Pin9=PA6
+Mcu.PinsNb=27
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32G431KBTx
+MxCube.Version=6.8.1
+MxDb.Version=DB.6.0.81
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false
+NVIC.TIM3_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
+NVIC.USB_LP_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PA0.Locked=true
+PA0.Signal=S_TIM2_CH1
+PA1.Locked=true
+PA1.Signal=S_TIM2_CH2
+PA10.Locked=true
+PA10.Mode=Asynchronous
+PA10.Signal=USART1_RX
+PA11.Mode=Device
+PA11.Signal=USB_DM
+PA12.Mode=Device
+PA12.Signal=USB_DP
+PA13.GPIOParameters=GPIO_Label
+PA13.GPIO_Label=T_SWDIO
+PA13.Locked=true
+PA13.Mode=Serial_Wire
+PA13.Signal=SYS_JTMS-SWDIO
+PA14.GPIOParameters=GPIO_Label
+PA14.GPIO_Label=T_SWCLK
+PA14.Locked=true
+PA14.Mode=Serial_Wire
+PA14.Signal=SYS_JTCK-SWCLK
+PA15.Locked=true
+PA15.Mode=I2C
+PA15.Signal=I2C1_SCL
+PA2.Locked=true
+PA2.Signal=S_TIM2_CH3
+PA3.Locked=true
+PA3.Signal=S_TIM2_CH4
+PA4.GPIOParameters=GPIO_Label
+PA4.GPIO_Label=TEMPERATURA
+PA4.Locked=true
+PA4.Mode=IN17-Single-Ended
+PA4.Signal=ADC2_IN17
+PA5.GPIOParameters=GPIO_Label
+PA5.GPIO_Label=CORRENTE
+PA5.Locked=true
+PA5.Mode=IN13-Single-Ended
+PA5.Signal=ADC2_IN13
+PA6.GPIOParameters=GPIO_Label
+PA6.GPIO_Label=DIRETTA
+PA6.Locked=true
+PA6.Mode=IN3-Single-Ended
+PA6.Signal=ADC2_IN3
+PA7.GPIOParameters=GPIO_Label
+PA7.GPIO_Label=RIFLESSA
+PA7.Locked=true
+PA7.Mode=IN4-Single-Ended
+PA7.Signal=ADC2_IN4
+PA9.Locked=true
+PA9.Mode=Asynchronous
+PA9.Signal=USART1_TX
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=AUDIO_IN
+PB0.Locked=true
+PB0.Mode=IN15-Single-Ended
+PB0.Signal=ADC1_IN15
+PB3.GPIOParameters=GPIO_Label
+PB3.GPIO_Label=T_SWO
+PB3.Locked=true
+PB3.Signal=SYS_JTDO-SWO
+PB7.Locked=true
+PB7.Mode=I2C
+PB7.Signal=I2C1_SDA
+PB8-BOOT0.Locked=true
+PF0-OSC_IN.Mode=HSE-External-Oscillator
+PF0-OSC_IN.Signal=RCC_OSC_IN
+PF1-OSC_OUT.Mode=HSE-External-Oscillator
+PF1-OSC_OUT.Signal=RCC_OSC_OUT
+PG10-NRST.Mode=Clock-out
+PG10-NRST.Signal=RCC_MCO
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32G431KBTx
+ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.5.1
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=squeow_codice.ioc
+ProjectManager.ProjectName=squeow_codice
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=Makefile
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_TIM2_Init-TIM2-false-HAL-true,4-MX_I2C1_Init-I2C1-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_ADC1_Init-ADC1-false-HAL-true,7-MX_ADC2_Init-ADC2-false-HAL-true,8-MX_USART1_UART_Init-USART1-false-HAL-true,9-MX_USB_Device_Init-USB_DEVICE-false-HAL-false
+RCC.ADC12Freq_Value=98304000
+RCC.AHBFreq_Value=98304000
+RCC.APB1Freq_Value=98304000
+RCC.APB1TimFreq_Value=98304000
+RCC.APB2Freq_Value=98304000
+RCC.APB2TimFreq_Value=98304000
+RCC.CK48CLockSelection=RCC_USBCLKSOURCE_HSI48
+RCC.CRSFreq_Value=48000000
+RCC.CortexFreq_Value=98304000
+RCC.EXTERNAL_CLOCK_VALUE=12288000
+RCC.FCLKCortexFreq_Value=98304000
+RCC.FDCANFreq_Value=98304000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=98304000
+RCC.HSE_VALUE=12288000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=98304000
+RCC.I2C2Freq_Value=98304000
+RCC.I2C3Freq_Value=98304000
+RCC.I2SFreq_Value=98304000
+RCC.IPParameters=ADC12Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CK48CLockSelection,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,PWRFreq_Value,RCC_MCO1Source,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=98304000
+RCC.LPUART1Freq_Value=98304000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=12288000
+RCC.PLLM=RCC_PLLM_DIV2
+RCC.PLLN=32
+RCC.PLLPoutputFreq_Value=98304000
+RCC.PLLQ=RCC_PLLQ_DIV4
+RCC.PLLQoutputFreq_Value=49152000
+RCC.PLLRCLKFreq_Value=98304000
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.PWRFreq_Value=98304000
+RCC.RCC_MCO1Source=RCC_MCO1SOURCE_HSE
+RCC.RNGFreq_Value=48000000
+RCC.SAI1Freq_Value=98304000
+RCC.SYSCLKFreq_VALUE=98304000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.UART4Freq_Value=170000000
+RCC.USART1Freq_Value=98304000
+RCC.USART2Freq_Value=98304000
+RCC.USART3Freq_Value=170000000
+RCC.USBFreq_Value=48000000
+RCC.VCOInputFreq_Value=6144000
+RCC.VCOOutputFreq_Value=196608000
+SH.S_TIM2_CH1.0=TIM2_CH1,PWM Generation1 CH1
+SH.S_TIM2_CH1.ConfNb=1
+SH.S_TIM2_CH2.0=TIM2_CH2,PWM Generation2 CH2
+SH.S_TIM2_CH2.ConfNb=1
+SH.S_TIM2_CH3.0=TIM2_CH3,PWM Generation3 CH3
+SH.S_TIM2_CH3.ConfNb=1
+SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4
+SH.S_TIM2_CH4.ConfNb=1
+TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
+TIM2.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
+TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
+TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
+TIM2.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4,PeriodNoDither,PulseNoDither_1,PulseNoDither_2,PulseNoDither_3,PulseNoDither_4
+TIM2.PeriodNoDither=2047
+TIM2.PulseNoDither_1=500
+TIM2.PulseNoDither_2=1000
+TIM2.PulseNoDither_3=1500
+TIM2.PulseNoDither_4=2000
+TIM3.IPParameters=PeriodNoDither,Prescaler
+TIM3.PeriodNoDither=199
+TIM3.Prescaler=49152
+USART1.IPParameters=VirtualMode-Asynchronous
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+USB_DEVICE.CLASS_NAME_FS=AUDIO
+USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS
+USB_DEVICE.VirtualMode=Audio
+USB_DEVICE.VirtualModeFS=Audio_FS
+VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals
+VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_TIM2_VS_ClockSourceINT.Mode=Internal
+VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
+VP_TIM3_VS_ClockSourceINT.Mode=Internal
+VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT
+VP_USB_DEVICE_VS_USB_DEVICE_AUDIO_FS.Mode=AUDIO_FS
+VP_USB_DEVICE_VS_USB_DEVICE_AUDIO_FS.Signal=USB_DEVICE_VS_USB_DEVICE_AUDIO_FS
+board=NUCLEO-G431KB
+boardIOC=true
diff --git a/squeow_sw/startup_stm32g431xx.s b/squeow_sw/startup_stm32g431xx.s
new file mode 100644
index 0000000..9ea4773
--- /dev/null
+++ b/squeow_sw/startup_stm32g431xx.s
@@ -0,0 +1,497 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32g431xx.s
+  * @author    MCD Application Team
+  * @brief     STM32G431xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+	bl	main
+
+LoopForever:
+    b LoopForever
+
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_PVM_IRQHandler
+	.word	RTC_TAMP_LSECSS_IRQHandler
+	.word	RTC_WKUP_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	0
+	.word	ADC1_2_IRQHandler
+	.word	USB_HP_IRQHandler
+	.word	USB_LP_IRQHandler
+	.word	FDCAN1_IT0_IRQHandler
+	.word	FDCAN1_IT1_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_TIM15_IRQHandler
+	.word	TIM1_UP_TIM16_IRQHandler
+	.word	TIM1_TRG_COM_TIM17_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTC_Alarm_IRQHandler
+	.word	USBWakeUp_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	0
+	.word	0
+	.word	LPTIM1_IRQHandler
+	.word	0
+	.word	SPI3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	0
+	.word	TIM6_DAC_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	0
+	.word	0
+	.word	UCPD1_IRQHandler
+	.word	COMP1_2_3_IRQHandler
+	.word	COMP4_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	CRS_IRQHandler
+	.word	SAI1_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	FPU_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	RNG_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	DMAMUX_OVR_IRQHandler
+	.word	0
+	.word	0
+	.word	DMA2_Channel6_IRQHandler
+	.word	0
+	.word	0
+	.word	CORDIC_IRQHandler
+	.word	FMAC_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+	.weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+	.weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+	.weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+	.weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_PVM_IRQHandler
+	.thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+	.weak	RTC_TAMP_LSECSS_IRQHandler
+	.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
+
+	.weak	RTC_WKUP_IRQHandler
+	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	USB_HP_IRQHandler
+	.thumb_set USB_HP_IRQHandler,Default_Handler
+
+	.weak	USB_LP_IRQHandler
+	.thumb_set USB_LP_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT0_IRQHandler
+	.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT1_IRQHandler
+	.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_TIM15_IRQHandler
+	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_TIM16_IRQHandler
+	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_TIM17_IRQHandler
+	.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTC_Alarm_IRQHandler
+	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+	.weak	USBWakeUp_IRQHandler
+	.thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	TIM6_DAC_IRQHandler
+	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	UCPD1_IRQHandler
+	.thumb_set UCPD1_IRQHandler,Default_Handler
+
+	.weak	COMP1_2_3_IRQHandler
+	.thumb_set COMP1_2_3_IRQHandler,Default_Handler
+
+	.weak	COMP4_IRQHandler
+	.thumb_set COMP4_IRQHandler,Default_Handler
+
+	.weak	CRS_IRQHandler
+	.thumb_set CRS_IRQHandler,Default_Handler
+
+	.weak	SAI1_IRQHandler
+	.thumb_set SAI1_IRQHandler,Default_Handler
+
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler
+
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+	.weak	DMAMUX_OVR_IRQHandler
+	.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel6_IRQHandler
+	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+	.weak	CORDIC_IRQHandler
+	.thumb_set CORDIC_IRQHandler,Default_Handler
+
+	.weak	FMAC_IRQHandler
+	.thumb_set FMAC_IRQHandler,Default_Handler
+